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456 lines
18 KiB
456 lines
18 KiB
5 days ago
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef GSP_STATIC_CONFIG_H
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#define GSP_STATIC_CONFIG_H
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//
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// This header describes the set of static GPU configuration information
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// that is collected during GSP RM init and made available to the
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// CPU RM (aka GSP client) via NV_RM_RPC_GET_GSP_STATIC_INFO() call.
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#include "ctrl/ctrl0080/ctrl0080gpu.h"
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#include "ctrl/ctrl2080/ctrl2080bios.h"
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#include "ctrl/ctrl2080/ctrl2080fb.h"
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#include "ctrl/ctrl2080/ctrl2080gpu.h"
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#include "vgpu/rpc_headers.h"
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#include "nvacpitypes.h"
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#include "ctrl/ctrl0073/ctrl0073system.h"
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#define MAX_DSM_SUPPORTED_FUNCS_RTN_LEN 8 // # bytes to store supported functions
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#define NV_ACPI_GENERIC_FUNC_COUNT 8
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#define REGISTRY_TABLE_ENTRY_TYPE_UNKNOWN 0
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#define REGISTRY_TABLE_ENTRY_TYPE_DWORD 1
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#define REGISTRY_TABLE_ENTRY_TYPE_BINARY 2
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#define REGISTRY_TABLE_ENTRY_TYPE_STRING 3
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typedef struct PACKED_REGISTRY_ENTRY
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{
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NvU32 nameOffset;
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NvU8 type;
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NvU32 data;
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NvU32 length;
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} PACKED_REGISTRY_ENTRY;
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typedef struct PACKED_REGISTRY_TABLE
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{
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NvU32 size;
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NvU32 numEntries;
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} PACKED_REGISTRY_TABLE;
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/* Indicates the current state of mux */
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typedef enum
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{
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dispMuxState_None = 0,
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dispMuxState_IntegratedGPU,
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dispMuxState_DiscreteGPU,
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} DISPMUXSTATE;
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typedef struct {
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// supported function status and cache
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NvU32 suppFuncStatus;
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NvU8 suppFuncs[MAX_DSM_SUPPORTED_FUNCS_RTN_LEN];
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NvU32 suppFuncsLen;
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NvBool bArg3isInteger;
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// callback status and cache
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NvU32 callbackStatus;
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NvU32 callback;
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} ACPI_DSM_CACHE;
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typedef struct {
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ACPI_DSM_CACHE dsm[ACPI_DSM_FUNCTION_COUNT];
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ACPI_DSM_FUNCTION dispStatusHotplugFunc;
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ACPI_DSM_FUNCTION dispStatusConfigFunc;
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ACPI_DSM_FUNCTION perfPostPowerStateFunc;
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ACPI_DSM_FUNCTION stereo3dStateActiveFunc;
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NvU32 dsmPlatCapsCache[ACPI_DSM_FUNCTION_COUNT];
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NvU32 MDTLFeatureSupport;
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// cache of generic func/subfunction remappings.
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ACPI_DSM_FUNCTION dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_COUNT];
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NvU32 dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_COUNT];
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NvU32 dsmCurrentFuncSupport;
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} ACPI_DATA;
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typedef struct DOD_METHOD_DATA
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{
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NV_STATUS status;
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NvU32 acpiIdListLen;
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NvU32 acpiIdList[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
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} DOD_METHOD_DATA;
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typedef struct JT_METHOD_DATA
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{
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NV_STATUS status;
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NvU32 jtCaps;
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NvU16 jtRevId;
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NvBool bSBIOSCaps;
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} JT_METHOD_DATA;
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typedef struct MUX_METHOD_DATA_ELEMENT
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{
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NvU32 acpiId;
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NvU32 mode;
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NV_STATUS status;
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} MUX_METHOD_DATA_ELEMENT;
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typedef struct MUX_METHOD_DATA
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{
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NvU32 tableLen;
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MUX_METHOD_DATA_ELEMENT acpiIdMuxModeTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
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MUX_METHOD_DATA_ELEMENT acpiIdMuxPartTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
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MUX_METHOD_DATA_ELEMENT acpiIdMuxStateTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
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} MUX_METHOD_DATA;
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typedef struct CAPS_METHOD_DATA
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{
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NV_STATUS status;
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NvU32 optimusCaps;
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} CAPS_METHOD_DATA;
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typedef struct ACPI_METHOD_DATA
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{
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NvBool bValid;
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DOD_METHOD_DATA dodMethodData;
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JT_METHOD_DATA jtMethodData;
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MUX_METHOD_DATA muxMethodData;
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CAPS_METHOD_DATA capsMethodData;
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} ACPI_METHOD_DATA;
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#define MAX_GROUP_COUNT 2
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// #include "gpu/nvbitmask.h"
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typedef enum
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{
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RM_ENGINE_TYPE_NULL = (0x00000000),
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RM_ENGINE_TYPE_GR0 = (0x00000001),
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RM_ENGINE_TYPE_GR1 = (0x00000002),
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RM_ENGINE_TYPE_GR2 = (0x00000003),
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RM_ENGINE_TYPE_GR3 = (0x00000004),
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RM_ENGINE_TYPE_GR4 = (0x00000005),
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RM_ENGINE_TYPE_GR5 = (0x00000006),
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RM_ENGINE_TYPE_GR6 = (0x00000007),
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RM_ENGINE_TYPE_GR7 = (0x00000008),
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RM_ENGINE_TYPE_COPY0 = (0x00000009),
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RM_ENGINE_TYPE_COPY1 = (0x0000000a),
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RM_ENGINE_TYPE_COPY2 = (0x0000000b),
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RM_ENGINE_TYPE_COPY3 = (0x0000000c),
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RM_ENGINE_TYPE_COPY4 = (0x0000000d),
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RM_ENGINE_TYPE_COPY5 = (0x0000000e),
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RM_ENGINE_TYPE_COPY6 = (0x0000000f),
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RM_ENGINE_TYPE_COPY7 = (0x00000010),
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RM_ENGINE_TYPE_COPY8 = (0x00000011),
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RM_ENGINE_TYPE_COPY9 = (0x00000012),
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RM_ENGINE_TYPE_COPY10 = (0x00000013),
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RM_ENGINE_TYPE_COPY11 = (0x00000014),
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RM_ENGINE_TYPE_COPY12 = (0x00000015),
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RM_ENGINE_TYPE_COPY13 = (0x00000016),
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RM_ENGINE_TYPE_COPY14 = (0x00000017),
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RM_ENGINE_TYPE_COPY15 = (0x00000018),
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RM_ENGINE_TYPE_COPY16 = (0x00000019),
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RM_ENGINE_TYPE_COPY17 = (0x0000001a),
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RM_ENGINE_TYPE_COPY18 = (0x0000001b),
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RM_ENGINE_TYPE_COPY19 = (0x0000001c),
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RM_ENGINE_TYPE_NVDEC0 = (0x0000001d),
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RM_ENGINE_TYPE_NVDEC1 = (0x0000001e),
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RM_ENGINE_TYPE_NVDEC2 = (0x0000001f),
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RM_ENGINE_TYPE_NVDEC3 = (0x00000020),
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RM_ENGINE_TYPE_NVDEC4 = (0x00000021),
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RM_ENGINE_TYPE_NVDEC5 = (0x00000022),
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RM_ENGINE_TYPE_NVDEC6 = (0x00000023),
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RM_ENGINE_TYPE_NVDEC7 = (0x00000024),
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RM_ENGINE_TYPE_NVENC0 = (0x00000025),
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RM_ENGINE_TYPE_NVENC1 = (0x00000026),
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RM_ENGINE_TYPE_NVENC2 = (0x00000027),
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// Bug 4175886 - Use this new value for all chips once GB20X is released
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RM_ENGINE_TYPE_NVENC3 = (0x00000028),
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RM_ENGINE_TYPE_VP = (0x00000029),
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RM_ENGINE_TYPE_ME = (0x0000002a),
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RM_ENGINE_TYPE_PPP = (0x0000002b),
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RM_ENGINE_TYPE_MPEG = (0x0000002c),
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RM_ENGINE_TYPE_SW = (0x0000002d),
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RM_ENGINE_TYPE_TSEC = (0x0000002e),
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RM_ENGINE_TYPE_VIC = (0x0000002f),
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RM_ENGINE_TYPE_MP = (0x00000030),
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RM_ENGINE_TYPE_SEC2 = (0x00000031),
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RM_ENGINE_TYPE_HOST = (0x00000032),
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RM_ENGINE_TYPE_DPU = (0x00000033),
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RM_ENGINE_TYPE_PMU = (0x00000034),
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RM_ENGINE_TYPE_FBFLCN = (0x00000035),
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RM_ENGINE_TYPE_NVJPEG0 = (0x00000036),
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RM_ENGINE_TYPE_NVJPEG1 = (0x00000037),
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RM_ENGINE_TYPE_NVJPEG2 = (0x00000038),
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RM_ENGINE_TYPE_NVJPEG3 = (0x00000039),
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RM_ENGINE_TYPE_NVJPEG4 = (0x0000003a),
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RM_ENGINE_TYPE_NVJPEG5 = (0x0000003b),
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RM_ENGINE_TYPE_NVJPEG6 = (0x0000003c),
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RM_ENGINE_TYPE_NVJPEG7 = (0x0000003d),
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RM_ENGINE_TYPE_OFA0 = (0x0000003e),
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RM_ENGINE_TYPE_OFA1 = (0x0000003f),
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RM_ENGINE_TYPE_RESERVED40 = (0x00000040),
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RM_ENGINE_TYPE_RESERVED41 = (0x00000041),
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RM_ENGINE_TYPE_RESERVED42 = (0x00000042),
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RM_ENGINE_TYPE_RESERVED43 = (0x00000043),
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RM_ENGINE_TYPE_RESERVED44 = (0x00000044),
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RM_ENGINE_TYPE_RESERVED45 = (0x00000045),
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RM_ENGINE_TYPE_RESERVED46 = (0x00000046),
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RM_ENGINE_TYPE_RESERVED47 = (0x00000047),
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RM_ENGINE_TYPE_RESERVED48 = (0x00000048),
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RM_ENGINE_TYPE_RESERVED49 = (0x00000049),
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RM_ENGINE_TYPE_RESERVED4a = (0x0000004a),
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RM_ENGINE_TYPE_RESERVED4b = (0x0000004b),
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RM_ENGINE_TYPE_RESERVED4c = (0x0000004c),
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RM_ENGINE_TYPE_RESERVED4d = (0x0000004d),
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RM_ENGINE_TYPE_RESERVED4e = (0x0000004e),
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RM_ENGINE_TYPE_RESERVED4f = (0x0000004f),
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RM_ENGINE_TYPE_RESERVED50 = (0x00000050),
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RM_ENGINE_TYPE_RESERVED51 = (0x00000051),
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RM_ENGINE_TYPE_RESERVED52 = (0x00000052),
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RM_ENGINE_TYPE_RESERVED53 = (0x00000053),
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RM_ENGINE_TYPE_LAST = (0x00000054),
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} RM_ENGINE_TYPE;
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//
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// The duplicates in the RM_ENGINE_TYPE. Using define instead of putting them
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// in the enum to make sure that each item in the enum has a unique number.
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//
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#define RM_ENGINE_TYPE_GRAPHICS RM_ENGINE_TYPE_GR0
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#define RM_ENGINE_TYPE_BSP RM_ENGINE_TYPE_NVDEC0
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#define RM_ENGINE_TYPE_MSENC RM_ENGINE_TYPE_NVENC0
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#define RM_ENGINE_TYPE_CIPHER RM_ENGINE_TYPE_TSEC
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#define RM_ENGINE_TYPE_NVJPG RM_ENGINE_TYPE_NVJPEG0
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#define RM_ENGINE_TYPE_COPY_SIZE 20
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// Bug 4175886 - Use this new value for all chips once GB20X is released
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#define RM_ENGINE_TYPE_NVENC_SIZE 4
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#define RM_ENGINE_TYPE_NVJPEG_SIZE 8
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#define RM_ENGINE_TYPE_NVDEC_SIZE 8
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#define RM_ENGINE_TYPE_OFA_SIZE 2
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#define RM_ENGINE_TYPE_GR_SIZE 8
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#define NVGPU_ENGINE_CAPS_MASK_BITS 32
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#define NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX ((RM_ENGINE_TYPE_LAST-1)/NVGPU_ENGINE_CAPS_MASK_BITS + 1)
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#define NVGPU_GET_ENGINE_CAPS_MASK(caps, id) (caps[(id)/NVGPU_ENGINE_CAPS_MASK_BITS] & NVBIT((id) % NVGPU_ENGINE_CAPS_MASK_BITS))
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#define NVGPU_SET_ENGINE_CAPS_MASK(caps, id) (caps[(id)/NVGPU_ENGINE_CAPS_MASK_BITS] |= NVBIT((id) % NVGPU_ENGINE_CAPS_MASK_BITS))
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// #include "gpu/gpu.h" // COMPUTE_BRANDING_TYPE
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// #include "gpu/gpu_acpi_data.h" // ACPI_METHOD_DATA
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// #include "vgpu/rpc_headers.h" // MAX_GPC_COUNT
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// #include "platform/chipset/chipset.h" // BUSINFO
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// #include "gpu/nvbitmask.h" // NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX
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typedef struct
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{
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NvU16 deviceID; // deviceID
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NvU16 vendorID; // vendorID
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NvU16 subdeviceID; // subsystem deviceID
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NvU16 subvendorID; // subsystem vendorID
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NvU8 revisionID; // revision ID
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} BUSINFO;
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// VF related info for GSP-RM
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typedef struct GSP_VF_INFO
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{
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NvU32 totalVFs;
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NvU32 firstVFOffset;
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NvU64 FirstVFBar0Address;
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NvU64 FirstVFBar1Address;
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NvU64 FirstVFBar2Address;
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NvBool b64bitBar0;
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NvBool b64bitBar1;
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NvBool b64bitBar2;
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} GSP_VF_INFO;
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// Cache config registers from pcie space
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typedef struct
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{
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// Link capabilities
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NvU32 linkCap;
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} GSP_PCIE_CONFIG_REG;
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typedef struct
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{
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NvU32 ecidLow;
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NvU32 ecidHigh;
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NvU32 ecidExtended;
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} EcidManufacturingInfo;
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typedef struct
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{
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NvU64 nonWprHeapOffset;
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NvU64 frtsOffset;
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} FW_WPR_LAYOUT_OFFSET;
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// Fetched from GSP-RM into CPU-RM
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typedef struct GspStaticConfigInfo_t
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{
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NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE];
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NV2080_CTRL_GPU_GET_GID_INFO_PARAMS gidInfo;
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NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo;
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NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams;
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NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS sriovCaps;
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NvU32 sriovMaxGfid;
|
||
|
|
|
||
|
|
NvU32 engineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX];
|
||
|
|
|
||
|
|
NvBool poisonFuseEnabled;
|
||
|
|
|
||
|
|
NvU64 fb_length;
|
||
|
|
NvU64 fbio_mask;
|
||
|
|
NvU32 fb_bus_width;
|
||
|
|
NvU32 fb_ram_type;
|
||
|
|
NvU64 fbp_mask;
|
||
|
|
NvU32 l2_cache_size;
|
||
|
|
|
||
|
|
NvU8 gpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
|
||
|
|
NvU8 gpuShortNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH];
|
||
|
|
NvU16 gpuNameString_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH];
|
||
|
|
NvBool bGpuInternalSku;
|
||
|
|
NvBool bIsQuadroGeneric;
|
||
|
|
NvBool bIsQuadroAd;
|
||
|
|
NvBool bIsNvidiaNvs;
|
||
|
|
NvBool bIsVgx;
|
||
|
|
NvBool bGeforceSmb;
|
||
|
|
NvBool bIsTitan;
|
||
|
|
NvBool bIsTesla;
|
||
|
|
NvBool bIsMobile;
|
||
|
|
NvBool bIsGc6Rtd3Allowed;
|
||
|
|
NvBool bIsGc8Rtd3Allowed;
|
||
|
|
NvBool bIsGcOffRtd3Allowed;
|
||
|
|
NvBool bIsGcoffLegacyAllowed;
|
||
|
|
NvBool bIsMigSupported;
|
||
|
|
|
||
|
|
/* "Total Board Power" refers to power requirement of GPU,
|
||
|
|
* while in GC6 state. Majority of this power will be used
|
||
|
|
* to keep V-RAM active to preserve its content.
|
||
|
|
* Some energy maybe consumed by Always-on components on GPU chip.
|
||
|
|
* This power will be provided by 3.3v voltage rail.
|
||
|
|
*/
|
||
|
|
NvU16 RTD3GC6TotalBoardPower;
|
||
|
|
|
||
|
|
/* PERST# (i.e. PCI Express Reset) is a sideband signal
|
||
|
|
* generated by the PCIe Host to indicate the PCIe devices,
|
||
|
|
* that the power-rails and the reference-clock are stable.
|
||
|
|
* The endpoint device typically uses this signal as a global reset.
|
||
|
|
*/
|
||
|
|
NvU16 RTD3GC6PerstDelay;
|
||
|
|
|
||
|
|
NvU64 bar1PdeBase;
|
||
|
|
NvU64 bar2PdeBase;
|
||
|
|
|
||
|
|
NvBool bVbiosValid;
|
||
|
|
NvU32 vbiosSubVendor;
|
||
|
|
NvU32 vbiosSubDevice;
|
||
|
|
|
||
|
|
NvBool bPageRetirementSupported;
|
||
|
|
|
||
|
|
NvBool bSplitVasBetweenServerClientRm;
|
||
|
|
|
||
|
|
NvBool bClRootportNeedsNosnoopWAR;
|
||
|
|
|
||
|
|
VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads;
|
||
|
|
VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution;
|
||
|
|
NvU64 displaylessMaxPixels;
|
||
|
|
|
||
|
|
// Client handle for internal RMAPI control.
|
||
|
|
NvHandle hInternalClient;
|
||
|
|
|
||
|
|
// Device handle for internal RMAPI control.
|
||
|
|
NvHandle hInternalDevice;
|
||
|
|
|
||
|
|
// Subdevice handle for internal RMAPI control.
|
||
|
|
NvHandle hInternalSubdevice;
|
||
|
|
|
||
|
|
NvBool bSelfHostedMode;
|
||
|
|
NvBool bAtsSupported;
|
||
|
|
|
||
|
|
NvBool bIsGpuUefi;
|
||
|
|
NvBool bIsEfiInit;
|
||
|
|
|
||
|
|
EcidManufacturingInfo ecidInfo[MAX_GROUP_COUNT];
|
||
|
|
|
||
|
|
FW_WPR_LAYOUT_OFFSET fwWprLayoutOffset;
|
||
|
|
} GspStaticConfigInfo;
|
||
|
|
|
||
|
|
// Pushed from CPU-RM to GSP-RM
|
||
|
|
typedef struct GspSystemInfo
|
||
|
|
{
|
||
|
|
NvU64 gpuPhysAddr;
|
||
|
|
NvU64 gpuPhysFbAddr;
|
||
|
|
NvU64 gpuPhysInstAddr;
|
||
|
|
NvU64 gpuPhysIoAddr;
|
||
|
|
NvU64 nvDomainBusDeviceFunc;
|
||
|
|
NvU64 simAccessBufPhysAddr;
|
||
|
|
NvU64 notifyOpSharedSurfacePhysAddr;
|
||
|
|
NvU64 pcieAtomicsOpMask;
|
||
|
|
NvU64 consoleMemSize;
|
||
|
|
NvU64 maxUserVa;
|
||
|
|
NvU32 pciConfigMirrorBase;
|
||
|
|
NvU32 pciConfigMirrorSize;
|
||
|
|
NvU32 PCIDeviceID;
|
||
|
|
NvU32 PCISubDeviceID;
|
||
|
|
NvU32 PCIRevisionID;
|
||
|
|
NvU32 pcieAtomicsCplDeviceCapMask;
|
||
|
|
NvU8 oorArch;
|
||
|
|
NvU64 clPdbProperties;
|
||
|
|
NvU32 Chipset;
|
||
|
|
NvBool bGpuBehindBridge;
|
||
|
|
NvBool bFlrSupported;
|
||
|
|
NvBool b64bBar0Supported;
|
||
|
|
NvBool bMnocAvailable;
|
||
|
|
NvU32 chipsetL1ssEnable;
|
||
|
|
NvBool bUpstreamL0sUnsupported;
|
||
|
|
NvBool bUpstreamL1Unsupported;
|
||
|
|
NvBool bUpstreamL1PorSupported;
|
||
|
|
NvBool bUpstreamL1PorMobileOnly;
|
||
|
|
NvBool bSystemHasMux;
|
||
|
|
NvU8 upstreamAddressValid;
|
||
|
|
BUSINFO FHBBusInfo;
|
||
|
|
BUSINFO chipsetIDInfo;
|
||
|
|
ACPI_METHOD_DATA acpiMethodData;
|
||
|
|
NvU32 hypervisorType;
|
||
|
|
NvBool bIsPassthru;
|
||
|
|
NvU64 sysTimerOffsetNs;
|
||
|
|
GSP_VF_INFO gspVFInfo;
|
||
|
|
NvBool bIsPrimary;
|
||
|
|
NvBool isGridBuild;
|
||
|
|
GSP_PCIE_CONFIG_REG pcieConfigReg;
|
||
|
|
NvU32 gridBuildCsp;
|
||
|
|
NvBool bPreserveVideoMemoryAllocations;
|
||
|
|
NvBool bTdrEventSupported;
|
||
|
|
NvBool bFeatureStretchVblankCapable;
|
||
|
|
NvBool bEnableDynamicGranularityPageArrays;
|
||
|
|
NvBool bClockBoostSupported;
|
||
|
|
NvBool bRouteDispIntrsToCPU;
|
||
|
|
NvU64 hostPageSize;
|
||
|
|
} GspSystemInfo;
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* GSP_STATIC_CONFIG_H */
|