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261 lines
14 KiB
261 lines
14 KiB
from __future__ import annotations
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import ctypes, collections, dataclasses, functools, os, hashlib
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from tinygrad.helpers import mv_address, getenv, DEBUG, fetch
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from tinygrad.runtime.autogen.am import am
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from tinygrad.runtime.support.hcq import MMIOInterface
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from tinygrad.runtime.support.amd import AMDReg, import_module, import_asic_regs
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from tinygrad.runtime.support.memory import TLSFAllocator, MemoryManager
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from tinygrad.runtime.support.system import System, PCIDevImplBase
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from tinygrad.runtime.support.am.ip import AM_SOC, AM_GMC, AM_IH, AM_PSP, AM_SMU, AM_GFX, AM_SDMA
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AM_DEBUG = getenv("AM_DEBUG", 0)
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@dataclasses.dataclass
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class AMRegister(AMDReg):
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adev:AMDev
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def read(self, inst=0): return self.adev.rreg(self.addr[inst])
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def read_bitfields(self, inst=0) -> dict[str, int]: return self.decode(self.read(inst=inst))
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def write(self, _am_val:int=0, inst=0, **kwargs): self.adev.wreg(self.addr[inst], _am_val | self.encode(**kwargs))
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def update(self, inst=0, **kwargs): self.write(self.read(inst=inst) & ~self.fields_mask(*kwargs.keys()), inst=inst, **kwargs)
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class AMFirmware:
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def __init__(self, adev):
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self.adev = adev
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def fmt_ver(hwip): return '_'.join(map(str, adev.ip_ver[hwip]))
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# Load SOS firmware
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self.sos_fw = {}
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blob, sos_hdr = self.load_fw(f"psp_{fmt_ver(am.MP0_HWIP)}_sos.bin", versioned_header='struct_psp_firmware_header')
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fw_bin = sos_hdr.psp_fw_bin
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for fw_i in range(sos_hdr.psp_fw_bin_count):
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fw_bin_desc = am.struct_psp_fw_bin_desc.from_address(ctypes.addressof(fw_bin) + fw_i * ctypes.sizeof(am.struct_psp_fw_bin_desc))
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ucode_start_offset = fw_bin_desc.offset_bytes + sos_hdr.header.ucode_array_offset_bytes
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self.sos_fw[fw_bin_desc.fw_type] = blob[ucode_start_offset:ucode_start_offset+fw_bin_desc.size_bytes]
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# Load other fw
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self.ucode_start: dict[str, int] = {}
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self.descs: list[tuple[list[int], memoryview]] = []
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blob, hdr = self.load_fw(f"smu_{fmt_ver(am.MP1_HWIP)}.bin", am.struct_smc_firmware_header_v1_0)
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self.smu_psp_desc = self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.header.ucode_size_bytes, am.GFX_FW_TYPE_SMU)
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# SDMA firmware
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blob, hdr = self.load_fw(f"sdma_{fmt_ver(am.SDMA0_HWIP)}.bin", versioned_header='struct_sdma_firmware_header')
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if hdr.header.header_version_major < 3:
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self.descs += [self.desc(blob, hdr.ctl_ucode_offset, hdr.ctl_ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH1)]
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self.descs += [self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.ctx_ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH0)]
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else: self.descs += [self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH0)]
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# PFP, ME, MEC firmware
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for (fw_name, fw_cnt) in ([('PFP', 1), ('ME', 1)] if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0) else []) + [('MEC', 1)]:
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blob, hdr = self.load_fw(f"gc_{fmt_ver(am.GC_HWIP)}_{fw_name.lower()}.bin", am.struct_gfx_firmware_header_v2_0)
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# Code part
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self.descs += [self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.ucode_size_bytes, getattr(am, f'GFX_FW_TYPE_RS64_{fw_name}'))]
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# Stack
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stack_fws = [getattr(am, f'GFX_FW_TYPE_RS64_{fw_name}_P{fwnum}_STACK') for fwnum in range(fw_cnt)]
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self.descs += [self.desc(blob, hdr.data_offset_bytes, hdr.data_size_bytes, *stack_fws)]
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self.ucode_start[fw_name] = hdr.ucode_start_addr_lo | (hdr.ucode_start_addr_hi << 32)
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# IMU firmware
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blob, hdr = self.load_fw(f"gc_{fmt_ver(am.GC_HWIP)}_imu.bin", am.struct_imu_firmware_header_v1_0)
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imu_i_off, imu_i_sz, imu_d_sz = hdr.header.ucode_array_offset_bytes, hdr.imu_iram_ucode_size_bytes, hdr.imu_dram_ucode_size_bytes
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self.descs += [self.desc(blob, imu_i_off, imu_i_sz, am.GFX_FW_TYPE_IMU_I), self.desc(blob, imu_i_off + imu_i_sz, imu_d_sz, am.GFX_FW_TYPE_IMU_D)]
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# RLC firmware
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blob, hdr0, _hdr1, hdr2, hdr3 = self.load_fw(f"gc_{fmt_ver(am.GC_HWIP)}_rlc.bin", am.struct_rlc_firmware_header_v2_0,
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am.struct_rlc_firmware_header_v2_1, am.struct_rlc_firmware_header_v2_2, am.struct_rlc_firmware_header_v2_3)
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for mem,fmem in [('IRAM', 'iram'), ('DRAM_BOOT', 'dram')]:
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off, sz = getattr(hdr2, f'rlc_{fmem}_ucode_offset_bytes'), getattr(hdr2, f'rlc_{fmem}_ucode_size_bytes')
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self.descs += [self.desc(blob, off, sz, getattr(am, f'GFX_FW_TYPE_RLC_{mem}'))]
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if hdr0.header.header_version_minor == 3:
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for mem in ['P', 'V']:
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off, sz = getattr(hdr3, f'rlc{mem.lower()}_ucode_offset_bytes'), getattr(hdr3, f'rlc{mem.lower()}_ucode_size_bytes')
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self.descs += [self.desc(blob, off, sz, getattr(am, f'GFX_FW_TYPE_RLC_{mem}'))]
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self.descs += [self.desc(blob, hdr0.header.ucode_array_offset_bytes, hdr0.header.ucode_size_bytes, am.GFX_FW_TYPE_RLC_G)]
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def load_fw(self, fname:str, *headers, versioned_header:str|None=None):
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fpath = fetch(f"https://gitlab.com/kernel-firmware/linux-firmware/-/raw/45f59212aebd226c7630aff4b58598967c0c8c91/amdgpu/{fname}", subdir="fw")
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blob = memoryview(bytearray(fpath.read_bytes()))
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if AM_DEBUG >= 1: print(f"am {self.adev.devfmt}: loading firmware {fname}: {hashlib.sha256(blob).hexdigest()}")
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if versioned_header:
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chdr = am.struct_common_firmware_header.from_address(mv_address(blob))
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headers += (getattr(am, versioned_header + f"_v{chdr.header_version_major}_{chdr.header_version_minor}"),)
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return tuple([blob] + [hdr.from_address(mv_address(blob)) for hdr in headers])
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def desc(self, blob:memoryview, offset:int, size:int, *types:int) -> tuple[list[int], memoryview]: return (list(types), blob[offset:offset+size])
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class AMPageTableEntry:
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def __init__(self, adev, paddr, lv): self.adev, self.paddr, self.lv, self.entries = adev, paddr, lv, adev.vram.view(paddr, 0x1000, fmt='Q')
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def set_entry(self, entry_id:int, paddr:int, table=False, uncached=False, system=False, snooped=False, frag=0, valid=True):
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assert paddr & self.adev.gmc.address_space_mask == paddr, f"Invalid physical address {paddr:#x}"
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self.entries[entry_id] = self.adev.gmc.get_pte_flags(self.lv, table, frag, uncached, system, snooped, valid) | (paddr & 0x0000FFFFFFFFF000)
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def entry(self, entry_id:int) -> int: return self.entries[entry_id]
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def valid(self, entry_id:int) -> bool: return (self.entries[entry_id] & am.AMDGPU_PTE_VALID) != 0
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def address(self, entry_id:int) -> int: return self.entries[entry_id] & 0x0000FFFFFFFFF000
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def is_huge_page(self, entry_id:int) -> bool: return self.lv == am.AMDGPU_VM_PTB or self.adev.gmc.is_pte_huge_page(self.entries[entry_id])
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def supports_huge_page(self, paddr:int): return self.lv >= am.AMDGPU_VM_PDB2
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class AMMemoryManager(MemoryManager):
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va_allocator = TLSFAllocator(512 * (1 << 30), base=0x200000000000) # global for all devices.
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def on_range_mapped(self):
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# Invalidate TLB after mappings.
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self.dev.gmc.flush_tlb(ip='GC', vmid=0)
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self.dev.gmc.flush_tlb(ip='MM', vmid=0)
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class AMDev(PCIDevImplBase):
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Version = 0xA0000006
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def __init__(self, devfmt, vram:MMIOInterface, doorbell:MMIOInterface, mmio:MMIOInterface, dma_regions:list[tuple[int, MMIOInterface]]|None=None):
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self.devfmt, self.vram, self.doorbell64, self.mmio, self.dma_regions = devfmt, vram, doorbell, mmio, dma_regions
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self.lock_fd = System.flock_acquire(f"am_{self.devfmt}.lock")
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self._run_discovery()
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self._build_regs()
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# AM boot Process:
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# The GPU being passed can be in one of several states: 1. Not initialized. 2. Initialized by amdgpu. 3. Initialized by AM.
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# The 1st and 2nd states require a full GPU setup since their states are unknown. The 2nd state also requires a mode1 reset to
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# reinitialize all components.
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#
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# The 3rd state can be set up partially to optimize boot time. In this case, only the GFX and SDMA IPs need to be initialized.
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# To enable this, AM uses a separate boot memory that is guaranteed not to be overwritten. This physical memory is utilized for
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# all blocks that are initialized only during the initial AM boot.
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# To determine if the GPU is in the third state, AM uses regSCRATCH_REG7 as a flag.
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self.is_booting = True
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self.init_sw(smi_dev=False)
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self.partial_boot = (self.reg("regSCRATCH_REG7").read() == AMDev.Version) and (getenv("AM_RESET", 0) != 1)
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if self.partial_boot and (self.reg("regGCVM_CONTEXT0_CNTL").read() != 0 or self.reg(self.gmc.pf_status_reg("GC")).read() != 0):
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if DEBUG >= 2: print(f"am {self.devfmt}: Malformed state. Issuing a full reset.")
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self.partial_boot = False
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# Init hw for IP blocks where it is needed
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if not self.partial_boot:
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if self.psp.is_sos_alive() and self.smu.is_smu_alive(): self.smu.mode1_reset()
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for ip in [self.soc, self.gmc, self.ih, self.psp, self.smu]:
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ip.init_hw()
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if DEBUG >= 2: print(f"am {self.devfmt}: {ip.__class__.__name__} initialized")
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# Booting done
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self.is_booting = False
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# Re-initialize main blocks
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for ip in [self.gfx, self.sdma]:
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ip.init_hw()
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if DEBUG >= 2: print(f"am {self.devfmt}: {ip.__class__.__name__} initialized")
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self.smu.set_clocks(level=-1) # last level, max perf.
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for ip in [self.soc, self.gfx]: ip.set_clockgating_state()
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self.reg("regSCRATCH_REG7").write(AMDev.Version)
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if DEBUG >= 2: print(f"am {self.devfmt}: boot done")
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def init_sw(self, smi_dev=False):
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self.smi_dev = smi_dev # During boot only boot memory can be allocated. This flag is to validate this.
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# Memory manager & firmware
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self.mm = AMMemoryManager(self, self.vram_size, boot_size=(32 << 20), pt_t=AMPageTableEntry, va_shifts=[12, 21, 30, 39], va_bits=48,
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first_lv=am.AMDGPU_VM_PDB2, va_base=AMMemoryManager.va_allocator.base,
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palloc_ranges=[(1 << (i + 12), 0x1000) for i in range(9 * (3 - am.AMDGPU_VM_PDB2), -1, -1)])
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self.fw = AMFirmware(self)
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# Initialize IP blocks
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self.soc:AM_SOC = AM_SOC(self)
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self.gmc:AM_GMC = AM_GMC(self)
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self.ih:AM_IH = AM_IH(self)
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self.psp:AM_PSP = AM_PSP(self)
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self.smu:AM_SMU = AM_SMU(self)
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self.gfx:AM_GFX = AM_GFX(self)
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self.sdma:AM_SDMA = AM_SDMA(self)
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# Init sw for all IP blocks
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for ip in [self.soc, self.gmc, self.ih, self.psp, self.smu, self.gfx, self.sdma]: ip.init_sw()
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def fini(self):
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if DEBUG >= 2: print(f"am {self.devfmt}: Finalizing")
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for ip in [self.sdma, self.gfx]: ip.fini_hw()
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self.smu.set_clocks(level=0)
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self.ih.interrupt_handler()
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os.close(self.lock_fd)
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def paddr2mc(self, paddr:int) -> int: return self.gmc.mc_base + paddr
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def reg(self, reg:str) -> AMRegister: return self.__dict__[reg]
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def rreg(self, reg:int) -> int:
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val = self.indirect_rreg(reg * 4) if reg > len(self.mmio) else self.mmio[reg]
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if AM_DEBUG >= 4 and getattr(self, '_prev_rreg', None) != (reg, val): print(f"am {self.devfmt}: Reading register {reg:#x} with value {val:#x}")
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self._prev_rreg = (reg, val)
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return val
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def wreg(self, reg:int, val:int):
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if AM_DEBUG >= 4: print(f"am {self.devfmt}: Writing register {reg:#x} with value {val:#x}")
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if reg > len(self.mmio): self.indirect_wreg(reg * 4, val)
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else: self.mmio[reg] = val
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def wreg_pair(self, reg_base:str, lo_suffix:str, hi_suffix:str, val:int):
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self.reg(f"{reg_base}{lo_suffix}").write(val & 0xffffffff)
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self.reg(f"{reg_base}{hi_suffix}").write(val >> 32)
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def indirect_rreg(self, reg:int) -> int:
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self.reg("regBIF_BX_PF0_RSMU_INDEX").write(reg)
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return self.reg("regBIF_BX_PF0_RSMU_DATA").read()
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def indirect_wreg(self, reg:int, val:int):
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self.reg("regBIF_BX_PF0_RSMU_INDEX").write(reg)
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self.reg("regBIF_BX_PF0_RSMU_DATA").write(val)
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def _run_discovery(self):
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# NOTE: Fixed register to query memory size without known ip bases to find the discovery table.
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# The table is located at the end of VRAM - 64KB and is 10KB in size.
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mmRCC_CONFIG_MEMSIZE = 0xde3
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self.vram_size = self.rreg(mmRCC_CONFIG_MEMSIZE) << 20
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tmr_offset, tmr_size = self.vram_size - (64 << 10), (10 << 10)
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self.bhdr = am.struct_binary_header.from_buffer(bytearray(self.vram.view(tmr_offset, tmr_size)[:]))
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ihdr = am.struct_ip_discovery_header.from_address(ctypes.addressof(self.bhdr) + self.bhdr.table_list[am.IP_DISCOVERY].offset)
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assert self.bhdr.binary_signature == am.BINARY_SIGNATURE and ihdr.signature == am.DISCOVERY_TABLE_SIGNATURE, "discovery signatures mismatch"
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# Mapping of HW IP to Discovery HW IP
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hw_id_map = {am.__dict__[x]: int(y) for x,y in am.hw_id_map}
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self.regs_offset:dict[int, dict[int, tuple]] = collections.defaultdict(dict)
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self.ip_ver:dict[int, tuple[int, int, int]] = {}
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for num_die in range(ihdr.num_dies):
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dhdr = am.struct_die_header.from_address(ctypes.addressof(self.bhdr) + ihdr.die_info[num_die].die_offset)
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ip_offset = ctypes.addressof(self.bhdr) + ctypes.sizeof(dhdr) + ihdr.die_info[num_die].die_offset
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for _ in range(dhdr.num_ips):
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ip = am.struct_ip_v4.from_address(ip_offset)
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ba = (ctypes.c_uint32 * ip.num_base_address).from_address(ip_offset + 8)
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for hw_ip in range(1, am.MAX_HWIP):
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if hw_ip in hw_id_map and hw_id_map[hw_ip] == ip.hw_id:
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self.regs_offset[hw_ip][ip.instance_number] = tuple(list(ba))
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self.ip_ver[hw_ip] = (ip.major, ip.minor, ip.revision)
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ip_offset += 8 + (8 if ihdr.base_addr_64_bit else 4) * ip.num_base_address
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gc_info = am.struct_gc_info_v1_0.from_address(gc_addr:=ctypes.addressof(self.bhdr) + self.bhdr.table_list[am.GC].offset)
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self.gc_info = getattr(am, f"struct_gc_info_v{gc_info.header.version_major}_{gc_info.header.version_minor}").from_address(gc_addr)
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def _ip_module(self, prefix:str, hwip, prever_prefix:str=""): return import_module(prefix, self.ip_ver[hwip], prever_prefix)
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def _build_regs(self):
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mods = [("mp", am.MP0_HWIP), ("hdp", am.HDP_HWIP), ("gc", am.GC_HWIP), ("mmhub", am.MMHUB_HWIP), ("osssys", am.OSSSYS_HWIP),
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("nbio" if self.ip_ver[am.GC_HWIP] < (12,0,0) else "nbif", am.NBIO_HWIP)]
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for prefix, hwip in mods:
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self.__dict__.update(import_asic_regs(prefix, self.ip_ver[hwip], cls=functools.partial(AMRegister, adev=self, bases=self.regs_offset[hwip])))
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self.__dict__.update(import_asic_regs('mp', (11, 0), cls=functools.partial(AMRegister, adev=self, bases=self.regs_offset[am.MP1_HWIP])))
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