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81 lines
2.0 KiB
81 lines
2.0 KiB
// this is needed for 1 mbps support
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#define CAN_QUANTA 8
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#define CAN_SEQ1 6 // roundf(quanta * 0.875f) - 1;
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#define CAN_SEQ2 1 // roundf(quanta * 0.125f);
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#define CAN_PCLK 24000
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// 333 = 33.3 kbps
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// 5000 = 500 kbps
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#define can_speed_to_prescaler(x) (CAN_PCLK / CAN_QUANTA * 10 / (x))
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bool llcan_set_speed(CAN_TypeDef *CAN, uint32_t speed, bool loopback, bool silent) {
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// initialization mode
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CAN->MCR = CAN_MCR_TTCM | CAN_MCR_INRQ;
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while((CAN->MSR & CAN_MSR_INAK) != CAN_MSR_INAK);
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// set time quanta from defines
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CAN->BTR = (CAN_BTR_TS1_0 * (CAN_SEQ1-1)) |
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(CAN_BTR_TS2_0 * (CAN_SEQ2-1)) |
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(can_speed_to_prescaler(speed) - 1);
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// silent loopback mode for debugging
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if (loopback) {
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CAN->BTR |= CAN_BTR_SILM | CAN_BTR_LBKM;
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}
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if (silent) {
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CAN->BTR |= CAN_BTR_SILM;
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}
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// reset
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CAN->MCR = CAN_MCR_TTCM | CAN_MCR_ABOM;
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#define CAN_TIMEOUT 1000000
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int tmp = 0;
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bool ret = false;
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while(((CAN->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (tmp < CAN_TIMEOUT)) tmp++;
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if (tmp < CAN_TIMEOUT) {
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ret = true;
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}
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return ret;
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}
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void llcan_init(CAN_TypeDef *CAN) {
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// accept all filter
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CAN->FMR |= CAN_FMR_FINIT;
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// no mask
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CAN->sFilterRegister[0].FR1 = 0;
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CAN->sFilterRegister[0].FR2 = 0;
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CAN->sFilterRegister[14].FR1 = 0;
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CAN->sFilterRegister[14].FR2 = 0;
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CAN->FA1R |= 1 | (1U << 14);
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CAN->FMR &= ~(CAN_FMR_FINIT);
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// enable certain CAN interrupts
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CAN->IER |= CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_WKUIE;
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if (CAN == CAN1) {
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NVIC_EnableIRQ(CAN1_TX_IRQn);
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NVIC_EnableIRQ(CAN1_RX0_IRQn);
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NVIC_EnableIRQ(CAN1_SCE_IRQn);
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} else if (CAN == CAN2) {
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NVIC_EnableIRQ(CAN2_TX_IRQn);
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NVIC_EnableIRQ(CAN2_RX0_IRQn);
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NVIC_EnableIRQ(CAN2_SCE_IRQn);
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#ifdef CAN3
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} else if (CAN == CAN3) {
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NVIC_EnableIRQ(CAN3_TX_IRQn);
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NVIC_EnableIRQ(CAN3_RX0_IRQn);
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NVIC_EnableIRQ(CAN3_SCE_IRQn);
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#endif
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}
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}
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void llcan_clear_send(CAN_TypeDef *CAN) {
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CAN->TSR |= CAN_TSR_ABRQ0;
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CAN->MSR &= ~(CAN_MSR_ERRI);
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CAN->MSR = CAN->MSR;
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}
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