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88 lines
2.4 KiB
88 lines
2.4 KiB
11 hours ago
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_IRQ_H__
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#define __AMDGPU_IRQ_H__
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// #include <linux/irqdomain.h>
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// #include "soc15_ih_clientid.h"
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// #include "amdgpu_ih.h"
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#define int32_t int
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#define uint32_t unsigned int
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#define int8_t signed char
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#define uint8_t unsigned char
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#define uint16_t unsigned short
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#define int16_t short
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#define uint64_t unsigned long long
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#define bool _Bool
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#define u32 unsigned int
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#define AMDGPU_MAX_IRQ_SRC_ID 0x100
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#define AMDGPU_MAX_IRQ_CLIENT_ID 0x100
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#define AMDGPU_IRQ_CLIENTID_LEGACY 0
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#define AMDGPU_IRQ_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
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#define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW 4
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struct amdgpu_device;
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enum amdgpu_interrupt_state {
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AMDGPU_IRQ_STATE_DISABLE,
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AMDGPU_IRQ_STATE_ENABLE,
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};
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struct amdgpu_iv_entry {
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// struct amdgpu_ih_ring *ih;
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unsigned client_id;
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unsigned src_id;
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unsigned ring_id;
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unsigned vmid;
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unsigned vmid_src;
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uint64_t timestamp;
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unsigned timestamp_src;
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unsigned pasid;
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unsigned node_id;
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unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
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const uint32_t *iv_entry;
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};
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enum interrupt_node_id_per_aid {
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AID0_NODEID = 0,
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XCD0_NODEID = 1,
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XCD1_NODEID = 2,
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AID1_NODEID = 4,
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XCD2_NODEID = 5,
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XCD3_NODEID = 6,
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AID2_NODEID = 8,
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XCD4_NODEID = 9,
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XCD5_NODEID = 10,
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AID3_NODEID = 12,
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XCD6_NODEID = 13,
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XCD7_NODEID = 14,
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NODEID_MAX,
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};
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#endif
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