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34 lines
1.5 KiB
34 lines
1.5 KiB
2 years ago
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#define CLOCK_SOURCE_PERIOD_MS 50U
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#define CLOCK_SOURCE_PULSE_LEN_MS 2U
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void clock_source_init(void) {
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// Setup timer
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register_set(&(TIM1->PSC), ((APB2_TIMER_FREQ*100U)-1U), 0xFFFFU); // Tick on 0.1 ms
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register_set(&(TIM1->ARR), ((CLOCK_SOURCE_PERIOD_MS*10U) - 1U), 0xFFFFU); // Period
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register_set(&(TIM1->CCMR1), 0U, 0xFFFFU); // No output on compare
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register_set(&(TIM1->CCER), TIM_CCER_CC1E, 0xFFFFU); // Enable compare 1
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register_set(&(TIM1->CCR1), (CLOCK_SOURCE_PULSE_LEN_MS*10U), 0xFFFFU); // Compare 1 value
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register_set(&(TIM1->CCR2), (CLOCK_SOURCE_PULSE_LEN_MS*10U), 0xFFFFU); // Compare 1 value
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register_set(&(TIM1->CCR3), (CLOCK_SOURCE_PULSE_LEN_MS*10U), 0xFFFFU); // Compare 1 value
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register_set_bits(&(TIM1->DIER), TIM_DIER_UIE | TIM_DIER_CC1IE); // Enable interrupts
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register_set(&(TIM1->CR1), TIM_CR1_CEN, 0x3FU); // Enable timer
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// No interrupts
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NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn);
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NVIC_DisableIRQ(TIM1_CC_IRQn);
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// Set GPIO as timer channels
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set_gpio_alternate(GPIOB, 14, GPIO_AF1_TIM1);
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set_gpio_alternate(GPIOB, 15, GPIO_AF1_TIM1);
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// Set PWM mode
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register_set(&(TIM1->CCMR1), (0b110 << TIM_CCMR1_OC2M_Pos), 0xFFFFU);
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register_set(&(TIM1->CCMR2), (0b110 << TIM_CCMR2_OC3M_Pos), 0xFFFFU);
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// Enable output
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register_set(&(TIM1->BDTR), TIM_BDTR_MOE, 0xFFFFU);
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// Enable complementary compares
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register_set_bits(&(TIM1->CCER), TIM_CCER_CC2NE | TIM_CCER_CC3NE);
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}
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