Squashed 'panda/' changes from 30c7ca8a5..256d274e7

256d274e7 Fix Mac installation instruction per: https://github.com/commaai/panda/pull/308/files
bfd8ff1b1 Update cppcheck commit with more coverage
b143a1cf9 Fixed Misra complaint
606f1d913 Fixed RTC on non-uno boards, second try. Cannot work when there is no xtal.
933c75770 Fix RTC on non-uno boards (#311)
48d0d0c78 VW button spam: fix safety and add tests (#306)
6cccf969a Fan and IR at 0 when in power savings mode (#309)
05373282a board get_sdk scripts were left on python2
de18a7ef1 bump version after uno merge
1965817d3 Changed default values for testing
a12a148d5 Uno (#274)
7d29dc5a2 bump panda version. We really need a better way
40075321d VW: stricter limits to comply with comma safety policy
e2e2be92c add safety mode to health packet
101238c7f turned on VW ignition based CAN logic
a0d8d5dae fix misra 5.3: check_ignition is intended as check_started and can't be used twice
ea636de61 made check_ignition function to both look at ignition_line and ignition_can
1102e6965 make ignition logic common for all cars (#303)
3a110c6f6 bump version after CMSIS core upgrade
55dfa5230 Update core to CMSIS 5.6 release  (#251)
ee864907c fix linter 2
f410b110d fix linter
55957d6e4 proper python3 exception inheritance
6ba0f47b5 fix linter errors
5c49fe050 Merge pull request #145 from gregjhogan/uds
0f361999b timeout is float
396d6aad5 safety_replay only installs few extra requirements
25af7d301 Misra also need python 3 env
7434c5ce2 centralize requirements for tests
a0c37c70a coverage not needed in linter reqs
fce38a91d Linter python (#299)
62e2f5caa update cppcheck commit
711810d2f more uds debug
4454e3a6b better CAN comm abstraction
6b1f28f57 fix more encoding and some bytes cleanup (#300)
43adad311 fix WARNING_INDICATOR_REQUESTED name
9c857da37 0x
b64d6fa5d typing
768fdf7e1 bytes() > chr().encode()
1be15ea93 custom errors from thread
68da8315f more python3
eb358e81c uds lib example
4f288586d updates for python3
932745f62 support tx flow control for chunked messages
b1c371292 add timeout param
cdf2f626b bug fixes
b1a319577 fix rx message filtering bug
80fb6a6fa convert uds lib to class
59cd2b47f handle separation time in microseconds
4429600d8 fix separation time parsing
c641e66f7 fix typo
48b8dcc6f fix flow control delay scale
78f413d88 flow control delay
33a5167d9 bug fixes
8ee89a091 multi-frame tx
5e89a9c72 clear rx buffer and numeric error ids
966230063 fix remaining size calculation
01ef1fae3 zero pad messages before sending
1ddc9735d uds can communication
dca176e71 syntax errors
95be4811e SERVICE_TYPE enum
98e73b51d more UDS message type implementation
c1c5b0356 uds lib
162f4853d fix chr to bytes conversions (#298)
4972376de Update VW regression test to follow Comma safety index refactoring (#296)
f9053f5df more Python 3 fixes, attempting to fix jenkins wifi regresison test (#295)
2f9e07628 Panda safety code for Volkswagen, Audi, SEAT, and Škoda (#293)

git-subtree-dir: panda
git-subtree-split: 256d274e760ce00d4e5ff5e0d9b86d0fb5924568

.circleci/config.yml

@@ -92,6 +92,20 @@ jobs:
           command: |
             docker run language_check /bin/bash -c "cd /panda/tests/language; ./test_language.py"
 
+  linter_python:
+    machine:
+      docker_layer_caching: true
+    steps:
+      - checkout
+      - run:
+          name: Build image
+          command: "docker build -t linter_python -f tests/linter_python/Dockerfile ."
+      - run:
+          name: Run linter python test
+          command: |
+            docker run linter_python /bin/bash -c "cd /panda/tests/linter_python; PYTHONPATH=/ ./flake8_panda.sh"
+            docker run linter_python /bin/bash -c "cd /panda/tests/linter_python; PYTHONPATH=/ ./pylint_panda.sh"
+
 workflows:
   version: 2
   main:
@@ -101,3 +115,4 @@ workflows:
       - build
       - safety_replay
       - language_check
+      - linter_python

Jenkinsfile

@@ -46,6 +46,21 @@ pipeline {
         }
       }
     }
+/*
+    stage('Test Dev Build (WIFI)') {
+      steps {
+        lock(resource: "Pandas", inversePrecedence: true, quantity: 1){
+          timeout(time: 60, unit: 'MINUTES') {
+            script {
+              sh "docker run --name ${env.DOCKER_NAME} --privileged --volume /dev/bus/usb:/dev/bus/usb --volume /var/run/dbus:/var/run/dbus --net host ${env.DOCKER_IMAGE_TAG} bash -c 'cd /tmp/panda; ./run_automated_tests.sh'"
+              sh "docker cp ${env.DOCKER_NAME}:/tmp/panda/nosetests.xml test_results_dev.xml"
+              sh "docker rm ${env.DOCKER_NAME}"
+            }
+          }
+        }
+      }
+    }
+*/
   }
   post {
     failure {

README.md

@@ -108,6 +108,8 @@ to ensure that the behavior remains unchanged.
     * compiling the code in various configuration and flashing it both through USB and WiFi.
     * Receiving, sending and forwarding CAN messages on all buses, over USB and WiFi.
 
+In addition, we run [Pylint](https://www.pylint.org/) and [Flake8](https://github.com/PyCQA/flake8) linters on all python files within the panda repo.
+
 Hardware
 ------
 

UPDATING.md

@@ -1,9 +1,9 @@
 # Updating your panda
 
-Panda should update automatically via the [Chffr](http://chffr.comma.ai/) app ([apple](https://itunes.apple.com/us/app/chffr-dash-cam-that-remembers/id1146683979) and [android](https://play.google.com/store/apps/details?id=ai.comma.chffr))
+Panda should update automatically via the [openpilot](http://openpilot.comma.ai/).
 
-If it doesn't however,  you can use the following commands on linux or Mac OSX
- `sudo pip install --upgrade pandacan`
-` PYTHONPATH="" sudo python -c "import panda; panda.flash_release()"`
-
-(You'll need to have `pip` and `sudo` installed.)
+On Linux or Mac OSX, you can manually update it using:
+```
+sudo pip install --upgrade pandacan`
+PYTHONPATH="" sudo python -c "import panda; panda.flash_release()"`
+```

VERSION

@@ -1 +1 @@
-v1.5.3
+v1.5.9

__init__.py

@@ -1 +1 @@
-from .python import Panda, PandaWifiStreaming, PandaDFU, ESPROM, CesantaFlasher, flash_release, BASEDIR, ensure_st_up_to_date, build_st, PandaSerial
+from .python import Panda, PandaWifiStreaming, PandaDFU, ESPROM, CesantaFlasher, flash_release, BASEDIR, ensure_st_up_to_date, build_st, PandaSerial  # noqa: F401

board/README.md

@@ -4,6 +4,7 @@ Dependencies
 **Mac**
 
 ```
+xcode-select --install
 ./get_sdk_mac.sh
 ```
 

board/board.h

@@ -7,9 +7,12 @@
 // ///// Board definition and detection ///// //
 #include "drivers/harness.h"
 #ifdef PANDA
+  #include "drivers/fan.h"
+  #include "drivers/rtc.h"
   #include "boards/white.h"
   #include "boards/grey.h"
   #include "boards/black.h"
+  #include "boards/uno.h"
 #else
   #include "boards/pedal.h"
 #endif
@@ -23,6 +26,9 @@ void detect_board_type(void) {
     } else if(detect_with_pull(GPIOA, 13, PULL_DOWN)) { // Rev AB deprecated, so no pullup means black. In REV C, A13 is pulled up to 5V with a 10K
       hw_type = HW_TYPE_GREY_PANDA;
       current_board = &board_grey;
+    } else if(!detect_with_pull(GPIOB, 15, PULL_UP)) {
+      hw_type = HW_TYPE_UNO;
+      current_board = &board_uno;
     } else {
       hw_type = HW_TYPE_BLACK_PANDA;
       current_board = &board_black;
@@ -60,6 +66,27 @@ void detect_configuration(void) {
 }
 
 // ///// Board functions ///// //
+// TODO: Make these config options in the board struct
 bool board_has_gps(void) {
-  return ((hw_type == HW_TYPE_GREY_PANDA) || (hw_type == HW_TYPE_BLACK_PANDA));
+  return ((hw_type == HW_TYPE_GREY_PANDA) || (hw_type == HW_TYPE_BLACK_PANDA) || (hw_type == HW_TYPE_UNO));
+}
+
+bool board_has_gmlan(void) {
+  return ((hw_type == HW_TYPE_WHITE_PANDA) || (hw_type == HW_TYPE_GREY_PANDA));
+}
+
+bool board_has_obd(void) {
+  return ((hw_type == HW_TYPE_BLACK_PANDA) || (hw_type == HW_TYPE_UNO));
+}
+
+bool board_has_lin(void) {
+  return ((hw_type == HW_TYPE_WHITE_PANDA) || (hw_type == HW_TYPE_GREY_PANDA));
+}
+
+bool board_has_rtc(void) {
+  return (hw_type == HW_TYPE_UNO);
+}
+
+bool board_has_relay(void) {
+  return ((hw_type == HW_TYPE_BLACK_PANDA) || (hw_type == HW_TYPE_UNO));
 }

board/board_declarations.h

@@ -8,6 +8,9 @@ typedef void (*board_set_esp_gps_mode)(uint8_t mode);
 typedef void (*board_set_can_mode)(uint8_t mode);
 typedef void (*board_usb_power_mode_tick)(uint64_t tcnt);
 typedef bool (*board_check_ignition)(void);
+typedef uint32_t (*board_read_current)(void);
+typedef void (*board_set_ir_power)(uint8_t percentage);
+typedef void (*board_set_fan_power)(uint8_t percentage);
 
 struct board {
   const char *board_type;
@@ -21,6 +24,9 @@ struct board {
   board_set_can_mode set_can_mode;
   board_usb_power_mode_tick usb_power_mode_tick;
   board_check_ignition check_ignition;
+  board_read_current read_current;
+  board_set_ir_power set_ir_power;
+  board_set_fan_power set_fan_power;
 };
 
 // ******************* Definitions ********************
@@ -30,6 +36,7 @@ struct board {
 #define HW_TYPE_GREY_PANDA 2U
 #define HW_TYPE_BLACK_PANDA 3U
 #define HW_TYPE_PEDAL 4U
+#define HW_TYPE_UNO 5U
 
 // LED colors
 #define LED_RED 0U
@@ -55,3 +62,11 @@ struct board {
 
 // ********************* Globals **********************
 uint8_t usb_power_mode = USB_POWER_NONE;
+
+// ************ Board function prototypes *************
+bool board_has_gps(void);
+bool board_has_gmlan(void);
+bool board_has_obd(void);
+bool board_has_lin(void);
+bool board_has_rtc(void);
+bool board_has_relay(void);

board/boards/black.h

@@ -23,7 +23,8 @@ void black_enable_can_transciever(uint8_t transciever, bool enabled) {
 }
 
 void black_enable_can_transcievers(bool enabled) {
-  for(uint8_t i=1U; i<=4U; i++){
+  uint8_t t1 = enabled ? 1U : 2U;  // leave transciever 1 enabled to detect CAN ignition
+  for(uint8_t i=t1; i<=4U; i++) {
     black_enable_can_transciever(i, enabled);
   }
 }
@@ -132,6 +133,19 @@ bool black_check_ignition(void){
   return harness_check_ignition();
 }
 
+uint32_t black_read_current(void){
+  // No current sense on black panda
+  return 0U;
+}
+
+void black_set_ir_power(uint8_t percentage){
+  UNUSED(percentage);
+}
+
+void black_set_fan_power(uint8_t percentage){
+  UNUSED(percentage);
+}
+
 void black_init(void) {
   common_init_gpio();
 
@@ -153,9 +167,6 @@ void black_init(void) {
   set_gpio_output(GPIOC, 10, 1);
   set_gpio_output(GPIOC, 11, 1);
 
-  // C8: FAN aka TIM3_CH3
-  set_gpio_alternate(GPIOC, 8, GPIO_AF2_TIM3);
-
   // Turn on GPS load switch.
   black_set_gps_load_switch(true);
 
@@ -213,5 +224,8 @@ const board board_black = {
   .set_esp_gps_mode = black_set_esp_gps_mode,
   .set_can_mode = black_set_can_mode,
   .usb_power_mode_tick = black_usb_power_mode_tick,
-  .check_ignition = black_check_ignition
+  .check_ignition = black_check_ignition,
+  .read_current = black_read_current,
+  .set_fan_power = black_set_fan_power,
+  .set_ir_power = black_set_ir_power
 };

board/boards/common.h

@@ -58,16 +58,18 @@ void peripherals_init(void){
   #endif
   RCC->APB1ENR |= RCC_APB1ENR_DACEN;
   RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;  // main counter
-  RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;  // slow loop and pedal
-  RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;  // gmlan_alt
+  RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;  // pedal and fan PWM
+  RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;  // gmlan_alt and IR PWM
   //RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;
   //RCC->APB1ENR |= RCC_APB1ENR_TIM6EN;
+  RCC->APB1ENR |= RCC_APB1ENR_PWREN;   // for RTC config
   RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
   RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
   //RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
   RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
   RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
   RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+  RCC->APB2ENR |= RCC_APB2ENR_TIM9EN;  // slow loop
 }
 
 // Detection with internal pullup

board/boards/grey.h

@@ -14,5 +14,8 @@ const board board_grey = {
   .set_esp_gps_mode = white_set_esp_gps_mode,
   .set_can_mode = white_set_can_mode,
   .usb_power_mode_tick = white_usb_power_mode_tick,
-  .check_ignition = white_check_ignition
+  .check_ignition = white_check_ignition,
+  .read_current = white_read_current,
+  .set_fan_power = white_set_fan_power,
+  .set_ir_power = white_set_ir_power
 };

board/boards/pedal.h

@@ -60,6 +60,19 @@ bool pedal_check_ignition(void){
   return false;
 }
 
+uint32_t pedal_read_current(void){
+  // No current sense on pedal
+  return 0U;
+}
+
+void pedal_set_ir_power(uint8_t percentage){
+  UNUSED(percentage);
+}
+
+void pedal_set_fan_power(uint8_t percentage){
+  UNUSED(percentage);
+}
+
 void pedal_init(void) {
   common_init_gpio();
 
@@ -93,4 +106,7 @@ const board board_pedal = {
   .set_can_mode = pedal_set_can_mode,
   .usb_power_mode_tick = pedal_usb_power_mode_tick,
   .check_ignition = pedal_check_ignition,
+  .read_current = pedal_read_current,
+  .set_fan_power = pedal_set_fan_power,
+  .set_ir_power = pedal_set_ir_power
 };

board/boards/uno.h

@@ -0,0 +1,247 @@
+// ///////////// //
+// Uno + Harness //
+// ///////////// //
+
+void uno_enable_can_transciever(uint8_t transciever, bool enabled) {
+  switch (transciever){
+    case 1U:
+      set_gpio_output(GPIOC, 1, !enabled);
+      break;
+    case 2U:
+      set_gpio_output(GPIOC, 13, !enabled);
+      break;
+    case 3U:
+      set_gpio_output(GPIOA, 0, !enabled);
+      break;
+    case 4U:
+      set_gpio_output(GPIOB, 10, !enabled);
+      break;
+    default:
+      puts("Invalid CAN transciever ("); puth(transciever); puts("): enabling failed\n");
+      break;
+  }
+}
+
+void uno_enable_can_transcievers(bool enabled) {
+  for(uint8_t i=1U; i<=4U; i++){
+    uno_enable_can_transciever(i, enabled);
+  }
+}
+
+void uno_set_led(uint8_t color, bool enabled) {
+  switch (color){
+    case LED_RED:
+      set_gpio_output(GPIOC, 9, !enabled);
+      break;
+     case LED_GREEN:
+      set_gpio_output(GPIOC, 7, !enabled);
+      break;
+    case LED_BLUE:
+      set_gpio_output(GPIOC, 6, !enabled);
+      break;
+    default:
+      break;
+  }
+}
+
+void uno_set_gps_load_switch(bool enabled) {
+  set_gpio_output(GPIOC, 12, enabled);
+}
+
+void uno_set_usb_power_mode(uint8_t mode) {
+  UNUSED(mode);
+  puts("Setting USB mode makes no sense on UNO\n");
+}
+
+void uno_set_esp_gps_mode(uint8_t mode) {
+  switch (mode) {
+    case ESP_GPS_DISABLED:
+      // GPS OFF
+      set_gpio_output(GPIOB, 1, 0);
+      set_gpio_output(GPIOC, 5, 0);
+      uno_set_gps_load_switch(false);
+      break;
+    case ESP_GPS_ENABLED:
+      // GPS ON
+      set_gpio_output(GPIOB, 1, 1);
+      set_gpio_output(GPIOC, 5, 1);
+      uno_set_gps_load_switch(true);
+      break;
+    case ESP_GPS_BOOTMODE:
+      set_gpio_output(GPIOB, 1, 1);
+      set_gpio_output(GPIOC, 5, 0);
+      uno_set_gps_load_switch(true);
+      break;
+    default:
+      puts("Invalid ESP/GPS mode\n");
+      break;
+  }
+}
+
+void uno_set_can_mode(uint8_t mode){
+  switch (mode) {
+    case CAN_MODE_NORMAL:
+    case CAN_MODE_OBD_CAN2:
+      if ((bool)(mode == CAN_MODE_NORMAL) != (bool)(car_harness_status == HARNESS_STATUS_NORMAL)) {
+        // B12,B13: disable OBD mode
+        set_gpio_mode(GPIOB, 12, MODE_INPUT);
+        set_gpio_mode(GPIOB, 13, MODE_INPUT);
+
+        // B5,B6: normal CAN2 mode
+        set_gpio_alternate(GPIOB, 5, GPIO_AF9_CAN2);
+        set_gpio_alternate(GPIOB, 6, GPIO_AF9_CAN2);
+      } else {
+        // B5,B6: disable normal CAN2 mode
+        set_gpio_mode(GPIOB, 5, MODE_INPUT);
+        set_gpio_mode(GPIOB, 6, MODE_INPUT);
+
+        // B12,B13: OBD mode
+        set_gpio_alternate(GPIOB, 12, GPIO_AF9_CAN2);
+        set_gpio_alternate(GPIOB, 13, GPIO_AF9_CAN2);
+      }
+      break;
+    default:
+      puts("Tried to set unsupported CAN mode: "); puth(mode); puts("\n");
+      break;
+  }
+}
+
+void uno_set_bootkick(bool enabled){
+  set_gpio_output(GPIOB, 14, !enabled);
+}
+
+void uno_usb_power_mode_tick(uint64_t tcnt){
+  if(tcnt == 3U){
+    uno_set_bootkick(false);
+  }
+}
+
+bool uno_check_ignition(void){
+  // ignition is checked through harness
+  return harness_check_ignition();
+}
+
+void uno_set_usb_switch(bool phone){
+  set_gpio_output(GPIOB, 3, phone);
+}
+
+void uno_set_ir_power(uint8_t percentage){
+  pwm_set(TIM4, 2, percentage);
+}
+
+void uno_set_fan_power(uint8_t percentage){
+  // Enable fan power only if percentage is non-zero.
+  set_gpio_output(GPIOA, 1, (percentage != 0U));
+  fan_set_power(percentage);
+}
+
+uint32_t uno_read_current(void){
+  // No current sense on Uno
+  return 0U;
+}
+
+void uno_init(void) {
+  common_init_gpio();
+
+  // A8,A15: normal CAN3 mode
+  set_gpio_alternate(GPIOA, 8, GPIO_AF11_CAN3);
+  set_gpio_alternate(GPIOA, 15, GPIO_AF11_CAN3);
+
+  // C0: OBD_SBU1 (orientation detection)
+  // C3: OBD_SBU2 (orientation detection)
+  set_gpio_mode(GPIOC, 0, MODE_ANALOG);
+  set_gpio_mode(GPIOC, 3, MODE_ANALOG);
+
+  // C10: OBD_SBU1_RELAY (harness relay driving output)
+  // C11: OBD_SBU2_RELAY (harness relay driving output)
+  set_gpio_mode(GPIOC, 10, MODE_OUTPUT);
+  set_gpio_mode(GPIOC, 11, MODE_OUTPUT);
+  set_gpio_output_type(GPIOC, 10, OUTPUT_TYPE_OPEN_DRAIN);
+  set_gpio_output_type(GPIOC, 11, OUTPUT_TYPE_OPEN_DRAIN);
+  set_gpio_output(GPIOC, 10, 1);
+  set_gpio_output(GPIOC, 11, 1);
+
+  // C8: FAN PWM aka TIM3_CH3
+  set_gpio_alternate(GPIOC, 8, GPIO_AF2_TIM3);
+
+  // Turn on GPS load switch.
+  uno_set_gps_load_switch(true);
+
+  // Turn on phone regulator
+  set_gpio_output(GPIOB, 4, 1);
+
+  // Initialize IR PWM and set to 0%
+  set_gpio_alternate(GPIOB, 7, GPIO_AF2_TIM4);
+  pwm_init(TIM4, 2);
+  uno_set_ir_power(0U);
+
+  // Initialize fan and set to 0%
+  fan_init();
+  uno_set_fan_power(0U);
+
+  // Initialize harness
+  harness_init();
+
+  // Initialize RTC
+  rtc_init();
+
+  // Enable CAN transcievers
+  uno_enable_can_transcievers(true);
+
+  // Disable LEDs
+  uno_set_led(LED_RED, false);
+  uno_set_led(LED_GREEN, false);
+  uno_set_led(LED_BLUE, false);
+
+  // Set normal CAN mode
+  uno_set_can_mode(CAN_MODE_NORMAL);
+
+  // flip CAN0 and CAN2 if we are flipped
+  if (car_harness_status == HARNESS_STATUS_NORMAL) {
+    can_flip_buses(0, 2);
+  }
+
+  // init multiplexer
+  can_set_obd(car_harness_status, false);
+
+  // Switch to phone usb mode if harness connection is powered by less than 7V
+  if(adc_get_voltage() < 7000U){
+    uno_set_usb_switch(true);
+  } else {
+    uno_set_usb_switch(false);
+  }
+
+  // Bootkick phone
+  uno_set_bootkick(true);
+}
+
+const harness_configuration uno_harness_config = {
+  .has_harness = true,
+  .GPIO_SBU1 = GPIOC,
+  .GPIO_SBU2 = GPIOC,
+  .GPIO_relay_normal = GPIOC,
+  .GPIO_relay_flipped = GPIOC,
+  .pin_SBU1 = 0,
+  .pin_SBU2 = 3,
+  .pin_relay_normal = 10,
+  .pin_relay_flipped = 11,
+  .adc_channel_SBU1 = 10,
+  .adc_channel_SBU2 = 13
+};
+
+const board board_uno = {
+  .board_type = "Uno",
+  .harness_config = &uno_harness_config,
+  .init = uno_init,
+  .enable_can_transciever = uno_enable_can_transciever,
+  .enable_can_transcievers = uno_enable_can_transcievers,
+  .set_led = uno_set_led,
+  .set_usb_power_mode = uno_set_usb_power_mode,
+  .set_esp_gps_mode = uno_set_esp_gps_mode,
+  .set_can_mode = uno_set_can_mode,
+  .usb_power_mode_tick = uno_usb_power_mode_tick,
+  .check_ignition = uno_check_ignition,
+  .read_current = uno_read_current,
+  .set_fan_power = uno_set_fan_power,
+  .set_ir_power = uno_set_ir_power
+};

board/boards/white.h

@@ -20,9 +20,11 @@ void white_enable_can_transciever(uint8_t transciever, bool enabled) {
 }
 
 void white_enable_can_transcievers(bool enabled) {
-  for(uint8_t i=1; i<=3U; i++)
+  uint8_t t1 = enabled ? 1U : 2U;  // leave transciever 1 enabled to detect CAN ignition
+  for(uint8_t i=t1; i<=3U; i++) {
     white_enable_can_transciever(i, enabled);
   }
+}
 
 void white_set_led(uint8_t color, bool enabled) {
   switch (color){
@@ -150,6 +152,10 @@ void white_set_can_mode(uint8_t mode){
   }
 }
 
+uint32_t white_read_current(void){
+  return adc_get(ADCCHAN_CURRENT);
+}
+
 uint64_t marker = 0;
 void white_usb_power_mode_tick(uint64_t tcnt){
 
@@ -158,7 +164,7 @@ void white_usb_power_mode_tick(uint64_t tcnt){
   #define CURRENT_THRESHOLD 0xF00U
   #define CLICKS 5U // 5 seconds to switch modes
 
-  uint32_t current = adc_get(ADCCHAN_CURRENT);
+  uint32_t current = white_read_current();
 
   // ~0x9a = 500 ma
   // puth(current); puts("\n");
@@ -217,6 +223,14 @@ void white_usb_power_mode_tick(uint64_t tcnt){
 #endif
 }
 
+void white_set_ir_power(uint8_t percentage){
+  UNUSED(percentage);
+}
+
+void white_set_fan_power(uint8_t percentage){
+  UNUSED(percentage);
+}
+
 bool white_check_ignition(void){
   // ignition is on PA1
   return !get_gpio_input(GPIOA, 1);
@@ -315,5 +329,8 @@ const board board_white = {
   .set_esp_gps_mode = white_set_esp_gps_mode,
   .set_can_mode = white_set_can_mode,
   .usb_power_mode_tick = white_usb_power_mode_tick,
-  .check_ignition = white_check_ignition
+  .check_ignition = white_check_ignition,
+  .read_current = white_read_current,
+  .set_fan_power = white_set_fan_power,
+  .set_ir_power = white_set_ir_power
 };

board/bootstub.c

@@ -33,6 +33,7 @@ const board *current_board;
 #include "drivers/clock.h"
 #include "drivers/llgpio.h"
 #include "drivers/adc.h"
+#include "drivers/pwm.h"
 
 #include "board.h"
 

board/drivers/can.h

@@ -30,6 +30,9 @@ void can_init_all(void);
 void can_send(CAN_FIFOMailBox_TypeDef *to_push, uint8_t bus_number);
 bool can_pop(can_ring *q, CAN_FIFOMailBox_TypeDef *elem);
 
+// Ignition detected from CAN meessages
+bool ignition_can = false;
+
 // end API
 
 #define ALL_CAN_SILENT 0xFF
@@ -173,7 +176,7 @@ void can_flip_buses(uint8_t bus1, uint8_t bus2){
 
 // TODO: Cleanup with new abstraction
 void can_set_gmlan(uint8_t bus) {
-  if(hw_type != HW_TYPE_BLACK_PANDA){
+  if(board_has_gmlan()){
     // first, disable GMLAN on prev bus
     uint8_t prev_bus = can_num_lookup[3];
     if (bus != prev_bus) {
@@ -226,7 +229,7 @@ void can_set_obd(uint8_t harness_orientation, bool obd){
   } else {
     puts("setting CAN2 to be normal\n");
   }
-  if(hw_type == HW_TYPE_BLACK_PANDA){
+  if(board_has_obd()){
     if(obd != (bool)(harness_orientation == HARNESS_STATUS_NORMAL)){
         // B5,B6: disable normal mode
         set_gpio_mode(GPIOB, 5, MODE_INPUT);
@@ -243,7 +246,7 @@ void can_set_obd(uint8_t harness_orientation, bool obd){
         set_gpio_mode(GPIOB, 13, MODE_INPUT);
     }
   } else {
-    puts("OBD CAN not available on non-black panda\n");
+    puts("OBD CAN not available on this board\n");
   }
 }
 
@@ -332,6 +335,36 @@ void process_can(uint8_t can_number) {
   }
 }
 
+void ignition_can_hook(CAN_FIFOMailBox_TypeDef *to_push) {
+
+  int bus = GET_BUS(to_push);
+  int addr = GET_ADDR(to_push);
+  int len = GET_LEN(to_push);
+
+  if (bus == 0) {
+    // GM exception
+    if ((addr == 0x1F1) && (len == 8)) {
+      //Bit 5 is ignition "on"
+      ignition_can = (GET_BYTE(to_push, 0) & 0x20) != 0;
+    }
+    // Tesla exception
+    if ((addr == 0x348) && (len == 8)) {
+      // GTW_status
+      ignition_can = (GET_BYTE(to_push, 0) & 0x1) != 0;
+    }
+    // Cadillac exception
+    if ((addr == 0x160) && (len == 5)) {
+      // this message isn't all zeros when ignition is on
+      ignition_can = GET_BYTES_04(to_push) != 0;
+    }
+    // VW exception
+    if ((addr == 0x3C0) && (len == 4)) {
+     // VW Terminal 15 (ignition-on) state
+     ignition_can  = (GET_BYTE(to_push, 2) & 0x2) != 0;
+    }
+  }
+}
+
 // CAN receive handlers
 // blink blue when we are receiving CAN messages
 void can_rx(uint8_t can_number) {
@@ -365,6 +398,7 @@ void can_rx(uint8_t can_number) {
     }
 
     safety_rx_hook(&to_push);
+    ignition_can_hook(&to_push);
 
     current_board->set_led(LED_BLUE, true);
     can_send_errs += can_push(&can_rx_q, &to_push) ? 0U : 1U;

board/drivers/fan.h

@@ -0,0 +1,36 @@
+void fan_init(void){
+    // Init PWM speed control
+    pwm_init(TIM3, 3);
+
+    // Init TACH interrupt
+    SYSCFG->EXTICR[0] = SYSCFG_EXTICR1_EXTI2_PD;
+    EXTI->IMR |= (1U << 2);
+    EXTI->RTSR |= (1U << 2);
+    EXTI->FTSR |= (1U << 2);
+    NVIC_EnableIRQ(EXTI2_IRQn);
+}
+
+void fan_set_power(uint8_t percentage){
+  pwm_set(TIM3, 3, percentage);
+}
+
+uint16_t fan_tach_counter = 0U;
+uint16_t fan_rpm = 0U;
+
+// Can be way more acurate than this, but this is probably good enough for our purposes.
+
+// Call this every second
+void fan_tick(void){
+    // 4 interrupts per rotation
+    fan_rpm = fan_tach_counter * 15U;
+    fan_tach_counter = 0U;
+}
+
+// TACH interrupt handler
+void EXTI2_IRQHandler(void) {
+    volatile unsigned int pr = EXTI->PR & (1U << 2);
+    if ((pr & (1U << 2)) != 0U) {
+        fan_tach_counter++;
+    }
+    EXTI->PR = (1U << 2);
+}

board/drivers/pwm.h

@@ -0,0 +1,55 @@
+#define PWM_COUNTER_OVERFLOW 2000U // To get ~50kHz
+
+void pwm_init(TIM_TypeDef *TIM, uint8_t channel){
+    // Enable timer and auto-reload
+    TIM->CR1 = TIM_CR1_CEN | TIM_CR1_ARPE;
+
+    // Set channel as PWM mode 1 and enable output
+    switch(channel){
+        case 1U:
+            TIM->CCMR1 |= (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE);
+            TIM->CCER |= TIM_CCER_CC1E;
+            break;
+        case 2U:
+            TIM->CCMR1 |= (TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2PE);
+            TIM->CCER |= TIM_CCER_CC2E;
+            break;
+        case 3U:
+            TIM->CCMR2 |= (TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3PE);
+            TIM->CCER |= TIM_CCER_CC3E;
+            break;
+        case 4U:
+            TIM->CCMR2 |= (TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4PE);
+            TIM->CCER |= TIM_CCER_CC4E;
+            break;
+        default:
+            break;
+    }
+
+    // Set max counter value
+    TIM->ARR = PWM_COUNTER_OVERFLOW;
+
+    // Update registers and clear counter
+    TIM->EGR |= TIM_EGR_UG;
+}
+
+// TODO: Implement for 32-bit timers
+void pwm_set(TIM_TypeDef *TIM, uint8_t channel, uint8_t percentage){
+    uint16_t comp_value = (((uint16_t) percentage * PWM_COUNTER_OVERFLOW) / 100U);
+    switch(channel){
+        case 1U:
+            TIM->CCR1 = comp_value;
+            break;
+        case 2U:
+            TIM->CCR2 = comp_value;
+            break;
+        case 3U:
+            TIM->CCR3 = comp_value;
+            break;
+        case 4U:
+            TIM->CCR4 = comp_value;
+            break;
+        default:
+            break;
+    }
+}

board/drivers/rtc.h

@@ -0,0 +1,108 @@
+#define RCC_BDCR_OPTIONS (RCC_BDCR_RTCEN | RCC_BDCR_RTCSEL_0 | RCC_BDCR_LSEON)
+#define RCC_BDCR_MASK (RCC_BDCR_RTCEN | RCC_BDCR_RTCSEL | RCC_BDCR_LSEMOD | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)
+
+#define YEAR_OFFSET 2000U
+
+typedef struct __attribute__((packed)) timestamp_t {
+  uint16_t year;
+  uint8_t month;
+  uint8_t day;
+  uint8_t weekday;
+  uint8_t hour;
+  uint8_t minute;
+  uint8_t second;
+} timestamp_t;
+
+uint8_t to_bcd(uint16_t value){
+    return (((value / 10U) & 0x0FU) << 4U) | ((value % 10U) & 0x0FU);
+}
+
+uint16_t from_bcd(uint8_t value){
+    return (((value & 0xF0U) >> 4U) * 10U) + (value & 0x0FU);
+}
+
+void rtc_init(void){
+    if(board_has_rtc()){
+        // Initialize RTC module and clock if not done already.
+        if((RCC->BDCR & RCC_BDCR_MASK) != RCC_BDCR_OPTIONS){
+            puts("Initializing RTC\n");
+            // Reset backup domain
+            RCC->BDCR |= RCC_BDCR_BDRST;
+
+            // Disable write protection
+            PWR->CR |= PWR_CR_DBP;
+
+            // Clear backup domain reset
+            RCC->BDCR &= ~(RCC_BDCR_BDRST);
+
+            // Set RTC options
+            RCC->BDCR = RCC_BDCR_OPTIONS | (RCC->BDCR & (~RCC_BDCR_MASK));
+
+            // Enable write protection
+            PWR->CR &= ~(PWR_CR_DBP);
+        }
+    }
+}
+
+void rtc_set_time(timestamp_t time){
+    if(board_has_rtc()){
+        puts("Setting RTC time\n");
+
+        // Disable write protection
+        PWR->CR |= PWR_CR_DBP;
+        RTC->WPR = 0xCA;
+        RTC->WPR = 0x53;
+
+        // Enable initialization mode
+        RTC->ISR |= RTC_ISR_INIT;
+        while((RTC->ISR & RTC_ISR_INITF) == 0){}
+        
+        // Set time
+        RTC->TR = (to_bcd(time.hour) << RTC_TR_HU_Pos) | (to_bcd(time.minute) << RTC_TR_MNU_Pos) | (to_bcd(time.second) << RTC_TR_SU_Pos);
+        RTC->DR = (to_bcd(time.year - YEAR_OFFSET) << RTC_DR_YU_Pos) | (time.weekday << RTC_DR_WDU_Pos) | (to_bcd(time.month) << RTC_DR_MU_Pos) | (to_bcd(time.day) << RTC_DR_DU_Pos);
+
+        // Set options
+        RTC->CR = 0U;
+        
+        // Disable initalization mode
+        RTC->ISR &= ~(RTC_ISR_INIT);
+
+        // Wait for synchronization
+        while((RTC->ISR & RTC_ISR_RSF) == 0){}
+
+        // Re-enable write protection
+        RTC->WPR = 0x00;
+        PWR->CR &= ~(PWR_CR_DBP);
+    }
+}
+
+timestamp_t rtc_get_time(void){
+    timestamp_t result;
+    // Init with zero values in case there is no RTC running
+    result.year = 0U;
+    result.month = 0U;
+    result.day = 0U;
+    result.weekday = 0U;
+    result.hour = 0U;
+    result.minute = 0U;
+    result.second = 0U;
+
+    if(board_has_rtc()){
+        // Wait until the register sync flag is set
+        while((RTC->ISR & RTC_ISR_RSF) == 0){}
+
+        // Read time and date registers. Since our HSE > 7*LSE, this should be fine.
+        uint32_t time = RTC->TR;
+        uint32_t date = RTC->DR;
+
+        // Parse values        
+        result.year = from_bcd((date & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos) + YEAR_OFFSET;
+        result.month = from_bcd((date & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos);
+        result.day = from_bcd((date & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos);
+        result.weekday = ((date & RTC_DR_WDU) >> RTC_DR_WDU_Pos);
+        result.hour = from_bcd((time & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos);
+        result.minute = from_bcd((time & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
+        result.second = from_bcd((time & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
+    }
+    return result;
+}

board/get_sdk.sh

@@ -1,3 +1,3 @@
 #!/bin/bash
 sudo apt-get install gcc-arm-none-eabi python-pip
-sudo pip2 install libusb1 pycrypto requests
+sudo pip install libusb1 pycrypto requests

board/get_sdk_mac.sh

@@ -2,4 +2,4 @@
 # Need formula for gcc
 brew tap ArmMbed/homebrew-formulae
 brew install python dfu-util arm-none-eabi-gcc
-pip2 install libusb1 pycrypto requests
+pip install --user libusb1 pycrypto requests

board/inc/cmsis_compiler.h

@@ -0,0 +1,284 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
+

board/inc/cmsis_version.h

@@ -0,0 +1,40 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.3
+ * @date     24. June 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 3U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
+

board/inc/core_cm3.h

@@ -1,40 +1,30 @@
 /**************************************************************************//**
  * @file     core_cm3.h
  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V4.30
- * @date     20. October 2015
+ * @version  V5.1.0
+ * @date     13. March 2019
  ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
  *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
 
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#elif defined (__clang__)
   #pragma clang system_header   /* treat file as system include file */
 #endif
 
@@ -70,53 +60,15 @@
   @{
  */
 
+#include "cmsis_version.h"
+
 /*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
 #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM3_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (0x03U)                                      /*!< Cortex-M Core */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
-  #define __STATIC_INLINE  static inline
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
 
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
-  #define __STATIC_INLINE  static inline
-
-#else
-  #error Unknown compiler
-#endif
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
 
 /** __FPU_USED indicates whether an FPU is used or not.
     This core does not support an FPU at all
@@ -129,7 +81,7 @@
   #endif
 
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
+  #if defined __ARM_FP
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
@@ -143,7 +95,7 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __TMS470__ )
+#elif defined ( __TI_ARM__ )
   #if defined __TI_VFP_SUPPORT__
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
@@ -160,8 +112,8 @@
 
 #endif
 
-#include "core_cmInstr.h"                /* Core Instruction Access */
-#include "core_cmFunc.h"                 /* Core Function Access */
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
 
 #ifdef __cplusplus
 }
@@ -191,7 +143,7 @@
   #endif
 
   #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4U
+    #define __NVIC_PRIO_BITS          3U
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
 
@@ -308,9 +260,11 @@ typedef union
   struct
   {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
@@ -336,12 +290,15 @@ typedef union
 #define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
 #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
 
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
 
 #define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
 #define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 
@@ -385,7 +342,7 @@ typedef struct
   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
         uint32_t RESERVED0[24U];
   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
+        uint32_t RESERVED1[24U];
   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
         uint32_t RESERVED2[24U];
   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
@@ -487,7 +444,7 @@ typedef struct
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 
 /* SCB Vector Table Offset Register Definitions */
-#if (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
 #define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
 
@@ -602,6 +559,60 @@ typedef struct
 #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
 
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
 /* SCB Hard Fault Status Register Definitions */
 #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
@@ -645,7 +656,7 @@ typedef struct
 {
         uint32_t RESERVED0[1U];
   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
 #else
         uint32_t RESERVED1[1U];
@@ -657,6 +668,12 @@ typedef struct
 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
 
 /* Auxiliary Control Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
 
 #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
@@ -666,6 +683,7 @@ typedef struct
 
 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+#endif
 
 /*@} end of group CMSIS_SCnotSCB */
 
@@ -746,10 +764,7 @@ typedef struct
   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
         uint32_t RESERVED2[15U];
   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED3[32U];
         uint32_t RESERVED4[43U];
   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
@@ -770,7 +785,7 @@ typedef struct
 
 /* ITM Trace Privilege Register Definitions */
 #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
 
 /* ITM Trace Control Register Definitions */
 #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
@@ -800,18 +815,6 @@ typedef struct
 #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
 #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
 
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
 /* ITM Lock Status Register Definitions */
 #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
@@ -984,7 +987,7 @@ typedef struct
  */
 typedef struct
 {
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
         uint32_t RESERVED0[2U];
   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
@@ -995,7 +998,7 @@ typedef struct
   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
         uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
         uint32_t RESERVED4[1U];
@@ -1044,13 +1047,13 @@ typedef struct
 
 /* TPI Integration ETM Data Register Definitions (FIFO0) */
 #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
 
 #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
 
 #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
 
 #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
@@ -1065,18 +1068,21 @@ typedef struct
 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
 
 /* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
 
 /* TPI Integration ITM Data Register Definitions (FIFO1) */
 #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
 
 #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
 
 #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
 
 #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
@@ -1091,12 +1097,15 @@ typedef struct
 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
 
 /* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
 
 /* TPI Integration Mode Control Register Definitions */
 #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
 
 /* TPI DEVID Register Definitions */
 #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
@@ -1118,16 +1127,16 @@ typedef struct
 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
 
 /* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
 #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
 
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
 /*@}*/ /* end of group CMSIS_TPI */
 
 
-#if (__MPU_PRESENT == 1U)
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
@@ -1153,6 +1162,8 @@ typedef struct
   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
 } MPU_Type;
 
+#define MPU_TYPE_RALIASES                  4U
+
 /* MPU Type Register Definitions */
 #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
@@ -1337,18 +1348,18 @@ typedef struct
 /**
   \brief   Mask and shift a bit field value for use in a register bit range.
   \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
   \return           Masked and shifted value.
 */
-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
 
 /**
   \brief     Mask and shift a register value to extract a bit filed value.
   \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
   \return           Masked and shifted bit field value.
 */
-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
 
 /*@} end of group CMSIS_core_bitfield */
 
@@ -1360,7 +1371,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Cortex-M3 Hardware */
+/* Memory mapping of Core Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
@@ -1379,7 +1390,7 @@ typedef struct
 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
 
-#if (__MPU_PRESENT == 1U)
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
 #endif
@@ -1410,6 +1421,45 @@ typedef struct
   @{
  */
 
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
 /**
   \brief   Set Priority Grouping
   \details Sets the priority grouping field using the required unlock sequence.
@@ -1419,7 +1469,7 @@ typedef struct
            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
   \param [in]      PriorityGroup  Priority grouping field.
  */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
@@ -1428,7 +1478,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
   reg_value  =  (reg_value                                   |
                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
   SCB->AIRCR =  reg_value;
 }
 
@@ -1438,121 +1488,180 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
   \details Reads the priority grouping field from the NVIC Interrupt Controller.
   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
 {
   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 }
 
 
 /**
-  \brief   Enable External Interrupt
-  \details Enables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
 /**
-  \brief   Disable External Interrupt
-  \details Disables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
   {
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
 }
 
 
 /**
   \brief   Get Pending Interrupt
-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
-  \param [in]      IRQn  Interrupt number.
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
   \return             0  Interrupt status is not pending.
   \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
 /**
   \brief   Set Pending Interrupt
-  \details Sets the pending bit of an external interrupt.
-  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
   {
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
 /**
   \brief   Clear Pending Interrupt
-  \details Clears the pending bit of an external interrupt.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
   {
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
 /**
   \brief   Get Active Interrupt
-  \details Reads the active register in NVIC and returns the active bit.
-  \param [in]      IRQn  Interrupt number.
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
   \return             0  Interrupt status is not active.
   \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
   {
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    return(0U);
+  }
 }
 
 
 /**
   \brief   Set Interrupt Priority
-  \details Sets the priority of an interrupt.
-  \note    The priority cannot be set for every core interrupt.
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
   \param [in]      IRQn  Interrupt number.
   \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-  if ((int32_t)(IRQn) < 0)
+  if ((int32_t)(IRQn) >= 0)
   {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
   }
   else
   {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
   }
 }
 
 
 /**
   \brief   Get Interrupt Priority
-  \details Reads the priority of an interrupt.
-           The interrupt number can be positive to specify an external (device specific) interrupt,
-           or negative to specify an internal (core) interrupt.
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
   \param [in]   IRQn  Interrupt number.
   \return             Interrupt Priority.
                       Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if ((int32_t)(IRQn) < 0)
+  if ((int32_t)(IRQn) >= 0)
   {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
   }
   else
   {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
@@ -1609,11 +1718,43 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
 }
 
 
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t vectors = (uint32_t )SCB->VTOR;
+  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+  /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t vectors = (uint32_t )SCB->VTOR;
+  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
 /**
   \brief   System Reset
   \details Initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 {
   __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                        buffered write are completed before reset */
@@ -1630,6 +1771,39 @@ __STATIC_INLINE void NVIC_SystemReset(void)
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
 
 
 /* ##################################    SysTick function  ############################################ */
@@ -1640,7 +1814,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
   @{
  */
 
-#if (__Vendor_SysTickConfig == 0U)
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
 
 /**
   \brief   System Tick Configuration
@@ -1684,7 +1858,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
  */
 
 extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
 
 /**
@@ -1761,3 +1935,4 @@ __STATIC_INLINE int32_t ITM_CheckChar (void)
 #endif /* __CORE_CM3_H_DEPENDANT */
 
 #endif /* __CMSIS_GENERIC */
+

board/inc/core_cm4.h

@@ -1,40 +1,30 @@
 /**************************************************************************//**
  * @file     core_cm4.h
  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V4.30
- * @date     20. October 2015
+ * @version  V5.1.0
+ * @date     13. March 2019
  ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
  *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
 
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#elif defined (__clang__)
   #pragma clang system_header   /* treat file as system include file */
 #endif
 
@@ -70,60 +60,22 @@
   @{
  */
 
+#include "cmsis_version.h"
+
 /* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
 #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (0x04U)                                      /*!< Cortex-M Core */
-
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
 
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
-  #define __STATIC_INLINE  static inline
-
-#else
-  #error Unknown compiler
-#endif
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
 
 /** __FPU_USED indicates whether an FPU is used or not.
     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
 */
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
       #define __FPU_USED       1U
     #else
       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@@ -134,8 +86,8 @@
   #endif
 
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #if (__FPU_PRESENT == 1)
+  #if defined __ARM_FP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
       #define __FPU_USED       1U
     #else
       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@@ -147,7 +99,7 @@
 
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
       #define __FPU_USED       1U
     #else
       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@@ -159,7 +111,7 @@
 
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
       #define __FPU_USED       1U
     #else
       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@@ -169,9 +121,9 @@
     #define __FPU_USED         0U
   #endif
 
-#elif defined ( __TMS470__ )
+#elif defined ( __TI_ARM__ )
   #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
       #define __FPU_USED       1U
     #else
       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@@ -183,7 +135,7 @@
 
 #elif defined ( __TASKING__ )
   #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
       #define __FPU_USED       1U
     #else
       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@@ -195,7 +147,7 @@
 
 #elif defined ( __CSMC__ )
   #if ( __CSMC__ & 0x400U)
-    #if (__FPU_PRESENT == 1U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
       #define __FPU_USED       1U
     #else
       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@@ -207,9 +159,8 @@
 
 #endif
 
-#include "core_cmInstr.h"                /* Core Instruction Access */
-#include "core_cmFunc.h"                 /* Core Function Access */
-#include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
 
 #ifdef __cplusplus
 }
@@ -244,7 +195,7 @@
   #endif
 
   #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4U
+    #define __NVIC_PRIO_BITS          3U
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
 
@@ -367,11 +318,12 @@ typedef union
   struct
   {
     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
@@ -397,8 +349,8 @@ typedef union
 #define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
 #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
 
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
 
 #define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
@@ -406,6 +358,9 @@ typedef union
 #define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
 #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
 
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
 #define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 
@@ -453,7 +408,7 @@ typedef struct
   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
         uint32_t RESERVED0[24U];
   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
+        uint32_t RESERVED1[24U];
   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
         uint32_t RESERVED2[24U];
   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
@@ -662,6 +617,66 @@ typedef struct
 #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
 
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
 /* SCB Hard Fault Status Register Definitions */
 #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
@@ -807,10 +822,7 @@ typedef struct
   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
         uint32_t RESERVED2[15U];
   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED3[32U];
         uint32_t RESERVED4[43U];
   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
@@ -831,7 +843,7 @@ typedef struct
 
 /* ITM Trace Privilege Register Definitions */
 #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
 
 /* ITM Trace Control Register Definitions */
 #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
@@ -861,18 +873,6 @@ typedef struct
 #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
 #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
 
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
 /* ITM Lock Status Register Definitions */
 #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
@@ -1045,7 +1045,7 @@ typedef struct
  */
 typedef struct
 {
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
         uint32_t RESERVED0[2U];
   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
@@ -1056,7 +1056,7 @@ typedef struct
   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
         uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
         uint32_t RESERVED4[1U];
@@ -1105,13 +1105,13 @@ typedef struct
 
 /* TPI Integration ETM Data Register Definitions (FIFO0) */
 #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
 
 #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
 
 #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
 
 #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
@@ -1126,18 +1126,21 @@ typedef struct
 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
 
 /* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
 
 /* TPI Integration ITM Data Register Definitions (FIFO1) */
 #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
 
 #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
 
 #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
 
 #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
@@ -1152,12 +1155,15 @@ typedef struct
 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
 
 /* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
 
 /* TPI Integration Mode Control Register Definitions */
 #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
 
 /* TPI DEVID Register Definitions */
 #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
@@ -1179,16 +1185,16 @@ typedef struct
 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
 
 /* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
 #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
 
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
 /*@}*/ /* end of group CMSIS_TPI */
 
 
-#if (__MPU_PRESENT == 1U)
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
@@ -1214,6 +1220,8 @@ typedef struct
   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
 } MPU_Type;
 
+#define MPU_TYPE_RALIASES                  4U
+
 /* MPU Type Register Definitions */
 #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
@@ -1280,10 +1288,9 @@ typedef struct
 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
-#endif
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
 
 
-#if (__FPU_PRESENT == 1U)
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_FPU     Floating Point Unit (FPU)
@@ -1302,6 +1309,7 @@ typedef struct
   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
   __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
 } FPU_Type;
 
 /* Floating-Point Context Control Register Definitions */
@@ -1387,8 +1395,12 @@ typedef struct
 #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
 #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
 
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR2: VFP Misc bits Mask */
+
 /*@} end of group CMSIS_FPU */
-#endif
 
 
 /**
@@ -1506,18 +1518,18 @@ typedef struct
 /**
   \brief   Mask and shift a bit field value for use in a register bit range.
   \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
   \return           Masked and shifted value.
 */
-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
 
 /**
   \brief     Mask and shift a register value to extract a bit filed value.
   \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
   \return           Masked and shifted bit field value.
 */
-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
 
 /*@} end of group CMSIS_core_bitfield */
 
@@ -1529,7 +1541,7 @@ typedef struct
   @{
  */
 
-/* Memory mapping of Cortex-M4 Hardware */
+/* Memory mapping of Core Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
@@ -1548,15 +1560,13 @@ typedef struct
 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
 
-#if (__MPU_PRESENT == 1U)
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
 #endif
 
-#if (__FPU_PRESENT == 1U)
 #define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
 #define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
-#endif
 
 /*@} */
 
@@ -1584,6 +1594,48 @@ typedef struct
   @{
  */
 
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
 /**
   \brief   Set Priority Grouping
   \details Sets the priority grouping field using the required unlock sequence.
@@ -1593,7 +1645,7 @@ typedef struct
            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
   \param [in]      PriorityGroup  Priority grouping field.
  */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
@@ -1602,7 +1654,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
   reg_value  =  (reg_value                                   |
                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
   SCB->AIRCR =  reg_value;
 }
 
@@ -1612,121 +1664,180 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
   \details Reads the priority grouping field from the NVIC Interrupt Controller.
   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
 {
   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 }
 
 
 /**
-  \brief   Enable External Interrupt
-  \details Enables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
   {
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
 /**
-  \brief   Disable External Interrupt
-  \details Disables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
 }
 
 
 /**
   \brief   Get Pending Interrupt
-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
-  \param [in]      IRQn  Interrupt number.
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
   \return             0  Interrupt status is not pending.
   \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
   {
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
 /**
   \brief   Set Pending Interrupt
-  \details Sets the pending bit of an external interrupt.
-  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
   {
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
 /**
   \brief   Clear Pending Interrupt
-  \details Clears the pending bit of an external interrupt.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
   {
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
 /**
   \brief   Get Active Interrupt
-  \details Reads the active register in NVIC and returns the active bit.
-  \param [in]      IRQn  Interrupt number.
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
   \return             0  Interrupt status is not active.
   \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
 {
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
 /**
   \brief   Set Interrupt Priority
-  \details Sets the priority of an interrupt.
-  \note    The priority cannot be set for every core interrupt.
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
   \param [in]      IRQn  Interrupt number.
   \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-  if ((int32_t)(IRQn) < 0)
+  if ((int32_t)(IRQn) >= 0)
   {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
   }
   else
   {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
   }
 }
 
 
 /**
   \brief   Get Interrupt Priority
-  \details Reads the priority of an interrupt.
-           The interrupt number can be positive to specify an external (device specific) interrupt,
-           or negative to specify an internal (core) interrupt.
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
   \param [in]   IRQn  Interrupt number.
   \return             Interrupt Priority.
                       Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if ((int32_t)(IRQn) < 0)
+  if ((int32_t)(IRQn) >= 0)
   {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
   }
   else
   {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
@@ -1783,11 +1894,43 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
 }
 
 
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t vectors = (uint32_t )SCB->VTOR;
+  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+  /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t vectors = (uint32_t )SCB->VTOR;
+  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
 /**
   \brief   System Reset
   \details Initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 {
   __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                        buffered write are completed before reset */
@@ -1805,6 +1948,50 @@ __STATIC_INLINE void NVIC_SystemReset(void)
 /*@} end of CMSIS_Core_NVICFunctions */
 
 
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
 
 /* ##################################    SysTick function  ############################################ */
 /**
@@ -1814,7 +2001,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
   @{
  */
 
-#if (__Vendor_SysTickConfig == 0U)
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
 
 /**
   \brief   System Tick Configuration
@@ -1858,7 +2045,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
  */
 
 extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
 
 /**
@@ -1935,3 +2122,4 @@ __STATIC_INLINE int32_t ITM_CheckChar (void)
 #endif /* __CORE_CM4_H_DEPENDANT */
 
 #endif /* __CMSIS_GENERIC */
+

board/inc/core_cmFunc.h

@@ -1,87 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
-*/
-
-/*------------------ RealView Compiler -----------------*/
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
-
-/*------------------ ARM Compiler V6 -------------------*/
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #include "cmsis_armcc_V6.h"
-
-/*------------------ GNU Compiler ----------------------*/
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
-
-/*------------------ ICC Compiler ----------------------*/
-#elif defined ( __ICCARM__ )
-  #include <cmsis_iar.h>
-
-/*------------------ TI CCS Compiler -------------------*/
-#elif defined ( __TMS470__ )
-  #include <cmsis_ccs.h>
-
-/*------------------ TASKING Compiler ------------------*/
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
-
-/*------------------ COSMIC Compiler -------------------*/
-#elif defined ( __CSMC__ )
-  #include <cmsis_csm.h>
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-#endif /* __CORE_CMFUNC_H */

board/inc/core_cmInstr.h

@@ -1,87 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/*------------------ RealView Compiler -----------------*/
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
-
-/*------------------ ARM Compiler V6 -------------------*/
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #include "cmsis_armcc_V6.h"
-
-/*------------------ GNU Compiler ----------------------*/
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
-
-/*------------------ ICC Compiler ----------------------*/
-#elif defined ( __ICCARM__ )
-  #include <cmsis_iar.h>
-
-/*------------------ TI CCS Compiler -------------------*/
-#elif defined ( __TMS470__ )
-  #include <cmsis_ccs.h>
-
-/*------------------ TASKING Compiler ------------------*/
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
-
-/*------------------ COSMIC Compiler -------------------*/
-#elif defined ( __CSMC__ )
-  #include <cmsis_csm.h>
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

board/inc/core_cmSimd.h

@@ -1,96 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmSimd.h
- * @brief    CMSIS Cortex-M SIMD Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CMSIMD_H
-#define __CORE_CMSIMD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-/*------------------ RealView Compiler -----------------*/
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
-
-/*------------------ ARM Compiler V6 -------------------*/
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #include "cmsis_armcc_V6.h"
-
-/*------------------ GNU Compiler ----------------------*/
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
-
-/*------------------ ICC Compiler ----------------------*/
-#elif defined ( __ICCARM__ )
-  #include <cmsis_iar.h>
-
-/*------------------ TI CCS Compiler -------------------*/
-#elif defined ( __TMS470__ )
-  #include <cmsis_ccs.h>
-
-/*------------------ TASKING Compiler ------------------*/
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
-
-/*------------------ COSMIC Compiler -------------------*/
-#elif defined ( __CSMC__ )
-  #include <cmsis_csm.h>
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CMSIMD_H */

board/inc/mpu_armv7.h

@@ -0,0 +1,273 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.1.0
+ * @date     08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if shareable) or 010b (if non-shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
+

board/main.c

@@ -13,6 +13,7 @@
 #include "drivers/llcan.h"
 #include "drivers/llgpio.h"
 #include "drivers/adc.h"
+#include "drivers/pwm.h"
 
 #include "board.h"
 
@@ -35,6 +36,10 @@
 
 // ********************* Serial debugging *********************
 
+bool check_started(void) {
+  return current_board->check_ignition() || ignition_can;
+}
+
 void debug_ring_callback(uart_ring *ring) {
   char rcv;
   while (getc(ring, &rcv)) {
@@ -80,10 +85,10 @@ void started_interrupt_handler(uint8_t interrupt_line) {
 
     #ifdef EON
       // set power savings mode here if on EON build
-      int power_save_state = current_board->check_ignition() ? POWER_SAVE_STATUS_DISABLED : POWER_SAVE_STATUS_ENABLED;
+      int power_save_state = check_started() ? POWER_SAVE_STATUS_DISABLED : POWER_SAVE_STATUS_ENABLED;
       set_power_save_state(power_save_state);
       // set CDP usb power mode everytime that the car starts to make sure EON is charging
-      if (current_board->check_ignition()) {
+      if (check_started()) {
         current_board->set_usb_power_mode(USB_POWER_CDP);
       }
     #endif
@@ -117,7 +122,7 @@ void set_safety_mode(uint16_t mode, int16_t param) {
     switch (mode) {
         case SAFETY_NOOUTPUT:
           set_intercept_relay(false);
-          if(hw_type == HW_TYPE_BLACK_PANDA){
+          if(board_has_obd()){
             current_board->set_can_mode(CAN_MODE_NORMAL);
           }
           can_silent = ALL_CAN_SILENT;
@@ -125,7 +130,7 @@ void set_safety_mode(uint16_t mode, int16_t param) {
         case SAFETY_ELM327:
           set_intercept_relay(false);
           heartbeat_counter = 0U;
-          if(hw_type == HW_TYPE_BLACK_PANDA){
+          if(board_has_obd()){
             current_board->set_can_mode(CAN_MODE_OBD_CAN2);
           }
           can_silent = ALL_CAN_LIVE;
@@ -133,19 +138,12 @@ void set_safety_mode(uint16_t mode, int16_t param) {
         default:
           set_intercept_relay(true);
           heartbeat_counter = 0U;
-          if(hw_type == HW_TYPE_BLACK_PANDA){
+          if(board_has_obd()){
             current_board->set_can_mode(CAN_MODE_NORMAL);
           }
           can_silent = ALL_CAN_LIVE;
           break;
       }
-    if (safety_ignition_hook() != -1) {
-      // if the ignition hook depends on something other than the started GPIO
-      // we have to disable power savings (fix for GM and Tesla)
-      set_power_save_state(POWER_SAVE_STATUS_DISABLED);
-    } else {
-      // power mode is already POWER_SAVE_STATUS_DISABLED and CAN TXs are active
-    }
     can_init_all();
   }
 }
@@ -159,30 +157,21 @@ int get_health_pkt(void *dat) {
     uint32_t can_send_errs_pkt;
     uint32_t can_fwd_errs_pkt;
     uint32_t gmlan_send_errs_pkt;
-    uint8_t started_pkt;
+    uint8_t ignition_line_pkt;
+    uint8_t ignition_can_pkt;
     uint8_t controls_allowed_pkt;
     uint8_t gas_interceptor_detected_pkt;
     uint8_t car_harness_status_pkt;
     uint8_t usb_power_mode_pkt;
+    uint8_t safety_mode_pkt;
   } *health = dat;
 
   health->voltage_pkt = adc_get_voltage();
+  health->current_pkt = current_board->read_current();
 
-  // No current sense on panda black
-  if(hw_type != HW_TYPE_BLACK_PANDA){
-    health->current_pkt = adc_get(ADCCHAN_CURRENT);
-  } else {
-    health->current_pkt = 0;
-  }
-
-  int safety_ignition = safety_ignition_hook();
-  if (safety_ignition < 0) {
-    //Use the GPIO pin to determine ignition
-    health->started_pkt = (uint8_t)(current_board->check_ignition());
-  } else {
-    //Current safety hooks want to determine ignition (ex: GM)
-    health->started_pkt = safety_ignition;
-  }
+  //Use the GPIO pin to determine ignition or use a CAN based logic
+  health->ignition_line_pkt = (uint8_t)(current_board->check_ignition());
+  health->ignition_can_pkt = (uint8_t)(ignition_can);
 
   health->controls_allowed_pkt = controls_allowed;
   health->gas_interceptor_detected_pkt = gas_interceptor_detected;
@@ -191,10 +180,17 @@ int get_health_pkt(void *dat) {
   health->gmlan_send_errs_pkt = gmlan_send_errs;
   health->car_harness_status_pkt = car_harness_status;
   health->usb_power_mode_pkt = usb_power_mode;
+  health->safety_mode_pkt = (uint8_t)(current_safety_mode);
 
   return sizeof(*health);
 }
 
+int get_rtc_pkt(void *dat) {
+  timestamp_t t = rtc_get_time();
+  (void)memcpy(dat, &t, sizeof(t));
+  return sizeof(t);
+}
+
 int usb_cb_ep1_in(void *usbdata, int len, bool hardwired) {
   UNUSED(hardwired);
   CAN_FIFOMailBox_TypeDef *reply = (CAN_FIFOMailBox_TypeDef *)usbdata;
@@ -247,7 +243,76 @@ int usb_cb_control_msg(USB_Setup_TypeDef *setup, uint8_t *resp, bool hardwired)
   unsigned int resp_len = 0;
   uart_ring *ur = NULL;
   int i;
+  timestamp_t t;
   switch (setup->b.bRequest) {
+    // **** 0xa0: get rtc time
+    case 0xa0:
+      resp_len = get_rtc_pkt(resp);
+      break;
+    // **** 0xa1: set rtc year
+    case 0xa1:
+      t = rtc_get_time();
+      t.year = setup->b.wValue.w;
+      rtc_set_time(t);
+      break;
+    // **** 0xa2: set rtc month
+    case 0xa2:
+      t = rtc_get_time();
+      t.month = setup->b.wValue.w;
+      rtc_set_time(t);
+      break;
+    // **** 0xa3: set rtc day
+    case 0xa3:
+      t = rtc_get_time();
+      t.day = setup->b.wValue.w;
+      rtc_set_time(t);
+      break;
+    // **** 0xa4: set rtc weekday
+    case 0xa4:
+      t = rtc_get_time();
+      t.weekday = setup->b.wValue.w;
+      rtc_set_time(t);
+      break;
+    // **** 0xa5: set rtc hour
+    case 0xa5:
+      t = rtc_get_time();
+      t.hour = setup->b.wValue.w;
+      rtc_set_time(t);
+      break;
+    // **** 0xa6: set rtc minute
+    case 0xa6:
+      t = rtc_get_time();
+      t.minute = setup->b.wValue.w;
+      rtc_set_time(t);
+      break;
+    // **** 0xa7: set rtc second
+    case 0xa7:
+      t = rtc_get_time();
+      t.second = setup->b.wValue.w;
+      rtc_set_time(t);
+      break;
+    // **** 0xb0: set IR power
+    case 0xb0:
+      if(power_save_status == POWER_SAVE_STATUS_DISABLED){
+        current_board->set_ir_power(setup->b.wValue.w);
+      } else {
+        puts("Setting IR power not allowed in power saving mode\n");
+      }
+      break;
+    // **** 0xb1: set fan power
+    case 0xb1:
+      if(power_save_status == POWER_SAVE_STATUS_DISABLED){
+        current_board->set_fan_power(setup->b.wValue.w);
+      } else {
+        puts("Setting fan power not allowed in power saving mode\n");
+      }
+      break;
+    // **** 0xb2: get fan rpm
+    case 0xb2:
+      resp[0] = (fan_rpm & 0x00FFU);
+      resp[1] = ((fan_rpm & 0xFF00U) >> 8U);
+      resp_len = 2;
+      break;
     // **** 0xc0: get CAN debug info
     case 0xc0:
       puts("can tx: "); puth(can_tx_cnt);
@@ -335,7 +400,7 @@ int usb_cb_control_msg(USB_Setup_TypeDef *setup, uint8_t *resp, bool hardwired)
       break;
     // **** 0xdb: set GMLAN (white/grey) or OBD CAN (black) multiplexing mode
     case 0xdb:
-      if(hw_type == HW_TYPE_BLACK_PANDA){
+      if(board_has_obd()){
         if (setup->b.wValue.w == 1U) {
           // Enable OBD CAN
           current_board->set_can_mode(CAN_MODE_OBD_CAN2);
@@ -583,8 +648,8 @@ uint64_t tcnt = 0;
 
 // called once per second
 // cppcheck-suppress unusedFunction ; used in headers not included in cppcheck
-void TIM3_IRQHandler(void) {
-  if (TIM3->SR != 0) {
+void TIM1_BRK_TIM9_IRQHandler(void) {
+  if (TIM9->SR != 0) {
     can_live = pending_can_live;
 
     current_board->usb_power_mode_tick(tcnt);
@@ -602,6 +667,10 @@ void TIM3_IRQHandler(void) {
       puth(can_tx2_q.r_ptr); puts(" "); puth(can_tx2_q.w_ptr); puts("\n");
     #endif
 
+    // Tick fan driver
+    fan_tick();
+    //puts("Fan speed: "); puth((unsigned int) fan_rpm); puts("rpm\n");
+
     // set green LED to be controls allowed
     current_board->set_led(LED_GREEN, controls_allowed);
 
@@ -616,7 +685,7 @@ void TIM3_IRQHandler(void) {
 
     // check heartbeat counter if we are running EON code. If the heartbeat has been gone for a while, go to NOOUTPUT safety mode.
     #ifdef EON
-    if (heartbeat_counter >= (current_board->check_ignition() ? EON_HEARTBEAT_IGNITION_CNT_ON : EON_HEARTBEAT_IGNITION_CNT_OFF)) {
+    if (heartbeat_counter >= (check_started() ? EON_HEARTBEAT_IGNITION_CNT_ON : EON_HEARTBEAT_IGNITION_CNT_OFF)) {
       puts("EON hasn't sent a heartbeat for 0x"); puth(heartbeat_counter); puts(" seconds. Safety is set to NOOUTPUT mode.\n");
       if(current_safety_mode != SAFETY_NOOUTPUT){
         set_safety_mode(SAFETY_NOOUTPUT, 0U);
@@ -627,7 +696,7 @@ void TIM3_IRQHandler(void) {
     // on to the next one
     tcnt += 1U;
   }
-  TIM3->SR = 0;
+  TIM9->SR = 0;
 }
 
 int main(void) {
@@ -675,8 +744,7 @@ int main(void) {
     uart_init(&uart_ring_esp_gps, 115200);
   }
 
-  // there is no LIN on panda black
-  if(hw_type != HW_TYPE_BLACK_PANDA){
+  if(board_has_lin()){
     // enable LIN
     uart_init(&uart_ring_lin1, 10400);
     UART5->CR2 |= USART_CR2_LINEN;
@@ -714,14 +782,13 @@ int main(void) {
     current_board->set_esp_gps_mode(ESP_GPS_DISABLED);
   }
   // only enter power save after the first cycle
-  /*if (current_board->check_ignition()) {
+  /*if (check_started()) {
     set_power_save_state(POWER_SAVE_STATUS_ENABLED);
   }*/
 #endif
-
-  // 48mhz / 65536 ~= 732 / 732 = 1
-  timer_init(TIM3, 732);
-  NVIC_EnableIRQ(TIM3_IRQn);
+  // 1hz
+  timer_init(TIM9, 1464);
+  NVIC_EnableIRQ(TIM1_BRK_TIM9_IRQn);
 
 #ifdef DEBUG
   puts("DEBUG ENABLED\n");

board/power_saving.h

@@ -25,7 +25,6 @@ void set_power_save_state(int state) {
       enable = true;
     }
 
-    // Switch CAN transcievers
     current_board->enable_can_transcievers(enable);
 
     // Switch EPS/GPS
@@ -35,16 +34,24 @@ void set_power_save_state(int state) {
       current_board->set_esp_gps_mode(ESP_GPS_DISABLED);
     }
 
-    if(hw_type != HW_TYPE_BLACK_PANDA){
+    if(board_has_gmlan()){
       // turn on GMLAN
       set_gpio_output(GPIOB, 14, enable);
       set_gpio_output(GPIOB, 15, enable);
+    }
 
+    if(board_has_lin()){
       // turn on LIN
       set_gpio_output(GPIOB, 7, enable);
       set_gpio_output(GPIOA, 14, enable);
     }
 
+    // Switch off IR and fan when in power saving
+    if(!enable){
+      current_board->set_ir_power(0U);
+      current_board->set_fan_power(0U);
+    }   
+
     power_save_status = state;
   }
 }

board/safety.h

@@ -14,6 +14,7 @@
 #include "safety/safety_chrysler.h"
 #include "safety/safety_subaru.h"
 #include "safety/safety_mazda.h"
+#include "safety/safety_volkswagen.h"
 #include "safety/safety_elm327.h"
 
 // from cereal.car.CarParams.SafetyModel
@@ -29,8 +30,8 @@
 #define SAFETY_CHRYSLER 9U
 #define SAFETY_TESLA 10U
 #define SAFETY_SUBARU 11U
-#define SAFETY_GM_PASSIVE 12U
 #define SAFETY_MAZDA 13U
+#define SAFETY_VOLKSWAGEN 15U
 #define SAFETY_TOYOTA_IPAS 16U
 #define SAFETY_ALLOUTPUT 17U
 #define SAFETY_GM_ASCM 18U
@@ -50,12 +51,6 @@ int safety_tx_lin_hook(int lin_num, uint8_t *data, int len){
   return current_hooks->tx_lin(lin_num, data, len);
 }
 
-// -1 = Disabled (Use GPIO to determine ignition)
-// 0 = Off (not started)
-// 1 = On (started)
-int safety_ignition_hook() {
-  return current_hooks->ignition();
-}
 int safety_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {
   return current_hooks->fwd(bus_num, to_fwd);
 }
@@ -78,8 +73,8 @@ const safety_hook_config safety_hook_registry[] = {
   {SAFETY_CHRYSLER, &chrysler_hooks},
   {SAFETY_TESLA, &tesla_hooks},
   {SAFETY_SUBARU, &subaru_hooks},
-  {SAFETY_GM_PASSIVE, &gm_passive_hooks},
   {SAFETY_MAZDA, &mazda_hooks},
+  {SAFETY_VOLKSWAGEN, &volkswagen_hooks},
   {SAFETY_TOYOTA_IPAS, &toyota_ipas_hooks},
   {SAFETY_ALLOUTPUT, &alloutput_hooks},
   {SAFETY_GM_ASCM, &gm_ascm_hooks},

board/safety/safety_cadillac.h

@@ -10,7 +10,6 @@ const int CADILLAC_MAX_RATE_DOWN = 5;
 const int CADILLAC_DRIVER_TORQUE_ALLOWANCE = 50;
 const int CADILLAC_DRIVER_TORQUE_FACTOR = 4;
 
-bool cadillac_ign = 0;
 int cadillac_cruise_engaged_last = 0;
 int cadillac_rt_torque_last = 0;
 const int cadillac_torque_msgs_n = 4;
@@ -35,11 +34,6 @@ static void cadillac_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {
     update_sample(&cadillac_torque_driver, torque_driver_new);
   }
 
-  // this message isn't all zeros when ignition is on
-  if ((addr == 0x160) && (bus == 0)) {
-    cadillac_ign = GET_BYTES_04(to_push) != 0;
-  }
-
   // enter controls on rising edge of ACC, exit controls on ACC off
   if ((addr == 0x370) && (bus == 0)) {
     int cruise_engaged = GET_BYTE(to_push, 2) & 0x80;  // bit 23
@@ -118,11 +112,6 @@ static int cadillac_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {
 static void cadillac_init(int16_t param) {
   UNUSED(param);
   controls_allowed = 0;
-  cadillac_ign = 0;
-}
-
-static int cadillac_ign_hook(void) {
-  return cadillac_ign;
 }
 
 const safety_hooks cadillac_hooks = {
@@ -130,6 +119,5 @@ const safety_hooks cadillac_hooks = {
   .rx = cadillac_rx_hook,
   .tx = cadillac_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = cadillac_ign_hook,
   .fwd = default_fwd_hook,
 };

board/safety/safety_chrysler.h

@@ -136,6 +136,5 @@ const safety_hooks chrysler_hooks = {
   .rx = chrysler_rx_hook,
   .tx = chrysler_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = default_ign_hook,
   .fwd = chrysler_fwd_hook,
 };

board/safety/safety_defaults.h

@@ -2,10 +2,6 @@ void default_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {
   UNUSED(to_push);
 }
 
-int default_ign_hook(void) {
-  return -1; // use GPIO to determine ignition
-}
-
 // *** no output safety mode ***
 
 static void nooutput_init(int16_t param) {
@@ -36,7 +32,6 @@ const safety_hooks nooutput_hooks = {
   .rx = default_rx_hook,
   .tx = nooutput_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = default_ign_hook,
   .fwd = default_fwd_hook,
 };
 
@@ -64,6 +59,5 @@ const safety_hooks alloutput_hooks = {
   .rx = default_rx_hook,
   .tx = alloutput_tx_hook,
   .tx_lin = alloutput_tx_lin_hook,
-  .ignition = default_ign_hook,
   .fwd = default_fwd_hook,
 };

board/safety/safety_elm327.h

@@ -38,6 +38,5 @@ const safety_hooks elm327_hooks = {
   .rx = default_rx_hook,
   .tx = elm327_tx_hook,
   .tx_lin = elm327_tx_lin_hook,
-  .ignition = default_ign_hook,
   .fwd = default_fwd_hook,
 };

board/safety/safety_ford.h

@@ -97,6 +97,5 @@ const safety_hooks ford_hooks = {
   .rx = ford_rx_hook,
   .tx = ford_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = default_ign_hook,
   .fwd = default_fwd_hook,
 };

board/safety/safety_gm.h

@@ -24,7 +24,6 @@ int gm_gas_prev = 0;
 bool gm_moving = false;
 // silence everything if stock car control ECUs are still online
 bool gm_ascm_detected = 0;
-bool gm_ignition_started = 0;
 int gm_rt_torque_last = 0;
 int gm_desired_torque_last = 0;
 uint32_t gm_ts_last = 0;
@@ -41,13 +40,6 @@ static void gm_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {
     update_sample(&gm_torque_driver, torque_driver_new);
   }
 
-  if ((addr == 0x1F1) && (bus_number == 0)) {
-    //Bit 5 should be ignition "on"
-    //Backup plan is Bit 2 (accessory power)
-    bool ign = (GET_BYTE(to_push, 0) & 0x20) != 0;
-    gm_ignition_started = ign;
-  }
-
   // sample speed, really only care if car is moving or not
   // rear left wheel speed
   if (addr == 842) {
@@ -224,41 +216,13 @@ static int gm_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {
 static void gm_init(int16_t param) {
   UNUSED(param);
   controls_allowed = 0;
-  gm_ignition_started = 0;
-}
-
-static int gm_ign_hook(void) {
-  return gm_ignition_started;
 }
 
-// All sending is disallowed.
-// The only difference from "no output" model
-// is using GM ignition hook.
-
-static void gm_passive_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {
-  int bus_number = GET_BUS(to_push);
-  int addr = GET_ADDR(to_push);
-
-  if ((addr == 0x1F1) && (bus_number == 0)) {
-    bool ign = (GET_BYTE(to_push, 0) & 0x20) != 0;
-    gm_ignition_started = ign;
-  }
-}
 
 const safety_hooks gm_hooks = {
   .init = gm_init,
   .rx = gm_rx_hook,
   .tx = gm_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = gm_ign_hook,
-  .fwd = default_fwd_hook,
-};
-
-const safety_hooks gm_passive_hooks = {
-  .init = gm_init,
-  .rx = gm_passive_rx_hook,
-  .tx = nooutput_tx_hook,
-  .tx_lin = nooutput_tx_lin_hook,
-  .ignition = gm_ign_hook,
   .fwd = default_fwd_hook,
 };

board/safety/safety_gm_ascm.h

@@ -39,7 +39,6 @@ const safety_hooks gm_ascm_hooks = {
   .rx = default_rx_hook,
   .tx = alloutput_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = default_ign_hook,
   .fwd = gm_ascm_fwd_hook,
 };
 

board/safety/safety_honda.h

@@ -156,7 +156,7 @@ static int honda_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {
   // FORCE CANCEL: safety check only relevant when spamming the cancel button in Bosch HW
   // ensuring that only the cancel button press is sent (VAL 2) when controls are off.
   // This avoids unintended engagements while still allowing resume spam
-  int bus_pt = ((hw_type == HW_TYPE_BLACK_PANDA) && honda_bosch_hardware)? 1 : 0;
+  int bus_pt = ((board_has_relay()) && honda_bosch_hardware)? 1 : 0;
   if ((addr == 0x296) && honda_bosch_hardware &&
       !current_controls_allowed && (bus == bus_pt)) {
     if (((GET_BYTE(to_send, 0) >> 5) & 0x7) != 2) {
@@ -210,8 +210,8 @@ static int honda_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {
 
 static int honda_bosch_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {
   int bus_fwd = -1;
-  int bus_rdr_cam = (hw_type == HW_TYPE_BLACK_PANDA) ? 2 : 1;  // radar bus, camera side
-  int bus_rdr_car = (hw_type == HW_TYPE_BLACK_PANDA) ? 0 : 2;  // radar bus, car side
+  int bus_rdr_cam = (board_has_relay()) ? 2 : 1;  // radar bus, camera side
+  int bus_rdr_car = (board_has_relay()) ? 0 : 2;  // radar bus, car side
 
   if (bus_num == bus_rdr_car) {
     bus_fwd = bus_rdr_cam;
@@ -231,7 +231,6 @@ const safety_hooks honda_hooks = {
   .rx = honda_rx_hook,
   .tx = honda_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = default_ign_hook,
   .fwd = honda_fwd_hook,
 };
 
@@ -240,6 +239,5 @@ const safety_hooks honda_bosch_hooks = {
   .rx = honda_rx_hook,
   .tx = honda_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = default_ign_hook,
   .fwd = honda_bosch_fwd_hook,
 };

board/safety/safety_hyundai.h

@@ -155,6 +155,5 @@ const safety_hooks hyundai_hooks = {
   .rx = hyundai_rx_hook,
   .tx = hyundai_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = default_ign_hook,
   .fwd = hyundai_fwd_hook,
 };

board/safety/safety_mazda.h

@@ -164,6 +164,5 @@ const safety_hooks mazda_hooks = {
   .rx = mazda_rx_hook,
   .tx = mazda_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = default_ign_hook,
   .fwd = mazda_fwd_hook,
 };

board/safety/safety_subaru.h

@@ -124,6 +124,5 @@ const safety_hooks subaru_hooks = {
   .rx = subaru_rx_hook,
   .tx = subaru_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = default_ign_hook,
   .fwd = subaru_fwd_hook,
 };

board/safety/safety_tesla.h

@@ -39,9 +39,6 @@ int tesla_gas_prev = 0;
 int tesla_speed = 0;
 int eac_status = 0;
 
-int tesla_ignition_started = 0;
-
-
 void set_gmlan_digital_output(int to_set);
 void reset_gmlan_switch_timeout(void);
 void gmlan_switch_init(int timeout_enable);
@@ -66,13 +63,6 @@ static void tesla_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {
     }
   }
 
-  // Detect drive rail on (ignition) (start recording)
-  if (addr == 0x348) {
-    // GTW_status
-    int drive_rail_on = GET_BYTE(to_push, 0) & 0x1;
-    tesla_ignition_started = drive_rail_on == 1;
-  }
-
   // exit controls on brake press
   // DI_torque2::DI_brakePedal 0x118
   if (addr == 0x118) {
@@ -183,14 +173,9 @@ static int tesla_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {
 static void tesla_init(int16_t param) {
   UNUSED(param);
   controls_allowed = 0;
-  tesla_ignition_started = 0;
   gmlan_switch_init(1); //init the gmlan switch with 1s timeout enabled
 }
 
-static int tesla_ign_hook(void) {
-  return tesla_ignition_started;
-}
-
 static int tesla_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {
 
   int bus_fwd = -1;
@@ -224,6 +209,5 @@ const safety_hooks tesla_hooks = {
   .rx = tesla_rx_hook,
   .tx = tesla_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = tesla_ign_hook,
   .fwd = tesla_fwd_hook,
 };

board/safety/safety_toyota.h

@@ -224,6 +224,5 @@ const safety_hooks toyota_hooks = {
   .rx = toyota_rx_hook,
   .tx = toyota_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = default_ign_hook,
   .fwd = toyota_fwd_hook,
 };

board/safety/safety_toyota_ipas.h

@@ -164,6 +164,5 @@ const safety_hooks toyota_ipas_hooks = {
   .rx = toyota_ipas_rx_hook,
   .tx = toyota_ipas_tx_hook,
   .tx_lin = nooutput_tx_lin_hook,
-  .ignition = default_ign_hook,
   .fwd = toyota_fwd_hook,
 };

board/safety/safety_volkswagen.h

@@ -0,0 +1,167 @@
+const int VOLKSWAGEN_MAX_STEER = 250;               // 2.5 Nm (EPS side max of 3.0Nm with fault if violated)
+const int VOLKSWAGEN_MAX_RT_DELTA = 75;             // 4 max rate up * 50Hz send rate * 250000 RT interval / 1000000 = 50 ; 50 * 1.5 for safety pad = 75
+const uint32_t VOLKSWAGEN_RT_INTERVAL = 250000;     // 250ms between real time checks
+const int VOLKSWAGEN_MAX_RATE_UP = 4;               // 2.0 Nm/s available rate of change from the steering rack (EPS side delta-limit of 5.0 Nm/s)
+const int VOLKSWAGEN_MAX_RATE_DOWN = 10;            // 5.0 Nm/s available rate of change from the steering rack (EPS side delta-limit of 5.0 Nm/s)
+const int VOLKSWAGEN_DRIVER_TORQUE_ALLOWANCE = 80;
+const int VOLKSWAGEN_DRIVER_TORQUE_FACTOR = 3;
+
+struct sample_t volkswagen_torque_driver;           // last few driver torques measured
+int volkswagen_rt_torque_last = 0;
+int volkswagen_desired_torque_last = 0;
+uint32_t volkswagen_ts_last = 0;
+int volkswagen_gas_prev = 0;
+
+// Safety-relevant CAN messages for the Volkswagen MQB platform.
+#define MSG_EPS_01              0x09F
+#define MSG_MOTOR_20            0x121
+#define MSG_ACC_06              0x122
+#define MSG_HCA_01              0x126
+#define MSG_GRA_ACC_01          0x12B
+#define MSG_LDW_02              0x397
+#define MSG_KLEMMEN_STATUS_01   0x3C0
+
+static void volkswagen_init(int16_t param) {
+  UNUSED(param); // May use param in the future to indicate MQB vs PQ35/PQ46/NMS vs MLB, or wiring configuration.
+  controls_allowed = 0;
+}
+
+static void volkswagen_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {
+  int bus = GET_BUS(to_push);
+  int addr = GET_ADDR(to_push);
+
+  // Update driver input torque samples from EPS_01.Driver_Strain for absolute torque, and EPS_01.Driver_Strain_VZ
+  // for the direction.
+  if ((bus == 0) && (addr == MSG_EPS_01)) {
+    int torque_driver_new = GET_BYTE(to_push, 5) | ((GET_BYTE(to_push, 6) & 0x1F) << 8);
+    int sign = (GET_BYTE(to_push, 6) & 0x80) >> 7;
+    if (sign == 1) {
+      torque_driver_new *= -1;
+    }
+
+    update_sample(&volkswagen_torque_driver, torque_driver_new);
+  }
+
+  // Monitor ACC_06.ACC_Status_ACC for stock ACC status. Because the current MQB port is lateral-only, OP's control
+  // allowed state is directly driven by stock ACC engagement. Permit the ACC message to come from either bus, in
+  // order to accommodate future camera-side integrations if needed.
+  if (addr == MSG_ACC_06) {
+    int acc_status = (GET_BYTE(to_push, 7) & 0x70) >> 4;
+    controls_allowed = ((acc_status == 3) || (acc_status == 4) || (acc_status == 5)) ? 1 : 0;
+  }
+
+  // exit controls on rising edge of gas press. Bits [12-20)
+  if (addr == MSG_MOTOR_20) {
+    int gas = (GET_BYTES_04(to_push) >> 12) & 0xFF;
+    if ((gas > 0) && (volkswagen_gas_prev == 0) && long_controls_allowed) {
+      controls_allowed = 0;
+    }
+    volkswagen_gas_prev = gas;
+  }
+}
+
+static int volkswagen_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {
+  int addr = GET_ADDR(to_send);
+  int bus = GET_BUS(to_send);
+  int tx = 1;
+
+  // Safety check for HCA_01 Heading Control Assist torque.
+  if (addr == MSG_HCA_01) {
+    bool violation = false;
+
+    int desired_torque = GET_BYTE(to_send, 2) | ((GET_BYTE(to_send, 3) & 0x3F) << 8);
+    int sign = (GET_BYTE(to_send, 3) & 0x80) >> 7;
+    if (sign == 1) {
+      desired_torque *= -1;
+    }
+
+    uint32_t ts = TIM2->CNT;
+
+    if (controls_allowed) {
+
+      // *** global torque limit check ***
+      violation |= max_limit_check(desired_torque, VOLKSWAGEN_MAX_STEER, -VOLKSWAGEN_MAX_STEER);
+
+      // *** torque rate limit check ***
+      violation |= driver_limit_check(desired_torque, volkswagen_desired_torque_last, &volkswagen_torque_driver,
+        VOLKSWAGEN_MAX_STEER, VOLKSWAGEN_MAX_RATE_UP, VOLKSWAGEN_MAX_RATE_DOWN,
+        VOLKSWAGEN_DRIVER_TORQUE_ALLOWANCE, VOLKSWAGEN_DRIVER_TORQUE_FACTOR);
+      volkswagen_desired_torque_last = desired_torque;
+
+      // *** torque real time rate limit check ***
+      violation |= rt_rate_limit_check(desired_torque, volkswagen_rt_torque_last, VOLKSWAGEN_MAX_RT_DELTA);
+
+      // every RT_INTERVAL set the new limits
+      uint32_t ts_elapsed = get_ts_elapsed(ts, volkswagen_ts_last);
+      if (ts_elapsed > VOLKSWAGEN_RT_INTERVAL) {
+        volkswagen_rt_torque_last = desired_torque;
+        volkswagen_ts_last = ts;
+      }
+    }
+
+    // no torque if controls is not allowed
+    if (!controls_allowed && (desired_torque != 0)) {
+      violation = true;
+    }
+
+    // reset to 0 if either controls is not allowed or there's a violation
+    if (violation || !controls_allowed) {
+      volkswagen_desired_torque_last = 0;
+      volkswagen_rt_torque_last = 0;
+      volkswagen_ts_last = ts;
+    }
+
+    if (violation) {
+      tx = 0;
+    }
+  }
+
+  // FORCE CANCEL: ensuring that only the cancel button press is sent when controls are off.
+  // This avoids unintended engagements while still allowing resume spam
+  if ((bus == 2) && (addr == MSG_GRA_ACC_01) && !controls_allowed) {
+    // disallow resume and set: bits 16 and 19
+    if ((GET_BYTE(to_send, 2) & 0x9) != 0) {
+      tx = 0;
+    }
+  }
+
+  // 1 allows the message through
+  return tx;
+}
+
+static int volkswagen_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {
+  int addr = GET_ADDR(to_fwd);
+  int bus_fwd = -1;
+
+  // NOTE: Will need refactoring for other bus layouts, such as no-forwarding at camera or J533 running-gear CAN
+
+  switch (bus_num) {
+    case 0:
+      // Forward all traffic from J533 gateway to Extended CAN devices.
+      bus_fwd = 2;
+      break;
+    case 2:
+      if ((addr == MSG_HCA_01) || (addr == MSG_LDW_02)) {
+        // OP takes control of the Heading Control Assist and Lane Departure Warning messages from the camera.
+        bus_fwd = -1;
+      } else {
+        // Forward all remaining traffic from Extended CAN devices to J533 gateway.
+        bus_fwd = 0;
+      }
+      break;
+    default:
+      // No other buses should be in use; fallback to do-not-forward.
+      bus_fwd = -1;
+      break;
+  }
+
+  return bus_fwd;
+}
+
+const safety_hooks volkswagen_hooks = {
+  .init = volkswagen_init,
+  .rx = volkswagen_rx_hook,
+  .tx = volkswagen_tx_hook,
+  .tx_lin = nooutput_tx_lin_hook,
+  .fwd = volkswagen_fwd_hook,
+};

board/safety_declarations.h

@@ -14,7 +14,6 @@ struct lookup_t {
 void safety_rx_hook(CAN_FIFOMailBox_TypeDef *to_push);
 int safety_tx_hook(CAN_FIFOMailBox_TypeDef *to_send);
 int safety_tx_lin_hook(int lin_num, uint8_t *data, int len);
-int safety_ignition_hook(void);
 uint32_t get_ts_elapsed(uint32_t ts, uint32_t ts_last);
 int to_signed(int d, int bits);
 void update_sample(struct sample_t *sample, int sample_new);
@@ -31,12 +30,10 @@ typedef void (*safety_hook_init)(int16_t param);
 typedef void (*rx_hook)(CAN_FIFOMailBox_TypeDef *to_push);
 typedef int (*tx_hook)(CAN_FIFOMailBox_TypeDef *to_send);
 typedef int (*tx_lin_hook)(int lin_num, uint8_t *data, int len);
-typedef int (*ign_hook)(void);
 typedef int (*fwd_hook)(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd);
 
 typedef struct {
   safety_hook_init init;
-  ign_hook ignition;
   rx_hook rx;
   tx_hook tx;
   tx_lin_hook tx_lin;

board/tools/enter_download_mode.py

@@ -11,7 +11,7 @@ def enter_download_mode(device):
 
   try:
     handle.controlWrite(usb1.TYPE_VENDOR | usb1.RECIPIENT_DEVICE, 0xd1, 0, 0, b'')
-  except (usb1.USBErrorIO, usb1.USBErrorPipe) as e:
+  except (usb1.USBErrorIO, usb1.USBErrorPipe):
     print("Device download mode enabled.")
     time.sleep(1)
   else:

crypto/getcertheader.py

@@ -1,6 +1,5 @@
 #!/usr/bin/env python3
 import sys
-import struct
 from Crypto.PublicKey import RSA
 
 def egcd(a, b):

examples/can_bit_transition.py

@@ -1,6 +1,4 @@
 #!/usr/bin/env python3
-
-import binascii
 import csv
 import sys
 

examples/can_unique.py

@@ -13,10 +13,8 @@
 # 0,344,c000c00000000000
 
 
-import binascii
 import csv
 import sys
-from panda import Panda
 
 class Message():
   """Details about a specific message ID."""

examples/eps_read_software_ids.py

@@ -0,0 +1,59 @@
+#!/usr/bin/env python3
+from panda import Panda
+from panda.python.uds import UdsClient, NegativeResponseError, DATA_IDENTIFIER_TYPE
+
+if __name__ == "__main__":
+  address = 0x18da30f1 # Honda EPS
+  panda = Panda()
+  uds_client = UdsClient(panda, address, debug=False)
+
+  print("tester present ...")
+  uds_client.tester_present()
+
+  try:
+    print("")
+    print("read data by id: boot software id ...")
+    data = uds_client.read_data_by_identifier(DATA_IDENTIFIER_TYPE.BOOT_SOFTWARE_IDENTIFICATION)
+    print(data.decode('utf-8'))
+  except NegativeResponseError as e:
+    print(e)
+
+  try:
+    print("")
+    print("read data by id: application software id ...")
+    data = uds_client.read_data_by_identifier(DATA_IDENTIFIER_TYPE.APPLICATION_SOFTWARE_IDENTIFICATION)
+    print(data.decode('utf-8'))
+  except NegativeResponseError as e:
+    print(e)
+
+  try:
+    print("")
+    print("read data by id: application data id ...")
+    data = uds_client.read_data_by_identifier(DATA_IDENTIFIER_TYPE.APPLICATION_DATA_IDENTIFICATION)
+    print(data.decode('utf-8'))
+  except NegativeResponseError as e:
+    print(e)
+
+  try:
+    print("")
+    print("read data by id: boot software fingerprint ...")
+    data = uds_client.read_data_by_identifier(DATA_IDENTIFIER_TYPE.BOOT_SOFTWARE_FINGERPRINT)
+    print(data.decode('utf-8'))
+  except NegativeResponseError as e:
+    print(e)
+
+  try:
+    print("")
+    print("read data by id: application software fingerprint ...")
+    data = uds_client.read_data_by_identifier(DATA_IDENTIFIER_TYPE.APPLICATION_SOFTWARE_FINGERPRINT)
+    print(data.decode('utf-8'))
+  except NegativeResponseError as e:
+    print(e)
+
+  try:
+    print("")
+    print("read data by id: application data fingerprint ...")
+    data = uds_client.read_data_by_identifier(DATA_IDENTIFIER_TYPE.APPLICATION_DATA_FINGERPRINT)
+    print(data.decode('utf-8'))
+  except NegativeResponseError as e:
+    print(e)

examples/get_panda_password.py

@@ -1,4 +1,5 @@
 #!/usr/bin/env python3
+import sys
 from panda import Panda
 
 def get_panda_password():

examples/query_vin_and_stats.py

@@ -8,9 +8,10 @@ from panda.python.isotp import isotp_send, isotp_recv
 # 0x7e0 = Toyota
 # 0x18DB33F1 for Honda?
 
+
 def get_current_data_for_pid(pid):
   # 01 xx = Show current data
-  isotp_send(panda, "\x01"+chr(pid), 0x7e0)
+  isotp_send(panda, b"\x01"+ bytes([pid]), 0x7e0)
   return isotp_recv(panda, 0x7e8)
 
 def get_supported_pids():
@@ -33,15 +34,15 @@ if __name__ == "__main__":
   panda.can_clear(0)
 
   # 09 02 = Get VIN
-  isotp_send(panda, "\x09\x02", 0x7df)
+  isotp_send(panda, b"\x09\x02", 0x7df)
   ret = isotp_recv(panda, 0x7e8)
   hexdump(ret)
-  print("VIN: %s" % ret[2:])
+  print("VIN: %s" % "".join(map(chr, ret[:2])))
 
   # 03 = get DTCS
-  isotp_send(panda, "\x03", 0x7e0)
+  isotp_send(panda, b"\x03", 0x7e0)
   dtcs = isotp_recv(panda, 0x7e8)
-  print("DTCs:", dtcs[2:].encode("hex"))
+  print("DTCs:", "".join(map(chr, dtcs[:2])))
 
   supported_pids = get_supported_pids()
   print("Supported PIDs:",supported_pids)

examples/tesla_tester.py

@@ -29,11 +29,11 @@ def tesla_tester():
 
   # BDY 0x248 is the MCU_commands message, which includes folding mirrors, opening the trunk, frunk, setting the cars lock state and more. For our test, we will edit the 3rd byte, which is MCU_lockRequest. 0x01 will lock, 0x02 will unlock:
   print("Unlocking Tesla...")
-  p.can_send(0x248, "\x00\x00\x02\x00\x00\x00\x00\x00", body_bus_num)
+  p.can_send(0x248, b"\x00\x00\x02\x00\x00\x00\x00\x00", body_bus_num)
 
   #Or, we can set the first byte, MCU_frontHoodCommand + MCU_liftgateSwitch, to 0x01 to pop the frunk, or 0x04 to open/close the trunk (0x05 should open both)
   print("Opening Frunk...")
-  p.can_send(0x248, "\x01\x00\x00\x00\x00\x00\x00\x00", body_bus_num)
+  p.can_send(0x248, b"\x01\x00\x00\x00\x00\x00\x00\x00", body_bus_num)
 
   #Back to safety...
   print("Disabling output on Panda...")

python/__init__.py

@@ -1,5 +1,5 @@
 # python library to interface with panda
-
+import datetime
 import binascii
 import struct
 import hashlib
@@ -10,10 +10,10 @@ import time
 import traceback
 import subprocess
 from .dfu import PandaDFU
-from .esptool import ESPROM, CesantaFlasher
-from .flash_release import flash_release
-from .update import ensure_st_up_to_date
-from .serial import PandaSerial
+from .esptool import ESPROM, CesantaFlasher  # noqa: F401
+from .flash_release import flash_release  # noqa: F401
+from .update import ensure_st_up_to_date  # noqa: F401
+from .serial import PandaSerial  # noqa: F401
 from .isotp import isotp_send, isotp_recv
 
 __version__ = '0.0.9'
@@ -27,10 +27,10 @@ def build_st(target, mkfile="Makefile"):
   from panda import BASEDIR
   cmd = 'cd %s && make -f %s clean && make -f %s %s >/dev/null' % (os.path.join(BASEDIR, "board"), mkfile, mkfile, target)
   try:
-    output = subprocess.check_output(cmd, stderr=subprocess.STDOUT, shell=True)
-  except subprocess.CalledProcessError as exception:
-    output = exception.output
-    returncode = exception.returncode
+    _ = subprocess.check_output(cmd, stderr=subprocess.STDOUT, shell=True)
+  except subprocess.CalledProcessError:
+    #output = exception.output
+    #returncode = exception.returncode
     raise
 
 def parse_can_buffer(dat):
@@ -122,8 +122,8 @@ class Panda(object):
   SAFETY_CHRYSLER = 9
   SAFETY_TESLA = 10
   SAFETY_SUBARU = 11
-  SAFETY_GM_PASSIVE = 12
   SAFETY_MAZDA = 13
+  SAFETY_VOLKSWAGEN = 15
   SAFETY_TOYOTA_IPAS = 16
   SAFETY_ALLOUTPUT = 17
   SAFETY_GM_ASCM = 18
@@ -144,6 +144,7 @@ class Panda(object):
   HW_TYPE_GREY_PANDA = b'\x02'
   HW_TYPE_BLACK_PANDA = b'\x03'
   HW_TYPE_PEDAL = b'\x04'
+  HW_TYPE_UNO = b'\x05'
 
   def __init__(self, serial=None, claim=True):
     self._serial = serial
@@ -382,11 +383,14 @@ class Panda(object):
   def is_black(self):
     return self.get_type() == Panda.HW_TYPE_BLACK_PANDA
 
+  def is_uno(self):
+    return self.get_type() == Panda.HW_TYPE_UNO
+
   def get_serial(self):
     dat = self._handle.controlRead(Panda.REQUEST_IN, 0xd0, 0, 0, 0x20)
     hashsig, calc_hash = dat[0x1c:], hashlib.sha1(dat[0:0x1c]).digest()[0:4]
     assert(hashsig == calc_hash)
-    return [dat[0:0x10], dat[0x10:0x10+10]]
+    return [dat[0:0x10].decode("utf8"), dat[0x10:0x10+10].decode("utf8")]
 
   def get_secret(self):
     return self._handle.controlRead(Panda.REQUEST_IN, 0xd0, 1, 0, 0x10)
@@ -557,7 +561,7 @@ class Panda(object):
   def kline_ll_recv(self, cnt, bus=2):
     echo = bytearray()
     while len(echo) != cnt:
-      ret = str(self._handle.controlRead(Panda.REQUEST_OUT, 0xe0, bus, 0, cnt-len(echo)))
+      ret = self._handle.controlRead(Panda.REQUEST_OUT, 0xe0, bus, 0, cnt-len(echo))
       if DEBUG and len(ret) > 0:
         print("kline recv: " + binascii.hexlify(ret))
       echo += ret
@@ -577,7 +581,7 @@ class Panda(object):
       ts = x[i:i+0xf]
       if DEBUG:
         print("kline send: " + binascii.hexlify(ts))
-      self._handle.bulkWrite(2, chr(bus).encode()+ts)
+      self._handle.bulkWrite(2, bytes([bus]) + ts)
       echo = self.kline_ll_recv(len(ts), bus=bus)
       if echo != ts:
         print("**** ECHO ERROR %d ****" % i)
@@ -592,3 +596,31 @@ class Panda(object):
 
   def send_heartbeat(self):
     self._handle.controlWrite(Panda.REQUEST_OUT, 0xf3, 0, 0, b'')
+
+  # ******************* RTC *******************
+  def set_datetime(self, dt):
+    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa1, int(dt.year), 0, b'')
+    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa2, int(dt.month), 0, b'')
+    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa3, int(dt.day), 0, b'')
+    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa4, int(dt.isoweekday()), 0, b'')
+    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa5, int(dt.hour), 0, b'')
+    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa6, int(dt.minute), 0, b'')
+    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa7, int(dt.second), 0, b'')
+
+  def get_datetime(self):
+    dat = self._handle.controlRead(Panda.REQUEST_IN, 0xa0, 0, 0, 8)
+    a = struct.unpack("HBBBBBB", dat)
+    return datetime.datetime(a[0], a[1], a[2], a[4], a[5], a[6])
+
+  # ******************* IR *******************
+  def set_ir_power(self, percentage):
+    self._handle.controlWrite(Panda.REQUEST_OUT, 0xb0, int(percentage), 0, b'')
+
+  # ******************* Fan ******************
+  def set_fan_power(self, percentage):
+    self._handle.controlWrite(Panda.REQUEST_OUT, 0xb1, int(percentage), 0, b'')
+
+  def get_fan_rpm(self):
+    dat = self._handle.controlRead(Panda.REQUEST_IN, 0xb2, 0, 0, 2)
+    a = struct.unpack("H", dat)
+    return a[0]

python/dfu.py

@@ -1,8 +1,6 @@
-
 import os
 import usb1
 import struct
-import time
 import binascii
 
 # *** DFU mode ***
@@ -116,6 +114,6 @@ class PandaDFU(object):
     self.status()
     try:
       self._handle.controlWrite(0x21, DFU_DNLOAD, 2, 0, b"")
-      stat = str(self._handle.controlRead(0x21, DFU_GETSTATUS, 0, 0, 6))
+      _ = str(self._handle.controlRead(0x21, DFU_GETSTATUS, 0, 0, 6))
     except Exception:
       pass

python/esptool.py

@@ -29,7 +29,7 @@ import subprocess
 import sys
 import tempfile
 import time
-import traceback
+#import traceback
 import usb1
 
 __version__ = "1.2"
@@ -44,7 +44,7 @@ class FakePort(object):
 
   @property
   def baudrate(self):
-    return self._baudrate
+    return self.baudrate
 
   @baudrate.setter
   def baudrate(self, x):
@@ -434,7 +434,7 @@ class BaseFirmwareImage(object):
 
     def write_v1_header(self, f, segments):
         f.write(struct.pack('<BBBBI', ESPROM.ESP_IMAGE_MAGIC, len(segments),
-                            self.flash_mode, self.flash_size_freq, self.entrypoint))
+                            self.flash_mode, self.flash_size_freq, self.entrypoint))  # pylint: disable=no-member
 
 
 class ESPFirmwareImage(BaseFirmwareImage):
@@ -864,7 +864,7 @@ def write_mem(esp, args):
 
 
 def dump_mem(esp, args):
-    f = file(args.filename, 'wb')
+    f = open(args.filename, 'wb')
     for i in range(args.size / 4):
         d = esp.read_reg(args.address + (i * 4))
         f.write(struct.pack('<I', d))
@@ -944,7 +944,7 @@ def make_image(args):
     if len(args.segfile) != len(args.segaddr):
         raise FatalError('Number of specified files does not match number of specified addresses')
     for (seg, addr) in zip(args.segfile, args.segaddr):
-        data = file(seg, 'rb').read()
+        data = open(seg, 'rb').read()
         image.add_segment(addr, data)
     image.entrypoint = args.entrypoint
     image.save(args.output)
@@ -1026,7 +1026,7 @@ def read_flash(esp, args):
     t = time.time() - t
     print('\rRead %d bytes at 0x%x in %.1f seconds (%.1f kbit/s)...'
            % (len(data), args.address, t, len(data) / t * 8 / 1000))
-    file(args.filename, 'wb').write(data)
+    open(args.filename, 'wb').write(data)
 
 
 def _verify_flash(flasher, args, flash_params=None):
@@ -1235,7 +1235,7 @@ class AddrFilenamePairAction(argparse.Action):
         for i in range(0,len(values),2):
             try:
                 address = int(values[i],0)
-            except ValueError as e:
+            except ValueError:
                 raise argparse.ArgumentError(self,'Address "%s" must be a number' % values[i])
             try:
                 argfile = open(values[i + 1], 'rb')

python/isotp.py

@@ -6,7 +6,7 @@ def msg(x):
   if DEBUG:
     print("S:", binascii.hexlify(x))
   if len(x) <= 7:
-    ret = chr(len(x)) + x
+    ret = bytes([len(x)]) + x
   else:
     assert False
   return ret.ljust(8, b"\x00")
@@ -40,7 +40,7 @@ def isotp_recv_subaddr(panda, addr, bus, sendaddr, subaddr):
     dat = msg[3:]
 
     # 0 block size?
-    CONTINUE = chr(subaddr).encode("utf8") + b"\x30" + b"\x00"*6
+    CONTINUE = bytes([subaddr]) + b"\x30" + b"\x00"*6
     panda.can_send(sendaddr, CONTINUE, bus)
 
     idx = 1
@@ -68,22 +68,22 @@ def isotp_send(panda, x, addr, bus=0, recvaddr=None, subaddr=None):
   if len(x) <= 7 and subaddr is None:
     panda.can_send(addr, msg(x), bus)
   elif len(x) <= 6 and subaddr is not None:
-    panda.can_send(addr, chr(subaddr)+msg(x)[0:7], bus)
+    panda.can_send(addr, bytes([subaddr]) + msg(x)[0:7], bus)
   else:
     if subaddr:
-      ss = (chr(subaddr) + chr(0x10 + (len(x)>>8)) + chr(len(x)&0xFF)).encode("utf8") + x[0:5]
+      ss = bytes([subaddr, 0x10 + (len(x) >> 8), len(x) & 0xFF]) + x[0:5]
       x = x[5:]
     else:
-      ss = (chr(0x10 + (len(x)>>8)) + chr(len(x)&0xFF)).encode("utf8") + x[0:6]
+      ss = bytes([0x10 + (len(x) >> 8), len(x) & 0xFF]) + x[0:6]
       x = x[6:]
     idx = 1
     sends = []
     while len(x) > 0:
       if subaddr:
-        sends.append((((chr(subaddr) + chr(0x20 + (idx&0xF))).encode('utf8') + x[0:6]).ljust(8, b"\x00")))
+        sends.append(((bytes([subaddr, 0x20 + (idx & 0xF)]) + x[0:6]).ljust(8, b"\x00")))
         x = x[6:]
       else:
-        sends.append(((chr(0x20 + (idx&0xF)).encode("utf8") + x[0:7]).ljust(8, b"\x00")))
+        sends.append(((bytes([0x20 + (idx & 0xF)]) + x[0:7]).ljust(8, b"\x00")))
         x = x[7:]
       idx += 1
 

python/serial.py

@@ -19,10 +19,7 @@ class PandaSerial(object):
   def write(self, dat):
     #print "W: ", dat.encode("hex")
     #print '  pigeon_send("' + ''.join(map(lambda x: "\\x%02X" % ord(x), dat)) + '");'
-    if(isinstance(dat, bytes)):
     return self.panda.serial_write(self.port, dat)
-    else:
-      return self.panda.serial_write(self.port, str.encode(dat))
 
   def close(self):
     pass

python/uds.py

@@ -0,0 +1,770 @@
+#!/usr/bin/env python3
+import time
+import struct
+from typing import NamedTuple, List
+from enum import IntEnum
+from queue import Queue, Empty
+from threading import Thread
+from binascii import hexlify
+
+class SERVICE_TYPE(IntEnum):
+  DIAGNOSTIC_SESSION_CONTROL         = 0x10
+  ECU_RESET                          = 0x11
+  SECURITY_ACCESS                    = 0x27
+  COMMUNICATION_CONTROL              = 0x28
+  TESTER_PRESENT                     = 0x3E
+  ACCESS_TIMING_PARAMETER            = 0x83
+  SECURED_DATA_TRANSMISSION          = 0x84
+  CONTROL_DTC_SETTING                = 0x85
+  RESPONSE_ON_EVENT                  = 0x86
+  LINK_CONTROL                       = 0x87
+  READ_DATA_BY_IDENTIFIER            = 0x22
+  READ_MEMORY_BY_ADDRESS             = 0x23
+  READ_SCALING_DATA_BY_IDENTIFIER    = 0x24
+  READ_DATA_BY_PERIODIC_IDENTIFIER   = 0x2A
+  DYNAMICALLY_DEFINE_DATA_IDENTIFIER = 0x2C
+  WRITE_DATA_BY_IDENTIFIER           = 0x2E
+  WRITE_MEMORY_BY_ADDRESS            = 0x3D
+  CLEAR_DIAGNOSTIC_INFORMATION       = 0x14
+  READ_DTC_INFORMATION               = 0x19
+  INPUT_OUTPUT_CONTROL_BY_IDENTIFIER = 0x2F
+  ROUTINE_CONTROL                    = 0x31
+  REQUEST_DOWNLOAD                   = 0x34
+  REQUEST_UPLOAD                     = 0x35
+  TRANSFER_DATA                      = 0x36
+  REQUEST_TRANSFER_EXIT              = 0x37
+
+class SESSION_TYPE(IntEnum):
+  DEFAULT = 1
+  PROGRAMMING = 2
+  EXTENDED_DIAGNOSTIC = 3
+  SAFETY_SYSTEM_DIAGNOSTIC = 4
+
+class RESET_TYPE(IntEnum):
+  HARD = 1
+  KEY_OFF_ON = 2
+  SOFT = 3
+  ENABLE_RAPID_POWER_SHUTDOWN = 4
+  DISABLE_RAPID_POWER_SHUTDOWN = 5
+
+class ACCESS_TYPE(IntEnum):
+  REQUEST_SEED = 1
+  SEND_KEY = 2
+
+class CONTROL_TYPE(IntEnum):
+  ENABLE_RX_ENABLE_TX = 0
+  ENABLE_RX_DISABLE_TX = 1
+  DISABLE_RX_ENABLE_TX = 2
+  DISABLE_RX_DISABLE_TX = 3
+
+class MESSAGE_TYPE(IntEnum):
+  NORMAL = 1
+  NETWORK_MANAGEMENT = 2
+  NORMAL_AND_NETWORK_MANAGEMENT = 3
+
+class TIMING_PARAMETER_TYPE(IntEnum):
+  READ_EXTENDED_SET = 1
+  SET_TO_DEFAULT_VALUES = 2
+  READ_CURRENTLY_ACTIVE = 3
+  SET_TO_GIVEN_VALUES = 4
+
+class DTC_SETTING_TYPE(IntEnum):
+  ON = 1
+  OFF = 2
+
+class RESPONSE_EVENT_TYPE(IntEnum):
+  STOP_RESPONSE_ON_EVENT = 0
+  ON_DTC_STATUS_CHANGE = 1
+  ON_TIMER_INTERRUPT = 2
+  ON_CHANGE_OF_DATA_IDENTIFIER = 3
+  REPORT_ACTIVATED_EVENTS = 4
+  START_RESPONSE_ON_EVENT = 5
+  CLEAR_RESPONSE_ON_EVENT = 6
+  ON_COMPARISON_OF_VALUES = 7
+
+class LINK_CONTROL_TYPE(IntEnum):
+  VERIFY_BAUDRATE_TRANSITION_WITH_FIXED_BAUDRATE = 1
+  VERIFY_BAUDRATE_TRANSITION_WITH_SPECIFIC_BAUDRATE = 2
+  TRANSITION_BAUDRATE = 3
+
+class BAUD_RATE_TYPE(IntEnum):
+  PC9600 = 1
+  PC19200 = 2
+  PC38400 = 3
+  PC57600 = 4
+  PC115200 = 5
+  CAN125000 = 16
+  CAN250000 = 17
+  CAN500000 = 18
+  CAN1000000 = 19
+
+class DATA_IDENTIFIER_TYPE(IntEnum):
+  BOOT_SOFTWARE_IDENTIFICATION = 0xF180
+  APPLICATION_SOFTWARE_IDENTIFICATION = 0xF181
+  APPLICATION_DATA_IDENTIFICATION = 0xF182
+  BOOT_SOFTWARE_FINGERPRINT = 0xF183
+  APPLICATION_SOFTWARE_FINGERPRINT = 0xF184
+  APPLICATION_DATA_FINGERPRINT = 0xF185
+  ACTIVE_DIAGNOSTIC_SESSION = 0xF186
+  VEHICLE_MANUFACTURER_SPARE_PART_NUMBER = 0xF187
+  VEHICLE_MANUFACTURER_ECU_SOFTWARE_NUMBER = 0xF188
+  VEHICLE_MANUFACTURER_ECU_SOFTWARE_VERSION_NUMBER = 0xF189
+  SYSTEM_SUPPLIER_IDENTIFIER = 0xF18A
+  ECU_MANUFACTURING_DATE = 0xF18B
+  ECU_SERIAL_NUMBER = 0xF18C
+  SUPPORTED_FUNCTIONAL_UNITS = 0xF18D
+  VEHICLE_MANUFACTURER_KIT_ASSEMBLY_PART_NUMBER = 0xF18E
+  VIN = 0xF190
+  VEHICLE_MANUFACTURER_ECU_HARDWARE_NUMBER = 0xF191
+  SYSTEM_SUPPLIER_ECU_HARDWARE_NUMBER = 0xF192
+  SYSTEM_SUPPLIER_ECU_HARDWARE_VERSION_NUMBER = 0xF193
+  SYSTEM_SUPPLIER_ECU_SOFTWARE_NUMBER = 0xF194
+  SYSTEM_SUPPLIER_ECU_SOFTWARE_VERSION_NUMBER = 0xF195
+  EXHAUST_REGULATION_OR_TYPE_APPROVAL_NUMBER = 0xF196
+  SYSTEM_NAME_OR_ENGINE_TYPE = 0xF197
+  REPAIR_SHOP_CODE_OR_TESTER_SERIAL_NUMBER = 0xF198
+  PROGRAMMING_DATE = 0xF199
+  CALIBRATION_REPAIR_SHOP_CODE_OR_CALIBRATION_EQUIPMENT_SERIAL_NUMBER = 0xF19A
+  CALIBRATION_DATE = 0xF19B
+  CALIBRATION_EQUIPMENT_SOFTWARE_NUMBER = 0xF19C
+  ECU_INSTALLATION_DATE = 0xF19D
+  ODX_FILE = 0xF19E
+  ENTITY = 0xF19F
+
+class TRANSMISSION_MODE_TYPE(IntEnum):
+  SEND_AT_SLOW_RATE = 1
+  SEND_AT_MEDIUM_RATE = 2
+  SEND_AT_FAST_RATE = 3
+  STOP_SENDING = 4
+
+class DYNAMIC_DEFINITION_TYPE(IntEnum):
+  DEFINE_BY_IDENTIFIER = 1
+  DEFINE_BY_MEMORY_ADDRESS = 2
+  CLEAR_DYNAMICALLY_DEFINED_DATA_IDENTIFIER = 3
+
+class DynamicSourceDefinition(NamedTuple):
+  data_identifier: int
+  position: int
+  memory_size: int
+  memory_address: int
+
+class DTC_GROUP_TYPE(IntEnum):
+  EMISSIONS = 0x000000
+  ALL = 0xFFFFFF
+
+class DTC_REPORT_TYPE(IntEnum):
+  NUMBER_OF_DTC_BY_STATUS_MASK = 0x01
+  DTC_BY_STATUS_MASK = 0x02
+  DTC_SNAPSHOT_IDENTIFICATION = 0x03
+  DTC_SNAPSHOT_RECORD_BY_DTC_NUMBER = 0x04
+  DTC_SNAPSHOT_RECORD_BY_RECORD_NUMBER = 0x05
+  DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER = 0x06
+  NUMBER_OF_DTC_BY_SEVERITY_MASK_RECORD = 0x07
+  DTC_BY_SEVERITY_MASK_RECORD = 0x08
+  SEVERITY_INFORMATION_OF_DTC = 0x09
+  SUPPORTED_DTC = 0x0A
+  FIRST_TEST_FAILED_DTC = 0x0B
+  FIRST_CONFIRMED_DTC = 0x0C
+  MOST_RECENT_TEST_FAILED_DTC = 0x0D
+  MOST_RECENT_CONFIRMED_DTC = 0x0E
+  MIRROR_MEMORY_DTC_BY_STATUS_MASK = 0x0F
+  MIRROR_MEMORY_DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER = 0x10
+  NUMBER_OF_MIRROR_MEMORY_DTC_BY_STATUS_MASK = 0x11
+  NUMBER_OF_EMISSIONS_RELATED_OBD_DTC_BY_STATUS_MASK = 0x12
+  EMISSIONS_RELATED_OBD_DTC_BY_STATUS_MASK = 0x13
+  DTC_FAULT_DETECTION_COUNTER = 0x14
+  DTC_WITH_PERMANENT_STATUS = 0x15
+
+class DTC_STATUS_MASK_TYPE(IntEnum):
+  TEST_FAILED = 0x01
+  TEST_FAILED_THIS_OPERATION_CYCLE = 0x02
+  PENDING_DTC = 0x04
+  CONFIRMED_DTC = 0x08
+  TEST_NOT_COMPLETED_SINCE_LAST_CLEAR = 0x10
+  TEST_FAILED_SINCE_LAST_CLEAR = 0x20
+  TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE = 0x40
+  WARNING_INDICATOR_REQUESTED = 0x80
+  ALL = 0xFF
+
+class DTC_SEVERITY_MASK_TYPE(IntEnum):
+  MAINTENANCE_ONLY = 0x20
+  CHECK_AT_NEXT_HALT = 0x40
+  CHECK_IMMEDIATELY = 0x80
+  ALL = 0xE0
+
+class CONTROL_PARAMETER_TYPE(IntEnum):
+  RETURN_CONTROL_TO_ECU = 0
+  RESET_TO_DEFAULT = 1
+  FREEZE_CURRENT_STATE = 2
+  SHORT_TERM_ADJUSTMENT = 3
+
+class ROUTINE_CONTROL_TYPE(IntEnum):
+  START = 1
+  STOP = 2
+  REQUEST_RESULTS = 3
+
+class ROUTINE_IDENTIFIER_TYPE(IntEnum):
+  ERASE_MEMORY = 0xFF00
+  CHECK_PROGRAMMING_DEPENDENCIES = 0xFF01
+  ERASE_MIRROR_MEMORY_DTCS = 0xFF02
+
+class MessageTimeoutError(Exception):
+  pass
+
+class NegativeResponseError(Exception):
+  def __init__(self, message, service_id, error_code):
+    self.message = message
+    self.service_id = service_id
+    self.error_code = error_code
+
+  def __str__(self):
+    return self.message
+
+class InvalidServiceIdError(Exception):
+  pass
+
+class InvalidSubFunctioneError(Exception):
+  pass
+
+_negative_response_codes = {
+    0x00: 'positive response',
+    0x10: 'general reject',
+    0x11: 'service not supported',
+    0x12: 'sub-function not supported',
+    0x13: 'incorrect message length or invalid format',
+    0x14: 'response too long',
+    0x21: 'busy repeat request',
+    0x22: 'conditions not correct',
+    0x24: 'request sequence error',
+    0x25: 'no response from subnet component',
+    0x26: 'failure prevents execution of requested action',
+    0x31: 'request out of range',
+    0x33: 'security access denied',
+    0x35: 'invalid key',
+    0x36: 'exceed numebr of attempts',
+    0x37: 'required time delay not expired',
+    0x70: 'upload download not accepted',
+    0x71: 'transfer data suspended',
+    0x72: 'general programming failure',
+    0x73: 'wrong block sequence counter',
+    0x78: 'request correctly received - response pending',
+    0x7e: 'sub-function not supported in active session',
+    0x7f: 'service not supported in active session',
+    0x81: 'rpm too high',
+    0x82: 'rpm too low',
+    0x83: 'engine is running',
+    0x84: 'engine is not running',
+    0x85: 'engine run time too low',
+    0x86: 'temperature too high',
+    0x87: 'temperature too low',
+    0x88: 'vehicle speed too high',
+    0x89: 'vehicle speed too low',
+    0x8a: 'throttle/pedal too high',
+    0x8b: 'throttle/pedal too low',
+    0x8c: 'transmission not in neutral',
+    0x8d: 'transmission not in gear',
+    0x8f: 'brake switch(es) not closed',
+    0x90: 'shifter lever not in park',
+    0x91: 'torque converter clutch locked',
+    0x92: 'voltage too high',
+    0x93: 'voltage too low',
+}
+
+class IsoTpMessage():
+  def __init__(self, can_tx_queue: Queue, can_rx_queue: Queue, timeout: float, debug: bool=False):
+    self.can_tx_queue = can_tx_queue
+    self.can_rx_queue = can_rx_queue
+    self.timeout = timeout
+    self.debug = debug
+
+  def send(self, dat: bytes) -> None:
+    self.tx_dat = dat
+    self.tx_len = len(dat)
+    self.tx_idx = 0
+    self.tx_done = False
+
+    if self.debug: print(f"ISO-TP: REQUEST - {hexlify(self.tx_dat)}")
+    self._tx_first_frame()
+
+  def _tx_first_frame(self) -> None:
+    if self.tx_len < 8:
+      # single frame (send all bytes)
+      if self.debug: print("ISO-TP: TX - single frame")
+      msg = (bytes([self.tx_len]) + self.tx_dat).ljust(8, b"\x00")
+      self.tx_done = True
+    else:
+      # first frame (send first 6 bytes)
+      if self.debug: print("ISO-TP: TX - first frame")
+      msg = (struct.pack("!H", 0x1000 | self.tx_len) + self.tx_dat[:6]).ljust(8, b"\x00")
+    self.can_tx_queue.put(msg)
+
+  def recv(self) -> bytes:
+    self.rx_dat = b""
+    self.rx_len = 0
+    self.rx_idx = 0
+    self.rx_done = False
+
+    try:
+      while True:
+        self._isotp_rx_next()
+        if self.tx_done and self.rx_done:
+          return self.rx_dat
+    except Empty:
+      raise MessageTimeoutError("timeout waiting for response")
+    finally:
+      if self.debug: print(f"ISO-TP: RESPONSE - {hexlify(self.rx_dat)}")
+
+  def _isotp_rx_next(self) -> None:
+    rx_data = self.can_rx_queue.get(block=True, timeout=self.timeout)
+
+    # single rx_frame
+    if rx_data[0] >> 4 == 0x0:
+      self.rx_len = rx_data[0] & 0xFF
+      self.rx_dat = rx_data[1:1+self.rx_len]
+      self.rx_idx = 0
+      self.rx_done = True
+      if self.debug: print(f"ISO-TP: RX - single frame - idx={self.rx_idx} done={self.rx_done}")
+      return
+
+    # first rx_frame
+    if rx_data[0] >> 4 == 0x1:
+      self.rx_len = ((rx_data[0] & 0x0F) << 8) + rx_data[1]
+      self.rx_dat = rx_data[2:]
+      self.rx_idx = 0
+      self.rx_done = False
+      if self.debug: print(f"ISO-TP: RX - first frame - idx={self.rx_idx} done={self.rx_done}")
+      if self.debug: print(f"ISO-TP: TX - flow control continue")
+      # send flow control message (send all bytes)
+      msg = b"\x30\x00\x00".ljust(8, b"\x00")
+      self.can_tx_queue.put(msg)
+      return
+    
+    # consecutive rx frame
+    if rx_data[0] >> 4 == 0x2:
+      assert self.rx_done == False, "isotp - rx: consecutive frame with no active frame"
+      self.rx_idx += 1
+      assert self.rx_idx & 0xF == rx_data[0] & 0xF, "isotp - rx: invalid consecutive frame index"
+      rx_size = self.rx_len - len(self.rx_dat)
+      self.rx_dat += rx_data[1:1+min(rx_size, 7)]
+      if self.rx_len == len(self.rx_dat):
+        self.rx_done = True
+      if self.debug: print(f"ISO-TP: RX - consecutive frame - idx={self.rx_idx} done={self.rx_done}")
+      return
+
+    # flow control
+    if rx_data[0] >> 4 == 0x3:
+      assert self.tx_done == False, "isotp - rx: flow control with no active frame"
+      assert rx_data[0] != 0x32, "isotp - rx: flow-control overflow/abort"
+      assert rx_data[0] == 0x30 or rx_data[0] == 0x31, "isotp - rx: flow-control transfer state indicator invalid"
+      if rx_data[0] == 0x30:
+        if self.debug: print("ISO-TP: RX - flow control continue")
+        delay_ts = rx_data[2] & 0x7F
+        # scale is 1 milliseconds if first bit == 0, 100 micro seconds if first bit == 1
+        delay_div = 1000. if rx_data[2] & 0x80 == 0 else 10000.
+        # first frame = 6 bytes, each consecutive frame = 7 bytes
+        start = 6 + self.tx_idx * 7
+        count = rx_data[1]
+        end = start + count * 7 if count > 0 else self.tx_len
+        for i in range(start, end, 7):
+          if delay_ts > 0 and i > start:
+            delay_s = delay_ts / delay_div
+            if self.debug: print(f"ISO-TP: TX - delay - seconds={delay_s}")
+            time.sleep(delay_s)
+          self.tx_idx += 1
+          # consecutive tx frames
+          msg = (bytes([0x20 | (self.tx_idx & 0xF)]) + self.tx_dat[i:i+7]).ljust(8, b"\x00")
+          self.can_tx_queue.put(msg)
+        if end >= self.tx_len:
+          self.tx_done = True
+        if self.debug: print(f"ISO-TP: TX - consecutive frame - idx={self.tx_idx} done={self.tx_done}")
+      elif rx_data[0] == 0x31:
+        # wait (do nothing until next flow control message)
+        if self.debug: print("ISO-TP: TX - flow control wait")
+
+class UdsClient():
+  def __init__(self, panda, tx_addr: int, rx_addr: int=None, bus: int=0, timeout: float=10, debug: bool=False):
+    self.panda = panda
+    self.bus = bus
+    self.tx_addr = tx_addr
+    if rx_addr == None:
+      if tx_addr < 0xFFF8:
+        # standard 11 bit response addr (add 8)
+        self.rx_addr = tx_addr+8
+      elif tx_addr > 0x10000000 and tx_addr < 0xFFFFFFFF:
+        # standard 29 bit response addr (flip last two bytes)
+        self.rx_addr = (tx_addr & 0xFFFF0000) + (tx_addr<<8 & 0xFF00) + (tx_addr>>8 & 0xFF)
+      else:
+        raise ValueError("invalid tx_addr: {}".format(tx_addr))
+
+    self.can_tx_queue = Queue()
+    self.can_rx_queue = Queue()
+    self.timeout = timeout
+    self.debug = debug
+
+    self.can_thread = Thread(target=self._can_thread, args=(self.debug,))
+    self.can_thread.daemon = True
+    self.can_thread.start()
+
+  def _can_thread(self, debug: bool=False):
+    try:
+      # allow all output
+      self.panda.set_safety_mode(0x1337)
+      # clear tx buffer
+      self.panda.can_clear(self.bus)
+      # clear rx buffer
+      self.panda.can_clear(0xFFFF)
+
+      while True:
+        # send
+        while not self.can_tx_queue.empty():
+          msg = self.can_tx_queue.get(block=False)
+          if debug: print("CAN-TX: {} - {}".format(hex(self.tx_addr), hexlify(msg)))
+          self.panda.can_send(self.tx_addr, msg, self.bus)
+
+        # receive
+        msgs = self.panda.can_recv()
+        for rx_addr, rx_ts, rx_data, rx_bus in msgs:
+          if rx_bus != self.bus or rx_addr != self.rx_addr or len(rx_data) == 0:
+            continue
+          if debug: print("CAN-RX: {} - {}".format(hex(self.rx_addr), hexlify(rx_data)))
+          self.can_rx_queue.put(rx_data)
+        else:
+          time.sleep(0.01)
+    finally:
+      self.panda.close()
+
+  # generic uds request
+  def _uds_request(self, service_type: SERVICE_TYPE, subfunction: int=None, data: bytes=None) -> bytes:
+    req = bytes([service_type])
+    if subfunction is not None:
+      req += bytes([subfunction])
+    if data is not None:
+      req += data
+
+    # send request, wait for response
+    isotp_msg = IsoTpMessage(self.can_tx_queue, self.can_rx_queue, self.timeout, self.debug)
+    isotp_msg.send(req)
+    while True:
+      resp = isotp_msg.recv()
+      resp_sid = resp[0] if len(resp) > 0 else None
+
+      # negative response
+      if resp_sid == 0x7F:
+        service_id = resp[1] if len(resp) > 1 else -1
+        try:
+          service_desc = SERVICE_TYPE(service_id).name
+        except Exception:
+          service_desc = 'NON_STANDARD_SERVICE'
+        error_code = resp[2] if len(resp) > 2 else -1
+        try:
+          error_desc = _negative_response_codes[error_code]
+        except Exception:
+          error_desc = resp[3:]
+        # wait for another message if response pending
+        if error_code == 0x78:
+          if self.debug: print("UDS-RX: response pending")
+          continue
+        raise NegativeResponseError('{} - {}'.format(service_desc, error_desc), service_id, error_code)
+
+      # positive response
+      if service_type+0x40 != resp_sid:
+        resp_sid_hex = hex(resp_sid) if resp_sid is not None else None
+        raise InvalidServiceIdError('invalid response service id: {}'.format(resp_sid_hex))
+
+      if subfunction is not None:
+        resp_sfn = resp[1] if len(resp) > 1 else None
+        if subfunction != resp_sfn:
+          resp_sfn_hex = hex(resp_sfn) if resp_sfn is not None else None
+          raise InvalidSubFunctioneError('invalid response subfunction: {}'.format(hex(resp_sfn_hex)))
+
+      # return data (exclude service id and sub-function id)
+      return resp[(1 if subfunction is None else 2):]
+
+  # services
+  def diagnostic_session_control(self, session_type: SESSION_TYPE):
+    self._uds_request(SERVICE_TYPE.DIAGNOSTIC_SESSION_CONTROL, subfunction=session_type)
+
+  def ecu_reset(self, reset_type: RESET_TYPE):
+    resp = self._uds_request(SERVICE_TYPE.ECU_RESET, subfunction=reset_type)
+    power_down_time = None
+    if reset_type == RESET_TYPE.ENABLE_RAPID_POWER_SHUTDOWN:
+      power_down_time = resp[0]
+      return power_down_time
+
+  def security_access(self, access_type: ACCESS_TYPE, security_key: bytes=None):
+    request_seed = access_type % 2 != 0
+    if request_seed and security_key is not None:
+      raise ValueError('security_key not allowed')
+    if not request_seed and security_key is None:
+      raise ValueError('security_key is missing')
+    resp = self._uds_request(SERVICE_TYPE.SECURITY_ACCESS, subfunction=access_type, data=security_key)
+    if request_seed:
+      security_seed = resp
+      return security_seed
+
+  def communication_control(self, control_type: CONTROL_TYPE, message_type: MESSAGE_TYPE):
+    data = bytes([message_type])
+    self._uds_request(SERVICE_TYPE.COMMUNICATION_CONTROL, subfunction=control_type, data=data)
+
+  def tester_present(self, ):
+    self._uds_request(SERVICE_TYPE.TESTER_PRESENT, subfunction=0x00)
+
+  def access_timing_parameter(self, timing_parameter_type: TIMING_PARAMETER_TYPE, parameter_values: bytes=None):
+    write_custom_values = timing_parameter_type == TIMING_PARAMETER_TYPE.SET_TO_GIVEN_VALUES
+    read_values = (
+      timing_parameter_type == TIMING_PARAMETER_TYPE.READ_CURRENTLY_ACTIVE or
+      timing_parameter_type == TIMING_PARAMETER_TYPE.READ_EXTENDED_SET
+    )
+    if not write_custom_values and parameter_values is not None:
+      raise ValueError('parameter_values not allowed')
+    if write_custom_values and parameter_values is None:
+      raise ValueError('parameter_values is missing')
+    resp = self._uds_request(SERVICE_TYPE.ACCESS_TIMING_PARAMETER, subfunction=timing_parameter_type, data=parameter_values)
+    if read_values:
+      # TODO: parse response into values?
+      parameter_values = resp
+      return parameter_values
+
+  def secured_data_transmission(self, data: bytes):
+    # TODO: split data into multiple input parameters?
+    resp = self._uds_request(SERVICE_TYPE.SECURED_DATA_TRANSMISSION, subfunction=None, data=data)
+    # TODO: parse response into multiple output values?
+    return resp
+
+  def control_dtc_setting(self, dtc_setting_type: DTC_SETTING_TYPE):
+    self._uds_request(SERVICE_TYPE.CONTROL_DTC_SETTING, subfunction=dtc_setting_type)
+
+  def response_on_event(self, response_event_type: RESPONSE_EVENT_TYPE, store_event: bool, window_time: int, event_type_record: int, service_response_record: int):
+    if store_event:
+      response_event_type |= 0x20
+    # TODO: split record parameters into arrays
+    data = bytes([window_time, event_type_record, service_response_record])
+    resp = self._uds_request(SERVICE_TYPE.RESPONSE_ON_EVENT, subfunction=response_event_type, data=data)
+
+    if response_event_type == RESPONSE_EVENT_TYPE.REPORT_ACTIVATED_EVENTS:
+      return {
+        "num_of_activated_events": resp[0],
+        "data": resp[1:], # TODO: parse the reset of response
+      }
+
+    return {
+      "num_of_identified_events": resp[0],
+      "event_window_time": resp[1],
+      "data": resp[2:], # TODO: parse the reset of response
+    }
+
+  def link_control(self, link_control_type: LINK_CONTROL_TYPE, baud_rate_type: BAUD_RATE_TYPE=None):
+    if link_control_type == LINK_CONTROL_TYPE.VERIFY_BAUDRATE_TRANSITION_WITH_FIXED_BAUDRATE:
+      # baud_rate_type = BAUD_RATE_TYPE
+      data = bytes([baud_rate_type])
+    elif link_control_type == LINK_CONTROL_TYPE.VERIFY_BAUDRATE_TRANSITION_WITH_SPECIFIC_BAUDRATE:
+      # baud_rate_type = custom value (3 bytes big-endian)
+      data = struct.pack('!I', baud_rate_type)[1:]
+    else:
+      data = None
+    self._uds_request(SERVICE_TYPE.LINK_CONTROL, subfunction=link_control_type, data=data)
+
+  def read_data_by_identifier(self, data_identifier_type: DATA_IDENTIFIER_TYPE):
+    # TODO: support list of identifiers
+    data = struct.pack('!H', data_identifier_type)
+    resp = self._uds_request(SERVICE_TYPE.READ_DATA_BY_IDENTIFIER, subfunction=None, data=data)
+    resp_id = struct.unpack('!H', resp[0:2])[0] if len(resp) >= 2 else None
+    if resp_id != data_identifier_type:
+      raise ValueError('invalid response data identifier: {}'.format(hex(resp_id)))
+    return resp[2:]
+
+  def read_memory_by_address(self, memory_address: int, memory_size: int, memory_address_bytes: int=4, memory_size_bytes: int=1):
+    if memory_address_bytes < 1 or memory_address_bytes > 4:
+      raise ValueError('invalid memory_address_bytes: {}'.format(memory_address_bytes))
+    if memory_size_bytes < 1 or memory_size_bytes > 4:
+      raise ValueError('invalid memory_size_bytes: {}'.format(memory_size_bytes))
+    data = bytes([memory_size_bytes<<4 | memory_address_bytes])
+
+    if memory_address >= 1<<(memory_address_bytes*8):
+      raise ValueError('invalid memory_address: {}'.format(memory_address))
+    data += struct.pack('!I', memory_address)[4-memory_address_bytes:]
+    if memory_size >= 1<<(memory_size_bytes*8):
+      raise ValueError('invalid memory_size: {}'.format(memory_size))
+    data += struct.pack('!I', memory_size)[4-memory_size_bytes:]
+
+    resp = self._uds_request(SERVICE_TYPE.READ_MEMORY_BY_ADDRESS, subfunction=None, data=data)
+    return resp
+
+  def read_scaling_data_by_identifier(self, data_identifier_type: DATA_IDENTIFIER_TYPE):
+    data = struct.pack('!H', data_identifier_type)
+    resp = self._uds_request(SERVICE_TYPE.READ_SCALING_DATA_BY_IDENTIFIER, subfunction=None, data=data)
+    resp_id = struct.unpack('!H', resp[0:2])[0] if len(resp) >= 2 else None
+    if resp_id != data_identifier_type:
+      raise ValueError('invalid response data identifier: {}'.format(hex(resp_id)))
+    return resp[2:] # TODO: parse the response
+
+  def read_data_by_periodic_identifier(self, transmission_mode_type: TRANSMISSION_MODE_TYPE, periodic_data_identifier: int):
+    # TODO: support list of identifiers
+    data = bytes([transmission_mode_type, periodic_data_identifier])
+    self._uds_request(SERVICE_TYPE.READ_DATA_BY_PERIODIC_IDENTIFIER, subfunction=None, data=data)
+
+  def dynamically_define_data_identifier(self, dynamic_definition_type: DYNAMIC_DEFINITION_TYPE, dynamic_data_identifier: int, source_definitions: List[DynamicSourceDefinition], memory_address_bytes: int=4, memory_size_bytes: int=1):
+    if memory_address_bytes < 1 or memory_address_bytes > 4:
+      raise ValueError('invalid memory_address_bytes: {}'.format(memory_address_bytes))
+    if memory_size_bytes < 1 or memory_size_bytes > 4:
+      raise ValueError('invalid memory_size_bytes: {}'.format(memory_size_bytes))
+
+    data = struct.pack('!H', dynamic_data_identifier)
+    if dynamic_definition_type == DYNAMIC_DEFINITION_TYPE.DEFINE_BY_IDENTIFIER:
+      for s in source_definitions:
+        data += struct.pack('!H', s["data_identifier"]) + bytes([s["position"], s["memory_size"]])
+    elif dynamic_definition_type == DYNAMIC_DEFINITION_TYPE.DEFINE_BY_MEMORY_ADDRESS:
+      data += bytes([memory_size_bytes<<4 | memory_address_bytes])
+      for s in source_definitions:
+        if s["memory_address"] >= 1<<(memory_address_bytes*8):
+          raise ValueError('invalid memory_address: {}'.format(s["memory_address"]))
+        data += struct.pack('!I', s["memory_address"])[4-memory_address_bytes:]
+        if s["memory_size"] >= 1<<(memory_size_bytes*8):
+          raise ValueError('invalid memory_size: {}'.format(s["memory_size"]))
+        data += struct.pack('!I', s["memory_size"])[4-memory_size_bytes:]
+    elif dynamic_definition_type == DYNAMIC_DEFINITION_TYPE.CLEAR_DYNAMICALLY_DEFINED_DATA_IDENTIFIER:
+      pass
+    else:
+      raise ValueError('invalid dynamic identifier type: {}'.format(hex(dynamic_definition_type)))
+    self._uds_request(SERVICE_TYPE.DYNAMICALLY_DEFINE_DATA_IDENTIFIER, subfunction=dynamic_definition_type, data=data)
+
+  def write_data_by_identifier(self, data_identifier_type: DATA_IDENTIFIER_TYPE, data_record: bytes):
+    data = struct.pack('!H', data_identifier_type) + data_record
+    resp = self._uds_request(SERVICE_TYPE.WRITE_DATA_BY_IDENTIFIER, subfunction=None, data=data)
+    resp_id = struct.unpack('!H', resp[0:2])[0] if len(resp) >= 2 else None
+    if resp_id != data_identifier_type:
+      raise ValueError('invalid response data identifier: {}'.format(hex(resp_id)))
+
+  def write_memory_by_address(self, memory_address: int, memory_size: int, data_record: bytes, memory_address_bytes: int=4, memory_size_bytes: int=1):
+    if memory_address_bytes < 1 or memory_address_bytes > 4:
+      raise ValueError('invalid memory_address_bytes: {}'.format(memory_address_bytes))
+    if memory_size_bytes < 1 or memory_size_bytes > 4:
+      raise ValueError('invalid memory_size_bytes: {}'.format(memory_size_bytes))
+    data = bytes([memory_size_bytes<<4 | memory_address_bytes])
+
+    if memory_address >= 1<<(memory_address_bytes*8):
+      raise ValueError('invalid memory_address: {}'.format(memory_address))
+    data += struct.pack('!I', memory_address)[4-memory_address_bytes:]
+    if memory_size >= 1<<(memory_size_bytes*8):
+      raise ValueError('invalid memory_size: {}'.format(memory_size))
+    data += struct.pack('!I', memory_size)[4-memory_size_bytes:]
+
+    data += data_record
+    self._uds_request(SERVICE_TYPE.WRITE_MEMORY_BY_ADDRESS, subfunction=0x00, data=data)
+
+  def clear_diagnostic_information(self, dtc_group_type: DTC_GROUP_TYPE):
+    data = struct.pack('!I', dtc_group_type)[1:] # 3 bytes
+    self._uds_request(SERVICE_TYPE.CLEAR_DIAGNOSTIC_INFORMATION, subfunction=None, data=data)
+
+  def read_dtc_information(self, dtc_report_type: DTC_REPORT_TYPE, dtc_status_mask_type: DTC_STATUS_MASK_TYPE=DTC_STATUS_MASK_TYPE.ALL, dtc_severity_mask_type: DTC_SEVERITY_MASK_TYPE=DTC_SEVERITY_MASK_TYPE.ALL, dtc_mask_record: int=0xFFFFFF, dtc_snapshot_record_num: int=0xFF, dtc_extended_record_num: int=0xFF):
+    data = b''
+    # dtc_status_mask_type
+    if dtc_report_type == DTC_REPORT_TYPE.NUMBER_OF_DTC_BY_STATUS_MASK or \
+      dtc_report_type == DTC_REPORT_TYPE.DTC_BY_STATUS_MASK or \
+      dtc_report_type == DTC_REPORT_TYPE.MIRROR_MEMORY_DTC_BY_STATUS_MASK or \
+      dtc_report_type == DTC_REPORT_TYPE.NUMBER_OF_MIRROR_MEMORY_DTC_BY_STATUS_MASK or \
+      dtc_report_type == DTC_REPORT_TYPE.NUMBER_OF_EMISSIONS_RELATED_OBD_DTC_BY_STATUS_MASK or \
+      dtc_report_type == DTC_REPORT_TYPE.EMISSIONS_RELATED_OBD_DTC_BY_STATUS_MASK:
+      data += bytes([dtc_status_mask_type])
+    # dtc_mask_record
+    if dtc_report_type == DTC_REPORT_TYPE.DTC_SNAPSHOT_IDENTIFICATION or \
+      dtc_report_type == DTC_REPORT_TYPE.DTC_SNAPSHOT_RECORD_BY_DTC_NUMBER or \
+      dtc_report_type == DTC_REPORT_TYPE.DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER or \
+      dtc_report_type == DTC_REPORT_TYPE.MIRROR_MEMORY_DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER or \
+      dtc_report_type == DTC_REPORT_TYPE.SEVERITY_INFORMATION_OF_DTC:
+      data += struct.pack('!I', dtc_mask_record)[1:] # 3 bytes
+    # dtc_snapshot_record_num
+    if dtc_report_type == DTC_REPORT_TYPE.DTC_SNAPSHOT_IDENTIFICATION or \
+      dtc_report_type == DTC_REPORT_TYPE.DTC_SNAPSHOT_RECORD_BY_DTC_NUMBER or \
+      dtc_report_type == DTC_REPORT_TYPE.DTC_SNAPSHOT_RECORD_BY_RECORD_NUMBER:
+      data += ord(dtc_snapshot_record_num)
+    # dtc_extended_record_num
+    if dtc_report_type == DTC_REPORT_TYPE.DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER or \
+      dtc_report_type == DTC_REPORT_TYPE.MIRROR_MEMORY_DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER:
+      data += bytes([dtc_extended_record_num])
+    # dtc_severity_mask_type
+    if dtc_report_type == DTC_REPORT_TYPE.NUMBER_OF_DTC_BY_SEVERITY_MASK_RECORD or \
+      dtc_report_type == DTC_REPORT_TYPE.DTC_BY_SEVERITY_MASK_RECORD:
+      data += bytes([dtc_severity_mask_type, dtc_status_mask_type])
+    
+    resp = self._uds_request(SERVICE_TYPE.READ_DTC_INFORMATION, subfunction=dtc_report_type, data=data)
+
+    # TODO: parse response
+    return resp
+
+  def input_output_control_by_identifier(self, data_identifier_type: DATA_IDENTIFIER_TYPE, control_parameter_type: CONTROL_PARAMETER_TYPE, control_option_record: bytes, control_enable_mask_record: bytes=b''):
+    data = struct.pack('!H', data_identifier_type) + bytes([control_parameter_type]) + control_option_record + control_enable_mask_record
+    resp = self._uds_request(SERVICE_TYPE.INPUT_OUTPUT_CONTROL_BY_IDENTIFIER, subfunction=None, data=data)
+    resp_id = struct.unpack('!H', resp[0:2])[0] if len(resp) >= 2 else None
+    if resp_id != data_identifier_type:
+      raise ValueError('invalid response data identifier: {}'.format(hex(resp_id)))
+    return resp[2:]
+
+  def routine_control(self, routine_control_type: ROUTINE_CONTROL_TYPE, routine_identifier_type: ROUTINE_IDENTIFIER_TYPE, routine_option_record: bytes=b''):
+    data = struct.pack('!H', routine_identifier_type) + routine_option_record
+    resp = self._uds_request(SERVICE_TYPE.ROUTINE_CONTROL, subfunction=routine_control_type, data=data)
+    resp_id = struct.unpack('!H', resp[0:2])[0] if len(resp) >= 2 else None
+    if resp_id != routine_identifier_type:
+      raise ValueError('invalid response routine identifier: {}'.format(hex(resp_id)))
+    return resp[2:]
+
+  def request_download(self, memory_address: int, memory_size: int, memory_address_bytes: int=4, memory_size_bytes: int=4, data_format: int=0x00):
+    data = bytes([data_format])
+
+    if memory_address_bytes < 1 or memory_address_bytes > 4:
+      raise ValueError('invalid memory_address_bytes: {}'.format(memory_address_bytes))
+    if memory_size_bytes < 1 or memory_size_bytes > 4:
+      raise ValueError('invalid memory_size_bytes: {}'.format(memory_size_bytes))
+    data += bytes([memory_size_bytes<<4 | memory_address_bytes])
+
+    if memory_address >= 1<<(memory_address_bytes*8):
+      raise ValueError('invalid memory_address: {}'.format(memory_address))
+    data += struct.pack('!I', memory_address)[4-memory_address_bytes:]
+    if memory_size >= 1<<(memory_size_bytes*8):
+      raise ValueError('invalid memory_size: {}'.format(memory_size))
+    data += struct.pack('!I', memory_size)[4-memory_size_bytes:]
+
+    resp = self._uds_request(SERVICE_TYPE.REQUEST_DOWNLOAD, subfunction=None, data=data)
+    max_num_bytes_len = resp[0] >> 4 if len(resp) > 0 else None
+    if max_num_bytes_len >= 1 and max_num_bytes_len <= 4:
+      max_num_bytes = struct.unpack('!I', (b"\x00"*(4-max_num_bytes_len))+resp[1:max_num_bytes_len+1])[0]
+    else:
+      raise ValueError('invalid max_num_bytes_len: {}'.format(max_num_bytes_len))
+
+    return max_num_bytes # max number of bytes per transfer data request
+
+  def request_upload(self, memory_address: int, memory_size: int, memory_address_bytes: int=4, memory_size_bytes: int=4, data_format: int=0x00):
+    data = bytes([data_format])
+
+    if memory_address_bytes < 1 or memory_address_bytes > 4:
+      raise ValueError('invalid memory_address_bytes: {}'.format(memory_address_bytes))
+    if memory_size_bytes < 1 or memory_size_bytes > 4:
+      raise ValueError('invalid memory_size_bytes: {}'.format(memory_size_bytes))
+    data += bytes([memory_size_bytes<<4 | memory_address_bytes])
+
+    if memory_address >= 1<<(memory_address_bytes*8):
+      raise ValueError('invalid memory_address: {}'.format(memory_address))
+    data += struct.pack('!I', memory_address)[4-memory_address_bytes:]
+    if memory_size >= 1<<(memory_size_bytes*8):
+      raise ValueError('invalid memory_size: {}'.format(memory_size))
+    data += struct.pack('!I', memory_size)[4-memory_size_bytes:]
+
+    resp = self._uds_request(SERVICE_TYPE.REQUEST_UPLOAD, subfunction=None, data=data)
+    max_num_bytes_len = resp[0] >> 4 if len(resp) > 0 else None
+    if max_num_bytes_len >= 1 and max_num_bytes_len <= 4:
+      max_num_bytes = struct.unpack('!I', (b"\x00"*(4-max_num_bytes_len))+resp[1:max_num_bytes_len+1])[0]
+    else:
+      raise ValueError('invalid max_num_bytes_len: {}'.format(max_num_bytes_len))
+
+    return max_num_bytes # max number of bytes per transfer data request
+
+  def transfer_data(self, block_sequence_count: int, data: bytes=b''):
+    data = bytes([block_sequence_count]) + data
+    resp = self._uds_request(SERVICE_TYPE.TRANSFER_DATA, subfunction=None, data=data)
+    resp_id = resp[0] if len(resp) > 0 else None
+    if resp_id != block_sequence_count:
+      raise ValueError('invalid block_sequence_count: {}'.format(resp_id))
+    return resp[1:]
+
+  def request_transfer_exit(self):
+    self._uds_request(SERVICE_TYPE.REQUEST_TRANSFER_EXIT, subfunction=None)

python/update.py

@@ -12,7 +12,6 @@ def ensure_st_up_to_date():
 
   panda = None
   panda_dfu = None
-  should_flash_recover = False
 
   while 1:
     # break on normal mode Panda

requirements.txt

@@ -1,7 +1,11 @@
 libusb1 == 1.6.6
-hexdump
-pycrypto
-tqdm
+numpy==1.17.2
+hexdump>=3.3
+pycrypto==2.6.1
+tqdm>=4.14.0
 nose
 parameterized
 requests
+flake8==3.7.8
+pylint==2.4.2
+cffi==1.11.4

setup.py

@@ -13,7 +13,7 @@
 import codecs
 import os
 import re
-from setuptools import setup, Extension
+from setuptools import setup
 
 here = os.path.abspath(os.path.dirname(__file__))
 

tests/automated/0_builds.py

@@ -1,4 +1,3 @@
-import os
 from panda import build_st
 
 def test_build_panda():

tests/automated/1_program.py

@@ -1,6 +1,4 @@
-import os
-from panda import Panda
-from .helpers import panda_type_to_serial, test_white_and_grey, test_all_pandas, panda_connect_and_init
+from .helpers import test_all_pandas, panda_connect_and_init
 
 @test_all_pandas
 @panda_connect_and_init

tests/automated/2_usb_to_can.py

@@ -1,5 +1,3 @@
-
-import os
 import sys
 import time
 from panda import Panda
@@ -180,6 +178,6 @@ def test_gmlan_bad_toggle(p):
 @test_all_pandas
 @panda_connect_and_init
 def test_serial_debug(p):
-  junk = p.serial_read(Panda.SERIAL_DEBUG)
+  _ = p.serial_read(Panda.SERIAL_DEBUG)  # junk
   p.call_control_api(0xc0)
   assert(p.serial_read(Panda.SERIAL_DEBUG).startswith(b"can "))

tests/automated/3_wifi.py

@@ -1,5 +1,3 @@
-
-import os
 import time
 from panda import Panda
 from .helpers import connect_wifi, test_white, test_all_pandas, panda_type_to_serial, panda_connect_and_init

tests/automated/4_wifi_functionality.py

@@ -1,8 +1,6 @@
-
 import time
 from panda import Panda
 from .helpers import time_many_sends, connect_wifi, test_white, panda_type_to_serial
-from nose.tools import timed, assert_equal, assert_less, assert_greater
 
 @test_white
 @panda_type_to_serial

tests/automated/5_wifi_udp.py

@@ -3,7 +3,7 @@ import sys
 import time
 from .helpers import time_many_sends, connect_wifi, test_white, panda_type_to_serial
 from panda import Panda, PandaWifiStreaming
-from nose.tools import timed, assert_equal, assert_less, assert_greater
+from nose.tools import assert_less, assert_greater
 
 @test_white
 @panda_type_to_serial

tests/automated/6_two_panda.py

@@ -171,7 +171,7 @@ def test_black_loopback(panda0, panda1):
       time.sleep(0.1)
 
       # check for receive
-      cans_echo = send_panda.can_recv()
+      _ = send_panda.can_recv()  # cans echo
       cans_loop = recv_panda.can_recv()
 
       loop_buses = []

tests/automated/helpers.py

@@ -2,13 +2,12 @@ import os
 import sys
 import time
 import random
-import binascii
 import subprocess
 import requests
 import _thread
 from functools import wraps
 from panda import Panda
-from nose.tools import timed, assert_equal, assert_less, assert_greater
+from nose.tools import assert_equal
 from parameterized import parameterized, param
 
 SPEED_NORMAL = 500
@@ -50,7 +49,7 @@ def connect_wifi(serial=None):
 
 FNULL = open(os.devnull, 'w')
 def _connect_wifi(dongle_id, pw, insecure_okay=False):
-  ssid = "panda-" + dongle_id.decode("utf8")
+  ssid = "panda-" + dongle_id
 
   r = subprocess.call(["ping", "-W", "4", "-c", "1", "192.168.0.10"], stdout=FNULL, stderr=subprocess.STDOUT)
   if not r:
@@ -69,7 +68,7 @@ def _connect_wifi(dongle_id, pw, insecure_okay=False):
     if sys.platform == "darwin":
       os.system("networksetup -setairportnetwork en0 %s %s" % (ssid, pw))
     else:
-      wlan_interface = subprocess.check_output(["sh", "-c", "iw dev | awk '/Interface/ {print $2}'"]).strip()
+      wlan_interface = subprocess.check_output(["sh", "-c", "iw dev | awk '/Interface/ {print $2}'"]).strip().decode('utf8')
       cnt = 0
       MAX_TRIES = 10
       while cnt < MAX_TRIES:
@@ -87,13 +86,13 @@ def _connect_wifi(dongle_id, pw, insecure_okay=False):
       if "-pair" in wifi_scan[0]:
         os.system("nmcli d wifi connect %s-pair" % (ssid))
         connect_cnt = 0
-        MAX_TRIES = 20
+        MAX_TRIES = 100
         while connect_cnt < MAX_TRIES:
           connect_cnt += 1
           r = subprocess.call(["ping", "-W", "4", "-c", "1", "192.168.0.10"], stdout=FNULL, stderr=subprocess.STDOUT)
           if r:
             print("Waiting for panda to ping...")
-            time.sleep(0.1)
+            time.sleep(0.5)
           else:
             break
         if insecure_okay:

tests/black_loopback_test.py

@@ -11,9 +11,6 @@ import time
 import random
 import argparse
 
-from hexdump import hexdump
-from itertools import permutations
-
 sys.path.append(os.path.join(os.path.dirname(os.path.realpath(__file__)), ".."))
 from panda import Panda
 
@@ -92,7 +89,7 @@ def test_buses(send_panda, recv_panda, test_array, sleep_duration):
     time.sleep(0.1)
 
     # check for receive
-    cans_echo = send_panda.can_recv()
+    _ = send_panda.can_recv()  # cans echo
     cans_loop = recv_panda.can_recv()
 
     loop_buses = []

tests/black_white_loopback_test.py

@@ -11,9 +11,6 @@ import time
 import random
 import argparse
 
-from hexdump import hexdump
-from itertools import permutations
-
 sys.path.append(os.path.join(os.path.dirname(os.path.realpath(__file__)), ".."))
 from panda import Panda
 
@@ -118,10 +115,10 @@ def test_buses(black_panda, other_panda, direction, test_array, sleep_duration):
 
     # check for receive
     if direction:
-      cans_echo = black_panda.can_recv()
+      _ = black_panda.can_recv()  # can echo
       cans_loop = other_panda.can_recv()
     else:
-      cans_echo = other_panda.can_recv()
+      _ = other_panda.can_recv()  # can echo
       cans_loop = black_panda.can_recv()
 
     loop_buses = []

tests/black_white_relay_endurance.py

@@ -11,9 +11,6 @@ import time
 import random
 import argparse
 
-from hexdump import hexdump
-from itertools import permutations
-
 sys.path.append(os.path.join(os.path.dirname(os.path.realpath(__file__)), ".."))
 from panda import Panda
 
@@ -124,10 +121,10 @@ def test_buses(black_panda, other_panda, direction, test_array, sleep_duration):
 
     # check for receive
     if direction:
-      cans_echo = black_panda.can_recv()
+      _ = black_panda.can_recv()  # cans echo
       cans_loop = other_panda.can_recv()
     else:
-      cans_echo = other_panda.can_recv()
+      _ = other_panda.can_recv()  # cans echo
       cans_loop = black_panda.can_recv()
 
     loop_buses = []

tests/black_white_relay_test.py

@@ -10,9 +10,6 @@ import time
 import random
 import argparse
 
-from hexdump import hexdump
-from itertools import permutations
-
 sys.path.append(os.path.join(os.path.dirname(os.path.realpath(__file__)), ".."))
 from panda import Panda
 
@@ -114,7 +111,7 @@ def test_buses(black_panda, other_panda, test_obj):
   time.sleep(0.05)
 
   # check for receive
-  cans_echo = other_panda.can_recv()
+  _ = other_panda.can_recv()  # can echo
   cans_loop = black_panda.can_recv()
 
   loop_buses = []

tests/elm_car_simulator.py

@@ -109,9 +109,9 @@ class ELMCarSimulator():
             print("    LIN Reply (%x)" % to_addr, binascii.hexlify(msg))
 
         PHYS_ADDR = 0x80
-        FUNC_ADDR = 0xC0
+        #FUNC_ADDR = 0xC0
         RECV = 0xF1
-        SEND = 0x33 # Car OBD Functional Address
+        #SEND = 0x33 # Car OBD Functional Address
         headers = struct.pack("BBB", PHYS_ADDR | len(msg), RECV, to_addr)
         if not self.__silent:
             print("    Sending LIN", binascii.hexlify(headers+msg),
@@ -172,7 +172,7 @@ class ELMCarSimulator():
 
         while not self.__stop:
             for address, ts, data, src in self.panda.can_recv():
-                if self.__on and src is 0 and len(data) == 8 and data[0] >= 2:
+                if self.__on and src == 0 and len(data) == 8 and data[0] >= 2:
                     if not self.__silent:
                         print("Processing CAN message", src, hex(address), binascii.hexlify(data))
                     self.__can_process_msg(data[1], data[2], address, ts, data, src)

tests/elm_wifi.py

@@ -1,16 +1,14 @@
-
 import os
 import sys
 import time
 import socket
 import select
-import pytest
 import struct
 
 sys.path.append(os.path.join(os.path.dirname(os.path.realpath(__file__)), ".."))
-from . import elm_car_simulator
 sys.path.append(os.path.join(os.path.dirname(os.path.realpath(__file__)), "..", ".."))
 from panda import Panda
+from panda.tests import elm_car_simulator
 
 def elm_connect():
     s = socket.create_connection(("192.168.0.10", 35000))
@@ -234,35 +232,35 @@ def test_elm_send_lin_multiline_msg():
 
         send_compare(s, b'0902\r', # headers OFF, Spaces ON
                      b"BUS INIT: OK\r"
-                     "49 02 01 00 00 00 31 \r"
-                     "49 02 02 44 34 47 50 \r"
-                     "49 02 03 30 30 52 35 \r"
-                     "49 02 04 35 42 31 32 \r"
-                     "49 02 05 33 34 35 36 \r\r>")
+                     b"49 02 01 00 00 00 31 \r"
+                     b"49 02 02 44 34 47 50 \r"
+                     b"49 02 03 30 30 52 35 \r"
+                     b"49 02 04 35 42 31 32 \r"
+                     b"49 02 05 33 34 35 36 \r\r>")
 
         send_compare(s, b'ATS0\r', b'OK\r\r>') # Spaces OFF
         send_compare(s, b'0902\r', # Headers OFF, Spaces OFF
                      b"49020100000031\r"
-                     "49020244344750\r"
-                     "49020330305235\r"
-                     "49020435423132\r"
-                     "49020533343536\r\r>")
+                     b"49020244344750\r"
+                     b"49020330305235\r"
+                     b"49020435423132\r"
+                     b"49020533343536\r\r>")
 
         send_compare(s, b'ATH1\r', b'OK\r\r>') # Headers ON
         send_compare(s, b'0902\r', # Headers ON, Spaces OFF
                      b"87F1104902010000003105\r"
-                     "87F11049020244344750E4\r"
-                     "87F11049020330305235BD\r"
-                     "87F11049020435423132B1\r"
-                     "87F11049020533343536AA\r\r>")
+                     b"87F11049020244344750E4\r"
+                     b"87F11049020330305235BD\r"
+                     b"87F11049020435423132B1\r"
+                     b"87F11049020533343536AA\r\r>")
 
         send_compare(s, b'ATS1\r', b'OK\r\r>') # Spaces ON
         send_compare(s, b'0902\r', # Headers ON, Spaces ON
                      b"87 F1 10 49 02 01 00 00 00 31 05 \r"
-                     "87 F1 10 49 02 02 44 34 47 50 E4 \r"
-                     "87 F1 10 49 02 03 30 30 52 35 BD \r"
-                     "87 F1 10 49 02 04 35 42 31 32 B1 \r"
-                     "87 F1 10 49 02 05 33 34 35 36 AA \r\r>")
+                     b"87 F1 10 49 02 02 44 34 47 50 E4 \r"
+                     b"87 F1 10 49 02 03 30 30 52 35 BD \r"
+                     b"87 F1 10 49 02 04 35 42 31 32 B1 \r"
+                     b"87 F1 10 49 02 05 33 34 35 36 AA \r\r>")
     finally:
         sim.stop()
         sim.join()
@@ -322,7 +320,7 @@ def test_elm_panda_safety_mode_KWPFast():
 
     def kline_send(p, x, bus=2):
         p.kline_drain(bus=bus)
-        p._handle.bulkWrite(2, chr(bus).encode()+x)
+        p._handle.bulkWrite(2, bytes([bus]) + x)
         return timed_recv_check(p, bus, x)
 
     def did_send(priority, toaddr, fromaddr, dat, bus=2, checkbyte=None):
@@ -461,7 +459,7 @@ def test_elm_send_can_multimsg():
         sim.can_add_extra_noise(b'\x03\x41\x0D\xFA', addr=0x7E9)# Inject message into the stream
         send_compare(s, b'010D\r',
                      b"7E8 03 41 0D 53 \r"
-                     "7E9 03 41 0D FA \r\r>") # Check it was ignored.
+                     b"7E9 03 41 0D FA \r\r>") # Check it was ignored.
     finally:
         sim.stop()
         sim.join()
@@ -503,28 +501,28 @@ def test_elm_send_can_multiline_msg():
 
         send_compare(s, b'0902\r', # headers OFF, Spaces ON
                      b"014 \r"
-                     "0: 49 02 01 31 44 34 \r"
-                     "1: 47 50 30 30 52 35 35 \r"
-                     "2: 42 31 32 33 34 35 36 \r\r>")
+                     b"0: 49 02 01 31 44 34 \r"
+                     b"1: 47 50 30 30 52 35 35 \r"
+                     b"2: 42 31 32 33 34 35 36 \r\r>")
 
         send_compare(s, b'ATS0\r', b'OK\r\r>') # Spaces OFF
         send_compare(s, b'0902\r', # Headers OFF, Spaces OFF
                      b"014\r"
-                     "0:490201314434\r"
-                     "1:47503030523535\r"
-                     "2:42313233343536\r\r>")
+                     b"0:490201314434\r"
+                     b"1:47503030523535\r"
+                     b"2:42313233343536\r\r>")
 
         send_compare(s, b'ATH1\r', b'OK\r\r>') # Headers ON
         send_compare(s, b'0902\r', # Headers ON, Spaces OFF
                      b"7E81014490201314434\r"
-                     "7E82147503030523535\r"
-                     "7E82242313233343536\r\r>")
+                     b"7E82147503030523535\r"
+                     b"7E82242313233343536\r\r>")
 
         send_compare(s, b'ATS1\r', b'OK\r\r>') # Spaces ON
         send_compare(s, b'0902\r', # Headers ON, Spaces ON
                      b"7E8 10 14 49 02 01 31 44 34 \r"
-                     "7E8 21 47 50 30 30 52 35 35 \r"
-                     "7E8 22 42 31 32 33 34 35 36 \r\r>")
+                     b"7E8 21 47 50 30 30 52 35 35 \r"
+                     b"7E8 22 42 31 32 33 34 35 36 \r\r>")
     finally:
         sim.stop()
         sim.join()

tests/fan_test.py

@@ -0,0 +1,17 @@
+#!/usr/bin/env python
+import os
+import sys
+import time
+
+sys.path.append(os.path.join(os.path.dirname(os.path.realpath(__file__)), ".."))
+from panda import Panda
+
+power = 0
+if __name__ == "__main__":
+  p = Panda()
+  while True:
+    p.set_fan_power(power)
+    time.sleep(5)
+    print("Power: ", power, "RPM: ", str(p.get_fan_rpm()))
+    power += 10
+    power %=100

tests/gmbitbang/recv.py

@@ -1,17 +1,16 @@
 #!/usr/bin/env python3
-import time
 from panda import Panda
 
 p = Panda()
 p.set_safety_mode(Panda.SAFETY_ALLOUTPUT)
 p.set_gmlan(bus=2)
-#p.can_send(0xaaa, "\x00\x00", bus=3)
+#p.can_send(0xaaa, b"\x00\x00", bus=3)
 last_add = None
 while 1:
   ret = p.can_recv()
   if len(ret) > 0:
     add = ret[0][0]
     if last_add is not None and add != last_add + 1:
-      print("MISS %d %d" % (last_add, add))
+      print("MISS: ", last_add, add)
     last_add = add
     print(ret)

tests/gmbitbang/rigol.py

@@ -1,4 +1,5 @@
 #!/usr/bin/env python3
+# pylint: skip-file
 import numpy as np
 import visa
 import matplotlib.pyplot as plt

tests/gps_stability_test.py

@@ -77,7 +77,7 @@ def init_gps(panda):
 
   # Upping baud rate
   print("Upping GPS baud rate")
-  msg = add_nmea_checksum("$PUBX,41,1,0007,0003,%d,0" % GPS_BAUD)+"\r\n"
+  msg = str.encode(add_nmea_checksum("$PUBX,41,1,0007,0003,%d,0" % GPS_BAUD)+"\r\n")
   ser.write(msg)
   time.sleep(1)   # needs a wait for it to actually send
 
@@ -86,24 +86,24 @@ def init_gps(panda):
 
   # Sending all config messages boardd sends
   print("Sending config")
-  ser.write("\xB5\x62\x06\x00\x14\x00\x03\xFF\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\x00\x01\x00\x00\x00\x00\x00\x1E\x7F")
-  ser.write("\xB5\x62\x06\x3E\x00\x00\x44\xD2")
-  ser.write("\xB5\x62\x06\x00\x14\x00\x00\xFF\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x19\x35")
-  ser.write("\xB5\x62\x06\x00\x14\x00\x01\x00\x00\x00\xC0\x08\x00\x00\x00\x08\x07\x00\x01\x00\x01\x00\x00\x00\x00\x00\xF4\x80")
-  ser.write("\xB5\x62\x06\x00\x14\x00\x04\xFF\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x1D\x85")
-  ser.write("\xB5\x62\x06\x00\x00\x00\x06\x18")
-  ser.write("\xB5\x62\x06\x00\x01\x00\x01\x08\x22")
-  ser.write("\xB5\x62\x06\x00\x01\x00\x02\x09\x23")
-  ser.write("\xB5\x62\x06\x00\x01\x00\x03\x0A\x24")
-  ser.write("\xB5\x62\x06\x08\x06\x00\x64\x00\x01\x00\x00\x00\x79\x10")
-  ser.write("\xB5\x62\x06\x24\x24\x00\x05\x00\x04\x03\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x5A\x63")
-  ser.write("\xB5\x62\x06\x1E\x14\x00\x00\x00\x00\x00\x01\x03\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x3C\x37")
-  ser.write("\xB5\x62\x06\x24\x00\x00\x2A\x84")
-  ser.write("\xB5\x62\x06\x23\x00\x00\x29\x81")
-  ser.write("\xB5\x62\x06\x1E\x00\x00\x24\x72")
-  ser.write("\xB5\x62\x06\x01\x03\x00\x01\x07\x01\x13\x51")
-  ser.write("\xB5\x62\x06\x01\x03\x00\x02\x15\x01\x22\x70")
-  ser.write("\xB5\x62\x06\x01\x03\x00\x02\x13\x01\x20\x6C")
+  ser.write(b"\xB5\x62\x06\x00\x14\x00\x03\xFF\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\x00\x01\x00\x00\x00\x00\x00\x1E\x7F")
+  ser.write(b"\xB5\x62\x06\x3E\x00\x00\x44\xD2")
+  ser.write(b"\xB5\x62\x06\x00\x14\x00\x00\xFF\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x19\x35")
+  ser.write(b"\xB5\x62\x06\x00\x14\x00\x01\x00\x00\x00\xC0\x08\x00\x00\x00\x08\x07\x00\x01\x00\x01\x00\x00\x00\x00\x00\xF4\x80")
+  ser.write(b"\xB5\x62\x06\x00\x14\x00\x04\xFF\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x1D\x85")
+  ser.write(b"\xB5\x62\x06\x00\x00\x00\x06\x18")
+  ser.write(b"\xB5\x62\x06\x00\x01\x00\x01\x08\x22")
+  ser.write(b"\xB5\x62\x06\x00\x01\x00\x02\x09\x23")
+  ser.write(b"\xB5\x62\x06\x00\x01\x00\x03\x0A\x24")
+  ser.write(b"\xB5\x62\x06\x08\x06\x00\x64\x00\x01\x00\x00\x00\x79\x10")
+  ser.write(b"\xB5\x62\x06\x24\x24\x00\x05\x00\x04\x03\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x5A\x63")
+  ser.write(b"\xB5\x62\x06\x1E\x14\x00\x00\x00\x00\x00\x01\x03\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x3C\x37")
+  ser.write(b"\xB5\x62\x06\x24\x00\x00\x2A\x84")
+  ser.write(b"\xB5\x62\x06\x23\x00\x00\x29\x81")
+  ser.write(b"\xB5\x62\x06\x1E\x00\x00\x24\x72")
+  ser.write(b"\xB5\x62\x06\x01\x03\x00\x01\x07\x01\x13\x51")
+  ser.write(b"\xB5\x62\x06\x01\x03\x00\x02\x15\x01\x22\x70")
+  ser.write(b"\xB5\x62\x06\x01\x03\x00\x02\x13\x01\x20\x6C")
 
   print("Initialized GPS")
 
@@ -163,7 +163,3 @@ if __name__ == "__main__":
         print("Total max failures: ", max_failures)
     received_messages = 0
     received_bytes = 0
-
-
-
-  

tests/ir_test.py

@@ -0,0 +1,17 @@
+#!/usr/bin/env python
+import os
+import sys
+import time
+
+sys.path.append(os.path.join(os.path.dirname(os.path.realpath(__file__)), ".."))
+from panda import Panda
+
+power = 0
+if __name__ == "__main__":
+  p = Panda()
+  while True:
+    p.set_ir_power(power)
+    print("Power: ", str(power))
+    time.sleep(1)
+    power += 10
+    power %=100

tests/language/Dockerfile

@@ -14,5 +14,4 @@ RUN pyenv install 3.7.3
 RUN pyenv global 3.7.3
 RUN pyenv rehash
 
-COPY tests/safety/requirements.txt /panda/tests/safety/requirements.txt
 COPY . /panda

tests/language/test_language.py

@@ -20,7 +20,7 @@ if __name__ == "__main__":
         res = subprocess.check_output(cmd, shell=True, stderr=subprocess.STDOUT)
         print(res)
         found_bad_language = True
-      except subprocess.CalledProcessError as e:
+      except subprocess.CalledProcessError:
         pass
   if found_bad_language:
     sys.exit("Failed: found bad language")

tests/linter_python/.pylintrc

@@ -0,0 +1,585 @@
+[MASTER]
+
+# A comma-separated list of package or module names from where C extensions may
+# be loaded. Extensions are loading into the active Python interpreter and may
+# run arbitrary code
+extension-pkg-whitelist=scipy
+
+# Add files or directories to the blacklist. They should be base names, not
+# paths.
+ignore=CVS
+
+# Add files or directories matching the regex patterns to the blacklist. The
+# regex matches against base names, not paths.
+ignore-patterns=
+
+# Python code to execute, usually for sys.path manipulation such as
+# pygtk.require().
+#init-hook=
+
+# Use multiple processes to speed up Pylint.
+jobs=4
+
+# List of plugins (as comma separated values of python modules names) to load,
+# usually to register additional checkers.
+load-plugins=
+
+# Pickle collected data for later comparisons.
+persistent=yes
+
+# Specify a configuration file.
+#rcfile=
+
+# When enabled, pylint would attempt to guess common misconfiguration and emit
+# user-friendly hints instead of false-positive error messages
+suggestion-mode=yes
+
+# Allow loading of arbitrary C extensions. Extensions are imported into the
+# active Python interpreter and may run arbitrary code.
+unsafe-load-any-extension=no
+
+
+[MESSAGES CONTROL]
+
+# Only show warnings with the listed confidence levels. Leave empty to show
+# all. Valid levels: HIGH, INFERENCE, INFERENCE_FAILURE, UNDEFINED
+confidence=
+
+# Disable the message, report, category or checker with the given id(s). You
+# can either give multiple identifiers separated by comma (,) or put this
+# option multiple times (only on the command line, not in the configuration
+# file where it should appear only once).You can also use "--disable=all" to
+# disable everything first and then reenable specific checks. For example, if
+# you want to run only the similarities checker, you can use "--disable=all
+# --enable=similarities". If you want to run only the classes checker, but have
+# no Warning level messages displayed, use"--disable=all --enable=classes
+# --disable=W"
+disable=print-statement,
+        parameter-unpacking,
+        unpacking-in-except,
+        old-raise-syntax,
+        backtick,
+        long-suffix,
+        old-ne-operator,
+        old-octal-literal,
+        import-star-module-level,
+        non-ascii-bytes-literal,
+        raw-checker-failed,
+        bad-inline-option,
+        locally-disabled,
+        locally-enabled,
+        file-ignored,
+        suppressed-message,
+        useless-suppression,
+        deprecated-pragma,
+        apply-builtin,
+        basestring-builtin,
+        buffer-builtin,
+        cmp-builtin,
+        coerce-builtin,
+        execfile-builtin,
+        file-builtin,
+        long-builtin,
+        raw_input-builtin,
+        reduce-builtin,
+        standarderror-builtin,
+        unicode-builtin,
+        xrange-builtin,
+        coerce-method,
+        delslice-method,
+        getslice-method,
+        setslice-method,
+        no-absolute-import,
+        old-division,
+        dict-iter-method,
+        dict-view-method,
+        next-method-called,
+        metaclass-assignment,
+        indexing-exception,
+        raising-string,
+        reload-builtin,
+        oct-method,
+        hex-method,
+        nonzero-method,
+        cmp-method,
+        input-builtin,
+        round-builtin,
+        intern-builtin,
+        unichr-builtin,
+        map-builtin-not-iterating,
+        zip-builtin-not-iterating,
+        range-builtin-not-iterating,
+        filter-builtin-not-iterating,
+        using-cmp-argument,
+        eq-without-hash,
+        div-method,
+        idiv-method,
+        rdiv-method,
+        exception-message-attribute,
+        invalid-str-codec,
+        sys-max-int,
+        bad-python3-import,
+        deprecated-string-function,
+        deprecated-str-translate-call,
+        deprecated-itertools-function,
+        deprecated-types-field,
+        next-method-defined,
+        dict-items-not-iterating,
+        dict-keys-not-iterating,
+        dict-values-not-iterating,
+        bad-indentation,
+        line-too-long,
+        missing-docstring,
+        multiple-statements,
+        bad-continuation,
+        invalid-name,
+        too-many-arguments,
+        too-many-locals,
+        superfluous-parens,
+        bad-whitespace,
+        too-many-instance-attributes,
+        wrong-import-position,
+        ungrouped-imports,
+        wrong-import-order,
+        protected-access,
+        trailing-whitespace,
+        too-many-branches,
+        too-few-public-methods,
+        too-many-statements,
+        trailing-newlines,
+        attribute-defined-outside-init,
+        too-many-return-statements,
+        too-many-public-methods,
+        unused-argument,
+        old-style-class,
+        no-init,
+        len-as-condition,
+        unneeded-not,
+        no-self-use,
+        multiple-imports,
+        no-else-return,
+        logging-not-lazy,
+        fixme,
+        redefined-outer-name,
+        unused-variable,
+        unsubscriptable-object,
+        expression-not-assigned,
+        too-many-boolean-expressions,
+        consider-using-ternary,
+        invalid-unary-operand-type,
+        relative-import,
+        deprecated-lambda
+
+
+# Enable the message, report, category or checker with the given id(s). You can
+# either give multiple identifier separated by comma (,) or put this option
+# multiple time (only on the command line, not in the configuration file where
+# it should appear only once). See also the "--disable" option for examples.
+enable=c-extension-no-member
+
+
+[REPORTS]
+
+# Python expression which should return a note less than 10 (10 is the highest
+# note). You have access to the variables errors warning, statement which
+# respectively contain the number of errors / warnings messages and the total
+# number of statements analyzed. This is used by the global evaluation report
+# (RP0004).
+evaluation=10.0 - ((float(5 * error + warning + refactor + convention) / statement) * 10)
+
+# Template used to display messages. This is a python new-style format string
+# used to format the message information. See doc for all details
+#msg-template=
+
+# Set the output format. Available formats are text, parseable, colorized, json
+# and msvs (visual studio).You can also give a reporter class, eg
+# mypackage.mymodule.MyReporterClass.
+output-format=text
+
+# Tells whether to display a full report or only the messages
+reports=no
+
+# Activate the evaluation score.
+score=yes
+
+
+[REFACTORING]
+
+# Maximum number of nested blocks for function / method body
+max-nested-blocks=5
+
+# Complete name of functions that never returns. When checking for
+# inconsistent-return-statements if a never returning function is called then
+# it will be considered as an explicit return statement and no message will be
+# printed.
+never-returning-functions=optparse.Values,sys.exit
+
+
+[LOGGING]
+
+# Logging modules to check that the string format arguments are in logging
+# function parameter format
+logging-modules=logging
+
+
+[SPELLING]
+
+# Limits count of emitted suggestions for spelling mistakes
+max-spelling-suggestions=4
+
+# Spelling dictionary name. Available dictionaries: none. To make it working
+# install python-enchant package.
+spelling-dict=
+
+# List of comma separated words that should not be checked.
+spelling-ignore-words=
+
+# A path to a file that contains private dictionary; one word per line.
+spelling-private-dict-file=
+
+# Tells whether to store unknown words to indicated private dictionary in
+# --spelling-private-dict-file option instead of raising a message.
+spelling-store-unknown-words=no
+
+
+[MISCELLANEOUS]
+
+# List of note tags to take in consideration, separated by a comma.
+notes=FIXME,
+      XXX,
+      TODO
+
+
+[SIMILARITIES]
+
+# Ignore comments when computing similarities.
+ignore-comments=yes
+
+# Ignore docstrings when computing similarities.
+ignore-docstrings=yes
+
+# Ignore imports when computing similarities.
+ignore-imports=no
+
+# Minimum lines number of a similarity.
+min-similarity-lines=4
+
+
+[TYPECHECK]
+
+# List of decorators that produce context managers, such as
+# contextlib.contextmanager. Add to this list to register other decorators that
+# produce valid context managers.
+contextmanager-decorators=contextlib.contextmanager
+
+# List of members which are set dynamically and missed by pylint inference
+# system, and so shouldn't trigger E1101 when accessed. Python regular
+# expressions are accepted.
+generated-members=capnp.* cereal.* pygame.* zmq.* setproctitle.* smbus2.* usb1.* serial.* cv2.*
+
+# Tells whether missing members accessed in mixin class should be ignored. A
+# mixin class is detected if its name ends with "mixin" (case insensitive).
+ignore-mixin-members=yes
+
+# This flag controls whether pylint should warn about no-member and similar
+# checks whenever an opaque object is returned when inferring. The inference
+# can return multiple potential results while evaluating a Python object, but
+# some branches might not be evaluated, which results in partial inference. In
+# that case, it might be useful to still emit no-member and other checks for
+# the rest of the inferred objects.
+ignore-on-opaque-inference=yes
+
+# List of class names for which member attributes should not be checked (useful
+# for classes with dynamically set attributes). This supports the use of
+# qualified names.
+ignored-classes=optparse.Values,thread._local,_thread._local
+
+# List of module names for which member attributes should not be checked
+# (useful for modules/projects where namespaces are manipulated during runtime
+# and thus existing member attributes cannot be deduced by static analysis. It
+# supports qualified module names, as well as Unix pattern matching.
+ignored-modules=flask setproctitle usb1 flask.ext.socketio smbus2 usb1.*
+
+# Show a hint with possible names when a member name was not found. The aspect
+# of finding the hint is based on edit distance.
+missing-member-hint=yes
+
+# The minimum edit distance a name should have in order to be considered a
+# similar match for a missing member name.
+missing-member-hint-distance=1
+
+# The total number of similar names that should be taken in consideration when
+# showing a hint for a missing member.
+missing-member-max-choices=1
+
+
+[VARIABLES]
+
+# List of additional names supposed to be defined in builtins. Remember that
+# you should avoid to define new builtins when possible.
+additional-builtins=
+
+# Tells whether unused global variables should be treated as a violation.
+allow-global-unused-variables=yes
+
+# List of strings which can identify a callback function by name. A callback
+# name must start or end with one of those strings.
+callbacks=cb_,
+          _cb
+
+# A regular expression matching the name of dummy variables (i.e. expectedly
+# not used).
+dummy-variables-rgx=_+$|(_[a-zA-Z0-9_]*[a-zA-Z0-9]+?$)|dummy|^ignored_|^unused_
+
+# Argument names that match this expression will be ignored. Default to name
+# with leading underscore
+ignored-argument-names=_.*|^ignored_|^unused_
+
+# Tells whether we should check for unused import in __init__ files.
+init-import=no
+
+# List of qualified module names which can have objects that can redefine
+# builtins.
+redefining-builtins-modules=six.moves,past.builtins,future.builtins
+
+
+[FORMAT]
+
+# Expected format of line ending, e.g. empty (any line ending), LF or CRLF.
+expected-line-ending-format=
+
+# Regexp for a line that is allowed to be longer than the limit.
+ignore-long-lines=^\s*(# )?<?https?://\S+>?$
+
+# Number of spaces of indent required inside a hanging  or continued line.
+indent-after-paren=4
+
+# String used as indentation unit. This is usually "    " (4 spaces) or "\t" (1
+# tab).
+indent-string='  '
+
+# Maximum number of characters on a single line.
+max-line-length=100
+
+# Maximum number of lines in a module
+max-module-lines=1000
+
+# List of optional constructs for which whitespace checking is disabled. `dict-
+# separator` is used to allow tabulation in dicts, etc.: {1  : 1,\n222: 2}.
+# `trailing-comma` allows a space between comma and closing bracket: (a, ).
+# `empty-line` allows space-only lines.
+no-space-check=trailing-comma,
+               dict-separator
+
+# Allow the body of a class to be on the same line as the declaration if body
+# contains single statement.
+single-line-class-stmt=no
+
+# Allow the body of an if to be on the same line as the test if there is no
+# else.
+single-line-if-stmt=no
+
+
+[BASIC]
+
+# Naming style matching correct argument names
+argument-naming-style=snake_case
+
+# Regular expression matching correct argument names. Overrides argument-
+# naming-style
+#argument-rgx=
+
+# Naming style matching correct attribute names
+attr-naming-style=snake_case
+
+# Regular expression matching correct attribute names. Overrides attr-naming-
+# style
+#attr-rgx=
+
+# Bad variable names which should always be refused, separated by a comma
+bad-names=foo,
+          bar,
+          baz,
+          toto,
+          tutu,
+          tata
+
+# Naming style matching correct class attribute names
+class-attribute-naming-style=any
+
+# Regular expression matching correct class attribute names. Overrides class-
+# attribute-naming-style
+#class-attribute-rgx=
+
+# Naming style matching correct class names
+class-naming-style=PascalCase
+
+# Regular expression matching correct class names. Overrides class-naming-style
+#class-rgx=
+
+# Naming style matching correct constant names
+const-naming-style=UPPER_CASE
+
+# Regular expression matching correct constant names. Overrides const-naming-
+# style
+#const-rgx=
+
+# Minimum line length for functions/classes that require docstrings, shorter
+# ones are exempt.
+docstring-min-length=-1
+
+# Naming style matching correct function names
+function-naming-style=snake_case
+
+# Regular expression matching correct function names. Overrides function-
+# naming-style
+#function-rgx=
+
+# Good variable names which should always be accepted, separated by a comma
+good-names=i,
+           j,
+           k,
+           ex,
+           Run,
+           _
+
+# Include a hint for the correct naming format with invalid-name
+include-naming-hint=no
+
+# Naming style matching correct inline iteration names
+inlinevar-naming-style=any
+
+# Regular expression matching correct inline iteration names. Overrides
+# inlinevar-naming-style
+#inlinevar-rgx=
+
+# Naming style matching correct method names
+method-naming-style=snake_case
+
+# Regular expression matching correct method names. Overrides method-naming-
+# style
+#method-rgx=
+
+# Naming style matching correct module names
+module-naming-style=snake_case
+
+# Regular expression matching correct module names. Overrides module-naming-
+# style
+#module-rgx=
+
+# Colon-delimited sets of names that determine each other's naming style when
+# the name regexes allow several styles.
+name-group=
+
+# Regular expression which should only match function or class names that do
+# not require a docstring.
+no-docstring-rgx=^_
+
+# List of decorators that produce properties, such as abc.abstractproperty. Add
+# to this list to register other decorators that produce valid properties.
+property-classes=abc.abstractproperty
+
+# Naming style matching correct variable names
+variable-naming-style=snake_case
+
+# Regular expression matching correct variable names. Overrides variable-
+# naming-style
+#variable-rgx=
+
+
+[DESIGN]
+
+# Maximum number of arguments for function / method
+max-args=5
+
+# Maximum number of attributes for a class (see R0902).
+max-attributes=7
+
+# Maximum number of boolean expressions in a if statement
+max-bool-expr=5
+
+# Maximum number of branch for function / method body
+max-branches=12
+
+# Maximum number of locals for function / method body
+max-locals=15
+
+# Maximum number of parents for a class (see R0901).
+max-parents=7
+
+# Maximum number of public methods for a class (see R0904).
+max-public-methods=20
+
+# Maximum number of return / yield for function / method body
+max-returns=6
+
+# Maximum number of statements in function / method body
+max-statements=50
+
+# Minimum number of public methods for a class (see R0903).
+min-public-methods=2
+
+
+[CLASSES]
+
+# List of method names used to declare (i.e. assign) instance attributes.
+defining-attr-methods=__init__,
+                      __new__,
+                      setUp
+
+# List of member names, which should be excluded from the protected access
+# warning.
+exclude-protected=_asdict,
+                  _fields,
+                  _replace,
+                  _source,
+                  _make
+
+# List of valid names for the first argument in a class method.
+valid-classmethod-first-arg=cls
+
+# List of valid names for the first argument in a metaclass class method.
+valid-metaclass-classmethod-first-arg=mcs
+
+
+[IMPORTS]
+
+# Allow wildcard imports from modules that define __all__.
+allow-wildcard-with-all=no
+
+# Analyse import fallback blocks. This can be used to support both Python 2 and
+# 3 compatible code, which means that the block might have code that exists
+# only in one or another interpreter, leading to false positives when analysed.
+analyse-fallback-blocks=no
+
+# Deprecated modules which should not be used, separated by a comma
+deprecated-modules=regsub,
+                   TERMIOS,
+                   Bastion,
+                   rexec
+
+# Create a graph of external dependencies in the given file (report RP0402 must
+# not be disabled)
+ext-import-graph=
+
+# Create a graph of every (i.e. internal and external) dependencies in the
+# given file (report RP0402 must not be disabled)
+import-graph=
+
+# Create a graph of internal dependencies in the given file (report RP0402 must
+# not be disabled)
+int-import-graph=
+
+# Force import order to recognize a module as part of the standard
+# compatibility libraries.
+known-standard-library=
+
+# Force import order to recognize a module as part of a third party library.
+known-third-party=enchant
+
+
+[EXCEPTIONS]
+
+# Exceptions that will emit a warning when being caught. Defaults to
+# "Exception"
+overgeneral-exceptions=Exception

tests/linter_python/Dockerfile

@@ -0,0 +1,19 @@
+FROM ubuntu:16.04
+
+RUN apt-get update && apt-get install -y make python python-pip locales curl git zlib1g-dev libffi-dev bzip2 libssl-dev
+
+RUN sed -i -e 's/# en_US.UTF-8 UTF-8/en_US.UTF-8 UTF-8/' /etc/locale.gen && locale-gen
+ENV LANG en_US.UTF-8
+ENV LANGUAGE en_US:en
+ENV LC_ALL en_US.UTF-8
+
+RUN curl -L https://github.com/pyenv/pyenv-installer/raw/master/bin/pyenv-installer | bash
+
+ENV PATH="/root/.pyenv/bin:/root/.pyenv/shims:${PATH}"
+RUN pyenv install 3.7.3
+RUN pyenv global 3.7.3
+RUN pyenv rehash
+
+COPY requirements.txt /tmp/
+RUN pip install -r /tmp/requirements.txt
+COPY . /panda

tests/linter_python/flake8_panda.sh

@@ -0,0 +1,8 @@
+#!/usr/bin/env bash
+
+RESULT=$(python3 -m flake8 --select=F $(find ../../ -type f | grep -v "/boardesp/" | grep -v "/cppcheck/" | grep "\.py$"))
+if [[ $RESULT  ]]; then
+	echo "Pyflakes found errors in the code. Please fix and try again"
+	echo "$RESULT"
+	exit 1
+fi

tests/linter_python/pylint_panda.sh

@@ -0,0 +1,11 @@
+#!/usr/bin/env bash
+
+python3 -m pylint --disable=R,C,W $(find ../../ -type f | grep -v "/boardesp/" | grep -v "/cppcheck/" | grep "\.py$")
+
+exit_status=$?
+(( res = exit_status & 3 ))
+
+if [[ $res != 0  ]]; then
+	echo "Pylint found errors in the code. Please fix and try again"
+	exit 1
+fi

tests/location_listener.py

@@ -30,7 +30,7 @@ if __name__ == "__main__":
   baudrate = 460800
 
   print("upping baud rate")
-  msg = add_nmea_checksum("$PUBX,41,1,0007,0003,%d,0" % baudrate)+"\r\n"
+  msg = str.encode(add_nmea_checksum("$PUBX,41,1,0007,0003,%d,0" % baudrate)+"\r\n")
   print(msg)
   ser.write(msg)
   time.sleep(0.1)   # needs a wait for it to actually send

tests/loopback_test.py

@@ -55,7 +55,7 @@ def run_test_w_pandas(pandas, sleep_duration):
 
       # send the characters
       st = get_test_string()
-      st = b"\xaa"+chr(len(st)+3).encode()+st
+      st = bytes([0xaa, len(st) + 3]) + st
       h[ho[0]].kline_send(st, bus=bus, checksum=False)
 
       # check for receive

tests/misra/Dockerfile

@@ -1,6 +1,19 @@
 FROM ubuntu:16.04
 
-RUN apt-get update && apt-get install -y make python python-pip git
-COPY tests/safety/requirements.txt /panda/tests/safety/requirements.txt
-RUN pip install -r /panda/tests/safety/requirements.txt
+RUN apt-get update && apt-get install -y clang make python python-pip git curl locales zlib1g-dev libffi-dev bzip2 libssl-dev libbz2-dev libusb-1.0-0
+
+RUN sed -i -e 's/# en_US.UTF-8 UTF-8/en_US.UTF-8 UTF-8/' /etc/locale.gen && locale-gen
+ENV LANG en_US.UTF-8
+ENV LANGUAGE en_US:en
+ENV LC_ALL en_US.UTF-8
+
+RUN curl -L https://github.com/pyenv/pyenv-installer/raw/master/bin/pyenv-installer | bash
+
+ENV PATH="/root/.pyenv/bin:/root/.pyenv/shims:${PATH}"
+RUN pyenv install 3.7.3
+RUN pyenv global 3.7.3
+RUN pyenv rehash
+
+COPY requirements.txt /tmp/
+RUN pip install -r /tmp/requirements.txt
 COPY . /panda

tests/misra/coverage_table

@@ -9,9 +9,9 @@
 2.6     X (Cppcheck)
 2.7     
 3.1     X (Addon)
-3.2     
+3.2     X (Addon)
 4.1     X (Addon)
-4.2     
+4.2     X (Addon)
 5.1     X (Addon)
 5.2     X (Addon)
 5.3     X (Addon)
@@ -123,7 +123,7 @@
 20.12   
 20.13   X (Addon)
 20.14   X (Addon)
-21.1    
+21.1    X (Addon)
 21.2    
 21.3    X (Addon)
 21.4    X (Addon)
@@ -134,7 +134,7 @@
 21.9    X (Addon)
 21.10   X (Addon)
 21.11   X (Addon)
-21.12   
+21.12   X (Addon)
 22.1    X (Cppcheck)
 22.2    X (Cppcheck)
 22.3    

tests/misra/suppressions.txt

@@ -4,3 +4,5 @@ misra.19.2
 misra.11.4
 # Advisory: casting from void pointer to type pointer is ok. Done by STM libraries as well
 misra.11.5
+# Required: it's ok re-defining potentially reserved Macro names. Not likely to cause confusion
+misra.21.1

tests/misra/test_misra.sh

@@ -4,7 +4,7 @@ mkdir /tmp/misra || true
 git clone https://github.com/danmar/cppcheck.git || true
 cd cppcheck
 git fetch
-git checkout ff7dba91e177dfb712477faddb9e91bece7e743c
+git checkout bdd41151ed550e3d240a6dd6847859216b7ad736
 make -j4
 cd ../../../
 

tests/pedal/enter_canloader.py

@@ -1,5 +1,4 @@
 #!/usr/bin/env python3
-import sys
 import time
 import struct
 import argparse

tests/rtc_test.py

@@ -0,0 +1,13 @@
+#!/usr/bin/env python
+import os
+import sys
+import datetime
+
+sys.path.append(os.path.join(os.path.dirname(os.path.realpath(__file__)), ".."))
+from panda import Panda
+
+if __name__ == "__main__":
+  p = Panda()
+  
+  p.set_datetime(datetime.datetime.now())
+  print(p.get_datetime())