sadmen
/
openpilot_comma
mirror of https://github.com/commaai/openpilot.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

clean up tici camera registers (#20209)

Browse Source 
* clean up registers

* clean up more

Co-authored-by: Comma Device <device@comma.ai>
old-commit-hash: ab87aa1da8
commatwo_master
ZwX1616 4 years ago committed by GitHub
parent 633687e43a
commit a899ac0de6
1 changed files with 34 additions and 70 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Unified View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 104
      selfdrive/camerad/cameras/sensor2_i2c.h

104
selfdrive/camerad/cameras/sensor2_i2c.h
Unescape View File

@ -1,77 +1,29 @@
struct i2c_random_wr_payload start_reg_array[] = {{0x301a, 0x91c}}; struct i2c_random_wr_payload start_reg_array[] = {{0x301A, 0x91C}};
struct i2c_random_wr_payload stop_reg_array[] = {{0x301a, 0x918}};; struct i2c_random_wr_payload stop_reg_array[] = {{0x301A, 0x918}};
struct i2c_random_wr_payload init_array_ar0231[] = { struct i2c_random_wr_payload init_array_ar0231[] = {
{0x301A, 0x0018}, // RESET_REGISTER {0x301A, 0x0018}, // RESET_REGISTER
{0x3092, 0x0C24}, // ROW_NOISE_CONTROL
{0x337A, 0x0C80}, // DBLC_SCALE0 // CLOCK Settings
{0x3520, 0x1288}, // RESERVED_MFR_3520
{0x3522, 0x880C}, // RESERVED_MFR_3522
{0x3524, 0x0C12}, // RESERVED_MFR_3524
{0x352C, 0x1212}, // RESERVED_MFR_352C
{0x354A, 0x007F}, // RESERVED_MFR_354A
{0x350C, 0x055C}, // RESERVED_MFR_350C
{0x3506, 0x3333}, // RESERVED_MFR_3506
{0x3508, 0x3333}, // RESERVED_MFR_3508
{0x3100, 0x4000}, // DLO_CONTROL0
{0x3280, 0x0CCC}, // RESERVED_MFR_3280
{0x3282, 0x0CCC}, // RESERVED_MFR_3282
{0x3284, 0x0CCC}, // RESERVED_MFR_3284
{0x3286, 0x0CCC}, // RESERVED_MFR_3286
{0x3288, 0x0FA0}, // RESERVED_MFR_3288
{0x328A, 0x0FA0}, // RESERVED_MFR_328A
{0x328C, 0x0FA0}, // RESERVED_MFR_328C
{0x328E, 0x0FA0}, // RESERVED_MFR_328E
{0x3290, 0x0FA0}, // RESERVED_MFR_3290
{0x3292, 0x0FA0}, // RESERVED_MFR_3292
{0x3294, 0x0FA0}, // RESERVED_MFR_3294
{0x3296, 0x0FA0}, // RESERVED_MFR_3296
{0x3298, 0x0FA0}, // RESERVED_MFR_3298
{0x329A, 0x0FA0}, // RESERVED_MFR_329A
{0x329C, 0x0FA0}, // RESERVED_MFR_329C
{0x329E, 0x0FA0}, // RESERVED_MFR_329E
{0x32E6, 0x00E0}, // RESERVED_MFR_32E6
{0x1008, 0x036F}, // RESERVED_PARAM_1008
{0x100C, 0x058F}, // RESERVED_PARAM_100C
{0x100E, 0x07AF}, // RESERVED_PARAM_100E
{0x1010, 0x014F}, // RESERVED_PARAM_1010
{0x3230, 0x0312}, // FINE_CORRECTION
{0x3232, 0x0532}, // FINE_CORRECTION2
{0x3234, 0x0752}, // FINE_CORRECTION3
{0x3236, 0x00F2}, // FINE_CORRECTION4
{0x3566, 0x3328}, // RESERVED_MFR_3566
{0x32D0, 0x3A02}, // RESERVED_MFR_32D0
{0x32D2, 0x3508}, // RESERVED_MFR_32D2
{0x32D4, 0x3702}, // RESERVED_MFR_32D4
{0x32D6, 0x3C04}, // RESERVED_MFR_32D6
{0x32DC, 0x370A}, // RESERVED_MFR_32DC
{0x302A, 0x0006}, // VT_PIX_CLK_DIV {0x302A, 0x0006}, // VT_PIX_CLK_DIV
{0x302C, 0x0001}, // VT_SYS_CLK_DIV {0x302C, 0x0001}, // VT_SYS_CLK_DIV
{0x302E, 0x0002}, // PRE_PLL_CLK_DIV {0x302E, 0x0002}, // PRE_PLL_CLK_DIV
{0x3030, 0x0028}, // PLL_MULTIPLIER {0x3030, 0x0028}, // PLL_MULTIPLIER
{0x3036, 0x000A}, // OP_WORD_CLK_DIV {0x3036, 0x000A}, // OP_WORD_CLK_DIV
{0x3038, 0x0001}, // OP_SYS_CLK_DIV {0x3038, 0x0001}, // OP_SYS_CLK_DIV
{0x30A2, 0x0001}, // X_ODD_INC_
{0x30A6, 0x0001}, // Y_ODD_INC_ // FORMAT
{0x3040, 0xC000}, // READ_MODE C000 {0x3040, 0xC000}, // READ_MODE
{0x30BA, 0x11F2}, // DIGITAL_CTRL
{0x3044, 0x0400}, // DARK_CONTROL
{0x3064, 0x1802}, // SMIA_TEST
{0x33E0, 0x0C80}, // TEST_ASIL_ROWS
{0x3180, 0x0080}, // RESERVED_MFR_3180
{0x33E4, 0x0080}, // RESERVED_MFR_33E4
{0x33E0, 0x0C80}, // TEST_ASIL_ROWS
{0x33E0, 0x0C80}, // TEST_ASIL_ROWS
{0x3004, 0x0000}, // X_ADDR_START_ {0x3004, 0x0000}, // X_ADDR_START_
{0x3008, 0x0787}, // X_ADDR_END_ 787 {0x3008, 0x0787}, // X_ADDR_END_
{0x3002, 0x0000}, // Y_ADDR_START_ {0x3002, 0x0000}, // Y_ADDR_START_
{0x3006, 0x04B7}, // Y_ADDR_END_ 4B7 {0x3006, 0x04B7}, // Y_ADDR_END_
{0x3032, 0x0000}, // SCALING_MODE {0x3032, 0x0000}, // SCALING_MODE
{0x3400, 0x0010}, // RESERVED_MFR_3400 {0x30A2, 0x0001}, // X_ODD_INC_
{0x3402, 0x0788}, // X_OUTPUT_CONTROL {0x30A6, 0x0001}, // Y_ODD_INC_
{0x3402, 0x0F10}, // X_OUTPUT_CONTROL {0x3402, 0x0F10}, // X_OUTPUT_CONTROL
{0x3404, 0x04B8}, // Y_OUTPUT_CONTROL
{0x3404, 0x0970}, // Y_OUTPUT_CONTROL {0x3404, 0x0970}, // Y_OUTPUT_CONTROL
{0x3064, 0x1802}, // SMIA_TEST
{0x30BA, 0x11F2}, // DIGITAL_CTRL {0x30BA, 0x11F2}, // DIGITAL_CTRL
// SLAV* MODE // SLAV* MODE
@ -80,8 +32,8 @@ struct i2c_random_wr_payload init_array_ar0231[] = {
{0x340C, 0x802}, // 2 // 0000 0000 0010 {0x340C, 0x802}, // 2 // 0000 0000 0010
// Readout timing // Readout timing
{0x300C, 0x074B}, // LINE_LENGTH_PCK: min for 2-exposure HDR {0x300C, 0x074B}, // LINE_LENGTH_PCK
{0x300A, 0x085E}, // FRAME_LENGTH_LINES_ 6EB {0x300A, 0x085E}, // FRAME_LENGTH_LINES
{0x3042, 0x0000}, // EXTRA_DELAY {0x3042, 0x0000}, // EXTRA_DELAY
// Readout Settings // Readout Settings
@ -99,27 +51,40 @@ struct i2c_random_wr_payload init_array_ar0231[] = {
{0x31B2, 0x003B}, // LINE_PREAMBLE {0x31B2, 0x003B}, // LINE_PREAMBLE
{0x301A, 0x01C}, // RESET_REGISTER {0x301A, 0x01C}, // RESET_REGISTER
// Noise Corrections
{0x3092, 0x0C24}, // ROW_NOISE_CONTROL
{0x337A, 0x0C80}, // DBLC_SCALE0
{0x3370, 0x03B1}, // DBLC
{0x3044, 0x0400}, // DARK_CONTROL
{0x31E0, 0x0001}, // PDC
// HDR Settings // HDR Settings
{0x3082, 0x0004}, // OPERATION_MODE_CTRL {0x3082, 0x0004}, // OPERATION_MODE_CTRL
{0x3238, 0x0004}, // EXPOSURE_RATIO {0x3238, 0x0004}, // EXPOSURE_RATIO
{0x3014, 0x098E}, // FINE_INTEGRATION_TIME_ {0x3014, 0x098E}, // FINE_INTEGRATION_TIME_
{0x321E, 0x098E}, // FINE_INTEGRATION_TIME2 {0x321E, 0x098E}, // FINE_INTEGRATION_TIME2
{0x30B0, 0x0800}, // DIGITAL_TEST
{0x32EA, 0x3C0E}, // RESERVED_MFR_32EA
{0x32EC, 0x72A1}, // RESERVED_MFR_32EC
{0x31D0, 0x0000}, // COMPANDING, no good in 10 bit? {0x31D0, 0x0000}, // COMPANDING, no good in 10 bit?
{0x33DA, 0x0000}, // COMPANDING {0x33DA, 0x0000}, // COMPANDING
{0x3370, 0x03B1}, // DBLC
{0x31E0, 0x0001}, // PDC
{0x318E, 0x0200}, // PRE_HDR_GAIN_EN {0x318E, 0x0200}, // PRE_HDR_GAIN_EN
// DLO Settings
{0x3100, 0x4000}, // DLO_CONTROL0
{0x3280, 0x0CCC}, // T1 G1
{0x3282, 0x0CCC}, // T1 R
{0x3284, 0x0CCC}, // T1 B
{0x3286, 0x0CCC}, // T1 G2
{0x3288, 0x0FA0}, // T2 G1
{0x328A, 0x0FA0}, // T2 R
{0x328C, 0x0FA0}, // T2 B
{0x328E, 0x0FA0}, // T2 G2
// Initial Gains // Initial Gains
{0x3022, 0x01}, // GROUPED_PARAMETER_HOLD_ {0x3022, 0x01}, // GROUPED_PARAMETER_HOLD_
{0x3366, 0x5555}, // ANALOG_GAIN {0x3366, 0x5555}, // ANALOG_GAIN
{0x3060, 0x3333}, // ANALOG_COLOR_GAIN {0x3060, 0x3333}, // ANALOG_COLOR_GAIN
{0x3362, 0x0000}, // DC GAIN {0x3362, 0x0000}, // DC GAIN
{0x305A, 0x00D8}, // RED_GAIN {0x305A, 0x0108}, // RED_GAIN
{0x3058, 0x011B}, // BLUE_GAIN {0x3058, 0x00FB}, // BLUE_GAIN
{0x3056, 0x009A}, // GREEN1_GAIN {0x3056, 0x009A}, // GREEN1_GAIN
{0x305C, 0x009A}, // GREEN2_GAIN {0x305C, 0x009A}, // GREEN2_GAIN
{0x3022, 0x00}, // GROUPED_PARAMETER_HOLD_ {0x3022, 0x00}, // GROUPED_PARAMETER_HOLD_
@ -127,4 +92,3 @@ struct i2c_random_wr_payload init_array_ar0231[] = {
// Initial Integration Time // Initial Integration Time
{0x3012, 0x256}, {0x3012, 0x256},
}; };

Write Preview
Loading…
Cancel
Save