|
|
@ -197,6 +197,7 @@ const struct i2c_random_wr_payload init_array_os04c10[] = { |
|
|
|
{0x370b, 0x48}, |
|
|
|
{0x370b, 0x48}, |
|
|
|
{0x370c, 0x01}, |
|
|
|
{0x370c, 0x01}, |
|
|
|
{0x370f, 0x00}, |
|
|
|
{0x370f, 0x00}, |
|
|
|
|
|
|
|
{0x3714, 0x28}, |
|
|
|
{0x3716, 0x04}, |
|
|
|
{0x3716, 0x04}, |
|
|
|
{0x3719, 0x11}, |
|
|
|
{0x3719, 0x11}, |
|
|
|
{0x371a, 0x1e}, |
|
|
|
{0x371a, 0x1e}, |
|
|
@ -228,6 +229,7 @@ const struct i2c_random_wr_payload init_array_os04c10[] = { |
|
|
|
{0x37bd, 0x01}, |
|
|
|
{0x37bd, 0x01}, |
|
|
|
{0x37bf, 0x26}, |
|
|
|
{0x37bf, 0x26}, |
|
|
|
{0x37c0, 0x11}, |
|
|
|
{0x37c0, 0x11}, |
|
|
|
|
|
|
|
{0x37c2, 0x14}, |
|
|
|
{0x37cd, 0x19}, |
|
|
|
{0x37cd, 0x19}, |
|
|
|
{0x37e0, 0x08}, |
|
|
|
{0x37e0, 0x08}, |
|
|
|
{0x37e6, 0x04}, |
|
|
|
{0x37e6, 0x04}, |
|
|
@ -237,9 +239,14 @@ const struct i2c_random_wr_payload init_array_os04c10[] = { |
|
|
|
{0x37d8, 0x02}, |
|
|
|
{0x37d8, 0x02}, |
|
|
|
{0x37e2, 0x10}, |
|
|
|
{0x37e2, 0x10}, |
|
|
|
{0x3739, 0x10}, |
|
|
|
{0x3739, 0x10}, |
|
|
|
|
|
|
|
{0x3662, 0x08}, |
|
|
|
{0x37e4, 0x20}, |
|
|
|
{0x37e4, 0x20}, |
|
|
|
{0x37e3, 0x08}, |
|
|
|
{0x37e3, 0x08}, |
|
|
|
|
|
|
|
{0x37d9, 0x04}, |
|
|
|
{0x4040, 0x00}, |
|
|
|
{0x4040, 0x00}, |
|
|
|
|
|
|
|
{0x4041, 0x03}, |
|
|
|
|
|
|
|
{0x4008, 0x01}, |
|
|
|
|
|
|
|
{0x4009, 0x06}, |
|
|
|
|
|
|
|
|
|
|
|
// FSIN
|
|
|
|
// FSIN
|
|
|
|
{0x3002, 0x22}, |
|
|
|
{0x3002, 0x22}, |
|
|
@ -260,11 +267,20 @@ const struct i2c_random_wr_payload init_array_os04c10[] = { |
|
|
|
{0x3802, 0x00}, {0x3803, 0x00}, |
|
|
|
{0x3802, 0x00}, {0x3803, 0x00}, |
|
|
|
{0x3804, 0x0a}, {0x3805, 0x8f}, |
|
|
|
{0x3804, 0x0a}, {0x3805, 0x8f}, |
|
|
|
{0x3806, 0x05}, {0x3807, 0xff}, |
|
|
|
{0x3806, 0x05}, {0x3807, 0xff}, |
|
|
|
|
|
|
|
{0x3808, 0x05}, {0x3809, 0x40}, |
|
|
|
|
|
|
|
{0x380a, 0x02}, {0x380b, 0xf8}, |
|
|
|
{0x3811, 0x08}, |
|
|
|
{0x3811, 0x08}, |
|
|
|
{0x3813, 0x08}, |
|
|
|
{0x3813, 0x08}, |
|
|
|
|
|
|
|
{0x3814, 0x03}, |
|
|
|
{0x3815, 0x01}, |
|
|
|
{0x3815, 0x01}, |
|
|
|
|
|
|
|
{0x3816, 0x03}, |
|
|
|
{0x3817, 0x01}, |
|
|
|
{0x3817, 0x01}, |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{0x380c, 0x0b}, {0x380d, 0xac}, // HTS
|
|
|
|
|
|
|
|
{0x380e, 0x06}, {0x380f, 0x9c}, // VTS
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{0x3820, 0xb3}, |
|
|
|
|
|
|
|
{0x3821, 0x01}, |
|
|
|
{0x3880, 0x00}, |
|
|
|
{0x3880, 0x00}, |
|
|
|
{0x3882, 0x20}, |
|
|
|
{0x3882, 0x20}, |
|
|
|
{0x3c91, 0x0b}, |
|
|
|
{0x3c91, 0x0b}, |
|
|
@ -313,27 +329,10 @@ const struct i2c_random_wr_payload init_array_os04c10[] = { |
|
|
|
// r
|
|
|
|
// r
|
|
|
|
{0x5104, 0x08}, {0x5105, 0xd6}, |
|
|
|
{0x5104, 0x08}, {0x5105, 0xd6}, |
|
|
|
{0x5144, 0x08}, {0x5145, 0xd6}, |
|
|
|
{0x5144, 0x08}, {0x5145, 0xd6}, |
|
|
|
|
|
|
|
|
|
|
|
{0x3714, 0x28}, |
|
|
|
|
|
|
|
{0x37c2, 0x14}, |
|
|
|
|
|
|
|
{0x3662, 0x08}, |
|
|
|
|
|
|
|
{0x37d9, 0x04}, |
|
|
|
|
|
|
|
{0x4041, 0x03}, |
|
|
|
|
|
|
|
{0x4008, 0x01}, |
|
|
|
|
|
|
|
{0x4009, 0x06}, |
|
|
|
|
|
|
|
{0x3808, 0x05}, {0x3809, 0x40}, |
|
|
|
|
|
|
|
{0x380a, 0x02}, {0x380b, 0xf8}, |
|
|
|
|
|
|
|
{0x3814, 0x03}, |
|
|
|
|
|
|
|
{0x3816, 0x03}, |
|
|
|
|
|
|
|
{0x380c, 0x0b}, {0x380d, 0xac}, // HTS
|
|
|
|
|
|
|
|
{0x380e, 0x06}, {0x380f, 0x9c}, // VTS
|
|
|
|
|
|
|
|
{0x3820, 0xb3}, |
|
|
|
|
|
|
|
{0x3821, 0x01}, |
|
|
|
|
|
|
|
}; |
|
|
|
}; |
|
|
|
|
|
|
|
|
|
|
|
const struct i2c_random_wr_payload ife_downscale_override_array_os04c10[] = { |
|
|
|
const struct i2c_random_wr_payload ife_downscale_override_array_os04c10[] = { |
|
|
|
// OS04C10_AA_00_02_17_wAO_2688x1524_MIPI728Mbps_Linear12bit_20FPS_4Lane_MCLK24MHz
|
|
|
|
// OS04C10_AA_00_02_17_wAO_2688x1524_MIPI728Mbps_Linear12bit_20FPS_4Lane_MCLK24MHz
|
|
|
|
{0x3829, 0x03}, |
|
|
|
|
|
|
|
{0x3714, 0x24}, |
|
|
|
{0x3714, 0x24}, |
|
|
|
{0x37c2, 0x04}, |
|
|
|
{0x37c2, 0x04}, |
|
|
|
{0x3662, 0x10}, |
|
|
|
{0x3662, 0x10}, |
|
|
|