# mypy: ignore-errors # -*- coding: utf-8 -*- # # TARGET arch is: [] # WORD_SIZE is: 8 # POINTER_SIZE is: 8 # LONGDOUBLE_SIZE is: 16 # import ctypes _vega10_ENUM_HEADER = True # macro ENUMS_GDS_PERFCOUNT_SELECT_H = True # macro SQ_WAVE_TYPE_PS0 = 0x00000000 # macro SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro SQIND_WAVE_HWREGS_OFFSET = 0x00000010 # macro SQIND_WAVE_HWREGS_SIZE = 0x000001f0 # macro SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro SQIND_WAVE_VGPRS_SIZE = 0x00000100 # macro SQ_GFXDEC_BEGIN = 0x0000a000 # macro SQ_GFXDEC_END = 0x0000c000 # macro SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro SQDEC_BEGIN = 0x00002300 # macro SQDEC_END = 0x000023ff # macro SQPERFSDEC_BEGIN = 0x0000d9c0 # macro SQPERFSDEC_END = 0x0000da40 # macro SQPERFDDEC_BEGIN = 0x0000d1c0 # macro SQPERFDDEC_END = 0x0000d240 # macro SQGFXUDEC_BEGIN = 0x0000c330 # macro SQGFXUDEC_END = 0x0000c380 # macro SQPWRDEC_BEGIN = 0x0000f08c # macro SQPWRDEC_END = 0x0000f094 # macro SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro SQ_MAX_PGM_SGPRS = 0x00000068 # macro SQ_MAX_PGM_VGPRS = 0x00000100 # macro SQ_THREAD_TRACE_TIME_UNIT = 0x00000004 # macro SQ_EX_MODE_EXCP_VALU_BASE = 0x00000000 # macro SQ_EX_MODE_EXCP_VALU_SIZE = 0x00000007 # macro SQ_EX_MODE_EXCP_INVALID = 0x00000000 # macro SQ_EX_MODE_EXCP_INPUT_DENORM = 0x00000001 # macro SQ_EX_MODE_EXCP_DIV0 = 0x00000002 # macro SQ_EX_MODE_EXCP_OVERFLOW = 0x00000003 # macro SQ_EX_MODE_EXCP_UNDERFLOW = 0x00000004 # macro SQ_EX_MODE_EXCP_INEXACT = 0x00000005 # macro SQ_EX_MODE_EXCP_INT_DIV0 = 0x00000006 # macro SQ_EX_MODE_EXCP_ADDR_WATCH0 = 0x00000007 # macro SQ_EX_MODE_EXCP_MEM_VIOL = 0x00000008 # macro SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 = 0x00000000 # macro SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 = 0x00000001 # macro SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 = 0x00000002 # macro INST_ID_PRIV_START = 0x80000000 # macro INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro INST_ID_HW_TRAP = 0xfffffff2 # macro INST_ID_KILL_SEQ = 0xfffffff3 # macro INST_ID_SPI_WREXEC = 0xfffffff4 # macro INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro SIMM16_WAITCNT_VM_CNT_START = 0x00000000 # macro SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000004 # macro SIMM16_WAITCNT_EXP_CNT_START = 0x00000004 # macro SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro SIMM16_WAITCNT_LGKM_CNT_START = 0x00000008 # macro SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000004 # macro SIMM16_WAITCNT_VM_CNT_HI_START = 0x0000000e # macro SIMM16_WAITCNT_VM_CNT_HI_SIZE = 0x00000002 # macro SQ_EDC_FUE_CNTL_SQ = 0x00000000 # macro SQ_EDC_FUE_CNTL_LDS = 0x00000001 # macro SQ_EDC_FUE_CNTL_SIMD0 = 0x00000002 # macro SQ_EDC_FUE_CNTL_SIMD1 = 0x00000003 # macro SQ_EDC_FUE_CNTL_SIMD2 = 0x00000004 # macro SQ_EDC_FUE_CNTL_SIMD3 = 0x00000005 # macro SQ_EDC_FUE_CNTL_TA = 0x00000006 # macro SQ_EDC_FUE_CNTL_TD = 0x00000007 # macro SQ_EDC_FUE_CNTL_TCP = 0x00000008 # macro CSDATA_TYPE_WIDTH = 0x00000002 # macro CSDATA_ADDR_WIDTH = 0x00000007 # macro CSDATA_DATA_WIDTH = 0x00000020 # macro GSTHREADID_SIZE = 0x00000002 # macro GB_TILING_CONFIG_TABLE_SIZE = 0x00000020 # macro GB_TILING_CONFIG_MACROTABLE_SIZE = 0x00000010 # macro SEM_ECC_ERROR = 0x00000000 # macro SEM_TRANS_ERROR = 0x00000001 # macro SEM_FAILED = 0x00000002 # macro SEM_PASSED = 0x00000003 # macro IQ_QUEUE_SLEEP = 0x00000000 # macro IQ_OFFLOAD_RETRY = 0x00000001 # macro IQ_SCH_WAVE_MSG = 0x00000002 # macro IQ_SEM_REARM = 0x00000003 # macro IQ_DEQUEUE_RETRY = 0x00000004 # macro IQ_INTR_TYPE_PQ = 0x00000000 # macro IQ_INTR_TYPE_IB = 0x00000001 # macro IQ_INTR_TYPE_MQD = 0x00000002 # macro VMID_SZ = 0x00000004 # macro CONFIG_SPACE_START = 0x00002000 # macro CONFIG_SPACE_END = 0x00009fff # macro CONFIG_SPACE1_START = 0x00002000 # macro CONFIG_SPACE1_END = 0x00002bff # macro CONFIG_SPACE2_START = 0x00003000 # macro CONFIG_SPACE2_END = 0x00009fff # macro UCONFIG_SPACE_START = 0x0000c000 # macro UCONFIG_SPACE_END = 0x0000ffff # macro PERSISTENT_SPACE_START = 0x00002c00 # macro PERSISTENT_SPACE_END = 0x00002fff # macro CONTEXT_SPACE_START = 0x0000a000 # macro CONTEXT_SPACE_END = 0x0000bfff # macro SQ_ENC_SOP1_BITS = 0xbe800000 # macro SQ_ENC_SOP1_MASK = 0xff800000 # macro SQ_ENC_SOP1_FIELD = 0x0000017d # macro SQ_ENC_SOPC_BITS = 0xbf000000 # macro SQ_ENC_SOPC_MASK = 0xff800000 # macro SQ_ENC_SOPC_FIELD = 0x0000017e # macro SQ_ENC_SOPP_BITS = 0xbf800000 # macro SQ_ENC_SOPP_MASK = 0xff800000 # macro SQ_ENC_SOPP_FIELD = 0x0000017f # macro SQ_ENC_SOPK_BITS = 0xb0000000 # macro SQ_ENC_SOPK_MASK = 0xf0000000 # macro SQ_ENC_SOPK_FIELD = 0x0000000b # macro SQ_ENC_SOP2_BITS = 0x80000000 # macro SQ_ENC_SOP2_MASK = 0xc0000000 # macro SQ_ENC_SOP2_FIELD = 0x00000002 # macro SQ_ENC_SMEM_BITS = 0xc0000000 # macro SQ_ENC_SMEM_MASK = 0xfc000000 # macro SQ_ENC_SMEM_FIELD = 0x00000030 # macro SQ_ENC_VOP1_BITS = 0x7e000000 # macro SQ_ENC_VOP1_MASK = 0xfe000000 # macro SQ_ENC_VOP1_FIELD = 0x0000003f # macro SQ_ENC_VOPC_BITS = 0x7c000000 # macro SQ_ENC_VOPC_MASK = 0xfe000000 # macro SQ_ENC_VOPC_FIELD = 0x0000003e # macro SQ_ENC_VOP2_BITS = 0x00000000 # macro SQ_ENC_VOP2_MASK = 0x80000000 # macro SQ_ENC_VOP2_FIELD = 0x00000000 # macro SQ_ENC_VINTRP_BITS = 0xd4000000 # macro SQ_ENC_VINTRP_MASK = 0xfc000000 # macro SQ_ENC_VINTRP_FIELD = 0x00000035 # macro SQ_ENC_VOP3P_BITS = 0xd3800000 # macro SQ_ENC_VOP3P_MASK = 0xff800000 # macro SQ_ENC_VOP3P_FIELD = 0x000001a7 # macro SQ_ENC_VOP3_BITS = 0xd0000000 # macro SQ_ENC_VOP3_MASK = 0xfc000000 # macro SQ_ENC_VOP3_FIELD = 0x00000034 # macro SQ_ENC_DS_BITS = 0xd8000000 # macro SQ_ENC_DS_MASK = 0xfc000000 # macro SQ_ENC_DS_FIELD = 0x00000036 # macro SQ_ENC_MUBUF_BITS = 0xe0000000 # macro SQ_ENC_MUBUF_MASK = 0xfc000000 # macro SQ_ENC_MUBUF_FIELD = 0x00000038 # macro SQ_ENC_MTBUF_BITS = 0xe8000000 # macro SQ_ENC_MTBUF_MASK = 0xfc000000 # macro SQ_ENC_MTBUF_FIELD = 0x0000003a # macro SQ_ENC_MIMG_BITS = 0xf0000000 # macro SQ_ENC_MIMG_MASK = 0xfc000000 # macro SQ_ENC_MIMG_FIELD = 0x0000003c # macro SQ_ENC_EXP_BITS = 0xc4000000 # macro SQ_ENC_EXP_MASK = 0xfc000000 # macro SQ_ENC_EXP_FIELD = 0x00000031 # macro SQ_ENC_FLAT_BITS = 0xdc000000 # macro SQ_ENC_FLAT_MASK = 0xfc000000 # macro SQ_ENC_FLAT_FIELD = 0x00000037 # macro SQ_V_OP3_INTRP_COUNT = 0x0000000c # macro SQ_SENDMSG_SYSTEM_SIZE = 0x00000003 # macro SQ_HWREG_ID_SIZE = 0x00000006 # macro SQ_V_OPC_COUNT = 0x00000100 # macro SQ_NUM_VGPR = 0x00000100 # macro SQ_WAITCNT_LGKM_SHIFT = 0x00000008 # macro SQ_HWREG_ID_SHIFT = 0x00000000 # macro SQ_EXP_NUM_POS = 0x00000004 # macro SQ_XLATE_VOP3_TO_VOPC_OFFSET = 0x00000000 # macro SQ_V_OP3_2IN_OFFSET = 0x00000280 # macro SQ_XLATE_VOP3_TO_VOP2_OFFSET = 0x00000100 # macro SQ_EXP_NUM_MRT = 0x00000008 # macro SQ_NUM_TTMP = 0x00000010 # macro SQ_SENDMSG_STREAMID_SHIFT = 0x00000008 # macro SQ_V_OP1_COUNT = 0x00000080 # macro SQ_WAITCNT_LGKM_SIZE = 0x00000004 # macro SQ_XLATE_VOP3_TO_VOPC_COUNT = 0x00000100 # macro SQ_SENDMSG_MSG_SHIFT = 0x00000000 # macro SQ_V_OP3_3IN_OFFSET = 0x000001c0 # macro SQ_HWREG_OFFSET_SHIFT = 0x00000006 # macro SQ_HWREG_SIZE_SHIFT = 0x0000000b # macro SQ_HWREG_OFFSET_SIZE = 0x00000005 # macro SQ_V_OP3_3IN_COUNT = 0x000000b0 # macro SQ_SENDMSG_MSG_SIZE = 0x00000004 # macro SQ_XLATE_VOP3_TO_VOP1_COUNT = 0x00000080 # macro SQ_EXP_NUM_GDS = 0x00000005 # macro SQ_V_OP2_COUNT = 0x00000040 # macro SQ_SENDMSG_GSOP_SIZE = 0x00000002 # macro SQ_WAITCNT_VM_SHIFT = 0x00000000 # macro SQ_XLATE_VOP3_TO_VOP3P_COUNT = 0x00000080 # macro SQ_V_OP3_2IN_COUNT = 0x00000080 # macro SQ_SENDMSG_SYSTEM_SHIFT = 0x00000004 # macro SQ_WAITCNT_VM_SIZE = 0x00000004 # macro SQ_XLATE_VOP3_TO_VOP3P_OFFSET = 0x00000380 # macro SQ_WAITCNT_EXP_SHIFT = 0x00000004 # macro SQ_XLATE_VOP3_TO_VOP2_COUNT = 0x00000040 # macro SQ_EXP_NUM_PARAM = 0x00000020 # macro SQ_HWREG_SIZE_SIZE = 0x00000005 # macro SQ_WAITCNT_EXP_SIZE = 0x00000003 # macro SQ_V_OP3_INTRP_OFFSET = 0x00000274 # macro SQ_SENDMSG_GSOP_SHIFT = 0x00000004 # macro SQ_XLATE_VOP3_TO_VINTRP_OFFSET = 0x00000270 # macro SQ_NUM_ATTR = 0x00000021 # macro SQ_NUM_SGPR = 0x00000066 # macro SQ_SRC_VGPR_BIT = 0x00000100 # macro SQ_V_INTRP_COUNT = 0x00000004 # macro SQ_SENDMSG_STREAMID_SIZE = 0x00000002 # macro SQ_V_OP3P_COUNT = 0x00000080 # macro SQ_XLATE_VOP3_TO_VOP1_OFFSET = 0x00000140 # macro SQ_XLATE_VOP3_TO_VINTRP_COUNT = 0x00000004 # macro SQ_SRC_DPP = 0x000000fa # macro SQ_TBUFFER_LOAD_FORMAT_X = 0x00000000 # macro SQ_TBUFFER_LOAD_FORMAT_XY = 0x00000001 # macro SQ_TBUFFER_LOAD_FORMAT_XYZ = 0x00000002 # macro SQ_TBUFFER_LOAD_FORMAT_XYZW = 0x00000003 # macro SQ_TBUFFER_STORE_FORMAT_X = 0x00000004 # macro SQ_TBUFFER_STORE_FORMAT_XY = 0x00000005 # macro SQ_TBUFFER_STORE_FORMAT_XYZ = 0x00000006 # macro SQ_TBUFFER_STORE_FORMAT_XYZW = 0x00000007 # macro SQ_TBUFFER_LOAD_FORMAT_D16_X = 0x00000008 # macro SQ_TBUFFER_LOAD_FORMAT_D16_XY = 0x00000009 # macro SQ_TBUFFER_LOAD_FORMAT_D16_XYZ = 0x0000000a # macro SQ_TBUFFER_LOAD_FORMAT_D16_XYZW = 0x0000000b # macro SQ_TBUFFER_STORE_FORMAT_D16_X = 0x0000000c # macro SQ_TBUFFER_STORE_FORMAT_D16_XY = 0x0000000d # macro SQ_TBUFFER_STORE_FORMAT_D16_XYZ = 0x0000000e # macro SQ_TBUFFER_STORE_FORMAT_D16_XYZW = 0x0000000f # macro SQ_GLOBAL_LOAD_UBYTE = 0x00000010 # macro SQ_GLOBAL_LOAD_SBYTE = 0x00000011 # macro SQ_GLOBAL_LOAD_USHORT = 0x00000012 # macro SQ_GLOBAL_LOAD_SSHORT = 0x00000013 # macro SQ_GLOBAL_LOAD_DWORD = 0x00000014 # macro SQ_GLOBAL_LOAD_DWORDX2 = 0x00000015 # macro SQ_GLOBAL_LOAD_DWORDX3 = 0x00000016 # macro SQ_GLOBAL_LOAD_DWORDX4 = 0x00000017 # macro SQ_GLOBAL_STORE_BYTE = 0x00000018 # macro SQ_GLOBAL_STORE_SHORT = 0x0000001a # macro SQ_GLOBAL_STORE_DWORD = 0x0000001c # macro SQ_GLOBAL_STORE_DWORDX2 = 0x0000001d # macro SQ_GLOBAL_STORE_DWORDX3 = 0x0000001e # macro SQ_GLOBAL_STORE_DWORDX4 = 0x0000001f # macro SQ_GLOBAL_ATOMIC_SWAP = 0x00000040 # macro SQ_GLOBAL_ATOMIC_CMPSWAP = 0x00000041 # macro SQ_GLOBAL_ATOMIC_ADD = 0x00000042 # macro SQ_GLOBAL_ATOMIC_SUB = 0x00000043 # macro SQ_GLOBAL_ATOMIC_SMIN = 0x00000044 # macro SQ_GLOBAL_ATOMIC_UMIN = 0x00000045 # macro SQ_GLOBAL_ATOMIC_SMAX = 0x00000046 # macro SQ_GLOBAL_ATOMIC_UMAX = 0x00000047 # macro SQ_GLOBAL_ATOMIC_AND = 0x00000048 # macro SQ_GLOBAL_ATOMIC_OR = 0x00000049 # macro SQ_GLOBAL_ATOMIC_XOR = 0x0000004a # macro SQ_GLOBAL_ATOMIC_INC = 0x0000004b # macro SQ_GLOBAL_ATOMIC_DEC = 0x0000004c # macro SQ_GLOBAL_ATOMIC_SWAP_X2 = 0x00000060 # macro SQ_GLOBAL_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro SQ_GLOBAL_ATOMIC_ADD_X2 = 0x00000062 # macro SQ_GLOBAL_ATOMIC_SUB_X2 = 0x00000063 # macro SQ_GLOBAL_ATOMIC_SMIN_X2 = 0x00000064 # macro SQ_GLOBAL_ATOMIC_UMIN_X2 = 0x00000065 # macro SQ_GLOBAL_ATOMIC_SMAX_X2 = 0x00000066 # macro SQ_GLOBAL_ATOMIC_UMAX_X2 = 0x00000067 # macro SQ_GLOBAL_ATOMIC_AND_X2 = 0x00000068 # macro SQ_GLOBAL_ATOMIC_OR_X2 = 0x00000069 # macro SQ_GLOBAL_ATOMIC_XOR_X2 = 0x0000006a # macro SQ_GLOBAL_ATOMIC_INC_X2 = 0x0000006b # macro SQ_GLOBAL_ATOMIC_DEC_X2 = 0x0000006c # macro SQ_VGPR0 = 0x00000000 # macro SQ_SCRATCH_LOAD_UBYTE = 0x00000010 # macro SQ_SCRATCH_LOAD_SBYTE = 0x00000011 # macro SQ_SCRATCH_LOAD_USHORT = 0x00000012 # macro SQ_SCRATCH_LOAD_SSHORT = 0x00000013 # macro SQ_SCRATCH_LOAD_DWORD = 0x00000014 # macro SQ_SCRATCH_LOAD_DWORDX2 = 0x00000015 # macro SQ_SCRATCH_LOAD_DWORDX3 = 0x00000016 # macro SQ_SCRATCH_LOAD_DWORDX4 = 0x00000017 # macro SQ_SCRATCH_STORE_BYTE = 0x00000018 # macro SQ_SCRATCH_STORE_SHORT = 0x0000001a # macro SQ_SCRATCH_STORE_DWORD = 0x0000001c # macro SQ_SCRATCH_STORE_DWORDX2 = 0x0000001d # macro SQ_SCRATCH_STORE_DWORDX3 = 0x0000001e # macro SQ_SCRATCH_STORE_DWORDX4 = 0x0000001f # macro SQ_VCC_ALL = 0x00000000 # macro SQ_SRC_0 = 0x00000080 # macro SQ_SRC_1_INT = 0x00000081 # macro SQ_SRC_2_INT = 0x00000082 # macro SQ_SRC_3_INT = 0x00000083 # macro SQ_SRC_4_INT = 0x00000084 # macro SQ_SRC_5_INT = 0x00000085 # macro SQ_SRC_6_INT = 0x00000086 # macro SQ_SRC_7_INT = 0x00000087 # macro SQ_SRC_8_INT = 0x00000088 # macro SQ_SRC_9_INT = 0x00000089 # macro SQ_SRC_10_INT = 0x0000008a # macro SQ_SRC_11_INT = 0x0000008b # macro SQ_SRC_12_INT = 0x0000008c # macro SQ_SRC_13_INT = 0x0000008d # macro SQ_SRC_14_INT = 0x0000008e # macro SQ_SRC_15_INT = 0x0000008f # macro SQ_SRC_16_INT = 0x00000090 # macro SQ_SRC_17_INT = 0x00000091 # macro SQ_SRC_18_INT = 0x00000092 # macro SQ_SRC_19_INT = 0x00000093 # macro SQ_SRC_20_INT = 0x00000094 # macro SQ_SRC_21_INT = 0x00000095 # macro SQ_SRC_22_INT = 0x00000096 # macro SQ_SRC_23_INT = 0x00000097 # macro SQ_SRC_24_INT = 0x00000098 # macro SQ_SRC_25_INT = 0x00000099 # macro SQ_SRC_26_INT = 0x0000009a # macro SQ_SRC_27_INT = 0x0000009b # macro SQ_SRC_28_INT = 0x0000009c # macro SQ_SRC_29_INT = 0x0000009d # macro SQ_SRC_30_INT = 0x0000009e # macro SQ_SRC_31_INT = 0x0000009f # macro SQ_SRC_32_INT = 0x000000a0 # macro SQ_SRC_33_INT = 0x000000a1 # macro SQ_SRC_34_INT = 0x000000a2 # macro SQ_SRC_35_INT = 0x000000a3 # macro SQ_SRC_36_INT = 0x000000a4 # macro SQ_SRC_37_INT = 0x000000a5 # macro SQ_SRC_38_INT = 0x000000a6 # macro SQ_SRC_39_INT = 0x000000a7 # macro SQ_SRC_40_INT = 0x000000a8 # macro SQ_SRC_41_INT = 0x000000a9 # macro SQ_SRC_42_INT = 0x000000aa # macro SQ_SRC_43_INT = 0x000000ab # macro SQ_SRC_44_INT = 0x000000ac # macro SQ_SRC_45_INT = 0x000000ad # macro SQ_SRC_46_INT = 0x000000ae # macro SQ_SRC_47_INT = 0x000000af # macro SQ_SRC_48_INT = 0x000000b0 # macro SQ_SRC_49_INT = 0x000000b1 # macro SQ_SRC_50_INT = 0x000000b2 # macro SQ_SRC_51_INT = 0x000000b3 # macro SQ_SRC_52_INT = 0x000000b4 # macro SQ_SRC_53_INT = 0x000000b5 # macro SQ_SRC_54_INT = 0x000000b6 # macro SQ_SRC_55_INT = 0x000000b7 # macro SQ_SRC_56_INT = 0x000000b8 # macro SQ_SRC_57_INT = 0x000000b9 # macro SQ_SRC_58_INT = 0x000000ba # macro SQ_SRC_59_INT = 0x000000bb # macro SQ_SRC_60_INT = 0x000000bc # macro SQ_SRC_61_INT = 0x000000bd # macro SQ_SRC_62_INT = 0x000000be # macro SQ_SRC_63_INT = 0x000000bf # macro SQ_IMAGE_LOAD = 0x00000000 # macro SQ_IMAGE_LOAD_MIP = 0x00000001 # macro SQ_IMAGE_LOAD_PCK = 0x00000002 # macro SQ_IMAGE_LOAD_PCK_SGN = 0x00000003 # macro SQ_IMAGE_LOAD_MIP_PCK = 0x00000004 # macro SQ_IMAGE_LOAD_MIP_PCK_SGN = 0x00000005 # macro SQ_IMAGE_STORE = 0x00000008 # macro SQ_IMAGE_STORE_MIP = 0x00000009 # macro SQ_IMAGE_STORE_PCK = 0x0000000a # macro SQ_IMAGE_STORE_MIP_PCK = 0x0000000b # macro SQ_IMAGE_GET_RESINFO = 0x0000000e # macro SQ_IMAGE_ATOMIC_SWAP = 0x00000010 # macro SQ_IMAGE_ATOMIC_CMPSWAP = 0x00000011 # macro SQ_IMAGE_ATOMIC_ADD = 0x00000012 # macro SQ_IMAGE_ATOMIC_SUB = 0x00000013 # macro SQ_IMAGE_ATOMIC_SMIN = 0x00000014 # macro SQ_IMAGE_ATOMIC_UMIN = 0x00000015 # macro SQ_IMAGE_ATOMIC_SMAX = 0x00000016 # macro SQ_IMAGE_ATOMIC_UMAX = 0x00000017 # macro SQ_IMAGE_ATOMIC_AND = 0x00000018 # macro SQ_IMAGE_ATOMIC_OR = 0x00000019 # macro SQ_IMAGE_ATOMIC_XOR = 0x0000001a # macro SQ_IMAGE_ATOMIC_INC = 0x0000001b # macro SQ_IMAGE_ATOMIC_DEC = 0x0000001c # macro SQ_IMAGE_SAMPLE = 0x00000020 # macro SQ_IMAGE_SAMPLE_CL = 0x00000021 # macro SQ_IMAGE_SAMPLE_D = 0x00000022 # macro SQ_IMAGE_SAMPLE_D_CL = 0x00000023 # macro SQ_IMAGE_SAMPLE_L = 0x00000024 # macro SQ_IMAGE_SAMPLE_B = 0x00000025 # macro SQ_IMAGE_SAMPLE_B_CL = 0x00000026 # macro SQ_IMAGE_SAMPLE_LZ = 0x00000027 # macro SQ_IMAGE_SAMPLE_C = 0x00000028 # macro SQ_IMAGE_SAMPLE_C_CL = 0x00000029 # macro SQ_IMAGE_SAMPLE_C_D = 0x0000002a # macro SQ_IMAGE_SAMPLE_C_D_CL = 0x0000002b # macro SQ_IMAGE_SAMPLE_C_L = 0x0000002c # macro SQ_IMAGE_SAMPLE_C_B = 0x0000002d # macro SQ_IMAGE_SAMPLE_C_B_CL = 0x0000002e # macro SQ_IMAGE_SAMPLE_C_LZ = 0x0000002f # macro SQ_IMAGE_SAMPLE_O = 0x00000030 # macro SQ_IMAGE_SAMPLE_CL_O = 0x00000031 # macro SQ_IMAGE_SAMPLE_D_O = 0x00000032 # macro SQ_IMAGE_SAMPLE_D_CL_O = 0x00000033 # macro SQ_IMAGE_SAMPLE_L_O = 0x00000034 # macro SQ_IMAGE_SAMPLE_B_O = 0x00000035 # macro SQ_IMAGE_SAMPLE_B_CL_O = 0x00000036 # macro SQ_IMAGE_SAMPLE_LZ_O = 0x00000037 # macro SQ_IMAGE_SAMPLE_C_O = 0x00000038 # macro SQ_IMAGE_SAMPLE_C_CL_O = 0x00000039 # macro SQ_IMAGE_SAMPLE_C_D_O = 0x0000003a # macro SQ_IMAGE_SAMPLE_C_D_CL_O = 0x0000003b # macro SQ_IMAGE_SAMPLE_C_L_O = 0x0000003c # macro SQ_IMAGE_SAMPLE_C_B_O = 0x0000003d # macro SQ_IMAGE_SAMPLE_C_B_CL_O = 0x0000003e # macro SQ_IMAGE_SAMPLE_C_LZ_O = 0x0000003f # macro SQ_IMAGE_GATHER4 = 0x00000040 # macro SQ_IMAGE_GATHER4_CL = 0x00000041 # macro SQ_IMAGE_GATHER4H = 0x00000042 # macro SQ_IMAGE_GATHER4_L = 0x00000044 # macro SQ_IMAGE_GATHER4_B = 0x00000045 # macro SQ_IMAGE_GATHER4_B_CL = 0x00000046 # macro SQ_IMAGE_GATHER4_LZ = 0x00000047 # macro SQ_IMAGE_GATHER4_C = 0x00000048 # macro SQ_IMAGE_GATHER4_C_CL = 0x00000049 # macro SQ_IMAGE_GATHER4H_PCK = 0x0000004a # macro SQ_IMAGE_GATHER8H_PCK = 0x0000004b # macro SQ_IMAGE_GATHER4_C_L = 0x0000004c # macro SQ_IMAGE_GATHER4_C_B = 0x0000004d # macro SQ_IMAGE_GATHER4_C_B_CL = 0x0000004e # macro SQ_IMAGE_GATHER4_C_LZ = 0x0000004f # macro SQ_IMAGE_GATHER4_O = 0x00000050 # macro SQ_IMAGE_GATHER4_CL_O = 0x00000051 # macro SQ_IMAGE_GATHER4_L_O = 0x00000054 # macro SQ_IMAGE_GATHER4_B_O = 0x00000055 # macro SQ_IMAGE_GATHER4_B_CL_O = 0x00000056 # macro SQ_IMAGE_GATHER4_LZ_O = 0x00000057 # macro SQ_IMAGE_GATHER4_C_O = 0x00000058 # macro SQ_IMAGE_GATHER4_C_CL_O = 0x00000059 # macro SQ_IMAGE_GATHER4_C_L_O = 0x0000005c # macro SQ_IMAGE_GATHER4_C_B_O = 0x0000005d # macro SQ_IMAGE_GATHER4_C_B_CL_O = 0x0000005e # macro SQ_IMAGE_GATHER4_C_LZ_O = 0x0000005f # macro SQ_IMAGE_GET_LOD = 0x00000060 # macro SQ_IMAGE_SAMPLE_CD = 0x00000068 # macro SQ_IMAGE_SAMPLE_CD_CL = 0x00000069 # macro SQ_IMAGE_SAMPLE_C_CD = 0x0000006a # macro SQ_IMAGE_SAMPLE_C_CD_CL = 0x0000006b # macro SQ_IMAGE_SAMPLE_CD_O = 0x0000006c # macro SQ_IMAGE_SAMPLE_CD_CL_O = 0x0000006d # macro SQ_IMAGE_SAMPLE_C_CD_O = 0x0000006e # macro SQ_IMAGE_SAMPLE_C_CD_CL_O = 0x0000006f # macro SQ_IMAGE_RSRC256 = 0x0000007e # macro SQ_IMAGE_SAMPLER = 0x0000007f # macro SQ_HW_REG_MODE = 0x00000001 # macro SQ_HW_REG_STATUS = 0x00000002 # macro SQ_HW_REG_TRAPSTS = 0x00000003 # macro SQ_HW_REG_HW_ID = 0x00000004 # macro SQ_HW_REG_GPR_ALLOC = 0x00000005 # macro SQ_HW_REG_LDS_ALLOC = 0x00000006 # macro SQ_HW_REG_IB_STS = 0x00000007 # macro SQ_HW_REG_PC_LO = 0x00000008 # macro SQ_HW_REG_PC_HI = 0x00000009 # macro SQ_HW_REG_INST_DW0 = 0x0000000a # macro SQ_HW_REG_INST_DW1 = 0x0000000b # macro SQ_HW_REG_IB_DBG0 = 0x0000000c # macro SQ_HW_REG_IB_DBG1 = 0x0000000d # macro SQ_HW_REG_FLUSH_IB = 0x0000000e # macro SQ_HW_REG_SH_MEM_BASES = 0x0000000f # macro SQ_HW_REG_SQ_SHADER_TBA_LO = 0x00000010 # macro SQ_HW_REG_SQ_SHADER_TBA_HI = 0x00000011 # macro SQ_HW_REG_SQ_SHADER_TMA_LO = 0x00000012 # macro SQ_HW_REG_SQ_SHADER_TMA_HI = 0x00000013 # macro SQ_S_MOV_B32 = 0x00000000 # macro SQ_S_MOV_B64 = 0x00000001 # macro SQ_S_CMOV_B32 = 0x00000002 # macro SQ_S_CMOV_B64 = 0x00000003 # macro SQ_S_NOT_B32 = 0x00000004 # macro SQ_S_NOT_B64 = 0x00000005 # macro SQ_S_WQM_B32 = 0x00000006 # macro SQ_S_WQM_B64 = 0x00000007 # macro SQ_S_BREV_B32 = 0x00000008 # macro SQ_S_BREV_B64 = 0x00000009 # macro SQ_S_BCNT0_I32_B32 = 0x0000000a # macro SQ_S_BCNT0_I32_B64 = 0x0000000b # macro SQ_S_BCNT1_I32_B32 = 0x0000000c # macro SQ_S_BCNT1_I32_B64 = 0x0000000d # macro SQ_S_FF0_I32_B32 = 0x0000000e # macro SQ_S_FF0_I32_B64 = 0x0000000f # macro SQ_S_FF1_I32_B32 = 0x00000010 # macro SQ_S_FF1_I32_B64 = 0x00000011 # macro SQ_S_FLBIT_I32_B32 = 0x00000012 # macro SQ_S_FLBIT_I32_B64 = 0x00000013 # macro SQ_S_FLBIT_I32 = 0x00000014 # macro SQ_S_FLBIT_I32_I64 = 0x00000015 # macro SQ_S_SEXT_I32_I8 = 0x00000016 # macro SQ_S_SEXT_I32_I16 = 0x00000017 # macro SQ_S_BITSET0_B32 = 0x00000018 # macro SQ_S_BITSET0_B64 = 0x00000019 # macro SQ_S_BITSET1_B32 = 0x0000001a # macro SQ_S_BITSET1_B64 = 0x0000001b # macro SQ_S_GETPC_B64 = 0x0000001c # macro SQ_S_SETPC_B64 = 0x0000001d # macro SQ_S_SWAPPC_B64 = 0x0000001e # macro SQ_S_RFE_B64 = 0x0000001f # macro SQ_S_AND_SAVEEXEC_B64 = 0x00000020 # macro SQ_S_OR_SAVEEXEC_B64 = 0x00000021 # macro SQ_S_XOR_SAVEEXEC_B64 = 0x00000022 # macro SQ_S_ANDN2_SAVEEXEC_B64 = 0x00000023 # macro SQ_S_ORN2_SAVEEXEC_B64 = 0x00000024 # macro SQ_S_NAND_SAVEEXEC_B64 = 0x00000025 # macro SQ_S_NOR_SAVEEXEC_B64 = 0x00000026 # macro SQ_S_XNOR_SAVEEXEC_B64 = 0x00000027 # macro SQ_S_QUADMASK_B32 = 0x00000028 # macro SQ_S_QUADMASK_B64 = 0x00000029 # macro SQ_S_MOVRELS_B32 = 0x0000002a # macro SQ_S_MOVRELS_B64 = 0x0000002b # macro SQ_S_MOVRELD_B32 = 0x0000002c # macro SQ_S_MOVRELD_B64 = 0x0000002d # macro SQ_S_CBRANCH_JOIN = 0x0000002e # macro SQ_S_MOV_REGRD_B32 = 0x0000002f # macro SQ_S_ABS_I32 = 0x00000030 # macro SQ_S_MOV_FED_B32 = 0x00000031 # macro SQ_S_SET_GPR_IDX_IDX = 0x00000032 # macro SQ_S_ANDN1_SAVEEXEC_B64 = 0x00000033 # macro SQ_S_ORN1_SAVEEXEC_B64 = 0x00000034 # macro SQ_S_ANDN1_WREXEC_B64 = 0x00000035 # macro SQ_S_ANDN2_WREXEC_B64 = 0x00000036 # macro SQ_S_BITREPLICATE_B64_B32 = 0x00000037 # macro SQ_CNT1 = 0x00000000 # macro SQ_CNT2 = 0x00000001 # macro SQ_CNT3 = 0x00000002 # macro SQ_CNT4 = 0x00000003 # macro SQ_V_MAD_LEGACY_F32 = 0x000001c0 # macro SQ_V_MAD_F32 = 0x000001c1 # macro SQ_V_MAD_I32_I24 = 0x000001c2 # macro SQ_V_MAD_U32_U24 = 0x000001c3 # macro SQ_V_CUBEID_F32 = 0x000001c4 # macro SQ_V_CUBESC_F32 = 0x000001c5 # macro SQ_V_CUBETC_F32 = 0x000001c6 # macro SQ_V_CUBEMA_F32 = 0x000001c7 # macro SQ_V_BFE_U32 = 0x000001c8 # macro SQ_V_BFE_I32 = 0x000001c9 # macro SQ_V_BFI_B32 = 0x000001ca # macro SQ_V_FMA_F32 = 0x000001cb # macro SQ_V_FMA_F64 = 0x000001cc # macro SQ_V_LERP_U8 = 0x000001cd # macro SQ_V_ALIGNBIT_B32 = 0x000001ce # macro SQ_V_ALIGNBYTE_B32 = 0x000001cf # macro SQ_V_MIN3_F32 = 0x000001d0 # macro SQ_V_MIN3_I32 = 0x000001d1 # macro SQ_V_MIN3_U32 = 0x000001d2 # macro SQ_V_MAX3_F32 = 0x000001d3 # macro SQ_V_MAX3_I32 = 0x000001d4 # macro SQ_V_MAX3_U32 = 0x000001d5 # macro SQ_V_MED3_F32 = 0x000001d6 # macro SQ_V_MED3_I32 = 0x000001d7 # macro SQ_V_MED3_U32 = 0x000001d8 # macro SQ_V_SAD_U8 = 0x000001d9 # macro SQ_V_SAD_HI_U8 = 0x000001da # macro SQ_V_SAD_U16 = 0x000001db # macro SQ_V_SAD_U32 = 0x000001dc # macro SQ_V_CVT_PK_U8_F32 = 0x000001dd # macro SQ_V_DIV_FIXUP_F32 = 0x000001de # macro SQ_V_DIV_FIXUP_F64 = 0x000001df # macro SQ_V_DIV_SCALE_F32 = 0x000001e0 # macro SQ_V_DIV_SCALE_F64 = 0x000001e1 # macro SQ_V_DIV_FMAS_F32 = 0x000001e2 # macro SQ_V_DIV_FMAS_F64 = 0x000001e3 # macro SQ_V_MSAD_U8 = 0x000001e4 # macro SQ_V_QSAD_PK_U16_U8 = 0x000001e5 # macro SQ_V_MQSAD_PK_U16_U8 = 0x000001e6 # macro SQ_V_MQSAD_U32_U8 = 0x000001e7 # macro SQ_V_MAD_U64_U32 = 0x000001e8 # macro SQ_V_MAD_I64_I32 = 0x000001e9 # macro SQ_V_MAD_LEGACY_F16 = 0x000001ea # macro SQ_V_MAD_LEGACY_U16 = 0x000001eb # macro SQ_V_MAD_LEGACY_I16 = 0x000001ec # macro SQ_V_PERM_B32 = 0x000001ed # macro SQ_V_FMA_LEGACY_F16 = 0x000001ee # macro SQ_V_DIV_FIXUP_LEGACY_F16 = 0x000001ef # macro SQ_V_CVT_PKACCUM_U8_F32 = 0x000001f0 # macro SQ_V_MAD_U32_U16 = 0x000001f1 # macro SQ_V_MAD_I32_I16 = 0x000001f2 # macro SQ_V_XAD_U32 = 0x000001f3 # macro SQ_V_MIN3_F16 = 0x000001f4 # macro SQ_V_MIN3_I16 = 0x000001f5 # macro SQ_V_MIN3_U16 = 0x000001f6 # macro SQ_V_MAX3_F16 = 0x000001f7 # macro SQ_V_MAX3_I16 = 0x000001f8 # macro SQ_V_MAX3_U16 = 0x000001f9 # macro SQ_V_MED3_F16 = 0x000001fa # macro SQ_V_MED3_I16 = 0x000001fb # macro SQ_V_MED3_U16 = 0x000001fc # macro SQ_V_LSHL_ADD_U32 = 0x000001fd # macro SQ_V_ADD_LSHL_U32 = 0x000001fe # macro SQ_V_ADD3_U32 = 0x000001ff # macro SQ_V_LSHL_OR_B32 = 0x00000200 # macro SQ_V_AND_OR_B32 = 0x00000201 # macro SQ_V_OR3_B32 = 0x00000202 # macro SQ_V_MAD_F16 = 0x00000203 # macro SQ_V_MAD_U16 = 0x00000204 # macro SQ_V_MAD_I16 = 0x00000205 # macro SQ_V_FMA_F16 = 0x00000206 # macro SQ_V_DIV_FIXUP_F16 = 0x00000207 # macro SQ_V_INTERP_P1LL_F16 = 0x00000274 # macro SQ_V_INTERP_P1LV_F16 = 0x00000275 # macro SQ_V_INTERP_P2_LEGACY_F16 = 0x00000276 # macro SQ_V_INTERP_P2_F16 = 0x00000277 # macro SQ_V_ADD_F64 = 0x00000280 # macro SQ_V_MUL_F64 = 0x00000281 # macro SQ_V_MIN_F64 = 0x00000282 # macro SQ_V_MAX_F64 = 0x00000283 # macro SQ_V_LDEXP_F64 = 0x00000284 # macro SQ_V_MUL_LO_U32 = 0x00000285 # macro SQ_V_MUL_HI_U32 = 0x00000286 # macro SQ_V_MUL_HI_I32 = 0x00000287 # macro SQ_V_LDEXP_F32 = 0x00000288 # macro SQ_V_READLANE_B32 = 0x00000289 # macro SQ_V_WRITELANE_B32 = 0x0000028a # macro SQ_V_BCNT_U32_B32 = 0x0000028b # macro SQ_V_MBCNT_LO_U32_B32 = 0x0000028c # macro SQ_V_MBCNT_HI_U32_B32 = 0x0000028d # macro SQ_V_MAC_LEGACY_F32 = 0x0000028e # macro SQ_V_LSHLREV_B64 = 0x0000028f # macro SQ_V_LSHRREV_B64 = 0x00000290 # macro SQ_V_ASHRREV_I64 = 0x00000291 # macro SQ_V_TRIG_PREOP_F64 = 0x00000292 # macro SQ_V_BFM_B32 = 0x00000293 # macro SQ_V_CVT_PKNORM_I16_F32 = 0x00000294 # macro SQ_V_CVT_PKNORM_U16_F32 = 0x00000295 # macro SQ_V_CVT_PKRTZ_F16_F32 = 0x00000296 # macro SQ_V_CVT_PK_U16_U32 = 0x00000297 # macro SQ_V_CVT_PK_I16_I32 = 0x00000298 # macro SQ_V_CVT_PKNORM_I16_F16 = 0x00000299 # macro SQ_V_CVT_PKNORM_U16_F16 = 0x0000029a # macro SQ_V_READLANE_REGRD_B32 = 0x0000029b # macro SQ_V_ADD_I32 = 0x0000029c # macro SQ_V_SUB_I32 = 0x0000029d # macro SQ_V_ADD_I16 = 0x0000029e # macro SQ_V_SUB_I16 = 0x0000029f # macro SQ_V_PACK_B32_F16 = 0x000002a0 # macro SQ_SRC_LITERAL = 0x000000ff # macro SQ_DPP_QUAD_PERM = 0x00000000 # macro SQ_DPP_ROW_SL1 = 0x00000101 # macro SQ_DPP_ROW_SL2 = 0x00000102 # macro SQ_DPP_ROW_SL3 = 0x00000103 # macro SQ_DPP_ROW_SL4 = 0x00000104 # macro SQ_DPP_ROW_SL5 = 0x00000105 # macro SQ_DPP_ROW_SL6 = 0x00000106 # macro SQ_DPP_ROW_SL7 = 0x00000107 # macro SQ_DPP_ROW_SL8 = 0x00000108 # macro SQ_DPP_ROW_SL9 = 0x00000109 # macro SQ_DPP_ROW_SL10 = 0x0000010a # macro SQ_DPP_ROW_SL11 = 0x0000010b # macro SQ_DPP_ROW_SL12 = 0x0000010c # macro SQ_DPP_ROW_SL13 = 0x0000010d # macro SQ_DPP_ROW_SL14 = 0x0000010e # macro SQ_DPP_ROW_SL15 = 0x0000010f # macro SQ_DPP_ROW_SR1 = 0x00000111 # macro SQ_DPP_ROW_SR2 = 0x00000112 # macro SQ_DPP_ROW_SR3 = 0x00000113 # macro SQ_DPP_ROW_SR4 = 0x00000114 # macro SQ_DPP_ROW_SR5 = 0x00000115 # macro SQ_DPP_ROW_SR6 = 0x00000116 # macro SQ_DPP_ROW_SR7 = 0x00000117 # macro SQ_DPP_ROW_SR8 = 0x00000118 # macro SQ_DPP_ROW_SR9 = 0x00000119 # macro SQ_DPP_ROW_SR10 = 0x0000011a # macro SQ_DPP_ROW_SR11 = 0x0000011b # macro SQ_DPP_ROW_SR12 = 0x0000011c # macro SQ_DPP_ROW_SR13 = 0x0000011d # macro SQ_DPP_ROW_SR14 = 0x0000011e # macro SQ_DPP_ROW_SR15 = 0x0000011f # macro SQ_DPP_ROW_RR1 = 0x00000121 # macro SQ_DPP_ROW_RR2 = 0x00000122 # macro SQ_DPP_ROW_RR3 = 0x00000123 # macro SQ_DPP_ROW_RR4 = 0x00000124 # macro SQ_DPP_ROW_RR5 = 0x00000125 # macro SQ_DPP_ROW_RR6 = 0x00000126 # macro SQ_DPP_ROW_RR7 = 0x00000127 # macro SQ_DPP_ROW_RR8 = 0x00000128 # macro SQ_DPP_ROW_RR9 = 0x00000129 # macro SQ_DPP_ROW_RR10 = 0x0000012a # macro SQ_DPP_ROW_RR11 = 0x0000012b # macro SQ_DPP_ROW_RR12 = 0x0000012c # macro SQ_DPP_ROW_RR13 = 0x0000012d # macro SQ_DPP_ROW_RR14 = 0x0000012e # macro SQ_DPP_ROW_RR15 = 0x0000012f # macro SQ_DPP_WF_SL1 = 0x00000130 # macro SQ_DPP_WF_RL1 = 0x00000134 # macro SQ_DPP_WF_SR1 = 0x00000138 # macro SQ_DPP_WF_RR1 = 0x0000013c # macro SQ_DPP_ROW_MIRROR = 0x00000140 # macro SQ_DPP_ROW_HALF_MIRROR = 0x00000141 # macro SQ_DPP_ROW_BCAST15 = 0x00000142 # macro SQ_DPP_ROW_BCAST31 = 0x00000143 # macro SQ_FLAT_SCRATCH_LO = 0x00000066 # macro SQ_FLAT_SCRATCH_HI = 0x00000067 # macro SQ_V_NOP = 0x00000000 # macro SQ_V_MOV_B32 = 0x00000001 # macro SQ_V_READFIRSTLANE_B32 = 0x00000002 # macro SQ_V_CVT_I32_F64 = 0x00000003 # macro SQ_V_CVT_F64_I32 = 0x00000004 # macro SQ_V_CVT_F32_I32 = 0x00000005 # macro SQ_V_CVT_F32_U32 = 0x00000006 # macro SQ_V_CVT_U32_F32 = 0x00000007 # macro SQ_V_CVT_I32_F32 = 0x00000008 # macro SQ_V_MOV_FED_B32 = 0x00000009 # macro SQ_V_CVT_F16_F32 = 0x0000000a # macro SQ_V_CVT_F32_F16 = 0x0000000b # macro SQ_V_CVT_RPI_I32_F32 = 0x0000000c # macro SQ_V_CVT_FLR_I32_F32 = 0x0000000d # macro SQ_V_CVT_OFF_F32_I4 = 0x0000000e # macro SQ_V_CVT_F32_F64 = 0x0000000f # macro SQ_V_CVT_F64_F32 = 0x00000010 # macro SQ_V_CVT_F32_UBYTE0 = 0x00000011 # macro SQ_V_CVT_F32_UBYTE1 = 0x00000012 # macro SQ_V_CVT_F32_UBYTE2 = 0x00000013 # macro SQ_V_CVT_F32_UBYTE3 = 0x00000014 # macro SQ_V_CVT_U32_F64 = 0x00000015 # macro SQ_V_CVT_F64_U32 = 0x00000016 # macro SQ_V_TRUNC_F64 = 0x00000017 # macro SQ_V_CEIL_F64 = 0x00000018 # macro SQ_V_RNDNE_F64 = 0x00000019 # macro SQ_V_FLOOR_F64 = 0x0000001a # macro SQ_V_FRACT_F32 = 0x0000001b # macro SQ_V_TRUNC_F32 = 0x0000001c # macro SQ_V_CEIL_F32 = 0x0000001d # macro SQ_V_RNDNE_F32 = 0x0000001e # macro SQ_V_FLOOR_F32 = 0x0000001f # macro SQ_V_EXP_F32 = 0x00000020 # macro SQ_V_LOG_F32 = 0x00000021 # macro SQ_V_RCP_F32 = 0x00000022 # macro SQ_V_RCP_IFLAG_F32 = 0x00000023 # macro SQ_V_RSQ_F32 = 0x00000024 # macro SQ_V_RCP_F64 = 0x00000025 # macro SQ_V_RSQ_F64 = 0x00000026 # macro SQ_V_SQRT_F32 = 0x00000027 # macro SQ_V_SQRT_F64 = 0x00000028 # macro SQ_V_SIN_F32 = 0x00000029 # macro SQ_V_COS_F32 = 0x0000002a # macro SQ_V_NOT_B32 = 0x0000002b # macro SQ_V_BFREV_B32 = 0x0000002c # macro SQ_V_FFBH_U32 = 0x0000002d # macro SQ_V_FFBL_B32 = 0x0000002e # macro SQ_V_FFBH_I32 = 0x0000002f # macro SQ_V_FREXP_EXP_I32_F64 = 0x00000030 # macro SQ_V_FREXP_MANT_F64 = 0x00000031 # macro SQ_V_FRACT_F64 = 0x00000032 # macro SQ_V_FREXP_EXP_I32_F32 = 0x00000033 # macro SQ_V_FREXP_MANT_F32 = 0x00000034 # macro SQ_V_CLREXCP = 0x00000035 # macro SQ_V_MOV_PRSV_B32 = 0x00000036 # macro SQ_V_CVT_F16_U16 = 0x00000039 # macro SQ_V_CVT_F16_I16 = 0x0000003a # macro SQ_V_CVT_U16_F16 = 0x0000003b # macro SQ_V_CVT_I16_F16 = 0x0000003c # macro SQ_V_RCP_F16 = 0x0000003d # macro SQ_V_SQRT_F16 = 0x0000003e # macro SQ_V_RSQ_F16 = 0x0000003f # macro SQ_V_LOG_F16 = 0x00000040 # macro SQ_V_EXP_F16 = 0x00000041 # macro SQ_V_FREXP_MANT_F16 = 0x00000042 # macro SQ_V_FREXP_EXP_I16_F16 = 0x00000043 # macro SQ_V_FLOOR_F16 = 0x00000044 # macro SQ_V_CEIL_F16 = 0x00000045 # macro SQ_V_TRUNC_F16 = 0x00000046 # macro SQ_V_RNDNE_F16 = 0x00000047 # macro SQ_V_FRACT_F16 = 0x00000048 # macro SQ_V_SIN_F16 = 0x00000049 # macro SQ_V_COS_F16 = 0x0000004a # macro SQ_V_EXP_LEGACY_F32 = 0x0000004b # macro SQ_V_LOG_LEGACY_F32 = 0x0000004c # macro SQ_V_CVT_NORM_I16_F16 = 0x0000004d # macro SQ_V_CVT_NORM_U16_F16 = 0x0000004e # macro SQ_V_SAT_PK_U8_I16 = 0x0000004f # macro SQ_V_WRITELANE_IMM32 = 0x00000050 # macro SQ_V_SWAP_B32 = 0x00000051 # macro SQ_FLAT_LOAD_UBYTE = 0x00000010 # macro SQ_FLAT_LOAD_SBYTE = 0x00000011 # macro SQ_FLAT_LOAD_USHORT = 0x00000012 # macro SQ_FLAT_LOAD_SSHORT = 0x00000013 # macro SQ_FLAT_LOAD_DWORD = 0x00000014 # macro SQ_FLAT_LOAD_DWORDX2 = 0x00000015 # macro SQ_FLAT_LOAD_DWORDX3 = 0x00000016 # macro SQ_FLAT_LOAD_DWORDX4 = 0x00000017 # macro SQ_FLAT_STORE_BYTE = 0x00000018 # macro SQ_FLAT_STORE_SHORT = 0x0000001a # macro SQ_FLAT_STORE_DWORD = 0x0000001c # macro SQ_FLAT_STORE_DWORDX2 = 0x0000001d # macro SQ_FLAT_STORE_DWORDX3 = 0x0000001e # macro SQ_FLAT_STORE_DWORDX4 = 0x0000001f # macro SQ_FLAT_ATOMIC_SWAP = 0x00000040 # macro SQ_FLAT_ATOMIC_CMPSWAP = 0x00000041 # macro SQ_FLAT_ATOMIC_ADD = 0x00000042 # macro SQ_FLAT_ATOMIC_SUB = 0x00000043 # macro SQ_FLAT_ATOMIC_SMIN = 0x00000044 # macro SQ_FLAT_ATOMIC_UMIN = 0x00000045 # macro SQ_FLAT_ATOMIC_SMAX = 0x00000046 # macro SQ_FLAT_ATOMIC_UMAX = 0x00000047 # macro SQ_FLAT_ATOMIC_AND = 0x00000048 # macro SQ_FLAT_ATOMIC_OR = 0x00000049 # macro SQ_FLAT_ATOMIC_XOR = 0x0000004a # macro SQ_FLAT_ATOMIC_INC = 0x0000004b # macro SQ_FLAT_ATOMIC_DEC = 0x0000004c # macro SQ_FLAT_ATOMIC_SWAP_X2 = 0x00000060 # macro SQ_FLAT_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro SQ_FLAT_ATOMIC_ADD_X2 = 0x00000062 # macro SQ_FLAT_ATOMIC_SUB_X2 = 0x00000063 # macro SQ_FLAT_ATOMIC_SMIN_X2 = 0x00000064 # macro SQ_FLAT_ATOMIC_UMIN_X2 = 0x00000065 # macro SQ_FLAT_ATOMIC_SMAX_X2 = 0x00000066 # macro SQ_FLAT_ATOMIC_UMAX_X2 = 0x00000067 # macro SQ_FLAT_ATOMIC_AND_X2 = 0x00000068 # macro SQ_FLAT_ATOMIC_OR_X2 = 0x00000069 # macro SQ_FLAT_ATOMIC_XOR_X2 = 0x0000006a # macro SQ_FLAT_ATOMIC_INC_X2 = 0x0000006b # macro SQ_FLAT_ATOMIC_DEC_X2 = 0x0000006c # macro SQ_DS_ADD_U32 = 0x00000000 # macro SQ_DS_SUB_U32 = 0x00000001 # macro SQ_DS_RSUB_U32 = 0x00000002 # macro SQ_DS_INC_U32 = 0x00000003 # macro SQ_DS_DEC_U32 = 0x00000004 # macro SQ_DS_MIN_I32 = 0x00000005 # macro SQ_DS_MAX_I32 = 0x00000006 # macro SQ_DS_MIN_U32 = 0x00000007 # macro SQ_DS_MAX_U32 = 0x00000008 # macro SQ_DS_AND_B32 = 0x00000009 # macro SQ_DS_OR_B32 = 0x0000000a # macro SQ_DS_XOR_B32 = 0x0000000b # macro SQ_DS_MSKOR_B32 = 0x0000000c # macro SQ_DS_WRITE_B32 = 0x0000000d # macro SQ_DS_WRITE2_B32 = 0x0000000e # macro SQ_DS_WRITE2ST64_B32 = 0x0000000f # macro SQ_DS_CMPST_B32 = 0x00000010 # macro SQ_DS_CMPST_F32 = 0x00000011 # macro SQ_DS_MIN_F32 = 0x00000012 # macro SQ_DS_MAX_F32 = 0x00000013 # macro SQ_DS_NOP = 0x00000014 # macro SQ_DS_ADD_F32 = 0x00000015 # macro SQ_DS_WRITE_ADDTID_B32 = 0x0000001d # macro SQ_DS_WRITE_B8 = 0x0000001e # macro SQ_DS_WRITE_B16 = 0x0000001f # macro SQ_DS_ADD_RTN_U32 = 0x00000020 # macro SQ_DS_SUB_RTN_U32 = 0x00000021 # macro SQ_DS_RSUB_RTN_U32 = 0x00000022 # macro SQ_DS_INC_RTN_U32 = 0x00000023 # macro SQ_DS_DEC_RTN_U32 = 0x00000024 # macro SQ_DS_MIN_RTN_I32 = 0x00000025 # macro SQ_DS_MAX_RTN_I32 = 0x00000026 # macro SQ_DS_MIN_RTN_U32 = 0x00000027 # macro SQ_DS_MAX_RTN_U32 = 0x00000028 # macro SQ_DS_AND_RTN_B32 = 0x00000029 # macro SQ_DS_OR_RTN_B32 = 0x0000002a # macro SQ_DS_XOR_RTN_B32 = 0x0000002b # macro SQ_DS_MSKOR_RTN_B32 = 0x0000002c # macro SQ_DS_WRXCHG_RTN_B32 = 0x0000002d # macro SQ_DS_WRXCHG2_RTN_B32 = 0x0000002e # macro SQ_DS_WRXCHG2ST64_RTN_B32 = 0x0000002f # macro SQ_DS_CMPST_RTN_B32 = 0x00000030 # macro SQ_DS_CMPST_RTN_F32 = 0x00000031 # macro SQ_DS_MIN_RTN_F32 = 0x00000032 # macro SQ_DS_MAX_RTN_F32 = 0x00000033 # macro SQ_DS_WRAP_RTN_B32 = 0x00000034 # macro SQ_DS_ADD_RTN_F32 = 0x00000035 # macro SQ_DS_READ_B32 = 0x00000036 # macro SQ_DS_READ2_B32 = 0x00000037 # macro SQ_DS_READ2ST64_B32 = 0x00000038 # macro SQ_DS_READ_I8 = 0x00000039 # macro SQ_DS_READ_U8 = 0x0000003a # macro SQ_DS_READ_I16 = 0x0000003b # macro SQ_DS_READ_U16 = 0x0000003c # macro SQ_DS_SWIZZLE_B32 = 0x0000003d # macro SQ_DS_PERMUTE_B32 = 0x0000003e # macro SQ_DS_BPERMUTE_B32 = 0x0000003f # macro SQ_DS_ADD_U64 = 0x00000040 # macro SQ_DS_SUB_U64 = 0x00000041 # macro SQ_DS_RSUB_U64 = 0x00000042 # macro SQ_DS_INC_U64 = 0x00000043 # macro SQ_DS_DEC_U64 = 0x00000044 # macro SQ_DS_MIN_I64 = 0x00000045 # macro SQ_DS_MAX_I64 = 0x00000046 # macro SQ_DS_MIN_U64 = 0x00000047 # macro SQ_DS_MAX_U64 = 0x00000048 # macro SQ_DS_AND_B64 = 0x00000049 # macro SQ_DS_OR_B64 = 0x0000004a # macro SQ_DS_XOR_B64 = 0x0000004b # macro SQ_DS_MSKOR_B64 = 0x0000004c # macro SQ_DS_WRITE_B64 = 0x0000004d # macro SQ_DS_WRITE2_B64 = 0x0000004e # macro SQ_DS_WRITE2ST64_B64 = 0x0000004f # macro SQ_DS_CMPST_B64 = 0x00000050 # macro SQ_DS_CMPST_F64 = 0x00000051 # macro SQ_DS_MIN_F64 = 0x00000052 # macro SQ_DS_MAX_F64 = 0x00000053 # macro SQ_DS_ADD_RTN_U64 = 0x00000060 # macro SQ_DS_SUB_RTN_U64 = 0x00000061 # macro SQ_DS_RSUB_RTN_U64 = 0x00000062 # macro SQ_DS_INC_RTN_U64 = 0x00000063 # macro SQ_DS_DEC_RTN_U64 = 0x00000064 # macro SQ_DS_MIN_RTN_I64 = 0x00000065 # macro SQ_DS_MAX_RTN_I64 = 0x00000066 # macro SQ_DS_MIN_RTN_U64 = 0x00000067 # macro SQ_DS_MAX_RTN_U64 = 0x00000068 # macro SQ_DS_AND_RTN_B64 = 0x00000069 # macro SQ_DS_OR_RTN_B64 = 0x0000006a # macro SQ_DS_XOR_RTN_B64 = 0x0000006b # macro SQ_DS_MSKOR_RTN_B64 = 0x0000006c # macro SQ_DS_WRXCHG_RTN_B64 = 0x0000006d # macro SQ_DS_WRXCHG2_RTN_B64 = 0x0000006e # macro SQ_DS_WRXCHG2ST64_RTN_B64 = 0x0000006f # macro SQ_DS_CMPST_RTN_B64 = 0x00000070 # macro SQ_DS_CMPST_RTN_F64 = 0x00000071 # macro SQ_DS_MIN_RTN_F64 = 0x00000072 # macro SQ_DS_MAX_RTN_F64 = 0x00000073 # macro SQ_DS_READ_B64 = 0x00000076 # macro SQ_DS_READ2_B64 = 0x00000077 # macro SQ_DS_READ2ST64_B64 = 0x00000078 # macro SQ_DS_CONDXCHG32_RTN_B64 = 0x0000007e # macro SQ_DS_ADD_SRC2_U32 = 0x00000080 # macro SQ_DS_SUB_SRC2_U32 = 0x00000081 # macro SQ_DS_RSUB_SRC2_U32 = 0x00000082 # macro SQ_DS_INC_SRC2_U32 = 0x00000083 # macro SQ_DS_DEC_SRC2_U32 = 0x00000084 # macro SQ_DS_MIN_SRC2_I32 = 0x00000085 # macro SQ_DS_MAX_SRC2_I32 = 0x00000086 # macro SQ_DS_MIN_SRC2_U32 = 0x00000087 # macro SQ_DS_MAX_SRC2_U32 = 0x00000088 # macro SQ_DS_AND_SRC2_B32 = 0x00000089 # macro SQ_DS_OR_SRC2_B32 = 0x0000008a # macro SQ_DS_XOR_SRC2_B32 = 0x0000008b # macro SQ_DS_WRITE_SRC2_B32 = 0x0000008d # macro SQ_DS_MIN_SRC2_F32 = 0x00000092 # macro SQ_DS_MAX_SRC2_F32 = 0x00000093 # macro SQ_DS_ADD_SRC2_F32 = 0x00000095 # macro SQ_DS_GWS_SEMA_RELEASE_ALL = 0x00000098 # macro SQ_DS_GWS_INIT = 0x00000099 # macro SQ_DS_GWS_SEMA_V = 0x0000009a # macro SQ_DS_GWS_SEMA_BR = 0x0000009b # macro SQ_DS_GWS_SEMA_P = 0x0000009c # macro SQ_DS_GWS_BARRIER = 0x0000009d # macro SQ_DS_READ_ADDTID_B32 = 0x000000b6 # macro SQ_DS_CONSUME = 0x000000bd # macro SQ_DS_APPEND = 0x000000be # macro SQ_DS_ORDERED_COUNT = 0x000000bf # macro SQ_DS_ADD_SRC2_U64 = 0x000000c0 # macro SQ_DS_SUB_SRC2_U64 = 0x000000c1 # macro SQ_DS_RSUB_SRC2_U64 = 0x000000c2 # macro SQ_DS_INC_SRC2_U64 = 0x000000c3 # macro SQ_DS_DEC_SRC2_U64 = 0x000000c4 # macro SQ_DS_MIN_SRC2_I64 = 0x000000c5 # macro SQ_DS_MAX_SRC2_I64 = 0x000000c6 # macro SQ_DS_MIN_SRC2_U64 = 0x000000c7 # macro SQ_DS_MAX_SRC2_U64 = 0x000000c8 # macro SQ_DS_AND_SRC2_B64 = 0x000000c9 # macro SQ_DS_OR_SRC2_B64 = 0x000000ca # macro SQ_DS_XOR_SRC2_B64 = 0x000000cb # macro SQ_DS_WRITE_SRC2_B64 = 0x000000cd # macro SQ_DS_MIN_SRC2_F64 = 0x000000d2 # macro SQ_DS_MAX_SRC2_F64 = 0x000000d3 # macro SQ_DS_WRITE_B96 = 0x000000de # macro SQ_DS_WRITE_B128 = 0x000000df # macro SQ_DS_CONDXCHG32_RTN_B128 = 0x000000fd # macro SQ_DS_READ_B96 = 0x000000fe # macro SQ_DS_READ_B128 = 0x000000ff # macro SQ_S_LOAD_DWORD = 0x00000000 # macro SQ_S_LOAD_DWORDX2 = 0x00000001 # macro SQ_S_LOAD_DWORDX4 = 0x00000002 # macro SQ_S_LOAD_DWORDX8 = 0x00000003 # macro SQ_S_LOAD_DWORDX16 = 0x00000004 # macro SQ_S_SCRATCH_LOAD_DWORD = 0x00000005 # macro SQ_S_SCRATCH_LOAD_DWORDX2 = 0x00000006 # macro SQ_S_SCRATCH_LOAD_DWORDX4 = 0x00000007 # macro SQ_S_BUFFER_LOAD_DWORD = 0x00000008 # macro SQ_S_BUFFER_LOAD_DWORDX2 = 0x00000009 # macro SQ_S_BUFFER_LOAD_DWORDX4 = 0x0000000a # macro SQ_S_BUFFER_LOAD_DWORDX8 = 0x0000000b # macro SQ_S_BUFFER_LOAD_DWORDX16 = 0x0000000c # macro SQ_S_STORE_DWORD = 0x00000010 # macro SQ_S_STORE_DWORDX2 = 0x00000011 # macro SQ_S_STORE_DWORDX4 = 0x00000012 # macro SQ_S_SCRATCH_STORE_DWORD = 0x00000015 # macro SQ_S_SCRATCH_STORE_DWORDX2 = 0x00000016 # macro SQ_S_SCRATCH_STORE_DWORDX4 = 0x00000017 # macro SQ_S_BUFFER_STORE_DWORD = 0x00000018 # macro SQ_S_BUFFER_STORE_DWORDX2 = 0x00000019 # macro SQ_S_BUFFER_STORE_DWORDX4 = 0x0000001a # macro SQ_S_DCACHE_INV = 0x00000020 # macro SQ_S_DCACHE_WB = 0x00000021 # macro SQ_S_DCACHE_INV_VOL = 0x00000022 # macro SQ_S_DCACHE_WB_VOL = 0x00000023 # macro SQ_S_MEMTIME = 0x00000024 # macro SQ_S_MEMREALTIME = 0x00000025 # macro SQ_S_ATC_PROBE = 0x00000026 # macro SQ_S_ATC_PROBE_BUFFER = 0x00000027 # macro SQ_S_BUFFER_ATOMIC_SWAP = 0x00000040 # macro SQ_S_BUFFER_ATOMIC_CMPSWAP = 0x00000041 # macro SQ_S_BUFFER_ATOMIC_ADD = 0x00000042 # macro SQ_S_BUFFER_ATOMIC_SUB = 0x00000043 # macro SQ_S_BUFFER_ATOMIC_SMIN = 0x00000044 # macro SQ_S_BUFFER_ATOMIC_UMIN = 0x00000045 # macro SQ_S_BUFFER_ATOMIC_SMAX = 0x00000046 # macro SQ_S_BUFFER_ATOMIC_UMAX = 0x00000047 # macro SQ_S_BUFFER_ATOMIC_AND = 0x00000048 # macro SQ_S_BUFFER_ATOMIC_OR = 0x00000049 # macro SQ_S_BUFFER_ATOMIC_XOR = 0x0000004a # macro SQ_S_BUFFER_ATOMIC_INC = 0x0000004b # macro SQ_S_BUFFER_ATOMIC_DEC = 0x0000004c # macro SQ_S_BUFFER_ATOMIC_SWAP_X2 = 0x00000060 # macro SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro SQ_S_BUFFER_ATOMIC_ADD_X2 = 0x00000062 # macro SQ_S_BUFFER_ATOMIC_SUB_X2 = 0x00000063 # macro SQ_S_BUFFER_ATOMIC_SMIN_X2 = 0x00000064 # macro SQ_S_BUFFER_ATOMIC_UMIN_X2 = 0x00000065 # macro SQ_S_BUFFER_ATOMIC_SMAX_X2 = 0x00000066 # macro SQ_S_BUFFER_ATOMIC_UMAX_X2 = 0x00000067 # macro SQ_S_BUFFER_ATOMIC_AND_X2 = 0x00000068 # macro SQ_S_BUFFER_ATOMIC_OR_X2 = 0x00000069 # macro SQ_S_BUFFER_ATOMIC_XOR_X2 = 0x0000006a # macro SQ_S_BUFFER_ATOMIC_INC_X2 = 0x0000006b # macro SQ_S_BUFFER_ATOMIC_DEC_X2 = 0x0000006c # macro SQ_S_ATOMIC_SWAP = 0x00000080 # macro SQ_S_ATOMIC_CMPSWAP = 0x00000081 # macro SQ_S_ATOMIC_ADD = 0x00000082 # macro SQ_S_ATOMIC_SUB = 0x00000083 # macro SQ_S_ATOMIC_SMIN = 0x00000084 # macro SQ_S_ATOMIC_UMIN = 0x00000085 # macro SQ_S_ATOMIC_SMAX = 0x00000086 # macro SQ_S_ATOMIC_UMAX = 0x00000087 # macro SQ_S_ATOMIC_AND = 0x00000088 # macro SQ_S_ATOMIC_OR = 0x00000089 # macro SQ_S_ATOMIC_XOR = 0x0000008a # macro SQ_S_ATOMIC_INC = 0x0000008b # macro SQ_S_ATOMIC_DEC = 0x0000008c # macro SQ_S_ATOMIC_SWAP_X2 = 0x000000a0 # macro SQ_S_ATOMIC_CMPSWAP_X2 = 0x000000a1 # macro SQ_S_ATOMIC_ADD_X2 = 0x000000a2 # macro SQ_S_ATOMIC_SUB_X2 = 0x000000a3 # macro SQ_S_ATOMIC_SMIN_X2 = 0x000000a4 # macro SQ_S_ATOMIC_UMIN_X2 = 0x000000a5 # macro SQ_S_ATOMIC_SMAX_X2 = 0x000000a6 # macro SQ_S_ATOMIC_UMAX_X2 = 0x000000a7 # macro SQ_S_ATOMIC_AND_X2 = 0x000000a8 # macro SQ_S_ATOMIC_OR_X2 = 0x000000a9 # macro SQ_S_ATOMIC_XOR_X2 = 0x000000aa # macro SQ_S_ATOMIC_INC_X2 = 0x000000ab # macro SQ_S_ATOMIC_DEC_X2 = 0x000000ac # macro SQ_V_CNDMASK_B32 = 0x00000000 # macro SQ_V_ADD_F32 = 0x00000001 # macro SQ_V_SUB_F32 = 0x00000002 # macro SQ_V_SUBREV_F32 = 0x00000003 # macro SQ_V_MUL_LEGACY_F32 = 0x00000004 # macro SQ_V_MUL_F32 = 0x00000005 # macro SQ_V_MUL_I32_I24 = 0x00000006 # macro SQ_V_MUL_HI_I32_I24 = 0x00000007 # macro SQ_V_MUL_U32_U24 = 0x00000008 # macro SQ_V_MUL_HI_U32_U24 = 0x00000009 # macro SQ_V_MIN_F32 = 0x0000000a # macro SQ_V_MAX_F32 = 0x0000000b # macro SQ_V_MIN_I32 = 0x0000000c # macro SQ_V_MAX_I32 = 0x0000000d # macro SQ_V_MIN_U32 = 0x0000000e # macro SQ_V_MAX_U32 = 0x0000000f # macro SQ_V_LSHRREV_B32 = 0x00000010 # macro SQ_V_ASHRREV_I32 = 0x00000011 # macro SQ_V_LSHLREV_B32 = 0x00000012 # macro SQ_V_AND_B32 = 0x00000013 # macro SQ_V_OR_B32 = 0x00000014 # macro SQ_V_XOR_B32 = 0x00000015 # macro SQ_V_MAC_F32 = 0x00000016 # macro SQ_V_MADMK_F32 = 0x00000017 # macro SQ_V_MADAK_F32 = 0x00000018 # macro SQ_V_ADD_CO_U32 = 0x00000019 # macro SQ_V_SUB_CO_U32 = 0x0000001a # macro SQ_V_SUBREV_CO_U32 = 0x0000001b # macro SQ_V_ADDC_CO_U32 = 0x0000001c # macro SQ_V_SUBB_CO_U32 = 0x0000001d # macro SQ_V_SUBBREV_CO_U32 = 0x0000001e # macro SQ_V_ADD_F16 = 0x0000001f # macro SQ_V_SUB_F16 = 0x00000020 # macro SQ_V_SUBREV_F16 = 0x00000021 # macro SQ_V_MUL_F16 = 0x00000022 # macro SQ_V_MAC_F16 = 0x00000023 # macro SQ_V_MADMK_F16 = 0x00000024 # macro SQ_V_MADAK_F16 = 0x00000025 # macro SQ_V_ADD_U16 = 0x00000026 # macro SQ_V_SUB_U16 = 0x00000027 # macro SQ_V_SUBREV_U16 = 0x00000028 # macro SQ_V_MUL_LO_U16 = 0x00000029 # macro SQ_V_LSHLREV_B16 = 0x0000002a # macro SQ_V_LSHRREV_B16 = 0x0000002b # macro SQ_V_ASHRREV_I16 = 0x0000002c # macro SQ_V_MAX_F16 = 0x0000002d # macro SQ_V_MIN_F16 = 0x0000002e # macro SQ_V_MAX_U16 = 0x0000002f # macro SQ_V_MAX_I16 = 0x00000030 # macro SQ_V_MIN_U16 = 0x00000031 # macro SQ_V_MIN_I16 = 0x00000032 # macro SQ_V_LDEXP_F16 = 0x00000033 # macro SQ_V_ADD_U32 = 0x00000034 # macro SQ_V_SUB_U32 = 0x00000035 # macro SQ_V_SUBREV_U32 = 0x00000036 # macro SQ_SYSMSG_OP_ECC_ERR_INTERRUPT = 0x00000001 # macro SQ_SYSMSG_OP_REG_RD = 0x00000002 # macro SQ_SYSMSG_OP_HOST_TRAP_ACK = 0x00000003 # macro SQ_SYSMSG_OP_TTRACE_PC = 0x00000004 # macro SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT = 0x00000005 # macro SQ_SYSMSG_OP_MEMVIOL_INTERRUPT = 0x00000006 # macro SQ_SRC_VCCZ = 0x000000fb # macro SQ_CHAN_X = 0x00000000 # macro SQ_CHAN_Y = 0x00000001 # macro SQ_CHAN_Z = 0x00000002 # macro SQ_CHAN_W = 0x00000003 # macro SQ_S_MOVK_I32 = 0x00000000 # macro SQ_S_CMOVK_I32 = 0x00000001 # macro SQ_S_CMPK_EQ_I32 = 0x00000002 # macro SQ_S_CMPK_LG_I32 = 0x00000003 # macro SQ_S_CMPK_GT_I32 = 0x00000004 # macro SQ_S_CMPK_GE_I32 = 0x00000005 # macro SQ_S_CMPK_LT_I32 = 0x00000006 # macro SQ_S_CMPK_LE_I32 = 0x00000007 # macro SQ_S_CMPK_EQ_U32 = 0x00000008 # macro SQ_S_CMPK_LG_U32 = 0x00000009 # macro SQ_S_CMPK_GT_U32 = 0x0000000a # macro SQ_S_CMPK_GE_U32 = 0x0000000b # macro SQ_S_CMPK_LT_U32 = 0x0000000c # macro SQ_S_CMPK_LE_U32 = 0x0000000d # macro SQ_S_ADDK_I32 = 0x0000000e # macro SQ_S_MULK_I32 = 0x0000000f # macro SQ_S_CBRANCH_I_FORK = 0x00000010 # macro SQ_S_GETREG_B32 = 0x00000011 # macro SQ_S_SETREG_B32 = 0x00000012 # macro SQ_S_GETREG_REGRD_B32 = 0x00000013 # macro SQ_S_SETREG_IMM32_B32 = 0x00000014 # macro SQ_S_CALL_B64 = 0x00000015 # macro SQ_L1 = 0x00000001 # macro SQ_L2 = 0x00000002 # macro SQ_L3 = 0x00000003 # macro SQ_L4 = 0x00000004 # macro SQ_L5 = 0x00000005 # macro SQ_L6 = 0x00000006 # macro SQ_L7 = 0x00000007 # macro SQ_L8 = 0x00000008 # macro SQ_L9 = 0x00000009 # macro SQ_L10 = 0x0000000a # macro SQ_L11 = 0x0000000b # macro SQ_L12 = 0x0000000c # macro SQ_L13 = 0x0000000d # macro SQ_L14 = 0x0000000e # macro SQ_L15 = 0x0000000f # macro SQ_SGPR0 = 0x00000000 # macro SQ_V_PK_MAD_I16 = 0x00000000 # macro SQ_V_PK_MUL_LO_U16 = 0x00000001 # macro SQ_V_PK_ADD_I16 = 0x00000002 # macro SQ_V_PK_SUB_I16 = 0x00000003 # macro SQ_V_PK_LSHLREV_B16 = 0x00000004 # macro SQ_V_PK_LSHRREV_B16 = 0x00000005 # macro SQ_V_PK_ASHRREV_I16 = 0x00000006 # macro SQ_V_PK_MAX_I16 = 0x00000007 # macro SQ_V_PK_MIN_I16 = 0x00000008 # macro SQ_V_PK_MAD_U16 = 0x00000009 # macro SQ_V_PK_ADD_U16 = 0x0000000a # macro SQ_V_PK_SUB_U16 = 0x0000000b # macro SQ_V_PK_MAX_U16 = 0x0000000c # macro SQ_V_PK_MIN_U16 = 0x0000000d # macro SQ_V_PK_MAD_F16 = 0x0000000e # macro SQ_V_PK_ADD_F16 = 0x0000000f # macro SQ_V_PK_MUL_F16 = 0x00000010 # macro SQ_V_PK_MIN_F16 = 0x00000011 # macro SQ_V_PK_MAX_F16 = 0x00000012 # macro SQ_V_MAD_MIX_F32 = 0x00000020 # macro SQ_V_MAD_MIXLO_F16 = 0x00000021 # macro SQ_V_MAD_MIXHI_F16 = 0x00000022 # macro SQ_V_INTERP_P1_F32 = 0x00000000 # macro SQ_V_INTERP_P2_F32 = 0x00000001 # macro SQ_V_INTERP_MOV_F32 = 0x00000002 # macro SQ_R1 = 0x00000001 # macro SQ_R2 = 0x00000002 # macro SQ_R3 = 0x00000003 # macro SQ_R4 = 0x00000004 # macro SQ_R5 = 0x00000005 # macro SQ_R6 = 0x00000006 # macro SQ_R7 = 0x00000007 # macro SQ_R8 = 0x00000008 # macro SQ_R9 = 0x00000009 # macro SQ_R10 = 0x0000000a # macro SQ_R11 = 0x0000000b # macro SQ_R12 = 0x0000000c # macro SQ_R13 = 0x0000000d # macro SQ_R14 = 0x0000000e # macro SQ_R15 = 0x0000000f # macro SQ_S_ADD_U32 = 0x00000000 # macro SQ_S_SUB_U32 = 0x00000001 # macro SQ_S_ADD_I32 = 0x00000002 # macro SQ_S_SUB_I32 = 0x00000003 # macro SQ_S_ADDC_U32 = 0x00000004 # macro SQ_S_SUBB_U32 = 0x00000005 # macro SQ_S_MIN_I32 = 0x00000006 # macro SQ_S_MIN_U32 = 0x00000007 # macro SQ_S_MAX_I32 = 0x00000008 # macro SQ_S_MAX_U32 = 0x00000009 # macro SQ_S_CSELECT_B32 = 0x0000000a # macro SQ_S_CSELECT_B64 = 0x0000000b # macro SQ_S_AND_B32 = 0x0000000c # macro SQ_S_AND_B64 = 0x0000000d # macro SQ_S_OR_B32 = 0x0000000e # macro SQ_S_OR_B64 = 0x0000000f # macro SQ_S_XOR_B32 = 0x00000010 # macro SQ_S_XOR_B64 = 0x00000011 # macro SQ_S_ANDN2_B32 = 0x00000012 # macro SQ_S_ANDN2_B64 = 0x00000013 # macro SQ_S_ORN2_B32 = 0x00000014 # macro SQ_S_ORN2_B64 = 0x00000015 # macro SQ_S_NAND_B32 = 0x00000016 # macro SQ_S_NAND_B64 = 0x00000017 # macro SQ_S_NOR_B32 = 0x00000018 # macro SQ_S_NOR_B64 = 0x00000019 # macro SQ_S_XNOR_B32 = 0x0000001a # macro SQ_S_XNOR_B64 = 0x0000001b # macro SQ_S_LSHL_B32 = 0x0000001c # macro SQ_S_LSHL_B64 = 0x0000001d # macro SQ_S_LSHR_B32 = 0x0000001e # macro SQ_S_LSHR_B64 = 0x0000001f # macro SQ_S_ASHR_I32 = 0x00000020 # macro SQ_S_ASHR_I64 = 0x00000021 # macro SQ_S_BFM_B32 = 0x00000022 # macro SQ_S_BFM_B64 = 0x00000023 # macro SQ_S_MUL_I32 = 0x00000024 # macro SQ_S_BFE_U32 = 0x00000025 # macro SQ_S_BFE_I32 = 0x00000026 # macro SQ_S_BFE_U64 = 0x00000027 # macro SQ_S_BFE_I64 = 0x00000028 # macro SQ_S_CBRANCH_G_FORK = 0x00000029 # macro SQ_S_ABSDIFF_I32 = 0x0000002a # macro SQ_S_RFE_RESTORE_B64 = 0x0000002b # macro SQ_S_MUL_HI_U32 = 0x0000002c # macro SQ_S_MUL_HI_I32 = 0x0000002d # macro SQ_S_LSHL1_ADD_U32 = 0x0000002e # macro SQ_S_LSHL2_ADD_U32 = 0x0000002f # macro SQ_S_LSHL3_ADD_U32 = 0x00000030 # macro SQ_S_LSHL4_ADD_U32 = 0x00000031 # macro SQ_S_PACK_LL_B32_B16 = 0x00000032 # macro SQ_S_PACK_LH_B32_B16 = 0x00000033 # macro SQ_S_PACK_HH_B32_B16 = 0x00000034 # macro SQ_FLAT = 0x00000000 # macro SQ_SCRATCH = 0x00000001 # macro SQ_GLOBAL = 0x00000002 # macro SQ_EXEC_LO = 0x0000007e # macro SQ_EXEC_HI = 0x0000007f # macro SQ_SRC_64_INT = 0x000000c0 # macro SQ_SRC_M_1_INT = 0x000000c1 # macro SQ_SRC_M_2_INT = 0x000000c2 # macro SQ_SRC_M_3_INT = 0x000000c3 # macro SQ_SRC_M_4_INT = 0x000000c4 # macro SQ_SRC_M_5_INT = 0x000000c5 # macro SQ_SRC_M_6_INT = 0x000000c6 # macro SQ_SRC_M_7_INT = 0x000000c7 # macro SQ_SRC_M_8_INT = 0x000000c8 # macro SQ_SRC_M_9_INT = 0x000000c9 # macro SQ_SRC_M_10_INT = 0x000000ca # macro SQ_SRC_M_11_INT = 0x000000cb # macro SQ_SRC_M_12_INT = 0x000000cc # macro SQ_SRC_M_13_INT = 0x000000cd # macro SQ_SRC_M_14_INT = 0x000000ce # macro SQ_SRC_M_15_INT = 0x000000cf # macro SQ_SRC_M_16_INT = 0x000000d0 # macro SQ_SRC_0_5 = 0x000000f0 # macro SQ_SRC_M_0_5 = 0x000000f1 # macro SQ_SRC_1 = 0x000000f2 # macro SQ_SRC_M_1 = 0x000000f3 # macro SQ_SRC_2 = 0x000000f4 # macro SQ_SRC_M_2 = 0x000000f5 # macro SQ_SRC_4 = 0x000000f6 # macro SQ_SRC_M_4 = 0x000000f7 # macro SQ_SRC_INV_2PI = 0x000000f8 # macro SQ_VCC_LO = 0x0000006a # macro SQ_VCC_HI = 0x0000006b # macro SQ_EXP_MRT0 = 0x00000000 # macro SQ_EXP_MRTZ = 0x00000008 # macro SQ_EXP_NULL = 0x00000009 # macro SQ_EXP_POS0 = 0x0000000c # macro SQ_EXP_PARAM0 = 0x00000020 # macro SQ_S_NOP = 0x00000000 # macro SQ_S_ENDPGM = 0x00000001 # macro SQ_S_BRANCH = 0x00000002 # macro SQ_S_WAKEUP = 0x00000003 # macro SQ_S_CBRANCH_SCC0 = 0x00000004 # macro SQ_S_CBRANCH_SCC1 = 0x00000005 # macro SQ_S_CBRANCH_VCCZ = 0x00000006 # macro SQ_S_CBRANCH_VCCNZ = 0x00000007 # macro SQ_S_CBRANCH_EXECZ = 0x00000008 # macro SQ_S_CBRANCH_EXECNZ = 0x00000009 # macro SQ_S_BARRIER = 0x0000000a # macro SQ_S_SETKILL = 0x0000000b # macro SQ_S_WAITCNT = 0x0000000c # macro SQ_S_SETHALT = 0x0000000d # macro SQ_S_SLEEP = 0x0000000e # macro SQ_S_SETPRIO = 0x0000000f # macro SQ_S_SENDMSG = 0x00000010 # macro SQ_S_SENDMSGHALT = 0x00000011 # macro SQ_S_TRAP = 0x00000012 # macro SQ_S_ICACHE_INV = 0x00000013 # macro SQ_S_INCPERFLEVEL = 0x00000014 # macro SQ_S_DECPERFLEVEL = 0x00000015 # macro SQ_S_TTRACEDATA = 0x00000016 # macro SQ_S_CBRANCH_CDBGSYS = 0x00000017 # macro SQ_S_CBRANCH_CDBGUSER = 0x00000018 # macro SQ_S_CBRANCH_CDBGSYS_OR_USER = 0x00000019 # macro SQ_S_CBRANCH_CDBGSYS_AND_USER = 0x0000001a # macro SQ_S_ENDPGM_SAVED = 0x0000001b # macro SQ_S_SET_GPR_IDX_OFF = 0x0000001c # macro SQ_S_SET_GPR_IDX_MODE = 0x0000001d # macro SQ_S_ENDPGM_ORDERED_PS_DONE = 0x0000001e # macro SQ_EXP = 0x00000000 # macro SQ_SRC_POPS_EXITING_WAVE_ID = 0x000000ef # macro SQ_XNACK_MASK_LO = 0x00000068 # macro SQ_XNACK_MASK_HI = 0x00000069 # macro SQ_OMOD_OFF = 0x00000000 # macro SQ_OMOD_M2 = 0x00000001 # macro SQ_OMOD_M4 = 0x00000002 # macro SQ_OMOD_D2 = 0x00000003 # macro SQ_SRC_EXECZ = 0x000000fc # macro SQ_F = 0x00000000 # macro SQ_LT = 0x00000001 # macro SQ_EQ = 0x00000002 # macro SQ_LE = 0x00000003 # macro SQ_GT = 0x00000004 # macro SQ_NE = 0x00000005 # macro SQ_GE = 0x00000006 # macro SQ_T = 0x00000007 # macro SQ_DPP_BOUND_OFF = 0x00000000 # macro SQ_DPP_BOUND_ZERO = 0x00000001 # macro SQ_M0 = 0x0000007c # macro SQ_MSG_INTERRUPT = 0x00000001 # macro SQ_MSG_GS = 0x00000002 # macro SQ_MSG_GS_DONE = 0x00000003 # macro SQ_MSG_SAVEWAVE = 0x00000004 # macro SQ_MSG_STALL_WAVE_GEN = 0x00000005 # macro SQ_MSG_HALT_WAVES = 0x00000006 # macro SQ_MSG_ORDERED_PS_DONE = 0x00000007 # macro SQ_MSG_EARLY_PRIM_DEALLOC = 0x00000008 # macro SQ_MSG_GS_ALLOC_REQ = 0x00000009 # macro SQ_MSG_SYSMSG = 0x0000000f # macro SQ_PARAM_P10 = 0x00000000 # macro SQ_PARAM_P20 = 0x00000001 # macro SQ_PARAM_P0 = 0x00000002 # macro SQ_V_OPC_OFFSET = 0x00000000 # macro SQ_V_OP2_OFFSET = 0x00000100 # macro SQ_V_OP1_OFFSET = 0x00000140 # macro SQ_V_INTRP_OFFSET = 0x00000270 # macro SQ_V_OP3P_OFFSET = 0x00000380 # macro SQ_SRC_SDWA = 0x000000f9 # macro SQ_SRC_SHARED_BASE = 0x000000eb # macro SQ_SRC_SHARED_LIMIT = 0x000000ec # macro SQ_SRC_PRIVATE_BASE = 0x000000ed # macro SQ_SRC_PRIVATE_LIMIT = 0x000000ee # macro SQ_LG = 0x00000005 # macro SQ_O = 0x00000007 # macro SQ_U = 0x00000008 # macro SQ_NGE = 0x00000009 # macro SQ_NLG = 0x0000000a # macro SQ_NGT = 0x0000000b # macro SQ_NLE = 0x0000000c # macro SQ_NEQ = 0x0000000d # macro SQ_NLT = 0x0000000e # macro SQ_TRU = 0x0000000f # macro SQ_SDWA_UNUSED_PAD = 0x00000000 # macro SQ_SDWA_UNUSED_SEXT = 0x00000001 # macro SQ_SDWA_UNUSED_PRESERVE = 0x00000002 # macro SQ_SRC_SCC = 0x000000fd # macro SQ_V_CMP_CLASS_F32 = 0x00000010 # macro SQ_V_CMPX_CLASS_F32 = 0x00000011 # macro SQ_V_CMP_CLASS_F64 = 0x00000012 # macro SQ_V_CMPX_CLASS_F64 = 0x00000013 # macro SQ_V_CMP_CLASS_F16 = 0x00000014 # macro SQ_V_CMPX_CLASS_F16 = 0x00000015 # macro SQ_V_CMP_F_F16 = 0x00000020 # macro SQ_V_CMP_LT_F16 = 0x00000021 # macro SQ_V_CMP_EQ_F16 = 0x00000022 # macro SQ_V_CMP_LE_F16 = 0x00000023 # macro SQ_V_CMP_GT_F16 = 0x00000024 # macro SQ_V_CMP_LG_F16 = 0x00000025 # macro SQ_V_CMP_GE_F16 = 0x00000026 # macro SQ_V_CMP_O_F16 = 0x00000027 # macro SQ_V_CMP_U_F16 = 0x00000028 # macro SQ_V_CMP_NGE_F16 = 0x00000029 # macro SQ_V_CMP_NLG_F16 = 0x0000002a # macro SQ_V_CMP_NGT_F16 = 0x0000002b # macro SQ_V_CMP_NLE_F16 = 0x0000002c # macro SQ_V_CMP_NEQ_F16 = 0x0000002d # macro SQ_V_CMP_NLT_F16 = 0x0000002e # macro SQ_V_CMP_TRU_F16 = 0x0000002f # macro SQ_V_CMPX_F_F16 = 0x00000030 # macro SQ_V_CMPX_LT_F16 = 0x00000031 # macro SQ_V_CMPX_EQ_F16 = 0x00000032 # macro SQ_V_CMPX_LE_F16 = 0x00000033 # macro SQ_V_CMPX_GT_F16 = 0x00000034 # macro SQ_V_CMPX_LG_F16 = 0x00000035 # macro SQ_V_CMPX_GE_F16 = 0x00000036 # macro SQ_V_CMPX_O_F16 = 0x00000037 # macro SQ_V_CMPX_U_F16 = 0x00000038 # macro SQ_V_CMPX_NGE_F16 = 0x00000039 # macro SQ_V_CMPX_NLG_F16 = 0x0000003a # macro SQ_V_CMPX_NGT_F16 = 0x0000003b # macro SQ_V_CMPX_NLE_F16 = 0x0000003c # macro SQ_V_CMPX_NEQ_F16 = 0x0000003d # macro SQ_V_CMPX_NLT_F16 = 0x0000003e # macro SQ_V_CMPX_TRU_F16 = 0x0000003f # macro SQ_V_CMP_F_F32 = 0x00000040 # macro SQ_V_CMP_LT_F32 = 0x00000041 # macro SQ_V_CMP_EQ_F32 = 0x00000042 # macro SQ_V_CMP_LE_F32 = 0x00000043 # macro SQ_V_CMP_GT_F32 = 0x00000044 # macro SQ_V_CMP_LG_F32 = 0x00000045 # macro SQ_V_CMP_GE_F32 = 0x00000046 # macro SQ_V_CMP_O_F32 = 0x00000047 # macro SQ_V_CMP_U_F32 = 0x00000048 # macro SQ_V_CMP_NGE_F32 = 0x00000049 # macro SQ_V_CMP_NLG_F32 = 0x0000004a # macro SQ_V_CMP_NGT_F32 = 0x0000004b # macro SQ_V_CMP_NLE_F32 = 0x0000004c # macro SQ_V_CMP_NEQ_F32 = 0x0000004d # macro SQ_V_CMP_NLT_F32 = 0x0000004e # macro SQ_V_CMP_TRU_F32 = 0x0000004f # macro SQ_V_CMPX_F_F32 = 0x00000050 # macro SQ_V_CMPX_LT_F32 = 0x00000051 # macro SQ_V_CMPX_EQ_F32 = 0x00000052 # macro SQ_V_CMPX_LE_F32 = 0x00000053 # macro SQ_V_CMPX_GT_F32 = 0x00000054 # macro SQ_V_CMPX_LG_F32 = 0x00000055 # macro SQ_V_CMPX_GE_F32 = 0x00000056 # macro SQ_V_CMPX_O_F32 = 0x00000057 # macro SQ_V_CMPX_U_F32 = 0x00000058 # macro SQ_V_CMPX_NGE_F32 = 0x00000059 # macro SQ_V_CMPX_NLG_F32 = 0x0000005a # macro SQ_V_CMPX_NGT_F32 = 0x0000005b # macro SQ_V_CMPX_NLE_F32 = 0x0000005c # macro SQ_V_CMPX_NEQ_F32 = 0x0000005d # macro SQ_V_CMPX_NLT_F32 = 0x0000005e # macro SQ_V_CMPX_TRU_F32 = 0x0000005f # macro SQ_V_CMP_F_F64 = 0x00000060 # macro SQ_V_CMP_LT_F64 = 0x00000061 # macro SQ_V_CMP_EQ_F64 = 0x00000062 # macro SQ_V_CMP_LE_F64 = 0x00000063 # macro SQ_V_CMP_GT_F64 = 0x00000064 # macro SQ_V_CMP_LG_F64 = 0x00000065 # macro SQ_V_CMP_GE_F64 = 0x00000066 # macro SQ_V_CMP_O_F64 = 0x00000067 # macro SQ_V_CMP_U_F64 = 0x00000068 # macro SQ_V_CMP_NGE_F64 = 0x00000069 # macro SQ_V_CMP_NLG_F64 = 0x0000006a # macro SQ_V_CMP_NGT_F64 = 0x0000006b # macro SQ_V_CMP_NLE_F64 = 0x0000006c # macro SQ_V_CMP_NEQ_F64 = 0x0000006d # macro SQ_V_CMP_NLT_F64 = 0x0000006e # macro SQ_V_CMP_TRU_F64 = 0x0000006f # macro SQ_V_CMPX_F_F64 = 0x00000070 # macro SQ_V_CMPX_LT_F64 = 0x00000071 # macro SQ_V_CMPX_EQ_F64 = 0x00000072 # macro SQ_V_CMPX_LE_F64 = 0x00000073 # macro SQ_V_CMPX_GT_F64 = 0x00000074 # macro SQ_V_CMPX_LG_F64 = 0x00000075 # macro SQ_V_CMPX_GE_F64 = 0x00000076 # macro SQ_V_CMPX_O_F64 = 0x00000077 # macro SQ_V_CMPX_U_F64 = 0x00000078 # macro SQ_V_CMPX_NGE_F64 = 0x00000079 # macro SQ_V_CMPX_NLG_F64 = 0x0000007a # macro SQ_V_CMPX_NGT_F64 = 0x0000007b # macro SQ_V_CMPX_NLE_F64 = 0x0000007c # macro SQ_V_CMPX_NEQ_F64 = 0x0000007d # macro SQ_V_CMPX_NLT_F64 = 0x0000007e # macro SQ_V_CMPX_TRU_F64 = 0x0000007f # macro SQ_V_CMP_F_I16 = 0x000000a0 # macro SQ_V_CMP_LT_I16 = 0x000000a1 # macro SQ_V_CMP_EQ_I16 = 0x000000a2 # macro SQ_V_CMP_LE_I16 = 0x000000a3 # macro SQ_V_CMP_GT_I16 = 0x000000a4 # macro SQ_V_CMP_NE_I16 = 0x000000a5 # macro SQ_V_CMP_GE_I16 = 0x000000a6 # macro SQ_V_CMP_T_I16 = 0x000000a7 # macro SQ_V_CMP_F_U16 = 0x000000a8 # macro SQ_V_CMP_LT_U16 = 0x000000a9 # macro SQ_V_CMP_EQ_U16 = 0x000000aa # macro SQ_V_CMP_LE_U16 = 0x000000ab # macro SQ_V_CMP_GT_U16 = 0x000000ac # macro SQ_V_CMP_NE_U16 = 0x000000ad # macro SQ_V_CMP_GE_U16 = 0x000000ae # macro SQ_V_CMP_T_U16 = 0x000000af # macro SQ_V_CMPX_F_I16 = 0x000000b0 # macro SQ_V_CMPX_LT_I16 = 0x000000b1 # macro SQ_V_CMPX_EQ_I16 = 0x000000b2 # macro SQ_V_CMPX_LE_I16 = 0x000000b3 # macro SQ_V_CMPX_GT_I16 = 0x000000b4 # macro SQ_V_CMPX_NE_I16 = 0x000000b5 # macro SQ_V_CMPX_GE_I16 = 0x000000b6 # macro SQ_V_CMPX_T_I16 = 0x000000b7 # macro SQ_V_CMPX_F_U16 = 0x000000b8 # macro SQ_V_CMPX_LT_U16 = 0x000000b9 # macro SQ_V_CMPX_EQ_U16 = 0x000000ba # macro SQ_V_CMPX_LE_U16 = 0x000000bb # macro SQ_V_CMPX_GT_U16 = 0x000000bc # macro SQ_V_CMPX_NE_U16 = 0x000000bd # macro SQ_V_CMPX_GE_U16 = 0x000000be # macro SQ_V_CMPX_T_U16 = 0x000000bf # macro SQ_V_CMP_F_I32 = 0x000000c0 # macro SQ_V_CMP_LT_I32 = 0x000000c1 # macro SQ_V_CMP_EQ_I32 = 0x000000c2 # macro SQ_V_CMP_LE_I32 = 0x000000c3 # macro SQ_V_CMP_GT_I32 = 0x000000c4 # macro SQ_V_CMP_NE_I32 = 0x000000c5 # macro SQ_V_CMP_GE_I32 = 0x000000c6 # macro SQ_V_CMP_T_I32 = 0x000000c7 # macro SQ_V_CMP_F_U32 = 0x000000c8 # macro SQ_V_CMP_LT_U32 = 0x000000c9 # macro SQ_V_CMP_EQ_U32 = 0x000000ca # macro SQ_V_CMP_LE_U32 = 0x000000cb # macro SQ_V_CMP_GT_U32 = 0x000000cc # macro SQ_V_CMP_NE_U32 = 0x000000cd # macro SQ_V_CMP_GE_U32 = 0x000000ce # macro SQ_V_CMP_T_U32 = 0x000000cf # macro SQ_V_CMPX_F_I32 = 0x000000d0 # macro SQ_V_CMPX_LT_I32 = 0x000000d1 # macro SQ_V_CMPX_EQ_I32 = 0x000000d2 # macro SQ_V_CMPX_LE_I32 = 0x000000d3 # macro SQ_V_CMPX_GT_I32 = 0x000000d4 # macro SQ_V_CMPX_NE_I32 = 0x000000d5 # macro SQ_V_CMPX_GE_I32 = 0x000000d6 # macro SQ_V_CMPX_T_I32 = 0x000000d7 # macro SQ_V_CMPX_F_U32 = 0x000000d8 # macro SQ_V_CMPX_LT_U32 = 0x000000d9 # macro SQ_V_CMPX_EQ_U32 = 0x000000da # macro SQ_V_CMPX_LE_U32 = 0x000000db # macro SQ_V_CMPX_GT_U32 = 0x000000dc # macro SQ_V_CMPX_NE_U32 = 0x000000dd # macro SQ_V_CMPX_GE_U32 = 0x000000de # macro SQ_V_CMPX_T_U32 = 0x000000df # macro SQ_V_CMP_F_I64 = 0x000000e0 # macro SQ_V_CMP_LT_I64 = 0x000000e1 # macro SQ_V_CMP_EQ_I64 = 0x000000e2 # macro SQ_V_CMP_LE_I64 = 0x000000e3 # macro SQ_V_CMP_GT_I64 = 0x000000e4 # macro SQ_V_CMP_NE_I64 = 0x000000e5 # macro SQ_V_CMP_GE_I64 = 0x000000e6 # macro SQ_V_CMP_T_I64 = 0x000000e7 # macro SQ_V_CMP_F_U64 = 0x000000e8 # macro SQ_V_CMP_LT_U64 = 0x000000e9 # macro SQ_V_CMP_EQ_U64 = 0x000000ea # macro SQ_V_CMP_LE_U64 = 0x000000eb # macro SQ_V_CMP_GT_U64 = 0x000000ec # macro SQ_V_CMP_NE_U64 = 0x000000ed # macro SQ_V_CMP_GE_U64 = 0x000000ee # macro SQ_V_CMP_T_U64 = 0x000000ef # macro SQ_V_CMPX_F_I64 = 0x000000f0 # macro SQ_V_CMPX_LT_I64 = 0x000000f1 # macro SQ_V_CMPX_EQ_I64 = 0x000000f2 # macro SQ_V_CMPX_LE_I64 = 0x000000f3 # macro SQ_V_CMPX_GT_I64 = 0x000000f4 # macro SQ_V_CMPX_NE_I64 = 0x000000f5 # macro SQ_V_CMPX_GE_I64 = 0x000000f6 # macro SQ_V_CMPX_T_I64 = 0x000000f7 # macro SQ_V_CMPX_F_U64 = 0x000000f8 # macro SQ_V_CMPX_LT_U64 = 0x000000f9 # macro SQ_V_CMPX_EQ_U64 = 0x000000fa # macro SQ_V_CMPX_LE_U64 = 0x000000fb # macro SQ_V_CMPX_GT_U64 = 0x000000fc # macro SQ_V_CMPX_NE_U64 = 0x000000fd # macro SQ_V_CMPX_GE_U64 = 0x000000fe # macro SQ_V_CMPX_T_U64 = 0x000000ff # macro SQ_GS_OP_NOP = 0x00000000 # macro SQ_GS_OP_CUT = 0x00000001 # macro SQ_GS_OP_EMIT = 0x00000002 # macro SQ_GS_OP_EMIT_CUT = 0x00000003 # macro SQ_SRC_LDS_DIRECT = 0x000000fe # macro SQ_ATTR0 = 0x00000000 # macro SQ_EXP_GDS0 = 0x00000018 # macro SQ_S_CMP_EQ_I32 = 0x00000000 # macro SQ_S_CMP_LG_I32 = 0x00000001 # macro SQ_S_CMP_GT_I32 = 0x00000002 # macro SQ_S_CMP_GE_I32 = 0x00000003 # macro SQ_S_CMP_LT_I32 = 0x00000004 # macro SQ_S_CMP_LE_I32 = 0x00000005 # macro SQ_S_CMP_EQ_U32 = 0x00000006 # macro SQ_S_CMP_LG_U32 = 0x00000007 # macro SQ_S_CMP_GT_U32 = 0x00000008 # macro SQ_S_CMP_GE_U32 = 0x00000009 # macro SQ_S_CMP_LT_U32 = 0x0000000a # macro SQ_S_CMP_LE_U32 = 0x0000000b # macro SQ_S_BITCMP0_B32 = 0x0000000c # macro SQ_S_BITCMP1_B32 = 0x0000000d # macro SQ_S_BITCMP0_B64 = 0x0000000e # macro SQ_S_BITCMP1_B64 = 0x0000000f # macro SQ_S_SETVSKIP = 0x00000010 # macro SQ_S_SET_GPR_IDX_ON = 0x00000011 # macro SQ_S_CMP_EQ_U64 = 0x00000012 # macro SQ_S_CMP_LG_U64 = 0x00000013 # macro SQ_TTMP0 = 0x0000006c # macro SQ_TTMP1 = 0x0000006d # macro SQ_TTMP2 = 0x0000006e # macro SQ_TTMP3 = 0x0000006f # macro SQ_TTMP4 = 0x00000070 # macro SQ_TTMP5 = 0x00000071 # macro SQ_TTMP6 = 0x00000072 # macro SQ_TTMP7 = 0x00000073 # macro SQ_TTMP8 = 0x00000074 # macro SQ_TTMP9 = 0x00000075 # macro SQ_TTMP10 = 0x00000076 # macro SQ_TTMP11 = 0x00000077 # macro SQ_TTMP12 = 0x00000078 # macro SQ_TTMP13 = 0x00000079 # macro SQ_TTMP14 = 0x0000007a # macro SQ_TTMP15 = 0x0000007b # macro SQ_SRC_VGPR0 = 0x00000100 # macro SQ_BUFFER_LOAD_FORMAT_X = 0x00000000 # macro SQ_BUFFER_LOAD_FORMAT_XY = 0x00000001 # macro SQ_BUFFER_LOAD_FORMAT_XYZ = 0x00000002 # macro SQ_BUFFER_LOAD_FORMAT_XYZW = 0x00000003 # macro SQ_BUFFER_STORE_FORMAT_X = 0x00000004 # macro SQ_BUFFER_STORE_FORMAT_XY = 0x00000005 # macro SQ_BUFFER_STORE_FORMAT_XYZ = 0x00000006 # macro SQ_BUFFER_STORE_FORMAT_XYZW = 0x00000007 # macro SQ_BUFFER_LOAD_FORMAT_D16_X = 0x00000008 # macro SQ_BUFFER_LOAD_FORMAT_D16_XY = 0x00000009 # macro SQ_BUFFER_LOAD_FORMAT_D16_XYZ = 0x0000000a # macro SQ_BUFFER_LOAD_FORMAT_D16_XYZW = 0x0000000b # macro SQ_BUFFER_STORE_FORMAT_D16_X = 0x0000000c # macro SQ_BUFFER_STORE_FORMAT_D16_XY = 0x0000000d # macro SQ_BUFFER_STORE_FORMAT_D16_XYZ = 0x0000000e # macro SQ_BUFFER_STORE_FORMAT_D16_XYZW = 0x0000000f # macro SQ_BUFFER_LOAD_UBYTE = 0x00000010 # macro SQ_BUFFER_LOAD_SBYTE = 0x00000011 # macro SQ_BUFFER_LOAD_USHORT = 0x00000012 # macro SQ_BUFFER_LOAD_SSHORT = 0x00000013 # macro SQ_BUFFER_LOAD_DWORD = 0x00000014 # macro SQ_BUFFER_LOAD_DWORDX2 = 0x00000015 # macro SQ_BUFFER_LOAD_DWORDX3 = 0x00000016 # macro SQ_BUFFER_LOAD_DWORDX4 = 0x00000017 # macro SQ_BUFFER_STORE_BYTE = 0x00000018 # macro SQ_BUFFER_STORE_SHORT = 0x0000001a # macro SQ_BUFFER_STORE_DWORD = 0x0000001c # macro SQ_BUFFER_STORE_DWORDX2 = 0x0000001d # macro SQ_BUFFER_STORE_DWORDX3 = 0x0000001e # macro SQ_BUFFER_STORE_DWORDX4 = 0x0000001f # macro SQ_BUFFER_STORE_LDS_DWORD = 0x0000003d # macro SQ_BUFFER_WBINVL1 = 0x0000003e # macro SQ_BUFFER_WBINVL1_VOL = 0x0000003f # macro SQ_BUFFER_ATOMIC_SWAP = 0x00000040 # macro SQ_BUFFER_ATOMIC_CMPSWAP = 0x00000041 # macro SQ_BUFFER_ATOMIC_ADD = 0x00000042 # macro SQ_BUFFER_ATOMIC_SUB = 0x00000043 # macro SQ_BUFFER_ATOMIC_SMIN = 0x00000044 # macro SQ_BUFFER_ATOMIC_UMIN = 0x00000045 # macro SQ_BUFFER_ATOMIC_SMAX = 0x00000046 # macro SQ_BUFFER_ATOMIC_UMAX = 0x00000047 # macro SQ_BUFFER_ATOMIC_AND = 0x00000048 # macro SQ_BUFFER_ATOMIC_OR = 0x00000049 # macro SQ_BUFFER_ATOMIC_XOR = 0x0000004a # macro SQ_BUFFER_ATOMIC_INC = 0x0000004b # macro SQ_BUFFER_ATOMIC_DEC = 0x0000004c # macro SQ_BUFFER_ATOMIC_SWAP_X2 = 0x00000060 # macro SQ_BUFFER_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro SQ_BUFFER_ATOMIC_ADD_X2 = 0x00000062 # macro SQ_BUFFER_ATOMIC_SUB_X2 = 0x00000063 # macro SQ_BUFFER_ATOMIC_SMIN_X2 = 0x00000064 # macro SQ_BUFFER_ATOMIC_UMIN_X2 = 0x00000065 # macro SQ_BUFFER_ATOMIC_SMAX_X2 = 0x00000066 # macro SQ_BUFFER_ATOMIC_UMAX_X2 = 0x00000067 # macro SQ_BUFFER_ATOMIC_AND_X2 = 0x00000068 # macro SQ_BUFFER_ATOMIC_OR_X2 = 0x00000069 # macro SQ_BUFFER_ATOMIC_XOR_X2 = 0x0000006a # macro SQ_BUFFER_ATOMIC_INC_X2 = 0x0000006b # macro SQ_BUFFER_ATOMIC_DEC_X2 = 0x0000006c # macro SQ_SDWA_BYTE_0 = 0x00000000 # macro SQ_SDWA_BYTE_1 = 0x00000001 # macro SQ_SDWA_BYTE_2 = 0x00000002 # macro SQ_SDWA_BYTE_3 = 0x00000003 # macro SQ_SDWA_WORD_0 = 0x00000004 # macro SQ_SDWA_WORD_1 = 0x00000005 # macro SQ_SDWA_DWORD = 0x00000006 # macro ROM_SIGNATURE = 0x0000aa55 # macro # values for enumeration 'GDS_PERFCOUNT_SELECT' GDS_PERFCOUNT_SELECT__enumvalues = { 0: 'GDS_PERF_SEL_DS_ADDR_CONFL', 1: 'GDS_PERF_SEL_DS_BANK_CONFL', 2: 'GDS_PERF_SEL_WBUF_FLUSH', 3: 'GDS_PERF_SEL_WR_COMP', 4: 'GDS_PERF_SEL_WBUF_WR', 5: 'GDS_PERF_SEL_RBUF_HIT', 6: 'GDS_PERF_SEL_RBUF_MISS', 7: 'GDS_PERF_SEL_SE0_SH0_NORET', 8: 'GDS_PERF_SEL_SE0_SH0_RET', 9: 'GDS_PERF_SEL_SE0_SH0_ORD_CNT', 10: 'GDS_PERF_SEL_SE0_SH0_2COMP_REQ', 11: 'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID', 12: 'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID', 13: 'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD', 14: 'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP', 15: 'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP', 16: 'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP', 17: 'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP', 18: 'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP', 19: 'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP', 20: 'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP', 21: 'GDS_PERF_SEL_SE0_SH1_NORET', 22: 'GDS_PERF_SEL_SE0_SH1_RET', 23: 'GDS_PERF_SEL_SE0_SH1_ORD_CNT', 24: 'GDS_PERF_SEL_SE0_SH1_2COMP_REQ', 25: 'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID', 26: 'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID', 27: 'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD', 28: 'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP', 29: 'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP', 30: 'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP', 31: 'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP', 32: 'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP', 33: 'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP', 34: 'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP', 35: 'GDS_PERF_SEL_SE1_SH0_NORET', 36: 'GDS_PERF_SEL_SE1_SH0_RET', 37: 'GDS_PERF_SEL_SE1_SH0_ORD_CNT', 38: 'GDS_PERF_SEL_SE1_SH0_2COMP_REQ', 39: 'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID', 40: 'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID', 41: 'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD', 42: 'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP', 43: 'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP', 44: 'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP', 45: 'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP', 46: 'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP', 47: 'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP', 48: 'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP', 49: 'GDS_PERF_SEL_SE1_SH1_NORET', 50: 'GDS_PERF_SEL_SE1_SH1_RET', 51: 'GDS_PERF_SEL_SE1_SH1_ORD_CNT', 52: 'GDS_PERF_SEL_SE1_SH1_2COMP_REQ', 53: 'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID', 54: 'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID', 55: 'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD', 56: 'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP', 57: 'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP', 58: 'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP', 59: 'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP', 60: 'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP', 61: 'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP', 62: 'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP', 63: 'GDS_PERF_SEL_SE2_SH0_NORET', 64: 'GDS_PERF_SEL_SE2_SH0_RET', 65: 'GDS_PERF_SEL_SE2_SH0_ORD_CNT', 66: 'GDS_PERF_SEL_SE2_SH0_2COMP_REQ', 67: 'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID', 68: 'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID', 69: 'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD', 70: 'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP', 71: 'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP', 72: 'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP', 73: 'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP', 74: 'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP', 75: 'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP', 76: 'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP', 77: 'GDS_PERF_SEL_SE2_SH1_NORET', 78: 'GDS_PERF_SEL_SE2_SH1_RET', 79: 'GDS_PERF_SEL_SE2_SH1_ORD_CNT', 80: 'GDS_PERF_SEL_SE2_SH1_2COMP_REQ', 81: 'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID', 82: 'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID', 83: 'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD', 84: 'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP', 85: 'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP', 86: 'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP', 87: 'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP', 88: 'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP', 89: 'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP', 90: 'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP', 91: 'GDS_PERF_SEL_SE3_SH0_NORET', 92: 'GDS_PERF_SEL_SE3_SH0_RET', 93: 'GDS_PERF_SEL_SE3_SH0_ORD_CNT', 94: 'GDS_PERF_SEL_SE3_SH0_2COMP_REQ', 95: 'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID', 96: 'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID', 97: 'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD', 98: 'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP', 99: 'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP', 100: 'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP', 101: 'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP', 102: 'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP', 103: 'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP', 104: 'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP', 105: 'GDS_PERF_SEL_SE3_SH1_NORET', 106: 'GDS_PERF_SEL_SE3_SH1_RET', 107: 'GDS_PERF_SEL_SE3_SH1_ORD_CNT', 108: 'GDS_PERF_SEL_SE3_SH1_2COMP_REQ', 109: 'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID', 110: 'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID', 111: 'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD', 112: 'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP', 113: 'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP', 114: 'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP', 115: 'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP', 116: 'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP', 117: 'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP', 118: 'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP', 119: 'GDS_PERF_SEL_GWS_RELEASED', 120: 'GDS_PERF_SEL_GWS_BYPASS', } GDS_PERF_SEL_DS_ADDR_CONFL = 0 GDS_PERF_SEL_DS_BANK_CONFL = 1 GDS_PERF_SEL_WBUF_FLUSH = 2 GDS_PERF_SEL_WR_COMP = 3 GDS_PERF_SEL_WBUF_WR = 4 GDS_PERF_SEL_RBUF_HIT = 5 GDS_PERF_SEL_RBUF_MISS = 6 GDS_PERF_SEL_SE0_SH0_NORET = 7 GDS_PERF_SEL_SE0_SH0_RET = 8 GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9 GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10 GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11 GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12 GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13 GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14 GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15 GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16 GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17 GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18 GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19 GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20 GDS_PERF_SEL_SE0_SH1_NORET = 21 GDS_PERF_SEL_SE0_SH1_RET = 22 GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23 GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24 GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25 GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26 GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27 GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28 GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29 GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30 GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31 GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32 GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33 GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34 GDS_PERF_SEL_SE1_SH0_NORET = 35 GDS_PERF_SEL_SE1_SH0_RET = 36 GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37 GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38 GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39 GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40 GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41 GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42 GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43 GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44 GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45 GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46 GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47 GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48 GDS_PERF_SEL_SE1_SH1_NORET = 49 GDS_PERF_SEL_SE1_SH1_RET = 50 GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51 GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52 GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53 GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54 GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55 GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56 GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57 GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58 GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59 GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60 GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61 GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62 GDS_PERF_SEL_SE2_SH0_NORET = 63 GDS_PERF_SEL_SE2_SH0_RET = 64 GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65 GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66 GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67 GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68 GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69 GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70 GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71 GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72 GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73 GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74 GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75 GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76 GDS_PERF_SEL_SE2_SH1_NORET = 77 GDS_PERF_SEL_SE2_SH1_RET = 78 GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79 GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80 GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81 GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82 GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83 GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84 GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85 GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86 GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87 GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88 GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89 GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90 GDS_PERF_SEL_SE3_SH0_NORET = 91 GDS_PERF_SEL_SE3_SH0_RET = 92 GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93 GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94 GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95 GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96 GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97 GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98 GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99 GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100 GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101 GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102 GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103 GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104 GDS_PERF_SEL_SE3_SH1_NORET = 105 GDS_PERF_SEL_SE3_SH1_RET = 106 GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107 GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108 GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109 GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110 GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111 GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112 GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113 GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114 GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115 GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116 GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117 GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118 GDS_PERF_SEL_GWS_RELEASED = 119 GDS_PERF_SEL_GWS_BYPASS = 120 GDS_PERFCOUNT_SELECT = ctypes.c_uint32 # enum # values for enumeration 'MEM_PWR_FORCE_CTRL' MEM_PWR_FORCE_CTRL__enumvalues = { 0: 'NO_FORCE_REQUEST', 1: 'FORCE_LIGHT_SLEEP_REQUEST', 2: 'FORCE_DEEP_SLEEP_REQUEST', 3: 'FORCE_SHUT_DOWN_REQUEST', } NO_FORCE_REQUEST = 0 FORCE_LIGHT_SLEEP_REQUEST = 1 FORCE_DEEP_SLEEP_REQUEST = 2 FORCE_SHUT_DOWN_REQUEST = 3 MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum # values for enumeration 'MEM_PWR_FORCE_CTRL2' MEM_PWR_FORCE_CTRL2__enumvalues = { 0: 'NO_FORCE_REQ', 1: 'FORCE_LIGHT_SLEEP_REQ', } NO_FORCE_REQ = 0 FORCE_LIGHT_SLEEP_REQ = 1 MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum # values for enumeration 'MEM_PWR_DIS_CTRL' MEM_PWR_DIS_CTRL__enumvalues = { 0: 'ENABLE_MEM_PWR_CTRL', 1: 'DISABLE_MEM_PWR_CTRL', } ENABLE_MEM_PWR_CTRL = 0 DISABLE_MEM_PWR_CTRL = 1 MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum # values for enumeration 'MEM_PWR_SEL_CTRL' MEM_PWR_SEL_CTRL__enumvalues = { 0: 'DYNAMIC_SHUT_DOWN_ENABLE', 1: 'DYNAMIC_DEEP_SLEEP_ENABLE', 2: 'DYNAMIC_LIGHT_SLEEP_ENABLE', } DYNAMIC_SHUT_DOWN_ENABLE = 0 DYNAMIC_DEEP_SLEEP_ENABLE = 1 DYNAMIC_LIGHT_SLEEP_ENABLE = 2 MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum # values for enumeration 'MEM_PWR_SEL_CTRL2' MEM_PWR_SEL_CTRL2__enumvalues = { 0: 'DYNAMIC_DEEP_SLEEP_EN', 1: 'DYNAMIC_LIGHT_SLEEP_EN', } DYNAMIC_DEEP_SLEEP_EN = 0 DYNAMIC_LIGHT_SLEEP_EN = 1 MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum # values for enumeration 'RowSize' RowSize__enumvalues = { 0: 'ADDR_CONFIG_1KB_ROW', 1: 'ADDR_CONFIG_2KB_ROW', 2: 'ADDR_CONFIG_4KB_ROW', } ADDR_CONFIG_1KB_ROW = 0 ADDR_CONFIG_2KB_ROW = 1 ADDR_CONFIG_4KB_ROW = 2 RowSize = ctypes.c_uint32 # enum # values for enumeration 'SurfaceEndian' SurfaceEndian__enumvalues = { 0: 'ENDIAN_NONE', 1: 'ENDIAN_8IN16', 2: 'ENDIAN_8IN32', 3: 'ENDIAN_8IN64', } ENDIAN_NONE = 0 ENDIAN_8IN16 = 1 ENDIAN_8IN32 = 2 ENDIAN_8IN64 = 3 SurfaceEndian = ctypes.c_uint32 # enum # values for enumeration 'ArrayMode' ArrayMode__enumvalues = { 0: 'ARRAY_LINEAR_GENERAL', 1: 'ARRAY_LINEAR_ALIGNED', 2: 'ARRAY_1D_TILED_THIN1', 3: 'ARRAY_1D_TILED_THICK', 4: 'ARRAY_2D_TILED_THIN1', 5: 'ARRAY_PRT_TILED_THIN1', 6: 'ARRAY_PRT_2D_TILED_THIN1', 7: 'ARRAY_2D_TILED_THICK', 8: 'ARRAY_2D_TILED_XTHICK', 9: 'ARRAY_PRT_TILED_THICK', 10: 'ARRAY_PRT_2D_TILED_THICK', 11: 'ARRAY_PRT_3D_TILED_THIN1', 12: 'ARRAY_3D_TILED_THIN1', 13: 'ARRAY_3D_TILED_THICK', 14: 'ARRAY_3D_TILED_XTHICK', 15: 'ARRAY_PRT_3D_TILED_THICK', } ARRAY_LINEAR_GENERAL = 0 ARRAY_LINEAR_ALIGNED = 1 ARRAY_1D_TILED_THIN1 = 2 ARRAY_1D_TILED_THICK = 3 ARRAY_2D_TILED_THIN1 = 4 ARRAY_PRT_TILED_THIN1 = 5 ARRAY_PRT_2D_TILED_THIN1 = 6 ARRAY_2D_TILED_THICK = 7 ARRAY_2D_TILED_XTHICK = 8 ARRAY_PRT_TILED_THICK = 9 ARRAY_PRT_2D_TILED_THICK = 10 ARRAY_PRT_3D_TILED_THIN1 = 11 ARRAY_3D_TILED_THIN1 = 12 ARRAY_3D_TILED_THICK = 13 ARRAY_3D_TILED_XTHICK = 14 ARRAY_PRT_3D_TILED_THICK = 15 ArrayMode = ctypes.c_uint32 # enum # values for enumeration 'NumPipes' NumPipes__enumvalues = { 0: 'ADDR_CONFIG_1_PIPE', 1: 'ADDR_CONFIG_2_PIPE', 2: 'ADDR_CONFIG_4_PIPE', 3: 'ADDR_CONFIG_8_PIPE', 4: 'ADDR_CONFIG_16_PIPE', 5: 'ADDR_CONFIG_32_PIPE', } ADDR_CONFIG_1_PIPE = 0 ADDR_CONFIG_2_PIPE = 1 ADDR_CONFIG_4_PIPE = 2 ADDR_CONFIG_8_PIPE = 3 ADDR_CONFIG_16_PIPE = 4 ADDR_CONFIG_32_PIPE = 5 NumPipes = ctypes.c_uint32 # enum # values for enumeration 'NumBanksConfig' NumBanksConfig__enumvalues = { 0: 'ADDR_CONFIG_1_BANK', 1: 'ADDR_CONFIG_2_BANK', 2: 'ADDR_CONFIG_4_BANK', 3: 'ADDR_CONFIG_8_BANK', 4: 'ADDR_CONFIG_16_BANK', } ADDR_CONFIG_1_BANK = 0 ADDR_CONFIG_2_BANK = 1 ADDR_CONFIG_4_BANK = 2 ADDR_CONFIG_8_BANK = 3 ADDR_CONFIG_16_BANK = 4 NumBanksConfig = ctypes.c_uint32 # enum # values for enumeration 'PipeInterleaveSize' PipeInterleaveSize__enumvalues = { 0: 'ADDR_CONFIG_PIPE_INTERLEAVE_256B', 1: 'ADDR_CONFIG_PIPE_INTERLEAVE_512B', 2: 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB', 3: 'ADDR_CONFIG_PIPE_INTERLEAVE_2KB', } ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 1 ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 2 ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 3 PipeInterleaveSize = ctypes.c_uint32 # enum # values for enumeration 'BankInterleaveSize' BankInterleaveSize__enumvalues = { 0: 'ADDR_CONFIG_BANK_INTERLEAVE_1', 1: 'ADDR_CONFIG_BANK_INTERLEAVE_2', 2: 'ADDR_CONFIG_BANK_INTERLEAVE_4', 3: 'ADDR_CONFIG_BANK_INTERLEAVE_8', } ADDR_CONFIG_BANK_INTERLEAVE_1 = 0 ADDR_CONFIG_BANK_INTERLEAVE_2 = 1 ADDR_CONFIG_BANK_INTERLEAVE_4 = 2 ADDR_CONFIG_BANK_INTERLEAVE_8 = 3 BankInterleaveSize = ctypes.c_uint32 # enum # values for enumeration 'NumShaderEngines' NumShaderEngines__enumvalues = { 0: 'ADDR_CONFIG_1_SHADER_ENGINE', 1: 'ADDR_CONFIG_2_SHADER_ENGINE', 2: 'ADDR_CONFIG_4_SHADER_ENGINE', 3: 'ADDR_CONFIG_8_SHADER_ENGINE', } ADDR_CONFIG_1_SHADER_ENGINE = 0 ADDR_CONFIG_2_SHADER_ENGINE = 1 ADDR_CONFIG_4_SHADER_ENGINE = 2 ADDR_CONFIG_8_SHADER_ENGINE = 3 NumShaderEngines = ctypes.c_uint32 # enum # values for enumeration 'NumRbPerShaderEngine' NumRbPerShaderEngine__enumvalues = { 0: 'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE', 1: 'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE', 2: 'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE', } ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0 ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 1 ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 2 NumRbPerShaderEngine = ctypes.c_uint32 # enum # values for enumeration 'NumGPUs' NumGPUs__enumvalues = { 0: 'ADDR_CONFIG_1_GPU', 1: 'ADDR_CONFIG_2_GPU', 2: 'ADDR_CONFIG_4_GPU', 3: 'ADDR_CONFIG_8_GPU', } ADDR_CONFIG_1_GPU = 0 ADDR_CONFIG_2_GPU = 1 ADDR_CONFIG_4_GPU = 2 ADDR_CONFIG_8_GPU = 3 NumGPUs = ctypes.c_uint32 # enum # values for enumeration 'NumMaxCompressedFragments' NumMaxCompressedFragments__enumvalues = { 0: 'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS', 1: 'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS', 2: 'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS', 3: 'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS', } ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0 ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 1 ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 2 ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 3 NumMaxCompressedFragments = ctypes.c_uint32 # enum # values for enumeration 'ShaderEngineTileSize' ShaderEngineTileSize__enumvalues = { 0: 'ADDR_CONFIG_SE_TILE_16', 1: 'ADDR_CONFIG_SE_TILE_32', } ADDR_CONFIG_SE_TILE_16 = 0 ADDR_CONFIG_SE_TILE_32 = 1 ShaderEngineTileSize = ctypes.c_uint32 # enum # values for enumeration 'MultiGPUTileSize' MultiGPUTileSize__enumvalues = { 0: 'ADDR_CONFIG_GPU_TILE_16', 1: 'ADDR_CONFIG_GPU_TILE_32', 2: 'ADDR_CONFIG_GPU_TILE_64', 3: 'ADDR_CONFIG_GPU_TILE_128', } ADDR_CONFIG_GPU_TILE_16 = 0 ADDR_CONFIG_GPU_TILE_32 = 1 ADDR_CONFIG_GPU_TILE_64 = 2 ADDR_CONFIG_GPU_TILE_128 = 3 MultiGPUTileSize = ctypes.c_uint32 # enum # values for enumeration 'NumLowerPipes' NumLowerPipes__enumvalues = { 0: 'ADDR_CONFIG_1_LOWER_PIPES', 1: 'ADDR_CONFIG_2_LOWER_PIPES', } ADDR_CONFIG_1_LOWER_PIPES = 0 ADDR_CONFIG_2_LOWER_PIPES = 1 NumLowerPipes = ctypes.c_uint32 # enum # values for enumeration 'ColorTransform' ColorTransform__enumvalues = { 0: 'DCC_CT_AUTO', 1: 'DCC_CT_NONE', 2: 'ABGR_TO_A_BG_G_RB', 3: 'BGRA_TO_BG_G_RB_A', } DCC_CT_AUTO = 0 DCC_CT_NONE = 1 ABGR_TO_A_BG_G_RB = 2 BGRA_TO_BG_G_RB_A = 3 ColorTransform = ctypes.c_uint32 # enum # values for enumeration 'CompareRef' CompareRef__enumvalues = { 0: 'REF_NEVER', 1: 'REF_LESS', 2: 'REF_EQUAL', 3: 'REF_LEQUAL', 4: 'REF_GREATER', 5: 'REF_NOTEQUAL', 6: 'REF_GEQUAL', 7: 'REF_ALWAYS', } REF_NEVER = 0 REF_LESS = 1 REF_EQUAL = 2 REF_LEQUAL = 3 REF_GREATER = 4 REF_NOTEQUAL = 5 REF_GEQUAL = 6 REF_ALWAYS = 7 CompareRef = ctypes.c_uint32 # enum # values for enumeration 'ReadSize' ReadSize__enumvalues = { 0: 'READ_256_BITS', 1: 'READ_512_BITS', } READ_256_BITS = 0 READ_512_BITS = 1 ReadSize = ctypes.c_uint32 # enum # values for enumeration 'DepthFormat' DepthFormat__enumvalues = { 0: 'DEPTH_INVALID', 1: 'DEPTH_16', 2: 'DEPTH_X8_24', 3: 'DEPTH_8_24', 4: 'DEPTH_X8_24_FLOAT', 5: 'DEPTH_8_24_FLOAT', 6: 'DEPTH_32_FLOAT', 7: 'DEPTH_X24_8_32_FLOAT', } DEPTH_INVALID = 0 DEPTH_16 = 1 DEPTH_X8_24 = 2 DEPTH_8_24 = 3 DEPTH_X8_24_FLOAT = 4 DEPTH_8_24_FLOAT = 5 DEPTH_32_FLOAT = 6 DEPTH_X24_8_32_FLOAT = 7 DepthFormat = ctypes.c_uint32 # enum # values for enumeration 'ZFormat' ZFormat__enumvalues = { 0: 'Z_INVALID', 1: 'Z_16', 2: 'Z_24', 3: 'Z_32_FLOAT', } Z_INVALID = 0 Z_16 = 1 Z_24 = 2 Z_32_FLOAT = 3 ZFormat = ctypes.c_uint32 # enum # values for enumeration 'StencilFormat' StencilFormat__enumvalues = { 0: 'STENCIL_INVALID', 1: 'STENCIL_8', } STENCIL_INVALID = 0 STENCIL_8 = 1 StencilFormat = ctypes.c_uint32 # enum # values for enumeration 'CmaskMode' CmaskMode__enumvalues = { 0: 'CMASK_CLEAR_NONE', 1: 'CMASK_CLEAR_ONE', 2: 'CMASK_CLEAR_ALL', 3: 'CMASK_ANY_EXPANDED', 4: 'CMASK_ALPHA0_FRAG1', 5: 'CMASK_ALPHA0_FRAG2', 6: 'CMASK_ALPHA0_FRAG4', 7: 'CMASK_ALPHA0_FRAGS', 8: 'CMASK_ALPHA1_FRAG1', 9: 'CMASK_ALPHA1_FRAG2', 10: 'CMASK_ALPHA1_FRAG4', 11: 'CMASK_ALPHA1_FRAGS', 12: 'CMASK_ALPHAX_FRAG1', 13: 'CMASK_ALPHAX_FRAG2', 14: 'CMASK_ALPHAX_FRAG4', 15: 'CMASK_ALPHAX_FRAGS', } CMASK_CLEAR_NONE = 0 CMASK_CLEAR_ONE = 1 CMASK_CLEAR_ALL = 2 CMASK_ANY_EXPANDED = 3 CMASK_ALPHA0_FRAG1 = 4 CMASK_ALPHA0_FRAG2 = 5 CMASK_ALPHA0_FRAG4 = 6 CMASK_ALPHA0_FRAGS = 7 CMASK_ALPHA1_FRAG1 = 8 CMASK_ALPHA1_FRAG2 = 9 CMASK_ALPHA1_FRAG4 = 10 CMASK_ALPHA1_FRAGS = 11 CMASK_ALPHAX_FRAG1 = 12 CMASK_ALPHAX_FRAG2 = 13 CMASK_ALPHAX_FRAG4 = 14 CMASK_ALPHAX_FRAGS = 15 CmaskMode = ctypes.c_uint32 # enum # values for enumeration 'QuadExportFormat' QuadExportFormat__enumvalues = { 0: 'EXPORT_UNUSED', 1: 'EXPORT_32_R', 2: 'EXPORT_32_GR', 3: 'EXPORT_32_AR', 4: 'EXPORT_FP16_ABGR', 5: 'EXPORT_UNSIGNED16_ABGR', 6: 'EXPORT_SIGNED16_ABGR', 7: 'EXPORT_32_ABGR', 8: 'EXPORT_32BPP_8PIX', 9: 'EXPORT_16_16_UNSIGNED_8PIX', 10: 'EXPORT_16_16_SIGNED_8PIX', 11: 'EXPORT_16_16_FLOAT_8PIX', } EXPORT_UNUSED = 0 EXPORT_32_R = 1 EXPORT_32_GR = 2 EXPORT_32_AR = 3 EXPORT_FP16_ABGR = 4 EXPORT_UNSIGNED16_ABGR = 5 EXPORT_SIGNED16_ABGR = 6 EXPORT_32_ABGR = 7 EXPORT_32BPP_8PIX = 8 EXPORT_16_16_UNSIGNED_8PIX = 9 EXPORT_16_16_SIGNED_8PIX = 10 EXPORT_16_16_FLOAT_8PIX = 11 QuadExportFormat = ctypes.c_uint32 # enum # values for enumeration 'QuadExportFormatOld' QuadExportFormatOld__enumvalues = { 0: 'EXPORT_4P_32BPC_ABGR', 1: 'EXPORT_4P_16BPC_ABGR', 2: 'EXPORT_4P_32BPC_GR', 3: 'EXPORT_4P_32BPC_AR', 4: 'EXPORT_2P_32BPC_ABGR', 5: 'EXPORT_8P_32BPC_R', } EXPORT_4P_32BPC_ABGR = 0 EXPORT_4P_16BPC_ABGR = 1 EXPORT_4P_32BPC_GR = 2 EXPORT_4P_32BPC_AR = 3 EXPORT_2P_32BPC_ABGR = 4 EXPORT_8P_32BPC_R = 5 QuadExportFormatOld = ctypes.c_uint32 # enum # values for enumeration 'ColorFormat' ColorFormat__enumvalues = { 0: 'COLOR_INVALID', 1: 'COLOR_8', 2: 'COLOR_16', 3: 'COLOR_8_8', 4: 'COLOR_32', 5: 'COLOR_16_16', 6: 'COLOR_10_11_11', 7: 'COLOR_11_11_10', 8: 'COLOR_10_10_10_2', 9: 'COLOR_2_10_10_10', 10: 'COLOR_8_8_8_8', 11: 'COLOR_32_32', 12: 'COLOR_16_16_16_16', 13: 'COLOR_RESERVED_13', 14: 'COLOR_32_32_32_32', 15: 'COLOR_RESERVED_15', 16: 'COLOR_5_6_5', 17: 'COLOR_1_5_5_5', 18: 'COLOR_5_5_5_1', 19: 'COLOR_4_4_4_4', 20: 'COLOR_8_24', 21: 'COLOR_24_8', 22: 'COLOR_X24_8_32_FLOAT', 23: 'COLOR_RESERVED_23', 24: 'COLOR_RESERVED_24', 25: 'COLOR_RESERVED_25', 26: 'COLOR_RESERVED_26', 27: 'COLOR_RESERVED_27', 28: 'COLOR_RESERVED_28', 29: 'COLOR_RESERVED_29', 30: 'COLOR_RESERVED_30', 31: 'COLOR_2_10_10_10_6E4', } COLOR_INVALID = 0 COLOR_8 = 1 COLOR_16 = 2 COLOR_8_8 = 3 COLOR_32 = 4 COLOR_16_16 = 5 COLOR_10_11_11 = 6 COLOR_11_11_10 = 7 COLOR_10_10_10_2 = 8 COLOR_2_10_10_10 = 9 COLOR_8_8_8_8 = 10 COLOR_32_32 = 11 COLOR_16_16_16_16 = 12 COLOR_RESERVED_13 = 13 COLOR_32_32_32_32 = 14 COLOR_RESERVED_15 = 15 COLOR_5_6_5 = 16 COLOR_1_5_5_5 = 17 COLOR_5_5_5_1 = 18 COLOR_4_4_4_4 = 19 COLOR_8_24 = 20 COLOR_24_8 = 21 COLOR_X24_8_32_FLOAT = 22 COLOR_RESERVED_23 = 23 COLOR_RESERVED_24 = 24 COLOR_RESERVED_25 = 25 COLOR_RESERVED_26 = 26 COLOR_RESERVED_27 = 27 COLOR_RESERVED_28 = 28 COLOR_RESERVED_29 = 29 COLOR_RESERVED_30 = 30 COLOR_2_10_10_10_6E4 = 31 ColorFormat = ctypes.c_uint32 # enum # values for enumeration 'SurfaceFormat' SurfaceFormat__enumvalues = { 0: 'FMT_INVALID', 1: 'FMT_8', 2: 'FMT_16', 3: 'FMT_8_8', 4: 'FMT_32', 5: 'FMT_16_16', 6: 'FMT_10_11_11', 7: 'FMT_11_11_10', 8: 'FMT_10_10_10_2', 9: 'FMT_2_10_10_10', 10: 'FMT_8_8_8_8', 11: 'FMT_32_32', 12: 'FMT_16_16_16_16', 13: 'FMT_32_32_32', 14: 'FMT_32_32_32_32', 15: 'FMT_RESERVED_4', 16: 'FMT_5_6_5', 17: 'FMT_1_5_5_5', 18: 'FMT_5_5_5_1', 19: 'FMT_4_4_4_4', 20: 'FMT_8_24', 21: 'FMT_24_8', 22: 'FMT_X24_8_32_FLOAT', 23: 'FMT_RESERVED_33', 24: 'FMT_11_11_10_FLOAT', 25: 'FMT_16_FLOAT', 26: 'FMT_32_FLOAT', 27: 'FMT_16_16_FLOAT', 28: 'FMT_8_24_FLOAT', 29: 'FMT_24_8_FLOAT', 30: 'FMT_32_32_FLOAT', 31: 'FMT_10_11_11_FLOAT', 32: 'FMT_16_16_16_16_FLOAT', 33: 'FMT_3_3_2', 34: 'FMT_6_5_5', 35: 'FMT_32_32_32_32_FLOAT', 36: 'FMT_RESERVED_36', 37: 'FMT_1', 38: 'FMT_1_REVERSED', 39: 'FMT_GB_GR', 40: 'FMT_BG_RG', 41: 'FMT_32_AS_8', 42: 'FMT_32_AS_8_8', 43: 'FMT_5_9_9_9_SHAREDEXP', 44: 'FMT_8_8_8', 45: 'FMT_16_16_16', 46: 'FMT_16_16_16_FLOAT', 47: 'FMT_4_4', 48: 'FMT_32_32_32_FLOAT', 49: 'FMT_BC1', 50: 'FMT_BC2', 51: 'FMT_BC3', 52: 'FMT_BC4', 53: 'FMT_BC5', 54: 'FMT_BC6', 55: 'FMT_BC7', 56: 'FMT_32_AS_32_32_32_32', 57: 'FMT_APC3', 58: 'FMT_APC4', 59: 'FMT_APC5', 60: 'FMT_APC6', 61: 'FMT_APC7', 62: 'FMT_CTX1', 63: 'FMT_RESERVED_63', } FMT_INVALID = 0 FMT_8 = 1 FMT_16 = 2 FMT_8_8 = 3 FMT_32 = 4 FMT_16_16 = 5 FMT_10_11_11 = 6 FMT_11_11_10 = 7 FMT_10_10_10_2 = 8 FMT_2_10_10_10 = 9 FMT_8_8_8_8 = 10 FMT_32_32 = 11 FMT_16_16_16_16 = 12 FMT_32_32_32 = 13 FMT_32_32_32_32 = 14 FMT_RESERVED_4 = 15 FMT_5_6_5 = 16 FMT_1_5_5_5 = 17 FMT_5_5_5_1 = 18 FMT_4_4_4_4 = 19 FMT_8_24 = 20 FMT_24_8 = 21 FMT_X24_8_32_FLOAT = 22 FMT_RESERVED_33 = 23 FMT_11_11_10_FLOAT = 24 FMT_16_FLOAT = 25 FMT_32_FLOAT = 26 FMT_16_16_FLOAT = 27 FMT_8_24_FLOAT = 28 FMT_24_8_FLOAT = 29 FMT_32_32_FLOAT = 30 FMT_10_11_11_FLOAT = 31 FMT_16_16_16_16_FLOAT = 32 FMT_3_3_2 = 33 FMT_6_5_5 = 34 FMT_32_32_32_32_FLOAT = 35 FMT_RESERVED_36 = 36 FMT_1 = 37 FMT_1_REVERSED = 38 FMT_GB_GR = 39 FMT_BG_RG = 40 FMT_32_AS_8 = 41 FMT_32_AS_8_8 = 42 FMT_5_9_9_9_SHAREDEXP = 43 FMT_8_8_8 = 44 FMT_16_16_16 = 45 FMT_16_16_16_FLOAT = 46 FMT_4_4 = 47 FMT_32_32_32_FLOAT = 48 FMT_BC1 = 49 FMT_BC2 = 50 FMT_BC3 = 51 FMT_BC4 = 52 FMT_BC5 = 53 FMT_BC6 = 54 FMT_BC7 = 55 FMT_32_AS_32_32_32_32 = 56 FMT_APC3 = 57 FMT_APC4 = 58 FMT_APC5 = 59 FMT_APC6 = 60 FMT_APC7 = 61 FMT_CTX1 = 62 FMT_RESERVED_63 = 63 SurfaceFormat = ctypes.c_uint32 # enum # values for enumeration 'BUF_DATA_FORMAT' BUF_DATA_FORMAT__enumvalues = { 0: 'BUF_DATA_FORMAT_INVALID', 1: 'BUF_DATA_FORMAT_8', 2: 'BUF_DATA_FORMAT_16', 3: 'BUF_DATA_FORMAT_8_8', 4: 'BUF_DATA_FORMAT_32', 5: 'BUF_DATA_FORMAT_16_16', 6: 'BUF_DATA_FORMAT_10_11_11', 7: 'BUF_DATA_FORMAT_11_11_10', 8: 'BUF_DATA_FORMAT_10_10_10_2', 9: 'BUF_DATA_FORMAT_2_10_10_10', 10: 'BUF_DATA_FORMAT_8_8_8_8', 11: 'BUF_DATA_FORMAT_32_32', 12: 'BUF_DATA_FORMAT_16_16_16_16', 13: 'BUF_DATA_FORMAT_32_32_32', 14: 'BUF_DATA_FORMAT_32_32_32_32', 15: 'BUF_DATA_FORMAT_RESERVED_15', } BUF_DATA_FORMAT_INVALID = 0 BUF_DATA_FORMAT_8 = 1 BUF_DATA_FORMAT_16 = 2 BUF_DATA_FORMAT_8_8 = 3 BUF_DATA_FORMAT_32 = 4 BUF_DATA_FORMAT_16_16 = 5 BUF_DATA_FORMAT_10_11_11 = 6 BUF_DATA_FORMAT_11_11_10 = 7 BUF_DATA_FORMAT_10_10_10_2 = 8 BUF_DATA_FORMAT_2_10_10_10 = 9 BUF_DATA_FORMAT_8_8_8_8 = 10 BUF_DATA_FORMAT_32_32 = 11 BUF_DATA_FORMAT_16_16_16_16 = 12 BUF_DATA_FORMAT_32_32_32 = 13 BUF_DATA_FORMAT_32_32_32_32 = 14 BUF_DATA_FORMAT_RESERVED_15 = 15 BUF_DATA_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'IMG_DATA_FORMAT' IMG_DATA_FORMAT__enumvalues = { 0: 'IMG_DATA_FORMAT_INVALID', 1: 'IMG_DATA_FORMAT_8', 2: 'IMG_DATA_FORMAT_16', 3: 'IMG_DATA_FORMAT_8_8', 4: 'IMG_DATA_FORMAT_32', 5: 'IMG_DATA_FORMAT_16_16', 6: 'IMG_DATA_FORMAT_10_11_11', 7: 'IMG_DATA_FORMAT_11_11_10', 8: 'IMG_DATA_FORMAT_10_10_10_2', 9: 'IMG_DATA_FORMAT_2_10_10_10', 10: 'IMG_DATA_FORMAT_8_8_8_8', 11: 'IMG_DATA_FORMAT_32_32', 12: 'IMG_DATA_FORMAT_16_16_16_16', 13: 'IMG_DATA_FORMAT_32_32_32', 14: 'IMG_DATA_FORMAT_32_32_32_32', 15: 'IMG_DATA_FORMAT_RESERVED_15', 16: 'IMG_DATA_FORMAT_5_6_5', 17: 'IMG_DATA_FORMAT_1_5_5_5', 18: 'IMG_DATA_FORMAT_5_5_5_1', 19: 'IMG_DATA_FORMAT_4_4_4_4', 20: 'IMG_DATA_FORMAT_8_24', 21: 'IMG_DATA_FORMAT_24_8', 22: 'IMG_DATA_FORMAT_X24_8_32', 23: 'IMG_DATA_FORMAT_8_AS_8_8_8_8', 24: 'IMG_DATA_FORMAT_ETC2_RGB', 25: 'IMG_DATA_FORMAT_ETC2_RGBA', 26: 'IMG_DATA_FORMAT_ETC2_R', 27: 'IMG_DATA_FORMAT_ETC2_RG', 28: 'IMG_DATA_FORMAT_ETC2_RGBA1', 29: 'IMG_DATA_FORMAT_RESERVED_29', 30: 'IMG_DATA_FORMAT_RESERVED_30', 31: 'IMG_DATA_FORMAT_6E4', 32: 'IMG_DATA_FORMAT_GB_GR', 33: 'IMG_DATA_FORMAT_BG_RG', 34: 'IMG_DATA_FORMAT_5_9_9_9', 35: 'IMG_DATA_FORMAT_BC1', 36: 'IMG_DATA_FORMAT_BC2', 37: 'IMG_DATA_FORMAT_BC3', 38: 'IMG_DATA_FORMAT_BC4', 39: 'IMG_DATA_FORMAT_BC5', 40: 'IMG_DATA_FORMAT_BC6', 41: 'IMG_DATA_FORMAT_BC7', 42: 'IMG_DATA_FORMAT_16_AS_32_32', 43: 'IMG_DATA_FORMAT_16_AS_16_16_16_16', 44: 'IMG_DATA_FORMAT_16_AS_32_32_32_32', 45: 'IMG_DATA_FORMAT_FMASK', 46: 'IMG_DATA_FORMAT_ASTC_2D_LDR', 47: 'IMG_DATA_FORMAT_ASTC_2D_HDR', 48: 'IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB', 49: 'IMG_DATA_FORMAT_ASTC_3D_LDR', 50: 'IMG_DATA_FORMAT_ASTC_3D_HDR', 51: 'IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB', 52: 'IMG_DATA_FORMAT_N_IN_16', 53: 'IMG_DATA_FORMAT_N_IN_16_16', 54: 'IMG_DATA_FORMAT_N_IN_16_16_16_16', 55: 'IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16', 56: 'IMG_DATA_FORMAT_RESERVED_56', 57: 'IMG_DATA_FORMAT_4_4', 58: 'IMG_DATA_FORMAT_6_5_5', 59: 'IMG_DATA_FORMAT_RESERVED_59', 60: 'IMG_DATA_FORMAT_RESERVED_60', 61: 'IMG_DATA_FORMAT_8_AS_32', 62: 'IMG_DATA_FORMAT_8_AS_32_32', 63: 'IMG_DATA_FORMAT_32_AS_32_32_32_32', } IMG_DATA_FORMAT_INVALID = 0 IMG_DATA_FORMAT_8 = 1 IMG_DATA_FORMAT_16 = 2 IMG_DATA_FORMAT_8_8 = 3 IMG_DATA_FORMAT_32 = 4 IMG_DATA_FORMAT_16_16 = 5 IMG_DATA_FORMAT_10_11_11 = 6 IMG_DATA_FORMAT_11_11_10 = 7 IMG_DATA_FORMAT_10_10_10_2 = 8 IMG_DATA_FORMAT_2_10_10_10 = 9 IMG_DATA_FORMAT_8_8_8_8 = 10 IMG_DATA_FORMAT_32_32 = 11 IMG_DATA_FORMAT_16_16_16_16 = 12 IMG_DATA_FORMAT_32_32_32 = 13 IMG_DATA_FORMAT_32_32_32_32 = 14 IMG_DATA_FORMAT_RESERVED_15 = 15 IMG_DATA_FORMAT_5_6_5 = 16 IMG_DATA_FORMAT_1_5_5_5 = 17 IMG_DATA_FORMAT_5_5_5_1 = 18 IMG_DATA_FORMAT_4_4_4_4 = 19 IMG_DATA_FORMAT_8_24 = 20 IMG_DATA_FORMAT_24_8 = 21 IMG_DATA_FORMAT_X24_8_32 = 22 IMG_DATA_FORMAT_8_AS_8_8_8_8 = 23 IMG_DATA_FORMAT_ETC2_RGB = 24 IMG_DATA_FORMAT_ETC2_RGBA = 25 IMG_DATA_FORMAT_ETC2_R = 26 IMG_DATA_FORMAT_ETC2_RG = 27 IMG_DATA_FORMAT_ETC2_RGBA1 = 28 IMG_DATA_FORMAT_RESERVED_29 = 29 IMG_DATA_FORMAT_RESERVED_30 = 30 IMG_DATA_FORMAT_6E4 = 31 IMG_DATA_FORMAT_GB_GR = 32 IMG_DATA_FORMAT_BG_RG = 33 IMG_DATA_FORMAT_5_9_9_9 = 34 IMG_DATA_FORMAT_BC1 = 35 IMG_DATA_FORMAT_BC2 = 36 IMG_DATA_FORMAT_BC3 = 37 IMG_DATA_FORMAT_BC4 = 38 IMG_DATA_FORMAT_BC5 = 39 IMG_DATA_FORMAT_BC6 = 40 IMG_DATA_FORMAT_BC7 = 41 IMG_DATA_FORMAT_16_AS_32_32 = 42 IMG_DATA_FORMAT_16_AS_16_16_16_16 = 43 IMG_DATA_FORMAT_16_AS_32_32_32_32 = 44 IMG_DATA_FORMAT_FMASK = 45 IMG_DATA_FORMAT_ASTC_2D_LDR = 46 IMG_DATA_FORMAT_ASTC_2D_HDR = 47 IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB = 48 IMG_DATA_FORMAT_ASTC_3D_LDR = 49 IMG_DATA_FORMAT_ASTC_3D_HDR = 50 IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB = 51 IMG_DATA_FORMAT_N_IN_16 = 52 IMG_DATA_FORMAT_N_IN_16_16 = 53 IMG_DATA_FORMAT_N_IN_16_16_16_16 = 54 IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 = 55 IMG_DATA_FORMAT_RESERVED_56 = 56 IMG_DATA_FORMAT_4_4 = 57 IMG_DATA_FORMAT_6_5_5 = 58 IMG_DATA_FORMAT_RESERVED_59 = 59 IMG_DATA_FORMAT_RESERVED_60 = 60 IMG_DATA_FORMAT_8_AS_32 = 61 IMG_DATA_FORMAT_8_AS_32_32 = 62 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 63 IMG_DATA_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'BUF_NUM_FORMAT' BUF_NUM_FORMAT__enumvalues = { 0: 'BUF_NUM_FORMAT_UNORM', 1: 'BUF_NUM_FORMAT_SNORM', 2: 'BUF_NUM_FORMAT_USCALED', 3: 'BUF_NUM_FORMAT_SSCALED', 4: 'BUF_NUM_FORMAT_UINT', 5: 'BUF_NUM_FORMAT_SINT', 6: 'BUF_NUM_FORMAT_UNORM_UINT', 7: 'BUF_NUM_FORMAT_FLOAT', } BUF_NUM_FORMAT_UNORM = 0 BUF_NUM_FORMAT_SNORM = 1 BUF_NUM_FORMAT_USCALED = 2 BUF_NUM_FORMAT_SSCALED = 3 BUF_NUM_FORMAT_UINT = 4 BUF_NUM_FORMAT_SINT = 5 BUF_NUM_FORMAT_UNORM_UINT = 6 BUF_NUM_FORMAT_FLOAT = 7 BUF_NUM_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'IMG_NUM_FORMAT' IMG_NUM_FORMAT__enumvalues = { 0: 'IMG_NUM_FORMAT_UNORM', 1: 'IMG_NUM_FORMAT_SNORM', 2: 'IMG_NUM_FORMAT_USCALED', 3: 'IMG_NUM_FORMAT_SSCALED', 4: 'IMG_NUM_FORMAT_UINT', 5: 'IMG_NUM_FORMAT_SINT', 6: 'IMG_NUM_FORMAT_UNORM_UINT', 7: 'IMG_NUM_FORMAT_FLOAT', 8: 'IMG_NUM_FORMAT_RESERVED_8', 9: 'IMG_NUM_FORMAT_SRGB', 10: 'IMG_NUM_FORMAT_RESERVED_10', 11: 'IMG_NUM_FORMAT_RESERVED_11', 12: 'IMG_NUM_FORMAT_RESERVED_12', 13: 'IMG_NUM_FORMAT_RESERVED_13', 14: 'IMG_NUM_FORMAT_RESERVED_14', 15: 'IMG_NUM_FORMAT_RESERVED_15', } IMG_NUM_FORMAT_UNORM = 0 IMG_NUM_FORMAT_SNORM = 1 IMG_NUM_FORMAT_USCALED = 2 IMG_NUM_FORMAT_SSCALED = 3 IMG_NUM_FORMAT_UINT = 4 IMG_NUM_FORMAT_SINT = 5 IMG_NUM_FORMAT_UNORM_UINT = 6 IMG_NUM_FORMAT_FLOAT = 7 IMG_NUM_FORMAT_RESERVED_8 = 8 IMG_NUM_FORMAT_SRGB = 9 IMG_NUM_FORMAT_RESERVED_10 = 10 IMG_NUM_FORMAT_RESERVED_11 = 11 IMG_NUM_FORMAT_RESERVED_12 = 12 IMG_NUM_FORMAT_RESERVED_13 = 13 IMG_NUM_FORMAT_RESERVED_14 = 14 IMG_NUM_FORMAT_RESERVED_15 = 15 IMG_NUM_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'IMG_NUM_FORMAT_FMASK' IMG_NUM_FORMAT_FMASK__enumvalues = { 0: 'IMG_NUM_FORMAT_FMASK_8_2_1', 1: 'IMG_NUM_FORMAT_FMASK_8_4_1', 2: 'IMG_NUM_FORMAT_FMASK_8_8_1', 3: 'IMG_NUM_FORMAT_FMASK_8_2_2', 4: 'IMG_NUM_FORMAT_FMASK_8_4_2', 5: 'IMG_NUM_FORMAT_FMASK_8_4_4', 6: 'IMG_NUM_FORMAT_FMASK_16_16_1', 7: 'IMG_NUM_FORMAT_FMASK_16_8_2', 8: 'IMG_NUM_FORMAT_FMASK_32_16_2', 9: 'IMG_NUM_FORMAT_FMASK_32_8_4', 10: 'IMG_NUM_FORMAT_FMASK_32_8_8', 11: 'IMG_NUM_FORMAT_FMASK_64_16_4', 12: 'IMG_NUM_FORMAT_FMASK_64_16_8', 13: 'IMG_NUM_FORMAT_FMASK_RESERVED_13', 14: 'IMG_NUM_FORMAT_FMASK_RESERVED_14', 15: 'IMG_NUM_FORMAT_FMASK_RESERVED_15', } IMG_NUM_FORMAT_FMASK_8_2_1 = 0 IMG_NUM_FORMAT_FMASK_8_4_1 = 1 IMG_NUM_FORMAT_FMASK_8_8_1 = 2 IMG_NUM_FORMAT_FMASK_8_2_2 = 3 IMG_NUM_FORMAT_FMASK_8_4_2 = 4 IMG_NUM_FORMAT_FMASK_8_4_4 = 5 IMG_NUM_FORMAT_FMASK_16_16_1 = 6 IMG_NUM_FORMAT_FMASK_16_8_2 = 7 IMG_NUM_FORMAT_FMASK_32_16_2 = 8 IMG_NUM_FORMAT_FMASK_32_8_4 = 9 IMG_NUM_FORMAT_FMASK_32_8_8 = 10 IMG_NUM_FORMAT_FMASK_64_16_4 = 11 IMG_NUM_FORMAT_FMASK_64_16_8 = 12 IMG_NUM_FORMAT_FMASK_RESERVED_13 = 13 IMG_NUM_FORMAT_FMASK_RESERVED_14 = 14 IMG_NUM_FORMAT_FMASK_RESERVED_15 = 15 IMG_NUM_FORMAT_FMASK = ctypes.c_uint32 # enum # values for enumeration 'IMG_NUM_FORMAT_N_IN_16' IMG_NUM_FORMAT_N_IN_16__enumvalues = { 0: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_0', 1: 'IMG_NUM_FORMAT_N_IN_16_UNORM_10', 2: 'IMG_NUM_FORMAT_N_IN_16_UNORM_9', 3: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_3', 4: 'IMG_NUM_FORMAT_N_IN_16_UINT_10', 5: 'IMG_NUM_FORMAT_N_IN_16_UINT_9', 6: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_6', 7: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10', 8: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9', 9: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_9', 10: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_10', 11: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_11', 12: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_12', 13: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_13', 14: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_14', 15: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_15', } IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0 IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 1 IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 2 IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 3 IMG_NUM_FORMAT_N_IN_16_UINT_10 = 4 IMG_NUM_FORMAT_N_IN_16_UINT_9 = 5 IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 6 IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 7 IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 8 IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 9 IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 10 IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 11 IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 12 IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 13 IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 14 IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 15 IMG_NUM_FORMAT_N_IN_16 = ctypes.c_uint32 # enum # values for enumeration 'IMG_NUM_FORMAT_ASTC_2D' IMG_NUM_FORMAT_ASTC_2D__enumvalues = { 0: 'IMG_NUM_FORMAT_ASTC_2D_4x4', 1: 'IMG_NUM_FORMAT_ASTC_2D_5x4', 2: 'IMG_NUM_FORMAT_ASTC_2D_5x5', 3: 'IMG_NUM_FORMAT_ASTC_2D_6x5', 4: 'IMG_NUM_FORMAT_ASTC_2D_6x6', 5: 'IMG_NUM_FORMAT_ASTC_2D_8x5', 6: 'IMG_NUM_FORMAT_ASTC_2D_8x6', 7: 'IMG_NUM_FORMAT_ASTC_2D_8x8', 8: 'IMG_NUM_FORMAT_ASTC_2D_10x5', 9: 'IMG_NUM_FORMAT_ASTC_2D_10x6', 10: 'IMG_NUM_FORMAT_ASTC_2D_10x8', 11: 'IMG_NUM_FORMAT_ASTC_2D_10x10', 12: 'IMG_NUM_FORMAT_ASTC_2D_12x10', 13: 'IMG_NUM_FORMAT_ASTC_2D_12x12', 14: 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_14', 15: 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_15', } IMG_NUM_FORMAT_ASTC_2D_4x4 = 0 IMG_NUM_FORMAT_ASTC_2D_5x4 = 1 IMG_NUM_FORMAT_ASTC_2D_5x5 = 2 IMG_NUM_FORMAT_ASTC_2D_6x5 = 3 IMG_NUM_FORMAT_ASTC_2D_6x6 = 4 IMG_NUM_FORMAT_ASTC_2D_8x5 = 5 IMG_NUM_FORMAT_ASTC_2D_8x6 = 6 IMG_NUM_FORMAT_ASTC_2D_8x8 = 7 IMG_NUM_FORMAT_ASTC_2D_10x5 = 8 IMG_NUM_FORMAT_ASTC_2D_10x6 = 9 IMG_NUM_FORMAT_ASTC_2D_10x8 = 10 IMG_NUM_FORMAT_ASTC_2D_10x10 = 11 IMG_NUM_FORMAT_ASTC_2D_12x10 = 12 IMG_NUM_FORMAT_ASTC_2D_12x12 = 13 IMG_NUM_FORMAT_ASTC_2D_RESERVED_14 = 14 IMG_NUM_FORMAT_ASTC_2D_RESERVED_15 = 15 IMG_NUM_FORMAT_ASTC_2D = ctypes.c_uint32 # enum # values for enumeration 'IMG_NUM_FORMAT_ASTC_3D' IMG_NUM_FORMAT_ASTC_3D__enumvalues = { 0: 'IMG_NUM_FORMAT_ASTC_3D_3x3x3', 1: 'IMG_NUM_FORMAT_ASTC_3D_4x3x3', 2: 'IMG_NUM_FORMAT_ASTC_3D_4x4x3', 3: 'IMG_NUM_FORMAT_ASTC_3D_4x4x4', 4: 'IMG_NUM_FORMAT_ASTC_3D_5x4x4', 5: 'IMG_NUM_FORMAT_ASTC_3D_5x5x4', 6: 'IMG_NUM_FORMAT_ASTC_3D_5x5x5', 7: 'IMG_NUM_FORMAT_ASTC_3D_6x5x5', 8: 'IMG_NUM_FORMAT_ASTC_3D_6x6x5', 9: 'IMG_NUM_FORMAT_ASTC_3D_6x6x6', 10: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_10', 11: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_11', 12: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_12', 13: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_13', 14: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_14', 15: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_15', } IMG_NUM_FORMAT_ASTC_3D_3x3x3 = 0 IMG_NUM_FORMAT_ASTC_3D_4x3x3 = 1 IMG_NUM_FORMAT_ASTC_3D_4x4x3 = 2 IMG_NUM_FORMAT_ASTC_3D_4x4x4 = 3 IMG_NUM_FORMAT_ASTC_3D_5x4x4 = 4 IMG_NUM_FORMAT_ASTC_3D_5x5x4 = 5 IMG_NUM_FORMAT_ASTC_3D_5x5x5 = 6 IMG_NUM_FORMAT_ASTC_3D_6x5x5 = 7 IMG_NUM_FORMAT_ASTC_3D_6x6x5 = 8 IMG_NUM_FORMAT_ASTC_3D_6x6x6 = 9 IMG_NUM_FORMAT_ASTC_3D_RESERVED_10 = 10 IMG_NUM_FORMAT_ASTC_3D_RESERVED_11 = 11 IMG_NUM_FORMAT_ASTC_3D_RESERVED_12 = 12 IMG_NUM_FORMAT_ASTC_3D_RESERVED_13 = 13 IMG_NUM_FORMAT_ASTC_3D_RESERVED_14 = 14 IMG_NUM_FORMAT_ASTC_3D_RESERVED_15 = 15 IMG_NUM_FORMAT_ASTC_3D = ctypes.c_uint32 # enum # values for enumeration 'TileType' TileType__enumvalues = { 0: 'ARRAY_COLOR_TILE', 1: 'ARRAY_DEPTH_TILE', } ARRAY_COLOR_TILE = 0 ARRAY_DEPTH_TILE = 1 TileType = ctypes.c_uint32 # enum # values for enumeration 'NonDispTilingOrder' NonDispTilingOrder__enumvalues = { 0: 'ADDR_SURF_MICRO_TILING_DISPLAY', 1: 'ADDR_SURF_MICRO_TILING_NON_DISPLAY', } ADDR_SURF_MICRO_TILING_DISPLAY = 0 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 1 NonDispTilingOrder = ctypes.c_uint32 # enum # values for enumeration 'MicroTileMode' MicroTileMode__enumvalues = { 0: 'ADDR_SURF_DISPLAY_MICRO_TILING', 1: 'ADDR_SURF_THIN_MICRO_TILING', 2: 'ADDR_SURF_DEPTH_MICRO_TILING', 3: 'ADDR_SURF_ROTATED_MICRO_TILING', 4: 'ADDR_SURF_THICK_MICRO_TILING', } ADDR_SURF_DISPLAY_MICRO_TILING = 0 ADDR_SURF_THIN_MICRO_TILING = 1 ADDR_SURF_DEPTH_MICRO_TILING = 2 ADDR_SURF_ROTATED_MICRO_TILING = 3 ADDR_SURF_THICK_MICRO_TILING = 4 MicroTileMode = ctypes.c_uint32 # enum # values for enumeration 'TileSplit' TileSplit__enumvalues = { 0: 'ADDR_SURF_TILE_SPLIT_64B', 1: 'ADDR_SURF_TILE_SPLIT_128B', 2: 'ADDR_SURF_TILE_SPLIT_256B', 3: 'ADDR_SURF_TILE_SPLIT_512B', 4: 'ADDR_SURF_TILE_SPLIT_1KB', 5: 'ADDR_SURF_TILE_SPLIT_2KB', 6: 'ADDR_SURF_TILE_SPLIT_4KB', } ADDR_SURF_TILE_SPLIT_64B = 0 ADDR_SURF_TILE_SPLIT_128B = 1 ADDR_SURF_TILE_SPLIT_256B = 2 ADDR_SURF_TILE_SPLIT_512B = 3 ADDR_SURF_TILE_SPLIT_1KB = 4 ADDR_SURF_TILE_SPLIT_2KB = 5 ADDR_SURF_TILE_SPLIT_4KB = 6 TileSplit = ctypes.c_uint32 # enum # values for enumeration 'SampleSplit' SampleSplit__enumvalues = { 0: 'ADDR_SURF_SAMPLE_SPLIT_1', 1: 'ADDR_SURF_SAMPLE_SPLIT_2', 2: 'ADDR_SURF_SAMPLE_SPLIT_4', 3: 'ADDR_SURF_SAMPLE_SPLIT_8', } ADDR_SURF_SAMPLE_SPLIT_1 = 0 ADDR_SURF_SAMPLE_SPLIT_2 = 1 ADDR_SURF_SAMPLE_SPLIT_4 = 2 ADDR_SURF_SAMPLE_SPLIT_8 = 3 SampleSplit = ctypes.c_uint32 # enum # values for enumeration 'PipeConfig' PipeConfig__enumvalues = { 0: 'ADDR_SURF_P2', 1: 'ADDR_SURF_P2_RESERVED0', 2: 'ADDR_SURF_P2_RESERVED1', 3: 'ADDR_SURF_P2_RESERVED2', 4: 'ADDR_SURF_P4_8x16', 5: 'ADDR_SURF_P4_16x16', 6: 'ADDR_SURF_P4_16x32', 7: 'ADDR_SURF_P4_32x32', 8: 'ADDR_SURF_P8_16x16_8x16', 9: 'ADDR_SURF_P8_16x32_8x16', 10: 'ADDR_SURF_P8_32x32_8x16', 11: 'ADDR_SURF_P8_16x32_16x16', 12: 'ADDR_SURF_P8_32x32_16x16', 13: 'ADDR_SURF_P8_32x32_16x32', 14: 'ADDR_SURF_P8_32x64_32x32', 15: 'ADDR_SURF_P8_RESERVED0', 16: 'ADDR_SURF_P16_32x32_8x16', 17: 'ADDR_SURF_P16_32x32_16x16', } ADDR_SURF_P2 = 0 ADDR_SURF_P2_RESERVED0 = 1 ADDR_SURF_P2_RESERVED1 = 2 ADDR_SURF_P2_RESERVED2 = 3 ADDR_SURF_P4_8x16 = 4 ADDR_SURF_P4_16x16 = 5 ADDR_SURF_P4_16x32 = 6 ADDR_SURF_P4_32x32 = 7 ADDR_SURF_P8_16x16_8x16 = 8 ADDR_SURF_P8_16x32_8x16 = 9 ADDR_SURF_P8_32x32_8x16 = 10 ADDR_SURF_P8_16x32_16x16 = 11 ADDR_SURF_P8_32x32_16x16 = 12 ADDR_SURF_P8_32x32_16x32 = 13 ADDR_SURF_P8_32x64_32x32 = 14 ADDR_SURF_P8_RESERVED0 = 15 ADDR_SURF_P16_32x32_8x16 = 16 ADDR_SURF_P16_32x32_16x16 = 17 PipeConfig = ctypes.c_uint32 # enum # values for enumeration 'SeEnable' SeEnable__enumvalues = { 0: 'ADDR_CONFIG_DISABLE_SE', 1: 'ADDR_CONFIG_ENABLE_SE', } ADDR_CONFIG_DISABLE_SE = 0 ADDR_CONFIG_ENABLE_SE = 1 SeEnable = ctypes.c_uint32 # enum # values for enumeration 'NumBanks' NumBanks__enumvalues = { 0: 'ADDR_SURF_2_BANK', 1: 'ADDR_SURF_4_BANK', 2: 'ADDR_SURF_8_BANK', 3: 'ADDR_SURF_16_BANK', } ADDR_SURF_2_BANK = 0 ADDR_SURF_4_BANK = 1 ADDR_SURF_8_BANK = 2 ADDR_SURF_16_BANK = 3 NumBanks = ctypes.c_uint32 # enum # values for enumeration 'BankWidth' BankWidth__enumvalues = { 0: 'ADDR_SURF_BANK_WIDTH_1', 1: 'ADDR_SURF_BANK_WIDTH_2', 2: 'ADDR_SURF_BANK_WIDTH_4', 3: 'ADDR_SURF_BANK_WIDTH_8', } ADDR_SURF_BANK_WIDTH_1 = 0 ADDR_SURF_BANK_WIDTH_2 = 1 ADDR_SURF_BANK_WIDTH_4 = 2 ADDR_SURF_BANK_WIDTH_8 = 3 BankWidth = ctypes.c_uint32 # enum # values for enumeration 'BankHeight' BankHeight__enumvalues = { 0: 'ADDR_SURF_BANK_HEIGHT_1', 1: 'ADDR_SURF_BANK_HEIGHT_2', 2: 'ADDR_SURF_BANK_HEIGHT_4', 3: 'ADDR_SURF_BANK_HEIGHT_8', } ADDR_SURF_BANK_HEIGHT_1 = 0 ADDR_SURF_BANK_HEIGHT_2 = 1 ADDR_SURF_BANK_HEIGHT_4 = 2 ADDR_SURF_BANK_HEIGHT_8 = 3 BankHeight = ctypes.c_uint32 # enum # values for enumeration 'BankWidthHeight' BankWidthHeight__enumvalues = { 0: 'ADDR_SURF_BANK_WH_1', 1: 'ADDR_SURF_BANK_WH_2', 2: 'ADDR_SURF_BANK_WH_4', 3: 'ADDR_SURF_BANK_WH_8', } ADDR_SURF_BANK_WH_1 = 0 ADDR_SURF_BANK_WH_2 = 1 ADDR_SURF_BANK_WH_4 = 2 ADDR_SURF_BANK_WH_8 = 3 BankWidthHeight = ctypes.c_uint32 # enum # values for enumeration 'MacroTileAspect' MacroTileAspect__enumvalues = { 0: 'ADDR_SURF_MACRO_ASPECT_1', 1: 'ADDR_SURF_MACRO_ASPECT_2', 2: 'ADDR_SURF_MACRO_ASPECT_4', 3: 'ADDR_SURF_MACRO_ASPECT_8', } ADDR_SURF_MACRO_ASPECT_1 = 0 ADDR_SURF_MACRO_ASPECT_2 = 1 ADDR_SURF_MACRO_ASPECT_4 = 2 ADDR_SURF_MACRO_ASPECT_8 = 3 MacroTileAspect = ctypes.c_uint32 # enum # values for enumeration 'GATCL1RequestType' GATCL1RequestType__enumvalues = { 0: 'GATCL1_TYPE_NORMAL', 1: 'GATCL1_TYPE_SHOOTDOWN', 2: 'GATCL1_TYPE_BYPASS', } GATCL1_TYPE_NORMAL = 0 GATCL1_TYPE_SHOOTDOWN = 1 GATCL1_TYPE_BYPASS = 2 GATCL1RequestType = ctypes.c_uint32 # enum # values for enumeration 'UTCL1RequestType' UTCL1RequestType__enumvalues = { 0: 'UTCL1_TYPE_NORMAL', 1: 'UTCL1_TYPE_SHOOTDOWN', 2: 'UTCL1_TYPE_BYPASS', } UTCL1_TYPE_NORMAL = 0 UTCL1_TYPE_SHOOTDOWN = 1 UTCL1_TYPE_BYPASS = 2 UTCL1RequestType = ctypes.c_uint32 # enum # values for enumeration 'UTCL1FaultType' UTCL1FaultType__enumvalues = { 0: 'UTCL1_XNACK_SUCCESS', 1: 'UTCL1_XNACK_RETRY', 2: 'UTCL1_XNACK_PRT', 3: 'UTCL1_XNACK_NO_RETRY', } UTCL1_XNACK_SUCCESS = 0 UTCL1_XNACK_RETRY = 1 UTCL1_XNACK_PRT = 2 UTCL1_XNACK_NO_RETRY = 3 UTCL1FaultType = ctypes.c_uint32 # enum # values for enumeration 'TCC_CACHE_POLICIES' TCC_CACHE_POLICIES__enumvalues = { 0: 'TCC_CACHE_POLICY_LRU', 1: 'TCC_CACHE_POLICY_STREAM', } TCC_CACHE_POLICY_LRU = 0 TCC_CACHE_POLICY_STREAM = 1 TCC_CACHE_POLICIES = ctypes.c_uint32 # enum # values for enumeration 'MTYPE' MTYPE__enumvalues = { 0: 'MTYPE_NC', 1: 'MTYPE_WC', 1: 'MTYPE_RW', 2: 'MTYPE_CC', 3: 'MTYPE_UC', } MTYPE_NC = 0 MTYPE_WC = 1 MTYPE_RW = 1 MTYPE_CC = 2 MTYPE_UC = 3 MTYPE = ctypes.c_uint32 # enum # values for enumeration 'RMI_CID' RMI_CID__enumvalues = { 0: 'RMI_CID_CC', 1: 'RMI_CID_FC', 2: 'RMI_CID_CM', 3: 'RMI_CID_DC', 4: 'RMI_CID_Z', 5: 'RMI_CID_S', 6: 'RMI_CID_TILE', 7: 'RMI_CID_ZPCPSD', } RMI_CID_CC = 0 RMI_CID_FC = 1 RMI_CID_CM = 2 RMI_CID_DC = 3 RMI_CID_Z = 4 RMI_CID_S = 5 RMI_CID_TILE = 6 RMI_CID_ZPCPSD = 7 RMI_CID = ctypes.c_uint32 # enum # values for enumeration 'PERFMON_COUNTER_MODE' PERFMON_COUNTER_MODE__enumvalues = { 0: 'PERFMON_COUNTER_MODE_ACCUM', 1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', 2: 'PERFMON_COUNTER_MODE_MAX', 3: 'PERFMON_COUNTER_MODE_DIRTY', 4: 'PERFMON_COUNTER_MODE_SAMPLE', 5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', 6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', 7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', 8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', 9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', 15: 'PERFMON_COUNTER_MODE_RESERVED', } PERFMON_COUNTER_MODE_ACCUM = 0 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1 PERFMON_COUNTER_MODE_MAX = 2 PERFMON_COUNTER_MODE_DIRTY = 3 PERFMON_COUNTER_MODE_SAMPLE = 4 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9 PERFMON_COUNTER_MODE_RESERVED = 15 PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum # values for enumeration 'PERFMON_SPM_MODE' PERFMON_SPM_MODE__enumvalues = { 0: 'PERFMON_SPM_MODE_OFF', 1: 'PERFMON_SPM_MODE_16BIT_CLAMP', 2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', 3: 'PERFMON_SPM_MODE_32BIT_CLAMP', 4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', 5: 'PERFMON_SPM_MODE_RESERVED_5', 6: 'PERFMON_SPM_MODE_RESERVED_6', 7: 'PERFMON_SPM_MODE_RESERVED_7', 8: 'PERFMON_SPM_MODE_TEST_MODE_0', 9: 'PERFMON_SPM_MODE_TEST_MODE_1', 10: 'PERFMON_SPM_MODE_TEST_MODE_2', } PERFMON_SPM_MODE_OFF = 0 PERFMON_SPM_MODE_16BIT_CLAMP = 1 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2 PERFMON_SPM_MODE_32BIT_CLAMP = 3 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4 PERFMON_SPM_MODE_RESERVED_5 = 5 PERFMON_SPM_MODE_RESERVED_6 = 6 PERFMON_SPM_MODE_RESERVED_7 = 7 PERFMON_SPM_MODE_TEST_MODE_0 = 8 PERFMON_SPM_MODE_TEST_MODE_1 = 9 PERFMON_SPM_MODE_TEST_MODE_2 = 10 PERFMON_SPM_MODE = ctypes.c_uint32 # enum # values for enumeration 'SurfaceTiling' SurfaceTiling__enumvalues = { 0: 'ARRAY_LINEAR', 1: 'ARRAY_TILED', } ARRAY_LINEAR = 0 ARRAY_TILED = 1 SurfaceTiling = ctypes.c_uint32 # enum # values for enumeration 'SurfaceArray' SurfaceArray__enumvalues = { 0: 'ARRAY_1D', 1: 'ARRAY_2D', 2: 'ARRAY_3D', 3: 'ARRAY_3D_SLICE', } ARRAY_1D = 0 ARRAY_2D = 1 ARRAY_3D = 2 ARRAY_3D_SLICE = 3 SurfaceArray = ctypes.c_uint32 # enum # values for enumeration 'ColorArray' ColorArray__enumvalues = { 0: 'ARRAY_2D_ALT_COLOR', 1: 'ARRAY_2D_COLOR', 3: 'ARRAY_3D_SLICE_COLOR', } ARRAY_2D_ALT_COLOR = 0 ARRAY_2D_COLOR = 1 ARRAY_3D_SLICE_COLOR = 3 ColorArray = ctypes.c_uint32 # enum # values for enumeration 'DepthArray' DepthArray__enumvalues = { 0: 'ARRAY_2D_ALT_DEPTH', 1: 'ARRAY_2D_DEPTH', } ARRAY_2D_ALT_DEPTH = 0 ARRAY_2D_DEPTH = 1 DepthArray = ctypes.c_uint32 # enum # values for enumeration 'ENUM_NUM_SIMD_PER_CU' ENUM_NUM_SIMD_PER_CU__enumvalues = { 4: 'NUM_SIMD_PER_CU', } NUM_SIMD_PER_CU = 4 ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum # values for enumeration 'DSM_ENABLE_ERROR_INJECT' DSM_ENABLE_ERROR_INJECT__enumvalues = { 0: 'DSM_ENABLE_ERROR_INJECT_FED_IN', 1: 'DSM_ENABLE_ERROR_INJECT_SINGLE', 2: 'DSM_ENABLE_ERROR_INJECT_DOUBLE', 3: 'DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED', } DSM_ENABLE_ERROR_INJECT_FED_IN = 0 DSM_ENABLE_ERROR_INJECT_SINGLE = 1 DSM_ENABLE_ERROR_INJECT_DOUBLE = 2 DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED = 3 DSM_ENABLE_ERROR_INJECT = ctypes.c_uint32 # enum # values for enumeration 'DSM_SELECT_INJECT_DELAY' DSM_SELECT_INJECT_DELAY__enumvalues = { 0: 'DSM_SELECT_INJECT_DELAY_NO_DELAY', 1: 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', } DSM_SELECT_INJECT_DELAY_NO_DELAY = 0 DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 1 DSM_SELECT_INJECT_DELAY = ctypes.c_uint32 # enum # values for enumeration 'SWIZZLE_TYPE_ENUM' SWIZZLE_TYPE_ENUM__enumvalues = { 0: 'SW_Z', 1: 'SW_S', 2: 'SW_D', 3: 'SW_R', 4: 'SW_L', } SW_Z = 0 SW_S = 1 SW_D = 2 SW_R = 3 SW_L = 4 SWIZZLE_TYPE_ENUM = ctypes.c_uint32 # enum # values for enumeration 'TC_MICRO_TILE_MODE' TC_MICRO_TILE_MODE__enumvalues = { 0: 'MICRO_TILE_MODE_LINEAR', 1: 'MICRO_TILE_MODE_ROTATED', 2: 'MICRO_TILE_MODE_STD_2D', 3: 'MICRO_TILE_MODE_STD_3D', 4: 'MICRO_TILE_MODE_DISPLAY_2D', 5: 'MICRO_TILE_MODE_DISPLAY_3D', 6: 'MICRO_TILE_MODE_Z_2D', 7: 'MICRO_TILE_MODE_Z_3D', } MICRO_TILE_MODE_LINEAR = 0 MICRO_TILE_MODE_ROTATED = 1 MICRO_TILE_MODE_STD_2D = 2 MICRO_TILE_MODE_STD_3D = 3 MICRO_TILE_MODE_DISPLAY_2D = 4 MICRO_TILE_MODE_DISPLAY_3D = 5 MICRO_TILE_MODE_Z_2D = 6 MICRO_TILE_MODE_Z_3D = 7 TC_MICRO_TILE_MODE = ctypes.c_uint32 # enum # values for enumeration 'SWIZZLE_MODE_ENUM' SWIZZLE_MODE_ENUM__enumvalues = { 0: 'SW_LINEAR', 1: 'SW_256B_S', 2: 'SW_256B_D', 3: 'SW_256B_R', 4: 'SW_4KB_Z', 5: 'SW_4KB_S', 6: 'SW_4KB_D', 7: 'SW_4KB_R', 8: 'SW_64KB_Z', 9: 'SW_64KB_S', 10: 'SW_64KB_D', 11: 'SW_64KB_R', 12: 'SW_VAR_Z', 13: 'SW_VAR_S', 14: 'SW_VAR_D', 15: 'SW_VAR_R', 16: 'SW_RESERVED_16', 17: 'SW_RESERVED_17', 18: 'SW_RESERVED_18', 19: 'SW_RESERVED_19', 20: 'SW_4KB_Z_X', 21: 'SW_4KB_S_X', 22: 'SW_4KB_D_X', 23: 'SW_4KB_R_X', 24: 'SW_64KB_Z_X', 25: 'SW_64KB_S_X', 26: 'SW_64KB_D_X', 27: 'SW_64KB_R_X', 28: 'SW_VAR_Z_X', 29: 'SW_VAR_S_X', 30: 'SW_VAR_D_X', 31: 'SW_VAR_R_X', 32: 'SW_RESERVED_12', 33: 'SW_RESERVED_13', 34: 'SW_RESERVED_14', 35: 'SW_RESERVED_15', } SW_LINEAR = 0 SW_256B_S = 1 SW_256B_D = 2 SW_256B_R = 3 SW_4KB_Z = 4 SW_4KB_S = 5 SW_4KB_D = 6 SW_4KB_R = 7 SW_64KB_Z = 8 SW_64KB_S = 9 SW_64KB_D = 10 SW_64KB_R = 11 SW_VAR_Z = 12 SW_VAR_S = 13 SW_VAR_D = 14 SW_VAR_R = 15 SW_RESERVED_16 = 16 SW_RESERVED_17 = 17 SW_RESERVED_18 = 18 SW_RESERVED_19 = 19 SW_4KB_Z_X = 20 SW_4KB_S_X = 21 SW_4KB_D_X = 22 SW_4KB_R_X = 23 SW_64KB_Z_X = 24 SW_64KB_S_X = 25 SW_64KB_D_X = 26 SW_64KB_R_X = 27 SW_VAR_Z_X = 28 SW_VAR_S_X = 29 SW_VAR_D_X = 30 SW_VAR_R_X = 31 SW_RESERVED_12 = 32 SW_RESERVED_13 = 33 SW_RESERVED_14 = 34 SW_RESERVED_15 = 35 SWIZZLE_MODE_ENUM = ctypes.c_uint32 # enum # values for enumeration 'PipeTiling' PipeTiling__enumvalues = { 0: 'CONFIG_1_PIPE', 1: 'CONFIG_2_PIPE', 2: 'CONFIG_4_PIPE', 3: 'CONFIG_8_PIPE', } CONFIG_1_PIPE = 0 CONFIG_2_PIPE = 1 CONFIG_4_PIPE = 2 CONFIG_8_PIPE = 3 PipeTiling = ctypes.c_uint32 # enum # values for enumeration 'BankTiling' BankTiling__enumvalues = { 0: 'CONFIG_4_BANK', 1: 'CONFIG_8_BANK', } CONFIG_4_BANK = 0 CONFIG_8_BANK = 1 BankTiling = ctypes.c_uint32 # enum # values for enumeration 'GroupInterleave' GroupInterleave__enumvalues = { 0: 'CONFIG_256B_GROUP', 1: 'CONFIG_512B_GROUP', } CONFIG_256B_GROUP = 0 CONFIG_512B_GROUP = 1 GroupInterleave = ctypes.c_uint32 # enum # values for enumeration 'RowTiling' RowTiling__enumvalues = { 0: 'CONFIG_1KB_ROW', 1: 'CONFIG_2KB_ROW', 2: 'CONFIG_4KB_ROW', 3: 'CONFIG_8KB_ROW', 4: 'CONFIG_1KB_ROW_OPT', 5: 'CONFIG_2KB_ROW_OPT', 6: 'CONFIG_4KB_ROW_OPT', 7: 'CONFIG_8KB_ROW_OPT', } CONFIG_1KB_ROW = 0 CONFIG_2KB_ROW = 1 CONFIG_4KB_ROW = 2 CONFIG_8KB_ROW = 3 CONFIG_1KB_ROW_OPT = 4 CONFIG_2KB_ROW_OPT = 5 CONFIG_4KB_ROW_OPT = 6 CONFIG_8KB_ROW_OPT = 7 RowTiling = ctypes.c_uint32 # enum # values for enumeration 'BankSwapBytes' BankSwapBytes__enumvalues = { 0: 'CONFIG_128B_SWAPS', 1: 'CONFIG_256B_SWAPS', 2: 'CONFIG_512B_SWAPS', 3: 'CONFIG_1KB_SWAPS', } CONFIG_128B_SWAPS = 0 CONFIG_256B_SWAPS = 1 CONFIG_512B_SWAPS = 2 CONFIG_1KB_SWAPS = 3 BankSwapBytes = ctypes.c_uint32 # enum # values for enumeration 'SampleSplitBytes' SampleSplitBytes__enumvalues = { 0: 'CONFIG_1KB_SPLIT', 1: 'CONFIG_2KB_SPLIT', 2: 'CONFIG_4KB_SPLIT', 3: 'CONFIG_8KB_SPLIT', } CONFIG_1KB_SPLIT = 0 CONFIG_2KB_SPLIT = 1 CONFIG_4KB_SPLIT = 2 CONFIG_8KB_SPLIT = 3 SampleSplitBytes = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR' OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR' OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS' OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY' OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE' OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE' OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE' OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN' OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET' OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE' OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE' OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR' OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE' OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', } OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum # values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS' OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', 8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', 9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', 10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', 11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', 12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', 13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', 14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', 15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', } OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_CONTROL_BLND_MODE' BLNDV_CONTROL_BLND_MODE__enumvalues = { 0: 'BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', 1: 'BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', 2: 'BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', 3: 'BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', } BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0 BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 1 BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 2 BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 3 BLNDV_CONTROL_BLND_MODE = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_CONTROL_BLND_STEREO_TYPE' BLNDV_CONTROL_BLND_STEREO_TYPE__enumvalues = { 0: 'BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', 1: 'BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', 2: 'BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', 3: 'BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED', } BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0 BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 1 BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 2 BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 3 BLNDV_CONTROL_BLND_STEREO_TYPE = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_CONTROL_BLND_STEREO_POLARITY' BLNDV_CONTROL_BLND_STEREO_POLARITY__enumvalues = { 0: 'BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW', 1: 'BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH', } BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0 BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 1 BLNDV_CONTROL_BLND_STEREO_POLARITY = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN' BLNDV_CONTROL_BLND_FEEDTHROUGH_EN__enumvalues = { 0: 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', 1: 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', } BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0 BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 1 BLNDV_CONTROL_BLND_FEEDTHROUGH_EN = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_CONTROL_BLND_ALPHA_MODE' BLNDV_CONTROL_BLND_ALPHA_MODE__enumvalues = { 0: 'BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', 1: 'BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', 2: 'BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', 3: 'BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED', } BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0 BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 2 BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 3 BLNDV_CONTROL_BLND_ALPHA_MODE = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY' BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY__enumvalues = { 0: 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE', 1: 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE', } BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE = 0 BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE = 1 BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE' BLNDV_CONTROL_BLND_MULTIPLIED_MODE__enumvalues = { 0: 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE', 1: 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE', } BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0 BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 1 BLNDV_CONTROL_BLND_MULTIPLIED_MODE = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_SM_CONTROL2_SM_MODE' BLNDV_SM_CONTROL2_SM_MODE__enumvalues = { 0: 'BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE', 2: 'BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', 4: 'BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', 6: 'BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', } BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0 BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 2 BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 4 BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 BLNDV_SM_CONTROL2_SM_MODE = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE' BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE__enumvalues = { 0: 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', 1: 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', } BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0 BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 1 BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE' BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE__enumvalues = { 0: 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', 1: 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', } BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0 BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 1 BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL' BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL__enumvalues = { 0: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', 1: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', 2: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', 3: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', } BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL' BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL__enumvalues = { 0: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', 1: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', 2: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', 3: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', } BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_CONTROL2_PTI_ENABLE' BLNDV_CONTROL2_PTI_ENABLE__enumvalues = { 0: 'BLNDV_CONTROL2_PTI_ENABLE_FALSE', 1: 'BLNDV_CONTROL2_PTI_ENABLE_TRUE', } BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0 BLNDV_CONTROL2_PTI_ENABLE_TRUE = 1 BLNDV_CONTROL2_PTI_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN' BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN__enumvalues = { 0: 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', 1: 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', } BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0 BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 1 BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN' BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN__enumvalues = { 0: 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', 1: 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', } BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0 BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 1 BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK' BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK__enumvalues = { 0: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', 1: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', } BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 1 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK' BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK__enumvalues = { 0: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', 1: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', } BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 1 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK' BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK__enumvalues = { 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', } BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 1 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK' BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__enumvalues = { 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', } BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 1 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK' BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK__enumvalues = { 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', } BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 1 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK' BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK__enumvalues = { 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', } BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 1 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK' BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK__enumvalues = { 0: 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', 1: 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', } BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0 BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 1 BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK' BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK__enumvalues = { 0: 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', 1: 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', } BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0 BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 1 BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE' BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE__enumvalues = { 0: 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', 1: 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', } BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0 BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 1 BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT' BLNDV_DEBUG_BLND_CNV_MUX_SELECT__enumvalues = { 0: 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW', 1: 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH', } BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0 BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 1 BLNDV_DEBUG_BLND_CNV_MUX_SELECT = ctypes.c_uint32 # enum # values for enumeration 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN' BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN__enumvalues = { 0: 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', 1: 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', } BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0 BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 1 BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum # values for enumeration 'LBV_PIXEL_DEPTH' LBV_PIXEL_DEPTH__enumvalues = { 0: 'PIXEL_DEPTH_30BPP', 1: 'PIXEL_DEPTH_24BPP', 2: 'PIXEL_DEPTH_18BPP', 3: 'PIXEL_DEPTH_38BPP', } PIXEL_DEPTH_30BPP = 0 PIXEL_DEPTH_24BPP = 1 PIXEL_DEPTH_18BPP = 2 PIXEL_DEPTH_38BPP = 3 LBV_PIXEL_DEPTH = ctypes.c_uint32 # enum # values for enumeration 'LBV_PIXEL_EXPAN_MODE' LBV_PIXEL_EXPAN_MODE__enumvalues = { 0: 'PIXEL_EXPAN_MODE_ZERO_EXP', 1: 'PIXEL_EXPAN_MODE_DYN_EXP', } PIXEL_EXPAN_MODE_ZERO_EXP = 0 PIXEL_EXPAN_MODE_DYN_EXP = 1 LBV_PIXEL_EXPAN_MODE = ctypes.c_uint32 # enum # values for enumeration 'LBV_INTERLEAVE_EN' LBV_INTERLEAVE_EN__enumvalues = { 0: 'INTERLEAVE_DIS', 1: 'INTERLEAVE_EN', } INTERLEAVE_DIS = 0 INTERLEAVE_EN = 1 LBV_INTERLEAVE_EN = ctypes.c_uint32 # enum # values for enumeration 'LBV_PIXEL_REDUCE_MODE' LBV_PIXEL_REDUCE_MODE__enumvalues = { 0: 'PIXEL_REDUCE_MODE_TRUNCATION', 1: 'PIXEL_REDUCE_MODE_ROUNDING', } PIXEL_REDUCE_MODE_TRUNCATION = 0 PIXEL_REDUCE_MODE_ROUNDING = 1 LBV_PIXEL_REDUCE_MODE = ctypes.c_uint32 # enum # values for enumeration 'LBV_DYNAMIC_PIXEL_DEPTH' LBV_DYNAMIC_PIXEL_DEPTH__enumvalues = { 0: 'DYNAMIC_PIXEL_DEPTH_36BPP', 1: 'DYNAMIC_PIXEL_DEPTH_30BPP', } DYNAMIC_PIXEL_DEPTH_36BPP = 0 DYNAMIC_PIXEL_DEPTH_30BPP = 1 LBV_DYNAMIC_PIXEL_DEPTH = ctypes.c_uint32 # enum # values for enumeration 'LBV_DITHER_EN' LBV_DITHER_EN__enumvalues = { 0: 'DITHER_DIS', 1: 'DITHER_EN', } DITHER_DIS = 0 DITHER_EN = 1 LBV_DITHER_EN = ctypes.c_uint32 # enum # values for enumeration 'LBV_DOWNSCALE_PREFETCH_EN' LBV_DOWNSCALE_PREFETCH_EN__enumvalues = { 0: 'DOWNSCALE_PREFETCH_DIS', 1: 'DOWNSCALE_PREFETCH_EN', } DOWNSCALE_PREFETCH_DIS = 0 DOWNSCALE_PREFETCH_EN = 1 LBV_DOWNSCALE_PREFETCH_EN = ctypes.c_uint32 # enum # values for enumeration 'LBV_MEMORY_CONFIG' LBV_MEMORY_CONFIG__enumvalues = { 0: 'MEMORY_CONFIG_0', 1: 'MEMORY_CONFIG_1', 2: 'MEMORY_CONFIG_2', 3: 'MEMORY_CONFIG_3', } MEMORY_CONFIG_0 = 0 MEMORY_CONFIG_1 = 1 MEMORY_CONFIG_2 = 2 MEMORY_CONFIG_3 = 3 LBV_MEMORY_CONFIG = ctypes.c_uint32 # enum # values for enumeration 'LBV_SYNC_RESET_SEL2' LBV_SYNC_RESET_SEL2__enumvalues = { 0: 'SYNC_RESET_SEL2_VBLANK', 1: 'SYNC_RESET_SEL2_VSYNC', } SYNC_RESET_SEL2_VBLANK = 0 SYNC_RESET_SEL2_VSYNC = 1 LBV_SYNC_RESET_SEL2 = ctypes.c_uint32 # enum # values for enumeration 'LBV_SYNC_DURATION' LBV_SYNC_DURATION__enumvalues = { 0: 'SYNC_DURATION_16', 1: 'SYNC_DURATION_32', 2: 'SYNC_DURATION_64', 3: 'SYNC_DURATION_128', } SYNC_DURATION_16 = 0 SYNC_DURATION_32 = 1 SYNC_DURATION_64 = 2 SYNC_DURATION_128 = 3 LBV_SYNC_DURATION = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CONTROL_CRTC_START_POINT_CNTL' CRTC_CONTROL_CRTC_START_POINT_CNTL__enumvalues = { 0: 'CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL', 1: 'CRTC_CONTROL_CRTC_START_POINT_CNTL_DP', } CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 1 CRTC_CONTROL_CRTC_START_POINT_CNTL = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL' CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL__enumvalues = { 0: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL', 1: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP', } CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 1 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL' CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL__enumvalues = { 0: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE', 1: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT', 2: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED', 3: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST', } CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 2 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST = 3 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY' CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY__enumvalues = { 0: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE', 1: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE', } CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 1 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE' CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE__enumvalues = { 0: 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE', 1: 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE', } CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE = 0 CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 1 CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CONTROL_CRTC_SOF_PULL_EN' CRTC_CONTROL_CRTC_SOF_PULL_EN__enumvalues = { 0: 'CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE', 1: 'CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE', } CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0 CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 1 CRTC_CONTROL_CRTC_SOF_PULL_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL' CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL__enumvalues = { 0: 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE', 1: 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE', } CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0 CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 1 CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL = ctypes.c_uint32 # enum # values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL' CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL__enumvalues = { 0: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE', 1: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE', } CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 1 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum # values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL' CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL__enumvalues = { 0: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE', 1: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE', } CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 1 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum # values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN' CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN__enumvalues = { 0: 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE', 1: 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE', } CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE = 1 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC' CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = { 0: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', 1: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', } CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum # values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT' CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT__enumvalues = { 0: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE', 1: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE', } CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE = 1 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum # values for enumeration 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK' CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__enumvalues = { 0: 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE', 1: 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE', } CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0 CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 1 CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR' CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR__enumvalues = { 0: 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE', 1: 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE', } CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0 CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE = 1 CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL' CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL__enumvalues = { 0: 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE', 1: 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE', } CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0 CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 1 CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL = ctypes.c_uint32 # enum # values for enumeration 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN' CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN__enumvalues = { 0: 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE', 1: 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE', } CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0 CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 1 CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT' CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT__enumvalues = { 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER', 2: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER', 5: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF', 6: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE', 7: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA', 8: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA', 9: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB', 10: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB', 11: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1', 12: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2', 13: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD', 14: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC', 16: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0', 17: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1', 18: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2', 19: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON', 20: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA', 21: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB', 22: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW', 23: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW', } CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER = 1 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER = 2 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF = 5 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE = 6 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 7 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 8 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 9 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 10 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 11 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 12 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD = 13 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC = 14 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 16 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 17 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 18 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 19 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA = 20 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB = 21 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW = 22 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW = 23 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum # values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT' CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT__enumvalues = { 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE', 2: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA', 3: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB', 4: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA', 5: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB', 6: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO', 7: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC', } CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE = 1 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA = 2 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB = 3 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA = 4 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB = 5 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 6 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC = 7 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum # values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN' CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN__enumvalues = { 0: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE', 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE', } CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE = 0 CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 1 CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR' CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR__enumvalues = { 0: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE', 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE', } CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0 CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 1 CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT' CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT__enumvalues = { 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER', 2: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER', 5: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF', 6: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE', 7: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA', 8: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA', 9: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB', 10: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB', 11: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1', 12: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2', 13: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD', 14: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC', 16: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0', 17: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1', 18: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2', 19: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON', 20: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA', 21: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB', 22: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW', 23: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW', } CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER = 1 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER = 2 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF = 5 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE = 6 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 7 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 8 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 9 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 10 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 11 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 12 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD = 13 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC = 14 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 16 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 17 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 18 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 19 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA = 20 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB = 21 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW = 22 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW = 23 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum # values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT' CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT__enumvalues = { 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE', 2: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA', 3: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB', 4: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA', 5: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB', 6: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO', 7: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC', } CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE = 1 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA = 2 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB = 3 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA = 4 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB = 5 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 6 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC = 7 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum # values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN' CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN__enumvalues = { 0: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE', 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE', } CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE = 0 CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 1 CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR' CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR__enumvalues = { 0: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE', 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE', } CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0 CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 1 CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE' CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE__enumvalues = { 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE', 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT', 2: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', 3: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED', } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE = 0 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT = 1 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED = 3 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK' CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK__enumvalues = { 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE', 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE', } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE = 0 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE = 1 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum # values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL' CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = { 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE', 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE', } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum # values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR' CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR__enumvalues = { 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE', 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE', } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE = 1 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT' CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT__enumvalues = { 0: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', 1: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF', 2: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE', 3: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1', 4: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2', 5: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', 6: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', 7: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', 8: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', 9: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK', 10: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL', 11: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', 12: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB', 13: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA', 14: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD', 15: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC', } CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 1 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 2 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 3 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 4 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 5 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 6 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 7 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 8 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK = 9 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL = 10 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 11 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 12 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 13 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 14 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 15 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum # values for enumeration 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY' CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY__enumvalues = { 0: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE', 1: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE', } CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE = 0 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE = 1 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum # values for enumeration 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY' CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY__enumvalues = { 0: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE', 1: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE', } CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE = 0 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE = 1 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum # values for enumeration 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE' CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE__enumvalues = { 0: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO', 1: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT', 2: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT', 3: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED', } CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO = 0 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT = 1 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT = 2 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED = 3 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CONTROL_CRTC_MASTER_EN' CRTC_CONTROL_CRTC_MASTER_EN__enumvalues = { 0: 'CRTC_CONTROL_CRTC_MASTER_EN_FALSE', 1: 'CRTC_CONTROL_CRTC_MASTER_EN_TRUE', } CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0 CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 1 CRTC_CONTROL_CRTC_MASTER_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN' CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN__enumvalues = { 0: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE', 1: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE', } CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0 CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 1 CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE' CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE__enumvalues = { 0: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE', 1: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE', } CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0 CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 1 CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE' CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE__enumvalues = { 0: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE', 1: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE', } CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE = 0 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE = 1 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD' CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD__enumvalues = { 0: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT', 1: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD', 2: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN', 3: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2', } CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT = 0 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD = 1 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN = 2 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum # values for enumeration 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY' CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY__enumvalues = { 0: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE', 1: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE', } CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 1 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY = ctypes.c_uint32 # enum # values for enumeration 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT' CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT__enumvalues = { 0: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE', 1: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE', } CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE = 0 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE = 1 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT = ctypes.c_uint32 # enum # values for enumeration 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN' CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN__enumvalues = { 0: 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE', 1: 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE', } CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0 CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 1 CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE' CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = { 0: 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', 1: 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', } CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR' CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = { 0: 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', 1: 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', } CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0 CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1 CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE' CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE__enumvalues = { 0: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE', 1: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA', 2: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB', 3: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED', } CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE = 0 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED = 3 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY' CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = { 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE', 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE', } CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum # values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY' CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY__enumvalues = { 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE', 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE', } CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE = 0 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE = 1 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY = ctypes.c_uint32 # enum # values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY' CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY__enumvalues = { 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE', 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE', } CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE = 0 CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE = 1 CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum # values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN' CRTC_STEREO_CONTROL_CRTC_STEREO_EN__enumvalues = { 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE', 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE', } CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0 CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 1 CRTC_STEREO_CONTROL_CRTC_STEREO_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR' CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR__enumvalues = { 0: 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE', 1: 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE', } CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0 CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 1 CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL' CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = { 0: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', 1: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', 2: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', 3: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', } CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum # values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY' CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY__enumvalues = { 0: 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE', 1: 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE', } CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0 CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE = 1 CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY = ctypes.c_uint32 # enum # values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY' CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY__enumvalues = { 0: 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE', 1: 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE', } CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0 CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE = 1 CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY = ctypes.c_uint32 # enum # values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN' CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN__enumvalues = { 0: 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE', 1: 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE', } CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE = 0 CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE = 1 CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN' CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN__enumvalues = { 0: 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE', 1: 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE', } CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0 CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 1 CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK' CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE' CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK' CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE' CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK' CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE' CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK' CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE' CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK' CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE' CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK' CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE' CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK' CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE' CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK' CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum # values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE' CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE__enumvalues = { 0: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE', 1: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE', } CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK' CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK__enumvalues = { 0: 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE', 1: 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE', } CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0 CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 1 CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY' CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY__enumvalues = { 0: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE', 1: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE', } CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE = 0 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE = 1 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY = ctypes.c_uint32 # enum # values for enumeration 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN' CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__enumvalues = { 0: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE', 1: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE', } CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 1 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE' CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__enumvalues = { 0: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0', 1: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1', } CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 1 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE' CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE__enumvalues = { 0: 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE', 1: 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE', } CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0 CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE = 1 CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN' CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN__enumvalues = { 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE', 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE', } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE = 0 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE = 1 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE' CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE__enumvalues = { 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB', 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601', 2: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709', 3: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS', 4: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS', 5: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB', 6: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB', 7: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS', } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB = 0 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601 = 1 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709 = 2 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS = 3 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS = 4 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB = 5 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB = 6 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS = 7 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE' CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE__enumvalues = { 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE', 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE', } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE = 0 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE = 1 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT' CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT__enumvalues = { 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC', 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC', 2: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC', 3: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED', } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC = 0 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC = 1 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC = 2 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED = 3 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK' MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = { 0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', 1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', } MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK' MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK__enumvalues = { 0: 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE', 1: 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE', } MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE = 0 MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE = 1 MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK' MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK__enumvalues = { 0: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE', 1: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE', } MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 1 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE' MASTER_UPDATE_MODE_MASTER_UPDATE_MODE__enumvalues = { 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN', 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA', 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA', 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE', } MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 1 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 2 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 3 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE = ctypes.c_uint32 # enum # values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE' MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = { 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN', 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD', 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', } MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN = 1 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD = 2 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE' CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE__enumvalues = { 0: 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE', 1: 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG', 2: 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL', } CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE = 0 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG = 1 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL = 2 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR' CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR__enumvalues = { 0: 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE', 1: 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE', } CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0 CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 1 CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR' CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__enumvalues = { 0: 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE', 1: 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE', } CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0 CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 1 CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR' CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR__enumvalues = { 0: 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE', 1: 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE', } CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0 CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE = 1 CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY' CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = { 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE' CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = { 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR' CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR__enumvalues = { 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE', 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE', } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE' CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = { 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR' CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR__enumvalues = { 0: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', 1: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE', } CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE' CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = { 0: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', 1: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', } CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE' CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = { 0: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', 1: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', } CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR' CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR__enumvalues = { 0: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', 1: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE', } CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE' CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = { 0: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', 1: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', } CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE' CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = { 0: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', 1: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', } CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_EN' CRTC_CRC_CNTL_CRTC_CRC_EN__enumvalues = { 0: 'CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE', 1: 'CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE', } CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0 CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 1 CRTC_CRC_CNTL_CRTC_CRC_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN' CRTC_CRC_CNTL_CRTC_CRC_CONT_EN__enumvalues = { 0: 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE', 1: 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE', } CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0 CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 1 CRTC_CRC_CNTL_CRTC_CRC_CONT_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE' CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE__enumvalues = { 0: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT', 1: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT', 2: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES', 3: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS', } CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 1 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 2 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 3 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE' CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE__enumvalues = { 0: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP', 1: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM', 2: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM', 3: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD', } CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 1 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 3 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS' CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = { 0: 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', 1: 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', } CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0 CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1 CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT' CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT__enumvalues = { 0: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB', 1: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B', 2: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB', 3: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B', 4: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB', 5: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B', 6: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB', 7: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B', } CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 1 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 2 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 3 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 4 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 5 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 6 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 7 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT = ctypes.c_uint32 # enum # values for enumeration 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT' CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT__enumvalues = { 0: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB', 1: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B', 2: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB', 3: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B', 4: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB', 5: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B', 6: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB', 7: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B', } CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 1 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 2 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 3 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 4 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 5 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 6 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 7 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE' CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE', 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT', 2: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS', 3: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED', } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE = 0 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT = 1 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 2 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED = 3 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE' CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE', } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 1 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE' CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE', } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 1 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW' CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel', 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel', 2: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel', 3: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel', } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 1 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 2 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 3 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE' CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE', } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 1 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE' CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE', } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 1 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY' CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE', } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 1 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY' CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE', } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 1 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE' CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE', } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 1 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE' CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE', } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 1 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR' CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE', } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 1 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE' CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE', } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 1 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT' CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME', 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME', 2: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME', 3: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME', 4: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME', 5: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME', 6: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME', 7: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME', } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 1 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 2 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 3 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 4 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 5 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 6 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 7 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE' CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE', } CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 1 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR' CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE', } CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE = 1 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE' CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE', } CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE = 1 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE' CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE', } CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 1 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR' CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE', } CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 1 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE' CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__enumvalues = { 0: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE', 1: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE', } CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 1 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE' CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE__enumvalues = { 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE', 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE', } CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE = 0 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE = 1 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR' CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR__enumvalues = { 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE', 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE', } CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE = 1 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE' CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE__enumvalues = { 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE', 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE', } CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE = 0 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE = 1 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE' CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE__enumvalues = { 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE', 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE', } CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE = 0 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE = 1 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE' CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = { 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF', 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON', } CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN' CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN__enumvalues = { 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE', 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE', } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE = 0 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE = 1 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN = ctypes.c_uint32 # enum # values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB' CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB__enumvalues = { 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE', 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE', } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE = 0 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE = 1 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum # values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE' CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = { 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', 2: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', 3: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR' CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = { 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum # values for enumeration 'CRTC_V_SYNC_A_POL' CRTC_V_SYNC_A_POL__enumvalues = { 0: 'CRTC_V_SYNC_A_POL_HIGH', 1: 'CRTC_V_SYNC_A_POL_LOW', } CRTC_V_SYNC_A_POL_HIGH = 0 CRTC_V_SYNC_A_POL_LOW = 1 CRTC_V_SYNC_A_POL = ctypes.c_uint32 # enum # values for enumeration 'CRTC_H_SYNC_A_POL' CRTC_H_SYNC_A_POL__enumvalues = { 0: 'CRTC_H_SYNC_A_POL_HIGH', 1: 'CRTC_H_SYNC_A_POL_LOW', } CRTC_H_SYNC_A_POL_HIGH = 0 CRTC_H_SYNC_A_POL_LOW = 1 CRTC_H_SYNC_A_POL = ctypes.c_uint32 # enum # values for enumeration 'CRTC_HORZ_REPETITION_COUNT' CRTC_HORZ_REPETITION_COUNT__enumvalues = { 0: 'CRTC_HORZ_REPETITION_COUNT_0', 1: 'CRTC_HORZ_REPETITION_COUNT_1', 2: 'CRTC_HORZ_REPETITION_COUNT_2', 3: 'CRTC_HORZ_REPETITION_COUNT_3', 4: 'CRTC_HORZ_REPETITION_COUNT_4', 5: 'CRTC_HORZ_REPETITION_COUNT_5', 6: 'CRTC_HORZ_REPETITION_COUNT_6', 7: 'CRTC_HORZ_REPETITION_COUNT_7', 8: 'CRTC_HORZ_REPETITION_COUNT_8', 9: 'CRTC_HORZ_REPETITION_COUNT_9', 10: 'CRTC_HORZ_REPETITION_COUNT_10', 11: 'CRTC_HORZ_REPETITION_COUNT_11', 12: 'CRTC_HORZ_REPETITION_COUNT_12', 13: 'CRTC_HORZ_REPETITION_COUNT_13', 14: 'CRTC_HORZ_REPETITION_COUNT_14', 15: 'CRTC_HORZ_REPETITION_COUNT_15', } CRTC_HORZ_REPETITION_COUNT_0 = 0 CRTC_HORZ_REPETITION_COUNT_1 = 1 CRTC_HORZ_REPETITION_COUNT_2 = 2 CRTC_HORZ_REPETITION_COUNT_3 = 3 CRTC_HORZ_REPETITION_COUNT_4 = 4 CRTC_HORZ_REPETITION_COUNT_5 = 5 CRTC_HORZ_REPETITION_COUNT_6 = 6 CRTC_HORZ_REPETITION_COUNT_7 = 7 CRTC_HORZ_REPETITION_COUNT_8 = 8 CRTC_HORZ_REPETITION_COUNT_9 = 9 CRTC_HORZ_REPETITION_COUNT_10 = 10 CRTC_HORZ_REPETITION_COUNT_11 = 11 CRTC_HORZ_REPETITION_COUNT_12 = 12 CRTC_HORZ_REPETITION_COUNT_13 = 13 CRTC_HORZ_REPETITION_COUNT_14 = 14 CRTC_HORZ_REPETITION_COUNT_15 = 15 CRTC_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum # values for enumeration 'CRTC_DRR_MODE_DBUF_UPDATE_MODE' CRTC_DRR_MODE_DBUF_UPDATE_MODE__enumvalues = { 0: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE', 1: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL', 2: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF', 3: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF', } CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE = 0 CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL = 1 CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF = 2 CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF = 3 CRTC_DRR_MODE_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum # values for enumeration 'FMT_CONTROL_PIXEL_ENCODING' FMT_CONTROL_PIXEL_ENCODING__enumvalues = { 0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', 1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', 2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', 3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', } FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0 FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1 FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2 FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3 FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum # values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE' FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = { 0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', 1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', 2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', 3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', } FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0 FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1 FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2 FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3 FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum # values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER' FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = { 0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', 1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', } FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0 FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1 FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum # values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS' FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = { 0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', 1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', } FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum # values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE' FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = { 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', } FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum # values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH' FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = { 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', 2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', } FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum # values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH' FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = { 0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', 1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', 2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', } FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum # values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH' FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = { 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', 2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', } FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum # values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL' FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = { 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', } FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum # values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL' FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = { 0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', 1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', 2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', 3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', } FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3 FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum # values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL' FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = { 0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', 1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', 2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', 3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', } FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3 FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum # values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL' FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = { 0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', 1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', 2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', 3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', } FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3 FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum # values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT' FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT__enumvalues = { 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN', 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN', } FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN = 0 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN = 1 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT = ctypes.c_uint32 # enum # values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0' FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = { 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', } FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum # values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT' FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = { 0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', 1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', 2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', 3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', 4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', 5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', 6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', 7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', } FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0 FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1 FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2 FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6 FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7 FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'FMT_CRC_CNTL_CONT_EN' FMT_CRC_CNTL_CONT_EN__enumvalues = { 0: 'FMT_CRC_CNTL_CONT_EN_ONE_SHOT', 1: 'FMT_CRC_CNTL_CONT_EN_CONT', } FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0 FMT_CRC_CNTL_CONT_EN_CONT = 1 FMT_CRC_CNTL_CONT_EN = ctypes.c_uint32 # enum # values for enumeration 'FMT_CRC_CNTL_INCLUDE_OVERSCAN' FMT_CRC_CNTL_INCLUDE_OVERSCAN__enumvalues = { 0: 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE', 1: 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE', } FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0 FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 1 FMT_CRC_CNTL_INCLUDE_OVERSCAN = ctypes.c_uint32 # enum # values for enumeration 'FMT_CRC_CNTL_ONLY_BLANKB' FMT_CRC_CNTL_ONLY_BLANKB__enumvalues = { 0: 'FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD', 1: 'FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK', } FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0 FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 1 FMT_CRC_CNTL_ONLY_BLANKB = ctypes.c_uint32 # enum # values for enumeration 'FMT_CRC_CNTL_PSR_MODE_ENABLE' FMT_CRC_CNTL_PSR_MODE_ENABLE__enumvalues = { 0: 'FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL', 1: 'FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC', } FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0 FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 1 FMT_CRC_CNTL_PSR_MODE_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'FMT_CRC_CNTL_INTERLACE_MODE' FMT_CRC_CNTL_INTERLACE_MODE__enumvalues = { 0: 'FMT_CRC_CNTL_INTERLACE_MODE_TOP', 1: 'FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM', 2: 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM', 3: 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH', } FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0 FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 1 FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 2 FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 3 FMT_CRC_CNTL_INTERLACE_MODE = ctypes.c_uint32 # enum # values for enumeration 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE' FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE__enumvalues = { 0: 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL', 1: 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN', } FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0 FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 1 FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT' FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT__enumvalues = { 0: 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN', 1: 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD', } FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0 FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 1 FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT = ctypes.c_uint32 # enum # values for enumeration 'FMT_DEBUG_CNTL_COLOR_SELECT' FMT_DEBUG_CNTL_COLOR_SELECT__enumvalues = { 0: 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', 1: 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', 2: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', 3: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', } FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0 FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 1 FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 2 FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 3 FMT_DEBUG_CNTL_COLOR_SELECT = ctypes.c_uint32 # enum # values for enumeration 'FMT_SPATIAL_DITHER_MODE' FMT_SPATIAL_DITHER_MODE__enumvalues = { 0: 'FMT_SPATIAL_DITHER_MODE_0', 1: 'FMT_SPATIAL_DITHER_MODE_1', 2: 'FMT_SPATIAL_DITHER_MODE_2', 3: 'FMT_SPATIAL_DITHER_MODE_3', } FMT_SPATIAL_DITHER_MODE_0 = 0 FMT_SPATIAL_DITHER_MODE_1 = 1 FMT_SPATIAL_DITHER_MODE_2 = 2 FMT_SPATIAL_DITHER_MODE_3 = 3 FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum # values for enumeration 'FMT_STEREOSYNC_OVR_POL' FMT_STEREOSYNC_OVR_POL__enumvalues = { 0: 'FMT_STEREOSYNC_OVR_POL_INVERTED', 1: 'FMT_STEREOSYNC_OVR_POL_NOT_INVERTED', } FMT_STEREOSYNC_OVR_POL_INVERTED = 0 FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 1 FMT_STEREOSYNC_OVR_POL = ctypes.c_uint32 # enum # values for enumeration 'FMT_DYNAMIC_EXP_MODE' FMT_DYNAMIC_EXP_MODE__enumvalues = { 0: 'FMT_DYNAMIC_EXP_MODE_10to12', 1: 'FMT_DYNAMIC_EXP_MODE_8to12', } FMT_DYNAMIC_EXP_MODE_10to12 = 0 FMT_DYNAMIC_EXP_MODE_8to12 = 1 FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum # values for enumeration 'HPD_INT_CONTROL_ACK' HPD_INT_CONTROL_ACK__enumvalues = { 0: 'HPD_INT_CONTROL_ACK_0', 1: 'HPD_INT_CONTROL_ACK_1', } HPD_INT_CONTROL_ACK_0 = 0 HPD_INT_CONTROL_ACK_1 = 1 HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum # values for enumeration 'HPD_INT_CONTROL_POLARITY' HPD_INT_CONTROL_POLARITY__enumvalues = { 0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 1: 'HPD_INT_CONTROL_GEN_INT_ON_CON', } HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0 HPD_INT_CONTROL_GEN_INT_ON_CON = 1 HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum # values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK' HPD_INT_CONTROL_RX_INT_ACK__enumvalues = { 0: 'HPD_INT_CONTROL_RX_INT_ACK_0', 1: 'HPD_INT_CONTROL_RX_INT_ACK_1', } HPD_INT_CONTROL_RX_INT_ACK_0 = 0 HPD_INT_CONTROL_RX_INT_ACK_1 = 1 HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum # values for enumeration 'LB_DATA_FORMAT_PIXEL_DEPTH' LB_DATA_FORMAT_PIXEL_DEPTH__enumvalues = { 0: 'LB_DATA_FORMAT_PIXEL_DEPTH_30BPP', 1: 'LB_DATA_FORMAT_PIXEL_DEPTH_24BPP', 2: 'LB_DATA_FORMAT_PIXEL_DEPTH_18BPP', 3: 'LB_DATA_FORMAT_PIXEL_DEPTH_36BPP', } LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0 LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 1 LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 2 LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 3 LB_DATA_FORMAT_PIXEL_DEPTH = ctypes.c_uint32 # enum # values for enumeration 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE' LB_DATA_FORMAT_PIXEL_EXPAN_MODE__enumvalues = { 0: 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION', 1: 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION', } LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0 LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 1 LB_DATA_FORMAT_PIXEL_EXPAN_MODE = ctypes.c_uint32 # enum # values for enumeration 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE' LB_DATA_FORMAT_PIXEL_REDUCE_MODE__enumvalues = { 0: 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION', 1: 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING', } LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0 LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 1 LB_DATA_FORMAT_PIXEL_REDUCE_MODE = ctypes.c_uint32 # enum # values for enumeration 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH' LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH__enumvalues = { 0: 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP', 1: 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP', } LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0 LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 1 LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH = ctypes.c_uint32 # enum # values for enumeration 'LB_DATA_FORMAT_INTERLEAVE_EN' LB_DATA_FORMAT_INTERLEAVE_EN__enumvalues = { 0: 'LB_DATA_FORMAT_INTERLEAVE_DISABLE', 1: 'LB_DATA_FORMAT_INTERLEAVE_ENABLE', } LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0 LB_DATA_FORMAT_INTERLEAVE_ENABLE = 1 LB_DATA_FORMAT_INTERLEAVE_EN = ctypes.c_uint32 # enum # values for enumeration 'LB_DATA_FORMAT_REQUEST_MODE' LB_DATA_FORMAT_REQUEST_MODE__enumvalues = { 0: 'LB_DATA_FORMAT_REQUEST_MODE_NORMAL', 1: 'LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE', } LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0 LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 1 LB_DATA_FORMAT_REQUEST_MODE = ctypes.c_uint32 # enum # values for enumeration 'LB_DATA_FORMAT_ALPHA_EN' LB_DATA_FORMAT_ALPHA_EN__enumvalues = { 0: 'LB_DATA_FORMAT_ALPHA_DISABLE', 1: 'LB_DATA_FORMAT_ALPHA_ENABLE', } LB_DATA_FORMAT_ALPHA_DISABLE = 0 LB_DATA_FORMAT_ALPHA_ENABLE = 1 LB_DATA_FORMAT_ALPHA_EN = ctypes.c_uint32 # enum # values for enumeration 'LB_VLINE_START_END_VLINE_INV' LB_VLINE_START_END_VLINE_INV__enumvalues = { 0: 'LB_VLINE_START_END_VLINE_NORMAL', 1: 'LB_VLINE_START_END_VLINE_INVERSE', } LB_VLINE_START_END_VLINE_NORMAL = 0 LB_VLINE_START_END_VLINE_INVERSE = 1 LB_VLINE_START_END_VLINE_INV = ctypes.c_uint32 # enum # values for enumeration 'LB_VLINE2_START_END_VLINE2_INV' LB_VLINE2_START_END_VLINE2_INV__enumvalues = { 0: 'LB_VLINE2_START_END_VLINE2_NORMAL', 1: 'LB_VLINE2_START_END_VLINE2_INVERSE', } LB_VLINE2_START_END_VLINE2_NORMAL = 0 LB_VLINE2_START_END_VLINE2_INVERSE = 1 LB_VLINE2_START_END_VLINE2_INV = ctypes.c_uint32 # enum # values for enumeration 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK' LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK__enumvalues = { 0: 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE', 1: 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE', } LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0 LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 1 LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK = ctypes.c_uint32 # enum # values for enumeration 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK' LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK__enumvalues = { 0: 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE', 1: 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE', } LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0 LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 1 LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK = ctypes.c_uint32 # enum # values for enumeration 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK' LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK__enumvalues = { 0: 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE', 1: 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE', } LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0 LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 1 LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK = ctypes.c_uint32 # enum # values for enumeration 'LB_VLINE_STATUS_VLINE_ACK' LB_VLINE_STATUS_VLINE_ACK__enumvalues = { 0: 'LB_VLINE_STATUS_VLINE_NORMAL', 1: 'LB_VLINE_STATUS_VLINE_CLEAR', } LB_VLINE_STATUS_VLINE_NORMAL = 0 LB_VLINE_STATUS_VLINE_CLEAR = 1 LB_VLINE_STATUS_VLINE_ACK = ctypes.c_uint32 # enum # values for enumeration 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE' LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE__enumvalues = { 0: 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED', 1: 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED', } LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0 LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 1 LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'LB_VLINE2_STATUS_VLINE2_ACK' LB_VLINE2_STATUS_VLINE2_ACK__enumvalues = { 0: 'LB_VLINE2_STATUS_VLINE2_NORMAL', 1: 'LB_VLINE2_STATUS_VLINE2_CLEAR', } LB_VLINE2_STATUS_VLINE2_NORMAL = 0 LB_VLINE2_STATUS_VLINE2_CLEAR = 1 LB_VLINE2_STATUS_VLINE2_ACK = ctypes.c_uint32 # enum # values for enumeration 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE' LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE__enumvalues = { 0: 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED', 1: 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED', } LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED = 0 LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED = 1 LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'LB_VBLANK_STATUS_VBLANK_ACK' LB_VBLANK_STATUS_VBLANK_ACK__enumvalues = { 0: 'LB_VBLANK_STATUS_VBLANK_NORMAL', 1: 'LB_VBLANK_STATUS_VBLANK_CLEAR', } LB_VBLANK_STATUS_VBLANK_NORMAL = 0 LB_VBLANK_STATUS_VBLANK_CLEAR = 1 LB_VBLANK_STATUS_VBLANK_ACK = ctypes.c_uint32 # enum # values for enumeration 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE' LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE__enumvalues = { 0: 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED', 1: 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED', } LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED = 0 LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED = 1 LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL' LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL__enumvalues = { 0: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE', 1: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK', 2: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET', 3: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET', } LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK = 1 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET = 2 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET = 3 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL = ctypes.c_uint32 # enum # values for enumeration 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2' LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2__enumvalues = { 0: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK', 1: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC', } LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 1 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 = ctypes.c_uint32 # enum # values for enumeration 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION' LB_SYNC_RESET_SEL_LB_SYNC_DURATION__enumvalues = { 0: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS', 1: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS', 2: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS', 3: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS', } LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 1 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 2 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 3 LB_SYNC_RESET_SEL_LB_SYNC_DURATION = ctypes.c_uint32 # enum # values for enumeration 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN' LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN__enumvalues = { 0: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE', 1: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE', } LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 1 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN = ctypes.c_uint32 # enum # values for enumeration 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN' LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN__enumvalues = { 0: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE', 1: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE', } LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 1 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN = ctypes.c_uint32 # enum # values for enumeration 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK' LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK__enumvalues = { 0: 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL', 1: 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET', } LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0 LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 1 LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK = ctypes.c_uint32 # enum # values for enumeration 'LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK' LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK__enumvalues = { 0: 'LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL', 1: 'LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET', } LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0 LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 1 LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK = ctypes.c_uint32 # enum # values for enumeration 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE' LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE__enumvalues = { 2: 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP', 3: 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP', } LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 2 LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP = 3 LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE = ctypes.c_uint32 # enum # values for enumeration 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET' LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET__enumvalues = { 0: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL', 1: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE', } LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE = 1 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET = ctypes.c_uint32 # enum # values for enumeration 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK' LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK__enumvalues = { 0: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0', 1: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1', } LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 1 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK = ctypes.c_uint32 # enum # values for enumeration 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE' LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE__enumvalues = { 0: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT', 1: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG', 2: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE', } LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT = 0 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG = 1 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE = 2 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE = ctypes.c_uint32 # enum # values for enumeration 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE' LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE__enumvalues = { 0: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE', 1: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN', } LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE = 0 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 1 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE' LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE__enumvalues = { 1: 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER', 2: 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE', } ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER = 1 ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE = 2 LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE = ctypes.c_uint32 # enum # values for enumeration 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL' LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL__enumvalues = { 0: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0', 1: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1', } LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 1 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL = ctypes.c_uint32 # enum # values for enumeration 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE' LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__enumvalues = { 0: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE', 1: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE', } LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE = 1 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE = ctypes.c_uint32 # enum # values for enumeration 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO' LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__enumvalues = { 0: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO', 1: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO', } LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO = 1 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO = ctypes.c_uint32 # enum # values for enumeration 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN' LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN__enumvalues = { 0: 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0', 1: 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1', } LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0 LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 1 LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum # values for enumeration 'HDMI_KEEPOUT_MODE' HDMI_KEEPOUT_MODE__enumvalues = { 0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', 1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', } HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0 HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1 HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum # values for enumeration 'HDMI_DATA_SCRAMBLE_EN' HDMI_DATA_SCRAMBLE_EN__enumvalues = { 0: 'HDMI_DATA_SCRAMBLE_DISABLE', 1: 'HDMI_DATA_SCRAMBLE_ENABLE', } HDMI_DATA_SCRAMBLE_DISABLE = 0 HDMI_DATA_SCRAMBLE_ENABLE = 1 HDMI_DATA_SCRAMBLE_EN = ctypes.c_uint32 # enum # values for enumeration 'HDMI_CLOCK_CHANNEL_RATE' HDMI_CLOCK_CHANNEL_RATE__enumvalues = { 0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', 1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', } HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0 HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1 HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum # values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED' HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = { 0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', } HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0 HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1 HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum # values for enumeration 'HDMI_PACKET_GEN_VERSION' HDMI_PACKET_GEN_VERSION__enumvalues = { 0: 'HDMI_PACKET_GEN_VERSION_OLD', 1: 'HDMI_PACKET_GEN_VERSION_NEW', } HDMI_PACKET_GEN_VERSION_OLD = 0 HDMI_PACKET_GEN_VERSION_NEW = 1 HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum # values for enumeration 'HDMI_ERROR_ACK' HDMI_ERROR_ACK__enumvalues = { 0: 'HDMI_ERROR_ACK_INT', 1: 'HDMI_ERROR_NOT_ACK', } HDMI_ERROR_ACK_INT = 0 HDMI_ERROR_NOT_ACK = 1 HDMI_ERROR_ACK = ctypes.c_uint32 # enum # values for enumeration 'HDMI_ERROR_MASK' HDMI_ERROR_MASK__enumvalues = { 0: 'HDMI_ERROR_MASK_INT', 1: 'HDMI_ERROR_NOT_MASK', } HDMI_ERROR_MASK_INT = 0 HDMI_ERROR_NOT_MASK = 1 HDMI_ERROR_MASK = ctypes.c_uint32 # enum # values for enumeration 'HDMI_DEEP_COLOR_DEPTH' HDMI_DEEP_COLOR_DEPTH__enumvalues = { 0: 'HDMI_DEEP_COLOR_DEPTH_24BPP', 1: 'HDMI_DEEP_COLOR_DEPTH_30BPP', 2: 'HDMI_DEEP_COLOR_DEPTH_36BPP', 3: 'HDMI_DEEP_COLOR_DEPTH_RESERVED', } HDMI_DEEP_COLOR_DEPTH_24BPP = 0 HDMI_DEEP_COLOR_DEPTH_30BPP = 1 HDMI_DEEP_COLOR_DEPTH_36BPP = 2 HDMI_DEEP_COLOR_DEPTH_RESERVED = 3 HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum # values for enumeration 'HDMI_AUDIO_DELAY_EN' HDMI_AUDIO_DELAY_EN__enumvalues = { 0: 'HDMI_AUDIO_DELAY_DISABLE', 1: 'HDMI_AUDIO_DELAY_58CLK', 2: 'HDMI_AUDIO_DELAY_56CLK', 3: 'HDMI_AUDIO_DELAY_RESERVED', } HDMI_AUDIO_DELAY_DISABLE = 0 HDMI_AUDIO_DELAY_58CLK = 1 HDMI_AUDIO_DELAY_56CLK = 2 HDMI_AUDIO_DELAY_RESERVED = 3 HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum # values for enumeration 'HDMI_AUDIO_SEND_MAX_PACKETS' HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = { 0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', 1: 'HDMI_SEND_MAX_AUDIO_PACKETS', } HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0 HDMI_SEND_MAX_AUDIO_PACKETS = 1 HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum # values for enumeration 'HDMI_ACR_SEND' HDMI_ACR_SEND__enumvalues = { 0: 'HDMI_ACR_NOT_SEND', 1: 'HDMI_ACR_PKT_SEND', } HDMI_ACR_NOT_SEND = 0 HDMI_ACR_PKT_SEND = 1 HDMI_ACR_SEND = ctypes.c_uint32 # enum # values for enumeration 'HDMI_ACR_CONT' HDMI_ACR_CONT__enumvalues = { 0: 'HDMI_ACR_CONT_DISABLE', 1: 'HDMI_ACR_CONT_ENABLE', } HDMI_ACR_CONT_DISABLE = 0 HDMI_ACR_CONT_ENABLE = 1 HDMI_ACR_CONT = ctypes.c_uint32 # enum # values for enumeration 'HDMI_ACR_SELECT' HDMI_ACR_SELECT__enumvalues = { 0: 'HDMI_ACR_SELECT_HW', 1: 'HDMI_ACR_SELECT_32K', 2: 'HDMI_ACR_SELECT_44K', 3: 'HDMI_ACR_SELECT_48K', } HDMI_ACR_SELECT_HW = 0 HDMI_ACR_SELECT_32K = 1 HDMI_ACR_SELECT_44K = 2 HDMI_ACR_SELECT_48K = 3 HDMI_ACR_SELECT = ctypes.c_uint32 # enum # values for enumeration 'HDMI_ACR_SOURCE' HDMI_ACR_SOURCE__enumvalues = { 0: 'HDMI_ACR_SOURCE_HW', 1: 'HDMI_ACR_SOURCE_SW', } HDMI_ACR_SOURCE_HW = 0 HDMI_ACR_SOURCE_SW = 1 HDMI_ACR_SOURCE = ctypes.c_uint32 # enum # values for enumeration 'HDMI_ACR_N_MULTIPLE' HDMI_ACR_N_MULTIPLE__enumvalues = { 0: 'HDMI_ACR_0_MULTIPLE_RESERVED', 1: 'HDMI_ACR_1_MULTIPLE', 2: 'HDMI_ACR_2_MULTIPLE', 3: 'HDMI_ACR_3_MULTIPLE_RESERVED', 4: 'HDMI_ACR_4_MULTIPLE', 5: 'HDMI_ACR_5_MULTIPLE_RESERVED', 6: 'HDMI_ACR_6_MULTIPLE_RESERVED', 7: 'HDMI_ACR_7_MULTIPLE_RESERVED', } HDMI_ACR_0_MULTIPLE_RESERVED = 0 HDMI_ACR_1_MULTIPLE = 1 HDMI_ACR_2_MULTIPLE = 2 HDMI_ACR_3_MULTIPLE_RESERVED = 3 HDMI_ACR_4_MULTIPLE = 4 HDMI_ACR_5_MULTIPLE_RESERVED = 5 HDMI_ACR_6_MULTIPLE_RESERVED = 6 HDMI_ACR_7_MULTIPLE_RESERVED = 7 HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum # values for enumeration 'HDMI_ACR_AUDIO_PRIORITY' HDMI_ACR_AUDIO_PRIORITY__enumvalues = { 0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', 1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', } HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum # values for enumeration 'HDMI_NULL_SEND' HDMI_NULL_SEND__enumvalues = { 0: 'HDMI_NULL_NOT_SEND', 1: 'HDMI_NULL_PKT_SEND', } HDMI_NULL_NOT_SEND = 0 HDMI_NULL_PKT_SEND = 1 HDMI_NULL_SEND = ctypes.c_uint32 # enum # values for enumeration 'HDMI_GC_SEND' HDMI_GC_SEND__enumvalues = { 0: 'HDMI_GC_NOT_SEND', 1: 'HDMI_GC_PKT_SEND', } HDMI_GC_NOT_SEND = 0 HDMI_GC_PKT_SEND = 1 HDMI_GC_SEND = ctypes.c_uint32 # enum # values for enumeration 'HDMI_GC_CONT' HDMI_GC_CONT__enumvalues = { 0: 'HDMI_GC_CONT_DISABLE', 1: 'HDMI_GC_CONT_ENABLE', } HDMI_GC_CONT_DISABLE = 0 HDMI_GC_CONT_ENABLE = 1 HDMI_GC_CONT = ctypes.c_uint32 # enum # values for enumeration 'HDMI_ISRC_SEND' HDMI_ISRC_SEND__enumvalues = { 0: 'HDMI_ISRC_NOT_SEND', 1: 'HDMI_ISRC_PKT_SEND', } HDMI_ISRC_NOT_SEND = 0 HDMI_ISRC_PKT_SEND = 1 HDMI_ISRC_SEND = ctypes.c_uint32 # enum # values for enumeration 'HDMI_ISRC_CONT' HDMI_ISRC_CONT__enumvalues = { 0: 'HDMI_ISRC_CONT_DISABLE', 1: 'HDMI_ISRC_CONT_ENABLE', } HDMI_ISRC_CONT_DISABLE = 0 HDMI_ISRC_CONT_ENABLE = 1 HDMI_ISRC_CONT = ctypes.c_uint32 # enum # values for enumeration 'HDMI_AVI_INFO_SEND' HDMI_AVI_INFO_SEND__enumvalues = { 0: 'HDMI_AVI_INFO_NOT_SEND', 1: 'HDMI_AVI_INFO_PKT_SEND', } HDMI_AVI_INFO_NOT_SEND = 0 HDMI_AVI_INFO_PKT_SEND = 1 HDMI_AVI_INFO_SEND = ctypes.c_uint32 # enum # values for enumeration 'HDMI_AVI_INFO_CONT' HDMI_AVI_INFO_CONT__enumvalues = { 0: 'HDMI_AVI_INFO_CONT_DISABLE', 1: 'HDMI_AVI_INFO_CONT_ENABLE', } HDMI_AVI_INFO_CONT_DISABLE = 0 HDMI_AVI_INFO_CONT_ENABLE = 1 HDMI_AVI_INFO_CONT = ctypes.c_uint32 # enum # values for enumeration 'HDMI_AUDIO_INFO_SEND' HDMI_AUDIO_INFO_SEND__enumvalues = { 0: 'HDMI_AUDIO_INFO_NOT_SEND', 1: 'HDMI_AUDIO_INFO_PKT_SEND', } HDMI_AUDIO_INFO_NOT_SEND = 0 HDMI_AUDIO_INFO_PKT_SEND = 1 HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum # values for enumeration 'HDMI_AUDIO_INFO_CONT' HDMI_AUDIO_INFO_CONT__enumvalues = { 0: 'HDMI_AUDIO_INFO_CONT_DISABLE', 1: 'HDMI_AUDIO_INFO_CONT_ENABLE', } HDMI_AUDIO_INFO_CONT_DISABLE = 0 HDMI_AUDIO_INFO_CONT_ENABLE = 1 HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum # values for enumeration 'HDMI_MPEG_INFO_SEND' HDMI_MPEG_INFO_SEND__enumvalues = { 0: 'HDMI_MPEG_INFO_NOT_SEND', 1: 'HDMI_MPEG_INFO_PKT_SEND', } HDMI_MPEG_INFO_NOT_SEND = 0 HDMI_MPEG_INFO_PKT_SEND = 1 HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum # values for enumeration 'HDMI_MPEG_INFO_CONT' HDMI_MPEG_INFO_CONT__enumvalues = { 0: 'HDMI_MPEG_INFO_CONT_DISABLE', 1: 'HDMI_MPEG_INFO_CONT_ENABLE', } HDMI_MPEG_INFO_CONT_DISABLE = 0 HDMI_MPEG_INFO_CONT_ENABLE = 1 HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum # values for enumeration 'HDMI_GENERIC0_SEND' HDMI_GENERIC0_SEND__enumvalues = { 0: 'HDMI_GENERIC0_NOT_SEND', 1: 'HDMI_GENERIC0_PKT_SEND', } HDMI_GENERIC0_NOT_SEND = 0 HDMI_GENERIC0_PKT_SEND = 1 HDMI_GENERIC0_SEND = ctypes.c_uint32 # enum # values for enumeration 'HDMI_GENERIC0_CONT' HDMI_GENERIC0_CONT__enumvalues = { 0: 'HDMI_GENERIC0_CONT_DISABLE', 1: 'HDMI_GENERIC0_CONT_ENABLE', } HDMI_GENERIC0_CONT_DISABLE = 0 HDMI_GENERIC0_CONT_ENABLE = 1 HDMI_GENERIC0_CONT = ctypes.c_uint32 # enum # values for enumeration 'HDMI_GENERIC1_SEND' HDMI_GENERIC1_SEND__enumvalues = { 0: 'HDMI_GENERIC1_NOT_SEND', 1: 'HDMI_GENERIC1_PKT_SEND', } HDMI_GENERIC1_NOT_SEND = 0 HDMI_GENERIC1_PKT_SEND = 1 HDMI_GENERIC1_SEND = ctypes.c_uint32 # enum # values for enumeration 'HDMI_GENERIC1_CONT' HDMI_GENERIC1_CONT__enumvalues = { 0: 'HDMI_GENERIC1_CONT_DISABLE', 1: 'HDMI_GENERIC1_CONT_ENABLE', } HDMI_GENERIC1_CONT_DISABLE = 0 HDMI_GENERIC1_CONT_ENABLE = 1 HDMI_GENERIC1_CONT = ctypes.c_uint32 # enum # values for enumeration 'HDMI_GC_AVMUTE_CONT' HDMI_GC_AVMUTE_CONT__enumvalues = { 0: 'HDMI_GC_AVMUTE_CONT_DISABLE', 1: 'HDMI_GC_AVMUTE_CONT_ENABLE', } HDMI_GC_AVMUTE_CONT_DISABLE = 0 HDMI_GC_AVMUTE_CONT_ENABLE = 1 HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum # values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE' HDMI_PACKING_PHASE_OVERRIDE__enumvalues = { 0: 'HDMI_PACKING_PHASE_SET_BY_HW', 1: 'HDMI_PACKING_PHASE_SET_BY_SW', } HDMI_PACKING_PHASE_SET_BY_HW = 0 HDMI_PACKING_PHASE_SET_BY_SW = 1 HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum # values for enumeration 'HDMI_GENERIC2_SEND' HDMI_GENERIC2_SEND__enumvalues = { 0: 'HDMI_GENERIC2_NOT_SEND', 1: 'HDMI_GENERIC2_PKT_SEND', } HDMI_GENERIC2_NOT_SEND = 0 HDMI_GENERIC2_PKT_SEND = 1 HDMI_GENERIC2_SEND = ctypes.c_uint32 # enum # values for enumeration 'HDMI_GENERIC2_CONT' HDMI_GENERIC2_CONT__enumvalues = { 0: 'HDMI_GENERIC2_CONT_DISABLE', 1: 'HDMI_GENERIC2_CONT_ENABLE', } HDMI_GENERIC2_CONT_DISABLE = 0 HDMI_GENERIC2_CONT_ENABLE = 1 HDMI_GENERIC2_CONT = ctypes.c_uint32 # enum # values for enumeration 'HDMI_GENERIC3_SEND' HDMI_GENERIC3_SEND__enumvalues = { 0: 'HDMI_GENERIC3_NOT_SEND', 1: 'HDMI_GENERIC3_PKT_SEND', } HDMI_GENERIC3_NOT_SEND = 0 HDMI_GENERIC3_PKT_SEND = 1 HDMI_GENERIC3_SEND = ctypes.c_uint32 # enum # values for enumeration 'HDMI_GENERIC3_CONT' HDMI_GENERIC3_CONT__enumvalues = { 0: 'HDMI_GENERIC3_CONT_DISABLE', 1: 'HDMI_GENERIC3_CONT_ENABLE', } HDMI_GENERIC3_CONT_DISABLE = 0 HDMI_GENERIC3_CONT_ENABLE = 1 HDMI_GENERIC3_CONT = ctypes.c_uint32 # enum # values for enumeration 'TMDS_PIXEL_ENCODING' TMDS_PIXEL_ENCODING__enumvalues = { 0: 'TMDS_PIXEL_ENCODING_444_OR_420', 1: 'TMDS_PIXEL_ENCODING_422', } TMDS_PIXEL_ENCODING_444_OR_420 = 0 TMDS_PIXEL_ENCODING_422 = 1 TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum # values for enumeration 'TMDS_COLOR_FORMAT' TMDS_COLOR_FORMAT__enumvalues = { 0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', 1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', 2: 'TMDS_COLOR_FORMAT_DUAL30BPP', 3: 'TMDS_COLOR_FORMAT_RESERVED', } TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0 TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1 TMDS_COLOR_FORMAT_DUAL30BPP = 2 TMDS_COLOR_FORMAT_RESERVED = 3 TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG' TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = { 0: 'TMDS_STEREOSYNC_CTL0', 1: 'TMDS_STEREOSYNC_CTL1', 2: 'TMDS_STEREOSYNC_CTL2', 3: 'TMDS_STEREOSYNC_CTL3', } TMDS_STEREOSYNC_CTL0 = 0 TMDS_STEREOSYNC_CTL1 = 1 TMDS_STEREOSYNC_CTL2 = 2 TMDS_STEREOSYNC_CTL3 = 3 TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL0_DATA_SEL' TMDS_CTL0_DATA_SEL__enumvalues = { 0: 'TMDS_CTL0_DATA_SEL0_RESERVED', 1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 2: 'TMDS_CTL0_DATA_SEL2_VSYNC', 3: 'TMDS_CTL0_DATA_SEL3_RESERVED', 4: 'TMDS_CTL0_DATA_SEL4_HSYNC', 5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', 6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', 7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', } TMDS_CTL0_DATA_SEL0_RESERVED = 0 TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1 TMDS_CTL0_DATA_SEL2_VSYNC = 2 TMDS_CTL0_DATA_SEL3_RESERVED = 3 TMDS_CTL0_DATA_SEL4_HSYNC = 4 TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5 TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6 TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7 TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL0_DATA_INVERT' TMDS_CTL0_DATA_INVERT__enumvalues = { 0: 'TMDS_CTL0_DATA_NORMAL', 1: 'TMDS_CTL0_DATA_INVERT_EN', } TMDS_CTL0_DATA_NORMAL = 0 TMDS_CTL0_DATA_INVERT_EN = 1 TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL0_DATA_MODULATION' TMDS_CTL0_DATA_MODULATION__enumvalues = { 0: 'TMDS_CTL0_DATA_MODULATION_DISABLE', 1: 'TMDS_CTL0_DATA_MODULATION_BIT0', 2: 'TMDS_CTL0_DATA_MODULATION_BIT1', 3: 'TMDS_CTL0_DATA_MODULATION_BIT2', } TMDS_CTL0_DATA_MODULATION_DISABLE = 0 TMDS_CTL0_DATA_MODULATION_BIT0 = 1 TMDS_CTL0_DATA_MODULATION_BIT1 = 2 TMDS_CTL0_DATA_MODULATION_BIT2 = 3 TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN' TMDS_CTL0_PATTERN_OUT_EN__enumvalues = { 0: 'TMDS_CTL0_PATTERN_OUT_DISABLE', 1: 'TMDS_CTL0_PATTERN_OUT_ENABLE', } TMDS_CTL0_PATTERN_OUT_DISABLE = 0 TMDS_CTL0_PATTERN_OUT_ENABLE = 1 TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL1_DATA_SEL' TMDS_CTL1_DATA_SEL__enumvalues = { 0: 'TMDS_CTL1_DATA_SEL0_RESERVED', 1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 2: 'TMDS_CTL1_DATA_SEL2_VSYNC', 3: 'TMDS_CTL1_DATA_SEL3_RESERVED', 4: 'TMDS_CTL1_DATA_SEL4_HSYNC', 5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', 6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', 7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', } TMDS_CTL1_DATA_SEL0_RESERVED = 0 TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1 TMDS_CTL1_DATA_SEL2_VSYNC = 2 TMDS_CTL1_DATA_SEL3_RESERVED = 3 TMDS_CTL1_DATA_SEL4_HSYNC = 4 TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5 TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6 TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7 TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL1_DATA_INVERT' TMDS_CTL1_DATA_INVERT__enumvalues = { 0: 'TMDS_CTL1_DATA_NORMAL', 1: 'TMDS_CTL1_DATA_INVERT_EN', } TMDS_CTL1_DATA_NORMAL = 0 TMDS_CTL1_DATA_INVERT_EN = 1 TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL1_DATA_MODULATION' TMDS_CTL1_DATA_MODULATION__enumvalues = { 0: 'TMDS_CTL1_DATA_MODULATION_DISABLE', 1: 'TMDS_CTL1_DATA_MODULATION_BIT0', 2: 'TMDS_CTL1_DATA_MODULATION_BIT1', 3: 'TMDS_CTL1_DATA_MODULATION_BIT2', } TMDS_CTL1_DATA_MODULATION_DISABLE = 0 TMDS_CTL1_DATA_MODULATION_BIT0 = 1 TMDS_CTL1_DATA_MODULATION_BIT1 = 2 TMDS_CTL1_DATA_MODULATION_BIT2 = 3 TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN' TMDS_CTL1_PATTERN_OUT_EN__enumvalues = { 0: 'TMDS_CTL1_PATTERN_OUT_DISABLE', 1: 'TMDS_CTL1_PATTERN_OUT_ENABLE', } TMDS_CTL1_PATTERN_OUT_DISABLE = 0 TMDS_CTL1_PATTERN_OUT_ENABLE = 1 TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL2_DATA_SEL' TMDS_CTL2_DATA_SEL__enumvalues = { 0: 'TMDS_CTL2_DATA_SEL0_RESERVED', 1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 2: 'TMDS_CTL2_DATA_SEL2_VSYNC', 3: 'TMDS_CTL2_DATA_SEL3_RESERVED', 4: 'TMDS_CTL2_DATA_SEL4_HSYNC', 5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', 6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', 7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', } TMDS_CTL2_DATA_SEL0_RESERVED = 0 TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1 TMDS_CTL2_DATA_SEL2_VSYNC = 2 TMDS_CTL2_DATA_SEL3_RESERVED = 3 TMDS_CTL2_DATA_SEL4_HSYNC = 4 TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5 TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6 TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7 TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL2_DATA_INVERT' TMDS_CTL2_DATA_INVERT__enumvalues = { 0: 'TMDS_CTL2_DATA_NORMAL', 1: 'TMDS_CTL2_DATA_INVERT_EN', } TMDS_CTL2_DATA_NORMAL = 0 TMDS_CTL2_DATA_INVERT_EN = 1 TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL2_DATA_MODULATION' TMDS_CTL2_DATA_MODULATION__enumvalues = { 0: 'TMDS_CTL2_DATA_MODULATION_DISABLE', 1: 'TMDS_CTL2_DATA_MODULATION_BIT0', 2: 'TMDS_CTL2_DATA_MODULATION_BIT1', 3: 'TMDS_CTL2_DATA_MODULATION_BIT2', } TMDS_CTL2_DATA_MODULATION_DISABLE = 0 TMDS_CTL2_DATA_MODULATION_BIT0 = 1 TMDS_CTL2_DATA_MODULATION_BIT1 = 2 TMDS_CTL2_DATA_MODULATION_BIT2 = 3 TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN' TMDS_CTL2_PATTERN_OUT_EN__enumvalues = { 0: 'TMDS_CTL2_PATTERN_OUT_DISABLE', 1: 'TMDS_CTL2_PATTERN_OUT_ENABLE', } TMDS_CTL2_PATTERN_OUT_DISABLE = 0 TMDS_CTL2_PATTERN_OUT_ENABLE = 1 TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL3_DATA_INVERT' TMDS_CTL3_DATA_INVERT__enumvalues = { 0: 'TMDS_CTL3_DATA_NORMAL', 1: 'TMDS_CTL3_DATA_INVERT_EN', } TMDS_CTL3_DATA_NORMAL = 0 TMDS_CTL3_DATA_INVERT_EN = 1 TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL3_DATA_MODULATION' TMDS_CTL3_DATA_MODULATION__enumvalues = { 0: 'TMDS_CTL3_DATA_MODULATION_DISABLE', 1: 'TMDS_CTL3_DATA_MODULATION_BIT0', 2: 'TMDS_CTL3_DATA_MODULATION_BIT1', 3: 'TMDS_CTL3_DATA_MODULATION_BIT2', } TMDS_CTL3_DATA_MODULATION_DISABLE = 0 TMDS_CTL3_DATA_MODULATION_BIT0 = 1 TMDS_CTL3_DATA_MODULATION_BIT1 = 2 TMDS_CTL3_DATA_MODULATION_BIT2 = 3 TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN' TMDS_CTL3_PATTERN_OUT_EN__enumvalues = { 0: 'TMDS_CTL3_PATTERN_OUT_DISABLE', 1: 'TMDS_CTL3_PATTERN_OUT_ENABLE', } TMDS_CTL3_PATTERN_OUT_DISABLE = 0 TMDS_CTL3_PATTERN_OUT_ENABLE = 1 TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum # values for enumeration 'TMDS_CTL3_DATA_SEL' TMDS_CTL3_DATA_SEL__enumvalues = { 0: 'TMDS_CTL3_DATA_SEL0_RESERVED', 1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 2: 'TMDS_CTL3_DATA_SEL2_VSYNC', 3: 'TMDS_CTL3_DATA_SEL3_RESERVED', 4: 'TMDS_CTL3_DATA_SEL4_HSYNC', 5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', 6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', 7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', } TMDS_CTL3_DATA_SEL0_RESERVED = 0 TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1 TMDS_CTL3_DATA_SEL2_VSYNC = 2 TMDS_CTL3_DATA_SEL3_RESERVED = 3 TMDS_CTL3_DATA_SEL4_HSYNC = 4 TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5 TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6 TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7 TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum # values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT' DIG_FE_CNTL_SOURCE_SELECT__enumvalues = { 0: 'DIG_FE_SOURCE_FROM_FMT0', 1: 'DIG_FE_SOURCE_FROM_FMT1', 2: 'DIG_FE_SOURCE_FROM_FMT2', 3: 'DIG_FE_SOURCE_FROM_FMT3', 4: 'DIG_FE_SOURCE_FROM_FMT4', 5: 'DIG_FE_SOURCE_FROM_FMT5', } DIG_FE_SOURCE_FROM_FMT0 = 0 DIG_FE_SOURCE_FROM_FMT1 = 1 DIG_FE_SOURCE_FROM_FMT2 = 2 DIG_FE_SOURCE_FROM_FMT3 = 3 DIG_FE_SOURCE_FROM_FMT4 = 4 DIG_FE_SOURCE_FROM_FMT5 = 5 DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum # values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT' DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = { 0: 'DIG_FE_STEREOSYNC_FROM_FMT0', 1: 'DIG_FE_STEREOSYNC_FROM_FMT1', 2: 'DIG_FE_STEREOSYNC_FROM_FMT2', 3: 'DIG_FE_STEREOSYNC_FROM_FMT3', 4: 'DIG_FE_STEREOSYNC_FROM_FMT4', 5: 'DIG_FE_STEREOSYNC_FROM_FMT5', } DIG_FE_STEREOSYNC_FROM_FMT0 = 0 DIG_FE_STEREOSYNC_FROM_FMT1 = 1 DIG_FE_STEREOSYNC_FROM_FMT2 = 2 DIG_FE_STEREOSYNC_FROM_FMT3 = 3 DIG_FE_STEREOSYNC_FROM_FMT4 = 4 DIG_FE_STEREOSYNC_FROM_FMT5 = 5 DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum # values for enumeration 'DIG_FIFO_READ_CLOCK_SRC' DIG_FIFO_READ_CLOCK_SRC__enumvalues = { 0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', 1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', } DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0 DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1 DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum # values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL' DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = { 0: 'DIG_OUTPUT_CRC_ON_LINK0', 1: 'DIG_OUTPUT_CRC_ON_LINK1', } DIG_OUTPUT_CRC_ON_LINK0 = 0 DIG_OUTPUT_CRC_ON_LINK1 = 1 DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL' DIG_OUTPUT_CRC_DATA_SEL__enumvalues = { 0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME', 1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', 2: 'DIG_OUTPUT_CRC_FOR_VBI', 3: 'DIG_OUTPUT_CRC_FOR_AUDIO', } DIG_OUTPUT_CRC_FOR_FULLFRAME = 0 DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1 DIG_OUTPUT_CRC_FOR_VBI = 2 DIG_OUTPUT_CRC_FOR_AUDIO = 3 DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum # values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN' DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = { 0: 'DIG_IN_NORMAL_OPERATION', 1: 'DIG_IN_DEBUG_MODE', } DIG_IN_NORMAL_OPERATION = 0 DIG_IN_DEBUG_MODE = 1 DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum # values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL' DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = { 0: 'DIG_10BIT_TEST_PATTERN', 1: 'DIG_ALTERNATING_TEST_PATTERN', } DIG_10BIT_TEST_PATTERN = 0 DIG_ALTERNATING_TEST_PATTERN = 1 DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum # values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN' DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = { 0: 'DIG_TEST_PATTERN_NORMAL', 1: 'DIG_TEST_PATTERN_RANDOM', } DIG_TEST_PATTERN_NORMAL = 0 DIG_TEST_PATTERN_RANDOM = 1 DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum # values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET' DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = { 0: 'DIG_RANDOM_PATTERN_ENABLED', 1: 'DIG_RANDOM_PATTERN_RESETED', } DIG_RANDOM_PATTERN_ENABLED = 0 DIG_RANDOM_PATTERN_RESETED = 1 DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN' DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = { 0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', 1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', } DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0 DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1 DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum # values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT' DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { 0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', 1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', } DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0 DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1 DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum # values for enumeration 'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL' DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL__enumvalues = { 0: 'DIG_FIFO_USE_OVERWRITE_LEVEL', 1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', } DIG_FIFO_USE_OVERWRITE_LEVEL = 0 DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1 DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum # values for enumeration 'DIG_FIFO_ERROR_ACK' DIG_FIFO_ERROR_ACK__enumvalues = { 0: 'DIG_FIFO_ERROR_ACK_INT', 1: 'DIG_FIFO_ERROR_NOT_ACK', } DIG_FIFO_ERROR_ACK_INT = 0 DIG_FIFO_ERROR_NOT_ACK = 1 DIG_FIFO_ERROR_ACK = ctypes.c_uint32 # enum # values for enumeration 'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE' DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE__enumvalues = { 0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', 1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', } DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0 DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1 DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum # values for enumeration 'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX' DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX__enumvalues = { 0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 1: 'DIG_FIFO_FORCE_RECOMP_MINMAX', } DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0 DIG_FIFO_FORCE_RECOMP_MINMAX = 1 DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum # values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK' AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = { 0: 'AFMT_INTERRUPT_DISABLE', 1: 'AFMT_INTERRUPT_ENABLE', } AFMT_INTERRUPT_DISABLE = 0 AFMT_INTERRUPT_ENABLE = 1 AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum # values for enumeration 'HDMI_GC_AVMUTE' HDMI_GC_AVMUTE__enumvalues = { 0: 'HDMI_GC_AVMUTE_SET', 1: 'HDMI_GC_AVMUTE_UNSET', } HDMI_GC_AVMUTE_SET = 0 HDMI_GC_AVMUTE_UNSET = 1 HDMI_GC_AVMUTE = ctypes.c_uint32 # enum # values for enumeration 'HDMI_DEFAULT_PAHSE' HDMI_DEFAULT_PAHSE__enumvalues = { 0: 'HDMI_DEFAULT_PHASE_IS_0', 1: 'HDMI_DEFAULT_PHASE_IS_1', } HDMI_DEFAULT_PHASE_IS_0 = 0 HDMI_DEFAULT_PHASE_IS_1 = 1 HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum # values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD' AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = { 0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', 1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', } AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0 AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1 AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum # values for enumeration 'AUDIO_LAYOUT_SELECT' AUDIO_LAYOUT_SELECT__enumvalues = { 0: 'AUDIO_LAYOUT_0', 1: 'AUDIO_LAYOUT_1', } AUDIO_LAYOUT_0 = 0 AUDIO_LAYOUT_1 = 1 AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum # values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT' AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = { 0: 'AFMT_AUDIO_CRC_ONESHOT', 1: 'AFMT_AUDIO_CRC_AUTO_RESTART', } AFMT_AUDIO_CRC_ONESHOT = 0 AFMT_AUDIO_CRC_AUTO_RESTART = 1 AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum # values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE' AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = { 0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', 1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', } AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0 AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1 AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum # values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL' AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { 0: 'AFMT_AUDIO_CRC_CH0_SIG', 1: 'AFMT_AUDIO_CRC_CH1_SIG', 2: 'AFMT_AUDIO_CRC_CH2_SIG', 3: 'AFMT_AUDIO_CRC_CH3_SIG', 4: 'AFMT_AUDIO_CRC_CH4_SIG', 5: 'AFMT_AUDIO_CRC_CH5_SIG', 6: 'AFMT_AUDIO_CRC_CH6_SIG', 7: 'AFMT_AUDIO_CRC_CH7_SIG', 8: 'AFMT_AUDIO_CRC_RESERVED_8', 9: 'AFMT_AUDIO_CRC_RESERVED_9', 10: 'AFMT_AUDIO_CRC_RESERVED_10', 11: 'AFMT_AUDIO_CRC_RESERVED_11', 12: 'AFMT_AUDIO_CRC_RESERVED_12', 13: 'AFMT_AUDIO_CRC_RESERVED_13', 14: 'AFMT_AUDIO_CRC_RESERVED_14', 15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', } AFMT_AUDIO_CRC_CH0_SIG = 0 AFMT_AUDIO_CRC_CH1_SIG = 1 AFMT_AUDIO_CRC_CH2_SIG = 2 AFMT_AUDIO_CRC_CH3_SIG = 3 AFMT_AUDIO_CRC_CH4_SIG = 4 AFMT_AUDIO_CRC_CH5_SIG = 5 AFMT_AUDIO_CRC_CH6_SIG = 6 AFMT_AUDIO_CRC_CH7_SIG = 7 AFMT_AUDIO_CRC_RESERVED_8 = 8 AFMT_AUDIO_CRC_RESERVED_9 = 9 AFMT_AUDIO_CRC_RESERVED_10 = 10 AFMT_AUDIO_CRC_RESERVED_11 = 11 AFMT_AUDIO_CRC_RESERVED_12 = 12 AFMT_AUDIO_CRC_RESERVED_13 = 13 AFMT_AUDIO_CRC_RESERVED_14 = 14 AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15 AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum # values for enumeration 'AFMT_RAMP_CONTROL0_SIGN' AFMT_RAMP_CONTROL0_SIGN__enumvalues = { 0: 'AFMT_RAMP_SIGNED', 1: 'AFMT_RAMP_UNSIGNED', } AFMT_RAMP_SIGNED = 0 AFMT_RAMP_UNSIGNED = 1 AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum # values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND' AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = { 0: 'AFMT_AUDIO_PACKET_SENT_DISABLED', 1: 'AFMT_AUDIO_PACKET_SENT_ENABLED', } AFMT_AUDIO_PACKET_SENT_DISABLED = 0 AFMT_AUDIO_PACKET_SENT_ENABLED = 1 AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum # values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS' AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = { 0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', 1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', } AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0 AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1 AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum # values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE' AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = { 0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', 1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', } AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0 AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1 AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum # values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT' AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = { 0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', 1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', 2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', 3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', 4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', 5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', 6: 'AFMT_AUDIO_SRC_RESERVED', } AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0 AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1 AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2 AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3 AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4 AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5 AFMT_AUDIO_SRC_RESERVED = 6 AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum # values for enumeration 'DIG_BE_CNTL_MODE' DIG_BE_CNTL_MODE__enumvalues = { 0: 'DIG_BE_DP_SST_MODE', 1: 'DIG_BE_RESERVED1', 2: 'DIG_BE_TMDS_DVI_MODE', 3: 'DIG_BE_TMDS_HDMI_MODE', 4: 'DIG_BE_SDVO_RESERVED', 5: 'DIG_BE_DP_MST_MODE', 6: 'DIG_BE_RESERVED2', 7: 'DIG_BE_RESERVED3', } DIG_BE_DP_SST_MODE = 0 DIG_BE_RESERVED1 = 1 DIG_BE_TMDS_DVI_MODE = 2 DIG_BE_TMDS_HDMI_MODE = 3 DIG_BE_SDVO_RESERVED = 4 DIG_BE_DP_MST_MODE = 5 DIG_BE_RESERVED2 = 6 DIG_BE_RESERVED3 = 7 DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum # values for enumeration 'DIG_BE_CNTL_HPD_SELECT' DIG_BE_CNTL_HPD_SELECT__enumvalues = { 0: 'DIG_BE_CNTL_HPD1', 1: 'DIG_BE_CNTL_HPD2', 2: 'DIG_BE_CNTL_HPD3', 3: 'DIG_BE_CNTL_HPD4', 4: 'DIG_BE_CNTL_HPD5', 5: 'DIG_BE_CNTL_HPD6', } DIG_BE_CNTL_HPD1 = 0 DIG_BE_CNTL_HPD2 = 1 DIG_BE_CNTL_HPD3 = 2 DIG_BE_CNTL_HPD4 = 3 DIG_BE_CNTL_HPD5 = 4 DIG_BE_CNTL_HPD6 = 5 DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum # values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT' LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { 0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', 1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', } LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0 LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1 LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum # values for enumeration 'TMDS_SYNC_PHASE' TMDS_SYNC_PHASE__enumvalues = { 0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', 1: 'TMDS_SYNC_PHASE_ON_FRAME_START', } TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0 TMDS_SYNC_PHASE_ON_FRAME_START = 1 TMDS_SYNC_PHASE = ctypes.c_uint32 # enum # values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL' TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = { 0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', 1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', } TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0 TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1 TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum # values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK' TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = { 0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', 1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', } TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0 TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1 TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum # values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK' TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = { 0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', 1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', } TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0 TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1 TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum # values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK' TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = { 0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', 1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', } TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0 TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1 TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum # values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK' TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = { 0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', 1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', 2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', 3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', } TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3 TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum # values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA' TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = { 0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', 1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', } TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0 TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1 TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum # values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB' TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = { 0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', 1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', } TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0 TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1 TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum # values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN' TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = { 0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', 1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', } TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0 TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1 TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum # values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK' TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = { 0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', 1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', } TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0 TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1 TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum # values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS' TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = { 0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', 1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', } TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0 TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1 TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum # values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS' TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = { 0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', 1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', } TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0 TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1 TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum # values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN' TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = { 0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW', 1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', } TMDS_TRANSMITTER_PLLSEL_BY_HW = 0 TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1 TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum # values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA' TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = { 0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', 1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', } TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0 TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1 TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum # values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB' TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = { 0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', 1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', } TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0 TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1 TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum # values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA' TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = { 0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', 1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', 2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', 3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', } TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2 TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3 TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum # values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB' TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = { 0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', 1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', 2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', } TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2 TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3 TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_ENABLE' DCP_GRPH_ENABLE__enumvalues = { 0: 'DCP_GRPH_ENABLE_FALSE', 1: 'DCP_GRPH_ENABLE_TRUE', } DCP_GRPH_ENABLE_FALSE = 0 DCP_GRPH_ENABLE_TRUE = 1 DCP_GRPH_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_KEYER_ALPHA_SEL' DCP_GRPH_KEYER_ALPHA_SEL__enumvalues = { 0: 'DCP_GRPH_KEYER_ALPHA_SEL_FALSE', 1: 'DCP_GRPH_KEYER_ALPHA_SEL_TRUE', } DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0 DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 1 DCP_GRPH_KEYER_ALPHA_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_DEPTH' DCP_GRPH_DEPTH__enumvalues = { 0: 'DCP_GRPH_DEPTH_8BPP', 1: 'DCP_GRPH_DEPTH_16BPP', 2: 'DCP_GRPH_DEPTH_32BPP', 3: 'DCP_GRPH_DEPTH_64BPP', } DCP_GRPH_DEPTH_8BPP = 0 DCP_GRPH_DEPTH_16BPP = 1 DCP_GRPH_DEPTH_32BPP = 2 DCP_GRPH_DEPTH_64BPP = 3 DCP_GRPH_DEPTH = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_NUM_BANKS' DCP_GRPH_NUM_BANKS__enumvalues = { 0: 'DCP_GRPH_NUM_BANKS_1BANK', 1: 'DCP_GRPH_NUM_BANKS_2BANK', 2: 'DCP_GRPH_NUM_BANKS_4BANK', 3: 'DCP_GRPH_NUM_BANKS_8BANK', 4: 'DCP_GRPH_NUM_BANKS_16BANK', } DCP_GRPH_NUM_BANKS_1BANK = 0 DCP_GRPH_NUM_BANKS_2BANK = 1 DCP_GRPH_NUM_BANKS_4BANK = 2 DCP_GRPH_NUM_BANKS_8BANK = 3 DCP_GRPH_NUM_BANKS_16BANK = 4 DCP_GRPH_NUM_BANKS = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_NUM_PIPES' DCP_GRPH_NUM_PIPES__enumvalues = { 0: 'DCP_GRPH_NUM_PIPES_1PIPE', 1: 'DCP_GRPH_NUM_PIPES_2PIPE', 2: 'DCP_GRPH_NUM_PIPES_4PIPE', 3: 'DCP_GRPH_NUM_PIPES_8PIPE', } DCP_GRPH_NUM_PIPES_1PIPE = 0 DCP_GRPH_NUM_PIPES_2PIPE = 1 DCP_GRPH_NUM_PIPES_4PIPE = 2 DCP_GRPH_NUM_PIPES_8PIPE = 3 DCP_GRPH_NUM_PIPES = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_FORMAT' DCP_GRPH_FORMAT__enumvalues = { 0: 'DCP_GRPH_FORMAT_8BPP', 1: 'DCP_GRPH_FORMAT_16BPP', 2: 'DCP_GRPH_FORMAT_32BPP', 3: 'DCP_GRPH_FORMAT_64BPP', } DCP_GRPH_FORMAT_8BPP = 0 DCP_GRPH_FORMAT_16BPP = 1 DCP_GRPH_FORMAT_32BPP = 2 DCP_GRPH_FORMAT_64BPP = 3 DCP_GRPH_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE' DCP_GRPH_ADDRESS_TRANSLATION_ENABLE__enumvalues = { 0: 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE', 1: 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE', } DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0 DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 1 DCP_GRPH_ADDRESS_TRANSLATION_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_SW_MODE' DCP_GRPH_SW_MODE__enumvalues = { 0: 'DCP_GRPH_SW_MODE_0', 2: 'DCP_GRPH_SW_MODE_2', 3: 'DCP_GRPH_SW_MODE_3', 22: 'DCP_GRPH_SW_MODE_22', 23: 'DCP_GRPH_SW_MODE_23', 26: 'DCP_GRPH_SW_MODE_26', 27: 'DCP_GRPH_SW_MODE_27', 30: 'DCP_GRPH_SW_MODE_30', 31: 'DCP_GRPH_SW_MODE_31', } DCP_GRPH_SW_MODE_0 = 0 DCP_GRPH_SW_MODE_2 = 2 DCP_GRPH_SW_MODE_3 = 3 DCP_GRPH_SW_MODE_22 = 22 DCP_GRPH_SW_MODE_23 = 23 DCP_GRPH_SW_MODE_26 = 26 DCP_GRPH_SW_MODE_27 = 27 DCP_GRPH_SW_MODE_30 = 30 DCP_GRPH_SW_MODE_31 = 31 DCP_GRPH_SW_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_COLOR_EXPANSION_MODE' DCP_GRPH_COLOR_EXPANSION_MODE__enumvalues = { 0: 'DCP_GRPH_COLOR_EXPANSION_MODE_DEXP', 1: 'DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP', } DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0 DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 1 DCP_GRPH_COLOR_EXPANSION_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_LUT_10BIT_BYPASS_EN' DCP_GRPH_LUT_10BIT_BYPASS_EN__enumvalues = { 0: 'DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE', 1: 'DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE', } DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0 DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 1 DCP_GRPH_LUT_10BIT_BYPASS_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN' DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__enumvalues = { 0: 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE', 1: 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE', } DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0 DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 1 DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_ENDIAN_SWAP' DCP_GRPH_ENDIAN_SWAP__enumvalues = { 0: 'DCP_GRPH_ENDIAN_SWAP_NONE', 1: 'DCP_GRPH_ENDIAN_SWAP_8IN16', 2: 'DCP_GRPH_ENDIAN_SWAP_8IN32', 3: 'DCP_GRPH_ENDIAN_SWAP_8IN64', } DCP_GRPH_ENDIAN_SWAP_NONE = 0 DCP_GRPH_ENDIAN_SWAP_8IN16 = 1 DCP_GRPH_ENDIAN_SWAP_8IN32 = 2 DCP_GRPH_ENDIAN_SWAP_8IN64 = 3 DCP_GRPH_ENDIAN_SWAP = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_RED_CROSSBAR' DCP_GRPH_RED_CROSSBAR__enumvalues = { 0: 'DCP_GRPH_RED_CROSSBAR_FROM_R', 1: 'DCP_GRPH_RED_CROSSBAR_FROM_G', 2: 'DCP_GRPH_RED_CROSSBAR_FROM_B', 3: 'DCP_GRPH_RED_CROSSBAR_FROM_A', } DCP_GRPH_RED_CROSSBAR_FROM_R = 0 DCP_GRPH_RED_CROSSBAR_FROM_G = 1 DCP_GRPH_RED_CROSSBAR_FROM_B = 2 DCP_GRPH_RED_CROSSBAR_FROM_A = 3 DCP_GRPH_RED_CROSSBAR = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_GREEN_CROSSBAR' DCP_GRPH_GREEN_CROSSBAR__enumvalues = { 0: 'DCP_GRPH_GREEN_CROSSBAR_FROM_G', 1: 'DCP_GRPH_GREEN_CROSSBAR_FROM_B', 2: 'DCP_GRPH_GREEN_CROSSBAR_FROM_A', 3: 'DCP_GRPH_GREEN_CROSSBAR_FROM_R', } DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0 DCP_GRPH_GREEN_CROSSBAR_FROM_B = 1 DCP_GRPH_GREEN_CROSSBAR_FROM_A = 2 DCP_GRPH_GREEN_CROSSBAR_FROM_R = 3 DCP_GRPH_GREEN_CROSSBAR = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_BLUE_CROSSBAR' DCP_GRPH_BLUE_CROSSBAR__enumvalues = { 0: 'DCP_GRPH_BLUE_CROSSBAR_FROM_B', 1: 'DCP_GRPH_BLUE_CROSSBAR_FROM_A', 2: 'DCP_GRPH_BLUE_CROSSBAR_FROM_R', 3: 'DCP_GRPH_BLUE_CROSSBAR_FROM_G', } DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0 DCP_GRPH_BLUE_CROSSBAR_FROM_A = 1 DCP_GRPH_BLUE_CROSSBAR_FROM_R = 2 DCP_GRPH_BLUE_CROSSBAR_FROM_G = 3 DCP_GRPH_BLUE_CROSSBAR = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_ALPHA_CROSSBAR' DCP_GRPH_ALPHA_CROSSBAR__enumvalues = { 0: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_A', 1: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_R', 2: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_G', 3: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_B', } DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0 DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 1 DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 2 DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 3 DCP_GRPH_ALPHA_CROSSBAR = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_PRIMARY_DFQ_ENABLE' DCP_GRPH_PRIMARY_DFQ_ENABLE__enumvalues = { 0: 'DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE', 1: 'DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE', } DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0 DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 1 DCP_GRPH_PRIMARY_DFQ_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_SECONDARY_DFQ_ENABLE' DCP_GRPH_SECONDARY_DFQ_ENABLE__enumvalues = { 0: 'DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE', 1: 'DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE', } DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0 DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 1 DCP_GRPH_SECONDARY_DFQ_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_INPUT_GAMMA_MODE' DCP_GRPH_INPUT_GAMMA_MODE__enumvalues = { 0: 'DCP_GRPH_INPUT_GAMMA_MODE_LUT', 1: 'DCP_GRPH_INPUT_GAMMA_MODE_BYPASS', } DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0 DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 1 DCP_GRPH_INPUT_GAMMA_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_MODE_UPDATE_PENDING' DCP_GRPH_MODE_UPDATE_PENDING__enumvalues = { 0: 'DCP_GRPH_MODE_UPDATE_PENDING_FALSE', 1: 'DCP_GRPH_MODE_UPDATE_PENDING_TRUE', } DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0 DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 1 DCP_GRPH_MODE_UPDATE_PENDING = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_MODE_UPDATE_TAKEN' DCP_GRPH_MODE_UPDATE_TAKEN__enumvalues = { 0: 'DCP_GRPH_MODE_UPDATE_TAKEN_FALSE', 1: 'DCP_GRPH_MODE_UPDATE_TAKEN_TRUE', } DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0 DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 1 DCP_GRPH_MODE_UPDATE_TAKEN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_SURFACE_UPDATE_PENDING' DCP_GRPH_SURFACE_UPDATE_PENDING__enumvalues = { 0: 'DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE', 1: 'DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE', } DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0 DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 1 DCP_GRPH_SURFACE_UPDATE_PENDING = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_SURFACE_UPDATE_TAKEN' DCP_GRPH_SURFACE_UPDATE_TAKEN__enumvalues = { 0: 'DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE', 1: 'DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE', } DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0 DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 1 DCP_GRPH_SURFACE_UPDATE_TAKEN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE' DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE__enumvalues = { 0: 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE', 1: 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE', } DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0 DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 1 DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_UPDATE_LOCK' DCP_GRPH_UPDATE_LOCK__enumvalues = { 0: 'DCP_GRPH_UPDATE_LOCK_FALSE', 1: 'DCP_GRPH_UPDATE_LOCK_TRUE', } DCP_GRPH_UPDATE_LOCK_FALSE = 0 DCP_GRPH_UPDATE_LOCK_TRUE = 1 DCP_GRPH_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK' DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK__enumvalues = { 0: 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE', 1: 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE', } DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0 DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 1 DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE' DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE__enumvalues = { 0: 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE', 1: 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE', } DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0 DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 1 DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE' DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__enumvalues = { 0: 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE', 1: 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE', } DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0 DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 1 DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN' DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN__enumvalues = { 0: 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE', 1: 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE', } DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0 DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 1 DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_XDMA_SUPER_AA_EN' DCP_GRPH_XDMA_SUPER_AA_EN__enumvalues = { 0: 'DCP_GRPH_XDMA_SUPER_AA_EN_FALSE', 1: 'DCP_GRPH_XDMA_SUPER_AA_EN_TRUE', } DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0 DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 1 DCP_GRPH_XDMA_SUPER_AA_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_DFQ_RESET' DCP_GRPH_DFQ_RESET__enumvalues = { 0: 'DCP_GRPH_DFQ_RESET_FALSE', 1: 'DCP_GRPH_DFQ_RESET_TRUE', } DCP_GRPH_DFQ_RESET_FALSE = 0 DCP_GRPH_DFQ_RESET_TRUE = 1 DCP_GRPH_DFQ_RESET = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_DFQ_SIZE' DCP_GRPH_DFQ_SIZE__enumvalues = { 0: 'DCP_GRPH_DFQ_SIZE_DEEP1', 1: 'DCP_GRPH_DFQ_SIZE_DEEP2', 2: 'DCP_GRPH_DFQ_SIZE_DEEP3', 3: 'DCP_GRPH_DFQ_SIZE_DEEP4', 4: 'DCP_GRPH_DFQ_SIZE_DEEP5', 5: 'DCP_GRPH_DFQ_SIZE_DEEP6', 6: 'DCP_GRPH_DFQ_SIZE_DEEP7', 7: 'DCP_GRPH_DFQ_SIZE_DEEP8', } DCP_GRPH_DFQ_SIZE_DEEP1 = 0 DCP_GRPH_DFQ_SIZE_DEEP2 = 1 DCP_GRPH_DFQ_SIZE_DEEP3 = 2 DCP_GRPH_DFQ_SIZE_DEEP4 = 3 DCP_GRPH_DFQ_SIZE_DEEP5 = 4 DCP_GRPH_DFQ_SIZE_DEEP6 = 5 DCP_GRPH_DFQ_SIZE_DEEP7 = 6 DCP_GRPH_DFQ_SIZE_DEEP8 = 7 DCP_GRPH_DFQ_SIZE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES' DCP_GRPH_DFQ_MIN_FREE_ENTRIES__enumvalues = { 0: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1', 1: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2', 2: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3', 3: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4', 4: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5', 5: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6', 6: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7', 7: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8', } DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 1 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 2 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 3 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 4 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 5 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 6 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 7 DCP_GRPH_DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_DFQ_RESET_ACK' DCP_GRPH_DFQ_RESET_ACK__enumvalues = { 0: 'DCP_GRPH_DFQ_RESET_ACK_FALSE', 1: 'DCP_GRPH_DFQ_RESET_ACK_TRUE', } DCP_GRPH_DFQ_RESET_ACK_FALSE = 0 DCP_GRPH_DFQ_RESET_ACK_TRUE = 1 DCP_GRPH_DFQ_RESET_ACK = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_PFLIP_INT_CLEAR' DCP_GRPH_PFLIP_INT_CLEAR__enumvalues = { 0: 'DCP_GRPH_PFLIP_INT_CLEAR_FALSE', 1: 'DCP_GRPH_PFLIP_INT_CLEAR_TRUE', } DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0 DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 1 DCP_GRPH_PFLIP_INT_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_PFLIP_INT_MASK' DCP_GRPH_PFLIP_INT_MASK__enumvalues = { 0: 'DCP_GRPH_PFLIP_INT_MASK_FALSE', 1: 'DCP_GRPH_PFLIP_INT_MASK_TRUE', } DCP_GRPH_PFLIP_INT_MASK_FALSE = 0 DCP_GRPH_PFLIP_INT_MASK_TRUE = 1 DCP_GRPH_PFLIP_INT_MASK = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_PFLIP_INT_TYPE' DCP_GRPH_PFLIP_INT_TYPE__enumvalues = { 0: 'DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL', 1: 'DCP_GRPH_PFLIP_INT_TYPE_PULSE', } DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0 DCP_GRPH_PFLIP_INT_TYPE_PULSE = 1 DCP_GRPH_PFLIP_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_PRESCALE_SELECT' DCP_GRPH_PRESCALE_SELECT__enumvalues = { 0: 'DCP_GRPH_PRESCALE_SELECT_FIXED', 1: 'DCP_GRPH_PRESCALE_SELECT_FLOATING', } DCP_GRPH_PRESCALE_SELECT_FIXED = 0 DCP_GRPH_PRESCALE_SELECT_FLOATING = 1 DCP_GRPH_PRESCALE_SELECT = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_PRESCALE_R_SIGN' DCP_GRPH_PRESCALE_R_SIGN__enumvalues = { 0: 'DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED', 1: 'DCP_GRPH_PRESCALE_R_SIGN_SIGNED', } DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0 DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 1 DCP_GRPH_PRESCALE_R_SIGN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_PRESCALE_G_SIGN' DCP_GRPH_PRESCALE_G_SIGN__enumvalues = { 0: 'DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED', 1: 'DCP_GRPH_PRESCALE_G_SIGN_SIGNED', } DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0 DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 1 DCP_GRPH_PRESCALE_G_SIGN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_PRESCALE_B_SIGN' DCP_GRPH_PRESCALE_B_SIGN__enumvalues = { 0: 'DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED', 1: 'DCP_GRPH_PRESCALE_B_SIGN_SIGNED', } DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0 DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 1 DCP_GRPH_PRESCALE_B_SIGN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_PRESCALE_BYPASS' DCP_GRPH_PRESCALE_BYPASS__enumvalues = { 0: 'DCP_GRPH_PRESCALE_BYPASS_FALSE', 1: 'DCP_GRPH_PRESCALE_BYPASS_TRUE', } DCP_GRPH_PRESCALE_BYPASS_FALSE = 0 DCP_GRPH_PRESCALE_BYPASS_TRUE = 1 DCP_GRPH_PRESCALE_BYPASS = ctypes.c_uint32 # enum # values for enumeration 'DCP_INPUT_CSC_GRPH_MODE' DCP_INPUT_CSC_GRPH_MODE__enumvalues = { 0: 'DCP_INPUT_CSC_GRPH_MODE_BYPASS', 1: 'DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF', 2: 'DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF', 3: 'DCP_INPUT_CSC_GRPH_MODE_RESERVED', } DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0 DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 1 DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 2 DCP_INPUT_CSC_GRPH_MODE_RESERVED = 3 DCP_INPUT_CSC_GRPH_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_OUTPUT_CSC_GRPH_MODE' DCP_OUTPUT_CSC_GRPH_MODE__enumvalues = { 0: 'DCP_OUTPUT_CSC_GRPH_MODE_BYPASS', 1: 'DCP_OUTPUT_CSC_GRPH_MODE_RGB', 2: 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601', 3: 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709', 4: 'DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF', 5: 'DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF', 6: 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0', 7: 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1', } DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0 DCP_OUTPUT_CSC_GRPH_MODE_RGB = 1 DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 2 DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 3 DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 4 DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 5 DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 6 DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 7 DCP_OUTPUT_CSC_GRPH_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_DENORM_MODE' DCP_DENORM_MODE__enumvalues = { 0: 'DCP_DENORM_MODE_UNITY', 1: 'DCP_DENORM_MODE_6BIT', 2: 'DCP_DENORM_MODE_8BIT', 3: 'DCP_DENORM_MODE_10BIT', 4: 'DCP_DENORM_MODE_11BIT', 5: 'DCP_DENORM_MODE_12BIT', 6: 'DCP_DENORM_MODE_RESERVED0', 7: 'DCP_DENORM_MODE_RESERVED1', } DCP_DENORM_MODE_UNITY = 0 DCP_DENORM_MODE_6BIT = 1 DCP_DENORM_MODE_8BIT = 2 DCP_DENORM_MODE_10BIT = 3 DCP_DENORM_MODE_11BIT = 4 DCP_DENORM_MODE_12BIT = 5 DCP_DENORM_MODE_RESERVED0 = 6 DCP_DENORM_MODE_RESERVED1 = 7 DCP_DENORM_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_DENORM_14BIT_OUT' DCP_DENORM_14BIT_OUT__enumvalues = { 0: 'DCP_DENORM_14BIT_OUT_FALSE', 1: 'DCP_DENORM_14BIT_OUT_TRUE', } DCP_DENORM_14BIT_OUT_FALSE = 0 DCP_DENORM_14BIT_OUT_TRUE = 1 DCP_DENORM_14BIT_OUT = ctypes.c_uint32 # enum # values for enumeration 'DCP_OUT_ROUND_TRUNC_MODE' DCP_OUT_ROUND_TRUNC_MODE__enumvalues = { 0: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12', 1: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11', 2: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10', 3: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9', 4: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8', 5: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED', 6: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14', 7: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13', 8: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_12', 9: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_11', 10: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_10', 11: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_9', 12: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_8', 13: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED', 14: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_14', 15: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_13', } DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 1 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 2 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 3 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 4 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 5 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 6 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 7 DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 8 DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 9 DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 10 DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 11 DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 12 DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 13 DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 14 DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 15 DCP_OUT_ROUND_TRUNC_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_KEY_MODE' DCP_KEY_MODE__enumvalues = { 0: 'DCP_KEY_MODE_ALPHA0', 1: 'DCP_KEY_MODE_ALPHA1', 2: 'DCP_KEY_MODE_IN_RANGE_ALPHA1', 3: 'DCP_KEY_MODE_IN_RANGE_ALPHA0', } DCP_KEY_MODE_ALPHA0 = 0 DCP_KEY_MODE_ALPHA1 = 1 DCP_KEY_MODE_IN_RANGE_ALPHA1 = 2 DCP_KEY_MODE_IN_RANGE_ALPHA0 = 3 DCP_KEY_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_DEGAMMA_MODE' DCP_GRPH_DEGAMMA_MODE__enumvalues = { 0: 'DCP_GRPH_DEGAMMA_MODE_BYPASS', 1: 'DCP_GRPH_DEGAMMA_MODE_ROMA', 2: 'DCP_GRPH_DEGAMMA_MODE_ROMB', 3: 'DCP_GRPH_DEGAMMA_MODE_RESERVED', } DCP_GRPH_DEGAMMA_MODE_BYPASS = 0 DCP_GRPH_DEGAMMA_MODE_ROMA = 1 DCP_GRPH_DEGAMMA_MODE_ROMB = 2 DCP_GRPH_DEGAMMA_MODE_RESERVED = 3 DCP_GRPH_DEGAMMA_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_DEGAMMA_MODE' DCP_CURSOR_DEGAMMA_MODE__enumvalues = { 0: 'DCP_CURSOR_DEGAMMA_MODE_BYPASS', 1: 'DCP_CURSOR_DEGAMMA_MODE_ROMA', 2: 'DCP_CURSOR_DEGAMMA_MODE_ROMB', 3: 'DCP_CURSOR_DEGAMMA_MODE_RESERVED', } DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0 DCP_CURSOR_DEGAMMA_MODE_ROMA = 1 DCP_CURSOR_DEGAMMA_MODE_ROMB = 2 DCP_CURSOR_DEGAMMA_MODE_RESERVED = 3 DCP_CURSOR_DEGAMMA_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_GAMUT_REMAP_MODE' DCP_GRPH_GAMUT_REMAP_MODE__enumvalues = { 0: 'DCP_GRPH_GAMUT_REMAP_MODE_BYPASS', 1: 'DCP_GRPH_GAMUT_REMAP_MODE_ROMA', 2: 'DCP_GRPH_GAMUT_REMAP_MODE_ROMB', 3: 'DCP_GRPH_GAMUT_REMAP_MODE_RESERVED', } DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0 DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 1 DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 2 DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 3 DCP_GRPH_GAMUT_REMAP_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_SPATIAL_DITHER_EN' DCP_SPATIAL_DITHER_EN__enumvalues = { 0: 'DCP_SPATIAL_DITHER_EN_FALSE', 1: 'DCP_SPATIAL_DITHER_EN_TRUE', } DCP_SPATIAL_DITHER_EN_FALSE = 0 DCP_SPATIAL_DITHER_EN_TRUE = 1 DCP_SPATIAL_DITHER_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_SPATIAL_DITHER_MODE' DCP_SPATIAL_DITHER_MODE__enumvalues = { 0: 'DCP_SPATIAL_DITHER_MODE_BYPASS', 1: 'DCP_SPATIAL_DITHER_MODE_ROMA', 2: 'DCP_SPATIAL_DITHER_MODE_ROMB', 3: 'DCP_SPATIAL_DITHER_MODE_RESERVED', } DCP_SPATIAL_DITHER_MODE_BYPASS = 0 DCP_SPATIAL_DITHER_MODE_ROMA = 1 DCP_SPATIAL_DITHER_MODE_ROMB = 2 DCP_SPATIAL_DITHER_MODE_RESERVED = 3 DCP_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_SPATIAL_DITHER_DEPTH' DCP_SPATIAL_DITHER_DEPTH__enumvalues = { 0: 'DCP_SPATIAL_DITHER_DEPTH_30BPP', 1: 'DCP_SPATIAL_DITHER_DEPTH_24BPP', 2: 'DCP_SPATIAL_DITHER_DEPTH_36BPP', 3: 'DCP_SPATIAL_DITHER_DEPTH_UNDEFINED', } DCP_SPATIAL_DITHER_DEPTH_30BPP = 0 DCP_SPATIAL_DITHER_DEPTH_24BPP = 1 DCP_SPATIAL_DITHER_DEPTH_36BPP = 2 DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 3 DCP_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum # values for enumeration 'DCP_FRAME_RANDOM_ENABLE' DCP_FRAME_RANDOM_ENABLE__enumvalues = { 0: 'DCP_FRAME_RANDOM_ENABLE_FALSE', 1: 'DCP_FRAME_RANDOM_ENABLE_TRUE', } DCP_FRAME_RANDOM_ENABLE_FALSE = 0 DCP_FRAME_RANDOM_ENABLE_TRUE = 1 DCP_FRAME_RANDOM_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_RGB_RANDOM_ENABLE' DCP_RGB_RANDOM_ENABLE__enumvalues = { 0: 'DCP_RGB_RANDOM_ENABLE_FALSE', 1: 'DCP_RGB_RANDOM_ENABLE_TRUE', } DCP_RGB_RANDOM_ENABLE_FALSE = 0 DCP_RGB_RANDOM_ENABLE_TRUE = 1 DCP_RGB_RANDOM_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_HIGHPASS_RANDOM_ENABLE' DCP_HIGHPASS_RANDOM_ENABLE__enumvalues = { 0: 'DCP_HIGHPASS_RANDOM_ENABLE_FALSE', 1: 'DCP_HIGHPASS_RANDOM_ENABLE_TRUE', } DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0 DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 1 DCP_HIGHPASS_RANDOM_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_EN' DCP_CURSOR_EN__enumvalues = { 0: 'DCP_CURSOR_EN_FALSE', 1: 'DCP_CURSOR_EN_TRUE', } DCP_CURSOR_EN_FALSE = 0 DCP_CURSOR_EN_TRUE = 1 DCP_CURSOR_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_CUR_INV_TRANS_CLAMP' DCP_CUR_INV_TRANS_CLAMP__enumvalues = { 0: 'DCP_CUR_INV_TRANS_CLAMP_FALSE', 1: 'DCP_CUR_INV_TRANS_CLAMP_TRUE', } DCP_CUR_INV_TRANS_CLAMP_FALSE = 0 DCP_CUR_INV_TRANS_CLAMP_TRUE = 1 DCP_CUR_INV_TRANS_CLAMP = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_MODE' DCP_CURSOR_MODE__enumvalues = { 0: 'DCP_CURSOR_MODE_MONO_2BPP', 1: 'DCP_CURSOR_MODE_24BPP_1BIT', 2: 'DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI', 3: 'DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI', } DCP_CURSOR_MODE_MONO_2BPP = 0 DCP_CURSOR_MODE_24BPP_1BIT = 1 DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 2 DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 3 DCP_CURSOR_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM' DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM__enumvalues = { 0: 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE', 1: 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO', } DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE = 0 DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO = 1 DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_2X_MAGNIFY' DCP_CURSOR_2X_MAGNIFY__enumvalues = { 0: 'DCP_CURSOR_2X_MAGNIFY_FALSE', 1: 'DCP_CURSOR_2X_MAGNIFY_TRUE', } DCP_CURSOR_2X_MAGNIFY_FALSE = 0 DCP_CURSOR_2X_MAGNIFY_TRUE = 1 DCP_CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_FORCE_MC_ON' DCP_CURSOR_FORCE_MC_ON__enumvalues = { 0: 'DCP_CURSOR_FORCE_MC_ON_FALSE', 1: 'DCP_CURSOR_FORCE_MC_ON_TRUE', } DCP_CURSOR_FORCE_MC_ON_FALSE = 0 DCP_CURSOR_FORCE_MC_ON_TRUE = 1 DCP_CURSOR_FORCE_MC_ON = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_URGENT_CONTROL' DCP_CURSOR_URGENT_CONTROL__enumvalues = { 0: 'DCP_CURSOR_URGENT_CONTROL_MODE_0', 1: 'DCP_CURSOR_URGENT_CONTROL_MODE_1', 2: 'DCP_CURSOR_URGENT_CONTROL_MODE_2', 3: 'DCP_CURSOR_URGENT_CONTROL_MODE_3', 4: 'DCP_CURSOR_URGENT_CONTROL_MODE_4', } DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0 DCP_CURSOR_URGENT_CONTROL_MODE_1 = 1 DCP_CURSOR_URGENT_CONTROL_MODE_2 = 2 DCP_CURSOR_URGENT_CONTROL_MODE_3 = 3 DCP_CURSOR_URGENT_CONTROL_MODE_4 = 4 DCP_CURSOR_URGENT_CONTROL = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_UPDATE_PENDING' DCP_CURSOR_UPDATE_PENDING__enumvalues = { 0: 'DCP_CURSOR_UPDATE_PENDING_FALSE', 1: 'DCP_CURSOR_UPDATE_PENDING_TRUE', } DCP_CURSOR_UPDATE_PENDING_FALSE = 0 DCP_CURSOR_UPDATE_PENDING_TRUE = 1 DCP_CURSOR_UPDATE_PENDING = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_UPDATE_TAKEN' DCP_CURSOR_UPDATE_TAKEN__enumvalues = { 0: 'DCP_CURSOR_UPDATE_TAKEN_FALSE', 1: 'DCP_CURSOR_UPDATE_TAKEN_TRUE', } DCP_CURSOR_UPDATE_TAKEN_FALSE = 0 DCP_CURSOR_UPDATE_TAKEN_TRUE = 1 DCP_CURSOR_UPDATE_TAKEN = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_UPDATE_LOCK' DCP_CURSOR_UPDATE_LOCK__enumvalues = { 0: 'DCP_CURSOR_UPDATE_LOCK_FALSE', 1: 'DCP_CURSOR_UPDATE_LOCK_TRUE', } DCP_CURSOR_UPDATE_LOCK_FALSE = 0 DCP_CURSOR_UPDATE_LOCK_TRUE = 1 DCP_CURSOR_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE' DCP_CURSOR_DISABLE_MULTIPLE_UPDATE__enumvalues = { 0: 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE', 1: 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE', } DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0 DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 1 DCP_CURSOR_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_UPDATE_STEREO_MODE' DCP_CURSOR_UPDATE_STEREO_MODE__enumvalues = { 0: 'DCP_CURSOR_UPDATE_STEREO_MODE_BOTH', 1: 'DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY', 2: 'DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED', 3: 'DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY', } DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0 DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 1 DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 2 DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 3 DCP_CURSOR_UPDATE_STEREO_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_CUR2_INV_TRANS_CLAMP' DCP_CUR2_INV_TRANS_CLAMP__enumvalues = { 0: 'DCP_CUR2_INV_TRANS_CLAMP_FALSE', 1: 'DCP_CUR2_INV_TRANS_CLAMP_TRUE', } DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0 DCP_CUR2_INV_TRANS_CLAMP_TRUE = 1 DCP_CUR2_INV_TRANS_CLAMP = ctypes.c_uint32 # enum # values for enumeration 'DCP_CUR_REQUEST_FILTER_DIS' DCP_CUR_REQUEST_FILTER_DIS__enumvalues = { 0: 'DCP_CUR_REQUEST_FILTER_DIS_FALSE', 1: 'DCP_CUR_REQUEST_FILTER_DIS_TRUE', } DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0 DCP_CUR_REQUEST_FILTER_DIS_TRUE = 1 DCP_CUR_REQUEST_FILTER_DIS = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_STEREO_EN' DCP_CURSOR_STEREO_EN__enumvalues = { 0: 'DCP_CURSOR_STEREO_EN_FALSE', 1: 'DCP_CURSOR_STEREO_EN_TRUE', } DCP_CURSOR_STEREO_EN_FALSE = 0 DCP_CURSOR_STEREO_EN_TRUE = 1 DCP_CURSOR_STEREO_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_STEREO_OFFSET_YNX' DCP_CURSOR_STEREO_OFFSET_YNX__enumvalues = { 0: 'DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION', 1: 'DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION', } DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0 DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 1 DCP_CURSOR_STEREO_OFFSET_YNX = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_RW_MODE' DCP_DC_LUT_RW_MODE__enumvalues = { 0: 'DCP_DC_LUT_RW_MODE_256_ENTRY', 1: 'DCP_DC_LUT_RW_MODE_PWL', } DCP_DC_LUT_RW_MODE_256_ENTRY = 0 DCP_DC_LUT_RW_MODE_PWL = 1 DCP_DC_LUT_RW_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_VGA_ACCESS_ENABLE' DCP_DC_LUT_VGA_ACCESS_ENABLE__enumvalues = { 0: 'DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE', 1: 'DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE', } DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0 DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 1 DCP_DC_LUT_VGA_ACCESS_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_AUTOFILL' DCP_DC_LUT_AUTOFILL__enumvalues = { 0: 'DCP_DC_LUT_AUTOFILL_FALSE', 1: 'DCP_DC_LUT_AUTOFILL_TRUE', } DCP_DC_LUT_AUTOFILL_FALSE = 0 DCP_DC_LUT_AUTOFILL_TRUE = 1 DCP_DC_LUT_AUTOFILL = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_AUTOFILL_DONE' DCP_DC_LUT_AUTOFILL_DONE__enumvalues = { 0: 'DCP_DC_LUT_AUTOFILL_DONE_FALSE', 1: 'DCP_DC_LUT_AUTOFILL_DONE_TRUE', } DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0 DCP_DC_LUT_AUTOFILL_DONE_TRUE = 1 DCP_DC_LUT_AUTOFILL_DONE = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_INC_B' DCP_DC_LUT_INC_B__enumvalues = { 0: 'DCP_DC_LUT_INC_B_NA', 1: 'DCP_DC_LUT_INC_B_2', 2: 'DCP_DC_LUT_INC_B_4', 3: 'DCP_DC_LUT_INC_B_8', 4: 'DCP_DC_LUT_INC_B_16', 5: 'DCP_DC_LUT_INC_B_32', 6: 'DCP_DC_LUT_INC_B_64', 7: 'DCP_DC_LUT_INC_B_128', 8: 'DCP_DC_LUT_INC_B_256', 9: 'DCP_DC_LUT_INC_B_512', } DCP_DC_LUT_INC_B_NA = 0 DCP_DC_LUT_INC_B_2 = 1 DCP_DC_LUT_INC_B_4 = 2 DCP_DC_LUT_INC_B_8 = 3 DCP_DC_LUT_INC_B_16 = 4 DCP_DC_LUT_INC_B_32 = 5 DCP_DC_LUT_INC_B_64 = 6 DCP_DC_LUT_INC_B_128 = 7 DCP_DC_LUT_INC_B_256 = 8 DCP_DC_LUT_INC_B_512 = 9 DCP_DC_LUT_INC_B = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_DATA_B_SIGNED_EN' DCP_DC_LUT_DATA_B_SIGNED_EN__enumvalues = { 0: 'DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE', 1: 'DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE', } DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0 DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 1 DCP_DC_LUT_DATA_B_SIGNED_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN' DCP_DC_LUT_DATA_B_FLOAT_POINT_EN__enumvalues = { 0: 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE', 1: 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE', } DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0 DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 1 DCP_DC_LUT_DATA_B_FLOAT_POINT_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_DATA_B_FORMAT' DCP_DC_LUT_DATA_B_FORMAT__enumvalues = { 0: 'DCP_DC_LUT_DATA_B_FORMAT_U0P10', 1: 'DCP_DC_LUT_DATA_B_FORMAT_S1P10', 2: 'DCP_DC_LUT_DATA_B_FORMAT_U1P11', 3: 'DCP_DC_LUT_DATA_B_FORMAT_U0P12', } DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0 DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 1 DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 2 DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 3 DCP_DC_LUT_DATA_B_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_INC_G' DCP_DC_LUT_INC_G__enumvalues = { 0: 'DCP_DC_LUT_INC_G_NA', 1: 'DCP_DC_LUT_INC_G_2', 2: 'DCP_DC_LUT_INC_G_4', 3: 'DCP_DC_LUT_INC_G_8', 4: 'DCP_DC_LUT_INC_G_16', 5: 'DCP_DC_LUT_INC_G_32', 6: 'DCP_DC_LUT_INC_G_64', 7: 'DCP_DC_LUT_INC_G_128', 8: 'DCP_DC_LUT_INC_G_256', 9: 'DCP_DC_LUT_INC_G_512', } DCP_DC_LUT_INC_G_NA = 0 DCP_DC_LUT_INC_G_2 = 1 DCP_DC_LUT_INC_G_4 = 2 DCP_DC_LUT_INC_G_8 = 3 DCP_DC_LUT_INC_G_16 = 4 DCP_DC_LUT_INC_G_32 = 5 DCP_DC_LUT_INC_G_64 = 6 DCP_DC_LUT_INC_G_128 = 7 DCP_DC_LUT_INC_G_256 = 8 DCP_DC_LUT_INC_G_512 = 9 DCP_DC_LUT_INC_G = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_DATA_G_SIGNED_EN' DCP_DC_LUT_DATA_G_SIGNED_EN__enumvalues = { 0: 'DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE', 1: 'DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE', } DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0 DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 1 DCP_DC_LUT_DATA_G_SIGNED_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN' DCP_DC_LUT_DATA_G_FLOAT_POINT_EN__enumvalues = { 0: 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE', 1: 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE', } DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0 DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 1 DCP_DC_LUT_DATA_G_FLOAT_POINT_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_DATA_G_FORMAT' DCP_DC_LUT_DATA_G_FORMAT__enumvalues = { 0: 'DCP_DC_LUT_DATA_G_FORMAT_U0P10', 1: 'DCP_DC_LUT_DATA_G_FORMAT_S1P10', 2: 'DCP_DC_LUT_DATA_G_FORMAT_U1P11', 3: 'DCP_DC_LUT_DATA_G_FORMAT_U0P12', } DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0 DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 1 DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 2 DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 3 DCP_DC_LUT_DATA_G_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_INC_R' DCP_DC_LUT_INC_R__enumvalues = { 0: 'DCP_DC_LUT_INC_R_NA', 1: 'DCP_DC_LUT_INC_R_2', 2: 'DCP_DC_LUT_INC_R_4', 3: 'DCP_DC_LUT_INC_R_8', 4: 'DCP_DC_LUT_INC_R_16', 5: 'DCP_DC_LUT_INC_R_32', 6: 'DCP_DC_LUT_INC_R_64', 7: 'DCP_DC_LUT_INC_R_128', 8: 'DCP_DC_LUT_INC_R_256', 9: 'DCP_DC_LUT_INC_R_512', } DCP_DC_LUT_INC_R_NA = 0 DCP_DC_LUT_INC_R_2 = 1 DCP_DC_LUT_INC_R_4 = 2 DCP_DC_LUT_INC_R_8 = 3 DCP_DC_LUT_INC_R_16 = 4 DCP_DC_LUT_INC_R_32 = 5 DCP_DC_LUT_INC_R_64 = 6 DCP_DC_LUT_INC_R_128 = 7 DCP_DC_LUT_INC_R_256 = 8 DCP_DC_LUT_INC_R_512 = 9 DCP_DC_LUT_INC_R = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_DATA_R_SIGNED_EN' DCP_DC_LUT_DATA_R_SIGNED_EN__enumvalues = { 0: 'DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE', 1: 'DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE', } DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0 DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 1 DCP_DC_LUT_DATA_R_SIGNED_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN' DCP_DC_LUT_DATA_R_FLOAT_POINT_EN__enumvalues = { 0: 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE', 1: 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE', } DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0 DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 1 DCP_DC_LUT_DATA_R_FLOAT_POINT_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_DC_LUT_DATA_R_FORMAT' DCP_DC_LUT_DATA_R_FORMAT__enumvalues = { 0: 'DCP_DC_LUT_DATA_R_FORMAT_U0P10', 1: 'DCP_DC_LUT_DATA_R_FORMAT_S1P10', 2: 'DCP_DC_LUT_DATA_R_FORMAT_U1P11', 3: 'DCP_DC_LUT_DATA_R_FORMAT_U0P12', } DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0 DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 1 DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 2 DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 3 DCP_DC_LUT_DATA_R_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'DCP_CRC_ENABLE' DCP_CRC_ENABLE__enumvalues = { 0: 'DCP_CRC_ENABLE_FALSE', 1: 'DCP_CRC_ENABLE_TRUE', } DCP_CRC_ENABLE_FALSE = 0 DCP_CRC_ENABLE_TRUE = 1 DCP_CRC_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_CRC_SOURCE_SEL' DCP_CRC_SOURCE_SEL__enumvalues = { 0: 'DCP_CRC_SOURCE_SEL_OUTPUT_PIX', 1: 'DCP_CRC_SOURCE_SEL_INPUT_L32', 2: 'DCP_CRC_SOURCE_SEL_INPUT_H32', 4: 'DCP_CRC_SOURCE_SEL_OUTPUT_CNTL', } DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0 DCP_CRC_SOURCE_SEL_INPUT_L32 = 1 DCP_CRC_SOURCE_SEL_INPUT_H32 = 2 DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 4 DCP_CRC_SOURCE_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCP_CRC_LINE_SEL' DCP_CRC_LINE_SEL__enumvalues = { 0: 'DCP_CRC_LINE_SEL_RESERVED', 1: 'DCP_CRC_LINE_SEL_EVEN', 2: 'DCP_CRC_LINE_SEL_ODD', 3: 'DCP_CRC_LINE_SEL_BOTH', } DCP_CRC_LINE_SEL_RESERVED = 0 DCP_CRC_LINE_SEL_EVEN = 1 DCP_CRC_LINE_SEL_ODD = 2 DCP_CRC_LINE_SEL_BOTH = 3 DCP_CRC_LINE_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_FLIP_RATE' DCP_GRPH_FLIP_RATE__enumvalues = { 0: 'DCP_GRPH_FLIP_RATE_1FRAME', 1: 'DCP_GRPH_FLIP_RATE_2FRAME', 2: 'DCP_GRPH_FLIP_RATE_3FRAME', 3: 'DCP_GRPH_FLIP_RATE_4FRAME', 4: 'DCP_GRPH_FLIP_RATE_5FRAME', 5: 'DCP_GRPH_FLIP_RATE_6FRAME', 6: 'DCP_GRPH_FLIP_RATE_7FRAME', 7: 'DCP_GRPH_FLIP_RATE_8FRAME', } DCP_GRPH_FLIP_RATE_1FRAME = 0 DCP_GRPH_FLIP_RATE_2FRAME = 1 DCP_GRPH_FLIP_RATE_3FRAME = 2 DCP_GRPH_FLIP_RATE_4FRAME = 3 DCP_GRPH_FLIP_RATE_5FRAME = 4 DCP_GRPH_FLIP_RATE_6FRAME = 5 DCP_GRPH_FLIP_RATE_7FRAME = 6 DCP_GRPH_FLIP_RATE_8FRAME = 7 DCP_GRPH_FLIP_RATE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_FLIP_RATE_ENABLE' DCP_GRPH_FLIP_RATE_ENABLE__enumvalues = { 0: 'DCP_GRPH_FLIP_RATE_ENABLE_FALSE', 1: 'DCP_GRPH_FLIP_RATE_ENABLE_TRUE', } DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0 DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 1 DCP_GRPH_FLIP_RATE_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GSL0_EN' DCP_GSL0_EN__enumvalues = { 0: 'DCP_GSL0_EN_FALSE', 1: 'DCP_GSL0_EN_TRUE', } DCP_GSL0_EN_FALSE = 0 DCP_GSL0_EN_TRUE = 1 DCP_GSL0_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GSL1_EN' DCP_GSL1_EN__enumvalues = { 0: 'DCP_GSL1_EN_FALSE', 1: 'DCP_GSL1_EN_TRUE', } DCP_GSL1_EN_FALSE = 0 DCP_GSL1_EN_TRUE = 1 DCP_GSL1_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GSL2_EN' DCP_GSL2_EN__enumvalues = { 0: 'DCP_GSL2_EN_FALSE', 1: 'DCP_GSL2_EN_TRUE', } DCP_GSL2_EN_FALSE = 0 DCP_GSL2_EN_TRUE = 1 DCP_GSL2_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GSL_MASTER_EN' DCP_GSL_MASTER_EN__enumvalues = { 0: 'DCP_GSL_MASTER_EN_FALSE', 1: 'DCP_GSL_MASTER_EN_TRUE', } DCP_GSL_MASTER_EN_FALSE = 0 DCP_GSL_MASTER_EN_TRUE = 1 DCP_GSL_MASTER_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GSL_XDMA_GROUP' DCP_GSL_XDMA_GROUP__enumvalues = { 0: 'DCP_GSL_XDMA_GROUP_VSYNC', 1: 'DCP_GSL_XDMA_GROUP_HSYNC0', 2: 'DCP_GSL_XDMA_GROUP_HSYNC1', 3: 'DCP_GSL_XDMA_GROUP_HSYNC2', } DCP_GSL_XDMA_GROUP_VSYNC = 0 DCP_GSL_XDMA_GROUP_HSYNC0 = 1 DCP_GSL_XDMA_GROUP_HSYNC1 = 2 DCP_GSL_XDMA_GROUP_HSYNC2 = 3 DCP_GSL_XDMA_GROUP = ctypes.c_uint32 # enum # values for enumeration 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN' DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__enumvalues = { 0: 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE', 1: 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE', } DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 1 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GSL_SYNC_SOURCE' DCP_GSL_SYNC_SOURCE__enumvalues = { 0: 'DCP_GSL_SYNC_SOURCE_FLIP', 1: 'DCP_GSL_SYNC_SOURCE_PHASE0', 2: 'DCP_GSL_SYNC_SOURCE_RESET', 3: 'DCP_GSL_SYNC_SOURCE_PHASE1', } DCP_GSL_SYNC_SOURCE_FLIP = 0 DCP_GSL_SYNC_SOURCE_PHASE0 = 1 DCP_GSL_SYNC_SOURCE_RESET = 2 DCP_GSL_SYNC_SOURCE_PHASE1 = 3 DCP_GSL_SYNC_SOURCE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC' DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__enumvalues = { 0: 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS', 1: 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN', } DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS = 0 DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN = 1 DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC = ctypes.c_uint32 # enum # values for enumeration 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING' DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__enumvalues = { 0: 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE', 1: 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE', } DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 1 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING = ctypes.c_uint32 # enum # values for enumeration 'DCP_TEST_DEBUG_WRITE_EN' DCP_TEST_DEBUG_WRITE_EN__enumvalues = { 0: 'DCP_TEST_DEBUG_WRITE_EN_FALSE', 1: 'DCP_TEST_DEBUG_WRITE_EN_TRUE', } DCP_TEST_DEBUG_WRITE_EN_FALSE = 0 DCP_TEST_DEBUG_WRITE_EN_TRUE = 1 DCP_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_STEREOSYNC_FLIP_EN' DCP_GRPH_STEREOSYNC_FLIP_EN__enumvalues = { 0: 'DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE', 1: 'DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE', } DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0 DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 1 DCP_GRPH_STEREOSYNC_FLIP_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_STEREOSYNC_FLIP_MODE' DCP_GRPH_STEREOSYNC_FLIP_MODE__enumvalues = { 0: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP', 1: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0', 2: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET', 3: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1', } DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0 DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 1 DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 2 DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 3 DCP_GRPH_STEREOSYNC_FLIP_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE' DCP_GRPH_STEREOSYNC_SELECT_DISABLE__enumvalues = { 0: 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE', 1: 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE', } DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0 DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 1 DCP_GRPH_STEREOSYNC_SELECT_DISABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_ROTATION_ANGLE' DCP_GRPH_ROTATION_ANGLE__enumvalues = { 0: 'DCP_GRPH_ROTATION_ANGLE_0', 1: 'DCP_GRPH_ROTATION_ANGLE_90', 2: 'DCP_GRPH_ROTATION_ANGLE_180', 3: 'DCP_GRPH_ROTATION_ANGLE_270', } DCP_GRPH_ROTATION_ANGLE_0 = 0 DCP_GRPH_ROTATION_ANGLE_90 = 1 DCP_GRPH_ROTATION_ANGLE_180 = 2 DCP_GRPH_ROTATION_ANGLE_270 = 3 DCP_GRPH_ROTATION_ANGLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN' DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__enumvalues = { 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE', 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE', } DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 1 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE' DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__enumvalues = { 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM', 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE', } DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE = 1 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_REGAMMA_MODE' DCP_GRPH_REGAMMA_MODE__enumvalues = { 0: 'DCP_GRPH_REGAMMA_MODE_BYPASS', 1: 'DCP_GRPH_REGAMMA_MODE_SRGB', 2: 'DCP_GRPH_REGAMMA_MODE_XVYCC', 3: 'DCP_GRPH_REGAMMA_MODE_PROGA', 4: 'DCP_GRPH_REGAMMA_MODE_PROGB', } DCP_GRPH_REGAMMA_MODE_BYPASS = 0 DCP_GRPH_REGAMMA_MODE_SRGB = 1 DCP_GRPH_REGAMMA_MODE_XVYCC = 2 DCP_GRPH_REGAMMA_MODE_PROGA = 3 DCP_GRPH_REGAMMA_MODE_PROGB = 4 DCP_GRPH_REGAMMA_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_ALPHA_ROUND_TRUNC_MODE' DCP_ALPHA_ROUND_TRUNC_MODE__enumvalues = { 0: 'DCP_ALPHA_ROUND_TRUNC_MODE_ROUND', 1: 'DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC', } DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0 DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 1 DCP_ALPHA_ROUND_TRUNC_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCP_CURSOR_ALPHA_BLND_ENA' DCP_CURSOR_ALPHA_BLND_ENA__enumvalues = { 0: 'DCP_CURSOR_ALPHA_BLND_ENA_FALSE', 1: 'DCP_CURSOR_ALPHA_BLND_ENA_TRUE', } DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0 DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 1 DCP_CURSOR_ALPHA_BLND_ENA = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK' DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__enumvalues = { 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE', 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE', } DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 1 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK' DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__enumvalues = { 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE', 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE', } DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 1 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK' DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__enumvalues = { 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE', 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE', } DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 1 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK' DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__enumvalues = { 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE', 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE', } DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 1 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_SURFACE_COUNTER_EN' DCP_GRPH_SURFACE_COUNTER_EN__enumvalues = { 0: 'DCP_GRPH_SURFACE_COUNTER_EN_DISABLE', 1: 'DCP_GRPH_SURFACE_COUNTER_EN_ENABLE', } DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0 DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 1 DCP_GRPH_SURFACE_COUNTER_EN = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT' DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT__enumvalues = { 0: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0', 1: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1', 2: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2', 3: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3', 4: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4', 5: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5', 6: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6', 7: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7', 8: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8', 9: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9', 10: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10', 11: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11', } DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 1 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 2 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 3 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 4 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 5 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 6 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 7 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 8 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 9 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 10 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 11 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED' DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__enumvalues = { 0: 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO', 1: 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES', } DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0 DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 1 DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR' DCP_GRPH_XDMA_FLIP_TYPE_CLEAR__enumvalues = { 0: 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE', 1: 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE', } DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE = 0 DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE = 1 DCP_GRPH_XDMA_FLIP_TYPE_CLEAR = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_XDMA_DRR_MODE_ENABLE' DCP_GRPH_XDMA_DRR_MODE_ENABLE__enumvalues = { 0: 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE', 1: 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE', } DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE = 0 DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE = 1 DCP_GRPH_XDMA_DRR_MODE_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE' DCP_GRPH_XDMA_MULTIFLIP_ENABLE__enumvalues = { 0: 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE', 1: 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE', } DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE = 0 DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE = 1 DCP_GRPH_XDMA_MULTIFLIP_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK' DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK__enumvalues = { 0: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE', 1: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE', } DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE = 0 DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE = 1 DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK = ctypes.c_uint32 # enum # values for enumeration 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK' DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK__enumvalues = { 0: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE', 1: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE', } DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE = 0 DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE = 1 DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_CVALUE_SEL' PERFCOUNTER_CVALUE_SEL__enumvalues = { 0: 'PERFCOUNTER_CVALUE_SEL_47_0', 1: 'PERFCOUNTER_CVALUE_SEL_15_0', 2: 'PERFCOUNTER_CVALUE_SEL_31_16', 3: 'PERFCOUNTER_CVALUE_SEL_47_32', 4: 'PERFCOUNTER_CVALUE_SEL_11_0', 5: 'PERFCOUNTER_CVALUE_SEL_23_12', 6: 'PERFCOUNTER_CVALUE_SEL_35_24', 7: 'PERFCOUNTER_CVALUE_SEL_47_36', } PERFCOUNTER_CVALUE_SEL_47_0 = 0 PERFCOUNTER_CVALUE_SEL_15_0 = 1 PERFCOUNTER_CVALUE_SEL_31_16 = 2 PERFCOUNTER_CVALUE_SEL_47_32 = 3 PERFCOUNTER_CVALUE_SEL_11_0 = 4 PERFCOUNTER_CVALUE_SEL_23_12 = 5 PERFCOUNTER_CVALUE_SEL_35_24 = 6 PERFCOUNTER_CVALUE_SEL_47_36 = 7 PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_INC_MODE' PERFCOUNTER_INC_MODE__enumvalues = { 0: 'PERFCOUNTER_INC_MODE_MULTI_BIT', 1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 2: 'PERFCOUNTER_INC_MODE_LSB', 3: 'PERFCOUNTER_INC_MODE_POS_EDGE', 4: 'PERFCOUNTER_INC_MODE_NEG_EDGE', } PERFCOUNTER_INC_MODE_MULTI_BIT = 0 PERFCOUNTER_INC_MODE_BOTH_EDGE = 1 PERFCOUNTER_INC_MODE_LSB = 2 PERFCOUNTER_INC_MODE_POS_EDGE = 3 PERFCOUNTER_INC_MODE_NEG_EDGE = 4 PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_HW_CNTL_SEL' PERFCOUNTER_HW_CNTL_SEL__enumvalues = { 0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', } PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0 PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1 PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_RUNEN_MODE' PERFCOUNTER_RUNEN_MODE__enumvalues = { 0: 'PERFCOUNTER_RUNEN_MODE_LEVEL', 1: 'PERFCOUNTER_RUNEN_MODE_EDGE', } PERFCOUNTER_RUNEN_MODE_LEVEL = 0 PERFCOUNTER_RUNEN_MODE_EDGE = 1 PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS' PERFCOUNTER_CNTOFF_START_DIS__enumvalues = { 0: 'PERFCOUNTER_CNTOFF_START_ENABLE', 1: 'PERFCOUNTER_CNTOFF_START_DISABLE', } PERFCOUNTER_CNTOFF_START_ENABLE = 0 PERFCOUNTER_CNTOFF_START_DISABLE = 1 PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_RESTART_EN' PERFCOUNTER_RESTART_EN__enumvalues = { 0: 'PERFCOUNTER_RESTART_DISABLE', 1: 'PERFCOUNTER_RESTART_ENABLE', } PERFCOUNTER_RESTART_DISABLE = 0 PERFCOUNTER_RESTART_ENABLE = 1 PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_INT_EN' PERFCOUNTER_INT_EN__enumvalues = { 0: 'PERFCOUNTER_INT_DISABLE', 1: 'PERFCOUNTER_INT_ENABLE', } PERFCOUNTER_INT_DISABLE = 0 PERFCOUNTER_INT_ENABLE = 1 PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_OFF_MASK' PERFCOUNTER_OFF_MASK__enumvalues = { 0: 'PERFCOUNTER_OFF_MASK_DISABLE', 1: 'PERFCOUNTER_OFF_MASK_ENABLE', } PERFCOUNTER_OFF_MASK_DISABLE = 0 PERFCOUNTER_OFF_MASK_ENABLE = 1 PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_ACTIVE' PERFCOUNTER_ACTIVE__enumvalues = { 0: 'PERFCOUNTER_IS_IDLE', 1: 'PERFCOUNTER_IS_ACTIVE', } PERFCOUNTER_IS_IDLE = 0 PERFCOUNTER_IS_ACTIVE = 1 PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_INT_TYPE' PERFCOUNTER_INT_TYPE__enumvalues = { 0: 'PERFCOUNTER_INT_TYPE_LEVEL', 1: 'PERFCOUNTER_INT_TYPE_PULSE', } PERFCOUNTER_INT_TYPE_LEVEL = 0 PERFCOUNTER_INT_TYPE_PULSE = 1 PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE' PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = { 0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', 1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', 2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', } PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0 PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1 PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2 PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_CNTL_SEL' PERFCOUNTER_CNTL_SEL__enumvalues = { 0: 'PERFCOUNTER_CNTL_SEL_0', 1: 'PERFCOUNTER_CNTL_SEL_1', 2: 'PERFCOUNTER_CNTL_SEL_2', 3: 'PERFCOUNTER_CNTL_SEL_3', 4: 'PERFCOUNTER_CNTL_SEL_4', 5: 'PERFCOUNTER_CNTL_SEL_5', 6: 'PERFCOUNTER_CNTL_SEL_6', 7: 'PERFCOUNTER_CNTL_SEL_7', } PERFCOUNTER_CNTL_SEL_0 = 0 PERFCOUNTER_CNTL_SEL_1 = 1 PERFCOUNTER_CNTL_SEL_2 = 2 PERFCOUNTER_CNTL_SEL_3 = 3 PERFCOUNTER_CNTL_SEL_4 = 4 PERFCOUNTER_CNTL_SEL_5 = 5 PERFCOUNTER_CNTL_SEL_6 = 6 PERFCOUNTER_CNTL_SEL_7 = 7 PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_CNT0_STATE' PERFCOUNTER_CNT0_STATE__enumvalues = { 0: 'PERFCOUNTER_CNT0_STATE_RESET', 1: 'PERFCOUNTER_CNT0_STATE_START', 2: 'PERFCOUNTER_CNT0_STATE_FREEZE', 3: 'PERFCOUNTER_CNT0_STATE_HW', } PERFCOUNTER_CNT0_STATE_RESET = 0 PERFCOUNTER_CNT0_STATE_START = 1 PERFCOUNTER_CNT0_STATE_FREEZE = 2 PERFCOUNTER_CNT0_STATE_HW = 3 PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_STATE_SEL0' PERFCOUNTER_STATE_SEL0__enumvalues = { 0: 'PERFCOUNTER_STATE_SEL0_GLOBAL', 1: 'PERFCOUNTER_STATE_SEL0_LOCAL', } PERFCOUNTER_STATE_SEL0_GLOBAL = 0 PERFCOUNTER_STATE_SEL0_LOCAL = 1 PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_CNT1_STATE' PERFCOUNTER_CNT1_STATE__enumvalues = { 0: 'PERFCOUNTER_CNT1_STATE_RESET', 1: 'PERFCOUNTER_CNT1_STATE_START', 2: 'PERFCOUNTER_CNT1_STATE_FREEZE', 3: 'PERFCOUNTER_CNT1_STATE_HW', } PERFCOUNTER_CNT1_STATE_RESET = 0 PERFCOUNTER_CNT1_STATE_START = 1 PERFCOUNTER_CNT1_STATE_FREEZE = 2 PERFCOUNTER_CNT1_STATE_HW = 3 PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_STATE_SEL1' PERFCOUNTER_STATE_SEL1__enumvalues = { 0: 'PERFCOUNTER_STATE_SEL1_GLOBAL', 1: 'PERFCOUNTER_STATE_SEL1_LOCAL', } PERFCOUNTER_STATE_SEL1_GLOBAL = 0 PERFCOUNTER_STATE_SEL1_LOCAL = 1 PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_CNT2_STATE' PERFCOUNTER_CNT2_STATE__enumvalues = { 0: 'PERFCOUNTER_CNT2_STATE_RESET', 1: 'PERFCOUNTER_CNT2_STATE_START', 2: 'PERFCOUNTER_CNT2_STATE_FREEZE', 3: 'PERFCOUNTER_CNT2_STATE_HW', } PERFCOUNTER_CNT2_STATE_RESET = 0 PERFCOUNTER_CNT2_STATE_START = 1 PERFCOUNTER_CNT2_STATE_FREEZE = 2 PERFCOUNTER_CNT2_STATE_HW = 3 PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_STATE_SEL2' PERFCOUNTER_STATE_SEL2__enumvalues = { 0: 'PERFCOUNTER_STATE_SEL2_GLOBAL', 1: 'PERFCOUNTER_STATE_SEL2_LOCAL', } PERFCOUNTER_STATE_SEL2_GLOBAL = 0 PERFCOUNTER_STATE_SEL2_LOCAL = 1 PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_CNT3_STATE' PERFCOUNTER_CNT3_STATE__enumvalues = { 0: 'PERFCOUNTER_CNT3_STATE_RESET', 1: 'PERFCOUNTER_CNT3_STATE_START', 2: 'PERFCOUNTER_CNT3_STATE_FREEZE', 3: 'PERFCOUNTER_CNT3_STATE_HW', } PERFCOUNTER_CNT3_STATE_RESET = 0 PERFCOUNTER_CNT3_STATE_START = 1 PERFCOUNTER_CNT3_STATE_FREEZE = 2 PERFCOUNTER_CNT3_STATE_HW = 3 PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_STATE_SEL3' PERFCOUNTER_STATE_SEL3__enumvalues = { 0: 'PERFCOUNTER_STATE_SEL3_GLOBAL', 1: 'PERFCOUNTER_STATE_SEL3_LOCAL', } PERFCOUNTER_STATE_SEL3_GLOBAL = 0 PERFCOUNTER_STATE_SEL3_LOCAL = 1 PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_CNT4_STATE' PERFCOUNTER_CNT4_STATE__enumvalues = { 0: 'PERFCOUNTER_CNT4_STATE_RESET', 1: 'PERFCOUNTER_CNT4_STATE_START', 2: 'PERFCOUNTER_CNT4_STATE_FREEZE', 3: 'PERFCOUNTER_CNT4_STATE_HW', } PERFCOUNTER_CNT4_STATE_RESET = 0 PERFCOUNTER_CNT4_STATE_START = 1 PERFCOUNTER_CNT4_STATE_FREEZE = 2 PERFCOUNTER_CNT4_STATE_HW = 3 PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_STATE_SEL4' PERFCOUNTER_STATE_SEL4__enumvalues = { 0: 'PERFCOUNTER_STATE_SEL4_GLOBAL', 1: 'PERFCOUNTER_STATE_SEL4_LOCAL', } PERFCOUNTER_STATE_SEL4_GLOBAL = 0 PERFCOUNTER_STATE_SEL4_LOCAL = 1 PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_CNT5_STATE' PERFCOUNTER_CNT5_STATE__enumvalues = { 0: 'PERFCOUNTER_CNT5_STATE_RESET', 1: 'PERFCOUNTER_CNT5_STATE_START', 2: 'PERFCOUNTER_CNT5_STATE_FREEZE', 3: 'PERFCOUNTER_CNT5_STATE_HW', } PERFCOUNTER_CNT5_STATE_RESET = 0 PERFCOUNTER_CNT5_STATE_START = 1 PERFCOUNTER_CNT5_STATE_FREEZE = 2 PERFCOUNTER_CNT5_STATE_HW = 3 PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_STATE_SEL5' PERFCOUNTER_STATE_SEL5__enumvalues = { 0: 'PERFCOUNTER_STATE_SEL5_GLOBAL', 1: 'PERFCOUNTER_STATE_SEL5_LOCAL', } PERFCOUNTER_STATE_SEL5_GLOBAL = 0 PERFCOUNTER_STATE_SEL5_LOCAL = 1 PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_CNT6_STATE' PERFCOUNTER_CNT6_STATE__enumvalues = { 0: 'PERFCOUNTER_CNT6_STATE_RESET', 1: 'PERFCOUNTER_CNT6_STATE_START', 2: 'PERFCOUNTER_CNT6_STATE_FREEZE', 3: 'PERFCOUNTER_CNT6_STATE_HW', } PERFCOUNTER_CNT6_STATE_RESET = 0 PERFCOUNTER_CNT6_STATE_START = 1 PERFCOUNTER_CNT6_STATE_FREEZE = 2 PERFCOUNTER_CNT6_STATE_HW = 3 PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_STATE_SEL6' PERFCOUNTER_STATE_SEL6__enumvalues = { 0: 'PERFCOUNTER_STATE_SEL6_GLOBAL', 1: 'PERFCOUNTER_STATE_SEL6_LOCAL', } PERFCOUNTER_STATE_SEL6_GLOBAL = 0 PERFCOUNTER_STATE_SEL6_LOCAL = 1 PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_CNT7_STATE' PERFCOUNTER_CNT7_STATE__enumvalues = { 0: 'PERFCOUNTER_CNT7_STATE_RESET', 1: 'PERFCOUNTER_CNT7_STATE_START', 2: 'PERFCOUNTER_CNT7_STATE_FREEZE', 3: 'PERFCOUNTER_CNT7_STATE_HW', } PERFCOUNTER_CNT7_STATE_RESET = 0 PERFCOUNTER_CNT7_STATE_START = 1 PERFCOUNTER_CNT7_STATE_FREEZE = 2 PERFCOUNTER_CNT7_STATE_HW = 3 PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum # values for enumeration 'PERFCOUNTER_STATE_SEL7' PERFCOUNTER_STATE_SEL7__enumvalues = { 0: 'PERFCOUNTER_STATE_SEL7_GLOBAL', 1: 'PERFCOUNTER_STATE_SEL7_LOCAL', } PERFCOUNTER_STATE_SEL7_GLOBAL = 0 PERFCOUNTER_STATE_SEL7_LOCAL = 1 PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum # values for enumeration 'PERFMON_STATE' PERFMON_STATE__enumvalues = { 0: 'PERFMON_STATE_RESET', 1: 'PERFMON_STATE_START', 2: 'PERFMON_STATE_FREEZE', 3: 'PERFMON_STATE_HW', } PERFMON_STATE_RESET = 0 PERFMON_STATE_START = 1 PERFMON_STATE_FREEZE = 2 PERFMON_STATE_HW = 3 PERFMON_STATE = ctypes.c_uint32 # enum # values for enumeration 'PERFMON_CNTOFF_AND_OR' PERFMON_CNTOFF_AND_OR__enumvalues = { 0: 'PERFMON_CNTOFF_OR', 1: 'PERFMON_CNTOFF_AND', } PERFMON_CNTOFF_OR = 0 PERFMON_CNTOFF_AND = 1 PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum # values for enumeration 'PERFMON_CNTOFF_INT_EN' PERFMON_CNTOFF_INT_EN__enumvalues = { 0: 'PERFMON_CNTOFF_INT_DISABLE', 1: 'PERFMON_CNTOFF_INT_ENABLE', } PERFMON_CNTOFF_INT_DISABLE = 0 PERFMON_CNTOFF_INT_ENABLE = 1 PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum # values for enumeration 'PERFMON_CNTOFF_INT_TYPE' PERFMON_CNTOFF_INT_TYPE__enumvalues = { 0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 1: 'PERFMON_CNTOFF_INT_TYPE_PULSE', } PERFMON_CNTOFF_INT_TYPE_LEVEL = 0 PERFMON_CNTOFF_INT_TYPE_PULSE = 1 PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'SCL_C_RAM_TAP_PAIR_IDX' SCL_C_RAM_TAP_PAIR_IDX__enumvalues = { 0: 'SCL_C_RAM_TAP_PAIR_ID0', 1: 'SCL_C_RAM_TAP_PAIR_ID1', 2: 'SCL_C_RAM_TAP_PAIR_ID2', 3: 'SCL_C_RAM_TAP_PAIR_ID3', 4: 'SCL_C_RAM_TAP_PAIR_ID4', } SCL_C_RAM_TAP_PAIR_ID0 = 0 SCL_C_RAM_TAP_PAIR_ID1 = 1 SCL_C_RAM_TAP_PAIR_ID2 = 2 SCL_C_RAM_TAP_PAIR_ID3 = 3 SCL_C_RAM_TAP_PAIR_ID4 = 4 SCL_C_RAM_TAP_PAIR_IDX = ctypes.c_uint32 # enum # values for enumeration 'SCL_C_RAM_PHASE' SCL_C_RAM_PHASE__enumvalues = { 0: 'SCL_C_RAM_PHASE_0', 1: 'SCL_C_RAM_PHASE_1', 2: 'SCL_C_RAM_PHASE_2', 3: 'SCL_C_RAM_PHASE_3', 4: 'SCL_C_RAM_PHASE_4', 5: 'SCL_C_RAM_PHASE_5', 6: 'SCL_C_RAM_PHASE_6', 7: 'SCL_C_RAM_PHASE_7', 8: 'SCL_C_RAM_PHASE_8', } SCL_C_RAM_PHASE_0 = 0 SCL_C_RAM_PHASE_1 = 1 SCL_C_RAM_PHASE_2 = 2 SCL_C_RAM_PHASE_3 = 3 SCL_C_RAM_PHASE_4 = 4 SCL_C_RAM_PHASE_5 = 5 SCL_C_RAM_PHASE_6 = 6 SCL_C_RAM_PHASE_7 = 7 SCL_C_RAM_PHASE_8 = 8 SCL_C_RAM_PHASE = ctypes.c_uint32 # enum # values for enumeration 'SCL_C_RAM_FILTER_TYPE' SCL_C_RAM_FILTER_TYPE__enumvalues = { 0: 'SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT', 1: 'SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT', 2: 'SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT', 3: 'SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT', } SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0 SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 1 SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 2 SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 3 SCL_C_RAM_FILTER_TYPE = ctypes.c_uint32 # enum # values for enumeration 'SCL_MODE_SEL' SCL_MODE_SEL__enumvalues = { 0: 'SCL_MODE_RGB_BYPASS', 1: 'SCL_MODE_RGB_SCALING', 2: 'SCL_MODE_YCBCR_SCALING', 3: 'SCL_MODE_YCBCR_BYPASS', } SCL_MODE_RGB_BYPASS = 0 SCL_MODE_RGB_SCALING = 1 SCL_MODE_YCBCR_SCALING = 2 SCL_MODE_YCBCR_BYPASS = 3 SCL_MODE_SEL = ctypes.c_uint32 # enum # values for enumeration 'SCL_PSCL_EN' SCL_PSCL_EN__enumvalues = { 0: 'SCL_PSCL_DISABLE', 1: 'SCL_PSCL_ENANBLE', } SCL_PSCL_DISABLE = 0 SCL_PSCL_ENANBLE = 1 SCL_PSCL_EN = ctypes.c_uint32 # enum # values for enumeration 'SCL_V_NUM_OF_TAPS' SCL_V_NUM_OF_TAPS__enumvalues = { 0: 'SCL_V_NUM_OF_TAPS_1', 1: 'SCL_V_NUM_OF_TAPS_2', 2: 'SCL_V_NUM_OF_TAPS_3', 3: 'SCL_V_NUM_OF_TAPS_4', 4: 'SCL_V_NUM_OF_TAPS_5', 5: 'SCL_V_NUM_OF_TAPS_6', } SCL_V_NUM_OF_TAPS_1 = 0 SCL_V_NUM_OF_TAPS_2 = 1 SCL_V_NUM_OF_TAPS_3 = 2 SCL_V_NUM_OF_TAPS_4 = 3 SCL_V_NUM_OF_TAPS_5 = 4 SCL_V_NUM_OF_TAPS_6 = 5 SCL_V_NUM_OF_TAPS = ctypes.c_uint32 # enum # values for enumeration 'SCL_H_NUM_OF_TAPS' SCL_H_NUM_OF_TAPS__enumvalues = { 0: 'SCL_H_NUM_OF_TAPS_1', 1: 'SCL_H_NUM_OF_TAPS_2', 3: 'SCL_H_NUM_OF_TAPS_4', 5: 'SCL_H_NUM_OF_TAPS_6', 7: 'SCL_H_NUM_OF_TAPS_8', 9: 'SCL_H_NUM_OF_TAPS_10', } SCL_H_NUM_OF_TAPS_1 = 0 SCL_H_NUM_OF_TAPS_2 = 1 SCL_H_NUM_OF_TAPS_4 = 3 SCL_H_NUM_OF_TAPS_6 = 5 SCL_H_NUM_OF_TAPS_8 = 7 SCL_H_NUM_OF_TAPS_10 = 9 SCL_H_NUM_OF_TAPS = ctypes.c_uint32 # enum # values for enumeration 'SCL_BOUNDARY_MODE' SCL_BOUNDARY_MODE__enumvalues = { 0: 'SCL_BOUNDARY_MODE_BLACK', 1: 'SCL_BOUNDARY_MODE_EDGE', } SCL_BOUNDARY_MODE_BLACK = 0 SCL_BOUNDARY_MODE_EDGE = 1 SCL_BOUNDARY_MODE = ctypes.c_uint32 # enum # values for enumeration 'SCL_EARLY_EOL_MOD' SCL_EARLY_EOL_MOD__enumvalues = { 0: 'SCL_EARLY_EOL_MODE_CRTC', 1: 'SCL_EARLY_EOL_MODE_INTERNAL', } SCL_EARLY_EOL_MODE_CRTC = 0 SCL_EARLY_EOL_MODE_INTERNAL = 1 SCL_EARLY_EOL_MOD = ctypes.c_uint32 # enum # values for enumeration 'SCL_BYPASS_MODE' SCL_BYPASS_MODE__enumvalues = { 0: 'SCL_BYPASS_MODE_MC_MR', 1: 'SCL_BYPASS_MODE_AC_NR', 2: 'SCL_BYPASS_MODE_AC_AR', 3: 'SCL_BYPASS_MODE_RESERVED', } SCL_BYPASS_MODE_MC_MR = 0 SCL_BYPASS_MODE_AC_NR = 1 SCL_BYPASS_MODE_AC_AR = 2 SCL_BYPASS_MODE_RESERVED = 3 SCL_BYPASS_MODE = ctypes.c_uint32 # enum # values for enumeration 'SCL_V_MANUAL_REPLICATE_FACTOR' SCL_V_MANUAL_REPLICATE_FACTOR__enumvalues = { 0: 'SCL_V_MANUAL_REPLICATE_FACTOR_1', 1: 'SCL_V_MANUAL_REPLICATE_FACTOR_2', 2: 'SCL_V_MANUAL_REPLICATE_FACTOR_3', 3: 'SCL_V_MANUAL_REPLICATE_FACTOR_4', 4: 'SCL_V_MANUAL_REPLICATE_FACTOR_5', 5: 'SCL_V_MANUAL_REPLICATE_FACTOR_6', 6: 'SCL_V_MANUAL_REPLICATE_FACTOR_7', 7: 'SCL_V_MANUAL_REPLICATE_FACTOR_8', 8: 'SCL_V_MANUAL_REPLICATE_FACTOR_9', 9: 'SCL_V_MANUAL_REPLICATE_FACTOR_10', 10: 'SCL_V_MANUAL_REPLICATE_FACTOR_11', 11: 'SCL_V_MANUAL_REPLICATE_FACTOR_12', 12: 'SCL_V_MANUAL_REPLICATE_FACTOR_13', 13: 'SCL_V_MANUAL_REPLICATE_FACTOR_14', 14: 'SCL_V_MANUAL_REPLICATE_FACTOR_15', 15: 'SCL_V_MANUAL_REPLICATE_FACTOR_16', } SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0 SCL_V_MANUAL_REPLICATE_FACTOR_2 = 1 SCL_V_MANUAL_REPLICATE_FACTOR_3 = 2 SCL_V_MANUAL_REPLICATE_FACTOR_4 = 3 SCL_V_MANUAL_REPLICATE_FACTOR_5 = 4 SCL_V_MANUAL_REPLICATE_FACTOR_6 = 5 SCL_V_MANUAL_REPLICATE_FACTOR_7 = 6 SCL_V_MANUAL_REPLICATE_FACTOR_8 = 7 SCL_V_MANUAL_REPLICATE_FACTOR_9 = 8 SCL_V_MANUAL_REPLICATE_FACTOR_10 = 9 SCL_V_MANUAL_REPLICATE_FACTOR_11 = 10 SCL_V_MANUAL_REPLICATE_FACTOR_12 = 11 SCL_V_MANUAL_REPLICATE_FACTOR_13 = 12 SCL_V_MANUAL_REPLICATE_FACTOR_14 = 13 SCL_V_MANUAL_REPLICATE_FACTOR_15 = 14 SCL_V_MANUAL_REPLICATE_FACTOR_16 = 15 SCL_V_MANUAL_REPLICATE_FACTOR = ctypes.c_uint32 # enum # values for enumeration 'SCL_H_MANUAL_REPLICATE_FACTOR' SCL_H_MANUAL_REPLICATE_FACTOR__enumvalues = { 0: 'SCL_H_MANUAL_REPLICATE_FACTOR_1', 1: 'SCL_H_MANUAL_REPLICATE_FACTOR_2', 2: 'SCL_H_MANUAL_REPLICATE_FACTOR_3', 3: 'SCL_H_MANUAL_REPLICATE_FACTOR_4', 4: 'SCL_H_MANUAL_REPLICATE_FACTOR_5', 5: 'SCL_H_MANUAL_REPLICATE_FACTOR_6', 6: 'SCL_H_MANUAL_REPLICATE_FACTOR_7', 7: 'SCL_H_MANUAL_REPLICATE_FACTOR_8', 8: 'SCL_H_MANUAL_REPLICATE_FACTOR_9', 9: 'SCL_H_MANUAL_REPLICATE_FACTOR_10', 10: 'SCL_H_MANUAL_REPLICATE_FACTOR_11', 11: 'SCL_H_MANUAL_REPLICATE_FACTOR_12', 12: 'SCL_H_MANUAL_REPLICATE_FACTOR_13', 13: 'SCL_H_MANUAL_REPLICATE_FACTOR_14', 14: 'SCL_H_MANUAL_REPLICATE_FACTOR_15', 15: 'SCL_H_MANUAL_REPLICATE_FACTOR_16', } SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0 SCL_H_MANUAL_REPLICATE_FACTOR_2 = 1 SCL_H_MANUAL_REPLICATE_FACTOR_3 = 2 SCL_H_MANUAL_REPLICATE_FACTOR_4 = 3 SCL_H_MANUAL_REPLICATE_FACTOR_5 = 4 SCL_H_MANUAL_REPLICATE_FACTOR_6 = 5 SCL_H_MANUAL_REPLICATE_FACTOR_7 = 6 SCL_H_MANUAL_REPLICATE_FACTOR_8 = 7 SCL_H_MANUAL_REPLICATE_FACTOR_9 = 8 SCL_H_MANUAL_REPLICATE_FACTOR_10 = 9 SCL_H_MANUAL_REPLICATE_FACTOR_11 = 10 SCL_H_MANUAL_REPLICATE_FACTOR_12 = 11 SCL_H_MANUAL_REPLICATE_FACTOR_13 = 12 SCL_H_MANUAL_REPLICATE_FACTOR_14 = 13 SCL_H_MANUAL_REPLICATE_FACTOR_15 = 14 SCL_H_MANUAL_REPLICATE_FACTOR_16 = 15 SCL_H_MANUAL_REPLICATE_FACTOR = ctypes.c_uint32 # enum # values for enumeration 'SCL_V_CALC_AUTO_RATIO_EN' SCL_V_CALC_AUTO_RATIO_EN__enumvalues = { 0: 'SCL_V_CALC_AUTO_RATIO_DISABLE', 1: 'SCL_V_CALC_AUTO_RATIO_ENABLE', } SCL_V_CALC_AUTO_RATIO_DISABLE = 0 SCL_V_CALC_AUTO_RATIO_ENABLE = 1 SCL_V_CALC_AUTO_RATIO_EN = ctypes.c_uint32 # enum # values for enumeration 'SCL_H_CALC_AUTO_RATIO_EN' SCL_H_CALC_AUTO_RATIO_EN__enumvalues = { 0: 'SCL_H_CALC_AUTO_RATIO_DISABLE', 1: 'SCL_H_CALC_AUTO_RATIO_ENABLE', } SCL_H_CALC_AUTO_RATIO_DISABLE = 0 SCL_H_CALC_AUTO_RATIO_ENABLE = 1 SCL_H_CALC_AUTO_RATIO_EN = ctypes.c_uint32 # enum # values for enumeration 'SCL_H_FILTER_PICK_NEAREST' SCL_H_FILTER_PICK_NEAREST__enumvalues = { 0: 'SCL_H_FILTER_PICK_NEAREST_DISABLE', 1: 'SCL_H_FILTER_PICK_NEAREST_ENABLE', } SCL_H_FILTER_PICK_NEAREST_DISABLE = 0 SCL_H_FILTER_PICK_NEAREST_ENABLE = 1 SCL_H_FILTER_PICK_NEAREST = ctypes.c_uint32 # enum # values for enumeration 'SCL_H_2TAP_HARDCODE_COEF_EN' SCL_H_2TAP_HARDCODE_COEF_EN__enumvalues = { 0: 'SCL_H_2TAP_HARDCODE_COEF_DISABLE', 1: 'SCL_H_2TAP_HARDCODE_COEF_ENABLE', } SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0 SCL_H_2TAP_HARDCODE_COEF_ENABLE = 1 SCL_H_2TAP_HARDCODE_COEF_EN = ctypes.c_uint32 # enum # values for enumeration 'SCL_V_FILTER_PICK_NEAREST' SCL_V_FILTER_PICK_NEAREST__enumvalues = { 0: 'SCL_V_FILTER_PICK_NEAREST_DISABLE', 1: 'SCL_V_FILTER_PICK_NEAREST_ENABLE', } SCL_V_FILTER_PICK_NEAREST_DISABLE = 0 SCL_V_FILTER_PICK_NEAREST_ENABLE = 1 SCL_V_FILTER_PICK_NEAREST = ctypes.c_uint32 # enum # values for enumeration 'SCL_V_2TAP_HARDCODE_COEF_EN' SCL_V_2TAP_HARDCODE_COEF_EN__enumvalues = { 0: 'SCL_V_2TAP_HARDCODE_COEF_DISABLE', 1: 'SCL_V_2TAP_HARDCODE_COEF_ENABLE', } SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0 SCL_V_2TAP_HARDCODE_COEF_ENABLE = 1 SCL_V_2TAP_HARDCODE_COEF_EN = ctypes.c_uint32 # enum # values for enumeration 'SCL_UPDATE_TAKEN' SCL_UPDATE_TAKEN__enumvalues = { 0: 'SCL_UPDATE_TAKEN_NO', 1: 'SCL_UPDATE_TAKEN_YES', } SCL_UPDATE_TAKEN_NO = 0 SCL_UPDATE_TAKEN_YES = 1 SCL_UPDATE_TAKEN = ctypes.c_uint32 # enum # values for enumeration 'SCL_UPDATE_LOCK' SCL_UPDATE_LOCK__enumvalues = { 0: 'SCL_UPDATE_UNLOCKED', 1: 'SCL_UPDATE_LOCKED', } SCL_UPDATE_UNLOCKED = 0 SCL_UPDATE_LOCKED = 1 SCL_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'SCL_COEF_UPDATE_COMPLETE' SCL_COEF_UPDATE_COMPLETE__enumvalues = { 0: 'SCL_COEF_UPDATE_NOT_COMPLETED', 1: 'SCL_COEF_UPDATE_COMPLETED', } SCL_COEF_UPDATE_NOT_COMPLETED = 0 SCL_COEF_UPDATE_COMPLETED = 1 SCL_COEF_UPDATE_COMPLETE = ctypes.c_uint32 # enum # values for enumeration 'SCL_HF_SHARP_SCALE_FACTOR' SCL_HF_SHARP_SCALE_FACTOR__enumvalues = { 0: 'SCL_HF_SHARP_SCALE_FACTOR_0', 1: 'SCL_HF_SHARP_SCALE_FACTOR_1', 2: 'SCL_HF_SHARP_SCALE_FACTOR_2', 3: 'SCL_HF_SHARP_SCALE_FACTOR_3', 4: 'SCL_HF_SHARP_SCALE_FACTOR_4', 5: 'SCL_HF_SHARP_SCALE_FACTOR_5', 6: 'SCL_HF_SHARP_SCALE_FACTOR_6', 7: 'SCL_HF_SHARP_SCALE_FACTOR_7', } SCL_HF_SHARP_SCALE_FACTOR_0 = 0 SCL_HF_SHARP_SCALE_FACTOR_1 = 1 SCL_HF_SHARP_SCALE_FACTOR_2 = 2 SCL_HF_SHARP_SCALE_FACTOR_3 = 3 SCL_HF_SHARP_SCALE_FACTOR_4 = 4 SCL_HF_SHARP_SCALE_FACTOR_5 = 5 SCL_HF_SHARP_SCALE_FACTOR_6 = 6 SCL_HF_SHARP_SCALE_FACTOR_7 = 7 SCL_HF_SHARP_SCALE_FACTOR = ctypes.c_uint32 # enum # values for enumeration 'SCL_HF_SHARP_EN' SCL_HF_SHARP_EN__enumvalues = { 0: 'SCL_HF_SHARP_DISABLE', 1: 'SCL_HF_SHARP_ENABLE', } SCL_HF_SHARP_DISABLE = 0 SCL_HF_SHARP_ENABLE = 1 SCL_HF_SHARP_EN = ctypes.c_uint32 # enum # values for enumeration 'SCL_VF_SHARP_SCALE_FACTOR' SCL_VF_SHARP_SCALE_FACTOR__enumvalues = { 0: 'SCL_VF_SHARP_SCALE_FACTOR_0', 1: 'SCL_VF_SHARP_SCALE_FACTOR_1', 2: 'SCL_VF_SHARP_SCALE_FACTOR_2', 3: 'SCL_VF_SHARP_SCALE_FACTOR_3', 4: 'SCL_VF_SHARP_SCALE_FACTOR_4', 5: 'SCL_VF_SHARP_SCALE_FACTOR_5', 6: 'SCL_VF_SHARP_SCALE_FACTOR_6', 7: 'SCL_VF_SHARP_SCALE_FACTOR_7', } SCL_VF_SHARP_SCALE_FACTOR_0 = 0 SCL_VF_SHARP_SCALE_FACTOR_1 = 1 SCL_VF_SHARP_SCALE_FACTOR_2 = 2 SCL_VF_SHARP_SCALE_FACTOR_3 = 3 SCL_VF_SHARP_SCALE_FACTOR_4 = 4 SCL_VF_SHARP_SCALE_FACTOR_5 = 5 SCL_VF_SHARP_SCALE_FACTOR_6 = 6 SCL_VF_SHARP_SCALE_FACTOR_7 = 7 SCL_VF_SHARP_SCALE_FACTOR = ctypes.c_uint32 # enum # values for enumeration 'SCL_VF_SHARP_EN' SCL_VF_SHARP_EN__enumvalues = { 0: 'SCL_VF_SHARP_DISABLE', 1: 'SCL_VF_SHARP_ENABLE', } SCL_VF_SHARP_DISABLE = 0 SCL_VF_SHARP_ENABLE = 1 SCL_VF_SHARP_EN = ctypes.c_uint32 # enum # values for enumeration 'SCL_ALU_DISABLE' SCL_ALU_DISABLE__enumvalues = { 0: 'SCL_ALU_ENABLED', 1: 'SCL_ALU_DISABLED', } SCL_ALU_ENABLED = 0 SCL_ALU_DISABLED = 1 SCL_ALU_DISABLE = ctypes.c_uint32 # enum # values for enumeration 'SCL_HOST_CONFLICT_MASK' SCL_HOST_CONFLICT_MASK__enumvalues = { 0: 'SCL_HOST_CONFLICT_DISABLE_INTERRUPT', 1: 'SCL_HOST_CONFLICT_ENABLE_INTERRUPT', } SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0 SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 1 SCL_HOST_CONFLICT_MASK = ctypes.c_uint32 # enum # values for enumeration 'SCL_SCL_MODE_CHANGE_MASK' SCL_SCL_MODE_CHANGE_MASK__enumvalues = { 0: 'SCL_MODE_CHANGE_DISABLE_INTERRUPT', 1: 'SCL_MODE_CHANGE_ENABLE_INTERRUPT', } SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0 SCL_MODE_CHANGE_ENABLE_INTERRUPT = 1 SCL_SCL_MODE_CHANGE_MASK = ctypes.c_uint32 # enum # values for enumeration 'SCLV_MODE_SEL' SCLV_MODE_SEL__enumvalues = { 0: 'SCLV_MODE_RGB_BYPASS', 1: 'SCLV_MODE_RGB_SCALING', 2: 'SCLV_MODE_YCBCR_SCALING', 3: 'SCLV_MODE_YCBCR_BYPASS', } SCLV_MODE_RGB_BYPASS = 0 SCLV_MODE_RGB_SCALING = 1 SCLV_MODE_YCBCR_SCALING = 2 SCLV_MODE_YCBCR_BYPASS = 3 SCLV_MODE_SEL = ctypes.c_uint32 # enum # values for enumeration 'SCLV_INTERLACE_SOURCE' SCLV_INTERLACE_SOURCE__enumvalues = { 0: 'INTERLACE_SOURCE_PROGRESSIVE', 1: 'INTERLACE_SOURCE_INTERLEAVE', 2: 'INTERLACE_SOURCE_STACK', } INTERLACE_SOURCE_PROGRESSIVE = 0 INTERLACE_SOURCE_INTERLEAVE = 1 INTERLACE_SOURCE_STACK = 2 SCLV_INTERLACE_SOURCE = ctypes.c_uint32 # enum # values for enumeration 'SCLV_UPDATE_LOCK' SCLV_UPDATE_LOCK__enumvalues = { 0: 'UPDATE_UNLOCKED', 1: 'UPDATE_LOCKED', } UPDATE_UNLOCKED = 0 UPDATE_LOCKED = 1 SCLV_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'SCLV_COEF_UPDATE_COMPLETE' SCLV_COEF_UPDATE_COMPLETE__enumvalues = { 0: 'COEF_UPDATE_NOT_COMPLETE', 1: 'COEF_UPDATE_COMPLETE', } COEF_UPDATE_NOT_COMPLETE = 0 COEF_UPDATE_COMPLETE = 1 SCLV_COEF_UPDATE_COMPLETE = ctypes.c_uint32 # enum # values for enumeration 'DPRX_SD_PIXEL_ENCODING' DPRX_SD_PIXEL_ENCODING__enumvalues = { 0: 'PIXEL_FORMAT_RGB_444', 1: 'PIXEL_FORMAT_YCBCR_444', 2: 'PIXEL_FORMAT_YCBCR_422', 3: 'PIXEL_FORMAT_Y_ONLY', } PIXEL_FORMAT_RGB_444 = 0 PIXEL_FORMAT_YCBCR_444 = 1 PIXEL_FORMAT_YCBCR_422 = 2 PIXEL_FORMAT_Y_ONLY = 3 DPRX_SD_PIXEL_ENCODING = ctypes.c_uint32 # enum # values for enumeration 'DPRX_SD_COMPONENT_DEPTH' DPRX_SD_COMPONENT_DEPTH__enumvalues = { 0: 'COMPONENT_DEPTH_6BPC', 1: 'COMPONENT_DEPTH_8BPC', 2: 'COMPONENT_DEPTH_10BPC', 3: 'COMPONENT_DEPTH_12BPC', 4: 'COMPONENT_DEPTH_16BPC', } COMPONENT_DEPTH_6BPC = 0 COMPONENT_DEPTH_8BPC = 1 COMPONENT_DEPTH_10BPC = 2 COMPONENT_DEPTH_12BPC = 3 COMPONENT_DEPTH_16BPC = 4 DPRX_SD_COMPONENT_DEPTH = ctypes.c_uint32 # enum # values for enumeration 'AZ_LATENCY_COUNTER_CONTROL' AZ_LATENCY_COUNTER_CONTROL__enumvalues = { 0: 'AZ_LATENCY_COUNTER_NO_RESET', 1: 'AZ_LATENCY_COUNTER_RESET_DONE', } AZ_LATENCY_COUNTER_NO_RESET = 0 AZ_LATENCY_COUNTER_RESET_DONE = 1 AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum # values for enumeration 'BLND_CONTROL_BLND_MODE' BLND_CONTROL_BLND_MODE__enumvalues = { 0: 'BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', 1: 'BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', 2: 'BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', 3: 'BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', } BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0 BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 1 BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 2 BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 3 BLND_CONTROL_BLND_MODE = ctypes.c_uint32 # enum # values for enumeration 'BLND_CONTROL_BLND_STEREO_TYPE' BLND_CONTROL_BLND_STEREO_TYPE__enumvalues = { 0: 'BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', 1: 'BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', 2: 'BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', 3: 'BLND_CONTROL_BLND_STEREO_TYPE_UNUSED', } BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0 BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 1 BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 2 BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 3 BLND_CONTROL_BLND_STEREO_TYPE = ctypes.c_uint32 # enum # values for enumeration 'BLND_CONTROL_BLND_STEREO_POLARITY' BLND_CONTROL_BLND_STEREO_POLARITY__enumvalues = { 0: 'BLND_CONTROL_BLND_STEREO_POLARITY_LOW', 1: 'BLND_CONTROL_BLND_STEREO_POLARITY_HIGH', } BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0 BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 1 BLND_CONTROL_BLND_STEREO_POLARITY = ctypes.c_uint32 # enum # values for enumeration 'BLND_CONTROL_BLND_FEEDTHROUGH_EN' BLND_CONTROL_BLND_FEEDTHROUGH_EN__enumvalues = { 0: 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', 1: 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', } BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0 BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 1 BLND_CONTROL_BLND_FEEDTHROUGH_EN = ctypes.c_uint32 # enum # values for enumeration 'BLND_CONTROL_BLND_ALPHA_MODE' BLND_CONTROL_BLND_ALPHA_MODE__enumvalues = { 0: 'BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', 1: 'BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', 2: 'BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', 3: 'BLND_CONTROL_BLND_ALPHA_MODE_UNUSED', } BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0 BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 2 BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 3 BLND_CONTROL_BLND_ALPHA_MODE = ctypes.c_uint32 # enum # values for enumeration 'BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY' BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY__enumvalues = { 0: 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE', 1: 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE', } BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE = 0 BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE = 1 BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum # values for enumeration 'BLND_CONTROL_BLND_MULTIPLIED_MODE' BLND_CONTROL_BLND_MULTIPLIED_MODE__enumvalues = { 0: 'BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE', 1: 'BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE', } BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0 BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 1 BLND_CONTROL_BLND_MULTIPLIED_MODE = ctypes.c_uint32 # enum # values for enumeration 'BLND_SM_CONTROL2_SM_MODE' BLND_SM_CONTROL2_SM_MODE__enumvalues = { 0: 'BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE', 2: 'BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', 4: 'BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', 6: 'BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', } BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0 BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 2 BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 4 BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 BLND_SM_CONTROL2_SM_MODE = ctypes.c_uint32 # enum # values for enumeration 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE' BLND_SM_CONTROL2_SM_FRAME_ALTERNATE__enumvalues = { 0: 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', 1: 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', } BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0 BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 1 BLND_SM_CONTROL2_SM_FRAME_ALTERNATE = ctypes.c_uint32 # enum # values for enumeration 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE' BLND_SM_CONTROL2_SM_FIELD_ALTERNATE__enumvalues = { 0: 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', 1: 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', } BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0 BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 1 BLND_SM_CONTROL2_SM_FIELD_ALTERNATE = ctypes.c_uint32 # enum # values for enumeration 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL' BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL__enumvalues = { 0: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', 1: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', 2: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', 3: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', } BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum # values for enumeration 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL' BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL__enumvalues = { 0: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', 1: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', 2: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', 3: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', } BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum # values for enumeration 'BLND_CONTROL2_PTI_ENABLE' BLND_CONTROL2_PTI_ENABLE__enumvalues = { 0: 'BLND_CONTROL2_PTI_ENABLE_FALSE', 1: 'BLND_CONTROL2_PTI_ENABLE_TRUE', } BLND_CONTROL2_PTI_ENABLE_FALSE = 0 BLND_CONTROL2_PTI_ENABLE_TRUE = 1 BLND_CONTROL2_PTI_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN' BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN__enumvalues = { 0: 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', 1: 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', } BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0 BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 1 BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN = ctypes.c_uint32 # enum # values for enumeration 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN' BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN__enumvalues = { 0: 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', 1: 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', } BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0 BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 1 BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN = ctypes.c_uint32 # enum # values for enumeration 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK' BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK__enumvalues = { 0: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', 1: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', } BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 1 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK = ctypes.c_uint32 # enum # values for enumeration 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK' BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK__enumvalues = { 0: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', 1: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', } BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 1 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK = ctypes.c_uint32 # enum # values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK' BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK__enumvalues = { 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', } BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 1 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK' BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__enumvalues = { 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', } BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 1 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK' BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK__enumvalues = { 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', } BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0 BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 1 BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK' BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK__enumvalues = { 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', } BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0 BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 1 BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK' BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK__enumvalues = { 0: 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', 1: 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', } BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0 BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 1 BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK' BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK__enumvalues = { 0: 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', 1: 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', } BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0 BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 1 BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE' BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE__enumvalues = { 0: 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', 1: 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', } BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0 BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 1 BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE = ctypes.c_uint32 # enum # values for enumeration 'BLND_DEBUG_BLND_CNV_MUX_SELECT' BLND_DEBUG_BLND_CNV_MUX_SELECT__enumvalues = { 0: 'BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW', 1: 'BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH', } BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0 BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 1 BLND_DEBUG_BLND_CNV_MUX_SELECT = ctypes.c_uint32 # enum # values for enumeration 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN' BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN__enumvalues = { 0: 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', 1: 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', } BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0 BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 1 BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', 2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', 3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', 4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', 5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', 6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', 7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', 8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', 9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', 2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', 3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', 4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', 5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', 6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', 7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', 8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', 9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', 1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', } AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { 0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', 1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', } AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', 2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', 3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', 4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', 5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', 6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', 7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', 8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', 9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', 2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', 3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', 4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', 5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', 6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', 7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', 8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', 9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { 0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', 1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', } AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_EN' UNP_GRPH_EN__enumvalues = { 0: 'UNP_GRPH_DISABLED', 1: 'UNP_GRPH_ENABLED', } UNP_GRPH_DISABLED = 0 UNP_GRPH_ENABLED = 1 UNP_GRPH_EN = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_DEPTH' UNP_GRPH_DEPTH__enumvalues = { 0: 'UNP_GRPH_8BPP', 1: 'UNP_GRPH_16BPP', 2: 'UNP_GRPH_32BPP', } UNP_GRPH_8BPP = 0 UNP_GRPH_16BPP = 1 UNP_GRPH_32BPP = 2 UNP_GRPH_DEPTH = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_NUM_BANKS' UNP_GRPH_NUM_BANKS__enumvalues = { 0: 'UNP_GRPH_ADDR_SURF_2_BANK', 1: 'UNP_GRPH_ADDR_SURF_4_BANK', 2: 'UNP_GRPH_ADDR_SURF_8_BANK', 3: 'UNP_GRPH_ADDR_SURF_16_BANK', } UNP_GRPH_ADDR_SURF_2_BANK = 0 UNP_GRPH_ADDR_SURF_4_BANK = 1 UNP_GRPH_ADDR_SURF_8_BANK = 2 UNP_GRPH_ADDR_SURF_16_BANK = 3 UNP_GRPH_NUM_BANKS = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_BANK_WIDTH' UNP_GRPH_BANK_WIDTH__enumvalues = { 0: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_1', 1: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_2', 2: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_4', 3: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_8', } UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0 UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 1 UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 2 UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 3 UNP_GRPH_BANK_WIDTH = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_BANK_HEIGHT' UNP_GRPH_BANK_HEIGHT__enumvalues = { 0: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1', 1: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2', 2: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4', 3: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8', } UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 1 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 2 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 3 UNP_GRPH_BANK_HEIGHT = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_TILE_SPLIT' UNP_GRPH_TILE_SPLIT__enumvalues = { 0: 'UNP_ADDR_SURF_TILE_SPLIT_64B', 1: 'UNP_ADDR_SURF_TILE_SPLIT_128B', 2: 'UNP_ADDR_SURF_TILE_SPLIT_256B', 3: 'UNP_ADDR_SURF_TILE_SPLIT_512B', 4: 'UNP_ADDR_SURF_TILE_SPLIT_1KB', 5: 'UNP_ADDR_SURF_TILE_SPLIT_2KB', 6: 'UNP_ADDR_SURF_TILE_SPLIT_4KB', } UNP_ADDR_SURF_TILE_SPLIT_64B = 0 UNP_ADDR_SURF_TILE_SPLIT_128B = 1 UNP_ADDR_SURF_TILE_SPLIT_256B = 2 UNP_ADDR_SURF_TILE_SPLIT_512B = 3 UNP_ADDR_SURF_TILE_SPLIT_1KB = 4 UNP_ADDR_SURF_TILE_SPLIT_2KB = 5 UNP_ADDR_SURF_TILE_SPLIT_4KB = 6 UNP_GRPH_TILE_SPLIT = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE' UNP_GRPH_ADDRESS_TRANSLATION_ENABLE__enumvalues = { 0: 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0', 1: 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1', } UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0 UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 1 UNP_GRPH_ADDRESS_TRANSLATION_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_MACRO_TILE_ASPECT' UNP_GRPH_MACRO_TILE_ASPECT__enumvalues = { 0: 'UNP_ADDR_SURF_MACRO_ASPECT_1', 1: 'UNP_ADDR_SURF_MACRO_ASPECT_2', 2: 'UNP_ADDR_SURF_MACRO_ASPECT_4', 3: 'UNP_ADDR_SURF_MACRO_ASPECT_8', } UNP_ADDR_SURF_MACRO_ASPECT_1 = 0 UNP_ADDR_SURF_MACRO_ASPECT_2 = 1 UNP_ADDR_SURF_MACRO_ASPECT_4 = 2 UNP_ADDR_SURF_MACRO_ASPECT_8 = 3 UNP_GRPH_MACRO_TILE_ASPECT = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_COLOR_EXPANSION_MODE' UNP_GRPH_COLOR_EXPANSION_MODE__enumvalues = { 0: 'UNP_GRPH_DYNAMIC_EXPANSION', 1: 'UNP_GRPH_ZERO_EXPANSION', } UNP_GRPH_DYNAMIC_EXPANSION = 0 UNP_GRPH_ZERO_EXPANSION = 1 UNP_GRPH_COLOR_EXPANSION_MODE = ctypes.c_uint32 # enum # values for enumeration 'UNP_VIDEO_FORMAT' UNP_VIDEO_FORMAT__enumvalues = { 0: 'UNP_VIDEO_FORMAT0', 1: 'UNP_VIDEO_FORMAT1', 2: 'UNP_VIDEO_FORMAT_YUV420_YCbCr', 3: 'UNP_VIDEO_FORMAT_YUV420_YCrCb', 4: 'UNP_VIDEO_FORMAT_YUV422_YCb', 5: 'UNP_VIDEO_FORMAT_YUV422_YCr', 6: 'UNP_VIDEO_FORMAT_YUV422_CbY', 7: 'UNP_VIDEO_FORMAT_YUV422_CrY', } UNP_VIDEO_FORMAT0 = 0 UNP_VIDEO_FORMAT1 = 1 UNP_VIDEO_FORMAT_YUV420_YCbCr = 2 UNP_VIDEO_FORMAT_YUV420_YCrCb = 3 UNP_VIDEO_FORMAT_YUV422_YCb = 4 UNP_VIDEO_FORMAT_YUV422_YCr = 5 UNP_VIDEO_FORMAT_YUV422_CbY = 6 UNP_VIDEO_FORMAT_YUV422_CrY = 7 UNP_VIDEO_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_ENDIAN_SWAP' UNP_GRPH_ENDIAN_SWAP__enumvalues = { 0: 'UNP_GRPH_ENDIAN_SWAP_NONE', 1: 'UNP_GRPH_ENDIAN_SWAP_8IN16', 2: 'UNP_GRPH_ENDIAN_SWAP_8IN32', 3: 'UNP_GRPH_ENDIAN_SWAP_8IN43', } UNP_GRPH_ENDIAN_SWAP_NONE = 0 UNP_GRPH_ENDIAN_SWAP_8IN16 = 1 UNP_GRPH_ENDIAN_SWAP_8IN32 = 2 UNP_GRPH_ENDIAN_SWAP_8IN43 = 3 UNP_GRPH_ENDIAN_SWAP = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_RED_CROSSBAR' UNP_GRPH_RED_CROSSBAR__enumvalues = { 0: 'UNP_GRPH_RED_CROSSBAR_R_Cr', 1: 'UNP_GRPH_RED_CROSSBAR_G_Y', 2: 'UNP_GRPH_RED_CROSSBAR_B_Cb', 3: 'UNP_GRPH_RED_CROSSBAR_A', } UNP_GRPH_RED_CROSSBAR_R_Cr = 0 UNP_GRPH_RED_CROSSBAR_G_Y = 1 UNP_GRPH_RED_CROSSBAR_B_Cb = 2 UNP_GRPH_RED_CROSSBAR_A = 3 UNP_GRPH_RED_CROSSBAR = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_GREEN_CROSSBAR' UNP_GRPH_GREEN_CROSSBAR__enumvalues = { 0: 'UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y', 1: 'UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C', 2: 'UNP_UNP_GRPH_GREEN_CROSSBAR_A', 3: 'UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr', } UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0 UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 1 UNP_UNP_GRPH_GREEN_CROSSBAR_A = 2 UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 3 UNP_GRPH_GREEN_CROSSBAR = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_BLUE_CROSSBAR' UNP_GRPH_BLUE_CROSSBAR__enumvalues = { 0: 'UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C', 1: 'UNP_GRPH_BLUE_CROSSBAR_A', 2: 'UNP_GRPH_BLUE_CROSSBAR_R_Cr', 3: 'UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y', } UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0 UNP_GRPH_BLUE_CROSSBAR_A = 1 UNP_GRPH_BLUE_CROSSBAR_R_Cr = 2 UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 3 UNP_GRPH_BLUE_CROSSBAR = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_MODE_UPDATE_LOCKG' UNP_GRPH_MODE_UPDATE_LOCKG__enumvalues = { 0: 'UNP_GRPH_UPDATE_LOCK_0', 1: 'UNP_GRPH_UPDATE_LOCK_1', } UNP_GRPH_UPDATE_LOCK_0 = 0 UNP_GRPH_UPDATE_LOCK_1 = 1 UNP_GRPH_MODE_UPDATE_LOCKG = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK' UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK__enumvalues = { 0: 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0', 1: 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1', } UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0 UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 1 UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE' UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE__enumvalues = { 0: 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0', 1: 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1', } UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0 UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 1 UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE' UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__enumvalues = { 0: 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0', 1: 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1', } UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0 UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 1 UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_STEREOSYNC_FLIP_EN' UNP_GRPH_STEREOSYNC_FLIP_EN__enumvalues = { 0: 'UNP_GRPH_STEREOSYNC_FLIP_DISABLE', 1: 'UNP_GRPH_STEREOSYNC_FLIP_ENABLE', } UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0 UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 1 UNP_GRPH_STEREOSYNC_FLIP_EN = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_STEREOSYNC_FLIP_MODE' UNP_GRPH_STEREOSYNC_FLIP_MODE__enumvalues = { 0: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_0', 1: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_1', 2: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_2', 3: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_3', } UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0 UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 1 UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 2 UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 3 UNP_GRPH_STEREOSYNC_FLIP_MODE = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_STACK_INTERLACE_FLIP_EN' UNP_GRPH_STACK_INTERLACE_FLIP_EN__enumvalues = { 0: 'UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE', 1: 'UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE', } UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0 UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 1 UNP_GRPH_STACK_INTERLACE_FLIP_EN = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE' UNP_GRPH_STACK_INTERLACE_FLIP_MODE__enumvalues = { 0: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0', 1: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1', 2: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2', 3: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3', } UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 1 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 2 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 3 UNP_GRPH_STACK_INTERLACE_FLIP_MODE = ctypes.c_uint32 # enum # values for enumeration 'UNP_GRPH_STEREOSYNC_SELECT_DISABLE' UNP_GRPH_STEREOSYNC_SELECT_DISABLE__enumvalues = { 0: 'UNP_GRPH_STEREOSYNC_SELECT_EN', 1: 'UNP_GRPH_STEREOSYNC_SELECT_DIS', } UNP_GRPH_STEREOSYNC_SELECT_EN = 0 UNP_GRPH_STEREOSYNC_SELECT_DIS = 1 UNP_GRPH_STEREOSYNC_SELECT_DISABLE = ctypes.c_uint32 # enum # values for enumeration 'UNP_CRC_SOURCE_SEL' UNP_CRC_SOURCE_SEL__enumvalues = { 0: 'UNP_CRC_SOURCE_SEL_NP_TO_LBV', 1: 'UNP_CRC_SOURCE_SEL_LOWER32', 2: 'UNP_CRC_SOURCE_SEL_RESERVED', 3: 'UNP_CRC_SOURCE_SEL_LOWER16', 4: 'UNP_CRC_SOURCE_SEL_UNP_TO_LBV', } UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0 UNP_CRC_SOURCE_SEL_LOWER32 = 1 UNP_CRC_SOURCE_SEL_RESERVED = 2 UNP_CRC_SOURCE_SEL_LOWER16 = 3 UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 4 UNP_CRC_SOURCE_SEL = ctypes.c_uint32 # enum # values for enumeration 'UNP_CRC_LINE_SEL' UNP_CRC_LINE_SEL__enumvalues = { 0: 'UNP_CRC_LINE_SEL_RESERVED', 1: 'UNP_CRC_LINE_SEL_EVEN_ONLY', 2: 'UNP_CRC_LINE_SEL_ODD_ONLY', 3: 'UNP_CRC_LINE_SEL_ODD_EVEN', } UNP_CRC_LINE_SEL_RESERVED = 0 UNP_CRC_LINE_SEL_EVEN_ONLY = 1 UNP_CRC_LINE_SEL_ODD_ONLY = 2 UNP_CRC_LINE_SEL_ODD_EVEN = 3 UNP_CRC_LINE_SEL = ctypes.c_uint32 # enum # values for enumeration 'UNP_ROTATION_ANGLE' UNP_ROTATION_ANGLE__enumvalues = { 0: 'UNP_ROTATION_ANGLE_0', 1: 'UNP_ROTATION_ANGLE_90', 2: 'UNP_ROTATION_ANGLE_180', 3: 'UNP_ROTATION_ANGLE_270', 4: 'UNP_ROTATION_ANGLE_0m', 5: 'UNP_ROTATION_ANGLE_90m', 6: 'UNP_ROTATION_ANGLE_180m', 7: 'UNP_ROTATION_ANGLE_270m', } UNP_ROTATION_ANGLE_0 = 0 UNP_ROTATION_ANGLE_90 = 1 UNP_ROTATION_ANGLE_180 = 2 UNP_ROTATION_ANGLE_270 = 3 UNP_ROTATION_ANGLE_0m = 4 UNP_ROTATION_ANGLE_90m = 5 UNP_ROTATION_ANGLE_180m = 6 UNP_ROTATION_ANGLE_270m = 7 UNP_ROTATION_ANGLE = ctypes.c_uint32 # enum # values for enumeration 'UNP_PIXEL_DROP' UNP_PIXEL_DROP__enumvalues = { 0: 'UNP_PIXEL_NO_DROP', 1: 'UNP_PIXEL_DROPPING', } UNP_PIXEL_NO_DROP = 0 UNP_PIXEL_DROPPING = 1 UNP_PIXEL_DROP = ctypes.c_uint32 # enum # values for enumeration 'UNP_BUFFER_MODE' UNP_BUFFER_MODE__enumvalues = { 0: 'UNP_BUFFER_MODE_LUMA', 1: 'UNP_BUFFER_MODE_LUMA_CHROMA', } UNP_BUFFER_MODE_LUMA = 0 UNP_BUFFER_MODE_LUMA_CHROMA = 1 UNP_BUFFER_MODE = ctypes.c_uint32 # enum # values for enumeration 'DP_LINK_TRAINING_COMPLETE' DP_LINK_TRAINING_COMPLETE__enumvalues = { 0: 'DP_LINK_TRAINING_NOT_COMPLETE', 1: 'DP_LINK_TRAINING_ALREADY_COMPLETE', } DP_LINK_TRAINING_NOT_COMPLETE = 0 DP_LINK_TRAINING_ALREADY_COMPLETE = 1 DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum # values for enumeration 'DP_EMBEDDED_PANEL_MODE' DP_EMBEDDED_PANEL_MODE__enumvalues = { 0: 'DP_EXTERNAL_PANEL', 1: 'DP_EMBEDDED_PANEL', } DP_EXTERNAL_PANEL = 0 DP_EMBEDDED_PANEL = 1 DP_EMBEDDED_PANEL_MODE = ctypes.c_uint32 # enum # values for enumeration 'DP_PIXEL_ENCODING' DP_PIXEL_ENCODING__enumvalues = { 0: 'DP_PIXEL_ENCODING_RGB444', 1: 'DP_PIXEL_ENCODING_YCBCR422', 2: 'DP_PIXEL_ENCODING_YCBCR444', 3: 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', 4: 'DP_PIXEL_ENCODING_Y_ONLY', 5: 'DP_PIXEL_ENCODING_YCBCR420', 6: 'DP_PIXEL_ENCODING_RESERVED', } DP_PIXEL_ENCODING_RGB444 = 0 DP_PIXEL_ENCODING_YCBCR422 = 1 DP_PIXEL_ENCODING_YCBCR444 = 2 DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 3 DP_PIXEL_ENCODING_Y_ONLY = 4 DP_PIXEL_ENCODING_YCBCR420 = 5 DP_PIXEL_ENCODING_RESERVED = 6 DP_PIXEL_ENCODING = ctypes.c_uint32 # enum # values for enumeration 'DP_DYN_RANGE' DP_DYN_RANGE__enumvalues = { 0: 'DP_DYN_VESA_RANGE', 1: 'DP_DYN_CEA_RANGE', } DP_DYN_VESA_RANGE = 0 DP_DYN_CEA_RANGE = 1 DP_DYN_RANGE = ctypes.c_uint32 # enum # values for enumeration 'DP_YCBCR_RANGE' DP_YCBCR_RANGE__enumvalues = { 0: 'DP_YCBCR_RANGE_BT601_5', 1: 'DP_YCBCR_RANGE_BT709_5', } DP_YCBCR_RANGE_BT601_5 = 0 DP_YCBCR_RANGE_BT709_5 = 1 DP_YCBCR_RANGE = ctypes.c_uint32 # enum # values for enumeration 'DP_COMPONENT_DEPTH' DP_COMPONENT_DEPTH__enumvalues = { 0: 'DP_COMPONENT_DEPTH_6BPC', 1: 'DP_COMPONENT_DEPTH_8BPC', 2: 'DP_COMPONENT_DEPTH_10BPC', 3: 'DP_COMPONENT_DEPTH_12BPC', 4: 'DP_COMPONENT_DEPTH_16BPC_RESERVED', 5: 'DP_COMPONENT_DEPTH_RESERVED', } DP_COMPONENT_DEPTH_6BPC = 0 DP_COMPONENT_DEPTH_8BPC = 1 DP_COMPONENT_DEPTH_10BPC = 2 DP_COMPONENT_DEPTH_12BPC = 3 DP_COMPONENT_DEPTH_16BPC_RESERVED = 4 DP_COMPONENT_DEPTH_RESERVED = 5 DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum # values for enumeration 'DP_MSA_MISC0_OVERRIDE_ENABLE' DP_MSA_MISC0_OVERRIDE_ENABLE__enumvalues = { 0: 'MSA_MISC0_OVERRIDE_DISABLE', 1: 'MSA_MISC0_OVERRIDE_ENABLE', } MSA_MISC0_OVERRIDE_DISABLE = 0 MSA_MISC0_OVERRIDE_ENABLE = 1 DP_MSA_MISC0_OVERRIDE_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE' DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__enumvalues = { 0: 'MSA_MISC1_BIT7_OVERRIDE_DISABLE', 1: 'MSA_MISC1_BIT7_OVERRIDE_ENABLE', } MSA_MISC1_BIT7_OVERRIDE_DISABLE = 0 MSA_MISC1_BIT7_OVERRIDE_ENABLE = 1 DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DP_UDI_LANES' DP_UDI_LANES__enumvalues = { 0: 'DP_UDI_1_LANE', 1: 'DP_UDI_2_LANES', 2: 'DP_UDI_LANES_RESERVED', 3: 'DP_UDI_4_LANES', } DP_UDI_1_LANE = 0 DP_UDI_2_LANES = 1 DP_UDI_LANES_RESERVED = 2 DP_UDI_4_LANES = 3 DP_UDI_LANES = ctypes.c_uint32 # enum # values for enumeration 'DP_VID_STREAM_DIS_DEFER' DP_VID_STREAM_DIS_DEFER__enumvalues = { 0: 'DP_VID_STREAM_DIS_NO_DEFER', 1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', 2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', } DP_VID_STREAM_DIS_NO_DEFER = 0 DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1 DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2 DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum # values for enumeration 'DP_STEER_OVERFLOW_ACK' DP_STEER_OVERFLOW_ACK__enumvalues = { 0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', } DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0 DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1 DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum # values for enumeration 'DP_STEER_OVERFLOW_MASK' DP_STEER_OVERFLOW_MASK__enumvalues = { 0: 'DP_STEER_OVERFLOW_MASKED', 1: 'DP_STEER_OVERFLOW_UNMASK', } DP_STEER_OVERFLOW_MASKED = 0 DP_STEER_OVERFLOW_UNMASK = 1 DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum # values for enumeration 'DP_TU_OVERFLOW_ACK' DP_TU_OVERFLOW_ACK__enumvalues = { 0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', } DP_TU_OVERFLOW_ACK_NO_EFFECT = 0 DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1 DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum # values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_EN' DPHY_ALT_SCRAMBLER_RESET_EN__enumvalues = { 0: 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', 1: 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', } DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0 DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 1 DPHY_ALT_SCRAMBLER_RESET_EN = ctypes.c_uint32 # enum # values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_SEL' DPHY_ALT_SCRAMBLER_RESET_SEL__enumvalues = { 0: 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', 1: 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', } DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0 DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 1 DPHY_ALT_SCRAMBLER_RESET_SEL = ctypes.c_uint32 # enum # values for enumeration 'DP_VID_TIMING_MODE' DP_VID_TIMING_MODE__enumvalues = { 0: 'DP_VID_TIMING_MODE_ASYNC', 1: 'DP_VID_TIMING_MODE_SYNC', } DP_VID_TIMING_MODE_ASYNC = 0 DP_VID_TIMING_MODE_SYNC = 1 DP_VID_TIMING_MODE = ctypes.c_uint32 # enum # values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE' DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = { 0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', 1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', } DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0 DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1 DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum # values for enumeration 'DP_VID_M_N_GEN_EN' DP_VID_M_N_GEN_EN__enumvalues = { 0: 'DP_VID_M_N_PROGRAMMED_VIA_REG', 1: 'DP_VID_M_N_CALC_AUTO', } DP_VID_M_N_PROGRAMMED_VIA_REG = 0 DP_VID_M_N_CALC_AUTO = 1 DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum # values for enumeration 'DP_VID_M_DOUBLE_VALUE_EN' DP_VID_M_DOUBLE_VALUE_EN__enumvalues = { 0: 'DP_VID_M_INPUT_PIXEL_RATE', 1: 'DP_VID_M_DOUBLE_INPUT_PIXEL_RATE', } DP_VID_M_INPUT_PIXEL_RATE = 0 DP_VID_M_DOUBLE_INPUT_PIXEL_RATE = 1 DP_VID_M_DOUBLE_VALUE_EN = ctypes.c_uint32 # enum # values for enumeration 'DP_VID_ENHANCED_FRAME_MODE' DP_VID_ENHANCED_FRAME_MODE__enumvalues = { 0: 'VID_NORMAL_FRAME_MODE', 1: 'VID_ENHANCED_MODE', } VID_NORMAL_FRAME_MODE = 0 VID_ENHANCED_MODE = 1 DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum # values for enumeration 'DP_VID_MSA_TOP_FIELD_MODE' DP_VID_MSA_TOP_FIELD_MODE__enumvalues = { 0: 'DP_TOP_FIELD_ONLY', 1: 'DP_TOP_PLUS_BOTTOM_FIELD', } DP_TOP_FIELD_ONLY = 0 DP_TOP_PLUS_BOTTOM_FIELD = 1 DP_VID_MSA_TOP_FIELD_MODE = ctypes.c_uint32 # enum # values for enumeration 'DP_VID_VBID_FIELD_POL' DP_VID_VBID_FIELD_POL__enumvalues = { 0: 'DP_VID_VBID_FIELD_POL_NORMAL', 1: 'DP_VID_VBID_FIELD_POL_INV', } DP_VID_VBID_FIELD_POL_NORMAL = 0 DP_VID_VBID_FIELD_POL_INV = 1 DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum # values for enumeration 'DP_VID_STREAM_DISABLE_ACK' DP_VID_STREAM_DISABLE_ACK__enumvalues = { 0: 'ID_STREAM_DISABLE_NO_ACK', 1: 'ID_STREAM_DISABLE_ACKED', } ID_STREAM_DISABLE_NO_ACK = 0 ID_STREAM_DISABLE_ACKED = 1 DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum # values for enumeration 'DP_VID_STREAM_DISABLE_MASK' DP_VID_STREAM_DISABLE_MASK__enumvalues = { 0: 'VID_STREAM_DISABLE_MASKED', 1: 'VID_STREAM_DISABLE_UNMASK', } VID_STREAM_DISABLE_MASKED = 0 VID_STREAM_DISABLE_UNMASK = 1 DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum # values for enumeration 'DPHY_ATEST_SEL_LANE0' DPHY_ATEST_SEL_LANE0__enumvalues = { 0: 'DPHY_ATEST_LANE0_PRBS_PATTERN', 1: 'DPHY_ATEST_LANE0_REG_PATTERN', } DPHY_ATEST_LANE0_PRBS_PATTERN = 0 DPHY_ATEST_LANE0_REG_PATTERN = 1 DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum # values for enumeration 'DPHY_ATEST_SEL_LANE1' DPHY_ATEST_SEL_LANE1__enumvalues = { 0: 'DPHY_ATEST_LANE1_PRBS_PATTERN', 1: 'DPHY_ATEST_LANE1_REG_PATTERN', } DPHY_ATEST_LANE1_PRBS_PATTERN = 0 DPHY_ATEST_LANE1_REG_PATTERN = 1 DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum # values for enumeration 'DPHY_ATEST_SEL_LANE2' DPHY_ATEST_SEL_LANE2__enumvalues = { 0: 'DPHY_ATEST_LANE2_PRBS_PATTERN', 1: 'DPHY_ATEST_LANE2_REG_PATTERN', } DPHY_ATEST_LANE2_PRBS_PATTERN = 0 DPHY_ATEST_LANE2_REG_PATTERN = 1 DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum # values for enumeration 'DPHY_ATEST_SEL_LANE3' DPHY_ATEST_SEL_LANE3__enumvalues = { 0: 'DPHY_ATEST_LANE3_PRBS_PATTERN', 1: 'DPHY_ATEST_LANE3_REG_PATTERN', } DPHY_ATEST_LANE3_PRBS_PATTERN = 0 DPHY_ATEST_LANE3_REG_PATTERN = 1 DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum # values for enumeration 'DPHY_SCRAMBLER_SEL' DPHY_SCRAMBLER_SEL__enumvalues = { 0: 'DPHY_SCRAMBLER_SEL_LANE_DATA', 1: 'DPHY_SCRAMBLER_SEL_DBG_DATA', } DPHY_SCRAMBLER_SEL_LANE_DATA = 0 DPHY_SCRAMBLER_SEL_DBG_DATA = 1 DPHY_SCRAMBLER_SEL = ctypes.c_uint32 # enum # values for enumeration 'DPHY_BYPASS' DPHY_BYPASS__enumvalues = { 0: 'DPHY_8B10B_OUTPUT', 1: 'DPHY_DBG_OUTPUT', } DPHY_8B10B_OUTPUT = 0 DPHY_DBG_OUTPUT = 1 DPHY_BYPASS = ctypes.c_uint32 # enum # values for enumeration 'DPHY_SKEW_BYPASS' DPHY_SKEW_BYPASS__enumvalues = { 0: 'DPHY_WITH_SKEW', 1: 'DPHY_NO_SKEW', } DPHY_WITH_SKEW = 0 DPHY_NO_SKEW = 1 DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum # values for enumeration 'DPHY_TRAINING_PATTERN_SEL' DPHY_TRAINING_PATTERN_SEL__enumvalues = { 0: 'DPHY_TRAINING_PATTERN_1', 1: 'DPHY_TRAINING_PATTERN_2', 2: 'DPHY_TRAINING_PATTERN_3', 3: 'DPHY_TRAINING_PATTERN_4', } DPHY_TRAINING_PATTERN_1 = 0 DPHY_TRAINING_PATTERN_2 = 1 DPHY_TRAINING_PATTERN_3 = 2 DPHY_TRAINING_PATTERN_4 = 3 DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum # values for enumeration 'DPHY_8B10B_RESET' DPHY_8B10B_RESET__enumvalues = { 0: 'DPHY_8B10B_NOT_RESET', 1: 'DPHY_8B10B_RESETET', } DPHY_8B10B_NOT_RESET = 0 DPHY_8B10B_RESETET = 1 DPHY_8B10B_RESET = ctypes.c_uint32 # enum # values for enumeration 'DP_DPHY_8B10B_EXT_DISP' DP_DPHY_8B10B_EXT_DISP__enumvalues = { 0: 'DP_DPHY_8B10B_EXT_DISP_ZERO', 1: 'DP_DPHY_8B10B_EXT_DISP_ONE', } DP_DPHY_8B10B_EXT_DISP_ZERO = 0 DP_DPHY_8B10B_EXT_DISP_ONE = 1 DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum # values for enumeration 'DPHY_8B10B_CUR_DISP' DPHY_8B10B_CUR_DISP__enumvalues = { 0: 'DPHY_8B10B_CUR_DISP_ZERO', 1: 'DPHY_8B10B_CUR_DISP_ONE', } DPHY_8B10B_CUR_DISP_ZERO = 0 DPHY_8B10B_CUR_DISP_ONE = 1 DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum # values for enumeration 'DPHY_PRBS_EN' DPHY_PRBS_EN__enumvalues = { 0: 'DPHY_PRBS_DISABLE', 1: 'DPHY_PRBS_ENABLE', } DPHY_PRBS_DISABLE = 0 DPHY_PRBS_ENABLE = 1 DPHY_PRBS_EN = ctypes.c_uint32 # enum # values for enumeration 'DPHY_PRBS_SEL' DPHY_PRBS_SEL__enumvalues = { 0: 'DPHY_PRBS7_SELECTED', 1: 'DPHY_PRBS23_SELECTED', 2: 'DPHY_PRBS11_SELECTED', } DPHY_PRBS7_SELECTED = 0 DPHY_PRBS23_SELECTED = 1 DPHY_PRBS11_SELECTED = 2 DPHY_PRBS_SEL = ctypes.c_uint32 # enum # values for enumeration 'DPHY_SCRAMBLER_DIS' DPHY_SCRAMBLER_DIS__enumvalues = { 0: 'DPHY_SCR_ENABLED', 1: 'DPHY_SCR_DISABLED', } DPHY_SCR_ENABLED = 0 DPHY_SCR_DISABLED = 1 DPHY_SCRAMBLER_DIS = ctypes.c_uint32 # enum # values for enumeration 'DPHY_SCRAMBLER_ADVANCE' DPHY_SCRAMBLER_ADVANCE__enumvalues = { 0: 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', 1: 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', } DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0 DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 1 DPHY_SCRAMBLER_ADVANCE = ctypes.c_uint32 # enum # values for enumeration 'DPHY_SCRAMBLER_KCODE' DPHY_SCRAMBLER_KCODE__enumvalues = { 0: 'DPHY_SCRAMBLER_KCODE_DISABLED', 1: 'DPHY_SCRAMBLER_KCODE_ENABLED', } DPHY_SCRAMBLER_KCODE_DISABLED = 0 DPHY_SCRAMBLER_KCODE_ENABLED = 1 DPHY_SCRAMBLER_KCODE = ctypes.c_uint32 # enum # values for enumeration 'DPHY_LOAD_BS_COUNT_START' DPHY_LOAD_BS_COUNT_START__enumvalues = { 0: 'DPHY_LOAD_BS_COUNT_STARTED', 1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED', } DPHY_LOAD_BS_COUNT_STARTED = 0 DPHY_LOAD_BS_COUNT_NOT_STARTED = 1 DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum # values for enumeration 'DPHY_CRC_EN' DPHY_CRC_EN__enumvalues = { 0: 'DPHY_CRC_DISABLED', 1: 'DPHY_CRC_ENABLED', } DPHY_CRC_DISABLED = 0 DPHY_CRC_ENABLED = 1 DPHY_CRC_EN = ctypes.c_uint32 # enum # values for enumeration 'DPHY_CRC_CONT_EN' DPHY_CRC_CONT_EN__enumvalues = { 0: 'DPHY_CRC_ONE_SHOT', 1: 'DPHY_CRC_CONTINUOUS', } DPHY_CRC_ONE_SHOT = 0 DPHY_CRC_CONTINUOUS = 1 DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum # values for enumeration 'DPHY_CRC_FIELD' DPHY_CRC_FIELD__enumvalues = { 0: 'DPHY_CRC_START_FROM_TOP_FIELD', 1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD', } DPHY_CRC_START_FROM_TOP_FIELD = 0 DPHY_CRC_START_FROM_BOTTOM_FIELD = 1 DPHY_CRC_FIELD = ctypes.c_uint32 # enum # values for enumeration 'DPHY_CRC_SEL' DPHY_CRC_SEL__enumvalues = { 0: 'DPHY_CRC_LANE0_SELECTED', 1: 'DPHY_CRC_LANE1_SELECTED', 2: 'DPHY_CRC_LANE2_SELECTED', 3: 'DPHY_CRC_LANE3_SELECTED', } DPHY_CRC_LANE0_SELECTED = 0 DPHY_CRC_LANE1_SELECTED = 1 DPHY_CRC_LANE2_SELECTED = 2 DPHY_CRC_LANE3_SELECTED = 3 DPHY_CRC_SEL = ctypes.c_uint32 # enum # values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE' DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = { 0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', 1: 'DPHY_FAST_TRAINING_CAPABLE', } DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0 DPHY_FAST_TRAINING_CAPABLE = 1 DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum # values for enumeration 'DP_SEC_COLLISION_ACK' DP_SEC_COLLISION_ACK__enumvalues = { 0: 'DP_SEC_COLLISION_ACK_NO_EFFECT', 1: 'DP_SEC_COLLISION_ACK_CLR_FLAG', } DP_SEC_COLLISION_ACK_NO_EFFECT = 0 DP_SEC_COLLISION_ACK_CLR_FLAG = 1 DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum # values for enumeration 'DP_SEC_AUDIO_MUTE' DP_SEC_AUDIO_MUTE__enumvalues = { 0: 'DP_SEC_AUDIO_MUTE_HW_CTRL', 1: 'DP_SEC_AUDIO_MUTE_SW_CTRL', } DP_SEC_AUDIO_MUTE_HW_CTRL = 0 DP_SEC_AUDIO_MUTE_SW_CTRL = 1 DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum # values for enumeration 'DP_SEC_TIMESTAMP_MODE' DP_SEC_TIMESTAMP_MODE__enumvalues = { 0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', } DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0 DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1 DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum # values for enumeration 'DP_SEC_ASP_PRIORITY' DP_SEC_ASP_PRIORITY__enumvalues = { 0: 'DP_SEC_ASP_LOW_PRIORITY', 1: 'DP_SEC_ASP_HIGH_PRIORITY', } DP_SEC_ASP_LOW_PRIORITY = 0 DP_SEC_ASP_HIGH_PRIORITY = 1 DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum # values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE' DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { 0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', 1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', } DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum # values for enumeration 'DP_MSE_SAT_UPDATE_ACT' DP_MSE_SAT_UPDATE_ACT__enumvalues = { 0: 'DP_MSE_SAT_UPDATE_NO_ACTION', 1: 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', 2: 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', } DP_MSE_SAT_UPDATE_NO_ACTION = 0 DP_MSE_SAT_UPDATE_WITH_TRIGGER = 1 DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 2 DP_MSE_SAT_UPDATE_ACT = ctypes.c_uint32 # enum # values for enumeration 'DP_MSE_LINK_LINE' DP_MSE_LINK_LINE__enumvalues = { 0: 'DP_MSE_LINK_LINE_32_MTP_LONG', 1: 'DP_MSE_LINK_LINE_64_MTP_LONG', 2: 'DP_MSE_LINK_LINE_128_MTP_LONG', 3: 'DP_MSE_LINK_LINE_256_MTP_LONG', } DP_MSE_LINK_LINE_32_MTP_LONG = 0 DP_MSE_LINK_LINE_64_MTP_LONG = 1 DP_MSE_LINK_LINE_128_MTP_LONG = 2 DP_MSE_LINK_LINE_256_MTP_LONG = 3 DP_MSE_LINK_LINE = ctypes.c_uint32 # enum # values for enumeration 'DP_MSE_BLANK_CODE' DP_MSE_BLANK_CODE__enumvalues = { 0: 'DP_MSE_BLANK_CODE_SF_FILLED', 1: 'DP_MSE_BLANK_CODE_ZERO_FILLED', } DP_MSE_BLANK_CODE_SF_FILLED = 0 DP_MSE_BLANK_CODE_ZERO_FILLED = 1 DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum # values for enumeration 'DP_MSE_TIMESTAMP_MODE' DP_MSE_TIMESTAMP_MODE__enumvalues = { 0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', 1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', } DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0 DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1 DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum # values for enumeration 'DP_MSE_ZERO_ENCODER' DP_MSE_ZERO_ENCODER__enumvalues = { 0: 'DP_MSE_NOT_ZERO_FE_ENCODER', 1: 'DP_MSE_ZERO_FE_ENCODER', } DP_MSE_NOT_ZERO_FE_ENCODER = 0 DP_MSE_ZERO_FE_ENCODER = 1 DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum # values for enumeration 'DP_MSE_OUTPUT_DPDBG_DATA' DP_MSE_OUTPUT_DPDBG_DATA__enumvalues = { 0: 'DP_MSE_OUTPUT_DPDBG_DATA_DIS', 1: 'DP_MSE_OUTPUT_DPDBG_DATA_EN', } DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0 DP_MSE_OUTPUT_DPDBG_DATA_EN = 1 DP_MSE_OUTPUT_DPDBG_DATA = ctypes.c_uint32 # enum # values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE' DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = { 0: 'DP_DPHY_HBR2_PASS_THROUGH', 1: 'DP_DPHY_HBR2_PATTERN_1', 2: 'DP_DPHY_HBR2_PATTERN_2_NEG', 3: 'DP_DPHY_HBR2_PATTERN_3', 6: 'DP_DPHY_HBR2_PATTERN_2_POS', } DP_DPHY_HBR2_PASS_THROUGH = 0 DP_DPHY_HBR2_PATTERN_1 = 1 DP_DPHY_HBR2_PATTERN_2_NEG = 2 DP_DPHY_HBR2_PATTERN_3 = 3 DP_DPHY_HBR2_PATTERN_2_POS = 6 DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum # values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK' DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = { 0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED', } DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0 DPHY_CRC_MST_PHASE_ERROR_ACKED = 1 DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum # values for enumeration 'DPHY_SW_FAST_TRAINING_START' DPHY_SW_FAST_TRAINING_START__enumvalues = { 0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED', 1: 'DPHY_SW_FAST_TRAINING_STARTED', } DPHY_SW_FAST_TRAINING_NOT_STARTED = 0 DPHY_SW_FAST_TRAINING_STARTED = 1 DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum # values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN' DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = { 0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', 1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', } DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum # values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK' DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = { 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', } DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0 DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1 DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum # values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK' DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = { 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', } DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0 DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1 DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum # values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN' DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = { 0: 'MSA_V_TIMING_OVERRIDE_DISABLED', 1: 'MSA_V_TIMING_OVERRIDE_ENABLED', } MSA_V_TIMING_OVERRIDE_DISABLED = 0 MSA_V_TIMING_OVERRIDE_ENABLED = 1 DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum # values for enumeration 'DP_SEC_GSP0_PRIORITY' DP_SEC_GSP0_PRIORITY__enumvalues = { 0: 'SEC_GSP0_PRIORITY_LOW', 1: 'SEC_GSP0_PRIORITY_HIGH', } SEC_GSP0_PRIORITY_LOW = 0 SEC_GSP0_PRIORITY_HIGH = 1 DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum # values for enumeration 'DP_SEC_GSP0_SEND' DP_SEC_GSP0_SEND__enumvalues = { 0: 'NOT_SENT', 1: 'FORCE_SENT', } NOT_SENT = 0 FORCE_SENT = 1 DP_SEC_GSP0_SEND = ctypes.c_uint32 # enum # values for enumeration 'COL_MAN_UPDATE_LOCK' COL_MAN_UPDATE_LOCK__enumvalues = { 0: 'COL_MAN_UPDATE_UNLOCKED', 1: 'COL_MAN_UPDATE_LOCKED', } COL_MAN_UPDATE_UNLOCKED = 0 COL_MAN_UPDATE_LOCKED = 1 COL_MAN_UPDATE_LOCK = ctypes.c_uint32 # enum # values for enumeration 'COL_MAN_DISABLE_MULTIPLE_UPDATE' COL_MAN_DISABLE_MULTIPLE_UPDATE__enumvalues = { 0: 'COL_MAN_MULTIPLE_UPDATE', 1: 'COL_MAN_MULTIPLE_UPDAT_EDISABLE', } COL_MAN_MULTIPLE_UPDATE = 0 COL_MAN_MULTIPLE_UPDAT_EDISABLE = 1 COL_MAN_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum # values for enumeration 'COL_MAN_INPUTCSC_MODE' COL_MAN_INPUTCSC_MODE__enumvalues = { 0: 'INPUTCSC_MODE_BYPASS', 1: 'INPUTCSC_MODE_A', 2: 'INPUTCSC_MODE_B', 3: 'INPUTCSC_MODE_UNITY', } INPUTCSC_MODE_BYPASS = 0 INPUTCSC_MODE_A = 1 INPUTCSC_MODE_B = 2 INPUTCSC_MODE_UNITY = 3 COL_MAN_INPUTCSC_MODE = ctypes.c_uint32 # enum # values for enumeration 'COL_MAN_INPUTCSC_TYPE' COL_MAN_INPUTCSC_TYPE__enumvalues = { 0: 'INPUTCSC_TYPE_12_0', 1: 'INPUTCSC_TYPE_10_2', 2: 'INPUTCSC_TYPE_8_4', } INPUTCSC_TYPE_12_0 = 0 INPUTCSC_TYPE_10_2 = 1 INPUTCSC_TYPE_8_4 = 2 COL_MAN_INPUTCSC_TYPE = ctypes.c_uint32 # enum # values for enumeration 'COL_MAN_INPUTCSC_CONVERT' COL_MAN_INPUTCSC_CONVERT__enumvalues = { 0: 'INPUTCSC_ROUND', 1: 'INPUTCSC_TRUNCATE', } INPUTCSC_ROUND = 0 INPUTCSC_TRUNCATE = 1 COL_MAN_INPUTCSC_CONVERT = ctypes.c_uint32 # enum # values for enumeration 'COL_MAN_PRESCALE_MODE' COL_MAN_PRESCALE_MODE__enumvalues = { 0: 'PRESCALE_MODE_BYPASS', 1: 'PRESCALE_MODE_PROGRAM', 2: 'PRESCALE_MODE_UNITY', } PRESCALE_MODE_BYPASS = 0 PRESCALE_MODE_PROGRAM = 1 PRESCALE_MODE_UNITY = 2 COL_MAN_PRESCALE_MODE = ctypes.c_uint32 # enum # values for enumeration 'COL_MAN_INPUT_GAMMA_MODE' COL_MAN_INPUT_GAMMA_MODE__enumvalues = { 0: 'INGAMMA_MODE_BYPASS', 1: 'INGAMMA_MODE_FIX', 2: 'INGAMMA_MODE_FLOAT', } INGAMMA_MODE_BYPASS = 0 INGAMMA_MODE_FIX = 1 INGAMMA_MODE_FLOAT = 2 COL_MAN_INPUT_GAMMA_MODE = ctypes.c_uint32 # enum # values for enumeration 'COL_MAN_OUTPUT_CSC_MODE' COL_MAN_OUTPUT_CSC_MODE__enumvalues = { 0: 'COL_MAN_OUTPUT_CSC_BYPASS', 1: 'COL_MAN_OUTPUT_CSC_RGB', 2: 'COL_MAN_OUTPUT_CSC_YCrCb601', 3: 'COL_MAN_OUTPUT_CSC_YCrCb709', 4: 'COL_MAN_OUTPUT_CSC_A', 5: 'COL_MAN_OUTPUT_CSC_B', 6: 'COL_MAN_OUTPUT_CSC_UNITY', } COL_MAN_OUTPUT_CSC_BYPASS = 0 COL_MAN_OUTPUT_CSC_RGB = 1 COL_MAN_OUTPUT_CSC_YCrCb601 = 2 COL_MAN_OUTPUT_CSC_YCrCb709 = 3 COL_MAN_OUTPUT_CSC_A = 4 COL_MAN_OUTPUT_CSC_B = 5 COL_MAN_OUTPUT_CSC_UNITY = 6 COL_MAN_OUTPUT_CSC_MODE = ctypes.c_uint32 # enum # values for enumeration 'COL_MAN_DENORM_CLAMP_CONTROL' COL_MAN_DENORM_CLAMP_CONTROL__enumvalues = { 0: 'DENORM_CLAMP_MODE_UNITY', 1: 'DENORM_CLAMP_MODE_8', 2: 'DENORM_CLAMP_MODE_10', 3: 'DENORM_CLAMP_MODE_12', } DENORM_CLAMP_MODE_UNITY = 0 DENORM_CLAMP_MODE_8 = 1 DENORM_CLAMP_MODE_10 = 2 DENORM_CLAMP_MODE_12 = 3 COL_MAN_DENORM_CLAMP_CONTROL = ctypes.c_uint32 # enum # values for enumeration 'COL_MAN_REGAMMA_MODE_CONTROL' COL_MAN_REGAMMA_MODE_CONTROL__enumvalues = { 0: 'COL_MAN_REGAMMA_MODE_BYPASS', 1: 'COL_MAN_REGAMMA_MODE_ROM_A', 2: 'COL_MAN_REGAMMA_MODE_ROM_B', 3: 'COL_MAN_REGAMMA_MODE_A', 4: 'COL_MAN_REGAMMA_MODE_B', } COL_MAN_REGAMMA_MODE_BYPASS = 0 COL_MAN_REGAMMA_MODE_ROM_A = 1 COL_MAN_REGAMMA_MODE_ROM_B = 2 COL_MAN_REGAMMA_MODE_A = 3 COL_MAN_REGAMMA_MODE_B = 4 COL_MAN_REGAMMA_MODE_CONTROL = ctypes.c_uint32 # enum # values for enumeration 'COL_MAN_GLOBAL_PASSTHROUGH_ENABLE' COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__enumvalues = { 0: 'CM_GLOBAL_PASSTHROUGH_DISBALE', 1: 'CM_GLOBAL_PASSTHROUGH_ENABLE', } CM_GLOBAL_PASSTHROUGH_DISBALE = 0 CM_GLOBAL_PASSTHROUGH_ENABLE = 1 COL_MAN_GLOBAL_PASSTHROUGH_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'COL_MAN_DEGAMMA_MODE' COL_MAN_DEGAMMA_MODE__enumvalues = { 0: 'DEGAMMA_MODE_BYPASS', 1: 'DEGAMMA_MODE_A', 2: 'DEGAMMA_MODE_B', } DEGAMMA_MODE_BYPASS = 0 DEGAMMA_MODE_A = 1 DEGAMMA_MODE_B = 2 COL_MAN_DEGAMMA_MODE = ctypes.c_uint32 # enum # values for enumeration 'COL_MAN_GAMUT_REMAP_MODE' COL_MAN_GAMUT_REMAP_MODE__enumvalues = { 0: 'GAMUT_REMAP_MODE_BYPASS', 1: 'GAMUT_REMAP_MODE_1', 2: 'GAMUT_REMAP_MODE_2', 3: 'GAMUT_REMAP_MODE_3', } GAMUT_REMAP_MODE_BYPASS = 0 GAMUT_REMAP_MODE_1 = 1 GAMUT_REMAP_MODE_2 = 2 GAMUT_REMAP_MODE_3 = 3 COL_MAN_GAMUT_REMAP_MODE = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_CONTROL_HPD_SEL' DP_AUX_CONTROL_HPD_SEL__enumvalues = { 0: 'DP_AUX_CONTROL_HPD1_SELECTED', 1: 'DP_AUX_CONTROL_HPD2_SELECTED', 2: 'DP_AUX_CONTROL_HPD3_SELECTED', 3: 'DP_AUX_CONTROL_HPD4_SELECTED', 4: 'DP_AUX_CONTROL_HPD5_SELECTED', 5: 'DP_AUX_CONTROL_HPD6_SELECTED', } DP_AUX_CONTROL_HPD1_SELECTED = 0 DP_AUX_CONTROL_HPD2_SELECTED = 1 DP_AUX_CONTROL_HPD3_SELECTED = 2 DP_AUX_CONTROL_HPD4_SELECTED = 3 DP_AUX_CONTROL_HPD5_SELECTED = 4 DP_AUX_CONTROL_HPD6_SELECTED = 5 DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_CONTROL_TEST_MODE' DP_AUX_CONTROL_TEST_MODE__enumvalues = { 0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE', 1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE', } DP_AUX_CONTROL_TEST_MODE_DISABLE = 0 DP_AUX_CONTROL_TEST_MODE_ENABLE = 1 DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_SW_CONTROL_SW_GO' DP_AUX_SW_CONTROL_SW_GO__enumvalues = { 0: 'DP_AUX_SW_CONTROL_SW__NOT_GO', 1: 'DP_AUX_SW_CONTROL_SW__GO', } DP_AUX_SW_CONTROL_SW__NOT_GO = 0 DP_AUX_SW_CONTROL_SW__GO = 1 DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG' DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = { 0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', 1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG', } DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0 DP_AUX_SW_CONTROL_LS_READ__TRIG = 1 DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY' DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = { 0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', 1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', 2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', 3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', } DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0 DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3 DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ' DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = { 0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', 1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', } DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0 DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1 DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG' DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = { 0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', 1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', } DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0 DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1 DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_INT_ACK' DP_AUX_INT_ACK__enumvalues = { 0: 'DP_AUX_INT__NOT_ACK', 1: 'DP_AUX_INT__ACK', } DP_AUX_INT__NOT_ACK = 0 DP_AUX_INT__ACK = 1 DP_AUX_INT_ACK = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_LS_UPDATE_ACK' DP_AUX_LS_UPDATE_ACK__enumvalues = { 0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 1: 'DP_AUX_INT_LS_UPDATE_ACK', } DP_AUX_INT_LS_UPDATE_NOT_ACK = 0 DP_AUX_INT_LS_UPDATE_ACK = 1 DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL' DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = { 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', } DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE' DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = { 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', 2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', 3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', } DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN' DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__enumvalues = { 0: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US', 1: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US', 2: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US', 3: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US', 4: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US', 5: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US', 6: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US', 7: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US', } DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 1 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 2 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 3 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 4 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 5 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 6 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 7 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY' DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = { 0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', 1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', 2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', 3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', 4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', 5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', } DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW' DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = { 0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', 1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', 2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', 3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', 4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', 5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', 6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', 7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', } DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7 DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW' DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = { 0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', 1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', 2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', 3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', 4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', 5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', 6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', 7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', } DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN' DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = { 0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', 1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', 2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', 3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', } DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT' DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = { 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', } DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1 DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START' DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = { 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', } DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1 DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP' DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = { 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', } DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1 DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN' DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = { 0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', 1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', 2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', 3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', } DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN' DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN__enumvalues = { 0: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US', 1: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US', 2: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US', 3: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US', 4: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US', 5: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US', 6: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US', 7: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US', } DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 1 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 2 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 3 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 4 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 5 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 6 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 7 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD' DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = { 0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', 1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', 2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', 3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', 4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', 5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', 6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', 7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', } DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7 DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ' DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = { 0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', 1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', } DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW' DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = { 0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', 1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', 2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', 3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', } DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT' DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = { 0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', 1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', 2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', 3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', } DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN' DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = { 0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', 1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', 2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', 3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', } DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_ERR_OCCURRED_ACK' DP_AUX_ERR_OCCURRED_ACK__enumvalues = { 0: 'DP_AUX_ERR_OCCURRED__NOT_ACK', 1: 'DP_AUX_ERR_OCCURRED__ACK', } DP_AUX_ERR_OCCURRED__NOT_ACK = 0 DP_AUX_ERR_OCCURRED__ACK = 1 DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK' DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = { 0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', } DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0 DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1 DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK' DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = { 0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', } ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0 ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1 DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_RESET' DP_AUX_RESET__enumvalues = { 0: 'DP_AUX_RESET_DEASSERTED', 1: 'DP_AUX_RESET_ASSERTED', } DP_AUX_RESET_DEASSERTED = 0 DP_AUX_RESET_ASSERTED = 1 DP_AUX_RESET = ctypes.c_uint32 # enum # values for enumeration 'DP_AUX_RESET_DONE' DP_AUX_RESET_DONE__enumvalues = { 0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE', 1: 'DP_AUX_RESET_SEQUENCE_DONE', } DP_AUX_RESET_SEQUENCE_NOT_DONE = 0 DP_AUX_RESET_SEQUENCE_DONE = 1 DP_AUX_RESET_DONE = ctypes.c_uint32 # enum # values for enumeration 'DSI_COMMAND_MODE_SRC_FORMAT' DSI_COMMAND_MODE_SRC_FORMAT__enumvalues = { 2: 'DSI_COMMAND_SRC_FORMAT_RGB8BIT', 3: 'DSI_COMMAND_SRC_FORMAT_RGB332', 4: 'DSI_COMMAND_SRC_FORMAT_RGB444', 5: 'DSI_COMMAND_SRC_FORMAT_RGB555', 6: 'DSI_COMMAND_SRC_FORMAT_RGB565', 8: 'DSI_COMMAND_SRC_FORMAT_RGB888', } DSI_COMMAND_SRC_FORMAT_RGB8BIT = 2 DSI_COMMAND_SRC_FORMAT_RGB332 = 3 DSI_COMMAND_SRC_FORMAT_RGB444 = 4 DSI_COMMAND_SRC_FORMAT_RGB555 = 5 DSI_COMMAND_SRC_FORMAT_RGB565 = 6 DSI_COMMAND_SRC_FORMAT_RGB888 = 8 DSI_COMMAND_MODE_SRC_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'DSI_COMMAND_MODE_DST_FORMAT' DSI_COMMAND_MODE_DST_FORMAT__enumvalues = { 0: 'DSI_COMMAND_DST_FORMAT_RGB111', 3: 'DSI_COMMAND_DST_FORMAT_RGB332', 4: 'DSI_COMMAND_DST_FORMAT_RGB444', 6: 'DSI_COMMAND_DST_FORMAT_RGB565', 7: 'DSI_COMMAND_DST_FORMAT_RGB666', 8: 'DSI_COMMAND_DST_FORMAT_RGB888', } DSI_COMMAND_DST_FORMAT_RGB111 = 0 DSI_COMMAND_DST_FORMAT_RGB332 = 3 DSI_COMMAND_DST_FORMAT_RGB444 = 4 DSI_COMMAND_DST_FORMAT_RGB565 = 6 DSI_COMMAND_DST_FORMAT_RGB666 = 7 DSI_COMMAND_DST_FORMAT_RGB888 = 8 DSI_COMMAND_MODE_DST_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'DSI_FLAG_CLR' DSI_FLAG_CLR__enumvalues = { 0: 'DSI_FLAG_NO_CLEAR', 1: 'DSI_FLAG_CLEAR', } DSI_FLAG_NO_CLEAR = 0 DSI_FLAG_CLEAR = 1 DSI_FLAG_CLR = ctypes.c_uint32 # enum # values for enumeration 'DSI_BIT_SWAP' DSI_BIT_SWAP__enumvalues = { 0: 'DSI_BIT_SWAP_DISABLE', 1: 'DSI_BIT_SWAP_ENABLE', } DSI_BIT_SWAP_DISABLE = 0 DSI_BIT_SWAP_ENABLE = 1 DSI_BIT_SWAP = ctypes.c_uint32 # enum # values for enumeration 'DSI_CLK_GATING' DSI_CLK_GATING__enumvalues = { 0: 'DSI_CLK_GATING_ENABLE', 1: 'DSI_CLK_GATING_DISABLE', } DSI_CLK_GATING_ENABLE = 0 DSI_CLK_GATING_DISABLE = 1 DSI_CLK_GATING = ctypes.c_uint32 # enum # values for enumeration 'DSI_LANE_ULPS_REQUEST' DSI_LANE_ULPS_REQUEST__enumvalues = { 0: 'DSI_LANE_ULPS_REQUEST_DEASSERT', 1: 'DSI_LANE_ULPS_REQUEST_ASSERT', } DSI_LANE_ULPS_REQUEST_DEASSERT = 0 DSI_LANE_ULPS_REQUEST_ASSERT = 1 DSI_LANE_ULPS_REQUEST = ctypes.c_uint32 # enum # values for enumeration 'DSI_LANE_ULPS_EXIT' DSI_LANE_ULPS_EXIT__enumvalues = { 0: 'DSI_LANE_ULPS_EXIT_DEASSERT', 1: 'DSI_LANE_ULPS_EXIT_ASSERT', } DSI_LANE_ULPS_EXIT_DEASSERT = 0 DSI_LANE_ULPS_EXIT_ASSERT = 1 DSI_LANE_ULPS_EXIT = ctypes.c_uint32 # enum # values for enumeration 'DSI_LANE_FORCE_TX_STOP' DSI_LANE_FORCE_TX_STOP__enumvalues = { 0: 'DSI_LANE_FORCE_TX_STOP_DEASSERT', 1: 'DSI_LANE_FORCE_TX_STOP_ASSERT', } DSI_LANE_FORCE_TX_STOP_DEASSERT = 0 DSI_LANE_FORCE_TX_STOP_ASSERT = 1 DSI_LANE_FORCE_TX_STOP = ctypes.c_uint32 # enum # values for enumeration 'DSI_CLOCK_LANE_HS_FORCE_REQUEST' DSI_CLOCK_LANE_HS_FORCE_REQUEST__enumvalues = { 0: 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT', 1: 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT', } DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT = 0 DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT = 1 DSI_CLOCK_LANE_HS_FORCE_REQUEST = ctypes.c_uint32 # enum # values for enumeration 'DSI_CONTROLLER_EN' DSI_CONTROLLER_EN__enumvalues = { 0: 'DSI_CONTROLLER_DISABLE', 1: 'DSI_CONTROLLER_ENABLE', } DSI_CONTROLLER_DISABLE = 0 DSI_CONTROLLER_ENABLE = 1 DSI_CONTROLLER_EN = ctypes.c_uint32 # enum # values for enumeration 'DSI_VIDEO_MODE_EN' DSI_VIDEO_MODE_EN__enumvalues = { 0: 'DSI_VIDEO_MODE_DISABLE', 1: 'DSI_VIDEO_MODE_ENABLE', } DSI_VIDEO_MODE_DISABLE = 0 DSI_VIDEO_MODE_ENABLE = 1 DSI_VIDEO_MODE_EN = ctypes.c_uint32 # enum # values for enumeration 'DSI_CMD_MODE_EN' DSI_CMD_MODE_EN__enumvalues = { 0: 'DSI_CMD_MODE_DISABLE', 1: 'DSI_CMD_MODE_ENABLE', } DSI_CMD_MODE_DISABLE = 0 DSI_CMD_MODE_ENABLE = 1 DSI_CMD_MODE_EN = ctypes.c_uint32 # enum # values for enumeration 'DSI_DATA_LANE0_EN' DSI_DATA_LANE0_EN__enumvalues = { 0: 'DSI_DATA_LANE0_DISABLE', 1: 'DSI_DATA_LANE0_ENABLE', } DSI_DATA_LANE0_DISABLE = 0 DSI_DATA_LANE0_ENABLE = 1 DSI_DATA_LANE0_EN = ctypes.c_uint32 # enum # values for enumeration 'DSI_DATA_LANE1_EN' DSI_DATA_LANE1_EN__enumvalues = { 0: 'DSI_DATA_LANE1_DISABLE', 1: 'DSI_DATA_LANE1_ENABLE', } DSI_DATA_LANE1_DISABLE = 0 DSI_DATA_LANE1_ENABLE = 1 DSI_DATA_LANE1_EN = ctypes.c_uint32 # enum # values for enumeration 'DSI_DATA_LANE2_EN' DSI_DATA_LANE2_EN__enumvalues = { 0: 'DSI_DATA_LANE2_DISABLE', 1: 'DSI_DATA_LANE2_ENABLE', } DSI_DATA_LANE2_DISABLE = 0 DSI_DATA_LANE2_ENABLE = 1 DSI_DATA_LANE2_EN = ctypes.c_uint32 # enum # values for enumeration 'DSI_DATA_LANE3_EN' DSI_DATA_LANE3_EN__enumvalues = { 0: 'DSI_DATA_LANE3_DISABLE', 1: 'DSI_DATA_LANE3_ENABLE', } DSI_DATA_LANE3_DISABLE = 0 DSI_DATA_LANE3_ENABLE = 1 DSI_DATA_LANE3_EN = ctypes.c_uint32 # enum # values for enumeration 'DSI_CLOCK_LANE_EN' DSI_CLOCK_LANE_EN__enumvalues = { 0: 'DSI_CLOCK_LANE_DISABLE', 1: 'DSI_CLOCK_LANE_ENABLE', } DSI_CLOCK_LANE_DISABLE = 0 DSI_CLOCK_LANE_ENABLE = 1 DSI_CLOCK_LANE_EN = ctypes.c_uint32 # enum # values for enumeration 'DSI_PHY_DATA_LANE0_EN' DSI_PHY_DATA_LANE0_EN__enumvalues = { 0: 'DSI_PHY_DATA_LANE0_DISABLE', 1: 'DSI_PHY_DATA_LANE0_ENABLE', } DSI_PHY_DATA_LANE0_DISABLE = 0 DSI_PHY_DATA_LANE0_ENABLE = 1 DSI_PHY_DATA_LANE0_EN = ctypes.c_uint32 # enum # values for enumeration 'DSI_PHY_DATA_LANE1_EN' DSI_PHY_DATA_LANE1_EN__enumvalues = { 0: 'DSI_PHY_DATA_LANE1_DISABLE', 1: 'DSI_PHY_DATA_LANE1_ENABLE', } DSI_PHY_DATA_LANE1_DISABLE = 0 DSI_PHY_DATA_LANE1_ENABLE = 1 DSI_PHY_DATA_LANE1_EN = ctypes.c_uint32 # enum # values for enumeration 'DSI_PHY_DATA_LANE2_EN' DSI_PHY_DATA_LANE2_EN__enumvalues = { 0: 'DSI_PHY_DATA_LANE2_DISABLE', 1: 'DSI_PHY_DATA_LANE2_ENABLE', } DSI_PHY_DATA_LANE2_DISABLE = 0 DSI_PHY_DATA_LANE2_ENABLE = 1 DSI_PHY_DATA_LANE2_EN = ctypes.c_uint32 # enum # values for enumeration 'DSI_PHY_DATA_LANE3_EN' DSI_PHY_DATA_LANE3_EN__enumvalues = { 0: 'DSI_PHY_DATA_LANE3_DISABLE', 1: 'DSI_PHY_DATA_LANE3_ENABLE', } DSI_PHY_DATA_LANE3_DISABLE = 0 DSI_PHY_DATA_LANE3_ENABLE = 1 DSI_PHY_DATA_LANE3_EN = ctypes.c_uint32 # enum # values for enumeration 'DSI_RESET_DISPCLK' DSI_RESET_DISPCLK__enumvalues = { 0: 'DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC', 1: 'DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC', } DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0 DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC = 1 DSI_RESET_DISPCLK = ctypes.c_uint32 # enum # values for enumeration 'DSI_RESET_DSICLK' DSI_RESET_DSICLK__enumvalues = { 0: 'DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC', 1: 'DSI_RESET_ON_DSICLK_DOMAIN_LOGIC', } DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC = 0 DSI_RESET_ON_DSICLK_DOMAIN_LOGIC = 1 DSI_RESET_DSICLK = ctypes.c_uint32 # enum # values for enumeration 'DSI_RESET_BYTECLK' DSI_RESET_BYTECLK__enumvalues = { 0: 'DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC', 1: 'DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC', } DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0 DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC = 1 DSI_RESET_BYTECLK = ctypes.c_uint32 # enum # values for enumeration 'DSI_RESET_ESCCLK' DSI_RESET_ESCCLK__enumvalues = { 0: 'DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC', 1: 'DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC', } DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0 DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC = 1 DSI_RESET_ESCCLK = ctypes.c_uint32 # enum # values for enumeration 'DSI_CRTC_SEL' DSI_CRTC_SEL__enumvalues = { 0: 'DSI_GET_PIXEL_STREAM_FROM_FMT0', 1: 'DSI_GET_PIXEL_STREAM_FROM_FMT1', 2: 'DSI_GET_PIXEL_STREAM_FROM_FMT2', 3: 'DSI_GET_PIXEL_STREAM_FROM_FMT3', 4: 'DSI_GET_PIXEL_STREAM_FROM_FMT4', 5: 'DSI_GET_PIXEL_STREAM_FROM_FMT5', } DSI_GET_PIXEL_STREAM_FROM_FMT0 = 0 DSI_GET_PIXEL_STREAM_FROM_FMT1 = 1 DSI_GET_PIXEL_STREAM_FROM_FMT2 = 2 DSI_GET_PIXEL_STREAM_FROM_FMT3 = 3 DSI_GET_PIXEL_STREAM_FROM_FMT4 = 4 DSI_GET_PIXEL_STREAM_FROM_FMT5 = 5 DSI_CRTC_SEL = ctypes.c_uint32 # enum # values for enumeration 'DSI_PACKET_BYTE_MSB_LSB_FLIP' DSI_PACKET_BYTE_MSB_LSB_FLIP__enumvalues = { 0: 'DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP', 1: 'DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP', } DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP = 0 DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP = 1 DSI_PACKET_BYTE_MSB_LSB_FLIP = ctypes.c_uint32 # enum # values for enumeration 'DSI_VIDEO_MODE_DST_FORMAT' DSI_VIDEO_MODE_DST_FORMAT__enumvalues = { 0: 'DSI_VIDEO_DST_FORMAT_RGB565', 1: 'DSI_VIDEO_DST_FORMAT_RGB666_PACKED', 2: 'DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED', 3: 'DSI_VIDEO_DST_FORMAT_RGB888', } DSI_VIDEO_DST_FORMAT_RGB565 = 0 DSI_VIDEO_DST_FORMAT_RGB666_PACKED = 1 DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED = 2 DSI_VIDEO_DST_FORMAT_RGB888 = 3 DSI_VIDEO_MODE_DST_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'DSI_VIDEO_TRAFFIC_MODE' DSI_VIDEO_TRAFFIC_MODE__enumvalues = { 0: 'DSI_TRAFFIC_MODE_SYNC_PULSES', 1: 'DSI_TRAFFIC_MODE_SYNC_EVENTS', 2: 'DSI_TRAFFIC_MODE_BURST', 3: 'DSI_TRAFFIC_MODE_RESERVED', } DSI_TRAFFIC_MODE_SYNC_PULSES = 0 DSI_TRAFFIC_MODE_SYNC_EVENTS = 1 DSI_TRAFFIC_MODE_BURST = 2 DSI_TRAFFIC_MODE_RESERVED = 3 DSI_VIDEO_TRAFFIC_MODE = ctypes.c_uint32 # enum # values for enumeration 'DSI_VIDEO_BLLP_PWR_MODE' DSI_VIDEO_BLLP_PWR_MODE__enumvalues = { 0: 'DSI_VIDEO_BLLP_PWR_MODE_HS', 1: 'DSI_VIDEO_BLLP_PWR_MODE_LP', } DSI_VIDEO_BLLP_PWR_MODE_HS = 0 DSI_VIDEO_BLLP_PWR_MODE_LP = 1 DSI_VIDEO_BLLP_PWR_MODE = ctypes.c_uint32 # enum # values for enumeration 'DSI_VIDEO_EOF_BLLP_PWR_MODE' DSI_VIDEO_EOF_BLLP_PWR_MODE__enumvalues = { 0: 'DSI_VIDEO_EOF_BLLP_PWR_MODE_HS', 1: 'DSI_VIDEO_EOF_BLLP_PWR_MODE_LP', } DSI_VIDEO_EOF_BLLP_PWR_MODE_HS = 0 DSI_VIDEO_EOF_BLLP_PWR_MODE_LP = 1 DSI_VIDEO_EOF_BLLP_PWR_MODE = ctypes.c_uint32 # enum # values for enumeration 'DSI_VIDEO_PWR_MODE' DSI_VIDEO_PWR_MODE__enumvalues = { 0: 'DSI_VIDEO_PWR_MODE_HS', 1: 'DSI_VIDEO_PWR_MODE_LP', } DSI_VIDEO_PWR_MODE_HS = 0 DSI_VIDEO_PWR_MODE_LP = 1 DSI_VIDEO_PWR_MODE = ctypes.c_uint32 # enum # values for enumeration 'DSI_VIDEO_PULSE_MODE_OPT' DSI_VIDEO_PULSE_MODE_OPT__enumvalues = { 0: 'PULSE_MODE_OPT_NO_HSA', 1: 'PULSE_MODE_OPT_SEND', } PULSE_MODE_OPT_NO_HSA = 0 PULSE_MODE_OPT_SEND = 1 DSI_VIDEO_PULSE_MODE_OPT = ctypes.c_uint32 # enum # values for enumeration 'DSI_RGB_SWAP' DSI_RGB_SWAP__enumvalues = { 0: 'DSI_SWAP_RGB', 1: 'DSI_SWAP_RBG', 2: 'DSI_SWAP_BGR', 3: 'DSI_SWAP_BRG', 4: 'DSI_SWAP_GRB', 5: 'DSI_SWAP_GBR', } DSI_SWAP_RGB = 0 DSI_SWAP_RBG = 1 DSI_SWAP_BGR = 2 DSI_SWAP_BRG = 3 DSI_SWAP_GRB = 4 DSI_SWAP_GBR = 5 DSI_RGB_SWAP = ctypes.c_uint32 # enum # values for enumeration 'DSI_CMD_PACKET_TYPE' DSI_CMD_PACKET_TYPE__enumvalues = { 0: 'DSI_CMD_PACKET_TYPE_SHORT', 1: 'DSI_CMD_PACKET_TYPE_LONG', } DSI_CMD_PACKET_TYPE_SHORT = 0 DSI_CMD_PACKET_TYPE_LONG = 1 DSI_CMD_PACKET_TYPE = ctypes.c_uint32 # enum # values for enumeration 'DSI_CMD_PWR_MODE' DSI_CMD_PWR_MODE__enumvalues = { 0: 'DSI_CMD_PWR_MODE_HS', 1: 'DSI_CMD_PWR_MODE_LP', } DSI_CMD_PWR_MODE_HS = 0 DSI_CMD_PWR_MODE_LP = 1 DSI_CMD_PWR_MODE = ctypes.c_uint32 # enum # values for enumeration 'DSI_CMD_EMBEDDED_MODE' DSI_CMD_EMBEDDED_MODE__enumvalues = { 0: 'CMD_EMBEDDED_MODE_DISABLE', 1: 'CMD_EMBEDDED_MODE_ENABLE', } CMD_EMBEDDED_MODE_DISABLE = 0 CMD_EMBEDDED_MODE_ENABLE = 1 DSI_CMD_EMBEDDED_MODE = ctypes.c_uint32 # enum # values for enumeration 'DSI_CMD_ORDER' DSI_CMD_ORDER__enumvalues = { 0: 'DSI_CMD_ORDER_COMMAND_FIRST', 1: 'DSI_CMD_ORDER_DATA_FIRST', } DSI_CMD_ORDER_COMMAND_FIRST = 0 DSI_CMD_ORDER_DATA_FIRST = 1 DSI_CMD_ORDER = ctypes.c_uint32 # enum # values for enumeration 'DSI_DATA_BUFFER_ID' DSI_DATA_BUFFER_ID__enumvalues = { 0: 'DSI_DATA_BUFFER_OFFSET0', 1: 'DSI_DATA_BUFFER_OFFSET1', } DSI_DATA_BUFFER_OFFSET0 = 0 DSI_DATA_BUFFER_OFFSET1 = 1 DSI_DATA_BUFFER_ID = ctypes.c_uint32 # enum # values for enumeration 'DSI_DWORD_BYTE_SWAP' DSI_DWORD_BYTE_SWAP__enumvalues = { 0: 'DWORD_BYTE_SWAP_NO_SWAP', 1: 'DWORD_BYTE_SWAP_BYTE_SWAP', 2: 'DWORD_BYTE_SWAP_WORD_SWAP', 3: 'DWORD_BYTE_SWAP_BOTH_SWAP', } DWORD_BYTE_SWAP_NO_SWAP = 0 DWORD_BYTE_SWAP_BYTE_SWAP = 1 DWORD_BYTE_SWAP_WORD_SWAP = 2 DWORD_BYTE_SWAP_BOTH_SWAP = 3 DSI_DWORD_BYTE_SWAP = ctypes.c_uint32 # enum # values for enumeration 'DSI_INSERT_DCS_COMMAND' DSI_INSERT_DCS_COMMAND__enumvalues = { 0: 'DSI_INSERT_DCS_COMMAND_DISABLE', 1: 'DSI_INSERT_DCS_COMMAND_ENABLE', } DSI_INSERT_DCS_COMMAND_DISABLE = 0 DSI_INSERT_DCS_COMMAND_ENABLE = 1 DSI_INSERT_DCS_COMMAND = ctypes.c_uint32 # enum # values for enumeration 'DSI_DMAFIFO_WRITE_WATERMARK' DSI_DMAFIFO_WRITE_WATERMARK__enumvalues = { 0: 'DSI_DMAFIFO_WRITE_WATERMARK_HALF', 1: 'DSI_DMAFIFO_WRITE_WATERMARK_FOURTH', 2: 'DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH', 3: 'DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH', } DSI_DMAFIFO_WRITE_WATERMARK_HALF = 0 DSI_DMAFIFO_WRITE_WATERMARK_FOURTH = 1 DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH = 2 DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH = 3 DSI_DMAFIFO_WRITE_WATERMARK = ctypes.c_uint32 # enum # values for enumeration 'DSI_DMAFIFO_READ_WATERMARK' DSI_DMAFIFO_READ_WATERMARK__enumvalues = { 0: 'DSI_DMAFIFO_READ_WATERMARK_HALF', 1: 'DSI_DMAFIFO_READ_WATERMARK_FOURTH', 2: 'DSI_DMAFIFO_READ_WATERMARK_EIGHTH', 3: 'DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH', } DSI_DMAFIFO_READ_WATERMARK_HALF = 0 DSI_DMAFIFO_READ_WATERMARK_FOURTH = 1 DSI_DMAFIFO_READ_WATERMARK_EIGHTH = 2 DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH = 3 DSI_DMAFIFO_READ_WATERMARK = ctypes.c_uint32 # enum # values for enumeration 'DSI_USE_DENG_LENGTH' DSI_USE_DENG_LENGTH__enumvalues = { 0: 'DSI_USE_DENG_LENGTH_DISABLE', 1: 'DSI_USE_DENG_LENGTH_ENABLE', } DSI_USE_DENG_LENGTH_DISABLE = 0 DSI_USE_DENG_LENGTH_ENABLE = 1 DSI_USE_DENG_LENGTH = ctypes.c_uint32 # enum # values for enumeration 'DSI_COMMAND_TRIGGER_MODE' DSI_COMMAND_TRIGGER_MODE__enumvalues = { 0: 'DSI_COMMAND_TRIGGER_MODE_AUTO', 1: 'DSI_COMMAND_TRIGGER_MODE_MANUAL', } DSI_COMMAND_TRIGGER_MODE_AUTO = 0 DSI_COMMAND_TRIGGER_MODE_MANUAL = 1 DSI_COMMAND_TRIGGER_MODE = ctypes.c_uint32 # enum # values for enumeration 'DSI_COMMAND_TRIGGER_SEL' DSI_COMMAND_TRIGGER_SEL__enumvalues = { 0: 'DSI_COMMAND_TRIGGER_SEL_NONE', 1: 'DSI_COMMAND_TRIGGER_SEL_CRTC', 2: 'DSI_COMMAND_TRIGGER_SEL_TE', 3: 'DSI_COMMAND_TRIGGER_SEL_HW', } DSI_COMMAND_TRIGGER_SEL_NONE = 0 DSI_COMMAND_TRIGGER_SEL_CRTC = 1 DSI_COMMAND_TRIGGER_SEL_TE = 2 DSI_COMMAND_TRIGGER_SEL_HW = 3 DSI_COMMAND_TRIGGER_SEL = ctypes.c_uint32 # enum # values for enumeration 'DSI_HW_SOURCE_SEL' DSI_HW_SOURCE_SEL__enumvalues = { 0: 'HW_SOURCE_SEL_NONE', 1: 'HW_SOURCE_SEL_DSC_VUP', 2: 'HW_SOURCE_SEL_DSC_VLP', 3: 'HW_SOURCE_SEL_DSC_JPEG', } HW_SOURCE_SEL_NONE = 0 HW_SOURCE_SEL_DSC_VUP = 1 HW_SOURCE_SEL_DSC_VLP = 2 HW_SOURCE_SEL_DSC_JPEG = 3 DSI_HW_SOURCE_SEL = ctypes.c_uint32 # enum # values for enumeration 'DSI_COMMAND_TRIGGER_ORDER' DSI_COMMAND_TRIGGER_ORDER__enumvalues = { 0: 'DSI_COMMAND_TRIGGER_ORDER_DMA', 1: 'DSI_COMMAND_TRIGGER_ORDER_DENG', } DSI_COMMAND_TRIGGER_ORDER_DMA = 0 DSI_COMMAND_TRIGGER_ORDER_DENG = 1 DSI_COMMAND_TRIGGER_ORDER = ctypes.c_uint32 # enum # values for enumeration 'DSI_TE_SRC_SEL' DSI_TE_SRC_SEL__enumvalues = { 0: 'DSI_TE_SEL_LINK', 1: 'DSI_TE_SEL_PIN', } DSI_TE_SEL_LINK = 0 DSI_TE_SEL_PIN = 1 DSI_TE_SRC_SEL = ctypes.c_uint32 # enum # values for enumeration 'DSI_EXT_TE_MUX' DSI_EXT_TE_MUX__enumvalues = { 0: 'DSI_XT_TE_MUX_LCDD17', 1: 'DSI_XT_TE_MUX_DCLK', 2: 'DSI_XT_TE_MUX_SS', 3: 'DSI_XT_TE_MUX_GCLK', 4: 'DSI_XT_TE_MUX_GOE', 5: 'DSI_XT_TE_MUX_DINV', 6: 'DSI_XT_TE_MUX_FRAME', 7: 'DSI_XT_TE_MUX_GPIO4', 8: 'DSI_XT_TE_MUX_GPIO5', } DSI_XT_TE_MUX_LCDD17 = 0 DSI_XT_TE_MUX_DCLK = 1 DSI_XT_TE_MUX_SS = 2 DSI_XT_TE_MUX_GCLK = 3 DSI_XT_TE_MUX_GOE = 4 DSI_XT_TE_MUX_DINV = 5 DSI_XT_TE_MUX_FRAME = 6 DSI_XT_TE_MUX_GPIO4 = 7 DSI_XT_TE_MUX_GPIO5 = 8 DSI_EXT_TE_MUX = ctypes.c_uint32 # enum # values for enumeration 'DSI_EXT_TE_MODE' DSI_EXT_TE_MODE__enumvalues = { 0: 'DSI_EXT_TE_MODE_VSYNC_EDGE', 1: 'DSI_EXT_TE_MODE_VSYNC_WIDTH', 2: 'DSI_EXT_TE_MODE_HVSYNC_EDGE', 3: 'DSI_EXT_TE_MODE_HVSYNC_WIDTH', } DSI_EXT_TE_MODE_VSYNC_EDGE = 0 DSI_EXT_TE_MODE_VSYNC_WIDTH = 1 DSI_EXT_TE_MODE_HVSYNC_EDGE = 2 DSI_EXT_TE_MODE_HVSYNC_WIDTH = 3 DSI_EXT_TE_MODE = ctypes.c_uint32 # enum # values for enumeration 'DSI_EXT_RESET_POL' DSI_EXT_RESET_POL__enumvalues = { 0: 'DSI_EXT_RESET_POL_HIGH', 1: 'DSI_EXT_RESET_POL_LOW', } DSI_EXT_RESET_POL_HIGH = 0 DSI_EXT_RESET_POL_LOW = 1 DSI_EXT_RESET_POL = ctypes.c_uint32 # enum # values for enumeration 'DSI_EXT_TE_POL' DSI_EXT_TE_POL__enumvalues = { 0: 'DSI_EXT_TE_POL_RISING', 1: 'DSI_EXT_TE_POL_FALLING', } DSI_EXT_TE_POL_RISING = 0 DSI_EXT_TE_POL_FALLING = 1 DSI_EXT_TE_POL = ctypes.c_uint32 # enum # values for enumeration 'DSI_RESET_PANEL' DSI_RESET_PANEL__enumvalues = { 0: 'DSI_RESET_PANEL_DEASSERT', 1: 'DSI_RESET_PANEL_ASSERT', } DSI_RESET_PANEL_DEASSERT = 0 DSI_RESET_PANEL_ASSERT = 1 DSI_RESET_PANEL = ctypes.c_uint32 # enum # values for enumeration 'DSI_CRC_ENABLE' DSI_CRC_ENABLE__enumvalues = { 0: 'DSI_CRC_CAL_DISABLE', 1: 'DSI_CRC_CAL_ENABLE', } DSI_CRC_CAL_DISABLE = 0 DSI_CRC_CAL_ENABLE = 1 DSI_CRC_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DSI_TX_EOT_APPEND' DSI_TX_EOT_APPEND__enumvalues = { 0: 'DSI_TX_EOT_APPEND_DISABLE', 1: 'DSI_TX_EOT_APPEND_ENABLE', } DSI_TX_EOT_APPEND_DISABLE = 0 DSI_TX_EOT_APPEND_ENABLE = 1 DSI_TX_EOT_APPEND = ctypes.c_uint32 # enum # values for enumeration 'DSI_RX_EOT_IGNORE' DSI_RX_EOT_IGNORE__enumvalues = { 0: 'DSI_RX_EOT_IGNORE_DISABLE', 1: 'DSI_RX_EOT_IGNORE_ENABLE', } DSI_RX_EOT_IGNORE_DISABLE = 0 DSI_RX_EOT_IGNORE_ENABLE = 1 DSI_RX_EOT_IGNORE = ctypes.c_uint32 # enum # values for enumeration 'DSI_MIPI_BIST_RESET' DSI_MIPI_BIST_RESET__enumvalues = { 0: 'DSI_MIPI_BIST_RESET_DEASSERT', 1: 'DSI_MIPI_BIST_RESET_ASSERT', } DSI_MIPI_BIST_RESET_DEASSERT = 0 DSI_MIPI_BIST_RESET_ASSERT = 1 DSI_MIPI_BIST_RESET = ctypes.c_uint32 # enum # values for enumeration 'DSI_MIPI_BIST_VIDEO_FRMT' DSI_MIPI_BIST_VIDEO_FRMT__enumvalues = { 0: 'DSI_MIPI_BIST_VIDEO_FRMT_YUV422', 1: 'DSI_MIPI_BIST_VIDEO_FRMT_RAW8', } DSI_MIPI_BIST_VIDEO_FRMT_YUV422 = 0 DSI_MIPI_BIST_VIDEO_FRMT_RAW8 = 1 DSI_MIPI_BIST_VIDEO_FRMT = ctypes.c_uint32 # enum # values for enumeration 'DSI_MIPI_BIST_START' DSI_MIPI_BIST_START__enumvalues = { 0: 'DSI_MIPI_BIST_START_DEASSERT', 1: 'DSI_MIPI_BIST_START_ASSERT', } DSI_MIPI_BIST_START_DEASSERT = 0 DSI_MIPI_BIST_START_ASSERT = 1 DSI_MIPI_BIST_START = ctypes.c_uint32 # enum # values for enumeration 'DSI_DBG_CLK_SEL' DSI_DBG_CLK_SEL__enumvalues = { 0: 'DSI_TEST_CLK_SEL_DISPCLK_P', 1: 'DSI_TEST_CLK_SEL_DISPCLK_G', 2: 'DSI_TEST_CLK_SEL_DISPCLK_R', 3: 'DSI_TEST_CLK_SEL_ESCCLK_G', 4: 'DSI_TEST_CLK_SEL_BYTECLK_G', 5: 'DSI_TEST_CLK_SEL_DSICLK_P', 6: 'DSI_TEST_CLK_SEL_DSICLK_R', 7: 'DSI_TEST_CLK_SEL_DSICLK_G', 8: 'DSI_TEST_CLK_SEL_DSICLK_TRN', } DSI_TEST_CLK_SEL_DISPCLK_P = 0 DSI_TEST_CLK_SEL_DISPCLK_G = 1 DSI_TEST_CLK_SEL_DISPCLK_R = 2 DSI_TEST_CLK_SEL_ESCCLK_G = 3 DSI_TEST_CLK_SEL_BYTECLK_G = 4 DSI_TEST_CLK_SEL_DSICLK_P = 5 DSI_TEST_CLK_SEL_DSICLK_R = 6 DSI_TEST_CLK_SEL_DSICLK_G = 7 DSI_TEST_CLK_SEL_DSICLK_TRN = 8 DSI_DBG_CLK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DSI_DENG_FIFO_USE_OVERWRITE_LEVEL' DSI_DENG_FIFO_USE_OVERWRITE_LEVEL__enumvalues = { 0: 'DSI_DENG_FIFO_LEVEL_OVERWRITE', 1: 'DSI_DENG_FIFO_LEVEL_CAL_AVERAGE', } DSI_DENG_FIFO_LEVEL_OVERWRITE = 0 DSI_DENG_FIFO_LEVEL_CAL_AVERAGE = 1 DSI_DENG_FIFO_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum # values for enumeration 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE' DSI_DENG_FIFO_FORCE_RECAL_AVERAGE__enumvalues = { 0: 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT', 1: 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT', } DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT = 0 DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT = 1 DSI_DENG_FIFO_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum # values for enumeration 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX' DSI_DENG_FIFO_FORCE_RECOMP_MINMAX__enumvalues = { 0: 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT', 1: 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT', } DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT = 0 DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT = 1 DSI_DENG_FIFO_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum # values for enumeration 'DSI_DENG_FIFO_START' DSI_DENG_FIFO_START__enumvalues = { 0: 'DSI_DENG_FIFO_START_DEASSERT', 1: 'DSI_DENG_FIFO_START_ASSERT', } DSI_DENG_FIFO_START_DEASSERT = 0 DSI_DENG_FIFO_START_ASSERT = 1 DSI_DENG_FIFO_START = ctypes.c_uint32 # enum # values for enumeration 'DSI_USE_CMDFIFO' DSI_USE_CMDFIFO__enumvalues = { 0: 'DSI_CMD_USE_DMAFIFO', 1: 'DSI_CMD_USE_CMDFIFO', } DSI_CMD_USE_DMAFIFO = 0 DSI_CMD_USE_CMDFIFO = 1 DSI_USE_CMDFIFO = ctypes.c_uint32 # enum # values for enumeration 'DSI_CRTC_FREEZE_TRIG' DSI_CRTC_FREEZE_TRIG__enumvalues = { 0: 'DSI_CRTC_FREEZE_TRIG_DEASSERT', 1: 'DSI_CRTC_FREEZE_TRIG_ASSERT', } DSI_CRTC_FREEZE_TRIG_DEASSERT = 0 DSI_CRTC_FREEZE_TRIG_ASSERT = 1 DSI_CRTC_FREEZE_TRIG = ctypes.c_uint32 # enum # values for enumeration 'DSI_PERF_LATENCY_SEL' DSI_PERF_LATENCY_SEL__enumvalues = { 0: 'DSI_PERF_LATENCY_SEL_DATA_LANE0', 1: 'DSI_PERF_LATENCY_SEL_DATA_LANE1', 2: 'DSI_PERF_LATENCY_SEL_DATA_LANE2', 3: 'DSI_PERF_LATENCY_SEL_DATA_LANE3', } DSI_PERF_LATENCY_SEL_DATA_LANE0 = 0 DSI_PERF_LATENCY_SEL_DATA_LANE1 = 1 DSI_PERF_LATENCY_SEL_DATA_LANE2 = 2 DSI_PERF_LATENCY_SEL_DATA_LANE3 = 3 DSI_PERF_LATENCY_SEL = ctypes.c_uint32 # enum # values for enumeration 'DSI_DEBUG_DSICLK_SEL' DSI_DEBUG_DSICLK_SEL__enumvalues = { 0: 'DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE', 1: 'DSI_DEBUG_DSICLK_SEL_CMD_ENGINE', 2: 'DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO', 3: 'DSI_DEBUG_DSICLK_SEL_CMDFIFO', 4: 'DSI_DEBUG_DSICLK_SEL_CMDBUFFER', 5: 'DSI_DEBUG_DSICLK_SEL_AFIFO', 6: 'DSI_DEBUG_DSICLK_SEL_LANECTRL', } DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE = 0 DSI_DEBUG_DSICLK_SEL_CMD_ENGINE = 1 DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO = 2 DSI_DEBUG_DSICLK_SEL_CMDFIFO = 3 DSI_DEBUG_DSICLK_SEL_CMDBUFFER = 4 DSI_DEBUG_DSICLK_SEL_AFIFO = 5 DSI_DEBUG_DSICLK_SEL_LANECTRL = 6 DSI_DEBUG_DSICLK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DSI_DEBUG_BYTECLK_SEL' DSI_DEBUG_BYTECLK_SEL__enumvalues = { 0: 'DSI_DEBUG_BYTECLK_SEL_AFIFO', 1: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO0', 2: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO1', 3: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO2', 4: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO3', 5: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF0', 6: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF1', 7: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF2', 8: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF3', 9: 'DSI_DEBUG_BYTECLK_SEL_PINGPONG0', 10: 'DSI_DEBUG_BYTECLK_SEL_PINGPONG1', 11: 'DSI_DEBUG_BYTECLK_SEL_PINGPING2', 12: 'DSI_DEBUG_BYTECLK_SEL_PINGPING3', 13: 'DSI_DEBUG_BYTECLK_SEL_EOT', 14: 'DSI_DEBUG_BYTECLK_SEL_LANECTRL', } DSI_DEBUG_BYTECLK_SEL_AFIFO = 0 DSI_DEBUG_BYTECLK_SEL_LANEFIFO0 = 1 DSI_DEBUG_BYTECLK_SEL_LANEFIFO1 = 2 DSI_DEBUG_BYTECLK_SEL_LANEFIFO2 = 3 DSI_DEBUG_BYTECLK_SEL_LANEFIFO3 = 4 DSI_DEBUG_BYTECLK_SEL_LANEBUF0 = 5 DSI_DEBUG_BYTECLK_SEL_LANEBUF1 = 6 DSI_DEBUG_BYTECLK_SEL_LANEBUF2 = 7 DSI_DEBUG_BYTECLK_SEL_LANEBUF3 = 8 DSI_DEBUG_BYTECLK_SEL_PINGPONG0 = 9 DSI_DEBUG_BYTECLK_SEL_PINGPONG1 = 10 DSI_DEBUG_BYTECLK_SEL_PINGPING2 = 11 DSI_DEBUG_BYTECLK_SEL_PINGPING3 = 12 DSI_DEBUG_BYTECLK_SEL_EOT = 13 DSI_DEBUG_BYTECLK_SEL_LANECTRL = 14 DSI_DEBUG_BYTECLK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_HPD_SEL' DCIOCHIP_HPD_SEL__enumvalues = { 0: 'DCIOCHIP_HPD_SEL_ASYNC', 1: 'DCIOCHIP_HPD_SEL_CLOCKED', } DCIOCHIP_HPD_SEL_ASYNC = 0 DCIOCHIP_HPD_SEL_CLOCKED = 1 DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_PAD_MODE' DCIOCHIP_PAD_MODE__enumvalues = { 0: 'DCIOCHIP_PAD_MODE_DDC', 1: 'DCIOCHIP_PAD_MODE_DP', } DCIOCHIP_PAD_MODE_DDC = 0 DCIOCHIP_PAD_MODE_DP = 1 DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_AUXSLAVE_PAD_MODE' DCIOCHIP_AUXSLAVE_PAD_MODE__enumvalues = { 0: 'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C', 1: 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX', } DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0 DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 1 DCIOCHIP_AUXSLAVE_PAD_MODE = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_INVERT' DCIOCHIP_INVERT__enumvalues = { 0: 'DCIOCHIP_POL_NON_INVERT', 1: 'DCIOCHIP_POL_INVERT', } DCIOCHIP_POL_NON_INVERT = 0 DCIOCHIP_POL_INVERT = 1 DCIOCHIP_INVERT = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_PD_EN' DCIOCHIP_PD_EN__enumvalues = { 0: 'DCIOCHIP_PD_EN_NOTALLOW', 1: 'DCIOCHIP_PD_EN_ALLOW', } DCIOCHIP_PD_EN_NOTALLOW = 0 DCIOCHIP_PD_EN_ALLOW = 1 DCIOCHIP_PD_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_GPIO_MASK_EN' DCIOCHIP_GPIO_MASK_EN__enumvalues = { 0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', 1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', } DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0 DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1 DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_MASK' DCIOCHIP_MASK__enumvalues = { 0: 'DCIOCHIP_MASK_DISABLE', 1: 'DCIOCHIP_MASK_ENABLE', } DCIOCHIP_MASK_DISABLE = 0 DCIOCHIP_MASK_ENABLE = 1 DCIOCHIP_MASK = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_GPIO_I2C_MASK' DCIOCHIP_GPIO_I2C_MASK__enumvalues = { 0: 'DCIOCHIP_GPIO_I2C_MASK_DISABLE', 1: 'DCIOCHIP_GPIO_I2C_MASK_ENABLE', } DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0 DCIOCHIP_GPIO_I2C_MASK_ENABLE = 1 DCIOCHIP_GPIO_I2C_MASK = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_GPIO_I2C_DRIVE' DCIOCHIP_GPIO_I2C_DRIVE__enumvalues = { 0: 'DCIOCHIP_GPIO_I2C_DRIVE_LOW', 1: 'DCIOCHIP_GPIO_I2C_DRIVE_HIGH', } DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0 DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 1 DCIOCHIP_GPIO_I2C_DRIVE = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_GPIO_I2C_EN' DCIOCHIP_GPIO_I2C_EN__enumvalues = { 0: 'DCIOCHIP_GPIO_I2C_DISABLE', 1: 'DCIOCHIP_GPIO_I2C_ENABLE', } DCIOCHIP_GPIO_I2C_DISABLE = 0 DCIOCHIP_GPIO_I2C_ENABLE = 1 DCIOCHIP_GPIO_I2C_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_MASK_4BIT' DCIOCHIP_MASK_4BIT__enumvalues = { 0: 'DCIOCHIP_MASK_4BIT_DISABLE', 15: 'DCIOCHIP_MASK_4BIT_ENABLE', } DCIOCHIP_MASK_4BIT_DISABLE = 0 DCIOCHIP_MASK_4BIT_ENABLE = 15 DCIOCHIP_MASK_4BIT = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_ENABLE_4BIT' DCIOCHIP_ENABLE_4BIT__enumvalues = { 0: 'DCIOCHIP_4BIT_DISABLE', 15: 'DCIOCHIP_4BIT_ENABLE', } DCIOCHIP_4BIT_DISABLE = 0 DCIOCHIP_4BIT_ENABLE = 15 DCIOCHIP_ENABLE_4BIT = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_MASK_5BIT' DCIOCHIP_MASK_5BIT__enumvalues = { 0: 'DCIOCHIP_MASIK_5BIT_DISABLE', 31: 'DCIOCHIP_MASIK_5BIT_ENABLE', } DCIOCHIP_MASIK_5BIT_DISABLE = 0 DCIOCHIP_MASIK_5BIT_ENABLE = 31 DCIOCHIP_MASK_5BIT = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_ENABLE_5BIT' DCIOCHIP_ENABLE_5BIT__enumvalues = { 0: 'DCIOCHIP_5BIT_DISABLE', 31: 'DCIOCHIP_5BIT_ENABLE', } DCIOCHIP_5BIT_DISABLE = 0 DCIOCHIP_5BIT_ENABLE = 31 DCIOCHIP_ENABLE_5BIT = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_MASK_2BIT' DCIOCHIP_MASK_2BIT__enumvalues = { 0: 'DCIOCHIP_MASK_2BIT_DISABLE', 3: 'DCIOCHIP_MASK_2BIT_ENABLE', } DCIOCHIP_MASK_2BIT_DISABLE = 0 DCIOCHIP_MASK_2BIT_ENABLE = 3 DCIOCHIP_MASK_2BIT = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_ENABLE_2BIT' DCIOCHIP_ENABLE_2BIT__enumvalues = { 0: 'DCIOCHIP_2BIT_DISABLE', 3: 'DCIOCHIP_2BIT_ENABLE', } DCIOCHIP_2BIT_DISABLE = 0 DCIOCHIP_2BIT_ENABLE = 3 DCIOCHIP_ENABLE_2BIT = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_REF_27_SRC_SEL' DCIOCHIP_REF_27_SRC_SEL__enumvalues = { 0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', 1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', 2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', 3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', } DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1 DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3 DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_DVO_VREFPON' DCIOCHIP_DVO_VREFPON__enumvalues = { 0: 'DCIOCHIP_DVO_VREFPON_DISABLE', 1: 'DCIOCHIP_DVO_VREFPON_ENABLE', } DCIOCHIP_DVO_VREFPON_DISABLE = 0 DCIOCHIP_DVO_VREFPON_ENABLE = 1 DCIOCHIP_DVO_VREFPON = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_DVO_VREFSEL' DCIOCHIP_DVO_VREFSEL__enumvalues = { 0: 'DCIOCHIP_DVO_VREFSEL_ONCHIP', 1: 'DCIOCHIP_DVO_VREFSEL_EXTERNAL', } DCIOCHIP_DVO_VREFSEL_ONCHIP = 0 DCIOCHIP_DVO_VREFSEL_EXTERNAL = 1 DCIOCHIP_DVO_VREFSEL = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_SPDIF1_IMODE' DCIOCHIP_SPDIF1_IMODE__enumvalues = { 0: 'DCIOCHIP_SPDIF1_IMODE_OE_A', 1: 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO', } DCIOCHIP_SPDIF1_IMODE_OE_A = 0 DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 1 DCIOCHIP_SPDIF1_IMODE = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL' DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = { 0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', 1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', 2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', } DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0 DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1 DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2 DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3 DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_AUX_SPIKESEL' DCIOCHIP_AUX_SPIKESEL__enumvalues = { 0: 'DCIOCHIP_AUX_SPIKESEL_50NS', 1: 'DCIOCHIP_AUX_SPIKESEL_10NS', } DCIOCHIP_AUX_SPIKESEL_50NS = 0 DCIOCHIP_AUX_SPIKESEL_10NS = 1 DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_AUX_CSEL0P9' DCIOCHIP_AUX_CSEL0P9__enumvalues = { 0: 'DCIOCHIP_AUX_CSEL_DEC1P0', 1: 'DCIOCHIP_AUX_CSEL_DEC0P9', } DCIOCHIP_AUX_CSEL_DEC1P0 = 0 DCIOCHIP_AUX_CSEL_DEC0P9 = 1 DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_AUX_CSEL1P1' DCIOCHIP_AUX_CSEL1P1__enumvalues = { 0: 'DCIOCHIP_AUX_CSEL_INC1P0', 1: 'DCIOCHIP_AUX_CSEL_INC1P1', } DCIOCHIP_AUX_CSEL_INC1P0 = 0 DCIOCHIP_AUX_CSEL_INC1P1 = 1 DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_AUX_RSEL0P9' DCIOCHIP_AUX_RSEL0P9__enumvalues = { 0: 'DCIOCHIP_AUX_RSEL_DEC1P0', 1: 'DCIOCHIP_AUX_RSEL_DEC0P9', } DCIOCHIP_AUX_RSEL_DEC1P0 = 0 DCIOCHIP_AUX_RSEL_DEC0P9 = 1 DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum # values for enumeration 'DCIOCHIP_AUX_RSEL1P1' DCIOCHIP_AUX_RSEL1P1__enumvalues = { 0: 'DCIOCHIP_AUX_RSEL_INC1P0', 1: 'DCIOCHIP_AUX_RSEL_INC1P1', } DCIOCHIP_AUX_RSEL_INC1P0 = 0 DCIOCHIP_AUX_RSEL_INC1P1 = 1 DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum # values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL' GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = { 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', } GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum # values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED' GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = { 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', } GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum # values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS' GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = { 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', } GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1 GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum # values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED' GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = { 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', } GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum # values for enumeration 'AZ_GLOBAL_CAPABILITIES' AZ_GLOBAL_CAPABILITIES__enumvalues = { 0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', 1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', } AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0 AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1 AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum # values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE' GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = { 0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', } ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0 ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1 GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum # values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL' GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = { 0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED', 1: 'FLUSH_CONTROL_FLUSH_STARTED', } FLUSH_CONTROL_FLUSH_NOT_STARTED = 0 FLUSH_CONTROL_FLUSH_STARTED = 1 GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum # values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET' GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = { 0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', 1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', } CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0 CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1 GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum # values for enumeration 'AZ_STATE_CHANGE_STATUS' AZ_STATE_CHANGE_STATUS__enumvalues = { 0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', 1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', } AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0 AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1 AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum # values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS' GLOBAL_STATUS_FLUSH_STATUS__enumvalues = { 0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', 1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', } GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0 GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1 GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum # values for enumeration 'STREAM_0_SYNCHRONIZATION' STREAM_0_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', 1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', } STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1 STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_1_SYNCHRONIZATION' STREAM_1_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', 1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', } STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1 STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_2_SYNCHRONIZATION' STREAM_2_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', 1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', } STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1 STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_3_SYNCHRONIZATION' STREAM_3_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', 1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', } STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1 STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_4_SYNCHRONIZATION' STREAM_4_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED', 1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED', } STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 1 STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_5_SYNCHRONIZATION' STREAM_5_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED', 1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED', } STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 1 STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_6_SYNCHRONIZATION' STREAM_6_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', } STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_7_SYNCHRONIZATION' STREAM_7_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', } STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_8_SYNCHRONIZATION' STREAM_8_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', } STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_9_SYNCHRONIZATION' STREAM_9_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', } STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_10_SYNCHRONIZATION' STREAM_10_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', } STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_11_SYNCHRONIZATION' STREAM_11_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', } STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_12_SYNCHRONIZATION' STREAM_12_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', } STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_13_SYNCHRONIZATION' STREAM_13_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', } STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_14_SYNCHRONIZATION' STREAM_14_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', } STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'STREAM_15_SYNCHRONIZATION' STREAM_15_SYNCHRONIZATION__enumvalues = { 0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', } STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum # values for enumeration 'CORB_READ_POINTER_RESET' CORB_READ_POINTER_RESET__enumvalues = { 0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', 1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', } CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0 CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1 CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum # values for enumeration 'AZ_CORB_SIZE' AZ_CORB_SIZE__enumvalues = { 0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED', 1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED', 2: 'AZ_CORB_SIZE_256ENTRIES', 3: 'AZ_CORB_SIZE_RESERVED', } AZ_CORB_SIZE_2ENTRIES_RESERVED = 0 AZ_CORB_SIZE_16ENTRIES_RESERVED = 1 AZ_CORB_SIZE_256ENTRIES = 2 AZ_CORB_SIZE_RESERVED = 3 AZ_CORB_SIZE = ctypes.c_uint32 # enum # values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET' AZ_RIRB_WRITE_POINTER_RESET__enumvalues = { 0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 1: 'AZ_RIRB_WRITE_POINTER_DO_RESET', } AZ_RIRB_WRITE_POINTER_NOT_RESET = 0 AZ_RIRB_WRITE_POINTER_DO_RESET = 1 AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum # values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL' RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = { 0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', 1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', } RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum # values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL' RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = { 0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', 1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', } RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum # values for enumeration 'AZ_RIRB_SIZE' AZ_RIRB_SIZE__enumvalues = { 0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 2: 'AZ_RIRB_SIZE_256ENTRIES', 3: 'AZ_RIRB_SIZE_UNDEFINED', } AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0 AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1 AZ_RIRB_SIZE_256ENTRIES = 2 AZ_RIRB_SIZE_UNDEFINED = 3 AZ_RIRB_SIZE = ctypes.c_uint32 # enum # values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID' IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = { 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum # values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY' IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = { 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum # values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE' DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = { 0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', 1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', } DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', 8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L' AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO' AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO' AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY' AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE' AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG' AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V' AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE' AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = { 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE' AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = { 0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', 1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', } AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { 0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', 1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', } AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT' AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = { 0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', 1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', } AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE' AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE' AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE' AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE' AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET' AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = { 0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', 1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', } AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0 AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1 AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY' CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = { 0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', 1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', 2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', 3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', 4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', 5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', 6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', 7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', } CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum # values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY' CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = { 0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', 1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', 2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', 3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', 4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', 5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', 6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', 7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', } CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', 8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE' AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE' AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE' AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE' AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE' AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum # values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET' AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = { 0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', 1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', } AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum # values for enumeration 'ENABLE' ENABLE__enumvalues = { 0: 'DISABLE_THE_FEATURE', 1: 'ENABLE_THE_FEATURE', } DISABLE_THE_FEATURE = 0 ENABLE_THE_FEATURE = 1 ENABLE = ctypes.c_uint32 # enum # values for enumeration 'ENABLE_CLOCK' ENABLE_CLOCK__enumvalues = { 0: 'DISABLE_THE_CLOCK', 1: 'ENABLE_THE_CLOCK', } DISABLE_THE_CLOCK = 0 ENABLE_THE_CLOCK = 1 ENABLE_CLOCK = ctypes.c_uint32 # enum # values for enumeration 'FORCE_VBI' FORCE_VBI__enumvalues = { 0: 'FORCE_VBI_LOW', 1: 'FORCE_VBI_HIGH', } FORCE_VBI_LOW = 0 FORCE_VBI_HIGH = 1 FORCE_VBI = ctypes.c_uint32 # enum # values for enumeration 'OVERRIDE_CGTT_SCLK' OVERRIDE_CGTT_SCLK__enumvalues = { 0: 'OVERRIDE_CGTT_SCLK_NOOP', 1: 'SET_OVERRIDE_CGTT_SCLK', } OVERRIDE_CGTT_SCLK_NOOP = 0 SET_OVERRIDE_CGTT_SCLK = 1 OVERRIDE_CGTT_SCLK = ctypes.c_uint32 # enum # values for enumeration 'CLEAR_SMU_INTR' CLEAR_SMU_INTR__enumvalues = { 0: 'SMU_INTR_STATUS_NOOP', 1: 'SMU_INTR_STATUS_CLEAR', } SMU_INTR_STATUS_NOOP = 0 SMU_INTR_STATUS_CLEAR = 1 CLEAR_SMU_INTR = ctypes.c_uint32 # enum # values for enumeration 'STATIC_SCREEN_SMU_INTR' STATIC_SCREEN_SMU_INTR__enumvalues = { 0: 'STATIC_SCREEN_SMU_INTR_NOOP', 1: 'SET_STATIC_SCREEN_SMU_INTR', } STATIC_SCREEN_SMU_INTR_NOOP = 0 SET_STATIC_SCREEN_SMU_INTR = 1 STATIC_SCREEN_SMU_INTR = ctypes.c_uint32 # enum # values for enumeration 'JITTER_REMOVE_DISABLE' JITTER_REMOVE_DISABLE__enumvalues = { 0: 'ENABLE_JITTER_REMOVAL', 1: 'DISABLE_JITTER_REMOVAL', } ENABLE_JITTER_REMOVAL = 0 DISABLE_JITTER_REMOVAL = 1 JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum # values for enumeration 'DS_REF_SRC' DS_REF_SRC__enumvalues = { 0: 'DS_REF_IS_XTALIN', 1: 'DS_REF_IS_EXT_GENLOCK', 2: 'DS_REF_IS_PCIE', } DS_REF_IS_XTALIN = 0 DS_REF_IS_EXT_GENLOCK = 1 DS_REF_IS_PCIE = 2 DS_REF_SRC = ctypes.c_uint32 # enum # values for enumeration 'DISABLE_CLOCK_GATING' DISABLE_CLOCK_GATING__enumvalues = { 0: 'CLOCK_GATING_ENABLED', 1: 'CLOCK_GATING_DISABLED', } CLOCK_GATING_ENABLED = 0 CLOCK_GATING_DISABLED = 1 DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum # values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO' DISABLE_CLOCK_GATING_IN_DCO__enumvalues = { 0: 'CLOCK_GATING_ENABLED_IN_DCO', 1: 'CLOCK_GATING_DISABLED_IN_DCO', } CLOCK_GATING_ENABLED_IN_DCO = 0 CLOCK_GATING_DISABLED_IN_DCO = 1 DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum # values for enumeration 'DCCG_DEEP_COLOR_CNTL' DCCG_DEEP_COLOR_CNTL__enumvalues = { 0: 'DCCG_DEEP_COLOR_DTO_DISABLE', 1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', 3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', } DCCG_DEEP_COLOR_DTO_DISABLE = 0 DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1 DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2 DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3 DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum # values for enumeration 'REFCLK_CLOCK_EN' REFCLK_CLOCK_EN__enumvalues = { 0: 'REFCLK_CLOCK_EN_XTALIN_CLK', 1: 'REFCLK_CLOCK_EN_ALLOW_SRC_SEL', } REFCLK_CLOCK_EN_XTALIN_CLK = 0 REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 1 REFCLK_CLOCK_EN = ctypes.c_uint32 # enum # values for enumeration 'REFCLK_SRC_SEL' REFCLK_SRC_SEL__enumvalues = { 0: 'REFCLK_SRC_SEL_PCIE_REFCLK', 1: 'REFCLK_SRC_SEL_CPL_REFCLK', } REFCLK_SRC_SEL_PCIE_REFCLK = 0 REFCLK_SRC_SEL_CPL_REFCLK = 1 REFCLK_SRC_SEL = ctypes.c_uint32 # enum # values for enumeration 'DPREFCLK_SRC_SEL' DPREFCLK_SRC_SEL__enumvalues = { 0: 'DPREFCLK_SRC_SEL_CK', 1: 'DPREFCLK_SRC_SEL_P0PLL', 2: 'DPREFCLK_SRC_SEL_P1PLL', 3: 'DPREFCLK_SRC_SEL_P2PLL', 4: 'DPREFCLK_SRC_SEL_P3PLL', } DPREFCLK_SRC_SEL_CK = 0 DPREFCLK_SRC_SEL_P0PLL = 1 DPREFCLK_SRC_SEL_P1PLL = 2 DPREFCLK_SRC_SEL_P2PLL = 3 DPREFCLK_SRC_SEL_P3PLL = 4 DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum # values for enumeration 'XTAL_REF_SEL' XTAL_REF_SEL__enumvalues = { 0: 'XTAL_REF_SEL_1X', 1: 'XTAL_REF_SEL_2X', } XTAL_REF_SEL_1X = 0 XTAL_REF_SEL_2X = 1 XTAL_REF_SEL = ctypes.c_uint32 # enum # values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL' XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = { 0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 1: 'XTAL_REF_CLOCK_SOURCE_SEL_PPLL', } XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0 XTAL_REF_CLOCK_SOURCE_SEL_PPLL = 1 XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum # values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL' MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { 0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', 1: 'MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', } MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 1 MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum # values for enumeration 'ALLOW_SR_ON_TRANS_REQ' ALLOW_SR_ON_TRANS_REQ__enumvalues = { 0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE', 1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE', } ALLOW_SR_ON_TRANS_REQ_ENABLE = 0 ALLOW_SR_ON_TRANS_REQ_DISABLE = 1 ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum # values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL' MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { 0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', 1: 'MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', } MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 1 MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum # values for enumeration 'PIPE_PIXEL_RATE_SOURCE' PIPE_PIXEL_RATE_SOURCE__enumvalues = { 0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL', 2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL', } PIPE_PIXEL_RATE_SOURCE_P0PLL = 0 PIPE_PIXEL_RATE_SOURCE_P1PLL = 1 PIPE_PIXEL_RATE_SOURCE_P2PLL = 2 PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum # values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE' PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = { 0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', 1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', 2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', 3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', 4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE', 5: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF', 6: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG', } PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 4 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 5 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG = 6 PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum # values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE' PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = { 0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', } PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0 PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1 PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum # values for enumeration 'DP_DTO_DS_DISABLE' DP_DTO_DS_DISABLE__enumvalues = { 0: 'DP_DTO_DESPREAD_DISABLE', 1: 'DP_DTO_DESPREAD_ENABLE', } DP_DTO_DESPREAD_DISABLE = 0 DP_DTO_DESPREAD_ENABLE = 1 DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum # values for enumeration 'CRTC_ADD_PIXEL' CRTC_ADD_PIXEL__enumvalues = { 0: 'CRTC_ADD_PIXEL_NOOP', 1: 'CRTC_ADD_PIXEL_FORCE', } CRTC_ADD_PIXEL_NOOP = 0 CRTC_ADD_PIXEL_FORCE = 1 CRTC_ADD_PIXEL = ctypes.c_uint32 # enum # values for enumeration 'CRTC_DROP_PIXEL' CRTC_DROP_PIXEL__enumvalues = { 0: 'CRTC_DROP_PIXEL_NOOP', 1: 'CRTC_DROP_PIXEL_FORCE', } CRTC_DROP_PIXEL_NOOP = 0 CRTC_DROP_PIXEL_FORCE = 1 CRTC_DROP_PIXEL = ctypes.c_uint32 # enum # values for enumeration 'SYMCLK_FE_FORCE_EN' SYMCLK_FE_FORCE_EN__enumvalues = { 0: 'SYMCLK_FE_FORCE_EN_DISABLE', 1: 'SYMCLK_FE_FORCE_EN_ENABLE', } SYMCLK_FE_FORCE_EN_DISABLE = 0 SYMCLK_FE_FORCE_EN_ENABLE = 1 SYMCLK_FE_FORCE_EN = ctypes.c_uint32 # enum # values for enumeration 'SYMCLK_FE_FORCE_SRC' SYMCLK_FE_FORCE_SRC__enumvalues = { 0: 'SYMCLK_FE_FORCE_SRC_UNIPHYA', 1: 'SYMCLK_FE_FORCE_SRC_UNIPHYB', 2: 'SYMCLK_FE_FORCE_SRC_UNIPHYC', 3: 'SYMCLK_FE_FORCE_SRC_UNIPHYD', 4: 'SYMCLK_FE_FORCE_SRC_UNIPHYE', 5: 'SYMCLK_FE_FORCE_SRC_UNIPHYF', 6: 'SYMCLK_FE_FORCE_SRC_UNIPHYG', } SYMCLK_FE_FORCE_SRC_UNIPHYA = 0 SYMCLK_FE_FORCE_SRC_UNIPHYB = 1 SYMCLK_FE_FORCE_SRC_UNIPHYC = 2 SYMCLK_FE_FORCE_SRC_UNIPHYD = 3 SYMCLK_FE_FORCE_SRC_UNIPHYE = 4 SYMCLK_FE_FORCE_SRC_UNIPHYF = 5 SYMCLK_FE_FORCE_SRC_UNIPHYG = 6 SYMCLK_FE_FORCE_SRC = ctypes.c_uint32 # enum # values for enumeration 'DPDBG_CLK_FORCE_EN' DPDBG_CLK_FORCE_EN__enumvalues = { 0: 'DPDBG_CLK_FORCE_EN_DISABLE', 1: 'DPDBG_CLK_FORCE_EN_ENABLE', } DPDBG_CLK_FORCE_EN_DISABLE = 0 DPDBG_CLK_FORCE_EN_ENABLE = 1 DPDBG_CLK_FORCE_EN = ctypes.c_uint32 # enum # values for enumeration 'DVOACLK_COARSE_SKEW_CNTL' DVOACLK_COARSE_SKEW_CNTL__enumvalues = { 0: 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', 1: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', 2: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', 3: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', 4: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', 5: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', 6: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', 7: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', 8: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', 9: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', 10: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', 11: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', 12: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', 13: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', 14: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', 15: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', 16: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', 17: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', 18: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', 19: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', 20: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', 21: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', 22: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', 23: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', 24: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', 25: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', 26: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', 27: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', 28: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', 29: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', 30: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', } DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0 DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 1 DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 2 DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 3 DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 4 DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 5 DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 6 DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 7 DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 8 DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 9 DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 10 DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 11 DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 12 DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 13 DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 14 DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 15 DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 16 DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 17 DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 18 DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 19 DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 20 DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 21 DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 22 DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 23 DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 24 DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 25 DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 26 DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 27 DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 28 DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 29 DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 30 DVOACLK_COARSE_SKEW_CNTL = ctypes.c_uint32 # enum # values for enumeration 'DVOACLK_FINE_SKEW_CNTL' DVOACLK_FINE_SKEW_CNTL__enumvalues = { 0: 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 1: 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', 2: 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', 3: 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', 4: 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', 5: 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', 6: 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', 7: 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', } DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0 DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 1 DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 2 DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 3 DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 4 DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 5 DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 6 DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 7 DVOACLK_FINE_SKEW_CNTL = ctypes.c_uint32 # enum # values for enumeration 'DVOACLKD_IN_PHASE' DVOACLKD_IN_PHASE__enumvalues = { 0: 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 1: 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', } DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 1 DVOACLKD_IN_PHASE = ctypes.c_uint32 # enum # values for enumeration 'DVOACLKC_IN_PHASE' DVOACLKC_IN_PHASE__enumvalues = { 0: 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 1: 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', } DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 1 DVOACLKC_IN_PHASE = ctypes.c_uint32 # enum # values for enumeration 'DVOACLKC_MVP_IN_PHASE' DVOACLKC_MVP_IN_PHASE__enumvalues = { 0: 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 1: 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', } DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 1 DVOACLKC_MVP_IN_PHASE = ctypes.c_uint32 # enum # values for enumeration 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE' DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__enumvalues = { 0: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', 1: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', } DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 1 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE = ctypes.c_uint32 # enum # values for enumeration 'MVP_CLK_SRC_SEL' MVP_CLK_SRC_SEL__enumvalues = { 0: 'MVP_CLK_SRC_SEL_RSRV', 1: 'MVP_CLK_SRC_SEL_IO_1', 2: 'MVP_CLK_SRC_SEL_IO_2', 3: 'MVP_CLK_SRC_SEL_REFCLK', } MVP_CLK_SRC_SEL_RSRV = 0 MVP_CLK_SRC_SEL_IO_1 = 1 MVP_CLK_SRC_SEL_IO_2 = 2 MVP_CLK_SRC_SEL_REFCLK = 3 MVP_CLK_SRC_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL' DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = { 0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0', 1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1', 2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2', 3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3', 4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4', 5: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5', 6: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', } DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0 = 0 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1 = 1 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2 = 2 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3 = 3 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4 = 4 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5 = 5 DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 6 DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCCG_AUDIO_DTO_SEL' DCCG_AUDIO_DTO_SEL__enumvalues = { 0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', 2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', } DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0 DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1 DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2 DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL' DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = { 0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', 1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1', } DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0 DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 1 DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO' DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = { 0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', 1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', } DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0 DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1 DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum # values for enumeration 'DCCG_DBG_EN' DCCG_DBG_EN__enumvalues = { 0: 'DCCG_DBG_EN_DISABLE', 1: 'DCCG_DBG_EN_ENABLE', } DCCG_DBG_EN_DISABLE = 0 DCCG_DBG_EN_ENABLE = 1 DCCG_DBG_EN = ctypes.c_uint32 # enum # values for enumeration 'DCCG_DBG_BLOCK_SEL' DCCG_DBG_BLOCK_SEL__enumvalues = { 0: 'DCCG_DBG_BLOCK_SEL_DCCG', 1: 'DCCG_DBG_BLOCK_SEL_PMON', 2: 'DCCG_DBG_BLOCK_SEL_PMON2', } DCCG_DBG_BLOCK_SEL_DCCG = 0 DCCG_DBG_BLOCK_SEL_PMON = 1 DCCG_DBG_BLOCK_SEL_PMON2 = 2 DCCG_DBG_BLOCK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DISPCLK_FREQ_RAMP_DONE' DISPCLK_FREQ_RAMP_DONE__enumvalues = { 0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 1: 'DISPCLK_FREQ_RAMP_COMPLETED', } DISPCLK_FREQ_RAMP_IN_PROGRESS = 0 DISPCLK_FREQ_RAMP_COMPLETED = 1 DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum # values for enumeration 'DCCG_FIFO_ERRDET_RESET' DCCG_FIFO_ERRDET_RESET__enumvalues = { 0: 'DCCG_FIFO_ERRDET_RESET_NOOP', 1: 'DCCG_FIFO_ERRDET_RESET_FORCE', } DCCG_FIFO_ERRDET_RESET_NOOP = 0 DCCG_FIFO_ERRDET_RESET_FORCE = 1 DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum # values for enumeration 'DCCG_FIFO_ERRDET_STATE' DCCG_FIFO_ERRDET_STATE__enumvalues = { 0: 'DCCG_FIFO_ERRDET_STATE_DETECTION', 1: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', } DCCG_FIFO_ERRDET_STATE_DETECTION = 0 DCCG_FIFO_ERRDET_STATE_CALIBRATION = 1 DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum # values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN' DCCG_FIFO_ERRDET_OVR_EN__enumvalues = { 0: 'DCCG_FIFO_ERRDET_OVR_DISABLE', 1: 'DCCG_FIFO_ERRDET_OVR_ENABLE', } DCCG_FIFO_ERRDET_OVR_DISABLE = 0 DCCG_FIFO_ERRDET_OVR_ENABLE = 1 DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum # values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE' DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = { 0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', 1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', } DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0 DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1 DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum # values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS' DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = { 0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', 1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', } DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0 DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1 DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum # values for enumeration 'DCCG_PERF_RUN' DCCG_PERF_RUN__enumvalues = { 0: 'DCCG_PERF_RUN_NOOP', 1: 'DCCG_PERF_RUN_START', } DCCG_PERF_RUN_NOOP = 0 DCCG_PERF_RUN_START = 1 DCCG_PERF_RUN = ctypes.c_uint32 # enum # values for enumeration 'DCCG_PERF_MODE_VSYNC' DCCG_PERF_MODE_VSYNC__enumvalues = { 0: 'DCCG_PERF_MODE_VSYNC_NOOP', 1: 'DCCG_PERF_MODE_VSYNC_START', } DCCG_PERF_MODE_VSYNC_NOOP = 0 DCCG_PERF_MODE_VSYNC_START = 1 DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum # values for enumeration 'DCCG_PERF_MODE_HSYNC' DCCG_PERF_MODE_HSYNC__enumvalues = { 0: 'DCCG_PERF_MODE_HSYNC_NOOP', 1: 'DCCG_PERF_MODE_HSYNC_START', } DCCG_PERF_MODE_HSYNC_NOOP = 0 DCCG_PERF_MODE_HSYNC_START = 1 DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum # values for enumeration 'DCCG_PERF_CRTC_SELECT' DCCG_PERF_CRTC_SELECT__enumvalues = { 0: 'DCCG_PERF_SEL_CRTC0', 1: 'DCCG_PERF_SEL_CRTC1', 2: 'DCCG_PERF_SEL_CRTC2', 3: 'DCCG_PERF_SEL_CRTC3', 4: 'DCCG_PERF_SEL_CRTC4', 5: 'DCCG_PERF_SEL_CRTC5', } DCCG_PERF_SEL_CRTC0 = 0 DCCG_PERF_SEL_CRTC1 = 1 DCCG_PERF_SEL_CRTC2 = 2 DCCG_PERF_SEL_CRTC3 = 3 DCCG_PERF_SEL_CRTC4 = 4 DCCG_PERF_SEL_CRTC5 = 5 DCCG_PERF_CRTC_SELECT = ctypes.c_uint32 # enum # values for enumeration 'CLOCK_BRANCH_SOFT_RESET' CLOCK_BRANCH_SOFT_RESET__enumvalues = { 0: 'CLOCK_BRANCH_SOFT_RESET_NOOP', 1: 'CLOCK_BRANCH_SOFT_RESET_FORCE', } CLOCK_BRANCH_SOFT_RESET_NOOP = 0 CLOCK_BRANCH_SOFT_RESET_FORCE = 1 CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'PLL_CFG_IF_SOFT_RESET' PLL_CFG_IF_SOFT_RESET__enumvalues = { 0: 'PLL_CFG_IF_SOFT_RESET_NOOP', 1: 'PLL_CFG_IF_SOFT_RESET_FORCE', } PLL_CFG_IF_SOFT_RESET_NOOP = 0 PLL_CFG_IF_SOFT_RESET_FORCE = 1 PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DVO_ENABLE_RST' DVO_ENABLE_RST__enumvalues = { 0: 'DVO_ENABLE_RST_DISABLE', 1: 'DVO_ENABLE_RST_ENABLE', } DVO_ENABLE_RST_DISABLE = 0 DVO_ENABLE_RST_ENABLE = 1 DVO_ENABLE_RST = ctypes.c_uint32 # enum # values for enumeration 'LptNumPipes' LptNumPipes__enumvalues = { 0: 'LPT_NUM_PIPES_1CH', 1: 'LPT_NUM_PIPES_2CH', 2: 'LPT_NUM_PIPES_4CH', 3: 'LPT_NUM_PIPES_8CH', } LPT_NUM_PIPES_1CH = 0 LPT_NUM_PIPES_2CH = 1 LPT_NUM_PIPES_4CH = 2 LPT_NUM_PIPES_8CH = 3 LptNumPipes = ctypes.c_uint32 # enum # values for enumeration 'LptNumBanks' LptNumBanks__enumvalues = { 0: 'LPT_NUM_BANKS_2BANK', 1: 'LPT_NUM_BANKS_4BANK', 2: 'LPT_NUM_BANKS_8BANK', 3: 'LPT_NUM_BANKS_16BANK', 4: 'LPT_NUM_BANKS_32BANK', } LPT_NUM_BANKS_2BANK = 0 LPT_NUM_BANKS_4BANK = 1 LPT_NUM_BANKS_8BANK = 2 LPT_NUM_BANKS_16BANK = 3 LPT_NUM_BANKS_32BANK = 4 LptNumBanks = ctypes.c_uint32 # enum # values for enumeration 'OVERRIDE_CGTT_DCEFCLK' OVERRIDE_CGTT_DCEFCLK__enumvalues = { 0: 'OVERRIDE_CGTT_DCEFCLK_NOOP', 1: 'SET_OVERRIDE_CGTT_DCEFCLK', } OVERRIDE_CGTT_DCEFCLK_NOOP = 0 SET_OVERRIDE_CGTT_DCEFCLK = 1 OVERRIDE_CGTT_DCEFCLK = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_GENERICA_SEL' DCIO_DC_GENERICA_SEL__enumvalues = { 0: 'DCIO_GENERICA_SEL_DACA_STEREOSYNC', 1: 'DCIO_GENERICA_SEL_STEREOSYNC', 2: 'DCIO_GENERICA_SEL_DACA_PIXCLK', 3: 'DCIO_GENERICA_SEL_DACB_PIXCLK', 4: 'DCIO_GENERICA_SEL_DVOA_CTL3', 5: 'DCIO_GENERICA_SEL_P1_PLLCLK', 6: 'DCIO_GENERICA_SEL_P2_PLLCLK', 7: 'DCIO_GENERICA_SEL_DVOA_STEREOSYNC', 8: 'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER', 9: 'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER', 10: 'DCIO_GENERICA_SEL_GENERICA_DCCG', 11: 'DCIO_GENERICA_SEL_SYNCEN', 12: 'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK', 13: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK', 14: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK', 15: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2', 16: 'DCIO_GENERICA_SEL_GENERICA_DPRX', 17: 'DCIO_GENERICA_SEL_GENERICB_DPRX', } DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0 DCIO_GENERICA_SEL_STEREOSYNC = 1 DCIO_GENERICA_SEL_DACA_PIXCLK = 2 DCIO_GENERICA_SEL_DACB_PIXCLK = 3 DCIO_GENERICA_SEL_DVOA_CTL3 = 4 DCIO_GENERICA_SEL_P1_PLLCLK = 5 DCIO_GENERICA_SEL_P2_PLLCLK = 6 DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 7 DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 8 DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 9 DCIO_GENERICA_SEL_GENERICA_DCCG = 10 DCIO_GENERICA_SEL_SYNCEN = 11 DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK = 12 DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK = 13 DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK = 14 DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15 DCIO_GENERICA_SEL_GENERICA_DPRX = 16 DCIO_GENERICA_SEL_GENERICB_DPRX = 17 DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL' DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = { 0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 7: 'DCIO_UNIPHYLPA_TEST_REFDIV_CLK', 8: 'DCIO_UNIPHYLPB_TEST_REFDIV_CLK', } DCIO_UNIPHYA_TEST_REFDIV_CLK = 0 DCIO_UNIPHYB_TEST_REFDIV_CLK = 1 DCIO_UNIPHYC_TEST_REFDIV_CLK = 2 DCIO_UNIPHYD_TEST_REFDIV_CLK = 3 DCIO_UNIPHYE_TEST_REFDIV_CLK = 4 DCIO_UNIPHYF_TEST_REFDIV_CLK = 5 DCIO_UNIPHYG_TEST_REFDIV_CLK = 6 DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 7 DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 8 DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL' DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = { 0: 'DCIO_UNIPHYA_FBDIV_CLK', 1: 'DCIO_UNIPHYB_FBDIV_CLK', 2: 'DCIO_UNIPHYC_FBDIV_CLK', 3: 'DCIO_UNIPHYD_FBDIV_CLK', 4: 'DCIO_UNIPHYE_FBDIV_CLK', 5: 'DCIO_UNIPHYF_FBDIV_CLK', 6: 'DCIO_UNIPHYG_FBDIV_CLK', 7: 'DCIO_UNIPHYLPA_FBDIV_CLK', 8: 'DCIO_UNIPHYLPB_FBDIV_CLK', } DCIO_UNIPHYA_FBDIV_CLK = 0 DCIO_UNIPHYB_FBDIV_CLK = 1 DCIO_UNIPHYC_FBDIV_CLK = 2 DCIO_UNIPHYD_FBDIV_CLK = 3 DCIO_UNIPHYE_FBDIV_CLK = 4 DCIO_UNIPHYF_FBDIV_CLK = 5 DCIO_UNIPHYG_FBDIV_CLK = 6 DCIO_UNIPHYLPA_FBDIV_CLK = 7 DCIO_UNIPHYLPB_FBDIV_CLK = 8 DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL' DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = { 0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK', 1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 7: 'DCIO_UNIPHYLPA_FBDIV_SSC_CLK', 8: 'DCIO_UNIPHYLPB_FBDIV_SSC_CLK', } DCIO_UNIPHYA_FBDIV_SSC_CLK = 0 DCIO_UNIPHYB_FBDIV_SSC_CLK = 1 DCIO_UNIPHYC_FBDIV_SSC_CLK = 2 DCIO_UNIPHYD_FBDIV_SSC_CLK = 3 DCIO_UNIPHYE_FBDIV_SSC_CLK = 4 DCIO_UNIPHYF_FBDIV_SSC_CLK = 5 DCIO_UNIPHYG_FBDIV_SSC_CLK = 6 DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 7 DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 8 DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL' DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = { 0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', 1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', 2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', 3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', 4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', 5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', 6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', 7: 'DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2', 8: 'DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2', } DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0 DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1 DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2 DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3 DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4 DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5 DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6 DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 7 DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 8 DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_GENERICB_SEL' DCIO_DC_GENERICB_SEL__enumvalues = { 0: 'DCIO_GENERICB_SEL_DACA_STEREOSYNC', 1: 'DCIO_GENERICB_SEL_STEREOSYNC', 2: 'DCIO_GENERICB_SEL_DACA_PIXCLK', 3: 'DCIO_GENERICB_SEL_DACB_PIXCLK', 4: 'DCIO_GENERICB_SEL_DVOA_CTL3', 5: 'DCIO_GENERICB_SEL_P1_PLLCLK', 6: 'DCIO_GENERICB_SEL_P2_PLLCLK', 7: 'DCIO_GENERICB_SEL_DVOA_STEREOSYNC', 8: 'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER', 9: 'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER', 10: 'DCIO_GENERICB_SEL_GENERICB_DCCG', 11: 'DCIO_GENERICB_SEL_SYNCEN', 12: 'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK', 13: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK', 14: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK', 15: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2', } DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0 DCIO_GENERICB_SEL_STEREOSYNC = 1 DCIO_GENERICB_SEL_DACA_PIXCLK = 2 DCIO_GENERICB_SEL_DACB_PIXCLK = 3 DCIO_GENERICB_SEL_DVOA_CTL3 = 4 DCIO_GENERICB_SEL_P1_PLLCLK = 5 DCIO_GENERICB_SEL_P2_PLLCLK = 6 DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 7 DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 8 DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 9 DCIO_GENERICB_SEL_GENERICB_DCCG = 10 DCIO_GENERICB_SEL_SYNCEN = 11 DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK = 12 DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK = 13 DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK = 14 DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15 DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_PAD_EXTERN_SIG_SEL' DCIO_DC_PAD_EXTERN_SIG_SEL__enumvalues = { 0: 'DCIO_DC_PAD_EXTERN_SIG_SEL_MVP', 1: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA', 2: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK', 3: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC', 4: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA', 5: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB', 6: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC', 7: 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1', 8: 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2', 9: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK', 10: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA', 11: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK', 12: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA', 13: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1', 14: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0', 15: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL', } DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0 DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 1 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 2 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 3 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 4 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 5 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 6 DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 7 DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 8 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 9 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 10 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 11 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 12 DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 13 DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 14 DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 15 DCIO_DC_PAD_EXTERN_SIG_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS' DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS__enumvalues = { 0: 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA', 1: 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE', 2: 'DCIO_MVP_PIXEL_SRC_STATUS_CRTC', 3: 'DCIO_MVP_PIXEL_SRC_STATUS_LB', } DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0 DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 1 DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 2 DCIO_MVP_PIXEL_SRC_STATUS_LB = 3 DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL' DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL__enumvalues = { 0: 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', 1: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', 2: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', 3: 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', } DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0 DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 1 DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 2 DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 3 DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL' DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = { 0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', 1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', 2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', 3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', } DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2 DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3 DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_GPIO_VIP_DEBUG' DCIO_DC_GPIO_VIP_DEBUG__enumvalues = { 0: 'DCIO_DC_GPIO_VIP_DEBUG_NORMAL', 1: 'DCIO_DC_GPIO_VIP_DEBUG_CG_BIG', } DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0 DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 1 DCIO_DC_GPIO_VIP_DEBUG = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_GPIO_MACRO_DEBUG' DCIO_DC_GPIO_MACRO_DEBUG__enumvalues = { 0: 'DCIO_DC_GPIO_MACRO_DEBUG_NORMAL', 1: 'DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF', 2: 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2', 3: 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3', } DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0 DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 1 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 2 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 3 DCIO_DC_GPIO_MACRO_DEBUG = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL' DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__enumvalues = { 0: 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL', 1: 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP', } DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0 DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 1 DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN' DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN__enumvalues = { 0: 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS', 1: 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE', } DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0 DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 1 DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE' DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE__enumvalues = { 0: 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 1: 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', } DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0 DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 1 DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION' DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION__enumvalues = { 0: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS', 1: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS', 2: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS', 3: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS', 4: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS', 5: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS', 6: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS', 7: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS', } DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 1 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 2 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 3 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 4 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 5 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 6 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 7 DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION = ctypes.c_uint32 # enum # values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT' DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = { 0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', 1: 'DCIO_UNIPHY_CHANNEL_INVERTED', } DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0 DCIO_UNIPHY_CHANNEL_INVERTED = 1 DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum # values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK' DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = { 0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', 1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', 2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', 3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', } DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3 DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum # values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE' DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = { 0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', 1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', 2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', 3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', } DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN' DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN__enumvalues = { 0: 'DCIO_VIP_MUX_EN_DVO', 1: 'DCIO_VIP_MUX_EN_VIP', } DCIO_VIP_MUX_EN_DVO = 0 DCIO_VIP_MUX_EN_VIP = 1 DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN' DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN__enumvalues = { 0: 'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT', 1: 'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE', } DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0 DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 1 DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN' DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN__enumvalues = { 0: 'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT', 1: 'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE', } DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0 DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 1 DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN' DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN__enumvalues = { 0: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE', 1: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE', } DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE = 0 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE = 1 DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE' DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE__enumvalues = { 0: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF', 1: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON', } DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 1 DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum # values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL' DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL__enumvalues = { 0: 'DCIO_LVTMA_SYNCEN_POL_NON_INVERT', 1: 'DCIO_LVTMA_SYNCEN_POL_INVERT', } DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0 DCIO_LVTMA_SYNCEN_POL_INVERT = 1 DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON' DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON__enumvalues = { 0: 'DCIO_LVTMA_DIGON_OFF', 1: 'DCIO_LVTMA_DIGON_ON', } DCIO_LVTMA_DIGON_OFF = 0 DCIO_LVTMA_DIGON_ON = 1 DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON = ctypes.c_uint32 # enum # values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL' DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL__enumvalues = { 0: 'DCIO_LVTMA_DIGON_POL_NON_INVERT', 1: 'DCIO_LVTMA_DIGON_POL_INVERT', } DCIO_LVTMA_DIGON_POL_NON_INVERT = 0 DCIO_LVTMA_DIGON_POL_INVERT = 1 DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON' DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON__enumvalues = { 0: 'DCIO_LVTMA_BLON_OFF', 1: 'DCIO_LVTMA_BLON_ON', } DCIO_LVTMA_BLON_OFF = 0 DCIO_LVTMA_BLON_ON = 1 DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON = ctypes.c_uint32 # enum # values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL' DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL__enumvalues = { 0: 'DCIO_LVTMA_BLON_POL_NON_INVERT', 1: 'DCIO_LVTMA_BLON_POL_INVERT', } DCIO_LVTMA_BLON_POL_NON_INVERT = 0 DCIO_LVTMA_BLON_POL_INVERT = 1 DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN' DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN__enumvalues = { 0: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON', 1: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE', } DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 1 DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN' DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = { 0: 'DCIO_BL_PWM_FRACTIONAL_DISABLE', 1: 'DCIO_BL_PWM_FRACTIONAL_ENABLE', } DCIO_BL_PWM_FRACTIONAL_DISABLE = 0 DCIO_BL_PWM_FRACTIONAL_ENABLE = 1 DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_EN' DCIO_BL_PWM_CNTL_BL_PWM_EN__enumvalues = { 0: 'DCIO_BL_PWM_DISABLE', 1: 'DCIO_BL_PWM_ENABLE', } DCIO_BL_PWM_DISABLE = 0 DCIO_BL_PWM_ENABLE = 1 DCIO_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT' DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT__enumvalues = { 0: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', 1: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', 2: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', 3: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', } DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 1 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 2 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 3 DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT = ctypes.c_uint32 # enum # values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE' DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = { 0: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE', 1: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE', } DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0 DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1 DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum # values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN' DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__enumvalues = { 0: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL', 1: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM', } DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 1 DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIO_BL_PWM_GRP1_REG_LOCK' DCIO_BL_PWM_GRP1_REG_LOCK__enumvalues = { 0: 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE', 1: 'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE', } DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0 DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 1 DCIO_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum # values for enumeration 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START' DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = { 0: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', 1: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', } DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum # values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL' DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = { 0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', 1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', 2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', 3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', 4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', 5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', } DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN' DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = { 0: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', 1: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', } DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN' DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = { 0: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', 1: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', } DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum # values for enumeration 'DCIO_GSL_SEL' DCIO_GSL_SEL__enumvalues = { 0: 'DCIO_GSL_SEL_GROUP_0', 1: 'DCIO_GSL_SEL_GROUP_1', 2: 'DCIO_GSL_SEL_GROUP_2', } DCIO_GSL_SEL_GROUP_0 = 0 DCIO_GSL_SEL_GROUP_1 = 1 DCIO_GSL_SEL_GROUP_2 = 2 DCIO_GSL_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_GENLK_CLK_GSL_MASK' DCIO_GENLK_CLK_GSL_MASK__enumvalues = { 0: 'DCIO_GENLK_CLK_GSL_MASK_NO', 1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING', 2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO', } DCIO_GENLK_CLK_GSL_MASK_NO = 0 DCIO_GENLK_CLK_GSL_MASK_TIMING = 1 DCIO_GENLK_CLK_GSL_MASK_STEREO = 2 DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum # values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK' DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = { 0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO', 1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', 2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', } DCIO_GENLK_VSYNC_GSL_MASK_NO = 0 DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1 DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2 DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum # values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK' DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = { 0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO', 1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', } DCIO_SWAPLOCK_A_GSL_MASK_NO = 0 DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1 DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2 DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum # values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK' DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = { 0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', } DCIO_SWAPLOCK_B_GSL_MASK_NO = 0 DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1 DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2 DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum # values for enumeration 'DCIO_GSL_VSYNC_SEL' DCIO_GSL_VSYNC_SEL__enumvalues = { 0: 'DCIO_GSL_VSYNC_SEL_PIPE0', 1: 'DCIO_GSL_VSYNC_SEL_PIPE1', 2: 'DCIO_GSL_VSYNC_SEL_PIPE2', 3: 'DCIO_GSL_VSYNC_SEL_PIPE3', 4: 'DCIO_GSL_VSYNC_SEL_PIPE4', 5: 'DCIO_GSL_VSYNC_SEL_PIPE5', } DCIO_GSL_VSYNC_SEL_PIPE0 = 0 DCIO_GSL_VSYNC_SEL_PIPE1 = 1 DCIO_GSL_VSYNC_SEL_PIPE2 = 2 DCIO_GSL_VSYNC_SEL_PIPE3 = 3 DCIO_GSL_VSYNC_SEL_PIPE4 = 4 DCIO_GSL_VSYNC_SEL_PIPE5 = 5 DCIO_GSL_VSYNC_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_GSL0_TIMING_SYNC_SEL' DCIO_GSL0_TIMING_SYNC_SEL__enumvalues = { 0: 'DCIO_GSL0_TIMING_SYNC_SEL_PIPE', 1: 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC', 2: 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK', 3: 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A', 4: 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B', } DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 1 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 2 DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 3 DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 4 DCIO_GSL0_TIMING_SYNC_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_GSL0_GLOBAL_UNLOCK_SEL' DCIO_GSL0_GLOBAL_UNLOCK_SEL__enumvalues = { 0: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION', 1: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', 2: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK', 3: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', 4: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', } DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 1 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 2 DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 3 DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 4 DCIO_GSL0_GLOBAL_UNLOCK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_GSL1_TIMING_SYNC_SEL' DCIO_GSL1_TIMING_SYNC_SEL__enumvalues = { 0: 'DCIO_GSL1_TIMING_SYNC_SEL_PIPE', 1: 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC', 2: 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK', 3: 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A', 4: 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B', } DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 1 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 2 DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 3 DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 4 DCIO_GSL1_TIMING_SYNC_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_GSL1_GLOBAL_UNLOCK_SEL' DCIO_GSL1_GLOBAL_UNLOCK_SEL__enumvalues = { 0: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION', 1: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', 2: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK', 3: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', 4: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', } DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 1 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 2 DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 3 DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 4 DCIO_GSL1_GLOBAL_UNLOCK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_GSL2_TIMING_SYNC_SEL' DCIO_GSL2_TIMING_SYNC_SEL__enumvalues = { 0: 'DCIO_GSL2_TIMING_SYNC_SEL_PIPE', 1: 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC', 2: 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK', 3: 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A', 4: 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B', } DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 1 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 2 DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 3 DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 4 DCIO_GSL2_TIMING_SYNC_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_GSL2_GLOBAL_UNLOCK_SEL' DCIO_GSL2_GLOBAL_UNLOCK_SEL__enumvalues = { 0: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION', 1: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', 2: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK', 3: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', 4: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', } DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 1 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 2 DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 3 DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 4 DCIO_GSL2_GLOBAL_UNLOCK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION' DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = { 0: 'DCIO_GPU_TIMER_START_0_END_27', 1: 'DCIO_GPU_TIMER_START_1_END_28', 2: 'DCIO_GPU_TIMER_START_2_END_29', 3: 'DCIO_GPU_TIMER_START_3_END_30', 4: 'DCIO_GPU_TIMER_START_4_END_31', 5: 'DCIO_GPU_TIMER_START_6_END_33', 6: 'DCIO_GPU_TIMER_START_8_END_35', 7: 'DCIO_GPU_TIMER_START_10_END_37', } DCIO_GPU_TIMER_START_0_END_27 = 0 DCIO_GPU_TIMER_START_1_END_28 = 1 DCIO_GPU_TIMER_START_2_END_29 = 2 DCIO_GPU_TIMER_START_3_END_30 = 3 DCIO_GPU_TIMER_START_4_END_31 = 4 DCIO_GPU_TIMER_START_6_END_33 = 5 DCIO_GPU_TIMER_START_8_END_35 = 6 DCIO_GPU_TIMER_START_10_END_37 = 7 DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum # values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL' DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = { 0: 'DCIO_TEST_CLK_SEL_DISPCLK', 1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 2: 'DCIO_TEST_CLK_SEL_SCLK', } DCIO_TEST_CLK_SEL_DISPCLK = 0 DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1 DCIO_TEST_CLK_SEL_SCLK = 2 DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS' DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = { 0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', 1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', } DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0 DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1 DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DCO_DCFE_EXT_VSYNC_MUX' DCIO_DCO_DCFE_EXT_VSYNC_MUX__enumvalues = { 0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', 1: 'DCIO_EXT_VSYNC_MUX_CRTC0', 2: 'DCIO_EXT_VSYNC_MUX_CRTC1', 3: 'DCIO_EXT_VSYNC_MUX_CRTC2', 4: 'DCIO_EXT_VSYNC_MUX_CRTC3', 5: 'DCIO_EXT_VSYNC_MUX_CRTC4', 6: 'DCIO_EXT_VSYNC_MUX_CRTC5', 7: 'DCIO_EXT_VSYNC_MUX_GENERICB', } DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0 DCIO_EXT_VSYNC_MUX_CRTC0 = 1 DCIO_EXT_VSYNC_MUX_CRTC1 = 2 DCIO_EXT_VSYNC_MUX_CRTC2 = 3 DCIO_EXT_VSYNC_MUX_CRTC3 = 4 DCIO_EXT_VSYNC_MUX_CRTC4 = 5 DCIO_EXT_VSYNC_MUX_CRTC5 = 6 DCIO_EXT_VSYNC_MUX_GENERICB = 7 DCIO_DCO_DCFE_EXT_VSYNC_MUX = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DCO_EXT_VSYNC_MASK' DCIO_DCO_EXT_VSYNC_MASK__enumvalues = { 0: 'DCIO_EXT_VSYNC_MASK_NONE', 1: 'DCIO_EXT_VSYNC_MASK_PIPE0', 2: 'DCIO_EXT_VSYNC_MASK_PIPE1', 3: 'DCIO_EXT_VSYNC_MASK_PIPE2', 4: 'DCIO_EXT_VSYNC_MASK_PIPE3', 5: 'DCIO_EXT_VSYNC_MASK_PIPE4', 6: 'DCIO_EXT_VSYNC_MASK_PIPE5', 7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', } DCIO_EXT_VSYNC_MASK_NONE = 0 DCIO_EXT_VSYNC_MASK_PIPE0 = 1 DCIO_EXT_VSYNC_MASK_PIPE1 = 2 DCIO_EXT_VSYNC_MASK_PIPE2 = 3 DCIO_EXT_VSYNC_MASK_PIPE3 = 4 DCIO_EXT_VSYNC_MASK_PIPE4 = 5 DCIO_EXT_VSYNC_MASK_PIPE5 = 6 DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7 DCIO_DCO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DSYNC_SOFT_RESET' DCIO_DSYNC_SOFT_RESET__enumvalues = { 0: 'DCIO_DSYNC_SOFT_RESET_DEASSERT', 1: 'DCIO_DSYNC_SOFT_RESET_ASSERT', } DCIO_DSYNC_SOFT_RESET_DEASSERT = 0 DCIO_DSYNC_SOFT_RESET_ASSERT = 1 DCIO_DSYNC_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DACA_SOFT_RESET' DCIO_DACA_SOFT_RESET__enumvalues = { 0: 'DCIO_DACA_SOFT_RESET_DEASSERT', 1: 'DCIO_DACA_SOFT_RESET_ASSERT', } DCIO_DACA_SOFT_RESET_DEASSERT = 0 DCIO_DACA_SOFT_RESET_ASSERT = 1 DCIO_DACA_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DCRXPHY_SOFT_RESET' DCIO_DCRXPHY_SOFT_RESET__enumvalues = { 0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', 1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', } DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0 DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1 DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DPHY_LANE_SEL' DCIO_DPHY_LANE_SEL__enumvalues = { 0: 'DCIO_DPHY_LANE_SEL_LANE0', 1: 'DCIO_DPHY_LANE_SEL_LANE1', 2: 'DCIO_DPHY_LANE_SEL_LANE2', 3: 'DCIO_DPHY_LANE_SEL_LANE3', } DCIO_DPHY_LANE_SEL_LANE0 = 0 DCIO_DPHY_LANE_SEL_LANE1 = 1 DCIO_DPHY_LANE_SEL_LANE2 = 2 DCIO_DPHY_LANE_SEL_LANE3 = 3 DCIO_DPHY_LANE_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE' DCIO_DPCS_INTERRUPT_TYPE__enumvalues = { 0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', 1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', } DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0 DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1 DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DPCS_INTERRUPT_MASK' DCIO_DPCS_INTERRUPT_MASK__enumvalues = { 0: 'DCIO_DPCS_INTERRUPT_DISABLE', 1: 'DCIO_DPCS_INTERRUPT_ENABLE', } DCIO_DPCS_INTERRUPT_DISABLE = 0 DCIO_DPCS_INTERRUPT_ENABLE = 1 DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT' DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = { 0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', 1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', 2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE', 3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE', 4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE', 5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE', 6: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE', 7: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE', 8: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE', 9: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE', 10: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE', 11: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE', 12: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', 13: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', 14: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP', 15: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP', 16: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP', 17: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP', 18: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP', 19: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP', 20: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP', 21: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP', 22: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP', 23: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP', 24: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', 25: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', 26: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM', 27: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM', 28: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM', 29: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM', 30: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM', 31: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM', 32: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM', 33: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM', 34: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM', 35: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM', } DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 2 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 3 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 4 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 5 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 6 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 7 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 8 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 9 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 10 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 11 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 12 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 13 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 14 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 15 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 16 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 17 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 18 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 19 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 20 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 21 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 22 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 23 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 24 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 25 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 26 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 27 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 28 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 29 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 30 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 31 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 32 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 33 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 34 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 35 DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum # values for enumeration 'DCIO_IMPCAL_STEP_DELAY' DCIO_IMPCAL_STEP_DELAY__enumvalues = { 0: 'DCIO_IMPCAL_STEP_DELAY_1us', 1: 'DCIO_IMPCAL_STEP_DELAY_2us', 2: 'DCIO_IMPCAL_STEP_DELAY_3us', 3: 'DCIO_IMPCAL_STEP_DELAY_4us', 4: 'DCIO_IMPCAL_STEP_DELAY_5us', 5: 'DCIO_IMPCAL_STEP_DELAY_6us', 6: 'DCIO_IMPCAL_STEP_DELAY_7us', 7: 'DCIO_IMPCAL_STEP_DELAY_8us', 8: 'DCIO_IMPCAL_STEP_DELAY_9us', 9: 'DCIO_IMPCAL_STEP_DELAY_10us', 10: 'DCIO_IMPCAL_STEP_DELAY_11us', 11: 'DCIO_IMPCAL_STEP_DELAY_12us', 12: 'DCIO_IMPCAL_STEP_DELAY_13us', 13: 'DCIO_IMPCAL_STEP_DELAY_14us', 14: 'DCIO_IMPCAL_STEP_DELAY_15us', 15: 'DCIO_IMPCAL_STEP_DELAY_16us', } DCIO_IMPCAL_STEP_DELAY_1us = 0 DCIO_IMPCAL_STEP_DELAY_2us = 1 DCIO_IMPCAL_STEP_DELAY_3us = 2 DCIO_IMPCAL_STEP_DELAY_4us = 3 DCIO_IMPCAL_STEP_DELAY_5us = 4 DCIO_IMPCAL_STEP_DELAY_6us = 5 DCIO_IMPCAL_STEP_DELAY_7us = 6 DCIO_IMPCAL_STEP_DELAY_8us = 7 DCIO_IMPCAL_STEP_DELAY_9us = 8 DCIO_IMPCAL_STEP_DELAY_10us = 9 DCIO_IMPCAL_STEP_DELAY_11us = 10 DCIO_IMPCAL_STEP_DELAY_12us = 11 DCIO_IMPCAL_STEP_DELAY_13us = 12 DCIO_IMPCAL_STEP_DELAY_14us = 13 DCIO_IMPCAL_STEP_DELAY_15us = 14 DCIO_IMPCAL_STEP_DELAY_16us = 15 DCIO_IMPCAL_STEP_DELAY = ctypes.c_uint32 # enum # values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL' DCIO_UNIPHY_IMPCAL_SEL__enumvalues = { 0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', 1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', } DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0 DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1 DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DBG_ASYNC_BLOCK_SEL' DCIO_DBG_ASYNC_BLOCK_SEL__enumvalues = { 0: 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', 1: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 2: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', 3: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCO', } DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0 DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 1 DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 2 DCIO_DBG_ASYNC_BLOCK_SEL_DCO = 3 DCIO_DBG_ASYNC_BLOCK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCIO_DBG_ASYNC_4BIT_SEL' DCIO_DBG_ASYNC_4BIT_SEL__enumvalues = { 0: 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', 1: 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 2: 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', 3: 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', 4: 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', 5: 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', 6: 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', 7: 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', } DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0 DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 1 DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 2 DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 3 DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 4 DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 5 DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 6 DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 7 DCIO_DBG_ASYNC_4BIT_SEL = ctypes.c_uint32 # enum # values for enumeration 'AOUT_EN' AOUT_EN__enumvalues = { 0: 'AOUT_DISABLE', 1: 'AOUT_ENABLE', } AOUT_DISABLE = 0 AOUT_ENABLE = 1 AOUT_EN = ctypes.c_uint32 # enum # values for enumeration 'AOUT_FIFO_START_ADDR' AOUT_FIFO_START_ADDR__enumvalues = { 0: 'AOUT_FIFO_START_ADDR_2', 1: 'AOUT_FIFO_START_ADDR_3', } AOUT_FIFO_START_ADDR_2 = 0 AOUT_FIFO_START_ADDR_3 = 1 AOUT_FIFO_START_ADDR = ctypes.c_uint32 # enum # values for enumeration 'AOUT_CRC_TEST_EN' AOUT_CRC_TEST_EN__enumvalues = { 0: 'AOUT_CRC_DISABLE', 1: 'AOUT_CRC_ENABLE', } AOUT_CRC_DISABLE = 0 AOUT_CRC_ENABLE = 1 AOUT_CRC_TEST_EN = ctypes.c_uint32 # enum # values for enumeration 'AOUT_CRC_SOFT_RESET' AOUT_CRC_SOFT_RESET__enumvalues = { 0: 'AOUT_CRC_NO_RESET', 1: 'AOUT_CRC_RESET', } AOUT_CRC_NO_RESET = 0 AOUT_CRC_RESET = 1 AOUT_CRC_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'AOUT_CRC_CONT_EN' AOUT_CRC_CONT_EN__enumvalues = { 0: 'AOUT_CRC_ONE_SHOT', 1: 'AOUT_CRC_CONT', } AOUT_CRC_ONE_SHOT = 0 AOUT_CRC_CONT = 1 AOUT_CRC_CONT_EN = ctypes.c_uint32 # enum # values for enumeration 'I2S_WORD_SIZE' I2S_WORD_SIZE__enumvalues = { 0: 'I2S_WORD_SIZE_32', 1: 'I2S_WORD_SIZE_16', } I2S_WORD_SIZE_32 = 0 I2S_WORD_SIZE_16 = 1 I2S_WORD_SIZE = ctypes.c_uint32 # enum # values for enumeration 'I2S_SAMPLE_ALIGNMENT' I2S_SAMPLE_ALIGNMENT__enumvalues = { 0: 'I2S_SAMPLE_LEFT_ALIGNED', 1: 'I2S_SAMPLE_RIGHT_ALIGNED', } I2S_SAMPLE_LEFT_ALIGNED = 0 I2S_SAMPLE_RIGHT_ALIGNED = 1 I2S_SAMPLE_ALIGNMENT = ctypes.c_uint32 # enum # values for enumeration 'I2S_SAMPLE_BIT_ORDER' I2S_SAMPLE_BIT_ORDER__enumvalues = { 0: 'I2S_SAMPLE_BIT_ORDER_MSB', 1: 'I2S_SAMPLE_BIT_ORDER_LSB', } I2S_SAMPLE_BIT_ORDER_MSB = 0 I2S_SAMPLE_BIT_ORDER_LSB = 1 I2S_SAMPLE_BIT_ORDER = ctypes.c_uint32 # enum # values for enumeration 'I2S_LRCLK_POLARITY' I2S_LRCLK_POLARITY__enumvalues = { 0: 'I2S_LRCLK_LOW_LEFT', 1: 'I2S_LRCLK_HIGH_LEFT', } I2S_LRCLK_LOW_LEFT = 0 I2S_LRCLK_HIGH_LEFT = 1 I2S_LRCLK_POLARITY = ctypes.c_uint32 # enum # values for enumeration 'I2S_WORD_ALIGNMENT' I2S_WORD_ALIGNMENT__enumvalues = { 0: 'I2S_WORD_ALTERNATE_ALIGNMENT', 1: 'I2S_WORD_I2S_ALIGNMENT', } I2S_WORD_ALTERNATE_ALIGNMENT = 0 I2S_WORD_I2S_ALIGNMENT = 1 I2S_WORD_ALIGNMENT = ctypes.c_uint32 # enum # values for enumeration 'SPDIF_INVERT_EN' SPDIF_INVERT_EN__enumvalues = { 0: 'SPDIF_INVERT_DISABLE', 1: 'SPDIF_INVERT_ENABLE', } SPDIF_INVERT_DISABLE = 0 SPDIF_INVERT_ENABLE = 1 SPDIF_INVERT_EN = ctypes.c_uint32 # enum # values for enumeration 'DPDBG_EN' DPDBG_EN__enumvalues = { 0: 'DPDBG_DISABLE', 1: 'DPDBG_ENABLE', } DPDBG_DISABLE = 0 DPDBG_ENABLE = 1 DPDBG_EN = ctypes.c_uint32 # enum # values for enumeration 'DPDBG_INPUT_EN' DPDBG_INPUT_EN__enumvalues = { 0: 'DPDBG_INPUT_DISABLE', 1: 'DPDBG_INPUT_ENABLE', } DPDBG_INPUT_DISABLE = 0 DPDBG_INPUT_ENABLE = 1 DPDBG_INPUT_EN = ctypes.c_uint32 # enum # values for enumeration 'DPDBG_ERROR_DETECTION_MODE' DPDBG_ERROR_DETECTION_MODE__enumvalues = { 0: 'DPDBG_ERROR_DETECTION_MODE_CSC', 1: 'DPDBG_ERROR_DETECTION_MODE_RS_ENCODING', } DPDBG_ERROR_DETECTION_MODE_CSC = 0 DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 1 DPDBG_ERROR_DETECTION_MODE = ctypes.c_uint32 # enum # values for enumeration 'DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK' DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK__enumvalues = { 0: 'DPDBG_FIFO_OVERFLOW_INT_DISABLE', 1: 'DPDBG_FIFO_OVERFLOW_INT_ENABLE', } DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0 DPDBG_FIFO_OVERFLOW_INT_ENABLE = 1 DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK = ctypes.c_uint32 # enum # values for enumeration 'DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE' DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE__enumvalues = { 0: 'DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED', 1: 'DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED', } DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0 DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 1 DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK' DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK__enumvalues = { 0: 'DPDBG_FIFO_OVERFLOW_INT_NO_ACK', 1: 'DPDBG_FIFO_OVERFLOW_INT_CLEAR', } DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0 DPDBG_FIFO_OVERFLOW_INT_CLEAR = 1 DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK = ctypes.c_uint32 # enum # values for enumeration 'PM_ASSERT_RESET' PM_ASSERT_RESET__enumvalues = { 0: 'PM_ASSERT_RESET_0', 1: 'PM_ASSERT_RESET_1', } PM_ASSERT_RESET_0 = 0 PM_ASSERT_RESET_1 = 1 PM_ASSERT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DAC_MUX_SELECT' DAC_MUX_SELECT__enumvalues = { 0: 'DAC_MUX_SELECT_DACA', 1: 'DAC_MUX_SELECT_DACB', } DAC_MUX_SELECT_DACA = 0 DAC_MUX_SELECT_DACB = 1 DAC_MUX_SELECT = ctypes.c_uint32 # enum # values for enumeration 'TMDS_DVO_MUX_SELECT' TMDS_DVO_MUX_SELECT__enumvalues = { 0: 'TMDS_DVO_MUX_SELECT_B', 1: 'TMDS_DVO_MUX_SELECT_G', 2: 'TMDS_DVO_MUX_SELECT_R', 3: 'TMDS_DVO_MUX_SELECT_RESERVED', } TMDS_DVO_MUX_SELECT_B = 0 TMDS_DVO_MUX_SELECT_G = 1 TMDS_DVO_MUX_SELECT_R = 2 TMDS_DVO_MUX_SELECT_RESERVED = 3 TMDS_DVO_MUX_SELECT = ctypes.c_uint32 # enum # values for enumeration 'DACA_SOFT_RESET' DACA_SOFT_RESET__enumvalues = { 0: 'DACA_SOFT_RESET_0', 1: 'DACA_SOFT_RESET_1', } DACA_SOFT_RESET_0 = 0 DACA_SOFT_RESET_1 = 1 DACA_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'I2S0_SPDIF0_SOFT_RESET' I2S0_SPDIF0_SOFT_RESET__enumvalues = { 0: 'I2S0_SPDIF0_SOFT_RESET_0', 1: 'I2S0_SPDIF0_SOFT_RESET_1', } I2S0_SPDIF0_SOFT_RESET_0 = 0 I2S0_SPDIF0_SOFT_RESET_1 = 1 I2S0_SPDIF0_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'I2S1_SOFT_RESET' I2S1_SOFT_RESET__enumvalues = { 0: 'I2S1_SOFT_RESET_0', 1: 'I2S1_SOFT_RESET_1', } I2S1_SOFT_RESET_0 = 0 I2S1_SOFT_RESET_1 = 1 I2S1_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'SPDIF1_SOFT_RESET' SPDIF1_SOFT_RESET__enumvalues = { 0: 'SPDIF1_SOFT_RESET_0', 1: 'SPDIF1_SOFT_RESET_1', } SPDIF1_SOFT_RESET_0 = 0 SPDIF1_SOFT_RESET_1 = 1 SPDIF1_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DB_CLK_SOFT_RESET' DB_CLK_SOFT_RESET__enumvalues = { 0: 'DB_CLK_SOFT_RESET_0', 1: 'DB_CLK_SOFT_RESET_1', } DB_CLK_SOFT_RESET_0 = 0 DB_CLK_SOFT_RESET_1 = 1 DB_CLK_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'FMT0_SOFT_RESET' FMT0_SOFT_RESET__enumvalues = { 0: 'FMT0_SOFT_RESET_0', 1: 'FMT0_SOFT_RESET_1', } FMT0_SOFT_RESET_0 = 0 FMT0_SOFT_RESET_1 = 1 FMT0_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'FMT1_SOFT_RESET' FMT1_SOFT_RESET__enumvalues = { 0: 'FMT1_SOFT_RESET_0', 1: 'FMT1_SOFT_RESET_1', } FMT1_SOFT_RESET_0 = 0 FMT1_SOFT_RESET_1 = 1 FMT1_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'FMT2_SOFT_RESET' FMT2_SOFT_RESET__enumvalues = { 0: 'FMT2_SOFT_RESET_0', 1: 'FMT2_SOFT_RESET_1', } FMT2_SOFT_RESET_0 = 0 FMT2_SOFT_RESET_1 = 1 FMT2_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'FMT3_SOFT_RESET' FMT3_SOFT_RESET__enumvalues = { 0: 'FMT3_SOFT_RESET_0', 1: 'FMT3_SOFT_RESET_1', } FMT3_SOFT_RESET_0 = 0 FMT3_SOFT_RESET_1 = 1 FMT3_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'FMT4_SOFT_RESET' FMT4_SOFT_RESET__enumvalues = { 0: 'FMT4_SOFT_RESET_0', 1: 'FMT4_SOFT_RESET_1', } FMT4_SOFT_RESET_0 = 0 FMT4_SOFT_RESET_1 = 1 FMT4_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'FMT5_SOFT_RESET' FMT5_SOFT_RESET__enumvalues = { 0: 'FMT5_SOFT_RESET_0', 1: 'FMT5_SOFT_RESET_1', } FMT5_SOFT_RESET_0 = 0 FMT5_SOFT_RESET_1 = 1 FMT5_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'MVP_SOFT_RESET' MVP_SOFT_RESET__enumvalues = { 0: 'MVP_SOFT_RESET_0', 1: 'MVP_SOFT_RESET_1', } MVP_SOFT_RESET_0 = 0 MVP_SOFT_RESET_1 = 1 MVP_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'ABM_SOFT_RESET' ABM_SOFT_RESET__enumvalues = { 0: 'ABM_SOFT_RESET_0', 1: 'ABM_SOFT_RESET_1', } ABM_SOFT_RESET_0 = 0 ABM_SOFT_RESET_1 = 1 ABM_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DVO_SOFT_RESET' DVO_SOFT_RESET__enumvalues = { 0: 'DVO_SOFT_RESET_0', 1: 'DVO_SOFT_RESET_1', } DVO_SOFT_RESET_0 = 0 DVO_SOFT_RESET_1 = 1 DVO_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGA_FE_SOFT_RESET' DIGA_FE_SOFT_RESET__enumvalues = { 0: 'DIGA_FE_SOFT_RESET_0', 1: 'DIGA_FE_SOFT_RESET_1', } DIGA_FE_SOFT_RESET_0 = 0 DIGA_FE_SOFT_RESET_1 = 1 DIGA_FE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGA_BE_SOFT_RESET' DIGA_BE_SOFT_RESET__enumvalues = { 0: 'DIGA_BE_SOFT_RESET_0', 1: 'DIGA_BE_SOFT_RESET_1', } DIGA_BE_SOFT_RESET_0 = 0 DIGA_BE_SOFT_RESET_1 = 1 DIGA_BE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGB_FE_SOFT_RESET' DIGB_FE_SOFT_RESET__enumvalues = { 0: 'DIGB_FE_SOFT_RESET_0', 1: 'DIGB_FE_SOFT_RESET_1', } DIGB_FE_SOFT_RESET_0 = 0 DIGB_FE_SOFT_RESET_1 = 1 DIGB_FE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGB_BE_SOFT_RESET' DIGB_BE_SOFT_RESET__enumvalues = { 0: 'DIGB_BE_SOFT_RESET_0', 1: 'DIGB_BE_SOFT_RESET_1', } DIGB_BE_SOFT_RESET_0 = 0 DIGB_BE_SOFT_RESET_1 = 1 DIGB_BE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGC_FE_SOFT_RESET' DIGC_FE_SOFT_RESET__enumvalues = { 0: 'DIGC_FE_SOFT_RESET_0', 1: 'DIGC_FE_SOFT_RESET_1', } DIGC_FE_SOFT_RESET_0 = 0 DIGC_FE_SOFT_RESET_1 = 1 DIGC_FE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGC_BE_SOFT_RESET' DIGC_BE_SOFT_RESET__enumvalues = { 0: 'DIGC_BE_SOFT_RESET_0', 1: 'DIGC_BE_SOFT_RESET_1', } DIGC_BE_SOFT_RESET_0 = 0 DIGC_BE_SOFT_RESET_1 = 1 DIGC_BE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGD_FE_SOFT_RESET' DIGD_FE_SOFT_RESET__enumvalues = { 0: 'DIGD_FE_SOFT_RESET_0', 1: 'DIGD_FE_SOFT_RESET_1', } DIGD_FE_SOFT_RESET_0 = 0 DIGD_FE_SOFT_RESET_1 = 1 DIGD_FE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGD_BE_SOFT_RESET' DIGD_BE_SOFT_RESET__enumvalues = { 0: 'DIGD_BE_SOFT_RESET_0', 1: 'DIGD_BE_SOFT_RESET_1', } DIGD_BE_SOFT_RESET_0 = 0 DIGD_BE_SOFT_RESET_1 = 1 DIGD_BE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGE_FE_SOFT_RESET' DIGE_FE_SOFT_RESET__enumvalues = { 0: 'DIGE_FE_SOFT_RESET_0', 1: 'DIGE_FE_SOFT_RESET_1', } DIGE_FE_SOFT_RESET_0 = 0 DIGE_FE_SOFT_RESET_1 = 1 DIGE_FE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGE_BE_SOFT_RESET' DIGE_BE_SOFT_RESET__enumvalues = { 0: 'DIGE_BE_SOFT_RESET_0', 1: 'DIGE_BE_SOFT_RESET_1', } DIGE_BE_SOFT_RESET_0 = 0 DIGE_BE_SOFT_RESET_1 = 1 DIGE_BE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGF_FE_SOFT_RESET' DIGF_FE_SOFT_RESET__enumvalues = { 0: 'DIGF_FE_SOFT_RESET_0', 1: 'DIGF_FE_SOFT_RESET_1', } DIGF_FE_SOFT_RESET_0 = 0 DIGF_FE_SOFT_RESET_1 = 1 DIGF_FE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGF_BE_SOFT_RESET' DIGF_BE_SOFT_RESET__enumvalues = { 0: 'DIGF_BE_SOFT_RESET_0', 1: 'DIGF_BE_SOFT_RESET_1', } DIGF_BE_SOFT_RESET_0 = 0 DIGF_BE_SOFT_RESET_1 = 1 DIGF_BE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGG_FE_SOFT_RESET' DIGG_FE_SOFT_RESET__enumvalues = { 0: 'DIGG_FE_SOFT_RESET_0', 1: 'DIGG_FE_SOFT_RESET_1', } DIGG_FE_SOFT_RESET_0 = 0 DIGG_FE_SOFT_RESET_1 = 1 DIGG_FE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGG_BE_SOFT_RESET' DIGG_BE_SOFT_RESET__enumvalues = { 0: 'DIGG_BE_SOFT_RESET_0', 1: 'DIGG_BE_SOFT_RESET_1', } DIGG_BE_SOFT_RESET_0 = 0 DIGG_BE_SOFT_RESET_1 = 1 DIGG_BE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DPDBG_SOFT_RESET' DPDBG_SOFT_RESET__enumvalues = { 0: 'DPDBG_SOFT_RESET_0', 1: 'DPDBG_SOFT_RESET_1', } DPDBG_SOFT_RESET_0 = 0 DPDBG_SOFT_RESET_1 = 1 DPDBG_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGLPA_FE_SOFT_RESET' DIGLPA_FE_SOFT_RESET__enumvalues = { 0: 'DIGLPA_FE_SOFT_RESET_0', 1: 'DIGLPA_FE_SOFT_RESET_1', } DIGLPA_FE_SOFT_RESET_0 = 0 DIGLPA_FE_SOFT_RESET_1 = 1 DIGLPA_FE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGLPA_BE_SOFT_RESET' DIGLPA_BE_SOFT_RESET__enumvalues = { 0: 'DIGLPA_BE_SOFT_RESET_0', 1: 'DIGLPA_BE_SOFT_RESET_1', } DIGLPA_BE_SOFT_RESET_0 = 0 DIGLPA_BE_SOFT_RESET_1 = 1 DIGLPA_BE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGLPB_FE_SOFT_RESET' DIGLPB_FE_SOFT_RESET__enumvalues = { 0: 'DIGLPB_FE_SOFT_RESET_0', 1: 'DIGLPB_FE_SOFT_RESET_1', } DIGLPB_FE_SOFT_RESET_0 = 0 DIGLPB_FE_SOFT_RESET_1 = 1 DIGLPB_FE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DIGLPB_BE_SOFT_RESET' DIGLPB_BE_SOFT_RESET__enumvalues = { 0: 'DIGLPB_BE_SOFT_RESET_0', 1: 'DIGLPB_BE_SOFT_RESET_1', } DIGLPB_BE_SOFT_RESET_0 = 0 DIGLPB_BE_SOFT_RESET_1 = 1 DIGLPB_BE_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'GENERICA_STEREOSYNC_SEL' GENERICA_STEREOSYNC_SEL__enumvalues = { 0: 'GENERICA_STEREOSYNC_SEL_D1', 1: 'GENERICA_STEREOSYNC_SEL_D2', 2: 'GENERICA_STEREOSYNC_SEL_D3', 3: 'GENERICA_STEREOSYNC_SEL_D4', 4: 'GENERICA_STEREOSYNC_SEL_D5', 5: 'GENERICA_STEREOSYNC_SEL_D6', 6: 'GENERICA_STEREOSYNC_SEL_RESERVED', } GENERICA_STEREOSYNC_SEL_D1 = 0 GENERICA_STEREOSYNC_SEL_D2 = 1 GENERICA_STEREOSYNC_SEL_D3 = 2 GENERICA_STEREOSYNC_SEL_D4 = 3 GENERICA_STEREOSYNC_SEL_D5 = 4 GENERICA_STEREOSYNC_SEL_D6 = 5 GENERICA_STEREOSYNC_SEL_RESERVED = 6 GENERICA_STEREOSYNC_SEL = ctypes.c_uint32 # enum # values for enumeration 'GENERICB_STEREOSYNC_SEL' GENERICB_STEREOSYNC_SEL__enumvalues = { 0: 'GENERICB_STEREOSYNC_SEL_D1', 1: 'GENERICB_STEREOSYNC_SEL_D2', 2: 'GENERICB_STEREOSYNC_SEL_D3', 3: 'GENERICB_STEREOSYNC_SEL_D4', 4: 'GENERICB_STEREOSYNC_SEL_D5', 5: 'GENERICB_STEREOSYNC_SEL_D6', 6: 'GENERICB_STEREOSYNC_SEL_RESERVED', } GENERICB_STEREOSYNC_SEL_D1 = 0 GENERICB_STEREOSYNC_SEL_D2 = 1 GENERICB_STEREOSYNC_SEL_D3 = 2 GENERICB_STEREOSYNC_SEL_D4 = 3 GENERICB_STEREOSYNC_SEL_D5 = 4 GENERICB_STEREOSYNC_SEL_D6 = 5 GENERICB_STEREOSYNC_SEL_RESERVED = 6 GENERICB_STEREOSYNC_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCO_DBG_BLOCK_SEL' DCO_DBG_BLOCK_SEL__enumvalues = { 0: 'DCO_DBG_BLOCK_SEL_DCO', 1: 'DCO_DBG_BLOCK_SEL_ABM', 2: 'DCO_DBG_BLOCK_SEL_DVO', 3: 'DCO_DBG_BLOCK_SEL_DAC', 4: 'DCO_DBG_BLOCK_SEL_MVP', 5: 'DCO_DBG_BLOCK_SEL_FMT0', 6: 'DCO_DBG_BLOCK_SEL_FMT1', 7: 'DCO_DBG_BLOCK_SEL_FMT2', 8: 'DCO_DBG_BLOCK_SEL_FMT3', 9: 'DCO_DBG_BLOCK_SEL_FMT4', 10: 'DCO_DBG_BLOCK_SEL_FMT5', 11: 'DCO_DBG_BLOCK_SEL_DIGFE_A', 12: 'DCO_DBG_BLOCK_SEL_DIGFE_B', 13: 'DCO_DBG_BLOCK_SEL_DIGFE_C', 14: 'DCO_DBG_BLOCK_SEL_DIGFE_D', 15: 'DCO_DBG_BLOCK_SEL_DIGFE_E', 16: 'DCO_DBG_BLOCK_SEL_DIGFE_F', 17: 'DCO_DBG_BLOCK_SEL_DIGFE_G', 18: 'DCO_DBG_BLOCK_SEL_DIGA', 19: 'DCO_DBG_BLOCK_SEL_DIGB', 20: 'DCO_DBG_BLOCK_SEL_DIGC', 21: 'DCO_DBG_BLOCK_SEL_DIGD', 22: 'DCO_DBG_BLOCK_SEL_DIGE', 23: 'DCO_DBG_BLOCK_SEL_DIGF', 24: 'DCO_DBG_BLOCK_SEL_DIGG', 25: 'DCO_DBG_BLOCK_SEL_DPFE_A', 26: 'DCO_DBG_BLOCK_SEL_DPFE_B', 27: 'DCO_DBG_BLOCK_SEL_DPFE_C', 28: 'DCO_DBG_BLOCK_SEL_DPFE_D', 29: 'DCO_DBG_BLOCK_SEL_DPFE_E', 30: 'DCO_DBG_BLOCK_SEL_DPFE_F', 31: 'DCO_DBG_BLOCK_SEL_DPFE_G', 32: 'DCO_DBG_BLOCK_SEL_DPA', 33: 'DCO_DBG_BLOCK_SEL_DPB', 34: 'DCO_DBG_BLOCK_SEL_DPC', 35: 'DCO_DBG_BLOCK_SEL_DPD', 36: 'DCO_DBG_BLOCK_SEL_DPE', 37: 'DCO_DBG_BLOCK_SEL_DPF', 38: 'DCO_DBG_BLOCK_SEL_DPG', 39: 'DCO_DBG_BLOCK_SEL_AUX0', 40: 'DCO_DBG_BLOCK_SEL_AUX1', 41: 'DCO_DBG_BLOCK_SEL_AUX2', 42: 'DCO_DBG_BLOCK_SEL_AUX3', 43: 'DCO_DBG_BLOCK_SEL_AUX4', 44: 'DCO_DBG_BLOCK_SEL_AUX5', 45: 'DCO_DBG_BLOCK_SEL_PERFMON_DCO', 46: 'DCO_DBG_BLOCK_SEL_AUDIO_OUT', 47: 'DCO_DBG_BLOCK_SEL_DIGLPFEA', 48: 'DCO_DBG_BLOCK_SEL_DIGLPFEB', 49: 'DCO_DBG_BLOCK_SEL_DIGLPA', 50: 'DCO_DBG_BLOCK_SEL_DIGLPB', 51: 'DCO_DBG_BLOCK_SEL_DPLPFEA', 52: 'DCO_DBG_BLOCK_SEL_DPLPFEB', 53: 'DCO_DBG_BLOCK_SEL_DPLPA', 54: 'DCO_DBG_BLOCK_SEL_DPLPB', } DCO_DBG_BLOCK_SEL_DCO = 0 DCO_DBG_BLOCK_SEL_ABM = 1 DCO_DBG_BLOCK_SEL_DVO = 2 DCO_DBG_BLOCK_SEL_DAC = 3 DCO_DBG_BLOCK_SEL_MVP = 4 DCO_DBG_BLOCK_SEL_FMT0 = 5 DCO_DBG_BLOCK_SEL_FMT1 = 6 DCO_DBG_BLOCK_SEL_FMT2 = 7 DCO_DBG_BLOCK_SEL_FMT3 = 8 DCO_DBG_BLOCK_SEL_FMT4 = 9 DCO_DBG_BLOCK_SEL_FMT5 = 10 DCO_DBG_BLOCK_SEL_DIGFE_A = 11 DCO_DBG_BLOCK_SEL_DIGFE_B = 12 DCO_DBG_BLOCK_SEL_DIGFE_C = 13 DCO_DBG_BLOCK_SEL_DIGFE_D = 14 DCO_DBG_BLOCK_SEL_DIGFE_E = 15 DCO_DBG_BLOCK_SEL_DIGFE_F = 16 DCO_DBG_BLOCK_SEL_DIGFE_G = 17 DCO_DBG_BLOCK_SEL_DIGA = 18 DCO_DBG_BLOCK_SEL_DIGB = 19 DCO_DBG_BLOCK_SEL_DIGC = 20 DCO_DBG_BLOCK_SEL_DIGD = 21 DCO_DBG_BLOCK_SEL_DIGE = 22 DCO_DBG_BLOCK_SEL_DIGF = 23 DCO_DBG_BLOCK_SEL_DIGG = 24 DCO_DBG_BLOCK_SEL_DPFE_A = 25 DCO_DBG_BLOCK_SEL_DPFE_B = 26 DCO_DBG_BLOCK_SEL_DPFE_C = 27 DCO_DBG_BLOCK_SEL_DPFE_D = 28 DCO_DBG_BLOCK_SEL_DPFE_E = 29 DCO_DBG_BLOCK_SEL_DPFE_F = 30 DCO_DBG_BLOCK_SEL_DPFE_G = 31 DCO_DBG_BLOCK_SEL_DPA = 32 DCO_DBG_BLOCK_SEL_DPB = 33 DCO_DBG_BLOCK_SEL_DPC = 34 DCO_DBG_BLOCK_SEL_DPD = 35 DCO_DBG_BLOCK_SEL_DPE = 36 DCO_DBG_BLOCK_SEL_DPF = 37 DCO_DBG_BLOCK_SEL_DPG = 38 DCO_DBG_BLOCK_SEL_AUX0 = 39 DCO_DBG_BLOCK_SEL_AUX1 = 40 DCO_DBG_BLOCK_SEL_AUX2 = 41 DCO_DBG_BLOCK_SEL_AUX3 = 42 DCO_DBG_BLOCK_SEL_AUX4 = 43 DCO_DBG_BLOCK_SEL_AUX5 = 44 DCO_DBG_BLOCK_SEL_PERFMON_DCO = 45 DCO_DBG_BLOCK_SEL_AUDIO_OUT = 46 DCO_DBG_BLOCK_SEL_DIGLPFEA = 47 DCO_DBG_BLOCK_SEL_DIGLPFEB = 48 DCO_DBG_BLOCK_SEL_DIGLPA = 49 DCO_DBG_BLOCK_SEL_DIGLPB = 50 DCO_DBG_BLOCK_SEL_DPLPFEA = 51 DCO_DBG_BLOCK_SEL_DPLPFEB = 52 DCO_DBG_BLOCK_SEL_DPLPA = 53 DCO_DBG_BLOCK_SEL_DPLPB = 54 DCO_DBG_BLOCK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE' DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = { 0: 'DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', 1: 'DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', } DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0 DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1 DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum # values for enumeration 'FMT420_MEMORY_SOURCE_SEL' FMT420_MEMORY_SOURCE_SEL__enumvalues = { 0: 'FMT420_MEMORY_SOURCE_SEL_FMT0', 1: 'FMT420_MEMORY_SOURCE_SEL_FMT1', 2: 'FMT420_MEMORY_SOURCE_SEL_FMT2', 3: 'FMT420_MEMORY_SOURCE_SEL_FMT3', 4: 'FMT420_MEMORY_SOURCE_SEL_FMT4', 5: 'FMT420_MEMORY_SOURCE_SEL_FMT5', 6: 'FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED', } FMT420_MEMORY_SOURCE_SEL_FMT0 = 0 FMT420_MEMORY_SOURCE_SEL_FMT1 = 1 FMT420_MEMORY_SOURCE_SEL_FMT2 = 2 FMT420_MEMORY_SOURCE_SEL_FMT3 = 3 FMT420_MEMORY_SOURCE_SEL_FMT4 = 4 FMT420_MEMORY_SOURCE_SEL_FMT5 = 5 FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED = 6 FMT420_MEMORY_SOURCE_SEL = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_CONTROL_GO' DOUT_I2C_CONTROL_GO__enumvalues = { 0: 'DOUT_I2C_CONTROL_STOP_TRANSFER', 1: 'DOUT_I2C_CONTROL_START_TRANSFER', } DOUT_I2C_CONTROL_STOP_TRANSFER = 0 DOUT_I2C_CONTROL_START_TRANSFER = 1 DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET' DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = { 0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', 1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', } DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0 DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1 DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET' DOUT_I2C_CONTROL_SEND_RESET__enumvalues = { 0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET', 1: 'DOUT_I2C_CONTROL__SEND_RESET', } DOUT_I2C_CONTROL__NOT_SEND_RESET = 0 DOUT_I2C_CONTROL__SEND_RESET = 1 DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET' DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = { 0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', 1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS', } DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0 DOUT_I2C_CONTROL_RESET_SW_STATUS = 1 DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT' DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = { 0: 'DOUT_I2C_CONTROL_SELECT_DDC1', 1: 'DOUT_I2C_CONTROL_SELECT_DDC2', 2: 'DOUT_I2C_CONTROL_SELECT_DDC3', 3: 'DOUT_I2C_CONTROL_SELECT_DDC4', 4: 'DOUT_I2C_CONTROL_SELECT_DDC5', 5: 'DOUT_I2C_CONTROL_SELECT_DDC6', 6: 'DOUT_I2C_CONTROL_SELECT_DDCVGA', } DOUT_I2C_CONTROL_SELECT_DDC1 = 0 DOUT_I2C_CONTROL_SELECT_DDC2 = 1 DOUT_I2C_CONTROL_SELECT_DDC3 = 2 DOUT_I2C_CONTROL_SELECT_DDC4 = 3 DOUT_I2C_CONTROL_SELECT_DDC5 = 4 DOUT_I2C_CONTROL_SELECT_DDC6 = 5 DOUT_I2C_CONTROL_SELECT_DDCVGA = 6 DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT' DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = { 0: 'DOUT_I2C_CONTROL_TRANS0', 1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1', 2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', 3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', } DOUT_I2C_CONTROL_TRANS0 = 0 DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3 DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_CONTROL_DBG_REF_SEL' DOUT_I2C_CONTROL_DBG_REF_SEL__enumvalues = { 0: 'DOUT_I2C_CONTROL_NORMAL_DEBUG', 1: 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', } DOUT_I2C_CONTROL_NORMAL_DEBUG = 0 DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 1 DOUT_I2C_CONTROL_DBG_REF_SEL = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY' DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = { 0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', 1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', 2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', 3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', } DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0 DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1 DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2 DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3 DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO' DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = { 0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', 1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', } DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0 DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1 DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER' DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = { 0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', 1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', } DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0 DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1 DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ' DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = { 0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', 1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', } DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0 DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1 DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG' DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = { 0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', 1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', } DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0 DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1 DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_ACK' DOUT_I2C_ACK__enumvalues = { 0: 'DOUT_I2C_NO_ACK', 1: 'DOUT_I2C_ACK_TO_CLEAN', } DOUT_I2C_NO_ACK = 0 DOUT_I2C_ACK_TO_CLEAN = 1 DOUT_I2C_ACK = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD' DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = { 0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', 1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', 2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', 3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', } DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0 DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1 DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2 DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3 DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN' DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = { 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', } DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1 DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL' DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = { 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', 1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', } DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0 DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1 DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE' DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = { 0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', 1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', } DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0 DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1 DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN' DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = { 0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', } DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1 DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK' DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = { 0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', 1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', } DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0 DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1 DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE' DOUT_I2C_DATA_INDEX_WRITE__enumvalues = { 0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE', 1: 'DOUT_I2C_DATA__INDEX_WRITE', } DOUT_I2C_DATA__NOT_INDEX_WRITE = 0 DOUT_I2C_DATA__INDEX_WRITE = 1 DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET' DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = { 0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', 1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', } DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0 DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1 DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum # values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE' DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = { 0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', 1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', } DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'FBC_IDLE_MASK_MASK_BITS' FBC_IDLE_MASK_MASK_BITS__enumvalues = { 0: 'FBC_IDLE_MASK_DISP_REG_UPDATE', 1: 'FBC_IDLE_MASK_RESERVED1', 2: 'FBC_IDLE_MASK_FBC_GRPH_COMP_EN', 3: 'FBC_IDLE_MASK_FBC_MIN_COMPRESSION', 4: 'FBC_IDLE_MASK_FBC_ALPHA_COMP_EN', 5: 'FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN', 6: 'FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF', 7: 'FBC_IDLE_MASK_RESERVED7', 8: 'FBC_IDLE_MASK_RESERVED8', 9: 'FBC_IDLE_MASK_RESERVED9', 10: 'FBC_IDLE_MASK_RESERVED10', 11: 'FBC_IDLE_MASK_RESERVED11', 12: 'FBC_IDLE_MASK_RESERVED12', 13: 'FBC_IDLE_MASK_RESERVED13', 14: 'FBC_IDLE_MASK_RESERVED14', 15: 'FBC_IDLE_MASK_RESERVED15', 16: 'FBC_IDLE_MASK_RESERVED16', 17: 'FBC_IDLE_MASK_RESERVED17', 18: 'FBC_IDLE_MASK_RESERVED18', 19: 'FBC_IDLE_MASK_RESERVED19', 20: 'FBC_IDLE_MASK_RESERVED20', 21: 'FBC_IDLE_MASK_RESERVED21', 22: 'FBC_IDLE_MASK_RESERVED22', 23: 'FBC_IDLE_MASK_RESERVED23', 24: 'FBC_IDLE_MASK_MC_HIT_REGION_0', 25: 'FBC_IDLE_MASK_MC_HIT_REGION_1', 26: 'FBC_IDLE_MASK_MC_HIT_REGION_2', 27: 'FBC_IDLE_MASK_MC_HIT_REGION_3', 28: 'FBC_IDLE_MASK_MC_WRITE', 29: 'FBC_IDLE_MASK_RESERVED29', 30: 'FBC_IDLE_MASK_RESERVED30', 31: 'FBC_IDLE_MASK_RESERVED31', } FBC_IDLE_MASK_DISP_REG_UPDATE = 0 FBC_IDLE_MASK_RESERVED1 = 1 FBC_IDLE_MASK_FBC_GRPH_COMP_EN = 2 FBC_IDLE_MASK_FBC_MIN_COMPRESSION = 3 FBC_IDLE_MASK_FBC_ALPHA_COMP_EN = 4 FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN = 5 FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF = 6 FBC_IDLE_MASK_RESERVED7 = 7 FBC_IDLE_MASK_RESERVED8 = 8 FBC_IDLE_MASK_RESERVED9 = 9 FBC_IDLE_MASK_RESERVED10 = 10 FBC_IDLE_MASK_RESERVED11 = 11 FBC_IDLE_MASK_RESERVED12 = 12 FBC_IDLE_MASK_RESERVED13 = 13 FBC_IDLE_MASK_RESERVED14 = 14 FBC_IDLE_MASK_RESERVED15 = 15 FBC_IDLE_MASK_RESERVED16 = 16 FBC_IDLE_MASK_RESERVED17 = 17 FBC_IDLE_MASK_RESERVED18 = 18 FBC_IDLE_MASK_RESERVED19 = 19 FBC_IDLE_MASK_RESERVED20 = 20 FBC_IDLE_MASK_RESERVED21 = 21 FBC_IDLE_MASK_RESERVED22 = 22 FBC_IDLE_MASK_RESERVED23 = 23 FBC_IDLE_MASK_MC_HIT_REGION_0 = 24 FBC_IDLE_MASK_MC_HIT_REGION_1 = 25 FBC_IDLE_MASK_MC_HIT_REGION_2 = 26 FBC_IDLE_MASK_MC_HIT_REGION_3 = 27 FBC_IDLE_MASK_MC_WRITE = 28 FBC_IDLE_MASK_RESERVED29 = 29 FBC_IDLE_MASK_RESERVED30 = 30 FBC_IDLE_MASK_RESERVED31 = 31 FBC_IDLE_MASK_MASK_BITS = ctypes.c_uint32 # enum # values for enumeration 'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL' DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL__enumvalues = { 0: 'DPCSRX_BPHY_PCS_RX0_CLK', 1: 'DPCSRX_BPHY_PCS_RX1_CLK', 2: 'DPCSRX_BPHY_PCS_RX2_CLK', 3: 'DPCSRX_BPHY_PCS_RX3_CLK', } DPCSRX_BPHY_PCS_RX0_CLK = 0 DPCSRX_BPHY_PCS_RX1_CLK = 1 DPCSRX_BPHY_PCS_RX2_CLK = 2 DPCSRX_BPHY_PCS_RX3_CLK = 3 DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL = ctypes.c_uint32 # enum # values for enumeration 'DPCSRX_DBG_CFGCLK_SEL' DPCSRX_DBG_CFGCLK_SEL__enumvalues = { 0: 'DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF', 1: 'DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', 2: 'DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE', 3: 'DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER', } DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0 DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 1 DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE = 2 DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER = 3 DPCSRX_DBG_CFGCLK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DPCSRX_RX_SYMCLK_SEL' DPCSRX_RX_SYMCLK_SEL__enumvalues = { 0: 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT0', 1: 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT1', 2: 'DPCSRX_DBG_RX_SYMCLK_SEL_INT', } DPCSRX_DBG_RX_SYMCLK_SEL_OUT0 = 0 DPCSRX_DBG_RX_SYMCLK_SEL_OUT1 = 1 DPCSRX_DBG_RX_SYMCLK_SEL_INT = 2 DPCSRX_RX_SYMCLK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DPCSTX_DBG_CFGCLK_SEL' DPCSTX_DBG_CFGCLK_SEL__enumvalues = { 0: 'DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF', 1: 'DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', 2: 'DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE', 3: 'DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER', } DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0 DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 1 DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE = 2 DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER = 3 DPCSTX_DBG_CFGCLK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DPCSTX_TX_SYMCLK_SEL' DPCSTX_TX_SYMCLK_SEL__enumvalues = { 0: 'DPCSTX_DBG_TX_SYMCLK_SEL_IN0', 1: 'DPCSTX_DBG_TX_SYMCLK_SEL_IN1', 2: 'DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR', } DPCSTX_DBG_TX_SYMCLK_SEL_IN0 = 0 DPCSTX_DBG_TX_SYMCLK_SEL_IN1 = 1 DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR = 2 DPCSTX_TX_SYMCLK_SEL = ctypes.c_uint32 # enum # values for enumeration 'DPCSTX_TX_SYMCLK_DIV2_SEL' DPCSTX_TX_SYMCLK_DIV2_SEL__enumvalues = { 0: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0', 1: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1', 2: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2', 3: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3', 4: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD', 5: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT', } DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0 = 0 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1 = 1 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2 = 2 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3 = 3 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD = 4 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT = 5 DPCSTX_TX_SYMCLK_DIV2_SEL = ctypes.c_uint32 # enum # values for enumeration 'SurfaceNumber' SurfaceNumber__enumvalues = { 0: 'NUMBER_UNORM', 1: 'NUMBER_SNORM', 2: 'NUMBER_USCALED', 3: 'NUMBER_SSCALED', 4: 'NUMBER_UINT', 5: 'NUMBER_SINT', 6: 'NUMBER_SRGB', 7: 'NUMBER_FLOAT', } NUMBER_UNORM = 0 NUMBER_SNORM = 1 NUMBER_USCALED = 2 NUMBER_SSCALED = 3 NUMBER_UINT = 4 NUMBER_SINT = 5 NUMBER_SRGB = 6 NUMBER_FLOAT = 7 SurfaceNumber = ctypes.c_uint32 # enum # values for enumeration 'SurfaceSwap' SurfaceSwap__enumvalues = { 0: 'SWAP_STD', 1: 'SWAP_ALT', 2: 'SWAP_STD_REV', 3: 'SWAP_ALT_REV', } SWAP_STD = 0 SWAP_ALT = 1 SWAP_STD_REV = 2 SWAP_ALT_REV = 3 SurfaceSwap = ctypes.c_uint32 # enum # values for enumeration 'CBMode' CBMode__enumvalues = { 0: 'CB_DISABLE', 1: 'CB_NORMAL', 2: 'CB_ELIMINATE_FAST_CLEAR', 3: 'CB_RESOLVE', 4: 'CB_DECOMPRESS', 5: 'CB_FMASK_DECOMPRESS', 6: 'CB_DCC_DECOMPRESS', } CB_DISABLE = 0 CB_NORMAL = 1 CB_ELIMINATE_FAST_CLEAR = 2 CB_RESOLVE = 3 CB_DECOMPRESS = 4 CB_FMASK_DECOMPRESS = 5 CB_DCC_DECOMPRESS = 6 CBMode = ctypes.c_uint32 # enum # values for enumeration 'RoundMode' RoundMode__enumvalues = { 0: 'ROUND_BY_HALF', 1: 'ROUND_TRUNCATE', } ROUND_BY_HALF = 0 ROUND_TRUNCATE = 1 RoundMode = ctypes.c_uint32 # enum # values for enumeration 'SourceFormat' SourceFormat__enumvalues = { 0: 'EXPORT_4C_32BPC', 1: 'EXPORT_4C_16BPC', 2: 'EXPORT_2C_32BPC_GR', 3: 'EXPORT_2C_32BPC_AR', } EXPORT_4C_32BPC = 0 EXPORT_4C_16BPC = 1 EXPORT_2C_32BPC_GR = 2 EXPORT_2C_32BPC_AR = 3 SourceFormat = ctypes.c_uint32 # enum # values for enumeration 'BlendOp' BlendOp__enumvalues = { 0: 'BLEND_ZERO', 1: 'BLEND_ONE', 2: 'BLEND_SRC_COLOR', 3: 'BLEND_ONE_MINUS_SRC_COLOR', 4: 'BLEND_SRC_ALPHA', 5: 'BLEND_ONE_MINUS_SRC_ALPHA', 6: 'BLEND_DST_ALPHA', 7: 'BLEND_ONE_MINUS_DST_ALPHA', 8: 'BLEND_DST_COLOR', 9: 'BLEND_ONE_MINUS_DST_COLOR', 10: 'BLEND_SRC_ALPHA_SATURATE', 11: 'BLEND_BOTH_SRC_ALPHA', 12: 'BLEND_BOTH_INV_SRC_ALPHA', 13: 'BLEND_CONSTANT_COLOR', 14: 'BLEND_ONE_MINUS_CONSTANT_COLOR', 15: 'BLEND_SRC1_COLOR', 16: 'BLEND_INV_SRC1_COLOR', 17: 'BLEND_SRC1_ALPHA', 18: 'BLEND_INV_SRC1_ALPHA', 19: 'BLEND_CONSTANT_ALPHA', 20: 'BLEND_ONE_MINUS_CONSTANT_ALPHA', } BLEND_ZERO = 0 BLEND_ONE = 1 BLEND_SRC_COLOR = 2 BLEND_ONE_MINUS_SRC_COLOR = 3 BLEND_SRC_ALPHA = 4 BLEND_ONE_MINUS_SRC_ALPHA = 5 BLEND_DST_ALPHA = 6 BLEND_ONE_MINUS_DST_ALPHA = 7 BLEND_DST_COLOR = 8 BLEND_ONE_MINUS_DST_COLOR = 9 BLEND_SRC_ALPHA_SATURATE = 10 BLEND_BOTH_SRC_ALPHA = 11 BLEND_BOTH_INV_SRC_ALPHA = 12 BLEND_CONSTANT_COLOR = 13 BLEND_ONE_MINUS_CONSTANT_COLOR = 14 BLEND_SRC1_COLOR = 15 BLEND_INV_SRC1_COLOR = 16 BLEND_SRC1_ALPHA = 17 BLEND_INV_SRC1_ALPHA = 18 BLEND_CONSTANT_ALPHA = 19 BLEND_ONE_MINUS_CONSTANT_ALPHA = 20 BlendOp = ctypes.c_uint32 # enum GL__ZERO = BLEND_ZERO # macro GL__ONE = BLEND_ONE # macro GL__SRC_COLOR = BLEND_SRC_COLOR # macro GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro GL__DST_COLOR = BLEND_DST_COLOR # macro GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro GL__DST_ALPHA = BLEND_DST_ALPHA # macro GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro # values for enumeration 'CombFunc' CombFunc__enumvalues = { 0: 'COMB_DST_PLUS_SRC', 1: 'COMB_SRC_MINUS_DST', 2: 'COMB_MIN_DST_SRC', 3: 'COMB_MAX_DST_SRC', 4: 'COMB_DST_MINUS_SRC', } COMB_DST_PLUS_SRC = 0 COMB_SRC_MINUS_DST = 1 COMB_MIN_DST_SRC = 2 COMB_MAX_DST_SRC = 3 COMB_DST_MINUS_SRC = 4 CombFunc = ctypes.c_uint32 # enum # values for enumeration 'BlendOpt' BlendOpt__enumvalues = { 0: 'FORCE_OPT_AUTO', 1: 'FORCE_OPT_DISABLE', 2: 'FORCE_OPT_ENABLE_IF_SRC_A_0', 3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', 4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', 5: 'FORCE_OPT_ENABLE_IF_SRC_A_1', 6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', } FORCE_OPT_AUTO = 0 FORCE_OPT_DISABLE = 1 FORCE_OPT_ENABLE_IF_SRC_A_0 = 2 FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3 FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4 FORCE_OPT_ENABLE_IF_SRC_A_1 = 5 FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6 FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7 BlendOpt = ctypes.c_uint32 # enum # values for enumeration 'CmaskCode' CmaskCode__enumvalues = { 0: 'CMASK_CLR00_F0', 1: 'CMASK_CLR00_F1', 2: 'CMASK_CLR00_F2', 3: 'CMASK_CLR00_FX', 4: 'CMASK_CLR01_F0', 5: 'CMASK_CLR01_F1', 6: 'CMASK_CLR01_F2', 7: 'CMASK_CLR01_FX', 8: 'CMASK_CLR10_F0', 9: 'CMASK_CLR10_F1', 10: 'CMASK_CLR10_F2', 11: 'CMASK_CLR10_FX', 12: 'CMASK_CLR11_F0', 13: 'CMASK_CLR11_F1', 14: 'CMASK_CLR11_F2', 15: 'CMASK_CLR11_FX', } CMASK_CLR00_F0 = 0 CMASK_CLR00_F1 = 1 CMASK_CLR00_F2 = 2 CMASK_CLR00_FX = 3 CMASK_CLR01_F0 = 4 CMASK_CLR01_F1 = 5 CMASK_CLR01_F2 = 6 CMASK_CLR01_FX = 7 CMASK_CLR10_F0 = 8 CMASK_CLR10_F1 = 9 CMASK_CLR10_F2 = 10 CMASK_CLR10_FX = 11 CMASK_CLR11_F0 = 12 CMASK_CLR11_F1 = 13 CMASK_CLR11_F2 = 14 CMASK_CLR11_FX = 15 CmaskCode = ctypes.c_uint32 # enum # values for enumeration 'CmaskAddr' CmaskAddr__enumvalues = { 0: 'CMASK_ADDR_TILED', 1: 'CMASK_ADDR_LINEAR', 2: 'CMASK_ADDR_COMPATIBLE', } CMASK_ADDR_TILED = 0 CMASK_ADDR_LINEAR = 1 CMASK_ADDR_COMPATIBLE = 2 CmaskAddr = ctypes.c_uint32 # enum # values for enumeration 'MemArbMode' MemArbMode__enumvalues = { 0: 'MEM_ARB_MODE_FIXED', 1: 'MEM_ARB_MODE_AGE', 2: 'MEM_ARB_MODE_WEIGHT', 3: 'MEM_ARB_MODE_BOTH', } MEM_ARB_MODE_FIXED = 0 MEM_ARB_MODE_AGE = 1 MEM_ARB_MODE_WEIGHT = 2 MEM_ARB_MODE_BOTH = 3 MemArbMode = ctypes.c_uint32 # enum # values for enumeration 'CBPerfSel' CBPerfSel__enumvalues = { 0: 'CB_PERF_SEL_NONE', 1: 'CB_PERF_SEL_BUSY', 2: 'CB_PERF_SEL_CORE_SCLK_VLD', 3: 'CB_PERF_SEL_REG_SCLK0_VLD', 4: 'CB_PERF_SEL_REG_SCLK1_VLD', 5: 'CB_PERF_SEL_DRAWN_QUAD', 6: 'CB_PERF_SEL_DRAWN_PIXEL', 7: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 8: 'CB_PERF_SEL_DRAWN_TILE', 9: 'CB_PERF_SEL_DB_CB_TILE_VALID_READY', 10: 'CB_PERF_SEL_DB_CB_TILE_VALID_READYB', 11: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY', 12: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB', 13: 'CB_PERF_SEL_CM_FC_TILE_VALID_READY', 14: 'CB_PERF_SEL_CM_FC_TILE_VALID_READYB', 15: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY', 16: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB', 17: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY', 18: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB', 19: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY', 20: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB', 21: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY', 22: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB', 23: 'CB_PERF_SEL_LQUAD_NO_TILE', 24: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R', 25: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR', 26: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR', 27: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR', 28: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR', 29: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR', 30: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR', 31: 'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT', 32: 'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID', 33: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK', 34: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK', 35: 'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL', 36: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY', 37: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB', 38: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY', 39: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB', 40: 'CB_PERF_SEL_FOP_IN_VALID_READY', 41: 'CB_PERF_SEL_FOP_IN_VALID_READYB', 42: 'CB_PERF_SEL_FOP_IN_VALIDB_READY', 43: 'CB_PERF_SEL_FOP_IN_VALIDB_READYB', 44: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY', 45: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB', 46: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY', 47: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB', 48: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY', 49: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB', 50: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY', 51: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB', 52: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY', 53: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB', 54: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY', 55: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB', 56: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY', 57: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB', 58: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY', 59: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB', 60: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY', 61: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB', 62: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY', 63: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB', 64: 'CB_PERF_SEL_CC_BC_CS_FRAG_VALID', 65: 'CB_PERF_SEL_CM_CACHE_HIT', 66: 'CB_PERF_SEL_CM_CACHE_TAG_MISS', 67: 'CB_PERF_SEL_CM_CACHE_SECTOR_MISS', 68: 'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL', 69: 'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL', 70: 'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL', 71: 'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', 72: 'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL', 73: 'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL', 74: 'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL', 75: 'CB_PERF_SEL_CM_CACHE_STALL', 76: 'CB_PERF_SEL_CM_CACHE_FLUSH', 77: 'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED', 78: 'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED', 79: 'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED', 80: 'CB_PERF_SEL_FC_CACHE_HIT', 81: 'CB_PERF_SEL_FC_CACHE_TAG_MISS', 82: 'CB_PERF_SEL_FC_CACHE_SECTOR_MISS', 83: 'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL', 84: 'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', 85: 'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL', 86: 'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', 87: 'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL', 88: 'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL', 89: 'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL', 90: 'CB_PERF_SEL_FC_CACHE_STALL', 91: 'CB_PERF_SEL_FC_CACHE_FLUSH', 92: 'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED', 93: 'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED', 94: 'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED', 95: 'CB_PERF_SEL_CC_CACHE_HIT', 96: 'CB_PERF_SEL_CC_CACHE_TAG_MISS', 97: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 98: 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', 99: 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', 100: 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', 101: 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', 102: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', 103: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', 104: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', 105: 'CB_PERF_SEL_CC_CACHE_STALL', 106: 'CB_PERF_SEL_CC_CACHE_FLUSH', 107: 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', 108: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', 109: 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', 110: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', 111: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', 112: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY', 113: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB', 114: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY', 115: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB', 116: 'CB_PERF_SEL_CM_MC_WRITE_REQUEST', 117: 'CB_PERF_SEL_FC_MC_WRITE_REQUEST', 118: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', 119: 'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT', 120: 'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT', 121: 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', 122: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY', 123: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB', 124: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY', 125: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB', 126: 'CB_PERF_SEL_CM_MC_READ_REQUEST', 127: 'CB_PERF_SEL_FC_MC_READ_REQUEST', 128: 'CB_PERF_SEL_CC_MC_READ_REQUEST', 129: 'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT', 130: 'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT', 131: 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', 132: 'CB_PERF_SEL_CM_TQ_FULL', 133: 'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL', 134: 'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL', 135: 'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL', 136: 'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL', 137: 'CB_PERF_SEL_FOP_FMASK_RAW_STALL', 138: 'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL', 139: 'CB_PERF_SEL_CC_SF_FULL', 140: 'CB_PERF_SEL_CC_RB_FULL', 141: 'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL', 142: 'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL', 143: 'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL', 144: 'CB_PERF_SEL_EVENT', 145: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', 146: 'CB_PERF_SEL_EVENT_CONTEXT_DONE', 147: 'CB_PERF_SEL_EVENT_CACHE_FLUSH', 148: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', 149: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', 150: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', 151: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', 152: 'CB_PERF_SEL_CC_SURFACE_SYNC', 153: 'CB_PERF_SEL_CMASK_READ_DATA_0xC', 154: 'CB_PERF_SEL_CMASK_READ_DATA_0xD', 155: 'CB_PERF_SEL_CMASK_READ_DATA_0xE', 156: 'CB_PERF_SEL_CMASK_READ_DATA_0xF', 157: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xC', 158: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xD', 159: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xE', 160: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xF', 161: 'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT', 162: 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', 163: 'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT', 164: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE', 165: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE', 166: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE', 167: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE', 168: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE', 169: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE', 170: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE', 171: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE', 172: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE', 173: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE', 174: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE', 175: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE', 176: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE', 177: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE', 178: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE', 179: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE', 180: 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT', 181: 'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS', 182: 'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS', 183: 'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS', 184: 'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS', 185: 'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS', 186: 'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS', 187: 'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT', 188: 'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS', 189: 'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS', 190: 'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS', 191: 'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS', 192: 'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS', 193: 'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS', 194: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_0', 195: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_1', 196: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_2', 197: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_3', 198: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_4', 199: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_5', 200: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_6', 201: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_7', 202: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0', 203: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1', 204: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2', 205: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3', 206: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4', 207: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5', 208: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6', 209: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7', 210: 'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST', 211: 'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS', 212: 'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS', 213: 'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', 214: 'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', 215: 'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED', 216: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', 217: 'CB_PERF_SEL_DRAWN_BUSY', 218: 'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY', 219: 'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY', 220: 'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY', 221: 'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY', 222: 'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED', 223: 'CB_PERF_SEL_FC_SEQUENCER_CLEAR', 224: 'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR', 225: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS', 226: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE', 227: 'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL', 228: 'CB_PERF_SEL_FC_DOC_IS_STALLED', 229: 'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED', 230: 'CB_PERF_SEL_FC_DOC_MRTS_COMBINED', 231: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS', 232: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT', 233: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS', 234: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT', 235: 'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL', 236: 'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR', 237: 'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS', 238: 'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS', 239: 'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS', 240: 'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS', 241: 'CB_PERF_SEL_FC_DCC_CACHE_HIT', 242: 'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS', 243: 'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS', 244: 'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL', 245: 'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', 246: 'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', 247: 'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', 248: 'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL', 249: 'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL', 250: 'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL', 251: 'CB_PERF_SEL_FC_DCC_CACHE_STALL', 252: 'CB_PERF_SEL_FC_DCC_CACHE_FLUSH', 253: 'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED', 254: 'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED', 255: 'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED', 256: 'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT', 257: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST', 258: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT', 259: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST', 260: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT', 261: 'CB_PERF_SEL_CC_DCC_RDREQ_STALL', 262: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN', 263: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT', 264: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN', 265: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT', 266: 'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR', 267: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1', 268: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2', 269: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', 270: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1', 271: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1', 272: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2', 273: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1', 274: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', 275: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', 276: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1', 277: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2', 278: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2', 279: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2', 280: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', 281: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1', 282: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1', 283: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2', 284: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3', 285: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4', 286: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1', 287: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2', 288: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3', 289: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4', 290: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1', 291: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2', 292: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3', 293: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4', 294: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1', 295: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2', 296: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3', 297: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1', 298: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2', 299: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3', 300: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4', 301: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1', 302: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2', 303: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3', 304: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4', 305: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1', 306: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2', 307: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3', 308: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4', 309: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1', 310: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2', 311: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3', 312: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1', 313: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1', 314: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1', 315: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1', 316: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1', 317: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1', 318: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1', 319: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1', 320: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2', 321: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2', 322: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2', 323: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2', 324: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2', 325: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2', 326: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2', 327: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1', 328: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1', 329: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1', 330: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1', 331: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2', 332: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2', 333: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2', 334: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2', 335: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2', 336: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2', 337: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2', 338: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1', 339: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1', 340: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1', 341: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1', 342: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1', 343: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2', 344: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3', 345: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4', 346: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5', 347: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6', 348: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0', 349: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1', 350: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1', 351: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2', 352: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3', 353: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4', 354: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5', 355: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0', 356: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1', 357: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1', 358: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1', 359: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1', 360: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1', 361: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1', 362: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1', 363: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1', 364: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1', 365: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2', 366: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2', 367: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2', 368: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2', 369: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2', 370: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2', 371: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2', 372: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1', 373: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2', 374: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3', 375: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4', 376: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5', 377: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6', 378: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7', 379: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED', 380: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1', 381: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1', 382: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2', 383: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3', 384: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1', 385: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2', 386: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3', 387: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4', 388: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5', 389: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1', 390: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2', 391: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3', 392: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4', 393: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5', 394: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6', 395: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7', 396: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', 397: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', 398: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', 399: 'CB_PERF_SEL_RBP_SPLIT_MICROTILE', 400: 'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK', 401: 'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK', 402: 'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING', 403: 'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS', 404: 'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD', } CB_PERF_SEL_NONE = 0 CB_PERF_SEL_BUSY = 1 CB_PERF_SEL_CORE_SCLK_VLD = 2 CB_PERF_SEL_REG_SCLK0_VLD = 3 CB_PERF_SEL_REG_SCLK1_VLD = 4 CB_PERF_SEL_DRAWN_QUAD = 5 CB_PERF_SEL_DRAWN_PIXEL = 6 CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 7 CB_PERF_SEL_DRAWN_TILE = 8 CB_PERF_SEL_DB_CB_TILE_VALID_READY = 9 CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 10 CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 11 CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 12 CB_PERF_SEL_CM_FC_TILE_VALID_READY = 13 CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 14 CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 15 CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 16 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 17 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 18 CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 19 CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 20 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 21 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 22 CB_PERF_SEL_LQUAD_NO_TILE = 23 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 24 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 25 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 26 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 27 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 28 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 29 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 30 CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 31 CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 32 CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 33 CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 34 CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 35 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 36 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 37 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 38 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 39 CB_PERF_SEL_FOP_IN_VALID_READY = 40 CB_PERF_SEL_FOP_IN_VALID_READYB = 41 CB_PERF_SEL_FOP_IN_VALIDB_READY = 42 CB_PERF_SEL_FOP_IN_VALIDB_READYB = 43 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 44 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 45 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 46 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 47 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 48 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 49 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 50 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 51 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 52 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 53 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 54 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 55 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 56 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 57 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 58 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 59 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 60 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 61 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 62 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 63 CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 64 CB_PERF_SEL_CM_CACHE_HIT = 65 CB_PERF_SEL_CM_CACHE_TAG_MISS = 66 CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 67 CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 68 CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 69 CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 70 CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 71 CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 72 CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 73 CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 74 CB_PERF_SEL_CM_CACHE_STALL = 75 CB_PERF_SEL_CM_CACHE_FLUSH = 76 CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 77 CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 78 CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 79 CB_PERF_SEL_FC_CACHE_HIT = 80 CB_PERF_SEL_FC_CACHE_TAG_MISS = 81 CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 82 CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 83 CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 84 CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 85 CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 86 CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 87 CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 88 CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 89 CB_PERF_SEL_FC_CACHE_STALL = 90 CB_PERF_SEL_FC_CACHE_FLUSH = 91 CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 92 CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 93 CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 94 CB_PERF_SEL_CC_CACHE_HIT = 95 CB_PERF_SEL_CC_CACHE_TAG_MISS = 96 CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 97 CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 98 CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 99 CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 100 CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 101 CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 102 CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 103 CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 104 CB_PERF_SEL_CC_CACHE_STALL = 105 CB_PERF_SEL_CC_CACHE_FLUSH = 106 CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 107 CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 108 CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 109 CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 110 CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 111 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 112 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 113 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 114 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 115 CB_PERF_SEL_CM_MC_WRITE_REQUEST = 116 CB_PERF_SEL_FC_MC_WRITE_REQUEST = 117 CB_PERF_SEL_CC_MC_WRITE_REQUEST = 118 CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 119 CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 120 CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 121 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 122 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 123 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 124 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 125 CB_PERF_SEL_CM_MC_READ_REQUEST = 126 CB_PERF_SEL_FC_MC_READ_REQUEST = 127 CB_PERF_SEL_CC_MC_READ_REQUEST = 128 CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 129 CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 130 CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 131 CB_PERF_SEL_CM_TQ_FULL = 132 CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 133 CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 134 CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 135 CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 136 CB_PERF_SEL_FOP_FMASK_RAW_STALL = 137 CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 138 CB_PERF_SEL_CC_SF_FULL = 139 CB_PERF_SEL_CC_RB_FULL = 140 CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 141 CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 142 CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 143 CB_PERF_SEL_EVENT = 144 CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 145 CB_PERF_SEL_EVENT_CONTEXT_DONE = 146 CB_PERF_SEL_EVENT_CACHE_FLUSH = 147 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 148 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 149 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 150 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 151 CB_PERF_SEL_CC_SURFACE_SYNC = 152 CB_PERF_SEL_CMASK_READ_DATA_0xC = 153 CB_PERF_SEL_CMASK_READ_DATA_0xD = 154 CB_PERF_SEL_CMASK_READ_DATA_0xE = 155 CB_PERF_SEL_CMASK_READ_DATA_0xF = 156 CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 157 CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 158 CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 159 CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 160 CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 161 CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 162 CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 163 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 164 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 165 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 166 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 167 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 168 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 169 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 170 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 171 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 172 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 173 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 174 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 175 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 176 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 177 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 178 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 179 CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 180 CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 181 CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 182 CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 183 CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 184 CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 185 CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 186 CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 187 CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 188 CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 189 CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 190 CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 191 CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 192 CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 193 CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 194 CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 195 CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 196 CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 197 CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 198 CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 199 CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 200 CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 201 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 202 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 203 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 204 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 205 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 206 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 207 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 208 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 209 CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 210 CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 211 CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 212 CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 213 CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 214 CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 215 CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 216 CB_PERF_SEL_DRAWN_BUSY = 217 CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 218 CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 219 CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 220 CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 221 CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 222 CB_PERF_SEL_FC_SEQUENCER_CLEAR = 223 CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 224 CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 225 CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 226 CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 227 CB_PERF_SEL_FC_DOC_IS_STALLED = 228 CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 229 CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 230 CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 231 CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 232 CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 233 CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 234 CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 235 CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 236 CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 237 CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 238 CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 239 CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 240 CB_PERF_SEL_FC_DCC_CACHE_HIT = 241 CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 242 CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 243 CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 244 CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 245 CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 246 CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 247 CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 248 CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 249 CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 250 CB_PERF_SEL_FC_DCC_CACHE_STALL = 251 CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 252 CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 253 CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 254 CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 255 CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 256 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 257 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 258 CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 259 CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 260 CB_PERF_SEL_CC_DCC_RDREQ_STALL = 261 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 262 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 263 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 264 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 265 CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 266 CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 267 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 268 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 269 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 270 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 271 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 272 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 273 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 274 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 275 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 276 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 277 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 278 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 279 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 280 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 281 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 282 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 283 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 284 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 285 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 286 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 287 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 288 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 289 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 290 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 291 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 292 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 293 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 294 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 295 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 296 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 297 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 298 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 299 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 300 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 301 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 302 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 303 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 304 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 305 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 306 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 307 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 308 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 309 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 310 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 311 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 312 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 313 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 314 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 315 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 316 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 317 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 318 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 319 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 320 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 321 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 322 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 323 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 324 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 325 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 326 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 327 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 328 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 329 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 330 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 331 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 332 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 333 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 334 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 335 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 336 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 337 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 338 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 339 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 340 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 341 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 342 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 343 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 344 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 345 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 346 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 347 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 348 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 349 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 350 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 351 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 352 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 353 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 354 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 355 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 356 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 357 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 358 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 359 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 360 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 361 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 362 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 363 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 364 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 365 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 366 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 367 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 368 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 369 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 370 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 371 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 372 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 373 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 374 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 375 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 376 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 377 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 378 CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 379 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 380 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 381 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 382 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 383 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 384 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 385 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 386 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 387 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 388 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 389 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 390 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 391 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 392 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 393 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 394 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 395 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 396 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 397 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 398 CB_PERF_SEL_RBP_SPLIT_MICROTILE = 399 CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 400 CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 401 CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 402 CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 403 CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 404 CBPerfSel = ctypes.c_uint32 # enum # values for enumeration 'CBPerfOpFilterSel' CBPerfOpFilterSel__enumvalues = { 0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', 1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', 2: 'CB_PERF_OP_FILTER_SEL_RESOLVE', 3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', 4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', 5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', } CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0 CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1 CB_PERF_OP_FILTER_SEL_RESOLVE = 2 CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3 CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4 CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5 CBPerfOpFilterSel = ctypes.c_uint32 # enum # values for enumeration 'CBPerfClearFilterSel' CBPerfClearFilterSel__enumvalues = { 0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', 1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', } CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0 CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1 CBPerfClearFilterSel = ctypes.c_uint32 # enum # values for enumeration 'TC_OP_MASKS' TC_OP_MASKS__enumvalues = { 8: 'TC_OP_MASK_FLUSH_DENROM', 32: 'TC_OP_MASK_64', 64: 'TC_OP_MASK_NO_RTN', } TC_OP_MASK_FLUSH_DENROM = 8 TC_OP_MASK_64 = 32 TC_OP_MASK_NO_RTN = 64 TC_OP_MASKS = ctypes.c_uint32 # enum # values for enumeration 'TC_OP' TC_OP__enumvalues = { 0: 'TC_OP_READ', 1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 2: 'TC_OP_ATOMIC_FMIN_RTN_32', 3: 'TC_OP_ATOMIC_FMAX_RTN_32', 4: 'TC_OP_RESERVED_FOP_RTN_32_0', 5: 'TC_OP_RESERVED_FOP_RTN_32_1', 6: 'TC_OP_RESERVED_FOP_RTN_32_2', 7: 'TC_OP_ATOMIC_SWAP_RTN_32', 8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32', 9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', 10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', 11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', 12: 'TC_OP_PROBE_FILTER', 13: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', 14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', 15: 'TC_OP_ATOMIC_ADD_RTN_32', 16: 'TC_OP_ATOMIC_SUB_RTN_32', 17: 'TC_OP_ATOMIC_SMIN_RTN_32', 18: 'TC_OP_ATOMIC_UMIN_RTN_32', 19: 'TC_OP_ATOMIC_SMAX_RTN_32', 20: 'TC_OP_ATOMIC_UMAX_RTN_32', 21: 'TC_OP_ATOMIC_AND_RTN_32', 22: 'TC_OP_ATOMIC_OR_RTN_32', 23: 'TC_OP_ATOMIC_XOR_RTN_32', 24: 'TC_OP_ATOMIC_INC_RTN_32', 25: 'TC_OP_ATOMIC_DEC_RTN_32', 26: 'TC_OP_WBINVL1_VOL', 27: 'TC_OP_WBINVL1_SD', 28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', 29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', 30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', 31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', 32: 'TC_OP_WRITE', 33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', 34: 'TC_OP_ATOMIC_FMIN_RTN_64', 35: 'TC_OP_ATOMIC_FMAX_RTN_64', 36: 'TC_OP_RESERVED_FOP_RTN_64_0', 37: 'TC_OP_RESERVED_FOP_RTN_64_1', 38: 'TC_OP_RESERVED_FOP_RTN_64_2', 39: 'TC_OP_ATOMIC_SWAP_RTN_64', 40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64', 41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', 42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', 43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', 44: 'TC_OP_WBINVL2_SD', 45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', 46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', 47: 'TC_OP_ATOMIC_ADD_RTN_64', 48: 'TC_OP_ATOMIC_SUB_RTN_64', 49: 'TC_OP_ATOMIC_SMIN_RTN_64', 50: 'TC_OP_ATOMIC_UMIN_RTN_64', 51: 'TC_OP_ATOMIC_SMAX_RTN_64', 52: 'TC_OP_ATOMIC_UMAX_RTN_64', 53: 'TC_OP_ATOMIC_AND_RTN_64', 54: 'TC_OP_ATOMIC_OR_RTN_64', 55: 'TC_OP_ATOMIC_XOR_RTN_64', 56: 'TC_OP_ATOMIC_INC_RTN_64', 57: 'TC_OP_ATOMIC_DEC_RTN_64', 58: 'TC_OP_WBL2_NC', 59: 'TC_OP_WBL2_WC', 60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', 61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', 62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', 63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 64: 'TC_OP_WBINVL1', 65: 'TC_OP_ATOMIC_FCMPSWAP_32', 66: 'TC_OP_ATOMIC_FMIN_32', 67: 'TC_OP_ATOMIC_FMAX_32', 68: 'TC_OP_RESERVED_FOP_32_0', 69: 'TC_OP_RESERVED_FOP_32_1', 70: 'TC_OP_RESERVED_FOP_32_2', 71: 'TC_OP_ATOMIC_SWAP_32', 72: 'TC_OP_ATOMIC_CMPSWAP_32', 73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', 74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', 75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', 76: 'TC_OP_INV_METADATA', 77: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1', 78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', 79: 'TC_OP_ATOMIC_ADD_32', 80: 'TC_OP_ATOMIC_SUB_32', 81: 'TC_OP_ATOMIC_SMIN_32', 82: 'TC_OP_ATOMIC_UMIN_32', 83: 'TC_OP_ATOMIC_SMAX_32', 84: 'TC_OP_ATOMIC_UMAX_32', 85: 'TC_OP_ATOMIC_AND_32', 86: 'TC_OP_ATOMIC_OR_32', 87: 'TC_OP_ATOMIC_XOR_32', 88: 'TC_OP_ATOMIC_INC_32', 89: 'TC_OP_ATOMIC_DEC_32', 90: 'TC_OP_INVL2_NC', 91: 'TC_OP_NOP_RTN0', 92: 'TC_OP_RESERVED_NON_FLOAT_32_1', 93: 'TC_OP_RESERVED_NON_FLOAT_32_2', 94: 'TC_OP_RESERVED_NON_FLOAT_32_3', 95: 'TC_OP_RESERVED_NON_FLOAT_32_4', 96: 'TC_OP_WBINVL2', 97: 'TC_OP_ATOMIC_FCMPSWAP_64', 98: 'TC_OP_ATOMIC_FMIN_64', 99: 'TC_OP_ATOMIC_FMAX_64', 100: 'TC_OP_RESERVED_FOP_64_0', 101: 'TC_OP_RESERVED_FOP_64_1', 102: 'TC_OP_RESERVED_FOP_64_2', 103: 'TC_OP_ATOMIC_SWAP_64', 104: 'TC_OP_ATOMIC_CMPSWAP_64', 105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', 106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', 107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', 108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', 109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', 110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', 111: 'TC_OP_ATOMIC_ADD_64', 112: 'TC_OP_ATOMIC_SUB_64', 113: 'TC_OP_ATOMIC_SMIN_64', 114: 'TC_OP_ATOMIC_UMIN_64', 115: 'TC_OP_ATOMIC_SMAX_64', 116: 'TC_OP_ATOMIC_UMAX_64', 117: 'TC_OP_ATOMIC_AND_64', 118: 'TC_OP_ATOMIC_OR_64', 119: 'TC_OP_ATOMIC_XOR_64', 120: 'TC_OP_ATOMIC_INC_64', 121: 'TC_OP_ATOMIC_DEC_64', 122: 'TC_OP_WBINVL2_NC', 123: 'TC_OP_NOP_ACK', 124: 'TC_OP_RESERVED_NON_FLOAT_64_1', 125: 'TC_OP_RESERVED_NON_FLOAT_64_2', 126: 'TC_OP_RESERVED_NON_FLOAT_64_3', 127: 'TC_OP_RESERVED_NON_FLOAT_64_4', } TC_OP_READ = 0 TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 TC_OP_ATOMIC_FMIN_RTN_32 = 2 TC_OP_ATOMIC_FMAX_RTN_32 = 3 TC_OP_RESERVED_FOP_RTN_32_0 = 4 TC_OP_RESERVED_FOP_RTN_32_1 = 5 TC_OP_RESERVED_FOP_RTN_32_2 = 6 TC_OP_ATOMIC_SWAP_RTN_32 = 7 TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 TC_OP_PROBE_FILTER = 12 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 13 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 TC_OP_ATOMIC_ADD_RTN_32 = 15 TC_OP_ATOMIC_SUB_RTN_32 = 16 TC_OP_ATOMIC_SMIN_RTN_32 = 17 TC_OP_ATOMIC_UMIN_RTN_32 = 18 TC_OP_ATOMIC_SMAX_RTN_32 = 19 TC_OP_ATOMIC_UMAX_RTN_32 = 20 TC_OP_ATOMIC_AND_RTN_32 = 21 TC_OP_ATOMIC_OR_RTN_32 = 22 TC_OP_ATOMIC_XOR_RTN_32 = 23 TC_OP_ATOMIC_INC_RTN_32 = 24 TC_OP_ATOMIC_DEC_RTN_32 = 25 TC_OP_WBINVL1_VOL = 26 TC_OP_WBINVL1_SD = 27 TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28 TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29 TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30 TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31 TC_OP_WRITE = 32 TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 TC_OP_ATOMIC_FMIN_RTN_64 = 34 TC_OP_ATOMIC_FMAX_RTN_64 = 35 TC_OP_RESERVED_FOP_RTN_64_0 = 36 TC_OP_RESERVED_FOP_RTN_64_1 = 37 TC_OP_RESERVED_FOP_RTN_64_2 = 38 TC_OP_ATOMIC_SWAP_RTN_64 = 39 TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 TC_OP_WBINVL2_SD = 44 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46 TC_OP_ATOMIC_ADD_RTN_64 = 47 TC_OP_ATOMIC_SUB_RTN_64 = 48 TC_OP_ATOMIC_SMIN_RTN_64 = 49 TC_OP_ATOMIC_UMIN_RTN_64 = 50 TC_OP_ATOMIC_SMAX_RTN_64 = 51 TC_OP_ATOMIC_UMAX_RTN_64 = 52 TC_OP_ATOMIC_AND_RTN_64 = 53 TC_OP_ATOMIC_OR_RTN_64 = 54 TC_OP_ATOMIC_XOR_RTN_64 = 55 TC_OP_ATOMIC_INC_RTN_64 = 56 TC_OP_ATOMIC_DEC_RTN_64 = 57 TC_OP_WBL2_NC = 58 TC_OP_WBL2_WC = 59 TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60 TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61 TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62 TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63 TC_OP_WBINVL1 = 64 TC_OP_ATOMIC_FCMPSWAP_32 = 65 TC_OP_ATOMIC_FMIN_32 = 66 TC_OP_ATOMIC_FMAX_32 = 67 TC_OP_RESERVED_FOP_32_0 = 68 TC_OP_RESERVED_FOP_32_1 = 69 TC_OP_RESERVED_FOP_32_2 = 70 TC_OP_ATOMIC_SWAP_32 = 71 TC_OP_ATOMIC_CMPSWAP_32 = 72 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 TC_OP_INV_METADATA = 76 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 77 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78 TC_OP_ATOMIC_ADD_32 = 79 TC_OP_ATOMIC_SUB_32 = 80 TC_OP_ATOMIC_SMIN_32 = 81 TC_OP_ATOMIC_UMIN_32 = 82 TC_OP_ATOMIC_SMAX_32 = 83 TC_OP_ATOMIC_UMAX_32 = 84 TC_OP_ATOMIC_AND_32 = 85 TC_OP_ATOMIC_OR_32 = 86 TC_OP_ATOMIC_XOR_32 = 87 TC_OP_ATOMIC_INC_32 = 88 TC_OP_ATOMIC_DEC_32 = 89 TC_OP_INVL2_NC = 90 TC_OP_NOP_RTN0 = 91 TC_OP_RESERVED_NON_FLOAT_32_1 = 92 TC_OP_RESERVED_NON_FLOAT_32_2 = 93 TC_OP_RESERVED_NON_FLOAT_32_3 = 94 TC_OP_RESERVED_NON_FLOAT_32_4 = 95 TC_OP_WBINVL2 = 96 TC_OP_ATOMIC_FCMPSWAP_64 = 97 TC_OP_ATOMIC_FMIN_64 = 98 TC_OP_ATOMIC_FMAX_64 = 99 TC_OP_RESERVED_FOP_64_0 = 100 TC_OP_RESERVED_FOP_64_1 = 101 TC_OP_RESERVED_FOP_64_2 = 102 TC_OP_ATOMIC_SWAP_64 = 103 TC_OP_ATOMIC_CMPSWAP_64 = 104 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110 TC_OP_ATOMIC_ADD_64 = 111 TC_OP_ATOMIC_SUB_64 = 112 TC_OP_ATOMIC_SMIN_64 = 113 TC_OP_ATOMIC_UMIN_64 = 114 TC_OP_ATOMIC_SMAX_64 = 115 TC_OP_ATOMIC_UMAX_64 = 116 TC_OP_ATOMIC_AND_64 = 117 TC_OP_ATOMIC_OR_64 = 118 TC_OP_ATOMIC_XOR_64 = 119 TC_OP_ATOMIC_INC_64 = 120 TC_OP_ATOMIC_DEC_64 = 121 TC_OP_WBINVL2_NC = 122 TC_OP_NOP_ACK = 123 TC_OP_RESERVED_NON_FLOAT_64_1 = 124 TC_OP_RESERVED_NON_FLOAT_64_2 = 125 TC_OP_RESERVED_NON_FLOAT_64_3 = 126 TC_OP_RESERVED_NON_FLOAT_64_4 = 127 TC_OP = ctypes.c_uint32 # enum # values for enumeration 'TC_CHUB_REQ_CREDITS_ENUM' TC_CHUB_REQ_CREDITS_ENUM__enumvalues = { 16: 'TC_CHUB_REQ_CREDITS', } TC_CHUB_REQ_CREDITS = 16 TC_CHUB_REQ_CREDITS_ENUM = ctypes.c_uint32 # enum # values for enumeration 'CHUB_TC_RET_CREDITS_ENUM' CHUB_TC_RET_CREDITS_ENUM__enumvalues = { 32: 'CHUB_TC_RET_CREDITS', } CHUB_TC_RET_CREDITS = 32 CHUB_TC_RET_CREDITS_ENUM = ctypes.c_uint32 # enum # values for enumeration 'TC_NACKS' TC_NACKS__enumvalues = { 0: 'TC_NACK_NO_FAULT', 1: 'TC_NACK_PAGE_FAULT', 2: 'TC_NACK_PROTECTION_FAULT', 3: 'TC_NACK_DATA_ERROR', } TC_NACK_NO_FAULT = 0 TC_NACK_PAGE_FAULT = 1 TC_NACK_PROTECTION_FAULT = 2 TC_NACK_DATA_ERROR = 3 TC_NACKS = ctypes.c_uint32 # enum # values for enumeration 'TC_EA_CID' TC_EA_CID__enumvalues = { 0: 'TC_EA_CID_RT', 1: 'TC_EA_CID_FMASK', 2: 'TC_EA_CID_DCC', 3: 'TC_EA_CID_TCPMETA', 4: 'TC_EA_CID_Z', 5: 'TC_EA_CID_STENCIL', 6: 'TC_EA_CID_HTILE', 7: 'TC_EA_CID_MISC', 8: 'TC_EA_CID_TCP', 9: 'TC_EA_CID_SQC', 10: 'TC_EA_CID_CPF', 11: 'TC_EA_CID_CPG', 12: 'TC_EA_CID_IA', 13: 'TC_EA_CID_WD', 14: 'TC_EA_CID_PA', 15: 'TC_EA_CID_UTCL2_TPI', } TC_EA_CID_RT = 0 TC_EA_CID_FMASK = 1 TC_EA_CID_DCC = 2 TC_EA_CID_TCPMETA = 3 TC_EA_CID_Z = 4 TC_EA_CID_STENCIL = 5 TC_EA_CID_HTILE = 6 TC_EA_CID_MISC = 7 TC_EA_CID_TCP = 8 TC_EA_CID_SQC = 9 TC_EA_CID_CPF = 10 TC_EA_CID_CPG = 11 TC_EA_CID_IA = 12 TC_EA_CID_WD = 13 TC_EA_CID_PA = 14 TC_EA_CID_UTCL2_TPI = 15 TC_EA_CID = ctypes.c_uint32 # enum # values for enumeration 'SPI_SAMPLE_CNTL' SPI_SAMPLE_CNTL__enumvalues = { 0: 'CENTROIDS_ONLY', 1: 'CENTERS_ONLY', 2: 'CENTROIDS_AND_CENTERS', 3: 'UNDEF', } CENTROIDS_ONLY = 0 CENTERS_ONLY = 1 CENTROIDS_AND_CENTERS = 2 UNDEF = 3 SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum # values for enumeration 'SPI_FOG_MODE' SPI_FOG_MODE__enumvalues = { 0: 'SPI_FOG_NONE', 1: 'SPI_FOG_EXP', 2: 'SPI_FOG_EXP2', 3: 'SPI_FOG_LINEAR', } SPI_FOG_NONE = 0 SPI_FOG_EXP = 1 SPI_FOG_EXP2 = 2 SPI_FOG_LINEAR = 3 SPI_FOG_MODE = ctypes.c_uint32 # enum # values for enumeration 'SPI_PNT_SPRITE_OVERRIDE' SPI_PNT_SPRITE_OVERRIDE__enumvalues = { 0: 'SPI_PNT_SPRITE_SEL_0', 1: 'SPI_PNT_SPRITE_SEL_1', 2: 'SPI_PNT_SPRITE_SEL_S', 3: 'SPI_PNT_SPRITE_SEL_T', 4: 'SPI_PNT_SPRITE_SEL_NONE', } SPI_PNT_SPRITE_SEL_0 = 0 SPI_PNT_SPRITE_SEL_1 = 1 SPI_PNT_SPRITE_SEL_S = 2 SPI_PNT_SPRITE_SEL_T = 3 SPI_PNT_SPRITE_SEL_NONE = 4 SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum # values for enumeration 'SPI_PERFCNT_SEL' SPI_PERFCNT_SEL__enumvalues = { 0: 'SPI_PERF_VS_WINDOW_VALID', 1: 'SPI_PERF_VS_BUSY', 2: 'SPI_PERF_VS_FIRST_WAVE', 3: 'SPI_PERF_VS_LAST_WAVE', 4: 'SPI_PERF_VS_LSHS_DEALLOC', 5: 'SPI_PERF_VS_PC_STALL', 6: 'SPI_PERF_VS_POS0_STALL', 7: 'SPI_PERF_VS_POS1_STALL', 8: 'SPI_PERF_VS_CRAWLER_STALL', 9: 'SPI_PERF_VS_EVENT_WAVE', 10: 'SPI_PERF_VS_WAVE', 11: 'SPI_PERF_VS_PERS_UPD_FULL0', 12: 'SPI_PERF_VS_PERS_UPD_FULL1', 13: 'SPI_PERF_VS_LATE_ALLOC_FULL', 14: 'SPI_PERF_VS_FIRST_SUBGRP', 15: 'SPI_PERF_VS_LAST_SUBGRP', 16: 'SPI_PERF_GS_WINDOW_VALID', 17: 'SPI_PERF_GS_BUSY', 18: 'SPI_PERF_GS_CRAWLER_STALL', 19: 'SPI_PERF_GS_EVENT_WAVE', 20: 'SPI_PERF_GS_WAVE', 21: 'SPI_PERF_GS_PERS_UPD_FULL0', 22: 'SPI_PERF_GS_PERS_UPD_FULL1', 23: 'SPI_PERF_GS_FIRST_SUBGRP', 24: 'SPI_PERF_GS_LAST_SUBGRP', 25: 'SPI_PERF_ES_WINDOW_VALID', 26: 'SPI_PERF_ES_BUSY', 27: 'SPI_PERF_ES_CRAWLER_STALL', 28: 'SPI_PERF_ES_FIRST_WAVE', 29: 'SPI_PERF_ES_LAST_WAVE', 30: 'SPI_PERF_ES_LSHS_DEALLOC', 31: 'SPI_PERF_ES_EVENT_WAVE', 32: 'SPI_PERF_ES_WAVE', 33: 'SPI_PERF_ES_PERS_UPD_FULL0', 34: 'SPI_PERF_ES_PERS_UPD_FULL1', 35: 'SPI_PERF_ES_FIRST_SUBGRP', 36: 'SPI_PERF_ES_LAST_SUBGRP', 37: 'SPI_PERF_HS_WINDOW_VALID', 38: 'SPI_PERF_HS_BUSY', 39: 'SPI_PERF_HS_CRAWLER_STALL', 40: 'SPI_PERF_HS_FIRST_WAVE', 41: 'SPI_PERF_HS_LAST_WAVE', 42: 'SPI_PERF_HS_LSHS_DEALLOC', 43: 'SPI_PERF_HS_EVENT_WAVE', 44: 'SPI_PERF_HS_WAVE', 45: 'SPI_PERF_HS_PERS_UPD_FULL0', 46: 'SPI_PERF_HS_PERS_UPD_FULL1', 47: 'SPI_PERF_LS_WINDOW_VALID', 48: 'SPI_PERF_LS_BUSY', 49: 'SPI_PERF_LS_CRAWLER_STALL', 50: 'SPI_PERF_LS_FIRST_WAVE', 51: 'SPI_PERF_LS_LAST_WAVE', 52: 'SPI_PERF_OFFCHIP_LDS_STALL_LS', 53: 'SPI_PERF_LS_EVENT_WAVE', 54: 'SPI_PERF_LS_WAVE', 55: 'SPI_PERF_LS_PERS_UPD_FULL0', 56: 'SPI_PERF_LS_PERS_UPD_FULL1', 57: 'SPI_PERF_CSG_WINDOW_VALID', 58: 'SPI_PERF_CSG_BUSY', 59: 'SPI_PERF_CSG_NUM_THREADGROUPS', 60: 'SPI_PERF_CSG_CRAWLER_STALL', 61: 'SPI_PERF_CSG_EVENT_WAVE', 62: 'SPI_PERF_CSG_WAVE', 63: 'SPI_PERF_CSN_WINDOW_VALID', 64: 'SPI_PERF_CSN_BUSY', 65: 'SPI_PERF_CSN_NUM_THREADGROUPS', 66: 'SPI_PERF_CSN_CRAWLER_STALL', 67: 'SPI_PERF_CSN_EVENT_WAVE', 68: 'SPI_PERF_CSN_WAVE', 69: 'SPI_PERF_PS_CTL_WINDOW_VALID', 70: 'SPI_PERF_PS_CTL_BUSY', 71: 'SPI_PERF_PS_CTL_ACTIVE', 72: 'SPI_PERF_PS_CTL_DEALLOC_BIN0', 73: 'SPI_PERF_PS_CTL_FPOS_BIN1_STALL', 74: 'SPI_PERF_PS_CTL_EVENT_WAVE', 75: 'SPI_PERF_PS_CTL_WAVE', 76: 'SPI_PERF_PS_CTL_OPT_WAVE', 77: 'SPI_PERF_PS_CTL_PASS_BIN0', 78: 'SPI_PERF_PS_CTL_PASS_BIN1', 79: 'SPI_PERF_PS_CTL_FPOS_BIN2', 80: 'SPI_PERF_PS_CTL_PRIM_BIN0', 81: 'SPI_PERF_PS_CTL_PRIM_BIN1', 82: 'SPI_PERF_PS_CTL_CNF_BIN2', 83: 'SPI_PERF_PS_CTL_CNF_BIN3', 84: 'SPI_PERF_PS_CTL_CRAWLER_STALL', 85: 'SPI_PERF_PS_CTL_LDS_RES_FULL', 86: 'SPI_PERF_PS_PERS_UPD_FULL0', 87: 'SPI_PERF_PS_PERS_UPD_FULL1', 88: 'SPI_PERF_PIX_ALLOC_PEND_CNT', 89: 'SPI_PERF_PIX_ALLOC_SCB_STALL', 90: 'SPI_PERF_PIX_ALLOC_DB0_STALL', 91: 'SPI_PERF_PIX_ALLOC_DB1_STALL', 92: 'SPI_PERF_PIX_ALLOC_DB2_STALL', 93: 'SPI_PERF_PIX_ALLOC_DB3_STALL', 94: 'SPI_PERF_LDS0_PC_VALID', 95: 'SPI_PERF_LDS1_PC_VALID', 96: 'SPI_PERF_RA_PIPE_REQ_BIN2', 97: 'SPI_PERF_RA_TASK_REQ_BIN3', 98: 'SPI_PERF_RA_WR_CTL_FULL', 99: 'SPI_PERF_RA_REQ_NO_ALLOC', 100: 'SPI_PERF_RA_REQ_NO_ALLOC_PS', 101: 'SPI_PERF_RA_REQ_NO_ALLOC_VS', 102: 'SPI_PERF_RA_REQ_NO_ALLOC_GS', 103: 'SPI_PERF_RA_REQ_NO_ALLOC_ES', 104: 'SPI_PERF_RA_REQ_NO_ALLOC_HS', 105: 'SPI_PERF_RA_REQ_NO_ALLOC_LS', 106: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', 107: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', 108: 'SPI_PERF_RA_RES_STALL_PS', 109: 'SPI_PERF_RA_RES_STALL_VS', 110: 'SPI_PERF_RA_RES_STALL_GS', 111: 'SPI_PERF_RA_RES_STALL_ES', 112: 'SPI_PERF_RA_RES_STALL_HS', 113: 'SPI_PERF_RA_RES_STALL_LS', 114: 'SPI_PERF_RA_RES_STALL_CSG', 115: 'SPI_PERF_RA_RES_STALL_CSN', 116: 'SPI_PERF_RA_TMP_STALL_PS', 117: 'SPI_PERF_RA_TMP_STALL_VS', 118: 'SPI_PERF_RA_TMP_STALL_GS', 119: 'SPI_PERF_RA_TMP_STALL_ES', 120: 'SPI_PERF_RA_TMP_STALL_HS', 121: 'SPI_PERF_RA_TMP_STALL_LS', 122: 'SPI_PERF_RA_TMP_STALL_CSG', 123: 'SPI_PERF_RA_TMP_STALL_CSN', 124: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', 125: 'SPI_PERF_RA_WAVE_SIMD_FULL_VS', 126: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', 127: 'SPI_PERF_RA_WAVE_SIMD_FULL_ES', 128: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 129: 'SPI_PERF_RA_WAVE_SIMD_FULL_LS', 130: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', 131: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 132: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', 133: 'SPI_PERF_RA_VGPR_SIMD_FULL_VS', 134: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', 135: 'SPI_PERF_RA_VGPR_SIMD_FULL_ES', 136: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 137: 'SPI_PERF_RA_VGPR_SIMD_FULL_LS', 138: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', 139: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 140: 'SPI_PERF_RA_SGPR_SIMD_FULL_PS', 141: 'SPI_PERF_RA_SGPR_SIMD_FULL_VS', 142: 'SPI_PERF_RA_SGPR_SIMD_FULL_GS', 143: 'SPI_PERF_RA_SGPR_SIMD_FULL_ES', 144: 'SPI_PERF_RA_SGPR_SIMD_FULL_HS', 145: 'SPI_PERF_RA_SGPR_SIMD_FULL_LS', 146: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSG', 147: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSN', 148: 'SPI_PERF_RA_LDS_CU_FULL_PS', 149: 'SPI_PERF_RA_LDS_CU_FULL_LS', 150: 'SPI_PERF_RA_LDS_CU_FULL_ES', 151: 'SPI_PERF_RA_LDS_CU_FULL_CSG', 152: 'SPI_PERF_RA_LDS_CU_FULL_CSN', 153: 'SPI_PERF_RA_BAR_CU_FULL_HS', 154: 'SPI_PERF_RA_BAR_CU_FULL_CSG', 155: 'SPI_PERF_RA_BAR_CU_FULL_CSN', 156: 'SPI_PERF_RA_BULKY_CU_FULL_CSG', 157: 'SPI_PERF_RA_BULKY_CU_FULL_CSN', 158: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 159: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', 160: 'SPI_PERF_RA_WVLIM_STALL_PS', 161: 'SPI_PERF_RA_WVLIM_STALL_VS', 162: 'SPI_PERF_RA_WVLIM_STALL_GS', 163: 'SPI_PERF_RA_WVLIM_STALL_ES', 164: 'SPI_PERF_RA_WVLIM_STALL_HS', 165: 'SPI_PERF_RA_WVLIM_STALL_LS', 166: 'SPI_PERF_RA_WVLIM_STALL_CSG', 167: 'SPI_PERF_RA_WVLIM_STALL_CSN', 168: 'SPI_PERF_RA_PS_LOCK_NA', 169: 'SPI_PERF_RA_VS_LOCK', 170: 'SPI_PERF_RA_GS_LOCK', 171: 'SPI_PERF_RA_ES_LOCK', 172: 'SPI_PERF_RA_HS_LOCK', 173: 'SPI_PERF_RA_LS_LOCK', 174: 'SPI_PERF_RA_CSG_LOCK', 175: 'SPI_PERF_RA_CSN_LOCK', 176: 'SPI_PERF_RA_RSV_UPD', 177: 'SPI_PERF_EXP_ARB_COL_CNT', 178: 'SPI_PERF_EXP_ARB_PAR_CNT', 179: 'SPI_PERF_EXP_ARB_POS_CNT', 180: 'SPI_PERF_EXP_ARB_GDS_CNT', 181: 'SPI_PERF_CLKGATE_BUSY_STALL', 182: 'SPI_PERF_CLKGATE_ACTIVE_STALL', 183: 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON', 184: 'SPI_PERF_CLKGATE_CGTT_DYN_ON', 185: 'SPI_PERF_CLKGATE_CGTT_REG_ON', 186: 'SPI_PERF_NUM_VS_POS_EXPORTS', 187: 'SPI_PERF_NUM_VS_PARAM_EXPORTS', 188: 'SPI_PERF_NUM_PS_COL_EXPORTS', 189: 'SPI_PERF_ES_GRP_FIFO_FULL', 190: 'SPI_PERF_GS_GRP_FIFO_FULL', 191: 'SPI_PERF_HS_GRP_FIFO_FULL', 192: 'SPI_PERF_LS_GRP_FIFO_FULL', 193: 'SPI_PERF_VS_ALLOC_CNT', 194: 'SPI_PERF_VS_LATE_ALLOC_ACCUM', 195: 'SPI_PERF_PC_ALLOC_CNT', 196: 'SPI_PERF_PC_ALLOC_ACCUM', } SPI_PERF_VS_WINDOW_VALID = 0 SPI_PERF_VS_BUSY = 1 SPI_PERF_VS_FIRST_WAVE = 2 SPI_PERF_VS_LAST_WAVE = 3 SPI_PERF_VS_LSHS_DEALLOC = 4 SPI_PERF_VS_PC_STALL = 5 SPI_PERF_VS_POS0_STALL = 6 SPI_PERF_VS_POS1_STALL = 7 SPI_PERF_VS_CRAWLER_STALL = 8 SPI_PERF_VS_EVENT_WAVE = 9 SPI_PERF_VS_WAVE = 10 SPI_PERF_VS_PERS_UPD_FULL0 = 11 SPI_PERF_VS_PERS_UPD_FULL1 = 12 SPI_PERF_VS_LATE_ALLOC_FULL = 13 SPI_PERF_VS_FIRST_SUBGRP = 14 SPI_PERF_VS_LAST_SUBGRP = 15 SPI_PERF_GS_WINDOW_VALID = 16 SPI_PERF_GS_BUSY = 17 SPI_PERF_GS_CRAWLER_STALL = 18 SPI_PERF_GS_EVENT_WAVE = 19 SPI_PERF_GS_WAVE = 20 SPI_PERF_GS_PERS_UPD_FULL0 = 21 SPI_PERF_GS_PERS_UPD_FULL1 = 22 SPI_PERF_GS_FIRST_SUBGRP = 23 SPI_PERF_GS_LAST_SUBGRP = 24 SPI_PERF_ES_WINDOW_VALID = 25 SPI_PERF_ES_BUSY = 26 SPI_PERF_ES_CRAWLER_STALL = 27 SPI_PERF_ES_FIRST_WAVE = 28 SPI_PERF_ES_LAST_WAVE = 29 SPI_PERF_ES_LSHS_DEALLOC = 30 SPI_PERF_ES_EVENT_WAVE = 31 SPI_PERF_ES_WAVE = 32 SPI_PERF_ES_PERS_UPD_FULL0 = 33 SPI_PERF_ES_PERS_UPD_FULL1 = 34 SPI_PERF_ES_FIRST_SUBGRP = 35 SPI_PERF_ES_LAST_SUBGRP = 36 SPI_PERF_HS_WINDOW_VALID = 37 SPI_PERF_HS_BUSY = 38 SPI_PERF_HS_CRAWLER_STALL = 39 SPI_PERF_HS_FIRST_WAVE = 40 SPI_PERF_HS_LAST_WAVE = 41 SPI_PERF_HS_LSHS_DEALLOC = 42 SPI_PERF_HS_EVENT_WAVE = 43 SPI_PERF_HS_WAVE = 44 SPI_PERF_HS_PERS_UPD_FULL0 = 45 SPI_PERF_HS_PERS_UPD_FULL1 = 46 SPI_PERF_LS_WINDOW_VALID = 47 SPI_PERF_LS_BUSY = 48 SPI_PERF_LS_CRAWLER_STALL = 49 SPI_PERF_LS_FIRST_WAVE = 50 SPI_PERF_LS_LAST_WAVE = 51 SPI_PERF_OFFCHIP_LDS_STALL_LS = 52 SPI_PERF_LS_EVENT_WAVE = 53 SPI_PERF_LS_WAVE = 54 SPI_PERF_LS_PERS_UPD_FULL0 = 55 SPI_PERF_LS_PERS_UPD_FULL1 = 56 SPI_PERF_CSG_WINDOW_VALID = 57 SPI_PERF_CSG_BUSY = 58 SPI_PERF_CSG_NUM_THREADGROUPS = 59 SPI_PERF_CSG_CRAWLER_STALL = 60 SPI_PERF_CSG_EVENT_WAVE = 61 SPI_PERF_CSG_WAVE = 62 SPI_PERF_CSN_WINDOW_VALID = 63 SPI_PERF_CSN_BUSY = 64 SPI_PERF_CSN_NUM_THREADGROUPS = 65 SPI_PERF_CSN_CRAWLER_STALL = 66 SPI_PERF_CSN_EVENT_WAVE = 67 SPI_PERF_CSN_WAVE = 68 SPI_PERF_PS_CTL_WINDOW_VALID = 69 SPI_PERF_PS_CTL_BUSY = 70 SPI_PERF_PS_CTL_ACTIVE = 71 SPI_PERF_PS_CTL_DEALLOC_BIN0 = 72 SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 73 SPI_PERF_PS_CTL_EVENT_WAVE = 74 SPI_PERF_PS_CTL_WAVE = 75 SPI_PERF_PS_CTL_OPT_WAVE = 76 SPI_PERF_PS_CTL_PASS_BIN0 = 77 SPI_PERF_PS_CTL_PASS_BIN1 = 78 SPI_PERF_PS_CTL_FPOS_BIN2 = 79 SPI_PERF_PS_CTL_PRIM_BIN0 = 80 SPI_PERF_PS_CTL_PRIM_BIN1 = 81 SPI_PERF_PS_CTL_CNF_BIN2 = 82 SPI_PERF_PS_CTL_CNF_BIN3 = 83 SPI_PERF_PS_CTL_CRAWLER_STALL = 84 SPI_PERF_PS_CTL_LDS_RES_FULL = 85 SPI_PERF_PS_PERS_UPD_FULL0 = 86 SPI_PERF_PS_PERS_UPD_FULL1 = 87 SPI_PERF_PIX_ALLOC_PEND_CNT = 88 SPI_PERF_PIX_ALLOC_SCB_STALL = 89 SPI_PERF_PIX_ALLOC_DB0_STALL = 90 SPI_PERF_PIX_ALLOC_DB1_STALL = 91 SPI_PERF_PIX_ALLOC_DB2_STALL = 92 SPI_PERF_PIX_ALLOC_DB3_STALL = 93 SPI_PERF_LDS0_PC_VALID = 94 SPI_PERF_LDS1_PC_VALID = 95 SPI_PERF_RA_PIPE_REQ_BIN2 = 96 SPI_PERF_RA_TASK_REQ_BIN3 = 97 SPI_PERF_RA_WR_CTL_FULL = 98 SPI_PERF_RA_REQ_NO_ALLOC = 99 SPI_PERF_RA_REQ_NO_ALLOC_PS = 100 SPI_PERF_RA_REQ_NO_ALLOC_VS = 101 SPI_PERF_RA_REQ_NO_ALLOC_GS = 102 SPI_PERF_RA_REQ_NO_ALLOC_ES = 103 SPI_PERF_RA_REQ_NO_ALLOC_HS = 104 SPI_PERF_RA_REQ_NO_ALLOC_LS = 105 SPI_PERF_RA_REQ_NO_ALLOC_CSG = 106 SPI_PERF_RA_REQ_NO_ALLOC_CSN = 107 SPI_PERF_RA_RES_STALL_PS = 108 SPI_PERF_RA_RES_STALL_VS = 109 SPI_PERF_RA_RES_STALL_GS = 110 SPI_PERF_RA_RES_STALL_ES = 111 SPI_PERF_RA_RES_STALL_HS = 112 SPI_PERF_RA_RES_STALL_LS = 113 SPI_PERF_RA_RES_STALL_CSG = 114 SPI_PERF_RA_RES_STALL_CSN = 115 SPI_PERF_RA_TMP_STALL_PS = 116 SPI_PERF_RA_TMP_STALL_VS = 117 SPI_PERF_RA_TMP_STALL_GS = 118 SPI_PERF_RA_TMP_STALL_ES = 119 SPI_PERF_RA_TMP_STALL_HS = 120 SPI_PERF_RA_TMP_STALL_LS = 121 SPI_PERF_RA_TMP_STALL_CSG = 122 SPI_PERF_RA_TMP_STALL_CSN = 123 SPI_PERF_RA_WAVE_SIMD_FULL_PS = 124 SPI_PERF_RA_WAVE_SIMD_FULL_VS = 125 SPI_PERF_RA_WAVE_SIMD_FULL_GS = 126 SPI_PERF_RA_WAVE_SIMD_FULL_ES = 127 SPI_PERF_RA_WAVE_SIMD_FULL_HS = 128 SPI_PERF_RA_WAVE_SIMD_FULL_LS = 129 SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 130 SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 131 SPI_PERF_RA_VGPR_SIMD_FULL_PS = 132 SPI_PERF_RA_VGPR_SIMD_FULL_VS = 133 SPI_PERF_RA_VGPR_SIMD_FULL_GS = 134 SPI_PERF_RA_VGPR_SIMD_FULL_ES = 135 SPI_PERF_RA_VGPR_SIMD_FULL_HS = 136 SPI_PERF_RA_VGPR_SIMD_FULL_LS = 137 SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 138 SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 139 SPI_PERF_RA_SGPR_SIMD_FULL_PS = 140 SPI_PERF_RA_SGPR_SIMD_FULL_VS = 141 SPI_PERF_RA_SGPR_SIMD_FULL_GS = 142 SPI_PERF_RA_SGPR_SIMD_FULL_ES = 143 SPI_PERF_RA_SGPR_SIMD_FULL_HS = 144 SPI_PERF_RA_SGPR_SIMD_FULL_LS = 145 SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 146 SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 147 SPI_PERF_RA_LDS_CU_FULL_PS = 148 SPI_PERF_RA_LDS_CU_FULL_LS = 149 SPI_PERF_RA_LDS_CU_FULL_ES = 150 SPI_PERF_RA_LDS_CU_FULL_CSG = 151 SPI_PERF_RA_LDS_CU_FULL_CSN = 152 SPI_PERF_RA_BAR_CU_FULL_HS = 153 SPI_PERF_RA_BAR_CU_FULL_CSG = 154 SPI_PERF_RA_BAR_CU_FULL_CSN = 155 SPI_PERF_RA_BULKY_CU_FULL_CSG = 156 SPI_PERF_RA_BULKY_CU_FULL_CSN = 157 SPI_PERF_RA_TGLIM_CU_FULL_CSG = 158 SPI_PERF_RA_TGLIM_CU_FULL_CSN = 159 SPI_PERF_RA_WVLIM_STALL_PS = 160 SPI_PERF_RA_WVLIM_STALL_VS = 161 SPI_PERF_RA_WVLIM_STALL_GS = 162 SPI_PERF_RA_WVLIM_STALL_ES = 163 SPI_PERF_RA_WVLIM_STALL_HS = 164 SPI_PERF_RA_WVLIM_STALL_LS = 165 SPI_PERF_RA_WVLIM_STALL_CSG = 166 SPI_PERF_RA_WVLIM_STALL_CSN = 167 SPI_PERF_RA_PS_LOCK_NA = 168 SPI_PERF_RA_VS_LOCK = 169 SPI_PERF_RA_GS_LOCK = 170 SPI_PERF_RA_ES_LOCK = 171 SPI_PERF_RA_HS_LOCK = 172 SPI_PERF_RA_LS_LOCK = 173 SPI_PERF_RA_CSG_LOCK = 174 SPI_PERF_RA_CSN_LOCK = 175 SPI_PERF_RA_RSV_UPD = 176 SPI_PERF_EXP_ARB_COL_CNT = 177 SPI_PERF_EXP_ARB_PAR_CNT = 178 SPI_PERF_EXP_ARB_POS_CNT = 179 SPI_PERF_EXP_ARB_GDS_CNT = 180 SPI_PERF_CLKGATE_BUSY_STALL = 181 SPI_PERF_CLKGATE_ACTIVE_STALL = 182 SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 183 SPI_PERF_CLKGATE_CGTT_DYN_ON = 184 SPI_PERF_CLKGATE_CGTT_REG_ON = 185 SPI_PERF_NUM_VS_POS_EXPORTS = 186 SPI_PERF_NUM_VS_PARAM_EXPORTS = 187 SPI_PERF_NUM_PS_COL_EXPORTS = 188 SPI_PERF_ES_GRP_FIFO_FULL = 189 SPI_PERF_GS_GRP_FIFO_FULL = 190 SPI_PERF_HS_GRP_FIFO_FULL = 191 SPI_PERF_LS_GRP_FIFO_FULL = 192 SPI_PERF_VS_ALLOC_CNT = 193 SPI_PERF_VS_LATE_ALLOC_ACCUM = 194 SPI_PERF_PC_ALLOC_CNT = 195 SPI_PERF_PC_ALLOC_ACCUM = 196 SPI_PERFCNT_SEL = ctypes.c_uint32 # enum # values for enumeration 'SPI_SHADER_FORMAT' SPI_SHADER_FORMAT__enumvalues = { 0: 'SPI_SHADER_NONE', 1: 'SPI_SHADER_1COMP', 2: 'SPI_SHADER_2COMP', 3: 'SPI_SHADER_4COMPRESS', 4: 'SPI_SHADER_4COMP', } SPI_SHADER_NONE = 0 SPI_SHADER_1COMP = 1 SPI_SHADER_2COMP = 2 SPI_SHADER_4COMPRESS = 3 SPI_SHADER_4COMP = 4 SPI_SHADER_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'SPI_SHADER_EX_FORMAT' SPI_SHADER_EX_FORMAT__enumvalues = { 0: 'SPI_SHADER_ZERO', 1: 'SPI_SHADER_32_R', 2: 'SPI_SHADER_32_GR', 3: 'SPI_SHADER_32_AR', 4: 'SPI_SHADER_FP16_ABGR', 5: 'SPI_SHADER_UNORM16_ABGR', 6: 'SPI_SHADER_SNORM16_ABGR', 7: 'SPI_SHADER_UINT16_ABGR', 8: 'SPI_SHADER_SINT16_ABGR', 9: 'SPI_SHADER_32_ABGR', } SPI_SHADER_ZERO = 0 SPI_SHADER_32_R = 1 SPI_SHADER_32_GR = 2 SPI_SHADER_32_AR = 3 SPI_SHADER_FP16_ABGR = 4 SPI_SHADER_UNORM16_ABGR = 5 SPI_SHADER_SNORM16_ABGR = 6 SPI_SHADER_UINT16_ABGR = 7 SPI_SHADER_SINT16_ABGR = 8 SPI_SHADER_32_ABGR = 9 SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'CLKGATE_SM_MODE' CLKGATE_SM_MODE__enumvalues = { 0: 'ON_SEQ', 1: 'OFF_SEQ', 2: 'PROG_SEQ', 3: 'READ_SEQ', 4: 'SM_MODE_RESERVED', } ON_SEQ = 0 OFF_SEQ = 1 PROG_SEQ = 2 READ_SEQ = 3 SM_MODE_RESERVED = 4 CLKGATE_SM_MODE = ctypes.c_uint32 # enum # values for enumeration 'CLKGATE_BASE_MODE' CLKGATE_BASE_MODE__enumvalues = { 0: 'MULT_8', 1: 'MULT_16', } MULT_8 = 0 MULT_16 = 1 CLKGATE_BASE_MODE = ctypes.c_uint32 # enum # values for enumeration 'SQ_TEX_CLAMP' SQ_TEX_CLAMP__enumvalues = { 0: 'SQ_TEX_WRAP', 1: 'SQ_TEX_MIRROR', 2: 'SQ_TEX_CLAMP_LAST_TEXEL', 3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', 4: 'SQ_TEX_CLAMP_HALF_BORDER', 5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 6: 'SQ_TEX_CLAMP_BORDER', 7: 'SQ_TEX_MIRROR_ONCE_BORDER', } SQ_TEX_WRAP = 0 SQ_TEX_MIRROR = 1 SQ_TEX_CLAMP_LAST_TEXEL = 2 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3 SQ_TEX_CLAMP_HALF_BORDER = 4 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5 SQ_TEX_CLAMP_BORDER = 6 SQ_TEX_MIRROR_ONCE_BORDER = 7 SQ_TEX_CLAMP = ctypes.c_uint32 # enum # values for enumeration 'SQ_TEX_XY_FILTER' SQ_TEX_XY_FILTER__enumvalues = { 0: 'SQ_TEX_XY_FILTER_POINT', 1: 'SQ_TEX_XY_FILTER_BILINEAR', 2: 'SQ_TEX_XY_FILTER_ANISO_POINT', 3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', } SQ_TEX_XY_FILTER_POINT = 0 SQ_TEX_XY_FILTER_BILINEAR = 1 SQ_TEX_XY_FILTER_ANISO_POINT = 2 SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3 SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum # values for enumeration 'SQ_TEX_Z_FILTER' SQ_TEX_Z_FILTER__enumvalues = { 0: 'SQ_TEX_Z_FILTER_NONE', 1: 'SQ_TEX_Z_FILTER_POINT', 2: 'SQ_TEX_Z_FILTER_LINEAR', } SQ_TEX_Z_FILTER_NONE = 0 SQ_TEX_Z_FILTER_POINT = 1 SQ_TEX_Z_FILTER_LINEAR = 2 SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum # values for enumeration 'SQ_TEX_MIP_FILTER' SQ_TEX_MIP_FILTER__enumvalues = { 0: 'SQ_TEX_MIP_FILTER_NONE', 1: 'SQ_TEX_MIP_FILTER_POINT', 2: 'SQ_TEX_MIP_FILTER_LINEAR', 3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', } SQ_TEX_MIP_FILTER_NONE = 0 SQ_TEX_MIP_FILTER_POINT = 1 SQ_TEX_MIP_FILTER_LINEAR = 2 SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3 SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum # values for enumeration 'SQ_TEX_ANISO_RATIO' SQ_TEX_ANISO_RATIO__enumvalues = { 0: 'SQ_TEX_ANISO_RATIO_1', 1: 'SQ_TEX_ANISO_RATIO_2', 2: 'SQ_TEX_ANISO_RATIO_4', 3: 'SQ_TEX_ANISO_RATIO_8', 4: 'SQ_TEX_ANISO_RATIO_16', } SQ_TEX_ANISO_RATIO_1 = 0 SQ_TEX_ANISO_RATIO_2 = 1 SQ_TEX_ANISO_RATIO_4 = 2 SQ_TEX_ANISO_RATIO_8 = 3 SQ_TEX_ANISO_RATIO_16 = 4 SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum # values for enumeration 'SQ_TEX_DEPTH_COMPARE' SQ_TEX_DEPTH_COMPARE__enumvalues = { 0: 'SQ_TEX_DEPTH_COMPARE_NEVER', 1: 'SQ_TEX_DEPTH_COMPARE_LESS', 2: 'SQ_TEX_DEPTH_COMPARE_EQUAL', 3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 4: 'SQ_TEX_DEPTH_COMPARE_GREATER', 5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS', } SQ_TEX_DEPTH_COMPARE_NEVER = 0 SQ_TEX_DEPTH_COMPARE_LESS = 1 SQ_TEX_DEPTH_COMPARE_EQUAL = 2 SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3 SQ_TEX_DEPTH_COMPARE_GREATER = 4 SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5 SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6 SQ_TEX_DEPTH_COMPARE_ALWAYS = 7 SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum # values for enumeration 'SQ_TEX_BORDER_COLOR' SQ_TEX_BORDER_COLOR__enumvalues = { 0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', 1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', 2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', 3: 'SQ_TEX_BORDER_COLOR_REGISTER', } SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0 SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2 SQ_TEX_BORDER_COLOR_REGISTER = 3 SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum # values for enumeration 'SQ_RSRC_BUF_TYPE' SQ_RSRC_BUF_TYPE__enumvalues = { 0: 'SQ_RSRC_BUF', 1: 'SQ_RSRC_BUF_RSVD_1', 2: 'SQ_RSRC_BUF_RSVD_2', 3: 'SQ_RSRC_BUF_RSVD_3', } SQ_RSRC_BUF = 0 SQ_RSRC_BUF_RSVD_1 = 1 SQ_RSRC_BUF_RSVD_2 = 2 SQ_RSRC_BUF_RSVD_3 = 3 SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum # values for enumeration 'SQ_RSRC_IMG_TYPE' SQ_RSRC_IMG_TYPE__enumvalues = { 0: 'SQ_RSRC_IMG_RSVD_0', 1: 'SQ_RSRC_IMG_RSVD_1', 2: 'SQ_RSRC_IMG_RSVD_2', 3: 'SQ_RSRC_IMG_RSVD_3', 4: 'SQ_RSRC_IMG_RSVD_4', 5: 'SQ_RSRC_IMG_RSVD_5', 6: 'SQ_RSRC_IMG_RSVD_6', 7: 'SQ_RSRC_IMG_RSVD_7', 8: 'SQ_RSRC_IMG_1D', 9: 'SQ_RSRC_IMG_2D', 10: 'SQ_RSRC_IMG_3D', 11: 'SQ_RSRC_IMG_CUBE', 12: 'SQ_RSRC_IMG_1D_ARRAY', 13: 'SQ_RSRC_IMG_2D_ARRAY', 14: 'SQ_RSRC_IMG_2D_MSAA', 15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY', } SQ_RSRC_IMG_RSVD_0 = 0 SQ_RSRC_IMG_RSVD_1 = 1 SQ_RSRC_IMG_RSVD_2 = 2 SQ_RSRC_IMG_RSVD_3 = 3 SQ_RSRC_IMG_RSVD_4 = 4 SQ_RSRC_IMG_RSVD_5 = 5 SQ_RSRC_IMG_RSVD_6 = 6 SQ_RSRC_IMG_RSVD_7 = 7 SQ_RSRC_IMG_1D = 8 SQ_RSRC_IMG_2D = 9 SQ_RSRC_IMG_3D = 10 SQ_RSRC_IMG_CUBE = 11 SQ_RSRC_IMG_1D_ARRAY = 12 SQ_RSRC_IMG_2D_ARRAY = 13 SQ_RSRC_IMG_2D_MSAA = 14 SQ_RSRC_IMG_2D_MSAA_ARRAY = 15 SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum # values for enumeration 'SQ_RSRC_FLAT_TYPE' SQ_RSRC_FLAT_TYPE__enumvalues = { 0: 'SQ_RSRC_FLAT_RSVD_0', 1: 'SQ_RSRC_FLAT', 2: 'SQ_RSRC_FLAT_RSVD_2', 3: 'SQ_RSRC_FLAT_RSVD_3', } SQ_RSRC_FLAT_RSVD_0 = 0 SQ_RSRC_FLAT = 1 SQ_RSRC_FLAT_RSVD_2 = 2 SQ_RSRC_FLAT_RSVD_3 = 3 SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'SQ_IMG_FILTER_TYPE' SQ_IMG_FILTER_TYPE__enumvalues = { 0: 'SQ_IMG_FILTER_MODE_BLEND', 1: 'SQ_IMG_FILTER_MODE_MIN', 2: 'SQ_IMG_FILTER_MODE_MAX', } SQ_IMG_FILTER_MODE_BLEND = 0 SQ_IMG_FILTER_MODE_MIN = 1 SQ_IMG_FILTER_MODE_MAX = 2 SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum # values for enumeration 'SQ_SEL_XYZW01' SQ_SEL_XYZW01__enumvalues = { 0: 'SQ_SEL_0', 1: 'SQ_SEL_1', 2: 'SQ_SEL_RESERVED_0', 3: 'SQ_SEL_RESERVED_1', 4: 'SQ_SEL_X', 5: 'SQ_SEL_Y', 6: 'SQ_SEL_Z', 7: 'SQ_SEL_W', } SQ_SEL_0 = 0 SQ_SEL_1 = 1 SQ_SEL_RESERVED_0 = 2 SQ_SEL_RESERVED_1 = 3 SQ_SEL_X = 4 SQ_SEL_Y = 5 SQ_SEL_Z = 6 SQ_SEL_W = 7 SQ_SEL_XYZW01 = ctypes.c_uint32 # enum # values for enumeration 'SQ_WAVE_TYPE' SQ_WAVE_TYPE__enumvalues = { 0: 'SQ_WAVE_TYPE_PS', 1: 'SQ_WAVE_TYPE_VS', 2: 'SQ_WAVE_TYPE_GS', 3: 'SQ_WAVE_TYPE_ES', 4: 'SQ_WAVE_TYPE_HS', 5: 'SQ_WAVE_TYPE_LS', 6: 'SQ_WAVE_TYPE_CS', 7: 'SQ_WAVE_TYPE_PS1', } SQ_WAVE_TYPE_PS = 0 SQ_WAVE_TYPE_VS = 1 SQ_WAVE_TYPE_GS = 2 SQ_WAVE_TYPE_ES = 3 SQ_WAVE_TYPE_HS = 4 SQ_WAVE_TYPE_LS = 5 SQ_WAVE_TYPE_CS = 6 SQ_WAVE_TYPE_PS1 = 7 SQ_WAVE_TYPE = ctypes.c_uint32 # enum # values for enumeration 'SQ_THREAD_TRACE_TOKEN_TYPE' SQ_THREAD_TRACE_TOKEN_TYPE__enumvalues = { 0: 'SQ_THREAD_TRACE_TOKEN_MISC', 1: 'SQ_THREAD_TRACE_TOKEN_TIMESTAMP', 2: 'SQ_THREAD_TRACE_TOKEN_REG', 3: 'SQ_THREAD_TRACE_TOKEN_WAVE_START', 4: 'SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC', 5: 'SQ_THREAD_TRACE_TOKEN_REG_CSPRIV', 6: 'SQ_THREAD_TRACE_TOKEN_WAVE_END', 7: 'SQ_THREAD_TRACE_TOKEN_EVENT', 8: 'SQ_THREAD_TRACE_TOKEN_EVENT_CS', 9: 'SQ_THREAD_TRACE_TOKEN_EVENT_GFX1', 10: 'SQ_THREAD_TRACE_TOKEN_INST', 11: 'SQ_THREAD_TRACE_TOKEN_INST_PC', 12: 'SQ_THREAD_TRACE_TOKEN_INST_USERDATA', 13: 'SQ_THREAD_TRACE_TOKEN_ISSUE', 14: 'SQ_THREAD_TRACE_TOKEN_PERF', 15: 'SQ_THREAD_TRACE_TOKEN_REG_CS', } SQ_THREAD_TRACE_TOKEN_MISC = 0 SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 1 SQ_THREAD_TRACE_TOKEN_REG = 2 SQ_THREAD_TRACE_TOKEN_WAVE_START = 3 SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 4 SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 5 SQ_THREAD_TRACE_TOKEN_WAVE_END = 6 SQ_THREAD_TRACE_TOKEN_EVENT = 7 SQ_THREAD_TRACE_TOKEN_EVENT_CS = 8 SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 9 SQ_THREAD_TRACE_TOKEN_INST = 10 SQ_THREAD_TRACE_TOKEN_INST_PC = 11 SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 12 SQ_THREAD_TRACE_TOKEN_ISSUE = 13 SQ_THREAD_TRACE_TOKEN_PERF = 14 SQ_THREAD_TRACE_TOKEN_REG_CS = 15 SQ_THREAD_TRACE_TOKEN_TYPE = ctypes.c_uint32 # enum # values for enumeration 'SQ_THREAD_TRACE_MISC_TOKEN_TYPE' SQ_THREAD_TRACE_MISC_TOKEN_TYPE__enumvalues = { 0: 'SQ_THREAD_TRACE_MISC_TOKEN_TIME', 1: 'SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET', 2: 'SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST', 3: 'SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC', 4: 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN', 5: 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END', 6: 'SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX', 7: 'SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN', } SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0 SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 1 SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 2 SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 3 SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 4 SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 5 SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 6 SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 7 SQ_THREAD_TRACE_MISC_TOKEN_TYPE = ctypes.c_uint32 # enum # values for enumeration 'SQ_THREAD_TRACE_INST_TYPE' SQ_THREAD_TRACE_INST_TYPE__enumvalues = { 0: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD', 1: 'SQ_THREAD_TRACE_INST_TYPE_SALU_32', 2: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD', 3: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR', 4: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR', 5: 'SQ_THREAD_TRACE_INST_TYPE_VALU_32', 6: 'SQ_THREAD_TRACE_INST_TYPE_LDS', 7: 'SQ_THREAD_TRACE_INST_TYPE_PC', 8: 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS', 9: 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX', 10: 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL', 11: 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS', 12: 'SQ_THREAD_TRACE_INST_TYPE_JUMP', 13: 'SQ_THREAD_TRACE_INST_TYPE_NEXT', 14: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD', 15: 'SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG', 16: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR', 17: 'SQ_THREAD_TRACE_INST_TYPE_SALU_64', 18: 'SQ_THREAD_TRACE_INST_TYPE_VALU_64', 19: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY', 20: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY', 21: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY', 22: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY', 23: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY', 24: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY', 25: 'SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT', } SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0 SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 1 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 2 SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 3 SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 4 SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 5 SQ_THREAD_TRACE_INST_TYPE_LDS = 6 SQ_THREAD_TRACE_INST_TYPE_PC = 7 SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 8 SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 9 SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 10 SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 11 SQ_THREAD_TRACE_INST_TYPE_JUMP = 12 SQ_THREAD_TRACE_INST_TYPE_NEXT = 13 SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 14 SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 15 SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 16 SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 17 SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 18 SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 19 SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 20 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 21 SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 22 SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 23 SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 24 SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT = 25 SQ_THREAD_TRACE_INST_TYPE = ctypes.c_uint32 # enum # values for enumeration 'SQ_THREAD_TRACE_REG_TYPE' SQ_THREAD_TRACE_REG_TYPE__enumvalues = { 0: 'SQ_THREAD_TRACE_REG_TYPE_EVENT', 1: 'SQ_THREAD_TRACE_REG_TYPE_DRAW', 2: 'SQ_THREAD_TRACE_REG_TYPE_DISPATCH', 3: 'SQ_THREAD_TRACE_REG_TYPE_USERDATA', 4: 'SQ_THREAD_TRACE_REG_TYPE_MARKER', 5: 'SQ_THREAD_TRACE_REG_TYPE_GFXDEC', 6: 'SQ_THREAD_TRACE_REG_TYPE_SHDEC', 7: 'SQ_THREAD_TRACE_REG_TYPE_OTHER', } SQ_THREAD_TRACE_REG_TYPE_EVENT = 0 SQ_THREAD_TRACE_REG_TYPE_DRAW = 1 SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 2 SQ_THREAD_TRACE_REG_TYPE_USERDATA = 3 SQ_THREAD_TRACE_REG_TYPE_MARKER = 4 SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 5 SQ_THREAD_TRACE_REG_TYPE_SHDEC = 6 SQ_THREAD_TRACE_REG_TYPE_OTHER = 7 SQ_THREAD_TRACE_REG_TYPE = ctypes.c_uint32 # enum # values for enumeration 'SQ_THREAD_TRACE_REG_OP' SQ_THREAD_TRACE_REG_OP__enumvalues = { 0: 'SQ_THREAD_TRACE_REG_OP_READ', 1: 'SQ_THREAD_TRACE_REG_OP_WRITE', } SQ_THREAD_TRACE_REG_OP_READ = 0 SQ_THREAD_TRACE_REG_OP_WRITE = 1 SQ_THREAD_TRACE_REG_OP = ctypes.c_uint32 # enum # values for enumeration 'SQ_THREAD_TRACE_MODE_SEL' SQ_THREAD_TRACE_MODE_SEL__enumvalues = { 0: 'SQ_THREAD_TRACE_MODE_OFF', 1: 'SQ_THREAD_TRACE_MODE_ON', } SQ_THREAD_TRACE_MODE_OFF = 0 SQ_THREAD_TRACE_MODE_ON = 1 SQ_THREAD_TRACE_MODE_SEL = ctypes.c_uint32 # enum # values for enumeration 'SQ_THREAD_TRACE_CAPTURE_MODE' SQ_THREAD_TRACE_CAPTURE_MODE__enumvalues = { 0: 'SQ_THREAD_TRACE_CAPTURE_MODE_ALL', 1: 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT', 2: 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL', } SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 1 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 2 SQ_THREAD_TRACE_CAPTURE_MODE = ctypes.c_uint32 # enum # values for enumeration 'SQ_THREAD_TRACE_VM_ID_MASK' SQ_THREAD_TRACE_VM_ID_MASK__enumvalues = { 0: 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE', 1: 'SQ_THREAD_TRACE_VM_ID_MASK_ALL', 2: 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL', } SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0 SQ_THREAD_TRACE_VM_ID_MASK_ALL = 1 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 2 SQ_THREAD_TRACE_VM_ID_MASK = ctypes.c_uint32 # enum # values for enumeration 'SQ_THREAD_TRACE_WAVE_MASK' SQ_THREAD_TRACE_WAVE_MASK__enumvalues = { 0: 'SQ_THREAD_TRACE_WAVE_MASK_NONE', 1: 'SQ_THREAD_TRACE_WAVE_MASK_ALL', } SQ_THREAD_TRACE_WAVE_MASK_NONE = 0 SQ_THREAD_TRACE_WAVE_MASK_ALL = 1 SQ_THREAD_TRACE_WAVE_MASK = ctypes.c_uint32 # enum # values for enumeration 'SQ_THREAD_TRACE_ISSUE' SQ_THREAD_TRACE_ISSUE__enumvalues = { 0: 'SQ_THREAD_TRACE_ISSUE_NULL', 1: 'SQ_THREAD_TRACE_ISSUE_STALL', 2: 'SQ_THREAD_TRACE_ISSUE_INST', 3: 'SQ_THREAD_TRACE_ISSUE_IMMED', } SQ_THREAD_TRACE_ISSUE_NULL = 0 SQ_THREAD_TRACE_ISSUE_STALL = 1 SQ_THREAD_TRACE_ISSUE_INST = 2 SQ_THREAD_TRACE_ISSUE_IMMED = 3 SQ_THREAD_TRACE_ISSUE = ctypes.c_uint32 # enum # values for enumeration 'SQ_THREAD_TRACE_ISSUE_MASK' SQ_THREAD_TRACE_ISSUE_MASK__enumvalues = { 0: 'SQ_THREAD_TRACE_ISSUE_MASK_ALL', 1: 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED', 2: 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED', 3: 'SQ_THREAD_TRACE_ISSUE_MASK_IMMED', } SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0 SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 1 SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 2 SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 3 SQ_THREAD_TRACE_ISSUE_MASK = ctypes.c_uint32 # enum # values for enumeration 'SQ_PERF_SEL' SQ_PERF_SEL__enumvalues = { 0: 'SQ_PERF_SEL_NONE', 1: 'SQ_PERF_SEL_ACCUM_PREV', 2: 'SQ_PERF_SEL_CYCLES', 3: 'SQ_PERF_SEL_BUSY_CYCLES', 4: 'SQ_PERF_SEL_WAVES', 5: 'SQ_PERF_SEL_LEVEL_WAVES', 6: 'SQ_PERF_SEL_WAVES_EQ_64', 7: 'SQ_PERF_SEL_WAVES_LT_64', 8: 'SQ_PERF_SEL_WAVES_LT_48', 9: 'SQ_PERF_SEL_WAVES_LT_32', 10: 'SQ_PERF_SEL_WAVES_LT_16', 11: 'SQ_PERF_SEL_WAVES_CU', 12: 'SQ_PERF_SEL_LEVEL_WAVES_CU', 13: 'SQ_PERF_SEL_BUSY_CU_CYCLES', 14: 'SQ_PERF_SEL_ITEMS', 15: 'SQ_PERF_SEL_QUADS', 16: 'SQ_PERF_SEL_EVENTS', 17: 'SQ_PERF_SEL_SURF_SYNCS', 18: 'SQ_PERF_SEL_TTRACE_REQS', 19: 'SQ_PERF_SEL_TTRACE_INFLIGHT_REQS', 20: 'SQ_PERF_SEL_TTRACE_STALL', 21: 'SQ_PERF_SEL_MSG_CNTR', 22: 'SQ_PERF_SEL_MSG_PERF', 23: 'SQ_PERF_SEL_MSG_GSCNT', 24: 'SQ_PERF_SEL_MSG_INTERRUPT', 25: 'SQ_PERF_SEL_INSTS', 26: 'SQ_PERF_SEL_INSTS_VALU', 27: 'SQ_PERF_SEL_INSTS_VMEM_WR', 28: 'SQ_PERF_SEL_INSTS_VMEM_RD', 29: 'SQ_PERF_SEL_INSTS_VMEM', 30: 'SQ_PERF_SEL_INSTS_SALU', 31: 'SQ_PERF_SEL_INSTS_SMEM', 32: 'SQ_PERF_SEL_INSTS_FLAT', 33: 'SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY', 34: 'SQ_PERF_SEL_INSTS_LDS', 35: 'SQ_PERF_SEL_INSTS_GDS', 36: 'SQ_PERF_SEL_INSTS_EXP', 37: 'SQ_PERF_SEL_INSTS_EXP_GDS', 38: 'SQ_PERF_SEL_INSTS_BRANCH', 39: 'SQ_PERF_SEL_INSTS_SENDMSG', 40: 'SQ_PERF_SEL_INSTS_VSKIPPED', 41: 'SQ_PERF_SEL_INST_LEVEL_VMEM', 42: 'SQ_PERF_SEL_INST_LEVEL_SMEM', 43: 'SQ_PERF_SEL_INST_LEVEL_LDS', 44: 'SQ_PERF_SEL_INST_LEVEL_GDS', 45: 'SQ_PERF_SEL_INST_LEVEL_EXP', 46: 'SQ_PERF_SEL_WAVE_CYCLES', 47: 'SQ_PERF_SEL_WAVE_READY', 48: 'SQ_PERF_SEL_WAIT_CNT_VM', 49: 'SQ_PERF_SEL_WAIT_CNT_LGKM', 50: 'SQ_PERF_SEL_WAIT_CNT_EXP', 51: 'SQ_PERF_SEL_WAIT_CNT_ANY', 52: 'SQ_PERF_SEL_WAIT_BARRIER', 53: 'SQ_PERF_SEL_WAIT_EXP_ALLOC', 54: 'SQ_PERF_SEL_WAIT_SLEEP', 55: 'SQ_PERF_SEL_WAIT_SLEEP_XNACK', 56: 'SQ_PERF_SEL_WAIT_OTHER', 57: 'SQ_PERF_SEL_WAIT_ANY', 58: 'SQ_PERF_SEL_WAIT_TTRACE', 59: 'SQ_PERF_SEL_WAIT_IFETCH', 60: 'SQ_PERF_SEL_WAIT_INST_ANY', 61: 'SQ_PERF_SEL_WAIT_INST_VMEM', 62: 'SQ_PERF_SEL_WAIT_INST_SCA', 63: 'SQ_PERF_SEL_WAIT_INST_LDS', 64: 'SQ_PERF_SEL_WAIT_INST_VALU', 65: 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', 66: 'SQ_PERF_SEL_WAIT_INST_MISC', 67: 'SQ_PERF_SEL_WAIT_INST_FLAT', 68: 'SQ_PERF_SEL_ACTIVE_INST_ANY', 69: 'SQ_PERF_SEL_ACTIVE_INST_VMEM', 70: 'SQ_PERF_SEL_ACTIVE_INST_LDS', 71: 'SQ_PERF_SEL_ACTIVE_INST_VALU', 72: 'SQ_PERF_SEL_ACTIVE_INST_SCA', 73: 'SQ_PERF_SEL_ACTIVE_INST_EXP_GDS', 74: 'SQ_PERF_SEL_ACTIVE_INST_MISC', 75: 'SQ_PERF_SEL_ACTIVE_INST_FLAT', 76: 'SQ_PERF_SEL_INST_CYCLES_VMEM_WR', 77: 'SQ_PERF_SEL_INST_CYCLES_VMEM_RD', 78: 'SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR', 79: 'SQ_PERF_SEL_INST_CYCLES_VMEM_DATA', 80: 'SQ_PERF_SEL_INST_CYCLES_VMEM_CMD', 81: 'SQ_PERF_SEL_INST_CYCLES_EXP', 82: 'SQ_PERF_SEL_INST_CYCLES_GDS', 83: 'SQ_PERF_SEL_INST_CYCLES_SMEM', 84: 'SQ_PERF_SEL_INST_CYCLES_SALU', 85: 'SQ_PERF_SEL_THREAD_CYCLES_VALU', 86: 'SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX', 87: 'SQ_PERF_SEL_IFETCH', 88: 'SQ_PERF_SEL_IFETCH_LEVEL', 89: 'SQ_PERF_SEL_CBRANCH_FORK', 90: 'SQ_PERF_SEL_CBRANCH_FORK_SPLIT', 91: 'SQ_PERF_SEL_VALU_LDS_DIRECT_RD', 92: 'SQ_PERF_SEL_VALU_LDS_INTERP_OP', 93: 'SQ_PERF_SEL_LDS_BANK_CONFLICT', 94: 'SQ_PERF_SEL_LDS_ADDR_CONFLICT', 95: 'SQ_PERF_SEL_LDS_UNALIGNED_STALL', 96: 'SQ_PERF_SEL_LDS_MEM_VIOLATIONS', 97: 'SQ_PERF_SEL_LDS_ATOMIC_RETURN', 98: 'SQ_PERF_SEL_LDS_IDX_ACTIVE', 99: 'SQ_PERF_SEL_VALU_DEP_STALL', 100: 'SQ_PERF_SEL_VALU_STARVE', 101: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', 102: 'SQ_PERF_SEL_LDS_DATA_FIFO_FULL', 103: 'SQ_PERF_SEL_LDS_CMD_FIFO_FULL', 104: 'SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL', 105: 'SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL', 106: 'SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY', 107: 'SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL', 108: 'SQ_PERF_SEL_VALU_SRC_C_CONFLICT', 109: 'SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT', 110: 'SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT', 111: 'SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT', 112: 'SQ_PERF_SEL_LDS_SRC_CD_CONFLICT', 113: 'SQ_PERF_SEL_SRC_CD_BUSY', 114: 'SQ_PERF_SEL_PT_POWER_STALL', 115: 'SQ_PERF_SEL_USER0', 116: 'SQ_PERF_SEL_USER1', 117: 'SQ_PERF_SEL_USER2', 118: 'SQ_PERF_SEL_USER3', 119: 'SQ_PERF_SEL_USER4', 120: 'SQ_PERF_SEL_USER5', 121: 'SQ_PERF_SEL_USER6', 122: 'SQ_PERF_SEL_USER7', 123: 'SQ_PERF_SEL_USER8', 124: 'SQ_PERF_SEL_USER9', 125: 'SQ_PERF_SEL_USER10', 126: 'SQ_PERF_SEL_USER11', 127: 'SQ_PERF_SEL_USER12', 128: 'SQ_PERF_SEL_USER13', 129: 'SQ_PERF_SEL_USER14', 130: 'SQ_PERF_SEL_USER15', 131: 'SQ_PERF_SEL_USER_LEVEL0', 132: 'SQ_PERF_SEL_USER_LEVEL1', 133: 'SQ_PERF_SEL_USER_LEVEL2', 134: 'SQ_PERF_SEL_USER_LEVEL3', 135: 'SQ_PERF_SEL_USER_LEVEL4', 136: 'SQ_PERF_SEL_USER_LEVEL5', 137: 'SQ_PERF_SEL_USER_LEVEL6', 138: 'SQ_PERF_SEL_USER_LEVEL7', 139: 'SQ_PERF_SEL_USER_LEVEL8', 140: 'SQ_PERF_SEL_USER_LEVEL9', 141: 'SQ_PERF_SEL_USER_LEVEL10', 142: 'SQ_PERF_SEL_USER_LEVEL11', 143: 'SQ_PERF_SEL_USER_LEVEL12', 144: 'SQ_PERF_SEL_USER_LEVEL13', 145: 'SQ_PERF_SEL_USER_LEVEL14', 146: 'SQ_PERF_SEL_USER_LEVEL15', 147: 'SQ_PERF_SEL_POWER_VALU', 148: 'SQ_PERF_SEL_POWER_VALU0', 149: 'SQ_PERF_SEL_POWER_VALU1', 150: 'SQ_PERF_SEL_POWER_VALU2', 151: 'SQ_PERF_SEL_POWER_GPR_RD', 152: 'SQ_PERF_SEL_POWER_GPR_WR', 153: 'SQ_PERF_SEL_POWER_LDS_BUSY', 154: 'SQ_PERF_SEL_POWER_ALU_BUSY', 155: 'SQ_PERF_SEL_POWER_TEX_BUSY', 156: 'SQ_PERF_SEL_ACCUM_PREV_HIRES', 157: 'SQ_PERF_SEL_WAVES_RESTORED', 158: 'SQ_PERF_SEL_WAVES_SAVED', 159: 'SQ_PERF_SEL_INSTS_SMEM_NORM', 160: 'SQ_PERF_SEL_ATC_INSTS_VMEM', 161: 'SQ_PERF_SEL_ATC_INST_LEVEL_VMEM', 162: 'SQ_PERF_SEL_ATC_XNACK_FIRST', 163: 'SQ_PERF_SEL_ATC_XNACK_ALL', 164: 'SQ_PERF_SEL_ATC_XNACK_FIFO_FULL', 165: 'SQ_PERF_SEL_ATC_INSTS_SMEM', 166: 'SQ_PERF_SEL_ATC_INST_LEVEL_SMEM', 167: 'SQ_PERF_SEL_IFETCH_XNACK', 168: 'SQ_PERF_SEL_TLB_SHOOTDOWN', 169: 'SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES', 170: 'SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY', 171: 'SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY', 172: 'SQ_PERF_SEL_INSTS_VMEM_REPLAY', 173: 'SQ_PERF_SEL_INSTS_SMEM_REPLAY', 174: 'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY', 175: 'SQ_PERF_SEL_INSTS_FLAT_REPLAY', 176: 'SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY', 177: 'SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY', 178: 'SQ_PERF_SEL_UTCL1_TRANSLATION_MISS', 179: 'SQ_PERF_SEL_UTCL1_PERMISSION_MISS', 180: 'SQ_PERF_SEL_UTCL1_REQUEST', 181: 'SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', 182: 'SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', 183: 'SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', 184: 'SQ_PERF_SEL_UTCL1_LFIFO_FULL', 185: 'SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', 186: 'SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', 187: 'SQ_PERF_SEL_DUMMY_END', 255: 'SQ_PERF_SEL_DUMMY_LAST', 256: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY', 257: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', 258: 'SQC_PERF_SEL_ICACHE_INPUT_VALIDB', 259: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY', 260: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', 261: 'SQC_PERF_SEL_DCACHE_INPUT_VALIDB', 262: 'SQC_PERF_SEL_TC_REQ', 263: 'SQC_PERF_SEL_TC_INST_REQ', 264: 'SQC_PERF_SEL_TC_DATA_READ_REQ', 265: 'SQC_PERF_SEL_TC_DATA_WRITE_REQ', 266: 'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ', 267: 'SQC_PERF_SEL_TC_STALL', 268: 'SQC_PERF_SEL_TC_STARVE', 269: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', 270: 'SQC_PERF_SEL_ICACHE_REQ', 271: 'SQC_PERF_SEL_ICACHE_HITS', 272: 'SQC_PERF_SEL_ICACHE_MISSES', 273: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', 274: 'SQC_PERF_SEL_ICACHE_INVAL_INST', 275: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', 276: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', 277: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', 278: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', 279: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO', 280: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', 281: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT', 282: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO', 283: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO', 284: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF', 285: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', 286: 'SQC_PERF_SEL_ICACHE_PREFETCH_1', 287: 'SQC_PERF_SEL_ICACHE_PREFETCH_2', 288: 'SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED', 289: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', 290: 'SQC_PERF_SEL_DCACHE_REQ', 291: 'SQC_PERF_SEL_DCACHE_HITS', 292: 'SQC_PERF_SEL_DCACHE_MISSES', 293: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', 294: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', 295: 'SQC_PERF_SEL_DCACHE_MISS_EVICT_READ', 296: 'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE', 297: 'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE', 298: 'SQC_PERF_SEL_DCACHE_ATOMIC', 299: 'SQC_PERF_SEL_DCACHE_VOLATILE', 300: 'SQC_PERF_SEL_DCACHE_INVAL_INST', 301: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', 302: 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST', 303: 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC', 304: 'SQC_PERF_SEL_DCACHE_WB_INST', 305: 'SQC_PERF_SEL_DCACHE_WB_ASYNC', 306: 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST', 307: 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC', 308: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', 309: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', 310: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', 311: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', 312: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', 313: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT', 314: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED', 315: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE', 316: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT', 317: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH', 318: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE', 319: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO', 320: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO', 321: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF', 322: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', 323: 'SQC_PERF_SEL_DCACHE_REQ_READ_1', 324: 'SQC_PERF_SEL_DCACHE_REQ_READ_2', 325: 'SQC_PERF_SEL_DCACHE_REQ_READ_4', 326: 'SQC_PERF_SEL_DCACHE_REQ_READ_8', 327: 'SQC_PERF_SEL_DCACHE_REQ_READ_16', 328: 'SQC_PERF_SEL_DCACHE_REQ_TIME', 329: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_1', 330: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_2', 331: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_4', 332: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', 333: 'SQC_PERF_SEL_SQ_DCACHE_REQS', 334: 'SQC_PERF_SEL_DCACHE_FLAT_REQ', 335: 'SQC_PERF_SEL_DCACHE_NONFLAT_REQ', 336: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', 337: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', 338: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 339: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', 340: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', 341: 'SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS', 342: 'SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS', 343: 'SQC_PERF_SEL_ICACHE_GATCL1_REQUEST', 344: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX', 345: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT', 346: 'SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL', 347: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES', 348: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', 349: 'SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT', 350: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL', 351: 'SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS', 352: 'SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS', 353: 'SQC_PERF_SEL_DCACHE_GATCL1_REQUEST', 354: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX', 355: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT', 356: 'SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL', 357: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES', 358: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', 359: 'SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT', 360: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL', 361: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS', 362: 'SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL', 363: 'SQC_PERF_SEL_DUMMY_LAST', } SQ_PERF_SEL_NONE = 0 SQ_PERF_SEL_ACCUM_PREV = 1 SQ_PERF_SEL_CYCLES = 2 SQ_PERF_SEL_BUSY_CYCLES = 3 SQ_PERF_SEL_WAVES = 4 SQ_PERF_SEL_LEVEL_WAVES = 5 SQ_PERF_SEL_WAVES_EQ_64 = 6 SQ_PERF_SEL_WAVES_LT_64 = 7 SQ_PERF_SEL_WAVES_LT_48 = 8 SQ_PERF_SEL_WAVES_LT_32 = 9 SQ_PERF_SEL_WAVES_LT_16 = 10 SQ_PERF_SEL_WAVES_CU = 11 SQ_PERF_SEL_LEVEL_WAVES_CU = 12 SQ_PERF_SEL_BUSY_CU_CYCLES = 13 SQ_PERF_SEL_ITEMS = 14 SQ_PERF_SEL_QUADS = 15 SQ_PERF_SEL_EVENTS = 16 SQ_PERF_SEL_SURF_SYNCS = 17 SQ_PERF_SEL_TTRACE_REQS = 18 SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 19 SQ_PERF_SEL_TTRACE_STALL = 20 SQ_PERF_SEL_MSG_CNTR = 21 SQ_PERF_SEL_MSG_PERF = 22 SQ_PERF_SEL_MSG_GSCNT = 23 SQ_PERF_SEL_MSG_INTERRUPT = 24 SQ_PERF_SEL_INSTS = 25 SQ_PERF_SEL_INSTS_VALU = 26 SQ_PERF_SEL_INSTS_VMEM_WR = 27 SQ_PERF_SEL_INSTS_VMEM_RD = 28 SQ_PERF_SEL_INSTS_VMEM = 29 SQ_PERF_SEL_INSTS_SALU = 30 SQ_PERF_SEL_INSTS_SMEM = 31 SQ_PERF_SEL_INSTS_FLAT = 32 SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 33 SQ_PERF_SEL_INSTS_LDS = 34 SQ_PERF_SEL_INSTS_GDS = 35 SQ_PERF_SEL_INSTS_EXP = 36 SQ_PERF_SEL_INSTS_EXP_GDS = 37 SQ_PERF_SEL_INSTS_BRANCH = 38 SQ_PERF_SEL_INSTS_SENDMSG = 39 SQ_PERF_SEL_INSTS_VSKIPPED = 40 SQ_PERF_SEL_INST_LEVEL_VMEM = 41 SQ_PERF_SEL_INST_LEVEL_SMEM = 42 SQ_PERF_SEL_INST_LEVEL_LDS = 43 SQ_PERF_SEL_INST_LEVEL_GDS = 44 SQ_PERF_SEL_INST_LEVEL_EXP = 45 SQ_PERF_SEL_WAVE_CYCLES = 46 SQ_PERF_SEL_WAVE_READY = 47 SQ_PERF_SEL_WAIT_CNT_VM = 48 SQ_PERF_SEL_WAIT_CNT_LGKM = 49 SQ_PERF_SEL_WAIT_CNT_EXP = 50 SQ_PERF_SEL_WAIT_CNT_ANY = 51 SQ_PERF_SEL_WAIT_BARRIER = 52 SQ_PERF_SEL_WAIT_EXP_ALLOC = 53 SQ_PERF_SEL_WAIT_SLEEP = 54 SQ_PERF_SEL_WAIT_SLEEP_XNACK = 55 SQ_PERF_SEL_WAIT_OTHER = 56 SQ_PERF_SEL_WAIT_ANY = 57 SQ_PERF_SEL_WAIT_TTRACE = 58 SQ_PERF_SEL_WAIT_IFETCH = 59 SQ_PERF_SEL_WAIT_INST_ANY = 60 SQ_PERF_SEL_WAIT_INST_VMEM = 61 SQ_PERF_SEL_WAIT_INST_SCA = 62 SQ_PERF_SEL_WAIT_INST_LDS = 63 SQ_PERF_SEL_WAIT_INST_VALU = 64 SQ_PERF_SEL_WAIT_INST_EXP_GDS = 65 SQ_PERF_SEL_WAIT_INST_MISC = 66 SQ_PERF_SEL_WAIT_INST_FLAT = 67 SQ_PERF_SEL_ACTIVE_INST_ANY = 68 SQ_PERF_SEL_ACTIVE_INST_VMEM = 69 SQ_PERF_SEL_ACTIVE_INST_LDS = 70 SQ_PERF_SEL_ACTIVE_INST_VALU = 71 SQ_PERF_SEL_ACTIVE_INST_SCA = 72 SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 73 SQ_PERF_SEL_ACTIVE_INST_MISC = 74 SQ_PERF_SEL_ACTIVE_INST_FLAT = 75 SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 76 SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 77 SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 78 SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 79 SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 80 SQ_PERF_SEL_INST_CYCLES_EXP = 81 SQ_PERF_SEL_INST_CYCLES_GDS = 82 SQ_PERF_SEL_INST_CYCLES_SMEM = 83 SQ_PERF_SEL_INST_CYCLES_SALU = 84 SQ_PERF_SEL_THREAD_CYCLES_VALU = 85 SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 86 SQ_PERF_SEL_IFETCH = 87 SQ_PERF_SEL_IFETCH_LEVEL = 88 SQ_PERF_SEL_CBRANCH_FORK = 89 SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 90 SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 91 SQ_PERF_SEL_VALU_LDS_INTERP_OP = 92 SQ_PERF_SEL_LDS_BANK_CONFLICT = 93 SQ_PERF_SEL_LDS_ADDR_CONFLICT = 94 SQ_PERF_SEL_LDS_UNALIGNED_STALL = 95 SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 96 SQ_PERF_SEL_LDS_ATOMIC_RETURN = 97 SQ_PERF_SEL_LDS_IDX_ACTIVE = 98 SQ_PERF_SEL_VALU_DEP_STALL = 99 SQ_PERF_SEL_VALU_STARVE = 100 SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 101 SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 102 SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 103 SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 104 SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 105 SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 106 SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 107 SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 108 SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 109 SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 110 SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 111 SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 112 SQ_PERF_SEL_SRC_CD_BUSY = 113 SQ_PERF_SEL_PT_POWER_STALL = 114 SQ_PERF_SEL_USER0 = 115 SQ_PERF_SEL_USER1 = 116 SQ_PERF_SEL_USER2 = 117 SQ_PERF_SEL_USER3 = 118 SQ_PERF_SEL_USER4 = 119 SQ_PERF_SEL_USER5 = 120 SQ_PERF_SEL_USER6 = 121 SQ_PERF_SEL_USER7 = 122 SQ_PERF_SEL_USER8 = 123 SQ_PERF_SEL_USER9 = 124 SQ_PERF_SEL_USER10 = 125 SQ_PERF_SEL_USER11 = 126 SQ_PERF_SEL_USER12 = 127 SQ_PERF_SEL_USER13 = 128 SQ_PERF_SEL_USER14 = 129 SQ_PERF_SEL_USER15 = 130 SQ_PERF_SEL_USER_LEVEL0 = 131 SQ_PERF_SEL_USER_LEVEL1 = 132 SQ_PERF_SEL_USER_LEVEL2 = 133 SQ_PERF_SEL_USER_LEVEL3 = 134 SQ_PERF_SEL_USER_LEVEL4 = 135 SQ_PERF_SEL_USER_LEVEL5 = 136 SQ_PERF_SEL_USER_LEVEL6 = 137 SQ_PERF_SEL_USER_LEVEL7 = 138 SQ_PERF_SEL_USER_LEVEL8 = 139 SQ_PERF_SEL_USER_LEVEL9 = 140 SQ_PERF_SEL_USER_LEVEL10 = 141 SQ_PERF_SEL_USER_LEVEL11 = 142 SQ_PERF_SEL_USER_LEVEL12 = 143 SQ_PERF_SEL_USER_LEVEL13 = 144 SQ_PERF_SEL_USER_LEVEL14 = 145 SQ_PERF_SEL_USER_LEVEL15 = 146 SQ_PERF_SEL_POWER_VALU = 147 SQ_PERF_SEL_POWER_VALU0 = 148 SQ_PERF_SEL_POWER_VALU1 = 149 SQ_PERF_SEL_POWER_VALU2 = 150 SQ_PERF_SEL_POWER_GPR_RD = 151 SQ_PERF_SEL_POWER_GPR_WR = 152 SQ_PERF_SEL_POWER_LDS_BUSY = 153 SQ_PERF_SEL_POWER_ALU_BUSY = 154 SQ_PERF_SEL_POWER_TEX_BUSY = 155 SQ_PERF_SEL_ACCUM_PREV_HIRES = 156 SQ_PERF_SEL_WAVES_RESTORED = 157 SQ_PERF_SEL_WAVES_SAVED = 158 SQ_PERF_SEL_INSTS_SMEM_NORM = 159 SQ_PERF_SEL_ATC_INSTS_VMEM = 160 SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 161 SQ_PERF_SEL_ATC_XNACK_FIRST = 162 SQ_PERF_SEL_ATC_XNACK_ALL = 163 SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 164 SQ_PERF_SEL_ATC_INSTS_SMEM = 165 SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 166 SQ_PERF_SEL_IFETCH_XNACK = 167 SQ_PERF_SEL_TLB_SHOOTDOWN = 168 SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 169 SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 170 SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 171 SQ_PERF_SEL_INSTS_VMEM_REPLAY = 172 SQ_PERF_SEL_INSTS_SMEM_REPLAY = 173 SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 174 SQ_PERF_SEL_INSTS_FLAT_REPLAY = 175 SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 176 SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 177 SQ_PERF_SEL_UTCL1_TRANSLATION_MISS = 178 SQ_PERF_SEL_UTCL1_PERMISSION_MISS = 179 SQ_PERF_SEL_UTCL1_REQUEST = 180 SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 181 SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 182 SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 183 SQ_PERF_SEL_UTCL1_LFIFO_FULL = 184 SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 185 SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 186 SQ_PERF_SEL_DUMMY_END = 187 SQ_PERF_SEL_DUMMY_LAST = 255 SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 256 SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 257 SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 258 SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 259 SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 260 SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 261 SQC_PERF_SEL_TC_REQ = 262 SQC_PERF_SEL_TC_INST_REQ = 263 SQC_PERF_SEL_TC_DATA_READ_REQ = 264 SQC_PERF_SEL_TC_DATA_WRITE_REQ = 265 SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 266 SQC_PERF_SEL_TC_STALL = 267 SQC_PERF_SEL_TC_STARVE = 268 SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 269 SQC_PERF_SEL_ICACHE_REQ = 270 SQC_PERF_SEL_ICACHE_HITS = 271 SQC_PERF_SEL_ICACHE_MISSES = 272 SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 273 SQC_PERF_SEL_ICACHE_INVAL_INST = 274 SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 275 SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 276 SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 277 SQC_PERF_SEL_ICACHE_CACHE_STALLED = 278 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 279 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 280 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 281 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 282 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 283 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 284 SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 285 SQC_PERF_SEL_ICACHE_PREFETCH_1 = 286 SQC_PERF_SEL_ICACHE_PREFETCH_2 = 287 SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED = 288 SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 289 SQC_PERF_SEL_DCACHE_REQ = 290 SQC_PERF_SEL_DCACHE_HITS = 291 SQC_PERF_SEL_DCACHE_MISSES = 292 SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 293 SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 294 SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 295 SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 296 SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 297 SQC_PERF_SEL_DCACHE_ATOMIC = 298 SQC_PERF_SEL_DCACHE_VOLATILE = 299 SQC_PERF_SEL_DCACHE_INVAL_INST = 300 SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 301 SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 302 SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 303 SQC_PERF_SEL_DCACHE_WB_INST = 304 SQC_PERF_SEL_DCACHE_WB_ASYNC = 305 SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 306 SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 307 SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 308 SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 309 SQC_PERF_SEL_DCACHE_CACHE_STALLED = 310 SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 311 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 312 SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 313 SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 314 SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 315 SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 316 SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 317 SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 318 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 319 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 320 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 321 SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 322 SQC_PERF_SEL_DCACHE_REQ_READ_1 = 323 SQC_PERF_SEL_DCACHE_REQ_READ_2 = 324 SQC_PERF_SEL_DCACHE_REQ_READ_4 = 325 SQC_PERF_SEL_DCACHE_REQ_READ_8 = 326 SQC_PERF_SEL_DCACHE_REQ_READ_16 = 327 SQC_PERF_SEL_DCACHE_REQ_TIME = 328 SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 329 SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 330 SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 331 SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 332 SQC_PERF_SEL_SQ_DCACHE_REQS = 333 SQC_PERF_SEL_DCACHE_FLAT_REQ = 334 SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 335 SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 336 SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 337 SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 338 SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 339 SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 340 SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 341 SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 342 SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 343 SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 344 SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 345 SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 346 SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 347 SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 348 SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 349 SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 350 SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 351 SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 352 SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 353 SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 354 SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 355 SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 356 SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 357 SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 358 SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 359 SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 360 SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 361 SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 362 SQC_PERF_SEL_DUMMY_LAST = 363 SQ_PERF_SEL = ctypes.c_uint32 # enum # values for enumeration 'SQ_CAC_POWER_SEL' SQ_CAC_POWER_SEL__enumvalues = { 0: 'SQ_CAC_POWER_VALU', 1: 'SQ_CAC_POWER_VALU0', 2: 'SQ_CAC_POWER_VALU1', 3: 'SQ_CAC_POWER_VALU2', 4: 'SQ_CAC_POWER_GPR_RD', 5: 'SQ_CAC_POWER_GPR_WR', 6: 'SQ_CAC_POWER_LDS_BUSY', 7: 'SQ_CAC_POWER_ALU_BUSY', 8: 'SQ_CAC_POWER_TEX_BUSY', } SQ_CAC_POWER_VALU = 0 SQ_CAC_POWER_VALU0 = 1 SQ_CAC_POWER_VALU1 = 2 SQ_CAC_POWER_VALU2 = 3 SQ_CAC_POWER_GPR_RD = 4 SQ_CAC_POWER_GPR_WR = 5 SQ_CAC_POWER_LDS_BUSY = 6 SQ_CAC_POWER_ALU_BUSY = 7 SQ_CAC_POWER_TEX_BUSY = 8 SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum # values for enumeration 'SQ_IND_CMD_CMD' SQ_IND_CMD_CMD__enumvalues = { 0: 'SQ_IND_CMD_CMD_NULL', 1: 'SQ_IND_CMD_CMD_SETHALT', 2: 'SQ_IND_CMD_CMD_SAVECTX', 3: 'SQ_IND_CMD_CMD_KILL', 4: 'SQ_IND_CMD_CMD_DEBUG', 5: 'SQ_IND_CMD_CMD_TRAP', 6: 'SQ_IND_CMD_CMD_SET_SPI_PRIO', 7: 'SQ_IND_CMD_CMD_SETFATALHALT', } SQ_IND_CMD_CMD_NULL = 0 SQ_IND_CMD_CMD_SETHALT = 1 SQ_IND_CMD_CMD_SAVECTX = 2 SQ_IND_CMD_CMD_KILL = 3 SQ_IND_CMD_CMD_DEBUG = 4 SQ_IND_CMD_CMD_TRAP = 5 SQ_IND_CMD_CMD_SET_SPI_PRIO = 6 SQ_IND_CMD_CMD_SETFATALHALT = 7 SQ_IND_CMD_CMD = ctypes.c_uint32 # enum # values for enumeration 'SQ_IND_CMD_MODE' SQ_IND_CMD_MODE__enumvalues = { 0: 'SQ_IND_CMD_MODE_SINGLE', 1: 'SQ_IND_CMD_MODE_BROADCAST', 2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE', 4: 'SQ_IND_CMD_MODE_BROADCAST_ME', } SQ_IND_CMD_MODE_SINGLE = 0 SQ_IND_CMD_MODE_BROADCAST = 1 SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2 SQ_IND_CMD_MODE_BROADCAST_PIPE = 3 SQ_IND_CMD_MODE_BROADCAST_ME = 4 SQ_IND_CMD_MODE = ctypes.c_uint32 # enum # values for enumeration 'SQ_EDC_INFO_SOURCE' SQ_EDC_INFO_SOURCE__enumvalues = { 0: 'SQ_EDC_INFO_SOURCE_INVALID', 1: 'SQ_EDC_INFO_SOURCE_INST', 2: 'SQ_EDC_INFO_SOURCE_SGPR', 3: 'SQ_EDC_INFO_SOURCE_VGPR', 4: 'SQ_EDC_INFO_SOURCE_LDS', 5: 'SQ_EDC_INFO_SOURCE_GDS', 6: 'SQ_EDC_INFO_SOURCE_TA', } SQ_EDC_INFO_SOURCE_INVALID = 0 SQ_EDC_INFO_SOURCE_INST = 1 SQ_EDC_INFO_SOURCE_SGPR = 2 SQ_EDC_INFO_SOURCE_VGPR = 3 SQ_EDC_INFO_SOURCE_LDS = 4 SQ_EDC_INFO_SOURCE_GDS = 5 SQ_EDC_INFO_SOURCE_TA = 6 SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum # values for enumeration 'SQ_ROUND_MODE' SQ_ROUND_MODE__enumvalues = { 0: 'SQ_ROUND_NEAREST_EVEN', 1: 'SQ_ROUND_PLUS_INFINITY', 2: 'SQ_ROUND_MINUS_INFINITY', 3: 'SQ_ROUND_TO_ZERO', } SQ_ROUND_NEAREST_EVEN = 0 SQ_ROUND_PLUS_INFINITY = 1 SQ_ROUND_MINUS_INFINITY = 2 SQ_ROUND_TO_ZERO = 3 SQ_ROUND_MODE = ctypes.c_uint32 # enum # values for enumeration 'SQ_INTERRUPT_WORD_ENCODING' SQ_INTERRUPT_WORD_ENCODING__enumvalues = { 0: 'SQ_INTERRUPT_WORD_ENCODING_AUTO', 1: 'SQ_INTERRUPT_WORD_ENCODING_INST', 2: 'SQ_INTERRUPT_WORD_ENCODING_ERROR', } SQ_INTERRUPT_WORD_ENCODING_AUTO = 0 SQ_INTERRUPT_WORD_ENCODING_INST = 1 SQ_INTERRUPT_WORD_ENCODING_ERROR = 2 SQ_INTERRUPT_WORD_ENCODING = ctypes.c_uint32 # enum # values for enumeration 'ENUM_SQ_EXPORT_RAT_INST' ENUM_SQ_EXPORT_RAT_INST__enumvalues = { 0: 'SQ_EXPORT_RAT_INST_NOP', 1: 'SQ_EXPORT_RAT_INST_STORE_TYPED', 2: 'SQ_EXPORT_RAT_INST_STORE_RAW', 3: 'SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM', 4: 'SQ_EXPORT_RAT_INST_CMPXCHG_INT', 5: 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT', 6: 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM', 7: 'SQ_EXPORT_RAT_INST_ADD', 8: 'SQ_EXPORT_RAT_INST_SUB', 9: 'SQ_EXPORT_RAT_INST_RSUB', 10: 'SQ_EXPORT_RAT_INST_MIN_INT', 11: 'SQ_EXPORT_RAT_INST_MIN_UINT', 12: 'SQ_EXPORT_RAT_INST_MAX_INT', 13: 'SQ_EXPORT_RAT_INST_MAX_UINT', 14: 'SQ_EXPORT_RAT_INST_AND', 15: 'SQ_EXPORT_RAT_INST_OR', 16: 'SQ_EXPORT_RAT_INST_XOR', 17: 'SQ_EXPORT_RAT_INST_MSKOR', 18: 'SQ_EXPORT_RAT_INST_INC_UINT', 19: 'SQ_EXPORT_RAT_INST_DEC_UINT', 20: 'SQ_EXPORT_RAT_INST_STORE_DWORD', 21: 'SQ_EXPORT_RAT_INST_STORE_SHORT', 22: 'SQ_EXPORT_RAT_INST_STORE_BYTE', 32: 'SQ_EXPORT_RAT_INST_NOP_RTN', 34: 'SQ_EXPORT_RAT_INST_XCHG_RTN', 35: 'SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN', 36: 'SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN', 37: 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN', 38: 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN', 39: 'SQ_EXPORT_RAT_INST_ADD_RTN', 40: 'SQ_EXPORT_RAT_INST_SUB_RTN', 41: 'SQ_EXPORT_RAT_INST_RSUB_RTN', 42: 'SQ_EXPORT_RAT_INST_MIN_INT_RTN', 43: 'SQ_EXPORT_RAT_INST_MIN_UINT_RTN', 44: 'SQ_EXPORT_RAT_INST_MAX_INT_RTN', 45: 'SQ_EXPORT_RAT_INST_MAX_UINT_RTN', 46: 'SQ_EXPORT_RAT_INST_AND_RTN', 47: 'SQ_EXPORT_RAT_INST_OR_RTN', 48: 'SQ_EXPORT_RAT_INST_XOR_RTN', 49: 'SQ_EXPORT_RAT_INST_MSKOR_RTN', 50: 'SQ_EXPORT_RAT_INST_INC_UINT_RTN', 51: 'SQ_EXPORT_RAT_INST_DEC_UINT_RTN', } SQ_EXPORT_RAT_INST_NOP = 0 SQ_EXPORT_RAT_INST_STORE_TYPED = 1 SQ_EXPORT_RAT_INST_STORE_RAW = 2 SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 3 SQ_EXPORT_RAT_INST_CMPXCHG_INT = 4 SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 5 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 6 SQ_EXPORT_RAT_INST_ADD = 7 SQ_EXPORT_RAT_INST_SUB = 8 SQ_EXPORT_RAT_INST_RSUB = 9 SQ_EXPORT_RAT_INST_MIN_INT = 10 SQ_EXPORT_RAT_INST_MIN_UINT = 11 SQ_EXPORT_RAT_INST_MAX_INT = 12 SQ_EXPORT_RAT_INST_MAX_UINT = 13 SQ_EXPORT_RAT_INST_AND = 14 SQ_EXPORT_RAT_INST_OR = 15 SQ_EXPORT_RAT_INST_XOR = 16 SQ_EXPORT_RAT_INST_MSKOR = 17 SQ_EXPORT_RAT_INST_INC_UINT = 18 SQ_EXPORT_RAT_INST_DEC_UINT = 19 SQ_EXPORT_RAT_INST_STORE_DWORD = 20 SQ_EXPORT_RAT_INST_STORE_SHORT = 21 SQ_EXPORT_RAT_INST_STORE_BYTE = 22 SQ_EXPORT_RAT_INST_NOP_RTN = 32 SQ_EXPORT_RAT_INST_XCHG_RTN = 34 SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 35 SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 36 SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 37 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 38 SQ_EXPORT_RAT_INST_ADD_RTN = 39 SQ_EXPORT_RAT_INST_SUB_RTN = 40 SQ_EXPORT_RAT_INST_RSUB_RTN = 41 SQ_EXPORT_RAT_INST_MIN_INT_RTN = 42 SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 43 SQ_EXPORT_RAT_INST_MAX_INT_RTN = 44 SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 45 SQ_EXPORT_RAT_INST_AND_RTN = 46 SQ_EXPORT_RAT_INST_OR_RTN = 47 SQ_EXPORT_RAT_INST_XOR_RTN = 48 SQ_EXPORT_RAT_INST_MSKOR_RTN = 49 SQ_EXPORT_RAT_INST_INC_UINT_RTN = 50 SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 51 ENUM_SQ_EXPORT_RAT_INST = ctypes.c_uint32 # enum # values for enumeration 'SQ_IBUF_ST' SQ_IBUF_ST__enumvalues = { 0: 'SQ_IBUF_IB_IDLE', 1: 'SQ_IBUF_IB_INI_WAIT_GNT', 2: 'SQ_IBUF_IB_INI_WAIT_DRET', 3: 'SQ_IBUF_IB_LE_4DW', 4: 'SQ_IBUF_IB_WAIT_DRET', 5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET', 6: 'SQ_IBUF_IB_DRET', 7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT', } SQ_IBUF_IB_IDLE = 0 SQ_IBUF_IB_INI_WAIT_GNT = 1 SQ_IBUF_IB_INI_WAIT_DRET = 2 SQ_IBUF_IB_LE_4DW = 3 SQ_IBUF_IB_WAIT_DRET = 4 SQ_IBUF_IB_EMPTY_WAIT_DRET = 5 SQ_IBUF_IB_DRET = 6 SQ_IBUF_IB_EMPTY_WAIT_GNT = 7 SQ_IBUF_ST = ctypes.c_uint32 # enum # values for enumeration 'SQ_INST_STR_ST' SQ_INST_STR_ST__enumvalues = { 0: 'SQ_INST_STR_IB_WAVE_NORML', 1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', 2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', 3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', 4: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0', 5: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1', 6: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 7: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', } SQ_INST_STR_IB_WAVE_NORML = 0 SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1 SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2 SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3 SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 4 SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 5 SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 6 SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 7 SQ_INST_STR_ST = ctypes.c_uint32 # enum # values for enumeration 'SQ_WAVE_IB_ECC_ST' SQ_WAVE_IB_ECC_ST__enumvalues = { 0: 'SQ_WAVE_IB_ECC_CLEAN', 1: 'SQ_WAVE_IB_ECC_ERR_CONTINUE', 2: 'SQ_WAVE_IB_ECC_ERR_HALT', 3: 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', } SQ_WAVE_IB_ECC_CLEAN = 0 SQ_WAVE_IB_ECC_ERR_CONTINUE = 1 SQ_WAVE_IB_ECC_ERR_HALT = 2 SQ_WAVE_IB_ECC_WITH_ERR_MSG = 3 SQ_WAVE_IB_ECC_ST = ctypes.c_uint32 # enum # values for enumeration 'SH_MEM_ADDRESS_MODE' SH_MEM_ADDRESS_MODE__enumvalues = { 0: 'SH_MEM_ADDRESS_MODE_64', 1: 'SH_MEM_ADDRESS_MODE_32', } SH_MEM_ADDRESS_MODE_64 = 0 SH_MEM_ADDRESS_MODE_32 = 1 SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum # values for enumeration 'SH_MEM_ALIGNMENT_MODE' SH_MEM_ALIGNMENT_MODE__enumvalues = { 0: 'SH_MEM_ALIGNMENT_MODE_DWORD', 1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', 2: 'SH_MEM_ALIGNMENT_MODE_STRICT', 3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', } SH_MEM_ALIGNMENT_MODE_DWORD = 0 SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1 SH_MEM_ALIGNMENT_MODE_STRICT = 2 SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3 SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum # values for enumeration 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX' SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX__enumvalues = { 24: 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC', 25: 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE', } SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 24 SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 25 SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX = ctypes.c_uint32 # enum # values for enumeration 'SQ_LB_CTR_SEL_VALUES' SQ_LB_CTR_SEL_VALUES__enumvalues = { 0: 'SQ_LB_CTR_SEL_ALU_CYCLES', 1: 'SQ_LB_CTR_SEL_ALU_STALLS', 2: 'SQ_LB_CTR_SEL_TEX_CYCLES', 3: 'SQ_LB_CTR_SEL_TEX_STALLS', 4: 'SQ_LB_CTR_SEL_SALU_CYCLES', 5: 'SQ_LB_CTR_SEL_SCALAR_STALLS', 6: 'SQ_LB_CTR_SEL_SMEM_CYCLES', 7: 'SQ_LB_CTR_SEL_ICACHE_STALLS', 8: 'SQ_LB_CTR_SEL_DCACHE_STALLS', 9: 'SQ_LB_CTR_SEL_RESERVED0', 10: 'SQ_LB_CTR_SEL_RESERVED1', 11: 'SQ_LB_CTR_SEL_RESERVED2', 12: 'SQ_LB_CTR_SEL_RESERVED3', 13: 'SQ_LB_CTR_SEL_RESERVED4', 14: 'SQ_LB_CTR_SEL_RESERVED5', 15: 'SQ_LB_CTR_SEL_RESERVED6', } SQ_LB_CTR_SEL_ALU_CYCLES = 0 SQ_LB_CTR_SEL_ALU_STALLS = 1 SQ_LB_CTR_SEL_TEX_CYCLES = 2 SQ_LB_CTR_SEL_TEX_STALLS = 3 SQ_LB_CTR_SEL_SALU_CYCLES = 4 SQ_LB_CTR_SEL_SCALAR_STALLS = 5 SQ_LB_CTR_SEL_SMEM_CYCLES = 6 SQ_LB_CTR_SEL_ICACHE_STALLS = 7 SQ_LB_CTR_SEL_DCACHE_STALLS = 8 SQ_LB_CTR_SEL_RESERVED0 = 9 SQ_LB_CTR_SEL_RESERVED1 = 10 SQ_LB_CTR_SEL_RESERVED2 = 11 SQ_LB_CTR_SEL_RESERVED3 = 12 SQ_LB_CTR_SEL_RESERVED4 = 13 SQ_LB_CTR_SEL_RESERVED5 = 14 SQ_LB_CTR_SEL_RESERVED6 = 15 SQ_LB_CTR_SEL_VALUES = ctypes.c_uint32 # enum # values for enumeration 'CSDATA_TYPE' CSDATA_TYPE__enumvalues = { 0: 'CSDATA_TYPE_TG', 1: 'CSDATA_TYPE_STATE', 2: 'CSDATA_TYPE_EVENT', 3: 'CSDATA_TYPE_PRIVATE', } CSDATA_TYPE_TG = 0 CSDATA_TYPE_STATE = 1 CSDATA_TYPE_EVENT = 2 CSDATA_TYPE_PRIVATE = 3 CSDATA_TYPE = ctypes.c_uint32 # enum # values for enumeration 'VGT_OUT_PRIM_TYPE' VGT_OUT_PRIM_TYPE__enumvalues = { 0: 'VGT_OUT_POINT', 1: 'VGT_OUT_LINE', 2: 'VGT_OUT_TRI', 3: 'VGT_OUT_RECT_V0', 4: 'VGT_OUT_RECT_V1', 5: 'VGT_OUT_RECT_V2', 6: 'VGT_OUT_RECT_V3', 7: 'VGT_OUT_2D_RECT', 8: 'VGT_TE_QUAD', 9: 'VGT_TE_PRIM_INDEX_LINE', 10: 'VGT_TE_PRIM_INDEX_TRI', 11: 'VGT_TE_PRIM_INDEX_QUAD', 12: 'VGT_OUT_LINE_ADJ', 13: 'VGT_OUT_TRI_ADJ', 14: 'VGT_OUT_PATCH', } VGT_OUT_POINT = 0 VGT_OUT_LINE = 1 VGT_OUT_TRI = 2 VGT_OUT_RECT_V0 = 3 VGT_OUT_RECT_V1 = 4 VGT_OUT_RECT_V2 = 5 VGT_OUT_RECT_V3 = 6 VGT_OUT_2D_RECT = 7 VGT_TE_QUAD = 8 VGT_TE_PRIM_INDEX_LINE = 9 VGT_TE_PRIM_INDEX_TRI = 10 VGT_TE_PRIM_INDEX_QUAD = 11 VGT_OUT_LINE_ADJ = 12 VGT_OUT_TRI_ADJ = 13 VGT_OUT_PATCH = 14 VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum # values for enumeration 'VGT_DI_PRIM_TYPE' VGT_DI_PRIM_TYPE__enumvalues = { 0: 'DI_PT_NONE', 1: 'DI_PT_POINTLIST', 2: 'DI_PT_LINELIST', 3: 'DI_PT_LINESTRIP', 4: 'DI_PT_TRILIST', 5: 'DI_PT_TRIFAN', 6: 'DI_PT_TRISTRIP', 7: 'DI_PT_2D_RECTANGLE', 8: 'DI_PT_UNUSED_1', 9: 'DI_PT_PATCH', 10: 'DI_PT_LINELIST_ADJ', 11: 'DI_PT_LINESTRIP_ADJ', 12: 'DI_PT_TRILIST_ADJ', 13: 'DI_PT_TRISTRIP_ADJ', 14: 'DI_PT_UNUSED_3', 15: 'DI_PT_UNUSED_4', 16: 'DI_PT_TRI_WITH_WFLAGS', 17: 'DI_PT_RECTLIST', 18: 'DI_PT_LINELOOP', 19: 'DI_PT_QUADLIST', 20: 'DI_PT_QUADSTRIP', 21: 'DI_PT_POLYGON', } DI_PT_NONE = 0 DI_PT_POINTLIST = 1 DI_PT_LINELIST = 2 DI_PT_LINESTRIP = 3 DI_PT_TRILIST = 4 DI_PT_TRIFAN = 5 DI_PT_TRISTRIP = 6 DI_PT_2D_RECTANGLE = 7 DI_PT_UNUSED_1 = 8 DI_PT_PATCH = 9 DI_PT_LINELIST_ADJ = 10 DI_PT_LINESTRIP_ADJ = 11 DI_PT_TRILIST_ADJ = 12 DI_PT_TRISTRIP_ADJ = 13 DI_PT_UNUSED_3 = 14 DI_PT_UNUSED_4 = 15 DI_PT_TRI_WITH_WFLAGS = 16 DI_PT_RECTLIST = 17 DI_PT_LINELOOP = 18 DI_PT_QUADLIST = 19 DI_PT_QUADSTRIP = 20 DI_PT_POLYGON = 21 VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum # values for enumeration 'VGT_DI_SOURCE_SELECT' VGT_DI_SOURCE_SELECT__enumvalues = { 0: 'DI_SRC_SEL_DMA', 1: 'DI_SRC_SEL_IMMEDIATE', 2: 'DI_SRC_SEL_AUTO_INDEX', 3: 'DI_SRC_SEL_RESERVED', } DI_SRC_SEL_DMA = 0 DI_SRC_SEL_IMMEDIATE = 1 DI_SRC_SEL_AUTO_INDEX = 2 DI_SRC_SEL_RESERVED = 3 VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum # values for enumeration 'VGT_DI_MAJOR_MODE_SELECT' VGT_DI_MAJOR_MODE_SELECT__enumvalues = { 0: 'DI_MAJOR_MODE_0', 1: 'DI_MAJOR_MODE_1', } DI_MAJOR_MODE_0 = 0 DI_MAJOR_MODE_1 = 1 VGT_DI_MAJOR_MODE_SELECT = ctypes.c_uint32 # enum # values for enumeration 'VGT_DI_INDEX_SIZE' VGT_DI_INDEX_SIZE__enumvalues = { 0: 'DI_INDEX_SIZE_16_BIT', 1: 'DI_INDEX_SIZE_32_BIT', 2: 'DI_INDEX_SIZE_8_BIT', } DI_INDEX_SIZE_16_BIT = 0 DI_INDEX_SIZE_32_BIT = 1 DI_INDEX_SIZE_8_BIT = 2 VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum # values for enumeration 'VGT_EVENT_TYPE' VGT_EVENT_TYPE__enumvalues = { 0: 'Reserved_0x00', 1: 'SAMPLE_STREAMOUTSTATS1', 2: 'SAMPLE_STREAMOUTSTATS2', 3: 'SAMPLE_STREAMOUTSTATS3', 4: 'CACHE_FLUSH_TS', 5: 'CONTEXT_DONE', 6: 'CACHE_FLUSH', 7: 'CS_PARTIAL_FLUSH', 8: 'VGT_STREAMOUT_SYNC', 9: 'Reserved_0x09', 10: 'VGT_STREAMOUT_RESET', 11: 'END_OF_PIPE_INCR_DE', 12: 'END_OF_PIPE_IB_END', 13: 'RST_PIX_CNT', 14: 'BREAK_BATCH', 15: 'VS_PARTIAL_FLUSH', 16: 'PS_PARTIAL_FLUSH', 17: 'FLUSH_HS_OUTPUT', 18: 'FLUSH_DFSM', 19: 'RESET_TO_LOWEST_VGT', 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', 21: 'ZPASS_DONE', 22: 'CACHE_FLUSH_AND_INV_EVENT', 23: 'PERFCOUNTER_START', 24: 'PERFCOUNTER_STOP', 25: 'PIPELINESTAT_START', 26: 'PIPELINESTAT_STOP', 27: 'PERFCOUNTER_SAMPLE', 28: 'Available_0x1c', 29: 'Available_0x1d', 30: 'SAMPLE_PIPELINESTAT', 31: 'SO_VGTSTREAMOUT_FLUSH', 32: 'SAMPLE_STREAMOUTSTATS', 33: 'RESET_VTX_CNT', 34: 'BLOCK_CONTEXT_DONE', 35: 'CS_CONTEXT_DONE', 36: 'VGT_FLUSH', 37: 'TGID_ROLLOVER', 38: 'SQ_NON_EVENT', 39: 'SC_SEND_DB_VPZ', 40: 'BOTTOM_OF_PIPE_TS', 41: 'FLUSH_SX_TS', 42: 'DB_CACHE_FLUSH_AND_INV', 43: 'FLUSH_AND_INV_DB_DATA_TS', 44: 'FLUSH_AND_INV_DB_META', 45: 'FLUSH_AND_INV_CB_DATA_TS', 46: 'FLUSH_AND_INV_CB_META', 47: 'CS_DONE', 48: 'PS_DONE', 49: 'FLUSH_AND_INV_CB_PIXEL_DATA', 50: 'SX_CB_RAT_ACK_REQUEST', 51: 'THREAD_TRACE_START', 52: 'THREAD_TRACE_STOP', 53: 'THREAD_TRACE_MARKER', 54: 'THREAD_TRACE_FLUSH', 55: 'THREAD_TRACE_FINISH', 56: 'PIXEL_PIPE_STAT_CONTROL', 57: 'PIXEL_PIPE_STAT_DUMP', 58: 'PIXEL_PIPE_STAT_RESET', 59: 'CONTEXT_SUSPEND', 60: 'OFFCHIP_HS_DEALLOC', 61: 'ENABLE_NGG_PIPELINE', 62: 'ENABLE_LEGACY_PIPELINE', 63: 'Reserved_0x3f', } Reserved_0x00 = 0 SAMPLE_STREAMOUTSTATS1 = 1 SAMPLE_STREAMOUTSTATS2 = 2 SAMPLE_STREAMOUTSTATS3 = 3 CACHE_FLUSH_TS = 4 CONTEXT_DONE = 5 CACHE_FLUSH = 6 CS_PARTIAL_FLUSH = 7 VGT_STREAMOUT_SYNC = 8 Reserved_0x09 = 9 VGT_STREAMOUT_RESET = 10 END_OF_PIPE_INCR_DE = 11 END_OF_PIPE_IB_END = 12 RST_PIX_CNT = 13 BREAK_BATCH = 14 VS_PARTIAL_FLUSH = 15 PS_PARTIAL_FLUSH = 16 FLUSH_HS_OUTPUT = 17 FLUSH_DFSM = 18 RESET_TO_LOWEST_VGT = 19 CACHE_FLUSH_AND_INV_TS_EVENT = 20 ZPASS_DONE = 21 CACHE_FLUSH_AND_INV_EVENT = 22 PERFCOUNTER_START = 23 PERFCOUNTER_STOP = 24 PIPELINESTAT_START = 25 PIPELINESTAT_STOP = 26 PERFCOUNTER_SAMPLE = 27 Available_0x1c = 28 Available_0x1d = 29 SAMPLE_PIPELINESTAT = 30 SO_VGTSTREAMOUT_FLUSH = 31 SAMPLE_STREAMOUTSTATS = 32 RESET_VTX_CNT = 33 BLOCK_CONTEXT_DONE = 34 CS_CONTEXT_DONE = 35 VGT_FLUSH = 36 TGID_ROLLOVER = 37 SQ_NON_EVENT = 38 SC_SEND_DB_VPZ = 39 BOTTOM_OF_PIPE_TS = 40 FLUSH_SX_TS = 41 DB_CACHE_FLUSH_AND_INV = 42 FLUSH_AND_INV_DB_DATA_TS = 43 FLUSH_AND_INV_DB_META = 44 FLUSH_AND_INV_CB_DATA_TS = 45 FLUSH_AND_INV_CB_META = 46 CS_DONE = 47 PS_DONE = 48 FLUSH_AND_INV_CB_PIXEL_DATA = 49 SX_CB_RAT_ACK_REQUEST = 50 THREAD_TRACE_START = 51 THREAD_TRACE_STOP = 52 THREAD_TRACE_MARKER = 53 THREAD_TRACE_FLUSH = 54 THREAD_TRACE_FINISH = 55 PIXEL_PIPE_STAT_CONTROL = 56 PIXEL_PIPE_STAT_DUMP = 57 PIXEL_PIPE_STAT_RESET = 58 CONTEXT_SUSPEND = 59 OFFCHIP_HS_DEALLOC = 60 ENABLE_NGG_PIPELINE = 61 ENABLE_LEGACY_PIPELINE = 62 Reserved_0x3f = 63 VGT_EVENT_TYPE = ctypes.c_uint32 # enum # values for enumeration 'VGT_DMA_SWAP_MODE' VGT_DMA_SWAP_MODE__enumvalues = { 0: 'VGT_DMA_SWAP_NONE', 1: 'VGT_DMA_SWAP_16_BIT', 2: 'VGT_DMA_SWAP_32_BIT', 3: 'VGT_DMA_SWAP_WORD', } VGT_DMA_SWAP_NONE = 0 VGT_DMA_SWAP_16_BIT = 1 VGT_DMA_SWAP_32_BIT = 2 VGT_DMA_SWAP_WORD = 3 VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum # values for enumeration 'VGT_INDEX_TYPE_MODE' VGT_INDEX_TYPE_MODE__enumvalues = { 0: 'VGT_INDEX_16', 1: 'VGT_INDEX_32', 2: 'VGT_INDEX_8', } VGT_INDEX_16 = 0 VGT_INDEX_32 = 1 VGT_INDEX_8 = 2 VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum # values for enumeration 'VGT_DMA_BUF_TYPE' VGT_DMA_BUF_TYPE__enumvalues = { 0: 'VGT_DMA_BUF_MEM', 1: 'VGT_DMA_BUF_RING', 2: 'VGT_DMA_BUF_SETUP', 3: 'VGT_DMA_PTR_UPDATE', } VGT_DMA_BUF_MEM = 0 VGT_DMA_BUF_RING = 1 VGT_DMA_BUF_SETUP = 2 VGT_DMA_PTR_UPDATE = 3 VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum # values for enumeration 'VGT_OUTPATH_SELECT' VGT_OUTPATH_SELECT__enumvalues = { 0: 'VGT_OUTPATH_VTX_REUSE', 1: 'VGT_OUTPATH_TESS_EN', 2: 'VGT_OUTPATH_PASSTHRU', 3: 'VGT_OUTPATH_GS_BLOCK', 4: 'VGT_OUTPATH_HS_BLOCK', 5: 'VGT_OUTPATH_PRIM_GEN', } VGT_OUTPATH_VTX_REUSE = 0 VGT_OUTPATH_TESS_EN = 1 VGT_OUTPATH_PASSTHRU = 2 VGT_OUTPATH_GS_BLOCK = 3 VGT_OUTPATH_HS_BLOCK = 4 VGT_OUTPATH_PRIM_GEN = 5 VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum # values for enumeration 'VGT_GRP_PRIM_TYPE' VGT_GRP_PRIM_TYPE__enumvalues = { 0: 'VGT_GRP_3D_POINT', 1: 'VGT_GRP_3D_LINE', 2: 'VGT_GRP_3D_TRI', 3: 'VGT_GRP_3D_RECT', 4: 'VGT_GRP_3D_QUAD', 5: 'VGT_GRP_2D_COPY_RECT_V0', 6: 'VGT_GRP_2D_COPY_RECT_V1', 7: 'VGT_GRP_2D_COPY_RECT_V2', 8: 'VGT_GRP_2D_COPY_RECT_V3', 9: 'VGT_GRP_2D_FILL_RECT', 10: 'VGT_GRP_2D_LINE', 11: 'VGT_GRP_2D_TRI', 12: 'VGT_GRP_PRIM_INDEX_LINE', 13: 'VGT_GRP_PRIM_INDEX_TRI', 14: 'VGT_GRP_PRIM_INDEX_QUAD', 15: 'VGT_GRP_3D_LINE_ADJ', 16: 'VGT_GRP_3D_TRI_ADJ', 17: 'VGT_GRP_3D_PATCH', 18: 'VGT_GRP_2D_RECT', } VGT_GRP_3D_POINT = 0 VGT_GRP_3D_LINE = 1 VGT_GRP_3D_TRI = 2 VGT_GRP_3D_RECT = 3 VGT_GRP_3D_QUAD = 4 VGT_GRP_2D_COPY_RECT_V0 = 5 VGT_GRP_2D_COPY_RECT_V1 = 6 VGT_GRP_2D_COPY_RECT_V2 = 7 VGT_GRP_2D_COPY_RECT_V3 = 8 VGT_GRP_2D_FILL_RECT = 9 VGT_GRP_2D_LINE = 10 VGT_GRP_2D_TRI = 11 VGT_GRP_PRIM_INDEX_LINE = 12 VGT_GRP_PRIM_INDEX_TRI = 13 VGT_GRP_PRIM_INDEX_QUAD = 14 VGT_GRP_3D_LINE_ADJ = 15 VGT_GRP_3D_TRI_ADJ = 16 VGT_GRP_3D_PATCH = 17 VGT_GRP_2D_RECT = 18 VGT_GRP_PRIM_TYPE = ctypes.c_uint32 # enum # values for enumeration 'VGT_GRP_PRIM_ORDER' VGT_GRP_PRIM_ORDER__enumvalues = { 0: 'VGT_GRP_LIST', 1: 'VGT_GRP_STRIP', 2: 'VGT_GRP_FAN', 3: 'VGT_GRP_LOOP', 4: 'VGT_GRP_POLYGON', } VGT_GRP_LIST = 0 VGT_GRP_STRIP = 1 VGT_GRP_FAN = 2 VGT_GRP_LOOP = 3 VGT_GRP_POLYGON = 4 VGT_GRP_PRIM_ORDER = ctypes.c_uint32 # enum # values for enumeration 'VGT_GROUP_CONV_SEL' VGT_GROUP_CONV_SEL__enumvalues = { 0: 'VGT_GRP_INDEX_16', 1: 'VGT_GRP_INDEX_32', 2: 'VGT_GRP_UINT_16', 3: 'VGT_GRP_UINT_32', 4: 'VGT_GRP_SINT_16', 5: 'VGT_GRP_SINT_32', 6: 'VGT_GRP_FLOAT_32', 7: 'VGT_GRP_AUTO_PRIM', 8: 'VGT_GRP_FIX_1_23_TO_FLOAT', } VGT_GRP_INDEX_16 = 0 VGT_GRP_INDEX_32 = 1 VGT_GRP_UINT_16 = 2 VGT_GRP_UINT_32 = 3 VGT_GRP_SINT_16 = 4 VGT_GRP_SINT_32 = 5 VGT_GRP_FLOAT_32 = 6 VGT_GRP_AUTO_PRIM = 7 VGT_GRP_FIX_1_23_TO_FLOAT = 8 VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum # values for enumeration 'VGT_GS_MODE_TYPE' VGT_GS_MODE_TYPE__enumvalues = { 0: 'GS_OFF', 1: 'GS_SCENARIO_A', 2: 'GS_SCENARIO_B', 3: 'GS_SCENARIO_G', 4: 'GS_SCENARIO_C', 5: 'SPRITE_EN', } GS_OFF = 0 GS_SCENARIO_A = 1 GS_SCENARIO_B = 2 GS_SCENARIO_G = 3 GS_SCENARIO_C = 4 SPRITE_EN = 5 VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum # values for enumeration 'VGT_GS_CUT_MODE' VGT_GS_CUT_MODE__enumvalues = { 0: 'GS_CUT_1024', 1: 'GS_CUT_512', 2: 'GS_CUT_256', 3: 'GS_CUT_128', } GS_CUT_1024 = 0 GS_CUT_512 = 1 GS_CUT_256 = 2 GS_CUT_128 = 3 VGT_GS_CUT_MODE = ctypes.c_uint32 # enum # values for enumeration 'VGT_GS_OUTPRIM_TYPE' VGT_GS_OUTPRIM_TYPE__enumvalues = { 0: 'POINTLIST', 1: 'LINESTRIP', 2: 'TRISTRIP', 3: 'RECTLIST', } POINTLIST = 0 LINESTRIP = 1 TRISTRIP = 2 RECTLIST = 3 VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum # values for enumeration 'VGT_CACHE_INVALID_MODE' VGT_CACHE_INVALID_MODE__enumvalues = { 0: 'VC_ONLY', 1: 'TC_ONLY', 2: 'VC_AND_TC', } VC_ONLY = 0 TC_ONLY = 1 VC_AND_TC = 2 VGT_CACHE_INVALID_MODE = ctypes.c_uint32 # enum # values for enumeration 'VGT_TESS_TYPE' VGT_TESS_TYPE__enumvalues = { 0: 'TESS_ISOLINE', 1: 'TESS_TRIANGLE', 2: 'TESS_QUAD', } TESS_ISOLINE = 0 TESS_TRIANGLE = 1 TESS_QUAD = 2 VGT_TESS_TYPE = ctypes.c_uint32 # enum # values for enumeration 'VGT_TESS_PARTITION' VGT_TESS_PARTITION__enumvalues = { 0: 'PART_INTEGER', 1: 'PART_POW2', 2: 'PART_FRAC_ODD', 3: 'PART_FRAC_EVEN', } PART_INTEGER = 0 PART_POW2 = 1 PART_FRAC_ODD = 2 PART_FRAC_EVEN = 3 VGT_TESS_PARTITION = ctypes.c_uint32 # enum # values for enumeration 'VGT_TESS_TOPOLOGY' VGT_TESS_TOPOLOGY__enumvalues = { 0: 'OUTPUT_POINT', 1: 'OUTPUT_LINE', 2: 'OUTPUT_TRIANGLE_CW', 3: 'OUTPUT_TRIANGLE_CCW', } OUTPUT_POINT = 0 OUTPUT_LINE = 1 OUTPUT_TRIANGLE_CW = 2 OUTPUT_TRIANGLE_CCW = 3 VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum # values for enumeration 'VGT_RDREQ_POLICY' VGT_RDREQ_POLICY__enumvalues = { 0: 'VGT_POLICY_LRU', 1: 'VGT_POLICY_STREAM', } VGT_POLICY_LRU = 0 VGT_POLICY_STREAM = 1 VGT_RDREQ_POLICY = ctypes.c_uint32 # enum # values for enumeration 'VGT_DIST_MODE' VGT_DIST_MODE__enumvalues = { 0: 'NO_DIST', 1: 'PATCHES', 2: 'DONUTS', 3: 'TRAPEZOIDS', } NO_DIST = 0 PATCHES = 1 DONUTS = 2 TRAPEZOIDS = 3 VGT_DIST_MODE = ctypes.c_uint32 # enum # values for enumeration 'VGT_STAGES_LS_EN' VGT_STAGES_LS_EN__enumvalues = { 0: 'LS_STAGE_OFF', 1: 'LS_STAGE_ON', 2: 'CS_STAGE_ON', 3: 'RESERVED_LS', } LS_STAGE_OFF = 0 LS_STAGE_ON = 1 CS_STAGE_ON = 2 RESERVED_LS = 3 VGT_STAGES_LS_EN = ctypes.c_uint32 # enum # values for enumeration 'VGT_STAGES_HS_EN' VGT_STAGES_HS_EN__enumvalues = { 0: 'HS_STAGE_OFF', 1: 'HS_STAGE_ON', } HS_STAGE_OFF = 0 HS_STAGE_ON = 1 VGT_STAGES_HS_EN = ctypes.c_uint32 # enum # values for enumeration 'VGT_STAGES_ES_EN' VGT_STAGES_ES_EN__enumvalues = { 0: 'ES_STAGE_OFF', 1: 'ES_STAGE_DS', 2: 'ES_STAGE_REAL', 3: 'RESERVED_ES', } ES_STAGE_OFF = 0 ES_STAGE_DS = 1 ES_STAGE_REAL = 2 RESERVED_ES = 3 VGT_STAGES_ES_EN = ctypes.c_uint32 # enum # values for enumeration 'VGT_STAGES_GS_EN' VGT_STAGES_GS_EN__enumvalues = { 0: 'GS_STAGE_OFF', 1: 'GS_STAGE_ON', } GS_STAGE_OFF = 0 GS_STAGE_ON = 1 VGT_STAGES_GS_EN = ctypes.c_uint32 # enum # values for enumeration 'VGT_STAGES_VS_EN' VGT_STAGES_VS_EN__enumvalues = { 0: 'VS_STAGE_REAL', 1: 'VS_STAGE_DS', 2: 'VS_STAGE_COPY_SHADER', 3: 'RESERVED_VS', } VS_STAGE_REAL = 0 VS_STAGE_DS = 1 VS_STAGE_COPY_SHADER = 2 RESERVED_VS = 3 VGT_STAGES_VS_EN = ctypes.c_uint32 # enum # values for enumeration 'VGT_PERFCOUNT_SELECT' VGT_PERFCOUNT_SELECT__enumvalues = { 0: 'vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE', 1: 'vgt_perf_VGT_SPI_ESVERT_VALID', 2: 'vgt_perf_VGT_SPI_ESVERT_EOV', 3: 'vgt_perf_VGT_SPI_ESVERT_STALLED', 4: 'vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY', 5: 'vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE', 6: 'vgt_perf_VGT_SPI_ESVERT_STATIC', 7: 'vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT', 8: 'vgt_perf_VGT_SPI_ESTHREAD_SEND', 9: 'vgt_perf_VGT_SPI_GSPRIM_VALID', 10: 'vgt_perf_VGT_SPI_GSPRIM_EOV', 11: 'vgt_perf_VGT_SPI_GSPRIM_CONT', 12: 'vgt_perf_VGT_SPI_GSPRIM_STALLED', 13: 'vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY', 14: 'vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE', 15: 'vgt_perf_VGT_SPI_GSPRIM_STATIC', 16: 'vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE', 17: 'vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT', 18: 'vgt_perf_VGT_SPI_GSTHREAD_SEND', 19: 'vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE', 20: 'vgt_perf_VGT_SPI_VSVERT_SEND', 21: 'vgt_perf_VGT_SPI_VSVERT_EOV', 22: 'vgt_perf_VGT_SPI_VSVERT_STALLED', 23: 'vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY', 24: 'vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE', 25: 'vgt_perf_VGT_SPI_VSVERT_STATIC', 26: 'vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT', 27: 'vgt_perf_VGT_SPI_VSTHREAD_SEND', 28: 'vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE', 29: 'vgt_perf_VGT_PA_CLIPV_SEND', 30: 'vgt_perf_VGT_PA_CLIPV_FIRSTVERT', 31: 'vgt_perf_VGT_PA_CLIPV_STALLED', 32: 'vgt_perf_VGT_PA_CLIPV_STARVED_BUSY', 33: 'vgt_perf_VGT_PA_CLIPV_STARVED_IDLE', 34: 'vgt_perf_VGT_PA_CLIPV_STATIC', 35: 'vgt_perf_VGT_PA_CLIPP_SEND', 36: 'vgt_perf_VGT_PA_CLIPP_EOP', 37: 'vgt_perf_VGT_PA_CLIPP_IS_EVENT', 38: 'vgt_perf_VGT_PA_CLIPP_NULL_PRIM', 39: 'vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT', 40: 'vgt_perf_VGT_PA_CLIPP_STALLED', 41: 'vgt_perf_VGT_PA_CLIPP_STARVED_BUSY', 42: 'vgt_perf_VGT_PA_CLIPP_STARVED_IDLE', 43: 'vgt_perf_VGT_PA_CLIPP_STATIC', 44: 'vgt_perf_VGT_PA_CLIPS_SEND', 45: 'vgt_perf_VGT_PA_CLIPS_STALLED', 46: 'vgt_perf_VGT_PA_CLIPS_STARVED_BUSY', 47: 'vgt_perf_VGT_PA_CLIPS_STARVED_IDLE', 48: 'vgt_perf_VGT_PA_CLIPS_STATIC', 49: 'vgt_perf_vsvert_ds_send', 50: 'vgt_perf_vsvert_api_send', 51: 'vgt_perf_hs_tif_stall', 52: 'vgt_perf_hs_input_stall', 53: 'vgt_perf_hs_interface_stall', 54: 'vgt_perf_hs_tfm_stall', 55: 'vgt_perf_te11_starved', 56: 'vgt_perf_gs_event_stall', 57: 'vgt_perf_vgt_pa_clipp_send_not_event', 58: 'vgt_perf_vgt_pa_clipp_valid_prim', 59: 'vgt_perf_reused_es_indices', 60: 'vgt_perf_vs_cache_hits', 61: 'vgt_perf_gs_cache_hits', 62: 'vgt_perf_ds_cache_hits', 63: 'vgt_perf_total_cache_hits', 64: 'vgt_perf_vgt_busy', 65: 'vgt_perf_vgt_gs_busy', 66: 'vgt_perf_esvert_stalled_es_tbl', 67: 'vgt_perf_esvert_stalled_gs_tbl', 68: 'vgt_perf_esvert_stalled_gs_event', 69: 'vgt_perf_esvert_stalled_gsprim', 70: 'vgt_perf_gsprim_stalled_es_tbl', 71: 'vgt_perf_gsprim_stalled_gs_tbl', 72: 'vgt_perf_gsprim_stalled_gs_event', 73: 'vgt_perf_gsprim_stalled_esvert', 74: 'vgt_perf_esthread_stalled_es_rb_full', 75: 'vgt_perf_esthread_stalled_spi_bp', 76: 'vgt_perf_counters_avail_stalled', 77: 'vgt_perf_gs_rb_space_avail_stalled', 78: 'vgt_perf_gs_issue_rtr_stalled', 79: 'vgt_perf_gsthread_stalled', 80: 'vgt_perf_strmout_stalled', 81: 'vgt_perf_wait_for_es_done_stalled', 82: 'vgt_perf_cm_stalled_by_gog', 83: 'vgt_perf_cm_reading_stalled', 84: 'vgt_perf_cm_stalled_by_gsfetch_done', 85: 'vgt_perf_gog_vs_tbl_stalled', 86: 'vgt_perf_gog_out_indx_stalled', 87: 'vgt_perf_gog_out_prim_stalled', 88: 'vgt_perf_waveid_stalled', 89: 'vgt_perf_gog_busy', 90: 'vgt_perf_reused_vs_indices', 91: 'vgt_perf_sclk_reg_vld_event', 92: 'vgt_perf_vs_conflicting_indices', 93: 'vgt_perf_sclk_core_vld_event', 94: 'vgt_perf_hswave_stalled', 95: 'vgt_perf_sclk_gs_vld_event', 96: 'vgt_perf_VGT_SPI_LSVERT_VALID', 97: 'vgt_perf_VGT_SPI_LSVERT_EOV', 98: 'vgt_perf_VGT_SPI_LSVERT_STALLED', 99: 'vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY', 100: 'vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE', 101: 'vgt_perf_VGT_SPI_LSVERT_STATIC', 102: 'vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE', 103: 'vgt_perf_VGT_SPI_LSWAVE_IS_EVENT', 104: 'vgt_perf_VGT_SPI_LSWAVE_SEND', 105: 'vgt_perf_VGT_SPI_HSVERT_VALID', 106: 'vgt_perf_VGT_SPI_HSVERT_EOV', 107: 'vgt_perf_VGT_SPI_HSVERT_STALLED', 108: 'vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY', 109: 'vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE', 110: 'vgt_perf_VGT_SPI_HSVERT_STATIC', 111: 'vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE', 112: 'vgt_perf_VGT_SPI_HSWAVE_IS_EVENT', 113: 'vgt_perf_VGT_SPI_HSWAVE_SEND', 114: 'vgt_perf_ds_prims', 115: 'vgt_perf_ds_RESERVED', 116: 'vgt_perf_ls_thread_groups', 117: 'vgt_perf_hs_thread_groups', 118: 'vgt_perf_es_thread_groups', 119: 'vgt_perf_vs_thread_groups', 120: 'vgt_perf_ls_done_latency', 121: 'vgt_perf_hs_done_latency', 122: 'vgt_perf_es_done_latency', 123: 'vgt_perf_gs_done_latency', 124: 'vgt_perf_vgt_hs_busy', 125: 'vgt_perf_vgt_te11_busy', 126: 'vgt_perf_ls_flush', 127: 'vgt_perf_hs_flush', 128: 'vgt_perf_es_flush', 129: 'vgt_perf_vgt_pa_clipp_eopg', 130: 'vgt_perf_ls_done', 131: 'vgt_perf_hs_done', 132: 'vgt_perf_es_done', 133: 'vgt_perf_gs_done', 134: 'vgt_perf_vsfetch_done', 135: 'vgt_perf_gs_done_received', 136: 'vgt_perf_es_ring_high_water_mark', 137: 'vgt_perf_gs_ring_high_water_mark', 138: 'vgt_perf_vs_table_high_water_mark', 139: 'vgt_perf_hs_tgs_active_high_water_mark', 140: 'vgt_perf_pa_clipp_dealloc', 141: 'vgt_perf_cut_mem_flush_stalled', 142: 'vgt_perf_vsvert_work_received', 143: 'vgt_perf_vgt_pa_clipp_starved_after_work', 144: 'vgt_perf_te11_con_starved_after_work', 145: 'vgt_perf_hs_waiting_on_ls_done_stall', 146: 'vgt_spi_vsvert_valid', } vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0 vgt_perf_VGT_SPI_ESVERT_VALID = 1 vgt_perf_VGT_SPI_ESVERT_EOV = 2 vgt_perf_VGT_SPI_ESVERT_STALLED = 3 vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 4 vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 5 vgt_perf_VGT_SPI_ESVERT_STATIC = 6 vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 7 vgt_perf_VGT_SPI_ESTHREAD_SEND = 8 vgt_perf_VGT_SPI_GSPRIM_VALID = 9 vgt_perf_VGT_SPI_GSPRIM_EOV = 10 vgt_perf_VGT_SPI_GSPRIM_CONT = 11 vgt_perf_VGT_SPI_GSPRIM_STALLED = 12 vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 13 vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 14 vgt_perf_VGT_SPI_GSPRIM_STATIC = 15 vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 16 vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 17 vgt_perf_VGT_SPI_GSTHREAD_SEND = 18 vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 19 vgt_perf_VGT_SPI_VSVERT_SEND = 20 vgt_perf_VGT_SPI_VSVERT_EOV = 21 vgt_perf_VGT_SPI_VSVERT_STALLED = 22 vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 23 vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 24 vgt_perf_VGT_SPI_VSVERT_STATIC = 25 vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 26 vgt_perf_VGT_SPI_VSTHREAD_SEND = 27 vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 28 vgt_perf_VGT_PA_CLIPV_SEND = 29 vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 30 vgt_perf_VGT_PA_CLIPV_STALLED = 31 vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 32 vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 33 vgt_perf_VGT_PA_CLIPV_STATIC = 34 vgt_perf_VGT_PA_CLIPP_SEND = 35 vgt_perf_VGT_PA_CLIPP_EOP = 36 vgt_perf_VGT_PA_CLIPP_IS_EVENT = 37 vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 38 vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 39 vgt_perf_VGT_PA_CLIPP_STALLED = 40 vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 41 vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 42 vgt_perf_VGT_PA_CLIPP_STATIC = 43 vgt_perf_VGT_PA_CLIPS_SEND = 44 vgt_perf_VGT_PA_CLIPS_STALLED = 45 vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 46 vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 47 vgt_perf_VGT_PA_CLIPS_STATIC = 48 vgt_perf_vsvert_ds_send = 49 vgt_perf_vsvert_api_send = 50 vgt_perf_hs_tif_stall = 51 vgt_perf_hs_input_stall = 52 vgt_perf_hs_interface_stall = 53 vgt_perf_hs_tfm_stall = 54 vgt_perf_te11_starved = 55 vgt_perf_gs_event_stall = 56 vgt_perf_vgt_pa_clipp_send_not_event = 57 vgt_perf_vgt_pa_clipp_valid_prim = 58 vgt_perf_reused_es_indices = 59 vgt_perf_vs_cache_hits = 60 vgt_perf_gs_cache_hits = 61 vgt_perf_ds_cache_hits = 62 vgt_perf_total_cache_hits = 63 vgt_perf_vgt_busy = 64 vgt_perf_vgt_gs_busy = 65 vgt_perf_esvert_stalled_es_tbl = 66 vgt_perf_esvert_stalled_gs_tbl = 67 vgt_perf_esvert_stalled_gs_event = 68 vgt_perf_esvert_stalled_gsprim = 69 vgt_perf_gsprim_stalled_es_tbl = 70 vgt_perf_gsprim_stalled_gs_tbl = 71 vgt_perf_gsprim_stalled_gs_event = 72 vgt_perf_gsprim_stalled_esvert = 73 vgt_perf_esthread_stalled_es_rb_full = 74 vgt_perf_esthread_stalled_spi_bp = 75 vgt_perf_counters_avail_stalled = 76 vgt_perf_gs_rb_space_avail_stalled = 77 vgt_perf_gs_issue_rtr_stalled = 78 vgt_perf_gsthread_stalled = 79 vgt_perf_strmout_stalled = 80 vgt_perf_wait_for_es_done_stalled = 81 vgt_perf_cm_stalled_by_gog = 82 vgt_perf_cm_reading_stalled = 83 vgt_perf_cm_stalled_by_gsfetch_done = 84 vgt_perf_gog_vs_tbl_stalled = 85 vgt_perf_gog_out_indx_stalled = 86 vgt_perf_gog_out_prim_stalled = 87 vgt_perf_waveid_stalled = 88 vgt_perf_gog_busy = 89 vgt_perf_reused_vs_indices = 90 vgt_perf_sclk_reg_vld_event = 91 vgt_perf_vs_conflicting_indices = 92 vgt_perf_sclk_core_vld_event = 93 vgt_perf_hswave_stalled = 94 vgt_perf_sclk_gs_vld_event = 95 vgt_perf_VGT_SPI_LSVERT_VALID = 96 vgt_perf_VGT_SPI_LSVERT_EOV = 97 vgt_perf_VGT_SPI_LSVERT_STALLED = 98 vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 99 vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 100 vgt_perf_VGT_SPI_LSVERT_STATIC = 101 vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 102 vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 103 vgt_perf_VGT_SPI_LSWAVE_SEND = 104 vgt_perf_VGT_SPI_HSVERT_VALID = 105 vgt_perf_VGT_SPI_HSVERT_EOV = 106 vgt_perf_VGT_SPI_HSVERT_STALLED = 107 vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 108 vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 109 vgt_perf_VGT_SPI_HSVERT_STATIC = 110 vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 111 vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 112 vgt_perf_VGT_SPI_HSWAVE_SEND = 113 vgt_perf_ds_prims = 114 vgt_perf_ds_RESERVED = 115 vgt_perf_ls_thread_groups = 116 vgt_perf_hs_thread_groups = 117 vgt_perf_es_thread_groups = 118 vgt_perf_vs_thread_groups = 119 vgt_perf_ls_done_latency = 120 vgt_perf_hs_done_latency = 121 vgt_perf_es_done_latency = 122 vgt_perf_gs_done_latency = 123 vgt_perf_vgt_hs_busy = 124 vgt_perf_vgt_te11_busy = 125 vgt_perf_ls_flush = 126 vgt_perf_hs_flush = 127 vgt_perf_es_flush = 128 vgt_perf_vgt_pa_clipp_eopg = 129 vgt_perf_ls_done = 130 vgt_perf_hs_done = 131 vgt_perf_es_done = 132 vgt_perf_gs_done = 133 vgt_perf_vsfetch_done = 134 vgt_perf_gs_done_received = 135 vgt_perf_es_ring_high_water_mark = 136 vgt_perf_gs_ring_high_water_mark = 137 vgt_perf_vs_table_high_water_mark = 138 vgt_perf_hs_tgs_active_high_water_mark = 139 vgt_perf_pa_clipp_dealloc = 140 vgt_perf_cut_mem_flush_stalled = 141 vgt_perf_vsvert_work_received = 142 vgt_perf_vgt_pa_clipp_starved_after_work = 143 vgt_perf_te11_con_starved_after_work = 144 vgt_perf_hs_waiting_on_ls_done_stall = 145 vgt_spi_vsvert_valid = 146 VGT_PERFCOUNT_SELECT = ctypes.c_uint32 # enum # values for enumeration 'IA_PERFCOUNT_SELECT' IA_PERFCOUNT_SELECT__enumvalues = { 0: 'ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE', 1: 'ia_perf_dma_data_fifo_full', 2: 'ia_perf_RESERVED1', 3: 'ia_perf_RESERVED2', 4: 'ia_perf_RESERVED3', 5: 'ia_perf_RESERVED4', 6: 'ia_perf_RESERVED5', 7: 'ia_perf_MC_LAT_BIN_0', 8: 'ia_perf_MC_LAT_BIN_1', 9: 'ia_perf_MC_LAT_BIN_2', 10: 'ia_perf_MC_LAT_BIN_3', 11: 'ia_perf_MC_LAT_BIN_4', 12: 'ia_perf_MC_LAT_BIN_5', 13: 'ia_perf_MC_LAT_BIN_6', 14: 'ia_perf_MC_LAT_BIN_7', 15: 'ia_perf_ia_busy', 16: 'ia_perf_ia_sclk_reg_vld_event', 17: 'ia_perf_RESERVED6', 18: 'ia_perf_ia_sclk_core_vld_event', 19: 'ia_perf_RESERVED7', 20: 'ia_perf_ia_dma_return', 21: 'ia_perf_ia_stalled', 22: 'ia_perf_shift_starved_pipe0_event', 23: 'ia_perf_shift_starved_pipe1_event', } ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0 ia_perf_dma_data_fifo_full = 1 ia_perf_RESERVED1 = 2 ia_perf_RESERVED2 = 3 ia_perf_RESERVED3 = 4 ia_perf_RESERVED4 = 5 ia_perf_RESERVED5 = 6 ia_perf_MC_LAT_BIN_0 = 7 ia_perf_MC_LAT_BIN_1 = 8 ia_perf_MC_LAT_BIN_2 = 9 ia_perf_MC_LAT_BIN_3 = 10 ia_perf_MC_LAT_BIN_4 = 11 ia_perf_MC_LAT_BIN_5 = 12 ia_perf_MC_LAT_BIN_6 = 13 ia_perf_MC_LAT_BIN_7 = 14 ia_perf_ia_busy = 15 ia_perf_ia_sclk_reg_vld_event = 16 ia_perf_RESERVED6 = 17 ia_perf_ia_sclk_core_vld_event = 18 ia_perf_RESERVED7 = 19 ia_perf_ia_dma_return = 20 ia_perf_ia_stalled = 21 ia_perf_shift_starved_pipe0_event = 22 ia_perf_shift_starved_pipe1_event = 23 IA_PERFCOUNT_SELECT = ctypes.c_uint32 # enum # values for enumeration 'WD_PERFCOUNT_SELECT' WD_PERFCOUNT_SELECT__enumvalues = { 0: 'wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE', 1: 'wd_perf_RBIU_DR_FIFO_STARVED', 2: 'wd_perf_RBIU_DR_FIFO_STALLED', 3: 'wd_perf_RBIU_DI_FIFO_STARVED', 4: 'wd_perf_RBIU_DI_FIFO_STALLED', 5: 'wd_perf_wd_busy', 6: 'wd_perf_wd_sclk_reg_vld_event', 7: 'wd_perf_wd_sclk_input_vld_event', 8: 'wd_perf_wd_sclk_core_vld_event', 9: 'wd_perf_wd_stalled', 10: 'wd_perf_inside_tf_bin_0', 11: 'wd_perf_inside_tf_bin_1', 12: 'wd_perf_inside_tf_bin_2', 13: 'wd_perf_inside_tf_bin_3', 14: 'wd_perf_inside_tf_bin_4', 15: 'wd_perf_inside_tf_bin_5', 16: 'wd_perf_inside_tf_bin_6', 17: 'wd_perf_inside_tf_bin_7', 18: 'wd_perf_inside_tf_bin_8', 19: 'wd_perf_tfreq_lat_bin_0', 20: 'wd_perf_tfreq_lat_bin_1', 21: 'wd_perf_tfreq_lat_bin_2', 22: 'wd_perf_tfreq_lat_bin_3', 23: 'wd_perf_tfreq_lat_bin_4', 24: 'wd_perf_tfreq_lat_bin_5', 25: 'wd_perf_tfreq_lat_bin_6', 26: 'wd_perf_tfreq_lat_bin_7', 27: 'wd_starved_on_hs_done', 28: 'wd_perf_se0_hs_done_latency', 29: 'wd_perf_se1_hs_done_latency', 30: 'wd_perf_se2_hs_done_latency', 31: 'wd_perf_se3_hs_done_latency', 32: 'wd_perf_hs_done_se0', 33: 'wd_perf_hs_done_se1', 34: 'wd_perf_hs_done_se2', 35: 'wd_perf_hs_done_se3', 36: 'wd_perf_null_patches', } wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0 wd_perf_RBIU_DR_FIFO_STARVED = 1 wd_perf_RBIU_DR_FIFO_STALLED = 2 wd_perf_RBIU_DI_FIFO_STARVED = 3 wd_perf_RBIU_DI_FIFO_STALLED = 4 wd_perf_wd_busy = 5 wd_perf_wd_sclk_reg_vld_event = 6 wd_perf_wd_sclk_input_vld_event = 7 wd_perf_wd_sclk_core_vld_event = 8 wd_perf_wd_stalled = 9 wd_perf_inside_tf_bin_0 = 10 wd_perf_inside_tf_bin_1 = 11 wd_perf_inside_tf_bin_2 = 12 wd_perf_inside_tf_bin_3 = 13 wd_perf_inside_tf_bin_4 = 14 wd_perf_inside_tf_bin_5 = 15 wd_perf_inside_tf_bin_6 = 16 wd_perf_inside_tf_bin_7 = 17 wd_perf_inside_tf_bin_8 = 18 wd_perf_tfreq_lat_bin_0 = 19 wd_perf_tfreq_lat_bin_1 = 20 wd_perf_tfreq_lat_bin_2 = 21 wd_perf_tfreq_lat_bin_3 = 22 wd_perf_tfreq_lat_bin_4 = 23 wd_perf_tfreq_lat_bin_5 = 24 wd_perf_tfreq_lat_bin_6 = 25 wd_perf_tfreq_lat_bin_7 = 26 wd_starved_on_hs_done = 27 wd_perf_se0_hs_done_latency = 28 wd_perf_se1_hs_done_latency = 29 wd_perf_se2_hs_done_latency = 30 wd_perf_se3_hs_done_latency = 31 wd_perf_hs_done_se0 = 32 wd_perf_hs_done_se1 = 33 wd_perf_hs_done_se2 = 34 wd_perf_hs_done_se3 = 35 wd_perf_null_patches = 36 WD_PERFCOUNT_SELECT = ctypes.c_uint32 # enum # values for enumeration 'WD_IA_DRAW_TYPE' WD_IA_DRAW_TYPE__enumvalues = { 0: 'WD_IA_DRAW_TYPE_DI_MM0', 1: 'WD_IA_DRAW_TYPE_REG_XFER', 2: 'WD_IA_DRAW_TYPE_EVENT_INIT', 3: 'WD_IA_DRAW_TYPE_EVENT_ADDR', 4: 'WD_IA_DRAW_TYPE_MIN_INDX', 5: 'WD_IA_DRAW_TYPE_MAX_INDX', 6: 'WD_IA_DRAW_TYPE_INDX_OFF', 7: 'WD_IA_DRAW_TYPE_IMM_DATA', } WD_IA_DRAW_TYPE_DI_MM0 = 0 WD_IA_DRAW_TYPE_REG_XFER = 1 WD_IA_DRAW_TYPE_EVENT_INIT = 2 WD_IA_DRAW_TYPE_EVENT_ADDR = 3 WD_IA_DRAW_TYPE_MIN_INDX = 4 WD_IA_DRAW_TYPE_MAX_INDX = 5 WD_IA_DRAW_TYPE_INDX_OFF = 6 WD_IA_DRAW_TYPE_IMM_DATA = 7 WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum # values for enumeration 'WD_IA_DRAW_REG_XFER' WD_IA_DRAW_REG_XFER__enumvalues = { 0: 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', 1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', } WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0 WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1 WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum # values for enumeration 'WD_IA_DRAW_SOURCE' WD_IA_DRAW_SOURCE__enumvalues = { 0: 'WD_IA_DRAW_SOURCE_DMA', 1: 'WD_IA_DRAW_SOURCE_IMMD', 2: 'WD_IA_DRAW_SOURCE_AUTO', 3: 'WD_IA_DRAW_SOURCE_OPAQ', } WD_IA_DRAW_SOURCE_DMA = 0 WD_IA_DRAW_SOURCE_IMMD = 1 WD_IA_DRAW_SOURCE_AUTO = 2 WD_IA_DRAW_SOURCE_OPAQ = 3 WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum # values for enumeration 'GB_EDC_DED_MODE' GB_EDC_DED_MODE__enumvalues = { 0: 'GB_EDC_DED_MODE_LOG', 1: 'GB_EDC_DED_MODE_HALT', 2: 'GB_EDC_DED_MODE_INT_HALT', } GB_EDC_DED_MODE_LOG = 0 GB_EDC_DED_MODE_HALT = 1 GB_EDC_DED_MODE_INT_HALT = 2 GB_EDC_DED_MODE = ctypes.c_uint32 # enum # values for enumeration 'TA_TC_ADDR_MODES' TA_TC_ADDR_MODES__enumvalues = { 0: 'TA_TC_ADDR_MODE_DEFAULT', 1: 'TA_TC_ADDR_MODE_COMP0', 2: 'TA_TC_ADDR_MODE_COMP1', 3: 'TA_TC_ADDR_MODE_COMP2', 4: 'TA_TC_ADDR_MODE_COMP3', 5: 'TA_TC_ADDR_MODE_UNALIGNED', 6: 'TA_TC_ADDR_MODE_BORDER_COLOR', } TA_TC_ADDR_MODE_DEFAULT = 0 TA_TC_ADDR_MODE_COMP0 = 1 TA_TC_ADDR_MODE_COMP1 = 2 TA_TC_ADDR_MODE_COMP2 = 3 TA_TC_ADDR_MODE_COMP3 = 4 TA_TC_ADDR_MODE_UNALIGNED = 5 TA_TC_ADDR_MODE_BORDER_COLOR = 6 TA_TC_ADDR_MODES = ctypes.c_uint32 # enum # values for enumeration 'TA_PERFCOUNT_SEL' TA_PERFCOUNT_SEL__enumvalues = { 0: 'TA_PERF_SEL_NULL', 1: 'TA_PERF_SEL_sh_fifo_busy', 2: 'TA_PERF_SEL_sh_fifo_cmd_busy', 3: 'TA_PERF_SEL_sh_fifo_addr_busy', 4: 'TA_PERF_SEL_sh_fifo_data_busy', 5: 'TA_PERF_SEL_sh_fifo_data_sfifo_busy', 6: 'TA_PERF_SEL_sh_fifo_data_tfifo_busy', 7: 'TA_PERF_SEL_gradient_busy', 8: 'TA_PERF_SEL_gradient_fifo_busy', 9: 'TA_PERF_SEL_lod_busy', 10: 'TA_PERF_SEL_lod_fifo_busy', 11: 'TA_PERF_SEL_addresser_busy', 12: 'TA_PERF_SEL_addresser_fifo_busy', 13: 'TA_PERF_SEL_aligner_busy', 14: 'TA_PERF_SEL_write_path_busy', 15: 'TA_PERF_SEL_ta_busy', 16: 'TA_PERF_SEL_sq_ta_cmd_cycles', 17: 'TA_PERF_SEL_sp_ta_addr_cycles', 18: 'TA_PERF_SEL_sp_ta_data_cycles', 19: 'TA_PERF_SEL_ta_fa_data_state_cycles', 20: 'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles', 21: 'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles', 22: 'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles', 23: 'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles', 24: 'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles', 25: 'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles', 26: 'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles', 27: 'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles', 28: 'TA_PERF_SEL_RESERVED_28', 29: 'TA_PERF_SEL_RESERVED_29', 30: 'TA_PERF_SEL_sh_fifo_addr_cycles', 31: 'TA_PERF_SEL_sh_fifo_data_cycles', 32: 'TA_PERF_SEL_total_wavefronts', 33: 'TA_PERF_SEL_gradient_cycles', 34: 'TA_PERF_SEL_walker_cycles', 35: 'TA_PERF_SEL_aligner_cycles', 36: 'TA_PERF_SEL_image_wavefronts', 37: 'TA_PERF_SEL_image_read_wavefronts', 38: 'TA_PERF_SEL_image_write_wavefronts', 39: 'TA_PERF_SEL_image_atomic_wavefronts', 40: 'TA_PERF_SEL_image_total_cycles', 41: 'TA_PERF_SEL_RESERVED_41', 42: 'TA_PERF_SEL_RESERVED_42', 43: 'TA_PERF_SEL_RESERVED_43', 44: 'TA_PERF_SEL_buffer_wavefronts', 45: 'TA_PERF_SEL_buffer_read_wavefronts', 46: 'TA_PERF_SEL_buffer_write_wavefronts', 47: 'TA_PERF_SEL_buffer_atomic_wavefronts', 48: 'TA_PERF_SEL_buffer_coalescable_wavefronts', 49: 'TA_PERF_SEL_buffer_total_cycles', 50: 'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles', 51: 'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles', 52: 'TA_PERF_SEL_buffer_coalesced_read_cycles', 53: 'TA_PERF_SEL_buffer_coalesced_write_cycles', 54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles', 55: 'TA_PERF_SEL_addr_stalled_by_td_cycles', 56: 'TA_PERF_SEL_data_stalled_by_tc_cycles', 57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', 58: 'TA_PERF_SEL_addresser_stalled_cycles', 59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', 60: 'TA_PERF_SEL_aniso_stalled_cycles', 61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', 62: 'TA_PERF_SEL_deriv_stalled_cycles', 63: 'TA_PERF_SEL_aniso_gt1_cycle_quads', 64: 'TA_PERF_SEL_color_1_cycle_pixels', 65: 'TA_PERF_SEL_color_2_cycle_pixels', 66: 'TA_PERF_SEL_color_3_cycle_pixels', 67: 'TA_PERF_SEL_color_4_cycle_pixels', 68: 'TA_PERF_SEL_mip_1_cycle_pixels', 69: 'TA_PERF_SEL_mip_2_cycle_pixels', 70: 'TA_PERF_SEL_vol_1_cycle_pixels', 71: 'TA_PERF_SEL_vol_2_cycle_pixels', 72: 'TA_PERF_SEL_bilin_point_1_cycle_pixels', 73: 'TA_PERF_SEL_mipmap_lod_0_samples', 74: 'TA_PERF_SEL_mipmap_lod_1_samples', 75: 'TA_PERF_SEL_mipmap_lod_2_samples', 76: 'TA_PERF_SEL_mipmap_lod_3_samples', 77: 'TA_PERF_SEL_mipmap_lod_4_samples', 78: 'TA_PERF_SEL_mipmap_lod_5_samples', 79: 'TA_PERF_SEL_mipmap_lod_6_samples', 80: 'TA_PERF_SEL_mipmap_lod_7_samples', 81: 'TA_PERF_SEL_mipmap_lod_8_samples', 82: 'TA_PERF_SEL_mipmap_lod_9_samples', 83: 'TA_PERF_SEL_mipmap_lod_10_samples', 84: 'TA_PERF_SEL_mipmap_lod_11_samples', 85: 'TA_PERF_SEL_mipmap_lod_12_samples', 86: 'TA_PERF_SEL_mipmap_lod_13_samples', 87: 'TA_PERF_SEL_mipmap_lod_14_samples', 88: 'TA_PERF_SEL_mipmap_invalid_samples', 89: 'TA_PERF_SEL_aniso_1_cycle_quads', 90: 'TA_PERF_SEL_aniso_2_cycle_quads', 91: 'TA_PERF_SEL_aniso_4_cycle_quads', 92: 'TA_PERF_SEL_aniso_6_cycle_quads', 93: 'TA_PERF_SEL_aniso_8_cycle_quads', 94: 'TA_PERF_SEL_aniso_10_cycle_quads', 95: 'TA_PERF_SEL_aniso_12_cycle_quads', 96: 'TA_PERF_SEL_aniso_14_cycle_quads', 97: 'TA_PERF_SEL_aniso_16_cycle_quads', 98: 'TA_PERF_SEL_write_path_input_cycles', 99: 'TA_PERF_SEL_write_path_output_cycles', 100: 'TA_PERF_SEL_flat_wavefronts', 101: 'TA_PERF_SEL_flat_read_wavefronts', 102: 'TA_PERF_SEL_flat_write_wavefronts', 103: 'TA_PERF_SEL_flat_atomic_wavefronts', 104: 'TA_PERF_SEL_flat_coalesceable_wavefronts', 105: 'TA_PERF_SEL_reg_sclk_vld', 106: 'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en', 107: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en', 108: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en', 109: 'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en', 110: 'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en', 111: 'TA_PERF_SEL_xnack_on_phase0', 112: 'TA_PERF_SEL_xnack_on_phase1', 113: 'TA_PERF_SEL_xnack_on_phase2', 114: 'TA_PERF_SEL_xnack_on_phase3', 115: 'TA_PERF_SEL_first_xnack_on_phase0', 116: 'TA_PERF_SEL_first_xnack_on_phase1', 117: 'TA_PERF_SEL_first_xnack_on_phase2', 118: 'TA_PERF_SEL_first_xnack_on_phase3', } TA_PERF_SEL_NULL = 0 TA_PERF_SEL_sh_fifo_busy = 1 TA_PERF_SEL_sh_fifo_cmd_busy = 2 TA_PERF_SEL_sh_fifo_addr_busy = 3 TA_PERF_SEL_sh_fifo_data_busy = 4 TA_PERF_SEL_sh_fifo_data_sfifo_busy = 5 TA_PERF_SEL_sh_fifo_data_tfifo_busy = 6 TA_PERF_SEL_gradient_busy = 7 TA_PERF_SEL_gradient_fifo_busy = 8 TA_PERF_SEL_lod_busy = 9 TA_PERF_SEL_lod_fifo_busy = 10 TA_PERF_SEL_addresser_busy = 11 TA_PERF_SEL_addresser_fifo_busy = 12 TA_PERF_SEL_aligner_busy = 13 TA_PERF_SEL_write_path_busy = 14 TA_PERF_SEL_ta_busy = 15 TA_PERF_SEL_sq_ta_cmd_cycles = 16 TA_PERF_SEL_sp_ta_addr_cycles = 17 TA_PERF_SEL_sp_ta_data_cycles = 18 TA_PERF_SEL_ta_fa_data_state_cycles = 19 TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 20 TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 21 TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 22 TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 23 TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 24 TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 25 TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 26 TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 27 TA_PERF_SEL_RESERVED_28 = 28 TA_PERF_SEL_RESERVED_29 = 29 TA_PERF_SEL_sh_fifo_addr_cycles = 30 TA_PERF_SEL_sh_fifo_data_cycles = 31 TA_PERF_SEL_total_wavefronts = 32 TA_PERF_SEL_gradient_cycles = 33 TA_PERF_SEL_walker_cycles = 34 TA_PERF_SEL_aligner_cycles = 35 TA_PERF_SEL_image_wavefronts = 36 TA_PERF_SEL_image_read_wavefronts = 37 TA_PERF_SEL_image_write_wavefronts = 38 TA_PERF_SEL_image_atomic_wavefronts = 39 TA_PERF_SEL_image_total_cycles = 40 TA_PERF_SEL_RESERVED_41 = 41 TA_PERF_SEL_RESERVED_42 = 42 TA_PERF_SEL_RESERVED_43 = 43 TA_PERF_SEL_buffer_wavefronts = 44 TA_PERF_SEL_buffer_read_wavefronts = 45 TA_PERF_SEL_buffer_write_wavefronts = 46 TA_PERF_SEL_buffer_atomic_wavefronts = 47 TA_PERF_SEL_buffer_coalescable_wavefronts = 48 TA_PERF_SEL_buffer_total_cycles = 49 TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 50 TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 51 TA_PERF_SEL_buffer_coalesced_read_cycles = 52 TA_PERF_SEL_buffer_coalesced_write_cycles = 53 TA_PERF_SEL_addr_stalled_by_tc_cycles = 54 TA_PERF_SEL_addr_stalled_by_td_cycles = 55 TA_PERF_SEL_data_stalled_by_tc_cycles = 56 TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57 TA_PERF_SEL_addresser_stalled_cycles = 58 TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59 TA_PERF_SEL_aniso_stalled_cycles = 60 TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61 TA_PERF_SEL_deriv_stalled_cycles = 62 TA_PERF_SEL_aniso_gt1_cycle_quads = 63 TA_PERF_SEL_color_1_cycle_pixels = 64 TA_PERF_SEL_color_2_cycle_pixels = 65 TA_PERF_SEL_color_3_cycle_pixels = 66 TA_PERF_SEL_color_4_cycle_pixels = 67 TA_PERF_SEL_mip_1_cycle_pixels = 68 TA_PERF_SEL_mip_2_cycle_pixels = 69 TA_PERF_SEL_vol_1_cycle_pixels = 70 TA_PERF_SEL_vol_2_cycle_pixels = 71 TA_PERF_SEL_bilin_point_1_cycle_pixels = 72 TA_PERF_SEL_mipmap_lod_0_samples = 73 TA_PERF_SEL_mipmap_lod_1_samples = 74 TA_PERF_SEL_mipmap_lod_2_samples = 75 TA_PERF_SEL_mipmap_lod_3_samples = 76 TA_PERF_SEL_mipmap_lod_4_samples = 77 TA_PERF_SEL_mipmap_lod_5_samples = 78 TA_PERF_SEL_mipmap_lod_6_samples = 79 TA_PERF_SEL_mipmap_lod_7_samples = 80 TA_PERF_SEL_mipmap_lod_8_samples = 81 TA_PERF_SEL_mipmap_lod_9_samples = 82 TA_PERF_SEL_mipmap_lod_10_samples = 83 TA_PERF_SEL_mipmap_lod_11_samples = 84 TA_PERF_SEL_mipmap_lod_12_samples = 85 TA_PERF_SEL_mipmap_lod_13_samples = 86 TA_PERF_SEL_mipmap_lod_14_samples = 87 TA_PERF_SEL_mipmap_invalid_samples = 88 TA_PERF_SEL_aniso_1_cycle_quads = 89 TA_PERF_SEL_aniso_2_cycle_quads = 90 TA_PERF_SEL_aniso_4_cycle_quads = 91 TA_PERF_SEL_aniso_6_cycle_quads = 92 TA_PERF_SEL_aniso_8_cycle_quads = 93 TA_PERF_SEL_aniso_10_cycle_quads = 94 TA_PERF_SEL_aniso_12_cycle_quads = 95 TA_PERF_SEL_aniso_14_cycle_quads = 96 TA_PERF_SEL_aniso_16_cycle_quads = 97 TA_PERF_SEL_write_path_input_cycles = 98 TA_PERF_SEL_write_path_output_cycles = 99 TA_PERF_SEL_flat_wavefronts = 100 TA_PERF_SEL_flat_read_wavefronts = 101 TA_PERF_SEL_flat_write_wavefronts = 102 TA_PERF_SEL_flat_atomic_wavefronts = 103 TA_PERF_SEL_flat_coalesceable_wavefronts = 104 TA_PERF_SEL_reg_sclk_vld = 105 TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 106 TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 107 TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 108 TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 109 TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 110 TA_PERF_SEL_xnack_on_phase0 = 111 TA_PERF_SEL_xnack_on_phase1 = 112 TA_PERF_SEL_xnack_on_phase2 = 113 TA_PERF_SEL_xnack_on_phase3 = 114 TA_PERF_SEL_first_xnack_on_phase0 = 115 TA_PERF_SEL_first_xnack_on_phase1 = 116 TA_PERF_SEL_first_xnack_on_phase2 = 117 TA_PERF_SEL_first_xnack_on_phase3 = 118 TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum # values for enumeration 'TD_PERFCOUNT_SEL' TD_PERFCOUNT_SEL__enumvalues = { 0: 'TD_PERF_SEL_none', 1: 'TD_PERF_SEL_td_busy', 2: 'TD_PERF_SEL_input_busy', 3: 'TD_PERF_SEL_output_busy', 4: 'TD_PERF_SEL_lerp_busy', 5: 'TD_PERF_SEL_reg_sclk_vld', 6: 'TD_PERF_SEL_local_cg_dyn_sclk_grp0_en', 7: 'TD_PERF_SEL_local_cg_dyn_sclk_grp1_en', 8: 'TD_PERF_SEL_local_cg_dyn_sclk_grp4_en', 9: 'TD_PERF_SEL_local_cg_dyn_sclk_grp5_en', 10: 'TD_PERF_SEL_tc_td_fifo_full', 11: 'TD_PERF_SEL_constant_state_full', 12: 'TD_PERF_SEL_sample_state_full', 13: 'TD_PERF_SEL_output_fifo_full', 14: 'TD_PERF_SEL_RESERVED_14', 15: 'TD_PERF_SEL_tc_stall', 16: 'TD_PERF_SEL_pc_stall', 17: 'TD_PERF_SEL_gds_stall', 18: 'TD_PERF_SEL_RESERVED_18', 19: 'TD_PERF_SEL_RESERVED_19', 20: 'TD_PERF_SEL_gather4_wavefront', 21: 'TD_PERF_SEL_gather4h_wavefront', 22: 'TD_PERF_SEL_gather4h_packed_wavefront', 23: 'TD_PERF_SEL_gather8h_packed_wavefront', 24: 'TD_PERF_SEL_sample_c_wavefront', 25: 'TD_PERF_SEL_load_wavefront', 26: 'TD_PERF_SEL_atomic_wavefront', 27: 'TD_PERF_SEL_store_wavefront', 28: 'TD_PERF_SEL_ldfptr_wavefront', 29: 'TD_PERF_SEL_d16_en_wavefront', 30: 'TD_PERF_SEL_bypass_filter_wavefront', 31: 'TD_PERF_SEL_min_max_filter_wavefront', 32: 'TD_PERF_SEL_coalescable_wavefront', 33: 'TD_PERF_SEL_coalesced_phase', 34: 'TD_PERF_SEL_four_phase_wavefront', 35: 'TD_PERF_SEL_eight_phase_wavefront', 36: 'TD_PERF_SEL_sixteen_phase_wavefront', 37: 'TD_PERF_SEL_four_phase_forward_wavefront', 38: 'TD_PERF_SEL_write_ack_wavefront', 39: 'TD_PERF_SEL_RESERVED_39', 40: 'TD_PERF_SEL_user_defined_border', 41: 'TD_PERF_SEL_white_border', 42: 'TD_PERF_SEL_opaque_black_border', 43: 'TD_PERF_SEL_RESERVED_43', 44: 'TD_PERF_SEL_RESERVED_44', 45: 'TD_PERF_SEL_nack', 46: 'TD_PERF_SEL_td_sp_traffic', 47: 'TD_PERF_SEL_consume_gds_traffic', 48: 'TD_PERF_SEL_addresscmd_poison', 49: 'TD_PERF_SEL_data_poison', 50: 'TD_PERF_SEL_start_cycle_0', 51: 'TD_PERF_SEL_start_cycle_1', 52: 'TD_PERF_SEL_start_cycle_2', 53: 'TD_PERF_SEL_start_cycle_3', 54: 'TD_PERF_SEL_null_cycle_output', 55: 'TD_PERF_SEL_d16_data_packed', 56: 'TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt', } TD_PERF_SEL_none = 0 TD_PERF_SEL_td_busy = 1 TD_PERF_SEL_input_busy = 2 TD_PERF_SEL_output_busy = 3 TD_PERF_SEL_lerp_busy = 4 TD_PERF_SEL_reg_sclk_vld = 5 TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 6 TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 7 TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 8 TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 9 TD_PERF_SEL_tc_td_fifo_full = 10 TD_PERF_SEL_constant_state_full = 11 TD_PERF_SEL_sample_state_full = 12 TD_PERF_SEL_output_fifo_full = 13 TD_PERF_SEL_RESERVED_14 = 14 TD_PERF_SEL_tc_stall = 15 TD_PERF_SEL_pc_stall = 16 TD_PERF_SEL_gds_stall = 17 TD_PERF_SEL_RESERVED_18 = 18 TD_PERF_SEL_RESERVED_19 = 19 TD_PERF_SEL_gather4_wavefront = 20 TD_PERF_SEL_gather4h_wavefront = 21 TD_PERF_SEL_gather4h_packed_wavefront = 22 TD_PERF_SEL_gather8h_packed_wavefront = 23 TD_PERF_SEL_sample_c_wavefront = 24 TD_PERF_SEL_load_wavefront = 25 TD_PERF_SEL_atomic_wavefront = 26 TD_PERF_SEL_store_wavefront = 27 TD_PERF_SEL_ldfptr_wavefront = 28 TD_PERF_SEL_d16_en_wavefront = 29 TD_PERF_SEL_bypass_filter_wavefront = 30 TD_PERF_SEL_min_max_filter_wavefront = 31 TD_PERF_SEL_coalescable_wavefront = 32 TD_PERF_SEL_coalesced_phase = 33 TD_PERF_SEL_four_phase_wavefront = 34 TD_PERF_SEL_eight_phase_wavefront = 35 TD_PERF_SEL_sixteen_phase_wavefront = 36 TD_PERF_SEL_four_phase_forward_wavefront = 37 TD_PERF_SEL_write_ack_wavefront = 38 TD_PERF_SEL_RESERVED_39 = 39 TD_PERF_SEL_user_defined_border = 40 TD_PERF_SEL_white_border = 41 TD_PERF_SEL_opaque_black_border = 42 TD_PERF_SEL_RESERVED_43 = 43 TD_PERF_SEL_RESERVED_44 = 44 TD_PERF_SEL_nack = 45 TD_PERF_SEL_td_sp_traffic = 46 TD_PERF_SEL_consume_gds_traffic = 47 TD_PERF_SEL_addresscmd_poison = 48 TD_PERF_SEL_data_poison = 49 TD_PERF_SEL_start_cycle_0 = 50 TD_PERF_SEL_start_cycle_1 = 51 TD_PERF_SEL_start_cycle_2 = 52 TD_PERF_SEL_start_cycle_3 = 53 TD_PERF_SEL_null_cycle_output = 54 TD_PERF_SEL_d16_data_packed = 55 TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt = 56 TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum # values for enumeration 'TCP_PERFCOUNT_SELECT' TCP_PERFCOUNT_SELECT__enumvalues = { 0: 'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES', 1: 'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES', 2: 'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES', 3: 'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES', 4: 'TCP_PERF_SEL_TD_TCP_STALL_CYCLES', 5: 'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES', 6: 'TCP_PERF_SEL_LOD_STALL_CYCLES', 7: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES', 8: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES', 9: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES', 10: 'TCP_PERF_SEL_ALLOC_STALL_CYCLES', 11: 'TCP_PERF_SEL_LFIFO_STALL_CYCLES', 12: 'TCP_PERF_SEL_RFIFO_STALL_CYCLES', 13: 'TCP_PERF_SEL_TCR_RDRET_STALL', 14: 'TCP_PERF_SEL_WRITE_CONFLICT_STALL', 15: 'TCP_PERF_SEL_HOLE_READ_STALL', 16: 'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES', 17: 'TCP_PERF_SEL_PENDING_STALL_CYCLES', 18: 'TCP_PERF_SEL_READFIFO_STALL_CYCLES', 19: 'TCP_PERF_SEL_TCP_LATENCY', 20: 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY', 21: 'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY', 22: 'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY', 23: 'TCP_PERF_SEL_TCC_READ_REQ', 24: 'TCP_PERF_SEL_TCC_WRITE_REQ', 25: 'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ', 26: 'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ', 27: 'TCP_PERF_SEL_TOTAL_LOCAL_READ', 28: 'TCP_PERF_SEL_TOTAL_GLOBAL_READ', 29: 'TCP_PERF_SEL_TOTAL_LOCAL_WRITE', 30: 'TCP_PERF_SEL_TOTAL_GLOBAL_WRITE', 31: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET', 32: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET', 33: 'TCP_PERF_SEL_TOTAL_WBINVL1', 34: 'TCP_PERF_SEL_IMG_READ_FMT_1', 35: 'TCP_PERF_SEL_IMG_READ_FMT_8', 36: 'TCP_PERF_SEL_IMG_READ_FMT_16', 37: 'TCP_PERF_SEL_IMG_READ_FMT_32', 38: 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_8', 39: 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_16', 40: 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_128', 41: 'TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE', 42: 'TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE', 43: 'TCP_PERF_SEL_IMG_READ_FMT_96', 44: 'TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE', 45: 'TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE', 46: 'TCP_PERF_SEL_IMG_READ_FMT_BC1', 47: 'TCP_PERF_SEL_IMG_READ_FMT_BC2', 48: 'TCP_PERF_SEL_IMG_READ_FMT_BC3', 49: 'TCP_PERF_SEL_IMG_READ_FMT_BC4', 50: 'TCP_PERF_SEL_IMG_READ_FMT_BC5', 51: 'TCP_PERF_SEL_IMG_READ_FMT_BC6', 52: 'TCP_PERF_SEL_IMG_READ_FMT_BC7', 53: 'TCP_PERF_SEL_IMG_READ_FMT_I8', 54: 'TCP_PERF_SEL_IMG_READ_FMT_I16', 55: 'TCP_PERF_SEL_IMG_READ_FMT_I32', 56: 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8', 57: 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16', 58: 'TCP_PERF_SEL_IMG_READ_FMT_D8', 59: 'TCP_PERF_SEL_IMG_READ_FMT_D16', 60: 'TCP_PERF_SEL_IMG_READ_FMT_D32', 61: 'TCP_PERF_SEL_IMG_WRITE_FMT_8', 62: 'TCP_PERF_SEL_IMG_WRITE_FMT_16', 63: 'TCP_PERF_SEL_IMG_WRITE_FMT_32', 64: 'TCP_PERF_SEL_IMG_WRITE_FMT_64', 65: 'TCP_PERF_SEL_IMG_WRITE_FMT_128', 66: 'TCP_PERF_SEL_IMG_WRITE_FMT_D8', 67: 'TCP_PERF_SEL_IMG_WRITE_FMT_D16', 68: 'TCP_PERF_SEL_IMG_WRITE_FMT_D32', 69: 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32', 70: 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32', 71: 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64', 72: 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64', 73: 'TCP_PERF_SEL_BUF_READ_FMT_8', 74: 'TCP_PERF_SEL_BUF_READ_FMT_16', 75: 'TCP_PERF_SEL_BUF_READ_FMT_32', 76: 'TCP_PERF_SEL_BUF_WRITE_FMT_8', 77: 'TCP_PERF_SEL_BUF_WRITE_FMT_16', 78: 'TCP_PERF_SEL_BUF_WRITE_FMT_32', 79: 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32', 80: 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32', 81: 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64', 82: 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64', 83: 'TCP_PERF_SEL_ARR_LINEAR_GENERAL', 84: 'TCP_PERF_SEL_ARR_LINEAR_ALIGNED', 85: 'TCP_PERF_SEL_ARR_1D_THIN1', 86: 'TCP_PERF_SEL_ARR_1D_THICK', 87: 'TCP_PERF_SEL_ARR_2D_THIN1', 88: 'TCP_PERF_SEL_ARR_2D_THICK', 89: 'TCP_PERF_SEL_ARR_2D_XTHICK', 90: 'TCP_PERF_SEL_ARR_3D_THIN1', 91: 'TCP_PERF_SEL_ARR_3D_THICK', 92: 'TCP_PERF_SEL_ARR_3D_XTHICK', 93: 'TCP_PERF_SEL_DIM_1D', 94: 'TCP_PERF_SEL_DIM_2D', 95: 'TCP_PERF_SEL_DIM_3D', 96: 'TCP_PERF_SEL_DIM_1D_ARRAY', 97: 'TCP_PERF_SEL_DIM_2D_ARRAY', 98: 'TCP_PERF_SEL_DIM_2D_MSAA', 99: 'TCP_PERF_SEL_DIM_2D_ARRAY_MSAA', 100: 'TCP_PERF_SEL_DIM_CUBE_ARRAY', 101: 'TCP_PERF_SEL_CP_TCP_INVALIDATE', 102: 'TCP_PERF_SEL_TA_TCP_STATE_READ', 103: 'TCP_PERF_SEL_TAGRAM0_REQ', 104: 'TCP_PERF_SEL_TAGRAM1_REQ', 105: 'TCP_PERF_SEL_TAGRAM2_REQ', 106: 'TCP_PERF_SEL_TAGRAM3_REQ', 107: 'TCP_PERF_SEL_GATE_EN1', 108: 'TCP_PERF_SEL_GATE_EN2', 109: 'TCP_PERF_SEL_CORE_REG_SCLK_VLD', 110: 'TCP_PERF_SEL_TCC_REQ', 111: 'TCP_PERF_SEL_TCC_NON_READ_REQ', 112: 'TCP_PERF_SEL_TCC_BYPASS_READ_REQ', 113: 'TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ', 114: 'TCP_PERF_SEL_TCC_VOLATILE_READ_REQ', 115: 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ', 116: 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ', 117: 'TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ', 118: 'TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ', 119: 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ', 120: 'TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ', 121: 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ', 122: 'TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ', 123: 'TCP_PERF_SEL_TCC_ATOMIC_REQ', 124: 'TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ', 125: 'TCP_PERF_SEL_TCC_DATA_BUS_BUSY', 126: 'TCP_PERF_SEL_TOTAL_ACCESSES', 127: 'TCP_PERF_SEL_TOTAL_READ', 128: 'TCP_PERF_SEL_TOTAL_HIT_LRU_READ', 129: 'TCP_PERF_SEL_TOTAL_HIT_EVICT_READ', 130: 'TCP_PERF_SEL_TOTAL_MISS_LRU_READ', 131: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ', 132: 'TCP_PERF_SEL_TOTAL_NON_READ', 133: 'TCP_PERF_SEL_TOTAL_WRITE', 134: 'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE', 135: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE', 136: 'TCP_PERF_SEL_TOTAL_WBINVL1_VOL', 137: 'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES', 138: 'TCP_PERF_SEL_DISPLAY_MICROTILING', 139: 'TCP_PERF_SEL_THIN_MICROTILING', 140: 'TCP_PERF_SEL_DEPTH_MICROTILING', 141: 'TCP_PERF_SEL_ARR_PRT_THIN1', 142: 'TCP_PERF_SEL_ARR_PRT_2D_THIN1', 143: 'TCP_PERF_SEL_ARR_PRT_3D_THIN1', 144: 'TCP_PERF_SEL_ARR_PRT_THICK', 145: 'TCP_PERF_SEL_ARR_PRT_2D_THICK', 146: 'TCP_PERF_SEL_ARR_PRT_3D_THICK', 147: 'TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL', 148: 'TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL', 149: 'TCP_PERF_SEL_UNALIGNED', 150: 'TCP_PERF_SEL_ROTATED_MICROTILING', 151: 'TCP_PERF_SEL_THICK_MICROTILING', 152: 'TCP_PERF_SEL_ATC', 153: 'TCP_PERF_SEL_POWER_STALL', 154: 'TCP_PERF_SEL_RESERVED_154', 155: 'TCP_PERF_SEL_TCC_LRU_REQ', 156: 'TCP_PERF_SEL_TCC_STREAM_REQ', 157: 'TCP_PERF_SEL_TCC_NC_READ_REQ', 158: 'TCP_PERF_SEL_TCC_NC_WRITE_REQ', 159: 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ', 160: 'TCP_PERF_SEL_TCC_UC_READ_REQ', 161: 'TCP_PERF_SEL_TCC_UC_WRITE_REQ', 162: 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ', 163: 'TCP_PERF_SEL_TCC_CC_READ_REQ', 164: 'TCP_PERF_SEL_TCC_CC_WRITE_REQ', 165: 'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ', 166: 'TCP_PERF_SEL_TCC_DCC_REQ', 167: 'TCP_PERF_SEL_TCC_PHYSICAL_REQ', 168: 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', 169: 'TCP_PERF_SEL_VOLATILE', 170: 'TCP_PERF_SEL_TC_TA_XNACK_STALL', 171: 'TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL', 172: 'TCP_PERF_SEL_SHOOTDOWN', 173: 'TCP_PERF_SEL_UTCL1_TRANSLATION_MISS', 174: 'TCP_PERF_SEL_UTCL1_PERMISSION_MISS', 175: 'TCP_PERF_SEL_UTCL1_REQUEST', 176: 'TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', 177: 'TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', 178: 'TCP_PERF_SEL_UTCL1_LFIFO_FULL', 179: 'TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', 180: 'TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', 181: 'TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT', 182: 'TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', 183: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB', 184: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA', 185: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1', 186: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_R', 187: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG', 188: 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_32', 189: 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_64', 190: 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_64', 191: 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_128', 192: 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32', 193: 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64', 194: 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64', 195: 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128', } TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0 TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 1 TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 2 TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 3 TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 4 TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 5 TCP_PERF_SEL_LOD_STALL_CYCLES = 6 TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 7 TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 8 TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 9 TCP_PERF_SEL_ALLOC_STALL_CYCLES = 10 TCP_PERF_SEL_LFIFO_STALL_CYCLES = 11 TCP_PERF_SEL_RFIFO_STALL_CYCLES = 12 TCP_PERF_SEL_TCR_RDRET_STALL = 13 TCP_PERF_SEL_WRITE_CONFLICT_STALL = 14 TCP_PERF_SEL_HOLE_READ_STALL = 15 TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 16 TCP_PERF_SEL_PENDING_STALL_CYCLES = 17 TCP_PERF_SEL_READFIFO_STALL_CYCLES = 18 TCP_PERF_SEL_TCP_LATENCY = 19 TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 20 TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 21 TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 22 TCP_PERF_SEL_TCC_READ_REQ = 23 TCP_PERF_SEL_TCC_WRITE_REQ = 24 TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 25 TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 26 TCP_PERF_SEL_TOTAL_LOCAL_READ = 27 TCP_PERF_SEL_TOTAL_GLOBAL_READ = 28 TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 29 TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 30 TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 31 TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 32 TCP_PERF_SEL_TOTAL_WBINVL1 = 33 TCP_PERF_SEL_IMG_READ_FMT_1 = 34 TCP_PERF_SEL_IMG_READ_FMT_8 = 35 TCP_PERF_SEL_IMG_READ_FMT_16 = 36 TCP_PERF_SEL_IMG_READ_FMT_32 = 37 TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 38 TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 39 TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 40 TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 41 TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 42 TCP_PERF_SEL_IMG_READ_FMT_96 = 43 TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 44 TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 45 TCP_PERF_SEL_IMG_READ_FMT_BC1 = 46 TCP_PERF_SEL_IMG_READ_FMT_BC2 = 47 TCP_PERF_SEL_IMG_READ_FMT_BC3 = 48 TCP_PERF_SEL_IMG_READ_FMT_BC4 = 49 TCP_PERF_SEL_IMG_READ_FMT_BC5 = 50 TCP_PERF_SEL_IMG_READ_FMT_BC6 = 51 TCP_PERF_SEL_IMG_READ_FMT_BC7 = 52 TCP_PERF_SEL_IMG_READ_FMT_I8 = 53 TCP_PERF_SEL_IMG_READ_FMT_I16 = 54 TCP_PERF_SEL_IMG_READ_FMT_I32 = 55 TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 56 TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 57 TCP_PERF_SEL_IMG_READ_FMT_D8 = 58 TCP_PERF_SEL_IMG_READ_FMT_D16 = 59 TCP_PERF_SEL_IMG_READ_FMT_D32 = 60 TCP_PERF_SEL_IMG_WRITE_FMT_8 = 61 TCP_PERF_SEL_IMG_WRITE_FMT_16 = 62 TCP_PERF_SEL_IMG_WRITE_FMT_32 = 63 TCP_PERF_SEL_IMG_WRITE_FMT_64 = 64 TCP_PERF_SEL_IMG_WRITE_FMT_128 = 65 TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 66 TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 67 TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 68 TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 69 TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 70 TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 71 TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 72 TCP_PERF_SEL_BUF_READ_FMT_8 = 73 TCP_PERF_SEL_BUF_READ_FMT_16 = 74 TCP_PERF_SEL_BUF_READ_FMT_32 = 75 TCP_PERF_SEL_BUF_WRITE_FMT_8 = 76 TCP_PERF_SEL_BUF_WRITE_FMT_16 = 77 TCP_PERF_SEL_BUF_WRITE_FMT_32 = 78 TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 79 TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 80 TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 81 TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 82 TCP_PERF_SEL_ARR_LINEAR_GENERAL = 83 TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 84 TCP_PERF_SEL_ARR_1D_THIN1 = 85 TCP_PERF_SEL_ARR_1D_THICK = 86 TCP_PERF_SEL_ARR_2D_THIN1 = 87 TCP_PERF_SEL_ARR_2D_THICK = 88 TCP_PERF_SEL_ARR_2D_XTHICK = 89 TCP_PERF_SEL_ARR_3D_THIN1 = 90 TCP_PERF_SEL_ARR_3D_THICK = 91 TCP_PERF_SEL_ARR_3D_XTHICK = 92 TCP_PERF_SEL_DIM_1D = 93 TCP_PERF_SEL_DIM_2D = 94 TCP_PERF_SEL_DIM_3D = 95 TCP_PERF_SEL_DIM_1D_ARRAY = 96 TCP_PERF_SEL_DIM_2D_ARRAY = 97 TCP_PERF_SEL_DIM_2D_MSAA = 98 TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 99 TCP_PERF_SEL_DIM_CUBE_ARRAY = 100 TCP_PERF_SEL_CP_TCP_INVALIDATE = 101 TCP_PERF_SEL_TA_TCP_STATE_READ = 102 TCP_PERF_SEL_TAGRAM0_REQ = 103 TCP_PERF_SEL_TAGRAM1_REQ = 104 TCP_PERF_SEL_TAGRAM2_REQ = 105 TCP_PERF_SEL_TAGRAM3_REQ = 106 TCP_PERF_SEL_GATE_EN1 = 107 TCP_PERF_SEL_GATE_EN2 = 108 TCP_PERF_SEL_CORE_REG_SCLK_VLD = 109 TCP_PERF_SEL_TCC_REQ = 110 TCP_PERF_SEL_TCC_NON_READ_REQ = 111 TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 112 TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 113 TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 114 TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 115 TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 116 TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 117 TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 118 TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 119 TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 120 TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 121 TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 122 TCP_PERF_SEL_TCC_ATOMIC_REQ = 123 TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 124 TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 125 TCP_PERF_SEL_TOTAL_ACCESSES = 126 TCP_PERF_SEL_TOTAL_READ = 127 TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 128 TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 129 TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 130 TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 131 TCP_PERF_SEL_TOTAL_NON_READ = 132 TCP_PERF_SEL_TOTAL_WRITE = 133 TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 134 TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 135 TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 136 TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 137 TCP_PERF_SEL_DISPLAY_MICROTILING = 138 TCP_PERF_SEL_THIN_MICROTILING = 139 TCP_PERF_SEL_DEPTH_MICROTILING = 140 TCP_PERF_SEL_ARR_PRT_THIN1 = 141 TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 142 TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 143 TCP_PERF_SEL_ARR_PRT_THICK = 144 TCP_PERF_SEL_ARR_PRT_2D_THICK = 145 TCP_PERF_SEL_ARR_PRT_3D_THICK = 146 TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 147 TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 148 TCP_PERF_SEL_UNALIGNED = 149 TCP_PERF_SEL_ROTATED_MICROTILING = 150 TCP_PERF_SEL_THICK_MICROTILING = 151 TCP_PERF_SEL_ATC = 152 TCP_PERF_SEL_POWER_STALL = 153 TCP_PERF_SEL_RESERVED_154 = 154 TCP_PERF_SEL_TCC_LRU_REQ = 155 TCP_PERF_SEL_TCC_STREAM_REQ = 156 TCP_PERF_SEL_TCC_NC_READ_REQ = 157 TCP_PERF_SEL_TCC_NC_WRITE_REQ = 158 TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 159 TCP_PERF_SEL_TCC_UC_READ_REQ = 160 TCP_PERF_SEL_TCC_UC_WRITE_REQ = 161 TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 162 TCP_PERF_SEL_TCC_CC_READ_REQ = 163 TCP_PERF_SEL_TCC_CC_WRITE_REQ = 164 TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 165 TCP_PERF_SEL_TCC_DCC_REQ = 166 TCP_PERF_SEL_TCC_PHYSICAL_REQ = 167 TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 168 TCP_PERF_SEL_VOLATILE = 169 TCP_PERF_SEL_TC_TA_XNACK_STALL = 170 TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL = 171 TCP_PERF_SEL_SHOOTDOWN = 172 TCP_PERF_SEL_UTCL1_TRANSLATION_MISS = 173 TCP_PERF_SEL_UTCL1_PERMISSION_MISS = 174 TCP_PERF_SEL_UTCL1_REQUEST = 175 TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 176 TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 177 TCP_PERF_SEL_UTCL1_LFIFO_FULL = 178 TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 179 TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 180 TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT = 181 TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 182 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB = 183 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA = 184 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1 = 185 TCP_PERF_SEL_IMG_READ_FMT_ETC2_R = 186 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG = 187 TCP_PERF_SEL_IMG_READ_FMT_8_AS_32 = 188 TCP_PERF_SEL_IMG_READ_FMT_8_AS_64 = 189 TCP_PERF_SEL_IMG_READ_FMT_16_AS_64 = 190 TCP_PERF_SEL_IMG_READ_FMT_16_AS_128 = 191 TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32 = 192 TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64 = 193 TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64 = 194 TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128 = 195 TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum # values for enumeration 'TCP_CACHE_POLICIES' TCP_CACHE_POLICIES__enumvalues = { 0: 'TCP_CACHE_POLICY_MISS_LRU', 1: 'TCP_CACHE_POLICY_MISS_EVICT', 2: 'TCP_CACHE_POLICY_HIT_LRU', 3: 'TCP_CACHE_POLICY_HIT_EVICT', } TCP_CACHE_POLICY_MISS_LRU = 0 TCP_CACHE_POLICY_MISS_EVICT = 1 TCP_CACHE_POLICY_HIT_LRU = 2 TCP_CACHE_POLICY_HIT_EVICT = 3 TCP_CACHE_POLICIES = ctypes.c_uint32 # enum # values for enumeration 'TCP_CACHE_STORE_POLICIES' TCP_CACHE_STORE_POLICIES__enumvalues = { 0: 'TCP_CACHE_STORE_POLICY_WT_LRU', 1: 'TCP_CACHE_STORE_POLICY_WT_EVICT', } TCP_CACHE_STORE_POLICY_WT_LRU = 0 TCP_CACHE_STORE_POLICY_WT_EVICT = 1 TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum # values for enumeration 'TCP_WATCH_MODES' TCP_WATCH_MODES__enumvalues = { 0: 'TCP_WATCH_MODE_READ', 1: 'TCP_WATCH_MODE_NONREAD', 2: 'TCP_WATCH_MODE_ATOMIC', 3: 'TCP_WATCH_MODE_ALL', } TCP_WATCH_MODE_READ = 0 TCP_WATCH_MODE_NONREAD = 1 TCP_WATCH_MODE_ATOMIC = 2 TCP_WATCH_MODE_ALL = 3 TCP_WATCH_MODES = ctypes.c_uint32 # enum # values for enumeration 'TCP_DSM_DATA_SEL' TCP_DSM_DATA_SEL__enumvalues = { 0: 'TCP_DSM_DISABLE', 1: 'TCP_DSM_SEL0', 2: 'TCP_DSM_SEL1', 3: 'TCP_DSM_SEL_BOTH', } TCP_DSM_DISABLE = 0 TCP_DSM_SEL0 = 1 TCP_DSM_SEL1 = 2 TCP_DSM_SEL_BOTH = 3 TCP_DSM_DATA_SEL = ctypes.c_uint32 # enum # values for enumeration 'TCP_DSM_SINGLE_WRITE' TCP_DSM_SINGLE_WRITE__enumvalues = { 0: 'TCP_DSM_SINGLE_WRITE_DIS', 1: 'TCP_DSM_SINGLE_WRITE_EN', } TCP_DSM_SINGLE_WRITE_DIS = 0 TCP_DSM_SINGLE_WRITE_EN = 1 TCP_DSM_SINGLE_WRITE = ctypes.c_uint32 # enum # values for enumeration 'TCP_DSM_INJECT_SEL' TCP_DSM_INJECT_SEL__enumvalues = { 0: 'TCP_DSM_INJECT_SEL0', 1: 'TCP_DSM_INJECT_SEL1', 2: 'TCP_DSM_INJECT_SEL2', 3: 'TCP_DSM_INJECT_SEL3', } TCP_DSM_INJECT_SEL0 = 0 TCP_DSM_INJECT_SEL1 = 1 TCP_DSM_INJECT_SEL2 = 2 TCP_DSM_INJECT_SEL3 = 3 TCP_DSM_INJECT_SEL = ctypes.c_uint32 # enum # values for enumeration 'TCC_PERF_SEL' TCC_PERF_SEL__enumvalues = { 0: 'TCC_PERF_SEL_NONE', 1: 'TCC_PERF_SEL_CYCLE', 2: 'TCC_PERF_SEL_BUSY', 3: 'TCC_PERF_SEL_REQ', 4: 'TCC_PERF_SEL_STREAMING_REQ', 5: 'TCC_PERF_SEL_EXE_REQ', 6: 'TCC_PERF_SEL_COMPRESSED_REQ', 7: 'TCC_PERF_SEL_COMPRESSED_0_REQ', 8: 'TCC_PERF_SEL_METADATA_REQ', 9: 'TCC_PERF_SEL_NC_VIRTUAL_REQ', 10: 'TCC_PERF_SEL_UC_VIRTUAL_REQ', 11: 'TCC_PERF_SEL_CC_PHYSICAL_REQ', 12: 'TCC_PERF_SEL_PROBE', 13: 'TCC_PERF_SEL_PROBE_ALL', 14: 'TCC_PERF_SEL_READ', 15: 'TCC_PERF_SEL_WRITE', 16: 'TCC_PERF_SEL_ATOMIC', 17: 'TCC_PERF_SEL_HIT', 18: 'TCC_PERF_SEL_SECTOR_HIT', 19: 'TCC_PERF_SEL_MISS', 20: 'TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT', 21: 'TCC_PERF_SEL_FULLY_WRITTEN_HIT', 22: 'TCC_PERF_SEL_WRITEBACK', 23: 'TCC_PERF_SEL_LATENCY_FIFO_FULL', 24: 'TCC_PERF_SEL_SRC_FIFO_FULL', 25: 'TCC_PERF_SEL_HOLE_FIFO_FULL', 26: 'TCC_PERF_SEL_EA_WRREQ', 27: 'TCC_PERF_SEL_EA_WRREQ_64B', 28: 'TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND', 29: 'TCC_PERF_SEL_EA_WR_UNCACHED_32B', 30: 'TCC_PERF_SEL_EA_WRREQ_STALL', 31: 'TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL', 32: 'TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 33: 'TCC_PERF_SEL_EA_WRREQ_LEVEL', 34: 'TCC_PERF_SEL_EA_ATOMIC', 35: 'TCC_PERF_SEL_EA_ATOMIC_LEVEL', 36: 'TCC_PERF_SEL_EA_RDREQ', 37: 'TCC_PERF_SEL_EA_RDREQ_32B', 38: 'TCC_PERF_SEL_EA_RD_UNCACHED_32B', 39: 'TCC_PERF_SEL_EA_RD_MDC_32B', 40: 'TCC_PERF_SEL_EA_RD_COMPRESSED_32B', 41: 'TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL', 42: 'TCC_PERF_SEL_EA_RDREQ_LEVEL', 43: 'TCC_PERF_SEL_TAG_STALL', 44: 'TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', 45: 'TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', 46: 'TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', 47: 'TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', 48: 'TCC_PERF_SEL_TAG_PROBE_STALL', 49: 'TCC_PERF_SEL_TAG_PROBE_FILTER_STALL', 50: 'TCC_PERF_SEL_READ_RETURN_TIMEOUT', 51: 'TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT', 52: 'TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE', 53: 'TCC_PERF_SEL_BUBBLE', 54: 'TCC_PERF_SEL_RETURN_ACK', 55: 'TCC_PERF_SEL_RETURN_DATA', 56: 'TCC_PERF_SEL_RETURN_HOLE', 57: 'TCC_PERF_SEL_RETURN_ACK_HOLE', 58: 'TCC_PERF_SEL_IB_REQ', 59: 'TCC_PERF_SEL_IB_STALL', 60: 'TCC_PERF_SEL_IB_TAG_STALL', 61: 'TCC_PERF_SEL_IB_MDC_STALL', 62: 'TCC_PERF_SEL_TCA_LEVEL', 63: 'TCC_PERF_SEL_HOLE_LEVEL', 64: 'TCC_PERF_SEL_NORMAL_WRITEBACK', 65: 'TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK', 66: 'TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK', 67: 'TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK', 68: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK', 69: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK', 70: 'TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK', 71: 'TCC_PERF_SEL_NORMAL_EVICT', 72: 'TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT', 73: 'TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT', 74: 'TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT', 75: 'TCC_PERF_SEL_TC_OP_WBINVL2_EVICT', 76: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT', 77: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT', 78: 'TCC_PERF_SEL_ALL_TC_OP_INV_EVICT', 79: 'TCC_PERF_SEL_PROBE_EVICT', 80: 'TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE', 81: 'TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE', 82: 'TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE', 83: 'TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE', 84: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE', 85: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE', 86: 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE', 87: 'TCC_PERF_SEL_TC_OP_WBL2_NC_START', 88: 'TCC_PERF_SEL_TC_OP_WBL2_WC_START', 89: 'TCC_PERF_SEL_TC_OP_INVL2_NC_START', 90: 'TCC_PERF_SEL_TC_OP_WBINVL2_START', 91: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_START', 92: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_START', 93: 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', 94: 'TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH', 95: 'TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH', 96: 'TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH', 97: 'TCC_PERF_SEL_TC_OP_WBINVL2_FINISH', 98: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH', 99: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH', 100: 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH', 101: 'TCC_PERF_SEL_MDC_REQ', 102: 'TCC_PERF_SEL_MDC_LEVEL', 103: 'TCC_PERF_SEL_MDC_TAG_HIT', 104: 'TCC_PERF_SEL_MDC_SECTOR_HIT', 105: 'TCC_PERF_SEL_MDC_SECTOR_MISS', 106: 'TCC_PERF_SEL_MDC_TAG_STALL', 107: 'TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', 108: 'TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', 109: 'TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', 110: 'TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', 111: 'TCC_PERF_SEL_PROBE_FILTER_DISABLED', 128: 'TCC_PERF_SEL_CLIENT0_REQ', 129: 'TCC_PERF_SEL_CLIENT1_REQ', 130: 'TCC_PERF_SEL_CLIENT2_REQ', 131: 'TCC_PERF_SEL_CLIENT3_REQ', 132: 'TCC_PERF_SEL_CLIENT4_REQ', 133: 'TCC_PERF_SEL_CLIENT5_REQ', 134: 'TCC_PERF_SEL_CLIENT6_REQ', 135: 'TCC_PERF_SEL_CLIENT7_REQ', 136: 'TCC_PERF_SEL_CLIENT8_REQ', 137: 'TCC_PERF_SEL_CLIENT9_REQ', 138: 'TCC_PERF_SEL_CLIENT10_REQ', 139: 'TCC_PERF_SEL_CLIENT11_REQ', 140: 'TCC_PERF_SEL_CLIENT12_REQ', 141: 'TCC_PERF_SEL_CLIENT13_REQ', 142: 'TCC_PERF_SEL_CLIENT14_REQ', 143: 'TCC_PERF_SEL_CLIENT15_REQ', 144: 'TCC_PERF_SEL_CLIENT16_REQ', 145: 'TCC_PERF_SEL_CLIENT17_REQ', 146: 'TCC_PERF_SEL_CLIENT18_REQ', 147: 'TCC_PERF_SEL_CLIENT19_REQ', 148: 'TCC_PERF_SEL_CLIENT20_REQ', 149: 'TCC_PERF_SEL_CLIENT21_REQ', 150: 'TCC_PERF_SEL_CLIENT22_REQ', 151: 'TCC_PERF_SEL_CLIENT23_REQ', 152: 'TCC_PERF_SEL_CLIENT24_REQ', 153: 'TCC_PERF_SEL_CLIENT25_REQ', 154: 'TCC_PERF_SEL_CLIENT26_REQ', 155: 'TCC_PERF_SEL_CLIENT27_REQ', 156: 'TCC_PERF_SEL_CLIENT28_REQ', 157: 'TCC_PERF_SEL_CLIENT29_REQ', 158: 'TCC_PERF_SEL_CLIENT30_REQ', 159: 'TCC_PERF_SEL_CLIENT31_REQ', 160: 'TCC_PERF_SEL_CLIENT32_REQ', 161: 'TCC_PERF_SEL_CLIENT33_REQ', 162: 'TCC_PERF_SEL_CLIENT34_REQ', 163: 'TCC_PERF_SEL_CLIENT35_REQ', 164: 'TCC_PERF_SEL_CLIENT36_REQ', 165: 'TCC_PERF_SEL_CLIENT37_REQ', 166: 'TCC_PERF_SEL_CLIENT38_REQ', 167: 'TCC_PERF_SEL_CLIENT39_REQ', 168: 'TCC_PERF_SEL_CLIENT40_REQ', 169: 'TCC_PERF_SEL_CLIENT41_REQ', 170: 'TCC_PERF_SEL_CLIENT42_REQ', 171: 'TCC_PERF_SEL_CLIENT43_REQ', 172: 'TCC_PERF_SEL_CLIENT44_REQ', 173: 'TCC_PERF_SEL_CLIENT45_REQ', 174: 'TCC_PERF_SEL_CLIENT46_REQ', 175: 'TCC_PERF_SEL_CLIENT47_REQ', 176: 'TCC_PERF_SEL_CLIENT48_REQ', 177: 'TCC_PERF_SEL_CLIENT49_REQ', 178: 'TCC_PERF_SEL_CLIENT50_REQ', 179: 'TCC_PERF_SEL_CLIENT51_REQ', 180: 'TCC_PERF_SEL_CLIENT52_REQ', 181: 'TCC_PERF_SEL_CLIENT53_REQ', 182: 'TCC_PERF_SEL_CLIENT54_REQ', 183: 'TCC_PERF_SEL_CLIENT55_REQ', 184: 'TCC_PERF_SEL_CLIENT56_REQ', 185: 'TCC_PERF_SEL_CLIENT57_REQ', 186: 'TCC_PERF_SEL_CLIENT58_REQ', 187: 'TCC_PERF_SEL_CLIENT59_REQ', 188: 'TCC_PERF_SEL_CLIENT60_REQ', 189: 'TCC_PERF_SEL_CLIENT61_REQ', 190: 'TCC_PERF_SEL_CLIENT62_REQ', 191: 'TCC_PERF_SEL_CLIENT63_REQ', 192: 'TCC_PERF_SEL_CLIENT64_REQ', 193: 'TCC_PERF_SEL_CLIENT65_REQ', 194: 'TCC_PERF_SEL_CLIENT66_REQ', 195: 'TCC_PERF_SEL_CLIENT67_REQ', 196: 'TCC_PERF_SEL_CLIENT68_REQ', 197: 'TCC_PERF_SEL_CLIENT69_REQ', 198: 'TCC_PERF_SEL_CLIENT70_REQ', 199: 'TCC_PERF_SEL_CLIENT71_REQ', 200: 'TCC_PERF_SEL_CLIENT72_REQ', 201: 'TCC_PERF_SEL_CLIENT73_REQ', 202: 'TCC_PERF_SEL_CLIENT74_REQ', 203: 'TCC_PERF_SEL_CLIENT75_REQ', 204: 'TCC_PERF_SEL_CLIENT76_REQ', 205: 'TCC_PERF_SEL_CLIENT77_REQ', 206: 'TCC_PERF_SEL_CLIENT78_REQ', 207: 'TCC_PERF_SEL_CLIENT79_REQ', 208: 'TCC_PERF_SEL_CLIENT80_REQ', 209: 'TCC_PERF_SEL_CLIENT81_REQ', 210: 'TCC_PERF_SEL_CLIENT82_REQ', 211: 'TCC_PERF_SEL_CLIENT83_REQ', 212: 'TCC_PERF_SEL_CLIENT84_REQ', 213: 'TCC_PERF_SEL_CLIENT85_REQ', 214: 'TCC_PERF_SEL_CLIENT86_REQ', 215: 'TCC_PERF_SEL_CLIENT87_REQ', 216: 'TCC_PERF_SEL_CLIENT88_REQ', 217: 'TCC_PERF_SEL_CLIENT89_REQ', 218: 'TCC_PERF_SEL_CLIENT90_REQ', 219: 'TCC_PERF_SEL_CLIENT91_REQ', 220: 'TCC_PERF_SEL_CLIENT92_REQ', 221: 'TCC_PERF_SEL_CLIENT93_REQ', 222: 'TCC_PERF_SEL_CLIENT94_REQ', 223: 'TCC_PERF_SEL_CLIENT95_REQ', 224: 'TCC_PERF_SEL_CLIENT96_REQ', 225: 'TCC_PERF_SEL_CLIENT97_REQ', 226: 'TCC_PERF_SEL_CLIENT98_REQ', 227: 'TCC_PERF_SEL_CLIENT99_REQ', 228: 'TCC_PERF_SEL_CLIENT100_REQ', 229: 'TCC_PERF_SEL_CLIENT101_REQ', 230: 'TCC_PERF_SEL_CLIENT102_REQ', 231: 'TCC_PERF_SEL_CLIENT103_REQ', 232: 'TCC_PERF_SEL_CLIENT104_REQ', 233: 'TCC_PERF_SEL_CLIENT105_REQ', 234: 'TCC_PERF_SEL_CLIENT106_REQ', 235: 'TCC_PERF_SEL_CLIENT107_REQ', 236: 'TCC_PERF_SEL_CLIENT108_REQ', 237: 'TCC_PERF_SEL_CLIENT109_REQ', 238: 'TCC_PERF_SEL_CLIENT110_REQ', 239: 'TCC_PERF_SEL_CLIENT111_REQ', 240: 'TCC_PERF_SEL_CLIENT112_REQ', 241: 'TCC_PERF_SEL_CLIENT113_REQ', 242: 'TCC_PERF_SEL_CLIENT114_REQ', 243: 'TCC_PERF_SEL_CLIENT115_REQ', 244: 'TCC_PERF_SEL_CLIENT116_REQ', 245: 'TCC_PERF_SEL_CLIENT117_REQ', 246: 'TCC_PERF_SEL_CLIENT118_REQ', 247: 'TCC_PERF_SEL_CLIENT119_REQ', 248: 'TCC_PERF_SEL_CLIENT120_REQ', 249: 'TCC_PERF_SEL_CLIENT121_REQ', 250: 'TCC_PERF_SEL_CLIENT122_REQ', 251: 'TCC_PERF_SEL_CLIENT123_REQ', 252: 'TCC_PERF_SEL_CLIENT124_REQ', 253: 'TCC_PERF_SEL_CLIENT125_REQ', 254: 'TCC_PERF_SEL_CLIENT126_REQ', 255: 'TCC_PERF_SEL_CLIENT127_REQ', } TCC_PERF_SEL_NONE = 0 TCC_PERF_SEL_CYCLE = 1 TCC_PERF_SEL_BUSY = 2 TCC_PERF_SEL_REQ = 3 TCC_PERF_SEL_STREAMING_REQ = 4 TCC_PERF_SEL_EXE_REQ = 5 TCC_PERF_SEL_COMPRESSED_REQ = 6 TCC_PERF_SEL_COMPRESSED_0_REQ = 7 TCC_PERF_SEL_METADATA_REQ = 8 TCC_PERF_SEL_NC_VIRTUAL_REQ = 9 TCC_PERF_SEL_UC_VIRTUAL_REQ = 10 TCC_PERF_SEL_CC_PHYSICAL_REQ = 11 TCC_PERF_SEL_PROBE = 12 TCC_PERF_SEL_PROBE_ALL = 13 TCC_PERF_SEL_READ = 14 TCC_PERF_SEL_WRITE = 15 TCC_PERF_SEL_ATOMIC = 16 TCC_PERF_SEL_HIT = 17 TCC_PERF_SEL_SECTOR_HIT = 18 TCC_PERF_SEL_MISS = 19 TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 20 TCC_PERF_SEL_FULLY_WRITTEN_HIT = 21 TCC_PERF_SEL_WRITEBACK = 22 TCC_PERF_SEL_LATENCY_FIFO_FULL = 23 TCC_PERF_SEL_SRC_FIFO_FULL = 24 TCC_PERF_SEL_HOLE_FIFO_FULL = 25 TCC_PERF_SEL_EA_WRREQ = 26 TCC_PERF_SEL_EA_WRREQ_64B = 27 TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 28 TCC_PERF_SEL_EA_WR_UNCACHED_32B = 29 TCC_PERF_SEL_EA_WRREQ_STALL = 30 TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL = 31 TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 32 TCC_PERF_SEL_EA_WRREQ_LEVEL = 33 TCC_PERF_SEL_EA_ATOMIC = 34 TCC_PERF_SEL_EA_ATOMIC_LEVEL = 35 TCC_PERF_SEL_EA_RDREQ = 36 TCC_PERF_SEL_EA_RDREQ_32B = 37 TCC_PERF_SEL_EA_RD_UNCACHED_32B = 38 TCC_PERF_SEL_EA_RD_MDC_32B = 39 TCC_PERF_SEL_EA_RD_COMPRESSED_32B = 40 TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL = 41 TCC_PERF_SEL_EA_RDREQ_LEVEL = 42 TCC_PERF_SEL_TAG_STALL = 43 TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 44 TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 45 TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 46 TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 47 TCC_PERF_SEL_TAG_PROBE_STALL = 48 TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 49 TCC_PERF_SEL_READ_RETURN_TIMEOUT = 50 TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 51 TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 52 TCC_PERF_SEL_BUBBLE = 53 TCC_PERF_SEL_RETURN_ACK = 54 TCC_PERF_SEL_RETURN_DATA = 55 TCC_PERF_SEL_RETURN_HOLE = 56 TCC_PERF_SEL_RETURN_ACK_HOLE = 57 TCC_PERF_SEL_IB_REQ = 58 TCC_PERF_SEL_IB_STALL = 59 TCC_PERF_SEL_IB_TAG_STALL = 60 TCC_PERF_SEL_IB_MDC_STALL = 61 TCC_PERF_SEL_TCA_LEVEL = 62 TCC_PERF_SEL_HOLE_LEVEL = 63 TCC_PERF_SEL_NORMAL_WRITEBACK = 64 TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 65 TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK = 66 TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 67 TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 68 TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 69 TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 70 TCC_PERF_SEL_NORMAL_EVICT = 71 TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 72 TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT = 73 TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 74 TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 75 TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 76 TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 77 TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 78 TCC_PERF_SEL_PROBE_EVICT = 79 TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 80 TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE = 81 TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 82 TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 83 TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 84 TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 85 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 86 TCC_PERF_SEL_TC_OP_WBL2_NC_START = 87 TCC_PERF_SEL_TC_OP_WBL2_WC_START = 88 TCC_PERF_SEL_TC_OP_INVL2_NC_START = 89 TCC_PERF_SEL_TC_OP_WBINVL2_START = 90 TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 91 TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 92 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 93 TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 94 TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH = 95 TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 96 TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 97 TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 98 TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 99 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 100 TCC_PERF_SEL_MDC_REQ = 101 TCC_PERF_SEL_MDC_LEVEL = 102 TCC_PERF_SEL_MDC_TAG_HIT = 103 TCC_PERF_SEL_MDC_SECTOR_HIT = 104 TCC_PERF_SEL_MDC_SECTOR_MISS = 105 TCC_PERF_SEL_MDC_TAG_STALL = 106 TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 107 TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 108 TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 109 TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 110 TCC_PERF_SEL_PROBE_FILTER_DISABLED = 111 TCC_PERF_SEL_CLIENT0_REQ = 128 TCC_PERF_SEL_CLIENT1_REQ = 129 TCC_PERF_SEL_CLIENT2_REQ = 130 TCC_PERF_SEL_CLIENT3_REQ = 131 TCC_PERF_SEL_CLIENT4_REQ = 132 TCC_PERF_SEL_CLIENT5_REQ = 133 TCC_PERF_SEL_CLIENT6_REQ = 134 TCC_PERF_SEL_CLIENT7_REQ = 135 TCC_PERF_SEL_CLIENT8_REQ = 136 TCC_PERF_SEL_CLIENT9_REQ = 137 TCC_PERF_SEL_CLIENT10_REQ = 138 TCC_PERF_SEL_CLIENT11_REQ = 139 TCC_PERF_SEL_CLIENT12_REQ = 140 TCC_PERF_SEL_CLIENT13_REQ = 141 TCC_PERF_SEL_CLIENT14_REQ = 142 TCC_PERF_SEL_CLIENT15_REQ = 143 TCC_PERF_SEL_CLIENT16_REQ = 144 TCC_PERF_SEL_CLIENT17_REQ = 145 TCC_PERF_SEL_CLIENT18_REQ = 146 TCC_PERF_SEL_CLIENT19_REQ = 147 TCC_PERF_SEL_CLIENT20_REQ = 148 TCC_PERF_SEL_CLIENT21_REQ = 149 TCC_PERF_SEL_CLIENT22_REQ = 150 TCC_PERF_SEL_CLIENT23_REQ = 151 TCC_PERF_SEL_CLIENT24_REQ = 152 TCC_PERF_SEL_CLIENT25_REQ = 153 TCC_PERF_SEL_CLIENT26_REQ = 154 TCC_PERF_SEL_CLIENT27_REQ = 155 TCC_PERF_SEL_CLIENT28_REQ = 156 TCC_PERF_SEL_CLIENT29_REQ = 157 TCC_PERF_SEL_CLIENT30_REQ = 158 TCC_PERF_SEL_CLIENT31_REQ = 159 TCC_PERF_SEL_CLIENT32_REQ = 160 TCC_PERF_SEL_CLIENT33_REQ = 161 TCC_PERF_SEL_CLIENT34_REQ = 162 TCC_PERF_SEL_CLIENT35_REQ = 163 TCC_PERF_SEL_CLIENT36_REQ = 164 TCC_PERF_SEL_CLIENT37_REQ = 165 TCC_PERF_SEL_CLIENT38_REQ = 166 TCC_PERF_SEL_CLIENT39_REQ = 167 TCC_PERF_SEL_CLIENT40_REQ = 168 TCC_PERF_SEL_CLIENT41_REQ = 169 TCC_PERF_SEL_CLIENT42_REQ = 170 TCC_PERF_SEL_CLIENT43_REQ = 171 TCC_PERF_SEL_CLIENT44_REQ = 172 TCC_PERF_SEL_CLIENT45_REQ = 173 TCC_PERF_SEL_CLIENT46_REQ = 174 TCC_PERF_SEL_CLIENT47_REQ = 175 TCC_PERF_SEL_CLIENT48_REQ = 176 TCC_PERF_SEL_CLIENT49_REQ = 177 TCC_PERF_SEL_CLIENT50_REQ = 178 TCC_PERF_SEL_CLIENT51_REQ = 179 TCC_PERF_SEL_CLIENT52_REQ = 180 TCC_PERF_SEL_CLIENT53_REQ = 181 TCC_PERF_SEL_CLIENT54_REQ = 182 TCC_PERF_SEL_CLIENT55_REQ = 183 TCC_PERF_SEL_CLIENT56_REQ = 184 TCC_PERF_SEL_CLIENT57_REQ = 185 TCC_PERF_SEL_CLIENT58_REQ = 186 TCC_PERF_SEL_CLIENT59_REQ = 187 TCC_PERF_SEL_CLIENT60_REQ = 188 TCC_PERF_SEL_CLIENT61_REQ = 189 TCC_PERF_SEL_CLIENT62_REQ = 190 TCC_PERF_SEL_CLIENT63_REQ = 191 TCC_PERF_SEL_CLIENT64_REQ = 192 TCC_PERF_SEL_CLIENT65_REQ = 193 TCC_PERF_SEL_CLIENT66_REQ = 194 TCC_PERF_SEL_CLIENT67_REQ = 195 TCC_PERF_SEL_CLIENT68_REQ = 196 TCC_PERF_SEL_CLIENT69_REQ = 197 TCC_PERF_SEL_CLIENT70_REQ = 198 TCC_PERF_SEL_CLIENT71_REQ = 199 TCC_PERF_SEL_CLIENT72_REQ = 200 TCC_PERF_SEL_CLIENT73_REQ = 201 TCC_PERF_SEL_CLIENT74_REQ = 202 TCC_PERF_SEL_CLIENT75_REQ = 203 TCC_PERF_SEL_CLIENT76_REQ = 204 TCC_PERF_SEL_CLIENT77_REQ = 205 TCC_PERF_SEL_CLIENT78_REQ = 206 TCC_PERF_SEL_CLIENT79_REQ = 207 TCC_PERF_SEL_CLIENT80_REQ = 208 TCC_PERF_SEL_CLIENT81_REQ = 209 TCC_PERF_SEL_CLIENT82_REQ = 210 TCC_PERF_SEL_CLIENT83_REQ = 211 TCC_PERF_SEL_CLIENT84_REQ = 212 TCC_PERF_SEL_CLIENT85_REQ = 213 TCC_PERF_SEL_CLIENT86_REQ = 214 TCC_PERF_SEL_CLIENT87_REQ = 215 TCC_PERF_SEL_CLIENT88_REQ = 216 TCC_PERF_SEL_CLIENT89_REQ = 217 TCC_PERF_SEL_CLIENT90_REQ = 218 TCC_PERF_SEL_CLIENT91_REQ = 219 TCC_PERF_SEL_CLIENT92_REQ = 220 TCC_PERF_SEL_CLIENT93_REQ = 221 TCC_PERF_SEL_CLIENT94_REQ = 222 TCC_PERF_SEL_CLIENT95_REQ = 223 TCC_PERF_SEL_CLIENT96_REQ = 224 TCC_PERF_SEL_CLIENT97_REQ = 225 TCC_PERF_SEL_CLIENT98_REQ = 226 TCC_PERF_SEL_CLIENT99_REQ = 227 TCC_PERF_SEL_CLIENT100_REQ = 228 TCC_PERF_SEL_CLIENT101_REQ = 229 TCC_PERF_SEL_CLIENT102_REQ = 230 TCC_PERF_SEL_CLIENT103_REQ = 231 TCC_PERF_SEL_CLIENT104_REQ = 232 TCC_PERF_SEL_CLIENT105_REQ = 233 TCC_PERF_SEL_CLIENT106_REQ = 234 TCC_PERF_SEL_CLIENT107_REQ = 235 TCC_PERF_SEL_CLIENT108_REQ = 236 TCC_PERF_SEL_CLIENT109_REQ = 237 TCC_PERF_SEL_CLIENT110_REQ = 238 TCC_PERF_SEL_CLIENT111_REQ = 239 TCC_PERF_SEL_CLIENT112_REQ = 240 TCC_PERF_SEL_CLIENT113_REQ = 241 TCC_PERF_SEL_CLIENT114_REQ = 242 TCC_PERF_SEL_CLIENT115_REQ = 243 TCC_PERF_SEL_CLIENT116_REQ = 244 TCC_PERF_SEL_CLIENT117_REQ = 245 TCC_PERF_SEL_CLIENT118_REQ = 246 TCC_PERF_SEL_CLIENT119_REQ = 247 TCC_PERF_SEL_CLIENT120_REQ = 248 TCC_PERF_SEL_CLIENT121_REQ = 249 TCC_PERF_SEL_CLIENT122_REQ = 250 TCC_PERF_SEL_CLIENT123_REQ = 251 TCC_PERF_SEL_CLIENT124_REQ = 252 TCC_PERF_SEL_CLIENT125_REQ = 253 TCC_PERF_SEL_CLIENT126_REQ = 254 TCC_PERF_SEL_CLIENT127_REQ = 255 TCC_PERF_SEL = ctypes.c_uint32 # enum # values for enumeration 'TCA_PERF_SEL' TCA_PERF_SEL__enumvalues = { 0: 'TCA_PERF_SEL_NONE', 1: 'TCA_PERF_SEL_CYCLE', 2: 'TCA_PERF_SEL_BUSY', 3: 'TCA_PERF_SEL_FORCED_HOLE_TCC0', 4: 'TCA_PERF_SEL_FORCED_HOLE_TCC1', 5: 'TCA_PERF_SEL_FORCED_HOLE_TCC2', 6: 'TCA_PERF_SEL_FORCED_HOLE_TCC3', 7: 'TCA_PERF_SEL_FORCED_HOLE_TCC4', 8: 'TCA_PERF_SEL_FORCED_HOLE_TCC5', 9: 'TCA_PERF_SEL_FORCED_HOLE_TCC6', 10: 'TCA_PERF_SEL_FORCED_HOLE_TCC7', 11: 'TCA_PERF_SEL_REQ_TCC0', 12: 'TCA_PERF_SEL_REQ_TCC1', 13: 'TCA_PERF_SEL_REQ_TCC2', 14: 'TCA_PERF_SEL_REQ_TCC3', 15: 'TCA_PERF_SEL_REQ_TCC4', 16: 'TCA_PERF_SEL_REQ_TCC5', 17: 'TCA_PERF_SEL_REQ_TCC6', 18: 'TCA_PERF_SEL_REQ_TCC7', 19: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0', 20: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1', 21: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2', 22: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3', 23: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4', 24: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5', 25: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6', 26: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7', 27: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC0', 28: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC1', 29: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC2', 30: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC3', 31: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC4', 32: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC5', 33: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC6', 34: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC7', } TCA_PERF_SEL_NONE = 0 TCA_PERF_SEL_CYCLE = 1 TCA_PERF_SEL_BUSY = 2 TCA_PERF_SEL_FORCED_HOLE_TCC0 = 3 TCA_PERF_SEL_FORCED_HOLE_TCC1 = 4 TCA_PERF_SEL_FORCED_HOLE_TCC2 = 5 TCA_PERF_SEL_FORCED_HOLE_TCC3 = 6 TCA_PERF_SEL_FORCED_HOLE_TCC4 = 7 TCA_PERF_SEL_FORCED_HOLE_TCC5 = 8 TCA_PERF_SEL_FORCED_HOLE_TCC6 = 9 TCA_PERF_SEL_FORCED_HOLE_TCC7 = 10 TCA_PERF_SEL_REQ_TCC0 = 11 TCA_PERF_SEL_REQ_TCC1 = 12 TCA_PERF_SEL_REQ_TCC2 = 13 TCA_PERF_SEL_REQ_TCC3 = 14 TCA_PERF_SEL_REQ_TCC4 = 15 TCA_PERF_SEL_REQ_TCC5 = 16 TCA_PERF_SEL_REQ_TCC6 = 17 TCA_PERF_SEL_REQ_TCC7 = 18 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 19 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 20 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 21 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 22 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 23 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 24 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 25 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 26 TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 27 TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 28 TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 29 TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 30 TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 31 TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 32 TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 33 TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 34 TCA_PERF_SEL = ctypes.c_uint32 # enum # values for enumeration 'GRBM_PERF_SEL' GRBM_PERF_SEL__enumvalues = { 0: 'GRBM_PERF_SEL_COUNT', 1: 'GRBM_PERF_SEL_USER_DEFINED', 2: 'GRBM_PERF_SEL_GUI_ACTIVE', 3: 'GRBM_PERF_SEL_CP_BUSY', 4: 'GRBM_PERF_SEL_CP_COHER_BUSY', 5: 'GRBM_PERF_SEL_CP_DMA_BUSY', 6: 'GRBM_PERF_SEL_CB_BUSY', 7: 'GRBM_PERF_SEL_DB_BUSY', 8: 'GRBM_PERF_SEL_PA_BUSY', 9: 'GRBM_PERF_SEL_SC_BUSY', 10: 'GRBM_PERF_SEL_RESERVED_6', 11: 'GRBM_PERF_SEL_SPI_BUSY', 12: 'GRBM_PERF_SEL_SX_BUSY', 13: 'GRBM_PERF_SEL_TA_BUSY', 14: 'GRBM_PERF_SEL_CB_CLEAN', 15: 'GRBM_PERF_SEL_DB_CLEAN', 16: 'GRBM_PERF_SEL_RESERVED_5', 17: 'GRBM_PERF_SEL_VGT_BUSY', 18: 'GRBM_PERF_SEL_RESERVED_4', 19: 'GRBM_PERF_SEL_RESERVED_3', 20: 'GRBM_PERF_SEL_RESERVED_2', 21: 'GRBM_PERF_SEL_RESERVED_1', 22: 'GRBM_PERF_SEL_RESERVED_0', 23: 'GRBM_PERF_SEL_IA_BUSY', 24: 'GRBM_PERF_SEL_IA_NO_DMA_BUSY', 25: 'GRBM_PERF_SEL_GDS_BUSY', 26: 'GRBM_PERF_SEL_BCI_BUSY', 27: 'GRBM_PERF_SEL_RLC_BUSY', 28: 'GRBM_PERF_SEL_TC_BUSY', 29: 'GRBM_PERF_SEL_CPG_BUSY', 30: 'GRBM_PERF_SEL_CPC_BUSY', 31: 'GRBM_PERF_SEL_CPF_BUSY', 32: 'GRBM_PERF_SEL_WD_BUSY', 33: 'GRBM_PERF_SEL_WD_NO_DMA_BUSY', 34: 'GRBM_PERF_SEL_UTCL2_BUSY', 35: 'GRBM_PERF_SEL_EA_BUSY', 36: 'GRBM_PERF_SEL_RMI_BUSY', 37: 'GRBM_PERF_SEL_CPAXI_BUSY', } GRBM_PERF_SEL_COUNT = 0 GRBM_PERF_SEL_USER_DEFINED = 1 GRBM_PERF_SEL_GUI_ACTIVE = 2 GRBM_PERF_SEL_CP_BUSY = 3 GRBM_PERF_SEL_CP_COHER_BUSY = 4 GRBM_PERF_SEL_CP_DMA_BUSY = 5 GRBM_PERF_SEL_CB_BUSY = 6 GRBM_PERF_SEL_DB_BUSY = 7 GRBM_PERF_SEL_PA_BUSY = 8 GRBM_PERF_SEL_SC_BUSY = 9 GRBM_PERF_SEL_RESERVED_6 = 10 GRBM_PERF_SEL_SPI_BUSY = 11 GRBM_PERF_SEL_SX_BUSY = 12 GRBM_PERF_SEL_TA_BUSY = 13 GRBM_PERF_SEL_CB_CLEAN = 14 GRBM_PERF_SEL_DB_CLEAN = 15 GRBM_PERF_SEL_RESERVED_5 = 16 GRBM_PERF_SEL_VGT_BUSY = 17 GRBM_PERF_SEL_RESERVED_4 = 18 GRBM_PERF_SEL_RESERVED_3 = 19 GRBM_PERF_SEL_RESERVED_2 = 20 GRBM_PERF_SEL_RESERVED_1 = 21 GRBM_PERF_SEL_RESERVED_0 = 22 GRBM_PERF_SEL_IA_BUSY = 23 GRBM_PERF_SEL_IA_NO_DMA_BUSY = 24 GRBM_PERF_SEL_GDS_BUSY = 25 GRBM_PERF_SEL_BCI_BUSY = 26 GRBM_PERF_SEL_RLC_BUSY = 27 GRBM_PERF_SEL_TC_BUSY = 28 GRBM_PERF_SEL_CPG_BUSY = 29 GRBM_PERF_SEL_CPC_BUSY = 30 GRBM_PERF_SEL_CPF_BUSY = 31 GRBM_PERF_SEL_WD_BUSY = 32 GRBM_PERF_SEL_WD_NO_DMA_BUSY = 33 GRBM_PERF_SEL_UTCL2_BUSY = 34 GRBM_PERF_SEL_EA_BUSY = 35 GRBM_PERF_SEL_RMI_BUSY = 36 GRBM_PERF_SEL_CPAXI_BUSY = 37 GRBM_PERF_SEL = ctypes.c_uint32 # enum # values for enumeration 'GRBM_SE0_PERF_SEL' GRBM_SE0_PERF_SEL__enumvalues = { 0: 'GRBM_SE0_PERF_SEL_COUNT', 1: 'GRBM_SE0_PERF_SEL_USER_DEFINED', 2: 'GRBM_SE0_PERF_SEL_CB_BUSY', 3: 'GRBM_SE0_PERF_SEL_DB_BUSY', 4: 'GRBM_SE0_PERF_SEL_SC_BUSY', 5: 'GRBM_SE0_PERF_SEL_RESERVED_1', 6: 'GRBM_SE0_PERF_SEL_SPI_BUSY', 7: 'GRBM_SE0_PERF_SEL_SX_BUSY', 8: 'GRBM_SE0_PERF_SEL_TA_BUSY', 9: 'GRBM_SE0_PERF_SEL_CB_CLEAN', 10: 'GRBM_SE0_PERF_SEL_DB_CLEAN', 11: 'GRBM_SE0_PERF_SEL_RESERVED_0', 12: 'GRBM_SE0_PERF_SEL_PA_BUSY', 13: 'GRBM_SE0_PERF_SEL_VGT_BUSY', 14: 'GRBM_SE0_PERF_SEL_BCI_BUSY', 15: 'GRBM_SE0_PERF_SEL_RMI_BUSY', } GRBM_SE0_PERF_SEL_COUNT = 0 GRBM_SE0_PERF_SEL_USER_DEFINED = 1 GRBM_SE0_PERF_SEL_CB_BUSY = 2 GRBM_SE0_PERF_SEL_DB_BUSY = 3 GRBM_SE0_PERF_SEL_SC_BUSY = 4 GRBM_SE0_PERF_SEL_RESERVED_1 = 5 GRBM_SE0_PERF_SEL_SPI_BUSY = 6 GRBM_SE0_PERF_SEL_SX_BUSY = 7 GRBM_SE0_PERF_SEL_TA_BUSY = 8 GRBM_SE0_PERF_SEL_CB_CLEAN = 9 GRBM_SE0_PERF_SEL_DB_CLEAN = 10 GRBM_SE0_PERF_SEL_RESERVED_0 = 11 GRBM_SE0_PERF_SEL_PA_BUSY = 12 GRBM_SE0_PERF_SEL_VGT_BUSY = 13 GRBM_SE0_PERF_SEL_BCI_BUSY = 14 GRBM_SE0_PERF_SEL_RMI_BUSY = 15 GRBM_SE0_PERF_SEL = ctypes.c_uint32 # enum # values for enumeration 'GRBM_SE1_PERF_SEL' GRBM_SE1_PERF_SEL__enumvalues = { 0: 'GRBM_SE1_PERF_SEL_COUNT', 1: 'GRBM_SE1_PERF_SEL_USER_DEFINED', 2: 'GRBM_SE1_PERF_SEL_CB_BUSY', 3: 'GRBM_SE1_PERF_SEL_DB_BUSY', 4: 'GRBM_SE1_PERF_SEL_SC_BUSY', 5: 'GRBM_SE1_PERF_SEL_RESERVED_1', 6: 'GRBM_SE1_PERF_SEL_SPI_BUSY', 7: 'GRBM_SE1_PERF_SEL_SX_BUSY', 8: 'GRBM_SE1_PERF_SEL_TA_BUSY', 9: 'GRBM_SE1_PERF_SEL_CB_CLEAN', 10: 'GRBM_SE1_PERF_SEL_DB_CLEAN', 11: 'GRBM_SE1_PERF_SEL_RESERVED_0', 12: 'GRBM_SE1_PERF_SEL_PA_BUSY', 13: 'GRBM_SE1_PERF_SEL_VGT_BUSY', 14: 'GRBM_SE1_PERF_SEL_BCI_BUSY', 15: 'GRBM_SE1_PERF_SEL_RMI_BUSY', } GRBM_SE1_PERF_SEL_COUNT = 0 GRBM_SE1_PERF_SEL_USER_DEFINED = 1 GRBM_SE1_PERF_SEL_CB_BUSY = 2 GRBM_SE1_PERF_SEL_DB_BUSY = 3 GRBM_SE1_PERF_SEL_SC_BUSY = 4 GRBM_SE1_PERF_SEL_RESERVED_1 = 5 GRBM_SE1_PERF_SEL_SPI_BUSY = 6 GRBM_SE1_PERF_SEL_SX_BUSY = 7 GRBM_SE1_PERF_SEL_TA_BUSY = 8 GRBM_SE1_PERF_SEL_CB_CLEAN = 9 GRBM_SE1_PERF_SEL_DB_CLEAN = 10 GRBM_SE1_PERF_SEL_RESERVED_0 = 11 GRBM_SE1_PERF_SEL_PA_BUSY = 12 GRBM_SE1_PERF_SEL_VGT_BUSY = 13 GRBM_SE1_PERF_SEL_BCI_BUSY = 14 GRBM_SE1_PERF_SEL_RMI_BUSY = 15 GRBM_SE1_PERF_SEL = ctypes.c_uint32 # enum # values for enumeration 'GRBM_SE2_PERF_SEL' GRBM_SE2_PERF_SEL__enumvalues = { 0: 'GRBM_SE2_PERF_SEL_COUNT', 1: 'GRBM_SE2_PERF_SEL_USER_DEFINED', 2: 'GRBM_SE2_PERF_SEL_CB_BUSY', 3: 'GRBM_SE2_PERF_SEL_DB_BUSY', 4: 'GRBM_SE2_PERF_SEL_SC_BUSY', 5: 'GRBM_SE2_PERF_SEL_RESERVED_1', 6: 'GRBM_SE2_PERF_SEL_SPI_BUSY', 7: 'GRBM_SE2_PERF_SEL_SX_BUSY', 8: 'GRBM_SE2_PERF_SEL_TA_BUSY', 9: 'GRBM_SE2_PERF_SEL_CB_CLEAN', 10: 'GRBM_SE2_PERF_SEL_DB_CLEAN', 11: 'GRBM_SE2_PERF_SEL_RESERVED_0', 12: 'GRBM_SE2_PERF_SEL_PA_BUSY', 13: 'GRBM_SE2_PERF_SEL_VGT_BUSY', 14: 'GRBM_SE2_PERF_SEL_BCI_BUSY', 15: 'GRBM_SE2_PERF_SEL_RMI_BUSY', } GRBM_SE2_PERF_SEL_COUNT = 0 GRBM_SE2_PERF_SEL_USER_DEFINED = 1 GRBM_SE2_PERF_SEL_CB_BUSY = 2 GRBM_SE2_PERF_SEL_DB_BUSY = 3 GRBM_SE2_PERF_SEL_SC_BUSY = 4 GRBM_SE2_PERF_SEL_RESERVED_1 = 5 GRBM_SE2_PERF_SEL_SPI_BUSY = 6 GRBM_SE2_PERF_SEL_SX_BUSY = 7 GRBM_SE2_PERF_SEL_TA_BUSY = 8 GRBM_SE2_PERF_SEL_CB_CLEAN = 9 GRBM_SE2_PERF_SEL_DB_CLEAN = 10 GRBM_SE2_PERF_SEL_RESERVED_0 = 11 GRBM_SE2_PERF_SEL_PA_BUSY = 12 GRBM_SE2_PERF_SEL_VGT_BUSY = 13 GRBM_SE2_PERF_SEL_BCI_BUSY = 14 GRBM_SE2_PERF_SEL_RMI_BUSY = 15 GRBM_SE2_PERF_SEL = ctypes.c_uint32 # enum # values for enumeration 'GRBM_SE3_PERF_SEL' GRBM_SE3_PERF_SEL__enumvalues = { 0: 'GRBM_SE3_PERF_SEL_COUNT', 1: 'GRBM_SE3_PERF_SEL_USER_DEFINED', 2: 'GRBM_SE3_PERF_SEL_CB_BUSY', 3: 'GRBM_SE3_PERF_SEL_DB_BUSY', 4: 'GRBM_SE3_PERF_SEL_SC_BUSY', 5: 'GRBM_SE3_PERF_SEL_RESERVED_1', 6: 'GRBM_SE3_PERF_SEL_SPI_BUSY', 7: 'GRBM_SE3_PERF_SEL_SX_BUSY', 8: 'GRBM_SE3_PERF_SEL_TA_BUSY', 9: 'GRBM_SE3_PERF_SEL_CB_CLEAN', 10: 'GRBM_SE3_PERF_SEL_DB_CLEAN', 11: 'GRBM_SE3_PERF_SEL_RESERVED_0', 12: 'GRBM_SE3_PERF_SEL_PA_BUSY', 13: 'GRBM_SE3_PERF_SEL_VGT_BUSY', 14: 'GRBM_SE3_PERF_SEL_BCI_BUSY', 15: 'GRBM_SE3_PERF_SEL_RMI_BUSY', } GRBM_SE3_PERF_SEL_COUNT = 0 GRBM_SE3_PERF_SEL_USER_DEFINED = 1 GRBM_SE3_PERF_SEL_CB_BUSY = 2 GRBM_SE3_PERF_SEL_DB_BUSY = 3 GRBM_SE3_PERF_SEL_SC_BUSY = 4 GRBM_SE3_PERF_SEL_RESERVED_1 = 5 GRBM_SE3_PERF_SEL_SPI_BUSY = 6 GRBM_SE3_PERF_SEL_SX_BUSY = 7 GRBM_SE3_PERF_SEL_TA_BUSY = 8 GRBM_SE3_PERF_SEL_CB_CLEAN = 9 GRBM_SE3_PERF_SEL_DB_CLEAN = 10 GRBM_SE3_PERF_SEL_RESERVED_0 = 11 GRBM_SE3_PERF_SEL_PA_BUSY = 12 GRBM_SE3_PERF_SEL_VGT_BUSY = 13 GRBM_SE3_PERF_SEL_BCI_BUSY = 14 GRBM_SE3_PERF_SEL_RMI_BUSY = 15 GRBM_SE3_PERF_SEL = ctypes.c_uint32 # enum # values for enumeration 'CP_RING_ID' CP_RING_ID__enumvalues = { 0: 'RINGID0', 1: 'RINGID1', 2: 'RINGID2', 3: 'RINGID3', } RINGID0 = 0 RINGID1 = 1 RINGID2 = 2 RINGID3 = 3 CP_RING_ID = ctypes.c_uint32 # enum # values for enumeration 'CP_PIPE_ID' CP_PIPE_ID__enumvalues = { 0: 'PIPE_ID0', 1: 'PIPE_ID1', 2: 'PIPE_ID2', 3: 'PIPE_ID3', } PIPE_ID0 = 0 PIPE_ID1 = 1 PIPE_ID2 = 2 PIPE_ID3 = 3 CP_PIPE_ID = ctypes.c_uint32 # enum # values for enumeration 'CP_ME_ID' CP_ME_ID__enumvalues = { 0: 'ME_ID0', 1: 'ME_ID1', 2: 'ME_ID2', 3: 'ME_ID3', } ME_ID0 = 0 ME_ID1 = 1 ME_ID2 = 2 ME_ID3 = 3 CP_ME_ID = ctypes.c_uint32 # enum # values for enumeration 'SPM_PERFMON_STATE' SPM_PERFMON_STATE__enumvalues = { 0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET', 1: 'STRM_PERFMON_STATE_START_COUNTING', 2: 'STRM_PERFMON_STATE_STOP_COUNTING', 3: 'STRM_PERFMON_STATE_RESERVED_3', 4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', 5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', } STRM_PERFMON_STATE_DISABLE_AND_RESET = 0 STRM_PERFMON_STATE_START_COUNTING = 1 STRM_PERFMON_STATE_STOP_COUNTING = 2 STRM_PERFMON_STATE_RESERVED_3 = 3 STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 SPM_PERFMON_STATE = ctypes.c_uint32 # enum # values for enumeration 'CP_PERFMON_STATE' CP_PERFMON_STATE__enumvalues = { 0: 'CP_PERFMON_STATE_DISABLE_AND_RESET', 1: 'CP_PERFMON_STATE_START_COUNTING', 2: 'CP_PERFMON_STATE_STOP_COUNTING', 3: 'CP_PERFMON_STATE_RESERVED_3', 4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', 5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', } CP_PERFMON_STATE_DISABLE_AND_RESET = 0 CP_PERFMON_STATE_START_COUNTING = 1 CP_PERFMON_STATE_STOP_COUNTING = 2 CP_PERFMON_STATE_RESERVED_3 = 3 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 CP_PERFMON_STATE = ctypes.c_uint32 # enum # values for enumeration 'CP_PERFMON_ENABLE_MODE' CP_PERFMON_ENABLE_MODE__enumvalues = { 0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', 1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', 3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', } CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0 CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3 CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum # values for enumeration 'CPG_PERFCOUNT_SEL' CPG_PERFCOUNT_SEL__enumvalues = { 0: 'CPG_PERF_SEL_ALWAYS_COUNT', 1: 'CPG_PERF_SEL_RBIU_FIFO_FULL', 2: 'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR', 3: 'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL', 4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', 5: 'CPG_PERF_SEL_ME_PARSER_BUSY', 6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', 7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 8: 'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', 9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', 10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', 11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', 12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', 13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', 14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', 15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', 16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', 17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', 18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', 19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', 20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', 21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', 22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', 23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', 24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', 25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', 26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', 27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', 28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', 29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', 30: 'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS', 31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', 32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', 33: 'CPG_PERF_SEL_REGISTER_CLK_VALID', 34: 'CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT', 35: 'CPG_PERF_SEL_MIU_READ_REQUEST_SENT', 36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', 37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', 38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', 39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', 40: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU', 41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', 42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', 43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', 44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', 45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', 46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', 47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', } CPG_PERF_SEL_ALWAYS_COUNT = 0 CPG_PERF_SEL_RBIU_FIFO_FULL = 1 CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 2 CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 3 CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4 CPG_PERF_SEL_ME_PARSER_BUSY = 5 CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6 CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7 CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 8 CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10 CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11 CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12 CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13 CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14 CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17 CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18 CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19 CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20 CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23 CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24 CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25 CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26 CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27 CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28 CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29 CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 30 CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31 CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32 CPG_PERF_SEL_REGISTER_CLK_VALID = 33 CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 34 CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 35 CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36 CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37 CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38 CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 40 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41 CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42 CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47 CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48 CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum # values for enumeration 'CPF_PERFCOUNT_SEL' CPF_PERFCOUNT_SEL__enumvalues = { 0: 'CPF_PERF_SEL_ALWAYS_COUNT', 1: 'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE', 2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', 3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', 4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', 5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', 6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', 7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE', 8: 'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS', 9: 'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR', 10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', 11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', 12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT', 13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', 14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', 15: 'CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND', 16: 'CPF_PERF_SEL_MIU_READ_REQUEST_SEND', 17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', 18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 19: 'CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', 20: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', } CPF_PERF_SEL_ALWAYS_COUNT = 0 CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 1 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6 CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 7 CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 8 CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 9 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10 CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11 CPF_PERF_SEL_GRBM_DWORDS_SENT = 12 CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13 CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14 CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 15 CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 16 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18 CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 19 CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 20 CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum # values for enumeration 'CPC_PERFCOUNT_SEL' CPC_PERFCOUNT_SEL__enumvalues = { 0: 'CPC_PERF_SEL_ALWAYS_COUNT', 1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', 2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', 3: 'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE', 4: 'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE', 5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', 6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', 7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', 8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', 9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ', 10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE', 11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', 12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', 13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', 14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', 15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', 16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', 17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ', 18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE', 19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', 20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', 21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', 22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', 23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', } CPC_PERF_SEL_ALWAYS_COUNT = 0 CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1 CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2 CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 3 CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 4 CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 9 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 10 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12 CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 17 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 18 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20 CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23 CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24 CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum # values for enumeration 'CP_ALPHA_TAG_RAM_SEL' CP_ALPHA_TAG_RAM_SEL__enumvalues = { 0: 'CPG_TAG_RAM', 1: 'CPC_TAG_RAM', 2: 'CPF_TAG_RAM', 3: 'RSV_TAG_RAM', } CPG_TAG_RAM = 0 CPC_TAG_RAM = 1 CPF_TAG_RAM = 2 RSV_TAG_RAM = 3 CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum # values for enumeration 'SX_BLEND_OPT' SX_BLEND_OPT__enumvalues = { 0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', 1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', 2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', 3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', 4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', 5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', 6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', 7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', } BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0 BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1 BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2 BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3 BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4 BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5 BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6 BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7 SX_BLEND_OPT = ctypes.c_uint32 # enum # values for enumeration 'SX_OPT_COMB_FCN' SX_OPT_COMB_FCN__enumvalues = { 0: 'OPT_COMB_NONE', 1: 'OPT_COMB_ADD', 2: 'OPT_COMB_SUBTRACT', 3: 'OPT_COMB_MIN', 4: 'OPT_COMB_MAX', 5: 'OPT_COMB_REVSUBTRACT', 6: 'OPT_COMB_BLEND_DISABLED', 7: 'OPT_COMB_SAFE_ADD', } OPT_COMB_NONE = 0 OPT_COMB_ADD = 1 OPT_COMB_SUBTRACT = 2 OPT_COMB_MIN = 3 OPT_COMB_MAX = 4 OPT_COMB_REVSUBTRACT = 5 OPT_COMB_BLEND_DISABLED = 6 OPT_COMB_SAFE_ADD = 7 SX_OPT_COMB_FCN = ctypes.c_uint32 # enum # values for enumeration 'SX_DOWNCONVERT_FORMAT' SX_DOWNCONVERT_FORMAT__enumvalues = { 0: 'SX_RT_EXPORT_NO_CONVERSION', 1: 'SX_RT_EXPORT_32_R', 2: 'SX_RT_EXPORT_32_A', 3: 'SX_RT_EXPORT_10_11_11', 4: 'SX_RT_EXPORT_2_10_10_10', 5: 'SX_RT_EXPORT_8_8_8_8', 6: 'SX_RT_EXPORT_5_6_5', 7: 'SX_RT_EXPORT_1_5_5_5', 8: 'SX_RT_EXPORT_4_4_4_4', 9: 'SX_RT_EXPORT_16_16_GR', 10: 'SX_RT_EXPORT_16_16_AR', } SX_RT_EXPORT_NO_CONVERSION = 0 SX_RT_EXPORT_32_R = 1 SX_RT_EXPORT_32_A = 2 SX_RT_EXPORT_10_11_11 = 3 SX_RT_EXPORT_2_10_10_10 = 4 SX_RT_EXPORT_8_8_8_8 = 5 SX_RT_EXPORT_5_6_5 = 6 SX_RT_EXPORT_1_5_5_5 = 7 SX_RT_EXPORT_4_4_4_4 = 8 SX_RT_EXPORT_16_16_GR = 9 SX_RT_EXPORT_16_16_AR = 10 SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'SX_PERFCOUNTER_VALS' SX_PERFCOUNTER_VALS__enumvalues = { 0: 'SX_PERF_SEL_PA_IDLE_CYCLES', 1: 'SX_PERF_SEL_PA_REQ', 2: 'SX_PERF_SEL_PA_POS', 3: 'SX_PERF_SEL_CLOCK', 4: 'SX_PERF_SEL_GATE_EN1', 5: 'SX_PERF_SEL_GATE_EN2', 6: 'SX_PERF_SEL_GATE_EN3', 7: 'SX_PERF_SEL_GATE_EN4', 8: 'SX_PERF_SEL_SH_POS_STARVE', 9: 'SX_PERF_SEL_SH_COLOR_STARVE', 10: 'SX_PERF_SEL_SH_POS_STALL', 11: 'SX_PERF_SEL_SH_COLOR_STALL', 12: 'SX_PERF_SEL_DB0_PIXELS', 13: 'SX_PERF_SEL_DB0_HALF_QUADS', 14: 'SX_PERF_SEL_DB0_PIXEL_STALL', 15: 'SX_PERF_SEL_DB0_PIXEL_IDLE', 16: 'SX_PERF_SEL_DB0_PRED_PIXELS', 17: 'SX_PERF_SEL_DB1_PIXELS', 18: 'SX_PERF_SEL_DB1_HALF_QUADS', 19: 'SX_PERF_SEL_DB1_PIXEL_STALL', 20: 'SX_PERF_SEL_DB1_PIXEL_IDLE', 21: 'SX_PERF_SEL_DB1_PRED_PIXELS', 22: 'SX_PERF_SEL_DB2_PIXELS', 23: 'SX_PERF_SEL_DB2_HALF_QUADS', 24: 'SX_PERF_SEL_DB2_PIXEL_STALL', 25: 'SX_PERF_SEL_DB2_PIXEL_IDLE', 26: 'SX_PERF_SEL_DB2_PRED_PIXELS', 27: 'SX_PERF_SEL_DB3_PIXELS', 28: 'SX_PERF_SEL_DB3_HALF_QUADS', 29: 'SX_PERF_SEL_DB3_PIXEL_STALL', 30: 'SX_PERF_SEL_DB3_PIXEL_IDLE', 31: 'SX_PERF_SEL_DB3_PRED_PIXELS', 32: 'SX_PERF_SEL_COL_BUSY', 33: 'SX_PERF_SEL_POS_BUSY', 34: 'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS', 35: 'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS', 36: 'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST', 37: 'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC', 38: 'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS', 39: 'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS', 40: 'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS', 41: 'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST', 42: 'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC', 43: 'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS', 44: 'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS', 45: 'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS', 46: 'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST', 47: 'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC', 48: 'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS', 49: 'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS', 50: 'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS', 51: 'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST', 52: 'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC', 53: 'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS', 54: 'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS', 55: 'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS', 56: 'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST', 57: 'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC', 58: 'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS', 59: 'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS', 60: 'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS', 61: 'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST', 62: 'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC', 63: 'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS', 64: 'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS', 65: 'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS', 66: 'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST', 67: 'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC', 68: 'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS', 69: 'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS', 70: 'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS', 71: 'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST', 72: 'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC', 73: 'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS', 74: 'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS', 75: 'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS', 76: 'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS', 77: 'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST', 78: 'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC', 79: 'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS', 80: 'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS', 81: 'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS', 82: 'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST', 83: 'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC', 84: 'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS', 85: 'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS', 86: 'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS', 87: 'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST', 88: 'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC', 89: 'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS', 90: 'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS', 91: 'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS', 92: 'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST', 93: 'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC', 94: 'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS', 95: 'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS', 96: 'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS', 97: 'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST', 98: 'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC', 99: 'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS', 100: 'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS', 101: 'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS', 102: 'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST', 103: 'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC', 104: 'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS', 105: 'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS', 106: 'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS', 107: 'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST', 108: 'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC', 109: 'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS', 110: 'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS', 111: 'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS', 112: 'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST', 113: 'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC', 114: 'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS', 115: 'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS', 116: 'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS', 117: 'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS', 118: 'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST', 119: 'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC', 120: 'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS', 121: 'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS', 122: 'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS', 123: 'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST', 124: 'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC', 125: 'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS', 126: 'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS', 127: 'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS', 128: 'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST', 129: 'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC', 130: 'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS', 131: 'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS', 132: 'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS', 133: 'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST', 134: 'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC', 135: 'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS', 136: 'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS', 137: 'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS', 138: 'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST', 139: 'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC', 140: 'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS', 141: 'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS', 142: 'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS', 143: 'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST', 144: 'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC', 145: 'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS', 146: 'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS', 147: 'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS', 148: 'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST', 149: 'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC', 150: 'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS', 151: 'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS', 152: 'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS', 153: 'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST', 154: 'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC', 155: 'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS', 156: 'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS', 157: 'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS', 158: 'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS', 159: 'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST', 160: 'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC', 161: 'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS', 162: 'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS', 163: 'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS', 164: 'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST', 165: 'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC', 166: 'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS', 167: 'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS', 168: 'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS', 169: 'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST', 170: 'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC', 171: 'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS', 172: 'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS', 173: 'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS', 174: 'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST', 175: 'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC', 176: 'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS', 177: 'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS', 178: 'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS', 179: 'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST', 180: 'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC', 181: 'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS', 182: 'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS', 183: 'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS', 184: 'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST', 185: 'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC', 186: 'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS', 187: 'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS', 188: 'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS', 189: 'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST', 190: 'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC', 191: 'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS', 192: 'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS', 193: 'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS', 194: 'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST', 195: 'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC', 196: 'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS', 197: 'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS', } SX_PERF_SEL_PA_IDLE_CYCLES = 0 SX_PERF_SEL_PA_REQ = 1 SX_PERF_SEL_PA_POS = 2 SX_PERF_SEL_CLOCK = 3 SX_PERF_SEL_GATE_EN1 = 4 SX_PERF_SEL_GATE_EN2 = 5 SX_PERF_SEL_GATE_EN3 = 6 SX_PERF_SEL_GATE_EN4 = 7 SX_PERF_SEL_SH_POS_STARVE = 8 SX_PERF_SEL_SH_COLOR_STARVE = 9 SX_PERF_SEL_SH_POS_STALL = 10 SX_PERF_SEL_SH_COLOR_STALL = 11 SX_PERF_SEL_DB0_PIXELS = 12 SX_PERF_SEL_DB0_HALF_QUADS = 13 SX_PERF_SEL_DB0_PIXEL_STALL = 14 SX_PERF_SEL_DB0_PIXEL_IDLE = 15 SX_PERF_SEL_DB0_PRED_PIXELS = 16 SX_PERF_SEL_DB1_PIXELS = 17 SX_PERF_SEL_DB1_HALF_QUADS = 18 SX_PERF_SEL_DB1_PIXEL_STALL = 19 SX_PERF_SEL_DB1_PIXEL_IDLE = 20 SX_PERF_SEL_DB1_PRED_PIXELS = 21 SX_PERF_SEL_DB2_PIXELS = 22 SX_PERF_SEL_DB2_HALF_QUADS = 23 SX_PERF_SEL_DB2_PIXEL_STALL = 24 SX_PERF_SEL_DB2_PIXEL_IDLE = 25 SX_PERF_SEL_DB2_PRED_PIXELS = 26 SX_PERF_SEL_DB3_PIXELS = 27 SX_PERF_SEL_DB3_HALF_QUADS = 28 SX_PERF_SEL_DB3_PIXEL_STALL = 29 SX_PERF_SEL_DB3_PIXEL_IDLE = 30 SX_PERF_SEL_DB3_PRED_PIXELS = 31 SX_PERF_SEL_COL_BUSY = 32 SX_PERF_SEL_POS_BUSY = 33 SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 34 SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 35 SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 36 SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 37 SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 38 SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 39 SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 40 SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 41 SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 42 SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 43 SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 44 SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 45 SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 46 SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 47 SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 48 SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 49 SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 50 SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 51 SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 52 SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 53 SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 54 SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 55 SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 56 SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 57 SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 58 SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 59 SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 60 SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 61 SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 62 SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 63 SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 64 SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 65 SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 66 SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 67 SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 68 SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 69 SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 70 SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 71 SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 72 SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 73 SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 74 SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 75 SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 76 SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 77 SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 78 SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 79 SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 80 SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 81 SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 82 SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 83 SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 84 SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 85 SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 86 SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 87 SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 88 SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 89 SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 90 SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 91 SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 92 SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 93 SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 94 SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 95 SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 96 SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 97 SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 98 SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 99 SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 100 SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 101 SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 102 SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 103 SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 104 SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 105 SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 106 SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 107 SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 108 SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 109 SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 110 SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 111 SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 112 SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 113 SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 114 SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 115 SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 116 SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 117 SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 118 SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 119 SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 120 SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 121 SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 122 SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 123 SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 124 SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 125 SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 126 SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 127 SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 128 SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 129 SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 130 SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 131 SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 132 SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 133 SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 134 SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 135 SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 136 SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 137 SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 138 SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 139 SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 140 SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 141 SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 142 SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 143 SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 144 SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 145 SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 146 SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 147 SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 148 SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 149 SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 150 SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 151 SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 152 SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 153 SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 154 SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 155 SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 156 SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 157 SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 158 SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 159 SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 160 SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 161 SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 162 SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 163 SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 164 SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 165 SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 166 SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 167 SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 168 SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 169 SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 170 SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 171 SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 172 SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 173 SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 174 SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 175 SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 176 SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 177 SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 178 SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 179 SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 180 SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 181 SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 182 SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 183 SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 184 SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 185 SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 186 SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 187 SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 188 SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 189 SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 190 SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 191 SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 192 SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 193 SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 194 SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 195 SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 196 SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 197 SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum # values for enumeration 'ForceControl' ForceControl__enumvalues = { 0: 'FORCE_OFF', 1: 'FORCE_ENABLE', 2: 'FORCE_DISABLE', 3: 'FORCE_RESERVED', } FORCE_OFF = 0 FORCE_ENABLE = 1 FORCE_DISABLE = 2 FORCE_RESERVED = 3 ForceControl = ctypes.c_uint32 # enum # values for enumeration 'ZSamplePosition' ZSamplePosition__enumvalues = { 0: 'Z_SAMPLE_CENTER', 1: 'Z_SAMPLE_CENTROID', } Z_SAMPLE_CENTER = 0 Z_SAMPLE_CENTROID = 1 ZSamplePosition = ctypes.c_uint32 # enum # values for enumeration 'ZOrder' ZOrder__enumvalues = { 0: 'LATE_Z', 1: 'EARLY_Z_THEN_LATE_Z', 2: 'RE_Z', 3: 'EARLY_Z_THEN_RE_Z', } LATE_Z = 0 EARLY_Z_THEN_LATE_Z = 1 RE_Z = 2 EARLY_Z_THEN_RE_Z = 3 ZOrder = ctypes.c_uint32 # enum # values for enumeration 'ZpassControl' ZpassControl__enumvalues = { 0: 'ZPASS_DISABLE', 1: 'ZPASS_SAMPLES', 2: 'ZPASS_PIXELS', } ZPASS_DISABLE = 0 ZPASS_SAMPLES = 1 ZPASS_PIXELS = 2 ZpassControl = ctypes.c_uint32 # enum # values for enumeration 'ZModeForce' ZModeForce__enumvalues = { 0: 'NO_FORCE', 1: 'FORCE_EARLY_Z', 2: 'FORCE_LATE_Z', 3: 'FORCE_RE_Z', } NO_FORCE = 0 FORCE_EARLY_Z = 1 FORCE_LATE_Z = 2 FORCE_RE_Z = 3 ZModeForce = ctypes.c_uint32 # enum # values for enumeration 'ZLimitSumm' ZLimitSumm__enumvalues = { 0: 'FORCE_SUMM_OFF', 1: 'FORCE_SUMM_MINZ', 2: 'FORCE_SUMM_MAXZ', 3: 'FORCE_SUMM_BOTH', } FORCE_SUMM_OFF = 0 FORCE_SUMM_MINZ = 1 FORCE_SUMM_MAXZ = 2 FORCE_SUMM_BOTH = 3 ZLimitSumm = ctypes.c_uint32 # enum # values for enumeration 'CompareFrag' CompareFrag__enumvalues = { 0: 'FRAG_NEVER', 1: 'FRAG_LESS', 2: 'FRAG_EQUAL', 3: 'FRAG_LEQUAL', 4: 'FRAG_GREATER', 5: 'FRAG_NOTEQUAL', 6: 'FRAG_GEQUAL', 7: 'FRAG_ALWAYS', } FRAG_NEVER = 0 FRAG_LESS = 1 FRAG_EQUAL = 2 FRAG_LEQUAL = 3 FRAG_GREATER = 4 FRAG_NOTEQUAL = 5 FRAG_GEQUAL = 6 FRAG_ALWAYS = 7 CompareFrag = ctypes.c_uint32 # enum # values for enumeration 'StencilOp' StencilOp__enumvalues = { 0: 'STENCIL_KEEP', 1: 'STENCIL_ZERO', 2: 'STENCIL_ONES', 3: 'STENCIL_REPLACE_TEST', 4: 'STENCIL_REPLACE_OP', 5: 'STENCIL_ADD_CLAMP', 6: 'STENCIL_SUB_CLAMP', 7: 'STENCIL_INVERT', 8: 'STENCIL_ADD_WRAP', 9: 'STENCIL_SUB_WRAP', 10: 'STENCIL_AND', 11: 'STENCIL_OR', 12: 'STENCIL_XOR', 13: 'STENCIL_NAND', 14: 'STENCIL_NOR', 15: 'STENCIL_XNOR', } STENCIL_KEEP = 0 STENCIL_ZERO = 1 STENCIL_ONES = 2 STENCIL_REPLACE_TEST = 3 STENCIL_REPLACE_OP = 4 STENCIL_ADD_CLAMP = 5 STENCIL_SUB_CLAMP = 6 STENCIL_INVERT = 7 STENCIL_ADD_WRAP = 8 STENCIL_SUB_WRAP = 9 STENCIL_AND = 10 STENCIL_OR = 11 STENCIL_XOR = 12 STENCIL_NAND = 13 STENCIL_NOR = 14 STENCIL_XNOR = 15 StencilOp = ctypes.c_uint32 # enum # values for enumeration 'ConservativeZExport' ConservativeZExport__enumvalues = { 0: 'EXPORT_ANY_Z', 1: 'EXPORT_LESS_THAN_Z', 2: 'EXPORT_GREATER_THAN_Z', 3: 'EXPORT_RESERVED', } EXPORT_ANY_Z = 0 EXPORT_LESS_THAN_Z = 1 EXPORT_GREATER_THAN_Z = 2 EXPORT_RESERVED = 3 ConservativeZExport = ctypes.c_uint32 # enum # values for enumeration 'DbPSLControl' DbPSLControl__enumvalues = { 0: 'PSLC_AUTO', 1: 'PSLC_ON_HANG_ONLY', 2: 'PSLC_ASAP', 3: 'PSLC_COUNTDOWN', } PSLC_AUTO = 0 PSLC_ON_HANG_ONLY = 1 PSLC_ASAP = 2 PSLC_COUNTDOWN = 3 DbPSLControl = ctypes.c_uint32 # enum # values for enumeration 'DbPRTFaultBehavior' DbPRTFaultBehavior__enumvalues = { 0: 'FAULT_ZERO', 1: 'FAULT_ONE', 2: 'FAULT_FAIL', 3: 'FAULT_PASS', } FAULT_ZERO = 0 FAULT_ONE = 1 FAULT_FAIL = 2 FAULT_PASS = 3 DbPRTFaultBehavior = ctypes.c_uint32 # enum # values for enumeration 'PerfCounter_Vals' PerfCounter_Vals__enumvalues = { 0: 'DB_PERF_SEL_SC_DB_tile_sends', 1: 'DB_PERF_SEL_SC_DB_tile_busy', 2: 'DB_PERF_SEL_SC_DB_tile_stalls', 3: 'DB_PERF_SEL_SC_DB_tile_events', 4: 'DB_PERF_SEL_SC_DB_tile_tiles', 5: 'DB_PERF_SEL_SC_DB_tile_covered', 6: 'DB_PERF_SEL_hiz_tc_read_starved', 7: 'DB_PERF_SEL_hiz_tc_write_stall', 8: 'DB_PERF_SEL_hiz_qtiles_culled', 9: 'DB_PERF_SEL_his_qtiles_culled', 10: 'DB_PERF_SEL_DB_SC_tile_sends', 11: 'DB_PERF_SEL_DB_SC_tile_busy', 12: 'DB_PERF_SEL_DB_SC_tile_stalls', 13: 'DB_PERF_SEL_DB_SC_tile_df_stalls', 14: 'DB_PERF_SEL_DB_SC_tile_tiles', 15: 'DB_PERF_SEL_DB_SC_tile_culled', 16: 'DB_PERF_SEL_DB_SC_tile_hier_kill', 17: 'DB_PERF_SEL_DB_SC_tile_fast_ops', 18: 'DB_PERF_SEL_DB_SC_tile_no_ops', 19: 'DB_PERF_SEL_DB_SC_tile_tile_rate', 20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', 21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', 22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', 23: 'DB_PERF_SEL_SC_DB_quad_sends', 24: 'DB_PERF_SEL_SC_DB_quad_busy', 25: 'DB_PERF_SEL_SC_DB_quad_squads', 26: 'DB_PERF_SEL_SC_DB_quad_tiles', 27: 'DB_PERF_SEL_SC_DB_quad_pixels', 28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles', 29: 'DB_PERF_SEL_DB_SC_quad_sends', 30: 'DB_PERF_SEL_DB_SC_quad_busy', 31: 'DB_PERF_SEL_DB_SC_quad_stalls', 32: 'DB_PERF_SEL_DB_SC_quad_tiles', 33: 'DB_PERF_SEL_DB_SC_quad_lit_quad', 34: 'DB_PERF_SEL_DB_CB_tile_sends', 35: 'DB_PERF_SEL_DB_CB_tile_busy', 36: 'DB_PERF_SEL_DB_CB_tile_stalls', 37: 'DB_PERF_SEL_SX_DB_quad_sends', 38: 'DB_PERF_SEL_SX_DB_quad_busy', 39: 'DB_PERF_SEL_SX_DB_quad_stalls', 40: 'DB_PERF_SEL_SX_DB_quad_quads', 41: 'DB_PERF_SEL_SX_DB_quad_pixels', 42: 'DB_PERF_SEL_SX_DB_quad_exports', 43: 'DB_PERF_SEL_SH_quads_outstanding_sum', 44: 'DB_PERF_SEL_DB_CB_lquad_sends', 45: 'DB_PERF_SEL_DB_CB_lquad_busy', 46: 'DB_PERF_SEL_DB_CB_lquad_stalls', 47: 'DB_PERF_SEL_DB_CB_lquad_quads', 48: 'DB_PERF_SEL_tile_rd_sends', 49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', 50: 'DB_PERF_SEL_quad_rd_sends', 51: 'DB_PERF_SEL_quad_rd_busy', 52: 'DB_PERF_SEL_quad_rd_mi_stall', 53: 'DB_PERF_SEL_quad_rd_rw_collision', 54: 'DB_PERF_SEL_quad_rd_tag_stall', 55: 'DB_PERF_SEL_quad_rd_32byte_reqs', 56: 'DB_PERF_SEL_quad_rd_panic', 57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', 58: 'DB_PERF_SEL_quad_rdret_sends', 59: 'DB_PERF_SEL_quad_rdret_busy', 60: 'DB_PERF_SEL_tile_wr_sends', 61: 'DB_PERF_SEL_tile_wr_acks', 62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', 63: 'DB_PERF_SEL_quad_wr_sends', 64: 'DB_PERF_SEL_quad_wr_busy', 65: 'DB_PERF_SEL_quad_wr_mi_stall', 66: 'DB_PERF_SEL_quad_wr_coherency_stall', 67: 'DB_PERF_SEL_quad_wr_acks', 68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', 69: 'DB_PERF_SEL_Tile_Cache_misses', 70: 'DB_PERF_SEL_Tile_Cache_hits', 71: 'DB_PERF_SEL_Tile_Cache_flushes', 72: 'DB_PERF_SEL_Tile_Cache_surface_stall', 73: 'DB_PERF_SEL_Tile_Cache_starves', 74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve', 75: 'DB_PERF_SEL_tcp_dispatcher_reads', 76: 'DB_PERF_SEL_tcp_prefetcher_reads', 77: 'DB_PERF_SEL_tcp_preloader_reads', 78: 'DB_PERF_SEL_tcp_dispatcher_flushes', 79: 'DB_PERF_SEL_tcp_prefetcher_flushes', 80: 'DB_PERF_SEL_tcp_preloader_flushes', 81: 'DB_PERF_SEL_Depth_Tile_Cache_sends', 82: 'DB_PERF_SEL_Depth_Tile_Cache_busy', 83: 'DB_PERF_SEL_Depth_Tile_Cache_starves', 84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', 85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', 86: 'DB_PERF_SEL_Depth_Tile_Cache_misses', 87: 'DB_PERF_SEL_Depth_Tile_Cache_hits', 88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes', 89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', 90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', 91: 'DB_PERF_SEL_Depth_Tile_Cache_event', 92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', 93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', 94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', 95: 'DB_PERF_SEL_Stencil_Cache_misses', 96: 'DB_PERF_SEL_Stencil_Cache_hits', 97: 'DB_PERF_SEL_Stencil_Cache_flushes', 98: 'DB_PERF_SEL_Stencil_Cache_starves', 99: 'DB_PERF_SEL_Stencil_Cache_frees', 100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses', 101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits', 102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', 103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves', 104: 'DB_PERF_SEL_Z_Cache_pmask_misses', 105: 'DB_PERF_SEL_Z_Cache_pmask_hits', 106: 'DB_PERF_SEL_Z_Cache_pmask_flushes', 107: 'DB_PERF_SEL_Z_Cache_pmask_starves', 108: 'DB_PERF_SEL_Z_Cache_frees', 109: 'DB_PERF_SEL_Plane_Cache_misses', 110: 'DB_PERF_SEL_Plane_Cache_hits', 111: 'DB_PERF_SEL_Plane_Cache_flushes', 112: 'DB_PERF_SEL_Plane_Cache_starves', 113: 'DB_PERF_SEL_Plane_Cache_frees', 114: 'DB_PERF_SEL_flush_expanded_stencil', 115: 'DB_PERF_SEL_flush_compressed_stencil', 116: 'DB_PERF_SEL_flush_single_stencil', 117: 'DB_PERF_SEL_planes_flushed', 118: 'DB_PERF_SEL_flush_1plane', 119: 'DB_PERF_SEL_flush_2plane', 120: 'DB_PERF_SEL_flush_3plane', 121: 'DB_PERF_SEL_flush_4plane', 122: 'DB_PERF_SEL_flush_5plane', 123: 'DB_PERF_SEL_flush_6plane', 124: 'DB_PERF_SEL_flush_7plane', 125: 'DB_PERF_SEL_flush_8plane', 126: 'DB_PERF_SEL_flush_9plane', 127: 'DB_PERF_SEL_flush_10plane', 128: 'DB_PERF_SEL_flush_11plane', 129: 'DB_PERF_SEL_flush_12plane', 130: 'DB_PERF_SEL_flush_13plane', 131: 'DB_PERF_SEL_flush_14plane', 132: 'DB_PERF_SEL_flush_15plane', 133: 'DB_PERF_SEL_flush_16plane', 134: 'DB_PERF_SEL_flush_expanded_z', 135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', 136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done', 137: 'DB_PERF_SEL_dk_tile_sends', 138: 'DB_PERF_SEL_dk_tile_busy', 139: 'DB_PERF_SEL_dk_tile_quad_starves', 140: 'DB_PERF_SEL_dk_tile_stalls', 141: 'DB_PERF_SEL_dk_squad_sends', 142: 'DB_PERF_SEL_dk_squad_busy', 143: 'DB_PERF_SEL_dk_squad_stalls', 144: 'DB_PERF_SEL_Op_Pipe_Busy', 145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', 146: 'DB_PERF_SEL_qc_busy', 147: 'DB_PERF_SEL_qc_xfc', 148: 'DB_PERF_SEL_qc_conflicts', 149: 'DB_PERF_SEL_qc_full_stall', 150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', 152: 'DB_PERF_SEL_tsc_insert_summarize_stall', 153: 'DB_PERF_SEL_tl_busy', 154: 'DB_PERF_SEL_tl_dtc_read_starved', 155: 'DB_PERF_SEL_tl_z_fetch_stall', 156: 'DB_PERF_SEL_tl_stencil_stall', 157: 'DB_PERF_SEL_tl_z_decompress_stall', 158: 'DB_PERF_SEL_tl_stencil_locked_stall', 159: 'DB_PERF_SEL_tl_events', 160: 'DB_PERF_SEL_tl_summarize_squads', 161: 'DB_PERF_SEL_tl_flush_expand_squads', 162: 'DB_PERF_SEL_tl_expand_squads', 163: 'DB_PERF_SEL_tl_preZ_squads', 164: 'DB_PERF_SEL_tl_postZ_squads', 165: 'DB_PERF_SEL_tl_preZ_noop_squads', 166: 'DB_PERF_SEL_tl_postZ_noop_squads', 167: 'DB_PERF_SEL_tl_tile_ops', 168: 'DB_PERF_SEL_tl_in_xfc', 169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', 170: 'DB_PERF_SEL_tl_in_fast_z_stall', 171: 'DB_PERF_SEL_tl_out_xfc', 172: 'DB_PERF_SEL_tl_out_squads', 173: 'DB_PERF_SEL_zf_plane_multicycle', 174: 'DB_PERF_SEL_PostZ_Samples_passing_Z', 175: 'DB_PERF_SEL_PostZ_Samples_failing_Z', 176: 'DB_PERF_SEL_PostZ_Samples_failing_S', 177: 'DB_PERF_SEL_PreZ_Samples_passing_Z', 178: 'DB_PERF_SEL_PreZ_Samples_failing_Z', 179: 'DB_PERF_SEL_PreZ_Samples_failing_S', 180: 'DB_PERF_SEL_ts_tc_update_stall', 181: 'DB_PERF_SEL_sc_kick_start', 182: 'DB_PERF_SEL_sc_kick_end', 183: 'DB_PERF_SEL_clock_reg_active', 184: 'DB_PERF_SEL_clock_main_active', 185: 'DB_PERF_SEL_clock_mem_export_active', 186: 'DB_PERF_SEL_esr_ps_out_busy', 187: 'DB_PERF_SEL_esr_ps_lqf_busy', 188: 'DB_PERF_SEL_esr_ps_lqf_stall', 189: 'DB_PERF_SEL_etr_out_send', 190: 'DB_PERF_SEL_etr_out_busy', 191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', 192: 'DB_PERF_SEL_etr_out_cb_tile_stall', 193: 'DB_PERF_SEL_etr_out_esr_stall', 194: 'DB_PERF_SEL_esr_ps_sqq_busy', 195: 'DB_PERF_SEL_esr_ps_sqq_stall', 196: 'DB_PERF_SEL_esr_eot_fwd_busy', 197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad', 198: 'DB_PERF_SEL_esr_eot_fwd_forward', 199: 'DB_PERF_SEL_esr_sqq_zi_busy', 200: 'DB_PERF_SEL_esr_sqq_zi_stall', 201: 'DB_PERF_SEL_postzl_sq_pt_busy', 202: 'DB_PERF_SEL_postzl_sq_pt_stall', 203: 'DB_PERF_SEL_postzl_se_busy', 204: 'DB_PERF_SEL_postzl_se_stall', 205: 'DB_PERF_SEL_postzl_partial_launch', 206: 'DB_PERF_SEL_postzl_full_launch', 207: 'DB_PERF_SEL_postzl_partial_waiting', 208: 'DB_PERF_SEL_postzl_tile_mem_stall', 209: 'DB_PERF_SEL_postzl_tile_init_stall', 210: 'DB_PEFF_SEL_prezl_tile_mem_stall', 211: 'DB_PERF_SEL_prezl_tile_init_stall', 212: 'DB_PERF_SEL_dtt_sm_clash_stall', 213: 'DB_PERF_SEL_dtt_sm_slot_stall', 214: 'DB_PERF_SEL_dtt_sm_miss_stall', 215: 'DB_PERF_SEL_mi_rdreq_busy', 216: 'DB_PERF_SEL_mi_rdreq_stall', 217: 'DB_PERF_SEL_mi_wrreq_busy', 218: 'DB_PERF_SEL_mi_wrreq_stall', 219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', 220: 'DB_PERF_SEL_dkg_tile_rate_tile', 221: 'DB_PERF_SEL_prezl_src_in_sends', 222: 'DB_PERF_SEL_prezl_src_in_stall', 223: 'DB_PERF_SEL_prezl_src_in_squads', 224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled', 225: 'DB_PERF_SEL_prezl_src_in_tile_rate', 226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', 227: 'DB_PERF_SEL_prezl_src_out_stall', 228: 'DB_PERF_SEL_postzl_src_in_sends', 229: 'DB_PERF_SEL_postzl_src_in_stall', 230: 'DB_PERF_SEL_postzl_src_in_squads', 231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled', 232: 'DB_PERF_SEL_postzl_src_in_tile_rate', 233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', 234: 'DB_PERF_SEL_postzl_src_out_stall', 235: 'DB_PERF_SEL_esr_ps_src_in_sends', 236: 'DB_PERF_SEL_esr_ps_src_in_stall', 237: 'DB_PERF_SEL_esr_ps_src_in_squads', 238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', 239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate', 240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', 241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', 242: 'DB_PERF_SEL_esr_ps_src_out_stall', 243: 'DB_PERF_SEL_depth_bounds_qtiles_culled', 244: 'DB_PERF_SEL_PreZ_Samples_failing_DB', 245: 'DB_PERF_SEL_PostZ_Samples_failing_DB', 246: 'DB_PERF_SEL_flush_compressed', 247: 'DB_PERF_SEL_flush_plane_le4', 248: 'DB_PERF_SEL_tiles_z_fully_summarized', 249: 'DB_PERF_SEL_tiles_stencil_fully_summarized', 250: 'DB_PERF_SEL_tiles_z_clear_on_expclear', 251: 'DB_PERF_SEL_tiles_s_clear_on_expclear', 252: 'DB_PERF_SEL_tiles_decomp_on_expclear', 253: 'DB_PERF_SEL_tiles_compressed_to_decompressed', 254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy', 255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 256: 'DB_PERF_SEL_di_dt_stall', 257: 'DB_PERF_SEL_DB_SC_quad_double_quad', 258: 'DB_PERF_SEL_SX_DB_quad_export_quads', 259: 'DB_PERF_SEL_SX_DB_quad_double_format', 260: 'DB_PERF_SEL_SX_DB_quad_fast_format', 261: 'DB_PERF_SEL_SX_DB_quad_slow_format', 262: 'DB_PERF_SEL_DB_CB_lquad_export_quads', 263: 'DB_PERF_SEL_DB_CB_lquad_double_format', 264: 'DB_PERF_SEL_DB_CB_lquad_fast_format', 265: 'DB_PERF_SEL_DB_CB_lquad_slow_format', 266: 'DB_PERF_SEL_CB_DB_rdreq_sends', 267: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', 268: 'DB_PERF_SEL_CB_DB_wrreq_sends', 269: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', 270: 'DB_PERF_SEL_DB_CB_rdret_ack', 271: 'DB_PERF_SEL_DB_CB_rdret_nack', 272: 'DB_PERF_SEL_DB_CB_wrret_ack', 273: 'DB_PERF_SEL_DB_CB_wrret_nack', 274: 'DB_PERF_SEL_DFSM_squads_in', 275: 'DB_PERF_SEL_DFSM_full_cleared_squads_out', 276: 'DB_PERF_SEL_DFSM_quads_in', 277: 'DB_PERF_SEL_DFSM_fully_cleared_quads_out', 278: 'DB_PERF_SEL_DFSM_lit_pixels_in', 279: 'DB_PERF_SEL_DFSM_fully_cleared_pixels_out', 280: 'DB_PERF_SEL_DFSM_lit_samples_in', 281: 'DB_PERF_SEL_DFSM_lit_samples_out', 282: 'DB_PERF_SEL_DFSM_cycles_above_watermark', 283: 'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream', 284: 'DB_PERF_SEL_DFSM_stalled_by_downstream', 285: 'DB_PERF_SEL_DFSM_evicted_squads_above_watermark', 286: 'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow', 287: 'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO', 288: 'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark', } DB_PERF_SEL_SC_DB_tile_sends = 0 DB_PERF_SEL_SC_DB_tile_busy = 1 DB_PERF_SEL_SC_DB_tile_stalls = 2 DB_PERF_SEL_SC_DB_tile_events = 3 DB_PERF_SEL_SC_DB_tile_tiles = 4 DB_PERF_SEL_SC_DB_tile_covered = 5 DB_PERF_SEL_hiz_tc_read_starved = 6 DB_PERF_SEL_hiz_tc_write_stall = 7 DB_PERF_SEL_hiz_qtiles_culled = 8 DB_PERF_SEL_his_qtiles_culled = 9 DB_PERF_SEL_DB_SC_tile_sends = 10 DB_PERF_SEL_DB_SC_tile_busy = 11 DB_PERF_SEL_DB_SC_tile_stalls = 12 DB_PERF_SEL_DB_SC_tile_df_stalls = 13 DB_PERF_SEL_DB_SC_tile_tiles = 14 DB_PERF_SEL_DB_SC_tile_culled = 15 DB_PERF_SEL_DB_SC_tile_hier_kill = 16 DB_PERF_SEL_DB_SC_tile_fast_ops = 17 DB_PERF_SEL_DB_SC_tile_no_ops = 18 DB_PERF_SEL_DB_SC_tile_tile_rate = 19 DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20 DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21 DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22 DB_PERF_SEL_SC_DB_quad_sends = 23 DB_PERF_SEL_SC_DB_quad_busy = 24 DB_PERF_SEL_SC_DB_quad_squads = 25 DB_PERF_SEL_SC_DB_quad_tiles = 26 DB_PERF_SEL_SC_DB_quad_pixels = 27 DB_PERF_SEL_SC_DB_quad_killed_tiles = 28 DB_PERF_SEL_DB_SC_quad_sends = 29 DB_PERF_SEL_DB_SC_quad_busy = 30 DB_PERF_SEL_DB_SC_quad_stalls = 31 DB_PERF_SEL_DB_SC_quad_tiles = 32 DB_PERF_SEL_DB_SC_quad_lit_quad = 33 DB_PERF_SEL_DB_CB_tile_sends = 34 DB_PERF_SEL_DB_CB_tile_busy = 35 DB_PERF_SEL_DB_CB_tile_stalls = 36 DB_PERF_SEL_SX_DB_quad_sends = 37 DB_PERF_SEL_SX_DB_quad_busy = 38 DB_PERF_SEL_SX_DB_quad_stalls = 39 DB_PERF_SEL_SX_DB_quad_quads = 40 DB_PERF_SEL_SX_DB_quad_pixels = 41 DB_PERF_SEL_SX_DB_quad_exports = 42 DB_PERF_SEL_SH_quads_outstanding_sum = 43 DB_PERF_SEL_DB_CB_lquad_sends = 44 DB_PERF_SEL_DB_CB_lquad_busy = 45 DB_PERF_SEL_DB_CB_lquad_stalls = 46 DB_PERF_SEL_DB_CB_lquad_quads = 47 DB_PERF_SEL_tile_rd_sends = 48 DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49 DB_PERF_SEL_quad_rd_sends = 50 DB_PERF_SEL_quad_rd_busy = 51 DB_PERF_SEL_quad_rd_mi_stall = 52 DB_PERF_SEL_quad_rd_rw_collision = 53 DB_PERF_SEL_quad_rd_tag_stall = 54 DB_PERF_SEL_quad_rd_32byte_reqs = 55 DB_PERF_SEL_quad_rd_panic = 56 DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57 DB_PERF_SEL_quad_rdret_sends = 58 DB_PERF_SEL_quad_rdret_busy = 59 DB_PERF_SEL_tile_wr_sends = 60 DB_PERF_SEL_tile_wr_acks = 61 DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62 DB_PERF_SEL_quad_wr_sends = 63 DB_PERF_SEL_quad_wr_busy = 64 DB_PERF_SEL_quad_wr_mi_stall = 65 DB_PERF_SEL_quad_wr_coherency_stall = 66 DB_PERF_SEL_quad_wr_acks = 67 DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68 DB_PERF_SEL_Tile_Cache_misses = 69 DB_PERF_SEL_Tile_Cache_hits = 70 DB_PERF_SEL_Tile_Cache_flushes = 71 DB_PERF_SEL_Tile_Cache_surface_stall = 72 DB_PERF_SEL_Tile_Cache_starves = 73 DB_PERF_SEL_Tile_Cache_mem_return_starve = 74 DB_PERF_SEL_tcp_dispatcher_reads = 75 DB_PERF_SEL_tcp_prefetcher_reads = 76 DB_PERF_SEL_tcp_preloader_reads = 77 DB_PERF_SEL_tcp_dispatcher_flushes = 78 DB_PERF_SEL_tcp_prefetcher_flushes = 79 DB_PERF_SEL_tcp_preloader_flushes = 80 DB_PERF_SEL_Depth_Tile_Cache_sends = 81 DB_PERF_SEL_Depth_Tile_Cache_busy = 82 DB_PERF_SEL_Depth_Tile_Cache_starves = 83 DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84 DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85 DB_PERF_SEL_Depth_Tile_Cache_misses = 86 DB_PERF_SEL_Depth_Tile_Cache_hits = 87 DB_PERF_SEL_Depth_Tile_Cache_flushes = 88 DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89 DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90 DB_PERF_SEL_Depth_Tile_Cache_event = 91 DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92 DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93 DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94 DB_PERF_SEL_Stencil_Cache_misses = 95 DB_PERF_SEL_Stencil_Cache_hits = 96 DB_PERF_SEL_Stencil_Cache_flushes = 97 DB_PERF_SEL_Stencil_Cache_starves = 98 DB_PERF_SEL_Stencil_Cache_frees = 99 DB_PERF_SEL_Z_Cache_separate_Z_misses = 100 DB_PERF_SEL_Z_Cache_separate_Z_hits = 101 DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102 DB_PERF_SEL_Z_Cache_separate_Z_starves = 103 DB_PERF_SEL_Z_Cache_pmask_misses = 104 DB_PERF_SEL_Z_Cache_pmask_hits = 105 DB_PERF_SEL_Z_Cache_pmask_flushes = 106 DB_PERF_SEL_Z_Cache_pmask_starves = 107 DB_PERF_SEL_Z_Cache_frees = 108 DB_PERF_SEL_Plane_Cache_misses = 109 DB_PERF_SEL_Plane_Cache_hits = 110 DB_PERF_SEL_Plane_Cache_flushes = 111 DB_PERF_SEL_Plane_Cache_starves = 112 DB_PERF_SEL_Plane_Cache_frees = 113 DB_PERF_SEL_flush_expanded_stencil = 114 DB_PERF_SEL_flush_compressed_stencil = 115 DB_PERF_SEL_flush_single_stencil = 116 DB_PERF_SEL_planes_flushed = 117 DB_PERF_SEL_flush_1plane = 118 DB_PERF_SEL_flush_2plane = 119 DB_PERF_SEL_flush_3plane = 120 DB_PERF_SEL_flush_4plane = 121 DB_PERF_SEL_flush_5plane = 122 DB_PERF_SEL_flush_6plane = 123 DB_PERF_SEL_flush_7plane = 124 DB_PERF_SEL_flush_8plane = 125 DB_PERF_SEL_flush_9plane = 126 DB_PERF_SEL_flush_10plane = 127 DB_PERF_SEL_flush_11plane = 128 DB_PERF_SEL_flush_12plane = 129 DB_PERF_SEL_flush_13plane = 130 DB_PERF_SEL_flush_14plane = 131 DB_PERF_SEL_flush_15plane = 132 DB_PERF_SEL_flush_16plane = 133 DB_PERF_SEL_flush_expanded_z = 134 DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135 DB_PERF_SEL_reZ_waiting_for_postZ_done = 136 DB_PERF_SEL_dk_tile_sends = 137 DB_PERF_SEL_dk_tile_busy = 138 DB_PERF_SEL_dk_tile_quad_starves = 139 DB_PERF_SEL_dk_tile_stalls = 140 DB_PERF_SEL_dk_squad_sends = 141 DB_PERF_SEL_dk_squad_busy = 142 DB_PERF_SEL_dk_squad_stalls = 143 DB_PERF_SEL_Op_Pipe_Busy = 144 DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145 DB_PERF_SEL_qc_busy = 146 DB_PERF_SEL_qc_xfc = 147 DB_PERF_SEL_qc_conflicts = 148 DB_PERF_SEL_qc_full_stall = 149 DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150 DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151 DB_PERF_SEL_tsc_insert_summarize_stall = 152 DB_PERF_SEL_tl_busy = 153 DB_PERF_SEL_tl_dtc_read_starved = 154 DB_PERF_SEL_tl_z_fetch_stall = 155 DB_PERF_SEL_tl_stencil_stall = 156 DB_PERF_SEL_tl_z_decompress_stall = 157 DB_PERF_SEL_tl_stencil_locked_stall = 158 DB_PERF_SEL_tl_events = 159 DB_PERF_SEL_tl_summarize_squads = 160 DB_PERF_SEL_tl_flush_expand_squads = 161 DB_PERF_SEL_tl_expand_squads = 162 DB_PERF_SEL_tl_preZ_squads = 163 DB_PERF_SEL_tl_postZ_squads = 164 DB_PERF_SEL_tl_preZ_noop_squads = 165 DB_PERF_SEL_tl_postZ_noop_squads = 166 DB_PERF_SEL_tl_tile_ops = 167 DB_PERF_SEL_tl_in_xfc = 168 DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169 DB_PERF_SEL_tl_in_fast_z_stall = 170 DB_PERF_SEL_tl_out_xfc = 171 DB_PERF_SEL_tl_out_squads = 172 DB_PERF_SEL_zf_plane_multicycle = 173 DB_PERF_SEL_PostZ_Samples_passing_Z = 174 DB_PERF_SEL_PostZ_Samples_failing_Z = 175 DB_PERF_SEL_PostZ_Samples_failing_S = 176 DB_PERF_SEL_PreZ_Samples_passing_Z = 177 DB_PERF_SEL_PreZ_Samples_failing_Z = 178 DB_PERF_SEL_PreZ_Samples_failing_S = 179 DB_PERF_SEL_ts_tc_update_stall = 180 DB_PERF_SEL_sc_kick_start = 181 DB_PERF_SEL_sc_kick_end = 182 DB_PERF_SEL_clock_reg_active = 183 DB_PERF_SEL_clock_main_active = 184 DB_PERF_SEL_clock_mem_export_active = 185 DB_PERF_SEL_esr_ps_out_busy = 186 DB_PERF_SEL_esr_ps_lqf_busy = 187 DB_PERF_SEL_esr_ps_lqf_stall = 188 DB_PERF_SEL_etr_out_send = 189 DB_PERF_SEL_etr_out_busy = 190 DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191 DB_PERF_SEL_etr_out_cb_tile_stall = 192 DB_PERF_SEL_etr_out_esr_stall = 193 DB_PERF_SEL_esr_ps_sqq_busy = 194 DB_PERF_SEL_esr_ps_sqq_stall = 195 DB_PERF_SEL_esr_eot_fwd_busy = 196 DB_PERF_SEL_esr_eot_fwd_holding_squad = 197 DB_PERF_SEL_esr_eot_fwd_forward = 198 DB_PERF_SEL_esr_sqq_zi_busy = 199 DB_PERF_SEL_esr_sqq_zi_stall = 200 DB_PERF_SEL_postzl_sq_pt_busy = 201 DB_PERF_SEL_postzl_sq_pt_stall = 202 DB_PERF_SEL_postzl_se_busy = 203 DB_PERF_SEL_postzl_se_stall = 204 DB_PERF_SEL_postzl_partial_launch = 205 DB_PERF_SEL_postzl_full_launch = 206 DB_PERF_SEL_postzl_partial_waiting = 207 DB_PERF_SEL_postzl_tile_mem_stall = 208 DB_PERF_SEL_postzl_tile_init_stall = 209 DB_PEFF_SEL_prezl_tile_mem_stall = 210 DB_PERF_SEL_prezl_tile_init_stall = 211 DB_PERF_SEL_dtt_sm_clash_stall = 212 DB_PERF_SEL_dtt_sm_slot_stall = 213 DB_PERF_SEL_dtt_sm_miss_stall = 214 DB_PERF_SEL_mi_rdreq_busy = 215 DB_PERF_SEL_mi_rdreq_stall = 216 DB_PERF_SEL_mi_wrreq_busy = 217 DB_PERF_SEL_mi_wrreq_stall = 218 DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219 DB_PERF_SEL_dkg_tile_rate_tile = 220 DB_PERF_SEL_prezl_src_in_sends = 221 DB_PERF_SEL_prezl_src_in_stall = 222 DB_PERF_SEL_prezl_src_in_squads = 223 DB_PERF_SEL_prezl_src_in_squads_unrolled = 224 DB_PERF_SEL_prezl_src_in_tile_rate = 225 DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226 DB_PERF_SEL_prezl_src_out_stall = 227 DB_PERF_SEL_postzl_src_in_sends = 228 DB_PERF_SEL_postzl_src_in_stall = 229 DB_PERF_SEL_postzl_src_in_squads = 230 DB_PERF_SEL_postzl_src_in_squads_unrolled = 231 DB_PERF_SEL_postzl_src_in_tile_rate = 232 DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233 DB_PERF_SEL_postzl_src_out_stall = 234 DB_PERF_SEL_esr_ps_src_in_sends = 235 DB_PERF_SEL_esr_ps_src_in_stall = 236 DB_PERF_SEL_esr_ps_src_in_squads = 237 DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238 DB_PERF_SEL_esr_ps_src_in_tile_rate = 239 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241 DB_PERF_SEL_esr_ps_src_out_stall = 242 DB_PERF_SEL_depth_bounds_qtiles_culled = 243 DB_PERF_SEL_PreZ_Samples_failing_DB = 244 DB_PERF_SEL_PostZ_Samples_failing_DB = 245 DB_PERF_SEL_flush_compressed = 246 DB_PERF_SEL_flush_plane_le4 = 247 DB_PERF_SEL_tiles_z_fully_summarized = 248 DB_PERF_SEL_tiles_stencil_fully_summarized = 249 DB_PERF_SEL_tiles_z_clear_on_expclear = 250 DB_PERF_SEL_tiles_s_clear_on_expclear = 251 DB_PERF_SEL_tiles_decomp_on_expclear = 252 DB_PERF_SEL_tiles_compressed_to_decompressed = 253 DB_PERF_SEL_Op_Pipe_Prez_Busy = 254 DB_PERF_SEL_Op_Pipe_Postz_Busy = 255 DB_PERF_SEL_di_dt_stall = 256 DB_PERF_SEL_DB_SC_quad_double_quad = 257 DB_PERF_SEL_SX_DB_quad_export_quads = 258 DB_PERF_SEL_SX_DB_quad_double_format = 259 DB_PERF_SEL_SX_DB_quad_fast_format = 260 DB_PERF_SEL_SX_DB_quad_slow_format = 261 DB_PERF_SEL_DB_CB_lquad_export_quads = 262 DB_PERF_SEL_DB_CB_lquad_double_format = 263 DB_PERF_SEL_DB_CB_lquad_fast_format = 264 DB_PERF_SEL_DB_CB_lquad_slow_format = 265 DB_PERF_SEL_CB_DB_rdreq_sends = 266 DB_PERF_SEL_CB_DB_rdreq_prt_sends = 267 DB_PERF_SEL_CB_DB_wrreq_sends = 268 DB_PERF_SEL_CB_DB_wrreq_prt_sends = 269 DB_PERF_SEL_DB_CB_rdret_ack = 270 DB_PERF_SEL_DB_CB_rdret_nack = 271 DB_PERF_SEL_DB_CB_wrret_ack = 272 DB_PERF_SEL_DB_CB_wrret_nack = 273 DB_PERF_SEL_DFSM_squads_in = 274 DB_PERF_SEL_DFSM_full_cleared_squads_out = 275 DB_PERF_SEL_DFSM_quads_in = 276 DB_PERF_SEL_DFSM_fully_cleared_quads_out = 277 DB_PERF_SEL_DFSM_lit_pixels_in = 278 DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 279 DB_PERF_SEL_DFSM_lit_samples_in = 280 DB_PERF_SEL_DFSM_lit_samples_out = 281 DB_PERF_SEL_DFSM_cycles_above_watermark = 282 DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 283 DB_PERF_SEL_DFSM_stalled_by_downstream = 284 DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 285 DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 286 DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 287 DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 288 PerfCounter_Vals = ctypes.c_uint32 # enum # values for enumeration 'RingCounterControl' RingCounterControl__enumvalues = { 0: 'COUNTER_RING_SPLIT', 1: 'COUNTER_RING_0', 2: 'COUNTER_RING_1', } COUNTER_RING_SPLIT = 0 COUNTER_RING_0 = 1 COUNTER_RING_1 = 2 RingCounterControl = ctypes.c_uint32 # enum # values for enumeration 'DbMemArbWatermarks' DbMemArbWatermarks__enumvalues = { 0: 'TRANSFERRED_64_BYTES', 1: 'TRANSFERRED_128_BYTES', 2: 'TRANSFERRED_256_BYTES', 3: 'TRANSFERRED_512_BYTES', 4: 'TRANSFERRED_1024_BYTES', 5: 'TRANSFERRED_2048_BYTES', 6: 'TRANSFERRED_4096_BYTES', 7: 'TRANSFERRED_8192_BYTES', } TRANSFERRED_64_BYTES = 0 TRANSFERRED_128_BYTES = 1 TRANSFERRED_256_BYTES = 2 TRANSFERRED_512_BYTES = 3 TRANSFERRED_1024_BYTES = 4 TRANSFERRED_2048_BYTES = 5 TRANSFERRED_4096_BYTES = 6 TRANSFERRED_8192_BYTES = 7 DbMemArbWatermarks = ctypes.c_uint32 # enum # values for enumeration 'DFSMFlushEvents' DFSMFlushEvents__enumvalues = { 0: 'DB_FLUSH_AND_INV_DB_DATA_TS', 1: 'DB_FLUSH_AND_INV_DB_META', 2: 'DB_CACHE_FLUSH', 3: 'DB_CACHE_FLUSH_TS', 4: 'DB_CACHE_FLUSH_AND_INV_EVENT', 5: 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', } DB_FLUSH_AND_INV_DB_DATA_TS = 0 DB_FLUSH_AND_INV_DB_META = 1 DB_CACHE_FLUSH = 2 DB_CACHE_FLUSH_TS = 3 DB_CACHE_FLUSH_AND_INV_EVENT = 4 DB_CACHE_FLUSH_AND_INV_TS_EVENT = 5 DFSMFlushEvents = ctypes.c_uint32 # enum # values for enumeration 'PixelPipeCounterId' PixelPipeCounterId__enumvalues = { 0: 'PIXEL_PIPE_OCCLUSION_COUNT_0', 1: 'PIXEL_PIPE_OCCLUSION_COUNT_1', 2: 'PIXEL_PIPE_OCCLUSION_COUNT_2', 3: 'PIXEL_PIPE_OCCLUSION_COUNT_3', 4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', 5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', 6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', } PIXEL_PIPE_OCCLUSION_COUNT_0 = 0 PIXEL_PIPE_OCCLUSION_COUNT_1 = 1 PIXEL_PIPE_OCCLUSION_COUNT_2 = 2 PIXEL_PIPE_OCCLUSION_COUNT_3 = 3 PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4 PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5 PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6 PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7 PixelPipeCounterId = ctypes.c_uint32 # enum # values for enumeration 'PixelPipeStride' PixelPipeStride__enumvalues = { 0: 'PIXEL_PIPE_STRIDE_32_BITS', 1: 'PIXEL_PIPE_STRIDE_64_BITS', 2: 'PIXEL_PIPE_STRIDE_128_BITS', 3: 'PIXEL_PIPE_STRIDE_256_BITS', } PIXEL_PIPE_STRIDE_32_BITS = 0 PIXEL_PIPE_STRIDE_64_BITS = 1 PIXEL_PIPE_STRIDE_128_BITS = 2 PIXEL_PIPE_STRIDE_256_BITS = 3 PixelPipeStride = ctypes.c_uint32 # enum # values for enumeration 'TEX_BORDER_COLOR_TYPE' TEX_BORDER_COLOR_TYPE__enumvalues = { 0: 'TEX_BorderColor_TransparentBlack', 1: 'TEX_BorderColor_OpaqueBlack', 2: 'TEX_BorderColor_OpaqueWhite', 3: 'TEX_BorderColor_Register', } TEX_BorderColor_TransparentBlack = 0 TEX_BorderColor_OpaqueBlack = 1 TEX_BorderColor_OpaqueWhite = 2 TEX_BorderColor_Register = 3 TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum # values for enumeration 'TEX_CHROMA_KEY' TEX_CHROMA_KEY__enumvalues = { 0: 'TEX_ChromaKey_Disabled', 1: 'TEX_ChromaKey_Kill', 2: 'TEX_ChromaKey_Blend', 3: 'TEX_ChromaKey_RESERVED_3', } TEX_ChromaKey_Disabled = 0 TEX_ChromaKey_Kill = 1 TEX_ChromaKey_Blend = 2 TEX_ChromaKey_RESERVED_3 = 3 TEX_CHROMA_KEY = ctypes.c_uint32 # enum # values for enumeration 'TEX_CLAMP' TEX_CLAMP__enumvalues = { 0: 'TEX_Clamp_Repeat', 1: 'TEX_Clamp_Mirror', 2: 'TEX_Clamp_ClampToLast', 3: 'TEX_Clamp_MirrorOnceToLast', 4: 'TEX_Clamp_ClampHalfToBorder', 5: 'TEX_Clamp_MirrorOnceHalfToBorder', 6: 'TEX_Clamp_ClampToBorder', 7: 'TEX_Clamp_MirrorOnceToBorder', } TEX_Clamp_Repeat = 0 TEX_Clamp_Mirror = 1 TEX_Clamp_ClampToLast = 2 TEX_Clamp_MirrorOnceToLast = 3 TEX_Clamp_ClampHalfToBorder = 4 TEX_Clamp_MirrorOnceHalfToBorder = 5 TEX_Clamp_ClampToBorder = 6 TEX_Clamp_MirrorOnceToBorder = 7 TEX_CLAMP = ctypes.c_uint32 # enum # values for enumeration 'TEX_COORD_TYPE' TEX_COORD_TYPE__enumvalues = { 0: 'TEX_CoordType_Unnormalized', 1: 'TEX_CoordType_Normalized', } TEX_CoordType_Unnormalized = 0 TEX_CoordType_Normalized = 1 TEX_COORD_TYPE = ctypes.c_uint32 # enum # values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION' TEX_DEPTH_COMPARE_FUNCTION__enumvalues = { 0: 'TEX_DepthCompareFunction_Never', 1: 'TEX_DepthCompareFunction_Less', 2: 'TEX_DepthCompareFunction_Equal', 3: 'TEX_DepthCompareFunction_LessEqual', 4: 'TEX_DepthCompareFunction_Greater', 5: 'TEX_DepthCompareFunction_NotEqual', 6: 'TEX_DepthCompareFunction_GreaterEqual', 7: 'TEX_DepthCompareFunction_Always', } TEX_DepthCompareFunction_Never = 0 TEX_DepthCompareFunction_Less = 1 TEX_DepthCompareFunction_Equal = 2 TEX_DepthCompareFunction_LessEqual = 3 TEX_DepthCompareFunction_Greater = 4 TEX_DepthCompareFunction_NotEqual = 5 TEX_DepthCompareFunction_GreaterEqual = 6 TEX_DepthCompareFunction_Always = 7 TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum # values for enumeration 'TEX_DIM' TEX_DIM__enumvalues = { 0: 'TEX_Dim_1D', 1: 'TEX_Dim_2D', 2: 'TEX_Dim_3D', 3: 'TEX_Dim_CubeMap', 4: 'TEX_Dim_1DArray', 5: 'TEX_Dim_2DArray', 6: 'TEX_Dim_2D_MSAA', 7: 'TEX_Dim_2DArray_MSAA', } TEX_Dim_1D = 0 TEX_Dim_2D = 1 TEX_Dim_3D = 2 TEX_Dim_CubeMap = 3 TEX_Dim_1DArray = 4 TEX_Dim_2DArray = 5 TEX_Dim_2D_MSAA = 6 TEX_Dim_2DArray_MSAA = 7 TEX_DIM = ctypes.c_uint32 # enum # values for enumeration 'TEX_FORMAT_COMP' TEX_FORMAT_COMP__enumvalues = { 0: 'TEX_FormatComp_Unsigned', 1: 'TEX_FormatComp_Signed', 2: 'TEX_FormatComp_UnsignedBiased', 3: 'TEX_FormatComp_RESERVED_3', } TEX_FormatComp_Unsigned = 0 TEX_FormatComp_Signed = 1 TEX_FormatComp_UnsignedBiased = 2 TEX_FormatComp_RESERVED_3 = 3 TEX_FORMAT_COMP = ctypes.c_uint32 # enum # values for enumeration 'TEX_MAX_ANISO_RATIO' TEX_MAX_ANISO_RATIO__enumvalues = { 0: 'TEX_MaxAnisoRatio_1to1', 1: 'TEX_MaxAnisoRatio_2to1', 2: 'TEX_MaxAnisoRatio_4to1', 3: 'TEX_MaxAnisoRatio_8to1', 4: 'TEX_MaxAnisoRatio_16to1', 5: 'TEX_MaxAnisoRatio_RESERVED_5', 6: 'TEX_MaxAnisoRatio_RESERVED_6', 7: 'TEX_MaxAnisoRatio_RESERVED_7', } TEX_MaxAnisoRatio_1to1 = 0 TEX_MaxAnisoRatio_2to1 = 1 TEX_MaxAnisoRatio_4to1 = 2 TEX_MaxAnisoRatio_8to1 = 3 TEX_MaxAnisoRatio_16to1 = 4 TEX_MaxAnisoRatio_RESERVED_5 = 5 TEX_MaxAnisoRatio_RESERVED_6 = 6 TEX_MaxAnisoRatio_RESERVED_7 = 7 TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum # values for enumeration 'TEX_MIP_FILTER' TEX_MIP_FILTER__enumvalues = { 0: 'TEX_MipFilter_None', 1: 'TEX_MipFilter_Point', 2: 'TEX_MipFilter_Linear', 3: 'TEX_MipFilter_Point_Aniso_Adj', } TEX_MipFilter_None = 0 TEX_MipFilter_Point = 1 TEX_MipFilter_Linear = 2 TEX_MipFilter_Point_Aniso_Adj = 3 TEX_MIP_FILTER = ctypes.c_uint32 # enum # values for enumeration 'TEX_REQUEST_SIZE' TEX_REQUEST_SIZE__enumvalues = { 0: 'TEX_RequestSize_32B', 1: 'TEX_RequestSize_64B', 2: 'TEX_RequestSize_128B', 3: 'TEX_RequestSize_2X64B', } TEX_RequestSize_32B = 0 TEX_RequestSize_64B = 1 TEX_RequestSize_128B = 2 TEX_RequestSize_2X64B = 3 TEX_REQUEST_SIZE = ctypes.c_uint32 # enum # values for enumeration 'TEX_SAMPLER_TYPE' TEX_SAMPLER_TYPE__enumvalues = { 0: 'TEX_SamplerType_Invalid', 1: 'TEX_SamplerType_Valid', } TEX_SamplerType_Invalid = 0 TEX_SamplerType_Valid = 1 TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum # values for enumeration 'TEX_XY_FILTER' TEX_XY_FILTER__enumvalues = { 0: 'TEX_XYFilter_Point', 1: 'TEX_XYFilter_Linear', 2: 'TEX_XYFilter_AnisoPoint', 3: 'TEX_XYFilter_AnisoLinear', } TEX_XYFilter_Point = 0 TEX_XYFilter_Linear = 1 TEX_XYFilter_AnisoPoint = 2 TEX_XYFilter_AnisoLinear = 3 TEX_XY_FILTER = ctypes.c_uint32 # enum # values for enumeration 'TEX_Z_FILTER' TEX_Z_FILTER__enumvalues = { 0: 'TEX_ZFilter_None', 1: 'TEX_ZFilter_Point', 2: 'TEX_ZFilter_Linear', 3: 'TEX_ZFilter_RESERVED_3', } TEX_ZFilter_None = 0 TEX_ZFilter_Point = 1 TEX_ZFilter_Linear = 2 TEX_ZFilter_RESERVED_3 = 3 TEX_Z_FILTER = ctypes.c_uint32 # enum # values for enumeration 'VTX_CLAMP' VTX_CLAMP__enumvalues = { 0: 'VTX_Clamp_ClampToZero', 1: 'VTX_Clamp_ClampToNAN', } VTX_Clamp_ClampToZero = 0 VTX_Clamp_ClampToNAN = 1 VTX_CLAMP = ctypes.c_uint32 # enum # values for enumeration 'VTX_FETCH_TYPE' VTX_FETCH_TYPE__enumvalues = { 0: 'VTX_FetchType_VertexData', 1: 'VTX_FetchType_InstanceData', 2: 'VTX_FetchType_NoIndexOffset', 3: 'VTX_FetchType_RESERVED_3', } VTX_FetchType_VertexData = 0 VTX_FetchType_InstanceData = 1 VTX_FetchType_NoIndexOffset = 2 VTX_FetchType_RESERVED_3 = 3 VTX_FETCH_TYPE = ctypes.c_uint32 # enum # values for enumeration 'VTX_FORMAT_COMP_ALL' VTX_FORMAT_COMP_ALL__enumvalues = { 0: 'VTX_FormatCompAll_Unsigned', 1: 'VTX_FormatCompAll_Signed', } VTX_FormatCompAll_Unsigned = 0 VTX_FormatCompAll_Signed = 1 VTX_FORMAT_COMP_ALL = ctypes.c_uint32 # enum # values for enumeration 'VTX_MEM_REQUEST_SIZE' VTX_MEM_REQUEST_SIZE__enumvalues = { 0: 'VTX_MemRequestSize_32B', 1: 'VTX_MemRequestSize_64B', } VTX_MemRequestSize_32B = 0 VTX_MemRequestSize_64B = 1 VTX_MEM_REQUEST_SIZE = ctypes.c_uint32 # enum # values for enumeration 'TVX_DATA_FORMAT' TVX_DATA_FORMAT__enumvalues = { 0: 'TVX_FMT_INVALID', 1: 'TVX_FMT_8', 2: 'TVX_FMT_4_4', 3: 'TVX_FMT_3_3_2', 4: 'TVX_FMT_RESERVED_4', 5: 'TVX_FMT_16', 6: 'TVX_FMT_16_FLOAT', 7: 'TVX_FMT_8_8', 8: 'TVX_FMT_5_6_5', 9: 'TVX_FMT_6_5_5', 10: 'TVX_FMT_1_5_5_5', 11: 'TVX_FMT_4_4_4_4', 12: 'TVX_FMT_5_5_5_1', 13: 'TVX_FMT_32', 14: 'TVX_FMT_32_FLOAT', 15: 'TVX_FMT_16_16', 16: 'TVX_FMT_16_16_FLOAT', 17: 'TVX_FMT_8_24', 18: 'TVX_FMT_8_24_FLOAT', 19: 'TVX_FMT_24_8', 20: 'TVX_FMT_24_8_FLOAT', 21: 'TVX_FMT_10_11_11', 22: 'TVX_FMT_10_11_11_FLOAT', 23: 'TVX_FMT_11_11_10', 24: 'TVX_FMT_11_11_10_FLOAT', 25: 'TVX_FMT_2_10_10_10', 26: 'TVX_FMT_8_8_8_8', 27: 'TVX_FMT_10_10_10_2', 28: 'TVX_FMT_X24_8_32_FLOAT', 29: 'TVX_FMT_32_32', 30: 'TVX_FMT_32_32_FLOAT', 31: 'TVX_FMT_16_16_16_16', 32: 'TVX_FMT_16_16_16_16_FLOAT', 33: 'TVX_FMT_RESERVED_33', 34: 'TVX_FMT_32_32_32_32', 35: 'TVX_FMT_32_32_32_32_FLOAT', 36: 'TVX_FMT_RESERVED_36', 37: 'TVX_FMT_1', 38: 'TVX_FMT_1_REVERSED', 39: 'TVX_FMT_GB_GR', 40: 'TVX_FMT_BG_RG', 41: 'TVX_FMT_32_AS_8', 42: 'TVX_FMT_32_AS_8_8', 43: 'TVX_FMT_5_9_9_9_SHAREDEXP', 44: 'TVX_FMT_8_8_8', 45: 'TVX_FMT_16_16_16', 46: 'TVX_FMT_16_16_16_FLOAT', 47: 'TVX_FMT_32_32_32', 48: 'TVX_FMT_32_32_32_FLOAT', 49: 'TVX_FMT_BC1', 50: 'TVX_FMT_BC2', 51: 'TVX_FMT_BC3', 52: 'TVX_FMT_BC4', 53: 'TVX_FMT_BC5', 54: 'TVX_FMT_APC0', 55: 'TVX_FMT_APC1', 56: 'TVX_FMT_APC2', 57: 'TVX_FMT_APC3', 58: 'TVX_FMT_APC4', 59: 'TVX_FMT_APC5', 60: 'TVX_FMT_APC6', 61: 'TVX_FMT_APC7', 62: 'TVX_FMT_CTX1', 63: 'TVX_FMT_RESERVED_63', } TVX_FMT_INVALID = 0 TVX_FMT_8 = 1 TVX_FMT_4_4 = 2 TVX_FMT_3_3_2 = 3 TVX_FMT_RESERVED_4 = 4 TVX_FMT_16 = 5 TVX_FMT_16_FLOAT = 6 TVX_FMT_8_8 = 7 TVX_FMT_5_6_5 = 8 TVX_FMT_6_5_5 = 9 TVX_FMT_1_5_5_5 = 10 TVX_FMT_4_4_4_4 = 11 TVX_FMT_5_5_5_1 = 12 TVX_FMT_32 = 13 TVX_FMT_32_FLOAT = 14 TVX_FMT_16_16 = 15 TVX_FMT_16_16_FLOAT = 16 TVX_FMT_8_24 = 17 TVX_FMT_8_24_FLOAT = 18 TVX_FMT_24_8 = 19 TVX_FMT_24_8_FLOAT = 20 TVX_FMT_10_11_11 = 21 TVX_FMT_10_11_11_FLOAT = 22 TVX_FMT_11_11_10 = 23 TVX_FMT_11_11_10_FLOAT = 24 TVX_FMT_2_10_10_10 = 25 TVX_FMT_8_8_8_8 = 26 TVX_FMT_10_10_10_2 = 27 TVX_FMT_X24_8_32_FLOAT = 28 TVX_FMT_32_32 = 29 TVX_FMT_32_32_FLOAT = 30 TVX_FMT_16_16_16_16 = 31 TVX_FMT_16_16_16_16_FLOAT = 32 TVX_FMT_RESERVED_33 = 33 TVX_FMT_32_32_32_32 = 34 TVX_FMT_32_32_32_32_FLOAT = 35 TVX_FMT_RESERVED_36 = 36 TVX_FMT_1 = 37 TVX_FMT_1_REVERSED = 38 TVX_FMT_GB_GR = 39 TVX_FMT_BG_RG = 40 TVX_FMT_32_AS_8 = 41 TVX_FMT_32_AS_8_8 = 42 TVX_FMT_5_9_9_9_SHAREDEXP = 43 TVX_FMT_8_8_8 = 44 TVX_FMT_16_16_16 = 45 TVX_FMT_16_16_16_FLOAT = 46 TVX_FMT_32_32_32 = 47 TVX_FMT_32_32_32_FLOAT = 48 TVX_FMT_BC1 = 49 TVX_FMT_BC2 = 50 TVX_FMT_BC3 = 51 TVX_FMT_BC4 = 52 TVX_FMT_BC5 = 53 TVX_FMT_APC0 = 54 TVX_FMT_APC1 = 55 TVX_FMT_APC2 = 56 TVX_FMT_APC3 = 57 TVX_FMT_APC4 = 58 TVX_FMT_APC5 = 59 TVX_FMT_APC6 = 60 TVX_FMT_APC7 = 61 TVX_FMT_CTX1 = 62 TVX_FMT_RESERVED_63 = 63 TVX_DATA_FORMAT = ctypes.c_uint32 # enum # values for enumeration 'TVX_DST_SEL' TVX_DST_SEL__enumvalues = { 0: 'TVX_DstSel_X', 1: 'TVX_DstSel_Y', 2: 'TVX_DstSel_Z', 3: 'TVX_DstSel_W', 4: 'TVX_DstSel_0f', 5: 'TVX_DstSel_1f', 6: 'TVX_DstSel_RESERVED_6', 7: 'TVX_DstSel_Mask', } TVX_DstSel_X = 0 TVX_DstSel_Y = 1 TVX_DstSel_Z = 2 TVX_DstSel_W = 3 TVX_DstSel_0f = 4 TVX_DstSel_1f = 5 TVX_DstSel_RESERVED_6 = 6 TVX_DstSel_Mask = 7 TVX_DST_SEL = ctypes.c_uint32 # enum # values for enumeration 'TVX_ENDIAN_SWAP' TVX_ENDIAN_SWAP__enumvalues = { 0: 'TVX_EndianSwap_None', 1: 'TVX_EndianSwap_8in16', 2: 'TVX_EndianSwap_8in32', 3: 'TVX_EndianSwap_8in64', } TVX_EndianSwap_None = 0 TVX_EndianSwap_8in16 = 1 TVX_EndianSwap_8in32 = 2 TVX_EndianSwap_8in64 = 3 TVX_ENDIAN_SWAP = ctypes.c_uint32 # enum # values for enumeration 'TVX_INST' TVX_INST__enumvalues = { 0: 'TVX_Inst_NormalVertexFetch', 1: 'TVX_Inst_SemanticVertexFetch', 2: 'TVX_Inst_RESERVED_2', 3: 'TVX_Inst_LD', 4: 'TVX_Inst_GetTextureResInfo', 5: 'TVX_Inst_GetNumberOfSamples', 6: 'TVX_Inst_GetLOD', 7: 'TVX_Inst_GetGradientsH', 8: 'TVX_Inst_GetGradientsV', 9: 'TVX_Inst_SetTextureOffsets', 10: 'TVX_Inst_KeepGradients', 11: 'TVX_Inst_SetGradientsH', 12: 'TVX_Inst_SetGradientsV', 13: 'TVX_Inst_Pass', 14: 'TVX_Inst_GetBufferResInfo', 15: 'TVX_Inst_RESERVED_15', 16: 'TVX_Inst_Sample', 17: 'TVX_Inst_Sample_L', 18: 'TVX_Inst_Sample_LB', 19: 'TVX_Inst_Sample_LZ', 20: 'TVX_Inst_Sample_G', 21: 'TVX_Inst_Gather4', 22: 'TVX_Inst_Sample_G_LB', 23: 'TVX_Inst_Gather4_O', 24: 'TVX_Inst_Sample_C', 25: 'TVX_Inst_Sample_C_L', 26: 'TVX_Inst_Sample_C_LB', 27: 'TVX_Inst_Sample_C_LZ', 28: 'TVX_Inst_Sample_C_G', 29: 'TVX_Inst_Gather4_C', 30: 'TVX_Inst_Sample_C_G_LB', 31: 'TVX_Inst_Gather4_C_O', } TVX_Inst_NormalVertexFetch = 0 TVX_Inst_SemanticVertexFetch = 1 TVX_Inst_RESERVED_2 = 2 TVX_Inst_LD = 3 TVX_Inst_GetTextureResInfo = 4 TVX_Inst_GetNumberOfSamples = 5 TVX_Inst_GetLOD = 6 TVX_Inst_GetGradientsH = 7 TVX_Inst_GetGradientsV = 8 TVX_Inst_SetTextureOffsets = 9 TVX_Inst_KeepGradients = 10 TVX_Inst_SetGradientsH = 11 TVX_Inst_SetGradientsV = 12 TVX_Inst_Pass = 13 TVX_Inst_GetBufferResInfo = 14 TVX_Inst_RESERVED_15 = 15 TVX_Inst_Sample = 16 TVX_Inst_Sample_L = 17 TVX_Inst_Sample_LB = 18 TVX_Inst_Sample_LZ = 19 TVX_Inst_Sample_G = 20 TVX_Inst_Gather4 = 21 TVX_Inst_Sample_G_LB = 22 TVX_Inst_Gather4_O = 23 TVX_Inst_Sample_C = 24 TVX_Inst_Sample_C_L = 25 TVX_Inst_Sample_C_LB = 26 TVX_Inst_Sample_C_LZ = 27 TVX_Inst_Sample_C_G = 28 TVX_Inst_Gather4_C = 29 TVX_Inst_Sample_C_G_LB = 30 TVX_Inst_Gather4_C_O = 31 TVX_INST = ctypes.c_uint32 # enum # values for enumeration 'TVX_NUM_FORMAT_ALL' TVX_NUM_FORMAT_ALL__enumvalues = { 0: 'TVX_NumFormatAll_Norm', 1: 'TVX_NumFormatAll_Int', 2: 'TVX_NumFormatAll_Scaled', 3: 'TVX_NumFormatAll_RESERVED_3', } TVX_NumFormatAll_Norm = 0 TVX_NumFormatAll_Int = 1 TVX_NumFormatAll_Scaled = 2 TVX_NumFormatAll_RESERVED_3 = 3 TVX_NUM_FORMAT_ALL = ctypes.c_uint32 # enum # values for enumeration 'TVX_SRC_SEL' TVX_SRC_SEL__enumvalues = { 0: 'TVX_SrcSel_X', 1: 'TVX_SrcSel_Y', 2: 'TVX_SrcSel_Z', 3: 'TVX_SrcSel_W', 4: 'TVX_SrcSel_0f', 5: 'TVX_SrcSel_1f', } TVX_SrcSel_X = 0 TVX_SrcSel_Y = 1 TVX_SrcSel_Z = 2 TVX_SrcSel_W = 3 TVX_SrcSel_0f = 4 TVX_SrcSel_1f = 5 TVX_SRC_SEL = ctypes.c_uint32 # enum # values for enumeration 'TVX_SRF_MODE_ALL' TVX_SRF_MODE_ALL__enumvalues = { 0: 'TVX_SRFModeAll_ZCMO', 1: 'TVX_SRFModeAll_NZ', } TVX_SRFModeAll_ZCMO = 0 TVX_SRFModeAll_NZ = 1 TVX_SRF_MODE_ALL = ctypes.c_uint32 # enum # values for enumeration 'TVX_TYPE' TVX_TYPE__enumvalues = { 0: 'TVX_Type_InvalidTextureResource', 1: 'TVX_Type_InvalidVertexBuffer', 2: 'TVX_Type_ValidTextureResource', 3: 'TVX_Type_ValidVertexBuffer', } TVX_Type_InvalidTextureResource = 0 TVX_Type_InvalidVertexBuffer = 1 TVX_Type_ValidTextureResource = 2 TVX_Type_ValidVertexBuffer = 3 TVX_TYPE = ctypes.c_uint32 # enum # values for enumeration 'SU_PERFCNT_SEL' SU_PERFCNT_SEL__enumvalues = { 0: 'PERF_PAPC_PASX_REQ', 1: 'PERF_PAPC_PASX_DISABLE_PIPE', 2: 'PERF_PAPC_PASX_FIRST_VECTOR', 3: 'PERF_PAPC_PASX_SECOND_VECTOR', 4: 'PERF_PAPC_PASX_FIRST_DEAD', 5: 'PERF_PAPC_PASX_SECOND_DEAD', 6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD', 7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD', 8: 'PERF_PAPC_PA_INPUT_PRIM', 9: 'PERF_PAPC_PA_INPUT_NULL_PRIM', 10: 'PERF_PAPC_PA_INPUT_EVENT_FLAG', 11: 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', 12: 'PERF_PAPC_PA_INPUT_END_OF_PACKET', 13: 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', 14: 'PERF_PAPC_CLPR_CULL_PRIM', 15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 16: 'PERF_PAPC_CLPR_VV_CULL_PRIM', 17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM', 18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', 19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', 20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', 21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', 22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM', 23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', 25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', 26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', 27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', 28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', 29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', 30: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', 31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', 32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', 34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', 35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', 37: 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', 38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', 39: 'PERF_PAPC_CLSM_NULL_PRIM', 40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', 41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', 44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', 46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', 47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', 48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 49: 'PERF_PAPC_SU_INPUT_PRIM', 50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM', 51: 'PERF_PAPC_SU_INPUT_NULL_PRIM', 52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL', 53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', 54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', 55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', 56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', 57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL', 58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL', 59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', 60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', 61: 'PERF_PAPC_SU_OUTPUT_PRIM', 62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', 63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', 64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', 65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', 66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', 68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', 69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', 71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', 72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', 73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', 74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', 75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', 76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', 77: 'PERF_PAPC_PASX_REQ_IDLE', 78: 'PERF_PAPC_PASX_REQ_BUSY', 79: 'PERF_PAPC_PASX_REQ_STALLED', 80: 'PERF_PAPC_PASX_REC_IDLE', 81: 'PERF_PAPC_PASX_REC_BUSY', 82: 'PERF_PAPC_PASX_REC_STARVED_SX', 83: 'PERF_PAPC_PASX_REC_STALLED', 84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', 85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', 86: 'PERF_PAPC_CCGSM_IDLE', 87: 'PERF_PAPC_CCGSM_BUSY', 88: 'PERF_PAPC_CCGSM_STALLED', 89: 'PERF_PAPC_CLPRIM_IDLE', 90: 'PERF_PAPC_CLPRIM_BUSY', 91: 'PERF_PAPC_CLPRIM_STALLED', 92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM', 93: 'PERF_PAPC_CLIPSM_IDLE', 94: 'PERF_PAPC_CLIPSM_BUSY', 95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', 96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', 98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', 99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', 100: 'PERF_PAPC_CLIPGA_IDLE', 101: 'PERF_PAPC_CLIPGA_BUSY', 102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', 103: 'PERF_PAPC_CLIPGA_STALLED', 104: 'PERF_PAPC_CLIP_IDLE', 105: 'PERF_PAPC_CLIP_BUSY', 106: 'PERF_PAPC_SU_IDLE', 107: 'PERF_PAPC_SU_BUSY', 108: 'PERF_PAPC_SU_STARVED_CLIP', 109: 'PERF_PAPC_SU_STALLED_SC', 110: 'PERF_PAPC_CL_DYN_SCLK_VLD', 111: 'PERF_PAPC_SU_DYN_SCLK_VLD', 112: 'PERF_PAPC_PA_REG_SCLK_VLD', 113: 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', 114: 'PERF_PAPC_PASX_SE0_REQ', 115: 'PERF_PAPC_PASX_SE1_REQ', 116: 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', 117: 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', 118: 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 119: 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', 121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', 122: 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', 123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', 124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', 125: 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', 126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', 127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', 128: 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', 129: 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', 130: 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', 131: 'PERF_PAPC_SU_SE0_STALLED_SC', 132: 'PERF_PAPC_SU_SE1_STALLED_SC', 133: 'PERF_PAPC_SU_SE01_STALLED_SC', 134: 'PERF_PAPC_CLSM_CLIPPING_PRIM', 135: 'PERF_PAPC_SU_CULLED_PRIM', 136: 'PERF_PAPC_SU_OUTPUT_EOPG', 137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', 138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', 139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', 140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', 141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', 142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', 143: 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', 144: 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', 145: 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', 146: 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', 147: 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', 148: 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', 149: 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', 150: 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', 151: 'PERF_PAPC_SU_SE2_STALLED_SC', 152: 'PERF_PAPC_SU_SE3_STALLED_SC', } PERF_PAPC_PASX_REQ = 0 PERF_PAPC_PASX_DISABLE_PIPE = 1 PERF_PAPC_PASX_FIRST_VECTOR = 2 PERF_PAPC_PASX_SECOND_VECTOR = 3 PERF_PAPC_PASX_FIRST_DEAD = 4 PERF_PAPC_PASX_SECOND_DEAD = 5 PERF_PAPC_PASX_VTX_KILL_DISCARD = 6 PERF_PAPC_PASX_VTX_NAN_DISCARD = 7 PERF_PAPC_PA_INPUT_PRIM = 8 PERF_PAPC_PA_INPUT_NULL_PRIM = 9 PERF_PAPC_PA_INPUT_EVENT_FLAG = 10 PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11 PERF_PAPC_PA_INPUT_END_OF_PACKET = 12 PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 13 PERF_PAPC_CLPR_CULL_PRIM = 14 PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15 PERF_PAPC_CLPR_VV_CULL_PRIM = 16 PERF_PAPC_CLPR_UCP_CULL_PRIM = 17 PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18 PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19 PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20 PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21 PERF_PAPC_CLPR_VV_CLIP_PRIM = 22 PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23 PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24 PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25 PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26 PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27 PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29 PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 30 PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31 PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32 PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33 PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34 PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35 PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36 PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 37 PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38 PERF_PAPC_CLSM_NULL_PRIM = 39 PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40 PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41 PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42 PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43 PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44 PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45 PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46 PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 47 PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48 PERF_PAPC_SU_INPUT_PRIM = 49 PERF_PAPC_SU_INPUT_CLIP_PRIM = 50 PERF_PAPC_SU_INPUT_NULL_PRIM = 51 PERF_PAPC_SU_INPUT_PRIM_DUAL = 52 PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53 PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54 PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55 PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56 PERF_PAPC_SU_POLYMODE_FACE_CULL = 57 PERF_PAPC_SU_POLYMODE_BACK_CULL = 58 PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59 PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60 PERF_PAPC_SU_OUTPUT_PRIM = 61 PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62 PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63 PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64 PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65 PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66 PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67 PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68 PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70 PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72 PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73 PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74 PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75 PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76 PERF_PAPC_PASX_REQ_IDLE = 77 PERF_PAPC_PASX_REQ_BUSY = 78 PERF_PAPC_PASX_REQ_STALLED = 79 PERF_PAPC_PASX_REC_IDLE = 80 PERF_PAPC_PASX_REC_BUSY = 81 PERF_PAPC_PASX_REC_STARVED_SX = 82 PERF_PAPC_PASX_REC_STALLED = 83 PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84 PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85 PERF_PAPC_CCGSM_IDLE = 86 PERF_PAPC_CCGSM_BUSY = 87 PERF_PAPC_CCGSM_STALLED = 88 PERF_PAPC_CLPRIM_IDLE = 89 PERF_PAPC_CLPRIM_BUSY = 90 PERF_PAPC_CLPRIM_STALLED = 91 PERF_PAPC_CLPRIM_STARVED_CCGSM = 92 PERF_PAPC_CLIPSM_IDLE = 93 PERF_PAPC_CLIPSM_BUSY = 94 PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95 PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96 PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97 PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98 PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99 PERF_PAPC_CLIPGA_IDLE = 100 PERF_PAPC_CLIPGA_BUSY = 101 PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102 PERF_PAPC_CLIPGA_STALLED = 103 PERF_PAPC_CLIP_IDLE = 104 PERF_PAPC_CLIP_BUSY = 105 PERF_PAPC_SU_IDLE = 106 PERF_PAPC_SU_BUSY = 107 PERF_PAPC_SU_STARVED_CLIP = 108 PERF_PAPC_SU_STALLED_SC = 109 PERF_PAPC_CL_DYN_SCLK_VLD = 110 PERF_PAPC_SU_DYN_SCLK_VLD = 111 PERF_PAPC_PA_REG_SCLK_VLD = 112 PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 113 PERF_PAPC_PASX_SE0_REQ = 114 PERF_PAPC_PASX_SE1_REQ = 115 PERF_PAPC_PASX_SE0_FIRST_VECTOR = 116 PERF_PAPC_PASX_SE0_SECOND_VECTOR = 117 PERF_PAPC_PASX_SE1_FIRST_VECTOR = 118 PERF_PAPC_PASX_SE1_SECOND_VECTOR = 119 PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120 PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121 PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 122 PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123 PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124 PERF_PAPC_SU_SE01_OUTPUT_PRIM = 125 PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126 PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127 PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 128 PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 129 PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 130 PERF_PAPC_SU_SE0_STALLED_SC = 131 PERF_PAPC_SU_SE1_STALLED_SC = 132 PERF_PAPC_SU_SE01_STALLED_SC = 133 PERF_PAPC_CLSM_CLIPPING_PRIM = 134 PERF_PAPC_SU_CULLED_PRIM = 135 PERF_PAPC_SU_OUTPUT_EOPG = 136 PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137 PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138 PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139 PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140 PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141 PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142 PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 143 PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 144 PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 145 PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 146 PERF_PAPC_SU_SE0_OUTPUT_EOPG = 147 PERF_PAPC_SU_SE1_OUTPUT_EOPG = 148 PERF_PAPC_SU_SE2_OUTPUT_EOPG = 149 PERF_PAPC_SU_SE3_OUTPUT_EOPG = 150 PERF_PAPC_SU_SE2_STALLED_SC = 151 PERF_PAPC_SU_SE3_STALLED_SC = 152 SU_PERFCNT_SEL = ctypes.c_uint32 # enum # values for enumeration 'SC_PERFCNT_SEL' SC_PERFCNT_SEL__enumvalues = { 0: 'SC_SRPS_WINDOW_VALID', 1: 'SC_PSSW_WINDOW_VALID', 2: 'SC_TPQZ_WINDOW_VALID', 3: 'SC_QZQP_WINDOW_VALID', 4: 'SC_TRPK_WINDOW_VALID', 5: 'SC_SRPS_WINDOW_VALID_BUSY', 6: 'SC_PSSW_WINDOW_VALID_BUSY', 7: 'SC_TPQZ_WINDOW_VALID_BUSY', 8: 'SC_QZQP_WINDOW_VALID_BUSY', 9: 'SC_TRPK_WINDOW_VALID_BUSY', 10: 'SC_STARVED_BY_PA', 11: 'SC_STALLED_BY_PRIMFIFO', 12: 'SC_STALLED_BY_DB_TILE', 13: 'SC_STARVED_BY_DB_TILE', 14: 'SC_STALLED_BY_TILEORDERFIFO', 15: 'SC_STALLED_BY_TILEFIFO', 16: 'SC_STALLED_BY_DB_QUAD', 17: 'SC_STARVED_BY_DB_QUAD', 18: 'SC_STALLED_BY_QUADFIFO', 19: 'SC_STALLED_BY_BCI', 20: 'SC_STALLED_BY_SPI', 21: 'SC_SCISSOR_DISCARD', 22: 'SC_BB_DISCARD', 23: 'SC_SUPERTILE_COUNT', 24: 'SC_SUPERTILE_PER_PRIM_H0', 25: 'SC_SUPERTILE_PER_PRIM_H1', 26: 'SC_SUPERTILE_PER_PRIM_H2', 27: 'SC_SUPERTILE_PER_PRIM_H3', 28: 'SC_SUPERTILE_PER_PRIM_H4', 29: 'SC_SUPERTILE_PER_PRIM_H5', 30: 'SC_SUPERTILE_PER_PRIM_H6', 31: 'SC_SUPERTILE_PER_PRIM_H7', 32: 'SC_SUPERTILE_PER_PRIM_H8', 33: 'SC_SUPERTILE_PER_PRIM_H9', 34: 'SC_SUPERTILE_PER_PRIM_H10', 35: 'SC_SUPERTILE_PER_PRIM_H11', 36: 'SC_SUPERTILE_PER_PRIM_H12', 37: 'SC_SUPERTILE_PER_PRIM_H13', 38: 'SC_SUPERTILE_PER_PRIM_H14', 39: 'SC_SUPERTILE_PER_PRIM_H15', 40: 'SC_SUPERTILE_PER_PRIM_H16', 41: 'SC_TILE_PER_PRIM_H0', 42: 'SC_TILE_PER_PRIM_H1', 43: 'SC_TILE_PER_PRIM_H2', 44: 'SC_TILE_PER_PRIM_H3', 45: 'SC_TILE_PER_PRIM_H4', 46: 'SC_TILE_PER_PRIM_H5', 47: 'SC_TILE_PER_PRIM_H6', 48: 'SC_TILE_PER_PRIM_H7', 49: 'SC_TILE_PER_PRIM_H8', 50: 'SC_TILE_PER_PRIM_H9', 51: 'SC_TILE_PER_PRIM_H10', 52: 'SC_TILE_PER_PRIM_H11', 53: 'SC_TILE_PER_PRIM_H12', 54: 'SC_TILE_PER_PRIM_H13', 55: 'SC_TILE_PER_PRIM_H14', 56: 'SC_TILE_PER_PRIM_H15', 57: 'SC_TILE_PER_PRIM_H16', 58: 'SC_TILE_PER_SUPERTILE_H0', 59: 'SC_TILE_PER_SUPERTILE_H1', 60: 'SC_TILE_PER_SUPERTILE_H2', 61: 'SC_TILE_PER_SUPERTILE_H3', 62: 'SC_TILE_PER_SUPERTILE_H4', 63: 'SC_TILE_PER_SUPERTILE_H5', 64: 'SC_TILE_PER_SUPERTILE_H6', 65: 'SC_TILE_PER_SUPERTILE_H7', 66: 'SC_TILE_PER_SUPERTILE_H8', 67: 'SC_TILE_PER_SUPERTILE_H9', 68: 'SC_TILE_PER_SUPERTILE_H10', 69: 'SC_TILE_PER_SUPERTILE_H11', 70: 'SC_TILE_PER_SUPERTILE_H12', 71: 'SC_TILE_PER_SUPERTILE_H13', 72: 'SC_TILE_PER_SUPERTILE_H14', 73: 'SC_TILE_PER_SUPERTILE_H15', 74: 'SC_TILE_PER_SUPERTILE_H16', 75: 'SC_TILE_PICKED_H1', 76: 'SC_TILE_PICKED_H2', 77: 'SC_TILE_PICKED_H3', 78: 'SC_TILE_PICKED_H4', 79: 'SC_QZ0_MULTI_GPU_TILE_DISCARD', 80: 'SC_QZ1_MULTI_GPU_TILE_DISCARD', 81: 'SC_QZ2_MULTI_GPU_TILE_DISCARD', 82: 'SC_QZ3_MULTI_GPU_TILE_DISCARD', 83: 'SC_QZ0_TILE_COUNT', 84: 'SC_QZ1_TILE_COUNT', 85: 'SC_QZ2_TILE_COUNT', 86: 'SC_QZ3_TILE_COUNT', 87: 'SC_QZ0_TILE_COVERED_COUNT', 88: 'SC_QZ1_TILE_COVERED_COUNT', 89: 'SC_QZ2_TILE_COVERED_COUNT', 90: 'SC_QZ3_TILE_COVERED_COUNT', 91: 'SC_QZ0_TILE_NOT_COVERED_COUNT', 92: 'SC_QZ1_TILE_NOT_COVERED_COUNT', 93: 'SC_QZ2_TILE_NOT_COVERED_COUNT', 94: 'SC_QZ3_TILE_NOT_COVERED_COUNT', 95: 'SC_QZ0_QUAD_PER_TILE_H0', 96: 'SC_QZ0_QUAD_PER_TILE_H1', 97: 'SC_QZ0_QUAD_PER_TILE_H2', 98: 'SC_QZ0_QUAD_PER_TILE_H3', 99: 'SC_QZ0_QUAD_PER_TILE_H4', 100: 'SC_QZ0_QUAD_PER_TILE_H5', 101: 'SC_QZ0_QUAD_PER_TILE_H6', 102: 'SC_QZ0_QUAD_PER_TILE_H7', 103: 'SC_QZ0_QUAD_PER_TILE_H8', 104: 'SC_QZ0_QUAD_PER_TILE_H9', 105: 'SC_QZ0_QUAD_PER_TILE_H10', 106: 'SC_QZ0_QUAD_PER_TILE_H11', 107: 'SC_QZ0_QUAD_PER_TILE_H12', 108: 'SC_QZ0_QUAD_PER_TILE_H13', 109: 'SC_QZ0_QUAD_PER_TILE_H14', 110: 'SC_QZ0_QUAD_PER_TILE_H15', 111: 'SC_QZ0_QUAD_PER_TILE_H16', 112: 'SC_QZ1_QUAD_PER_TILE_H0', 113: 'SC_QZ1_QUAD_PER_TILE_H1', 114: 'SC_QZ1_QUAD_PER_TILE_H2', 115: 'SC_QZ1_QUAD_PER_TILE_H3', 116: 'SC_QZ1_QUAD_PER_TILE_H4', 117: 'SC_QZ1_QUAD_PER_TILE_H5', 118: 'SC_QZ1_QUAD_PER_TILE_H6', 119: 'SC_QZ1_QUAD_PER_TILE_H7', 120: 'SC_QZ1_QUAD_PER_TILE_H8', 121: 'SC_QZ1_QUAD_PER_TILE_H9', 122: 'SC_QZ1_QUAD_PER_TILE_H10', 123: 'SC_QZ1_QUAD_PER_TILE_H11', 124: 'SC_QZ1_QUAD_PER_TILE_H12', 125: 'SC_QZ1_QUAD_PER_TILE_H13', 126: 'SC_QZ1_QUAD_PER_TILE_H14', 127: 'SC_QZ1_QUAD_PER_TILE_H15', 128: 'SC_QZ1_QUAD_PER_TILE_H16', 129: 'SC_QZ2_QUAD_PER_TILE_H0', 130: 'SC_QZ2_QUAD_PER_TILE_H1', 131: 'SC_QZ2_QUAD_PER_TILE_H2', 132: 'SC_QZ2_QUAD_PER_TILE_H3', 133: 'SC_QZ2_QUAD_PER_TILE_H4', 134: 'SC_QZ2_QUAD_PER_TILE_H5', 135: 'SC_QZ2_QUAD_PER_TILE_H6', 136: 'SC_QZ2_QUAD_PER_TILE_H7', 137: 'SC_QZ2_QUAD_PER_TILE_H8', 138: 'SC_QZ2_QUAD_PER_TILE_H9', 139: 'SC_QZ2_QUAD_PER_TILE_H10', 140: 'SC_QZ2_QUAD_PER_TILE_H11', 141: 'SC_QZ2_QUAD_PER_TILE_H12', 142: 'SC_QZ2_QUAD_PER_TILE_H13', 143: 'SC_QZ2_QUAD_PER_TILE_H14', 144: 'SC_QZ2_QUAD_PER_TILE_H15', 145: 'SC_QZ2_QUAD_PER_TILE_H16', 146: 'SC_QZ3_QUAD_PER_TILE_H0', 147: 'SC_QZ3_QUAD_PER_TILE_H1', 148: 'SC_QZ3_QUAD_PER_TILE_H2', 149: 'SC_QZ3_QUAD_PER_TILE_H3', 150: 'SC_QZ3_QUAD_PER_TILE_H4', 151: 'SC_QZ3_QUAD_PER_TILE_H5', 152: 'SC_QZ3_QUAD_PER_TILE_H6', 153: 'SC_QZ3_QUAD_PER_TILE_H7', 154: 'SC_QZ3_QUAD_PER_TILE_H8', 155: 'SC_QZ3_QUAD_PER_TILE_H9', 156: 'SC_QZ3_QUAD_PER_TILE_H10', 157: 'SC_QZ3_QUAD_PER_TILE_H11', 158: 'SC_QZ3_QUAD_PER_TILE_H12', 159: 'SC_QZ3_QUAD_PER_TILE_H13', 160: 'SC_QZ3_QUAD_PER_TILE_H14', 161: 'SC_QZ3_QUAD_PER_TILE_H15', 162: 'SC_QZ3_QUAD_PER_TILE_H16', 163: 'SC_QZ0_QUAD_COUNT', 164: 'SC_QZ1_QUAD_COUNT', 165: 'SC_QZ2_QUAD_COUNT', 166: 'SC_QZ3_QUAD_COUNT', 167: 'SC_P0_HIZ_TILE_COUNT', 168: 'SC_P1_HIZ_TILE_COUNT', 169: 'SC_P2_HIZ_TILE_COUNT', 170: 'SC_P3_HIZ_TILE_COUNT', 171: 'SC_P0_HIZ_QUAD_PER_TILE_H0', 172: 'SC_P0_HIZ_QUAD_PER_TILE_H1', 173: 'SC_P0_HIZ_QUAD_PER_TILE_H2', 174: 'SC_P0_HIZ_QUAD_PER_TILE_H3', 175: 'SC_P0_HIZ_QUAD_PER_TILE_H4', 176: 'SC_P0_HIZ_QUAD_PER_TILE_H5', 177: 'SC_P0_HIZ_QUAD_PER_TILE_H6', 178: 'SC_P0_HIZ_QUAD_PER_TILE_H7', 179: 'SC_P0_HIZ_QUAD_PER_TILE_H8', 180: 'SC_P0_HIZ_QUAD_PER_TILE_H9', 181: 'SC_P0_HIZ_QUAD_PER_TILE_H10', 182: 'SC_P0_HIZ_QUAD_PER_TILE_H11', 183: 'SC_P0_HIZ_QUAD_PER_TILE_H12', 184: 'SC_P0_HIZ_QUAD_PER_TILE_H13', 185: 'SC_P0_HIZ_QUAD_PER_TILE_H14', 186: 'SC_P0_HIZ_QUAD_PER_TILE_H15', 187: 'SC_P0_HIZ_QUAD_PER_TILE_H16', 188: 'SC_P1_HIZ_QUAD_PER_TILE_H0', 189: 'SC_P1_HIZ_QUAD_PER_TILE_H1', 190: 'SC_P1_HIZ_QUAD_PER_TILE_H2', 191: 'SC_P1_HIZ_QUAD_PER_TILE_H3', 192: 'SC_P1_HIZ_QUAD_PER_TILE_H4', 193: 'SC_P1_HIZ_QUAD_PER_TILE_H5', 194: 'SC_P1_HIZ_QUAD_PER_TILE_H6', 195: 'SC_P1_HIZ_QUAD_PER_TILE_H7', 196: 'SC_P1_HIZ_QUAD_PER_TILE_H8', 197: 'SC_P1_HIZ_QUAD_PER_TILE_H9', 198: 'SC_P1_HIZ_QUAD_PER_TILE_H10', 199: 'SC_P1_HIZ_QUAD_PER_TILE_H11', 200: 'SC_P1_HIZ_QUAD_PER_TILE_H12', 201: 'SC_P1_HIZ_QUAD_PER_TILE_H13', 202: 'SC_P1_HIZ_QUAD_PER_TILE_H14', 203: 'SC_P1_HIZ_QUAD_PER_TILE_H15', 204: 'SC_P1_HIZ_QUAD_PER_TILE_H16', 205: 'SC_P2_HIZ_QUAD_PER_TILE_H0', 206: 'SC_P2_HIZ_QUAD_PER_TILE_H1', 207: 'SC_P2_HIZ_QUAD_PER_TILE_H2', 208: 'SC_P2_HIZ_QUAD_PER_TILE_H3', 209: 'SC_P2_HIZ_QUAD_PER_TILE_H4', 210: 'SC_P2_HIZ_QUAD_PER_TILE_H5', 211: 'SC_P2_HIZ_QUAD_PER_TILE_H6', 212: 'SC_P2_HIZ_QUAD_PER_TILE_H7', 213: 'SC_P2_HIZ_QUAD_PER_TILE_H8', 214: 'SC_P2_HIZ_QUAD_PER_TILE_H9', 215: 'SC_P2_HIZ_QUAD_PER_TILE_H10', 216: 'SC_P2_HIZ_QUAD_PER_TILE_H11', 217: 'SC_P2_HIZ_QUAD_PER_TILE_H12', 218: 'SC_P2_HIZ_QUAD_PER_TILE_H13', 219: 'SC_P2_HIZ_QUAD_PER_TILE_H14', 220: 'SC_P2_HIZ_QUAD_PER_TILE_H15', 221: 'SC_P2_HIZ_QUAD_PER_TILE_H16', 222: 'SC_P3_HIZ_QUAD_PER_TILE_H0', 223: 'SC_P3_HIZ_QUAD_PER_TILE_H1', 224: 'SC_P3_HIZ_QUAD_PER_TILE_H2', 225: 'SC_P3_HIZ_QUAD_PER_TILE_H3', 226: 'SC_P3_HIZ_QUAD_PER_TILE_H4', 227: 'SC_P3_HIZ_QUAD_PER_TILE_H5', 228: 'SC_P3_HIZ_QUAD_PER_TILE_H6', 229: 'SC_P3_HIZ_QUAD_PER_TILE_H7', 230: 'SC_P3_HIZ_QUAD_PER_TILE_H8', 231: 'SC_P3_HIZ_QUAD_PER_TILE_H9', 232: 'SC_P3_HIZ_QUAD_PER_TILE_H10', 233: 'SC_P3_HIZ_QUAD_PER_TILE_H11', 234: 'SC_P3_HIZ_QUAD_PER_TILE_H12', 235: 'SC_P3_HIZ_QUAD_PER_TILE_H13', 236: 'SC_P3_HIZ_QUAD_PER_TILE_H14', 237: 'SC_P3_HIZ_QUAD_PER_TILE_H15', 238: 'SC_P3_HIZ_QUAD_PER_TILE_H16', 239: 'SC_P0_HIZ_QUAD_COUNT', 240: 'SC_P1_HIZ_QUAD_COUNT', 241: 'SC_P2_HIZ_QUAD_COUNT', 242: 'SC_P3_HIZ_QUAD_COUNT', 243: 'SC_P0_DETAIL_QUAD_COUNT', 244: 'SC_P1_DETAIL_QUAD_COUNT', 245: 'SC_P2_DETAIL_QUAD_COUNT', 246: 'SC_P3_DETAIL_QUAD_COUNT', 247: 'SC_P0_DETAIL_QUAD_WITH_1_PIX', 248: 'SC_P0_DETAIL_QUAD_WITH_2_PIX', 249: 'SC_P0_DETAIL_QUAD_WITH_3_PIX', 250: 'SC_P0_DETAIL_QUAD_WITH_4_PIX', 251: 'SC_P1_DETAIL_QUAD_WITH_1_PIX', 252: 'SC_P1_DETAIL_QUAD_WITH_2_PIX', 253: 'SC_P1_DETAIL_QUAD_WITH_3_PIX', 254: 'SC_P1_DETAIL_QUAD_WITH_4_PIX', 255: 'SC_P2_DETAIL_QUAD_WITH_1_PIX', 256: 'SC_P2_DETAIL_QUAD_WITH_2_PIX', 257: 'SC_P2_DETAIL_QUAD_WITH_3_PIX', 258: 'SC_P2_DETAIL_QUAD_WITH_4_PIX', 259: 'SC_P3_DETAIL_QUAD_WITH_1_PIX', 260: 'SC_P3_DETAIL_QUAD_WITH_2_PIX', 261: 'SC_P3_DETAIL_QUAD_WITH_3_PIX', 262: 'SC_P3_DETAIL_QUAD_WITH_4_PIX', 263: 'SC_EARLYZ_QUAD_COUNT', 264: 'SC_EARLYZ_QUAD_WITH_1_PIX', 265: 'SC_EARLYZ_QUAD_WITH_2_PIX', 266: 'SC_EARLYZ_QUAD_WITH_3_PIX', 267: 'SC_EARLYZ_QUAD_WITH_4_PIX', 268: 'SC_PKR_QUAD_PER_ROW_H1', 269: 'SC_PKR_QUAD_PER_ROW_H2', 270: 'SC_PKR_4X2_QUAD_SPLIT', 271: 'SC_PKR_4X2_FILL_QUAD', 272: 'SC_PKR_END_OF_VECTOR', 273: 'SC_PKR_CONTROL_XFER', 274: 'SC_PKR_DBHANG_FORCE_EOV', 275: 'SC_REG_SCLK_BUSY', 276: 'SC_GRP0_DYN_SCLK_BUSY', 277: 'SC_GRP1_DYN_SCLK_BUSY', 278: 'SC_GRP2_DYN_SCLK_BUSY', 279: 'SC_GRP3_DYN_SCLK_BUSY', 280: 'SC_GRP4_DYN_SCLK_BUSY', 281: 'SC_PA0_SC_DATA_FIFO_RD', 282: 'SC_PA0_SC_DATA_FIFO_WE', 283: 'SC_PA1_SC_DATA_FIFO_RD', 284: 'SC_PA1_SC_DATA_FIFO_WE', 285: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', 286: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 287: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', 288: 'SC_PS_ARB_STALLED_FROM_BELOW', 289: 'SC_PS_ARB_STARVED_FROM_ABOVE', 290: 'SC_PS_ARB_SC_BUSY', 291: 'SC_PS_ARB_PA_SC_BUSY', 292: 'SC_PA2_SC_DATA_FIFO_RD', 293: 'SC_PA2_SC_DATA_FIFO_WE', 294: 'SC_PA3_SC_DATA_FIFO_RD', 295: 'SC_PA3_SC_DATA_FIFO_WE', 296: 'SC_PA_SC_DEALLOC_0_0_WE', 297: 'SC_PA_SC_DEALLOC_0_1_WE', 298: 'SC_PA_SC_DEALLOC_1_0_WE', 299: 'SC_PA_SC_DEALLOC_1_1_WE', 300: 'SC_PA_SC_DEALLOC_2_0_WE', 301: 'SC_PA_SC_DEALLOC_2_1_WE', 302: 'SC_PA_SC_DEALLOC_3_0_WE', 303: 'SC_PA_SC_DEALLOC_3_1_WE', 304: 'SC_PA0_SC_EOP_WE', 305: 'SC_PA0_SC_EOPG_WE', 306: 'SC_PA0_SC_EVENT_WE', 307: 'SC_PA1_SC_EOP_WE', 308: 'SC_PA1_SC_EOPG_WE', 309: 'SC_PA1_SC_EVENT_WE', 310: 'SC_PA2_SC_EOP_WE', 311: 'SC_PA2_SC_EOPG_WE', 312: 'SC_PA2_SC_EVENT_WE', 313: 'SC_PA3_SC_EOP_WE', 314: 'SC_PA3_SC_EOPG_WE', 315: 'SC_PA3_SC_EVENT_WE', 316: 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', 317: 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', 318: 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', 319: 'SC_PS_ARB_EOP_POP_SYNC_POP', 320: 'SC_PS_ARB_EVENT_SYNC_POP', 321: 'SC_SC_PS_ENG_MULTICYCLE_BUBBLE', 322: 'SC_PA0_SC_FPOV_WE', 323: 'SC_PA1_SC_FPOV_WE', 324: 'SC_PA2_SC_FPOV_WE', 325: 'SC_PA3_SC_FPOV_WE', 326: 'SC_PA0_SC_LPOV_WE', 327: 'SC_PA1_SC_LPOV_WE', 328: 'SC_PA2_SC_LPOV_WE', 329: 'SC_PA3_SC_LPOV_WE', 330: 'SC_SC_SPI_DEALLOC_0_0', 331: 'SC_SC_SPI_DEALLOC_0_1', 332: 'SC_SC_SPI_DEALLOC_0_2', 333: 'SC_SC_SPI_DEALLOC_1_0', 334: 'SC_SC_SPI_DEALLOC_1_1', 335: 'SC_SC_SPI_DEALLOC_1_2', 336: 'SC_SC_SPI_DEALLOC_2_0', 337: 'SC_SC_SPI_DEALLOC_2_1', 338: 'SC_SC_SPI_DEALLOC_2_2', 339: 'SC_SC_SPI_DEALLOC_3_0', 340: 'SC_SC_SPI_DEALLOC_3_1', 341: 'SC_SC_SPI_DEALLOC_3_2', 342: 'SC_SC_SPI_FPOV_0', 343: 'SC_SC_SPI_FPOV_1', 344: 'SC_SC_SPI_FPOV_2', 345: 'SC_SC_SPI_FPOV_3', 346: 'SC_SC_SPI_EVENT', 347: 'SC_PS_TS_EVENT_FIFO_PUSH', 348: 'SC_PS_TS_EVENT_FIFO_POP', 349: 'SC_PS_CTX_DONE_FIFO_PUSH', 350: 'SC_PS_CTX_DONE_FIFO_POP', 351: 'SC_MULTICYCLE_BUBBLE_FREEZE', 352: 'SC_EOP_SYNC_WINDOW', 353: 'SC_PA0_SC_NULL_WE', 354: 'SC_PA0_SC_NULL_DEALLOC_WE', 355: 'SC_PA0_SC_DATA_FIFO_EOPG_RD', 356: 'SC_PA0_SC_DATA_FIFO_EOP_RD', 357: 'SC_PA0_SC_DEALLOC_0_RD', 358: 'SC_PA0_SC_DEALLOC_1_RD', 359: 'SC_PA1_SC_DATA_FIFO_EOPG_RD', 360: 'SC_PA1_SC_DATA_FIFO_EOP_RD', 361: 'SC_PA1_SC_DEALLOC_0_RD', 362: 'SC_PA1_SC_DEALLOC_1_RD', 363: 'SC_PA1_SC_NULL_WE', 364: 'SC_PA1_SC_NULL_DEALLOC_WE', 365: 'SC_PA2_SC_DATA_FIFO_EOPG_RD', 366: 'SC_PA2_SC_DATA_FIFO_EOP_RD', 367: 'SC_PA2_SC_DEALLOC_0_RD', 368: 'SC_PA2_SC_DEALLOC_1_RD', 369: 'SC_PA2_SC_NULL_WE', 370: 'SC_PA2_SC_NULL_DEALLOC_WE', 371: 'SC_PA3_SC_DATA_FIFO_EOPG_RD', 372: 'SC_PA3_SC_DATA_FIFO_EOP_RD', 373: 'SC_PA3_SC_DEALLOC_0_RD', 374: 'SC_PA3_SC_DEALLOC_1_RD', 375: 'SC_PA3_SC_NULL_WE', 376: 'SC_PA3_SC_NULL_DEALLOC_WE', 377: 'SC_PS_PA0_SC_FIFO_EMPTY', 378: 'SC_PS_PA0_SC_FIFO_FULL', 379: 'SC_PA0_PS_DATA_SEND', 380: 'SC_PS_PA1_SC_FIFO_EMPTY', 381: 'SC_PS_PA1_SC_FIFO_FULL', 382: 'SC_PA1_PS_DATA_SEND', 383: 'SC_PS_PA2_SC_FIFO_EMPTY', 384: 'SC_PS_PA2_SC_FIFO_FULL', 385: 'SC_PA2_PS_DATA_SEND', 386: 'SC_PS_PA3_SC_FIFO_EMPTY', 387: 'SC_PS_PA3_SC_FIFO_FULL', 388: 'SC_PA3_PS_DATA_SEND', 389: 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', 390: 'SC_BUSY_CNT_NOT_ZERO', 391: 'SC_BM_BUSY', 392: 'SC_BACKEND_BUSY', 393: 'SC_SCF_SCB_INTERFACE_BUSY', 394: 'SC_SCB_BUSY', 395: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', 396: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', 397: 'SC_PBB_BIN_HIST_NUM_PRIMS', 398: 'SC_PBB_BATCH_HIST_NUM_PRIMS', 399: 'SC_PBB_BIN_HIST_NUM_CONTEXTS', 400: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', 401: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', 402: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', 403: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', 404: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', 405: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', 406: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', 407: 'SC_PBB_BUSY', 408: 'SC_PBB_BUSY_AND_RTR', 409: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', 410: 'SC_PBB_NUM_BINS', 411: 'SC_PBB_END_OF_BIN', 412: 'SC_PBB_END_OF_BATCH', 413: 'SC_PBB_PRIMBIN_PROCESSED', 414: 'SC_PBB_PRIM_ADDED_TO_BATCH', 415: 'SC_PBB_NONBINNED_PRIM', 416: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 417: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', 418: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', 419: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', 420: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', 421: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', 422: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', 423: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', 424: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', 425: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', 426: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', 427: 'SC_POPS_INTRA_WAVE_OVERLAPS', 428: 'SC_POPS_FORCE_EOV', 429: 'SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE', 430: 'SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE', } SC_SRPS_WINDOW_VALID = 0 SC_PSSW_WINDOW_VALID = 1 SC_TPQZ_WINDOW_VALID = 2 SC_QZQP_WINDOW_VALID = 3 SC_TRPK_WINDOW_VALID = 4 SC_SRPS_WINDOW_VALID_BUSY = 5 SC_PSSW_WINDOW_VALID_BUSY = 6 SC_TPQZ_WINDOW_VALID_BUSY = 7 SC_QZQP_WINDOW_VALID_BUSY = 8 SC_TRPK_WINDOW_VALID_BUSY = 9 SC_STARVED_BY_PA = 10 SC_STALLED_BY_PRIMFIFO = 11 SC_STALLED_BY_DB_TILE = 12 SC_STARVED_BY_DB_TILE = 13 SC_STALLED_BY_TILEORDERFIFO = 14 SC_STALLED_BY_TILEFIFO = 15 SC_STALLED_BY_DB_QUAD = 16 SC_STARVED_BY_DB_QUAD = 17 SC_STALLED_BY_QUADFIFO = 18 SC_STALLED_BY_BCI = 19 SC_STALLED_BY_SPI = 20 SC_SCISSOR_DISCARD = 21 SC_BB_DISCARD = 22 SC_SUPERTILE_COUNT = 23 SC_SUPERTILE_PER_PRIM_H0 = 24 SC_SUPERTILE_PER_PRIM_H1 = 25 SC_SUPERTILE_PER_PRIM_H2 = 26 SC_SUPERTILE_PER_PRIM_H3 = 27 SC_SUPERTILE_PER_PRIM_H4 = 28 SC_SUPERTILE_PER_PRIM_H5 = 29 SC_SUPERTILE_PER_PRIM_H6 = 30 SC_SUPERTILE_PER_PRIM_H7 = 31 SC_SUPERTILE_PER_PRIM_H8 = 32 SC_SUPERTILE_PER_PRIM_H9 = 33 SC_SUPERTILE_PER_PRIM_H10 = 34 SC_SUPERTILE_PER_PRIM_H11 = 35 SC_SUPERTILE_PER_PRIM_H12 = 36 SC_SUPERTILE_PER_PRIM_H13 = 37 SC_SUPERTILE_PER_PRIM_H14 = 38 SC_SUPERTILE_PER_PRIM_H15 = 39 SC_SUPERTILE_PER_PRIM_H16 = 40 SC_TILE_PER_PRIM_H0 = 41 SC_TILE_PER_PRIM_H1 = 42 SC_TILE_PER_PRIM_H2 = 43 SC_TILE_PER_PRIM_H3 = 44 SC_TILE_PER_PRIM_H4 = 45 SC_TILE_PER_PRIM_H5 = 46 SC_TILE_PER_PRIM_H6 = 47 SC_TILE_PER_PRIM_H7 = 48 SC_TILE_PER_PRIM_H8 = 49 SC_TILE_PER_PRIM_H9 = 50 SC_TILE_PER_PRIM_H10 = 51 SC_TILE_PER_PRIM_H11 = 52 SC_TILE_PER_PRIM_H12 = 53 SC_TILE_PER_PRIM_H13 = 54 SC_TILE_PER_PRIM_H14 = 55 SC_TILE_PER_PRIM_H15 = 56 SC_TILE_PER_PRIM_H16 = 57 SC_TILE_PER_SUPERTILE_H0 = 58 SC_TILE_PER_SUPERTILE_H1 = 59 SC_TILE_PER_SUPERTILE_H2 = 60 SC_TILE_PER_SUPERTILE_H3 = 61 SC_TILE_PER_SUPERTILE_H4 = 62 SC_TILE_PER_SUPERTILE_H5 = 63 SC_TILE_PER_SUPERTILE_H6 = 64 SC_TILE_PER_SUPERTILE_H7 = 65 SC_TILE_PER_SUPERTILE_H8 = 66 SC_TILE_PER_SUPERTILE_H9 = 67 SC_TILE_PER_SUPERTILE_H10 = 68 SC_TILE_PER_SUPERTILE_H11 = 69 SC_TILE_PER_SUPERTILE_H12 = 70 SC_TILE_PER_SUPERTILE_H13 = 71 SC_TILE_PER_SUPERTILE_H14 = 72 SC_TILE_PER_SUPERTILE_H15 = 73 SC_TILE_PER_SUPERTILE_H16 = 74 SC_TILE_PICKED_H1 = 75 SC_TILE_PICKED_H2 = 76 SC_TILE_PICKED_H3 = 77 SC_TILE_PICKED_H4 = 78 SC_QZ0_MULTI_GPU_TILE_DISCARD = 79 SC_QZ1_MULTI_GPU_TILE_DISCARD = 80 SC_QZ2_MULTI_GPU_TILE_DISCARD = 81 SC_QZ3_MULTI_GPU_TILE_DISCARD = 82 SC_QZ0_TILE_COUNT = 83 SC_QZ1_TILE_COUNT = 84 SC_QZ2_TILE_COUNT = 85 SC_QZ3_TILE_COUNT = 86 SC_QZ0_TILE_COVERED_COUNT = 87 SC_QZ1_TILE_COVERED_COUNT = 88 SC_QZ2_TILE_COVERED_COUNT = 89 SC_QZ3_TILE_COVERED_COUNT = 90 SC_QZ0_TILE_NOT_COVERED_COUNT = 91 SC_QZ1_TILE_NOT_COVERED_COUNT = 92 SC_QZ2_TILE_NOT_COVERED_COUNT = 93 SC_QZ3_TILE_NOT_COVERED_COUNT = 94 SC_QZ0_QUAD_PER_TILE_H0 = 95 SC_QZ0_QUAD_PER_TILE_H1 = 96 SC_QZ0_QUAD_PER_TILE_H2 = 97 SC_QZ0_QUAD_PER_TILE_H3 = 98 SC_QZ0_QUAD_PER_TILE_H4 = 99 SC_QZ0_QUAD_PER_TILE_H5 = 100 SC_QZ0_QUAD_PER_TILE_H6 = 101 SC_QZ0_QUAD_PER_TILE_H7 = 102 SC_QZ0_QUAD_PER_TILE_H8 = 103 SC_QZ0_QUAD_PER_TILE_H9 = 104 SC_QZ0_QUAD_PER_TILE_H10 = 105 SC_QZ0_QUAD_PER_TILE_H11 = 106 SC_QZ0_QUAD_PER_TILE_H12 = 107 SC_QZ0_QUAD_PER_TILE_H13 = 108 SC_QZ0_QUAD_PER_TILE_H14 = 109 SC_QZ0_QUAD_PER_TILE_H15 = 110 SC_QZ0_QUAD_PER_TILE_H16 = 111 SC_QZ1_QUAD_PER_TILE_H0 = 112 SC_QZ1_QUAD_PER_TILE_H1 = 113 SC_QZ1_QUAD_PER_TILE_H2 = 114 SC_QZ1_QUAD_PER_TILE_H3 = 115 SC_QZ1_QUAD_PER_TILE_H4 = 116 SC_QZ1_QUAD_PER_TILE_H5 = 117 SC_QZ1_QUAD_PER_TILE_H6 = 118 SC_QZ1_QUAD_PER_TILE_H7 = 119 SC_QZ1_QUAD_PER_TILE_H8 = 120 SC_QZ1_QUAD_PER_TILE_H9 = 121 SC_QZ1_QUAD_PER_TILE_H10 = 122 SC_QZ1_QUAD_PER_TILE_H11 = 123 SC_QZ1_QUAD_PER_TILE_H12 = 124 SC_QZ1_QUAD_PER_TILE_H13 = 125 SC_QZ1_QUAD_PER_TILE_H14 = 126 SC_QZ1_QUAD_PER_TILE_H15 = 127 SC_QZ1_QUAD_PER_TILE_H16 = 128 SC_QZ2_QUAD_PER_TILE_H0 = 129 SC_QZ2_QUAD_PER_TILE_H1 = 130 SC_QZ2_QUAD_PER_TILE_H2 = 131 SC_QZ2_QUAD_PER_TILE_H3 = 132 SC_QZ2_QUAD_PER_TILE_H4 = 133 SC_QZ2_QUAD_PER_TILE_H5 = 134 SC_QZ2_QUAD_PER_TILE_H6 = 135 SC_QZ2_QUAD_PER_TILE_H7 = 136 SC_QZ2_QUAD_PER_TILE_H8 = 137 SC_QZ2_QUAD_PER_TILE_H9 = 138 SC_QZ2_QUAD_PER_TILE_H10 = 139 SC_QZ2_QUAD_PER_TILE_H11 = 140 SC_QZ2_QUAD_PER_TILE_H12 = 141 SC_QZ2_QUAD_PER_TILE_H13 = 142 SC_QZ2_QUAD_PER_TILE_H14 = 143 SC_QZ2_QUAD_PER_TILE_H15 = 144 SC_QZ2_QUAD_PER_TILE_H16 = 145 SC_QZ3_QUAD_PER_TILE_H0 = 146 SC_QZ3_QUAD_PER_TILE_H1 = 147 SC_QZ3_QUAD_PER_TILE_H2 = 148 SC_QZ3_QUAD_PER_TILE_H3 = 149 SC_QZ3_QUAD_PER_TILE_H4 = 150 SC_QZ3_QUAD_PER_TILE_H5 = 151 SC_QZ3_QUAD_PER_TILE_H6 = 152 SC_QZ3_QUAD_PER_TILE_H7 = 153 SC_QZ3_QUAD_PER_TILE_H8 = 154 SC_QZ3_QUAD_PER_TILE_H9 = 155 SC_QZ3_QUAD_PER_TILE_H10 = 156 SC_QZ3_QUAD_PER_TILE_H11 = 157 SC_QZ3_QUAD_PER_TILE_H12 = 158 SC_QZ3_QUAD_PER_TILE_H13 = 159 SC_QZ3_QUAD_PER_TILE_H14 = 160 SC_QZ3_QUAD_PER_TILE_H15 = 161 SC_QZ3_QUAD_PER_TILE_H16 = 162 SC_QZ0_QUAD_COUNT = 163 SC_QZ1_QUAD_COUNT = 164 SC_QZ2_QUAD_COUNT = 165 SC_QZ3_QUAD_COUNT = 166 SC_P0_HIZ_TILE_COUNT = 167 SC_P1_HIZ_TILE_COUNT = 168 SC_P2_HIZ_TILE_COUNT = 169 SC_P3_HIZ_TILE_COUNT = 170 SC_P0_HIZ_QUAD_PER_TILE_H0 = 171 SC_P0_HIZ_QUAD_PER_TILE_H1 = 172 SC_P0_HIZ_QUAD_PER_TILE_H2 = 173 SC_P0_HIZ_QUAD_PER_TILE_H3 = 174 SC_P0_HIZ_QUAD_PER_TILE_H4 = 175 SC_P0_HIZ_QUAD_PER_TILE_H5 = 176 SC_P0_HIZ_QUAD_PER_TILE_H6 = 177 SC_P0_HIZ_QUAD_PER_TILE_H7 = 178 SC_P0_HIZ_QUAD_PER_TILE_H8 = 179 SC_P0_HIZ_QUAD_PER_TILE_H9 = 180 SC_P0_HIZ_QUAD_PER_TILE_H10 = 181 SC_P0_HIZ_QUAD_PER_TILE_H11 = 182 SC_P0_HIZ_QUAD_PER_TILE_H12 = 183 SC_P0_HIZ_QUAD_PER_TILE_H13 = 184 SC_P0_HIZ_QUAD_PER_TILE_H14 = 185 SC_P0_HIZ_QUAD_PER_TILE_H15 = 186 SC_P0_HIZ_QUAD_PER_TILE_H16 = 187 SC_P1_HIZ_QUAD_PER_TILE_H0 = 188 SC_P1_HIZ_QUAD_PER_TILE_H1 = 189 SC_P1_HIZ_QUAD_PER_TILE_H2 = 190 SC_P1_HIZ_QUAD_PER_TILE_H3 = 191 SC_P1_HIZ_QUAD_PER_TILE_H4 = 192 SC_P1_HIZ_QUAD_PER_TILE_H5 = 193 SC_P1_HIZ_QUAD_PER_TILE_H6 = 194 SC_P1_HIZ_QUAD_PER_TILE_H7 = 195 SC_P1_HIZ_QUAD_PER_TILE_H8 = 196 SC_P1_HIZ_QUAD_PER_TILE_H9 = 197 SC_P1_HIZ_QUAD_PER_TILE_H10 = 198 SC_P1_HIZ_QUAD_PER_TILE_H11 = 199 SC_P1_HIZ_QUAD_PER_TILE_H12 = 200 SC_P1_HIZ_QUAD_PER_TILE_H13 = 201 SC_P1_HIZ_QUAD_PER_TILE_H14 = 202 SC_P1_HIZ_QUAD_PER_TILE_H15 = 203 SC_P1_HIZ_QUAD_PER_TILE_H16 = 204 SC_P2_HIZ_QUAD_PER_TILE_H0 = 205 SC_P2_HIZ_QUAD_PER_TILE_H1 = 206 SC_P2_HIZ_QUAD_PER_TILE_H2 = 207 SC_P2_HIZ_QUAD_PER_TILE_H3 = 208 SC_P2_HIZ_QUAD_PER_TILE_H4 = 209 SC_P2_HIZ_QUAD_PER_TILE_H5 = 210 SC_P2_HIZ_QUAD_PER_TILE_H6 = 211 SC_P2_HIZ_QUAD_PER_TILE_H7 = 212 SC_P2_HIZ_QUAD_PER_TILE_H8 = 213 SC_P2_HIZ_QUAD_PER_TILE_H9 = 214 SC_P2_HIZ_QUAD_PER_TILE_H10 = 215 SC_P2_HIZ_QUAD_PER_TILE_H11 = 216 SC_P2_HIZ_QUAD_PER_TILE_H12 = 217 SC_P2_HIZ_QUAD_PER_TILE_H13 = 218 SC_P2_HIZ_QUAD_PER_TILE_H14 = 219 SC_P2_HIZ_QUAD_PER_TILE_H15 = 220 SC_P2_HIZ_QUAD_PER_TILE_H16 = 221 SC_P3_HIZ_QUAD_PER_TILE_H0 = 222 SC_P3_HIZ_QUAD_PER_TILE_H1 = 223 SC_P3_HIZ_QUAD_PER_TILE_H2 = 224 SC_P3_HIZ_QUAD_PER_TILE_H3 = 225 SC_P3_HIZ_QUAD_PER_TILE_H4 = 226 SC_P3_HIZ_QUAD_PER_TILE_H5 = 227 SC_P3_HIZ_QUAD_PER_TILE_H6 = 228 SC_P3_HIZ_QUAD_PER_TILE_H7 = 229 SC_P3_HIZ_QUAD_PER_TILE_H8 = 230 SC_P3_HIZ_QUAD_PER_TILE_H9 = 231 SC_P3_HIZ_QUAD_PER_TILE_H10 = 232 SC_P3_HIZ_QUAD_PER_TILE_H11 = 233 SC_P3_HIZ_QUAD_PER_TILE_H12 = 234 SC_P3_HIZ_QUAD_PER_TILE_H13 = 235 SC_P3_HIZ_QUAD_PER_TILE_H14 = 236 SC_P3_HIZ_QUAD_PER_TILE_H15 = 237 SC_P3_HIZ_QUAD_PER_TILE_H16 = 238 SC_P0_HIZ_QUAD_COUNT = 239 SC_P1_HIZ_QUAD_COUNT = 240 SC_P2_HIZ_QUAD_COUNT = 241 SC_P3_HIZ_QUAD_COUNT = 242 SC_P0_DETAIL_QUAD_COUNT = 243 SC_P1_DETAIL_QUAD_COUNT = 244 SC_P2_DETAIL_QUAD_COUNT = 245 SC_P3_DETAIL_QUAD_COUNT = 246 SC_P0_DETAIL_QUAD_WITH_1_PIX = 247 SC_P0_DETAIL_QUAD_WITH_2_PIX = 248 SC_P0_DETAIL_QUAD_WITH_3_PIX = 249 SC_P0_DETAIL_QUAD_WITH_4_PIX = 250 SC_P1_DETAIL_QUAD_WITH_1_PIX = 251 SC_P1_DETAIL_QUAD_WITH_2_PIX = 252 SC_P1_DETAIL_QUAD_WITH_3_PIX = 253 SC_P1_DETAIL_QUAD_WITH_4_PIX = 254 SC_P2_DETAIL_QUAD_WITH_1_PIX = 255 SC_P2_DETAIL_QUAD_WITH_2_PIX = 256 SC_P2_DETAIL_QUAD_WITH_3_PIX = 257 SC_P2_DETAIL_QUAD_WITH_4_PIX = 258 SC_P3_DETAIL_QUAD_WITH_1_PIX = 259 SC_P3_DETAIL_QUAD_WITH_2_PIX = 260 SC_P3_DETAIL_QUAD_WITH_3_PIX = 261 SC_P3_DETAIL_QUAD_WITH_4_PIX = 262 SC_EARLYZ_QUAD_COUNT = 263 SC_EARLYZ_QUAD_WITH_1_PIX = 264 SC_EARLYZ_QUAD_WITH_2_PIX = 265 SC_EARLYZ_QUAD_WITH_3_PIX = 266 SC_EARLYZ_QUAD_WITH_4_PIX = 267 SC_PKR_QUAD_PER_ROW_H1 = 268 SC_PKR_QUAD_PER_ROW_H2 = 269 SC_PKR_4X2_QUAD_SPLIT = 270 SC_PKR_4X2_FILL_QUAD = 271 SC_PKR_END_OF_VECTOR = 272 SC_PKR_CONTROL_XFER = 273 SC_PKR_DBHANG_FORCE_EOV = 274 SC_REG_SCLK_BUSY = 275 SC_GRP0_DYN_SCLK_BUSY = 276 SC_GRP1_DYN_SCLK_BUSY = 277 SC_GRP2_DYN_SCLK_BUSY = 278 SC_GRP3_DYN_SCLK_BUSY = 279 SC_GRP4_DYN_SCLK_BUSY = 280 SC_PA0_SC_DATA_FIFO_RD = 281 SC_PA0_SC_DATA_FIFO_WE = 282 SC_PA1_SC_DATA_FIFO_RD = 283 SC_PA1_SC_DATA_FIFO_WE = 284 SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 285 SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 286 SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 287 SC_PS_ARB_STALLED_FROM_BELOW = 288 SC_PS_ARB_STARVED_FROM_ABOVE = 289 SC_PS_ARB_SC_BUSY = 290 SC_PS_ARB_PA_SC_BUSY = 291 SC_PA2_SC_DATA_FIFO_RD = 292 SC_PA2_SC_DATA_FIFO_WE = 293 SC_PA3_SC_DATA_FIFO_RD = 294 SC_PA3_SC_DATA_FIFO_WE = 295 SC_PA_SC_DEALLOC_0_0_WE = 296 SC_PA_SC_DEALLOC_0_1_WE = 297 SC_PA_SC_DEALLOC_1_0_WE = 298 SC_PA_SC_DEALLOC_1_1_WE = 299 SC_PA_SC_DEALLOC_2_0_WE = 300 SC_PA_SC_DEALLOC_2_1_WE = 301 SC_PA_SC_DEALLOC_3_0_WE = 302 SC_PA_SC_DEALLOC_3_1_WE = 303 SC_PA0_SC_EOP_WE = 304 SC_PA0_SC_EOPG_WE = 305 SC_PA0_SC_EVENT_WE = 306 SC_PA1_SC_EOP_WE = 307 SC_PA1_SC_EOPG_WE = 308 SC_PA1_SC_EVENT_WE = 309 SC_PA2_SC_EOP_WE = 310 SC_PA2_SC_EOPG_WE = 311 SC_PA2_SC_EVENT_WE = 312 SC_PA3_SC_EOP_WE = 313 SC_PA3_SC_EOPG_WE = 314 SC_PA3_SC_EVENT_WE = 315 SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 316 SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 317 SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 318 SC_PS_ARB_EOP_POP_SYNC_POP = 319 SC_PS_ARB_EVENT_SYNC_POP = 320 SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 321 SC_PA0_SC_FPOV_WE = 322 SC_PA1_SC_FPOV_WE = 323 SC_PA2_SC_FPOV_WE = 324 SC_PA3_SC_FPOV_WE = 325 SC_PA0_SC_LPOV_WE = 326 SC_PA1_SC_LPOV_WE = 327 SC_PA2_SC_LPOV_WE = 328 SC_PA3_SC_LPOV_WE = 329 SC_SC_SPI_DEALLOC_0_0 = 330 SC_SC_SPI_DEALLOC_0_1 = 331 SC_SC_SPI_DEALLOC_0_2 = 332 SC_SC_SPI_DEALLOC_1_0 = 333 SC_SC_SPI_DEALLOC_1_1 = 334 SC_SC_SPI_DEALLOC_1_2 = 335 SC_SC_SPI_DEALLOC_2_0 = 336 SC_SC_SPI_DEALLOC_2_1 = 337 SC_SC_SPI_DEALLOC_2_2 = 338 SC_SC_SPI_DEALLOC_3_0 = 339 SC_SC_SPI_DEALLOC_3_1 = 340 SC_SC_SPI_DEALLOC_3_2 = 341 SC_SC_SPI_FPOV_0 = 342 SC_SC_SPI_FPOV_1 = 343 SC_SC_SPI_FPOV_2 = 344 SC_SC_SPI_FPOV_3 = 345 SC_SC_SPI_EVENT = 346 SC_PS_TS_EVENT_FIFO_PUSH = 347 SC_PS_TS_EVENT_FIFO_POP = 348 SC_PS_CTX_DONE_FIFO_PUSH = 349 SC_PS_CTX_DONE_FIFO_POP = 350 SC_MULTICYCLE_BUBBLE_FREEZE = 351 SC_EOP_SYNC_WINDOW = 352 SC_PA0_SC_NULL_WE = 353 SC_PA0_SC_NULL_DEALLOC_WE = 354 SC_PA0_SC_DATA_FIFO_EOPG_RD = 355 SC_PA0_SC_DATA_FIFO_EOP_RD = 356 SC_PA0_SC_DEALLOC_0_RD = 357 SC_PA0_SC_DEALLOC_1_RD = 358 SC_PA1_SC_DATA_FIFO_EOPG_RD = 359 SC_PA1_SC_DATA_FIFO_EOP_RD = 360 SC_PA1_SC_DEALLOC_0_RD = 361 SC_PA1_SC_DEALLOC_1_RD = 362 SC_PA1_SC_NULL_WE = 363 SC_PA1_SC_NULL_DEALLOC_WE = 364 SC_PA2_SC_DATA_FIFO_EOPG_RD = 365 SC_PA2_SC_DATA_FIFO_EOP_RD = 366 SC_PA2_SC_DEALLOC_0_RD = 367 SC_PA2_SC_DEALLOC_1_RD = 368 SC_PA2_SC_NULL_WE = 369 SC_PA2_SC_NULL_DEALLOC_WE = 370 SC_PA3_SC_DATA_FIFO_EOPG_RD = 371 SC_PA3_SC_DATA_FIFO_EOP_RD = 372 SC_PA3_SC_DEALLOC_0_RD = 373 SC_PA3_SC_DEALLOC_1_RD = 374 SC_PA3_SC_NULL_WE = 375 SC_PA3_SC_NULL_DEALLOC_WE = 376 SC_PS_PA0_SC_FIFO_EMPTY = 377 SC_PS_PA0_SC_FIFO_FULL = 378 SC_PA0_PS_DATA_SEND = 379 SC_PS_PA1_SC_FIFO_EMPTY = 380 SC_PS_PA1_SC_FIFO_FULL = 381 SC_PA1_PS_DATA_SEND = 382 SC_PS_PA2_SC_FIFO_EMPTY = 383 SC_PS_PA2_SC_FIFO_FULL = 384 SC_PA2_PS_DATA_SEND = 385 SC_PS_PA3_SC_FIFO_EMPTY = 386 SC_PS_PA3_SC_FIFO_FULL = 387 SC_PA3_PS_DATA_SEND = 388 SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 389 SC_BUSY_CNT_NOT_ZERO = 390 SC_BM_BUSY = 391 SC_BACKEND_BUSY = 392 SC_SCF_SCB_INTERFACE_BUSY = 393 SC_SCB_BUSY = 394 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 395 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 396 SC_PBB_BIN_HIST_NUM_PRIMS = 397 SC_PBB_BATCH_HIST_NUM_PRIMS = 398 SC_PBB_BIN_HIST_NUM_CONTEXTS = 399 SC_PBB_BATCH_HIST_NUM_CONTEXTS = 400 SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 401 SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 402 SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 403 SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 404 SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 405 SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 406 SC_PBB_BUSY = 407 SC_PBB_BUSY_AND_RTR = 408 SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 409 SC_PBB_NUM_BINS = 410 SC_PBB_END_OF_BIN = 411 SC_PBB_END_OF_BATCH = 412 SC_PBB_PRIMBIN_PROCESSED = 413 SC_PBB_PRIM_ADDED_TO_BATCH = 414 SC_PBB_NONBINNED_PRIM = 415 SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 416 SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 417 SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 418 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 419 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 420 SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 421 SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 422 SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 423 SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 424 SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 425 SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 426 SC_POPS_INTRA_WAVE_OVERLAPS = 427 SC_POPS_FORCE_EOV = 428 SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE = 429 SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE = 430 SC_PERFCNT_SEL = ctypes.c_uint32 # enum # values for enumeration 'SePairXsel' SePairXsel__enumvalues = { 0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', 1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', 2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', 3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', 4: 'RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE', } RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0 RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1 RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2 RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3 RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE = 4 SePairXsel = ctypes.c_uint32 # enum # values for enumeration 'SePairYsel' SePairYsel__enumvalues = { 0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', 1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', 2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', 3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', 4: 'RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE', } RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0 RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1 RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2 RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3 RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE = 4 SePairYsel = ctypes.c_uint32 # enum # values for enumeration 'SePairMap' SePairMap__enumvalues = { 0: 'RASTER_CONFIG_SE_PAIR_MAP_0', 1: 'RASTER_CONFIG_SE_PAIR_MAP_1', 2: 'RASTER_CONFIG_SE_PAIR_MAP_2', 3: 'RASTER_CONFIG_SE_PAIR_MAP_3', } RASTER_CONFIG_SE_PAIR_MAP_0 = 0 RASTER_CONFIG_SE_PAIR_MAP_1 = 1 RASTER_CONFIG_SE_PAIR_MAP_2 = 2 RASTER_CONFIG_SE_PAIR_MAP_3 = 3 SePairMap = ctypes.c_uint32 # enum # values for enumeration 'SeXsel' SeXsel__enumvalues = { 0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', 1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', 2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', 3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', 4: 'RASTER_CONFIG_SE_XSEL_128_WIDE_TILE', } RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0 RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1 RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2 RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3 RASTER_CONFIG_SE_XSEL_128_WIDE_TILE = 4 SeXsel = ctypes.c_uint32 # enum # values for enumeration 'SeYsel' SeYsel__enumvalues = { 0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', 2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', 3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', 4: 'RASTER_CONFIG_SE_YSEL_128_WIDE_TILE', } RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0 RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1 RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2 RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3 RASTER_CONFIG_SE_YSEL_128_WIDE_TILE = 4 SeYsel = ctypes.c_uint32 # enum # values for enumeration 'SeMap' SeMap__enumvalues = { 0: 'RASTER_CONFIG_SE_MAP_0', 1: 'RASTER_CONFIG_SE_MAP_1', 2: 'RASTER_CONFIG_SE_MAP_2', 3: 'RASTER_CONFIG_SE_MAP_3', } RASTER_CONFIG_SE_MAP_0 = 0 RASTER_CONFIG_SE_MAP_1 = 1 RASTER_CONFIG_SE_MAP_2 = 2 RASTER_CONFIG_SE_MAP_3 = 3 SeMap = ctypes.c_uint32 # enum # values for enumeration 'ScXsel' ScXsel__enumvalues = { 0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', 1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', 2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', 3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', } RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0 RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1 RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2 RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3 ScXsel = ctypes.c_uint32 # enum # values for enumeration 'ScYsel' ScYsel__enumvalues = { 0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', 2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', 3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', } RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0 RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1 RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2 RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3 ScYsel = ctypes.c_uint32 # enum # values for enumeration 'ScMap' ScMap__enumvalues = { 0: 'RASTER_CONFIG_SC_MAP_0', 1: 'RASTER_CONFIG_SC_MAP_1', 2: 'RASTER_CONFIG_SC_MAP_2', 3: 'RASTER_CONFIG_SC_MAP_3', } RASTER_CONFIG_SC_MAP_0 = 0 RASTER_CONFIG_SC_MAP_1 = 1 RASTER_CONFIG_SC_MAP_2 = 2 RASTER_CONFIG_SC_MAP_3 = 3 ScMap = ctypes.c_uint32 # enum # values for enumeration 'PkrXsel2' PkrXsel2__enumvalues = { 0: 'RASTER_CONFIG_PKR_XSEL2_0', 1: 'RASTER_CONFIG_PKR_XSEL2_1', 2: 'RASTER_CONFIG_PKR_XSEL2_2', 3: 'RASTER_CONFIG_PKR_XSEL2_3', } RASTER_CONFIG_PKR_XSEL2_0 = 0 RASTER_CONFIG_PKR_XSEL2_1 = 1 RASTER_CONFIG_PKR_XSEL2_2 = 2 RASTER_CONFIG_PKR_XSEL2_3 = 3 PkrXsel2 = ctypes.c_uint32 # enum # values for enumeration 'PkrXsel' PkrXsel__enumvalues = { 0: 'RASTER_CONFIG_PKR_XSEL_0', 1: 'RASTER_CONFIG_PKR_XSEL_1', 2: 'RASTER_CONFIG_PKR_XSEL_2', 3: 'RASTER_CONFIG_PKR_XSEL_3', } RASTER_CONFIG_PKR_XSEL_0 = 0 RASTER_CONFIG_PKR_XSEL_1 = 1 RASTER_CONFIG_PKR_XSEL_2 = 2 RASTER_CONFIG_PKR_XSEL_3 = 3 PkrXsel = ctypes.c_uint32 # enum # values for enumeration 'PkrYsel' PkrYsel__enumvalues = { 0: 'RASTER_CONFIG_PKR_YSEL_0', 1: 'RASTER_CONFIG_PKR_YSEL_1', 2: 'RASTER_CONFIG_PKR_YSEL_2', 3: 'RASTER_CONFIG_PKR_YSEL_3', } RASTER_CONFIG_PKR_YSEL_0 = 0 RASTER_CONFIG_PKR_YSEL_1 = 1 RASTER_CONFIG_PKR_YSEL_2 = 2 RASTER_CONFIG_PKR_YSEL_3 = 3 PkrYsel = ctypes.c_uint32 # enum # values for enumeration 'PkrMap' PkrMap__enumvalues = { 0: 'RASTER_CONFIG_PKR_MAP_0', 1: 'RASTER_CONFIG_PKR_MAP_1', 2: 'RASTER_CONFIG_PKR_MAP_2', 3: 'RASTER_CONFIG_PKR_MAP_3', } RASTER_CONFIG_PKR_MAP_0 = 0 RASTER_CONFIG_PKR_MAP_1 = 1 RASTER_CONFIG_PKR_MAP_2 = 2 RASTER_CONFIG_PKR_MAP_3 = 3 PkrMap = ctypes.c_uint32 # enum # values for enumeration 'RbXsel' RbXsel__enumvalues = { 0: 'RASTER_CONFIG_RB_XSEL_0', 1: 'RASTER_CONFIG_RB_XSEL_1', } RASTER_CONFIG_RB_XSEL_0 = 0 RASTER_CONFIG_RB_XSEL_1 = 1 RbXsel = ctypes.c_uint32 # enum # values for enumeration 'RbYsel' RbYsel__enumvalues = { 0: 'RASTER_CONFIG_RB_YSEL_0', 1: 'RASTER_CONFIG_RB_YSEL_1', } RASTER_CONFIG_RB_YSEL_0 = 0 RASTER_CONFIG_RB_YSEL_1 = 1 RbYsel = ctypes.c_uint32 # enum # values for enumeration 'RbXsel2' RbXsel2__enumvalues = { 0: 'RASTER_CONFIG_RB_XSEL2_0', 1: 'RASTER_CONFIG_RB_XSEL2_1', 2: 'RASTER_CONFIG_RB_XSEL2_2', 3: 'RASTER_CONFIG_RB_XSEL2_3', } RASTER_CONFIG_RB_XSEL2_0 = 0 RASTER_CONFIG_RB_XSEL2_1 = 1 RASTER_CONFIG_RB_XSEL2_2 = 2 RASTER_CONFIG_RB_XSEL2_3 = 3 RbXsel2 = ctypes.c_uint32 # enum # values for enumeration 'RbMap' RbMap__enumvalues = { 0: 'RASTER_CONFIG_RB_MAP_0', 1: 'RASTER_CONFIG_RB_MAP_1', 2: 'RASTER_CONFIG_RB_MAP_2', 3: 'RASTER_CONFIG_RB_MAP_3', } RASTER_CONFIG_RB_MAP_0 = 0 RASTER_CONFIG_RB_MAP_1 = 1 RASTER_CONFIG_RB_MAP_2 = 2 RASTER_CONFIG_RB_MAP_3 = 3 RbMap = ctypes.c_uint32 # enum # values for enumeration 'BinningMode' BinningMode__enumvalues = { 0: 'BINNING_ALLOWED', 1: 'FORCE_BINNING_ON', 2: 'DISABLE_BINNING_USE_NEW_SC', 3: 'DISABLE_BINNING_USE_LEGACY_SC', } BINNING_ALLOWED = 0 FORCE_BINNING_ON = 1 DISABLE_BINNING_USE_NEW_SC = 2 DISABLE_BINNING_USE_LEGACY_SC = 3 BinningMode = ctypes.c_uint32 # enum # values for enumeration 'BinEventCntl' BinEventCntl__enumvalues = { 0: 'BINNER_BREAK_BATCH', 1: 'BINNER_PIPELINE', 2: 'BINNER_DROP_ASSERT', } BINNER_BREAK_BATCH = 0 BINNER_PIPELINE = 1 BINNER_DROP_ASSERT = 2 BinEventCntl = ctypes.c_uint32 # enum # values for enumeration 'CovToShaderSel' CovToShaderSel__enumvalues = { 0: 'INPUT_COVERAGE', 1: 'INPUT_INNER_COVERAGE', 2: 'INPUT_DEPTH_COVERAGE', 3: 'RAW', } INPUT_COVERAGE = 0 INPUT_INNER_COVERAGE = 1 INPUT_DEPTH_COVERAGE = 2 RAW = 3 CovToShaderSel = ctypes.c_uint32 # enum # values for enumeration 'RMIPerfSel' RMIPerfSel__enumvalues = { 0: 'RMI_PERF_SEL_NONE', 1: 'RMI_PERF_SEL_BUSY', 2: 'RMI_PERF_SEL_REG_CLK_VLD', 3: 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', 4: 'RMI_PERF_SEL_DYN_CLK_RB_VLD', 5: 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', 6: 'RMI_PERF_SEL_PERF_WINDOW', 7: 'RMI_PERF_SEL_EVENT_SEND', 8: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0', 9: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1', 10: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2', 11: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3', 12: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4', 13: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5', 14: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6', 15: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7', 16: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8', 17: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9', 18: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10', 19: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11', 20: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12', 21: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13', 22: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14', 23: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15', 24: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL', 25: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0', 26: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1', 27: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2', 28: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3', 29: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4', 30: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5', 31: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6', 32: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7', 33: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8', 34: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9', 35: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10', 36: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11', 37: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12', 38: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13', 39: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14', 40: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15', 41: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL', 42: 'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS', 43: 'RMI_PERF_SEL_UTCL1_PERMISSION_MISS', 44: 'RMI_PERF_SEL_UTCL1_REQUEST', 45: 'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', 46: 'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', 47: 'RMI_PERF_SEL_UTCL1_LFIFO_FULL', 48: 'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', 49: 'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', 50: 'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', 51: 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL', 52: 'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS', 53: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', 54: 'RMI_PERF_SEL_RB_RMI_WRREQ_BUSY', 55: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', 56: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', 57: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', 58: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', 59: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', 60: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', 61: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', 62: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', 63: 'RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID', 64: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', 65: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', 66: 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', 67: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', 68: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', 69: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', 70: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', 71: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', 72: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', 73: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', 74: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', 75: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', 76: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', 77: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', 78: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', 79: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', 80: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', 81: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', 82: 'RMI_PERF_SEL_RB_RMI_RDREQ_BUSY', 83: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', 84: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', 85: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', 86: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', 87: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', 88: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', 89: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', 90: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', 91: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', 92: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', 93: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', 94: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', 95: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', 96: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', 97: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', 98: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', 99: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', 100: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', 101: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', 102: 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', 103: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', 104: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', 105: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', 106: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', 107: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', 108: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', 109: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', 110: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', 111: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', 112: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', 113: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', 114: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', 115: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', 116: 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', 117: 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', 118: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', 119: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', 120: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', 121: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', 122: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', 123: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', 124: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', 125: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', 126: 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', 127: 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', 128: 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', 129: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', 130: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', 131: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', 132: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', 133: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', 134: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', 135: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', 136: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', 137: 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', 138: 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', 139: 'RMI_PERF_SEL_UTCL1_BUSY', 140: 'RMI_PERF_SEL_RMI_UTC_REQ', 141: 'RMI_PERF_SEL_RMI_UTC_BUSY', 142: 'RMI_PERF_SEL_UTCL1_UTCL2_REQ', 143: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY', 144: 'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT', 145: 'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT', 146: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT', 147: 'RMI_PERF_SEL_XNACK_FIFO_NUM_USED', 148: 'RMI_PERF_SEL_LAT_FIFO_NUM_USED', 149: 'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ', 150: 'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ', 151: 'RMI_PERF_SEL_XNACK_FIFO_FULL', 152: 'RMI_PERF_SEL_XNACK_FIFO_BUSY', 153: 'RMI_PERF_SEL_LAT_FIFO_FULL', 154: 'RMI_PERF_SEL_SKID_FIFO_DEPTH', 155: 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', 156: 'RMI_PERF_SEL_PRT_FIFO_NUM_USED', 157: 'RMI_PERF_SEL_PRT_FIFO_REQ', 158: 'RMI_PERF_SEL_PRT_FIFO_BUSY', 159: 'RMI_PERF_SEL_TCIW_REQ', 160: 'RMI_PERF_SEL_TCIW_BUSY', 161: 'RMI_PERF_SEL_SKID_FIFO_REQ', 162: 'RMI_PERF_SEL_SKID_FIFO_BUSY', 163: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0', 164: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1', 165: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2', 166: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3', 167: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR', 168: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR', 169: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB', 170: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB', 171: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', 172: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', 173: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', 174: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', 175: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR', 176: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR', 177: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB', 178: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB', 179: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR', 180: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR', 181: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB', 182: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB', 183: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTR', 184: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR', 185: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB', 186: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB', 187: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR', 188: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR', 189: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB', 190: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB', 191: 'RMI_PERF_SEL_UTC_POP_RTS_RTR', 192: 'RMI_PERF_SEL_UTC_POP_RTSB_RTR', 193: 'RMI_PERF_SEL_UTC_POP_RTS_RTRB', 194: 'RMI_PERF_SEL_UTC_POP_RTSB_RTRB', 195: 'RMI_PERF_SEL_POP_XNACK_RTS_RTR', 196: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTR', 197: 'RMI_PERF_SEL_POP_XNACK_RTS_RTRB', 198: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB', 199: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR', 200: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR', 201: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB', 202: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB', 203: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR', 204: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR', 205: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB', 206: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB', 207: 'RMI_PERF_SEL_SKID_FIFO_IN_RTS', 208: 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB', 209: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTS', 210: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB', 211: 'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR', 212: 'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR', 213: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR', 214: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR', 215: 'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR', 216: 'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR', 217: 'RMI_PERF_SEL_REORDER_FIFO_REQ', 218: 'RMI_PERF_SEL_REORDER_FIFO_BUSY', 219: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', 220: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', 221: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', 222: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', 223: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', 224: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', 225: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', 226: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', 227: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', 228: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0', 229: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1', 230: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2', 231: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3', } RMI_PERF_SEL_NONE = 0 RMI_PERF_SEL_BUSY = 1 RMI_PERF_SEL_REG_CLK_VLD = 2 RMI_PERF_SEL_DYN_CLK_CMN_VLD = 3 RMI_PERF_SEL_DYN_CLK_RB_VLD = 4 RMI_PERF_SEL_DYN_CLK_PERF_VLD = 5 RMI_PERF_SEL_PERF_WINDOW = 6 RMI_PERF_SEL_EVENT_SEND = 7 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 8 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 9 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 10 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 11 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 12 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 13 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 14 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 15 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 16 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 17 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 18 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 19 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 20 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 21 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 22 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 23 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 24 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 25 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 26 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 27 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 28 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 29 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 30 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 31 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 32 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 33 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 34 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 35 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 36 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 37 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 38 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 39 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 40 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 41 RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 42 RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 43 RMI_PERF_SEL_UTCL1_REQUEST = 44 RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 45 RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 46 RMI_PERF_SEL_UTCL1_LFIFO_FULL = 47 RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 48 RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 49 RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 50 RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 51 RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 52 RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 53 RMI_PERF_SEL_RB_RMI_WRREQ_BUSY = 54 RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 55 RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 56 RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 57 RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 58 RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 59 RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 60 RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 61 RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 62 RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID = 63 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 64 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 65 RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 66 RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 67 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 68 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 69 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 70 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 71 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 72 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 73 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 74 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 75 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 76 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 77 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 78 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 79 RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 80 RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 81 RMI_PERF_SEL_RB_RMI_RDREQ_BUSY = 82 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 83 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 84 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 85 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 86 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 87 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 88 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 89 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 90 RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 91 RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 92 RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 93 RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 94 RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 95 RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 96 RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 97 RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 98 RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 99 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 100 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 101 RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 102 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 103 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 104 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 105 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 106 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 107 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 108 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 109 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 110 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 111 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 112 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 113 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 114 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 115 RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 116 RMI_PERF_SEL_RMI_TC_REQ_BUSY = 117 RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 118 RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 119 RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 120 RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 121 RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 122 RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 123 RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 124 RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 125 RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 126 RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 127 RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 128 RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 129 RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 130 RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 131 RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 132 RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 133 RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 134 RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 135 RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 136 RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 137 RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 138 RMI_PERF_SEL_UTCL1_BUSY = 139 RMI_PERF_SEL_RMI_UTC_REQ = 140 RMI_PERF_SEL_RMI_UTC_BUSY = 141 RMI_PERF_SEL_UTCL1_UTCL2_REQ = 142 RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 143 RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 144 RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 145 RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 146 RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 147 RMI_PERF_SEL_LAT_FIFO_NUM_USED = 148 RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 149 RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 150 RMI_PERF_SEL_XNACK_FIFO_FULL = 151 RMI_PERF_SEL_XNACK_FIFO_BUSY = 152 RMI_PERF_SEL_LAT_FIFO_FULL = 153 RMI_PERF_SEL_SKID_FIFO_DEPTH = 154 RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 155 RMI_PERF_SEL_PRT_FIFO_NUM_USED = 156 RMI_PERF_SEL_PRT_FIFO_REQ = 157 RMI_PERF_SEL_PRT_FIFO_BUSY = 158 RMI_PERF_SEL_TCIW_REQ = 159 RMI_PERF_SEL_TCIW_BUSY = 160 RMI_PERF_SEL_SKID_FIFO_REQ = 161 RMI_PERF_SEL_SKID_FIFO_BUSY = 162 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 163 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 164 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 165 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 166 RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 167 RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 168 RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 169 RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 170 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 171 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 172 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 173 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 174 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 175 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 176 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 177 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 178 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 179 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 180 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 181 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 182 RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 183 RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 184 RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 185 RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 186 RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 187 RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 188 RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 189 RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 190 RMI_PERF_SEL_UTC_POP_RTS_RTR = 191 RMI_PERF_SEL_UTC_POP_RTSB_RTR = 192 RMI_PERF_SEL_UTC_POP_RTS_RTRB = 193 RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 194 RMI_PERF_SEL_POP_XNACK_RTS_RTR = 195 RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 196 RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 197 RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 198 RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 199 RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 200 RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 201 RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 202 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 203 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 204 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 205 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 206 RMI_PERF_SEL_SKID_FIFO_IN_RTS = 207 RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 208 RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 209 RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 210 RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 211 RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 212 RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 213 RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 214 RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 215 RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 216 RMI_PERF_SEL_REORDER_FIFO_REQ = 217 RMI_PERF_SEL_REORDER_FIFO_BUSY = 218 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 219 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 220 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 221 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 222 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 223 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 224 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 225 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 226 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 227 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 228 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 229 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 230 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 231 RMIPerfSel = ctypes.c_uint32 # enum # values for enumeration 'IH_PERF_SEL' IH_PERF_SEL__enumvalues = { 0: 'IH_PERF_SEL_CYCLE', 1: 'IH_PERF_SEL_IDLE', 2: 'IH_PERF_SEL_INPUT_IDLE', 3: 'IH_PERF_SEL_BUFFER_IDLE', 4: 'IH_PERF_SEL_RB0_FULL', 5: 'IH_PERF_SEL_RB0_OVERFLOW', 6: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', 7: 'IH_PERF_SEL_RB0_WPTR_WRAP', 8: 'IH_PERF_SEL_RB0_RPTR_WRAP', 9: 'IH_PERF_SEL_MC_WR_IDLE', 10: 'IH_PERF_SEL_MC_WR_COUNT', 11: 'IH_PERF_SEL_MC_WR_STALL', 12: 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', 13: 'IH_PERF_SEL_MC_WR_CLEAN_STALL', 14: 'IH_PERF_SEL_BIF_LINE0_RISING', 15: 'IH_PERF_SEL_BIF_LINE0_FALLING', 16: 'IH_PERF_SEL_RB1_FULL', 17: 'IH_PERF_SEL_RB1_OVERFLOW', 18: 'Reserved18', 19: 'IH_PERF_SEL_RB1_WPTR_WRAP', 20: 'IH_PERF_SEL_RB1_RPTR_WRAP', 21: 'IH_PERF_SEL_RB2_FULL', 22: 'IH_PERF_SEL_RB2_OVERFLOW', 23: 'Reserved23', 24: 'IH_PERF_SEL_RB2_WPTR_WRAP', 25: 'IH_PERF_SEL_RB2_RPTR_WRAP', 26: 'Reserved26', 27: 'Reserved27', 28: 'Reserved28', 29: 'Reserved29', 30: 'IH_PERF_SEL_RB0_FULL_VF0', 31: 'IH_PERF_SEL_RB0_FULL_VF1', 32: 'IH_PERF_SEL_RB0_FULL_VF2', 33: 'IH_PERF_SEL_RB0_FULL_VF3', 34: 'IH_PERF_SEL_RB0_FULL_VF4', 35: 'IH_PERF_SEL_RB0_FULL_VF5', 36: 'IH_PERF_SEL_RB0_FULL_VF6', 37: 'IH_PERF_SEL_RB0_FULL_VF7', 38: 'IH_PERF_SEL_RB0_FULL_VF8', 39: 'IH_PERF_SEL_RB0_FULL_VF9', 40: 'IH_PERF_SEL_RB0_FULL_VF10', 41: 'IH_PERF_SEL_RB0_FULL_VF11', 42: 'IH_PERF_SEL_RB0_FULL_VF12', 43: 'IH_PERF_SEL_RB0_FULL_VF13', 44: 'IH_PERF_SEL_RB0_FULL_VF14', 45: 'IH_PERF_SEL_RB0_FULL_VF15', 46: 'IH_PERF_SEL_RB0_OVERFLOW_VF0', 47: 'IH_PERF_SEL_RB0_OVERFLOW_VF1', 48: 'IH_PERF_SEL_RB0_OVERFLOW_VF2', 49: 'IH_PERF_SEL_RB0_OVERFLOW_VF3', 50: 'IH_PERF_SEL_RB0_OVERFLOW_VF4', 51: 'IH_PERF_SEL_RB0_OVERFLOW_VF5', 52: 'IH_PERF_SEL_RB0_OVERFLOW_VF6', 53: 'IH_PERF_SEL_RB0_OVERFLOW_VF7', 54: 'IH_PERF_SEL_RB0_OVERFLOW_VF8', 55: 'IH_PERF_SEL_RB0_OVERFLOW_VF9', 56: 'IH_PERF_SEL_RB0_OVERFLOW_VF10', 57: 'IH_PERF_SEL_RB0_OVERFLOW_VF11', 58: 'IH_PERF_SEL_RB0_OVERFLOW_VF12', 59: 'IH_PERF_SEL_RB0_OVERFLOW_VF13', 60: 'IH_PERF_SEL_RB0_OVERFLOW_VF14', 61: 'IH_PERF_SEL_RB0_OVERFLOW_VF15', 62: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', 63: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', 64: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', 65: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', 66: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', 67: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', 68: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', 69: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', 70: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', 71: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 72: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', 73: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', 74: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', 75: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', 76: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', 77: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', 78: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 79: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', 80: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', 81: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', 82: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', 83: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 84: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', 85: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 86: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', 87: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 88: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', 89: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', 90: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', 91: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', 92: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', 93: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', 94: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', 95: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', 96: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', 97: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', 98: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', 99: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 100: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', 101: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 102: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', 103: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 104: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', 105: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', 106: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', 107: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', 108: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', 109: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', 110: 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', 111: 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', 112: 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', 113: 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', 114: 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', 115: 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', 116: 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', 117: 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', 118: 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', 119: 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', 120: 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', 121: 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', 122: 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', 123: 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', 124: 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', 125: 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', 126: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', 127: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', 128: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', 129: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', 130: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', 131: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', 132: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', 133: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', 134: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', 135: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', 136: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', 137: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', 138: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', 139: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', 140: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', 141: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', 142: 'Reserved142', 143: 'Reserved143', 144: 'Reserved144', 145: 'Reserved145', 146: 'Reserved146', 147: 'Reserved147', 148: 'Reserved148', 149: 'Reserved149', 150: 'IH_PERF_SEL_CLIENT0_INT', 151: 'IH_PERF_SEL_CLIENT1_INT', 152: 'IH_PERF_SEL_CLIENT2_INT', 153: 'IH_PERF_SEL_CLIENT3_INT', 154: 'IH_PERF_SEL_CLIENT4_INT', 155: 'IH_PERF_SEL_CLIENT5_INT', 156: 'IH_PERF_SEL_CLIENT6_INT', 157: 'IH_PERF_SEL_CLIENT7_INT', 158: 'IH_PERF_SEL_CLIENT8_INT', 159: 'IH_PERF_SEL_CLIENT9_INT', 160: 'IH_PERF_SEL_CLIENT10_INT', 161: 'IH_PERF_SEL_CLIENT11_INT', 162: 'IH_PERF_SEL_CLIENT12_INT', 163: 'IH_PERF_SEL_CLIENT13_INT', 164: 'IH_PERF_SEL_CLIENT14_INT', 165: 'IH_PERF_SEL_CLIENT15_INT', 166: 'IH_PERF_SEL_CLIENT16_INT', 167: 'IH_PERF_SEL_CLIENT17_INT', 168: 'IH_PERF_SEL_CLIENT18_INT', 169: 'IH_PERF_SEL_CLIENT19_INT', 170: 'IH_PERF_SEL_CLIENT20_INT', 171: 'IH_PERF_SEL_CLIENT21_INT', 172: 'IH_PERF_SEL_CLIENT22_INT', 173: 'IH_PERF_SEL_CLIENT23_INT', 174: 'IH_PERF_SEL_CLIENT24_INT', 175: 'IH_PERF_SEL_CLIENT25_INT', 176: 'IH_PERF_SEL_CLIENT26_INT', 177: 'IH_PERF_SEL_CLIENT27_INT', 178: 'IH_PERF_SEL_CLIENT28_INT', 179: 'IH_PERF_SEL_CLIENT29_INT', 180: 'IH_PERF_SEL_CLIENT30_INT', 181: 'IH_PERF_SEL_CLIENT31_INT', 182: 'Reserved182', 183: 'Reserved183', 184: 'Reserved184', 185: 'Reserved185', 186: 'Reserved186', 187: 'Reserved187', 188: 'Reserved188', 189: 'Reserved189', 190: 'Reserved190', 191: 'Reserved191', 192: 'Reserved192', 193: 'Reserved193', 194: 'Reserved194', 195: 'Reserved195', 196: 'Reserved196', 197: 'Reserved197', 198: 'Reserved198', 199: 'Reserved199', 200: 'Reserved200', 201: 'Reserved201', 202: 'Reserved202', 203: 'Reserved203', 204: 'Reserved204', 205: 'Reserved205', 206: 'Reserved206', 207: 'Reserved207', 208: 'Reserved208', 209: 'Reserved209', 210: 'Reserved210', 211: 'Reserved211', 212: 'Reserved212', 213: 'Reserved213', 214: 'Reserved214', 215: 'Reserved215', 216: 'Reserved216', 217: 'Reserved217', 218: 'Reserved218', 219: 'Reserved219', 220: 'IH_PERF_SEL_RB1_FULL_VF0', 221: 'IH_PERF_SEL_RB1_FULL_VF1', 222: 'IH_PERF_SEL_RB1_FULL_VF2', 223: 'IH_PERF_SEL_RB1_FULL_VF3', 224: 'IH_PERF_SEL_RB1_FULL_VF4', 225: 'IH_PERF_SEL_RB1_FULL_VF5', 226: 'IH_PERF_SEL_RB1_FULL_VF6', 227: 'IH_PERF_SEL_RB1_FULL_VF7', 228: 'IH_PERF_SEL_RB1_FULL_VF8', 229: 'IH_PERF_SEL_RB1_FULL_VF9', 230: 'IH_PERF_SEL_RB1_FULL_VF10', 231: 'IH_PERF_SEL_RB1_FULL_VF11', 232: 'IH_PERF_SEL_RB1_FULL_VF12', 233: 'IH_PERF_SEL_RB1_FULL_VF13', 234: 'IH_PERF_SEL_RB1_FULL_VF14', 235: 'IH_PERF_SEL_RB1_FULL_VF15', 236: 'IH_PERF_SEL_RB1_OVERFLOW_VF0', 237: 'IH_PERF_SEL_RB1_OVERFLOW_VF1', 238: 'IH_PERF_SEL_RB1_OVERFLOW_VF2', 239: 'IH_PERF_SEL_RB1_OVERFLOW_VF3', 240: 'IH_PERF_SEL_RB1_OVERFLOW_VF4', 241: 'IH_PERF_SEL_RB1_OVERFLOW_VF5', 242: 'IH_PERF_SEL_RB1_OVERFLOW_VF6', 243: 'IH_PERF_SEL_RB1_OVERFLOW_VF7', 244: 'IH_PERF_SEL_RB1_OVERFLOW_VF8', 245: 'IH_PERF_SEL_RB1_OVERFLOW_VF9', 246: 'IH_PERF_SEL_RB1_OVERFLOW_VF10', 247: 'IH_PERF_SEL_RB1_OVERFLOW_VF11', 248: 'IH_PERF_SEL_RB1_OVERFLOW_VF12', 249: 'IH_PERF_SEL_RB1_OVERFLOW_VF13', 250: 'IH_PERF_SEL_RB1_OVERFLOW_VF14', 251: 'IH_PERF_SEL_RB1_OVERFLOW_VF15', 252: 'Reserved252', 253: 'Reserved253', 254: 'Reserved254', 255: 'Reserved255', 256: 'Reserved256', 257: 'Reserved257', 258: 'Reserved258', 259: 'Reserved259', 260: 'Reserved260', 261: 'Reserved261', 262: 'Reserved262', 263: 'Reserved263', 264: 'Reserved264', 265: 'Reserved265', 266: 'Reserved266', 267: 'Reserved267', 268: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 269: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', 270: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', 271: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', 272: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', 273: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 274: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', 275: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 276: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', 277: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 278: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', 279: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', 280: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', 281: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', 282: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', 283: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', 284: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', 285: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', 286: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', 287: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', 288: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', 289: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 290: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', 291: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 292: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', 293: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 294: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', 295: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', 296: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', 297: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', 298: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', 299: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', 300: 'Reserved300', 301: 'Reserved301', 302: 'Reserved302', 303: 'Reserved303', 304: 'Reserved304', 305: 'Reserved305', 306: 'Reserved306', 307: 'Reserved307', 308: 'Reserved308', 309: 'Reserved309', 310: 'Reserved310', 311: 'Reserved311', 312: 'Reserved312', 313: 'Reserved313', 314: 'Reserved314', 315: 'Reserved315', 316: 'Reserved316', 317: 'Reserved317', 318: 'Reserved318', 319: 'Reserved319', 320: 'Reserved320', 321: 'Reserved321', 322: 'Reserved322', 323: 'Reserved323', 324: 'Reserved324', 325: 'Reserved325', 326: 'Reserved326', 327: 'Reserved327', 328: 'Reserved328', 329: 'Reserved329', 330: 'Reserved330', 331: 'Reserved331', 332: 'IH_PERF_SEL_RB2_FULL_VF0', 333: 'IH_PERF_SEL_RB2_FULL_VF1', 334: 'IH_PERF_SEL_RB2_FULL_VF2', 335: 'IH_PERF_SEL_RB2_FULL_VF3', 336: 'IH_PERF_SEL_RB2_FULL_VF4', 337: 'IH_PERF_SEL_RB2_FULL_VF5', 338: 'IH_PERF_SEL_RB2_FULL_VF6', 339: 'IH_PERF_SEL_RB2_FULL_VF7', 340: 'IH_PERF_SEL_RB2_FULL_VF8', 341: 'IH_PERF_SEL_RB2_FULL_VF9', 342: 'IH_PERF_SEL_RB2_FULL_VF10', 343: 'IH_PERF_SEL_RB2_FULL_VF11', 344: 'IH_PERF_SEL_RB2_FULL_VF12', 345: 'IH_PERF_SEL_RB2_FULL_VF13', 346: 'IH_PERF_SEL_RB2_FULL_VF14', 347: 'IH_PERF_SEL_RB2_FULL_VF15', 348: 'IH_PERF_SEL_RB2_OVERFLOW_VF0', 349: 'IH_PERF_SEL_RB2_OVERFLOW_VF1', 350: 'IH_PERF_SEL_RB2_OVERFLOW_VF2', 351: 'IH_PERF_SEL_RB2_OVERFLOW_VF3', 352: 'IH_PERF_SEL_RB2_OVERFLOW_VF4', 353: 'IH_PERF_SEL_RB2_OVERFLOW_VF5', 354: 'IH_PERF_SEL_RB2_OVERFLOW_VF6', 355: 'IH_PERF_SEL_RB2_OVERFLOW_VF7', 356: 'IH_PERF_SEL_RB2_OVERFLOW_VF8', 357: 'IH_PERF_SEL_RB2_OVERFLOW_VF9', 358: 'IH_PERF_SEL_RB2_OVERFLOW_VF10', 359: 'IH_PERF_SEL_RB2_OVERFLOW_VF11', 360: 'IH_PERF_SEL_RB2_OVERFLOW_VF12', 361: 'IH_PERF_SEL_RB2_OVERFLOW_VF13', 362: 'IH_PERF_SEL_RB2_OVERFLOW_VF14', 363: 'IH_PERF_SEL_RB2_OVERFLOW_VF15', 364: 'Reserved364', 365: 'Reserved365', 366: 'Reserved366', 367: 'Reserved367', 368: 'Reserved368', 369: 'Reserved369', 370: 'Reserved370', 371: 'Reserved371', 372: 'Reserved372', 373: 'Reserved373', 374: 'Reserved374', 375: 'Reserved375', 376: 'Reserved376', 377: 'Reserved377', 378: 'Reserved378', 379: 'Reserved379', 380: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 381: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', 382: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', 383: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', 384: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', 385: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 386: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', 387: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 388: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', 389: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 390: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', 391: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', 392: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', 393: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', 394: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', 395: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', 396: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', 397: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', 398: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', 399: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', 400: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', 401: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 402: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', 403: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 404: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', 405: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 406: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', 407: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', 408: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', 409: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', 410: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', 411: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', 412: 'Reserved412', 413: 'Reserved413', 414: 'Reserved414', 415: 'Reserved415', 416: 'Reserved416', 417: 'Reserved417', 418: 'Reserved418', 419: 'Reserved419', 420: 'Reserved420', 421: 'Reserved421', 422: 'Reserved422', 423: 'Reserved423', 424: 'Reserved424', 425: 'Reserved425', 426: 'Reserved426', 427: 'Reserved427', 428: 'Reserved428', 429: 'Reserved429', 430: 'Reserved430', 431: 'Reserved431', 432: 'Reserved432', 433: 'Reserved433', 434: 'Reserved434', 435: 'Reserved435', 436: 'Reserved436', 437: 'Reserved437', 438: 'Reserved438', 439: 'Reserved439', 440: 'Reserved440', 441: 'Reserved441', 442: 'Reserved442', 443: 'Reserved443', 444: 'Reserved444', 445: 'Reserved445', 446: 'Reserved446', 447: 'Reserved447', 448: 'Reserved448', 449: 'Reserved449', 450: 'Reserved450', 451: 'Reserved451', 452: 'Reserved452', 453: 'Reserved453', 454: 'Reserved454', 455: 'Reserved455', 456: 'Reserved456', 457: 'Reserved457', 458: 'Reserved458', 459: 'Reserved459', 460: 'Reserved460', 461: 'Reserved461', 462: 'Reserved462', 463: 'Reserved463', 464: 'Reserved464', 465: 'Reserved465', 466: 'Reserved466', 467: 'Reserved467', 468: 'Reserved468', 469: 'Reserved469', 470: 'Reserved470', 471: 'Reserved471', 472: 'Reserved472', 473: 'Reserved473', 474: 'Reserved474', 475: 'Reserved475', 476: 'Reserved476', 477: 'Reserved477', 478: 'Reserved478', 479: 'Reserved479', 480: 'Reserved480', 481: 'Reserved481', 482: 'Reserved482', 483: 'Reserved483', 484: 'Reserved484', 485: 'Reserved485', 486: 'Reserved486', 487: 'Reserved487', 488: 'Reserved488', 489: 'Reserved489', 490: 'Reserved490', 491: 'Reserved491', 492: 'Reserved492', 493: 'Reserved493', 494: 'Reserved494', 495: 'Reserved495', 496: 'Reserved496', 497: 'Reserved497', 498: 'Reserved498', 499: 'Reserved499', 500: 'Reserved500', 501: 'Reserved501', 502: 'Reserved502', 503: 'Reserved503', 504: 'Reserved504', 505: 'Reserved505', 506: 'Reserved506', 507: 'Reserved507', 508: 'Reserved508', 509: 'Reserved509', 510: 'Reserved510', 511: 'Reserved511', } IH_PERF_SEL_CYCLE = 0 IH_PERF_SEL_IDLE = 1 IH_PERF_SEL_INPUT_IDLE = 2 IH_PERF_SEL_BUFFER_IDLE = 3 IH_PERF_SEL_RB0_FULL = 4 IH_PERF_SEL_RB0_OVERFLOW = 5 IH_PERF_SEL_RB0_WPTR_WRITEBACK = 6 IH_PERF_SEL_RB0_WPTR_WRAP = 7 IH_PERF_SEL_RB0_RPTR_WRAP = 8 IH_PERF_SEL_MC_WR_IDLE = 9 IH_PERF_SEL_MC_WR_COUNT = 10 IH_PERF_SEL_MC_WR_STALL = 11 IH_PERF_SEL_MC_WR_CLEAN_PENDING = 12 IH_PERF_SEL_MC_WR_CLEAN_STALL = 13 IH_PERF_SEL_BIF_LINE0_RISING = 14 IH_PERF_SEL_BIF_LINE0_FALLING = 15 IH_PERF_SEL_RB1_FULL = 16 IH_PERF_SEL_RB1_OVERFLOW = 17 Reserved18 = 18 IH_PERF_SEL_RB1_WPTR_WRAP = 19 IH_PERF_SEL_RB1_RPTR_WRAP = 20 IH_PERF_SEL_RB2_FULL = 21 IH_PERF_SEL_RB2_OVERFLOW = 22 Reserved23 = 23 IH_PERF_SEL_RB2_WPTR_WRAP = 24 IH_PERF_SEL_RB2_RPTR_WRAP = 25 Reserved26 = 26 Reserved27 = 27 Reserved28 = 28 Reserved29 = 29 IH_PERF_SEL_RB0_FULL_VF0 = 30 IH_PERF_SEL_RB0_FULL_VF1 = 31 IH_PERF_SEL_RB0_FULL_VF2 = 32 IH_PERF_SEL_RB0_FULL_VF3 = 33 IH_PERF_SEL_RB0_FULL_VF4 = 34 IH_PERF_SEL_RB0_FULL_VF5 = 35 IH_PERF_SEL_RB0_FULL_VF6 = 36 IH_PERF_SEL_RB0_FULL_VF7 = 37 IH_PERF_SEL_RB0_FULL_VF8 = 38 IH_PERF_SEL_RB0_FULL_VF9 = 39 IH_PERF_SEL_RB0_FULL_VF10 = 40 IH_PERF_SEL_RB0_FULL_VF11 = 41 IH_PERF_SEL_RB0_FULL_VF12 = 42 IH_PERF_SEL_RB0_FULL_VF13 = 43 IH_PERF_SEL_RB0_FULL_VF14 = 44 IH_PERF_SEL_RB0_FULL_VF15 = 45 IH_PERF_SEL_RB0_OVERFLOW_VF0 = 46 IH_PERF_SEL_RB0_OVERFLOW_VF1 = 47 IH_PERF_SEL_RB0_OVERFLOW_VF2 = 48 IH_PERF_SEL_RB0_OVERFLOW_VF3 = 49 IH_PERF_SEL_RB0_OVERFLOW_VF4 = 50 IH_PERF_SEL_RB0_OVERFLOW_VF5 = 51 IH_PERF_SEL_RB0_OVERFLOW_VF6 = 52 IH_PERF_SEL_RB0_OVERFLOW_VF7 = 53 IH_PERF_SEL_RB0_OVERFLOW_VF8 = 54 IH_PERF_SEL_RB0_OVERFLOW_VF9 = 55 IH_PERF_SEL_RB0_OVERFLOW_VF10 = 56 IH_PERF_SEL_RB0_OVERFLOW_VF11 = 57 IH_PERF_SEL_RB0_OVERFLOW_VF12 = 58 IH_PERF_SEL_RB0_OVERFLOW_VF13 = 59 IH_PERF_SEL_RB0_OVERFLOW_VF14 = 60 IH_PERF_SEL_RB0_OVERFLOW_VF15 = 61 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 62 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 63 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 64 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 65 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 66 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 67 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 68 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 69 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 70 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 71 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 72 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 73 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 74 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 75 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 76 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 77 IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 78 IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 79 IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 80 IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 81 IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 82 IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 83 IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 84 IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 85 IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 86 IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 87 IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 88 IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 89 IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 90 IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 91 IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 92 IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 93 IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 94 IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 95 IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 96 IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 97 IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 98 IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 99 IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 100 IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 101 IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 102 IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 103 IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 104 IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 105 IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 106 IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 107 IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 108 IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 109 IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 110 IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 111 IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 112 IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 113 IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 114 IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 115 IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 116 IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 117 IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 118 IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 119 IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 120 IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 121 IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 122 IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 123 IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 124 IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 125 IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 126 IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 127 IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 128 IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 129 IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 130 IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 131 IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 132 IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 133 IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 134 IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 135 IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 136 IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 137 IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 138 IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 139 IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 140 IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 141 Reserved142 = 142 Reserved143 = 143 Reserved144 = 144 Reserved145 = 145 Reserved146 = 146 Reserved147 = 147 Reserved148 = 148 Reserved149 = 149 IH_PERF_SEL_CLIENT0_INT = 150 IH_PERF_SEL_CLIENT1_INT = 151 IH_PERF_SEL_CLIENT2_INT = 152 IH_PERF_SEL_CLIENT3_INT = 153 IH_PERF_SEL_CLIENT4_INT = 154 IH_PERF_SEL_CLIENT5_INT = 155 IH_PERF_SEL_CLIENT6_INT = 156 IH_PERF_SEL_CLIENT7_INT = 157 IH_PERF_SEL_CLIENT8_INT = 158 IH_PERF_SEL_CLIENT9_INT = 159 IH_PERF_SEL_CLIENT10_INT = 160 IH_PERF_SEL_CLIENT11_INT = 161 IH_PERF_SEL_CLIENT12_INT = 162 IH_PERF_SEL_CLIENT13_INT = 163 IH_PERF_SEL_CLIENT14_INT = 164 IH_PERF_SEL_CLIENT15_INT = 165 IH_PERF_SEL_CLIENT16_INT = 166 IH_PERF_SEL_CLIENT17_INT = 167 IH_PERF_SEL_CLIENT18_INT = 168 IH_PERF_SEL_CLIENT19_INT = 169 IH_PERF_SEL_CLIENT20_INT = 170 IH_PERF_SEL_CLIENT21_INT = 171 IH_PERF_SEL_CLIENT22_INT = 172 IH_PERF_SEL_CLIENT23_INT = 173 IH_PERF_SEL_CLIENT24_INT = 174 IH_PERF_SEL_CLIENT25_INT = 175 IH_PERF_SEL_CLIENT26_INT = 176 IH_PERF_SEL_CLIENT27_INT = 177 IH_PERF_SEL_CLIENT28_INT = 178 IH_PERF_SEL_CLIENT29_INT = 179 IH_PERF_SEL_CLIENT30_INT = 180 IH_PERF_SEL_CLIENT31_INT = 181 Reserved182 = 182 Reserved183 = 183 Reserved184 = 184 Reserved185 = 185 Reserved186 = 186 Reserved187 = 187 Reserved188 = 188 Reserved189 = 189 Reserved190 = 190 Reserved191 = 191 Reserved192 = 192 Reserved193 = 193 Reserved194 = 194 Reserved195 = 195 Reserved196 = 196 Reserved197 = 197 Reserved198 = 198 Reserved199 = 199 Reserved200 = 200 Reserved201 = 201 Reserved202 = 202 Reserved203 = 203 Reserved204 = 204 Reserved205 = 205 Reserved206 = 206 Reserved207 = 207 Reserved208 = 208 Reserved209 = 209 Reserved210 = 210 Reserved211 = 211 Reserved212 = 212 Reserved213 = 213 Reserved214 = 214 Reserved215 = 215 Reserved216 = 216 Reserved217 = 217 Reserved218 = 218 Reserved219 = 219 IH_PERF_SEL_RB1_FULL_VF0 = 220 IH_PERF_SEL_RB1_FULL_VF1 = 221 IH_PERF_SEL_RB1_FULL_VF2 = 222 IH_PERF_SEL_RB1_FULL_VF3 = 223 IH_PERF_SEL_RB1_FULL_VF4 = 224 IH_PERF_SEL_RB1_FULL_VF5 = 225 IH_PERF_SEL_RB1_FULL_VF6 = 226 IH_PERF_SEL_RB1_FULL_VF7 = 227 IH_PERF_SEL_RB1_FULL_VF8 = 228 IH_PERF_SEL_RB1_FULL_VF9 = 229 IH_PERF_SEL_RB1_FULL_VF10 = 230 IH_PERF_SEL_RB1_FULL_VF11 = 231 IH_PERF_SEL_RB1_FULL_VF12 = 232 IH_PERF_SEL_RB1_FULL_VF13 = 233 IH_PERF_SEL_RB1_FULL_VF14 = 234 IH_PERF_SEL_RB1_FULL_VF15 = 235 IH_PERF_SEL_RB1_OVERFLOW_VF0 = 236 IH_PERF_SEL_RB1_OVERFLOW_VF1 = 237 IH_PERF_SEL_RB1_OVERFLOW_VF2 = 238 IH_PERF_SEL_RB1_OVERFLOW_VF3 = 239 IH_PERF_SEL_RB1_OVERFLOW_VF4 = 240 IH_PERF_SEL_RB1_OVERFLOW_VF5 = 241 IH_PERF_SEL_RB1_OVERFLOW_VF6 = 242 IH_PERF_SEL_RB1_OVERFLOW_VF7 = 243 IH_PERF_SEL_RB1_OVERFLOW_VF8 = 244 IH_PERF_SEL_RB1_OVERFLOW_VF9 = 245 IH_PERF_SEL_RB1_OVERFLOW_VF10 = 246 IH_PERF_SEL_RB1_OVERFLOW_VF11 = 247 IH_PERF_SEL_RB1_OVERFLOW_VF12 = 248 IH_PERF_SEL_RB1_OVERFLOW_VF13 = 249 IH_PERF_SEL_RB1_OVERFLOW_VF14 = 250 IH_PERF_SEL_RB1_OVERFLOW_VF15 = 251 Reserved252 = 252 Reserved253 = 253 Reserved254 = 254 Reserved255 = 255 Reserved256 = 256 Reserved257 = 257 Reserved258 = 258 Reserved259 = 259 Reserved260 = 260 Reserved261 = 261 Reserved262 = 262 Reserved263 = 263 Reserved264 = 264 Reserved265 = 265 Reserved266 = 266 Reserved267 = 267 IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 268 IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 269 IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 270 IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 271 IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 272 IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 273 IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 274 IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 275 IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 276 IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 277 IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 278 IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 279 IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 280 IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 281 IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 282 IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 283 IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 284 IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 285 IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 286 IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 287 IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 288 IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 289 IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 290 IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 291 IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 292 IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 293 IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 294 IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 295 IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 296 IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 297 IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 298 IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 299 Reserved300 = 300 Reserved301 = 301 Reserved302 = 302 Reserved303 = 303 Reserved304 = 304 Reserved305 = 305 Reserved306 = 306 Reserved307 = 307 Reserved308 = 308 Reserved309 = 309 Reserved310 = 310 Reserved311 = 311 Reserved312 = 312 Reserved313 = 313 Reserved314 = 314 Reserved315 = 315 Reserved316 = 316 Reserved317 = 317 Reserved318 = 318 Reserved319 = 319 Reserved320 = 320 Reserved321 = 321 Reserved322 = 322 Reserved323 = 323 Reserved324 = 324 Reserved325 = 325 Reserved326 = 326 Reserved327 = 327 Reserved328 = 328 Reserved329 = 329 Reserved330 = 330 Reserved331 = 331 IH_PERF_SEL_RB2_FULL_VF0 = 332 IH_PERF_SEL_RB2_FULL_VF1 = 333 IH_PERF_SEL_RB2_FULL_VF2 = 334 IH_PERF_SEL_RB2_FULL_VF3 = 335 IH_PERF_SEL_RB2_FULL_VF4 = 336 IH_PERF_SEL_RB2_FULL_VF5 = 337 IH_PERF_SEL_RB2_FULL_VF6 = 338 IH_PERF_SEL_RB2_FULL_VF7 = 339 IH_PERF_SEL_RB2_FULL_VF8 = 340 IH_PERF_SEL_RB2_FULL_VF9 = 341 IH_PERF_SEL_RB2_FULL_VF10 = 342 IH_PERF_SEL_RB2_FULL_VF11 = 343 IH_PERF_SEL_RB2_FULL_VF12 = 344 IH_PERF_SEL_RB2_FULL_VF13 = 345 IH_PERF_SEL_RB2_FULL_VF14 = 346 IH_PERF_SEL_RB2_FULL_VF15 = 347 IH_PERF_SEL_RB2_OVERFLOW_VF0 = 348 IH_PERF_SEL_RB2_OVERFLOW_VF1 = 349 IH_PERF_SEL_RB2_OVERFLOW_VF2 = 350 IH_PERF_SEL_RB2_OVERFLOW_VF3 = 351 IH_PERF_SEL_RB2_OVERFLOW_VF4 = 352 IH_PERF_SEL_RB2_OVERFLOW_VF5 = 353 IH_PERF_SEL_RB2_OVERFLOW_VF6 = 354 IH_PERF_SEL_RB2_OVERFLOW_VF7 = 355 IH_PERF_SEL_RB2_OVERFLOW_VF8 = 356 IH_PERF_SEL_RB2_OVERFLOW_VF9 = 357 IH_PERF_SEL_RB2_OVERFLOW_VF10 = 358 IH_PERF_SEL_RB2_OVERFLOW_VF11 = 359 IH_PERF_SEL_RB2_OVERFLOW_VF12 = 360 IH_PERF_SEL_RB2_OVERFLOW_VF13 = 361 IH_PERF_SEL_RB2_OVERFLOW_VF14 = 362 IH_PERF_SEL_RB2_OVERFLOW_VF15 = 363 Reserved364 = 364 Reserved365 = 365 Reserved366 = 366 Reserved367 = 367 Reserved368 = 368 Reserved369 = 369 Reserved370 = 370 Reserved371 = 371 Reserved372 = 372 Reserved373 = 373 Reserved374 = 374 Reserved375 = 375 Reserved376 = 376 Reserved377 = 377 Reserved378 = 378 Reserved379 = 379 IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 380 IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 381 IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 382 IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 383 IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 384 IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 385 IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 386 IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 387 IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 388 IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 389 IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 390 IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 391 IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 392 IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 393 IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 394 IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 395 IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 396 IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 397 IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 398 IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 399 IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 400 IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 401 IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 402 IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 403 IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 404 IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 405 IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 406 IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 407 IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 408 IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 409 IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 410 IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 411 Reserved412 = 412 Reserved413 = 413 Reserved414 = 414 Reserved415 = 415 Reserved416 = 416 Reserved417 = 417 Reserved418 = 418 Reserved419 = 419 Reserved420 = 420 Reserved421 = 421 Reserved422 = 422 Reserved423 = 423 Reserved424 = 424 Reserved425 = 425 Reserved426 = 426 Reserved427 = 427 Reserved428 = 428 Reserved429 = 429 Reserved430 = 430 Reserved431 = 431 Reserved432 = 432 Reserved433 = 433 Reserved434 = 434 Reserved435 = 435 Reserved436 = 436 Reserved437 = 437 Reserved438 = 438 Reserved439 = 439 Reserved440 = 440 Reserved441 = 441 Reserved442 = 442 Reserved443 = 443 Reserved444 = 444 Reserved445 = 445 Reserved446 = 446 Reserved447 = 447 Reserved448 = 448 Reserved449 = 449 Reserved450 = 450 Reserved451 = 451 Reserved452 = 452 Reserved453 = 453 Reserved454 = 454 Reserved455 = 455 Reserved456 = 456 Reserved457 = 457 Reserved458 = 458 Reserved459 = 459 Reserved460 = 460 Reserved461 = 461 Reserved462 = 462 Reserved463 = 463 Reserved464 = 464 Reserved465 = 465 Reserved466 = 466 Reserved467 = 467 Reserved468 = 468 Reserved469 = 469 Reserved470 = 470 Reserved471 = 471 Reserved472 = 472 Reserved473 = 473 Reserved474 = 474 Reserved475 = 475 Reserved476 = 476 Reserved477 = 477 Reserved478 = 478 Reserved479 = 479 Reserved480 = 480 Reserved481 = 481 Reserved482 = 482 Reserved483 = 483 Reserved484 = 484 Reserved485 = 485 Reserved486 = 486 Reserved487 = 487 Reserved488 = 488 Reserved489 = 489 Reserved490 = 490 Reserved491 = 491 Reserved492 = 492 Reserved493 = 493 Reserved494 = 494 Reserved495 = 495 Reserved496 = 496 Reserved497 = 497 Reserved498 = 498 Reserved499 = 499 Reserved500 = 500 Reserved501 = 501 Reserved502 = 502 Reserved503 = 503 Reserved504 = 504 Reserved505 = 505 Reserved506 = 506 Reserved507 = 507 Reserved508 = 508 Reserved509 = 509 Reserved510 = 510 Reserved511 = 511 IH_PERF_SEL = ctypes.c_uint32 # enum # values for enumeration 'SEM_PERF_SEL' SEM_PERF_SEL__enumvalues = { 0: 'SEM_PERF_SEL_CYCLE', 1: 'SEM_PERF_SEL_IDLE', 2: 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 3: 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 4: 'SEM_PERF_SEL_UVD_REQ_SIGNAL', 5: 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 6: 'SEM_PERF_SEL_ACP_REQ_SIGNAL', 7: 'SEM_PERF_SEL_ISP_REQ_SIGNAL', 8: 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 9: 'SEM_PERF_SEL_VP8_REQ_SIGNAL', 10: 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 11: 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 12: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', 13: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', 14: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', 15: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', 16: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', 17: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', 18: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', 19: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', 20: 'SEM_PERF_SEL_SDMA0_REQ_WAIT', 21: 'SEM_PERF_SEL_SDMA1_REQ_WAIT', 22: 'SEM_PERF_SEL_UVD_REQ_WAIT', 23: 'SEM_PERF_SEL_VCE0_REQ_WAIT', 24: 'SEM_PERF_SEL_ACP_REQ_WAIT', 25: 'SEM_PERF_SEL_ISP_REQ_WAIT', 26: 'SEM_PERF_SEL_VCE1_REQ_WAIT', 27: 'SEM_PERF_SEL_VP8_REQ_WAIT', 28: 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', 29: 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', 30: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', 31: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', 32: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', 33: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', 34: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', 35: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', 36: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', 37: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', 38: 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', 39: 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', 40: 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', 41: 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', 42: 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', 43: 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', 44: 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', 45: 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', 46: 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', 47: 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', 48: 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', 49: 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', 50: 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', 51: 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', 52: 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', 53: 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', 54: 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', 55: 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', 56: 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', 57: 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', 58: 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', 59: 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', 60: 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', 61: 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', 62: 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', 63: 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', 64: 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', 65: 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', 66: 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', 67: 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', 68: 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', 69: 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', 70: 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', 71: 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', 72: 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', 73: 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', 74: 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', 75: 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', 76: 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', 77: 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', 78: 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', 79: 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', 80: 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', 81: 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', 82: 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', 83: 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', 84: 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', 85: 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', 86: 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', 87: 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', 88: 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', 89: 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', 90: 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', 91: 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', 92: 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', 93: 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', 94: 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', 95: 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', 96: 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', 97: 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', 98: 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', 99: 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', 100: 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', 101: 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', 102: 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', 103: 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', 104: 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', 105: 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', 106: 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', 107: 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', 108: 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', 109: 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', 110: 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', 111: 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', 112: 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', 113: 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', 114: 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', 115: 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', 116: 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', 117: 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', 118: 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', 119: 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', 120: 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', 121: 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', 122: 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', 123: 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', 124: 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', 125: 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', 126: 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', 127: 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', 128: 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', 129: 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', 130: 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', 131: 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', 132: 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', 133: 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', 134: 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', 135: 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', 136: 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', 137: 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', 138: 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', 139: 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', 140: 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', 141: 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', 142: 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', 143: 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', 144: 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', 145: 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', 146: 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', 147: 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', 148: 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', 149: 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', 150: 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', 151: 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', 152: 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', 153: 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', 154: 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', 155: 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', 156: 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', 157: 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', 158: 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', 159: 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', 160: 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', 161: 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', 162: 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', 163: 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', 164: 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', 165: 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', 166: 'SEM_PERF_SEL_MC_RD_REQ', 167: 'SEM_PERF_SEL_MC_RD_RET', 168: 'SEM_PERF_SEL_MC_WR_REQ', 169: 'SEM_PERF_SEL_MC_WR_RET', 170: 'SEM_PERF_SEL_ATC_REQ', 171: 'SEM_PERF_SEL_ATC_RET', 172: 'SEM_PERF_SEL_ATC_XNACK', 173: 'SEM_PERF_SEL_ATC_INVALIDATION', } SEM_PERF_SEL_CYCLE = 0 SEM_PERF_SEL_IDLE = 1 SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 2 SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 3 SEM_PERF_SEL_UVD_REQ_SIGNAL = 4 SEM_PERF_SEL_VCE0_REQ_SIGNAL = 5 SEM_PERF_SEL_ACP_REQ_SIGNAL = 6 SEM_PERF_SEL_ISP_REQ_SIGNAL = 7 SEM_PERF_SEL_VCE1_REQ_SIGNAL = 8 SEM_PERF_SEL_VP8_REQ_SIGNAL = 9 SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 10 SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 11 SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 12 SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 13 SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 14 SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 15 SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 16 SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 17 SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 18 SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 19 SEM_PERF_SEL_SDMA0_REQ_WAIT = 20 SEM_PERF_SEL_SDMA1_REQ_WAIT = 21 SEM_PERF_SEL_UVD_REQ_WAIT = 22 SEM_PERF_SEL_VCE0_REQ_WAIT = 23 SEM_PERF_SEL_ACP_REQ_WAIT = 24 SEM_PERF_SEL_ISP_REQ_WAIT = 25 SEM_PERF_SEL_VCE1_REQ_WAIT = 26 SEM_PERF_SEL_VP8_REQ_WAIT = 27 SEM_PERF_SEL_CPG_E0_REQ_WAIT = 28 SEM_PERF_SEL_CPG_E1_REQ_WAIT = 29 SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 30 SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 31 SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 32 SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 33 SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 34 SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 35 SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 36 SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 37 SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 38 SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 39 SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 40 SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 41 SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 42 SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 43 SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 44 SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 45 SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 46 SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 47 SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 48 SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 49 SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 50 SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 51 SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 52 SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 53 SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 54 SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 55 SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 56 SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 57 SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 58 SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 59 SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 60 SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 61 SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 62 SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 63 SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 64 SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 65 SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 66 SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 67 SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 68 SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 69 SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 70 SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 71 SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 72 SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 73 SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 74 SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 75 SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 76 SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 77 SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 78 SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 79 SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 80 SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 81 SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 82 SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 83 SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 84 SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 85 SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 86 SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 87 SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 88 SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 89 SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 90 SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 91 SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 92 SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 93 SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 94 SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 95 SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 96 SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 97 SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 98 SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 99 SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 100 SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 101 SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 102 SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 103 SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 104 SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 105 SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 106 SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 107 SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 108 SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 109 SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 110 SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 111 SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 112 SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 113 SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 114 SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 115 SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 116 SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 117 SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 118 SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 119 SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 120 SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 121 SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 122 SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 123 SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 124 SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 125 SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 126 SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 127 SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 128 SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 129 SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 130 SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 131 SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 132 SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 133 SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 134 SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 135 SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 136 SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 137 SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 138 SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 139 SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 140 SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 141 SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 142 SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 143 SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 144 SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 145 SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 146 SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 147 SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 148 SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 149 SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 150 SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 151 SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 152 SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 153 SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 154 SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 155 SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 156 SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 157 SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 158 SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 159 SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 160 SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 161 SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 162 SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 163 SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 164 SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 165 SEM_PERF_SEL_MC_RD_REQ = 166 SEM_PERF_SEL_MC_RD_RET = 167 SEM_PERF_SEL_MC_WR_REQ = 168 SEM_PERF_SEL_MC_WR_RET = 169 SEM_PERF_SEL_ATC_REQ = 170 SEM_PERF_SEL_ATC_RET = 171 SEM_PERF_SEL_ATC_XNACK = 172 SEM_PERF_SEL_ATC_INVALIDATION = 173 SEM_PERF_SEL = ctypes.c_uint32 # enum # values for enumeration 'SDMA_PERF_SEL' SDMA_PERF_SEL__enumvalues = { 0: 'SDMA_PERF_SEL_CYCLE', 1: 'SDMA_PERF_SEL_IDLE', 2: 'SDMA_PERF_SEL_REG_IDLE', 3: 'SDMA_PERF_SEL_RB_EMPTY', 4: 'SDMA_PERF_SEL_RB_FULL', 5: 'SDMA_PERF_SEL_RB_WPTR_WRAP', 6: 'SDMA_PERF_SEL_RB_RPTR_WRAP', 7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 8: 'SDMA_PERF_SEL_RB_RPTR_WB', 9: 'SDMA_PERF_SEL_RB_CMD_IDLE', 10: 'SDMA_PERF_SEL_RB_CMD_FULL', 11: 'SDMA_PERF_SEL_IB_CMD_IDLE', 12: 'SDMA_PERF_SEL_IB_CMD_FULL', 13: 'SDMA_PERF_SEL_EX_IDLE', 14: 'SDMA_PERF_SEL_SRBM_REG_SEND', 15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', 16: 'SDMA_PERF_SEL_MC_WR_IDLE', 17: 'SDMA_PERF_SEL_MC_WR_COUNT', 18: 'SDMA_PERF_SEL_MC_RD_IDLE', 19: 'SDMA_PERF_SEL_MC_RD_COUNT', 20: 'SDMA_PERF_SEL_MC_RD_RET_STALL', 21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', 24: 'SDMA_PERF_SEL_SEM_IDLE', 25: 'SDMA_PERF_SEL_SEM_REQ_STALL', 26: 'SDMA_PERF_SEL_SEM_REQ_COUNT', 27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', 28: 'SDMA_PERF_SEL_SEM_RESP_FAIL', 29: 'SDMA_PERF_SEL_SEM_RESP_PASS', 30: 'SDMA_PERF_SEL_INT_IDLE', 31: 'SDMA_PERF_SEL_INT_REQ_STALL', 32: 'SDMA_PERF_SEL_INT_REQ_COUNT', 33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', 34: 'SDMA_PERF_SEL_INT_RESP_RETRY', 35: 'SDMA_PERF_SEL_NUM_PACKET', 37: 'SDMA_PERF_SEL_CE_WREQ_IDLE', 38: 'SDMA_PERF_SEL_CE_WR_IDLE', 39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 40: 'SDMA_PERF_SEL_CE_RREQ_IDLE', 41: 'SDMA_PERF_SEL_CE_OUT_IDLE', 42: 'SDMA_PERF_SEL_CE_IN_IDLE', 43: 'SDMA_PERF_SEL_CE_DST_IDLE', 46: 'SDMA_PERF_SEL_CE_AFIFO_FULL', 49: 'SDMA_PERF_SEL_CE_INFO_FULL', 50: 'SDMA_PERF_SEL_CE_INFO1_FULL', 51: 'SDMA_PERF_SEL_CE_RD_STALL', 52: 'SDMA_PERF_SEL_CE_WR_STALL', 53: 'SDMA_PERF_SEL_GFX_SELECT', 54: 'SDMA_PERF_SEL_RLC0_SELECT', 55: 'SDMA_PERF_SEL_RLC1_SELECT', 56: 'SDMA_PERF_SEL_PAGE_SELECT', 57: 'SDMA_PERF_SEL_CTX_CHANGE', 58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', 60: 'SDMA_PERF_SEL_DOORBELL', 61: 'SDMA_PERF_SEL_RD_BA_RTR', 62: 'SDMA_PERF_SEL_WR_BA_RTR', 63: 'SDMA_PERF_SEL_F32_L1_WR_VLD', 64: 'SDMA_PERF_SEL_CE_L1_WR_VLD', 65: 'SDMA_PERF_SEL_CE_L1_STALL', 66: 'SDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 67: 'SDMA_PERF_SEL_SDMA_INVACK_FLUSH', 68: 'SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', 69: 'SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', 70: 'SDMA_PERF_SEL_ATCL2_RET_XNACK', 71: 'SDMA_PERF_SEL_ATCL2_RET_ACK', 72: 'SDMA_PERF_SEL_ATCL2_FREE', 73: 'SDMA_PERF_SEL_SDMA_ATCL2_SEND', 74: 'SDMA_PERF_SEL_DMA_L1_WR_SEND', 75: 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 76: 'SDMA_PERF_SEL_DMA_MC_WR_SEND', 77: 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 78: 'SDMA_PERF_SEL_L1_WR_FIFO_IDLE', 79: 'SDMA_PERF_SEL_L1_RD_FIFO_IDLE', 80: 'SDMA_PERF_SEL_L1_WRL2_IDLE', 81: 'SDMA_PERF_SEL_L1_RDL2_IDLE', 82: 'SDMA_PERF_SEL_L1_WRMC_IDLE', 83: 'SDMA_PERF_SEL_L1_RDMC_IDLE', 84: 'SDMA_PERF_SEL_L1_WR_INV_IDLE', 85: 'SDMA_PERF_SEL_L1_RD_INV_IDLE', 86: 'SDMA_PERF_SEL_L1_WR_INV_EN', 87: 'SDMA_PERF_SEL_L1_RD_INV_EN', 88: 'SDMA_PERF_SEL_L1_WR_WAIT_INVADR', 89: 'SDMA_PERF_SEL_L1_RD_WAIT_INVADR', 90: 'SDMA_PERF_SEL_IS_INVREQ_ADDR_WR', 91: 'SDMA_PERF_SEL_IS_INVREQ_ADDR_RD', 92: 'SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', 93: 'SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', 94: 'SDMA_PERF_SEL_L1_INV_MIDDLE', 254: 'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER', 255: 'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER', } SDMA_PERF_SEL_CYCLE = 0 SDMA_PERF_SEL_IDLE = 1 SDMA_PERF_SEL_REG_IDLE = 2 SDMA_PERF_SEL_RB_EMPTY = 3 SDMA_PERF_SEL_RB_FULL = 4 SDMA_PERF_SEL_RB_WPTR_WRAP = 5 SDMA_PERF_SEL_RB_RPTR_WRAP = 6 SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 SDMA_PERF_SEL_RB_RPTR_WB = 8 SDMA_PERF_SEL_RB_CMD_IDLE = 9 SDMA_PERF_SEL_RB_CMD_FULL = 10 SDMA_PERF_SEL_IB_CMD_IDLE = 11 SDMA_PERF_SEL_IB_CMD_FULL = 12 SDMA_PERF_SEL_EX_IDLE = 13 SDMA_PERF_SEL_SRBM_REG_SEND = 14 SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 SDMA_PERF_SEL_MC_WR_IDLE = 16 SDMA_PERF_SEL_MC_WR_COUNT = 17 SDMA_PERF_SEL_MC_RD_IDLE = 18 SDMA_PERF_SEL_MC_RD_COUNT = 19 SDMA_PERF_SEL_MC_RD_RET_STALL = 20 SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 SDMA_PERF_SEL_SEM_IDLE = 24 SDMA_PERF_SEL_SEM_REQ_STALL = 25 SDMA_PERF_SEL_SEM_REQ_COUNT = 26 SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 SDMA_PERF_SEL_SEM_RESP_FAIL = 28 SDMA_PERF_SEL_SEM_RESP_PASS = 29 SDMA_PERF_SEL_INT_IDLE = 30 SDMA_PERF_SEL_INT_REQ_STALL = 31 SDMA_PERF_SEL_INT_REQ_COUNT = 32 SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 SDMA_PERF_SEL_INT_RESP_RETRY = 34 SDMA_PERF_SEL_NUM_PACKET = 35 SDMA_PERF_SEL_CE_WREQ_IDLE = 37 SDMA_PERF_SEL_CE_WR_IDLE = 38 SDMA_PERF_SEL_CE_SPLIT_IDLE = 39 SDMA_PERF_SEL_CE_RREQ_IDLE = 40 SDMA_PERF_SEL_CE_OUT_IDLE = 41 SDMA_PERF_SEL_CE_IN_IDLE = 42 SDMA_PERF_SEL_CE_DST_IDLE = 43 SDMA_PERF_SEL_CE_AFIFO_FULL = 46 SDMA_PERF_SEL_CE_INFO_FULL = 49 SDMA_PERF_SEL_CE_INFO1_FULL = 50 SDMA_PERF_SEL_CE_RD_STALL = 51 SDMA_PERF_SEL_CE_WR_STALL = 52 SDMA_PERF_SEL_GFX_SELECT = 53 SDMA_PERF_SEL_RLC0_SELECT = 54 SDMA_PERF_SEL_RLC1_SELECT = 55 SDMA_PERF_SEL_PAGE_SELECT = 56 SDMA_PERF_SEL_CTX_CHANGE = 57 SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 SDMA_PERF_SEL_DOORBELL = 60 SDMA_PERF_SEL_RD_BA_RTR = 61 SDMA_PERF_SEL_WR_BA_RTR = 62 SDMA_PERF_SEL_F32_L1_WR_VLD = 63 SDMA_PERF_SEL_CE_L1_WR_VLD = 64 SDMA_PERF_SEL_CE_L1_STALL = 65 SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 66 SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 67 SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 68 SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 69 SDMA_PERF_SEL_ATCL2_RET_XNACK = 70 SDMA_PERF_SEL_ATCL2_RET_ACK = 71 SDMA_PERF_SEL_ATCL2_FREE = 72 SDMA_PERF_SEL_SDMA_ATCL2_SEND = 73 SDMA_PERF_SEL_DMA_L1_WR_SEND = 74 SDMA_PERF_SEL_DMA_L1_RD_SEND = 75 SDMA_PERF_SEL_DMA_MC_WR_SEND = 76 SDMA_PERF_SEL_DMA_MC_RD_SEND = 77 SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 78 SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 79 SDMA_PERF_SEL_L1_WRL2_IDLE = 80 SDMA_PERF_SEL_L1_RDL2_IDLE = 81 SDMA_PERF_SEL_L1_WRMC_IDLE = 82 SDMA_PERF_SEL_L1_RDMC_IDLE = 83 SDMA_PERF_SEL_L1_WR_INV_IDLE = 84 SDMA_PERF_SEL_L1_RD_INV_IDLE = 85 SDMA_PERF_SEL_L1_WR_INV_EN = 86 SDMA_PERF_SEL_L1_RD_INV_EN = 87 SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 88 SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 89 SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 90 SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 91 SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 92 SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 93 SDMA_PERF_SEL_L1_INV_MIDDLE = 94 SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 254 SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 255 SDMA_PERF_SEL = ctypes.c_uint32 # enum # values for enumeration 'ENUM_XDMA_LOCAL_SW_MODE' ENUM_XDMA_LOCAL_SW_MODE__enumvalues = { 2: 'XDMA_LOCAL_SW_MODE_SW_256B_D', 10: 'XDMA_LOCAL_SW_MODE_SW_64KB_D', 26: 'XDMA_LOCAL_SW_MODE_SW_64KB_D_X', } XDMA_LOCAL_SW_MODE_SW_256B_D = 2 XDMA_LOCAL_SW_MODE_SW_64KB_D = 10 XDMA_LOCAL_SW_MODE_SW_64KB_D_X = 26 ENUM_XDMA_LOCAL_SW_MODE = ctypes.c_uint32 # enum # values for enumeration 'ENUM_XDMA_SLV_ALPHA_POSITION' ENUM_XDMA_SLV_ALPHA_POSITION__enumvalues = { 0: 'XDMA_SLV_ALPHA_POSITION_7_0', 1: 'XDMA_SLV_ALPHA_POSITION_15_8', 2: 'XDMA_SLV_ALPHA_POSITION_23_16', 3: 'XDMA_SLV_ALPHA_POSITION_31_24', } XDMA_SLV_ALPHA_POSITION_7_0 = 0 XDMA_SLV_ALPHA_POSITION_15_8 = 1 XDMA_SLV_ALPHA_POSITION_23_16 = 2 XDMA_SLV_ALPHA_POSITION_31_24 = 3 ENUM_XDMA_SLV_ALPHA_POSITION = ctypes.c_uint32 # enum # values for enumeration 'ENUM_XDMA_MSTR_ALPHA_POSITION' ENUM_XDMA_MSTR_ALPHA_POSITION__enumvalues = { 0: 'XDMA_MSTR_ALPHA_POSITION_7_0', 1: 'XDMA_MSTR_ALPHA_POSITION_15_8', 2: 'XDMA_MSTR_ALPHA_POSITION_23_16', 3: 'XDMA_MSTR_ALPHA_POSITION_31_24', } XDMA_MSTR_ALPHA_POSITION_7_0 = 0 XDMA_MSTR_ALPHA_POSITION_15_8 = 1 XDMA_MSTR_ALPHA_POSITION_23_16 = 2 XDMA_MSTR_ALPHA_POSITION_31_24 = 3 ENUM_XDMA_MSTR_ALPHA_POSITION = ctypes.c_uint32 # enum # values for enumeration 'ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL' ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL__enumvalues = { 0: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0', 1: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1', 2: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2', 3: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3', 4: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4', 5: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5', } XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0 = 0 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1 = 1 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2 = 2 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3 = 3 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4 = 4 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5 = 5 ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL = ctypes.c_uint32 # enum __all__ = \ ['ABGR_TO_A_BG_G_RB', 'ABM_SOFT_RESET', 'ABM_SOFT_RESET_0', 'ABM_SOFT_RESET_1', 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ADDR_CONFIG_16_BANK', 'ADDR_CONFIG_16_PIPE', 'ADDR_CONFIG_1KB_ROW', 'ADDR_CONFIG_1_BANK', 'ADDR_CONFIG_1_GPU', 'ADDR_CONFIG_1_LOWER_PIPES', 'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_1_PIPE', 'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE', 'ADDR_CONFIG_1_SHADER_ENGINE', 'ADDR_CONFIG_2KB_ROW', 'ADDR_CONFIG_2_BANK', 'ADDR_CONFIG_2_GPU', 'ADDR_CONFIG_2_LOWER_PIPES', 'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_2_PIPE', 'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE', 'ADDR_CONFIG_2_SHADER_ENGINE', 'ADDR_CONFIG_32_PIPE', 'ADDR_CONFIG_4KB_ROW', 'ADDR_CONFIG_4_BANK', 'ADDR_CONFIG_4_GPU', 'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_4_PIPE', 'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE', 'ADDR_CONFIG_4_SHADER_ENGINE', 'ADDR_CONFIG_8_BANK', 'ADDR_CONFIG_8_GPU', 'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_8_PIPE', 'ADDR_CONFIG_8_SHADER_ENGINE', 'ADDR_CONFIG_BANK_INTERLEAVE_1', 'ADDR_CONFIG_BANK_INTERLEAVE_2', 'ADDR_CONFIG_BANK_INTERLEAVE_4', 'ADDR_CONFIG_BANK_INTERLEAVE_8', 'ADDR_CONFIG_DISABLE_SE', 'ADDR_CONFIG_ENABLE_SE', 'ADDR_CONFIG_GPU_TILE_128', 'ADDR_CONFIG_GPU_TILE_16', 'ADDR_CONFIG_GPU_TILE_32', 'ADDR_CONFIG_GPU_TILE_64', 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB', 'ADDR_CONFIG_PIPE_INTERLEAVE_256B', 'ADDR_CONFIG_PIPE_INTERLEAVE_2KB', 'ADDR_CONFIG_PIPE_INTERLEAVE_512B', 'ADDR_CONFIG_SE_TILE_16', 'ADDR_CONFIG_SE_TILE_32', 'ADDR_SURF_16_BANK', 'ADDR_SURF_2_BANK', 'ADDR_SURF_4_BANK', 'ADDR_SURF_8_BANK', 'ADDR_SURF_BANK_HEIGHT_1', 'ADDR_SURF_BANK_HEIGHT_2', 'ADDR_SURF_BANK_HEIGHT_4', 'ADDR_SURF_BANK_HEIGHT_8', 'ADDR_SURF_BANK_WH_1', 'ADDR_SURF_BANK_WH_2', 'ADDR_SURF_BANK_WH_4', 'ADDR_SURF_BANK_WH_8', 'ADDR_SURF_BANK_WIDTH_1', 'ADDR_SURF_BANK_WIDTH_2', 'ADDR_SURF_BANK_WIDTH_4', 'ADDR_SURF_BANK_WIDTH_8', 'ADDR_SURF_DEPTH_MICRO_TILING', 'ADDR_SURF_DISPLAY_MICRO_TILING', 'ADDR_SURF_MACRO_ASPECT_1', 'ADDR_SURF_MACRO_ASPECT_2', 'ADDR_SURF_MACRO_ASPECT_4', 'ADDR_SURF_MACRO_ASPECT_8', 'ADDR_SURF_MICRO_TILING_DISPLAY', 'ADDR_SURF_MICRO_TILING_NON_DISPLAY', 'ADDR_SURF_P16_32x32_16x16', 'ADDR_SURF_P16_32x32_8x16', 'ADDR_SURF_P2', 'ADDR_SURF_P2_RESERVED0', 'ADDR_SURF_P2_RESERVED1', 'ADDR_SURF_P2_RESERVED2', 'ADDR_SURF_P4_16x16', 'ADDR_SURF_P4_16x32', 'ADDR_SURF_P4_32x32', 'ADDR_SURF_P4_8x16', 'ADDR_SURF_P8_16x16_8x16', 'ADDR_SURF_P8_16x32_16x16', 'ADDR_SURF_P8_16x32_8x16', 'ADDR_SURF_P8_32x32_16x16', 'ADDR_SURF_P8_32x32_16x32', 'ADDR_SURF_P8_32x32_8x16', 'ADDR_SURF_P8_32x64_32x32', 'ADDR_SURF_P8_RESERVED0', 'ADDR_SURF_ROTATED_MICRO_TILING', 'ADDR_SURF_SAMPLE_SPLIT_1', 'ADDR_SURF_SAMPLE_SPLIT_2', 'ADDR_SURF_SAMPLE_SPLIT_4', 'ADDR_SURF_SAMPLE_SPLIT_8', 'ADDR_SURF_THICK_MICRO_TILING', 'ADDR_SURF_THIN_MICRO_TILING', 'ADDR_SURF_TILE_SPLIT_128B', 'ADDR_SURF_TILE_SPLIT_1KB', 'ADDR_SURF_TILE_SPLIT_256B', 'ADDR_SURF_TILE_SPLIT_2KB', 'ADDR_SURF_TILE_SPLIT_4KB', 'ADDR_SURF_TILE_SPLIT_512B', 'ADDR_SURF_TILE_SPLIT_64B', 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', 'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG', 'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG', 'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG', 'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG', 'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL', 'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE', 'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10', 'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12', 'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14', 'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9', 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD', 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND', 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS', 'AFMT_AUDIO_PACKET_SENT_DISABLED', 'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT', 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', 'AFMT_AUDIO_SRC_RESERVED', 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE', 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', 'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE', 'AFMT_INTERRUPT_STATUS_CHG_MASK', 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', 'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED', 'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', 'ALLOW_SR_ON_TRANS_REQ', 'ALLOW_SR_ON_TRANS_REQ_DISABLE', 'ALLOW_SR_ON_TRANS_REQ_ENABLE', 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER', 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE', 'AOUT_CRC_CONT', 'AOUT_CRC_CONT_EN', 'AOUT_CRC_DISABLE', 'AOUT_CRC_ENABLE', 'AOUT_CRC_NO_RESET', 'AOUT_CRC_ONE_SHOT', 'AOUT_CRC_RESET', 'AOUT_CRC_SOFT_RESET', 'AOUT_CRC_TEST_EN', 'AOUT_DISABLE', 'AOUT_EN', 'AOUT_ENABLE', 'AOUT_FIFO_START_ADDR', 'AOUT_FIFO_START_ADDR_2', 'AOUT_FIFO_START_ADDR_3', 'ARRAY_1D', 'ARRAY_1D_TILED_THICK', 'ARRAY_1D_TILED_THIN1', 'ARRAY_2D', 'ARRAY_2D_ALT_COLOR', 'ARRAY_2D_ALT_DEPTH', 'ARRAY_2D_COLOR', 'ARRAY_2D_DEPTH', 'ARRAY_2D_TILED_THICK', 'ARRAY_2D_TILED_THIN1', 'ARRAY_2D_TILED_XTHICK', 'ARRAY_3D', 'ARRAY_3D_SLICE', 'ARRAY_3D_SLICE_COLOR', 'ARRAY_3D_TILED_THICK', 'ARRAY_3D_TILED_THIN1', 'ARRAY_3D_TILED_XTHICK', 'ARRAY_COLOR_TILE', 'ARRAY_DEPTH_TILE', 'ARRAY_LINEAR', 'ARRAY_LINEAR_ALIGNED', 'ARRAY_LINEAR_GENERAL', 'ARRAY_PRT_2D_TILED_THICK', 'ARRAY_PRT_2D_TILED_THIN1', 'ARRAY_PRT_3D_TILED_THICK', 'ARRAY_PRT_3D_TILED_THIN1', 'ARRAY_PRT_TILED_THICK', 'ARRAY_PRT_TILED_THIN1', 'ARRAY_TILED', 'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', 'AUDIO_LAYOUT_SELECT', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', 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'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT', 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE', 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET', 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', 'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED', 'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED', 'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES', 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', 'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET', 'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE', 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES', 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED', 'AZ_RIRB_WRITE_POINTER_DO_RESET', 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET', 'AZ_STATE_CHANGE_STATUS', 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'ArrayMode', 'Available_0x1c', 'Available_0x1d', 'BGRA_TO_BG_G_RB_A', 'BINNER_BREAK_BATCH', 'BINNER_DROP_ASSERT', 'BINNER_PIPELINE', 'BINNING_ALLOWED', 'BLEND_BOTH_INV_SRC_ALPHA', 'BLEND_BOTH_SRC_ALPHA', 'BLEND_CONSTANT_ALPHA', 'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR', 'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE', 'BLEND_ONE_MINUS_CONSTANT_ALPHA', 'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA', 'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA', 'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA', 'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE', 'BLEND_SRC_COLOR', 'BLEND_ZERO', 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN', 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN', 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', 'BLNDV_CONTROL2_PTI_ENABLE', 'BLNDV_CONTROL2_PTI_ENABLE_FALSE', 'BLNDV_CONTROL2_PTI_ENABLE_TRUE', 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY', 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE', 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE', 'BLNDV_CONTROL_BLND_ALPHA_MODE', 'BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', 'BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', 'BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', 'BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED', 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN', 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', 'BLNDV_CONTROL_BLND_MODE', 'BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', 'BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', 'BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', 'BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE', 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE', 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE', 'BLNDV_CONTROL_BLND_STEREO_POLARITY', 'BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH', 'BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW', 'BLNDV_CONTROL_BLND_STEREO_TYPE', 'BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', 'BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', 'BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', 'BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED', 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT', 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH', 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW', 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE', 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL', 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL', 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE', 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', 'BLNDV_SM_CONTROL2_SM_MODE', 'BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', 'BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', 'BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', 'BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE', 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN', 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK', 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK', 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK', 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK', 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK', 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK', 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK', 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK', 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE', 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN', 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN', 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', 'BLND_CONTROL2_PTI_ENABLE', 'BLND_CONTROL2_PTI_ENABLE_FALSE', 'BLND_CONTROL2_PTI_ENABLE_TRUE', 'BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY', 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE', 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE', 'BLND_CONTROL_BLND_ALPHA_MODE', 'BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', 'BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', 'BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', 'BLND_CONTROL_BLND_ALPHA_MODE_UNUSED', 'BLND_CONTROL_BLND_FEEDTHROUGH_EN', 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', 'BLND_CONTROL_BLND_MODE', 'BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', 'BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', 'BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', 'BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', 'BLND_CONTROL_BLND_MULTIPLIED_MODE', 'BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE', 'BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE', 'BLND_CONTROL_BLND_STEREO_POLARITY', 'BLND_CONTROL_BLND_STEREO_POLARITY_HIGH', 'BLND_CONTROL_BLND_STEREO_POLARITY_LOW', 'BLND_CONTROL_BLND_STEREO_TYPE', 'BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', 'BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', 'BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', 'BLND_CONTROL_BLND_STEREO_TYPE_UNUSED', 'BLND_DEBUG_BLND_CNV_MUX_SELECT', 'BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH', 'BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW', 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE', 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL', 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL', 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE', 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', 'BLND_SM_CONTROL2_SM_MODE', 'BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', 'BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', 'BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', 'BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE', 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN', 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK', 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK', 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK', 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK', 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK', 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK', 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK', 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK', 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE', 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', 'BLOCK_CONTEXT_DONE', 'BOTTOM_OF_PIPE_TS', 'BREAK_BATCH', 'BUF_DATA_FORMAT', 'BUF_DATA_FORMAT_10_10_10_2', 'BUF_DATA_FORMAT_10_11_11', 'BUF_DATA_FORMAT_11_11_10', 'BUF_DATA_FORMAT_16', 'BUF_DATA_FORMAT_16_16', 'BUF_DATA_FORMAT_16_16_16_16', 'BUF_DATA_FORMAT_2_10_10_10', 'BUF_DATA_FORMAT_32', 'BUF_DATA_FORMAT_32_32', 'BUF_DATA_FORMAT_32_32_32', 'BUF_DATA_FORMAT_32_32_32_32', 'BUF_DATA_FORMAT_8', 'BUF_DATA_FORMAT_8_8', 'BUF_DATA_FORMAT_8_8_8_8', 'BUF_DATA_FORMAT_INVALID', 'BUF_DATA_FORMAT_RESERVED_15', 'BUF_NUM_FORMAT', 'BUF_NUM_FORMAT_FLOAT', 'BUF_NUM_FORMAT_SINT', 'BUF_NUM_FORMAT_SNORM', 'BUF_NUM_FORMAT_SSCALED', 'BUF_NUM_FORMAT_UINT', 'BUF_NUM_FORMAT_UNORM', 'BUF_NUM_FORMAT_UNORM_UINT', 'BUF_NUM_FORMAT_USCALED', 'BankHeight', 'BankInterleaveSize', 'BankSwapBytes', 'BankTiling', 'BankWidth', 'BankWidthHeight', 'BinEventCntl', 'BinningMode', 'BlendOp', 'BlendOpt', 'CACHE_FLUSH', 'CACHE_FLUSH_AND_INV_EVENT', 'CACHE_FLUSH_AND_INV_TS_EVENT', 'CACHE_FLUSH_TS', 'CBMode', 'CBPerfClearFilterSel', 'CBPerfOpFilterSel', 'CBPerfSel', 'CB_DCC_DECOMPRESS', 'CB_DECOMPRESS', 'CB_DISABLE', 'CB_ELIMINATE_FAST_CLEAR', 'CB_FMASK_DECOMPRESS', 'CB_NORMAL', 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', 'CB_PERF_OP_FILTER_SEL_RESOLVE', 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', 'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL', 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', 'CB_PERF_SEL_BUSY', 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY', 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB', 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY', 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB', 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY', 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB', 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY', 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB', 'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY', 'CB_PERF_SEL_CC_BC_CS_FRAG_VALID', 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', 'CB_PERF_SEL_CC_CACHE_FLUSH', 'CB_PERF_SEL_CC_CACHE_HIT', 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL', 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', 'CB_PERF_SEL_CC_CACHE_TAG_MISS', 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', 'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6', 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7', 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN', 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT', 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN', 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2', 'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED', 'CB_PERF_SEL_CC_DCC_RDREQ_STALL', 'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL', 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY', 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB', 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY', 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB', 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY', 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB', 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY', 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB', 'CB_PERF_SEL_CC_MC_READ_REQUEST', 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', 'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL', 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY', 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB', 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY', 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB', 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY', 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB', 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY', 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB', 'CB_PERF_SEL_CC_RB_FULL', 'CB_PERF_SEL_CC_SF_FULL', 'CB_PERF_SEL_CC_SURFACE_SYNC', 'CB_PERF_SEL_CMASK_READ_DATA_0xC', 'CB_PERF_SEL_CMASK_READ_DATA_0xD', 'CB_PERF_SEL_CMASK_READ_DATA_0xE', 'CB_PERF_SEL_CMASK_READ_DATA_0xF', 'CB_PERF_SEL_CMASK_WRITE_DATA_0xC', 'CB_PERF_SEL_CMASK_WRITE_DATA_0xD', 'CB_PERF_SEL_CMASK_WRITE_DATA_0xE', 'CB_PERF_SEL_CMASK_WRITE_DATA_0xF', 'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY', 'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL', 'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED', 'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL', 'CB_PERF_SEL_CM_CACHE_FLUSH', 'CB_PERF_SEL_CM_CACHE_HIT', 'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', 'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL', 'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL', 'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL', 'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED', 'CB_PERF_SEL_CM_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CM_CACHE_STALL', 'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED', 'CB_PERF_SEL_CM_CACHE_TAG_MISS', 'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL', 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY', 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB', 'CB_PERF_SEL_CM_FC_TILE_VALID_READY', 'CB_PERF_SEL_CM_FC_TILE_VALID_READYB', 'CB_PERF_SEL_CM_MC_READ_REQUEST', 'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT', 'CB_PERF_SEL_CM_MC_WRITE_REQUEST', 'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT', 'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL', 'CB_PERF_SEL_CM_TQ_FULL', 'CB_PERF_SEL_CORE_SCLK_VLD', 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY', 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB', 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY', 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB', 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY', 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB', 'CB_PERF_SEL_DB_CB_TILE_VALID_READY', 'CB_PERF_SEL_DB_CB_TILE_VALID_READYB', 'CB_PERF_SEL_DRAWN_BUSY', 'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD', 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_DRAWN_TILE', 'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT', 'CB_PERF_SEL_EVENT', 'CB_PERF_SEL_EVENT_CACHE_FLUSH', 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', 'CB_PERF_SEL_EVENT_CONTEXT_DONE', 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', 'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY', 'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL', 'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED', 'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', 'CB_PERF_SEL_FC_CACHE_FLUSH', 'CB_PERF_SEL_FC_CACHE_HIT', 'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', 'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL', 'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL', 'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL', 'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED', 'CB_PERF_SEL_FC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_FC_CACHE_STALL', 'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED', 'CB_PERF_SEL_FC_CACHE_TAG_MISS', 'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL', 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY', 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB', 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY', 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB', 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY', 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB', 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY', 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB', 'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL', 'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED', 'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', 'CB_PERF_SEL_FC_DCC_CACHE_FLUSH', 'CB_PERF_SEL_FC_DCC_CACHE_HIT', 'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', 'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL', 'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL', 'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', 'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED', 'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_FC_DCC_CACHE_STALL', 'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED', 'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS', 'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL', 'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR', 'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT', 'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS', 'CB_PERF_SEL_FC_DOC_IS_STALLED', 'CB_PERF_SEL_FC_DOC_MRTS_COMBINED', 'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED', 'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR', 'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS', 'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS', 'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS', 'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT', 'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS', 'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL', 'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS', 'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL', 'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST', 'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT', 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST', 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT', 'CB_PERF_SEL_FC_MC_READ_REQUEST', 'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT', 'CB_PERF_SEL_FC_MC_WRITE_REQUEST', 'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT', 'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED', 'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL', 'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL', 'CB_PERF_SEL_FC_SEQUENCER_CLEAR', 'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR', 'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE', 'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS', 'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL', 'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL', 'CB_PERF_SEL_FOP_FMASK_RAW_STALL', 'CB_PERF_SEL_FOP_IN_VALIDB_READY', 'CB_PERF_SEL_FOP_IN_VALIDB_READYB', 'CB_PERF_SEL_FOP_IN_VALID_READY', 'CB_PERF_SEL_FOP_IN_VALID_READYB', 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR', 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR', 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR', 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R', 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR', 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR', 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR', 'CB_PERF_SEL_LQUAD_NO_TILE', 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY', 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB', 'CB_PERF_SEL_NONE', 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT', 'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS', 'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS', 'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS', 'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS', 'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS', 'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS', 'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', 'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS', 'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS', 'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST', 'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED', 'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE', 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE', 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE', 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE', 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE', 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE', 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE', 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE', 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE', 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE', 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE', 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE', 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE', 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE', 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE', 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE', 'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID', 'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL', 'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT', 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK', 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK', 'CB_PERF_SEL_QUAD_READS_FRAGMENT_0', 'CB_PERF_SEL_QUAD_READS_FRAGMENT_1', 'CB_PERF_SEL_QUAD_READS_FRAGMENT_2', 'CB_PERF_SEL_QUAD_READS_FRAGMENT_3', 'CB_PERF_SEL_QUAD_READS_FRAGMENT_4', 'CB_PERF_SEL_QUAD_READS_FRAGMENT_5', 'CB_PERF_SEL_QUAD_READS_FRAGMENT_6', 'CB_PERF_SEL_QUAD_READS_FRAGMENT_7', 'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT', 'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS', 'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS', 'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS', 'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS', 'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS', 'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS', 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0', 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1', 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2', 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3', 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4', 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5', 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6', 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7', 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', 'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD', 'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS', 'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK', 'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING', 'CB_PERF_SEL_RBP_SPLIT_MICROTILE', 'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK', 'CB_PERF_SEL_REG_SCLK0_VLD', 'CB_PERF_SEL_REG_SCLK1_VLD', 'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY', 'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT', 'CB_RESOLVE', 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY', 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY', 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', 'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY', 'CHUB_TC_RET_CREDITS', 'CHUB_TC_RET_CREDITS_ENUM', 'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', 'CLKGATE_SM_MODE', 'CLOCK_BRANCH_SOFT_RESET', 'CLOCK_BRANCH_SOFT_RESET_FORCE', 'CLOCK_BRANCH_SOFT_RESET_NOOP', 'CLOCK_GATING_DISABLED', 'CLOCK_GATING_DISABLED_IN_DCO', 'CLOCK_GATING_ENABLED', 'CLOCK_GATING_ENABLED_IN_DCO', 'CMASK_ADDR_COMPATIBLE', 'CMASK_ADDR_LINEAR', 'CMASK_ADDR_TILED', 'CMASK_ALPHA0_FRAG1', 'CMASK_ALPHA0_FRAG2', 'CMASK_ALPHA0_FRAG4', 'CMASK_ALPHA0_FRAGS', 'CMASK_ALPHA1_FRAG1', 'CMASK_ALPHA1_FRAG2', 'CMASK_ALPHA1_FRAG4', 'CMASK_ALPHA1_FRAGS', 'CMASK_ALPHAX_FRAG1', 'CMASK_ALPHAX_FRAG2', 'CMASK_ALPHAX_FRAG4', 'CMASK_ALPHAX_FRAGS', 'CMASK_ANY_EXPANDED', 'CMASK_CLEAR_ALL', 'CMASK_CLEAR_NONE', 'CMASK_CLEAR_ONE', 'CMASK_CLR00_F0', 'CMASK_CLR00_F1', 'CMASK_CLR00_F2', 'CMASK_CLR00_FX', 'CMASK_CLR01_F0', 'CMASK_CLR01_F1', 'CMASK_CLR01_F2', 'CMASK_CLR01_FX', 'CMASK_CLR10_F0', 'CMASK_CLR10_F1', 'CMASK_CLR10_F2', 'CMASK_CLR10_FX', 'CMASK_CLR11_F0', 'CMASK_CLR11_F1', 'CMASK_CLR11_F2', 'CMASK_CLR11_FX', 'CMD_EMBEDDED_MODE_DISABLE', 'CMD_EMBEDDED_MODE_ENABLE', 'CM_GLOBAL_PASSTHROUGH_DISBALE', 'CM_GLOBAL_PASSTHROUGH_ENABLE', 'COEF_UPDATE_COMPLETE', 'COEF_UPDATE_NOT_COMPLETE', 'COLOR_10_10_10_2', 'COLOR_10_11_11', 'COLOR_11_11_10', 'COLOR_16', 'COLOR_16_16', 'COLOR_16_16_16_16', 'COLOR_1_5_5_5', 'COLOR_24_8', 'COLOR_2_10_10_10', 'COLOR_2_10_10_10_6E4', 'COLOR_32', 'COLOR_32_32', 'COLOR_32_32_32_32', 'COLOR_4_4_4_4', 'COLOR_5_5_5_1', 'COLOR_5_6_5', 'COLOR_8', 'COLOR_8_24', 'COLOR_8_8', 'COLOR_8_8_8_8', 'COLOR_INVALID', 'COLOR_RESERVED_13', 'COLOR_RESERVED_15', 'COLOR_RESERVED_23', 'COLOR_RESERVED_24', 'COLOR_RESERVED_25', 'COLOR_RESERVED_26', 'COLOR_RESERVED_27', 'COLOR_RESERVED_28', 'COLOR_RESERVED_29', 'COLOR_RESERVED_30', 'COLOR_X24_8_32_FLOAT', 'COL_MAN_DEGAMMA_MODE', 'COL_MAN_DENORM_CLAMP_CONTROL', 'COL_MAN_DISABLE_MULTIPLE_UPDATE', 'COL_MAN_GAMUT_REMAP_MODE', 'COL_MAN_GLOBAL_PASSTHROUGH_ENABLE', 'COL_MAN_INPUTCSC_CONVERT', 'COL_MAN_INPUTCSC_MODE', 'COL_MAN_INPUTCSC_TYPE', 'COL_MAN_INPUT_GAMMA_MODE', 'COL_MAN_MULTIPLE_UPDATE', 'COL_MAN_MULTIPLE_UPDAT_EDISABLE', 'COL_MAN_OUTPUT_CSC_A', 'COL_MAN_OUTPUT_CSC_B', 'COL_MAN_OUTPUT_CSC_BYPASS', 'COL_MAN_OUTPUT_CSC_MODE', 'COL_MAN_OUTPUT_CSC_RGB', 'COL_MAN_OUTPUT_CSC_UNITY', 'COL_MAN_OUTPUT_CSC_YCrCb601', 'COL_MAN_OUTPUT_CSC_YCrCb709', 'COL_MAN_PRESCALE_MODE', 'COL_MAN_REGAMMA_MODE_A', 'COL_MAN_REGAMMA_MODE_B', 'COL_MAN_REGAMMA_MODE_BYPASS', 'COL_MAN_REGAMMA_MODE_CONTROL', 'COL_MAN_REGAMMA_MODE_ROM_A', 'COL_MAN_REGAMMA_MODE_ROM_B', 'COL_MAN_UPDATE_LOCK', 'COL_MAN_UPDATE_LOCKED', 'COL_MAN_UPDATE_UNLOCKED', 'COMB_DST_MINUS_SRC', 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', 'COMB_MIN_DST_SRC', 'COMB_SRC_MINUS_DST', 'COMPONENT_DEPTH_10BPC', 'COMPONENT_DEPTH_12BPC', 'COMPONENT_DEPTH_16BPC', 'COMPONENT_DEPTH_6BPC', 'COMPONENT_DEPTH_8BPC', 'CONFIG_128B_SWAPS', 'CONFIG_1KB_ROW', 'CONFIG_1KB_ROW_OPT', 'CONFIG_1KB_SPLIT', 'CONFIG_1KB_SWAPS', 'CONFIG_1_PIPE', 'CONFIG_256B_GROUP', 'CONFIG_256B_SWAPS', 'CONFIG_2KB_ROW', 'CONFIG_2KB_ROW_OPT', 'CONFIG_2KB_SPLIT', 'CONFIG_2_PIPE', 'CONFIG_4KB_ROW', 'CONFIG_4KB_ROW_OPT', 'CONFIG_4KB_SPLIT', 'CONFIG_4_BANK', 'CONFIG_4_PIPE', 'CONFIG_512B_GROUP', 'CONFIG_512B_SWAPS', 'CONFIG_8KB_ROW', 'CONFIG_8KB_ROW_OPT', 'CONFIG_8KB_SPLIT', 'CONFIG_8_BANK', 'CONFIG_8_PIPE', 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', 'CONFIG_SPACE2_END', 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', 'CONFIG_SPACE_START', 'CONTEXT_DONE', 'CONTEXT_SPACE_END', 'CONTEXT_SPACE_START', 'CONTEXT_SUSPEND', 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', 'CORB_READ_POINTER_RESET', 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0', 'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_PERFCOUNT_SEL', 'CPC_PERF_SEL_ALWAYS_COUNT', 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ', 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE', 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ', 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE', 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', 'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE', 'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE', 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM', 'CPF_PERFCOUNT_SEL', 'CPF_PERF_SEL_ALWAYS_COUNT', 'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE', 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', 'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR', 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', 'CPF_PERF_SEL_GRBM_DWORDS_SENT', 'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS', 'CPF_PERF_SEL_MIU_READ_REQUEST_SEND', 'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE', 'CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND', 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', 'CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPF_TAG_RAM', 'CPG_PERFCOUNT_SEL', 'CPG_PERF_SEL_ALWAYS_COUNT', 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU', 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', 'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', 'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR', 'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL', 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', 'CPG_PERF_SEL_ME_PARSER_BUSY', 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', 'CPG_PERF_SEL_MIU_READ_REQUEST_SENT', 'CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT', 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', 'CPG_PERF_SEL_RBIU_FIFO_FULL', 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', 'CPG_PERF_SEL_REGISTER_CLK_VALID', 'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS', 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM', 'CP_ALPHA_TAG_RAM_SEL', 'CP_ME_ID', 'CP_PERFMON_ENABLE_MODE', 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE', 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', 'CP_PERFMON_STATE_DISABLE_AND_RESET', 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', 'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING', 'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', 'CRTC_ADD_PIXEL', 'CRTC_ADD_PIXEL_FORCE', 'CRTC_ADD_PIXEL_NOOP', 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN', 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE', 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE', 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE', 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE', 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE', 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL', 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE', 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT', 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST', 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED', 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE', 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE', 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE', 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL', 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP', 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL', 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY', 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE', 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE', 'CRTC_CONTROL_CRTC_MASTER_EN', 'CRTC_CONTROL_CRTC_MASTER_EN_FALSE', 'CRTC_CONTROL_CRTC_MASTER_EN_TRUE', 'CRTC_CONTROL_CRTC_SOF_PULL_EN', 'CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE', 'CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE', 'CRTC_CONTROL_CRTC_START_POINT_CNTL', 'CRTC_CONTROL_CRTC_START_POINT_CNTL_DP', 'CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL', 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN', 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE', 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE', 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN', 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE', 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE', 'CRTC_CRC_CNTL_CRTC_CRC_EN', 'CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE', 'CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE', 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE', 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM', 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD', 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM', 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP', 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE', 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES', 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS', 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT', 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT', 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS', 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB', 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B', 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN', 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE', 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE', 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE', 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0', 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1', 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY', 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE', 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE', 'CRTC_DROP_PIXEL', 'CRTC_DROP_PIXEL_FORCE', 'CRTC_DROP_PIXEL_NOOP', 'CRTC_DRR_MODE_DBUF_UPDATE_MODE', 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE', 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL', 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF', 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF', 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN', 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE', 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE', 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE', 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR', 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE', 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE', 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE', 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE', 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE', 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE', 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE', 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE', 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE', 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'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON', 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0', 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1', 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2', 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW', 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW', 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA', 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER', 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER', 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB', 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK', 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE', 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE', 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR', 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE', 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE', 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE', 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE', 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY', 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR', 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE', 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE', 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE', 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR', 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE', 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE', 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE', 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE', 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE', 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED', 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA', 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB', 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR', 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE', 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE', 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE', 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR', 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE', 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE', 'CRTC_V_SYNC_A_POL', 'CRTC_V_SYNC_A_POL_HIGH', 'CRTC_V_SYNC_A_POL_LOW', 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL', 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE', 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE', 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT', 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE', 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE', 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC', 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN', 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE', 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE', 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL', 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE', 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE', 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL', 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE', 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE', 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK', 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE', 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE', 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR', 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE', 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE', 'CSDATA_ADDR_WIDTH', 'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', 'CSDATA_TYPE_EVENT', 'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', 'CSDATA_TYPE_TG', 'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', 'CS_DONE', 'CS_PARTIAL_FLUSH', 'CS_STAGE_ON', 'CmaskAddr', 'CmaskCode', 'CmaskMode', 'ColorArray', 'ColorFormat', 'ColorTransform', 'CombFunc', 'CompareFrag', 'CompareRef', 'ConservativeZExport', 'CovToShaderSel', 'DACA_SOFT_RESET', 'DACA_SOFT_RESET_0', 'DACA_SOFT_RESET_1', 'DAC_MUX_SELECT', 'DAC_MUX_SELECT_DACA', 'DAC_MUX_SELECT_DACB', 'DB_CACHE_FLUSH', 'DB_CACHE_FLUSH_AND_INV', 'DB_CACHE_FLUSH_AND_INV_EVENT', 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', 'DB_CACHE_FLUSH_TS', 'DB_CLK_SOFT_RESET', 'DB_CLK_SOFT_RESET_0', 'DB_CLK_SOFT_RESET_1', 'DB_FLUSH_AND_INV_DB_DATA_TS', 'DB_FLUSH_AND_INV_DB_META', 'DB_PEFF_SEL_prezl_tile_mem_stall', 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', 'DB_PERF_SEL_CB_DB_rdreq_sends', 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', 'DB_PERF_SEL_CB_DB_wrreq_sends', 'DB_PERF_SEL_DB_CB_lquad_busy', 'DB_PERF_SEL_DB_CB_lquad_double_format', 'DB_PERF_SEL_DB_CB_lquad_export_quads', 'DB_PERF_SEL_DB_CB_lquad_fast_format', 'DB_PERF_SEL_DB_CB_lquad_quads', 'DB_PERF_SEL_DB_CB_lquad_sends', 'DB_PERF_SEL_DB_CB_lquad_slow_format', 'DB_PERF_SEL_DB_CB_lquad_stalls', 'DB_PERF_SEL_DB_CB_rdret_ack', 'DB_PERF_SEL_DB_CB_rdret_nack', 'DB_PERF_SEL_DB_CB_tile_busy', 'DB_PERF_SEL_DB_CB_tile_sends', 'DB_PERF_SEL_DB_CB_tile_stalls', 'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack', 'DB_PERF_SEL_DB_SC_quad_busy', 'DB_PERF_SEL_DB_SC_quad_double_quad', 'DB_PERF_SEL_DB_SC_quad_lit_quad', 'DB_PERF_SEL_DB_SC_quad_sends', 'DB_PERF_SEL_DB_SC_quad_stalls', 'DB_PERF_SEL_DB_SC_quad_tiles', 'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled', 'DB_PERF_SEL_DB_SC_tile_df_stalls', 'DB_PERF_SEL_DB_SC_tile_fast_ops', 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', 'DB_PERF_SEL_DB_SC_tile_hier_kill', 'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends', 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', 'DB_PERF_SEL_DB_SC_tile_stalls', 'DB_PERF_SEL_DB_SC_tile_tile_rate', 'DB_PERF_SEL_DB_SC_tile_tiles', 'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream', 'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO', 'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow', 'DB_PERF_SEL_DFSM_cycles_above_watermark', 'DB_PERF_SEL_DFSM_evicted_squads_above_watermark', 'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark', 'DB_PERF_SEL_DFSM_full_cleared_squads_out', 'DB_PERF_SEL_DFSM_fully_cleared_pixels_out', 'DB_PERF_SEL_DFSM_fully_cleared_quads_out', 'DB_PERF_SEL_DFSM_lit_pixels_in', 'DB_PERF_SEL_DFSM_lit_samples_in', 'DB_PERF_SEL_DFSM_lit_samples_out', 'DB_PERF_SEL_DFSM_quads_in', 'DB_PERF_SEL_DFSM_squads_in', 'DB_PERF_SEL_DFSM_stalled_by_downstream', 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', 'DB_PERF_SEL_Depth_Tile_Cache_busy', 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', 'DB_PERF_SEL_Depth_Tile_Cache_event', 'DB_PERF_SEL_Depth_Tile_Cache_flushes', 'DB_PERF_SEL_Depth_Tile_Cache_hits', 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', 'DB_PERF_SEL_Depth_Tile_Cache_misses', 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', 'DB_PERF_SEL_Depth_Tile_Cache_sends', 'DB_PERF_SEL_Depth_Tile_Cache_starves', 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', 'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy', 'DB_PERF_SEL_Plane_Cache_flushes', 'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits', 'DB_PERF_SEL_Plane_Cache_misses', 'DB_PERF_SEL_Plane_Cache_starves', 'DB_PERF_SEL_PostZ_Samples_failing_DB', 'DB_PERF_SEL_PostZ_Samples_failing_S', 'DB_PERF_SEL_PostZ_Samples_failing_Z', 'DB_PERF_SEL_PostZ_Samples_passing_Z', 'DB_PERF_SEL_PreZ_Samples_failing_DB', 'DB_PERF_SEL_PreZ_Samples_failing_S', 'DB_PERF_SEL_PreZ_Samples_failing_Z', 'DB_PERF_SEL_PreZ_Samples_passing_Z', 'DB_PERF_SEL_SC_DB_quad_busy', 'DB_PERF_SEL_SC_DB_quad_killed_tiles', 'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_sends', 'DB_PERF_SEL_SC_DB_quad_squads', 'DB_PERF_SEL_SC_DB_quad_tiles', 'DB_PERF_SEL_SC_DB_tile_busy', 'DB_PERF_SEL_SC_DB_tile_covered', 'DB_PERF_SEL_SC_DB_tile_events', 'DB_PERF_SEL_SC_DB_tile_sends', 'DB_PERF_SEL_SC_DB_tile_stalls', 'DB_PERF_SEL_SC_DB_tile_tiles', 'DB_PERF_SEL_SH_quads_outstanding_sum', 'DB_PERF_SEL_SX_DB_quad_busy', 'DB_PERF_SEL_SX_DB_quad_double_format', 'DB_PERF_SEL_SX_DB_quad_export_quads', 'DB_PERF_SEL_SX_DB_quad_exports', 'DB_PERF_SEL_SX_DB_quad_fast_format', 'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads', 'DB_PERF_SEL_SX_DB_quad_sends', 'DB_PERF_SEL_SX_DB_quad_slow_format', 'DB_PERF_SEL_SX_DB_quad_stalls', 'DB_PERF_SEL_Stencil_Cache_flushes', 'DB_PERF_SEL_Stencil_Cache_frees', 'DB_PERF_SEL_Stencil_Cache_hits', 'DB_PERF_SEL_Stencil_Cache_misses', 'DB_PERF_SEL_Stencil_Cache_starves', 'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits', 'DB_PERF_SEL_Tile_Cache_mem_return_starve', 'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves', 'DB_PERF_SEL_Tile_Cache_surface_stall', 'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes', 'DB_PERF_SEL_Z_Cache_pmask_hits', 'DB_PERF_SEL_Z_Cache_pmask_misses', 'DB_PERF_SEL_Z_Cache_pmask_starves', 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', 'DB_PERF_SEL_Z_Cache_separate_Z_hits', 'DB_PERF_SEL_Z_Cache_separate_Z_misses', 'DB_PERF_SEL_Z_Cache_separate_Z_starves', 'DB_PERF_SEL_clock_main_active', 'DB_PERF_SEL_clock_mem_export_active', 'DB_PERF_SEL_clock_reg_active', 'DB_PERF_SEL_depth_bounds_qtiles_culled', 'DB_PERF_SEL_di_dt_stall', 'DB_PERF_SEL_dk_squad_busy', 'DB_PERF_SEL_dk_squad_sends', 'DB_PERF_SEL_dk_squad_stalls', 'DB_PERF_SEL_dk_tile_busy', 'DB_PERF_SEL_dk_tile_quad_starves', 'DB_PERF_SEL_dk_tile_sends', 'DB_PERF_SEL_dk_tile_stalls', 'DB_PERF_SEL_dkg_tile_rate_tile', 'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall', 'DB_PERF_SEL_dtt_sm_slot_stall', 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', 'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward', 'DB_PERF_SEL_esr_eot_fwd_holding_squad', 'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall', 'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_sqq_busy', 'DB_PERF_SEL_esr_ps_sqq_stall', 'DB_PERF_SEL_esr_ps_src_in_sends', 'DB_PERF_SEL_esr_ps_src_in_squads', 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', 'DB_PERF_SEL_esr_ps_src_in_stall', 'DB_PERF_SEL_esr_ps_src_in_tile_rate', 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', 'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_sqq_zi_busy', 'DB_PERF_SEL_esr_sqq_zi_stall', 'DB_PERF_SEL_etr_out_busy', 'DB_PERF_SEL_etr_out_cb_tile_stall', 'DB_PERF_SEL_etr_out_esr_stall', 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', 'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane', 'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane', 'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane', 'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane', 'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane', 'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane', 'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane', 'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane', 'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed', 'DB_PERF_SEL_flush_compressed_stencil', 'DB_PERF_SEL_flush_expanded_stencil', 'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4', 'DB_PERF_SEL_flush_single_stencil', 'DB_PERF_SEL_his_qtiles_culled', 'DB_PERF_SEL_hiz_qtiles_culled', 'DB_PERF_SEL_hiz_tc_read_starved', 'DB_PERF_SEL_hiz_tc_write_stall', 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', 'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall', 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', 'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall', 'DB_PERF_SEL_planes_flushed', 'DB_PERF_SEL_postzl_full_launch', 'DB_PERF_SEL_postzl_partial_launch', 'DB_PERF_SEL_postzl_partial_waiting', 'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall', 'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall', 'DB_PERF_SEL_postzl_src_in_sends', 'DB_PERF_SEL_postzl_src_in_squads', 'DB_PERF_SEL_postzl_src_in_squads_unrolled', 'DB_PERF_SEL_postzl_src_in_stall', 'DB_PERF_SEL_postzl_src_in_tile_rate', 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', 'DB_PERF_SEL_postzl_src_out_stall', 'DB_PERF_SEL_postzl_tile_init_stall', 'DB_PERF_SEL_postzl_tile_mem_stall', 'DB_PERF_SEL_prezl_src_in_sends', 'DB_PERF_SEL_prezl_src_in_squads', 'DB_PERF_SEL_prezl_src_in_squads_unrolled', 'DB_PERF_SEL_prezl_src_in_stall', 'DB_PERF_SEL_prezl_src_in_tile_rate', 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', 'DB_PERF_SEL_prezl_src_out_stall', 'DB_PERF_SEL_prezl_tile_init_stall', 'DB_PERF_SEL_qc_busy', 'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall', 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc', 'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy', 'DB_PERF_SEL_quad_rd_mi_stall', 'DB_PERF_SEL_quad_rd_panic', 'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends', 'DB_PERF_SEL_quad_rd_tag_stall', 'DB_PERF_SEL_quad_rdret_busy', 'DB_PERF_SEL_quad_rdret_sends', 'DB_PERF_SEL_quad_wr_acks', 'DB_PERF_SEL_quad_wr_busy', 'DB_PERF_SEL_quad_wr_coherency_stall', 'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends', 'DB_PERF_SEL_reZ_waiting_for_postZ_done', 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', 'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start', 'DB_PERF_SEL_tcp_dispatcher_flushes', 'DB_PERF_SEL_tcp_dispatcher_reads', 'DB_PERF_SEL_tcp_prefetcher_flushes', 'DB_PERF_SEL_tcp_prefetcher_reads', 'DB_PERF_SEL_tcp_preloader_flushes', 'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends', 'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends', 'DB_PERF_SEL_tiles_compressed_to_decompressed', 'DB_PERF_SEL_tiles_decomp_on_expclear', 'DB_PERF_SEL_tiles_s_clear_on_expclear', 'DB_PERF_SEL_tiles_stencil_fully_summarized', 'DB_PERF_SEL_tiles_z_clear_on_expclear', 'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy', 'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events', 'DB_PERF_SEL_tl_expand_squads', 'DB_PERF_SEL_tl_flush_expand_squads', 'DB_PERF_SEL_tl_in_fast_z_stall', 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', 'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads', 'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads', 'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads', 'DB_PERF_SEL_tl_preZ_squads', 'DB_PERF_SEL_tl_stencil_locked_stall', 'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads', 'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall', 'DB_PERF_SEL_tl_z_fetch_stall', 'DB_PERF_SEL_ts_tc_update_stall', 'DB_PERF_SEL_tsc_insert_summarize_stall', 'DB_PERF_SEL_zf_plane_multicycle', 'DCCG_AUDIO_DTO0_SOURCE_SEL', 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0', 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1', 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2', 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3', 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4', 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5', 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', 'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1', 'DCCG_AUDIO_DTO_SEL', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', 'DCCG_AUDIO_DTO_USE_512FBR_DTO', 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DBG_BLOCK_SEL', 'DCCG_DBG_BLOCK_SEL_DCCG', 'DCCG_DBG_BLOCK_SEL_PMON', 'DCCG_DBG_BLOCK_SEL_PMON2', 'DCCG_DBG_EN', 'DCCG_DBG_EN_DISABLE', 'DCCG_DBG_EN_ENABLE', 'DCCG_DEEP_COLOR_CNTL', 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE', 'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN', 'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET', 'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP', 'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', 'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_CRTC_SELECT', 'DCCG_PERF_MODE_HSYNC', 'DCCG_PERF_MODE_HSYNC_NOOP', 'DCCG_PERF_MODE_HSYNC_START', 'DCCG_PERF_MODE_VSYNC', 'DCCG_PERF_MODE_VSYNC_NOOP', 'DCCG_PERF_MODE_VSYNC_START', 'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START', 'DCCG_PERF_SEL_CRTC0', 'DCCG_PERF_SEL_CRTC1', 'DCCG_PERF_SEL_CRTC2', 'DCCG_PERF_SEL_CRTC3', 'DCCG_PERF_SEL_CRTC4', 'DCCG_PERF_SEL_CRTC5', 'DCC_CT_AUTO', 'DCC_CT_NONE', 'DCIOCHIP_2BIT_DISABLE', 'DCIOCHIP_2BIT_ENABLE', 'DCIOCHIP_4BIT_DISABLE', 'DCIOCHIP_4BIT_ENABLE', 'DCIOCHIP_5BIT_DISABLE', 'DCIOCHIP_5BIT_ENABLE', 'DCIOCHIP_AUXSLAVE_PAD_MODE', 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX', 'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C', 'DCIOCHIP_AUX_CSEL0P9', 'DCIOCHIP_AUX_CSEL1P1', 'DCIOCHIP_AUX_CSEL_DEC0P9', 'DCIOCHIP_AUX_CSEL_DEC1P0', 'DCIOCHIP_AUX_CSEL_INC1P0', 'DCIOCHIP_AUX_CSEL_INC1P1', 'DCIOCHIP_AUX_FALLSLEWSEL', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_RSEL0P9', 'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9', 'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0', 'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL', 'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS', 'DCIOCHIP_DVO_VREFPON', 'DCIOCHIP_DVO_VREFPON_DISABLE', 'DCIOCHIP_DVO_VREFPON_ENABLE', 'DCIOCHIP_DVO_VREFSEL', 'DCIOCHIP_DVO_VREFSEL_EXTERNAL', 'DCIOCHIP_DVO_VREFSEL_ONCHIP', 'DCIOCHIP_ENABLE_2BIT', 'DCIOCHIP_ENABLE_4BIT', 'DCIOCHIP_ENABLE_5BIT', 'DCIOCHIP_GPIO_I2C_DISABLE', 'DCIOCHIP_GPIO_I2C_DRIVE', 'DCIOCHIP_GPIO_I2C_DRIVE_HIGH', 'DCIOCHIP_GPIO_I2C_DRIVE_LOW', 'DCIOCHIP_GPIO_I2C_EN', 'DCIOCHIP_GPIO_I2C_ENABLE', 'DCIOCHIP_GPIO_I2C_MASK', 'DCIOCHIP_GPIO_I2C_MASK_DISABLE', 'DCIOCHIP_GPIO_I2C_MASK_ENABLE', 'DCIOCHIP_GPIO_MASK_EN', 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL', 'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED', 'DCIOCHIP_INVERT', 'DCIOCHIP_MASIK_5BIT_DISABLE', 'DCIOCHIP_MASIK_5BIT_ENABLE', 'DCIOCHIP_MASK', 'DCIOCHIP_MASK_2BIT', 'DCIOCHIP_MASK_2BIT_DISABLE', 'DCIOCHIP_MASK_2BIT_ENABLE', 'DCIOCHIP_MASK_4BIT', 'DCIOCHIP_MASK_4BIT_DISABLE', 'DCIOCHIP_MASK_4BIT_ENABLE', 'DCIOCHIP_MASK_5BIT', 'DCIOCHIP_MASK_DISABLE', 'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE', 'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN', 'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW', 'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT', 'DCIOCHIP_REF_27_SRC_SEL', 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', 'DCIOCHIP_SPDIF1_IMODE', 'DCIOCHIP_SPDIF1_IMODE_OE_A', 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO', 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE', 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN', 'DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT', 'DCIO_BL_PWM_CNTL_BL_PWM_EN', 'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', 'DCIO_BL_PWM_DISABLE', 'DCIO_BL_PWM_ENABLE', 'DCIO_BL_PWM_FRACTIONAL_DISABLE', 'DCIO_BL_PWM_FRACTIONAL_ENABLE', 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL', 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN', 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN', 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', 'DCIO_BL_PWM_GRP1_REG_LOCK', 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE', 'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE', 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START', 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', 'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE', 'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE', 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL', 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM', 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL', 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', 'DCIO_DACA_SOFT_RESET', 'DCIO_DACA_SOFT_RESET_ASSERT', 'DCIO_DACA_SOFT_RESET_DEASSERT', 'DCIO_DBG_ASYNC_4BIT_SEL', 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 'DCIO_DBG_ASYNC_BLOCK_SEL', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCO', 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', 'DCIO_DCO_DCFE_EXT_VSYNC_MUX', 'DCIO_DCO_EXT_VSYNC_MASK', 'DCIO_DCRXPHY_SOFT_RESET', 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', 'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN', 'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN', 'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN', 'DCIO_DC_GENERICA_SEL', 'DCIO_DC_GENERICB_SEL', 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL', 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL', 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL', 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL', 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL', 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL', 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP', 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN', 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS', 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE', 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE', 'DCIO_DC_GPIO_MACRO_DEBUG', 'DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF', 'DCIO_DC_GPIO_MACRO_DEBUG_NORMAL', 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2', 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3', 'DCIO_DC_GPIO_VIP_DEBUG', 'DCIO_DC_GPIO_VIP_DEBUG_CG_BIG', 'DCIO_DC_GPIO_VIP_DEBUG_NORMAL', 'DCIO_DC_GPU_TIMER_READ_SELECT', 'DCIO_DC_GPU_TIMER_START_POSITION', 'DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS', 'DCIO_DC_PAD_EXTERN_SIG_SEL', 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK', 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA', 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK', 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA', 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA', 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB', 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC', 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK', 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC', 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1', 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2', 'DCIO_DC_PAD_EXTERN_SIG_SEL_MVP', 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0', 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1', 'DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL', 'DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA', 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL', 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL', 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE', 'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK', 'DCIO_DPCS_INTERRUPT_TYPE', 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', 'DCIO_DPHY_LANE_SEL', 'DCIO_DPHY_LANE_SEL_LANE0', 'DCIO_DPHY_LANE_SEL_LANE1', 'DCIO_DPHY_LANE_SEL_LANE2', 'DCIO_DPHY_LANE_SEL_LANE3', 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 'DCIO_DSYNC_SOFT_RESET', 'DCIO_DSYNC_SOFT_RESET_ASSERT', 'DCIO_DSYNC_SOFT_RESET_DEASSERT', 'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE', 'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT', 'DCIO_EXT_VSYNC_MASK_NONE', 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', 'DCIO_EXT_VSYNC_MASK_PIPE0', 'DCIO_EXT_VSYNC_MASK_PIPE1', 'DCIO_EXT_VSYNC_MASK_PIPE2', 'DCIO_EXT_VSYNC_MASK_PIPE3', 'DCIO_EXT_VSYNC_MASK_PIPE4', 'DCIO_EXT_VSYNC_MASK_PIPE5', 'DCIO_EXT_VSYNC_MUX_CRTC0', 'DCIO_EXT_VSYNC_MUX_CRTC1', 'DCIO_EXT_VSYNC_MUX_CRTC2', 'DCIO_EXT_VSYNC_MUX_CRTC3', 'DCIO_EXT_VSYNC_MUX_CRTC4', 'DCIO_EXT_VSYNC_MUX_CRTC5', 'DCIO_EXT_VSYNC_MUX_GENERICB', 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', 'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER', 'DCIO_GENERICA_SEL_DACA_PIXCLK', 'DCIO_GENERICA_SEL_DACA_STEREOSYNC', 'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER', 'DCIO_GENERICA_SEL_DACB_PIXCLK', 'DCIO_GENERICA_SEL_DVOA_CTL3', 'DCIO_GENERICA_SEL_DVOA_STEREOSYNC', 'DCIO_GENERICA_SEL_GENERICA_DCCG', 'DCIO_GENERICA_SEL_GENERICA_DPRX', 'DCIO_GENERICA_SEL_GENERICB_DPRX', 'DCIO_GENERICA_SEL_P1_PLLCLK', 'DCIO_GENERICA_SEL_P2_PLLCLK', 'DCIO_GENERICA_SEL_STEREOSYNC', 'DCIO_GENERICA_SEL_SYNCEN', 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK', 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2', 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK', 'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK', 'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER', 'DCIO_GENERICB_SEL_DACA_PIXCLK', 'DCIO_GENERICB_SEL_DACA_STEREOSYNC', 'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER', 'DCIO_GENERICB_SEL_DACB_PIXCLK', 'DCIO_GENERICB_SEL_DVOA_CTL3', 'DCIO_GENERICB_SEL_DVOA_STEREOSYNC', 'DCIO_GENERICB_SEL_GENERICB_DCCG', 'DCIO_GENERICB_SEL_P1_PLLCLK', 'DCIO_GENERICB_SEL_P2_PLLCLK', 'DCIO_GENERICB_SEL_STEREOSYNC', 'DCIO_GENERICB_SEL_SYNCEN', 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK', 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2', 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK', 'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK', 'DCIO_GENLK_CLK_GSL_MASK', 'DCIO_GENLK_CLK_GSL_MASK_NO', 'DCIO_GENLK_CLK_GSL_MASK_STEREO', 'DCIO_GENLK_CLK_GSL_MASK_TIMING', 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', 'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO', 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM', 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM', 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE', 'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37', 'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29', 'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31', 'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35', 'DCIO_GSL0_GLOBAL_UNLOCK_SEL', 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK', 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION', 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', 'DCIO_GSL0_TIMING_SYNC_SEL', 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK', 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC', 'DCIO_GSL0_TIMING_SYNC_SEL_PIPE', 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A', 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B', 'DCIO_GSL1_GLOBAL_UNLOCK_SEL', 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK', 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION', 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', 'DCIO_GSL1_TIMING_SYNC_SEL', 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK', 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC', 'DCIO_GSL1_TIMING_SYNC_SEL_PIPE', 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A', 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B', 'DCIO_GSL2_GLOBAL_UNLOCK_SEL', 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK', 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION', 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', 'DCIO_GSL2_TIMING_SYNC_SEL', 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK', 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC', 'DCIO_GSL2_TIMING_SYNC_SEL_PIPE', 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A', 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B', 'DCIO_GSL_SEL', 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1', 'DCIO_GSL_SEL_GROUP_2', 'DCIO_GSL_VSYNC_SEL', 'DCIO_GSL_VSYNC_SEL_PIPE0', 'DCIO_GSL_VSYNC_SEL_PIPE1', 'DCIO_GSL_VSYNC_SEL_PIPE2', 'DCIO_GSL_VSYNC_SEL_PIPE3', 'DCIO_GSL_VSYNC_SEL_PIPE4', 'DCIO_GSL_VSYNC_SEL_PIPE5', 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', 'DCIO_IMPCAL_STEP_DELAY', 'DCIO_IMPCAL_STEP_DELAY_10us', 'DCIO_IMPCAL_STEP_DELAY_11us', 'DCIO_IMPCAL_STEP_DELAY_12us', 'DCIO_IMPCAL_STEP_DELAY_13us', 'DCIO_IMPCAL_STEP_DELAY_14us', 'DCIO_IMPCAL_STEP_DELAY_15us', 'DCIO_IMPCAL_STEP_DELAY_16us', 'DCIO_IMPCAL_STEP_DELAY_1us', 'DCIO_IMPCAL_STEP_DELAY_2us', 'DCIO_IMPCAL_STEP_DELAY_3us', 'DCIO_IMPCAL_STEP_DELAY_4us', 'DCIO_IMPCAL_STEP_DELAY_5us', 'DCIO_IMPCAL_STEP_DELAY_6us', 'DCIO_IMPCAL_STEP_DELAY_7us', 'DCIO_IMPCAL_STEP_DELAY_8us', 'DCIO_IMPCAL_STEP_DELAY_9us', 'DCIO_LVTMA_BLON_OFF', 'DCIO_LVTMA_BLON_ON', 'DCIO_LVTMA_BLON_POL_INVERT', 'DCIO_LVTMA_BLON_POL_NON_INVERT', 'DCIO_LVTMA_DIGON_OFF', 'DCIO_LVTMA_DIGON_ON', 'DCIO_LVTMA_DIGON_POL_INVERT', 'DCIO_LVTMA_DIGON_POL_NON_INVERT', 'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN', 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON', 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL', 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON', 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL', 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL', 'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE', 'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN', 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE', 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE', 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF', 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON', 'DCIO_LVTMA_SYNCEN_POL_INVERT', 'DCIO_LVTMA_SYNCEN_POL_NON_INVERT', 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON', 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE', 'DCIO_MVP_PIXEL_SRC_STATUS_CRTC', 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA', 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE', 'DCIO_MVP_PIXEL_SRC_STATUS_LB', 'DCIO_SWAPLOCK_A_GSL_MASK', 'DCIO_SWAPLOCK_A_GSL_MASK_NO', 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK', 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK', 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SCLK', 'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK', 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK', 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK', 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK', 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK', 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK', 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK', 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHYLPA_FBDIV_CLK', 'DCIO_UNIPHYLPA_FBDIV_SSC_CLK', 'DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2', 'DCIO_UNIPHYLPA_TEST_REFDIV_CLK', 'DCIO_UNIPHYLPB_FBDIV_CLK', 'DCIO_UNIPHYLPB_FBDIV_SSC_CLK', 'DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2', 'DCIO_UNIPHYLPB_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED', 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE', 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL', 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT', 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK', 'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION', 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS', 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS', 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS', 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS', 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS', 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS', 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS', 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS', 'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE', 'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT', 'DCIO_VIP_MUX_EN_DVO', 'DCIO_VIP_MUX_EN_VIP', 'DCO_DBG_BLOCK_SEL', 'DCO_DBG_BLOCK_SEL_ABM', 'DCO_DBG_BLOCK_SEL_AUDIO_OUT', 'DCO_DBG_BLOCK_SEL_AUX0', 'DCO_DBG_BLOCK_SEL_AUX1', 'DCO_DBG_BLOCK_SEL_AUX2', 'DCO_DBG_BLOCK_SEL_AUX3', 'DCO_DBG_BLOCK_SEL_AUX4', 'DCO_DBG_BLOCK_SEL_AUX5', 'DCO_DBG_BLOCK_SEL_DAC', 'DCO_DBG_BLOCK_SEL_DCO', 'DCO_DBG_BLOCK_SEL_DIGA', 'DCO_DBG_BLOCK_SEL_DIGB', 'DCO_DBG_BLOCK_SEL_DIGC', 'DCO_DBG_BLOCK_SEL_DIGD', 'DCO_DBG_BLOCK_SEL_DIGE', 'DCO_DBG_BLOCK_SEL_DIGF', 'DCO_DBG_BLOCK_SEL_DIGFE_A', 'DCO_DBG_BLOCK_SEL_DIGFE_B', 'DCO_DBG_BLOCK_SEL_DIGFE_C', 'DCO_DBG_BLOCK_SEL_DIGFE_D', 'DCO_DBG_BLOCK_SEL_DIGFE_E', 'DCO_DBG_BLOCK_SEL_DIGFE_F', 'DCO_DBG_BLOCK_SEL_DIGFE_G', 'DCO_DBG_BLOCK_SEL_DIGG', 'DCO_DBG_BLOCK_SEL_DIGLPA', 'DCO_DBG_BLOCK_SEL_DIGLPB', 'DCO_DBG_BLOCK_SEL_DIGLPFEA', 'DCO_DBG_BLOCK_SEL_DIGLPFEB', 'DCO_DBG_BLOCK_SEL_DPA', 'DCO_DBG_BLOCK_SEL_DPB', 'DCO_DBG_BLOCK_SEL_DPC', 'DCO_DBG_BLOCK_SEL_DPD', 'DCO_DBG_BLOCK_SEL_DPE', 'DCO_DBG_BLOCK_SEL_DPF', 'DCO_DBG_BLOCK_SEL_DPFE_A', 'DCO_DBG_BLOCK_SEL_DPFE_B', 'DCO_DBG_BLOCK_SEL_DPFE_C', 'DCO_DBG_BLOCK_SEL_DPFE_D', 'DCO_DBG_BLOCK_SEL_DPFE_E', 'DCO_DBG_BLOCK_SEL_DPFE_F', 'DCO_DBG_BLOCK_SEL_DPFE_G', 'DCO_DBG_BLOCK_SEL_DPG', 'DCO_DBG_BLOCK_SEL_DPLPA', 'DCO_DBG_BLOCK_SEL_DPLPB', 'DCO_DBG_BLOCK_SEL_DPLPFEA', 'DCO_DBG_BLOCK_SEL_DPLPFEB', 'DCO_DBG_BLOCK_SEL_DVO', 'DCO_DBG_BLOCK_SEL_FMT0', 'DCO_DBG_BLOCK_SEL_FMT1', 'DCO_DBG_BLOCK_SEL_FMT2', 'DCO_DBG_BLOCK_SEL_FMT3', 'DCO_DBG_BLOCK_SEL_FMT4', 'DCO_DBG_BLOCK_SEL_FMT5', 'DCO_DBG_BLOCK_SEL_MVP', 'DCO_DBG_BLOCK_SEL_PERFMON_DCO', 'DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE', 'DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', 'DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', 'DCP_ALPHA_ROUND_TRUNC_MODE', 'DCP_ALPHA_ROUND_TRUNC_MODE_ROUND', 'DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC', 'DCP_CRC_ENABLE', 'DCP_CRC_ENABLE_FALSE', 'DCP_CRC_ENABLE_TRUE', 'DCP_CRC_LINE_SEL', 'DCP_CRC_LINE_SEL_BOTH', 'DCP_CRC_LINE_SEL_EVEN', 'DCP_CRC_LINE_SEL_ODD', 'DCP_CRC_LINE_SEL_RESERVED', 'DCP_CRC_SOURCE_SEL', 'DCP_CRC_SOURCE_SEL_INPUT_H32', 'DCP_CRC_SOURCE_SEL_INPUT_L32', 'DCP_CRC_SOURCE_SEL_OUTPUT_CNTL', 'DCP_CRC_SOURCE_SEL_OUTPUT_PIX', 'DCP_CUR2_INV_TRANS_CLAMP', 'DCP_CUR2_INV_TRANS_CLAMP_FALSE', 'DCP_CUR2_INV_TRANS_CLAMP_TRUE', 'DCP_CURSOR_2X_MAGNIFY', 'DCP_CURSOR_2X_MAGNIFY_FALSE', 'DCP_CURSOR_2X_MAGNIFY_TRUE', 'DCP_CURSOR_ALPHA_BLND_ENA', 'DCP_CURSOR_ALPHA_BLND_ENA_FALSE', 'DCP_CURSOR_ALPHA_BLND_ENA_TRUE', 'DCP_CURSOR_DEGAMMA_MODE', 'DCP_CURSOR_DEGAMMA_MODE_BYPASS', 'DCP_CURSOR_DEGAMMA_MODE_RESERVED', 'DCP_CURSOR_DEGAMMA_MODE_ROMA', 'DCP_CURSOR_DEGAMMA_MODE_ROMB', 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE', 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE', 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE', 'DCP_CURSOR_EN', 'DCP_CURSOR_EN_FALSE', 'DCP_CURSOR_EN_TRUE', 'DCP_CURSOR_FORCE_MC_ON', 'DCP_CURSOR_FORCE_MC_ON_FALSE', 'DCP_CURSOR_FORCE_MC_ON_TRUE', 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM', 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE', 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO', 'DCP_CURSOR_MODE', 'DCP_CURSOR_MODE_24BPP_1BIT', 'DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI', 'DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI', 'DCP_CURSOR_MODE_MONO_2BPP', 'DCP_CURSOR_STEREO_EN', 'DCP_CURSOR_STEREO_EN_FALSE', 'DCP_CURSOR_STEREO_EN_TRUE', 'DCP_CURSOR_STEREO_OFFSET_YNX', 'DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION', 'DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION', 'DCP_CURSOR_UPDATE_LOCK', 'DCP_CURSOR_UPDATE_LOCK_FALSE', 'DCP_CURSOR_UPDATE_LOCK_TRUE', 'DCP_CURSOR_UPDATE_PENDING', 'DCP_CURSOR_UPDATE_PENDING_FALSE', 'DCP_CURSOR_UPDATE_PENDING_TRUE', 'DCP_CURSOR_UPDATE_STEREO_MODE', 'DCP_CURSOR_UPDATE_STEREO_MODE_BOTH', 'DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY', 'DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY', 'DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED', 'DCP_CURSOR_UPDATE_TAKEN', 'DCP_CURSOR_UPDATE_TAKEN_FALSE', 'DCP_CURSOR_UPDATE_TAKEN_TRUE', 'DCP_CURSOR_URGENT_CONTROL', 'DCP_CURSOR_URGENT_CONTROL_MODE_0', 'DCP_CURSOR_URGENT_CONTROL_MODE_1', 'DCP_CURSOR_URGENT_CONTROL_MODE_2', 'DCP_CURSOR_URGENT_CONTROL_MODE_3', 'DCP_CURSOR_URGENT_CONTROL_MODE_4', 'DCP_CUR_INV_TRANS_CLAMP', 'DCP_CUR_INV_TRANS_CLAMP_FALSE', 'DCP_CUR_INV_TRANS_CLAMP_TRUE', 'DCP_CUR_REQUEST_FILTER_DIS', 'DCP_CUR_REQUEST_FILTER_DIS_FALSE', 'DCP_CUR_REQUEST_FILTER_DIS_TRUE', 'DCP_DC_LUT_AUTOFILL', 'DCP_DC_LUT_AUTOFILL_DONE', 'DCP_DC_LUT_AUTOFILL_DONE_FALSE', 'DCP_DC_LUT_AUTOFILL_DONE_TRUE', 'DCP_DC_LUT_AUTOFILL_FALSE', 'DCP_DC_LUT_AUTOFILL_TRUE', 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN', 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE', 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE', 'DCP_DC_LUT_DATA_B_FORMAT', 'DCP_DC_LUT_DATA_B_FORMAT_S1P10', 'DCP_DC_LUT_DATA_B_FORMAT_U0P10', 'DCP_DC_LUT_DATA_B_FORMAT_U0P12', 'DCP_DC_LUT_DATA_B_FORMAT_U1P11', 'DCP_DC_LUT_DATA_B_SIGNED_EN', 'DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE', 'DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE', 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN', 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE', 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE', 'DCP_DC_LUT_DATA_G_FORMAT', 'DCP_DC_LUT_DATA_G_FORMAT_S1P10', 'DCP_DC_LUT_DATA_G_FORMAT_U0P10', 'DCP_DC_LUT_DATA_G_FORMAT_U0P12', 'DCP_DC_LUT_DATA_G_FORMAT_U1P11', 'DCP_DC_LUT_DATA_G_SIGNED_EN', 'DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE', 'DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE', 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN', 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE', 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE', 'DCP_DC_LUT_DATA_R_FORMAT', 'DCP_DC_LUT_DATA_R_FORMAT_S1P10', 'DCP_DC_LUT_DATA_R_FORMAT_U0P10', 'DCP_DC_LUT_DATA_R_FORMAT_U0P12', 'DCP_DC_LUT_DATA_R_FORMAT_U1P11', 'DCP_DC_LUT_DATA_R_SIGNED_EN', 'DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE', 'DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE', 'DCP_DC_LUT_INC_B', 'DCP_DC_LUT_INC_B_128', 'DCP_DC_LUT_INC_B_16', 'DCP_DC_LUT_INC_B_2', 'DCP_DC_LUT_INC_B_256', 'DCP_DC_LUT_INC_B_32', 'DCP_DC_LUT_INC_B_4', 'DCP_DC_LUT_INC_B_512', 'DCP_DC_LUT_INC_B_64', 'DCP_DC_LUT_INC_B_8', 'DCP_DC_LUT_INC_B_NA', 'DCP_DC_LUT_INC_G', 'DCP_DC_LUT_INC_G_128', 'DCP_DC_LUT_INC_G_16', 'DCP_DC_LUT_INC_G_2', 'DCP_DC_LUT_INC_G_256', 'DCP_DC_LUT_INC_G_32', 'DCP_DC_LUT_INC_G_4', 'DCP_DC_LUT_INC_G_512', 'DCP_DC_LUT_INC_G_64', 'DCP_DC_LUT_INC_G_8', 'DCP_DC_LUT_INC_G_NA', 'DCP_DC_LUT_INC_R', 'DCP_DC_LUT_INC_R_128', 'DCP_DC_LUT_INC_R_16', 'DCP_DC_LUT_INC_R_2', 'DCP_DC_LUT_INC_R_256', 'DCP_DC_LUT_INC_R_32', 'DCP_DC_LUT_INC_R_4', 'DCP_DC_LUT_INC_R_512', 'DCP_DC_LUT_INC_R_64', 'DCP_DC_LUT_INC_R_8', 'DCP_DC_LUT_INC_R_NA', 'DCP_DC_LUT_RW_MODE', 'DCP_DC_LUT_RW_MODE_256_ENTRY', 'DCP_DC_LUT_RW_MODE_PWL', 'DCP_DC_LUT_VGA_ACCESS_ENABLE', 'DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE', 'DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE', 'DCP_DENORM_14BIT_OUT', 'DCP_DENORM_14BIT_OUT_FALSE', 'DCP_DENORM_14BIT_OUT_TRUE', 'DCP_DENORM_MODE', 'DCP_DENORM_MODE_10BIT', 'DCP_DENORM_MODE_11BIT', 'DCP_DENORM_MODE_12BIT', 'DCP_DENORM_MODE_6BIT', 'DCP_DENORM_MODE_8BIT', 'DCP_DENORM_MODE_RESERVED0', 'DCP_DENORM_MODE_RESERVED1', 'DCP_DENORM_MODE_UNITY', 'DCP_FRAME_RANDOM_ENABLE', 'DCP_FRAME_RANDOM_ENABLE_FALSE', 'DCP_FRAME_RANDOM_ENABLE_TRUE', 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE', 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE', 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE', 'DCP_GRPH_ALPHA_CROSSBAR', 'DCP_GRPH_ALPHA_CROSSBAR_FROM_A', 'DCP_GRPH_ALPHA_CROSSBAR_FROM_B', 'DCP_GRPH_ALPHA_CROSSBAR_FROM_G', 'DCP_GRPH_ALPHA_CROSSBAR_FROM_R', 'DCP_GRPH_BLUE_CROSSBAR', 'DCP_GRPH_BLUE_CROSSBAR_FROM_A', 'DCP_GRPH_BLUE_CROSSBAR_FROM_B', 'DCP_GRPH_BLUE_CROSSBAR_FROM_G', 'DCP_GRPH_BLUE_CROSSBAR_FROM_R', 'DCP_GRPH_COLOR_EXPANSION_MODE', 'DCP_GRPH_COLOR_EXPANSION_MODE_DEXP', 'DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP', 'DCP_GRPH_DEGAMMA_MODE', 'DCP_GRPH_DEGAMMA_MODE_BYPASS', 'DCP_GRPH_DEGAMMA_MODE_RESERVED', 'DCP_GRPH_DEGAMMA_MODE_ROMA', 'DCP_GRPH_DEGAMMA_MODE_ROMB', 'DCP_GRPH_DEPTH', 'DCP_GRPH_DEPTH_16BPP', 'DCP_GRPH_DEPTH_32BPP', 'DCP_GRPH_DEPTH_64BPP', 'DCP_GRPH_DEPTH_8BPP', 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES', 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1', 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2', 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3', 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4', 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5', 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6', 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7', 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8', 'DCP_GRPH_DFQ_RESET', 'DCP_GRPH_DFQ_RESET_ACK', 'DCP_GRPH_DFQ_RESET_ACK_FALSE', 'DCP_GRPH_DFQ_RESET_ACK_TRUE', 'DCP_GRPH_DFQ_RESET_FALSE', 'DCP_GRPH_DFQ_RESET_TRUE', 'DCP_GRPH_DFQ_SIZE', 'DCP_GRPH_DFQ_SIZE_DEEP1', 'DCP_GRPH_DFQ_SIZE_DEEP2', 'DCP_GRPH_DFQ_SIZE_DEEP3', 'DCP_GRPH_DFQ_SIZE_DEEP4', 'DCP_GRPH_DFQ_SIZE_DEEP5', 'DCP_GRPH_DFQ_SIZE_DEEP6', 'DCP_GRPH_DFQ_SIZE_DEEP7', 'DCP_GRPH_DFQ_SIZE_DEEP8', 'DCP_GRPH_ENABLE', 'DCP_GRPH_ENABLE_FALSE', 'DCP_GRPH_ENABLE_TRUE', 'DCP_GRPH_ENDIAN_SWAP', 'DCP_GRPH_ENDIAN_SWAP_8IN16', 'DCP_GRPH_ENDIAN_SWAP_8IN32', 'DCP_GRPH_ENDIAN_SWAP_8IN64', 'DCP_GRPH_ENDIAN_SWAP_NONE', 'DCP_GRPH_FLIP_RATE', 'DCP_GRPH_FLIP_RATE_1FRAME', 'DCP_GRPH_FLIP_RATE_2FRAME', 'DCP_GRPH_FLIP_RATE_3FRAME', 'DCP_GRPH_FLIP_RATE_4FRAME', 'DCP_GRPH_FLIP_RATE_5FRAME', 'DCP_GRPH_FLIP_RATE_6FRAME', 'DCP_GRPH_FLIP_RATE_7FRAME', 'DCP_GRPH_FLIP_RATE_8FRAME', 'DCP_GRPH_FLIP_RATE_ENABLE', 'DCP_GRPH_FLIP_RATE_ENABLE_FALSE', 'DCP_GRPH_FLIP_RATE_ENABLE_TRUE', 'DCP_GRPH_FORMAT', 'DCP_GRPH_FORMAT_16BPP', 'DCP_GRPH_FORMAT_32BPP', 'DCP_GRPH_FORMAT_64BPP', 'DCP_GRPH_FORMAT_8BPP', 'DCP_GRPH_GAMUT_REMAP_MODE', 'DCP_GRPH_GAMUT_REMAP_MODE_BYPASS', 'DCP_GRPH_GAMUT_REMAP_MODE_RESERVED', 'DCP_GRPH_GAMUT_REMAP_MODE_ROMA', 'DCP_GRPH_GAMUT_REMAP_MODE_ROMB', 'DCP_GRPH_GREEN_CROSSBAR', 'DCP_GRPH_GREEN_CROSSBAR_FROM_A', 'DCP_GRPH_GREEN_CROSSBAR_FROM_B', 'DCP_GRPH_GREEN_CROSSBAR_FROM_G', 'DCP_GRPH_GREEN_CROSSBAR_FROM_R', 'DCP_GRPH_INPUT_GAMMA_MODE', 'DCP_GRPH_INPUT_GAMMA_MODE_BYPASS', 'DCP_GRPH_INPUT_GAMMA_MODE_LUT', 'DCP_GRPH_KEYER_ALPHA_SEL', 'DCP_GRPH_KEYER_ALPHA_SEL_FALSE', 'DCP_GRPH_KEYER_ALPHA_SEL_TRUE', 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN', 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE', 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE', 'DCP_GRPH_LUT_10BIT_BYPASS_EN', 'DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE', 'DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE', 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE', 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE', 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE', 'DCP_GRPH_MODE_UPDATE_PENDING', 'DCP_GRPH_MODE_UPDATE_PENDING_FALSE', 'DCP_GRPH_MODE_UPDATE_PENDING_TRUE', 'DCP_GRPH_MODE_UPDATE_TAKEN', 'DCP_GRPH_MODE_UPDATE_TAKEN_FALSE', 'DCP_GRPH_MODE_UPDATE_TAKEN_TRUE', 'DCP_GRPH_NUM_BANKS', 'DCP_GRPH_NUM_BANKS_16BANK', 'DCP_GRPH_NUM_BANKS_1BANK', 'DCP_GRPH_NUM_BANKS_2BANK', 'DCP_GRPH_NUM_BANKS_4BANK', 'DCP_GRPH_NUM_BANKS_8BANK', 'DCP_GRPH_NUM_PIPES', 'DCP_GRPH_NUM_PIPES_1PIPE', 'DCP_GRPH_NUM_PIPES_2PIPE', 'DCP_GRPH_NUM_PIPES_4PIPE', 'DCP_GRPH_NUM_PIPES_8PIPE', 'DCP_GRPH_PFLIP_INT_CLEAR', 'DCP_GRPH_PFLIP_INT_CLEAR_FALSE', 'DCP_GRPH_PFLIP_INT_CLEAR_TRUE', 'DCP_GRPH_PFLIP_INT_MASK', 'DCP_GRPH_PFLIP_INT_MASK_FALSE', 'DCP_GRPH_PFLIP_INT_MASK_TRUE', 'DCP_GRPH_PFLIP_INT_TYPE', 'DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL', 'DCP_GRPH_PFLIP_INT_TYPE_PULSE', 'DCP_GRPH_PRESCALE_BYPASS', 'DCP_GRPH_PRESCALE_BYPASS_FALSE', 'DCP_GRPH_PRESCALE_BYPASS_TRUE', 'DCP_GRPH_PRESCALE_B_SIGN', 'DCP_GRPH_PRESCALE_B_SIGN_SIGNED', 'DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED', 'DCP_GRPH_PRESCALE_G_SIGN', 'DCP_GRPH_PRESCALE_G_SIGN_SIGNED', 'DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED', 'DCP_GRPH_PRESCALE_R_SIGN', 'DCP_GRPH_PRESCALE_R_SIGN_SIGNED', 'DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED', 'DCP_GRPH_PRESCALE_SELECT', 'DCP_GRPH_PRESCALE_SELECT_FIXED', 'DCP_GRPH_PRESCALE_SELECT_FLOATING', 'DCP_GRPH_PRIMARY_DFQ_ENABLE', 'DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE', 'DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE', 'DCP_GRPH_RED_CROSSBAR', 'DCP_GRPH_RED_CROSSBAR_FROM_A', 'DCP_GRPH_RED_CROSSBAR_FROM_B', 'DCP_GRPH_RED_CROSSBAR_FROM_G', 'DCP_GRPH_RED_CROSSBAR_FROM_R', 'DCP_GRPH_REGAMMA_MODE', 'DCP_GRPH_REGAMMA_MODE_BYPASS', 'DCP_GRPH_REGAMMA_MODE_PROGA', 'DCP_GRPH_REGAMMA_MODE_PROGB', 'DCP_GRPH_REGAMMA_MODE_SRGB', 'DCP_GRPH_REGAMMA_MODE_XVYCC', 'DCP_GRPH_ROTATION_ANGLE', 'DCP_GRPH_ROTATION_ANGLE_0', 'DCP_GRPH_ROTATION_ANGLE_180', 'DCP_GRPH_ROTATION_ANGLE_270', 'DCP_GRPH_ROTATION_ANGLE_90', 'DCP_GRPH_SECONDARY_DFQ_ENABLE', 'DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE', 'DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE', 'DCP_GRPH_STEREOSYNC_FLIP_EN', 'DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE', 'DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE', 'DCP_GRPH_STEREOSYNC_FLIP_MODE', 'DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP', 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0', 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1', 'DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET', 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE', 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE', 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE', 'DCP_GRPH_SURFACE_COUNTER_EN', 'DCP_GRPH_SURFACE_COUNTER_EN_DISABLE', 'DCP_GRPH_SURFACE_COUNTER_EN_ENABLE', 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED', 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO', 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES', 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT', 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0', 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1', 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10', 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11', 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2', 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3', 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4', 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5', 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6', 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7', 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8', 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9', 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE', 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE', 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE', 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK', 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE', 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE', 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN', 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE', 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE', 'DCP_GRPH_SURFACE_UPDATE_PENDING', 'DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE', 'DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE', 'DCP_GRPH_SURFACE_UPDATE_TAKEN', 'DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE', 'DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE', 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE', 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE', 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE', 'DCP_GRPH_SW_MODE', 'DCP_GRPH_SW_MODE_0', 'DCP_GRPH_SW_MODE_2', 'DCP_GRPH_SW_MODE_22', 'DCP_GRPH_SW_MODE_23', 'DCP_GRPH_SW_MODE_26', 'DCP_GRPH_SW_MODE_27', 'DCP_GRPH_SW_MODE_3', 'DCP_GRPH_SW_MODE_30', 'DCP_GRPH_SW_MODE_31', 'DCP_GRPH_UPDATE_LOCK', 'DCP_GRPH_UPDATE_LOCK_FALSE', 'DCP_GRPH_UPDATE_LOCK_TRUE', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE', 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE', 'DCP_GRPH_XDMA_DRR_MODE_ENABLE', 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE', 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE', 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK', 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE', 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE', 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK', 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE', 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE', 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR', 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE', 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE', 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE', 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE', 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE', 'DCP_GRPH_XDMA_SUPER_AA_EN', 'DCP_GRPH_XDMA_SUPER_AA_EN_FALSE', 'DCP_GRPH_XDMA_SUPER_AA_EN_TRUE', 'DCP_GSL0_EN', 'DCP_GSL0_EN_FALSE', 'DCP_GSL0_EN_TRUE', 'DCP_GSL1_EN', 'DCP_GSL1_EN_FALSE', 'DCP_GSL1_EN_TRUE', 'DCP_GSL2_EN', 'DCP_GSL2_EN_FALSE', 'DCP_GSL2_EN_TRUE', 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING', 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE', 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE', 'DCP_GSL_MASTER_EN', 'DCP_GSL_MASTER_EN_FALSE', 'DCP_GSL_MASTER_EN_TRUE', 'DCP_GSL_SYNC_SOURCE', 'DCP_GSL_SYNC_SOURCE_FLIP', 'DCP_GSL_SYNC_SOURCE_PHASE0', 'DCP_GSL_SYNC_SOURCE_PHASE1', 'DCP_GSL_SYNC_SOURCE_RESET', 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC', 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS', 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN', 'DCP_GSL_XDMA_GROUP', 'DCP_GSL_XDMA_GROUP_HSYNC0', 'DCP_GSL_XDMA_GROUP_HSYNC1', 'DCP_GSL_XDMA_GROUP_HSYNC2', 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN', 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE', 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE', 'DCP_GSL_XDMA_GROUP_VSYNC', 'DCP_HIGHPASS_RANDOM_ENABLE', 'DCP_HIGHPASS_RANDOM_ENABLE_FALSE', 'DCP_HIGHPASS_RANDOM_ENABLE_TRUE', 'DCP_INPUT_CSC_GRPH_MODE', 'DCP_INPUT_CSC_GRPH_MODE_BYPASS', 'DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF', 'DCP_INPUT_CSC_GRPH_MODE_RESERVED', 'DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF', 'DCP_KEY_MODE', 'DCP_KEY_MODE_ALPHA0', 'DCP_KEY_MODE_ALPHA1', 'DCP_KEY_MODE_IN_RANGE_ALPHA0', 'DCP_KEY_MODE_IN_RANGE_ALPHA1', 'DCP_OUTPUT_CSC_GRPH_MODE', 'DCP_OUTPUT_CSC_GRPH_MODE_BYPASS', 'DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF', 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0', 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1', 'DCP_OUTPUT_CSC_GRPH_MODE_RGB', 'DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF', 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601', 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709', 'DCP_OUT_ROUND_TRUNC_MODE', 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_10', 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_11', 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_12', 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_13', 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_14', 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_8', 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_9', 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED', 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10', 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11', 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12', 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13', 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14', 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8', 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9', 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED', 'DCP_RGB_RANDOM_ENABLE', 'DCP_RGB_RANDOM_ENABLE_FALSE', 'DCP_RGB_RANDOM_ENABLE_TRUE', 'DCP_SPATIAL_DITHER_DEPTH', 'DCP_SPATIAL_DITHER_DEPTH_24BPP', 'DCP_SPATIAL_DITHER_DEPTH_30BPP', 'DCP_SPATIAL_DITHER_DEPTH_36BPP', 'DCP_SPATIAL_DITHER_DEPTH_UNDEFINED', 'DCP_SPATIAL_DITHER_EN', 'DCP_SPATIAL_DITHER_EN_FALSE', 'DCP_SPATIAL_DITHER_EN_TRUE', 'DCP_SPATIAL_DITHER_MODE', 'DCP_SPATIAL_DITHER_MODE_BYPASS', 'DCP_SPATIAL_DITHER_MODE_RESERVED', 'DCP_SPATIAL_DITHER_MODE_ROMA', 'DCP_SPATIAL_DITHER_MODE_ROMB', 'DCP_TEST_DEBUG_WRITE_EN', 'DCP_TEST_DEBUG_WRITE_EN_FALSE', 'DCP_TEST_DEBUG_WRITE_EN_TRUE', 'DC_MEM_GLOBAL_PWR_REQ_DIS', 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', 'DEGAMMA_MODE_A', 'DEGAMMA_MODE_B', 'DEGAMMA_MODE_BYPASS', 'DENORM_CLAMP_MODE_10', 'DENORM_CLAMP_MODE_12', 'DENORM_CLAMP_MODE_8', 'DENORM_CLAMP_MODE_UNITY', 'DEPTH_16', 'DEPTH_32_FLOAT', 'DEPTH_8_24', 'DEPTH_8_24_FLOAT', 'DEPTH_INVALID', 'DEPTH_X24_8_32_FLOAT', 'DEPTH_X8_24', 'DEPTH_X8_24_FLOAT', 'DFSMFlushEvents', 'DIGA_BE_SOFT_RESET', 'DIGA_BE_SOFT_RESET_0', 'DIGA_BE_SOFT_RESET_1', 'DIGA_FE_SOFT_RESET', 'DIGA_FE_SOFT_RESET_0', 'DIGA_FE_SOFT_RESET_1', 'DIGB_BE_SOFT_RESET', 'DIGB_BE_SOFT_RESET_0', 'DIGB_BE_SOFT_RESET_1', 'DIGB_FE_SOFT_RESET', 'DIGB_FE_SOFT_RESET_0', 'DIGB_FE_SOFT_RESET_1', 'DIGC_BE_SOFT_RESET', 'DIGC_BE_SOFT_RESET_0', 'DIGC_BE_SOFT_RESET_1', 'DIGC_FE_SOFT_RESET', 'DIGC_FE_SOFT_RESET_0', 'DIGC_FE_SOFT_RESET_1', 'DIGD_BE_SOFT_RESET', 'DIGD_BE_SOFT_RESET_0', 'DIGD_BE_SOFT_RESET_1', 'DIGD_FE_SOFT_RESET', 'DIGD_FE_SOFT_RESET_0', 'DIGD_FE_SOFT_RESET_1', 'DIGE_BE_SOFT_RESET', 'DIGE_BE_SOFT_RESET_0', 'DIGE_BE_SOFT_RESET_1', 'DIGE_FE_SOFT_RESET', 'DIGE_FE_SOFT_RESET_0', 'DIGE_FE_SOFT_RESET_1', 'DIGF_BE_SOFT_RESET', 'DIGF_BE_SOFT_RESET_0', 'DIGF_BE_SOFT_RESET_1', 'DIGF_FE_SOFT_RESET', 'DIGF_FE_SOFT_RESET_0', 'DIGF_FE_SOFT_RESET_1', 'DIGG_BE_SOFT_RESET', 'DIGG_BE_SOFT_RESET_0', 'DIGG_BE_SOFT_RESET_1', 'DIGG_FE_SOFT_RESET', 'DIGG_FE_SOFT_RESET_0', 'DIGG_FE_SOFT_RESET_1', 'DIGLPA_BE_SOFT_RESET', 'DIGLPA_BE_SOFT_RESET_0', 'DIGLPA_BE_SOFT_RESET_1', 'DIGLPA_FE_SOFT_RESET', 'DIGLPA_FE_SOFT_RESET_0', 'DIGLPA_FE_SOFT_RESET_1', 'DIGLPB_BE_SOFT_RESET', 'DIGLPB_BE_SOFT_RESET_0', 'DIGLPB_BE_SOFT_RESET_1', 'DIGLPB_FE_SOFT_RESET', 'DIGLPB_FE_SOFT_RESET_0', 'DIGLPB_FE_SOFT_RESET_1', 'DIG_10BIT_TEST_PATTERN', 'DIG_ALTERNATING_TEST_PATTERN', 'DIG_BE_CNTL_HPD1', 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', 'DIG_BE_CNTL_HPD4', 'DIG_BE_CNTL_HPD5', 'DIG_BE_CNTL_HPD6', 'DIG_BE_CNTL_HPD_SELECT', 'DIG_BE_CNTL_MODE', 'DIG_BE_DP_MST_MODE', 'DIG_BE_DP_SST_MODE', 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', 'DIG_BE_RESERVED3', 'DIG_BE_SDVO_RESERVED', 'DIG_BE_TMDS_DVI_MODE', 'DIG_BE_TMDS_HDMI_MODE', 'DIG_FE_CNTL_SOURCE_SELECT', 'DIG_FE_CNTL_STEREOSYNC_SELECT', 'DIG_FE_SOURCE_FROM_FMT0', 'DIG_FE_SOURCE_FROM_FMT1', 'DIG_FE_SOURCE_FROM_FMT2', 'DIG_FE_SOURCE_FROM_FMT3', 'DIG_FE_SOURCE_FROM_FMT4', 'DIG_FE_SOURCE_FROM_FMT5', 'DIG_FE_STEREOSYNC_FROM_FMT0', 'DIG_FE_STEREOSYNC_FROM_FMT1', 'DIG_FE_STEREOSYNC_FROM_FMT2', 'DIG_FE_STEREOSYNC_FROM_FMT3', 'DIG_FE_STEREOSYNC_FROM_FMT4', 'DIG_FE_STEREOSYNC_FROM_FMT5', 'DIG_FIFO_ERROR_ACK', 'DIG_FIFO_ERROR_ACK_INT', 'DIG_FIFO_ERROR_NOT_ACK', 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', 'DIG_FIFO_FORCE_RECOMP_MINMAX', 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_READ_CLOCK_SRC', 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', 'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE', 'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX', 'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL', 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', 'DIG_FIFO_USE_OVERWRITE_LEVEL', 'DIG_IN_DEBUG_MODE', 'DIG_IN_NORMAL_OPERATION', 'DIG_OUTPUT_CRC_CNTL_LINK_SEL', 'DIG_OUTPUT_CRC_DATA_SEL', 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', 'DIG_OUTPUT_CRC_FOR_AUDIO', 'DIG_OUTPUT_CRC_FOR_FULLFRAME', 'DIG_OUTPUT_CRC_FOR_VBI', 'DIG_OUTPUT_CRC_ON_LINK0', 'DIG_OUTPUT_CRC_ON_LINK1', 'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED', 'DIG_RANDOM_PATTERN_SEED_RAN_PAT', 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN', 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL', 'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM', 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN', 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET', 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', 'DISABLE_BINNING_USE_LEGACY_SC', 'DISABLE_BINNING_USE_NEW_SC', 'DISABLE_CLOCK_GATING', 'DISABLE_CLOCK_GATING_IN_DCO', 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', 'DISABLE_THE_CLOCK', 'DISABLE_THE_FEATURE', 'DISPCLK_CHG_FWD_CORR_DISABLE', 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', 'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE', 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DITHER_DIS', 'DITHER_EN', 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT', 'DI_INDEX_SIZE_8_BIT', 'DI_MAJOR_MODE_0', 'DI_MAJOR_MODE_1', 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', 'DI_PT_LINELIST_ADJ', 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', 'DI_PT_NONE', 'DI_PT_PATCH', 'DI_PT_POINTLIST', 'DI_PT_POLYGON', 'DI_PT_QUADLIST', 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', 'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', 'DI_PT_TRISTRIP', 'DI_PT_TRISTRIP_ADJ', 'DI_PT_TRI_WITH_WFLAGS', 'DI_PT_UNUSED_1', 'DI_PT_UNUSED_3', 'DI_PT_UNUSED_4', 'DI_SRC_SEL_AUTO_INDEX', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', 'DI_SRC_SEL_RESERVED', 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE', 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', 'DONUTS', 'DOUT_I2C_ACK', 'DOUT_I2C_ACK_TO_CLEAN', 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', 'DOUT_I2C_ARBITRATION_ABORT_XFER', 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG', 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO', 'DOUT_I2C_ARBITRATION_SW_PRIORITY', 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ', 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', 'DOUT_I2C_CONTROL_DBG_REF_SEL', 'DOUT_I2C_CONTROL_DDC_SELECT', 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', 'DOUT_I2C_CONTROL_GO', 'DOUT_I2C_CONTROL_NORMAL_DEBUG', 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', 'DOUT_I2C_CONTROL_RESET_SW_STATUS', 'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2', 'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4', 'DOUT_I2C_CONTROL_SELECT_DDC5', 'DOUT_I2C_CONTROL_SELECT_DDC6', 'DOUT_I2C_CONTROL_SELECT_DDCVGA', 'DOUT_I2C_CONTROL_SEND_RESET', 'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER', 'DOUT_I2C_CONTROL_STOP_TRANSFER', 'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0', 'DOUT_I2C_CONTROL_TRANS0_TRANS1', 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', 'DOUT_I2C_CONTROL_TRANSACTION_COUNT', 'DOUT_I2C_CONTROL__NOT_SEND_RESET', 'DOUT_I2C_CONTROL__SEND_RESET', 'DOUT_I2C_DATA_INDEX_WRITE', 'DOUT_I2C_DATA__INDEX_WRITE', 'DOUT_I2C_DATA__NOT_INDEX_WRITE', 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN', 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN', 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL', 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE', 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', 'DOUT_I2C_DDC_SPEED_THRESHOLD', 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET', 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', 'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', 'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DOWNSCALE_PREFETCH_DIS', 'DOWNSCALE_PREFETCH_EN', 'DPCSRX_BPHY_PCS_RX0_CLK', 'DPCSRX_BPHY_PCS_RX1_CLK', 'DPCSRX_BPHY_PCS_RX2_CLK', 'DPCSRX_BPHY_PCS_RX3_CLK', 'DPCSRX_DBG_CFGCLK_SEL', 'DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER', 'DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE', 'DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF', 'DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', 'DPCSRX_DBG_RX_SYMCLK_SEL_INT', 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT0', 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT1', 'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL', 'DPCSRX_RX_SYMCLK_SEL', 'DPCSTX_DBG_CFGCLK_SEL', 'DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER', 'DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE', 'DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF', 'DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD', 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT', 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0', 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1', 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2', 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3', 'DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR', 'DPCSTX_DBG_TX_SYMCLK_SEL_IN0', 'DPCSTX_DBG_TX_SYMCLK_SEL_IN1', 'DPCSTX_TX_SYMCLK_DIV2_SEL', 'DPCSTX_TX_SYMCLK_SEL', 'DPDBG_CLK_FORCE_EN', 'DPDBG_CLK_FORCE_EN_DISABLE', 'DPDBG_CLK_FORCE_EN_ENABLE', 'DPDBG_DISABLE', 'DPDBG_EN', 'DPDBG_ENABLE', 'DPDBG_ERROR_DETECTION_MODE', 'DPDBG_ERROR_DETECTION_MODE_CSC', 'DPDBG_ERROR_DETECTION_MODE_RS_ENCODING', 'DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK', 'DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK', 'DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE', 'DPDBG_FIFO_OVERFLOW_INT_CLEAR', 'DPDBG_FIFO_OVERFLOW_INT_DISABLE', 'DPDBG_FIFO_OVERFLOW_INT_ENABLE', 'DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED', 'DPDBG_FIFO_OVERFLOW_INT_NO_ACK', 'DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED', 'DPDBG_INPUT_DISABLE', 'DPDBG_INPUT_EN', 'DPDBG_INPUT_ENABLE', 'DPDBG_SOFT_RESET', 'DPDBG_SOFT_RESET_0', 'DPDBG_SOFT_RESET_1', 'DPHY_8B10B_CUR_DISP', 'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO', 'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET', 'DPHY_8B10B_RESETET', 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', 'DPHY_ALT_SCRAMBLER_RESET_EN', 'DPHY_ALT_SCRAMBLER_RESET_SEL', 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', 'DPHY_ATEST_LANE0_PRBS_PATTERN', 'DPHY_ATEST_LANE0_REG_PATTERN', 'DPHY_ATEST_LANE1_PRBS_PATTERN', 'DPHY_ATEST_LANE1_REG_PATTERN', 'DPHY_ATEST_LANE2_PRBS_PATTERN', 'DPHY_ATEST_LANE2_REG_PATTERN', 'DPHY_ATEST_LANE3_PRBS_PATTERN', 'DPHY_ATEST_LANE3_REG_PATTERN', 'DPHY_ATEST_SEL_LANE0', 'DPHY_ATEST_SEL_LANE1', 'DPHY_ATEST_SEL_LANE2', 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', 'DPHY_CRC_CONTINUOUS', 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', 'DPHY_CRC_EN', 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', 'DPHY_CRC_LANE0_SELECTED', 'DPHY_CRC_LANE1_SELECTED', 'DPHY_CRC_LANE2_SELECTED', 'DPHY_CRC_LANE3_SELECTED', 'DPHY_CRC_MST_PHASE_ERROR_ACK', 'DPHY_CRC_MST_PHASE_ERROR_ACKED', 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT', 'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD', 'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT', 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', 'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', 'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START', 'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW', 'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED', 'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN', 'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL', 'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SCRAMBLER_ADVANCE', 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', 'DPHY_SCRAMBLER_DIS', 'DPHY_SCRAMBLER_KCODE', 'DPHY_SCRAMBLER_KCODE_DISABLED', 'DPHY_SCRAMBLER_KCODE_ENABLED', 'DPHY_SCRAMBLER_SEL', 'DPHY_SCRAMBLER_SEL_DBG_DATA', 'DPHY_SCRAMBLER_SEL_LANE_DATA', 'DPHY_SCR_DISABLED', 'DPHY_SCR_ENABLED', 'DPHY_SKEW_BYPASS', 'DPHY_SW_FAST_TRAINING_NOT_STARTED', 'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED', 'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2', 'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4', 'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL', 'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL', 'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL', 'DPREFCLK_SRC_SEL_P3PLL', 'DPRX_SD_COMPONENT_DEPTH', 'DPRX_SD_PIXEL_ENCODING', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG', 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ', 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', 'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED', 'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED', 'DP_AUX_CONTROL_HPD5_SELECTED', 'DP_AUX_CONTROL_HPD6_SELECTED', 'DP_AUX_CONTROL_HPD_SEL', 'DP_AUX_CONTROL_TEST_MODE', 'DP_AUX_CONTROL_TEST_MODE_DISABLE', 'DP_AUX_CONTROL_TEST_MODE_ENABLE', 'DP_AUX_DEFINITE_ERR_REACHED_ACK', 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START', 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP', 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN', 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN', 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW', 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW', 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN', 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US', 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US', 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US', 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US', 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US', 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US', 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US', 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US', 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD', 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY', 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN', 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US', 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US', 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US', 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US', 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US', 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US', 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US', 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US', 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE', 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL', 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', 'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK', 'DP_AUX_ERR_OCCURRED__NOT_ACK', 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ', 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW', 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT', 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN', 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK', 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK', 'DP_AUX_INT__NOT_ACK', 'DP_AUX_LS_UPDATE_ACK', 'DP_AUX_POTENTIAL_ERR_REACHED_ACK', 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET', 'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED', 'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE', 'DP_AUX_RESET_SEQUENCE_NOT_DONE', 'DP_AUX_SW_CONTROL_LS_READ_TRIG', 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', 'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO', 'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO', 'DP_COMPONENT_DEPTH', 'DP_COMPONENT_DEPTH_10BPC', 'DP_COMPONENT_DEPTH_12BPC', 'DP_COMPONENT_DEPTH_16BPC_RESERVED', 'DP_COMPONENT_DEPTH_6BPC', 'DP_COMPONENT_DEPTH_8BPC', 'DP_COMPONENT_DEPTH_RESERVED', 'DP_DPHY_8B10B_EXT_DISP', 'DP_DPHY_8B10B_EXT_DISP_ONE', 'DP_DPHY_8B10B_EXT_DISP_ZERO', 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK', 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK', 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN', 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', 'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1', 'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS', 'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE', 'DP_DTO_DESPREAD_DISABLE', 'DP_DTO_DESPREAD_ENABLE', 'DP_DTO_DS_DISABLE', 'DP_DYN_CEA_RANGE', 'DP_DYN_RANGE', 'DP_DYN_VESA_RANGE', 'DP_EMBEDDED_PANEL', 'DP_EMBEDDED_PANEL_MODE', 'DP_EXTERNAL_PANEL', 'DP_LINK_TRAINING_ALREADY_COMPLETE', 'DP_LINK_TRAINING_COMPLETE', 'DP_LINK_TRAINING_NOT_COMPLETE', 'DP_MSA_MISC0_OVERRIDE_ENABLE', 'DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE', 'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE', 'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED', 'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG', 'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG', 'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER', 'DP_MSE_OUTPUT_DPDBG_DATA', 'DP_MSE_OUTPUT_DPDBG_DATA_DIS', 'DP_MSE_OUTPUT_DPDBG_DATA_EN', 'DP_MSE_SAT_UPDATE_ACT', 'DP_MSE_SAT_UPDATE_NO_ACTION', 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE', 'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER', 'DP_PIXEL_ENCODING', 'DP_PIXEL_ENCODING_RESERVED', 'DP_PIXEL_ENCODING_RGB444', 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', 'DP_PIXEL_ENCODING_YCBCR420', 'DP_PIXEL_ENCODING_YCBCR422', 'DP_PIXEL_ENCODING_YCBCR444', 'DP_PIXEL_ENCODING_Y_ONLY', 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE', 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', 'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY', 'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE', 'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL', 'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG', 'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY', 'DP_SEC_GSP0_SEND', 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', 'DP_SEC_TIMESTAMP_MODE', 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 'DP_STEER_OVERFLOW_ACK', 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK', 'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK', 'DP_TOP_FIELD_ONLY', 'DP_TOP_PLUS_BOTTOM_FIELD', 'DP_TU_OVERFLOW_ACK', 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_UDI_1_LANE', 'DP_UDI_2_LANES', 'DP_UDI_4_LANES', 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED', 'DP_VID_ENHANCED_FRAME_MODE', 'DP_VID_MSA_TOP_FIELD_MODE', 'DP_VID_M_DOUBLE_INPUT_PIXEL_RATE', 'DP_VID_M_DOUBLE_VALUE_EN', 'DP_VID_M_INPUT_PIXEL_RATE', 'DP_VID_M_N_CALC_AUTO', 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', 'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN', 'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_STREAM_DISABLE_ACK', 'DP_VID_STREAM_DISABLE_MASK', 'DP_VID_STREAM_DIS_DEFER', 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER', 'DP_VID_TIMING_MODE', 'DP_VID_TIMING_MODE_ASYNC', 'DP_VID_TIMING_MODE_SYNC', 'DP_VID_VBID_FIELD_POL', 'DP_VID_VBID_FIELD_POL_INV', 'DP_VID_VBID_FIELD_POL_NORMAL', 'DP_YCBCR_RANGE', 'DP_YCBCR_RANGE_BT601_5', 'DP_YCBCR_RANGE_BT709_5', 'DSI_BIT_SWAP', 'DSI_BIT_SWAP_DISABLE', 'DSI_BIT_SWAP_ENABLE', 'DSI_CLK_GATING', 'DSI_CLK_GATING_DISABLE', 'DSI_CLK_GATING_ENABLE', 'DSI_CLOCK_LANE_DISABLE', 'DSI_CLOCK_LANE_EN', 'DSI_CLOCK_LANE_ENABLE', 'DSI_CLOCK_LANE_HS_FORCE_REQUEST', 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT', 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT', 'DSI_CMD_EMBEDDED_MODE', 'DSI_CMD_MODE_DISABLE', 'DSI_CMD_MODE_EN', 'DSI_CMD_MODE_ENABLE', 'DSI_CMD_ORDER', 'DSI_CMD_ORDER_COMMAND_FIRST', 'DSI_CMD_ORDER_DATA_FIRST', 'DSI_CMD_PACKET_TYPE', 'DSI_CMD_PACKET_TYPE_LONG', 'DSI_CMD_PACKET_TYPE_SHORT', 'DSI_CMD_PWR_MODE', 'DSI_CMD_PWR_MODE_HS', 'DSI_CMD_PWR_MODE_LP', 'DSI_CMD_USE_CMDFIFO', 'DSI_CMD_USE_DMAFIFO', 'DSI_COMMAND_DST_FORMAT_RGB111', 'DSI_COMMAND_DST_FORMAT_RGB332', 'DSI_COMMAND_DST_FORMAT_RGB444', 'DSI_COMMAND_DST_FORMAT_RGB565', 'DSI_COMMAND_DST_FORMAT_RGB666', 'DSI_COMMAND_DST_FORMAT_RGB888', 'DSI_COMMAND_MODE_DST_FORMAT', 'DSI_COMMAND_MODE_SRC_FORMAT', 'DSI_COMMAND_SRC_FORMAT_RGB332', 'DSI_COMMAND_SRC_FORMAT_RGB444', 'DSI_COMMAND_SRC_FORMAT_RGB555', 'DSI_COMMAND_SRC_FORMAT_RGB565', 'DSI_COMMAND_SRC_FORMAT_RGB888', 'DSI_COMMAND_SRC_FORMAT_RGB8BIT', 'DSI_COMMAND_TRIGGER_MODE', 'DSI_COMMAND_TRIGGER_MODE_AUTO', 'DSI_COMMAND_TRIGGER_MODE_MANUAL', 'DSI_COMMAND_TRIGGER_ORDER', 'DSI_COMMAND_TRIGGER_ORDER_DENG', 'DSI_COMMAND_TRIGGER_ORDER_DMA', 'DSI_COMMAND_TRIGGER_SEL', 'DSI_COMMAND_TRIGGER_SEL_CRTC', 'DSI_COMMAND_TRIGGER_SEL_HW', 'DSI_COMMAND_TRIGGER_SEL_NONE', 'DSI_COMMAND_TRIGGER_SEL_TE', 'DSI_CONTROLLER_DISABLE', 'DSI_CONTROLLER_EN', 'DSI_CONTROLLER_ENABLE', 'DSI_CRC_CAL_DISABLE', 'DSI_CRC_CAL_ENABLE', 'DSI_CRC_ENABLE', 'DSI_CRTC_FREEZE_TRIG', 'DSI_CRTC_FREEZE_TRIG_ASSERT', 'DSI_CRTC_FREEZE_TRIG_DEASSERT', 'DSI_CRTC_SEL', 'DSI_DATA_BUFFER_ID', 'DSI_DATA_BUFFER_OFFSET0', 'DSI_DATA_BUFFER_OFFSET1', 'DSI_DATA_LANE0_DISABLE', 'DSI_DATA_LANE0_EN', 'DSI_DATA_LANE0_ENABLE', 'DSI_DATA_LANE1_DISABLE', 'DSI_DATA_LANE1_EN', 'DSI_DATA_LANE1_ENABLE', 'DSI_DATA_LANE2_DISABLE', 'DSI_DATA_LANE2_EN', 'DSI_DATA_LANE2_ENABLE', 'DSI_DATA_LANE3_DISABLE', 'DSI_DATA_LANE3_EN', 'DSI_DATA_LANE3_ENABLE', 'DSI_DBG_CLK_SEL', 'DSI_DEBUG_BYTECLK_SEL', 'DSI_DEBUG_BYTECLK_SEL_AFIFO', 'DSI_DEBUG_BYTECLK_SEL_EOT', 'DSI_DEBUG_BYTECLK_SEL_LANEBUF0', 'DSI_DEBUG_BYTECLK_SEL_LANEBUF1', 'DSI_DEBUG_BYTECLK_SEL_LANEBUF2', 'DSI_DEBUG_BYTECLK_SEL_LANEBUF3', 'DSI_DEBUG_BYTECLK_SEL_LANECTRL', 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO0', 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO1', 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO2', 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO3', 'DSI_DEBUG_BYTECLK_SEL_PINGPING2', 'DSI_DEBUG_BYTECLK_SEL_PINGPING3', 'DSI_DEBUG_BYTECLK_SEL_PINGPONG0', 'DSI_DEBUG_BYTECLK_SEL_PINGPONG1', 'DSI_DEBUG_DSICLK_SEL', 'DSI_DEBUG_DSICLK_SEL_AFIFO', 'DSI_DEBUG_DSICLK_SEL_CMDBUFFER', 'DSI_DEBUG_DSICLK_SEL_CMDFIFO', 'DSI_DEBUG_DSICLK_SEL_CMD_ENGINE', 'DSI_DEBUG_DSICLK_SEL_LANECTRL', 'DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO', 'DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE', 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE', 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT', 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT', 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX', 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT', 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT', 'DSI_DENG_FIFO_LEVEL_CAL_AVERAGE', 'DSI_DENG_FIFO_LEVEL_OVERWRITE', 'DSI_DENG_FIFO_START', 'DSI_DENG_FIFO_START_ASSERT', 'DSI_DENG_FIFO_START_DEASSERT', 'DSI_DENG_FIFO_USE_OVERWRITE_LEVEL', 'DSI_DMAFIFO_READ_WATERMARK', 'DSI_DMAFIFO_READ_WATERMARK_EIGHTH', 'DSI_DMAFIFO_READ_WATERMARK_FOURTH', 'DSI_DMAFIFO_READ_WATERMARK_HALF', 'DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH', 'DSI_DMAFIFO_WRITE_WATERMARK', 'DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH', 'DSI_DMAFIFO_WRITE_WATERMARK_FOURTH', 'DSI_DMAFIFO_WRITE_WATERMARK_HALF', 'DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH', 'DSI_DWORD_BYTE_SWAP', 'DSI_EXT_RESET_POL', 'DSI_EXT_RESET_POL_HIGH', 'DSI_EXT_RESET_POL_LOW', 'DSI_EXT_TE_MODE', 'DSI_EXT_TE_MODE_HVSYNC_EDGE', 'DSI_EXT_TE_MODE_HVSYNC_WIDTH', 'DSI_EXT_TE_MODE_VSYNC_EDGE', 'DSI_EXT_TE_MODE_VSYNC_WIDTH', 'DSI_EXT_TE_MUX', 'DSI_EXT_TE_POL', 'DSI_EXT_TE_POL_FALLING', 'DSI_EXT_TE_POL_RISING', 'DSI_FLAG_CLEAR', 'DSI_FLAG_CLR', 'DSI_FLAG_NO_CLEAR', 'DSI_GET_PIXEL_STREAM_FROM_FMT0', 'DSI_GET_PIXEL_STREAM_FROM_FMT1', 'DSI_GET_PIXEL_STREAM_FROM_FMT2', 'DSI_GET_PIXEL_STREAM_FROM_FMT3', 'DSI_GET_PIXEL_STREAM_FROM_FMT4', 'DSI_GET_PIXEL_STREAM_FROM_FMT5', 'DSI_HW_SOURCE_SEL', 'DSI_INSERT_DCS_COMMAND', 'DSI_INSERT_DCS_COMMAND_DISABLE', 'DSI_INSERT_DCS_COMMAND_ENABLE', 'DSI_LANE_FORCE_TX_STOP', 'DSI_LANE_FORCE_TX_STOP_ASSERT', 'DSI_LANE_FORCE_TX_STOP_DEASSERT', 'DSI_LANE_ULPS_EXIT', 'DSI_LANE_ULPS_EXIT_ASSERT', 'DSI_LANE_ULPS_EXIT_DEASSERT', 'DSI_LANE_ULPS_REQUEST', 'DSI_LANE_ULPS_REQUEST_ASSERT', 'DSI_LANE_ULPS_REQUEST_DEASSERT', 'DSI_MIPI_BIST_RESET', 'DSI_MIPI_BIST_RESET_ASSERT', 'DSI_MIPI_BIST_RESET_DEASSERT', 'DSI_MIPI_BIST_START', 'DSI_MIPI_BIST_START_ASSERT', 'DSI_MIPI_BIST_START_DEASSERT', 'DSI_MIPI_BIST_VIDEO_FRMT', 'DSI_MIPI_BIST_VIDEO_FRMT_RAW8', 'DSI_MIPI_BIST_VIDEO_FRMT_YUV422', 'DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC', 'DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC', 'DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC', 'DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC', 'DSI_PACKET_BYTE_MSB_LSB_FLIP', 'DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP', 'DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP', 'DSI_PERF_LATENCY_SEL', 'DSI_PERF_LATENCY_SEL_DATA_LANE0', 'DSI_PERF_LATENCY_SEL_DATA_LANE1', 'DSI_PERF_LATENCY_SEL_DATA_LANE2', 'DSI_PERF_LATENCY_SEL_DATA_LANE3', 'DSI_PHY_DATA_LANE0_DISABLE', 'DSI_PHY_DATA_LANE0_EN', 'DSI_PHY_DATA_LANE0_ENABLE', 'DSI_PHY_DATA_LANE1_DISABLE', 'DSI_PHY_DATA_LANE1_EN', 'DSI_PHY_DATA_LANE1_ENABLE', 'DSI_PHY_DATA_LANE2_DISABLE', 'DSI_PHY_DATA_LANE2_EN', 'DSI_PHY_DATA_LANE2_ENABLE', 'DSI_PHY_DATA_LANE3_DISABLE', 'DSI_PHY_DATA_LANE3_EN', 'DSI_PHY_DATA_LANE3_ENABLE', 'DSI_RESET_BYTECLK', 'DSI_RESET_DISPCLK', 'DSI_RESET_DSICLK', 'DSI_RESET_ESCCLK', 'DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC', 'DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC', 'DSI_RESET_ON_DSICLK_DOMAIN_LOGIC', 'DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC', 'DSI_RESET_PANEL', 'DSI_RESET_PANEL_ASSERT', 'DSI_RESET_PANEL_DEASSERT', 'DSI_RGB_SWAP', 'DSI_RX_EOT_IGNORE', 'DSI_RX_EOT_IGNORE_DISABLE', 'DSI_RX_EOT_IGNORE_ENABLE', 'DSI_SWAP_BGR', 'DSI_SWAP_BRG', 'DSI_SWAP_GBR', 'DSI_SWAP_GRB', 'DSI_SWAP_RBG', 'DSI_SWAP_RGB', 'DSI_TEST_CLK_SEL_BYTECLK_G', 'DSI_TEST_CLK_SEL_DISPCLK_G', 'DSI_TEST_CLK_SEL_DISPCLK_P', 'DSI_TEST_CLK_SEL_DISPCLK_R', 'DSI_TEST_CLK_SEL_DSICLK_G', 'DSI_TEST_CLK_SEL_DSICLK_P', 'DSI_TEST_CLK_SEL_DSICLK_R', 'DSI_TEST_CLK_SEL_DSICLK_TRN', 'DSI_TEST_CLK_SEL_ESCCLK_G', 'DSI_TE_SEL_LINK', 'DSI_TE_SEL_PIN', 'DSI_TE_SRC_SEL', 'DSI_TRAFFIC_MODE_BURST', 'DSI_TRAFFIC_MODE_RESERVED', 'DSI_TRAFFIC_MODE_SYNC_EVENTS', 'DSI_TRAFFIC_MODE_SYNC_PULSES', 'DSI_TX_EOT_APPEND', 'DSI_TX_EOT_APPEND_DISABLE', 'DSI_TX_EOT_APPEND_ENABLE', 'DSI_USE_CMDFIFO', 'DSI_USE_DENG_LENGTH', 'DSI_USE_DENG_LENGTH_DISABLE', 'DSI_USE_DENG_LENGTH_ENABLE', 'DSI_VIDEO_BLLP_PWR_MODE', 'DSI_VIDEO_BLLP_PWR_MODE_HS', 'DSI_VIDEO_BLLP_PWR_MODE_LP', 'DSI_VIDEO_DST_FORMAT_RGB565', 'DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED', 'DSI_VIDEO_DST_FORMAT_RGB666_PACKED', 'DSI_VIDEO_DST_FORMAT_RGB888', 'DSI_VIDEO_EOF_BLLP_PWR_MODE', 'DSI_VIDEO_EOF_BLLP_PWR_MODE_HS', 'DSI_VIDEO_EOF_BLLP_PWR_MODE_LP', 'DSI_VIDEO_MODE_DISABLE', 'DSI_VIDEO_MODE_DST_FORMAT', 'DSI_VIDEO_MODE_EN', 'DSI_VIDEO_MODE_ENABLE', 'DSI_VIDEO_PULSE_MODE_OPT', 'DSI_VIDEO_PWR_MODE', 'DSI_VIDEO_PWR_MODE_HS', 'DSI_VIDEO_PWR_MODE_LP', 'DSI_VIDEO_TRAFFIC_MODE', 'DSI_XT_TE_MUX_DCLK', 'DSI_XT_TE_MUX_DINV', 'DSI_XT_TE_MUX_FRAME', 'DSI_XT_TE_MUX_GCLK', 'DSI_XT_TE_MUX_GOE', 'DSI_XT_TE_MUX_GPIO4', 'DSI_XT_TE_MUX_GPIO5', 'DSI_XT_TE_MUX_LCDD17', 'DSI_XT_TE_MUX_SS', 'DSM_ENABLE_ERROR_INJECT', 'DSM_ENABLE_ERROR_INJECT_DOUBLE', 'DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED', 'DSM_ENABLE_ERROR_INJECT_FED_IN', 'DSM_ENABLE_ERROR_INJECT_SINGLE', 'DSM_SELECT_INJECT_DELAY', 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', 'DSM_SELECT_INJECT_DELAY_NO_DELAY', 'DS_REF_IS_EXT_GENLOCK', 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN', 'DS_REF_SRC', 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKC_IN_PHASE', 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKC_MVP_IN_PHASE', 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE', 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKD_IN_PHASE', 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', 'DVOACLK_COARSE_SKEW_CNTL', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', 'DVOACLK_FINE_SKEW_CNTL', 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 'DVO_ENABLE_RST', 'DVO_ENABLE_RST_DISABLE', 'DVO_ENABLE_RST_ENABLE', 'DVO_SOFT_RESET', 'DVO_SOFT_RESET_0', 'DVO_SOFT_RESET_1', 'DWORD_BYTE_SWAP_BOTH_SWAP', 'DWORD_BYTE_SWAP_BYTE_SWAP', 'DWORD_BYTE_SWAP_NO_SWAP', 'DWORD_BYTE_SWAP_WORD_SWAP', 'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE', 'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE', 'DYNAMIC_PIXEL_DEPTH_30BPP', 'DYNAMIC_PIXEL_DEPTH_36BPP', 'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks', 'DbPRTFaultBehavior', 'DbPSLControl', 'DepthArray', 'DepthFormat', 'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z', 'ENABLE', 'ENABLE_CLOCK', 'ENABLE_JITTER_REMOVAL', 'ENABLE_LEGACY_PIPELINE', 'ENABLE_MEM_PWR_CTRL', 'ENABLE_NGG_PIPELINE', 'ENABLE_THE_CLOCK', 'ENABLE_THE_FEATURE', 'ENDIAN_8IN16', 'ENDIAN_8IN32', 'ENDIAN_8IN64', 'ENDIAN_NONE', 'END_OF_PIPE_IB_END', 'END_OF_PIPE_INCR_DE', 'ENUMS_GDS_PERFCOUNT_SELECT_H', 'ENUM_NUM_SIMD_PER_CU', 'ENUM_SQ_EXPORT_RAT_INST', 'ENUM_XDMA_LOCAL_SW_MODE', 'ENUM_XDMA_MSTR_ALPHA_POSITION', 'ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL', 'ENUM_XDMA_SLV_ALPHA_POSITION', 'ES_STAGE_DS', 'ES_STAGE_OFF', 'ES_STAGE_REAL', 'EXPORT_16_16_FLOAT_8PIX', 'EXPORT_16_16_SIGNED_8PIX', 'EXPORT_16_16_UNSIGNED_8PIX', 'EXPORT_2C_32BPC_AR', 'EXPORT_2C_32BPC_GR', 'EXPORT_2P_32BPC_ABGR', 'EXPORT_32BPP_8PIX', 'EXPORT_32_ABGR', 'EXPORT_32_AR', 'EXPORT_32_GR', 'EXPORT_32_R', 'EXPORT_4C_16BPC', 'EXPORT_4C_32BPC', 'EXPORT_4P_16BPC_ABGR', 'EXPORT_4P_32BPC_ABGR', 'EXPORT_4P_32BPC_AR', 'EXPORT_4P_32BPC_GR', 'EXPORT_8P_32BPC_R', 'EXPORT_ANY_Z', 'EXPORT_FP16_ABGR', 'EXPORT_GREATER_THAN_Z', 'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'EXPORT_SIGNED16_ABGR', 'EXPORT_UNSIGNED16_ABGR', 'EXPORT_UNUSED', 'FAULT_FAIL', 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', 'FBC_IDLE_MASK_DISP_REG_UPDATE', 'FBC_IDLE_MASK_FBC_ALPHA_COMP_EN', 'FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF', 'FBC_IDLE_MASK_FBC_GRPH_COMP_EN', 'FBC_IDLE_MASK_FBC_MIN_COMPRESSION', 'FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN', 'FBC_IDLE_MASK_MASK_BITS', 'FBC_IDLE_MASK_MC_HIT_REGION_0', 'FBC_IDLE_MASK_MC_HIT_REGION_1', 'FBC_IDLE_MASK_MC_HIT_REGION_2', 'FBC_IDLE_MASK_MC_HIT_REGION_3', 'FBC_IDLE_MASK_MC_WRITE', 'FBC_IDLE_MASK_RESERVED1', 'FBC_IDLE_MASK_RESERVED10', 'FBC_IDLE_MASK_RESERVED11', 'FBC_IDLE_MASK_RESERVED12', 'FBC_IDLE_MASK_RESERVED13', 'FBC_IDLE_MASK_RESERVED14', 'FBC_IDLE_MASK_RESERVED15', 'FBC_IDLE_MASK_RESERVED16', 'FBC_IDLE_MASK_RESERVED17', 'FBC_IDLE_MASK_RESERVED18', 'FBC_IDLE_MASK_RESERVED19', 'FBC_IDLE_MASK_RESERVED20', 'FBC_IDLE_MASK_RESERVED21', 'FBC_IDLE_MASK_RESERVED22', 'FBC_IDLE_MASK_RESERVED23', 'FBC_IDLE_MASK_RESERVED29', 'FBC_IDLE_MASK_RESERVED30', 'FBC_IDLE_MASK_RESERVED31', 'FBC_IDLE_MASK_RESERVED7', 'FBC_IDLE_MASK_RESERVED8', 'FBC_IDLE_MASK_RESERVED9', 'FLUSH_AND_INV_CB_DATA_TS', 'FLUSH_AND_INV_CB_META', 'FLUSH_AND_INV_CB_PIXEL_DATA', 'FLUSH_AND_INV_DB_DATA_TS', 'FLUSH_AND_INV_DB_META', 'FLUSH_CONTROL_FLUSH_NOT_STARTED', 'FLUSH_CONTROL_FLUSH_STARTED', 'FLUSH_DFSM', 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', 'FMT0_SOFT_RESET', 'FMT0_SOFT_RESET_0', 'FMT0_SOFT_RESET_1', 'FMT1_SOFT_RESET', 'FMT1_SOFT_RESET_0', 'FMT1_SOFT_RESET_1', 'FMT2_SOFT_RESET', 'FMT2_SOFT_RESET_0', 'FMT2_SOFT_RESET_1', 'FMT3_SOFT_RESET', 'FMT3_SOFT_RESET_0', 'FMT3_SOFT_RESET_1', 'FMT420_MEMORY_SOURCE_SEL', 'FMT420_MEMORY_SOURCE_SEL_FMT0', 'FMT420_MEMORY_SOURCE_SEL_FMT1', 'FMT420_MEMORY_SOURCE_SEL_FMT2', 'FMT420_MEMORY_SOURCE_SEL_FMT3', 'FMT420_MEMORY_SOURCE_SEL_FMT4', 'FMT420_MEMORY_SOURCE_SEL_FMT5', 'FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED', 'FMT4_SOFT_RESET', 'FMT4_SOFT_RESET_0', 'FMT4_SOFT_RESET_1', 'FMT5_SOFT_RESET', 'FMT5_SOFT_RESET_0', 'FMT5_SOFT_RESET_1', 'FMT_1', 'FMT_10_10_10_2', 'FMT_10_11_11', 'FMT_10_11_11_FLOAT', 'FMT_11_11_10', 'FMT_11_11_10_FLOAT', 'FMT_16', 'FMT_16_16', 'FMT_16_16_16', 'FMT_16_16_16_16', 'FMT_16_16_16_16_FLOAT', 'FMT_16_16_16_FLOAT', 'FMT_16_16_FLOAT', 'FMT_16_FLOAT', 'FMT_1_5_5_5', 'FMT_1_REVERSED', 'FMT_24_8', 'FMT_24_8_FLOAT', 'FMT_2_10_10_10', 'FMT_32', 'FMT_32_32', 'FMT_32_32_32', 'FMT_32_32_32_32', 'FMT_32_32_32_32_FLOAT', 'FMT_32_32_32_FLOAT', 'FMT_32_32_FLOAT', 'FMT_32_AS_32_32_32_32', 'FMT_32_AS_8', 'FMT_32_AS_8_8', 'FMT_32_FLOAT', 'FMT_3_3_2', 'FMT_4_4', 'FMT_4_4_4_4', 'FMT_5_5_5_1', 'FMT_5_6_5', 'FMT_5_9_9_9_SHAREDEXP', 'FMT_6_5_5', 'FMT_8', 'FMT_8_24', 'FMT_8_24_FLOAT', 'FMT_8_8', 'FMT_8_8_8', 'FMT_8_8_8_8', 'FMT_APC3', 'FMT_APC4', 'FMT_APC5', 'FMT_APC6', 'FMT_APC7', 'FMT_BC1', 'FMT_BC2', 'FMT_BC3', 'FMT_BC4', 'FMT_BC5', 'FMT_BC6', 'FMT_BC7', 'FMT_BG_RG', 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL', 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL', 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL', 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH', 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH', 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL', 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH', 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE', 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', 'FMT_CLAMP_CNTL_COLOR_FORMAT', 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS', 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', 'FMT_CONTROL_PIXEL_ENCODING', 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', 'FMT_CONTROL_SUBSAMPLING_MODE', 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', 'FMT_CONTROL_SUBSAMPLING_ORDER', 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', 'FMT_CRC_CNTL_CONT_EN', 'FMT_CRC_CNTL_CONT_EN_CONT', 'FMT_CRC_CNTL_CONT_EN_ONE_SHOT', 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE', 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL', 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN', 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT', 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN', 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD', 'FMT_CRC_CNTL_INCLUDE_OVERSCAN', 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE', 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE', 'FMT_CRC_CNTL_INTERLACE_MODE', 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM', 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH', 'FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM', 'FMT_CRC_CNTL_INTERLACE_MODE_TOP', 'FMT_CRC_CNTL_ONLY_BLANKB', 'FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD', 'FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK', 'FMT_CRC_CNTL_PSR_MODE_ENABLE', 'FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC', 'FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL', 'FMT_CTX1', 'FMT_DEBUG_CNTL_COLOR_SELECT', 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', 'FMT_DYNAMIC_EXP_MODE', 'FMT_DYNAMIC_EXP_MODE_10to12', 'FMT_DYNAMIC_EXP_MODE_8to12', 'FMT_GB_GR', 'FMT_INVALID', 'FMT_RESERVED_33', 'FMT_RESERVED_36', 'FMT_RESERVED_4', 'FMT_RESERVED_63', 'FMT_SPATIAL_DITHER_MODE', 'FMT_SPATIAL_DITHER_MODE_0', 'FMT_SPATIAL_DITHER_MODE_1', 'FMT_SPATIAL_DITHER_MODE_2', 'FMT_SPATIAL_DITHER_MODE_3', 'FMT_STEREOSYNC_OVR_POL', 'FMT_STEREOSYNC_OVR_POL_INVERTED', 'FMT_STEREOSYNC_OVR_POL_NOT_INVERTED', 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0', 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT', 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN', 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN', 'FMT_X24_8_32_FLOAT', 'FORCE_BINNING_ON', 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', 'FORCE_EARLY_Z', 'FORCE_ENABLE', 'FORCE_LATE_Z', 'FORCE_LIGHT_SLEEP_REQ', 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF', 'FORCE_OPT_AUTO', 'FORCE_OPT_DISABLE', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0', 'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z', 'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH', 'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF', 'FORCE_VBI', 'FORCE_VBI_HIGH', 'FORCE_VBI_LOW', 'FRAG_ALWAYS', 'FRAG_EQUAL', 'FRAG_GEQUAL', 'FRAG_GREATER', 'FRAG_LEQUAL', 'FRAG_LESS', 'FRAG_NEVER', 'FRAG_NOTEQUAL', 'ForceControl', 'GAMUT_REMAP_MODE_1', 'GAMUT_REMAP_MODE_2', 'GAMUT_REMAP_MODE_3', 'GAMUT_REMAP_MODE_BYPASS', 'GATCL1RequestType', 'GATCL1_TYPE_BYPASS', 'GATCL1_TYPE_NORMAL', 'GATCL1_TYPE_SHOOTDOWN', 'GB_EDC_DED_MODE', 'GB_EDC_DED_MODE_HALT', 'GB_EDC_DED_MODE_INT_HALT', 'GB_EDC_DED_MODE_LOG', 'GB_TILING_CONFIG_MACROTABLE_SIZE', 'GB_TILING_CONFIG_TABLE_SIZE', 'GDS_PERFCOUNT_SELECT', 'GDS_PERF_SEL_DS_ADDR_CONFL', 'GDS_PERF_SEL_DS_BANK_CONFL', 'GDS_PERF_SEL_GWS_BYPASS', 'GDS_PERF_SEL_GWS_RELEASED', 'GDS_PERF_SEL_RBUF_HIT', 'GDS_PERF_SEL_RBUF_MISS', 'GDS_PERF_SEL_SE0_SH0_2COMP_REQ', 'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP', 'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP', 'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP', 'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID', 'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP', 'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP', 'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP', 'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH0_NORET', 'GDS_PERF_SEL_SE0_SH0_ORD_CNT', 'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH0_RET', 'GDS_PERF_SEL_SE0_SH1_2COMP_REQ', 'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP', 'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP', 'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP', 'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID', 'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP', 'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP', 'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP', 'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH1_NORET', 'GDS_PERF_SEL_SE0_SH1_ORD_CNT', 'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH1_RET', 'GDS_PERF_SEL_SE1_SH0_2COMP_REQ', 'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP', 'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP', 'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP', 'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID', 'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP', 'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP', 'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP', 'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH0_NORET', 'GDS_PERF_SEL_SE1_SH0_ORD_CNT', 'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH0_RET', 'GDS_PERF_SEL_SE1_SH1_2COMP_REQ', 'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP', 'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP', 'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP', 'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID', 'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP', 'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP', 'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP', 'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH1_NORET', 'GDS_PERF_SEL_SE1_SH1_ORD_CNT', 'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH1_RET', 'GDS_PERF_SEL_SE2_SH0_2COMP_REQ', 'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP', 'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP', 'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP', 'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID', 'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP', 'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP', 'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP', 'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH0_NORET', 'GDS_PERF_SEL_SE2_SH0_ORD_CNT', 'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH0_RET', 'GDS_PERF_SEL_SE2_SH1_2COMP_REQ', 'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP', 'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP', 'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP', 'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID', 'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP', 'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP', 'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP', 'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH1_NORET', 'GDS_PERF_SEL_SE2_SH1_ORD_CNT', 'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH1_RET', 'GDS_PERF_SEL_SE3_SH0_2COMP_REQ', 'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP', 'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP', 'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP', 'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID', 'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP', 'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP', 'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP', 'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH0_NORET', 'GDS_PERF_SEL_SE3_SH0_ORD_CNT', 'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH0_RET', 'GDS_PERF_SEL_SE3_SH1_2COMP_REQ', 'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP', 'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP', 'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP', 'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID', 'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP', 'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP', 'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP', 'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH1_NORET', 'GDS_PERF_SEL_SE3_SH1_ORD_CNT', 'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH1_RET', 'GDS_PERF_SEL_WBUF_FLUSH', 'GDS_PERF_SEL_WBUF_WR', 'GDS_PERF_SEL_WR_COMP', 'GENERICA_STEREOSYNC_SEL', 'GENERICA_STEREOSYNC_SEL_D1', 'GENERICA_STEREOSYNC_SEL_D2', 'GENERICA_STEREOSYNC_SEL_D3', 'GENERICA_STEREOSYNC_SEL_D4', 'GENERICA_STEREOSYNC_SEL_D5', 'GENERICA_STEREOSYNC_SEL_D6', 'GENERICA_STEREOSYNC_SEL_RESERVED', 'GENERICB_STEREOSYNC_SEL', 'GENERICB_STEREOSYNC_SEL_D1', 'GENERICB_STEREOSYNC_SEL_D2', 'GENERICB_STEREOSYNC_SEL_D3', 'GENERICB_STEREOSYNC_SEL_D4', 'GENERICB_STEREOSYNC_SEL_D5', 'GENERICB_STEREOSYNC_SEL_D6', 'GENERICB_STEREOSYNC_SEL_RESERVED', 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL', 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED', 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS', 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED', 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE', 'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL', 'GLOBAL_STATUS_FLUSH_STATUS', 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', 'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA', 'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA', 'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA', 'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA', 'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA', 'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO', 'GRBM_PERF_SEL', 'GRBM_PERF_SEL_BCI_BUSY', 'GRBM_PERF_SEL_CB_BUSY', 'GRBM_PERF_SEL_CB_CLEAN', 'GRBM_PERF_SEL_COUNT', 'GRBM_PERF_SEL_CPAXI_BUSY', 'GRBM_PERF_SEL_CPC_BUSY', 'GRBM_PERF_SEL_CPF_BUSY', 'GRBM_PERF_SEL_CPG_BUSY', 'GRBM_PERF_SEL_CP_BUSY', 'GRBM_PERF_SEL_CP_COHER_BUSY', 'GRBM_PERF_SEL_CP_DMA_BUSY', 'GRBM_PERF_SEL_DB_BUSY', 'GRBM_PERF_SEL_DB_CLEAN', 'GRBM_PERF_SEL_EA_BUSY', 'GRBM_PERF_SEL_GDS_BUSY', 'GRBM_PERF_SEL_GUI_ACTIVE', 'GRBM_PERF_SEL_IA_BUSY', 'GRBM_PERF_SEL_IA_NO_DMA_BUSY', 'GRBM_PERF_SEL_PA_BUSY', 'GRBM_PERF_SEL_RESERVED_0', 'GRBM_PERF_SEL_RESERVED_1', 'GRBM_PERF_SEL_RESERVED_2', 'GRBM_PERF_SEL_RESERVED_3', 'GRBM_PERF_SEL_RESERVED_4', 'GRBM_PERF_SEL_RESERVED_5', 'GRBM_PERF_SEL_RESERVED_6', 'GRBM_PERF_SEL_RLC_BUSY', 'GRBM_PERF_SEL_RMI_BUSY', 'GRBM_PERF_SEL_SC_BUSY', 'GRBM_PERF_SEL_SPI_BUSY', 'GRBM_PERF_SEL_SX_BUSY', 'GRBM_PERF_SEL_TA_BUSY', 'GRBM_PERF_SEL_TC_BUSY', 'GRBM_PERF_SEL_USER_DEFINED', 'GRBM_PERF_SEL_UTCL2_BUSY', 'GRBM_PERF_SEL_VGT_BUSY', 'GRBM_PERF_SEL_WD_BUSY', 'GRBM_PERF_SEL_WD_NO_DMA_BUSY', 'GRBM_SE0_PERF_SEL', 'GRBM_SE0_PERF_SEL_BCI_BUSY', 'GRBM_SE0_PERF_SEL_CB_BUSY', 'GRBM_SE0_PERF_SEL_CB_CLEAN', 'GRBM_SE0_PERF_SEL_COUNT', 'GRBM_SE0_PERF_SEL_DB_BUSY', 'GRBM_SE0_PERF_SEL_DB_CLEAN', 'GRBM_SE0_PERF_SEL_PA_BUSY', 'GRBM_SE0_PERF_SEL_RESERVED_0', 'GRBM_SE0_PERF_SEL_RESERVED_1', 'GRBM_SE0_PERF_SEL_RMI_BUSY', 'GRBM_SE0_PERF_SEL_SC_BUSY', 'GRBM_SE0_PERF_SEL_SPI_BUSY', 'GRBM_SE0_PERF_SEL_SX_BUSY', 'GRBM_SE0_PERF_SEL_TA_BUSY', 'GRBM_SE0_PERF_SEL_USER_DEFINED', 'GRBM_SE0_PERF_SEL_VGT_BUSY', 'GRBM_SE1_PERF_SEL', 'GRBM_SE1_PERF_SEL_BCI_BUSY', 'GRBM_SE1_PERF_SEL_CB_BUSY', 'GRBM_SE1_PERF_SEL_CB_CLEAN', 'GRBM_SE1_PERF_SEL_COUNT', 'GRBM_SE1_PERF_SEL_DB_BUSY', 'GRBM_SE1_PERF_SEL_DB_CLEAN', 'GRBM_SE1_PERF_SEL_PA_BUSY', 'GRBM_SE1_PERF_SEL_RESERVED_0', 'GRBM_SE1_PERF_SEL_RESERVED_1', 'GRBM_SE1_PERF_SEL_RMI_BUSY', 'GRBM_SE1_PERF_SEL_SC_BUSY', 'GRBM_SE1_PERF_SEL_SPI_BUSY', 'GRBM_SE1_PERF_SEL_SX_BUSY', 'GRBM_SE1_PERF_SEL_TA_BUSY', 'GRBM_SE1_PERF_SEL_USER_DEFINED', 'GRBM_SE1_PERF_SEL_VGT_BUSY', 'GRBM_SE2_PERF_SEL', 'GRBM_SE2_PERF_SEL_BCI_BUSY', 'GRBM_SE2_PERF_SEL_CB_BUSY', 'GRBM_SE2_PERF_SEL_CB_CLEAN', 'GRBM_SE2_PERF_SEL_COUNT', 'GRBM_SE2_PERF_SEL_DB_BUSY', 'GRBM_SE2_PERF_SEL_DB_CLEAN', 'GRBM_SE2_PERF_SEL_PA_BUSY', 'GRBM_SE2_PERF_SEL_RESERVED_0', 'GRBM_SE2_PERF_SEL_RESERVED_1', 'GRBM_SE2_PERF_SEL_RMI_BUSY', 'GRBM_SE2_PERF_SEL_SC_BUSY', 'GRBM_SE2_PERF_SEL_SPI_BUSY', 'GRBM_SE2_PERF_SEL_SX_BUSY', 'GRBM_SE2_PERF_SEL_TA_BUSY', 'GRBM_SE2_PERF_SEL_USER_DEFINED', 'GRBM_SE2_PERF_SEL_VGT_BUSY', 'GRBM_SE3_PERF_SEL', 'GRBM_SE3_PERF_SEL_BCI_BUSY', 'GRBM_SE3_PERF_SEL_CB_BUSY', 'GRBM_SE3_PERF_SEL_CB_CLEAN', 'GRBM_SE3_PERF_SEL_COUNT', 'GRBM_SE3_PERF_SEL_DB_BUSY', 'GRBM_SE3_PERF_SEL_DB_CLEAN', 'GRBM_SE3_PERF_SEL_PA_BUSY', 'GRBM_SE3_PERF_SEL_RESERVED_0', 'GRBM_SE3_PERF_SEL_RESERVED_1', 'GRBM_SE3_PERF_SEL_RMI_BUSY', 'GRBM_SE3_PERF_SEL_SC_BUSY', 'GRBM_SE3_PERF_SEL_SPI_BUSY', 'GRBM_SE3_PERF_SEL_SX_BUSY', 'GRBM_SE3_PERF_SEL_TA_BUSY', 'GRBM_SE3_PERF_SEL_USER_DEFINED', 'GRBM_SE3_PERF_SEL_VGT_BUSY', 'GSTHREADID_SIZE', 'GS_CUT_1024', 'GS_CUT_128', 'GS_CUT_256', 'GS_CUT_512', 'GS_OFF', 'GS_SCENARIO_A', 'GS_SCENARIO_B', 'GS_SCENARIO_C', 'GS_SCENARIO_G', 'GS_STAGE_OFF', 'GS_STAGE_ON', 'GroupInterleave', 'HDMI_ACR_0_MULTIPLE_RESERVED', 'HDMI_ACR_1_MULTIPLE', 'HDMI_ACR_2_MULTIPLE', 'HDMI_ACR_3_MULTIPLE_RESERVED', 'HDMI_ACR_4_MULTIPLE', 'HDMI_ACR_5_MULTIPLE_RESERVED', 'HDMI_ACR_6_MULTIPLE_RESERVED', 'HDMI_ACR_7_MULTIPLE_RESERVED', 'HDMI_ACR_AUDIO_PRIORITY', 'HDMI_ACR_CONT', 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE', 'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE', 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', 'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K', 'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K', 'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE', 'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW', 'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK', 'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN', 'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT', 'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE', 'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND', 'HDMI_AUDIO_INFO_SEND', 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', 'HDMI_AUDIO_SEND_MAX_PACKETS', 'HDMI_AVI_INFO_CONT', 'HDMI_AVI_INFO_CONT_DISABLE', 'HDMI_AVI_INFO_CONT_ENABLE', 'HDMI_AVI_INFO_NOT_SEND', 'HDMI_AVI_INFO_PKT_SEND', 'HDMI_AVI_INFO_SEND', 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', 'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DATA_SCRAMBLE_DISABLE', 'HDMI_DATA_SCRAMBLE_EN', 'HDMI_DATA_SCRAMBLE_ENABLE', 'HDMI_DEEP_COLOR_DEPTH', 'HDMI_DEEP_COLOR_DEPTH_24BPP', 'HDMI_DEEP_COLOR_DEPTH_30BPP', 'HDMI_DEEP_COLOR_DEPTH_36BPP', 'HDMI_DEEP_COLOR_DEPTH_RESERVED', 'HDMI_DEFAULT_PAHSE', 'HDMI_DEFAULT_PHASE_IS_0', 'HDMI_DEFAULT_PHASE_IS_1', 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', 'HDMI_ERROR_MASK', 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK', 'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_GC_AVMUTE', 'HDMI_GC_AVMUTE_CONT', 'HDMI_GC_AVMUTE_CONT_DISABLE', 'HDMI_GC_AVMUTE_CONT_ENABLE', 'HDMI_GC_AVMUTE_SET', 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', 'HDMI_GC_CONT_DISABLE', 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', 'HDMI_GC_PKT_SEND', 'HDMI_GC_SEND', 'HDMI_GENERIC0_CONT', 'HDMI_GENERIC0_CONT_DISABLE', 'HDMI_GENERIC0_CONT_ENABLE', 'HDMI_GENERIC0_NOT_SEND', 'HDMI_GENERIC0_PKT_SEND', 'HDMI_GENERIC0_SEND', 'HDMI_GENERIC1_CONT', 'HDMI_GENERIC1_CONT_DISABLE', 'HDMI_GENERIC1_CONT_ENABLE', 'HDMI_GENERIC1_NOT_SEND', 'HDMI_GENERIC1_PKT_SEND', 'HDMI_GENERIC1_SEND', 'HDMI_GENERIC2_CONT', 'HDMI_GENERIC2_CONT_DISABLE', 'HDMI_GENERIC2_CONT_ENABLE', 'HDMI_GENERIC2_NOT_SEND', 'HDMI_GENERIC2_PKT_SEND', 'HDMI_GENERIC2_SEND', 'HDMI_GENERIC3_CONT', 'HDMI_GENERIC3_CONT_DISABLE', 'HDMI_GENERIC3_CONT_ENABLE', 'HDMI_GENERIC3_NOT_SEND', 'HDMI_GENERIC3_PKT_SEND', 'HDMI_GENERIC3_SEND', 'HDMI_ISRC_CONT', 'HDMI_ISRC_CONT_DISABLE', 'HDMI_ISRC_CONT_ENABLE', 'HDMI_ISRC_NOT_SEND', 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND', 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE', 'HDMI_MPEG_INFO_CONT', 'HDMI_MPEG_INFO_CONT_DISABLE', 'HDMI_MPEG_INFO_CONT_ENABLE', 'HDMI_MPEG_INFO_NOT_SEND', 'HDMI_MPEG_INFO_PKT_SEND', 'HDMI_MPEG_INFO_SEND', 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', 'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND', 'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION', 'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD', 'HDMI_PACKING_PHASE_OVERRIDE', 'HDMI_PACKING_PHASE_SET_BY_HW', 'HDMI_PACKING_PHASE_SET_BY_SW', 'HDMI_SEND_MAX_AUDIO_PACKETS', 'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0', 'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON', 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY', 'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0', 'HPD_INT_CONTROL_RX_INT_ACK_1', 'HS_STAGE_OFF', 'HS_STAGE_ON', 'HW_SOURCE_SEL_DSC_JPEG', 'HW_SOURCE_SEL_DSC_VLP', 'HW_SOURCE_SEL_DSC_VUP', 'HW_SOURCE_SEL_NONE', 'I2S0_SPDIF0_SOFT_RESET', 'I2S0_SPDIF0_SOFT_RESET_0', 'I2S0_SPDIF0_SOFT_RESET_1', 'I2S1_SOFT_RESET', 'I2S1_SOFT_RESET_0', 'I2S1_SOFT_RESET_1', 'I2S_LRCLK_HIGH_LEFT', 'I2S_LRCLK_LOW_LEFT', 'I2S_LRCLK_POLARITY', 'I2S_SAMPLE_ALIGNMENT', 'I2S_SAMPLE_BIT_ORDER', 'I2S_SAMPLE_BIT_ORDER_LSB', 'I2S_SAMPLE_BIT_ORDER_MSB', 'I2S_SAMPLE_LEFT_ALIGNED', 'I2S_SAMPLE_RIGHT_ALIGNED', 'I2S_WORD_ALIGNMENT', 'I2S_WORD_ALTERNATE_ALIGNMENT', 'I2S_WORD_I2S_ALIGNMENT', 'I2S_WORD_SIZE', 'I2S_WORD_SIZE_16', 'I2S_WORD_SIZE_32', 'IA_PERFCOUNT_SELECT', 'ID_STREAM_DISABLE_ACKED', 'ID_STREAM_DISABLE_NO_ACK', 'IH_PERF_SEL', 'IH_PERF_SEL_BIF_LINE0_FALLING', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', 'IH_PERF_SEL_BIF_LINE0_RISING', 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', 'IH_PERF_SEL_BUFFER_IDLE', 'IH_PERF_SEL_CLIENT0_INT', 'IH_PERF_SEL_CLIENT10_INT', 'IH_PERF_SEL_CLIENT11_INT', 'IH_PERF_SEL_CLIENT12_INT', 'IH_PERF_SEL_CLIENT13_INT', 'IH_PERF_SEL_CLIENT14_INT', 'IH_PERF_SEL_CLIENT15_INT', 'IH_PERF_SEL_CLIENT16_INT', 'IH_PERF_SEL_CLIENT17_INT', 'IH_PERF_SEL_CLIENT18_INT', 'IH_PERF_SEL_CLIENT19_INT', 'IH_PERF_SEL_CLIENT1_INT', 'IH_PERF_SEL_CLIENT20_INT', 'IH_PERF_SEL_CLIENT21_INT', 'IH_PERF_SEL_CLIENT22_INT', 'IH_PERF_SEL_CLIENT23_INT', 'IH_PERF_SEL_CLIENT24_INT', 'IH_PERF_SEL_CLIENT25_INT', 'IH_PERF_SEL_CLIENT26_INT', 'IH_PERF_SEL_CLIENT27_INT', 'IH_PERF_SEL_CLIENT28_INT', 'IH_PERF_SEL_CLIENT29_INT', 'IH_PERF_SEL_CLIENT2_INT', 'IH_PERF_SEL_CLIENT30_INT', 'IH_PERF_SEL_CLIENT31_INT', 'IH_PERF_SEL_CLIENT3_INT', 'IH_PERF_SEL_CLIENT4_INT', 'IH_PERF_SEL_CLIENT5_INT', 'IH_PERF_SEL_CLIENT6_INT', 'IH_PERF_SEL_CLIENT7_INT', 'IH_PERF_SEL_CLIENT8_INT', 'IH_PERF_SEL_CLIENT9_INT', 'IH_PERF_SEL_CYCLE', 'IH_PERF_SEL_IDLE', 'IH_PERF_SEL_INPUT_IDLE', 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', 'IH_PERF_SEL_MC_WR_CLEAN_STALL', 'IH_PERF_SEL_MC_WR_COUNT', 'IH_PERF_SEL_MC_WR_IDLE', 'IH_PERF_SEL_MC_WR_STALL', 'IH_PERF_SEL_RB0_FULL', 'IH_PERF_SEL_RB0_FULL_VF0', 'IH_PERF_SEL_RB0_FULL_VF1', 'IH_PERF_SEL_RB0_FULL_VF10', 'IH_PERF_SEL_RB0_FULL_VF11', 'IH_PERF_SEL_RB0_FULL_VF12', 'IH_PERF_SEL_RB0_FULL_VF13', 'IH_PERF_SEL_RB0_FULL_VF14', 'IH_PERF_SEL_RB0_FULL_VF15', 'IH_PERF_SEL_RB0_FULL_VF2', 'IH_PERF_SEL_RB0_FULL_VF3', 'IH_PERF_SEL_RB0_FULL_VF4', 'IH_PERF_SEL_RB0_FULL_VF5', 'IH_PERF_SEL_RB0_FULL_VF6', 'IH_PERF_SEL_RB0_FULL_VF7', 'IH_PERF_SEL_RB0_FULL_VF8', 'IH_PERF_SEL_RB0_FULL_VF9', 'IH_PERF_SEL_RB0_OVERFLOW', 'IH_PERF_SEL_RB0_OVERFLOW_VF0', 'IH_PERF_SEL_RB0_OVERFLOW_VF1', 'IH_PERF_SEL_RB0_OVERFLOW_VF10', 'IH_PERF_SEL_RB0_OVERFLOW_VF11', 'IH_PERF_SEL_RB0_OVERFLOW_VF12', 'IH_PERF_SEL_RB0_OVERFLOW_VF13', 'IH_PERF_SEL_RB0_OVERFLOW_VF14', 'IH_PERF_SEL_RB0_OVERFLOW_VF15', 'IH_PERF_SEL_RB0_OVERFLOW_VF2', 'IH_PERF_SEL_RB0_OVERFLOW_VF3', 'IH_PERF_SEL_RB0_OVERFLOW_VF4', 'IH_PERF_SEL_RB0_OVERFLOW_VF5', 'IH_PERF_SEL_RB0_OVERFLOW_VF6', 'IH_PERF_SEL_RB0_OVERFLOW_VF7', 'IH_PERF_SEL_RB0_OVERFLOW_VF8', 'IH_PERF_SEL_RB0_OVERFLOW_VF9', 'IH_PERF_SEL_RB0_RPTR_WRAP', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRAP', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 'IH_PERF_SEL_RB1_FULL', 'IH_PERF_SEL_RB1_FULL_VF0', 'IH_PERF_SEL_RB1_FULL_VF1', 'IH_PERF_SEL_RB1_FULL_VF10', 'IH_PERF_SEL_RB1_FULL_VF11', 'IH_PERF_SEL_RB1_FULL_VF12', 'IH_PERF_SEL_RB1_FULL_VF13', 'IH_PERF_SEL_RB1_FULL_VF14', 'IH_PERF_SEL_RB1_FULL_VF15', 'IH_PERF_SEL_RB1_FULL_VF2', 'IH_PERF_SEL_RB1_FULL_VF3', 'IH_PERF_SEL_RB1_FULL_VF4', 'IH_PERF_SEL_RB1_FULL_VF5', 'IH_PERF_SEL_RB1_FULL_VF6', 'IH_PERF_SEL_RB1_FULL_VF7', 'IH_PERF_SEL_RB1_FULL_VF8', 'IH_PERF_SEL_RB1_FULL_VF9', 'IH_PERF_SEL_RB1_OVERFLOW', 'IH_PERF_SEL_RB1_OVERFLOW_VF0', 'IH_PERF_SEL_RB1_OVERFLOW_VF1', 'IH_PERF_SEL_RB1_OVERFLOW_VF10', 'IH_PERF_SEL_RB1_OVERFLOW_VF11', 'IH_PERF_SEL_RB1_OVERFLOW_VF12', 'IH_PERF_SEL_RB1_OVERFLOW_VF13', 'IH_PERF_SEL_RB1_OVERFLOW_VF14', 'IH_PERF_SEL_RB1_OVERFLOW_VF15', 'IH_PERF_SEL_RB1_OVERFLOW_VF2', 'IH_PERF_SEL_RB1_OVERFLOW_VF3', 'IH_PERF_SEL_RB1_OVERFLOW_VF4', 'IH_PERF_SEL_RB1_OVERFLOW_VF5', 'IH_PERF_SEL_RB1_OVERFLOW_VF6', 'IH_PERF_SEL_RB1_OVERFLOW_VF7', 'IH_PERF_SEL_RB1_OVERFLOW_VF8', 'IH_PERF_SEL_RB1_OVERFLOW_VF9', 'IH_PERF_SEL_RB1_RPTR_WRAP', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB1_WPTR_WRAP', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_FULL', 'IH_PERF_SEL_RB2_FULL_VF0', 'IH_PERF_SEL_RB2_FULL_VF1', 'IH_PERF_SEL_RB2_FULL_VF10', 'IH_PERF_SEL_RB2_FULL_VF11', 'IH_PERF_SEL_RB2_FULL_VF12', 'IH_PERF_SEL_RB2_FULL_VF13', 'IH_PERF_SEL_RB2_FULL_VF14', 'IH_PERF_SEL_RB2_FULL_VF15', 'IH_PERF_SEL_RB2_FULL_VF2', 'IH_PERF_SEL_RB2_FULL_VF3', 'IH_PERF_SEL_RB2_FULL_VF4', 'IH_PERF_SEL_RB2_FULL_VF5', 'IH_PERF_SEL_RB2_FULL_VF6', 'IH_PERF_SEL_RB2_FULL_VF7', 'IH_PERF_SEL_RB2_FULL_VF8', 'IH_PERF_SEL_RB2_FULL_VF9', 'IH_PERF_SEL_RB2_OVERFLOW', 'IH_PERF_SEL_RB2_OVERFLOW_VF0', 'IH_PERF_SEL_RB2_OVERFLOW_VF1', 'IH_PERF_SEL_RB2_OVERFLOW_VF10', 'IH_PERF_SEL_RB2_OVERFLOW_VF11', 'IH_PERF_SEL_RB2_OVERFLOW_VF12', 'IH_PERF_SEL_RB2_OVERFLOW_VF13', 'IH_PERF_SEL_RB2_OVERFLOW_VF14', 'IH_PERF_SEL_RB2_OVERFLOW_VF15', 'IH_PERF_SEL_RB2_OVERFLOW_VF2', 'IH_PERF_SEL_RB2_OVERFLOW_VF3', 'IH_PERF_SEL_RB2_OVERFLOW_VF4', 'IH_PERF_SEL_RB2_OVERFLOW_VF5', 'IH_PERF_SEL_RB2_OVERFLOW_VF6', 'IH_PERF_SEL_RB2_OVERFLOW_VF7', 'IH_PERF_SEL_RB2_OVERFLOW_VF8', 'IH_PERF_SEL_RB2_OVERFLOW_VF9', 'IH_PERF_SEL_RB2_RPTR_WRAP', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_WPTR_WRAP', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 'IMG_DATA_FORMAT', 'IMG_DATA_FORMAT_10_10_10_2', 'IMG_DATA_FORMAT_10_11_11', 'IMG_DATA_FORMAT_11_11_10', 'IMG_DATA_FORMAT_16', 'IMG_DATA_FORMAT_16_16', 'IMG_DATA_FORMAT_16_16_16_16', 'IMG_DATA_FORMAT_16_AS_16_16_16_16', 'IMG_DATA_FORMAT_16_AS_32_32', 'IMG_DATA_FORMAT_16_AS_32_32_32_32', 'IMG_DATA_FORMAT_1_5_5_5', 'IMG_DATA_FORMAT_24_8', 'IMG_DATA_FORMAT_2_10_10_10', 'IMG_DATA_FORMAT_32', 'IMG_DATA_FORMAT_32_32', 'IMG_DATA_FORMAT_32_32_32', 'IMG_DATA_FORMAT_32_32_32_32', 'IMG_DATA_FORMAT_32_AS_32_32_32_32', 'IMG_DATA_FORMAT_4_4', 'IMG_DATA_FORMAT_4_4_4_4', 'IMG_DATA_FORMAT_5_5_5_1', 'IMG_DATA_FORMAT_5_6_5', 'IMG_DATA_FORMAT_5_9_9_9', 'IMG_DATA_FORMAT_6E4', 'IMG_DATA_FORMAT_6_5_5', 'IMG_DATA_FORMAT_8', 'IMG_DATA_FORMAT_8_24', 'IMG_DATA_FORMAT_8_8', 'IMG_DATA_FORMAT_8_8_8_8', 'IMG_DATA_FORMAT_8_AS_32', 'IMG_DATA_FORMAT_8_AS_32_32', 'IMG_DATA_FORMAT_8_AS_8_8_8_8', 'IMG_DATA_FORMAT_ASTC_2D_HDR', 'IMG_DATA_FORMAT_ASTC_2D_LDR', 'IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB', 'IMG_DATA_FORMAT_ASTC_3D_HDR', 'IMG_DATA_FORMAT_ASTC_3D_LDR', 'IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB', 'IMG_DATA_FORMAT_BC1', 'IMG_DATA_FORMAT_BC2', 'IMG_DATA_FORMAT_BC3', 'IMG_DATA_FORMAT_BC4', 'IMG_DATA_FORMAT_BC5', 'IMG_DATA_FORMAT_BC6', 'IMG_DATA_FORMAT_BC7', 'IMG_DATA_FORMAT_BG_RG', 'IMG_DATA_FORMAT_ETC2_R', 'IMG_DATA_FORMAT_ETC2_RG', 'IMG_DATA_FORMAT_ETC2_RGB', 'IMG_DATA_FORMAT_ETC2_RGBA', 'IMG_DATA_FORMAT_ETC2_RGBA1', 'IMG_DATA_FORMAT_FMASK', 'IMG_DATA_FORMAT_GB_GR', 'IMG_DATA_FORMAT_INVALID', 'IMG_DATA_FORMAT_N_IN_16', 'IMG_DATA_FORMAT_N_IN_16_16', 'IMG_DATA_FORMAT_N_IN_16_16_16_16', 'IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16', 'IMG_DATA_FORMAT_RESERVED_15', 'IMG_DATA_FORMAT_RESERVED_29', 'IMG_DATA_FORMAT_RESERVED_30', 'IMG_DATA_FORMAT_RESERVED_56', 'IMG_DATA_FORMAT_RESERVED_59', 'IMG_DATA_FORMAT_RESERVED_60', 'IMG_DATA_FORMAT_X24_8_32', 'IMG_NUM_FORMAT', 'IMG_NUM_FORMAT_ASTC_2D', 'IMG_NUM_FORMAT_ASTC_2D_10x10', 'IMG_NUM_FORMAT_ASTC_2D_10x5', 'IMG_NUM_FORMAT_ASTC_2D_10x6', 'IMG_NUM_FORMAT_ASTC_2D_10x8', 'IMG_NUM_FORMAT_ASTC_2D_12x10', 'IMG_NUM_FORMAT_ASTC_2D_12x12', 'IMG_NUM_FORMAT_ASTC_2D_4x4', 'IMG_NUM_FORMAT_ASTC_2D_5x4', 'IMG_NUM_FORMAT_ASTC_2D_5x5', 'IMG_NUM_FORMAT_ASTC_2D_6x5', 'IMG_NUM_FORMAT_ASTC_2D_6x6', 'IMG_NUM_FORMAT_ASTC_2D_8x5', 'IMG_NUM_FORMAT_ASTC_2D_8x6', 'IMG_NUM_FORMAT_ASTC_2D_8x8', 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_14', 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_15', 'IMG_NUM_FORMAT_ASTC_3D', 'IMG_NUM_FORMAT_ASTC_3D_3x3x3', 'IMG_NUM_FORMAT_ASTC_3D_4x3x3', 'IMG_NUM_FORMAT_ASTC_3D_4x4x3', 'IMG_NUM_FORMAT_ASTC_3D_4x4x4', 'IMG_NUM_FORMAT_ASTC_3D_5x4x4', 'IMG_NUM_FORMAT_ASTC_3D_5x5x4', 'IMG_NUM_FORMAT_ASTC_3D_5x5x5', 'IMG_NUM_FORMAT_ASTC_3D_6x5x5', 'IMG_NUM_FORMAT_ASTC_3D_6x6x5', 'IMG_NUM_FORMAT_ASTC_3D_6x6x6', 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_10', 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_11', 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_12', 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_13', 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_14', 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_15', 'IMG_NUM_FORMAT_FLOAT', 'IMG_NUM_FORMAT_FMASK', 'IMG_NUM_FORMAT_FMASK_16_16_1', 'IMG_NUM_FORMAT_FMASK_16_8_2', 'IMG_NUM_FORMAT_FMASK_32_16_2', 'IMG_NUM_FORMAT_FMASK_32_8_4', 'IMG_NUM_FORMAT_FMASK_32_8_8', 'IMG_NUM_FORMAT_FMASK_64_16_4', 'IMG_NUM_FORMAT_FMASK_64_16_8', 'IMG_NUM_FORMAT_FMASK_8_2_1', 'IMG_NUM_FORMAT_FMASK_8_2_2', 'IMG_NUM_FORMAT_FMASK_8_4_1', 'IMG_NUM_FORMAT_FMASK_8_4_2', 'IMG_NUM_FORMAT_FMASK_8_4_4', 'IMG_NUM_FORMAT_FMASK_8_8_1', 'IMG_NUM_FORMAT_FMASK_RESERVED_13', 'IMG_NUM_FORMAT_FMASK_RESERVED_14', 'IMG_NUM_FORMAT_FMASK_RESERVED_15', 'IMG_NUM_FORMAT_N_IN_16', 'IMG_NUM_FORMAT_N_IN_16_RESERVED_0', 'IMG_NUM_FORMAT_N_IN_16_RESERVED_10', 'IMG_NUM_FORMAT_N_IN_16_RESERVED_11', 'IMG_NUM_FORMAT_N_IN_16_RESERVED_12', 'IMG_NUM_FORMAT_N_IN_16_RESERVED_13', 'IMG_NUM_FORMAT_N_IN_16_RESERVED_14', 'IMG_NUM_FORMAT_N_IN_16_RESERVED_15', 'IMG_NUM_FORMAT_N_IN_16_RESERVED_3', 'IMG_NUM_FORMAT_N_IN_16_RESERVED_6', 'IMG_NUM_FORMAT_N_IN_16_RESERVED_9', 'IMG_NUM_FORMAT_N_IN_16_UINT_10', 'IMG_NUM_FORMAT_N_IN_16_UINT_9', 'IMG_NUM_FORMAT_N_IN_16_UNORM_10', 'IMG_NUM_FORMAT_N_IN_16_UNORM_9', 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10', 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9', 'IMG_NUM_FORMAT_RESERVED_10', 'IMG_NUM_FORMAT_RESERVED_11', 'IMG_NUM_FORMAT_RESERVED_12', 'IMG_NUM_FORMAT_RESERVED_13', 'IMG_NUM_FORMAT_RESERVED_14', 'IMG_NUM_FORMAT_RESERVED_15', 'IMG_NUM_FORMAT_RESERVED_8', 'IMG_NUM_FORMAT_SINT', 'IMG_NUM_FORMAT_SNORM', 'IMG_NUM_FORMAT_SRGB', 'IMG_NUM_FORMAT_SSCALED', 'IMG_NUM_FORMAT_UINT', 'IMG_NUM_FORMAT_UNORM', 'IMG_NUM_FORMAT_UNORM_UINT', 'IMG_NUM_FORMAT_USCALED', 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY', 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID', 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', 'INGAMMA_MODE_BYPASS', 'INGAMMA_MODE_FIX', 'INGAMMA_MODE_FLOAT', 'INPUTCSC_MODE_A', 'INPUTCSC_MODE_B', 'INPUTCSC_MODE_BYPASS', 'INPUTCSC_MODE_UNITY', 'INPUTCSC_ROUND', 'INPUTCSC_TRUNCATE', 'INPUTCSC_TYPE_10_2', 'INPUTCSC_TYPE_12_0', 'INPUTCSC_TYPE_8_4', 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', 'INPUT_INNER_COVERAGE', 'INST_ID_ECC_INTERRUPT_MSG', 'INST_ID_HOST_REG_TRAP_MSG', 'INST_ID_HW_TRAP', 'INST_ID_KILL_SEQ', 'INST_ID_PRIV_START', 'INST_ID_SPI_WREXEC', 'INST_ID_TTRACE_NEW_PC_MSG', 'INTERLACE_SOURCE_INTERLEAVE', 'INTERLACE_SOURCE_PROGRESSIVE', 'INTERLACE_SOURCE_STACK', 'INTERLEAVE_DIS', 'INTERLEAVE_EN', 'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD', 'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP', 'IQ_SCH_WAVE_MSG', 'IQ_SEM_REARM', 'JITTER_REMOVE_DISABLE', 'LATE_Z', 'LBV_DITHER_EN', 'LBV_DOWNSCALE_PREFETCH_EN', 'LBV_DYNAMIC_PIXEL_DEPTH', 'LBV_INTERLEAVE_EN', 'LBV_MEMORY_CONFIG', 'LBV_PIXEL_DEPTH', 'LBV_PIXEL_EXPAN_MODE', 'LBV_PIXEL_REDUCE_MODE', 'LBV_SYNC_DURATION', 'LBV_SYNC_RESET_SEL2', 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK', 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL', 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET', 'LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK', 'LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL', 'LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET', 'LB_DATA_FORMAT_ALPHA_DISABLE', 'LB_DATA_FORMAT_ALPHA_EN', 'LB_DATA_FORMAT_ALPHA_ENABLE', 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH', 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP', 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP', 'LB_DATA_FORMAT_INTERLEAVE_DISABLE', 'LB_DATA_FORMAT_INTERLEAVE_EN', 'LB_DATA_FORMAT_INTERLEAVE_ENABLE', 'LB_DATA_FORMAT_PIXEL_DEPTH', 'LB_DATA_FORMAT_PIXEL_DEPTH_18BPP', 'LB_DATA_FORMAT_PIXEL_DEPTH_24BPP', 'LB_DATA_FORMAT_PIXEL_DEPTH_30BPP', 'LB_DATA_FORMAT_PIXEL_DEPTH_36BPP', 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE', 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION', 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION', 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE', 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING', 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION', 'LB_DATA_FORMAT_REQUEST_MODE', 'LB_DATA_FORMAT_REQUEST_MODE_NORMAL', 'LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE', 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE', 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE', 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO', 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO', 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE', 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO', 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL', 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0', 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1', 'LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE', 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE', 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE', 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK', 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE', 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE', 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK', 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE', 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE', 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK', 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE', 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN', 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE', 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE', 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE', 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN', 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL', 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET', 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK', 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0', 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1', 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE', 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE', 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP', 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP', 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE', 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN', 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE', 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE', 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG', 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE', 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT', 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION', 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS', 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS', 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS', 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS', 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL', 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2', 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK', 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC', 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE', 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET', 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK', 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET', 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN', 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0', 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1', 'LB_VBLANK_STATUS_VBLANK_ACK', 'LB_VBLANK_STATUS_VBLANK_CLEAR', 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE', 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED', 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED', 'LB_VBLANK_STATUS_VBLANK_NORMAL', 'LB_VLINE2_START_END_VLINE2_INV', 'LB_VLINE2_START_END_VLINE2_INVERSE', 'LB_VLINE2_START_END_VLINE2_NORMAL', 'LB_VLINE2_STATUS_VLINE2_ACK', 'LB_VLINE2_STATUS_VLINE2_CLEAR', 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE', 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED', 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED', 'LB_VLINE2_STATUS_VLINE2_NORMAL', 'LB_VLINE_START_END_VLINE_INV', 'LB_VLINE_START_END_VLINE_INVERSE', 'LB_VLINE_START_END_VLINE_NORMAL', 'LB_VLINE_STATUS_VLINE_ACK', 'LB_VLINE_STATUS_VLINE_CLEAR', 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE', 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED', 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED', 'LB_VLINE_STATUS_VLINE_NORMAL', 'LINESTRIP', 'LPT_NUM_BANKS_16BANK', 'LPT_NUM_BANKS_2BANK', 'LPT_NUM_BANKS_32BANK', 'LPT_NUM_BANKS_4BANK', 'LPT_NUM_BANKS_8BANK', 'LPT_NUM_PIPES_1CH', 'LPT_NUM_PIPES_2CH', 'LPT_NUM_PIPES_4CH', 'LPT_NUM_PIPES_8CH', 'LS_STAGE_OFF', 'LS_STAGE_ON', 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', 'LptNumBanks', 'LptNumPipes', 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK', 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE', 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE', 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK', 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK', 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE', 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE', 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE', 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN', 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD', 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE', 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE', 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN', 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA', 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA', 'MEMORY_CONFIG_0', 'MEMORY_CONFIG_1', 'MEMORY_CONFIG_2', 'MEMORY_CONFIG_3', 'MEM_ARB_MODE_AGE', 'MEM_ARB_MODE_BOTH', 'MEM_ARB_MODE_FIXED', 'MEM_ARB_MODE_WEIGHT', 'MEM_PWR_DIS_CTRL', 'MEM_PWR_FORCE_CTRL', 'MEM_PWR_FORCE_CTRL2', 'MEM_PWR_SEL_CTRL', 'MEM_PWR_SEL_CTRL2', 'ME_ID0', 'ME_ID1', 'ME_ID2', 'ME_ID3', 'MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MICRO_TILE_MODE_DISPLAY_2D', 'MICRO_TILE_MODE_DISPLAY_3D', 'MICRO_TILE_MODE_LINEAR', 'MICRO_TILE_MODE_ROTATED', 'MICRO_TILE_MODE_STD_2D', 'MICRO_TILE_MODE_STD_3D', 'MICRO_TILE_MODE_Z_2D', 'MICRO_TILE_MODE_Z_3D', 'MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MSA_MISC0_OVERRIDE_DISABLE', 'MSA_MISC0_OVERRIDE_ENABLE', 'MSA_MISC1_BIT7_OVERRIDE_DISABLE', 'MSA_MISC1_BIT7_OVERRIDE_ENABLE', 'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED', 'MTYPE', 'MTYPE_CC', 'MTYPE_NC', 'MTYPE_RW', 'MTYPE_UC', 'MTYPE_WC', 'MULT_16', 'MULT_8', 'MVP_CLK_SRC_SEL', 'MVP_CLK_SRC_SEL_IO_1', 'MVP_CLK_SRC_SEL_IO_2', 'MVP_CLK_SRC_SEL_REFCLK', 'MVP_CLK_SRC_SEL_RSRV', 'MVP_SOFT_RESET', 'MVP_SOFT_RESET_0', 'MVP_SOFT_RESET_1', 'MacroTileAspect', 'MemArbMode', 'MicroTileMode', 'MultiGPUTileSize', 'NOT_SENT', 'NO_DIST', 'NO_FORCE', 'NO_FORCE_REQ', 'NO_FORCE_REQUEST', 'NUMBER_FLOAT', 'NUMBER_SINT', 'NUMBER_SNORM', 'NUMBER_SRGB', 'NUMBER_SSCALED', 'NUMBER_UINT', 'NUMBER_UNORM', 'NUMBER_USCALED', 'NUM_SIMD_PER_CU', 'NonDispTilingOrder', 'NumBanks', 'NumBanksConfig', 'NumGPUs', 'NumLowerPipes', 'NumMaxCompressedFragments', 'NumPipes', 'NumRbPerShaderEngine', 'NumShaderEngines', 'OFFCHIP_HS_DEALLOC', 'OFF_SEQ', 'ON_SEQ', 'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', 'OPT_COMB_MAX', 'OPT_COMB_MIN', 'OPT_COMB_NONE', 'OPT_COMB_REVSUBTRACT', 'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', 'OUTPUT_LINE', 'OUTPUT_POINT', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY', 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', 'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', 'OVERRIDE_CGTT_DCEFCLK', 'OVERRIDE_CGTT_DCEFCLK_NOOP', 'OVERRIDE_CGTT_SCLK', 'OVERRIDE_CGTT_SCLK_NOOP', 'PART_FRAC_EVEN', 'PART_FRAC_ODD', 'PART_INTEGER', 'PART_POW2', 'PATCHES', 'PERFCOUNTER_ACTIVE', 'PERFCOUNTER_CNT0_STATE', 'PERFCOUNTER_CNT0_STATE_FREEZE', 'PERFCOUNTER_CNT0_STATE_HW', 'PERFCOUNTER_CNT0_STATE_RESET', 'PERFCOUNTER_CNT0_STATE_START', 'PERFCOUNTER_CNT1_STATE', 'PERFCOUNTER_CNT1_STATE_FREEZE', 'PERFCOUNTER_CNT1_STATE_HW', 'PERFCOUNTER_CNT1_STATE_RESET', 'PERFCOUNTER_CNT1_STATE_START', 'PERFCOUNTER_CNT2_STATE', 'PERFCOUNTER_CNT2_STATE_FREEZE', 'PERFCOUNTER_CNT2_STATE_HW', 'PERFCOUNTER_CNT2_STATE_RESET', 'PERFCOUNTER_CNT2_STATE_START', 'PERFCOUNTER_CNT3_STATE', 'PERFCOUNTER_CNT3_STATE_FREEZE', 'PERFCOUNTER_CNT3_STATE_HW', 'PERFCOUNTER_CNT3_STATE_RESET', 'PERFCOUNTER_CNT3_STATE_START', 'PERFCOUNTER_CNT4_STATE', 'PERFCOUNTER_CNT4_STATE_FREEZE', 'PERFCOUNTER_CNT4_STATE_HW', 'PERFCOUNTER_CNT4_STATE_RESET', 'PERFCOUNTER_CNT4_STATE_START', 'PERFCOUNTER_CNT5_STATE', 'PERFCOUNTER_CNT5_STATE_FREEZE', 'PERFCOUNTER_CNT5_STATE_HW', 'PERFCOUNTER_CNT5_STATE_RESET', 'PERFCOUNTER_CNT5_STATE_START', 'PERFCOUNTER_CNT6_STATE', 'PERFCOUNTER_CNT6_STATE_FREEZE', 'PERFCOUNTER_CNT6_STATE_HW', 'PERFCOUNTER_CNT6_STATE_RESET', 'PERFCOUNTER_CNT6_STATE_START', 'PERFCOUNTER_CNT7_STATE', 'PERFCOUNTER_CNT7_STATE_FREEZE', 'PERFCOUNTER_CNT7_STATE_HW', 'PERFCOUNTER_CNT7_STATE_RESET', 'PERFCOUNTER_CNT7_STATE_START', 'PERFCOUNTER_CNTL_SEL', 'PERFCOUNTER_CNTL_SEL_0', 'PERFCOUNTER_CNTL_SEL_1', 'PERFCOUNTER_CNTL_SEL_2', 'PERFCOUNTER_CNTL_SEL_3', 'PERFCOUNTER_CNTL_SEL_4', 'PERFCOUNTER_CNTL_SEL_5', 'PERFCOUNTER_CNTL_SEL_6', 'PERFCOUNTER_CNTL_SEL_7', 'PERFCOUNTER_CNTOFF_START_DIS', 'PERFCOUNTER_CNTOFF_START_DISABLE', 'PERFCOUNTER_CNTOFF_START_ENABLE', 'PERFCOUNTER_COUNTED_VALUE_TYPE', 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL', 'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0', 'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16', 'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0', 'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36', 'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_INC_MODE', 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB', 'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE', 'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE', 'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE', 'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL', 'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE', 'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK', 'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE', 'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN', 'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE', 'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL', 'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START', 'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL', 'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1', 'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL', 'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL', 'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3', 'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL', 'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL', 'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5', 'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL', 'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL', 'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7', 'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL', 'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR', 'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN', 'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE', 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE', 'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE', 'PERFMON_COUNTER_MODE_ACCUM', 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', 'PERFMON_COUNTER_MODE_DIRTY', 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', 'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED', 'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE', 'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', 'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', 'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5', 'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7', 'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1', 'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE', 'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET', 'PERFMON_STATE_START', 'PERF_PAPC_CCGSM_BUSY', 'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED', 'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE', 'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY', 'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY', 'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY', 'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED', 'PERF_PAPC_CLPRIM_STARVED_CCGSM', 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM', 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM', 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM', 'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM', 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', 'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_DISABLE_PIPE', 'PERF_PAPC_PASX_FIRST_DEAD', 'PERF_PAPC_PASX_FIRST_VECTOR', 'PERF_PAPC_PASX_REC_BUSY', 'PERF_PAPC_PASX_REC_IDLE', 'PERF_PAPC_PASX_REC_STALLED', 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', 'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ', 'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE', 'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', 'PERF_PAPC_PASX_SE0_REQ', 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 'PERF_PAPC_PASX_SE1_REQ', 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 'PERF_PAPC_PASX_SECOND_DEAD', 'PERF_PAPC_PASX_SECOND_VECTOR', 'PERF_PAPC_PASX_VTX_KILL_DISCARD', 'PERF_PAPC_PASX_VTX_NAN_DISCARD', 'PERF_PAPC_PA_INPUT_END_OF_PACKET', 'PERF_PAPC_PA_INPUT_EVENT_FLAG', 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', 'PERF_PAPC_PA_INPUT_NULL_PRIM', 'PERF_PAPC_PA_INPUT_PRIM', 'PERF_PAPC_PA_REG_SCLK_VLD', 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', 'PERF_PAPC_SU_BUSY', 'PERF_PAPC_SU_CULLED_PRIM', 'PERF_PAPC_SU_DYN_SCLK_VLD', 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', 'PERF_PAPC_SU_IDLE', 'PERF_PAPC_SU_INPUT_CLIP_PRIM', 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', 'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM', 'PERF_PAPC_SU_INPUT_PRIM_DUAL', 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG', 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM', 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', 'PERF_PAPC_SU_POLYMODE_BACK_CULL', 'PERF_PAPC_SU_POLYMODE_FACE_CULL', 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', 'PERF_PAPC_SU_SE01_STALLED_SC', 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', 'PERF_PAPC_SU_SE0_STALLED_SC', 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', 'PERF_PAPC_SU_SE1_STALLED_SC', 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', 'PERF_PAPC_SU_SE2_STALLED_SC', 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', 'PERF_PAPC_SU_SE3_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC', 'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', 'PERSISTENT_SPACE_END', 'PERSISTENT_SPACE_START', 'PIPELINESTAT_START', 'PIPELINESTAT_STOP', 'PIPE_ID0', 'PIPE_ID1', 'PIPE_ID2', 'PIPE_ID3', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG', 'PIPE_PIXEL_RATE_PLL_SOURCE', 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE', 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL', 'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIXEL_DEPTH_18BPP', 'PIXEL_DEPTH_24BPP', 'PIXEL_DEPTH_30BPP', 'PIXEL_DEPTH_38BPP', 'PIXEL_EXPAN_MODE_DYN_EXP', 'PIXEL_EXPAN_MODE_ZERO_EXP', 'PIXEL_FORMAT_RGB_444', 'PIXEL_FORMAT_YCBCR_422', 'PIXEL_FORMAT_YCBCR_444', 'PIXEL_FORMAT_Y_ONLY', 'PIXEL_PIPE_OCCLUSION_COUNT_0', 'PIXEL_PIPE_OCCLUSION_COUNT_1', 'PIXEL_PIPE_OCCLUSION_COUNT_2', 'PIXEL_PIPE_OCCLUSION_COUNT_3', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL', 'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET', 'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS', 'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS', 'PIXEL_REDUCE_MODE_ROUNDING', 'PIXEL_REDUCE_MODE_TRUNCATION', 'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE', 'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM_ASSERT_RESET', 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', 'POINTLIST', 'PRESCALE_MODE_BYPASS', 'PRESCALE_MODE_PROGRAM', 'PRESCALE_MODE_UNITY', 'PROG_SEQ', 'PSLC_ASAP', 'PSLC_AUTO', 'PSLC_COUNTDOWN', 'PSLC_ON_HANG_ONLY', 'PS_DONE', 'PS_PARTIAL_FLUSH', 'PULSE_MODE_OPT_NO_HSA', 'PULSE_MODE_OPT_SEND', 'PerfCounter_Vals', 'PipeConfig', 'PipeInterleaveSize', 'PipeTiling', 'PixelPipeCounterId', 'PixelPipeStride', 'PkrMap', 'PkrXsel', 'PkrXsel2', 'PkrYsel', 'QuadExportFormat', 'QuadExportFormatOld', 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1', 'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3', 'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1', 'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3', 'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1', 'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3', 'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1', 'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3', 'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1', 'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3', 'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1', 'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3', 'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1', 'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1', 'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1', 'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3', 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0', 'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2', 'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0', 'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2', 'RASTER_CONFIG_SE_PAIR_MAP_3', 'RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE', 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE', 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_XSEL_128_WIDE_TILE', 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_YSEL_128_WIDE_TILE', 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', 'READ_256_BITS', 'READ_512_BITS', 'READ_SEQ', 'RECTLIST', 'REFCLK_CLOCK_EN', 'REFCLK_CLOCK_EN_ALLOW_SRC_SEL', 'REFCLK_CLOCK_EN_XTALIN_CLK', 'REFCLK_SRC_SEL', 'REFCLK_SRC_SEL_CPL_REFCLK', 'REFCLK_SRC_SEL_PCIE_REFCLK', 'REF_ALWAYS', 'REF_EQUAL', 'REF_GEQUAL', 'REF_GREATER', 'REF_LEQUAL', 'REF_LESS', 'REF_NEVER', 'REF_NOTEQUAL', 'RESERVED_ES', 'RESERVED_LS', 'RESERVED_VS', 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', 'RE_Z', 'RINGID0', 'RINGID1', 'RINGID2', 'RINGID3', 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL', 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL', 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', 'RMIPerfSel', 'RMI_CID', 'RMI_CID_CC', 'RMI_CID_CM', 'RMI_CID_DC', 'RMI_CID_FC', 'RMI_CID_S', 'RMI_CID_TILE', 'RMI_CID_Z', 'RMI_CID_ZPCPSD', 'RMI_PERF_SEL_BUSY', 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0', 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1', 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2', 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3', 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', 'RMI_PERF_SEL_DYN_CLK_RB_VLD', 'RMI_PERF_SEL_EVENT_SEND', 'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ', 'RMI_PERF_SEL_LAT_FIFO_FULL', 'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ', 'RMI_PERF_SEL_LAT_FIFO_NUM_USED', 'RMI_PERF_SEL_NONE', 'RMI_PERF_SEL_PERF_WINDOW', 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR', 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB', 'RMI_PERF_SEL_POP_DEMUX_RTS_RTR', 'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB', 'RMI_PERF_SEL_POP_XNACK_RTSB_RTR', 'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB', 'RMI_PERF_SEL_POP_XNACK_RTS_RTR', 'RMI_PERF_SEL_POP_XNACK_RTS_RTRB', 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR', 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB', 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR', 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB', 'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT', 'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT', 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT', 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY', 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR', 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB', 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR', 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB', 'RMI_PERF_SEL_PRT_FIFO_BUSY', 'RMI_PERF_SEL_PRT_FIFO_NUM_USED', 'RMI_PERF_SEL_PRT_FIFO_REQ', 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', 'RMI_PERF_SEL_RB_RMI_RDREQ_BUSY', 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', 'RMI_PERF_SEL_RB_RMI_WRREQ_BUSY', 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', 'RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID', 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR', 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB', 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR', 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB', 'RMI_PERF_SEL_REG_CLK_VLD', 'RMI_PERF_SEL_REORDER_FIFO_BUSY', 'RMI_PERF_SEL_REORDER_FIFO_REQ', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9', 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9', 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL', 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0', 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1', 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2', 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3', 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', 'RMI_PERF_SEL_RMI_UTC_BUSY', 'RMI_PERF_SEL_RMI_UTC_REQ', 'RMI_PERF_SEL_SKID_FIFO_BUSY', 'RMI_PERF_SEL_SKID_FIFO_DEPTH', 'RMI_PERF_SEL_SKID_FIFO_IN_RTS', 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB', 'RMI_PERF_SEL_SKID_FIFO_OUT_RTS', 'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB', 'RMI_PERF_SEL_SKID_FIFO_REQ', 'RMI_PERF_SEL_TCIW_BUSY', 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', 'RMI_PERF_SEL_TCIW_REQ', 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', 'RMI_PERF_SEL_UTCL1_BUSY', 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL', 'RMI_PERF_SEL_UTCL1_LFIFO_FULL', 'RMI_PERF_SEL_UTCL1_PERMISSION_MISS', 'RMI_PERF_SEL_UTCL1_REQUEST', 'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', 'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', 'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', 'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', 'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS', 'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', 'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS', 'RMI_PERF_SEL_UTCL1_UTCL2_REQ', 'RMI_PERF_SEL_UTC_POP_RTSB_RTR', 'RMI_PERF_SEL_UTC_POP_RTSB_RTRB', 'RMI_PERF_SEL_UTC_POP_RTS_RTR', 'RMI_PERF_SEL_UTC_POP_RTS_RTRB', 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR', 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB', 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR', 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB', 'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR', 'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR', 'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR', 'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR', 'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR', 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR', 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB', 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR', 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB', 'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR', 'RMI_PERF_SEL_XNACK_FIFO_BUSY', 'RMI_PERF_SEL_XNACK_FIFO_FULL', 'RMI_PERF_SEL_XNACK_FIFO_NUM_USED', 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR', 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB', 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR', 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB', 'ROM_SIGNATURE', 'ROUND_BY_HALF', 'ROUND_TRUNCATE', 'RST_PIX_CNT', 'RSV_TAG_RAM', 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', 'ReadSize', 'Reserved142', 'Reserved143', 'Reserved144', 'Reserved145', 'Reserved146', 'Reserved147', 'Reserved148', 'Reserved149', 'Reserved18', 'Reserved182', 'Reserved183', 'Reserved184', 'Reserved185', 'Reserved186', 'Reserved187', 'Reserved188', 'Reserved189', 'Reserved190', 'Reserved191', 'Reserved192', 'Reserved193', 'Reserved194', 'Reserved195', 'Reserved196', 'Reserved197', 'Reserved198', 'Reserved199', 'Reserved200', 'Reserved201', 'Reserved202', 'Reserved203', 'Reserved204', 'Reserved205', 'Reserved206', 'Reserved207', 'Reserved208', 'Reserved209', 'Reserved210', 'Reserved211', 'Reserved212', 'Reserved213', 'Reserved214', 'Reserved215', 'Reserved216', 'Reserved217', 'Reserved218', 'Reserved219', 'Reserved23', 'Reserved252', 'Reserved253', 'Reserved254', 'Reserved255', 'Reserved256', 'Reserved257', 'Reserved258', 'Reserved259', 'Reserved26', 'Reserved260', 'Reserved261', 'Reserved262', 'Reserved263', 'Reserved264', 'Reserved265', 'Reserved266', 'Reserved267', 'Reserved27', 'Reserved28', 'Reserved29', 'Reserved300', 'Reserved301', 'Reserved302', 'Reserved303', 'Reserved304', 'Reserved305', 'Reserved306', 'Reserved307', 'Reserved308', 'Reserved309', 'Reserved310', 'Reserved311', 'Reserved312', 'Reserved313', 'Reserved314', 'Reserved315', 'Reserved316', 'Reserved317', 'Reserved318', 'Reserved319', 'Reserved320', 'Reserved321', 'Reserved322', 'Reserved323', 'Reserved324', 'Reserved325', 'Reserved326', 'Reserved327', 'Reserved328', 'Reserved329', 'Reserved330', 'Reserved331', 'Reserved364', 'Reserved365', 'Reserved366', 'Reserved367', 'Reserved368', 'Reserved369', 'Reserved370', 'Reserved371', 'Reserved372', 'Reserved373', 'Reserved374', 'Reserved375', 'Reserved376', 'Reserved377', 'Reserved378', 'Reserved379', 'Reserved412', 'Reserved413', 'Reserved414', 'Reserved415', 'Reserved416', 'Reserved417', 'Reserved418', 'Reserved419', 'Reserved420', 'Reserved421', 'Reserved422', 'Reserved423', 'Reserved424', 'Reserved425', 'Reserved426', 'Reserved427', 'Reserved428', 'Reserved429', 'Reserved430', 'Reserved431', 'Reserved432', 'Reserved433', 'Reserved434', 'Reserved435', 'Reserved436', 'Reserved437', 'Reserved438', 'Reserved439', 'Reserved440', 'Reserved441', 'Reserved442', 'Reserved443', 'Reserved444', 'Reserved445', 'Reserved446', 'Reserved447', 'Reserved448', 'Reserved449', 'Reserved450', 'Reserved451', 'Reserved452', 'Reserved453', 'Reserved454', 'Reserved455', 'Reserved456', 'Reserved457', 'Reserved458', 'Reserved459', 'Reserved460', 'Reserved461', 'Reserved462', 'Reserved463', 'Reserved464', 'Reserved465', 'Reserved466', 'Reserved467', 'Reserved468', 'Reserved469', 'Reserved470', 'Reserved471', 'Reserved472', 'Reserved473', 'Reserved474', 'Reserved475', 'Reserved476', 'Reserved477', 'Reserved478', 'Reserved479', 'Reserved480', 'Reserved481', 'Reserved482', 'Reserved483', 'Reserved484', 'Reserved485', 'Reserved486', 'Reserved487', 'Reserved488', 'Reserved489', 'Reserved490', 'Reserved491', 'Reserved492', 'Reserved493', 'Reserved494', 'Reserved495', 'Reserved496', 'Reserved497', 'Reserved498', 'Reserved499', 'Reserved500', 'Reserved501', 'Reserved502', 'Reserved503', 'Reserved504', 'Reserved505', 'Reserved506', 'Reserved507', 'Reserved508', 'Reserved509', 'Reserved510', 'Reserved511', 'Reserved_0x00', 'Reserved_0x09', 'Reserved_0x3f', 'RingCounterControl', 'RoundMode', 'RowSize', 'RowTiling', 'SAMPLE_PIPELINESTAT', 'SAMPLE_STREAMOUTSTATS', 'SAMPLE_STREAMOUTSTATS1', 'SAMPLE_STREAMOUTSTATS2', 'SAMPLE_STREAMOUTSTATS3', 'SCLV_COEF_UPDATE_COMPLETE', 'SCLV_INTERLACE_SOURCE', 'SCLV_MODE_RGB_BYPASS', 'SCLV_MODE_RGB_SCALING', 'SCLV_MODE_SEL', 'SCLV_MODE_YCBCR_BYPASS', 'SCLV_MODE_YCBCR_SCALING', 'SCLV_UPDATE_LOCK', 'SCL_ALU_DISABLE', 'SCL_ALU_DISABLED', 'SCL_ALU_ENABLED', 'SCL_BOUNDARY_MODE', 'SCL_BOUNDARY_MODE_BLACK', 'SCL_BOUNDARY_MODE_EDGE', 'SCL_BYPASS_MODE', 'SCL_BYPASS_MODE_AC_AR', 'SCL_BYPASS_MODE_AC_NR', 'SCL_BYPASS_MODE_MC_MR', 'SCL_BYPASS_MODE_RESERVED', 'SCL_COEF_UPDATE_COMPLETE', 'SCL_COEF_UPDATE_COMPLETED', 'SCL_COEF_UPDATE_NOT_COMPLETED', 'SCL_C_RAM_FILTER_TYPE', 'SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT', 'SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT', 'SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT', 'SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT', 'SCL_C_RAM_PHASE', 'SCL_C_RAM_PHASE_0', 'SCL_C_RAM_PHASE_1', 'SCL_C_RAM_PHASE_2', 'SCL_C_RAM_PHASE_3', 'SCL_C_RAM_PHASE_4', 'SCL_C_RAM_PHASE_5', 'SCL_C_RAM_PHASE_6', 'SCL_C_RAM_PHASE_7', 'SCL_C_RAM_PHASE_8', 'SCL_C_RAM_TAP_PAIR_ID0', 'SCL_C_RAM_TAP_PAIR_ID1', 'SCL_C_RAM_TAP_PAIR_ID2', 'SCL_C_RAM_TAP_PAIR_ID3', 'SCL_C_RAM_TAP_PAIR_ID4', 'SCL_C_RAM_TAP_PAIR_IDX', 'SCL_EARLY_EOL_MOD', 'SCL_EARLY_EOL_MODE_CRTC', 'SCL_EARLY_EOL_MODE_INTERNAL', 'SCL_HF_SHARP_DISABLE', 'SCL_HF_SHARP_EN', 'SCL_HF_SHARP_ENABLE', 'SCL_HF_SHARP_SCALE_FACTOR', 'SCL_HF_SHARP_SCALE_FACTOR_0', 'SCL_HF_SHARP_SCALE_FACTOR_1', 'SCL_HF_SHARP_SCALE_FACTOR_2', 'SCL_HF_SHARP_SCALE_FACTOR_3', 'SCL_HF_SHARP_SCALE_FACTOR_4', 'SCL_HF_SHARP_SCALE_FACTOR_5', 'SCL_HF_SHARP_SCALE_FACTOR_6', 'SCL_HF_SHARP_SCALE_FACTOR_7', 'SCL_HOST_CONFLICT_DISABLE_INTERRUPT', 'SCL_HOST_CONFLICT_ENABLE_INTERRUPT', 'SCL_HOST_CONFLICT_MASK', 'SCL_H_2TAP_HARDCODE_COEF_DISABLE', 'SCL_H_2TAP_HARDCODE_COEF_EN', 'SCL_H_2TAP_HARDCODE_COEF_ENABLE', 'SCL_H_CALC_AUTO_RATIO_DISABLE', 'SCL_H_CALC_AUTO_RATIO_EN', 'SCL_H_CALC_AUTO_RATIO_ENABLE', 'SCL_H_FILTER_PICK_NEAREST', 'SCL_H_FILTER_PICK_NEAREST_DISABLE', 'SCL_H_FILTER_PICK_NEAREST_ENABLE', 'SCL_H_MANUAL_REPLICATE_FACTOR', 'SCL_H_MANUAL_REPLICATE_FACTOR_1', 'SCL_H_MANUAL_REPLICATE_FACTOR_10', 'SCL_H_MANUAL_REPLICATE_FACTOR_11', 'SCL_H_MANUAL_REPLICATE_FACTOR_12', 'SCL_H_MANUAL_REPLICATE_FACTOR_13', 'SCL_H_MANUAL_REPLICATE_FACTOR_14', 'SCL_H_MANUAL_REPLICATE_FACTOR_15', 'SCL_H_MANUAL_REPLICATE_FACTOR_16', 'SCL_H_MANUAL_REPLICATE_FACTOR_2', 'SCL_H_MANUAL_REPLICATE_FACTOR_3', 'SCL_H_MANUAL_REPLICATE_FACTOR_4', 'SCL_H_MANUAL_REPLICATE_FACTOR_5', 'SCL_H_MANUAL_REPLICATE_FACTOR_6', 'SCL_H_MANUAL_REPLICATE_FACTOR_7', 'SCL_H_MANUAL_REPLICATE_FACTOR_8', 'SCL_H_MANUAL_REPLICATE_FACTOR_9', 'SCL_H_NUM_OF_TAPS', 'SCL_H_NUM_OF_TAPS_1', 'SCL_H_NUM_OF_TAPS_10', 'SCL_H_NUM_OF_TAPS_2', 'SCL_H_NUM_OF_TAPS_4', 'SCL_H_NUM_OF_TAPS_6', 'SCL_H_NUM_OF_TAPS_8', 'SCL_MODE_CHANGE_DISABLE_INTERRUPT', 'SCL_MODE_CHANGE_ENABLE_INTERRUPT', 'SCL_MODE_RGB_BYPASS', 'SCL_MODE_RGB_SCALING', 'SCL_MODE_SEL', 'SCL_MODE_YCBCR_BYPASS', 'SCL_MODE_YCBCR_SCALING', 'SCL_PSCL_DISABLE', 'SCL_PSCL_EN', 'SCL_PSCL_ENANBLE', 'SCL_SCL_MODE_CHANGE_MASK', 'SCL_UPDATE_LOCK', 'SCL_UPDATE_LOCKED', 'SCL_UPDATE_TAKEN', 'SCL_UPDATE_TAKEN_NO', 'SCL_UPDATE_TAKEN_YES', 'SCL_UPDATE_UNLOCKED', 'SCL_VF_SHARP_DISABLE', 'SCL_VF_SHARP_EN', 'SCL_VF_SHARP_ENABLE', 'SCL_VF_SHARP_SCALE_FACTOR', 'SCL_VF_SHARP_SCALE_FACTOR_0', 'SCL_VF_SHARP_SCALE_FACTOR_1', 'SCL_VF_SHARP_SCALE_FACTOR_2', 'SCL_VF_SHARP_SCALE_FACTOR_3', 'SCL_VF_SHARP_SCALE_FACTOR_4', 'SCL_VF_SHARP_SCALE_FACTOR_5', 'SCL_VF_SHARP_SCALE_FACTOR_6', 'SCL_VF_SHARP_SCALE_FACTOR_7', 'SCL_V_2TAP_HARDCODE_COEF_DISABLE', 'SCL_V_2TAP_HARDCODE_COEF_EN', 'SCL_V_2TAP_HARDCODE_COEF_ENABLE', 'SCL_V_CALC_AUTO_RATIO_DISABLE', 'SCL_V_CALC_AUTO_RATIO_EN', 'SCL_V_CALC_AUTO_RATIO_ENABLE', 'SCL_V_FILTER_PICK_NEAREST', 'SCL_V_FILTER_PICK_NEAREST_DISABLE', 'SCL_V_FILTER_PICK_NEAREST_ENABLE', 'SCL_V_MANUAL_REPLICATE_FACTOR', 'SCL_V_MANUAL_REPLICATE_FACTOR_1', 'SCL_V_MANUAL_REPLICATE_FACTOR_10', 'SCL_V_MANUAL_REPLICATE_FACTOR_11', 'SCL_V_MANUAL_REPLICATE_FACTOR_12', 'SCL_V_MANUAL_REPLICATE_FACTOR_13', 'SCL_V_MANUAL_REPLICATE_FACTOR_14', 'SCL_V_MANUAL_REPLICATE_FACTOR_15', 'SCL_V_MANUAL_REPLICATE_FACTOR_16', 'SCL_V_MANUAL_REPLICATE_FACTOR_2', 'SCL_V_MANUAL_REPLICATE_FACTOR_3', 'SCL_V_MANUAL_REPLICATE_FACTOR_4', 'SCL_V_MANUAL_REPLICATE_FACTOR_5', 'SCL_V_MANUAL_REPLICATE_FACTOR_6', 'SCL_V_MANUAL_REPLICATE_FACTOR_7', 'SCL_V_MANUAL_REPLICATE_FACTOR_8', 'SCL_V_MANUAL_REPLICATE_FACTOR_9', 'SCL_V_NUM_OF_TAPS', 'SCL_V_NUM_OF_TAPS_1', 'SCL_V_NUM_OF_TAPS_2', 'SCL_V_NUM_OF_TAPS_3', 'SCL_V_NUM_OF_TAPS_4', 'SCL_V_NUM_OF_TAPS_5', 'SCL_V_NUM_OF_TAPS_6', 'SC_BACKEND_BUSY', 'SC_BB_DISCARD', 'SC_BM_BUSY', 'SC_BUSY_CNT_NOT_ZERO', 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', 'SC_EARLYZ_QUAD_COUNT', 'SC_EARLYZ_QUAD_WITH_1_PIX', 'SC_EARLYZ_QUAD_WITH_2_PIX', 'SC_EARLYZ_QUAD_WITH_3_PIX', 'SC_EARLYZ_QUAD_WITH_4_PIX', 'SC_EOP_SYNC_WINDOW', 'SC_GRP0_DYN_SCLK_BUSY', 'SC_GRP1_DYN_SCLK_BUSY', 'SC_GRP2_DYN_SCLK_BUSY', 'SC_GRP3_DYN_SCLK_BUSY', 'SC_GRP4_DYN_SCLK_BUSY', 'SC_MULTICYCLE_BUBBLE_FREEZE', 'SC_P0_DETAIL_QUAD_COUNT', 'SC_P0_DETAIL_QUAD_WITH_1_PIX', 'SC_P0_DETAIL_QUAD_WITH_2_PIX', 'SC_P0_DETAIL_QUAD_WITH_3_PIX', 'SC_P0_DETAIL_QUAD_WITH_4_PIX', 'SC_P0_HIZ_QUAD_COUNT', 'SC_P0_HIZ_QUAD_PER_TILE_H0', 'SC_P0_HIZ_QUAD_PER_TILE_H1', 'SC_P0_HIZ_QUAD_PER_TILE_H10', 'SC_P0_HIZ_QUAD_PER_TILE_H11', 'SC_P0_HIZ_QUAD_PER_TILE_H12', 'SC_P0_HIZ_QUAD_PER_TILE_H13', 'SC_P0_HIZ_QUAD_PER_TILE_H14', 'SC_P0_HIZ_QUAD_PER_TILE_H15', 'SC_P0_HIZ_QUAD_PER_TILE_H16', 'SC_P0_HIZ_QUAD_PER_TILE_H2', 'SC_P0_HIZ_QUAD_PER_TILE_H3', 'SC_P0_HIZ_QUAD_PER_TILE_H4', 'SC_P0_HIZ_QUAD_PER_TILE_H5', 'SC_P0_HIZ_QUAD_PER_TILE_H6', 'SC_P0_HIZ_QUAD_PER_TILE_H7', 'SC_P0_HIZ_QUAD_PER_TILE_H8', 'SC_P0_HIZ_QUAD_PER_TILE_H9', 'SC_P0_HIZ_TILE_COUNT', 'SC_P1_DETAIL_QUAD_COUNT', 'SC_P1_DETAIL_QUAD_WITH_1_PIX', 'SC_P1_DETAIL_QUAD_WITH_2_PIX', 'SC_P1_DETAIL_QUAD_WITH_3_PIX', 'SC_P1_DETAIL_QUAD_WITH_4_PIX', 'SC_P1_HIZ_QUAD_COUNT', 'SC_P1_HIZ_QUAD_PER_TILE_H0', 'SC_P1_HIZ_QUAD_PER_TILE_H1', 'SC_P1_HIZ_QUAD_PER_TILE_H10', 'SC_P1_HIZ_QUAD_PER_TILE_H11', 'SC_P1_HIZ_QUAD_PER_TILE_H12', 'SC_P1_HIZ_QUAD_PER_TILE_H13', 'SC_P1_HIZ_QUAD_PER_TILE_H14', 'SC_P1_HIZ_QUAD_PER_TILE_H15', 'SC_P1_HIZ_QUAD_PER_TILE_H16', 'SC_P1_HIZ_QUAD_PER_TILE_H2', 'SC_P1_HIZ_QUAD_PER_TILE_H3', 'SC_P1_HIZ_QUAD_PER_TILE_H4', 'SC_P1_HIZ_QUAD_PER_TILE_H5', 'SC_P1_HIZ_QUAD_PER_TILE_H6', 'SC_P1_HIZ_QUAD_PER_TILE_H7', 'SC_P1_HIZ_QUAD_PER_TILE_H8', 'SC_P1_HIZ_QUAD_PER_TILE_H9', 'SC_P1_HIZ_TILE_COUNT', 'SC_P2_DETAIL_QUAD_COUNT', 'SC_P2_DETAIL_QUAD_WITH_1_PIX', 'SC_P2_DETAIL_QUAD_WITH_2_PIX', 'SC_P2_DETAIL_QUAD_WITH_3_PIX', 'SC_P2_DETAIL_QUAD_WITH_4_PIX', 'SC_P2_HIZ_QUAD_COUNT', 'SC_P2_HIZ_QUAD_PER_TILE_H0', 'SC_P2_HIZ_QUAD_PER_TILE_H1', 'SC_P2_HIZ_QUAD_PER_TILE_H10', 'SC_P2_HIZ_QUAD_PER_TILE_H11', 'SC_P2_HIZ_QUAD_PER_TILE_H12', 'SC_P2_HIZ_QUAD_PER_TILE_H13', 'SC_P2_HIZ_QUAD_PER_TILE_H14', 'SC_P2_HIZ_QUAD_PER_TILE_H15', 'SC_P2_HIZ_QUAD_PER_TILE_H16', 'SC_P2_HIZ_QUAD_PER_TILE_H2', 'SC_P2_HIZ_QUAD_PER_TILE_H3', 'SC_P2_HIZ_QUAD_PER_TILE_H4', 'SC_P2_HIZ_QUAD_PER_TILE_H5', 'SC_P2_HIZ_QUAD_PER_TILE_H6', 'SC_P2_HIZ_QUAD_PER_TILE_H7', 'SC_P2_HIZ_QUAD_PER_TILE_H8', 'SC_P2_HIZ_QUAD_PER_TILE_H9', 'SC_P2_HIZ_TILE_COUNT', 'SC_P3_DETAIL_QUAD_COUNT', 'SC_P3_DETAIL_QUAD_WITH_1_PIX', 'SC_P3_DETAIL_QUAD_WITH_2_PIX', 'SC_P3_DETAIL_QUAD_WITH_3_PIX', 'SC_P3_DETAIL_QUAD_WITH_4_PIX', 'SC_P3_HIZ_QUAD_COUNT', 'SC_P3_HIZ_QUAD_PER_TILE_H0', 'SC_P3_HIZ_QUAD_PER_TILE_H1', 'SC_P3_HIZ_QUAD_PER_TILE_H10', 'SC_P3_HIZ_QUAD_PER_TILE_H11', 'SC_P3_HIZ_QUAD_PER_TILE_H12', 'SC_P3_HIZ_QUAD_PER_TILE_H13', 'SC_P3_HIZ_QUAD_PER_TILE_H14', 'SC_P3_HIZ_QUAD_PER_TILE_H15', 'SC_P3_HIZ_QUAD_PER_TILE_H16', 'SC_P3_HIZ_QUAD_PER_TILE_H2', 'SC_P3_HIZ_QUAD_PER_TILE_H3', 'SC_P3_HIZ_QUAD_PER_TILE_H4', 'SC_P3_HIZ_QUAD_PER_TILE_H5', 'SC_P3_HIZ_QUAD_PER_TILE_H6', 'SC_P3_HIZ_QUAD_PER_TILE_H7', 'SC_P3_HIZ_QUAD_PER_TILE_H8', 'SC_P3_HIZ_QUAD_PER_TILE_H9', 'SC_P3_HIZ_TILE_COUNT', 'SC_PA0_PS_DATA_SEND', 'SC_PA0_SC_DATA_FIFO_EOPG_RD', 'SC_PA0_SC_DATA_FIFO_EOP_RD', 'SC_PA0_SC_DATA_FIFO_RD', 'SC_PA0_SC_DATA_FIFO_WE', 'SC_PA0_SC_DEALLOC_0_RD', 'SC_PA0_SC_DEALLOC_1_RD', 'SC_PA0_SC_EOPG_WE', 'SC_PA0_SC_EOP_WE', 'SC_PA0_SC_EVENT_WE', 'SC_PA0_SC_FPOV_WE', 'SC_PA0_SC_LPOV_WE', 'SC_PA0_SC_NULL_DEALLOC_WE', 'SC_PA0_SC_NULL_WE', 'SC_PA1_PS_DATA_SEND', 'SC_PA1_SC_DATA_FIFO_EOPG_RD', 'SC_PA1_SC_DATA_FIFO_EOP_RD', 'SC_PA1_SC_DATA_FIFO_RD', 'SC_PA1_SC_DATA_FIFO_WE', 'SC_PA1_SC_DEALLOC_0_RD', 'SC_PA1_SC_DEALLOC_1_RD', 'SC_PA1_SC_EOPG_WE', 'SC_PA1_SC_EOP_WE', 'SC_PA1_SC_EVENT_WE', 'SC_PA1_SC_FPOV_WE', 'SC_PA1_SC_LPOV_WE', 'SC_PA1_SC_NULL_DEALLOC_WE', 'SC_PA1_SC_NULL_WE', 'SC_PA2_PS_DATA_SEND', 'SC_PA2_SC_DATA_FIFO_EOPG_RD', 'SC_PA2_SC_DATA_FIFO_EOP_RD', 'SC_PA2_SC_DATA_FIFO_RD', 'SC_PA2_SC_DATA_FIFO_WE', 'SC_PA2_SC_DEALLOC_0_RD', 'SC_PA2_SC_DEALLOC_1_RD', 'SC_PA2_SC_EOPG_WE', 'SC_PA2_SC_EOP_WE', 'SC_PA2_SC_EVENT_WE', 'SC_PA2_SC_FPOV_WE', 'SC_PA2_SC_LPOV_WE', 'SC_PA2_SC_NULL_DEALLOC_WE', 'SC_PA2_SC_NULL_WE', 'SC_PA3_PS_DATA_SEND', 'SC_PA3_SC_DATA_FIFO_EOPG_RD', 'SC_PA3_SC_DATA_FIFO_EOP_RD', 'SC_PA3_SC_DATA_FIFO_RD', 'SC_PA3_SC_DATA_FIFO_WE', 'SC_PA3_SC_DEALLOC_0_RD', 'SC_PA3_SC_DEALLOC_1_RD', 'SC_PA3_SC_EOPG_WE', 'SC_PA3_SC_EOP_WE', 'SC_PA3_SC_EVENT_WE', 'SC_PA3_SC_FPOV_WE', 'SC_PA3_SC_LPOV_WE', 'SC_PA3_SC_NULL_DEALLOC_WE', 'SC_PA3_SC_NULL_WE', 'SC_PA_SC_DEALLOC_0_0_WE', 'SC_PA_SC_DEALLOC_0_1_WE', 'SC_PA_SC_DEALLOC_1_0_WE', 'SC_PA_SC_DEALLOC_1_1_WE', 'SC_PA_SC_DEALLOC_2_0_WE', 'SC_PA_SC_DEALLOC_2_1_WE', 'SC_PA_SC_DEALLOC_3_0_WE', 'SC_PA_SC_DEALLOC_3_1_WE', 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', 'SC_PBB_BATCH_HIST_NUM_PRIMS', 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', 'SC_PBB_BIN_HIST_NUM_CONTEXTS', 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', 'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY', 'SC_PBB_BUSY_AND_RTR', 'SC_PBB_END_OF_BATCH', 'SC_PBB_END_OF_BIN', 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', 'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS', 'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH', 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL', 'SC_PKR_4X2_FILL_QUAD', 'SC_PKR_4X2_QUAD_SPLIT', 'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV', 'SC_PKR_END_OF_VECTOR', 'SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE', 'SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE', 'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', 'SC_POPS_FORCE_EOV', 'SC_POPS_INTRA_WAVE_OVERLAPS', 'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY', 'SC_PS_ARB_EOP_POP_SYNC_POP', 'SC_PS_ARB_EVENT_SYNC_POP', 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', 'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY', 'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE', 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP', 'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_PA0_SC_FIFO_EMPTY', 'SC_PS_PA0_SC_FIFO_FULL', 'SC_PS_PA1_SC_FIFO_EMPTY', 'SC_PS_PA1_SC_FIFO_FULL', 'SC_PS_PA2_SC_FIFO_EMPTY', 'SC_PS_PA2_SC_FIFO_FULL', 'SC_PS_PA3_SC_FIFO_EMPTY', 'SC_PS_PA3_SC_FIFO_FULL', 'SC_PS_TS_EVENT_FIFO_POP', 'SC_PS_TS_EVENT_FIFO_PUSH', 'SC_QZ0_MULTI_GPU_TILE_DISCARD', 'SC_QZ0_QUAD_COUNT', 'SC_QZ0_QUAD_PER_TILE_H0', 'SC_QZ0_QUAD_PER_TILE_H1', 'SC_QZ0_QUAD_PER_TILE_H10', 'SC_QZ0_QUAD_PER_TILE_H11', 'SC_QZ0_QUAD_PER_TILE_H12', 'SC_QZ0_QUAD_PER_TILE_H13', 'SC_QZ0_QUAD_PER_TILE_H14', 'SC_QZ0_QUAD_PER_TILE_H15', 'SC_QZ0_QUAD_PER_TILE_H16', 'SC_QZ0_QUAD_PER_TILE_H2', 'SC_QZ0_QUAD_PER_TILE_H3', 'SC_QZ0_QUAD_PER_TILE_H4', 'SC_QZ0_QUAD_PER_TILE_H5', 'SC_QZ0_QUAD_PER_TILE_H6', 'SC_QZ0_QUAD_PER_TILE_H7', 'SC_QZ0_QUAD_PER_TILE_H8', 'SC_QZ0_QUAD_PER_TILE_H9', 'SC_QZ0_TILE_COUNT', 'SC_QZ0_TILE_COVERED_COUNT', 'SC_QZ0_TILE_NOT_COVERED_COUNT', 'SC_QZ1_MULTI_GPU_TILE_DISCARD', 'SC_QZ1_QUAD_COUNT', 'SC_QZ1_QUAD_PER_TILE_H0', 'SC_QZ1_QUAD_PER_TILE_H1', 'SC_QZ1_QUAD_PER_TILE_H10', 'SC_QZ1_QUAD_PER_TILE_H11', 'SC_QZ1_QUAD_PER_TILE_H12', 'SC_QZ1_QUAD_PER_TILE_H13', 'SC_QZ1_QUAD_PER_TILE_H14', 'SC_QZ1_QUAD_PER_TILE_H15', 'SC_QZ1_QUAD_PER_TILE_H16', 'SC_QZ1_QUAD_PER_TILE_H2', 'SC_QZ1_QUAD_PER_TILE_H3', 'SC_QZ1_QUAD_PER_TILE_H4', 'SC_QZ1_QUAD_PER_TILE_H5', 'SC_QZ1_QUAD_PER_TILE_H6', 'SC_QZ1_QUAD_PER_TILE_H7', 'SC_QZ1_QUAD_PER_TILE_H8', 'SC_QZ1_QUAD_PER_TILE_H9', 'SC_QZ1_TILE_COUNT', 'SC_QZ1_TILE_COVERED_COUNT', 'SC_QZ1_TILE_NOT_COVERED_COUNT', 'SC_QZ2_MULTI_GPU_TILE_DISCARD', 'SC_QZ2_QUAD_COUNT', 'SC_QZ2_QUAD_PER_TILE_H0', 'SC_QZ2_QUAD_PER_TILE_H1', 'SC_QZ2_QUAD_PER_TILE_H10', 'SC_QZ2_QUAD_PER_TILE_H11', 'SC_QZ2_QUAD_PER_TILE_H12', 'SC_QZ2_QUAD_PER_TILE_H13', 'SC_QZ2_QUAD_PER_TILE_H14', 'SC_QZ2_QUAD_PER_TILE_H15', 'SC_QZ2_QUAD_PER_TILE_H16', 'SC_QZ2_QUAD_PER_TILE_H2', 'SC_QZ2_QUAD_PER_TILE_H3', 'SC_QZ2_QUAD_PER_TILE_H4', 'SC_QZ2_QUAD_PER_TILE_H5', 'SC_QZ2_QUAD_PER_TILE_H6', 'SC_QZ2_QUAD_PER_TILE_H7', 'SC_QZ2_QUAD_PER_TILE_H8', 'SC_QZ2_QUAD_PER_TILE_H9', 'SC_QZ2_TILE_COUNT', 'SC_QZ2_TILE_COVERED_COUNT', 'SC_QZ2_TILE_NOT_COVERED_COUNT', 'SC_QZ3_MULTI_GPU_TILE_DISCARD', 'SC_QZ3_QUAD_COUNT', 'SC_QZ3_QUAD_PER_TILE_H0', 'SC_QZ3_QUAD_PER_TILE_H1', 'SC_QZ3_QUAD_PER_TILE_H10', 'SC_QZ3_QUAD_PER_TILE_H11', 'SC_QZ3_QUAD_PER_TILE_H12', 'SC_QZ3_QUAD_PER_TILE_H13', 'SC_QZ3_QUAD_PER_TILE_H14', 'SC_QZ3_QUAD_PER_TILE_H15', 'SC_QZ3_QUAD_PER_TILE_H16', 'SC_QZ3_QUAD_PER_TILE_H2', 'SC_QZ3_QUAD_PER_TILE_H3', 'SC_QZ3_QUAD_PER_TILE_H4', 'SC_QZ3_QUAD_PER_TILE_H5', 'SC_QZ3_QUAD_PER_TILE_H6', 'SC_QZ3_QUAD_PER_TILE_H7', 'SC_QZ3_QUAD_PER_TILE_H8', 'SC_QZ3_QUAD_PER_TILE_H9', 'SC_QZ3_TILE_COUNT', 'SC_QZ3_TILE_COVERED_COUNT', 'SC_QZ3_TILE_NOT_COVERED_COUNT', 'SC_QZQP_WINDOW_VALID', 'SC_QZQP_WINDOW_VALID_BUSY', 'SC_REG_SCLK_BUSY', 'SC_SCB_BUSY', 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD', 'SC_SC_PS_ENG_MULTICYCLE_BUBBLE', 'SC_SC_SPI_DEALLOC_0_0', 'SC_SC_SPI_DEALLOC_0_1', 'SC_SC_SPI_DEALLOC_0_2', 'SC_SC_SPI_DEALLOC_1_0', 'SC_SC_SPI_DEALLOC_1_1', 'SC_SC_SPI_DEALLOC_1_2', 'SC_SC_SPI_DEALLOC_2_0', 'SC_SC_SPI_DEALLOC_2_1', 'SC_SC_SPI_DEALLOC_2_2', 'SC_SC_SPI_DEALLOC_3_0', 'SC_SC_SPI_DEALLOC_3_1', 'SC_SC_SPI_DEALLOC_3_2', 'SC_SC_SPI_EVENT', 'SC_SC_SPI_FPOV_0', 'SC_SC_SPI_FPOV_1', 'SC_SC_SPI_FPOV_2', 'SC_SC_SPI_FPOV_3', 'SC_SEND_DB_VPZ', 'SC_SRPS_WINDOW_VALID', 'SC_SRPS_WINDOW_VALID_BUSY', 'SC_STALLED_BY_BCI', 'SC_STALLED_BY_DB_QUAD', 'SC_STALLED_BY_DB_TILE', 'SC_STALLED_BY_PRIMFIFO', 'SC_STALLED_BY_QUADFIFO', 'SC_STALLED_BY_SPI', 'SC_STALLED_BY_TILEFIFO', 'SC_STALLED_BY_TILEORDERFIFO', 'SC_STARVED_BY_DB_QUAD', 'SC_STARVED_BY_DB_TILE', 'SC_STARVED_BY_PA', 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', 'SC_SUPERTILE_COUNT', 'SC_SUPERTILE_PER_PRIM_H0', 'SC_SUPERTILE_PER_PRIM_H1', 'SC_SUPERTILE_PER_PRIM_H10', 'SC_SUPERTILE_PER_PRIM_H11', 'SC_SUPERTILE_PER_PRIM_H12', 'SC_SUPERTILE_PER_PRIM_H13', 'SC_SUPERTILE_PER_PRIM_H14', 'SC_SUPERTILE_PER_PRIM_H15', 'SC_SUPERTILE_PER_PRIM_H16', 'SC_SUPERTILE_PER_PRIM_H2', 'SC_SUPERTILE_PER_PRIM_H3', 'SC_SUPERTILE_PER_PRIM_H4', 'SC_SUPERTILE_PER_PRIM_H5', 'SC_SUPERTILE_PER_PRIM_H6', 'SC_SUPERTILE_PER_PRIM_H7', 'SC_SUPERTILE_PER_PRIM_H8', 'SC_SUPERTILE_PER_PRIM_H9', 'SC_TILE_PER_PRIM_H0', 'SC_TILE_PER_PRIM_H1', 'SC_TILE_PER_PRIM_H10', 'SC_TILE_PER_PRIM_H11', 'SC_TILE_PER_PRIM_H12', 'SC_TILE_PER_PRIM_H13', 'SC_TILE_PER_PRIM_H14', 'SC_TILE_PER_PRIM_H15', 'SC_TILE_PER_PRIM_H16', 'SC_TILE_PER_PRIM_H2', 'SC_TILE_PER_PRIM_H3', 'SC_TILE_PER_PRIM_H4', 'SC_TILE_PER_PRIM_H5', 'SC_TILE_PER_PRIM_H6', 'SC_TILE_PER_PRIM_H7', 'SC_TILE_PER_PRIM_H8', 'SC_TILE_PER_PRIM_H9', 'SC_TILE_PER_SUPERTILE_H0', 'SC_TILE_PER_SUPERTILE_H1', 'SC_TILE_PER_SUPERTILE_H10', 'SC_TILE_PER_SUPERTILE_H11', 'SC_TILE_PER_SUPERTILE_H12', 'SC_TILE_PER_SUPERTILE_H13', 'SC_TILE_PER_SUPERTILE_H14', 'SC_TILE_PER_SUPERTILE_H15', 'SC_TILE_PER_SUPERTILE_H16', 'SC_TILE_PER_SUPERTILE_H2', 'SC_TILE_PER_SUPERTILE_H3', 'SC_TILE_PER_SUPERTILE_H4', 'SC_TILE_PER_SUPERTILE_H5', 'SC_TILE_PER_SUPERTILE_H6', 'SC_TILE_PER_SUPERTILE_H7', 'SC_TILE_PER_SUPERTILE_H8', 'SC_TILE_PER_SUPERTILE_H9', 'SC_TILE_PICKED_H1', 'SC_TILE_PICKED_H2', 'SC_TILE_PICKED_H3', 'SC_TILE_PICKED_H4', 'SC_TPQZ_WINDOW_VALID', 'SC_TPQZ_WINDOW_VALID_BUSY', 'SC_TRPK_WINDOW_VALID', 'SC_TRPK_WINDOW_VALID_BUSY', 'SDMA_PERF_SEL', 'SDMA_PERF_SEL_ATCL2_FREE', 'SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', 'SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', 'SDMA_PERF_SEL_ATCL2_RET_ACK', 'SDMA_PERF_SEL_ATCL2_RET_XNACK', 'SDMA_PERF_SEL_CE_AFIFO_FULL', 'SDMA_PERF_SEL_CE_DST_IDLE', 'SDMA_PERF_SEL_CE_INFO1_FULL', 'SDMA_PERF_SEL_CE_INFO_FULL', 'SDMA_PERF_SEL_CE_IN_IDLE', 'SDMA_PERF_SEL_CE_L1_STALL', 'SDMA_PERF_SEL_CE_L1_WR_VLD', 'SDMA_PERF_SEL_CE_OUT_IDLE', 'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE', 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE', 'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL', 'SDMA_PERF_SEL_CTX_CHANGE', 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE', 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND', 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND', 'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_EX_IDLE', 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', 'SDMA_PERF_SEL_F32_L1_WR_VLD', 'SDMA_PERF_SEL_GFX_SELECT', 'SDMA_PERF_SEL_IB_CMD_FULL', 'SDMA_PERF_SEL_IB_CMD_IDLE', 'SDMA_PERF_SEL_IDLE', 'SDMA_PERF_SEL_INT_IDLE', 'SDMA_PERF_SEL_INT_REQ_COUNT', 'SDMA_PERF_SEL_INT_REQ_STALL', 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', 'SDMA_PERF_SEL_INT_RESP_RETRY', 'SDMA_PERF_SEL_IS_INVREQ_ADDR_RD', 'SDMA_PERF_SEL_IS_INVREQ_ADDR_WR', 'SDMA_PERF_SEL_L1_INV_MIDDLE', 'SDMA_PERF_SEL_L1_RDL2_IDLE', 'SDMA_PERF_SEL_L1_RDMC_IDLE', 'SDMA_PERF_SEL_L1_RD_FIFO_IDLE', 'SDMA_PERF_SEL_L1_RD_INV_EN', 'SDMA_PERF_SEL_L1_RD_INV_IDLE', 'SDMA_PERF_SEL_L1_RD_WAIT_INVADR', 'SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', 'SDMA_PERF_SEL_L1_WRL2_IDLE', 'SDMA_PERF_SEL_L1_WRMC_IDLE', 'SDMA_PERF_SEL_L1_WR_FIFO_IDLE', 'SDMA_PERF_SEL_L1_WR_INV_EN', 'SDMA_PERF_SEL_L1_WR_INV_IDLE', 'SDMA_PERF_SEL_L1_WR_WAIT_INVADR', 'SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', 'SDMA_PERF_SEL_MC_RD_COUNT', 'SDMA_PERF_SEL_MC_RD_IDLE', 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', 'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT', 'SDMA_PERF_SEL_MC_WR_IDLE', 'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER', 'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_PAGE_SELECT', 'SDMA_PERF_SEL_RB_CMD_FULL', 'SDMA_PERF_SEL_RB_CMD_IDLE', 'SDMA_PERF_SEL_RB_EMPTY', 'SDMA_PERF_SEL_RB_FULL', 'SDMA_PERF_SEL_RB_RPTR_WB', 'SDMA_PERF_SEL_RB_RPTR_WRAP', 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 'SDMA_PERF_SEL_RB_WPTR_WRAP', 'SDMA_PERF_SEL_RD_BA_RTR', 'SDMA_PERF_SEL_REG_IDLE', 'SDMA_PERF_SEL_RLC0_SELECT', 'SDMA_PERF_SEL_RLC1_SELECT', 'SDMA_PERF_SEL_SDMA_ATCL2_SEND', 'SDMA_PERF_SEL_SDMA_INVACK_FLUSH', 'SDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 'SDMA_PERF_SEL_SEM_IDLE', 'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL', 'SDMA_PERF_SEL_SEM_RESP_FAIL', 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', 'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND', 'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER', 'SDMA_PERF_SEL_WR_BA_RTR', 'SEC_GSP0_PRIORITY_HIGH', 'SEC_GSP0_PRIORITY_LOW', 'SEM_ECC_ERROR', 'SEM_FAILED', 'SEM_PASSED', 'SEM_PERF_SEL', 'SEM_PERF_SEL_ACP_REQ_SIGNAL', 'SEM_PERF_SEL_ACP_REQ_WAIT', 'SEM_PERF_SEL_ATC_INVALIDATION', 'SEM_PERF_SEL_ATC_REQ', 'SEM_PERF_SEL_ATC_RET', 'SEM_PERF_SEL_ATC_XNACK', 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', 'SEM_PERF_SEL_CYCLE', 'SEM_PERF_SEL_IDLE', 'SEM_PERF_SEL_ISP_REQ_SIGNAL', 'SEM_PERF_SEL_ISP_REQ_WAIT', 'SEM_PERF_SEL_MC_RD_REQ', 'SEM_PERF_SEL_MC_RD_RET', 'SEM_PERF_SEL_MC_WR_REQ', 'SEM_PERF_SEL_MC_WR_RET', 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA0_REQ_WAIT', 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA1_REQ_WAIT', 'SEM_PERF_SEL_UVD_REQ_SIGNAL', 'SEM_PERF_SEL_UVD_REQ_WAIT', 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 'SEM_PERF_SEL_VCE0_REQ_WAIT', 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 'SEM_PERF_SEL_VCE1_REQ_WAIT', 'SEM_PERF_SEL_VP8_REQ_SIGNAL', 'SEM_PERF_SEL_VP8_REQ_WAIT', 'SEM_TRANS_ERROR', 'SET_OVERRIDE_CGTT_DCEFCLK', 'SET_OVERRIDE_CGTT_SCLK', 'SET_STATIC_SCREEN_SMU_INTR', 'SH_MEM_ADDRESS_MODE', 'SH_MEM_ADDRESS_MODE_32', 'SH_MEM_ADDRESS_MODE_64', 'SH_MEM_ALIGNMENT_MODE', 'SH_MEM_ALIGNMENT_MODE_DWORD', 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', 'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', 'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START', 'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START', 'SIMM16_WAITCNT_VM_CNT_HI_SIZE', 'SIMM16_WAITCNT_VM_CNT_HI_START', 'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START', 'SMU_INTR_STATUS_CLEAR', 'SMU_INTR_STATUS_NOOP', 'SM_MODE_RESERVED', 'SO_VGTSTREAMOUT_FLUSH', 'SPDIF1_SOFT_RESET', 'SPDIF1_SOFT_RESET_0', 'SPDIF1_SOFT_RESET_1', 'SPDIF_INVERT_DISABLE', 'SPDIF_INVERT_EN', 'SPDIF_INVERT_ENABLE', 'SPI_FOG_EXP', 'SPI_FOG_EXP2', 'SPI_FOG_LINEAR', 'SPI_FOG_MODE', 'SPI_FOG_NONE', 'SPI_PERFCNT_SEL', 'SPI_PERF_CLKGATE_ACTIVE_STALL', 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON', 'SPI_PERF_CLKGATE_BUSY_STALL', 'SPI_PERF_CLKGATE_CGTT_DYN_ON', 'SPI_PERF_CLKGATE_CGTT_REG_ON', 'SPI_PERF_CSG_BUSY', 'SPI_PERF_CSG_CRAWLER_STALL', 'SPI_PERF_CSG_EVENT_WAVE', 'SPI_PERF_CSG_NUM_THREADGROUPS', 'SPI_PERF_CSG_WAVE', 'SPI_PERF_CSG_WINDOW_VALID', 'SPI_PERF_CSN_BUSY', 'SPI_PERF_CSN_CRAWLER_STALL', 'SPI_PERF_CSN_EVENT_WAVE', 'SPI_PERF_CSN_NUM_THREADGROUPS', 'SPI_PERF_CSN_WAVE', 'SPI_PERF_CSN_WINDOW_VALID', 'SPI_PERF_ES_BUSY', 'SPI_PERF_ES_CRAWLER_STALL', 'SPI_PERF_ES_EVENT_WAVE', 'SPI_PERF_ES_FIRST_SUBGRP', 'SPI_PERF_ES_FIRST_WAVE', 'SPI_PERF_ES_GRP_FIFO_FULL', 'SPI_PERF_ES_LAST_SUBGRP', 'SPI_PERF_ES_LAST_WAVE', 'SPI_PERF_ES_LSHS_DEALLOC', 'SPI_PERF_ES_PERS_UPD_FULL0', 'SPI_PERF_ES_PERS_UPD_FULL1', 'SPI_PERF_ES_WAVE', 'SPI_PERF_ES_WINDOW_VALID', 'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT', 'SPI_PERF_EXP_ARB_PAR_CNT', 'SPI_PERF_EXP_ARB_POS_CNT', 'SPI_PERF_GS_BUSY', 'SPI_PERF_GS_CRAWLER_STALL', 'SPI_PERF_GS_EVENT_WAVE', 'SPI_PERF_GS_FIRST_SUBGRP', 'SPI_PERF_GS_GRP_FIFO_FULL', 'SPI_PERF_GS_LAST_SUBGRP', 'SPI_PERF_GS_PERS_UPD_FULL0', 'SPI_PERF_GS_PERS_UPD_FULL1', 'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WINDOW_VALID', 'SPI_PERF_HS_BUSY', 'SPI_PERF_HS_CRAWLER_STALL', 'SPI_PERF_HS_EVENT_WAVE', 'SPI_PERF_HS_FIRST_WAVE', 'SPI_PERF_HS_GRP_FIFO_FULL', 'SPI_PERF_HS_LAST_WAVE', 'SPI_PERF_HS_LSHS_DEALLOC', 'SPI_PERF_HS_PERS_UPD_FULL0', 'SPI_PERF_HS_PERS_UPD_FULL1', 'SPI_PERF_HS_WAVE', 'SPI_PERF_HS_WINDOW_VALID', 'SPI_PERF_LDS0_PC_VALID', 'SPI_PERF_LDS1_PC_VALID', 'SPI_PERF_LS_BUSY', 'SPI_PERF_LS_CRAWLER_STALL', 'SPI_PERF_LS_EVENT_WAVE', 'SPI_PERF_LS_FIRST_WAVE', 'SPI_PERF_LS_GRP_FIFO_FULL', 'SPI_PERF_LS_LAST_WAVE', 'SPI_PERF_LS_PERS_UPD_FULL0', 'SPI_PERF_LS_PERS_UPD_FULL1', 'SPI_PERF_LS_WAVE', 'SPI_PERF_LS_WINDOW_VALID', 'SPI_PERF_NUM_PS_COL_EXPORTS', 'SPI_PERF_NUM_VS_PARAM_EXPORTS', 'SPI_PERF_NUM_VS_POS_EXPORTS', 'SPI_PERF_OFFCHIP_LDS_STALL_LS', 'SPI_PERF_PC_ALLOC_ACCUM', 'SPI_PERF_PC_ALLOC_CNT', 'SPI_PERF_PIX_ALLOC_DB0_STALL', 'SPI_PERF_PIX_ALLOC_DB1_STALL', 'SPI_PERF_PIX_ALLOC_DB2_STALL', 'SPI_PERF_PIX_ALLOC_DB3_STALL', 'SPI_PERF_PIX_ALLOC_PEND_CNT', 'SPI_PERF_PIX_ALLOC_SCB_STALL', 'SPI_PERF_PS_CTL_ACTIVE', 'SPI_PERF_PS_CTL_BUSY', 'SPI_PERF_PS_CTL_CNF_BIN2', 'SPI_PERF_PS_CTL_CNF_BIN3', 'SPI_PERF_PS_CTL_CRAWLER_STALL', 'SPI_PERF_PS_CTL_DEALLOC_BIN0', 'SPI_PERF_PS_CTL_EVENT_WAVE', 'SPI_PERF_PS_CTL_FPOS_BIN1_STALL', 'SPI_PERF_PS_CTL_FPOS_BIN2', 'SPI_PERF_PS_CTL_LDS_RES_FULL', 'SPI_PERF_PS_CTL_OPT_WAVE', 'SPI_PERF_PS_CTL_PASS_BIN0', 'SPI_PERF_PS_CTL_PASS_BIN1', 'SPI_PERF_PS_CTL_PRIM_BIN0', 'SPI_PERF_PS_CTL_PRIM_BIN1', 'SPI_PERF_PS_CTL_WAVE', 'SPI_PERF_PS_CTL_WINDOW_VALID', 'SPI_PERF_PS_PERS_UPD_FULL0', 'SPI_PERF_PS_PERS_UPD_FULL1', 'SPI_PERF_RA_BAR_CU_FULL_CSG', 'SPI_PERF_RA_BAR_CU_FULL_CSN', 'SPI_PERF_RA_BAR_CU_FULL_HS', 'SPI_PERF_RA_BULKY_CU_FULL_CSG', 'SPI_PERF_RA_BULKY_CU_FULL_CSN', 'SPI_PERF_RA_CSG_LOCK', 'SPI_PERF_RA_CSN_LOCK', 'SPI_PERF_RA_ES_LOCK', 'SPI_PERF_RA_GS_LOCK', 'SPI_PERF_RA_HS_LOCK', 'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN', 'SPI_PERF_RA_LDS_CU_FULL_ES', 'SPI_PERF_RA_LDS_CU_FULL_LS', 'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_LS_LOCK', 'SPI_PERF_RA_PIPE_REQ_BIN2', 'SPI_PERF_RA_PS_LOCK_NA', 'SPI_PERF_RA_REQ_NO_ALLOC', 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', 'SPI_PERF_RA_REQ_NO_ALLOC_ES', 'SPI_PERF_RA_REQ_NO_ALLOC_GS', 'SPI_PERF_RA_REQ_NO_ALLOC_HS', 'SPI_PERF_RA_REQ_NO_ALLOC_LS', 'SPI_PERF_RA_REQ_NO_ALLOC_PS', 'SPI_PERF_RA_REQ_NO_ALLOC_VS', 'SPI_PERF_RA_RES_STALL_CSG', 'SPI_PERF_RA_RES_STALL_CSN', 'SPI_PERF_RA_RES_STALL_ES', 'SPI_PERF_RA_RES_STALL_GS', 'SPI_PERF_RA_RES_STALL_HS', 'SPI_PERF_RA_RES_STALL_LS', 'SPI_PERF_RA_RES_STALL_PS', 'SPI_PERF_RA_RES_STALL_VS', 'SPI_PERF_RA_RSV_UPD', 'SPI_PERF_RA_SGPR_SIMD_FULL_CSG', 'SPI_PERF_RA_SGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_SGPR_SIMD_FULL_ES', 'SPI_PERF_RA_SGPR_SIMD_FULL_GS', 'SPI_PERF_RA_SGPR_SIMD_FULL_HS', 'SPI_PERF_RA_SGPR_SIMD_FULL_LS', 'SPI_PERF_RA_SGPR_SIMD_FULL_PS', 'SPI_PERF_RA_SGPR_SIMD_FULL_VS', 'SPI_PERF_RA_TASK_REQ_BIN3', 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', 'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN', 'SPI_PERF_RA_TMP_STALL_ES', 'SPI_PERF_RA_TMP_STALL_GS', 'SPI_PERF_RA_TMP_STALL_HS', 'SPI_PERF_RA_TMP_STALL_LS', 'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_TMP_STALL_VS', 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_ES', 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 'SPI_PERF_RA_VGPR_SIMD_FULL_LS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', 'SPI_PERF_RA_VGPR_SIMD_FULL_VS', 'SPI_PERF_RA_VS_LOCK', 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_ES', 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 'SPI_PERF_RA_WAVE_SIMD_FULL_LS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', 'SPI_PERF_RA_WAVE_SIMD_FULL_VS', 'SPI_PERF_RA_WR_CTL_FULL', 'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN', 'SPI_PERF_RA_WVLIM_STALL_ES', 'SPI_PERF_RA_WVLIM_STALL_GS', 'SPI_PERF_RA_WVLIM_STALL_HS', 'SPI_PERF_RA_WVLIM_STALL_LS', 'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_RA_WVLIM_STALL_VS', 'SPI_PERF_VS_ALLOC_CNT', 'SPI_PERF_VS_BUSY', 'SPI_PERF_VS_CRAWLER_STALL', 'SPI_PERF_VS_EVENT_WAVE', 'SPI_PERF_VS_FIRST_SUBGRP', 'SPI_PERF_VS_FIRST_WAVE', 'SPI_PERF_VS_LAST_SUBGRP', 'SPI_PERF_VS_LAST_WAVE', 'SPI_PERF_VS_LATE_ALLOC_ACCUM', 'SPI_PERF_VS_LATE_ALLOC_FULL', 'SPI_PERF_VS_LSHS_DEALLOC', 'SPI_PERF_VS_PC_STALL', 'SPI_PERF_VS_PERS_UPD_FULL0', 'SPI_PERF_VS_PERS_UPD_FULL1', 'SPI_PERF_VS_POS0_STALL', 'SPI_PERF_VS_POS1_STALL', 'SPI_PERF_VS_WAVE', 'SPI_PERF_VS_WINDOW_VALID', 'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0', 'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE', 'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', 'SPI_SAMPLE_CNTL', 'SPI_SHADER_1COMP', 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', 'SPI_SHADER_32_AR', 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', 'SPI_SHADER_4COMP', 'SPI_SHADER_4COMPRESS', 'SPI_SHADER_EX_FORMAT', 'SPI_SHADER_FORMAT', 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE', 'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR', 'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR', 'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN', 'SQC_PERF_SEL_DCACHE_ATOMIC', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', 'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE', 'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT', 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE', 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT', 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', 'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH', 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO', 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO', 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF', 'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED', 'SQC_PERF_SEL_DCACHE_FLAT_REQ', 'SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT', 'SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL', 'SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL', 'SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS', 'SQC_PERF_SEL_DCACHE_GATCL1_REQUEST', 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX', 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES', 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT', 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL', 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS', 'SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS', 'SQC_PERF_SEL_DCACHE_HITS', 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', 'SQC_PERF_SEL_DCACHE_INPUT_VALIDB', 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY', 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', 'SQC_PERF_SEL_DCACHE_INVAL_INST', 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC', 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST', 'SQC_PERF_SEL_DCACHE_MISSES', 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_DCACHE_MISS_EVICT_READ', 'SQC_PERF_SEL_DCACHE_NONFLAT_REQ', 'SQC_PERF_SEL_DCACHE_REQ', 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', 'SQC_PERF_SEL_DCACHE_REQ_READ_1', 'SQC_PERF_SEL_DCACHE_REQ_READ_16', 'SQC_PERF_SEL_DCACHE_REQ_READ_2', 'SQC_PERF_SEL_DCACHE_REQ_READ_4', 'SQC_PERF_SEL_DCACHE_REQ_READ_8', 'SQC_PERF_SEL_DCACHE_REQ_TIME', 'SQC_PERF_SEL_DCACHE_REQ_WRITE_1', 'SQC_PERF_SEL_DCACHE_REQ_WRITE_2', 'SQC_PERF_SEL_DCACHE_REQ_WRITE_4', 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_DCACHE_VOLATILE', 'SQC_PERF_SEL_DCACHE_WB_ASYNC', 'SQC_PERF_SEL_DCACHE_WB_INST', 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC', 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST', 'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE', 'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE', 'SQC_PERF_SEL_DUMMY_LAST', 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO', 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT', 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO', 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO', 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF', 'SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT', 'SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL', 'SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS', 'SQC_PERF_SEL_ICACHE_GATCL1_REQUEST', 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX', 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES', 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT', 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL', 'SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS', 'SQC_PERF_SEL_ICACHE_HITS', 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', 'SQC_PERF_SEL_ICACHE_INPUT_VALIDB', 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY', 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', 'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES', 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_ICACHE_PREFETCH_1', 'SQC_PERF_SEL_ICACHE_PREFETCH_2', 'SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED', 'SQC_PERF_SEL_ICACHE_REQ', 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_SQ_DCACHE_REQS', 'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ', 'SQC_PERF_SEL_TC_DATA_READ_REQ', 'SQC_PERF_SEL_TC_DATA_WRITE_REQ', 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ', 'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL', 'SQC_PERF_SEL_TC_STARVE', 'SQDEC_BEGIN', 'SQDEC_END', 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', 'SQIND_GLOBAL_REGS_OFFSET', 'SQIND_GLOBAL_REGS_SIZE', 'SQIND_LOCAL_REGS_OFFSET', 'SQIND_LOCAL_REGS_SIZE', 'SQIND_WAVE_HWREGS_OFFSET', 'SQIND_WAVE_HWREGS_SIZE', 'SQIND_WAVE_SGPRS_OFFSET', 'SQIND_WAVE_SGPRS_SIZE', 'SQIND_WAVE_VGPRS_OFFSET', 'SQIND_WAVE_VGPRS_SIZE', 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', 'SQPERFSDEC_BEGIN', 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', 'SQPWRDEC_END', 'SQ_ATTR0', 'SQ_BUFFER_ATOMIC_ADD', 'SQ_BUFFER_ATOMIC_ADD_X2', 'SQ_BUFFER_ATOMIC_AND', 'SQ_BUFFER_ATOMIC_AND_X2', 'SQ_BUFFER_ATOMIC_CMPSWAP', 'SQ_BUFFER_ATOMIC_CMPSWAP_X2', 'SQ_BUFFER_ATOMIC_DEC', 'SQ_BUFFER_ATOMIC_DEC_X2', 'SQ_BUFFER_ATOMIC_INC', 'SQ_BUFFER_ATOMIC_INC_X2', 'SQ_BUFFER_ATOMIC_OR', 'SQ_BUFFER_ATOMIC_OR_X2', 'SQ_BUFFER_ATOMIC_SMAX', 'SQ_BUFFER_ATOMIC_SMAX_X2', 'SQ_BUFFER_ATOMIC_SMIN', 'SQ_BUFFER_ATOMIC_SMIN_X2', 'SQ_BUFFER_ATOMIC_SUB', 'SQ_BUFFER_ATOMIC_SUB_X2', 'SQ_BUFFER_ATOMIC_SWAP', 'SQ_BUFFER_ATOMIC_SWAP_X2', 'SQ_BUFFER_ATOMIC_UMAX', 'SQ_BUFFER_ATOMIC_UMAX_X2', 'SQ_BUFFER_ATOMIC_UMIN', 'SQ_BUFFER_ATOMIC_UMIN_X2', 'SQ_BUFFER_ATOMIC_XOR', 'SQ_BUFFER_ATOMIC_XOR_X2', 'SQ_BUFFER_LOAD_DWORD', 'SQ_BUFFER_LOAD_DWORDX2', 'SQ_BUFFER_LOAD_DWORDX3', 'SQ_BUFFER_LOAD_DWORDX4', 'SQ_BUFFER_LOAD_FORMAT_D16_X', 'SQ_BUFFER_LOAD_FORMAT_D16_XY', 'SQ_BUFFER_LOAD_FORMAT_D16_XYZ', 'SQ_BUFFER_LOAD_FORMAT_D16_XYZW', 'SQ_BUFFER_LOAD_FORMAT_X', 'SQ_BUFFER_LOAD_FORMAT_XY', 'SQ_BUFFER_LOAD_FORMAT_XYZ', 'SQ_BUFFER_LOAD_FORMAT_XYZW', 'SQ_BUFFER_LOAD_SBYTE', 'SQ_BUFFER_LOAD_SSHORT', 'SQ_BUFFER_LOAD_UBYTE', 'SQ_BUFFER_LOAD_USHORT', 'SQ_BUFFER_STORE_BYTE', 'SQ_BUFFER_STORE_DWORD', 'SQ_BUFFER_STORE_DWORDX2', 'SQ_BUFFER_STORE_DWORDX3', 'SQ_BUFFER_STORE_DWORDX4', 'SQ_BUFFER_STORE_FORMAT_D16_X', 'SQ_BUFFER_STORE_FORMAT_D16_XY', 'SQ_BUFFER_STORE_FORMAT_D16_XYZ', 'SQ_BUFFER_STORE_FORMAT_D16_XYZW', 'SQ_BUFFER_STORE_FORMAT_X', 'SQ_BUFFER_STORE_FORMAT_XY', 'SQ_BUFFER_STORE_FORMAT_XYZ', 'SQ_BUFFER_STORE_FORMAT_XYZW', 'SQ_BUFFER_STORE_LDS_DWORD', 'SQ_BUFFER_STORE_SHORT', 'SQ_BUFFER_WBINVL1', 'SQ_BUFFER_WBINVL1_VOL', 'SQ_CAC_POWER_ALU_BUSY', 'SQ_CAC_POWER_GPR_RD', 'SQ_CAC_POWER_GPR_WR', 'SQ_CAC_POWER_LDS_BUSY', 'SQ_CAC_POWER_SEL', 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU', 'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2', 'SQ_CHAN_W', 'SQ_CHAN_X', 'SQ_CHAN_Y', 'SQ_CHAN_Z', 'SQ_CNT1', 'SQ_CNT2', 'SQ_CNT3', 'SQ_CNT4', 'SQ_DISPATCHER_GFX_CNT_PER_RING', 'SQ_DISPATCHER_GFX_MIN', 'SQ_DPP_BOUND_OFF', 'SQ_DPP_BOUND_ZERO', 'SQ_DPP_QUAD_PERM', 'SQ_DPP_ROW_BCAST15', 'SQ_DPP_ROW_BCAST31', 'SQ_DPP_ROW_HALF_MIRROR', 'SQ_DPP_ROW_MIRROR', 'SQ_DPP_ROW_RR1', 'SQ_DPP_ROW_RR10', 'SQ_DPP_ROW_RR11', 'SQ_DPP_ROW_RR12', 'SQ_DPP_ROW_RR13', 'SQ_DPP_ROW_RR14', 'SQ_DPP_ROW_RR15', 'SQ_DPP_ROW_RR2', 'SQ_DPP_ROW_RR3', 'SQ_DPP_ROW_RR4', 'SQ_DPP_ROW_RR5', 'SQ_DPP_ROW_RR6', 'SQ_DPP_ROW_RR7', 'SQ_DPP_ROW_RR8', 'SQ_DPP_ROW_RR9', 'SQ_DPP_ROW_SL1', 'SQ_DPP_ROW_SL10', 'SQ_DPP_ROW_SL11', 'SQ_DPP_ROW_SL12', 'SQ_DPP_ROW_SL13', 'SQ_DPP_ROW_SL14', 'SQ_DPP_ROW_SL15', 'SQ_DPP_ROW_SL2', 'SQ_DPP_ROW_SL3', 'SQ_DPP_ROW_SL4', 'SQ_DPP_ROW_SL5', 'SQ_DPP_ROW_SL6', 'SQ_DPP_ROW_SL7', 'SQ_DPP_ROW_SL8', 'SQ_DPP_ROW_SL9', 'SQ_DPP_ROW_SR1', 'SQ_DPP_ROW_SR10', 'SQ_DPP_ROW_SR11', 'SQ_DPP_ROW_SR12', 'SQ_DPP_ROW_SR13', 'SQ_DPP_ROW_SR14', 'SQ_DPP_ROW_SR15', 'SQ_DPP_ROW_SR2', 'SQ_DPP_ROW_SR3', 'SQ_DPP_ROW_SR4', 'SQ_DPP_ROW_SR5', 'SQ_DPP_ROW_SR6', 'SQ_DPP_ROW_SR7', 'SQ_DPP_ROW_SR8', 'SQ_DPP_ROW_SR9', 'SQ_DPP_WF_RL1', 'SQ_DPP_WF_RR1', 'SQ_DPP_WF_SL1', 'SQ_DPP_WF_SR1', 'SQ_DS_ADD_F32', 'SQ_DS_ADD_RTN_F32', 'SQ_DS_ADD_RTN_U32', 'SQ_DS_ADD_RTN_U64', 'SQ_DS_ADD_SRC2_F32', 'SQ_DS_ADD_SRC2_U32', 'SQ_DS_ADD_SRC2_U64', 'SQ_DS_ADD_U32', 'SQ_DS_ADD_U64', 'SQ_DS_AND_B32', 'SQ_DS_AND_B64', 'SQ_DS_AND_RTN_B32', 'SQ_DS_AND_RTN_B64', 'SQ_DS_AND_SRC2_B32', 'SQ_DS_AND_SRC2_B64', 'SQ_DS_APPEND', 'SQ_DS_BPERMUTE_B32', 'SQ_DS_CMPST_B32', 'SQ_DS_CMPST_B64', 'SQ_DS_CMPST_F32', 'SQ_DS_CMPST_F64', 'SQ_DS_CMPST_RTN_B32', 'SQ_DS_CMPST_RTN_B64', 'SQ_DS_CMPST_RTN_F32', 'SQ_DS_CMPST_RTN_F64', 'SQ_DS_CONDXCHG32_RTN_B128', 'SQ_DS_CONDXCHG32_RTN_B64', 'SQ_DS_CONSUME', 'SQ_DS_DEC_RTN_U32', 'SQ_DS_DEC_RTN_U64', 'SQ_DS_DEC_SRC2_U32', 'SQ_DS_DEC_SRC2_U64', 'SQ_DS_DEC_U32', 'SQ_DS_DEC_U64', 'SQ_DS_GWS_BARRIER', 'SQ_DS_GWS_INIT', 'SQ_DS_GWS_SEMA_BR', 'SQ_DS_GWS_SEMA_P', 'SQ_DS_GWS_SEMA_RELEASE_ALL', 'SQ_DS_GWS_SEMA_V', 'SQ_DS_INC_RTN_U32', 'SQ_DS_INC_RTN_U64', 'SQ_DS_INC_SRC2_U32', 'SQ_DS_INC_SRC2_U64', 'SQ_DS_INC_U32', 'SQ_DS_INC_U64', 'SQ_DS_MAX_F32', 'SQ_DS_MAX_F64', 'SQ_DS_MAX_I32', 'SQ_DS_MAX_I64', 'SQ_DS_MAX_RTN_F32', 'SQ_DS_MAX_RTN_F64', 'SQ_DS_MAX_RTN_I32', 'SQ_DS_MAX_RTN_I64', 'SQ_DS_MAX_RTN_U32', 'SQ_DS_MAX_RTN_U64', 'SQ_DS_MAX_SRC2_F32', 'SQ_DS_MAX_SRC2_F64', 'SQ_DS_MAX_SRC2_I32', 'SQ_DS_MAX_SRC2_I64', 'SQ_DS_MAX_SRC2_U32', 'SQ_DS_MAX_SRC2_U64', 'SQ_DS_MAX_U32', 'SQ_DS_MAX_U64', 'SQ_DS_MIN_F32', 'SQ_DS_MIN_F64', 'SQ_DS_MIN_I32', 'SQ_DS_MIN_I64', 'SQ_DS_MIN_RTN_F32', 'SQ_DS_MIN_RTN_F64', 'SQ_DS_MIN_RTN_I32', 'SQ_DS_MIN_RTN_I64', 'SQ_DS_MIN_RTN_U32', 'SQ_DS_MIN_RTN_U64', 'SQ_DS_MIN_SRC2_F32', 'SQ_DS_MIN_SRC2_F64', 'SQ_DS_MIN_SRC2_I32', 'SQ_DS_MIN_SRC2_I64', 'SQ_DS_MIN_SRC2_U32', 'SQ_DS_MIN_SRC2_U64', 'SQ_DS_MIN_U32', 'SQ_DS_MIN_U64', 'SQ_DS_MSKOR_B32', 'SQ_DS_MSKOR_B64', 'SQ_DS_MSKOR_RTN_B32', 'SQ_DS_MSKOR_RTN_B64', 'SQ_DS_NOP', 'SQ_DS_ORDERED_COUNT', 'SQ_DS_OR_B32', 'SQ_DS_OR_B64', 'SQ_DS_OR_RTN_B32', 'SQ_DS_OR_RTN_B64', 'SQ_DS_OR_SRC2_B32', 'SQ_DS_OR_SRC2_B64', 'SQ_DS_PERMUTE_B32', 'SQ_DS_READ2ST64_B32', 'SQ_DS_READ2ST64_B64', 'SQ_DS_READ2_B32', 'SQ_DS_READ2_B64', 'SQ_DS_READ_ADDTID_B32', 'SQ_DS_READ_B128', 'SQ_DS_READ_B32', 'SQ_DS_READ_B64', 'SQ_DS_READ_B96', 'SQ_DS_READ_I16', 'SQ_DS_READ_I8', 'SQ_DS_READ_U16', 'SQ_DS_READ_U8', 'SQ_DS_RSUB_RTN_U32', 'SQ_DS_RSUB_RTN_U64', 'SQ_DS_RSUB_SRC2_U32', 'SQ_DS_RSUB_SRC2_U64', 'SQ_DS_RSUB_U32', 'SQ_DS_RSUB_U64', 'SQ_DS_SUB_RTN_U32', 'SQ_DS_SUB_RTN_U64', 'SQ_DS_SUB_SRC2_U32', 'SQ_DS_SUB_SRC2_U64', 'SQ_DS_SUB_U32', 'SQ_DS_SUB_U64', 'SQ_DS_SWIZZLE_B32', 'SQ_DS_WRAP_RTN_B32', 'SQ_DS_WRITE2ST64_B32', 'SQ_DS_WRITE2ST64_B64', 'SQ_DS_WRITE2_B32', 'SQ_DS_WRITE2_B64', 'SQ_DS_WRITE_ADDTID_B32', 'SQ_DS_WRITE_B128', 'SQ_DS_WRITE_B16', 'SQ_DS_WRITE_B32', 'SQ_DS_WRITE_B64', 'SQ_DS_WRITE_B8', 'SQ_DS_WRITE_B96', 'SQ_DS_WRITE_SRC2_B32', 'SQ_DS_WRITE_SRC2_B64', 'SQ_DS_WRXCHG2ST64_RTN_B32', 'SQ_DS_WRXCHG2ST64_RTN_B64', 'SQ_DS_WRXCHG2_RTN_B32', 'SQ_DS_WRXCHG2_RTN_B64', 'SQ_DS_WRXCHG_RTN_B32', 'SQ_DS_WRXCHG_RTN_B64', 'SQ_DS_XOR_B32', 'SQ_DS_XOR_B64', 'SQ_DS_XOR_RTN_B32', 'SQ_DS_XOR_RTN_B64', 'SQ_DS_XOR_SRC2_B32', 'SQ_DS_XOR_SRC2_B64', 'SQ_EDC_FUE_CNTL_LDS', 'SQ_EDC_FUE_CNTL_SIMD0', 'SQ_EDC_FUE_CNTL_SIMD1', 'SQ_EDC_FUE_CNTL_SIMD2', 'SQ_EDC_FUE_CNTL_SIMD3', 'SQ_EDC_FUE_CNTL_SQ', 'SQ_EDC_FUE_CNTL_TA', 'SQ_EDC_FUE_CNTL_TCP', 'SQ_EDC_FUE_CNTL_TD', 'SQ_EDC_INFO_SOURCE', 'SQ_EDC_INFO_SOURCE_GDS', 'SQ_EDC_INFO_SOURCE_INST', 'SQ_EDC_INFO_SOURCE_INVALID', 'SQ_EDC_INFO_SOURCE_LDS', 'SQ_EDC_INFO_SOURCE_SGPR', 'SQ_EDC_INFO_SOURCE_TA', 'SQ_EDC_INFO_SOURCE_VGPR', 'SQ_ENC_DS_BITS', 'SQ_ENC_DS_FIELD', 'SQ_ENC_DS_MASK', 'SQ_ENC_EXP_BITS', 'SQ_ENC_EXP_FIELD', 'SQ_ENC_EXP_MASK', 'SQ_ENC_FLAT_BITS', 'SQ_ENC_FLAT_FIELD', 'SQ_ENC_FLAT_MASK', 'SQ_ENC_MIMG_BITS', 'SQ_ENC_MIMG_FIELD', 'SQ_ENC_MIMG_MASK', 'SQ_ENC_MTBUF_BITS', 'SQ_ENC_MTBUF_FIELD', 'SQ_ENC_MTBUF_MASK', 'SQ_ENC_MUBUF_BITS', 'SQ_ENC_MUBUF_FIELD', 'SQ_ENC_MUBUF_MASK', 'SQ_ENC_SMEM_BITS', 'SQ_ENC_SMEM_FIELD', 'SQ_ENC_SMEM_MASK', 'SQ_ENC_SOP1_BITS', 'SQ_ENC_SOP1_FIELD', 'SQ_ENC_SOP1_MASK', 'SQ_ENC_SOP2_BITS', 'SQ_ENC_SOP2_FIELD', 'SQ_ENC_SOP2_MASK', 'SQ_ENC_SOPC_BITS', 'SQ_ENC_SOPC_FIELD', 'SQ_ENC_SOPC_MASK', 'SQ_ENC_SOPK_BITS', 'SQ_ENC_SOPK_FIELD', 'SQ_ENC_SOPK_MASK', 'SQ_ENC_SOPP_BITS', 'SQ_ENC_SOPP_FIELD', 'SQ_ENC_SOPP_MASK', 'SQ_ENC_VINTRP_BITS', 'SQ_ENC_VINTRP_FIELD', 'SQ_ENC_VINTRP_MASK', 'SQ_ENC_VOP1_BITS', 'SQ_ENC_VOP1_FIELD', 'SQ_ENC_VOP1_MASK', 'SQ_ENC_VOP2_BITS', 'SQ_ENC_VOP2_FIELD', 'SQ_ENC_VOP2_MASK', 'SQ_ENC_VOP3P_BITS', 'SQ_ENC_VOP3P_FIELD', 'SQ_ENC_VOP3P_MASK', 'SQ_ENC_VOP3_BITS', 'SQ_ENC_VOP3_FIELD', 'SQ_ENC_VOP3_MASK', 'SQ_ENC_VOPC_BITS', 'SQ_ENC_VOPC_FIELD', 'SQ_ENC_VOPC_MASK', 'SQ_EQ', 'SQ_EXEC_HI', 'SQ_EXEC_LO', 'SQ_EXP', 'SQ_EXPORT_RAT_INST_ADD', 'SQ_EXPORT_RAT_INST_ADD_RTN', 'SQ_EXPORT_RAT_INST_AND', 'SQ_EXPORT_RAT_INST_AND_RTN', 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM', 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN', 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT', 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN', 'SQ_EXPORT_RAT_INST_CMPXCHG_INT', 'SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN', 'SQ_EXPORT_RAT_INST_DEC_UINT', 'SQ_EXPORT_RAT_INST_DEC_UINT_RTN', 'SQ_EXPORT_RAT_INST_INC_UINT', 'SQ_EXPORT_RAT_INST_INC_UINT_RTN', 'SQ_EXPORT_RAT_INST_MAX_INT', 'SQ_EXPORT_RAT_INST_MAX_INT_RTN', 'SQ_EXPORT_RAT_INST_MAX_UINT', 'SQ_EXPORT_RAT_INST_MAX_UINT_RTN', 'SQ_EXPORT_RAT_INST_MIN_INT', 'SQ_EXPORT_RAT_INST_MIN_INT_RTN', 'SQ_EXPORT_RAT_INST_MIN_UINT', 'SQ_EXPORT_RAT_INST_MIN_UINT_RTN', 'SQ_EXPORT_RAT_INST_MSKOR', 'SQ_EXPORT_RAT_INST_MSKOR_RTN', 'SQ_EXPORT_RAT_INST_NOP', 'SQ_EXPORT_RAT_INST_NOP_RTN', 'SQ_EXPORT_RAT_INST_OR', 'SQ_EXPORT_RAT_INST_OR_RTN', 'SQ_EXPORT_RAT_INST_RSUB', 'SQ_EXPORT_RAT_INST_RSUB_RTN', 'SQ_EXPORT_RAT_INST_STORE_BYTE', 'SQ_EXPORT_RAT_INST_STORE_DWORD', 'SQ_EXPORT_RAT_INST_STORE_RAW', 'SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM', 'SQ_EXPORT_RAT_INST_STORE_SHORT', 'SQ_EXPORT_RAT_INST_STORE_TYPED', 'SQ_EXPORT_RAT_INST_SUB', 'SQ_EXPORT_RAT_INST_SUB_RTN', 'SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN', 'SQ_EXPORT_RAT_INST_XCHG_RTN', 'SQ_EXPORT_RAT_INST_XOR', 'SQ_EXPORT_RAT_INST_XOR_RTN', 'SQ_EXP_GDS0', 'SQ_EXP_MRT0', 'SQ_EXP_MRTZ', 'SQ_EXP_NULL', 'SQ_EXP_NUM_GDS', 'SQ_EXP_NUM_MRT', 'SQ_EXP_NUM_PARAM', 'SQ_EXP_NUM_POS', 'SQ_EXP_PARAM0', 'SQ_EXP_POS0', 'SQ_EX_MODE_EXCP_ADDR_WATCH0', 'SQ_EX_MODE_EXCP_DIV0', 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH1', 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH2', 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH3', 'SQ_EX_MODE_EXCP_INEXACT', 'SQ_EX_MODE_EXCP_INPUT_DENORM', 'SQ_EX_MODE_EXCP_INT_DIV0', 'SQ_EX_MODE_EXCP_INVALID', 'SQ_EX_MODE_EXCP_MEM_VIOL', 'SQ_EX_MODE_EXCP_OVERFLOW', 'SQ_EX_MODE_EXCP_UNDERFLOW', 'SQ_EX_MODE_EXCP_VALU_BASE', 'SQ_EX_MODE_EXCP_VALU_SIZE', 'SQ_F', 'SQ_FLAT', 'SQ_FLAT_ATOMIC_ADD', 'SQ_FLAT_ATOMIC_ADD_X2', 'SQ_FLAT_ATOMIC_AND', 'SQ_FLAT_ATOMIC_AND_X2', 'SQ_FLAT_ATOMIC_CMPSWAP', 'SQ_FLAT_ATOMIC_CMPSWAP_X2', 'SQ_FLAT_ATOMIC_DEC', 'SQ_FLAT_ATOMIC_DEC_X2', 'SQ_FLAT_ATOMIC_INC', 'SQ_FLAT_ATOMIC_INC_X2', 'SQ_FLAT_ATOMIC_OR', 'SQ_FLAT_ATOMIC_OR_X2', 'SQ_FLAT_ATOMIC_SMAX', 'SQ_FLAT_ATOMIC_SMAX_X2', 'SQ_FLAT_ATOMIC_SMIN', 'SQ_FLAT_ATOMIC_SMIN_X2', 'SQ_FLAT_ATOMIC_SUB', 'SQ_FLAT_ATOMIC_SUB_X2', 'SQ_FLAT_ATOMIC_SWAP', 'SQ_FLAT_ATOMIC_SWAP_X2', 'SQ_FLAT_ATOMIC_UMAX', 'SQ_FLAT_ATOMIC_UMAX_X2', 'SQ_FLAT_ATOMIC_UMIN', 'SQ_FLAT_ATOMIC_UMIN_X2', 'SQ_FLAT_ATOMIC_XOR', 'SQ_FLAT_ATOMIC_XOR_X2', 'SQ_FLAT_LOAD_DWORD', 'SQ_FLAT_LOAD_DWORDX2', 'SQ_FLAT_LOAD_DWORDX3', 'SQ_FLAT_LOAD_DWORDX4', 'SQ_FLAT_LOAD_SBYTE', 'SQ_FLAT_LOAD_SSHORT', 'SQ_FLAT_LOAD_UBYTE', 'SQ_FLAT_LOAD_USHORT', 'SQ_FLAT_SCRATCH_HI', 'SQ_FLAT_SCRATCH_LO', 'SQ_FLAT_STORE_BYTE', 'SQ_FLAT_STORE_DWORD', 'SQ_FLAT_STORE_DWORDX2', 'SQ_FLAT_STORE_DWORDX3', 'SQ_FLAT_STORE_DWORDX4', 'SQ_FLAT_STORE_SHORT', 'SQ_GE', 'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT', 'SQ_GLOBAL', 'SQ_GLOBAL_ATOMIC_ADD', 'SQ_GLOBAL_ATOMIC_ADD_X2', 'SQ_GLOBAL_ATOMIC_AND', 'SQ_GLOBAL_ATOMIC_AND_X2', 'SQ_GLOBAL_ATOMIC_CMPSWAP', 'SQ_GLOBAL_ATOMIC_CMPSWAP_X2', 'SQ_GLOBAL_ATOMIC_DEC', 'SQ_GLOBAL_ATOMIC_DEC_X2', 'SQ_GLOBAL_ATOMIC_INC', 'SQ_GLOBAL_ATOMIC_INC_X2', 'SQ_GLOBAL_ATOMIC_OR', 'SQ_GLOBAL_ATOMIC_OR_X2', 'SQ_GLOBAL_ATOMIC_SMAX', 'SQ_GLOBAL_ATOMIC_SMAX_X2', 'SQ_GLOBAL_ATOMIC_SMIN', 'SQ_GLOBAL_ATOMIC_SMIN_X2', 'SQ_GLOBAL_ATOMIC_SUB', 'SQ_GLOBAL_ATOMIC_SUB_X2', 'SQ_GLOBAL_ATOMIC_SWAP', 'SQ_GLOBAL_ATOMIC_SWAP_X2', 'SQ_GLOBAL_ATOMIC_UMAX', 'SQ_GLOBAL_ATOMIC_UMAX_X2', 'SQ_GLOBAL_ATOMIC_UMIN', 'SQ_GLOBAL_ATOMIC_UMIN_X2', 'SQ_GLOBAL_ATOMIC_XOR', 'SQ_GLOBAL_ATOMIC_XOR_X2', 'SQ_GLOBAL_LOAD_DWORD', 'SQ_GLOBAL_LOAD_DWORDX2', 'SQ_GLOBAL_LOAD_DWORDX3', 'SQ_GLOBAL_LOAD_DWORDX4', 'SQ_GLOBAL_LOAD_SBYTE', 'SQ_GLOBAL_LOAD_SSHORT', 'SQ_GLOBAL_LOAD_UBYTE', 'SQ_GLOBAL_LOAD_USHORT', 'SQ_GLOBAL_STORE_BYTE', 'SQ_GLOBAL_STORE_DWORD', 'SQ_GLOBAL_STORE_DWORDX2', 'SQ_GLOBAL_STORE_DWORDX3', 'SQ_GLOBAL_STORE_DWORDX4', 'SQ_GLOBAL_STORE_SHORT', 'SQ_GS_OP_CUT', 'SQ_GS_OP_EMIT', 'SQ_GS_OP_EMIT_CUT', 'SQ_GS_OP_NOP', 'SQ_GT', 'SQ_HWREG_ID_SHIFT', 'SQ_HWREG_ID_SIZE', 'SQ_HWREG_OFFSET_SHIFT', 'SQ_HWREG_OFFSET_SIZE', 'SQ_HWREG_SIZE_SHIFT', 'SQ_HWREG_SIZE_SIZE', 'SQ_HW_REG_FLUSH_IB', 'SQ_HW_REG_GPR_ALLOC', 'SQ_HW_REG_HW_ID', 'SQ_HW_REG_IB_DBG0', 'SQ_HW_REG_IB_DBG1', 'SQ_HW_REG_IB_STS', 'SQ_HW_REG_INST_DW0', 'SQ_HW_REG_INST_DW1', 'SQ_HW_REG_LDS_ALLOC', 'SQ_HW_REG_MODE', 'SQ_HW_REG_PC_HI', 'SQ_HW_REG_PC_LO', 'SQ_HW_REG_SH_MEM_BASES', 'SQ_HW_REG_SQ_SHADER_TBA_HI', 'SQ_HW_REG_SQ_SHADER_TBA_LO', 'SQ_HW_REG_SQ_SHADER_TMA_HI', 'SQ_HW_REG_SQ_SHADER_TMA_LO', 'SQ_HW_REG_STATUS', 'SQ_HW_REG_TRAPSTS', 'SQ_IBUF_IB_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_GNT', 'SQ_IBUF_IB_IDLE', 'SQ_IBUF_IB_INI_WAIT_DRET', 'SQ_IBUF_IB_INI_WAIT_GNT', 'SQ_IBUF_IB_LE_4DW', 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST', 'SQ_IMAGE_ATOMIC_ADD', 'SQ_IMAGE_ATOMIC_AND', 'SQ_IMAGE_ATOMIC_CMPSWAP', 'SQ_IMAGE_ATOMIC_DEC', 'SQ_IMAGE_ATOMIC_INC', 'SQ_IMAGE_ATOMIC_OR', 'SQ_IMAGE_ATOMIC_SMAX', 'SQ_IMAGE_ATOMIC_SMIN', 'SQ_IMAGE_ATOMIC_SUB', 'SQ_IMAGE_ATOMIC_SWAP', 'SQ_IMAGE_ATOMIC_UMAX', 'SQ_IMAGE_ATOMIC_UMIN', 'SQ_IMAGE_ATOMIC_XOR', 'SQ_IMAGE_GATHER4', 'SQ_IMAGE_GATHER4H', 'SQ_IMAGE_GATHER4H_PCK', 'SQ_IMAGE_GATHER4_B', 'SQ_IMAGE_GATHER4_B_CL', 'SQ_IMAGE_GATHER4_B_CL_O', 'SQ_IMAGE_GATHER4_B_O', 'SQ_IMAGE_GATHER4_C', 'SQ_IMAGE_GATHER4_CL', 'SQ_IMAGE_GATHER4_CL_O', 'SQ_IMAGE_GATHER4_C_B', 'SQ_IMAGE_GATHER4_C_B_CL', 'SQ_IMAGE_GATHER4_C_B_CL_O', 'SQ_IMAGE_GATHER4_C_B_O', 'SQ_IMAGE_GATHER4_C_CL', 'SQ_IMAGE_GATHER4_C_CL_O', 'SQ_IMAGE_GATHER4_C_L', 'SQ_IMAGE_GATHER4_C_LZ', 'SQ_IMAGE_GATHER4_C_LZ_O', 'SQ_IMAGE_GATHER4_C_L_O', 'SQ_IMAGE_GATHER4_C_O', 'SQ_IMAGE_GATHER4_L', 'SQ_IMAGE_GATHER4_LZ', 'SQ_IMAGE_GATHER4_LZ_O', 'SQ_IMAGE_GATHER4_L_O', 'SQ_IMAGE_GATHER4_O', 'SQ_IMAGE_GATHER8H_PCK', 'SQ_IMAGE_GET_LOD', 'SQ_IMAGE_GET_RESINFO', 'SQ_IMAGE_LOAD', 'SQ_IMAGE_LOAD_MIP', 'SQ_IMAGE_LOAD_MIP_PCK', 'SQ_IMAGE_LOAD_MIP_PCK_SGN', 'SQ_IMAGE_LOAD_PCK', 'SQ_IMAGE_LOAD_PCK_SGN', 'SQ_IMAGE_RSRC256', 'SQ_IMAGE_SAMPLE', 'SQ_IMAGE_SAMPLER', 'SQ_IMAGE_SAMPLE_B', 'SQ_IMAGE_SAMPLE_B_CL', 'SQ_IMAGE_SAMPLE_B_CL_O', 'SQ_IMAGE_SAMPLE_B_O', 'SQ_IMAGE_SAMPLE_C', 'SQ_IMAGE_SAMPLE_CD', 'SQ_IMAGE_SAMPLE_CD_CL', 'SQ_IMAGE_SAMPLE_CD_CL_O', 'SQ_IMAGE_SAMPLE_CD_O', 'SQ_IMAGE_SAMPLE_CL', 'SQ_IMAGE_SAMPLE_CL_O', 'SQ_IMAGE_SAMPLE_C_B', 'SQ_IMAGE_SAMPLE_C_B_CL', 'SQ_IMAGE_SAMPLE_C_B_CL_O', 'SQ_IMAGE_SAMPLE_C_B_O', 'SQ_IMAGE_SAMPLE_C_CD', 'SQ_IMAGE_SAMPLE_C_CD_CL', 'SQ_IMAGE_SAMPLE_C_CD_CL_O', 'SQ_IMAGE_SAMPLE_C_CD_O', 'SQ_IMAGE_SAMPLE_C_CL', 'SQ_IMAGE_SAMPLE_C_CL_O', 'SQ_IMAGE_SAMPLE_C_D', 'SQ_IMAGE_SAMPLE_C_D_CL', 'SQ_IMAGE_SAMPLE_C_D_CL_O', 'SQ_IMAGE_SAMPLE_C_D_O', 'SQ_IMAGE_SAMPLE_C_L', 'SQ_IMAGE_SAMPLE_C_LZ', 'SQ_IMAGE_SAMPLE_C_LZ_O', 'SQ_IMAGE_SAMPLE_C_L_O', 'SQ_IMAGE_SAMPLE_C_O', 'SQ_IMAGE_SAMPLE_D', 'SQ_IMAGE_SAMPLE_D_CL', 'SQ_IMAGE_SAMPLE_D_CL_O', 'SQ_IMAGE_SAMPLE_D_O', 'SQ_IMAGE_SAMPLE_L', 'SQ_IMAGE_SAMPLE_LZ', 'SQ_IMAGE_SAMPLE_LZ_O', 'SQ_IMAGE_SAMPLE_L_O', 'SQ_IMAGE_SAMPLE_O', 'SQ_IMAGE_STORE', 'SQ_IMAGE_STORE_MIP', 'SQ_IMAGE_STORE_MIP_PCK', 'SQ_IMAGE_STORE_PCK', 'SQ_IMG_FILTER_MODE_BLEND', 'SQ_IMG_FILTER_MODE_MAX', 'SQ_IMG_FILTER_MODE_MIN', 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD', 'SQ_IND_CMD_CMD_DEBUG', 'SQ_IND_CMD_CMD_KILL', 'SQ_IND_CMD_CMD_NULL', 'SQ_IND_CMD_CMD_SAVECTX', 'SQ_IND_CMD_CMD_SETFATALHALT', 'SQ_IND_CMD_CMD_SETHALT', 'SQ_IND_CMD_CMD_SET_SPI_PRIO', 'SQ_IND_CMD_CMD_TRAP', 'SQ_IND_CMD_MODE', 'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME', 'SQ_IND_CMD_MODE_BROADCAST_PIPE', 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE', 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML', 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0', 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1', 'SQ_INST_STR_ST', 'SQ_INTERRUPT_WORD_ENCODING', 'SQ_INTERRUPT_WORD_ENCODING_AUTO', 'SQ_INTERRUPT_WORD_ENCODING_ERROR', 'SQ_INTERRUPT_WORD_ENCODING_INST', 'SQ_L1', 'SQ_L10', 'SQ_L11', 'SQ_L12', 'SQ_L13', 'SQ_L14', 'SQ_L15', 'SQ_L2', 'SQ_L3', 'SQ_L4', 'SQ_L5', 'SQ_L6', 'SQ_L7', 'SQ_L8', 'SQ_L9', 'SQ_LB_CTR_SEL_ALU_CYCLES', 'SQ_LB_CTR_SEL_ALU_STALLS', 'SQ_LB_CTR_SEL_DCACHE_STALLS', 'SQ_LB_CTR_SEL_ICACHE_STALLS', 'SQ_LB_CTR_SEL_RESERVED0', 'SQ_LB_CTR_SEL_RESERVED1', 'SQ_LB_CTR_SEL_RESERVED2', 'SQ_LB_CTR_SEL_RESERVED3', 'SQ_LB_CTR_SEL_RESERVED4', 'SQ_LB_CTR_SEL_RESERVED5', 'SQ_LB_CTR_SEL_RESERVED6', 'SQ_LB_CTR_SEL_SALU_CYCLES', 'SQ_LB_CTR_SEL_SCALAR_STALLS', 'SQ_LB_CTR_SEL_SMEM_CYCLES', 'SQ_LB_CTR_SEL_TEX_CYCLES', 'SQ_LB_CTR_SEL_TEX_STALLS', 'SQ_LB_CTR_SEL_VALUES', 'SQ_LE', 'SQ_LG', 'SQ_LT', 'SQ_M0', 'SQ_MAX_PGM_SGPRS', 'SQ_MAX_PGM_VGPRS', 'SQ_MSG_EARLY_PRIM_DEALLOC', 'SQ_MSG_GS', 'SQ_MSG_GS_ALLOC_REQ', 'SQ_MSG_GS_DONE', 'SQ_MSG_HALT_WAVES', 'SQ_MSG_INTERRUPT', 'SQ_MSG_ORDERED_PS_DONE', 'SQ_MSG_SAVEWAVE', 'SQ_MSG_STALL_WAVE_GEN', 'SQ_MSG_SYSMSG', 'SQ_NE', 'SQ_NEQ', 'SQ_NGE', 'SQ_NGT', 'SQ_NLE', 'SQ_NLG', 'SQ_NLT', 'SQ_NON_EVENT', 'SQ_NUM_ATTR', 'SQ_NUM_SGPR', 'SQ_NUM_TTMP', 'SQ_NUM_VGPR', 'SQ_O', 'SQ_OMOD_D2', 'SQ_OMOD_M2', 'SQ_OMOD_M4', 'SQ_OMOD_OFF', 'SQ_PARAM_P0', 'SQ_PARAM_P10', 'SQ_PARAM_P20', 'SQ_PERF_SEL', 'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_ACCUM_PREV_HIRES', 'SQ_PERF_SEL_ACTIVE_INST_ANY', 'SQ_PERF_SEL_ACTIVE_INST_EXP_GDS', 'SQ_PERF_SEL_ACTIVE_INST_FLAT', 'SQ_PERF_SEL_ACTIVE_INST_LDS', 'SQ_PERF_SEL_ACTIVE_INST_MISC', 'SQ_PERF_SEL_ACTIVE_INST_SCA', 'SQ_PERF_SEL_ACTIVE_INST_VALU', 'SQ_PERF_SEL_ACTIVE_INST_VMEM', 'SQ_PERF_SEL_ATC_INSTS_SMEM', 'SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY', 'SQ_PERF_SEL_ATC_INSTS_VMEM', 'SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY', 'SQ_PERF_SEL_ATC_INST_LEVEL_SMEM', 'SQ_PERF_SEL_ATC_INST_LEVEL_VMEM', 'SQ_PERF_SEL_ATC_XNACK_ALL', 'SQ_PERF_SEL_ATC_XNACK_FIFO_FULL', 'SQ_PERF_SEL_ATC_XNACK_FIRST', 'SQ_PERF_SEL_BUSY_CU_CYCLES', 'SQ_PERF_SEL_BUSY_CYCLES', 'SQ_PERF_SEL_CBRANCH_FORK', 'SQ_PERF_SEL_CBRANCH_FORK_SPLIT', 'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END', 'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS', 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', 'SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT', 'SQ_PERF_SEL_IFETCH', 'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_XNACK', 'SQ_PERF_SEL_INSTS', 'SQ_PERF_SEL_INSTS_BRANCH', 'SQ_PERF_SEL_INSTS_EXP', 'SQ_PERF_SEL_INSTS_EXP_GDS', 'SQ_PERF_SEL_INSTS_FLAT', 'SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY', 'SQ_PERF_SEL_INSTS_FLAT_REPLAY', 'SQ_PERF_SEL_INSTS_GDS', 'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_SALU', 'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM', 'SQ_PERF_SEL_INSTS_SMEM_NORM', 'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY', 'SQ_PERF_SEL_INSTS_SMEM_REPLAY', 'SQ_PERF_SEL_INSTS_VALU', 'SQ_PERF_SEL_INSTS_VMEM', 'SQ_PERF_SEL_INSTS_VMEM_RD', 'SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY', 'SQ_PERF_SEL_INSTS_VMEM_REPLAY', 'SQ_PERF_SEL_INSTS_VMEM_WR', 'SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY', 'SQ_PERF_SEL_INSTS_VSKIPPED', 'SQ_PERF_SEL_INST_CYCLES_EXP', 'SQ_PERF_SEL_INST_CYCLES_GDS', 'SQ_PERF_SEL_INST_CYCLES_SALU', 'SQ_PERF_SEL_INST_CYCLES_SMEM', 'SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR', 'SQ_PERF_SEL_INST_CYCLES_VMEM_CMD', 'SQ_PERF_SEL_INST_CYCLES_VMEM_DATA', 'SQ_PERF_SEL_INST_CYCLES_VMEM_RD', 'SQ_PERF_SEL_INST_CYCLES_VMEM_WR', 'SQ_PERF_SEL_INST_LEVEL_EXP', 'SQ_PERF_SEL_INST_LEVEL_GDS', 'SQ_PERF_SEL_INST_LEVEL_LDS', 'SQ_PERF_SEL_INST_LEVEL_SMEM', 'SQ_PERF_SEL_INST_LEVEL_VMEM', 'SQ_PERF_SEL_ITEMS', 'SQ_PERF_SEL_LDS_ADDR_CONFLICT', 'SQ_PERF_SEL_LDS_ATOMIC_RETURN', 'SQ_PERF_SEL_LDS_BANK_CONFLICT', 'SQ_PERF_SEL_LDS_CMD_FIFO_FULL', 'SQ_PERF_SEL_LDS_DATA_FIFO_FULL', 'SQ_PERF_SEL_LDS_IDX_ACTIVE', 'SQ_PERF_SEL_LDS_MEM_VIOLATIONS', 'SQ_PERF_SEL_LDS_SRC_CD_CONFLICT', 'SQ_PERF_SEL_LDS_UNALIGNED_STALL', 'SQ_PERF_SEL_LEVEL_WAVES', 'SQ_PERF_SEL_LEVEL_WAVES_CU', 'SQ_PERF_SEL_MSG_CNTR', 'SQ_PERF_SEL_MSG_GSCNT', 'SQ_PERF_SEL_MSG_INTERRUPT', 'SQ_PERF_SEL_MSG_PERF', 'SQ_PERF_SEL_NONE', 'SQ_PERF_SEL_POWER_ALU_BUSY', 'SQ_PERF_SEL_POWER_GPR_RD', 'SQ_PERF_SEL_POWER_GPR_WR', 'SQ_PERF_SEL_POWER_LDS_BUSY', 'SQ_PERF_SEL_POWER_TEX_BUSY', 'SQ_PERF_SEL_POWER_VALU', 'SQ_PERF_SEL_POWER_VALU0', 'SQ_PERF_SEL_POWER_VALU1', 'SQ_PERF_SEL_POWER_VALU2', 'SQ_PERF_SEL_PT_POWER_STALL', 'SQ_PERF_SEL_QUADS', 'SQ_PERF_SEL_SRC_CD_BUSY', 'SQ_PERF_SEL_SURF_SYNCS', 'SQ_PERF_SEL_THREAD_CYCLES_VALU', 'SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX', 'SQ_PERF_SEL_TLB_SHOOTDOWN', 'SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES', 'SQ_PERF_SEL_TTRACE_INFLIGHT_REQS', 'SQ_PERF_SEL_TTRACE_REQS', 'SQ_PERF_SEL_TTRACE_STALL', 'SQ_PERF_SEL_USER0', 'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11', 'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14', 'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3', 'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6', 'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9', 'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1', 'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11', 'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13', 'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15', 'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3', 'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5', 'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7', 'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9', 'SQ_PERF_SEL_UTCL1_LFIFO_FULL', 'SQ_PERF_SEL_UTCL1_PERMISSION_MISS', 'SQ_PERF_SEL_UTCL1_REQUEST', 'SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', 'SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', 'SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', 'SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', 'SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', 'SQ_PERF_SEL_UTCL1_TRANSLATION_MISS', 'SQ_PERF_SEL_VALU_DEP_STALL', 'SQ_PERF_SEL_VALU_LDS_DIRECT_RD', 'SQ_PERF_SEL_VALU_LDS_INTERP_OP', 'SQ_PERF_SEL_VALU_SRC_C_CONFLICT', 'SQ_PERF_SEL_VALU_STARVE', 'SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY', 'SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT', 'SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL', 'SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL', 'SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT', 'SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL', 'SQ_PERF_SEL_WAIT_ANY', 'SQ_PERF_SEL_WAIT_BARRIER', 'SQ_PERF_SEL_WAIT_CNT_ANY', 'SQ_PERF_SEL_WAIT_CNT_EXP', 'SQ_PERF_SEL_WAIT_CNT_LGKM', 'SQ_PERF_SEL_WAIT_CNT_VM', 'SQ_PERF_SEL_WAIT_EXP_ALLOC', 'SQ_PERF_SEL_WAIT_IFETCH', 'SQ_PERF_SEL_WAIT_INST_ANY', 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', 'SQ_PERF_SEL_WAIT_INST_FLAT', 'SQ_PERF_SEL_WAIT_INST_LDS', 'SQ_PERF_SEL_WAIT_INST_MISC', 'SQ_PERF_SEL_WAIT_INST_SCA', 'SQ_PERF_SEL_WAIT_INST_VALU', 'SQ_PERF_SEL_WAIT_INST_VMEM', 'SQ_PERF_SEL_WAIT_OTHER', 'SQ_PERF_SEL_WAIT_SLEEP', 'SQ_PERF_SEL_WAIT_SLEEP_XNACK', 'SQ_PERF_SEL_WAIT_TTRACE', 'SQ_PERF_SEL_WAVES', 'SQ_PERF_SEL_WAVES_CU', 'SQ_PERF_SEL_WAVES_EQ_64', 'SQ_PERF_SEL_WAVES_LT_16', 'SQ_PERF_SEL_WAVES_LT_32', 'SQ_PERF_SEL_WAVES_LT_48', 'SQ_PERF_SEL_WAVES_LT_64', 'SQ_PERF_SEL_WAVES_RESTORED', 'SQ_PERF_SEL_WAVES_SAVED', 'SQ_PERF_SEL_WAVE_CYCLES', 'SQ_PERF_SEL_WAVE_READY', 'SQ_R1', 'SQ_R10', 'SQ_R11', 'SQ_R12', 'SQ_R13', 'SQ_R14', 'SQ_R15', 'SQ_R2', 'SQ_R3', 'SQ_R4', 'SQ_R5', 'SQ_R6', 'SQ_R7', 'SQ_R8', 'SQ_R9', 'SQ_ROUND_MINUS_INFINITY', 'SQ_ROUND_MODE', 'SQ_ROUND_NEAREST_EVEN', 'SQ_ROUND_PLUS_INFINITY', 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', 'SQ_RSRC_BUF_RSVD_1', 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', 'SQ_RSRC_BUF_TYPE', 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', 'SQ_RSRC_FLAT_RSVD_2', 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', 'SQ_RSRC_IMG_1D', 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', 'SQ_RSRC_IMG_2D_ARRAY', 'SQ_RSRC_IMG_2D_MSAA', 'SQ_RSRC_IMG_2D_MSAA_ARRAY', 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', 'SQ_RSRC_IMG_RSVD_0', 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', 'SQ_RSRC_IMG_RSVD_3', 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', 'SQ_RSRC_IMG_RSVD_6', 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', 'SQ_SCRATCH', 'SQ_SCRATCH_LOAD_DWORD', 'SQ_SCRATCH_LOAD_DWORDX2', 'SQ_SCRATCH_LOAD_DWORDX3', 'SQ_SCRATCH_LOAD_DWORDX4', 'SQ_SCRATCH_LOAD_SBYTE', 'SQ_SCRATCH_LOAD_SSHORT', 'SQ_SCRATCH_LOAD_UBYTE', 'SQ_SCRATCH_LOAD_USHORT', 'SQ_SCRATCH_STORE_BYTE', 'SQ_SCRATCH_STORE_DWORD', 'SQ_SCRATCH_STORE_DWORDX2', 'SQ_SCRATCH_STORE_DWORDX3', 'SQ_SCRATCH_STORE_DWORDX4', 'SQ_SCRATCH_STORE_SHORT', 'SQ_SDWA_BYTE_0', 'SQ_SDWA_BYTE_1', 'SQ_SDWA_BYTE_2', 'SQ_SDWA_BYTE_3', 'SQ_SDWA_DWORD', 'SQ_SDWA_UNUSED_PAD', 'SQ_SDWA_UNUSED_PRESERVE', 'SQ_SDWA_UNUSED_SEXT', 'SQ_SDWA_WORD_0', 'SQ_SDWA_WORD_1', 'SQ_SEL_0', 'SQ_SEL_1', 'SQ_SEL_RESERVED_0', 'SQ_SEL_RESERVED_1', 'SQ_SEL_W', 'SQ_SEL_X', 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', 'SQ_SENDMSG_GSOP_SHIFT', 'SQ_SENDMSG_GSOP_SIZE', 'SQ_SENDMSG_MSG_SHIFT', 'SQ_SENDMSG_MSG_SIZE', 'SQ_SENDMSG_STREAMID_SHIFT', 'SQ_SENDMSG_STREAMID_SIZE', 'SQ_SENDMSG_SYSTEM_SHIFT', 'SQ_SENDMSG_SYSTEM_SIZE', 'SQ_SGPR0', 'SQ_SRC_0', 'SQ_SRC_0_5', 'SQ_SRC_1', 'SQ_SRC_10_INT', 'SQ_SRC_11_INT', 'SQ_SRC_12_INT', 'SQ_SRC_13_INT', 'SQ_SRC_14_INT', 'SQ_SRC_15_INT', 'SQ_SRC_16_INT', 'SQ_SRC_17_INT', 'SQ_SRC_18_INT', 'SQ_SRC_19_INT', 'SQ_SRC_1_INT', 'SQ_SRC_2', 'SQ_SRC_20_INT', 'SQ_SRC_21_INT', 'SQ_SRC_22_INT', 'SQ_SRC_23_INT', 'SQ_SRC_24_INT', 'SQ_SRC_25_INT', 'SQ_SRC_26_INT', 'SQ_SRC_27_INT', 'SQ_SRC_28_INT', 'SQ_SRC_29_INT', 'SQ_SRC_2_INT', 'SQ_SRC_30_INT', 'SQ_SRC_31_INT', 'SQ_SRC_32_INT', 'SQ_SRC_33_INT', 'SQ_SRC_34_INT', 'SQ_SRC_35_INT', 'SQ_SRC_36_INT', 'SQ_SRC_37_INT', 'SQ_SRC_38_INT', 'SQ_SRC_39_INT', 'SQ_SRC_3_INT', 'SQ_SRC_4', 'SQ_SRC_40_INT', 'SQ_SRC_41_INT', 'SQ_SRC_42_INT', 'SQ_SRC_43_INT', 'SQ_SRC_44_INT', 'SQ_SRC_45_INT', 'SQ_SRC_46_INT', 'SQ_SRC_47_INT', 'SQ_SRC_48_INT', 'SQ_SRC_49_INT', 'SQ_SRC_4_INT', 'SQ_SRC_50_INT', 'SQ_SRC_51_INT', 'SQ_SRC_52_INT', 'SQ_SRC_53_INT', 'SQ_SRC_54_INT', 'SQ_SRC_55_INT', 'SQ_SRC_56_INT', 'SQ_SRC_57_INT', 'SQ_SRC_58_INT', 'SQ_SRC_59_INT', 'SQ_SRC_5_INT', 'SQ_SRC_60_INT', 'SQ_SRC_61_INT', 'SQ_SRC_62_INT', 'SQ_SRC_63_INT', 'SQ_SRC_64_INT', 'SQ_SRC_6_INT', 'SQ_SRC_7_INT', 'SQ_SRC_8_INT', 'SQ_SRC_9_INT', 'SQ_SRC_DPP', 'SQ_SRC_EXECZ', 'SQ_SRC_INV_2PI', 'SQ_SRC_LDS_DIRECT', 'SQ_SRC_LITERAL', 'SQ_SRC_M_0_5', 'SQ_SRC_M_1', 'SQ_SRC_M_10_INT', 'SQ_SRC_M_11_INT', 'SQ_SRC_M_12_INT', 'SQ_SRC_M_13_INT', 'SQ_SRC_M_14_INT', 'SQ_SRC_M_15_INT', 'SQ_SRC_M_16_INT', 'SQ_SRC_M_1_INT', 'SQ_SRC_M_2', 'SQ_SRC_M_2_INT', 'SQ_SRC_M_3_INT', 'SQ_SRC_M_4', 'SQ_SRC_M_4_INT', 'SQ_SRC_M_5_INT', 'SQ_SRC_M_6_INT', 'SQ_SRC_M_7_INT', 'SQ_SRC_M_8_INT', 'SQ_SRC_M_9_INT', 'SQ_SRC_POPS_EXITING_WAVE_ID', 'SQ_SRC_PRIVATE_BASE', 'SQ_SRC_PRIVATE_LIMIT', 'SQ_SRC_SCC', 'SQ_SRC_SDWA', 'SQ_SRC_SHARED_BASE', 'SQ_SRC_SHARED_LIMIT', 'SQ_SRC_VCCZ', 'SQ_SRC_VGPR0', 'SQ_SRC_VGPR_BIT', 'SQ_SYSMSG_OP_ECC_ERR_INTERRUPT', 'SQ_SYSMSG_OP_HOST_TRAP_ACK', 'SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT', 'SQ_SYSMSG_OP_MEMVIOL_INTERRUPT', 'SQ_SYSMSG_OP_REG_RD', 'SQ_SYSMSG_OP_TTRACE_PC', 'SQ_S_ABSDIFF_I32', 'SQ_S_ABS_I32', 'SQ_S_ADDC_U32', 'SQ_S_ADDK_I32', 'SQ_S_ADD_I32', 'SQ_S_ADD_U32', 'SQ_S_ANDN1_SAVEEXEC_B64', 'SQ_S_ANDN1_WREXEC_B64', 'SQ_S_ANDN2_B32', 'SQ_S_ANDN2_B64', 'SQ_S_ANDN2_SAVEEXEC_B64', 'SQ_S_ANDN2_WREXEC_B64', 'SQ_S_AND_B32', 'SQ_S_AND_B64', 'SQ_S_AND_SAVEEXEC_B64', 'SQ_S_ASHR_I32', 'SQ_S_ASHR_I64', 'SQ_S_ATC_PROBE', 'SQ_S_ATC_PROBE_BUFFER', 'SQ_S_ATOMIC_ADD', 'SQ_S_ATOMIC_ADD_X2', 'SQ_S_ATOMIC_AND', 'SQ_S_ATOMIC_AND_X2', 'SQ_S_ATOMIC_CMPSWAP', 'SQ_S_ATOMIC_CMPSWAP_X2', 'SQ_S_ATOMIC_DEC', 'SQ_S_ATOMIC_DEC_X2', 'SQ_S_ATOMIC_INC', 'SQ_S_ATOMIC_INC_X2', 'SQ_S_ATOMIC_OR', 'SQ_S_ATOMIC_OR_X2', 'SQ_S_ATOMIC_SMAX', 'SQ_S_ATOMIC_SMAX_X2', 'SQ_S_ATOMIC_SMIN', 'SQ_S_ATOMIC_SMIN_X2', 'SQ_S_ATOMIC_SUB', 'SQ_S_ATOMIC_SUB_X2', 'SQ_S_ATOMIC_SWAP', 'SQ_S_ATOMIC_SWAP_X2', 'SQ_S_ATOMIC_UMAX', 'SQ_S_ATOMIC_UMAX_X2', 'SQ_S_ATOMIC_UMIN', 'SQ_S_ATOMIC_UMIN_X2', 'SQ_S_ATOMIC_XOR', 'SQ_S_ATOMIC_XOR_X2', 'SQ_S_BARRIER', 'SQ_S_BCNT0_I32_B32', 'SQ_S_BCNT0_I32_B64', 'SQ_S_BCNT1_I32_B32', 'SQ_S_BCNT1_I32_B64', 'SQ_S_BFE_I32', 'SQ_S_BFE_I64', 'SQ_S_BFE_U32', 'SQ_S_BFE_U64', 'SQ_S_BFM_B32', 'SQ_S_BFM_B64', 'SQ_S_BITCMP0_B32', 'SQ_S_BITCMP0_B64', 'SQ_S_BITCMP1_B32', 'SQ_S_BITCMP1_B64', 'SQ_S_BITREPLICATE_B64_B32', 'SQ_S_BITSET0_B32', 'SQ_S_BITSET0_B64', 'SQ_S_BITSET1_B32', 'SQ_S_BITSET1_B64', 'SQ_S_BRANCH', 'SQ_S_BREV_B32', 'SQ_S_BREV_B64', 'SQ_S_BUFFER_ATOMIC_ADD', 'SQ_S_BUFFER_ATOMIC_ADD_X2', 'SQ_S_BUFFER_ATOMIC_AND', 'SQ_S_BUFFER_ATOMIC_AND_X2', 'SQ_S_BUFFER_ATOMIC_CMPSWAP', 'SQ_S_BUFFER_ATOMIC_CMPSWAP_X2', 'SQ_S_BUFFER_ATOMIC_DEC', 'SQ_S_BUFFER_ATOMIC_DEC_X2', 'SQ_S_BUFFER_ATOMIC_INC', 'SQ_S_BUFFER_ATOMIC_INC_X2', 'SQ_S_BUFFER_ATOMIC_OR', 'SQ_S_BUFFER_ATOMIC_OR_X2', 'SQ_S_BUFFER_ATOMIC_SMAX', 'SQ_S_BUFFER_ATOMIC_SMAX_X2', 'SQ_S_BUFFER_ATOMIC_SMIN', 'SQ_S_BUFFER_ATOMIC_SMIN_X2', 'SQ_S_BUFFER_ATOMIC_SUB', 'SQ_S_BUFFER_ATOMIC_SUB_X2', 'SQ_S_BUFFER_ATOMIC_SWAP', 'SQ_S_BUFFER_ATOMIC_SWAP_X2', 'SQ_S_BUFFER_ATOMIC_UMAX', 'SQ_S_BUFFER_ATOMIC_UMAX_X2', 'SQ_S_BUFFER_ATOMIC_UMIN', 'SQ_S_BUFFER_ATOMIC_UMIN_X2', 'SQ_S_BUFFER_ATOMIC_XOR', 'SQ_S_BUFFER_ATOMIC_XOR_X2', 'SQ_S_BUFFER_LOAD_DWORD', 'SQ_S_BUFFER_LOAD_DWORDX16', 'SQ_S_BUFFER_LOAD_DWORDX2', 'SQ_S_BUFFER_LOAD_DWORDX4', 'SQ_S_BUFFER_LOAD_DWORDX8', 'SQ_S_BUFFER_STORE_DWORD', 'SQ_S_BUFFER_STORE_DWORDX2', 'SQ_S_BUFFER_STORE_DWORDX4', 'SQ_S_CALL_B64', 'SQ_S_CBRANCH_CDBGSYS', 'SQ_S_CBRANCH_CDBGSYS_AND_USER', 'SQ_S_CBRANCH_CDBGSYS_OR_USER', 'SQ_S_CBRANCH_CDBGUSER', 'SQ_S_CBRANCH_EXECNZ', 'SQ_S_CBRANCH_EXECZ', 'SQ_S_CBRANCH_G_FORK', 'SQ_S_CBRANCH_I_FORK', 'SQ_S_CBRANCH_JOIN', 'SQ_S_CBRANCH_SCC0', 'SQ_S_CBRANCH_SCC1', 'SQ_S_CBRANCH_VCCNZ', 'SQ_S_CBRANCH_VCCZ', 'SQ_S_CMOVK_I32', 'SQ_S_CMOV_B32', 'SQ_S_CMOV_B64', 'SQ_S_CMPK_EQ_I32', 'SQ_S_CMPK_EQ_U32', 'SQ_S_CMPK_GE_I32', 'SQ_S_CMPK_GE_U32', 'SQ_S_CMPK_GT_I32', 'SQ_S_CMPK_GT_U32', 'SQ_S_CMPK_LE_I32', 'SQ_S_CMPK_LE_U32', 'SQ_S_CMPK_LG_I32', 'SQ_S_CMPK_LG_U32', 'SQ_S_CMPK_LT_I32', 'SQ_S_CMPK_LT_U32', 'SQ_S_CMP_EQ_I32', 'SQ_S_CMP_EQ_U32', 'SQ_S_CMP_EQ_U64', 'SQ_S_CMP_GE_I32', 'SQ_S_CMP_GE_U32', 'SQ_S_CMP_GT_I32', 'SQ_S_CMP_GT_U32', 'SQ_S_CMP_LE_I32', 'SQ_S_CMP_LE_U32', 'SQ_S_CMP_LG_I32', 'SQ_S_CMP_LG_U32', 'SQ_S_CMP_LG_U64', 'SQ_S_CMP_LT_I32', 'SQ_S_CMP_LT_U32', 'SQ_S_CSELECT_B32', 'SQ_S_CSELECT_B64', 'SQ_S_DCACHE_INV', 'SQ_S_DCACHE_INV_VOL', 'SQ_S_DCACHE_WB', 'SQ_S_DCACHE_WB_VOL', 'SQ_S_DECPERFLEVEL', 'SQ_S_ENDPGM', 'SQ_S_ENDPGM_ORDERED_PS_DONE', 'SQ_S_ENDPGM_SAVED', 'SQ_S_FF0_I32_B32', 'SQ_S_FF0_I32_B64', 'SQ_S_FF1_I32_B32', 'SQ_S_FF1_I32_B64', 'SQ_S_FLBIT_I32', 'SQ_S_FLBIT_I32_B32', 'SQ_S_FLBIT_I32_B64', 'SQ_S_FLBIT_I32_I64', 'SQ_S_GETPC_B64', 'SQ_S_GETREG_B32', 'SQ_S_GETREG_REGRD_B32', 'SQ_S_ICACHE_INV', 'SQ_S_INCPERFLEVEL', 'SQ_S_LOAD_DWORD', 'SQ_S_LOAD_DWORDX16', 'SQ_S_LOAD_DWORDX2', 'SQ_S_LOAD_DWORDX4', 'SQ_S_LOAD_DWORDX8', 'SQ_S_LSHL1_ADD_U32', 'SQ_S_LSHL2_ADD_U32', 'SQ_S_LSHL3_ADD_U32', 'SQ_S_LSHL4_ADD_U32', 'SQ_S_LSHL_B32', 'SQ_S_LSHL_B64', 'SQ_S_LSHR_B32', 'SQ_S_LSHR_B64', 'SQ_S_MAX_I32', 'SQ_S_MAX_U32', 'SQ_S_MEMREALTIME', 'SQ_S_MEMTIME', 'SQ_S_MIN_I32', 'SQ_S_MIN_U32', 'SQ_S_MOVK_I32', 'SQ_S_MOVRELD_B32', 'SQ_S_MOVRELD_B64', 'SQ_S_MOVRELS_B32', 'SQ_S_MOVRELS_B64', 'SQ_S_MOV_B32', 'SQ_S_MOV_B64', 'SQ_S_MOV_FED_B32', 'SQ_S_MOV_REGRD_B32', 'SQ_S_MULK_I32', 'SQ_S_MUL_HI_I32', 'SQ_S_MUL_HI_U32', 'SQ_S_MUL_I32', 'SQ_S_NAND_B32', 'SQ_S_NAND_B64', 'SQ_S_NAND_SAVEEXEC_B64', 'SQ_S_NOP', 'SQ_S_NOR_B32', 'SQ_S_NOR_B64', 'SQ_S_NOR_SAVEEXEC_B64', 'SQ_S_NOT_B32', 'SQ_S_NOT_B64', 'SQ_S_ORN1_SAVEEXEC_B64', 'SQ_S_ORN2_B32', 'SQ_S_ORN2_B64', 'SQ_S_ORN2_SAVEEXEC_B64', 'SQ_S_OR_B32', 'SQ_S_OR_B64', 'SQ_S_OR_SAVEEXEC_B64', 'SQ_S_PACK_HH_B32_B16', 'SQ_S_PACK_LH_B32_B16', 'SQ_S_PACK_LL_B32_B16', 'SQ_S_QUADMASK_B32', 'SQ_S_QUADMASK_B64', 'SQ_S_RFE_B64', 'SQ_S_RFE_RESTORE_B64', 'SQ_S_SCRATCH_LOAD_DWORD', 'SQ_S_SCRATCH_LOAD_DWORDX2', 'SQ_S_SCRATCH_LOAD_DWORDX4', 'SQ_S_SCRATCH_STORE_DWORD', 'SQ_S_SCRATCH_STORE_DWORDX2', 'SQ_S_SCRATCH_STORE_DWORDX4', 'SQ_S_SENDMSG', 'SQ_S_SENDMSGHALT', 'SQ_S_SETHALT', 'SQ_S_SETKILL', 'SQ_S_SETPC_B64', 'SQ_S_SETPRIO', 'SQ_S_SETREG_B32', 'SQ_S_SETREG_IMM32_B32', 'SQ_S_SETVSKIP', 'SQ_S_SET_GPR_IDX_IDX', 'SQ_S_SET_GPR_IDX_MODE', 'SQ_S_SET_GPR_IDX_OFF', 'SQ_S_SET_GPR_IDX_ON', 'SQ_S_SEXT_I32_I16', 'SQ_S_SEXT_I32_I8', 'SQ_S_SLEEP', 'SQ_S_STORE_DWORD', 'SQ_S_STORE_DWORDX2', 'SQ_S_STORE_DWORDX4', 'SQ_S_SUBB_U32', 'SQ_S_SUB_I32', 'SQ_S_SUB_U32', 'SQ_S_SWAPPC_B64', 'SQ_S_TRAP', 'SQ_S_TTRACEDATA', 'SQ_S_WAITCNT', 'SQ_S_WAKEUP', 'SQ_S_WQM_B32', 'SQ_S_WQM_B64', 'SQ_S_XNOR_B32', 'SQ_S_XNOR_B64', 'SQ_S_XNOR_SAVEEXEC_B64', 'SQ_S_XOR_B32', 'SQ_S_XOR_B64', 'SQ_S_XOR_SAVEEXEC_B64', 'SQ_T', 'SQ_TBUFFER_LOAD_FORMAT_D16_X', 'SQ_TBUFFER_LOAD_FORMAT_D16_XY', 'SQ_TBUFFER_LOAD_FORMAT_D16_XYZ', 'SQ_TBUFFER_LOAD_FORMAT_D16_XYZW', 'SQ_TBUFFER_LOAD_FORMAT_X', 'SQ_TBUFFER_LOAD_FORMAT_XY', 'SQ_TBUFFER_LOAD_FORMAT_XYZ', 'SQ_TBUFFER_LOAD_FORMAT_XYZW', 'SQ_TBUFFER_STORE_FORMAT_D16_X', 'SQ_TBUFFER_STORE_FORMAT_D16_XY', 'SQ_TBUFFER_STORE_FORMAT_D16_XYZ', 'SQ_TBUFFER_STORE_FORMAT_D16_XYZW', 'SQ_TBUFFER_STORE_FORMAT_X', 'SQ_TBUFFER_STORE_FORMAT_XY', 'SQ_TBUFFER_STORE_FORMAT_XYZ', 'SQ_TBUFFER_STORE_FORMAT_XYZW', 'SQ_TEX_ANISO_RATIO', 'SQ_TEX_ANISO_RATIO_1', 'SQ_TEX_ANISO_RATIO_16', 'SQ_TEX_ANISO_RATIO_2', 'SQ_TEX_ANISO_RATIO_4', 'SQ_TEX_ANISO_RATIO_8', 'SQ_TEX_BORDER_COLOR', 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', 'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', 'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER', 'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE', 'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL', 'SQ_TEX_DEPTH_COMPARE_GREATER', 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS', 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER', 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER', 'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE', 'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', 'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER', 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', 'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER', 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT', 'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT', 'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR', 'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', 'SQ_THREAD_TRACE_CAPTURE_MODE', 'SQ_THREAD_TRACE_CAPTURE_MODE_ALL', 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT', 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL', 'SQ_THREAD_TRACE_INST_TYPE', 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL', 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS', 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS', 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX', 'SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT', 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD', 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY', 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR', 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY', 'SQ_THREAD_TRACE_INST_TYPE_JUMP', 'SQ_THREAD_TRACE_INST_TYPE_LDS', 'SQ_THREAD_TRACE_INST_TYPE_NEXT', 'SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG', 'SQ_THREAD_TRACE_INST_TYPE_PC', 'SQ_THREAD_TRACE_INST_TYPE_SALU_32', 'SQ_THREAD_TRACE_INST_TYPE_SALU_64', 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD', 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY', 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR', 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY', 'SQ_THREAD_TRACE_INST_TYPE_VALU_32', 'SQ_THREAD_TRACE_INST_TYPE_VALU_64', 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD', 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY', 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR', 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY', 'SQ_THREAD_TRACE_ISSUE', 'SQ_THREAD_TRACE_ISSUE_IMMED', 'SQ_THREAD_TRACE_ISSUE_INST', 'SQ_THREAD_TRACE_ISSUE_MASK', 'SQ_THREAD_TRACE_ISSUE_MASK_ALL', 'SQ_THREAD_TRACE_ISSUE_MASK_IMMED', 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED', 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED', 'SQ_THREAD_TRACE_ISSUE_NULL', 'SQ_THREAD_TRACE_ISSUE_STALL', 'SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST', 'SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX', 'SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN', 'SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC', 'SQ_THREAD_TRACE_MISC_TOKEN_TIME', 'SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET', 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN', 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END', 'SQ_THREAD_TRACE_MISC_TOKEN_TYPE', 'SQ_THREAD_TRACE_MODE_OFF', 'SQ_THREAD_TRACE_MODE_ON', 'SQ_THREAD_TRACE_MODE_SEL', 'SQ_THREAD_TRACE_REG_OP', 'SQ_THREAD_TRACE_REG_OP_READ', 'SQ_THREAD_TRACE_REG_OP_WRITE', 'SQ_THREAD_TRACE_REG_TYPE', 'SQ_THREAD_TRACE_REG_TYPE_DISPATCH', 'SQ_THREAD_TRACE_REG_TYPE_DRAW', 'SQ_THREAD_TRACE_REG_TYPE_EVENT', 'SQ_THREAD_TRACE_REG_TYPE_GFXDEC', 'SQ_THREAD_TRACE_REG_TYPE_MARKER', 'SQ_THREAD_TRACE_REG_TYPE_OTHER', 'SQ_THREAD_TRACE_REG_TYPE_SHDEC', 'SQ_THREAD_TRACE_REG_TYPE_USERDATA', 'SQ_THREAD_TRACE_TIME_UNIT', 'SQ_THREAD_TRACE_TOKEN_EVENT', 'SQ_THREAD_TRACE_TOKEN_EVENT_CS', 'SQ_THREAD_TRACE_TOKEN_EVENT_GFX1', 'SQ_THREAD_TRACE_TOKEN_INST', 'SQ_THREAD_TRACE_TOKEN_INST_PC', 'SQ_THREAD_TRACE_TOKEN_INST_USERDATA', 'SQ_THREAD_TRACE_TOKEN_ISSUE', 'SQ_THREAD_TRACE_TOKEN_MISC', 'SQ_THREAD_TRACE_TOKEN_PERF', 'SQ_THREAD_TRACE_TOKEN_REG', 'SQ_THREAD_TRACE_TOKEN_REG_CS', 'SQ_THREAD_TRACE_TOKEN_REG_CSPRIV', 'SQ_THREAD_TRACE_TOKEN_TIMESTAMP', 'SQ_THREAD_TRACE_TOKEN_TYPE', 'SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC', 'SQ_THREAD_TRACE_TOKEN_WAVE_END', 'SQ_THREAD_TRACE_TOKEN_WAVE_START', 'SQ_THREAD_TRACE_VM_ID_MASK', 'SQ_THREAD_TRACE_VM_ID_MASK_ALL', 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE', 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL', 'SQ_THREAD_TRACE_WAVE_MASK', 'SQ_THREAD_TRACE_WAVE_MASK_ALL', 'SQ_THREAD_TRACE_WAVE_MASK_NONE', 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX', 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE', 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC', 'SQ_TRU', 'SQ_TTMP0', 'SQ_TTMP1', 'SQ_TTMP10', 'SQ_TTMP11', 'SQ_TTMP12', 'SQ_TTMP13', 'SQ_TTMP14', 'SQ_TTMP15', 'SQ_TTMP2', 'SQ_TTMP3', 'SQ_TTMP4', 'SQ_TTMP5', 'SQ_TTMP6', 'SQ_TTMP7', 'SQ_TTMP8', 'SQ_TTMP9', 'SQ_U', 'SQ_VCC_ALL', 'SQ_VCC_HI', 'SQ_VCC_LO', 'SQ_VGPR0', 'SQ_V_ADD3_U32', 'SQ_V_ADDC_CO_U32', 'SQ_V_ADD_CO_U32', 'SQ_V_ADD_F16', 'SQ_V_ADD_F32', 'SQ_V_ADD_F64', 'SQ_V_ADD_I16', 'SQ_V_ADD_I32', 'SQ_V_ADD_LSHL_U32', 'SQ_V_ADD_U16', 'SQ_V_ADD_U32', 'SQ_V_ALIGNBIT_B32', 'SQ_V_ALIGNBYTE_B32', 'SQ_V_AND_B32', 'SQ_V_AND_OR_B32', 'SQ_V_ASHRREV_I16', 'SQ_V_ASHRREV_I32', 'SQ_V_ASHRREV_I64', 'SQ_V_BCNT_U32_B32', 'SQ_V_BFE_I32', 'SQ_V_BFE_U32', 'SQ_V_BFI_B32', 'SQ_V_BFM_B32', 'SQ_V_BFREV_B32', 'SQ_V_CEIL_F16', 'SQ_V_CEIL_F32', 'SQ_V_CEIL_F64', 'SQ_V_CLREXCP', 'SQ_V_CMPX_CLASS_F16', 'SQ_V_CMPX_CLASS_F32', 'SQ_V_CMPX_CLASS_F64', 'SQ_V_CMPX_EQ_F16', 'SQ_V_CMPX_EQ_F32', 'SQ_V_CMPX_EQ_F64', 'SQ_V_CMPX_EQ_I16', 'SQ_V_CMPX_EQ_I32', 'SQ_V_CMPX_EQ_I64', 'SQ_V_CMPX_EQ_U16', 'SQ_V_CMPX_EQ_U32', 'SQ_V_CMPX_EQ_U64', 'SQ_V_CMPX_F_F16', 'SQ_V_CMPX_F_F32', 'SQ_V_CMPX_F_F64', 'SQ_V_CMPX_F_I16', 'SQ_V_CMPX_F_I32', 'SQ_V_CMPX_F_I64', 'SQ_V_CMPX_F_U16', 'SQ_V_CMPX_F_U32', 'SQ_V_CMPX_F_U64', 'SQ_V_CMPX_GE_F16', 'SQ_V_CMPX_GE_F32', 'SQ_V_CMPX_GE_F64', 'SQ_V_CMPX_GE_I16', 'SQ_V_CMPX_GE_I32', 'SQ_V_CMPX_GE_I64', 'SQ_V_CMPX_GE_U16', 'SQ_V_CMPX_GE_U32', 'SQ_V_CMPX_GE_U64', 'SQ_V_CMPX_GT_F16', 'SQ_V_CMPX_GT_F32', 'SQ_V_CMPX_GT_F64', 'SQ_V_CMPX_GT_I16', 'SQ_V_CMPX_GT_I32', 'SQ_V_CMPX_GT_I64', 'SQ_V_CMPX_GT_U16', 'SQ_V_CMPX_GT_U32', 'SQ_V_CMPX_GT_U64', 'SQ_V_CMPX_LE_F16', 'SQ_V_CMPX_LE_F32', 'SQ_V_CMPX_LE_F64', 'SQ_V_CMPX_LE_I16', 'SQ_V_CMPX_LE_I32', 'SQ_V_CMPX_LE_I64', 'SQ_V_CMPX_LE_U16', 'SQ_V_CMPX_LE_U32', 'SQ_V_CMPX_LE_U64', 'SQ_V_CMPX_LG_F16', 'SQ_V_CMPX_LG_F32', 'SQ_V_CMPX_LG_F64', 'SQ_V_CMPX_LT_F16', 'SQ_V_CMPX_LT_F32', 'SQ_V_CMPX_LT_F64', 'SQ_V_CMPX_LT_I16', 'SQ_V_CMPX_LT_I32', 'SQ_V_CMPX_LT_I64', 'SQ_V_CMPX_LT_U16', 'SQ_V_CMPX_LT_U32', 'SQ_V_CMPX_LT_U64', 'SQ_V_CMPX_NEQ_F16', 'SQ_V_CMPX_NEQ_F32', 'SQ_V_CMPX_NEQ_F64', 'SQ_V_CMPX_NE_I16', 'SQ_V_CMPX_NE_I32', 'SQ_V_CMPX_NE_I64', 'SQ_V_CMPX_NE_U16', 'SQ_V_CMPX_NE_U32', 'SQ_V_CMPX_NE_U64', 'SQ_V_CMPX_NGE_F16', 'SQ_V_CMPX_NGE_F32', 'SQ_V_CMPX_NGE_F64', 'SQ_V_CMPX_NGT_F16', 'SQ_V_CMPX_NGT_F32', 'SQ_V_CMPX_NGT_F64', 'SQ_V_CMPX_NLE_F16', 'SQ_V_CMPX_NLE_F32', 'SQ_V_CMPX_NLE_F64', 'SQ_V_CMPX_NLG_F16', 'SQ_V_CMPX_NLG_F32', 'SQ_V_CMPX_NLG_F64', 'SQ_V_CMPX_NLT_F16', 'SQ_V_CMPX_NLT_F32', 'SQ_V_CMPX_NLT_F64', 'SQ_V_CMPX_O_F16', 'SQ_V_CMPX_O_F32', 'SQ_V_CMPX_O_F64', 'SQ_V_CMPX_TRU_F16', 'SQ_V_CMPX_TRU_F32', 'SQ_V_CMPX_TRU_F64', 'SQ_V_CMPX_T_I16', 'SQ_V_CMPX_T_I32', 'SQ_V_CMPX_T_I64', 'SQ_V_CMPX_T_U16', 'SQ_V_CMPX_T_U32', 'SQ_V_CMPX_T_U64', 'SQ_V_CMPX_U_F16', 'SQ_V_CMPX_U_F32', 'SQ_V_CMPX_U_F64', 'SQ_V_CMP_CLASS_F16', 'SQ_V_CMP_CLASS_F32', 'SQ_V_CMP_CLASS_F64', 'SQ_V_CMP_EQ_F16', 'SQ_V_CMP_EQ_F32', 'SQ_V_CMP_EQ_F64', 'SQ_V_CMP_EQ_I16', 'SQ_V_CMP_EQ_I32', 'SQ_V_CMP_EQ_I64', 'SQ_V_CMP_EQ_U16', 'SQ_V_CMP_EQ_U32', 'SQ_V_CMP_EQ_U64', 'SQ_V_CMP_F_F16', 'SQ_V_CMP_F_F32', 'SQ_V_CMP_F_F64', 'SQ_V_CMP_F_I16', 'SQ_V_CMP_F_I32', 'SQ_V_CMP_F_I64', 'SQ_V_CMP_F_U16', 'SQ_V_CMP_F_U32', 'SQ_V_CMP_F_U64', 'SQ_V_CMP_GE_F16', 'SQ_V_CMP_GE_F32', 'SQ_V_CMP_GE_F64', 'SQ_V_CMP_GE_I16', 'SQ_V_CMP_GE_I32', 'SQ_V_CMP_GE_I64', 'SQ_V_CMP_GE_U16', 'SQ_V_CMP_GE_U32', 'SQ_V_CMP_GE_U64', 'SQ_V_CMP_GT_F16', 'SQ_V_CMP_GT_F32', 'SQ_V_CMP_GT_F64', 'SQ_V_CMP_GT_I16', 'SQ_V_CMP_GT_I32', 'SQ_V_CMP_GT_I64', 'SQ_V_CMP_GT_U16', 'SQ_V_CMP_GT_U32', 'SQ_V_CMP_GT_U64', 'SQ_V_CMP_LE_F16', 'SQ_V_CMP_LE_F32', 'SQ_V_CMP_LE_F64', 'SQ_V_CMP_LE_I16', 'SQ_V_CMP_LE_I32', 'SQ_V_CMP_LE_I64', 'SQ_V_CMP_LE_U16', 'SQ_V_CMP_LE_U32', 'SQ_V_CMP_LE_U64', 'SQ_V_CMP_LG_F16', 'SQ_V_CMP_LG_F32', 'SQ_V_CMP_LG_F64', 'SQ_V_CMP_LT_F16', 'SQ_V_CMP_LT_F32', 'SQ_V_CMP_LT_F64', 'SQ_V_CMP_LT_I16', 'SQ_V_CMP_LT_I32', 'SQ_V_CMP_LT_I64', 'SQ_V_CMP_LT_U16', 'SQ_V_CMP_LT_U32', 'SQ_V_CMP_LT_U64', 'SQ_V_CMP_NEQ_F16', 'SQ_V_CMP_NEQ_F32', 'SQ_V_CMP_NEQ_F64', 'SQ_V_CMP_NE_I16', 'SQ_V_CMP_NE_I32', 'SQ_V_CMP_NE_I64', 'SQ_V_CMP_NE_U16', 'SQ_V_CMP_NE_U32', 'SQ_V_CMP_NE_U64', 'SQ_V_CMP_NGE_F16', 'SQ_V_CMP_NGE_F32', 'SQ_V_CMP_NGE_F64', 'SQ_V_CMP_NGT_F16', 'SQ_V_CMP_NGT_F32', 'SQ_V_CMP_NGT_F64', 'SQ_V_CMP_NLE_F16', 'SQ_V_CMP_NLE_F32', 'SQ_V_CMP_NLE_F64', 'SQ_V_CMP_NLG_F16', 'SQ_V_CMP_NLG_F32', 'SQ_V_CMP_NLG_F64', 'SQ_V_CMP_NLT_F16', 'SQ_V_CMP_NLT_F32', 'SQ_V_CMP_NLT_F64', 'SQ_V_CMP_O_F16', 'SQ_V_CMP_O_F32', 'SQ_V_CMP_O_F64', 'SQ_V_CMP_TRU_F16', 'SQ_V_CMP_TRU_F32', 'SQ_V_CMP_TRU_F64', 'SQ_V_CMP_T_I16', 'SQ_V_CMP_T_I32', 'SQ_V_CMP_T_I64', 'SQ_V_CMP_T_U16', 'SQ_V_CMP_T_U32', 'SQ_V_CMP_T_U64', 'SQ_V_CMP_U_F16', 'SQ_V_CMP_U_F32', 'SQ_V_CMP_U_F64', 'SQ_V_CNDMASK_B32', 'SQ_V_COS_F16', 'SQ_V_COS_F32', 'SQ_V_CUBEID_F32', 'SQ_V_CUBEMA_F32', 'SQ_V_CUBESC_F32', 'SQ_V_CUBETC_F32', 'SQ_V_CVT_F16_F32', 'SQ_V_CVT_F16_I16', 'SQ_V_CVT_F16_U16', 'SQ_V_CVT_F32_F16', 'SQ_V_CVT_F32_F64', 'SQ_V_CVT_F32_I32', 'SQ_V_CVT_F32_U32', 'SQ_V_CVT_F32_UBYTE0', 'SQ_V_CVT_F32_UBYTE1', 'SQ_V_CVT_F32_UBYTE2', 'SQ_V_CVT_F32_UBYTE3', 'SQ_V_CVT_F64_F32', 'SQ_V_CVT_F64_I32', 'SQ_V_CVT_F64_U32', 'SQ_V_CVT_FLR_I32_F32', 'SQ_V_CVT_I16_F16', 'SQ_V_CVT_I32_F32', 'SQ_V_CVT_I32_F64', 'SQ_V_CVT_NORM_I16_F16', 'SQ_V_CVT_NORM_U16_F16', 'SQ_V_CVT_OFF_F32_I4', 'SQ_V_CVT_PKACCUM_U8_F32', 'SQ_V_CVT_PKNORM_I16_F16', 'SQ_V_CVT_PKNORM_I16_F32', 'SQ_V_CVT_PKNORM_U16_F16', 'SQ_V_CVT_PKNORM_U16_F32', 'SQ_V_CVT_PKRTZ_F16_F32', 'SQ_V_CVT_PK_I16_I32', 'SQ_V_CVT_PK_U16_U32', 'SQ_V_CVT_PK_U8_F32', 'SQ_V_CVT_RPI_I32_F32', 'SQ_V_CVT_U16_F16', 'SQ_V_CVT_U32_F32', 'SQ_V_CVT_U32_F64', 'SQ_V_DIV_FIXUP_F16', 'SQ_V_DIV_FIXUP_F32', 'SQ_V_DIV_FIXUP_F64', 'SQ_V_DIV_FIXUP_LEGACY_F16', 'SQ_V_DIV_FMAS_F32', 'SQ_V_DIV_FMAS_F64', 'SQ_V_DIV_SCALE_F32', 'SQ_V_DIV_SCALE_F64', 'SQ_V_EXP_F16', 'SQ_V_EXP_F32', 'SQ_V_EXP_LEGACY_F32', 'SQ_V_FFBH_I32', 'SQ_V_FFBH_U32', 'SQ_V_FFBL_B32', 'SQ_V_FLOOR_F16', 'SQ_V_FLOOR_F32', 'SQ_V_FLOOR_F64', 'SQ_V_FMA_F16', 'SQ_V_FMA_F32', 'SQ_V_FMA_F64', 'SQ_V_FMA_LEGACY_F16', 'SQ_V_FRACT_F16', 'SQ_V_FRACT_F32', 'SQ_V_FRACT_F64', 'SQ_V_FREXP_EXP_I16_F16', 'SQ_V_FREXP_EXP_I32_F32', 'SQ_V_FREXP_EXP_I32_F64', 'SQ_V_FREXP_MANT_F16', 'SQ_V_FREXP_MANT_F32', 'SQ_V_FREXP_MANT_F64', 'SQ_V_INTERP_MOV_F32', 'SQ_V_INTERP_P1LL_F16', 'SQ_V_INTERP_P1LV_F16', 'SQ_V_INTERP_P1_F32', 'SQ_V_INTERP_P2_F16', 'SQ_V_INTERP_P2_F32', 'SQ_V_INTERP_P2_LEGACY_F16', 'SQ_V_INTRP_COUNT', 'SQ_V_INTRP_OFFSET', 'SQ_V_LDEXP_F16', 'SQ_V_LDEXP_F32', 'SQ_V_LDEXP_F64', 'SQ_V_LERP_U8', 'SQ_V_LOG_F16', 'SQ_V_LOG_F32', 'SQ_V_LOG_LEGACY_F32', 'SQ_V_LSHLREV_B16', 'SQ_V_LSHLREV_B32', 'SQ_V_LSHLREV_B64', 'SQ_V_LSHL_ADD_U32', 'SQ_V_LSHL_OR_B32', 'SQ_V_LSHRREV_B16', 'SQ_V_LSHRREV_B32', 'SQ_V_LSHRREV_B64', 'SQ_V_MAC_F16', 'SQ_V_MAC_F32', 'SQ_V_MAC_LEGACY_F32', 'SQ_V_MADAK_F16', 'SQ_V_MADAK_F32', 'SQ_V_MADMK_F16', 'SQ_V_MADMK_F32', 'SQ_V_MAD_F16', 'SQ_V_MAD_F32', 'SQ_V_MAD_I16', 'SQ_V_MAD_I32_I16', 'SQ_V_MAD_I32_I24', 'SQ_V_MAD_I64_I32', 'SQ_V_MAD_LEGACY_F16', 'SQ_V_MAD_LEGACY_F32', 'SQ_V_MAD_LEGACY_I16', 'SQ_V_MAD_LEGACY_U16', 'SQ_V_MAD_MIXHI_F16', 'SQ_V_MAD_MIXLO_F16', 'SQ_V_MAD_MIX_F32', 'SQ_V_MAD_U16', 'SQ_V_MAD_U32_U16', 'SQ_V_MAD_U32_U24', 'SQ_V_MAD_U64_U32', 'SQ_V_MAX3_F16', 'SQ_V_MAX3_F32', 'SQ_V_MAX3_I16', 'SQ_V_MAX3_I32', 'SQ_V_MAX3_U16', 'SQ_V_MAX3_U32', 'SQ_V_MAX_F16', 'SQ_V_MAX_F32', 'SQ_V_MAX_F64', 'SQ_V_MAX_I16', 'SQ_V_MAX_I32', 'SQ_V_MAX_U16', 'SQ_V_MAX_U32', 'SQ_V_MBCNT_HI_U32_B32', 'SQ_V_MBCNT_LO_U32_B32', 'SQ_V_MED3_F16', 'SQ_V_MED3_F32', 'SQ_V_MED3_I16', 'SQ_V_MED3_I32', 'SQ_V_MED3_U16', 'SQ_V_MED3_U32', 'SQ_V_MIN3_F16', 'SQ_V_MIN3_F32', 'SQ_V_MIN3_I16', 'SQ_V_MIN3_I32', 'SQ_V_MIN3_U16', 'SQ_V_MIN3_U32', 'SQ_V_MIN_F16', 'SQ_V_MIN_F32', 'SQ_V_MIN_F64', 'SQ_V_MIN_I16', 'SQ_V_MIN_I32', 'SQ_V_MIN_U16', 'SQ_V_MIN_U32', 'SQ_V_MOV_B32', 'SQ_V_MOV_FED_B32', 'SQ_V_MOV_PRSV_B32', 'SQ_V_MQSAD_PK_U16_U8', 'SQ_V_MQSAD_U32_U8', 'SQ_V_MSAD_U8', 'SQ_V_MUL_F16', 'SQ_V_MUL_F32', 'SQ_V_MUL_F64', 'SQ_V_MUL_HI_I32', 'SQ_V_MUL_HI_I32_I24', 'SQ_V_MUL_HI_U32', 'SQ_V_MUL_HI_U32_U24', 'SQ_V_MUL_I32_I24', 'SQ_V_MUL_LEGACY_F32', 'SQ_V_MUL_LO_U16', 'SQ_V_MUL_LO_U32', 'SQ_V_MUL_U32_U24', 'SQ_V_NOP', 'SQ_V_NOT_B32', 'SQ_V_OP1_COUNT', 'SQ_V_OP1_OFFSET', 'SQ_V_OP2_COUNT', 'SQ_V_OP2_OFFSET', 'SQ_V_OP3P_COUNT', 'SQ_V_OP3P_OFFSET', 'SQ_V_OP3_2IN_COUNT', 'SQ_V_OP3_2IN_OFFSET', 'SQ_V_OP3_3IN_COUNT', 'SQ_V_OP3_3IN_OFFSET', 'SQ_V_OP3_INTRP_COUNT', 'SQ_V_OP3_INTRP_OFFSET', 'SQ_V_OPC_COUNT', 'SQ_V_OPC_OFFSET', 'SQ_V_OR3_B32', 'SQ_V_OR_B32', 'SQ_V_PACK_B32_F16', 'SQ_V_PERM_B32', 'SQ_V_PK_ADD_F16', 'SQ_V_PK_ADD_I16', 'SQ_V_PK_ADD_U16', 'SQ_V_PK_ASHRREV_I16', 'SQ_V_PK_LSHLREV_B16', 'SQ_V_PK_LSHRREV_B16', 'SQ_V_PK_MAD_F16', 'SQ_V_PK_MAD_I16', 'SQ_V_PK_MAD_U16', 'SQ_V_PK_MAX_F16', 'SQ_V_PK_MAX_I16', 'SQ_V_PK_MAX_U16', 'SQ_V_PK_MIN_F16', 'SQ_V_PK_MIN_I16', 'SQ_V_PK_MIN_U16', 'SQ_V_PK_MUL_F16', 'SQ_V_PK_MUL_LO_U16', 'SQ_V_PK_SUB_I16', 'SQ_V_PK_SUB_U16', 'SQ_V_QSAD_PK_U16_U8', 'SQ_V_RCP_F16', 'SQ_V_RCP_F32', 'SQ_V_RCP_F64', 'SQ_V_RCP_IFLAG_F32', 'SQ_V_READFIRSTLANE_B32', 'SQ_V_READLANE_B32', 'SQ_V_READLANE_REGRD_B32', 'SQ_V_RNDNE_F16', 'SQ_V_RNDNE_F32', 'SQ_V_RNDNE_F64', 'SQ_V_RSQ_F16', 'SQ_V_RSQ_F32', 'SQ_V_RSQ_F64', 'SQ_V_SAD_HI_U8', 'SQ_V_SAD_U16', 'SQ_V_SAD_U32', 'SQ_V_SAD_U8', 'SQ_V_SAT_PK_U8_I16', 'SQ_V_SIN_F16', 'SQ_V_SIN_F32', 'SQ_V_SQRT_F16', 'SQ_V_SQRT_F32', 'SQ_V_SQRT_F64', 'SQ_V_SUBBREV_CO_U32', 'SQ_V_SUBB_CO_U32', 'SQ_V_SUBREV_CO_U32', 'SQ_V_SUBREV_F16', 'SQ_V_SUBREV_F32', 'SQ_V_SUBREV_U16', 'SQ_V_SUBREV_U32', 'SQ_V_SUB_CO_U32', 'SQ_V_SUB_F16', 'SQ_V_SUB_F32', 'SQ_V_SUB_I16', 'SQ_V_SUB_I32', 'SQ_V_SUB_U16', 'SQ_V_SUB_U32', 'SQ_V_SWAP_B32', 'SQ_V_TRIG_PREOP_F64', 'SQ_V_TRUNC_F16', 'SQ_V_TRUNC_F32', 'SQ_V_TRUNC_F64', 'SQ_V_WRITELANE_B32', 'SQ_V_WRITELANE_IMM32', 'SQ_V_XAD_U32', 'SQ_V_XOR_B32', 'SQ_WAITCNT_EXP_SHIFT', 'SQ_WAITCNT_EXP_SIZE', 'SQ_WAITCNT_LGKM_SHIFT', 'SQ_WAITCNT_LGKM_SIZE', 'SQ_WAITCNT_VM_SHIFT', 'SQ_WAITCNT_VM_SIZE', 'SQ_WAVE_IB_ECC_CLEAN', 'SQ_WAVE_IB_ECC_ERR_CONTINUE', 'SQ_WAVE_IB_ECC_ERR_HALT', 'SQ_WAVE_IB_ECC_ST', 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', 'SQ_WAVE_TYPE_ES', 'SQ_WAVE_TYPE_GS', 'SQ_WAVE_TYPE_HS', 'SQ_WAVE_TYPE_LS', 'SQ_WAVE_TYPE_PS', 'SQ_WAVE_TYPE_PS0', 'SQ_WAVE_TYPE_PS1', 'SQ_WAVE_TYPE_VS', 'SQ_XLATE_VOP3_TO_VINTRP_COUNT', 'SQ_XLATE_VOP3_TO_VINTRP_OFFSET', 'SQ_XLATE_VOP3_TO_VOP1_COUNT', 'SQ_XLATE_VOP3_TO_VOP1_OFFSET', 'SQ_XLATE_VOP3_TO_VOP2_COUNT', 'SQ_XLATE_VOP3_TO_VOP2_OFFSET', 'SQ_XLATE_VOP3_TO_VOP3P_COUNT', 'SQ_XLATE_VOP3_TO_VOP3P_OFFSET', 'SQ_XLATE_VOP3_TO_VOPC_COUNT', 'SQ_XLATE_VOP3_TO_VOPC_OFFSET', 'SQ_XNACK_MASK_HI', 'SQ_XNACK_MASK_LO', 'STATIC_SCREEN_SMU_INTR', 'STATIC_SCREEN_SMU_INTR_NOOP', 'STENCIL_8', 'STENCIL_ADD_CLAMP', 'STENCIL_ADD_WRAP', 'STENCIL_AND', 'STENCIL_INVALID', 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR', 'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP', 'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP', 'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', 'STREAM_0_SYNCHRONIZATION', 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', 'STREAM_10_SYNCHRONIZATION', 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', 'STREAM_11_SYNCHRONIZATION', 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', 'STREAM_12_SYNCHRONIZATION', 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', 'STREAM_13_SYNCHRONIZATION', 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', 'STREAM_14_SYNCHRONIZATION', 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', 'STREAM_15_SYNCHRONIZATION', 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', 'STREAM_1_SYNCHRONIZATION', 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', 'STREAM_2_SYNCHRONIZATION', 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', 'STREAM_3_SYNCHRONIZATION', 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', 'STREAM_4_SYNCHRONIZATION', 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED', 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED', 'STREAM_5_SYNCHRONIZATION', 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED', 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED', 'STREAM_6_SYNCHRONIZATION', 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', 'STREAM_7_SYNCHRONIZATION', 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', 'STREAM_8_SYNCHRONIZATION', 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', 'STREAM_9_SYNCHRONIZATION', 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', 'STRM_PERFMON_STATE_DISABLE_AND_RESET', 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', 'STRM_PERFMON_STATE_RESERVED_3', 'STRM_PERFMON_STATE_START_COUNTING', 'STRM_PERFMON_STATE_STOP_COUNTING', 'SU_PERFCNT_SEL', 'SWAP_ALT', 'SWAP_ALT_REV', 'SWAP_STD', 'SWAP_STD_REV', 'SWIZZLE_MODE_ENUM', 'SWIZZLE_TYPE_ENUM', 'SW_256B_D', 'SW_256B_R', 'SW_256B_S', 'SW_4KB_D', 'SW_4KB_D_X', 'SW_4KB_R', 'SW_4KB_R_X', 'SW_4KB_S', 'SW_4KB_S_X', 'SW_4KB_Z', 'SW_4KB_Z_X', 'SW_64KB_D', 'SW_64KB_D_X', 'SW_64KB_R', 'SW_64KB_R_X', 'SW_64KB_S', 'SW_64KB_S_X', 'SW_64KB_Z', 'SW_64KB_Z_X', 'SW_D', 'SW_L', 'SW_LINEAR', 'SW_R', 'SW_RESERVED_12', 'SW_RESERVED_13', 'SW_RESERVED_14', 'SW_RESERVED_15', 'SW_RESERVED_16', 'SW_RESERVED_17', 'SW_RESERVED_18', 'SW_RESERVED_19', 'SW_S', 'SW_VAR_D', 'SW_VAR_D_X', 'SW_VAR_R', 'SW_VAR_R_X', 'SW_VAR_S', 'SW_VAR_S_X', 'SW_VAR_Z', 'SW_VAR_Z_X', 'SW_Z', 'SX_BLEND_OPT', 'SX_CB_RAT_ACK_REQUEST', 'SX_DOWNCONVERT_FORMAT', 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', 'SX_PERF_SEL_CLOCK', 'SX_PERF_SEL_COL_BUSY', 'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB0_HALF_QUADS', 'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS', 'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC', 'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST', 'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS', 'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS', 'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS', 'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC', 'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST', 'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS', 'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS', 'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS', 'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC', 'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST', 'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS', 'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS', 'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS', 'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC', 'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST', 'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS', 'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS', 'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS', 'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC', 'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST', 'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS', 'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS', 'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS', 'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC', 'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST', 'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS', 'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS', 'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS', 'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC', 'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST', 'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS', 'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS', 'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS', 'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC', 'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST', 'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS', 'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS', 'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL', 'SX_PERF_SEL_DB0_PRED_PIXELS', 'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB1_HALF_QUADS', 'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS', 'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC', 'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST', 'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS', 'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS', 'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS', 'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC', 'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST', 'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS', 'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS', 'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS', 'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC', 'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST', 'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS', 'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS', 'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS', 'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC', 'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST', 'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS', 'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS', 'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS', 'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC', 'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST', 'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS', 'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS', 'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS', 'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC', 'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST', 'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS', 'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS', 'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS', 'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC', 'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST', 'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS', 'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS', 'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS', 'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC', 'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST', 'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS', 'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS', 'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL', 'SX_PERF_SEL_DB1_PRED_PIXELS', 'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB2_HALF_QUADS', 'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS', 'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC', 'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST', 'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS', 'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS', 'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS', 'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC', 'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST', 'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS', 'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS', 'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS', 'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC', 'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST', 'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS', 'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS', 'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS', 'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC', 'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST', 'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS', 'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS', 'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS', 'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC', 'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST', 'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS', 'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS', 'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS', 'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC', 'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST', 'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS', 'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS', 'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS', 'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC', 'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST', 'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS', 'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS', 'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS', 'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC', 'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST', 'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS', 'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS', 'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL', 'SX_PERF_SEL_DB2_PRED_PIXELS', 'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB3_HALF_QUADS', 'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS', 'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC', 'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST', 'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS', 'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS', 'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS', 'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC', 'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST', 'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS', 'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS', 'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS', 'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC', 'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST', 'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS', 'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS', 'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS', 'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC', 'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST', 'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS', 'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS', 'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS', 'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC', 'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST', 'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS', 'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS', 'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS', 'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC', 'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST', 'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS', 'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS', 'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS', 'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC', 'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST', 'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS', 'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS', 'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS', 'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC', 'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST', 'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS', 'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS', 'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL', 'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_GATE_EN1', 'SX_PERF_SEL_GATE_EN2', 'SX_PERF_SEL_GATE_EN3', 'SX_PERF_SEL_GATE_EN4', 'SX_PERF_SEL_PA_IDLE_CYCLES', 'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_REQ', 'SX_PERF_SEL_POS_BUSY', 'SX_PERF_SEL_SH_COLOR_STALL', 'SX_PERF_SEL_SH_COLOR_STARVE', 'SX_PERF_SEL_SH_POS_STALL', 'SX_PERF_SEL_SH_POS_STARVE', 'SX_RT_EXPORT_10_11_11', 'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR', 'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10', 'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4', 'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8', 'SX_RT_EXPORT_NO_CONVERSION', 'SYMCLK_FE_FORCE_EN', 'SYMCLK_FE_FORCE_EN_DISABLE', 'SYMCLK_FE_FORCE_EN_ENABLE', 'SYMCLK_FE_FORCE_SRC', 'SYMCLK_FE_FORCE_SRC_UNIPHYA', 'SYMCLK_FE_FORCE_SRC_UNIPHYB', 'SYMCLK_FE_FORCE_SRC_UNIPHYC', 'SYMCLK_FE_FORCE_SRC_UNIPHYD', 'SYMCLK_FE_FORCE_SRC_UNIPHYE', 'SYMCLK_FE_FORCE_SRC_UNIPHYF', 'SYMCLK_FE_FORCE_SRC_UNIPHYG', 'SYNC_DURATION_128', 'SYNC_DURATION_16', 'SYNC_DURATION_32', 'SYNC_DURATION_64', 'SYNC_RESET_SEL2_VBLANK', 'SYNC_RESET_SEL2_VSYNC', 'SampleSplit', 'SampleSplitBytes', 'ScMap', 'ScXsel', 'ScYsel', 'SeEnable', 'SeMap', 'SePairMap', 'SePairXsel', 'SePairYsel', 'SeXsel', 'SeYsel', 'ShaderEngineTileSize', 'SourceFormat', 'StencilFormat', 'StencilOp', 'SurfaceArray', 'SurfaceEndian', 'SurfaceFormat', 'SurfaceNumber', 'SurfaceSwap', 'SurfaceTiling', 'TA_PERFCOUNT_SEL', 'TA_PERF_SEL_NULL', 'TA_PERF_SEL_RESERVED_28', 'TA_PERF_SEL_RESERVED_29', 'TA_PERF_SEL_RESERVED_41', 'TA_PERF_SEL_RESERVED_42', 'TA_PERF_SEL_RESERVED_43', 'TA_PERF_SEL_addr_stalled_by_tc_cycles', 'TA_PERF_SEL_addr_stalled_by_td_cycles', 'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy', 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', 'TA_PERF_SEL_addresser_stalled_cycles', 'TA_PERF_SEL_aligner_busy', 'TA_PERF_SEL_aligner_cycles', 'TA_PERF_SEL_aniso_10_cycle_quads', 'TA_PERF_SEL_aniso_12_cycle_quads', 'TA_PERF_SEL_aniso_14_cycle_quads', 'TA_PERF_SEL_aniso_16_cycle_quads', 'TA_PERF_SEL_aniso_1_cycle_quads', 'TA_PERF_SEL_aniso_2_cycle_quads', 'TA_PERF_SEL_aniso_4_cycle_quads', 'TA_PERF_SEL_aniso_6_cycle_quads', 'TA_PERF_SEL_aniso_8_cycle_quads', 'TA_PERF_SEL_aniso_gt1_cycle_quads', 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', 'TA_PERF_SEL_aniso_stalled_cycles', 'TA_PERF_SEL_bilin_point_1_cycle_pixels', 'TA_PERF_SEL_buffer_atomic_wavefronts', 'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles', 'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles', 'TA_PERF_SEL_buffer_coalescable_wavefronts', 'TA_PERF_SEL_buffer_coalesced_read_cycles', 'TA_PERF_SEL_buffer_coalesced_write_cycles', 'TA_PERF_SEL_buffer_read_wavefronts', 'TA_PERF_SEL_buffer_total_cycles', 'TA_PERF_SEL_buffer_wavefronts', 'TA_PERF_SEL_buffer_write_wavefronts', 'TA_PERF_SEL_color_1_cycle_pixels', 'TA_PERF_SEL_color_2_cycle_pixels', 'TA_PERF_SEL_color_3_cycle_pixels', 'TA_PERF_SEL_color_4_cycle_pixels', 'TA_PERF_SEL_data_stalled_by_tc_cycles', 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', 'TA_PERF_SEL_deriv_stalled_cycles', 'TA_PERF_SEL_first_xnack_on_phase0', 'TA_PERF_SEL_first_xnack_on_phase1', 'TA_PERF_SEL_first_xnack_on_phase2', 'TA_PERF_SEL_first_xnack_on_phase3', 'TA_PERF_SEL_flat_atomic_wavefronts', 'TA_PERF_SEL_flat_coalesceable_wavefronts', 'TA_PERF_SEL_flat_read_wavefronts', 'TA_PERF_SEL_flat_wavefronts', 'TA_PERF_SEL_flat_write_wavefronts', 'TA_PERF_SEL_gradient_busy', 'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy', 'TA_PERF_SEL_image_atomic_wavefronts', 'TA_PERF_SEL_image_read_wavefronts', 'TA_PERF_SEL_image_total_cycles', 'TA_PERF_SEL_image_wavefronts', 'TA_PERF_SEL_image_write_wavefronts', 'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en', 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en', 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en', 'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en', 'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en', 'TA_PERF_SEL_lod_busy', 'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_pixels', 'TA_PERF_SEL_mip_2_cycle_pixels', 'TA_PERF_SEL_mipmap_invalid_samples', 'TA_PERF_SEL_mipmap_lod_0_samples', 'TA_PERF_SEL_mipmap_lod_10_samples', 'TA_PERF_SEL_mipmap_lod_11_samples', 'TA_PERF_SEL_mipmap_lod_12_samples', 'TA_PERF_SEL_mipmap_lod_13_samples', 'TA_PERF_SEL_mipmap_lod_14_samples', 'TA_PERF_SEL_mipmap_lod_1_samples', 'TA_PERF_SEL_mipmap_lod_2_samples', 'TA_PERF_SEL_mipmap_lod_3_samples', 'TA_PERF_SEL_mipmap_lod_4_samples', 'TA_PERF_SEL_mipmap_lod_5_samples', 'TA_PERF_SEL_mipmap_lod_6_samples', 'TA_PERF_SEL_mipmap_lod_7_samples', 'TA_PERF_SEL_mipmap_lod_8_samples', 'TA_PERF_SEL_mipmap_lod_9_samples', 'TA_PERF_SEL_reg_sclk_vld', 'TA_PERF_SEL_sh_fifo_addr_busy', 'TA_PERF_SEL_sh_fifo_addr_cycles', 'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles', 'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles', 'TA_PERF_SEL_sh_fifo_busy', 'TA_PERF_SEL_sh_fifo_cmd_busy', 'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles', 'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles', 'TA_PERF_SEL_sh_fifo_data_busy', 'TA_PERF_SEL_sh_fifo_data_cycles', 'TA_PERF_SEL_sh_fifo_data_sfifo_busy', 'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles', 'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles', 'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles', 'TA_PERF_SEL_sh_fifo_data_tfifo_busy', 'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles', 'TA_PERF_SEL_sp_ta_addr_cycles', 'TA_PERF_SEL_sp_ta_data_cycles', 'TA_PERF_SEL_sq_ta_cmd_cycles', 'TA_PERF_SEL_ta_busy', 'TA_PERF_SEL_ta_fa_data_state_cycles', 'TA_PERF_SEL_total_wavefronts', 'TA_PERF_SEL_vol_1_cycle_pixels', 'TA_PERF_SEL_vol_2_cycle_pixels', 'TA_PERF_SEL_walker_cycles', 'TA_PERF_SEL_write_path_busy', 'TA_PERF_SEL_write_path_input_cycles', 'TA_PERF_SEL_write_path_output_cycles', 'TA_PERF_SEL_xnack_on_phase0', 'TA_PERF_SEL_xnack_on_phase1', 'TA_PERF_SEL_xnack_on_phase2', 'TA_PERF_SEL_xnack_on_phase3', 'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR', 'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1', 'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3', 'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED', 'TCA_PERF_SEL', 'TCA_PERF_SEL_BUSY', 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0', 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1', 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2', 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3', 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4', 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5', 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6', 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7', 'TCA_PERF_SEL_CROSSBAR_STALL_TCC0', 'TCA_PERF_SEL_CROSSBAR_STALL_TCC1', 'TCA_PERF_SEL_CROSSBAR_STALL_TCC2', 'TCA_PERF_SEL_CROSSBAR_STALL_TCC3', 'TCA_PERF_SEL_CROSSBAR_STALL_TCC4', 'TCA_PERF_SEL_CROSSBAR_STALL_TCC5', 'TCA_PERF_SEL_CROSSBAR_STALL_TCC6', 'TCA_PERF_SEL_CROSSBAR_STALL_TCC7', 'TCA_PERF_SEL_CYCLE', 'TCA_PERF_SEL_FORCED_HOLE_TCC0', 'TCA_PERF_SEL_FORCED_HOLE_TCC1', 'TCA_PERF_SEL_FORCED_HOLE_TCC2', 'TCA_PERF_SEL_FORCED_HOLE_TCC3', 'TCA_PERF_SEL_FORCED_HOLE_TCC4', 'TCA_PERF_SEL_FORCED_HOLE_TCC5', 'TCA_PERF_SEL_FORCED_HOLE_TCC6', 'TCA_PERF_SEL_FORCED_HOLE_TCC7', 'TCA_PERF_SEL_NONE', 'TCA_PERF_SEL_REQ_TCC0', 'TCA_PERF_SEL_REQ_TCC1', 'TCA_PERF_SEL_REQ_TCC2', 'TCA_PERF_SEL_REQ_TCC3', 'TCA_PERF_SEL_REQ_TCC4', 'TCA_PERF_SEL_REQ_TCC5', 'TCA_PERF_SEL_REQ_TCC6', 'TCA_PERF_SEL_REQ_TCC7', 'TCC_CACHE_POLICIES', 'TCC_CACHE_POLICY_LRU', 'TCC_CACHE_POLICY_STREAM', 'TCC_PERF_SEL', 'TCC_PERF_SEL_ALL_TC_OP_INV_EVICT', 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE', 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH', 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', 'TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK', 'TCC_PERF_SEL_ATOMIC', 'TCC_PERF_SEL_BUBBLE', 'TCC_PERF_SEL_BUSY', 'TCC_PERF_SEL_CC_PHYSICAL_REQ', 'TCC_PERF_SEL_CLIENT0_REQ', 'TCC_PERF_SEL_CLIENT100_REQ', 'TCC_PERF_SEL_CLIENT101_REQ', 'TCC_PERF_SEL_CLIENT102_REQ', 'TCC_PERF_SEL_CLIENT103_REQ', 'TCC_PERF_SEL_CLIENT104_REQ', 'TCC_PERF_SEL_CLIENT105_REQ', 'TCC_PERF_SEL_CLIENT106_REQ', 'TCC_PERF_SEL_CLIENT107_REQ', 'TCC_PERF_SEL_CLIENT108_REQ', 'TCC_PERF_SEL_CLIENT109_REQ', 'TCC_PERF_SEL_CLIENT10_REQ', 'TCC_PERF_SEL_CLIENT110_REQ', 'TCC_PERF_SEL_CLIENT111_REQ', 'TCC_PERF_SEL_CLIENT112_REQ', 'TCC_PERF_SEL_CLIENT113_REQ', 'TCC_PERF_SEL_CLIENT114_REQ', 'TCC_PERF_SEL_CLIENT115_REQ', 'TCC_PERF_SEL_CLIENT116_REQ', 'TCC_PERF_SEL_CLIENT117_REQ', 'TCC_PERF_SEL_CLIENT118_REQ', 'TCC_PERF_SEL_CLIENT119_REQ', 'TCC_PERF_SEL_CLIENT11_REQ', 'TCC_PERF_SEL_CLIENT120_REQ', 'TCC_PERF_SEL_CLIENT121_REQ', 'TCC_PERF_SEL_CLIENT122_REQ', 'TCC_PERF_SEL_CLIENT123_REQ', 'TCC_PERF_SEL_CLIENT124_REQ', 'TCC_PERF_SEL_CLIENT125_REQ', 'TCC_PERF_SEL_CLIENT126_REQ', 'TCC_PERF_SEL_CLIENT127_REQ', 'TCC_PERF_SEL_CLIENT12_REQ', 'TCC_PERF_SEL_CLIENT13_REQ', 'TCC_PERF_SEL_CLIENT14_REQ', 'TCC_PERF_SEL_CLIENT15_REQ', 'TCC_PERF_SEL_CLIENT16_REQ', 'TCC_PERF_SEL_CLIENT17_REQ', 'TCC_PERF_SEL_CLIENT18_REQ', 'TCC_PERF_SEL_CLIENT19_REQ', 'TCC_PERF_SEL_CLIENT1_REQ', 'TCC_PERF_SEL_CLIENT20_REQ', 'TCC_PERF_SEL_CLIENT21_REQ', 'TCC_PERF_SEL_CLIENT22_REQ', 'TCC_PERF_SEL_CLIENT23_REQ', 'TCC_PERF_SEL_CLIENT24_REQ', 'TCC_PERF_SEL_CLIENT25_REQ', 'TCC_PERF_SEL_CLIENT26_REQ', 'TCC_PERF_SEL_CLIENT27_REQ', 'TCC_PERF_SEL_CLIENT28_REQ', 'TCC_PERF_SEL_CLIENT29_REQ', 'TCC_PERF_SEL_CLIENT2_REQ', 'TCC_PERF_SEL_CLIENT30_REQ', 'TCC_PERF_SEL_CLIENT31_REQ', 'TCC_PERF_SEL_CLIENT32_REQ', 'TCC_PERF_SEL_CLIENT33_REQ', 'TCC_PERF_SEL_CLIENT34_REQ', 'TCC_PERF_SEL_CLIENT35_REQ', 'TCC_PERF_SEL_CLIENT36_REQ', 'TCC_PERF_SEL_CLIENT37_REQ', 'TCC_PERF_SEL_CLIENT38_REQ', 'TCC_PERF_SEL_CLIENT39_REQ', 'TCC_PERF_SEL_CLIENT3_REQ', 'TCC_PERF_SEL_CLIENT40_REQ', 'TCC_PERF_SEL_CLIENT41_REQ', 'TCC_PERF_SEL_CLIENT42_REQ', 'TCC_PERF_SEL_CLIENT43_REQ', 'TCC_PERF_SEL_CLIENT44_REQ', 'TCC_PERF_SEL_CLIENT45_REQ', 'TCC_PERF_SEL_CLIENT46_REQ', 'TCC_PERF_SEL_CLIENT47_REQ', 'TCC_PERF_SEL_CLIENT48_REQ', 'TCC_PERF_SEL_CLIENT49_REQ', 'TCC_PERF_SEL_CLIENT4_REQ', 'TCC_PERF_SEL_CLIENT50_REQ', 'TCC_PERF_SEL_CLIENT51_REQ', 'TCC_PERF_SEL_CLIENT52_REQ', 'TCC_PERF_SEL_CLIENT53_REQ', 'TCC_PERF_SEL_CLIENT54_REQ', 'TCC_PERF_SEL_CLIENT55_REQ', 'TCC_PERF_SEL_CLIENT56_REQ', 'TCC_PERF_SEL_CLIENT57_REQ', 'TCC_PERF_SEL_CLIENT58_REQ', 'TCC_PERF_SEL_CLIENT59_REQ', 'TCC_PERF_SEL_CLIENT5_REQ', 'TCC_PERF_SEL_CLIENT60_REQ', 'TCC_PERF_SEL_CLIENT61_REQ', 'TCC_PERF_SEL_CLIENT62_REQ', 'TCC_PERF_SEL_CLIENT63_REQ', 'TCC_PERF_SEL_CLIENT64_REQ', 'TCC_PERF_SEL_CLIENT65_REQ', 'TCC_PERF_SEL_CLIENT66_REQ', 'TCC_PERF_SEL_CLIENT67_REQ', 'TCC_PERF_SEL_CLIENT68_REQ', 'TCC_PERF_SEL_CLIENT69_REQ', 'TCC_PERF_SEL_CLIENT6_REQ', 'TCC_PERF_SEL_CLIENT70_REQ', 'TCC_PERF_SEL_CLIENT71_REQ', 'TCC_PERF_SEL_CLIENT72_REQ', 'TCC_PERF_SEL_CLIENT73_REQ', 'TCC_PERF_SEL_CLIENT74_REQ', 'TCC_PERF_SEL_CLIENT75_REQ', 'TCC_PERF_SEL_CLIENT76_REQ', 'TCC_PERF_SEL_CLIENT77_REQ', 'TCC_PERF_SEL_CLIENT78_REQ', 'TCC_PERF_SEL_CLIENT79_REQ', 'TCC_PERF_SEL_CLIENT7_REQ', 'TCC_PERF_SEL_CLIENT80_REQ', 'TCC_PERF_SEL_CLIENT81_REQ', 'TCC_PERF_SEL_CLIENT82_REQ', 'TCC_PERF_SEL_CLIENT83_REQ', 'TCC_PERF_SEL_CLIENT84_REQ', 'TCC_PERF_SEL_CLIENT85_REQ', 'TCC_PERF_SEL_CLIENT86_REQ', 'TCC_PERF_SEL_CLIENT87_REQ', 'TCC_PERF_SEL_CLIENT88_REQ', 'TCC_PERF_SEL_CLIENT89_REQ', 'TCC_PERF_SEL_CLIENT8_REQ', 'TCC_PERF_SEL_CLIENT90_REQ', 'TCC_PERF_SEL_CLIENT91_REQ', 'TCC_PERF_SEL_CLIENT92_REQ', 'TCC_PERF_SEL_CLIENT93_REQ', 'TCC_PERF_SEL_CLIENT94_REQ', 'TCC_PERF_SEL_CLIENT95_REQ', 'TCC_PERF_SEL_CLIENT96_REQ', 'TCC_PERF_SEL_CLIENT97_REQ', 'TCC_PERF_SEL_CLIENT98_REQ', 'TCC_PERF_SEL_CLIENT99_REQ', 'TCC_PERF_SEL_CLIENT9_REQ', 'TCC_PERF_SEL_COMPRESSED_0_REQ', 'TCC_PERF_SEL_COMPRESSED_REQ', 'TCC_PERF_SEL_CYCLE', 'TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'TCC_PERF_SEL_EA_ATOMIC', 'TCC_PERF_SEL_EA_ATOMIC_LEVEL', 'TCC_PERF_SEL_EA_RDREQ', 'TCC_PERF_SEL_EA_RDREQ_32B', 'TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL', 'TCC_PERF_SEL_EA_RDREQ_LEVEL', 'TCC_PERF_SEL_EA_RD_COMPRESSED_32B', 'TCC_PERF_SEL_EA_RD_MDC_32B', 'TCC_PERF_SEL_EA_RD_UNCACHED_32B', 'TCC_PERF_SEL_EA_WRREQ', 'TCC_PERF_SEL_EA_WRREQ_64B', 'TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL', 'TCC_PERF_SEL_EA_WRREQ_LEVEL', 'TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND', 'TCC_PERF_SEL_EA_WRREQ_STALL', 'TCC_PERF_SEL_EA_WR_UNCACHED_32B', 'TCC_PERF_SEL_EXE_REQ', 'TCC_PERF_SEL_FULLY_WRITTEN_HIT', 'TCC_PERF_SEL_HIT', 'TCC_PERF_SEL_HOLE_FIFO_FULL', 'TCC_PERF_SEL_HOLE_LEVEL', 'TCC_PERF_SEL_IB_MDC_STALL', 'TCC_PERF_SEL_IB_REQ', 'TCC_PERF_SEL_IB_STALL', 'TCC_PERF_SEL_IB_TAG_STALL', 'TCC_PERF_SEL_LATENCY_FIFO_FULL', 'TCC_PERF_SEL_MDC_LEVEL', 'TCC_PERF_SEL_MDC_REQ', 'TCC_PERF_SEL_MDC_SECTOR_HIT', 'TCC_PERF_SEL_MDC_SECTOR_MISS', 'TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', 'TCC_PERF_SEL_MDC_TAG_HIT', 'TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', 'TCC_PERF_SEL_MDC_TAG_STALL', 'TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', 'TCC_PERF_SEL_METADATA_REQ', 'TCC_PERF_SEL_MISS', 'TCC_PERF_SEL_NC_VIRTUAL_REQ', 'TCC_PERF_SEL_NONE', 'TCC_PERF_SEL_NORMAL_EVICT', 'TCC_PERF_SEL_NORMAL_WRITEBACK', 'TCC_PERF_SEL_PROBE', 'TCC_PERF_SEL_PROBE_ALL', 'TCC_PERF_SEL_PROBE_EVICT', 'TCC_PERF_SEL_PROBE_FILTER_DISABLED', 'TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', 'TCC_PERF_SEL_READ', 'TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE', 'TCC_PERF_SEL_READ_RETURN_TIMEOUT', 'TCC_PERF_SEL_REQ', 'TCC_PERF_SEL_RETURN_ACK', 'TCC_PERF_SEL_RETURN_ACK_HOLE', 'TCC_PERF_SEL_RETURN_DATA', 'TCC_PERF_SEL_RETURN_HOLE', 'TCC_PERF_SEL_SECTOR_HIT', 'TCC_PERF_SEL_SRC_FIFO_FULL', 'TCC_PERF_SEL_STREAMING_REQ', 'TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', 'TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', 'TCC_PERF_SEL_TAG_PROBE_FILTER_STALL', 'TCC_PERF_SEL_TAG_PROBE_STALL', 'TCC_PERF_SEL_TAG_STALL', 'TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', 'TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', 'TCC_PERF_SEL_TCA_LEVEL', 'TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE', 'TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT', 'TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH', 'TCC_PERF_SEL_TC_OP_INVL2_NC_START', 'TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE', 'TCC_PERF_SEL_TC_OP_WBINVL2_EVICT', 'TCC_PERF_SEL_TC_OP_WBINVL2_FINISH', 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE', 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT', 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH', 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_START', 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK', 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE', 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT', 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH', 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_START', 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK', 'TCC_PERF_SEL_TC_OP_WBINVL2_START', 'TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK', 'TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE', 'TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT', 'TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH', 'TCC_PERF_SEL_TC_OP_WBL2_NC_START', 'TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK', 'TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE', 'TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT', 'TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH', 'TCC_PERF_SEL_TC_OP_WBL2_WC_START', 'TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK', 'TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 'TCC_PERF_SEL_UC_VIRTUAL_REQ', 'TCC_PERF_SEL_WRITE', 'TCC_PERF_SEL_WRITEBACK', 'TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT', 'TCP_CACHE_POLICIES', 'TCP_CACHE_POLICY_HIT_EVICT', 'TCP_CACHE_POLICY_HIT_LRU', 'TCP_CACHE_POLICY_MISS_EVICT', 'TCP_CACHE_POLICY_MISS_LRU', 'TCP_CACHE_STORE_POLICIES', 'TCP_CACHE_STORE_POLICY_WT_EVICT', 'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_DSM_DATA_SEL', 'TCP_DSM_DISABLE', 'TCP_DSM_INJECT_SEL', 'TCP_DSM_INJECT_SEL0', 'TCP_DSM_INJECT_SEL1', 'TCP_DSM_INJECT_SEL2', 'TCP_DSM_INJECT_SEL3', 'TCP_DSM_SEL0', 'TCP_DSM_SEL1', 'TCP_DSM_SEL_BOTH', 'TCP_DSM_SINGLE_WRITE', 'TCP_DSM_SINGLE_WRITE_DIS', 'TCP_DSM_SINGLE_WRITE_EN', 'TCP_PERFCOUNT_SELECT', 'TCP_PERF_SEL_ALLOC_STALL_CYCLES', 'TCP_PERF_SEL_ARR_1D_THICK', 'TCP_PERF_SEL_ARR_1D_THIN1', 'TCP_PERF_SEL_ARR_2D_THICK', 'TCP_PERF_SEL_ARR_2D_THIN1', 'TCP_PERF_SEL_ARR_2D_XTHICK', 'TCP_PERF_SEL_ARR_3D_THICK', 'TCP_PERF_SEL_ARR_3D_THIN1', 'TCP_PERF_SEL_ARR_3D_XTHICK', 'TCP_PERF_SEL_ARR_LINEAR_ALIGNED', 'TCP_PERF_SEL_ARR_LINEAR_GENERAL', 'TCP_PERF_SEL_ARR_PRT_2D_THICK', 'TCP_PERF_SEL_ARR_PRT_2D_THIN1', 'TCP_PERF_SEL_ARR_PRT_3D_THICK', 'TCP_PERF_SEL_ARR_PRT_3D_THIN1', 'TCP_PERF_SEL_ARR_PRT_THICK', 'TCP_PERF_SEL_ARR_PRT_THIN1', 'TCP_PERF_SEL_ATC', 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES', 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32', 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64', 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32', 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64', 'TCP_PERF_SEL_BUF_READ_FMT_16', 'TCP_PERF_SEL_BUF_READ_FMT_32', 'TCP_PERF_SEL_BUF_READ_FMT_8', 'TCP_PERF_SEL_BUF_WRITE_FMT_16', 'TCP_PERF_SEL_BUF_WRITE_FMT_32', 'TCP_PERF_SEL_BUF_WRITE_FMT_8', 'TCP_PERF_SEL_CORE_REG_SCLK_VLD', 'TCP_PERF_SEL_CP_TCP_INVALIDATE', 'TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL', 'TCP_PERF_SEL_DEPTH_MICROTILING', 'TCP_PERF_SEL_DIM_1D', 'TCP_PERF_SEL_DIM_1D_ARRAY', 'TCP_PERF_SEL_DIM_2D', 'TCP_PERF_SEL_DIM_2D_ARRAY', 'TCP_PERF_SEL_DIM_2D_ARRAY_MSAA', 'TCP_PERF_SEL_DIM_2D_MSAA', 'TCP_PERF_SEL_DIM_3D', 'TCP_PERF_SEL_DIM_CUBE_ARRAY', 'TCP_PERF_SEL_DISPLAY_MICROTILING', 'TCP_PERF_SEL_GATE_EN1', 'TCP_PERF_SEL_GATE_EN2', 'TCP_PERF_SEL_HOLE_READ_STALL', 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32', 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64', 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32', 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64', 'TCP_PERF_SEL_IMG_READ_FMT_1', 'TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE', 'TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE', 'TCP_PERF_SEL_IMG_READ_FMT_16', 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_128', 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_64', 'TCP_PERF_SEL_IMG_READ_FMT_32', 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_128', 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_16', 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_8', 'TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE', 'TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE', 'TCP_PERF_SEL_IMG_READ_FMT_8', 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_32', 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_64', 'TCP_PERF_SEL_IMG_READ_FMT_96', 'TCP_PERF_SEL_IMG_READ_FMT_BC1', 'TCP_PERF_SEL_IMG_READ_FMT_BC2', 'TCP_PERF_SEL_IMG_READ_FMT_BC3', 'TCP_PERF_SEL_IMG_READ_FMT_BC4', 'TCP_PERF_SEL_IMG_READ_FMT_BC5', 'TCP_PERF_SEL_IMG_READ_FMT_BC6', 'TCP_PERF_SEL_IMG_READ_FMT_BC7', 'TCP_PERF_SEL_IMG_READ_FMT_D16', 'TCP_PERF_SEL_IMG_READ_FMT_D32', 'TCP_PERF_SEL_IMG_READ_FMT_D8', 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_R', 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG', 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB', 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA', 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1', 'TCP_PERF_SEL_IMG_READ_FMT_I16', 'TCP_PERF_SEL_IMG_READ_FMT_I32', 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16', 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8', 'TCP_PERF_SEL_IMG_READ_FMT_I8', 'TCP_PERF_SEL_IMG_WRITE_FMT_128', 'TCP_PERF_SEL_IMG_WRITE_FMT_16', 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128', 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64', 'TCP_PERF_SEL_IMG_WRITE_FMT_32', 'TCP_PERF_SEL_IMG_WRITE_FMT_64', 'TCP_PERF_SEL_IMG_WRITE_FMT_8', 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32', 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64', 'TCP_PERF_SEL_IMG_WRITE_FMT_D16', 'TCP_PERF_SEL_IMG_WRITE_FMT_D32', 'TCP_PERF_SEL_IMG_WRITE_FMT_D8', 'TCP_PERF_SEL_LFIFO_STALL_CYCLES', 'TCP_PERF_SEL_LOD_STALL_CYCLES', 'TCP_PERF_SEL_PENDING_STALL_CYCLES', 'TCP_PERF_SEL_POWER_STALL', 'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES', 'TCP_PERF_SEL_READFIFO_STALL_CYCLES', 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES', 'TCP_PERF_SEL_RESERVED_154', 'TCP_PERF_SEL_RFIFO_STALL_CYCLES', 'TCP_PERF_SEL_ROTATED_MICROTILING', 'TCP_PERF_SEL_SHOOTDOWN', 'TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL', 'TCP_PERF_SEL_TAGRAM0_REQ', 'TCP_PERF_SEL_TAGRAM1_REQ', 'TCP_PERF_SEL_TAGRAM2_REQ', 'TCP_PERF_SEL_TAGRAM3_REQ', 'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES', 'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES', 'TCP_PERF_SEL_TA_TCP_STATE_READ', 'TCP_PERF_SEL_TCC_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ', 'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ', 'TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_BYPASS_READ_REQ', 'TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ', 'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_CC_READ_REQ', 'TCP_PERF_SEL_TCC_CC_WRITE_REQ', 'TCP_PERF_SEL_TCC_DATA_BUS_BUSY', 'TCP_PERF_SEL_TCC_DCC_REQ', 'TCP_PERF_SEL_TCC_LRU_REQ', 'TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ', 'TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ', 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_NC_READ_REQ', 'TCP_PERF_SEL_TCC_NC_WRITE_REQ', 'TCP_PERF_SEL_TCC_NON_READ_REQ', 'TCP_PERF_SEL_TCC_PHYSICAL_REQ', 'TCP_PERF_SEL_TCC_READ_REQ', 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY', 'TCP_PERF_SEL_TCC_REQ', 'TCP_PERF_SEL_TCC_STREAM_REQ', 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_UC_READ_REQ', 'TCP_PERF_SEL_TCC_UC_WRITE_REQ', 'TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ', 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ', 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ', 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ', 'TCP_PERF_SEL_TCC_VOLATILE_READ_REQ', 'TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ', 'TCP_PERF_SEL_TCC_WRITE_REQ', 'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY', 'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY', 'TCP_PERF_SEL_TCP_LATENCY', 'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES', 'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES', 'TCP_PERF_SEL_TCR_RDRET_STALL', 'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES', 'TCP_PERF_SEL_TC_TA_XNACK_STALL', 'TCP_PERF_SEL_TD_TCP_STALL_CYCLES', 'TCP_PERF_SEL_THICK_MICROTILING', 'TCP_PERF_SEL_THIN_MICROTILING', 'TCP_PERF_SEL_TOTAL_ACCESSES', 'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET', 'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET', 'TCP_PERF_SEL_TOTAL_GLOBAL_READ', 'TCP_PERF_SEL_TOTAL_GLOBAL_WRITE', 'TCP_PERF_SEL_TOTAL_HIT_EVICT_READ', 'TCP_PERF_SEL_TOTAL_HIT_LRU_READ', 'TCP_PERF_SEL_TOTAL_LOCAL_READ', 'TCP_PERF_SEL_TOTAL_LOCAL_WRITE', 'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ', 'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE', 'TCP_PERF_SEL_TOTAL_MISS_LRU_READ', 'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE', 'TCP_PERF_SEL_TOTAL_NON_READ', 'TCP_PERF_SEL_TOTAL_READ', 'TCP_PERF_SEL_TOTAL_WBINVL1', 'TCP_PERF_SEL_TOTAL_WBINVL1_VOL', 'TCP_PERF_SEL_TOTAL_WRITE', 'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES', 'TCP_PERF_SEL_UNALIGNED', 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', 'TCP_PERF_SEL_UTCL1_LFIFO_FULL', 'TCP_PERF_SEL_UTCL1_PERMISSION_MISS', 'TCP_PERF_SEL_UTCL1_REQUEST', 'TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL', 'TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', 'TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', 'TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', 'TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', 'TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', 'TCP_PERF_SEL_UTCL1_TRANSLATION_MISS', 'TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT', 'TCP_PERF_SEL_VOLATILE', 'TCP_PERF_SEL_WRITE_CONFLICT_STALL', 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES', 'TCP_WATCH_MODES', 'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC', 'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', 'TC_CHUB_REQ_CREDITS', 'TC_CHUB_REQ_CREDITS_ENUM', 'TC_EA_CID', 'TC_EA_CID_CPF', 'TC_EA_CID_CPG', 'TC_EA_CID_DCC', 'TC_EA_CID_FMASK', 'TC_EA_CID_HTILE', 'TC_EA_CID_IA', 'TC_EA_CID_MISC', 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC', 'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA', 'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', 'TC_MICRO_TILE_MODE', 'TC_NACKS', 'TC_NACK_DATA_ERROR', 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT', 'TC_NACK_PROTECTION_FAULT', 'TC_ONLY', 'TC_OP', 'TC_OP_ATOMIC_ADD_32', 'TC_OP_ATOMIC_ADD_64', 'TC_OP_ATOMIC_ADD_RTN_32', 'TC_OP_ATOMIC_ADD_RTN_64', 'TC_OP_ATOMIC_AND_32', 'TC_OP_ATOMIC_AND_64', 'TC_OP_ATOMIC_AND_RTN_32', 'TC_OP_ATOMIC_AND_RTN_64', 'TC_OP_ATOMIC_CMPSWAP_32', 'TC_OP_ATOMIC_CMPSWAP_64', 'TC_OP_ATOMIC_CMPSWAP_RTN_32', 'TC_OP_ATOMIC_CMPSWAP_RTN_64', 'TC_OP_ATOMIC_DEC_32', 'TC_OP_ATOMIC_DEC_64', 'TC_OP_ATOMIC_DEC_RTN_32', 'TC_OP_ATOMIC_DEC_RTN_64', 'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64', 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', 'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64', 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', 'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64', 'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64', 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', 'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64', 'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64', 'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64', 'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64', 'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64', 'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64', 'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64', 'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64', 'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64', 'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64', 'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64', 'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64', 'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64', 'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64', 'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64', 'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64', 'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64', 'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64', 'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64', 'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS', 'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN', 'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER', 'TC_OP_READ', 'TC_OP_RESERVED_FOP_32_0', 'TC_OP_RESERVED_FOP_32_1', 'TC_OP_RESERVED_FOP_32_2', 'TC_OP_RESERVED_FOP_64_0', 'TC_OP_RESERVED_FOP_64_1', 'TC_OP_RESERVED_FOP_64_2', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', 'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_1', 'TC_OP_RESERVED_FOP_RTN_32_2', 'TC_OP_RESERVED_FOP_RTN_64_0', 'TC_OP_RESERVED_FOP_RTN_64_1', 'TC_OP_RESERVED_FOP_RTN_64_2', 'TC_OP_RESERVED_NON_FLOAT_32_1', 'TC_OP_RESERVED_NON_FLOAT_32_2', 'TC_OP_RESERVED_NON_FLOAT_32_3', 'TC_OP_RESERVED_NON_FLOAT_32_4', 'TC_OP_RESERVED_NON_FLOAT_64_1', 'TC_OP_RESERVED_NON_FLOAT_64_2', 'TC_OP_RESERVED_NON_FLOAT_64_3', 'TC_OP_RESERVED_NON_FLOAT_64_4', 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1', 'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2', 'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC', 'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL', 'TD_PERF_SEL_RESERVED_14', 'TD_PERF_SEL_RESERVED_18', 'TD_PERF_SEL_RESERVED_19', 'TD_PERF_SEL_RESERVED_39', 'TD_PERF_SEL_RESERVED_43', 'TD_PERF_SEL_RESERVED_44', 'TD_PERF_SEL_addresscmd_poison', 'TD_PERF_SEL_atomic_wavefront', 'TD_PERF_SEL_bypass_filter_wavefront', 'TD_PERF_SEL_coalescable_wavefront', 'TD_PERF_SEL_coalesced_phase', 'TD_PERF_SEL_constant_state_full', 'TD_PERF_SEL_consume_gds_traffic', 'TD_PERF_SEL_d16_data_packed', 'TD_PERF_SEL_d16_en_wavefront', 'TD_PERF_SEL_data_poison', 'TD_PERF_SEL_eight_phase_wavefront', 'TD_PERF_SEL_four_phase_forward_wavefront', 'TD_PERF_SEL_four_phase_wavefront', 'TD_PERF_SEL_gather4_wavefront', 'TD_PERF_SEL_gather4h_packed_wavefront', 'TD_PERF_SEL_gather4h_wavefront', 'TD_PERF_SEL_gather8h_packed_wavefront', 'TD_PERF_SEL_gds_stall', 'TD_PERF_SEL_input_busy', 'TD_PERF_SEL_ldfptr_wavefront', 'TD_PERF_SEL_lerp_busy', 'TD_PERF_SEL_load_wavefront', 'TD_PERF_SEL_local_cg_dyn_sclk_grp0_en', 'TD_PERF_SEL_local_cg_dyn_sclk_grp1_en', 'TD_PERF_SEL_local_cg_dyn_sclk_grp4_en', 'TD_PERF_SEL_local_cg_dyn_sclk_grp5_en', 'TD_PERF_SEL_min_max_filter_wavefront', 'TD_PERF_SEL_nack', 'TD_PERF_SEL_none', 'TD_PERF_SEL_null_cycle_output', 'TD_PERF_SEL_opaque_black_border', 'TD_PERF_SEL_output_busy', 'TD_PERF_SEL_output_fifo_full', 'TD_PERF_SEL_pc_stall', 'TD_PERF_SEL_reg_sclk_vld', 'TD_PERF_SEL_sample_c_wavefront', 'TD_PERF_SEL_sample_state_full', 'TD_PERF_SEL_sixteen_phase_wavefront', 'TD_PERF_SEL_start_cycle_0', 'TD_PERF_SEL_start_cycle_1', 'TD_PERF_SEL_start_cycle_2', 'TD_PERF_SEL_start_cycle_3', 'TD_PERF_SEL_store_wavefront', 'TD_PERF_SEL_tc_stall', 'TD_PERF_SEL_tc_td_fifo_full', 'TD_PERF_SEL_td_busy', 'TD_PERF_SEL_td_sp_traffic', 'TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt', 'TD_PERF_SEL_user_defined_border', 'TD_PERF_SEL_white_border', 'TD_PERF_SEL_write_ack_wavefront', 'TESS_ISOLINE', 'TESS_QUAD', 'TESS_TRIANGLE', 'TEX_BORDER_COLOR_TYPE', 'TEX_BorderColor_OpaqueBlack', 'TEX_BorderColor_OpaqueWhite', 'TEX_BorderColor_Register', 'TEX_BorderColor_TransparentBlack', 'TEX_CHROMA_KEY', 'TEX_CLAMP', 'TEX_COORD_TYPE', 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled', 'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3', 'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder', 'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror', 'TEX_Clamp_MirrorOnceHalfToBorder', 'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast', 'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized', 'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION', 'TEX_DIM', 'TEX_DepthCompareFunction_Always', 'TEX_DepthCompareFunction_Equal', 'TEX_DepthCompareFunction_Greater', 'TEX_DepthCompareFunction_GreaterEqual', 'TEX_DepthCompareFunction_Less', 'TEX_DepthCompareFunction_LessEqual', 'TEX_DepthCompareFunction_Never', 'TEX_DepthCompareFunction_NotEqual', 'TEX_Dim_1D', 'TEX_Dim_1DArray', 'TEX_Dim_2D', 'TEX_Dim_2DArray', 'TEX_Dim_2DArray_MSAA', 'TEX_Dim_2D_MSAA', 'TEX_Dim_3D', 'TEX_Dim_CubeMap', 'TEX_FORMAT_COMP', 'TEX_FormatComp_RESERVED_3', 'TEX_FormatComp_Signed', 'TEX_FormatComp_Unsigned', 'TEX_FormatComp_UnsignedBiased', 'TEX_MAX_ANISO_RATIO', 'TEX_MIP_FILTER', 'TEX_MaxAnisoRatio_16to1', 'TEX_MaxAnisoRatio_1to1', 'TEX_MaxAnisoRatio_2to1', 'TEX_MaxAnisoRatio_4to1', 'TEX_MaxAnisoRatio_8to1', 'TEX_MaxAnisoRatio_RESERVED_5', 'TEX_MaxAnisoRatio_RESERVED_6', 'TEX_MaxAnisoRatio_RESERVED_7', 'TEX_MipFilter_Linear', 'TEX_MipFilter_None', 'TEX_MipFilter_Point', 'TEX_MipFilter_Point_Aniso_Adj', 'TEX_REQUEST_SIZE', 'TEX_RequestSize_128B', 'TEX_RequestSize_2X64B', 'TEX_RequestSize_32B', 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE', 'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid', 'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint', 'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER', 'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point', 'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER', 'THREAD_TRACE_FINISH', 'THREAD_TRACE_FLUSH', 'THREAD_TRACE_MARKER', 'THREAD_TRACE_START', 'THREAD_TRACE_STOP', 'TMDS_COLOR_FORMAT', 'TMDS_COLOR_FORMAT_DUAL30BPP', 'TMDS_COLOR_FORMAT_RESERVED', 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', 'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN', 'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0', 'TMDS_CTL0_DATA_MODULATION_BIT1', 'TMDS_CTL0_DATA_MODULATION_BIT2', 'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL', 'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED', 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC', 'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC', 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', 'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN', 'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT', 'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION', 'TMDS_CTL1_DATA_MODULATION_BIT0', 'TMDS_CTL1_DATA_MODULATION_BIT1', 'TMDS_CTL1_DATA_MODULATION_BIT2', 'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL', 'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED', 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC', 'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC', 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', 'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN', 'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT', 'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION', 'TMDS_CTL2_DATA_MODULATION_BIT0', 'TMDS_CTL2_DATA_MODULATION_BIT1', 'TMDS_CTL2_DATA_MODULATION_BIT2', 'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL', 'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED', 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC', 'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC', 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', 'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN', 'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT', 'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION', 'TMDS_CTL3_DATA_MODULATION_BIT0', 'TMDS_CTL3_DATA_MODULATION_BIT1', 'TMDS_CTL3_DATA_MODULATION_BIT2', 'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL', 'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED', 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC', 'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC', 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', 'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN', 'TMDS_CTL3_PATTERN_OUT_ENABLE', 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL', 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', 'TMDS_DVO_MUX_SELECT', 'TMDS_DVO_MUX_SELECT_B', 'TMDS_DVO_MUX_SELECT_G', 'TMDS_DVO_MUX_SELECT_R', 'TMDS_DVO_MUX_SELECT_RESERVED', 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', 'TMDS_PIXEL_ENCODING', 'TMDS_PIXEL_ENCODING_422', 'TMDS_PIXEL_ENCODING_444_OR_420', 'TMDS_REG_TEST_OUTPUTA_CNTLA', 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', 'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0', 'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2', 'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG', 'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START', 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA', 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB', 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA', 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB', 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN', 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK', 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN', 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK', 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS', 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS', 'TMDS_TRANSMITTER_ENABLE_HPD_MASK', 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK', 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK', 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', 'TMDS_TRANSMITTER_PLLSEL_BY_HW', 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', 'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES', 'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES', 'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES', 'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS', 'TRISTRIP', 'TVX_DATA_FORMAT', 'TVX_DST_SEL', 'TVX_DstSel_0f', 'TVX_DstSel_1f', 'TVX_DstSel_Mask', 'TVX_DstSel_RESERVED_6', 'TVX_DstSel_W', 'TVX_DstSel_X', 'TVX_DstSel_Y', 'TVX_DstSel_Z', 'TVX_ENDIAN_SWAP', 'TVX_EndianSwap_8in16', 'TVX_EndianSwap_8in32', 'TVX_EndianSwap_8in64', 'TVX_EndianSwap_None', 'TVX_FMT_1', 'TVX_FMT_10_10_10_2', 'TVX_FMT_10_11_11', 'TVX_FMT_10_11_11_FLOAT', 'TVX_FMT_11_11_10', 'TVX_FMT_11_11_10_FLOAT', 'TVX_FMT_16', 'TVX_FMT_16_16', 'TVX_FMT_16_16_16', 'TVX_FMT_16_16_16_16', 'TVX_FMT_16_16_16_16_FLOAT', 'TVX_FMT_16_16_16_FLOAT', 'TVX_FMT_16_16_FLOAT', 'TVX_FMT_16_FLOAT', 'TVX_FMT_1_5_5_5', 'TVX_FMT_1_REVERSED', 'TVX_FMT_24_8', 'TVX_FMT_24_8_FLOAT', 'TVX_FMT_2_10_10_10', 'TVX_FMT_32', 'TVX_FMT_32_32', 'TVX_FMT_32_32_32', 'TVX_FMT_32_32_32_32', 'TVX_FMT_32_32_32_32_FLOAT', 'TVX_FMT_32_32_32_FLOAT', 'TVX_FMT_32_32_FLOAT', 'TVX_FMT_32_AS_8', 'TVX_FMT_32_AS_8_8', 'TVX_FMT_32_FLOAT', 'TVX_FMT_3_3_2', 'TVX_FMT_4_4', 'TVX_FMT_4_4_4_4', 'TVX_FMT_5_5_5_1', 'TVX_FMT_5_6_5', 'TVX_FMT_5_9_9_9_SHAREDEXP', 'TVX_FMT_6_5_5', 'TVX_FMT_8', 'TVX_FMT_8_24', 'TVX_FMT_8_24_FLOAT', 'TVX_FMT_8_8', 'TVX_FMT_8_8_8', 'TVX_FMT_8_8_8_8', 'TVX_FMT_APC0', 'TVX_FMT_APC1', 'TVX_FMT_APC2', 'TVX_FMT_APC3', 'TVX_FMT_APC4', 'TVX_FMT_APC5', 'TVX_FMT_APC6', 'TVX_FMT_APC7', 'TVX_FMT_BC1', 'TVX_FMT_BC2', 'TVX_FMT_BC3', 'TVX_FMT_BC4', 'TVX_FMT_BC5', 'TVX_FMT_BG_RG', 'TVX_FMT_CTX1', 'TVX_FMT_GB_GR', 'TVX_FMT_INVALID', 'TVX_FMT_RESERVED_33', 'TVX_FMT_RESERVED_36', 'TVX_FMT_RESERVED_4', 'TVX_FMT_RESERVED_63', 'TVX_FMT_X24_8_32_FLOAT', 'TVX_INST', 'TVX_Inst_Gather4', 'TVX_Inst_Gather4_C', 'TVX_Inst_Gather4_C_O', 'TVX_Inst_Gather4_O', 'TVX_Inst_GetBufferResInfo', 'TVX_Inst_GetGradientsH', 'TVX_Inst_GetGradientsV', 'TVX_Inst_GetLOD', 'TVX_Inst_GetNumberOfSamples', 'TVX_Inst_GetTextureResInfo', 'TVX_Inst_KeepGradients', 'TVX_Inst_LD', 'TVX_Inst_NormalVertexFetch', 'TVX_Inst_Pass', 'TVX_Inst_RESERVED_15', 'TVX_Inst_RESERVED_2', 'TVX_Inst_Sample', 'TVX_Inst_Sample_C', 'TVX_Inst_Sample_C_G', 'TVX_Inst_Sample_C_G_LB', 'TVX_Inst_Sample_C_L', 'TVX_Inst_Sample_C_LB', 'TVX_Inst_Sample_C_LZ', 'TVX_Inst_Sample_G', 'TVX_Inst_Sample_G_LB', 'TVX_Inst_Sample_L', 'TVX_Inst_Sample_LB', 'TVX_Inst_Sample_LZ', 'TVX_Inst_SemanticVertexFetch', 'TVX_Inst_SetGradientsH', 'TVX_Inst_SetGradientsV', 'TVX_Inst_SetTextureOffsets', 'TVX_NUM_FORMAT_ALL', 'TVX_NumFormatAll_Int', 'TVX_NumFormatAll_Norm', 'TVX_NumFormatAll_RESERVED_3', 'TVX_NumFormatAll_Scaled', 'TVX_SRC_SEL', 'TVX_SRFModeAll_NZ', 'TVX_SRFModeAll_ZCMO', 'TVX_SRF_MODE_ALL', 'TVX_SrcSel_0f', 'TVX_SrcSel_1f', 'TVX_SrcSel_W', 'TVX_SrcSel_X', 'TVX_SrcSel_Y', 'TVX_SrcSel_Z', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource', 'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource', 'TVX_Type_ValidVertexBuffer', 'TileSplit', 'TileType', 'UCONFIG_SPACE_END', 'UCONFIG_SPACE_START', 'UNDEF', 'UNP_ADDR_SURF_MACRO_ASPECT_1', 'UNP_ADDR_SURF_MACRO_ASPECT_2', 'UNP_ADDR_SURF_MACRO_ASPECT_4', 'UNP_ADDR_SURF_MACRO_ASPECT_8', 'UNP_ADDR_SURF_TILE_SPLIT_128B', 'UNP_ADDR_SURF_TILE_SPLIT_1KB', 'UNP_ADDR_SURF_TILE_SPLIT_256B', 'UNP_ADDR_SURF_TILE_SPLIT_2KB', 'UNP_ADDR_SURF_TILE_SPLIT_4KB', 'UNP_ADDR_SURF_TILE_SPLIT_512B', 'UNP_ADDR_SURF_TILE_SPLIT_64B', 'UNP_BUFFER_MODE', 'UNP_BUFFER_MODE_LUMA', 'UNP_BUFFER_MODE_LUMA_CHROMA', 'UNP_CRC_LINE_SEL', 'UNP_CRC_LINE_SEL_EVEN_ONLY', 'UNP_CRC_LINE_SEL_ODD_EVEN', 'UNP_CRC_LINE_SEL_ODD_ONLY', 'UNP_CRC_LINE_SEL_RESERVED', 'UNP_CRC_SOURCE_SEL', 'UNP_CRC_SOURCE_SEL_LOWER16', 'UNP_CRC_SOURCE_SEL_LOWER32', 'UNP_CRC_SOURCE_SEL_NP_TO_LBV', 'UNP_CRC_SOURCE_SEL_RESERVED', 'UNP_CRC_SOURCE_SEL_UNP_TO_LBV', 'UNP_GRPH_16BPP', 'UNP_GRPH_32BPP', 'UNP_GRPH_8BPP', 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE', 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0', 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1', 'UNP_GRPH_ADDR_SURF_16_BANK', 'UNP_GRPH_ADDR_SURF_2_BANK', 'UNP_GRPH_ADDR_SURF_4_BANK', 'UNP_GRPH_ADDR_SURF_8_BANK', 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1', 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2', 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4', 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8', 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_1', 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_2', 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_4', 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_8', 'UNP_GRPH_BANK_HEIGHT', 'UNP_GRPH_BANK_WIDTH', 'UNP_GRPH_BLUE_CROSSBAR', 'UNP_GRPH_BLUE_CROSSBAR_A', 'UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C', 'UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y', 'UNP_GRPH_BLUE_CROSSBAR_R_Cr', 'UNP_GRPH_COLOR_EXPANSION_MODE', 'UNP_GRPH_DEPTH', 'UNP_GRPH_DISABLED', 'UNP_GRPH_DYNAMIC_EXPANSION', 'UNP_GRPH_EN', 'UNP_GRPH_ENABLED', 'UNP_GRPH_ENDIAN_SWAP', 'UNP_GRPH_ENDIAN_SWAP_8IN16', 'UNP_GRPH_ENDIAN_SWAP_8IN32', 'UNP_GRPH_ENDIAN_SWAP_8IN43', 'UNP_GRPH_ENDIAN_SWAP_NONE', 'UNP_GRPH_GREEN_CROSSBAR', 'UNP_GRPH_MACRO_TILE_ASPECT', 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE', 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0', 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1', 'UNP_GRPH_MODE_UPDATE_LOCKG', 'UNP_GRPH_NUM_BANKS', 'UNP_GRPH_RED_CROSSBAR', 'UNP_GRPH_RED_CROSSBAR_A', 'UNP_GRPH_RED_CROSSBAR_B_Cb', 'UNP_GRPH_RED_CROSSBAR_G_Y', 'UNP_GRPH_RED_CROSSBAR_R_Cr', 'UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE', 'UNP_GRPH_STACK_INTERLACE_FLIP_EN', 'UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE', 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE', 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0', 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1', 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2', 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3', 'UNP_GRPH_STEREOSYNC_FLIP_DISABLE', 'UNP_GRPH_STEREOSYNC_FLIP_EN', 'UNP_GRPH_STEREOSYNC_FLIP_ENABLE', 'UNP_GRPH_STEREOSYNC_FLIP_MODE', 'UNP_GRPH_STEREOSYNC_FLIP_MODE_0', 'UNP_GRPH_STEREOSYNC_FLIP_MODE_1', 'UNP_GRPH_STEREOSYNC_FLIP_MODE_2', 'UNP_GRPH_STEREOSYNC_FLIP_MODE_3', 'UNP_GRPH_STEREOSYNC_SELECT_DIS', 'UNP_GRPH_STEREOSYNC_SELECT_DISABLE', 'UNP_GRPH_STEREOSYNC_SELECT_EN', 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE', 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0', 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1', 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK', 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0', 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1', 'UNP_GRPH_TILE_SPLIT', 'UNP_GRPH_UPDATE_LOCK_0', 'UNP_GRPH_UPDATE_LOCK_1', 'UNP_GRPH_ZERO_EXPANSION', 'UNP_PIXEL_DROP', 'UNP_PIXEL_DROPPING', 'UNP_PIXEL_NO_DROP', 'UNP_ROTATION_ANGLE', 'UNP_ROTATION_ANGLE_0', 'UNP_ROTATION_ANGLE_0m', 'UNP_ROTATION_ANGLE_180', 'UNP_ROTATION_ANGLE_180m', 'UNP_ROTATION_ANGLE_270', 'UNP_ROTATION_ANGLE_270m', 'UNP_ROTATION_ANGLE_90', 'UNP_ROTATION_ANGLE_90m', 'UNP_UNP_GRPH_GREEN_CROSSBAR_A', 'UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C', 'UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y', 'UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr', 'UNP_VIDEO_FORMAT', 'UNP_VIDEO_FORMAT0', 'UNP_VIDEO_FORMAT1', 'UNP_VIDEO_FORMAT_YUV420_YCbCr', 'UNP_VIDEO_FORMAT_YUV420_YCrCb', 'UNP_VIDEO_FORMAT_YUV422_CbY', 'UNP_VIDEO_FORMAT_YUV422_CrY', 'UNP_VIDEO_FORMAT_YUV422_YCb', 'UNP_VIDEO_FORMAT_YUV422_YCr', 'UPDATE_LOCKED', 'UPDATE_UNLOCKED', 'UTCL1FaultType', 'UTCL1RequestType', 'UTCL1_TYPE_BYPASS', 'UTCL1_TYPE_NORMAL', 'UTCL1_TYPE_SHOOTDOWN', 'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', 'UTCL1_XNACK_RETRY', 'UTCL1_XNACK_SUCCESS', 'VC_AND_TC', 'VC_ONLY', 'VGT_CACHE_INVALID_MODE', 'VGT_DIST_MODE', 'VGT_DI_INDEX_SIZE', 'VGT_DI_MAJOR_MODE_SELECT', 'VGT_DI_PRIM_TYPE', 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', 'VGT_DMA_BUF_RING', 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', 'VGT_DMA_PTR_UPDATE', 'VGT_DMA_SWAP_16_BIT', 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', 'VGT_DMA_SWAP_NONE', 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', 'VGT_FLUSH', 'VGT_GROUP_CONV_SEL', 'VGT_GRP_2D_COPY_RECT_V0', 'VGT_GRP_2D_COPY_RECT_V1', 'VGT_GRP_2D_COPY_RECT_V2', 'VGT_GRP_2D_COPY_RECT_V3', 'VGT_GRP_2D_FILL_RECT', 'VGT_GRP_2D_LINE', 'VGT_GRP_2D_RECT', 'VGT_GRP_2D_TRI', 'VGT_GRP_3D_LINE', 'VGT_GRP_3D_LINE_ADJ', 'VGT_GRP_3D_PATCH', 'VGT_GRP_3D_POINT', 'VGT_GRP_3D_QUAD', 'VGT_GRP_3D_RECT', 'VGT_GRP_3D_TRI', 'VGT_GRP_3D_TRI_ADJ', 'VGT_GRP_AUTO_PRIM', 'VGT_GRP_FAN', 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32', 'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_LIST', 'VGT_GRP_LOOP', 'VGT_GRP_POLYGON', 'VGT_GRP_PRIM_INDEX_LINE', 'VGT_GRP_PRIM_INDEX_QUAD', 'VGT_GRP_PRIM_INDEX_TRI', 'VGT_GRP_PRIM_ORDER', 'VGT_GRP_PRIM_TYPE', 'VGT_GRP_SINT_16', 'VGT_GRP_SINT_32', 'VGT_GRP_STRIP', 'VGT_GRP_UINT_16', 'VGT_GRP_UINT_32', 'VGT_GS_CUT_MODE', 'VGT_GS_MODE_TYPE', 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', 'VGT_INDEX_32', 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', 'VGT_OUTPATH_GS_BLOCK', 'VGT_OUTPATH_HS_BLOCK', 'VGT_OUTPATH_PASSTHRU', 'VGT_OUTPATH_PRIM_GEN', 'VGT_OUTPATH_SELECT', 'VGT_OUTPATH_TESS_EN', 'VGT_OUTPATH_VTX_REUSE', 'VGT_OUT_2D_RECT', 'VGT_OUT_LINE', 'VGT_OUT_LINE_ADJ', 'VGT_OUT_PATCH', 'VGT_OUT_POINT', 'VGT_OUT_PRIM_TYPE', 'VGT_OUT_RECT_V0', 'VGT_OUT_RECT_V1', 'VGT_OUT_RECT_V2', 'VGT_OUT_RECT_V3', 'VGT_OUT_TRI', 'VGT_OUT_TRI_ADJ', 'VGT_PERFCOUNT_SELECT', 'VGT_POLICY_LRU', 'VGT_POLICY_STREAM', 'VGT_RDREQ_POLICY', 'VGT_STAGES_ES_EN', 'VGT_STAGES_GS_EN', 'VGT_STAGES_HS_EN', 'VGT_STAGES_LS_EN', 'VGT_STAGES_VS_EN', 'VGT_STREAMOUT_RESET', 'VGT_STREAMOUT_SYNC', 'VGT_TESS_PARTITION', 'VGT_TESS_TOPOLOGY', 'VGT_TESS_TYPE', 'VGT_TE_PRIM_INDEX_LINE', 'VGT_TE_PRIM_INDEX_QUAD', 'VGT_TE_PRIM_INDEX_TRI', 'VGT_TE_QUAD', 'VID_ENHANCED_MODE', 'VID_NORMAL_FRAME_MODE', 'VID_STREAM_DISABLE_MASKED', 'VID_STREAM_DISABLE_UNMASK', 'VMID_SZ', 'VS_PARTIAL_FLUSH', 'VS_STAGE_COPY_SHADER', 'VS_STAGE_DS', 'VS_STAGE_REAL', 'VTX_CLAMP', 'VTX_Clamp_ClampToNAN', 'VTX_Clamp_ClampToZero', 'VTX_FETCH_TYPE', 'VTX_FORMAT_COMP_ALL', 'VTX_FetchType_InstanceData', 'VTX_FetchType_NoIndexOffset', 'VTX_FetchType_RESERVED_3', 'VTX_FetchType_VertexData', 'VTX_FormatCompAll_Signed', 'VTX_FormatCompAll_Unsigned', 'VTX_MEM_REQUEST_SIZE', 'VTX_MemRequestSize_32B', 'VTX_MemRequestSize_64B', 'WD_IA_DRAW_REG_XFER', 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', 'WD_IA_DRAW_SOURCE', 'WD_IA_DRAW_SOURCE_AUTO', 'WD_IA_DRAW_SOURCE_DMA', 'WD_IA_DRAW_SOURCE_IMMD', 'WD_IA_DRAW_SOURCE_OPAQ', 'WD_IA_DRAW_TYPE', 'WD_IA_DRAW_TYPE_DI_MM0', 'WD_IA_DRAW_TYPE_EVENT_ADDR', 'WD_IA_DRAW_TYPE_EVENT_INIT', 'WD_IA_DRAW_TYPE_IMM_DATA', 'WD_IA_DRAW_TYPE_INDX_OFF', 'WD_IA_DRAW_TYPE_MAX_INDX', 'WD_IA_DRAW_TYPE_MIN_INDX', 'WD_IA_DRAW_TYPE_REG_XFER', 'WD_PERFCOUNT_SELECT', 'XDMA_LOCAL_SW_MODE_SW_256B_D', 'XDMA_LOCAL_SW_MODE_SW_64KB_D', 'XDMA_LOCAL_SW_MODE_SW_64KB_D_X', 'XDMA_MSTR_ALPHA_POSITION_15_8', 'XDMA_MSTR_ALPHA_POSITION_23_16', 'XDMA_MSTR_ALPHA_POSITION_31_24', 'XDMA_MSTR_ALPHA_POSITION_7_0', 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0', 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1', 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2', 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3', 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4', 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5', 'XDMA_SLV_ALPHA_POSITION_15_8', 'XDMA_SLV_ALPHA_POSITION_23_16', 'XDMA_SLV_ALPHA_POSITION_31_24', 'XDMA_SLV_ALPHA_POSITION_7_0', 'XTAL_REF_CLOCK_SOURCE_SEL', 'XTAL_REF_CLOCK_SOURCE_SEL_PPLL', 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL', 'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'ZFormat', 'ZLimitSumm', 'ZModeForce', 'ZOrder', 'ZPASS_DISABLE', 'ZPASS_DONE', 'ZPASS_PIXELS', 'ZPASS_SAMPLES', 'ZSamplePosition', 'Z_16', 'Z_24', 'Z_32_FLOAT', 'Z_INVALID', 'Z_SAMPLE_CENTER', 'Z_SAMPLE_CENTROID', 'ZpassControl', '_vega10_ENUM_HEADER', 'ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE', 'ia_perf_MC_LAT_BIN_0', 'ia_perf_MC_LAT_BIN_1', 'ia_perf_MC_LAT_BIN_2', 'ia_perf_MC_LAT_BIN_3', 'ia_perf_MC_LAT_BIN_4', 'ia_perf_MC_LAT_BIN_5', 'ia_perf_MC_LAT_BIN_6', 'ia_perf_MC_LAT_BIN_7', 'ia_perf_RESERVED1', 'ia_perf_RESERVED2', 'ia_perf_RESERVED3', 'ia_perf_RESERVED4', 'ia_perf_RESERVED5', 'ia_perf_RESERVED6', 'ia_perf_RESERVED7', 'ia_perf_dma_data_fifo_full', 'ia_perf_ia_busy', 'ia_perf_ia_dma_return', 'ia_perf_ia_sclk_core_vld_event', 'ia_perf_ia_sclk_reg_vld_event', 'ia_perf_ia_stalled', 'ia_perf_shift_starved_pipe0_event', 'ia_perf_shift_starved_pipe1_event', 'vgt_perf_VGT_PA_CLIPP_EOP', 'vgt_perf_VGT_PA_CLIPP_IS_EVENT', 'vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT', 'vgt_perf_VGT_PA_CLIPP_NULL_PRIM', 'vgt_perf_VGT_PA_CLIPP_SEND', 'vgt_perf_VGT_PA_CLIPP_STALLED', 'vgt_perf_VGT_PA_CLIPP_STARVED_BUSY', 'vgt_perf_VGT_PA_CLIPP_STARVED_IDLE', 'vgt_perf_VGT_PA_CLIPP_STATIC', 'vgt_perf_VGT_PA_CLIPS_SEND', 'vgt_perf_VGT_PA_CLIPS_STALLED', 'vgt_perf_VGT_PA_CLIPS_STARVED_BUSY', 'vgt_perf_VGT_PA_CLIPS_STARVED_IDLE', 'vgt_perf_VGT_PA_CLIPS_STATIC', 'vgt_perf_VGT_PA_CLIPV_FIRSTVERT', 'vgt_perf_VGT_PA_CLIPV_SEND', 'vgt_perf_VGT_PA_CLIPV_STALLED', 'vgt_perf_VGT_PA_CLIPV_STARVED_BUSY', 'vgt_perf_VGT_PA_CLIPV_STARVED_IDLE', 'vgt_perf_VGT_PA_CLIPV_STATIC', 'vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE', 'vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE', 'vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT', 'vgt_perf_VGT_SPI_ESTHREAD_SEND', 'vgt_perf_VGT_SPI_ESVERT_EOV', 'vgt_perf_VGT_SPI_ESVERT_STALLED', 'vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY', 'vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE', 'vgt_perf_VGT_SPI_ESVERT_STATIC', 'vgt_perf_VGT_SPI_ESVERT_VALID', 'vgt_perf_VGT_SPI_GSPRIM_CONT', 'vgt_perf_VGT_SPI_GSPRIM_EOV', 'vgt_perf_VGT_SPI_GSPRIM_STALLED', 'vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY', 'vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE', 'vgt_perf_VGT_SPI_GSPRIM_STATIC', 'vgt_perf_VGT_SPI_GSPRIM_VALID', 'vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE', 'vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT', 'vgt_perf_VGT_SPI_GSTHREAD_SEND', 'vgt_perf_VGT_SPI_HSVERT_EOV', 'vgt_perf_VGT_SPI_HSVERT_STALLED', 'vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY', 'vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE', 'vgt_perf_VGT_SPI_HSVERT_STATIC', 'vgt_perf_VGT_SPI_HSVERT_VALID', 'vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE', 'vgt_perf_VGT_SPI_HSWAVE_IS_EVENT', 'vgt_perf_VGT_SPI_HSWAVE_SEND', 'vgt_perf_VGT_SPI_LSVERT_EOV', 'vgt_perf_VGT_SPI_LSVERT_STALLED', 'vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY', 'vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE', 'vgt_perf_VGT_SPI_LSVERT_STATIC', 'vgt_perf_VGT_SPI_LSVERT_VALID', 'vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE', 'vgt_perf_VGT_SPI_LSWAVE_IS_EVENT', 'vgt_perf_VGT_SPI_LSWAVE_SEND', 'vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE', 'vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT', 'vgt_perf_VGT_SPI_VSTHREAD_SEND', 'vgt_perf_VGT_SPI_VSVERT_EOV', 'vgt_perf_VGT_SPI_VSVERT_SEND', 'vgt_perf_VGT_SPI_VSVERT_STALLED', 'vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY', 'vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE', 'vgt_perf_VGT_SPI_VSVERT_STATIC', 'vgt_perf_cm_reading_stalled', 'vgt_perf_cm_stalled_by_gog', 'vgt_perf_cm_stalled_by_gsfetch_done', 'vgt_perf_counters_avail_stalled', 'vgt_perf_cut_mem_flush_stalled', 'vgt_perf_ds_RESERVED', 'vgt_perf_ds_cache_hits', 'vgt_perf_ds_prims', 'vgt_perf_es_done', 'vgt_perf_es_done_latency', 'vgt_perf_es_flush', 'vgt_perf_es_ring_high_water_mark', 'vgt_perf_es_thread_groups', 'vgt_perf_esthread_stalled_es_rb_full', 'vgt_perf_esthread_stalled_spi_bp', 'vgt_perf_esvert_stalled_es_tbl', 'vgt_perf_esvert_stalled_gs_event', 'vgt_perf_esvert_stalled_gs_tbl', 'vgt_perf_esvert_stalled_gsprim', 'vgt_perf_gog_busy', 'vgt_perf_gog_out_indx_stalled', 'vgt_perf_gog_out_prim_stalled', 'vgt_perf_gog_vs_tbl_stalled', 'vgt_perf_gs_cache_hits', 'vgt_perf_gs_done', 'vgt_perf_gs_done_latency', 'vgt_perf_gs_done_received', 'vgt_perf_gs_event_stall', 'vgt_perf_gs_issue_rtr_stalled', 'vgt_perf_gs_rb_space_avail_stalled', 'vgt_perf_gs_ring_high_water_mark', 'vgt_perf_gsprim_stalled_es_tbl', 'vgt_perf_gsprim_stalled_esvert', 'vgt_perf_gsprim_stalled_gs_event', 'vgt_perf_gsprim_stalled_gs_tbl', 'vgt_perf_gsthread_stalled', 'vgt_perf_hs_done', 'vgt_perf_hs_done_latency', 'vgt_perf_hs_flush', 'vgt_perf_hs_input_stall', 'vgt_perf_hs_interface_stall', 'vgt_perf_hs_tfm_stall', 'vgt_perf_hs_tgs_active_high_water_mark', 'vgt_perf_hs_thread_groups', 'vgt_perf_hs_tif_stall', 'vgt_perf_hs_waiting_on_ls_done_stall', 'vgt_perf_hswave_stalled', 'vgt_perf_ls_done', 'vgt_perf_ls_done_latency', 'vgt_perf_ls_flush', 'vgt_perf_ls_thread_groups', 'vgt_perf_pa_clipp_dealloc', 'vgt_perf_reused_es_indices', 'vgt_perf_reused_vs_indices', 'vgt_perf_sclk_core_vld_event', 'vgt_perf_sclk_gs_vld_event', 'vgt_perf_sclk_reg_vld_event', 'vgt_perf_strmout_stalled', 'vgt_perf_te11_con_starved_after_work', 'vgt_perf_te11_starved', 'vgt_perf_total_cache_hits', 'vgt_perf_vgt_busy', 'vgt_perf_vgt_gs_busy', 'vgt_perf_vgt_hs_busy', 'vgt_perf_vgt_pa_clipp_eopg', 'vgt_perf_vgt_pa_clipp_send_not_event', 'vgt_perf_vgt_pa_clipp_starved_after_work', 'vgt_perf_vgt_pa_clipp_valid_prim', 'vgt_perf_vgt_te11_busy', 'vgt_perf_vs_cache_hits', 'vgt_perf_vs_conflicting_indices', 'vgt_perf_vs_table_high_water_mark', 'vgt_perf_vs_thread_groups', 'vgt_perf_vsfetch_done', 'vgt_perf_vsvert_api_send', 'vgt_perf_vsvert_ds_send', 'vgt_perf_vsvert_work_received', 'vgt_perf_wait_for_es_done_stalled', 'vgt_perf_waveid_stalled', 'vgt_spi_vsvert_valid', 'wd_perf_RBIU_DI_FIFO_STALLED', 'wd_perf_RBIU_DI_FIFO_STARVED', 'wd_perf_RBIU_DR_FIFO_STALLED', 'wd_perf_RBIU_DR_FIFO_STARVED', 'wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE', 'wd_perf_hs_done_se0', 'wd_perf_hs_done_se1', 'wd_perf_hs_done_se2', 'wd_perf_hs_done_se3', 'wd_perf_inside_tf_bin_0', 'wd_perf_inside_tf_bin_1', 'wd_perf_inside_tf_bin_2', 'wd_perf_inside_tf_bin_3', 'wd_perf_inside_tf_bin_4', 'wd_perf_inside_tf_bin_5', 'wd_perf_inside_tf_bin_6', 'wd_perf_inside_tf_bin_7', 'wd_perf_inside_tf_bin_8', 'wd_perf_null_patches', 'wd_perf_se0_hs_done_latency', 'wd_perf_se1_hs_done_latency', 'wd_perf_se2_hs_done_latency', 'wd_perf_se3_hs_done_latency', 'wd_perf_tfreq_lat_bin_0', 'wd_perf_tfreq_lat_bin_1', 'wd_perf_tfreq_lat_bin_2', 'wd_perf_tfreq_lat_bin_3', 'wd_perf_tfreq_lat_bin_4', 'wd_perf_tfreq_lat_bin_5', 'wd_perf_tfreq_lat_bin_6', 'wd_perf_tfreq_lat_bin_7', 'wd_perf_wd_busy', 'wd_perf_wd_sclk_core_vld_event', 'wd_perf_wd_sclk_input_vld_event', 'wd_perf_wd_sclk_reg_vld_event', 'wd_perf_wd_stalled', 'wd_starved_on_hs_done']