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52 lines
1.4 KiB
52 lines
1.4 KiB
We have to figure out how to make the tinygrad ops match to hw.
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Generic folded reduce may not work.
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GPUs:
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AMD:
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RDNA2: https://developer.amd.com/wp-content/resources/RDNA2_Shader_ISA_November2020.pdf
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We have RX6900XT with 80 CU, 40 WGP, and 1 "processor"
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@ 1.825 GHz, there's 18,688 FP32 GFLOPS of compute. 10240 FLOPS/cycle, 128 per CU (32 FMAs per vALU, 2 per compute unit)
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286 GFLOP for ENET=2 BS=64. At theoretical max, (286/18688)*1000 = 15.3 ms.
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We observe about 10x factor off with pytorch.
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We will focus on speed for AMD, since we have complete docs for that GPU.
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Each "processor" has an "ultra threaded dispatch processor"
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Each SIMD unit has 256 vector registers (or 1024?), and operates on 32 at once.
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Ahh, I think there's 1024 total, but only 256 per wavefront
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M1:
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On M1 GPU, theoretical is 2.275 TFLOPS. https://www.notebookcheck.net/Apple-M1-GPU-Benchmarks-and-Specs.503610.0.html
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We observe 2000ms for BS=8 (37 GFLOP). 37/2275 = 11.9 ms. tinygrad is over a factor of 100x off (similar on AMD GPU)
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NOTE: the timer in the M1 OpenCL doesn't seem to be anywhere close to wall time.
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Adreno:
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TBD, no comma three here. Image > Buffer because the L1 cache is used. Would UBWC help on weights?
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We have a good bit of work on this in hyperthneed. Let's get the disassembler out and make this fast.
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TPUs:
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These use really big systolic arrays and have a lot less flexibility.
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IIRC, their vector math unit is similar to the GPU.
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