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openpilot is an open source driver assistance system. openpilot performs the functions of Automated Lane Centering and Adaptive Cruise Control for over 200 supported car makes and models.
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openpilot_comma/tinygrad_repo/tinygrad/runtime/autogen/am/navi10.py

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# mypy: ignore-errors
# -*- coding: utf-8 -*-
#
# TARGET arch is: []
# WORD_SIZE is: 8
# POINTER_SIZE is: 8
# LONGDOUBLE_SIZE is: 16
#
import ctypes
_navi10_ENUM_HEADER = True # macro
ENUMS_GDS_PERFCOUNT_SELECT_H = True # macro
SQ_WAVE_TYPE_PS0 = 0x00000000 # macro
SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro
SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro
SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro
SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro
SQIND_WAVE_HWREGS_OFFSET = 0x00000100 # macro
SQIND_WAVE_HWREGS_SIZE = 0x00000100 # macro
SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro
SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro
SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro
SQIND_WAVE_VGPRS_SIZE = 0x00000400 # macro
SQ_GFXDEC_BEGIN = 0x0000a000 # macro
SQ_GFXDEC_END = 0x0000c000 # macro
SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro
SQDEC_BEGIN = 0x00002300 # macro
SQDEC_END = 0x000023ff # macro
SQPERFSDEC_BEGIN = 0x0000d9c0 # macro
SQPERFSDEC_END = 0x0000da40 # macro
SQPERFDDEC_BEGIN = 0x0000d1c0 # macro
SQPERFDDEC_END = 0x0000d240 # macro
SQGFXUDEC_BEGIN = 0x0000c330 # macro
SQGFXUDEC_END = 0x0000c380 # macro
SQPWRDEC_BEGIN = 0x0000f08c # macro
SQPWRDEC_END = 0x0000f094 # macro
SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro
SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro
SQ_MAX_PGM_SGPRS = 0x00000068 # macro
SQ_MAX_PGM_VGPRS = 0x00000100 # macro
SQ_EX_MODE_EXCP_VALU_BASE = 0x00000000 # macro
SQ_EX_MODE_EXCP_VALU_SIZE = 0x00000007 # macro
SQ_EX_MODE_EXCP_INVALID = 0x00000000 # macro
SQ_EX_MODE_EXCP_INPUT_DENORM = 0x00000001 # macro
SQ_EX_MODE_EXCP_DIV0 = 0x00000002 # macro
SQ_EX_MODE_EXCP_OVERFLOW = 0x00000003 # macro
SQ_EX_MODE_EXCP_UNDERFLOW = 0x00000004 # macro
SQ_EX_MODE_EXCP_INEXACT = 0x00000005 # macro
SQ_EX_MODE_EXCP_INT_DIV0 = 0x00000006 # macro
SQ_EX_MODE_EXCP_ADDR_WATCH0 = 0x00000007 # macro
SQ_EX_MODE_EXCP_MEM_VIOL = 0x00000008 # macro
SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 = 0x00000000 # macro
SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 = 0x00000001 # macro
SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 = 0x00000002 # macro
INST_ID_PRIV_START = 0x80000000 # macro
INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro
INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro
INST_ID_HW_TRAP = 0xfffffff2 # macro
INST_ID_KILL_SEQ = 0xfffffff3 # macro
INST_ID_SPI_WREXEC = 0xfffffff4 # macro
INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro
SIMM16_WAITCNT_VM_CNT_START = 0x00000000 # macro
SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000004 # macro
SIMM16_WAITCNT_EXP_CNT_START = 0x00000004 # macro
SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro
SIMM16_WAITCNT_LGKM_CNT_START = 0x00000008 # macro
SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000004 # macro
SIMM16_WAITCNT_VM_CNT_HI_START = 0x0000000e # macro
SIMM16_WAITCNT_VM_CNT_HI_SIZE = 0x00000002 # macro
SIMM16_WAITCNT_DEPCTR_SA_SDST_START = 0x00000000 # macro
SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VA_VCC_START = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VM_VSRC_START = 0x00000002 # macro
SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE = 0x00000003 # macro
SIMM16_WAITCNT_DEPCTR_VA_SSRC_START = 0x00000008 # macro
SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VA_SDST_START = 0x00000009 # macro
SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE = 0x00000003 # macro
SIMM16_WAITCNT_DEPCTR_VA_VDST_START = 0x0000000c # macro
SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE = 0x00000004 # macro
SQ_EDC_FUE_CNTL_SIMD0 = 0x00000000 # macro
SQ_EDC_FUE_CNTL_SIMD1 = 0x00000001 # macro
SQ_EDC_FUE_CNTL_SIMD2 = 0x00000002 # macro
SQ_EDC_FUE_CNTL_SIMD3 = 0x00000003 # macro
SQ_EDC_FUE_CNTL_SQ = 0x00000004 # macro
SQ_EDC_FUE_CNTL_LDS = 0x00000005 # macro
SQ_EDC_FUE_CNTL_TD = 0x00000006 # macro
SQ_EDC_FUE_CNTL_TA = 0x00000007 # macro
SQ_EDC_FUE_CNTL_TCP = 0x00000008 # macro
CSDATA_TYPE_WIDTH = 0x00000002 # macro
CSDATA_ADDR_WIDTH = 0x00000007 # macro
CSDATA_DATA_WIDTH = 0x00000020 # macro
CSCNTL_TYPE_WIDTH = 0x00000002 # macro
CSCNTL_ADDR_WIDTH = 0x00000007 # macro
CSCNTL_DATA_WIDTH = 0x00000020 # macro
GSTHREADID_SIZE = 0x00000002 # macro
SEM_ECC_ERROR = 0x00000000 # macro
SEM_TRANS_ERROR = 0x00000001 # macro
SEM_RESP_FAILED = 0x00000002 # macro
SEM_RESP_PASSED = 0x00000003 # macro
IQ_QUEUE_SLEEP = 0x00000000 # macro
IQ_OFFLOAD_RETRY = 0x00000001 # macro
IQ_SCH_WAVE_MSG = 0x00000002 # macro
IQ_SEM_REARM = 0x00000003 # macro
IQ_DEQUEUE_RETRY = 0x00000004 # macro
IQ_INTR_TYPE_PQ = 0x00000000 # macro
IQ_INTR_TYPE_IB = 0x00000001 # macro
IQ_INTR_TYPE_MQD = 0x00000002 # macro
VMID_SZ = 0x00000004 # macro
CONFIG_SPACE_START = 0x00002000 # macro
CONFIG_SPACE_END = 0x00009fff # macro
CONFIG_SPACE1_START = 0x00002000 # macro
CONFIG_SPACE1_END = 0x00002bff # macro
CONFIG_SPACE2_START = 0x00003000 # macro
CONFIG_SPACE2_END = 0x00009fff # macro
UCONFIG_SPACE_START = 0x0000c000 # macro
UCONFIG_SPACE_END = 0x0000ffff # macro
PERSISTENT_SPACE_START = 0x00002c00 # macro
PERSISTENT_SPACE_END = 0x00002fff # macro
CONTEXT_SPACE_START = 0x0000a000 # macro
CONTEXT_SPACE_END = 0x0000bfff # macro
ROM_SIGNATURE = 0x0000aa55 # macro
IP_USB_PD_REVISION_ID = 0x00000000 # macro
# values for enumeration 'GDS_PERFCOUNT_SELECT'
GDS_PERFCOUNT_SELECT__enumvalues = {
0: 'GDS_PERF_SEL_DS_ADDR_CONFL',
1: 'GDS_PERF_SEL_DS_BANK_CONFL',
2: 'GDS_PERF_SEL_WBUF_FLUSH',
3: 'GDS_PERF_SEL_WR_COMP',
4: 'GDS_PERF_SEL_WBUF_WR',
5: 'GDS_PERF_SEL_RBUF_HIT',
6: 'GDS_PERF_SEL_RBUF_MISS',
7: 'GDS_PERF_SEL_SE0_SH0_NORET',
8: 'GDS_PERF_SEL_SE0_SH0_RET',
9: 'GDS_PERF_SEL_SE0_SH0_ORD_CNT',
10: 'GDS_PERF_SEL_SE0_SH0_2COMP_REQ',
11: 'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID',
12: 'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID',
13: 'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD',
14: 'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP',
15: 'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP',
16: 'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP',
17: 'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP',
18: 'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP',
19: 'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP',
20: 'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP',
21: 'GDS_PERF_SEL_SE0_SH1_NORET',
22: 'GDS_PERF_SEL_SE0_SH1_RET',
23: 'GDS_PERF_SEL_SE0_SH1_ORD_CNT',
24: 'GDS_PERF_SEL_SE0_SH1_2COMP_REQ',
25: 'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID',
26: 'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID',
27: 'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD',
28: 'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP',
29: 'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP',
30: 'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP',
31: 'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP',
32: 'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP',
33: 'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP',
34: 'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP',
35: 'GDS_PERF_SEL_SE1_SH0_NORET',
36: 'GDS_PERF_SEL_SE1_SH0_RET',
37: 'GDS_PERF_SEL_SE1_SH0_ORD_CNT',
38: 'GDS_PERF_SEL_SE1_SH0_2COMP_REQ',
39: 'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID',
40: 'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID',
41: 'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD',
42: 'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP',
43: 'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP',
44: 'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP',
45: 'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP',
46: 'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP',
47: 'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP',
48: 'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP',
49: 'GDS_PERF_SEL_SE1_SH1_NORET',
50: 'GDS_PERF_SEL_SE1_SH1_RET',
51: 'GDS_PERF_SEL_SE1_SH1_ORD_CNT',
52: 'GDS_PERF_SEL_SE1_SH1_2COMP_REQ',
53: 'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID',
54: 'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID',
55: 'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD',
56: 'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP',
57: 'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP',
58: 'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP',
59: 'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP',
60: 'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP',
61: 'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP',
62: 'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP',
63: 'GDS_PERF_SEL_SE2_SH0_NORET',
64: 'GDS_PERF_SEL_SE2_SH0_RET',
65: 'GDS_PERF_SEL_SE2_SH0_ORD_CNT',
66: 'GDS_PERF_SEL_SE2_SH0_2COMP_REQ',
67: 'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID',
68: 'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID',
69: 'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD',
70: 'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP',
71: 'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP',
72: 'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP',
73: 'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP',
74: 'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP',
75: 'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP',
76: 'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP',
77: 'GDS_PERF_SEL_SE2_SH1_NORET',
78: 'GDS_PERF_SEL_SE2_SH1_RET',
79: 'GDS_PERF_SEL_SE2_SH1_ORD_CNT',
80: 'GDS_PERF_SEL_SE2_SH1_2COMP_REQ',
81: 'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID',
82: 'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID',
83: 'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD',
84: 'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP',
85: 'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP',
86: 'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP',
87: 'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP',
88: 'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP',
89: 'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP',
90: 'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP',
91: 'GDS_PERF_SEL_SE3_SH0_NORET',
92: 'GDS_PERF_SEL_SE3_SH0_RET',
93: 'GDS_PERF_SEL_SE3_SH0_ORD_CNT',
94: 'GDS_PERF_SEL_SE3_SH0_2COMP_REQ',
95: 'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID',
96: 'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID',
97: 'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD',
98: 'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP',
99: 'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP',
100: 'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP',
101: 'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP',
102: 'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP',
103: 'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP',
104: 'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP',
105: 'GDS_PERF_SEL_SE3_SH1_NORET',
106: 'GDS_PERF_SEL_SE3_SH1_RET',
107: 'GDS_PERF_SEL_SE3_SH1_ORD_CNT',
108: 'GDS_PERF_SEL_SE3_SH1_2COMP_REQ',
109: 'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID',
110: 'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID',
111: 'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD',
112: 'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP',
113: 'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP',
114: 'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP',
115: 'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP',
116: 'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP',
117: 'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP',
118: 'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP',
119: 'GDS_PERF_SEL_GWS_RELEASED',
120: 'GDS_PERF_SEL_GWS_BYPASS',
}
GDS_PERF_SEL_DS_ADDR_CONFL = 0
GDS_PERF_SEL_DS_BANK_CONFL = 1
GDS_PERF_SEL_WBUF_FLUSH = 2
GDS_PERF_SEL_WR_COMP = 3
GDS_PERF_SEL_WBUF_WR = 4
GDS_PERF_SEL_RBUF_HIT = 5
GDS_PERF_SEL_RBUF_MISS = 6
GDS_PERF_SEL_SE0_SH0_NORET = 7
GDS_PERF_SEL_SE0_SH0_RET = 8
GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9
GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10
GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11
GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12
GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13
GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14
GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15
GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16
GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17
GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18
GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19
GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20
GDS_PERF_SEL_SE0_SH1_NORET = 21
GDS_PERF_SEL_SE0_SH1_RET = 22
GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23
GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24
GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25
GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26
GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27
GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28
GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29
GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30
GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31
GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32
GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33
GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34
GDS_PERF_SEL_SE1_SH0_NORET = 35
GDS_PERF_SEL_SE1_SH0_RET = 36
GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37
GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38
GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39
GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40
GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41
GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42
GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43
GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44
GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45
GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46
GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47
GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48
GDS_PERF_SEL_SE1_SH1_NORET = 49
GDS_PERF_SEL_SE1_SH1_RET = 50
GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51
GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52
GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53
GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54
GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55
GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56
GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57
GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58
GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59
GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60
GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61
GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62
GDS_PERF_SEL_SE2_SH0_NORET = 63
GDS_PERF_SEL_SE2_SH0_RET = 64
GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65
GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66
GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67
GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68
GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69
GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70
GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71
GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72
GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73
GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74
GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75
GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76
GDS_PERF_SEL_SE2_SH1_NORET = 77
GDS_PERF_SEL_SE2_SH1_RET = 78
GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79
GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80
GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81
GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82
GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83
GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84
GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85
GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86
GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87
GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88
GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89
GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90
GDS_PERF_SEL_SE3_SH0_NORET = 91
GDS_PERF_SEL_SE3_SH0_RET = 92
GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93
GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94
GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95
GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96
GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97
GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98
GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99
GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100
GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101
GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102
GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103
GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104
GDS_PERF_SEL_SE3_SH1_NORET = 105
GDS_PERF_SEL_SE3_SH1_RET = 106
GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107
GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108
GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109
GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110
GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111
GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112
GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113
GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114
GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115
GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116
GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117
GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118
GDS_PERF_SEL_GWS_RELEASED = 119
GDS_PERF_SEL_GWS_BYPASS = 120
GDS_PERFCOUNT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'GATCL1RequestType'
GATCL1RequestType__enumvalues = {
0: 'GATCL1_TYPE_NORMAL',
1: 'GATCL1_TYPE_SHOOTDOWN',
2: 'GATCL1_TYPE_BYPASS',
}
GATCL1_TYPE_NORMAL = 0
GATCL1_TYPE_SHOOTDOWN = 1
GATCL1_TYPE_BYPASS = 2
GATCL1RequestType = ctypes.c_uint32 # enum
# values for enumeration 'UTCL1RequestType'
UTCL1RequestType__enumvalues = {
0: 'UTCL1_TYPE_NORMAL',
1: 'UTCL1_TYPE_SHOOTDOWN',
2: 'UTCL1_TYPE_BYPASS',
}
UTCL1_TYPE_NORMAL = 0
UTCL1_TYPE_SHOOTDOWN = 1
UTCL1_TYPE_BYPASS = 2
UTCL1RequestType = ctypes.c_uint32 # enum
# values for enumeration 'UTCL1FaultType'
UTCL1FaultType__enumvalues = {
0: 'UTCL1_XNACK_SUCCESS',
1: 'UTCL1_XNACK_RETRY',
2: 'UTCL1_XNACK_PRT',
3: 'UTCL1_XNACK_NO_RETRY',
}
UTCL1_XNACK_SUCCESS = 0
UTCL1_XNACK_RETRY = 1
UTCL1_XNACK_PRT = 2
UTCL1_XNACK_NO_RETRY = 3
UTCL1FaultType = ctypes.c_uint32 # enum
# values for enumeration 'UTCL0RequestType'
UTCL0RequestType__enumvalues = {
0: 'UTCL0_TYPE_NORMAL',
1: 'UTCL0_TYPE_SHOOTDOWN',
2: 'UTCL0_TYPE_BYPASS',
}
UTCL0_TYPE_NORMAL = 0
UTCL0_TYPE_SHOOTDOWN = 1
UTCL0_TYPE_BYPASS = 2
UTCL0RequestType = ctypes.c_uint32 # enum
# values for enumeration 'UTCL0FaultType'
UTCL0FaultType__enumvalues = {
0: 'UTCL0_XNACK_SUCCESS',
1: 'UTCL0_XNACK_RETRY',
2: 'UTCL0_XNACK_PRT',
3: 'UTCL0_XNACK_NO_RETRY',
}
UTCL0_XNACK_SUCCESS = 0
UTCL0_XNACK_RETRY = 1
UTCL0_XNACK_PRT = 2
UTCL0_XNACK_NO_RETRY = 3
UTCL0FaultType = ctypes.c_uint32 # enum
# values for enumeration 'VMEMCMD_RETURN_ORDER'
VMEMCMD_RETURN_ORDER__enumvalues = {
0: 'VMEMCMD_RETURN_OUT_OF_ORDER',
1: 'VMEMCMD_RETURN_IN_ORDER',
2: 'VMEMCMD_RETURN_IN_ORDER_READ',
}
VMEMCMD_RETURN_OUT_OF_ORDER = 0
VMEMCMD_RETURN_IN_ORDER = 1
VMEMCMD_RETURN_IN_ORDER_READ = 2
VMEMCMD_RETURN_ORDER = ctypes.c_uint32 # enum
# values for enumeration 'GL0V_CACHE_POLICIES'
GL0V_CACHE_POLICIES__enumvalues = {
0: 'GL0V_CACHE_POLICY_MISS_LRU',
1: 'GL0V_CACHE_POLICY_MISS_EVICT',
2: 'GL0V_CACHE_POLICY_HIT_LRU',
3: 'GL0V_CACHE_POLICY_HIT_EVICT',
}
GL0V_CACHE_POLICY_MISS_LRU = 0
GL0V_CACHE_POLICY_MISS_EVICT = 1
GL0V_CACHE_POLICY_HIT_LRU = 2
GL0V_CACHE_POLICY_HIT_EVICT = 3
GL0V_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'GL1_CACHE_POLICIES'
GL1_CACHE_POLICIES__enumvalues = {
0: 'GL1_CACHE_POLICY_MISS_LRU',
1: 'GL1_CACHE_POLICY_MISS_EVICT',
2: 'GL1_CACHE_POLICY_HIT_LRU',
3: 'GL1_CACHE_POLICY_HIT_EVICT',
}
GL1_CACHE_POLICY_MISS_LRU = 0
GL1_CACHE_POLICY_MISS_EVICT = 1
GL1_CACHE_POLICY_HIT_LRU = 2
GL1_CACHE_POLICY_HIT_EVICT = 3
GL1_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'GL1_CACHE_STORE_POLICIES'
GL1_CACHE_STORE_POLICIES__enumvalues = {
0: 'GL1_CACHE_STORE_POLICY_BYPASS',
}
GL1_CACHE_STORE_POLICY_BYPASS = 0
GL1_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'TCC_CACHE_POLICIES'
TCC_CACHE_POLICIES__enumvalues = {
0: 'TCC_CACHE_POLICY_LRU',
1: 'TCC_CACHE_POLICY_STREAM',
}
TCC_CACHE_POLICY_LRU = 0
TCC_CACHE_POLICY_STREAM = 1
TCC_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'TCC_MTYPE'
TCC_MTYPE__enumvalues = {
0: 'MTYPE_NC',
1: 'MTYPE_WC',
2: 'MTYPE_CC',
}
MTYPE_NC = 0
MTYPE_WC = 1
MTYPE_CC = 2
TCC_MTYPE = ctypes.c_uint32 # enum
# values for enumeration 'GL2_CACHE_POLICIES'
GL2_CACHE_POLICIES__enumvalues = {
0: 'GL2_CACHE_POLICY_LRU',
1: 'GL2_CACHE_POLICY_STREAM',
2: 'GL2_CACHE_POLICY_NOA',
3: 'GL2_CACHE_POLICY_BYPASS',
}
GL2_CACHE_POLICY_LRU = 0
GL2_CACHE_POLICY_STREAM = 1
GL2_CACHE_POLICY_NOA = 2
GL2_CACHE_POLICY_BYPASS = 3
GL2_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'MTYPE'
MTYPE__enumvalues = {
0: 'MTYPE_C_RW_US',
1: 'MTYPE_RESERVED_1',
2: 'MTYPE_C_RO_S',
3: 'MTYPE_UC',
4: 'MTYPE_C_RW_S',
5: 'MTYPE_RESERVED_5',
6: 'MTYPE_C_RO_US',
7: 'MTYPE_RESERVED_7',
}
MTYPE_C_RW_US = 0
MTYPE_RESERVED_1 = 1
MTYPE_C_RO_S = 2
MTYPE_UC = 3
MTYPE_C_RW_S = 4
MTYPE_RESERVED_5 = 5
MTYPE_C_RO_US = 6
MTYPE_RESERVED_7 = 7
MTYPE = ctypes.c_uint32 # enum
# values for enumeration 'RMI_CID'
RMI_CID__enumvalues = {
0: 'RMI_CID_CC',
1: 'RMI_CID_FC',
2: 'RMI_CID_CM',
3: 'RMI_CID_DC',
4: 'RMI_CID_Z',
5: 'RMI_CID_S',
6: 'RMI_CID_TILE',
7: 'RMI_CID_ZPCPSD',
}
RMI_CID_CC = 0
RMI_CID_FC = 1
RMI_CID_CM = 2
RMI_CID_DC = 3
RMI_CID_Z = 4
RMI_CID_S = 5
RMI_CID_TILE = 6
RMI_CID_ZPCPSD = 7
RMI_CID = ctypes.c_uint32 # enum
# values for enumeration 'WritePolicy'
WritePolicy__enumvalues = {
0: 'CACHE_LRU_WR',
1: 'CACHE_STREAM',
2: 'CACHE_BYPASS',
3: 'UNCACHED_WR',
}
CACHE_LRU_WR = 0
CACHE_STREAM = 1
CACHE_BYPASS = 2
UNCACHED_WR = 3
WritePolicy = ctypes.c_uint32 # enum
# values for enumeration 'ReadPolicy'
ReadPolicy__enumvalues = {
0: 'CACHE_LRU_RD',
1: 'CACHE_NOA',
2: 'UNCACHED_RD',
3: 'RESERVED_RDPOLICY',
}
CACHE_LRU_RD = 0
CACHE_NOA = 1
UNCACHED_RD = 2
RESERVED_RDPOLICY = 3
ReadPolicy = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_COUNTER_MODE'
PERFMON_COUNTER_MODE__enumvalues = {
0: 'PERFMON_COUNTER_MODE_ACCUM',
1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES',
2: 'PERFMON_COUNTER_MODE_MAX',
3: 'PERFMON_COUNTER_MODE_DIRTY',
4: 'PERFMON_COUNTER_MODE_SAMPLE',
5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT',
6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT',
7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI',
8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI',
9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES',
15: 'PERFMON_COUNTER_MODE_RESERVED',
}
PERFMON_COUNTER_MODE_ACCUM = 0
PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1
PERFMON_COUNTER_MODE_MAX = 2
PERFMON_COUNTER_MODE_DIRTY = 3
PERFMON_COUNTER_MODE_SAMPLE = 4
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6
PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7
PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8
PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9
PERFMON_COUNTER_MODE_RESERVED = 15
PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_SPM_MODE'
PERFMON_SPM_MODE__enumvalues = {
0: 'PERFMON_SPM_MODE_OFF',
1: 'PERFMON_SPM_MODE_16BIT_CLAMP',
2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP',
3: 'PERFMON_SPM_MODE_32BIT_CLAMP',
4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP',
5: 'PERFMON_SPM_MODE_RESERVED_5',
6: 'PERFMON_SPM_MODE_RESERVED_6',
7: 'PERFMON_SPM_MODE_RESERVED_7',
8: 'PERFMON_SPM_MODE_TEST_MODE_0',
9: 'PERFMON_SPM_MODE_TEST_MODE_1',
10: 'PERFMON_SPM_MODE_TEST_MODE_2',
}
PERFMON_SPM_MODE_OFF = 0
PERFMON_SPM_MODE_16BIT_CLAMP = 1
PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2
PERFMON_SPM_MODE_32BIT_CLAMP = 3
PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4
PERFMON_SPM_MODE_RESERVED_5 = 5
PERFMON_SPM_MODE_RESERVED_6 = 6
PERFMON_SPM_MODE_RESERVED_7 = 7
PERFMON_SPM_MODE_TEST_MODE_0 = 8
PERFMON_SPM_MODE_TEST_MODE_1 = 9
PERFMON_SPM_MODE_TEST_MODE_2 = 10
PERFMON_SPM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SurfaceTiling'
SurfaceTiling__enumvalues = {
0: 'ARRAY_LINEAR',
1: 'ARRAY_TILED',
}
ARRAY_LINEAR = 0
ARRAY_TILED = 1
SurfaceTiling = ctypes.c_uint32 # enum
# values for enumeration 'SurfaceArray'
SurfaceArray__enumvalues = {
0: 'ARRAY_1D',
1: 'ARRAY_2D',
2: 'ARRAY_3D',
3: 'ARRAY_3D_SLICE',
}
ARRAY_1D = 0
ARRAY_2D = 1
ARRAY_3D = 2
ARRAY_3D_SLICE = 3
SurfaceArray = ctypes.c_uint32 # enum
# values for enumeration 'ColorArray'
ColorArray__enumvalues = {
0: 'ARRAY_2D_ALT_COLOR',
1: 'ARRAY_2D_COLOR',
3: 'ARRAY_3D_SLICE_COLOR',
}
ARRAY_2D_ALT_COLOR = 0
ARRAY_2D_COLOR = 1
ARRAY_3D_SLICE_COLOR = 3
ColorArray = ctypes.c_uint32 # enum
# values for enumeration 'DepthArray'
DepthArray__enumvalues = {
0: 'ARRAY_2D_ALT_DEPTH',
1: 'ARRAY_2D_DEPTH',
}
ARRAY_2D_ALT_DEPTH = 0
ARRAY_2D_DEPTH = 1
DepthArray = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_NUM_SIMD_PER_CU'
ENUM_NUM_SIMD_PER_CU__enumvalues = {
2: 'NUM_SIMD_PER_CU',
}
NUM_SIMD_PER_CU = 2
ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum
# values for enumeration 'DSM_ENABLE_ERROR_INJECT'
DSM_ENABLE_ERROR_INJECT__enumvalues = {
0: 'DSM_ENABLE_ERROR_INJECT_FED_IN',
1: 'DSM_ENABLE_ERROR_INJECT_SINGLE',
2: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE',
3: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED',
}
DSM_ENABLE_ERROR_INJECT_FED_IN = 0
DSM_ENABLE_ERROR_INJECT_SINGLE = 1
DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 2
DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 3
DSM_ENABLE_ERROR_INJECT = ctypes.c_uint32 # enum
# values for enumeration 'DSM_SELECT_INJECT_DELAY'
DSM_SELECT_INJECT_DELAY__enumvalues = {
0: 'DSM_SELECT_INJECT_DELAY_NO_DELAY',
1: 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR',
}
DSM_SELECT_INJECT_DELAY_NO_DELAY = 0
DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 1
DSM_SELECT_INJECT_DELAY = ctypes.c_uint32 # enum
# values for enumeration 'DSM_DATA_SEL'
DSM_DATA_SEL__enumvalues = {
0: 'DSM_DATA_SEL_DISABLE',
1: 'DSM_DATA_SEL_0',
2: 'DSM_DATA_SEL_1',
3: 'DSM_DATA_SEL_BOTH',
}
DSM_DATA_SEL_DISABLE = 0
DSM_DATA_SEL_0 = 1
DSM_DATA_SEL_1 = 2
DSM_DATA_SEL_BOTH = 3
DSM_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DSM_SINGLE_WRITE'
DSM_SINGLE_WRITE__enumvalues = {
0: 'DSM_SINGLE_WRITE_DIS',
1: 'DSM_SINGLE_WRITE_EN',
}
DSM_SINGLE_WRITE_DIS = 0
DSM_SINGLE_WRITE_EN = 1
DSM_SINGLE_WRITE = ctypes.c_uint32 # enum
# values for enumeration 'Hdp_SurfaceEndian'
Hdp_SurfaceEndian__enumvalues = {
0: 'HDP_ENDIAN_NONE',
1: 'HDP_ENDIAN_8IN16',
2: 'HDP_ENDIAN_8IN32',
3: 'HDP_ENDIAN_8IN64',
}
HDP_ENDIAN_NONE = 0
HDP_ENDIAN_8IN16 = 1
HDP_ENDIAN_8IN32 = 2
HDP_ENDIAN_8IN64 = 3
Hdp_SurfaceEndian = ctypes.c_uint32 # enum
# values for enumeration 'CNVC_ENABLE'
CNVC_ENABLE__enumvalues = {
0: 'CNVC_DIS',
1: 'CNVC_EN',
}
CNVC_DIS = 0
CNVC_EN = 1
CNVC_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'CNVC_BYPASS'
CNVC_BYPASS__enumvalues = {
0: 'CNVC_BYPASS_DISABLE',
1: 'CNVC_BYPASS_EN',
}
CNVC_BYPASS_DISABLE = 0
CNVC_BYPASS_EN = 1
CNVC_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'CNVC_PENDING'
CNVC_PENDING__enumvalues = {
0: 'CNVC_NOT_PENDING',
1: 'CNVC_YES_PENDING',
}
CNVC_NOT_PENDING = 0
CNVC_YES_PENDING = 1
CNVC_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'DENORM_TRUNCATE'
DENORM_TRUNCATE__enumvalues = {
0: 'CNVC_ROUND',
1: 'CNVC_TRUNCATE',
}
CNVC_ROUND = 0
CNVC_TRUNCATE = 1
DENORM_TRUNCATE = ctypes.c_uint32 # enum
# values for enumeration 'PIX_EXPAND_MODE'
PIX_EXPAND_MODE__enumvalues = {
0: 'PIX_DYNAMIC_EXPANSION',
1: 'PIX_ZERO_EXPANSION',
}
PIX_DYNAMIC_EXPANSION = 0
PIX_ZERO_EXPANSION = 1
PIX_EXPAND_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_PIXEL_FORMAT'
SURFACE_PIXEL_FORMAT__enumvalues = {
1: 'ARGB1555',
2: 'RGBA5551',
3: 'RGB565',
4: 'BGR565',
5: 'ARGB4444',
6: 'RGBA4444',
8: 'ARGB8888',
9: 'RGBA8888',
10: 'ARGB2101010',
11: 'RGBA1010102',
12: 'AYCrCb8888',
13: 'YCrCbA8888',
14: 'ACrYCb8888',
15: 'CrYCbA8888',
16: 'ARGB16161616_10MSB',
17: 'RGBA16161616_10MSB',
18: 'ARGB16161616_10LSB',
19: 'RGBA16161616_10LSB',
20: 'ARGB16161616_12MSB',
21: 'RGBA16161616_12MSB',
22: 'ARGB16161616_12LSB',
23: 'RGBA16161616_12LSB',
24: 'ARGB16161616_FLOAT',
25: 'RGBA16161616_FLOAT',
26: 'ARGB16161616_UNORM',
27: 'RGBA16161616_UNORM',
28: 'ARGB16161616_SNORM',
29: 'RGBA16161616_SNORM',
32: 'AYCrCb16161616_10MSB',
33: 'AYCrCb16161616_10LSB',
34: 'YCrCbA16161616_10MSB',
35: 'YCrCbA16161616_10LSB',
36: 'ACrYCb16161616_10MSB',
37: 'ACrYCb16161616_10LSB',
38: 'CrYCbA16161616_10MSB',
39: 'CrYCbA16161616_10LSB',
40: 'AYCrCb16161616_12MSB',
41: 'AYCrCb16161616_12LSB',
42: 'YCrCbA16161616_12MSB',
43: 'YCrCbA16161616_12LSB',
44: 'ACrYCb16161616_12MSB',
45: 'ACrYCb16161616_12LSB',
46: 'CrYCbA16161616_12MSB',
47: 'CrYCbA16161616_12LSB',
64: 'Y8_CrCb88_420_PLANAR',
65: 'Y8_CbCr88_420_PLANAR',
66: 'Y10_CrCb1010_420_PLANAR',
67: 'Y10_CbCr1010_420_PLANAR',
68: 'Y12_CrCb1212_420_PLANAR',
69: 'Y12_CbCr1212_420_PLANAR',
72: 'YCrYCb8888_422_PACKED',
73: 'YCbYCr8888_422_PACKED',
74: 'CrYCbY8888_422_PACKED',
75: 'CbYCrY8888_422_PACKED',
76: 'YCrYCb10101010_422_PACKED',
77: 'YCbYCr10101010_422_PACKED',
78: 'CrYCbY10101010_422_PACKED',
79: 'CbYCrY10101010_422_PACKED',
80: 'YCrYCb12121212_422_PACKED',
81: 'YCbYCr12121212_422_PACKED',
82: 'CrYCbY12121212_422_PACKED',
83: 'CbYCrY12121212_422_PACKED',
112: 'RGB111110_FIX',
113: 'BGR101111_FIX',
114: 'ACrYCb2101010',
115: 'CrYCbA1010102',
118: 'RGB111110_FLOAT',
119: 'BGR101111_FLOAT',
120: 'MONO_8',
121: 'MONO_10MSB',
122: 'MONO_10LSB',
123: 'MONO_12MSB',
124: 'MONO_12LSB',
125: 'MONO_16',
}
ARGB1555 = 1
RGBA5551 = 2
RGB565 = 3
BGR565 = 4
ARGB4444 = 5
RGBA4444 = 6
ARGB8888 = 8
RGBA8888 = 9
ARGB2101010 = 10
RGBA1010102 = 11
AYCrCb8888 = 12
YCrCbA8888 = 13
ACrYCb8888 = 14
CrYCbA8888 = 15
ARGB16161616_10MSB = 16
RGBA16161616_10MSB = 17
ARGB16161616_10LSB = 18
RGBA16161616_10LSB = 19
ARGB16161616_12MSB = 20
RGBA16161616_12MSB = 21
ARGB16161616_12LSB = 22
RGBA16161616_12LSB = 23
ARGB16161616_FLOAT = 24
RGBA16161616_FLOAT = 25
ARGB16161616_UNORM = 26
RGBA16161616_UNORM = 27
ARGB16161616_SNORM = 28
RGBA16161616_SNORM = 29
AYCrCb16161616_10MSB = 32
AYCrCb16161616_10LSB = 33
YCrCbA16161616_10MSB = 34
YCrCbA16161616_10LSB = 35
ACrYCb16161616_10MSB = 36
ACrYCb16161616_10LSB = 37
CrYCbA16161616_10MSB = 38
CrYCbA16161616_10LSB = 39
AYCrCb16161616_12MSB = 40
AYCrCb16161616_12LSB = 41
YCrCbA16161616_12MSB = 42
YCrCbA16161616_12LSB = 43
ACrYCb16161616_12MSB = 44
ACrYCb16161616_12LSB = 45
CrYCbA16161616_12MSB = 46
CrYCbA16161616_12LSB = 47
Y8_CrCb88_420_PLANAR = 64
Y8_CbCr88_420_PLANAR = 65
Y10_CrCb1010_420_PLANAR = 66
Y10_CbCr1010_420_PLANAR = 67
Y12_CrCb1212_420_PLANAR = 68
Y12_CbCr1212_420_PLANAR = 69
YCrYCb8888_422_PACKED = 72
YCbYCr8888_422_PACKED = 73
CrYCbY8888_422_PACKED = 74
CbYCrY8888_422_PACKED = 75
YCrYCb10101010_422_PACKED = 76
YCbYCr10101010_422_PACKED = 77
CrYCbY10101010_422_PACKED = 78
CbYCrY10101010_422_PACKED = 79
YCrYCb12121212_422_PACKED = 80
YCbYCr12121212_422_PACKED = 81
CrYCbY12121212_422_PACKED = 82
CbYCrY12121212_422_PACKED = 83
RGB111110_FIX = 112
BGR101111_FIX = 113
ACrYCb2101010 = 114
CrYCbA1010102 = 115
RGB111110_FLOAT = 118
BGR101111_FLOAT = 119
MONO_8 = 120
MONO_10MSB = 121
MONO_10LSB = 122
MONO_12MSB = 123
MONO_12LSB = 124
MONO_16 = 125
SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'XNORM'
XNORM__enumvalues = {
0: 'XNORM_A',
1: 'XNORM_B',
}
XNORM_A = 0
XNORM_B = 1
XNORM = ctypes.c_uint32 # enum
# values for enumeration 'COLOR_KEYER_MODE'
COLOR_KEYER_MODE__enumvalues = {
0: 'FORCE_00',
1: 'FORCE_FF',
2: 'RANGE_00',
3: 'RANGE_FF',
}
FORCE_00 = 0
FORCE_FF = 1
RANGE_00 = 2
RANGE_FF = 3
COLOR_KEYER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CUR_ENABLE'
CUR_ENABLE__enumvalues = {
0: 'CUR_DIS',
1: 'CUR_EN',
}
CUR_DIS = 0
CUR_EN = 1
CUR_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'CUR_PENDING'
CUR_PENDING__enumvalues = {
0: 'CUR_NOT_PENDING',
1: 'CUR_YES_PENDING',
}
CUR_NOT_PENDING = 0
CUR_YES_PENDING = 1
CUR_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'CUR_EXPAND_MODE'
CUR_EXPAND_MODE__enumvalues = {
0: 'CUR_DYNAMIC_EXPANSION',
1: 'CUR_ZERO_EXPANSION',
}
CUR_DYNAMIC_EXPANSION = 0
CUR_ZERO_EXPANSION = 1
CUR_EXPAND_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CUR_ROM_EN'
CUR_ROM_EN__enumvalues = {
0: 'CUR_FP_NO_ROM',
1: 'CUR_FP_USE_ROM',
}
CUR_FP_NO_ROM = 0
CUR_FP_USE_ROM = 1
CUR_ROM_EN = ctypes.c_uint32 # enum
# values for enumeration 'CUR_MODE'
CUR_MODE__enumvalues = {
0: 'MONO_2BIT',
1: 'COLOR_24BIT_1BIT_AND',
2: 'COLOR_24BIT_8BIT_ALPHA_PREMULT',
3: 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT',
4: 'COLOR_64BIT_FP_PREMULT',
5: 'COLOR_64BIT_FP_UNPREMULT',
}
MONO_2BIT = 0
COLOR_24BIT_1BIT_AND = 1
COLOR_24BIT_8BIT_ALPHA_PREMULT = 2
COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3
COLOR_64BIT_FP_PREMULT = 4
COLOR_64BIT_FP_UNPREMULT = 5
CUR_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CUR_INV_CLAMP'
CUR_INV_CLAMP__enumvalues = {
0: 'CUR_CLAMP_DIS',
1: 'CUR_CLAMP_EN',
}
CUR_CLAMP_DIS = 0
CUR_CLAMP_EN = 1
CUR_INV_CLAMP = ctypes.c_uint32 # enum
# values for enumeration 'SCL_COEF_FILTER_TYPE_SEL'
SCL_COEF_FILTER_TYPE_SEL__enumvalues = {
0: 'SCL_COEF_LUMA_VERT_FILTER',
1: 'SCL_COEF_LUMA_HORZ_FILTER',
2: 'SCL_COEF_CHROMA_VERT_FILTER',
3: 'SCL_COEF_CHROMA_HORZ_FILTER',
4: 'SCL_COEF_ALPHA_VERT_FILTER',
5: 'SCL_COEF_ALPHA_HORZ_FILTER',
}
SCL_COEF_LUMA_VERT_FILTER = 0
SCL_COEF_LUMA_HORZ_FILTER = 1
SCL_COEF_CHROMA_VERT_FILTER = 2
SCL_COEF_CHROMA_HORZ_FILTER = 3
SCL_COEF_ALPHA_VERT_FILTER = 4
SCL_COEF_ALPHA_HORZ_FILTER = 5
SCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DSCL_MODE_SEL'
DSCL_MODE_SEL__enumvalues = {
0: 'DSCL_MODE_SCALING_444_BYPASS',
1: 'DSCL_MODE_SCALING_444_RGB_ENABLE',
2: 'DSCL_MODE_SCALING_444_YCBCR_ENABLE',
3: 'DSCL_MODE_SCALING_YCBCR_ENABLE',
4: 'DSCL_MODE_LUMA_SCALING_BYPASS',
5: 'DSCL_MODE_CHROMA_SCALING_BYPASS',
6: 'DSCL_MODE_DSCL_BYPASS',
}
DSCL_MODE_SCALING_444_BYPASS = 0
DSCL_MODE_SCALING_444_RGB_ENABLE = 1
DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2
DSCL_MODE_SCALING_YCBCR_ENABLE = 3
DSCL_MODE_LUMA_SCALING_BYPASS = 4
DSCL_MODE_CHROMA_SCALING_BYPASS = 5
DSCL_MODE_DSCL_BYPASS = 6
DSCL_MODE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SCL_AUTOCAL_MODE'
SCL_AUTOCAL_MODE__enumvalues = {
0: 'AUTOCAL_MODE_OFF',
1: 'AUTOCAL_MODE_AUTOSCALE',
2: 'AUTOCAL_MODE_AUTOCENTER',
3: 'AUTOCAL_MODE_AUTOREPLICATE',
}
AUTOCAL_MODE_OFF = 0
AUTOCAL_MODE_AUTOSCALE = 1
AUTOCAL_MODE_AUTOCENTER = 2
AUTOCAL_MODE_AUTOREPLICATE = 3
SCL_AUTOCAL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SCL_COEF_RAM_SEL'
SCL_COEF_RAM_SEL__enumvalues = {
0: 'SCL_COEF_RAM_SEL_0',
1: 'SCL_COEF_RAM_SEL_1',
}
SCL_COEF_RAM_SEL_0 = 0
SCL_COEF_RAM_SEL_1 = 1
SCL_COEF_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SCL_CHROMA_COEF'
SCL_CHROMA_COEF__enumvalues = {
0: 'SCL_CHROMA_COEF_LUMA',
1: 'SCL_CHROMA_COEF_CHROMA',
}
SCL_CHROMA_COEF_LUMA = 0
SCL_CHROMA_COEF_CHROMA = 1
SCL_CHROMA_COEF = ctypes.c_uint32 # enum
# values for enumeration 'SCL_ALPHA_COEF'
SCL_ALPHA_COEF__enumvalues = {
0: 'SCL_ALPHA_COEF_LUMA',
1: 'SCL_ALPHA_COEF_ALPHA',
}
SCL_ALPHA_COEF_LUMA = 0
SCL_ALPHA_COEF_ALPHA = 1
SCL_ALPHA_COEF = ctypes.c_uint32 # enum
# values for enumeration 'COEF_RAM_SELECT_RD'
COEF_RAM_SELECT_RD__enumvalues = {
0: 'COEF_RAM_SELECT_BACK',
1: 'COEF_RAM_SELECT_CURRENT',
}
COEF_RAM_SELECT_BACK = 0
COEF_RAM_SELECT_CURRENT = 1
COEF_RAM_SELECT_RD = ctypes.c_uint32 # enum
# values for enumeration 'SCL_2TAP_HARDCODE'
SCL_2TAP_HARDCODE__enumvalues = {
0: 'SCL_COEF_2TAP_HARDCODE_OFF',
1: 'SCL_COEF_2TAP_HARDCODE_ON',
}
SCL_COEF_2TAP_HARDCODE_OFF = 0
SCL_COEF_2TAP_HARDCODE_ON = 1
SCL_2TAP_HARDCODE = ctypes.c_uint32 # enum
# values for enumeration 'SCL_SHARP_EN'
SCL_SHARP_EN__enumvalues = {
0: 'SCL_SHARP_DISABLE',
1: 'SCL_SHARP_ENABLE',
}
SCL_SHARP_DISABLE = 0
SCL_SHARP_ENABLE = 1
SCL_SHARP_EN = ctypes.c_uint32 # enum
# values for enumeration 'SCL_BOUNDARY'
SCL_BOUNDARY__enumvalues = {
0: 'SCL_BOUNDARY_EDGE',
1: 'SCL_BOUNDARY_BLACK',
}
SCL_BOUNDARY_EDGE = 0
SCL_BOUNDARY_BLACK = 1
SCL_BOUNDARY = ctypes.c_uint32 # enum
# values for enumeration 'LB_INTERLEAVE_EN'
LB_INTERLEAVE_EN__enumvalues = {
0: 'LB_INTERLEAVE_DISABLE',
1: 'LB_INTERLEAVE_ENABLE',
}
LB_INTERLEAVE_DISABLE = 0
LB_INTERLEAVE_ENABLE = 1
LB_INTERLEAVE_EN = ctypes.c_uint32 # enum
# values for enumeration 'LB_ALPHA_EN'
LB_ALPHA_EN__enumvalues = {
0: 'LB_ALPHA_DISABLE',
1: 'LB_ALPHA_ENABLE',
}
LB_ALPHA_DISABLE = 0
LB_ALPHA_ENABLE = 1
LB_ALPHA_EN = ctypes.c_uint32 # enum
# values for enumeration 'OBUF_BYPASS_SEL'
OBUF_BYPASS_SEL__enumvalues = {
0: 'OBUF_BYPASS_DIS',
1: 'OBUF_BYPASS_EN',
}
OBUF_BYPASS_DIS = 0
OBUF_BYPASS_EN = 1
OBUF_BYPASS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OBUF_USE_FULL_BUFFER_SEL'
OBUF_USE_FULL_BUFFER_SEL__enumvalues = {
0: 'OBUF_RECOUT',
1: 'OBUF_FULL',
}
OBUF_RECOUT = 0
OBUF_FULL = 1
OBUF_USE_FULL_BUFFER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OBUF_IS_HALF_RECOUT_WIDTH_SEL'
OBUF_IS_HALF_RECOUT_WIDTH_SEL__enumvalues = {
0: 'OBUF_FULL_RECOUT',
1: 'OBUF_HALF_RECOUT',
}
OBUF_FULL_RECOUT = 0
OBUF_HALF_RECOUT = 1
OBUF_IS_HALF_RECOUT_WIDTH_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CM_BYPASS'
CM_BYPASS__enumvalues = {
0: 'NON_BYPASS',
1: 'BYPASS_EN',
}
NON_BYPASS = 0
BYPASS_EN = 1
CM_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'CM_EN'
CM_EN__enumvalues = {
0: 'CM_DISABLE',
1: 'CM_ENABLE',
}
CM_DISABLE = 0
CM_ENABLE = 1
CM_EN = ctypes.c_uint32 # enum
# values for enumeration 'CM_PENDING'
CM_PENDING__enumvalues = {
0: 'CM_NOT_PENDING',
1: 'CM_YES_PENDING',
}
CM_NOT_PENDING = 0
CM_YES_PENDING = 1
CM_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'CM_DATA_SIGNED'
CM_DATA_SIGNED__enumvalues = {
0: 'UNSIGNED',
1: 'SIGNED',
}
UNSIGNED = 0
SIGNED = 1
CM_DATA_SIGNED = ctypes.c_uint32 # enum
# values for enumeration 'CM_WRITE_BASE_ONLY'
CM_WRITE_BASE_ONLY__enumvalues = {
0: 'WRITE_BOTH',
1: 'WRITE_BASE_ONLY',
}
WRITE_BOTH = 0
WRITE_BASE_ONLY = 1
CM_WRITE_BASE_ONLY = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_4_CONFIG_ENUM'
CM_LUT_4_CONFIG_ENUM__enumvalues = {
0: 'LUT_4CFG_NO_MEMORY',
1: 'LUT_4CFG_ROM_A',
2: 'LUT_4CFG_ROM_B',
3: 'LUT_4CFG_MEMORY_A',
4: 'LUT_4CFG_MEMORY_B',
}
LUT_4CFG_NO_MEMORY = 0
LUT_4CFG_ROM_A = 1
LUT_4CFG_ROM_B = 2
LUT_4CFG_MEMORY_A = 3
LUT_4CFG_MEMORY_B = 4
CM_LUT_4_CONFIG_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_2_CONFIG_ENUM'
CM_LUT_2_CONFIG_ENUM__enumvalues = {
0: 'LUT_2CFG_NO_MEMORY',
1: 'LUT_2CFG_MEMORY_A',
2: 'LUT_2CFG_MEMORY_B',
}
LUT_2CFG_NO_MEMORY = 0
LUT_2CFG_MEMORY_A = 1
LUT_2CFG_MEMORY_B = 2
CM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_4_MODE_ENUM'
CM_LUT_4_MODE_ENUM__enumvalues = {
0: 'LUT_4_MODE_BYPASS',
1: 'LUT_4_MODE_ROMA_LUT',
2: 'LUT_4_MODE_ROMB_LUT',
3: 'LUT_4_MODE_RAMA_LUT',
4: 'LUT_4_MODE_RAMB_LUT',
}
LUT_4_MODE_BYPASS = 0
LUT_4_MODE_ROMA_LUT = 1
LUT_4_MODE_ROMB_LUT = 2
LUT_4_MODE_RAMA_LUT = 3
LUT_4_MODE_RAMB_LUT = 4
CM_LUT_4_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_2_MODE_ENUM'
CM_LUT_2_MODE_ENUM__enumvalues = {
0: 'LUT_2_MODE_BYPASS',
1: 'LUT_2_MODE_RAMA_LUT',
2: 'LUT_2_MODE_RAMB_LUT',
}
LUT_2_MODE_BYPASS = 0
LUT_2_MODE_RAMA_LUT = 1
LUT_2_MODE_RAMB_LUT = 2
CM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_RAM_SEL'
CM_LUT_RAM_SEL__enumvalues = {
0: 'RAMA_ACCESS',
1: 'RAMB_ACCESS',
}
RAMA_ACCESS = 0
RAMB_ACCESS = 1
CM_LUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_NUM_SEG'
CM_LUT_NUM_SEG__enumvalues = {
0: 'SEGMENTS_1',
1: 'SEGMENTS_2',
2: 'SEGMENTS_4',
3: 'SEGMENTS_8',
4: 'SEGMENTS_16',
5: 'SEGMENTS_32',
6: 'SEGMENTS_64',
7: 'SEGMENTS_128',
}
SEGMENTS_1 = 0
SEGMENTS_2 = 1
SEGMENTS_4 = 2
SEGMENTS_8 = 3
SEGMENTS_16 = 4
SEGMENTS_32 = 5
SEGMENTS_64 = 6
SEGMENTS_128 = 7
CM_LUT_NUM_SEG = ctypes.c_uint32 # enum
# values for enumeration 'CM_ICSC_MODE_ENUM'
CM_ICSC_MODE_ENUM__enumvalues = {
0: 'BYPASS_ICSC',
1: 'COEF_ICSC',
2: 'COEF_ICSC_B',
}
BYPASS_ICSC = 0
COEF_ICSC = 1
COEF_ICSC_B = 2
CM_ICSC_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_GAMUT_REMAP_MODE_ENUM'
CM_GAMUT_REMAP_MODE_ENUM__enumvalues = {
0: 'BYPASS_GAMUT',
1: 'GAMUT_COEF',
2: 'GAMUT_COEF_B',
}
BYPASS_GAMUT = 0
GAMUT_COEF = 1
GAMUT_COEF_B = 2
CM_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_COEF_FORMAT_ENUM'
CM_COEF_FORMAT_ENUM__enumvalues = {
0: 'FIX_S2_13',
1: 'FIX_S3_12',
}
FIX_S2_13 = 0
FIX_S3_12 = 1
CM_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CMC_LUT_2_CONFIG_ENUM'
CMC_LUT_2_CONFIG_ENUM__enumvalues = {
0: 'CMC_LUT_2CFG_NO_MEMORY',
1: 'CMC_LUT_2CFG_MEMORY_A',
2: 'CMC_LUT_2CFG_MEMORY_B',
}
CMC_LUT_2CFG_NO_MEMORY = 0
CMC_LUT_2CFG_MEMORY_A = 1
CMC_LUT_2CFG_MEMORY_B = 2
CMC_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CMC_LUT_2_MODE_ENUM'
CMC_LUT_2_MODE_ENUM__enumvalues = {
0: 'CMC_LUT_2_MODE_BYPASS',
1: 'CMC_LUT_2_MODE_RAMA_LUT',
2: 'CMC_LUT_2_MODE_RAMB_LUT',
}
CMC_LUT_2_MODE_BYPASS = 0
CMC_LUT_2_MODE_RAMA_LUT = 1
CMC_LUT_2_MODE_RAMB_LUT = 2
CMC_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CMC_LUT_RAM_SEL'
CMC_LUT_RAM_SEL__enumvalues = {
0: 'CMC_RAMA_ACCESS',
1: 'CMC_RAMB_ACCESS',
}
CMC_RAMA_ACCESS = 0
CMC_RAMB_ACCESS = 1
CMC_LUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CMC_3DLUT_RAM_SEL'
CMC_3DLUT_RAM_SEL__enumvalues = {
0: 'CMC_RAM0_ACCESS',
1: 'CMC_RAM1_ACCESS',
2: 'CMC_RAM2_ACCESS',
3: 'CMC_RAM3_ACCESS',
}
CMC_RAM0_ACCESS = 0
CMC_RAM1_ACCESS = 1
CMC_RAM2_ACCESS = 2
CMC_RAM3_ACCESS = 3
CMC_3DLUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CMC_LUT_NUM_SEG'
CMC_LUT_NUM_SEG__enumvalues = {
0: 'CMC_SEGMENTS_1',
1: 'CMC_SEGMENTS_2',
2: 'CMC_SEGMENTS_4',
3: 'CMC_SEGMENTS_8',
4: 'CMC_SEGMENTS_16',
5: 'CMC_SEGMENTS_32',
6: 'CMC_SEGMENTS_64',
7: 'CMC_SEGMENTS_128',
}
CMC_SEGMENTS_1 = 0
CMC_SEGMENTS_2 = 1
CMC_SEGMENTS_4 = 2
CMC_SEGMENTS_8 = 3
CMC_SEGMENTS_16 = 4
CMC_SEGMENTS_32 = 5
CMC_SEGMENTS_64 = 6
CMC_SEGMENTS_128 = 7
CMC_LUT_NUM_SEG = ctypes.c_uint32 # enum
# values for enumeration 'CMC_3DLUT_30BIT_ENUM'
CMC_3DLUT_30BIT_ENUM__enumvalues = {
0: 'CMC_3DLUT_36BIT',
1: 'CMC_3DLUT_30BIT',
}
CMC_3DLUT_36BIT = 0
CMC_3DLUT_30BIT = 1
CMC_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CMC_3DLUT_SIZE_ENUM'
CMC_3DLUT_SIZE_ENUM__enumvalues = {
0: 'CMC_3DLUT_17CUBE',
1: 'CMC_3DLUT_9CUBE',
}
CMC_3DLUT_17CUBE = 0
CMC_3DLUT_9CUBE = 1
CMC_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'TEST_CLK_SEL'
TEST_CLK_SEL__enumvalues = {
0: 'TEST_CLK_SEL_0',
1: 'TEST_CLK_SEL_1',
2: 'TEST_CLK_SEL_2',
3: 'TEST_CLK_SEL_3',
4: 'TEST_CLK_SEL_4',
5: 'TEST_CLK_SEL_5',
6: 'TEST_CLK_SEL_6',
7: 'TEST_CLK_SEL_7',
8: 'TEST_CLK_SEL_8',
}
TEST_CLK_SEL_0 = 0
TEST_CLK_SEL_1 = 1
TEST_CLK_SEL_2 = 2
TEST_CLK_SEL_3 = 3
TEST_CLK_SEL_4 = 4
TEST_CLK_SEL_5 = 5
TEST_CLK_SEL_6 = 6
TEST_CLK_SEL_7 = 7
TEST_CLK_SEL_8 = 8
TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_SRC_SEL'
CRC_SRC_SEL__enumvalues = {
0: 'CRC_SRC_0',
1: 'CRC_SRC_1',
2: 'CRC_SRC_2',
3: 'CRC_SRC_3',
}
CRC_SRC_0 = 0
CRC_SRC_1 = 1
CRC_SRC_2 = 2
CRC_SRC_3 = 3
CRC_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_IN_PIX_SEL'
CRC_IN_PIX_SEL__enumvalues = {
0: 'CRC_IN_PIX_0',
1: 'CRC_IN_PIX_1',
2: 'CRC_IN_PIX_2',
3: 'CRC_IN_PIX_3',
4: 'CRC_IN_PIX_4',
5: 'CRC_IN_PIX_5',
6: 'CRC_IN_PIX_6',
7: 'CRC_IN_PIX_7',
}
CRC_IN_PIX_0 = 0
CRC_IN_PIX_1 = 1
CRC_IN_PIX_2 = 2
CRC_IN_PIX_3 = 3
CRC_IN_PIX_4 = 4
CRC_IN_PIX_5 = 5
CRC_IN_PIX_6 = 6
CRC_IN_PIX_7 = 7
CRC_IN_PIX_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_CUR_BITS_SEL'
CRC_CUR_BITS_SEL__enumvalues = {
0: 'CRC_CUR_BITS_0',
1: 'CRC_CUR_BITS_1',
}
CRC_CUR_BITS_0 = 0
CRC_CUR_BITS_1 = 1
CRC_CUR_BITS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_IN_CUR_SEL'
CRC_IN_CUR_SEL__enumvalues = {
0: 'CRC_IN_CUR_0',
1: 'CRC_IN_CUR_1',
}
CRC_IN_CUR_0 = 0
CRC_IN_CUR_1 = 1
CRC_IN_CUR_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_CUR_SEL'
CRC_CUR_SEL__enumvalues = {
0: 'CRC_CUR_0',
1: 'CRC_CUR_1',
}
CRC_CUR_0 = 0
CRC_CUR_1 = 1
CRC_CUR_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_STEREO_SEL'
CRC_STEREO_SEL__enumvalues = {
0: 'CRC_STEREO_0',
1: 'CRC_STEREO_1',
2: 'CRC_STEREO_2',
3: 'CRC_STEREO_3',
}
CRC_STEREO_0 = 0
CRC_STEREO_1 = 1
CRC_STEREO_2 = 2
CRC_STEREO_3 = 3
CRC_STEREO_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_INTERLACE_SEL'
CRC_INTERLACE_SEL__enumvalues = {
0: 'CRC_INTERLACE_0',
1: 'CRC_INTERLACE_1',
2: 'CRC_INTERLACE_2',
3: 'CRC_INTERLACE_3',
}
CRC_INTERLACE_0 = 0
CRC_INTERLACE_1 = 1
CRC_INTERLACE_2 = 2
CRC_INTERLACE_3 = 3
CRC_INTERLACE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CVALUE_SEL'
PERFCOUNTER_CVALUE_SEL__enumvalues = {
0: 'PERFCOUNTER_CVALUE_SEL_47_0',
1: 'PERFCOUNTER_CVALUE_SEL_15_0',
2: 'PERFCOUNTER_CVALUE_SEL_31_16',
3: 'PERFCOUNTER_CVALUE_SEL_47_32',
4: 'PERFCOUNTER_CVALUE_SEL_11_0',
5: 'PERFCOUNTER_CVALUE_SEL_23_12',
6: 'PERFCOUNTER_CVALUE_SEL_35_24',
7: 'PERFCOUNTER_CVALUE_SEL_47_36',
}
PERFCOUNTER_CVALUE_SEL_47_0 = 0
PERFCOUNTER_CVALUE_SEL_15_0 = 1
PERFCOUNTER_CVALUE_SEL_31_16 = 2
PERFCOUNTER_CVALUE_SEL_47_32 = 3
PERFCOUNTER_CVALUE_SEL_11_0 = 4
PERFCOUNTER_CVALUE_SEL_23_12 = 5
PERFCOUNTER_CVALUE_SEL_35_24 = 6
PERFCOUNTER_CVALUE_SEL_47_36 = 7
PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_INC_MODE'
PERFCOUNTER_INC_MODE__enumvalues = {
0: 'PERFCOUNTER_INC_MODE_MULTI_BIT',
1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE',
2: 'PERFCOUNTER_INC_MODE_LSB',
3: 'PERFCOUNTER_INC_MODE_POS_EDGE',
4: 'PERFCOUNTER_INC_MODE_NEG_EDGE',
}
PERFCOUNTER_INC_MODE_MULTI_BIT = 0
PERFCOUNTER_INC_MODE_BOTH_EDGE = 1
PERFCOUNTER_INC_MODE_LSB = 2
PERFCOUNTER_INC_MODE_POS_EDGE = 3
PERFCOUNTER_INC_MODE_NEG_EDGE = 4
PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL'
PERFCOUNTER_HW_CNTL_SEL__enumvalues = {
0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN',
1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF',
}
PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0
PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1
PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_RUNEN_MODE'
PERFCOUNTER_RUNEN_MODE__enumvalues = {
0: 'PERFCOUNTER_RUNEN_MODE_LEVEL',
1: 'PERFCOUNTER_RUNEN_MODE_EDGE',
}
PERFCOUNTER_RUNEN_MODE_LEVEL = 0
PERFCOUNTER_RUNEN_MODE_EDGE = 1
PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS'
PERFCOUNTER_CNTOFF_START_DIS__enumvalues = {
0: 'PERFCOUNTER_CNTOFF_START_ENABLE',
1: 'PERFCOUNTER_CNTOFF_START_DISABLE',
}
PERFCOUNTER_CNTOFF_START_ENABLE = 0
PERFCOUNTER_CNTOFF_START_DISABLE = 1
PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_RESTART_EN'
PERFCOUNTER_RESTART_EN__enumvalues = {
0: 'PERFCOUNTER_RESTART_DISABLE',
1: 'PERFCOUNTER_RESTART_ENABLE',
}
PERFCOUNTER_RESTART_DISABLE = 0
PERFCOUNTER_RESTART_ENABLE = 1
PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_INT_EN'
PERFCOUNTER_INT_EN__enumvalues = {
0: 'PERFCOUNTER_INT_DISABLE',
1: 'PERFCOUNTER_INT_ENABLE',
}
PERFCOUNTER_INT_DISABLE = 0
PERFCOUNTER_INT_ENABLE = 1
PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_OFF_MASK'
PERFCOUNTER_OFF_MASK__enumvalues = {
0: 'PERFCOUNTER_OFF_MASK_DISABLE',
1: 'PERFCOUNTER_OFF_MASK_ENABLE',
}
PERFCOUNTER_OFF_MASK_DISABLE = 0
PERFCOUNTER_OFF_MASK_ENABLE = 1
PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_ACTIVE'
PERFCOUNTER_ACTIVE__enumvalues = {
0: 'PERFCOUNTER_IS_IDLE',
1: 'PERFCOUNTER_IS_ACTIVE',
}
PERFCOUNTER_IS_IDLE = 0
PERFCOUNTER_IS_ACTIVE = 1
PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_INT_TYPE'
PERFCOUNTER_INT_TYPE__enumvalues = {
0: 'PERFCOUNTER_INT_TYPE_LEVEL',
1: 'PERFCOUNTER_INT_TYPE_PULSE',
}
PERFCOUNTER_INT_TYPE_LEVEL = 0
PERFCOUNTER_INT_TYPE_PULSE = 1
PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE'
PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = {
0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC',
1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX',
2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN',
}
PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0
PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1
PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2
PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_HW_STOP1_SEL'
PERFCOUNTER_HW_STOP1_SEL__enumvalues = {
0: 'PERFCOUNTER_HW_STOP1_0',
1: 'PERFCOUNTER_HW_STOP1_1',
}
PERFCOUNTER_HW_STOP1_0 = 0
PERFCOUNTER_HW_STOP1_1 = 1
PERFCOUNTER_HW_STOP1_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_HW_STOP2_SEL'
PERFCOUNTER_HW_STOP2_SEL__enumvalues = {
0: 'PERFCOUNTER_HW_STOP2_0',
1: 'PERFCOUNTER_HW_STOP2_1',
}
PERFCOUNTER_HW_STOP2_0 = 0
PERFCOUNTER_HW_STOP2_1 = 1
PERFCOUNTER_HW_STOP2_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNTL_SEL'
PERFCOUNTER_CNTL_SEL__enumvalues = {
0: 'PERFCOUNTER_CNTL_SEL_0',
1: 'PERFCOUNTER_CNTL_SEL_1',
2: 'PERFCOUNTER_CNTL_SEL_2',
3: 'PERFCOUNTER_CNTL_SEL_3',
4: 'PERFCOUNTER_CNTL_SEL_4',
5: 'PERFCOUNTER_CNTL_SEL_5',
6: 'PERFCOUNTER_CNTL_SEL_6',
7: 'PERFCOUNTER_CNTL_SEL_7',
}
PERFCOUNTER_CNTL_SEL_0 = 0
PERFCOUNTER_CNTL_SEL_1 = 1
PERFCOUNTER_CNTL_SEL_2 = 2
PERFCOUNTER_CNTL_SEL_3 = 3
PERFCOUNTER_CNTL_SEL_4 = 4
PERFCOUNTER_CNTL_SEL_5 = 5
PERFCOUNTER_CNTL_SEL_6 = 6
PERFCOUNTER_CNTL_SEL_7 = 7
PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT0_STATE'
PERFCOUNTER_CNT0_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT0_STATE_RESET',
1: 'PERFCOUNTER_CNT0_STATE_START',
2: 'PERFCOUNTER_CNT0_STATE_FREEZE',
3: 'PERFCOUNTER_CNT0_STATE_HW',
}
PERFCOUNTER_CNT0_STATE_RESET = 0
PERFCOUNTER_CNT0_STATE_START = 1
PERFCOUNTER_CNT0_STATE_FREEZE = 2
PERFCOUNTER_CNT0_STATE_HW = 3
PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL0'
PERFCOUNTER_STATE_SEL0__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL0_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL0_LOCAL',
}
PERFCOUNTER_STATE_SEL0_GLOBAL = 0
PERFCOUNTER_STATE_SEL0_LOCAL = 1
PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT1_STATE'
PERFCOUNTER_CNT1_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT1_STATE_RESET',
1: 'PERFCOUNTER_CNT1_STATE_START',
2: 'PERFCOUNTER_CNT1_STATE_FREEZE',
3: 'PERFCOUNTER_CNT1_STATE_HW',
}
PERFCOUNTER_CNT1_STATE_RESET = 0
PERFCOUNTER_CNT1_STATE_START = 1
PERFCOUNTER_CNT1_STATE_FREEZE = 2
PERFCOUNTER_CNT1_STATE_HW = 3
PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL1'
PERFCOUNTER_STATE_SEL1__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL1_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL1_LOCAL',
}
PERFCOUNTER_STATE_SEL1_GLOBAL = 0
PERFCOUNTER_STATE_SEL1_LOCAL = 1
PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT2_STATE'
PERFCOUNTER_CNT2_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT2_STATE_RESET',
1: 'PERFCOUNTER_CNT2_STATE_START',
2: 'PERFCOUNTER_CNT2_STATE_FREEZE',
3: 'PERFCOUNTER_CNT2_STATE_HW',
}
PERFCOUNTER_CNT2_STATE_RESET = 0
PERFCOUNTER_CNT2_STATE_START = 1
PERFCOUNTER_CNT2_STATE_FREEZE = 2
PERFCOUNTER_CNT2_STATE_HW = 3
PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL2'
PERFCOUNTER_STATE_SEL2__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL2_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL2_LOCAL',
}
PERFCOUNTER_STATE_SEL2_GLOBAL = 0
PERFCOUNTER_STATE_SEL2_LOCAL = 1
PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT3_STATE'
PERFCOUNTER_CNT3_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT3_STATE_RESET',
1: 'PERFCOUNTER_CNT3_STATE_START',
2: 'PERFCOUNTER_CNT3_STATE_FREEZE',
3: 'PERFCOUNTER_CNT3_STATE_HW',
}
PERFCOUNTER_CNT3_STATE_RESET = 0
PERFCOUNTER_CNT3_STATE_START = 1
PERFCOUNTER_CNT3_STATE_FREEZE = 2
PERFCOUNTER_CNT3_STATE_HW = 3
PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL3'
PERFCOUNTER_STATE_SEL3__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL3_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL3_LOCAL',
}
PERFCOUNTER_STATE_SEL3_GLOBAL = 0
PERFCOUNTER_STATE_SEL3_LOCAL = 1
PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT4_STATE'
PERFCOUNTER_CNT4_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT4_STATE_RESET',
1: 'PERFCOUNTER_CNT4_STATE_START',
2: 'PERFCOUNTER_CNT4_STATE_FREEZE',
3: 'PERFCOUNTER_CNT4_STATE_HW',
}
PERFCOUNTER_CNT4_STATE_RESET = 0
PERFCOUNTER_CNT4_STATE_START = 1
PERFCOUNTER_CNT4_STATE_FREEZE = 2
PERFCOUNTER_CNT4_STATE_HW = 3
PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL4'
PERFCOUNTER_STATE_SEL4__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL4_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL4_LOCAL',
}
PERFCOUNTER_STATE_SEL4_GLOBAL = 0
PERFCOUNTER_STATE_SEL4_LOCAL = 1
PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT5_STATE'
PERFCOUNTER_CNT5_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT5_STATE_RESET',
1: 'PERFCOUNTER_CNT5_STATE_START',
2: 'PERFCOUNTER_CNT5_STATE_FREEZE',
3: 'PERFCOUNTER_CNT5_STATE_HW',
}
PERFCOUNTER_CNT5_STATE_RESET = 0
PERFCOUNTER_CNT5_STATE_START = 1
PERFCOUNTER_CNT5_STATE_FREEZE = 2
PERFCOUNTER_CNT5_STATE_HW = 3
PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL5'
PERFCOUNTER_STATE_SEL5__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL5_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL5_LOCAL',
}
PERFCOUNTER_STATE_SEL5_GLOBAL = 0
PERFCOUNTER_STATE_SEL5_LOCAL = 1
PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT6_STATE'
PERFCOUNTER_CNT6_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT6_STATE_RESET',
1: 'PERFCOUNTER_CNT6_STATE_START',
2: 'PERFCOUNTER_CNT6_STATE_FREEZE',
3: 'PERFCOUNTER_CNT6_STATE_HW',
}
PERFCOUNTER_CNT6_STATE_RESET = 0
PERFCOUNTER_CNT6_STATE_START = 1
PERFCOUNTER_CNT6_STATE_FREEZE = 2
PERFCOUNTER_CNT6_STATE_HW = 3
PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL6'
PERFCOUNTER_STATE_SEL6__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL6_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL6_LOCAL',
}
PERFCOUNTER_STATE_SEL6_GLOBAL = 0
PERFCOUNTER_STATE_SEL6_LOCAL = 1
PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT7_STATE'
PERFCOUNTER_CNT7_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT7_STATE_RESET',
1: 'PERFCOUNTER_CNT7_STATE_START',
2: 'PERFCOUNTER_CNT7_STATE_FREEZE',
3: 'PERFCOUNTER_CNT7_STATE_HW',
}
PERFCOUNTER_CNT7_STATE_RESET = 0
PERFCOUNTER_CNT7_STATE_START = 1
PERFCOUNTER_CNT7_STATE_FREEZE = 2
PERFCOUNTER_CNT7_STATE_HW = 3
PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL7'
PERFCOUNTER_STATE_SEL7__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL7_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL7_LOCAL',
}
PERFCOUNTER_STATE_SEL7_GLOBAL = 0
PERFCOUNTER_STATE_SEL7_LOCAL = 1
PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_STATE'
PERFMON_STATE__enumvalues = {
0: 'PERFMON_STATE_RESET',
1: 'PERFMON_STATE_START',
2: 'PERFMON_STATE_FREEZE',
3: 'PERFMON_STATE_HW',
}
PERFMON_STATE_RESET = 0
PERFMON_STATE_START = 1
PERFMON_STATE_FREEZE = 2
PERFMON_STATE_HW = 3
PERFMON_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_CNTOFF_AND_OR'
PERFMON_CNTOFF_AND_OR__enumvalues = {
0: 'PERFMON_CNTOFF_OR',
1: 'PERFMON_CNTOFF_AND',
}
PERFMON_CNTOFF_OR = 0
PERFMON_CNTOFF_AND = 1
PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_CNTOFF_INT_EN'
PERFMON_CNTOFF_INT_EN__enumvalues = {
0: 'PERFMON_CNTOFF_INT_DISABLE',
1: 'PERFMON_CNTOFF_INT_ENABLE',
}
PERFMON_CNTOFF_INT_DISABLE = 0
PERFMON_CNTOFF_INT_ENABLE = 1
PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_CNTOFF_INT_TYPE'
PERFMON_CNTOFF_INT_TYPE__enumvalues = {
0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL',
1: 'PERFMON_CNTOFF_INT_TYPE_PULSE',
}
PERFMON_CNTOFF_INT_TYPE_LEVEL = 0
PERFMON_CNTOFF_INT_TYPE_PULSE = 1
PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'ROTATION_ANGLE'
ROTATION_ANGLE__enumvalues = {
0: 'ROTATE_0_DEGREES',
1: 'ROTATE_90_DEGREES',
2: 'ROTATE_180_DEGREES',
3: 'ROTATE_270_DEGREES',
}
ROTATE_0_DEGREES = 0
ROTATE_90_DEGREES = 1
ROTATE_180_DEGREES = 2
ROTATE_270_DEGREES = 3
ROTATION_ANGLE = ctypes.c_uint32 # enum
# values for enumeration 'H_MIRROR_EN'
H_MIRROR_EN__enumvalues = {
0: 'HW_MIRRORING_DISABLE',
1: 'HW_MIRRORING_ENABLE',
}
HW_MIRRORING_DISABLE = 0
HW_MIRRORING_ENABLE = 1
H_MIRROR_EN = ctypes.c_uint32 # enum
# values for enumeration 'NUM_PIPES'
NUM_PIPES__enumvalues = {
0: 'ONE_PIPE',
1: 'TWO_PIPES',
2: 'FOUR_PIPES',
3: 'EIGHT_PIPES',
4: 'SIXTEEN_PIPES',
5: 'THIRTY_TWO_PIPES',
6: 'SIXTY_FOUR_PIPES',
}
ONE_PIPE = 0
TWO_PIPES = 1
FOUR_PIPES = 2
EIGHT_PIPES = 3
SIXTEEN_PIPES = 4
THIRTY_TWO_PIPES = 5
SIXTY_FOUR_PIPES = 6
NUM_PIPES = ctypes.c_uint32 # enum
# values for enumeration 'NUM_BANKS'
NUM_BANKS__enumvalues = {
0: 'ONE_BANK',
1: 'TWO_BANKS',
2: 'FOUR_BANKS',
3: 'EIGHT_BANKS',
4: 'SIXTEEN_BANKS',
}
ONE_BANK = 0
TWO_BANKS = 1
FOUR_BANKS = 2
EIGHT_BANKS = 3
SIXTEEN_BANKS = 4
NUM_BANKS = ctypes.c_uint32 # enum
# values for enumeration 'SW_MODE'
SW_MODE__enumvalues = {
0: 'SWIZZLE_LINEAR',
5: 'SWIZZLE_4KB_S',
6: 'SWIZZLE_4KB_D',
9: 'SWIZZLE_64KB_S',
10: 'SWIZZLE_64KB_D',
13: 'SWIZZLE_VAR_S',
14: 'SWIZZLE_VAR_D',
17: 'SWIZZLE_64KB_S_T',
18: 'SWIZZLE_64KB_D_T',
21: 'SWIZZLE_4KB_S_X',
22: 'SWIZZLE_4KB_D_X',
25: 'SWIZZLE_64KB_S_X',
26: 'SWIZZLE_64KB_D_X',
27: 'SWIZZLE_64KB_R_X',
29: 'SWIZZLE_VAR_S_X',
30: 'SWIZZLE_VAR_D_X',
}
SWIZZLE_LINEAR = 0
SWIZZLE_4KB_S = 5
SWIZZLE_4KB_D = 6
SWIZZLE_64KB_S = 9
SWIZZLE_64KB_D = 10
SWIZZLE_VAR_S = 13
SWIZZLE_VAR_D = 14
SWIZZLE_64KB_S_T = 17
SWIZZLE_64KB_D_T = 18
SWIZZLE_4KB_S_X = 21
SWIZZLE_4KB_D_X = 22
SWIZZLE_64KB_S_X = 25
SWIZZLE_64KB_D_X = 26
SWIZZLE_64KB_R_X = 27
SWIZZLE_VAR_S_X = 29
SWIZZLE_VAR_D_X = 30
SW_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_INTERLEAVE'
PIPE_INTERLEAVE__enumvalues = {
0: 'PIPE_INTERLEAVE_256B',
1: 'PIPE_INTERLEAVE_512B',
2: 'PIPE_INTERLEAVE_1KB',
}
PIPE_INTERLEAVE_256B = 0
PIPE_INTERLEAVE_512B = 1
PIPE_INTERLEAVE_1KB = 2
PIPE_INTERLEAVE = ctypes.c_uint32 # enum
# values for enumeration 'LEGACY_PIPE_INTERLEAVE'
LEGACY_PIPE_INTERLEAVE__enumvalues = {
0: 'LEGACY_PIPE_INTERLEAVE_256B',
1: 'LEGACY_PIPE_INTERLEAVE_512B',
}
LEGACY_PIPE_INTERLEAVE_256B = 0
LEGACY_PIPE_INTERLEAVE_512B = 1
LEGACY_PIPE_INTERLEAVE = ctypes.c_uint32 # enum
# values for enumeration 'NUM_SE'
NUM_SE__enumvalues = {
0: 'ONE_SHADER_ENGIN',
1: 'TWO_SHADER_ENGINS',
2: 'FOUR_SHADER_ENGINS',
3: 'EIGHT_SHADER_ENGINS',
}
ONE_SHADER_ENGIN = 0
TWO_SHADER_ENGINS = 1
FOUR_SHADER_ENGINS = 2
EIGHT_SHADER_ENGINS = 3
NUM_SE = ctypes.c_uint32 # enum
# values for enumeration 'NUM_RB_PER_SE'
NUM_RB_PER_SE__enumvalues = {
0: 'ONE_RB_PER_SE',
1: 'TWO_RB_PER_SE',
2: 'FOUR_RB_PER_SE',
}
ONE_RB_PER_SE = 0
TWO_RB_PER_SE = 1
FOUR_RB_PER_SE = 2
NUM_RB_PER_SE = ctypes.c_uint32 # enum
# values for enumeration 'MAX_COMPRESSED_FRAGS'
MAX_COMPRESSED_FRAGS__enumvalues = {
0: 'ONE_FRAGMENT',
1: 'TWO_FRAGMENTS',
2: 'FOUR_FRAGMENTS',
3: 'EIGHT_FRAGMENTS',
}
ONE_FRAGMENT = 0
TWO_FRAGMENTS = 1
FOUR_FRAGMENTS = 2
EIGHT_FRAGMENTS = 3
MAX_COMPRESSED_FRAGS = ctypes.c_uint32 # enum
# values for enumeration 'DIM_TYPE'
DIM_TYPE__enumvalues = {
0: 'DIM_TYPE_1D',
1: 'DIM_TYPE_2D',
2: 'DIM_TYPE_3D',
3: 'DIM_TYPE_RESERVED',
}
DIM_TYPE_1D = 0
DIM_TYPE_2D = 1
DIM_TYPE_3D = 2
DIM_TYPE_RESERVED = 3
DIM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'META_LINEAR'
META_LINEAR__enumvalues = {
0: 'META_SURF_TILED',
1: 'META_SURF_LINEAR',
}
META_SURF_TILED = 0
META_SURF_LINEAR = 1
META_LINEAR = ctypes.c_uint32 # enum
# values for enumeration 'RB_ALIGNED'
RB_ALIGNED__enumvalues = {
0: 'RB_UNALIGNED_META_SURF',
1: 'RB_ALIGNED_META_SURF',
}
RB_UNALIGNED_META_SURF = 0
RB_ALIGNED_META_SURF = 1
RB_ALIGNED = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_ALIGNED'
PIPE_ALIGNED__enumvalues = {
0: 'PIPE_UNALIGNED_SURF',
1: 'PIPE_ALIGNED_SURF',
}
PIPE_UNALIGNED_SURF = 0
PIPE_ALIGNED_SURF = 1
PIPE_ALIGNED = ctypes.c_uint32 # enum
# values for enumeration 'ARRAY_MODE'
ARRAY_MODE__enumvalues = {
0: 'AM_LINEAR_GENERAL',
1: 'AM_LINEAR_ALIGNED',
2: 'AM_1D_TILED_THIN1',
3: 'AM_1D_TILED_THICK',
4: 'AM_2D_TILED_THIN1',
5: 'AM_PRT_TILED_THIN1',
6: 'AM_PRT_2D_TILED_THIN1',
7: 'AM_2D_TILED_THICK',
8: 'AM_2D_TILED_XTHICK',
9: 'AM_PRT_TILED_THICK',
10: 'AM_PRT_2D_TILED_THICK',
11: 'AM_PRT_3D_TILED_THIN1',
12: 'AM_3D_TILED_THIN1',
13: 'AM_3D_TILED_THICK',
14: 'AM_3D_TILED_XTHICK',
15: 'AM_PRT_3D_TILED_THICK',
}
AM_LINEAR_GENERAL = 0
AM_LINEAR_ALIGNED = 1
AM_1D_TILED_THIN1 = 2
AM_1D_TILED_THICK = 3
AM_2D_TILED_THIN1 = 4
AM_PRT_TILED_THIN1 = 5
AM_PRT_2D_TILED_THIN1 = 6
AM_2D_TILED_THICK = 7
AM_2D_TILED_XTHICK = 8
AM_PRT_TILED_THICK = 9
AM_PRT_2D_TILED_THICK = 10
AM_PRT_3D_TILED_THIN1 = 11
AM_3D_TILED_THIN1 = 12
AM_3D_TILED_THICK = 13
AM_3D_TILED_XTHICK = 14
AM_PRT_3D_TILED_THICK = 15
ARRAY_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_CONFIG'
PIPE_CONFIG__enumvalues = {
0: 'P2',
4: 'P4_8x16',
5: 'P4_16x16',
6: 'P4_16x32',
7: 'P4_32x32',
8: 'P8_16x16_8x16',
9: 'P8_16x32_8x16',
10: 'P8_32x32_8x16',
11: 'P8_16x32_16x16',
12: 'P8_32x32_16x16',
13: 'P8_32x32_16x32',
14: 'P8_32x64_32x32',
16: 'P16_32x32_8x16',
17: 'P16_32x32_16x16',
18: 'P16_ADDR_SURF',
}
P2 = 0
P4_8x16 = 4
P4_16x16 = 5
P4_16x32 = 6
P4_32x32 = 7
P8_16x16_8x16 = 8
P8_16x32_8x16 = 9
P8_32x32_8x16 = 10
P8_16x32_16x16 = 11
P8_32x32_16x16 = 12
P8_32x32_16x32 = 13
P8_32x64_32x32 = 14
P16_32x32_8x16 = 16
P16_32x32_16x16 = 17
P16_ADDR_SURF = 18
PIPE_CONFIG = ctypes.c_uint32 # enum
# values for enumeration 'MICRO_TILE_MODE_NEW'
MICRO_TILE_MODE_NEW__enumvalues = {
0: 'DISPLAY_MICRO_TILING',
1: 'THIN_MICRO_TILING',
2: 'DEPTH_MICRO_TILING',
3: 'ROTATED_MICRO_TILING',
4: 'THICK_MICRO_TILING',
}
DISPLAY_MICRO_TILING = 0
THIN_MICRO_TILING = 1
DEPTH_MICRO_TILING = 2
ROTATED_MICRO_TILING = 3
THICK_MICRO_TILING = 4
MICRO_TILE_MODE_NEW = ctypes.c_uint32 # enum
# values for enumeration 'TILE_SPLIT'
TILE_SPLIT__enumvalues = {
0: 'SURF_TILE_SPLIT_64B',
1: 'SURF_TILE_SPLIT_128B',
2: 'SURF_TILE_SPLIT_256B',
3: 'SURF_TILE_SPLIT_512B',
4: 'SURF_TILE_SPLIT_1KB',
5: 'SURF_TILE_SPLIT_2KB',
6: 'SURF_TILE_SPLIT_4KB',
}
SURF_TILE_SPLIT_64B = 0
SURF_TILE_SPLIT_128B = 1
SURF_TILE_SPLIT_256B = 2
SURF_TILE_SPLIT_512B = 3
SURF_TILE_SPLIT_1KB = 4
SURF_TILE_SPLIT_2KB = 5
SURF_TILE_SPLIT_4KB = 6
TILE_SPLIT = ctypes.c_uint32 # enum
# values for enumeration 'BANK_WIDTH'
BANK_WIDTH__enumvalues = {
0: 'SURF_BANK_WIDTH_1',
1: 'SURF_BANK_WIDTH_2',
2: 'SURF_BANK_WIDTH_4',
3: 'SURF_BANK_WIDTH_8',
}
SURF_BANK_WIDTH_1 = 0
SURF_BANK_WIDTH_2 = 1
SURF_BANK_WIDTH_4 = 2
SURF_BANK_WIDTH_8 = 3
BANK_WIDTH = ctypes.c_uint32 # enum
# values for enumeration 'BANK_HEIGHT'
BANK_HEIGHT__enumvalues = {
0: 'SURF_BANK_HEIGHT_1',
1: 'SURF_BANK_HEIGHT_2',
2: 'SURF_BANK_HEIGHT_4',
3: 'SURF_BANK_HEIGHT_8',
}
SURF_BANK_HEIGHT_1 = 0
SURF_BANK_HEIGHT_2 = 1
SURF_BANK_HEIGHT_4 = 2
SURF_BANK_HEIGHT_8 = 3
BANK_HEIGHT = ctypes.c_uint32 # enum
# values for enumeration 'MACRO_TILE_ASPECT'
MACRO_TILE_ASPECT__enumvalues = {
0: 'SURF_MACRO_ASPECT_1',
1: 'SURF_MACRO_ASPECT_2',
2: 'SURF_MACRO_ASPECT_4',
3: 'SURF_MACRO_ASPECT_8',
}
SURF_MACRO_ASPECT_1 = 0
SURF_MACRO_ASPECT_2 = 1
SURF_MACRO_ASPECT_4 = 2
SURF_MACRO_ASPECT_8 = 3
MACRO_TILE_ASPECT = ctypes.c_uint32 # enum
# values for enumeration 'LEGACY_NUM_BANKS'
LEGACY_NUM_BANKS__enumvalues = {
0: 'SURF_2_BANK',
1: 'SURF_4_BANK',
2: 'SURF_8_BANK',
3: 'SURF_16_BANK',
}
SURF_2_BANK = 0
SURF_4_BANK = 1
SURF_8_BANK = 2
SURF_16_BANK = 3
LEGACY_NUM_BANKS = ctypes.c_uint32 # enum
# values for enumeration 'SWATH_HEIGHT'
SWATH_HEIGHT__enumvalues = {
0: 'SWATH_HEIGHT_1L',
1: 'SWATH_HEIGHT_2L',
2: 'SWATH_HEIGHT_4L',
3: 'SWATH_HEIGHT_8L',
4: 'SWATH_HEIGHT_16L',
}
SWATH_HEIGHT_1L = 0
SWATH_HEIGHT_2L = 1
SWATH_HEIGHT_4L = 2
SWATH_HEIGHT_8L = 3
SWATH_HEIGHT_16L = 4
SWATH_HEIGHT = ctypes.c_uint32 # enum
# values for enumeration 'PTE_ROW_HEIGHT_LINEAR'
PTE_ROW_HEIGHT_LINEAR__enumvalues = {
0: 'PTE_ROW_HEIGHT_LINEAR_8L',
1: 'PTE_ROW_HEIGHT_LINEAR_16L',
2: 'PTE_ROW_HEIGHT_LINEAR_32L',
3: 'PTE_ROW_HEIGHT_LINEAR_64L',
4: 'PTE_ROW_HEIGHT_LINEAR_128L',
5: 'PTE_ROW_HEIGHT_LINEAR_256L',
6: 'PTE_ROW_HEIGHT_LINEAR_512L',
7: 'PTE_ROW_HEIGHT_LINEAR_1024L',
}
PTE_ROW_HEIGHT_LINEAR_8L = 0
PTE_ROW_HEIGHT_LINEAR_16L = 1
PTE_ROW_HEIGHT_LINEAR_32L = 2
PTE_ROW_HEIGHT_LINEAR_64L = 3
PTE_ROW_HEIGHT_LINEAR_128L = 4
PTE_ROW_HEIGHT_LINEAR_256L = 5
PTE_ROW_HEIGHT_LINEAR_512L = 6
PTE_ROW_HEIGHT_LINEAR_1024L = 7
PTE_ROW_HEIGHT_LINEAR = ctypes.c_uint32 # enum
# values for enumeration 'CHUNK_SIZE'
CHUNK_SIZE__enumvalues = {
0: 'CHUNK_SIZE_1KB',
1: 'CHUNK_SIZE_2KB',
2: 'CHUNK_SIZE_4KB',
3: 'CHUNK_SIZE_8KB',
4: 'CHUNK_SIZE_16KB',
5: 'CHUNK_SIZE_32KB',
6: 'CHUNK_SIZE_64KB',
}
CHUNK_SIZE_1KB = 0
CHUNK_SIZE_2KB = 1
CHUNK_SIZE_4KB = 2
CHUNK_SIZE_8KB = 3
CHUNK_SIZE_16KB = 4
CHUNK_SIZE_32KB = 5
CHUNK_SIZE_64KB = 6
CHUNK_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'MIN_CHUNK_SIZE'
MIN_CHUNK_SIZE__enumvalues = {
0: 'NO_MIN_CHUNK_SIZE',
1: 'MIN_CHUNK_SIZE_256B',
2: 'MIN_CHUNK_SIZE_512B',
3: 'MIN_CHUNK_SIZE_1024B',
}
NO_MIN_CHUNK_SIZE = 0
MIN_CHUNK_SIZE_256B = 1
MIN_CHUNK_SIZE_512B = 2
MIN_CHUNK_SIZE_1024B = 3
MIN_CHUNK_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'META_CHUNK_SIZE'
META_CHUNK_SIZE__enumvalues = {
0: 'META_CHUNK_SIZE_1KB',
1: 'META_CHUNK_SIZE_2KB',
2: 'META_CHUNK_SIZE_4KB',
3: 'META_CHUNK_SIZE_8KB',
}
META_CHUNK_SIZE_1KB = 0
META_CHUNK_SIZE_2KB = 1
META_CHUNK_SIZE_4KB = 2
META_CHUNK_SIZE_8KB = 3
META_CHUNK_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'MIN_META_CHUNK_SIZE'
MIN_META_CHUNK_SIZE__enumvalues = {
0: 'NO_MIN_META_CHUNK_SIZE',
1: 'MIN_META_CHUNK_SIZE_64B',
2: 'MIN_META_CHUNK_SIZE_128B',
3: 'MIN_META_CHUNK_SIZE_256B',
}
NO_MIN_META_CHUNK_SIZE = 0
MIN_META_CHUNK_SIZE_64B = 1
MIN_META_CHUNK_SIZE_128B = 2
MIN_META_CHUNK_SIZE_256B = 3
MIN_META_CHUNK_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'DPTE_GROUP_SIZE'
DPTE_GROUP_SIZE__enumvalues = {
0: 'DPTE_GROUP_SIZE_64B',
1: 'DPTE_GROUP_SIZE_128B',
2: 'DPTE_GROUP_SIZE_256B',
3: 'DPTE_GROUP_SIZE_512B',
4: 'DPTE_GROUP_SIZE_1024B',
5: 'DPTE_GROUP_SIZE_2048B',
6: 'DPTE_GROUP_SIZE_4096B',
7: 'DPTE_GROUP_SIZE_8192B',
}
DPTE_GROUP_SIZE_64B = 0
DPTE_GROUP_SIZE_128B = 1
DPTE_GROUP_SIZE_256B = 2
DPTE_GROUP_SIZE_512B = 3
DPTE_GROUP_SIZE_1024B = 4
DPTE_GROUP_SIZE_2048B = 5
DPTE_GROUP_SIZE_4096B = 6
DPTE_GROUP_SIZE_8192B = 7
DPTE_GROUP_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'MPTE_GROUP_SIZE'
MPTE_GROUP_SIZE__enumvalues = {
0: 'MPTE_GROUP_SIZE_64B',
1: 'MPTE_GROUP_SIZE_128B',
2: 'MPTE_GROUP_SIZE_256B',
3: 'MPTE_GROUP_SIZE_512B',
4: 'MPTE_GROUP_SIZE_1024B',
5: 'MPTE_GROUP_SIZE_2048B',
6: 'MPTE_GROUP_SIZE_4096B',
7: 'MPTE_GROUP_SIZE_8192B',
}
MPTE_GROUP_SIZE_64B = 0
MPTE_GROUP_SIZE_128B = 1
MPTE_GROUP_SIZE_256B = 2
MPTE_GROUP_SIZE_512B = 3
MPTE_GROUP_SIZE_1024B = 4
MPTE_GROUP_SIZE_2048B = 5
MPTE_GROUP_SIZE_4096B = 6
MPTE_GROUP_SIZE_8192B = 7
MPTE_GROUP_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_BLANK_EN'
HUBP_BLANK_EN__enumvalues = {
0: 'HUBP_BLANK_SW_DEASSERT',
1: 'HUBP_BLANK_SW_ASSERT',
}
HUBP_BLANK_SW_DEASSERT = 0
HUBP_BLANK_SW_ASSERT = 1
HUBP_BLANK_EN = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_DISABLE'
HUBP_DISABLE__enumvalues = {
0: 'HUBP_ENABLED',
1: 'HUBP_DISABLED',
}
HUBP_ENABLED = 0
HUBP_DISABLED = 1
HUBP_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_TTU_DISABLE'
HUBP_TTU_DISABLE__enumvalues = {
0: 'HUBP_TTU_ENABLED',
1: 'HUBP_TTU_DISABLED',
}
HUBP_TTU_ENABLED = 0
HUBP_TTU_DISABLED = 1
HUBP_TTU_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_NO_OUTSTANDING_REQ'
HUBP_NO_OUTSTANDING_REQ__enumvalues = {
0: 'OUTSTANDING_REQ',
1: 'NO_OUTSTANDING_REQ',
}
OUTSTANDING_REQ = 0
NO_OUTSTANDING_REQ = 1
HUBP_NO_OUTSTANDING_REQ = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_IN_BLANK'
HUBP_IN_BLANK__enumvalues = {
0: 'HUBP_IN_ACTIVE',
1: 'HUBP_IN_VBLANK',
}
HUBP_IN_ACTIVE = 0
HUBP_IN_VBLANK = 1
HUBP_IN_BLANK = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_VTG_SEL'
HUBP_VTG_SEL__enumvalues = {
0: 'VTG_SEL_0',
1: 'VTG_SEL_1',
2: 'VTG_SEL_2',
3: 'VTG_SEL_3',
4: 'VTG_SEL_4',
5: 'VTG_SEL_5',
}
VTG_SEL_0 = 0
VTG_SEL_1 = 1
VTG_SEL_2 = 2
VTG_SEL_3 = 3
VTG_SEL_4 = 4
VTG_SEL_5 = 5
HUBP_VTG_SEL = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_VREADY_AT_OR_AFTER_VSYNC'
HUBP_VREADY_AT_OR_AFTER_VSYNC__enumvalues = {
0: 'VREADY_BEFORE_VSYNC',
1: 'VREADY_AT_OR_AFTER_VSYNC',
}
VREADY_BEFORE_VSYNC = 0
VREADY_AT_OR_AFTER_VSYNC = 1
HUBP_VREADY_AT_OR_AFTER_VSYNC = ctypes.c_uint32 # enum
# values for enumeration 'VMPG_SIZE'
VMPG_SIZE__enumvalues = {
0: 'VMPG_SIZE_4KB',
1: 'VMPG_SIZE_64KB',
}
VMPG_SIZE_4KB = 0
VMPG_SIZE_64KB = 1
VMPG_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_MEASURE_WIN_MODE_DCFCLK'
HUBP_MEASURE_WIN_MODE_DCFCLK__enumvalues = {
0: 'HUBP_MEASURE_WIN_MODE_DCFCLK_0',
1: 'HUBP_MEASURE_WIN_MODE_DCFCLK_1',
2: 'HUBP_MEASURE_WIN_MODE_DCFCLK_2',
3: 'HUBP_MEASURE_WIN_MODE_DCFCLK_3',
}
HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0
HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 1
HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 2
HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 3
HUBP_MEASURE_WIN_MODE_DCFCLK = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_TMZ'
SURFACE_TMZ__enumvalues = {
0: 'SURFACE_IS_NOT_TMZ',
1: 'SURFACE_IS_TMZ',
}
SURFACE_IS_NOT_TMZ = 0
SURFACE_IS_TMZ = 1
SURFACE_TMZ = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_DCC'
SURFACE_DCC__enumvalues = {
0: 'SURFACE_IS_NOT_DCC',
1: 'SURFACE_IS_DCC',
}
SURFACE_IS_NOT_DCC = 0
SURFACE_IS_DCC = 1
SURFACE_DCC = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_DCC_IND_64B'
SURFACE_DCC_IND_64B__enumvalues = {
0: 'SURFACE_DCC_IS_NOT_IND_64B',
1: 'SURFACE_DCC_IS_IND_64B',
}
SURFACE_DCC_IS_NOT_IND_64B = 0
SURFACE_DCC_IS_IND_64B = 1
SURFACE_DCC_IND_64B = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_TYPE'
SURFACE_FLIP_TYPE__enumvalues = {
0: 'SURFACE_V_FLIP',
1: 'SURFACE_I_FLIP',
}
SURFACE_V_FLIP = 0
SURFACE_I_FLIP = 1
SURFACE_FLIP_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_MODE_FOR_STEREOSYNC'
SURFACE_FLIP_MODE_FOR_STEREOSYNC__enumvalues = {
0: 'FLIP_ANY_FRAME',
1: 'FLIP_LEFT_EYE',
2: 'FLIP_RIGHT_EYE',
3: 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED',
}
FLIP_ANY_FRAME = 0
FLIP_LEFT_EYE = 1
FLIP_RIGHT_EYE = 2
SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 3
SURFACE_FLIP_MODE_FOR_STEREOSYNC = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_UPDATE_LOCK'
SURFACE_UPDATE_LOCK__enumvalues = {
0: 'SURFACE_UPDATE_IS_UNLOCKED',
1: 'SURFACE_UPDATE_IS_LOCKED',
}
SURFACE_UPDATE_IS_UNLOCKED = 0
SURFACE_UPDATE_IS_LOCKED = 1
SURFACE_UPDATE_LOCK = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_IN_STEREOSYNC'
SURFACE_FLIP_IN_STEREOSYNC__enumvalues = {
0: 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE',
1: 'SURFACE_FLIP_IN_STEREOSYNC_MODE',
}
SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0
SURFACE_FLIP_IN_STEREOSYNC_MODE = 1
SURFACE_FLIP_IN_STEREOSYNC = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_DISABLE'
SURFACE_FLIP_STEREO_SELECT_DISABLE__enumvalues = {
0: 'SURFACE_FLIP_STEREO_SELECT_ENABLED',
1: 'SURFACE_FLIP_STEREO_SELECT_DISABLED',
}
SURFACE_FLIP_STEREO_SELECT_ENABLED = 0
SURFACE_FLIP_STEREO_SELECT_DISABLED = 1
SURFACE_FLIP_STEREO_SELECT_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_POLARITY'
SURFACE_FLIP_STEREO_SELECT_POLARITY__enumvalues = {
0: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT',
1: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT',
}
SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0
SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 1
SURFACE_FLIP_STEREO_SELECT_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_INUSE_RAED_NO_LATCH'
SURFACE_INUSE_RAED_NO_LATCH__enumvalues = {
0: 'SURFACE_INUSE_IS_LATCHED',
1: 'SURFACE_INUSE_IS_NOT_LATCHED',
}
SURFACE_INUSE_IS_LATCHED = 0
SURFACE_INUSE_IS_NOT_LATCHED = 1
SURFACE_INUSE_RAED_NO_LATCH = ctypes.c_uint32 # enum
# values for enumeration 'INT_MASK'
INT_MASK__enumvalues = {
0: 'INT_DISABLED',
1: 'INT_ENABLED',
}
INT_DISABLED = 0
INT_ENABLED = 1
INT_MASK = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_INT_TYPE'
SURFACE_FLIP_INT_TYPE__enumvalues = {
0: 'SURFACE_FLIP_INT_LEVEL',
1: 'SURFACE_FLIP_INT_PULSE',
}
SURFACE_FLIP_INT_LEVEL = 0
SURFACE_FLIP_INT_PULSE = 1
SURFACE_FLIP_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_AWAY_INT_TYPE'
SURFACE_FLIP_AWAY_INT_TYPE__enumvalues = {
0: 'SURFACE_FLIP_AWAY_INT_LEVEL',
1: 'SURFACE_FLIP_AWAY_INT_PULSE',
}
SURFACE_FLIP_AWAY_INT_LEVEL = 0
SURFACE_FLIP_AWAY_INT_PULSE = 1
SURFACE_FLIP_AWAY_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_VUPDATE_SKIP_NUM'
SURFACE_FLIP_VUPDATE_SKIP_NUM__enumvalues = {
0: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0',
1: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1',
2: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2',
3: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3',
4: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4',
5: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5',
6: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6',
7: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7',
8: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8',
9: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9',
10: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10',
11: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11',
12: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12',
13: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13',
14: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14',
15: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15',
}
SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0
SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 1
SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 2
SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 3
SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 4
SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 5
SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 6
SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 7
SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 8
SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 9
SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 10
SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 11
SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 12
SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 13
SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 14
SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 15
SURFACE_FLIP_VUPDATE_SKIP_NUM = ctypes.c_uint32 # enum
# values for enumeration 'DFQ_SIZE'
DFQ_SIZE__enumvalues = {
0: 'DFQ_SIZE_0',
1: 'DFQ_SIZE_1',
2: 'DFQ_SIZE_2',
3: 'DFQ_SIZE_3',
4: 'DFQ_SIZE_4',
5: 'DFQ_SIZE_5',
6: 'DFQ_SIZE_6',
7: 'DFQ_SIZE_7',
}
DFQ_SIZE_0 = 0
DFQ_SIZE_1 = 1
DFQ_SIZE_2 = 2
DFQ_SIZE_3 = 3
DFQ_SIZE_4 = 4
DFQ_SIZE_5 = 5
DFQ_SIZE_6 = 6
DFQ_SIZE_7 = 7
DFQ_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'DFQ_MIN_FREE_ENTRIES'
DFQ_MIN_FREE_ENTRIES__enumvalues = {
0: 'DFQ_MIN_FREE_ENTRIES_0',
1: 'DFQ_MIN_FREE_ENTRIES_1',
2: 'DFQ_MIN_FREE_ENTRIES_2',
3: 'DFQ_MIN_FREE_ENTRIES_3',
4: 'DFQ_MIN_FREE_ENTRIES_4',
5: 'DFQ_MIN_FREE_ENTRIES_5',
6: 'DFQ_MIN_FREE_ENTRIES_6',
7: 'DFQ_MIN_FREE_ENTRIES_7',
}
DFQ_MIN_FREE_ENTRIES_0 = 0
DFQ_MIN_FREE_ENTRIES_1 = 1
DFQ_MIN_FREE_ENTRIES_2 = 2
DFQ_MIN_FREE_ENTRIES_3 = 3
DFQ_MIN_FREE_ENTRIES_4 = 4
DFQ_MIN_FREE_ENTRIES_5 = 5
DFQ_MIN_FREE_ENTRIES_6 = 6
DFQ_MIN_FREE_ENTRIES_7 = 7
DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum
# values for enumeration 'DFQ_NUM_ENTRIES'
DFQ_NUM_ENTRIES__enumvalues = {
0: 'DFQ_NUM_ENTRIES_0',
1: 'DFQ_NUM_ENTRIES_1',
2: 'DFQ_NUM_ENTRIES_2',
3: 'DFQ_NUM_ENTRIES_3',
4: 'DFQ_NUM_ENTRIES_4',
5: 'DFQ_NUM_ENTRIES_5',
6: 'DFQ_NUM_ENTRIES_6',
7: 'DFQ_NUM_ENTRIES_7',
8: 'DFQ_NUM_ENTRIES_8',
}
DFQ_NUM_ENTRIES_0 = 0
DFQ_NUM_ENTRIES_1 = 1
DFQ_NUM_ENTRIES_2 = 2
DFQ_NUM_ENTRIES_3 = 3
DFQ_NUM_ENTRIES_4 = 4
DFQ_NUM_ENTRIES_5 = 5
DFQ_NUM_ENTRIES_6 = 6
DFQ_NUM_ENTRIES_7 = 7
DFQ_NUM_ENTRIES_8 = 8
DFQ_NUM_ENTRIES = ctypes.c_uint32 # enum
# values for enumeration 'FLIP_RATE'
FLIP_RATE__enumvalues = {
0: 'FLIP_RATE_0',
1: 'FLIP_RATE_1',
2: 'FLIP_RATE_2',
3: 'FLIP_RATE_3',
4: 'FLIP_RATE_4',
5: 'FLIP_RATE_5',
6: 'FLIP_RATE_6',
7: 'FLIP_RATE_7',
}
FLIP_RATE_0 = 0
FLIP_RATE_1 = 1
FLIP_RATE_2 = 2
FLIP_RATE_3 = 3
FLIP_RATE_4 = 4
FLIP_RATE_5 = 5
FLIP_RATE_6 = 6
FLIP_RATE_7 = 7
FLIP_RATE = ctypes.c_uint32 # enum
# values for enumeration 'DETILE_BUFFER_PACKER_ENABLE'
DETILE_BUFFER_PACKER_ENABLE__enumvalues = {
0: 'DETILE_BUFFER_PACKER_IS_DISABLE',
1: 'DETILE_BUFFER_PACKER_IS_ENABLE',
}
DETILE_BUFFER_PACKER_IS_DISABLE = 0
DETILE_BUFFER_PACKER_IS_ENABLE = 1
DETILE_BUFFER_PACKER_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'CROSSBAR_FOR_ALPHA'
CROSSBAR_FOR_ALPHA__enumvalues = {
0: 'ALPHA_DATA_ON_ALPHA_PORT',
1: 'ALPHA_DATA_ON_Y_G_PORT',
2: 'ALPHA_DATA_ON_CB_B_PORT',
3: 'ALPHA_DATA_ON_CR_R_PORT',
}
ALPHA_DATA_ON_ALPHA_PORT = 0
ALPHA_DATA_ON_Y_G_PORT = 1
ALPHA_DATA_ON_CB_B_PORT = 2
ALPHA_DATA_ON_CR_R_PORT = 3
CROSSBAR_FOR_ALPHA = ctypes.c_uint32 # enum
# values for enumeration 'CROSSBAR_FOR_Y_G'
CROSSBAR_FOR_Y_G__enumvalues = {
0: 'Y_G_DATA_ON_ALPHA_PORT',
1: 'Y_G_DATA_ON_Y_G_PORT',
2: 'Y_G_DATA_ON_CB_B_PORT',
3: 'Y_G_DATA_ON_CR_R_PORT',
}
Y_G_DATA_ON_ALPHA_PORT = 0
Y_G_DATA_ON_Y_G_PORT = 1
Y_G_DATA_ON_CB_B_PORT = 2
Y_G_DATA_ON_CR_R_PORT = 3
CROSSBAR_FOR_Y_G = ctypes.c_uint32 # enum
# values for enumeration 'CROSSBAR_FOR_CB_B'
CROSSBAR_FOR_CB_B__enumvalues = {
0: 'CB_B_DATA_ON_ALPHA_PORT',
1: 'CB_B_DATA_ON_Y_G_PORT',
2: 'CB_B_DATA_ON_CB_B_PORT',
3: 'CB_B_DATA_ON_CR_R_PORT',
}
CB_B_DATA_ON_ALPHA_PORT = 0
CB_B_DATA_ON_Y_G_PORT = 1
CB_B_DATA_ON_CB_B_PORT = 2
CB_B_DATA_ON_CR_R_PORT = 3
CROSSBAR_FOR_CB_B = ctypes.c_uint32 # enum
# values for enumeration 'CROSSBAR_FOR_CR_R'
CROSSBAR_FOR_CR_R__enumvalues = {
0: 'CR_R_DATA_ON_ALPHA_PORT',
1: 'CR_R_DATA_ON_Y_G_PORT',
2: 'CR_R_DATA_ON_CB_B_PORT',
3: 'CR_R_DATA_ON_CR_R_PORT',
}
CR_R_DATA_ON_ALPHA_PORT = 0
CR_R_DATA_ON_Y_G_PORT = 1
CR_R_DATA_ON_CB_B_PORT = 2
CR_R_DATA_ON_CR_R_PORT = 3
CROSSBAR_FOR_CR_R = ctypes.c_uint32 # enum
# values for enumeration 'DET_MEM_PWR_LIGHT_SLEEP_MODE'
DET_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = {
0: 'DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
1: 'DET_MEM_POWER_LIGHT_SLEEP_MODE_1',
2: 'DET_MEM_POWER_LIGHT_SLEEP_MODE_2',
}
DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0
DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1
DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2
DET_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE'
PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = {
0: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
1: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1',
}
PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0
PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1
PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_ENABLE'
CURSOR_ENABLE__enumvalues = {
0: 'CURSOR_IS_DISABLE',
1: 'CURSOR_IS_ENABLE',
}
CURSOR_IS_DISABLE = 0
CURSOR_IS_ENABLE = 1
CURSOR_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_2X_MAGNIFY'
CURSOR_2X_MAGNIFY__enumvalues = {
0: 'CURSOR_2X_MAGNIFY_IS_DISABLE',
1: 'CURSOR_2X_MAGNIFY_IS_ENABLE',
}
CURSOR_2X_MAGNIFY_IS_DISABLE = 0
CURSOR_2X_MAGNIFY_IS_ENABLE = 1
CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_MODE'
CURSOR_MODE__enumvalues = {
0: 'CURSOR_MONO_2BIT',
1: 'CURSOR_COLOR_24BIT_1BIT_AND',
2: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT',
3: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT',
4: 'CURSOR_COLOR_64BIT_FP_PREMULT',
5: 'CURSOR_COLOR_64BIT_FP_UNPREMULT',
}
CURSOR_MONO_2BIT = 0
CURSOR_COLOR_24BIT_1BIT_AND = 1
CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 2
CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3
CURSOR_COLOR_64BIT_FP_PREMULT = 4
CURSOR_COLOR_64BIT_FP_UNPREMULT = 5
CURSOR_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_SURFACE_TMZ'
CURSOR_SURFACE_TMZ__enumvalues = {
0: 'CURSOR_SURFACE_IS_NOT_TMZ',
1: 'CURSOR_SURFACE_IS_TMZ',
}
CURSOR_SURFACE_IS_NOT_TMZ = 0
CURSOR_SURFACE_IS_TMZ = 1
CURSOR_SURFACE_TMZ = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_SNOOP'
CURSOR_SNOOP__enumvalues = {
0: 'CURSOR_IS_NOT_SNOOP',
1: 'CURSOR_IS_SNOOP',
}
CURSOR_IS_NOT_SNOOP = 0
CURSOR_IS_SNOOP = 1
CURSOR_SNOOP = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_SYSTEM'
CURSOR_SYSTEM__enumvalues = {
0: 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS',
1: 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS',
}
CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0
CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 1
CURSOR_SYSTEM = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_PITCH'
CURSOR_PITCH__enumvalues = {
0: 'CURSOR_PITCH_64_PIXELS',
1: 'CURSOR_PITCH_128_PIXELS',
2: 'CURSOR_PITCH_256_PIXELS',
}
CURSOR_PITCH_64_PIXELS = 0
CURSOR_PITCH_128_PIXELS = 1
CURSOR_PITCH_256_PIXELS = 2
CURSOR_PITCH = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_LINES_PER_CHUNK'
CURSOR_LINES_PER_CHUNK__enumvalues = {
0: 'CURSOR_LINE_PER_CHUNK_1',
1: 'CURSOR_LINE_PER_CHUNK_2',
2: 'CURSOR_LINE_PER_CHUNK_4',
3: 'CURSOR_LINE_PER_CHUNK_8',
4: 'CURSOR_LINE_PER_CHUNK_16',
}
CURSOR_LINE_PER_CHUNK_1 = 0
CURSOR_LINE_PER_CHUNK_2 = 1
CURSOR_LINE_PER_CHUNK_4 = 2
CURSOR_LINE_PER_CHUNK_8 = 3
CURSOR_LINE_PER_CHUNK_16 = 4
CURSOR_LINES_PER_CHUNK = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_EN'
CURSOR_PERFMON_LATENCY_MEASURE_EN__enumvalues = {
0: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED',
1: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED',
}
CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0
CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 1
CURSOR_PERFMON_LATENCY_MEASURE_EN = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_SEL'
CURSOR_PERFMON_LATENCY_MEASURE_SEL__enumvalues = {
0: 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY',
1: 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY',
}
CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0
CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 1
CURSOR_PERFMON_LATENCY_MEASURE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_STEREO_EN'
CURSOR_STEREO_EN__enumvalues = {
0: 'CURSOR_STEREO_IS_DISABLED',
1: 'CURSOR_STEREO_IS_ENABLED',
}
CURSOR_STEREO_IS_DISABLED = 0
CURSOR_STEREO_IS_ENABLED = 1
CURSOR_STEREO_EN = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS'
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__enumvalues = {
0: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0',
1: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1',
}
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 1
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'CROB_MEM_PWR_LIGHT_SLEEP_MODE'
CROB_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = {
0: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
1: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1',
2: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2',
}
CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0
CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1
CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2
CROB_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_UPDATED'
DMDATA_UPDATED__enumvalues = {
0: 'DMDATA_NOT_UPDATED',
1: 'DMDATA_WAS_UPDATED',
}
DMDATA_NOT_UPDATED = 0
DMDATA_WAS_UPDATED = 1
DMDATA_UPDATED = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_REPEAT'
DMDATA_REPEAT__enumvalues = {
0: 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY',
1: 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES',
}
DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0
DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 1
DMDATA_REPEAT = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_MODE'
DMDATA_MODE__enumvalues = {
0: 'DMDATA_SOFTWARE_UPDATE_MODE',
1: 'DMDATA_HARDWARE_UPDATE_MODE',
}
DMDATA_SOFTWARE_UPDATE_MODE = 0
DMDATA_HARDWARE_UPDATE_MODE = 1
DMDATA_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_QOS_MODE'
DMDATA_QOS_MODE__enumvalues = {
0: 'DMDATA_QOS_LEVEL_FROM_TTU',
1: 'DMDATA_QOS_LEVEL_FROM_SOFTWARE',
}
DMDATA_QOS_LEVEL_FROM_TTU = 0
DMDATA_QOS_LEVEL_FROM_SOFTWARE = 1
DMDATA_QOS_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_DONE'
DMDATA_DONE__enumvalues = {
0: 'DMDATA_NOT_SENT_TO_DIG',
1: 'DMDATA_SENT_TO_DIG',
}
DMDATA_NOT_SENT_TO_DIG = 0
DMDATA_SENT_TO_DIG = 1
DMDATA_DONE = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_UNDERFLOW'
DMDATA_UNDERFLOW__enumvalues = {
0: 'DMDATA_NOT_UNDERFLOW',
1: 'DMDATA_UNDERFLOWED',
}
DMDATA_NOT_UNDERFLOW = 0
DMDATA_UNDERFLOWED = 1
DMDATA_UNDERFLOW = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_UNDERFLOW_CLEAR'
DMDATA_UNDERFLOW_CLEAR__enumvalues = {
0: 'DMDATA_DONT_CLEAR',
1: 'DMDATA_CLEAR_UNDERFLOW_STATUS',
}
DMDATA_DONT_CLEAR = 0
DMDATA_CLEAR_UNDERFLOW_STATUS = 1
DMDATA_UNDERFLOW_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_XFC_PIXEL_FORMAT_ENUM'
HUBP_XFC_PIXEL_FORMAT_ENUM__enumvalues = {
0: 'HUBP_XFC_PIXEL_IS_32BPP',
1: 'HUBP_XFC_PIXEL_IS_64BPP',
}
HUBP_XFC_PIXEL_IS_32BPP = 0
HUBP_XFC_PIXEL_IS_64BPP = 1
HUBP_XFC_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_XFC_FRAME_MODE_ENUM'
HUBP_XFC_FRAME_MODE_ENUM__enumvalues = {
0: 'HUBP_XFC_PARTIAL_FRAME_MODE',
1: 'HUBP_XFC_FULL_FRAME_MODE',
}
HUBP_XFC_PARTIAL_FRAME_MODE = 0
HUBP_XFC_FULL_FRAME_MODE = 1
HUBP_XFC_FRAME_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_XFC_CHUNK_SIZE_ENUM'
HUBP_XFC_CHUNK_SIZE_ENUM__enumvalues = {
0: 'HUBP_XFC_CHUNK_SIZE_256B',
1: 'HUBP_XFC_CHUNK_SIZE_512B',
2: 'HUBP_XFC_CHUNK_SIZE_1KB',
3: 'HUBP_XFC_CHUNK_SIZE_2KB',
4: 'HUBP_XFC_CHUNK_SIZE_4KB',
5: 'HUBP_XFC_CHUNK_SIZE_8KB',
6: 'HUBP_XFC_CHUNK_SIZE_16KB',
7: 'HUBP_XFC_CHUNK_SIZE_32KB',
}
HUBP_XFC_CHUNK_SIZE_256B = 0
HUBP_XFC_CHUNK_SIZE_512B = 1
HUBP_XFC_CHUNK_SIZE_1KB = 2
HUBP_XFC_CHUNK_SIZE_2KB = 3
HUBP_XFC_CHUNK_SIZE_4KB = 4
HUBP_XFC_CHUNK_SIZE_8KB = 5
HUBP_XFC_CHUNK_SIZE_16KB = 6
HUBP_XFC_CHUNK_SIZE_32KB = 7
HUBP_XFC_CHUNK_SIZE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MMHUBBUB_XFC_XFCMON_MODE_ENUM'
MMHUBBUB_XFC_XFCMON_MODE_ENUM__enumvalues = {
0: 'MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT',
1: 'MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS',
2: 'MMHUBBUB_XFC_XFCMON_MODE_PERIODS',
}
MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT = 0
MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS = 1
MMHUBBUB_XFC_XFCMON_MODE_PERIODS = 2
MMHUBBUB_XFC_XFCMON_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM'
MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM__enumvalues = {
0: 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB',
1: 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB',
}
MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB = 0
MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB = 1
MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MMHUBBUB_XFC_PIXEL_FORMAT_ENUM'
MMHUBBUB_XFC_PIXEL_FORMAT_ENUM__enumvalues = {
0: 'MMHUBBUB_XFC_PIXEL_IS_32BPP',
1: 'MMHUBBUB_XFC_PIXEL_IS_64BPP',
}
MMHUBBUB_XFC_PIXEL_IS_32BPP = 0
MMHUBBUB_XFC_PIXEL_IS_64BPP = 1
MMHUBBUB_XFC_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MMHUBBUB_XFC_FRAME_MODE_ENUM'
MMHUBBUB_XFC_FRAME_MODE_ENUM__enumvalues = {
0: 'MMHUBBUB_XFC_PARTIAL_FRAME_MODE',
1: 'MMHUBBUB_XFC_FULL_FRAME_MODE',
}
MMHUBBUB_XFC_PARTIAL_FRAME_MODE = 0
MMHUBBUB_XFC_FULL_FRAME_MODE = 1
MMHUBBUB_XFC_FRAME_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_MPC_TEST_CLK_SEL'
MPC_CFG_MPC_TEST_CLK_SEL__enumvalues = {
0: 'MPC_CFG_MPC_TEST_CLK_SEL_0',
1: 'MPC_CFG_MPC_TEST_CLK_SEL_1',
2: 'MPC_CFG_MPC_TEST_CLK_SEL_2',
3: 'MPC_CFG_MPC_TEST_CLK_SEL_3',
}
MPC_CFG_MPC_TEST_CLK_SEL_0 = 0
MPC_CFG_MPC_TEST_CLK_SEL_1 = 1
MPC_CFG_MPC_TEST_CLK_SEL_2 = 2
MPC_CFG_MPC_TEST_CLK_SEL_3 = 3
MPC_CFG_MPC_TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CRC_CALC_MODE'
MPC_CRC_CALC_MODE__enumvalues = {
0: 'MPC_CRC_ONE_SHOT_MODE',
1: 'MPC_CRC_CONTINUOUS_MODE',
}
MPC_CRC_ONE_SHOT_MODE = 0
MPC_CRC_CONTINUOUS_MODE = 1
MPC_CRC_CALC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CRC_CALC_STEREO_MODE'
MPC_CRC_CALC_STEREO_MODE__enumvalues = {
0: 'MPC_CRC_STEREO_MODE_LEFT',
1: 'MPC_CRC_STEREO_MODE_RIGHT',
2: 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT',
3: 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH',
}
MPC_CRC_STEREO_MODE_LEFT = 0
MPC_CRC_STEREO_MODE_RIGHT = 1
MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 2
MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 3
MPC_CRC_CALC_STEREO_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CRC_CALC_INTERLACE_MODE'
MPC_CRC_CALC_INTERLACE_MODE__enumvalues = {
0: 'MPC_CRC_INTERLACE_MODE_TOP',
1: 'MPC_CRC_INTERLACE_MODE_BOTTOM',
2: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM',
3: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH',
}
MPC_CRC_INTERLACE_MODE_TOP = 0
MPC_CRC_INTERLACE_MODE_BOTTOM = 1
MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 2
MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 3
MPC_CRC_CALC_INTERLACE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CRC_SOURCE_SELECT'
MPC_CRC_SOURCE_SELECT__enumvalues = {
0: 'MPC_CRC_SOURCE_SEL_DPP',
1: 'MPC_CRC_SOURCE_SEL_OPP',
2: 'MPC_CRC_SOURCE_SEL_DWB',
3: 'MPC_CRC_SOURCE_SEL_OTHER',
}
MPC_CRC_SOURCE_SEL_DPP = 0
MPC_CRC_SOURCE_SEL_OPP = 1
MPC_CRC_SOURCE_SEL_DWB = 2
MPC_CRC_SOURCE_SEL_OTHER = 3
MPC_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET'
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET'
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_CFG_VUPDATE_LOCK_SET'
MPC_CFG_CFG_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_ADR_VUPDATE_LOCK_SET'
MPC_CFG_ADR_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_ADR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_CUR_VUPDATE_LOCK_SET'
MPC_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OUT_RATE_CONTROL_DISABLE_SET'
MPC_OUT_RATE_CONTROL_DISABLE_SET__enumvalues = {
0: 'MPC_OUT_RATE_CONTROL_SET_ENABLE',
1: 'MPC_OUT_RATE_CONTROL_SET_DISABLE',
}
MPC_OUT_RATE_CONTROL_SET_ENABLE = 0
MPC_OUT_RATE_CONTROL_SET_DISABLE = 1
MPC_OUT_RATE_CONTROL_DISABLE_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE'
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE__enumvalues = {
0: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS',
1: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS',
2: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS',
3: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS',
4: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS',
5: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS',
6: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS',
7: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH',
}
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 1
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 2
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 3
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 4
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 5
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 6
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 7
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OCSC_COEF_FORMAT'
MPC_OCSC_COEF_FORMAT__enumvalues = {
0: 'MPC_OCSC_COEF_FORMAT_S2_13',
1: 'MPC_OCSC_COEF_FORMAT_S3_12',
}
MPC_OCSC_COEF_FORMAT_S2_13 = 0
MPC_OCSC_COEF_FORMAT_S3_12 = 1
MPC_OCSC_COEF_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OUT_CSC_MODE'
MPC_OUT_CSC_MODE__enumvalues = {
0: 'MPC_OUT_CSC_MODE_0',
1: 'MPC_OUT_CSC_MODE_1',
2: 'MPC_OUT_CSC_MODE_2',
3: 'MPC_OUT_CSC_MODE_RSV',
}
MPC_OUT_CSC_MODE_0 = 0
MPC_OUT_CSC_MODE_1 = 1
MPC_OUT_CSC_MODE_2 = 2
MPC_OUT_CSC_MODE_RSV = 3
MPC_OUT_CSC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_MODE'
MPCC_CONTROL_MPCC_MODE__enumvalues = {
0: 'MPCC_CONTROL_MPCC_MODE_BYPASS',
1: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH',
2: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY',
3: 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING',
}
MPCC_CONTROL_MPCC_MODE_BYPASS = 0
MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 1
MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 2
MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 3
MPCC_CONTROL_MPCC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE'
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE__enumvalues = {
0: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA',
1: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN',
2: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA',
3: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED',
}
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 2
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 3
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE'
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE__enumvalues = {
0: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE',
1: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE',
}
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 1
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY'
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY__enumvalues = {
0: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE',
1: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE',
}
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 1
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_EN'
MPCC_SM_CONTROL_MPCC_SM_EN__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE',
1: 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE',
}
MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0
MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 1
MPCC_SM_CONTROL_MPCC_SM_EN = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_MODE'
MPCC_SM_CONTROL_MPCC_SM_MODE__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE',
2: 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING',
4: 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING',
6: 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING',
}
MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0
MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 2
MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 4
MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6
MPCC_SM_CONTROL_MPCC_SM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT'
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE',
1: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE',
}
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 1
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT'
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE',
1: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE',
}
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 1
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL'
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE',
1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED',
2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW',
3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH',
}
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL'
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE',
1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED',
2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW',
3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH',
}
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 1
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK'
MPCC_STALL_STATUS_MPCC_STALL_INT_ACK__enumvalues = {
0: 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE',
1: 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE',
}
MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE = 0
MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE = 1
MPCC_STALL_STATUS_MPCC_STALL_INT_ACK = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK'
MPCC_STALL_STATUS_MPCC_STALL_INT_MASK__enumvalues = {
0: 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE',
1: 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE',
}
MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE = 0
MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE = 1
MPCC_STALL_STATUS_MPCC_STALL_INT_MASK = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_BG_COLOR_BPC'
MPCC_BG_COLOR_BPC__enumvalues = {
0: 'MPCC_BG_COLOR_BPC_8bit',
1: 'MPCC_BG_COLOR_BPC_9bit',
2: 'MPCC_BG_COLOR_BPC_10bit',
3: 'MPCC_BG_COLOR_BPC_11bit',
4: 'MPCC_BG_COLOR_BPC_12bit',
}
MPCC_BG_COLOR_BPC_8bit = 0
MPCC_BG_COLOR_BPC_9bit = 1
MPCC_BG_COLOR_BPC_10bit = 2
MPCC_BG_COLOR_BPC_11bit = 3
MPCC_BG_COLOR_BPC_12bit = 4
MPCC_BG_COLOR_BPC = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE'
MPCC_CONTROL_MPCC_BOT_GAIN_MODE__enumvalues = {
0: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0',
1: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1',
}
MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0
MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 1
MPCC_CONTROL_MPCC_BOT_GAIN_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL'
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL__enumvalues = {
0: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA',
1: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB',
}
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 1
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_MODE_MPCC_OGAM_MODE'
MPCC_OGAM_MODE_MPCC_OGAM_MODE__enumvalues = {
0: 'MPCC_OGAM_MODE_0',
1: 'MPCC_OGAM_MODE_1',
2: 'MPCC_OGAM_MODE_2',
3: 'MPCC_OGAM_MODE_RSV',
}
MPCC_OGAM_MODE_0 = 0
MPCC_OGAM_MODE_1 = 1
MPCC_OGAM_MODE_2 = 2
MPCC_OGAM_MODE_RSV = 3
MPCC_OGAM_MODE_MPCC_OGAM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_EN'
ENUM_DPG_EN__enumvalues = {
0: 'ENUM_DPG_DISABLE',
1: 'ENUM_DPG_ENABLE',
}
ENUM_DPG_DISABLE = 0
ENUM_DPG_ENABLE = 1
ENUM_DPG_EN = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_MODE'
ENUM_DPG_MODE__enumvalues = {
0: 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK',
1: 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK',
2: 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK',
3: 'ENUM_DPG_MODE_VERTICAL_BAR',
4: 'ENUM_DPG_MODE_HORIZONTAL_BAR',
5: 'ENUM_DPG_MODE_RGB_SINGLE_RAMP',
6: 'ENUM_DPG_MODE_RGB_DUAL_RAMP',
7: 'ENUM_DPG_MODE_RGB_XR_BIAS',
}
ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0
ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 1
ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 2
ENUM_DPG_MODE_VERTICAL_BAR = 3
ENUM_DPG_MODE_HORIZONTAL_BAR = 4
ENUM_DPG_MODE_RGB_SINGLE_RAMP = 5
ENUM_DPG_MODE_RGB_DUAL_RAMP = 6
ENUM_DPG_MODE_RGB_XR_BIAS = 7
ENUM_DPG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_DYNAMIC_RANGE'
ENUM_DPG_DYNAMIC_RANGE__enumvalues = {
0: 'ENUM_DPG_DYNAMIC_RANGE_VESA',
1: 'ENUM_DPG_DYNAMIC_RANGE_CEA',
}
ENUM_DPG_DYNAMIC_RANGE_VESA = 0
ENUM_DPG_DYNAMIC_RANGE_CEA = 1
ENUM_DPG_DYNAMIC_RANGE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_BIT_DEPTH'
ENUM_DPG_BIT_DEPTH__enumvalues = {
0: 'ENUM_DPG_BIT_DEPTH_6BPC',
1: 'ENUM_DPG_BIT_DEPTH_8BPC',
2: 'ENUM_DPG_BIT_DEPTH_10BPC',
3: 'ENUM_DPG_BIT_DEPTH_12BPC',
}
ENUM_DPG_BIT_DEPTH_6BPC = 0
ENUM_DPG_BIT_DEPTH_8BPC = 1
ENUM_DPG_BIT_DEPTH_10BPC = 2
ENUM_DPG_BIT_DEPTH_12BPC = 3
ENUM_DPG_BIT_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_FIELD_POLARITY'
ENUM_DPG_FIELD_POLARITY__enumvalues = {
0: 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD',
1: 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN',
}
ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0
ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1
ENUM_DPG_FIELD_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING'
FMT_CONTROL_PIXEL_ENCODING__enumvalues = {
0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444',
1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422',
2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420',
3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED',
}
FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0
FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1
FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2
FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3
FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE'
FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = {
0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP',
1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE',
2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP',
3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED',
}
FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0
FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1
FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2
FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3
FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER'
FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = {
0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR',
1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB',
}
FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0
FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1
FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS'
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = {
0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE',
1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE',
}
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE'
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION',
1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING',
}
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH'
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP',
1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP',
2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP',
}
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH'
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP',
1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP',
2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP',
}
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH'
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP',
1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP',
2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP',
}
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL'
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2',
1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4',
}
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL'
FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei',
1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi',
2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi',
3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED',
}
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3
FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL'
FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A',
1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B',
2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C',
3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D',
}
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3
FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL'
FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E',
1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F',
2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G',
3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED',
}
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3
FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0'
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = {
0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR',
1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB',
}
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT'
FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = {
0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC',
1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC',
2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC',
3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC',
4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1',
5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2',
6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3',
7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE',
}
FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0
FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1
FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2
FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6
FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7
FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'FMT_SPATIAL_DITHER_MODE'
FMT_SPATIAL_DITHER_MODE__enumvalues = {
0: 'FMT_SPATIAL_DITHER_MODE_0',
1: 'FMT_SPATIAL_DITHER_MODE_1',
2: 'FMT_SPATIAL_DITHER_MODE_2',
3: 'FMT_SPATIAL_DITHER_MODE_3',
}
FMT_SPATIAL_DITHER_MODE_0 = 0
FMT_SPATIAL_DITHER_MODE_1 = 1
FMT_SPATIAL_DITHER_MODE_2 = 2
FMT_SPATIAL_DITHER_MODE_3 = 3
FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMT_DYNAMIC_EXP_MODE'
FMT_DYNAMIC_EXP_MODE__enumvalues = {
0: 'FMT_DYNAMIC_EXP_MODE_10to12',
1: 'FMT_DYNAMIC_EXP_MODE_8to12',
}
FMT_DYNAMIC_EXP_MODE_10to12 = 0
FMT_DYNAMIC_EXP_MODE_8to12 = 1
FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMTMEM_PWR_FORCE_CTRL'
FMTMEM_PWR_FORCE_CTRL__enumvalues = {
0: 'FMTMEM_NO_FORCE_REQUEST',
1: 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST',
3: 'FMTMEM_FORCE_SHUT_DOWN_REQUEST',
}
FMTMEM_NO_FORCE_REQUEST = 0
FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 1
FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 2
FMTMEM_FORCE_SHUT_DOWN_REQUEST = 3
FMTMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'FMTMEM_PWR_DIS_CTRL'
FMTMEM_PWR_DIS_CTRL__enumvalues = {
0: 'FMTMEM_ENABLE_MEM_PWR_CTRL',
1: 'FMTMEM_DISABLE_MEM_PWR_CTRL',
}
FMTMEM_ENABLE_MEM_PWR_CTRL = 0
FMTMEM_DISABLE_MEM_PWR_CTRL = 1
FMTMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_POWER_STATE_ENUM'
FMT_POWER_STATE_ENUM__enumvalues = {
0: 'FMT_POWER_STATE_ENUM_ON',
1: 'FMT_POWER_STATE_ENUM_LS',
2: 'FMT_POWER_STATE_ENUM_DS',
3: 'FMT_POWER_STATE_ENUM_SD',
}
FMT_POWER_STATE_ENUM_ON = 0
FMT_POWER_STATE_ENUM_LS = 1
FMT_POWER_STATE_ENUM_DS = 2
FMT_POWER_STATE_ENUM_SD = 3
FMT_POWER_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'FMT_STEREOSYNC_OVERRIDE_CONTROL'
FMT_STEREOSYNC_OVERRIDE_CONTROL__enumvalues = {
0: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0',
1: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1',
}
FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0
FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 1
FMT_STEREOSYNC_OVERRIDE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL'
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL__enumvalues = {
0: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP',
1: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1',
2: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2',
3: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED',
}
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 1
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 2
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 3
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_FRAME_RANDOM_ENABLE_CONTROL'
FMT_FRAME_RANDOM_ENABLE_CONTROL__enumvalues = {
0: 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME',
1: 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE',
}
FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0
FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 1
FMT_FRAME_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_RGB_RANDOM_ENABLE_CONTROL'
FMT_RGB_RANDOM_ENABLE_CONTROL__enumvalues = {
0: 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE',
1: 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE',
}
FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0
FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 1
FMT_RGB_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_FMT_PTI_FIELD_POLARITY'
ENUM_FMT_PTI_FIELD_POLARITY__enumvalues = {
0: 'ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD',
1: 'ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN',
}
ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0
ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1
ENUM_FMT_PTI_FIELD_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CLOCK_ENABLE_CONTROL'
OPP_PIPE_CLOCK_ENABLE_CONTROL__enumvalues = {
0: 'OPP_PIPE_CLOCK_DISABLE',
1: 'OPP_PIPE_CLOCK_ENABLE',
}
OPP_PIPE_CLOCK_DISABLE = 0
OPP_PIPE_CLOCK_ENABLE = 1
OPP_PIPE_CLOCK_ENABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL'
OPP_PIPE_DIGTIAL_BYPASS_CONTROL__enumvalues = {
0: 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE',
1: 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE',
}
OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0
OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 1
OPP_PIPE_DIGTIAL_BYPASS_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_EN'
OPP_PIPE_CRC_EN__enumvalues = {
0: 'OPP_PIPE_CRC_DISABLE',
1: 'OPP_PIPE_CRC_ENABLE',
}
OPP_PIPE_CRC_DISABLE = 0
OPP_PIPE_CRC_ENABLE = 1
OPP_PIPE_CRC_EN = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_CONT_EN'
OPP_PIPE_CRC_CONT_EN__enumvalues = {
0: 'OPP_PIPE_CRC_MODE_ONE_SHOT',
1: 'OPP_PIPE_CRC_MODE_CONTINUOUS',
}
OPP_PIPE_CRC_MODE_ONE_SHOT = 0
OPP_PIPE_CRC_MODE_CONTINUOUS = 1
OPP_PIPE_CRC_CONT_EN = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_STEREO_MODE'
OPP_PIPE_CRC_STEREO_MODE__enumvalues = {
0: 'OPP_PIPE_CRC_STEREO_MODE_LEFT',
1: 'OPP_PIPE_CRC_STEREO_MODE_RIGHT',
2: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE',
3: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE',
}
OPP_PIPE_CRC_STEREO_MODE_LEFT = 0
OPP_PIPE_CRC_STEREO_MODE_RIGHT = 1
OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 2
OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 3
OPP_PIPE_CRC_STEREO_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_STEREO_EN'
OPP_PIPE_CRC_STEREO_EN__enumvalues = {
0: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO',
1: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO',
}
OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0
OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 1
OPP_PIPE_CRC_STEREO_EN = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_INTERLACE_MODE'
OPP_PIPE_CRC_INTERLACE_MODE__enumvalues = {
0: 'OPP_PIPE_CRC_INTERLACE_MODE_TOP',
1: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM',
2: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD',
3: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD',
}
OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0
OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 1
OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 2
OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 3
OPP_PIPE_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_INTERLACE_EN'
OPP_PIPE_CRC_INTERLACE_EN__enumvalues = {
0: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE',
1: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED',
}
OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0
OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 1
OPP_PIPE_CRC_INTERLACE_EN = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_PIXEL_SELECT'
OPP_PIPE_CRC_PIXEL_SELECT__enumvalues = {
0: 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS',
1: 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED',
2: 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS',
3: 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS',
}
OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0
OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 1
OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 2
OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 3
OPP_PIPE_CRC_PIXEL_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_SOURCE_SELECT'
OPP_PIPE_CRC_SOURCE_SELECT__enumvalues = {
0: 'OPP_PIPE_CRC_SOURCE_SELECT_FMT',
1: 'OPP_PIPE_CRC_SOURCE_SELECT_SFT',
}
OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0
OPP_PIPE_CRC_SOURCE_SELECT_SFT = 1
OPP_PIPE_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_ONE_SHOT_PENDING'
OPP_PIPE_CRC_ONE_SHOT_PENDING__enumvalues = {
0: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING',
1: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING',
}
OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0
OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 1
OPP_PIPE_CRC_ONE_SHOT_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'OPP_TOP_CLOCK_GATING_CONTROL'
OPP_TOP_CLOCK_GATING_CONTROL__enumvalues = {
0: 'OPP_TOP_CLOCK_GATING_ENABLED',
1: 'OPP_TOP_CLOCK_GATING_DISABLED',
}
OPP_TOP_CLOCK_GATING_ENABLED = 0
OPP_TOP_CLOCK_GATING_DISABLED = 1
OPP_TOP_CLOCK_GATING_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_TOP_CLOCK_ENABLE_STATUS'
OPP_TOP_CLOCK_ENABLE_STATUS__enumvalues = {
0: 'OPP_TOP_CLOCK_DISABLED_STATUS',
1: 'OPP_TOP_CLOCK_ENABLED_STATUS',
}
OPP_TOP_CLOCK_DISABLED_STATUS = 0
OPP_TOP_CLOCK_ENABLED_STATUS = 1
OPP_TOP_CLOCK_ENABLE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'OPP_TEST_CLK_SEL_CONTROL'
OPP_TEST_CLK_SEL_CONTROL__enumvalues = {
0: 'OPP_TEST_CLK_SEL_DISPCLK_P',
1: 'OPP_TEST_CLK_SEL_DISPCLK_R',
2: 'OPP_TEST_CLK_SEL_DISPCLK_ABM0',
3: 'OPP_TEST_CLK_SEL_RESERVED0',
4: 'OPP_TEST_CLK_SEL_DISPCLK_OPP0',
5: 'OPP_TEST_CLK_SEL_DISPCLK_OPP1',
6: 'OPP_TEST_CLK_SEL_DISPCLK_OPP2',
7: 'OPP_TEST_CLK_SEL_DISPCLK_OPP3',
8: 'OPP_TEST_CLK_SEL_DISPCLK_OPP4',
9: 'OPP_TEST_CLK_SEL_DISPCLK_OPP5',
}
OPP_TEST_CLK_SEL_DISPCLK_P = 0
OPP_TEST_CLK_SEL_DISPCLK_R = 1
OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 2
OPP_TEST_CLK_SEL_RESERVED0 = 3
OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 4
OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 5
OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 6
OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 7
OPP_TEST_CLK_SEL_DISPCLK_OPP4 = 8
OPP_TEST_CLK_SEL_DISPCLK_OPP5 = 9
OPP_TEST_CLK_SEL_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_START_POINT_CNTL'
OTG_CONTROL_OTG_START_POINT_CNTL__enumvalues = {
0: 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL',
1: 'OTG_CONTROL_OTG_START_POINT_CNTL_DP',
}
OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0
OTG_CONTROL_OTG_START_POINT_CNTL_DP = 1
OTG_CONTROL_OTG_START_POINT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL'
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL__enumvalues = {
0: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL',
1: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP',
}
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 1
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL'
OTG_CONTROL_OTG_DISABLE_POINT_CNTL__enumvalues = {
0: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE',
1: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT',
2: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED',
3: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST',
}
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED = 2
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 3
OTG_CONTROL_OTG_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY'
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY__enumvalues = {
0: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE',
1: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE',
}
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 1
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE'
OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE__enumvalues = {
0: 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE',
1: 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE',
}
OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE = 0
OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE = 1
OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_SOF_PULL_EN'
OTG_CONTROL_OTG_SOF_PULL_EN__enumvalues = {
0: 'OTG_CONTROL_OTG_SOF_PULL_EN_FALSE',
1: 'OTG_CONTROL_OTG_SOF_PULL_EN_TRUE',
}
OTG_CONTROL_OTG_SOF_PULL_EN_FALSE = 0
OTG_CONTROL_OTG_SOF_PULL_EN_TRUE = 1
OTG_CONTROL_OTG_SOF_PULL_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL'
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE',
1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE',
}
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 1
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL'
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE',
1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE',
}
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 1
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN'
OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE',
1: 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE',
}
OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0
OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE = 1
OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC'
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE',
1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE',
}
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT'
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE',
1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE',
}
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 1
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD'
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0',
1: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1',
}
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 1
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK'
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__enumvalues = {
0: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE',
1: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE',
}
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 1
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR'
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR__enumvalues = {
0: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE',
1: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE',
}
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 1
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN'
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN__enumvalues = {
0: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE',
1: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE',
}
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 1
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT'
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN',
2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN',
3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN',
4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN',
5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN',
6: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN',
7: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN',
8: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN',
9: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN',
10: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN',
11: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1',
12: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2',
13: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN',
14: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL',
15: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK',
16: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP',
17: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING',
18: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF',
19: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC',
20: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC',
21: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL',
22: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
23: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1',
24: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING',
}
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 1
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 2
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 3
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 4
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 5
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 6
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 7
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 8
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 9
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 10
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 11
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 12
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 13
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL = 14
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 15
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 16
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 17
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 18
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 19
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 20
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 23
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 24
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT'
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE',
2: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA',
3: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB',
4: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA',
5: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1',
6: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC',
7: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD',
}
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 1
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 2
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 3
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 4
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 5
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 6
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 7
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT'
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN',
2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN',
3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN',
4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN',
5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN',
6: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN',
7: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN',
8: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN',
9: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN',
10: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN',
11: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1',
12: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2',
13: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN',
14: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL',
15: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK',
16: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP',
17: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING',
18: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF',
19: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC',
20: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC',
21: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL',
22: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
23: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1',
24: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING',
}
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 1
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 2
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 3
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 4
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 5
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 6
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 7
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 8
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 9
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 10
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 11
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 12
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 13
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL = 14
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 15
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 16
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 17
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 18
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 19
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 20
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 23
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 24
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT'
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1',
2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2',
3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3',
4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4',
5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5',
}
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 1
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 2
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 3
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4 = 4
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5 = 5
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT'
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE',
2: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA',
3: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB',
4: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA',
5: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1',
6: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC',
7: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD',
}
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 1
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 2
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 3
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 4
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 5
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 6
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 7
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT'
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1',
2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2',
3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3',
4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4',
5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5',
}
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 1
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 2
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 3
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4 = 4
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5 = 5
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN'
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE',
}
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 1
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR'
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE',
}
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 1
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN'
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE',
}
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 1
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR'
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE',
}
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 1
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE'
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE__enumvalues = {
0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE',
1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT',
2: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT',
3: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED',
}
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 1
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 3
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK'
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK__enumvalues = {
0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE',
1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE',
}
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 1
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL'
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = {
0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE',
1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE',
}
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR'
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR__enumvalues = {
0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE',
1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE',
}
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 1
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT'
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT__enumvalues = {
0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0',
1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1',
2: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA',
3: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB',
4: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC',
5: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD',
6: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE',
7: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF',
8: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1',
9: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2',
10: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA',
11: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK',
12: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA',
13: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK',
14: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
15: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE',
16: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK',
17: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC',
18: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA',
19: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB',
}
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 1
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 2
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 3
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 4
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 5
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 6
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 7
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 8
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 9
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 10
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 11
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 12
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 13
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 14
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE = 15
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 16
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 17
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 18
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 19
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY'
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY__enumvalues = {
0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE',
1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE',
}
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 1
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY'
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY__enumvalues = {
0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE',
1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE',
}
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 1
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE'
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE__enumvalues = {
0: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO',
1: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT',
2: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT',
3: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED',
}
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 1
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 2
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 3
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_MASTER_EN'
OTG_CONTROL_OTG_MASTER_EN__enumvalues = {
0: 'OTG_CONTROL_OTG_MASTER_EN_FALSE',
1: 'OTG_CONTROL_OTG_MASTER_EN_TRUE',
}
OTG_CONTROL_OTG_MASTER_EN_FALSE = 0
OTG_CONTROL_OTG_MASTER_EN_TRUE = 1
OTG_CONTROL_OTG_MASTER_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN'
OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN__enumvalues = {
0: 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE',
1: 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE',
}
OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE = 0
OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE = 1
OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE'
OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE__enumvalues = {
0: 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE',
1: 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE',
}
OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE = 0
OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE = 1
OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE'
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE__enumvalues = {
0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE',
1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE',
}
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 1
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD'
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD__enumvalues = {
0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT',
1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM',
2: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP',
3: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2',
}
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 1
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 2
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY'
OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY__enumvalues = {
0: 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE',
1: 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE',
}
OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0
OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 1
OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT'
OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT__enumvalues = {
0: 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE',
1: 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE',
}
OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE = 0
OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE = 1
OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN'
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN__enumvalues = {
0: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE',
1: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE',
}
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 1
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE'
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = {
0: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE',
1: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE',
}
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR'
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = {
0: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE',
1: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE',
}
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE'
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE__enumvalues = {
0: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE',
1: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA',
2: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB',
3: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED',
}
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 3
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY'
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = {
0: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE',
1: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE',
}
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY'
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY__enumvalues = {
0: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE',
1: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE',
}
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 1
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EN'
OTG_STEREO_CONTROL_OTG_STEREO_EN__enumvalues = {
0: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE',
1: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE',
}
OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0
OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 1
OTG_STEREO_CONTROL_OTG_STEREO_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR'
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR__enumvalues = {
0: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE',
1: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE',
}
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 1
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL'
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = {
0: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE',
1: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA',
2: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB',
3: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED',
}
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY'
OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY__enumvalues = {
0: 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE',
1: 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE',
}
OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE = 0
OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE = 1
OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY'
OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY__enumvalues = {
0: 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE',
1: 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE',
}
OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE = 0
OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE = 1
OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN'
OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN__enumvalues = {
0: 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE',
1: 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE',
}
OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE = 0
OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE = 1
OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN'
OTG_START_LINE_CONTROL_OTG_PREFETCH_EN__enumvalues = {
0: 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE',
1: 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE',
}
OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE = 0
OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE = 1
OTG_START_LINE_CONTROL_OTG_PREFETCH_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK'
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK__enumvalues = {
0: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE',
1: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE',
}
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 1
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY'
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY__enumvalues = {
0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE',
1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE',
}
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 1
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN'
OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN__enumvalues = {
0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE',
1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE',
}
OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0
OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 1
OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE'
OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE__enumvalues = {
0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0',
1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1',
2: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2',
3: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3',
}
OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0
OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 1
OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2 = 2
OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3 = 3
OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE'
OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE__enumvalues = {
0: 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE',
1: 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE',
}
OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0
OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE = 1
OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK'
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = {
0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE',
1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE',
}
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME'
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME__enumvalues = {
0: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME',
1: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME',
2: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME',
3: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME',
}
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 1
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 2
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 3
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME = ctypes.c_uint32 # enum
# values for enumeration 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK'
MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK__enumvalues = {
0: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE',
1: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE',
}
MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0
MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 1
MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK = ctypes.c_uint32 # enum
# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE'
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = {
0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH',
1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP',
2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM',
3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED',
}
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 1
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 2
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE'
OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE__enumvalues = {
0: 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE',
1: 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG',
2: 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL',
}
OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE = 0
OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG = 1
OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL = 2
OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR'
OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR__enumvalues = {
0: 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE',
1: 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE',
}
OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE = 0
OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE = 1
OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR'
OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR__enumvalues = {
0: 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE',
1: 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE',
}
OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0
OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 1
OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR'
OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR__enumvalues = {
0: 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE',
1: 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE',
}
OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE = 0
OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE = 1
OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY'
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE',
1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE',
}
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE'
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE',
}
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR'
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE',
1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE',
}
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE'
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE',
}
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR'
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE',
1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE',
}
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE'
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE',
}
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE'
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE',
}
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR'
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE',
1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE',
}
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE'
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE',
}
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE'
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE',
}
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_EN'
OTG_CRC_CNTL_OTG_CRC_EN__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE',
1: 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE',
}
OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0
OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 1
OTG_CRC_CNTL_OTG_CRC_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_EN'
OTG_CRC_CNTL_OTG_CRC_CONT_EN__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE',
1: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE',
}
OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0
OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 1
OTG_CRC_CNTL_OTG_CRC_CONT_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE'
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT',
1: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT',
2: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES',
3: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS',
}
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 1
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 2
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 3
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE'
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP',
1: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM',
2: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM',
3: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD',
}
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 1
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 3
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS'
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE',
1: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE',
}
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT'
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB',
1: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B',
2: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB',
3: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B',
4: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB',
5: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B',
6: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB',
7: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B',
}
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 1
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 2
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 3
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 4
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 5
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 6
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 7
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT'
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB',
1: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B',
2: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB',
3: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B',
4: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB',
5: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B',
6: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB',
7: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B',
}
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 1
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 2
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 3
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 4
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 5
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 6
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 7
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE'
OTG_CRC_CNTL2_OTG_CRC_DSC_MODE__enumvalues = {
0: 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE',
1: 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE',
}
OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE = 0
OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE = 1
OTG_CRC_CNTL2_OTG_CRC_DSC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE'
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE__enumvalues = {
0: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE',
1: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE',
}
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE = 0
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE = 1
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE'
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE__enumvalues = {
0: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE',
1: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1',
2: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2',
3: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3',
}
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE = 0
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1 = 1
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2 = 2
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3 = 3
OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT'
OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT__enumvalues = {
0: 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0',
1: 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1',
2: 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2',
3: 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3',
}
OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0 = 0
OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1 = 1
OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2 = 2
OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3 = 3
OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE'
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE',
1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT',
2: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS',
3: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED',
}
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE = 0
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT = 1
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 2
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED = 3
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE'
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE',
1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE',
}
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 1
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE'
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE',
1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE',
}
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 1
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW'
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel',
1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel',
2: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel',
3: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel',
}
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 1
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 2
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 3
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE'
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE',
1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE',
}
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 1
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE'
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE',
1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE',
}
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 1
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY'
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE',
1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE',
}
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 1
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY'
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE',
1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE',
}
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 1
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE'
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE',
1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE',
}
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 1
OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE'
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE',
1: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE',
}
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 1
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR'
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE',
1: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE',
}
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 1
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE'
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE',
1: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE',
}
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 1
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT'
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME',
1: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME',
2: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME',
3: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME',
4: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME',
5: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME',
6: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME',
7: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME',
}
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 1
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 2
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 3
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 4
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 5
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 6
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 7
OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE'
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE',
1: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE',
}
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 1
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR'
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE',
1: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE',
}
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE = 0
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE = 1
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE'
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE',
1: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE',
}
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE = 1
OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE'
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE',
1: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE',
}
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 1
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR'
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE',
1: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE',
}
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 1
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE'
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__enumvalues = {
0: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE',
1: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE',
}
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 1
OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE'
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE',
}
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 1
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR'
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE',
}
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 1
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE'
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE',
}
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 1
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE'
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE',
}
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 1
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE'
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON',
}
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN'
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN__enumvalues = {
0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE',
1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE',
}
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 1
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB'
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB__enumvalues = {
0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE',
1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE',
}
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 1
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum
# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE'
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = {
0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH',
1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE',
2: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE',
3: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED',
}
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR'
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = {
0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE',
1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE',
}
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_SYNC_A_POL'
OTG_V_SYNC_A_POL__enumvalues = {
0: 'OTG_V_SYNC_A_POL_HIGH',
1: 'OTG_V_SYNC_A_POL_LOW',
}
OTG_V_SYNC_A_POL_HIGH = 0
OTG_V_SYNC_A_POL_LOW = 1
OTG_V_SYNC_A_POL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_H_SYNC_A_POL'
OTG_H_SYNC_A_POL__enumvalues = {
0: 'OTG_H_SYNC_A_POL_HIGH',
1: 'OTG_H_SYNC_A_POL_LOW',
}
OTG_H_SYNC_A_POL_HIGH = 0
OTG_H_SYNC_A_POL_LOW = 1
OTG_H_SYNC_A_POL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_HORZ_REPETITION_COUNT'
OTG_HORZ_REPETITION_COUNT__enumvalues = {
0: 'OTG_HORZ_REPETITION_COUNT_0',
1: 'OTG_HORZ_REPETITION_COUNT_1',
2: 'OTG_HORZ_REPETITION_COUNT_2',
3: 'OTG_HORZ_REPETITION_COUNT_3',
4: 'OTG_HORZ_REPETITION_COUNT_4',
5: 'OTG_HORZ_REPETITION_COUNT_5',
6: 'OTG_HORZ_REPETITION_COUNT_6',
7: 'OTG_HORZ_REPETITION_COUNT_7',
8: 'OTG_HORZ_REPETITION_COUNT_8',
9: 'OTG_HORZ_REPETITION_COUNT_9',
10: 'OTG_HORZ_REPETITION_COUNT_10',
11: 'OTG_HORZ_REPETITION_COUNT_11',
12: 'OTG_HORZ_REPETITION_COUNT_12',
13: 'OTG_HORZ_REPETITION_COUNT_13',
14: 'OTG_HORZ_REPETITION_COUNT_14',
15: 'OTG_HORZ_REPETITION_COUNT_15',
}
OTG_HORZ_REPETITION_COUNT_0 = 0
OTG_HORZ_REPETITION_COUNT_1 = 1
OTG_HORZ_REPETITION_COUNT_2 = 2
OTG_HORZ_REPETITION_COUNT_3 = 3
OTG_HORZ_REPETITION_COUNT_4 = 4
OTG_HORZ_REPETITION_COUNT_5 = 5
OTG_HORZ_REPETITION_COUNT_6 = 6
OTG_HORZ_REPETITION_COUNT_7 = 7
OTG_HORZ_REPETITION_COUNT_8 = 8
OTG_HORZ_REPETITION_COUNT_9 = 9
OTG_HORZ_REPETITION_COUNT_10 = 10
OTG_HORZ_REPETITION_COUNT_11 = 11
OTG_HORZ_REPETITION_COUNT_12 = 12
OTG_HORZ_REPETITION_COUNT_13 = 13
OTG_HORZ_REPETITION_COUNT_14 = 14
OTG_HORZ_REPETITION_COUNT_15 = 15
OTG_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum
# values for enumeration 'MASTER_UPDATE_LOCK_SEL'
MASTER_UPDATE_LOCK_SEL__enumvalues = {
0: 'MASTER_UPDATE_LOCK_SEL_0',
1: 'MASTER_UPDATE_LOCK_SEL_1',
2: 'MASTER_UPDATE_LOCK_SEL_2',
3: 'MASTER_UPDATE_LOCK_SEL_3',
4: 'MASTER_UPDATE_LOCK_SEL_4',
5: 'MASTER_UPDATE_LOCK_SEL_5',
}
MASTER_UPDATE_LOCK_SEL_0 = 0
MASTER_UPDATE_LOCK_SEL_1 = 1
MASTER_UPDATE_LOCK_SEL_2 = 2
MASTER_UPDATE_LOCK_SEL_3 = 3
MASTER_UPDATE_LOCK_SEL_4 = 4
MASTER_UPDATE_LOCK_SEL_5 = 5
MASTER_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DRR_UPDATE_LOCK_SEL'
DRR_UPDATE_LOCK_SEL__enumvalues = {
0: 'DRR_UPDATE_LOCK_SEL_0',
1: 'DRR_UPDATE_LOCK_SEL_1',
2: 'DRR_UPDATE_LOCK_SEL_2',
3: 'DRR_UPDATE_LOCK_SEL_3',
4: 'DRR_UPDATE_LOCK_SEL_4',
5: 'DRR_UPDATE_LOCK_SEL_5',
}
DRR_UPDATE_LOCK_SEL_0 = 0
DRR_UPDATE_LOCK_SEL_1 = 1
DRR_UPDATE_LOCK_SEL_2 = 2
DRR_UPDATE_LOCK_SEL_3 = 3
DRR_UPDATE_LOCK_SEL_4 = 4
DRR_UPDATE_LOCK_SEL_5 = 5
DRR_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL'
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL__enumvalues = {
0: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0',
1: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1',
2: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2',
3: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3',
4: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4',
5: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5',
}
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 1
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 2
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 3
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4 = 4
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5 = 5
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD'
OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD__enumvalues = {
0: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH',
1: 'MASTER_UPDATE_LOCK_DB_FIELD_TOP',
2: 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED',
}
MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0
MASTER_UPDATE_LOCK_DB_FIELD_TOP = 1
MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 2
OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL'
OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL__enumvalues = {
0: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH',
1: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT',
2: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT',
3: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED',
}
MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0
MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 1
MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 2
MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 3
OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_H_TIMING_DIV_BY2'
OTG_H_TIMING_DIV_BY2__enumvalues = {
0: 'OTG_H_TIMING_DIV_BY2_FALSE',
1: 'OTG_H_TIMING_DIV_BY2_TRUE',
}
OTG_H_TIMING_DIV_BY2_FALSE = 0
OTG_H_TIMING_DIV_BY2_TRUE = 1
OTG_H_TIMING_DIV_BY2 = ctypes.c_uint32 # enum
# values for enumeration 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE'
OTG_H_TIMING_DIV_BY2_UPDATE_MODE__enumvalues = {
0: 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0',
1: 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1',
}
OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0 = 0
OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1 = 1
OTG_H_TIMING_DIV_BY2_UPDATE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL'
OTG_TRIGA_RISING_EDGE_DETECT_CNTL__enumvalues = {
0: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0',
1: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1',
2: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2',
3: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3',
}
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 1
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 2
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 3
OTG_TRIGA_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL'
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__enumvalues = {
0: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0',
1: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1',
2: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2',
3: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3',
}
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 1
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 2
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 3
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_FREQUENCY_SELECT'
OTG_TRIGA_FREQUENCY_SELECT__enumvalues = {
0: 'OTG_TRIGA_FREQUENCY_SELECT_0',
1: 'OTG_TRIGA_FREQUENCY_SELECT_1',
2: 'OTG_TRIGA_FREQUENCY_SELECT_2',
3: 'OTG_TRIGA_FREQUENCY_SELECT_3',
}
OTG_TRIGA_FREQUENCY_SELECT_0 = 0
OTG_TRIGA_FREQUENCY_SELECT_1 = 1
OTG_TRIGA_FREQUENCY_SELECT_2 = 2
OTG_TRIGA_FREQUENCY_SELECT_3 = 3
OTG_TRIGA_FREQUENCY_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL'
OTG_TRIGB_RISING_EDGE_DETECT_CNTL__enumvalues = {
0: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0',
1: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1',
2: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2',
3: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3',
}
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 1
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 2
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 3
OTG_TRIGB_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL'
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__enumvalues = {
0: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0',
1: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1',
2: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2',
3: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3',
}
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 1
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 2
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 3
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_FREQUENCY_SELECT'
OTG_TRIGB_FREQUENCY_SELECT__enumvalues = {
0: 'OTG_TRIGB_FREQUENCY_SELECT_0',
1: 'OTG_TRIGB_FREQUENCY_SELECT_1',
2: 'OTG_TRIGB_FREQUENCY_SELECT_2',
3: 'OTG_TRIGB_FREQUENCY_SELECT_3',
}
OTG_TRIGB_FREQUENCY_SELECT_0 = 0
OTG_TRIGB_FREQUENCY_SELECT_1 = 1
OTG_TRIGB_FREQUENCY_SELECT_2 = 2
OTG_TRIGB_FREQUENCY_SELECT_3 = 3
OTG_TRIGB_FREQUENCY_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_PIPE_ABORT'
OTG_PIPE_ABORT__enumvalues = {
0: 'OTG_PIPE_ABORT_0',
1: 'OTG_PIPE_ABORT_1',
}
OTG_PIPE_ABORT_0 = 0
OTG_PIPE_ABORT_1 = 1
OTG_PIPE_ABORT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_MASTER_UPDATE_LOCK_GSL_EN'
OTG_MASTER_UPDATE_LOCK_GSL_EN__enumvalues = {
0: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE',
1: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE',
}
OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0
OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 1
OTG_MASTER_UPDATE_LOCK_GSL_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_PTI_CONTROL_OTG_PIT_EN'
OTG_PTI_CONTROL_OTG_PIT_EN__enumvalues = {
0: 'OTG_PTI_CONTROL_OTG_PIT_EN_FALSE',
1: 'OTG_PTI_CONTROL_OTG_PIT_EN_TRUE',
}
OTG_PTI_CONTROL_OTG_PIT_EN_FALSE = 0
OTG_PTI_CONTROL_OTG_PIT_EN_TRUE = 1
OTG_PTI_CONTROL_OTG_PIT_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GSL_MASTER_MODE'
OTG_GSL_MASTER_MODE__enumvalues = {
0: 'OTG_GSL_MASTER_MODE_0',
1: 'OTG_GSL_MASTER_MODE_1',
2: 'OTG_GSL_MASTER_MODE_2',
3: 'OTG_GSL_MASTER_MODE_3',
}
OTG_GSL_MASTER_MODE_0 = 0
OTG_GSL_MASTER_MODE_1 = 1
OTG_GSL_MASTER_MODE_2 = 2
OTG_GSL_MASTER_MODE_3 = 3
OTG_GSL_MASTER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DC_DMCUB_TIMER_WINDOW'
DC_DMCUB_TIMER_WINDOW__enumvalues = {
0: 'BITS_31_0',
1: 'BITS_32_1',
2: 'BITS_33_2',
3: 'BITS_34_3',
4: 'BITS_35_4',
5: 'BITS_36_5',
6: 'BITS_37_6',
7: 'BITS_38_7',
}
BITS_31_0 = 0
BITS_32_1 = 1
BITS_33_2 = 2
BITS_34_3 = 3
BITS_35_4 = 4
BITS_36_5 = 5
BITS_37_6 = 6
BITS_38_7 = 7
DC_DMCUB_TIMER_WINDOW = ctypes.c_uint32 # enum
# values for enumeration 'DC_DMCUB_INT_TYPE'
DC_DMCUB_INT_TYPE__enumvalues = {
0: 'INT_LEVEL',
1: 'INT_PULSE',
}
INT_LEVEL = 0
INT_PULSE = 1
DC_DMCUB_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'INVALID_REG_ACCESS_TYPE'
INVALID_REG_ACCESS_TYPE__enumvalues = {
0: 'REG_UNALLOCATED_ADDR_WRITE',
1: 'REG_UNALLOCATED_ADDR_READ',
2: 'REG_VIRTUAL_WRITE',
3: 'REG_VIRTUAL_READ',
}
REG_UNALLOCATED_ADDR_WRITE = 0
REG_UNALLOCATED_ADDR_READ = 1
REG_VIRTUAL_WRITE = 2
REG_VIRTUAL_READ = 3
INVALID_REG_ACCESS_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DMU_DC_GPU_TIMER_START_POSITION'
DMU_DC_GPU_TIMER_START_POSITION__enumvalues = {
0: 'DMU_GPU_TIMER_START_0_END_27',
1: 'DMU_GPU_TIMER_START_1_END_28',
2: 'DMU_GPU_TIMER_START_2_END_29',
3: 'DMU_GPU_TIMER_START_3_END_30',
4: 'DMU_GPU_TIMER_START_4_END_31',
5: 'DMU_GPU_TIMER_START_6_END_33',
6: 'DMU_GPU_TIMER_START_8_END_35',
7: 'DMU_GPU_TIMER_START_10_END_37',
}
DMU_GPU_TIMER_START_0_END_27 = 0
DMU_GPU_TIMER_START_1_END_28 = 1
DMU_GPU_TIMER_START_2_END_29 = 2
DMU_GPU_TIMER_START_3_END_30 = 3
DMU_GPU_TIMER_START_4_END_31 = 4
DMU_GPU_TIMER_START_6_END_33 = 5
DMU_GPU_TIMER_START_8_END_35 = 6
DMU_GPU_TIMER_START_10_END_37 = 7
DMU_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum
# values for enumeration 'DMU_DC_GPU_TIMER_READ_SELECT'
DMU_DC_GPU_TIMER_READ_SELECT__enumvalues = {
0: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0',
1: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1',
2: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2',
3: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3',
4: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4',
5: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5',
6: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6',
7: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7',
8: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8',
9: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9',
10: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10',
11: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11',
12: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12',
13: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13',
14: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14',
15: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15',
16: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16',
17: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17',
18: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18',
19: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19',
20: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20',
21: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21',
22: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22',
23: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23',
24: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24',
25: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25',
26: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26',
27: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27',
28: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28',
29: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29',
30: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30',
31: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31',
32: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32',
33: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33',
34: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34',
35: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35',
36: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36',
37: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37',
38: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38',
39: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39',
40: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40',
41: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41',
42: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42',
43: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43',
44: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44',
45: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45',
46: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46',
47: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47',
48: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48',
49: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49',
50: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50',
51: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51',
52: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52',
53: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53',
54: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54',
55: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55',
56: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56',
57: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57',
58: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58',
59: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59',
60: 'RESERVED_60',
61: 'RESERVED_61',
62: 'RESERVED_62',
63: 'RESERVED_63',
64: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64',
65: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65',
66: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66',
67: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67',
68: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68',
69: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69',
70: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70',
71: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71',
72: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72',
73: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73',
74: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74',
75: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75',
76: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76',
77: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77',
78: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78',
79: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79',
80: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80',
81: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81',
82: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82',
83: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83',
84: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84',
85: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85',
86: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86',
87: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87',
88: 'RESERVED_88',
89: 'RESERVED_89',
90: 'RESERVED_90',
91: 'RESERVED_91',
}
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 1
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 2
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 3
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 4
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 5
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 6
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 7
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8 = 8
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9 = 9
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10 = 10
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11 = 11
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 12
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 13
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 14
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 15
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 16
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 17
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 18
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 19
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20 = 20
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21 = 21
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22 = 22
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23 = 23
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 24
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 25
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 26
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 27
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 28
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 29
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 30
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 31
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32 = 32
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33 = 33
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34 = 34
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35 = 35
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 36
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 37
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 38
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 39
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 40
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 41
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 42
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 43
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44 = 44
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45 = 45
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46 = 46
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47 = 47
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 48
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 49
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 50
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 51
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 52
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 53
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 54
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 55
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56 = 56
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57 = 57
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58 = 58
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59 = 59
RESERVED_60 = 60
RESERVED_61 = 61
RESERVED_62 = 62
RESERVED_63 = 63
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 64
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 65
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 66
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 67
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 68
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 69
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 70
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 71
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72 = 72
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73 = 73
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74 = 74
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75 = 75
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 76
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 77
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 78
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 79
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 80
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 81
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 82
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 83
DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84 = 84
DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85 = 85
DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86 = 86
DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87 = 87
RESERVED_88 = 88
RESERVED_89 = 89
RESERVED_90 = 90
RESERVED_91 = 91
DMU_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'IHC_INTERRUPT_LINE_STATUS'
IHC_INTERRUPT_LINE_STATUS__enumvalues = {
0: 'INTERRUPT_LINE_NOT_ASSERTED',
1: 'INTERRUPT_LINE_ASSERTED',
}
INTERRUPT_LINE_NOT_ASSERTED = 0
INTERRUPT_LINE_ASSERTED = 1
IHC_INTERRUPT_LINE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'DMU_CLOCK_GATING_DISABLE'
DMU_CLOCK_GATING_DISABLE__enumvalues = {
0: 'DMU_ENABLE_CLOCK_GATING',
1: 'DMU_DISABLE_CLOCK_GATING',
}
DMU_ENABLE_CLOCK_GATING = 0
DMU_DISABLE_CLOCK_GATING = 1
DMU_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'DMU_CLOCK_ON'
DMU_CLOCK_ON__enumvalues = {
0: 'DMU_CLOCK_STATUS_ON',
1: 'DMU_CLOCK_STATUS_OFF',
}
DMU_CLOCK_STATUS_ON = 0
DMU_CLOCK_STATUS_OFF = 1
DMU_CLOCK_ON = ctypes.c_uint32 # enum
# values for enumeration 'DC_SMU_INTERRUPT_ENABLE'
DC_SMU_INTERRUPT_ENABLE__enumvalues = {
0: 'DISABLE_THE_INTERRUPT',
1: 'ENABLE_THE_INTERRUPT',
}
DISABLE_THE_INTERRUPT = 0
ENABLE_THE_INTERRUPT = 1
DC_SMU_INTERRUPT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'STATIC_SCREEN_SMU_INTR'
STATIC_SCREEN_SMU_INTR__enumvalues = {
0: 'STATIC_SCREEN_SMU_INTR_NOOP',
1: 'SET_STATIC_SCREEN_SMU_INTR',
}
STATIC_SCREEN_SMU_INTR_NOOP = 0
SET_STATIC_SCREEN_SMU_INTR = 1
STATIC_SCREEN_SMU_INTR = ctypes.c_uint32 # enum
# values for enumeration 'ENABLE'
ENABLE__enumvalues = {
0: 'DISABLE_THE_FEATURE',
1: 'ENABLE_THE_FEATURE',
}
DISABLE_THE_FEATURE = 0
ENABLE_THE_FEATURE = 1
ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'DS_HW_CAL_ENABLE'
DS_HW_CAL_ENABLE__enumvalues = {
0: 'DS_HW_CAL_DIS',
1: 'DS_HW_CAL_EN',
}
DS_HW_CAL_DIS = 0
DS_HW_CAL_EN = 1
DS_HW_CAL_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'ENABLE_CLOCK'
ENABLE_CLOCK__enumvalues = {
0: 'DISABLE_THE_CLOCK',
1: 'ENABLE_THE_CLOCK',
}
DISABLE_THE_CLOCK = 0
ENABLE_THE_CLOCK = 1
ENABLE_CLOCK = ctypes.c_uint32 # enum
# values for enumeration 'CLEAR_SMU_INTR'
CLEAR_SMU_INTR__enumvalues = {
0: 'SMU_INTR_STATUS_NOOP',
1: 'SMU_INTR_STATUS_CLEAR',
}
SMU_INTR_STATUS_NOOP = 0
SMU_INTR_STATUS_CLEAR = 1
CLEAR_SMU_INTR = ctypes.c_uint32 # enum
# values for enumeration 'JITTER_REMOVE_DISABLE'
JITTER_REMOVE_DISABLE__enumvalues = {
0: 'ENABLE_JITTER_REMOVAL',
1: 'DISABLE_JITTER_REMOVAL',
}
ENABLE_JITTER_REMOVAL = 0
DISABLE_JITTER_REMOVAL = 1
JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'DS_REF_SRC'
DS_REF_SRC__enumvalues = {
0: 'DS_REF_IS_XTALIN',
1: 'DS_REF_IS_EXT_GENLOCK',
2: 'DS_REF_IS_PCIE',
}
DS_REF_IS_XTALIN = 0
DS_REF_IS_EXT_GENLOCK = 1
DS_REF_IS_PCIE = 2
DS_REF_SRC = ctypes.c_uint32 # enum
# values for enumeration 'DISABLE_CLOCK_GATING'
DISABLE_CLOCK_GATING__enumvalues = {
0: 'CLOCK_GATING_ENABLED',
1: 'CLOCK_GATING_DISABLED',
}
CLOCK_GATING_ENABLED = 0
CLOCK_GATING_DISABLED = 1
DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum
# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO'
DISABLE_CLOCK_GATING_IN_DCO__enumvalues = {
0: 'CLOCK_GATING_ENABLED_IN_DCO',
1: 'CLOCK_GATING_DISABLED_IN_DCO',
}
CLOCK_GATING_ENABLED_IN_DCO = 0
CLOCK_GATING_DISABLED_IN_DCO = 1
DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_DEEP_COLOR_CNTL'
DCCG_DEEP_COLOR_CNTL__enumvalues = {
0: 'DCCG_DEEP_COLOR_DTO_DISABLE',
1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO',
2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO',
3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO',
}
DCCG_DEEP_COLOR_DTO_DISABLE = 0
DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1
DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2
DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3
DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'REFCLK_CLOCK_EN'
REFCLK_CLOCK_EN__enumvalues = {
0: 'REFCLK_CLOCK_EN_XTALIN_CLK',
1: 'REFCLK_CLOCK_EN_ALLOW_SRC_SEL',
}
REFCLK_CLOCK_EN_XTALIN_CLK = 0
REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 1
REFCLK_CLOCK_EN = ctypes.c_uint32 # enum
# values for enumeration 'REFCLK_SRC_SEL'
REFCLK_SRC_SEL__enumvalues = {
0: 'REFCLK_SRC_SEL_PCIE_REFCLK',
1: 'REFCLK_SRC_SEL_CPL_REFCLK',
}
REFCLK_SRC_SEL_PCIE_REFCLK = 0
REFCLK_SRC_SEL_CPL_REFCLK = 1
REFCLK_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DPREFCLK_SRC_SEL'
DPREFCLK_SRC_SEL__enumvalues = {
0: 'DPREFCLK_SRC_SEL_CK',
1: 'DPREFCLK_SRC_SEL_P0PLL',
2: 'DPREFCLK_SRC_SEL_P1PLL',
3: 'DPREFCLK_SRC_SEL_P2PLL',
}
DPREFCLK_SRC_SEL_CK = 0
DPREFCLK_SRC_SEL_P0PLL = 1
DPREFCLK_SRC_SEL_P1PLL = 2
DPREFCLK_SRC_SEL_P2PLL = 3
DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'XTAL_REF_SEL'
XTAL_REF_SEL__enumvalues = {
0: 'XTAL_REF_SEL_1X',
1: 'XTAL_REF_SEL_2X',
}
XTAL_REF_SEL_1X = 0
XTAL_REF_SEL_2X = 1
XTAL_REF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL'
XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = {
0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN',
1: 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK',
}
XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0
XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 1
XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL'
MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = {
0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN',
1: 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK',
}
MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0
MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1
MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'ALLOW_SR_ON_TRANS_REQ'
ALLOW_SR_ON_TRANS_REQ__enumvalues = {
0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE',
1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE',
}
ALLOW_SR_ON_TRANS_REQ_ENABLE = 0
ALLOW_SR_ON_TRANS_REQ_DISABLE = 1
ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum
# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL'
MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = {
0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN',
1: 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK',
}
MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0
MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1
MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_PIXEL_RATE_SOURCE'
PIPE_PIXEL_RATE_SOURCE__enumvalues = {
0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL',
1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL',
2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL',
}
PIPE_PIXEL_RATE_SOURCE_P0PLL = 0
PIPE_PIXEL_RATE_SOURCE_P1PLL = 1
PIPE_PIXEL_RATE_SOURCE_P2PLL = 2
PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'TEST_CLK_DIV_SEL'
TEST_CLK_DIV_SEL__enumvalues = {
0: 'NO_DIV',
1: 'DIV_2',
2: 'DIV_4',
3: 'DIV_8',
}
NO_DIV = 0
DIV_2 = 1
DIV_4 = 2
DIV_8 = 3
TEST_CLK_DIV_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE'
PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = {
0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA',
1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB',
2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC',
3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD',
4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE',
5: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF',
6: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED',
}
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 4
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 5
PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 6
PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE'
PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = {
0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL',
1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL',
}
PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0
PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1
PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'DP_DTO_DS_DISABLE'
DP_DTO_DS_DISABLE__enumvalues = {
0: 'DP_DTO_DESPREAD_DISABLE',
1: 'DP_DTO_DESPREAD_ENABLE',
}
DP_DTO_DESPREAD_DISABLE = 0
DP_DTO_DESPREAD_ENABLE = 1
DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_ADD_PIXEL'
OTG_ADD_PIXEL__enumvalues = {
0: 'OTG_ADD_PIXEL_NOOP',
1: 'OTG_ADD_PIXEL_FORCE',
}
OTG_ADD_PIXEL_NOOP = 0
OTG_ADD_PIXEL_FORCE = 1
OTG_ADD_PIXEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DROP_PIXEL'
OTG_DROP_PIXEL__enumvalues = {
0: 'OTG_DROP_PIXEL_NOOP',
1: 'OTG_DROP_PIXEL_FORCE',
}
OTG_DROP_PIXEL_NOOP = 0
OTG_DROP_PIXEL_FORCE = 1
OTG_DROP_PIXEL = ctypes.c_uint32 # enum
# values for enumeration 'SYMCLK_FE_FORCE_EN'
SYMCLK_FE_FORCE_EN__enumvalues = {
0: 'SYMCLK_FE_FORCE_EN_DISABLE',
1: 'SYMCLK_FE_FORCE_EN_ENABLE',
}
SYMCLK_FE_FORCE_EN_DISABLE = 0
SYMCLK_FE_FORCE_EN_ENABLE = 1
SYMCLK_FE_FORCE_EN = ctypes.c_uint32 # enum
# values for enumeration 'SYMCLK_FE_FORCE_SRC'
SYMCLK_FE_FORCE_SRC__enumvalues = {
0: 'SYMCLK_FE_FORCE_SRC_UNIPHYA',
1: 'SYMCLK_FE_FORCE_SRC_UNIPHYB',
2: 'SYMCLK_FE_FORCE_SRC_UNIPHYC',
3: 'SYMCLK_FE_FORCE_SRC_UNIPHYD',
4: 'SYMCLK_FE_FORCE_SRC_UNIPHYE',
5: 'SYMCLK_FE_FORCE_SRC_UNIPHYF',
6: 'SYMCLK_FE_FORCE_SRC_RESERVED',
}
SYMCLK_FE_FORCE_SRC_UNIPHYA = 0
SYMCLK_FE_FORCE_SRC_UNIPHYB = 1
SYMCLK_FE_FORCE_SRC_UNIPHYC = 2
SYMCLK_FE_FORCE_SRC_UNIPHYD = 3
SYMCLK_FE_FORCE_SRC_UNIPHYE = 4
SYMCLK_FE_FORCE_SRC_UNIPHYF = 5
SYMCLK_FE_FORCE_SRC_RESERVED = 6
SYMCLK_FE_FORCE_SRC = ctypes.c_uint32 # enum
# values for enumeration 'DVOACLK_COARSE_SKEW_CNTL'
DVOACLK_COARSE_SKEW_CNTL__enumvalues = {
0: 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT',
1: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP',
2: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS',
3: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS',
4: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS',
5: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS',
6: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS',
7: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS',
8: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS',
9: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS',
10: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS',
11: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS',
12: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS',
13: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS',
14: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS',
15: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS',
16: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP',
17: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS',
18: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS',
19: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS',
20: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS',
21: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS',
22: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS',
23: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS',
24: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS',
25: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS',
26: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS',
27: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS',
28: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS',
29: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS',
30: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS',
}
DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0
DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 1
DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 2
DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 3
DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 4
DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 5
DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 6
DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 7
DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 8
DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 9
DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 10
DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 11
DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 12
DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 13
DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 14
DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 15
DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 16
DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 17
DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 18
DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 19
DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 20
DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 21
DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 22
DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 23
DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 24
DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 25
DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 26
DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 27
DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 28
DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 29
DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 30
DVOACLK_COARSE_SKEW_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'DVOACLK_FINE_SKEW_CNTL'
DVOACLK_FINE_SKEW_CNTL__enumvalues = {
0: 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT',
1: 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP',
2: 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS',
3: 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS',
4: 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP',
5: 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS',
6: 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS',
7: 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS',
}
DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0
DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 1
DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 2
DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 3
DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 4
DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 5
DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 6
DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 7
DVOACLK_FINE_SKEW_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'DVOACLKD_IN_PHASE'
DVOACLKD_IN_PHASE__enumvalues = {
0: 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO',
1: 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO',
}
DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0
DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 1
DVOACLKD_IN_PHASE = ctypes.c_uint32 # enum
# values for enumeration 'DVOACLKC_IN_PHASE'
DVOACLKC_IN_PHASE__enumvalues = {
0: 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO',
1: 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO',
}
DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0
DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 1
DVOACLKC_IN_PHASE = ctypes.c_uint32 # enum
# values for enumeration 'DVOACLKC_MVP_IN_PHASE'
DVOACLKC_MVP_IN_PHASE__enumvalues = {
0: 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO',
1: 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO',
}
DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0
DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 1
DVOACLKC_MVP_IN_PHASE = ctypes.c_uint32 # enum
# values for enumeration 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE'
DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__enumvalues = {
0: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE',
1: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE',
}
DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0
DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 1
DVOACLKC_MVP_SKEW_PHASE_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL'
DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = {
0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0',
1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1',
2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2',
3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3',
4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4',
5: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5',
6: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED',
}
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 1
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 2
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 3
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4 = 4
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5 = 5
DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 6
DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_AUDIO_DTO_SEL'
DCCG_AUDIO_DTO_SEL__enumvalues = {
0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0',
1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1',
2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO',
}
DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0
DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1
DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2
DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL'
DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = {
0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0',
1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1',
}
DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0
DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 1
DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO'
DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = {
0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP',
1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP',
}
DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0
DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1
DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum
# values for enumeration 'DISPCLK_FREQ_RAMP_DONE'
DISPCLK_FREQ_RAMP_DONE__enumvalues = {
0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS',
1: 'DISPCLK_FREQ_RAMP_COMPLETED',
}
DISPCLK_FREQ_RAMP_IN_PROGRESS = 0
DISPCLK_FREQ_RAMP_COMPLETED = 1
DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_FIFO_ERRDET_RESET'
DCCG_FIFO_ERRDET_RESET__enumvalues = {
0: 'DCCG_FIFO_ERRDET_RESET_NOOP',
1: 'DCCG_FIFO_ERRDET_RESET_FORCE',
}
DCCG_FIFO_ERRDET_RESET_NOOP = 0
DCCG_FIFO_ERRDET_RESET_FORCE = 1
DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_FIFO_ERRDET_STATE'
DCCG_FIFO_ERRDET_STATE__enumvalues = {
0: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION',
1: 'DCCG_FIFO_ERRDET_STATE_DETECTION',
}
DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0
DCCG_FIFO_ERRDET_STATE_DETECTION = 1
DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN'
DCCG_FIFO_ERRDET_OVR_EN__enumvalues = {
0: 'DCCG_FIFO_ERRDET_OVR_DISABLE',
1: 'DCCG_FIFO_ERRDET_OVR_ENABLE',
}
DCCG_FIFO_ERRDET_OVR_DISABLE = 0
DCCG_FIFO_ERRDET_OVR_ENABLE = 1
DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum
# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE'
DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = {
0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING',
1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING',
}
DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0
DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1
DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS'
DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = {
0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE',
1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE',
}
DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0
DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1
DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_PERF_RUN'
DCCG_PERF_RUN__enumvalues = {
0: 'DCCG_PERF_RUN_NOOP',
1: 'DCCG_PERF_RUN_START',
}
DCCG_PERF_RUN_NOOP = 0
DCCG_PERF_RUN_START = 1
DCCG_PERF_RUN = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_PERF_MODE_VSYNC'
DCCG_PERF_MODE_VSYNC__enumvalues = {
0: 'DCCG_PERF_MODE_VSYNC_NOOP',
1: 'DCCG_PERF_MODE_VSYNC_START',
}
DCCG_PERF_MODE_VSYNC_NOOP = 0
DCCG_PERF_MODE_VSYNC_START = 1
DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_PERF_MODE_HSYNC'
DCCG_PERF_MODE_HSYNC__enumvalues = {
0: 'DCCG_PERF_MODE_HSYNC_NOOP',
1: 'DCCG_PERF_MODE_HSYNC_START',
}
DCCG_PERF_MODE_HSYNC_NOOP = 0
DCCG_PERF_MODE_HSYNC_START = 1
DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_PERF_OTG_SELECT'
DCCG_PERF_OTG_SELECT__enumvalues = {
0: 'DCCG_PERF_SEL_OTG0',
1: 'DCCG_PERF_SEL_OTG1',
2: 'DCCG_PERF_SEL_OTG2',
3: 'DCCG_PERF_SEL_OTG3',
4: 'DCCG_PERF_SEL_OTG4',
5: 'DCCG_PERF_SEL_OTG5',
6: 'DCCG_PERF_SEL_RESERVED',
}
DCCG_PERF_SEL_OTG0 = 0
DCCG_PERF_SEL_OTG1 = 1
DCCG_PERF_SEL_OTG2 = 2
DCCG_PERF_SEL_OTG3 = 3
DCCG_PERF_SEL_OTG4 = 4
DCCG_PERF_SEL_OTG5 = 5
DCCG_PERF_SEL_RESERVED = 6
DCCG_PERF_OTG_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'CLOCK_BRANCH_SOFT_RESET'
CLOCK_BRANCH_SOFT_RESET__enumvalues = {
0: 'CLOCK_BRANCH_SOFT_RESET_NOOP',
1: 'CLOCK_BRANCH_SOFT_RESET_FORCE',
}
CLOCK_BRANCH_SOFT_RESET_NOOP = 0
CLOCK_BRANCH_SOFT_RESET_FORCE = 1
CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'PLL_CFG_IF_SOFT_RESET'
PLL_CFG_IF_SOFT_RESET__enumvalues = {
0: 'PLL_CFG_IF_SOFT_RESET_NOOP',
1: 'PLL_CFG_IF_SOFT_RESET_FORCE',
}
PLL_CFG_IF_SOFT_RESET_NOOP = 0
PLL_CFG_IF_SOFT_RESET_FORCE = 1
PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DVO_ENABLE_RST'
DVO_ENABLE_RST__enumvalues = {
0: 'DVO_ENABLE_RST_DISABLE',
1: 'DVO_ENABLE_RST_ENABLE',
}
DVO_ENABLE_RST_DISABLE = 0
DVO_ENABLE_RST_ENABLE = 1
DVO_ENABLE_RST = ctypes.c_uint32 # enum
# values for enumeration 'DS_JITTER_COUNT_SRC_SEL'
DS_JITTER_COUNT_SRC_SEL__enumvalues = {
0: 'DS_JITTER_COUNT_SRC_SEL0',
1: 'DS_JITTER_COUNT_SRC_SEL1',
}
DS_JITTER_COUNT_SRC_SEL0 = 0
DS_JITTER_COUNT_SRC_SEL1 = 1
DS_JITTER_COUNT_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIO_FIFO_ERROR'
DIO_FIFO_ERROR__enumvalues = {
0: 'DIO_FIFO_ERROR_00',
1: 'DIO_FIFO_ERROR_01',
2: 'DIO_FIFO_ERROR_10',
3: 'DIO_FIFO_ERROR_11',
}
DIO_FIFO_ERROR_00 = 0
DIO_FIFO_ERROR_01 = 1
DIO_FIFO_ERROR_10 = 2
DIO_FIFO_ERROR_11 = 3
DIO_FIFO_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'VSYNC_CNT_REFCLK_SEL'
VSYNC_CNT_REFCLK_SEL__enumvalues = {
0: 'VSYNC_CNT_REFCLK_SEL_0',
1: 'VSYNC_CNT_REFCLK_SEL_1',
}
VSYNC_CNT_REFCLK_SEL_0 = 0
VSYNC_CNT_REFCLK_SEL_1 = 1
VSYNC_CNT_REFCLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'VSYNC_CNT_RESET_SEL'
VSYNC_CNT_RESET_SEL__enumvalues = {
0: 'VSYNC_CNT_RESET_SEL_0',
1: 'VSYNC_CNT_RESET_SEL_1',
}
VSYNC_CNT_RESET_SEL_0 = 0
VSYNC_CNT_RESET_SEL_1 = 1
VSYNC_CNT_RESET_SEL = ctypes.c_uint32 # enum
# values for enumeration 'VSYNC_CNT_LATCH_MASK'
VSYNC_CNT_LATCH_MASK__enumvalues = {
0: 'VSYNC_CNT_LATCH_MASK_0',
1: 'VSYNC_CNT_LATCH_MASK_1',
}
VSYNC_CNT_LATCH_MASK_0 = 0
VSYNC_CNT_LATCH_MASK_1 = 1
VSYNC_CNT_LATCH_MASK = ctypes.c_uint32 # enum
# values for enumeration 'HPD_INT_CONTROL_ACK'
HPD_INT_CONTROL_ACK__enumvalues = {
0: 'HPD_INT_CONTROL_ACK_0',
1: 'HPD_INT_CONTROL_ACK_1',
}
HPD_INT_CONTROL_ACK_0 = 0
HPD_INT_CONTROL_ACK_1 = 1
HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum
# values for enumeration 'HPD_INT_CONTROL_POLARITY'
HPD_INT_CONTROL_POLARITY__enumvalues = {
0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON',
1: 'HPD_INT_CONTROL_GEN_INT_ON_CON',
}
HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0
HPD_INT_CONTROL_GEN_INT_ON_CON = 1
HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK'
HPD_INT_CONTROL_RX_INT_ACK__enumvalues = {
0: 'HPD_INT_CONTROL_RX_INT_ACK_0',
1: 'HPD_INT_CONTROL_RX_INT_ACK_1',
}
HPD_INT_CONTROL_RX_INT_ACK_0 = 0
HPD_INT_CONTROL_RX_INT_ACK_1 = 1
HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSO_NUM_OF_SST_LINKS'
DP_MSO_NUM_OF_SST_LINKS__enumvalues = {
0: 'DP_MSO_ONE_SSTLINK',
1: 'DP_MSO_TWO_SSTLINK',
2: 'DP_MSO_FOUR_SSTLINK',
}
DP_MSO_ONE_SSTLINK = 0
DP_MSO_TWO_SSTLINK = 1
DP_MSO_FOUR_SSTLINK = 2
DP_MSO_NUM_OF_SST_LINKS = ctypes.c_uint32 # enum
# values for enumeration 'DP_SYNC_POLARITY'
DP_SYNC_POLARITY__enumvalues = {
0: 'DP_SYNC_POLARITY_ACTIVE_HIGH',
1: 'DP_SYNC_POLARITY_ACTIVE_LOW',
}
DP_SYNC_POLARITY_ACTIVE_HIGH = 0
DP_SYNC_POLARITY_ACTIVE_LOW = 1
DP_SYNC_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_COMBINE_PIXEL_NUM'
DP_COMBINE_PIXEL_NUM__enumvalues = {
0: 'DP_COMBINE_ONE_PIXEL',
1: 'DP_COMBINE_TWO_PIXEL',
2: 'DP_COMBINE_FOUR_PIXEL',
}
DP_COMBINE_ONE_PIXEL = 0
DP_COMBINE_TWO_PIXEL = 1
DP_COMBINE_FOUR_PIXEL = 2
DP_COMBINE_PIXEL_NUM = ctypes.c_uint32 # enum
# values for enumeration 'DP_LINK_TRAINING_COMPLETE'
DP_LINK_TRAINING_COMPLETE__enumvalues = {
0: 'DP_LINK_TRAINING_NOT_COMPLETE',
1: 'DP_LINK_TRAINING_ALREADY_COMPLETE',
}
DP_LINK_TRAINING_NOT_COMPLETE = 0
DP_LINK_TRAINING_ALREADY_COMPLETE = 1
DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum
# values for enumeration 'DP_EMBEDDED_PANEL_MODE'
DP_EMBEDDED_PANEL_MODE__enumvalues = {
0: 'DP_EXTERNAL_PANEL',
1: 'DP_EMBEDDED_PANEL',
}
DP_EXTERNAL_PANEL = 0
DP_EMBEDDED_PANEL = 1
DP_EMBEDDED_PANEL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_PIXEL_ENCODING'
DP_PIXEL_ENCODING__enumvalues = {
0: 'DP_PIXEL_ENCODING_RGB444',
1: 'DP_PIXEL_ENCODING_YCBCR422',
2: 'DP_PIXEL_ENCODING_YCBCR444',
3: 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT',
4: 'DP_PIXEL_ENCODING_Y_ONLY',
5: 'DP_PIXEL_ENCODING_YCBCR420',
6: 'DP_PIXEL_ENCODING_RESERVED',
}
DP_PIXEL_ENCODING_RGB444 = 0
DP_PIXEL_ENCODING_YCBCR422 = 1
DP_PIXEL_ENCODING_YCBCR444 = 2
DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 3
DP_PIXEL_ENCODING_Y_ONLY = 4
DP_PIXEL_ENCODING_YCBCR420 = 5
DP_PIXEL_ENCODING_RESERVED = 6
DP_PIXEL_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'DP_COMPONENT_DEPTH'
DP_COMPONENT_DEPTH__enumvalues = {
0: 'DP_COMPONENT_DEPTH_6BPC',
1: 'DP_COMPONENT_DEPTH_8BPC',
2: 'DP_COMPONENT_DEPTH_10BPC',
3: 'DP_COMPONENT_DEPTH_12BPC',
4: 'DP_COMPONENT_DEPTH_16BPC_RESERVED',
5: 'DP_COMPONENT_DEPTH_RESERVED',
}
DP_COMPONENT_DEPTH_6BPC = 0
DP_COMPONENT_DEPTH_8BPC = 1
DP_COMPONENT_DEPTH_10BPC = 2
DP_COMPONENT_DEPTH_12BPC = 3
DP_COMPONENT_DEPTH_16BPC_RESERVED = 4
DP_COMPONENT_DEPTH_RESERVED = 5
DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'DP_UDI_LANES'
DP_UDI_LANES__enumvalues = {
0: 'DP_UDI_1_LANE',
1: 'DP_UDI_2_LANES',
2: 'DP_UDI_LANES_RESERVED',
3: 'DP_UDI_4_LANES',
}
DP_UDI_1_LANE = 0
DP_UDI_2_LANES = 1
DP_UDI_LANES_RESERVED = 2
DP_UDI_4_LANES = 3
DP_UDI_LANES = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_STREAM_DIS_DEFER'
DP_VID_STREAM_DIS_DEFER__enumvalues = {
0: 'DP_VID_STREAM_DIS_NO_DEFER',
1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK',
2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK',
}
DP_VID_STREAM_DIS_NO_DEFER = 0
DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1
DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2
DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum
# values for enumeration 'DP_STEER_OVERFLOW_ACK'
DP_STEER_OVERFLOW_ACK__enumvalues = {
0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT',
1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT',
}
DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0
DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1
DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_STEER_OVERFLOW_MASK'
DP_STEER_OVERFLOW_MASK__enumvalues = {
0: 'DP_STEER_OVERFLOW_MASKED',
1: 'DP_STEER_OVERFLOW_UNMASK',
}
DP_STEER_OVERFLOW_MASKED = 0
DP_STEER_OVERFLOW_UNMASK = 1
DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DP_TU_OVERFLOW_ACK'
DP_TU_OVERFLOW_ACK__enumvalues = {
0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT',
1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT',
}
DP_TU_OVERFLOW_ACK_NO_EFFECT = 0
DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1
DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE'
DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = {
0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE',
1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START',
}
DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0
DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1
DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_M_N_GEN_EN'
DP_VID_M_N_GEN_EN__enumvalues = {
0: 'DP_VID_M_N_PROGRAMMED_VIA_REG',
1: 'DP_VID_M_N_CALC_AUTO',
}
DP_VID_M_N_PROGRAMMED_VIA_REG = 0
DP_VID_M_N_CALC_AUTO = 1
DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_N_MUL'
DP_VID_N_MUL__enumvalues = {
0: 'DP_VID_M_1X_INPUT_PIXEL_RATE',
1: 'DP_VID_M_2X_INPUT_PIXEL_RATE',
2: 'DP_VID_M_4X_INPUT_PIXEL_RATE',
3: 'DP_VID_M_8X_INPUT_PIXEL_RATE',
}
DP_VID_M_1X_INPUT_PIXEL_RATE = 0
DP_VID_M_2X_INPUT_PIXEL_RATE = 1
DP_VID_M_4X_INPUT_PIXEL_RATE = 2
DP_VID_M_8X_INPUT_PIXEL_RATE = 3
DP_VID_N_MUL = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE'
DP_VID_ENHANCED_FRAME_MODE__enumvalues = {
0: 'VID_NORMAL_FRAME_MODE',
1: 'VID_ENHANCED_MODE',
}
VID_NORMAL_FRAME_MODE = 0
VID_ENHANCED_MODE = 1
DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_VBID_FIELD_POL'
DP_VID_VBID_FIELD_POL__enumvalues = {
0: 'DP_VID_VBID_FIELD_POL_NORMAL',
1: 'DP_VID_VBID_FIELD_POL_INV',
}
DP_VID_VBID_FIELD_POL_NORMAL = 0
DP_VID_VBID_FIELD_POL_INV = 1
DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_STREAM_DISABLE_ACK'
DP_VID_STREAM_DISABLE_ACK__enumvalues = {
0: 'ID_STREAM_DISABLE_NO_ACK',
1: 'ID_STREAM_DISABLE_ACKED',
}
ID_STREAM_DISABLE_NO_ACK = 0
ID_STREAM_DISABLE_ACKED = 1
DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_STREAM_DISABLE_MASK'
DP_VID_STREAM_DISABLE_MASK__enumvalues = {
0: 'VID_STREAM_DISABLE_MASKED',
1: 'VID_STREAM_DISABLE_UNMASK',
}
VID_STREAM_DISABLE_MASKED = 0
VID_STREAM_DISABLE_UNMASK = 1
DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ATEST_SEL_LANE0'
DPHY_ATEST_SEL_LANE0__enumvalues = {
0: 'DPHY_ATEST_LANE0_PRBS_PATTERN',
1: 'DPHY_ATEST_LANE0_REG_PATTERN',
}
DPHY_ATEST_LANE0_PRBS_PATTERN = 0
DPHY_ATEST_LANE0_REG_PATTERN = 1
DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ATEST_SEL_LANE1'
DPHY_ATEST_SEL_LANE1__enumvalues = {
0: 'DPHY_ATEST_LANE1_PRBS_PATTERN',
1: 'DPHY_ATEST_LANE1_REG_PATTERN',
}
DPHY_ATEST_LANE1_PRBS_PATTERN = 0
DPHY_ATEST_LANE1_REG_PATTERN = 1
DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ATEST_SEL_LANE2'
DPHY_ATEST_SEL_LANE2__enumvalues = {
0: 'DPHY_ATEST_LANE2_PRBS_PATTERN',
1: 'DPHY_ATEST_LANE2_REG_PATTERN',
}
DPHY_ATEST_LANE2_PRBS_PATTERN = 0
DPHY_ATEST_LANE2_REG_PATTERN = 1
DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ATEST_SEL_LANE3'
DPHY_ATEST_SEL_LANE3__enumvalues = {
0: 'DPHY_ATEST_LANE3_PRBS_PATTERN',
1: 'DPHY_ATEST_LANE3_REG_PATTERN',
}
DPHY_ATEST_LANE3_PRBS_PATTERN = 0
DPHY_ATEST_LANE3_REG_PATTERN = 1
DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_BYPASS'
DPHY_BYPASS__enumvalues = {
0: 'DPHY_8B10B_OUTPUT',
1: 'DPHY_DBG_OUTPUT',
}
DPHY_8B10B_OUTPUT = 0
DPHY_DBG_OUTPUT = 1
DPHY_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_SKEW_BYPASS'
DPHY_SKEW_BYPASS__enumvalues = {
0: 'DPHY_WITH_SKEW',
1: 'DPHY_NO_SKEW',
}
DPHY_WITH_SKEW = 0
DPHY_NO_SKEW = 1
DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_TRAINING_PATTERN_SEL'
DPHY_TRAINING_PATTERN_SEL__enumvalues = {
0: 'DPHY_TRAINING_PATTERN_1',
1: 'DPHY_TRAINING_PATTERN_2',
2: 'DPHY_TRAINING_PATTERN_3',
3: 'DPHY_TRAINING_PATTERN_4',
}
DPHY_TRAINING_PATTERN_1 = 0
DPHY_TRAINING_PATTERN_2 = 1
DPHY_TRAINING_PATTERN_3 = 2
DPHY_TRAINING_PATTERN_4 = 3
DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_8B10B_RESET'
DPHY_8B10B_RESET__enumvalues = {
0: 'DPHY_8B10B_NOT_RESET',
1: 'DPHY_8B10B_RESETET',
}
DPHY_8B10B_NOT_RESET = 0
DPHY_8B10B_RESETET = 1
DPHY_8B10B_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_8B10B_EXT_DISP'
DP_DPHY_8B10B_EXT_DISP__enumvalues = {
0: 'DP_DPHY_8B10B_EXT_DISP_ZERO',
1: 'DP_DPHY_8B10B_EXT_DISP_ONE',
}
DP_DPHY_8B10B_EXT_DISP_ZERO = 0
DP_DPHY_8B10B_EXT_DISP_ONE = 1
DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_8B10B_CUR_DISP'
DPHY_8B10B_CUR_DISP__enumvalues = {
0: 'DPHY_8B10B_CUR_DISP_ZERO',
1: 'DPHY_8B10B_CUR_DISP_ONE',
}
DPHY_8B10B_CUR_DISP_ZERO = 0
DPHY_8B10B_CUR_DISP_ONE = 1
DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_PRBS_EN'
DPHY_PRBS_EN__enumvalues = {
0: 'DPHY_PRBS_DISABLE',
1: 'DPHY_PRBS_ENABLE',
}
DPHY_PRBS_DISABLE = 0
DPHY_PRBS_ENABLE = 1
DPHY_PRBS_EN = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_PRBS_SEL'
DPHY_PRBS_SEL__enumvalues = {
0: 'DPHY_PRBS7_SELECTED',
1: 'DPHY_PRBS23_SELECTED',
2: 'DPHY_PRBS11_SELECTED',
}
DPHY_PRBS7_SELECTED = 0
DPHY_PRBS23_SELECTED = 1
DPHY_PRBS11_SELECTED = 2
DPHY_PRBS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_FEC_ENABLE'
DPHY_FEC_ENABLE__enumvalues = {
0: 'DPHY_FEC_DISABLED',
1: 'DPHY_FEC_ENABLED',
}
DPHY_FEC_DISABLED = 0
DPHY_FEC_ENABLED = 1
DPHY_FEC_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'FEC_ACTIVE_STATUS'
FEC_ACTIVE_STATUS__enumvalues = {
0: 'DPHY_FEC_NOT_ACTIVE',
1: 'DPHY_FEC_ACTIVE',
}
DPHY_FEC_NOT_ACTIVE = 0
DPHY_FEC_ACTIVE = 1
FEC_ACTIVE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_FEC_READY'
DPHY_FEC_READY__enumvalues = {
0: 'DPHY_FEC_READY_EN',
1: 'DPHY_FEC_READY_DIS',
}
DPHY_FEC_READY_EN = 0
DPHY_FEC_READY_DIS = 1
DPHY_FEC_READY = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_LOAD_BS_COUNT_START'
DPHY_LOAD_BS_COUNT_START__enumvalues = {
0: 'DPHY_LOAD_BS_COUNT_STARTED',
1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED',
}
DPHY_LOAD_BS_COUNT_STARTED = 0
DPHY_LOAD_BS_COUNT_NOT_STARTED = 1
DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_EN'
DPHY_CRC_EN__enumvalues = {
0: 'DPHY_CRC_DISABLED',
1: 'DPHY_CRC_ENABLED',
}
DPHY_CRC_DISABLED = 0
DPHY_CRC_ENABLED = 1
DPHY_CRC_EN = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_CONT_EN'
DPHY_CRC_CONT_EN__enumvalues = {
0: 'DPHY_CRC_ONE_SHOT',
1: 'DPHY_CRC_CONTINUOUS',
}
DPHY_CRC_ONE_SHOT = 0
DPHY_CRC_CONTINUOUS = 1
DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_FIELD'
DPHY_CRC_FIELD__enumvalues = {
0: 'DPHY_CRC_START_FROM_TOP_FIELD',
1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD',
}
DPHY_CRC_START_FROM_TOP_FIELD = 0
DPHY_CRC_START_FROM_BOTTOM_FIELD = 1
DPHY_CRC_FIELD = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_SEL'
DPHY_CRC_SEL__enumvalues = {
0: 'DPHY_CRC_LANE0_SELECTED',
1: 'DPHY_CRC_LANE1_SELECTED',
2: 'DPHY_CRC_LANE2_SELECTED',
3: 'DPHY_CRC_LANE3_SELECTED',
}
DPHY_CRC_LANE0_SELECTED = 0
DPHY_CRC_LANE1_SELECTED = 1
DPHY_CRC_LANE2_SELECTED = 2
DPHY_CRC_LANE3_SELECTED = 3
DPHY_CRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE'
DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = {
0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0',
1: 'DPHY_FAST_TRAINING_CAPABLE',
}
DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0
DPHY_FAST_TRAINING_CAPABLE = 1
DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_COLLISION_ACK'
DP_SEC_COLLISION_ACK__enumvalues = {
0: 'DP_SEC_COLLISION_ACK_NO_EFFECT',
1: 'DP_SEC_COLLISION_ACK_CLR_FLAG',
}
DP_SEC_COLLISION_ACK_NO_EFFECT = 0
DP_SEC_COLLISION_ACK_CLR_FLAG = 1
DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_AUDIO_MUTE'
DP_SEC_AUDIO_MUTE__enumvalues = {
0: 'DP_SEC_AUDIO_MUTE_HW_CTRL',
1: 'DP_SEC_AUDIO_MUTE_SW_CTRL',
}
DP_SEC_AUDIO_MUTE_HW_CTRL = 0
DP_SEC_AUDIO_MUTE_SW_CTRL = 1
DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_TIMESTAMP_MODE'
DP_SEC_TIMESTAMP_MODE__enumvalues = {
0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE',
1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE',
}
DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0
DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1
DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_ASP_PRIORITY'
DP_SEC_ASP_PRIORITY__enumvalues = {
0: 'DP_SEC_ASP_LOW_PRIORITY',
1: 'DP_SEC_ASP_HIGH_PRIORITY',
}
DP_SEC_ASP_LOW_PRIORITY = 0
DP_SEC_ASP_HIGH_PRIORITY = 1
DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE'
DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = {
0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ',
1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED',
}
DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0
DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1
DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_SAT_UPDATE_ACT'
DP_MSE_SAT_UPDATE_ACT__enumvalues = {
0: 'DP_MSE_SAT_UPDATE_NO_ACTION',
1: 'DP_MSE_SAT_UPDATE_WITH_TRIGGER',
2: 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER',
}
DP_MSE_SAT_UPDATE_NO_ACTION = 0
DP_MSE_SAT_UPDATE_WITH_TRIGGER = 1
DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 2
DP_MSE_SAT_UPDATE_ACT = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_LINK_LINE'
DP_MSE_LINK_LINE__enumvalues = {
0: 'DP_MSE_LINK_LINE_32_MTP_LONG',
1: 'DP_MSE_LINK_LINE_64_MTP_LONG',
2: 'DP_MSE_LINK_LINE_128_MTP_LONG',
3: 'DP_MSE_LINK_LINE_256_MTP_LONG',
}
DP_MSE_LINK_LINE_32_MTP_LONG = 0
DP_MSE_LINK_LINE_64_MTP_LONG = 1
DP_MSE_LINK_LINE_128_MTP_LONG = 2
DP_MSE_LINK_LINE_256_MTP_LONG = 3
DP_MSE_LINK_LINE = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_BLANK_CODE'
DP_MSE_BLANK_CODE__enumvalues = {
0: 'DP_MSE_BLANK_CODE_SF_FILLED',
1: 'DP_MSE_BLANK_CODE_ZERO_FILLED',
}
DP_MSE_BLANK_CODE_SF_FILLED = 0
DP_MSE_BLANK_CODE_ZERO_FILLED = 1
DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_TIMESTAMP_MODE'
DP_MSE_TIMESTAMP_MODE__enumvalues = {
0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE',
1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE',
}
DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0
DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1
DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_ZERO_ENCODER'
DP_MSE_ZERO_ENCODER__enumvalues = {
0: 'DP_MSE_NOT_ZERO_FE_ENCODER',
1: 'DP_MSE_ZERO_FE_ENCODER',
}
DP_MSE_NOT_ZERO_FE_ENCODER = 0
DP_MSE_ZERO_FE_ENCODER = 1
DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE'
DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = {
0: 'DP_DPHY_HBR2_PASS_THROUGH',
1: 'DP_DPHY_HBR2_PATTERN_1',
2: 'DP_DPHY_HBR2_PATTERN_2_NEG',
3: 'DP_DPHY_HBR2_PATTERN_3',
6: 'DP_DPHY_HBR2_PATTERN_2_POS',
}
DP_DPHY_HBR2_PASS_THROUGH = 0
DP_DPHY_HBR2_PATTERN_1 = 1
DP_DPHY_HBR2_PATTERN_2_NEG = 2
DP_DPHY_HBR2_PATTERN_3 = 3
DP_DPHY_HBR2_PATTERN_2_POS = 6
DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK'
DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = {
0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK',
1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED',
}
DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0
DPHY_CRC_MST_PHASE_ERROR_ACKED = 1
DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_SW_FAST_TRAINING_START'
DPHY_SW_FAST_TRAINING_START__enumvalues = {
0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED',
1: 'DPHY_SW_FAST_TRAINING_STARTED',
}
DPHY_SW_FAST_TRAINING_NOT_STARTED = 0
DPHY_SW_FAST_TRAINING_STARTED = 1
DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN'
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = {
0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED',
1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED',
}
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK'
DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = {
0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED',
1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED',
}
DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0
DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1
DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK'
DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = {
0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED',
1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED',
}
DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0
DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1
DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN'
DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = {
0: 'MSA_V_TIMING_OVERRIDE_DISABLED',
1: 'MSA_V_TIMING_OVERRIDE_ENABLED',
}
MSA_V_TIMING_OVERRIDE_DISABLED = 0
MSA_V_TIMING_OVERRIDE_ENABLED = 1
DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_GSP0_PRIORITY'
DP_SEC_GSP0_PRIORITY__enumvalues = {
0: 'SEC_GSP0_PRIORITY_LOW',
1: 'SEC_GSP0_PRIORITY_HIGH',
}
SEC_GSP0_PRIORITY_LOW = 0
SEC_GSP0_PRIORITY_HIGH = 1
DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_GSP_SEND'
DP_SEC_GSP_SEND__enumvalues = {
0: 'NOT_SENT',
1: 'FORCE_SENT',
}
NOT_SENT = 0
FORCE_SENT = 1
DP_SEC_GSP_SEND = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_GSP_SEND_ANY_LINE'
DP_SEC_GSP_SEND_ANY_LINE__enumvalues = {
0: 'SEND_AT_LINK_NUMBER',
1: 'SEND_AT_EARLIEST_TIME',
}
SEND_AT_LINK_NUMBER = 0
SEND_AT_EARLIEST_TIME = 1
DP_SEC_GSP_SEND_ANY_LINE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_LINE_REFERENCE'
DP_SEC_LINE_REFERENCE__enumvalues = {
0: 'REFER_TO_DP_SOF',
1: 'REFER_TO_OTG_SOF',
}
REFER_TO_DP_SOF = 0
REFER_TO_OTG_SOF = 1
DP_SEC_LINE_REFERENCE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_GSP_SEND_PPS'
DP_SEC_GSP_SEND_PPS__enumvalues = {
0: 'SEND_NORMAL_PACKET',
1: 'SEND_PPS_PACKET',
}
SEND_NORMAL_PACKET = 0
SEND_PPS_PACKET = 1
DP_SEC_GSP_SEND_PPS = ctypes.c_uint32 # enum
# values for enumeration 'DP_ML_PHY_SEQ_MODE'
DP_ML_PHY_SEQ_MODE__enumvalues = {
0: 'DP_ML_PHY_SEQ_LINE_NUM',
1: 'DP_ML_PHY_SEQ_IMMEDIATE',
}
DP_ML_PHY_SEQ_LINE_NUM = 0
DP_ML_PHY_SEQ_IMMEDIATE = 1
DP_ML_PHY_SEQ_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_LINK_TRAINING_SWITCH_MODE'
DP_LINK_TRAINING_SWITCH_MODE__enumvalues = {
0: 'DP_LINK_TRAINING_SWITCH_TO_IDLE',
1: 'DP_LINK_TRAINING_SWITCH_TO_VIDEO',
}
DP_LINK_TRAINING_SWITCH_TO_IDLE = 0
DP_LINK_TRAINING_SWITCH_TO_VIDEO = 1
DP_LINK_TRAINING_SWITCH_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_DSC_MODE'
DP_DSC_MODE__enumvalues = {
0: 'DP_DSC_DISABLE',
1: 'DP_DSC_444_SIMPLE_422',
2: 'DP_DSC_NATIVE_422_420',
}
DP_DSC_DISABLE = 0
DP_DSC_444_SIMPLE_422 = 1
DP_DSC_NATIVE_422_420 = 2
DP_DSC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_KEEPOUT_MODE'
HDMI_KEEPOUT_MODE__enumvalues = {
0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC',
1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC',
}
HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0
HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1
HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE'
HDMI_CLOCK_CHANNEL_RATE__enumvalues = {
0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE',
1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE',
}
HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0
HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1
HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED'
HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = {
0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE',
1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE',
}
HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0
HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1
HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_PACKET_GEN_VERSION'
HDMI_PACKET_GEN_VERSION__enumvalues = {
0: 'HDMI_PACKET_GEN_VERSION_OLD',
1: 'HDMI_PACKET_GEN_VERSION_NEW',
}
HDMI_PACKET_GEN_VERSION_OLD = 0
HDMI_PACKET_GEN_VERSION_NEW = 1
HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ERROR_ACK'
HDMI_ERROR_ACK__enumvalues = {
0: 'HDMI_ERROR_ACK_INT',
1: 'HDMI_ERROR_NOT_ACK',
}
HDMI_ERROR_ACK_INT = 0
HDMI_ERROR_NOT_ACK = 1
HDMI_ERROR_ACK = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ERROR_MASK'
HDMI_ERROR_MASK__enumvalues = {
0: 'HDMI_ERROR_MASK_INT',
1: 'HDMI_ERROR_NOT_MASK',
}
HDMI_ERROR_MASK_INT = 0
HDMI_ERROR_NOT_MASK = 1
HDMI_ERROR_MASK = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_DEEP_COLOR_DEPTH'
HDMI_DEEP_COLOR_DEPTH__enumvalues = {
0: 'HDMI_DEEP_COLOR_DEPTH_24BPP',
1: 'HDMI_DEEP_COLOR_DEPTH_30BPP',
2: 'HDMI_DEEP_COLOR_DEPTH_36BPP',
3: 'HDMI_DEEP_COLOR_DEPTH_48BPP',
}
HDMI_DEEP_COLOR_DEPTH_24BPP = 0
HDMI_DEEP_COLOR_DEPTH_30BPP = 1
HDMI_DEEP_COLOR_DEPTH_36BPP = 2
HDMI_DEEP_COLOR_DEPTH_48BPP = 3
HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_AUDIO_DELAY_EN'
HDMI_AUDIO_DELAY_EN__enumvalues = {
0: 'HDMI_AUDIO_DELAY_DISABLE',
1: 'HDMI_AUDIO_DELAY_58CLK',
2: 'HDMI_AUDIO_DELAY_56CLK',
3: 'HDMI_AUDIO_DELAY_RESERVED',
}
HDMI_AUDIO_DELAY_DISABLE = 0
HDMI_AUDIO_DELAY_58CLK = 1
HDMI_AUDIO_DELAY_56CLK = 2
HDMI_AUDIO_DELAY_RESERVED = 3
HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_AUDIO_SEND_MAX_PACKETS'
HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = {
0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS',
1: 'HDMI_SEND_MAX_AUDIO_PACKETS',
}
HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0
HDMI_SEND_MAX_AUDIO_PACKETS = 1
HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_SEND'
HDMI_ACR_SEND__enumvalues = {
0: 'HDMI_ACR_NOT_SEND',
1: 'HDMI_ACR_PKT_SEND',
}
HDMI_ACR_NOT_SEND = 0
HDMI_ACR_PKT_SEND = 1
HDMI_ACR_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_CONT'
HDMI_ACR_CONT__enumvalues = {
0: 'HDMI_ACR_CONT_DISABLE',
1: 'HDMI_ACR_CONT_ENABLE',
}
HDMI_ACR_CONT_DISABLE = 0
HDMI_ACR_CONT_ENABLE = 1
HDMI_ACR_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_SELECT'
HDMI_ACR_SELECT__enumvalues = {
0: 'HDMI_ACR_SELECT_HW',
1: 'HDMI_ACR_SELECT_32K',
2: 'HDMI_ACR_SELECT_44K',
3: 'HDMI_ACR_SELECT_48K',
}
HDMI_ACR_SELECT_HW = 0
HDMI_ACR_SELECT_32K = 1
HDMI_ACR_SELECT_44K = 2
HDMI_ACR_SELECT_48K = 3
HDMI_ACR_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_SOURCE'
HDMI_ACR_SOURCE__enumvalues = {
0: 'HDMI_ACR_SOURCE_HW',
1: 'HDMI_ACR_SOURCE_SW',
}
HDMI_ACR_SOURCE_HW = 0
HDMI_ACR_SOURCE_SW = 1
HDMI_ACR_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_N_MULTIPLE'
HDMI_ACR_N_MULTIPLE__enumvalues = {
0: 'HDMI_ACR_0_MULTIPLE_RESERVED',
1: 'HDMI_ACR_1_MULTIPLE',
2: 'HDMI_ACR_2_MULTIPLE',
3: 'HDMI_ACR_3_MULTIPLE_RESERVED',
4: 'HDMI_ACR_4_MULTIPLE',
5: 'HDMI_ACR_5_MULTIPLE_RESERVED',
6: 'HDMI_ACR_6_MULTIPLE_RESERVED',
7: 'HDMI_ACR_7_MULTIPLE_RESERVED',
}
HDMI_ACR_0_MULTIPLE_RESERVED = 0
HDMI_ACR_1_MULTIPLE = 1
HDMI_ACR_2_MULTIPLE = 2
HDMI_ACR_3_MULTIPLE_RESERVED = 3
HDMI_ACR_4_MULTIPLE = 4
HDMI_ACR_5_MULTIPLE_RESERVED = 5
HDMI_ACR_6_MULTIPLE_RESERVED = 6
HDMI_ACR_7_MULTIPLE_RESERVED = 7
HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY'
HDMI_ACR_AUDIO_PRIORITY__enumvalues = {
0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE',
1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT',
}
HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0
HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1
HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_NULL_SEND'
HDMI_NULL_SEND__enumvalues = {
0: 'HDMI_NULL_NOT_SEND',
1: 'HDMI_NULL_PKT_SEND',
}
HDMI_NULL_NOT_SEND = 0
HDMI_NULL_PKT_SEND = 1
HDMI_NULL_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GC_SEND'
HDMI_GC_SEND__enumvalues = {
0: 'HDMI_GC_NOT_SEND',
1: 'HDMI_GC_PKT_SEND',
}
HDMI_GC_NOT_SEND = 0
HDMI_GC_PKT_SEND = 1
HDMI_GC_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GC_CONT'
HDMI_GC_CONT__enumvalues = {
0: 'HDMI_GC_CONT_DISABLE',
1: 'HDMI_GC_CONT_ENABLE',
}
HDMI_GC_CONT_DISABLE = 0
HDMI_GC_CONT_ENABLE = 1
HDMI_GC_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ISRC_SEND'
HDMI_ISRC_SEND__enumvalues = {
0: 'HDMI_ISRC_NOT_SEND',
1: 'HDMI_ISRC_PKT_SEND',
}
HDMI_ISRC_NOT_SEND = 0
HDMI_ISRC_PKT_SEND = 1
HDMI_ISRC_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ISRC_CONT'
HDMI_ISRC_CONT__enumvalues = {
0: 'HDMI_ISRC_CONT_DISABLE',
1: 'HDMI_ISRC_CONT_ENABLE',
}
HDMI_ISRC_CONT_DISABLE = 0
HDMI_ISRC_CONT_ENABLE = 1
HDMI_ISRC_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_AUDIO_INFO_SEND'
HDMI_AUDIO_INFO_SEND__enumvalues = {
0: 'HDMI_AUDIO_INFO_NOT_SEND',
1: 'HDMI_AUDIO_INFO_PKT_SEND',
}
HDMI_AUDIO_INFO_NOT_SEND = 0
HDMI_AUDIO_INFO_PKT_SEND = 1
HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_AUDIO_INFO_CONT'
HDMI_AUDIO_INFO_CONT__enumvalues = {
0: 'HDMI_AUDIO_INFO_CONT_DISABLE',
1: 'HDMI_AUDIO_INFO_CONT_ENABLE',
}
HDMI_AUDIO_INFO_CONT_DISABLE = 0
HDMI_AUDIO_INFO_CONT_ENABLE = 1
HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_MPEG_INFO_SEND'
HDMI_MPEG_INFO_SEND__enumvalues = {
0: 'HDMI_MPEG_INFO_NOT_SEND',
1: 'HDMI_MPEG_INFO_PKT_SEND',
}
HDMI_MPEG_INFO_NOT_SEND = 0
HDMI_MPEG_INFO_PKT_SEND = 1
HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_MPEG_INFO_CONT'
HDMI_MPEG_INFO_CONT__enumvalues = {
0: 'HDMI_MPEG_INFO_CONT_DISABLE',
1: 'HDMI_MPEG_INFO_CONT_ENABLE',
}
HDMI_MPEG_INFO_CONT_DISABLE = 0
HDMI_MPEG_INFO_CONT_ENABLE = 1
HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GENERIC_SEND'
HDMI_GENERIC_SEND__enumvalues = {
0: 'HDMI_GENERIC_NOT_SEND',
1: 'HDMI_GENERIC_PKT_SEND',
}
HDMI_GENERIC_NOT_SEND = 0
HDMI_GENERIC_PKT_SEND = 1
HDMI_GENERIC_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GENERIC_CONT'
HDMI_GENERIC_CONT__enumvalues = {
0: 'HDMI_GENERIC_CONT_DISABLE',
1: 'HDMI_GENERIC_CONT_ENABLE',
}
HDMI_GENERIC_CONT_DISABLE = 0
HDMI_GENERIC_CONT_ENABLE = 1
HDMI_GENERIC_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GC_AVMUTE_CONT'
HDMI_GC_AVMUTE_CONT__enumvalues = {
0: 'HDMI_GC_AVMUTE_CONT_DISABLE',
1: 'HDMI_GC_AVMUTE_CONT_ENABLE',
}
HDMI_GC_AVMUTE_CONT_DISABLE = 0
HDMI_GC_AVMUTE_CONT_ENABLE = 1
HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE'
HDMI_PACKING_PHASE_OVERRIDE__enumvalues = {
0: 'HDMI_PACKING_PHASE_SET_BY_HW',
1: 'HDMI_PACKING_PHASE_SET_BY_SW',
}
HDMI_PACKING_PHASE_SET_BY_HW = 0
HDMI_PACKING_PHASE_SET_BY_SW = 1
HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_PIXEL_ENCODING'
TMDS_PIXEL_ENCODING__enumvalues = {
0: 'TMDS_PIXEL_ENCODING_444_OR_420',
1: 'TMDS_PIXEL_ENCODING_422',
}
TMDS_PIXEL_ENCODING_444_OR_420 = 0
TMDS_PIXEL_ENCODING_422 = 1
TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_COLOR_FORMAT'
TMDS_COLOR_FORMAT__enumvalues = {
0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP',
1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB',
2: 'TMDS_COLOR_FORMAT_DUAL30BPP',
3: 'TMDS_COLOR_FORMAT_RESERVED',
}
TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0
TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1
TMDS_COLOR_FORMAT_DUAL30BPP = 2
TMDS_COLOR_FORMAT_RESERVED = 3
TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG'
TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = {
0: 'TMDS_STEREOSYNC_CTL0',
1: 'TMDS_STEREOSYNC_CTL1',
2: 'TMDS_STEREOSYNC_CTL2',
3: 'TMDS_STEREOSYNC_CTL3',
}
TMDS_STEREOSYNC_CTL0 = 0
TMDS_STEREOSYNC_CTL1 = 1
TMDS_STEREOSYNC_CTL2 = 2
TMDS_STEREOSYNC_CTL3 = 3
TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL0_DATA_SEL'
TMDS_CTL0_DATA_SEL__enumvalues = {
0: 'TMDS_CTL0_DATA_SEL0_RESERVED',
1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE',
2: 'TMDS_CTL0_DATA_SEL2_VSYNC',
3: 'TMDS_CTL0_DATA_SEL3_RESERVED',
4: 'TMDS_CTL0_DATA_SEL4_HSYNC',
5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED',
6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA',
7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA',
}
TMDS_CTL0_DATA_SEL0_RESERVED = 0
TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1
TMDS_CTL0_DATA_SEL2_VSYNC = 2
TMDS_CTL0_DATA_SEL3_RESERVED = 3
TMDS_CTL0_DATA_SEL4_HSYNC = 4
TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5
TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6
TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7
TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL0_DATA_INVERT'
TMDS_CTL0_DATA_INVERT__enumvalues = {
0: 'TMDS_CTL0_DATA_NORMAL',
1: 'TMDS_CTL0_DATA_INVERT_EN',
}
TMDS_CTL0_DATA_NORMAL = 0
TMDS_CTL0_DATA_INVERT_EN = 1
TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL0_DATA_MODULATION'
TMDS_CTL0_DATA_MODULATION__enumvalues = {
0: 'TMDS_CTL0_DATA_MODULATION_DISABLE',
1: 'TMDS_CTL0_DATA_MODULATION_BIT0',
2: 'TMDS_CTL0_DATA_MODULATION_BIT1',
3: 'TMDS_CTL0_DATA_MODULATION_BIT2',
}
TMDS_CTL0_DATA_MODULATION_DISABLE = 0
TMDS_CTL0_DATA_MODULATION_BIT0 = 1
TMDS_CTL0_DATA_MODULATION_BIT1 = 2
TMDS_CTL0_DATA_MODULATION_BIT2 = 3
TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN'
TMDS_CTL0_PATTERN_OUT_EN__enumvalues = {
0: 'TMDS_CTL0_PATTERN_OUT_DISABLE',
1: 'TMDS_CTL0_PATTERN_OUT_ENABLE',
}
TMDS_CTL0_PATTERN_OUT_DISABLE = 0
TMDS_CTL0_PATTERN_OUT_ENABLE = 1
TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL1_DATA_SEL'
TMDS_CTL1_DATA_SEL__enumvalues = {
0: 'TMDS_CTL1_DATA_SEL0_RESERVED',
1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE',
2: 'TMDS_CTL1_DATA_SEL2_VSYNC',
3: 'TMDS_CTL1_DATA_SEL3_RESERVED',
4: 'TMDS_CTL1_DATA_SEL4_HSYNC',
5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED',
6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME',
7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED',
}
TMDS_CTL1_DATA_SEL0_RESERVED = 0
TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1
TMDS_CTL1_DATA_SEL2_VSYNC = 2
TMDS_CTL1_DATA_SEL3_RESERVED = 3
TMDS_CTL1_DATA_SEL4_HSYNC = 4
TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5
TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6
TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7
TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL1_DATA_INVERT'
TMDS_CTL1_DATA_INVERT__enumvalues = {
0: 'TMDS_CTL1_DATA_NORMAL',
1: 'TMDS_CTL1_DATA_INVERT_EN',
}
TMDS_CTL1_DATA_NORMAL = 0
TMDS_CTL1_DATA_INVERT_EN = 1
TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL1_DATA_MODULATION'
TMDS_CTL1_DATA_MODULATION__enumvalues = {
0: 'TMDS_CTL1_DATA_MODULATION_DISABLE',
1: 'TMDS_CTL1_DATA_MODULATION_BIT0',
2: 'TMDS_CTL1_DATA_MODULATION_BIT1',
3: 'TMDS_CTL1_DATA_MODULATION_BIT2',
}
TMDS_CTL1_DATA_MODULATION_DISABLE = 0
TMDS_CTL1_DATA_MODULATION_BIT0 = 1
TMDS_CTL1_DATA_MODULATION_BIT1 = 2
TMDS_CTL1_DATA_MODULATION_BIT2 = 3
TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN'
TMDS_CTL1_PATTERN_OUT_EN__enumvalues = {
0: 'TMDS_CTL1_PATTERN_OUT_DISABLE',
1: 'TMDS_CTL1_PATTERN_OUT_ENABLE',
}
TMDS_CTL1_PATTERN_OUT_DISABLE = 0
TMDS_CTL1_PATTERN_OUT_ENABLE = 1
TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL2_DATA_SEL'
TMDS_CTL2_DATA_SEL__enumvalues = {
0: 'TMDS_CTL2_DATA_SEL0_RESERVED',
1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE',
2: 'TMDS_CTL2_DATA_SEL2_VSYNC',
3: 'TMDS_CTL2_DATA_SEL3_RESERVED',
4: 'TMDS_CTL2_DATA_SEL4_HSYNC',
5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED',
6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME',
7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED',
}
TMDS_CTL2_DATA_SEL0_RESERVED = 0
TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1
TMDS_CTL2_DATA_SEL2_VSYNC = 2
TMDS_CTL2_DATA_SEL3_RESERVED = 3
TMDS_CTL2_DATA_SEL4_HSYNC = 4
TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5
TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6
TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7
TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL2_DATA_INVERT'
TMDS_CTL2_DATA_INVERT__enumvalues = {
0: 'TMDS_CTL2_DATA_NORMAL',
1: 'TMDS_CTL2_DATA_INVERT_EN',
}
TMDS_CTL2_DATA_NORMAL = 0
TMDS_CTL2_DATA_INVERT_EN = 1
TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL2_DATA_MODULATION'
TMDS_CTL2_DATA_MODULATION__enumvalues = {
0: 'TMDS_CTL2_DATA_MODULATION_DISABLE',
1: 'TMDS_CTL2_DATA_MODULATION_BIT0',
2: 'TMDS_CTL2_DATA_MODULATION_BIT1',
3: 'TMDS_CTL2_DATA_MODULATION_BIT2',
}
TMDS_CTL2_DATA_MODULATION_DISABLE = 0
TMDS_CTL2_DATA_MODULATION_BIT0 = 1
TMDS_CTL2_DATA_MODULATION_BIT1 = 2
TMDS_CTL2_DATA_MODULATION_BIT2 = 3
TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN'
TMDS_CTL2_PATTERN_OUT_EN__enumvalues = {
0: 'TMDS_CTL2_PATTERN_OUT_DISABLE',
1: 'TMDS_CTL2_PATTERN_OUT_ENABLE',
}
TMDS_CTL2_PATTERN_OUT_DISABLE = 0
TMDS_CTL2_PATTERN_OUT_ENABLE = 1
TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL3_DATA_INVERT'
TMDS_CTL3_DATA_INVERT__enumvalues = {
0: 'TMDS_CTL3_DATA_NORMAL',
1: 'TMDS_CTL3_DATA_INVERT_EN',
}
TMDS_CTL3_DATA_NORMAL = 0
TMDS_CTL3_DATA_INVERT_EN = 1
TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL3_DATA_MODULATION'
TMDS_CTL3_DATA_MODULATION__enumvalues = {
0: 'TMDS_CTL3_DATA_MODULATION_DISABLE',
1: 'TMDS_CTL3_DATA_MODULATION_BIT0',
2: 'TMDS_CTL3_DATA_MODULATION_BIT1',
3: 'TMDS_CTL3_DATA_MODULATION_BIT2',
}
TMDS_CTL3_DATA_MODULATION_DISABLE = 0
TMDS_CTL3_DATA_MODULATION_BIT0 = 1
TMDS_CTL3_DATA_MODULATION_BIT1 = 2
TMDS_CTL3_DATA_MODULATION_BIT2 = 3
TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN'
TMDS_CTL3_PATTERN_OUT_EN__enumvalues = {
0: 'TMDS_CTL3_PATTERN_OUT_DISABLE',
1: 'TMDS_CTL3_PATTERN_OUT_ENABLE',
}
TMDS_CTL3_PATTERN_OUT_DISABLE = 0
TMDS_CTL3_PATTERN_OUT_ENABLE = 1
TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL3_DATA_SEL'
TMDS_CTL3_DATA_SEL__enumvalues = {
0: 'TMDS_CTL3_DATA_SEL0_RESERVED',
1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE',
2: 'TMDS_CTL3_DATA_SEL2_VSYNC',
3: 'TMDS_CTL3_DATA_SEL3_RESERVED',
4: 'TMDS_CTL3_DATA_SEL4_HSYNC',
5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED',
6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME',
7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED',
}
TMDS_CTL3_DATA_SEL0_RESERVED = 0
TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1
TMDS_CTL3_DATA_SEL2_VSYNC = 2
TMDS_CTL3_DATA_SEL3_RESERVED = 3
TMDS_CTL3_DATA_SEL4_HSYNC = 4
TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5
TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6
TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7
TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT'
DIG_FE_CNTL_SOURCE_SELECT__enumvalues = {
0: 'DIG_FE_SOURCE_FROM_OTG0',
1: 'DIG_FE_SOURCE_FROM_OTG1',
2: 'DIG_FE_SOURCE_FROM_OTG2',
3: 'DIG_FE_SOURCE_FROM_OTG3',
4: 'DIG_FE_SOURCE_FROM_OTG4',
5: 'DIG_FE_SOURCE_FROM_OTG5',
6: 'DIG_FE_SOURCE_RESERVED',
}
DIG_FE_SOURCE_FROM_OTG0 = 0
DIG_FE_SOURCE_FROM_OTG1 = 1
DIG_FE_SOURCE_FROM_OTG2 = 2
DIG_FE_SOURCE_FROM_OTG3 = 3
DIG_FE_SOURCE_FROM_OTG4 = 4
DIG_FE_SOURCE_FROM_OTG5 = 5
DIG_FE_SOURCE_RESERVED = 6
DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT'
DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = {
0: 'DIG_FE_STEREOSYNC_FROM_OTG0',
1: 'DIG_FE_STEREOSYNC_FROM_OTG1',
2: 'DIG_FE_STEREOSYNC_FROM_OTG2',
3: 'DIG_FE_STEREOSYNC_FROM_OTG3',
4: 'DIG_FE_STEREOSYNC_FROM_OTG4',
5: 'DIG_FE_STEREOSYNC_FROM_OTG5',
6: 'DIG_FE_STEREOSYNC_RESERVED',
}
DIG_FE_STEREOSYNC_FROM_OTG0 = 0
DIG_FE_STEREOSYNC_FROM_OTG1 = 1
DIG_FE_STEREOSYNC_FROM_OTG2 = 2
DIG_FE_STEREOSYNC_FROM_OTG3 = 3
DIG_FE_STEREOSYNC_FROM_OTG4 = 4
DIG_FE_STEREOSYNC_FROM_OTG5 = 5
DIG_FE_STEREOSYNC_RESERVED = 6
DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC'
DIG_FIFO_READ_CLOCK_SRC__enumvalues = {
0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG',
1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE',
}
DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0
DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1
DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum
# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL'
DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = {
0: 'DIG_OUTPUT_CRC_ON_LINK0',
1: 'DIG_OUTPUT_CRC_ON_LINK1',
}
DIG_OUTPUT_CRC_ON_LINK0 = 0
DIG_OUTPUT_CRC_ON_LINK1 = 1
DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL'
DIG_OUTPUT_CRC_DATA_SEL__enumvalues = {
0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME',
1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY',
2: 'DIG_OUTPUT_CRC_FOR_VBI',
3: 'DIG_OUTPUT_CRC_FOR_AUDIO',
}
DIG_OUTPUT_CRC_FOR_FULLFRAME = 0
DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1
DIG_OUTPUT_CRC_FOR_VBI = 2
DIG_OUTPUT_CRC_FOR_AUDIO = 3
DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN'
DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = {
0: 'DIG_IN_NORMAL_OPERATION',
1: 'DIG_IN_DEBUG_MODE',
}
DIG_IN_NORMAL_OPERATION = 0
DIG_IN_DEBUG_MODE = 1
DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL'
DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = {
0: 'DIG_10BIT_TEST_PATTERN',
1: 'DIG_ALTERNATING_TEST_PATTERN',
}
DIG_10BIT_TEST_PATTERN = 0
DIG_ALTERNATING_TEST_PATTERN = 1
DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN'
DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = {
0: 'DIG_TEST_PATTERN_NORMAL',
1: 'DIG_TEST_PATTERN_RANDOM',
}
DIG_TEST_PATTERN_NORMAL = 0
DIG_TEST_PATTERN_RANDOM = 1
DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET'
DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = {
0: 'DIG_RANDOM_PATTERN_ENABLED',
1: 'DIG_RANDOM_PATTERN_RESETED',
}
DIG_RANDOM_PATTERN_ENABLED = 0
DIG_RANDOM_PATTERN_RESETED = 1
DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN'
DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = {
0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE',
1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG',
}
DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0
DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1
DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum
# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT'
DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = {
0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS',
1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH',
}
DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0
DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1
DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL'
DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL__enumvalues = {
0: 'DIG_FIFO_USE_OVERWRITE_LEVEL',
1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL',
}
DIG_FIFO_USE_OVERWRITE_LEVEL = 0
DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1
DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_ERROR_ACK'
DIG_FIFO_ERROR_ACK__enumvalues = {
0: 'DIG_FIFO_ERROR_ACK_INT',
1: 'DIG_FIFO_ERROR_NOT_ACK',
}
DIG_FIFO_ERROR_ACK_INT = 0
DIG_FIFO_ERROR_NOT_ACK = 1
DIG_FIFO_ERROR_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE'
DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE__enumvalues = {
0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE',
1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL',
}
DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0
DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1
DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX'
DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX__enumvalues = {
0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX',
1: 'DIG_FIFO_FORCE_RECOMP_MINMAX',
}
DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0
DIG_FIFO_FORCE_RECOMP_MINMAX = 1
DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK'
AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = {
0: 'AFMT_INTERRUPT_DISABLE',
1: 'AFMT_INTERRUPT_ENABLE',
}
AFMT_INTERRUPT_DISABLE = 0
AFMT_INTERRUPT_ENABLE = 1
AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GC_AVMUTE'
HDMI_GC_AVMUTE__enumvalues = {
0: 'HDMI_GC_AVMUTE_SET',
1: 'HDMI_GC_AVMUTE_UNSET',
}
HDMI_GC_AVMUTE_SET = 0
HDMI_GC_AVMUTE_UNSET = 1
HDMI_GC_AVMUTE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_DEFAULT_PAHSE'
HDMI_DEFAULT_PAHSE__enumvalues = {
0: 'HDMI_DEFAULT_PHASE_IS_0',
1: 'HDMI_DEFAULT_PHASE_IS_1',
}
HDMI_DEFAULT_PHASE_IS_0 = 0
HDMI_DEFAULT_PHASE_IS_1 = 1
HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD'
AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = {
0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS',
1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER',
}
AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0
AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1
AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum
# values for enumeration 'AUDIO_LAYOUT_SELECT'
AUDIO_LAYOUT_SELECT__enumvalues = {
0: 'AUDIO_LAYOUT_0',
1: 'AUDIO_LAYOUT_1',
}
AUDIO_LAYOUT_0 = 0
AUDIO_LAYOUT_1 = 1
AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT'
AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = {
0: 'AFMT_AUDIO_CRC_ONESHOT',
1: 'AFMT_AUDIO_CRC_AUTO_RESTART',
}
AFMT_AUDIO_CRC_ONESHOT = 0
AFMT_AUDIO_CRC_AUTO_RESTART = 1
AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE'
AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = {
0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT',
1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT',
}
AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0
AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1
AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL'
AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = {
0: 'AFMT_AUDIO_CRC_CH0_SIG',
1: 'AFMT_AUDIO_CRC_CH1_SIG',
2: 'AFMT_AUDIO_CRC_CH2_SIG',
3: 'AFMT_AUDIO_CRC_CH3_SIG',
4: 'AFMT_AUDIO_CRC_CH4_SIG',
5: 'AFMT_AUDIO_CRC_CH5_SIG',
6: 'AFMT_AUDIO_CRC_CH6_SIG',
7: 'AFMT_AUDIO_CRC_CH7_SIG',
8: 'AFMT_AUDIO_CRC_RESERVED_8',
9: 'AFMT_AUDIO_CRC_RESERVED_9',
10: 'AFMT_AUDIO_CRC_RESERVED_10',
11: 'AFMT_AUDIO_CRC_RESERVED_11',
12: 'AFMT_AUDIO_CRC_RESERVED_12',
13: 'AFMT_AUDIO_CRC_RESERVED_13',
14: 'AFMT_AUDIO_CRC_RESERVED_14',
15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT',
}
AFMT_AUDIO_CRC_CH0_SIG = 0
AFMT_AUDIO_CRC_CH1_SIG = 1
AFMT_AUDIO_CRC_CH2_SIG = 2
AFMT_AUDIO_CRC_CH3_SIG = 3
AFMT_AUDIO_CRC_CH4_SIG = 4
AFMT_AUDIO_CRC_CH5_SIG = 5
AFMT_AUDIO_CRC_CH6_SIG = 6
AFMT_AUDIO_CRC_CH7_SIG = 7
AFMT_AUDIO_CRC_RESERVED_8 = 8
AFMT_AUDIO_CRC_RESERVED_9 = 9
AFMT_AUDIO_CRC_RESERVED_10 = 10
AFMT_AUDIO_CRC_RESERVED_11 = 11
AFMT_AUDIO_CRC_RESERVED_12 = 12
AFMT_AUDIO_CRC_RESERVED_13 = 13
AFMT_AUDIO_CRC_RESERVED_14 = 14
AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15
AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN'
AFMT_RAMP_CONTROL0_SIGN__enumvalues = {
0: 'AFMT_RAMP_SIGNED',
1: 'AFMT_RAMP_UNSIGNED',
}
AFMT_RAMP_SIGNED = 0
AFMT_RAMP_UNSIGNED = 1
AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND'
AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = {
0: 'AFMT_AUDIO_PACKET_SENT_DISABLED',
1: 'AFMT_AUDIO_PACKET_SENT_ENABLED',
}
AFMT_AUDIO_PACKET_SENT_DISABLED = 0
AFMT_AUDIO_PACKET_SENT_ENABLED = 1
AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS'
AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = {
0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED',
1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED',
}
AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0
AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1
AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE'
AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = {
0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK',
1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS',
}
AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0
AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1
AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT'
AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = {
0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0',
1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1',
2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2',
3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3',
4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4',
5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5',
6: 'AFMT_AUDIO_SRC_RESERVED',
}
AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0
AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1
AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2
AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3
AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4
AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5
AFMT_AUDIO_SRC_RESERVED = 6
AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DIG_BE_CNTL_MODE'
DIG_BE_CNTL_MODE__enumvalues = {
0: 'DIG_BE_DP_SST_MODE',
1: 'DIG_BE_RESERVED1',
2: 'DIG_BE_TMDS_DVI_MODE',
3: 'DIG_BE_TMDS_HDMI_MODE',
4: 'DIG_BE_RESERVED4',
5: 'DIG_BE_DP_MST_MODE',
6: 'DIG_BE_RESERVED2',
7: 'DIG_BE_RESERVED3',
}
DIG_BE_DP_SST_MODE = 0
DIG_BE_RESERVED1 = 1
DIG_BE_TMDS_DVI_MODE = 2
DIG_BE_TMDS_HDMI_MODE = 3
DIG_BE_RESERVED4 = 4
DIG_BE_DP_MST_MODE = 5
DIG_BE_RESERVED2 = 6
DIG_BE_RESERVED3 = 7
DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DIG_BE_CNTL_HPD_SELECT'
DIG_BE_CNTL_HPD_SELECT__enumvalues = {
0: 'DIG_BE_CNTL_HPD1',
1: 'DIG_BE_CNTL_HPD2',
2: 'DIG_BE_CNTL_HPD3',
3: 'DIG_BE_CNTL_HPD4',
4: 'DIG_BE_CNTL_HPD5',
5: 'DIG_BE_CNTL_HPD6',
6: 'DIG_BE_CNTL_NO_HPD',
}
DIG_BE_CNTL_HPD1 = 0
DIG_BE_CNTL_HPD2 = 1
DIG_BE_CNTL_HPD3 = 2
DIG_BE_CNTL_HPD4 = 3
DIG_BE_CNTL_HPD5 = 4
DIG_BE_CNTL_HPD6 = 5
DIG_BE_CNTL_NO_HPD = 6
DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT'
LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = {
0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS',
1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH',
}
LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0
LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1
LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_SYNC_PHASE'
TMDS_SYNC_PHASE__enumvalues = {
0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START',
1: 'TMDS_SYNC_PHASE_ON_FRAME_START',
}
TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0
TMDS_SYNC_PHASE_ON_FRAME_START = 1
TMDS_SYNC_PHASE = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL'
TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = {
0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS',
1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL',
}
TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0
TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1
TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK'
TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE',
1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE',
}
TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0
TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1
TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK'
TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE',
1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE',
}
TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0
TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1
TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK'
TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE',
1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE',
}
TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0
TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1
TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK'
TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE',
1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON',
2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON',
3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE',
}
TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3
TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA'
TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = {
0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK',
1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK',
}
TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0
TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1
TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB'
TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = {
0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK',
1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK',
}
TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0
TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1
TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN'
TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = {
0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE',
1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE',
}
TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0
TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1
TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK'
TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD',
1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD',
}
TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0
TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1
TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS'
TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = {
0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK',
1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS',
}
TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0
TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1
TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS'
TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = {
0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK',
1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS',
}
TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0
TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1
TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN'
TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = {
0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW',
1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW',
}
TMDS_TRANSMITTER_PLLSEL_BY_HW = 0
TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1
TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA'
TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = {
0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT',
1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT',
}
TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0
TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1
TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB'
TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = {
0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT',
1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT',
}
TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0
TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1
TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA'
TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = {
0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0',
1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1',
2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2',
3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA',
}
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2
TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3
TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB'
TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = {
0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0',
1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1',
2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2',
3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA',
}
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2
TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3
TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_VBI_GSP_INDEX'
AFMT_VBI_GSP_INDEX__enumvalues = {
0: 'AFMT_VBI_GSP0_INDEX',
1: 'AFMT_VBI_GSP1_INDEX',
2: 'AFMT_VBI_GSP2_INDEX',
3: 'AFMT_VBI_GSP3_INDEX',
4: 'AFMT_VBI_GSP4_INDEX',
5: 'AFMT_VBI_GSP5_INDEX',
6: 'AFMT_VBI_GSP6_INDEX',
7: 'AFMT_VBI_GSP7_INDEX',
8: 'AFMT_VBI_GSP8_INDEX',
9: 'AFMT_VBI_GSP9_INDEX',
10: 'AFMT_VBI_GSP10_INDEX',
}
AFMT_VBI_GSP0_INDEX = 0
AFMT_VBI_GSP1_INDEX = 1
AFMT_VBI_GSP2_INDEX = 2
AFMT_VBI_GSP3_INDEX = 3
AFMT_VBI_GSP4_INDEX = 4
AFMT_VBI_GSP5_INDEX = 5
AFMT_VBI_GSP6_INDEX = 6
AFMT_VBI_GSP7_INDEX = 7
AFMT_VBI_GSP8_INDEX = 8
AFMT_VBI_GSP9_INDEX = 9
AFMT_VBI_GSP10_INDEX = 10
AFMT_VBI_GSP_INDEX = ctypes.c_uint32 # enum
# values for enumeration 'DIG_DIGITAL_BYPASS_SEL'
DIG_DIGITAL_BYPASS_SEL__enumvalues = {
0: 'DIG_DIGITAL_BYPASS_SEL_BYPASS',
1: 'DIG_DIGITAL_BYPASS_SEL_36BPP',
2: 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB',
3: 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB',
4: 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB',
5: 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB',
6: 'DIG_DIGITAL_BYPASS_SEL_ALPHA',
}
DIG_DIGITAL_BYPASS_SEL_BYPASS = 0
DIG_DIGITAL_BYPASS_SEL_36BPP = 1
DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 2
DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 3
DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 4
DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 5
DIG_DIGITAL_BYPASS_SEL_ALPHA = 6
DIG_DIGITAL_BYPASS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_INPUT_PIXEL_SEL'
DIG_INPUT_PIXEL_SEL__enumvalues = {
0: 'DIG_ALL_PIXEL',
1: 'DIG_EVEN_PIXEL_ONLY',
2: 'DIG_ODD_PIXEL_ONLY',
}
DIG_ALL_PIXEL = 0
DIG_EVEN_PIXEL_ONLY = 1
DIG_ODD_PIXEL_ONLY = 2
DIG_INPUT_PIXEL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DOLBY_VISION_ENABLE'
DOLBY_VISION_ENABLE__enumvalues = {
0: 'DOLBY_VISION_ENABLED',
1: 'DOLBY_VISION_DISABLED',
}
DOLBY_VISION_ENABLED = 0
DOLBY_VISION_DISABLED = 1
DOLBY_VISION_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'METADATA_HUBP_SEL'
METADATA_HUBP_SEL__enumvalues = {
0: 'METADATA_HUBP_SEL_0',
1: 'METADATA_HUBP_SEL_1',
2: 'METADATA_HUBP_SEL_2',
3: 'METADATA_HUBP_SEL_3',
4: 'METADATA_HUBP_SEL_4',
5: 'METADATA_HUBP_SEL_5',
6: 'METADATA_HUBP_SEL_RESERVED',
}
METADATA_HUBP_SEL_0 = 0
METADATA_HUBP_SEL_1 = 1
METADATA_HUBP_SEL_2 = 2
METADATA_HUBP_SEL_3 = 3
METADATA_HUBP_SEL_4 = 4
METADATA_HUBP_SEL_5 = 5
METADATA_HUBP_SEL_RESERVED = 6
METADATA_HUBP_SEL = ctypes.c_uint32 # enum
# values for enumeration 'METADATA_STREAM_TYPE_SEL'
METADATA_STREAM_TYPE_SEL__enumvalues = {
0: 'METADATA_STREAM_DP',
1: 'METADATA_STREAM_DVE',
}
METADATA_STREAM_DP = 0
METADATA_STREAM_DVE = 1
METADATA_STREAM_TYPE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_METADATA_ENABLE'
HDMI_METADATA_ENABLE__enumvalues = {
0: 'HDMI_METADATA_NOT_SEND',
1: 'HDMI_METADATA_PKT_SEND',
}
HDMI_METADATA_NOT_SEND = 0
HDMI_METADATA_PKT_SEND = 1
HDMI_METADATA_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_PACKET_LINE_REFERENCE'
HDMI_PACKET_LINE_REFERENCE__enumvalues = {
0: 'HDMI_PKT_LINE_REF_VSYNC',
1: 'HDMI_PKT_LINE_REF_OTGSOF',
}
HDMI_PKT_LINE_REF_VSYNC = 0
HDMI_PKT_LINE_REF_OTGSOF = 1
HDMI_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_CONTROL_HPD_SEL'
DP_AUX_CONTROL_HPD_SEL__enumvalues = {
0: 'DP_AUX_CONTROL_HPD1_SELECTED',
1: 'DP_AUX_CONTROL_HPD2_SELECTED',
2: 'DP_AUX_CONTROL_HPD3_SELECTED',
3: 'DP_AUX_CONTROL_HPD4_SELECTED',
4: 'DP_AUX_CONTROL_HPD5_SELECTED',
5: 'DP_AUX_CONTROL_HPD6_SELECTED',
6: 'DP_AUX_CONTROL_NO_HPD_SELECTED',
}
DP_AUX_CONTROL_HPD1_SELECTED = 0
DP_AUX_CONTROL_HPD2_SELECTED = 1
DP_AUX_CONTROL_HPD3_SELECTED = 2
DP_AUX_CONTROL_HPD4_SELECTED = 3
DP_AUX_CONTROL_HPD5_SELECTED = 4
DP_AUX_CONTROL_HPD6_SELECTED = 5
DP_AUX_CONTROL_NO_HPD_SELECTED = 6
DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_CONTROL_TEST_MODE'
DP_AUX_CONTROL_TEST_MODE__enumvalues = {
0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE',
1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE',
}
DP_AUX_CONTROL_TEST_MODE_DISABLE = 0
DP_AUX_CONTROL_TEST_MODE_ENABLE = 1
DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO'
DP_AUX_SW_CONTROL_SW_GO__enumvalues = {
0: 'DP_AUX_SW_CONTROL_SW__NOT_GO',
1: 'DP_AUX_SW_CONTROL_SW__GO',
}
DP_AUX_SW_CONTROL_SW__NOT_GO = 0
DP_AUX_SW_CONTROL_SW__GO = 1
DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG'
DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = {
0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG',
1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG',
}
DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0
DP_AUX_SW_CONTROL_LS_READ__TRIG = 1
DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY'
DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = {
0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW',
1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW',
2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC',
3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS',
}
DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0
DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1
DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2
DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3
DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ'
DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = {
0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ',
1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ',
}
DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0
DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1
DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG'
DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = {
0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG',
1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG',
}
DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0
DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1
DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_INT_ACK'
DP_AUX_INT_ACK__enumvalues = {
0: 'DP_AUX_INT__NOT_ACK',
1: 'DP_AUX_INT__ACK',
}
DP_AUX_INT__NOT_ACK = 0
DP_AUX_INT__ACK = 1
DP_AUX_INT_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_LS_UPDATE_ACK'
DP_AUX_LS_UPDATE_ACK__enumvalues = {
0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK',
1: 'DP_AUX_INT_LS_UPDATE_ACK',
}
DP_AUX_INT_LS_UPDATE_NOT_ACK = 0
DP_AUX_INT_LS_UPDATE_ACK = 1
DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL'
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = {
0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK',
1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF',
}
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE'
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = {
0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ',
1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ',
2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ',
3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ',
}
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY'
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = {
0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0',
1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US',
2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US',
3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US',
4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US',
5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US',
}
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW'
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD',
1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD',
2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD',
3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD',
4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD',
5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD',
6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD',
7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD',
}
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7
DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW'
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD',
1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD',
2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD',
3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD',
4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD',
5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD',
6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD',
7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD',
}
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN'
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES',
1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES',
2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES',
3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED',
}
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT'
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
}
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START'
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START',
1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START',
}
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP'
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP',
1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP',
}
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN'
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS',
1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS',
2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS',
3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS',
}
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_RX_TIMEOUT_LEN_MUL'
DP_AUX_RX_TIMEOUT_LEN_MUL__enumvalues = {
0: 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL',
1: 'DP_AUX_RX_TIMEOUT_LEN_MUL_2',
2: 'DP_AUX_RX_TIMEOUT_LEN_MUL_4',
3: 'DP_AUX_RX_TIMEOUT_LEN_MUL_8',
}
DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0
DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 1
DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 2
DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 3
DP_AUX_RX_TIMEOUT_LEN_MUL = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_TX_PRECHARGE_LEN_MUL'
DP_AUX_TX_PRECHARGE_LEN_MUL__enumvalues = {
0: 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL',
1: 'DP_AUX_TX_PRECHARGE_LEN_MUL_2',
2: 'DP_AUX_TX_PRECHARGE_LEN_MUL_4',
3: 'DP_AUX_TX_PRECHARGE_LEN_MUL_8',
}
DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0
DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 1
DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 2
DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 3
DP_AUX_TX_PRECHARGE_LEN_MUL = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD'
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = {
0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2',
1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4',
2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8',
3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16',
4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32',
5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64',
6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128',
7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256',
}
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7
DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ'
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = {
0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX',
1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX',
}
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW'
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = {
0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US',
1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US',
2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US',
3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US',
}
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT'
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = {
0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS',
1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS',
2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS',
3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED',
}
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN'
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = {
0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0',
1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64',
2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128',
3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256',
}
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK'
DP_AUX_ERR_OCCURRED_ACK__enumvalues = {
0: 'DP_AUX_ERR_OCCURRED__NOT_ACK',
1: 'DP_AUX_ERR_OCCURRED__ACK',
}
DP_AUX_ERR_OCCURRED__NOT_ACK = 0
DP_AUX_ERR_OCCURRED__ACK = 1
DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK'
DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = {
0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK',
1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK',
}
DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0
DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1
DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK'
DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = {
0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK',
1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK',
}
ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0
ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1
DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_RESET'
DP_AUX_RESET__enumvalues = {
0: 'DP_AUX_RESET_DEASSERTED',
1: 'DP_AUX_RESET_ASSERTED',
}
DP_AUX_RESET_DEASSERTED = 0
DP_AUX_RESET_ASSERTED = 1
DP_AUX_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_RESET_DONE'
DP_AUX_RESET_DONE__enumvalues = {
0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE',
1: 'DP_AUX_RESET_SEQUENCE_DONE',
}
DP_AUX_RESET_SEQUENCE_NOT_DONE = 0
DP_AUX_RESET_SEQUENCE_DONE = 1
DP_AUX_RESET_DONE = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_PHY_WAKE_PRIORITY'
DP_AUX_PHY_WAKE_PRIORITY__enumvalues = {
0: 'DP_AUX_PHY_WAKE_HIGH_PRIORITY',
1: 'DP_AUX_PHY_WAKE_LOW_PRIORITY',
}
DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0
DP_AUX_PHY_WAKE_LOW_PRIORITY = 1
DP_AUX_PHY_WAKE_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_GO'
DOUT_I2C_CONTROL_GO__enumvalues = {
0: 'DOUT_I2C_CONTROL_STOP_TRANSFER',
1: 'DOUT_I2C_CONTROL_START_TRANSFER',
}
DOUT_I2C_CONTROL_STOP_TRANSFER = 0
DOUT_I2C_CONTROL_START_TRANSFER = 1
DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET'
DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = {
0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER',
1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER',
}
DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0
DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1
DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET'
DOUT_I2C_CONTROL_SEND_RESET__enumvalues = {
0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET',
1: 'DOUT_I2C_CONTROL__SEND_RESET',
}
DOUT_I2C_CONTROL__NOT_SEND_RESET = 0
DOUT_I2C_CONTROL__SEND_RESET = 1
DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH'
DOUT_I2C_CONTROL_SEND_RESET_LENGTH__enumvalues = {
0: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9',
1: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10',
}
DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0
DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 1
DOUT_I2C_CONTROL_SEND_RESET_LENGTH = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET'
DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = {
0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS',
1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS',
}
DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0
DOUT_I2C_CONTROL_RESET_SW_STATUS = 1
DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT'
DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = {
0: 'DOUT_I2C_CONTROL_SELECT_DDC1',
1: 'DOUT_I2C_CONTROL_SELECT_DDC2',
2: 'DOUT_I2C_CONTROL_SELECT_DDC3',
3: 'DOUT_I2C_CONTROL_SELECT_DDC4',
4: 'DOUT_I2C_CONTROL_SELECT_DDC5',
5: 'DOUT_I2C_CONTROL_SELECT_DDC6',
6: 'DOUT_I2C_CONTROL_SELECT_DDCVGA',
}
DOUT_I2C_CONTROL_SELECT_DDC1 = 0
DOUT_I2C_CONTROL_SELECT_DDC2 = 1
DOUT_I2C_CONTROL_SELECT_DDC3 = 2
DOUT_I2C_CONTROL_SELECT_DDC4 = 3
DOUT_I2C_CONTROL_SELECT_DDC5 = 4
DOUT_I2C_CONTROL_SELECT_DDC6 = 5
DOUT_I2C_CONTROL_SELECT_DDCVGA = 6
DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT'
DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = {
0: 'DOUT_I2C_CONTROL_TRANS0',
1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1',
2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2',
3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3',
}
DOUT_I2C_CONTROL_TRANS0 = 0
DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1
DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2
DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3
DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY'
DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = {
0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL',
1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH',
2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED',
3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED',
}
DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0
DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1
DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2
DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3
DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO'
DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = {
0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED',
1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED',
}
DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0
DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1
DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER'
DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = {
0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER',
1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER',
}
DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0
DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1
DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ'
DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = {
0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ',
1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ',
}
DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0
DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1
DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG'
DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = {
0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG',
1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG',
}
DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0
DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1
DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ACK'
DOUT_I2C_ACK__enumvalues = {
0: 'DOUT_I2C_NO_ACK',
1: 'DOUT_I2C_ACK_TO_CLEAN',
}
DOUT_I2C_NO_ACK = 0
DOUT_I2C_ACK_TO_CLEAN = 1
DOUT_I2C_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD'
DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = {
0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO',
1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE',
2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE',
3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE',
}
DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0
DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1
DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2
DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3
DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN'
DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = {
0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR',
1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA',
}
DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0
DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1
DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL'
DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = {
0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS',
1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS',
}
DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0
DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1
DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE'
DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = {
0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT',
1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT',
}
DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0
DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1
DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_EDID_DETECT_STATUS'
DOUT_I2C_DDC_EDID_DETECT_STATUS__enumvalues = {
0: 'DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED',
1: 'DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED',
}
DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED = 0
DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED = 1
DOUT_I2C_DDC_EDID_DETECT_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN'
DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = {
0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR',
1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL',
}
DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0
DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1
DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK'
DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = {
0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS',
1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS',
}
DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0
DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1
DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE'
DOUT_I2C_DATA_INDEX_WRITE__enumvalues = {
0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE',
1: 'DOUT_I2C_DATA__INDEX_WRITE',
}
DOUT_I2C_DATA__NOT_INDEX_WRITE = 0
DOUT_I2C_DATA__INDEX_WRITE = 1
DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET'
DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = {
0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION',
1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION',
}
DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0
DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1
DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE'
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = {
0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL',
1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE',
}
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_FORCE_CTRL'
DIOMEM_PWR_FORCE_CTRL__enumvalues = {
0: 'DIOMEM_NO_FORCE_REQUEST',
1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST',
3: 'DIOMEM_FORCE_SHUT_DOWN_REQUEST',
}
DIOMEM_NO_FORCE_REQUEST = 0
DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 1
DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 2
DIOMEM_FORCE_SHUT_DOWN_REQUEST = 3
DIOMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_FORCE_CTRL2'
DIOMEM_PWR_FORCE_CTRL2__enumvalues = {
0: 'DIOMEM_NO_FORCE_REQ',
1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQ',
}
DIOMEM_NO_FORCE_REQ = 0
DIOMEM_FORCE_LIGHT_SLEEP_REQ = 1
DIOMEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_DIS_CTRL'
DIOMEM_PWR_DIS_CTRL__enumvalues = {
0: 'DIOMEM_ENABLE_MEM_PWR_CTRL',
1: 'DIOMEM_DISABLE_MEM_PWR_CTRL',
}
DIOMEM_ENABLE_MEM_PWR_CTRL = 0
DIOMEM_DISABLE_MEM_PWR_CTRL = 1
DIOMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'CLOCK_GATING_EN'
CLOCK_GATING_EN__enumvalues = {
0: 'CLOCK_GATING_ENABLE',
1: 'CLOCK_GATING_DISABLE',
}
CLOCK_GATING_ENABLE = 0
CLOCK_GATING_DISABLE = 1
CLOCK_GATING_EN = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_SEL_CTRL'
DIOMEM_PWR_SEL_CTRL__enumvalues = {
0: 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE',
1: 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE',
2: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE',
}
DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0
DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 1
DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 2
DIOMEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_SEL_CTRL2'
DIOMEM_PWR_SEL_CTRL2__enumvalues = {
0: 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN',
1: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN',
}
DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0
DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 1
DIOMEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum
# values for enumeration 'PM_ASSERT_RESET'
PM_ASSERT_RESET__enumvalues = {
0: 'PM_ASSERT_RESET_0',
1: 'PM_ASSERT_RESET_1',
}
PM_ASSERT_RESET_0 = 0
PM_ASSERT_RESET_1 = 1
PM_ASSERT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DAC_MUX_SELECT'
DAC_MUX_SELECT__enumvalues = {
0: 'DAC_MUX_SELECT_DACA',
1: 'DAC_MUX_SELECT_DACB',
}
DAC_MUX_SELECT_DACA = 0
DAC_MUX_SELECT_DACB = 1
DAC_MUX_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_MUX_SELECT'
TMDS_MUX_SELECT__enumvalues = {
0: 'TMDS_MUX_SELECT_B',
1: 'TMDS_MUX_SELECT_G',
2: 'TMDS_MUX_SELECT_R',
3: 'TMDS_MUX_SELECT_RESERVED',
}
TMDS_MUX_SELECT_B = 0
TMDS_MUX_SELECT_G = 1
TMDS_MUX_SELECT_R = 2
TMDS_MUX_SELECT_RESERVED = 3
TMDS_MUX_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'SOFT_RESET'
SOFT_RESET__enumvalues = {
0: 'SOFT_RESET_0',
1: 'SOFT_RESET_1',
}
SOFT_RESET_0 = 0
SOFT_RESET_1 = 1
SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_STEREOSYNC_SEL'
GENERIC_STEREOSYNC_SEL__enumvalues = {
0: 'GENERIC_STEREOSYNC_SEL_D1',
1: 'GENERIC_STEREOSYNC_SEL_D2',
2: 'GENERIC_STEREOSYNC_SEL_D3',
3: 'GENERIC_STEREOSYNC_SEL_D4',
4: 'GENERIC_STEREOSYNC_SEL_D5',
5: 'GENERIC_STEREOSYNC_SEL_D6',
6: 'GENERIC_STEREOSYNC_SEL_RESERVED',
}
GENERIC_STEREOSYNC_SEL_D1 = 0
GENERIC_STEREOSYNC_SEL_D2 = 1
GENERIC_STEREOSYNC_SEL_D3 = 2
GENERIC_STEREOSYNC_SEL_D4 = 3
GENERIC_STEREOSYNC_SEL_D5 = 4
GENERIC_STEREOSYNC_SEL_D6 = 5
GENERIC_STEREOSYNC_SEL_RESERVED = 6
GENERIC_STEREOSYNC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE'
DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = {
0: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL',
1: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE',
}
DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0
DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1
DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE'
DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE__enumvalues = {
0: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0',
1: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1',
}
DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0
DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 1
DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERICA_SEL'
DCIO_DC_GENERICA_SEL__enumvalues = {
0: 'DCIO_GENERICA_SEL_DACA_STEREOSYNC',
1: 'DCIO_GENERICA_SEL_STEREOSYNC',
2: 'DCIO_GENERICA_SEL_DACA_PIXCLK',
3: 'DCIO_GENERICA_SEL_DACB_PIXCLK',
4: 'DCIO_GENERICA_SEL_DVOA_CTL3',
5: 'DCIO_GENERICA_SEL_P1_PLLCLK',
6: 'DCIO_GENERICA_SEL_P2_PLLCLK',
7: 'DCIO_GENERICA_SEL_DVOA_STEREOSYNC',
8: 'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER',
9: 'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER',
10: 'DCIO_GENERICA_SEL_GENERICA_DCCG',
11: 'DCIO_GENERICA_SEL_SYNCEN',
12: 'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK',
13: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK',
14: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK',
15: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2',
16: 'DCIO_GENERICA_SEL_GENERICA_DPRX',
17: 'DCIO_GENERICA_SEL_GENERICB_DPRX',
}
DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0
DCIO_GENERICA_SEL_STEREOSYNC = 1
DCIO_GENERICA_SEL_DACA_PIXCLK = 2
DCIO_GENERICA_SEL_DACB_PIXCLK = 3
DCIO_GENERICA_SEL_DVOA_CTL3 = 4
DCIO_GENERICA_SEL_P1_PLLCLK = 5
DCIO_GENERICA_SEL_P2_PLLCLK = 6
DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 7
DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 8
DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 9
DCIO_GENERICA_SEL_GENERICA_DCCG = 10
DCIO_GENERICA_SEL_SYNCEN = 11
DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK = 12
DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK = 13
DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK = 14
DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15
DCIO_GENERICA_SEL_GENERICA_DPRX = 16
DCIO_GENERICA_SEL_GENERICB_DPRX = 17
DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL'
DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = {
0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK',
1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK',
2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK',
3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK',
4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK',
5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK',
6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK',
}
DCIO_UNIPHYA_TEST_REFDIV_CLK = 0
DCIO_UNIPHYB_TEST_REFDIV_CLK = 1
DCIO_UNIPHYC_TEST_REFDIV_CLK = 2
DCIO_UNIPHYD_TEST_REFDIV_CLK = 3
DCIO_UNIPHYE_TEST_REFDIV_CLK = 4
DCIO_UNIPHYF_TEST_REFDIV_CLK = 5
DCIO_UNIPHYG_TEST_REFDIV_CLK = 6
DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL'
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = {
0: 'DCIO_UNIPHYA_FBDIV_CLK',
1: 'DCIO_UNIPHYB_FBDIV_CLK',
2: 'DCIO_UNIPHYC_FBDIV_CLK',
3: 'DCIO_UNIPHYD_FBDIV_CLK',
4: 'DCIO_UNIPHYE_FBDIV_CLK',
5: 'DCIO_UNIPHYF_FBDIV_CLK',
6: 'DCIO_UNIPHYG_FBDIV_CLK',
}
DCIO_UNIPHYA_FBDIV_CLK = 0
DCIO_UNIPHYB_FBDIV_CLK = 1
DCIO_UNIPHYC_FBDIV_CLK = 2
DCIO_UNIPHYD_FBDIV_CLK = 3
DCIO_UNIPHYE_FBDIV_CLK = 4
DCIO_UNIPHYF_FBDIV_CLK = 5
DCIO_UNIPHYG_FBDIV_CLK = 6
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL'
DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = {
0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK',
1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK',
2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK',
3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK',
4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK',
5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK',
6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK',
}
DCIO_UNIPHYA_FBDIV_SSC_CLK = 0
DCIO_UNIPHYB_FBDIV_SSC_CLK = 1
DCIO_UNIPHYC_FBDIV_SSC_CLK = 2
DCIO_UNIPHYD_FBDIV_SSC_CLK = 3
DCIO_UNIPHYE_FBDIV_SSC_CLK = 4
DCIO_UNIPHYF_FBDIV_SSC_CLK = 5
DCIO_UNIPHYG_FBDIV_SSC_CLK = 6
DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL'
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = {
0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2',
1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2',
2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2',
3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2',
4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2',
5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2',
6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2',
}
DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0
DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1
DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2
DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3
DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4
DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5
DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERICB_SEL'
DCIO_DC_GENERICB_SEL__enumvalues = {
0: 'DCIO_GENERICB_SEL_DACA_STEREOSYNC',
1: 'DCIO_GENERICB_SEL_STEREOSYNC',
2: 'DCIO_GENERICB_SEL_DACA_PIXCLK',
3: 'DCIO_GENERICB_SEL_DACB_PIXCLK',
4: 'DCIO_GENERICB_SEL_DVOA_CTL3',
5: 'DCIO_GENERICB_SEL_P1_PLLCLK',
6: 'DCIO_GENERICB_SEL_P2_PLLCLK',
7: 'DCIO_GENERICB_SEL_DVOA_STEREOSYNC',
8: 'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER',
9: 'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER',
10: 'DCIO_GENERICB_SEL_GENERICB_DCCG',
11: 'DCIO_GENERICB_SEL_SYNCEN',
12: 'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK',
13: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK',
14: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK',
15: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2',
}
DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0
DCIO_GENERICB_SEL_STEREOSYNC = 1
DCIO_GENERICB_SEL_DACA_PIXCLK = 2
DCIO_GENERICB_SEL_DACB_PIXCLK = 3
DCIO_GENERICB_SEL_DVOA_CTL3 = 4
DCIO_GENERICB_SEL_P1_PLLCLK = 5
DCIO_GENERICB_SEL_P2_PLLCLK = 6
DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 7
DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 8
DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 9
DCIO_GENERICB_SEL_GENERICB_DCCG = 10
DCIO_GENERICB_SEL_SYNCEN = 11
DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK = 12
DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK = 13
DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK = 14
DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15
DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL'
DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL__enumvalues = {
0: 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE',
1: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1',
2: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2',
3: 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED',
}
DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0
DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 1
DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 2
DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 3
DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL'
DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = {
0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE',
1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1',
2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2',
3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3',
}
DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2
DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3
DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION'
DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION__enumvalues = {
0: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS',
1: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS',
2: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS',
3: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS',
4: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS',
5: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS',
6: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS',
7: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS',
}
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 1
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 2
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 3
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 4
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 5
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 6
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 7
DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT'
DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = {
0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION',
1: 'DCIO_UNIPHY_CHANNEL_INVERTED',
}
DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0
DCIO_UNIPHY_CHANNEL_INVERTED = 1
DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK'
DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = {
0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW',
1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW',
2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED',
3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED',
}
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3
DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE'
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = {
0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0',
1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1',
2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2',
3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3',
}
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN'
DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN__enumvalues = {
0: 'DCIO_VIP_MUX_EN_DVO',
1: 'DCIO_VIP_MUX_EN_VIP',
}
DCIO_VIP_MUX_EN_DVO = 0
DCIO_VIP_MUX_EN_VIP = 1
DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN'
DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN__enumvalues = {
0: 'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT',
1: 'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE',
}
DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0
DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 1
DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN'
DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN__enumvalues = {
0: 'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT',
1: 'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE',
}
DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0
DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 1
DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN'
DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN__enumvalues = {
0: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE',
1: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE',
}
DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE = 0
DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE = 1
DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE'
DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE__enumvalues = {
0: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF',
1: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON',
}
DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0
DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 1
DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL'
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL__enumvalues = {
0: 'DCIO_LVTMA_SYNCEN_POL_NON_INVERT',
1: 'DCIO_LVTMA_SYNCEN_POL_INVERT',
}
DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0
DCIO_LVTMA_SYNCEN_POL_INVERT = 1
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON'
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON__enumvalues = {
0: 'DCIO_LVTMA_DIGON_OFF',
1: 'DCIO_LVTMA_DIGON_ON',
}
DCIO_LVTMA_DIGON_OFF = 0
DCIO_LVTMA_DIGON_ON = 1
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL'
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL__enumvalues = {
0: 'DCIO_LVTMA_DIGON_POL_NON_INVERT',
1: 'DCIO_LVTMA_DIGON_POL_INVERT',
}
DCIO_LVTMA_DIGON_POL_NON_INVERT = 0
DCIO_LVTMA_DIGON_POL_INVERT = 1
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON'
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON__enumvalues = {
0: 'DCIO_LVTMA_BLON_OFF',
1: 'DCIO_LVTMA_BLON_ON',
}
DCIO_LVTMA_BLON_OFF = 0
DCIO_LVTMA_BLON_ON = 1
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL'
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL__enumvalues = {
0: 'DCIO_LVTMA_BLON_POL_NON_INVERT',
1: 'DCIO_LVTMA_BLON_POL_INVERT',
}
DCIO_LVTMA_BLON_POL_NON_INVERT = 0
DCIO_LVTMA_BLON_POL_INVERT = 1
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN'
DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN__enumvalues = {
0: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON',
1: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE',
}
DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0
DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 1
DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN'
DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = {
0: 'DCIO_BL_PWM_FRACTIONAL_DISABLE',
1: 'DCIO_BL_PWM_FRACTIONAL_ENABLE',
}
DCIO_BL_PWM_FRACTIONAL_DISABLE = 0
DCIO_BL_PWM_FRACTIONAL_ENABLE = 1
DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_EN'
DCIO_BL_PWM_CNTL_BL_PWM_EN__enumvalues = {
0: 'DCIO_BL_PWM_DISABLE',
1: 'DCIO_BL_PWM_ENABLE',
}
DCIO_BL_PWM_DISABLE = 0
DCIO_BL_PWM_ENABLE = 1
DCIO_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE'
DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = {
0: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE',
1: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE',
}
DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0
DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1
DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN'
DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__enumvalues = {
0: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL',
1: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM',
}
DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0
DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 1
DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_BL_PWM_GRP1_REG_LOCK'
DCIO_BL_PWM_GRP1_REG_LOCK__enumvalues = {
0: 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE',
1: 'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE',
}
DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0
DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 1
DCIO_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START'
DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = {
0: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE',
1: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE',
}
DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0
DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1
DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL'
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = {
0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1',
1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2',
2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3',
3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4',
4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5',
5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6',
}
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN'
DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = {
0: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM',
1: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM',
}
DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0
DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1
DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN'
DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = {
0: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE',
1: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE',
}
DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0
DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1
DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_GSL_SEL'
DCIO_GSL_SEL__enumvalues = {
0: 'DCIO_GSL_SEL_GROUP_0',
1: 'DCIO_GSL_SEL_GROUP_1',
2: 'DCIO_GSL_SEL_GROUP_2',
}
DCIO_GSL_SEL_GROUP_0 = 0
DCIO_GSL_SEL_GROUP_1 = 1
DCIO_GSL_SEL_GROUP_2 = 2
DCIO_GSL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK'
DCIO_GENLK_CLK_GSL_MASK__enumvalues = {
0: 'DCIO_GENLK_CLK_GSL_MASK_NO',
1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING',
2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO',
}
DCIO_GENLK_CLK_GSL_MASK_NO = 0
DCIO_GENLK_CLK_GSL_MASK_TIMING = 1
DCIO_GENLK_CLK_GSL_MASK_STEREO = 2
DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK'
DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = {
0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO',
1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING',
2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO',
}
DCIO_GENLK_VSYNC_GSL_MASK_NO = 0
DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1
DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2
DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK'
DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = {
0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO',
1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING',
2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO',
}
DCIO_SWAPLOCK_A_GSL_MASK_NO = 0
DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1
DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2
DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK'
DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = {
0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO',
1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING',
2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO',
}
DCIO_SWAPLOCK_B_GSL_MASK_NO = 0
DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1
DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2
DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION'
DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = {
0: 'DCIO_GPU_TIMER_START_0_END_27',
1: 'DCIO_GPU_TIMER_START_1_END_28',
2: 'DCIO_GPU_TIMER_START_2_END_29',
3: 'DCIO_GPU_TIMER_START_3_END_30',
4: 'DCIO_GPU_TIMER_START_4_END_31',
5: 'DCIO_GPU_TIMER_START_6_END_33',
6: 'DCIO_GPU_TIMER_START_8_END_35',
7: 'DCIO_GPU_TIMER_START_10_END_37',
}
DCIO_GPU_TIMER_START_0_END_27 = 0
DCIO_GPU_TIMER_START_1_END_28 = 1
DCIO_GPU_TIMER_START_2_END_29 = 2
DCIO_GPU_TIMER_START_3_END_30 = 3
DCIO_GPU_TIMER_START_4_END_31 = 4
DCIO_GPU_TIMER_START_6_END_33 = 5
DCIO_GPU_TIMER_START_8_END_35 = 6
DCIO_GPU_TIMER_START_10_END_37 = 7
DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL'
DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = {
0: 'DCIO_TEST_CLK_SEL_DISPCLK',
1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK',
2: 'DCIO_TEST_CLK_SEL_SOCCLK',
}
DCIO_TEST_CLK_SEL_DISPCLK = 0
DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1
DCIO_TEST_CLK_SEL_SOCCLK = 2
DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS'
DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = {
0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE',
1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE',
}
DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0
DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1
DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DIO_OTG_EXT_VSYNC_MUX'
DCIO_DIO_OTG_EXT_VSYNC_MUX__enumvalues = {
0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB',
1: 'DCIO_EXT_VSYNC_MUX_OTG0',
2: 'DCIO_EXT_VSYNC_MUX_OTG1',
3: 'DCIO_EXT_VSYNC_MUX_OTG2',
4: 'DCIO_EXT_VSYNC_MUX_OTG3',
5: 'DCIO_EXT_VSYNC_MUX_OTG4',
6: 'DCIO_EXT_VSYNC_MUX_OTG5',
7: 'DCIO_EXT_VSYNC_MUX_GENERICB',
}
DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0
DCIO_EXT_VSYNC_MUX_OTG0 = 1
DCIO_EXT_VSYNC_MUX_OTG1 = 2
DCIO_EXT_VSYNC_MUX_OTG2 = 3
DCIO_EXT_VSYNC_MUX_OTG3 = 4
DCIO_EXT_VSYNC_MUX_OTG4 = 5
DCIO_EXT_VSYNC_MUX_OTG5 = 6
DCIO_EXT_VSYNC_MUX_GENERICB = 7
DCIO_DIO_OTG_EXT_VSYNC_MUX = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DIO_EXT_VSYNC_MASK'
DCIO_DIO_EXT_VSYNC_MASK__enumvalues = {
0: 'DCIO_EXT_VSYNC_MASK_NONE',
1: 'DCIO_EXT_VSYNC_MASK_PIPE0',
2: 'DCIO_EXT_VSYNC_MASK_PIPE1',
3: 'DCIO_EXT_VSYNC_MASK_PIPE2',
4: 'DCIO_EXT_VSYNC_MASK_PIPE3',
5: 'DCIO_EXT_VSYNC_MASK_PIPE4',
6: 'DCIO_EXT_VSYNC_MASK_PIPE5',
7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE',
}
DCIO_EXT_VSYNC_MASK_NONE = 0
DCIO_EXT_VSYNC_MASK_PIPE0 = 1
DCIO_EXT_VSYNC_MASK_PIPE1 = 2
DCIO_EXT_VSYNC_MASK_PIPE2 = 3
DCIO_EXT_VSYNC_MASK_PIPE3 = 4
DCIO_EXT_VSYNC_MASK_PIPE4 = 5
DCIO_EXT_VSYNC_MASK_PIPE5 = 6
DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7
DCIO_DIO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DSYNC_SOFT_RESET'
DCIO_DSYNC_SOFT_RESET__enumvalues = {
0: 'DCIO_DSYNC_SOFT_RESET_DEASSERT',
1: 'DCIO_DSYNC_SOFT_RESET_ASSERT',
}
DCIO_DSYNC_SOFT_RESET_DEASSERT = 0
DCIO_DSYNC_SOFT_RESET_ASSERT = 1
DCIO_DSYNC_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DACA_SOFT_RESET'
DCIO_DACA_SOFT_RESET__enumvalues = {
0: 'DCIO_DACA_SOFT_RESET_DEASSERT',
1: 'DCIO_DACA_SOFT_RESET_ASSERT',
}
DCIO_DACA_SOFT_RESET_DEASSERT = 0
DCIO_DACA_SOFT_RESET_ASSERT = 1
DCIO_DACA_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET'
DCIO_DCRXPHY_SOFT_RESET__enumvalues = {
0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT',
1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT',
}
DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0
DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1
DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DPHY_LANE_SEL'
DCIO_DPHY_LANE_SEL__enumvalues = {
0: 'DCIO_DPHY_LANE_SEL_LANE0',
1: 'DCIO_DPHY_LANE_SEL_LANE1',
2: 'DCIO_DPHY_LANE_SEL_LANE2',
3: 'DCIO_DPHY_LANE_SEL_LANE3',
}
DCIO_DPHY_LANE_SEL_LANE0 = 0
DCIO_DPHY_LANE_SEL_LANE1 = 1
DCIO_DPHY_LANE_SEL_LANE2 = 2
DCIO_DPHY_LANE_SEL_LANE3 = 3
DCIO_DPHY_LANE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE'
DCIO_DPCS_INTERRUPT_TYPE__enumvalues = {
0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED',
1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED',
}
DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0
DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1
DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK'
DCIO_DPCS_INTERRUPT_MASK__enumvalues = {
0: 'DCIO_DPCS_INTERRUPT_DISABLE',
1: 'DCIO_DPCS_INTERRUPT_ENABLE',
}
DCIO_DPCS_INTERRUPT_DISABLE = 0
DCIO_DPCS_INTERRUPT_ENABLE = 1
DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT'
DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = {
0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE',
1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE',
2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP',
3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP',
4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM',
5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM',
}
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 2
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 3
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 4
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 5
DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_IMPCAL_STEP_DELAY'
DCIO_IMPCAL_STEP_DELAY__enumvalues = {
0: 'DCIO_IMPCAL_STEP_DELAY_1us',
1: 'DCIO_IMPCAL_STEP_DELAY_2us',
2: 'DCIO_IMPCAL_STEP_DELAY_3us',
3: 'DCIO_IMPCAL_STEP_DELAY_4us',
4: 'DCIO_IMPCAL_STEP_DELAY_5us',
5: 'DCIO_IMPCAL_STEP_DELAY_6us',
6: 'DCIO_IMPCAL_STEP_DELAY_7us',
7: 'DCIO_IMPCAL_STEP_DELAY_8us',
8: 'DCIO_IMPCAL_STEP_DELAY_9us',
9: 'DCIO_IMPCAL_STEP_DELAY_10us',
10: 'DCIO_IMPCAL_STEP_DELAY_11us',
11: 'DCIO_IMPCAL_STEP_DELAY_12us',
12: 'DCIO_IMPCAL_STEP_DELAY_13us',
13: 'DCIO_IMPCAL_STEP_DELAY_14us',
14: 'DCIO_IMPCAL_STEP_DELAY_15us',
15: 'DCIO_IMPCAL_STEP_DELAY_16us',
}
DCIO_IMPCAL_STEP_DELAY_1us = 0
DCIO_IMPCAL_STEP_DELAY_2us = 1
DCIO_IMPCAL_STEP_DELAY_3us = 2
DCIO_IMPCAL_STEP_DELAY_4us = 3
DCIO_IMPCAL_STEP_DELAY_5us = 4
DCIO_IMPCAL_STEP_DELAY_6us = 5
DCIO_IMPCAL_STEP_DELAY_7us = 6
DCIO_IMPCAL_STEP_DELAY_8us = 7
DCIO_IMPCAL_STEP_DELAY_9us = 8
DCIO_IMPCAL_STEP_DELAY_10us = 9
DCIO_IMPCAL_STEP_DELAY_11us = 10
DCIO_IMPCAL_STEP_DELAY_12us = 11
DCIO_IMPCAL_STEP_DELAY_13us = 12
DCIO_IMPCAL_STEP_DELAY_14us = 13
DCIO_IMPCAL_STEP_DELAY_15us = 14
DCIO_IMPCAL_STEP_DELAY_16us = 15
DCIO_IMPCAL_STEP_DELAY = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL'
DCIO_UNIPHY_IMPCAL_SEL__enumvalues = {
0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE',
1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY',
}
DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0
DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1
DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_HPD_SEL'
DCIOCHIP_HPD_SEL__enumvalues = {
0: 'DCIOCHIP_HPD_SEL_ASYNC',
1: 'DCIOCHIP_HPD_SEL_CLOCKED',
}
DCIOCHIP_HPD_SEL_ASYNC = 0
DCIOCHIP_HPD_SEL_CLOCKED = 1
DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_PAD_MODE'
DCIOCHIP_PAD_MODE__enumvalues = {
0: 'DCIOCHIP_PAD_MODE_DDC',
1: 'DCIOCHIP_PAD_MODE_DP',
}
DCIOCHIP_PAD_MODE_DDC = 0
DCIOCHIP_PAD_MODE_DP = 1
DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUXSLAVE_PAD_MODE'
DCIOCHIP_AUXSLAVE_PAD_MODE__enumvalues = {
0: 'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C',
1: 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX',
}
DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0
DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 1
DCIOCHIP_AUXSLAVE_PAD_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_INVERT'
DCIOCHIP_INVERT__enumvalues = {
0: 'DCIOCHIP_POL_NON_INVERT',
1: 'DCIOCHIP_POL_INVERT',
}
DCIOCHIP_POL_NON_INVERT = 0
DCIOCHIP_POL_INVERT = 1
DCIOCHIP_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_PD_EN'
DCIOCHIP_PD_EN__enumvalues = {
0: 'DCIOCHIP_PD_EN_NOTALLOW',
1: 'DCIOCHIP_PD_EN_ALLOW',
}
DCIOCHIP_PD_EN_NOTALLOW = 0
DCIOCHIP_PD_EN_ALLOW = 1
DCIOCHIP_PD_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_GPIO_MASK_EN'
DCIOCHIP_GPIO_MASK_EN__enumvalues = {
0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE',
1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE',
}
DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0
DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1
DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_MASK'
DCIOCHIP_MASK__enumvalues = {
0: 'DCIOCHIP_MASK_DISABLE',
1: 'DCIOCHIP_MASK_ENABLE',
}
DCIOCHIP_MASK_DISABLE = 0
DCIOCHIP_MASK_ENABLE = 1
DCIOCHIP_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_GPIO_I2C_MASK'
DCIOCHIP_GPIO_I2C_MASK__enumvalues = {
0: 'DCIOCHIP_GPIO_I2C_MASK_DISABLE',
1: 'DCIOCHIP_GPIO_I2C_MASK_ENABLE',
}
DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0
DCIOCHIP_GPIO_I2C_MASK_ENABLE = 1
DCIOCHIP_GPIO_I2C_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_GPIO_I2C_DRIVE'
DCIOCHIP_GPIO_I2C_DRIVE__enumvalues = {
0: 'DCIOCHIP_GPIO_I2C_DRIVE_LOW',
1: 'DCIOCHIP_GPIO_I2C_DRIVE_HIGH',
}
DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0
DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 1
DCIOCHIP_GPIO_I2C_DRIVE = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_GPIO_I2C_EN'
DCIOCHIP_GPIO_I2C_EN__enumvalues = {
0: 'DCIOCHIP_GPIO_I2C_DISABLE',
1: 'DCIOCHIP_GPIO_I2C_ENABLE',
}
DCIOCHIP_GPIO_I2C_DISABLE = 0
DCIOCHIP_GPIO_I2C_ENABLE = 1
DCIOCHIP_GPIO_I2C_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_MASK_4BIT'
DCIOCHIP_MASK_4BIT__enumvalues = {
0: 'DCIOCHIP_MASK_4BIT_DISABLE',
15: 'DCIOCHIP_MASK_4BIT_ENABLE',
}
DCIOCHIP_MASK_4BIT_DISABLE = 0
DCIOCHIP_MASK_4BIT_ENABLE = 15
DCIOCHIP_MASK_4BIT = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_ENABLE_4BIT'
DCIOCHIP_ENABLE_4BIT__enumvalues = {
0: 'DCIOCHIP_4BIT_DISABLE',
15: 'DCIOCHIP_4BIT_ENABLE',
}
DCIOCHIP_4BIT_DISABLE = 0
DCIOCHIP_4BIT_ENABLE = 15
DCIOCHIP_ENABLE_4BIT = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_MASK_5BIT'
DCIOCHIP_MASK_5BIT__enumvalues = {
0: 'DCIOCHIP_MASIK_5BIT_DISABLE',
31: 'DCIOCHIP_MASIK_5BIT_ENABLE',
}
DCIOCHIP_MASIK_5BIT_DISABLE = 0
DCIOCHIP_MASIK_5BIT_ENABLE = 31
DCIOCHIP_MASK_5BIT = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_ENABLE_5BIT'
DCIOCHIP_ENABLE_5BIT__enumvalues = {
0: 'DCIOCHIP_5BIT_DISABLE',
31: 'DCIOCHIP_5BIT_ENABLE',
}
DCIOCHIP_5BIT_DISABLE = 0
DCIOCHIP_5BIT_ENABLE = 31
DCIOCHIP_ENABLE_5BIT = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_MASK_2BIT'
DCIOCHIP_MASK_2BIT__enumvalues = {
0: 'DCIOCHIP_MASK_2BIT_DISABLE',
3: 'DCIOCHIP_MASK_2BIT_ENABLE',
}
DCIOCHIP_MASK_2BIT_DISABLE = 0
DCIOCHIP_MASK_2BIT_ENABLE = 3
DCIOCHIP_MASK_2BIT = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_ENABLE_2BIT'
DCIOCHIP_ENABLE_2BIT__enumvalues = {
0: 'DCIOCHIP_2BIT_DISABLE',
3: 'DCIOCHIP_2BIT_ENABLE',
}
DCIOCHIP_2BIT_DISABLE = 0
DCIOCHIP_2BIT_ENABLE = 3
DCIOCHIP_ENABLE_2BIT = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL'
DCIOCHIP_REF_27_SRC_SEL__enumvalues = {
0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER',
1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER',
2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS',
3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS',
}
DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1
DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3
DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_DVO_VREFPON'
DCIOCHIP_DVO_VREFPON__enumvalues = {
0: 'DCIOCHIP_DVO_VREFPON_DISABLE',
1: 'DCIOCHIP_DVO_VREFPON_ENABLE',
}
DCIOCHIP_DVO_VREFPON_DISABLE = 0
DCIOCHIP_DVO_VREFPON_ENABLE = 1
DCIOCHIP_DVO_VREFPON = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_DVO_VREFSEL'
DCIOCHIP_DVO_VREFSEL__enumvalues = {
0: 'DCIOCHIP_DVO_VREFSEL_ONCHIP',
1: 'DCIOCHIP_DVO_VREFSEL_EXTERNAL',
}
DCIOCHIP_DVO_VREFSEL_ONCHIP = 0
DCIOCHIP_DVO_VREFSEL_EXTERNAL = 1
DCIOCHIP_DVO_VREFSEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_SPDIF1_IMODE'
DCIOCHIP_SPDIF1_IMODE__enumvalues = {
0: 'DCIOCHIP_SPDIF1_IMODE_OE_A',
1: 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO',
}
DCIOCHIP_SPDIF1_IMODE_OE_A = 0
DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 1
DCIOCHIP_SPDIF1_IMODE = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL'
DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = {
0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW',
1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0',
2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1',
3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH',
}
DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0
DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1
DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2
DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3
DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_I2C_FALLSLEWSEL'
DCIOCHIP_I2C_FALLSLEWSEL__enumvalues = {
0: 'DCIOCHIP_I2C_FALLSLEWSEL_00',
1: 'DCIOCHIP_I2C_FALLSLEWSEL_01',
2: 'DCIOCHIP_I2C_FALLSLEWSEL_10',
3: 'DCIOCHIP_I2C_FALLSLEWSEL_11',
}
DCIOCHIP_I2C_FALLSLEWSEL_00 = 0
DCIOCHIP_I2C_FALLSLEWSEL_01 = 1
DCIOCHIP_I2C_FALLSLEWSEL_10 = 2
DCIOCHIP_I2C_FALLSLEWSEL_11 = 3
DCIOCHIP_I2C_FALLSLEWSEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_SPIKESEL'
DCIOCHIP_AUX_SPIKESEL__enumvalues = {
0: 'DCIOCHIP_AUX_SPIKESEL_50NS',
1: 'DCIOCHIP_AUX_SPIKESEL_10NS',
}
DCIOCHIP_AUX_SPIKESEL_50NS = 0
DCIOCHIP_AUX_SPIKESEL_10NS = 1
DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_CSEL0P9'
DCIOCHIP_AUX_CSEL0P9__enumvalues = {
0: 'DCIOCHIP_AUX_CSEL_DEC1P0',
1: 'DCIOCHIP_AUX_CSEL_DEC0P9',
}
DCIOCHIP_AUX_CSEL_DEC1P0 = 0
DCIOCHIP_AUX_CSEL_DEC0P9 = 1
DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_CSEL1P1'
DCIOCHIP_AUX_CSEL1P1__enumvalues = {
0: 'DCIOCHIP_AUX_CSEL_INC1P0',
1: 'DCIOCHIP_AUX_CSEL_INC1P1',
}
DCIOCHIP_AUX_CSEL_INC1P0 = 0
DCIOCHIP_AUX_CSEL_INC1P1 = 1
DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_RSEL0P9'
DCIOCHIP_AUX_RSEL0P9__enumvalues = {
0: 'DCIOCHIP_AUX_RSEL_DEC1P0',
1: 'DCIOCHIP_AUX_RSEL_DEC0P9',
}
DCIOCHIP_AUX_RSEL_DEC1P0 = 0
DCIOCHIP_AUX_RSEL_DEC0P9 = 1
DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_RSEL1P1'
DCIOCHIP_AUX_RSEL1P1__enumvalues = {
0: 'DCIOCHIP_AUX_RSEL_INC1P0',
1: 'DCIOCHIP_AUX_RSEL_INC1P1',
}
DCIOCHIP_AUX_RSEL_INC1P0 = 0
DCIOCHIP_AUX_RSEL_INC1P1 = 1
DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_HYS_TUNE'
DCIOCHIP_AUX_HYS_TUNE__enumvalues = {
0: 'DCIOCHIP_AUX_HYS_TUNE_0',
1: 'DCIOCHIP_AUX_HYS_TUNE_1',
2: 'DCIOCHIP_AUX_HYS_TUNE_2',
3: 'DCIOCHIP_AUX_HYS_TUNE_3',
}
DCIOCHIP_AUX_HYS_TUNE_0 = 0
DCIOCHIP_AUX_HYS_TUNE_1 = 1
DCIOCHIP_AUX_HYS_TUNE_2 = 2
DCIOCHIP_AUX_HYS_TUNE_3 = 3
DCIOCHIP_AUX_HYS_TUNE = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_VOD_TUNE'
DCIOCHIP_AUX_VOD_TUNE__enumvalues = {
0: 'DCIOCHIP_AUX_VOD_TUNE_0',
1: 'DCIOCHIP_AUX_VOD_TUNE_1',
2: 'DCIOCHIP_AUX_VOD_TUNE_2',
3: 'DCIOCHIP_AUX_VOD_TUNE_3',
}
DCIOCHIP_AUX_VOD_TUNE_0 = 0
DCIOCHIP_AUX_VOD_TUNE_1 = 1
DCIOCHIP_AUX_VOD_TUNE_2 = 2
DCIOCHIP_AUX_VOD_TUNE_3 = 3
DCIOCHIP_AUX_VOD_TUNE = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_I2C_VPH_1V2_EN'
DCIOCHIP_I2C_VPH_1V2_EN__enumvalues = {
0: 'DCIOCHIP_I2C_VPH_1V2_EN_0',
1: 'DCIOCHIP_I2C_VPH_1V2_EN_1',
}
DCIOCHIP_I2C_VPH_1V2_EN_0 = 0
DCIOCHIP_I2C_VPH_1V2_EN_1 = 1
DCIOCHIP_I2C_VPH_1V2_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_I2C_COMPSEL'
DCIOCHIP_I2C_COMPSEL__enumvalues = {
0: 'DCIOCHIP_I2C_REC_SCHMIT',
1: 'DCIOCHIP_I2C_REC_COMPARATOR',
}
DCIOCHIP_I2C_REC_SCHMIT = 0
DCIOCHIP_I2C_REC_COMPARATOR = 1
DCIOCHIP_I2C_COMPSEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_ALL_PWR_OK'
DCIOCHIP_AUX_ALL_PWR_OK__enumvalues = {
0: 'DCIOCHIP_AUX_ALL_PWR_OK_0',
1: 'DCIOCHIP_AUX_ALL_PWR_OK_1',
}
DCIOCHIP_AUX_ALL_PWR_OK_0 = 0
DCIOCHIP_AUX_ALL_PWR_OK_1 = 1
DCIOCHIP_AUX_ALL_PWR_OK = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_I2C_RECEIVER_SEL'
DCIOCHIP_I2C_RECEIVER_SEL__enumvalues = {
0: 'DCIOCHIP_I2C_RECEIVER_SEL_0',
1: 'DCIOCHIP_I2C_RECEIVER_SEL_1',
2: 'DCIOCHIP_I2C_RECEIVER_SEL_2',
3: 'DCIOCHIP_I2C_RECEIVER_SEL_3',
}
DCIOCHIP_I2C_RECEIVER_SEL_0 = 0
DCIOCHIP_I2C_RECEIVER_SEL_1 = 1
DCIOCHIP_I2C_RECEIVER_SEL_2 = 2
DCIOCHIP_I2C_RECEIVER_SEL_3 = 3
DCIOCHIP_I2C_RECEIVER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_RECEIVER_SEL'
DCIOCHIP_AUX_RECEIVER_SEL__enumvalues = {
0: 'DCIOCHIP_AUX_RECEIVER_SEL_0',
1: 'DCIOCHIP_AUX_RECEIVER_SEL_1',
2: 'DCIOCHIP_AUX_RECEIVER_SEL_2',
3: 'DCIOCHIP_AUX_RECEIVER_SEL_3',
}
DCIOCHIP_AUX_RECEIVER_SEL_0 = 0
DCIOCHIP_AUX_RECEIVER_SEL_1 = 1
DCIOCHIP_AUX_RECEIVER_SEL_2 = 2
DCIOCHIP_AUX_RECEIVER_SEL_3 = 3
DCIOCHIP_AUX_RECEIVER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL'
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = {
0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE',
1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE',
}
GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED'
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = {
0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED',
1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED',
}
GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS'
GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = {
0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET',
1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET',
}
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1
GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED'
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = {
0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED',
1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED',
}
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum
# values for enumeration 'AZ_GLOBAL_CAPABILITIES'
AZ_GLOBAL_CAPABILITIES__enumvalues = {
0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED',
1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED',
}
AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0
AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1
AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum
# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE'
GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = {
0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE',
1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE',
}
ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0
ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1
GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum
# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL'
GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = {
0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED',
1: 'FLUSH_CONTROL_FLUSH_STARTED',
}
FLUSH_CONTROL_FLUSH_NOT_STARTED = 0
FLUSH_CONTROL_FLUSH_STARTED = 1
GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET'
GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = {
0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET',
1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET',
}
CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0
CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1
GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum
# values for enumeration 'AZ_STATE_CHANGE_STATUS'
AZ_STATE_CHANGE_STATUS__enumvalues = {
0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT',
1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT',
}
AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0
AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1
AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS'
GLOBAL_STATUS_FLUSH_STATUS__enumvalues = {
0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED',
1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED',
}
GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0
GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1
GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_0_SYNCHRONIZATION'
STREAM_0_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_1_SYNCHRONIZATION'
STREAM_1_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_2_SYNCHRONIZATION'
STREAM_2_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_3_SYNCHRONIZATION'
STREAM_3_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_4_SYNCHRONIZATION'
STREAM_4_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_5_SYNCHRONIZATION'
STREAM_5_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_6_SYNCHRONIZATION'
STREAM_6_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_7_SYNCHRONIZATION'
STREAM_7_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_8_SYNCHRONIZATION'
STREAM_8_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_9_SYNCHRONIZATION'
STREAM_9_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_10_SYNCHRONIZATION'
STREAM_10_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_11_SYNCHRONIZATION'
STREAM_11_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_12_SYNCHRONIZATION'
STREAM_12_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_13_SYNCHRONIZATION'
STREAM_13_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_14_SYNCHRONIZATION'
STREAM_14_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_15_SYNCHRONIZATION'
STREAM_15_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'CORB_READ_POINTER_RESET'
CORB_READ_POINTER_RESET__enumvalues = {
0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET',
1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET',
}
CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0
CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1
CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum
# values for enumeration 'AZ_CORB_SIZE'
AZ_CORB_SIZE__enumvalues = {
0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED',
1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED',
2: 'AZ_CORB_SIZE_256ENTRIES',
3: 'AZ_CORB_SIZE_RESERVED',
}
AZ_CORB_SIZE_2ENTRIES_RESERVED = 0
AZ_CORB_SIZE_16ENTRIES_RESERVED = 1
AZ_CORB_SIZE_256ENTRIES = 2
AZ_CORB_SIZE_RESERVED = 3
AZ_CORB_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET'
AZ_RIRB_WRITE_POINTER_RESET__enumvalues = {
0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET',
1: 'AZ_RIRB_WRITE_POINTER_DO_RESET',
}
AZ_RIRB_WRITE_POINTER_NOT_RESET = 0
AZ_RIRB_WRITE_POINTER_DO_RESET = 1
AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum
# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL'
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = {
0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED',
1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED',
}
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL'
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = {
0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED',
1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED',
}
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'AZ_RIRB_SIZE'
AZ_RIRB_SIZE__enumvalues = {
0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED',
1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED',
2: 'AZ_RIRB_SIZE_256ENTRIES',
3: 'AZ_RIRB_SIZE_UNDEFINED',
}
AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0
AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1
AZ_RIRB_SIZE_256ENTRIES = 2
AZ_RIRB_SIZE_UNDEFINED = 3
AZ_RIRB_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID'
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = {
0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID',
1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID',
}
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum
# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY'
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = {
0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY',
1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY',
}
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum
# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE'
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = {
0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE',
1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE',
}
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16',
2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20',
3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24',
4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2',
2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3',
3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4',
4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5',
5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6',
6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7',
7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8',
8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE'
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN',
}
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE'
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED',
}
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT'
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN',
}
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE'
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1',
2: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2',
3: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3',
4: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4',
5: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5',
6: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6',
7: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7',
8: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8',
9: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9',
10: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10',
11: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11',
12: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12',
13: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13',
14: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14',
15: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15',
}
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 1
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 2
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 3
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 4
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 5
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 6
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 7
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 8
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 9
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 10
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 11
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 12
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 13
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 14
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 15
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_FORCE_CTRL'
MEM_PWR_FORCE_CTRL__enumvalues = {
0: 'NO_FORCE_REQUEST',
1: 'FORCE_LIGHT_SLEEP_REQUEST',
2: 'FORCE_DEEP_SLEEP_REQUEST',
3: 'FORCE_SHUT_DOWN_REQUEST',
}
NO_FORCE_REQUEST = 0
FORCE_LIGHT_SLEEP_REQUEST = 1
FORCE_DEEP_SLEEP_REQUEST = 2
FORCE_SHUT_DOWN_REQUEST = 3
MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_FORCE_CTRL2'
MEM_PWR_FORCE_CTRL2__enumvalues = {
0: 'NO_FORCE_REQ',
1: 'FORCE_LIGHT_SLEEP_REQ',
}
NO_FORCE_REQ = 0
FORCE_LIGHT_SLEEP_REQ = 1
MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_DIS_CTRL'
MEM_PWR_DIS_CTRL__enumvalues = {
0: 'ENABLE_MEM_PWR_CTRL',
1: 'DISABLE_MEM_PWR_CTRL',
}
ENABLE_MEM_PWR_CTRL = 0
DISABLE_MEM_PWR_CTRL = 1
MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_SEL_CTRL'
MEM_PWR_SEL_CTRL__enumvalues = {
0: 'DYNAMIC_SHUT_DOWN_ENABLE',
1: 'DYNAMIC_DEEP_SLEEP_ENABLE',
2: 'DYNAMIC_LIGHT_SLEEP_ENABLE',
}
DYNAMIC_SHUT_DOWN_ENABLE = 0
DYNAMIC_DEEP_SLEEP_ENABLE = 1
DYNAMIC_LIGHT_SLEEP_ENABLE = 2
MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_SEL_CTRL2'
MEM_PWR_SEL_CTRL2__enumvalues = {
0: 'DYNAMIC_DEEP_SLEEP_EN',
1: 'DYNAMIC_LIGHT_SLEEP_EN',
}
DYNAMIC_DEEP_SLEEP_EN = 0
DYNAMIC_LIGHT_SLEEP_EN = 1
MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET'
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = {
0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET',
1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC',
}
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY'
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = {
0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL',
1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6',
2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5',
3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4',
4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3',
5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2',
6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1',
7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0',
}
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum
# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY'
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = {
0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL',
1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6',
2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5',
3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4',
4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3',
5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2',
6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1',
7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0',
}
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16',
2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20',
3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24',
4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2',
2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3',
3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4',
4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5',
5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6',
6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7',
7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8',
8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET'
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = {
0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET',
1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET',
}
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum
# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL'
AZ_LATENCY_COUNTER_CONTROL__enumvalues = {
0: 'AZ_LATENCY_COUNTER_NO_RESET',
1: 'AZ_LATENCY_COUNTER_RESET_DONE',
}
AZ_LATENCY_COUNTER_NO_RESET = 0
AZ_LATENCY_COUNTER_RESET_DONE = 1
AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16',
2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20',
3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24',
4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2',
2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3',
3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4',
4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5',
5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6',
6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7',
7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8',
8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED',
9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED',
10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED',
11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED',
12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED',
13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED',
14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED',
15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED',
9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED',
9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE'
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE',
1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE',
}
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE'
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY',
1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY',
}
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED',
9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED',
9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_ICH_RESET_ENUM'
DSCC_ICH_RESET_ENUM__enumvalues = {
1: 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET',
2: 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET',
4: 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET',
8: 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET',
}
DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 1
DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 2
DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 4
DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 8
DSCC_ICH_RESET_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_DSC_VERSION_MINOR_ENUM'
DSCC_DSC_VERSION_MINOR_ENUM__enumvalues = {
1: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION',
2: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION',
}
DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 1
DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 2
DSCC_DSC_VERSION_MINOR_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_DSC_VERSION_MAJOR_ENUM'
DSCC_DSC_VERSION_MAJOR_ENUM__enumvalues = {
1: 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION',
}
DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 1
DSCC_DSC_VERSION_MAJOR_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_LINEBUF_DEPTH_ENUM'
DSCC_LINEBUF_DEPTH_ENUM__enumvalues = {
8: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT',
9: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT',
10: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT',
11: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT',
12: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT',
13: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT',
}
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 8
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 9
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 10
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 11
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 12
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 13
DSCC_LINEBUF_DEPTH_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_BITS_PER_COMPONENT_ENUM'
DSCC_BITS_PER_COMPONENT_ENUM__enumvalues = {
8: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT',
10: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT',
12: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT',
}
DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8
DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10
DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12
DSCC_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_ENABLE_ENUM'
DSCC_ENABLE_ENUM__enumvalues = {
0: 'DSCC_ENABLE_ENUM_DISABLED',
1: 'DSCC_ENABLE_ENUM_ENABLED',
}
DSCC_ENABLE_ENUM_DISABLED = 0
DSCC_ENABLE_ENUM_ENABLED = 1
DSCC_ENABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_MEM_PWR_FORCE_ENUM'
DSCC_MEM_PWR_FORCE_ENUM__enumvalues = {
0: 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST',
1: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST',
3: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST',
}
DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0
DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 1
DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 2
DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 3
DSCC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'POWER_STATE_ENUM'
POWER_STATE_ENUM__enumvalues = {
0: 'POWER_STATE_ENUM_ON',
1: 'POWER_STATE_ENUM_LS',
2: 'POWER_STATE_ENUM_DS',
3: 'POWER_STATE_ENUM_SD',
}
POWER_STATE_ENUM_ON = 0
POWER_STATE_ENUM_LS = 1
POWER_STATE_ENUM_DS = 2
POWER_STATE_ENUM_SD = 3
POWER_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_MEM_PWR_DIS_ENUM'
DSCC_MEM_PWR_DIS_ENUM__enumvalues = {
0: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN',
1: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS',
}
DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0
DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 1
DSCC_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCCIF_ENABLE_ENUM'
DSCCIF_ENABLE_ENUM__enumvalues = {
0: 'DSCCIF_ENABLE_ENUM_DISABLED',
1: 'DSCCIF_ENABLE_ENUM_ENABLED',
}
DSCCIF_ENABLE_ENUM_DISABLED = 0
DSCCIF_ENABLE_ENUM_ENABLED = 1
DSCCIF_ENABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM'
DSCCIF_INPUT_PIXEL_FORMAT_ENUM__enumvalues = {
0: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB',
1: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444',
2: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422',
3: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422',
4: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420',
}
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 1
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 2
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 3
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 4
DSCCIF_INPUT_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCCIF_BITS_PER_COMPONENT_ENUM'
DSCCIF_BITS_PER_COMPONENT_ENUM__enumvalues = {
8: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT',
10: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT',
12: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT',
}
DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8
DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10
DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12
DSCCIF_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'ENABLE_ENUM'
ENABLE_ENUM__enumvalues = {
0: 'ENABLE_ENUM_DISABLED',
1: 'ENABLE_ENUM_ENABLED',
}
ENABLE_ENUM_DISABLED = 0
ENABLE_ENUM_ENABLED = 1
ENABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CLOCK_GATING_DISABLE_ENUM'
CLOCK_GATING_DISABLE_ENUM__enumvalues = {
0: 'CLOCK_GATING_DISABLE_ENUM_ENABLED',
1: 'CLOCK_GATING_DISABLE_ENUM_DISABLED',
}
CLOCK_GATING_DISABLE_ENUM_ENABLED = 0
CLOCK_GATING_DISABLE_ENUM_DISABLED = 1
CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'TEST_CLOCK_MUX_SELECT_ENUM'
TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = {
0: 'TEST_CLOCK_MUX_SELECT_DISPCLK_P',
1: 'TEST_CLOCK_MUX_SELECT_DISPCLK_G',
2: 'TEST_CLOCK_MUX_SELECT_DISPCLK_R',
3: 'TEST_CLOCK_MUX_SELECT_DSCCLK_P',
4: 'TEST_CLOCK_MUX_SELECT_DSCCLK_G',
5: 'TEST_CLOCK_MUX_SELECT_DSCCLK_R',
}
TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0
TEST_CLOCK_MUX_SELECT_DISPCLK_G = 1
TEST_CLOCK_MUX_SELECT_DISPCLK_R = 2
TEST_CLOCK_MUX_SELECT_DSCCLK_P = 3
TEST_CLOCK_MUX_SELECT_DSCCLK_G = 4
TEST_CLOCK_MUX_SELECT_DSCCLK_R = 5
TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WB_ENABLE_ENUM'
WB_ENABLE_ENUM__enumvalues = {
0: 'WB_EN_DISABLE',
1: 'WB_EN_ENABLE',
}
WB_EN_DISABLE = 0
WB_EN_ENABLE = 1
WB_ENABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WB_CLK_GATE_DIS_ENUM'
WB_CLK_GATE_DIS_ENUM__enumvalues = {
0: 'WB_CLK_GATE_ENABLE',
1: 'WB_CLK_GATE_DISABLE',
}
WB_CLK_GATE_ENABLE = 0
WB_CLK_GATE_DISABLE = 1
WB_CLK_GATE_DIS_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WB_MEM_PWR_DIS_ENUM'
WB_MEM_PWR_DIS_ENUM__enumvalues = {
0: 'WB_MEM_PWR_ENABLE',
1: 'WB_MEM_PWR_DISABLE',
}
WB_MEM_PWR_ENABLE = 0
WB_MEM_PWR_DISABLE = 1
WB_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WB_TEST_CLK_SEL_ENUM'
WB_TEST_CLK_SEL_ENUM__enumvalues = {
0: 'WB_TEST_CLK_SEL_REG',
1: 'WB_TEST_CLK_SEL_WB',
2: 'WB_TEST_CLK_SEL_WBSCL',
3: 'WB_TEST_CLK_SEL_PERM',
}
WB_TEST_CLK_SEL_REG = 0
WB_TEST_CLK_SEL_WB = 1
WB_TEST_CLK_SEL_WBSCL = 2
WB_TEST_CLK_SEL_PERM = 3
WB_TEST_CLK_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_LB_MEM_PWR_MODE_SEL_ENUM'
WBSCL_LB_MEM_PWR_MODE_SEL_ENUM__enumvalues = {
0: 'WBSCL_LB_MEM_PWR_MODE_SEL_SD',
1: 'WBSCL_LB_MEM_PWR_MODE_SEL_DS',
2: 'WBSCL_LB_MEM_PWR_MODE_SEL_LS',
3: 'WBSCL_LB_MEM_PWR_MODE_SEL_ON',
}
WBSCL_LB_MEM_PWR_MODE_SEL_SD = 0
WBSCL_LB_MEM_PWR_MODE_SEL_DS = 1
WBSCL_LB_MEM_PWR_MODE_SEL_LS = 2
WBSCL_LB_MEM_PWR_MODE_SEL_ON = 3
WBSCL_LB_MEM_PWR_MODE_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_LB_MEM_PWR_FORCE_ENUM'
WBSCL_LB_MEM_PWR_FORCE_ENUM__enumvalues = {
0: 'WBSCL_LB_MEM_PWR_FORCE_NO',
1: 'WBSCL_LB_MEM_PWR_FORCE_LS',
2: 'WBSCL_LB_MEM_PWR_FORCE_DS',
3: 'WBSCL_LB_MEM_PWR_FORCE_SD',
}
WBSCL_LB_MEM_PWR_FORCE_NO = 0
WBSCL_LB_MEM_PWR_FORCE_LS = 1
WBSCL_LB_MEM_PWR_FORCE_DS = 2
WBSCL_LB_MEM_PWR_FORCE_SD = 3
WBSCL_LB_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_MEM_PWR_STATE_ENUM'
WBSCL_MEM_PWR_STATE_ENUM__enumvalues = {
0: 'WBSCL_MEM_PWR_STATE_ON',
1: 'WBSCL_MEM_PWR_STATE_LS',
2: 'WBSCL_MEM_PWR_STATE_DS',
3: 'WBSCL_MEM_PWR_STATE_SD',
}
WBSCL_MEM_PWR_STATE_ON = 0
WBSCL_MEM_PWR_STATE_LS = 1
WBSCL_MEM_PWR_STATE_DS = 2
WBSCL_MEM_PWR_STATE_SD = 3
WBSCL_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_LUT_MEM_PWR_STATE_ENUM'
WBSCL_LUT_MEM_PWR_STATE_ENUM__enumvalues = {
0: 'WBSCL_LUT_MEM_PWR_STATE_ON',
1: 'WBSCL_LUT_MEM_PWR_STATE_LS',
2: 'WBSCL_LUT_MEM_PWR_STATE_RESERVED2',
3: 'WBSCL_LUT_MEM_PWR_STATE_RESERVED3',
}
WBSCL_LUT_MEM_PWR_STATE_ON = 0
WBSCL_LUT_MEM_PWR_STATE_LS = 1
WBSCL_LUT_MEM_PWR_STATE_RESERVED2 = 2
WBSCL_LUT_MEM_PWR_STATE_RESERVED3 = 3
WBSCL_LUT_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WB_RAM_PW_SAVE_MODE_ENUM'
WB_RAM_PW_SAVE_MODE_ENUM__enumvalues = {
0: 'WB_RAM_PW_SAVE_MODE_LS',
1: 'WB_RAM_PW_SAVE_MODE_SD',
}
WB_RAM_PW_SAVE_MODE_LS = 0
WB_RAM_PW_SAVE_MODE_SD = 1
WB_RAM_PW_SAVE_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_OUT_BPC_ENUM'
CNV_OUT_BPC_ENUM__enumvalues = {
0: 'CNV_OUT_BPC_8BPC',
1: 'CNV_OUT_BPC_10BPC',
}
CNV_OUT_BPC_8BPC = 0
CNV_OUT_BPC_10BPC = 1
CNV_OUT_BPC_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_FRAME_CAPTURE_RATE_ENUM'
CNV_FRAME_CAPTURE_RATE_ENUM__enumvalues = {
0: 'CNV_FRAME_CAPTURE_RATE_0',
1: 'CNV_FRAME_CAPTURE_RATE_1',
2: 'CNV_FRAME_CAPTURE_RATE_2',
3: 'CNV_FRAME_CAPTURE_RATE_3',
}
CNV_FRAME_CAPTURE_RATE_0 = 0
CNV_FRAME_CAPTURE_RATE_1 = 1
CNV_FRAME_CAPTURE_RATE_2 = 2
CNV_FRAME_CAPTURE_RATE_3 = 3
CNV_FRAME_CAPTURE_RATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_WINDOW_CROP_EN_ENUM'
CNV_WINDOW_CROP_EN_ENUM__enumvalues = {
0: 'CNV_WINDOW_CROP_DISABLE',
1: 'CNV_WINDOW_CROP_ENABLE',
}
CNV_WINDOW_CROP_DISABLE = 0
CNV_WINDOW_CROP_ENABLE = 1
CNV_WINDOW_CROP_EN_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_INTERLACED_MODE_ENUM'
CNV_INTERLACED_MODE_ENUM__enumvalues = {
0: 'CNV_INTERLACED_MODE_PROGRESSIVE',
1: 'CNV_INTERLACED_MODE_INTERLACED',
}
CNV_INTERLACED_MODE_PROGRESSIVE = 0
CNV_INTERLACED_MODE_INTERLACED = 1
CNV_INTERLACED_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_EYE_SELECT'
CNV_EYE_SELECT__enumvalues = {
0: 'STEREO_DISABLED',
1: 'LEFT_EYE',
2: 'RIGHT_EYE',
3: 'BOTH_EYE',
}
STEREO_DISABLED = 0
LEFT_EYE = 1
RIGHT_EYE = 2
BOTH_EYE = 3
CNV_EYE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'CNV_STEREO_TYPE_ENUM'
CNV_STEREO_TYPE_ENUM__enumvalues = {
0: 'CNV_STEREO_TYPE_RESERVED0',
1: 'CNV_STEREO_TYPE_RESERVED1',
2: 'CNV_STEREO_TYPE_RESERVED2',
3: 'CNV_STEREO_TYPE_FRAME_SEQUENTIAL',
}
CNV_STEREO_TYPE_RESERVED0 = 0
CNV_STEREO_TYPE_RESERVED1 = 1
CNV_STEREO_TYPE_RESERVED2 = 2
CNV_STEREO_TYPE_FRAME_SEQUENTIAL = 3
CNV_STEREO_TYPE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_STEREO_POLARITY_ENUM'
CNV_STEREO_POLARITY_ENUM__enumvalues = {
0: 'CNV_STEREO_POLARITY_LEFT',
1: 'CNV_STEREO_POLARITY_RIGHT',
}
CNV_STEREO_POLARITY_LEFT = 0
CNV_STEREO_POLARITY_RIGHT = 1
CNV_STEREO_POLARITY_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_INTERLACED_FIELD_ORDER_ENUM'
CNV_INTERLACED_FIELD_ORDER_ENUM__enumvalues = {
0: 'CNV_INTERLACED_FIELD_ORDER_TOP',
1: 'CNV_INTERLACED_FIELD_ORDER_BOT',
}
CNV_INTERLACED_FIELD_ORDER_TOP = 0
CNV_INTERLACED_FIELD_ORDER_BOT = 1
CNV_INTERLACED_FIELD_ORDER_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_STEREO_SPLIT_ENUM'
CNV_STEREO_SPLIT_ENUM__enumvalues = {
0: 'CNV_STEREO_SPLIT_DISABLE',
1: 'CNV_STEREO_SPLIT_ENABLE',
}
CNV_STEREO_SPLIT_DISABLE = 0
CNV_STEREO_SPLIT_ENABLE = 1
CNV_STEREO_SPLIT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_NEW_CONTENT_ENUM'
CNV_NEW_CONTENT_ENUM__enumvalues = {
0: 'CNV_NEW_CONTENT_NEG',
1: 'CNV_NEW_CONTENT_POS',
}
CNV_NEW_CONTENT_NEG = 0
CNV_NEW_CONTENT_POS = 1
CNV_NEW_CONTENT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_FRAME_CAPTURE_EN_ENUM'
CNV_FRAME_CAPTURE_EN_ENUM__enumvalues = {
0: 'CNV_FRAME_CAPTURE_DISABLE',
1: 'CNV_FRAME_CAPTURE_ENABLE',
}
CNV_FRAME_CAPTURE_DISABLE = 0
CNV_FRAME_CAPTURE_ENABLE = 1
CNV_FRAME_CAPTURE_EN_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_UPDATE_PENDING_ENUM'
CNV_UPDATE_PENDING_ENUM__enumvalues = {
0: 'CNV_UPDATE_PENDING_NEG',
1: 'CNV_UPDATE_PENDING_POS',
}
CNV_UPDATE_PENDING_NEG = 0
CNV_UPDATE_PENDING_POS = 1
CNV_UPDATE_PENDING_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_UPDATE_LOCK_ENUM'
CNV_UPDATE_LOCK_ENUM__enumvalues = {
0: 'CNV_UPDATE_UNLOCK',
1: 'CNV_UPDATE_LOCK',
}
CNV_UPDATE_UNLOCK = 0
CNV_UPDATE_LOCK = 1
CNV_UPDATE_LOCK_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_CSC_BYPASS_ENUM'
CNV_CSC_BYPASS_ENUM__enumvalues = {
0: 'CNV_CSC_BYPASS_NEG',
1: 'CNV_CSC_BYPASS_POS',
}
CNV_CSC_BYPASS_NEG = 0
CNV_CSC_BYPASS_POS = 1
CNV_CSC_BYPASS_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_TEST_CRC_EN_ENUM'
CNV_TEST_CRC_EN_ENUM__enumvalues = {
0: 'CNV_TEST_CRC_DISABLE',
1: 'CNV_TEST_CRC_ENABLE',
}
CNV_TEST_CRC_DISABLE = 0
CNV_TEST_CRC_ENABLE = 1
CNV_TEST_CRC_EN_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNV_TEST_CRC_CONT_EN_ENUM'
CNV_TEST_CRC_CONT_EN_ENUM__enumvalues = {
0: 'CNV_TEST_CRC_CONT_DISABLE',
1: 'CNV_TEST_CRC_CONT_ENABLE',
}
CNV_TEST_CRC_CONT_DISABLE = 0
CNV_TEST_CRC_CONT_ENABLE = 1
CNV_TEST_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WB_SOFT_RESET_ENUM'
WB_SOFT_RESET_ENUM__enumvalues = {
0: 'WB_SOFT_RESET_NEG',
1: 'WB_SOFT_RESET_POS',
}
WB_SOFT_RESET_NEG = 0
WB_SOFT_RESET_POS = 1
WB_SOFT_RESET_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_GMC_WARM_UP_ENABLE_ENUM'
DWB_GMC_WARM_UP_ENABLE_ENUM__enumvalues = {
0: 'DWB_GMC_WARM_UP_DISABLE',
1: 'DWB_GMC_WARM_UP_ENABLE',
}
DWB_GMC_WARM_UP_DISABLE = 0
DWB_GMC_WARM_UP_ENABLE = 1
DWB_GMC_WARM_UP_ENABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_MODE_WARMUP_ENUM'
DWB_MODE_WARMUP_ENUM__enumvalues = {
0: 'DWB_MODE_WARMUP_420',
1: 'DWB_MODE_WARMUP_444',
}
DWB_MODE_WARMUP_420 = 0
DWB_MODE_WARMUP_444 = 1
DWB_MODE_WARMUP_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_DATA_DEPTH_WARMUP_ENUM'
DWB_DATA_DEPTH_WARMUP_ENUM__enumvalues = {
0: 'DWB_DATA_DEPTH_WARMUP_8BPC',
1: 'DWB_DATA_DEPTH_WARMUP_10BPC',
}
DWB_DATA_DEPTH_WARMUP_8BPC = 0
DWB_DATA_DEPTH_WARMUP_10BPC = 1
DWB_DATA_DEPTH_WARMUP_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM'
WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM__enumvalues = {
0: 'WBSCL_COEF_RAM_TAP_PAIR_IDX0',
1: 'WBSCL_COEF_RAM_TAP_PAIR_IDX1',
2: 'WBSCL_COEF_RAM_TAP_PAIR_IDX2',
3: 'WBSCL_COEF_RAM_TAP_PAIR_IDX3',
4: 'WBSCL_COEF_RAM_TAP_PAIR_IDX4',
5: 'WBSCL_COEF_RAM_TAP_PAIR_IDX5',
}
WBSCL_COEF_RAM_TAP_PAIR_IDX0 = 0
WBSCL_COEF_RAM_TAP_PAIR_IDX1 = 1
WBSCL_COEF_RAM_TAP_PAIR_IDX2 = 2
WBSCL_COEF_RAM_TAP_PAIR_IDX3 = 3
WBSCL_COEF_RAM_TAP_PAIR_IDX4 = 4
WBSCL_COEF_RAM_TAP_PAIR_IDX5 = 5
WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_COEF_RAM_PHASE_ENUM'
WBSCL_COEF_RAM_PHASE_ENUM__enumvalues = {
0: 'WBSCL_COEF_RAM_PHASE0',
1: 'WBSCL_COEF_RAM_PHASE1',
2: 'WBSCL_COEF_RAM_PHASE2',
3: 'WBSCL_COEF_RAM_PHASE3',
4: 'WBSCL_COEF_RAM_PHASE4',
5: 'WBSCL_COEF_RAM_PHASE5',
6: 'WBSCL_COEF_RAM_PHASE6',
7: 'WBSCL_COEF_RAM_PHASE7',
8: 'WBSCL_COEF_RAM_PHASE8',
}
WBSCL_COEF_RAM_PHASE0 = 0
WBSCL_COEF_RAM_PHASE1 = 1
WBSCL_COEF_RAM_PHASE2 = 2
WBSCL_COEF_RAM_PHASE3 = 3
WBSCL_COEF_RAM_PHASE4 = 4
WBSCL_COEF_RAM_PHASE5 = 5
WBSCL_COEF_RAM_PHASE6 = 6
WBSCL_COEF_RAM_PHASE7 = 7
WBSCL_COEF_RAM_PHASE8 = 8
WBSCL_COEF_RAM_PHASE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_COEF_RAM_FILTER_TYPE_ENUM'
WBSCL_COEF_RAM_FILTER_TYPE_ENUM__enumvalues = {
0: 'WBSCL_COEF_RAM_FILTER_TYPE_VL',
1: 'WBSCL_COEF_RAM_FILTER_TYPE_VC',
2: 'WBSCL_COEF_RAM_FILTER_TYPE_HL',
3: 'WBSCL_COEF_RAM_FILTER_TYPE_HC',
}
WBSCL_COEF_RAM_FILTER_TYPE_VL = 0
WBSCL_COEF_RAM_FILTER_TYPE_VC = 1
WBSCL_COEF_RAM_FILTER_TYPE_HL = 2
WBSCL_COEF_RAM_FILTER_TYPE_HC = 3
WBSCL_COEF_RAM_FILTER_TYPE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_COEF_FILTER_TYPE_SEL'
WBSCL_COEF_FILTER_TYPE_SEL__enumvalues = {
0: 'WBSCL_COEF_LUMA_VERT_FILTER',
1: 'WBSCL_COEF_CHROMA_VERT_FILTER',
2: 'WBSCL_COEF_LUMA_HORZ_FILTER',
3: 'WBSCL_COEF_CHROMA_HORZ_FILTER',
}
WBSCL_COEF_LUMA_VERT_FILTER = 0
WBSCL_COEF_CHROMA_VERT_FILTER = 1
WBSCL_COEF_LUMA_HORZ_FILTER = 2
WBSCL_COEF_CHROMA_HORZ_FILTER = 3
WBSCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_MODE_SEL'
WBSCL_MODE_SEL__enumvalues = {
0: 'WBSCL_MODE_SCALING_444_BYPASS',
1: 'WBSCL_MODE_SCALING_444_RGB_ENABLE',
2: 'WBSCL_MODE_SCALING_444_YCBCR_ENABLE',
3: 'WBSCL_MODE_SCALING_YCBCR_ENABLE',
}
WBSCL_MODE_SCALING_444_BYPASS = 0
WBSCL_MODE_SCALING_444_RGB_ENABLE = 1
WBSCL_MODE_SCALING_444_YCBCR_ENABLE = 2
WBSCL_MODE_SCALING_YCBCR_ENABLE = 3
WBSCL_MODE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_PIXEL_DEPTH'
WBSCL_PIXEL_DEPTH__enumvalues = {
0: 'PIXEL_DEPTH_8BPC',
1: 'PIXEL_DEPTH_10BPC',
}
PIXEL_DEPTH_8BPC = 0
PIXEL_DEPTH_10BPC = 1
WBSCL_PIXEL_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_COEF_RAM_SEL_ENUM'
WBSCL_COEF_RAM_SEL_ENUM__enumvalues = {
0: 'WBSCL_COEF_RAM_SEL_0',
1: 'WBSCL_COEF_RAM_SEL_1',
}
WBSCL_COEF_RAM_SEL_0 = 0
WBSCL_COEF_RAM_SEL_1 = 1
WBSCL_COEF_RAM_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_COEF_RAM_RD_SEL_ENUM'
WBSCL_COEF_RAM_RD_SEL_ENUM__enumvalues = {
0: 'WBSCL_COEF_RAM_RD_SEL_0',
1: 'WBSCL_COEF_RAM_RD_SEL_1',
}
WBSCL_COEF_RAM_RD_SEL_0 = 0
WBSCL_COEF_RAM_RD_SEL_1 = 1
WBSCL_COEF_RAM_RD_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_COEF_RAM_TAP_COEF_EN_ENUM'
WBSCL_COEF_RAM_TAP_COEF_EN_ENUM__enumvalues = {
0: 'WBSCL_COEF_RAM_TAP_COEF_DISABLE',
1: 'WBSCL_COEF_RAM_TAP_COEF_ENABLE',
}
WBSCL_COEF_RAM_TAP_COEF_DISABLE = 0
WBSCL_COEF_RAM_TAP_COEF_ENABLE = 1
WBSCL_COEF_RAM_TAP_COEF_EN_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_NUM_OF_TAPS_ENUM'
WBSCL_NUM_OF_TAPS_ENUM__enumvalues = {
0: 'WBSCL_NUM_OF_TAPS0',
1: 'WBSCL_NUM_OF_TAPS1',
2: 'WBSCL_NUM_OF_TAPS2',
3: 'WBSCL_NUM_OF_TAPS3',
4: 'WBSCL_NUM_OF_TAPS4',
5: 'WBSCL_NUM_OF_TAPS5',
6: 'WBSCL_NUM_OF_TAPS6',
7: 'WBSCL_NUM_OF_TAPS7',
8: 'WBSCL_NUM_OF_TAPS8',
9: 'WBSCL_NUM_OF_TAPS9',
10: 'WBSCL_NUM_OF_TAPS10',
11: 'WBSCL_NUM_OF_TAPS11',
}
WBSCL_NUM_OF_TAPS0 = 0
WBSCL_NUM_OF_TAPS1 = 1
WBSCL_NUM_OF_TAPS2 = 2
WBSCL_NUM_OF_TAPS3 = 3
WBSCL_NUM_OF_TAPS4 = 4
WBSCL_NUM_OF_TAPS5 = 5
WBSCL_NUM_OF_TAPS6 = 6
WBSCL_NUM_OF_TAPS7 = 7
WBSCL_NUM_OF_TAPS8 = 8
WBSCL_NUM_OF_TAPS9 = 9
WBSCL_NUM_OF_TAPS10 = 10
WBSCL_NUM_OF_TAPS11 = 11
WBSCL_NUM_OF_TAPS_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_STATUS_ACK_ENUM'
WBSCL_STATUS_ACK_ENUM__enumvalues = {
0: 'WBSCL_STATUS_ACK_NCLR',
1: 'WBSCL_STATUS_ACK_CLR',
}
WBSCL_STATUS_ACK_NCLR = 0
WBSCL_STATUS_ACK_CLR = 1
WBSCL_STATUS_ACK_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_STATUS_MASK_ENUM'
WBSCL_STATUS_MASK_ENUM__enumvalues = {
0: 'WBSCL_STATUS_MASK_DISABLE',
1: 'WBSCL_STATUS_MASK_ENABLE',
}
WBSCL_STATUS_MASK_DISABLE = 0
WBSCL_STATUS_MASK_ENABLE = 1
WBSCL_STATUS_MASK_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM'
WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM__enumvalues = {
0: 'WBSCL_DATA_OVERFLOW_INT_TYPE_REG',
1: 'WBSCL_DATA_OVERFLOW_INT_TYPE_HW',
}
WBSCL_DATA_OVERFLOW_INT_TYPE_REG = 0
WBSCL_DATA_OVERFLOW_INT_TYPE_HW = 1
WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_HOST_CONFLICT_INT_TYPE_ENUM'
WBSCL_HOST_CONFLICT_INT_TYPE_ENUM__enumvalues = {
0: 'WBSCL_HOST_CONFLICT_INT_TYPE_REG',
1: 'WBSCL_HOST_CONFLICT_INT_TYPE_HW',
}
WBSCL_HOST_CONFLICT_INT_TYPE_REG = 0
WBSCL_HOST_CONFLICT_INT_TYPE_HW = 1
WBSCL_HOST_CONFLICT_INT_TYPE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_TEST_CRC_EN_ENUM'
WBSCL_TEST_CRC_EN_ENUM__enumvalues = {
0: 'WBSCL_TEST_CRC_DISABLE',
1: 'WBSCL_TEST_CRC_ENABLE',
}
WBSCL_TEST_CRC_DISABLE = 0
WBSCL_TEST_CRC_ENABLE = 1
WBSCL_TEST_CRC_EN_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_TEST_CRC_CONT_EN_ENUM'
WBSCL_TEST_CRC_CONT_EN_ENUM__enumvalues = {
0: 'WBSCL_TEST_CRC_CONT_DISABLE',
1: 'WBSCL_TEST_CRC_CONT_ENABLE',
}
WBSCL_TEST_CRC_CONT_DISABLE = 0
WBSCL_TEST_CRC_CONT_ENABLE = 1
WBSCL_TEST_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_TEST_CRC_MASK_ENUM'
WBSCL_TEST_CRC_MASK_ENUM__enumvalues = {
0: 'WBSCL_TEST_CRC_MASKED',
1: 'WBSCL_TEST_CRC_UNMASKED',
}
WBSCL_TEST_CRC_MASKED = 0
WBSCL_TEST_CRC_UNMASKED = 1
WBSCL_TEST_CRC_MASK_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_BACKPRESSURE_CNT_EN_ENUM'
WBSCL_BACKPRESSURE_CNT_EN_ENUM__enumvalues = {
0: 'WBSCL_BACKPRESSURE_CNT_DISABLE',
1: 'WBSCL_BACKPRESSURE_CNT_ENABLE',
}
WBSCL_BACKPRESSURE_CNT_DISABLE = 0
WBSCL_BACKPRESSURE_CNT_ENABLE = 1
WBSCL_BACKPRESSURE_CNT_EN_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'WBSCL_OUTSIDE_PIX_STRATEGY_ENUM'
WBSCL_OUTSIDE_PIX_STRATEGY_ENUM__enumvalues = {
0: 'WBSCL_OUTSIDE_PIX_STRATEGY_BLACK',
1: 'WBSCL_OUTSIDE_PIX_STRATEGY_EDGE',
}
WBSCL_OUTSIDE_PIX_STRATEGY_BLACK = 0
WBSCL_OUTSIDE_PIX_STRATEGY_EDGE = 1
WBSCL_OUTSIDE_PIX_STRATEGY_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL'
DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL__enumvalues = {
0: 'DPCSRX_BPHY_PCS_RX0_CLK',
1: 'DPCSRX_BPHY_PCS_RX1_CLK',
2: 'DPCSRX_BPHY_PCS_RX2_CLK',
3: 'DPCSRX_BPHY_PCS_RX3_CLK',
}
DPCSRX_BPHY_PCS_RX0_CLK = 0
DPCSRX_BPHY_PCS_RX1_CLK = 1
DPCSRX_BPHY_PCS_RX2_CLK = 2
DPCSRX_BPHY_PCS_RX3_CLK = 3
DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DPCSTX_DVI_LINK_MODE'
DPCSTX_DVI_LINK_MODE__enumvalues = {
0: 'DPCSTX_DVI_LINK_MODE_NORMAL',
1: 'DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER',
2: 'DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER',
}
DPCSTX_DVI_LINK_MODE_NORMAL = 0
DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER = 1
DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER = 2
DPCSTX_DVI_LINK_MODE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET'
RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET__enumvalues = {
0: 'RDPCS_CBUS_SOFT_RESET_DISABLE',
1: 'RDPCS_CBUS_SOFT_RESET_ENABLE',
}
RDPCS_CBUS_SOFT_RESET_DISABLE = 0
RDPCS_CBUS_SOFT_RESET_ENABLE = 1
RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET'
RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET__enumvalues = {
0: 'RDPCS_SRAM_SRAM_RESET_DISABLE',
}
RDPCS_SRAM_SRAM_RESET_DISABLE = 0
RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN'
RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN__enumvalues = {
0: 'RDPCS_TX_FIFO_LANE_DISABLE',
1: 'RDPCS_TX_FIFO_LANE_ENABLE',
}
RDPCS_TX_FIFO_LANE_DISABLE = 0
RDPCS_TX_FIFO_LANE_ENABLE = 1
RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_FIFO_EN'
RDPCSTX_CNTL_RDPCS_TX_FIFO_EN__enumvalues = {
0: 'RDPCS_TX_FIFO_DISABLE',
1: 'RDPCS_TX_FIFO_ENABLE',
}
RDPCS_TX_FIFO_DISABLE = 0
RDPCS_TX_FIFO_ENABLE = 1
RDPCSTX_CNTL_RDPCS_TX_FIFO_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET'
RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET__enumvalues = {
0: 'RDPCS_TX_SOFT_RESET_DISABLE',
1: 'RDPCS_TX_SOFT_RESET_ENABLE',
}
RDPCS_TX_SOFT_RESET_DISABLE = 0
RDPCS_TX_SOFT_RESET_ENABLE = 1
RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN'
RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN__enumvalues = {
0: 'RDPCS_EXT_REFCLK_DISABLE',
1: 'RDPCS_EXT_REFCLK_ENABLE',
}
RDPCS_EXT_REFCLK_DISABLE = 0
RDPCS_EXT_REFCLK_ENABLE = 1
RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN'
RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN__enumvalues = {
0: 'RDPCS_EXT_REFCLK_EN_DISABLE',
1: 'RDPCS_EXT_REFCLK_EN_ENABLE',
}
RDPCS_EXT_REFCLK_EN_DISABLE = 0
RDPCS_EXT_REFCLK_EN_ENABLE = 1
RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS'
RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS__enumvalues = {
0: 'RDPCS_SYMCLK_DIV2_GATE_ENABLE',
1: 'RDPCS_SYMCLK_DIV2_GATE_DISABLE',
}
RDPCS_SYMCLK_DIV2_GATE_ENABLE = 0
RDPCS_SYMCLK_DIV2_GATE_DISABLE = 1
RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN'
RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN__enumvalues = {
0: 'RDPCS_SYMCLK_DIV2_DISABLE',
1: 'RDPCS_SYMCLK_DIV2_ENABLE',
}
RDPCS_SYMCLK_DIV2_DISABLE = 0
RDPCS_SYMCLK_DIV2_ENABLE = 1
RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON'
RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON__enumvalues = {
0: 'RDPCS_SYMCLK_DIV2_CLOCK_OFF',
1: 'RDPCS_SYMCLK_DIV2_CLOCK_ON',
}
RDPCS_SYMCLK_DIV2_CLOCK_OFF = 0
RDPCS_SYMCLK_DIV2_CLOCK_ON = 1
RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS'
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS__enumvalues = {
0: 'RDPCS_SRAMCLK_GATE_ENABLE',
1: 'RDPCS_SRAMCLK_GATE_DISABLE',
}
RDPCS_SRAMCLK_GATE_ENABLE = 0
RDPCS_SRAMCLK_GATE_DISABLE = 1
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN'
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN__enumvalues = {
0: 'RDPCS_SRAMCLK_DISABLE',
1: 'RDPCS_SRAMCLK_ENABLE',
}
RDPCS_SRAMCLK_DISABLE = 0
RDPCS_SRAMCLK_ENABLE = 1
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS'
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS__enumvalues = {
0: 'RDPCS_SRAMCLK_NOT_BYPASS',
1: 'RDPCS_SRAMCLK_BYPASS',
}
RDPCS_SRAMCLK_NOT_BYPASS = 0
RDPCS_SRAMCLK_BYPASS = 1
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON'
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON__enumvalues = {
0: 'RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF',
1: 'RDPCS_SYMCLK_SRAMCLK_CLOCK_ON',
}
RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF = 0
RDPCS_SYMCLK_SRAMCLK_CLOCK_ON = 1
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE'
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE__enumvalues = {
0: 'RDPCS_DPALT_DISABLE_TOGGLE_ENABLE',
1: 'RDPCS_DPALT_DISABLE_TOGGLE_DISABLE',
}
RDPCS_DPALT_DISABLE_TOGGLE_ENABLE = 0
RDPCS_DPALT_DISABLE_TOGGLE_DISABLE = 1
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE'
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE__enumvalues = {
0: 'RDPCS_DPALT_4LANE_TOGGLE_2LANE',
1: 'RDPCS_DPALT_4LANE_TOGGLE_4LANE',
}
RDPCS_DPALT_4LANE_TOGGLE_2LANE = 0
RDPCS_DPALT_4LANE_TOGGLE_4LANE = 1
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK'
RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK__enumvalues = {
0: 'RDPCS_REG_FIFO_ERROR_MASK_DISABLE',
1: 'RDPCS_REG_FIFO_ERROR_MASK_ENABLE',
}
RDPCS_REG_FIFO_ERROR_MASK_DISABLE = 0
RDPCS_REG_FIFO_ERROR_MASK_ENABLE = 1
RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK'
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK__enumvalues = {
0: 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE',
1: 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE',
}
RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0
RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 1
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK'
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK__enumvalues = {
0: 'RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE',
1: 'RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE',
}
RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0
RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE = 1
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK'
RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK__enumvalues = {
0: 'RDPCS_TX_FIFO_ERROR_MASK_DISABLE',
1: 'RDPCS_TX_FIFO_ERROR_MASK_ENABLE',
}
RDPCS_TX_FIFO_ERROR_MASK_DISABLE = 0
RDPCS_TX_FIFO_ERROR_MASK_ENABLE = 1
RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE'
RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE__enumvalues = {
0: 'RDPCS_MEM_PWR_NO_FORCE',
1: 'RDPCS_MEM_PWR_LIGHT_SLEEP',
2: 'RDPCS_MEM_PWR_DEEP_SLEEP',
3: 'RDPCS_MEM_PWR_SHUT_DOWN',
}
RDPCS_MEM_PWR_NO_FORCE = 0
RDPCS_MEM_PWR_LIGHT_SLEEP = 1
RDPCS_MEM_PWR_DEEP_SLEEP = 2
RDPCS_MEM_PWR_SHUT_DOWN = 3
RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE'
RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE__enumvalues = {
0: 'RDPCS_MEM_PWR_PWR_STATE_ON',
1: 'RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP',
2: 'RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP',
3: 'RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN',
}
RDPCS_MEM_PWR_PWR_STATE_ON = 0
RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 1
RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP = 2
RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN = 3
RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF'
RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF__enumvalues = {
0: 'RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY',
1: 'RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD',
2: 'RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3',
3: 'RDPCS_MEM_POWER_CTRL_POFF_FOR_SD',
}
RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY = 0
RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD = 1
RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3 = 2
RDPCS_MEM_POWER_CTRL_POFF_FOR_SD = 3
RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE'
RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE__enumvalues = {
0: 'RDPCS_PHY_REF_RANGE_0',
1: 'RDPCS_PHY_REF_RANGE_1',
2: 'RDPCS_PHY_REF_RANGE_2',
3: 'RDPCS_PHY_REF_RANGE_3',
4: 'RDPCS_PHY_REF_RANGE_4',
5: 'RDPCS_PHY_REF_RANGE_5',
6: 'RDPCS_PHY_REF_RANGE_6',
7: 'RDPCS_PHY_REF_RANGE_7',
}
RDPCS_PHY_REF_RANGE_0 = 0
RDPCS_PHY_REF_RANGE_1 = 1
RDPCS_PHY_REF_RANGE_2 = 2
RDPCS_PHY_REF_RANGE_3 = 3
RDPCS_PHY_REF_RANGE_4 = 4
RDPCS_PHY_REF_RANGE_5 = 5
RDPCS_PHY_REF_RANGE_6 = 6
RDPCS_PHY_REF_RANGE_7 = 7
RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL'
RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL__enumvalues = {
0: 'RDPCS_PHY_CR_PARA_SEL_JTAG',
1: 'RDPCS_PHY_CR_PARA_SEL_CR',
}
RDPCS_PHY_CR_PARA_SEL_JTAG = 0
RDPCS_PHY_CR_PARA_SEL_CR = 1
RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL'
RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL__enumvalues = {
0: 'RDPCS_PHY_CR_MUX_SEL_FOR_USB',
1: 'RDPCS_PHY_CR_MUX_SEL_FOR_DC',
}
RDPCS_PHY_CR_MUX_SEL_FOR_USB = 0
RDPCS_PHY_CR_MUX_SEL_FOR_DC = 1
RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE'
RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE__enumvalues = {
0: 'RDPCS_SRAM_INIT_NOT_DONE',
1: 'RDPCS_SRAM_INIT_DONE',
}
RDPCS_SRAM_INIT_NOT_DONE = 0
RDPCS_SRAM_INIT_DONE = 1
RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE'
RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE__enumvalues = {
0: 'RDPCS_SRAM_EXT_LD_NOT_DONE',
1: 'RDPCS_SRAM_EXT_LD_DONE',
}
RDPCS_SRAM_EXT_LD_NOT_DONE = 0
RDPCS_SRAM_EXT_LD_DONE = 1
RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL'
RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL__enumvalues = {
0: 'RDPCS_PHY_DP_TX_TERM_CTRL_54',
1: 'RDPCS_PHY_DP_TX_TERM_CTRL_52',
2: 'RDPCS_PHY_DP_TX_TERM_CTRL_50',
3: 'RDPCS_PHY_DP_TX_TERM_CTRL_48',
4: 'RDPCS_PHY_DP_TX_TERM_CTRL_46',
5: 'RDPCS_PHY_DP_TX_TERM_CTRL_44',
6: 'RDPCS_PHY_DP_TX_TERM_CTRL_42',
7: 'RDPCS_PHY_DP_TX_TERM_CTRL_40',
}
RDPCS_PHY_DP_TX_TERM_CTRL_54 = 0
RDPCS_PHY_DP_TX_TERM_CTRL_52 = 1
RDPCS_PHY_DP_TX_TERM_CTRL_50 = 2
RDPCS_PHY_DP_TX_TERM_CTRL_48 = 3
RDPCS_PHY_DP_TX_TERM_CTRL_46 = 4
RDPCS_PHY_DP_TX_TERM_CTRL_44 = 5
RDPCS_PHY_DP_TX_TERM_CTRL_42 = 6
RDPCS_PHY_DP_TX_TERM_CTRL_40 = 7
RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE'
RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE__enumvalues = {
0: 'RRDPCS_PHY_DP_TX_PSTATE_POWER_UP',
1: 'RRDPCS_PHY_DP_TX_PSTATE_HOLD',
2: 'RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF',
3: 'RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN',
}
RRDPCS_PHY_DP_TX_PSTATE_POWER_UP = 0
RRDPCS_PHY_DP_TX_PSTATE_HOLD = 1
RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF = 2
RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN = 3
RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE'
RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE__enumvalues = {
0: 'RDPCS_PHY_DP_TX_RATE',
1: 'RDPCS_PHY_DP_TX_RATE_DIV2',
2: 'RDPCS_PHY_DP_TX_RATE_DIV4',
}
RDPCS_PHY_DP_TX_RATE = 0
RDPCS_PHY_DP_TX_RATE_DIV2 = 1
RDPCS_PHY_DP_TX_RATE_DIV4 = 2
RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH'
RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH__enumvalues = {
0: 'RDPCS_PHY_DP_TX_WIDTH_8',
1: 'RDPCS_PHY_DP_TX_WIDTH_10',
2: 'RDPCS_PHY_DP_TX_WIDTH_16',
3: 'RDPCS_PHY_DP_TX_WIDTH_20',
}
RDPCS_PHY_DP_TX_WIDTH_8 = 0
RDPCS_PHY_DP_TX_WIDTH_10 = 1
RDPCS_PHY_DP_TX_WIDTH_16 = 2
RDPCS_PHY_DP_TX_WIDTH_20 = 3
RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT'
RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT__enumvalues = {
0: 'RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT',
1: 'RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT',
}
RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0
RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT = 1
RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV'
RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__enumvalues = {
0: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1',
1: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2',
2: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3',
3: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8',
4: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16',
}
RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1 = 0
RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2 = 1
RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3 = 2
RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8 = 3
RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16 = 4
RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV'
RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__enumvalues = {
0: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0',
1: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1',
2: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2',
3: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3',
}
RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0
RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 1
RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 2
RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 3
RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV'
RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__enumvalues = {
0: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV',
1: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2',
2: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4',
3: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8',
4: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3',
5: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5',
6: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6',
7: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10',
}
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2 = 1
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4 = 2
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8 = 3
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3 = 4
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5 = 5
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6 = 6
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10 = 7
RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = ctypes.c_uint32 # enum
# values for enumeration 'RDPCS_TEST_CLK_SEL'
RDPCS_TEST_CLK_SEL__enumvalues = {
0: 'RDPCS_TEST_CLK_SEL_NONE',
1: 'RDPCS_TEST_CLK_SEL_CFGCLK',
2: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS',
3: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS',
4: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4',
5: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4',
6: 'RDPCS_TEST_CLK_SEL_SRAMCLK',
7: 'RDPCS_TEST_CLK_SEL_EXT_CR_CLK',
8: 'RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK',
9: 'RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK',
10: 'RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK',
11: 'RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK',
12: 'RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK',
13: 'RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK',
14: 'RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK',
15: 'RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk',
16: 'RDPCS_TEST_CLK_SEL_dtb_out0',
17: 'RDPCS_TEST_CLK_SEL_dtb_out1',
}
RDPCS_TEST_CLK_SEL_NONE = 0
RDPCS_TEST_CLK_SEL_CFGCLK = 1
RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 2
RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 3
RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 4
RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 5
RDPCS_TEST_CLK_SEL_SRAMCLK = 6
RDPCS_TEST_CLK_SEL_EXT_CR_CLK = 7
RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK = 8
RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK = 9
RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK = 10
RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK = 11
RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 12
RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 13
RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK = 14
RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk = 15
RDPCS_TEST_CLK_SEL_dtb_out0 = 16
RDPCS_TEST_CLK_SEL_dtb_out1 = 17
RDPCS_TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CBMode'
CBMode__enumvalues = {
0: 'CB_DISABLE',
1: 'CB_NORMAL',
2: 'CB_ELIMINATE_FAST_CLEAR',
3: 'CB_RESOLVE',
4: 'CB_DECOMPRESS',
5: 'CB_FMASK_DECOMPRESS',
6: 'CB_DCC_DECOMPRESS',
7: 'CB_RESERVED',
}
CB_DISABLE = 0
CB_NORMAL = 1
CB_ELIMINATE_FAST_CLEAR = 2
CB_RESOLVE = 3
CB_DECOMPRESS = 4
CB_FMASK_DECOMPRESS = 5
CB_DCC_DECOMPRESS = 6
CB_RESERVED = 7
CBMode = ctypes.c_uint32 # enum
# values for enumeration 'BlendOp'
BlendOp__enumvalues = {
0: 'BLEND_ZERO',
1: 'BLEND_ONE',
2: 'BLEND_SRC_COLOR',
3: 'BLEND_ONE_MINUS_SRC_COLOR',
4: 'BLEND_SRC_ALPHA',
5: 'BLEND_ONE_MINUS_SRC_ALPHA',
6: 'BLEND_DST_ALPHA',
7: 'BLEND_ONE_MINUS_DST_ALPHA',
8: 'BLEND_DST_COLOR',
9: 'BLEND_ONE_MINUS_DST_COLOR',
10: 'BLEND_SRC_ALPHA_SATURATE',
11: 'BLEND_BOTH_SRC_ALPHA',
12: 'BLEND_BOTH_INV_SRC_ALPHA',
13: 'BLEND_CONSTANT_COLOR',
14: 'BLEND_ONE_MINUS_CONSTANT_COLOR',
15: 'BLEND_SRC1_COLOR',
16: 'BLEND_INV_SRC1_COLOR',
17: 'BLEND_SRC1_ALPHA',
18: 'BLEND_INV_SRC1_ALPHA',
19: 'BLEND_CONSTANT_ALPHA',
20: 'BLEND_ONE_MINUS_CONSTANT_ALPHA',
}
BLEND_ZERO = 0
BLEND_ONE = 1
BLEND_SRC_COLOR = 2
BLEND_ONE_MINUS_SRC_COLOR = 3
BLEND_SRC_ALPHA = 4
BLEND_ONE_MINUS_SRC_ALPHA = 5
BLEND_DST_ALPHA = 6
BLEND_ONE_MINUS_DST_ALPHA = 7
BLEND_DST_COLOR = 8
BLEND_ONE_MINUS_DST_COLOR = 9
BLEND_SRC_ALPHA_SATURATE = 10
BLEND_BOTH_SRC_ALPHA = 11
BLEND_BOTH_INV_SRC_ALPHA = 12
BLEND_CONSTANT_COLOR = 13
BLEND_ONE_MINUS_CONSTANT_COLOR = 14
BLEND_SRC1_COLOR = 15
BLEND_INV_SRC1_COLOR = 16
BLEND_SRC1_ALPHA = 17
BLEND_INV_SRC1_ALPHA = 18
BLEND_CONSTANT_ALPHA = 19
BLEND_ONE_MINUS_CONSTANT_ALPHA = 20
BlendOp = ctypes.c_uint32 # enum
GL__ZERO = BLEND_ZERO # macro
GL__ONE = BLEND_ONE # macro
GL__SRC_COLOR = BLEND_SRC_COLOR # macro
GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro
GL__DST_COLOR = BLEND_DST_COLOR # macro
GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro
GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro
GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro
GL__DST_ALPHA = BLEND_DST_ALPHA # macro
GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro
GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro
GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro
GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro
GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro
GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro
# values for enumeration 'CombFunc'
CombFunc__enumvalues = {
0: 'COMB_DST_PLUS_SRC',
1: 'COMB_SRC_MINUS_DST',
2: 'COMB_MIN_DST_SRC',
3: 'COMB_MAX_DST_SRC',
4: 'COMB_DST_MINUS_SRC',
}
COMB_DST_PLUS_SRC = 0
COMB_SRC_MINUS_DST = 1
COMB_MIN_DST_SRC = 2
COMB_MAX_DST_SRC = 3
COMB_DST_MINUS_SRC = 4
CombFunc = ctypes.c_uint32 # enum
# values for enumeration 'BlendOpt'
BlendOpt__enumvalues = {
0: 'FORCE_OPT_AUTO',
1: 'FORCE_OPT_DISABLE',
2: 'FORCE_OPT_ENABLE_IF_SRC_A_0',
3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0',
4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0',
5: 'FORCE_OPT_ENABLE_IF_SRC_A_1',
6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1',
7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1',
}
FORCE_OPT_AUTO = 0
FORCE_OPT_DISABLE = 1
FORCE_OPT_ENABLE_IF_SRC_A_0 = 2
FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3
FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4
FORCE_OPT_ENABLE_IF_SRC_A_1 = 5
FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6
FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7
BlendOpt = ctypes.c_uint32 # enum
# values for enumeration 'CmaskCode'
CmaskCode__enumvalues = {
0: 'CMASK_CLR00_F0',
1: 'CMASK_CLR00_F1',
2: 'CMASK_CLR00_F2',
3: 'CMASK_CLR00_FX',
4: 'CMASK_CLR01_F0',
5: 'CMASK_CLR01_F1',
6: 'CMASK_CLR01_F2',
7: 'CMASK_CLR01_FX',
8: 'CMASK_CLR10_F0',
9: 'CMASK_CLR10_F1',
10: 'CMASK_CLR10_F2',
11: 'CMASK_CLR10_FX',
12: 'CMASK_CLR11_F0',
13: 'CMASK_CLR11_F1',
14: 'CMASK_CLR11_F2',
15: 'CMASK_CLR11_FX',
}
CMASK_CLR00_F0 = 0
CMASK_CLR00_F1 = 1
CMASK_CLR00_F2 = 2
CMASK_CLR00_FX = 3
CMASK_CLR01_F0 = 4
CMASK_CLR01_F1 = 5
CMASK_CLR01_F2 = 6
CMASK_CLR01_FX = 7
CMASK_CLR10_F0 = 8
CMASK_CLR10_F1 = 9
CMASK_CLR10_F2 = 10
CMASK_CLR10_FX = 11
CMASK_CLR11_F0 = 12
CMASK_CLR11_F1 = 13
CMASK_CLR11_F2 = 14
CMASK_CLR11_FX = 15
CmaskCode = ctypes.c_uint32 # enum
# values for enumeration 'MemArbMode'
MemArbMode__enumvalues = {
0: 'MEM_ARB_MODE_FIXED',
1: 'MEM_ARB_MODE_AGE',
2: 'MEM_ARB_MODE_WEIGHT',
3: 'MEM_ARB_MODE_BOTH',
}
MEM_ARB_MODE_FIXED = 0
MEM_ARB_MODE_AGE = 1
MEM_ARB_MODE_WEIGHT = 2
MEM_ARB_MODE_BOTH = 3
MemArbMode = ctypes.c_uint32 # enum
# values for enumeration 'CBPerfOpFilterSel'
CBPerfOpFilterSel__enumvalues = {
0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY',
1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION',
2: 'CB_PERF_OP_FILTER_SEL_RESOLVE',
3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS',
4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS',
5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR',
}
CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0
CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1
CB_PERF_OP_FILTER_SEL_RESOLVE = 2
CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3
CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4
CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5
CBPerfOpFilterSel = ctypes.c_uint32 # enum
# values for enumeration 'CBPerfClearFilterSel'
CBPerfClearFilterSel__enumvalues = {
0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR',
1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR',
}
CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0
CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1
CBPerfClearFilterSel = ctypes.c_uint32 # enum
# values for enumeration 'CBPerfSel'
CBPerfSel__enumvalues = {
0: 'CB_PERF_SEL_NONE',
1: 'CB_PERF_SEL_BUSY',
2: 'CB_PERF_SEL_CORE_SCLK_VLD',
3: 'CB_PERF_SEL_REG_SCLK0_VLD',
4: 'CB_PERF_SEL_REG_SCLK1_VLD',
5: 'CB_PERF_SEL_DRAWN_QUAD',
6: 'CB_PERF_SEL_DRAWN_PIXEL',
7: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT',
8: 'CB_PERF_SEL_DRAWN_TILE',
9: 'CB_PERF_SEL_DB_CB_TILE_VALID_READY',
10: 'CB_PERF_SEL_DB_CB_TILE_VALID_READYB',
11: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY',
12: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB',
13: 'CB_PERF_SEL_CM_FC_TILE_VALID_READY',
14: 'CB_PERF_SEL_CM_FC_TILE_VALID_READYB',
15: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY',
16: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB',
17: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY',
18: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB',
19: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY',
20: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB',
21: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY',
22: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB',
23: 'CB_PERF_SEL_LQUAD_NO_TILE',
24: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R',
25: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR',
26: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR',
27: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR',
28: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR',
29: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR',
30: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR',
31: 'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT',
32: 'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID',
33: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK',
34: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK',
35: 'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL',
36: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY',
37: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB',
38: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY',
39: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB',
40: 'CB_PERF_SEL_FOP_IN_VALID_READY',
41: 'CB_PERF_SEL_FOP_IN_VALID_READYB',
42: 'CB_PERF_SEL_FOP_IN_VALIDB_READY',
43: 'CB_PERF_SEL_FOP_IN_VALIDB_READYB',
44: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY',
45: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB',
46: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY',
47: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB',
48: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY',
49: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB',
50: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY',
51: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB',
52: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY',
53: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB',
54: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY',
55: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB',
56: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY',
57: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB',
58: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY',
59: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB',
60: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY',
61: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB',
62: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY',
63: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB',
64: 'CB_PERF_SEL_CC_BC_CS_FRAG_VALID',
65: 'CB_PERF_SEL_CM_CACHE_HIT',
66: 'CB_PERF_SEL_CM_CACHE_TAG_MISS',
67: 'CB_PERF_SEL_CM_CACHE_SECTOR_MISS',
68: 'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL',
69: 'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL',
70: 'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL',
71: 'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL',
72: 'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL',
73: 'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL',
74: 'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL',
75: 'CB_PERF_SEL_CM_CACHE_STALL',
76: 'CB_PERF_SEL_CM_CACHE_FLUSH',
77: 'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED',
78: 'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED',
79: 'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED',
80: 'CB_PERF_SEL_FC_CACHE_HIT',
81: 'CB_PERF_SEL_FC_CACHE_TAG_MISS',
82: 'CB_PERF_SEL_FC_CACHE_SECTOR_MISS',
83: 'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL',
84: 'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL',
85: 'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL',
86: 'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL',
87: 'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL',
88: 'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL',
89: 'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL',
90: 'CB_PERF_SEL_FC_CACHE_STALL',
91: 'CB_PERF_SEL_FC_CACHE_FLUSH',
92: 'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED',
93: 'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED',
94: 'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED',
95: 'CB_PERF_SEL_CC_CACHE_HIT',
96: 'CB_PERF_SEL_CC_CACHE_TAG_MISS',
97: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS',
98: 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL',
99: 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL',
100: 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL',
101: 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL',
102: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL',
103: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL',
104: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL',
105: 'CB_PERF_SEL_CC_CACHE_STALL',
106: 'CB_PERF_SEL_CC_CACHE_FLUSH',
107: 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED',
108: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED',
109: 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED',
110: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION',
111: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY',
112: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB',
113: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY',
114: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB',
115: 'CB_PERF_SEL_CM_MC_WRITE_REQUEST',
116: 'CB_PERF_SEL_FC_MC_WRITE_REQUEST',
117: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST',
118: 'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT',
119: 'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT',
120: 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT',
121: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY',
122: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB',
123: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY',
124: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB',
125: 'CB_PERF_SEL_CM_MC_READ_REQUEST',
126: 'CB_PERF_SEL_FC_MC_READ_REQUEST',
127: 'CB_PERF_SEL_CC_MC_READ_REQUEST',
128: 'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT',
129: 'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT',
130: 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT',
131: 'CB_PERF_SEL_CM_TQ_FULL',
132: 'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL',
133: 'CB_PERF_SEL_CM_TQ_FIFO_STUTTER_STALL',
134: 'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL',
135: 'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL',
136: 'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL',
137: 'CB_PERF_SEL_FC_TILE_STUTTER_STALL',
138: 'CB_PERF_SEL_FC_QUAD_STUTTER_STALL',
139: 'CB_PERF_SEL_FC_KEYID_STUTTER_STALL',
140: 'CB_PERF_SEL_FOP_FMASK_RAW_STALL',
141: 'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL',
142: 'CB_PERF_SEL_CC_SF_FULL',
143: 'CB_PERF_SEL_CC_RB_FULL',
144: 'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL',
145: 'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL',
146: 'CB_PERF_SEL_CC_EVENFIFO_STUTTER_STALL',
147: 'CB_PERF_SEL_CC_ODDFIFO_STUTTER_STALL',
148: 'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL',
149: 'CB_PERF_SEL_EVENT',
150: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS',
151: 'CB_PERF_SEL_EVENT_CONTEXT_DONE',
152: 'CB_PERF_SEL_EVENT_CACHE_FLUSH',
153: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT',
154: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT',
155: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS',
156: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META',
157: 'CB_PERF_SEL_CC_SURFACE_SYNC',
158: 'CB_PERF_SEL_CMASK_READ_DATA_0xC',
159: 'CB_PERF_SEL_CMASK_READ_DATA_0xD',
160: 'CB_PERF_SEL_CMASK_READ_DATA_0xE',
161: 'CB_PERF_SEL_CMASK_READ_DATA_0xF',
162: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xC',
163: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xD',
164: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xE',
165: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xF',
166: 'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT',
167: 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT',
168: 'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT',
169: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE',
170: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE',
171: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE',
172: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE',
173: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE',
174: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE',
175: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE',
176: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE',
177: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE',
178: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE',
179: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE',
180: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE',
181: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE',
182: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE',
183: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE',
184: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE',
185: 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT',
186: 'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS',
187: 'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS',
188: 'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS',
189: 'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS',
190: 'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS',
191: 'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS',
192: 'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT',
193: 'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS',
194: 'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS',
195: 'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS',
196: 'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS',
197: 'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS',
198: 'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS',
199: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_0',
200: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_1',
201: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_2',
202: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_3',
203: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_4',
204: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_5',
205: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_6',
206: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_7',
207: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0',
208: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1',
209: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2',
210: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3',
211: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4',
212: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5',
213: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6',
214: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7',
215: 'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST',
216: 'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS',
217: 'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS',
218: 'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED',
219: 'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED',
220: 'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED',
221: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST',
222: 'CB_PERF_SEL_DRAWN_BUSY',
223: 'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY',
224: 'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY',
225: 'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY',
226: 'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY',
227: 'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED',
228: 'CB_PERF_SEL_FC_SEQUENCER_CLEAR',
229: 'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR',
230: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS',
231: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE',
232: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC',
233: 'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL',
234: 'CB_PERF_SEL_FC_DOC_IS_STALLED',
235: 'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED',
236: 'CB_PERF_SEL_FC_DOC_MRTS_COMBINED',
237: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS',
238: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT',
239: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS',
240: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT',
241: 'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL',
242: 'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR',
243: 'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS',
244: 'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS',
245: 'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS',
246: 'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS',
247: 'CB_PERF_SEL_FC_DCC_CACHE_HIT',
248: 'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS',
249: 'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS',
250: 'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL',
251: 'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL',
252: 'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL',
253: 'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL',
254: 'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL',
255: 'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL',
256: 'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL',
257: 'CB_PERF_SEL_FC_DCC_CACHE_STALL',
258: 'CB_PERF_SEL_FC_DCC_CACHE_FLUSH',
259: 'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED',
260: 'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED',
261: 'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED',
262: 'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT',
263: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST',
264: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT',
265: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST',
266: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT',
267: 'CB_PERF_SEL_CC_DCC_RDREQ_STALL',
268: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN',
269: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT',
270: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN',
271: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT',
272: 'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR',
273: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1',
274: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2',
275: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1',
276: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1',
277: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1',
278: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2',
279: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1',
280: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2',
281: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1',
282: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1',
283: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2',
284: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2',
285: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2',
286: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2',
287: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1',
288: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1',
289: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2',
290: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3',
291: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4',
292: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1',
293: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2',
294: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3',
295: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4',
296: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1',
297: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2',
298: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3',
299: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4',
300: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1',
301: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2',
302: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3',
303: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1',
304: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2',
305: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3',
306: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4',
307: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1',
308: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2',
309: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3',
310: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4',
311: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1',
312: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2',
313: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3',
314: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4',
315: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1',
316: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2',
317: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3',
318: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1',
319: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1',
320: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1',
321: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1',
322: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1',
323: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1',
324: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1',
325: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1',
326: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2',
327: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2',
328: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2',
329: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2',
330: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2',
331: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2',
332: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2',
333: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1',
334: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1',
335: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1',
336: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1',
337: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2',
338: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2',
339: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2',
340: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2',
341: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2',
342: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2',
343: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2',
344: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1',
345: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1',
346: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1',
347: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1',
348: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1',
349: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2',
350: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3',
351: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4',
352: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5',
353: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6',
354: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0',
355: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1',
356: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1',
357: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2',
358: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3',
359: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4',
360: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5',
361: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0',
362: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1',
363: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1',
364: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1',
365: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1',
366: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1',
367: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1',
368: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1',
369: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1',
370: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1',
371: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2',
372: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2',
373: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2',
374: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2',
375: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2',
376: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2',
377: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2',
378: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1',
379: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2',
380: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3',
381: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4',
382: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5',
383: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6',
384: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7',
385: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED',
386: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1',
387: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1',
388: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2',
389: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3',
390: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1',
391: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2',
392: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3',
393: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4',
394: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5',
395: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1',
396: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2',
397: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3',
398: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4',
399: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5',
400: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6',
401: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7',
402: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH',
403: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT',
404: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT',
405: 'CB_PERF_SEL_RBP_SPLIT_MICROTILE',
406: 'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK',
407: 'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK',
408: 'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING',
409: 'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS',
410: 'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD',
411: 'CB_PERF_SEL_NACK_CM_READ',
412: 'CB_PERF_SEL_NACK_CM_WRITE',
413: 'CB_PERF_SEL_NACK_FC_READ',
414: 'CB_PERF_SEL_NACK_FC_WRITE',
415: 'CB_PERF_SEL_NACK_DC_READ',
416: 'CB_PERF_SEL_NACK_DC_WRITE',
417: 'CB_PERF_SEL_NACK_CC_READ',
418: 'CB_PERF_SEL_NACK_CC_WRITE',
419: 'CB_PERF_SEL_CM_MC_EARLY_WRITE_RETURN',
420: 'CB_PERF_SEL_FC_MC_EARLY_WRITE_RETURN',
421: 'CB_PERF_SEL_DC_MC_EARLY_WRITE_RETURN',
422: 'CB_PERF_SEL_CC_MC_EARLY_WRITE_RETURN',
423: 'CB_PERF_SEL_CM_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT',
424: 'CB_PERF_SEL_FC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT',
425: 'CB_PERF_SEL_DC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT',
426: 'CB_PERF_SEL_CC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT',
427: 'CB_PERF_SEL_CM_MC_WRITE_ACK64B',
428: 'CB_PERF_SEL_FC_MC_WRITE_ACK64B',
429: 'CB_PERF_SEL_DC_MC_WRITE_ACK64B',
430: 'CB_PERF_SEL_CC_MC_WRITE_ACK64B',
431: 'CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS',
432: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_DB_DATA_TS',
433: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_PIXEL_DATA',
434: 'CB_PERF_SEL_DB_CB_TILE_TILENOTEVENT',
435: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32BPP_8PIX',
436: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_UNSIGNED_8PIX',
437: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_SIGNED_8PIX',
438: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_FLOAT_8PIX',
439: 'CB_PERF_SEL_MERGE_PIXELS_WITH_BLEND_ENABLED',
440: 'CB_PERF_SEL_DB_CB_CONTEXT_DONE',
441: 'CB_PERF_SEL_DB_CB_EOP_DONE',
442: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST_PARTIAL',
443: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD',
}
CB_PERF_SEL_NONE = 0
CB_PERF_SEL_BUSY = 1
CB_PERF_SEL_CORE_SCLK_VLD = 2
CB_PERF_SEL_REG_SCLK0_VLD = 3
CB_PERF_SEL_REG_SCLK1_VLD = 4
CB_PERF_SEL_DRAWN_QUAD = 5
CB_PERF_SEL_DRAWN_PIXEL = 6
CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 7
CB_PERF_SEL_DRAWN_TILE = 8
CB_PERF_SEL_DB_CB_TILE_VALID_READY = 9
CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 10
CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 11
CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 12
CB_PERF_SEL_CM_FC_TILE_VALID_READY = 13
CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 14
CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 15
CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 16
CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 17
CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 18
CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 19
CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 20
CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 21
CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 22
CB_PERF_SEL_LQUAD_NO_TILE = 23
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 24
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 25
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 26
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 27
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 28
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 29
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 30
CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 31
CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 32
CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 33
CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 34
CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 35
CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 36
CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 37
CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 38
CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 39
CB_PERF_SEL_FOP_IN_VALID_READY = 40
CB_PERF_SEL_FOP_IN_VALID_READYB = 41
CB_PERF_SEL_FOP_IN_VALIDB_READY = 42
CB_PERF_SEL_FOP_IN_VALIDB_READYB = 43
CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 44
CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 45
CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 46
CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 47
CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 48
CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 49
CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 50
CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 51
CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 52
CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 53
CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 54
CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 55
CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 56
CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 57
CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 58
CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 59
CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 60
CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 61
CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 62
CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 63
CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 64
CB_PERF_SEL_CM_CACHE_HIT = 65
CB_PERF_SEL_CM_CACHE_TAG_MISS = 66
CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 67
CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 68
CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 69
CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 70
CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 71
CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 72
CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 73
CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 74
CB_PERF_SEL_CM_CACHE_STALL = 75
CB_PERF_SEL_CM_CACHE_FLUSH = 76
CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 77
CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 78
CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 79
CB_PERF_SEL_FC_CACHE_HIT = 80
CB_PERF_SEL_FC_CACHE_TAG_MISS = 81
CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 82
CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 83
CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 84
CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 85
CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 86
CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 87
CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 88
CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 89
CB_PERF_SEL_FC_CACHE_STALL = 90
CB_PERF_SEL_FC_CACHE_FLUSH = 91
CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 92
CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 93
CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 94
CB_PERF_SEL_CC_CACHE_HIT = 95
CB_PERF_SEL_CC_CACHE_TAG_MISS = 96
CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 97
CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 98
CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 99
CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 100
CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 101
CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 102
CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 103
CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 104
CB_PERF_SEL_CC_CACHE_STALL = 105
CB_PERF_SEL_CC_CACHE_FLUSH = 106
CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 107
CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 108
CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 109
CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 110
CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 111
CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 112
CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 113
CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 114
CB_PERF_SEL_CM_MC_WRITE_REQUEST = 115
CB_PERF_SEL_FC_MC_WRITE_REQUEST = 116
CB_PERF_SEL_CC_MC_WRITE_REQUEST = 117
CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 118
CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 119
CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 120
CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 121
CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 122
CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 123
CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 124
CB_PERF_SEL_CM_MC_READ_REQUEST = 125
CB_PERF_SEL_FC_MC_READ_REQUEST = 126
CB_PERF_SEL_CC_MC_READ_REQUEST = 127
CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 128
CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 129
CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 130
CB_PERF_SEL_CM_TQ_FULL = 131
CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 132
CB_PERF_SEL_CM_TQ_FIFO_STUTTER_STALL = 133
CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 134
CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 135
CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 136
CB_PERF_SEL_FC_TILE_STUTTER_STALL = 137
CB_PERF_SEL_FC_QUAD_STUTTER_STALL = 138
CB_PERF_SEL_FC_KEYID_STUTTER_STALL = 139
CB_PERF_SEL_FOP_FMASK_RAW_STALL = 140
CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 141
CB_PERF_SEL_CC_SF_FULL = 142
CB_PERF_SEL_CC_RB_FULL = 143
CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 144
CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 145
CB_PERF_SEL_CC_EVENFIFO_STUTTER_STALL = 146
CB_PERF_SEL_CC_ODDFIFO_STUTTER_STALL = 147
CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 148
CB_PERF_SEL_EVENT = 149
CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 150
CB_PERF_SEL_EVENT_CONTEXT_DONE = 151
CB_PERF_SEL_EVENT_CACHE_FLUSH = 152
CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 153
CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 154
CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 155
CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 156
CB_PERF_SEL_CC_SURFACE_SYNC = 157
CB_PERF_SEL_CMASK_READ_DATA_0xC = 158
CB_PERF_SEL_CMASK_READ_DATA_0xD = 159
CB_PERF_SEL_CMASK_READ_DATA_0xE = 160
CB_PERF_SEL_CMASK_READ_DATA_0xF = 161
CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 162
CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 163
CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 164
CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 165
CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 166
CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 167
CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 168
CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 169
CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 170
CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 171
CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 172
CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 173
CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 174
CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 175
CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 176
CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 177
CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 178
CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 179
CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 180
CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 181
CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 182
CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 183
CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 184
CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 185
CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 186
CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 187
CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 188
CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 189
CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 190
CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 191
CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 192
CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 193
CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 194
CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 195
CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 196
CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 197
CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 198
CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 199
CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 200
CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 201
CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 202
CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 203
CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 204
CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 205
CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 206
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 207
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 208
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 209
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 210
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 211
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 212
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 213
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 214
CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 215
CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 216
CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 217
CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 218
CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 219
CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 220
CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 221
CB_PERF_SEL_DRAWN_BUSY = 222
CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 223
CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 224
CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 225
CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 226
CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 227
CB_PERF_SEL_FC_SEQUENCER_CLEAR = 228
CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 229
CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 230
CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 231
CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 232
CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 233
CB_PERF_SEL_FC_DOC_IS_STALLED = 234
CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 235
CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 236
CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 237
CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 238
CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 239
CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 240
CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 241
CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 242
CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 243
CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 244
CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 245
CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 246
CB_PERF_SEL_FC_DCC_CACHE_HIT = 247
CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 248
CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 249
CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 250
CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 251
CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 252
CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 253
CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 254
CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 255
CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 256
CB_PERF_SEL_FC_DCC_CACHE_STALL = 257
CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 258
CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 259
CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 260
CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 261
CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 262
CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 263
CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 264
CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 265
CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 266
CB_PERF_SEL_CC_DCC_RDREQ_STALL = 267
CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 268
CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 269
CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 270
CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 271
CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 272
CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 273
CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 274
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 275
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 276
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 277
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 278
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 279
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 280
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 281
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 282
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 283
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 284
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 285
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 286
CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 287
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 288
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 289
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 290
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 291
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 292
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 293
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 294
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 295
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 296
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 297
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 298
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 299
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 300
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 301
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 302
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 303
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 304
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 305
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 306
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 307
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 308
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 309
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 310
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 311
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 312
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 313
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 314
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 315
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 316
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 317
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 318
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 319
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 320
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 321
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 322
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 323
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 324
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 325
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 326
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 327
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 328
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 329
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 330
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 331
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 332
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 333
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 334
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 335
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 336
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 337
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 338
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 339
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 340
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 341
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 342
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 343
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 344
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 345
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 346
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 347
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 348
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 349
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 350
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 351
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 352
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 353
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 354
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 355
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 356
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 357
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 358
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 359
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 360
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 361
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 362
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 363
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 364
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 365
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 366
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 367
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 368
CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 369
CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 370
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 371
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 372
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 373
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 374
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 375
CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 376
CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 377
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 378
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 379
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 380
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 381
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 382
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 383
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 384
CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 385
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 386
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 387
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 388
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 389
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 390
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 391
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 392
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 393
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 394
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 395
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 396
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 397
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 398
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 399
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 400
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 401
CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 402
CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 403
CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 404
CB_PERF_SEL_RBP_SPLIT_MICROTILE = 405
CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 406
CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 407
CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 408
CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 409
CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 410
CB_PERF_SEL_NACK_CM_READ = 411
CB_PERF_SEL_NACK_CM_WRITE = 412
CB_PERF_SEL_NACK_FC_READ = 413
CB_PERF_SEL_NACK_FC_WRITE = 414
CB_PERF_SEL_NACK_DC_READ = 415
CB_PERF_SEL_NACK_DC_WRITE = 416
CB_PERF_SEL_NACK_CC_READ = 417
CB_PERF_SEL_NACK_CC_WRITE = 418
CB_PERF_SEL_CM_MC_EARLY_WRITE_RETURN = 419
CB_PERF_SEL_FC_MC_EARLY_WRITE_RETURN = 420
CB_PERF_SEL_DC_MC_EARLY_WRITE_RETURN = 421
CB_PERF_SEL_CC_MC_EARLY_WRITE_RETURN = 422
CB_PERF_SEL_CM_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 423
CB_PERF_SEL_FC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 424
CB_PERF_SEL_DC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 425
CB_PERF_SEL_CC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 426
CB_PERF_SEL_CM_MC_WRITE_ACK64B = 427
CB_PERF_SEL_FC_MC_WRITE_ACK64B = 428
CB_PERF_SEL_DC_MC_WRITE_ACK64B = 429
CB_PERF_SEL_CC_MC_WRITE_ACK64B = 430
CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS = 431
CB_PERF_SEL_EVENT_FLUSH_AND_INV_DB_DATA_TS = 432
CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_PIXEL_DATA = 433
CB_PERF_SEL_DB_CB_TILE_TILENOTEVENT = 434
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32BPP_8PIX = 435
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_UNSIGNED_8PIX = 436
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_SIGNED_8PIX = 437
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_FLOAT_8PIX = 438
CB_PERF_SEL_MERGE_PIXELS_WITH_BLEND_ENABLED = 439
CB_PERF_SEL_DB_CB_CONTEXT_DONE = 440
CB_PERF_SEL_DB_CB_EOP_DONE = 441
CB_PERF_SEL_CC_MC_WRITE_REQUEST_PARTIAL = 442
CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD = 443
CBPerfSel = ctypes.c_uint32 # enum
# values for enumeration 'CmaskAddr'
CmaskAddr__enumvalues = {
0: 'CMASK_ADDR_TILED',
1: 'CMASK_ADDR_LINEAR',
2: 'CMASK_ADDR_COMPATIBLE',
}
CMASK_ADDR_TILED = 0
CMASK_ADDR_LINEAR = 1
CMASK_ADDR_COMPATIBLE = 2
CmaskAddr = ctypes.c_uint32 # enum
# values for enumeration 'SourceFormat'
SourceFormat__enumvalues = {
0: 'EXPORT_4C_32BPC',
1: 'EXPORT_4C_16BPC',
2: 'EXPORT_2C_32BPC_GR',
3: 'EXPORT_2C_32BPC_AR',
}
EXPORT_4C_32BPC = 0
EXPORT_4C_16BPC = 1
EXPORT_2C_32BPC_GR = 2
EXPORT_2C_32BPC_AR = 3
SourceFormat = ctypes.c_uint32 # enum
# values for enumeration 'TC_OP_MASKS'
TC_OP_MASKS__enumvalues = {
8: 'TC_OP_MASK_FLUSH_DENROM',
32: 'TC_OP_MASK_64',
64: 'TC_OP_MASK_NO_RTN',
}
TC_OP_MASK_FLUSH_DENROM = 8
TC_OP_MASK_64 = 32
TC_OP_MASK_NO_RTN = 64
TC_OP_MASKS = ctypes.c_uint32 # enum
# values for enumeration 'TC_OP'
TC_OP__enumvalues = {
0: 'TC_OP_READ',
1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32',
2: 'TC_OP_ATOMIC_FMIN_RTN_32',
3: 'TC_OP_ATOMIC_FMAX_RTN_32',
4: 'TC_OP_RESERVED_FOP_RTN_32_0',
5: 'TC_OP_RESERVED_FOP_RTN_32_1',
6: 'TC_OP_RESERVED_FOP_RTN_32_2',
7: 'TC_OP_ATOMIC_SWAP_RTN_32',
8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32',
9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32',
10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32',
11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32',
12: 'TC_OP_PROBE_FILTER',
13: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1',
14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2',
15: 'TC_OP_ATOMIC_ADD_RTN_32',
16: 'TC_OP_ATOMIC_SUB_RTN_32',
17: 'TC_OP_ATOMIC_SMIN_RTN_32',
18: 'TC_OP_ATOMIC_UMIN_RTN_32',
19: 'TC_OP_ATOMIC_SMAX_RTN_32',
20: 'TC_OP_ATOMIC_UMAX_RTN_32',
21: 'TC_OP_ATOMIC_AND_RTN_32',
22: 'TC_OP_ATOMIC_OR_RTN_32',
23: 'TC_OP_ATOMIC_XOR_RTN_32',
24: 'TC_OP_ATOMIC_INC_RTN_32',
25: 'TC_OP_ATOMIC_DEC_RTN_32',
26: 'TC_OP_WBINVL1_VOL',
27: 'TC_OP_WBINVL1_SD',
28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0',
29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1',
30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2',
31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3',
32: 'TC_OP_WRITE',
33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64',
34: 'TC_OP_ATOMIC_FMIN_RTN_64',
35: 'TC_OP_ATOMIC_FMAX_RTN_64',
36: 'TC_OP_RESERVED_FOP_RTN_64_0',
37: 'TC_OP_RESERVED_FOP_RTN_64_1',
38: 'TC_OP_RESERVED_FOP_RTN_64_2',
39: 'TC_OP_ATOMIC_SWAP_RTN_64',
40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64',
41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64',
42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64',
43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64',
44: 'TC_OP_WBINVL2_SD',
45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0',
46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1',
47: 'TC_OP_ATOMIC_ADD_RTN_64',
48: 'TC_OP_ATOMIC_SUB_RTN_64',
49: 'TC_OP_ATOMIC_SMIN_RTN_64',
50: 'TC_OP_ATOMIC_UMIN_RTN_64',
51: 'TC_OP_ATOMIC_SMAX_RTN_64',
52: 'TC_OP_ATOMIC_UMAX_RTN_64',
53: 'TC_OP_ATOMIC_AND_RTN_64',
54: 'TC_OP_ATOMIC_OR_RTN_64',
55: 'TC_OP_ATOMIC_XOR_RTN_64',
56: 'TC_OP_ATOMIC_INC_RTN_64',
57: 'TC_OP_ATOMIC_DEC_RTN_64',
58: 'TC_OP_WBL2_NC',
59: 'TC_OP_WBL2_WC',
60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1',
61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2',
62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3',
63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4',
64: 'TC_OP_WBINVL1',
65: 'TC_OP_ATOMIC_FCMPSWAP_32',
66: 'TC_OP_ATOMIC_FMIN_32',
67: 'TC_OP_ATOMIC_FMAX_32',
68: 'TC_OP_RESERVED_FOP_32_0',
69: 'TC_OP_RESERVED_FOP_32_1',
70: 'TC_OP_RESERVED_FOP_32_2',
71: 'TC_OP_ATOMIC_SWAP_32',
72: 'TC_OP_ATOMIC_CMPSWAP_32',
73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32',
74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32',
75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32',
76: 'TC_OP_INV_METADATA',
77: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1',
78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2',
79: 'TC_OP_ATOMIC_ADD_32',
80: 'TC_OP_ATOMIC_SUB_32',
81: 'TC_OP_ATOMIC_SMIN_32',
82: 'TC_OP_ATOMIC_UMIN_32',
83: 'TC_OP_ATOMIC_SMAX_32',
84: 'TC_OP_ATOMIC_UMAX_32',
85: 'TC_OP_ATOMIC_AND_32',
86: 'TC_OP_ATOMIC_OR_32',
87: 'TC_OP_ATOMIC_XOR_32',
88: 'TC_OP_ATOMIC_INC_32',
89: 'TC_OP_ATOMIC_DEC_32',
90: 'TC_OP_INVL2_NC',
91: 'TC_OP_NOP_RTN0',
92: 'TC_OP_RESERVED_NON_FLOAT_32_1',
93: 'TC_OP_RESERVED_NON_FLOAT_32_2',
94: 'TC_OP_RESERVED_NON_FLOAT_32_3',
95: 'TC_OP_RESERVED_NON_FLOAT_32_4',
96: 'TC_OP_WBINVL2',
97: 'TC_OP_ATOMIC_FCMPSWAP_64',
98: 'TC_OP_ATOMIC_FMIN_64',
99: 'TC_OP_ATOMIC_FMAX_64',
100: 'TC_OP_RESERVED_FOP_64_0',
101: 'TC_OP_RESERVED_FOP_64_1',
102: 'TC_OP_RESERVED_FOP_64_2',
103: 'TC_OP_ATOMIC_SWAP_64',
104: 'TC_OP_ATOMIC_CMPSWAP_64',
105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64',
106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64',
107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64',
108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0',
109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1',
110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2',
111: 'TC_OP_ATOMIC_ADD_64',
112: 'TC_OP_ATOMIC_SUB_64',
113: 'TC_OP_ATOMIC_SMIN_64',
114: 'TC_OP_ATOMIC_UMIN_64',
115: 'TC_OP_ATOMIC_SMAX_64',
116: 'TC_OP_ATOMIC_UMAX_64',
117: 'TC_OP_ATOMIC_AND_64',
118: 'TC_OP_ATOMIC_OR_64',
119: 'TC_OP_ATOMIC_XOR_64',
120: 'TC_OP_ATOMIC_INC_64',
121: 'TC_OP_ATOMIC_DEC_64',
122: 'TC_OP_WBINVL2_NC',
123: 'TC_OP_NOP_ACK',
124: 'TC_OP_RESERVED_NON_FLOAT_64_1',
125: 'TC_OP_RESERVED_NON_FLOAT_64_2',
126: 'TC_OP_RESERVED_NON_FLOAT_64_3',
127: 'TC_OP_RESERVED_NON_FLOAT_64_4',
}
TC_OP_READ = 0
TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1
TC_OP_ATOMIC_FMIN_RTN_32 = 2
TC_OP_ATOMIC_FMAX_RTN_32 = 3
TC_OP_RESERVED_FOP_RTN_32_0 = 4
TC_OP_RESERVED_FOP_RTN_32_1 = 5
TC_OP_RESERVED_FOP_RTN_32_2 = 6
TC_OP_ATOMIC_SWAP_RTN_32 = 7
TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11
TC_OP_PROBE_FILTER = 12
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 13
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14
TC_OP_ATOMIC_ADD_RTN_32 = 15
TC_OP_ATOMIC_SUB_RTN_32 = 16
TC_OP_ATOMIC_SMIN_RTN_32 = 17
TC_OP_ATOMIC_UMIN_RTN_32 = 18
TC_OP_ATOMIC_SMAX_RTN_32 = 19
TC_OP_ATOMIC_UMAX_RTN_32 = 20
TC_OP_ATOMIC_AND_RTN_32 = 21
TC_OP_ATOMIC_OR_RTN_32 = 22
TC_OP_ATOMIC_XOR_RTN_32 = 23
TC_OP_ATOMIC_INC_RTN_32 = 24
TC_OP_ATOMIC_DEC_RTN_32 = 25
TC_OP_WBINVL1_VOL = 26
TC_OP_WBINVL1_SD = 27
TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28
TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29
TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30
TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31
TC_OP_WRITE = 32
TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33
TC_OP_ATOMIC_FMIN_RTN_64 = 34
TC_OP_ATOMIC_FMAX_RTN_64 = 35
TC_OP_RESERVED_FOP_RTN_64_0 = 36
TC_OP_RESERVED_FOP_RTN_64_1 = 37
TC_OP_RESERVED_FOP_RTN_64_2 = 38
TC_OP_ATOMIC_SWAP_RTN_64 = 39
TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43
TC_OP_WBINVL2_SD = 44
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46
TC_OP_ATOMIC_ADD_RTN_64 = 47
TC_OP_ATOMIC_SUB_RTN_64 = 48
TC_OP_ATOMIC_SMIN_RTN_64 = 49
TC_OP_ATOMIC_UMIN_RTN_64 = 50
TC_OP_ATOMIC_SMAX_RTN_64 = 51
TC_OP_ATOMIC_UMAX_RTN_64 = 52
TC_OP_ATOMIC_AND_RTN_64 = 53
TC_OP_ATOMIC_OR_RTN_64 = 54
TC_OP_ATOMIC_XOR_RTN_64 = 55
TC_OP_ATOMIC_INC_RTN_64 = 56
TC_OP_ATOMIC_DEC_RTN_64 = 57
TC_OP_WBL2_NC = 58
TC_OP_WBL2_WC = 59
TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60
TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61
TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62
TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63
TC_OP_WBINVL1 = 64
TC_OP_ATOMIC_FCMPSWAP_32 = 65
TC_OP_ATOMIC_FMIN_32 = 66
TC_OP_ATOMIC_FMAX_32 = 67
TC_OP_RESERVED_FOP_32_0 = 68
TC_OP_RESERVED_FOP_32_1 = 69
TC_OP_RESERVED_FOP_32_2 = 70
TC_OP_ATOMIC_SWAP_32 = 71
TC_OP_ATOMIC_CMPSWAP_32 = 72
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75
TC_OP_INV_METADATA = 76
TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 77
TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78
TC_OP_ATOMIC_ADD_32 = 79
TC_OP_ATOMIC_SUB_32 = 80
TC_OP_ATOMIC_SMIN_32 = 81
TC_OP_ATOMIC_UMIN_32 = 82
TC_OP_ATOMIC_SMAX_32 = 83
TC_OP_ATOMIC_UMAX_32 = 84
TC_OP_ATOMIC_AND_32 = 85
TC_OP_ATOMIC_OR_32 = 86
TC_OP_ATOMIC_XOR_32 = 87
TC_OP_ATOMIC_INC_32 = 88
TC_OP_ATOMIC_DEC_32 = 89
TC_OP_INVL2_NC = 90
TC_OP_NOP_RTN0 = 91
TC_OP_RESERVED_NON_FLOAT_32_1 = 92
TC_OP_RESERVED_NON_FLOAT_32_2 = 93
TC_OP_RESERVED_NON_FLOAT_32_3 = 94
TC_OP_RESERVED_NON_FLOAT_32_4 = 95
TC_OP_WBINVL2 = 96
TC_OP_ATOMIC_FCMPSWAP_64 = 97
TC_OP_ATOMIC_FMIN_64 = 98
TC_OP_ATOMIC_FMAX_64 = 99
TC_OP_RESERVED_FOP_64_0 = 100
TC_OP_RESERVED_FOP_64_1 = 101
TC_OP_RESERVED_FOP_64_2 = 102
TC_OP_ATOMIC_SWAP_64 = 103
TC_OP_ATOMIC_CMPSWAP_64 = 104
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110
TC_OP_ATOMIC_ADD_64 = 111
TC_OP_ATOMIC_SUB_64 = 112
TC_OP_ATOMIC_SMIN_64 = 113
TC_OP_ATOMIC_UMIN_64 = 114
TC_OP_ATOMIC_SMAX_64 = 115
TC_OP_ATOMIC_UMAX_64 = 116
TC_OP_ATOMIC_AND_64 = 117
TC_OP_ATOMIC_OR_64 = 118
TC_OP_ATOMIC_XOR_64 = 119
TC_OP_ATOMIC_INC_64 = 120
TC_OP_ATOMIC_DEC_64 = 121
TC_OP_WBINVL2_NC = 122
TC_OP_NOP_ACK = 123
TC_OP_RESERVED_NON_FLOAT_64_1 = 124
TC_OP_RESERVED_NON_FLOAT_64_2 = 125
TC_OP_RESERVED_NON_FLOAT_64_3 = 126
TC_OP_RESERVED_NON_FLOAT_64_4 = 127
TC_OP = ctypes.c_uint32 # enum
# values for enumeration 'TC_NACKS'
TC_NACKS__enumvalues = {
0: 'TC_NACK_NO_FAULT',
1: 'TC_NACK_PAGE_FAULT',
2: 'TC_NACK_PROTECTION_FAULT',
3: 'TC_NACK_DATA_ERROR',
}
TC_NACK_NO_FAULT = 0
TC_NACK_PAGE_FAULT = 1
TC_NACK_PROTECTION_FAULT = 2
TC_NACK_DATA_ERROR = 3
TC_NACKS = ctypes.c_uint32 # enum
# values for enumeration 'TC_EA_CID'
TC_EA_CID__enumvalues = {
0: 'TC_EA_CID_RT',
1: 'TC_EA_CID_FMASK',
2: 'TC_EA_CID_DCC',
3: 'TC_EA_CID_TCPMETA',
4: 'TC_EA_CID_Z',
5: 'TC_EA_CID_STENCIL',
6: 'TC_EA_CID_HTILE',
7: 'TC_EA_CID_MISC',
8: 'TC_EA_CID_TCP',
9: 'TC_EA_CID_SQC',
10: 'TC_EA_CID_CPF',
11: 'TC_EA_CID_CPG',
12: 'TC_EA_CID_IA',
13: 'TC_EA_CID_WD',
14: 'TC_EA_CID_PA',
15: 'TC_EA_CID_UTCL2_TPI',
}
TC_EA_CID_RT = 0
TC_EA_CID_FMASK = 1
TC_EA_CID_DCC = 2
TC_EA_CID_TCPMETA = 3
TC_EA_CID_Z = 4
TC_EA_CID_STENCIL = 5
TC_EA_CID_HTILE = 6
TC_EA_CID_MISC = 7
TC_EA_CID_TCP = 8
TC_EA_CID_SQC = 9
TC_EA_CID_CPF = 10
TC_EA_CID_CPG = 11
TC_EA_CID_IA = 12
TC_EA_CID_WD = 13
TC_EA_CID_PA = 14
TC_EA_CID_UTCL2_TPI = 15
TC_EA_CID = ctypes.c_uint32 # enum
# values for enumeration 'GL2_OP_MASKS'
GL2_OP_MASKS__enumvalues = {
8: 'GL2_OP_MASK_FLUSH_DENROM',
32: 'GL2_OP_MASK_64',
64: 'GL2_OP_MASK_NO_RTN',
}
GL2_OP_MASK_FLUSH_DENROM = 8
GL2_OP_MASK_64 = 32
GL2_OP_MASK_NO_RTN = 64
GL2_OP_MASKS = ctypes.c_uint32 # enum
# values for enumeration 'GL2_OP'
GL2_OP__enumvalues = {
0: 'GL2_OP_READ',
1: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32',
2: 'GL2_OP_ATOMIC_FMIN_RTN_32',
3: 'GL2_OP_ATOMIC_FMAX_RTN_32',
7: 'GL2_OP_ATOMIC_SWAP_RTN_32',
8: 'GL2_OP_ATOMIC_CMPSWAP_RTN_32',
9: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32',
10: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32',
11: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32',
12: 'GL2_OP_PROBE_FILTER',
13: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1',
14: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2',
15: 'GL2_OP_ATOMIC_ADD_RTN_32',
16: 'GL2_OP_ATOMIC_SUB_RTN_32',
17: 'GL2_OP_ATOMIC_SMIN_RTN_32',
18: 'GL2_OP_ATOMIC_UMIN_RTN_32',
19: 'GL2_OP_ATOMIC_SMAX_RTN_32',
20: 'GL2_OP_ATOMIC_UMAX_RTN_32',
21: 'GL2_OP_ATOMIC_AND_RTN_32',
22: 'GL2_OP_ATOMIC_OR_RTN_32',
23: 'GL2_OP_ATOMIC_XOR_RTN_32',
24: 'GL2_OP_ATOMIC_INC_RTN_32',
25: 'GL2_OP_ATOMIC_DEC_RTN_32',
32: 'GL2_OP_WRITE',
33: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64',
34: 'GL2_OP_ATOMIC_FMIN_RTN_64',
35: 'GL2_OP_ATOMIC_FMAX_RTN_64',
39: 'GL2_OP_ATOMIC_SWAP_RTN_64',
40: 'GL2_OP_ATOMIC_CMPSWAP_RTN_64',
41: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64',
42: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64',
43: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64',
47: 'GL2_OP_ATOMIC_ADD_RTN_64',
48: 'GL2_OP_ATOMIC_SUB_RTN_64',
49: 'GL2_OP_ATOMIC_SMIN_RTN_64',
50: 'GL2_OP_ATOMIC_UMIN_RTN_64',
51: 'GL2_OP_ATOMIC_SMAX_RTN_64',
52: 'GL2_OP_ATOMIC_UMAX_RTN_64',
53: 'GL2_OP_ATOMIC_AND_RTN_64',
54: 'GL2_OP_ATOMIC_OR_RTN_64',
55: 'GL2_OP_ATOMIC_XOR_RTN_64',
56: 'GL2_OP_ATOMIC_INC_RTN_64',
57: 'GL2_OP_ATOMIC_DEC_RTN_64',
64: 'GL2_OP_GL1_INV',
65: 'GL2_OP_ATOMIC_FCMPSWAP_32',
66: 'GL2_OP_ATOMIC_FMIN_32',
67: 'GL2_OP_ATOMIC_FMAX_32',
71: 'GL2_OP_ATOMIC_SWAP_32',
72: 'GL2_OP_ATOMIC_CMPSWAP_32',
73: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32',
74: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32',
75: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32',
79: 'GL2_OP_ATOMIC_ADD_32',
80: 'GL2_OP_ATOMIC_SUB_32',
81: 'GL2_OP_ATOMIC_SMIN_32',
82: 'GL2_OP_ATOMIC_UMIN_32',
83: 'GL2_OP_ATOMIC_SMAX_32',
84: 'GL2_OP_ATOMIC_UMAX_32',
85: 'GL2_OP_ATOMIC_AND_32',
86: 'GL2_OP_ATOMIC_OR_32',
87: 'GL2_OP_ATOMIC_XOR_32',
88: 'GL2_OP_ATOMIC_INC_32',
89: 'GL2_OP_ATOMIC_DEC_32',
91: 'GL2_OP_NOP_RTN0',
97: 'GL2_OP_ATOMIC_FCMPSWAP_64',
98: 'GL2_OP_ATOMIC_FMIN_64',
99: 'GL2_OP_ATOMIC_FMAX_64',
103: 'GL2_OP_ATOMIC_SWAP_64',
104: 'GL2_OP_ATOMIC_CMPSWAP_64',
105: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64',
106: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64',
107: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64',
111: 'GL2_OP_ATOMIC_ADD_64',
112: 'GL2_OP_ATOMIC_SUB_64',
113: 'GL2_OP_ATOMIC_SMIN_64',
114: 'GL2_OP_ATOMIC_UMIN_64',
115: 'GL2_OP_ATOMIC_SMAX_64',
116: 'GL2_OP_ATOMIC_UMAX_64',
117: 'GL2_OP_ATOMIC_AND_64',
118: 'GL2_OP_ATOMIC_OR_64',
119: 'GL2_OP_ATOMIC_XOR_64',
120: 'GL2_OP_ATOMIC_INC_64',
121: 'GL2_OP_ATOMIC_DEC_64',
123: 'GL2_OP_NOP_ACK',
}
GL2_OP_READ = 0
GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 1
GL2_OP_ATOMIC_FMIN_RTN_32 = 2
GL2_OP_ATOMIC_FMAX_RTN_32 = 3
GL2_OP_ATOMIC_SWAP_RTN_32 = 7
GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 8
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11
GL2_OP_PROBE_FILTER = 12
GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 13
GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14
GL2_OP_ATOMIC_ADD_RTN_32 = 15
GL2_OP_ATOMIC_SUB_RTN_32 = 16
GL2_OP_ATOMIC_SMIN_RTN_32 = 17
GL2_OP_ATOMIC_UMIN_RTN_32 = 18
GL2_OP_ATOMIC_SMAX_RTN_32 = 19
GL2_OP_ATOMIC_UMAX_RTN_32 = 20
GL2_OP_ATOMIC_AND_RTN_32 = 21
GL2_OP_ATOMIC_OR_RTN_32 = 22
GL2_OP_ATOMIC_XOR_RTN_32 = 23
GL2_OP_ATOMIC_INC_RTN_32 = 24
GL2_OP_ATOMIC_DEC_RTN_32 = 25
GL2_OP_WRITE = 32
GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 33
GL2_OP_ATOMIC_FMIN_RTN_64 = 34
GL2_OP_ATOMIC_FMAX_RTN_64 = 35
GL2_OP_ATOMIC_SWAP_RTN_64 = 39
GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 40
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43
GL2_OP_ATOMIC_ADD_RTN_64 = 47
GL2_OP_ATOMIC_SUB_RTN_64 = 48
GL2_OP_ATOMIC_SMIN_RTN_64 = 49
GL2_OP_ATOMIC_UMIN_RTN_64 = 50
GL2_OP_ATOMIC_SMAX_RTN_64 = 51
GL2_OP_ATOMIC_UMAX_RTN_64 = 52
GL2_OP_ATOMIC_AND_RTN_64 = 53
GL2_OP_ATOMIC_OR_RTN_64 = 54
GL2_OP_ATOMIC_XOR_RTN_64 = 55
GL2_OP_ATOMIC_INC_RTN_64 = 56
GL2_OP_ATOMIC_DEC_RTN_64 = 57
GL2_OP_GL1_INV = 64
GL2_OP_ATOMIC_FCMPSWAP_32 = 65
GL2_OP_ATOMIC_FMIN_32 = 66
GL2_OP_ATOMIC_FMAX_32 = 67
GL2_OP_ATOMIC_SWAP_32 = 71
GL2_OP_ATOMIC_CMPSWAP_32 = 72
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75
GL2_OP_ATOMIC_ADD_32 = 79
GL2_OP_ATOMIC_SUB_32 = 80
GL2_OP_ATOMIC_SMIN_32 = 81
GL2_OP_ATOMIC_UMIN_32 = 82
GL2_OP_ATOMIC_SMAX_32 = 83
GL2_OP_ATOMIC_UMAX_32 = 84
GL2_OP_ATOMIC_AND_32 = 85
GL2_OP_ATOMIC_OR_32 = 86
GL2_OP_ATOMIC_XOR_32 = 87
GL2_OP_ATOMIC_INC_32 = 88
GL2_OP_ATOMIC_DEC_32 = 89
GL2_OP_NOP_RTN0 = 91
GL2_OP_ATOMIC_FCMPSWAP_64 = 97
GL2_OP_ATOMIC_FMIN_64 = 98
GL2_OP_ATOMIC_FMAX_64 = 99
GL2_OP_ATOMIC_SWAP_64 = 103
GL2_OP_ATOMIC_CMPSWAP_64 = 104
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107
GL2_OP_ATOMIC_ADD_64 = 111
GL2_OP_ATOMIC_SUB_64 = 112
GL2_OP_ATOMIC_SMIN_64 = 113
GL2_OP_ATOMIC_UMIN_64 = 114
GL2_OP_ATOMIC_SMAX_64 = 115
GL2_OP_ATOMIC_UMAX_64 = 116
GL2_OP_ATOMIC_AND_64 = 117
GL2_OP_ATOMIC_OR_64 = 118
GL2_OP_ATOMIC_XOR_64 = 119
GL2_OP_ATOMIC_INC_64 = 120
GL2_OP_ATOMIC_DEC_64 = 121
GL2_OP_NOP_ACK = 123
GL2_OP = ctypes.c_uint32 # enum
# values for enumeration 'GL2_NACKS'
GL2_NACKS__enumvalues = {
0: 'GL2_NACK_NO_FAULT',
1: 'GL2_NACK_PAGE_FAULT',
2: 'GL2_NACK_PROTECTION_FAULT',
3: 'GL2_NACK_DATA_ERROR',
}
GL2_NACK_NO_FAULT = 0
GL2_NACK_PAGE_FAULT = 1
GL2_NACK_PROTECTION_FAULT = 2
GL2_NACK_DATA_ERROR = 3
GL2_NACKS = ctypes.c_uint32 # enum
# values for enumeration 'GL2_EA_CID'
GL2_EA_CID__enumvalues = {
0: 'GL2_EA_CID_CLIENT',
1: 'GL2_EA_CID_SDMA',
2: 'GL2_EA_CID_RLC',
4: 'GL2_EA_CID_CP',
5: 'GL2_EA_CID_CPDMA',
6: 'GL2_EA_CID_UTCL2',
7: 'GL2_EA_CID_RT',
8: 'GL2_EA_CID_FMASK',
9: 'GL2_EA_CID_DCC',
10: 'GL2_EA_CID_Z_STENCIL',
11: 'GL2_EA_CID_ZPCPSD',
12: 'GL2_EA_CID_HTILE',
15: 'GL2_EA_CID_TCPMETA',
}
GL2_EA_CID_CLIENT = 0
GL2_EA_CID_SDMA = 1
GL2_EA_CID_RLC = 2
GL2_EA_CID_CP = 4
GL2_EA_CID_CPDMA = 5
GL2_EA_CID_UTCL2 = 6
GL2_EA_CID_RT = 7
GL2_EA_CID_FMASK = 8
GL2_EA_CID_DCC = 9
GL2_EA_CID_Z_STENCIL = 10
GL2_EA_CID_ZPCPSD = 11
GL2_EA_CID_HTILE = 12
GL2_EA_CID_TCPMETA = 15
GL2_EA_CID = ctypes.c_uint32 # enum
# values for enumeration 'SPI_SAMPLE_CNTL'
SPI_SAMPLE_CNTL__enumvalues = {
0: 'CENTROIDS_ONLY',
1: 'CENTERS_ONLY',
2: 'CENTROIDS_AND_CENTERS',
3: 'UNDEF',
}
CENTROIDS_ONLY = 0
CENTERS_ONLY = 1
CENTROIDS_AND_CENTERS = 2
UNDEF = 3
SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'SPI_FOG_MODE'
SPI_FOG_MODE__enumvalues = {
0: 'SPI_FOG_NONE',
1: 'SPI_FOG_EXP',
2: 'SPI_FOG_EXP2',
3: 'SPI_FOG_LINEAR',
}
SPI_FOG_NONE = 0
SPI_FOG_EXP = 1
SPI_FOG_EXP2 = 2
SPI_FOG_LINEAR = 3
SPI_FOG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE'
SPI_PNT_SPRITE_OVERRIDE__enumvalues = {
0: 'SPI_PNT_SPRITE_SEL_0',
1: 'SPI_PNT_SPRITE_SEL_1',
2: 'SPI_PNT_SPRITE_SEL_S',
3: 'SPI_PNT_SPRITE_SEL_T',
4: 'SPI_PNT_SPRITE_SEL_NONE',
}
SPI_PNT_SPRITE_SEL_0 = 0
SPI_PNT_SPRITE_SEL_1 = 1
SPI_PNT_SPRITE_SEL_S = 2
SPI_PNT_SPRITE_SEL_T = 3
SPI_PNT_SPRITE_SEL_NONE = 4
SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'SPI_PERFCNT_SEL'
SPI_PERFCNT_SEL__enumvalues = {
0: 'SPI_PERF_VS_WINDOW_VALID',
1: 'SPI_PERF_VS_BUSY',
2: 'SPI_PERF_VS_FIRST_WAVE',
3: 'SPI_PERF_VS_LAST_WAVE',
4: 'SPI_PERF_VS_LSHS_DEALLOC',
5: 'SPI_PERF_VS_PC_STALL',
6: 'SPI_PERF_VS_POS0_STALL',
7: 'SPI_PERF_VS_POS1_STALL',
8: 'SPI_PERF_VS_CRAWLER_STALL',
9: 'SPI_PERF_VS_EVENT_WAVE',
10: 'SPI_PERF_VS_WAVE',
11: 'SPI_PERF_VS_PERS_UPD_FULL0',
12: 'SPI_PERF_VS_PERS_UPD_FULL1',
13: 'SPI_PERF_VS_LATE_ALLOC_FULL',
14: 'SPI_PERF_VS_FIRST_SUBGRP',
15: 'SPI_PERF_VS_LAST_SUBGRP',
16: 'SPI_PERF_VS_ALLOC_CNT',
17: 'SPI_PERF_VS_PC_ALLOC_CNT',
18: 'SPI_PERF_VS_LATE_ALLOC_ACCUM',
19: 'SPI_PERF_GS_WINDOW_VALID',
20: 'SPI_PERF_GS_BUSY',
21: 'SPI_PERF_GS_CRAWLER_STALL',
22: 'SPI_PERF_GS_EVENT_WAVE',
23: 'SPI_PERF_GS_WAVE',
24: 'SPI_PERF_GS_PERS_UPD_FULL0',
25: 'SPI_PERF_GS_PERS_UPD_FULL1',
26: 'SPI_PERF_GS_FIRST_SUBGRP',
27: 'SPI_PERF_GS_LAST_SUBGRP',
28: 'SPI_PERF_GS_HS_DEALLOC',
29: 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT',
30: 'SPI_PERF_GS_GRP_FIFO_FULL',
31: 'SPI_PERF_HS_WINDOW_VALID',
32: 'SPI_PERF_HS_BUSY',
33: 'SPI_PERF_HS_CRAWLER_STALL',
34: 'SPI_PERF_HS_FIRST_WAVE',
35: 'SPI_PERF_HS_LAST_WAVE',
36: 'SPI_PERF_HS_OFFCHIP_LDS_STALL',
37: 'SPI_PERF_HS_EVENT_WAVE',
38: 'SPI_PERF_HS_WAVE',
39: 'SPI_PERF_HS_PERS_UPD_FULL0',
40: 'SPI_PERF_HS_PERS_UPD_FULL1',
41: 'SPI_PERF_CSG_WINDOW_VALID',
42: 'SPI_PERF_CSG_BUSY',
43: 'SPI_PERF_CSG_NUM_THREADGROUPS',
44: 'SPI_PERF_CSG_CRAWLER_STALL',
45: 'SPI_PERF_CSG_EVENT_WAVE',
46: 'SPI_PERF_CSG_WAVE',
47: 'SPI_PERF_CSN_WINDOW_VALID',
48: 'SPI_PERF_CSN_BUSY',
49: 'SPI_PERF_CSN_NUM_THREADGROUPS',
50: 'SPI_PERF_CSN_CRAWLER_STALL',
51: 'SPI_PERF_CSN_EVENT_WAVE',
52: 'SPI_PERF_CSN_WAVE',
53: 'SPI_PERF_PS0_WINDOW_VALID',
54: 'SPI_PERF_PS1_WINDOW_VALID',
55: 'SPI_PERF_PS2_WINDOW_VALID',
56: 'SPI_PERF_PS3_WINDOW_VALID',
57: 'SPI_PERF_PS0_BUSY',
58: 'SPI_PERF_PS1_BUSY',
59: 'SPI_PERF_PS2_BUSY',
60: 'SPI_PERF_PS3_BUSY',
61: 'SPI_PERF_PS0_ACTIVE',
62: 'SPI_PERF_PS1_ACTIVE',
63: 'SPI_PERF_PS2_ACTIVE',
64: 'SPI_PERF_PS3_ACTIVE',
65: 'SPI_PERF_PS0_DEALLOC_BIN0',
66: 'SPI_PERF_PS1_DEALLOC_BIN0',
67: 'SPI_PERF_PS2_DEALLOC_BIN0',
68: 'SPI_PERF_PS3_DEALLOC_BIN0',
69: 'SPI_PERF_PS0_FPOS_BIN1_STALL',
70: 'SPI_PERF_PS1_FPOS_BIN1_STALL',
71: 'SPI_PERF_PS2_FPOS_BIN1_STALL',
72: 'SPI_PERF_PS3_FPOS_BIN1_STALL',
73: 'SPI_PERF_PS0_EVENT_WAVE',
74: 'SPI_PERF_PS1_EVENT_WAVE',
75: 'SPI_PERF_PS2_EVENT_WAVE',
76: 'SPI_PERF_PS3_EVENT_WAVE',
77: 'SPI_PERF_PS0_WAVE',
78: 'SPI_PERF_PS1_WAVE',
79: 'SPI_PERF_PS2_WAVE',
80: 'SPI_PERF_PS3_WAVE',
81: 'SPI_PERF_PS0_OPT_WAVE',
82: 'SPI_PERF_PS1_OPT_WAVE',
83: 'SPI_PERF_PS2_OPT_WAVE',
84: 'SPI_PERF_PS3_OPT_WAVE',
85: 'SPI_PERF_PS0_PASS_BIN0',
86: 'SPI_PERF_PS1_PASS_BIN0',
87: 'SPI_PERF_PS2_PASS_BIN0',
88: 'SPI_PERF_PS3_PASS_BIN0',
89: 'SPI_PERF_PS0_PASS_BIN1',
90: 'SPI_PERF_PS1_PASS_BIN1',
91: 'SPI_PERF_PS2_PASS_BIN1',
92: 'SPI_PERF_PS3_PASS_BIN1',
93: 'SPI_PERF_PS0_FPOS_BIN2',
94: 'SPI_PERF_PS1_FPOS_BIN2',
95: 'SPI_PERF_PS2_FPOS_BIN2',
96: 'SPI_PERF_PS3_FPOS_BIN2',
97: 'SPI_PERF_PS0_PRIM_BIN0',
98: 'SPI_PERF_PS1_PRIM_BIN0',
99: 'SPI_PERF_PS2_PRIM_BIN0',
100: 'SPI_PERF_PS3_PRIM_BIN0',
101: 'SPI_PERF_PS0_PRIM_BIN1',
102: 'SPI_PERF_PS1_PRIM_BIN1',
103: 'SPI_PERF_PS2_PRIM_BIN1',
104: 'SPI_PERF_PS3_PRIM_BIN1',
105: 'SPI_PERF_PS0_CNF_BIN2',
106: 'SPI_PERF_PS1_CNF_BIN2',
107: 'SPI_PERF_PS2_CNF_BIN2',
108: 'SPI_PERF_PS3_CNF_BIN2',
109: 'SPI_PERF_PS0_CNF_BIN3',
110: 'SPI_PERF_PS1_CNF_BIN3',
111: 'SPI_PERF_PS2_CNF_BIN3',
112: 'SPI_PERF_PS3_CNF_BIN3',
113: 'SPI_PERF_PS0_CRAWLER_STALL',
114: 'SPI_PERF_PS1_CRAWLER_STALL',
115: 'SPI_PERF_PS2_CRAWLER_STALL',
116: 'SPI_PERF_PS3_CRAWLER_STALL',
117: 'SPI_PERF_PS0_LDS_RES_FULL',
118: 'SPI_PERF_PS1_LDS_RES_FULL',
119: 'SPI_PERF_PS2_LDS_RES_FULL',
120: 'SPI_PERF_PS3_LDS_RES_FULL',
121: 'SPI_PERF_PS_PERS_UPD_FULL0',
122: 'SPI_PERF_PS_PERS_UPD_FULL1',
123: 'SPI_PERF_PS0_POPS_WAVE_SENT',
124: 'SPI_PERF_PS1_POPS_WAVE_SENT',
125: 'SPI_PERF_PS2_POPS_WAVE_SENT',
126: 'SPI_PERF_PS3_POPS_WAVE_SENT',
127: 'SPI_PERF_PS0_POPS_WAVE_EXIT',
128: 'SPI_PERF_PS1_POPS_WAVE_EXIT',
129: 'SPI_PERF_PS2_POPS_WAVE_EXIT',
130: 'SPI_PERF_PS3_POPS_WAVE_EXIT',
131: 'SPI_PERF_LDS0_PC_VALID',
132: 'SPI_PERF_LDS1_PC_VALID',
133: 'SPI_PERF_RA_PIPE_REQ_BIN2',
134: 'SPI_PERF_RA_TASK_REQ_BIN3',
135: 'SPI_PERF_RA_WR_CTL_FULL',
136: 'SPI_PERF_RA_REQ_NO_ALLOC',
137: 'SPI_PERF_RA_REQ_NO_ALLOC_PS',
138: 'SPI_PERF_RA_REQ_NO_ALLOC_VS',
139: 'SPI_PERF_RA_REQ_NO_ALLOC_GS',
140: 'SPI_PERF_RA_REQ_NO_ALLOC_HS',
141: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG',
142: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN',
143: 'SPI_PERF_RA_RES_STALL_PS',
144: 'SPI_PERF_RA_RES_STALL_VS',
145: 'SPI_PERF_RA_RES_STALL_GS',
146: 'SPI_PERF_RA_RES_STALL_HS',
147: 'SPI_PERF_RA_RES_STALL_CSG',
148: 'SPI_PERF_RA_RES_STALL_CSN',
149: 'SPI_PERF_RA_TMP_STALL_PS',
150: 'SPI_PERF_RA_TMP_STALL_VS',
151: 'SPI_PERF_RA_TMP_STALL_GS',
152: 'SPI_PERF_RA_TMP_STALL_HS',
153: 'SPI_PERF_RA_TMP_STALL_CSG',
154: 'SPI_PERF_RA_TMP_STALL_CSN',
155: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS',
156: 'SPI_PERF_RA_WAVE_SIMD_FULL_VS',
157: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS',
158: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS',
159: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG',
160: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN',
161: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS',
162: 'SPI_PERF_RA_VGPR_SIMD_FULL_VS',
163: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS',
164: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS',
165: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG',
166: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN',
167: 'SPI_PERF_RA_SGPR_SIMD_FULL_PS',
168: 'SPI_PERF_RA_SGPR_SIMD_FULL_VS',
169: 'SPI_PERF_RA_SGPR_SIMD_FULL_GS',
170: 'SPI_PERF_RA_SGPR_SIMD_FULL_HS',
171: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSG',
172: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSN',
173: 'SPI_PERF_RA_LDS_CU_FULL_PS',
174: 'SPI_PERF_RA_LDS_CU_FULL_LS',
175: 'SPI_PERF_RA_LDS_CU_FULL_ES',
176: 'SPI_PERF_RA_LDS_CU_FULL_CSG',
177: 'SPI_PERF_RA_LDS_CU_FULL_CSN',
178: 'SPI_PERF_RA_BAR_CU_FULL_HS',
179: 'SPI_PERF_RA_BAR_CU_FULL_CSG',
180: 'SPI_PERF_RA_BAR_CU_FULL_CSN',
181: 'SPI_PERF_RA_BULKY_CU_FULL_CSG',
182: 'SPI_PERF_RA_BULKY_CU_FULL_CSN',
183: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG',
184: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN',
185: 'SPI_PERF_RA_WVLIM_STALL_PS',
186: 'SPI_PERF_RA_WVLIM_STALL_VS',
187: 'SPI_PERF_RA_WVLIM_STALL_GS',
188: 'SPI_PERF_RA_WVLIM_STALL_HS',
189: 'SPI_PERF_RA_WVLIM_STALL_CSG',
190: 'SPI_PERF_RA_WVLIM_STALL_CSN',
191: 'SPI_PERF_RA_VS_LOCK',
192: 'SPI_PERF_RA_GS_LOCK',
193: 'SPI_PERF_RA_HS_LOCK',
194: 'SPI_PERF_RA_CSG_LOCK',
195: 'SPI_PERF_RA_CSN_LOCK',
196: 'SPI_PERF_RA_RSV_UPD',
197: 'SPI_PERF_EXP_ARB_COL_CNT',
198: 'SPI_PERF_EXP_ARB_PAR_CNT',
199: 'SPI_PERF_EXP_ARB_POS_CNT',
200: 'SPI_PERF_EXP_ARB_GDS_CNT',
201: 'SPI_PERF_NUM_PS_COL_R0_EXPORTS',
202: 'SPI_PERF_NUM_PS_COL_R1_EXPORTS',
203: 'SPI_PERF_NUM_VS_POS_R0_EXPORTS',
204: 'SPI_PERF_NUM_VS_POS_R1_EXPORTS',
205: 'SPI_PERF_NUM_VS_PARAM_R0_EXPORTS',
206: 'SPI_PERF_NUM_VS_PARAM_R1_EXPORTS',
207: 'SPI_PERF_NUM_VS_GDS_R0_EXPORTS',
208: 'SPI_PERF_NUM_VS_GDS_R1_EXPORTS',
209: 'SPI_PERF_NUM_EXPGRANT_EXPORTS',
210: 'SPI_PERF_CLKGATE_BUSY_STALL',
211: 'SPI_PERF_CLKGATE_ACTIVE_STALL',
212: 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON',
213: 'SPI_PERF_CLKGATE_CGTT_DYN_ON',
214: 'SPI_PERF_CLKGATE_CGTT_REG_ON',
215: 'SPI_PERF_PIX_ALLOC_PEND_CNT',
216: 'SPI_PERF_PIX_ALLOC_SCB0_STALL',
217: 'SPI_PERF_PIX_ALLOC_SCB1_STALL',
218: 'SPI_PERF_PIX_ALLOC_SCB2_STALL',
219: 'SPI_PERF_PIX_ALLOC_SCB3_STALL',
220: 'SPI_PERF_PIX_ALLOC_DB0_STALL',
221: 'SPI_PERF_PIX_ALLOC_DB1_STALL',
222: 'SPI_PERF_PIX_ALLOC_DB2_STALL',
223: 'SPI_PERF_PIX_ALLOC_DB3_STALL',
224: 'SPI_PERF_PIX_ALLOC_DB4_STALL',
225: 'SPI_PERF_PIX_ALLOC_DB5_STALL',
226: 'SPI_PERF_PIX_ALLOC_DB6_STALL',
227: 'SPI_PERF_PIX_ALLOC_DB7_STALL',
228: 'SPI_PERF_PC_ALLOC_ACCUM',
229: 'SPI_PERF_GS_NGG_SE_HAS_BATON',
230: 'SPI_PERF_GS_NGG_SE_DOES_NOT_HAVE_BATON',
231: 'SPI_PERF_GS_NGG_SE_FORWARDED_BATON',
232: 'SPI_PERF_GS_NGG_SE_AT_SYNC_EVENT',
233: 'SPI_PERF_GS_NGG_SE_SG_ALLOC_PC_SPACE_CNT',
234: 'SPI_PERF_GS_NGG_SE_DEALLOC_PC_SPACE_CNT',
235: 'SPI_PERF_GS_NGG_PC_FULL',
236: 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC',
237: 'SPI_PERF_GS_NGG_GS_ALLOC_FIFO_EMPTY',
238: 'SPI_PERF_GSC_VTX_BUSY',
239: 'SPI_PERF_GSC_VTX_INPUT_STARVED',
240: 'SPI_PERF_GSC_VTX_VSR_STALL',
241: 'SPI_PERF_GSC_VTX_VSR_FULL',
242: 'SPI_PERF_GSC_VTX_CAC_BUSY',
243: 'SPI_PERF_ESC_VTX_BUSY',
244: 'SPI_PERF_ESC_VTX_INPUT_STARVED',
245: 'SPI_PERF_ESC_VTX_VSR_STALL',
246: 'SPI_PERF_ESC_VTX_VSR_FULL',
247: 'SPI_PERF_ESC_VTX_CAC_BUSY',
248: 'SPI_PERF_SWC_PS_WR',
249: 'SPI_PERF_SWC_VS_WR',
250: 'SPI_PERF_SWC_GS_WR',
251: 'SPI_PERF_SWC_HS_WR',
252: 'SPI_PERF_SWC_CSG_WR',
253: 'SPI_PERF_SWC_CSC_WR',
254: 'SPI_PERF_VWC_PS_WR',
255: 'SPI_PERF_VWC_VS_WR',
256: 'SPI_PERF_VWC_GS_WR',
257: 'SPI_PERF_VWC_HS_WR',
258: 'SPI_PERF_VWC_CSG_WR',
259: 'SPI_PERF_VWC_CSC_WR',
260: 'SPI_PERF_ES_WINDOW_VALID',
261: 'SPI_PERF_ES_BUSY',
262: 'SPI_PERF_ES_CRAWLER_STALL',
263: 'SPI_PERF_ES_FIRST_WAVE',
264: 'SPI_PERF_ES_LAST_WAVE',
265: 'SPI_PERF_ES_LSHS_DEALLOC',
266: 'SPI_PERF_ES_EVENT_WAVE',
267: 'SPI_PERF_ES_WAVE',
268: 'SPI_PERF_ES_PERS_UPD_FULL0',
269: 'SPI_PERF_ES_PERS_UPD_FULL1',
270: 'SPI_PERF_ES_FIRST_SUBGRP',
271: 'SPI_PERF_ES_LAST_SUBGRP',
272: 'SPI_PERF_LS_WINDOW_VALID',
273: 'SPI_PERF_LS_BUSY',
274: 'SPI_PERF_LS_CRAWLER_STALL',
275: 'SPI_PERF_LS_FIRST_WAVE',
276: 'SPI_PERF_LS_LAST_WAVE',
277: 'SPI_PERF_LS_OFFCHIP_LDS_STALL',
278: 'SPI_PERF_LS_EVENT_WAVE',
279: 'SPI_PERF_LS_WAVE',
280: 'SPI_PERF_LS_PERS_UPD_FULL0',
281: 'SPI_PERF_LS_PERS_UPD_FULL1',
}
SPI_PERF_VS_WINDOW_VALID = 0
SPI_PERF_VS_BUSY = 1
SPI_PERF_VS_FIRST_WAVE = 2
SPI_PERF_VS_LAST_WAVE = 3
SPI_PERF_VS_LSHS_DEALLOC = 4
SPI_PERF_VS_PC_STALL = 5
SPI_PERF_VS_POS0_STALL = 6
SPI_PERF_VS_POS1_STALL = 7
SPI_PERF_VS_CRAWLER_STALL = 8
SPI_PERF_VS_EVENT_WAVE = 9
SPI_PERF_VS_WAVE = 10
SPI_PERF_VS_PERS_UPD_FULL0 = 11
SPI_PERF_VS_PERS_UPD_FULL1 = 12
SPI_PERF_VS_LATE_ALLOC_FULL = 13
SPI_PERF_VS_FIRST_SUBGRP = 14
SPI_PERF_VS_LAST_SUBGRP = 15
SPI_PERF_VS_ALLOC_CNT = 16
SPI_PERF_VS_PC_ALLOC_CNT = 17
SPI_PERF_VS_LATE_ALLOC_ACCUM = 18
SPI_PERF_GS_WINDOW_VALID = 19
SPI_PERF_GS_BUSY = 20
SPI_PERF_GS_CRAWLER_STALL = 21
SPI_PERF_GS_EVENT_WAVE = 22
SPI_PERF_GS_WAVE = 23
SPI_PERF_GS_PERS_UPD_FULL0 = 24
SPI_PERF_GS_PERS_UPD_FULL1 = 25
SPI_PERF_GS_FIRST_SUBGRP = 26
SPI_PERF_GS_LAST_SUBGRP = 27
SPI_PERF_GS_HS_DEALLOC = 28
SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 29
SPI_PERF_GS_GRP_FIFO_FULL = 30
SPI_PERF_HS_WINDOW_VALID = 31
SPI_PERF_HS_BUSY = 32
SPI_PERF_HS_CRAWLER_STALL = 33
SPI_PERF_HS_FIRST_WAVE = 34
SPI_PERF_HS_LAST_WAVE = 35
SPI_PERF_HS_OFFCHIP_LDS_STALL = 36
SPI_PERF_HS_EVENT_WAVE = 37
SPI_PERF_HS_WAVE = 38
SPI_PERF_HS_PERS_UPD_FULL0 = 39
SPI_PERF_HS_PERS_UPD_FULL1 = 40
SPI_PERF_CSG_WINDOW_VALID = 41
SPI_PERF_CSG_BUSY = 42
SPI_PERF_CSG_NUM_THREADGROUPS = 43
SPI_PERF_CSG_CRAWLER_STALL = 44
SPI_PERF_CSG_EVENT_WAVE = 45
SPI_PERF_CSG_WAVE = 46
SPI_PERF_CSN_WINDOW_VALID = 47
SPI_PERF_CSN_BUSY = 48
SPI_PERF_CSN_NUM_THREADGROUPS = 49
SPI_PERF_CSN_CRAWLER_STALL = 50
SPI_PERF_CSN_EVENT_WAVE = 51
SPI_PERF_CSN_WAVE = 52
SPI_PERF_PS0_WINDOW_VALID = 53
SPI_PERF_PS1_WINDOW_VALID = 54
SPI_PERF_PS2_WINDOW_VALID = 55
SPI_PERF_PS3_WINDOW_VALID = 56
SPI_PERF_PS0_BUSY = 57
SPI_PERF_PS1_BUSY = 58
SPI_PERF_PS2_BUSY = 59
SPI_PERF_PS3_BUSY = 60
SPI_PERF_PS0_ACTIVE = 61
SPI_PERF_PS1_ACTIVE = 62
SPI_PERF_PS2_ACTIVE = 63
SPI_PERF_PS3_ACTIVE = 64
SPI_PERF_PS0_DEALLOC_BIN0 = 65
SPI_PERF_PS1_DEALLOC_BIN0 = 66
SPI_PERF_PS2_DEALLOC_BIN0 = 67
SPI_PERF_PS3_DEALLOC_BIN0 = 68
SPI_PERF_PS0_FPOS_BIN1_STALL = 69
SPI_PERF_PS1_FPOS_BIN1_STALL = 70
SPI_PERF_PS2_FPOS_BIN1_STALL = 71
SPI_PERF_PS3_FPOS_BIN1_STALL = 72
SPI_PERF_PS0_EVENT_WAVE = 73
SPI_PERF_PS1_EVENT_WAVE = 74
SPI_PERF_PS2_EVENT_WAVE = 75
SPI_PERF_PS3_EVENT_WAVE = 76
SPI_PERF_PS0_WAVE = 77
SPI_PERF_PS1_WAVE = 78
SPI_PERF_PS2_WAVE = 79
SPI_PERF_PS3_WAVE = 80
SPI_PERF_PS0_OPT_WAVE = 81
SPI_PERF_PS1_OPT_WAVE = 82
SPI_PERF_PS2_OPT_WAVE = 83
SPI_PERF_PS3_OPT_WAVE = 84
SPI_PERF_PS0_PASS_BIN0 = 85
SPI_PERF_PS1_PASS_BIN0 = 86
SPI_PERF_PS2_PASS_BIN0 = 87
SPI_PERF_PS3_PASS_BIN0 = 88
SPI_PERF_PS0_PASS_BIN1 = 89
SPI_PERF_PS1_PASS_BIN1 = 90
SPI_PERF_PS2_PASS_BIN1 = 91
SPI_PERF_PS3_PASS_BIN1 = 92
SPI_PERF_PS0_FPOS_BIN2 = 93
SPI_PERF_PS1_FPOS_BIN2 = 94
SPI_PERF_PS2_FPOS_BIN2 = 95
SPI_PERF_PS3_FPOS_BIN2 = 96
SPI_PERF_PS0_PRIM_BIN0 = 97
SPI_PERF_PS1_PRIM_BIN0 = 98
SPI_PERF_PS2_PRIM_BIN0 = 99
SPI_PERF_PS3_PRIM_BIN0 = 100
SPI_PERF_PS0_PRIM_BIN1 = 101
SPI_PERF_PS1_PRIM_BIN1 = 102
SPI_PERF_PS2_PRIM_BIN1 = 103
SPI_PERF_PS3_PRIM_BIN1 = 104
SPI_PERF_PS0_CNF_BIN2 = 105
SPI_PERF_PS1_CNF_BIN2 = 106
SPI_PERF_PS2_CNF_BIN2 = 107
SPI_PERF_PS3_CNF_BIN2 = 108
SPI_PERF_PS0_CNF_BIN3 = 109
SPI_PERF_PS1_CNF_BIN3 = 110
SPI_PERF_PS2_CNF_BIN3 = 111
SPI_PERF_PS3_CNF_BIN3 = 112
SPI_PERF_PS0_CRAWLER_STALL = 113
SPI_PERF_PS1_CRAWLER_STALL = 114
SPI_PERF_PS2_CRAWLER_STALL = 115
SPI_PERF_PS3_CRAWLER_STALL = 116
SPI_PERF_PS0_LDS_RES_FULL = 117
SPI_PERF_PS1_LDS_RES_FULL = 118
SPI_PERF_PS2_LDS_RES_FULL = 119
SPI_PERF_PS3_LDS_RES_FULL = 120
SPI_PERF_PS_PERS_UPD_FULL0 = 121
SPI_PERF_PS_PERS_UPD_FULL1 = 122
SPI_PERF_PS0_POPS_WAVE_SENT = 123
SPI_PERF_PS1_POPS_WAVE_SENT = 124
SPI_PERF_PS2_POPS_WAVE_SENT = 125
SPI_PERF_PS3_POPS_WAVE_SENT = 126
SPI_PERF_PS0_POPS_WAVE_EXIT = 127
SPI_PERF_PS1_POPS_WAVE_EXIT = 128
SPI_PERF_PS2_POPS_WAVE_EXIT = 129
SPI_PERF_PS3_POPS_WAVE_EXIT = 130
SPI_PERF_LDS0_PC_VALID = 131
SPI_PERF_LDS1_PC_VALID = 132
SPI_PERF_RA_PIPE_REQ_BIN2 = 133
SPI_PERF_RA_TASK_REQ_BIN3 = 134
SPI_PERF_RA_WR_CTL_FULL = 135
SPI_PERF_RA_REQ_NO_ALLOC = 136
SPI_PERF_RA_REQ_NO_ALLOC_PS = 137
SPI_PERF_RA_REQ_NO_ALLOC_VS = 138
SPI_PERF_RA_REQ_NO_ALLOC_GS = 139
SPI_PERF_RA_REQ_NO_ALLOC_HS = 140
SPI_PERF_RA_REQ_NO_ALLOC_CSG = 141
SPI_PERF_RA_REQ_NO_ALLOC_CSN = 142
SPI_PERF_RA_RES_STALL_PS = 143
SPI_PERF_RA_RES_STALL_VS = 144
SPI_PERF_RA_RES_STALL_GS = 145
SPI_PERF_RA_RES_STALL_HS = 146
SPI_PERF_RA_RES_STALL_CSG = 147
SPI_PERF_RA_RES_STALL_CSN = 148
SPI_PERF_RA_TMP_STALL_PS = 149
SPI_PERF_RA_TMP_STALL_VS = 150
SPI_PERF_RA_TMP_STALL_GS = 151
SPI_PERF_RA_TMP_STALL_HS = 152
SPI_PERF_RA_TMP_STALL_CSG = 153
SPI_PERF_RA_TMP_STALL_CSN = 154
SPI_PERF_RA_WAVE_SIMD_FULL_PS = 155
SPI_PERF_RA_WAVE_SIMD_FULL_VS = 156
SPI_PERF_RA_WAVE_SIMD_FULL_GS = 157
SPI_PERF_RA_WAVE_SIMD_FULL_HS = 158
SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 159
SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 160
SPI_PERF_RA_VGPR_SIMD_FULL_PS = 161
SPI_PERF_RA_VGPR_SIMD_FULL_VS = 162
SPI_PERF_RA_VGPR_SIMD_FULL_GS = 163
SPI_PERF_RA_VGPR_SIMD_FULL_HS = 164
SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 165
SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 166
SPI_PERF_RA_SGPR_SIMD_FULL_PS = 167
SPI_PERF_RA_SGPR_SIMD_FULL_VS = 168
SPI_PERF_RA_SGPR_SIMD_FULL_GS = 169
SPI_PERF_RA_SGPR_SIMD_FULL_HS = 170
SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 171
SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 172
SPI_PERF_RA_LDS_CU_FULL_PS = 173
SPI_PERF_RA_LDS_CU_FULL_LS = 174
SPI_PERF_RA_LDS_CU_FULL_ES = 175
SPI_PERF_RA_LDS_CU_FULL_CSG = 176
SPI_PERF_RA_LDS_CU_FULL_CSN = 177
SPI_PERF_RA_BAR_CU_FULL_HS = 178
SPI_PERF_RA_BAR_CU_FULL_CSG = 179
SPI_PERF_RA_BAR_CU_FULL_CSN = 180
SPI_PERF_RA_BULKY_CU_FULL_CSG = 181
SPI_PERF_RA_BULKY_CU_FULL_CSN = 182
SPI_PERF_RA_TGLIM_CU_FULL_CSG = 183
SPI_PERF_RA_TGLIM_CU_FULL_CSN = 184
SPI_PERF_RA_WVLIM_STALL_PS = 185
SPI_PERF_RA_WVLIM_STALL_VS = 186
SPI_PERF_RA_WVLIM_STALL_GS = 187
SPI_PERF_RA_WVLIM_STALL_HS = 188
SPI_PERF_RA_WVLIM_STALL_CSG = 189
SPI_PERF_RA_WVLIM_STALL_CSN = 190
SPI_PERF_RA_VS_LOCK = 191
SPI_PERF_RA_GS_LOCK = 192
SPI_PERF_RA_HS_LOCK = 193
SPI_PERF_RA_CSG_LOCK = 194
SPI_PERF_RA_CSN_LOCK = 195
SPI_PERF_RA_RSV_UPD = 196
SPI_PERF_EXP_ARB_COL_CNT = 197
SPI_PERF_EXP_ARB_PAR_CNT = 198
SPI_PERF_EXP_ARB_POS_CNT = 199
SPI_PERF_EXP_ARB_GDS_CNT = 200
SPI_PERF_NUM_PS_COL_R0_EXPORTS = 201
SPI_PERF_NUM_PS_COL_R1_EXPORTS = 202
SPI_PERF_NUM_VS_POS_R0_EXPORTS = 203
SPI_PERF_NUM_VS_POS_R1_EXPORTS = 204
SPI_PERF_NUM_VS_PARAM_R0_EXPORTS = 205
SPI_PERF_NUM_VS_PARAM_R1_EXPORTS = 206
SPI_PERF_NUM_VS_GDS_R0_EXPORTS = 207
SPI_PERF_NUM_VS_GDS_R1_EXPORTS = 208
SPI_PERF_NUM_EXPGRANT_EXPORTS = 209
SPI_PERF_CLKGATE_BUSY_STALL = 210
SPI_PERF_CLKGATE_ACTIVE_STALL = 211
SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 212
SPI_PERF_CLKGATE_CGTT_DYN_ON = 213
SPI_PERF_CLKGATE_CGTT_REG_ON = 214
SPI_PERF_PIX_ALLOC_PEND_CNT = 215
SPI_PERF_PIX_ALLOC_SCB0_STALL = 216
SPI_PERF_PIX_ALLOC_SCB1_STALL = 217
SPI_PERF_PIX_ALLOC_SCB2_STALL = 218
SPI_PERF_PIX_ALLOC_SCB3_STALL = 219
SPI_PERF_PIX_ALLOC_DB0_STALL = 220
SPI_PERF_PIX_ALLOC_DB1_STALL = 221
SPI_PERF_PIX_ALLOC_DB2_STALL = 222
SPI_PERF_PIX_ALLOC_DB3_STALL = 223
SPI_PERF_PIX_ALLOC_DB4_STALL = 224
SPI_PERF_PIX_ALLOC_DB5_STALL = 225
SPI_PERF_PIX_ALLOC_DB6_STALL = 226
SPI_PERF_PIX_ALLOC_DB7_STALL = 227
SPI_PERF_PC_ALLOC_ACCUM = 228
SPI_PERF_GS_NGG_SE_HAS_BATON = 229
SPI_PERF_GS_NGG_SE_DOES_NOT_HAVE_BATON = 230
SPI_PERF_GS_NGG_SE_FORWARDED_BATON = 231
SPI_PERF_GS_NGG_SE_AT_SYNC_EVENT = 232
SPI_PERF_GS_NGG_SE_SG_ALLOC_PC_SPACE_CNT = 233
SPI_PERF_GS_NGG_SE_DEALLOC_PC_SPACE_CNT = 234
SPI_PERF_GS_NGG_PC_FULL = 235
SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 236
SPI_PERF_GS_NGG_GS_ALLOC_FIFO_EMPTY = 237
SPI_PERF_GSC_VTX_BUSY = 238
SPI_PERF_GSC_VTX_INPUT_STARVED = 239
SPI_PERF_GSC_VTX_VSR_STALL = 240
SPI_PERF_GSC_VTX_VSR_FULL = 241
SPI_PERF_GSC_VTX_CAC_BUSY = 242
SPI_PERF_ESC_VTX_BUSY = 243
SPI_PERF_ESC_VTX_INPUT_STARVED = 244
SPI_PERF_ESC_VTX_VSR_STALL = 245
SPI_PERF_ESC_VTX_VSR_FULL = 246
SPI_PERF_ESC_VTX_CAC_BUSY = 247
SPI_PERF_SWC_PS_WR = 248
SPI_PERF_SWC_VS_WR = 249
SPI_PERF_SWC_GS_WR = 250
SPI_PERF_SWC_HS_WR = 251
SPI_PERF_SWC_CSG_WR = 252
SPI_PERF_SWC_CSC_WR = 253
SPI_PERF_VWC_PS_WR = 254
SPI_PERF_VWC_VS_WR = 255
SPI_PERF_VWC_GS_WR = 256
SPI_PERF_VWC_HS_WR = 257
SPI_PERF_VWC_CSG_WR = 258
SPI_PERF_VWC_CSC_WR = 259
SPI_PERF_ES_WINDOW_VALID = 260
SPI_PERF_ES_BUSY = 261
SPI_PERF_ES_CRAWLER_STALL = 262
SPI_PERF_ES_FIRST_WAVE = 263
SPI_PERF_ES_LAST_WAVE = 264
SPI_PERF_ES_LSHS_DEALLOC = 265
SPI_PERF_ES_EVENT_WAVE = 266
SPI_PERF_ES_WAVE = 267
SPI_PERF_ES_PERS_UPD_FULL0 = 268
SPI_PERF_ES_PERS_UPD_FULL1 = 269
SPI_PERF_ES_FIRST_SUBGRP = 270
SPI_PERF_ES_LAST_SUBGRP = 271
SPI_PERF_LS_WINDOW_VALID = 272
SPI_PERF_LS_BUSY = 273
SPI_PERF_LS_CRAWLER_STALL = 274
SPI_PERF_LS_FIRST_WAVE = 275
SPI_PERF_LS_LAST_WAVE = 276
SPI_PERF_LS_OFFCHIP_LDS_STALL = 277
SPI_PERF_LS_EVENT_WAVE = 278
SPI_PERF_LS_WAVE = 279
SPI_PERF_LS_PERS_UPD_FULL0 = 280
SPI_PERF_LS_PERS_UPD_FULL1 = 281
SPI_PERFCNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SPI_SHADER_FORMAT'
SPI_SHADER_FORMAT__enumvalues = {
0: 'SPI_SHADER_NONE',
1: 'SPI_SHADER_1COMP',
2: 'SPI_SHADER_2COMP',
3: 'SPI_SHADER_4COMPRESS',
4: 'SPI_SHADER_4COMP',
}
SPI_SHADER_NONE = 0
SPI_SHADER_1COMP = 1
SPI_SHADER_2COMP = 2
SPI_SHADER_4COMPRESS = 3
SPI_SHADER_4COMP = 4
SPI_SHADER_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'SPI_SHADER_EX_FORMAT'
SPI_SHADER_EX_FORMAT__enumvalues = {
0: 'SPI_SHADER_ZERO',
1: 'SPI_SHADER_32_R',
2: 'SPI_SHADER_32_GR',
3: 'SPI_SHADER_32_AR',
4: 'SPI_SHADER_FP16_ABGR',
5: 'SPI_SHADER_UNORM16_ABGR',
6: 'SPI_SHADER_SNORM16_ABGR',
7: 'SPI_SHADER_UINT16_ABGR',
8: 'SPI_SHADER_SINT16_ABGR',
9: 'SPI_SHADER_32_ABGR',
}
SPI_SHADER_ZERO = 0
SPI_SHADER_32_R = 1
SPI_SHADER_32_GR = 2
SPI_SHADER_32_AR = 3
SPI_SHADER_FP16_ABGR = 4
SPI_SHADER_UNORM16_ABGR = 5
SPI_SHADER_SNORM16_ABGR = 6
SPI_SHADER_UINT16_ABGR = 7
SPI_SHADER_SINT16_ABGR = 8
SPI_SHADER_32_ABGR = 9
SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'CLKGATE_SM_MODE'
CLKGATE_SM_MODE__enumvalues = {
0: 'ON_SEQ',
1: 'OFF_SEQ',
2: 'PROG_SEQ',
3: 'READ_SEQ',
4: 'SM_MODE_RESERVED',
}
ON_SEQ = 0
OFF_SEQ = 1
PROG_SEQ = 2
READ_SEQ = 3
SM_MODE_RESERVED = 4
CLKGATE_SM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CLKGATE_BASE_MODE'
CLKGATE_BASE_MODE__enumvalues = {
0: 'MULT_8',
1: 'MULT_16',
}
MULT_8 = 0
MULT_16 = 1
CLKGATE_BASE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SPI_LB_WAVES_SELECT'
SPI_LB_WAVES_SELECT__enumvalues = {
0: 'HS_GS',
1: 'VS_PS',
2: 'CS_NA',
3: 'SPI_LB_WAVES_RSVD',
}
HS_GS = 0
VS_PS = 1
CS_NA = 2
SPI_LB_WAVES_RSVD = 3
SPI_LB_WAVES_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_CLAMP'
SQ_TEX_CLAMP__enumvalues = {
0: 'SQ_TEX_WRAP',
1: 'SQ_TEX_MIRROR',
2: 'SQ_TEX_CLAMP_LAST_TEXEL',
3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL',
4: 'SQ_TEX_CLAMP_HALF_BORDER',
5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER',
6: 'SQ_TEX_CLAMP_BORDER',
7: 'SQ_TEX_MIRROR_ONCE_BORDER',
}
SQ_TEX_WRAP = 0
SQ_TEX_MIRROR = 1
SQ_TEX_CLAMP_LAST_TEXEL = 2
SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3
SQ_TEX_CLAMP_HALF_BORDER = 4
SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5
SQ_TEX_CLAMP_BORDER = 6
SQ_TEX_MIRROR_ONCE_BORDER = 7
SQ_TEX_CLAMP = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_XY_FILTER'
SQ_TEX_XY_FILTER__enumvalues = {
0: 'SQ_TEX_XY_FILTER_POINT',
1: 'SQ_TEX_XY_FILTER_BILINEAR',
2: 'SQ_TEX_XY_FILTER_ANISO_POINT',
3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR',
}
SQ_TEX_XY_FILTER_POINT = 0
SQ_TEX_XY_FILTER_BILINEAR = 1
SQ_TEX_XY_FILTER_ANISO_POINT = 2
SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3
SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_Z_FILTER'
SQ_TEX_Z_FILTER__enumvalues = {
0: 'SQ_TEX_Z_FILTER_NONE',
1: 'SQ_TEX_Z_FILTER_POINT',
2: 'SQ_TEX_Z_FILTER_LINEAR',
}
SQ_TEX_Z_FILTER_NONE = 0
SQ_TEX_Z_FILTER_POINT = 1
SQ_TEX_Z_FILTER_LINEAR = 2
SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_MIP_FILTER'
SQ_TEX_MIP_FILTER__enumvalues = {
0: 'SQ_TEX_MIP_FILTER_NONE',
1: 'SQ_TEX_MIP_FILTER_POINT',
2: 'SQ_TEX_MIP_FILTER_LINEAR',
3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ',
}
SQ_TEX_MIP_FILTER_NONE = 0
SQ_TEX_MIP_FILTER_POINT = 1
SQ_TEX_MIP_FILTER_LINEAR = 2
SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3
SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_ANISO_RATIO'
SQ_TEX_ANISO_RATIO__enumvalues = {
0: 'SQ_TEX_ANISO_RATIO_1',
1: 'SQ_TEX_ANISO_RATIO_2',
2: 'SQ_TEX_ANISO_RATIO_4',
3: 'SQ_TEX_ANISO_RATIO_8',
4: 'SQ_TEX_ANISO_RATIO_16',
}
SQ_TEX_ANISO_RATIO_1 = 0
SQ_TEX_ANISO_RATIO_2 = 1
SQ_TEX_ANISO_RATIO_4 = 2
SQ_TEX_ANISO_RATIO_8 = 3
SQ_TEX_ANISO_RATIO_16 = 4
SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_DEPTH_COMPARE'
SQ_TEX_DEPTH_COMPARE__enumvalues = {
0: 'SQ_TEX_DEPTH_COMPARE_NEVER',
1: 'SQ_TEX_DEPTH_COMPARE_LESS',
2: 'SQ_TEX_DEPTH_COMPARE_EQUAL',
3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL',
4: 'SQ_TEX_DEPTH_COMPARE_GREATER',
5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL',
6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL',
7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS',
}
SQ_TEX_DEPTH_COMPARE_NEVER = 0
SQ_TEX_DEPTH_COMPARE_LESS = 1
SQ_TEX_DEPTH_COMPARE_EQUAL = 2
SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3
SQ_TEX_DEPTH_COMPARE_GREATER = 4
SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5
SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6
SQ_TEX_DEPTH_COMPARE_ALWAYS = 7
SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_BORDER_COLOR'
SQ_TEX_BORDER_COLOR__enumvalues = {
0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK',
1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK',
2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE',
3: 'SQ_TEX_BORDER_COLOR_REGISTER',
}
SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0
SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1
SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2
SQ_TEX_BORDER_COLOR_REGISTER = 3
SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum
# values for enumeration 'SQ_RSRC_BUF_TYPE'
SQ_RSRC_BUF_TYPE__enumvalues = {
0: 'SQ_RSRC_BUF',
1: 'SQ_RSRC_BUF_RSVD_1',
2: 'SQ_RSRC_BUF_RSVD_2',
3: 'SQ_RSRC_BUF_RSVD_3',
}
SQ_RSRC_BUF = 0
SQ_RSRC_BUF_RSVD_1 = 1
SQ_RSRC_BUF_RSVD_2 = 2
SQ_RSRC_BUF_RSVD_3 = 3
SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_RSRC_IMG_TYPE'
SQ_RSRC_IMG_TYPE__enumvalues = {
0: 'SQ_RSRC_IMG_RSVD_0',
1: 'SQ_RSRC_IMG_RSVD_1',
2: 'SQ_RSRC_IMG_RSVD_2',
3: 'SQ_RSRC_IMG_RSVD_3',
4: 'SQ_RSRC_IMG_RSVD_4',
5: 'SQ_RSRC_IMG_RSVD_5',
6: 'SQ_RSRC_IMG_RSVD_6',
7: 'SQ_RSRC_IMG_RSVD_7',
8: 'SQ_RSRC_IMG_1D',
9: 'SQ_RSRC_IMG_2D',
10: 'SQ_RSRC_IMG_3D',
11: 'SQ_RSRC_IMG_CUBE',
12: 'SQ_RSRC_IMG_1D_ARRAY',
13: 'SQ_RSRC_IMG_2D_ARRAY',
14: 'SQ_RSRC_IMG_2D_MSAA',
15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY',
}
SQ_RSRC_IMG_RSVD_0 = 0
SQ_RSRC_IMG_RSVD_1 = 1
SQ_RSRC_IMG_RSVD_2 = 2
SQ_RSRC_IMG_RSVD_3 = 3
SQ_RSRC_IMG_RSVD_4 = 4
SQ_RSRC_IMG_RSVD_5 = 5
SQ_RSRC_IMG_RSVD_6 = 6
SQ_RSRC_IMG_RSVD_7 = 7
SQ_RSRC_IMG_1D = 8
SQ_RSRC_IMG_2D = 9
SQ_RSRC_IMG_3D = 10
SQ_RSRC_IMG_CUBE = 11
SQ_RSRC_IMG_1D_ARRAY = 12
SQ_RSRC_IMG_2D_ARRAY = 13
SQ_RSRC_IMG_2D_MSAA = 14
SQ_RSRC_IMG_2D_MSAA_ARRAY = 15
SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_RSRC_FLAT_TYPE'
SQ_RSRC_FLAT_TYPE__enumvalues = {
0: 'SQ_RSRC_FLAT_RSVD_0',
1: 'SQ_RSRC_FLAT',
2: 'SQ_RSRC_FLAT_RSVD_2',
3: 'SQ_RSRC_FLAT_RSVD_3',
}
SQ_RSRC_FLAT_RSVD_0 = 0
SQ_RSRC_FLAT = 1
SQ_RSRC_FLAT_RSVD_2 = 2
SQ_RSRC_FLAT_RSVD_3 = 3
SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_IMG_FILTER_TYPE'
SQ_IMG_FILTER_TYPE__enumvalues = {
0: 'SQ_IMG_FILTER_MODE_BLEND',
1: 'SQ_IMG_FILTER_MODE_MIN',
2: 'SQ_IMG_FILTER_MODE_MAX',
}
SQ_IMG_FILTER_MODE_BLEND = 0
SQ_IMG_FILTER_MODE_MIN = 1
SQ_IMG_FILTER_MODE_MAX = 2
SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_SEL_XYZW01'
SQ_SEL_XYZW01__enumvalues = {
0: 'SQ_SEL_0',
1: 'SQ_SEL_1',
2: 'SQ_SEL_N_BC_1',
3: 'SQ_SEL_RESERVED_1',
4: 'SQ_SEL_X',
5: 'SQ_SEL_Y',
6: 'SQ_SEL_Z',
7: 'SQ_SEL_W',
}
SQ_SEL_0 = 0
SQ_SEL_1 = 1
SQ_SEL_N_BC_1 = 2
SQ_SEL_RESERVED_1 = 3
SQ_SEL_X = 4
SQ_SEL_Y = 5
SQ_SEL_Z = 6
SQ_SEL_W = 7
SQ_SEL_XYZW01 = ctypes.c_uint32 # enum
# values for enumeration 'SQ_OOB_SELECT'
SQ_OOB_SELECT__enumvalues = {
0: 'SQ_OOB_INDEX_AND_OFFSET',
1: 'SQ_OOB_INDEX_ONLY',
2: 'SQ_OOB_NUM_RECORDS_0',
3: 'SQ_OOB_COMPLETE',
}
SQ_OOB_INDEX_AND_OFFSET = 0
SQ_OOB_INDEX_ONLY = 1
SQ_OOB_NUM_RECORDS_0 = 2
SQ_OOB_COMPLETE = 3
SQ_OOB_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'SQ_WAVE_TYPE'
SQ_WAVE_TYPE__enumvalues = {
0: 'SQ_WAVE_TYPE_PS',
1: 'SQ_WAVE_TYPE_VS',
2: 'SQ_WAVE_TYPE_GS',
3: 'SQ_WAVE_TYPE_ES',
4: 'SQ_WAVE_TYPE_HS',
5: 'SQ_WAVE_TYPE_LS',
6: 'SQ_WAVE_TYPE_CS',
7: 'SQ_WAVE_TYPE_PS1',
8: 'SQ_WAVE_TYPE_PS2',
9: 'SQ_WAVE_TYPE_PS3',
}
SQ_WAVE_TYPE_PS = 0
SQ_WAVE_TYPE_VS = 1
SQ_WAVE_TYPE_GS = 2
SQ_WAVE_TYPE_ES = 3
SQ_WAVE_TYPE_HS = 4
SQ_WAVE_TYPE_LS = 5
SQ_WAVE_TYPE_CS = 6
SQ_WAVE_TYPE_PS1 = 7
SQ_WAVE_TYPE_PS2 = 8
SQ_WAVE_TYPE_PS3 = 9
SQ_WAVE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_PERF_SEL'
SQ_PERF_SEL__enumvalues = {
0: 'SQ_PERF_SEL_NONE',
1: 'SQ_PERF_SEL_ACCUM_PREV',
2: 'SQ_PERF_SEL_CYCLES',
3: 'SQ_PERF_SEL_BUSY_CYCLES',
4: 'SQ_PERF_SEL_WAVES',
5: 'SQ_PERF_SEL_WAVES_32',
6: 'SQ_PERF_SEL_WAVES_64',
7: 'SQ_PERF_SEL_LEVEL_WAVES',
8: 'SQ_PERF_SEL_ITEMS',
9: 'SQ_PERF_SEL_WAVE32_ITEMS',
10: 'SQ_PERF_SEL_WAVE64_ITEMS',
11: 'SQ_PERF_SEL_QUADS',
12: 'SQ_PERF_SEL_EVENTS',
13: 'SQ_PERF_SEL_WAVES_EQ_64',
14: 'SQ_PERF_SEL_WAVES_LT_64',
15: 'SQ_PERF_SEL_WAVES_LT_48',
16: 'SQ_PERF_SEL_WAVES_LT_32',
17: 'SQ_PERF_SEL_WAVES_LT_16',
18: 'SQ_PERF_SEL_WAVES_RESTORED',
19: 'SQ_PERF_SEL_WAVES_SAVED',
20: 'SQ_PERF_SEL_MSG',
21: 'SQ_PERF_SEL_MSG_GSCNT',
22: 'SQ_PERF_SEL_MSG_INTERRUPT',
23: 'SQ_PERF_SEL_Reserved_1',
24: 'SQ_PERF_SEL_Reserved_2',
25: 'SQ_PERF_SEL_Reserved_3',
26: 'SQ_PERF_SEL_WAVE_CYCLES',
27: 'SQ_PERF_SEL_WAVE_READY',
28: 'SQ_PERF_SEL_WAIT_INST_ANY',
29: 'SQ_PERF_SEL_WAIT_INST_VALU',
30: 'SQ_PERF_SEL_WAIT_INST_SCA',
31: 'SQ_PERF_SEL_WAIT_INST_LDS',
32: 'SQ_PERF_SEL_WAIT_INST_TEX',
33: 'SQ_PERF_SEL_WAIT_INST_FLAT',
34: 'SQ_PERF_SEL_WAIT_INST_VMEM',
35: 'SQ_PERF_SEL_WAIT_INST_EXP_GDS',
36: 'SQ_PERF_SEL_WAIT_INST_BR_MSG',
37: 'SQ_PERF_SEL_WAIT_ANY',
38: 'SQ_PERF_SEL_WAIT_CNT_ANY',
39: 'SQ_PERF_SEL_WAIT_CNT_VMVS',
40: 'SQ_PERF_SEL_WAIT_CNT_LGKM',
41: 'SQ_PERF_SEL_WAIT_CNT_EXP',
42: 'SQ_PERF_SEL_WAIT_TTRACE',
43: 'SQ_PERF_SEL_WAIT_IFETCH',
44: 'SQ_PERF_SEL_WAIT_BARRIER',
45: 'SQ_PERF_SEL_WAIT_EXP_ALLOC',
46: 'SQ_PERF_SEL_WAIT_SLEEP',
47: 'SQ_PERF_SEL_WAIT_SLEEP_XNACK',
48: 'SQ_PERF_SEL_WAIT_OTHER',
49: 'SQ_PERF_SEL_INSTS_ALL',
50: 'SQ_PERF_SEL_INSTS_BRANCH',
51: 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN',
52: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN',
53: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS',
54: 'SQ_PERF_SEL_INSTS_EXP_GDS',
55: 'SQ_PERF_SEL_INSTS_GDS',
56: 'SQ_PERF_SEL_INSTS_EXP',
57: 'SQ_PERF_SEL_INSTS_FLAT',
58: 'SQ_PERF_SEL_Reserved_4',
59: 'SQ_PERF_SEL_INSTS_LDS',
60: 'SQ_PERF_SEL_INSTS_SALU',
61: 'SQ_PERF_SEL_INSTS_SMEM',
62: 'SQ_PERF_SEL_INSTS_SMEM_NORM',
63: 'SQ_PERF_SEL_INSTS_SENDMSG',
64: 'SQ_PERF_SEL_INSTS_VALU',
65: 'SQ_PERF_SEL_Reserved_17',
66: 'SQ_PERF_SEL_INSTS_VALU_TRANS32',
67: 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC',
68: 'SQ_PERF_SEL_INSTS_TEX',
69: 'SQ_PERF_SEL_INSTS_TEX_LOAD',
70: 'SQ_PERF_SEL_INSTS_TEX_STORE',
71: 'SQ_PERF_SEL_INSTS_WAVE32',
72: 'SQ_PERF_SEL_INSTS_WAVE32_FLAT',
73: 'SQ_PERF_SEL_Reserved_5',
74: 'SQ_PERF_SEL_INSTS_WAVE32_LDS',
75: 'SQ_PERF_SEL_INSTS_WAVE32_VALU',
76: 'SQ_PERF_SEL_Reserved_16',
77: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32',
78: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC',
79: 'SQ_PERF_SEL_INSTS_WAVE32_TEX',
80: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD',
81: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE',
82: 'SQ_PERF_SEL_ITEM_CYCLES_VALU',
83: 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES',
84: 'SQ_PERF_SEL_WAVE32_INSTS',
85: 'SQ_PERF_SEL_WAVE64_INSTS',
86: 'SQ_PERF_SEL_Reserved_18',
87: 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED',
88: 'SQ_PERF_SEL_WAVE64_HALF_SKIP',
89: 'SQ_PERF_SEL_INSTS_TEX_REPLAY',
90: 'SQ_PERF_SEL_INSTS_SMEM_REPLAY',
91: 'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY',
92: 'SQ_PERF_SEL_INSTS_FLAT_REPLAY',
93: 'SQ_PERF_SEL_XNACK_ALL',
94: 'SQ_PERF_SEL_XNACK_FIRST',
95: 'SQ_PERF_SEL_INSTS_VALU_LDS_DIRECT_RD',
96: 'SQ_PERF_SEL_INSTS_VALU_VINTRP_OP',
97: 'SQ_PERF_SEL_INST_LEVEL_EXP',
98: 'SQ_PERF_SEL_INST_LEVEL_GDS',
99: 'SQ_PERF_SEL_INST_LEVEL_LDS',
100: 'SQ_PERF_SEL_INST_LEVEL_SMEM',
101: 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD',
102: 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE',
103: 'SQ_PERF_SEL_IFETCH_REQS',
104: 'SQ_PERF_SEL_IFETCH_LEVEL',
105: 'SQ_PERF_SEL_IFETCH_XNACK',
106: 'SQ_PERF_SEL_Reserved_6',
107: 'SQ_PERF_SEL_Reserved_7',
108: 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL',
109: 'SQ_PERF_SEL_VALU_SGATHER_STALL',
110: 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL',
111: 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL',
112: 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL',
113: 'SQ_PERF_SEL_SALU_SGATHER_STALL',
114: 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL',
115: 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL',
116: 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL',
117: 'SQ_PERF_SEL_INST_CYCLES_VALU',
118: 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32',
119: 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC',
120: 'SQ_PERF_SEL_INST_CYCLES_VMEM',
121: 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD',
122: 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE',
123: 'SQ_PERF_SEL_INST_CYCLES_LDS',
124: 'SQ_PERF_SEL_INST_CYCLES_TEX',
125: 'SQ_PERF_SEL_INST_CYCLES_FLAT',
126: 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS',
127: 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL',
128: 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL',
129: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL',
130: 'SQ_PERF_SEL_Reserved_8',
131: 'SQ_PERF_SEL_Reserved_9',
132: 'SQ_PERF_SEL_Reserved_10',
133: 'SQ_PERF_SEL_Reserved_11',
134: 'SQ_PERF_SEL_Reserved_12',
135: 'SQ_PERF_SEL_Reserved_13',
136: 'SQ_PERF_SEL_Reserved_14',
137: 'SQ_PERF_SEL_VMEM_BUS_ACTIVE',
138: 'SQ_PERF_SEL_VMEM_BUS_STALL',
139: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL',
140: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL',
141: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL',
142: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL',
143: 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY',
144: 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY',
145: 'SQ_PERF_SEL_Reserved_15',
146: 'SQ_PERF_SEL_SALU_PIPE_STALL',
147: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES',
148: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_STALL',
149: 'SQ_PERF_SEL_MSG_BUS_BUSY',
150: 'SQ_PERF_SEL_EXP_REQ_BUS_STALL',
151: 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY',
152: 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY',
153: 'SQ_PERF_SEL_EXP_BUS0_BUSY',
154: 'SQ_PERF_SEL_EXP_BUS1_BUSY',
155: 'SQ_PERF_SEL_INST_CACHE_REQS',
156: 'SQ_PERF_SEL_INST_CACHE_REQ_STALL',
157: 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VALU',
158: 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_SALU',
159: 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VMEM',
160: 'SQ_PERF_SEL_USER0',
161: 'SQ_PERF_SEL_USER1',
162: 'SQ_PERF_SEL_USER2',
163: 'SQ_PERF_SEL_USER3',
164: 'SQ_PERF_SEL_USER4',
165: 'SQ_PERF_SEL_USER5',
166: 'SQ_PERF_SEL_USER6',
167: 'SQ_PERF_SEL_USER7',
168: 'SQ_PERF_SEL_USER8',
169: 'SQ_PERF_SEL_USER9',
170: 'SQ_PERF_SEL_USER10',
171: 'SQ_PERF_SEL_USER11',
172: 'SQ_PERF_SEL_USER12',
173: 'SQ_PERF_SEL_USER13',
174: 'SQ_PERF_SEL_USER14',
175: 'SQ_PERF_SEL_USER15',
176: 'SQ_PERF_SEL_USER_LEVEL0',
177: 'SQ_PERF_SEL_USER_LEVEL1',
178: 'SQ_PERF_SEL_USER_LEVEL2',
179: 'SQ_PERF_SEL_USER_LEVEL3',
180: 'SQ_PERF_SEL_USER_LEVEL4',
181: 'SQ_PERF_SEL_USER_LEVEL5',
182: 'SQ_PERF_SEL_USER_LEVEL6',
183: 'SQ_PERF_SEL_USER_LEVEL7',
184: 'SQ_PERF_SEL_USER_LEVEL8',
185: 'SQ_PERF_SEL_USER_LEVEL9',
186: 'SQ_PERF_SEL_USER_LEVEL10',
187: 'SQ_PERF_SEL_USER_LEVEL11',
188: 'SQ_PERF_SEL_USER_LEVEL12',
189: 'SQ_PERF_SEL_USER_LEVEL13',
190: 'SQ_PERF_SEL_USER_LEVEL14',
191: 'SQ_PERF_SEL_USER_LEVEL15',
192: 'SQ_PERF_SEL_VALU_RETURN_SDST',
193: 'SQ_PERF_SEL_VMEM_SECOND_TRY_USED',
194: 'SQ_PERF_SEL_VMEM_SECOND_TRY_STALL',
195: 'SQ_PERF_SEL_DUMMY_END',
255: 'SQ_PERF_SEL_DUMMY_LAST',
256: 'SQG_PERF_SEL_UTCL0_TRANSLATION_MISS',
257: 'SQG_PERF_SEL_UTCL0_PERMISSION_MISS',
258: 'SQG_PERF_SEL_UTCL0_TRANSLATION_HIT',
259: 'SQG_PERF_SEL_UTCL0_REQUEST',
260: 'SQG_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL',
261: 'SQG_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX',
262: 'SQG_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT',
263: 'SQG_PERF_SEL_UTCL0_LFIFO_FULL',
264: 'SQG_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES',
265: 'SQG_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS',
266: 'SQG_PERF_SEL_UTCL0_HIT_FIFO_FULL',
267: 'SQG_PERF_SEL_UTCL0_UTCL1_REQ',
268: 'SQG_PERF_SEL_TLB_SHOOTDOWN',
269: 'SQG_PERF_SEL_TLB_SHOOTDOWN_CYCLES',
270: 'SQG_PERF_SEL_TTRACE_REQS',
271: 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS',
272: 'SQG_PERF_SEL_TTRACE_STALL',
273: 'SQG_PERF_SEL_TTRACE_LOST_PACKETS',
274: 'SQG_PERF_SEL_DUMMY_LAST',
275: 'SQC_PERF_SEL_POWER_VALU',
276: 'SQC_PERF_SEL_POWER_VALU0',
277: 'SQC_PERF_SEL_POWER_VALU1',
278: 'SQC_PERF_SEL_POWER_VALU2',
279: 'SQC_PERF_SEL_POWER_GPR_RD',
280: 'SQC_PERF_SEL_POWER_GPR_WR',
281: 'SQC_PERF_SEL_POWER_LDS_BUSY',
282: 'SQC_PERF_SEL_POWER_ALU_BUSY',
283: 'SQC_PERF_SEL_POWER_TEX_BUSY',
284: 'SQC_PERF_SEL_PT_POWER_STALL',
285: 'SQC_PERF_SEL_LDS_BANK_CONFLICT',
286: 'SQC_PERF_SEL_LDS_ADDR_CONFLICT',
287: 'SQC_PERF_SEL_LDS_UNALIGNED_STALL',
288: 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS',
289: 'SQC_PERF_SEL_LDS_ATOMIC_RETURN',
290: 'SQC_PERF_SEL_LDS_IDX_ACTIVE',
291: 'SQC_PERF_SEL_LDS_DATA_FIFO_FULL',
292: 'SQC_PERF_SEL_LDS_CMD_FIFO_FULL',
293: 'SQC_PERF_SEL_LDS_ADDR_STALL',
294: 'SQC_PERF_SEL_LDS_ADDR_ACTIVE',
295: 'SQC_PERF_SEL_LDS_DIRECT_FIFO_FULL_STALL',
296: 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD',
297: 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD',
298: 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL',
299: 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES',
300: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES',
301: 'SQC_PERF_SEL_ICACHE_REQ',
302: 'SQC_PERF_SEL_ICACHE_HITS',
303: 'SQC_PERF_SEL_ICACHE_MISSES',
304: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE',
305: 'SQC_PERF_SEL_ICACHE_INVAL_INST',
306: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC',
307: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL',
308: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL',
309: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL',
310: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL',
311: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL',
312: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY',
313: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB',
314: 'SQC_PERF_SEL_ICACHE_INPUT_VALIDB',
315: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY',
316: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB',
317: 'SQC_PERF_SEL_DCACHE_INPUT_VALIDB',
318: 'SQC_PERF_SEL_TC_REQ',
319: 'SQC_PERF_SEL_TC_INST_REQ',
320: 'SQC_PERF_SEL_TC_DATA_READ_REQ',
321: 'SQC_PERF_SEL_TC_DATA_WRITE_REQ',
322: 'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ',
323: 'SQC_PERF_SEL_TC_STALL',
324: 'SQC_PERF_SEL_TC_STARVE',
325: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT',
326: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB',
327: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED',
328: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO',
329: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX',
330: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT',
331: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO',
332: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO',
333: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF',
334: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT',
335: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES',
336: 'SQC_PERF_SEL_DCACHE_REQ',
337: 'SQC_PERF_SEL_DCACHE_HITS',
338: 'SQC_PERF_SEL_DCACHE_MISSES',
339: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE',
340: 'SQC_PERF_SEL_DCACHE_INVAL_INST',
341: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC',
342: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ',
343: 'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE',
344: 'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE',
345: 'SQC_PERF_SEL_DCACHE_ATOMIC',
346: 'SQC_PERF_SEL_DCACHE_WB_INST',
347: 'SQC_PERF_SEL_DCACHE_WB_ASYNC',
348: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT',
349: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB',
350: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED',
351: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO',
352: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX',
353: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT',
354: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT',
355: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED',
356: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE',
357: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT',
358: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH',
359: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE',
360: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO',
361: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO',
362: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF',
363: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT',
364: 'SQC_PERF_SEL_DCACHE_REQ_READ_1',
365: 'SQC_PERF_SEL_DCACHE_REQ_READ_2',
366: 'SQC_PERF_SEL_DCACHE_REQ_READ_4',
367: 'SQC_PERF_SEL_DCACHE_REQ_READ_8',
368: 'SQC_PERF_SEL_DCACHE_REQ_READ_16',
369: 'SQC_PERF_SEL_DCACHE_REQ_TIME',
370: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_1',
371: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_2',
372: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_4',
373: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE',
374: 'SQC_PERF_SEL_SQ_DCACHE_REQS',
375: 'SQC_PERF_SEL_DCACHE_FLAT_REQ',
376: 'SQC_PERF_SEL_DCACHE_NONFLAT_REQ',
377: 'SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_MISS',
378: 'SQC_PERF_SEL_ICACHE_UTCL0_PERMISSION_MISS',
379: 'SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_HIT',
380: 'SQC_PERF_SEL_ICACHE_UTCL0_REQUEST',
381: 'SQC_PERF_SEL_ICACHE_UTCL0_XNACK',
382: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_INFLIGHT_MAX',
383: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_LRU_INFLIGHT',
384: 'SQC_PERF_SEL_ICACHE_UTCL0_LFIFO_FULL',
385: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_LFIFO_NOT_RES',
386: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS',
387: 'SQC_PERF_SEL_ICACHE_UTCL0_UTCL1_INFLIGHT',
388: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_MISSFIFO_FULL',
389: 'SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_MISS',
390: 'SQC_PERF_SEL_DCACHE_UTCL0_PERMISSION_MISS',
391: 'SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_HIT',
392: 'SQC_PERF_SEL_DCACHE_UTCL0_REQUEST',
393: 'SQC_PERF_SEL_DCACHE_UTCL0_XNACK',
394: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_INFLIGHT_MAX',
395: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_LRU_INFLIGHT',
396: 'SQC_PERF_SEL_DCACHE_UTCL0_LFIFO_FULL',
397: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_LFIFO_NOT_RES',
398: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS',
399: 'SQC_PERF_SEL_DCACHE_UTCL0_UTCL1_INFLIGHT',
400: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_MISSFIFO_FULL',
401: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_MULTI_MISS',
402: 'SQC_PERF_SEL_DCACHE_UTCL0_HIT_FIFO_FULL',
403: 'SQC_PERF_SEL_ICACHE_UTCL0_INFLIGHT_LEVEL',
404: 'SQC_PERF_SEL_ICACHE_UTCL0_ALL_REQ',
405: 'SQC_PERF_SEL_ICACHE_UTCL1_INFLIGHT_LEVEL',
406: 'SQC_PERF_SEL_ICACHE_UTCL1_ALL_REQ',
407: 'SQC_PERF_SEL_DCACHE_UTCL0_INFLIGHT_LEVEL',
408: 'SQC_PERF_SEL_DCACHE_UTCL0_ALL_REQ',
409: 'SQC_PERF_SEL_DCACHE_UTCL1_INFLIGHT_LEVEL',
410: 'SQC_PERF_SEL_DCACHE_UTCL1_ALL_REQ',
411: 'SQC_PERF_SEL_ICACHE_GCR',
412: 'SQC_PERF_SEL_ICACHE_GCR_HITS',
413: 'SQC_PERF_SEL_DCACHE_GCR',
414: 'SQC_PERF_SEL_DCACHE_GCR_HITS',
415: 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE',
416: 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE',
417: 'SQC_PERF_SEL_DCACHE_GCR_WRITEBACK',
418: 'SQC_PERF_SEL_DUMMY_LAST',
448: 'SP_PERF_SEL_DUMMY_BEGIN',
511: 'SP_PERF_SEL_DUMMY_LAST',
}
SQ_PERF_SEL_NONE = 0
SQ_PERF_SEL_ACCUM_PREV = 1
SQ_PERF_SEL_CYCLES = 2
SQ_PERF_SEL_BUSY_CYCLES = 3
SQ_PERF_SEL_WAVES = 4
SQ_PERF_SEL_WAVES_32 = 5
SQ_PERF_SEL_WAVES_64 = 6
SQ_PERF_SEL_LEVEL_WAVES = 7
SQ_PERF_SEL_ITEMS = 8
SQ_PERF_SEL_WAVE32_ITEMS = 9
SQ_PERF_SEL_WAVE64_ITEMS = 10
SQ_PERF_SEL_QUADS = 11
SQ_PERF_SEL_EVENTS = 12
SQ_PERF_SEL_WAVES_EQ_64 = 13
SQ_PERF_SEL_WAVES_LT_64 = 14
SQ_PERF_SEL_WAVES_LT_48 = 15
SQ_PERF_SEL_WAVES_LT_32 = 16
SQ_PERF_SEL_WAVES_LT_16 = 17
SQ_PERF_SEL_WAVES_RESTORED = 18
SQ_PERF_SEL_WAVES_SAVED = 19
SQ_PERF_SEL_MSG = 20
SQ_PERF_SEL_MSG_GSCNT = 21
SQ_PERF_SEL_MSG_INTERRUPT = 22
SQ_PERF_SEL_Reserved_1 = 23
SQ_PERF_SEL_Reserved_2 = 24
SQ_PERF_SEL_Reserved_3 = 25
SQ_PERF_SEL_WAVE_CYCLES = 26
SQ_PERF_SEL_WAVE_READY = 27
SQ_PERF_SEL_WAIT_INST_ANY = 28
SQ_PERF_SEL_WAIT_INST_VALU = 29
SQ_PERF_SEL_WAIT_INST_SCA = 30
SQ_PERF_SEL_WAIT_INST_LDS = 31
SQ_PERF_SEL_WAIT_INST_TEX = 32
SQ_PERF_SEL_WAIT_INST_FLAT = 33
SQ_PERF_SEL_WAIT_INST_VMEM = 34
SQ_PERF_SEL_WAIT_INST_EXP_GDS = 35
SQ_PERF_SEL_WAIT_INST_BR_MSG = 36
SQ_PERF_SEL_WAIT_ANY = 37
SQ_PERF_SEL_WAIT_CNT_ANY = 38
SQ_PERF_SEL_WAIT_CNT_VMVS = 39
SQ_PERF_SEL_WAIT_CNT_LGKM = 40
SQ_PERF_SEL_WAIT_CNT_EXP = 41
SQ_PERF_SEL_WAIT_TTRACE = 42
SQ_PERF_SEL_WAIT_IFETCH = 43
SQ_PERF_SEL_WAIT_BARRIER = 44
SQ_PERF_SEL_WAIT_EXP_ALLOC = 45
SQ_PERF_SEL_WAIT_SLEEP = 46
SQ_PERF_SEL_WAIT_SLEEP_XNACK = 47
SQ_PERF_SEL_WAIT_OTHER = 48
SQ_PERF_SEL_INSTS_ALL = 49
SQ_PERF_SEL_INSTS_BRANCH = 50
SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 51
SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 52
SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 53
SQ_PERF_SEL_INSTS_EXP_GDS = 54
SQ_PERF_SEL_INSTS_GDS = 55
SQ_PERF_SEL_INSTS_EXP = 56
SQ_PERF_SEL_INSTS_FLAT = 57
SQ_PERF_SEL_Reserved_4 = 58
SQ_PERF_SEL_INSTS_LDS = 59
SQ_PERF_SEL_INSTS_SALU = 60
SQ_PERF_SEL_INSTS_SMEM = 61
SQ_PERF_SEL_INSTS_SMEM_NORM = 62
SQ_PERF_SEL_INSTS_SENDMSG = 63
SQ_PERF_SEL_INSTS_VALU = 64
SQ_PERF_SEL_Reserved_17 = 65
SQ_PERF_SEL_INSTS_VALU_TRANS32 = 66
SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 67
SQ_PERF_SEL_INSTS_TEX = 68
SQ_PERF_SEL_INSTS_TEX_LOAD = 69
SQ_PERF_SEL_INSTS_TEX_STORE = 70
SQ_PERF_SEL_INSTS_WAVE32 = 71
SQ_PERF_SEL_INSTS_WAVE32_FLAT = 72
SQ_PERF_SEL_Reserved_5 = 73
SQ_PERF_SEL_INSTS_WAVE32_LDS = 74
SQ_PERF_SEL_INSTS_WAVE32_VALU = 75
SQ_PERF_SEL_Reserved_16 = 76
SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 77
SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 78
SQ_PERF_SEL_INSTS_WAVE32_TEX = 79
SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 80
SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 81
SQ_PERF_SEL_ITEM_CYCLES_VALU = 82
SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 83
SQ_PERF_SEL_WAVE32_INSTS = 84
SQ_PERF_SEL_WAVE64_INSTS = 85
SQ_PERF_SEL_Reserved_18 = 86
SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 87
SQ_PERF_SEL_WAVE64_HALF_SKIP = 88
SQ_PERF_SEL_INSTS_TEX_REPLAY = 89
SQ_PERF_SEL_INSTS_SMEM_REPLAY = 90
SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 91
SQ_PERF_SEL_INSTS_FLAT_REPLAY = 92
SQ_PERF_SEL_XNACK_ALL = 93
SQ_PERF_SEL_XNACK_FIRST = 94
SQ_PERF_SEL_INSTS_VALU_LDS_DIRECT_RD = 95
SQ_PERF_SEL_INSTS_VALU_VINTRP_OP = 96
SQ_PERF_SEL_INST_LEVEL_EXP = 97
SQ_PERF_SEL_INST_LEVEL_GDS = 98
SQ_PERF_SEL_INST_LEVEL_LDS = 99
SQ_PERF_SEL_INST_LEVEL_SMEM = 100
SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 101
SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 102
SQ_PERF_SEL_IFETCH_REQS = 103
SQ_PERF_SEL_IFETCH_LEVEL = 104
SQ_PERF_SEL_IFETCH_XNACK = 105
SQ_PERF_SEL_Reserved_6 = 106
SQ_PERF_SEL_Reserved_7 = 107
SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 108
SQ_PERF_SEL_VALU_SGATHER_STALL = 109
SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 110
SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 111
SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 112
SQ_PERF_SEL_SALU_SGATHER_STALL = 113
SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 114
SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 115
SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 116
SQ_PERF_SEL_INST_CYCLES_VALU = 117
SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 118
SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 119
SQ_PERF_SEL_INST_CYCLES_VMEM = 120
SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 121
SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 122
SQ_PERF_SEL_INST_CYCLES_LDS = 123
SQ_PERF_SEL_INST_CYCLES_TEX = 124
SQ_PERF_SEL_INST_CYCLES_FLAT = 125
SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 126
SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 127
SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 128
SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 129
SQ_PERF_SEL_Reserved_8 = 130
SQ_PERF_SEL_Reserved_9 = 131
SQ_PERF_SEL_Reserved_10 = 132
SQ_PERF_SEL_Reserved_11 = 133
SQ_PERF_SEL_Reserved_12 = 134
SQ_PERF_SEL_Reserved_13 = 135
SQ_PERF_SEL_Reserved_14 = 136
SQ_PERF_SEL_VMEM_BUS_ACTIVE = 137
SQ_PERF_SEL_VMEM_BUS_STALL = 138
SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 139
SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 140
SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 141
SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 142
SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 143
SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 144
SQ_PERF_SEL_Reserved_15 = 145
SQ_PERF_SEL_SALU_PIPE_STALL = 146
SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 147
SQ_PERF_SEL_SMEM_DCACHE_RETURN_STALL = 148
SQ_PERF_SEL_MSG_BUS_BUSY = 149
SQ_PERF_SEL_EXP_REQ_BUS_STALL = 150
SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 151
SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 152
SQ_PERF_SEL_EXP_BUS0_BUSY = 153
SQ_PERF_SEL_EXP_BUS1_BUSY = 154
SQ_PERF_SEL_INST_CACHE_REQS = 155
SQ_PERF_SEL_INST_CACHE_REQ_STALL = 156
SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VALU = 157
SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_SALU = 158
SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VMEM = 159
SQ_PERF_SEL_USER0 = 160
SQ_PERF_SEL_USER1 = 161
SQ_PERF_SEL_USER2 = 162
SQ_PERF_SEL_USER3 = 163
SQ_PERF_SEL_USER4 = 164
SQ_PERF_SEL_USER5 = 165
SQ_PERF_SEL_USER6 = 166
SQ_PERF_SEL_USER7 = 167
SQ_PERF_SEL_USER8 = 168
SQ_PERF_SEL_USER9 = 169
SQ_PERF_SEL_USER10 = 170
SQ_PERF_SEL_USER11 = 171
SQ_PERF_SEL_USER12 = 172
SQ_PERF_SEL_USER13 = 173
SQ_PERF_SEL_USER14 = 174
SQ_PERF_SEL_USER15 = 175
SQ_PERF_SEL_USER_LEVEL0 = 176
SQ_PERF_SEL_USER_LEVEL1 = 177
SQ_PERF_SEL_USER_LEVEL2 = 178
SQ_PERF_SEL_USER_LEVEL3 = 179
SQ_PERF_SEL_USER_LEVEL4 = 180
SQ_PERF_SEL_USER_LEVEL5 = 181
SQ_PERF_SEL_USER_LEVEL6 = 182
SQ_PERF_SEL_USER_LEVEL7 = 183
SQ_PERF_SEL_USER_LEVEL8 = 184
SQ_PERF_SEL_USER_LEVEL9 = 185
SQ_PERF_SEL_USER_LEVEL10 = 186
SQ_PERF_SEL_USER_LEVEL11 = 187
SQ_PERF_SEL_USER_LEVEL12 = 188
SQ_PERF_SEL_USER_LEVEL13 = 189
SQ_PERF_SEL_USER_LEVEL14 = 190
SQ_PERF_SEL_USER_LEVEL15 = 191
SQ_PERF_SEL_VALU_RETURN_SDST = 192
SQ_PERF_SEL_VMEM_SECOND_TRY_USED = 193
SQ_PERF_SEL_VMEM_SECOND_TRY_STALL = 194
SQ_PERF_SEL_DUMMY_END = 195
SQ_PERF_SEL_DUMMY_LAST = 255
SQG_PERF_SEL_UTCL0_TRANSLATION_MISS = 256
SQG_PERF_SEL_UTCL0_PERMISSION_MISS = 257
SQG_PERF_SEL_UTCL0_TRANSLATION_HIT = 258
SQG_PERF_SEL_UTCL0_REQUEST = 259
SQG_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 260
SQG_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 261
SQG_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 262
SQG_PERF_SEL_UTCL0_LFIFO_FULL = 263
SQG_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 264
SQG_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 265
SQG_PERF_SEL_UTCL0_HIT_FIFO_FULL = 266
SQG_PERF_SEL_UTCL0_UTCL1_REQ = 267
SQG_PERF_SEL_TLB_SHOOTDOWN = 268
SQG_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 269
SQG_PERF_SEL_TTRACE_REQS = 270
SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 271
SQG_PERF_SEL_TTRACE_STALL = 272
SQG_PERF_SEL_TTRACE_LOST_PACKETS = 273
SQG_PERF_SEL_DUMMY_LAST = 274
SQC_PERF_SEL_POWER_VALU = 275
SQC_PERF_SEL_POWER_VALU0 = 276
SQC_PERF_SEL_POWER_VALU1 = 277
SQC_PERF_SEL_POWER_VALU2 = 278
SQC_PERF_SEL_POWER_GPR_RD = 279
SQC_PERF_SEL_POWER_GPR_WR = 280
SQC_PERF_SEL_POWER_LDS_BUSY = 281
SQC_PERF_SEL_POWER_ALU_BUSY = 282
SQC_PERF_SEL_POWER_TEX_BUSY = 283
SQC_PERF_SEL_PT_POWER_STALL = 284
SQC_PERF_SEL_LDS_BANK_CONFLICT = 285
SQC_PERF_SEL_LDS_ADDR_CONFLICT = 286
SQC_PERF_SEL_LDS_UNALIGNED_STALL = 287
SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 288
SQC_PERF_SEL_LDS_ATOMIC_RETURN = 289
SQC_PERF_SEL_LDS_IDX_ACTIVE = 290
SQC_PERF_SEL_LDS_DATA_FIFO_FULL = 291
SQC_PERF_SEL_LDS_CMD_FIFO_FULL = 292
SQC_PERF_SEL_LDS_ADDR_STALL = 293
SQC_PERF_SEL_LDS_ADDR_ACTIVE = 294
SQC_PERF_SEL_LDS_DIRECT_FIFO_FULL_STALL = 295
SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 296
SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 297
SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 298
SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 299
SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 300
SQC_PERF_SEL_ICACHE_REQ = 301
SQC_PERF_SEL_ICACHE_HITS = 302
SQC_PERF_SEL_ICACHE_MISSES = 303
SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 304
SQC_PERF_SEL_ICACHE_INVAL_INST = 305
SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 306
SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 307
SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 308
SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 309
SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 310
SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 311
SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 312
SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 313
SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 314
SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 315
SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 316
SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 317
SQC_PERF_SEL_TC_REQ = 318
SQC_PERF_SEL_TC_INST_REQ = 319
SQC_PERF_SEL_TC_DATA_READ_REQ = 320
SQC_PERF_SEL_TC_DATA_WRITE_REQ = 321
SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 322
SQC_PERF_SEL_TC_STALL = 323
SQC_PERF_SEL_TC_STARVE = 324
SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 325
SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 326
SQC_PERF_SEL_ICACHE_CACHE_STALLED = 327
SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 328
SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 329
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 330
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 331
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 332
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 333
SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 334
SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 335
SQC_PERF_SEL_DCACHE_REQ = 336
SQC_PERF_SEL_DCACHE_HITS = 337
SQC_PERF_SEL_DCACHE_MISSES = 338
SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 339
SQC_PERF_SEL_DCACHE_INVAL_INST = 340
SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 341
SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 342
SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 343
SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 344
SQC_PERF_SEL_DCACHE_ATOMIC = 345
SQC_PERF_SEL_DCACHE_WB_INST = 346
SQC_PERF_SEL_DCACHE_WB_ASYNC = 347
SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 348
SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 349
SQC_PERF_SEL_DCACHE_CACHE_STALLED = 350
SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO = 351
SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 352
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 353
SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 354
SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 355
SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 356
SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 357
SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 358
SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 359
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 360
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 361
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 362
SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 363
SQC_PERF_SEL_DCACHE_REQ_READ_1 = 364
SQC_PERF_SEL_DCACHE_REQ_READ_2 = 365
SQC_PERF_SEL_DCACHE_REQ_READ_4 = 366
SQC_PERF_SEL_DCACHE_REQ_READ_8 = 367
SQC_PERF_SEL_DCACHE_REQ_READ_16 = 368
SQC_PERF_SEL_DCACHE_REQ_TIME = 369
SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 370
SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 371
SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 372
SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 373
SQC_PERF_SEL_SQ_DCACHE_REQS = 374
SQC_PERF_SEL_DCACHE_FLAT_REQ = 375
SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 376
SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_MISS = 377
SQC_PERF_SEL_ICACHE_UTCL0_PERMISSION_MISS = 378
SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_HIT = 379
SQC_PERF_SEL_ICACHE_UTCL0_REQUEST = 380
SQC_PERF_SEL_ICACHE_UTCL0_XNACK = 381
SQC_PERF_SEL_ICACHE_UTCL0_STALL_INFLIGHT_MAX = 382
SQC_PERF_SEL_ICACHE_UTCL0_STALL_LRU_INFLIGHT = 383
SQC_PERF_SEL_ICACHE_UTCL0_LFIFO_FULL = 384
SQC_PERF_SEL_ICACHE_UTCL0_STALL_LFIFO_NOT_RES = 385
SQC_PERF_SEL_ICACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 386
SQC_PERF_SEL_ICACHE_UTCL0_UTCL1_INFLIGHT = 387
SQC_PERF_SEL_ICACHE_UTCL0_STALL_MISSFIFO_FULL = 388
SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_MISS = 389
SQC_PERF_SEL_DCACHE_UTCL0_PERMISSION_MISS = 390
SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_HIT = 391
SQC_PERF_SEL_DCACHE_UTCL0_REQUEST = 392
SQC_PERF_SEL_DCACHE_UTCL0_XNACK = 393
SQC_PERF_SEL_DCACHE_UTCL0_STALL_INFLIGHT_MAX = 394
SQC_PERF_SEL_DCACHE_UTCL0_STALL_LRU_INFLIGHT = 395
SQC_PERF_SEL_DCACHE_UTCL0_LFIFO_FULL = 396
SQC_PERF_SEL_DCACHE_UTCL0_STALL_LFIFO_NOT_RES = 397
SQC_PERF_SEL_DCACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 398
SQC_PERF_SEL_DCACHE_UTCL0_UTCL1_INFLIGHT = 399
SQC_PERF_SEL_DCACHE_UTCL0_STALL_MISSFIFO_FULL = 400
SQC_PERF_SEL_DCACHE_UTCL0_STALL_MULTI_MISS = 401
SQC_PERF_SEL_DCACHE_UTCL0_HIT_FIFO_FULL = 402
SQC_PERF_SEL_ICACHE_UTCL0_INFLIGHT_LEVEL = 403
SQC_PERF_SEL_ICACHE_UTCL0_ALL_REQ = 404
SQC_PERF_SEL_ICACHE_UTCL1_INFLIGHT_LEVEL = 405
SQC_PERF_SEL_ICACHE_UTCL1_ALL_REQ = 406
SQC_PERF_SEL_DCACHE_UTCL0_INFLIGHT_LEVEL = 407
SQC_PERF_SEL_DCACHE_UTCL0_ALL_REQ = 408
SQC_PERF_SEL_DCACHE_UTCL1_INFLIGHT_LEVEL = 409
SQC_PERF_SEL_DCACHE_UTCL1_ALL_REQ = 410
SQC_PERF_SEL_ICACHE_GCR = 411
SQC_PERF_SEL_ICACHE_GCR_HITS = 412
SQC_PERF_SEL_DCACHE_GCR = 413
SQC_PERF_SEL_DCACHE_GCR_HITS = 414
SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 415
SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 416
SQC_PERF_SEL_DCACHE_GCR_WRITEBACK = 417
SQC_PERF_SEL_DUMMY_LAST = 418
SP_PERF_SEL_DUMMY_BEGIN = 448
SP_PERF_SEL_DUMMY_LAST = 511
SQ_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SQ_CAC_POWER_SEL'
SQ_CAC_POWER_SEL__enumvalues = {
0: 'SQ_CAC_POWER_VALU',
1: 'SQ_CAC_POWER_VALU0',
2: 'SQ_CAC_POWER_VALU1',
3: 'SQ_CAC_POWER_VALU2',
4: 'SQ_CAC_POWER_GPR_RD',
5: 'SQ_CAC_POWER_GPR_WR',
6: 'SQ_CAC_POWER_LDS_BUSY',
7: 'SQ_CAC_POWER_ALU_BUSY',
8: 'SQ_CAC_POWER_TEX_BUSY',
}
SQ_CAC_POWER_VALU = 0
SQ_CAC_POWER_VALU0 = 1
SQ_CAC_POWER_VALU1 = 2
SQ_CAC_POWER_VALU2 = 3
SQ_CAC_POWER_GPR_RD = 4
SQ_CAC_POWER_GPR_WR = 5
SQ_CAC_POWER_LDS_BUSY = 6
SQ_CAC_POWER_ALU_BUSY = 7
SQ_CAC_POWER_TEX_BUSY = 8
SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SQ_IND_CMD_CMD'
SQ_IND_CMD_CMD__enumvalues = {
0: 'SQ_IND_CMD_CMD_NULL',
1: 'SQ_IND_CMD_CMD_SETHALT',
2: 'SQ_IND_CMD_CMD_SAVECTX',
3: 'SQ_IND_CMD_CMD_KILL',
4: 'SQ_IND_CMD_CMD_DEBUG',
5: 'SQ_IND_CMD_CMD_TRAP',
6: 'SQ_IND_CMD_CMD_SET_SPI_PRIO',
7: 'SQ_IND_CMD_CMD_SETFATALHALT',
8: 'SQ_IND_CMD_CMD_SINGLE_STEP',
}
SQ_IND_CMD_CMD_NULL = 0
SQ_IND_CMD_CMD_SETHALT = 1
SQ_IND_CMD_CMD_SAVECTX = 2
SQ_IND_CMD_CMD_KILL = 3
SQ_IND_CMD_CMD_DEBUG = 4
SQ_IND_CMD_CMD_TRAP = 5
SQ_IND_CMD_CMD_SET_SPI_PRIO = 6
SQ_IND_CMD_CMD_SETFATALHALT = 7
SQ_IND_CMD_CMD_SINGLE_STEP = 8
SQ_IND_CMD_CMD = ctypes.c_uint32 # enum
# values for enumeration 'SQ_IND_CMD_MODE'
SQ_IND_CMD_MODE__enumvalues = {
0: 'SQ_IND_CMD_MODE_SINGLE',
1: 'SQ_IND_CMD_MODE_BROADCAST',
2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE',
3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE',
4: 'SQ_IND_CMD_MODE_BROADCAST_ME',
}
SQ_IND_CMD_MODE_SINGLE = 0
SQ_IND_CMD_MODE_BROADCAST = 1
SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2
SQ_IND_CMD_MODE_BROADCAST_PIPE = 3
SQ_IND_CMD_MODE_BROADCAST_ME = 4
SQ_IND_CMD_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_EDC_INFO_SOURCE'
SQ_EDC_INFO_SOURCE__enumvalues = {
0: 'SQ_EDC_INFO_SOURCE_INVALID',
1: 'SQ_EDC_INFO_SOURCE_INST',
2: 'SQ_EDC_INFO_SOURCE_SGPR',
3: 'SQ_EDC_INFO_SOURCE_VGPR',
4: 'SQ_EDC_INFO_SOURCE_LDS',
5: 'SQ_EDC_INFO_SOURCE_GDS',
6: 'SQ_EDC_INFO_SOURCE_TA',
}
SQ_EDC_INFO_SOURCE_INVALID = 0
SQ_EDC_INFO_SOURCE_INST = 1
SQ_EDC_INFO_SOURCE_SGPR = 2
SQ_EDC_INFO_SOURCE_VGPR = 3
SQ_EDC_INFO_SOURCE_LDS = 4
SQ_EDC_INFO_SOURCE_GDS = 5
SQ_EDC_INFO_SOURCE_TA = 6
SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_ROUND_MODE'
SQ_ROUND_MODE__enumvalues = {
0: 'SQ_ROUND_NEAREST_EVEN',
1: 'SQ_ROUND_PLUS_INFINITY',
2: 'SQ_ROUND_MINUS_INFINITY',
3: 'SQ_ROUND_TO_ZERO',
}
SQ_ROUND_NEAREST_EVEN = 0
SQ_ROUND_PLUS_INFINITY = 1
SQ_ROUND_MINUS_INFINITY = 2
SQ_ROUND_TO_ZERO = 3
SQ_ROUND_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_INTERRUPT_WORD_ENCODING'
SQ_INTERRUPT_WORD_ENCODING__enumvalues = {
0: 'SQ_INTERRUPT_WORD_ENCODING_AUTO',
1: 'SQ_INTERRUPT_WORD_ENCODING_INST',
2: 'SQ_INTERRUPT_WORD_ENCODING_ERROR',
}
SQ_INTERRUPT_WORD_ENCODING_AUTO = 0
SQ_INTERRUPT_WORD_ENCODING_INST = 1
SQ_INTERRUPT_WORD_ENCODING_ERROR = 2
SQ_INTERRUPT_WORD_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'SQ_IBUF_ST'
SQ_IBUF_ST__enumvalues = {
0: 'SQ_IBUF_IB_IDLE',
1: 'SQ_IBUF_IB_INI_WAIT_GNT',
2: 'SQ_IBUF_IB_INI_WAIT_DRET',
3: 'SQ_IBUF_IB_LE_4DW',
4: 'SQ_IBUF_IB_WAIT_DRET',
5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET',
6: 'SQ_IBUF_IB_DRET',
7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT',
}
SQ_IBUF_IB_IDLE = 0
SQ_IBUF_IB_INI_WAIT_GNT = 1
SQ_IBUF_IB_INI_WAIT_DRET = 2
SQ_IBUF_IB_LE_4DW = 3
SQ_IBUF_IB_WAIT_DRET = 4
SQ_IBUF_IB_EMPTY_WAIT_DRET = 5
SQ_IBUF_IB_DRET = 6
SQ_IBUF_IB_EMPTY_WAIT_GNT = 7
SQ_IBUF_ST = ctypes.c_uint32 # enum
# values for enumeration 'SQ_INST_STR_ST'
SQ_INST_STR_ST__enumvalues = {
0: 'SQ_INST_STR_IB_WAVE_NORML',
1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV',
2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV',
3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV',
4: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0',
5: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1',
6: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT',
7: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT',
}
SQ_INST_STR_IB_WAVE_NORML = 0
SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1
SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2
SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3
SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 4
SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 5
SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 6
SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 7
SQ_INST_STR_ST = ctypes.c_uint32 # enum
# values for enumeration 'SQ_WAVE_IB_ECC_ST'
SQ_WAVE_IB_ECC_ST__enumvalues = {
0: 'SQ_WAVE_IB_ECC_CLEAN',
1: 'SQ_WAVE_IB_ECC_ERR_CONTINUE',
2: 'SQ_WAVE_IB_ECC_ERR_HALT',
3: 'SQ_WAVE_IB_ECC_WITH_ERR_MSG',
}
SQ_WAVE_IB_ECC_CLEAN = 0
SQ_WAVE_IB_ECC_ERR_CONTINUE = 1
SQ_WAVE_IB_ECC_ERR_HALT = 2
SQ_WAVE_IB_ECC_WITH_ERR_MSG = 3
SQ_WAVE_IB_ECC_ST = ctypes.c_uint32 # enum
# values for enumeration 'SH_MEM_ADDRESS_MODE'
SH_MEM_ADDRESS_MODE__enumvalues = {
0: 'SH_MEM_ADDRESS_MODE_64',
1: 'SH_MEM_ADDRESS_MODE_32',
}
SH_MEM_ADDRESS_MODE_64 = 0
SH_MEM_ADDRESS_MODE_32 = 1
SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SH_MEM_RETRY_MODE'
SH_MEM_RETRY_MODE__enumvalues = {
0: 'SH_MEM_RETRY_MODE_ALL',
1: 'SH_MEM_RETRY_MODE_WRITEATOMIC',
2: 'SH_MEM_RETRY_MODE_NONE',
}
SH_MEM_RETRY_MODE_ALL = 0
SH_MEM_RETRY_MODE_WRITEATOMIC = 1
SH_MEM_RETRY_MODE_NONE = 2
SH_MEM_RETRY_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SH_MEM_ALIGNMENT_MODE'
SH_MEM_ALIGNMENT_MODE__enumvalues = {
0: 'SH_MEM_ALIGNMENT_MODE_DWORD',
1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT',
2: 'SH_MEM_ALIGNMENT_MODE_STRICT',
3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED',
}
SH_MEM_ALIGNMENT_MODE_DWORD = 0
SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1
SH_MEM_ALIGNMENT_MODE_STRICT = 2
SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3
SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT'
SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT__enumvalues = {
0: 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT',
1: 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT',
2: 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT',
3: 'SQ_TT_TOKEN_MASK_COMP_SHIFT',
4: 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT',
5: 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT',
6: 'SQ_TT_TOKEN_MASK_OTHER_SHIFT',
7: 'SQ_TT_TOKEN_MASK_READS_SHIFT',
}
SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0
SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 1
SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 2
SQ_TT_TOKEN_MASK_COMP_SHIFT = 3
SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 4
SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 5
SQ_TT_TOKEN_MASK_OTHER_SHIFT = 6
SQ_TT_TOKEN_MASK_READS_SHIFT = 7
SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE'
SQ_TT_TOKEN_MASK_REG_INCLUDE__enumvalues = {
1: 'SQ_TT_TOKEN_MASK_SQDEC_BIT',
2: 'SQ_TT_TOKEN_MASK_SHDEC_BIT',
4: 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT',
8: 'SQ_TT_TOKEN_MASK_COMP_BIT',
16: 'SQ_TT_TOKEN_MASK_CONTEXT_BIT',
32: 'SQ_TT_TOKEN_MASK_CONFIG_BIT',
64: 'SQ_TT_TOKEN_MASK_OTHER_BIT',
128: 'SQ_TT_TOKEN_MASK_READS_BIT',
}
SQ_TT_TOKEN_MASK_SQDEC_BIT = 1
SQ_TT_TOKEN_MASK_SHDEC_BIT = 2
SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 4
SQ_TT_TOKEN_MASK_COMP_BIT = 8
SQ_TT_TOKEN_MASK_CONTEXT_BIT = 16
SQ_TT_TOKEN_MASK_CONFIG_BIT = 32
SQ_TT_TOKEN_MASK_OTHER_BIT = 64
SQ_TT_TOKEN_MASK_READS_BIT = 128
SQ_TT_TOKEN_MASK_REG_INCLUDE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT'
SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT__enumvalues = {
0: 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT',
1: 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT',
2: 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT',
3: 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT',
4: 'SQ_TT_TOKEN_EXCLUDE_IMMED1_SHIFT',
5: 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT',
6: 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT',
7: 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT',
8: 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT',
9: 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT',
10: 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT',
11: 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT',
}
SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0
SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 1
SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 2
SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 3
SQ_TT_TOKEN_EXCLUDE_IMMED1_SHIFT = 4
SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 5
SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 6
SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 7
SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 8
SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 9
SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 10
SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 11
SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE'
SQ_TT_TOKEN_MASK_INST_EXCLUDE__enumvalues = {
0: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD',
1: 'SQ_TT_INST_EXCLUDE_EXPGNT234',
}
SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD = 0
SQ_TT_INST_EXCLUDE_EXPGNT234 = 1
SQ_TT_TOKEN_MASK_INST_EXCLUDE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_MODE'
SQ_TT_MODE__enumvalues = {
0: 'SQ_TT_MODE_OFF',
1: 'SQ_TT_MODE_ON',
2: 'SQ_TT_MODE_GLOBAL',
3: 'SQ_TT_MODE_DETAIL',
}
SQ_TT_MODE_OFF = 0
SQ_TT_MODE_ON = 1
SQ_TT_MODE_GLOBAL = 2
SQ_TT_MODE_DETAIL = 3
SQ_TT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_WTYPE_INCLUDE_SHIFT'
SQ_TT_WTYPE_INCLUDE_SHIFT__enumvalues = {
0: 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT',
1: 'SQ_TT_WTYPE_INCLUDE_VS_SHIFT',
2: 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT',
3: 'SQ_TT_WTYPE_INCLUDE_ES_SHIFT',
4: 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT',
5: 'SQ_TT_WTYPE_INCLUDE_LS_SHIFT',
6: 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT',
}
SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0
SQ_TT_WTYPE_INCLUDE_VS_SHIFT = 1
SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 2
SQ_TT_WTYPE_INCLUDE_ES_SHIFT = 3
SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 4
SQ_TT_WTYPE_INCLUDE_LS_SHIFT = 5
SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 6
SQ_TT_WTYPE_INCLUDE_SHIFT = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_WTYPE_INCLUDE'
SQ_TT_WTYPE_INCLUDE__enumvalues = {
1: 'SQ_TT_WTYPE_INCLUDE_PS_BIT',
2: 'SQ_TT_WTYPE_INCLUDE_VS_BIT',
4: 'SQ_TT_WTYPE_INCLUDE_GS_BIT',
8: 'SQ_TT_WTYPE_INCLUDE_ES_BIT',
16: 'SQ_TT_WTYPE_INCLUDE_HS_BIT',
32: 'SQ_TT_WTYPE_INCLUDE_LS_BIT',
64: 'SQ_TT_WTYPE_INCLUDE_CS_BIT',
}
SQ_TT_WTYPE_INCLUDE_PS_BIT = 1
SQ_TT_WTYPE_INCLUDE_VS_BIT = 2
SQ_TT_WTYPE_INCLUDE_GS_BIT = 4
SQ_TT_WTYPE_INCLUDE_ES_BIT = 8
SQ_TT_WTYPE_INCLUDE_HS_BIT = 16
SQ_TT_WTYPE_INCLUDE_LS_BIT = 32
SQ_TT_WTYPE_INCLUDE_CS_BIT = 64
SQ_TT_WTYPE_INCLUDE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_UTIL_TIMER'
SQ_TT_UTIL_TIMER__enumvalues = {
0: 'SQ_TT_UTIL_TIMER_100_CLK',
1: 'SQ_TT_UTIL_TIMER_250_CLK',
}
SQ_TT_UTIL_TIMER_100_CLK = 0
SQ_TT_UTIL_TIMER_250_CLK = 1
SQ_TT_UTIL_TIMER = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_WAVESTART_MODE'
SQ_TT_WAVESTART_MODE__enumvalues = {
0: 'SQ_TT_WAVESTART_MODE_SHORT',
1: 'SQ_TT_WAVESTART_MODE_ALLOC',
2: 'SQ_TT_WAVESTART_MODE_PBB_ID',
}
SQ_TT_WAVESTART_MODE_SHORT = 0
SQ_TT_WAVESTART_MODE_ALLOC = 1
SQ_TT_WAVESTART_MODE_PBB_ID = 2
SQ_TT_WAVESTART_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_RT_FREQ'
SQ_TT_RT_FREQ__enumvalues = {
0: 'SQ_TT_RT_FREQ_NEVER',
1: 'SQ_TT_RT_FREQ_1024_CLK',
2: 'SQ_TT_RT_FREQ_4096_CLK',
}
SQ_TT_RT_FREQ_NEVER = 0
SQ_TT_RT_FREQ_1024_CLK = 1
SQ_TT_RT_FREQ_4096_CLK = 2
SQ_TT_RT_FREQ = ctypes.c_uint32 # enum
# values for enumeration 'SQ_WATCH_MODES'
SQ_WATCH_MODES__enumvalues = {
0: 'SQ_WATCH_MODE_READ',
1: 'SQ_WATCH_MODE_NONREAD',
2: 'SQ_WATCH_MODE_ATOMIC',
3: 'SQ_WATCH_MODE_ALL',
}
SQ_WATCH_MODE_READ = 0
SQ_WATCH_MODE_NONREAD = 1
SQ_WATCH_MODE_ATOMIC = 2
SQ_WATCH_MODE_ALL = 3
SQ_WATCH_MODES = ctypes.c_uint32 # enum
# values for enumeration 'SQ_WAVE_SCHED_MODES'
SQ_WAVE_SCHED_MODES__enumvalues = {
0: 'SQ_WAVE_SCHED_MODE_NORMAL',
1: 'SQ_WAVE_SCHED_MODE_EXPERT',
2: 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST',
}
SQ_WAVE_SCHED_MODE_NORMAL = 0
SQ_WAVE_SCHED_MODE_EXPERT = 1
SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 2
SQ_WAVE_SCHED_MODES = ctypes.c_uint32 # enum
# values for enumeration 'CSDATA_TYPE'
CSDATA_TYPE__enumvalues = {
0: 'CSDATA_TYPE_TG',
1: 'CSDATA_TYPE_STATE',
2: 'CSDATA_TYPE_EVENT',
3: 'CSDATA_TYPE_PRIVATE',
}
CSDATA_TYPE_TG = 0
CSDATA_TYPE_STATE = 1
CSDATA_TYPE_EVENT = 2
CSDATA_TYPE_PRIVATE = 3
CSDATA_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'CSCNTL_TYPE'
CSCNTL_TYPE__enumvalues = {
0: 'CSCNTL_TYPE_TG',
1: 'CSCNTL_TYPE_STATE',
2: 'CSCNTL_TYPE_EVENT',
3: 'CSCNTL_TYPE_PRIVATE',
}
CSCNTL_TYPE_TG = 0
CSCNTL_TYPE_STATE = 1
CSCNTL_TYPE_EVENT = 2
CSCNTL_TYPE_PRIVATE = 3
CSCNTL_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_OUT_PRIM_TYPE'
VGT_OUT_PRIM_TYPE__enumvalues = {
0: 'VGT_OUT_POINT',
1: 'VGT_OUT_LINE',
2: 'VGT_OUT_TRI',
3: 'VGT_OUT_RECT_V0',
4: 'VGT_OUT_RECT_V1',
5: 'VGT_OUT_RECT_V2',
6: 'VGT_OUT_RECT_V3',
7: 'VGT_OUT_2D_RECT',
8: 'VGT_TE_QUAD',
9: 'VGT_TE_PRIM_INDEX_LINE',
10: 'VGT_TE_PRIM_INDEX_TRI',
11: 'VGT_TE_PRIM_INDEX_QUAD',
12: 'VGT_OUT_LINE_ADJ',
13: 'VGT_OUT_TRI_ADJ',
14: 'VGT_OUT_PATCH',
}
VGT_OUT_POINT = 0
VGT_OUT_LINE = 1
VGT_OUT_TRI = 2
VGT_OUT_RECT_V0 = 3
VGT_OUT_RECT_V1 = 4
VGT_OUT_RECT_V2 = 5
VGT_OUT_RECT_V3 = 6
VGT_OUT_2D_RECT = 7
VGT_TE_QUAD = 8
VGT_TE_PRIM_INDEX_LINE = 9
VGT_TE_PRIM_INDEX_TRI = 10
VGT_TE_PRIM_INDEX_QUAD = 11
VGT_OUT_LINE_ADJ = 12
VGT_OUT_TRI_ADJ = 13
VGT_OUT_PATCH = 14
VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DI_PRIM_TYPE'
VGT_DI_PRIM_TYPE__enumvalues = {
0: 'DI_PT_NONE',
1: 'DI_PT_POINTLIST',
2: 'DI_PT_LINELIST',
3: 'DI_PT_LINESTRIP',
4: 'DI_PT_TRILIST',
5: 'DI_PT_TRIFAN',
6: 'DI_PT_TRISTRIP',
7: 'DI_PT_2D_RECTANGLE',
8: 'DI_PT_UNUSED_1',
9: 'DI_PT_PATCH',
10: 'DI_PT_LINELIST_ADJ',
11: 'DI_PT_LINESTRIP_ADJ',
12: 'DI_PT_TRILIST_ADJ',
13: 'DI_PT_TRISTRIP_ADJ',
14: 'DI_PT_UNUSED_3',
15: 'DI_PT_UNUSED_4',
16: 'DI_PT_TRI_WITH_WFLAGS',
17: 'DI_PT_RECTLIST',
18: 'DI_PT_LINELOOP',
19: 'DI_PT_QUADLIST',
20: 'DI_PT_QUADSTRIP',
21: 'DI_PT_POLYGON',
}
DI_PT_NONE = 0
DI_PT_POINTLIST = 1
DI_PT_LINELIST = 2
DI_PT_LINESTRIP = 3
DI_PT_TRILIST = 4
DI_PT_TRIFAN = 5
DI_PT_TRISTRIP = 6
DI_PT_2D_RECTANGLE = 7
DI_PT_UNUSED_1 = 8
DI_PT_PATCH = 9
DI_PT_LINELIST_ADJ = 10
DI_PT_LINESTRIP_ADJ = 11
DI_PT_TRILIST_ADJ = 12
DI_PT_TRISTRIP_ADJ = 13
DI_PT_UNUSED_3 = 14
DI_PT_UNUSED_4 = 15
DI_PT_TRI_WITH_WFLAGS = 16
DI_PT_RECTLIST = 17
DI_PT_LINELOOP = 18
DI_PT_QUADLIST = 19
DI_PT_QUADSTRIP = 20
DI_PT_POLYGON = 21
VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DI_SOURCE_SELECT'
VGT_DI_SOURCE_SELECT__enumvalues = {
0: 'DI_SRC_SEL_DMA',
1: 'DI_SRC_SEL_IMMEDIATE',
2: 'DI_SRC_SEL_AUTO_INDEX',
3: 'DI_SRC_SEL_RESERVED',
}
DI_SRC_SEL_DMA = 0
DI_SRC_SEL_IMMEDIATE = 1
DI_SRC_SEL_AUTO_INDEX = 2
DI_SRC_SEL_RESERVED = 3
VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DI_MAJOR_MODE_SELECT'
VGT_DI_MAJOR_MODE_SELECT__enumvalues = {
0: 'DI_MAJOR_MODE_0',
1: 'DI_MAJOR_MODE_1',
}
DI_MAJOR_MODE_0 = 0
DI_MAJOR_MODE_1 = 1
VGT_DI_MAJOR_MODE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DI_INDEX_SIZE'
VGT_DI_INDEX_SIZE__enumvalues = {
0: 'DI_INDEX_SIZE_16_BIT',
1: 'DI_INDEX_SIZE_32_BIT',
2: 'DI_INDEX_SIZE_8_BIT',
}
DI_INDEX_SIZE_16_BIT = 0
DI_INDEX_SIZE_32_BIT = 1
DI_INDEX_SIZE_8_BIT = 2
VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_EVENT_TYPE'
VGT_EVENT_TYPE__enumvalues = {
0: 'Reserved_0x00',
1: 'SAMPLE_STREAMOUTSTATS1',
2: 'SAMPLE_STREAMOUTSTATS2',
3: 'SAMPLE_STREAMOUTSTATS3',
4: 'CACHE_FLUSH_TS',
5: 'CONTEXT_DONE',
6: 'CACHE_FLUSH',
7: 'CS_PARTIAL_FLUSH',
8: 'VGT_STREAMOUT_SYNC',
9: 'SET_FE_ID',
10: 'VGT_STREAMOUT_RESET',
11: 'END_OF_PIPE_INCR_DE',
12: 'END_OF_PIPE_IB_END',
13: 'RST_PIX_CNT',
14: 'BREAK_BATCH',
15: 'VS_PARTIAL_FLUSH',
16: 'PS_PARTIAL_FLUSH',
17: 'FLUSH_HS_OUTPUT',
18: 'FLUSH_DFSM',
19: 'RESET_TO_LOWEST_VGT',
20: 'CACHE_FLUSH_AND_INV_TS_EVENT',
21: 'ZPASS_DONE',
22: 'CACHE_FLUSH_AND_INV_EVENT',
23: 'PERFCOUNTER_START',
24: 'PERFCOUNTER_STOP',
25: 'PIPELINESTAT_START',
26: 'PIPELINESTAT_STOP',
27: 'PERFCOUNTER_SAMPLE',
28: 'FLUSH_ES_OUTPUT',
29: 'BIN_CONF_OVERRIDE_CHECK',
30: 'SAMPLE_PIPELINESTAT',
31: 'SO_VGTSTREAMOUT_FLUSH',
32: 'SAMPLE_STREAMOUTSTATS',
33: 'RESET_VTX_CNT',
34: 'BLOCK_CONTEXT_DONE',
35: 'CS_CONTEXT_DONE',
36: 'VGT_FLUSH',
37: 'TGID_ROLLOVER',
38: 'SQ_NON_EVENT',
39: 'SC_SEND_DB_VPZ',
40: 'BOTTOM_OF_PIPE_TS',
41: 'FLUSH_SX_TS',
42: 'DB_CACHE_FLUSH_AND_INV',
43: 'FLUSH_AND_INV_DB_DATA_TS',
44: 'FLUSH_AND_INV_DB_META',
45: 'FLUSH_AND_INV_CB_DATA_TS',
46: 'FLUSH_AND_INV_CB_META',
47: 'CS_DONE',
48: 'PS_DONE',
49: 'FLUSH_AND_INV_CB_PIXEL_DATA',
50: 'SX_CB_RAT_ACK_REQUEST',
51: 'THREAD_TRACE_START',
52: 'THREAD_TRACE_STOP',
53: 'THREAD_TRACE_MARKER',
54: 'THREAD_TRACE_DRAW',
55: 'THREAD_TRACE_FINISH',
56: 'PIXEL_PIPE_STAT_CONTROL',
57: 'PIXEL_PIPE_STAT_DUMP',
58: 'PIXEL_PIPE_STAT_RESET',
59: 'CONTEXT_SUSPEND',
60: 'OFFCHIP_HS_DEALLOC',
61: 'ENABLE_NGG_PIPELINE',
62: 'ENABLE_LEGACY_PIPELINE',
63: 'DRAW_DONE',
}
Reserved_0x00 = 0
SAMPLE_STREAMOUTSTATS1 = 1
SAMPLE_STREAMOUTSTATS2 = 2
SAMPLE_STREAMOUTSTATS3 = 3
CACHE_FLUSH_TS = 4
CONTEXT_DONE = 5
CACHE_FLUSH = 6
CS_PARTIAL_FLUSH = 7
VGT_STREAMOUT_SYNC = 8
SET_FE_ID = 9
VGT_STREAMOUT_RESET = 10
END_OF_PIPE_INCR_DE = 11
END_OF_PIPE_IB_END = 12
RST_PIX_CNT = 13
BREAK_BATCH = 14
VS_PARTIAL_FLUSH = 15
PS_PARTIAL_FLUSH = 16
FLUSH_HS_OUTPUT = 17
FLUSH_DFSM = 18
RESET_TO_LOWEST_VGT = 19
CACHE_FLUSH_AND_INV_TS_EVENT = 20
ZPASS_DONE = 21
CACHE_FLUSH_AND_INV_EVENT = 22
PERFCOUNTER_START = 23
PERFCOUNTER_STOP = 24
PIPELINESTAT_START = 25
PIPELINESTAT_STOP = 26
PERFCOUNTER_SAMPLE = 27
FLUSH_ES_OUTPUT = 28
BIN_CONF_OVERRIDE_CHECK = 29
SAMPLE_PIPELINESTAT = 30
SO_VGTSTREAMOUT_FLUSH = 31
SAMPLE_STREAMOUTSTATS = 32
RESET_VTX_CNT = 33
BLOCK_CONTEXT_DONE = 34
CS_CONTEXT_DONE = 35
VGT_FLUSH = 36
TGID_ROLLOVER = 37
SQ_NON_EVENT = 38
SC_SEND_DB_VPZ = 39
BOTTOM_OF_PIPE_TS = 40
FLUSH_SX_TS = 41
DB_CACHE_FLUSH_AND_INV = 42
FLUSH_AND_INV_DB_DATA_TS = 43
FLUSH_AND_INV_DB_META = 44
FLUSH_AND_INV_CB_DATA_TS = 45
FLUSH_AND_INV_CB_META = 46
CS_DONE = 47
PS_DONE = 48
FLUSH_AND_INV_CB_PIXEL_DATA = 49
SX_CB_RAT_ACK_REQUEST = 50
THREAD_TRACE_START = 51
THREAD_TRACE_STOP = 52
THREAD_TRACE_MARKER = 53
THREAD_TRACE_DRAW = 54
THREAD_TRACE_FINISH = 55
PIXEL_PIPE_STAT_CONTROL = 56
PIXEL_PIPE_STAT_DUMP = 57
PIXEL_PIPE_STAT_RESET = 58
CONTEXT_SUSPEND = 59
OFFCHIP_HS_DEALLOC = 60
ENABLE_NGG_PIPELINE = 61
ENABLE_LEGACY_PIPELINE = 62
DRAW_DONE = 63
VGT_EVENT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DMA_SWAP_MODE'
VGT_DMA_SWAP_MODE__enumvalues = {
0: 'VGT_DMA_SWAP_NONE',
1: 'VGT_DMA_SWAP_16_BIT',
2: 'VGT_DMA_SWAP_32_BIT',
3: 'VGT_DMA_SWAP_WORD',
}
VGT_DMA_SWAP_NONE = 0
VGT_DMA_SWAP_16_BIT = 1
VGT_DMA_SWAP_32_BIT = 2
VGT_DMA_SWAP_WORD = 3
VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_INDEX_TYPE_MODE'
VGT_INDEX_TYPE_MODE__enumvalues = {
0: 'VGT_INDEX_16',
1: 'VGT_INDEX_32',
2: 'VGT_INDEX_8',
}
VGT_INDEX_16 = 0
VGT_INDEX_32 = 1
VGT_INDEX_8 = 2
VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DMA_BUF_TYPE'
VGT_DMA_BUF_TYPE__enumvalues = {
0: 'VGT_DMA_BUF_MEM',
1: 'VGT_DMA_BUF_RING',
2: 'VGT_DMA_BUF_SETUP',
3: 'VGT_DMA_PTR_UPDATE',
}
VGT_DMA_BUF_MEM = 0
VGT_DMA_BUF_RING = 1
VGT_DMA_BUF_SETUP = 2
VGT_DMA_PTR_UPDATE = 3
VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_OUTPATH_SELECT'
VGT_OUTPATH_SELECT__enumvalues = {
0: 'VGT_OUTPATH_VTX_REUSE',
1: 'VGT_OUTPATH_GS_BLOCK',
2: 'VGT_OUTPATH_HS_BLOCK',
3: 'VGT_OUTPATH_PRIM_GEN',
4: 'VGT_OUTPATH_TE_PRIM_GEN',
5: 'VGT_OUTPATH_TE_GS_BLOCK',
6: 'VGT_OUTPATH_TE_OUTPUT',
}
VGT_OUTPATH_VTX_REUSE = 0
VGT_OUTPATH_GS_BLOCK = 1
VGT_OUTPATH_HS_BLOCK = 2
VGT_OUTPATH_PRIM_GEN = 3
VGT_OUTPATH_TE_PRIM_GEN = 4
VGT_OUTPATH_TE_GS_BLOCK = 5
VGT_OUTPATH_TE_OUTPUT = 6
VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'VGT_GRP_PRIM_TYPE'
VGT_GRP_PRIM_TYPE__enumvalues = {
0: 'VGT_GRP_3D_POINT',
1: 'VGT_GRP_3D_LINE',
2: 'VGT_GRP_3D_TRI',
3: 'VGT_GRP_3D_RECT',
4: 'VGT_GRP_3D_QUAD',
5: 'VGT_GRP_2D_COPY_RECT_V0',
6: 'VGT_GRP_2D_COPY_RECT_V1',
7: 'VGT_GRP_2D_COPY_RECT_V2',
8: 'VGT_GRP_2D_COPY_RECT_V3',
9: 'VGT_GRP_2D_FILL_RECT',
10: 'VGT_GRP_2D_LINE',
11: 'VGT_GRP_2D_TRI',
12: 'VGT_GRP_PRIM_INDEX_LINE',
13: 'VGT_GRP_PRIM_INDEX_TRI',
14: 'VGT_GRP_PRIM_INDEX_QUAD',
15: 'VGT_GRP_3D_LINE_ADJ',
16: 'VGT_GRP_3D_TRI_ADJ',
17: 'VGT_GRP_3D_PATCH',
18: 'VGT_GRP_2D_RECT',
}
VGT_GRP_3D_POINT = 0
VGT_GRP_3D_LINE = 1
VGT_GRP_3D_TRI = 2
VGT_GRP_3D_RECT = 3
VGT_GRP_3D_QUAD = 4
VGT_GRP_2D_COPY_RECT_V0 = 5
VGT_GRP_2D_COPY_RECT_V1 = 6
VGT_GRP_2D_COPY_RECT_V2 = 7
VGT_GRP_2D_COPY_RECT_V3 = 8
VGT_GRP_2D_FILL_RECT = 9
VGT_GRP_2D_LINE = 10
VGT_GRP_2D_TRI = 11
VGT_GRP_PRIM_INDEX_LINE = 12
VGT_GRP_PRIM_INDEX_TRI = 13
VGT_GRP_PRIM_INDEX_QUAD = 14
VGT_GRP_3D_LINE_ADJ = 15
VGT_GRP_3D_TRI_ADJ = 16
VGT_GRP_3D_PATCH = 17
VGT_GRP_2D_RECT = 18
VGT_GRP_PRIM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_GRP_PRIM_ORDER'
VGT_GRP_PRIM_ORDER__enumvalues = {
0: 'VGT_GRP_LIST',
1: 'VGT_GRP_STRIP',
2: 'VGT_GRP_FAN',
3: 'VGT_GRP_LOOP',
4: 'VGT_GRP_POLYGON',
}
VGT_GRP_LIST = 0
VGT_GRP_STRIP = 1
VGT_GRP_FAN = 2
VGT_GRP_LOOP = 3
VGT_GRP_POLYGON = 4
VGT_GRP_PRIM_ORDER = ctypes.c_uint32 # enum
# values for enumeration 'VGT_GROUP_CONV_SEL'
VGT_GROUP_CONV_SEL__enumvalues = {
0: 'VGT_GRP_INDEX_16',
1: 'VGT_GRP_INDEX_32',
2: 'VGT_GRP_UINT_16',
3: 'VGT_GRP_UINT_32',
4: 'VGT_GRP_SINT_16',
5: 'VGT_GRP_SINT_32',
6: 'VGT_GRP_FLOAT_32',
7: 'VGT_GRP_AUTO_PRIM',
8: 'VGT_GRP_FIX_1_23_TO_FLOAT',
}
VGT_GRP_INDEX_16 = 0
VGT_GRP_INDEX_32 = 1
VGT_GRP_UINT_16 = 2
VGT_GRP_UINT_32 = 3
VGT_GRP_SINT_16 = 4
VGT_GRP_SINT_32 = 5
VGT_GRP_FLOAT_32 = 6
VGT_GRP_AUTO_PRIM = 7
VGT_GRP_FIX_1_23_TO_FLOAT = 8
VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum
# values for enumeration 'VGT_GS_MODE_TYPE'
VGT_GS_MODE_TYPE__enumvalues = {
0: 'GS_OFF',
1: 'GS_SCENARIO_A',
2: 'GS_SCENARIO_B',
3: 'GS_SCENARIO_G',
4: 'GS_SCENARIO_C',
5: 'SPRITE_EN',
}
GS_OFF = 0
GS_SCENARIO_A = 1
GS_SCENARIO_B = 2
GS_SCENARIO_G = 3
GS_SCENARIO_C = 4
SPRITE_EN = 5
VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_GS_CUT_MODE'
VGT_GS_CUT_MODE__enumvalues = {
0: 'GS_CUT_1024',
1: 'GS_CUT_512',
2: 'GS_CUT_256',
3: 'GS_CUT_128',
}
GS_CUT_1024 = 0
GS_CUT_512 = 1
GS_CUT_256 = 2
GS_CUT_128 = 3
VGT_GS_CUT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_GS_OUTPRIM_TYPE'
VGT_GS_OUTPRIM_TYPE__enumvalues = {
0: 'POINTLIST',
1: 'LINESTRIP',
2: 'TRISTRIP',
3: 'RECTLIST',
}
POINTLIST = 0
LINESTRIP = 1
TRISTRIP = 2
RECTLIST = 3
VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_CACHE_INVALID_MODE'
VGT_CACHE_INVALID_MODE__enumvalues = {
0: 'VC_ONLY',
1: 'TC_ONLY',
2: 'VC_AND_TC',
}
VC_ONLY = 0
TC_ONLY = 1
VC_AND_TC = 2
VGT_CACHE_INVALID_MODE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_TESS_TYPE'
VGT_TESS_TYPE__enumvalues = {
0: 'TESS_ISOLINE',
1: 'TESS_TRIANGLE',
2: 'TESS_QUAD',
}
TESS_ISOLINE = 0
TESS_TRIANGLE = 1
TESS_QUAD = 2
VGT_TESS_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_TESS_PARTITION'
VGT_TESS_PARTITION__enumvalues = {
0: 'PART_INTEGER',
1: 'PART_POW2',
2: 'PART_FRAC_ODD',
3: 'PART_FRAC_EVEN',
}
PART_INTEGER = 0
PART_POW2 = 1
PART_FRAC_ODD = 2
PART_FRAC_EVEN = 3
VGT_TESS_PARTITION = ctypes.c_uint32 # enum
# values for enumeration 'VGT_TESS_TOPOLOGY'
VGT_TESS_TOPOLOGY__enumvalues = {
0: 'OUTPUT_POINT',
1: 'OUTPUT_LINE',
2: 'OUTPUT_TRIANGLE_CW',
3: 'OUTPUT_TRIANGLE_CCW',
}
OUTPUT_POINT = 0
OUTPUT_LINE = 1
OUTPUT_TRIANGLE_CW = 2
OUTPUT_TRIANGLE_CCW = 3
VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum
# values for enumeration 'VGT_RDREQ_POLICY'
VGT_RDREQ_POLICY__enumvalues = {
0: 'VGT_POLICY_LRU',
1: 'VGT_POLICY_STREAM',
2: 'VGT_POLICY_BYPASS',
}
VGT_POLICY_LRU = 0
VGT_POLICY_STREAM = 1
VGT_POLICY_BYPASS = 2
VGT_RDREQ_POLICY = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DIST_MODE'
VGT_DIST_MODE__enumvalues = {
0: 'NO_DIST',
1: 'PATCHES',
2: 'DONUTS',
3: 'TRAPEZOIDS',
}
NO_DIST = 0
PATCHES = 1
DONUTS = 2
TRAPEZOIDS = 3
VGT_DIST_MODE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DETECT_ONE'
VGT_DETECT_ONE__enumvalues = {
0: 'PRE_CLAMP_TF1',
1: 'POST_CLAMP_TF1',
2: 'DISABLE_TF1',
}
PRE_CLAMP_TF1 = 0
POST_CLAMP_TF1 = 1
DISABLE_TF1 = 2
VGT_DETECT_ONE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DETECT_ZERO'
VGT_DETECT_ZERO__enumvalues = {
0: 'PRE_CLAMP_TF0',
1: 'POST_CLAMP_TF0',
2: 'DISABLE_TF0',
}
PRE_CLAMP_TF0 = 0
POST_CLAMP_TF0 = 1
DISABLE_TF0 = 2
VGT_DETECT_ZERO = ctypes.c_uint32 # enum
# values for enumeration 'VGT_STAGES_LS_EN'
VGT_STAGES_LS_EN__enumvalues = {
0: 'LS_STAGE_OFF',
1: 'LS_STAGE_ON',
2: 'CS_STAGE_ON',
3: 'RESERVED_LS',
}
LS_STAGE_OFF = 0
LS_STAGE_ON = 1
CS_STAGE_ON = 2
RESERVED_LS = 3
VGT_STAGES_LS_EN = ctypes.c_uint32 # enum
# values for enumeration 'VGT_STAGES_HS_EN'
VGT_STAGES_HS_EN__enumvalues = {
0: 'HS_STAGE_OFF',
1: 'HS_STAGE_ON',
}
HS_STAGE_OFF = 0
HS_STAGE_ON = 1
VGT_STAGES_HS_EN = ctypes.c_uint32 # enum
# values for enumeration 'VGT_STAGES_ES_EN'
VGT_STAGES_ES_EN__enumvalues = {
0: 'ES_STAGE_OFF',
1: 'ES_STAGE_DS',
2: 'ES_STAGE_REAL',
3: 'RESERVED_ES',
}
ES_STAGE_OFF = 0
ES_STAGE_DS = 1
ES_STAGE_REAL = 2
RESERVED_ES = 3
VGT_STAGES_ES_EN = ctypes.c_uint32 # enum
# values for enumeration 'VGT_STAGES_GS_EN'
VGT_STAGES_GS_EN__enumvalues = {
0: 'GS_STAGE_OFF',
1: 'GS_STAGE_ON',
}
GS_STAGE_OFF = 0
GS_STAGE_ON = 1
VGT_STAGES_GS_EN = ctypes.c_uint32 # enum
# values for enumeration 'VGT_STAGES_VS_EN'
VGT_STAGES_VS_EN__enumvalues = {
0: 'VS_STAGE_REAL',
1: 'VS_STAGE_DS',
2: 'VS_STAGE_COPY_SHADER',
3: 'RESERVED_VS',
}
VS_STAGE_REAL = 0
VS_STAGE_DS = 1
VS_STAGE_COPY_SHADER = 2
RESERVED_VS = 3
VGT_STAGES_VS_EN = ctypes.c_uint32 # enum
# values for enumeration 'GE_PERFCOUNT_SELECT'
GE_PERFCOUNT_SELECT__enumvalues = {
0: 'ge_assembler_busy',
1: 'ge_assembler_stalled',
2: 'ge_cm_reading_stalled',
3: 'ge_cm_stalled_by_gog',
4: 'ge_cm_stalled_by_gsfetch_done',
5: 'ge_dma_busy',
6: 'ge_dma_lat_bin_0',
7: 'ge_dma_lat_bin_1',
8: 'ge_dma_lat_bin_2',
9: 'ge_dma_lat_bin_3',
10: 'ge_dma_lat_bin_4',
11: 'ge_dma_lat_bin_5',
12: 'ge_dma_lat_bin_6',
13: 'ge_dma_lat_bin_7',
14: 'ge_dma_return',
15: 'ge_dma_utcl1_consecutive_retry_event',
16: 'ge_dma_utcl1_request_event',
17: 'ge_dma_utcl1_retry_event',
18: 'ge_dma_utcl1_stall_event',
19: 'ge_dma_utcl1_stall_utcl2_event',
20: 'ge_dma_utcl1_translation_hit_event',
21: 'ge_dma_utcl1_translation_miss_event',
22: 'ge_dma_utcl2_stall_on_trans',
23: 'ge_dma_utcl2_trans_ack',
24: 'ge_dma_utcl2_trans_xnack',
25: 'ge_ds_cache_hits',
26: 'ge_ds_prims',
27: 'ge_es_done',
28: 'ge_es_done_latency',
29: 'ge_es_flush',
30: 'ge_es_ring_high_water_mark',
31: 'ge_es_thread_groups',
32: 'ge_esthread_stalled_es_rb_full',
33: 'ge_esthread_stalled_spi_bp',
34: 'ge_esvert_stalled_es_tbl',
35: 'ge_esvert_stalled_gs_event',
36: 'ge_esvert_stalled_gs_tbl',
37: 'ge_esvert_stalled_gsprim',
38: 'ge_gea_dma_starved',
39: 'ge_gog_busy',
40: 'ge_gog_out_indx_stalled',
41: 'ge_gog_out_prim_stalled',
42: 'ge_gog_vs_tbl_stalled',
43: 'ge_gs_cache_hits',
44: 'ge_gs_counters_avail_stalled',
45: 'ge_gs_done',
46: 'ge_gs_done_latency',
47: 'ge_gs_event_stall',
48: 'ge_gs_issue_rtr_stalled',
49: 'ge_gs_rb_space_avail_stalled',
50: 'ge_gs_ring_high_water_mark',
51: 'ge_gsprim_stalled_es_tbl',
52: 'ge_gsprim_stalled_esvert',
53: 'ge_gsprim_stalled_gs_event',
54: 'ge_gsprim_stalled_gs_tbl',
55: 'ge_gsthread_stalled',
56: 'ge_hs_done',
57: 'ge_hs_done_latency',
58: 'ge_hs_done_se0',
59: 'ge_hs_done_se1',
60: 'ge_hs_done_se2_reserved',
61: 'ge_hs_done_se3_reserved',
62: 'ge_hs_tfm_stall',
63: 'ge_hs_tgs_active_high_water_mark',
64: 'ge_hs_thread_groups',
65: 'ge_inside_tf_bin_0',
66: 'ge_inside_tf_bin_1',
67: 'ge_inside_tf_bin_2',
68: 'ge_inside_tf_bin_3',
69: 'ge_inside_tf_bin_4',
70: 'ge_inside_tf_bin_5',
71: 'ge_inside_tf_bin_6',
72: 'ge_inside_tf_bin_7',
73: 'ge_inside_tf_bin_8',
74: 'ge_ls_done',
75: 'ge_ls_done_latency',
76: 'ge_null_patch',
77: 'ge_pa_clipp_eop',
78: 'ge_pa_clipp_is_event',
79: 'ge_pa_clipp_new_vtx_vect',
80: 'ge_pa_clipp_null_prim',
81: 'ge_pa_clipp_send',
82: 'ge_pa_clipp_send_not_event',
83: 'ge_pa_clipp_stalled',
84: 'ge_pa_clipp_starved_busy',
85: 'ge_pa_clipp_starved_idle',
86: 'ge_pa_clipp_valid_prim',
87: 'ge_pa_clips_send',
88: 'ge_pa_clips_stalled',
89: 'ge_pa_clipv_send',
90: 'ge_pa_clipv_stalled',
91: 'ge_rbiu_di_fifo_stalled',
92: 'ge_rbiu_di_fifo_starved',
93: 'ge_rbiu_dr_fifo_stalled',
94: 'ge_rbiu_dr_fifo_starved',
95: 'ge_reused_es_indices',
96: 'ge_reused_vs_indices',
97: 'ge_sclk_core_vld',
98: 'ge_sclk_gs_vld',
99: 'ge_sclk_input_vld',
100: 'ge_sclk_leg_gs_arb_vld',
101: 'ge_sclk_ngg_vld',
102: 'ge_sclk_reg_vld',
103: 'ge_sclk_te11_vld',
104: 'ge_sclk_vr_vld',
105: 'ge_sclk_wd_te11_vld',
106: 'ge_spi_esvert_eov',
107: 'ge_spi_esvert_stalled',
108: 'ge_spi_esvert_starved_busy',
109: 'ge_spi_esvert_valid',
110: 'ge_spi_eswave_is_event',
111: 'ge_spi_eswave_send',
112: 'ge_spi_gsprim_cont',
113: 'ge_spi_gsprim_eov',
114: 'ge_spi_gsprim_stalled',
115: 'ge_spi_gsprim_starved_busy',
116: 'ge_spi_gsprim_starved_idle',
117: 'ge_spi_gsprim_valid',
118: 'ge_spi_gssubgrp_is_event',
119: 'ge_spi_gssubgrp_send',
120: 'ge_spi_gswave_is_event',
121: 'ge_spi_gswave_send',
122: 'ge_spi_hsvert_eov',
123: 'ge_spi_hsvert_stalled',
124: 'ge_spi_hsvert_starved_busy',
125: 'ge_spi_hsvert_valid',
126: 'ge_spi_hswave_is_event',
127: 'ge_spi_hswave_send',
128: 'ge_spi_lsvert_eov',
129: 'ge_spi_lsvert_stalled',
130: 'ge_spi_lsvert_starved_busy',
131: 'ge_spi_lsvert_starved_idle',
132: 'ge_spi_lsvert_valid',
133: 'ge_spi_lswave_is_event',
134: 'ge_spi_lswave_send',
135: 'ge_spi_vsvert_eov',
136: 'ge_spi_vsvert_send',
137: 'ge_spi_vsvert_stalled',
138: 'ge_spi_vsvert_starved_busy',
139: 'ge_spi_vsvert_starved_idle',
140: 'ge_spi_vswave_is_event',
141: 'ge_spi_vswave_send',
142: 'ge_starved_on_hs_done',
143: 'ge_stat_busy',
144: 'ge_stat_combined_busy',
145: 'ge_stat_no_dma_busy',
146: 'ge_strmout_stalled',
147: 'ge_te11_busy',
148: 'ge_te11_starved',
149: 'ge_tfreq_lat_bin_0',
150: 'ge_tfreq_lat_bin_1',
151: 'ge_tfreq_lat_bin_2',
152: 'ge_tfreq_lat_bin_3',
153: 'ge_tfreq_lat_bin_4',
154: 'ge_tfreq_lat_bin_5',
155: 'ge_tfreq_lat_bin_6',
156: 'ge_tfreq_lat_bin_7',
157: 'ge_tfreq_utcl1_consecutive_retry_event',
158: 'ge_tfreq_utcl1_request_event',
159: 'ge_tfreq_utcl1_retry_event',
160: 'ge_tfreq_utcl1_stall_event',
161: 'ge_tfreq_utcl1_stall_utcl2_event',
162: 'ge_tfreq_utcl1_translation_hit_event',
163: 'ge_tfreq_utcl1_translation_miss_event',
164: 'ge_tfreq_utcl2_stall_on_trans',
165: 'ge_tfreq_utcl2_trans_ack',
166: 'ge_tfreq_utcl2_trans_xnack',
167: 'ge_vs_cache_hits',
168: 'ge_vs_done',
169: 'ge_vs_pc_stall',
170: 'ge_vs_table_high_water_mark',
171: 'ge_vs_thread_groups',
172: 'ge_vsvert_api_send',
173: 'ge_vsvert_ds_send',
174: 'ge_wait_for_es_done_stalled',
175: 'ge_waveid_stalled',
}
ge_assembler_busy = 0
ge_assembler_stalled = 1
ge_cm_reading_stalled = 2
ge_cm_stalled_by_gog = 3
ge_cm_stalled_by_gsfetch_done = 4
ge_dma_busy = 5
ge_dma_lat_bin_0 = 6
ge_dma_lat_bin_1 = 7
ge_dma_lat_bin_2 = 8
ge_dma_lat_bin_3 = 9
ge_dma_lat_bin_4 = 10
ge_dma_lat_bin_5 = 11
ge_dma_lat_bin_6 = 12
ge_dma_lat_bin_7 = 13
ge_dma_return = 14
ge_dma_utcl1_consecutive_retry_event = 15
ge_dma_utcl1_request_event = 16
ge_dma_utcl1_retry_event = 17
ge_dma_utcl1_stall_event = 18
ge_dma_utcl1_stall_utcl2_event = 19
ge_dma_utcl1_translation_hit_event = 20
ge_dma_utcl1_translation_miss_event = 21
ge_dma_utcl2_stall_on_trans = 22
ge_dma_utcl2_trans_ack = 23
ge_dma_utcl2_trans_xnack = 24
ge_ds_cache_hits = 25
ge_ds_prims = 26
ge_es_done = 27
ge_es_done_latency = 28
ge_es_flush = 29
ge_es_ring_high_water_mark = 30
ge_es_thread_groups = 31
ge_esthread_stalled_es_rb_full = 32
ge_esthread_stalled_spi_bp = 33
ge_esvert_stalled_es_tbl = 34
ge_esvert_stalled_gs_event = 35
ge_esvert_stalled_gs_tbl = 36
ge_esvert_stalled_gsprim = 37
ge_gea_dma_starved = 38
ge_gog_busy = 39
ge_gog_out_indx_stalled = 40
ge_gog_out_prim_stalled = 41
ge_gog_vs_tbl_stalled = 42
ge_gs_cache_hits = 43
ge_gs_counters_avail_stalled = 44
ge_gs_done = 45
ge_gs_done_latency = 46
ge_gs_event_stall = 47
ge_gs_issue_rtr_stalled = 48
ge_gs_rb_space_avail_stalled = 49
ge_gs_ring_high_water_mark = 50
ge_gsprim_stalled_es_tbl = 51
ge_gsprim_stalled_esvert = 52
ge_gsprim_stalled_gs_event = 53
ge_gsprim_stalled_gs_tbl = 54
ge_gsthread_stalled = 55
ge_hs_done = 56
ge_hs_done_latency = 57
ge_hs_done_se0 = 58
ge_hs_done_se1 = 59
ge_hs_done_se2_reserved = 60
ge_hs_done_se3_reserved = 61
ge_hs_tfm_stall = 62
ge_hs_tgs_active_high_water_mark = 63
ge_hs_thread_groups = 64
ge_inside_tf_bin_0 = 65
ge_inside_tf_bin_1 = 66
ge_inside_tf_bin_2 = 67
ge_inside_tf_bin_3 = 68
ge_inside_tf_bin_4 = 69
ge_inside_tf_bin_5 = 70
ge_inside_tf_bin_6 = 71
ge_inside_tf_bin_7 = 72
ge_inside_tf_bin_8 = 73
ge_ls_done = 74
ge_ls_done_latency = 75
ge_null_patch = 76
ge_pa_clipp_eop = 77
ge_pa_clipp_is_event = 78
ge_pa_clipp_new_vtx_vect = 79
ge_pa_clipp_null_prim = 80
ge_pa_clipp_send = 81
ge_pa_clipp_send_not_event = 82
ge_pa_clipp_stalled = 83
ge_pa_clipp_starved_busy = 84
ge_pa_clipp_starved_idle = 85
ge_pa_clipp_valid_prim = 86
ge_pa_clips_send = 87
ge_pa_clips_stalled = 88
ge_pa_clipv_send = 89
ge_pa_clipv_stalled = 90
ge_rbiu_di_fifo_stalled = 91
ge_rbiu_di_fifo_starved = 92
ge_rbiu_dr_fifo_stalled = 93
ge_rbiu_dr_fifo_starved = 94
ge_reused_es_indices = 95
ge_reused_vs_indices = 96
ge_sclk_core_vld = 97
ge_sclk_gs_vld = 98
ge_sclk_input_vld = 99
ge_sclk_leg_gs_arb_vld = 100
ge_sclk_ngg_vld = 101
ge_sclk_reg_vld = 102
ge_sclk_te11_vld = 103
ge_sclk_vr_vld = 104
ge_sclk_wd_te11_vld = 105
ge_spi_esvert_eov = 106
ge_spi_esvert_stalled = 107
ge_spi_esvert_starved_busy = 108
ge_spi_esvert_valid = 109
ge_spi_eswave_is_event = 110
ge_spi_eswave_send = 111
ge_spi_gsprim_cont = 112
ge_spi_gsprim_eov = 113
ge_spi_gsprim_stalled = 114
ge_spi_gsprim_starved_busy = 115
ge_spi_gsprim_starved_idle = 116
ge_spi_gsprim_valid = 117
ge_spi_gssubgrp_is_event = 118
ge_spi_gssubgrp_send = 119
ge_spi_gswave_is_event = 120
ge_spi_gswave_send = 121
ge_spi_hsvert_eov = 122
ge_spi_hsvert_stalled = 123
ge_spi_hsvert_starved_busy = 124
ge_spi_hsvert_valid = 125
ge_spi_hswave_is_event = 126
ge_spi_hswave_send = 127
ge_spi_lsvert_eov = 128
ge_spi_lsvert_stalled = 129
ge_spi_lsvert_starved_busy = 130
ge_spi_lsvert_starved_idle = 131
ge_spi_lsvert_valid = 132
ge_spi_lswave_is_event = 133
ge_spi_lswave_send = 134
ge_spi_vsvert_eov = 135
ge_spi_vsvert_send = 136
ge_spi_vsvert_stalled = 137
ge_spi_vsvert_starved_busy = 138
ge_spi_vsvert_starved_idle = 139
ge_spi_vswave_is_event = 140
ge_spi_vswave_send = 141
ge_starved_on_hs_done = 142
ge_stat_busy = 143
ge_stat_combined_busy = 144
ge_stat_no_dma_busy = 145
ge_strmout_stalled = 146
ge_te11_busy = 147
ge_te11_starved = 148
ge_tfreq_lat_bin_0 = 149
ge_tfreq_lat_bin_1 = 150
ge_tfreq_lat_bin_2 = 151
ge_tfreq_lat_bin_3 = 152
ge_tfreq_lat_bin_4 = 153
ge_tfreq_lat_bin_5 = 154
ge_tfreq_lat_bin_6 = 155
ge_tfreq_lat_bin_7 = 156
ge_tfreq_utcl1_consecutive_retry_event = 157
ge_tfreq_utcl1_request_event = 158
ge_tfreq_utcl1_retry_event = 159
ge_tfreq_utcl1_stall_event = 160
ge_tfreq_utcl1_stall_utcl2_event = 161
ge_tfreq_utcl1_translation_hit_event = 162
ge_tfreq_utcl1_translation_miss_event = 163
ge_tfreq_utcl2_stall_on_trans = 164
ge_tfreq_utcl2_trans_ack = 165
ge_tfreq_utcl2_trans_xnack = 166
ge_vs_cache_hits = 167
ge_vs_done = 168
ge_vs_pc_stall = 169
ge_vs_table_high_water_mark = 170
ge_vs_thread_groups = 171
ge_vsvert_api_send = 172
ge_vsvert_ds_send = 173
ge_wait_for_es_done_stalled = 174
ge_waveid_stalled = 175
GE_PERFCOUNT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'WD_IA_DRAW_TYPE'
WD_IA_DRAW_TYPE__enumvalues = {
0: 'WD_IA_DRAW_TYPE_DI_MM0',
1: 'WD_IA_DRAW_TYPE_REG_XFER',
2: 'WD_IA_DRAW_TYPE_EVENT_INIT',
3: 'WD_IA_DRAW_TYPE_EVENT_ADDR',
4: 'WD_IA_DRAW_TYPE_MIN_INDX',
5: 'WD_IA_DRAW_TYPE_MAX_INDX',
6: 'WD_IA_DRAW_TYPE_INDX_OFF',
7: 'WD_IA_DRAW_TYPE_IMM_DATA',
}
WD_IA_DRAW_TYPE_DI_MM0 = 0
WD_IA_DRAW_TYPE_REG_XFER = 1
WD_IA_DRAW_TYPE_EVENT_INIT = 2
WD_IA_DRAW_TYPE_EVENT_ADDR = 3
WD_IA_DRAW_TYPE_MIN_INDX = 4
WD_IA_DRAW_TYPE_MAX_INDX = 5
WD_IA_DRAW_TYPE_INDX_OFF = 6
WD_IA_DRAW_TYPE_IMM_DATA = 7
WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'WD_IA_DRAW_REG_XFER'
WD_IA_DRAW_REG_XFER__enumvalues = {
0: 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM',
1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN',
2: 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID',
3: 'WD_IA_DRAW_REG_XFER_GE_CNTL',
}
WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0
WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1
WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 2
WD_IA_DRAW_REG_XFER_GE_CNTL = 3
WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum
# values for enumeration 'WD_IA_DRAW_SOURCE'
WD_IA_DRAW_SOURCE__enumvalues = {
0: 'WD_IA_DRAW_SOURCE_DMA',
1: 'WD_IA_DRAW_SOURCE_IMMD',
2: 'WD_IA_DRAW_SOURCE_AUTO',
3: 'WD_IA_DRAW_SOURCE_OPAQ',
}
WD_IA_DRAW_SOURCE_DMA = 0
WD_IA_DRAW_SOURCE_IMMD = 1
WD_IA_DRAW_SOURCE_AUTO = 2
WD_IA_DRAW_SOURCE_OPAQ = 3
WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'GB_EDC_DED_MODE'
GB_EDC_DED_MODE__enumvalues = {
0: 'GB_EDC_DED_MODE_LOG',
1: 'GB_EDC_DED_MODE_HALT',
2: 'GB_EDC_DED_MODE_INT_HALT',
}
GB_EDC_DED_MODE_LOG = 0
GB_EDC_DED_MODE_HALT = 1
GB_EDC_DED_MODE_INT_HALT = 2
GB_EDC_DED_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CHA_PERF_SEL'
CHA_PERF_SEL__enumvalues = {
0: 'CHA_PERF_SEL_BUSY',
1: 'CHA_PERF_SEL_STALL_CHC0',
2: 'CHA_PERF_SEL_STALL_CHC1',
3: 'CHA_PERF_SEL_STALL_CHC2',
4: 'CHA_PERF_SEL_STALL_CHC3',
5: 'CHA_PERF_SEL_STALL_CHC4',
6: 'CHA_PERF_SEL_REQUEST_CHC0',
7: 'CHA_PERF_SEL_REQUEST_CHC1',
8: 'CHA_PERF_SEL_REQUEST_CHC2',
9: 'CHA_PERF_SEL_REQUEST_CHC3',
10: 'CHA_PERF_SEL_REQUEST_CHC4',
11: 'CHA_PERF_SEL_REQUEST_CHC5',
12: 'CHA_PERF_SEL_MEM_32B_WDS_CHC0',
13: 'CHA_PERF_SEL_MEM_32B_WDS_CHC1',
14: 'CHA_PERF_SEL_MEM_32B_WDS_CHC2',
15: 'CHA_PERF_SEL_MEM_32B_WDS_CHC3',
16: 'CHA_PERF_SEL_MEM_32B_WDS_CHC4',
17: 'CHA_PERF_SEL_IO_32B_WDS_CHC0',
18: 'CHA_PERF_SEL_IO_32B_WDS_CHC1',
19: 'CHA_PERF_SEL_IO_32B_WDS_CHC2',
20: 'CHA_PERF_SEL_IO_32B_WDS_CHC3',
21: 'CHA_PERF_SEL_IO_32B_WDS_CHC4',
22: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0',
23: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1',
24: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2',
25: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3',
26: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4',
27: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0',
28: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1',
29: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2',
30: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3',
31: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4',
32: 'CHA_PERF_SEL_ARB_REQUESTS',
33: 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL',
34: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0',
35: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1',
36: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2',
37: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3',
38: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4',
39: 'CHA_PERF_SEL_CYCLE',
}
CHA_PERF_SEL_BUSY = 0
CHA_PERF_SEL_STALL_CHC0 = 1
CHA_PERF_SEL_STALL_CHC1 = 2
CHA_PERF_SEL_STALL_CHC2 = 3
CHA_PERF_SEL_STALL_CHC3 = 4
CHA_PERF_SEL_STALL_CHC4 = 5
CHA_PERF_SEL_REQUEST_CHC0 = 6
CHA_PERF_SEL_REQUEST_CHC1 = 7
CHA_PERF_SEL_REQUEST_CHC2 = 8
CHA_PERF_SEL_REQUEST_CHC3 = 9
CHA_PERF_SEL_REQUEST_CHC4 = 10
CHA_PERF_SEL_REQUEST_CHC5 = 11
CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 12
CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 13
CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 14
CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 15
CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 16
CHA_PERF_SEL_IO_32B_WDS_CHC0 = 17
CHA_PERF_SEL_IO_32B_WDS_CHC1 = 18
CHA_PERF_SEL_IO_32B_WDS_CHC2 = 19
CHA_PERF_SEL_IO_32B_WDS_CHC3 = 20
CHA_PERF_SEL_IO_32B_WDS_CHC4 = 21
CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 22
CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 23
CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 24
CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 25
CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 26
CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 27
CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 28
CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 29
CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 30
CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 31
CHA_PERF_SEL_ARB_REQUESTS = 32
CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 33
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 34
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 35
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 36
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 37
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 38
CHA_PERF_SEL_CYCLE = 39
CHA_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CHC_PERF_SEL'
CHC_PERF_SEL__enumvalues = {
0: 'CHC_PERF_SEL_GATE_EN1',
1: 'CHC_PERF_SEL_GATE_EN2',
2: 'CHC_PERF_SEL_CORE_REG_SCLK_VLD',
3: 'CHC_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES',
4: 'CHC_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES',
5: 'CHC_PERF_SEL_CYCLE',
6: 'CHC_PERF_SEL_REQ',
}
CHC_PERF_SEL_GATE_EN1 = 0
CHC_PERF_SEL_GATE_EN2 = 1
CHC_PERF_SEL_CORE_REG_SCLK_VLD = 2
CHC_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES = 3
CHC_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES = 4
CHC_PERF_SEL_CYCLE = 5
CHC_PERF_SEL_REQ = 6
CHC_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CHCG_PERF_SEL'
CHCG_PERF_SEL__enumvalues = {
0: 'CHCG_PERF_SEL_GATE_EN1',
1: 'CHCG_PERF_SEL_GATE_EN2',
2: 'CHCG_PERF_SEL_CORE_REG_SCLK_VLD',
3: 'CHCG_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES',
4: 'CHCG_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES',
5: 'CHCG_PERF_SEL_CYCLE',
6: 'CHCG_PERF_SEL_REQ',
}
CHCG_PERF_SEL_GATE_EN1 = 0
CHCG_PERF_SEL_GATE_EN2 = 1
CHCG_PERF_SEL_CORE_REG_SCLK_VLD = 2
CHCG_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES = 3
CHCG_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES = 4
CHCG_PERF_SEL_CYCLE = 5
CHCG_PERF_SEL_REQ = 6
CHCG_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL1A_PERF_SEL'
GL1A_PERF_SEL__enumvalues = {
0: 'GL1A_PERF_SEL_BUSY',
1: 'GL1A_PERF_SEL_STALL_GL1C0',
2: 'GL1A_PERF_SEL_STALL_GL1C1',
3: 'GL1A_PERF_SEL_STALL_GL1C2',
4: 'GL1A_PERF_SEL_STALL_GL1C3',
5: 'GL1A_PERF_SEL_STALL_GL1C4',
6: 'GL1A_PERF_SEL_REQUEST_GL1C0',
7: 'GL1A_PERF_SEL_REQUEST_GL1C1',
8: 'GL1A_PERF_SEL_REQUEST_GL1C2',
9: 'GL1A_PERF_SEL_REQUEST_GL1C3',
10: 'GL1A_PERF_SEL_REQUEST_GL1C4',
11: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C0',
12: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C1',
13: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C2',
14: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C3',
15: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C4',
16: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C0',
17: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C1',
18: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C2',
19: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C3',
20: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C4',
21: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0',
22: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1',
23: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2',
24: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3',
25: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4',
26: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0',
27: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1',
28: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2',
29: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3',
30: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4',
31: 'GL1A_PERF_SEL_ARB_REQUESTS',
32: 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL',
33: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0',
34: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1',
35: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2',
36: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3',
37: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4',
38: 'GL1A_PERF_SEL_CYCLE',
}
GL1A_PERF_SEL_BUSY = 0
GL1A_PERF_SEL_STALL_GL1C0 = 1
GL1A_PERF_SEL_STALL_GL1C1 = 2
GL1A_PERF_SEL_STALL_GL1C2 = 3
GL1A_PERF_SEL_STALL_GL1C3 = 4
GL1A_PERF_SEL_STALL_GL1C4 = 5
GL1A_PERF_SEL_REQUEST_GL1C0 = 6
GL1A_PERF_SEL_REQUEST_GL1C1 = 7
GL1A_PERF_SEL_REQUEST_GL1C2 = 8
GL1A_PERF_SEL_REQUEST_GL1C3 = 9
GL1A_PERF_SEL_REQUEST_GL1C4 = 10
GL1A_PERF_SEL_MEM_32B_WDS_GL1C0 = 11
GL1A_PERF_SEL_MEM_32B_WDS_GL1C1 = 12
GL1A_PERF_SEL_MEM_32B_WDS_GL1C2 = 13
GL1A_PERF_SEL_MEM_32B_WDS_GL1C3 = 14
GL1A_PERF_SEL_MEM_32B_WDS_GL1C4 = 15
GL1A_PERF_SEL_IO_32B_WDS_GL1C0 = 16
GL1A_PERF_SEL_IO_32B_WDS_GL1C1 = 17
GL1A_PERF_SEL_IO_32B_WDS_GL1C2 = 18
GL1A_PERF_SEL_IO_32B_WDS_GL1C3 = 19
GL1A_PERF_SEL_IO_32B_WDS_GL1C4 = 20
GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0 = 21
GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1 = 22
GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2 = 23
GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3 = 24
GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4 = 25
GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0 = 26
GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1 = 27
GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2 = 28
GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3 = 29
GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4 = 30
GL1A_PERF_SEL_ARB_REQUESTS = 31
GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 32
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 33
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 34
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 35
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 36
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4 = 37
GL1A_PERF_SEL_CYCLE = 38
GL1A_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL1C_PERF_SEL'
GL1C_PERF_SEL__enumvalues = {
0: 'GL1C_PERF_SEL_GATE_EN1',
1: 'GL1C_PERF_SEL_GATE_EN2',
2: 'GL1C_PERF_SEL_CORE_REG_SCLK_VLD',
3: 'GL1C_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES',
4: 'GL1C_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES',
5: 'GL1C_PERF_SEL_CYCLE',
6: 'GL1C_PERF_SEL_REQ',
}
GL1C_PERF_SEL_GATE_EN1 = 0
GL1C_PERF_SEL_GATE_EN2 = 1
GL1C_PERF_SEL_CORE_REG_SCLK_VLD = 2
GL1C_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES = 3
GL1C_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES = 4
GL1C_PERF_SEL_CYCLE = 5
GL1C_PERF_SEL_REQ = 6
GL1C_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL1CG_PERF_SEL'
GL1CG_PERF_SEL__enumvalues = {
0: 'GL1CG_PERF_SEL_GATE_EN1',
1: 'GL1CG_PERF_SEL_GATE_EN2',
2: 'GL1CG_PERF_SEL_CORE_REG_SCLK_VLD',
3: 'GL1CG_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES',
4: 'GL1CG_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES',
5: 'GL1CG_PERF_SEL_CYCLE',
6: 'GL1CG_PERF_SEL_REQ',
}
GL1CG_PERF_SEL_GATE_EN1 = 0
GL1CG_PERF_SEL_GATE_EN2 = 1
GL1CG_PERF_SEL_CORE_REG_SCLK_VLD = 2
GL1CG_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES = 3
GL1CG_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES = 4
GL1CG_PERF_SEL_CYCLE = 5
GL1CG_PERF_SEL_REQ = 6
GL1CG_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TA_TC_REQ_MODES'
TA_TC_REQ_MODES__enumvalues = {
0: 'TA_TC_REQ_MODE_BORDER',
1: 'TA_TC_REQ_MODE_TEX2',
2: 'TA_TC_REQ_MODE_TEX1',
3: 'TA_TC_REQ_MODE_TEX0',
4: 'TA_TC_REQ_MODE_NORMAL',
5: 'TA_TC_REQ_MODE_DWORD',
6: 'TA_TC_REQ_MODE_BYTE',
7: 'TA_TC_REQ_MODE_BYTE_NV',
}
TA_TC_REQ_MODE_BORDER = 0
TA_TC_REQ_MODE_TEX2 = 1
TA_TC_REQ_MODE_TEX1 = 2
TA_TC_REQ_MODE_TEX0 = 3
TA_TC_REQ_MODE_NORMAL = 4
TA_TC_REQ_MODE_DWORD = 5
TA_TC_REQ_MODE_BYTE = 6
TA_TC_REQ_MODE_BYTE_NV = 7
TA_TC_REQ_MODES = ctypes.c_uint32 # enum
# values for enumeration 'TA_TC_ADDR_MODES'
TA_TC_ADDR_MODES__enumvalues = {
0: 'TA_TC_ADDR_MODE_DEFAULT',
1: 'TA_TC_ADDR_MODE_COMP0',
2: 'TA_TC_ADDR_MODE_COMP1',
3: 'TA_TC_ADDR_MODE_COMP2',
4: 'TA_TC_ADDR_MODE_COMP3',
5: 'TA_TC_ADDR_MODE_UNALIGNED',
6: 'TA_TC_ADDR_MODE_BORDER_COLOR',
}
TA_TC_ADDR_MODE_DEFAULT = 0
TA_TC_ADDR_MODE_COMP0 = 1
TA_TC_ADDR_MODE_COMP1 = 2
TA_TC_ADDR_MODE_COMP2 = 3
TA_TC_ADDR_MODE_COMP3 = 4
TA_TC_ADDR_MODE_UNALIGNED = 5
TA_TC_ADDR_MODE_BORDER_COLOR = 6
TA_TC_ADDR_MODES = ctypes.c_uint32 # enum
# values for enumeration 'TA_PERFCOUNT_SEL'
TA_PERFCOUNT_SEL__enumvalues = {
0: 'TA_PERF_SEL_NULL',
1: 'TA_PERF_SEL_sh_fifo_busy',
2: 'TA_PERF_SEL_sh_fifo_cmd_busy',
3: 'TA_PERF_SEL_sh_fifo_addr_busy',
4: 'TA_PERF_SEL_sh_fifo_data_busy',
5: 'TA_PERF_SEL_sh_fifo_data_sfifo_busy',
6: 'TA_PERF_SEL_sh_fifo_data_tfifo_busy',
7: 'TA_PERF_SEL_gradient_busy',
8: 'TA_PERF_SEL_gradient_fifo_busy',
9: 'TA_PERF_SEL_lod_busy',
10: 'TA_PERF_SEL_lod_fifo_busy',
11: 'TA_PERF_SEL_addresser_busy',
12: 'TA_PERF_SEL_addresser_fifo_busy',
13: 'TA_PERF_SEL_aligner_busy',
14: 'TA_PERF_SEL_write_path_busy',
15: 'TA_PERF_SEL_ta_busy',
16: 'TA_PERF_SEL_sq_ta_cmd_cycles',
17: 'TA_PERF_SEL_sp_ta_addr_cycles',
18: 'TA_PERF_SEL_sp_ta_data_cycles',
19: 'TA_PERF_SEL_ta_fa_data_state_cycles',
20: 'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles',
21: 'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles',
22: 'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles',
23: 'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles',
24: 'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles',
25: 'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles',
26: 'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles',
27: 'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles',
28: 'TA_PERF_SEL_ta_sh_fifo_starved',
29: 'TA_PERF_SEL_RESERVED_29',
30: 'TA_PERF_SEL_sh_fifo_addr_cycles',
31: 'TA_PERF_SEL_sh_fifo_data_cycles',
32: 'TA_PERF_SEL_total_wavefronts',
33: 'TA_PERF_SEL_gradient_cycles',
34: 'TA_PERF_SEL_walker_cycles',
35: 'TA_PERF_SEL_aligner_cycles',
36: 'TA_PERF_SEL_image_wavefronts',
37: 'TA_PERF_SEL_image_read_wavefronts',
38: 'TA_PERF_SEL_image_write_wavefronts',
39: 'TA_PERF_SEL_image_atomic_wavefronts',
40: 'TA_PERF_SEL_image_total_cycles',
41: 'TA_PERF_SEL_RESERVED_41',
42: 'TA_PERF_SEL_RESERVED_42',
43: 'TA_PERF_SEL_RESERVED_43',
44: 'TA_PERF_SEL_buffer_wavefronts',
45: 'TA_PERF_SEL_buffer_read_wavefronts',
46: 'TA_PERF_SEL_buffer_write_wavefronts',
47: 'TA_PERF_SEL_buffer_atomic_wavefronts',
48: 'TA_PERF_SEL_buffer_coalescable_wavefronts',
49: 'TA_PERF_SEL_buffer_total_cycles',
50: 'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles',
51: 'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles',
52: 'TA_PERF_SEL_buffer_coalesced_read_cycles',
53: 'TA_PERF_SEL_buffer_coalesced_write_cycles',
54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles',
55: 'TA_PERF_SEL_addr_stalled_by_td_cycles',
56: 'TA_PERF_SEL_data_stalled_by_tc_cycles',
57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles',
58: 'TA_PERF_SEL_addresser_stalled_cycles',
59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles',
60: 'TA_PERF_SEL_aniso_stalled_cycles',
61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles',
62: 'TA_PERF_SEL_deriv_stalled_cycles',
63: 'TA_PERF_SEL_aniso_gt1_cycle_quads',
64: 'TA_PERF_SEL_color_1_cycle_pixels',
65: 'TA_PERF_SEL_color_2_cycle_pixels',
66: 'TA_PERF_SEL_color_3_cycle_pixels',
67: 'TA_PERF_SEL_color_4_cycle_pixels',
68: 'TA_PERF_SEL_mip_1_cycle_pixels',
69: 'TA_PERF_SEL_mip_2_cycle_pixels',
70: 'TA_PERF_SEL_vol_1_cycle_pixels',
71: 'TA_PERF_SEL_vol_2_cycle_pixels',
72: 'TA_PERF_SEL_bilin_point_1_cycle_pixels',
73: 'TA_PERF_SEL_mipmap_lod_0_samples',
74: 'TA_PERF_SEL_mipmap_lod_1_samples',
75: 'TA_PERF_SEL_mipmap_lod_2_samples',
76: 'TA_PERF_SEL_mipmap_lod_3_samples',
77: 'TA_PERF_SEL_mipmap_lod_4_samples',
78: 'TA_PERF_SEL_mipmap_lod_5_samples',
79: 'TA_PERF_SEL_mipmap_lod_6_samples',
80: 'TA_PERF_SEL_mipmap_lod_7_samples',
81: 'TA_PERF_SEL_mipmap_lod_8_samples',
82: 'TA_PERF_SEL_mipmap_lod_9_samples',
83: 'TA_PERF_SEL_mipmap_lod_10_samples',
84: 'TA_PERF_SEL_mipmap_lod_11_samples',
85: 'TA_PERF_SEL_mipmap_lod_12_samples',
86: 'TA_PERF_SEL_mipmap_lod_13_samples',
87: 'TA_PERF_SEL_mipmap_lod_14_samples',
88: 'TA_PERF_SEL_mipmap_invalid_samples',
89: 'TA_PERF_SEL_aniso_1_cycle_quads',
90: 'TA_PERF_SEL_aniso_2_cycle_quads',
91: 'TA_PERF_SEL_aniso_4_cycle_quads',
92: 'TA_PERF_SEL_aniso_6_cycle_quads',
93: 'TA_PERF_SEL_aniso_8_cycle_quads',
94: 'TA_PERF_SEL_aniso_10_cycle_quads',
95: 'TA_PERF_SEL_aniso_12_cycle_quads',
96: 'TA_PERF_SEL_aniso_14_cycle_quads',
97: 'TA_PERF_SEL_aniso_16_cycle_quads',
98: 'TA_PERF_SEL_write_path_input_cycles',
99: 'TA_PERF_SEL_write_path_output_cycles',
100: 'TA_PERF_SEL_flat_wavefronts',
101: 'TA_PERF_SEL_flat_read_wavefronts',
102: 'TA_PERF_SEL_flat_write_wavefronts',
103: 'TA_PERF_SEL_flat_atomic_wavefronts',
104: 'TA_PERF_SEL_flat_coalesceable_wavefronts',
105: 'TA_PERF_SEL_reg_sclk_vld',
106: 'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en',
107: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en',
108: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en',
109: 'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en',
110: 'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en',
111: 'TA_PERF_SEL_xnack_on_phase0',
112: 'TA_PERF_SEL_xnack_on_phase1',
113: 'TA_PERF_SEL_xnack_on_phase2',
114: 'TA_PERF_SEL_xnack_on_phase3',
115: 'TA_PERF_SEL_first_xnack_on_phase0',
116: 'TA_PERF_SEL_first_xnack_on_phase1',
117: 'TA_PERF_SEL_first_xnack_on_phase2',
118: 'TA_PERF_SEL_first_xnack_on_phase3',
}
TA_PERF_SEL_NULL = 0
TA_PERF_SEL_sh_fifo_busy = 1
TA_PERF_SEL_sh_fifo_cmd_busy = 2
TA_PERF_SEL_sh_fifo_addr_busy = 3
TA_PERF_SEL_sh_fifo_data_busy = 4
TA_PERF_SEL_sh_fifo_data_sfifo_busy = 5
TA_PERF_SEL_sh_fifo_data_tfifo_busy = 6
TA_PERF_SEL_gradient_busy = 7
TA_PERF_SEL_gradient_fifo_busy = 8
TA_PERF_SEL_lod_busy = 9
TA_PERF_SEL_lod_fifo_busy = 10
TA_PERF_SEL_addresser_busy = 11
TA_PERF_SEL_addresser_fifo_busy = 12
TA_PERF_SEL_aligner_busy = 13
TA_PERF_SEL_write_path_busy = 14
TA_PERF_SEL_ta_busy = 15
TA_PERF_SEL_sq_ta_cmd_cycles = 16
TA_PERF_SEL_sp_ta_addr_cycles = 17
TA_PERF_SEL_sp_ta_data_cycles = 18
TA_PERF_SEL_ta_fa_data_state_cycles = 19
TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 20
TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 21
TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 22
TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 23
TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 24
TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 25
TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 26
TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 27
TA_PERF_SEL_ta_sh_fifo_starved = 28
TA_PERF_SEL_RESERVED_29 = 29
TA_PERF_SEL_sh_fifo_addr_cycles = 30
TA_PERF_SEL_sh_fifo_data_cycles = 31
TA_PERF_SEL_total_wavefronts = 32
TA_PERF_SEL_gradient_cycles = 33
TA_PERF_SEL_walker_cycles = 34
TA_PERF_SEL_aligner_cycles = 35
TA_PERF_SEL_image_wavefronts = 36
TA_PERF_SEL_image_read_wavefronts = 37
TA_PERF_SEL_image_write_wavefronts = 38
TA_PERF_SEL_image_atomic_wavefronts = 39
TA_PERF_SEL_image_total_cycles = 40
TA_PERF_SEL_RESERVED_41 = 41
TA_PERF_SEL_RESERVED_42 = 42
TA_PERF_SEL_RESERVED_43 = 43
TA_PERF_SEL_buffer_wavefronts = 44
TA_PERF_SEL_buffer_read_wavefronts = 45
TA_PERF_SEL_buffer_write_wavefronts = 46
TA_PERF_SEL_buffer_atomic_wavefronts = 47
TA_PERF_SEL_buffer_coalescable_wavefronts = 48
TA_PERF_SEL_buffer_total_cycles = 49
TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 50
TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 51
TA_PERF_SEL_buffer_coalesced_read_cycles = 52
TA_PERF_SEL_buffer_coalesced_write_cycles = 53
TA_PERF_SEL_addr_stalled_by_tc_cycles = 54
TA_PERF_SEL_addr_stalled_by_td_cycles = 55
TA_PERF_SEL_data_stalled_by_tc_cycles = 56
TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57
TA_PERF_SEL_addresser_stalled_cycles = 58
TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59
TA_PERF_SEL_aniso_stalled_cycles = 60
TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61
TA_PERF_SEL_deriv_stalled_cycles = 62
TA_PERF_SEL_aniso_gt1_cycle_quads = 63
TA_PERF_SEL_color_1_cycle_pixels = 64
TA_PERF_SEL_color_2_cycle_pixels = 65
TA_PERF_SEL_color_3_cycle_pixels = 66
TA_PERF_SEL_color_4_cycle_pixels = 67
TA_PERF_SEL_mip_1_cycle_pixels = 68
TA_PERF_SEL_mip_2_cycle_pixels = 69
TA_PERF_SEL_vol_1_cycle_pixels = 70
TA_PERF_SEL_vol_2_cycle_pixels = 71
TA_PERF_SEL_bilin_point_1_cycle_pixels = 72
TA_PERF_SEL_mipmap_lod_0_samples = 73
TA_PERF_SEL_mipmap_lod_1_samples = 74
TA_PERF_SEL_mipmap_lod_2_samples = 75
TA_PERF_SEL_mipmap_lod_3_samples = 76
TA_PERF_SEL_mipmap_lod_4_samples = 77
TA_PERF_SEL_mipmap_lod_5_samples = 78
TA_PERF_SEL_mipmap_lod_6_samples = 79
TA_PERF_SEL_mipmap_lod_7_samples = 80
TA_PERF_SEL_mipmap_lod_8_samples = 81
TA_PERF_SEL_mipmap_lod_9_samples = 82
TA_PERF_SEL_mipmap_lod_10_samples = 83
TA_PERF_SEL_mipmap_lod_11_samples = 84
TA_PERF_SEL_mipmap_lod_12_samples = 85
TA_PERF_SEL_mipmap_lod_13_samples = 86
TA_PERF_SEL_mipmap_lod_14_samples = 87
TA_PERF_SEL_mipmap_invalid_samples = 88
TA_PERF_SEL_aniso_1_cycle_quads = 89
TA_PERF_SEL_aniso_2_cycle_quads = 90
TA_PERF_SEL_aniso_4_cycle_quads = 91
TA_PERF_SEL_aniso_6_cycle_quads = 92
TA_PERF_SEL_aniso_8_cycle_quads = 93
TA_PERF_SEL_aniso_10_cycle_quads = 94
TA_PERF_SEL_aniso_12_cycle_quads = 95
TA_PERF_SEL_aniso_14_cycle_quads = 96
TA_PERF_SEL_aniso_16_cycle_quads = 97
TA_PERF_SEL_write_path_input_cycles = 98
TA_PERF_SEL_write_path_output_cycles = 99
TA_PERF_SEL_flat_wavefronts = 100
TA_PERF_SEL_flat_read_wavefronts = 101
TA_PERF_SEL_flat_write_wavefronts = 102
TA_PERF_SEL_flat_atomic_wavefronts = 103
TA_PERF_SEL_flat_coalesceable_wavefronts = 104
TA_PERF_SEL_reg_sclk_vld = 105
TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 106
TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 107
TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 108
TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 109
TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 110
TA_PERF_SEL_xnack_on_phase0 = 111
TA_PERF_SEL_xnack_on_phase1 = 112
TA_PERF_SEL_xnack_on_phase2 = 113
TA_PERF_SEL_xnack_on_phase3 = 114
TA_PERF_SEL_first_xnack_on_phase0 = 115
TA_PERF_SEL_first_xnack_on_phase1 = 116
TA_PERF_SEL_first_xnack_on_phase2 = 117
TA_PERF_SEL_first_xnack_on_phase3 = 118
TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TD_PERFCOUNT_SEL'
TD_PERFCOUNT_SEL__enumvalues = {
0: 'TD_PERF_SEL_none',
1: 'TD_PERF_SEL_td_busy',
2: 'TD_PERF_SEL_input_busy',
3: 'TD_PERF_SEL_sampler_lerp_busy',
4: 'TD_PERF_SEL_sampler_out_busy',
5: 'TD_PERF_SEL_nofilter_busy',
6: 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off',
7: 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off',
8: 'TD_PERF_SEL_RESERVED_8',
9: 'TD_PERF_SEL_core_state_rams_read',
10: 'TD_PERF_SEL_weight_data_rams_read',
11: 'TD_PERF_SEL_reference_data_rams_read',
12: 'TD_PERF_SEL_tc_td_data_fifo_full',
13: 'TD_PERF_SEL_tc_td_ram_fifo_full',
14: 'TD_PERF_SEL_input_state_fifo_full',
15: 'TD_PERF_SEL_ta_data_stall',
16: 'TD_PERF_SEL_tc_data_stall',
17: 'TD_PERF_SEL_tc_ram_stall',
18: 'TD_PERF_SEL_lds_stall',
19: 'TD_PERF_SEL_sampler_pkr_full',
20: 'TD_PERF_SEL_nofilter_pkr_full',
21: 'TD_PERF_SEL_RESERVED_21',
22: 'TD_PERF_SEL_gather4_wavefront',
23: 'TD_PERF_SEL_gather4h_wavefront',
24: 'TD_PERF_SEL_gather4h_packed_wavefront',
25: 'TD_PERF_SEL_gather8h_packed_wavefront',
26: 'TD_PERF_SEL_sample_c_wavefront',
27: 'TD_PERF_SEL_load_wavefront',
28: 'TD_PERF_SEL_store_wavefront',
29: 'TD_PERF_SEL_ldfptr_wavefront',
30: 'TD_PERF_SEL_write_ack_wavefront',
31: 'TD_PERF_SEL_d16_en_wavefront',
32: 'TD_PERF_SEL_bypassLerp_wavefront',
33: 'TD_PERF_SEL_min_max_filter_wavefront',
34: 'TD_PERF_SEL_one_comp_wavefront',
35: 'TD_PERF_SEL_two_comp_wavefront',
36: 'TD_PERF_SEL_three_comp_wavefront',
37: 'TD_PERF_SEL_four_comp_wavefront',
38: 'TD_PERF_SEL_user_defined_border',
39: 'TD_PERF_SEL_white_border',
40: 'TD_PERF_SEL_opaque_black_border',
41: 'TD_PERF_SEL_lod_warn_from_ta',
42: 'TD_PERF_SEL_wavefront_dest_is_lds',
43: 'TD_PERF_SEL_td_cycling_of_nofilter_instr',
44: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr',
45: 'TD_PERF_SEL_out_of_order_instr',
46: 'TD_PERF_SEL_total_num_instr',
47: 'TD_PERF_SEL_mixmode_instruction',
48: 'TD_PERF_SEL_mixmode_resource',
49: 'TD_PERF_SEL_status_packet',
50: 'TD_PERF_SEL_address_cmd_poison',
51: 'TD_PERF_SEL_data_poison',
52: 'TD_PERF_SEL_done_scoreboard_not_empty',
53: 'TD_PERF_SEL_done_scoreboard_is_full',
54: 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo',
55: 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds',
56: 'TD_PERF_SEL_nofilter_formatters_turned_off',
57: 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt',
58: 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt',
}
TD_PERF_SEL_none = 0
TD_PERF_SEL_td_busy = 1
TD_PERF_SEL_input_busy = 2
TD_PERF_SEL_sampler_lerp_busy = 3
TD_PERF_SEL_sampler_out_busy = 4
TD_PERF_SEL_nofilter_busy = 5
TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 6
TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 7
TD_PERF_SEL_RESERVED_8 = 8
TD_PERF_SEL_core_state_rams_read = 9
TD_PERF_SEL_weight_data_rams_read = 10
TD_PERF_SEL_reference_data_rams_read = 11
TD_PERF_SEL_tc_td_data_fifo_full = 12
TD_PERF_SEL_tc_td_ram_fifo_full = 13
TD_PERF_SEL_input_state_fifo_full = 14
TD_PERF_SEL_ta_data_stall = 15
TD_PERF_SEL_tc_data_stall = 16
TD_PERF_SEL_tc_ram_stall = 17
TD_PERF_SEL_lds_stall = 18
TD_PERF_SEL_sampler_pkr_full = 19
TD_PERF_SEL_nofilter_pkr_full = 20
TD_PERF_SEL_RESERVED_21 = 21
TD_PERF_SEL_gather4_wavefront = 22
TD_PERF_SEL_gather4h_wavefront = 23
TD_PERF_SEL_gather4h_packed_wavefront = 24
TD_PERF_SEL_gather8h_packed_wavefront = 25
TD_PERF_SEL_sample_c_wavefront = 26
TD_PERF_SEL_load_wavefront = 27
TD_PERF_SEL_store_wavefront = 28
TD_PERF_SEL_ldfptr_wavefront = 29
TD_PERF_SEL_write_ack_wavefront = 30
TD_PERF_SEL_d16_en_wavefront = 31
TD_PERF_SEL_bypassLerp_wavefront = 32
TD_PERF_SEL_min_max_filter_wavefront = 33
TD_PERF_SEL_one_comp_wavefront = 34
TD_PERF_SEL_two_comp_wavefront = 35
TD_PERF_SEL_three_comp_wavefront = 36
TD_PERF_SEL_four_comp_wavefront = 37
TD_PERF_SEL_user_defined_border = 38
TD_PERF_SEL_white_border = 39
TD_PERF_SEL_opaque_black_border = 40
TD_PERF_SEL_lod_warn_from_ta = 41
TD_PERF_SEL_wavefront_dest_is_lds = 42
TD_PERF_SEL_td_cycling_of_nofilter_instr = 43
TD_PERF_SEL_tc_cycling_of_nofilter_instr = 44
TD_PERF_SEL_out_of_order_instr = 45
TD_PERF_SEL_total_num_instr = 46
TD_PERF_SEL_mixmode_instruction = 47
TD_PERF_SEL_mixmode_resource = 48
TD_PERF_SEL_status_packet = 49
TD_PERF_SEL_address_cmd_poison = 50
TD_PERF_SEL_data_poison = 51
TD_PERF_SEL_done_scoreboard_not_empty = 52
TD_PERF_SEL_done_scoreboard_is_full = 53
TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 54
TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 55
TD_PERF_SEL_nofilter_formatters_turned_off = 56
TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 57
TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 58
TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TCP_PERFCOUNT_SELECT'
TCP_PERFCOUNT_SELECT__enumvalues = {
0: 'TCP_PERF_SEL_GATE_EN1',
1: 'TCP_PERF_SEL_GATE_EN2',
2: 'TCP_PERF_SEL_CORE_REG_SCLK_VLD',
3: 'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES',
4: 'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES',
5: 'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES',
6: 'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES',
7: 'TCP_PERF_SEL_TD_TCP_STALL_CYCLES',
8: 'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES',
9: 'TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES',
10: 'TCP_PERF_SEL_LOD_STALL_CYCLES',
11: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES',
12: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES',
13: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES',
14: 'TCP_PERF_SEL_ALLOC_STALL_CYCLES',
15: 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL',
16: 'TCP_PERF_SEL_LFIFO_STALL_CYCLES',
17: 'TCP_PERF_SEL_RFIFO_STALL_CYCLES',
18: 'TCP_PERF_SEL_TCR_RDRET_STALL',
19: 'TCP_PERF_SEL_WRITE_CONFLICT_STALL',
20: 'TCP_PERF_SEL_HOLE_READ_STALL',
21: 'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES',
22: 'TCP_PERF_SEL_PENDING_STALL_CYCLES',
23: 'TCP_PERF_SEL_READFIFO_STALL_CYCLES',
24: 'TCP_PERF_SEL_POWER_STALL',
25: 'TCP_PERF_SEL_UTCL0_SERIALIZATION_STALL',
26: 'TCP_PERF_SEL_TC_TA_XNACK_STALL',
27: 'TCP_PERF_SEL_TA_TCP_STATE_READ',
28: 'TCP_PERF_SEL_TOTAL_ACCESSES',
29: 'TCP_PERF_SEL_TOTAL_READ',
30: 'TCP_PERF_SEL_TOTAL_NON_READ',
31: 'TCP_PERF_SEL_TOTAL_WRITE',
32: 'TCP_PERF_SEL_TOTAL_HIT_LRU_READ',
33: 'TCP_PERF_SEL_TOTAL_MISS_LRU_READ',
34: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ',
35: 'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE',
36: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE',
37: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET',
38: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET',
39: 'TCP_PERF_SEL_TOTAL_WBINVL1',
40: 'TCP_PERF_SEL_CP_TCP_INVALIDATE',
41: 'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES',
42: 'TCP_PERF_SEL_SHOOTDOWN',
43: 'TCP_PERF_SEL_UTCL0_REQUEST',
44: 'TCP_PERF_SEL_UTCL0_TRANSLATION_MISS',
45: 'TCP_PERF_SEL_UTCL0_TRANSLATION_HIT',
46: 'TCP_PERF_SEL_UTCL0_PERMISSION_MISS',
47: 'TCP_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX',
48: 'TCP_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT',
49: 'TCP_PERF_SEL_UTCL0_STALL_MULTI_MISS',
50: 'TCP_PERF_SEL_UTCL0_LFIFO_FULL',
51: 'TCP_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES',
52: 'TCP_PERF_SEL_UTCL0_STALL_UTCL2_REQ_OUT_OF_CREDITS',
53: 'TCP_PERF_SEL_CLIENT_UTCL0_INFLIGHT',
54: 'TCP_PERF_SEL_UTCL0_UTCL2_INFLIGHT',
55: 'TCP_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL',
56: 'TCP_PERF_SEL_TOTAL_CACHE_ACCESSES',
57: 'TCP_PERF_SEL_TAGRAM0_REQ',
58: 'TCP_PERF_SEL_TAGRAM1_REQ',
59: 'TCP_PERF_SEL_TAGRAM2_REQ',
60: 'TCP_PERF_SEL_TAGRAM3_REQ',
61: 'TCP_PERF_SEL_TCP_LATENCY',
62: 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY',
63: 'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY',
64: 'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY',
65: 'TCP_PERF_SEL_TCC_READ_REQ',
66: 'TCP_PERF_SEL_TCC_WRITE_REQ',
67: 'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ',
68: 'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ',
69: 'TCP_PERF_SEL_TCC_LRU_REQ',
70: 'TCP_PERF_SEL_TCC_STREAM_REQ',
71: 'TCP_PERF_SEL_TCC_NC_READ_REQ',
72: 'TCP_PERF_SEL_TCC_NC_WRITE_REQ',
73: 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ',
74: 'TCP_PERF_SEL_TCC_UC_READ_REQ',
75: 'TCP_PERF_SEL_TCC_UC_WRITE_REQ',
76: 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ',
77: 'TCP_PERF_SEL_TCC_CC_READ_REQ',
78: 'TCP_PERF_SEL_TCC_CC_WRITE_REQ',
79: 'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ',
80: 'TCP_PERF_SEL_TCC_DCC_REQ',
81: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET',
82: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET',
83: 'TCP_PERF_SEL_GL1_REQ_READ',
84: 'TCP_PERF_SEL_GL1_REQ_READ_LATENCY',
85: 'TCP_PERF_SEL_GL1_REQ_WRITE',
86: 'TCP_PERF_SEL_GL1_REQ_WRITE_LATENCY',
87: 'TCP_PERF_SEL_REQ_MISS_TAGRAM0',
88: 'TCP_PERF_SEL_REQ_MISS_TAGRAM1',
89: 'TCP_PERF_SEL_REQ_MISS_TAGRAM2',
90: 'TCP_PERF_SEL_REQ_MISS_TAGRAM3',
91: 'TCP_PERF_SEL_TA_REQ',
92: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET',
93: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET',
94: 'TCP_PERF_SEL_TA_REQ_READ',
95: 'TCP_PERF_SEL_TA_REQ_WRITE',
96: 'TCP_PERF_SEL_TA_REQ_STATE_READ',
}
TCP_PERF_SEL_GATE_EN1 = 0
TCP_PERF_SEL_GATE_EN2 = 1
TCP_PERF_SEL_CORE_REG_SCLK_VLD = 2
TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 3
TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 4
TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 5
TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 6
TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 7
TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 8
TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES = 9
TCP_PERF_SEL_LOD_STALL_CYCLES = 10
TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 11
TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 12
TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 13
TCP_PERF_SEL_ALLOC_STALL_CYCLES = 14
TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 15
TCP_PERF_SEL_LFIFO_STALL_CYCLES = 16
TCP_PERF_SEL_RFIFO_STALL_CYCLES = 17
TCP_PERF_SEL_TCR_RDRET_STALL = 18
TCP_PERF_SEL_WRITE_CONFLICT_STALL = 19
TCP_PERF_SEL_HOLE_READ_STALL = 20
TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 21
TCP_PERF_SEL_PENDING_STALL_CYCLES = 22
TCP_PERF_SEL_READFIFO_STALL_CYCLES = 23
TCP_PERF_SEL_POWER_STALL = 24
TCP_PERF_SEL_UTCL0_SERIALIZATION_STALL = 25
TCP_PERF_SEL_TC_TA_XNACK_STALL = 26
TCP_PERF_SEL_TA_TCP_STATE_READ = 27
TCP_PERF_SEL_TOTAL_ACCESSES = 28
TCP_PERF_SEL_TOTAL_READ = 29
TCP_PERF_SEL_TOTAL_NON_READ = 30
TCP_PERF_SEL_TOTAL_WRITE = 31
TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 32
TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 33
TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 34
TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 35
TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 36
TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 37
TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 38
TCP_PERF_SEL_TOTAL_WBINVL1 = 39
TCP_PERF_SEL_CP_TCP_INVALIDATE = 40
TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 41
TCP_PERF_SEL_SHOOTDOWN = 42
TCP_PERF_SEL_UTCL0_REQUEST = 43
TCP_PERF_SEL_UTCL0_TRANSLATION_MISS = 44
TCP_PERF_SEL_UTCL0_TRANSLATION_HIT = 45
TCP_PERF_SEL_UTCL0_PERMISSION_MISS = 46
TCP_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 47
TCP_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 48
TCP_PERF_SEL_UTCL0_STALL_MULTI_MISS = 49
TCP_PERF_SEL_UTCL0_LFIFO_FULL = 50
TCP_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 51
TCP_PERF_SEL_UTCL0_STALL_UTCL2_REQ_OUT_OF_CREDITS = 52
TCP_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 53
TCP_PERF_SEL_UTCL0_UTCL2_INFLIGHT = 54
TCP_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 55
TCP_PERF_SEL_TOTAL_CACHE_ACCESSES = 56
TCP_PERF_SEL_TAGRAM0_REQ = 57
TCP_PERF_SEL_TAGRAM1_REQ = 58
TCP_PERF_SEL_TAGRAM2_REQ = 59
TCP_PERF_SEL_TAGRAM3_REQ = 60
TCP_PERF_SEL_TCP_LATENCY = 61
TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 62
TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 63
TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 64
TCP_PERF_SEL_TCC_READ_REQ = 65
TCP_PERF_SEL_TCC_WRITE_REQ = 66
TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 67
TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 68
TCP_PERF_SEL_TCC_LRU_REQ = 69
TCP_PERF_SEL_TCC_STREAM_REQ = 70
TCP_PERF_SEL_TCC_NC_READ_REQ = 71
TCP_PERF_SEL_TCC_NC_WRITE_REQ = 72
TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 73
TCP_PERF_SEL_TCC_UC_READ_REQ = 74
TCP_PERF_SEL_TCC_UC_WRITE_REQ = 75
TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 76
TCP_PERF_SEL_TCC_CC_READ_REQ = 77
TCP_PERF_SEL_TCC_CC_WRITE_REQ = 78
TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 79
TCP_PERF_SEL_TCC_DCC_REQ = 80
TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 81
TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 82
TCP_PERF_SEL_GL1_REQ_READ = 83
TCP_PERF_SEL_GL1_REQ_READ_LATENCY = 84
TCP_PERF_SEL_GL1_REQ_WRITE = 85
TCP_PERF_SEL_GL1_REQ_WRITE_LATENCY = 86
TCP_PERF_SEL_REQ_MISS_TAGRAM0 = 87
TCP_PERF_SEL_REQ_MISS_TAGRAM1 = 88
TCP_PERF_SEL_REQ_MISS_TAGRAM2 = 89
TCP_PERF_SEL_REQ_MISS_TAGRAM3 = 90
TCP_PERF_SEL_TA_REQ = 91
TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 92
TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 93
TCP_PERF_SEL_TA_REQ_READ = 94
TCP_PERF_SEL_TA_REQ_WRITE = 95
TCP_PERF_SEL_TA_REQ_STATE_READ = 96
TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'TCP_CACHE_POLICIES'
TCP_CACHE_POLICIES__enumvalues = {
0: 'TCP_CACHE_POLICY_MISS_LRU',
1: 'TCP_CACHE_POLICY_MISS_EVICT',
2: 'TCP_CACHE_POLICY_HIT_LRU',
3: 'TCP_CACHE_POLICY_HIT_EVICT',
}
TCP_CACHE_POLICY_MISS_LRU = 0
TCP_CACHE_POLICY_MISS_EVICT = 1
TCP_CACHE_POLICY_HIT_LRU = 2
TCP_CACHE_POLICY_HIT_EVICT = 3
TCP_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'TCP_CACHE_STORE_POLICIES'
TCP_CACHE_STORE_POLICIES__enumvalues = {
0: 'TCP_CACHE_STORE_POLICY_WT_LRU',
1: 'TCP_CACHE_STORE_POLICY_WT_EVICT',
}
TCP_CACHE_STORE_POLICY_WT_LRU = 0
TCP_CACHE_STORE_POLICY_WT_EVICT = 1
TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'TCP_WATCH_MODES'
TCP_WATCH_MODES__enumvalues = {
0: 'TCP_WATCH_MODE_READ',
1: 'TCP_WATCH_MODE_NONREAD',
2: 'TCP_WATCH_MODE_ATOMIC',
3: 'TCP_WATCH_MODE_ALL',
}
TCP_WATCH_MODE_READ = 0
TCP_WATCH_MODE_NONREAD = 1
TCP_WATCH_MODE_ATOMIC = 2
TCP_WATCH_MODE_ALL = 3
TCP_WATCH_MODES = ctypes.c_uint32 # enum
# values for enumeration 'TCP_DSM_DATA_SEL'
TCP_DSM_DATA_SEL__enumvalues = {
0: 'TCP_DSM_DISABLE',
1: 'TCP_DSM_SEL0',
2: 'TCP_DSM_SEL1',
3: 'TCP_DSM_SEL_BOTH',
}
TCP_DSM_DISABLE = 0
TCP_DSM_SEL0 = 1
TCP_DSM_SEL1 = 2
TCP_DSM_SEL_BOTH = 3
TCP_DSM_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TCP_DSM_SINGLE_WRITE'
TCP_DSM_SINGLE_WRITE__enumvalues = {
0: 'TCP_DSM_SINGLE_WRITE_DIS',
1: 'TCP_DSM_SINGLE_WRITE_EN',
}
TCP_DSM_SINGLE_WRITE_DIS = 0
TCP_DSM_SINGLE_WRITE_EN = 1
TCP_DSM_SINGLE_WRITE = ctypes.c_uint32 # enum
# values for enumeration 'TCP_DSM_INJECT_SEL'
TCP_DSM_INJECT_SEL__enumvalues = {
0: 'TCP_DSM_INJECT_SEL0',
1: 'TCP_DSM_INJECT_SEL1',
2: 'TCP_DSM_INJECT_SEL2',
3: 'TCP_DSM_INJECT_SEL3',
}
TCP_DSM_INJECT_SEL0 = 0
TCP_DSM_INJECT_SEL1 = 1
TCP_DSM_INJECT_SEL2 = 2
TCP_DSM_INJECT_SEL3 = 3
TCP_DSM_INJECT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TCP_OPCODE_TYPE'
TCP_OPCODE_TYPE__enumvalues = {
0: 'TCP_OPCODE_READ',
1: 'TCP_OPCODE_WRITE',
2: 'TCP_OPCODE_ATOMIC',
3: 'TCP_OPCODE_WBINVL1',
4: 'TCP_OPCODE_ATOMIC_CMPSWAP',
5: 'TCP_OPCODE_GATHERH',
}
TCP_OPCODE_READ = 0
TCP_OPCODE_WRITE = 1
TCP_OPCODE_ATOMIC = 2
TCP_OPCODE_WBINVL1 = 3
TCP_OPCODE_ATOMIC_CMPSWAP = 4
TCP_OPCODE_GATHERH = 5
TCP_OPCODE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'GL2C_PERF_SEL'
GL2C_PERF_SEL__enumvalues = {
0: 'GL2C_PERF_SEL_NONE',
1: 'GL2C_PERF_SEL_CYCLE',
2: 'GL2C_PERF_SEL_BUSY',
3: 'GL2C_PERF_SEL_REQ',
4: 'GL2C_PERF_SEL_VOL_REQ',
5: 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ',
6: 'GL2C_PERF_SEL_READ',
7: 'GL2C_PERF_SEL_WRITE',
8: 'GL2C_PERF_SEL_ATOMIC',
9: 'GL2C_PERF_SEL_NOP_ACK',
10: 'GL2C_PERF_SEL_NOP_RTN0',
11: 'GL2C_PERF_SEL_PROBE',
12: 'GL2C_PERF_SEL_PROBE_ALL',
13: 'GL2C_PERF_SEL_INTERNAL_PROBE',
14: 'GL2C_PERF_SEL_COMPRESSED_READ_REQ',
15: 'GL2C_PERF_SEL_METADATA_READ_REQ',
16: 'GL2C_PERF_SEL_CLIENT0_REQ',
17: 'GL2C_PERF_SEL_CLIENT1_REQ',
18: 'GL2C_PERF_SEL_CLIENT2_REQ',
19: 'GL2C_PERF_SEL_CLIENT3_REQ',
20: 'GL2C_PERF_SEL_CLIENT4_REQ',
21: 'GL2C_PERF_SEL_CLIENT5_REQ',
22: 'GL2C_PERF_SEL_CLIENT6_REQ',
23: 'GL2C_PERF_SEL_CLIENT7_REQ',
24: 'GL2C_PERF_SEL_C_RW_S_REQ',
25: 'GL2C_PERF_SEL_C_RW_US_REQ',
26: 'GL2C_PERF_SEL_C_RO_S_REQ',
27: 'GL2C_PERF_SEL_C_RO_US_REQ',
28: 'GL2C_PERF_SEL_UC_REQ',
29: 'GL2C_PERF_SEL_LRU_REQ',
30: 'GL2C_PERF_SEL_STREAM_REQ',
31: 'GL2C_PERF_SEL_BYPASS_REQ',
32: 'GL2C_PERF_SEL_NOA_REQ',
33: 'GL2C_PERF_SEL_SHARED_REQ',
34: 'GL2C_PERF_SEL_HIT',
35: 'GL2C_PERF_SEL_MISS',
36: 'GL2C_PERF_SEL_FULL_HIT',
37: 'GL2C_PERF_SEL_PARTIAL_32B_HIT',
38: 'GL2C_PERF_SEL_PARTIAL_64B_HIT',
39: 'GL2C_PERF_SEL_PARTIAL_96B_HIT',
40: 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT',
41: 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT',
42: 'GL2C_PERF_SEL_UNCACHED_WRITE',
43: 'GL2C_PERF_SEL_WRITEBACK',
44: 'GL2C_PERF_SEL_NORMAL_WRITEBACK',
45: 'GL2C_PERF_SEL_EVICT',
46: 'GL2C_PERF_SEL_NORMAL_EVICT',
47: 'GL2C_PERF_SEL_PROBE_EVICT',
48: 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE',
49: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO',
50: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP',
51: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0',
52: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1',
53: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2',
54: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3',
55: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4',
56: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5',
57: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6',
58: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7',
59: 'GL2C_PERF_SEL_READ_32_REQ',
60: 'GL2C_PERF_SEL_READ_64_REQ',
61: 'GL2C_PERF_SEL_READ_128_REQ',
62: 'GL2C_PERF_SEL_WRITE_32_REQ',
63: 'GL2C_PERF_SEL_WRITE_64_REQ',
64: 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ',
65: 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ',
66: 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ',
67: 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ',
68: 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ',
69: 'GL2C_PERF_SEL_MC_WRREQ',
70: 'GL2C_PERF_SEL_EA_WRREQ_64B',
71: 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND',
72: 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B',
73: 'GL2C_PERF_SEL_MC_WRREQ_STALL',
74: 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL',
75: 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL',
76: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL',
77: 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL',
78: 'GL2C_PERF_SEL_MC_WRREQ_LEVEL',
79: 'GL2C_PERF_SEL_EA_ATOMIC',
80: 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL',
81: 'GL2C_PERF_SEL_MC_RDREQ',
82: 'GL2C_PERF_SEL_EA_RDREQ_SPLIT',
83: 'GL2C_PERF_SEL_EA_RDREQ_32B',
84: 'GL2C_PERF_SEL_EA_RDREQ_64B',
85: 'GL2C_PERF_SEL_EA_RDREQ_96B',
86: 'GL2C_PERF_SEL_EA_RDREQ_128B',
87: 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B',
88: 'GL2C_PERF_SEL_EA_RD_MDC_32B',
89: 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B',
90: 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL',
91: 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL',
92: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL',
93: 'GL2C_PERF_SEL_MC_RDREQ_LEVEL',
94: 'GL2C_PERF_SEL_EA_RDREQ_DRAM',
95: 'GL2C_PERF_SEL_EA_WRREQ_DRAM',
96: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B',
97: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B',
98: 'GL2C_PERF_SEL_ONION_READ',
99: 'GL2C_PERF_SEL_ONION_WRITE',
100: 'GL2C_PERF_SEL_IO_READ',
101: 'GL2C_PERF_SEL_IO_WRITE',
102: 'GL2C_PERF_SEL_GARLIC_READ',
103: 'GL2C_PERF_SEL_GARLIC_WRITE',
104: 'GL2C_PERF_SEL_LATENCY_FIFO_FULL',
105: 'GL2C_PERF_SEL_SRC_FIFO_FULL',
106: 'GL2C_PERF_SEL_TAG_STALL',
107: 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL',
108: 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL',
109: 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL',
110: 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL',
111: 'GL2C_PERF_SEL_TAG_PROBE_STALL',
112: 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL',
113: 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL',
114: 'GL2C_PERF_SEL_TAG_READ_DST_STALL',
115: 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT',
116: 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT',
117: 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE',
118: 'GL2C_PERF_SEL_BUBBLE',
119: 'GL2C_PERF_SEL_IB_REQ',
120: 'GL2C_PERF_SEL_IB_STALL',
121: 'GL2C_PERF_SEL_IB_TAG_STALL',
122: 'GL2C_PERF_SEL_IB_CM_STALL',
123: 'GL2C_PERF_SEL_RETURN_ACK',
124: 'GL2C_PERF_SEL_RETURN_DATA',
125: 'GL2C_PERF_SEL_EA_RDRET_NACK',
126: 'GL2C_PERF_SEL_EA_WRRET_NACK',
127: 'GL2C_PERF_SEL_GL2A_LEVEL',
128: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION',
129: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED',
130: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START',
131: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START',
132: 'GL2C_PERF_SEL_GCR_INV',
133: 'GL2C_PERF_SEL_GCR_WB',
134: 'GL2C_PERF_SEL_GCR_DISCARD',
135: 'GL2C_PERF_SEL_GCR_RANGE',
136: 'GL2C_PERF_SEL_GCR_ALL',
137: 'GL2C_PERF_SEL_GCR_VOL',
138: 'GL2C_PERF_SEL_GCR_UNSHARED',
139: 'GL2C_PERF_SEL_GCR_MDC_INV',
140: 'GL2C_PERF_SEL_GCR_GL2_INV_ALL',
141: 'GL2C_PERF_SEL_GCR_GL2_WB_ALL',
142: 'GL2C_PERF_SEL_GCR_MDC_INV_ALL',
143: 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE',
144: 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE',
145: 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE',
146: 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE',
147: 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT',
148: 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT',
149: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE',
150: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE',
151: 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK',
152: 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE',
153: 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT',
154: 'GL2C_PERF_SEL_GCR_INVL2_VOL_START',
155: 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE',
156: 'GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT',
157: 'GL2C_PERF_SEL_GCR_WBL2_VOL_START',
158: 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE',
159: 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT',
160: 'GL2C_PERF_SEL_GCR_WBINVL2_START',
161: 'GL2C_PERF_SEL_MDC_INV_METADATA',
162: 'GL2C_PERF_SEL_MDC_REQ',
163: 'GL2C_PERF_SEL_MDC_LEVEL',
164: 'GL2C_PERF_SEL_MDC_TAG_HIT',
165: 'GL2C_PERF_SEL_MDC_SECTOR_HIT',
166: 'GL2C_PERF_SEL_MDC_SECTOR_MISS',
167: 'GL2C_PERF_SEL_MDC_TAG_STALL',
168: 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL',
169: 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL',
170: 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL',
171: 'GL2C_PERF_SEL_CM_CHANNEL0_REQ',
172: 'GL2C_PERF_SEL_CM_CHANNEL1_REQ',
173: 'GL2C_PERF_SEL_CM_CHANNEL2_REQ',
174: 'GL2C_PERF_SEL_CM_CHANNEL3_REQ',
175: 'GL2C_PERF_SEL_CM_CHANNEL4_REQ',
176: 'GL2C_PERF_SEL_CM_CHANNEL5_REQ',
177: 'GL2C_PERF_SEL_CM_CHANNEL6_REQ',
178: 'GL2C_PERF_SEL_CM_CHANNEL7_REQ',
179: 'GL2C_PERF_SEL_CM_CHANNEL8_REQ',
180: 'GL2C_PERF_SEL_CM_CHANNEL9_REQ',
181: 'GL2C_PERF_SEL_CM_CHANNEL10_REQ',
182: 'GL2C_PERF_SEL_CM_CHANNEL11_REQ',
183: 'GL2C_PERF_SEL_CM_CHANNEL12_REQ',
184: 'GL2C_PERF_SEL_CM_CHANNEL13_REQ',
185: 'GL2C_PERF_SEL_CM_CHANNEL14_REQ',
186: 'GL2C_PERF_SEL_CM_CHANNEL15_REQ',
187: 'GL2C_PERF_SEL_CM_CHANNEL16_REQ',
188: 'GL2C_PERF_SEL_CM_CHANNEL17_REQ',
189: 'GL2C_PERF_SEL_CM_CHANNEL18_REQ',
190: 'GL2C_PERF_SEL_CM_CHANNEL19_REQ',
191: 'GL2C_PERF_SEL_CM_CHANNEL20_REQ',
192: 'GL2C_PERF_SEL_CM_CHANNEL21_REQ',
193: 'GL2C_PERF_SEL_CM_CHANNEL22_REQ',
194: 'GL2C_PERF_SEL_CM_CHANNEL23_REQ',
195: 'GL2C_PERF_SEL_CM_CHANNEL24_REQ',
196: 'GL2C_PERF_SEL_CM_CHANNEL25_REQ',
197: 'GL2C_PERF_SEL_CM_CHANNEL26_REQ',
198: 'GL2C_PERF_SEL_CM_CHANNEL27_REQ',
199: 'GL2C_PERF_SEL_CM_CHANNEL28_REQ',
200: 'GL2C_PERF_SEL_CM_CHANNEL29_REQ',
201: 'GL2C_PERF_SEL_CM_CHANNEL30_REQ',
202: 'GL2C_PERF_SEL_CM_CHANNEL31_REQ',
203: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ',
204: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ',
205: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ',
206: 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ',
207: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ',
208: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ',
209: 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ',
210: 'GL2C_PERF_SEL_CM_COMP_READ_REQ',
211: 'GL2C_PERF_SEL_CM_READ_BACK_REQ',
212: 'GL2C_PERF_SEL_CM_METADATA_WR_REQ',
213: 'GL2C_PERF_SEL_CM_WR_ACK_REQ',
214: 'GL2C_PERF_SEL_CM_NO_ACK_REQ',
215: 'GL2C_PERF_SEL_CM_NOOP_REQ',
216: 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ',
217: 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ',
218: 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ',
219: 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ',
220: 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ',
221: 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ',
222: 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ',
223: 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ',
224: 'GL2C_PERF_SEL_CM_RVF_FULL',
225: 'GL2C_PERF_SEL_CM_SDR_FULL',
226: 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL',
227: 'GL2C_PERF_SEL_CM_DCC_STALL',
}
GL2C_PERF_SEL_NONE = 0
GL2C_PERF_SEL_CYCLE = 1
GL2C_PERF_SEL_BUSY = 2
GL2C_PERF_SEL_REQ = 3
GL2C_PERF_SEL_VOL_REQ = 4
GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 5
GL2C_PERF_SEL_READ = 6
GL2C_PERF_SEL_WRITE = 7
GL2C_PERF_SEL_ATOMIC = 8
GL2C_PERF_SEL_NOP_ACK = 9
GL2C_PERF_SEL_NOP_RTN0 = 10
GL2C_PERF_SEL_PROBE = 11
GL2C_PERF_SEL_PROBE_ALL = 12
GL2C_PERF_SEL_INTERNAL_PROBE = 13
GL2C_PERF_SEL_COMPRESSED_READ_REQ = 14
GL2C_PERF_SEL_METADATA_READ_REQ = 15
GL2C_PERF_SEL_CLIENT0_REQ = 16
GL2C_PERF_SEL_CLIENT1_REQ = 17
GL2C_PERF_SEL_CLIENT2_REQ = 18
GL2C_PERF_SEL_CLIENT3_REQ = 19
GL2C_PERF_SEL_CLIENT4_REQ = 20
GL2C_PERF_SEL_CLIENT5_REQ = 21
GL2C_PERF_SEL_CLIENT6_REQ = 22
GL2C_PERF_SEL_CLIENT7_REQ = 23
GL2C_PERF_SEL_C_RW_S_REQ = 24
GL2C_PERF_SEL_C_RW_US_REQ = 25
GL2C_PERF_SEL_C_RO_S_REQ = 26
GL2C_PERF_SEL_C_RO_US_REQ = 27
GL2C_PERF_SEL_UC_REQ = 28
GL2C_PERF_SEL_LRU_REQ = 29
GL2C_PERF_SEL_STREAM_REQ = 30
GL2C_PERF_SEL_BYPASS_REQ = 31
GL2C_PERF_SEL_NOA_REQ = 32
GL2C_PERF_SEL_SHARED_REQ = 33
GL2C_PERF_SEL_HIT = 34
GL2C_PERF_SEL_MISS = 35
GL2C_PERF_SEL_FULL_HIT = 36
GL2C_PERF_SEL_PARTIAL_32B_HIT = 37
GL2C_PERF_SEL_PARTIAL_64B_HIT = 38
GL2C_PERF_SEL_PARTIAL_96B_HIT = 39
GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 40
GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 41
GL2C_PERF_SEL_UNCACHED_WRITE = 42
GL2C_PERF_SEL_WRITEBACK = 43
GL2C_PERF_SEL_NORMAL_WRITEBACK = 44
GL2C_PERF_SEL_EVICT = 45
GL2C_PERF_SEL_NORMAL_EVICT = 46
GL2C_PERF_SEL_PROBE_EVICT = 47
GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 48
GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO = 49
GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP = 50
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 51
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 52
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 53
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 54
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 55
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 56
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 57
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 58
GL2C_PERF_SEL_READ_32_REQ = 59
GL2C_PERF_SEL_READ_64_REQ = 60
GL2C_PERF_SEL_READ_128_REQ = 61
GL2C_PERF_SEL_WRITE_32_REQ = 62
GL2C_PERF_SEL_WRITE_64_REQ = 63
GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 64
GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 65
GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 66
GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 67
GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 68
GL2C_PERF_SEL_MC_WRREQ = 69
GL2C_PERF_SEL_EA_WRREQ_64B = 70
GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 71
GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 72
GL2C_PERF_SEL_MC_WRREQ_STALL = 73
GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 74
GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 75
GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 76
GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 77
GL2C_PERF_SEL_MC_WRREQ_LEVEL = 78
GL2C_PERF_SEL_EA_ATOMIC = 79
GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 80
GL2C_PERF_SEL_MC_RDREQ = 81
GL2C_PERF_SEL_EA_RDREQ_SPLIT = 82
GL2C_PERF_SEL_EA_RDREQ_32B = 83
GL2C_PERF_SEL_EA_RDREQ_64B = 84
GL2C_PERF_SEL_EA_RDREQ_96B = 85
GL2C_PERF_SEL_EA_RDREQ_128B = 86
GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 87
GL2C_PERF_SEL_EA_RD_MDC_32B = 88
GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 89
GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 90
GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 91
GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 92
GL2C_PERF_SEL_MC_RDREQ_LEVEL = 93
GL2C_PERF_SEL_EA_RDREQ_DRAM = 94
GL2C_PERF_SEL_EA_WRREQ_DRAM = 95
GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 96
GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 97
GL2C_PERF_SEL_ONION_READ = 98
GL2C_PERF_SEL_ONION_WRITE = 99
GL2C_PERF_SEL_IO_READ = 100
GL2C_PERF_SEL_IO_WRITE = 101
GL2C_PERF_SEL_GARLIC_READ = 102
GL2C_PERF_SEL_GARLIC_WRITE = 103
GL2C_PERF_SEL_LATENCY_FIFO_FULL = 104
GL2C_PERF_SEL_SRC_FIFO_FULL = 105
GL2C_PERF_SEL_TAG_STALL = 106
GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 107
GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 108
GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 109
GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 110
GL2C_PERF_SEL_TAG_PROBE_STALL = 111
GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 112
GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 113
GL2C_PERF_SEL_TAG_READ_DST_STALL = 114
GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 115
GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 116
GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 117
GL2C_PERF_SEL_BUBBLE = 118
GL2C_PERF_SEL_IB_REQ = 119
GL2C_PERF_SEL_IB_STALL = 120
GL2C_PERF_SEL_IB_TAG_STALL = 121
GL2C_PERF_SEL_IB_CM_STALL = 122
GL2C_PERF_SEL_RETURN_ACK = 123
GL2C_PERF_SEL_RETURN_DATA = 124
GL2C_PERF_SEL_EA_RDRET_NACK = 125
GL2C_PERF_SEL_EA_WRRET_NACK = 126
GL2C_PERF_SEL_GL2A_LEVEL = 127
GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 128
GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 129
GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 130
GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 131
GL2C_PERF_SEL_GCR_INV = 132
GL2C_PERF_SEL_GCR_WB = 133
GL2C_PERF_SEL_GCR_DISCARD = 134
GL2C_PERF_SEL_GCR_RANGE = 135
GL2C_PERF_SEL_GCR_ALL = 136
GL2C_PERF_SEL_GCR_VOL = 137
GL2C_PERF_SEL_GCR_UNSHARED = 138
GL2C_PERF_SEL_GCR_MDC_INV = 139
GL2C_PERF_SEL_GCR_GL2_INV_ALL = 140
GL2C_PERF_SEL_GCR_GL2_WB_ALL = 141
GL2C_PERF_SEL_GCR_MDC_INV_ALL = 142
GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 143
GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 144
GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 145
GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 146
GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 147
GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 148
GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 149
GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 150
GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 151
GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 152
GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 153
GL2C_PERF_SEL_GCR_INVL2_VOL_START = 154
GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 155
GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT = 156
GL2C_PERF_SEL_GCR_WBL2_VOL_START = 157
GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 158
GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 159
GL2C_PERF_SEL_GCR_WBINVL2_START = 160
GL2C_PERF_SEL_MDC_INV_METADATA = 161
GL2C_PERF_SEL_MDC_REQ = 162
GL2C_PERF_SEL_MDC_LEVEL = 163
GL2C_PERF_SEL_MDC_TAG_HIT = 164
GL2C_PERF_SEL_MDC_SECTOR_HIT = 165
GL2C_PERF_SEL_MDC_SECTOR_MISS = 166
GL2C_PERF_SEL_MDC_TAG_STALL = 167
GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 168
GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 169
GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 170
GL2C_PERF_SEL_CM_CHANNEL0_REQ = 171
GL2C_PERF_SEL_CM_CHANNEL1_REQ = 172
GL2C_PERF_SEL_CM_CHANNEL2_REQ = 173
GL2C_PERF_SEL_CM_CHANNEL3_REQ = 174
GL2C_PERF_SEL_CM_CHANNEL4_REQ = 175
GL2C_PERF_SEL_CM_CHANNEL5_REQ = 176
GL2C_PERF_SEL_CM_CHANNEL6_REQ = 177
GL2C_PERF_SEL_CM_CHANNEL7_REQ = 178
GL2C_PERF_SEL_CM_CHANNEL8_REQ = 179
GL2C_PERF_SEL_CM_CHANNEL9_REQ = 180
GL2C_PERF_SEL_CM_CHANNEL10_REQ = 181
GL2C_PERF_SEL_CM_CHANNEL11_REQ = 182
GL2C_PERF_SEL_CM_CHANNEL12_REQ = 183
GL2C_PERF_SEL_CM_CHANNEL13_REQ = 184
GL2C_PERF_SEL_CM_CHANNEL14_REQ = 185
GL2C_PERF_SEL_CM_CHANNEL15_REQ = 186
GL2C_PERF_SEL_CM_CHANNEL16_REQ = 187
GL2C_PERF_SEL_CM_CHANNEL17_REQ = 188
GL2C_PERF_SEL_CM_CHANNEL18_REQ = 189
GL2C_PERF_SEL_CM_CHANNEL19_REQ = 190
GL2C_PERF_SEL_CM_CHANNEL20_REQ = 191
GL2C_PERF_SEL_CM_CHANNEL21_REQ = 192
GL2C_PERF_SEL_CM_CHANNEL22_REQ = 193
GL2C_PERF_SEL_CM_CHANNEL23_REQ = 194
GL2C_PERF_SEL_CM_CHANNEL24_REQ = 195
GL2C_PERF_SEL_CM_CHANNEL25_REQ = 196
GL2C_PERF_SEL_CM_CHANNEL26_REQ = 197
GL2C_PERF_SEL_CM_CHANNEL27_REQ = 198
GL2C_PERF_SEL_CM_CHANNEL28_REQ = 199
GL2C_PERF_SEL_CM_CHANNEL29_REQ = 200
GL2C_PERF_SEL_CM_CHANNEL30_REQ = 201
GL2C_PERF_SEL_CM_CHANNEL31_REQ = 202
GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 203
GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 204
GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 205
GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 206
GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 207
GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 208
GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 209
GL2C_PERF_SEL_CM_COMP_READ_REQ = 210
GL2C_PERF_SEL_CM_READ_BACK_REQ = 211
GL2C_PERF_SEL_CM_METADATA_WR_REQ = 212
GL2C_PERF_SEL_CM_WR_ACK_REQ = 213
GL2C_PERF_SEL_CM_NO_ACK_REQ = 214
GL2C_PERF_SEL_CM_NOOP_REQ = 215
GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 216
GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 217
GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 218
GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 219
GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 220
GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 221
GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 222
GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 223
GL2C_PERF_SEL_CM_RVF_FULL = 224
GL2C_PERF_SEL_CM_SDR_FULL = 225
GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 226
GL2C_PERF_SEL_CM_DCC_STALL = 227
GL2C_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL2A_PERF_SEL'
GL2A_PERF_SEL__enumvalues = {
0: 'GL2A_PERF_SEL_NONE',
1: 'GL2A_PERF_SEL_CYCLE',
2: 'GL2A_PERF_SEL_BUSY',
3: 'GL2A_PERF_SEL_REQ_GL2C0',
4: 'GL2A_PERF_SEL_REQ_GL2C1',
5: 'GL2A_PERF_SEL_REQ_GL2C2',
6: 'GL2A_PERF_SEL_REQ_GL2C3',
7: 'GL2A_PERF_SEL_REQ_GL2C4',
8: 'GL2A_PERF_SEL_REQ_GL2C5',
9: 'GL2A_PERF_SEL_REQ_GL2C6',
10: 'GL2A_PERF_SEL_REQ_GL2C7',
11: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0',
12: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1',
13: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2',
14: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3',
15: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4',
16: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5',
17: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6',
18: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7',
19: 'GL2A_PERF_SEL_REQ_BURST_GL2C0',
20: 'GL2A_PERF_SEL_REQ_BURST_GL2C1',
21: 'GL2A_PERF_SEL_REQ_BURST_GL2C2',
22: 'GL2A_PERF_SEL_REQ_BURST_GL2C3',
23: 'GL2A_PERF_SEL_REQ_BURST_GL2C4',
24: 'GL2A_PERF_SEL_REQ_BURST_GL2C5',
25: 'GL2A_PERF_SEL_REQ_BURST_GL2C6',
26: 'GL2A_PERF_SEL_REQ_BURST_GL2C7',
27: 'GL2A_PERF_SEL_REQ_STALL_GL2C0',
28: 'GL2A_PERF_SEL_REQ_STALL_GL2C1',
29: 'GL2A_PERF_SEL_REQ_STALL_GL2C2',
30: 'GL2A_PERF_SEL_REQ_STALL_GL2C3',
31: 'GL2A_PERF_SEL_REQ_STALL_GL2C4',
32: 'GL2A_PERF_SEL_REQ_STALL_GL2C5',
33: 'GL2A_PERF_SEL_REQ_STALL_GL2C6',
34: 'GL2A_PERF_SEL_REQ_STALL_GL2C7',
35: 'GL2A_PERF_SEL_RTN_STALL_GL2C0',
36: 'GL2A_PERF_SEL_RTN_STALL_GL2C1',
37: 'GL2A_PERF_SEL_RTN_STALL_GL2C2',
38: 'GL2A_PERF_SEL_RTN_STALL_GL2C3',
39: 'GL2A_PERF_SEL_RTN_STALL_GL2C4',
40: 'GL2A_PERF_SEL_RTN_STALL_GL2C5',
41: 'GL2A_PERF_SEL_RTN_STALL_GL2C6',
42: 'GL2A_PERF_SEL_RTN_STALL_GL2C7',
43: 'GL2A_PERF_SEL_RTN_CLIENT0',
44: 'GL2A_PERF_SEL_RTN_CLIENT1',
45: 'GL2A_PERF_SEL_RTN_CLIENT2',
46: 'GL2A_PERF_SEL_RTN_CLIENT3',
47: 'GL2A_PERF_SEL_RTN_CLIENT4',
48: 'GL2A_PERF_SEL_RTN_CLIENT5',
49: 'GL2A_PERF_SEL_RTN_CLIENT6',
50: 'GL2A_PERF_SEL_RTN_CLIENT7',
51: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0',
52: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1',
53: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2',
54: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3',
55: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4',
56: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5',
57: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6',
58: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7',
}
GL2A_PERF_SEL_NONE = 0
GL2A_PERF_SEL_CYCLE = 1
GL2A_PERF_SEL_BUSY = 2
GL2A_PERF_SEL_REQ_GL2C0 = 3
GL2A_PERF_SEL_REQ_GL2C1 = 4
GL2A_PERF_SEL_REQ_GL2C2 = 5
GL2A_PERF_SEL_REQ_GL2C3 = 6
GL2A_PERF_SEL_REQ_GL2C4 = 7
GL2A_PERF_SEL_REQ_GL2C5 = 8
GL2A_PERF_SEL_REQ_GL2C6 = 9
GL2A_PERF_SEL_REQ_GL2C7 = 10
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 11
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 12
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 13
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 14
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 15
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 16
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 17
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 18
GL2A_PERF_SEL_REQ_BURST_GL2C0 = 19
GL2A_PERF_SEL_REQ_BURST_GL2C1 = 20
GL2A_PERF_SEL_REQ_BURST_GL2C2 = 21
GL2A_PERF_SEL_REQ_BURST_GL2C3 = 22
GL2A_PERF_SEL_REQ_BURST_GL2C4 = 23
GL2A_PERF_SEL_REQ_BURST_GL2C5 = 24
GL2A_PERF_SEL_REQ_BURST_GL2C6 = 25
GL2A_PERF_SEL_REQ_BURST_GL2C7 = 26
GL2A_PERF_SEL_REQ_STALL_GL2C0 = 27
GL2A_PERF_SEL_REQ_STALL_GL2C1 = 28
GL2A_PERF_SEL_REQ_STALL_GL2C2 = 29
GL2A_PERF_SEL_REQ_STALL_GL2C3 = 30
GL2A_PERF_SEL_REQ_STALL_GL2C4 = 31
GL2A_PERF_SEL_REQ_STALL_GL2C5 = 32
GL2A_PERF_SEL_REQ_STALL_GL2C6 = 33
GL2A_PERF_SEL_REQ_STALL_GL2C7 = 34
GL2A_PERF_SEL_RTN_STALL_GL2C0 = 35
GL2A_PERF_SEL_RTN_STALL_GL2C1 = 36
GL2A_PERF_SEL_RTN_STALL_GL2C2 = 37
GL2A_PERF_SEL_RTN_STALL_GL2C3 = 38
GL2A_PERF_SEL_RTN_STALL_GL2C4 = 39
GL2A_PERF_SEL_RTN_STALL_GL2C5 = 40
GL2A_PERF_SEL_RTN_STALL_GL2C6 = 41
GL2A_PERF_SEL_RTN_STALL_GL2C7 = 42
GL2A_PERF_SEL_RTN_CLIENT0 = 43
GL2A_PERF_SEL_RTN_CLIENT1 = 44
GL2A_PERF_SEL_RTN_CLIENT2 = 45
GL2A_PERF_SEL_RTN_CLIENT3 = 46
GL2A_PERF_SEL_RTN_CLIENT4 = 47
GL2A_PERF_SEL_RTN_CLIENT5 = 48
GL2A_PERF_SEL_RTN_CLIENT6 = 49
GL2A_PERF_SEL_RTN_CLIENT7 = 50
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 51
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 52
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 53
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 54
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 55
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 56
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 57
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 58
GL2A_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_PERF_SEL'
GRBM_PERF_SEL__enumvalues = {
0: 'GRBM_PERF_SEL_COUNT',
1: 'GRBM_PERF_SEL_USER_DEFINED',
2: 'GRBM_PERF_SEL_GUI_ACTIVE',
3: 'GRBM_PERF_SEL_CP_BUSY',
4: 'GRBM_PERF_SEL_CP_COHER_BUSY',
5: 'GRBM_PERF_SEL_CP_DMA_BUSY',
6: 'GRBM_PERF_SEL_CB_BUSY',
7: 'GRBM_PERF_SEL_DB_BUSY',
8: 'GRBM_PERF_SEL_PA_BUSY',
9: 'GRBM_PERF_SEL_SC_BUSY',
10: 'GRBM_PERF_SEL_RESERVED_6',
11: 'GRBM_PERF_SEL_SPI_BUSY',
12: 'GRBM_PERF_SEL_SX_BUSY',
13: 'GRBM_PERF_SEL_TA_BUSY',
14: 'GRBM_PERF_SEL_CB_CLEAN',
15: 'GRBM_PERF_SEL_DB_CLEAN',
16: 'GRBM_PERF_SEL_RESERVED_5',
17: 'GRBM_PERF_SEL_RESERVED_9',
18: 'GRBM_PERF_SEL_RESERVED_4',
19: 'GRBM_PERF_SEL_RESERVED_3',
20: 'GRBM_PERF_SEL_RESERVED_2',
21: 'GRBM_PERF_SEL_RESERVED_1',
22: 'GRBM_PERF_SEL_RESERVED_0',
23: 'GRBM_PERF_SEL_RESERVED_8',
24: 'GRBM_PERF_SEL_RESERVED_7',
25: 'GRBM_PERF_SEL_GDS_BUSY',
26: 'GRBM_PERF_SEL_BCI_BUSY',
27: 'GRBM_PERF_SEL_RLC_BUSY',
28: 'GRBM_PERF_SEL_TCP_BUSY',
29: 'GRBM_PERF_SEL_CPG_BUSY',
30: 'GRBM_PERF_SEL_CPC_BUSY',
31: 'GRBM_PERF_SEL_CPF_BUSY',
32: 'GRBM_PERF_SEL_GE_BUSY',
33: 'GRBM_PERF_SEL_GE_NO_DMA_BUSY',
34: 'GRBM_PERF_SEL_UTCL2_BUSY',
35: 'GRBM_PERF_SEL_EA_BUSY',
36: 'GRBM_PERF_SEL_RMI_BUSY',
37: 'GRBM_PERF_SEL_CPAXI_BUSY',
39: 'GRBM_PERF_SEL_UTCL1_BUSY',
40: 'GRBM_PERF_SEL_GL2CC_BUSY',
41: 'GRBM_PERF_SEL_SDMA_BUSY',
42: 'GRBM_PERF_SEL_CH_BUSY',
43: 'GRBM_PERF_SEL_PH_BUSY',
44: 'GRBM_PERF_SEL_PMM_BUSY',
45: 'GRBM_PERF_SEL_GUS_BUSY',
46: 'GRBM_PERF_SEL_GL1CC_BUSY',
}
GRBM_PERF_SEL_COUNT = 0
GRBM_PERF_SEL_USER_DEFINED = 1
GRBM_PERF_SEL_GUI_ACTIVE = 2
GRBM_PERF_SEL_CP_BUSY = 3
GRBM_PERF_SEL_CP_COHER_BUSY = 4
GRBM_PERF_SEL_CP_DMA_BUSY = 5
GRBM_PERF_SEL_CB_BUSY = 6
GRBM_PERF_SEL_DB_BUSY = 7
GRBM_PERF_SEL_PA_BUSY = 8
GRBM_PERF_SEL_SC_BUSY = 9
GRBM_PERF_SEL_RESERVED_6 = 10
GRBM_PERF_SEL_SPI_BUSY = 11
GRBM_PERF_SEL_SX_BUSY = 12
GRBM_PERF_SEL_TA_BUSY = 13
GRBM_PERF_SEL_CB_CLEAN = 14
GRBM_PERF_SEL_DB_CLEAN = 15
GRBM_PERF_SEL_RESERVED_5 = 16
GRBM_PERF_SEL_RESERVED_9 = 17
GRBM_PERF_SEL_RESERVED_4 = 18
GRBM_PERF_SEL_RESERVED_3 = 19
GRBM_PERF_SEL_RESERVED_2 = 20
GRBM_PERF_SEL_RESERVED_1 = 21
GRBM_PERF_SEL_RESERVED_0 = 22
GRBM_PERF_SEL_RESERVED_8 = 23
GRBM_PERF_SEL_RESERVED_7 = 24
GRBM_PERF_SEL_GDS_BUSY = 25
GRBM_PERF_SEL_BCI_BUSY = 26
GRBM_PERF_SEL_RLC_BUSY = 27
GRBM_PERF_SEL_TCP_BUSY = 28
GRBM_PERF_SEL_CPG_BUSY = 29
GRBM_PERF_SEL_CPC_BUSY = 30
GRBM_PERF_SEL_CPF_BUSY = 31
GRBM_PERF_SEL_GE_BUSY = 32
GRBM_PERF_SEL_GE_NO_DMA_BUSY = 33
GRBM_PERF_SEL_UTCL2_BUSY = 34
GRBM_PERF_SEL_EA_BUSY = 35
GRBM_PERF_SEL_RMI_BUSY = 36
GRBM_PERF_SEL_CPAXI_BUSY = 37
GRBM_PERF_SEL_UTCL1_BUSY = 39
GRBM_PERF_SEL_GL2CC_BUSY = 40
GRBM_PERF_SEL_SDMA_BUSY = 41
GRBM_PERF_SEL_CH_BUSY = 42
GRBM_PERF_SEL_PH_BUSY = 43
GRBM_PERF_SEL_PMM_BUSY = 44
GRBM_PERF_SEL_GUS_BUSY = 45
GRBM_PERF_SEL_GL1CC_BUSY = 46
GRBM_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_SE0_PERF_SEL'
GRBM_SE0_PERF_SEL__enumvalues = {
0: 'GRBM_SE0_PERF_SEL_COUNT',
1: 'GRBM_SE0_PERF_SEL_USER_DEFINED',
2: 'GRBM_SE0_PERF_SEL_CB_BUSY',
3: 'GRBM_SE0_PERF_SEL_DB_BUSY',
4: 'GRBM_SE0_PERF_SEL_SC_BUSY',
5: 'GRBM_SE0_PERF_SEL_RESERVED_1',
6: 'GRBM_SE0_PERF_SEL_SPI_BUSY',
7: 'GRBM_SE0_PERF_SEL_SX_BUSY',
8: 'GRBM_SE0_PERF_SEL_TA_BUSY',
9: 'GRBM_SE0_PERF_SEL_CB_CLEAN',
10: 'GRBM_SE0_PERF_SEL_DB_CLEAN',
11: 'GRBM_SE0_PERF_SEL_RESERVED_0',
12: 'GRBM_SE0_PERF_SEL_PA_BUSY',
13: 'GRBM_SE0_PERF_SEL_RESERVED_2',
14: 'GRBM_SE0_PERF_SEL_BCI_BUSY',
15: 'GRBM_SE0_PERF_SEL_RMI_BUSY',
16: 'GRBM_SE0_PERF_SEL_UTCL1_BUSY',
17: 'GRBM_SE0_PERF_SEL_TCP_BUSY',
18: 'GRBM_SE0_PERF_SEL_GL1CC_BUSY',
}
GRBM_SE0_PERF_SEL_COUNT = 0
GRBM_SE0_PERF_SEL_USER_DEFINED = 1
GRBM_SE0_PERF_SEL_CB_BUSY = 2
GRBM_SE0_PERF_SEL_DB_BUSY = 3
GRBM_SE0_PERF_SEL_SC_BUSY = 4
GRBM_SE0_PERF_SEL_RESERVED_1 = 5
GRBM_SE0_PERF_SEL_SPI_BUSY = 6
GRBM_SE0_PERF_SEL_SX_BUSY = 7
GRBM_SE0_PERF_SEL_TA_BUSY = 8
GRBM_SE0_PERF_SEL_CB_CLEAN = 9
GRBM_SE0_PERF_SEL_DB_CLEAN = 10
GRBM_SE0_PERF_SEL_RESERVED_0 = 11
GRBM_SE0_PERF_SEL_PA_BUSY = 12
GRBM_SE0_PERF_SEL_RESERVED_2 = 13
GRBM_SE0_PERF_SEL_BCI_BUSY = 14
GRBM_SE0_PERF_SEL_RMI_BUSY = 15
GRBM_SE0_PERF_SEL_UTCL1_BUSY = 16
GRBM_SE0_PERF_SEL_TCP_BUSY = 17
GRBM_SE0_PERF_SEL_GL1CC_BUSY = 18
GRBM_SE0_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_SE1_PERF_SEL'
GRBM_SE1_PERF_SEL__enumvalues = {
0: 'GRBM_SE1_PERF_SEL_COUNT',
1: 'GRBM_SE1_PERF_SEL_USER_DEFINED',
2: 'GRBM_SE1_PERF_SEL_CB_BUSY',
3: 'GRBM_SE1_PERF_SEL_DB_BUSY',
4: 'GRBM_SE1_PERF_SEL_SC_BUSY',
5: 'GRBM_SE1_PERF_SEL_RESERVED_1',
6: 'GRBM_SE1_PERF_SEL_SPI_BUSY',
7: 'GRBM_SE1_PERF_SEL_SX_BUSY',
8: 'GRBM_SE1_PERF_SEL_TA_BUSY',
9: 'GRBM_SE1_PERF_SEL_CB_CLEAN',
10: 'GRBM_SE1_PERF_SEL_DB_CLEAN',
11: 'GRBM_SE1_PERF_SEL_RESERVED_0',
12: 'GRBM_SE1_PERF_SEL_PA_BUSY',
13: 'GRBM_SE1_PERF_SEL_RESERVED_2',
14: 'GRBM_SE1_PERF_SEL_BCI_BUSY',
15: 'GRBM_SE1_PERF_SEL_RMI_BUSY',
16: 'GRBM_SE1_PERF_SEL_UTCL1_BUSY',
17: 'GRBM_SE1_PERF_SEL_TCP_BUSY',
18: 'GRBM_SE1_PERF_SEL_GL1CC_BUSY',
}
GRBM_SE1_PERF_SEL_COUNT = 0
GRBM_SE1_PERF_SEL_USER_DEFINED = 1
GRBM_SE1_PERF_SEL_CB_BUSY = 2
GRBM_SE1_PERF_SEL_DB_BUSY = 3
GRBM_SE1_PERF_SEL_SC_BUSY = 4
GRBM_SE1_PERF_SEL_RESERVED_1 = 5
GRBM_SE1_PERF_SEL_SPI_BUSY = 6
GRBM_SE1_PERF_SEL_SX_BUSY = 7
GRBM_SE1_PERF_SEL_TA_BUSY = 8
GRBM_SE1_PERF_SEL_CB_CLEAN = 9
GRBM_SE1_PERF_SEL_DB_CLEAN = 10
GRBM_SE1_PERF_SEL_RESERVED_0 = 11
GRBM_SE1_PERF_SEL_PA_BUSY = 12
GRBM_SE1_PERF_SEL_RESERVED_2 = 13
GRBM_SE1_PERF_SEL_BCI_BUSY = 14
GRBM_SE1_PERF_SEL_RMI_BUSY = 15
GRBM_SE1_PERF_SEL_UTCL1_BUSY = 16
GRBM_SE1_PERF_SEL_TCP_BUSY = 17
GRBM_SE1_PERF_SEL_GL1CC_BUSY = 18
GRBM_SE1_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_SE2_PERF_SEL'
GRBM_SE2_PERF_SEL__enumvalues = {
0: 'GRBM_SE2_PERF_SEL_COUNT',
1: 'GRBM_SE2_PERF_SEL_USER_DEFINED',
2: 'GRBM_SE2_PERF_SEL_CB_BUSY',
3: 'GRBM_SE2_PERF_SEL_DB_BUSY',
4: 'GRBM_SE2_PERF_SEL_SC_BUSY',
5: 'GRBM_SE2_PERF_SEL_RESERVED_1',
6: 'GRBM_SE2_PERF_SEL_SPI_BUSY',
7: 'GRBM_SE2_PERF_SEL_SX_BUSY',
8: 'GRBM_SE2_PERF_SEL_TA_BUSY',
9: 'GRBM_SE2_PERF_SEL_CB_CLEAN',
10: 'GRBM_SE2_PERF_SEL_DB_CLEAN',
11: 'GRBM_SE2_PERF_SEL_RESERVED_0',
12: 'GRBM_SE2_PERF_SEL_PA_BUSY',
13: 'GRBM_SE2_PERF_SEL_RESERVED_2',
14: 'GRBM_SE2_PERF_SEL_BCI_BUSY',
15: 'GRBM_SE2_PERF_SEL_RMI_BUSY',
16: 'GRBM_SE2_PERF_SEL_UTCL1_BUSY',
17: 'GRBM_SE2_PERF_SEL_TCP_BUSY',
18: 'GRBM_SE2_PERF_SEL_GL1CC_BUSY',
}
GRBM_SE2_PERF_SEL_COUNT = 0
GRBM_SE2_PERF_SEL_USER_DEFINED = 1
GRBM_SE2_PERF_SEL_CB_BUSY = 2
GRBM_SE2_PERF_SEL_DB_BUSY = 3
GRBM_SE2_PERF_SEL_SC_BUSY = 4
GRBM_SE2_PERF_SEL_RESERVED_1 = 5
GRBM_SE2_PERF_SEL_SPI_BUSY = 6
GRBM_SE2_PERF_SEL_SX_BUSY = 7
GRBM_SE2_PERF_SEL_TA_BUSY = 8
GRBM_SE2_PERF_SEL_CB_CLEAN = 9
GRBM_SE2_PERF_SEL_DB_CLEAN = 10
GRBM_SE2_PERF_SEL_RESERVED_0 = 11
GRBM_SE2_PERF_SEL_PA_BUSY = 12
GRBM_SE2_PERF_SEL_RESERVED_2 = 13
GRBM_SE2_PERF_SEL_BCI_BUSY = 14
GRBM_SE2_PERF_SEL_RMI_BUSY = 15
GRBM_SE2_PERF_SEL_UTCL1_BUSY = 16
GRBM_SE2_PERF_SEL_TCP_BUSY = 17
GRBM_SE2_PERF_SEL_GL1CC_BUSY = 18
GRBM_SE2_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_SE3_PERF_SEL'
GRBM_SE3_PERF_SEL__enumvalues = {
0: 'GRBM_SE3_PERF_SEL_COUNT',
1: 'GRBM_SE3_PERF_SEL_USER_DEFINED',
2: 'GRBM_SE3_PERF_SEL_CB_BUSY',
3: 'GRBM_SE3_PERF_SEL_DB_BUSY',
4: 'GRBM_SE3_PERF_SEL_SC_BUSY',
5: 'GRBM_SE3_PERF_SEL_RESERVED_1',
6: 'GRBM_SE3_PERF_SEL_SPI_BUSY',
7: 'GRBM_SE3_PERF_SEL_SX_BUSY',
8: 'GRBM_SE3_PERF_SEL_TA_BUSY',
9: 'GRBM_SE3_PERF_SEL_CB_CLEAN',
10: 'GRBM_SE3_PERF_SEL_DB_CLEAN',
11: 'GRBM_SE3_PERF_SEL_RESERVED_0',
12: 'GRBM_SE3_PERF_SEL_PA_BUSY',
13: 'GRBM_SE3_PERF_SEL_RESERVED_2',
14: 'GRBM_SE3_PERF_SEL_BCI_BUSY',
15: 'GRBM_SE3_PERF_SEL_RMI_BUSY',
16: 'GRBM_SE3_PERF_SEL_UTCL1_BUSY',
17: 'GRBM_SE3_PERF_SEL_TCP_BUSY',
18: 'GRBM_SE3_PERF_SEL_GL1CC_BUSY',
}
GRBM_SE3_PERF_SEL_COUNT = 0
GRBM_SE3_PERF_SEL_USER_DEFINED = 1
GRBM_SE3_PERF_SEL_CB_BUSY = 2
GRBM_SE3_PERF_SEL_DB_BUSY = 3
GRBM_SE3_PERF_SEL_SC_BUSY = 4
GRBM_SE3_PERF_SEL_RESERVED_1 = 5
GRBM_SE3_PERF_SEL_SPI_BUSY = 6
GRBM_SE3_PERF_SEL_SX_BUSY = 7
GRBM_SE3_PERF_SEL_TA_BUSY = 8
GRBM_SE3_PERF_SEL_CB_CLEAN = 9
GRBM_SE3_PERF_SEL_DB_CLEAN = 10
GRBM_SE3_PERF_SEL_RESERVED_0 = 11
GRBM_SE3_PERF_SEL_PA_BUSY = 12
GRBM_SE3_PERF_SEL_RESERVED_2 = 13
GRBM_SE3_PERF_SEL_BCI_BUSY = 14
GRBM_SE3_PERF_SEL_RMI_BUSY = 15
GRBM_SE3_PERF_SEL_UTCL1_BUSY = 16
GRBM_SE3_PERF_SEL_TCP_BUSY = 17
GRBM_SE3_PERF_SEL_GL1CC_BUSY = 18
GRBM_SE3_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CP_RING_ID'
CP_RING_ID__enumvalues = {
0: 'RINGID0',
1: 'RINGID1',
2: 'RINGID2',
3: 'RINGID3',
}
RINGID0 = 0
RINGID1 = 1
RINGID2 = 2
RINGID3 = 3
CP_RING_ID = ctypes.c_uint32 # enum
# values for enumeration 'CP_PIPE_ID'
CP_PIPE_ID__enumvalues = {
0: 'PIPE_ID0',
1: 'PIPE_ID1',
2: 'PIPE_ID2',
3: 'PIPE_ID3',
}
PIPE_ID0 = 0
PIPE_ID1 = 1
PIPE_ID2 = 2
PIPE_ID3 = 3
CP_PIPE_ID = ctypes.c_uint32 # enum
# values for enumeration 'CP_ME_ID'
CP_ME_ID__enumvalues = {
0: 'ME_ID0',
1: 'ME_ID1',
2: 'ME_ID2',
3: 'ME_ID3',
}
ME_ID0 = 0
ME_ID1 = 1
ME_ID2 = 2
ME_ID3 = 3
CP_ME_ID = ctypes.c_uint32 # enum
# values for enumeration 'SPM_PERFMON_STATE'
SPM_PERFMON_STATE__enumvalues = {
0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET',
1: 'STRM_PERFMON_STATE_START_COUNTING',
2: 'STRM_PERFMON_STATE_STOP_COUNTING',
3: 'STRM_PERFMON_STATE_RESERVED_3',
4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM',
5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM',
}
STRM_PERFMON_STATE_DISABLE_AND_RESET = 0
STRM_PERFMON_STATE_START_COUNTING = 1
STRM_PERFMON_STATE_STOP_COUNTING = 2
STRM_PERFMON_STATE_RESERVED_3 = 3
STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4
STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5
SPM_PERFMON_STATE = ctypes.c_uint32 # enum
# values for enumeration 'CP_PERFMON_STATE'
CP_PERFMON_STATE__enumvalues = {
0: 'CP_PERFMON_STATE_DISABLE_AND_RESET',
1: 'CP_PERFMON_STATE_START_COUNTING',
2: 'CP_PERFMON_STATE_STOP_COUNTING',
3: 'CP_PERFMON_STATE_RESERVED_3',
4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM',
5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM',
}
CP_PERFMON_STATE_DISABLE_AND_RESET = 0
CP_PERFMON_STATE_START_COUNTING = 1
CP_PERFMON_STATE_STOP_COUNTING = 2
CP_PERFMON_STATE_RESERVED_3 = 3
CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4
CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5
CP_PERFMON_STATE = ctypes.c_uint32 # enum
# values for enumeration 'CP_PERFMON_ENABLE_MODE'
CP_PERFMON_ENABLE_MODE__enumvalues = {
0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT',
1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1',
2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE',
3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE',
}
CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0
CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1
CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2
CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3
CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CPG_PERFCOUNT_SEL'
CPG_PERFCOUNT_SEL__enumvalues = {
0: 'CPG_PERF_SEL_ALWAYS_COUNT',
1: 'CPG_PERF_SEL_RBIU_FIFO_FULL',
2: 'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR',
3: 'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL',
4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT',
5: 'CPG_PERF_SEL_ME_PARSER_BUSY',
6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS',
7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS',
8: 'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS',
9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS',
10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS',
11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS',
12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ',
13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ',
14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX',
15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS',
16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE',
17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM',
18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY',
19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY',
20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY',
21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ',
22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP',
23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ',
24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX',
25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU',
26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS',
27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH',
28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER',
29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER',
30: 'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS',
31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY',
32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID',
33: 'CPG_PERF_SEL_REGISTER_CLK_VALID',
34: 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT',
35: 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT',
36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP',
37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE',
38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO',
39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO',
40: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU',
41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ',
42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG',
43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER',
44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE',
45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS',
46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS',
48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION',
49: 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
50: 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT',
51: 'CPG_PERF_SEL_CPG_STAT_BUSY',
52: 'CPG_PERF_SEL_CPG_STAT_IDLE',
53: 'CPG_PERF_SEL_CPG_STAT_STALL',
54: 'CPG_PERF_SEL_CPG_TCIU_BUSY',
55: 'CPG_PERF_SEL_CPG_TCIU_IDLE',
56: 'CPF_PERF_SEL_CPG_TCIU_STALL',
57: 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY',
58: 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE',
59: 'CPG_PERF_SEL_CPG_UTCL2IU_STALL',
60: 'CPG_PERF_SEL_CPG_GCRIU_BUSY',
61: 'CPG_PERF_SEL_CPG_GCRIU_IDLE',
62: 'CPG_PERF_SEL_CPG_GCRIU_STALL',
63: 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
64: 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY',
65: 'CPG_PERF_SEL_CPG_UTCL2IU_XACK',
66: 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK',
67: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY',
68: 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT',
69: 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS',
70: 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT',
71: 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS',
72: 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT',
73: 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS',
74: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1',
75: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1',
76: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2',
77: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2',
}
CPG_PERF_SEL_ALWAYS_COUNT = 0
CPG_PERF_SEL_RBIU_FIFO_FULL = 1
CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 2
CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 3
CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4
CPG_PERF_SEL_ME_PARSER_BUSY = 5
CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6
CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7
CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 8
CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9
CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10
CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11
CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12
CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13
CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14
CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15
CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16
CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17
CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18
CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19
CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20
CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21
CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22
CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23
CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24
CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25
CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26
CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27
CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28
CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29
CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 30
CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31
CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32
CPG_PERF_SEL_REGISTER_CLK_VALID = 33
CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 34
CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 35
CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36
CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37
CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38
CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39
CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 40
CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41
CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42
CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43
CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44
CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45
CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46
CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47
CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48
CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 49
CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 50
CPG_PERF_SEL_CPG_STAT_BUSY = 51
CPG_PERF_SEL_CPG_STAT_IDLE = 52
CPG_PERF_SEL_CPG_STAT_STALL = 53
CPG_PERF_SEL_CPG_TCIU_BUSY = 54
CPG_PERF_SEL_CPG_TCIU_IDLE = 55
CPF_PERF_SEL_CPG_TCIU_STALL = 56
CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 57
CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 58
CPG_PERF_SEL_CPG_UTCL2IU_STALL = 59
CPG_PERF_SEL_CPG_GCRIU_BUSY = 60
CPG_PERF_SEL_CPG_GCRIU_IDLE = 61
CPG_PERF_SEL_CPG_GCRIU_STALL = 62
CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 63
CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 64
CPG_PERF_SEL_CPG_UTCL2IU_XACK = 65
CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 66
CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 67
CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 68
CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 69
CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 70
CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 71
CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 72
CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 73
CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 74
CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 75
CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 76
CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 77
CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPF_PERFCOUNT_SEL'
CPF_PERFCOUNT_SEL__enumvalues = {
0: 'CPF_PERF_SEL_ALWAYS_COUNT',
1: 'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE',
2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE',
3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS',
4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING',
5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1',
6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2',
7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE',
8: 'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS',
9: 'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR',
10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR',
11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS',
12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT',
13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID',
14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID',
15: 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SEND',
16: 'CPF_PERF_SEL_GUS_READ_REQUEST_SEND',
17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS',
19: 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION',
20: 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION',
21: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE',
22: 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
23: 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT',
24: 'CPF_PERF_SEL_CPF_STAT_BUSY',
25: 'CPF_PERF_SEL_CPF_STAT_IDLE',
26: 'CPF_PERF_SEL_CPF_STAT_STALL',
27: 'CPF_PERF_SEL_CPF_TCIU_BUSY',
28: 'CPF_PERF_SEL_CPF_TCIU_IDLE',
29: 'CPF_PERF_SEL_CPF_TCIU_STALL',
30: 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY',
31: 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE',
32: 'CPF_PERF_SEL_CPF_UTCL2IU_STALL',
33: 'CPF_PERF_SEL_CPF_GCRIU_BUSY',
34: 'CPF_PERF_SEL_CPF_GCRIU_IDLE',
35: 'CPF_PERF_SEL_CPF_GCRIU_STALL',
36: 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
37: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB',
38: 'CPF_PERF_SEL_CPF_UTCL2IU_XACK',
39: 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK',
}
CPF_PERF_SEL_ALWAYS_COUNT = 0
CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 1
CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2
CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6
CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 7
CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 8
CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 9
CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10
CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11
CPF_PERF_SEL_GRBM_DWORDS_SENT = 12
CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13
CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14
CPF_PERF_SEL_GUS_WRITE_REQUEST_SEND = 15
CPF_PERF_SEL_GUS_READ_REQUEST_SEND = 16
CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17
CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18
CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 19
CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 20
CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 21
CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 22
CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 23
CPF_PERF_SEL_CPF_STAT_BUSY = 24
CPF_PERF_SEL_CPF_STAT_IDLE = 25
CPF_PERF_SEL_CPF_STAT_STALL = 26
CPF_PERF_SEL_CPF_TCIU_BUSY = 27
CPF_PERF_SEL_CPF_TCIU_IDLE = 28
CPF_PERF_SEL_CPF_TCIU_STALL = 29
CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 30
CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 31
CPF_PERF_SEL_CPF_UTCL2IU_STALL = 32
CPF_PERF_SEL_CPF_GCRIU_BUSY = 33
CPF_PERF_SEL_CPF_GCRIU_IDLE = 34
CPF_PERF_SEL_CPF_GCRIU_STALL = 35
CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 36
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 37
CPF_PERF_SEL_CPF_UTCL2IU_XACK = 38
CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 39
CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPC_PERFCOUNT_SEL'
CPC_PERFCOUNT_SEL__enumvalues = {
0: 'CPC_PERF_SEL_ALWAYS_COUNT',
1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE',
2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION',
3: 'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE',
4: 'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE',
5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE',
6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY',
7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF',
8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ',
9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ',
10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE',
11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ',
12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF',
13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE',
14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY',
15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF',
16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ',
17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ',
18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE',
19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ',
20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF',
21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE',
22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS',
24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION',
25: 'CPC_PERF_SEL_CPC_STAT_BUSY',
26: 'CPC_PERF_SEL_CPC_STAT_IDLE',
27: 'CPC_PERF_SEL_CPC_STAT_STALL',
28: 'CPC_PERF_SEL_CPC_TCIU_BUSY',
29: 'CPC_PERF_SEL_CPC_TCIU_IDLE',
30: 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY',
31: 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE',
32: 'CPC_PERF_SEL_CPC_UTCL2IU_STALL',
33: 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY',
34: 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY',
35: 'CPC_PERF_SEL_CPC_GCRIU_BUSY',
36: 'CPC_PERF_SEL_CPC_GCRIU_IDLE',
37: 'CPC_PERF_SEL_CPC_GCRIU_STALL',
38: 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
39: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ',
40: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ',
41: 'CPC_PERF_SEL_CPC_UTCL2IU_XACK',
42: 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK',
43: 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT',
44: 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS',
}
CPC_PERF_SEL_ALWAYS_COUNT = 0
CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1
CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2
CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 3
CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 4
CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8
CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 9
CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 10
CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11
CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12
CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16
CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 17
CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 18
CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19
CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20
CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21
CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22
CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23
CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24
CPC_PERF_SEL_CPC_STAT_BUSY = 25
CPC_PERF_SEL_CPC_STAT_IDLE = 26
CPC_PERF_SEL_CPC_STAT_STALL = 27
CPC_PERF_SEL_CPC_TCIU_BUSY = 28
CPC_PERF_SEL_CPC_TCIU_IDLE = 29
CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 30
CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 31
CPC_PERF_SEL_CPC_UTCL2IU_STALL = 32
CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 33
CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 34
CPC_PERF_SEL_CPC_GCRIU_BUSY = 35
CPC_PERF_SEL_CPC_GCRIU_IDLE = 36
CPC_PERF_SEL_CPC_GCRIU_STALL = 37
CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 38
CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 39
CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 40
CPC_PERF_SEL_CPC_UTCL2IU_XACK = 41
CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 42
CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 43
CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 44
CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CP_ALPHA_TAG_RAM_SEL'
CP_ALPHA_TAG_RAM_SEL__enumvalues = {
0: 'CPG_TAG_RAM',
1: 'CPC_TAG_RAM',
2: 'CPF_TAG_RAM',
3: 'RSV_TAG_RAM',
}
CPG_TAG_RAM = 0
CPC_TAG_RAM = 1
CPF_TAG_RAM = 2
RSV_TAG_RAM = 3
CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPF_PERFCOUNTWINDOW_SEL'
CPF_PERFCOUNTWINDOW_SEL__enumvalues = {
0: 'CPF_PERFWINDOW_SEL_CSF',
1: 'CPF_PERFWINDOW_SEL_HQD1',
2: 'CPF_PERFWINDOW_SEL_HQD2',
3: 'CPF_PERFWINDOW_SEL_RDMA',
4: 'CPF_PERFWINDOW_SEL_RWPP',
}
CPF_PERFWINDOW_SEL_CSF = 0
CPF_PERFWINDOW_SEL_HQD1 = 1
CPF_PERFWINDOW_SEL_HQD2 = 2
CPF_PERFWINDOW_SEL_RDMA = 3
CPF_PERFWINDOW_SEL_RWPP = 4
CPF_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPG_PERFCOUNTWINDOW_SEL'
CPG_PERFCOUNTWINDOW_SEL__enumvalues = {
0: 'CPG_PERFWINDOW_SEL_PFP',
1: 'CPG_PERFWINDOW_SEL_ME',
2: 'CPG_PERFWINDOW_SEL_CE',
3: 'CPG_PERFWINDOW_SEL_MES',
4: 'CPG_PERFWINDOW_SEL_MEC1',
5: 'CPG_PERFWINDOW_SEL_MEC2',
6: 'CPG_PERFWINDOW_SEL_DFY',
7: 'CPG_PERFWINDOW_SEL_DMA',
8: 'CPG_PERFWINDOW_SEL_SHADOW',
9: 'CPG_PERFWINDOW_SEL_RB',
10: 'CPG_PERFWINDOW_SEL_CEDMA',
11: 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR',
12: 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR',
13: 'CPG_PERFWINDOW_SEL_PQ1',
14: 'CPG_PERFWINDOW_SEL_PQ2',
15: 'CPG_PERFWINDOW_SEL_PQ3',
16: 'CPG_PERFWINDOW_SEL_MEMWR',
17: 'CPG_PERFWINDOW_SEL_MEMRD',
18: 'CPG_PERFWINDOW_SEL_VGT0',
19: 'CPG_PERFWINDOW_SEL_VGT1',
20: 'CPG_PERFWINDOW_SEL_APPEND',
21: 'CPG_PERFWINDOW_SEL_QURD',
22: 'CPG_PERFWINDOW_SEL_DDID',
23: 'CPG_PERFWINDOW_SEL_SR',
24: 'CPG_PERFWINDOW_SEL_QU_EOP',
25: 'CPG_PERFWINDOW_SEL_QU_STRM',
26: 'CPG_PERFWINDOW_SEL_QU_PIPE',
27: 'CPG_PERFWINDOW_SEL_RESERVED1',
28: 'CPG_PERFWINDOW_SEL_CPC_IC',
29: 'CPG_PERFWINDOW_SEL_RESERVED2',
30: 'CPG_PERFWINDOW_SEL_CPG_IC',
}
CPG_PERFWINDOW_SEL_PFP = 0
CPG_PERFWINDOW_SEL_ME = 1
CPG_PERFWINDOW_SEL_CE = 2
CPG_PERFWINDOW_SEL_MES = 3
CPG_PERFWINDOW_SEL_MEC1 = 4
CPG_PERFWINDOW_SEL_MEC2 = 5
CPG_PERFWINDOW_SEL_DFY = 6
CPG_PERFWINDOW_SEL_DMA = 7
CPG_PERFWINDOW_SEL_SHADOW = 8
CPG_PERFWINDOW_SEL_RB = 9
CPG_PERFWINDOW_SEL_CEDMA = 10
CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 11
CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 12
CPG_PERFWINDOW_SEL_PQ1 = 13
CPG_PERFWINDOW_SEL_PQ2 = 14
CPG_PERFWINDOW_SEL_PQ3 = 15
CPG_PERFWINDOW_SEL_MEMWR = 16
CPG_PERFWINDOW_SEL_MEMRD = 17
CPG_PERFWINDOW_SEL_VGT0 = 18
CPG_PERFWINDOW_SEL_VGT1 = 19
CPG_PERFWINDOW_SEL_APPEND = 20
CPG_PERFWINDOW_SEL_QURD = 21
CPG_PERFWINDOW_SEL_DDID = 22
CPG_PERFWINDOW_SEL_SR = 23
CPG_PERFWINDOW_SEL_QU_EOP = 24
CPG_PERFWINDOW_SEL_QU_STRM = 25
CPG_PERFWINDOW_SEL_QU_PIPE = 26
CPG_PERFWINDOW_SEL_RESERVED1 = 27
CPG_PERFWINDOW_SEL_CPC_IC = 28
CPG_PERFWINDOW_SEL_RESERVED2 = 29
CPG_PERFWINDOW_SEL_CPG_IC = 30
CPG_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPF_LATENCY_STATS_SEL'
CPF_LATENCY_STATS_SEL__enumvalues = {
0: 'CPF_LATENCY_STATS_SEL_XACK_MAX',
1: 'CPF_LATENCY_STATS_SEL_XACK_MIN',
2: 'CPF_LATENCY_STATS_SEL_XACK_LAST',
3: 'CPF_LATENCY_STATS_SEL_XNACK_MAX',
4: 'CPF_LATENCY_STATS_SEL_XNACK_MIN',
5: 'CPF_LATENCY_STATS_SEL_XNACK_LAST',
6: 'CPF_LATENCY_STATS_SEL_READ_MAX',
7: 'CPF_LATENCY_STATS_SEL_READ_MIN',
8: 'CPF_LATENCY_STATS_SEL_READ_LAST',
9: 'CPF_LATENCY_STATS_SEL_INVAL_MAX',
10: 'CPF_LATENCY_STATS_SEL_INVAL_MIN',
11: 'CPF_LATENCY_STATS_SEL_INVAL_LAST',
}
CPF_LATENCY_STATS_SEL_XACK_MAX = 0
CPF_LATENCY_STATS_SEL_XACK_MIN = 1
CPF_LATENCY_STATS_SEL_XACK_LAST = 2
CPF_LATENCY_STATS_SEL_XNACK_MAX = 3
CPF_LATENCY_STATS_SEL_XNACK_MIN = 4
CPF_LATENCY_STATS_SEL_XNACK_LAST = 5
CPF_LATENCY_STATS_SEL_READ_MAX = 6
CPF_LATENCY_STATS_SEL_READ_MIN = 7
CPF_LATENCY_STATS_SEL_READ_LAST = 8
CPF_LATENCY_STATS_SEL_INVAL_MAX = 9
CPF_LATENCY_STATS_SEL_INVAL_MIN = 10
CPF_LATENCY_STATS_SEL_INVAL_LAST = 11
CPF_LATENCY_STATS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPG_LATENCY_STATS_SEL'
CPG_LATENCY_STATS_SEL__enumvalues = {
0: 'CPG_LATENCY_STATS_SEL_XACK_MAX',
1: 'CPG_LATENCY_STATS_SEL_XACK_MIN',
2: 'CPG_LATENCY_STATS_SEL_XACK_LAST',
3: 'CPG_LATENCY_STATS_SEL_XNACK_MAX',
4: 'CPG_LATENCY_STATS_SEL_XNACK_MIN',
5: 'CPG_LATENCY_STATS_SEL_XNACK_LAST',
6: 'CPG_LATENCY_STATS_SEL_WRITE_MAX',
7: 'CPG_LATENCY_STATS_SEL_WRITE_MIN',
8: 'CPG_LATENCY_STATS_SEL_WRITE_LAST',
9: 'CPG_LATENCY_STATS_SEL_READ_MAX',
10: 'CPG_LATENCY_STATS_SEL_READ_MIN',
11: 'CPG_LATENCY_STATS_SEL_READ_LAST',
12: 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX',
13: 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN',
14: 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST',
15: 'CPG_LATENCY_STATS_SEL_INVAL_MAX',
16: 'CPG_LATENCY_STATS_SEL_INVAL_MIN',
17: 'CPG_LATENCY_STATS_SEL_INVAL_LAST',
}
CPG_LATENCY_STATS_SEL_XACK_MAX = 0
CPG_LATENCY_STATS_SEL_XACK_MIN = 1
CPG_LATENCY_STATS_SEL_XACK_LAST = 2
CPG_LATENCY_STATS_SEL_XNACK_MAX = 3
CPG_LATENCY_STATS_SEL_XNACK_MIN = 4
CPG_LATENCY_STATS_SEL_XNACK_LAST = 5
CPG_LATENCY_STATS_SEL_WRITE_MAX = 6
CPG_LATENCY_STATS_SEL_WRITE_MIN = 7
CPG_LATENCY_STATS_SEL_WRITE_LAST = 8
CPG_LATENCY_STATS_SEL_READ_MAX = 9
CPG_LATENCY_STATS_SEL_READ_MIN = 10
CPG_LATENCY_STATS_SEL_READ_LAST = 11
CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 12
CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 13
CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 14
CPG_LATENCY_STATS_SEL_INVAL_MAX = 15
CPG_LATENCY_STATS_SEL_INVAL_MIN = 16
CPG_LATENCY_STATS_SEL_INVAL_LAST = 17
CPG_LATENCY_STATS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPC_LATENCY_STATS_SEL'
CPC_LATENCY_STATS_SEL__enumvalues = {
0: 'CPC_LATENCY_STATS_SEL_XACK_MAX',
1: 'CPC_LATENCY_STATS_SEL_XACK_MIN',
2: 'CPC_LATENCY_STATS_SEL_XACK_LAST',
3: 'CPC_LATENCY_STATS_SEL_XNACK_MAX',
4: 'CPC_LATENCY_STATS_SEL_XNACK_MIN',
5: 'CPC_LATENCY_STATS_SEL_XNACK_LAST',
6: 'CPC_LATENCY_STATS_SEL_INVAL_MAX',
7: 'CPC_LATENCY_STATS_SEL_INVAL_MIN',
8: 'CPC_LATENCY_STATS_SEL_INVAL_LAST',
}
CPC_LATENCY_STATS_SEL_XACK_MAX = 0
CPC_LATENCY_STATS_SEL_XACK_MIN = 1
CPC_LATENCY_STATS_SEL_XACK_LAST = 2
CPC_LATENCY_STATS_SEL_XNACK_MAX = 3
CPC_LATENCY_STATS_SEL_XNACK_MIN = 4
CPC_LATENCY_STATS_SEL_XNACK_LAST = 5
CPC_LATENCY_STATS_SEL_INVAL_MAX = 6
CPC_LATENCY_STATS_SEL_INVAL_MIN = 7
CPC_LATENCY_STATS_SEL_INVAL_LAST = 8
CPC_LATENCY_STATS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CP_DDID_CNTL_MODE'
CP_DDID_CNTL_MODE__enumvalues = {
0: 'STALL',
1: 'OVERRUN',
}
STALL = 0
OVERRUN = 1
CP_DDID_CNTL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CP_DDID_CNTL_SIZE'
CP_DDID_CNTL_SIZE__enumvalues = {
0: 'SIZE_8K',
1: 'SIZE_16K',
}
SIZE_8K = 0
SIZE_16K = 1
CP_DDID_CNTL_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'CP_DDID_CNTL_VMID_SEL'
CP_DDID_CNTL_VMID_SEL__enumvalues = {
0: 'DDID_VMID_PIPE',
1: 'DDID_VMID_CNTL',
}
DDID_VMID_PIPE = 0
DDID_VMID_CNTL = 1
CP_DDID_CNTL_VMID_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SX_BLEND_OPT'
SX_BLEND_OPT__enumvalues = {
0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL',
1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE',
2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0',
3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1',
4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0',
5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1',
6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0',
7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE',
}
BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0
BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1
BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2
BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3
BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4
BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5
BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6
BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7
SX_BLEND_OPT = ctypes.c_uint32 # enum
# values for enumeration 'SX_OPT_COMB_FCN'
SX_OPT_COMB_FCN__enumvalues = {
0: 'OPT_COMB_NONE',
1: 'OPT_COMB_ADD',
2: 'OPT_COMB_SUBTRACT',
3: 'OPT_COMB_MIN',
4: 'OPT_COMB_MAX',
5: 'OPT_COMB_REVSUBTRACT',
6: 'OPT_COMB_BLEND_DISABLED',
7: 'OPT_COMB_SAFE_ADD',
}
OPT_COMB_NONE = 0
OPT_COMB_ADD = 1
OPT_COMB_SUBTRACT = 2
OPT_COMB_MIN = 3
OPT_COMB_MAX = 4
OPT_COMB_REVSUBTRACT = 5
OPT_COMB_BLEND_DISABLED = 6
OPT_COMB_SAFE_ADD = 7
SX_OPT_COMB_FCN = ctypes.c_uint32 # enum
# values for enumeration 'SX_DOWNCONVERT_FORMAT'
SX_DOWNCONVERT_FORMAT__enumvalues = {
0: 'SX_RT_EXPORT_NO_CONVERSION',
1: 'SX_RT_EXPORT_32_R',
2: 'SX_RT_EXPORT_32_A',
3: 'SX_RT_EXPORT_10_11_11',
4: 'SX_RT_EXPORT_2_10_10_10',
5: 'SX_RT_EXPORT_8_8_8_8',
6: 'SX_RT_EXPORT_5_6_5',
7: 'SX_RT_EXPORT_1_5_5_5',
8: 'SX_RT_EXPORT_4_4_4_4',
9: 'SX_RT_EXPORT_16_16_GR',
10: 'SX_RT_EXPORT_16_16_AR',
}
SX_RT_EXPORT_NO_CONVERSION = 0
SX_RT_EXPORT_32_R = 1
SX_RT_EXPORT_32_A = 2
SX_RT_EXPORT_10_11_11 = 3
SX_RT_EXPORT_2_10_10_10 = 4
SX_RT_EXPORT_8_8_8_8 = 5
SX_RT_EXPORT_5_6_5 = 6
SX_RT_EXPORT_1_5_5_5 = 7
SX_RT_EXPORT_4_4_4_4 = 8
SX_RT_EXPORT_16_16_GR = 9
SX_RT_EXPORT_16_16_AR = 10
SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'SX_PERFCOUNTER_VALS'
SX_PERFCOUNTER_VALS__enumvalues = {
0: 'SX_PERF_SEL_PA_IDLE_CYCLES',
1: 'SX_PERF_SEL_PA_REQ',
2: 'SX_PERF_SEL_PA_POS',
3: 'SX_PERF_SEL_CLOCK',
4: 'SX_PERF_SEL_GATE_EN1',
5: 'SX_PERF_SEL_GATE_EN2',
6: 'SX_PERF_SEL_GATE_EN3',
7: 'SX_PERF_SEL_GATE_EN4',
8: 'SX_PERF_SEL_SH_POS_STARVE',
9: 'SX_PERF_SEL_SH_COLOR_STARVE',
10: 'SX_PERF_SEL_SH_POS_STALL',
11: 'SX_PERF_SEL_SH_COLOR_STALL',
12: 'SX_PERF_SEL_DB0_PIXELS',
13: 'SX_PERF_SEL_DB0_HALF_QUADS',
14: 'SX_PERF_SEL_DB0_PIXEL_STALL',
15: 'SX_PERF_SEL_DB0_PIXEL_IDLE',
16: 'SX_PERF_SEL_DB0_PRED_PIXELS',
17: 'SX_PERF_SEL_DB1_PIXELS',
18: 'SX_PERF_SEL_DB1_HALF_QUADS',
19: 'SX_PERF_SEL_DB1_PIXEL_STALL',
20: 'SX_PERF_SEL_DB1_PIXEL_IDLE',
21: 'SX_PERF_SEL_DB1_PRED_PIXELS',
22: 'SX_PERF_SEL_DB2_PIXELS',
23: 'SX_PERF_SEL_DB2_HALF_QUADS',
24: 'SX_PERF_SEL_DB2_PIXEL_STALL',
25: 'SX_PERF_SEL_DB2_PIXEL_IDLE',
26: 'SX_PERF_SEL_DB2_PRED_PIXELS',
27: 'SX_PERF_SEL_DB3_PIXELS',
28: 'SX_PERF_SEL_DB3_HALF_QUADS',
29: 'SX_PERF_SEL_DB3_PIXEL_STALL',
30: 'SX_PERF_SEL_DB3_PIXEL_IDLE',
31: 'SX_PERF_SEL_DB3_PRED_PIXELS',
32: 'SX_PERF_SEL_COL_BUSY',
33: 'SX_PERF_SEL_POS_BUSY',
34: 'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS',
35: 'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS',
36: 'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST',
37: 'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC',
38: 'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS',
39: 'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS',
40: 'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS',
41: 'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST',
42: 'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC',
43: 'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS',
44: 'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS',
45: 'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS',
46: 'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST',
47: 'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC',
48: 'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS',
49: 'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS',
50: 'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS',
51: 'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST',
52: 'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC',
53: 'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS',
54: 'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS',
55: 'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS',
56: 'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST',
57: 'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC',
58: 'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS',
59: 'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS',
60: 'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS',
61: 'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST',
62: 'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC',
63: 'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS',
64: 'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS',
65: 'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS',
66: 'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST',
67: 'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC',
68: 'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS',
69: 'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS',
70: 'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS',
71: 'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST',
72: 'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC',
73: 'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS',
74: 'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS',
75: 'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS',
76: 'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS',
77: 'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST',
78: 'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC',
79: 'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS',
80: 'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS',
81: 'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS',
82: 'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST',
83: 'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC',
84: 'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS',
85: 'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS',
86: 'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS',
87: 'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST',
88: 'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC',
89: 'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS',
90: 'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS',
91: 'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS',
92: 'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST',
93: 'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC',
94: 'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS',
95: 'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS',
96: 'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS',
97: 'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST',
98: 'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC',
99: 'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS',
100: 'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS',
101: 'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS',
102: 'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST',
103: 'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC',
104: 'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS',
105: 'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS',
106: 'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS',
107: 'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST',
108: 'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC',
109: 'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS',
110: 'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS',
111: 'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS',
112: 'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST',
113: 'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC',
114: 'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS',
115: 'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS',
116: 'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS',
117: 'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS',
118: 'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST',
119: 'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC',
120: 'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS',
121: 'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS',
122: 'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS',
123: 'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST',
124: 'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC',
125: 'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS',
126: 'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS',
127: 'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS',
128: 'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST',
129: 'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC',
130: 'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS',
131: 'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS',
132: 'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS',
133: 'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST',
134: 'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC',
135: 'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS',
136: 'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS',
137: 'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS',
138: 'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST',
139: 'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC',
140: 'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS',
141: 'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS',
142: 'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS',
143: 'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST',
144: 'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC',
145: 'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS',
146: 'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS',
147: 'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS',
148: 'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST',
149: 'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC',
150: 'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS',
151: 'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS',
152: 'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS',
153: 'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST',
154: 'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC',
155: 'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS',
156: 'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS',
157: 'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS',
158: 'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS',
159: 'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST',
160: 'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC',
161: 'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS',
162: 'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS',
163: 'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS',
164: 'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST',
165: 'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC',
166: 'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS',
167: 'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS',
168: 'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS',
169: 'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST',
170: 'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC',
171: 'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS',
172: 'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS',
173: 'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS',
174: 'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST',
175: 'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC',
176: 'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS',
177: 'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS',
178: 'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS',
179: 'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST',
180: 'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC',
181: 'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS',
182: 'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS',
183: 'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS',
184: 'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST',
185: 'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC',
186: 'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS',
187: 'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS',
188: 'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS',
189: 'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST',
190: 'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC',
191: 'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS',
192: 'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS',
193: 'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS',
194: 'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST',
195: 'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC',
196: 'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS',
197: 'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS',
198: 'SX_PERF_SEL_PA_REQ_LATENCY',
199: 'SX_PERF_SEL_POS_SCBD_STALL',
200: 'SX_PERF_SEL_COL_SCBD_STALL',
201: 'SX_PERF_SEL_CLOCK_DROP_STALL',
202: 'SX_PERF_SEL_GATE_EN5',
203: 'SX_PERF_SEL_GATE_EN6',
204: 'SX_PERF_SEL_DB0_SIZE',
205: 'SX_PERF_SEL_DB1_SIZE',
206: 'SX_PERF_SEL_DB2_SIZE',
207: 'SX_PERF_SEL_DB3_SIZE',
208: 'SX_PERF_SEL_SPLITMODE',
209: 'SX_PERF_SEL_COL_SCBD0_STALL',
210: 'SX_PERF_SEL_COL_SCBD1_STALL',
211: 'SX_PERF_SEL_IDX_STALL_CYCLES',
212: 'SX_PERF_SEL_IDX_IDLE_CYCLES',
213: 'SX_PERF_SEL_IDX_REQ',
214: 'SX_PERF_SEL_IDX_RET',
215: 'SX_PERF_SEL_IDX_REQ_LATENCY',
216: 'SX_PERF_SEL_IDX_SCBD_STALL',
217: 'SX_PERF_SEL_GATE_EN7',
218: 'SX_PERF_SEL_GATE_EN8',
219: 'SX_PERF_SEL_SH_IDX_STARVE',
220: 'SX_PERF_SEL_IDX_BUSY',
}
SX_PERF_SEL_PA_IDLE_CYCLES = 0
SX_PERF_SEL_PA_REQ = 1
SX_PERF_SEL_PA_POS = 2
SX_PERF_SEL_CLOCK = 3
SX_PERF_SEL_GATE_EN1 = 4
SX_PERF_SEL_GATE_EN2 = 5
SX_PERF_SEL_GATE_EN3 = 6
SX_PERF_SEL_GATE_EN4 = 7
SX_PERF_SEL_SH_POS_STARVE = 8
SX_PERF_SEL_SH_COLOR_STARVE = 9
SX_PERF_SEL_SH_POS_STALL = 10
SX_PERF_SEL_SH_COLOR_STALL = 11
SX_PERF_SEL_DB0_PIXELS = 12
SX_PERF_SEL_DB0_HALF_QUADS = 13
SX_PERF_SEL_DB0_PIXEL_STALL = 14
SX_PERF_SEL_DB0_PIXEL_IDLE = 15
SX_PERF_SEL_DB0_PRED_PIXELS = 16
SX_PERF_SEL_DB1_PIXELS = 17
SX_PERF_SEL_DB1_HALF_QUADS = 18
SX_PERF_SEL_DB1_PIXEL_STALL = 19
SX_PERF_SEL_DB1_PIXEL_IDLE = 20
SX_PERF_SEL_DB1_PRED_PIXELS = 21
SX_PERF_SEL_DB2_PIXELS = 22
SX_PERF_SEL_DB2_HALF_QUADS = 23
SX_PERF_SEL_DB2_PIXEL_STALL = 24
SX_PERF_SEL_DB2_PIXEL_IDLE = 25
SX_PERF_SEL_DB2_PRED_PIXELS = 26
SX_PERF_SEL_DB3_PIXELS = 27
SX_PERF_SEL_DB3_HALF_QUADS = 28
SX_PERF_SEL_DB3_PIXEL_STALL = 29
SX_PERF_SEL_DB3_PIXEL_IDLE = 30
SX_PERF_SEL_DB3_PRED_PIXELS = 31
SX_PERF_SEL_COL_BUSY = 32
SX_PERF_SEL_POS_BUSY = 33
SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 34
SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 35
SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 36
SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 37
SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 38
SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 39
SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 40
SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 41
SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 42
SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 43
SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 44
SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 45
SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 46
SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 47
SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 48
SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 49
SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 50
SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 51
SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 52
SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 53
SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 54
SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 55
SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 56
SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 57
SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 58
SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 59
SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 60
SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 61
SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 62
SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 63
SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 64
SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 65
SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 66
SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 67
SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 68
SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 69
SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 70
SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 71
SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 72
SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 73
SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 74
SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 75
SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 76
SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 77
SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 78
SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 79
SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 80
SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 81
SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 82
SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 83
SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 84
SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 85
SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 86
SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 87
SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 88
SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 89
SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 90
SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 91
SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 92
SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 93
SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 94
SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 95
SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 96
SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 97
SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 98
SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 99
SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 100
SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 101
SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 102
SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 103
SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 104
SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 105
SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 106
SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 107
SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 108
SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 109
SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 110
SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 111
SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 112
SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 113
SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 114
SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 115
SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 116
SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 117
SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 118
SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 119
SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 120
SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 121
SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 122
SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 123
SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 124
SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 125
SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 126
SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 127
SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 128
SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 129
SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 130
SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 131
SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 132
SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 133
SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 134
SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 135
SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 136
SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 137
SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 138
SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 139
SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 140
SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 141
SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 142
SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 143
SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 144
SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 145
SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 146
SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 147
SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 148
SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 149
SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 150
SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 151
SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 152
SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 153
SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 154
SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 155
SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 156
SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 157
SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 158
SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 159
SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 160
SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 161
SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 162
SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 163
SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 164
SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 165
SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 166
SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 167
SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 168
SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 169
SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 170
SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 171
SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 172
SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 173
SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 174
SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 175
SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 176
SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 177
SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 178
SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 179
SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 180
SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 181
SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 182
SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 183
SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 184
SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 185
SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 186
SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 187
SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 188
SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 189
SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 190
SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 191
SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 192
SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 193
SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 194
SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 195
SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 196
SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 197
SX_PERF_SEL_PA_REQ_LATENCY = 198
SX_PERF_SEL_POS_SCBD_STALL = 199
SX_PERF_SEL_COL_SCBD_STALL = 200
SX_PERF_SEL_CLOCK_DROP_STALL = 201
SX_PERF_SEL_GATE_EN5 = 202
SX_PERF_SEL_GATE_EN6 = 203
SX_PERF_SEL_DB0_SIZE = 204
SX_PERF_SEL_DB1_SIZE = 205
SX_PERF_SEL_DB2_SIZE = 206
SX_PERF_SEL_DB3_SIZE = 207
SX_PERF_SEL_SPLITMODE = 208
SX_PERF_SEL_COL_SCBD0_STALL = 209
SX_PERF_SEL_COL_SCBD1_STALL = 210
SX_PERF_SEL_IDX_STALL_CYCLES = 211
SX_PERF_SEL_IDX_IDLE_CYCLES = 212
SX_PERF_SEL_IDX_REQ = 213
SX_PERF_SEL_IDX_RET = 214
SX_PERF_SEL_IDX_REQ_LATENCY = 215
SX_PERF_SEL_IDX_SCBD_STALL = 216
SX_PERF_SEL_GATE_EN7 = 217
SX_PERF_SEL_GATE_EN8 = 218
SX_PERF_SEL_SH_IDX_STARVE = 219
SX_PERF_SEL_IDX_BUSY = 220
SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum
# values for enumeration 'ForceControl'
ForceControl__enumvalues = {
0: 'FORCE_OFF',
1: 'FORCE_ENABLE',
2: 'FORCE_DISABLE',
3: 'FORCE_RESERVED',
}
FORCE_OFF = 0
FORCE_ENABLE = 1
FORCE_DISABLE = 2
FORCE_RESERVED = 3
ForceControl = ctypes.c_uint32 # enum
# values for enumeration 'ZSamplePosition'
ZSamplePosition__enumvalues = {
0: 'Z_SAMPLE_CENTER',
1: 'Z_SAMPLE_CENTROID',
}
Z_SAMPLE_CENTER = 0
Z_SAMPLE_CENTROID = 1
ZSamplePosition = ctypes.c_uint32 # enum
# values for enumeration 'ZOrder'
ZOrder__enumvalues = {
0: 'LATE_Z',
1: 'EARLY_Z_THEN_LATE_Z',
2: 'RE_Z',
3: 'EARLY_Z_THEN_RE_Z',
}
LATE_Z = 0
EARLY_Z_THEN_LATE_Z = 1
RE_Z = 2
EARLY_Z_THEN_RE_Z = 3
ZOrder = ctypes.c_uint32 # enum
# values for enumeration 'ZpassControl'
ZpassControl__enumvalues = {
0: 'ZPASS_DISABLE',
1: 'ZPASS_SAMPLES',
2: 'ZPASS_PIXELS',
}
ZPASS_DISABLE = 0
ZPASS_SAMPLES = 1
ZPASS_PIXELS = 2
ZpassControl = ctypes.c_uint32 # enum
# values for enumeration 'ZModeForce'
ZModeForce__enumvalues = {
0: 'NO_FORCE',
1: 'FORCE_EARLY_Z',
2: 'FORCE_LATE_Z',
3: 'FORCE_RE_Z',
}
NO_FORCE = 0
FORCE_EARLY_Z = 1
FORCE_LATE_Z = 2
FORCE_RE_Z = 3
ZModeForce = ctypes.c_uint32 # enum
# values for enumeration 'ZLimitSumm'
ZLimitSumm__enumvalues = {
0: 'FORCE_SUMM_OFF',
1: 'FORCE_SUMM_MINZ',
2: 'FORCE_SUMM_MAXZ',
3: 'FORCE_SUMM_BOTH',
}
FORCE_SUMM_OFF = 0
FORCE_SUMM_MINZ = 1
FORCE_SUMM_MAXZ = 2
FORCE_SUMM_BOTH = 3
ZLimitSumm = ctypes.c_uint32 # enum
# values for enumeration 'CompareFrag'
CompareFrag__enumvalues = {
0: 'FRAG_NEVER',
1: 'FRAG_LESS',
2: 'FRAG_EQUAL',
3: 'FRAG_LEQUAL',
4: 'FRAG_GREATER',
5: 'FRAG_NOTEQUAL',
6: 'FRAG_GEQUAL',
7: 'FRAG_ALWAYS',
}
FRAG_NEVER = 0
FRAG_LESS = 1
FRAG_EQUAL = 2
FRAG_LEQUAL = 3
FRAG_GREATER = 4
FRAG_NOTEQUAL = 5
FRAG_GEQUAL = 6
FRAG_ALWAYS = 7
CompareFrag = ctypes.c_uint32 # enum
# values for enumeration 'StencilOp'
StencilOp__enumvalues = {
0: 'STENCIL_KEEP',
1: 'STENCIL_ZERO',
2: 'STENCIL_ONES',
3: 'STENCIL_REPLACE_TEST',
4: 'STENCIL_REPLACE_OP',
5: 'STENCIL_ADD_CLAMP',
6: 'STENCIL_SUB_CLAMP',
7: 'STENCIL_INVERT',
8: 'STENCIL_ADD_WRAP',
9: 'STENCIL_SUB_WRAP',
10: 'STENCIL_AND',
11: 'STENCIL_OR',
12: 'STENCIL_XOR',
13: 'STENCIL_NAND',
14: 'STENCIL_NOR',
15: 'STENCIL_XNOR',
}
STENCIL_KEEP = 0
STENCIL_ZERO = 1
STENCIL_ONES = 2
STENCIL_REPLACE_TEST = 3
STENCIL_REPLACE_OP = 4
STENCIL_ADD_CLAMP = 5
STENCIL_SUB_CLAMP = 6
STENCIL_INVERT = 7
STENCIL_ADD_WRAP = 8
STENCIL_SUB_WRAP = 9
STENCIL_AND = 10
STENCIL_OR = 11
STENCIL_XOR = 12
STENCIL_NAND = 13
STENCIL_NOR = 14
STENCIL_XNOR = 15
StencilOp = ctypes.c_uint32 # enum
# values for enumeration 'ConservativeZExport'
ConservativeZExport__enumvalues = {
0: 'EXPORT_ANY_Z',
1: 'EXPORT_LESS_THAN_Z',
2: 'EXPORT_GREATER_THAN_Z',
3: 'EXPORT_RESERVED',
}
EXPORT_ANY_Z = 0
EXPORT_LESS_THAN_Z = 1
EXPORT_GREATER_THAN_Z = 2
EXPORT_RESERVED = 3
ConservativeZExport = ctypes.c_uint32 # enum
# values for enumeration 'DbPSLControl'
DbPSLControl__enumvalues = {
0: 'PSLC_AUTO',
1: 'PSLC_ON_HANG_ONLY',
2: 'PSLC_ASAP',
3: 'PSLC_COUNTDOWN',
}
PSLC_AUTO = 0
PSLC_ON_HANG_ONLY = 1
PSLC_ASAP = 2
PSLC_COUNTDOWN = 3
DbPSLControl = ctypes.c_uint32 # enum
# values for enumeration 'DbPRTFaultBehavior'
DbPRTFaultBehavior__enumvalues = {
0: 'FAULT_ZERO',
1: 'FAULT_ONE',
2: 'FAULT_FAIL',
3: 'FAULT_PASS',
}
FAULT_ZERO = 0
FAULT_ONE = 1
FAULT_FAIL = 2
FAULT_PASS = 3
DbPRTFaultBehavior = ctypes.c_uint32 # enum
# values for enumeration 'PerfCounter_Vals'
PerfCounter_Vals__enumvalues = {
0: 'DB_PERF_SEL_SC_DB_tile_sends',
1: 'DB_PERF_SEL_SC_DB_tile_busy',
2: 'DB_PERF_SEL_SC_DB_tile_stalls',
3: 'DB_PERF_SEL_SC_DB_tile_events',
4: 'DB_PERF_SEL_SC_DB_tile_tiles',
5: 'DB_PERF_SEL_SC_DB_tile_covered',
6: 'DB_PERF_SEL_hiz_tc_read_starved',
7: 'DB_PERF_SEL_hiz_tc_write_stall',
8: 'DB_PERF_SEL_hiz_tile_culled',
9: 'DB_PERF_SEL_his_tile_culled',
10: 'DB_PERF_SEL_DB_SC_tile_sends',
11: 'DB_PERF_SEL_DB_SC_tile_busy',
12: 'DB_PERF_SEL_DB_SC_tile_stalls',
13: 'DB_PERF_SEL_DB_SC_tile_df_stalls',
14: 'DB_PERF_SEL_DB_SC_tile_tiles',
15: 'DB_PERF_SEL_DB_SC_tile_culled',
16: 'DB_PERF_SEL_DB_SC_tile_hier_kill',
17: 'DB_PERF_SEL_DB_SC_tile_fast_ops',
18: 'DB_PERF_SEL_DB_SC_tile_no_ops',
19: 'DB_PERF_SEL_DB_SC_tile_tile_rate',
20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill',
21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops',
22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops',
23: 'DB_PERF_SEL_SC_DB_quad_sends',
24: 'DB_PERF_SEL_SC_DB_quad_busy',
25: 'DB_PERF_SEL_SC_DB_quad_squads',
26: 'DB_PERF_SEL_SC_DB_quad_tiles',
27: 'DB_PERF_SEL_SC_DB_quad_pixels',
28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles',
29: 'DB_PERF_SEL_DB_SC_quad_sends',
30: 'DB_PERF_SEL_DB_SC_quad_busy',
31: 'DB_PERF_SEL_DB_SC_quad_stalls',
32: 'DB_PERF_SEL_DB_SC_quad_tiles',
33: 'DB_PERF_SEL_DB_SC_quad_lit_quad',
34: 'DB_PERF_SEL_DB_CB_tile_sends',
35: 'DB_PERF_SEL_DB_CB_tile_busy',
36: 'DB_PERF_SEL_DB_CB_tile_stalls',
37: 'DB_PERF_SEL_SX_DB_quad_sends',
38: 'DB_PERF_SEL_SX_DB_quad_busy',
39: 'DB_PERF_SEL_SX_DB_quad_stalls',
40: 'DB_PERF_SEL_SX_DB_quad_quads',
41: 'DB_PERF_SEL_SX_DB_quad_pixels',
42: 'DB_PERF_SEL_SX_DB_quad_exports',
43: 'DB_PERF_SEL_SH_quads_outstanding_sum',
44: 'DB_PERF_SEL_DB_CB_lquad_sends',
45: 'DB_PERF_SEL_DB_CB_lquad_busy',
46: 'DB_PERF_SEL_DB_CB_lquad_stalls',
47: 'DB_PERF_SEL_DB_CB_lquad_quads',
48: 'DB_PERF_SEL_tile_rd_sends',
49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum',
50: 'DB_PERF_SEL_quad_rd_sends',
51: 'DB_PERF_SEL_quad_rd_busy',
52: 'DB_PERF_SEL_quad_rd_mi_stall',
53: 'DB_PERF_SEL_quad_rd_rw_collision',
54: 'DB_PERF_SEL_quad_rd_tag_stall',
55: 'DB_PERF_SEL_quad_rd_32byte_reqs',
56: 'DB_PERF_SEL_quad_rd_panic',
57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum',
58: 'DB_PERF_SEL_quad_rdret_sends',
59: 'DB_PERF_SEL_quad_rdret_busy',
60: 'DB_PERF_SEL_tile_wr_sends',
61: 'DB_PERF_SEL_tile_wr_acks',
62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum',
63: 'DB_PERF_SEL_quad_wr_sends',
64: 'DB_PERF_SEL_quad_wr_busy',
65: 'DB_PERF_SEL_quad_wr_mi_stall',
66: 'DB_PERF_SEL_quad_wr_coherency_stall',
67: 'DB_PERF_SEL_quad_wr_acks',
68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum',
69: 'DB_PERF_SEL_Tile_Cache_misses',
70: 'DB_PERF_SEL_Tile_Cache_hits',
71: 'DB_PERF_SEL_Tile_Cache_flushes',
72: 'DB_PERF_SEL_Tile_Cache_surface_stall',
73: 'DB_PERF_SEL_Tile_Cache_starves',
74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve',
75: 'DB_PERF_SEL_tcp_dispatcher_reads',
76: 'DB_PERF_SEL_tcp_prefetcher_reads',
77: 'DB_PERF_SEL_tcp_preloader_reads',
78: 'DB_PERF_SEL_tcp_dispatcher_flushes',
79: 'DB_PERF_SEL_tcp_prefetcher_flushes',
80: 'DB_PERF_SEL_tcp_preloader_flushes',
81: 'DB_PERF_SEL_Depth_Tile_Cache_sends',
82: 'DB_PERF_SEL_Depth_Tile_Cache_busy',
83: 'DB_PERF_SEL_Depth_Tile_Cache_starves',
84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked',
85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall',
86: 'DB_PERF_SEL_Depth_Tile_Cache_misses',
87: 'DB_PERF_SEL_Depth_Tile_Cache_hits',
88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes',
89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile',
90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop',
91: 'DB_PERF_SEL_Depth_Tile_Cache_event',
92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees',
93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees',
94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve',
95: 'DB_PERF_SEL_Stencil_Cache_misses',
96: 'DB_PERF_SEL_Stencil_Cache_hits',
97: 'DB_PERF_SEL_Stencil_Cache_flushes',
98: 'DB_PERF_SEL_Stencil_Cache_starves',
99: 'DB_PERF_SEL_Stencil_Cache_frees',
100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses',
101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits',
102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes',
103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves',
104: 'DB_PERF_SEL_Z_Cache_pmask_misses',
105: 'DB_PERF_SEL_Z_Cache_pmask_hits',
106: 'DB_PERF_SEL_Z_Cache_pmask_flushes',
107: 'DB_PERF_SEL_Z_Cache_pmask_starves',
108: 'DB_PERF_SEL_Z_Cache_frees',
109: 'DB_PERF_SEL_Plane_Cache_misses',
110: 'DB_PERF_SEL_Plane_Cache_hits',
111: 'DB_PERF_SEL_Plane_Cache_flushes',
112: 'DB_PERF_SEL_Plane_Cache_starves',
113: 'DB_PERF_SEL_Plane_Cache_frees',
114: 'DB_PERF_SEL_flush_expanded_stencil',
115: 'DB_PERF_SEL_flush_compressed_stencil',
116: 'DB_PERF_SEL_flush_single_stencil',
117: 'DB_PERF_SEL_planes_flushed',
118: 'DB_PERF_SEL_flush_1plane',
119: 'DB_PERF_SEL_flush_2plane',
120: 'DB_PERF_SEL_flush_3plane',
121: 'DB_PERF_SEL_flush_4plane',
122: 'DB_PERF_SEL_flush_5plane',
123: 'DB_PERF_SEL_flush_6plane',
124: 'DB_PERF_SEL_flush_7plane',
125: 'DB_PERF_SEL_flush_8plane',
126: 'DB_PERF_SEL_flush_9plane',
127: 'DB_PERF_SEL_flush_10plane',
128: 'DB_PERF_SEL_flush_11plane',
129: 'DB_PERF_SEL_flush_12plane',
130: 'DB_PERF_SEL_flush_13plane',
131: 'DB_PERF_SEL_flush_14plane',
132: 'DB_PERF_SEL_flush_15plane',
133: 'DB_PERF_SEL_flush_16plane',
134: 'DB_PERF_SEL_flush_expanded_z',
135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done',
136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done',
137: 'DB_PERF_SEL_dk_tile_sends',
138: 'DB_PERF_SEL_dk_tile_busy',
139: 'DB_PERF_SEL_dk_tile_quad_starves',
140: 'DB_PERF_SEL_dk_tile_stalls',
141: 'DB_PERF_SEL_dk_squad_sends',
142: 'DB_PERF_SEL_dk_squad_busy',
143: 'DB_PERF_SEL_dk_squad_stalls',
144: 'DB_PERF_SEL_Op_Pipe_Busy',
145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall',
146: 'DB_PERF_SEL_qc_busy',
147: 'DB_PERF_SEL_qc_xfc',
148: 'DB_PERF_SEL_qc_conflicts',
149: 'DB_PERF_SEL_qc_full_stall',
150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ',
151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ',
152: 'DB_PERF_SEL_tsc_insert_summarize_stall',
153: 'DB_PERF_SEL_tl_busy',
154: 'DB_PERF_SEL_tl_dtc_read_starved',
155: 'DB_PERF_SEL_tl_z_fetch_stall',
156: 'DB_PERF_SEL_tl_stencil_stall',
157: 'DB_PERF_SEL_tl_z_decompress_stall',
158: 'DB_PERF_SEL_tl_stencil_locked_stall',
159: 'DB_PERF_SEL_tl_events',
160: 'DB_PERF_SEL_tl_summarize_squads',
161: 'DB_PERF_SEL_tl_flush_expand_squads',
162: 'DB_PERF_SEL_tl_expand_squads',
163: 'DB_PERF_SEL_tl_preZ_squads',
164: 'DB_PERF_SEL_tl_postZ_squads',
165: 'DB_PERF_SEL_tl_preZ_noop_squads',
166: 'DB_PERF_SEL_tl_postZ_noop_squads',
167: 'DB_PERF_SEL_tl_tile_ops',
168: 'DB_PERF_SEL_tl_in_xfc',
169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall',
170: 'DB_PERF_SEL_tl_in_fast_z_stall',
171: 'DB_PERF_SEL_tl_out_xfc',
172: 'DB_PERF_SEL_tl_out_squads',
173: 'DB_PERF_SEL_zf_plane_multicycle',
174: 'DB_PERF_SEL_PostZ_Samples_passing_Z',
175: 'DB_PERF_SEL_PostZ_Samples_failing_Z',
176: 'DB_PERF_SEL_PostZ_Samples_failing_S',
177: 'DB_PERF_SEL_PreZ_Samples_passing_Z',
178: 'DB_PERF_SEL_PreZ_Samples_failing_Z',
179: 'DB_PERF_SEL_PreZ_Samples_failing_S',
180: 'DB_PERF_SEL_ts_tc_update_stall',
181: 'DB_PERF_SEL_sc_kick_start',
182: 'DB_PERF_SEL_sc_kick_end',
183: 'DB_PERF_SEL_clock_reg_active',
184: 'DB_PERF_SEL_clock_main_active',
185: 'DB_PERF_SEL_clock_mem_export_active',
186: 'DB_PERF_SEL_esr_ps_out_busy',
187: 'DB_PERF_SEL_esr_ps_lqf_busy',
188: 'DB_PERF_SEL_esr_ps_lqf_stall',
189: 'DB_PERF_SEL_etr_out_send',
190: 'DB_PERF_SEL_etr_out_busy',
191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall',
192: 'DB_PERF_SEL_etr_out_cb_tile_stall',
193: 'DB_PERF_SEL_etr_out_esr_stall',
194: 'DB_PERF_SEL_esr_ps_sqq_busy',
195: 'DB_PERF_SEL_esr_ps_sqq_stall',
196: 'DB_PERF_SEL_esr_eot_fwd_busy',
197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad',
198: 'DB_PERF_SEL_esr_eot_fwd_forward',
199: 'DB_PERF_SEL_esr_sqq_zi_busy',
200: 'DB_PERF_SEL_esr_sqq_zi_stall',
201: 'DB_PERF_SEL_postzl_sq_pt_busy',
202: 'DB_PERF_SEL_postzl_sq_pt_stall',
203: 'DB_PERF_SEL_postzl_se_busy',
204: 'DB_PERF_SEL_postzl_se_stall',
205: 'DB_PERF_SEL_postzl_partial_launch',
206: 'DB_PERF_SEL_postzl_full_launch',
207: 'DB_PERF_SEL_postzl_partial_waiting',
208: 'DB_PERF_SEL_postzl_tile_mem_stall',
209: 'DB_PERF_SEL_postzl_tile_init_stall',
210: 'DB_PERF_SEL_prezl_tile_mem_stall',
211: 'DB_PERF_SEL_prezl_tile_init_stall',
212: 'DB_PERF_SEL_dtt_sm_clash_stall',
213: 'DB_PERF_SEL_dtt_sm_slot_stall',
214: 'DB_PERF_SEL_dtt_sm_miss_stall',
215: 'DB_PERF_SEL_mi_rdreq_busy',
216: 'DB_PERF_SEL_mi_rdreq_stall',
217: 'DB_PERF_SEL_mi_wrreq_busy',
218: 'DB_PERF_SEL_mi_wrreq_stall',
219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop',
220: 'DB_PERF_SEL_dkg_tile_rate_tile',
221: 'DB_PERF_SEL_prezl_src_in_sends',
222: 'DB_PERF_SEL_prezl_src_in_stall',
223: 'DB_PERF_SEL_prezl_src_in_squads',
224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled',
225: 'DB_PERF_SEL_prezl_src_in_tile_rate',
226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled',
227: 'DB_PERF_SEL_prezl_src_out_stall',
228: 'DB_PERF_SEL_postzl_src_in_sends',
229: 'DB_PERF_SEL_postzl_src_in_stall',
230: 'DB_PERF_SEL_postzl_src_in_squads',
231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled',
232: 'DB_PERF_SEL_postzl_src_in_tile_rate',
233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled',
234: 'DB_PERF_SEL_postzl_src_out_stall',
235: 'DB_PERF_SEL_esr_ps_src_in_sends',
236: 'DB_PERF_SEL_esr_ps_src_in_stall',
237: 'DB_PERF_SEL_esr_ps_src_in_squads',
238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled',
239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate',
240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled',
241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate',
242: 'DB_PERF_SEL_esr_ps_src_out_stall',
243: 'DB_PERF_SEL_depth_bounds_tile_culled',
244: 'DB_PERF_SEL_PreZ_Samples_failing_DB',
245: 'DB_PERF_SEL_PostZ_Samples_failing_DB',
246: 'DB_PERF_SEL_flush_compressed',
247: 'DB_PERF_SEL_flush_plane_le4',
248: 'DB_PERF_SEL_tiles_z_fully_summarized',
249: 'DB_PERF_SEL_tiles_stencil_fully_summarized',
250: 'DB_PERF_SEL_tiles_z_clear_on_expclear',
251: 'DB_PERF_SEL_tiles_s_clear_on_expclear',
252: 'DB_PERF_SEL_tiles_decomp_on_expclear',
253: 'DB_PERF_SEL_tiles_compressed_to_decompressed',
254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy',
255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy',
256: 'DB_PERF_SEL_di_dt_stall',
257: 'DB_PERF_SEL_DB_SC_quad_lit_quad_pre_invoke',
258: 'DB_PERF_SEL_DB_SC_s_tile_rate',
259: 'DB_PERF_SEL_DB_SC_c_tile_rate',
260: 'DB_PERF_SEL_DB_SC_z_tile_rate',
261: 'Spare_261',
262: 'DB_PERF_SEL_DB_CB_lquad_export_quads',
263: 'DB_PERF_SEL_DB_CB_lquad_double_format',
264: 'DB_PERF_SEL_DB_CB_lquad_fast_format',
265: 'DB_PERF_SEL_DB_CB_lquad_slow_format',
266: 'DB_PERF_SEL_CB_DB_rdreq_sends',
267: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends',
268: 'DB_PERF_SEL_CB_DB_wrreq_sends',
269: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends',
270: 'DB_PERF_SEL_DB_CB_rdret_ack',
271: 'DB_PERF_SEL_DB_CB_rdret_nack',
272: 'DB_PERF_SEL_DB_CB_wrret_ack',
273: 'DB_PERF_SEL_DB_CB_wrret_nack',
274: 'DB_PERF_SEL_DFSM_Stall_opmode_change',
275: 'DB_PERF_SEL_DFSM_Stall_cam_fifo',
276: 'DB_PERF_SEL_DFSM_Stall_bypass_fifo',
277: 'DB_PERF_SEL_DFSM_Stall_retained_tile_fifo',
278: 'DB_PERF_SEL_DFSM_Stall_control_fifo',
279: 'DB_PERF_SEL_DFSM_Stall_overflow_counter',
280: 'DB_PERF_SEL_DFSM_Stall_pops_stall_overflow',
281: 'DB_PERF_SEL_DFSM_Stall_pops_stall_self_flush',
282: 'DB_PERF_SEL_DFSM_Stall_middle_output',
283: 'DB_PERF_SEL_DFSM_Stall_stalling_general',
284: 'Spare_285',
285: 'Spare_286',
286: 'DB_PERF_SEL_DFSM_prez_killed_squad',
287: 'DB_PERF_SEL_DFSM_squads_in',
288: 'DB_PERF_SEL_DFSM_full_cleared_squads_out',
289: 'DB_PERF_SEL_DFSM_quads_in',
290: 'DB_PERF_SEL_DFSM_fully_cleared_quads_out',
291: 'DB_PERF_SEL_DFSM_lit_pixels_in',
292: 'DB_PERF_SEL_DFSM_fully_cleared_pixels_out',
293: 'DB_PERF_SEL_DFSM_lit_samples_in',
294: 'DB_PERF_SEL_DFSM_lit_samples_out',
295: 'DB_PERF_SEL_DFSM_evicted_tiles_above_watermark',
296: 'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream',
297: 'DB_PERF_SEL_DFSM_stalled_by_downstream',
298: 'DB_PERF_SEL_DFSM_evicted_squads_above_watermark',
299: 'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow',
300: 'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO',
301: 'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark',
302: 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall',
303: 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall',
304: 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall',
305: 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall',
306: 'DB_PERF_SEL_unmapped_z_tile_culled',
307: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS',
308: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA',
309: 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS',
310: 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event',
311: 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix',
312: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix',
313: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix',
314: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix',
315: 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending',
316: 'DB_PERF_SEL_DB_CB_context_dones',
317: 'DB_PERF_SEL_DB_CB_eop_dones',
318: 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed',
319: 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled',
320: 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read',
321: 'DB_PERF_SEL_SC_DB_tile_backface',
322: 'DB_PERF_SEL_SC_DB_quad_quads',
323: 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel',
324: 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels',
325: 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels',
326: 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels',
327: 'DB_PERF_SEL_DFSM_Flush_flushabit',
328: 'DB_PERF_SEL_DFSM_Flush_flushabit_camcoord_fifo',
329: 'DB_PERF_SEL_DFSM_Flush_flushabit_passthrough',
330: 'DB_PERF_SEL_DFSM_Flush_flushabit_forceflush',
331: 'DB_PERF_SEL_DFSM_Flush_flushabit_nearlyfull',
332: 'DB_PERF_SEL_DFSM_Flush_flushabit_primitivesinflightwatermark',
333: 'DB_PERF_SEL_DFSM_Flush_flushabit_punch_stalling',
334: 'DB_PERF_SEL_DFSM_Flush_flushabit_retainedtilefifo_watermark',
335: 'DB_PERF_SEL_DFSM_Flush_flushabit_tilesinflightwatermark',
336: 'DB_PERF_SEL_DFSM_Flush_flushall',
337: 'DB_PERF_SEL_DFSM_Flush_flushall_dfsmflush',
338: 'DB_PERF_SEL_DFSM_Flush_flushall_opmodechange',
339: 'DB_PERF_SEL_DFSM_Flush_flushall_sampleratechange',
340: 'DB_PERF_SEL_DFSM_Flush_flushall_watchdog',
341: 'DB_PERF_SEL_DB_SC_quad_double_quad',
342: 'DB_PERF_SEL_SX_DB_quad_export_quads',
343: 'DB_PERF_SEL_SX_DB_quad_double_format',
344: 'DB_PERF_SEL_SX_DB_quad_fast_format',
345: 'DB_PERF_SEL_SX_DB_quad_slow_format',
}
DB_PERF_SEL_SC_DB_tile_sends = 0
DB_PERF_SEL_SC_DB_tile_busy = 1
DB_PERF_SEL_SC_DB_tile_stalls = 2
DB_PERF_SEL_SC_DB_tile_events = 3
DB_PERF_SEL_SC_DB_tile_tiles = 4
DB_PERF_SEL_SC_DB_tile_covered = 5
DB_PERF_SEL_hiz_tc_read_starved = 6
DB_PERF_SEL_hiz_tc_write_stall = 7
DB_PERF_SEL_hiz_tile_culled = 8
DB_PERF_SEL_his_tile_culled = 9
DB_PERF_SEL_DB_SC_tile_sends = 10
DB_PERF_SEL_DB_SC_tile_busy = 11
DB_PERF_SEL_DB_SC_tile_stalls = 12
DB_PERF_SEL_DB_SC_tile_df_stalls = 13
DB_PERF_SEL_DB_SC_tile_tiles = 14
DB_PERF_SEL_DB_SC_tile_culled = 15
DB_PERF_SEL_DB_SC_tile_hier_kill = 16
DB_PERF_SEL_DB_SC_tile_fast_ops = 17
DB_PERF_SEL_DB_SC_tile_no_ops = 18
DB_PERF_SEL_DB_SC_tile_tile_rate = 19
DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20
DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21
DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22
DB_PERF_SEL_SC_DB_quad_sends = 23
DB_PERF_SEL_SC_DB_quad_busy = 24
DB_PERF_SEL_SC_DB_quad_squads = 25
DB_PERF_SEL_SC_DB_quad_tiles = 26
DB_PERF_SEL_SC_DB_quad_pixels = 27
DB_PERF_SEL_SC_DB_quad_killed_tiles = 28
DB_PERF_SEL_DB_SC_quad_sends = 29
DB_PERF_SEL_DB_SC_quad_busy = 30
DB_PERF_SEL_DB_SC_quad_stalls = 31
DB_PERF_SEL_DB_SC_quad_tiles = 32
DB_PERF_SEL_DB_SC_quad_lit_quad = 33
DB_PERF_SEL_DB_CB_tile_sends = 34
DB_PERF_SEL_DB_CB_tile_busy = 35
DB_PERF_SEL_DB_CB_tile_stalls = 36
DB_PERF_SEL_SX_DB_quad_sends = 37
DB_PERF_SEL_SX_DB_quad_busy = 38
DB_PERF_SEL_SX_DB_quad_stalls = 39
DB_PERF_SEL_SX_DB_quad_quads = 40
DB_PERF_SEL_SX_DB_quad_pixels = 41
DB_PERF_SEL_SX_DB_quad_exports = 42
DB_PERF_SEL_SH_quads_outstanding_sum = 43
DB_PERF_SEL_DB_CB_lquad_sends = 44
DB_PERF_SEL_DB_CB_lquad_busy = 45
DB_PERF_SEL_DB_CB_lquad_stalls = 46
DB_PERF_SEL_DB_CB_lquad_quads = 47
DB_PERF_SEL_tile_rd_sends = 48
DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49
DB_PERF_SEL_quad_rd_sends = 50
DB_PERF_SEL_quad_rd_busy = 51
DB_PERF_SEL_quad_rd_mi_stall = 52
DB_PERF_SEL_quad_rd_rw_collision = 53
DB_PERF_SEL_quad_rd_tag_stall = 54
DB_PERF_SEL_quad_rd_32byte_reqs = 55
DB_PERF_SEL_quad_rd_panic = 56
DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57
DB_PERF_SEL_quad_rdret_sends = 58
DB_PERF_SEL_quad_rdret_busy = 59
DB_PERF_SEL_tile_wr_sends = 60
DB_PERF_SEL_tile_wr_acks = 61
DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62
DB_PERF_SEL_quad_wr_sends = 63
DB_PERF_SEL_quad_wr_busy = 64
DB_PERF_SEL_quad_wr_mi_stall = 65
DB_PERF_SEL_quad_wr_coherency_stall = 66
DB_PERF_SEL_quad_wr_acks = 67
DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68
DB_PERF_SEL_Tile_Cache_misses = 69
DB_PERF_SEL_Tile_Cache_hits = 70
DB_PERF_SEL_Tile_Cache_flushes = 71
DB_PERF_SEL_Tile_Cache_surface_stall = 72
DB_PERF_SEL_Tile_Cache_starves = 73
DB_PERF_SEL_Tile_Cache_mem_return_starve = 74
DB_PERF_SEL_tcp_dispatcher_reads = 75
DB_PERF_SEL_tcp_prefetcher_reads = 76
DB_PERF_SEL_tcp_preloader_reads = 77
DB_PERF_SEL_tcp_dispatcher_flushes = 78
DB_PERF_SEL_tcp_prefetcher_flushes = 79
DB_PERF_SEL_tcp_preloader_flushes = 80
DB_PERF_SEL_Depth_Tile_Cache_sends = 81
DB_PERF_SEL_Depth_Tile_Cache_busy = 82
DB_PERF_SEL_Depth_Tile_Cache_starves = 83
DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84
DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85
DB_PERF_SEL_Depth_Tile_Cache_misses = 86
DB_PERF_SEL_Depth_Tile_Cache_hits = 87
DB_PERF_SEL_Depth_Tile_Cache_flushes = 88
DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89
DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90
DB_PERF_SEL_Depth_Tile_Cache_event = 91
DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92
DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93
DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94
DB_PERF_SEL_Stencil_Cache_misses = 95
DB_PERF_SEL_Stencil_Cache_hits = 96
DB_PERF_SEL_Stencil_Cache_flushes = 97
DB_PERF_SEL_Stencil_Cache_starves = 98
DB_PERF_SEL_Stencil_Cache_frees = 99
DB_PERF_SEL_Z_Cache_separate_Z_misses = 100
DB_PERF_SEL_Z_Cache_separate_Z_hits = 101
DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102
DB_PERF_SEL_Z_Cache_separate_Z_starves = 103
DB_PERF_SEL_Z_Cache_pmask_misses = 104
DB_PERF_SEL_Z_Cache_pmask_hits = 105
DB_PERF_SEL_Z_Cache_pmask_flushes = 106
DB_PERF_SEL_Z_Cache_pmask_starves = 107
DB_PERF_SEL_Z_Cache_frees = 108
DB_PERF_SEL_Plane_Cache_misses = 109
DB_PERF_SEL_Plane_Cache_hits = 110
DB_PERF_SEL_Plane_Cache_flushes = 111
DB_PERF_SEL_Plane_Cache_starves = 112
DB_PERF_SEL_Plane_Cache_frees = 113
DB_PERF_SEL_flush_expanded_stencil = 114
DB_PERF_SEL_flush_compressed_stencil = 115
DB_PERF_SEL_flush_single_stencil = 116
DB_PERF_SEL_planes_flushed = 117
DB_PERF_SEL_flush_1plane = 118
DB_PERF_SEL_flush_2plane = 119
DB_PERF_SEL_flush_3plane = 120
DB_PERF_SEL_flush_4plane = 121
DB_PERF_SEL_flush_5plane = 122
DB_PERF_SEL_flush_6plane = 123
DB_PERF_SEL_flush_7plane = 124
DB_PERF_SEL_flush_8plane = 125
DB_PERF_SEL_flush_9plane = 126
DB_PERF_SEL_flush_10plane = 127
DB_PERF_SEL_flush_11plane = 128
DB_PERF_SEL_flush_12plane = 129
DB_PERF_SEL_flush_13plane = 130
DB_PERF_SEL_flush_14plane = 131
DB_PERF_SEL_flush_15plane = 132
DB_PERF_SEL_flush_16plane = 133
DB_PERF_SEL_flush_expanded_z = 134
DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135
DB_PERF_SEL_reZ_waiting_for_postZ_done = 136
DB_PERF_SEL_dk_tile_sends = 137
DB_PERF_SEL_dk_tile_busy = 138
DB_PERF_SEL_dk_tile_quad_starves = 139
DB_PERF_SEL_dk_tile_stalls = 140
DB_PERF_SEL_dk_squad_sends = 141
DB_PERF_SEL_dk_squad_busy = 142
DB_PERF_SEL_dk_squad_stalls = 143
DB_PERF_SEL_Op_Pipe_Busy = 144
DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145
DB_PERF_SEL_qc_busy = 146
DB_PERF_SEL_qc_xfc = 147
DB_PERF_SEL_qc_conflicts = 148
DB_PERF_SEL_qc_full_stall = 149
DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150
DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151
DB_PERF_SEL_tsc_insert_summarize_stall = 152
DB_PERF_SEL_tl_busy = 153
DB_PERF_SEL_tl_dtc_read_starved = 154
DB_PERF_SEL_tl_z_fetch_stall = 155
DB_PERF_SEL_tl_stencil_stall = 156
DB_PERF_SEL_tl_z_decompress_stall = 157
DB_PERF_SEL_tl_stencil_locked_stall = 158
DB_PERF_SEL_tl_events = 159
DB_PERF_SEL_tl_summarize_squads = 160
DB_PERF_SEL_tl_flush_expand_squads = 161
DB_PERF_SEL_tl_expand_squads = 162
DB_PERF_SEL_tl_preZ_squads = 163
DB_PERF_SEL_tl_postZ_squads = 164
DB_PERF_SEL_tl_preZ_noop_squads = 165
DB_PERF_SEL_tl_postZ_noop_squads = 166
DB_PERF_SEL_tl_tile_ops = 167
DB_PERF_SEL_tl_in_xfc = 168
DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169
DB_PERF_SEL_tl_in_fast_z_stall = 170
DB_PERF_SEL_tl_out_xfc = 171
DB_PERF_SEL_tl_out_squads = 172
DB_PERF_SEL_zf_plane_multicycle = 173
DB_PERF_SEL_PostZ_Samples_passing_Z = 174
DB_PERF_SEL_PostZ_Samples_failing_Z = 175
DB_PERF_SEL_PostZ_Samples_failing_S = 176
DB_PERF_SEL_PreZ_Samples_passing_Z = 177
DB_PERF_SEL_PreZ_Samples_failing_Z = 178
DB_PERF_SEL_PreZ_Samples_failing_S = 179
DB_PERF_SEL_ts_tc_update_stall = 180
DB_PERF_SEL_sc_kick_start = 181
DB_PERF_SEL_sc_kick_end = 182
DB_PERF_SEL_clock_reg_active = 183
DB_PERF_SEL_clock_main_active = 184
DB_PERF_SEL_clock_mem_export_active = 185
DB_PERF_SEL_esr_ps_out_busy = 186
DB_PERF_SEL_esr_ps_lqf_busy = 187
DB_PERF_SEL_esr_ps_lqf_stall = 188
DB_PERF_SEL_etr_out_send = 189
DB_PERF_SEL_etr_out_busy = 190
DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191
DB_PERF_SEL_etr_out_cb_tile_stall = 192
DB_PERF_SEL_etr_out_esr_stall = 193
DB_PERF_SEL_esr_ps_sqq_busy = 194
DB_PERF_SEL_esr_ps_sqq_stall = 195
DB_PERF_SEL_esr_eot_fwd_busy = 196
DB_PERF_SEL_esr_eot_fwd_holding_squad = 197
DB_PERF_SEL_esr_eot_fwd_forward = 198
DB_PERF_SEL_esr_sqq_zi_busy = 199
DB_PERF_SEL_esr_sqq_zi_stall = 200
DB_PERF_SEL_postzl_sq_pt_busy = 201
DB_PERF_SEL_postzl_sq_pt_stall = 202
DB_PERF_SEL_postzl_se_busy = 203
DB_PERF_SEL_postzl_se_stall = 204
DB_PERF_SEL_postzl_partial_launch = 205
DB_PERF_SEL_postzl_full_launch = 206
DB_PERF_SEL_postzl_partial_waiting = 207
DB_PERF_SEL_postzl_tile_mem_stall = 208
DB_PERF_SEL_postzl_tile_init_stall = 209
DB_PERF_SEL_prezl_tile_mem_stall = 210
DB_PERF_SEL_prezl_tile_init_stall = 211
DB_PERF_SEL_dtt_sm_clash_stall = 212
DB_PERF_SEL_dtt_sm_slot_stall = 213
DB_PERF_SEL_dtt_sm_miss_stall = 214
DB_PERF_SEL_mi_rdreq_busy = 215
DB_PERF_SEL_mi_rdreq_stall = 216
DB_PERF_SEL_mi_wrreq_busy = 217
DB_PERF_SEL_mi_wrreq_stall = 218
DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219
DB_PERF_SEL_dkg_tile_rate_tile = 220
DB_PERF_SEL_prezl_src_in_sends = 221
DB_PERF_SEL_prezl_src_in_stall = 222
DB_PERF_SEL_prezl_src_in_squads = 223
DB_PERF_SEL_prezl_src_in_squads_unrolled = 224
DB_PERF_SEL_prezl_src_in_tile_rate = 225
DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226
DB_PERF_SEL_prezl_src_out_stall = 227
DB_PERF_SEL_postzl_src_in_sends = 228
DB_PERF_SEL_postzl_src_in_stall = 229
DB_PERF_SEL_postzl_src_in_squads = 230
DB_PERF_SEL_postzl_src_in_squads_unrolled = 231
DB_PERF_SEL_postzl_src_in_tile_rate = 232
DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233
DB_PERF_SEL_postzl_src_out_stall = 234
DB_PERF_SEL_esr_ps_src_in_sends = 235
DB_PERF_SEL_esr_ps_src_in_stall = 236
DB_PERF_SEL_esr_ps_src_in_squads = 237
DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238
DB_PERF_SEL_esr_ps_src_in_tile_rate = 239
DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240
DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241
DB_PERF_SEL_esr_ps_src_out_stall = 242
DB_PERF_SEL_depth_bounds_tile_culled = 243
DB_PERF_SEL_PreZ_Samples_failing_DB = 244
DB_PERF_SEL_PostZ_Samples_failing_DB = 245
DB_PERF_SEL_flush_compressed = 246
DB_PERF_SEL_flush_plane_le4 = 247
DB_PERF_SEL_tiles_z_fully_summarized = 248
DB_PERF_SEL_tiles_stencil_fully_summarized = 249
DB_PERF_SEL_tiles_z_clear_on_expclear = 250
DB_PERF_SEL_tiles_s_clear_on_expclear = 251
DB_PERF_SEL_tiles_decomp_on_expclear = 252
DB_PERF_SEL_tiles_compressed_to_decompressed = 253
DB_PERF_SEL_Op_Pipe_Prez_Busy = 254
DB_PERF_SEL_Op_Pipe_Postz_Busy = 255
DB_PERF_SEL_di_dt_stall = 256
DB_PERF_SEL_DB_SC_quad_lit_quad_pre_invoke = 257
DB_PERF_SEL_DB_SC_s_tile_rate = 258
DB_PERF_SEL_DB_SC_c_tile_rate = 259
DB_PERF_SEL_DB_SC_z_tile_rate = 260
Spare_261 = 261
DB_PERF_SEL_DB_CB_lquad_export_quads = 262
DB_PERF_SEL_DB_CB_lquad_double_format = 263
DB_PERF_SEL_DB_CB_lquad_fast_format = 264
DB_PERF_SEL_DB_CB_lquad_slow_format = 265
DB_PERF_SEL_CB_DB_rdreq_sends = 266
DB_PERF_SEL_CB_DB_rdreq_prt_sends = 267
DB_PERF_SEL_CB_DB_wrreq_sends = 268
DB_PERF_SEL_CB_DB_wrreq_prt_sends = 269
DB_PERF_SEL_DB_CB_rdret_ack = 270
DB_PERF_SEL_DB_CB_rdret_nack = 271
DB_PERF_SEL_DB_CB_wrret_ack = 272
DB_PERF_SEL_DB_CB_wrret_nack = 273
DB_PERF_SEL_DFSM_Stall_opmode_change = 274
DB_PERF_SEL_DFSM_Stall_cam_fifo = 275
DB_PERF_SEL_DFSM_Stall_bypass_fifo = 276
DB_PERF_SEL_DFSM_Stall_retained_tile_fifo = 277
DB_PERF_SEL_DFSM_Stall_control_fifo = 278
DB_PERF_SEL_DFSM_Stall_overflow_counter = 279
DB_PERF_SEL_DFSM_Stall_pops_stall_overflow = 280
DB_PERF_SEL_DFSM_Stall_pops_stall_self_flush = 281
DB_PERF_SEL_DFSM_Stall_middle_output = 282
DB_PERF_SEL_DFSM_Stall_stalling_general = 283
Spare_285 = 284
Spare_286 = 285
DB_PERF_SEL_DFSM_prez_killed_squad = 286
DB_PERF_SEL_DFSM_squads_in = 287
DB_PERF_SEL_DFSM_full_cleared_squads_out = 288
DB_PERF_SEL_DFSM_quads_in = 289
DB_PERF_SEL_DFSM_fully_cleared_quads_out = 290
DB_PERF_SEL_DFSM_lit_pixels_in = 291
DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 292
DB_PERF_SEL_DFSM_lit_samples_in = 293
DB_PERF_SEL_DFSM_lit_samples_out = 294
DB_PERF_SEL_DFSM_evicted_tiles_above_watermark = 295
DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 296
DB_PERF_SEL_DFSM_stalled_by_downstream = 297
DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 298
DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 299
DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 300
DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 301
DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 302
DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 303
DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 304
DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 305
DB_PERF_SEL_unmapped_z_tile_culled = 306
DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 307
DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 308
DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 309
DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 310
DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 311
DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 312
DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 313
DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 314
DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 315
DB_PERF_SEL_DB_CB_context_dones = 316
DB_PERF_SEL_DB_CB_eop_dones = 317
DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 318
DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 319
DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 320
DB_PERF_SEL_SC_DB_tile_backface = 321
DB_PERF_SEL_SC_DB_quad_quads = 322
DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 323
DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 324
DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 325
DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 326
DB_PERF_SEL_DFSM_Flush_flushabit = 327
DB_PERF_SEL_DFSM_Flush_flushabit_camcoord_fifo = 328
DB_PERF_SEL_DFSM_Flush_flushabit_passthrough = 329
DB_PERF_SEL_DFSM_Flush_flushabit_forceflush = 330
DB_PERF_SEL_DFSM_Flush_flushabit_nearlyfull = 331
DB_PERF_SEL_DFSM_Flush_flushabit_primitivesinflightwatermark = 332
DB_PERF_SEL_DFSM_Flush_flushabit_punch_stalling = 333
DB_PERF_SEL_DFSM_Flush_flushabit_retainedtilefifo_watermark = 334
DB_PERF_SEL_DFSM_Flush_flushabit_tilesinflightwatermark = 335
DB_PERF_SEL_DFSM_Flush_flushall = 336
DB_PERF_SEL_DFSM_Flush_flushall_dfsmflush = 337
DB_PERF_SEL_DFSM_Flush_flushall_opmodechange = 338
DB_PERF_SEL_DFSM_Flush_flushall_sampleratechange = 339
DB_PERF_SEL_DFSM_Flush_flushall_watchdog = 340
DB_PERF_SEL_DB_SC_quad_double_quad = 341
DB_PERF_SEL_SX_DB_quad_export_quads = 342
DB_PERF_SEL_SX_DB_quad_double_format = 343
DB_PERF_SEL_SX_DB_quad_fast_format = 344
DB_PERF_SEL_SX_DB_quad_slow_format = 345
PerfCounter_Vals = ctypes.c_uint32 # enum
# values for enumeration 'RingCounterControl'
RingCounterControl__enumvalues = {
0: 'COUNTER_RING_SPLIT',
1: 'COUNTER_RING_0',
2: 'COUNTER_RING_1',
}
COUNTER_RING_SPLIT = 0
COUNTER_RING_0 = 1
COUNTER_RING_1 = 2
RingCounterControl = ctypes.c_uint32 # enum
# values for enumeration 'DbMemArbWatermarks'
DbMemArbWatermarks__enumvalues = {
0: 'TRANSFERRED_64_BYTES',
1: 'TRANSFERRED_128_BYTES',
2: 'TRANSFERRED_256_BYTES',
3: 'TRANSFERRED_512_BYTES',
4: 'TRANSFERRED_1024_BYTES',
5: 'TRANSFERRED_2048_BYTES',
6: 'TRANSFERRED_4096_BYTES',
7: 'TRANSFERRED_8192_BYTES',
}
TRANSFERRED_64_BYTES = 0
TRANSFERRED_128_BYTES = 1
TRANSFERRED_256_BYTES = 2
TRANSFERRED_512_BYTES = 3
TRANSFERRED_1024_BYTES = 4
TRANSFERRED_2048_BYTES = 5
TRANSFERRED_4096_BYTES = 6
TRANSFERRED_8192_BYTES = 7
DbMemArbWatermarks = ctypes.c_uint32 # enum
# values for enumeration 'DFSMFlushEvents'
DFSMFlushEvents__enumvalues = {
0: 'DB_FLUSH_AND_INV_DB_DATA_TS',
1: 'DB_FLUSH_AND_INV_DB_META',
2: 'DB_CACHE_FLUSH',
3: 'DB_CACHE_FLUSH_TS',
4: 'DB_CACHE_FLUSH_AND_INV_EVENT',
5: 'DB_CACHE_FLUSH_AND_INV_TS_EVENT',
6: 'DB_VPORT_CHANGED_EVENT',
7: 'DB_CONTEXT_DONE_EVENT',
8: 'DB_BREAK_BATCH_EVENT',
9: 'DB_PSINVOKE_CHANGE_EVENT',
10: 'DB_CONTEXT_SUSPEND_EVENT',
}
DB_FLUSH_AND_INV_DB_DATA_TS = 0
DB_FLUSH_AND_INV_DB_META = 1
DB_CACHE_FLUSH = 2
DB_CACHE_FLUSH_TS = 3
DB_CACHE_FLUSH_AND_INV_EVENT = 4
DB_CACHE_FLUSH_AND_INV_TS_EVENT = 5
DB_VPORT_CHANGED_EVENT = 6
DB_CONTEXT_DONE_EVENT = 7
DB_BREAK_BATCH_EVENT = 8
DB_PSINVOKE_CHANGE_EVENT = 9
DB_CONTEXT_SUSPEND_EVENT = 10
DFSMFlushEvents = ctypes.c_uint32 # enum
# values for enumeration 'PixelPipeCounterId'
PixelPipeCounterId__enumvalues = {
0: 'PIXEL_PIPE_OCCLUSION_COUNT_0',
1: 'PIXEL_PIPE_OCCLUSION_COUNT_1',
2: 'PIXEL_PIPE_OCCLUSION_COUNT_2',
3: 'PIXEL_PIPE_OCCLUSION_COUNT_3',
4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0',
5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0',
6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1',
7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1',
}
PIXEL_PIPE_OCCLUSION_COUNT_0 = 0
PIXEL_PIPE_OCCLUSION_COUNT_1 = 1
PIXEL_PIPE_OCCLUSION_COUNT_2 = 2
PIXEL_PIPE_OCCLUSION_COUNT_3 = 3
PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4
PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5
PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6
PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7
PixelPipeCounterId = ctypes.c_uint32 # enum
# values for enumeration 'PixelPipeStride'
PixelPipeStride__enumvalues = {
0: 'PIXEL_PIPE_STRIDE_32_BITS',
1: 'PIXEL_PIPE_STRIDE_64_BITS',
2: 'PIXEL_PIPE_STRIDE_128_BITS',
3: 'PIXEL_PIPE_STRIDE_256_BITS',
}
PIXEL_PIPE_STRIDE_32_BITS = 0
PIXEL_PIPE_STRIDE_64_BITS = 1
PIXEL_PIPE_STRIDE_128_BITS = 2
PIXEL_PIPE_STRIDE_256_BITS = 3
PixelPipeStride = ctypes.c_uint32 # enum
# values for enumeration 'FullTileWaveBreak'
FullTileWaveBreak__enumvalues = {
0: 'FULL_TILE_WAVE_BREAK_NBC_ONLY',
1: 'FULL_TILE_WAVE_BREAK_BOTH',
2: 'FULL_TILE_WAVE_BREAK_NONE',
3: 'FULL_TILE_WAVE_BREAK_BC_ONLY',
}
FULL_TILE_WAVE_BREAK_NBC_ONLY = 0
FULL_TILE_WAVE_BREAK_BOTH = 1
FULL_TILE_WAVE_BREAK_NONE = 2
FULL_TILE_WAVE_BREAK_BC_ONLY = 3
FullTileWaveBreak = ctypes.c_uint32 # enum
# values for enumeration 'TEX_BORDER_COLOR_TYPE'
TEX_BORDER_COLOR_TYPE__enumvalues = {
0: 'TEX_BorderColor_TransparentBlack',
1: 'TEX_BorderColor_OpaqueBlack',
2: 'TEX_BorderColor_OpaqueWhite',
3: 'TEX_BorderColor_Register',
}
TEX_BorderColor_TransparentBlack = 0
TEX_BorderColor_OpaqueBlack = 1
TEX_BorderColor_OpaqueWhite = 2
TEX_BorderColor_Register = 3
TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_BC_SWIZZLE'
TEX_BC_SWIZZLE__enumvalues = {
0: 'TEX_BC_Swizzle_XYZW',
1: 'TEX_BC_Swizzle_XWYZ',
2: 'TEX_BC_Swizzle_WZYX',
3: 'TEX_BC_Swizzle_WXYZ',
4: 'TEX_BC_Swizzle_ZYXW',
5: 'TEX_BC_Swizzle_YXWZ',
}
TEX_BC_Swizzle_XYZW = 0
TEX_BC_Swizzle_XWYZ = 1
TEX_BC_Swizzle_WZYX = 2
TEX_BC_Swizzle_WXYZ = 3
TEX_BC_Swizzle_ZYXW = 4
TEX_BC_Swizzle_YXWZ = 5
TEX_BC_SWIZZLE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_CHROMA_KEY'
TEX_CHROMA_KEY__enumvalues = {
0: 'TEX_ChromaKey_Disabled',
1: 'TEX_ChromaKey_Kill',
2: 'TEX_ChromaKey_Blend',
3: 'TEX_ChromaKey_RESERVED_3',
}
TEX_ChromaKey_Disabled = 0
TEX_ChromaKey_Kill = 1
TEX_ChromaKey_Blend = 2
TEX_ChromaKey_RESERVED_3 = 3
TEX_CHROMA_KEY = ctypes.c_uint32 # enum
# values for enumeration 'TEX_CLAMP'
TEX_CLAMP__enumvalues = {
0: 'TEX_Clamp_Repeat',
1: 'TEX_Clamp_Mirror',
2: 'TEX_Clamp_ClampToLast',
3: 'TEX_Clamp_MirrorOnceToLast',
4: 'TEX_Clamp_ClampHalfToBorder',
5: 'TEX_Clamp_MirrorOnceHalfToBorder',
6: 'TEX_Clamp_ClampToBorder',
7: 'TEX_Clamp_MirrorOnceToBorder',
}
TEX_Clamp_Repeat = 0
TEX_Clamp_Mirror = 1
TEX_Clamp_ClampToLast = 2
TEX_Clamp_MirrorOnceToLast = 3
TEX_Clamp_ClampHalfToBorder = 4
TEX_Clamp_MirrorOnceHalfToBorder = 5
TEX_Clamp_ClampToBorder = 6
TEX_Clamp_MirrorOnceToBorder = 7
TEX_CLAMP = ctypes.c_uint32 # enum
# values for enumeration 'TEX_COORD_TYPE'
TEX_COORD_TYPE__enumvalues = {
0: 'TEX_CoordType_Unnormalized',
1: 'TEX_CoordType_Normalized',
}
TEX_CoordType_Unnormalized = 0
TEX_CoordType_Normalized = 1
TEX_COORD_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION'
TEX_DEPTH_COMPARE_FUNCTION__enumvalues = {
0: 'TEX_DepthCompareFunction_Never',
1: 'TEX_DepthCompareFunction_Less',
2: 'TEX_DepthCompareFunction_Equal',
3: 'TEX_DepthCompareFunction_LessEqual',
4: 'TEX_DepthCompareFunction_Greater',
5: 'TEX_DepthCompareFunction_NotEqual',
6: 'TEX_DepthCompareFunction_GreaterEqual',
7: 'TEX_DepthCompareFunction_Always',
}
TEX_DepthCompareFunction_Never = 0
TEX_DepthCompareFunction_Less = 1
TEX_DepthCompareFunction_Equal = 2
TEX_DepthCompareFunction_LessEqual = 3
TEX_DepthCompareFunction_Greater = 4
TEX_DepthCompareFunction_NotEqual = 5
TEX_DepthCompareFunction_GreaterEqual = 6
TEX_DepthCompareFunction_Always = 7
TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum
# values for enumeration 'TEX_DIM'
TEX_DIM__enumvalues = {
0: 'TEX_Dim_1D',
1: 'TEX_Dim_2D',
2: 'TEX_Dim_3D',
3: 'TEX_Dim_CubeMap',
4: 'TEX_Dim_1DArray',
5: 'TEX_Dim_2DArray',
6: 'TEX_Dim_2D_MSAA',
7: 'TEX_Dim_2DArray_MSAA',
}
TEX_Dim_1D = 0
TEX_Dim_2D = 1
TEX_Dim_3D = 2
TEX_Dim_CubeMap = 3
TEX_Dim_1DArray = 4
TEX_Dim_2DArray = 5
TEX_Dim_2D_MSAA = 6
TEX_Dim_2DArray_MSAA = 7
TEX_DIM = ctypes.c_uint32 # enum
# values for enumeration 'TEX_FORMAT_COMP'
TEX_FORMAT_COMP__enumvalues = {
0: 'TEX_FormatComp_Unsigned',
1: 'TEX_FormatComp_Signed',
2: 'TEX_FormatComp_UnsignedBiased',
3: 'TEX_FormatComp_RESERVED_3',
}
TEX_FormatComp_Unsigned = 0
TEX_FormatComp_Signed = 1
TEX_FormatComp_UnsignedBiased = 2
TEX_FormatComp_RESERVED_3 = 3
TEX_FORMAT_COMP = ctypes.c_uint32 # enum
# values for enumeration 'TEX_MAX_ANISO_RATIO'
TEX_MAX_ANISO_RATIO__enumvalues = {
0: 'TEX_MaxAnisoRatio_1to1',
1: 'TEX_MaxAnisoRatio_2to1',
2: 'TEX_MaxAnisoRatio_4to1',
3: 'TEX_MaxAnisoRatio_8to1',
4: 'TEX_MaxAnisoRatio_16to1',
5: 'TEX_MaxAnisoRatio_RESERVED_5',
6: 'TEX_MaxAnisoRatio_RESERVED_6',
7: 'TEX_MaxAnisoRatio_RESERVED_7',
}
TEX_MaxAnisoRatio_1to1 = 0
TEX_MaxAnisoRatio_2to1 = 1
TEX_MaxAnisoRatio_4to1 = 2
TEX_MaxAnisoRatio_8to1 = 3
TEX_MaxAnisoRatio_16to1 = 4
TEX_MaxAnisoRatio_RESERVED_5 = 5
TEX_MaxAnisoRatio_RESERVED_6 = 6
TEX_MaxAnisoRatio_RESERVED_7 = 7
TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum
# values for enumeration 'TEX_MIP_FILTER'
TEX_MIP_FILTER__enumvalues = {
0: 'TEX_MipFilter_None',
1: 'TEX_MipFilter_Point',
2: 'TEX_MipFilter_Linear',
3: 'TEX_MipFilter_Point_Aniso_Adj',
}
TEX_MipFilter_None = 0
TEX_MipFilter_Point = 1
TEX_MipFilter_Linear = 2
TEX_MipFilter_Point_Aniso_Adj = 3
TEX_MIP_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'TEX_REQUEST_SIZE'
TEX_REQUEST_SIZE__enumvalues = {
0: 'TEX_RequestSize_32B',
1: 'TEX_RequestSize_64B',
2: 'TEX_RequestSize_128B',
3: 'TEX_RequestSize_2X64B',
}
TEX_RequestSize_32B = 0
TEX_RequestSize_64B = 1
TEX_RequestSize_128B = 2
TEX_RequestSize_2X64B = 3
TEX_REQUEST_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_SAMPLER_TYPE'
TEX_SAMPLER_TYPE__enumvalues = {
0: 'TEX_SamplerType_Invalid',
1: 'TEX_SamplerType_Valid',
}
TEX_SamplerType_Invalid = 0
TEX_SamplerType_Valid = 1
TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_XY_FILTER'
TEX_XY_FILTER__enumvalues = {
0: 'TEX_XYFilter_Point',
1: 'TEX_XYFilter_Linear',
2: 'TEX_XYFilter_AnisoPoint',
3: 'TEX_XYFilter_AnisoLinear',
}
TEX_XYFilter_Point = 0
TEX_XYFilter_Linear = 1
TEX_XYFilter_AnisoPoint = 2
TEX_XYFilter_AnisoLinear = 3
TEX_XY_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'TEX_Z_FILTER'
TEX_Z_FILTER__enumvalues = {
0: 'TEX_ZFilter_None',
1: 'TEX_ZFilter_Point',
2: 'TEX_ZFilter_Linear',
3: 'TEX_ZFilter_RESERVED_3',
}
TEX_ZFilter_None = 0
TEX_ZFilter_Point = 1
TEX_ZFilter_Linear = 2
TEX_ZFilter_RESERVED_3 = 3
TEX_Z_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'VTX_CLAMP'
VTX_CLAMP__enumvalues = {
0: 'VTX_Clamp_ClampToZero',
1: 'VTX_Clamp_ClampToNAN',
}
VTX_Clamp_ClampToZero = 0
VTX_Clamp_ClampToNAN = 1
VTX_CLAMP = ctypes.c_uint32 # enum
# values for enumeration 'VTX_FETCH_TYPE'
VTX_FETCH_TYPE__enumvalues = {
0: 'VTX_FetchType_VertexData',
1: 'VTX_FetchType_InstanceData',
2: 'VTX_FetchType_NoIndexOffset',
3: 'VTX_FetchType_RESERVED_3',
}
VTX_FetchType_VertexData = 0
VTX_FetchType_InstanceData = 1
VTX_FetchType_NoIndexOffset = 2
VTX_FetchType_RESERVED_3 = 3
VTX_FETCH_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VTX_FORMAT_COMP_ALL'
VTX_FORMAT_COMP_ALL__enumvalues = {
0: 'VTX_FormatCompAll_Unsigned',
1: 'VTX_FormatCompAll_Signed',
}
VTX_FormatCompAll_Unsigned = 0
VTX_FormatCompAll_Signed = 1
VTX_FORMAT_COMP_ALL = ctypes.c_uint32 # enum
# values for enumeration 'VTX_MEM_REQUEST_SIZE'
VTX_MEM_REQUEST_SIZE__enumvalues = {
0: 'VTX_MemRequestSize_32B',
1: 'VTX_MemRequestSize_64B',
}
VTX_MemRequestSize_32B = 0
VTX_MemRequestSize_64B = 1
VTX_MEM_REQUEST_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'TVX_DATA_FORMAT'
TVX_DATA_FORMAT__enumvalues = {
0: 'TVX_FMT_INVALID',
1: 'TVX_FMT_8',
2: 'TVX_FMT_4_4',
3: 'TVX_FMT_3_3_2',
4: 'TVX_FMT_RESERVED_4',
5: 'TVX_FMT_16',
6: 'TVX_FMT_16_FLOAT',
7: 'TVX_FMT_8_8',
8: 'TVX_FMT_5_6_5',
9: 'TVX_FMT_6_5_5',
10: 'TVX_FMT_1_5_5_5',
11: 'TVX_FMT_4_4_4_4',
12: 'TVX_FMT_5_5_5_1',
13: 'TVX_FMT_32',
14: 'TVX_FMT_32_FLOAT',
15: 'TVX_FMT_16_16',
16: 'TVX_FMT_16_16_FLOAT',
17: 'TVX_FMT_8_24',
18: 'TVX_FMT_8_24_FLOAT',
19: 'TVX_FMT_24_8',
20: 'TVX_FMT_24_8_FLOAT',
21: 'TVX_FMT_10_11_11',
22: 'TVX_FMT_10_11_11_FLOAT',
23: 'TVX_FMT_11_11_10',
24: 'TVX_FMT_11_11_10_FLOAT',
25: 'TVX_FMT_2_10_10_10',
26: 'TVX_FMT_8_8_8_8',
27: 'TVX_FMT_10_10_10_2',
28: 'TVX_FMT_X24_8_32_FLOAT',
29: 'TVX_FMT_32_32',
30: 'TVX_FMT_32_32_FLOAT',
31: 'TVX_FMT_16_16_16_16',
32: 'TVX_FMT_16_16_16_16_FLOAT',
33: 'TVX_FMT_RESERVED_33',
34: 'TVX_FMT_32_32_32_32',
35: 'TVX_FMT_32_32_32_32_FLOAT',
36: 'TVX_FMT_RESERVED_36',
37: 'TVX_FMT_1',
38: 'TVX_FMT_1_REVERSED',
39: 'TVX_FMT_GB_GR',
40: 'TVX_FMT_BG_RG',
41: 'TVX_FMT_32_AS_8',
42: 'TVX_FMT_32_AS_8_8',
43: 'TVX_FMT_5_9_9_9_SHAREDEXP',
44: 'TVX_FMT_8_8_8',
45: 'TVX_FMT_16_16_16',
46: 'TVX_FMT_16_16_16_FLOAT',
47: 'TVX_FMT_32_32_32',
48: 'TVX_FMT_32_32_32_FLOAT',
49: 'TVX_FMT_BC1',
50: 'TVX_FMT_BC2',
51: 'TVX_FMT_BC3',
52: 'TVX_FMT_BC4',
53: 'TVX_FMT_BC5',
54: 'TVX_FMT_APC0',
55: 'TVX_FMT_APC1',
56: 'TVX_FMT_APC2',
57: 'TVX_FMT_APC3',
58: 'TVX_FMT_APC4',
59: 'TVX_FMT_APC5',
60: 'TVX_FMT_APC6',
61: 'TVX_FMT_APC7',
62: 'TVX_FMT_CTX1',
63: 'TVX_FMT_RESERVED_63',
}
TVX_FMT_INVALID = 0
TVX_FMT_8 = 1
TVX_FMT_4_4 = 2
TVX_FMT_3_3_2 = 3
TVX_FMT_RESERVED_4 = 4
TVX_FMT_16 = 5
TVX_FMT_16_FLOAT = 6
TVX_FMT_8_8 = 7
TVX_FMT_5_6_5 = 8
TVX_FMT_6_5_5 = 9
TVX_FMT_1_5_5_5 = 10
TVX_FMT_4_4_4_4 = 11
TVX_FMT_5_5_5_1 = 12
TVX_FMT_32 = 13
TVX_FMT_32_FLOAT = 14
TVX_FMT_16_16 = 15
TVX_FMT_16_16_FLOAT = 16
TVX_FMT_8_24 = 17
TVX_FMT_8_24_FLOAT = 18
TVX_FMT_24_8 = 19
TVX_FMT_24_8_FLOAT = 20
TVX_FMT_10_11_11 = 21
TVX_FMT_10_11_11_FLOAT = 22
TVX_FMT_11_11_10 = 23
TVX_FMT_11_11_10_FLOAT = 24
TVX_FMT_2_10_10_10 = 25
TVX_FMT_8_8_8_8 = 26
TVX_FMT_10_10_10_2 = 27
TVX_FMT_X24_8_32_FLOAT = 28
TVX_FMT_32_32 = 29
TVX_FMT_32_32_FLOAT = 30
TVX_FMT_16_16_16_16 = 31
TVX_FMT_16_16_16_16_FLOAT = 32
TVX_FMT_RESERVED_33 = 33
TVX_FMT_32_32_32_32 = 34
TVX_FMT_32_32_32_32_FLOAT = 35
TVX_FMT_RESERVED_36 = 36
TVX_FMT_1 = 37
TVX_FMT_1_REVERSED = 38
TVX_FMT_GB_GR = 39
TVX_FMT_BG_RG = 40
TVX_FMT_32_AS_8 = 41
TVX_FMT_32_AS_8_8 = 42
TVX_FMT_5_9_9_9_SHAREDEXP = 43
TVX_FMT_8_8_8 = 44
TVX_FMT_16_16_16 = 45
TVX_FMT_16_16_16_FLOAT = 46
TVX_FMT_32_32_32 = 47
TVX_FMT_32_32_32_FLOAT = 48
TVX_FMT_BC1 = 49
TVX_FMT_BC2 = 50
TVX_FMT_BC3 = 51
TVX_FMT_BC4 = 52
TVX_FMT_BC5 = 53
TVX_FMT_APC0 = 54
TVX_FMT_APC1 = 55
TVX_FMT_APC2 = 56
TVX_FMT_APC3 = 57
TVX_FMT_APC4 = 58
TVX_FMT_APC5 = 59
TVX_FMT_APC6 = 60
TVX_FMT_APC7 = 61
TVX_FMT_CTX1 = 62
TVX_FMT_RESERVED_63 = 63
TVX_DATA_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'TVX_DST_SEL'
TVX_DST_SEL__enumvalues = {
0: 'TVX_DstSel_X',
1: 'TVX_DstSel_Y',
2: 'TVX_DstSel_Z',
3: 'TVX_DstSel_W',
4: 'TVX_DstSel_0f',
5: 'TVX_DstSel_1f',
6: 'TVX_DstSel_RESERVED_6',
7: 'TVX_DstSel_Mask',
}
TVX_DstSel_X = 0
TVX_DstSel_Y = 1
TVX_DstSel_Z = 2
TVX_DstSel_W = 3
TVX_DstSel_0f = 4
TVX_DstSel_1f = 5
TVX_DstSel_RESERVED_6 = 6
TVX_DstSel_Mask = 7
TVX_DST_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TVX_ENDIAN_SWAP'
TVX_ENDIAN_SWAP__enumvalues = {
0: 'TVX_EndianSwap_None',
1: 'TVX_EndianSwap_8in16',
2: 'TVX_EndianSwap_8in32',
3: 'TVX_EndianSwap_8in64',
}
TVX_EndianSwap_None = 0
TVX_EndianSwap_8in16 = 1
TVX_EndianSwap_8in32 = 2
TVX_EndianSwap_8in64 = 3
TVX_ENDIAN_SWAP = ctypes.c_uint32 # enum
# values for enumeration 'TVX_INST'
TVX_INST__enumvalues = {
0: 'TVX_Inst_NormalVertexFetch',
1: 'TVX_Inst_SemanticVertexFetch',
2: 'TVX_Inst_RESERVED_2',
3: 'TVX_Inst_LD',
4: 'TVX_Inst_GetTextureResInfo',
5: 'TVX_Inst_GetNumberOfSamples',
6: 'TVX_Inst_GetLOD',
7: 'TVX_Inst_GetGradientsH',
8: 'TVX_Inst_GetGradientsV',
9: 'TVX_Inst_SetTextureOffsets',
10: 'TVX_Inst_KeepGradients',
11: 'TVX_Inst_SetGradientsH',
12: 'TVX_Inst_SetGradientsV',
13: 'TVX_Inst_Pass',
14: 'TVX_Inst_GetBufferResInfo',
15: 'TVX_Inst_RESERVED_15',
16: 'TVX_Inst_Sample',
17: 'TVX_Inst_Sample_L',
18: 'TVX_Inst_Sample_LB',
19: 'TVX_Inst_Sample_LZ',
20: 'TVX_Inst_Sample_G',
21: 'TVX_Inst_Gather4',
22: 'TVX_Inst_Sample_G_LB',
23: 'TVX_Inst_Gather4_O',
24: 'TVX_Inst_Sample_C',
25: 'TVX_Inst_Sample_C_L',
26: 'TVX_Inst_Sample_C_LB',
27: 'TVX_Inst_Sample_C_LZ',
28: 'TVX_Inst_Sample_C_G',
29: 'TVX_Inst_Gather4_C',
30: 'TVX_Inst_Sample_C_G_LB',
31: 'TVX_Inst_Gather4_C_O',
}
TVX_Inst_NormalVertexFetch = 0
TVX_Inst_SemanticVertexFetch = 1
TVX_Inst_RESERVED_2 = 2
TVX_Inst_LD = 3
TVX_Inst_GetTextureResInfo = 4
TVX_Inst_GetNumberOfSamples = 5
TVX_Inst_GetLOD = 6
TVX_Inst_GetGradientsH = 7
TVX_Inst_GetGradientsV = 8
TVX_Inst_SetTextureOffsets = 9
TVX_Inst_KeepGradients = 10
TVX_Inst_SetGradientsH = 11
TVX_Inst_SetGradientsV = 12
TVX_Inst_Pass = 13
TVX_Inst_GetBufferResInfo = 14
TVX_Inst_RESERVED_15 = 15
TVX_Inst_Sample = 16
TVX_Inst_Sample_L = 17
TVX_Inst_Sample_LB = 18
TVX_Inst_Sample_LZ = 19
TVX_Inst_Sample_G = 20
TVX_Inst_Gather4 = 21
TVX_Inst_Sample_G_LB = 22
TVX_Inst_Gather4_O = 23
TVX_Inst_Sample_C = 24
TVX_Inst_Sample_C_L = 25
TVX_Inst_Sample_C_LB = 26
TVX_Inst_Sample_C_LZ = 27
TVX_Inst_Sample_C_G = 28
TVX_Inst_Gather4_C = 29
TVX_Inst_Sample_C_G_LB = 30
TVX_Inst_Gather4_C_O = 31
TVX_INST = ctypes.c_uint32 # enum
# values for enumeration 'TVX_NUM_FORMAT_ALL'
TVX_NUM_FORMAT_ALL__enumvalues = {
0: 'TVX_NumFormatAll_Norm',
1: 'TVX_NumFormatAll_Int',
2: 'TVX_NumFormatAll_Scaled',
3: 'TVX_NumFormatAll_RESERVED_3',
}
TVX_NumFormatAll_Norm = 0
TVX_NumFormatAll_Int = 1
TVX_NumFormatAll_Scaled = 2
TVX_NumFormatAll_RESERVED_3 = 3
TVX_NUM_FORMAT_ALL = ctypes.c_uint32 # enum
# values for enumeration 'TVX_SRC_SEL'
TVX_SRC_SEL__enumvalues = {
0: 'TVX_SrcSel_X',
1: 'TVX_SrcSel_Y',
2: 'TVX_SrcSel_Z',
3: 'TVX_SrcSel_W',
4: 'TVX_SrcSel_0f',
5: 'TVX_SrcSel_1f',
}
TVX_SrcSel_X = 0
TVX_SrcSel_Y = 1
TVX_SrcSel_Z = 2
TVX_SrcSel_W = 3
TVX_SrcSel_0f = 4
TVX_SrcSel_1f = 5
TVX_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TVX_SRF_MODE_ALL'
TVX_SRF_MODE_ALL__enumvalues = {
0: 'TVX_SRFModeAll_ZCMO',
1: 'TVX_SRFModeAll_NZ',
}
TVX_SRFModeAll_ZCMO = 0
TVX_SRFModeAll_NZ = 1
TVX_SRF_MODE_ALL = ctypes.c_uint32 # enum
# values for enumeration 'TVX_TYPE'
TVX_TYPE__enumvalues = {
0: 'TVX_Type_InvalidTextureResource',
1: 'TVX_Type_InvalidVertexBuffer',
2: 'TVX_Type_ValidTextureResource',
3: 'TVX_Type_ValidVertexBuffer',
}
TVX_Type_InvalidTextureResource = 0
TVX_Type_InvalidVertexBuffer = 1
TVX_Type_ValidTextureResource = 2
TVX_Type_ValidVertexBuffer = 3
TVX_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'PH_PERFCNT_SEL'
PH_PERFCNT_SEL__enumvalues = {
0: 'PH_SC0_SRPS_WINDOW_VALID',
1: 'PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
2: 'PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES',
3: 'PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
4: 'PH_SC0_ARB_STALLED_FROM_BELOW',
5: 'PH_SC0_ARB_STARVED_FROM_ABOVE',
6: 'PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
7: 'PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
8: 'PH_SC0_ARB_BUSY',
9: 'PH_SC0_ARB_PA_BUSY_SOP',
10: 'PH_SC0_ARB_EOP_POP_SYNC_POP',
11: 'PH_SC0_ARB_EVENT_SYNC_POP',
12: 'PH_SC0_PS_ENG_MULTICYCLE_BUBBLE',
13: 'PH_SC0_EOP_SYNC_WINDOW',
14: 'PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM',
15: 'PH_SC0_BUSY_CNT_NOT_ZERO',
16: 'PH_SC0_SEND',
17: 'PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND',
18: 'PH_SC0_CREDIT_AT_MAX',
19: 'PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND',
20: 'PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
21: 'PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION',
22: 'PH_SC0_GFX_PIPE0_TO_1_TRANSITION',
23: 'PH_SC0_GFX_PIPE1_TO_0_TRANSITION',
24: 'PH_SC0_PA0_DATA_FIFO_RD',
25: 'PH_SC0_PA0_DATA_FIFO_WE',
26: 'PH_SC0_PA0_FIFO_EMPTY',
27: 'PH_SC0_PA0_FIFO_FULL',
28: 'PH_SC0_PA0_NULL_WE',
29: 'PH_SC0_PA0_EVENT_WE',
30: 'PH_SC0_PA0_FPOV_WE',
31: 'PH_SC0_PA0_LPOV_WE',
32: 'PH_SC0_PA0_EOP_WE',
33: 'PH_SC0_PA0_DATA_FIFO_EOP_RD',
34: 'PH_SC0_PA0_EOPG_WE',
35: 'PH_SC0_PA0_DEALLOC_4_0_RD',
36: 'PH_SC0_PA1_DATA_FIFO_RD',
37: 'PH_SC0_PA1_DATA_FIFO_WE',
38: 'PH_SC0_PA1_FIFO_EMPTY',
39: 'PH_SC0_PA1_FIFO_FULL',
40: 'PH_SC0_PA1_NULL_WE',
41: 'PH_SC0_PA1_EVENT_WE',
42: 'PH_SC0_PA1_FPOV_WE',
43: 'PH_SC0_PA1_LPOV_WE',
44: 'PH_SC0_PA1_EOP_WE',
45: 'PH_SC0_PA1_DATA_FIFO_EOP_RD',
46: 'PH_SC0_PA1_EOPG_WE',
47: 'PH_SC0_PA1_DEALLOC_4_0_RD',
48: 'PH_SC0_PA2_DATA_FIFO_RD',
49: 'PH_SC0_PA2_DATA_FIFO_WE',
50: 'PH_SC0_PA2_FIFO_EMPTY',
51: 'PH_SC0_PA2_FIFO_FULL',
52: 'PH_SC0_PA2_NULL_WE',
53: 'PH_SC0_PA2_EVENT_WE',
54: 'PH_SC0_PA2_FPOV_WE',
55: 'PH_SC0_PA2_LPOV_WE',
56: 'PH_SC0_PA2_EOP_WE',
57: 'PH_SC0_PA2_DATA_FIFO_EOP_RD',
58: 'PH_SC0_PA2_EOPG_WE',
59: 'PH_SC0_PA2_DEALLOC_4_0_RD',
60: 'PH_SC0_PA3_DATA_FIFO_RD',
61: 'PH_SC0_PA3_DATA_FIFO_WE',
62: 'PH_SC0_PA3_FIFO_EMPTY',
63: 'PH_SC0_PA3_FIFO_FULL',
64: 'PH_SC0_PA3_NULL_WE',
65: 'PH_SC0_PA3_EVENT_WE',
66: 'PH_SC0_PA3_FPOV_WE',
67: 'PH_SC0_PA3_LPOV_WE',
68: 'PH_SC0_PA3_EOP_WE',
69: 'PH_SC0_PA3_DATA_FIFO_EOP_RD',
70: 'PH_SC0_PA3_EOPG_WE',
71: 'PH_SC0_PA3_DEALLOC_4_0_RD',
72: 'PH_SC0_PA4_DATA_FIFO_RD',
73: 'PH_SC0_PA4_DATA_FIFO_WE',
74: 'PH_SC0_PA4_FIFO_EMPTY',
75: 'PH_SC0_PA4_FIFO_FULL',
76: 'PH_SC0_PA4_NULL_WE',
77: 'PH_SC0_PA4_EVENT_WE',
78: 'PH_SC0_PA4_FPOV_WE',
79: 'PH_SC0_PA4_LPOV_WE',
80: 'PH_SC0_PA4_EOP_WE',
81: 'PH_SC0_PA4_DATA_FIFO_EOP_RD',
82: 'PH_SC0_PA4_EOPG_WE',
83: 'PH_SC0_PA4_DEALLOC_4_0_RD',
84: 'PH_SC0_PA5_DATA_FIFO_RD',
85: 'PH_SC0_PA5_DATA_FIFO_WE',
86: 'PH_SC0_PA5_FIFO_EMPTY',
87: 'PH_SC0_PA5_FIFO_FULL',
88: 'PH_SC0_PA5_NULL_WE',
89: 'PH_SC0_PA5_EVENT_WE',
90: 'PH_SC0_PA5_FPOV_WE',
91: 'PH_SC0_PA5_LPOV_WE',
92: 'PH_SC0_PA5_EOP_WE',
93: 'PH_SC0_PA5_DATA_FIFO_EOP_RD',
94: 'PH_SC0_PA5_EOPG_WE',
95: 'PH_SC0_PA5_DEALLOC_4_0_RD',
96: 'PH_SC0_PA6_DATA_FIFO_RD',
97: 'PH_SC0_PA6_DATA_FIFO_WE',
98: 'PH_SC0_PA6_FIFO_EMPTY',
99: 'PH_SC0_PA6_FIFO_FULL',
100: 'PH_SC0_PA6_NULL_WE',
101: 'PH_SC0_PA6_EVENT_WE',
102: 'PH_SC0_PA6_FPOV_WE',
103: 'PH_SC0_PA6_LPOV_WE',
104: 'PH_SC0_PA6_EOP_WE',
105: 'PH_SC0_PA6_DATA_FIFO_EOP_RD',
106: 'PH_SC0_PA6_EOPG_WE',
107: 'PH_SC0_PA6_DEALLOC_4_0_RD',
108: 'PH_SC0_PA7_DATA_FIFO_RD',
109: 'PH_SC0_PA7_DATA_FIFO_WE',
110: 'PH_SC0_PA7_FIFO_EMPTY',
111: 'PH_SC0_PA7_FIFO_FULL',
112: 'PH_SC0_PA7_NULL_WE',
113: 'PH_SC0_PA7_EVENT_WE',
114: 'PH_SC0_PA7_FPOV_WE',
115: 'PH_SC0_PA7_LPOV_WE',
116: 'PH_SC0_PA7_EOP_WE',
117: 'PH_SC0_PA7_DATA_FIFO_EOP_RD',
118: 'PH_SC0_PA7_EOPG_WE',
119: 'PH_SC0_PA7_DEALLOC_4_0_RD',
120: 'PH_SC1_SRPS_WINDOW_VALID',
121: 'PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
122: 'PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES',
123: 'PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
124: 'PH_SC1_ARB_STALLED_FROM_BELOW',
125: 'PH_SC1_ARB_STARVED_FROM_ABOVE',
126: 'PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
127: 'PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
128: 'PH_SC1_ARB_BUSY',
129: 'PH_SC1_ARB_PA_BUSY_SOP',
130: 'PH_SC1_ARB_EOP_POP_SYNC_POP',
131: 'PH_SC1_ARB_EVENT_SYNC_POP',
132: 'PH_SC1_PS_ENG_MULTICYCLE_BUBBLE',
133: 'PH_SC1_EOP_SYNC_WINDOW',
134: 'PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM',
135: 'PH_SC1_BUSY_CNT_NOT_ZERO',
136: 'PH_SC1_SEND',
137: 'PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND',
138: 'PH_SC1_CREDIT_AT_MAX',
139: 'PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND',
140: 'PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
141: 'PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
142: 'PH_SC1_GFX_PIPE0_TO_1_TRANSITION',
143: 'PH_SC1_GFX_PIPE1_TO_0_TRANSITION',
144: 'PH_SC1_PA0_DATA_FIFO_RD',
145: 'PH_SC1_PA0_DATA_FIFO_WE',
146: 'PH_SC1_PA0_FIFO_EMPTY',
147: 'PH_SC1_PA0_FIFO_FULL',
148: 'PH_SC1_PA0_NULL_WE',
149: 'PH_SC1_PA0_EVENT_WE',
150: 'PH_SC1_PA0_FPOV_WE',
151: 'PH_SC1_PA0_LPOV_WE',
152: 'PH_SC1_PA0_EOP_WE',
153: 'PH_SC1_PA0_DATA_FIFO_EOP_RD',
154: 'PH_SC1_PA0_EOPG_WE',
155: 'PH_SC1_PA0_DEALLOC_4_0_RD',
156: 'PH_SC1_PA1_DATA_FIFO_RD',
157: 'PH_SC1_PA1_DATA_FIFO_WE',
158: 'PH_SC1_PA1_FIFO_EMPTY',
159: 'PH_SC1_PA1_FIFO_FULL',
160: 'PH_SC1_PA1_NULL_WE',
161: 'PH_SC1_PA1_EVENT_WE',
162: 'PH_SC1_PA1_FPOV_WE',
163: 'PH_SC1_PA1_LPOV_WE',
164: 'PH_SC1_PA1_EOP_WE',
165: 'PH_SC1_PA1_DATA_FIFO_EOP_RD',
166: 'PH_SC1_PA1_EOPG_WE',
167: 'PH_SC1_PA1_DEALLOC_4_0_RD',
168: 'PH_SC1_PA2_DATA_FIFO_RD',
169: 'PH_SC1_PA2_DATA_FIFO_WE',
170: 'PH_SC1_PA2_FIFO_EMPTY',
171: 'PH_SC1_PA2_FIFO_FULL',
172: 'PH_SC1_PA2_NULL_WE',
173: 'PH_SC1_PA2_EVENT_WE',
174: 'PH_SC1_PA2_FPOV_WE',
175: 'PH_SC1_PA2_LPOV_WE',
176: 'PH_SC1_PA2_EOP_WE',
177: 'PH_SC1_PA2_DATA_FIFO_EOP_RD',
178: 'PH_SC1_PA2_EOPG_WE',
179: 'PH_SC1_PA2_DEALLOC_4_0_RD',
180: 'PH_SC1_PA3_DATA_FIFO_RD',
181: 'PH_SC1_PA3_DATA_FIFO_WE',
182: 'PH_SC1_PA3_FIFO_EMPTY',
183: 'PH_SC1_PA3_FIFO_FULL',
184: 'PH_SC1_PA3_NULL_WE',
185: 'PH_SC1_PA3_EVENT_WE',
186: 'PH_SC1_PA3_FPOV_WE',
187: 'PH_SC1_PA3_LPOV_WE',
188: 'PH_SC1_PA3_EOP_WE',
189: 'PH_SC1_PA3_DATA_FIFO_EOP_RD',
190: 'PH_SC1_PA3_EOPG_WE',
191: 'PH_SC1_PA3_DEALLOC_4_0_RD',
192: 'PH_SC1_PA4_DATA_FIFO_RD',
193: 'PH_SC1_PA4_DATA_FIFO_WE',
194: 'PH_SC1_PA4_FIFO_EMPTY',
195: 'PH_SC1_PA4_FIFO_FULL',
196: 'PH_SC1_PA4_NULL_WE',
197: 'PH_SC1_PA4_EVENT_WE',
198: 'PH_SC1_PA4_FPOV_WE',
199: 'PH_SC1_PA4_LPOV_WE',
200: 'PH_SC1_PA4_EOP_WE',
201: 'PH_SC1_PA4_DATA_FIFO_EOP_RD',
202: 'PH_SC1_PA4_EOPG_WE',
203: 'PH_SC1_PA4_DEALLOC_4_0_RD',
204: 'PH_SC1_PA5_DATA_FIFO_RD',
205: 'PH_SC1_PA5_DATA_FIFO_WE',
206: 'PH_SC1_PA5_FIFO_EMPTY',
207: 'PH_SC1_PA5_FIFO_FULL',
208: 'PH_SC1_PA5_NULL_WE',
209: 'PH_SC1_PA5_EVENT_WE',
210: 'PH_SC1_PA5_FPOV_WE',
211: 'PH_SC1_PA5_LPOV_WE',
212: 'PH_SC1_PA5_EOP_WE',
213: 'PH_SC1_PA5_DATA_FIFO_EOP_RD',
214: 'PH_SC1_PA5_EOPG_WE',
215: 'PH_SC1_PA5_DEALLOC_4_0_RD',
216: 'PH_SC1_PA6_DATA_FIFO_RD',
217: 'PH_SC1_PA6_DATA_FIFO_WE',
218: 'PH_SC1_PA6_FIFO_EMPTY',
219: 'PH_SC1_PA6_FIFO_FULL',
220: 'PH_SC1_PA6_NULL_WE',
221: 'PH_SC1_PA6_EVENT_WE',
222: 'PH_SC1_PA6_FPOV_WE',
223: 'PH_SC1_PA6_LPOV_WE',
224: 'PH_SC1_PA6_EOP_WE',
225: 'PH_SC1_PA6_DATA_FIFO_EOP_RD',
226: 'PH_SC1_PA6_EOPG_WE',
227: 'PH_SC1_PA6_DEALLOC_4_0_RD',
228: 'PH_SC1_PA7_DATA_FIFO_RD',
229: 'PH_SC1_PA7_DATA_FIFO_WE',
230: 'PH_SC1_PA7_FIFO_EMPTY',
231: 'PH_SC1_PA7_FIFO_FULL',
232: 'PH_SC1_PA7_NULL_WE',
233: 'PH_SC1_PA7_EVENT_WE',
234: 'PH_SC1_PA7_FPOV_WE',
235: 'PH_SC1_PA7_LPOV_WE',
236: 'PH_SC1_PA7_EOP_WE',
237: 'PH_SC1_PA7_DATA_FIFO_EOP_RD',
238: 'PH_SC1_PA7_EOPG_WE',
239: 'PH_SC1_PA7_DEALLOC_4_0_RD',
240: 'PH_SC2_SRPS_WINDOW_VALID',
241: 'PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
242: 'PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES',
243: 'PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
244: 'PH_SC2_ARB_STALLED_FROM_BELOW',
245: 'PH_SC2_ARB_STARVED_FROM_ABOVE',
246: 'PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
247: 'PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
248: 'PH_SC2_ARB_BUSY',
249: 'PH_SC2_ARB_PA_BUSY_SOP',
250: 'PH_SC2_ARB_EOP_POP_SYNC_POP',
251: 'PH_SC2_ARB_EVENT_SYNC_POP',
252: 'PH_SC2_PS_ENG_MULTICYCLE_BUBBLE',
253: 'PH_SC2_EOP_SYNC_WINDOW',
254: 'PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM',
255: 'PH_SC2_BUSY_CNT_NOT_ZERO',
256: 'PH_SC2_SEND',
257: 'PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND',
258: 'PH_SC2_CREDIT_AT_MAX',
259: 'PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND',
260: 'PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
261: 'PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
262: 'PH_SC2_GFX_PIPE0_TO_1_TRANSITION',
263: 'PH_SC2_GFX_PIPE1_TO_0_TRANSITION',
264: 'PH_SC2_PA0_DATA_FIFO_RD',
265: 'PH_SC2_PA0_DATA_FIFO_WE',
266: 'PH_SC2_PA0_FIFO_EMPTY',
267: 'PH_SC2_PA0_FIFO_FULL',
268: 'PH_SC2_PA0_NULL_WE',
269: 'PH_SC2_PA0_EVENT_WE',
270: 'PH_SC2_PA0_FPOV_WE',
271: 'PH_SC2_PA0_LPOV_WE',
272: 'PH_SC2_PA0_EOP_WE',
273: 'PH_SC2_PA0_DATA_FIFO_EOP_RD',
274: 'PH_SC2_PA0_EOPG_WE',
275: 'PH_SC2_PA0_DEALLOC_4_0_RD',
276: 'PH_SC2_PA1_DATA_FIFO_RD',
277: 'PH_SC2_PA1_DATA_FIFO_WE',
278: 'PH_SC2_PA1_FIFO_EMPTY',
279: 'PH_SC2_PA1_FIFO_FULL',
280: 'PH_SC2_PA1_NULL_WE',
281: 'PH_SC2_PA1_EVENT_WE',
282: 'PH_SC2_PA1_FPOV_WE',
283: 'PH_SC2_PA1_LPOV_WE',
284: 'PH_SC2_PA1_EOP_WE',
285: 'PH_SC2_PA1_DATA_FIFO_EOP_RD',
286: 'PH_SC2_PA1_EOPG_WE',
287: 'PH_SC2_PA1_DEALLOC_4_0_RD',
288: 'PH_SC2_PA2_DATA_FIFO_RD',
289: 'PH_SC2_PA2_DATA_FIFO_WE',
290: 'PH_SC2_PA2_FIFO_EMPTY',
291: 'PH_SC2_PA2_FIFO_FULL',
292: 'PH_SC2_PA2_NULL_WE',
293: 'PH_SC2_PA2_EVENT_WE',
294: 'PH_SC2_PA2_FPOV_WE',
295: 'PH_SC2_PA2_LPOV_WE',
296: 'PH_SC2_PA2_EOP_WE',
297: 'PH_SC2_PA2_DATA_FIFO_EOP_RD',
298: 'PH_SC2_PA2_EOPG_WE',
299: 'PH_SC2_PA2_DEALLOC_4_0_RD',
300: 'PH_SC2_PA3_DATA_FIFO_RD',
301: 'PH_SC2_PA3_DATA_FIFO_WE',
302: 'PH_SC2_PA3_FIFO_EMPTY',
303: 'PH_SC2_PA3_FIFO_FULL',
304: 'PH_SC2_PA3_NULL_WE',
305: 'PH_SC2_PA3_EVENT_WE',
306: 'PH_SC2_PA3_FPOV_WE',
307: 'PH_SC2_PA3_LPOV_WE',
308: 'PH_SC2_PA3_EOP_WE',
309: 'PH_SC2_PA3_DATA_FIFO_EOP_RD',
310: 'PH_SC2_PA3_EOPG_WE',
311: 'PH_SC2_PA3_DEALLOC_4_0_RD',
312: 'PH_SC2_PA4_DATA_FIFO_RD',
313: 'PH_SC2_PA4_DATA_FIFO_WE',
314: 'PH_SC2_PA4_FIFO_EMPTY',
315: 'PH_SC2_PA4_FIFO_FULL',
316: 'PH_SC2_PA4_NULL_WE',
317: 'PH_SC2_PA4_EVENT_WE',
318: 'PH_SC2_PA4_FPOV_WE',
319: 'PH_SC2_PA4_LPOV_WE',
320: 'PH_SC2_PA4_EOP_WE',
321: 'PH_SC2_PA4_DATA_FIFO_EOP_RD',
322: 'PH_SC2_PA4_EOPG_WE',
323: 'PH_SC2_PA4_DEALLOC_4_0_RD',
324: 'PH_SC2_PA5_DATA_FIFO_RD',
325: 'PH_SC2_PA5_DATA_FIFO_WE',
326: 'PH_SC2_PA5_FIFO_EMPTY',
327: 'PH_SC2_PA5_FIFO_FULL',
328: 'PH_SC2_PA5_NULL_WE',
329: 'PH_SC2_PA5_EVENT_WE',
330: 'PH_SC2_PA5_FPOV_WE',
331: 'PH_SC2_PA5_LPOV_WE',
332: 'PH_SC2_PA5_EOP_WE',
333: 'PH_SC2_PA5_DATA_FIFO_EOP_RD',
334: 'PH_SC2_PA5_EOPG_WE',
335: 'PH_SC2_PA5_DEALLOC_4_0_RD',
336: 'PH_SC2_PA6_DATA_FIFO_RD',
337: 'PH_SC2_PA6_DATA_FIFO_WE',
338: 'PH_SC2_PA6_FIFO_EMPTY',
339: 'PH_SC2_PA6_FIFO_FULL',
340: 'PH_SC2_PA6_NULL_WE',
341: 'PH_SC2_PA6_EVENT_WE',
342: 'PH_SC2_PA6_FPOV_WE',
343: 'PH_SC2_PA6_LPOV_WE',
344: 'PH_SC2_PA6_EOP_WE',
345: 'PH_SC2_PA6_DATA_FIFO_EOP_RD',
346: 'PH_SC2_PA6_EOPG_WE',
347: 'PH_SC2_PA6_DEALLOC_4_0_RD',
348: 'PH_SC2_PA7_DATA_FIFO_RD',
349: 'PH_SC2_PA7_DATA_FIFO_WE',
350: 'PH_SC2_PA7_FIFO_EMPTY',
351: 'PH_SC2_PA7_FIFO_FULL',
352: 'PH_SC2_PA7_NULL_WE',
353: 'PH_SC2_PA7_EVENT_WE',
354: 'PH_SC2_PA7_FPOV_WE',
355: 'PH_SC2_PA7_LPOV_WE',
356: 'PH_SC2_PA7_EOP_WE',
357: 'PH_SC2_PA7_DATA_FIFO_EOP_RD',
358: 'PH_SC2_PA7_EOPG_WE',
359: 'PH_SC2_PA7_DEALLOC_4_0_RD',
360: 'PH_SC3_SRPS_WINDOW_VALID',
361: 'PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
362: 'PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES',
363: 'PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
364: 'PH_SC3_ARB_STALLED_FROM_BELOW',
365: 'PH_SC3_ARB_STARVED_FROM_ABOVE',
366: 'PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
367: 'PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
368: 'PH_SC3_ARB_BUSY',
369: 'PH_SC3_ARB_PA_BUSY_SOP',
370: 'PH_SC3_ARB_EOP_POP_SYNC_POP',
371: 'PH_SC3_ARB_EVENT_SYNC_POP',
372: 'PH_SC3_PS_ENG_MULTICYCLE_BUBBLE',
373: 'PH_SC3_EOP_SYNC_WINDOW',
374: 'PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM',
375: 'PH_SC3_BUSY_CNT_NOT_ZERO',
376: 'PH_SC3_SEND',
377: 'PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND',
378: 'PH_SC3_CREDIT_AT_MAX',
379: 'PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND',
380: 'PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
381: 'PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
382: 'PH_SC3_GFX_PIPE0_TO_1_TRANSITION',
383: 'PH_SC3_GFX_PIPE1_TO_0_TRANSITION',
384: 'PH_SC3_PA0_DATA_FIFO_RD',
385: 'PH_SC3_PA0_DATA_FIFO_WE',
386: 'PH_SC3_PA0_FIFO_EMPTY',
387: 'PH_SC3_PA0_FIFO_FULL',
388: 'PH_SC3_PA0_NULL_WE',
389: 'PH_SC3_PA0_EVENT_WE',
390: 'PH_SC3_PA0_FPOV_WE',
391: 'PH_SC3_PA0_LPOV_WE',
392: 'PH_SC3_PA0_EOP_WE',
393: 'PH_SC3_PA0_DATA_FIFO_EOP_RD',
394: 'PH_SC3_PA0_EOPG_WE',
395: 'PH_SC3_PA0_DEALLOC_4_0_RD',
396: 'PH_SC3_PA1_DATA_FIFO_RD',
397: 'PH_SC3_PA1_DATA_FIFO_WE',
398: 'PH_SC3_PA1_FIFO_EMPTY',
399: 'PH_SC3_PA1_FIFO_FULL',
400: 'PH_SC3_PA1_NULL_WE',
401: 'PH_SC3_PA1_EVENT_WE',
402: 'PH_SC3_PA1_FPOV_WE',
403: 'PH_SC3_PA1_LPOV_WE',
404: 'PH_SC3_PA1_EOP_WE',
405: 'PH_SC3_PA1_DATA_FIFO_EOP_RD',
406: 'PH_SC3_PA1_EOPG_WE',
407: 'PH_SC3_PA1_DEALLOC_4_0_RD',
408: 'PH_SC3_PA2_DATA_FIFO_RD',
409: 'PH_SC3_PA2_DATA_FIFO_WE',
410: 'PH_SC3_PA2_FIFO_EMPTY',
411: 'PH_SC3_PA2_FIFO_FULL',
412: 'PH_SC3_PA2_NULL_WE',
413: 'PH_SC3_PA2_EVENT_WE',
414: 'PH_SC3_PA2_FPOV_WE',
415: 'PH_SC3_PA2_LPOV_WE',
416: 'PH_SC3_PA2_EOP_WE',
417: 'PH_SC3_PA2_DATA_FIFO_EOP_RD',
418: 'PH_SC3_PA2_EOPG_WE',
419: 'PH_SC3_PA2_DEALLOC_4_0_RD',
420: 'PH_SC3_PA3_DATA_FIFO_RD',
421: 'PH_SC3_PA3_DATA_FIFO_WE',
422: 'PH_SC3_PA3_FIFO_EMPTY',
423: 'PH_SC3_PA3_FIFO_FULL',
424: 'PH_SC3_PA3_NULL_WE',
425: 'PH_SC3_PA3_EVENT_WE',
426: 'PH_SC3_PA3_FPOV_WE',
427: 'PH_SC3_PA3_LPOV_WE',
428: 'PH_SC3_PA3_EOP_WE',
429: 'PH_SC3_PA3_DATA_FIFO_EOP_RD',
430: 'PH_SC3_PA3_EOPG_WE',
431: 'PH_SC3_PA3_DEALLOC_4_0_RD',
432: 'PH_SC3_PA4_DATA_FIFO_RD',
433: 'PH_SC3_PA4_DATA_FIFO_WE',
434: 'PH_SC3_PA4_FIFO_EMPTY',
435: 'PH_SC3_PA4_FIFO_FULL',
436: 'PH_SC3_PA4_NULL_WE',
437: 'PH_SC3_PA4_EVENT_WE',
438: 'PH_SC3_PA4_FPOV_WE',
439: 'PH_SC3_PA4_LPOV_WE',
440: 'PH_SC3_PA4_EOP_WE',
441: 'PH_SC3_PA4_DATA_FIFO_EOP_RD',
442: 'PH_SC3_PA4_EOPG_WE',
443: 'PH_SC3_PA4_DEALLOC_4_0_RD',
444: 'PH_SC3_PA5_DATA_FIFO_RD',
445: 'PH_SC3_PA5_DATA_FIFO_WE',
446: 'PH_SC3_PA5_FIFO_EMPTY',
447: 'PH_SC3_PA5_FIFO_FULL',
448: 'PH_SC3_PA5_NULL_WE',
449: 'PH_SC3_PA5_EVENT_WE',
450: 'PH_SC3_PA5_FPOV_WE',
451: 'PH_SC3_PA5_LPOV_WE',
452: 'PH_SC3_PA5_EOP_WE',
453: 'PH_SC3_PA5_DATA_FIFO_EOP_RD',
454: 'PH_SC3_PA5_EOPG_WE',
455: 'PH_SC3_PA5_DEALLOC_4_0_RD',
456: 'PH_SC3_PA6_DATA_FIFO_RD',
457: 'PH_SC3_PA6_DATA_FIFO_WE',
458: 'PH_SC3_PA6_FIFO_EMPTY',
459: 'PH_SC3_PA6_FIFO_FULL',
460: 'PH_SC3_PA6_NULL_WE',
461: 'PH_SC3_PA6_EVENT_WE',
462: 'PH_SC3_PA6_FPOV_WE',
463: 'PH_SC3_PA6_LPOV_WE',
464: 'PH_SC3_PA6_EOP_WE',
465: 'PH_SC3_PA6_DATA_FIFO_EOP_RD',
466: 'PH_SC3_PA6_EOPG_WE',
467: 'PH_SC3_PA6_DEALLOC_4_0_RD',
468: 'PH_SC3_PA7_DATA_FIFO_RD',
469: 'PH_SC3_PA7_DATA_FIFO_WE',
470: 'PH_SC3_PA7_FIFO_EMPTY',
471: 'PH_SC3_PA7_FIFO_FULL',
472: 'PH_SC3_PA7_NULL_WE',
473: 'PH_SC3_PA7_EVENT_WE',
474: 'PH_SC3_PA7_FPOV_WE',
475: 'PH_SC3_PA7_LPOV_WE',
476: 'PH_SC3_PA7_EOP_WE',
477: 'PH_SC3_PA7_DATA_FIFO_EOP_RD',
478: 'PH_SC3_PA7_EOPG_WE',
479: 'PH_SC3_PA7_DEALLOC_4_0_RD',
480: 'PH_SC4_SRPS_WINDOW_VALID',
481: 'PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
482: 'PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES',
483: 'PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
484: 'PH_SC4_ARB_STALLED_FROM_BELOW',
485: 'PH_SC4_ARB_STARVED_FROM_ABOVE',
486: 'PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
487: 'PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
488: 'PH_SC4_ARB_BUSY',
489: 'PH_SC4_ARB_PA_BUSY_SOP',
490: 'PH_SC4_ARB_EOP_POP_SYNC_POP',
491: 'PH_SC4_ARB_EVENT_SYNC_POP',
492: 'PH_SC4_PS_ENG_MULTICYCLE_BUBBLE',
493: 'PH_SC4_EOP_SYNC_WINDOW',
494: 'PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM',
495: 'PH_SC4_BUSY_CNT_NOT_ZERO',
496: 'PH_SC4_SEND',
497: 'PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND',
498: 'PH_SC4_CREDIT_AT_MAX',
499: 'PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND',
500: 'PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
501: 'PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
502: 'PH_SC4_GFX_PIPE0_TO_1_TRANSITION',
503: 'PH_SC4_GFX_PIPE1_TO_0_TRANSITION',
504: 'PH_SC4_PA0_DATA_FIFO_RD',
505: 'PH_SC4_PA0_DATA_FIFO_WE',
506: 'PH_SC4_PA0_FIFO_EMPTY',
507: 'PH_SC4_PA0_FIFO_FULL',
508: 'PH_SC4_PA0_NULL_WE',
509: 'PH_SC4_PA0_EVENT_WE',
510: 'PH_SC4_PA0_FPOV_WE',
511: 'PH_SC4_PA0_LPOV_WE',
512: 'PH_SC4_PA0_EOP_WE',
513: 'PH_SC4_PA0_DATA_FIFO_EOP_RD',
514: 'PH_SC4_PA0_EOPG_WE',
515: 'PH_SC4_PA0_DEALLOC_4_0_RD',
516: 'PH_SC4_PA1_DATA_FIFO_RD',
517: 'PH_SC4_PA1_DATA_FIFO_WE',
518: 'PH_SC4_PA1_FIFO_EMPTY',
519: 'PH_SC4_PA1_FIFO_FULL',
520: 'PH_SC4_PA1_NULL_WE',
521: 'PH_SC4_PA1_EVENT_WE',
522: 'PH_SC4_PA1_FPOV_WE',
523: 'PH_SC4_PA1_LPOV_WE',
524: 'PH_SC4_PA1_EOP_WE',
525: 'PH_SC4_PA1_DATA_FIFO_EOP_RD',
526: 'PH_SC4_PA1_EOPG_WE',
527: 'PH_SC4_PA1_DEALLOC_4_0_RD',
528: 'PH_SC4_PA2_DATA_FIFO_RD',
529: 'PH_SC4_PA2_DATA_FIFO_WE',
530: 'PH_SC4_PA2_FIFO_EMPTY',
531: 'PH_SC4_PA2_FIFO_FULL',
532: 'PH_SC4_PA2_NULL_WE',
533: 'PH_SC4_PA2_EVENT_WE',
534: 'PH_SC4_PA2_FPOV_WE',
535: 'PH_SC4_PA2_LPOV_WE',
536: 'PH_SC4_PA2_EOP_WE',
537: 'PH_SC4_PA2_DATA_FIFO_EOP_RD',
538: 'PH_SC4_PA2_EOPG_WE',
539: 'PH_SC4_PA2_DEALLOC_4_0_RD',
540: 'PH_SC4_PA3_DATA_FIFO_RD',
541: 'PH_SC4_PA3_DATA_FIFO_WE',
542: 'PH_SC4_PA3_FIFO_EMPTY',
543: 'PH_SC4_PA3_FIFO_FULL',
544: 'PH_SC4_PA3_NULL_WE',
545: 'PH_SC4_PA3_EVENT_WE',
546: 'PH_SC4_PA3_FPOV_WE',
547: 'PH_SC4_PA3_LPOV_WE',
548: 'PH_SC4_PA3_EOP_WE',
549: 'PH_SC4_PA3_DATA_FIFO_EOP_RD',
550: 'PH_SC4_PA3_EOPG_WE',
551: 'PH_SC4_PA3_DEALLOC_4_0_RD',
552: 'PH_SC4_PA4_DATA_FIFO_RD',
553: 'PH_SC4_PA4_DATA_FIFO_WE',
554: 'PH_SC4_PA4_FIFO_EMPTY',
555: 'PH_SC4_PA4_FIFO_FULL',
556: 'PH_SC4_PA4_NULL_WE',
557: 'PH_SC4_PA4_EVENT_WE',
558: 'PH_SC4_PA4_FPOV_WE',
559: 'PH_SC4_PA4_LPOV_WE',
560: 'PH_SC4_PA4_EOP_WE',
561: 'PH_SC4_PA4_DATA_FIFO_EOP_RD',
562: 'PH_SC4_PA4_EOPG_WE',
563: 'PH_SC4_PA4_DEALLOC_4_0_RD',
564: 'PH_SC4_PA5_DATA_FIFO_RD',
565: 'PH_SC4_PA5_DATA_FIFO_WE',
566: 'PH_SC4_PA5_FIFO_EMPTY',
567: 'PH_SC4_PA5_FIFO_FULL',
568: 'PH_SC4_PA5_NULL_WE',
569: 'PH_SC4_PA5_EVENT_WE',
570: 'PH_SC4_PA5_FPOV_WE',
571: 'PH_SC4_PA5_LPOV_WE',
572: 'PH_SC4_PA5_EOP_WE',
573: 'PH_SC4_PA5_DATA_FIFO_EOP_RD',
574: 'PH_SC4_PA5_EOPG_WE',
575: 'PH_SC4_PA5_DEALLOC_4_0_RD',
576: 'PH_SC4_PA6_DATA_FIFO_RD',
577: 'PH_SC4_PA6_DATA_FIFO_WE',
578: 'PH_SC4_PA6_FIFO_EMPTY',
579: 'PH_SC4_PA6_FIFO_FULL',
580: 'PH_SC4_PA6_NULL_WE',
581: 'PH_SC4_PA6_EVENT_WE',
582: 'PH_SC4_PA6_FPOV_WE',
583: 'PH_SC4_PA6_LPOV_WE',
584: 'PH_SC4_PA6_EOP_WE',
585: 'PH_SC4_PA6_DATA_FIFO_EOP_RD',
586: 'PH_SC4_PA6_EOPG_WE',
587: 'PH_SC4_PA6_DEALLOC_4_0_RD',
588: 'PH_SC4_PA7_DATA_FIFO_RD',
589: 'PH_SC4_PA7_DATA_FIFO_WE',
590: 'PH_SC4_PA7_FIFO_EMPTY',
591: 'PH_SC4_PA7_FIFO_FULL',
592: 'PH_SC4_PA7_NULL_WE',
593: 'PH_SC4_PA7_EVENT_WE',
594: 'PH_SC4_PA7_FPOV_WE',
595: 'PH_SC4_PA7_LPOV_WE',
596: 'PH_SC4_PA7_EOP_WE',
597: 'PH_SC4_PA7_DATA_FIFO_EOP_RD',
598: 'PH_SC4_PA7_EOPG_WE',
599: 'PH_SC4_PA7_DEALLOC_4_0_RD',
600: 'PH_SC5_SRPS_WINDOW_VALID',
601: 'PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
602: 'PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES',
603: 'PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
604: 'PH_SC5_ARB_STALLED_FROM_BELOW',
605: 'PH_SC5_ARB_STARVED_FROM_ABOVE',
606: 'PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
607: 'PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
608: 'PH_SC5_ARB_BUSY',
609: 'PH_SC5_ARB_PA_BUSY_SOP',
610: 'PH_SC5_ARB_EOP_POP_SYNC_POP',
611: 'PH_SC5_ARB_EVENT_SYNC_POP',
612: 'PH_SC5_PS_ENG_MULTICYCLE_BUBBLE',
613: 'PH_SC5_EOP_SYNC_WINDOW',
614: 'PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM',
615: 'PH_SC5_BUSY_CNT_NOT_ZERO',
616: 'PH_SC5_SEND',
617: 'PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND',
618: 'PH_SC5_CREDIT_AT_MAX',
619: 'PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND',
620: 'PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
621: 'PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
622: 'PH_SC5_GFX_PIPE0_TO_1_TRANSITION',
623: 'PH_SC5_GFX_PIPE1_TO_0_TRANSITION',
624: 'PH_SC5_PA0_DATA_FIFO_RD',
625: 'PH_SC5_PA0_DATA_FIFO_WE',
626: 'PH_SC5_PA0_FIFO_EMPTY',
627: 'PH_SC5_PA0_FIFO_FULL',
628: 'PH_SC5_PA0_NULL_WE',
629: 'PH_SC5_PA0_EVENT_WE',
630: 'PH_SC5_PA0_FPOV_WE',
631: 'PH_SC5_PA0_LPOV_WE',
632: 'PH_SC5_PA0_EOP_WE',
633: 'PH_SC5_PA0_DATA_FIFO_EOP_RD',
634: 'PH_SC5_PA0_EOPG_WE',
635: 'PH_SC5_PA0_DEALLOC_4_0_RD',
636: 'PH_SC5_PA1_DATA_FIFO_RD',
637: 'PH_SC5_PA1_DATA_FIFO_WE',
638: 'PH_SC5_PA1_FIFO_EMPTY',
639: 'PH_SC5_PA1_FIFO_FULL',
640: 'PH_SC5_PA1_NULL_WE',
641: 'PH_SC5_PA1_EVENT_WE',
642: 'PH_SC5_PA1_FPOV_WE',
643: 'PH_SC5_PA1_LPOV_WE',
644: 'PH_SC5_PA1_EOP_WE',
645: 'PH_SC5_PA1_DATA_FIFO_EOP_RD',
646: 'PH_SC5_PA1_EOPG_WE',
647: 'PH_SC5_PA1_DEALLOC_4_0_RD',
648: 'PH_SC5_PA2_DATA_FIFO_RD',
649: 'PH_SC5_PA2_DATA_FIFO_WE',
650: 'PH_SC5_PA2_FIFO_EMPTY',
651: 'PH_SC5_PA2_FIFO_FULL',
652: 'PH_SC5_PA2_NULL_WE',
653: 'PH_SC5_PA2_EVENT_WE',
654: 'PH_SC5_PA2_FPOV_WE',
655: 'PH_SC5_PA2_LPOV_WE',
656: 'PH_SC5_PA2_EOP_WE',
657: 'PH_SC5_PA2_DATA_FIFO_EOP_RD',
658: 'PH_SC5_PA2_EOPG_WE',
659: 'PH_SC5_PA2_DEALLOC_4_0_RD',
660: 'PH_SC5_PA3_DATA_FIFO_RD',
661: 'PH_SC5_PA3_DATA_FIFO_WE',
662: 'PH_SC5_PA3_FIFO_EMPTY',
663: 'PH_SC5_PA3_FIFO_FULL',
664: 'PH_SC5_PA3_NULL_WE',
665: 'PH_SC5_PA3_EVENT_WE',
666: 'PH_SC5_PA3_FPOV_WE',
667: 'PH_SC5_PA3_LPOV_WE',
668: 'PH_SC5_PA3_EOP_WE',
669: 'PH_SC5_PA3_DATA_FIFO_EOP_RD',
670: 'PH_SC5_PA3_EOPG_WE',
671: 'PH_SC5_PA3_DEALLOC_4_0_RD',
672: 'PH_SC5_PA4_DATA_FIFO_RD',
673: 'PH_SC5_PA4_DATA_FIFO_WE',
674: 'PH_SC5_PA4_FIFO_EMPTY',
675: 'PH_SC5_PA4_FIFO_FULL',
676: 'PH_SC5_PA4_NULL_WE',
677: 'PH_SC5_PA4_EVENT_WE',
678: 'PH_SC5_PA4_FPOV_WE',
679: 'PH_SC5_PA4_LPOV_WE',
680: 'PH_SC5_PA4_EOP_WE',
681: 'PH_SC5_PA4_DATA_FIFO_EOP_RD',
682: 'PH_SC5_PA4_EOPG_WE',
683: 'PH_SC5_PA4_DEALLOC_4_0_RD',
684: 'PH_SC5_PA5_DATA_FIFO_RD',
685: 'PH_SC5_PA5_DATA_FIFO_WE',
686: 'PH_SC5_PA5_FIFO_EMPTY',
687: 'PH_SC5_PA5_FIFO_FULL',
688: 'PH_SC5_PA5_NULL_WE',
689: 'PH_SC5_PA5_EVENT_WE',
690: 'PH_SC5_PA5_FPOV_WE',
691: 'PH_SC5_PA5_LPOV_WE',
692: 'PH_SC5_PA5_EOP_WE',
693: 'PH_SC5_PA5_DATA_FIFO_EOP_RD',
694: 'PH_SC5_PA5_EOPG_WE',
695: 'PH_SC5_PA5_DEALLOC_4_0_RD',
696: 'PH_SC5_PA6_DATA_FIFO_RD',
697: 'PH_SC5_PA6_DATA_FIFO_WE',
698: 'PH_SC5_PA6_FIFO_EMPTY',
699: 'PH_SC5_PA6_FIFO_FULL',
700: 'PH_SC5_PA6_NULL_WE',
701: 'PH_SC5_PA6_EVENT_WE',
702: 'PH_SC5_PA6_FPOV_WE',
703: 'PH_SC5_PA6_LPOV_WE',
704: 'PH_SC5_PA6_EOP_WE',
705: 'PH_SC5_PA6_DATA_FIFO_EOP_RD',
706: 'PH_SC5_PA6_EOPG_WE',
707: 'PH_SC5_PA6_DEALLOC_4_0_RD',
708: 'PH_SC5_PA7_DATA_FIFO_RD',
709: 'PH_SC5_PA7_DATA_FIFO_WE',
710: 'PH_SC5_PA7_FIFO_EMPTY',
711: 'PH_SC5_PA7_FIFO_FULL',
712: 'PH_SC5_PA7_NULL_WE',
713: 'PH_SC5_PA7_EVENT_WE',
714: 'PH_SC5_PA7_FPOV_WE',
715: 'PH_SC5_PA7_LPOV_WE',
716: 'PH_SC5_PA7_EOP_WE',
717: 'PH_SC5_PA7_DATA_FIFO_EOP_RD',
718: 'PH_SC5_PA7_EOPG_WE',
719: 'PH_SC5_PA7_DEALLOC_4_0_RD',
720: 'PH_SC6_SRPS_WINDOW_VALID',
721: 'PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
722: 'PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES',
723: 'PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
724: 'PH_SC6_ARB_STALLED_FROM_BELOW',
725: 'PH_SC6_ARB_STARVED_FROM_ABOVE',
726: 'PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
727: 'PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
728: 'PH_SC6_ARB_BUSY',
729: 'PH_SC6_ARB_PA_BUSY_SOP',
730: 'PH_SC6_ARB_EOP_POP_SYNC_POP',
731: 'PH_SC6_ARB_EVENT_SYNC_POP',
732: 'PH_SC6_PS_ENG_MULTICYCLE_BUBBLE',
733: 'PH_SC6_EOP_SYNC_WINDOW',
734: 'PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM',
735: 'PH_SC6_BUSY_CNT_NOT_ZERO',
736: 'PH_SC6_SEND',
737: 'PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND',
738: 'PH_SC6_CREDIT_AT_MAX',
739: 'PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND',
740: 'PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
741: 'PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
742: 'PH_SC6_GFX_PIPE0_TO_1_TRANSITION',
743: 'PH_SC6_GFX_PIPE1_TO_0_TRANSITION',
744: 'PH_SC6_PA0_DATA_FIFO_RD',
745: 'PH_SC6_PA0_DATA_FIFO_WE',
746: 'PH_SC6_PA0_FIFO_EMPTY',
747: 'PH_SC6_PA0_FIFO_FULL',
748: 'PH_SC6_PA0_NULL_WE',
749: 'PH_SC6_PA0_EVENT_WE',
750: 'PH_SC6_PA0_FPOV_WE',
751: 'PH_SC6_PA0_LPOV_WE',
752: 'PH_SC6_PA0_EOP_WE',
753: 'PH_SC6_PA0_DATA_FIFO_EOP_RD',
754: 'PH_SC6_PA0_EOPG_WE',
755: 'PH_SC6_PA0_DEALLOC_4_0_RD',
756: 'PH_SC6_PA1_DATA_FIFO_RD',
757: 'PH_SC6_PA1_DATA_FIFO_WE',
758: 'PH_SC6_PA1_FIFO_EMPTY',
759: 'PH_SC6_PA1_FIFO_FULL',
760: 'PH_SC6_PA1_NULL_WE',
761: 'PH_SC6_PA1_EVENT_WE',
762: 'PH_SC6_PA1_FPOV_WE',
763: 'PH_SC6_PA1_LPOV_WE',
764: 'PH_SC6_PA1_EOP_WE',
765: 'PH_SC6_PA1_DATA_FIFO_EOP_RD',
766: 'PH_SC6_PA1_EOPG_WE',
767: 'PH_SC6_PA1_DEALLOC_4_0_RD',
768: 'PH_SC6_PA2_DATA_FIFO_RD',
769: 'PH_SC6_PA2_DATA_FIFO_WE',
770: 'PH_SC6_PA2_FIFO_EMPTY',
771: 'PH_SC6_PA2_FIFO_FULL',
772: 'PH_SC6_PA2_NULL_WE',
773: 'PH_SC6_PA2_EVENT_WE',
774: 'PH_SC6_PA2_FPOV_WE',
775: 'PH_SC6_PA2_LPOV_WE',
776: 'PH_SC6_PA2_EOP_WE',
777: 'PH_SC6_PA2_DATA_FIFO_EOP_RD',
778: 'PH_SC6_PA2_EOPG_WE',
779: 'PH_SC6_PA2_DEALLOC_4_0_RD',
780: 'PH_SC6_PA3_DATA_FIFO_RD',
781: 'PH_SC6_PA3_DATA_FIFO_WE',
782: 'PH_SC6_PA3_FIFO_EMPTY',
783: 'PH_SC6_PA3_FIFO_FULL',
784: 'PH_SC6_PA3_NULL_WE',
785: 'PH_SC6_PA3_EVENT_WE',
786: 'PH_SC6_PA3_FPOV_WE',
787: 'PH_SC6_PA3_LPOV_WE',
788: 'PH_SC6_PA3_EOP_WE',
789: 'PH_SC6_PA3_DATA_FIFO_EOP_RD',
790: 'PH_SC6_PA3_EOPG_WE',
791: 'PH_SC6_PA3_DEALLOC_4_0_RD',
792: 'PH_SC6_PA4_DATA_FIFO_RD',
793: 'PH_SC6_PA4_DATA_FIFO_WE',
794: 'PH_SC6_PA4_FIFO_EMPTY',
795: 'PH_SC6_PA4_FIFO_FULL',
796: 'PH_SC6_PA4_NULL_WE',
797: 'PH_SC6_PA4_EVENT_WE',
798: 'PH_SC6_PA4_FPOV_WE',
799: 'PH_SC6_PA4_LPOV_WE',
800: 'PH_SC6_PA4_EOP_WE',
801: 'PH_SC6_PA4_DATA_FIFO_EOP_RD',
802: 'PH_SC6_PA4_EOPG_WE',
803: 'PH_SC6_PA4_DEALLOC_4_0_RD',
804: 'PH_SC6_PA5_DATA_FIFO_RD',
805: 'PH_SC6_PA5_DATA_FIFO_WE',
806: 'PH_SC6_PA5_FIFO_EMPTY',
807: 'PH_SC6_PA5_FIFO_FULL',
808: 'PH_SC6_PA5_NULL_WE',
809: 'PH_SC6_PA5_EVENT_WE',
810: 'PH_SC6_PA5_FPOV_WE',
811: 'PH_SC6_PA5_LPOV_WE',
812: 'PH_SC6_PA5_EOP_WE',
813: 'PH_SC6_PA5_DATA_FIFO_EOP_RD',
814: 'PH_SC6_PA5_EOPG_WE',
815: 'PH_SC6_PA5_DEALLOC_4_0_RD',
816: 'PH_SC6_PA6_DATA_FIFO_RD',
817: 'PH_SC6_PA6_DATA_FIFO_WE',
818: 'PH_SC6_PA6_FIFO_EMPTY',
819: 'PH_SC6_PA6_FIFO_FULL',
820: 'PH_SC6_PA6_NULL_WE',
821: 'PH_SC6_PA6_EVENT_WE',
822: 'PH_SC6_PA6_FPOV_WE',
823: 'PH_SC6_PA6_LPOV_WE',
824: 'PH_SC6_PA6_EOP_WE',
825: 'PH_SC6_PA6_DATA_FIFO_EOP_RD',
826: 'PH_SC6_PA6_EOPG_WE',
827: 'PH_SC6_PA6_DEALLOC_4_0_RD',
828: 'PH_SC6_PA7_DATA_FIFO_RD',
829: 'PH_SC6_PA7_DATA_FIFO_WE',
830: 'PH_SC6_PA7_FIFO_EMPTY',
831: 'PH_SC6_PA7_FIFO_FULL',
832: 'PH_SC6_PA7_NULL_WE',
833: 'PH_SC6_PA7_EVENT_WE',
834: 'PH_SC6_PA7_FPOV_WE',
835: 'PH_SC6_PA7_LPOV_WE',
836: 'PH_SC6_PA7_EOP_WE',
837: 'PH_SC6_PA7_DATA_FIFO_EOP_RD',
838: 'PH_SC6_PA7_EOPG_WE',
839: 'PH_SC6_PA7_DEALLOC_4_0_RD',
840: 'PH_SC7_SRPS_WINDOW_VALID',
841: 'PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
842: 'PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES',
843: 'PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
844: 'PH_SC7_ARB_STALLED_FROM_BELOW',
845: 'PH_SC7_ARB_STARVED_FROM_ABOVE',
846: 'PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
847: 'PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
848: 'PH_SC7_ARB_BUSY',
849: 'PH_SC7_ARB_PA_BUSY_SOP',
850: 'PH_SC7_ARB_EOP_POP_SYNC_POP',
851: 'PH_SC7_ARB_EVENT_SYNC_POP',
852: 'PH_SC7_PS_ENG_MULTICYCLE_BUBBLE',
853: 'PH_SC7_EOP_SYNC_WINDOW',
854: 'PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM',
855: 'PH_SC7_BUSY_CNT_NOT_ZERO',
856: 'PH_SC7_SEND',
857: 'PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND',
858: 'PH_SC7_CREDIT_AT_MAX',
859: 'PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND',
860: 'PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
861: 'PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
862: 'PH_SC7_GFX_PIPE0_TO_1_TRANSITION',
863: 'PH_SC7_GFX_PIPE1_TO_0_TRANSITION',
864: 'PH_SC7_PA0_DATA_FIFO_RD',
865: 'PH_SC7_PA0_DATA_FIFO_WE',
866: 'PH_SC7_PA0_FIFO_EMPTY',
867: 'PH_SC7_PA0_FIFO_FULL',
868: 'PH_SC7_PA0_NULL_WE',
869: 'PH_SC7_PA0_EVENT_WE',
870: 'PH_SC7_PA0_FPOV_WE',
871: 'PH_SC7_PA0_LPOV_WE',
872: 'PH_SC7_PA0_EOP_WE',
873: 'PH_SC7_PA0_DATA_FIFO_EOP_RD',
874: 'PH_SC7_PA0_EOPG_WE',
875: 'PH_SC7_PA0_DEALLOC_4_0_RD',
876: 'PH_SC7_PA1_DATA_FIFO_RD',
877: 'PH_SC7_PA1_DATA_FIFO_WE',
878: 'PH_SC7_PA1_FIFO_EMPTY',
879: 'PH_SC7_PA1_FIFO_FULL',
880: 'PH_SC7_PA1_NULL_WE',
881: 'PH_SC7_PA1_EVENT_WE',
882: 'PH_SC7_PA1_FPOV_WE',
883: 'PH_SC7_PA1_LPOV_WE',
884: 'PH_SC7_PA1_EOP_WE',
885: 'PH_SC7_PA1_DATA_FIFO_EOP_RD',
886: 'PH_SC7_PA1_EOPG_WE',
887: 'PH_SC7_PA1_DEALLOC_4_0_RD',
888: 'PH_SC7_PA2_DATA_FIFO_RD',
889: 'PH_SC7_PA2_DATA_FIFO_WE',
890: 'PH_SC7_PA2_FIFO_EMPTY',
891: 'PH_SC7_PA2_FIFO_FULL',
892: 'PH_SC7_PA2_NULL_WE',
893: 'PH_SC7_PA2_EVENT_WE',
894: 'PH_SC7_PA2_FPOV_WE',
895: 'PH_SC7_PA2_LPOV_WE',
896: 'PH_SC7_PA2_EOP_WE',
897: 'PH_SC7_PA2_DATA_FIFO_EOP_RD',
898: 'PH_SC7_PA2_EOPG_WE',
899: 'PH_SC7_PA2_DEALLOC_4_0_RD',
900: 'PH_SC7_PA3_DATA_FIFO_RD',
901: 'PH_SC7_PA3_DATA_FIFO_WE',
902: 'PH_SC7_PA3_FIFO_EMPTY',
903: 'PH_SC7_PA3_FIFO_FULL',
904: 'PH_SC7_PA3_NULL_WE',
905: 'PH_SC7_PA3_EVENT_WE',
906: 'PH_SC7_PA3_FPOV_WE',
907: 'PH_SC7_PA3_LPOV_WE',
908: 'PH_SC7_PA3_EOP_WE',
909: 'PH_SC7_PA3_DATA_FIFO_EOP_RD',
910: 'PH_SC7_PA3_EOPG_WE',
911: 'PH_SC7_PA3_DEALLOC_4_0_RD',
912: 'PH_SC7_PA4_DATA_FIFO_RD',
913: 'PH_SC7_PA4_DATA_FIFO_WE',
914: 'PH_SC7_PA4_FIFO_EMPTY',
915: 'PH_SC7_PA4_FIFO_FULL',
916: 'PH_SC7_PA4_NULL_WE',
917: 'PH_SC7_PA4_EVENT_WE',
918: 'PH_SC7_PA4_FPOV_WE',
919: 'PH_SC7_PA4_LPOV_WE',
920: 'PH_SC7_PA4_EOP_WE',
921: 'PH_SC7_PA4_DATA_FIFO_EOP_RD',
922: 'PH_SC7_PA4_EOPG_WE',
923: 'PH_SC7_PA4_DEALLOC_4_0_RD',
924: 'PH_SC7_PA5_DATA_FIFO_RD',
925: 'PH_SC7_PA5_DATA_FIFO_WE',
926: 'PH_SC7_PA5_FIFO_EMPTY',
927: 'PH_SC7_PA5_FIFO_FULL',
928: 'PH_SC7_PA5_NULL_WE',
929: 'PH_SC7_PA5_EVENT_WE',
930: 'PH_SC7_PA5_FPOV_WE',
931: 'PH_SC7_PA5_LPOV_WE',
932: 'PH_SC7_PA5_EOP_WE',
933: 'PH_SC7_PA5_DATA_FIFO_EOP_RD',
934: 'PH_SC7_PA5_EOPG_WE',
935: 'PH_SC7_PA5_DEALLOC_4_0_RD',
936: 'PH_SC7_PA6_DATA_FIFO_RD',
937: 'PH_SC7_PA6_DATA_FIFO_WE',
938: 'PH_SC7_PA6_FIFO_EMPTY',
939: 'PH_SC7_PA6_FIFO_FULL',
940: 'PH_SC7_PA6_NULL_WE',
941: 'PH_SC7_PA6_EVENT_WE',
942: 'PH_SC7_PA6_FPOV_WE',
943: 'PH_SC7_PA6_LPOV_WE',
944: 'PH_SC7_PA6_EOP_WE',
945: 'PH_SC7_PA6_DATA_FIFO_EOP_RD',
946: 'PH_SC7_PA6_EOPG_WE',
947: 'PH_SC7_PA6_DEALLOC_4_0_RD',
948: 'PH_SC7_PA7_DATA_FIFO_RD',
949: 'PH_SC7_PA7_DATA_FIFO_WE',
950: 'PH_SC7_PA7_FIFO_EMPTY',
951: 'PH_SC7_PA7_FIFO_FULL',
952: 'PH_SC7_PA7_NULL_WE',
953: 'PH_SC7_PA7_EVENT_WE',
954: 'PH_SC7_PA7_FPOV_WE',
955: 'PH_SC7_PA7_LPOV_WE',
956: 'PH_SC7_PA7_EOP_WE',
957: 'PH_SC7_PA7_DATA_FIFO_EOP_RD',
958: 'PH_SC7_PA7_EOPG_WE',
959: 'PH_SC7_PA7_DEALLOC_4_0_RD',
}
PH_SC0_SRPS_WINDOW_VALID = 0
PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 1
PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 2
PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 3
PH_SC0_ARB_STALLED_FROM_BELOW = 4
PH_SC0_ARB_STARVED_FROM_ABOVE = 5
PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 6
PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 7
PH_SC0_ARB_BUSY = 8
PH_SC0_ARB_PA_BUSY_SOP = 9
PH_SC0_ARB_EOP_POP_SYNC_POP = 10
PH_SC0_ARB_EVENT_SYNC_POP = 11
PH_SC0_PS_ENG_MULTICYCLE_BUBBLE = 12
PH_SC0_EOP_SYNC_WINDOW = 13
PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 14
PH_SC0_BUSY_CNT_NOT_ZERO = 15
PH_SC0_SEND = 16
PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 17
PH_SC0_CREDIT_AT_MAX = 18
PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 19
PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 20
PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 21
PH_SC0_GFX_PIPE0_TO_1_TRANSITION = 22
PH_SC0_GFX_PIPE1_TO_0_TRANSITION = 23
PH_SC0_PA0_DATA_FIFO_RD = 24
PH_SC0_PA0_DATA_FIFO_WE = 25
PH_SC0_PA0_FIFO_EMPTY = 26
PH_SC0_PA0_FIFO_FULL = 27
PH_SC0_PA0_NULL_WE = 28
PH_SC0_PA0_EVENT_WE = 29
PH_SC0_PA0_FPOV_WE = 30
PH_SC0_PA0_LPOV_WE = 31
PH_SC0_PA0_EOP_WE = 32
PH_SC0_PA0_DATA_FIFO_EOP_RD = 33
PH_SC0_PA0_EOPG_WE = 34
PH_SC0_PA0_DEALLOC_4_0_RD = 35
PH_SC0_PA1_DATA_FIFO_RD = 36
PH_SC0_PA1_DATA_FIFO_WE = 37
PH_SC0_PA1_FIFO_EMPTY = 38
PH_SC0_PA1_FIFO_FULL = 39
PH_SC0_PA1_NULL_WE = 40
PH_SC0_PA1_EVENT_WE = 41
PH_SC0_PA1_FPOV_WE = 42
PH_SC0_PA1_LPOV_WE = 43
PH_SC0_PA1_EOP_WE = 44
PH_SC0_PA1_DATA_FIFO_EOP_RD = 45
PH_SC0_PA1_EOPG_WE = 46
PH_SC0_PA1_DEALLOC_4_0_RD = 47
PH_SC0_PA2_DATA_FIFO_RD = 48
PH_SC0_PA2_DATA_FIFO_WE = 49
PH_SC0_PA2_FIFO_EMPTY = 50
PH_SC0_PA2_FIFO_FULL = 51
PH_SC0_PA2_NULL_WE = 52
PH_SC0_PA2_EVENT_WE = 53
PH_SC0_PA2_FPOV_WE = 54
PH_SC0_PA2_LPOV_WE = 55
PH_SC0_PA2_EOP_WE = 56
PH_SC0_PA2_DATA_FIFO_EOP_RD = 57
PH_SC0_PA2_EOPG_WE = 58
PH_SC0_PA2_DEALLOC_4_0_RD = 59
PH_SC0_PA3_DATA_FIFO_RD = 60
PH_SC0_PA3_DATA_FIFO_WE = 61
PH_SC0_PA3_FIFO_EMPTY = 62
PH_SC0_PA3_FIFO_FULL = 63
PH_SC0_PA3_NULL_WE = 64
PH_SC0_PA3_EVENT_WE = 65
PH_SC0_PA3_FPOV_WE = 66
PH_SC0_PA3_LPOV_WE = 67
PH_SC0_PA3_EOP_WE = 68
PH_SC0_PA3_DATA_FIFO_EOP_RD = 69
PH_SC0_PA3_EOPG_WE = 70
PH_SC0_PA3_DEALLOC_4_0_RD = 71
PH_SC0_PA4_DATA_FIFO_RD = 72
PH_SC0_PA4_DATA_FIFO_WE = 73
PH_SC0_PA4_FIFO_EMPTY = 74
PH_SC0_PA4_FIFO_FULL = 75
PH_SC0_PA4_NULL_WE = 76
PH_SC0_PA4_EVENT_WE = 77
PH_SC0_PA4_FPOV_WE = 78
PH_SC0_PA4_LPOV_WE = 79
PH_SC0_PA4_EOP_WE = 80
PH_SC0_PA4_DATA_FIFO_EOP_RD = 81
PH_SC0_PA4_EOPG_WE = 82
PH_SC0_PA4_DEALLOC_4_0_RD = 83
PH_SC0_PA5_DATA_FIFO_RD = 84
PH_SC0_PA5_DATA_FIFO_WE = 85
PH_SC0_PA5_FIFO_EMPTY = 86
PH_SC0_PA5_FIFO_FULL = 87
PH_SC0_PA5_NULL_WE = 88
PH_SC0_PA5_EVENT_WE = 89
PH_SC0_PA5_FPOV_WE = 90
PH_SC0_PA5_LPOV_WE = 91
PH_SC0_PA5_EOP_WE = 92
PH_SC0_PA5_DATA_FIFO_EOP_RD = 93
PH_SC0_PA5_EOPG_WE = 94
PH_SC0_PA5_DEALLOC_4_0_RD = 95
PH_SC0_PA6_DATA_FIFO_RD = 96
PH_SC0_PA6_DATA_FIFO_WE = 97
PH_SC0_PA6_FIFO_EMPTY = 98
PH_SC0_PA6_FIFO_FULL = 99
PH_SC0_PA6_NULL_WE = 100
PH_SC0_PA6_EVENT_WE = 101
PH_SC0_PA6_FPOV_WE = 102
PH_SC0_PA6_LPOV_WE = 103
PH_SC0_PA6_EOP_WE = 104
PH_SC0_PA6_DATA_FIFO_EOP_RD = 105
PH_SC0_PA6_EOPG_WE = 106
PH_SC0_PA6_DEALLOC_4_0_RD = 107
PH_SC0_PA7_DATA_FIFO_RD = 108
PH_SC0_PA7_DATA_FIFO_WE = 109
PH_SC0_PA7_FIFO_EMPTY = 110
PH_SC0_PA7_FIFO_FULL = 111
PH_SC0_PA7_NULL_WE = 112
PH_SC0_PA7_EVENT_WE = 113
PH_SC0_PA7_FPOV_WE = 114
PH_SC0_PA7_LPOV_WE = 115
PH_SC0_PA7_EOP_WE = 116
PH_SC0_PA7_DATA_FIFO_EOP_RD = 117
PH_SC0_PA7_EOPG_WE = 118
PH_SC0_PA7_DEALLOC_4_0_RD = 119
PH_SC1_SRPS_WINDOW_VALID = 120
PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 121
PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 122
PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 123
PH_SC1_ARB_STALLED_FROM_BELOW = 124
PH_SC1_ARB_STARVED_FROM_ABOVE = 125
PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 126
PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 127
PH_SC1_ARB_BUSY = 128
PH_SC1_ARB_PA_BUSY_SOP = 129
PH_SC1_ARB_EOP_POP_SYNC_POP = 130
PH_SC1_ARB_EVENT_SYNC_POP = 131
PH_SC1_PS_ENG_MULTICYCLE_BUBBLE = 132
PH_SC1_EOP_SYNC_WINDOW = 133
PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 134
PH_SC1_BUSY_CNT_NOT_ZERO = 135
PH_SC1_SEND = 136
PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 137
PH_SC1_CREDIT_AT_MAX = 138
PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 139
PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 140
PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 141
PH_SC1_GFX_PIPE0_TO_1_TRANSITION = 142
PH_SC1_GFX_PIPE1_TO_0_TRANSITION = 143
PH_SC1_PA0_DATA_FIFO_RD = 144
PH_SC1_PA0_DATA_FIFO_WE = 145
PH_SC1_PA0_FIFO_EMPTY = 146
PH_SC1_PA0_FIFO_FULL = 147
PH_SC1_PA0_NULL_WE = 148
PH_SC1_PA0_EVENT_WE = 149
PH_SC1_PA0_FPOV_WE = 150
PH_SC1_PA0_LPOV_WE = 151
PH_SC1_PA0_EOP_WE = 152
PH_SC1_PA0_DATA_FIFO_EOP_RD = 153
PH_SC1_PA0_EOPG_WE = 154
PH_SC1_PA0_DEALLOC_4_0_RD = 155
PH_SC1_PA1_DATA_FIFO_RD = 156
PH_SC1_PA1_DATA_FIFO_WE = 157
PH_SC1_PA1_FIFO_EMPTY = 158
PH_SC1_PA1_FIFO_FULL = 159
PH_SC1_PA1_NULL_WE = 160
PH_SC1_PA1_EVENT_WE = 161
PH_SC1_PA1_FPOV_WE = 162
PH_SC1_PA1_LPOV_WE = 163
PH_SC1_PA1_EOP_WE = 164
PH_SC1_PA1_DATA_FIFO_EOP_RD = 165
PH_SC1_PA1_EOPG_WE = 166
PH_SC1_PA1_DEALLOC_4_0_RD = 167
PH_SC1_PA2_DATA_FIFO_RD = 168
PH_SC1_PA2_DATA_FIFO_WE = 169
PH_SC1_PA2_FIFO_EMPTY = 170
PH_SC1_PA2_FIFO_FULL = 171
PH_SC1_PA2_NULL_WE = 172
PH_SC1_PA2_EVENT_WE = 173
PH_SC1_PA2_FPOV_WE = 174
PH_SC1_PA2_LPOV_WE = 175
PH_SC1_PA2_EOP_WE = 176
PH_SC1_PA2_DATA_FIFO_EOP_RD = 177
PH_SC1_PA2_EOPG_WE = 178
PH_SC1_PA2_DEALLOC_4_0_RD = 179
PH_SC1_PA3_DATA_FIFO_RD = 180
PH_SC1_PA3_DATA_FIFO_WE = 181
PH_SC1_PA3_FIFO_EMPTY = 182
PH_SC1_PA3_FIFO_FULL = 183
PH_SC1_PA3_NULL_WE = 184
PH_SC1_PA3_EVENT_WE = 185
PH_SC1_PA3_FPOV_WE = 186
PH_SC1_PA3_LPOV_WE = 187
PH_SC1_PA3_EOP_WE = 188
PH_SC1_PA3_DATA_FIFO_EOP_RD = 189
PH_SC1_PA3_EOPG_WE = 190
PH_SC1_PA3_DEALLOC_4_0_RD = 191
PH_SC1_PA4_DATA_FIFO_RD = 192
PH_SC1_PA4_DATA_FIFO_WE = 193
PH_SC1_PA4_FIFO_EMPTY = 194
PH_SC1_PA4_FIFO_FULL = 195
PH_SC1_PA4_NULL_WE = 196
PH_SC1_PA4_EVENT_WE = 197
PH_SC1_PA4_FPOV_WE = 198
PH_SC1_PA4_LPOV_WE = 199
PH_SC1_PA4_EOP_WE = 200
PH_SC1_PA4_DATA_FIFO_EOP_RD = 201
PH_SC1_PA4_EOPG_WE = 202
PH_SC1_PA4_DEALLOC_4_0_RD = 203
PH_SC1_PA5_DATA_FIFO_RD = 204
PH_SC1_PA5_DATA_FIFO_WE = 205
PH_SC1_PA5_FIFO_EMPTY = 206
PH_SC1_PA5_FIFO_FULL = 207
PH_SC1_PA5_NULL_WE = 208
PH_SC1_PA5_EVENT_WE = 209
PH_SC1_PA5_FPOV_WE = 210
PH_SC1_PA5_LPOV_WE = 211
PH_SC1_PA5_EOP_WE = 212
PH_SC1_PA5_DATA_FIFO_EOP_RD = 213
PH_SC1_PA5_EOPG_WE = 214
PH_SC1_PA5_DEALLOC_4_0_RD = 215
PH_SC1_PA6_DATA_FIFO_RD = 216
PH_SC1_PA6_DATA_FIFO_WE = 217
PH_SC1_PA6_FIFO_EMPTY = 218
PH_SC1_PA6_FIFO_FULL = 219
PH_SC1_PA6_NULL_WE = 220
PH_SC1_PA6_EVENT_WE = 221
PH_SC1_PA6_FPOV_WE = 222
PH_SC1_PA6_LPOV_WE = 223
PH_SC1_PA6_EOP_WE = 224
PH_SC1_PA6_DATA_FIFO_EOP_RD = 225
PH_SC1_PA6_EOPG_WE = 226
PH_SC1_PA6_DEALLOC_4_0_RD = 227
PH_SC1_PA7_DATA_FIFO_RD = 228
PH_SC1_PA7_DATA_FIFO_WE = 229
PH_SC1_PA7_FIFO_EMPTY = 230
PH_SC1_PA7_FIFO_FULL = 231
PH_SC1_PA7_NULL_WE = 232
PH_SC1_PA7_EVENT_WE = 233
PH_SC1_PA7_FPOV_WE = 234
PH_SC1_PA7_LPOV_WE = 235
PH_SC1_PA7_EOP_WE = 236
PH_SC1_PA7_DATA_FIFO_EOP_RD = 237
PH_SC1_PA7_EOPG_WE = 238
PH_SC1_PA7_DEALLOC_4_0_RD = 239
PH_SC2_SRPS_WINDOW_VALID = 240
PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 241
PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 242
PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 243
PH_SC2_ARB_STALLED_FROM_BELOW = 244
PH_SC2_ARB_STARVED_FROM_ABOVE = 245
PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 246
PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 247
PH_SC2_ARB_BUSY = 248
PH_SC2_ARB_PA_BUSY_SOP = 249
PH_SC2_ARB_EOP_POP_SYNC_POP = 250
PH_SC2_ARB_EVENT_SYNC_POP = 251
PH_SC2_PS_ENG_MULTICYCLE_BUBBLE = 252
PH_SC2_EOP_SYNC_WINDOW = 253
PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 254
PH_SC2_BUSY_CNT_NOT_ZERO = 255
PH_SC2_SEND = 256
PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 257
PH_SC2_CREDIT_AT_MAX = 258
PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 259
PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 260
PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 261
PH_SC2_GFX_PIPE0_TO_1_TRANSITION = 262
PH_SC2_GFX_PIPE1_TO_0_TRANSITION = 263
PH_SC2_PA0_DATA_FIFO_RD = 264
PH_SC2_PA0_DATA_FIFO_WE = 265
PH_SC2_PA0_FIFO_EMPTY = 266
PH_SC2_PA0_FIFO_FULL = 267
PH_SC2_PA0_NULL_WE = 268
PH_SC2_PA0_EVENT_WE = 269
PH_SC2_PA0_FPOV_WE = 270
PH_SC2_PA0_LPOV_WE = 271
PH_SC2_PA0_EOP_WE = 272
PH_SC2_PA0_DATA_FIFO_EOP_RD = 273
PH_SC2_PA0_EOPG_WE = 274
PH_SC2_PA0_DEALLOC_4_0_RD = 275
PH_SC2_PA1_DATA_FIFO_RD = 276
PH_SC2_PA1_DATA_FIFO_WE = 277
PH_SC2_PA1_FIFO_EMPTY = 278
PH_SC2_PA1_FIFO_FULL = 279
PH_SC2_PA1_NULL_WE = 280
PH_SC2_PA1_EVENT_WE = 281
PH_SC2_PA1_FPOV_WE = 282
PH_SC2_PA1_LPOV_WE = 283
PH_SC2_PA1_EOP_WE = 284
PH_SC2_PA1_DATA_FIFO_EOP_RD = 285
PH_SC2_PA1_EOPG_WE = 286
PH_SC2_PA1_DEALLOC_4_0_RD = 287
PH_SC2_PA2_DATA_FIFO_RD = 288
PH_SC2_PA2_DATA_FIFO_WE = 289
PH_SC2_PA2_FIFO_EMPTY = 290
PH_SC2_PA2_FIFO_FULL = 291
PH_SC2_PA2_NULL_WE = 292
PH_SC2_PA2_EVENT_WE = 293
PH_SC2_PA2_FPOV_WE = 294
PH_SC2_PA2_LPOV_WE = 295
PH_SC2_PA2_EOP_WE = 296
PH_SC2_PA2_DATA_FIFO_EOP_RD = 297
PH_SC2_PA2_EOPG_WE = 298
PH_SC2_PA2_DEALLOC_4_0_RD = 299
PH_SC2_PA3_DATA_FIFO_RD = 300
PH_SC2_PA3_DATA_FIFO_WE = 301
PH_SC2_PA3_FIFO_EMPTY = 302
PH_SC2_PA3_FIFO_FULL = 303
PH_SC2_PA3_NULL_WE = 304
PH_SC2_PA3_EVENT_WE = 305
PH_SC2_PA3_FPOV_WE = 306
PH_SC2_PA3_LPOV_WE = 307
PH_SC2_PA3_EOP_WE = 308
PH_SC2_PA3_DATA_FIFO_EOP_RD = 309
PH_SC2_PA3_EOPG_WE = 310
PH_SC2_PA3_DEALLOC_4_0_RD = 311
PH_SC2_PA4_DATA_FIFO_RD = 312
PH_SC2_PA4_DATA_FIFO_WE = 313
PH_SC2_PA4_FIFO_EMPTY = 314
PH_SC2_PA4_FIFO_FULL = 315
PH_SC2_PA4_NULL_WE = 316
PH_SC2_PA4_EVENT_WE = 317
PH_SC2_PA4_FPOV_WE = 318
PH_SC2_PA4_LPOV_WE = 319
PH_SC2_PA4_EOP_WE = 320
PH_SC2_PA4_DATA_FIFO_EOP_RD = 321
PH_SC2_PA4_EOPG_WE = 322
PH_SC2_PA4_DEALLOC_4_0_RD = 323
PH_SC2_PA5_DATA_FIFO_RD = 324
PH_SC2_PA5_DATA_FIFO_WE = 325
PH_SC2_PA5_FIFO_EMPTY = 326
PH_SC2_PA5_FIFO_FULL = 327
PH_SC2_PA5_NULL_WE = 328
PH_SC2_PA5_EVENT_WE = 329
PH_SC2_PA5_FPOV_WE = 330
PH_SC2_PA5_LPOV_WE = 331
PH_SC2_PA5_EOP_WE = 332
PH_SC2_PA5_DATA_FIFO_EOP_RD = 333
PH_SC2_PA5_EOPG_WE = 334
PH_SC2_PA5_DEALLOC_4_0_RD = 335
PH_SC2_PA6_DATA_FIFO_RD = 336
PH_SC2_PA6_DATA_FIFO_WE = 337
PH_SC2_PA6_FIFO_EMPTY = 338
PH_SC2_PA6_FIFO_FULL = 339
PH_SC2_PA6_NULL_WE = 340
PH_SC2_PA6_EVENT_WE = 341
PH_SC2_PA6_FPOV_WE = 342
PH_SC2_PA6_LPOV_WE = 343
PH_SC2_PA6_EOP_WE = 344
PH_SC2_PA6_DATA_FIFO_EOP_RD = 345
PH_SC2_PA6_EOPG_WE = 346
PH_SC2_PA6_DEALLOC_4_0_RD = 347
PH_SC2_PA7_DATA_FIFO_RD = 348
PH_SC2_PA7_DATA_FIFO_WE = 349
PH_SC2_PA7_FIFO_EMPTY = 350
PH_SC2_PA7_FIFO_FULL = 351
PH_SC2_PA7_NULL_WE = 352
PH_SC2_PA7_EVENT_WE = 353
PH_SC2_PA7_FPOV_WE = 354
PH_SC2_PA7_LPOV_WE = 355
PH_SC2_PA7_EOP_WE = 356
PH_SC2_PA7_DATA_FIFO_EOP_RD = 357
PH_SC2_PA7_EOPG_WE = 358
PH_SC2_PA7_DEALLOC_4_0_RD = 359
PH_SC3_SRPS_WINDOW_VALID = 360
PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 361
PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 362
PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 363
PH_SC3_ARB_STALLED_FROM_BELOW = 364
PH_SC3_ARB_STARVED_FROM_ABOVE = 365
PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 366
PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 367
PH_SC3_ARB_BUSY = 368
PH_SC3_ARB_PA_BUSY_SOP = 369
PH_SC3_ARB_EOP_POP_SYNC_POP = 370
PH_SC3_ARB_EVENT_SYNC_POP = 371
PH_SC3_PS_ENG_MULTICYCLE_BUBBLE = 372
PH_SC3_EOP_SYNC_WINDOW = 373
PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 374
PH_SC3_BUSY_CNT_NOT_ZERO = 375
PH_SC3_SEND = 376
PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 377
PH_SC3_CREDIT_AT_MAX = 378
PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 379
PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 380
PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 381
PH_SC3_GFX_PIPE0_TO_1_TRANSITION = 382
PH_SC3_GFX_PIPE1_TO_0_TRANSITION = 383
PH_SC3_PA0_DATA_FIFO_RD = 384
PH_SC3_PA0_DATA_FIFO_WE = 385
PH_SC3_PA0_FIFO_EMPTY = 386
PH_SC3_PA0_FIFO_FULL = 387
PH_SC3_PA0_NULL_WE = 388
PH_SC3_PA0_EVENT_WE = 389
PH_SC3_PA0_FPOV_WE = 390
PH_SC3_PA0_LPOV_WE = 391
PH_SC3_PA0_EOP_WE = 392
PH_SC3_PA0_DATA_FIFO_EOP_RD = 393
PH_SC3_PA0_EOPG_WE = 394
PH_SC3_PA0_DEALLOC_4_0_RD = 395
PH_SC3_PA1_DATA_FIFO_RD = 396
PH_SC3_PA1_DATA_FIFO_WE = 397
PH_SC3_PA1_FIFO_EMPTY = 398
PH_SC3_PA1_FIFO_FULL = 399
PH_SC3_PA1_NULL_WE = 400
PH_SC3_PA1_EVENT_WE = 401
PH_SC3_PA1_FPOV_WE = 402
PH_SC3_PA1_LPOV_WE = 403
PH_SC3_PA1_EOP_WE = 404
PH_SC3_PA1_DATA_FIFO_EOP_RD = 405
PH_SC3_PA1_EOPG_WE = 406
PH_SC3_PA1_DEALLOC_4_0_RD = 407
PH_SC3_PA2_DATA_FIFO_RD = 408
PH_SC3_PA2_DATA_FIFO_WE = 409
PH_SC3_PA2_FIFO_EMPTY = 410
PH_SC3_PA2_FIFO_FULL = 411
PH_SC3_PA2_NULL_WE = 412
PH_SC3_PA2_EVENT_WE = 413
PH_SC3_PA2_FPOV_WE = 414
PH_SC3_PA2_LPOV_WE = 415
PH_SC3_PA2_EOP_WE = 416
PH_SC3_PA2_DATA_FIFO_EOP_RD = 417
PH_SC3_PA2_EOPG_WE = 418
PH_SC3_PA2_DEALLOC_4_0_RD = 419
PH_SC3_PA3_DATA_FIFO_RD = 420
PH_SC3_PA3_DATA_FIFO_WE = 421
PH_SC3_PA3_FIFO_EMPTY = 422
PH_SC3_PA3_FIFO_FULL = 423
PH_SC3_PA3_NULL_WE = 424
PH_SC3_PA3_EVENT_WE = 425
PH_SC3_PA3_FPOV_WE = 426
PH_SC3_PA3_LPOV_WE = 427
PH_SC3_PA3_EOP_WE = 428
PH_SC3_PA3_DATA_FIFO_EOP_RD = 429
PH_SC3_PA3_EOPG_WE = 430
PH_SC3_PA3_DEALLOC_4_0_RD = 431
PH_SC3_PA4_DATA_FIFO_RD = 432
PH_SC3_PA4_DATA_FIFO_WE = 433
PH_SC3_PA4_FIFO_EMPTY = 434
PH_SC3_PA4_FIFO_FULL = 435
PH_SC3_PA4_NULL_WE = 436
PH_SC3_PA4_EVENT_WE = 437
PH_SC3_PA4_FPOV_WE = 438
PH_SC3_PA4_LPOV_WE = 439
PH_SC3_PA4_EOP_WE = 440
PH_SC3_PA4_DATA_FIFO_EOP_RD = 441
PH_SC3_PA4_EOPG_WE = 442
PH_SC3_PA4_DEALLOC_4_0_RD = 443
PH_SC3_PA5_DATA_FIFO_RD = 444
PH_SC3_PA5_DATA_FIFO_WE = 445
PH_SC3_PA5_FIFO_EMPTY = 446
PH_SC3_PA5_FIFO_FULL = 447
PH_SC3_PA5_NULL_WE = 448
PH_SC3_PA5_EVENT_WE = 449
PH_SC3_PA5_FPOV_WE = 450
PH_SC3_PA5_LPOV_WE = 451
PH_SC3_PA5_EOP_WE = 452
PH_SC3_PA5_DATA_FIFO_EOP_RD = 453
PH_SC3_PA5_EOPG_WE = 454
PH_SC3_PA5_DEALLOC_4_0_RD = 455
PH_SC3_PA6_DATA_FIFO_RD = 456
PH_SC3_PA6_DATA_FIFO_WE = 457
PH_SC3_PA6_FIFO_EMPTY = 458
PH_SC3_PA6_FIFO_FULL = 459
PH_SC3_PA6_NULL_WE = 460
PH_SC3_PA6_EVENT_WE = 461
PH_SC3_PA6_FPOV_WE = 462
PH_SC3_PA6_LPOV_WE = 463
PH_SC3_PA6_EOP_WE = 464
PH_SC3_PA6_DATA_FIFO_EOP_RD = 465
PH_SC3_PA6_EOPG_WE = 466
PH_SC3_PA6_DEALLOC_4_0_RD = 467
PH_SC3_PA7_DATA_FIFO_RD = 468
PH_SC3_PA7_DATA_FIFO_WE = 469
PH_SC3_PA7_FIFO_EMPTY = 470
PH_SC3_PA7_FIFO_FULL = 471
PH_SC3_PA7_NULL_WE = 472
PH_SC3_PA7_EVENT_WE = 473
PH_SC3_PA7_FPOV_WE = 474
PH_SC3_PA7_LPOV_WE = 475
PH_SC3_PA7_EOP_WE = 476
PH_SC3_PA7_DATA_FIFO_EOP_RD = 477
PH_SC3_PA7_EOPG_WE = 478
PH_SC3_PA7_DEALLOC_4_0_RD = 479
PH_SC4_SRPS_WINDOW_VALID = 480
PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 481
PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 482
PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 483
PH_SC4_ARB_STALLED_FROM_BELOW = 484
PH_SC4_ARB_STARVED_FROM_ABOVE = 485
PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 486
PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 487
PH_SC4_ARB_BUSY = 488
PH_SC4_ARB_PA_BUSY_SOP = 489
PH_SC4_ARB_EOP_POP_SYNC_POP = 490
PH_SC4_ARB_EVENT_SYNC_POP = 491
PH_SC4_PS_ENG_MULTICYCLE_BUBBLE = 492
PH_SC4_EOP_SYNC_WINDOW = 493
PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 494
PH_SC4_BUSY_CNT_NOT_ZERO = 495
PH_SC4_SEND = 496
PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 497
PH_SC4_CREDIT_AT_MAX = 498
PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 499
PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 500
PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 501
PH_SC4_GFX_PIPE0_TO_1_TRANSITION = 502
PH_SC4_GFX_PIPE1_TO_0_TRANSITION = 503
PH_SC4_PA0_DATA_FIFO_RD = 504
PH_SC4_PA0_DATA_FIFO_WE = 505
PH_SC4_PA0_FIFO_EMPTY = 506
PH_SC4_PA0_FIFO_FULL = 507
PH_SC4_PA0_NULL_WE = 508
PH_SC4_PA0_EVENT_WE = 509
PH_SC4_PA0_FPOV_WE = 510
PH_SC4_PA0_LPOV_WE = 511
PH_SC4_PA0_EOP_WE = 512
PH_SC4_PA0_DATA_FIFO_EOP_RD = 513
PH_SC4_PA0_EOPG_WE = 514
PH_SC4_PA0_DEALLOC_4_0_RD = 515
PH_SC4_PA1_DATA_FIFO_RD = 516
PH_SC4_PA1_DATA_FIFO_WE = 517
PH_SC4_PA1_FIFO_EMPTY = 518
PH_SC4_PA1_FIFO_FULL = 519
PH_SC4_PA1_NULL_WE = 520
PH_SC4_PA1_EVENT_WE = 521
PH_SC4_PA1_FPOV_WE = 522
PH_SC4_PA1_LPOV_WE = 523
PH_SC4_PA1_EOP_WE = 524
PH_SC4_PA1_DATA_FIFO_EOP_RD = 525
PH_SC4_PA1_EOPG_WE = 526
PH_SC4_PA1_DEALLOC_4_0_RD = 527
PH_SC4_PA2_DATA_FIFO_RD = 528
PH_SC4_PA2_DATA_FIFO_WE = 529
PH_SC4_PA2_FIFO_EMPTY = 530
PH_SC4_PA2_FIFO_FULL = 531
PH_SC4_PA2_NULL_WE = 532
PH_SC4_PA2_EVENT_WE = 533
PH_SC4_PA2_FPOV_WE = 534
PH_SC4_PA2_LPOV_WE = 535
PH_SC4_PA2_EOP_WE = 536
PH_SC4_PA2_DATA_FIFO_EOP_RD = 537
PH_SC4_PA2_EOPG_WE = 538
PH_SC4_PA2_DEALLOC_4_0_RD = 539
PH_SC4_PA3_DATA_FIFO_RD = 540
PH_SC4_PA3_DATA_FIFO_WE = 541
PH_SC4_PA3_FIFO_EMPTY = 542
PH_SC4_PA3_FIFO_FULL = 543
PH_SC4_PA3_NULL_WE = 544
PH_SC4_PA3_EVENT_WE = 545
PH_SC4_PA3_FPOV_WE = 546
PH_SC4_PA3_LPOV_WE = 547
PH_SC4_PA3_EOP_WE = 548
PH_SC4_PA3_DATA_FIFO_EOP_RD = 549
PH_SC4_PA3_EOPG_WE = 550
PH_SC4_PA3_DEALLOC_4_0_RD = 551
PH_SC4_PA4_DATA_FIFO_RD = 552
PH_SC4_PA4_DATA_FIFO_WE = 553
PH_SC4_PA4_FIFO_EMPTY = 554
PH_SC4_PA4_FIFO_FULL = 555
PH_SC4_PA4_NULL_WE = 556
PH_SC4_PA4_EVENT_WE = 557
PH_SC4_PA4_FPOV_WE = 558
PH_SC4_PA4_LPOV_WE = 559
PH_SC4_PA4_EOP_WE = 560
PH_SC4_PA4_DATA_FIFO_EOP_RD = 561
PH_SC4_PA4_EOPG_WE = 562
PH_SC4_PA4_DEALLOC_4_0_RD = 563
PH_SC4_PA5_DATA_FIFO_RD = 564
PH_SC4_PA5_DATA_FIFO_WE = 565
PH_SC4_PA5_FIFO_EMPTY = 566
PH_SC4_PA5_FIFO_FULL = 567
PH_SC4_PA5_NULL_WE = 568
PH_SC4_PA5_EVENT_WE = 569
PH_SC4_PA5_FPOV_WE = 570
PH_SC4_PA5_LPOV_WE = 571
PH_SC4_PA5_EOP_WE = 572
PH_SC4_PA5_DATA_FIFO_EOP_RD = 573
PH_SC4_PA5_EOPG_WE = 574
PH_SC4_PA5_DEALLOC_4_0_RD = 575
PH_SC4_PA6_DATA_FIFO_RD = 576
PH_SC4_PA6_DATA_FIFO_WE = 577
PH_SC4_PA6_FIFO_EMPTY = 578
PH_SC4_PA6_FIFO_FULL = 579
PH_SC4_PA6_NULL_WE = 580
PH_SC4_PA6_EVENT_WE = 581
PH_SC4_PA6_FPOV_WE = 582
PH_SC4_PA6_LPOV_WE = 583
PH_SC4_PA6_EOP_WE = 584
PH_SC4_PA6_DATA_FIFO_EOP_RD = 585
PH_SC4_PA6_EOPG_WE = 586
PH_SC4_PA6_DEALLOC_4_0_RD = 587
PH_SC4_PA7_DATA_FIFO_RD = 588
PH_SC4_PA7_DATA_FIFO_WE = 589
PH_SC4_PA7_FIFO_EMPTY = 590
PH_SC4_PA7_FIFO_FULL = 591
PH_SC4_PA7_NULL_WE = 592
PH_SC4_PA7_EVENT_WE = 593
PH_SC4_PA7_FPOV_WE = 594
PH_SC4_PA7_LPOV_WE = 595
PH_SC4_PA7_EOP_WE = 596
PH_SC4_PA7_DATA_FIFO_EOP_RD = 597
PH_SC4_PA7_EOPG_WE = 598
PH_SC4_PA7_DEALLOC_4_0_RD = 599
PH_SC5_SRPS_WINDOW_VALID = 600
PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 601
PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 602
PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 603
PH_SC5_ARB_STALLED_FROM_BELOW = 604
PH_SC5_ARB_STARVED_FROM_ABOVE = 605
PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 606
PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 607
PH_SC5_ARB_BUSY = 608
PH_SC5_ARB_PA_BUSY_SOP = 609
PH_SC5_ARB_EOP_POP_SYNC_POP = 610
PH_SC5_ARB_EVENT_SYNC_POP = 611
PH_SC5_PS_ENG_MULTICYCLE_BUBBLE = 612
PH_SC5_EOP_SYNC_WINDOW = 613
PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 614
PH_SC5_BUSY_CNT_NOT_ZERO = 615
PH_SC5_SEND = 616
PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 617
PH_SC5_CREDIT_AT_MAX = 618
PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 619
PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 620
PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 621
PH_SC5_GFX_PIPE0_TO_1_TRANSITION = 622
PH_SC5_GFX_PIPE1_TO_0_TRANSITION = 623
PH_SC5_PA0_DATA_FIFO_RD = 624
PH_SC5_PA0_DATA_FIFO_WE = 625
PH_SC5_PA0_FIFO_EMPTY = 626
PH_SC5_PA0_FIFO_FULL = 627
PH_SC5_PA0_NULL_WE = 628
PH_SC5_PA0_EVENT_WE = 629
PH_SC5_PA0_FPOV_WE = 630
PH_SC5_PA0_LPOV_WE = 631
PH_SC5_PA0_EOP_WE = 632
PH_SC5_PA0_DATA_FIFO_EOP_RD = 633
PH_SC5_PA0_EOPG_WE = 634
PH_SC5_PA0_DEALLOC_4_0_RD = 635
PH_SC5_PA1_DATA_FIFO_RD = 636
PH_SC5_PA1_DATA_FIFO_WE = 637
PH_SC5_PA1_FIFO_EMPTY = 638
PH_SC5_PA1_FIFO_FULL = 639
PH_SC5_PA1_NULL_WE = 640
PH_SC5_PA1_EVENT_WE = 641
PH_SC5_PA1_FPOV_WE = 642
PH_SC5_PA1_LPOV_WE = 643
PH_SC5_PA1_EOP_WE = 644
PH_SC5_PA1_DATA_FIFO_EOP_RD = 645
PH_SC5_PA1_EOPG_WE = 646
PH_SC5_PA1_DEALLOC_4_0_RD = 647
PH_SC5_PA2_DATA_FIFO_RD = 648
PH_SC5_PA2_DATA_FIFO_WE = 649
PH_SC5_PA2_FIFO_EMPTY = 650
PH_SC5_PA2_FIFO_FULL = 651
PH_SC5_PA2_NULL_WE = 652
PH_SC5_PA2_EVENT_WE = 653
PH_SC5_PA2_FPOV_WE = 654
PH_SC5_PA2_LPOV_WE = 655
PH_SC5_PA2_EOP_WE = 656
PH_SC5_PA2_DATA_FIFO_EOP_RD = 657
PH_SC5_PA2_EOPG_WE = 658
PH_SC5_PA2_DEALLOC_4_0_RD = 659
PH_SC5_PA3_DATA_FIFO_RD = 660
PH_SC5_PA3_DATA_FIFO_WE = 661
PH_SC5_PA3_FIFO_EMPTY = 662
PH_SC5_PA3_FIFO_FULL = 663
PH_SC5_PA3_NULL_WE = 664
PH_SC5_PA3_EVENT_WE = 665
PH_SC5_PA3_FPOV_WE = 666
PH_SC5_PA3_LPOV_WE = 667
PH_SC5_PA3_EOP_WE = 668
PH_SC5_PA3_DATA_FIFO_EOP_RD = 669
PH_SC5_PA3_EOPG_WE = 670
PH_SC5_PA3_DEALLOC_4_0_RD = 671
PH_SC5_PA4_DATA_FIFO_RD = 672
PH_SC5_PA4_DATA_FIFO_WE = 673
PH_SC5_PA4_FIFO_EMPTY = 674
PH_SC5_PA4_FIFO_FULL = 675
PH_SC5_PA4_NULL_WE = 676
PH_SC5_PA4_EVENT_WE = 677
PH_SC5_PA4_FPOV_WE = 678
PH_SC5_PA4_LPOV_WE = 679
PH_SC5_PA4_EOP_WE = 680
PH_SC5_PA4_DATA_FIFO_EOP_RD = 681
PH_SC5_PA4_EOPG_WE = 682
PH_SC5_PA4_DEALLOC_4_0_RD = 683
PH_SC5_PA5_DATA_FIFO_RD = 684
PH_SC5_PA5_DATA_FIFO_WE = 685
PH_SC5_PA5_FIFO_EMPTY = 686
PH_SC5_PA5_FIFO_FULL = 687
PH_SC5_PA5_NULL_WE = 688
PH_SC5_PA5_EVENT_WE = 689
PH_SC5_PA5_FPOV_WE = 690
PH_SC5_PA5_LPOV_WE = 691
PH_SC5_PA5_EOP_WE = 692
PH_SC5_PA5_DATA_FIFO_EOP_RD = 693
PH_SC5_PA5_EOPG_WE = 694
PH_SC5_PA5_DEALLOC_4_0_RD = 695
PH_SC5_PA6_DATA_FIFO_RD = 696
PH_SC5_PA6_DATA_FIFO_WE = 697
PH_SC5_PA6_FIFO_EMPTY = 698
PH_SC5_PA6_FIFO_FULL = 699
PH_SC5_PA6_NULL_WE = 700
PH_SC5_PA6_EVENT_WE = 701
PH_SC5_PA6_FPOV_WE = 702
PH_SC5_PA6_LPOV_WE = 703
PH_SC5_PA6_EOP_WE = 704
PH_SC5_PA6_DATA_FIFO_EOP_RD = 705
PH_SC5_PA6_EOPG_WE = 706
PH_SC5_PA6_DEALLOC_4_0_RD = 707
PH_SC5_PA7_DATA_FIFO_RD = 708
PH_SC5_PA7_DATA_FIFO_WE = 709
PH_SC5_PA7_FIFO_EMPTY = 710
PH_SC5_PA7_FIFO_FULL = 711
PH_SC5_PA7_NULL_WE = 712
PH_SC5_PA7_EVENT_WE = 713
PH_SC5_PA7_FPOV_WE = 714
PH_SC5_PA7_LPOV_WE = 715
PH_SC5_PA7_EOP_WE = 716
PH_SC5_PA7_DATA_FIFO_EOP_RD = 717
PH_SC5_PA7_EOPG_WE = 718
PH_SC5_PA7_DEALLOC_4_0_RD = 719
PH_SC6_SRPS_WINDOW_VALID = 720
PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 721
PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 722
PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 723
PH_SC6_ARB_STALLED_FROM_BELOW = 724
PH_SC6_ARB_STARVED_FROM_ABOVE = 725
PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 726
PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 727
PH_SC6_ARB_BUSY = 728
PH_SC6_ARB_PA_BUSY_SOP = 729
PH_SC6_ARB_EOP_POP_SYNC_POP = 730
PH_SC6_ARB_EVENT_SYNC_POP = 731
PH_SC6_PS_ENG_MULTICYCLE_BUBBLE = 732
PH_SC6_EOP_SYNC_WINDOW = 733
PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 734
PH_SC6_BUSY_CNT_NOT_ZERO = 735
PH_SC6_SEND = 736
PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 737
PH_SC6_CREDIT_AT_MAX = 738
PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 739
PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 740
PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 741
PH_SC6_GFX_PIPE0_TO_1_TRANSITION = 742
PH_SC6_GFX_PIPE1_TO_0_TRANSITION = 743
PH_SC6_PA0_DATA_FIFO_RD = 744
PH_SC6_PA0_DATA_FIFO_WE = 745
PH_SC6_PA0_FIFO_EMPTY = 746
PH_SC6_PA0_FIFO_FULL = 747
PH_SC6_PA0_NULL_WE = 748
PH_SC6_PA0_EVENT_WE = 749
PH_SC6_PA0_FPOV_WE = 750
PH_SC6_PA0_LPOV_WE = 751
PH_SC6_PA0_EOP_WE = 752
PH_SC6_PA0_DATA_FIFO_EOP_RD = 753
PH_SC6_PA0_EOPG_WE = 754
PH_SC6_PA0_DEALLOC_4_0_RD = 755
PH_SC6_PA1_DATA_FIFO_RD = 756
PH_SC6_PA1_DATA_FIFO_WE = 757
PH_SC6_PA1_FIFO_EMPTY = 758
PH_SC6_PA1_FIFO_FULL = 759
PH_SC6_PA1_NULL_WE = 760
PH_SC6_PA1_EVENT_WE = 761
PH_SC6_PA1_FPOV_WE = 762
PH_SC6_PA1_LPOV_WE = 763
PH_SC6_PA1_EOP_WE = 764
PH_SC6_PA1_DATA_FIFO_EOP_RD = 765
PH_SC6_PA1_EOPG_WE = 766
PH_SC6_PA1_DEALLOC_4_0_RD = 767
PH_SC6_PA2_DATA_FIFO_RD = 768
PH_SC6_PA2_DATA_FIFO_WE = 769
PH_SC6_PA2_FIFO_EMPTY = 770
PH_SC6_PA2_FIFO_FULL = 771
PH_SC6_PA2_NULL_WE = 772
PH_SC6_PA2_EVENT_WE = 773
PH_SC6_PA2_FPOV_WE = 774
PH_SC6_PA2_LPOV_WE = 775
PH_SC6_PA2_EOP_WE = 776
PH_SC6_PA2_DATA_FIFO_EOP_RD = 777
PH_SC6_PA2_EOPG_WE = 778
PH_SC6_PA2_DEALLOC_4_0_RD = 779
PH_SC6_PA3_DATA_FIFO_RD = 780
PH_SC6_PA3_DATA_FIFO_WE = 781
PH_SC6_PA3_FIFO_EMPTY = 782
PH_SC6_PA3_FIFO_FULL = 783
PH_SC6_PA3_NULL_WE = 784
PH_SC6_PA3_EVENT_WE = 785
PH_SC6_PA3_FPOV_WE = 786
PH_SC6_PA3_LPOV_WE = 787
PH_SC6_PA3_EOP_WE = 788
PH_SC6_PA3_DATA_FIFO_EOP_RD = 789
PH_SC6_PA3_EOPG_WE = 790
PH_SC6_PA3_DEALLOC_4_0_RD = 791
PH_SC6_PA4_DATA_FIFO_RD = 792
PH_SC6_PA4_DATA_FIFO_WE = 793
PH_SC6_PA4_FIFO_EMPTY = 794
PH_SC6_PA4_FIFO_FULL = 795
PH_SC6_PA4_NULL_WE = 796
PH_SC6_PA4_EVENT_WE = 797
PH_SC6_PA4_FPOV_WE = 798
PH_SC6_PA4_LPOV_WE = 799
PH_SC6_PA4_EOP_WE = 800
PH_SC6_PA4_DATA_FIFO_EOP_RD = 801
PH_SC6_PA4_EOPG_WE = 802
PH_SC6_PA4_DEALLOC_4_0_RD = 803
PH_SC6_PA5_DATA_FIFO_RD = 804
PH_SC6_PA5_DATA_FIFO_WE = 805
PH_SC6_PA5_FIFO_EMPTY = 806
PH_SC6_PA5_FIFO_FULL = 807
PH_SC6_PA5_NULL_WE = 808
PH_SC6_PA5_EVENT_WE = 809
PH_SC6_PA5_FPOV_WE = 810
PH_SC6_PA5_LPOV_WE = 811
PH_SC6_PA5_EOP_WE = 812
PH_SC6_PA5_DATA_FIFO_EOP_RD = 813
PH_SC6_PA5_EOPG_WE = 814
PH_SC6_PA5_DEALLOC_4_0_RD = 815
PH_SC6_PA6_DATA_FIFO_RD = 816
PH_SC6_PA6_DATA_FIFO_WE = 817
PH_SC6_PA6_FIFO_EMPTY = 818
PH_SC6_PA6_FIFO_FULL = 819
PH_SC6_PA6_NULL_WE = 820
PH_SC6_PA6_EVENT_WE = 821
PH_SC6_PA6_FPOV_WE = 822
PH_SC6_PA6_LPOV_WE = 823
PH_SC6_PA6_EOP_WE = 824
PH_SC6_PA6_DATA_FIFO_EOP_RD = 825
PH_SC6_PA6_EOPG_WE = 826
PH_SC6_PA6_DEALLOC_4_0_RD = 827
PH_SC6_PA7_DATA_FIFO_RD = 828
PH_SC6_PA7_DATA_FIFO_WE = 829
PH_SC6_PA7_FIFO_EMPTY = 830
PH_SC6_PA7_FIFO_FULL = 831
PH_SC6_PA7_NULL_WE = 832
PH_SC6_PA7_EVENT_WE = 833
PH_SC6_PA7_FPOV_WE = 834
PH_SC6_PA7_LPOV_WE = 835
PH_SC6_PA7_EOP_WE = 836
PH_SC6_PA7_DATA_FIFO_EOP_RD = 837
PH_SC6_PA7_EOPG_WE = 838
PH_SC6_PA7_DEALLOC_4_0_RD = 839
PH_SC7_SRPS_WINDOW_VALID = 840
PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 841
PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 842
PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 843
PH_SC7_ARB_STALLED_FROM_BELOW = 844
PH_SC7_ARB_STARVED_FROM_ABOVE = 845
PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 846
PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 847
PH_SC7_ARB_BUSY = 848
PH_SC7_ARB_PA_BUSY_SOP = 849
PH_SC7_ARB_EOP_POP_SYNC_POP = 850
PH_SC7_ARB_EVENT_SYNC_POP = 851
PH_SC7_PS_ENG_MULTICYCLE_BUBBLE = 852
PH_SC7_EOP_SYNC_WINDOW = 853
PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 854
PH_SC7_BUSY_CNT_NOT_ZERO = 855
PH_SC7_SEND = 856
PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 857
PH_SC7_CREDIT_AT_MAX = 858
PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 859
PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 860
PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 861
PH_SC7_GFX_PIPE0_TO_1_TRANSITION = 862
PH_SC7_GFX_PIPE1_TO_0_TRANSITION = 863
PH_SC7_PA0_DATA_FIFO_RD = 864
PH_SC7_PA0_DATA_FIFO_WE = 865
PH_SC7_PA0_FIFO_EMPTY = 866
PH_SC7_PA0_FIFO_FULL = 867
PH_SC7_PA0_NULL_WE = 868
PH_SC7_PA0_EVENT_WE = 869
PH_SC7_PA0_FPOV_WE = 870
PH_SC7_PA0_LPOV_WE = 871
PH_SC7_PA0_EOP_WE = 872
PH_SC7_PA0_DATA_FIFO_EOP_RD = 873
PH_SC7_PA0_EOPG_WE = 874
PH_SC7_PA0_DEALLOC_4_0_RD = 875
PH_SC7_PA1_DATA_FIFO_RD = 876
PH_SC7_PA1_DATA_FIFO_WE = 877
PH_SC7_PA1_FIFO_EMPTY = 878
PH_SC7_PA1_FIFO_FULL = 879
PH_SC7_PA1_NULL_WE = 880
PH_SC7_PA1_EVENT_WE = 881
PH_SC7_PA1_FPOV_WE = 882
PH_SC7_PA1_LPOV_WE = 883
PH_SC7_PA1_EOP_WE = 884
PH_SC7_PA1_DATA_FIFO_EOP_RD = 885
PH_SC7_PA1_EOPG_WE = 886
PH_SC7_PA1_DEALLOC_4_0_RD = 887
PH_SC7_PA2_DATA_FIFO_RD = 888
PH_SC7_PA2_DATA_FIFO_WE = 889
PH_SC7_PA2_FIFO_EMPTY = 890
PH_SC7_PA2_FIFO_FULL = 891
PH_SC7_PA2_NULL_WE = 892
PH_SC7_PA2_EVENT_WE = 893
PH_SC7_PA2_FPOV_WE = 894
PH_SC7_PA2_LPOV_WE = 895
PH_SC7_PA2_EOP_WE = 896
PH_SC7_PA2_DATA_FIFO_EOP_RD = 897
PH_SC7_PA2_EOPG_WE = 898
PH_SC7_PA2_DEALLOC_4_0_RD = 899
PH_SC7_PA3_DATA_FIFO_RD = 900
PH_SC7_PA3_DATA_FIFO_WE = 901
PH_SC7_PA3_FIFO_EMPTY = 902
PH_SC7_PA3_FIFO_FULL = 903
PH_SC7_PA3_NULL_WE = 904
PH_SC7_PA3_EVENT_WE = 905
PH_SC7_PA3_FPOV_WE = 906
PH_SC7_PA3_LPOV_WE = 907
PH_SC7_PA3_EOP_WE = 908
PH_SC7_PA3_DATA_FIFO_EOP_RD = 909
PH_SC7_PA3_EOPG_WE = 910
PH_SC7_PA3_DEALLOC_4_0_RD = 911
PH_SC7_PA4_DATA_FIFO_RD = 912
PH_SC7_PA4_DATA_FIFO_WE = 913
PH_SC7_PA4_FIFO_EMPTY = 914
PH_SC7_PA4_FIFO_FULL = 915
PH_SC7_PA4_NULL_WE = 916
PH_SC7_PA4_EVENT_WE = 917
PH_SC7_PA4_FPOV_WE = 918
PH_SC7_PA4_LPOV_WE = 919
PH_SC7_PA4_EOP_WE = 920
PH_SC7_PA4_DATA_FIFO_EOP_RD = 921
PH_SC7_PA4_EOPG_WE = 922
PH_SC7_PA4_DEALLOC_4_0_RD = 923
PH_SC7_PA5_DATA_FIFO_RD = 924
PH_SC7_PA5_DATA_FIFO_WE = 925
PH_SC7_PA5_FIFO_EMPTY = 926
PH_SC7_PA5_FIFO_FULL = 927
PH_SC7_PA5_NULL_WE = 928
PH_SC7_PA5_EVENT_WE = 929
PH_SC7_PA5_FPOV_WE = 930
PH_SC7_PA5_LPOV_WE = 931
PH_SC7_PA5_EOP_WE = 932
PH_SC7_PA5_DATA_FIFO_EOP_RD = 933
PH_SC7_PA5_EOPG_WE = 934
PH_SC7_PA5_DEALLOC_4_0_RD = 935
PH_SC7_PA6_DATA_FIFO_RD = 936
PH_SC7_PA6_DATA_FIFO_WE = 937
PH_SC7_PA6_FIFO_EMPTY = 938
PH_SC7_PA6_FIFO_FULL = 939
PH_SC7_PA6_NULL_WE = 940
PH_SC7_PA6_EVENT_WE = 941
PH_SC7_PA6_FPOV_WE = 942
PH_SC7_PA6_LPOV_WE = 943
PH_SC7_PA6_EOP_WE = 944
PH_SC7_PA6_DATA_FIFO_EOP_RD = 945
PH_SC7_PA6_EOPG_WE = 946
PH_SC7_PA6_DEALLOC_4_0_RD = 947
PH_SC7_PA7_DATA_FIFO_RD = 948
PH_SC7_PA7_DATA_FIFO_WE = 949
PH_SC7_PA7_FIFO_EMPTY = 950
PH_SC7_PA7_FIFO_FULL = 951
PH_SC7_PA7_NULL_WE = 952
PH_SC7_PA7_EVENT_WE = 953
PH_SC7_PA7_FPOV_WE = 954
PH_SC7_PA7_LPOV_WE = 955
PH_SC7_PA7_EOP_WE = 956
PH_SC7_PA7_DATA_FIFO_EOP_RD = 957
PH_SC7_PA7_EOPG_WE = 958
PH_SC7_PA7_DEALLOC_4_0_RD = 959
PH_PERFCNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SU_PERFCNT_SEL'
SU_PERFCNT_SEL__enumvalues = {
0: 'PERF_PAPC_PASX_REQ',
1: 'PERF_PAPC_PASX_DISABLE_PIPE',
2: 'PERF_PAPC_PASX_FIRST_VECTOR',
3: 'PERF_PAPC_PASX_SECOND_VECTOR',
4: 'PERF_PAPC_PASX_FIRST_DEAD',
5: 'PERF_PAPC_PASX_SECOND_DEAD',
6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD',
7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD',
8: 'PERF_PAPC_PA_INPUT_PRIM',
9: 'PERF_PAPC_PA_INPUT_NULL_PRIM',
10: 'PERF_PAPC_PA_INPUT_EVENT_FLAG',
11: 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT',
12: 'PERF_PAPC_PA_INPUT_END_OF_PACKET',
13: 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT',
14: 'PERF_PAPC_CLPR_CULL_PRIM',
15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM',
16: 'PERF_PAPC_CLPR_VV_CULL_PRIM',
17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM',
18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM',
19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM',
20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM',
21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM',
22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM',
23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM',
24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE',
25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1',
26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2',
27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3',
28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4',
29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8',
30: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12',
31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR',
32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR',
33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT',
34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT',
35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP',
36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM',
37: 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM',
38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM',
39: 'PERF_PAPC_CLSM_NULL_PRIM',
40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM',
41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM',
42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1',
43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2',
44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3',
45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4',
46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8',
47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13',
48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM',
49: 'PERF_PAPC_SU_INPUT_PRIM',
50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM',
51: 'PERF_PAPC_SU_INPUT_NULL_PRIM',
52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL',
53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL',
54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM',
55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM',
56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM',
57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL',
58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL',
59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL',
60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL',
61: 'PERF_PAPC_SU_OUTPUT_PRIM',
62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM',
63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM',
64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG',
65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT',
66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET',
67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE',
68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK',
69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT',
70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE',
71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK',
72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT',
73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL',
74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL',
75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL',
76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL',
77: 'PERF_PAPC_PASX_REQ_IDLE',
78: 'PERF_PAPC_PASX_REQ_BUSY',
79: 'PERF_PAPC_PASX_REQ_STALLED',
80: 'PERF_PAPC_PASX_REC_IDLE',
81: 'PERF_PAPC_PASX_REC_BUSY',
82: 'PERF_PAPC_PASX_REC_STARVED_SX',
83: 'PERF_PAPC_PASX_REC_STALLED',
84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM',
85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN',
86: 'PERF_PAPC_CCGSM_IDLE',
87: 'PERF_PAPC_CCGSM_BUSY',
88: 'PERF_PAPC_CCGSM_STALLED',
89: 'PERF_PAPC_CLPRIM_IDLE',
90: 'PERF_PAPC_CLPRIM_BUSY',
91: 'PERF_PAPC_CLPRIM_STALLED',
92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM',
93: 'PERF_PAPC_CLIPSM_IDLE',
94: 'PERF_PAPC_CLIPSM_BUSY',
95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH',
96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ',
97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA',
98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP',
99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM',
100: 'PERF_PAPC_CLIPGA_IDLE',
101: 'PERF_PAPC_CLIPGA_BUSY',
102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP',
103: 'PERF_PAPC_CLIPGA_STALLED',
104: 'PERF_PAPC_CLIP_IDLE',
105: 'PERF_PAPC_CLIP_BUSY',
106: 'PERF_PAPC_SU_IDLE',
107: 'PERF_PAPC_SU_BUSY',
108: 'PERF_PAPC_SU_STARVED_CLIP',
109: 'PERF_PAPC_SU_STALLED_SC',
110: 'PERF_PAPC_CL_DYN_SCLK_VLD',
111: 'PERF_PAPC_SU_DYN_SCLK_VLD',
112: 'PERF_PAPC_PA_REG_SCLK_VLD',
113: 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL',
114: 'PERF_PAPC_PASX_SE0_REQ',
115: 'PERF_PAPC_PASX_SE1_REQ',
116: 'PERF_PAPC_PASX_SE0_FIRST_VECTOR',
117: 'PERF_PAPC_PASX_SE0_SECOND_VECTOR',
118: 'PERF_PAPC_PASX_SE1_FIRST_VECTOR',
119: 'PERF_PAPC_PASX_SE1_SECOND_VECTOR',
120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL',
121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL',
122: 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL',
123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM',
124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM',
125: 'PERF_PAPC_SU_SE01_OUTPUT_PRIM',
126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM',
127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM',
128: 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM',
129: 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT',
130: 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT',
131: 'PERF_PAPC_SU_SE0_STALLED_SC',
132: 'PERF_PAPC_SU_SE1_STALLED_SC',
133: 'PERF_PAPC_SU_SE01_STALLED_SC',
134: 'PERF_PAPC_CLSM_CLIPPING_PRIM',
135: 'PERF_PAPC_SU_CULLED_PRIM',
136: 'PERF_PAPC_SU_OUTPUT_EOPG',
137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL',
138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL',
139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM',
140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM',
141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM',
142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM',
143: 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET',
144: 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET',
145: 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET',
146: 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET',
147: 'PERF_PAPC_SU_SE0_OUTPUT_EOPG',
148: 'PERF_PAPC_SU_SE1_OUTPUT_EOPG',
149: 'PERF_PAPC_SU_SE2_OUTPUT_EOPG',
150: 'PERF_PAPC_SU_SE3_OUTPUT_EOPG',
151: 'PERF_PAPC_SU_SE2_STALLED_SC',
152: 'PERF_PAPC_SU_SE3_STALLED_SC',
153: 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT',
154: 'PERF_SMALL_PRIM_CULL_PRIM_1X1',
155: 'PERF_SMALL_PRIM_CULL_PRIM_2X1',
156: 'PERF_SMALL_PRIM_CULL_PRIM_1X2',
157: 'PERF_SMALL_PRIM_CULL_PRIM_2X2',
158: 'PERF_SMALL_PRIM_CULL_PRIM_3X1',
159: 'PERF_SMALL_PRIM_CULL_PRIM_1X3',
160: 'PERF_SMALL_PRIM_CULL_PRIM_3X2',
161: 'PERF_SMALL_PRIM_CULL_PRIM_2X3',
162: 'PERF_SMALL_PRIM_CULL_PRIM_NX1',
163: 'PERF_SMALL_PRIM_CULL_PRIM_1XN',
164: 'PERF_SMALL_PRIM_CULL_PRIM_NX2',
165: 'PERF_SMALL_PRIM_CULL_PRIM_2XN',
166: 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT',
167: 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT',
168: 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT',
169: 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT',
170: 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT',
171: 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT',
172: 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT',
173: 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT',
174: 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT',
175: 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT',
176: 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT',
177: 'PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1',
178: 'PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT',
179: 'PERF_UTC_SIDEBAND_DRIVER_BUSY',
180: 'PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1',
181: 'PERF_UTC_INDEX_DRIVER_STALLING_CLIENT',
182: 'PERF_UTC_INDEX_DRIVER_BUSY',
183: 'PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1',
184: 'PERF_UTC_POSITION_DRIVER_STALLING_CLIENT',
185: 'PERF_UTC_POSITION_DRIVER_BUSY',
186: 'PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1',
187: 'PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER',
188: 'PERF_UTC_SIDEBAND_RECEIVER_BUSY',
189: 'PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1',
190: 'PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER',
191: 'PERF_UTC_INDEX_RECEIVER_BUSY',
192: 'PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1',
193: 'PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER',
194: 'PERF_UTC_POSITION_RECEIVER_BUSY',
195: 'PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE',
196: 'PERF_TCIF_STALLING_CLIENT_NO_CREDITS',
197: 'PERF_TCIF_BUSY',
198: 'PERF_TCIF_SIDEBAND_RDREQ',
199: 'PERF_TCIF_INDEX_RDREQ',
200: 'PERF_TCIF_POSITION_RDREQ',
201: 'PERF_SIDEBAND_WAITING_ON_UTCL1',
202: 'PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY',
203: 'PERF_WRITING_TO_SIDEBAND_MEMORY',
204: 'PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD',
205: 'PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD',
206: 'PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD',
207: 'PERF_SIDEBAND_WAITING_ON_RETURNED_DATA',
208: 'PERF_SIDEBAND_POP_BIT_FIFO_FULL',
209: 'PERF_SIDEBAND_FIFO_VMID_FIFO_FULL',
210: 'PERF_SIDEBAND_INVALID_REFETCH',
211: 'PERF_SIDEBAND_QUALIFIED_BUSY',
212: 'PERF_SIDEBAND_QUALIFIED_STARVED',
213: 'PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_',
214: 'PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_',
215: 'PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_',
216: 'PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_',
217: 'PERF_INDEX_REQUEST_WAITING_ON_TOKENS',
218: 'PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO',
219: 'PERF_INDEX_REQUEST_QUALIFIED_BUSY',
220: 'PERF_INDEX_REQUEST_QUALIFIED_STARVED',
221: 'PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE',
222: 'PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO',
223: 'PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE',
224: 'PERF_INDEX_RECEIVE_QUALIFIED_BUSY',
225: 'PERF_INDEX_RECEIVE_QUALIFIED_STARVED',
226: 'PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE',
227: 'PERF_INDEX_RECEIVE_1_VALID_DWORDS_THIS_CACHELINE',
228: 'PERF_INDEX_RECEIVE_2_VALID_DWORDS_THIS_CACHELINE',
229: 'PERF_INDEX_RECEIVE_3_VALID_DWORDS_THIS_CACHELINE',
230: 'PERF_INDEX_RECEIVE_4_VALID_DWORDS_THIS_CACHELINE',
231: 'PERF_INDEX_RECEIVE_5_VALID_DWORDS_THIS_CACHELINE',
232: 'PERF_INDEX_RECEIVE_6_VALID_DWORDS_THIS_CACHELINE',
233: 'PERF_INDEX_RECEIVE_7_VALID_DWORDS_THIS_CACHELINE',
234: 'PERF_INDEX_RECEIVE_8_VALID_DWORDS_THIS_CACHELINE',
235: 'PERF_INDEX_RECEIVE_9_VALID_DWORDS_THIS_CACHELINE',
236: 'PERF_INDEX_RECEIVE_10_VALID_DWORDS_THIS_CACHELINE',
237: 'PERF_INDEX_RECEIVE_11_VALID_DWORDS_THIS_CACHELINE',
238: 'PERF_INDEX_RECEIVE_12_VALID_DWORDS_THIS_CACHELINE',
239: 'PERF_INDEX_RECEIVE_13_VALID_DWORDS_THIS_CACHELINE',
240: 'PERF_INDEX_RECEIVE_14_VALID_DWORDS_THIS_CACHELINE',
241: 'PERF_INDEX_RECEIVE_15_VALID_DWORDS_THIS_CACHELINE',
242: 'PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE',
243: 'PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO',
244: 'PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO',
245: 'PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO',
246: 'PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO',
247: 'PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO',
248: 'PERF_POS_REQ_STALLED_BY_NO_TOKENS',
249: 'PERF_POS_REQ_STARVED_BY_NO_PRIM',
250: 'PERF_POS_REQ_STALLED_BY_UTCL1',
251: 'PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE',
252: 'PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE',
253: 'PERF_POS_REQ_QUALIFIED_BUSY',
254: 'PERF_POS_REQ_QUALIFIED_STARVED',
255: 'PERF_POS_REQ_REUSE_0_NEW_VERTS_THIS_PRIM',
256: 'PERF_POS_REQ_REUSE_1_NEW_VERTS_THIS_PRIM',
257: 'PERF_POS_REQ_REUSE_2_NEW_VERTS_THIS_PRIM',
258: 'PERF_POS_REQ_REUSE_3_NEW_VERTS_THIS_PRIM',
259: 'PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO',
260: 'PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO',
261: 'PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE',
262: 'PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE',
263: 'PERF_POS_RET_QUALIFIED_BUSY',
264: 'PERF_POS_RET_QUALIFIED_STARVED',
265: 'PERF_POS_RET_1_CACHELINE_POSITION_USED',
266: 'PERF_POS_RET_2_CACHELINE_POSITION_USED',
267: 'PERF_POS_RET_3_CACHELINE_POSITION_USED',
268: 'PERF_POS_RET_4_CACHELINE_POSITION_USED',
269: 'PERF_TC_INDEX_LATENCY_BIN0',
270: 'PERF_TC_INDEX_LATENCY_BIN1',
271: 'PERF_TC_INDEX_LATENCY_BIN2',
272: 'PERF_TC_INDEX_LATENCY_BIN3',
273: 'PERF_TC_INDEX_LATENCY_BIN4',
274: 'PERF_TC_INDEX_LATENCY_BIN5',
275: 'PERF_TC_INDEX_LATENCY_BIN6',
276: 'PERF_TC_INDEX_LATENCY_BIN7',
277: 'PERF_TC_INDEX_LATENCY_BIN8',
278: 'PERF_TC_INDEX_LATENCY_BIN9',
279: 'PERF_TC_INDEX_LATENCY_BIN10',
280: 'PERF_TC_INDEX_LATENCY_BIN11',
281: 'PERF_TC_INDEX_LATENCY_BIN12',
282: 'PERF_TC_INDEX_LATENCY_BIN13',
283: 'PERF_TC_INDEX_LATENCY_BIN14',
284: 'PERF_TC_INDEX_LATENCY_BIN15',
285: 'PERF_TC_POSITION_LATENCY_BIN0',
286: 'PERF_TC_POSITION_LATENCY_BIN1',
287: 'PERF_TC_POSITION_LATENCY_BIN2',
288: 'PERF_TC_POSITION_LATENCY_BIN3',
289: 'PERF_TC_POSITION_LATENCY_BIN4',
290: 'PERF_TC_POSITION_LATENCY_BIN5',
291: 'PERF_TC_POSITION_LATENCY_BIN6',
292: 'PERF_TC_POSITION_LATENCY_BIN7',
293: 'PERF_TC_POSITION_LATENCY_BIN8',
294: 'PERF_TC_POSITION_LATENCY_BIN9',
295: 'PERF_TC_POSITION_LATENCY_BIN10',
296: 'PERF_TC_POSITION_LATENCY_BIN11',
297: 'PERF_TC_POSITION_LATENCY_BIN12',
298: 'PERF_TC_POSITION_LATENCY_BIN13',
299: 'PERF_TC_POSITION_LATENCY_BIN14',
300: 'PERF_TC_POSITION_LATENCY_BIN15',
301: 'PERF_TC_STREAM0_DATA_AVAILABLE',
302: 'PERF_TC_STREAM1_DATA_AVAILABLE',
303: 'PERF_TC_STREAM2_DATA_AVAILABLE',
304: 'PERF_PAWD_DEALLOC_FIFO_IS_FULL',
305: 'PERF_PAWD_DEALLOC_WAITING_TO_BE_READ',
306: 'PERF_SHOOTDOWN_WAIT_ON_UTCL1',
307: 'PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND',
308: 'PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX',
309: 'PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION',
310: 'PERF_SHOOTDOWN_WAIT_ALL_CLEAN',
311: 'PERF_SHOOTDOWN_WAIT_DEASSERT',
312: 'PERF_UTCL1_TRANSLATION_MISS_CLIENT0',
313: 'PERF_UTCL1_TRANSLATION_MISS_CLIENT1',
314: 'PERF_UTCL1_TRANSLATION_MISS_CLIENT2',
315: 'PERF_UTCL1_PERMISSION_MISS_CLIENT0',
316: 'PERF_UTCL1_PERMISSION_MISS_CLIENT1',
317: 'PERF_UTCL1_PERMISSION_MISS_CLIENT2',
318: 'PERF_UTCL1_TRANSLATION_HIT_CLIENT0',
319: 'PERF_UTCL1_TRANSLATION_HIT_CLIENT1',
320: 'PERF_UTCL1_TRANSLATION_HIT_CLIENT2',
321: 'PERF_UTCL1_REQUEST_CLIENT0',
322: 'PERF_UTCL1_REQUEST_CLIENT1',
323: 'PERF_UTCL1_REQUEST_CLIENT2',
324: 'PERF_UTCL1_STALL_MISSFIFO_FULL',
325: 'PERF_UTCL1_STALL_INFLIGHT_MAX',
326: 'PERF_UTCL1_STALL_LRU_INFLIGHT',
327: 'PERF_UTCL1_STALL_MULTI_MISS',
328: 'PERF_UTCL1_LFIFO_FULL',
329: 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0',
330: 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1',
331: 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2',
332: 'PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS',
333: 'PERF_UTCL1_UTCL2_REQ',
334: 'PERF_UTCL1_UTCL2_RET',
335: 'PERF_UTCL1_UTCL2_INFLIGHT',
336: 'PERF_CLIENT_UTCL1_INFLIGHT',
337: 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED',
338: 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND',
339: 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND',
340: 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED',
341: 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND',
342: 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND',
343: 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED',
344: 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND',
345: 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND',
346: 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED',
347: 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND',
348: 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND',
349: 'PERF_PA_VERTEX_FIFO_FULL',
350: 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL',
351: 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL',
352: 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL',
355: 'ENGG_CSB_MACHINE_IS_STARVED',
356: 'ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY',
357: 'ENGG_CSB_MACHINE_STALLED_BY_SPI',
358: 'ENGG_CSB_GE_INPUT_FIFO_FULL',
359: 'ENGG_CSB_SPI_INPUT_FIFO_FULL',
360: 'ENGG_CSB_OBJECTID_INPUT_FIFO_FULL',
361: 'ENGG_CSB_PRIM_COUNT_EQ0',
362: 'ENGG_CSB_GE_SENDING_SUBGROUP',
363: 'ENGG_CSB_DELAY_BIN00',
364: 'ENGG_CSB_DELAY_BIN01',
365: 'ENGG_CSB_DELAY_BIN02',
366: 'ENGG_CSB_DELAY_BIN03',
367: 'ENGG_CSB_DELAY_BIN04',
368: 'ENGG_CSB_DELAY_BIN05',
369: 'ENGG_CSB_DELAY_BIN06',
370: 'ENGG_CSB_DELAY_BIN07',
371: 'ENGG_CSB_DELAY_BIN08',
372: 'ENGG_CSB_DELAY_BIN09',
373: 'ENGG_CSB_DELAY_BIN10',
374: 'ENGG_CSB_DELAY_BIN11',
375: 'ENGG_CSB_DELAY_BIN12',
376: 'ENGG_CSB_DELAY_BIN13',
377: 'ENGG_CSB_DELAY_BIN14',
378: 'ENGG_CSB_DELAY_BIN15',
379: 'ENGG_CSB_SPI_DELAY_BIN00',
380: 'ENGG_CSB_SPI_DELAY_BIN01',
381: 'ENGG_CSB_SPI_DELAY_BIN02',
382: 'ENGG_CSB_SPI_DELAY_BIN03',
383: 'ENGG_CSB_SPI_DELAY_BIN04',
384: 'ENGG_CSB_SPI_DELAY_BIN05',
385: 'ENGG_CSB_SPI_DELAY_BIN06',
386: 'ENGG_CSB_SPI_DELAY_BIN07',
387: 'ENGG_CSB_SPI_DELAY_BIN08',
388: 'ENGG_CSB_SPI_DELAY_BIN09',
389: 'ENGG_CSB_SPI_DELAY_BIN10',
390: 'ENGG_CSB_SPI_DELAY_BIN11',
391: 'ENGG_CSB_SPI_DELAY_BIN12',
392: 'ENGG_CSB_SPI_DELAY_BIN13',
393: 'ENGG_CSB_SPI_DELAY_BIN14',
394: 'ENGG_CSB_SPI_DELAY_BIN15',
395: 'ENGG_INDEX_REQ_STARVED',
396: 'ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL',
397: 'ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL',
398: 'ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS',
399: 'ENGG_INDEX_RET_REQ2RTN_FIFO_FULL',
400: 'ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY',
401: 'ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL',
402: 'ENGG_INDEX_RET_SXRX_STARVED_BY_CSB',
403: 'ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS',
404: 'ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO',
405: 'ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO',
406: 'ENGG_INDEX_RET_SXRX_READING_EVENT',
407: 'ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP',
408: 'ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0',
409: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL',
410: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL',
411: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL',
412: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL',
413: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS',
414: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS',
415: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS',
416: 'ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO',
417: 'ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO',
418: 'ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM',
419: 'ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE',
420: 'ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE',
421: 'ENGG_INDEX_PRIM_IF_QUALIFIED_BUSY',
422: 'ENGG_INDEX_PRIM_IF_QUALIFIED_STARVED',
423: 'ENGG_INDEX_PRIM_IF_REUSE_0_NEW_VERTS_THIS_PRIM',
424: 'ENGG_INDEX_PRIM_IF_REUSE_1_NEW_VERTS_THIS_PRIM',
425: 'ENGG_INDEX_PRIM_IF_REUSE_2_NEW_VERTS_THIS_PRIM',
426: 'ENGG_INDEX_PRIM_IF_REUSE_3_NEW_VERTS_THIS_PRIM',
427: 'ENGG_POS_REQ_STARVED',
428: 'ENGG_POS_REQ_STALLED_BY_FULL_CLIPV_FIFO',
}
PERF_PAPC_PASX_REQ = 0
PERF_PAPC_PASX_DISABLE_PIPE = 1
PERF_PAPC_PASX_FIRST_VECTOR = 2
PERF_PAPC_PASX_SECOND_VECTOR = 3
PERF_PAPC_PASX_FIRST_DEAD = 4
PERF_PAPC_PASX_SECOND_DEAD = 5
PERF_PAPC_PASX_VTX_KILL_DISCARD = 6
PERF_PAPC_PASX_VTX_NAN_DISCARD = 7
PERF_PAPC_PA_INPUT_PRIM = 8
PERF_PAPC_PA_INPUT_NULL_PRIM = 9
PERF_PAPC_PA_INPUT_EVENT_FLAG = 10
PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11
PERF_PAPC_PA_INPUT_END_OF_PACKET = 12
PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 13
PERF_PAPC_CLPR_CULL_PRIM = 14
PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15
PERF_PAPC_CLPR_VV_CULL_PRIM = 16
PERF_PAPC_CLPR_UCP_CULL_PRIM = 17
PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18
PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19
PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20
PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21
PERF_PAPC_CLPR_VV_CLIP_PRIM = 22
PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23
PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24
PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25
PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26
PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27
PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28
PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29
PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 30
PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31
PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32
PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33
PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34
PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35
PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36
PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 37
PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38
PERF_PAPC_CLSM_NULL_PRIM = 39
PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40
PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41
PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42
PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43
PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44
PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45
PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46
PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 47
PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48
PERF_PAPC_SU_INPUT_PRIM = 49
PERF_PAPC_SU_INPUT_CLIP_PRIM = 50
PERF_PAPC_SU_INPUT_NULL_PRIM = 51
PERF_PAPC_SU_INPUT_PRIM_DUAL = 52
PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53
PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54
PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55
PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56
PERF_PAPC_SU_POLYMODE_FACE_CULL = 57
PERF_PAPC_SU_POLYMODE_BACK_CULL = 58
PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59
PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60
PERF_PAPC_SU_OUTPUT_PRIM = 61
PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62
PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63
PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64
PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65
PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66
PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67
PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68
PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69
PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70
PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71
PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72
PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73
PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74
PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75
PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76
PERF_PAPC_PASX_REQ_IDLE = 77
PERF_PAPC_PASX_REQ_BUSY = 78
PERF_PAPC_PASX_REQ_STALLED = 79
PERF_PAPC_PASX_REC_IDLE = 80
PERF_PAPC_PASX_REC_BUSY = 81
PERF_PAPC_PASX_REC_STARVED_SX = 82
PERF_PAPC_PASX_REC_STALLED = 83
PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84
PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85
PERF_PAPC_CCGSM_IDLE = 86
PERF_PAPC_CCGSM_BUSY = 87
PERF_PAPC_CCGSM_STALLED = 88
PERF_PAPC_CLPRIM_IDLE = 89
PERF_PAPC_CLPRIM_BUSY = 90
PERF_PAPC_CLPRIM_STALLED = 91
PERF_PAPC_CLPRIM_STARVED_CCGSM = 92
PERF_PAPC_CLIPSM_IDLE = 93
PERF_PAPC_CLIPSM_BUSY = 94
PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95
PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96
PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97
PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98
PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99
PERF_PAPC_CLIPGA_IDLE = 100
PERF_PAPC_CLIPGA_BUSY = 101
PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102
PERF_PAPC_CLIPGA_STALLED = 103
PERF_PAPC_CLIP_IDLE = 104
PERF_PAPC_CLIP_BUSY = 105
PERF_PAPC_SU_IDLE = 106
PERF_PAPC_SU_BUSY = 107
PERF_PAPC_SU_STARVED_CLIP = 108
PERF_PAPC_SU_STALLED_SC = 109
PERF_PAPC_CL_DYN_SCLK_VLD = 110
PERF_PAPC_SU_DYN_SCLK_VLD = 111
PERF_PAPC_PA_REG_SCLK_VLD = 112
PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 113
PERF_PAPC_PASX_SE0_REQ = 114
PERF_PAPC_PASX_SE1_REQ = 115
PERF_PAPC_PASX_SE0_FIRST_VECTOR = 116
PERF_PAPC_PASX_SE0_SECOND_VECTOR = 117
PERF_PAPC_PASX_SE1_FIRST_VECTOR = 118
PERF_PAPC_PASX_SE1_SECOND_VECTOR = 119
PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120
PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121
PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 122
PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123
PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124
PERF_PAPC_SU_SE01_OUTPUT_PRIM = 125
PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126
PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127
PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 128
PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 129
PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 130
PERF_PAPC_SU_SE0_STALLED_SC = 131
PERF_PAPC_SU_SE1_STALLED_SC = 132
PERF_PAPC_SU_SE01_STALLED_SC = 133
PERF_PAPC_CLSM_CLIPPING_PRIM = 134
PERF_PAPC_SU_CULLED_PRIM = 135
PERF_PAPC_SU_OUTPUT_EOPG = 136
PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137
PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138
PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139
PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140
PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141
PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142
PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 143
PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 144
PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 145
PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 146
PERF_PAPC_SU_SE0_OUTPUT_EOPG = 147
PERF_PAPC_SU_SE1_OUTPUT_EOPG = 148
PERF_PAPC_SU_SE2_OUTPUT_EOPG = 149
PERF_PAPC_SU_SE3_OUTPUT_EOPG = 150
PERF_PAPC_SU_SE2_STALLED_SC = 151
PERF_PAPC_SU_SE3_STALLED_SC = 152
PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 153
PERF_SMALL_PRIM_CULL_PRIM_1X1 = 154
PERF_SMALL_PRIM_CULL_PRIM_2X1 = 155
PERF_SMALL_PRIM_CULL_PRIM_1X2 = 156
PERF_SMALL_PRIM_CULL_PRIM_2X2 = 157
PERF_SMALL_PRIM_CULL_PRIM_3X1 = 158
PERF_SMALL_PRIM_CULL_PRIM_1X3 = 159
PERF_SMALL_PRIM_CULL_PRIM_3X2 = 160
PERF_SMALL_PRIM_CULL_PRIM_2X3 = 161
PERF_SMALL_PRIM_CULL_PRIM_NX1 = 162
PERF_SMALL_PRIM_CULL_PRIM_1XN = 163
PERF_SMALL_PRIM_CULL_PRIM_NX2 = 164
PERF_SMALL_PRIM_CULL_PRIM_2XN = 165
PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 166
PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 167
PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 168
PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 169
PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 170
PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 171
PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 172
PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 173
PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 174
PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 175
PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 176
PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1 = 177
PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT = 178
PERF_UTC_SIDEBAND_DRIVER_BUSY = 179
PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1 = 180
PERF_UTC_INDEX_DRIVER_STALLING_CLIENT = 181
PERF_UTC_INDEX_DRIVER_BUSY = 182
PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1 = 183
PERF_UTC_POSITION_DRIVER_STALLING_CLIENT = 184
PERF_UTC_POSITION_DRIVER_BUSY = 185
PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1 = 186
PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER = 187
PERF_UTC_SIDEBAND_RECEIVER_BUSY = 188
PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1 = 189
PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER = 190
PERF_UTC_INDEX_RECEIVER_BUSY = 191
PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1 = 192
PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER = 193
PERF_UTC_POSITION_RECEIVER_BUSY = 194
PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE = 195
PERF_TCIF_STALLING_CLIENT_NO_CREDITS = 196
PERF_TCIF_BUSY = 197
PERF_TCIF_SIDEBAND_RDREQ = 198
PERF_TCIF_INDEX_RDREQ = 199
PERF_TCIF_POSITION_RDREQ = 200
PERF_SIDEBAND_WAITING_ON_UTCL1 = 201
PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY = 202
PERF_WRITING_TO_SIDEBAND_MEMORY = 203
PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD = 204
PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD = 205
PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD = 206
PERF_SIDEBAND_WAITING_ON_RETURNED_DATA = 207
PERF_SIDEBAND_POP_BIT_FIFO_FULL = 208
PERF_SIDEBAND_FIFO_VMID_FIFO_FULL = 209
PERF_SIDEBAND_INVALID_REFETCH = 210
PERF_SIDEBAND_QUALIFIED_BUSY = 211
PERF_SIDEBAND_QUALIFIED_STARVED = 212
PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_ = 213
PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_ = 214
PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_ = 215
PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_ = 216
PERF_INDEX_REQUEST_WAITING_ON_TOKENS = 217
PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO = 218
PERF_INDEX_REQUEST_QUALIFIED_BUSY = 219
PERF_INDEX_REQUEST_QUALIFIED_STARVED = 220
PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE = 221
PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO = 222
PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE = 223
PERF_INDEX_RECEIVE_QUALIFIED_BUSY = 224
PERF_INDEX_RECEIVE_QUALIFIED_STARVED = 225
PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE = 226
PERF_INDEX_RECEIVE_1_VALID_DWORDS_THIS_CACHELINE = 227
PERF_INDEX_RECEIVE_2_VALID_DWORDS_THIS_CACHELINE = 228
PERF_INDEX_RECEIVE_3_VALID_DWORDS_THIS_CACHELINE = 229
PERF_INDEX_RECEIVE_4_VALID_DWORDS_THIS_CACHELINE = 230
PERF_INDEX_RECEIVE_5_VALID_DWORDS_THIS_CACHELINE = 231
PERF_INDEX_RECEIVE_6_VALID_DWORDS_THIS_CACHELINE = 232
PERF_INDEX_RECEIVE_7_VALID_DWORDS_THIS_CACHELINE = 233
PERF_INDEX_RECEIVE_8_VALID_DWORDS_THIS_CACHELINE = 234
PERF_INDEX_RECEIVE_9_VALID_DWORDS_THIS_CACHELINE = 235
PERF_INDEX_RECEIVE_10_VALID_DWORDS_THIS_CACHELINE = 236
PERF_INDEX_RECEIVE_11_VALID_DWORDS_THIS_CACHELINE = 237
PERF_INDEX_RECEIVE_12_VALID_DWORDS_THIS_CACHELINE = 238
PERF_INDEX_RECEIVE_13_VALID_DWORDS_THIS_CACHELINE = 239
PERF_INDEX_RECEIVE_14_VALID_DWORDS_THIS_CACHELINE = 240
PERF_INDEX_RECEIVE_15_VALID_DWORDS_THIS_CACHELINE = 241
PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE = 242
PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 243
PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 244
PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO = 245
PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO = 246
PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO = 247
PERF_POS_REQ_STALLED_BY_NO_TOKENS = 248
PERF_POS_REQ_STARVED_BY_NO_PRIM = 249
PERF_POS_REQ_STALLED_BY_UTCL1 = 250
PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE = 251
PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 252
PERF_POS_REQ_QUALIFIED_BUSY = 253
PERF_POS_REQ_QUALIFIED_STARVED = 254
PERF_POS_REQ_REUSE_0_NEW_VERTS_THIS_PRIM = 255
PERF_POS_REQ_REUSE_1_NEW_VERTS_THIS_PRIM = 256
PERF_POS_REQ_REUSE_2_NEW_VERTS_THIS_PRIM = 257
PERF_POS_REQ_REUSE_3_NEW_VERTS_THIS_PRIM = 258
PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO = 259
PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO = 260
PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE = 261
PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE = 262
PERF_POS_RET_QUALIFIED_BUSY = 263
PERF_POS_RET_QUALIFIED_STARVED = 264
PERF_POS_RET_1_CACHELINE_POSITION_USED = 265
PERF_POS_RET_2_CACHELINE_POSITION_USED = 266
PERF_POS_RET_3_CACHELINE_POSITION_USED = 267
PERF_POS_RET_4_CACHELINE_POSITION_USED = 268
PERF_TC_INDEX_LATENCY_BIN0 = 269
PERF_TC_INDEX_LATENCY_BIN1 = 270
PERF_TC_INDEX_LATENCY_BIN2 = 271
PERF_TC_INDEX_LATENCY_BIN3 = 272
PERF_TC_INDEX_LATENCY_BIN4 = 273
PERF_TC_INDEX_LATENCY_BIN5 = 274
PERF_TC_INDEX_LATENCY_BIN6 = 275
PERF_TC_INDEX_LATENCY_BIN7 = 276
PERF_TC_INDEX_LATENCY_BIN8 = 277
PERF_TC_INDEX_LATENCY_BIN9 = 278
PERF_TC_INDEX_LATENCY_BIN10 = 279
PERF_TC_INDEX_LATENCY_BIN11 = 280
PERF_TC_INDEX_LATENCY_BIN12 = 281
PERF_TC_INDEX_LATENCY_BIN13 = 282
PERF_TC_INDEX_LATENCY_BIN14 = 283
PERF_TC_INDEX_LATENCY_BIN15 = 284
PERF_TC_POSITION_LATENCY_BIN0 = 285
PERF_TC_POSITION_LATENCY_BIN1 = 286
PERF_TC_POSITION_LATENCY_BIN2 = 287
PERF_TC_POSITION_LATENCY_BIN3 = 288
PERF_TC_POSITION_LATENCY_BIN4 = 289
PERF_TC_POSITION_LATENCY_BIN5 = 290
PERF_TC_POSITION_LATENCY_BIN6 = 291
PERF_TC_POSITION_LATENCY_BIN7 = 292
PERF_TC_POSITION_LATENCY_BIN8 = 293
PERF_TC_POSITION_LATENCY_BIN9 = 294
PERF_TC_POSITION_LATENCY_BIN10 = 295
PERF_TC_POSITION_LATENCY_BIN11 = 296
PERF_TC_POSITION_LATENCY_BIN12 = 297
PERF_TC_POSITION_LATENCY_BIN13 = 298
PERF_TC_POSITION_LATENCY_BIN14 = 299
PERF_TC_POSITION_LATENCY_BIN15 = 300
PERF_TC_STREAM0_DATA_AVAILABLE = 301
PERF_TC_STREAM1_DATA_AVAILABLE = 302
PERF_TC_STREAM2_DATA_AVAILABLE = 303
PERF_PAWD_DEALLOC_FIFO_IS_FULL = 304
PERF_PAWD_DEALLOC_WAITING_TO_BE_READ = 305
PERF_SHOOTDOWN_WAIT_ON_UTCL1 = 306
PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND = 307
PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX = 308
PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION = 309
PERF_SHOOTDOWN_WAIT_ALL_CLEAN = 310
PERF_SHOOTDOWN_WAIT_DEASSERT = 311
PERF_UTCL1_TRANSLATION_MISS_CLIENT0 = 312
PERF_UTCL1_TRANSLATION_MISS_CLIENT1 = 313
PERF_UTCL1_TRANSLATION_MISS_CLIENT2 = 314
PERF_UTCL1_PERMISSION_MISS_CLIENT0 = 315
PERF_UTCL1_PERMISSION_MISS_CLIENT1 = 316
PERF_UTCL1_PERMISSION_MISS_CLIENT2 = 317
PERF_UTCL1_TRANSLATION_HIT_CLIENT0 = 318
PERF_UTCL1_TRANSLATION_HIT_CLIENT1 = 319
PERF_UTCL1_TRANSLATION_HIT_CLIENT2 = 320
PERF_UTCL1_REQUEST_CLIENT0 = 321
PERF_UTCL1_REQUEST_CLIENT1 = 322
PERF_UTCL1_REQUEST_CLIENT2 = 323
PERF_UTCL1_STALL_MISSFIFO_FULL = 324
PERF_UTCL1_STALL_INFLIGHT_MAX = 325
PERF_UTCL1_STALL_LRU_INFLIGHT = 326
PERF_UTCL1_STALL_MULTI_MISS = 327
PERF_UTCL1_LFIFO_FULL = 328
PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0 = 329
PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1 = 330
PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2 = 331
PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 332
PERF_UTCL1_UTCL2_REQ = 333
PERF_UTCL1_UTCL2_RET = 334
PERF_UTCL1_UTCL2_INFLIGHT = 335
PERF_CLIENT_UTCL1_INFLIGHT = 336
PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 337
PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 338
PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 339
PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 340
PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 341
PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 342
PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 343
PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 344
PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 345
PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 346
PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 347
PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 348
PERF_PA_VERTEX_FIFO_FULL = 349
PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 350
PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 351
PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 352
ENGG_CSB_MACHINE_IS_STARVED = 355
ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 356
ENGG_CSB_MACHINE_STALLED_BY_SPI = 357
ENGG_CSB_GE_INPUT_FIFO_FULL = 358
ENGG_CSB_SPI_INPUT_FIFO_FULL = 359
ENGG_CSB_OBJECTID_INPUT_FIFO_FULL = 360
ENGG_CSB_PRIM_COUNT_EQ0 = 361
ENGG_CSB_GE_SENDING_SUBGROUP = 362
ENGG_CSB_DELAY_BIN00 = 363
ENGG_CSB_DELAY_BIN01 = 364
ENGG_CSB_DELAY_BIN02 = 365
ENGG_CSB_DELAY_BIN03 = 366
ENGG_CSB_DELAY_BIN04 = 367
ENGG_CSB_DELAY_BIN05 = 368
ENGG_CSB_DELAY_BIN06 = 369
ENGG_CSB_DELAY_BIN07 = 370
ENGG_CSB_DELAY_BIN08 = 371
ENGG_CSB_DELAY_BIN09 = 372
ENGG_CSB_DELAY_BIN10 = 373
ENGG_CSB_DELAY_BIN11 = 374
ENGG_CSB_DELAY_BIN12 = 375
ENGG_CSB_DELAY_BIN13 = 376
ENGG_CSB_DELAY_BIN14 = 377
ENGG_CSB_DELAY_BIN15 = 378
ENGG_CSB_SPI_DELAY_BIN00 = 379
ENGG_CSB_SPI_DELAY_BIN01 = 380
ENGG_CSB_SPI_DELAY_BIN02 = 381
ENGG_CSB_SPI_DELAY_BIN03 = 382
ENGG_CSB_SPI_DELAY_BIN04 = 383
ENGG_CSB_SPI_DELAY_BIN05 = 384
ENGG_CSB_SPI_DELAY_BIN06 = 385
ENGG_CSB_SPI_DELAY_BIN07 = 386
ENGG_CSB_SPI_DELAY_BIN08 = 387
ENGG_CSB_SPI_DELAY_BIN09 = 388
ENGG_CSB_SPI_DELAY_BIN10 = 389
ENGG_CSB_SPI_DELAY_BIN11 = 390
ENGG_CSB_SPI_DELAY_BIN12 = 391
ENGG_CSB_SPI_DELAY_BIN13 = 392
ENGG_CSB_SPI_DELAY_BIN14 = 393
ENGG_CSB_SPI_DELAY_BIN15 = 394
ENGG_INDEX_REQ_STARVED = 395
ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 396
ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 397
ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 398
ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 399
ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 400
ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 401
ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 402
ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 403
ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 404
ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 405
ENGG_INDEX_RET_SXRX_READING_EVENT = 406
ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 407
ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 408
ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 409
ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 410
ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 411
ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 412
ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS = 413
ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS = 414
ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS = 415
ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 416
ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 417
ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 418
ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 419
ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 420
ENGG_INDEX_PRIM_IF_QUALIFIED_BUSY = 421
ENGG_INDEX_PRIM_IF_QUALIFIED_STARVED = 422
ENGG_INDEX_PRIM_IF_REUSE_0_NEW_VERTS_THIS_PRIM = 423
ENGG_INDEX_PRIM_IF_REUSE_1_NEW_VERTS_THIS_PRIM = 424
ENGG_INDEX_PRIM_IF_REUSE_2_NEW_VERTS_THIS_PRIM = 425
ENGG_INDEX_PRIM_IF_REUSE_3_NEW_VERTS_THIS_PRIM = 426
ENGG_POS_REQ_STARVED = 427
ENGG_POS_REQ_STALLED_BY_FULL_CLIPV_FIFO = 428
SU_PERFCNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SC_PERFCNT_SEL'
SC_PERFCNT_SEL__enumvalues = {
0: 'SC_SRPS_WINDOW_VALID',
1: 'SC_PSSW_WINDOW_VALID',
2: 'SC_TPQZ_WINDOW_VALID',
3: 'SC_QZQP_WINDOW_VALID',
4: 'SC_TRPK_WINDOW_VALID',
5: 'SC_SRPS_WINDOW_VALID_BUSY',
6: 'SC_PSSW_WINDOW_VALID_BUSY',
7: 'SC_TPQZ_WINDOW_VALID_BUSY',
8: 'SC_QZQP_WINDOW_VALID_BUSY',
9: 'SC_TRPK_WINDOW_VALID_BUSY',
10: 'SC_STARVED_BY_PA',
11: 'SC_STALLED_BY_PRIMFIFO',
12: 'SC_STALLED_BY_DB_TILE',
13: 'SC_STARVED_BY_DB_TILE',
14: 'SC_STALLED_BY_TILEORDERFIFO',
15: 'SC_STALLED_BY_TILEFIFO',
16: 'SC_STALLED_BY_DB_QUAD',
17: 'SC_STARVED_BY_DB_QUAD',
18: 'SC_STALLED_BY_QUADFIFO',
19: 'SC_STALLED_BY_BCI',
20: 'SC_STALLED_BY_SPI',
21: 'SC_SCISSOR_DISCARD',
22: 'SC_BB_DISCARD',
23: 'SC_SUPERTILE_COUNT',
24: 'SC_SUPERTILE_PER_PRIM_H0',
25: 'SC_SUPERTILE_PER_PRIM_H1',
26: 'SC_SUPERTILE_PER_PRIM_H2',
27: 'SC_SUPERTILE_PER_PRIM_H3',
28: 'SC_SUPERTILE_PER_PRIM_H4',
29: 'SC_SUPERTILE_PER_PRIM_H5',
30: 'SC_SUPERTILE_PER_PRIM_H6',
31: 'SC_SUPERTILE_PER_PRIM_H7',
32: 'SC_SUPERTILE_PER_PRIM_H8',
33: 'SC_SUPERTILE_PER_PRIM_H9',
34: 'SC_SUPERTILE_PER_PRIM_H10',
35: 'SC_SUPERTILE_PER_PRIM_H11',
36: 'SC_SUPERTILE_PER_PRIM_H12',
37: 'SC_SUPERTILE_PER_PRIM_H13',
38: 'SC_SUPERTILE_PER_PRIM_H14',
39: 'SC_SUPERTILE_PER_PRIM_H15',
40: 'SC_SUPERTILE_PER_PRIM_H16',
41: 'SC_TILE_PER_PRIM_H0',
42: 'SC_TILE_PER_PRIM_H1',
43: 'SC_TILE_PER_PRIM_H2',
44: 'SC_TILE_PER_PRIM_H3',
45: 'SC_TILE_PER_PRIM_H4',
46: 'SC_TILE_PER_PRIM_H5',
47: 'SC_TILE_PER_PRIM_H6',
48: 'SC_TILE_PER_PRIM_H7',
49: 'SC_TILE_PER_PRIM_H8',
50: 'SC_TILE_PER_PRIM_H9',
51: 'SC_TILE_PER_PRIM_H10',
52: 'SC_TILE_PER_PRIM_H11',
53: 'SC_TILE_PER_PRIM_H12',
54: 'SC_TILE_PER_PRIM_H13',
55: 'SC_TILE_PER_PRIM_H14',
56: 'SC_TILE_PER_PRIM_H15',
57: 'SC_TILE_PER_PRIM_H16',
58: 'SC_TILE_PER_SUPERTILE_H0',
59: 'SC_TILE_PER_SUPERTILE_H1',
60: 'SC_TILE_PER_SUPERTILE_H2',
61: 'SC_TILE_PER_SUPERTILE_H3',
62: 'SC_TILE_PER_SUPERTILE_H4',
63: 'SC_TILE_PER_SUPERTILE_H5',
64: 'SC_TILE_PER_SUPERTILE_H6',
65: 'SC_TILE_PER_SUPERTILE_H7',
66: 'SC_TILE_PER_SUPERTILE_H8',
67: 'SC_TILE_PER_SUPERTILE_H9',
68: 'SC_TILE_PER_SUPERTILE_H10',
69: 'SC_TILE_PER_SUPERTILE_H11',
70: 'SC_TILE_PER_SUPERTILE_H12',
71: 'SC_TILE_PER_SUPERTILE_H13',
72: 'SC_TILE_PER_SUPERTILE_H14',
73: 'SC_TILE_PER_SUPERTILE_H15',
74: 'SC_TILE_PER_SUPERTILE_H16',
75: 'SC_TILE_PICKED_H1',
76: 'SC_TILE_PICKED_H2',
77: 'SC_TILE_PICKED_H3',
78: 'SC_TILE_PICKED_H4',
79: 'SC_QZ0_TILE_COUNT',
80: 'SC_QZ1_TILE_COUNT',
81: 'SC_QZ2_TILE_COUNT',
82: 'SC_QZ3_TILE_COUNT',
83: 'SC_QZ0_TILE_COVERED_COUNT',
84: 'SC_QZ1_TILE_COVERED_COUNT',
85: 'SC_QZ2_TILE_COVERED_COUNT',
86: 'SC_QZ3_TILE_COVERED_COUNT',
87: 'SC_QZ0_TILE_NOT_COVERED_COUNT',
88: 'SC_QZ1_TILE_NOT_COVERED_COUNT',
89: 'SC_QZ2_TILE_NOT_COVERED_COUNT',
90: 'SC_QZ3_TILE_NOT_COVERED_COUNT',
91: 'SC_QZ0_QUAD_PER_TILE_H0',
92: 'SC_QZ0_QUAD_PER_TILE_H1',
93: 'SC_QZ0_QUAD_PER_TILE_H2',
94: 'SC_QZ0_QUAD_PER_TILE_H3',
95: 'SC_QZ0_QUAD_PER_TILE_H4',
96: 'SC_QZ0_QUAD_PER_TILE_H5',
97: 'SC_QZ0_QUAD_PER_TILE_H6',
98: 'SC_QZ0_QUAD_PER_TILE_H7',
99: 'SC_QZ0_QUAD_PER_TILE_H8',
100: 'SC_QZ0_QUAD_PER_TILE_H9',
101: 'SC_QZ0_QUAD_PER_TILE_H10',
102: 'SC_QZ0_QUAD_PER_TILE_H11',
103: 'SC_QZ0_QUAD_PER_TILE_H12',
104: 'SC_QZ0_QUAD_PER_TILE_H13',
105: 'SC_QZ0_QUAD_PER_TILE_H14',
106: 'SC_QZ0_QUAD_PER_TILE_H15',
107: 'SC_QZ0_QUAD_PER_TILE_H16',
108: 'SC_QZ1_QUAD_PER_TILE_H0',
109: 'SC_QZ1_QUAD_PER_TILE_H1',
110: 'SC_QZ1_QUAD_PER_TILE_H2',
111: 'SC_QZ1_QUAD_PER_TILE_H3',
112: 'SC_QZ1_QUAD_PER_TILE_H4',
113: 'SC_QZ1_QUAD_PER_TILE_H5',
114: 'SC_QZ1_QUAD_PER_TILE_H6',
115: 'SC_QZ1_QUAD_PER_TILE_H7',
116: 'SC_QZ1_QUAD_PER_TILE_H8',
117: 'SC_QZ1_QUAD_PER_TILE_H9',
118: 'SC_QZ1_QUAD_PER_TILE_H10',
119: 'SC_QZ1_QUAD_PER_TILE_H11',
120: 'SC_QZ1_QUAD_PER_TILE_H12',
121: 'SC_QZ1_QUAD_PER_TILE_H13',
122: 'SC_QZ1_QUAD_PER_TILE_H14',
123: 'SC_QZ1_QUAD_PER_TILE_H15',
124: 'SC_QZ1_QUAD_PER_TILE_H16',
125: 'SC_QZ2_QUAD_PER_TILE_H0',
126: 'SC_QZ2_QUAD_PER_TILE_H1',
127: 'SC_QZ2_QUAD_PER_TILE_H2',
128: 'SC_QZ2_QUAD_PER_TILE_H3',
129: 'SC_QZ2_QUAD_PER_TILE_H4',
130: 'SC_QZ2_QUAD_PER_TILE_H5',
131: 'SC_QZ2_QUAD_PER_TILE_H6',
132: 'SC_QZ2_QUAD_PER_TILE_H7',
133: 'SC_QZ2_QUAD_PER_TILE_H8',
134: 'SC_QZ2_QUAD_PER_TILE_H9',
135: 'SC_QZ2_QUAD_PER_TILE_H10',
136: 'SC_QZ2_QUAD_PER_TILE_H11',
137: 'SC_QZ2_QUAD_PER_TILE_H12',
138: 'SC_QZ2_QUAD_PER_TILE_H13',
139: 'SC_QZ2_QUAD_PER_TILE_H14',
140: 'SC_QZ2_QUAD_PER_TILE_H15',
141: 'SC_QZ2_QUAD_PER_TILE_H16',
142: 'SC_QZ3_QUAD_PER_TILE_H0',
143: 'SC_QZ3_QUAD_PER_TILE_H1',
144: 'SC_QZ3_QUAD_PER_TILE_H2',
145: 'SC_QZ3_QUAD_PER_TILE_H3',
146: 'SC_QZ3_QUAD_PER_TILE_H4',
147: 'SC_QZ3_QUAD_PER_TILE_H5',
148: 'SC_QZ3_QUAD_PER_TILE_H6',
149: 'SC_QZ3_QUAD_PER_TILE_H7',
150: 'SC_QZ3_QUAD_PER_TILE_H8',
151: 'SC_QZ3_QUAD_PER_TILE_H9',
152: 'SC_QZ3_QUAD_PER_TILE_H10',
153: 'SC_QZ3_QUAD_PER_TILE_H11',
154: 'SC_QZ3_QUAD_PER_TILE_H12',
155: 'SC_QZ3_QUAD_PER_TILE_H13',
156: 'SC_QZ3_QUAD_PER_TILE_H14',
157: 'SC_QZ3_QUAD_PER_TILE_H15',
158: 'SC_QZ3_QUAD_PER_TILE_H16',
159: 'SC_QZ0_QUAD_COUNT',
160: 'SC_QZ1_QUAD_COUNT',
161: 'SC_QZ2_QUAD_COUNT',
162: 'SC_QZ3_QUAD_COUNT',
163: 'SC_P0_HIZ_TILE_COUNT',
164: 'SC_P1_HIZ_TILE_COUNT',
165: 'SC_P2_HIZ_TILE_COUNT',
166: 'SC_P3_HIZ_TILE_COUNT',
167: 'SC_P0_HIZ_QUAD_PER_TILE_H0',
168: 'SC_P0_HIZ_QUAD_PER_TILE_H1',
169: 'SC_P0_HIZ_QUAD_PER_TILE_H2',
170: 'SC_P0_HIZ_QUAD_PER_TILE_H3',
171: 'SC_P0_HIZ_QUAD_PER_TILE_H4',
172: 'SC_P0_HIZ_QUAD_PER_TILE_H5',
173: 'SC_P0_HIZ_QUAD_PER_TILE_H6',
174: 'SC_P0_HIZ_QUAD_PER_TILE_H7',
175: 'SC_P0_HIZ_QUAD_PER_TILE_H8',
176: 'SC_P0_HIZ_QUAD_PER_TILE_H9',
177: 'SC_P0_HIZ_QUAD_PER_TILE_H10',
178: 'SC_P0_HIZ_QUAD_PER_TILE_H11',
179: 'SC_P0_HIZ_QUAD_PER_TILE_H12',
180: 'SC_P0_HIZ_QUAD_PER_TILE_H13',
181: 'SC_P0_HIZ_QUAD_PER_TILE_H14',
182: 'SC_P0_HIZ_QUAD_PER_TILE_H15',
183: 'SC_P0_HIZ_QUAD_PER_TILE_H16',
184: 'SC_P1_HIZ_QUAD_PER_TILE_H0',
185: 'SC_P1_HIZ_QUAD_PER_TILE_H1',
186: 'SC_P1_HIZ_QUAD_PER_TILE_H2',
187: 'SC_P1_HIZ_QUAD_PER_TILE_H3',
188: 'SC_P1_HIZ_QUAD_PER_TILE_H4',
189: 'SC_P1_HIZ_QUAD_PER_TILE_H5',
190: 'SC_P1_HIZ_QUAD_PER_TILE_H6',
191: 'SC_P1_HIZ_QUAD_PER_TILE_H7',
192: 'SC_P1_HIZ_QUAD_PER_TILE_H8',
193: 'SC_P1_HIZ_QUAD_PER_TILE_H9',
194: 'SC_P1_HIZ_QUAD_PER_TILE_H10',
195: 'SC_P1_HIZ_QUAD_PER_TILE_H11',
196: 'SC_P1_HIZ_QUAD_PER_TILE_H12',
197: 'SC_P1_HIZ_QUAD_PER_TILE_H13',
198: 'SC_P1_HIZ_QUAD_PER_TILE_H14',
199: 'SC_P1_HIZ_QUAD_PER_TILE_H15',
200: 'SC_P1_HIZ_QUAD_PER_TILE_H16',
201: 'SC_P2_HIZ_QUAD_PER_TILE_H0',
202: 'SC_P2_HIZ_QUAD_PER_TILE_H1',
203: 'SC_P2_HIZ_QUAD_PER_TILE_H2',
204: 'SC_P2_HIZ_QUAD_PER_TILE_H3',
205: 'SC_P2_HIZ_QUAD_PER_TILE_H4',
206: 'SC_P2_HIZ_QUAD_PER_TILE_H5',
207: 'SC_P2_HIZ_QUAD_PER_TILE_H6',
208: 'SC_P2_HIZ_QUAD_PER_TILE_H7',
209: 'SC_P2_HIZ_QUAD_PER_TILE_H8',
210: 'SC_P2_HIZ_QUAD_PER_TILE_H9',
211: 'SC_P2_HIZ_QUAD_PER_TILE_H10',
212: 'SC_P2_HIZ_QUAD_PER_TILE_H11',
213: 'SC_P2_HIZ_QUAD_PER_TILE_H12',
214: 'SC_P2_HIZ_QUAD_PER_TILE_H13',
215: 'SC_P2_HIZ_QUAD_PER_TILE_H14',
216: 'SC_P2_HIZ_QUAD_PER_TILE_H15',
217: 'SC_P2_HIZ_QUAD_PER_TILE_H16',
218: 'SC_P3_HIZ_QUAD_PER_TILE_H0',
219: 'SC_P3_HIZ_QUAD_PER_TILE_H1',
220: 'SC_P3_HIZ_QUAD_PER_TILE_H2',
221: 'SC_P3_HIZ_QUAD_PER_TILE_H3',
222: 'SC_P3_HIZ_QUAD_PER_TILE_H4',
223: 'SC_P3_HIZ_QUAD_PER_TILE_H5',
224: 'SC_P3_HIZ_QUAD_PER_TILE_H6',
225: 'SC_P3_HIZ_QUAD_PER_TILE_H7',
226: 'SC_P3_HIZ_QUAD_PER_TILE_H8',
227: 'SC_P3_HIZ_QUAD_PER_TILE_H9',
228: 'SC_P3_HIZ_QUAD_PER_TILE_H10',
229: 'SC_P3_HIZ_QUAD_PER_TILE_H11',
230: 'SC_P3_HIZ_QUAD_PER_TILE_H12',
231: 'SC_P3_HIZ_QUAD_PER_TILE_H13',
232: 'SC_P3_HIZ_QUAD_PER_TILE_H14',
233: 'SC_P3_HIZ_QUAD_PER_TILE_H15',
234: 'SC_P3_HIZ_QUAD_PER_TILE_H16',
235: 'SC_P0_HIZ_QUAD_COUNT',
236: 'SC_P1_HIZ_QUAD_COUNT',
237: 'SC_P2_HIZ_QUAD_COUNT',
238: 'SC_P3_HIZ_QUAD_COUNT',
239: 'SC_P0_DETAIL_QUAD_COUNT',
240: 'SC_P1_DETAIL_QUAD_COUNT',
241: 'SC_P2_DETAIL_QUAD_COUNT',
242: 'SC_P3_DETAIL_QUAD_COUNT',
243: 'SC_P0_DETAIL_QUAD_WITH_1_PIX',
244: 'SC_P0_DETAIL_QUAD_WITH_2_PIX',
245: 'SC_P0_DETAIL_QUAD_WITH_3_PIX',
246: 'SC_P0_DETAIL_QUAD_WITH_4_PIX',
247: 'SC_P1_DETAIL_QUAD_WITH_1_PIX',
248: 'SC_P1_DETAIL_QUAD_WITH_2_PIX',
249: 'SC_P1_DETAIL_QUAD_WITH_3_PIX',
250: 'SC_P1_DETAIL_QUAD_WITH_4_PIX',
251: 'SC_P2_DETAIL_QUAD_WITH_1_PIX',
252: 'SC_P2_DETAIL_QUAD_WITH_2_PIX',
253: 'SC_P2_DETAIL_QUAD_WITH_3_PIX',
254: 'SC_P2_DETAIL_QUAD_WITH_4_PIX',
255: 'SC_P3_DETAIL_QUAD_WITH_1_PIX',
256: 'SC_P3_DETAIL_QUAD_WITH_2_PIX',
257: 'SC_P3_DETAIL_QUAD_WITH_3_PIX',
258: 'SC_P3_DETAIL_QUAD_WITH_4_PIX',
259: 'SC_EARLYZ_QUAD_COUNT',
260: 'SC_EARLYZ_QUAD_WITH_1_PIX',
261: 'SC_EARLYZ_QUAD_WITH_2_PIX',
262: 'SC_EARLYZ_QUAD_WITH_3_PIX',
263: 'SC_EARLYZ_QUAD_WITH_4_PIX',
264: 'SC_PKR_QUAD_PER_ROW_H1',
265: 'SC_PKR_QUAD_PER_ROW_H2',
266: 'SC_PKR_4X2_QUAD_SPLIT',
267: 'SC_PKR_4X2_FILL_QUAD',
268: 'SC_PKR_END_OF_VECTOR',
269: 'SC_PKR_CONTROL_XFER',
270: 'SC_PKR_DBHANG_FORCE_EOV',
271: 'SC_REG_SCLK_BUSY',
272: 'SC_GRP0_DYN_SCLK_BUSY',
273: 'SC_GRP1_DYN_SCLK_BUSY',
274: 'SC_GRP2_DYN_SCLK_BUSY',
275: 'SC_GRP3_DYN_SCLK_BUSY',
276: 'SC_GRP4_DYN_SCLK_BUSY',
277: 'SC_PA0_SC_DATA_FIFO_RD',
278: 'SC_PA0_SC_DATA_FIFO_WE',
279: 'SC_PA1_SC_DATA_FIFO_RD',
280: 'SC_PA1_SC_DATA_FIFO_WE',
281: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
282: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES',
283: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
284: 'SC_PS_ARB_STALLED_FROM_BELOW',
285: 'SC_PS_ARB_STARVED_FROM_ABOVE',
286: 'SC_PS_ARB_SC_BUSY',
287: 'SC_PS_ARB_PA_SC_BUSY',
288: 'SC_PA2_SC_DATA_FIFO_RD',
289: 'SC_PA2_SC_DATA_FIFO_WE',
290: 'SC_PA3_SC_DATA_FIFO_RD',
291: 'SC_PA3_SC_DATA_FIFO_WE',
292: 'SC_PA_SC_DEALLOC_0_0_WE',
293: 'SC_PA_SC_DEALLOC_0_1_WE',
294: 'SC_PA_SC_DEALLOC_1_0_WE',
295: 'SC_PA_SC_DEALLOC_1_1_WE',
296: 'SC_PA_SC_DEALLOC_2_0_WE',
297: 'SC_PA_SC_DEALLOC_2_1_WE',
298: 'SC_PA_SC_DEALLOC_3_0_WE',
299: 'SC_PA_SC_DEALLOC_3_1_WE',
300: 'SC_PA0_SC_EOP_WE',
301: 'SC_PA0_SC_EOPG_WE',
302: 'SC_PA0_SC_EVENT_WE',
303: 'SC_PA1_SC_EOP_WE',
304: 'SC_PA1_SC_EOPG_WE',
305: 'SC_PA1_SC_EVENT_WE',
306: 'SC_PA2_SC_EOP_WE',
307: 'SC_PA2_SC_EOPG_WE',
308: 'SC_PA2_SC_EVENT_WE',
309: 'SC_PA3_SC_EOP_WE',
310: 'SC_PA3_SC_EOPG_WE',
311: 'SC_PA3_SC_EVENT_WE',
312: 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO',
313: 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH',
314: 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP',
315: 'SC_PS_ARB_EOP_POP_SYNC_POP',
316: 'SC_PS_ARB_EVENT_SYNC_POP',
317: 'SC_SC_PS_ENG_MULTICYCLE_BUBBLE',
318: 'SC_PA0_SC_FPOV_WE',
319: 'SC_PA1_SC_FPOV_WE',
320: 'SC_PA2_SC_FPOV_WE',
321: 'SC_PA3_SC_FPOV_WE',
322: 'SC_PA0_SC_LPOV_WE',
323: 'SC_PA1_SC_LPOV_WE',
324: 'SC_PA2_SC_LPOV_WE',
325: 'SC_PA3_SC_LPOV_WE',
326: 'SC_SC_SPI_DEALLOC_0_0',
327: 'SC_SC_SPI_DEALLOC_0_1',
328: 'SC_SC_SPI_DEALLOC_0_2',
329: 'SC_SC_SPI_DEALLOC_1_0',
330: 'SC_SC_SPI_DEALLOC_1_1',
331: 'SC_SC_SPI_DEALLOC_1_2',
332: 'SC_SC_SPI_DEALLOC_2_0',
333: 'SC_SC_SPI_DEALLOC_2_1',
334: 'SC_SC_SPI_DEALLOC_2_2',
335: 'SC_SC_SPI_DEALLOC_3_0',
336: 'SC_SC_SPI_DEALLOC_3_1',
337: 'SC_SC_SPI_DEALLOC_3_2',
338: 'SC_SC_SPI_FPOV_0',
339: 'SC_SC_SPI_FPOV_1',
340: 'SC_SC_SPI_FPOV_2',
341: 'SC_SC_SPI_FPOV_3',
342: 'SC_SC_SPI_EVENT',
343: 'SC_PS_TS_EVENT_FIFO_PUSH',
344: 'SC_PS_TS_EVENT_FIFO_POP',
345: 'SC_PS_CTX_DONE_FIFO_PUSH',
346: 'SC_PS_CTX_DONE_FIFO_POP',
347: 'SC_MULTICYCLE_BUBBLE_FREEZE',
348: 'SC_EOP_SYNC_WINDOW',
349: 'SC_PA0_SC_NULL_WE',
350: 'SC_PA0_SC_NULL_DEALLOC_WE',
351: 'SC_PA0_SC_DATA_FIFO_EOPG_RD',
352: 'SC_PA0_SC_DATA_FIFO_EOP_RD',
353: 'SC_PA0_SC_DEALLOC_0_RD',
354: 'SC_PA0_SC_DEALLOC_1_RD',
355: 'SC_PA1_SC_DATA_FIFO_EOPG_RD',
356: 'SC_PA1_SC_DATA_FIFO_EOP_RD',
357: 'SC_PA1_SC_DEALLOC_0_RD',
358: 'SC_PA1_SC_DEALLOC_1_RD',
359: 'SC_PA1_SC_NULL_WE',
360: 'SC_PA1_SC_NULL_DEALLOC_WE',
361: 'SC_PA2_SC_DATA_FIFO_EOPG_RD',
362: 'SC_PA2_SC_DATA_FIFO_EOP_RD',
363: 'SC_PA2_SC_DEALLOC_0_RD',
364: 'SC_PA2_SC_DEALLOC_1_RD',
365: 'SC_PA2_SC_NULL_WE',
366: 'SC_PA2_SC_NULL_DEALLOC_WE',
367: 'SC_PA3_SC_DATA_FIFO_EOPG_RD',
368: 'SC_PA3_SC_DATA_FIFO_EOP_RD',
369: 'SC_PA3_SC_DEALLOC_0_RD',
370: 'SC_PA3_SC_DEALLOC_1_RD',
371: 'SC_PA3_SC_NULL_WE',
372: 'SC_PA3_SC_NULL_DEALLOC_WE',
373: 'SC_PS_PA0_SC_FIFO_EMPTY',
374: 'SC_PS_PA0_SC_FIFO_FULL',
375: 'SC_RESERVED_0',
376: 'SC_PS_PA1_SC_FIFO_EMPTY',
377: 'SC_PS_PA1_SC_FIFO_FULL',
378: 'SC_RESERVED_1',
379: 'SC_PS_PA2_SC_FIFO_EMPTY',
380: 'SC_PS_PA2_SC_FIFO_FULL',
381: 'SC_RESERVED_2',
382: 'SC_PS_PA3_SC_FIFO_EMPTY',
383: 'SC_PS_PA3_SC_FIFO_FULL',
384: 'SC_RESERVED_3',
385: 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM',
386: 'SC_BUSY_CNT_NOT_ZERO',
387: 'SC_BM_BUSY',
388: 'SC_BACKEND_BUSY',
389: 'SC_SCF_SCB_INTERFACE_BUSY',
390: 'SC_SCB_BUSY',
391: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY',
392: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL',
393: 'SC_PBB_BIN_HIST_NUM_PRIMS',
394: 'SC_PBB_BATCH_HIST_NUM_PRIMS',
395: 'SC_PBB_BIN_HIST_NUM_CONTEXTS',
396: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS',
397: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES',
398: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES',
399: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS',
400: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS',
401: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM',
402: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW',
403: 'SC_PBB_BUSY',
404: 'SC_PBB_BUSY_AND_NO_SENDS',
405: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES',
406: 'SC_PBB_NUM_BINS',
407: 'SC_PBB_END_OF_BIN',
408: 'SC_PBB_END_OF_BATCH',
409: 'SC_PBB_PRIMBIN_PROCESSED',
410: 'SC_PBB_PRIM_ADDED_TO_BATCH',
411: 'SC_PBB_NONBINNED_PRIM',
412: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB',
413: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB',
414: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION',
415: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW',
416: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN',
417: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE',
418: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE',
419: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM',
420: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE',
421: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT',
422: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT',
423: 'SC_POPS_INTRA_WAVE_OVERLAPS',
424: 'SC_POPS_FORCE_EOV',
425: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX',
426: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP',
427: 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE',
428: 'SC_FULL_FULL_QUAD',
429: 'SC_FULL_HALF_QUAD',
430: 'SC_FULL_QTR_QUAD',
431: 'SC_HALF_FULL_QUAD',
432: 'SC_HALF_HALF_QUAD',
433: 'SC_HALF_QTR_QUAD',
434: 'SC_QTR_FULL_QUAD',
435: 'SC_QTR_HALF_QUAD',
436: 'SC_QTR_QTR_QUAD',
437: 'SC_GRP5_DYN_SCLK_BUSY',
438: 'SC_GRP6_DYN_SCLK_BUSY',
439: 'SC_GRP7_DYN_SCLK_BUSY',
440: 'SC_GRP8_DYN_SCLK_BUSY',
441: 'SC_GRP9_DYN_SCLK_BUSY',
442: 'SC_PS_TO_BE_SCLK_GATE_STALL',
443: 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL',
444: 'SC_PK_BUSY',
445: 'SC_PK_MAX_DEALLOC_FORCE_EOV',
446: 'SC_PK_DEALLOC_WAVE_BREAK',
447: 'SC_SPI_SEND',
448: 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND',
449: 'SC_SPI_CREDIT_AT_MAX',
450: 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND',
451: 'SC_BCI_SEND',
452: 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND',
453: 'SC_BCI_CREDIT_AT_MAX',
454: 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND',
455: 'SC_SPIBC_FULL_FREEZE',
456: 'SC_PW_BM_PASS_EMPTY_PRIM',
457: 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM',
458: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0',
459: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1',
460: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2',
461: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3',
462: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4',
463: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5',
464: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6',
465: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7',
466: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8',
467: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9',
468: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10',
469: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11',
470: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12',
471: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13',
472: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14',
473: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15',
474: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16',
475: 'SC_DB0_TILE_INTERFACE_BUSY',
476: 'SC_DB0_TILE_INTERFACE_SEND',
477: 'SC_DB0_TILE_INTERFACE_SEND_EVENT',
478: 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT',
479: 'SC_DB0_TILE_INTERFACE_SEND_SOP',
480: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND',
481: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX',
482: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND',
483: 'SC_DB1_TILE_INTERFACE_BUSY',
484: 'SC_DB1_TILE_INTERFACE_SEND',
485: 'SC_DB1_TILE_INTERFACE_SEND_EVENT',
486: 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT',
487: 'SC_DB1_TILE_INTERFACE_SEND_SOP',
488: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND',
489: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX',
490: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND',
491: 'SC_BACKEND_PRIM_FIFO_FULL',
492: 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER',
493: 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH',
494: 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH',
495: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT',
496: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT',
497: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV',
498: 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE',
499: 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE',
500: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT',
}
SC_SRPS_WINDOW_VALID = 0
SC_PSSW_WINDOW_VALID = 1
SC_TPQZ_WINDOW_VALID = 2
SC_QZQP_WINDOW_VALID = 3
SC_TRPK_WINDOW_VALID = 4
SC_SRPS_WINDOW_VALID_BUSY = 5
SC_PSSW_WINDOW_VALID_BUSY = 6
SC_TPQZ_WINDOW_VALID_BUSY = 7
SC_QZQP_WINDOW_VALID_BUSY = 8
SC_TRPK_WINDOW_VALID_BUSY = 9
SC_STARVED_BY_PA = 10
SC_STALLED_BY_PRIMFIFO = 11
SC_STALLED_BY_DB_TILE = 12
SC_STARVED_BY_DB_TILE = 13
SC_STALLED_BY_TILEORDERFIFO = 14
SC_STALLED_BY_TILEFIFO = 15
SC_STALLED_BY_DB_QUAD = 16
SC_STARVED_BY_DB_QUAD = 17
SC_STALLED_BY_QUADFIFO = 18
SC_STALLED_BY_BCI = 19
SC_STALLED_BY_SPI = 20
SC_SCISSOR_DISCARD = 21
SC_BB_DISCARD = 22
SC_SUPERTILE_COUNT = 23
SC_SUPERTILE_PER_PRIM_H0 = 24
SC_SUPERTILE_PER_PRIM_H1 = 25
SC_SUPERTILE_PER_PRIM_H2 = 26
SC_SUPERTILE_PER_PRIM_H3 = 27
SC_SUPERTILE_PER_PRIM_H4 = 28
SC_SUPERTILE_PER_PRIM_H5 = 29
SC_SUPERTILE_PER_PRIM_H6 = 30
SC_SUPERTILE_PER_PRIM_H7 = 31
SC_SUPERTILE_PER_PRIM_H8 = 32
SC_SUPERTILE_PER_PRIM_H9 = 33
SC_SUPERTILE_PER_PRIM_H10 = 34
SC_SUPERTILE_PER_PRIM_H11 = 35
SC_SUPERTILE_PER_PRIM_H12 = 36
SC_SUPERTILE_PER_PRIM_H13 = 37
SC_SUPERTILE_PER_PRIM_H14 = 38
SC_SUPERTILE_PER_PRIM_H15 = 39
SC_SUPERTILE_PER_PRIM_H16 = 40
SC_TILE_PER_PRIM_H0 = 41
SC_TILE_PER_PRIM_H1 = 42
SC_TILE_PER_PRIM_H2 = 43
SC_TILE_PER_PRIM_H3 = 44
SC_TILE_PER_PRIM_H4 = 45
SC_TILE_PER_PRIM_H5 = 46
SC_TILE_PER_PRIM_H6 = 47
SC_TILE_PER_PRIM_H7 = 48
SC_TILE_PER_PRIM_H8 = 49
SC_TILE_PER_PRIM_H9 = 50
SC_TILE_PER_PRIM_H10 = 51
SC_TILE_PER_PRIM_H11 = 52
SC_TILE_PER_PRIM_H12 = 53
SC_TILE_PER_PRIM_H13 = 54
SC_TILE_PER_PRIM_H14 = 55
SC_TILE_PER_PRIM_H15 = 56
SC_TILE_PER_PRIM_H16 = 57
SC_TILE_PER_SUPERTILE_H0 = 58
SC_TILE_PER_SUPERTILE_H1 = 59
SC_TILE_PER_SUPERTILE_H2 = 60
SC_TILE_PER_SUPERTILE_H3 = 61
SC_TILE_PER_SUPERTILE_H4 = 62
SC_TILE_PER_SUPERTILE_H5 = 63
SC_TILE_PER_SUPERTILE_H6 = 64
SC_TILE_PER_SUPERTILE_H7 = 65
SC_TILE_PER_SUPERTILE_H8 = 66
SC_TILE_PER_SUPERTILE_H9 = 67
SC_TILE_PER_SUPERTILE_H10 = 68
SC_TILE_PER_SUPERTILE_H11 = 69
SC_TILE_PER_SUPERTILE_H12 = 70
SC_TILE_PER_SUPERTILE_H13 = 71
SC_TILE_PER_SUPERTILE_H14 = 72
SC_TILE_PER_SUPERTILE_H15 = 73
SC_TILE_PER_SUPERTILE_H16 = 74
SC_TILE_PICKED_H1 = 75
SC_TILE_PICKED_H2 = 76
SC_TILE_PICKED_H3 = 77
SC_TILE_PICKED_H4 = 78
SC_QZ0_TILE_COUNT = 79
SC_QZ1_TILE_COUNT = 80
SC_QZ2_TILE_COUNT = 81
SC_QZ3_TILE_COUNT = 82
SC_QZ0_TILE_COVERED_COUNT = 83
SC_QZ1_TILE_COVERED_COUNT = 84
SC_QZ2_TILE_COVERED_COUNT = 85
SC_QZ3_TILE_COVERED_COUNT = 86
SC_QZ0_TILE_NOT_COVERED_COUNT = 87
SC_QZ1_TILE_NOT_COVERED_COUNT = 88
SC_QZ2_TILE_NOT_COVERED_COUNT = 89
SC_QZ3_TILE_NOT_COVERED_COUNT = 90
SC_QZ0_QUAD_PER_TILE_H0 = 91
SC_QZ0_QUAD_PER_TILE_H1 = 92
SC_QZ0_QUAD_PER_TILE_H2 = 93
SC_QZ0_QUAD_PER_TILE_H3 = 94
SC_QZ0_QUAD_PER_TILE_H4 = 95
SC_QZ0_QUAD_PER_TILE_H5 = 96
SC_QZ0_QUAD_PER_TILE_H6 = 97
SC_QZ0_QUAD_PER_TILE_H7 = 98
SC_QZ0_QUAD_PER_TILE_H8 = 99
SC_QZ0_QUAD_PER_TILE_H9 = 100
SC_QZ0_QUAD_PER_TILE_H10 = 101
SC_QZ0_QUAD_PER_TILE_H11 = 102
SC_QZ0_QUAD_PER_TILE_H12 = 103
SC_QZ0_QUAD_PER_TILE_H13 = 104
SC_QZ0_QUAD_PER_TILE_H14 = 105
SC_QZ0_QUAD_PER_TILE_H15 = 106
SC_QZ0_QUAD_PER_TILE_H16 = 107
SC_QZ1_QUAD_PER_TILE_H0 = 108
SC_QZ1_QUAD_PER_TILE_H1 = 109
SC_QZ1_QUAD_PER_TILE_H2 = 110
SC_QZ1_QUAD_PER_TILE_H3 = 111
SC_QZ1_QUAD_PER_TILE_H4 = 112
SC_QZ1_QUAD_PER_TILE_H5 = 113
SC_QZ1_QUAD_PER_TILE_H6 = 114
SC_QZ1_QUAD_PER_TILE_H7 = 115
SC_QZ1_QUAD_PER_TILE_H8 = 116
SC_QZ1_QUAD_PER_TILE_H9 = 117
SC_QZ1_QUAD_PER_TILE_H10 = 118
SC_QZ1_QUAD_PER_TILE_H11 = 119
SC_QZ1_QUAD_PER_TILE_H12 = 120
SC_QZ1_QUAD_PER_TILE_H13 = 121
SC_QZ1_QUAD_PER_TILE_H14 = 122
SC_QZ1_QUAD_PER_TILE_H15 = 123
SC_QZ1_QUAD_PER_TILE_H16 = 124
SC_QZ2_QUAD_PER_TILE_H0 = 125
SC_QZ2_QUAD_PER_TILE_H1 = 126
SC_QZ2_QUAD_PER_TILE_H2 = 127
SC_QZ2_QUAD_PER_TILE_H3 = 128
SC_QZ2_QUAD_PER_TILE_H4 = 129
SC_QZ2_QUAD_PER_TILE_H5 = 130
SC_QZ2_QUAD_PER_TILE_H6 = 131
SC_QZ2_QUAD_PER_TILE_H7 = 132
SC_QZ2_QUAD_PER_TILE_H8 = 133
SC_QZ2_QUAD_PER_TILE_H9 = 134
SC_QZ2_QUAD_PER_TILE_H10 = 135
SC_QZ2_QUAD_PER_TILE_H11 = 136
SC_QZ2_QUAD_PER_TILE_H12 = 137
SC_QZ2_QUAD_PER_TILE_H13 = 138
SC_QZ2_QUAD_PER_TILE_H14 = 139
SC_QZ2_QUAD_PER_TILE_H15 = 140
SC_QZ2_QUAD_PER_TILE_H16 = 141
SC_QZ3_QUAD_PER_TILE_H0 = 142
SC_QZ3_QUAD_PER_TILE_H1 = 143
SC_QZ3_QUAD_PER_TILE_H2 = 144
SC_QZ3_QUAD_PER_TILE_H3 = 145
SC_QZ3_QUAD_PER_TILE_H4 = 146
SC_QZ3_QUAD_PER_TILE_H5 = 147
SC_QZ3_QUAD_PER_TILE_H6 = 148
SC_QZ3_QUAD_PER_TILE_H7 = 149
SC_QZ3_QUAD_PER_TILE_H8 = 150
SC_QZ3_QUAD_PER_TILE_H9 = 151
SC_QZ3_QUAD_PER_TILE_H10 = 152
SC_QZ3_QUAD_PER_TILE_H11 = 153
SC_QZ3_QUAD_PER_TILE_H12 = 154
SC_QZ3_QUAD_PER_TILE_H13 = 155
SC_QZ3_QUAD_PER_TILE_H14 = 156
SC_QZ3_QUAD_PER_TILE_H15 = 157
SC_QZ3_QUAD_PER_TILE_H16 = 158
SC_QZ0_QUAD_COUNT = 159
SC_QZ1_QUAD_COUNT = 160
SC_QZ2_QUAD_COUNT = 161
SC_QZ3_QUAD_COUNT = 162
SC_P0_HIZ_TILE_COUNT = 163
SC_P1_HIZ_TILE_COUNT = 164
SC_P2_HIZ_TILE_COUNT = 165
SC_P3_HIZ_TILE_COUNT = 166
SC_P0_HIZ_QUAD_PER_TILE_H0 = 167
SC_P0_HIZ_QUAD_PER_TILE_H1 = 168
SC_P0_HIZ_QUAD_PER_TILE_H2 = 169
SC_P0_HIZ_QUAD_PER_TILE_H3 = 170
SC_P0_HIZ_QUAD_PER_TILE_H4 = 171
SC_P0_HIZ_QUAD_PER_TILE_H5 = 172
SC_P0_HIZ_QUAD_PER_TILE_H6 = 173
SC_P0_HIZ_QUAD_PER_TILE_H7 = 174
SC_P0_HIZ_QUAD_PER_TILE_H8 = 175
SC_P0_HIZ_QUAD_PER_TILE_H9 = 176
SC_P0_HIZ_QUAD_PER_TILE_H10 = 177
SC_P0_HIZ_QUAD_PER_TILE_H11 = 178
SC_P0_HIZ_QUAD_PER_TILE_H12 = 179
SC_P0_HIZ_QUAD_PER_TILE_H13 = 180
SC_P0_HIZ_QUAD_PER_TILE_H14 = 181
SC_P0_HIZ_QUAD_PER_TILE_H15 = 182
SC_P0_HIZ_QUAD_PER_TILE_H16 = 183
SC_P1_HIZ_QUAD_PER_TILE_H0 = 184
SC_P1_HIZ_QUAD_PER_TILE_H1 = 185
SC_P1_HIZ_QUAD_PER_TILE_H2 = 186
SC_P1_HIZ_QUAD_PER_TILE_H3 = 187
SC_P1_HIZ_QUAD_PER_TILE_H4 = 188
SC_P1_HIZ_QUAD_PER_TILE_H5 = 189
SC_P1_HIZ_QUAD_PER_TILE_H6 = 190
SC_P1_HIZ_QUAD_PER_TILE_H7 = 191
SC_P1_HIZ_QUAD_PER_TILE_H8 = 192
SC_P1_HIZ_QUAD_PER_TILE_H9 = 193
SC_P1_HIZ_QUAD_PER_TILE_H10 = 194
SC_P1_HIZ_QUAD_PER_TILE_H11 = 195
SC_P1_HIZ_QUAD_PER_TILE_H12 = 196
SC_P1_HIZ_QUAD_PER_TILE_H13 = 197
SC_P1_HIZ_QUAD_PER_TILE_H14 = 198
SC_P1_HIZ_QUAD_PER_TILE_H15 = 199
SC_P1_HIZ_QUAD_PER_TILE_H16 = 200
SC_P2_HIZ_QUAD_PER_TILE_H0 = 201
SC_P2_HIZ_QUAD_PER_TILE_H1 = 202
SC_P2_HIZ_QUAD_PER_TILE_H2 = 203
SC_P2_HIZ_QUAD_PER_TILE_H3 = 204
SC_P2_HIZ_QUAD_PER_TILE_H4 = 205
SC_P2_HIZ_QUAD_PER_TILE_H5 = 206
SC_P2_HIZ_QUAD_PER_TILE_H6 = 207
SC_P2_HIZ_QUAD_PER_TILE_H7 = 208
SC_P2_HIZ_QUAD_PER_TILE_H8 = 209
SC_P2_HIZ_QUAD_PER_TILE_H9 = 210
SC_P2_HIZ_QUAD_PER_TILE_H10 = 211
SC_P2_HIZ_QUAD_PER_TILE_H11 = 212
SC_P2_HIZ_QUAD_PER_TILE_H12 = 213
SC_P2_HIZ_QUAD_PER_TILE_H13 = 214
SC_P2_HIZ_QUAD_PER_TILE_H14 = 215
SC_P2_HIZ_QUAD_PER_TILE_H15 = 216
SC_P2_HIZ_QUAD_PER_TILE_H16 = 217
SC_P3_HIZ_QUAD_PER_TILE_H0 = 218
SC_P3_HIZ_QUAD_PER_TILE_H1 = 219
SC_P3_HIZ_QUAD_PER_TILE_H2 = 220
SC_P3_HIZ_QUAD_PER_TILE_H3 = 221
SC_P3_HIZ_QUAD_PER_TILE_H4 = 222
SC_P3_HIZ_QUAD_PER_TILE_H5 = 223
SC_P3_HIZ_QUAD_PER_TILE_H6 = 224
SC_P3_HIZ_QUAD_PER_TILE_H7 = 225
SC_P3_HIZ_QUAD_PER_TILE_H8 = 226
SC_P3_HIZ_QUAD_PER_TILE_H9 = 227
SC_P3_HIZ_QUAD_PER_TILE_H10 = 228
SC_P3_HIZ_QUAD_PER_TILE_H11 = 229
SC_P3_HIZ_QUAD_PER_TILE_H12 = 230
SC_P3_HIZ_QUAD_PER_TILE_H13 = 231
SC_P3_HIZ_QUAD_PER_TILE_H14 = 232
SC_P3_HIZ_QUAD_PER_TILE_H15 = 233
SC_P3_HIZ_QUAD_PER_TILE_H16 = 234
SC_P0_HIZ_QUAD_COUNT = 235
SC_P1_HIZ_QUAD_COUNT = 236
SC_P2_HIZ_QUAD_COUNT = 237
SC_P3_HIZ_QUAD_COUNT = 238
SC_P0_DETAIL_QUAD_COUNT = 239
SC_P1_DETAIL_QUAD_COUNT = 240
SC_P2_DETAIL_QUAD_COUNT = 241
SC_P3_DETAIL_QUAD_COUNT = 242
SC_P0_DETAIL_QUAD_WITH_1_PIX = 243
SC_P0_DETAIL_QUAD_WITH_2_PIX = 244
SC_P0_DETAIL_QUAD_WITH_3_PIX = 245
SC_P0_DETAIL_QUAD_WITH_4_PIX = 246
SC_P1_DETAIL_QUAD_WITH_1_PIX = 247
SC_P1_DETAIL_QUAD_WITH_2_PIX = 248
SC_P1_DETAIL_QUAD_WITH_3_PIX = 249
SC_P1_DETAIL_QUAD_WITH_4_PIX = 250
SC_P2_DETAIL_QUAD_WITH_1_PIX = 251
SC_P2_DETAIL_QUAD_WITH_2_PIX = 252
SC_P2_DETAIL_QUAD_WITH_3_PIX = 253
SC_P2_DETAIL_QUAD_WITH_4_PIX = 254
SC_P3_DETAIL_QUAD_WITH_1_PIX = 255
SC_P3_DETAIL_QUAD_WITH_2_PIX = 256
SC_P3_DETAIL_QUAD_WITH_3_PIX = 257
SC_P3_DETAIL_QUAD_WITH_4_PIX = 258
SC_EARLYZ_QUAD_COUNT = 259
SC_EARLYZ_QUAD_WITH_1_PIX = 260
SC_EARLYZ_QUAD_WITH_2_PIX = 261
SC_EARLYZ_QUAD_WITH_3_PIX = 262
SC_EARLYZ_QUAD_WITH_4_PIX = 263
SC_PKR_QUAD_PER_ROW_H1 = 264
SC_PKR_QUAD_PER_ROW_H2 = 265
SC_PKR_4X2_QUAD_SPLIT = 266
SC_PKR_4X2_FILL_QUAD = 267
SC_PKR_END_OF_VECTOR = 268
SC_PKR_CONTROL_XFER = 269
SC_PKR_DBHANG_FORCE_EOV = 270
SC_REG_SCLK_BUSY = 271
SC_GRP0_DYN_SCLK_BUSY = 272
SC_GRP1_DYN_SCLK_BUSY = 273
SC_GRP2_DYN_SCLK_BUSY = 274
SC_GRP3_DYN_SCLK_BUSY = 275
SC_GRP4_DYN_SCLK_BUSY = 276
SC_PA0_SC_DATA_FIFO_RD = 277
SC_PA0_SC_DATA_FIFO_WE = 278
SC_PA1_SC_DATA_FIFO_RD = 279
SC_PA1_SC_DATA_FIFO_WE = 280
SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 281
SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 282
SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 283
SC_PS_ARB_STALLED_FROM_BELOW = 284
SC_PS_ARB_STARVED_FROM_ABOVE = 285
SC_PS_ARB_SC_BUSY = 286
SC_PS_ARB_PA_SC_BUSY = 287
SC_PA2_SC_DATA_FIFO_RD = 288
SC_PA2_SC_DATA_FIFO_WE = 289
SC_PA3_SC_DATA_FIFO_RD = 290
SC_PA3_SC_DATA_FIFO_WE = 291
SC_PA_SC_DEALLOC_0_0_WE = 292
SC_PA_SC_DEALLOC_0_1_WE = 293
SC_PA_SC_DEALLOC_1_0_WE = 294
SC_PA_SC_DEALLOC_1_1_WE = 295
SC_PA_SC_DEALLOC_2_0_WE = 296
SC_PA_SC_DEALLOC_2_1_WE = 297
SC_PA_SC_DEALLOC_3_0_WE = 298
SC_PA_SC_DEALLOC_3_1_WE = 299
SC_PA0_SC_EOP_WE = 300
SC_PA0_SC_EOPG_WE = 301
SC_PA0_SC_EVENT_WE = 302
SC_PA1_SC_EOP_WE = 303
SC_PA1_SC_EOPG_WE = 304
SC_PA1_SC_EVENT_WE = 305
SC_PA2_SC_EOP_WE = 306
SC_PA2_SC_EOPG_WE = 307
SC_PA2_SC_EVENT_WE = 308
SC_PA3_SC_EOP_WE = 309
SC_PA3_SC_EOPG_WE = 310
SC_PA3_SC_EVENT_WE = 311
SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 312
SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 313
SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 314
SC_PS_ARB_EOP_POP_SYNC_POP = 315
SC_PS_ARB_EVENT_SYNC_POP = 316
SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 317
SC_PA0_SC_FPOV_WE = 318
SC_PA1_SC_FPOV_WE = 319
SC_PA2_SC_FPOV_WE = 320
SC_PA3_SC_FPOV_WE = 321
SC_PA0_SC_LPOV_WE = 322
SC_PA1_SC_LPOV_WE = 323
SC_PA2_SC_LPOV_WE = 324
SC_PA3_SC_LPOV_WE = 325
SC_SC_SPI_DEALLOC_0_0 = 326
SC_SC_SPI_DEALLOC_0_1 = 327
SC_SC_SPI_DEALLOC_0_2 = 328
SC_SC_SPI_DEALLOC_1_0 = 329
SC_SC_SPI_DEALLOC_1_1 = 330
SC_SC_SPI_DEALLOC_1_2 = 331
SC_SC_SPI_DEALLOC_2_0 = 332
SC_SC_SPI_DEALLOC_2_1 = 333
SC_SC_SPI_DEALLOC_2_2 = 334
SC_SC_SPI_DEALLOC_3_0 = 335
SC_SC_SPI_DEALLOC_3_1 = 336
SC_SC_SPI_DEALLOC_3_2 = 337
SC_SC_SPI_FPOV_0 = 338
SC_SC_SPI_FPOV_1 = 339
SC_SC_SPI_FPOV_2 = 340
SC_SC_SPI_FPOV_3 = 341
SC_SC_SPI_EVENT = 342
SC_PS_TS_EVENT_FIFO_PUSH = 343
SC_PS_TS_EVENT_FIFO_POP = 344
SC_PS_CTX_DONE_FIFO_PUSH = 345
SC_PS_CTX_DONE_FIFO_POP = 346
SC_MULTICYCLE_BUBBLE_FREEZE = 347
SC_EOP_SYNC_WINDOW = 348
SC_PA0_SC_NULL_WE = 349
SC_PA0_SC_NULL_DEALLOC_WE = 350
SC_PA0_SC_DATA_FIFO_EOPG_RD = 351
SC_PA0_SC_DATA_FIFO_EOP_RD = 352
SC_PA0_SC_DEALLOC_0_RD = 353
SC_PA0_SC_DEALLOC_1_RD = 354
SC_PA1_SC_DATA_FIFO_EOPG_RD = 355
SC_PA1_SC_DATA_FIFO_EOP_RD = 356
SC_PA1_SC_DEALLOC_0_RD = 357
SC_PA1_SC_DEALLOC_1_RD = 358
SC_PA1_SC_NULL_WE = 359
SC_PA1_SC_NULL_DEALLOC_WE = 360
SC_PA2_SC_DATA_FIFO_EOPG_RD = 361
SC_PA2_SC_DATA_FIFO_EOP_RD = 362
SC_PA2_SC_DEALLOC_0_RD = 363
SC_PA2_SC_DEALLOC_1_RD = 364
SC_PA2_SC_NULL_WE = 365
SC_PA2_SC_NULL_DEALLOC_WE = 366
SC_PA3_SC_DATA_FIFO_EOPG_RD = 367
SC_PA3_SC_DATA_FIFO_EOP_RD = 368
SC_PA3_SC_DEALLOC_0_RD = 369
SC_PA3_SC_DEALLOC_1_RD = 370
SC_PA3_SC_NULL_WE = 371
SC_PA3_SC_NULL_DEALLOC_WE = 372
SC_PS_PA0_SC_FIFO_EMPTY = 373
SC_PS_PA0_SC_FIFO_FULL = 374
SC_RESERVED_0 = 375
SC_PS_PA1_SC_FIFO_EMPTY = 376
SC_PS_PA1_SC_FIFO_FULL = 377
SC_RESERVED_1 = 378
SC_PS_PA2_SC_FIFO_EMPTY = 379
SC_PS_PA2_SC_FIFO_FULL = 380
SC_RESERVED_2 = 381
SC_PS_PA3_SC_FIFO_EMPTY = 382
SC_PS_PA3_SC_FIFO_FULL = 383
SC_RESERVED_3 = 384
SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 385
SC_BUSY_CNT_NOT_ZERO = 386
SC_BM_BUSY = 387
SC_BACKEND_BUSY = 388
SC_SCF_SCB_INTERFACE_BUSY = 389
SC_SCB_BUSY = 390
SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 391
SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 392
SC_PBB_BIN_HIST_NUM_PRIMS = 393
SC_PBB_BATCH_HIST_NUM_PRIMS = 394
SC_PBB_BIN_HIST_NUM_CONTEXTS = 395
SC_PBB_BATCH_HIST_NUM_CONTEXTS = 396
SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 397
SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 398
SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 399
SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 400
SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 401
SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 402
SC_PBB_BUSY = 403
SC_PBB_BUSY_AND_NO_SENDS = 404
SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 405
SC_PBB_NUM_BINS = 406
SC_PBB_END_OF_BIN = 407
SC_PBB_END_OF_BATCH = 408
SC_PBB_PRIMBIN_PROCESSED = 409
SC_PBB_PRIM_ADDED_TO_BATCH = 410
SC_PBB_NONBINNED_PRIM = 411
SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 412
SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 413
SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 414
SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 415
SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 416
SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 417
SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 418
SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 419
SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 420
SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 421
SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 422
SC_POPS_INTRA_WAVE_OVERLAPS = 423
SC_POPS_FORCE_EOV = 424
SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 425
SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 426
SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 427
SC_FULL_FULL_QUAD = 428
SC_FULL_HALF_QUAD = 429
SC_FULL_QTR_QUAD = 430
SC_HALF_FULL_QUAD = 431
SC_HALF_HALF_QUAD = 432
SC_HALF_QTR_QUAD = 433
SC_QTR_FULL_QUAD = 434
SC_QTR_HALF_QUAD = 435
SC_QTR_QTR_QUAD = 436
SC_GRP5_DYN_SCLK_BUSY = 437
SC_GRP6_DYN_SCLK_BUSY = 438
SC_GRP7_DYN_SCLK_BUSY = 439
SC_GRP8_DYN_SCLK_BUSY = 440
SC_GRP9_DYN_SCLK_BUSY = 441
SC_PS_TO_BE_SCLK_GATE_STALL = 442
SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 443
SC_PK_BUSY = 444
SC_PK_MAX_DEALLOC_FORCE_EOV = 445
SC_PK_DEALLOC_WAVE_BREAK = 446
SC_SPI_SEND = 447
SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 448
SC_SPI_CREDIT_AT_MAX = 449
SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 450
SC_BCI_SEND = 451
SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 452
SC_BCI_CREDIT_AT_MAX = 453
SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 454
SC_SPIBC_FULL_FREEZE = 455
SC_PW_BM_PASS_EMPTY_PRIM = 456
SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 457
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 458
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 459
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 460
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 461
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 462
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 463
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 464
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 465
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 466
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 467
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 468
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 469
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 470
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 471
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 472
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 473
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 474
SC_DB0_TILE_INTERFACE_BUSY = 475
SC_DB0_TILE_INTERFACE_SEND = 476
SC_DB0_TILE_INTERFACE_SEND_EVENT = 477
SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 478
SC_DB0_TILE_INTERFACE_SEND_SOP = 479
SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 480
SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 481
SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 482
SC_DB1_TILE_INTERFACE_BUSY = 483
SC_DB1_TILE_INTERFACE_SEND = 484
SC_DB1_TILE_INTERFACE_SEND_EVENT = 485
SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 486
SC_DB1_TILE_INTERFACE_SEND_SOP = 487
SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 488
SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 489
SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 490
SC_BACKEND_PRIM_FIFO_FULL = 491
SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 492
SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 493
SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 494
SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 495
SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 496
SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 497
SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 498
SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 499
SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 500
SC_PERFCNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SePairXsel'
SePairXsel__enumvalues = {
0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3
SePairXsel = ctypes.c_uint32 # enum
# values for enumeration 'SePairYsel'
SePairYsel__enumvalues = {
0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3
SePairYsel = ctypes.c_uint32 # enum
# values for enumeration 'SePairMap'
SePairMap__enumvalues = {
0: 'RASTER_CONFIG_SE_PAIR_MAP_0',
1: 'RASTER_CONFIG_SE_PAIR_MAP_1',
2: 'RASTER_CONFIG_SE_PAIR_MAP_2',
3: 'RASTER_CONFIG_SE_PAIR_MAP_3',
}
RASTER_CONFIG_SE_PAIR_MAP_0 = 0
RASTER_CONFIG_SE_PAIR_MAP_1 = 1
RASTER_CONFIG_SE_PAIR_MAP_2 = 2
RASTER_CONFIG_SE_PAIR_MAP_3 = 3
SePairMap = ctypes.c_uint32 # enum
# values for enumeration 'SeXsel'
SeXsel__enumvalues = {
0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3
SeXsel = ctypes.c_uint32 # enum
# values for enumeration 'SeYsel'
SeYsel__enumvalues = {
0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3
SeYsel = ctypes.c_uint32 # enum
# values for enumeration 'SeMap'
SeMap__enumvalues = {
0: 'RASTER_CONFIG_SE_MAP_0',
1: 'RASTER_CONFIG_SE_MAP_1',
2: 'RASTER_CONFIG_SE_MAP_2',
3: 'RASTER_CONFIG_SE_MAP_3',
}
RASTER_CONFIG_SE_MAP_0 = 0
RASTER_CONFIG_SE_MAP_1 = 1
RASTER_CONFIG_SE_MAP_2 = 2
RASTER_CONFIG_SE_MAP_3 = 3
SeMap = ctypes.c_uint32 # enum
# values for enumeration 'ScXsel'
ScXsel__enumvalues = {
0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3
ScXsel = ctypes.c_uint32 # enum
# values for enumeration 'ScYsel'
ScYsel__enumvalues = {
0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3
ScYsel = ctypes.c_uint32 # enum
# values for enumeration 'ScMap'
ScMap__enumvalues = {
0: 'RASTER_CONFIG_SC_MAP_0',
1: 'RASTER_CONFIG_SC_MAP_1',
2: 'RASTER_CONFIG_SC_MAP_2',
3: 'RASTER_CONFIG_SC_MAP_3',
}
RASTER_CONFIG_SC_MAP_0 = 0
RASTER_CONFIG_SC_MAP_1 = 1
RASTER_CONFIG_SC_MAP_2 = 2
RASTER_CONFIG_SC_MAP_3 = 3
ScMap = ctypes.c_uint32 # enum
# values for enumeration 'PkrXsel2'
PkrXsel2__enumvalues = {
0: 'RASTER_CONFIG_PKR_XSEL2_0',
1: 'RASTER_CONFIG_PKR_XSEL2_1',
2: 'RASTER_CONFIG_PKR_XSEL2_2',
3: 'RASTER_CONFIG_PKR_XSEL2_3',
}
RASTER_CONFIG_PKR_XSEL2_0 = 0
RASTER_CONFIG_PKR_XSEL2_1 = 1
RASTER_CONFIG_PKR_XSEL2_2 = 2
RASTER_CONFIG_PKR_XSEL2_3 = 3
PkrXsel2 = ctypes.c_uint32 # enum
# values for enumeration 'PkrXsel'
PkrXsel__enumvalues = {
0: 'RASTER_CONFIG_PKR_XSEL_0',
1: 'RASTER_CONFIG_PKR_XSEL_1',
2: 'RASTER_CONFIG_PKR_XSEL_2',
3: 'RASTER_CONFIG_PKR_XSEL_3',
}
RASTER_CONFIG_PKR_XSEL_0 = 0
RASTER_CONFIG_PKR_XSEL_1 = 1
RASTER_CONFIG_PKR_XSEL_2 = 2
RASTER_CONFIG_PKR_XSEL_3 = 3
PkrXsel = ctypes.c_uint32 # enum
# values for enumeration 'PkrYsel'
PkrYsel__enumvalues = {
0: 'RASTER_CONFIG_PKR_YSEL_0',
1: 'RASTER_CONFIG_PKR_YSEL_1',
2: 'RASTER_CONFIG_PKR_YSEL_2',
3: 'RASTER_CONFIG_PKR_YSEL_3',
}
RASTER_CONFIG_PKR_YSEL_0 = 0
RASTER_CONFIG_PKR_YSEL_1 = 1
RASTER_CONFIG_PKR_YSEL_2 = 2
RASTER_CONFIG_PKR_YSEL_3 = 3
PkrYsel = ctypes.c_uint32 # enum
# values for enumeration 'PkrMap'
PkrMap__enumvalues = {
0: 'RASTER_CONFIG_PKR_MAP_0',
1: 'RASTER_CONFIG_PKR_MAP_1',
2: 'RASTER_CONFIG_PKR_MAP_2',
3: 'RASTER_CONFIG_PKR_MAP_3',
}
RASTER_CONFIG_PKR_MAP_0 = 0
RASTER_CONFIG_PKR_MAP_1 = 1
RASTER_CONFIG_PKR_MAP_2 = 2
RASTER_CONFIG_PKR_MAP_3 = 3
PkrMap = ctypes.c_uint32 # enum
# values for enumeration 'RbXsel'
RbXsel__enumvalues = {
0: 'RASTER_CONFIG_RB_XSEL_0',
1: 'RASTER_CONFIG_RB_XSEL_1',
}
RASTER_CONFIG_RB_XSEL_0 = 0
RASTER_CONFIG_RB_XSEL_1 = 1
RbXsel = ctypes.c_uint32 # enum
# values for enumeration 'RbYsel'
RbYsel__enumvalues = {
0: 'RASTER_CONFIG_RB_YSEL_0',
1: 'RASTER_CONFIG_RB_YSEL_1',
}
RASTER_CONFIG_RB_YSEL_0 = 0
RASTER_CONFIG_RB_YSEL_1 = 1
RbYsel = ctypes.c_uint32 # enum
# values for enumeration 'RbXsel2'
RbXsel2__enumvalues = {
0: 'RASTER_CONFIG_RB_XSEL2_0',
1: 'RASTER_CONFIG_RB_XSEL2_1',
2: 'RASTER_CONFIG_RB_XSEL2_2',
3: 'RASTER_CONFIG_RB_XSEL2_3',
}
RASTER_CONFIG_RB_XSEL2_0 = 0
RASTER_CONFIG_RB_XSEL2_1 = 1
RASTER_CONFIG_RB_XSEL2_2 = 2
RASTER_CONFIG_RB_XSEL2_3 = 3
RbXsel2 = ctypes.c_uint32 # enum
# values for enumeration 'RbMap'
RbMap__enumvalues = {
0: 'RASTER_CONFIG_RB_MAP_0',
1: 'RASTER_CONFIG_RB_MAP_1',
2: 'RASTER_CONFIG_RB_MAP_2',
3: 'RASTER_CONFIG_RB_MAP_3',
}
RASTER_CONFIG_RB_MAP_0 = 0
RASTER_CONFIG_RB_MAP_1 = 1
RASTER_CONFIG_RB_MAP_2 = 2
RASTER_CONFIG_RB_MAP_3 = 3
RbMap = ctypes.c_uint32 # enum
# values for enumeration 'BinningMode'
BinningMode__enumvalues = {
0: 'BINNING_ALLOWED',
1: 'FORCE_BINNING_ON',
2: 'DISABLE_BINNING_USE_NEW_SC',
3: 'DISABLE_BINNING_USE_LEGACY_SC',
}
BINNING_ALLOWED = 0
FORCE_BINNING_ON = 1
DISABLE_BINNING_USE_NEW_SC = 2
DISABLE_BINNING_USE_LEGACY_SC = 3
BinningMode = ctypes.c_uint32 # enum
# values for enumeration 'BinSizeExtend'
BinSizeExtend__enumvalues = {
0: 'BIN_SIZE_32_PIXELS',
1: 'BIN_SIZE_64_PIXELS',
2: 'BIN_SIZE_128_PIXELS',
3: 'BIN_SIZE_256_PIXELS',
4: 'BIN_SIZE_512_PIXELS',
}
BIN_SIZE_32_PIXELS = 0
BIN_SIZE_64_PIXELS = 1
BIN_SIZE_128_PIXELS = 2
BIN_SIZE_256_PIXELS = 3
BIN_SIZE_512_PIXELS = 4
BinSizeExtend = ctypes.c_uint32 # enum
# values for enumeration 'BinMapMode'
BinMapMode__enumvalues = {
0: 'BIN_MAP_MODE_NONE',
1: 'BIN_MAP_MODE_RTA_INDEX',
2: 'BIN_MAP_MODE_POPS',
}
BIN_MAP_MODE_NONE = 0
BIN_MAP_MODE_RTA_INDEX = 1
BIN_MAP_MODE_POPS = 2
BinMapMode = ctypes.c_uint32 # enum
# values for enumeration 'BinEventCntl'
BinEventCntl__enumvalues = {
0: 'BINNER_BREAK_BATCH',
1: 'BINNER_PIPELINE',
2: 'BINNER_DROP',
3: 'BINNER_DROP_ASSERT',
}
BINNER_BREAK_BATCH = 0
BINNER_PIPELINE = 1
BINNER_DROP = 2
BINNER_DROP_ASSERT = 3
BinEventCntl = ctypes.c_uint32 # enum
# values for enumeration 'CovToShaderSel'
CovToShaderSel__enumvalues = {
0: 'INPUT_COVERAGE',
1: 'INPUT_INNER_COVERAGE',
2: 'INPUT_DEPTH_COVERAGE',
3: 'RAW',
}
INPUT_COVERAGE = 0
INPUT_INNER_COVERAGE = 1
INPUT_DEPTH_COVERAGE = 2
RAW = 3
CovToShaderSel = ctypes.c_uint32 # enum
# values for enumeration 'ScUncertaintyRegionMode'
ScUncertaintyRegionMode__enumvalues = {
0: 'SC_HALF_LSB',
1: 'SC_LSB_ONE_SIDED',
2: 'SC_LSB_TWO_SIDED',
}
SC_HALF_LSB = 0
SC_LSB_ONE_SIDED = 1
SC_LSB_TWO_SIDED = 2
ScUncertaintyRegionMode = ctypes.c_uint32 # enum
# values for enumeration 'RMIPerfSel'
RMIPerfSel__enumvalues = {
0: 'RMI_PERF_SEL_NONE',
1: 'RMI_PERF_SEL_BUSY',
2: 'RMI_PERF_SEL_REG_CLK_VLD',
3: 'RMI_PERF_SEL_DYN_CLK_CMN_VLD',
4: 'RMI_PERF_SEL_DYN_CLK_RB_VLD',
5: 'RMI_PERF_SEL_DYN_CLK_PERF_VLD',
6: 'RMI_PERF_SEL_PERF_WINDOW',
7: 'RMI_PERF_SEL_EVENT_SEND',
8: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0',
9: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1',
10: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2',
11: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3',
12: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4',
13: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5',
14: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6',
15: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7',
16: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8',
17: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9',
18: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10',
19: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11',
20: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12',
21: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13',
22: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14',
23: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15',
24: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL',
25: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0',
26: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1',
27: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2',
28: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3',
29: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4',
30: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5',
31: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6',
32: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7',
33: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8',
34: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9',
35: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10',
36: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11',
37: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12',
38: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13',
39: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14',
40: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15',
41: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL',
42: 'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS',
43: 'RMI_PERF_SEL_UTCL1_PERMISSION_MISS',
44: 'RMI_PERF_SEL_UTCL1_TRANSLATION_HIT',
45: 'RMI_PERF_SEL_UTCL1_REQUEST',
46: 'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX',
47: 'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT',
48: 'RMI_PERF_SEL_UTCL1_LFIFO_FULL',
49: 'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES',
50: 'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS',
51: 'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL',
52: 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL',
53: 'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS',
54: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID',
55: 'RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY',
56: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0',
57: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1',
58: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2',
59: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3',
60: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4',
61: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5',
62: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6',
63: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7',
64: 'RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID',
65: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID',
66: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID',
67: 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY',
68: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID',
69: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0',
70: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1',
71: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2',
72: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3',
73: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4',
74: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5',
75: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6',
76: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7',
77: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0',
78: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1',
79: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2',
80: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3',
81: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID',
82: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID',
83: 'RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY',
84: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0',
85: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1',
86: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2',
87: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3',
88: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4',
89: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5',
90: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6',
91: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7',
92: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0',
93: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1',
94: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2',
95: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3',
96: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4',
97: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5',
98: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6',
99: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7',
100: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID',
101: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID',
102: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID',
103: 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY',
104: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID',
105: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0',
106: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1',
107: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2',
108: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3',
109: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4',
110: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5',
111: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6',
112: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7',
113: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0',
114: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1',
115: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2',
116: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3',
117: 'RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX',
118: 'RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY',
119: 'RMI_PERF_SEL_RB_RMI_WR_IDLE',
120: 'RMI_PERF_SEL_RB_RMI_WR_STARVE',
121: 'RMI_PERF_SEL_RB_RMI_WR_STALL',
122: 'RMI_PERF_SEL_RB_RMI_WR_BUSY',
123: 'RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY',
124: 'RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX',
125: 'RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY',
126: 'RMI_PERF_SEL_RB_RMI_RD_IDLE',
127: 'RMI_PERF_SEL_RB_RMI_RD_STARVE',
128: 'RMI_PERF_SEL_RB_RMI_RD_STALL',
129: 'RMI_PERF_SEL_RB_RMI_RD_BUSY',
130: 'RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY',
131: 'RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID',
132: 'RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID',
133: 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID',
134: 'RMI_PERF_SEL_RMI_TC_REQ_BUSY',
135: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0',
136: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1',
137: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2',
138: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3',
139: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4',
140: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5',
141: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6',
142: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7',
143: 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID',
144: 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID',
145: 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID',
146: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0',
147: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1',
148: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2',
149: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3',
150: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4',
151: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5',
152: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6',
153: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7',
154: 'RMI_PERF_SEL_RMI_TC_STALL_RDREQ',
155: 'RMI_PERF_SEL_RMI_TC_STALL_WRREQ',
156: 'RMI_PERF_SEL_RMI_TC_STALL_ALLREQ',
157: 'RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND',
158: 'RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND',
159: 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID',
160: 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID',
161: 'RMI_PERF_SEL_UTCL1_BUSY',
162: 'RMI_PERF_SEL_RMI_UTC_REQ',
163: 'RMI_PERF_SEL_RMI_UTC_BUSY',
164: 'RMI_PERF_SEL_UTCL1_UTCL2_REQ',
165: 'RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2',
166: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY',
167: 'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT',
168: 'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT',
169: 'RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS',
170: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT',
171: 'RMI_PERF_SEL_XNACK_FIFO_NUM_USED',
172: 'RMI_PERF_SEL_LAT_FIFO_NUM_USED',
173: 'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ',
174: 'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ',
175: 'RMI_PERF_SEL_XNACK_FIFO_FULL',
176: 'RMI_PERF_SEL_XNACK_FIFO_BUSY',
177: 'RMI_PERF_SEL_LAT_FIFO_FULL',
178: 'RMI_PERF_SEL_SKID_FIFO_DEPTH',
179: 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT',
180: 'RMI_PERF_SEL_PRT_FIFO_NUM_USED',
181: 'RMI_PERF_SEL_PRT_FIFO_REQ',
182: 'RMI_PERF_SEL_PRT_FIFO_BUSY',
183: 'RMI_PERF_SEL_TCIW_REQ',
184: 'RMI_PERF_SEL_TCIW_BUSY',
185: 'RMI_PERF_SEL_SKID_FIFO_REQ',
186: 'RMI_PERF_SEL_SKID_FIFO_BUSY',
187: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0',
188: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1',
189: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2',
190: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3',
191: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR',
192: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR',
193: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB',
194: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB',
195: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR',
196: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR',
197: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB',
198: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB',
199: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR',
200: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR',
201: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB',
202: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB',
203: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR',
204: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR',
205: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB',
206: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB',
207: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTR',
208: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR',
209: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB',
210: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB',
211: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR',
212: 'RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC',
213: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR',
214: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB',
215: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB',
216: 'RMI_PERF_SEL_UTC_POP_RTS_RTR',
217: 'RMI_PERF_SEL_UTC_POP_RTSB_RTR',
218: 'RMI_PERF_SEL_UTC_POP_RTS_RTRB',
219: 'RMI_PERF_SEL_UTC_POP_RTSB_RTRB',
220: 'RMI_PERF_SEL_POP_XNACK_RTS_RTR',
221: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTR',
222: 'RMI_PERF_SEL_POP_XNACK_RTS_RTRB',
223: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB',
224: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR',
225: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR',
226: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB',
227: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB',
228: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR',
229: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR',
230: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB',
231: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB',
232: 'RMI_PERF_SEL_SKID_FIFO_IN_RTS',
233: 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB',
234: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTS',
235: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB',
236: 'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR',
237: 'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR',
238: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR',
239: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR',
240: 'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR',
241: 'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR',
242: 'RMI_PERF_SEL_REORDER_FIFO_REQ',
243: 'RMI_PERF_SEL_REORDER_FIFO_BUSY',
244: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID',
245: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0',
246: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1',
247: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2',
248: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3',
249: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4',
250: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5',
251: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6',
252: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7',
253: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0',
254: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1',
255: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2',
256: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3',
}
RMI_PERF_SEL_NONE = 0
RMI_PERF_SEL_BUSY = 1
RMI_PERF_SEL_REG_CLK_VLD = 2
RMI_PERF_SEL_DYN_CLK_CMN_VLD = 3
RMI_PERF_SEL_DYN_CLK_RB_VLD = 4
RMI_PERF_SEL_DYN_CLK_PERF_VLD = 5
RMI_PERF_SEL_PERF_WINDOW = 6
RMI_PERF_SEL_EVENT_SEND = 7
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 8
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 9
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 10
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 11
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 12
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 13
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 14
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 15
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 16
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 17
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 18
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 19
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 20
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 21
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 22
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 23
RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 24
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 25
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 26
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 27
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 28
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 29
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 30
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 31
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 32
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 33
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 34
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 35
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 36
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 37
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 38
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 39
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 40
RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 41
RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 42
RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 43
RMI_PERF_SEL_UTCL1_TRANSLATION_HIT = 44
RMI_PERF_SEL_UTCL1_REQUEST = 45
RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 46
RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 47
RMI_PERF_SEL_UTCL1_LFIFO_FULL = 48
RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 49
RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 50
RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 51
RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 52
RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 53
RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 54
RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY = 55
RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 56
RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 57
RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 58
RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 59
RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 60
RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 61
RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 62
RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 63
RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID = 64
RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 65
RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 66
RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 67
RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 68
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 69
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 70
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 71
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 72
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 73
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 74
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 75
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 76
RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 77
RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 78
RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 79
RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 80
RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 81
RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 82
RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY = 83
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 84
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 85
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 86
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 87
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 88
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 89
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 90
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 91
RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 92
RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 93
RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 94
RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 95
RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 96
RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 97
RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 98
RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 99
RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 100
RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 101
RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 102
RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 103
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 104
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 105
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 106
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 107
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 108
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 109
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 110
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 111
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 112
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 113
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 114
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 115
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 116
RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX = 117
RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY = 118
RMI_PERF_SEL_RB_RMI_WR_IDLE = 119
RMI_PERF_SEL_RB_RMI_WR_STARVE = 120
RMI_PERF_SEL_RB_RMI_WR_STALL = 121
RMI_PERF_SEL_RB_RMI_WR_BUSY = 122
RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY = 123
RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX = 124
RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY = 125
RMI_PERF_SEL_RB_RMI_RD_IDLE = 126
RMI_PERF_SEL_RB_RMI_RD_STARVE = 127
RMI_PERF_SEL_RB_RMI_RD_STALL = 128
RMI_PERF_SEL_RB_RMI_RD_BUSY = 129
RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY = 130
RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID = 131
RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID = 132
RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 133
RMI_PERF_SEL_RMI_TC_REQ_BUSY = 134
RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 135
RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 136
RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 137
RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 138
RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 139
RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 140
RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 141
RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 142
RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 143
RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 144
RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 145
RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 146
RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 147
RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 148
RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 149
RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 150
RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 151
RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 152
RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 153
RMI_PERF_SEL_RMI_TC_STALL_RDREQ = 154
RMI_PERF_SEL_RMI_TC_STALL_WRREQ = 155
RMI_PERF_SEL_RMI_TC_STALL_ALLREQ = 156
RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND = 157
RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND = 158
RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 159
RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 160
RMI_PERF_SEL_UTCL1_BUSY = 161
RMI_PERF_SEL_RMI_UTC_REQ = 162
RMI_PERF_SEL_RMI_UTC_BUSY = 163
RMI_PERF_SEL_UTCL1_UTCL2_REQ = 164
RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2 = 165
RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 166
RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 167
RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 168
RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS = 169
RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 170
RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 171
RMI_PERF_SEL_LAT_FIFO_NUM_USED = 172
RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 173
RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 174
RMI_PERF_SEL_XNACK_FIFO_FULL = 175
RMI_PERF_SEL_XNACK_FIFO_BUSY = 176
RMI_PERF_SEL_LAT_FIFO_FULL = 177
RMI_PERF_SEL_SKID_FIFO_DEPTH = 178
RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 179
RMI_PERF_SEL_PRT_FIFO_NUM_USED = 180
RMI_PERF_SEL_PRT_FIFO_REQ = 181
RMI_PERF_SEL_PRT_FIFO_BUSY = 182
RMI_PERF_SEL_TCIW_REQ = 183
RMI_PERF_SEL_TCIW_BUSY = 184
RMI_PERF_SEL_SKID_FIFO_REQ = 185
RMI_PERF_SEL_SKID_FIFO_BUSY = 186
RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 187
RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 188
RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 189
RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 190
RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 191
RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 192
RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 193
RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 194
RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 195
RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 196
RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 197
RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 198
RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 199
RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 200
RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 201
RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 202
RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 203
RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 204
RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 205
RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 206
RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 207
RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 208
RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 209
RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 210
RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 211
RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC = 212
RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 213
RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 214
RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 215
RMI_PERF_SEL_UTC_POP_RTS_RTR = 216
RMI_PERF_SEL_UTC_POP_RTSB_RTR = 217
RMI_PERF_SEL_UTC_POP_RTS_RTRB = 218
RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 219
RMI_PERF_SEL_POP_XNACK_RTS_RTR = 220
RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 221
RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 222
RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 223
RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 224
RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 225
RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 226
RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 227
RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 228
RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 229
RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 230
RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 231
RMI_PERF_SEL_SKID_FIFO_IN_RTS = 232
RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 233
RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 234
RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 235
RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 236
RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 237
RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 238
RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 239
RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 240
RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 241
RMI_PERF_SEL_REORDER_FIFO_REQ = 242
RMI_PERF_SEL_REORDER_FIFO_BUSY = 243
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 244
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 245
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 246
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 247
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 248
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 249
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 250
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 251
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 252
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 253
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 254
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 255
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 256
RMIPerfSel = ctypes.c_uint32 # enum
# values for enumeration 'GCRPerfSel'
GCRPerfSel__enumvalues = {
0: 'GCR_PERF_SEL_NONE',
1: 'GCR_PERF_SEL_SDMA0_ALL_REQ',
2: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ',
3: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ',
4: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ',
5: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ',
6: 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ',
7: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ',
8: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ',
9: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ',
10: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ',
11: 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ',
12: 'GCR_PERF_SEL_SDMA0_METADATA_REQ',
13: 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ',
14: 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ',
15: 'GCR_PERF_SEL_SDMA0_TCP_REQ',
16: 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ',
17: 'GCR_PERF_SEL_SDMA1_ALL_REQ',
18: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ',
19: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ',
20: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ',
21: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ',
22: 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ',
23: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ',
24: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ',
25: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ',
26: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ',
27: 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ',
28: 'GCR_PERF_SEL_SDMA1_METADATA_REQ',
29: 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ',
30: 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ',
31: 'GCR_PERF_SEL_SDMA1_TCP_REQ',
32: 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ',
33: 'GCR_PERF_SEL_CPG_ALL_REQ',
34: 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ',
35: 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ',
36: 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ',
37: 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ',
38: 'GCR_PERF_SEL_CPG_GL2_ALL_REQ',
39: 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ',
40: 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ',
41: 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ',
42: 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ',
43: 'GCR_PERF_SEL_CPG_GL1_ALL_REQ',
44: 'GCR_PERF_SEL_CPG_METADATA_REQ',
45: 'GCR_PERF_SEL_CPG_SQC_DATA_REQ',
46: 'GCR_PERF_SEL_CPG_SQC_INST_REQ',
47: 'GCR_PERF_SEL_CPG_TCP_REQ',
48: 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ',
49: 'GCR_PERF_SEL_CPC_ALL_REQ',
50: 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ',
51: 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ',
52: 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ',
53: 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ',
54: 'GCR_PERF_SEL_CPC_GL2_ALL_REQ',
55: 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ',
56: 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ',
57: 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ',
58: 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ',
59: 'GCR_PERF_SEL_CPC_GL1_ALL_REQ',
60: 'GCR_PERF_SEL_CPC_METADATA_REQ',
61: 'GCR_PERF_SEL_CPC_SQC_DATA_REQ',
62: 'GCR_PERF_SEL_CPC_SQC_INST_REQ',
63: 'GCR_PERF_SEL_CPC_TCP_REQ',
64: 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ',
65: 'GCR_PERF_SEL_CPF_ALL_REQ',
66: 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ',
67: 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ',
68: 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ',
69: 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ',
70: 'GCR_PERF_SEL_CPF_GL2_ALL_REQ',
71: 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ',
72: 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ',
73: 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ',
74: 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ',
75: 'GCR_PERF_SEL_CPF_GL1_ALL_REQ',
76: 'GCR_PERF_SEL_CPF_METADATA_REQ',
77: 'GCR_PERF_SEL_CPF_SQC_DATA_REQ',
78: 'GCR_PERF_SEL_CPF_SQC_INST_REQ',
79: 'GCR_PERF_SEL_CPF_TCP_REQ',
80: 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ',
81: 'GCR_PERF_SEL_VIRT_REQ',
82: 'GCR_PERF_SEL_PHY_REQ',
83: 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ',
84: 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ',
85: 'GCR_PERF_SEL_ALL_REQ',
86: 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ',
87: 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ',
88: 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ',
89: 'GCR_PERF_SEL_UTCL2_REQ',
90: 'GCR_PERF_SEL_UTCL2_RET',
91: 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT',
92: 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ',
93: 'GCR_PERF_SEL_UTCL2_FILTERED_RET',
}
GCR_PERF_SEL_NONE = 0
GCR_PERF_SEL_SDMA0_ALL_REQ = 1
GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 2
GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 3
GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 4
GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 5
GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 6
GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 7
GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 8
GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 9
GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 10
GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 11
GCR_PERF_SEL_SDMA0_METADATA_REQ = 12
GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 13
GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 14
GCR_PERF_SEL_SDMA0_TCP_REQ = 15
GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 16
GCR_PERF_SEL_SDMA1_ALL_REQ = 17
GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 18
GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 19
GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 20
GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 21
GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 22
GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 23
GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 24
GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 25
GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 26
GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 27
GCR_PERF_SEL_SDMA1_METADATA_REQ = 28
GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 29
GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 30
GCR_PERF_SEL_SDMA1_TCP_REQ = 31
GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 32
GCR_PERF_SEL_CPG_ALL_REQ = 33
GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 34
GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 35
GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 36
GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 37
GCR_PERF_SEL_CPG_GL2_ALL_REQ = 38
GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 39
GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 40
GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 41
GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 42
GCR_PERF_SEL_CPG_GL1_ALL_REQ = 43
GCR_PERF_SEL_CPG_METADATA_REQ = 44
GCR_PERF_SEL_CPG_SQC_DATA_REQ = 45
GCR_PERF_SEL_CPG_SQC_INST_REQ = 46
GCR_PERF_SEL_CPG_TCP_REQ = 47
GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 48
GCR_PERF_SEL_CPC_ALL_REQ = 49
GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 50
GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 51
GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 52
GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 53
GCR_PERF_SEL_CPC_GL2_ALL_REQ = 54
GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 55
GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 56
GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 57
GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 58
GCR_PERF_SEL_CPC_GL1_ALL_REQ = 59
GCR_PERF_SEL_CPC_METADATA_REQ = 60
GCR_PERF_SEL_CPC_SQC_DATA_REQ = 61
GCR_PERF_SEL_CPC_SQC_INST_REQ = 62
GCR_PERF_SEL_CPC_TCP_REQ = 63
GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 64
GCR_PERF_SEL_CPF_ALL_REQ = 65
GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 66
GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 67
GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 68
GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 69
GCR_PERF_SEL_CPF_GL2_ALL_REQ = 70
GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 71
GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 72
GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 73
GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 74
GCR_PERF_SEL_CPF_GL1_ALL_REQ = 75
GCR_PERF_SEL_CPF_METADATA_REQ = 76
GCR_PERF_SEL_CPF_SQC_DATA_REQ = 77
GCR_PERF_SEL_CPF_SQC_INST_REQ = 78
GCR_PERF_SEL_CPF_TCP_REQ = 79
GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 80
GCR_PERF_SEL_VIRT_REQ = 81
GCR_PERF_SEL_PHY_REQ = 82
GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 83
GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 84
GCR_PERF_SEL_ALL_REQ = 85
GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 86
GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 87
GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 88
GCR_PERF_SEL_UTCL2_REQ = 89
GCR_PERF_SEL_UTCL2_RET = 90
GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 91
GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 92
GCR_PERF_SEL_UTCL2_FILTERED_RET = 93
GCRPerfSel = ctypes.c_uint32 # enum
# values for enumeration 'UTCL1PerfSel'
UTCL1PerfSel__enumvalues = {
0: 'UTCL1_PERF_SEL_NONE',
1: 'UTCL1_PERF_SEL_REQS',
2: 'UTCL1_PERF_SEL_HITS',
3: 'UTCL1_PERF_SEL_MISSES',
4: 'UTCL1_PERF_SEL_BYPASS_REQS',
5: 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS',
6: 'UTCL1_PERF_SEL_NUM_SMALLK_PAGES',
7: 'UTCL1_PERF_SEL_NUM_BIGK_PAGES',
8: 'UTCL1_PERF_SEL_TOTAL_UTCL2_REQS',
9: 'UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM',
10: 'UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS',
11: 'UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL',
12: 'UTCL1_PERF_SEL_STALL_MH_CAM_FULL',
13: 'UTCL1_PERF_SEL_NONRANGE_INV_REQS',
14: 'UTCL1_PERF_SEL_RANGE_INV_REQS',
}
UTCL1_PERF_SEL_NONE = 0
UTCL1_PERF_SEL_REQS = 1
UTCL1_PERF_SEL_HITS = 2
UTCL1_PERF_SEL_MISSES = 3
UTCL1_PERF_SEL_BYPASS_REQS = 4
UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 5
UTCL1_PERF_SEL_NUM_SMALLK_PAGES = 6
UTCL1_PERF_SEL_NUM_BIGK_PAGES = 7
UTCL1_PERF_SEL_TOTAL_UTCL2_REQS = 8
UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM = 9
UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS = 10
UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL = 11
UTCL1_PERF_SEL_STALL_MH_CAM_FULL = 12
UTCL1_PERF_SEL_NONRANGE_INV_REQS = 13
UTCL1_PERF_SEL_RANGE_INV_REQS = 14
UTCL1PerfSel = ctypes.c_uint32 # enum
# values for enumeration 'SDMA_PERF_SEL'
SDMA_PERF_SEL__enumvalues = {
0: 'SDMA_PERF_SEL_CYCLE',
1: 'SDMA_PERF_SEL_IDLE',
2: 'SDMA_PERF_SEL_REG_IDLE',
3: 'SDMA_PERF_SEL_RB_EMPTY',
4: 'SDMA_PERF_SEL_RB_FULL',
5: 'SDMA_PERF_SEL_RB_WPTR_WRAP',
6: 'SDMA_PERF_SEL_RB_RPTR_WRAP',
7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ',
8: 'SDMA_PERF_SEL_RB_RPTR_WB',
9: 'SDMA_PERF_SEL_RB_CMD_IDLE',
10: 'SDMA_PERF_SEL_RB_CMD_FULL',
11: 'SDMA_PERF_SEL_IB_CMD_IDLE',
12: 'SDMA_PERF_SEL_IB_CMD_FULL',
13: 'SDMA_PERF_SEL_EX_IDLE',
14: 'SDMA_PERF_SEL_SRBM_REG_SEND',
15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
16: 'SDMA_PERF_SEL_MC_WR_IDLE',
17: 'SDMA_PERF_SEL_MC_WR_COUNT',
18: 'SDMA_PERF_SEL_MC_RD_IDLE',
19: 'SDMA_PERF_SEL_MC_RD_COUNT',
20: 'SDMA_PERF_SEL_MC_RD_RET_STALL',
21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE',
24: 'SDMA_PERF_SEL_SEM_IDLE',
25: 'SDMA_PERF_SEL_SEM_REQ_STALL',
26: 'SDMA_PERF_SEL_SEM_REQ_COUNT',
27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE',
28: 'SDMA_PERF_SEL_SEM_RESP_FAIL',
29: 'SDMA_PERF_SEL_SEM_RESP_PASS',
30: 'SDMA_PERF_SEL_INT_IDLE',
31: 'SDMA_PERF_SEL_INT_REQ_STALL',
32: 'SDMA_PERF_SEL_INT_REQ_COUNT',
33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED',
34: 'SDMA_PERF_SEL_INT_RESP_RETRY',
35: 'SDMA_PERF_SEL_NUM_PACKET',
37: 'SDMA_PERF_SEL_CE_WREQ_IDLE',
38: 'SDMA_PERF_SEL_CE_WR_IDLE',
39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE',
40: 'SDMA_PERF_SEL_CE_RREQ_IDLE',
41: 'SDMA_PERF_SEL_CE_OUT_IDLE',
42: 'SDMA_PERF_SEL_CE_IN_IDLE',
43: 'SDMA_PERF_SEL_CE_DST_IDLE',
46: 'SDMA_PERF_SEL_CE_AFIFO_FULL',
49: 'SDMA_PERF_SEL_CE_INFO_FULL',
50: 'SDMA_PERF_SEL_CE_INFO1_FULL',
51: 'SDMA_PERF_SEL_CE_RD_STALL',
52: 'SDMA_PERF_SEL_CE_WR_STALL',
53: 'SDMA_PERF_SEL_GFX_SELECT',
54: 'SDMA_PERF_SEL_RLC0_SELECT',
55: 'SDMA_PERF_SEL_RLC1_SELECT',
56: 'SDMA_PERF_SEL_PAGE_SELECT',
57: 'SDMA_PERF_SEL_CTX_CHANGE',
58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED',
59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION',
60: 'SDMA_PERF_SEL_DOORBELL',
61: 'SDMA_PERF_SEL_RD_BA_RTR',
62: 'SDMA_PERF_SEL_WR_BA_RTR',
63: 'SDMA_PERF_SEL_F32_L1_WR_VLD',
64: 'SDMA_PERF_SEL_CE_L1_WR_VLD',
65: 'SDMA_PERF_SEL_CPF_SDMA_INVREQ',
66: 'SDMA_PERF_SEL_SDMA_CPF_INVACK',
67: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ',
68: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK',
69: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL',
70: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL',
71: 'SDMA_PERF_SEL_UTCL2_RET_XNACK',
72: 'SDMA_PERF_SEL_UTCL2_RET_ACK',
73: 'SDMA_PERF_SEL_UTCL2_FREE',
74: 'SDMA_PERF_SEL_SDMA_UTCL2_SEND',
75: 'SDMA_PERF_SEL_DMA_L1_WR_SEND',
76: 'SDMA_PERF_SEL_DMA_L1_RD_SEND',
77: 'SDMA_PERF_SEL_DMA_MC_WR_SEND',
78: 'SDMA_PERF_SEL_DMA_MC_RD_SEND',
79: 'SDMA_PERF_SEL_GPUVM_INVREQ_HIGH',
80: 'SDMA_PERF_SEL_GPUVM_INVREQ_LOW',
81: 'SDMA_PERF_SEL_L1_WRL2_IDLE',
82: 'SDMA_PERF_SEL_L1_RDL2_IDLE',
83: 'SDMA_PERF_SEL_L1_WRMC_IDLE',
84: 'SDMA_PERF_SEL_L1_RDMC_IDLE',
85: 'SDMA_PERF_SEL_L1_WR_INV_IDLE',
86: 'SDMA_PERF_SEL_L1_RD_INV_IDLE',
87: 'SDMA_PERF_SEL_META_L2_REQ_SEND',
88: 'SDMA_PERF_SEL_L2_META_RET_VLD',
89: 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND',
90: 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN',
91: 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND',
92: 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN',
93: 'SDMA_PERF_SEL_META_REQ_SEND',
94: 'SDMA_PERF_SEL_META_RTN_VLD',
95: 'SDMA_PERF_SEL_TLBI_SEND',
96: 'SDMA_PERF_SEL_TLBI_RTN',
97: 'SDMA_PERF_SEL_GCR_SEND',
98: 'SDMA_PERF_SEL_GCR_RTN',
99: 'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER',
100: 'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER',
}
SDMA_PERF_SEL_CYCLE = 0
SDMA_PERF_SEL_IDLE = 1
SDMA_PERF_SEL_REG_IDLE = 2
SDMA_PERF_SEL_RB_EMPTY = 3
SDMA_PERF_SEL_RB_FULL = 4
SDMA_PERF_SEL_RB_WPTR_WRAP = 5
SDMA_PERF_SEL_RB_RPTR_WRAP = 6
SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7
SDMA_PERF_SEL_RB_RPTR_WB = 8
SDMA_PERF_SEL_RB_CMD_IDLE = 9
SDMA_PERF_SEL_RB_CMD_FULL = 10
SDMA_PERF_SEL_IB_CMD_IDLE = 11
SDMA_PERF_SEL_IB_CMD_FULL = 12
SDMA_PERF_SEL_EX_IDLE = 13
SDMA_PERF_SEL_SRBM_REG_SEND = 14
SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15
SDMA_PERF_SEL_MC_WR_IDLE = 16
SDMA_PERF_SEL_MC_WR_COUNT = 17
SDMA_PERF_SEL_MC_RD_IDLE = 18
SDMA_PERF_SEL_MC_RD_COUNT = 19
SDMA_PERF_SEL_MC_RD_RET_STALL = 20
SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21
SDMA_PERF_SEL_SEM_IDLE = 24
SDMA_PERF_SEL_SEM_REQ_STALL = 25
SDMA_PERF_SEL_SEM_REQ_COUNT = 26
SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27
SDMA_PERF_SEL_SEM_RESP_FAIL = 28
SDMA_PERF_SEL_SEM_RESP_PASS = 29
SDMA_PERF_SEL_INT_IDLE = 30
SDMA_PERF_SEL_INT_REQ_STALL = 31
SDMA_PERF_SEL_INT_REQ_COUNT = 32
SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33
SDMA_PERF_SEL_INT_RESP_RETRY = 34
SDMA_PERF_SEL_NUM_PACKET = 35
SDMA_PERF_SEL_CE_WREQ_IDLE = 37
SDMA_PERF_SEL_CE_WR_IDLE = 38
SDMA_PERF_SEL_CE_SPLIT_IDLE = 39
SDMA_PERF_SEL_CE_RREQ_IDLE = 40
SDMA_PERF_SEL_CE_OUT_IDLE = 41
SDMA_PERF_SEL_CE_IN_IDLE = 42
SDMA_PERF_SEL_CE_DST_IDLE = 43
SDMA_PERF_SEL_CE_AFIFO_FULL = 46
SDMA_PERF_SEL_CE_INFO_FULL = 49
SDMA_PERF_SEL_CE_INFO1_FULL = 50
SDMA_PERF_SEL_CE_RD_STALL = 51
SDMA_PERF_SEL_CE_WR_STALL = 52
SDMA_PERF_SEL_GFX_SELECT = 53
SDMA_PERF_SEL_RLC0_SELECT = 54
SDMA_PERF_SEL_RLC1_SELECT = 55
SDMA_PERF_SEL_PAGE_SELECT = 56
SDMA_PERF_SEL_CTX_CHANGE = 57
SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58
SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59
SDMA_PERF_SEL_DOORBELL = 60
SDMA_PERF_SEL_RD_BA_RTR = 61
SDMA_PERF_SEL_WR_BA_RTR = 62
SDMA_PERF_SEL_F32_L1_WR_VLD = 63
SDMA_PERF_SEL_CE_L1_WR_VLD = 64
SDMA_PERF_SEL_CPF_SDMA_INVREQ = 65
SDMA_PERF_SEL_SDMA_CPF_INVACK = 66
SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 67
SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 68
SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 69
SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 70
SDMA_PERF_SEL_UTCL2_RET_XNACK = 71
SDMA_PERF_SEL_UTCL2_RET_ACK = 72
SDMA_PERF_SEL_UTCL2_FREE = 73
SDMA_PERF_SEL_SDMA_UTCL2_SEND = 74
SDMA_PERF_SEL_DMA_L1_WR_SEND = 75
SDMA_PERF_SEL_DMA_L1_RD_SEND = 76
SDMA_PERF_SEL_DMA_MC_WR_SEND = 77
SDMA_PERF_SEL_DMA_MC_RD_SEND = 78
SDMA_PERF_SEL_GPUVM_INVREQ_HIGH = 79
SDMA_PERF_SEL_GPUVM_INVREQ_LOW = 80
SDMA_PERF_SEL_L1_WRL2_IDLE = 81
SDMA_PERF_SEL_L1_RDL2_IDLE = 82
SDMA_PERF_SEL_L1_WRMC_IDLE = 83
SDMA_PERF_SEL_L1_RDMC_IDLE = 84
SDMA_PERF_SEL_L1_WR_INV_IDLE = 85
SDMA_PERF_SEL_L1_RD_INV_IDLE = 86
SDMA_PERF_SEL_META_L2_REQ_SEND = 87
SDMA_PERF_SEL_L2_META_RET_VLD = 88
SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 89
SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 90
SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 91
SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 92
SDMA_PERF_SEL_META_REQ_SEND = 93
SDMA_PERF_SEL_META_RTN_VLD = 94
SDMA_PERF_SEL_TLBI_SEND = 95
SDMA_PERF_SEL_TLBI_RTN = 96
SDMA_PERF_SEL_GCR_SEND = 97
SDMA_PERF_SEL_GCR_RTN = 98
SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 99
SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 100
SDMA_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'NUM_PIPES_BC_ENUM'
NUM_PIPES_BC_ENUM__enumvalues = {
0: 'ADDR_NUM_PIPES_BC_P8',
1: 'ADDR_NUM_PIPES_BC_P16',
}
ADDR_NUM_PIPES_BC_P8 = 0
ADDR_NUM_PIPES_BC_P16 = 1
NUM_PIPES_BC_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'NUM_BANKS_BC_ENUM'
NUM_BANKS_BC_ENUM__enumvalues = {
0: 'ADDR_NUM_BANKS_BC_BANKS_1',
1: 'ADDR_NUM_BANKS_BC_BANKS_2',
2: 'ADDR_NUM_BANKS_BC_BANKS_4',
3: 'ADDR_NUM_BANKS_BC_BANKS_8',
4: 'ADDR_NUM_BANKS_BC_BANKS_16',
}
ADDR_NUM_BANKS_BC_BANKS_1 = 0
ADDR_NUM_BANKS_BC_BANKS_2 = 1
ADDR_NUM_BANKS_BC_BANKS_4 = 2
ADDR_NUM_BANKS_BC_BANKS_8 = 3
ADDR_NUM_BANKS_BC_BANKS_16 = 4
NUM_BANKS_BC_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'SWIZZLE_TYPE_ENUM'
SWIZZLE_TYPE_ENUM__enumvalues = {
0: 'SW_Z',
1: 'SW_S',
2: 'SW_D',
3: 'SW_R',
4: 'SW_L',
}
SW_Z = 0
SW_S = 1
SW_D = 2
SW_R = 3
SW_L = 4
SWIZZLE_TYPE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'TC_MICRO_TILE_MODE'
TC_MICRO_TILE_MODE__enumvalues = {
0: 'MICRO_TILE_MODE_LINEAR',
1: 'MICRO_TILE_MODE_RENDER_TARGET',
2: 'MICRO_TILE_MODE_STD_2D',
3: 'MICRO_TILE_MODE_STD_3D',
4: 'MICRO_TILE_MODE_DISPLAY_2D',
5: 'MICRO_TILE_MODE_DISPLAY_3D',
6: 'MICRO_TILE_MODE_Z',
}
MICRO_TILE_MODE_LINEAR = 0
MICRO_TILE_MODE_RENDER_TARGET = 1
MICRO_TILE_MODE_STD_2D = 2
MICRO_TILE_MODE_STD_3D = 3
MICRO_TILE_MODE_DISPLAY_2D = 4
MICRO_TILE_MODE_DISPLAY_3D = 5
MICRO_TILE_MODE_Z = 6
TC_MICRO_TILE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SWIZZLE_MODE_ENUM'
SWIZZLE_MODE_ENUM__enumvalues = {
0: 'SW_LINEAR',
1: 'SW_256B_S',
2: 'SW_256B_D',
3: 'SW_256B_R',
4: 'SW_4KB_Z',
5: 'SW_4KB_S',
6: 'SW_4KB_D',
7: 'SW_4KB_R',
8: 'SW_64KB_Z',
9: 'SW_64KB_S',
10: 'SW_64KB_D',
11: 'SW_64KB_R',
12: 'SW_VAR_Z',
13: 'SW_VAR_S',
14: 'SW_VAR_D',
15: 'SW_VAR_R',
16: 'SW_64KB_Z_T',
17: 'SW_64KB_S_T',
18: 'SW_64KB_D_T',
19: 'SW_64KB_R_T',
20: 'SW_4KB_Z_X',
21: 'SW_4KB_S_X',
22: 'SW_4KB_D_X',
23: 'SW_4KB_R_X',
24: 'SW_64KB_Z_X',
25: 'SW_64KB_S_X',
26: 'SW_64KB_D_X',
27: 'SW_64KB_R_X',
28: 'SW_VAR_Z_X',
29: 'SW_VAR_S_X',
30: 'SW_VAR_D_X',
31: 'SW_VAR_R_X',
}
SW_LINEAR = 0
SW_256B_S = 1
SW_256B_D = 2
SW_256B_R = 3
SW_4KB_Z = 4
SW_4KB_S = 5
SW_4KB_D = 6
SW_4KB_R = 7
SW_64KB_Z = 8
SW_64KB_S = 9
SW_64KB_D = 10
SW_64KB_R = 11
SW_VAR_Z = 12
SW_VAR_S = 13
SW_VAR_D = 14
SW_VAR_R = 15
SW_64KB_Z_T = 16
SW_64KB_S_T = 17
SW_64KB_D_T = 18
SW_64KB_R_T = 19
SW_4KB_Z_X = 20
SW_4KB_S_X = 21
SW_4KB_D_X = 22
SW_4KB_R_X = 23
SW_64KB_Z_X = 24
SW_64KB_S_X = 25
SW_64KB_D_X = 26
SW_64KB_R_X = 27
SW_VAR_Z_X = 28
SW_VAR_S_X = 29
SW_VAR_D_X = 30
SW_VAR_R_X = 31
SWIZZLE_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'SurfaceEndian'
SurfaceEndian__enumvalues = {
0: 'ENDIAN_NONE',
1: 'ENDIAN_8IN16',
2: 'ENDIAN_8IN32',
3: 'ENDIAN_8IN64',
}
ENDIAN_NONE = 0
ENDIAN_8IN16 = 1
ENDIAN_8IN32 = 2
ENDIAN_8IN64 = 3
SurfaceEndian = ctypes.c_uint32 # enum
# values for enumeration 'ArrayMode'
ArrayMode__enumvalues = {
0: 'ARRAY_LINEAR_GENERAL',
1: 'ARRAY_LINEAR_ALIGNED',
2: 'ARRAY_1D_TILED_THIN1',
3: 'ARRAY_1D_TILED_THICK',
4: 'ARRAY_2D_TILED_THIN1',
5: 'ARRAY_PRT_TILED_THIN1',
6: 'ARRAY_PRT_2D_TILED_THIN1',
7: 'ARRAY_2D_TILED_THICK',
8: 'ARRAY_2D_TILED_XTHICK',
9: 'ARRAY_PRT_TILED_THICK',
10: 'ARRAY_PRT_2D_TILED_THICK',
11: 'ARRAY_PRT_3D_TILED_THIN1',
12: 'ARRAY_3D_TILED_THIN1',
13: 'ARRAY_3D_TILED_THICK',
14: 'ARRAY_3D_TILED_XTHICK',
15: 'ARRAY_PRT_3D_TILED_THICK',
}
ARRAY_LINEAR_GENERAL = 0
ARRAY_LINEAR_ALIGNED = 1
ARRAY_1D_TILED_THIN1 = 2
ARRAY_1D_TILED_THICK = 3
ARRAY_2D_TILED_THIN1 = 4
ARRAY_PRT_TILED_THIN1 = 5
ARRAY_PRT_2D_TILED_THIN1 = 6
ARRAY_2D_TILED_THICK = 7
ARRAY_2D_TILED_XTHICK = 8
ARRAY_PRT_TILED_THICK = 9
ARRAY_PRT_2D_TILED_THICK = 10
ARRAY_PRT_3D_TILED_THIN1 = 11
ARRAY_3D_TILED_THIN1 = 12
ARRAY_3D_TILED_THICK = 13
ARRAY_3D_TILED_XTHICK = 14
ARRAY_PRT_3D_TILED_THICK = 15
ArrayMode = ctypes.c_uint32 # enum
# values for enumeration 'NumPipes'
NumPipes__enumvalues = {
0: 'ADDR_CONFIG_1_PIPE',
1: 'ADDR_CONFIG_2_PIPE',
2: 'ADDR_CONFIG_4_PIPE',
3: 'ADDR_CONFIG_8_PIPE',
4: 'ADDR_CONFIG_16_PIPE',
5: 'ADDR_CONFIG_32_PIPE',
6: 'ADDR_CONFIG_64_PIPE',
}
ADDR_CONFIG_1_PIPE = 0
ADDR_CONFIG_2_PIPE = 1
ADDR_CONFIG_4_PIPE = 2
ADDR_CONFIG_8_PIPE = 3
ADDR_CONFIG_16_PIPE = 4
ADDR_CONFIG_32_PIPE = 5
ADDR_CONFIG_64_PIPE = 6
NumPipes = ctypes.c_uint32 # enum
# values for enumeration 'NumBanksConfig'
NumBanksConfig__enumvalues = {
0: 'ADDR_CONFIG_1_BANK',
1: 'ADDR_CONFIG_2_BANK',
2: 'ADDR_CONFIG_4_BANK',
3: 'ADDR_CONFIG_8_BANK',
4: 'ADDR_CONFIG_16_BANK',
}
ADDR_CONFIG_1_BANK = 0
ADDR_CONFIG_2_BANK = 1
ADDR_CONFIG_4_BANK = 2
ADDR_CONFIG_8_BANK = 3
ADDR_CONFIG_16_BANK = 4
NumBanksConfig = ctypes.c_uint32 # enum
# values for enumeration 'PipeInterleaveSize'
PipeInterleaveSize__enumvalues = {
0: 'ADDR_CONFIG_PIPE_INTERLEAVE_256B',
1: 'ADDR_CONFIG_PIPE_INTERLEAVE_512B',
2: 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB',
3: 'ADDR_CONFIG_PIPE_INTERLEAVE_2KB',
}
ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0
ADDR_CONFIG_PIPE_INTERLEAVE_512B = 1
ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 2
ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 3
PipeInterleaveSize = ctypes.c_uint32 # enum
# values for enumeration 'BankInterleaveSize'
BankInterleaveSize__enumvalues = {
0: 'ADDR_CONFIG_BANK_INTERLEAVE_1',
1: 'ADDR_CONFIG_BANK_INTERLEAVE_2',
2: 'ADDR_CONFIG_BANK_INTERLEAVE_4',
3: 'ADDR_CONFIG_BANK_INTERLEAVE_8',
}
ADDR_CONFIG_BANK_INTERLEAVE_1 = 0
ADDR_CONFIG_BANK_INTERLEAVE_2 = 1
ADDR_CONFIG_BANK_INTERLEAVE_4 = 2
ADDR_CONFIG_BANK_INTERLEAVE_8 = 3
BankInterleaveSize = ctypes.c_uint32 # enum
# values for enumeration 'NumShaderEngines'
NumShaderEngines__enumvalues = {
0: 'ADDR_CONFIG_1_SHADER_ENGINE',
1: 'ADDR_CONFIG_2_SHADER_ENGINE',
2: 'ADDR_CONFIG_4_SHADER_ENGINE',
3: 'ADDR_CONFIG_8_SHADER_ENGINE',
}
ADDR_CONFIG_1_SHADER_ENGINE = 0
ADDR_CONFIG_2_SHADER_ENGINE = 1
ADDR_CONFIG_4_SHADER_ENGINE = 2
ADDR_CONFIG_8_SHADER_ENGINE = 3
NumShaderEngines = ctypes.c_uint32 # enum
# values for enumeration 'NumRbPerShaderEngine'
NumRbPerShaderEngine__enumvalues = {
0: 'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE',
1: 'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE',
2: 'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE',
}
ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0
ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 1
ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 2
NumRbPerShaderEngine = ctypes.c_uint32 # enum
# values for enumeration 'NumGPUs'
NumGPUs__enumvalues = {
0: 'ADDR_CONFIG_1_GPU',
1: 'ADDR_CONFIG_2_GPU',
2: 'ADDR_CONFIG_4_GPU',
3: 'ADDR_CONFIG_8_GPU',
}
ADDR_CONFIG_1_GPU = 0
ADDR_CONFIG_2_GPU = 1
ADDR_CONFIG_4_GPU = 2
ADDR_CONFIG_8_GPU = 3
NumGPUs = ctypes.c_uint32 # enum
# values for enumeration 'NumMaxCompressedFragments'
NumMaxCompressedFragments__enumvalues = {
0: 'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS',
1: 'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS',
2: 'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS',
3: 'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS',
}
ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0
ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 1
ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 2
ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 3
NumMaxCompressedFragments = ctypes.c_uint32 # enum
# values for enumeration 'ShaderEngineTileSize'
ShaderEngineTileSize__enumvalues = {
0: 'ADDR_CONFIG_SE_TILE_16',
1: 'ADDR_CONFIG_SE_TILE_32',
}
ADDR_CONFIG_SE_TILE_16 = 0
ADDR_CONFIG_SE_TILE_32 = 1
ShaderEngineTileSize = ctypes.c_uint32 # enum
# values for enumeration 'MultiGPUTileSize'
MultiGPUTileSize__enumvalues = {
0: 'ADDR_CONFIG_GPU_TILE_16',
1: 'ADDR_CONFIG_GPU_TILE_32',
2: 'ADDR_CONFIG_GPU_TILE_64',
3: 'ADDR_CONFIG_GPU_TILE_128',
}
ADDR_CONFIG_GPU_TILE_16 = 0
ADDR_CONFIG_GPU_TILE_32 = 1
ADDR_CONFIG_GPU_TILE_64 = 2
ADDR_CONFIG_GPU_TILE_128 = 3
MultiGPUTileSize = ctypes.c_uint32 # enum
# values for enumeration 'RowSize'
RowSize__enumvalues = {
0: 'ADDR_CONFIG_1KB_ROW',
1: 'ADDR_CONFIG_2KB_ROW',
2: 'ADDR_CONFIG_4KB_ROW',
}
ADDR_CONFIG_1KB_ROW = 0
ADDR_CONFIG_2KB_ROW = 1
ADDR_CONFIG_4KB_ROW = 2
RowSize = ctypes.c_uint32 # enum
# values for enumeration 'NumLowerPipes'
NumLowerPipes__enumvalues = {
0: 'ADDR_CONFIG_1_LOWER_PIPES',
1: 'ADDR_CONFIG_2_LOWER_PIPES',
}
ADDR_CONFIG_1_LOWER_PIPES = 0
ADDR_CONFIG_2_LOWER_PIPES = 1
NumLowerPipes = ctypes.c_uint32 # enum
# values for enumeration 'ColorTransform'
ColorTransform__enumvalues = {
0: 'DCC_CT_AUTO',
1: 'DCC_CT_NONE',
2: 'ABGR_TO_A_BG_G_RB',
3: 'BGRA_TO_BG_G_RB_A',
}
DCC_CT_AUTO = 0
DCC_CT_NONE = 1
ABGR_TO_A_BG_G_RB = 2
BGRA_TO_BG_G_RB_A = 3
ColorTransform = ctypes.c_uint32 # enum
# values for enumeration 'CompareRef'
CompareRef__enumvalues = {
0: 'REF_NEVER',
1: 'REF_LESS',
2: 'REF_EQUAL',
3: 'REF_LEQUAL',
4: 'REF_GREATER',
5: 'REF_NOTEQUAL',
6: 'REF_GEQUAL',
7: 'REF_ALWAYS',
}
REF_NEVER = 0
REF_LESS = 1
REF_EQUAL = 2
REF_LEQUAL = 3
REF_GREATER = 4
REF_NOTEQUAL = 5
REF_GEQUAL = 6
REF_ALWAYS = 7
CompareRef = ctypes.c_uint32 # enum
# values for enumeration 'ReadSize'
ReadSize__enumvalues = {
0: 'READ_256_BITS',
1: 'READ_512_BITS',
}
READ_256_BITS = 0
READ_512_BITS = 1
ReadSize = ctypes.c_uint32 # enum
# values for enumeration 'DepthFormat'
DepthFormat__enumvalues = {
0: 'DEPTH_INVALID',
1: 'DEPTH_16',
2: 'DEPTH_X8_24',
3: 'DEPTH_8_24',
4: 'DEPTH_X8_24_FLOAT',
5: 'DEPTH_8_24_FLOAT',
6: 'DEPTH_32_FLOAT',
7: 'DEPTH_X24_8_32_FLOAT',
}
DEPTH_INVALID = 0
DEPTH_16 = 1
DEPTH_X8_24 = 2
DEPTH_8_24 = 3
DEPTH_X8_24_FLOAT = 4
DEPTH_8_24_FLOAT = 5
DEPTH_32_FLOAT = 6
DEPTH_X24_8_32_FLOAT = 7
DepthFormat = ctypes.c_uint32 # enum
# values for enumeration 'ZFormat'
ZFormat__enumvalues = {
0: 'Z_INVALID',
1: 'Z_16',
2: 'Z_24',
3: 'Z_32_FLOAT',
}
Z_INVALID = 0
Z_16 = 1
Z_24 = 2
Z_32_FLOAT = 3
ZFormat = ctypes.c_uint32 # enum
# values for enumeration 'StencilFormat'
StencilFormat__enumvalues = {
0: 'STENCIL_INVALID',
1: 'STENCIL_8',
}
STENCIL_INVALID = 0
STENCIL_8 = 1
StencilFormat = ctypes.c_uint32 # enum
# values for enumeration 'CmaskMode'
CmaskMode__enumvalues = {
0: 'CMASK_CLEAR_NONE',
1: 'CMASK_CLEAR_ONE',
2: 'CMASK_CLEAR_ALL',
3: 'CMASK_ANY_EXPANDED',
4: 'CMASK_ALPHA0_FRAG1',
5: 'CMASK_ALPHA0_FRAG2',
6: 'CMASK_ALPHA0_FRAG4',
7: 'CMASK_ALPHA0_FRAGS',
8: 'CMASK_ALPHA1_FRAG1',
9: 'CMASK_ALPHA1_FRAG2',
10: 'CMASK_ALPHA1_FRAG4',
11: 'CMASK_ALPHA1_FRAGS',
12: 'CMASK_ALPHAX_FRAG1',
13: 'CMASK_ALPHAX_FRAG2',
14: 'CMASK_ALPHAX_FRAG4',
15: 'CMASK_ALPHAX_FRAGS',
}
CMASK_CLEAR_NONE = 0
CMASK_CLEAR_ONE = 1
CMASK_CLEAR_ALL = 2
CMASK_ANY_EXPANDED = 3
CMASK_ALPHA0_FRAG1 = 4
CMASK_ALPHA0_FRAG2 = 5
CMASK_ALPHA0_FRAG4 = 6
CMASK_ALPHA0_FRAGS = 7
CMASK_ALPHA1_FRAG1 = 8
CMASK_ALPHA1_FRAG2 = 9
CMASK_ALPHA1_FRAG4 = 10
CMASK_ALPHA1_FRAGS = 11
CMASK_ALPHAX_FRAG1 = 12
CMASK_ALPHAX_FRAG2 = 13
CMASK_ALPHAX_FRAG4 = 14
CMASK_ALPHAX_FRAGS = 15
CmaskMode = ctypes.c_uint32 # enum
# values for enumeration 'QuadExportFormat'
QuadExportFormat__enumvalues = {
0: 'EXPORT_UNUSED',
1: 'EXPORT_32_R',
2: 'EXPORT_32_GR',
3: 'EXPORT_32_AR',
4: 'EXPORT_FP16_ABGR',
5: 'EXPORT_UNSIGNED16_ABGR',
6: 'EXPORT_SIGNED16_ABGR',
7: 'EXPORT_32_ABGR',
8: 'EXPORT_32BPP_8PIX',
9: 'EXPORT_16_16_UNSIGNED_8PIX',
10: 'EXPORT_16_16_SIGNED_8PIX',
11: 'EXPORT_16_16_FLOAT_8PIX',
}
EXPORT_UNUSED = 0
EXPORT_32_R = 1
EXPORT_32_GR = 2
EXPORT_32_AR = 3
EXPORT_FP16_ABGR = 4
EXPORT_UNSIGNED16_ABGR = 5
EXPORT_SIGNED16_ABGR = 6
EXPORT_32_ABGR = 7
EXPORT_32BPP_8PIX = 8
EXPORT_16_16_UNSIGNED_8PIX = 9
EXPORT_16_16_SIGNED_8PIX = 10
EXPORT_16_16_FLOAT_8PIX = 11
QuadExportFormat = ctypes.c_uint32 # enum
# values for enumeration 'QuadExportFormatOld'
QuadExportFormatOld__enumvalues = {
0: 'EXPORT_4P_32BPC_ABGR',
1: 'EXPORT_4P_16BPC_ABGR',
2: 'EXPORT_4P_32BPC_GR',
3: 'EXPORT_4P_32BPC_AR',
4: 'EXPORT_2P_32BPC_ABGR',
5: 'EXPORT_8P_32BPC_R',
}
EXPORT_4P_32BPC_ABGR = 0
EXPORT_4P_16BPC_ABGR = 1
EXPORT_4P_32BPC_GR = 2
EXPORT_4P_32BPC_AR = 3
EXPORT_2P_32BPC_ABGR = 4
EXPORT_8P_32BPC_R = 5
QuadExportFormatOld = ctypes.c_uint32 # enum
# values for enumeration 'ColorFormat'
ColorFormat__enumvalues = {
0: 'COLOR_INVALID',
1: 'COLOR_8',
2: 'COLOR_16',
3: 'COLOR_8_8',
4: 'COLOR_32',
5: 'COLOR_16_16',
6: 'COLOR_10_11_11',
7: 'COLOR_11_11_10',
8: 'COLOR_10_10_10_2',
9: 'COLOR_2_10_10_10',
10: 'COLOR_8_8_8_8',
11: 'COLOR_32_32',
12: 'COLOR_16_16_16_16',
13: 'COLOR_RESERVED_13',
14: 'COLOR_32_32_32_32',
15: 'COLOR_RESERVED_15',
16: 'COLOR_5_6_5',
17: 'COLOR_1_5_5_5',
18: 'COLOR_5_5_5_1',
19: 'COLOR_4_4_4_4',
20: 'COLOR_8_24',
21: 'COLOR_24_8',
22: 'COLOR_X24_8_32_FLOAT',
23: 'COLOR_RESERVED_23',
24: 'COLOR_RESERVED_24',
25: 'COLOR_RESERVED_25',
26: 'COLOR_RESERVED_26',
27: 'COLOR_RESERVED_27',
28: 'COLOR_RESERVED_28',
29: 'COLOR_RESERVED_29',
30: 'COLOR_RESERVED_30',
31: 'COLOR_2_10_10_10_6E4',
}
COLOR_INVALID = 0
COLOR_8 = 1
COLOR_16 = 2
COLOR_8_8 = 3
COLOR_32 = 4
COLOR_16_16 = 5
COLOR_10_11_11 = 6
COLOR_11_11_10 = 7
COLOR_10_10_10_2 = 8
COLOR_2_10_10_10 = 9
COLOR_8_8_8_8 = 10
COLOR_32_32 = 11
COLOR_16_16_16_16 = 12
COLOR_RESERVED_13 = 13
COLOR_32_32_32_32 = 14
COLOR_RESERVED_15 = 15
COLOR_5_6_5 = 16
COLOR_1_5_5_5 = 17
COLOR_5_5_5_1 = 18
COLOR_4_4_4_4 = 19
COLOR_8_24 = 20
COLOR_24_8 = 21
COLOR_X24_8_32_FLOAT = 22
COLOR_RESERVED_23 = 23
COLOR_RESERVED_24 = 24
COLOR_RESERVED_25 = 25
COLOR_RESERVED_26 = 26
COLOR_RESERVED_27 = 27
COLOR_RESERVED_28 = 28
COLOR_RESERVED_29 = 29
COLOR_RESERVED_30 = 30
COLOR_2_10_10_10_6E4 = 31
ColorFormat = ctypes.c_uint32 # enum
# values for enumeration 'SurfaceFormat'
SurfaceFormat__enumvalues = {
0: 'FMT_INVALID',
1: 'FMT_8',
2: 'FMT_16',
3: 'FMT_8_8',
4: 'FMT_32',
5: 'FMT_16_16',
6: 'FMT_10_11_11',
7: 'FMT_11_11_10',
8: 'FMT_10_10_10_2',
9: 'FMT_2_10_10_10',
10: 'FMT_8_8_8_8',
11: 'FMT_32_32',
12: 'FMT_16_16_16_16',
13: 'FMT_32_32_32',
14: 'FMT_32_32_32_32',
15: 'FMT_RESERVED_4',
16: 'FMT_5_6_5',
17: 'FMT_1_5_5_5',
18: 'FMT_5_5_5_1',
19: 'FMT_4_4_4_4',
20: 'FMT_8_24',
21: 'FMT_24_8',
22: 'FMT_X24_8_32_FLOAT',
23: 'FMT_RESERVED_33',
24: 'FMT_11_11_10_FLOAT',
25: 'FMT_16_FLOAT',
26: 'FMT_32_FLOAT',
27: 'FMT_16_16_FLOAT',
28: 'FMT_8_24_FLOAT',
29: 'FMT_24_8_FLOAT',
30: 'FMT_32_32_FLOAT',
31: 'FMT_10_11_11_FLOAT',
32: 'FMT_16_16_16_16_FLOAT',
33: 'FMT_3_3_2',
34: 'FMT_6_5_5',
35: 'FMT_32_32_32_32_FLOAT',
36: 'FMT_RESERVED_36',
37: 'FMT_1',
38: 'FMT_1_REVERSED',
39: 'FMT_GB_GR',
40: 'FMT_BG_RG',
41: 'FMT_32_AS_8',
42: 'FMT_32_AS_8_8',
43: 'FMT_5_9_9_9_SHAREDEXP',
44: 'FMT_8_8_8',
45: 'FMT_16_16_16',
46: 'FMT_16_16_16_FLOAT',
47: 'FMT_4_4',
48: 'FMT_32_32_32_FLOAT',
49: 'FMT_BC1',
50: 'FMT_BC2',
51: 'FMT_BC3',
52: 'FMT_BC4',
53: 'FMT_BC5',
54: 'FMT_BC6',
55: 'FMT_BC7',
56: 'FMT_32_AS_32_32_32_32',
57: 'FMT_APC3',
58: 'FMT_APC4',
59: 'FMT_APC5',
60: 'FMT_APC6',
61: 'FMT_APC7',
62: 'FMT_CTX1',
63: 'FMT_RESERVED_63',
}
FMT_INVALID = 0
FMT_8 = 1
FMT_16 = 2
FMT_8_8 = 3
FMT_32 = 4
FMT_16_16 = 5
FMT_10_11_11 = 6
FMT_11_11_10 = 7
FMT_10_10_10_2 = 8
FMT_2_10_10_10 = 9
FMT_8_8_8_8 = 10
FMT_32_32 = 11
FMT_16_16_16_16 = 12
FMT_32_32_32 = 13
FMT_32_32_32_32 = 14
FMT_RESERVED_4 = 15
FMT_5_6_5 = 16
FMT_1_5_5_5 = 17
FMT_5_5_5_1 = 18
FMT_4_4_4_4 = 19
FMT_8_24 = 20
FMT_24_8 = 21
FMT_X24_8_32_FLOAT = 22
FMT_RESERVED_33 = 23
FMT_11_11_10_FLOAT = 24
FMT_16_FLOAT = 25
FMT_32_FLOAT = 26
FMT_16_16_FLOAT = 27
FMT_8_24_FLOAT = 28
FMT_24_8_FLOAT = 29
FMT_32_32_FLOAT = 30
FMT_10_11_11_FLOAT = 31
FMT_16_16_16_16_FLOAT = 32
FMT_3_3_2 = 33
FMT_6_5_5 = 34
FMT_32_32_32_32_FLOAT = 35
FMT_RESERVED_36 = 36
FMT_1 = 37
FMT_1_REVERSED = 38
FMT_GB_GR = 39
FMT_BG_RG = 40
FMT_32_AS_8 = 41
FMT_32_AS_8_8 = 42
FMT_5_9_9_9_SHAREDEXP = 43
FMT_8_8_8 = 44
FMT_16_16_16 = 45
FMT_16_16_16_FLOAT = 46
FMT_4_4 = 47
FMT_32_32_32_FLOAT = 48
FMT_BC1 = 49
FMT_BC2 = 50
FMT_BC3 = 51
FMT_BC4 = 52
FMT_BC5 = 53
FMT_BC6 = 54
FMT_BC7 = 55
FMT_32_AS_32_32_32_32 = 56
FMT_APC3 = 57
FMT_APC4 = 58
FMT_APC5 = 59
FMT_APC6 = 60
FMT_APC7 = 61
FMT_CTX1 = 62
FMT_RESERVED_63 = 63
SurfaceFormat = ctypes.c_uint32 # enum
# values for enumeration 'IMG_NUM_FORMAT_FMASK'
IMG_NUM_FORMAT_FMASK__enumvalues = {
0: 'IMG_NUM_FORMAT_FMASK_8_2_1',
1: 'IMG_NUM_FORMAT_FMASK_8_4_1',
2: 'IMG_NUM_FORMAT_FMASK_8_8_1',
3: 'IMG_NUM_FORMAT_FMASK_8_2_2',
4: 'IMG_NUM_FORMAT_FMASK_8_4_2',
5: 'IMG_NUM_FORMAT_FMASK_8_4_4',
6: 'IMG_NUM_FORMAT_FMASK_16_16_1',
7: 'IMG_NUM_FORMAT_FMASK_16_8_2',
8: 'IMG_NUM_FORMAT_FMASK_32_16_2',
9: 'IMG_NUM_FORMAT_FMASK_32_8_4',
10: 'IMG_NUM_FORMAT_FMASK_32_8_8',
11: 'IMG_NUM_FORMAT_FMASK_64_16_4',
12: 'IMG_NUM_FORMAT_FMASK_64_16_8',
13: 'IMG_NUM_FORMAT_FMASK_RESERVED_13',
14: 'IMG_NUM_FORMAT_FMASK_RESERVED_14',
15: 'IMG_NUM_FORMAT_FMASK_RESERVED_15',
}
IMG_NUM_FORMAT_FMASK_8_2_1 = 0
IMG_NUM_FORMAT_FMASK_8_4_1 = 1
IMG_NUM_FORMAT_FMASK_8_8_1 = 2
IMG_NUM_FORMAT_FMASK_8_2_2 = 3
IMG_NUM_FORMAT_FMASK_8_4_2 = 4
IMG_NUM_FORMAT_FMASK_8_4_4 = 5
IMG_NUM_FORMAT_FMASK_16_16_1 = 6
IMG_NUM_FORMAT_FMASK_16_8_2 = 7
IMG_NUM_FORMAT_FMASK_32_16_2 = 8
IMG_NUM_FORMAT_FMASK_32_8_4 = 9
IMG_NUM_FORMAT_FMASK_32_8_8 = 10
IMG_NUM_FORMAT_FMASK_64_16_4 = 11
IMG_NUM_FORMAT_FMASK_64_16_8 = 12
IMG_NUM_FORMAT_FMASK_RESERVED_13 = 13
IMG_NUM_FORMAT_FMASK_RESERVED_14 = 14
IMG_NUM_FORMAT_FMASK_RESERVED_15 = 15
IMG_NUM_FORMAT_FMASK = ctypes.c_uint32 # enum
# values for enumeration 'IMG_NUM_FORMAT_N_IN_16'
IMG_NUM_FORMAT_N_IN_16__enumvalues = {
0: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_0',
1: 'IMG_NUM_FORMAT_N_IN_16_UNORM_10',
2: 'IMG_NUM_FORMAT_N_IN_16_UNORM_9',
3: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_3',
4: 'IMG_NUM_FORMAT_N_IN_16_UINT_10',
5: 'IMG_NUM_FORMAT_N_IN_16_UINT_9',
6: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_6',
7: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10',
8: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9',
9: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_9',
10: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_10',
11: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_11',
12: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_12',
13: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_13',
14: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_14',
15: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_15',
}
IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0
IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 1
IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 2
IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 3
IMG_NUM_FORMAT_N_IN_16_UINT_10 = 4
IMG_NUM_FORMAT_N_IN_16_UINT_9 = 5
IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 6
IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 7
IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 8
IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 9
IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 10
IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 11
IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 12
IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 13
IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 14
IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 15
IMG_NUM_FORMAT_N_IN_16 = ctypes.c_uint32 # enum
# values for enumeration 'TileType'
TileType__enumvalues = {
0: 'ARRAY_COLOR_TILE',
1: 'ARRAY_DEPTH_TILE',
}
ARRAY_COLOR_TILE = 0
ARRAY_DEPTH_TILE = 1
TileType = ctypes.c_uint32 # enum
# values for enumeration 'NonDispTilingOrder'
NonDispTilingOrder__enumvalues = {
0: 'ADDR_SURF_MICRO_TILING_DISPLAY',
1: 'ADDR_SURF_MICRO_TILING_NON_DISPLAY',
}
ADDR_SURF_MICRO_TILING_DISPLAY = 0
ADDR_SURF_MICRO_TILING_NON_DISPLAY = 1
NonDispTilingOrder = ctypes.c_uint32 # enum
# values for enumeration 'MicroTileMode'
MicroTileMode__enumvalues = {
0: 'ADDR_SURF_DISPLAY_MICRO_TILING',
1: 'ADDR_SURF_THIN_MICRO_TILING',
2: 'ADDR_SURF_DEPTH_MICRO_TILING',
3: 'ADDR_SURF_ROTATED_MICRO_TILING',
4: 'ADDR_SURF_THICK_MICRO_TILING',
}
ADDR_SURF_DISPLAY_MICRO_TILING = 0
ADDR_SURF_THIN_MICRO_TILING = 1
ADDR_SURF_DEPTH_MICRO_TILING = 2
ADDR_SURF_ROTATED_MICRO_TILING = 3
ADDR_SURF_THICK_MICRO_TILING = 4
MicroTileMode = ctypes.c_uint32 # enum
# values for enumeration 'TileSplit'
TileSplit__enumvalues = {
0: 'ADDR_SURF_TILE_SPLIT_64B',
1: 'ADDR_SURF_TILE_SPLIT_128B',
2: 'ADDR_SURF_TILE_SPLIT_256B',
3: 'ADDR_SURF_TILE_SPLIT_512B',
4: 'ADDR_SURF_TILE_SPLIT_1KB',
5: 'ADDR_SURF_TILE_SPLIT_2KB',
6: 'ADDR_SURF_TILE_SPLIT_4KB',
}
ADDR_SURF_TILE_SPLIT_64B = 0
ADDR_SURF_TILE_SPLIT_128B = 1
ADDR_SURF_TILE_SPLIT_256B = 2
ADDR_SURF_TILE_SPLIT_512B = 3
ADDR_SURF_TILE_SPLIT_1KB = 4
ADDR_SURF_TILE_SPLIT_2KB = 5
ADDR_SURF_TILE_SPLIT_4KB = 6
TileSplit = ctypes.c_uint32 # enum
# values for enumeration 'SampleSplit'
SampleSplit__enumvalues = {
0: 'ADDR_SURF_SAMPLE_SPLIT_1',
1: 'ADDR_SURF_SAMPLE_SPLIT_2',
2: 'ADDR_SURF_SAMPLE_SPLIT_4',
3: 'ADDR_SURF_SAMPLE_SPLIT_8',
}
ADDR_SURF_SAMPLE_SPLIT_1 = 0
ADDR_SURF_SAMPLE_SPLIT_2 = 1
ADDR_SURF_SAMPLE_SPLIT_4 = 2
ADDR_SURF_SAMPLE_SPLIT_8 = 3
SampleSplit = ctypes.c_uint32 # enum
# values for enumeration 'PipeConfig'
PipeConfig__enumvalues = {
0: 'ADDR_SURF_P2',
1: 'ADDR_SURF_P2_RESERVED0',
2: 'ADDR_SURF_P2_RESERVED1',
3: 'ADDR_SURF_P2_RESERVED2',
4: 'ADDR_SURF_P4_8x16',
5: 'ADDR_SURF_P4_16x16',
6: 'ADDR_SURF_P4_16x32',
7: 'ADDR_SURF_P4_32x32',
8: 'ADDR_SURF_P8_16x16_8x16',
9: 'ADDR_SURF_P8_16x32_8x16',
10: 'ADDR_SURF_P8_32x32_8x16',
11: 'ADDR_SURF_P8_16x32_16x16',
12: 'ADDR_SURF_P8_32x32_16x16',
13: 'ADDR_SURF_P8_32x32_16x32',
14: 'ADDR_SURF_P8_32x64_32x32',
15: 'ADDR_SURF_P8_RESERVED0',
16: 'ADDR_SURF_P16_32x32_8x16',
17: 'ADDR_SURF_P16_32x32_16x16',
18: 'ADDR_SURF_P16',
}
ADDR_SURF_P2 = 0
ADDR_SURF_P2_RESERVED0 = 1
ADDR_SURF_P2_RESERVED1 = 2
ADDR_SURF_P2_RESERVED2 = 3
ADDR_SURF_P4_8x16 = 4
ADDR_SURF_P4_16x16 = 5
ADDR_SURF_P4_16x32 = 6
ADDR_SURF_P4_32x32 = 7
ADDR_SURF_P8_16x16_8x16 = 8
ADDR_SURF_P8_16x32_8x16 = 9
ADDR_SURF_P8_32x32_8x16 = 10
ADDR_SURF_P8_16x32_16x16 = 11
ADDR_SURF_P8_32x32_16x16 = 12
ADDR_SURF_P8_32x32_16x32 = 13
ADDR_SURF_P8_32x64_32x32 = 14
ADDR_SURF_P8_RESERVED0 = 15
ADDR_SURF_P16_32x32_8x16 = 16
ADDR_SURF_P16_32x32_16x16 = 17
ADDR_SURF_P16 = 18
PipeConfig = ctypes.c_uint32 # enum
# values for enumeration 'SeEnable'
SeEnable__enumvalues = {
0: 'ADDR_CONFIG_DISABLE_SE',
1: 'ADDR_CONFIG_ENABLE_SE',
}
ADDR_CONFIG_DISABLE_SE = 0
ADDR_CONFIG_ENABLE_SE = 1
SeEnable = ctypes.c_uint32 # enum
# values for enumeration 'NumBanks'
NumBanks__enumvalues = {
0: 'ADDR_SURF_2_BANK',
1: 'ADDR_SURF_4_BANK',
2: 'ADDR_SURF_8_BANK',
3: 'ADDR_SURF_16_BANK',
}
ADDR_SURF_2_BANK = 0
ADDR_SURF_4_BANK = 1
ADDR_SURF_8_BANK = 2
ADDR_SURF_16_BANK = 3
NumBanks = ctypes.c_uint32 # enum
# values for enumeration 'BankWidth'
BankWidth__enumvalues = {
0: 'ADDR_SURF_BANK_WIDTH_1',
1: 'ADDR_SURF_BANK_WIDTH_2',
2: 'ADDR_SURF_BANK_WIDTH_4',
3: 'ADDR_SURF_BANK_WIDTH_8',
}
ADDR_SURF_BANK_WIDTH_1 = 0
ADDR_SURF_BANK_WIDTH_2 = 1
ADDR_SURF_BANK_WIDTH_4 = 2
ADDR_SURF_BANK_WIDTH_8 = 3
BankWidth = ctypes.c_uint32 # enum
# values for enumeration 'BankHeight'
BankHeight__enumvalues = {
0: 'ADDR_SURF_BANK_HEIGHT_1',
1: 'ADDR_SURF_BANK_HEIGHT_2',
2: 'ADDR_SURF_BANK_HEIGHT_4',
3: 'ADDR_SURF_BANK_HEIGHT_8',
}
ADDR_SURF_BANK_HEIGHT_1 = 0
ADDR_SURF_BANK_HEIGHT_2 = 1
ADDR_SURF_BANK_HEIGHT_4 = 2
ADDR_SURF_BANK_HEIGHT_8 = 3
BankHeight = ctypes.c_uint32 # enum
# values for enumeration 'BankWidthHeight'
BankWidthHeight__enumvalues = {
0: 'ADDR_SURF_BANK_WH_1',
1: 'ADDR_SURF_BANK_WH_2',
2: 'ADDR_SURF_BANK_WH_4',
3: 'ADDR_SURF_BANK_WH_8',
}
ADDR_SURF_BANK_WH_1 = 0
ADDR_SURF_BANK_WH_2 = 1
ADDR_SURF_BANK_WH_4 = 2
ADDR_SURF_BANK_WH_8 = 3
BankWidthHeight = ctypes.c_uint32 # enum
# values for enumeration 'MacroTileAspect'
MacroTileAspect__enumvalues = {
0: 'ADDR_SURF_MACRO_ASPECT_1',
1: 'ADDR_SURF_MACRO_ASPECT_2',
2: 'ADDR_SURF_MACRO_ASPECT_4',
3: 'ADDR_SURF_MACRO_ASPECT_8',
}
ADDR_SURF_MACRO_ASPECT_1 = 0
ADDR_SURF_MACRO_ASPECT_2 = 1
ADDR_SURF_MACRO_ASPECT_4 = 2
ADDR_SURF_MACRO_ASPECT_8 = 3
MacroTileAspect = ctypes.c_uint32 # enum
# values for enumeration 'PipeTiling'
PipeTiling__enumvalues = {
0: 'CONFIG_1_PIPE',
1: 'CONFIG_2_PIPE',
2: 'CONFIG_4_PIPE',
3: 'CONFIG_8_PIPE',
}
CONFIG_1_PIPE = 0
CONFIG_2_PIPE = 1
CONFIG_4_PIPE = 2
CONFIG_8_PIPE = 3
PipeTiling = ctypes.c_uint32 # enum
# values for enumeration 'BankTiling'
BankTiling__enumvalues = {
0: 'CONFIG_4_BANK',
1: 'CONFIG_8_BANK',
}
CONFIG_4_BANK = 0
CONFIG_8_BANK = 1
BankTiling = ctypes.c_uint32 # enum
# values for enumeration 'GroupInterleave'
GroupInterleave__enumvalues = {
0: 'CONFIG_256B_GROUP',
1: 'CONFIG_512B_GROUP',
}
CONFIG_256B_GROUP = 0
CONFIG_512B_GROUP = 1
GroupInterleave = ctypes.c_uint32 # enum
# values for enumeration 'RowTiling'
RowTiling__enumvalues = {
0: 'CONFIG_1KB_ROW',
1: 'CONFIG_2KB_ROW',
2: 'CONFIG_4KB_ROW',
3: 'CONFIG_8KB_ROW',
4: 'CONFIG_1KB_ROW_OPT',
5: 'CONFIG_2KB_ROW_OPT',
6: 'CONFIG_4KB_ROW_OPT',
7: 'CONFIG_8KB_ROW_OPT',
}
CONFIG_1KB_ROW = 0
CONFIG_2KB_ROW = 1
CONFIG_4KB_ROW = 2
CONFIG_8KB_ROW = 3
CONFIG_1KB_ROW_OPT = 4
CONFIG_2KB_ROW_OPT = 5
CONFIG_4KB_ROW_OPT = 6
CONFIG_8KB_ROW_OPT = 7
RowTiling = ctypes.c_uint32 # enum
# values for enumeration 'BankSwapBytes'
BankSwapBytes__enumvalues = {
0: 'CONFIG_128B_SWAPS',
1: 'CONFIG_256B_SWAPS',
2: 'CONFIG_512B_SWAPS',
3: 'CONFIG_1KB_SWAPS',
}
CONFIG_128B_SWAPS = 0
CONFIG_256B_SWAPS = 1
CONFIG_512B_SWAPS = 2
CONFIG_1KB_SWAPS = 3
BankSwapBytes = ctypes.c_uint32 # enum
# values for enumeration 'SampleSplitBytes'
SampleSplitBytes__enumvalues = {
0: 'CONFIG_1KB_SPLIT',
1: 'CONFIG_2KB_SPLIT',
2: 'CONFIG_4KB_SPLIT',
3: 'CONFIG_8KB_SPLIT',
}
CONFIG_1KB_SPLIT = 0
CONFIG_2KB_SPLIT = 1
CONFIG_4KB_SPLIT = 2
CONFIG_8KB_SPLIT = 3
SampleSplitBytes = ctypes.c_uint32 # enum
# values for enumeration 'SurfaceNumber'
SurfaceNumber__enumvalues = {
0: 'NUMBER_UNORM',
1: 'NUMBER_SNORM',
2: 'NUMBER_USCALED',
3: 'NUMBER_SSCALED',
4: 'NUMBER_UINT',
5: 'NUMBER_SINT',
6: 'NUMBER_SRGB',
7: 'NUMBER_FLOAT',
}
NUMBER_UNORM = 0
NUMBER_SNORM = 1
NUMBER_USCALED = 2
NUMBER_SSCALED = 3
NUMBER_UINT = 4
NUMBER_SINT = 5
NUMBER_SRGB = 6
NUMBER_FLOAT = 7
SurfaceNumber = ctypes.c_uint32 # enum
# values for enumeration 'SurfaceSwap'
SurfaceSwap__enumvalues = {
0: 'SWAP_STD',
1: 'SWAP_ALT',
2: 'SWAP_STD_REV',
3: 'SWAP_ALT_REV',
}
SWAP_STD = 0
SWAP_ALT = 1
SWAP_STD_REV = 2
SWAP_ALT_REV = 3
SurfaceSwap = ctypes.c_uint32 # enum
# values for enumeration 'RoundMode'
RoundMode__enumvalues = {
0: 'ROUND_BY_HALF',
1: 'ROUND_TRUNCATE',
}
ROUND_BY_HALF = 0
ROUND_TRUNCATE = 1
RoundMode = ctypes.c_uint32 # enum
# values for enumeration 'BUF_FMT'
BUF_FMT__enumvalues = {
0: 'BUF_FMT_INVALID',
1: 'BUF_FMT_8_UNORM',
2: 'BUF_FMT_8_SNORM',
3: 'BUF_FMT_8_USCALED',
4: 'BUF_FMT_8_SSCALED',
5: 'BUF_FMT_8_UINT',
6: 'BUF_FMT_8_SINT',
7: 'BUF_FMT_16_UNORM',
8: 'BUF_FMT_16_SNORM',
9: 'BUF_FMT_16_USCALED',
10: 'BUF_FMT_16_SSCALED',
11: 'BUF_FMT_16_UINT',
12: 'BUF_FMT_16_SINT',
13: 'BUF_FMT_16_FLOAT',
14: 'BUF_FMT_8_8_UNORM',
15: 'BUF_FMT_8_8_SNORM',
16: 'BUF_FMT_8_8_USCALED',
17: 'BUF_FMT_8_8_SSCALED',
18: 'BUF_FMT_8_8_UINT',
19: 'BUF_FMT_8_8_SINT',
20: 'BUF_FMT_32_UINT',
21: 'BUF_FMT_32_SINT',
22: 'BUF_FMT_32_FLOAT',
23: 'BUF_FMT_16_16_UNORM',
24: 'BUF_FMT_16_16_SNORM',
25: 'BUF_FMT_16_16_USCALED',
26: 'BUF_FMT_16_16_SSCALED',
27: 'BUF_FMT_16_16_UINT',
28: 'BUF_FMT_16_16_SINT',
29: 'BUF_FMT_16_16_FLOAT',
30: 'BUF_FMT_10_11_11_UNORM',
31: 'BUF_FMT_10_11_11_SNORM',
32: 'BUF_FMT_10_11_11_USCALED',
33: 'BUF_FMT_10_11_11_SSCALED',
34: 'BUF_FMT_10_11_11_UINT',
35: 'BUF_FMT_10_11_11_SINT',
36: 'BUF_FMT_10_11_11_FLOAT',
37: 'BUF_FMT_11_11_10_UNORM',
38: 'BUF_FMT_11_11_10_SNORM',
39: 'BUF_FMT_11_11_10_USCALED',
40: 'BUF_FMT_11_11_10_SSCALED',
41: 'BUF_FMT_11_11_10_UINT',
42: 'BUF_FMT_11_11_10_SINT',
43: 'BUF_FMT_11_11_10_FLOAT',
44: 'BUF_FMT_10_10_10_2_UNORM',
45: 'BUF_FMT_10_10_10_2_SNORM',
46: 'BUF_FMT_10_10_10_2_USCALED',
47: 'BUF_FMT_10_10_10_2_SSCALED',
48: 'BUF_FMT_10_10_10_2_UINT',
49: 'BUF_FMT_10_10_10_2_SINT',
50: 'BUF_FMT_2_10_10_10_UNORM',
51: 'BUF_FMT_2_10_10_10_SNORM',
52: 'BUF_FMT_2_10_10_10_USCALED',
53: 'BUF_FMT_2_10_10_10_SSCALED',
54: 'BUF_FMT_2_10_10_10_UINT',
55: 'BUF_FMT_2_10_10_10_SINT',
56: 'BUF_FMT_8_8_8_8_UNORM',
57: 'BUF_FMT_8_8_8_8_SNORM',
58: 'BUF_FMT_8_8_8_8_USCALED',
59: 'BUF_FMT_8_8_8_8_SSCALED',
60: 'BUF_FMT_8_8_8_8_UINT',
61: 'BUF_FMT_8_8_8_8_SINT',
62: 'BUF_FMT_32_32_UINT',
63: 'BUF_FMT_32_32_SINT',
64: 'BUF_FMT_32_32_FLOAT',
65: 'BUF_FMT_16_16_16_16_UNORM',
66: 'BUF_FMT_16_16_16_16_SNORM',
67: 'BUF_FMT_16_16_16_16_USCALED',
68: 'BUF_FMT_16_16_16_16_SSCALED',
69: 'BUF_FMT_16_16_16_16_UINT',
70: 'BUF_FMT_16_16_16_16_SINT',
71: 'BUF_FMT_16_16_16_16_FLOAT',
72: 'BUF_FMT_32_32_32_UINT',
73: 'BUF_FMT_32_32_32_SINT',
74: 'BUF_FMT_32_32_32_FLOAT',
75: 'BUF_FMT_32_32_32_32_UINT',
76: 'BUF_FMT_32_32_32_32_SINT',
77: 'BUF_FMT_32_32_32_32_FLOAT',
78: 'BUF_FMT_RESERVED_78',
79: 'BUF_FMT_RESERVED_79',
80: 'BUF_FMT_RESERVED_80',
81: 'BUF_FMT_RESERVED_81',
82: 'BUF_FMT_RESERVED_82',
83: 'BUF_FMT_RESERVED_83',
84: 'BUF_FMT_RESERVED_84',
85: 'BUF_FMT_RESERVED_85',
86: 'BUF_FMT_RESERVED_86',
87: 'BUF_FMT_RESERVED_87',
88: 'BUF_FMT_RESERVED_88',
89: 'BUF_FMT_RESERVED_89',
90: 'BUF_FMT_RESERVED_90',
91: 'BUF_FMT_RESERVED_91',
92: 'BUF_FMT_RESERVED_92',
93: 'BUF_FMT_RESERVED_93',
94: 'BUF_FMT_RESERVED_94',
95: 'BUF_FMT_RESERVED_95',
96: 'BUF_FMT_RESERVED_96',
97: 'BUF_FMT_RESERVED_97',
98: 'BUF_FMT_RESERVED_98',
99: 'BUF_FMT_RESERVED_99',
100: 'BUF_FMT_RESERVED_100',
101: 'BUF_FMT_RESERVED_101',
102: 'BUF_FMT_RESERVED_102',
103: 'BUF_FMT_RESERVED_103',
104: 'BUF_FMT_RESERVED_104',
105: 'BUF_FMT_RESERVED_105',
106: 'BUF_FMT_RESERVED_106',
107: 'BUF_FMT_RESERVED_107',
108: 'BUF_FMT_RESERVED_108',
109: 'BUF_FMT_RESERVED_109',
110: 'BUF_FMT_RESERVED_110',
111: 'BUF_FMT_RESERVED_111',
112: 'BUF_FMT_RESERVED_112',
113: 'BUF_FMT_RESERVED_113',
114: 'BUF_FMT_RESERVED_114',
115: 'BUF_FMT_RESERVED_115',
116: 'BUF_FMT_RESERVED_116',
117: 'BUF_FMT_RESERVED_117',
118: 'BUF_FMT_RESERVED_118',
119: 'BUF_FMT_RESERVED_119',
120: 'BUF_FMT_RESERVED_120',
121: 'BUF_FMT_RESERVED_121',
122: 'BUF_FMT_RESERVED_122',
123: 'BUF_FMT_RESERVED_123',
124: 'BUF_FMT_RESERVED_124',
125: 'BUF_FMT_RESERVED_125',
126: 'BUF_FMT_RESERVED_126',
127: 'BUF_FMT_RESERVED_127',
}
BUF_FMT_INVALID = 0
BUF_FMT_8_UNORM = 1
BUF_FMT_8_SNORM = 2
BUF_FMT_8_USCALED = 3
BUF_FMT_8_SSCALED = 4
BUF_FMT_8_UINT = 5
BUF_FMT_8_SINT = 6
BUF_FMT_16_UNORM = 7
BUF_FMT_16_SNORM = 8
BUF_FMT_16_USCALED = 9
BUF_FMT_16_SSCALED = 10
BUF_FMT_16_UINT = 11
BUF_FMT_16_SINT = 12
BUF_FMT_16_FLOAT = 13
BUF_FMT_8_8_UNORM = 14
BUF_FMT_8_8_SNORM = 15
BUF_FMT_8_8_USCALED = 16
BUF_FMT_8_8_SSCALED = 17
BUF_FMT_8_8_UINT = 18
BUF_FMT_8_8_SINT = 19
BUF_FMT_32_UINT = 20
BUF_FMT_32_SINT = 21
BUF_FMT_32_FLOAT = 22
BUF_FMT_16_16_UNORM = 23
BUF_FMT_16_16_SNORM = 24
BUF_FMT_16_16_USCALED = 25
BUF_FMT_16_16_SSCALED = 26
BUF_FMT_16_16_UINT = 27
BUF_FMT_16_16_SINT = 28
BUF_FMT_16_16_FLOAT = 29
BUF_FMT_10_11_11_UNORM = 30
BUF_FMT_10_11_11_SNORM = 31
BUF_FMT_10_11_11_USCALED = 32
BUF_FMT_10_11_11_SSCALED = 33
BUF_FMT_10_11_11_UINT = 34
BUF_FMT_10_11_11_SINT = 35
BUF_FMT_10_11_11_FLOAT = 36
BUF_FMT_11_11_10_UNORM = 37
BUF_FMT_11_11_10_SNORM = 38
BUF_FMT_11_11_10_USCALED = 39
BUF_FMT_11_11_10_SSCALED = 40
BUF_FMT_11_11_10_UINT = 41
BUF_FMT_11_11_10_SINT = 42
BUF_FMT_11_11_10_FLOAT = 43
BUF_FMT_10_10_10_2_UNORM = 44
BUF_FMT_10_10_10_2_SNORM = 45
BUF_FMT_10_10_10_2_USCALED = 46
BUF_FMT_10_10_10_2_SSCALED = 47
BUF_FMT_10_10_10_2_UINT = 48
BUF_FMT_10_10_10_2_SINT = 49
BUF_FMT_2_10_10_10_UNORM = 50
BUF_FMT_2_10_10_10_SNORM = 51
BUF_FMT_2_10_10_10_USCALED = 52
BUF_FMT_2_10_10_10_SSCALED = 53
BUF_FMT_2_10_10_10_UINT = 54
BUF_FMT_2_10_10_10_SINT = 55
BUF_FMT_8_8_8_8_UNORM = 56
BUF_FMT_8_8_8_8_SNORM = 57
BUF_FMT_8_8_8_8_USCALED = 58
BUF_FMT_8_8_8_8_SSCALED = 59
BUF_FMT_8_8_8_8_UINT = 60
BUF_FMT_8_8_8_8_SINT = 61
BUF_FMT_32_32_UINT = 62
BUF_FMT_32_32_SINT = 63
BUF_FMT_32_32_FLOAT = 64
BUF_FMT_16_16_16_16_UNORM = 65
BUF_FMT_16_16_16_16_SNORM = 66
BUF_FMT_16_16_16_16_USCALED = 67
BUF_FMT_16_16_16_16_SSCALED = 68
BUF_FMT_16_16_16_16_UINT = 69
BUF_FMT_16_16_16_16_SINT = 70
BUF_FMT_16_16_16_16_FLOAT = 71
BUF_FMT_32_32_32_UINT = 72
BUF_FMT_32_32_32_SINT = 73
BUF_FMT_32_32_32_FLOAT = 74
BUF_FMT_32_32_32_32_UINT = 75
BUF_FMT_32_32_32_32_SINT = 76
BUF_FMT_32_32_32_32_FLOAT = 77
BUF_FMT_RESERVED_78 = 78
BUF_FMT_RESERVED_79 = 79
BUF_FMT_RESERVED_80 = 80
BUF_FMT_RESERVED_81 = 81
BUF_FMT_RESERVED_82 = 82
BUF_FMT_RESERVED_83 = 83
BUF_FMT_RESERVED_84 = 84
BUF_FMT_RESERVED_85 = 85
BUF_FMT_RESERVED_86 = 86
BUF_FMT_RESERVED_87 = 87
BUF_FMT_RESERVED_88 = 88
BUF_FMT_RESERVED_89 = 89
BUF_FMT_RESERVED_90 = 90
BUF_FMT_RESERVED_91 = 91
BUF_FMT_RESERVED_92 = 92
BUF_FMT_RESERVED_93 = 93
BUF_FMT_RESERVED_94 = 94
BUF_FMT_RESERVED_95 = 95
BUF_FMT_RESERVED_96 = 96
BUF_FMT_RESERVED_97 = 97
BUF_FMT_RESERVED_98 = 98
BUF_FMT_RESERVED_99 = 99
BUF_FMT_RESERVED_100 = 100
BUF_FMT_RESERVED_101 = 101
BUF_FMT_RESERVED_102 = 102
BUF_FMT_RESERVED_103 = 103
BUF_FMT_RESERVED_104 = 104
BUF_FMT_RESERVED_105 = 105
BUF_FMT_RESERVED_106 = 106
BUF_FMT_RESERVED_107 = 107
BUF_FMT_RESERVED_108 = 108
BUF_FMT_RESERVED_109 = 109
BUF_FMT_RESERVED_110 = 110
BUF_FMT_RESERVED_111 = 111
BUF_FMT_RESERVED_112 = 112
BUF_FMT_RESERVED_113 = 113
BUF_FMT_RESERVED_114 = 114
BUF_FMT_RESERVED_115 = 115
BUF_FMT_RESERVED_116 = 116
BUF_FMT_RESERVED_117 = 117
BUF_FMT_RESERVED_118 = 118
BUF_FMT_RESERVED_119 = 119
BUF_FMT_RESERVED_120 = 120
BUF_FMT_RESERVED_121 = 121
BUF_FMT_RESERVED_122 = 122
BUF_FMT_RESERVED_123 = 123
BUF_FMT_RESERVED_124 = 124
BUF_FMT_RESERVED_125 = 125
BUF_FMT_RESERVED_126 = 126
BUF_FMT_RESERVED_127 = 127
BUF_FMT = ctypes.c_uint32 # enum
# values for enumeration 'IMG_FMT'
IMG_FMT__enumvalues = {
0: 'IMG_FMT_INVALID',
1: 'IMG_FMT_8_UNORM',
2: 'IMG_FMT_8_SNORM',
3: 'IMG_FMT_8_USCALED',
4: 'IMG_FMT_8_SSCALED',
5: 'IMG_FMT_8_UINT',
6: 'IMG_FMT_8_SINT',
7: 'IMG_FMT_16_UNORM',
8: 'IMG_FMT_16_SNORM',
9: 'IMG_FMT_16_USCALED',
10: 'IMG_FMT_16_SSCALED',
11: 'IMG_FMT_16_UINT',
12: 'IMG_FMT_16_SINT',
13: 'IMG_FMT_16_FLOAT',
14: 'IMG_FMT_8_8_UNORM',
15: 'IMG_FMT_8_8_SNORM',
16: 'IMG_FMT_8_8_USCALED',
17: 'IMG_FMT_8_8_SSCALED',
18: 'IMG_FMT_8_8_UINT',
19: 'IMG_FMT_8_8_SINT',
20: 'IMG_FMT_32_UINT',
21: 'IMG_FMT_32_SINT',
22: 'IMG_FMT_32_FLOAT',
23: 'IMG_FMT_16_16_UNORM',
24: 'IMG_FMT_16_16_SNORM',
25: 'IMG_FMT_16_16_USCALED',
26: 'IMG_FMT_16_16_SSCALED',
27: 'IMG_FMT_16_16_UINT',
28: 'IMG_FMT_16_16_SINT',
29: 'IMG_FMT_16_16_FLOAT',
30: 'IMG_FMT_10_11_11_UNORM',
31: 'IMG_FMT_10_11_11_SNORM',
32: 'IMG_FMT_10_11_11_USCALED',
33: 'IMG_FMT_10_11_11_SSCALED',
34: 'IMG_FMT_10_11_11_UINT',
35: 'IMG_FMT_10_11_11_SINT',
36: 'IMG_FMT_10_11_11_FLOAT',
37: 'IMG_FMT_11_11_10_UNORM',
38: 'IMG_FMT_11_11_10_SNORM',
39: 'IMG_FMT_11_11_10_USCALED',
40: 'IMG_FMT_11_11_10_SSCALED',
41: 'IMG_FMT_11_11_10_UINT',
42: 'IMG_FMT_11_11_10_SINT',
43: 'IMG_FMT_11_11_10_FLOAT',
44: 'IMG_FMT_10_10_10_2_UNORM',
45: 'IMG_FMT_10_10_10_2_SNORM',
46: 'IMG_FMT_10_10_10_2_USCALED',
47: 'IMG_FMT_10_10_10_2_SSCALED',
48: 'IMG_FMT_10_10_10_2_UINT',
49: 'IMG_FMT_10_10_10_2_SINT',
50: 'IMG_FMT_2_10_10_10_UNORM',
51: 'IMG_FMT_2_10_10_10_SNORM',
52: 'IMG_FMT_2_10_10_10_USCALED',
53: 'IMG_FMT_2_10_10_10_SSCALED',
54: 'IMG_FMT_2_10_10_10_UINT',
55: 'IMG_FMT_2_10_10_10_SINT',
56: 'IMG_FMT_8_8_8_8_UNORM',
57: 'IMG_FMT_8_8_8_8_SNORM',
58: 'IMG_FMT_8_8_8_8_USCALED',
59: 'IMG_FMT_8_8_8_8_SSCALED',
60: 'IMG_FMT_8_8_8_8_UINT',
61: 'IMG_FMT_8_8_8_8_SINT',
62: 'IMG_FMT_32_32_UINT',
63: 'IMG_FMT_32_32_SINT',
64: 'IMG_FMT_32_32_FLOAT',
65: 'IMG_FMT_16_16_16_16_UNORM',
66: 'IMG_FMT_16_16_16_16_SNORM',
67: 'IMG_FMT_16_16_16_16_USCALED',
68: 'IMG_FMT_16_16_16_16_SSCALED',
69: 'IMG_FMT_16_16_16_16_UINT',
70: 'IMG_FMT_16_16_16_16_SINT',
71: 'IMG_FMT_16_16_16_16_FLOAT',
72: 'IMG_FMT_32_32_32_UINT',
73: 'IMG_FMT_32_32_32_SINT',
74: 'IMG_FMT_32_32_32_FLOAT',
75: 'IMG_FMT_32_32_32_32_UINT',
76: 'IMG_FMT_32_32_32_32_SINT',
77: 'IMG_FMT_32_32_32_32_FLOAT',
78: 'IMG_FMT_RESERVED_78',
79: 'IMG_FMT_RESERVED_79',
80: 'IMG_FMT_RESERVED_80',
81: 'IMG_FMT_RESERVED_81',
82: 'IMG_FMT_RESERVED_82',
83: 'IMG_FMT_RESERVED_83',
84: 'IMG_FMT_RESERVED_84',
85: 'IMG_FMT_RESERVED_85',
86: 'IMG_FMT_RESERVED_86',
87: 'IMG_FMT_RESERVED_87',
88: 'IMG_FMT_RESERVED_88',
89: 'IMG_FMT_RESERVED_89',
90: 'IMG_FMT_RESERVED_90',
91: 'IMG_FMT_RESERVED_91',
92: 'IMG_FMT_RESERVED_92',
93: 'IMG_FMT_RESERVED_93',
94: 'IMG_FMT_RESERVED_94',
95: 'IMG_FMT_RESERVED_95',
96: 'IMG_FMT_RESERVED_96',
97: 'IMG_FMT_RESERVED_97',
98: 'IMG_FMT_RESERVED_98',
99: 'IMG_FMT_RESERVED_99',
100: 'IMG_FMT_RESERVED_100',
101: 'IMG_FMT_RESERVED_101',
102: 'IMG_FMT_RESERVED_102',
103: 'IMG_FMT_RESERVED_103',
104: 'IMG_FMT_RESERVED_104',
105: 'IMG_FMT_RESERVED_105',
106: 'IMG_FMT_RESERVED_106',
107: 'IMG_FMT_RESERVED_107',
108: 'IMG_FMT_RESERVED_108',
109: 'IMG_FMT_RESERVED_109',
110: 'IMG_FMT_RESERVED_110',
111: 'IMG_FMT_RESERVED_111',
112: 'IMG_FMT_RESERVED_112',
113: 'IMG_FMT_RESERVED_113',
114: 'IMG_FMT_RESERVED_114',
115: 'IMG_FMT_RESERVED_115',
116: 'IMG_FMT_RESERVED_116',
117: 'IMG_FMT_RESERVED_117',
118: 'IMG_FMT_RESERVED_118',
119: 'IMG_FMT_RESERVED_119',
120: 'IMG_FMT_RESERVED_120',
121: 'IMG_FMT_RESERVED_121',
122: 'IMG_FMT_RESERVED_122',
123: 'IMG_FMT_RESERVED_123',
124: 'IMG_FMT_RESERVED_124',
125: 'IMG_FMT_RESERVED_125',
126: 'IMG_FMT_RESERVED_126',
127: 'IMG_FMT_RESERVED_127',
128: 'IMG_FMT_8_SRGB',
129: 'IMG_FMT_8_8_SRGB',
130: 'IMG_FMT_8_8_8_8_SRGB',
131: 'IMG_FMT_6E4_FLOAT',
132: 'IMG_FMT_5_9_9_9_FLOAT',
133: 'IMG_FMT_5_6_5_UNORM',
134: 'IMG_FMT_1_5_5_5_UNORM',
135: 'IMG_FMT_5_5_5_1_UNORM',
136: 'IMG_FMT_4_4_4_4_UNORM',
137: 'IMG_FMT_4_4_UNORM',
138: 'IMG_FMT_1_UNORM',
139: 'IMG_FMT_1_REVERSED_UNORM',
140: 'IMG_FMT_32_FLOAT_CLAMP',
141: 'IMG_FMT_8_24_UNORM',
142: 'IMG_FMT_8_24_UINT',
143: 'IMG_FMT_24_8_UNORM',
144: 'IMG_FMT_24_8_UINT',
145: 'IMG_FMT_X24_8_32_UINT',
146: 'IMG_FMT_X24_8_32_FLOAT',
147: 'IMG_FMT_GB_GR_UNORM',
148: 'IMG_FMT_GB_GR_SNORM',
149: 'IMG_FMT_GB_GR_UINT',
150: 'IMG_FMT_GB_GR_SRGB',
151: 'IMG_FMT_BG_RG_UNORM',
152: 'IMG_FMT_BG_RG_SNORM',
153: 'IMG_FMT_BG_RG_UINT',
154: 'IMG_FMT_BG_RG_SRGB',
155: 'IMG_FMT_RESERVED_155',
156: 'IMG_FMT_FMASK8_S2_F1',
157: 'IMG_FMT_FMASK8_S4_F1',
158: 'IMG_FMT_FMASK8_S8_F1',
159: 'IMG_FMT_FMASK8_S2_F2',
160: 'IMG_FMT_FMASK8_S4_F2',
161: 'IMG_FMT_FMASK8_S4_F4',
162: 'IMG_FMT_FMASK16_S16_F1',
163: 'IMG_FMT_FMASK16_S8_F2',
164: 'IMG_FMT_FMASK32_S16_F2',
165: 'IMG_FMT_FMASK32_S8_F4',
166: 'IMG_FMT_FMASK32_S8_F8',
167: 'IMG_FMT_FMASK64_S16_F4',
168: 'IMG_FMT_FMASK64_S16_F8',
169: 'IMG_FMT_BC1_UNORM',
170: 'IMG_FMT_BC1_SRGB',
171: 'IMG_FMT_BC2_UNORM',
172: 'IMG_FMT_BC2_SRGB',
173: 'IMG_FMT_BC3_UNORM',
174: 'IMG_FMT_BC3_SRGB',
175: 'IMG_FMT_BC4_UNORM',
176: 'IMG_FMT_BC4_SNORM',
177: 'IMG_FMT_BC5_UNORM',
178: 'IMG_FMT_BC5_SNORM',
179: 'IMG_FMT_BC6_UFLOAT',
180: 'IMG_FMT_BC6_SFLOAT',
181: 'IMG_FMT_BC7_UNORM',
182: 'IMG_FMT_BC7_SRGB',
265: 'IMG_FMT_MM_8_UNORM',
266: 'IMG_FMT_MM_8_UINT',
267: 'IMG_FMT_MM_8_8_UNORM',
268: 'IMG_FMT_MM_8_8_UINT',
269: 'IMG_FMT_MM_8_8_8_8_UNORM',
270: 'IMG_FMT_MM_8_8_8_8_UINT',
271: 'IMG_FMT_MM_VYUY8_UNORM',
272: 'IMG_FMT_MM_VYUY8_UINT',
273: 'IMG_FMT_MM_10_11_11_UNORM',
274: 'IMG_FMT_MM_10_11_11_UINT',
275: 'IMG_FMT_MM_2_10_10_10_UNORM',
276: 'IMG_FMT_MM_2_10_10_10_UINT',
277: 'IMG_FMT_MM_16_16_16_16_UNORM',
278: 'IMG_FMT_MM_16_16_16_16_UINT',
279: 'IMG_FMT_MM_10_IN_16_UNORM',
280: 'IMG_FMT_MM_10_IN_16_UINT',
281: 'IMG_FMT_MM_10_IN_16_16_UNORM',
282: 'IMG_FMT_MM_10_IN_16_16_UINT',
283: 'IMG_FMT_MM_10_IN_16_16_16_16_UNORM',
284: 'IMG_FMT_MM_10_IN_16_16_16_16_UINT',
285: 'IMG_FMT_RESERVED_285',
286: 'IMG_FMT_RESERVED_286',
287: 'IMG_FMT_RESERVED_287',
288: 'IMG_FMT_RESERVED_288',
289: 'IMG_FMT_RESERVED_289',
290: 'IMG_FMT_RESERVED_290',
291: 'IMG_FMT_RESERVED_291',
292: 'IMG_FMT_RESERVED_292',
293: 'IMG_FMT_RESERVED_293',
294: 'IMG_FMT_RESERVED_294',
295: 'IMG_FMT_RESERVED_295',
296: 'IMG_FMT_RESERVED_296',
297: 'IMG_FMT_RESERVED_297',
298: 'IMG_FMT_RESERVED_298',
299: 'IMG_FMT_RESERVED_299',
300: 'IMG_FMT_RESERVED_300',
301: 'IMG_FMT_RESERVED_301',
302: 'IMG_FMT_RESERVED_302',
303: 'IMG_FMT_RESERVED_303',
304: 'IMG_FMT_RESERVED_304',
305: 'IMG_FMT_RESERVED_305',
306: 'IMG_FMT_RESERVED_306',
307: 'IMG_FMT_RESERVED_307',
308: 'IMG_FMT_RESERVED_308',
309: 'IMG_FMT_RESERVED_309',
310: 'IMG_FMT_RESERVED_310',
311: 'IMG_FMT_RESERVED_311',
312: 'IMG_FMT_RESERVED_312',
313: 'IMG_FMT_RESERVED_313',
314: 'IMG_FMT_RESERVED_314',
315: 'IMG_FMT_RESERVED_315',
316: 'IMG_FMT_RESERVED_316',
317: 'IMG_FMT_RESERVED_317',
318: 'IMG_FMT_RESERVED_318',
319: 'IMG_FMT_RESERVED_319',
320: 'IMG_FMT_RESERVED_320',
321: 'IMG_FMT_RESERVED_321',
322: 'IMG_FMT_RESERVED_322',
323: 'IMG_FMT_RESERVED_323',
324: 'IMG_FMT_RESERVED_324',
325: 'IMG_FMT_RESERVED_325',
326: 'IMG_FMT_RESERVED_326',
327: 'IMG_FMT_RESERVED_327',
328: 'IMG_FMT_RESERVED_328',
329: 'IMG_FMT_RESERVED_329',
330: 'IMG_FMT_RESERVED_330',
331: 'IMG_FMT_RESERVED_331',
332: 'IMG_FMT_RESERVED_332',
333: 'IMG_FMT_RESERVED_333',
334: 'IMG_FMT_RESERVED_334',
335: 'IMG_FMT_RESERVED_335',
336: 'IMG_FMT_RESERVED_336',
337: 'IMG_FMT_RESERVED_337',
338: 'IMG_FMT_RESERVED_338',
339: 'IMG_FMT_RESERVED_339',
340: 'IMG_FMT_RESERVED_340',
341: 'IMG_FMT_RESERVED_341',
342: 'IMG_FMT_RESERVED_342',
343: 'IMG_FMT_RESERVED_343',
344: 'IMG_FMT_RESERVED_344',
345: 'IMG_FMT_RESERVED_345',
346: 'IMG_FMT_RESERVED_346',
347: 'IMG_FMT_RESERVED_347',
348: 'IMG_FMT_RESERVED_348',
349: 'IMG_FMT_RESERVED_349',
350: 'IMG_FMT_RESERVED_350',
351: 'IMG_FMT_RESERVED_351',
352: 'IMG_FMT_RESERVED_352',
353: 'IMG_FMT_RESERVED_353',
354: 'IMG_FMT_RESERVED_354',
355: 'IMG_FMT_RESERVED_355',
356: 'IMG_FMT_RESERVED_356',
357: 'IMG_FMT_RESERVED_357',
358: 'IMG_FMT_RESERVED_358',
359: 'IMG_FMT_RESERVED_359',
360: 'IMG_FMT_RESERVED_360',
361: 'IMG_FMT_RESERVED_361',
362: 'IMG_FMT_RESERVED_362',
363: 'IMG_FMT_RESERVED_363',
364: 'IMG_FMT_RESERVED_364',
365: 'IMG_FMT_RESERVED_365',
366: 'IMG_FMT_RESERVED_366',
367: 'IMG_FMT_RESERVED_367',
368: 'IMG_FMT_RESERVED_368',
369: 'IMG_FMT_RESERVED_369',
370: 'IMG_FMT_RESERVED_370',
371: 'IMG_FMT_RESERVED_371',
372: 'IMG_FMT_RESERVED_372',
373: 'IMG_FMT_RESERVED_373',
374: 'IMG_FMT_RESERVED_374',
375: 'IMG_FMT_RESERVED_375',
376: 'IMG_FMT_RESERVED_376',
377: 'IMG_FMT_RESERVED_377',
378: 'IMG_FMT_RESERVED_378',
379: 'IMG_FMT_RESERVED_379',
380: 'IMG_FMT_RESERVED_380',
381: 'IMG_FMT_RESERVED_381',
382: 'IMG_FMT_RESERVED_382',
383: 'IMG_FMT_RESERVED_383',
384: 'IMG_FMT_RESERVED_384',
385: 'IMG_FMT_RESERVED_385',
386: 'IMG_FMT_RESERVED_386',
387: 'IMG_FMT_RESERVED_387',
388: 'IMG_FMT_RESERVED_388',
389: 'IMG_FMT_RESERVED_389',
390: 'IMG_FMT_RESERVED_390',
391: 'IMG_FMT_RESERVED_391',
392: 'IMG_FMT_RESERVED_392',
393: 'IMG_FMT_RESERVED_393',
394: 'IMG_FMT_RESERVED_394',
395: 'IMG_FMT_RESERVED_395',
396: 'IMG_FMT_RESERVED_396',
397: 'IMG_FMT_RESERVED_397',
398: 'IMG_FMT_RESERVED_398',
399: 'IMG_FMT_RESERVED_399',
400: 'IMG_FMT_RESERVED_400',
401: 'IMG_FMT_RESERVED_401',
402: 'IMG_FMT_RESERVED_402',
403: 'IMG_FMT_RESERVED_403',
404: 'IMG_FMT_RESERVED_404',
405: 'IMG_FMT_RESERVED_405',
406: 'IMG_FMT_RESERVED_406',
407: 'IMG_FMT_RESERVED_407',
408: 'IMG_FMT_RESERVED_408',
409: 'IMG_FMT_RESERVED_409',
410: 'IMG_FMT_RESERVED_410',
411: 'IMG_FMT_RESERVED_411',
412: 'IMG_FMT_RESERVED_412',
413: 'IMG_FMT_RESERVED_413',
414: 'IMG_FMT_RESERVED_414',
415: 'IMG_FMT_RESERVED_415',
416: 'IMG_FMT_RESERVED_416',
417: 'IMG_FMT_RESERVED_417',
418: 'IMG_FMT_RESERVED_418',
419: 'IMG_FMT_RESERVED_419',
420: 'IMG_FMT_RESERVED_420',
421: 'IMG_FMT_RESERVED_421',
422: 'IMG_FMT_RESERVED_422',
423: 'IMG_FMT_RESERVED_423',
424: 'IMG_FMT_RESERVED_424',
425: 'IMG_FMT_RESERVED_425',
426: 'IMG_FMT_RESERVED_426',
427: 'IMG_FMT_RESERVED_427',
428: 'IMG_FMT_RESERVED_428',
429: 'IMG_FMT_RESERVED_429',
430: 'IMG_FMT_RESERVED_430',
431: 'IMG_FMT_RESERVED_431',
432: 'IMG_FMT_RESERVED_432',
433: 'IMG_FMT_RESERVED_433',
434: 'IMG_FMT_RESERVED_434',
435: 'IMG_FMT_RESERVED_435',
436: 'IMG_FMT_RESERVED_436',
437: 'IMG_FMT_RESERVED_437',
438: 'IMG_FMT_RESERVED_438',
439: 'IMG_FMT_RESERVED_439',
440: 'IMG_FMT_RESERVED_440',
441: 'IMG_FMT_RESERVED_441',
442: 'IMG_FMT_RESERVED_442',
443: 'IMG_FMT_RESERVED_443',
444: 'IMG_FMT_RESERVED_444',
445: 'IMG_FMT_RESERVED_445',
446: 'IMG_FMT_RESERVED_446',
447: 'IMG_FMT_RESERVED_447',
448: 'IMG_FMT_RESERVED_448',
449: 'IMG_FMT_RESERVED_449',
450: 'IMG_FMT_RESERVED_450',
451: 'IMG_FMT_RESERVED_451',
452: 'IMG_FMT_RESERVED_452',
453: 'IMG_FMT_RESERVED_453',
454: 'IMG_FMT_RESERVED_454',
455: 'IMG_FMT_RESERVED_455',
456: 'IMG_FMT_RESERVED_456',
457: 'IMG_FMT_RESERVED_457',
458: 'IMG_FMT_RESERVED_458',
459: 'IMG_FMT_RESERVED_459',
460: 'IMG_FMT_RESERVED_460',
461: 'IMG_FMT_RESERVED_461',
462: 'IMG_FMT_RESERVED_462',
463: 'IMG_FMT_RESERVED_463',
464: 'IMG_FMT_RESERVED_464',
465: 'IMG_FMT_RESERVED_465',
466: 'IMG_FMT_RESERVED_466',
467: 'IMG_FMT_RESERVED_467',
468: 'IMG_FMT_RESERVED_468',
469: 'IMG_FMT_RESERVED_469',
470: 'IMG_FMT_RESERVED_470',
471: 'IMG_FMT_RESERVED_471',
472: 'IMG_FMT_RESERVED_472',
473: 'IMG_FMT_RESERVED_473',
474: 'IMG_FMT_RESERVED_474',
475: 'IMG_FMT_RESERVED_475',
476: 'IMG_FMT_RESERVED_476',
477: 'IMG_FMT_RESERVED_477',
478: 'IMG_FMT_RESERVED_478',
479: 'IMG_FMT_RESERVED_479',
480: 'IMG_FMT_RESERVED_480',
481: 'IMG_FMT_RESERVED_481',
482: 'IMG_FMT_RESERVED_482',
483: 'IMG_FMT_RESERVED_483',
484: 'IMG_FMT_RESERVED_484',
485: 'IMG_FMT_RESERVED_485',
486: 'IMG_FMT_RESERVED_486',
487: 'IMG_FMT_RESERVED_487',
488: 'IMG_FMT_RESERVED_488',
489: 'IMG_FMT_RESERVED_489',
490: 'IMG_FMT_RESERVED_490',
491: 'IMG_FMT_RESERVED_491',
492: 'IMG_FMT_RESERVED_492',
493: 'IMG_FMT_RESERVED_493',
494: 'IMG_FMT_RESERVED_494',
495: 'IMG_FMT_RESERVED_495',
496: 'IMG_FMT_RESERVED_496',
497: 'IMG_FMT_RESERVED_497',
498: 'IMG_FMT_RESERVED_498',
499: 'IMG_FMT_RESERVED_499',
500: 'IMG_FMT_RESERVED_500',
501: 'IMG_FMT_RESERVED_501',
502: 'IMG_FMT_RESERVED_502',
503: 'IMG_FMT_RESERVED_503',
504: 'IMG_FMT_RESERVED_504',
505: 'IMG_FMT_RESERVED_505',
506: 'IMG_FMT_RESERVED_506',
507: 'IMG_FMT_RESERVED_507',
508: 'IMG_FMT_RESERVED_508',
509: 'IMG_FMT_RESERVED_509',
510: 'IMG_FMT_RESERVED_510',
511: 'IMG_FMT_RESERVED_511',
}
IMG_FMT_INVALID = 0
IMG_FMT_8_UNORM = 1
IMG_FMT_8_SNORM = 2
IMG_FMT_8_USCALED = 3
IMG_FMT_8_SSCALED = 4
IMG_FMT_8_UINT = 5
IMG_FMT_8_SINT = 6
IMG_FMT_16_UNORM = 7
IMG_FMT_16_SNORM = 8
IMG_FMT_16_USCALED = 9
IMG_FMT_16_SSCALED = 10
IMG_FMT_16_UINT = 11
IMG_FMT_16_SINT = 12
IMG_FMT_16_FLOAT = 13
IMG_FMT_8_8_UNORM = 14
IMG_FMT_8_8_SNORM = 15
IMG_FMT_8_8_USCALED = 16
IMG_FMT_8_8_SSCALED = 17
IMG_FMT_8_8_UINT = 18
IMG_FMT_8_8_SINT = 19
IMG_FMT_32_UINT = 20
IMG_FMT_32_SINT = 21
IMG_FMT_32_FLOAT = 22
IMG_FMT_16_16_UNORM = 23
IMG_FMT_16_16_SNORM = 24
IMG_FMT_16_16_USCALED = 25
IMG_FMT_16_16_SSCALED = 26
IMG_FMT_16_16_UINT = 27
IMG_FMT_16_16_SINT = 28
IMG_FMT_16_16_FLOAT = 29
IMG_FMT_10_11_11_UNORM = 30
IMG_FMT_10_11_11_SNORM = 31
IMG_FMT_10_11_11_USCALED = 32
IMG_FMT_10_11_11_SSCALED = 33
IMG_FMT_10_11_11_UINT = 34
IMG_FMT_10_11_11_SINT = 35
IMG_FMT_10_11_11_FLOAT = 36
IMG_FMT_11_11_10_UNORM = 37
IMG_FMT_11_11_10_SNORM = 38
IMG_FMT_11_11_10_USCALED = 39
IMG_FMT_11_11_10_SSCALED = 40
IMG_FMT_11_11_10_UINT = 41
IMG_FMT_11_11_10_SINT = 42
IMG_FMT_11_11_10_FLOAT = 43
IMG_FMT_10_10_10_2_UNORM = 44
IMG_FMT_10_10_10_2_SNORM = 45
IMG_FMT_10_10_10_2_USCALED = 46
IMG_FMT_10_10_10_2_SSCALED = 47
IMG_FMT_10_10_10_2_UINT = 48
IMG_FMT_10_10_10_2_SINT = 49
IMG_FMT_2_10_10_10_UNORM = 50
IMG_FMT_2_10_10_10_SNORM = 51
IMG_FMT_2_10_10_10_USCALED = 52
IMG_FMT_2_10_10_10_SSCALED = 53
IMG_FMT_2_10_10_10_UINT = 54
IMG_FMT_2_10_10_10_SINT = 55
IMG_FMT_8_8_8_8_UNORM = 56
IMG_FMT_8_8_8_8_SNORM = 57
IMG_FMT_8_8_8_8_USCALED = 58
IMG_FMT_8_8_8_8_SSCALED = 59
IMG_FMT_8_8_8_8_UINT = 60
IMG_FMT_8_8_8_8_SINT = 61
IMG_FMT_32_32_UINT = 62
IMG_FMT_32_32_SINT = 63
IMG_FMT_32_32_FLOAT = 64
IMG_FMT_16_16_16_16_UNORM = 65
IMG_FMT_16_16_16_16_SNORM = 66
IMG_FMT_16_16_16_16_USCALED = 67
IMG_FMT_16_16_16_16_SSCALED = 68
IMG_FMT_16_16_16_16_UINT = 69
IMG_FMT_16_16_16_16_SINT = 70
IMG_FMT_16_16_16_16_FLOAT = 71
IMG_FMT_32_32_32_UINT = 72
IMG_FMT_32_32_32_SINT = 73
IMG_FMT_32_32_32_FLOAT = 74
IMG_FMT_32_32_32_32_UINT = 75
IMG_FMT_32_32_32_32_SINT = 76
IMG_FMT_32_32_32_32_FLOAT = 77
IMG_FMT_RESERVED_78 = 78
IMG_FMT_RESERVED_79 = 79
IMG_FMT_RESERVED_80 = 80
IMG_FMT_RESERVED_81 = 81
IMG_FMT_RESERVED_82 = 82
IMG_FMT_RESERVED_83 = 83
IMG_FMT_RESERVED_84 = 84
IMG_FMT_RESERVED_85 = 85
IMG_FMT_RESERVED_86 = 86
IMG_FMT_RESERVED_87 = 87
IMG_FMT_RESERVED_88 = 88
IMG_FMT_RESERVED_89 = 89
IMG_FMT_RESERVED_90 = 90
IMG_FMT_RESERVED_91 = 91
IMG_FMT_RESERVED_92 = 92
IMG_FMT_RESERVED_93 = 93
IMG_FMT_RESERVED_94 = 94
IMG_FMT_RESERVED_95 = 95
IMG_FMT_RESERVED_96 = 96
IMG_FMT_RESERVED_97 = 97
IMG_FMT_RESERVED_98 = 98
IMG_FMT_RESERVED_99 = 99
IMG_FMT_RESERVED_100 = 100
IMG_FMT_RESERVED_101 = 101
IMG_FMT_RESERVED_102 = 102
IMG_FMT_RESERVED_103 = 103
IMG_FMT_RESERVED_104 = 104
IMG_FMT_RESERVED_105 = 105
IMG_FMT_RESERVED_106 = 106
IMG_FMT_RESERVED_107 = 107
IMG_FMT_RESERVED_108 = 108
IMG_FMT_RESERVED_109 = 109
IMG_FMT_RESERVED_110 = 110
IMG_FMT_RESERVED_111 = 111
IMG_FMT_RESERVED_112 = 112
IMG_FMT_RESERVED_113 = 113
IMG_FMT_RESERVED_114 = 114
IMG_FMT_RESERVED_115 = 115
IMG_FMT_RESERVED_116 = 116
IMG_FMT_RESERVED_117 = 117
IMG_FMT_RESERVED_118 = 118
IMG_FMT_RESERVED_119 = 119
IMG_FMT_RESERVED_120 = 120
IMG_FMT_RESERVED_121 = 121
IMG_FMT_RESERVED_122 = 122
IMG_FMT_RESERVED_123 = 123
IMG_FMT_RESERVED_124 = 124
IMG_FMT_RESERVED_125 = 125
IMG_FMT_RESERVED_126 = 126
IMG_FMT_RESERVED_127 = 127
IMG_FMT_8_SRGB = 128
IMG_FMT_8_8_SRGB = 129
IMG_FMT_8_8_8_8_SRGB = 130
IMG_FMT_6E4_FLOAT = 131
IMG_FMT_5_9_9_9_FLOAT = 132
IMG_FMT_5_6_5_UNORM = 133
IMG_FMT_1_5_5_5_UNORM = 134
IMG_FMT_5_5_5_1_UNORM = 135
IMG_FMT_4_4_4_4_UNORM = 136
IMG_FMT_4_4_UNORM = 137
IMG_FMT_1_UNORM = 138
IMG_FMT_1_REVERSED_UNORM = 139
IMG_FMT_32_FLOAT_CLAMP = 140
IMG_FMT_8_24_UNORM = 141
IMG_FMT_8_24_UINT = 142
IMG_FMT_24_8_UNORM = 143
IMG_FMT_24_8_UINT = 144
IMG_FMT_X24_8_32_UINT = 145
IMG_FMT_X24_8_32_FLOAT = 146
IMG_FMT_GB_GR_UNORM = 147
IMG_FMT_GB_GR_SNORM = 148
IMG_FMT_GB_GR_UINT = 149
IMG_FMT_GB_GR_SRGB = 150
IMG_FMT_BG_RG_UNORM = 151
IMG_FMT_BG_RG_SNORM = 152
IMG_FMT_BG_RG_UINT = 153
IMG_FMT_BG_RG_SRGB = 154
IMG_FMT_RESERVED_155 = 155
IMG_FMT_FMASK8_S2_F1 = 156
IMG_FMT_FMASK8_S4_F1 = 157
IMG_FMT_FMASK8_S8_F1 = 158
IMG_FMT_FMASK8_S2_F2 = 159
IMG_FMT_FMASK8_S4_F2 = 160
IMG_FMT_FMASK8_S4_F4 = 161
IMG_FMT_FMASK16_S16_F1 = 162
IMG_FMT_FMASK16_S8_F2 = 163
IMG_FMT_FMASK32_S16_F2 = 164
IMG_FMT_FMASK32_S8_F4 = 165
IMG_FMT_FMASK32_S8_F8 = 166
IMG_FMT_FMASK64_S16_F4 = 167
IMG_FMT_FMASK64_S16_F8 = 168
IMG_FMT_BC1_UNORM = 169
IMG_FMT_BC1_SRGB = 170
IMG_FMT_BC2_UNORM = 171
IMG_FMT_BC2_SRGB = 172
IMG_FMT_BC3_UNORM = 173
IMG_FMT_BC3_SRGB = 174
IMG_FMT_BC4_UNORM = 175
IMG_FMT_BC4_SNORM = 176
IMG_FMT_BC5_UNORM = 177
IMG_FMT_BC5_SNORM = 178
IMG_FMT_BC6_UFLOAT = 179
IMG_FMT_BC6_SFLOAT = 180
IMG_FMT_BC7_UNORM = 181
IMG_FMT_BC7_SRGB = 182
IMG_FMT_MM_8_UNORM = 265
IMG_FMT_MM_8_UINT = 266
IMG_FMT_MM_8_8_UNORM = 267
IMG_FMT_MM_8_8_UINT = 268
IMG_FMT_MM_8_8_8_8_UNORM = 269
IMG_FMT_MM_8_8_8_8_UINT = 270
IMG_FMT_MM_VYUY8_UNORM = 271
IMG_FMT_MM_VYUY8_UINT = 272
IMG_FMT_MM_10_11_11_UNORM = 273
IMG_FMT_MM_10_11_11_UINT = 274
IMG_FMT_MM_2_10_10_10_UNORM = 275
IMG_FMT_MM_2_10_10_10_UINT = 276
IMG_FMT_MM_16_16_16_16_UNORM = 277
IMG_FMT_MM_16_16_16_16_UINT = 278
IMG_FMT_MM_10_IN_16_UNORM = 279
IMG_FMT_MM_10_IN_16_UINT = 280
IMG_FMT_MM_10_IN_16_16_UNORM = 281
IMG_FMT_MM_10_IN_16_16_UINT = 282
IMG_FMT_MM_10_IN_16_16_16_16_UNORM = 283
IMG_FMT_MM_10_IN_16_16_16_16_UINT = 284
IMG_FMT_RESERVED_285 = 285
IMG_FMT_RESERVED_286 = 286
IMG_FMT_RESERVED_287 = 287
IMG_FMT_RESERVED_288 = 288
IMG_FMT_RESERVED_289 = 289
IMG_FMT_RESERVED_290 = 290
IMG_FMT_RESERVED_291 = 291
IMG_FMT_RESERVED_292 = 292
IMG_FMT_RESERVED_293 = 293
IMG_FMT_RESERVED_294 = 294
IMG_FMT_RESERVED_295 = 295
IMG_FMT_RESERVED_296 = 296
IMG_FMT_RESERVED_297 = 297
IMG_FMT_RESERVED_298 = 298
IMG_FMT_RESERVED_299 = 299
IMG_FMT_RESERVED_300 = 300
IMG_FMT_RESERVED_301 = 301
IMG_FMT_RESERVED_302 = 302
IMG_FMT_RESERVED_303 = 303
IMG_FMT_RESERVED_304 = 304
IMG_FMT_RESERVED_305 = 305
IMG_FMT_RESERVED_306 = 306
IMG_FMT_RESERVED_307 = 307
IMG_FMT_RESERVED_308 = 308
IMG_FMT_RESERVED_309 = 309
IMG_FMT_RESERVED_310 = 310
IMG_FMT_RESERVED_311 = 311
IMG_FMT_RESERVED_312 = 312
IMG_FMT_RESERVED_313 = 313
IMG_FMT_RESERVED_314 = 314
IMG_FMT_RESERVED_315 = 315
IMG_FMT_RESERVED_316 = 316
IMG_FMT_RESERVED_317 = 317
IMG_FMT_RESERVED_318 = 318
IMG_FMT_RESERVED_319 = 319
IMG_FMT_RESERVED_320 = 320
IMG_FMT_RESERVED_321 = 321
IMG_FMT_RESERVED_322 = 322
IMG_FMT_RESERVED_323 = 323
IMG_FMT_RESERVED_324 = 324
IMG_FMT_RESERVED_325 = 325
IMG_FMT_RESERVED_326 = 326
IMG_FMT_RESERVED_327 = 327
IMG_FMT_RESERVED_328 = 328
IMG_FMT_RESERVED_329 = 329
IMG_FMT_RESERVED_330 = 330
IMG_FMT_RESERVED_331 = 331
IMG_FMT_RESERVED_332 = 332
IMG_FMT_RESERVED_333 = 333
IMG_FMT_RESERVED_334 = 334
IMG_FMT_RESERVED_335 = 335
IMG_FMT_RESERVED_336 = 336
IMG_FMT_RESERVED_337 = 337
IMG_FMT_RESERVED_338 = 338
IMG_FMT_RESERVED_339 = 339
IMG_FMT_RESERVED_340 = 340
IMG_FMT_RESERVED_341 = 341
IMG_FMT_RESERVED_342 = 342
IMG_FMT_RESERVED_343 = 343
IMG_FMT_RESERVED_344 = 344
IMG_FMT_RESERVED_345 = 345
IMG_FMT_RESERVED_346 = 346
IMG_FMT_RESERVED_347 = 347
IMG_FMT_RESERVED_348 = 348
IMG_FMT_RESERVED_349 = 349
IMG_FMT_RESERVED_350 = 350
IMG_FMT_RESERVED_351 = 351
IMG_FMT_RESERVED_352 = 352
IMG_FMT_RESERVED_353 = 353
IMG_FMT_RESERVED_354 = 354
IMG_FMT_RESERVED_355 = 355
IMG_FMT_RESERVED_356 = 356
IMG_FMT_RESERVED_357 = 357
IMG_FMT_RESERVED_358 = 358
IMG_FMT_RESERVED_359 = 359
IMG_FMT_RESERVED_360 = 360
IMG_FMT_RESERVED_361 = 361
IMG_FMT_RESERVED_362 = 362
IMG_FMT_RESERVED_363 = 363
IMG_FMT_RESERVED_364 = 364
IMG_FMT_RESERVED_365 = 365
IMG_FMT_RESERVED_366 = 366
IMG_FMT_RESERVED_367 = 367
IMG_FMT_RESERVED_368 = 368
IMG_FMT_RESERVED_369 = 369
IMG_FMT_RESERVED_370 = 370
IMG_FMT_RESERVED_371 = 371
IMG_FMT_RESERVED_372 = 372
IMG_FMT_RESERVED_373 = 373
IMG_FMT_RESERVED_374 = 374
IMG_FMT_RESERVED_375 = 375
IMG_FMT_RESERVED_376 = 376
IMG_FMT_RESERVED_377 = 377
IMG_FMT_RESERVED_378 = 378
IMG_FMT_RESERVED_379 = 379
IMG_FMT_RESERVED_380 = 380
IMG_FMT_RESERVED_381 = 381
IMG_FMT_RESERVED_382 = 382
IMG_FMT_RESERVED_383 = 383
IMG_FMT_RESERVED_384 = 384
IMG_FMT_RESERVED_385 = 385
IMG_FMT_RESERVED_386 = 386
IMG_FMT_RESERVED_387 = 387
IMG_FMT_RESERVED_388 = 388
IMG_FMT_RESERVED_389 = 389
IMG_FMT_RESERVED_390 = 390
IMG_FMT_RESERVED_391 = 391
IMG_FMT_RESERVED_392 = 392
IMG_FMT_RESERVED_393 = 393
IMG_FMT_RESERVED_394 = 394
IMG_FMT_RESERVED_395 = 395
IMG_FMT_RESERVED_396 = 396
IMG_FMT_RESERVED_397 = 397
IMG_FMT_RESERVED_398 = 398
IMG_FMT_RESERVED_399 = 399
IMG_FMT_RESERVED_400 = 400
IMG_FMT_RESERVED_401 = 401
IMG_FMT_RESERVED_402 = 402
IMG_FMT_RESERVED_403 = 403
IMG_FMT_RESERVED_404 = 404
IMG_FMT_RESERVED_405 = 405
IMG_FMT_RESERVED_406 = 406
IMG_FMT_RESERVED_407 = 407
IMG_FMT_RESERVED_408 = 408
IMG_FMT_RESERVED_409 = 409
IMG_FMT_RESERVED_410 = 410
IMG_FMT_RESERVED_411 = 411
IMG_FMT_RESERVED_412 = 412
IMG_FMT_RESERVED_413 = 413
IMG_FMT_RESERVED_414 = 414
IMG_FMT_RESERVED_415 = 415
IMG_FMT_RESERVED_416 = 416
IMG_FMT_RESERVED_417 = 417
IMG_FMT_RESERVED_418 = 418
IMG_FMT_RESERVED_419 = 419
IMG_FMT_RESERVED_420 = 420
IMG_FMT_RESERVED_421 = 421
IMG_FMT_RESERVED_422 = 422
IMG_FMT_RESERVED_423 = 423
IMG_FMT_RESERVED_424 = 424
IMG_FMT_RESERVED_425 = 425
IMG_FMT_RESERVED_426 = 426
IMG_FMT_RESERVED_427 = 427
IMG_FMT_RESERVED_428 = 428
IMG_FMT_RESERVED_429 = 429
IMG_FMT_RESERVED_430 = 430
IMG_FMT_RESERVED_431 = 431
IMG_FMT_RESERVED_432 = 432
IMG_FMT_RESERVED_433 = 433
IMG_FMT_RESERVED_434 = 434
IMG_FMT_RESERVED_435 = 435
IMG_FMT_RESERVED_436 = 436
IMG_FMT_RESERVED_437 = 437
IMG_FMT_RESERVED_438 = 438
IMG_FMT_RESERVED_439 = 439
IMG_FMT_RESERVED_440 = 440
IMG_FMT_RESERVED_441 = 441
IMG_FMT_RESERVED_442 = 442
IMG_FMT_RESERVED_443 = 443
IMG_FMT_RESERVED_444 = 444
IMG_FMT_RESERVED_445 = 445
IMG_FMT_RESERVED_446 = 446
IMG_FMT_RESERVED_447 = 447
IMG_FMT_RESERVED_448 = 448
IMG_FMT_RESERVED_449 = 449
IMG_FMT_RESERVED_450 = 450
IMG_FMT_RESERVED_451 = 451
IMG_FMT_RESERVED_452 = 452
IMG_FMT_RESERVED_453 = 453
IMG_FMT_RESERVED_454 = 454
IMG_FMT_RESERVED_455 = 455
IMG_FMT_RESERVED_456 = 456
IMG_FMT_RESERVED_457 = 457
IMG_FMT_RESERVED_458 = 458
IMG_FMT_RESERVED_459 = 459
IMG_FMT_RESERVED_460 = 460
IMG_FMT_RESERVED_461 = 461
IMG_FMT_RESERVED_462 = 462
IMG_FMT_RESERVED_463 = 463
IMG_FMT_RESERVED_464 = 464
IMG_FMT_RESERVED_465 = 465
IMG_FMT_RESERVED_466 = 466
IMG_FMT_RESERVED_467 = 467
IMG_FMT_RESERVED_468 = 468
IMG_FMT_RESERVED_469 = 469
IMG_FMT_RESERVED_470 = 470
IMG_FMT_RESERVED_471 = 471
IMG_FMT_RESERVED_472 = 472
IMG_FMT_RESERVED_473 = 473
IMG_FMT_RESERVED_474 = 474
IMG_FMT_RESERVED_475 = 475
IMG_FMT_RESERVED_476 = 476
IMG_FMT_RESERVED_477 = 477
IMG_FMT_RESERVED_478 = 478
IMG_FMT_RESERVED_479 = 479
IMG_FMT_RESERVED_480 = 480
IMG_FMT_RESERVED_481 = 481
IMG_FMT_RESERVED_482 = 482
IMG_FMT_RESERVED_483 = 483
IMG_FMT_RESERVED_484 = 484
IMG_FMT_RESERVED_485 = 485
IMG_FMT_RESERVED_486 = 486
IMG_FMT_RESERVED_487 = 487
IMG_FMT_RESERVED_488 = 488
IMG_FMT_RESERVED_489 = 489
IMG_FMT_RESERVED_490 = 490
IMG_FMT_RESERVED_491 = 491
IMG_FMT_RESERVED_492 = 492
IMG_FMT_RESERVED_493 = 493
IMG_FMT_RESERVED_494 = 494
IMG_FMT_RESERVED_495 = 495
IMG_FMT_RESERVED_496 = 496
IMG_FMT_RESERVED_497 = 497
IMG_FMT_RESERVED_498 = 498
IMG_FMT_RESERVED_499 = 499
IMG_FMT_RESERVED_500 = 500
IMG_FMT_RESERVED_501 = 501
IMG_FMT_RESERVED_502 = 502
IMG_FMT_RESERVED_503 = 503
IMG_FMT_RESERVED_504 = 504
IMG_FMT_RESERVED_505 = 505
IMG_FMT_RESERVED_506 = 506
IMG_FMT_RESERVED_507 = 507
IMG_FMT_RESERVED_508 = 508
IMG_FMT_RESERVED_509 = 509
IMG_FMT_RESERVED_510 = 510
IMG_FMT_RESERVED_511 = 511
IMG_FMT = ctypes.c_uint32 # enum
# values for enumeration 'BUF_DATA_FORMAT'
BUF_DATA_FORMAT__enumvalues = {
0: 'BUF_DATA_FORMAT_INVALID',
1: 'BUF_DATA_FORMAT_8',
2: 'BUF_DATA_FORMAT_16',
3: 'BUF_DATA_FORMAT_8_8',
4: 'BUF_DATA_FORMAT_32',
5: 'BUF_DATA_FORMAT_16_16',
6: 'BUF_DATA_FORMAT_10_11_11',
7: 'BUF_DATA_FORMAT_11_11_10',
8: 'BUF_DATA_FORMAT_10_10_10_2',
9: 'BUF_DATA_FORMAT_2_10_10_10',
10: 'BUF_DATA_FORMAT_8_8_8_8',
11: 'BUF_DATA_FORMAT_32_32',
12: 'BUF_DATA_FORMAT_16_16_16_16',
13: 'BUF_DATA_FORMAT_32_32_32',
14: 'BUF_DATA_FORMAT_32_32_32_32',
15: 'BUF_DATA_FORMAT_RESERVED_15',
}
BUF_DATA_FORMAT_INVALID = 0
BUF_DATA_FORMAT_8 = 1
BUF_DATA_FORMAT_16 = 2
BUF_DATA_FORMAT_8_8 = 3
BUF_DATA_FORMAT_32 = 4
BUF_DATA_FORMAT_16_16 = 5
BUF_DATA_FORMAT_10_11_11 = 6
BUF_DATA_FORMAT_11_11_10 = 7
BUF_DATA_FORMAT_10_10_10_2 = 8
BUF_DATA_FORMAT_2_10_10_10 = 9
BUF_DATA_FORMAT_8_8_8_8 = 10
BUF_DATA_FORMAT_32_32 = 11
BUF_DATA_FORMAT_16_16_16_16 = 12
BUF_DATA_FORMAT_32_32_32 = 13
BUF_DATA_FORMAT_32_32_32_32 = 14
BUF_DATA_FORMAT_RESERVED_15 = 15
BUF_DATA_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'IMG_DATA_FORMAT'
IMG_DATA_FORMAT__enumvalues = {
0: 'IMG_DATA_FORMAT_INVALID',
1: 'IMG_DATA_FORMAT_8',
2: 'IMG_DATA_FORMAT_16',
3: 'IMG_DATA_FORMAT_8_8',
4: 'IMG_DATA_FORMAT_32',
5: 'IMG_DATA_FORMAT_16_16',
6: 'IMG_DATA_FORMAT_10_11_11',
7: 'IMG_DATA_FORMAT_11_11_10',
8: 'IMG_DATA_FORMAT_10_10_10_2',
9: 'IMG_DATA_FORMAT_2_10_10_10',
10: 'IMG_DATA_FORMAT_8_8_8_8',
11: 'IMG_DATA_FORMAT_32_32',
12: 'IMG_DATA_FORMAT_16_16_16_16',
13: 'IMG_DATA_FORMAT_32_32_32',
14: 'IMG_DATA_FORMAT_32_32_32_32',
15: 'IMG_DATA_FORMAT_RESERVED_15',
16: 'IMG_DATA_FORMAT_5_6_5',
17: 'IMG_DATA_FORMAT_1_5_5_5',
18: 'IMG_DATA_FORMAT_5_5_5_1',
19: 'IMG_DATA_FORMAT_4_4_4_4',
20: 'IMG_DATA_FORMAT_8_24',
21: 'IMG_DATA_FORMAT_24_8',
22: 'IMG_DATA_FORMAT_X24_8_32',
23: 'IMG_DATA_FORMAT_RESERVED_23',
24: 'IMG_DATA_FORMAT_RESERVED_24',
25: 'IMG_DATA_FORMAT_RESERVED_25',
26: 'IMG_DATA_FORMAT_RESERVED_26',
27: 'IMG_DATA_FORMAT_RESERVED_27',
28: 'IMG_DATA_FORMAT_RESERVED_28',
29: 'IMG_DATA_FORMAT_RESERVED_29',
30: 'IMG_DATA_FORMAT_RESERVED_30',
31: 'IMG_DATA_FORMAT_6E4',
32: 'IMG_DATA_FORMAT_GB_GR',
33: 'IMG_DATA_FORMAT_BG_RG',
34: 'IMG_DATA_FORMAT_5_9_9_9',
35: 'IMG_DATA_FORMAT_BC1',
36: 'IMG_DATA_FORMAT_BC2',
37: 'IMG_DATA_FORMAT_BC3',
38: 'IMG_DATA_FORMAT_BC4',
39: 'IMG_DATA_FORMAT_BC5',
40: 'IMG_DATA_FORMAT_BC6',
41: 'IMG_DATA_FORMAT_BC7',
42: 'IMG_DATA_FORMAT_RESERVED_42',
43: 'IMG_DATA_FORMAT_RESERVED_43',
44: 'IMG_DATA_FORMAT_FMASK8_S2_F1',
45: 'IMG_DATA_FORMAT_FMASK8_S4_F1',
46: 'IMG_DATA_FORMAT_FMASK8_S8_F1',
47: 'IMG_DATA_FORMAT_FMASK8_S2_F2',
48: 'IMG_DATA_FORMAT_FMASK8_S4_F2',
49: 'IMG_DATA_FORMAT_FMASK8_S4_F4',
50: 'IMG_DATA_FORMAT_FMASK16_S16_F1',
51: 'IMG_DATA_FORMAT_FMASK16_S8_F2',
52: 'IMG_DATA_FORMAT_FMASK32_S16_F2',
53: 'IMG_DATA_FORMAT_FMASK32_S8_F4',
54: 'IMG_DATA_FORMAT_FMASK32_S8_F8',
55: 'IMG_DATA_FORMAT_FMASK64_S16_F4',
56: 'IMG_DATA_FORMAT_FMASK64_S16_F8',
57: 'IMG_DATA_FORMAT_4_4',
58: 'IMG_DATA_FORMAT_6_5_5',
59: 'IMG_DATA_FORMAT_1',
60: 'IMG_DATA_FORMAT_1_REVERSED',
61: 'IMG_DATA_FORMAT_RESERVED_61',
62: 'IMG_DATA_FORMAT_RESERVED_62',
63: 'IMG_DATA_FORMAT_32_AS_32_32_32_32',
75: 'IMG_DATA_FORMAT_RESERVED_75',
76: 'IMG_DATA_FORMAT_MM_8',
77: 'IMG_DATA_FORMAT_MM_8_8',
78: 'IMG_DATA_FORMAT_MM_8_8_8_8',
79: 'IMG_DATA_FORMAT_MM_VYUY8',
80: 'IMG_DATA_FORMAT_MM_10_11_11',
81: 'IMG_DATA_FORMAT_MM_2_10_10_10',
82: 'IMG_DATA_FORMAT_MM_16_16_16_16',
83: 'IMG_DATA_FORMAT_MM_10_IN_16',
84: 'IMG_DATA_FORMAT_MM_10_IN_16_16',
85: 'IMG_DATA_FORMAT_MM_10_IN_16_16_16_16',
86: 'IMG_DATA_FORMAT_RESERVED_86',
87: 'IMG_DATA_FORMAT_RESERVED_87',
88: 'IMG_DATA_FORMAT_RESERVED_88',
89: 'IMG_DATA_FORMAT_RESERVED_89',
90: 'IMG_DATA_FORMAT_RESERVED_90',
91: 'IMG_DATA_FORMAT_RESERVED_91',
92: 'IMG_DATA_FORMAT_RESERVED_92',
93: 'IMG_DATA_FORMAT_RESERVED_93',
94: 'IMG_DATA_FORMAT_RESERVED_94',
95: 'IMG_DATA_FORMAT_RESERVED_95',
96: 'IMG_DATA_FORMAT_RESERVED_96',
97: 'IMG_DATA_FORMAT_RESERVED_97',
98: 'IMG_DATA_FORMAT_RESERVED_98',
99: 'IMG_DATA_FORMAT_RESERVED_99',
100: 'IMG_DATA_FORMAT_RESERVED_100',
101: 'IMG_DATA_FORMAT_RESERVED_101',
102: 'IMG_DATA_FORMAT_RESERVED_102',
103: 'IMG_DATA_FORMAT_RESERVED_103',
104: 'IMG_DATA_FORMAT_RESERVED_104',
105: 'IMG_DATA_FORMAT_RESERVED_105',
106: 'IMG_DATA_FORMAT_RESERVED_106',
107: 'IMG_DATA_FORMAT_RESERVED_107',
108: 'IMG_DATA_FORMAT_RESERVED_108',
109: 'IMG_DATA_FORMAT_RESERVED_109',
110: 'IMG_DATA_FORMAT_RESERVED_110',
111: 'IMG_DATA_FORMAT_RESERVED_111',
112: 'IMG_DATA_FORMAT_RESERVED_112',
113: 'IMG_DATA_FORMAT_RESERVED_113',
114: 'IMG_DATA_FORMAT_RESERVED_114',
115: 'IMG_DATA_FORMAT_RESERVED_115',
116: 'IMG_DATA_FORMAT_RESERVED_116',
117: 'IMG_DATA_FORMAT_RESERVED_117',
118: 'IMG_DATA_FORMAT_RESERVED_118',
119: 'IMG_DATA_FORMAT_RESERVED_119',
120: 'IMG_DATA_FORMAT_RESERVED_120',
121: 'IMG_DATA_FORMAT_RESERVED_121',
122: 'IMG_DATA_FORMAT_RESERVED_122',
123: 'IMG_DATA_FORMAT_RESERVED_123',
124: 'IMG_DATA_FORMAT_RESERVED_124',
125: 'IMG_DATA_FORMAT_RESERVED_125',
126: 'IMG_DATA_FORMAT_RESERVED_126',
127: 'IMG_DATA_FORMAT_RESERVED_127',
}
IMG_DATA_FORMAT_INVALID = 0
IMG_DATA_FORMAT_8 = 1
IMG_DATA_FORMAT_16 = 2
IMG_DATA_FORMAT_8_8 = 3
IMG_DATA_FORMAT_32 = 4
IMG_DATA_FORMAT_16_16 = 5
IMG_DATA_FORMAT_10_11_11 = 6
IMG_DATA_FORMAT_11_11_10 = 7
IMG_DATA_FORMAT_10_10_10_2 = 8
IMG_DATA_FORMAT_2_10_10_10 = 9
IMG_DATA_FORMAT_8_8_8_8 = 10
IMG_DATA_FORMAT_32_32 = 11
IMG_DATA_FORMAT_16_16_16_16 = 12
IMG_DATA_FORMAT_32_32_32 = 13
IMG_DATA_FORMAT_32_32_32_32 = 14
IMG_DATA_FORMAT_RESERVED_15 = 15
IMG_DATA_FORMAT_5_6_5 = 16
IMG_DATA_FORMAT_1_5_5_5 = 17
IMG_DATA_FORMAT_5_5_5_1 = 18
IMG_DATA_FORMAT_4_4_4_4 = 19
IMG_DATA_FORMAT_8_24 = 20
IMG_DATA_FORMAT_24_8 = 21
IMG_DATA_FORMAT_X24_8_32 = 22
IMG_DATA_FORMAT_RESERVED_23 = 23
IMG_DATA_FORMAT_RESERVED_24 = 24
IMG_DATA_FORMAT_RESERVED_25 = 25
IMG_DATA_FORMAT_RESERVED_26 = 26
IMG_DATA_FORMAT_RESERVED_27 = 27
IMG_DATA_FORMAT_RESERVED_28 = 28
IMG_DATA_FORMAT_RESERVED_29 = 29
IMG_DATA_FORMAT_RESERVED_30 = 30
IMG_DATA_FORMAT_6E4 = 31
IMG_DATA_FORMAT_GB_GR = 32
IMG_DATA_FORMAT_BG_RG = 33
IMG_DATA_FORMAT_5_9_9_9 = 34
IMG_DATA_FORMAT_BC1 = 35
IMG_DATA_FORMAT_BC2 = 36
IMG_DATA_FORMAT_BC3 = 37
IMG_DATA_FORMAT_BC4 = 38
IMG_DATA_FORMAT_BC5 = 39
IMG_DATA_FORMAT_BC6 = 40
IMG_DATA_FORMAT_BC7 = 41
IMG_DATA_FORMAT_RESERVED_42 = 42
IMG_DATA_FORMAT_RESERVED_43 = 43
IMG_DATA_FORMAT_FMASK8_S2_F1 = 44
IMG_DATA_FORMAT_FMASK8_S4_F1 = 45
IMG_DATA_FORMAT_FMASK8_S8_F1 = 46
IMG_DATA_FORMAT_FMASK8_S2_F2 = 47
IMG_DATA_FORMAT_FMASK8_S4_F2 = 48
IMG_DATA_FORMAT_FMASK8_S4_F4 = 49
IMG_DATA_FORMAT_FMASK16_S16_F1 = 50
IMG_DATA_FORMAT_FMASK16_S8_F2 = 51
IMG_DATA_FORMAT_FMASK32_S16_F2 = 52
IMG_DATA_FORMAT_FMASK32_S8_F4 = 53
IMG_DATA_FORMAT_FMASK32_S8_F8 = 54
IMG_DATA_FORMAT_FMASK64_S16_F4 = 55
IMG_DATA_FORMAT_FMASK64_S16_F8 = 56
IMG_DATA_FORMAT_4_4 = 57
IMG_DATA_FORMAT_6_5_5 = 58
IMG_DATA_FORMAT_1 = 59
IMG_DATA_FORMAT_1_REVERSED = 60
IMG_DATA_FORMAT_RESERVED_61 = 61
IMG_DATA_FORMAT_RESERVED_62 = 62
IMG_DATA_FORMAT_32_AS_32_32_32_32 = 63
IMG_DATA_FORMAT_RESERVED_75 = 75
IMG_DATA_FORMAT_MM_8 = 76
IMG_DATA_FORMAT_MM_8_8 = 77
IMG_DATA_FORMAT_MM_8_8_8_8 = 78
IMG_DATA_FORMAT_MM_VYUY8 = 79
IMG_DATA_FORMAT_MM_10_11_11 = 80
IMG_DATA_FORMAT_MM_2_10_10_10 = 81
IMG_DATA_FORMAT_MM_16_16_16_16 = 82
IMG_DATA_FORMAT_MM_10_IN_16 = 83
IMG_DATA_FORMAT_MM_10_IN_16_16 = 84
IMG_DATA_FORMAT_MM_10_IN_16_16_16_16 = 85
IMG_DATA_FORMAT_RESERVED_86 = 86
IMG_DATA_FORMAT_RESERVED_87 = 87
IMG_DATA_FORMAT_RESERVED_88 = 88
IMG_DATA_FORMAT_RESERVED_89 = 89
IMG_DATA_FORMAT_RESERVED_90 = 90
IMG_DATA_FORMAT_RESERVED_91 = 91
IMG_DATA_FORMAT_RESERVED_92 = 92
IMG_DATA_FORMAT_RESERVED_93 = 93
IMG_DATA_FORMAT_RESERVED_94 = 94
IMG_DATA_FORMAT_RESERVED_95 = 95
IMG_DATA_FORMAT_RESERVED_96 = 96
IMG_DATA_FORMAT_RESERVED_97 = 97
IMG_DATA_FORMAT_RESERVED_98 = 98
IMG_DATA_FORMAT_RESERVED_99 = 99
IMG_DATA_FORMAT_RESERVED_100 = 100
IMG_DATA_FORMAT_RESERVED_101 = 101
IMG_DATA_FORMAT_RESERVED_102 = 102
IMG_DATA_FORMAT_RESERVED_103 = 103
IMG_DATA_FORMAT_RESERVED_104 = 104
IMG_DATA_FORMAT_RESERVED_105 = 105
IMG_DATA_FORMAT_RESERVED_106 = 106
IMG_DATA_FORMAT_RESERVED_107 = 107
IMG_DATA_FORMAT_RESERVED_108 = 108
IMG_DATA_FORMAT_RESERVED_109 = 109
IMG_DATA_FORMAT_RESERVED_110 = 110
IMG_DATA_FORMAT_RESERVED_111 = 111
IMG_DATA_FORMAT_RESERVED_112 = 112
IMG_DATA_FORMAT_RESERVED_113 = 113
IMG_DATA_FORMAT_RESERVED_114 = 114
IMG_DATA_FORMAT_RESERVED_115 = 115
IMG_DATA_FORMAT_RESERVED_116 = 116
IMG_DATA_FORMAT_RESERVED_117 = 117
IMG_DATA_FORMAT_RESERVED_118 = 118
IMG_DATA_FORMAT_RESERVED_119 = 119
IMG_DATA_FORMAT_RESERVED_120 = 120
IMG_DATA_FORMAT_RESERVED_121 = 121
IMG_DATA_FORMAT_RESERVED_122 = 122
IMG_DATA_FORMAT_RESERVED_123 = 123
IMG_DATA_FORMAT_RESERVED_124 = 124
IMG_DATA_FORMAT_RESERVED_125 = 125
IMG_DATA_FORMAT_RESERVED_126 = 126
IMG_DATA_FORMAT_RESERVED_127 = 127
IMG_DATA_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'BUF_NUM_FORMAT'
BUF_NUM_FORMAT__enumvalues = {
0: 'BUF_NUM_FORMAT_UNORM',
1: 'BUF_NUM_FORMAT_SNORM',
2: 'BUF_NUM_FORMAT_USCALED',
3: 'BUF_NUM_FORMAT_SSCALED',
4: 'BUF_NUM_FORMAT_UINT',
5: 'BUF_NUM_FORMAT_SINT',
6: 'BUF_NUM_FORMAT_SNORM_NZ',
7: 'BUF_NUM_FORMAT_FLOAT',
}
BUF_NUM_FORMAT_UNORM = 0
BUF_NUM_FORMAT_SNORM = 1
BUF_NUM_FORMAT_USCALED = 2
BUF_NUM_FORMAT_SSCALED = 3
BUF_NUM_FORMAT_UINT = 4
BUF_NUM_FORMAT_SINT = 5
BUF_NUM_FORMAT_SNORM_NZ = 6
BUF_NUM_FORMAT_FLOAT = 7
BUF_NUM_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'IMG_NUM_FORMAT'
IMG_NUM_FORMAT__enumvalues = {
0: 'IMG_NUM_FORMAT_UNORM',
1: 'IMG_NUM_FORMAT_SNORM',
2: 'IMG_NUM_FORMAT_USCALED',
3: 'IMG_NUM_FORMAT_SSCALED',
4: 'IMG_NUM_FORMAT_UINT',
5: 'IMG_NUM_FORMAT_SINT',
6: 'IMG_NUM_FORMAT_SNORM_NZ',
7: 'IMG_NUM_FORMAT_FLOAT',
8: 'IMG_NUM_FORMAT_RESERVED_8',
9: 'IMG_NUM_FORMAT_SRGB',
10: 'IMG_NUM_FORMAT_UBNORM',
11: 'IMG_NUM_FORMAT_UBNORM_NZ',
12: 'IMG_NUM_FORMAT_UBINT',
13: 'IMG_NUM_FORMAT_UBSCALED',
14: 'IMG_NUM_FORMAT_RESERVED_14',
15: 'IMG_NUM_FORMAT_RESERVED_15',
}
IMG_NUM_FORMAT_UNORM = 0
IMG_NUM_FORMAT_SNORM = 1
IMG_NUM_FORMAT_USCALED = 2
IMG_NUM_FORMAT_SSCALED = 3
IMG_NUM_FORMAT_UINT = 4
IMG_NUM_FORMAT_SINT = 5
IMG_NUM_FORMAT_SNORM_NZ = 6
IMG_NUM_FORMAT_FLOAT = 7
IMG_NUM_FORMAT_RESERVED_8 = 8
IMG_NUM_FORMAT_SRGB = 9
IMG_NUM_FORMAT_UBNORM = 10
IMG_NUM_FORMAT_UBNORM_NZ = 11
IMG_NUM_FORMAT_UBINT = 12
IMG_NUM_FORMAT_UBSCALED = 13
IMG_NUM_FORMAT_RESERVED_14 = 14
IMG_NUM_FORMAT_RESERVED_15 = 15
IMG_NUM_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'IH_PERF_SEL'
IH_PERF_SEL__enumvalues = {
0: 'IH_PERF_SEL_CYCLE',
1: 'IH_PERF_SEL_IDLE',
2: 'IH_PERF_SEL_INPUT_IDLE',
3: 'IH_PERF_SEL_BUFFER_IDLE',
4: 'IH_PERF_SEL_RB0_FULL',
5: 'IH_PERF_SEL_RB0_OVERFLOW',
6: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK',
7: 'IH_PERF_SEL_RB0_WPTR_WRAP',
8: 'IH_PERF_SEL_RB0_RPTR_WRAP',
9: 'IH_PERF_SEL_MC_WR_IDLE',
10: 'IH_PERF_SEL_MC_WR_COUNT',
11: 'IH_PERF_SEL_MC_WR_STALL',
12: 'IH_PERF_SEL_MC_WR_CLEAN_PENDING',
13: 'IH_PERF_SEL_MC_WR_CLEAN_STALL',
14: 'IH_PERF_SEL_BIF_LINE0_RISING',
15: 'IH_PERF_SEL_BIF_LINE0_FALLING',
16: 'IH_PERF_SEL_RB1_FULL',
17: 'IH_PERF_SEL_RB1_OVERFLOW',
18: 'IH_PERF_SEL_COOKIE_REC_ERROR',
19: 'IH_PERF_SEL_RB1_WPTR_WRAP',
20: 'IH_PERF_SEL_RB1_RPTR_WRAP',
21: 'IH_PERF_SEL_RB2_FULL',
22: 'IH_PERF_SEL_RB2_OVERFLOW',
23: 'IH_PERF_SEL_CLIENT_CREDIT_ERROR',
24: 'IH_PERF_SEL_RB2_WPTR_WRAP',
25: 'IH_PERF_SEL_RB2_RPTR_WRAP',
26: 'IH_PERF_SEL_STORM_CLIENT_INT_DROP',
27: 'IH_PERF_SEL_SELF_IV_VALID',
28: 'IH_PERF_SEL_BUFFER_FIFO_FULL',
29: 'IH_PERF_SEL_RB0_FULL_VF0',
30: 'IH_PERF_SEL_RB0_FULL_VF1',
31: 'IH_PERF_SEL_RB0_FULL_VF2',
32: 'IH_PERF_SEL_RB0_FULL_VF3',
33: 'IH_PERF_SEL_RB0_FULL_VF4',
34: 'IH_PERF_SEL_RB0_FULL_VF5',
35: 'IH_PERF_SEL_RB0_FULL_VF6',
36: 'IH_PERF_SEL_RB0_FULL_VF7',
37: 'IH_PERF_SEL_RB0_FULL_VF8',
38: 'IH_PERF_SEL_RB0_FULL_VF9',
39: 'IH_PERF_SEL_RB0_FULL_VF10',
40: 'IH_PERF_SEL_RB0_FULL_VF11',
41: 'IH_PERF_SEL_RB0_FULL_VF12',
42: 'IH_PERF_SEL_RB0_FULL_VF13',
43: 'IH_PERF_SEL_RB0_FULL_VF14',
44: 'IH_PERF_SEL_RB0_FULL_VF15',
45: 'IH_PERF_SEL_RB0_FULL_VF16',
46: 'IH_PERF_SEL_RB0_FULL_VF17',
47: 'IH_PERF_SEL_RB0_FULL_VF18',
48: 'IH_PERF_SEL_RB0_FULL_VF19',
49: 'IH_PERF_SEL_RB0_FULL_VF20',
50: 'IH_PERF_SEL_RB0_FULL_VF21',
51: 'IH_PERF_SEL_RB0_FULL_VF22',
52: 'IH_PERF_SEL_RB0_FULL_VF23',
53: 'IH_PERF_SEL_RB0_FULL_VF24',
54: 'IH_PERF_SEL_RB0_FULL_VF25',
55: 'IH_PERF_SEL_RB0_FULL_VF26',
56: 'IH_PERF_SEL_RB0_FULL_VF27',
57: 'IH_PERF_SEL_RB0_FULL_VF28',
58: 'IH_PERF_SEL_RB0_FULL_VF29',
59: 'IH_PERF_SEL_RB0_FULL_VF30',
60: 'IH_PERF_SEL_RB0_OVERFLOW_VF0',
61: 'IH_PERF_SEL_RB0_OVERFLOW_VF1',
62: 'IH_PERF_SEL_RB0_OVERFLOW_VF2',
63: 'IH_PERF_SEL_RB0_OVERFLOW_VF3',
64: 'IH_PERF_SEL_RB0_OVERFLOW_VF4',
65: 'IH_PERF_SEL_RB0_OVERFLOW_VF5',
66: 'IH_PERF_SEL_RB0_OVERFLOW_VF6',
67: 'IH_PERF_SEL_RB0_OVERFLOW_VF7',
68: 'IH_PERF_SEL_RB0_OVERFLOW_VF8',
69: 'IH_PERF_SEL_RB0_OVERFLOW_VF9',
70: 'IH_PERF_SEL_RB0_OVERFLOW_VF10',
71: 'IH_PERF_SEL_RB0_OVERFLOW_VF11',
72: 'IH_PERF_SEL_RB0_OVERFLOW_VF12',
73: 'IH_PERF_SEL_RB0_OVERFLOW_VF13',
74: 'IH_PERF_SEL_RB0_OVERFLOW_VF14',
75: 'IH_PERF_SEL_RB0_OVERFLOW_VF15',
76: 'IH_PERF_SEL_RB0_OVERFLOW_VF16',
77: 'IH_PERF_SEL_RB0_OVERFLOW_VF17',
78: 'IH_PERF_SEL_RB0_OVERFLOW_VF18',
79: 'IH_PERF_SEL_RB0_OVERFLOW_VF19',
80: 'IH_PERF_SEL_RB0_OVERFLOW_VF20',
81: 'IH_PERF_SEL_RB0_OVERFLOW_VF21',
82: 'IH_PERF_SEL_RB0_OVERFLOW_VF22',
83: 'IH_PERF_SEL_RB0_OVERFLOW_VF23',
84: 'IH_PERF_SEL_RB0_OVERFLOW_VF24',
85: 'IH_PERF_SEL_RB0_OVERFLOW_VF25',
86: 'IH_PERF_SEL_RB0_OVERFLOW_VF26',
87: 'IH_PERF_SEL_RB0_OVERFLOW_VF27',
88: 'IH_PERF_SEL_RB0_OVERFLOW_VF28',
89: 'IH_PERF_SEL_RB0_OVERFLOW_VF29',
90: 'IH_PERF_SEL_RB0_OVERFLOW_VF30',
91: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0',
92: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1',
93: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2',
94: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3',
95: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4',
96: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5',
97: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6',
98: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7',
99: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8',
100: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9',
101: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10',
102: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11',
103: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12',
104: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13',
105: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14',
106: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15',
107: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF16',
108: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF17',
109: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF18',
110: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF19',
111: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF20',
112: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF21',
113: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF22',
114: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF23',
115: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF24',
116: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF25',
117: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF26',
118: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF27',
119: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF28',
120: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF29',
121: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF30',
122: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0',
123: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1',
124: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2',
125: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3',
126: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4',
127: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5',
128: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6',
129: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7',
130: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8',
131: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9',
132: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10',
133: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11',
134: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12',
135: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13',
136: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14',
137: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15',
138: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF16',
139: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF17',
140: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF18',
141: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF19',
142: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF20',
143: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF21',
144: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF22',
145: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF23',
146: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF24',
147: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF25',
148: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF26',
149: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF27',
150: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF28',
151: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF29',
152: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF30',
153: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0',
154: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1',
155: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2',
156: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3',
157: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4',
158: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5',
159: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6',
160: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7',
161: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8',
162: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9',
163: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10',
164: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11',
165: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12',
166: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13',
167: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14',
168: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15',
169: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF16',
170: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF17',
171: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF18',
172: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF19',
173: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF20',
174: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF21',
175: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF22',
176: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF23',
177: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF24',
178: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF25',
179: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF26',
180: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF27',
181: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF28',
182: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF29',
183: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF30',
184: 'IH_PERF_SEL_BIF_LINE0_RISING_VF0',
185: 'IH_PERF_SEL_BIF_LINE0_RISING_VF1',
186: 'IH_PERF_SEL_BIF_LINE0_RISING_VF2',
187: 'IH_PERF_SEL_BIF_LINE0_RISING_VF3',
188: 'IH_PERF_SEL_BIF_LINE0_RISING_VF4',
189: 'IH_PERF_SEL_BIF_LINE0_RISING_VF5',
190: 'IH_PERF_SEL_BIF_LINE0_RISING_VF6',
191: 'IH_PERF_SEL_BIF_LINE0_RISING_VF7',
192: 'IH_PERF_SEL_BIF_LINE0_RISING_VF8',
193: 'IH_PERF_SEL_BIF_LINE0_RISING_VF9',
194: 'IH_PERF_SEL_BIF_LINE0_RISING_VF10',
195: 'IH_PERF_SEL_BIF_LINE0_RISING_VF11',
196: 'IH_PERF_SEL_BIF_LINE0_RISING_VF12',
197: 'IH_PERF_SEL_BIF_LINE0_RISING_VF13',
198: 'IH_PERF_SEL_BIF_LINE0_RISING_VF14',
199: 'IH_PERF_SEL_BIF_LINE0_RISING_VF15',
200: 'IH_PERF_SEL_BIF_LINE0_RISING_VF16',
201: 'IH_PERF_SEL_BIF_LINE0_RISING_VF17',
202: 'IH_PERF_SEL_BIF_LINE0_RISING_VF18',
203: 'IH_PERF_SEL_BIF_LINE0_RISING_VF19',
204: 'IH_PERF_SEL_BIF_LINE0_RISING_VF20',
205: 'IH_PERF_SEL_BIF_LINE0_RISING_VF21',
206: 'IH_PERF_SEL_BIF_LINE0_RISING_VF22',
207: 'IH_PERF_SEL_BIF_LINE0_RISING_VF23',
208: 'IH_PERF_SEL_BIF_LINE0_RISING_VF24',
209: 'IH_PERF_SEL_BIF_LINE0_RISING_VF25',
210: 'IH_PERF_SEL_BIF_LINE0_RISING_VF26',
211: 'IH_PERF_SEL_BIF_LINE0_RISING_VF27',
212: 'IH_PERF_SEL_BIF_LINE0_RISING_VF28',
213: 'IH_PERF_SEL_BIF_LINE0_RISING_VF29',
214: 'IH_PERF_SEL_BIF_LINE0_RISING_VF30',
215: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0',
216: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1',
217: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2',
218: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3',
219: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4',
220: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5',
221: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6',
222: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7',
223: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8',
224: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9',
225: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10',
226: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11',
227: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12',
228: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13',
229: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14',
230: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15',
231: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF16',
232: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF17',
233: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF18',
234: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF19',
235: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF20',
236: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF21',
237: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF22',
238: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF23',
239: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF24',
240: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF25',
241: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF26',
242: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF27',
243: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF28',
244: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF29',
245: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF30',
246: 'IH_PERF_SEL_CLIENT0_INT',
247: 'IH_PERF_SEL_CLIENT1_INT',
248: 'IH_PERF_SEL_CLIENT2_INT',
249: 'IH_PERF_SEL_CLIENT3_INT',
250: 'IH_PERF_SEL_CLIENT4_INT',
251: 'IH_PERF_SEL_CLIENT5_INT',
252: 'IH_PERF_SEL_CLIENT6_INT',
253: 'IH_PERF_SEL_CLIENT7_INT',
254: 'IH_PERF_SEL_CLIENT8_INT',
255: 'IH_PERF_SEL_CLIENT9_INT',
256: 'IH_PERF_SEL_CLIENT10_INT',
257: 'IH_PERF_SEL_CLIENT11_INT',
258: 'IH_PERF_SEL_CLIENT12_INT',
259: 'IH_PERF_SEL_CLIENT13_INT',
260: 'IH_PERF_SEL_CLIENT14_INT',
261: 'IH_PERF_SEL_CLIENT15_INT',
262: 'IH_PERF_SEL_CLIENT16_INT',
263: 'IH_PERF_SEL_CLIENT17_INT',
264: 'IH_PERF_SEL_CLIENT18_INT',
265: 'IH_PERF_SEL_CLIENT19_INT',
266: 'IH_PERF_SEL_CLIENT20_INT',
267: 'IH_PERF_SEL_CLIENT21_INT',
268: 'IH_PERF_SEL_CLIENT22_INT',
269: 'IH_PERF_SEL_CLIENT23_INT',
270: 'IH_PERF_SEL_CLIENT24_INT',
271: 'IH_PERF_SEL_CLIENT25_INT',
272: 'IH_PERF_SEL_CLIENT26_INT',
273: 'IH_PERF_SEL_CLIENT27_INT',
274: 'IH_PERF_SEL_CLIENT28_INT',
275: 'IH_PERF_SEL_CLIENT29_INT',
276: 'IH_PERF_SEL_CLIENT30_INT',
277: 'IH_PERF_SEL_CLIENT31_INT',
278: 'IH_PERF_SEL_RB1_FULL_VF0',
279: 'IH_PERF_SEL_RB1_FULL_VF1',
280: 'IH_PERF_SEL_RB1_FULL_VF2',
281: 'IH_PERF_SEL_RB1_FULL_VF3',
282: 'IH_PERF_SEL_RB1_FULL_VF4',
283: 'IH_PERF_SEL_RB1_FULL_VF5',
284: 'IH_PERF_SEL_RB1_FULL_VF6',
285: 'IH_PERF_SEL_RB1_FULL_VF7',
286: 'IH_PERF_SEL_RB1_FULL_VF8',
287: 'IH_PERF_SEL_RB1_FULL_VF9',
288: 'IH_PERF_SEL_RB1_FULL_VF10',
289: 'IH_PERF_SEL_RB1_FULL_VF11',
290: 'IH_PERF_SEL_RB1_FULL_VF12',
291: 'IH_PERF_SEL_RB1_FULL_VF13',
292: 'IH_PERF_SEL_RB1_FULL_VF14',
293: 'IH_PERF_SEL_RB1_FULL_VF15',
294: 'IH_PERF_SEL_RB1_FULL_VF16',
295: 'IH_PERF_SEL_RB1_FULL_VF17',
296: 'IH_PERF_SEL_RB1_FULL_VF18',
297: 'IH_PERF_SEL_RB1_FULL_VF19',
298: 'IH_PERF_SEL_RB1_FULL_VF20',
299: 'IH_PERF_SEL_RB1_FULL_VF21',
300: 'IH_PERF_SEL_RB1_FULL_VF22',
301: 'IH_PERF_SEL_RB1_FULL_VF23',
302: 'IH_PERF_SEL_RB1_FULL_VF24',
303: 'IH_PERF_SEL_RB1_FULL_VF25',
304: 'IH_PERF_SEL_RB1_FULL_VF26',
305: 'IH_PERF_SEL_RB1_FULL_VF27',
306: 'IH_PERF_SEL_RB1_FULL_VF28',
307: 'IH_PERF_SEL_RB1_FULL_VF29',
308: 'IH_PERF_SEL_RB1_FULL_VF30',
309: 'IH_PERF_SEL_RB1_OVERFLOW_VF0',
310: 'IH_PERF_SEL_RB1_OVERFLOW_VF1',
311: 'IH_PERF_SEL_RB1_OVERFLOW_VF2',
312: 'IH_PERF_SEL_RB1_OVERFLOW_VF3',
313: 'IH_PERF_SEL_RB1_OVERFLOW_VF4',
314: 'IH_PERF_SEL_RB1_OVERFLOW_VF5',
315: 'IH_PERF_SEL_RB1_OVERFLOW_VF6',
316: 'IH_PERF_SEL_RB1_OVERFLOW_VF7',
317: 'IH_PERF_SEL_RB1_OVERFLOW_VF8',
318: 'IH_PERF_SEL_RB1_OVERFLOW_VF9',
319: 'IH_PERF_SEL_RB1_OVERFLOW_VF10',
320: 'IH_PERF_SEL_RB1_OVERFLOW_VF11',
321: 'IH_PERF_SEL_RB1_OVERFLOW_VF12',
322: 'IH_PERF_SEL_RB1_OVERFLOW_VF13',
323: 'IH_PERF_SEL_RB1_OVERFLOW_VF14',
324: 'IH_PERF_SEL_RB1_OVERFLOW_VF15',
325: 'IH_PERF_SEL_RB1_OVERFLOW_VF16',
326: 'IH_PERF_SEL_RB1_OVERFLOW_VF17',
327: 'IH_PERF_SEL_RB1_OVERFLOW_VF18',
328: 'IH_PERF_SEL_RB1_OVERFLOW_VF19',
329: 'IH_PERF_SEL_RB1_OVERFLOW_VF20',
330: 'IH_PERF_SEL_RB1_OVERFLOW_VF21',
331: 'IH_PERF_SEL_RB1_OVERFLOW_VF22',
332: 'IH_PERF_SEL_RB1_OVERFLOW_VF23',
333: 'IH_PERF_SEL_RB1_OVERFLOW_VF24',
334: 'IH_PERF_SEL_RB1_OVERFLOW_VF25',
335: 'IH_PERF_SEL_RB1_OVERFLOW_VF26',
336: 'IH_PERF_SEL_RB1_OVERFLOW_VF27',
337: 'IH_PERF_SEL_RB1_OVERFLOW_VF28',
338: 'IH_PERF_SEL_RB1_OVERFLOW_VF29',
339: 'IH_PERF_SEL_RB1_OVERFLOW_VF30',
340: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0',
341: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1',
342: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2',
343: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3',
344: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4',
345: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5',
346: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6',
347: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7',
348: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8',
349: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9',
350: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10',
351: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11',
352: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12',
353: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13',
354: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14',
355: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15',
356: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF16',
357: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF17',
358: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF18',
359: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF19',
360: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF20',
361: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF21',
362: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF22',
363: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF23',
364: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF24',
365: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF25',
366: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF26',
367: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF27',
368: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF28',
369: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF29',
370: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF30',
371: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0',
372: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1',
373: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2',
374: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3',
375: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4',
376: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5',
377: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6',
378: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7',
379: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8',
380: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9',
381: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10',
382: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11',
383: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12',
384: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13',
385: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14',
386: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15',
387: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF16',
388: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF17',
389: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF18',
390: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF19',
391: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF20',
392: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF21',
393: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF22',
394: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF23',
395: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF24',
396: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF25',
397: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF26',
398: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF27',
399: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF28',
400: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF29',
401: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF30',
402: 'IH_PERF_SEL_RB2_FULL_VF0',
403: 'IH_PERF_SEL_RB2_FULL_VF1',
404: 'IH_PERF_SEL_RB2_FULL_VF2',
405: 'IH_PERF_SEL_RB2_FULL_VF3',
406: 'IH_PERF_SEL_RB2_FULL_VF4',
407: 'IH_PERF_SEL_RB2_FULL_VF5',
408: 'IH_PERF_SEL_RB2_FULL_VF6',
409: 'IH_PERF_SEL_RB2_FULL_VF7',
410: 'IH_PERF_SEL_RB2_FULL_VF8',
411: 'IH_PERF_SEL_RB2_FULL_VF9',
412: 'IH_PERF_SEL_RB2_FULL_VF10',
413: 'IH_PERF_SEL_RB2_FULL_VF11',
414: 'IH_PERF_SEL_RB2_FULL_VF12',
415: 'IH_PERF_SEL_RB2_FULL_VF13',
416: 'IH_PERF_SEL_RB2_FULL_VF14',
417: 'IH_PERF_SEL_RB2_FULL_VF15',
418: 'IH_PERF_SEL_RB2_FULL_VF16',
419: 'IH_PERF_SEL_RB2_FULL_VF17',
420: 'IH_PERF_SEL_RB2_FULL_VF18',
421: 'IH_PERF_SEL_RB2_FULL_VF19',
422: 'IH_PERF_SEL_RB2_FULL_VF20',
423: 'IH_PERF_SEL_RB2_FULL_VF21',
424: 'IH_PERF_SEL_RB2_FULL_VF22',
425: 'IH_PERF_SEL_RB2_FULL_VF23',
426: 'IH_PERF_SEL_RB2_FULL_VF24',
427: 'IH_PERF_SEL_RB2_FULL_VF25',
428: 'IH_PERF_SEL_RB2_FULL_VF26',
429: 'IH_PERF_SEL_RB2_FULL_VF27',
430: 'IH_PERF_SEL_RB2_FULL_VF28',
431: 'IH_PERF_SEL_RB2_FULL_VF29',
432: 'IH_PERF_SEL_RB2_FULL_VF30',
433: 'IH_PERF_SEL_RB2_OVERFLOW_VF0',
434: 'IH_PERF_SEL_RB2_OVERFLOW_VF1',
435: 'IH_PERF_SEL_RB2_OVERFLOW_VF2',
436: 'IH_PERF_SEL_RB2_OVERFLOW_VF3',
437: 'IH_PERF_SEL_RB2_OVERFLOW_VF4',
438: 'IH_PERF_SEL_RB2_OVERFLOW_VF5',
439: 'IH_PERF_SEL_RB2_OVERFLOW_VF6',
440: 'IH_PERF_SEL_RB2_OVERFLOW_VF7',
441: 'IH_PERF_SEL_RB2_OVERFLOW_VF8',
442: 'IH_PERF_SEL_RB2_OVERFLOW_VF9',
443: 'IH_PERF_SEL_RB2_OVERFLOW_VF10',
444: 'IH_PERF_SEL_RB2_OVERFLOW_VF11',
445: 'IH_PERF_SEL_RB2_OVERFLOW_VF12',
446: 'IH_PERF_SEL_RB2_OVERFLOW_VF13',
447: 'IH_PERF_SEL_RB2_OVERFLOW_VF14',
448: 'IH_PERF_SEL_RB2_OVERFLOW_VF15',
449: 'IH_PERF_SEL_RB2_OVERFLOW_VF16',
450: 'IH_PERF_SEL_RB2_OVERFLOW_VF17',
451: 'IH_PERF_SEL_RB2_OVERFLOW_VF18',
452: 'IH_PERF_SEL_RB2_OVERFLOW_VF19',
453: 'IH_PERF_SEL_RB2_OVERFLOW_VF20',
454: 'IH_PERF_SEL_RB2_OVERFLOW_VF21',
455: 'IH_PERF_SEL_RB2_OVERFLOW_VF22',
456: 'IH_PERF_SEL_RB2_OVERFLOW_VF23',
457: 'IH_PERF_SEL_RB2_OVERFLOW_VF24',
458: 'IH_PERF_SEL_RB2_OVERFLOW_VF25',
459: 'IH_PERF_SEL_RB2_OVERFLOW_VF26',
460: 'IH_PERF_SEL_RB2_OVERFLOW_VF27',
461: 'IH_PERF_SEL_RB2_OVERFLOW_VF28',
462: 'IH_PERF_SEL_RB2_OVERFLOW_VF29',
463: 'IH_PERF_SEL_RB2_OVERFLOW_VF30',
464: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0',
465: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1',
466: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2',
467: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3',
468: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4',
469: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5',
470: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6',
471: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7',
472: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8',
473: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9',
474: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10',
475: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11',
476: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12',
477: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13',
478: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14',
479: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15',
480: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF16',
481: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF17',
482: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF18',
483: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF19',
484: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF20',
485: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF21',
486: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF22',
487: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF23',
488: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF24',
489: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF25',
490: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF26',
491: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF27',
492: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF28',
493: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF29',
494: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF30',
495: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0',
496: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1',
497: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2',
498: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3',
499: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4',
500: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5',
501: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6',
502: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7',
503: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8',
504: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9',
505: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10',
506: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11',
507: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12',
508: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13',
509: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14',
510: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15',
511: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF16',
512: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF17',
513: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF18',
514: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF19',
515: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF20',
516: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF21',
517: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF22',
518: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF23',
519: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF24',
520: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF25',
521: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF26',
522: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF27',
523: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF28',
524: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF29',
525: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF30',
526: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP',
527: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0',
528: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1',
529: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2',
530: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3',
531: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4',
532: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5',
533: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6',
534: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7',
535: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8',
536: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9',
537: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10',
538: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11',
539: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12',
540: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13',
541: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14',
542: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15',
543: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16',
544: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF17',
545: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF18',
546: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF19',
547: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF20',
548: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF21',
549: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF22',
550: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF23',
551: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF24',
552: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF25',
553: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF26',
554: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF27',
555: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF28',
556: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF29',
557: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF30',
558: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP',
559: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0',
560: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1',
561: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2',
562: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3',
563: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4',
564: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5',
565: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6',
566: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7',
567: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8',
568: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9',
569: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10',
570: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11',
571: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12',
572: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13',
573: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14',
574: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15',
575: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16',
576: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF17',
577: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF18',
578: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF19',
579: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF20',
580: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF21',
581: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF22',
582: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF23',
583: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF24',
584: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF25',
585: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF26',
586: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF27',
587: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF28',
588: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF29',
589: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF30',
590: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP',
591: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0',
592: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1',
593: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2',
594: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3',
595: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4',
596: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5',
597: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6',
598: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7',
599: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8',
600: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9',
601: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10',
602: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11',
603: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12',
604: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13',
605: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14',
606: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15',
607: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16',
608: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF17',
609: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF18',
610: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF19',
611: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF20',
612: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF21',
613: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF22',
614: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF23',
615: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF24',
616: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF25',
617: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF26',
618: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF27',
619: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF28',
620: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF29',
621: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF30',
622: 'IH_PERF_SEL_RB0_LOAD_RPTR',
623: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0',
624: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1',
625: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2',
626: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3',
627: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4',
628: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5',
629: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6',
630: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7',
631: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8',
632: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9',
633: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10',
634: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11',
635: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12',
636: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13',
637: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14',
638: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15',
639: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF16',
640: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF17',
641: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF18',
642: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF19',
643: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF20',
644: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF21',
645: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF22',
646: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF23',
647: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF24',
648: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF25',
649: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF26',
650: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF27',
651: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF28',
652: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF29',
653: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF30',
654: 'IH_PERF_SEL_RB1_LOAD_RPTR',
655: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0',
656: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1',
657: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2',
658: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3',
659: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4',
660: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5',
661: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6',
662: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7',
663: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8',
664: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9',
665: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10',
666: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11',
667: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12',
668: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13',
669: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14',
670: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15',
671: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF16',
672: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF17',
673: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF18',
674: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF19',
675: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF20',
676: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF21',
677: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF22',
678: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF23',
679: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF24',
680: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF25',
681: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF26',
682: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF27',
683: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF28',
684: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF29',
685: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF30',
686: 'IH_PERF_SEL_RB2_LOAD_RPTR',
687: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0',
688: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1',
689: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2',
690: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3',
691: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4',
692: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5',
693: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6',
694: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7',
695: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8',
696: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9',
697: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10',
698: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11',
699: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12',
700: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13',
701: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14',
702: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15',
703: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF16',
704: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF17',
705: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF18',
706: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF19',
707: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF20',
708: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF21',
709: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF22',
710: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF23',
711: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF24',
712: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF25',
713: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF26',
714: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF27',
715: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF28',
716: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF29',
717: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF30',
}
IH_PERF_SEL_CYCLE = 0
IH_PERF_SEL_IDLE = 1
IH_PERF_SEL_INPUT_IDLE = 2
IH_PERF_SEL_BUFFER_IDLE = 3
IH_PERF_SEL_RB0_FULL = 4
IH_PERF_SEL_RB0_OVERFLOW = 5
IH_PERF_SEL_RB0_WPTR_WRITEBACK = 6
IH_PERF_SEL_RB0_WPTR_WRAP = 7
IH_PERF_SEL_RB0_RPTR_WRAP = 8
IH_PERF_SEL_MC_WR_IDLE = 9
IH_PERF_SEL_MC_WR_COUNT = 10
IH_PERF_SEL_MC_WR_STALL = 11
IH_PERF_SEL_MC_WR_CLEAN_PENDING = 12
IH_PERF_SEL_MC_WR_CLEAN_STALL = 13
IH_PERF_SEL_BIF_LINE0_RISING = 14
IH_PERF_SEL_BIF_LINE0_FALLING = 15
IH_PERF_SEL_RB1_FULL = 16
IH_PERF_SEL_RB1_OVERFLOW = 17
IH_PERF_SEL_COOKIE_REC_ERROR = 18
IH_PERF_SEL_RB1_WPTR_WRAP = 19
IH_PERF_SEL_RB1_RPTR_WRAP = 20
IH_PERF_SEL_RB2_FULL = 21
IH_PERF_SEL_RB2_OVERFLOW = 22
IH_PERF_SEL_CLIENT_CREDIT_ERROR = 23
IH_PERF_SEL_RB2_WPTR_WRAP = 24
IH_PERF_SEL_RB2_RPTR_WRAP = 25
IH_PERF_SEL_STORM_CLIENT_INT_DROP = 26
IH_PERF_SEL_SELF_IV_VALID = 27
IH_PERF_SEL_BUFFER_FIFO_FULL = 28
IH_PERF_SEL_RB0_FULL_VF0 = 29
IH_PERF_SEL_RB0_FULL_VF1 = 30
IH_PERF_SEL_RB0_FULL_VF2 = 31
IH_PERF_SEL_RB0_FULL_VF3 = 32
IH_PERF_SEL_RB0_FULL_VF4 = 33
IH_PERF_SEL_RB0_FULL_VF5 = 34
IH_PERF_SEL_RB0_FULL_VF6 = 35
IH_PERF_SEL_RB0_FULL_VF7 = 36
IH_PERF_SEL_RB0_FULL_VF8 = 37
IH_PERF_SEL_RB0_FULL_VF9 = 38
IH_PERF_SEL_RB0_FULL_VF10 = 39
IH_PERF_SEL_RB0_FULL_VF11 = 40
IH_PERF_SEL_RB0_FULL_VF12 = 41
IH_PERF_SEL_RB0_FULL_VF13 = 42
IH_PERF_SEL_RB0_FULL_VF14 = 43
IH_PERF_SEL_RB0_FULL_VF15 = 44
IH_PERF_SEL_RB0_FULL_VF16 = 45
IH_PERF_SEL_RB0_FULL_VF17 = 46
IH_PERF_SEL_RB0_FULL_VF18 = 47
IH_PERF_SEL_RB0_FULL_VF19 = 48
IH_PERF_SEL_RB0_FULL_VF20 = 49
IH_PERF_SEL_RB0_FULL_VF21 = 50
IH_PERF_SEL_RB0_FULL_VF22 = 51
IH_PERF_SEL_RB0_FULL_VF23 = 52
IH_PERF_SEL_RB0_FULL_VF24 = 53
IH_PERF_SEL_RB0_FULL_VF25 = 54
IH_PERF_SEL_RB0_FULL_VF26 = 55
IH_PERF_SEL_RB0_FULL_VF27 = 56
IH_PERF_SEL_RB0_FULL_VF28 = 57
IH_PERF_SEL_RB0_FULL_VF29 = 58
IH_PERF_SEL_RB0_FULL_VF30 = 59
IH_PERF_SEL_RB0_OVERFLOW_VF0 = 60
IH_PERF_SEL_RB0_OVERFLOW_VF1 = 61
IH_PERF_SEL_RB0_OVERFLOW_VF2 = 62
IH_PERF_SEL_RB0_OVERFLOW_VF3 = 63
IH_PERF_SEL_RB0_OVERFLOW_VF4 = 64
IH_PERF_SEL_RB0_OVERFLOW_VF5 = 65
IH_PERF_SEL_RB0_OVERFLOW_VF6 = 66
IH_PERF_SEL_RB0_OVERFLOW_VF7 = 67
IH_PERF_SEL_RB0_OVERFLOW_VF8 = 68
IH_PERF_SEL_RB0_OVERFLOW_VF9 = 69
IH_PERF_SEL_RB0_OVERFLOW_VF10 = 70
IH_PERF_SEL_RB0_OVERFLOW_VF11 = 71
IH_PERF_SEL_RB0_OVERFLOW_VF12 = 72
IH_PERF_SEL_RB0_OVERFLOW_VF13 = 73
IH_PERF_SEL_RB0_OVERFLOW_VF14 = 74
IH_PERF_SEL_RB0_OVERFLOW_VF15 = 75
IH_PERF_SEL_RB0_OVERFLOW_VF16 = 76
IH_PERF_SEL_RB0_OVERFLOW_VF17 = 77
IH_PERF_SEL_RB0_OVERFLOW_VF18 = 78
IH_PERF_SEL_RB0_OVERFLOW_VF19 = 79
IH_PERF_SEL_RB0_OVERFLOW_VF20 = 80
IH_PERF_SEL_RB0_OVERFLOW_VF21 = 81
IH_PERF_SEL_RB0_OVERFLOW_VF22 = 82
IH_PERF_SEL_RB0_OVERFLOW_VF23 = 83
IH_PERF_SEL_RB0_OVERFLOW_VF24 = 84
IH_PERF_SEL_RB0_OVERFLOW_VF25 = 85
IH_PERF_SEL_RB0_OVERFLOW_VF26 = 86
IH_PERF_SEL_RB0_OVERFLOW_VF27 = 87
IH_PERF_SEL_RB0_OVERFLOW_VF28 = 88
IH_PERF_SEL_RB0_OVERFLOW_VF29 = 89
IH_PERF_SEL_RB0_OVERFLOW_VF30 = 90
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 91
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 92
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 93
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 94
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 95
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 96
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 97
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 98
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 99
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 100
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 101
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 102
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 103
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 104
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 105
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 106
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF16 = 107
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF17 = 108
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF18 = 109
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF19 = 110
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF20 = 111
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF21 = 112
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF22 = 113
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF23 = 114
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF24 = 115
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF25 = 116
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF26 = 117
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF27 = 118
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF28 = 119
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF29 = 120
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF30 = 121
IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 122
IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 123
IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 124
IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 125
IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 126
IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 127
IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 128
IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 129
IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 130
IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 131
IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 132
IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 133
IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 134
IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 135
IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 136
IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 137
IH_PERF_SEL_RB0_WPTR_WRAP_VF16 = 138
IH_PERF_SEL_RB0_WPTR_WRAP_VF17 = 139
IH_PERF_SEL_RB0_WPTR_WRAP_VF18 = 140
IH_PERF_SEL_RB0_WPTR_WRAP_VF19 = 141
IH_PERF_SEL_RB0_WPTR_WRAP_VF20 = 142
IH_PERF_SEL_RB0_WPTR_WRAP_VF21 = 143
IH_PERF_SEL_RB0_WPTR_WRAP_VF22 = 144
IH_PERF_SEL_RB0_WPTR_WRAP_VF23 = 145
IH_PERF_SEL_RB0_WPTR_WRAP_VF24 = 146
IH_PERF_SEL_RB0_WPTR_WRAP_VF25 = 147
IH_PERF_SEL_RB0_WPTR_WRAP_VF26 = 148
IH_PERF_SEL_RB0_WPTR_WRAP_VF27 = 149
IH_PERF_SEL_RB0_WPTR_WRAP_VF28 = 150
IH_PERF_SEL_RB0_WPTR_WRAP_VF29 = 151
IH_PERF_SEL_RB0_WPTR_WRAP_VF30 = 152
IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 153
IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 154
IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 155
IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 156
IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 157
IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 158
IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 159
IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 160
IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 161
IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 162
IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 163
IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 164
IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 165
IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 166
IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 167
IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 168
IH_PERF_SEL_RB0_RPTR_WRAP_VF16 = 169
IH_PERF_SEL_RB0_RPTR_WRAP_VF17 = 170
IH_PERF_SEL_RB0_RPTR_WRAP_VF18 = 171
IH_PERF_SEL_RB0_RPTR_WRAP_VF19 = 172
IH_PERF_SEL_RB0_RPTR_WRAP_VF20 = 173
IH_PERF_SEL_RB0_RPTR_WRAP_VF21 = 174
IH_PERF_SEL_RB0_RPTR_WRAP_VF22 = 175
IH_PERF_SEL_RB0_RPTR_WRAP_VF23 = 176
IH_PERF_SEL_RB0_RPTR_WRAP_VF24 = 177
IH_PERF_SEL_RB0_RPTR_WRAP_VF25 = 178
IH_PERF_SEL_RB0_RPTR_WRAP_VF26 = 179
IH_PERF_SEL_RB0_RPTR_WRAP_VF27 = 180
IH_PERF_SEL_RB0_RPTR_WRAP_VF28 = 181
IH_PERF_SEL_RB0_RPTR_WRAP_VF29 = 182
IH_PERF_SEL_RB0_RPTR_WRAP_VF30 = 183
IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 184
IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 185
IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 186
IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 187
IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 188
IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 189
IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 190
IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 191
IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 192
IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 193
IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 194
IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 195
IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 196
IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 197
IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 198
IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 199
IH_PERF_SEL_BIF_LINE0_RISING_VF16 = 200
IH_PERF_SEL_BIF_LINE0_RISING_VF17 = 201
IH_PERF_SEL_BIF_LINE0_RISING_VF18 = 202
IH_PERF_SEL_BIF_LINE0_RISING_VF19 = 203
IH_PERF_SEL_BIF_LINE0_RISING_VF20 = 204
IH_PERF_SEL_BIF_LINE0_RISING_VF21 = 205
IH_PERF_SEL_BIF_LINE0_RISING_VF22 = 206
IH_PERF_SEL_BIF_LINE0_RISING_VF23 = 207
IH_PERF_SEL_BIF_LINE0_RISING_VF24 = 208
IH_PERF_SEL_BIF_LINE0_RISING_VF25 = 209
IH_PERF_SEL_BIF_LINE0_RISING_VF26 = 210
IH_PERF_SEL_BIF_LINE0_RISING_VF27 = 211
IH_PERF_SEL_BIF_LINE0_RISING_VF28 = 212
IH_PERF_SEL_BIF_LINE0_RISING_VF29 = 213
IH_PERF_SEL_BIF_LINE0_RISING_VF30 = 214
IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 215
IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 216
IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 217
IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 218
IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 219
IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 220
IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 221
IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 222
IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 223
IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 224
IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 225
IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 226
IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 227
IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 228
IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 229
IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 230
IH_PERF_SEL_BIF_LINE0_FALLING_VF16 = 231
IH_PERF_SEL_BIF_LINE0_FALLING_VF17 = 232
IH_PERF_SEL_BIF_LINE0_FALLING_VF18 = 233
IH_PERF_SEL_BIF_LINE0_FALLING_VF19 = 234
IH_PERF_SEL_BIF_LINE0_FALLING_VF20 = 235
IH_PERF_SEL_BIF_LINE0_FALLING_VF21 = 236
IH_PERF_SEL_BIF_LINE0_FALLING_VF22 = 237
IH_PERF_SEL_BIF_LINE0_FALLING_VF23 = 238
IH_PERF_SEL_BIF_LINE0_FALLING_VF24 = 239
IH_PERF_SEL_BIF_LINE0_FALLING_VF25 = 240
IH_PERF_SEL_BIF_LINE0_FALLING_VF26 = 241
IH_PERF_SEL_BIF_LINE0_FALLING_VF27 = 242
IH_PERF_SEL_BIF_LINE0_FALLING_VF28 = 243
IH_PERF_SEL_BIF_LINE0_FALLING_VF29 = 244
IH_PERF_SEL_BIF_LINE0_FALLING_VF30 = 245
IH_PERF_SEL_CLIENT0_INT = 246
IH_PERF_SEL_CLIENT1_INT = 247
IH_PERF_SEL_CLIENT2_INT = 248
IH_PERF_SEL_CLIENT3_INT = 249
IH_PERF_SEL_CLIENT4_INT = 250
IH_PERF_SEL_CLIENT5_INT = 251
IH_PERF_SEL_CLIENT6_INT = 252
IH_PERF_SEL_CLIENT7_INT = 253
IH_PERF_SEL_CLIENT8_INT = 254
IH_PERF_SEL_CLIENT9_INT = 255
IH_PERF_SEL_CLIENT10_INT = 256
IH_PERF_SEL_CLIENT11_INT = 257
IH_PERF_SEL_CLIENT12_INT = 258
IH_PERF_SEL_CLIENT13_INT = 259
IH_PERF_SEL_CLIENT14_INT = 260
IH_PERF_SEL_CLIENT15_INT = 261
IH_PERF_SEL_CLIENT16_INT = 262
IH_PERF_SEL_CLIENT17_INT = 263
IH_PERF_SEL_CLIENT18_INT = 264
IH_PERF_SEL_CLIENT19_INT = 265
IH_PERF_SEL_CLIENT20_INT = 266
IH_PERF_SEL_CLIENT21_INT = 267
IH_PERF_SEL_CLIENT22_INT = 268
IH_PERF_SEL_CLIENT23_INT = 269
IH_PERF_SEL_CLIENT24_INT = 270
IH_PERF_SEL_CLIENT25_INT = 271
IH_PERF_SEL_CLIENT26_INT = 272
IH_PERF_SEL_CLIENT27_INT = 273
IH_PERF_SEL_CLIENT28_INT = 274
IH_PERF_SEL_CLIENT29_INT = 275
IH_PERF_SEL_CLIENT30_INT = 276
IH_PERF_SEL_CLIENT31_INT = 277
IH_PERF_SEL_RB1_FULL_VF0 = 278
IH_PERF_SEL_RB1_FULL_VF1 = 279
IH_PERF_SEL_RB1_FULL_VF2 = 280
IH_PERF_SEL_RB1_FULL_VF3 = 281
IH_PERF_SEL_RB1_FULL_VF4 = 282
IH_PERF_SEL_RB1_FULL_VF5 = 283
IH_PERF_SEL_RB1_FULL_VF6 = 284
IH_PERF_SEL_RB1_FULL_VF7 = 285
IH_PERF_SEL_RB1_FULL_VF8 = 286
IH_PERF_SEL_RB1_FULL_VF9 = 287
IH_PERF_SEL_RB1_FULL_VF10 = 288
IH_PERF_SEL_RB1_FULL_VF11 = 289
IH_PERF_SEL_RB1_FULL_VF12 = 290
IH_PERF_SEL_RB1_FULL_VF13 = 291
IH_PERF_SEL_RB1_FULL_VF14 = 292
IH_PERF_SEL_RB1_FULL_VF15 = 293
IH_PERF_SEL_RB1_FULL_VF16 = 294
IH_PERF_SEL_RB1_FULL_VF17 = 295
IH_PERF_SEL_RB1_FULL_VF18 = 296
IH_PERF_SEL_RB1_FULL_VF19 = 297
IH_PERF_SEL_RB1_FULL_VF20 = 298
IH_PERF_SEL_RB1_FULL_VF21 = 299
IH_PERF_SEL_RB1_FULL_VF22 = 300
IH_PERF_SEL_RB1_FULL_VF23 = 301
IH_PERF_SEL_RB1_FULL_VF24 = 302
IH_PERF_SEL_RB1_FULL_VF25 = 303
IH_PERF_SEL_RB1_FULL_VF26 = 304
IH_PERF_SEL_RB1_FULL_VF27 = 305
IH_PERF_SEL_RB1_FULL_VF28 = 306
IH_PERF_SEL_RB1_FULL_VF29 = 307
IH_PERF_SEL_RB1_FULL_VF30 = 308
IH_PERF_SEL_RB1_OVERFLOW_VF0 = 309
IH_PERF_SEL_RB1_OVERFLOW_VF1 = 310
IH_PERF_SEL_RB1_OVERFLOW_VF2 = 311
IH_PERF_SEL_RB1_OVERFLOW_VF3 = 312
IH_PERF_SEL_RB1_OVERFLOW_VF4 = 313
IH_PERF_SEL_RB1_OVERFLOW_VF5 = 314
IH_PERF_SEL_RB1_OVERFLOW_VF6 = 315
IH_PERF_SEL_RB1_OVERFLOW_VF7 = 316
IH_PERF_SEL_RB1_OVERFLOW_VF8 = 317
IH_PERF_SEL_RB1_OVERFLOW_VF9 = 318
IH_PERF_SEL_RB1_OVERFLOW_VF10 = 319
IH_PERF_SEL_RB1_OVERFLOW_VF11 = 320
IH_PERF_SEL_RB1_OVERFLOW_VF12 = 321
IH_PERF_SEL_RB1_OVERFLOW_VF13 = 322
IH_PERF_SEL_RB1_OVERFLOW_VF14 = 323
IH_PERF_SEL_RB1_OVERFLOW_VF15 = 324
IH_PERF_SEL_RB1_OVERFLOW_VF16 = 325
IH_PERF_SEL_RB1_OVERFLOW_VF17 = 326
IH_PERF_SEL_RB1_OVERFLOW_VF18 = 327
IH_PERF_SEL_RB1_OVERFLOW_VF19 = 328
IH_PERF_SEL_RB1_OVERFLOW_VF20 = 329
IH_PERF_SEL_RB1_OVERFLOW_VF21 = 330
IH_PERF_SEL_RB1_OVERFLOW_VF22 = 331
IH_PERF_SEL_RB1_OVERFLOW_VF23 = 332
IH_PERF_SEL_RB1_OVERFLOW_VF24 = 333
IH_PERF_SEL_RB1_OVERFLOW_VF25 = 334
IH_PERF_SEL_RB1_OVERFLOW_VF26 = 335
IH_PERF_SEL_RB1_OVERFLOW_VF27 = 336
IH_PERF_SEL_RB1_OVERFLOW_VF28 = 337
IH_PERF_SEL_RB1_OVERFLOW_VF29 = 338
IH_PERF_SEL_RB1_OVERFLOW_VF30 = 339
IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 340
IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 341
IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 342
IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 343
IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 344
IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 345
IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 346
IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 347
IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 348
IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 349
IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 350
IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 351
IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 352
IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 353
IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 354
IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 355
IH_PERF_SEL_RB1_WPTR_WRAP_VF16 = 356
IH_PERF_SEL_RB1_WPTR_WRAP_VF17 = 357
IH_PERF_SEL_RB1_WPTR_WRAP_VF18 = 358
IH_PERF_SEL_RB1_WPTR_WRAP_VF19 = 359
IH_PERF_SEL_RB1_WPTR_WRAP_VF20 = 360
IH_PERF_SEL_RB1_WPTR_WRAP_VF21 = 361
IH_PERF_SEL_RB1_WPTR_WRAP_VF22 = 362
IH_PERF_SEL_RB1_WPTR_WRAP_VF23 = 363
IH_PERF_SEL_RB1_WPTR_WRAP_VF24 = 364
IH_PERF_SEL_RB1_WPTR_WRAP_VF25 = 365
IH_PERF_SEL_RB1_WPTR_WRAP_VF26 = 366
IH_PERF_SEL_RB1_WPTR_WRAP_VF27 = 367
IH_PERF_SEL_RB1_WPTR_WRAP_VF28 = 368
IH_PERF_SEL_RB1_WPTR_WRAP_VF29 = 369
IH_PERF_SEL_RB1_WPTR_WRAP_VF30 = 370
IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 371
IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 372
IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 373
IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 374
IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 375
IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 376
IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 377
IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 378
IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 379
IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 380
IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 381
IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 382
IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 383
IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 384
IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 385
IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 386
IH_PERF_SEL_RB1_RPTR_WRAP_VF16 = 387
IH_PERF_SEL_RB1_RPTR_WRAP_VF17 = 388
IH_PERF_SEL_RB1_RPTR_WRAP_VF18 = 389
IH_PERF_SEL_RB1_RPTR_WRAP_VF19 = 390
IH_PERF_SEL_RB1_RPTR_WRAP_VF20 = 391
IH_PERF_SEL_RB1_RPTR_WRAP_VF21 = 392
IH_PERF_SEL_RB1_RPTR_WRAP_VF22 = 393
IH_PERF_SEL_RB1_RPTR_WRAP_VF23 = 394
IH_PERF_SEL_RB1_RPTR_WRAP_VF24 = 395
IH_PERF_SEL_RB1_RPTR_WRAP_VF25 = 396
IH_PERF_SEL_RB1_RPTR_WRAP_VF26 = 397
IH_PERF_SEL_RB1_RPTR_WRAP_VF27 = 398
IH_PERF_SEL_RB1_RPTR_WRAP_VF28 = 399
IH_PERF_SEL_RB1_RPTR_WRAP_VF29 = 400
IH_PERF_SEL_RB1_RPTR_WRAP_VF30 = 401
IH_PERF_SEL_RB2_FULL_VF0 = 402
IH_PERF_SEL_RB2_FULL_VF1 = 403
IH_PERF_SEL_RB2_FULL_VF2 = 404
IH_PERF_SEL_RB2_FULL_VF3 = 405
IH_PERF_SEL_RB2_FULL_VF4 = 406
IH_PERF_SEL_RB2_FULL_VF5 = 407
IH_PERF_SEL_RB2_FULL_VF6 = 408
IH_PERF_SEL_RB2_FULL_VF7 = 409
IH_PERF_SEL_RB2_FULL_VF8 = 410
IH_PERF_SEL_RB2_FULL_VF9 = 411
IH_PERF_SEL_RB2_FULL_VF10 = 412
IH_PERF_SEL_RB2_FULL_VF11 = 413
IH_PERF_SEL_RB2_FULL_VF12 = 414
IH_PERF_SEL_RB2_FULL_VF13 = 415
IH_PERF_SEL_RB2_FULL_VF14 = 416
IH_PERF_SEL_RB2_FULL_VF15 = 417
IH_PERF_SEL_RB2_FULL_VF16 = 418
IH_PERF_SEL_RB2_FULL_VF17 = 419
IH_PERF_SEL_RB2_FULL_VF18 = 420
IH_PERF_SEL_RB2_FULL_VF19 = 421
IH_PERF_SEL_RB2_FULL_VF20 = 422
IH_PERF_SEL_RB2_FULL_VF21 = 423
IH_PERF_SEL_RB2_FULL_VF22 = 424
IH_PERF_SEL_RB2_FULL_VF23 = 425
IH_PERF_SEL_RB2_FULL_VF24 = 426
IH_PERF_SEL_RB2_FULL_VF25 = 427
IH_PERF_SEL_RB2_FULL_VF26 = 428
IH_PERF_SEL_RB2_FULL_VF27 = 429
IH_PERF_SEL_RB2_FULL_VF28 = 430
IH_PERF_SEL_RB2_FULL_VF29 = 431
IH_PERF_SEL_RB2_FULL_VF30 = 432
IH_PERF_SEL_RB2_OVERFLOW_VF0 = 433
IH_PERF_SEL_RB2_OVERFLOW_VF1 = 434
IH_PERF_SEL_RB2_OVERFLOW_VF2 = 435
IH_PERF_SEL_RB2_OVERFLOW_VF3 = 436
IH_PERF_SEL_RB2_OVERFLOW_VF4 = 437
IH_PERF_SEL_RB2_OVERFLOW_VF5 = 438
IH_PERF_SEL_RB2_OVERFLOW_VF6 = 439
IH_PERF_SEL_RB2_OVERFLOW_VF7 = 440
IH_PERF_SEL_RB2_OVERFLOW_VF8 = 441
IH_PERF_SEL_RB2_OVERFLOW_VF9 = 442
IH_PERF_SEL_RB2_OVERFLOW_VF10 = 443
IH_PERF_SEL_RB2_OVERFLOW_VF11 = 444
IH_PERF_SEL_RB2_OVERFLOW_VF12 = 445
IH_PERF_SEL_RB2_OVERFLOW_VF13 = 446
IH_PERF_SEL_RB2_OVERFLOW_VF14 = 447
IH_PERF_SEL_RB2_OVERFLOW_VF15 = 448
IH_PERF_SEL_RB2_OVERFLOW_VF16 = 449
IH_PERF_SEL_RB2_OVERFLOW_VF17 = 450
IH_PERF_SEL_RB2_OVERFLOW_VF18 = 451
IH_PERF_SEL_RB2_OVERFLOW_VF19 = 452
IH_PERF_SEL_RB2_OVERFLOW_VF20 = 453
IH_PERF_SEL_RB2_OVERFLOW_VF21 = 454
IH_PERF_SEL_RB2_OVERFLOW_VF22 = 455
IH_PERF_SEL_RB2_OVERFLOW_VF23 = 456
IH_PERF_SEL_RB2_OVERFLOW_VF24 = 457
IH_PERF_SEL_RB2_OVERFLOW_VF25 = 458
IH_PERF_SEL_RB2_OVERFLOW_VF26 = 459
IH_PERF_SEL_RB2_OVERFLOW_VF27 = 460
IH_PERF_SEL_RB2_OVERFLOW_VF28 = 461
IH_PERF_SEL_RB2_OVERFLOW_VF29 = 462
IH_PERF_SEL_RB2_OVERFLOW_VF30 = 463
IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 464
IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 465
IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 466
IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 467
IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 468
IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 469
IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 470
IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 471
IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 472
IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 473
IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 474
IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 475
IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 476
IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 477
IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 478
IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 479
IH_PERF_SEL_RB2_WPTR_WRAP_VF16 = 480
IH_PERF_SEL_RB2_WPTR_WRAP_VF17 = 481
IH_PERF_SEL_RB2_WPTR_WRAP_VF18 = 482
IH_PERF_SEL_RB2_WPTR_WRAP_VF19 = 483
IH_PERF_SEL_RB2_WPTR_WRAP_VF20 = 484
IH_PERF_SEL_RB2_WPTR_WRAP_VF21 = 485
IH_PERF_SEL_RB2_WPTR_WRAP_VF22 = 486
IH_PERF_SEL_RB2_WPTR_WRAP_VF23 = 487
IH_PERF_SEL_RB2_WPTR_WRAP_VF24 = 488
IH_PERF_SEL_RB2_WPTR_WRAP_VF25 = 489
IH_PERF_SEL_RB2_WPTR_WRAP_VF26 = 490
IH_PERF_SEL_RB2_WPTR_WRAP_VF27 = 491
IH_PERF_SEL_RB2_WPTR_WRAP_VF28 = 492
IH_PERF_SEL_RB2_WPTR_WRAP_VF29 = 493
IH_PERF_SEL_RB2_WPTR_WRAP_VF30 = 494
IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 495
IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 496
IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 497
IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 498
IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 499
IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 500
IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 501
IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 502
IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 503
IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 504
IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 505
IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 506
IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 507
IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 508
IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 509
IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 510
IH_PERF_SEL_RB2_RPTR_WRAP_VF16 = 511
IH_PERF_SEL_RB2_RPTR_WRAP_VF17 = 512
IH_PERF_SEL_RB2_RPTR_WRAP_VF18 = 513
IH_PERF_SEL_RB2_RPTR_WRAP_VF19 = 514
IH_PERF_SEL_RB2_RPTR_WRAP_VF20 = 515
IH_PERF_SEL_RB2_RPTR_WRAP_VF21 = 516
IH_PERF_SEL_RB2_RPTR_WRAP_VF22 = 517
IH_PERF_SEL_RB2_RPTR_WRAP_VF23 = 518
IH_PERF_SEL_RB2_RPTR_WRAP_VF24 = 519
IH_PERF_SEL_RB2_RPTR_WRAP_VF25 = 520
IH_PERF_SEL_RB2_RPTR_WRAP_VF26 = 521
IH_PERF_SEL_RB2_RPTR_WRAP_VF27 = 522
IH_PERF_SEL_RB2_RPTR_WRAP_VF28 = 523
IH_PERF_SEL_RB2_RPTR_WRAP_VF29 = 524
IH_PERF_SEL_RB2_RPTR_WRAP_VF30 = 525
IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 526
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 527
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 528
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 529
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 530
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 531
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 532
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 533
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 534
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 535
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 536
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 537
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 538
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 539
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 540
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 541
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 542
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16 = 543
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF17 = 544
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF18 = 545
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF19 = 546
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF20 = 547
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF21 = 548
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF22 = 549
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF23 = 550
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF24 = 551
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF25 = 552
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF26 = 553
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF27 = 554
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF28 = 555
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF29 = 556
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF30 = 557
IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 558
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 559
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 560
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 561
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 562
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 563
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 564
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 565
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 566
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 567
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 568
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 569
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 570
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 571
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 572
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 573
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 574
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16 = 575
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF17 = 576
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF18 = 577
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF19 = 578
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF20 = 579
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF21 = 580
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF22 = 581
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF23 = 582
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF24 = 583
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF25 = 584
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF26 = 585
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF27 = 586
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF28 = 587
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF29 = 588
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF30 = 589
IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 590
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 591
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 592
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 593
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 594
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 595
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 596
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 597
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 598
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 599
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 600
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 601
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 602
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 603
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 604
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 605
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 606
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16 = 607
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF17 = 608
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF18 = 609
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF19 = 610
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF20 = 611
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF21 = 612
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF22 = 613
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF23 = 614
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF24 = 615
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF25 = 616
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF26 = 617
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF27 = 618
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF28 = 619
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF29 = 620
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF30 = 621
IH_PERF_SEL_RB0_LOAD_RPTR = 622
IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 623
IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 624
IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 625
IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 626
IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 627
IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 628
IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 629
IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 630
IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 631
IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 632
IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 633
IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 634
IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 635
IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 636
IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 637
IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 638
IH_PERF_SEL_RB0_LOAD_RPTR_VF16 = 639
IH_PERF_SEL_RB0_LOAD_RPTR_VF17 = 640
IH_PERF_SEL_RB0_LOAD_RPTR_VF18 = 641
IH_PERF_SEL_RB0_LOAD_RPTR_VF19 = 642
IH_PERF_SEL_RB0_LOAD_RPTR_VF20 = 643
IH_PERF_SEL_RB0_LOAD_RPTR_VF21 = 644
IH_PERF_SEL_RB0_LOAD_RPTR_VF22 = 645
IH_PERF_SEL_RB0_LOAD_RPTR_VF23 = 646
IH_PERF_SEL_RB0_LOAD_RPTR_VF24 = 647
IH_PERF_SEL_RB0_LOAD_RPTR_VF25 = 648
IH_PERF_SEL_RB0_LOAD_RPTR_VF26 = 649
IH_PERF_SEL_RB0_LOAD_RPTR_VF27 = 650
IH_PERF_SEL_RB0_LOAD_RPTR_VF28 = 651
IH_PERF_SEL_RB0_LOAD_RPTR_VF29 = 652
IH_PERF_SEL_RB0_LOAD_RPTR_VF30 = 653
IH_PERF_SEL_RB1_LOAD_RPTR = 654
IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 655
IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 656
IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 657
IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 658
IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 659
IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 660
IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 661
IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 662
IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 663
IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 664
IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 665
IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 666
IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 667
IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 668
IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 669
IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 670
IH_PERF_SEL_RB1_LOAD_RPTR_VF16 = 671
IH_PERF_SEL_RB1_LOAD_RPTR_VF17 = 672
IH_PERF_SEL_RB1_LOAD_RPTR_VF18 = 673
IH_PERF_SEL_RB1_LOAD_RPTR_VF19 = 674
IH_PERF_SEL_RB1_LOAD_RPTR_VF20 = 675
IH_PERF_SEL_RB1_LOAD_RPTR_VF21 = 676
IH_PERF_SEL_RB1_LOAD_RPTR_VF22 = 677
IH_PERF_SEL_RB1_LOAD_RPTR_VF23 = 678
IH_PERF_SEL_RB1_LOAD_RPTR_VF24 = 679
IH_PERF_SEL_RB1_LOAD_RPTR_VF25 = 680
IH_PERF_SEL_RB1_LOAD_RPTR_VF26 = 681
IH_PERF_SEL_RB1_LOAD_RPTR_VF27 = 682
IH_PERF_SEL_RB1_LOAD_RPTR_VF28 = 683
IH_PERF_SEL_RB1_LOAD_RPTR_VF29 = 684
IH_PERF_SEL_RB1_LOAD_RPTR_VF30 = 685
IH_PERF_SEL_RB2_LOAD_RPTR = 686
IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 687
IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 688
IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 689
IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 690
IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 691
IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 692
IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 693
IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 694
IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 695
IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 696
IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 697
IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 698
IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 699
IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 700
IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 701
IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 702
IH_PERF_SEL_RB2_LOAD_RPTR_VF16 = 703
IH_PERF_SEL_RB2_LOAD_RPTR_VF17 = 704
IH_PERF_SEL_RB2_LOAD_RPTR_VF18 = 705
IH_PERF_SEL_RB2_LOAD_RPTR_VF19 = 706
IH_PERF_SEL_RB2_LOAD_RPTR_VF20 = 707
IH_PERF_SEL_RB2_LOAD_RPTR_VF21 = 708
IH_PERF_SEL_RB2_LOAD_RPTR_VF22 = 709
IH_PERF_SEL_RB2_LOAD_RPTR_VF23 = 710
IH_PERF_SEL_RB2_LOAD_RPTR_VF24 = 711
IH_PERF_SEL_RB2_LOAD_RPTR_VF25 = 712
IH_PERF_SEL_RB2_LOAD_RPTR_VF26 = 713
IH_PERF_SEL_RB2_LOAD_RPTR_VF27 = 714
IH_PERF_SEL_RB2_LOAD_RPTR_VF28 = 715
IH_PERF_SEL_RB2_LOAD_RPTR_VF29 = 716
IH_PERF_SEL_RB2_LOAD_RPTR_VF30 = 717
IH_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'IH_CLIENT_TYPE'
IH_CLIENT_TYPE__enumvalues = {
0: 'IH_GFX_VMID_CLIENT',
1: 'IH_MM_VMID_CLIENT',
2: 'IH_MULTI_VMID_CLIENT',
3: 'IH_CLIENT_TYPE_RESERVED',
}
IH_GFX_VMID_CLIENT = 0
IH_MM_VMID_CLIENT = 1
IH_MULTI_VMID_CLIENT = 2
IH_CLIENT_TYPE_RESERVED = 3
IH_CLIENT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'IH_RING_ID'
IH_RING_ID__enumvalues = {
0: 'IH_RING_ID_INTERRUPT',
1: 'IH_RING_ID_REQUEST',
2: 'IH_RING_ID_TRANSLATION',
3: 'IH_RING_ID_RESERVED',
}
IH_RING_ID_INTERRUPT = 0
IH_RING_ID_REQUEST = 1
IH_RING_ID_TRANSLATION = 2
IH_RING_ID_RESERVED = 3
IH_RING_ID = ctypes.c_uint32 # enum
# values for enumeration 'IH_VF_RB_SELECT'
IH_VF_RB_SELECT__enumvalues = {
0: 'IH_VF_RB_SELECT_CLIENT_FCN_ID',
1: 'IH_VF_RB_SELECT_IH_FCN_ID',
2: 'IH_VF_RB_SELECT_PF',
3: 'IH_VF_RB_SELECT_RESERVED',
}
IH_VF_RB_SELECT_CLIENT_FCN_ID = 0
IH_VF_RB_SELECT_IH_FCN_ID = 1
IH_VF_RB_SELECT_PF = 2
IH_VF_RB_SELECT_RESERVED = 3
IH_VF_RB_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'IH_INTERFACE_TYPE'
IH_INTERFACE_TYPE__enumvalues = {
0: 'IH_LEGACY_INTERFACE',
1: 'IH_REGISTER_WRITE_INTERFACE',
}
IH_LEGACY_INTERFACE = 0
IH_REGISTER_WRITE_INTERFACE = 1
IH_INTERFACE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SEM_PERF_SEL'
SEM_PERF_SEL__enumvalues = {
0: 'SEM_PERF_SEL_CYCLE',
1: 'SEM_PERF_SEL_IDLE',
2: 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL',
3: 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL',
4: 'SEM_PERF_SEL_UVD_REQ_SIGNAL',
5: 'SEM_PERF_SEL_VCE0_REQ_SIGNAL',
6: 'SEM_PERF_SEL_ACP_REQ_SIGNAL',
7: 'SEM_PERF_SEL_ISP_REQ_SIGNAL',
8: 'SEM_PERF_SEL_VCE1_REQ_SIGNAL',
9: 'SEM_PERF_SEL_VP8_REQ_SIGNAL',
10: 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL',
11: 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL',
12: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL',
13: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL',
14: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL',
15: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL',
16: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL',
17: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL',
18: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL',
19: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL',
20: 'SEM_PERF_SEL_SDMA0_REQ_WAIT',
21: 'SEM_PERF_SEL_SDMA1_REQ_WAIT',
22: 'SEM_PERF_SEL_UVD_REQ_WAIT',
23: 'SEM_PERF_SEL_VCE0_REQ_WAIT',
24: 'SEM_PERF_SEL_ACP_REQ_WAIT',
25: 'SEM_PERF_SEL_ISP_REQ_WAIT',
26: 'SEM_PERF_SEL_VCE1_REQ_WAIT',
27: 'SEM_PERF_SEL_VP8_REQ_WAIT',
28: 'SEM_PERF_SEL_CPG_E0_REQ_WAIT',
29: 'SEM_PERF_SEL_CPG_E1_REQ_WAIT',
30: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT',
31: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT',
32: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT',
33: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT',
34: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT',
35: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT',
36: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT',
37: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT',
38: 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT',
39: 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT',
40: 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT',
41: 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT',
42: 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT',
43: 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT',
44: 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT',
45: 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT',
46: 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT',
47: 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT',
48: 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT',
49: 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT',
50: 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT',
51: 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT',
52: 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT',
53: 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT',
54: 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT',
55: 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT',
56: 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT',
57: 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT',
58: 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT',
59: 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT',
60: 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT',
61: 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT',
62: 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT',
63: 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT',
64: 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT',
65: 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT',
66: 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT',
67: 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT',
68: 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT',
69: 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT',
70: 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT',
71: 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT',
72: 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT',
73: 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT',
74: 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT',
75: 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT',
76: 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT',
77: 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT',
78: 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT',
79: 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT',
80: 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT',
81: 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT',
82: 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT',
83: 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT',
84: 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT',
85: 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT',
86: 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT',
87: 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT',
88: 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT',
89: 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT',
90: 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT',
91: 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT',
92: 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT',
93: 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT',
94: 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT',
95: 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT',
96: 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT',
97: 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT',
98: 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT',
99: 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT',
100: 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT',
101: 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT',
102: 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT',
103: 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT',
104: 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT',
105: 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT',
106: 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT',
107: 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT',
108: 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT',
109: 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT',
110: 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT',
111: 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT',
112: 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT',
113: 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT',
114: 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT',
115: 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT',
116: 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT',
117: 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT',
118: 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT',
119: 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT',
120: 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT',
121: 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT',
122: 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT',
123: 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT',
124: 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT',
125: 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT',
126: 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT',
127: 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT',
128: 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT',
129: 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT',
130: 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT',
131: 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT',
132: 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT',
133: 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT',
134: 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT',
135: 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT',
136: 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT',
137: 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT',
138: 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT',
139: 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT',
140: 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT',
141: 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT',
142: 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT',
143: 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT',
144: 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT',
145: 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT',
146: 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT',
147: 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT',
148: 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT',
149: 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT',
150: 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT',
151: 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT',
152: 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT',
153: 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT',
154: 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT',
155: 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT',
156: 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT',
157: 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT',
158: 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT',
159: 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT',
160: 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT',
161: 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT',
162: 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT',
163: 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT',
164: 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT',
165: 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT',
166: 'SEM_PERF_SEL_MC_RD_REQ',
167: 'SEM_PERF_SEL_MC_RD_RET',
168: 'SEM_PERF_SEL_MC_WR_REQ',
169: 'SEM_PERF_SEL_MC_WR_RET',
170: 'SEM_PERF_SEL_ATC_REQ',
171: 'SEM_PERF_SEL_ATC_RET',
172: 'SEM_PERF_SEL_ATC_XNACK',
173: 'SEM_PERF_SEL_ATC_INVALIDATION',
174: 'SEM_PERF_SEL_ATC_VM_INVALIDATION',
}
SEM_PERF_SEL_CYCLE = 0
SEM_PERF_SEL_IDLE = 1
SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 2
SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 3
SEM_PERF_SEL_UVD_REQ_SIGNAL = 4
SEM_PERF_SEL_VCE0_REQ_SIGNAL = 5
SEM_PERF_SEL_ACP_REQ_SIGNAL = 6
SEM_PERF_SEL_ISP_REQ_SIGNAL = 7
SEM_PERF_SEL_VCE1_REQ_SIGNAL = 8
SEM_PERF_SEL_VP8_REQ_SIGNAL = 9
SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 10
SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 11
SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 12
SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 13
SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 14
SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 15
SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 16
SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 17
SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 18
SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 19
SEM_PERF_SEL_SDMA0_REQ_WAIT = 20
SEM_PERF_SEL_SDMA1_REQ_WAIT = 21
SEM_PERF_SEL_UVD_REQ_WAIT = 22
SEM_PERF_SEL_VCE0_REQ_WAIT = 23
SEM_PERF_SEL_ACP_REQ_WAIT = 24
SEM_PERF_SEL_ISP_REQ_WAIT = 25
SEM_PERF_SEL_VCE1_REQ_WAIT = 26
SEM_PERF_SEL_VP8_REQ_WAIT = 27
SEM_PERF_SEL_CPG_E0_REQ_WAIT = 28
SEM_PERF_SEL_CPG_E1_REQ_WAIT = 29
SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 30
SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 31
SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 32
SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 33
SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 34
SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 35
SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 36
SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 37
SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 38
SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 39
SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 40
SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 41
SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 42
SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 43
SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 44
SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 45
SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 46
SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 47
SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 48
SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 49
SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 50
SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 51
SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 52
SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 53
SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 54
SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 55
SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 56
SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 57
SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 58
SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 59
SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 60
SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 61
SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 62
SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 63
SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 64
SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 65
SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 66
SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 67
SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 68
SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 69
SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 70
SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 71
SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 72
SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 73
SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 74
SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 75
SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 76
SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 77
SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 78
SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 79
SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 80
SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 81
SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 82
SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 83
SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 84
SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 85
SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 86
SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 87
SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 88
SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 89
SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 90
SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 91
SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 92
SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 93
SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 94
SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 95
SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 96
SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 97
SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 98
SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 99
SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 100
SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 101
SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 102
SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 103
SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 104
SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 105
SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 106
SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 107
SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 108
SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 109
SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 110
SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 111
SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 112
SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 113
SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 114
SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 115
SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 116
SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 117
SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 118
SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 119
SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 120
SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 121
SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 122
SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 123
SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 124
SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 125
SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 126
SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 127
SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 128
SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 129
SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 130
SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 131
SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 132
SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 133
SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 134
SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 135
SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 136
SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 137
SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 138
SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 139
SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 140
SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 141
SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 142
SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 143
SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 144
SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 145
SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 146
SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 147
SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 148
SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 149
SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 150
SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 151
SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 152
SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 153
SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 154
SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 155
SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 156
SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 157
SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 158
SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 159
SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 160
SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 161
SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 162
SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 163
SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 164
SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 165
SEM_PERF_SEL_MC_RD_REQ = 166
SEM_PERF_SEL_MC_RD_RET = 167
SEM_PERF_SEL_MC_WR_REQ = 168
SEM_PERF_SEL_MC_WR_RET = 169
SEM_PERF_SEL_ATC_REQ = 170
SEM_PERF_SEL_ATC_RET = 171
SEM_PERF_SEL_ATC_XNACK = 172
SEM_PERF_SEL_ATC_INVALIDATION = 173
SEM_PERF_SEL_ATC_VM_INVALIDATION = 174
SEM_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'EFC_SURFACE_PIXEL_FORMAT'
EFC_SURFACE_PIXEL_FORMAT__enumvalues = {
1: 'EFC_ARGB1555',
2: 'EFC_RGBA5551',
3: 'EFC_RGB565',
4: 'EFC_BGR565',
5: 'EFC_ARGB4444',
6: 'EFC_RGBA4444',
8: 'EFC_ARGB8888',
9: 'EFC_RGBA8888',
10: 'EFC_ARGB2101010',
11: 'EFC_RGBA1010102',
12: 'EFC_AYCrCb8888',
13: 'EFC_YCrCbA8888',
14: 'EFC_ACrYCb8888',
15: 'EFC_CrYCbA8888',
16: 'EFC_ARGB16161616_10MSB',
17: 'EFC_RGBA16161616_10MSB',
18: 'EFC_ARGB16161616_10LSB',
19: 'EFC_RGBA16161616_10LSB',
20: 'EFC_ARGB16161616_12MSB',
21: 'EFC_RGBA16161616_12MSB',
22: 'EFC_ARGB16161616_12LSB',
23: 'EFC_RGBA16161616_12LSB',
24: 'EFC_ARGB16161616_FLOAT',
25: 'EFC_RGBA16161616_FLOAT',
26: 'EFC_ARGB16161616_UNORM',
27: 'EFC_RGBA16161616_UNORM',
28: 'EFC_ARGB16161616_SNORM',
29: 'EFC_RGBA16161616_SNORM',
32: 'EFC_AYCrCb16161616_10MSB',
33: 'EFC_AYCrCb16161616_10LSB',
34: 'EFC_YCrCbA16161616_10MSB',
35: 'EFC_YCrCbA16161616_10LSB',
36: 'EFC_ACrYCb16161616_10MSB',
37: 'EFC_ACrYCb16161616_10LSB',
38: 'EFC_CrYCbA16161616_10MSB',
39: 'EFC_CrYCbA16161616_10LSB',
40: 'EFC_AYCrCb16161616_12MSB',
41: 'EFC_AYCrCb16161616_12LSB',
42: 'EFC_YCrCbA16161616_12MSB',
43: 'EFC_YCrCbA16161616_12LSB',
44: 'EFC_ACrYCb16161616_12MSB',
45: 'EFC_ACrYCb16161616_12LSB',
46: 'EFC_CrYCbA16161616_12MSB',
47: 'EFC_CrYCbA16161616_12LSB',
64: 'EFC_Y8_CrCb88_420_PLANAR',
65: 'EFC_Y8_CbCr88_420_PLANAR',
66: 'EFC_Y10_CrCb1010_420_PLANAR',
67: 'EFC_Y10_CbCr1010_420_PLANAR',
68: 'EFC_Y12_CrCb1212_420_PLANAR',
69: 'EFC_Y12_CbCr1212_420_PLANAR',
72: 'EFC_YCrYCb8888_422_PACKED',
73: 'EFC_YCbYCr8888_422_PACKED',
74: 'EFC_CrYCbY8888_422_PACKED',
75: 'EFC_CbYCrY8888_422_PACKED',
76: 'EFC_YCrYCb10101010_422_PACKED',
77: 'EFC_YCbYCr10101010_422_PACKED',
78: 'EFC_CrYCbY10101010_422_PACKED',
79: 'EFC_CbYCrY10101010_422_PACKED',
80: 'EFC_YCrYCb12121212_422_PACKED',
81: 'EFC_YCbYCr12121212_422_PACKED',
82: 'EFC_CrYCbY12121212_422_PACKED',
83: 'EFC_CbYCrY12121212_422_PACKED',
112: 'EFC_RGB111110_FIX',
113: 'EFC_BGR101111_FIX',
114: 'EFC_ACrYCb2101010',
115: 'EFC_CrYCbA1010102',
118: 'EFC_RGB111110_FLOAT',
119: 'EFC_BGR101111_FLOAT',
120: 'EFC_MONO_8',
121: 'EFC_MONO_10MSB',
122: 'EFC_MONO_10LSB',
123: 'EFC_MONO_12MSB',
124: 'EFC_MONO_12LSB',
125: 'EFC_MONO_16',
}
EFC_ARGB1555 = 1
EFC_RGBA5551 = 2
EFC_RGB565 = 3
EFC_BGR565 = 4
EFC_ARGB4444 = 5
EFC_RGBA4444 = 6
EFC_ARGB8888 = 8
EFC_RGBA8888 = 9
EFC_ARGB2101010 = 10
EFC_RGBA1010102 = 11
EFC_AYCrCb8888 = 12
EFC_YCrCbA8888 = 13
EFC_ACrYCb8888 = 14
EFC_CrYCbA8888 = 15
EFC_ARGB16161616_10MSB = 16
EFC_RGBA16161616_10MSB = 17
EFC_ARGB16161616_10LSB = 18
EFC_RGBA16161616_10LSB = 19
EFC_ARGB16161616_12MSB = 20
EFC_RGBA16161616_12MSB = 21
EFC_ARGB16161616_12LSB = 22
EFC_RGBA16161616_12LSB = 23
EFC_ARGB16161616_FLOAT = 24
EFC_RGBA16161616_FLOAT = 25
EFC_ARGB16161616_UNORM = 26
EFC_RGBA16161616_UNORM = 27
EFC_ARGB16161616_SNORM = 28
EFC_RGBA16161616_SNORM = 29
EFC_AYCrCb16161616_10MSB = 32
EFC_AYCrCb16161616_10LSB = 33
EFC_YCrCbA16161616_10MSB = 34
EFC_YCrCbA16161616_10LSB = 35
EFC_ACrYCb16161616_10MSB = 36
EFC_ACrYCb16161616_10LSB = 37
EFC_CrYCbA16161616_10MSB = 38
EFC_CrYCbA16161616_10LSB = 39
EFC_AYCrCb16161616_12MSB = 40
EFC_AYCrCb16161616_12LSB = 41
EFC_YCrCbA16161616_12MSB = 42
EFC_YCrCbA16161616_12LSB = 43
EFC_ACrYCb16161616_12MSB = 44
EFC_ACrYCb16161616_12LSB = 45
EFC_CrYCbA16161616_12MSB = 46
EFC_CrYCbA16161616_12LSB = 47
EFC_Y8_CrCb88_420_PLANAR = 64
EFC_Y8_CbCr88_420_PLANAR = 65
EFC_Y10_CrCb1010_420_PLANAR = 66
EFC_Y10_CbCr1010_420_PLANAR = 67
EFC_Y12_CrCb1212_420_PLANAR = 68
EFC_Y12_CbCr1212_420_PLANAR = 69
EFC_YCrYCb8888_422_PACKED = 72
EFC_YCbYCr8888_422_PACKED = 73
EFC_CrYCbY8888_422_PACKED = 74
EFC_CbYCrY8888_422_PACKED = 75
EFC_YCrYCb10101010_422_PACKED = 76
EFC_YCbYCr10101010_422_PACKED = 77
EFC_CrYCbY10101010_422_PACKED = 78
EFC_CbYCrY10101010_422_PACKED = 79
EFC_YCrYCb12121212_422_PACKED = 80
EFC_YCbYCr12121212_422_PACKED = 81
EFC_CrYCbY12121212_422_PACKED = 82
EFC_CbYCrY12121212_422_PACKED = 83
EFC_RGB111110_FIX = 112
EFC_BGR101111_FIX = 113
EFC_ACrYCb2101010 = 114
EFC_CrYCbA1010102 = 115
EFC_RGB111110_FLOAT = 118
EFC_BGR101111_FLOAT = 119
EFC_MONO_8 = 120
EFC_MONO_10MSB = 121
EFC_MONO_10LSB = 122
EFC_MONO_12MSB = 123
EFC_MONO_12LSB = 124
EFC_MONO_16 = 125
EFC_SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'UVDFirmwareCommand'
UVDFirmwareCommand__enumvalues = {
0: 'UVDFC_FENCE',
1: 'UVDFC_TRAP',
2: 'UVDFC_DECODED_ADDR',
3: 'UVDFC_MBLOCK_ADDR',
4: 'UVDFC_ITBUF_ADDR',
5: 'UVDFC_DISPLAY_ADDR',
6: 'UVDFC_EOD',
7: 'UVDFC_DISPLAY_PITCH',
8: 'UVDFC_DISPLAY_TILING',
9: 'UVDFC_BITSTREAM_ADDR',
10: 'UVDFC_BITSTREAM_SIZE',
}
UVDFC_FENCE = 0
UVDFC_TRAP = 1
UVDFC_DECODED_ADDR = 2
UVDFC_MBLOCK_ADDR = 3
UVDFC_ITBUF_ADDR = 4
UVDFC_DISPLAY_ADDR = 5
UVDFC_EOD = 6
UVDFC_DISPLAY_PITCH = 7
UVDFC_DISPLAY_TILING = 8
UVDFC_BITSTREAM_ADDR = 9
UVDFC_BITSTREAM_SIZE = 10
UVDFirmwareCommand = ctypes.c_uint32 # enum
__all__ = \
['ABGR_TO_A_BG_G_RB', 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE',
'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ACrYCb16161616_10LSB',
'ACrYCb16161616_10MSB', 'ACrYCb16161616_12LSB',
'ACrYCb16161616_12MSB', 'ACrYCb2101010', 'ACrYCb8888',
'ADDR_CONFIG_16_BANK', 'ADDR_CONFIG_16_PIPE',
'ADDR_CONFIG_1KB_ROW', 'ADDR_CONFIG_1_BANK', 'ADDR_CONFIG_1_GPU',
'ADDR_CONFIG_1_LOWER_PIPES',
'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_1_PIPE',
'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE',
'ADDR_CONFIG_1_SHADER_ENGINE', 'ADDR_CONFIG_2KB_ROW',
'ADDR_CONFIG_2_BANK', 'ADDR_CONFIG_2_GPU',
'ADDR_CONFIG_2_LOWER_PIPES',
'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_2_PIPE',
'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE',
'ADDR_CONFIG_2_SHADER_ENGINE', 'ADDR_CONFIG_32_PIPE',
'ADDR_CONFIG_4KB_ROW', 'ADDR_CONFIG_4_BANK', 'ADDR_CONFIG_4_GPU',
'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_4_PIPE',
'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE',
'ADDR_CONFIG_4_SHADER_ENGINE', 'ADDR_CONFIG_64_PIPE',
'ADDR_CONFIG_8_BANK', 'ADDR_CONFIG_8_GPU',
'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_8_PIPE',
'ADDR_CONFIG_8_SHADER_ENGINE', 'ADDR_CONFIG_BANK_INTERLEAVE_1',
'ADDR_CONFIG_BANK_INTERLEAVE_2', 'ADDR_CONFIG_BANK_INTERLEAVE_4',
'ADDR_CONFIG_BANK_INTERLEAVE_8', 'ADDR_CONFIG_DISABLE_SE',
'ADDR_CONFIG_ENABLE_SE', 'ADDR_CONFIG_GPU_TILE_128',
'ADDR_CONFIG_GPU_TILE_16', 'ADDR_CONFIG_GPU_TILE_32',
'ADDR_CONFIG_GPU_TILE_64', 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB',
'ADDR_CONFIG_PIPE_INTERLEAVE_256B',
'ADDR_CONFIG_PIPE_INTERLEAVE_2KB',
'ADDR_CONFIG_PIPE_INTERLEAVE_512B', 'ADDR_CONFIG_SE_TILE_16',
'ADDR_CONFIG_SE_TILE_32', 'ADDR_NUM_BANKS_BC_BANKS_1',
'ADDR_NUM_BANKS_BC_BANKS_16', 'ADDR_NUM_BANKS_BC_BANKS_2',
'ADDR_NUM_BANKS_BC_BANKS_4', 'ADDR_NUM_BANKS_BC_BANKS_8',
'ADDR_NUM_PIPES_BC_P16', 'ADDR_NUM_PIPES_BC_P8',
'ADDR_SURF_16_BANK', 'ADDR_SURF_2_BANK', 'ADDR_SURF_4_BANK',
'ADDR_SURF_8_BANK', 'ADDR_SURF_BANK_HEIGHT_1',
'ADDR_SURF_BANK_HEIGHT_2', 'ADDR_SURF_BANK_HEIGHT_4',
'ADDR_SURF_BANK_HEIGHT_8', 'ADDR_SURF_BANK_WH_1',
'ADDR_SURF_BANK_WH_2', 'ADDR_SURF_BANK_WH_4',
'ADDR_SURF_BANK_WH_8', 'ADDR_SURF_BANK_WIDTH_1',
'ADDR_SURF_BANK_WIDTH_2', 'ADDR_SURF_BANK_WIDTH_4',
'ADDR_SURF_BANK_WIDTH_8', 'ADDR_SURF_DEPTH_MICRO_TILING',
'ADDR_SURF_DISPLAY_MICRO_TILING', 'ADDR_SURF_MACRO_ASPECT_1',
'ADDR_SURF_MACRO_ASPECT_2', 'ADDR_SURF_MACRO_ASPECT_4',
'ADDR_SURF_MACRO_ASPECT_8', 'ADDR_SURF_MICRO_TILING_DISPLAY',
'ADDR_SURF_MICRO_TILING_NON_DISPLAY', 'ADDR_SURF_P16',
'ADDR_SURF_P16_32x32_16x16', 'ADDR_SURF_P16_32x32_8x16',
'ADDR_SURF_P2', 'ADDR_SURF_P2_RESERVED0',
'ADDR_SURF_P2_RESERVED1', 'ADDR_SURF_P2_RESERVED2',
'ADDR_SURF_P4_16x16', 'ADDR_SURF_P4_16x32', 'ADDR_SURF_P4_32x32',
'ADDR_SURF_P4_8x16', 'ADDR_SURF_P8_16x16_8x16',
'ADDR_SURF_P8_16x32_16x16', 'ADDR_SURF_P8_16x32_8x16',
'ADDR_SURF_P8_32x32_16x16', 'ADDR_SURF_P8_32x32_16x32',
'ADDR_SURF_P8_32x32_8x16', 'ADDR_SURF_P8_32x64_32x32',
'ADDR_SURF_P8_RESERVED0', 'ADDR_SURF_ROTATED_MICRO_TILING',
'ADDR_SURF_SAMPLE_SPLIT_1', 'ADDR_SURF_SAMPLE_SPLIT_2',
'ADDR_SURF_SAMPLE_SPLIT_4', 'ADDR_SURF_SAMPLE_SPLIT_8',
'ADDR_SURF_THICK_MICRO_TILING', 'ADDR_SURF_THIN_MICRO_TILING',
'ADDR_SURF_TILE_SPLIT_128B', 'ADDR_SURF_TILE_SPLIT_1KB',
'ADDR_SURF_TILE_SPLIT_256B', 'ADDR_SURF_TILE_SPLIT_2KB',
'ADDR_SURF_TILE_SPLIT_4KB', 'ADDR_SURF_TILE_SPLIT_512B',
'ADDR_SURF_TILE_SPLIT_64B', 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT',
'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG',
'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG',
'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG',
'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG',
'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL',
'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE',
'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10',
'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12',
'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14',
'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9',
'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT',
'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT',
'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS',
'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER',
'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD',
'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND',
'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS',
'AFMT_AUDIO_PACKET_SENT_DISABLED',
'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM0',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM1',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM2',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM3',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM4',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', 'AFMT_AUDIO_SRC_RESERVED',
'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE',
'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS',
'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK',
'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE',
'AFMT_INTERRUPT_STATUS_CHG_MASK',
'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED',
'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED',
'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED',
'AFMT_VBI_GSP0_INDEX', 'AFMT_VBI_GSP10_INDEX',
'AFMT_VBI_GSP1_INDEX', 'AFMT_VBI_GSP2_INDEX',
'AFMT_VBI_GSP3_INDEX', 'AFMT_VBI_GSP4_INDEX',
'AFMT_VBI_GSP5_INDEX', 'AFMT_VBI_GSP6_INDEX',
'AFMT_VBI_GSP7_INDEX', 'AFMT_VBI_GSP8_INDEX',
'AFMT_VBI_GSP9_INDEX', 'AFMT_VBI_GSP_INDEX',
'ALLOW_SR_ON_TRANS_REQ', 'ALLOW_SR_ON_TRANS_REQ_DISABLE',
'ALLOW_SR_ON_TRANS_REQ_ENABLE', 'ALPHA_DATA_ON_ALPHA_PORT',
'ALPHA_DATA_ON_CB_B_PORT', 'ALPHA_DATA_ON_CR_R_PORT',
'ALPHA_DATA_ON_Y_G_PORT', 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK',
'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 'AM_1D_TILED_THICK',
'AM_1D_TILED_THIN1', 'AM_2D_TILED_THICK', 'AM_2D_TILED_THIN1',
'AM_2D_TILED_XTHICK', 'AM_3D_TILED_THICK', 'AM_3D_TILED_THIN1',
'AM_3D_TILED_XTHICK', 'AM_LINEAR_ALIGNED', 'AM_LINEAR_GENERAL',
'AM_PRT_2D_TILED_THICK', 'AM_PRT_2D_TILED_THIN1',
'AM_PRT_3D_TILED_THICK', 'AM_PRT_3D_TILED_THIN1',
'AM_PRT_TILED_THICK', 'AM_PRT_TILED_THIN1', 'ARGB1555',
'ARGB16161616_10LSB', 'ARGB16161616_10MSB', 'ARGB16161616_12LSB',
'ARGB16161616_12MSB', 'ARGB16161616_FLOAT', 'ARGB16161616_SNORM',
'ARGB16161616_UNORM', 'ARGB2101010', 'ARGB4444', 'ARGB8888',
'ARRAY_1D', 'ARRAY_1D_TILED_THICK', 'ARRAY_1D_TILED_THIN1',
'ARRAY_2D', 'ARRAY_2D_ALT_COLOR', 'ARRAY_2D_ALT_DEPTH',
'ARRAY_2D_COLOR', 'ARRAY_2D_DEPTH', 'ARRAY_2D_TILED_THICK',
'ARRAY_2D_TILED_THIN1', 'ARRAY_2D_TILED_XTHICK', 'ARRAY_3D',
'ARRAY_3D_SLICE', 'ARRAY_3D_SLICE_COLOR', 'ARRAY_3D_TILED_THICK',
'ARRAY_3D_TILED_THIN1', 'ARRAY_3D_TILED_XTHICK',
'ARRAY_COLOR_TILE', 'ARRAY_DEPTH_TILE', 'ARRAY_LINEAR',
'ARRAY_LINEAR_ALIGNED', 'ARRAY_LINEAR_GENERAL', 'ARRAY_MODE',
'ARRAY_PRT_2D_TILED_THICK', 'ARRAY_PRT_2D_TILED_THIN1',
'ARRAY_PRT_3D_TILED_THICK', 'ARRAY_PRT_3D_TILED_THIN1',
'ARRAY_PRT_TILED_THICK', 'ARRAY_PRT_TILED_THIN1', 'ARRAY_TILED',
'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', 'AUDIO_LAYOUT_SELECT',
'AUTOCAL_MODE_AUTOCENTER', 'AUTOCAL_MODE_AUTOREPLICATE',
'AUTOCAL_MODE_AUTOSCALE', 'AUTOCAL_MODE_OFF',
'AYCrCb16161616_10LSB', 'AYCrCb16161616_10MSB',
'AYCrCb16161616_12LSB', 'AYCrCb16161616_12MSB', 'AYCrCb8888',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE',
'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE',
'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE',
'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY',
'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE',
'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO',
'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET',
'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET',
'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9',
'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN',
'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT',
'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE',
'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED',
'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE',
'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED',
'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE',
'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN',
'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF',
'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET',
'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET',
'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC',
'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED',
'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED',
'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES',
'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED',
'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED',
'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET',
'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE',
'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES',
'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED',
'AZ_RIRB_WRITE_POINTER_DO_RESET',
'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET',
'AZ_STATE_CHANGE_STATUS',
'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT',
'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'ArrayMode',
'BANK_HEIGHT', 'BANK_WIDTH', 'BGR101111_FIX', 'BGR101111_FLOAT',
'BGR565', 'BGRA_TO_BG_G_RB_A', 'BINNER_BREAK_BATCH',
'BINNER_DROP', 'BINNER_DROP_ASSERT', 'BINNER_PIPELINE',
'BINNING_ALLOWED', 'BIN_CONF_OVERRIDE_CHECK', 'BIN_MAP_MODE_NONE',
'BIN_MAP_MODE_POPS', 'BIN_MAP_MODE_RTA_INDEX',
'BIN_SIZE_128_PIXELS', 'BIN_SIZE_256_PIXELS',
'BIN_SIZE_32_PIXELS', 'BIN_SIZE_512_PIXELS', 'BIN_SIZE_64_PIXELS',
'BITS_31_0', 'BITS_32_1', 'BITS_33_2', 'BITS_34_3', 'BITS_35_4',
'BITS_36_5', 'BITS_37_6', 'BITS_38_7', 'BLEND_BOTH_INV_SRC_ALPHA',
'BLEND_BOTH_SRC_ALPHA', 'BLEND_CONSTANT_ALPHA',
'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR',
'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE',
'BLEND_ONE_MINUS_CONSTANT_ALPHA',
'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA',
'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA',
'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1',
'BLEND_OPT_PRESERVE_A1_IGNORE_A0',
'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE',
'BLEND_OPT_PRESERVE_C0_IGNORE_C1',
'BLEND_OPT_PRESERVE_C1_IGNORE_C0',
'BLEND_OPT_PRESERVE_NONE_IGNORE_A0',
'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL',
'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA',
'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE',
'BLEND_SRC_COLOR', 'BLEND_ZERO', 'BLOCK_CONTEXT_DONE', 'BOTH_EYE',
'BOTTOM_OF_PIPE_TS', 'BREAK_BATCH', 'BUF_DATA_FORMAT',
'BUF_DATA_FORMAT_10_10_10_2', 'BUF_DATA_FORMAT_10_11_11',
'BUF_DATA_FORMAT_11_11_10', 'BUF_DATA_FORMAT_16',
'BUF_DATA_FORMAT_16_16', 'BUF_DATA_FORMAT_16_16_16_16',
'BUF_DATA_FORMAT_2_10_10_10', 'BUF_DATA_FORMAT_32',
'BUF_DATA_FORMAT_32_32', 'BUF_DATA_FORMAT_32_32_32',
'BUF_DATA_FORMAT_32_32_32_32', 'BUF_DATA_FORMAT_8',
'BUF_DATA_FORMAT_8_8', 'BUF_DATA_FORMAT_8_8_8_8',
'BUF_DATA_FORMAT_INVALID', 'BUF_DATA_FORMAT_RESERVED_15',
'BUF_FMT', 'BUF_FMT_10_10_10_2_SINT', 'BUF_FMT_10_10_10_2_SNORM',
'BUF_FMT_10_10_10_2_SSCALED', 'BUF_FMT_10_10_10_2_UINT',
'BUF_FMT_10_10_10_2_UNORM', 'BUF_FMT_10_10_10_2_USCALED',
'BUF_FMT_10_11_11_FLOAT', 'BUF_FMT_10_11_11_SINT',
'BUF_FMT_10_11_11_SNORM', 'BUF_FMT_10_11_11_SSCALED',
'BUF_FMT_10_11_11_UINT', 'BUF_FMT_10_11_11_UNORM',
'BUF_FMT_10_11_11_USCALED', 'BUF_FMT_11_11_10_FLOAT',
'BUF_FMT_11_11_10_SINT', 'BUF_FMT_11_11_10_SNORM',
'BUF_FMT_11_11_10_SSCALED', 'BUF_FMT_11_11_10_UINT',
'BUF_FMT_11_11_10_UNORM', 'BUF_FMT_11_11_10_USCALED',
'BUF_FMT_16_16_16_16_FLOAT', 'BUF_FMT_16_16_16_16_SINT',
'BUF_FMT_16_16_16_16_SNORM', 'BUF_FMT_16_16_16_16_SSCALED',
'BUF_FMT_16_16_16_16_UINT', 'BUF_FMT_16_16_16_16_UNORM',
'BUF_FMT_16_16_16_16_USCALED', 'BUF_FMT_16_16_FLOAT',
'BUF_FMT_16_16_SINT', 'BUF_FMT_16_16_SNORM',
'BUF_FMT_16_16_SSCALED', 'BUF_FMT_16_16_UINT',
'BUF_FMT_16_16_UNORM', 'BUF_FMT_16_16_USCALED',
'BUF_FMT_16_FLOAT', 'BUF_FMT_16_SINT', 'BUF_FMT_16_SNORM',
'BUF_FMT_16_SSCALED', 'BUF_FMT_16_UINT', 'BUF_FMT_16_UNORM',
'BUF_FMT_16_USCALED', 'BUF_FMT_2_10_10_10_SINT',
'BUF_FMT_2_10_10_10_SNORM', 'BUF_FMT_2_10_10_10_SSCALED',
'BUF_FMT_2_10_10_10_UINT', 'BUF_FMT_2_10_10_10_UNORM',
'BUF_FMT_2_10_10_10_USCALED', 'BUF_FMT_32_32_32_32_FLOAT',
'BUF_FMT_32_32_32_32_SINT', 'BUF_FMT_32_32_32_32_UINT',
'BUF_FMT_32_32_32_FLOAT', 'BUF_FMT_32_32_32_SINT',
'BUF_FMT_32_32_32_UINT', 'BUF_FMT_32_32_FLOAT',
'BUF_FMT_32_32_SINT', 'BUF_FMT_32_32_UINT', 'BUF_FMT_32_FLOAT',
'BUF_FMT_32_SINT', 'BUF_FMT_32_UINT', 'BUF_FMT_8_8_8_8_SINT',
'BUF_FMT_8_8_8_8_SNORM', 'BUF_FMT_8_8_8_8_SSCALED',
'BUF_FMT_8_8_8_8_UINT', 'BUF_FMT_8_8_8_8_UNORM',
'BUF_FMT_8_8_8_8_USCALED', 'BUF_FMT_8_8_SINT',
'BUF_FMT_8_8_SNORM', 'BUF_FMT_8_8_SSCALED', 'BUF_FMT_8_8_UINT',
'BUF_FMT_8_8_UNORM', 'BUF_FMT_8_8_USCALED', 'BUF_FMT_8_SINT',
'BUF_FMT_8_SNORM', 'BUF_FMT_8_SSCALED', 'BUF_FMT_8_UINT',
'BUF_FMT_8_UNORM', 'BUF_FMT_8_USCALED', 'BUF_FMT_INVALID',
'BUF_FMT_RESERVED_100', 'BUF_FMT_RESERVED_101',
'BUF_FMT_RESERVED_102', 'BUF_FMT_RESERVED_103',
'BUF_FMT_RESERVED_104', 'BUF_FMT_RESERVED_105',
'BUF_FMT_RESERVED_106', 'BUF_FMT_RESERVED_107',
'BUF_FMT_RESERVED_108', 'BUF_FMT_RESERVED_109',
'BUF_FMT_RESERVED_110', 'BUF_FMT_RESERVED_111',
'BUF_FMT_RESERVED_112', 'BUF_FMT_RESERVED_113',
'BUF_FMT_RESERVED_114', 'BUF_FMT_RESERVED_115',
'BUF_FMT_RESERVED_116', 'BUF_FMT_RESERVED_117',
'BUF_FMT_RESERVED_118', 'BUF_FMT_RESERVED_119',
'BUF_FMT_RESERVED_120', 'BUF_FMT_RESERVED_121',
'BUF_FMT_RESERVED_122', 'BUF_FMT_RESERVED_123',
'BUF_FMT_RESERVED_124', 'BUF_FMT_RESERVED_125',
'BUF_FMT_RESERVED_126', 'BUF_FMT_RESERVED_127',
'BUF_FMT_RESERVED_78', 'BUF_FMT_RESERVED_79',
'BUF_FMT_RESERVED_80', 'BUF_FMT_RESERVED_81',
'BUF_FMT_RESERVED_82', 'BUF_FMT_RESERVED_83',
'BUF_FMT_RESERVED_84', 'BUF_FMT_RESERVED_85',
'BUF_FMT_RESERVED_86', 'BUF_FMT_RESERVED_87',
'BUF_FMT_RESERVED_88', 'BUF_FMT_RESERVED_89',
'BUF_FMT_RESERVED_90', 'BUF_FMT_RESERVED_91',
'BUF_FMT_RESERVED_92', 'BUF_FMT_RESERVED_93',
'BUF_FMT_RESERVED_94', 'BUF_FMT_RESERVED_95',
'BUF_FMT_RESERVED_96', 'BUF_FMT_RESERVED_97',
'BUF_FMT_RESERVED_98', 'BUF_FMT_RESERVED_99', 'BUF_NUM_FORMAT',
'BUF_NUM_FORMAT_FLOAT', 'BUF_NUM_FORMAT_SINT',
'BUF_NUM_FORMAT_SNORM', 'BUF_NUM_FORMAT_SNORM_NZ',
'BUF_NUM_FORMAT_SSCALED', 'BUF_NUM_FORMAT_UINT',
'BUF_NUM_FORMAT_UNORM', 'BUF_NUM_FORMAT_USCALED', 'BYPASS_EN',
'BYPASS_GAMUT', 'BYPASS_ICSC', 'BankHeight', 'BankInterleaveSize',
'BankSwapBytes', 'BankTiling', 'BankWidth', 'BankWidthHeight',
'BinEventCntl', 'BinMapMode', 'BinSizeExtend', 'BinningMode',
'BlendOp', 'BlendOpt', 'CACHE_BYPASS', 'CACHE_FLUSH',
'CACHE_FLUSH_AND_INV_EVENT', 'CACHE_FLUSH_AND_INV_TS_EVENT',
'CACHE_FLUSH_TS', 'CACHE_LRU_RD', 'CACHE_LRU_WR', 'CACHE_NOA',
'CACHE_STREAM', 'CBMode', 'CBPerfClearFilterSel',
'CBPerfOpFilterSel', 'CBPerfSel', 'CB_B_DATA_ON_ALPHA_PORT',
'CB_B_DATA_ON_CB_B_PORT', 'CB_B_DATA_ON_CR_R_PORT',
'CB_B_DATA_ON_Y_G_PORT', 'CB_DCC_DECOMPRESS', 'CB_DECOMPRESS',
'CB_DISABLE', 'CB_ELIMINATE_FAST_CLEAR', 'CB_FMASK_DECOMPRESS',
'CB_NORMAL', 'CB_PERF_CLEAR_FILTER_SEL_CLEAR',
'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR',
'CB_PERF_OP_FILTER_SEL_DECOMPRESS',
'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR',
'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS',
'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION',
'CB_PERF_OP_FILTER_SEL_RESOLVE',
'CB_PERF_OP_FILTER_SEL_WRITE_ONLY',
'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL',
'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', 'CB_PERF_SEL_BUSY',
'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY',
'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB',
'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY',
'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB',
'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY',
'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB',
'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY',
'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB',
'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY',
'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD',
'CB_PERF_SEL_CC_BC_CS_FRAG_VALID',
'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL',
'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED',
'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL',
'CB_PERF_SEL_CC_CACHE_FLUSH', 'CB_PERF_SEL_CC_CACHE_HIT',
'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL',
'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC',
'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL',
'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL',
'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL',
'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED',
'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL',
'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED',
'CB_PERF_SEL_CC_CACHE_TAG_MISS',
'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION',
'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL',
'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6',
'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7',
'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN',
'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT',
'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN',
'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2',
'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED',
'CB_PERF_SEL_CC_DCC_RDREQ_STALL',
'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL',
'CB_PERF_SEL_CC_EVENFIFO_STUTTER_STALL',
'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY',
'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB',
'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY',
'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB',
'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY',
'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB',
'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY',
'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB',
'CB_PERF_SEL_CC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_CC_MC_EARLY_WRITE_RETURN',
'CB_PERF_SEL_CC_MC_READ_REQUEST',
'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_CC_MC_WRITE_ACK64B',
'CB_PERF_SEL_CC_MC_WRITE_REQUEST',
'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_CC_MC_WRITE_REQUEST_PARTIAL',
'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL',
'CB_PERF_SEL_CC_ODDFIFO_STUTTER_STALL',
'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY',
'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB',
'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY',
'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB',
'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY',
'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB',
'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY',
'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB',
'CB_PERF_SEL_CC_RB_FULL', 'CB_PERF_SEL_CC_SF_FULL',
'CB_PERF_SEL_CC_SURFACE_SYNC', 'CB_PERF_SEL_CMASK_READ_DATA_0xC',
'CB_PERF_SEL_CMASK_READ_DATA_0xD',
'CB_PERF_SEL_CMASK_READ_DATA_0xE',
'CB_PERF_SEL_CMASK_READ_DATA_0xF',
'CB_PERF_SEL_CMASK_WRITE_DATA_0xC',
'CB_PERF_SEL_CMASK_WRITE_DATA_0xD',
'CB_PERF_SEL_CMASK_WRITE_DATA_0xE',
'CB_PERF_SEL_CMASK_WRITE_DATA_0xF',
'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY',
'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL',
'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED',
'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL',
'CB_PERF_SEL_CM_CACHE_FLUSH', 'CB_PERF_SEL_CM_CACHE_HIT',
'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL',
'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL',
'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL',
'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL',
'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED',
'CB_PERF_SEL_CM_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CM_CACHE_STALL',
'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED',
'CB_PERF_SEL_CM_CACHE_TAG_MISS',
'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL',
'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY',
'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB',
'CB_PERF_SEL_CM_FC_TILE_VALID_READY',
'CB_PERF_SEL_CM_FC_TILE_VALID_READYB',
'CB_PERF_SEL_CM_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_CM_MC_EARLY_WRITE_RETURN',
'CB_PERF_SEL_CM_MC_READ_REQUEST',
'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_CM_MC_WRITE_ACK64B',
'CB_PERF_SEL_CM_MC_WRITE_REQUEST',
'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_CM_TQ_FIFO_STUTTER_STALL',
'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL',
'CB_PERF_SEL_CM_TQ_FULL', 'CB_PERF_SEL_CORE_SCLK_VLD',
'CB_PERF_SEL_DB_CB_CONTEXT_DONE', 'CB_PERF_SEL_DB_CB_EOP_DONE',
'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY',
'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB',
'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY',
'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB',
'CB_PERF_SEL_DB_CB_TILE_TILENOTEVENT',
'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY',
'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB',
'CB_PERF_SEL_DB_CB_TILE_VALID_READY',
'CB_PERF_SEL_DB_CB_TILE_VALID_READYB',
'CB_PERF_SEL_DC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_DC_MC_EARLY_WRITE_RETURN',
'CB_PERF_SEL_DC_MC_WRITE_ACK64B', 'CB_PERF_SEL_DRAWN_BUSY',
'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD',
'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_DRAWN_TILE',
'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT',
'CB_PERF_SEL_EVENT', 'CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS',
'CB_PERF_SEL_EVENT_CACHE_FLUSH',
'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT',
'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT',
'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS',
'CB_PERF_SEL_EVENT_CONTEXT_DONE',
'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS',
'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META',
'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_PIXEL_DATA',
'CB_PERF_SEL_EVENT_FLUSH_AND_INV_DB_DATA_TS',
'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT',
'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY',
'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL',
'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED',
'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL',
'CB_PERF_SEL_FC_CACHE_FLUSH', 'CB_PERF_SEL_FC_CACHE_HIT',
'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL',
'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL',
'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL',
'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL',
'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED',
'CB_PERF_SEL_FC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_FC_CACHE_STALL',
'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED',
'CB_PERF_SEL_FC_CACHE_TAG_MISS',
'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL',
'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY',
'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB',
'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY',
'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB',
'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY',
'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB',
'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY',
'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB',
'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL',
'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED',
'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL',
'CB_PERF_SEL_FC_DCC_CACHE_FLUSH', 'CB_PERF_SEL_FC_DCC_CACHE_HIT',
'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL',
'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL',
'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL',
'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL',
'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED',
'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS',
'CB_PERF_SEL_FC_DCC_CACHE_STALL',
'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED',
'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS',
'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL',
'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR',
'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT',
'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS',
'CB_PERF_SEL_FC_DOC_IS_STALLED',
'CB_PERF_SEL_FC_DOC_MRTS_COMBINED',
'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED',
'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR',
'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS',
'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS',
'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS',
'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT',
'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS',
'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL',
'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS',
'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL',
'CB_PERF_SEL_FC_KEYID_STUTTER_STALL',
'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST',
'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST',
'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_FC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_FC_MC_EARLY_WRITE_RETURN',
'CB_PERF_SEL_FC_MC_READ_REQUEST',
'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_FC_MC_WRITE_ACK64B',
'CB_PERF_SEL_FC_MC_WRITE_REQUEST',
'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED',
'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL',
'CB_PERF_SEL_FC_QUAD_STUTTER_STALL',
'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL',
'CB_PERF_SEL_FC_SEQUENCER_CLEAR',
'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR',
'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE',
'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS',
'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL',
'CB_PERF_SEL_FC_TILE_STUTTER_STALL',
'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL',
'CB_PERF_SEL_FOP_FMASK_RAW_STALL',
'CB_PERF_SEL_FOP_IN_VALIDB_READY',
'CB_PERF_SEL_FOP_IN_VALIDB_READYB',
'CB_PERF_SEL_FOP_IN_VALID_READY',
'CB_PERF_SEL_FOP_IN_VALID_READYB',
'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_FLOAT_8PIX',
'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_SIGNED_8PIX',
'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_UNSIGNED_8PIX',
'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32BPP_8PIX',
'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR',
'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR',
'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR',
'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R',
'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR',
'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR',
'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR',
'CB_PERF_SEL_LQUAD_NO_TILE',
'CB_PERF_SEL_MERGE_PIXELS_WITH_BLEND_ENABLED',
'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY',
'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB',
'CB_PERF_SEL_NACK_CC_READ', 'CB_PERF_SEL_NACK_CC_WRITE',
'CB_PERF_SEL_NACK_CM_READ', 'CB_PERF_SEL_NACK_CM_WRITE',
'CB_PERF_SEL_NACK_DC_READ', 'CB_PERF_SEL_NACK_DC_WRITE',
'CB_PERF_SEL_NACK_FC_READ', 'CB_PERF_SEL_NACK_FC_WRITE',
'CB_PERF_SEL_NONE', 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT',
'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS',
'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS',
'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS',
'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS',
'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS',
'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS',
'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED',
'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS',
'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS',
'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST',
'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED',
'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED',
'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE',
'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE',
'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID',
'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL',
'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT',
'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK',
'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK',
'CB_PERF_SEL_QUAD_READS_FRAGMENT_0',
'CB_PERF_SEL_QUAD_READS_FRAGMENT_1',
'CB_PERF_SEL_QUAD_READS_FRAGMENT_2',
'CB_PERF_SEL_QUAD_READS_FRAGMENT_3',
'CB_PERF_SEL_QUAD_READS_FRAGMENT_4',
'CB_PERF_SEL_QUAD_READS_FRAGMENT_5',
'CB_PERF_SEL_QUAD_READS_FRAGMENT_6',
'CB_PERF_SEL_QUAD_READS_FRAGMENT_7',
'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT',
'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS',
'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS',
'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS',
'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS',
'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS',
'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS',
'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0',
'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1',
'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2',
'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3',
'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4',
'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5',
'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6',
'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7',
'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH',
'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT',
'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT',
'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD',
'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS',
'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK',
'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING',
'CB_PERF_SEL_RBP_SPLIT_MICROTILE',
'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK',
'CB_PERF_SEL_REG_SCLK0_VLD', 'CB_PERF_SEL_REG_SCLK1_VLD',
'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY',
'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT', 'CB_RESERVED',
'CB_RESOLVE',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL',
'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY',
'CHA_PERF_SEL', 'CHA_PERF_SEL_ARB_REQUESTS', 'CHA_PERF_SEL_BUSY',
'CHA_PERF_SEL_CYCLE', 'CHA_PERF_SEL_IO_32B_WDS_CHC0',
'CHA_PERF_SEL_IO_32B_WDS_CHC1', 'CHA_PERF_SEL_IO_32B_WDS_CHC2',
'CHA_PERF_SEL_IO_32B_WDS_CHC3', 'CHA_PERF_SEL_IO_32B_WDS_CHC4',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC0',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC1',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC2',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC3',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC4',
'CHA_PERF_SEL_MEM_32B_WDS_CHC0', 'CHA_PERF_SEL_MEM_32B_WDS_CHC1',
'CHA_PERF_SEL_MEM_32B_WDS_CHC2', 'CHA_PERF_SEL_MEM_32B_WDS_CHC3',
'CHA_PERF_SEL_MEM_32B_WDS_CHC4',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', 'CHA_PERF_SEL_REQUEST_CHC0',
'CHA_PERF_SEL_REQUEST_CHC1', 'CHA_PERF_SEL_REQUEST_CHC2',
'CHA_PERF_SEL_REQUEST_CHC3', 'CHA_PERF_SEL_REQUEST_CHC4',
'CHA_PERF_SEL_REQUEST_CHC5', 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL',
'CHA_PERF_SEL_STALL_CHC0', 'CHA_PERF_SEL_STALL_CHC1',
'CHA_PERF_SEL_STALL_CHC2', 'CHA_PERF_SEL_STALL_CHC3',
'CHA_PERF_SEL_STALL_CHC4', 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0',
'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1',
'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2',
'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3',
'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', 'CHCG_PERF_SEL',
'CHCG_PERF_SEL_CORE_REG_SCLK_VLD', 'CHCG_PERF_SEL_CYCLE',
'CHCG_PERF_SEL_GATE_EN1', 'CHCG_PERF_SEL_GATE_EN2',
'CHCG_PERF_SEL_REQ', 'CHCG_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES',
'CHCG_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES', 'CHC_PERF_SEL',
'CHC_PERF_SEL_CORE_REG_SCLK_VLD', 'CHC_PERF_SEL_CYCLE',
'CHC_PERF_SEL_GATE_EN1', 'CHC_PERF_SEL_GATE_EN2',
'CHC_PERF_SEL_REQ', 'CHC_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES',
'CHC_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES', 'CHUNK_SIZE',
'CHUNK_SIZE_16KB', 'CHUNK_SIZE_1KB', 'CHUNK_SIZE_2KB',
'CHUNK_SIZE_32KB', 'CHUNK_SIZE_4KB', 'CHUNK_SIZE_64KB',
'CHUNK_SIZE_8KB', 'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE',
'CLKGATE_SM_MODE', 'CLOCK_BRANCH_SOFT_RESET',
'CLOCK_BRANCH_SOFT_RESET_FORCE', 'CLOCK_BRANCH_SOFT_RESET_NOOP',
'CLOCK_GATING_DISABLE', 'CLOCK_GATING_DISABLED',
'CLOCK_GATING_DISABLED_IN_DCO', 'CLOCK_GATING_DISABLE_ENUM',
'CLOCK_GATING_DISABLE_ENUM_DISABLED',
'CLOCK_GATING_DISABLE_ENUM_ENABLED', 'CLOCK_GATING_EN',
'CLOCK_GATING_ENABLE', 'CLOCK_GATING_ENABLED',
'CLOCK_GATING_ENABLED_IN_DCO', 'CMASK_ADDR_COMPATIBLE',
'CMASK_ADDR_LINEAR', 'CMASK_ADDR_TILED', 'CMASK_ALPHA0_FRAG1',
'CMASK_ALPHA0_FRAG2', 'CMASK_ALPHA0_FRAG4', 'CMASK_ALPHA0_FRAGS',
'CMASK_ALPHA1_FRAG1', 'CMASK_ALPHA1_FRAG2', 'CMASK_ALPHA1_FRAG4',
'CMASK_ALPHA1_FRAGS', 'CMASK_ALPHAX_FRAG1', 'CMASK_ALPHAX_FRAG2',
'CMASK_ALPHAX_FRAG4', 'CMASK_ALPHAX_FRAGS', 'CMASK_ANY_EXPANDED',
'CMASK_CLEAR_ALL', 'CMASK_CLEAR_NONE', 'CMASK_CLEAR_ONE',
'CMASK_CLR00_F0', 'CMASK_CLR00_F1', 'CMASK_CLR00_F2',
'CMASK_CLR00_FX', 'CMASK_CLR01_F0', 'CMASK_CLR01_F1',
'CMASK_CLR01_F2', 'CMASK_CLR01_FX', 'CMASK_CLR10_F0',
'CMASK_CLR10_F1', 'CMASK_CLR10_F2', 'CMASK_CLR10_FX',
'CMASK_CLR11_F0', 'CMASK_CLR11_F1', 'CMASK_CLR11_F2',
'CMASK_CLR11_FX', 'CMC_3DLUT_17CUBE', 'CMC_3DLUT_30BIT',
'CMC_3DLUT_30BIT_ENUM', 'CMC_3DLUT_36BIT', 'CMC_3DLUT_9CUBE',
'CMC_3DLUT_RAM_SEL', 'CMC_3DLUT_SIZE_ENUM',
'CMC_LUT_2CFG_MEMORY_A', 'CMC_LUT_2CFG_MEMORY_B',
'CMC_LUT_2CFG_NO_MEMORY', 'CMC_LUT_2_CONFIG_ENUM',
'CMC_LUT_2_MODE_BYPASS', 'CMC_LUT_2_MODE_ENUM',
'CMC_LUT_2_MODE_RAMA_LUT', 'CMC_LUT_2_MODE_RAMB_LUT',
'CMC_LUT_NUM_SEG', 'CMC_LUT_RAM_SEL', 'CMC_RAM0_ACCESS',
'CMC_RAM1_ACCESS', 'CMC_RAM2_ACCESS', 'CMC_RAM3_ACCESS',
'CMC_RAMA_ACCESS', 'CMC_RAMB_ACCESS', 'CMC_SEGMENTS_1',
'CMC_SEGMENTS_128', 'CMC_SEGMENTS_16', 'CMC_SEGMENTS_2',
'CMC_SEGMENTS_32', 'CMC_SEGMENTS_4', 'CMC_SEGMENTS_64',
'CMC_SEGMENTS_8', 'CM_BYPASS', 'CM_COEF_FORMAT_ENUM',
'CM_DATA_SIGNED', 'CM_DISABLE', 'CM_EN', 'CM_ENABLE',
'CM_GAMUT_REMAP_MODE_ENUM', 'CM_ICSC_MODE_ENUM',
'CM_LUT_2_CONFIG_ENUM', 'CM_LUT_2_MODE_ENUM',
'CM_LUT_4_CONFIG_ENUM', 'CM_LUT_4_MODE_ENUM', 'CM_LUT_NUM_SEG',
'CM_LUT_RAM_SEL', 'CM_NOT_PENDING', 'CM_PENDING',
'CM_WRITE_BASE_ONLY', 'CM_YES_PENDING', 'CNVC_BYPASS',
'CNVC_BYPASS_DISABLE', 'CNVC_BYPASS_EN', 'CNVC_DIS', 'CNVC_EN',
'CNVC_ENABLE', 'CNVC_NOT_PENDING', 'CNVC_PENDING', 'CNVC_ROUND',
'CNVC_TRUNCATE', 'CNVC_YES_PENDING', 'CNV_CSC_BYPASS_ENUM',
'CNV_CSC_BYPASS_NEG', 'CNV_CSC_BYPASS_POS', 'CNV_EYE_SELECT',
'CNV_FRAME_CAPTURE_DISABLE', 'CNV_FRAME_CAPTURE_ENABLE',
'CNV_FRAME_CAPTURE_EN_ENUM', 'CNV_FRAME_CAPTURE_RATE_0',
'CNV_FRAME_CAPTURE_RATE_1', 'CNV_FRAME_CAPTURE_RATE_2',
'CNV_FRAME_CAPTURE_RATE_3', 'CNV_FRAME_CAPTURE_RATE_ENUM',
'CNV_INTERLACED_FIELD_ORDER_BOT',
'CNV_INTERLACED_FIELD_ORDER_ENUM',
'CNV_INTERLACED_FIELD_ORDER_TOP', 'CNV_INTERLACED_MODE_ENUM',
'CNV_INTERLACED_MODE_INTERLACED',
'CNV_INTERLACED_MODE_PROGRESSIVE', 'CNV_NEW_CONTENT_ENUM',
'CNV_NEW_CONTENT_NEG', 'CNV_NEW_CONTENT_POS', 'CNV_OUT_BPC_10BPC',
'CNV_OUT_BPC_8BPC', 'CNV_OUT_BPC_ENUM',
'CNV_STEREO_POLARITY_ENUM', 'CNV_STEREO_POLARITY_LEFT',
'CNV_STEREO_POLARITY_RIGHT', 'CNV_STEREO_SPLIT_DISABLE',
'CNV_STEREO_SPLIT_ENABLE', 'CNV_STEREO_SPLIT_ENUM',
'CNV_STEREO_TYPE_ENUM', 'CNV_STEREO_TYPE_FRAME_SEQUENTIAL',
'CNV_STEREO_TYPE_RESERVED0', 'CNV_STEREO_TYPE_RESERVED1',
'CNV_STEREO_TYPE_RESERVED2', 'CNV_TEST_CRC_CONT_DISABLE',
'CNV_TEST_CRC_CONT_ENABLE', 'CNV_TEST_CRC_CONT_EN_ENUM',
'CNV_TEST_CRC_DISABLE', 'CNV_TEST_CRC_ENABLE',
'CNV_TEST_CRC_EN_ENUM', 'CNV_UPDATE_LOCK', 'CNV_UPDATE_LOCK_ENUM',
'CNV_UPDATE_PENDING_ENUM', 'CNV_UPDATE_PENDING_NEG',
'CNV_UPDATE_PENDING_POS', 'CNV_UPDATE_UNLOCK',
'CNV_WINDOW_CROP_DISABLE', 'CNV_WINDOW_CROP_ENABLE',
'CNV_WINDOW_CROP_EN_ENUM', 'COEF_ICSC', 'COEF_ICSC_B',
'COEF_RAM_SELECT_BACK', 'COEF_RAM_SELECT_CURRENT',
'COEF_RAM_SELECT_RD', 'COLOR_10_10_10_2', 'COLOR_10_11_11',
'COLOR_11_11_10', 'COLOR_16', 'COLOR_16_16', 'COLOR_16_16_16_16',
'COLOR_1_5_5_5', 'COLOR_24BIT_1BIT_AND',
'COLOR_24BIT_8BIT_ALPHA_PREMULT',
'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', 'COLOR_24_8',
'COLOR_2_10_10_10', 'COLOR_2_10_10_10_6E4', 'COLOR_32',
'COLOR_32_32', 'COLOR_32_32_32_32', 'COLOR_4_4_4_4',
'COLOR_5_5_5_1', 'COLOR_5_6_5', 'COLOR_64BIT_FP_PREMULT',
'COLOR_64BIT_FP_UNPREMULT', 'COLOR_8', 'COLOR_8_24', 'COLOR_8_8',
'COLOR_8_8_8_8', 'COLOR_INVALID', 'COLOR_KEYER_MODE',
'COLOR_RESERVED_13', 'COLOR_RESERVED_15', 'COLOR_RESERVED_23',
'COLOR_RESERVED_24', 'COLOR_RESERVED_25', 'COLOR_RESERVED_26',
'COLOR_RESERVED_27', 'COLOR_RESERVED_28', 'COLOR_RESERVED_29',
'COLOR_RESERVED_30', 'COLOR_X24_8_32_FLOAT', 'COMB_DST_MINUS_SRC',
'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', 'COMB_MIN_DST_SRC',
'COMB_SRC_MINUS_DST', 'CONFIG_128B_SWAPS', 'CONFIG_1KB_ROW',
'CONFIG_1KB_ROW_OPT', 'CONFIG_1KB_SPLIT', 'CONFIG_1KB_SWAPS',
'CONFIG_1_PIPE', 'CONFIG_256B_GROUP', 'CONFIG_256B_SWAPS',
'CONFIG_2KB_ROW', 'CONFIG_2KB_ROW_OPT', 'CONFIG_2KB_SPLIT',
'CONFIG_2_PIPE', 'CONFIG_4KB_ROW', 'CONFIG_4KB_ROW_OPT',
'CONFIG_4KB_SPLIT', 'CONFIG_4_BANK', 'CONFIG_4_PIPE',
'CONFIG_512B_GROUP', 'CONFIG_512B_SWAPS', 'CONFIG_8KB_ROW',
'CONFIG_8KB_ROW_OPT', 'CONFIG_8KB_SPLIT', 'CONFIG_8_BANK',
'CONFIG_8_PIPE', 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START',
'CONFIG_SPACE2_END', 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END',
'CONFIG_SPACE_START', 'CONTEXT_DONE', 'CONTEXT_SPACE_END',
'CONTEXT_SPACE_START', 'CONTEXT_SUSPEND',
'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET',
'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET',
'CORB_READ_POINTER_RESET',
'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET',
'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0',
'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_LATENCY_STATS_SEL',
'CPC_LATENCY_STATS_SEL_INVAL_LAST',
'CPC_LATENCY_STATS_SEL_INVAL_MAX',
'CPC_LATENCY_STATS_SEL_INVAL_MIN',
'CPC_LATENCY_STATS_SEL_XACK_LAST',
'CPC_LATENCY_STATS_SEL_XACK_MAX',
'CPC_LATENCY_STATS_SEL_XACK_MIN',
'CPC_LATENCY_STATS_SEL_XNACK_LAST',
'CPC_LATENCY_STATS_SEL_XNACK_MAX',
'CPC_LATENCY_STATS_SEL_XNACK_MIN', 'CPC_PERFCOUNT_SEL',
'CPC_PERF_SEL_ALWAYS_COUNT', 'CPC_PERF_SEL_CPC_GCRIU_BUSY',
'CPC_PERF_SEL_CPC_GCRIU_IDLE', 'CPC_PERF_SEL_CPC_GCRIU_STALL',
'CPC_PERF_SEL_CPC_STAT_BUSY', 'CPC_PERF_SEL_CPC_STAT_IDLE',
'CPC_PERF_SEL_CPC_STAT_STALL', 'CPC_PERF_SEL_CPC_TCIU_BUSY',
'CPC_PERF_SEL_CPC_TCIU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY',
'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_STALL',
'CPC_PERF_SEL_CPC_UTCL2IU_XACK', 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK',
'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE',
'CPC_PERF_SEL_ME1_DC0_SPI_BUSY',
'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ',
'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ',
'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE',
'CPC_PERF_SEL_ME2_DC1_SPI_BUSY',
'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ',
'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ',
'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT',
'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS',
'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE',
'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE',
'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION',
'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE',
'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE',
'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION',
'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM',
'CPF_LATENCY_STATS_SEL', 'CPF_LATENCY_STATS_SEL_INVAL_LAST',
'CPF_LATENCY_STATS_SEL_INVAL_MAX',
'CPF_LATENCY_STATS_SEL_INVAL_MIN',
'CPF_LATENCY_STATS_SEL_READ_LAST',
'CPF_LATENCY_STATS_SEL_READ_MAX',
'CPF_LATENCY_STATS_SEL_READ_MIN',
'CPF_LATENCY_STATS_SEL_XACK_LAST',
'CPF_LATENCY_STATS_SEL_XACK_MAX',
'CPF_LATENCY_STATS_SEL_XACK_MIN',
'CPF_LATENCY_STATS_SEL_XNACK_LAST',
'CPF_LATENCY_STATS_SEL_XNACK_MAX',
'CPF_LATENCY_STATS_SEL_XNACK_MIN', 'CPF_PERFCOUNTWINDOW_SEL',
'CPF_PERFCOUNT_SEL', 'CPF_PERFWINDOW_SEL_CSF',
'CPF_PERFWINDOW_SEL_HQD1', 'CPF_PERFWINDOW_SEL_HQD2',
'CPF_PERFWINDOW_SEL_RDMA', 'CPF_PERFWINDOW_SEL_RWPP',
'CPF_PERF_SEL_ALWAYS_COUNT',
'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION',
'CPF_PERF_SEL_CPF_GCRIU_BUSY', 'CPF_PERF_SEL_CPF_GCRIU_IDLE',
'CPF_PERF_SEL_CPF_GCRIU_STALL', 'CPF_PERF_SEL_CPF_STAT_BUSY',
'CPF_PERF_SEL_CPF_STAT_IDLE', 'CPF_PERF_SEL_CPF_STAT_STALL',
'CPF_PERF_SEL_CPF_TCIU_BUSY', 'CPF_PERF_SEL_CPF_TCIU_IDLE',
'CPF_PERF_SEL_CPF_TCIU_STALL', 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY',
'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', 'CPF_PERF_SEL_CPF_UTCL2IU_STALL',
'CPF_PERF_SEL_CPF_UTCL2IU_XACK', 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK',
'CPF_PERF_SEL_CPG_TCIU_STALL',
'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING',
'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS',
'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR',
'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR',
'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID',
'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION',
'CPF_PERF_SEL_GRBM_DWORDS_SENT',
'CPF_PERF_SEL_GUS_READ_REQUEST_SEND',
'CPF_PERF_SEL_GUS_WRITE_REQUEST_SEND',
'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS',
'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE',
'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE',
'CPF_PERF_SEL_REGISTER_CLOCK_VALID',
'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT',
'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE',
'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS',
'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPF_TAG_RAM',
'CPG_LATENCY_STATS_SEL', 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST',
'CPG_LATENCY_STATS_SEL_ATOMIC_MAX',
'CPG_LATENCY_STATS_SEL_ATOMIC_MIN',
'CPG_LATENCY_STATS_SEL_INVAL_LAST',
'CPG_LATENCY_STATS_SEL_INVAL_MAX',
'CPG_LATENCY_STATS_SEL_INVAL_MIN',
'CPG_LATENCY_STATS_SEL_READ_LAST',
'CPG_LATENCY_STATS_SEL_READ_MAX',
'CPG_LATENCY_STATS_SEL_READ_MIN',
'CPG_LATENCY_STATS_SEL_WRITE_LAST',
'CPG_LATENCY_STATS_SEL_WRITE_MAX',
'CPG_LATENCY_STATS_SEL_WRITE_MIN',
'CPG_LATENCY_STATS_SEL_XACK_LAST',
'CPG_LATENCY_STATS_SEL_XACK_MAX',
'CPG_LATENCY_STATS_SEL_XACK_MIN',
'CPG_LATENCY_STATS_SEL_XNACK_LAST',
'CPG_LATENCY_STATS_SEL_XNACK_MAX',
'CPG_LATENCY_STATS_SEL_XNACK_MIN', 'CPG_PERFCOUNTWINDOW_SEL',
'CPG_PERFCOUNT_SEL', 'CPG_PERFWINDOW_SEL_APPEND',
'CPG_PERFWINDOW_SEL_CE', 'CPG_PERFWINDOW_SEL_CEDMA',
'CPG_PERFWINDOW_SEL_CPC_IC', 'CPG_PERFWINDOW_SEL_CPG_IC',
'CPG_PERFWINDOW_SEL_DDID', 'CPG_PERFWINDOW_SEL_DFY',
'CPG_PERFWINDOW_SEL_DMA', 'CPG_PERFWINDOW_SEL_ME',
'CPG_PERFWINDOW_SEL_MEC1', 'CPG_PERFWINDOW_SEL_MEC2',
'CPG_PERFWINDOW_SEL_MEMRD', 'CPG_PERFWINDOW_SEL_MEMWR',
'CPG_PERFWINDOW_SEL_MES', 'CPG_PERFWINDOW_SEL_PFP',
'CPG_PERFWINDOW_SEL_PQ1', 'CPG_PERFWINDOW_SEL_PQ2',
'CPG_PERFWINDOW_SEL_PQ3', 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR',
'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', 'CPG_PERFWINDOW_SEL_QURD',
'CPG_PERFWINDOW_SEL_QU_EOP', 'CPG_PERFWINDOW_SEL_QU_PIPE',
'CPG_PERFWINDOW_SEL_QU_STRM', 'CPG_PERFWINDOW_SEL_RB',
'CPG_PERFWINDOW_SEL_RESERVED1', 'CPG_PERFWINDOW_SEL_RESERVED2',
'CPG_PERFWINDOW_SEL_SHADOW', 'CPG_PERFWINDOW_SEL_SR',
'CPG_PERFWINDOW_SEL_VGT0', 'CPG_PERFWINDOW_SEL_VGT1',
'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', 'CPG_PERF_SEL_ALWAYS_COUNT',
'CPG_PERF_SEL_CE_INSTR_CACHE_HIT',
'CPG_PERF_SEL_CE_INSTR_CACHE_MISS',
'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG',
'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU',
'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ',
'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER',
'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO',
'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO',
'CPG_PERF_SEL_CE_STALL_RAM_DUMP',
'CPG_PERF_SEL_CE_STALL_RAM_WRITE',
'CPG_PERF_SEL_COUNT_TYPE0_PACKETS',
'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 'CPG_PERF_SEL_CPG_GCRIU_BUSY',
'CPG_PERF_SEL_CPG_GCRIU_IDLE', 'CPG_PERF_SEL_CPG_GCRIU_STALL',
'CPG_PERF_SEL_CPG_STAT_BUSY', 'CPG_PERF_SEL_CPG_STAT_IDLE',
'CPG_PERF_SEL_CPG_STAT_STALL', 'CPG_PERF_SEL_CPG_TCIU_BUSY',
'CPG_PERF_SEL_CPG_TCIU_IDLE', 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY',
'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', 'CPG_PERF_SEL_CPG_UTCL2IU_STALL',
'CPG_PERF_SEL_CPG_UTCL2IU_XACK', 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK',
'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS',
'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT',
'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS',
'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS',
'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS',
'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR',
'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL',
'CPG_PERF_SEL_DYNAMIC_CLK_VALID',
'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
'CPG_PERF_SEL_GUS_READ_REQUEST_SENT',
'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT',
'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY',
'CPG_PERF_SEL_ME_INSTR_CACHE_HIT',
'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', 'CPG_PERF_SEL_ME_PARSER_BUSY',
'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP',
'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ',
'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX',
'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH',
'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS',
'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU',
'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER',
'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER',
'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT',
'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS',
'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1',
'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2',
'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1',
'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2',
'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ',
'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY',
'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY',
'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY',
'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY',
'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE',
'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM',
'CPG_PERF_SEL_RBIU_FIFO_FULL',
'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ',
'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ',
'CPG_PERF_SEL_REGISTER_CLK_VALID',
'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS',
'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX',
'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS',
'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT',
'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE',
'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS',
'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION',
'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM',
'CP_ALPHA_TAG_RAM_SEL', 'CP_DDID_CNTL_MODE', 'CP_DDID_CNTL_SIZE',
'CP_DDID_CNTL_VMID_SEL', 'CP_ME_ID', 'CP_PERFMON_ENABLE_MODE',
'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT',
'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE',
'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE',
'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE',
'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM',
'CP_PERFMON_STATE_DISABLE_AND_RESET',
'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM',
'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING',
'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID',
'CRC_CUR_0', 'CRC_CUR_1', 'CRC_CUR_BITS_0', 'CRC_CUR_BITS_1',
'CRC_CUR_BITS_SEL', 'CRC_CUR_SEL', 'CRC_INTERLACE_0',
'CRC_INTERLACE_1', 'CRC_INTERLACE_2', 'CRC_INTERLACE_3',
'CRC_INTERLACE_SEL', 'CRC_IN_CUR_0', 'CRC_IN_CUR_1',
'CRC_IN_CUR_SEL', 'CRC_IN_PIX_0', 'CRC_IN_PIX_1', 'CRC_IN_PIX_2',
'CRC_IN_PIX_3', 'CRC_IN_PIX_4', 'CRC_IN_PIX_5', 'CRC_IN_PIX_6',
'CRC_IN_PIX_7', 'CRC_IN_PIX_SEL', 'CRC_SRC_0', 'CRC_SRC_1',
'CRC_SRC_2', 'CRC_SRC_3', 'CRC_SRC_SEL', 'CRC_STEREO_0',
'CRC_STEREO_1', 'CRC_STEREO_2', 'CRC_STEREO_3', 'CRC_STEREO_SEL',
'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1',
'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2',
'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
'CROB_MEM_PWR_LIGHT_SLEEP_MODE', 'CROSSBAR_FOR_ALPHA',
'CROSSBAR_FOR_CB_B', 'CROSSBAR_FOR_CR_R', 'CROSSBAR_FOR_Y_G',
'CR_R_DATA_ON_ALPHA_PORT', 'CR_R_DATA_ON_CB_B_PORT',
'CR_R_DATA_ON_CR_R_PORT', 'CR_R_DATA_ON_Y_G_PORT',
'CSCNTL_ADDR_WIDTH', 'CSCNTL_DATA_WIDTH', 'CSCNTL_TYPE',
'CSCNTL_TYPE_EVENT', 'CSCNTL_TYPE_PRIVATE', 'CSCNTL_TYPE_STATE',
'CSCNTL_TYPE_TG', 'CSCNTL_TYPE_WIDTH', 'CSDATA_ADDR_WIDTH',
'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', 'CSDATA_TYPE_EVENT',
'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', 'CSDATA_TYPE_TG',
'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', 'CS_DONE', 'CS_NA',
'CS_PARTIAL_FLUSH', 'CS_STAGE_ON', 'CURSOR_2X_MAGNIFY',
'CURSOR_2X_MAGNIFY_IS_DISABLE', 'CURSOR_2X_MAGNIFY_IS_ENABLE',
'CURSOR_COLOR_24BIT_1BIT_AND',
'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT',
'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT',
'CURSOR_COLOR_64BIT_FP_PREMULT',
'CURSOR_COLOR_64BIT_FP_UNPREMULT', 'CURSOR_ENABLE',
'CURSOR_IN_GUEST_PHYSICAL_ADDRESS',
'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', 'CURSOR_IS_DISABLE',
'CURSOR_IS_ENABLE', 'CURSOR_IS_NOT_SNOOP', 'CURSOR_IS_SNOOP',
'CURSOR_LINES_PER_CHUNK', 'CURSOR_LINE_PER_CHUNK_1',
'CURSOR_LINE_PER_CHUNK_16', 'CURSOR_LINE_PER_CHUNK_2',
'CURSOR_LINE_PER_CHUNK_4', 'CURSOR_LINE_PER_CHUNK_8',
'CURSOR_MODE', 'CURSOR_MONO_2BIT',
'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY',
'CURSOR_PERFMON_LATENCY_MEASURE_EN',
'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED',
'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED',
'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY',
'CURSOR_PERFMON_LATENCY_MEASURE_SEL', 'CURSOR_PITCH',
'CURSOR_PITCH_128_PIXELS', 'CURSOR_PITCH_256_PIXELS',
'CURSOR_PITCH_64_PIXELS', 'CURSOR_SNOOP', 'CURSOR_STEREO_EN',
'CURSOR_STEREO_IS_DISABLED', 'CURSOR_STEREO_IS_ENABLED',
'CURSOR_SURFACE_IS_NOT_TMZ', 'CURSOR_SURFACE_IS_TMZ',
'CURSOR_SURFACE_TMZ', 'CURSOR_SYSTEM',
'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS',
'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0',
'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1',
'CUR_CLAMP_DIS', 'CUR_CLAMP_EN', 'CUR_DIS',
'CUR_DYNAMIC_EXPANSION', 'CUR_EN', 'CUR_ENABLE',
'CUR_EXPAND_MODE', 'CUR_FP_NO_ROM', 'CUR_FP_USE_ROM',
'CUR_INV_CLAMP', 'CUR_MODE', 'CUR_NOT_PENDING', 'CUR_PENDING',
'CUR_ROM_EN', 'CUR_YES_PENDING', 'CUR_ZERO_EXPANSION',
'CbYCrY10101010_422_PACKED', 'CbYCrY12121212_422_PACKED',
'CbYCrY8888_422_PACKED', 'CmaskAddr', 'CmaskCode', 'CmaskMode',
'ColorArray', 'ColorFormat', 'ColorTransform', 'CombFunc',
'CompareFrag', 'CompareRef', 'ConservativeZExport',
'CovToShaderSel', 'CrYCbA1010102', 'CrYCbA16161616_10LSB',
'CrYCbA16161616_10MSB', 'CrYCbA16161616_12LSB',
'CrYCbA16161616_12MSB', 'CrYCbA8888', 'CrYCbY10101010_422_PACKED',
'CrYCbY12121212_422_PACKED', 'CrYCbY8888_422_PACKED',
'DAC_MUX_SELECT', 'DAC_MUX_SELECT_DACA', 'DAC_MUX_SELECT_DACB',
'DB_BREAK_BATCH_EVENT', 'DB_CACHE_FLUSH',
'DB_CACHE_FLUSH_AND_INV', 'DB_CACHE_FLUSH_AND_INV_EVENT',
'DB_CACHE_FLUSH_AND_INV_TS_EVENT', 'DB_CACHE_FLUSH_TS',
'DB_CONTEXT_DONE_EVENT', 'DB_CONTEXT_SUSPEND_EVENT',
'DB_FLUSH_AND_INV_DB_DATA_TS', 'DB_FLUSH_AND_INV_DB_META',
'DB_PERF_SEL_CB_DB_rdreq_prt_sends',
'DB_PERF_SEL_CB_DB_rdreq_sends',
'DB_PERF_SEL_CB_DB_wrreq_prt_sends',
'DB_PERF_SEL_CB_DB_wrreq_sends',
'DB_PERF_SEL_DB_CB_context_dones', 'DB_PERF_SEL_DB_CB_eop_dones',
'DB_PERF_SEL_DB_CB_lquad_busy',
'DB_PERF_SEL_DB_CB_lquad_double_format',
'DB_PERF_SEL_DB_CB_lquad_export_quads',
'DB_PERF_SEL_DB_CB_lquad_fast_format',
'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix',
'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix',
'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix',
'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix',
'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending',
'DB_PERF_SEL_DB_CB_lquad_quads', 'DB_PERF_SEL_DB_CB_lquad_sends',
'DB_PERF_SEL_DB_CB_lquad_slow_format',
'DB_PERF_SEL_DB_CB_lquad_stalls', 'DB_PERF_SEL_DB_CB_rdret_ack',
'DB_PERF_SEL_DB_CB_rdret_nack', 'DB_PERF_SEL_DB_CB_tile_busy',
'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS',
'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA',
'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS',
'DB_PERF_SEL_DB_CB_tile_sends', 'DB_PERF_SEL_DB_CB_tile_stalls',
'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event',
'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack',
'DB_PERF_SEL_DB_SC_c_tile_rate', 'DB_PERF_SEL_DB_SC_quad_busy',
'DB_PERF_SEL_DB_SC_quad_double_quad',
'DB_PERF_SEL_DB_SC_quad_lit_quad',
'DB_PERF_SEL_DB_SC_quad_lit_quad_pre_invoke',
'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel',
'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels',
'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels',
'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels',
'DB_PERF_SEL_DB_SC_quad_sends', 'DB_PERF_SEL_DB_SC_quad_stalls',
'DB_PERF_SEL_DB_SC_quad_tiles', 'DB_PERF_SEL_DB_SC_s_tile_rate',
'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled',
'DB_PERF_SEL_DB_SC_tile_df_stalls',
'DB_PERF_SEL_DB_SC_tile_fast_ops',
'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops',
'DB_PERF_SEL_DB_SC_tile_fast_z_ops',
'DB_PERF_SEL_DB_SC_tile_hier_kill',
'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends',
'DB_PERF_SEL_DB_SC_tile_ssaa_kill',
'DB_PERF_SEL_DB_SC_tile_stalls',
'DB_PERF_SEL_DB_SC_tile_tile_rate',
'DB_PERF_SEL_DB_SC_tile_tiles', 'DB_PERF_SEL_DB_SC_z_tile_rate',
'DB_PERF_SEL_DFSM_Flush_flushabit',
'DB_PERF_SEL_DFSM_Flush_flushabit_camcoord_fifo',
'DB_PERF_SEL_DFSM_Flush_flushabit_forceflush',
'DB_PERF_SEL_DFSM_Flush_flushabit_nearlyfull',
'DB_PERF_SEL_DFSM_Flush_flushabit_passthrough',
'DB_PERF_SEL_DFSM_Flush_flushabit_primitivesinflightwatermark',
'DB_PERF_SEL_DFSM_Flush_flushabit_punch_stalling',
'DB_PERF_SEL_DFSM_Flush_flushabit_retainedtilefifo_watermark',
'DB_PERF_SEL_DFSM_Flush_flushabit_tilesinflightwatermark',
'DB_PERF_SEL_DFSM_Flush_flushall',
'DB_PERF_SEL_DFSM_Flush_flushall_dfsmflush',
'DB_PERF_SEL_DFSM_Flush_flushall_opmodechange',
'DB_PERF_SEL_DFSM_Flush_flushall_sampleratechange',
'DB_PERF_SEL_DFSM_Flush_flushall_watchdog',
'DB_PERF_SEL_DFSM_Stall_bypass_fifo',
'DB_PERF_SEL_DFSM_Stall_cam_fifo',
'DB_PERF_SEL_DFSM_Stall_control_fifo',
'DB_PERF_SEL_DFSM_Stall_middle_output',
'DB_PERF_SEL_DFSM_Stall_opmode_change',
'DB_PERF_SEL_DFSM_Stall_overflow_counter',
'DB_PERF_SEL_DFSM_Stall_pops_stall_overflow',
'DB_PERF_SEL_DFSM_Stall_pops_stall_self_flush',
'DB_PERF_SEL_DFSM_Stall_retained_tile_fifo',
'DB_PERF_SEL_DFSM_Stall_stalling_general',
'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream',
'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO',
'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow',
'DB_PERF_SEL_DFSM_evicted_squads_above_watermark',
'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark',
'DB_PERF_SEL_DFSM_evicted_tiles_above_watermark',
'DB_PERF_SEL_DFSM_full_cleared_squads_out',
'DB_PERF_SEL_DFSM_fully_cleared_pixels_out',
'DB_PERF_SEL_DFSM_fully_cleared_quads_out',
'DB_PERF_SEL_DFSM_lit_pixels_in',
'DB_PERF_SEL_DFSM_lit_samples_in',
'DB_PERF_SEL_DFSM_lit_samples_out',
'DB_PERF_SEL_DFSM_prez_killed_squad', 'DB_PERF_SEL_DFSM_quads_in',
'DB_PERF_SEL_DFSM_squads_in',
'DB_PERF_SEL_DFSM_stalled_by_downstream',
'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall',
'DB_PERF_SEL_Depth_Tile_Cache_busy',
'DB_PERF_SEL_Depth_Tile_Cache_data_frees',
'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop',
'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked',
'DB_PERF_SEL_Depth_Tile_Cache_event',
'DB_PERF_SEL_Depth_Tile_Cache_flushes',
'DB_PERF_SEL_Depth_Tile_Cache_hits',
'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve',
'DB_PERF_SEL_Depth_Tile_Cache_misses',
'DB_PERF_SEL_Depth_Tile_Cache_noop_tile',
'DB_PERF_SEL_Depth_Tile_Cache_sends',
'DB_PERF_SEL_Depth_Tile_Cache_starves',
'DB_PERF_SEL_Depth_Tile_Cache_tile_frees',
'DB_PERF_SEL_MI_psd_req_wrack_counter_stall',
'DB_PERF_SEL_MI_quad_req_wrack_counter_stall',
'DB_PERF_SEL_MI_tile_req_wrack_counter_stall',
'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall',
'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall',
'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy',
'DB_PERF_SEL_Plane_Cache_flushes',
'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits',
'DB_PERF_SEL_Plane_Cache_misses',
'DB_PERF_SEL_Plane_Cache_starves',
'DB_PERF_SEL_PostZ_Samples_failing_DB',
'DB_PERF_SEL_PostZ_Samples_failing_S',
'DB_PERF_SEL_PostZ_Samples_failing_Z',
'DB_PERF_SEL_PostZ_Samples_passing_Z',
'DB_PERF_SEL_PreZ_Samples_failing_DB',
'DB_PERF_SEL_PreZ_Samples_failing_S',
'DB_PERF_SEL_PreZ_Samples_failing_Z',
'DB_PERF_SEL_PreZ_Samples_passing_Z',
'DB_PERF_SEL_SC_DB_quad_busy',
'DB_PERF_SEL_SC_DB_quad_killed_tiles',
'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_quads',
'DB_PERF_SEL_SC_DB_quad_sends', 'DB_PERF_SEL_SC_DB_quad_squads',
'DB_PERF_SEL_SC_DB_quad_tiles', 'DB_PERF_SEL_SC_DB_tile_backface',
'DB_PERF_SEL_SC_DB_tile_busy', 'DB_PERF_SEL_SC_DB_tile_covered',
'DB_PERF_SEL_SC_DB_tile_events', 'DB_PERF_SEL_SC_DB_tile_sends',
'DB_PERF_SEL_SC_DB_tile_stalls', 'DB_PERF_SEL_SC_DB_tile_tiles',
'DB_PERF_SEL_SH_quads_outstanding_sum',
'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled',
'DB_PERF_SEL_SX_DB_quad_all_pixels_killed',
'DB_PERF_SEL_SX_DB_quad_busy',
'DB_PERF_SEL_SX_DB_quad_double_format',
'DB_PERF_SEL_SX_DB_quad_export_quads',
'DB_PERF_SEL_SX_DB_quad_exports',
'DB_PERF_SEL_SX_DB_quad_fast_format',
'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read',
'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads',
'DB_PERF_SEL_SX_DB_quad_sends',
'DB_PERF_SEL_SX_DB_quad_slow_format',
'DB_PERF_SEL_SX_DB_quad_stalls',
'DB_PERF_SEL_Stencil_Cache_flushes',
'DB_PERF_SEL_Stencil_Cache_frees',
'DB_PERF_SEL_Stencil_Cache_hits',
'DB_PERF_SEL_Stencil_Cache_misses',
'DB_PERF_SEL_Stencil_Cache_starves',
'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits',
'DB_PERF_SEL_Tile_Cache_mem_return_starve',
'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves',
'DB_PERF_SEL_Tile_Cache_surface_stall',
'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes',
'DB_PERF_SEL_Z_Cache_pmask_hits',
'DB_PERF_SEL_Z_Cache_pmask_misses',
'DB_PERF_SEL_Z_Cache_pmask_starves',
'DB_PERF_SEL_Z_Cache_separate_Z_flushes',
'DB_PERF_SEL_Z_Cache_separate_Z_hits',
'DB_PERF_SEL_Z_Cache_separate_Z_misses',
'DB_PERF_SEL_Z_Cache_separate_Z_starves',
'DB_PERF_SEL_clock_main_active',
'DB_PERF_SEL_clock_mem_export_active',
'DB_PERF_SEL_clock_reg_active',
'DB_PERF_SEL_depth_bounds_tile_culled', 'DB_PERF_SEL_di_dt_stall',
'DB_PERF_SEL_dk_squad_busy', 'DB_PERF_SEL_dk_squad_sends',
'DB_PERF_SEL_dk_squad_stalls', 'DB_PERF_SEL_dk_tile_busy',
'DB_PERF_SEL_dk_tile_quad_starves', 'DB_PERF_SEL_dk_tile_sends',
'DB_PERF_SEL_dk_tile_stalls', 'DB_PERF_SEL_dkg_tile_rate_tile',
'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall',
'DB_PERF_SEL_dtt_sm_slot_stall',
'DB_PERF_SEL_earlyZ_waiting_for_postZ_done',
'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward',
'DB_PERF_SEL_esr_eot_fwd_holding_squad',
'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall',
'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_sqq_busy',
'DB_PERF_SEL_esr_ps_sqq_stall', 'DB_PERF_SEL_esr_ps_src_in_sends',
'DB_PERF_SEL_esr_ps_src_in_squads',
'DB_PERF_SEL_esr_ps_src_in_squads_unrolled',
'DB_PERF_SEL_esr_ps_src_in_stall',
'DB_PERF_SEL_esr_ps_src_in_tile_rate',
'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled',
'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate',
'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_sqq_zi_busy',
'DB_PERF_SEL_esr_sqq_zi_stall', 'DB_PERF_SEL_etr_out_busy',
'DB_PERF_SEL_etr_out_cb_tile_stall',
'DB_PERF_SEL_etr_out_esr_stall',
'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall',
'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane',
'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane',
'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane',
'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane',
'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane',
'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane',
'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane',
'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane',
'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed',
'DB_PERF_SEL_flush_compressed_stencil',
'DB_PERF_SEL_flush_expanded_stencil',
'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4',
'DB_PERF_SEL_flush_single_stencil', 'DB_PERF_SEL_his_tile_culled',
'DB_PERF_SEL_hiz_tc_read_starved',
'DB_PERF_SEL_hiz_tc_write_stall', 'DB_PERF_SEL_hiz_tile_culled',
'DB_PERF_SEL_mi_quad_rd_outstanding_sum',
'DB_PERF_SEL_mi_quad_wr_outstanding_sum',
'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall',
'DB_PERF_SEL_mi_tile_rd_outstanding_sum',
'DB_PERF_SEL_mi_tile_wr_outstanding_sum',
'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall',
'DB_PERF_SEL_planes_flushed', 'DB_PERF_SEL_postzl_full_launch',
'DB_PERF_SEL_postzl_partial_launch',
'DB_PERF_SEL_postzl_partial_waiting',
'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall',
'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall',
'DB_PERF_SEL_postzl_src_in_sends',
'DB_PERF_SEL_postzl_src_in_squads',
'DB_PERF_SEL_postzl_src_in_squads_unrolled',
'DB_PERF_SEL_postzl_src_in_stall',
'DB_PERF_SEL_postzl_src_in_tile_rate',
'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled',
'DB_PERF_SEL_postzl_src_out_stall',
'DB_PERF_SEL_postzl_tile_init_stall',
'DB_PERF_SEL_postzl_tile_mem_stall',
'DB_PERF_SEL_prezl_src_in_sends',
'DB_PERF_SEL_prezl_src_in_squads',
'DB_PERF_SEL_prezl_src_in_squads_unrolled',
'DB_PERF_SEL_prezl_src_in_stall',
'DB_PERF_SEL_prezl_src_in_tile_rate',
'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled',
'DB_PERF_SEL_prezl_src_out_stall',
'DB_PERF_SEL_prezl_tile_init_stall',
'DB_PERF_SEL_prezl_tile_mem_stall', 'DB_PERF_SEL_qc_busy',
'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall',
'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ',
'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc',
'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy',
'DB_PERF_SEL_quad_rd_mi_stall', 'DB_PERF_SEL_quad_rd_panic',
'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends',
'DB_PERF_SEL_quad_rd_tag_stall', 'DB_PERF_SEL_quad_rdret_busy',
'DB_PERF_SEL_quad_rdret_sends', 'DB_PERF_SEL_quad_wr_acks',
'DB_PERF_SEL_quad_wr_busy', 'DB_PERF_SEL_quad_wr_coherency_stall',
'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends',
'DB_PERF_SEL_reZ_waiting_for_postZ_done',
'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop',
'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start',
'DB_PERF_SEL_tcp_dispatcher_flushes',
'DB_PERF_SEL_tcp_dispatcher_reads',
'DB_PERF_SEL_tcp_prefetcher_flushes',
'DB_PERF_SEL_tcp_prefetcher_reads',
'DB_PERF_SEL_tcp_preloader_flushes',
'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends',
'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends',
'DB_PERF_SEL_tiles_compressed_to_decompressed',
'DB_PERF_SEL_tiles_decomp_on_expclear',
'DB_PERF_SEL_tiles_s_clear_on_expclear',
'DB_PERF_SEL_tiles_stencil_fully_summarized',
'DB_PERF_SEL_tiles_z_clear_on_expclear',
'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy',
'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events',
'DB_PERF_SEL_tl_expand_squads',
'DB_PERF_SEL_tl_flush_expand_squads',
'DB_PERF_SEL_tl_in_fast_z_stall',
'DB_PERF_SEL_tl_in_single_stencil_expand_stall',
'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads',
'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads',
'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads',
'DB_PERF_SEL_tl_preZ_squads',
'DB_PERF_SEL_tl_stencil_locked_stall',
'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads',
'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall',
'DB_PERF_SEL_tl_z_fetch_stall', 'DB_PERF_SEL_ts_tc_update_stall',
'DB_PERF_SEL_tsc_insert_summarize_stall',
'DB_PERF_SEL_unmapped_z_tile_culled',
'DB_PERF_SEL_zf_plane_multicycle', 'DB_PSINVOKE_CHANGE_EVENT',
'DB_VPORT_CHANGED_EVENT', 'DCCG_AUDIO_DTO0_SOURCE_SEL',
'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0',
'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1',
'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2',
'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3',
'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4',
'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5',
'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED',
'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0',
'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1', 'DCCG_AUDIO_DTO_SEL',
'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1',
'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO',
'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP',
'DCCG_AUDIO_DTO_USE_512FBR_DTO',
'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DEEP_COLOR_CNTL',
'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO',
'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE',
'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN',
'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET',
'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP',
'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION',
'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_MODE_HSYNC',
'DCCG_PERF_MODE_HSYNC_NOOP', 'DCCG_PERF_MODE_HSYNC_START',
'DCCG_PERF_MODE_VSYNC', 'DCCG_PERF_MODE_VSYNC_NOOP',
'DCCG_PERF_MODE_VSYNC_START', 'DCCG_PERF_OTG_SELECT',
'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START',
'DCCG_PERF_SEL_OTG0', 'DCCG_PERF_SEL_OTG1', 'DCCG_PERF_SEL_OTG2',
'DCCG_PERF_SEL_OTG3', 'DCCG_PERF_SEL_OTG4', 'DCCG_PERF_SEL_OTG5',
'DCCG_PERF_SEL_RESERVED', 'DCC_CT_AUTO', 'DCC_CT_NONE',
'DCIOCHIP_2BIT_DISABLE', 'DCIOCHIP_2BIT_ENABLE',
'DCIOCHIP_4BIT_DISABLE', 'DCIOCHIP_4BIT_ENABLE',
'DCIOCHIP_5BIT_DISABLE', 'DCIOCHIP_5BIT_ENABLE',
'DCIOCHIP_AUXSLAVE_PAD_MODE', 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX',
'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C', 'DCIOCHIP_AUX_ALL_PWR_OK',
'DCIOCHIP_AUX_ALL_PWR_OK_0', 'DCIOCHIP_AUX_ALL_PWR_OK_1',
'DCIOCHIP_AUX_CSEL0P9', 'DCIOCHIP_AUX_CSEL1P1',
'DCIOCHIP_AUX_CSEL_DEC0P9', 'DCIOCHIP_AUX_CSEL_DEC1P0',
'DCIOCHIP_AUX_CSEL_INC1P0', 'DCIOCHIP_AUX_CSEL_INC1P1',
'DCIOCHIP_AUX_FALLSLEWSEL', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0',
'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW',
'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_HYS_TUNE',
'DCIOCHIP_AUX_HYS_TUNE_0', 'DCIOCHIP_AUX_HYS_TUNE_1',
'DCIOCHIP_AUX_HYS_TUNE_2', 'DCIOCHIP_AUX_HYS_TUNE_3',
'DCIOCHIP_AUX_RECEIVER_SEL', 'DCIOCHIP_AUX_RECEIVER_SEL_0',
'DCIOCHIP_AUX_RECEIVER_SEL_1', 'DCIOCHIP_AUX_RECEIVER_SEL_2',
'DCIOCHIP_AUX_RECEIVER_SEL_3', 'DCIOCHIP_AUX_RSEL0P9',
'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9',
'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0',
'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL',
'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS',
'DCIOCHIP_AUX_VOD_TUNE', 'DCIOCHIP_AUX_VOD_TUNE_0',
'DCIOCHIP_AUX_VOD_TUNE_1', 'DCIOCHIP_AUX_VOD_TUNE_2',
'DCIOCHIP_AUX_VOD_TUNE_3', 'DCIOCHIP_DVO_VREFPON',
'DCIOCHIP_DVO_VREFPON_DISABLE', 'DCIOCHIP_DVO_VREFPON_ENABLE',
'DCIOCHIP_DVO_VREFSEL', 'DCIOCHIP_DVO_VREFSEL_EXTERNAL',
'DCIOCHIP_DVO_VREFSEL_ONCHIP', 'DCIOCHIP_ENABLE_2BIT',
'DCIOCHIP_ENABLE_4BIT', 'DCIOCHIP_ENABLE_5BIT',
'DCIOCHIP_GPIO_I2C_DISABLE', 'DCIOCHIP_GPIO_I2C_DRIVE',
'DCIOCHIP_GPIO_I2C_DRIVE_HIGH', 'DCIOCHIP_GPIO_I2C_DRIVE_LOW',
'DCIOCHIP_GPIO_I2C_EN', 'DCIOCHIP_GPIO_I2C_ENABLE',
'DCIOCHIP_GPIO_I2C_MASK', 'DCIOCHIP_GPIO_I2C_MASK_DISABLE',
'DCIOCHIP_GPIO_I2C_MASK_ENABLE', 'DCIOCHIP_GPIO_MASK_EN',
'DCIOCHIP_GPIO_MASK_EN_HARDWARE',
'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL',
'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED',
'DCIOCHIP_I2C_COMPSEL', 'DCIOCHIP_I2C_FALLSLEWSEL',
'DCIOCHIP_I2C_FALLSLEWSEL_00', 'DCIOCHIP_I2C_FALLSLEWSEL_01',
'DCIOCHIP_I2C_FALLSLEWSEL_10', 'DCIOCHIP_I2C_FALLSLEWSEL_11',
'DCIOCHIP_I2C_RECEIVER_SEL', 'DCIOCHIP_I2C_RECEIVER_SEL_0',
'DCIOCHIP_I2C_RECEIVER_SEL_1', 'DCIOCHIP_I2C_RECEIVER_SEL_2',
'DCIOCHIP_I2C_RECEIVER_SEL_3', 'DCIOCHIP_I2C_REC_COMPARATOR',
'DCIOCHIP_I2C_REC_SCHMIT', 'DCIOCHIP_I2C_VPH_1V2_EN',
'DCIOCHIP_I2C_VPH_1V2_EN_0', 'DCIOCHIP_I2C_VPH_1V2_EN_1',
'DCIOCHIP_INVERT', 'DCIOCHIP_MASIK_5BIT_DISABLE',
'DCIOCHIP_MASIK_5BIT_ENABLE', 'DCIOCHIP_MASK',
'DCIOCHIP_MASK_2BIT', 'DCIOCHIP_MASK_2BIT_DISABLE',
'DCIOCHIP_MASK_2BIT_ENABLE', 'DCIOCHIP_MASK_4BIT',
'DCIOCHIP_MASK_4BIT_DISABLE', 'DCIOCHIP_MASK_4BIT_ENABLE',
'DCIOCHIP_MASK_5BIT', 'DCIOCHIP_MASK_DISABLE',
'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE',
'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN',
'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW',
'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT',
'DCIOCHIP_REF_27_SRC_SEL',
'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS',
'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER',
'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS',
'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', 'DCIOCHIP_SPDIF1_IMODE',
'DCIOCHIP_SPDIF1_IMODE_OE_A', 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO',
'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE',
'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN',
'DCIO_BL_PWM_CNTL_BL_PWM_EN',
'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', 'DCIO_BL_PWM_DISABLE',
'DCIO_BL_PWM_ENABLE', 'DCIO_BL_PWM_FRACTIONAL_DISABLE',
'DCIO_BL_PWM_FRACTIONAL_ENABLE',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6',
'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE',
'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN',
'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE',
'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN',
'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM',
'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM',
'DCIO_BL_PWM_GRP1_REG_LOCK', 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE',
'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE',
'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START',
'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE',
'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE',
'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE',
'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE',
'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL',
'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM',
'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL',
'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', 'DCIO_DACA_SOFT_RESET',
'DCIO_DACA_SOFT_RESET_ASSERT', 'DCIO_DACA_SOFT_RESET_DEASSERT',
'DCIO_DCRXPHY_SOFT_RESET', 'DCIO_DCRXPHY_SOFT_RESET_ASSERT',
'DCIO_DCRXPHY_SOFT_RESET_DEASSERT',
'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN',
'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN',
'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN', 'DCIO_DC_GENERICA_SEL',
'DCIO_DC_GENERICB_SEL',
'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL',
'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL',
'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL',
'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL',
'DCIO_DC_GPU_TIMER_READ_SELECT',
'DCIO_DC_GPU_TIMER_START_POSITION',
'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL',
'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL',
'DCIO_DIO_EXT_VSYNC_MASK', 'DCIO_DIO_OTG_EXT_VSYNC_MUX',
'DCIO_DISPCLK_R_DCIO_GATE_DISABLE',
'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE',
'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK',
'DCIO_DPCS_INTERRUPT_TYPE',
'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED',
'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', 'DCIO_DPHY_LANE_SEL',
'DCIO_DPHY_LANE_SEL_LANE0', 'DCIO_DPHY_LANE_SEL_LANE1',
'DCIO_DPHY_LANE_SEL_LANE2', 'DCIO_DPHY_LANE_SEL_LANE3',
'DCIO_DSYNC_SOFT_RESET', 'DCIO_DSYNC_SOFT_RESET_ASSERT',
'DCIO_DSYNC_SOFT_RESET_DEASSERT',
'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE',
'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT', 'DCIO_EXT_VSYNC_MASK_NONE',
'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', 'DCIO_EXT_VSYNC_MASK_PIPE0',
'DCIO_EXT_VSYNC_MASK_PIPE1', 'DCIO_EXT_VSYNC_MASK_PIPE2',
'DCIO_EXT_VSYNC_MASK_PIPE3', 'DCIO_EXT_VSYNC_MASK_PIPE4',
'DCIO_EXT_VSYNC_MASK_PIPE5', 'DCIO_EXT_VSYNC_MUX_GENERICB',
'DCIO_EXT_VSYNC_MUX_OTG0', 'DCIO_EXT_VSYNC_MUX_OTG1',
'DCIO_EXT_VSYNC_MUX_OTG2', 'DCIO_EXT_VSYNC_MUX_OTG3',
'DCIO_EXT_VSYNC_MUX_OTG4', 'DCIO_EXT_VSYNC_MUX_OTG5',
'DCIO_EXT_VSYNC_MUX_SWAPLOCKB',
'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER',
'DCIO_GENERICA_SEL_DACA_PIXCLK',
'DCIO_GENERICA_SEL_DACA_STEREOSYNC',
'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER',
'DCIO_GENERICA_SEL_DACB_PIXCLK', 'DCIO_GENERICA_SEL_DVOA_CTL3',
'DCIO_GENERICA_SEL_DVOA_STEREOSYNC',
'DCIO_GENERICA_SEL_GENERICA_DCCG',
'DCIO_GENERICA_SEL_GENERICA_DPRX',
'DCIO_GENERICA_SEL_GENERICB_DPRX', 'DCIO_GENERICA_SEL_P1_PLLCLK',
'DCIO_GENERICA_SEL_P2_PLLCLK', 'DCIO_GENERICA_SEL_STEREOSYNC',
'DCIO_GENERICA_SEL_SYNCEN', 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK',
'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2',
'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK',
'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK',
'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER',
'DCIO_GENERICB_SEL_DACA_PIXCLK',
'DCIO_GENERICB_SEL_DACA_STEREOSYNC',
'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER',
'DCIO_GENERICB_SEL_DACB_PIXCLK', 'DCIO_GENERICB_SEL_DVOA_CTL3',
'DCIO_GENERICB_SEL_DVOA_STEREOSYNC',
'DCIO_GENERICB_SEL_GENERICB_DCCG', 'DCIO_GENERICB_SEL_P1_PLLCLK',
'DCIO_GENERICB_SEL_P2_PLLCLK', 'DCIO_GENERICB_SEL_STEREOSYNC',
'DCIO_GENERICB_SEL_SYNCEN', 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK',
'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2',
'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK',
'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK', 'DCIO_GENLK_CLK_GSL_MASK',
'DCIO_GENLK_CLK_GSL_MASK_NO', 'DCIO_GENLK_CLK_GSL_MASK_STEREO',
'DCIO_GENLK_CLK_GSL_MASK_TIMING',
'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE',
'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1',
'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2',
'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3',
'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO',
'DCIO_GENLK_VSYNC_GSL_MASK_STEREO',
'DCIO_GENLK_VSYNC_GSL_MASK_TIMING',
'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP',
'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM',
'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE',
'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP',
'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM',
'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE',
'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37',
'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29',
'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31',
'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35',
'DCIO_GSL_SEL', 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1',
'DCIO_GSL_SEL_GROUP_2', 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE',
'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2',
'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', 'DCIO_IMPCAL_STEP_DELAY',
'DCIO_IMPCAL_STEP_DELAY_10us', 'DCIO_IMPCAL_STEP_DELAY_11us',
'DCIO_IMPCAL_STEP_DELAY_12us', 'DCIO_IMPCAL_STEP_DELAY_13us',
'DCIO_IMPCAL_STEP_DELAY_14us', 'DCIO_IMPCAL_STEP_DELAY_15us',
'DCIO_IMPCAL_STEP_DELAY_16us', 'DCIO_IMPCAL_STEP_DELAY_1us',
'DCIO_IMPCAL_STEP_DELAY_2us', 'DCIO_IMPCAL_STEP_DELAY_3us',
'DCIO_IMPCAL_STEP_DELAY_4us', 'DCIO_IMPCAL_STEP_DELAY_5us',
'DCIO_IMPCAL_STEP_DELAY_6us', 'DCIO_IMPCAL_STEP_DELAY_7us',
'DCIO_IMPCAL_STEP_DELAY_8us', 'DCIO_IMPCAL_STEP_DELAY_9us',
'DCIO_LVTMA_BLON_OFF', 'DCIO_LVTMA_BLON_ON',
'DCIO_LVTMA_BLON_POL_INVERT', 'DCIO_LVTMA_BLON_POL_NON_INVERT',
'DCIO_LVTMA_DIGON_OFF', 'DCIO_LVTMA_DIGON_ON',
'DCIO_LVTMA_DIGON_POL_INVERT', 'DCIO_LVTMA_DIGON_POL_NON_INVERT',
'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN',
'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON',
'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL',
'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON',
'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL',
'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL',
'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE',
'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN',
'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE',
'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE',
'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF',
'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON',
'DCIO_LVTMA_SYNCEN_POL_INVERT',
'DCIO_LVTMA_SYNCEN_POL_NON_INVERT',
'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON',
'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE',
'DCIO_SWAPLOCK_A_GSL_MASK', 'DCIO_SWAPLOCK_A_GSL_MASK_NO',
'DCIO_SWAPLOCK_A_GSL_MASK_STEREO',
'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK',
'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO',
'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK',
'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SOCCLK',
'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK',
'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK',
'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK',
'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK',
'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK',
'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK',
'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK',
'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED',
'DCIO_UNIPHY_CHANNEL_NO_INVERSION',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL',
'DCIO_UNIPHY_IMPCAL_SEL_BINARY',
'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE',
'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT',
'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK',
'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION',
'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW',
'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED',
'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED',
'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW',
'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS',
'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS',
'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS',
'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS',
'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS',
'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS',
'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS',
'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS',
'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE',
'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT', 'DCIO_VIP_MUX_EN_DVO',
'DCIO_VIP_MUX_EN_VIP', 'DC_DMCUB_INT_TYPE',
'DC_DMCUB_TIMER_WINDOW', 'DC_MEM_GLOBAL_PWR_REQ_DIS',
'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE',
'DC_SMU_INTERRUPT_ENABLE', 'DDID_VMID_CNTL', 'DDID_VMID_PIPE',
'DENORM_TRUNCATE', 'DEPTH_16', 'DEPTH_32_FLOAT', 'DEPTH_8_24',
'DEPTH_8_24_FLOAT', 'DEPTH_INVALID', 'DEPTH_MICRO_TILING',
'DEPTH_X24_8_32_FLOAT', 'DEPTH_X8_24', 'DEPTH_X8_24_FLOAT',
'DETILE_BUFFER_PACKER_ENABLE', 'DETILE_BUFFER_PACKER_IS_DISABLE',
'DETILE_BUFFER_PACKER_IS_ENABLE',
'DET_MEM_POWER_LIGHT_SLEEP_MODE_1',
'DET_MEM_POWER_LIGHT_SLEEP_MODE_2',
'DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
'DET_MEM_PWR_LIGHT_SLEEP_MODE', 'DFQ_MIN_FREE_ENTRIES',
'DFQ_MIN_FREE_ENTRIES_0', 'DFQ_MIN_FREE_ENTRIES_1',
'DFQ_MIN_FREE_ENTRIES_2', 'DFQ_MIN_FREE_ENTRIES_3',
'DFQ_MIN_FREE_ENTRIES_4', 'DFQ_MIN_FREE_ENTRIES_5',
'DFQ_MIN_FREE_ENTRIES_6', 'DFQ_MIN_FREE_ENTRIES_7',
'DFQ_NUM_ENTRIES', 'DFQ_NUM_ENTRIES_0', 'DFQ_NUM_ENTRIES_1',
'DFQ_NUM_ENTRIES_2', 'DFQ_NUM_ENTRIES_3', 'DFQ_NUM_ENTRIES_4',
'DFQ_NUM_ENTRIES_5', 'DFQ_NUM_ENTRIES_6', 'DFQ_NUM_ENTRIES_7',
'DFQ_NUM_ENTRIES_8', 'DFQ_SIZE', 'DFQ_SIZE_0', 'DFQ_SIZE_1',
'DFQ_SIZE_2', 'DFQ_SIZE_3', 'DFQ_SIZE_4', 'DFQ_SIZE_5',
'DFQ_SIZE_6', 'DFQ_SIZE_7', 'DFSMFlushEvents',
'DIG_10BIT_TEST_PATTERN', 'DIG_ALL_PIXEL',
'DIG_ALTERNATING_TEST_PATTERN', 'DIG_BE_CNTL_HPD1',
'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', 'DIG_BE_CNTL_HPD4',
'DIG_BE_CNTL_HPD5', 'DIG_BE_CNTL_HPD6', 'DIG_BE_CNTL_HPD_SELECT',
'DIG_BE_CNTL_MODE', 'DIG_BE_CNTL_NO_HPD', 'DIG_BE_DP_MST_MODE',
'DIG_BE_DP_SST_MODE', 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2',
'DIG_BE_RESERVED3', 'DIG_BE_RESERVED4', 'DIG_BE_TMDS_DVI_MODE',
'DIG_BE_TMDS_HDMI_MODE', 'DIG_DIGITAL_BYPASS_SEL',
'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB',
'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB',
'DIG_DIGITAL_BYPASS_SEL_36BPP',
'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB',
'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB',
'DIG_DIGITAL_BYPASS_SEL_ALPHA', 'DIG_DIGITAL_BYPASS_SEL_BYPASS',
'DIG_EVEN_PIXEL_ONLY', 'DIG_FE_CNTL_SOURCE_SELECT',
'DIG_FE_CNTL_STEREOSYNC_SELECT', 'DIG_FE_SOURCE_FROM_OTG0',
'DIG_FE_SOURCE_FROM_OTG1', 'DIG_FE_SOURCE_FROM_OTG2',
'DIG_FE_SOURCE_FROM_OTG3', 'DIG_FE_SOURCE_FROM_OTG4',
'DIG_FE_SOURCE_FROM_OTG5', 'DIG_FE_SOURCE_RESERVED',
'DIG_FE_STEREOSYNC_FROM_OTG0', 'DIG_FE_STEREOSYNC_FROM_OTG1',
'DIG_FE_STEREOSYNC_FROM_OTG2', 'DIG_FE_STEREOSYNC_FROM_OTG3',
'DIG_FE_STEREOSYNC_FROM_OTG4', 'DIG_FE_STEREOSYNC_FROM_OTG5',
'DIG_FE_STEREOSYNC_RESERVED', 'DIG_FIFO_ERROR_ACK',
'DIG_FIFO_ERROR_ACK_INT', 'DIG_FIFO_ERROR_NOT_ACK',
'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL',
'DIG_FIFO_FORCE_RECOMP_MINMAX',
'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE',
'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_READ_CLOCK_SRC',
'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG',
'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE',
'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE',
'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX',
'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL',
'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', 'DIG_FIFO_USE_OVERWRITE_LEVEL',
'DIG_INPUT_PIXEL_SEL', 'DIG_IN_DEBUG_MODE',
'DIG_IN_NORMAL_OPERATION', 'DIG_ODD_PIXEL_ONLY',
'DIG_OUTPUT_CRC_CNTL_LINK_SEL', 'DIG_OUTPUT_CRC_DATA_SEL',
'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', 'DIG_OUTPUT_CRC_FOR_AUDIO',
'DIG_OUTPUT_CRC_FOR_FULLFRAME', 'DIG_OUTPUT_CRC_FOR_VBI',
'DIG_OUTPUT_CRC_ON_LINK0', 'DIG_OUTPUT_CRC_ON_LINK1',
'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED',
'DIG_RANDOM_PATTERN_SEED_RAN_PAT',
'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS',
'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH',
'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG',
'DIG_TEST_PATTERN_EXTERNAL_RESET_EN',
'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE',
'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL',
'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM',
'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN',
'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET',
'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', 'DIM_TYPE', 'DIM_TYPE_1D',
'DIM_TYPE_2D', 'DIM_TYPE_3D', 'DIM_TYPE_RESERVED',
'DIOMEM_DISABLE_MEM_PWR_CTRL', 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN',
'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE',
'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN',
'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE',
'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', 'DIOMEM_ENABLE_MEM_PWR_CTRL',
'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', 'DIOMEM_FORCE_LIGHT_SLEEP_REQ',
'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST',
'DIOMEM_FORCE_SHUT_DOWN_REQUEST', 'DIOMEM_NO_FORCE_REQ',
'DIOMEM_NO_FORCE_REQUEST', 'DIOMEM_PWR_DIS_CTRL',
'DIOMEM_PWR_FORCE_CTRL', 'DIOMEM_PWR_FORCE_CTRL2',
'DIOMEM_PWR_SEL_CTRL', 'DIOMEM_PWR_SEL_CTRL2', 'DIO_FIFO_ERROR',
'DIO_FIFO_ERROR_00', 'DIO_FIFO_ERROR_01', 'DIO_FIFO_ERROR_10',
'DIO_FIFO_ERROR_11',
'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE',
'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL',
'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE',
'DISABLE_BINNING_USE_LEGACY_SC', 'DISABLE_BINNING_USE_NEW_SC',
'DISABLE_CLOCK_GATING', 'DISABLE_CLOCK_GATING_IN_DCO',
'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', 'DISABLE_TF0',
'DISABLE_TF1', 'DISABLE_THE_CLOCK', 'DISABLE_THE_FEATURE',
'DISABLE_THE_INTERRUPT', 'DISPCLK_CHG_FWD_CORR_DISABLE',
'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING',
'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING',
'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE',
'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DISPLAY_MICRO_TILING', 'DIV_2',
'DIV_4', 'DIV_8', 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT',
'DI_INDEX_SIZE_8_BIT', 'DI_MAJOR_MODE_0', 'DI_MAJOR_MODE_1',
'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', 'DI_PT_LINELIST_ADJ',
'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ',
'DI_PT_NONE', 'DI_PT_PATCH', 'DI_PT_POINTLIST', 'DI_PT_POLYGON',
'DI_PT_QUADLIST', 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST',
'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ',
'DI_PT_TRISTRIP', 'DI_PT_TRISTRIP_ADJ', 'DI_PT_TRI_WITH_WFLAGS',
'DI_PT_UNUSED_1', 'DI_PT_UNUSED_3', 'DI_PT_UNUSED_4',
'DI_SRC_SEL_AUTO_INDEX', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE',
'DI_SRC_SEL_RESERVED',
'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE',
'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE',
'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE',
'DMDATA_CLEAR_UNDERFLOW_STATUS', 'DMDATA_DONE',
'DMDATA_DONT_CLEAR', 'DMDATA_HARDWARE_UPDATE_MODE', 'DMDATA_MODE',
'DMDATA_NOT_SENT_TO_DIG', 'DMDATA_NOT_UNDERFLOW',
'DMDATA_NOT_UPDATED', 'DMDATA_QOS_LEVEL_FROM_SOFTWARE',
'DMDATA_QOS_LEVEL_FROM_TTU', 'DMDATA_QOS_MODE', 'DMDATA_REPEAT',
'DMDATA_SENT_TO_DIG', 'DMDATA_SOFTWARE_UPDATE_MODE',
'DMDATA_UNDERFLOW', 'DMDATA_UNDERFLOWED',
'DMDATA_UNDERFLOW_CLEAR', 'DMDATA_UPDATED',
'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES',
'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', 'DMDATA_WAS_UPDATED',
'DMU_CLOCK_GATING_DISABLE', 'DMU_CLOCK_ON',
'DMU_CLOCK_STATUS_OFF', 'DMU_CLOCK_STATUS_ON',
'DMU_DC_GPU_TIMER_READ_SELECT', 'DMU_DC_GPU_TIMER_START_POSITION',
'DMU_DISABLE_CLOCK_GATING', 'DMU_ENABLE_CLOCK_GATING',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75',
'DMU_GPU_TIMER_START_0_END_27', 'DMU_GPU_TIMER_START_10_END_37',
'DMU_GPU_TIMER_START_1_END_28', 'DMU_GPU_TIMER_START_2_END_29',
'DMU_GPU_TIMER_START_3_END_30', 'DMU_GPU_TIMER_START_4_END_31',
'DMU_GPU_TIMER_START_6_END_33', 'DMU_GPU_TIMER_START_8_END_35',
'DOLBY_VISION_DISABLED', 'DOLBY_VISION_ENABLE',
'DOLBY_VISION_ENABLED', 'DONUTS', 'DOUT_I2C_ACK',
'DOUT_I2C_ACK_TO_CLEAN',
'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER',
'DOUT_I2C_ARBITRATION_ABORT_XFER',
'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG',
'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG',
'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG',
'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER',
'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO',
'DOUT_I2C_ARBITRATION_SW_PRIORITY',
'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED',
'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED',
'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH',
'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL',
'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED',
'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED',
'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ',
'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ',
'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ',
'DOUT_I2C_CONTROL_DDC_SELECT', 'DOUT_I2C_CONTROL_GO',
'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER',
'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS',
'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER',
'DOUT_I2C_CONTROL_RESET_SW_STATUS',
'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2',
'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4',
'DOUT_I2C_CONTROL_SELECT_DDC5', 'DOUT_I2C_CONTROL_SELECT_DDC6',
'DOUT_I2C_CONTROL_SELECT_DDCVGA', 'DOUT_I2C_CONTROL_SEND_RESET',
'DOUT_I2C_CONTROL_SEND_RESET_LENGTH',
'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER',
'DOUT_I2C_CONTROL_STOP_TRANSFER',
'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0',
'DOUT_I2C_CONTROL_TRANS0_TRANS1',
'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2',
'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3',
'DOUT_I2C_CONTROL_TRANSACTION_COUNT',
'DOUT_I2C_CONTROL__NOT_SEND_RESET',
'DOUT_I2C_CONTROL__SEND_RESET',
'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10',
'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9',
'DOUT_I2C_DATA_INDEX_WRITE', 'DOUT_I2C_DATA__INDEX_WRITE',
'DOUT_I2C_DATA__NOT_INDEX_WRITE',
'DOUT_I2C_DDC_EDID_DETECT_STATUS',
'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR',
'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL',
'DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED',
'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT',
'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT',
'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE',
'DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED',
'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL',
'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA',
'DOUT_I2C_DDC_SPEED_THRESHOLD',
'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO',
'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE',
'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE',
'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE',
'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET',
'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION',
'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION',
'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE',
'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL',
'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE',
'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS',
'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS',
'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DPCSRX_BPHY_PCS_RX0_CLK',
'DPCSRX_BPHY_PCS_RX1_CLK', 'DPCSRX_BPHY_PCS_RX2_CLK',
'DPCSRX_BPHY_PCS_RX3_CLK',
'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL', 'DPCSTX_DVI_LINK_MODE',
'DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER',
'DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER',
'DPCSTX_DVI_LINK_MODE_NORMAL', 'DPHY_8B10B_CUR_DISP',
'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO',
'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET',
'DPHY_8B10B_RESETET', 'DPHY_ATEST_LANE0_PRBS_PATTERN',
'DPHY_ATEST_LANE0_REG_PATTERN', 'DPHY_ATEST_LANE1_PRBS_PATTERN',
'DPHY_ATEST_LANE1_REG_PATTERN', 'DPHY_ATEST_LANE2_PRBS_PATTERN',
'DPHY_ATEST_LANE2_REG_PATTERN', 'DPHY_ATEST_LANE3_PRBS_PATTERN',
'DPHY_ATEST_LANE3_REG_PATTERN', 'DPHY_ATEST_SEL_LANE0',
'DPHY_ATEST_SEL_LANE1', 'DPHY_ATEST_SEL_LANE2',
'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', 'DPHY_CRC_CONTINUOUS',
'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', 'DPHY_CRC_EN',
'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', 'DPHY_CRC_LANE0_SELECTED',
'DPHY_CRC_LANE1_SELECTED', 'DPHY_CRC_LANE2_SELECTED',
'DPHY_CRC_LANE3_SELECTED', 'DPHY_CRC_MST_PHASE_ERROR_ACK',
'DPHY_CRC_MST_PHASE_ERROR_ACKED',
'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT',
'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD',
'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT',
'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0',
'DPHY_FEC_ACTIVE', 'DPHY_FEC_DISABLED', 'DPHY_FEC_ENABLE',
'DPHY_FEC_ENABLED', 'DPHY_FEC_NOT_ACTIVE', 'DPHY_FEC_READY',
'DPHY_FEC_READY_DIS', 'DPHY_FEC_READY_EN',
'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START',
'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW',
'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED',
'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN',
'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL',
'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SKEW_BYPASS',
'DPHY_SW_FAST_TRAINING_NOT_STARTED',
'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED',
'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2',
'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4',
'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL',
'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL',
'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL',
'DPTE_GROUP_SIZE', 'DPTE_GROUP_SIZE_1024B',
'DPTE_GROUP_SIZE_128B', 'DPTE_GROUP_SIZE_2048B',
'DPTE_GROUP_SIZE_256B', 'DPTE_GROUP_SIZE_4096B',
'DPTE_GROUP_SIZE_512B', 'DPTE_GROUP_SIZE_64B',
'DPTE_GROUP_SIZE_8192B', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY',
'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW',
'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW',
'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS',
'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC',
'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG',
'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ',
'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG',
'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG',
'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ',
'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ',
'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED',
'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED',
'DP_AUX_CONTROL_HPD5_SELECTED', 'DP_AUX_CONTROL_HPD6_SELECTED',
'DP_AUX_CONTROL_HPD_SEL', 'DP_AUX_CONTROL_NO_HPD_SELECTED',
'DP_AUX_CONTROL_TEST_MODE', 'DP_AUX_CONTROL_TEST_MODE_DISABLE',
'DP_AUX_CONTROL_TEST_MODE_ENABLE',
'DP_AUX_DEFINITE_ERR_REACHED_ACK',
'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START',
'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD',
'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START',
'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP',
'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START',
'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF',
'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK',
'DP_AUX_ERR_OCCURRED__NOT_ACK',
'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX',
'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ',
'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64',
'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK',
'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK',
'DP_AUX_INT__NOT_ACK', 'DP_AUX_LS_UPDATE_ACK',
'DP_AUX_PHY_WAKE_HIGH_PRIORITY', 'DP_AUX_PHY_WAKE_LOW_PRIORITY',
'DP_AUX_PHY_WAKE_PRIORITY', 'DP_AUX_POTENTIAL_ERR_REACHED_ACK',
'DP_AUX_POTENTIAL_ERR_REACHED__ACK',
'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET',
'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED',
'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE',
'DP_AUX_RESET_SEQUENCE_NOT_DONE', 'DP_AUX_RX_TIMEOUT_LEN_MUL',
'DP_AUX_RX_TIMEOUT_LEN_MUL_2', 'DP_AUX_RX_TIMEOUT_LEN_MUL_4',
'DP_AUX_RX_TIMEOUT_LEN_MUL_8', 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL',
'DP_AUX_SW_CONTROL_LS_READ_TRIG',
'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG',
'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO',
'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO',
'DP_AUX_TX_PRECHARGE_LEN_MUL', 'DP_AUX_TX_PRECHARGE_LEN_MUL_2',
'DP_AUX_TX_PRECHARGE_LEN_MUL_4', 'DP_AUX_TX_PRECHARGE_LEN_MUL_8',
'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', 'DP_COMBINE_FOUR_PIXEL',
'DP_COMBINE_ONE_PIXEL', 'DP_COMBINE_PIXEL_NUM',
'DP_COMBINE_TWO_PIXEL', 'DP_COMPONENT_DEPTH',
'DP_COMPONENT_DEPTH_10BPC', 'DP_COMPONENT_DEPTH_12BPC',
'DP_COMPONENT_DEPTH_16BPC_RESERVED', 'DP_COMPONENT_DEPTH_6BPC',
'DP_COMPONENT_DEPTH_8BPC', 'DP_COMPONENT_DEPTH_RESERVED',
'DP_DPHY_8B10B_EXT_DISP', 'DP_DPHY_8B10B_EXT_DISP_ONE',
'DP_DPHY_8B10B_EXT_DISP_ZERO',
'DP_DPHY_FAST_TRAINING_COMPLETE_ACK',
'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED',
'DP_DPHY_FAST_TRAINING_COMPLETE_MASK',
'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED',
'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED',
'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED',
'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED',
'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN',
'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED',
'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1',
'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS',
'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE',
'DP_DSC_444_SIMPLE_422', 'DP_DSC_DISABLE', 'DP_DSC_MODE',
'DP_DSC_NATIVE_422_420', 'DP_DTO_DESPREAD_DISABLE',
'DP_DTO_DESPREAD_ENABLE', 'DP_DTO_DS_DISABLE',
'DP_EMBEDDED_PANEL', 'DP_EMBEDDED_PANEL_MODE',
'DP_EXTERNAL_PANEL', 'DP_LINK_TRAINING_ALREADY_COMPLETE',
'DP_LINK_TRAINING_COMPLETE', 'DP_LINK_TRAINING_NOT_COMPLETE',
'DP_LINK_TRAINING_SWITCH_MODE', 'DP_LINK_TRAINING_SWITCH_TO_IDLE',
'DP_LINK_TRAINING_SWITCH_TO_VIDEO', 'DP_ML_PHY_SEQ_IMMEDIATE',
'DP_ML_PHY_SEQ_LINE_NUM', 'DP_ML_PHY_SEQ_MODE',
'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE',
'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED',
'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG',
'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG',
'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER',
'DP_MSE_SAT_UPDATE_ACT', 'DP_MSE_SAT_UPDATE_NO_ACTION',
'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER',
'DP_MSE_SAT_UPDATE_WITH_TRIGGER',
'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE',
'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE',
'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER',
'DP_MSO_FOUR_SSTLINK', 'DP_MSO_NUM_OF_SST_LINKS',
'DP_MSO_ONE_SSTLINK', 'DP_MSO_TWO_SSTLINK', 'DP_PIXEL_ENCODING',
'DP_PIXEL_ENCODING_RESERVED', 'DP_PIXEL_ENCODING_RGB444',
'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', 'DP_PIXEL_ENCODING_YCBCR420',
'DP_PIXEL_ENCODING_YCBCR422', 'DP_PIXEL_ENCODING_YCBCR444',
'DP_PIXEL_ENCODING_Y_ONLY', 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ',
'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE',
'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED',
'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY',
'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE',
'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL',
'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG',
'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY',
'DP_SEC_GSP_SEND', 'DP_SEC_GSP_SEND_ANY_LINE',
'DP_SEC_GSP_SEND_PPS', 'DP_SEC_LINE_REFERENCE',
'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', 'DP_SEC_TIMESTAMP_MODE',
'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 'DP_STEER_OVERFLOW_ACK',
'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT',
'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK',
'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK',
'DP_SYNC_POLARITY', 'DP_SYNC_POLARITY_ACTIVE_HIGH',
'DP_SYNC_POLARITY_ACTIVE_LOW', 'DP_TU_OVERFLOW_ACK',
'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT',
'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_UDI_1_LANE', 'DP_UDI_2_LANES',
'DP_UDI_4_LANES', 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED',
'DP_VID_ENHANCED_FRAME_MODE', 'DP_VID_M_1X_INPUT_PIXEL_RATE',
'DP_VID_M_2X_INPUT_PIXEL_RATE', 'DP_VID_M_4X_INPUT_PIXEL_RATE',
'DP_VID_M_8X_INPUT_PIXEL_RATE', 'DP_VID_M_N_CALC_AUTO',
'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE',
'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START',
'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN',
'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_N_MUL',
'DP_VID_STREAM_DISABLE_ACK', 'DP_VID_STREAM_DISABLE_MASK',
'DP_VID_STREAM_DIS_DEFER', 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK',
'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER',
'DP_VID_VBID_FIELD_POL', 'DP_VID_VBID_FIELD_POL_INV',
'DP_VID_VBID_FIELD_POL_NORMAL', 'DRAW_DONE',
'DRR_UPDATE_LOCK_SEL', 'DRR_UPDATE_LOCK_SEL_0',
'DRR_UPDATE_LOCK_SEL_1', 'DRR_UPDATE_LOCK_SEL_2',
'DRR_UPDATE_LOCK_SEL_3', 'DRR_UPDATE_LOCK_SEL_4',
'DRR_UPDATE_LOCK_SEL_5', 'DSCCIF_BITS_PER_COMPONENT_ENUM',
'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT',
'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT',
'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT',
'DSCCIF_ENABLE_ENUM', 'DSCCIF_ENABLE_ENUM_DISABLED',
'DSCCIF_ENABLE_ENUM_ENABLED', 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444',
'DSCC_BITS_PER_COMPONENT_ENUM',
'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT',
'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT',
'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT',
'DSCC_DSC_VERSION_MAJOR_ENUM',
'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION',
'DSCC_DSC_VERSION_MINOR_ENUM',
'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION',
'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION',
'DSCC_ENABLE_ENUM', 'DSCC_ENABLE_ENUM_DISABLED',
'DSCC_ENABLE_ENUM_ENABLED', 'DSCC_ICH_RESET_ENUM',
'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET',
'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET',
'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET',
'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', 'DSCC_LINEBUF_DEPTH_ENUM',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT',
'DSCC_MEM_PWR_DIS_ENUM', 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS',
'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', 'DSCC_MEM_PWR_FORCE_ENUM',
'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST',
'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST',
'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST',
'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST',
'DSCL_MODE_CHROMA_SCALING_BYPASS', 'DSCL_MODE_DSCL_BYPASS',
'DSCL_MODE_LUMA_SCALING_BYPASS', 'DSCL_MODE_SCALING_444_BYPASS',
'DSCL_MODE_SCALING_444_RGB_ENABLE',
'DSCL_MODE_SCALING_444_YCBCR_ENABLE',
'DSCL_MODE_SCALING_YCBCR_ENABLE', 'DSCL_MODE_SEL', 'DSM_DATA_SEL',
'DSM_DATA_SEL_0', 'DSM_DATA_SEL_1', 'DSM_DATA_SEL_BOTH',
'DSM_DATA_SEL_DISABLE', 'DSM_ENABLE_ERROR_INJECT',
'DSM_ENABLE_ERROR_INJECT_FED_IN',
'DSM_ENABLE_ERROR_INJECT_SINGLE',
'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE',
'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED',
'DSM_SELECT_INJECT_DELAY', 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR',
'DSM_SELECT_INJECT_DELAY_NO_DELAY', 'DSM_SINGLE_WRITE',
'DSM_SINGLE_WRITE_DIS', 'DSM_SINGLE_WRITE_EN', 'DS_HW_CAL_DIS',
'DS_HW_CAL_EN', 'DS_HW_CAL_ENABLE', 'DS_JITTER_COUNT_SRC_SEL',
'DS_JITTER_COUNT_SRC_SEL0', 'DS_JITTER_COUNT_SRC_SEL1',
'DS_REF_IS_EXT_GENLOCK', 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN',
'DS_REF_SRC', 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO',
'DVOACLKC_IN_PHASE', 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO',
'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO',
'DVOACLKC_MVP_IN_PHASE', 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO',
'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE',
'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE',
'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE',
'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKD_IN_PHASE',
'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', 'DVOACLK_COARSE_SKEW_CNTL',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT',
'DVOACLK_FINE_SKEW_CNTL', 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP',
'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS',
'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS',
'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP',
'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS',
'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS',
'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS',
'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 'DVO_ENABLE_RST',
'DVO_ENABLE_RST_DISABLE', 'DVO_ENABLE_RST_ENABLE',
'DWB_DATA_DEPTH_WARMUP_10BPC', 'DWB_DATA_DEPTH_WARMUP_8BPC',
'DWB_DATA_DEPTH_WARMUP_ENUM', 'DWB_GMC_WARM_UP_DISABLE',
'DWB_GMC_WARM_UP_ENABLE', 'DWB_GMC_WARM_UP_ENABLE_ENUM',
'DWB_MODE_WARMUP_420', 'DWB_MODE_WARMUP_444',
'DWB_MODE_WARMUP_ENUM', 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE',
'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0',
'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1',
'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE',
'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE',
'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks',
'DbPRTFaultBehavior', 'DbPSLControl', 'DepthArray', 'DepthFormat',
'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z',
'EFC_ACrYCb16161616_10LSB', 'EFC_ACrYCb16161616_10MSB',
'EFC_ACrYCb16161616_12LSB', 'EFC_ACrYCb16161616_12MSB',
'EFC_ACrYCb2101010', 'EFC_ACrYCb8888', 'EFC_ARGB1555',
'EFC_ARGB16161616_10LSB', 'EFC_ARGB16161616_10MSB',
'EFC_ARGB16161616_12LSB', 'EFC_ARGB16161616_12MSB',
'EFC_ARGB16161616_FLOAT', 'EFC_ARGB16161616_SNORM',
'EFC_ARGB16161616_UNORM', 'EFC_ARGB2101010', 'EFC_ARGB4444',
'EFC_ARGB8888', 'EFC_AYCrCb16161616_10LSB',
'EFC_AYCrCb16161616_10MSB', 'EFC_AYCrCb16161616_12LSB',
'EFC_AYCrCb16161616_12MSB', 'EFC_AYCrCb8888', 'EFC_BGR101111_FIX',
'EFC_BGR101111_FLOAT', 'EFC_BGR565',
'EFC_CbYCrY10101010_422_PACKED', 'EFC_CbYCrY12121212_422_PACKED',
'EFC_CbYCrY8888_422_PACKED', 'EFC_CrYCbA1010102',
'EFC_CrYCbA16161616_10LSB', 'EFC_CrYCbA16161616_10MSB',
'EFC_CrYCbA16161616_12LSB', 'EFC_CrYCbA16161616_12MSB',
'EFC_CrYCbA8888', 'EFC_CrYCbY10101010_422_PACKED',
'EFC_CrYCbY12121212_422_PACKED', 'EFC_CrYCbY8888_422_PACKED',
'EFC_MONO_10LSB', 'EFC_MONO_10MSB', 'EFC_MONO_12LSB',
'EFC_MONO_12MSB', 'EFC_MONO_16', 'EFC_MONO_8',
'EFC_RGB111110_FIX', 'EFC_RGB111110_FLOAT', 'EFC_RGB565',
'EFC_RGBA1010102', 'EFC_RGBA16161616_10LSB',
'EFC_RGBA16161616_10MSB', 'EFC_RGBA16161616_12LSB',
'EFC_RGBA16161616_12MSB', 'EFC_RGBA16161616_FLOAT',
'EFC_RGBA16161616_SNORM', 'EFC_RGBA16161616_UNORM',
'EFC_RGBA4444', 'EFC_RGBA5551', 'EFC_RGBA8888',
'EFC_SURFACE_PIXEL_FORMAT', 'EFC_Y10_CbCr1010_420_PLANAR',
'EFC_Y10_CrCb1010_420_PLANAR', 'EFC_Y12_CbCr1212_420_PLANAR',
'EFC_Y12_CrCb1212_420_PLANAR', 'EFC_Y8_CbCr88_420_PLANAR',
'EFC_Y8_CrCb88_420_PLANAR', 'EFC_YCbYCr10101010_422_PACKED',
'EFC_YCbYCr12121212_422_PACKED', 'EFC_YCbYCr8888_422_PACKED',
'EFC_YCrCbA16161616_10LSB', 'EFC_YCrCbA16161616_10MSB',
'EFC_YCrCbA16161616_12LSB', 'EFC_YCrCbA16161616_12MSB',
'EFC_YCrCbA8888', 'EFC_YCrYCb10101010_422_PACKED',
'EFC_YCrYCb12121212_422_PACKED', 'EFC_YCrYCb8888_422_PACKED',
'EIGHT_BANKS', 'EIGHT_FRAGMENTS', 'EIGHT_PIPES',
'EIGHT_SHADER_ENGINS', 'ENABLE', 'ENABLE_CLOCK', 'ENABLE_ENUM',
'ENABLE_ENUM_DISABLED', 'ENABLE_ENUM_ENABLED',
'ENABLE_JITTER_REMOVAL', 'ENABLE_LEGACY_PIPELINE',
'ENABLE_MEM_PWR_CTRL', 'ENABLE_NGG_PIPELINE', 'ENABLE_THE_CLOCK',
'ENABLE_THE_FEATURE', 'ENABLE_THE_INTERRUPT', 'ENDIAN_8IN16',
'ENDIAN_8IN32', 'ENDIAN_8IN64', 'ENDIAN_NONE',
'END_OF_PIPE_IB_END', 'END_OF_PIPE_INCR_DE',
'ENGG_CSB_DELAY_BIN00', 'ENGG_CSB_DELAY_BIN01',
'ENGG_CSB_DELAY_BIN02', 'ENGG_CSB_DELAY_BIN03',
'ENGG_CSB_DELAY_BIN04', 'ENGG_CSB_DELAY_BIN05',
'ENGG_CSB_DELAY_BIN06', 'ENGG_CSB_DELAY_BIN07',
'ENGG_CSB_DELAY_BIN08', 'ENGG_CSB_DELAY_BIN09',
'ENGG_CSB_DELAY_BIN10', 'ENGG_CSB_DELAY_BIN11',
'ENGG_CSB_DELAY_BIN12', 'ENGG_CSB_DELAY_BIN13',
'ENGG_CSB_DELAY_BIN14', 'ENGG_CSB_DELAY_BIN15',
'ENGG_CSB_GE_INPUT_FIFO_FULL', 'ENGG_CSB_GE_SENDING_SUBGROUP',
'ENGG_CSB_MACHINE_IS_STARVED',
'ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY',
'ENGG_CSB_MACHINE_STALLED_BY_SPI',
'ENGG_CSB_OBJECTID_INPUT_FIFO_FULL', 'ENGG_CSB_PRIM_COUNT_EQ0',
'ENGG_CSB_SPI_DELAY_BIN00', 'ENGG_CSB_SPI_DELAY_BIN01',
'ENGG_CSB_SPI_DELAY_BIN02', 'ENGG_CSB_SPI_DELAY_BIN03',
'ENGG_CSB_SPI_DELAY_BIN04', 'ENGG_CSB_SPI_DELAY_BIN05',
'ENGG_CSB_SPI_DELAY_BIN06', 'ENGG_CSB_SPI_DELAY_BIN07',
'ENGG_CSB_SPI_DELAY_BIN08', 'ENGG_CSB_SPI_DELAY_BIN09',
'ENGG_CSB_SPI_DELAY_BIN10', 'ENGG_CSB_SPI_DELAY_BIN11',
'ENGG_CSB_SPI_DELAY_BIN12', 'ENGG_CSB_SPI_DELAY_BIN13',
'ENGG_CSB_SPI_DELAY_BIN14', 'ENGG_CSB_SPI_DELAY_BIN15',
'ENGG_CSB_SPI_INPUT_FIFO_FULL',
'ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE',
'ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE',
'ENGG_INDEX_PRIM_IF_QUALIFIED_BUSY',
'ENGG_INDEX_PRIM_IF_QUALIFIED_STARVED',
'ENGG_INDEX_PRIM_IF_REUSE_0_NEW_VERTS_THIS_PRIM',
'ENGG_INDEX_PRIM_IF_REUSE_1_NEW_VERTS_THIS_PRIM',
'ENGG_INDEX_PRIM_IF_REUSE_2_NEW_VERTS_THIS_PRIM',
'ENGG_INDEX_PRIM_IF_REUSE_3_NEW_VERTS_THIS_PRIM',
'ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO',
'ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO',
'ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM',
'ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL',
'ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL',
'ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', 'ENGG_INDEX_REQ_STARVED',
'ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY',
'ENGG_INDEX_RET_REQ2RTN_FIFO_FULL',
'ENGG_INDEX_RET_SXRX_READING_EVENT',
'ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP',
'ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL',
'ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL',
'ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL',
'ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL',
'ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS',
'ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS',
'ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS',
'ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0',
'ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO',
'ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO',
'ENGG_INDEX_RET_SXRX_STARVED_BY_CSB',
'ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS',
'ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL',
'ENGG_POS_REQ_STALLED_BY_FULL_CLIPV_FIFO', 'ENGG_POS_REQ_STARVED',
'ENUMS_GDS_PERFCOUNT_SELECT_H', 'ENUM_DPG_BIT_DEPTH',
'ENUM_DPG_BIT_DEPTH_10BPC', 'ENUM_DPG_BIT_DEPTH_12BPC',
'ENUM_DPG_BIT_DEPTH_6BPC', 'ENUM_DPG_BIT_DEPTH_8BPC',
'ENUM_DPG_DISABLE', 'ENUM_DPG_DYNAMIC_RANGE',
'ENUM_DPG_DYNAMIC_RANGE_CEA', 'ENUM_DPG_DYNAMIC_RANGE_VESA',
'ENUM_DPG_EN', 'ENUM_DPG_ENABLE', 'ENUM_DPG_FIELD_POLARITY',
'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD',
'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', 'ENUM_DPG_MODE',
'ENUM_DPG_MODE_HORIZONTAL_BAR', 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK',
'ENUM_DPG_MODE_RGB_DUAL_RAMP', 'ENUM_DPG_MODE_RGB_SINGLE_RAMP',
'ENUM_DPG_MODE_RGB_XR_BIAS', 'ENUM_DPG_MODE_VERTICAL_BAR',
'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK',
'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK',
'ENUM_FMT_PTI_FIELD_POLARITY',
'ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD',
'ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN',
'ENUM_NUM_SIMD_PER_CU', 'ES_STAGE_DS', 'ES_STAGE_OFF',
'ES_STAGE_REAL', 'EXPORT_16_16_FLOAT_8PIX',
'EXPORT_16_16_SIGNED_8PIX', 'EXPORT_16_16_UNSIGNED_8PIX',
'EXPORT_2C_32BPC_AR', 'EXPORT_2C_32BPC_GR',
'EXPORT_2P_32BPC_ABGR', 'EXPORT_32BPP_8PIX', 'EXPORT_32_ABGR',
'EXPORT_32_AR', 'EXPORT_32_GR', 'EXPORT_32_R', 'EXPORT_4C_16BPC',
'EXPORT_4C_32BPC', 'EXPORT_4P_16BPC_ABGR', 'EXPORT_4P_32BPC_ABGR',
'EXPORT_4P_32BPC_AR', 'EXPORT_4P_32BPC_GR', 'EXPORT_8P_32BPC_R',
'EXPORT_ANY_Z', 'EXPORT_FP16_ABGR', 'EXPORT_GREATER_THAN_Z',
'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'EXPORT_SIGNED16_ABGR',
'EXPORT_UNSIGNED16_ABGR', 'EXPORT_UNUSED', 'FAULT_FAIL',
'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', 'FEC_ACTIVE_STATUS',
'FIX_S2_13', 'FIX_S3_12', 'FLIP_ANY_FRAME', 'FLIP_LEFT_EYE',
'FLIP_RATE', 'FLIP_RATE_0', 'FLIP_RATE_1', 'FLIP_RATE_2',
'FLIP_RATE_3', 'FLIP_RATE_4', 'FLIP_RATE_5', 'FLIP_RATE_6',
'FLIP_RATE_7', 'FLIP_RIGHT_EYE', 'FLUSH_AND_INV_CB_DATA_TS',
'FLUSH_AND_INV_CB_META', 'FLUSH_AND_INV_CB_PIXEL_DATA',
'FLUSH_AND_INV_DB_DATA_TS', 'FLUSH_AND_INV_DB_META',
'FLUSH_CONTROL_FLUSH_NOT_STARTED', 'FLUSH_CONTROL_FLUSH_STARTED',
'FLUSH_DFSM', 'FLUSH_ES_OUTPUT', 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS',
'FMTMEM_DISABLE_MEM_PWR_CTRL', 'FMTMEM_ENABLE_MEM_PWR_CTRL',
'FMTMEM_FORCE_DEEP_SLEEP_REQUEST',
'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST',
'FMTMEM_FORCE_SHUT_DOWN_REQUEST', 'FMTMEM_NO_FORCE_REQUEST',
'FMTMEM_PWR_DIS_CTRL', 'FMTMEM_PWR_FORCE_CTRL', 'FMT_1',
'FMT_10_10_10_2', 'FMT_10_11_11', 'FMT_10_11_11_FLOAT',
'FMT_11_11_10', 'FMT_11_11_10_FLOAT', 'FMT_16', 'FMT_16_16',
'FMT_16_16_16', 'FMT_16_16_16_16', 'FMT_16_16_16_16_FLOAT',
'FMT_16_16_16_FLOAT', 'FMT_16_16_FLOAT', 'FMT_16_FLOAT',
'FMT_1_5_5_5', 'FMT_1_REVERSED', 'FMT_24_8', 'FMT_24_8_FLOAT',
'FMT_2_10_10_10', 'FMT_32', 'FMT_32_32', 'FMT_32_32_32',
'FMT_32_32_32_32', 'FMT_32_32_32_32_FLOAT', 'FMT_32_32_32_FLOAT',
'FMT_32_32_FLOAT', 'FMT_32_AS_32_32_32_32', 'FMT_32_AS_8',
'FMT_32_AS_8_8', 'FMT_32_FLOAT', 'FMT_3_3_2', 'FMT_4_4',
'FMT_4_4_4_4', 'FMT_5_5_5_1', 'FMT_5_6_5',
'FMT_5_9_9_9_SHAREDEXP', 'FMT_6_5_5', 'FMT_8', 'FMT_8_24',
'FMT_8_24_FLOAT', 'FMT_8_8', 'FMT_8_8_8', 'FMT_8_8_8_8',
'FMT_APC3', 'FMT_APC4', 'FMT_APC5', 'FMT_APC6', 'FMT_APC7',
'FMT_BC1', 'FMT_BC2', 'FMT_BC3', 'FMT_BC4', 'FMT_BC5', 'FMT_BC6',
'FMT_BC7', 'FMT_BG_RG', 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED',
'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH',
'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP',
'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP',
'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION',
'FMT_CLAMP_CNTL_COLOR_FORMAT',
'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC',
'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC',
'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC',
'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC',
'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE',
'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1',
'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2',
'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3',
'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS',
'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE',
'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE',
'FMT_CONTROL_PIXEL_ENCODING',
'FMT_CONTROL_PIXEL_ENCODING_RESERVED',
'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444',
'FMT_CONTROL_PIXEL_ENCODING_YCBCR420',
'FMT_CONTROL_PIXEL_ENCODING_YCBCR422',
'FMT_CONTROL_SUBSAMPLING_MODE',
'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE',
'FMT_CONTROL_SUBSAMPLING_MODE_DROP',
'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP',
'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED',
'FMT_CONTROL_SUBSAMPLING_ORDER',
'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR',
'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', 'FMT_CTX1',
'FMT_DYNAMIC_EXP_MODE', 'FMT_DYNAMIC_EXP_MODE_10to12',
'FMT_DYNAMIC_EXP_MODE_8to12', 'FMT_FRAME_RANDOM_ENABLE_CONTROL',
'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME',
'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', 'FMT_GB_GR', 'FMT_INVALID',
'FMT_POWER_STATE_ENUM', 'FMT_POWER_STATE_ENUM_DS',
'FMT_POWER_STATE_ENUM_LS', 'FMT_POWER_STATE_ENUM_ON',
'FMT_POWER_STATE_ENUM_SD', 'FMT_RESERVED_33', 'FMT_RESERVED_36',
'FMT_RESERVED_4', 'FMT_RESERVED_63',
'FMT_RGB_RANDOM_ENABLE_CONTROL',
'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE',
'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED',
'FMT_SPATIAL_DITHER_MODE', 'FMT_SPATIAL_DITHER_MODE_0',
'FMT_SPATIAL_DITHER_MODE_1', 'FMT_SPATIAL_DITHER_MODE_2',
'FMT_SPATIAL_DITHER_MODE_3', 'FMT_STEREOSYNC_OVERRIDE_CONTROL',
'FMT_STEREOSYNC_OVERRIDE_CONTROL_0',
'FMT_STEREOSYNC_OVERRIDE_CONTROL_1',
'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0',
'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR',
'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB',
'FMT_X24_8_32_FLOAT', 'FORCE_00', 'FORCE_BINNING_ON',
'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', 'FORCE_EARLY_Z',
'FORCE_ENABLE', 'FORCE_FF', 'FORCE_LATE_Z',
'FORCE_LIGHT_SLEEP_REQ', 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF',
'FORCE_OPT_AUTO', 'FORCE_OPT_DISABLE',
'FORCE_OPT_ENABLE_IF_SRC_ARGB_0',
'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0',
'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0',
'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z',
'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH',
'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF',
'FOUR_BANKS', 'FOUR_FRAGMENTS', 'FOUR_PIPES', 'FOUR_RB_PER_SE',
'FOUR_SHADER_ENGINS', 'FRAG_ALWAYS', 'FRAG_EQUAL', 'FRAG_GEQUAL',
'FRAG_GREATER', 'FRAG_LEQUAL', 'FRAG_LESS', 'FRAG_NEVER',
'FRAG_NOTEQUAL', 'FULL_TILE_WAVE_BREAK_BC_ONLY',
'FULL_TILE_WAVE_BREAK_BOTH', 'FULL_TILE_WAVE_BREAK_NBC_ONLY',
'FULL_TILE_WAVE_BREAK_NONE', 'ForceControl', 'FullTileWaveBreak',
'GAMUT_COEF', 'GAMUT_COEF_B', 'GATCL1RequestType',
'GATCL1_TYPE_BYPASS', 'GATCL1_TYPE_NORMAL',
'GATCL1_TYPE_SHOOTDOWN', 'GB_EDC_DED_MODE',
'GB_EDC_DED_MODE_HALT', 'GB_EDC_DED_MODE_INT_HALT',
'GB_EDC_DED_MODE_LOG', 'GCRPerfSel', 'GCR_PERF_SEL_ALL_REQ',
'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ',
'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ',
'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ',
'GCR_PERF_SEL_CPC_ALL_REQ', 'GCR_PERF_SEL_CPC_GL1_ALL_REQ',
'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPC_GL2_ALL_REQ',
'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPC_METADATA_REQ',
'GCR_PERF_SEL_CPC_SQC_DATA_REQ', 'GCR_PERF_SEL_CPC_SQC_INST_REQ',
'GCR_PERF_SEL_CPC_TCP_REQ',
'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_CPF_ALL_REQ', 'GCR_PERF_SEL_CPF_GL1_ALL_REQ',
'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPF_GL2_ALL_REQ',
'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPF_METADATA_REQ',
'GCR_PERF_SEL_CPF_SQC_DATA_REQ', 'GCR_PERF_SEL_CPF_SQC_INST_REQ',
'GCR_PERF_SEL_CPF_TCP_REQ',
'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_CPG_ALL_REQ', 'GCR_PERF_SEL_CPG_GL1_ALL_REQ',
'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPG_GL2_ALL_REQ',
'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPG_METADATA_REQ',
'GCR_PERF_SEL_CPG_SQC_DATA_REQ', 'GCR_PERF_SEL_CPG_SQC_INST_REQ',
'GCR_PERF_SEL_CPG_TCP_REQ',
'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', 'GCR_PERF_SEL_NONE',
'GCR_PERF_SEL_PHY_REQ', 'GCR_PERF_SEL_SDMA0_ALL_REQ',
'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ',
'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ',
'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ',
'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ',
'GCR_PERF_SEL_SDMA0_METADATA_REQ',
'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ',
'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA0_TCP_REQ',
'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_SDMA1_ALL_REQ', 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ',
'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ',
'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ',
'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ',
'GCR_PERF_SEL_SDMA1_METADATA_REQ',
'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ',
'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA1_TCP_REQ',
'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ',
'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ',
'GCR_PERF_SEL_UTCL2_FILTERED_RET',
'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ',
'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT',
'GCR_PERF_SEL_UTCL2_REQ', 'GCR_PERF_SEL_UTCL2_RET',
'GCR_PERF_SEL_VIRT_REQ', 'GDS_PERFCOUNT_SELECT',
'GDS_PERF_SEL_DS_ADDR_CONFL', 'GDS_PERF_SEL_DS_BANK_CONFL',
'GDS_PERF_SEL_GWS_BYPASS', 'GDS_PERF_SEL_GWS_RELEASED',
'GDS_PERF_SEL_RBUF_HIT', 'GDS_PERF_SEL_RBUF_MISS',
'GDS_PERF_SEL_SE0_SH0_2COMP_REQ',
'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP',
'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP',
'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID',
'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP',
'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP',
'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP',
'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD',
'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH0_NORET',
'GDS_PERF_SEL_SE0_SH0_ORD_CNT',
'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH0_RET',
'GDS_PERF_SEL_SE0_SH1_2COMP_REQ',
'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP',
'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP',
'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID',
'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP',
'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP',
'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP',
'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD',
'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH1_NORET',
'GDS_PERF_SEL_SE0_SH1_ORD_CNT',
'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH1_RET',
'GDS_PERF_SEL_SE1_SH0_2COMP_REQ',
'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP',
'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP',
'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID',
'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP',
'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP',
'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP',
'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD',
'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH0_NORET',
'GDS_PERF_SEL_SE1_SH0_ORD_CNT',
'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH0_RET',
'GDS_PERF_SEL_SE1_SH1_2COMP_REQ',
'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP',
'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP',
'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID',
'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP',
'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP',
'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP',
'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD',
'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH1_NORET',
'GDS_PERF_SEL_SE1_SH1_ORD_CNT',
'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH1_RET',
'GDS_PERF_SEL_SE2_SH0_2COMP_REQ',
'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP',
'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP',
'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID',
'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP',
'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP',
'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP',
'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD',
'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH0_NORET',
'GDS_PERF_SEL_SE2_SH0_ORD_CNT',
'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH0_RET',
'GDS_PERF_SEL_SE2_SH1_2COMP_REQ',
'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP',
'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP',
'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID',
'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP',
'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP',
'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP',
'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD',
'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH1_NORET',
'GDS_PERF_SEL_SE2_SH1_ORD_CNT',
'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH1_RET',
'GDS_PERF_SEL_SE3_SH0_2COMP_REQ',
'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP',
'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP',
'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID',
'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP',
'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP',
'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP',
'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD',
'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH0_NORET',
'GDS_PERF_SEL_SE3_SH0_ORD_CNT',
'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH0_RET',
'GDS_PERF_SEL_SE3_SH1_2COMP_REQ',
'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP',
'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP',
'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID',
'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP',
'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP',
'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP',
'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD',
'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH1_NORET',
'GDS_PERF_SEL_SE3_SH1_ORD_CNT',
'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH1_RET',
'GDS_PERF_SEL_WBUF_FLUSH', 'GDS_PERF_SEL_WBUF_WR',
'GDS_PERF_SEL_WR_COMP', 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE',
'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE',
'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL',
'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED',
'GENERIC_STEREOSYNC_SEL', 'GENERIC_STEREOSYNC_SEL_D1',
'GENERIC_STEREOSYNC_SEL_D2', 'GENERIC_STEREOSYNC_SEL_D3',
'GENERIC_STEREOSYNC_SEL_D4', 'GENERIC_STEREOSYNC_SEL_D5',
'GENERIC_STEREOSYNC_SEL_D6', 'GENERIC_STEREOSYNC_SEL_RESERVED',
'GE_PERFCOUNT_SELECT', 'GL0V_CACHE_POLICIES',
'GL0V_CACHE_POLICY_HIT_EVICT', 'GL0V_CACHE_POLICY_HIT_LRU',
'GL0V_CACHE_POLICY_MISS_EVICT', 'GL0V_CACHE_POLICY_MISS_LRU',
'GL1A_PERF_SEL', 'GL1A_PERF_SEL_ARB_REQUESTS',
'GL1A_PERF_SEL_BUSY', 'GL1A_PERF_SEL_CYCLE',
'GL1A_PERF_SEL_IO_32B_WDS_GL1C0',
'GL1A_PERF_SEL_IO_32B_WDS_GL1C1',
'GL1A_PERF_SEL_IO_32B_WDS_GL1C2',
'GL1A_PERF_SEL_IO_32B_WDS_GL1C3',
'GL1A_PERF_SEL_IO_32B_WDS_GL1C4',
'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0',
'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1',
'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2',
'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3',
'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4',
'GL1A_PERF_SEL_MEM_32B_WDS_GL1C0',
'GL1A_PERF_SEL_MEM_32B_WDS_GL1C1',
'GL1A_PERF_SEL_MEM_32B_WDS_GL1C2',
'GL1A_PERF_SEL_MEM_32B_WDS_GL1C3',
'GL1A_PERF_SEL_MEM_32B_WDS_GL1C4',
'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0',
'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1',
'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2',
'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3',
'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4',
'GL1A_PERF_SEL_REQUEST_GL1C0', 'GL1A_PERF_SEL_REQUEST_GL1C1',
'GL1A_PERF_SEL_REQUEST_GL1C2', 'GL1A_PERF_SEL_REQUEST_GL1C3',
'GL1A_PERF_SEL_REQUEST_GL1C4', 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL',
'GL1A_PERF_SEL_STALL_GL1C0', 'GL1A_PERF_SEL_STALL_GL1C1',
'GL1A_PERF_SEL_STALL_GL1C2', 'GL1A_PERF_SEL_STALL_GL1C3',
'GL1A_PERF_SEL_STALL_GL1C4',
'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0',
'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1',
'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2',
'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3',
'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4', 'GL1CG_PERF_SEL',
'GL1CG_PERF_SEL_CORE_REG_SCLK_VLD', 'GL1CG_PERF_SEL_CYCLE',
'GL1CG_PERF_SEL_GATE_EN1', 'GL1CG_PERF_SEL_GATE_EN2',
'GL1CG_PERF_SEL_REQ', 'GL1CG_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES',
'GL1CG_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES', 'GL1C_PERF_SEL',
'GL1C_PERF_SEL_CORE_REG_SCLK_VLD', 'GL1C_PERF_SEL_CYCLE',
'GL1C_PERF_SEL_GATE_EN1', 'GL1C_PERF_SEL_GATE_EN2',
'GL1C_PERF_SEL_REQ', 'GL1C_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES',
'GL1C_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES', 'GL1_CACHE_POLICIES',
'GL1_CACHE_POLICY_HIT_EVICT', 'GL1_CACHE_POLICY_HIT_LRU',
'GL1_CACHE_POLICY_MISS_EVICT', 'GL1_CACHE_POLICY_MISS_LRU',
'GL1_CACHE_STORE_POLICIES', 'GL1_CACHE_STORE_POLICY_BYPASS',
'GL2A_PERF_SEL', 'GL2A_PERF_SEL_BUSY', 'GL2A_PERF_SEL_CYCLE',
'GL2A_PERF_SEL_NONE', 'GL2A_PERF_SEL_REQ_BURST_GL2C0',
'GL2A_PERF_SEL_REQ_BURST_GL2C1', 'GL2A_PERF_SEL_REQ_BURST_GL2C2',
'GL2A_PERF_SEL_REQ_BURST_GL2C3', 'GL2A_PERF_SEL_REQ_BURST_GL2C4',
'GL2A_PERF_SEL_REQ_BURST_GL2C5', 'GL2A_PERF_SEL_REQ_BURST_GL2C6',
'GL2A_PERF_SEL_REQ_BURST_GL2C7', 'GL2A_PERF_SEL_REQ_GL2C0',
'GL2A_PERF_SEL_REQ_GL2C1', 'GL2A_PERF_SEL_REQ_GL2C2',
'GL2A_PERF_SEL_REQ_GL2C3', 'GL2A_PERF_SEL_REQ_GL2C4',
'GL2A_PERF_SEL_REQ_GL2C5', 'GL2A_PERF_SEL_REQ_GL2C6',
'GL2A_PERF_SEL_REQ_GL2C7', 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7',
'GL2A_PERF_SEL_REQ_STALL_GL2C0', 'GL2A_PERF_SEL_REQ_STALL_GL2C1',
'GL2A_PERF_SEL_REQ_STALL_GL2C2', 'GL2A_PERF_SEL_REQ_STALL_GL2C3',
'GL2A_PERF_SEL_REQ_STALL_GL2C4', 'GL2A_PERF_SEL_REQ_STALL_GL2C5',
'GL2A_PERF_SEL_REQ_STALL_GL2C6', 'GL2A_PERF_SEL_REQ_STALL_GL2C7',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7',
'GL2A_PERF_SEL_RTN_CLIENT0', 'GL2A_PERF_SEL_RTN_CLIENT1',
'GL2A_PERF_SEL_RTN_CLIENT2', 'GL2A_PERF_SEL_RTN_CLIENT3',
'GL2A_PERF_SEL_RTN_CLIENT4', 'GL2A_PERF_SEL_RTN_CLIENT5',
'GL2A_PERF_SEL_RTN_CLIENT6', 'GL2A_PERF_SEL_RTN_CLIENT7',
'GL2A_PERF_SEL_RTN_STALL_GL2C0', 'GL2A_PERF_SEL_RTN_STALL_GL2C1',
'GL2A_PERF_SEL_RTN_STALL_GL2C2', 'GL2A_PERF_SEL_RTN_STALL_GL2C3',
'GL2A_PERF_SEL_RTN_STALL_GL2C4', 'GL2A_PERF_SEL_RTN_STALL_GL2C5',
'GL2A_PERF_SEL_RTN_STALL_GL2C6', 'GL2A_PERF_SEL_RTN_STALL_GL2C7',
'GL2C_PERF_SEL', 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT',
'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT',
'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE',
'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE',
'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK',
'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START',
'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START',
'GL2C_PERF_SEL_ATOMIC', 'GL2C_PERF_SEL_BUBBLE',
'GL2C_PERF_SEL_BUSY', 'GL2C_PERF_SEL_BYPASS_REQ',
'GL2C_PERF_SEL_CLIENT0_REQ', 'GL2C_PERF_SEL_CLIENT1_REQ',
'GL2C_PERF_SEL_CLIENT2_REQ', 'GL2C_PERF_SEL_CLIENT3_REQ',
'GL2C_PERF_SEL_CLIENT4_REQ', 'GL2C_PERF_SEL_CLIENT5_REQ',
'GL2C_PERF_SEL_CLIENT6_REQ', 'GL2C_PERF_SEL_CLIENT7_REQ',
'GL2C_PERF_SEL_CM_CHANNEL0_REQ', 'GL2C_PERF_SEL_CM_CHANNEL10_REQ',
'GL2C_PERF_SEL_CM_CHANNEL11_REQ',
'GL2C_PERF_SEL_CM_CHANNEL12_REQ',
'GL2C_PERF_SEL_CM_CHANNEL13_REQ',
'GL2C_PERF_SEL_CM_CHANNEL14_REQ',
'GL2C_PERF_SEL_CM_CHANNEL15_REQ',
'GL2C_PERF_SEL_CM_CHANNEL16_REQ',
'GL2C_PERF_SEL_CM_CHANNEL17_REQ',
'GL2C_PERF_SEL_CM_CHANNEL18_REQ',
'GL2C_PERF_SEL_CM_CHANNEL19_REQ', 'GL2C_PERF_SEL_CM_CHANNEL1_REQ',
'GL2C_PERF_SEL_CM_CHANNEL20_REQ',
'GL2C_PERF_SEL_CM_CHANNEL21_REQ',
'GL2C_PERF_SEL_CM_CHANNEL22_REQ',
'GL2C_PERF_SEL_CM_CHANNEL23_REQ',
'GL2C_PERF_SEL_CM_CHANNEL24_REQ',
'GL2C_PERF_SEL_CM_CHANNEL25_REQ',
'GL2C_PERF_SEL_CM_CHANNEL26_REQ',
'GL2C_PERF_SEL_CM_CHANNEL27_REQ',
'GL2C_PERF_SEL_CM_CHANNEL28_REQ',
'GL2C_PERF_SEL_CM_CHANNEL29_REQ', 'GL2C_PERF_SEL_CM_CHANNEL2_REQ',
'GL2C_PERF_SEL_CM_CHANNEL30_REQ',
'GL2C_PERF_SEL_CM_CHANNEL31_REQ', 'GL2C_PERF_SEL_CM_CHANNEL3_REQ',
'GL2C_PERF_SEL_CM_CHANNEL4_REQ', 'GL2C_PERF_SEL_CM_CHANNEL5_REQ',
'GL2C_PERF_SEL_CM_CHANNEL6_REQ', 'GL2C_PERF_SEL_CM_CHANNEL7_REQ',
'GL2C_PERF_SEL_CM_CHANNEL8_REQ', 'GL2C_PERF_SEL_CM_CHANNEL9_REQ',
'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ',
'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ',
'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ',
'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ',
'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ',
'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ',
'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ',
'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ',
'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ',
'GL2C_PERF_SEL_CM_COMP_READ_REQ',
'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ',
'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ',
'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ',
'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ',
'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ',
'GL2C_PERF_SEL_CM_DCC_STALL', 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ',
'GL2C_PERF_SEL_CM_MERGE_BUF_FULL',
'GL2C_PERF_SEL_CM_METADATA_WR_REQ', 'GL2C_PERF_SEL_CM_NOOP_REQ',
'GL2C_PERF_SEL_CM_NO_ACK_REQ', 'GL2C_PERF_SEL_CM_READ_BACK_REQ',
'GL2C_PERF_SEL_CM_RVF_FULL', 'GL2C_PERF_SEL_CM_SDR_FULL',
'GL2C_PERF_SEL_CM_WR_ACK_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_REQ', 'GL2C_PERF_SEL_CYCLE',
'GL2C_PERF_SEL_C_RO_S_REQ', 'GL2C_PERF_SEL_C_RO_US_REQ',
'GL2C_PERF_SEL_C_RW_S_REQ', 'GL2C_PERF_SEL_C_RW_US_REQ',
'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'GL2C_PERF_SEL_EA_ATOMIC',
'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', 'GL2C_PERF_SEL_EA_RDREQ_128B',
'GL2C_PERF_SEL_EA_RDREQ_32B', 'GL2C_PERF_SEL_EA_RDREQ_64B',
'GL2C_PERF_SEL_EA_RDREQ_96B', 'GL2C_PERF_SEL_EA_RDREQ_DRAM',
'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B',
'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL',
'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL',
'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL',
'GL2C_PERF_SEL_EA_RDREQ_SPLIT', 'GL2C_PERF_SEL_EA_RDRET_NACK',
'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B',
'GL2C_PERF_SEL_EA_RD_MDC_32B', 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B',
'GL2C_PERF_SEL_EA_WRREQ_64B', 'GL2C_PERF_SEL_EA_WRREQ_DRAM',
'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B',
'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL',
'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL',
'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL',
'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND',
'GL2C_PERF_SEL_EA_WRRET_NACK', 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B',
'GL2C_PERF_SEL_EVICT', 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT',
'GL2C_PERF_SEL_FULL_HIT', 'GL2C_PERF_SEL_GARLIC_READ',
'GL2C_PERF_SEL_GARLIC_WRITE', 'GL2C_PERF_SEL_GCR_ALL',
'GL2C_PERF_SEL_GCR_DISCARD', 'GL2C_PERF_SEL_GCR_GL2_INV_ALL',
'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', 'GL2C_PERF_SEL_GCR_GL2_WB_ALL',
'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE',
'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', 'GL2C_PERF_SEL_GCR_INV',
'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE',
'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT',
'GL2C_PERF_SEL_GCR_INVL2_VOL_START', 'GL2C_PERF_SEL_GCR_MDC_INV',
'GL2C_PERF_SEL_GCR_MDC_INV_ALL',
'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', 'GL2C_PERF_SEL_GCR_RANGE',
'GL2C_PERF_SEL_GCR_UNSHARED', 'GL2C_PERF_SEL_GCR_VOL',
'GL2C_PERF_SEL_GCR_WB', 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE',
'GL2C_PERF_SEL_GCR_WBINVL2_EVICT',
'GL2C_PERF_SEL_GCR_WBINVL2_START',
'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE',
'GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT',
'GL2C_PERF_SEL_GCR_WBL2_VOL_START', 'GL2C_PERF_SEL_GL2A_LEVEL',
'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', 'GL2C_PERF_SEL_HIT',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO',
'GL2C_PERF_SEL_IB_CM_STALL', 'GL2C_PERF_SEL_IB_REQ',
'GL2C_PERF_SEL_IB_STALL', 'GL2C_PERF_SEL_IB_TAG_STALL',
'GL2C_PERF_SEL_INTERNAL_PROBE', 'GL2C_PERF_SEL_IO_READ',
'GL2C_PERF_SEL_IO_WRITE', 'GL2C_PERF_SEL_LATENCY_FIFO_FULL',
'GL2C_PERF_SEL_LRU_REQ', 'GL2C_PERF_SEL_MC_RDREQ',
'GL2C_PERF_SEL_MC_RDREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ',
'GL2C_PERF_SEL_MC_WRREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ_STALL',
'GL2C_PERF_SEL_MDC_INV_METADATA', 'GL2C_PERF_SEL_MDC_LEVEL',
'GL2C_PERF_SEL_MDC_REQ', 'GL2C_PERF_SEL_MDC_SECTOR_HIT',
'GL2C_PERF_SEL_MDC_SECTOR_MISS',
'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL',
'GL2C_PERF_SEL_MDC_TAG_HIT',
'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL',
'GL2C_PERF_SEL_MDC_TAG_STALL',
'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL',
'GL2C_PERF_SEL_METADATA_READ_REQ', 'GL2C_PERF_SEL_MISS',
'GL2C_PERF_SEL_NOA_REQ', 'GL2C_PERF_SEL_NONE',
'GL2C_PERF_SEL_NOP_ACK', 'GL2C_PERF_SEL_NOP_RTN0',
'GL2C_PERF_SEL_NORMAL_EVICT', 'GL2C_PERF_SEL_NORMAL_WRITEBACK',
'GL2C_PERF_SEL_ONION_READ', 'GL2C_PERF_SEL_ONION_WRITE',
'GL2C_PERF_SEL_PARTIAL_32B_HIT', 'GL2C_PERF_SEL_PARTIAL_64B_HIT',
'GL2C_PERF_SEL_PARTIAL_96B_HIT', 'GL2C_PERF_SEL_PROBE',
'GL2C_PERF_SEL_PROBE_ALL', 'GL2C_PERF_SEL_PROBE_EVICT',
'GL2C_PERF_SEL_PROBE_FILTER_DISABLED',
'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION',
'GL2C_PERF_SEL_READ', 'GL2C_PERF_SEL_READ_128_REQ',
'GL2C_PERF_SEL_READ_32_REQ', 'GL2C_PERF_SEL_READ_64_REQ',
'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE',
'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', 'GL2C_PERF_SEL_REQ',
'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', 'GL2C_PERF_SEL_RETURN_ACK',
'GL2C_PERF_SEL_RETURN_DATA', 'GL2C_PERF_SEL_SHARED_REQ',
'GL2C_PERF_SEL_SRC_FIFO_FULL', 'GL2C_PERF_SEL_STREAM_REQ',
'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL',
'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL',
'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL',
'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL',
'GL2C_PERF_SEL_TAG_PROBE_STALL',
'GL2C_PERF_SEL_TAG_READ_DST_STALL', 'GL2C_PERF_SEL_TAG_STALL',
'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL',
'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL',
'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 'GL2C_PERF_SEL_UC_REQ',
'GL2C_PERF_SEL_UNCACHED_WRITE', 'GL2C_PERF_SEL_VOL_REQ',
'GL2C_PERF_SEL_WRITE', 'GL2C_PERF_SEL_WRITEBACK',
'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT',
'GL2C_PERF_SEL_WRITE_32_REQ', 'GL2C_PERF_SEL_WRITE_64_REQ',
'GL2_CACHE_POLICIES', 'GL2_CACHE_POLICY_BYPASS',
'GL2_CACHE_POLICY_LRU', 'GL2_CACHE_POLICY_NOA',
'GL2_CACHE_POLICY_STREAM', 'GL2_EA_CID', 'GL2_EA_CID_CLIENT',
'GL2_EA_CID_CP', 'GL2_EA_CID_CPDMA', 'GL2_EA_CID_DCC',
'GL2_EA_CID_FMASK', 'GL2_EA_CID_HTILE', 'GL2_EA_CID_RLC',
'GL2_EA_CID_RT', 'GL2_EA_CID_SDMA', 'GL2_EA_CID_TCPMETA',
'GL2_EA_CID_UTCL2', 'GL2_EA_CID_ZPCPSD', 'GL2_EA_CID_Z_STENCIL',
'GL2_NACKS', 'GL2_NACK_DATA_ERROR', 'GL2_NACK_NO_FAULT',
'GL2_NACK_PAGE_FAULT', 'GL2_NACK_PROTECTION_FAULT', 'GL2_OP',
'GL2_OP_ATOMIC_ADD_32', 'GL2_OP_ATOMIC_ADD_64',
'GL2_OP_ATOMIC_ADD_RTN_32', 'GL2_OP_ATOMIC_ADD_RTN_64',
'GL2_OP_ATOMIC_AND_32', 'GL2_OP_ATOMIC_AND_64',
'GL2_OP_ATOMIC_AND_RTN_32', 'GL2_OP_ATOMIC_AND_RTN_64',
'GL2_OP_ATOMIC_CMPSWAP_32', 'GL2_OP_ATOMIC_CMPSWAP_64',
'GL2_OP_ATOMIC_CMPSWAP_RTN_32', 'GL2_OP_ATOMIC_CMPSWAP_RTN_64',
'GL2_OP_ATOMIC_DEC_32', 'GL2_OP_ATOMIC_DEC_64',
'GL2_OP_ATOMIC_DEC_RTN_32', 'GL2_OP_ATOMIC_DEC_RTN_64',
'GL2_OP_ATOMIC_FCMPSWAP_32', 'GL2_OP_ATOMIC_FCMPSWAP_64',
'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32',
'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64',
'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32',
'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64',
'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64',
'GL2_OP_ATOMIC_FMAX_32', 'GL2_OP_ATOMIC_FMAX_64',
'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32',
'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64',
'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32',
'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64',
'GL2_OP_ATOMIC_FMAX_RTN_32', 'GL2_OP_ATOMIC_FMAX_RTN_64',
'GL2_OP_ATOMIC_FMIN_32', 'GL2_OP_ATOMIC_FMIN_64',
'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32',
'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64',
'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32',
'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64',
'GL2_OP_ATOMIC_FMIN_RTN_32', 'GL2_OP_ATOMIC_FMIN_RTN_64',
'GL2_OP_ATOMIC_INC_32', 'GL2_OP_ATOMIC_INC_64',
'GL2_OP_ATOMIC_INC_RTN_32', 'GL2_OP_ATOMIC_INC_RTN_64',
'GL2_OP_ATOMIC_OR_32', 'GL2_OP_ATOMIC_OR_64',
'GL2_OP_ATOMIC_OR_RTN_32', 'GL2_OP_ATOMIC_OR_RTN_64',
'GL2_OP_ATOMIC_SMAX_32', 'GL2_OP_ATOMIC_SMAX_64',
'GL2_OP_ATOMIC_SMAX_RTN_32', 'GL2_OP_ATOMIC_SMAX_RTN_64',
'GL2_OP_ATOMIC_SMIN_32', 'GL2_OP_ATOMIC_SMIN_64',
'GL2_OP_ATOMIC_SMIN_RTN_32', 'GL2_OP_ATOMIC_SMIN_RTN_64',
'GL2_OP_ATOMIC_SUB_32', 'GL2_OP_ATOMIC_SUB_64',
'GL2_OP_ATOMIC_SUB_RTN_32', 'GL2_OP_ATOMIC_SUB_RTN_64',
'GL2_OP_ATOMIC_SWAP_32', 'GL2_OP_ATOMIC_SWAP_64',
'GL2_OP_ATOMIC_SWAP_RTN_32', 'GL2_OP_ATOMIC_SWAP_RTN_64',
'GL2_OP_ATOMIC_UMAX_32', 'GL2_OP_ATOMIC_UMAX_64',
'GL2_OP_ATOMIC_UMAX_RTN_32', 'GL2_OP_ATOMIC_UMAX_RTN_64',
'GL2_OP_ATOMIC_UMIN_32', 'GL2_OP_ATOMIC_UMIN_64',
'GL2_OP_ATOMIC_UMIN_RTN_32', 'GL2_OP_ATOMIC_UMIN_RTN_64',
'GL2_OP_ATOMIC_XOR_32', 'GL2_OP_ATOMIC_XOR_64',
'GL2_OP_ATOMIC_XOR_RTN_32', 'GL2_OP_ATOMIC_XOR_RTN_64',
'GL2_OP_GL1_INV', 'GL2_OP_MASKS', 'GL2_OP_MASK_64',
'GL2_OP_MASK_FLUSH_DENROM', 'GL2_OP_MASK_NO_RTN',
'GL2_OP_NOP_ACK', 'GL2_OP_NOP_RTN0', 'GL2_OP_PROBE_FILTER',
'GL2_OP_READ', 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1',
'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', 'GL2_OP_WRITE',
'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE',
'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL',
'GLOBAL_STATUS_FLUSH_STATUS',
'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED',
'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED',
'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA',
'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA',
'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA',
'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA',
'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA',
'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO',
'GRBM_PERF_SEL', 'GRBM_PERF_SEL_BCI_BUSY',
'GRBM_PERF_SEL_CB_BUSY', 'GRBM_PERF_SEL_CB_CLEAN',
'GRBM_PERF_SEL_CH_BUSY', 'GRBM_PERF_SEL_COUNT',
'GRBM_PERF_SEL_CPAXI_BUSY', 'GRBM_PERF_SEL_CPC_BUSY',
'GRBM_PERF_SEL_CPF_BUSY', 'GRBM_PERF_SEL_CPG_BUSY',
'GRBM_PERF_SEL_CP_BUSY', 'GRBM_PERF_SEL_CP_COHER_BUSY',
'GRBM_PERF_SEL_CP_DMA_BUSY', 'GRBM_PERF_SEL_DB_BUSY',
'GRBM_PERF_SEL_DB_CLEAN', 'GRBM_PERF_SEL_EA_BUSY',
'GRBM_PERF_SEL_GDS_BUSY', 'GRBM_PERF_SEL_GE_BUSY',
'GRBM_PERF_SEL_GE_NO_DMA_BUSY', 'GRBM_PERF_SEL_GL1CC_BUSY',
'GRBM_PERF_SEL_GL2CC_BUSY', 'GRBM_PERF_SEL_GUI_ACTIVE',
'GRBM_PERF_SEL_GUS_BUSY', 'GRBM_PERF_SEL_PA_BUSY',
'GRBM_PERF_SEL_PH_BUSY', 'GRBM_PERF_SEL_PMM_BUSY',
'GRBM_PERF_SEL_RESERVED_0', 'GRBM_PERF_SEL_RESERVED_1',
'GRBM_PERF_SEL_RESERVED_2', 'GRBM_PERF_SEL_RESERVED_3',
'GRBM_PERF_SEL_RESERVED_4', 'GRBM_PERF_SEL_RESERVED_5',
'GRBM_PERF_SEL_RESERVED_6', 'GRBM_PERF_SEL_RESERVED_7',
'GRBM_PERF_SEL_RESERVED_8', 'GRBM_PERF_SEL_RESERVED_9',
'GRBM_PERF_SEL_RLC_BUSY', 'GRBM_PERF_SEL_RMI_BUSY',
'GRBM_PERF_SEL_SC_BUSY', 'GRBM_PERF_SEL_SDMA_BUSY',
'GRBM_PERF_SEL_SPI_BUSY', 'GRBM_PERF_SEL_SX_BUSY',
'GRBM_PERF_SEL_TA_BUSY', 'GRBM_PERF_SEL_TCP_BUSY',
'GRBM_PERF_SEL_USER_DEFINED', 'GRBM_PERF_SEL_UTCL1_BUSY',
'GRBM_PERF_SEL_UTCL2_BUSY', 'GRBM_SE0_PERF_SEL',
'GRBM_SE0_PERF_SEL_BCI_BUSY', 'GRBM_SE0_PERF_SEL_CB_BUSY',
'GRBM_SE0_PERF_SEL_CB_CLEAN', 'GRBM_SE0_PERF_SEL_COUNT',
'GRBM_SE0_PERF_SEL_DB_BUSY', 'GRBM_SE0_PERF_SEL_DB_CLEAN',
'GRBM_SE0_PERF_SEL_GL1CC_BUSY', 'GRBM_SE0_PERF_SEL_PA_BUSY',
'GRBM_SE0_PERF_SEL_RESERVED_0', 'GRBM_SE0_PERF_SEL_RESERVED_1',
'GRBM_SE0_PERF_SEL_RESERVED_2', 'GRBM_SE0_PERF_SEL_RMI_BUSY',
'GRBM_SE0_PERF_SEL_SC_BUSY', 'GRBM_SE0_PERF_SEL_SPI_BUSY',
'GRBM_SE0_PERF_SEL_SX_BUSY', 'GRBM_SE0_PERF_SEL_TA_BUSY',
'GRBM_SE0_PERF_SEL_TCP_BUSY', 'GRBM_SE0_PERF_SEL_USER_DEFINED',
'GRBM_SE0_PERF_SEL_UTCL1_BUSY', 'GRBM_SE1_PERF_SEL',
'GRBM_SE1_PERF_SEL_BCI_BUSY', 'GRBM_SE1_PERF_SEL_CB_BUSY',
'GRBM_SE1_PERF_SEL_CB_CLEAN', 'GRBM_SE1_PERF_SEL_COUNT',
'GRBM_SE1_PERF_SEL_DB_BUSY', 'GRBM_SE1_PERF_SEL_DB_CLEAN',
'GRBM_SE1_PERF_SEL_GL1CC_BUSY', 'GRBM_SE1_PERF_SEL_PA_BUSY',
'GRBM_SE1_PERF_SEL_RESERVED_0', 'GRBM_SE1_PERF_SEL_RESERVED_1',
'GRBM_SE1_PERF_SEL_RESERVED_2', 'GRBM_SE1_PERF_SEL_RMI_BUSY',
'GRBM_SE1_PERF_SEL_SC_BUSY', 'GRBM_SE1_PERF_SEL_SPI_BUSY',
'GRBM_SE1_PERF_SEL_SX_BUSY', 'GRBM_SE1_PERF_SEL_TA_BUSY',
'GRBM_SE1_PERF_SEL_TCP_BUSY', 'GRBM_SE1_PERF_SEL_USER_DEFINED',
'GRBM_SE1_PERF_SEL_UTCL1_BUSY', 'GRBM_SE2_PERF_SEL',
'GRBM_SE2_PERF_SEL_BCI_BUSY', 'GRBM_SE2_PERF_SEL_CB_BUSY',
'GRBM_SE2_PERF_SEL_CB_CLEAN', 'GRBM_SE2_PERF_SEL_COUNT',
'GRBM_SE2_PERF_SEL_DB_BUSY', 'GRBM_SE2_PERF_SEL_DB_CLEAN',
'GRBM_SE2_PERF_SEL_GL1CC_BUSY', 'GRBM_SE2_PERF_SEL_PA_BUSY',
'GRBM_SE2_PERF_SEL_RESERVED_0', 'GRBM_SE2_PERF_SEL_RESERVED_1',
'GRBM_SE2_PERF_SEL_RESERVED_2', 'GRBM_SE2_PERF_SEL_RMI_BUSY',
'GRBM_SE2_PERF_SEL_SC_BUSY', 'GRBM_SE2_PERF_SEL_SPI_BUSY',
'GRBM_SE2_PERF_SEL_SX_BUSY', 'GRBM_SE2_PERF_SEL_TA_BUSY',
'GRBM_SE2_PERF_SEL_TCP_BUSY', 'GRBM_SE2_PERF_SEL_USER_DEFINED',
'GRBM_SE2_PERF_SEL_UTCL1_BUSY', 'GRBM_SE3_PERF_SEL',
'GRBM_SE3_PERF_SEL_BCI_BUSY', 'GRBM_SE3_PERF_SEL_CB_BUSY',
'GRBM_SE3_PERF_SEL_CB_CLEAN', 'GRBM_SE3_PERF_SEL_COUNT',
'GRBM_SE3_PERF_SEL_DB_BUSY', 'GRBM_SE3_PERF_SEL_DB_CLEAN',
'GRBM_SE3_PERF_SEL_GL1CC_BUSY', 'GRBM_SE3_PERF_SEL_PA_BUSY',
'GRBM_SE3_PERF_SEL_RESERVED_0', 'GRBM_SE3_PERF_SEL_RESERVED_1',
'GRBM_SE3_PERF_SEL_RESERVED_2', 'GRBM_SE3_PERF_SEL_RMI_BUSY',
'GRBM_SE3_PERF_SEL_SC_BUSY', 'GRBM_SE3_PERF_SEL_SPI_BUSY',
'GRBM_SE3_PERF_SEL_SX_BUSY', 'GRBM_SE3_PERF_SEL_TA_BUSY',
'GRBM_SE3_PERF_SEL_TCP_BUSY', 'GRBM_SE3_PERF_SEL_USER_DEFINED',
'GRBM_SE3_PERF_SEL_UTCL1_BUSY', 'GSTHREADID_SIZE', 'GS_CUT_1024',
'GS_CUT_128', 'GS_CUT_256', 'GS_CUT_512', 'GS_OFF',
'GS_SCENARIO_A', 'GS_SCENARIO_B', 'GS_SCENARIO_C',
'GS_SCENARIO_G', 'GS_STAGE_OFF', 'GS_STAGE_ON', 'GroupInterleave',
'HDMI_ACR_0_MULTIPLE_RESERVED', 'HDMI_ACR_1_MULTIPLE',
'HDMI_ACR_2_MULTIPLE', 'HDMI_ACR_3_MULTIPLE_RESERVED',
'HDMI_ACR_4_MULTIPLE', 'HDMI_ACR_5_MULTIPLE_RESERVED',
'HDMI_ACR_6_MULTIPLE_RESERVED', 'HDMI_ACR_7_MULTIPLE_RESERVED',
'HDMI_ACR_AUDIO_PRIORITY', 'HDMI_ACR_CONT',
'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE',
'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE',
'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE',
'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K',
'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K',
'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE',
'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW',
'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK',
'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN',
'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT',
'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE',
'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND',
'HDMI_AUDIO_INFO_SEND',
'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT',
'HDMI_AUDIO_SEND_MAX_PACKETS',
'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE',
'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE',
'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DEEP_COLOR_DEPTH',
'HDMI_DEEP_COLOR_DEPTH_24BPP', 'HDMI_DEEP_COLOR_DEPTH_30BPP',
'HDMI_DEEP_COLOR_DEPTH_36BPP', 'HDMI_DEEP_COLOR_DEPTH_48BPP',
'HDMI_DEFAULT_PAHSE', 'HDMI_DEFAULT_PHASE_IS_0',
'HDMI_DEFAULT_PHASE_IS_1', 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT',
'HDMI_ERROR_MASK', 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK',
'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE',
'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_GC_AVMUTE',
'HDMI_GC_AVMUTE_CONT', 'HDMI_GC_AVMUTE_CONT_DISABLE',
'HDMI_GC_AVMUTE_CONT_ENABLE', 'HDMI_GC_AVMUTE_SET',
'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', 'HDMI_GC_CONT_DISABLE',
'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', 'HDMI_GC_PKT_SEND',
'HDMI_GC_SEND', 'HDMI_GENERIC_CONT', 'HDMI_GENERIC_CONT_DISABLE',
'HDMI_GENERIC_CONT_ENABLE', 'HDMI_GENERIC_NOT_SEND',
'HDMI_GENERIC_PKT_SEND', 'HDMI_GENERIC_SEND', 'HDMI_ISRC_CONT',
'HDMI_ISRC_CONT_DISABLE', 'HDMI_ISRC_CONT_ENABLE',
'HDMI_ISRC_NOT_SEND', 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND',
'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC',
'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE',
'HDMI_METADATA_ENABLE', 'HDMI_METADATA_NOT_SEND',
'HDMI_METADATA_PKT_SEND', 'HDMI_MPEG_INFO_CONT',
'HDMI_MPEG_INFO_CONT_DISABLE', 'HDMI_MPEG_INFO_CONT_ENABLE',
'HDMI_MPEG_INFO_NOT_SEND', 'HDMI_MPEG_INFO_PKT_SEND',
'HDMI_MPEG_INFO_SEND', 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS',
'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND',
'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION',
'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD',
'HDMI_PACKET_LINE_REFERENCE', 'HDMI_PACKING_PHASE_OVERRIDE',
'HDMI_PACKING_PHASE_SET_BY_HW', 'HDMI_PACKING_PHASE_SET_BY_SW',
'HDMI_PKT_LINE_REF_OTGSOF', 'HDMI_PKT_LINE_REF_VSYNC',
'HDMI_SEND_MAX_AUDIO_PACKETS', 'HDP_ENDIAN_8IN16',
'HDP_ENDIAN_8IN32', 'HDP_ENDIAN_8IN64', 'HDP_ENDIAN_NONE',
'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0',
'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON',
'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY',
'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0',
'HPD_INT_CONTROL_RX_INT_ACK_1', 'HS_GS', 'HS_STAGE_OFF',
'HS_STAGE_ON', 'HUBP_BLANK_EN', 'HUBP_BLANK_SW_ASSERT',
'HUBP_BLANK_SW_DEASSERT', 'HUBP_DISABLE', 'HUBP_DISABLED',
'HUBP_ENABLED', 'HUBP_IN_ACTIVE', 'HUBP_IN_BLANK',
'HUBP_IN_VBLANK', 'HUBP_MEASURE_WIN_MODE_DCFCLK',
'HUBP_MEASURE_WIN_MODE_DCFCLK_0',
'HUBP_MEASURE_WIN_MODE_DCFCLK_1',
'HUBP_MEASURE_WIN_MODE_DCFCLK_2',
'HUBP_MEASURE_WIN_MODE_DCFCLK_3', 'HUBP_NO_OUTSTANDING_REQ',
'HUBP_TTU_DISABLE', 'HUBP_TTU_DISABLED', 'HUBP_TTU_ENABLED',
'HUBP_VREADY_AT_OR_AFTER_VSYNC', 'HUBP_VTG_SEL',
'HUBP_XFC_CHUNK_SIZE_16KB', 'HUBP_XFC_CHUNK_SIZE_1KB',
'HUBP_XFC_CHUNK_SIZE_256B', 'HUBP_XFC_CHUNK_SIZE_2KB',
'HUBP_XFC_CHUNK_SIZE_32KB', 'HUBP_XFC_CHUNK_SIZE_4KB',
'HUBP_XFC_CHUNK_SIZE_512B', 'HUBP_XFC_CHUNK_SIZE_8KB',
'HUBP_XFC_CHUNK_SIZE_ENUM', 'HUBP_XFC_FRAME_MODE_ENUM',
'HUBP_XFC_FULL_FRAME_MODE', 'HUBP_XFC_PARTIAL_FRAME_MODE',
'HUBP_XFC_PIXEL_FORMAT_ENUM', 'HUBP_XFC_PIXEL_IS_32BPP',
'HUBP_XFC_PIXEL_IS_64BPP', 'HW_MIRRORING_DISABLE',
'HW_MIRRORING_ENABLE', 'H_MIRROR_EN', 'Hdp_SurfaceEndian',
'ID_STREAM_DISABLE_ACKED', 'ID_STREAM_DISABLE_NO_ACK',
'IHC_INTERRUPT_LINE_STATUS', 'IH_CLIENT_TYPE',
'IH_CLIENT_TYPE_RESERVED', 'IH_GFX_VMID_CLIENT',
'IH_INTERFACE_TYPE', 'IH_LEGACY_INTERFACE', 'IH_MM_VMID_CLIENT',
'IH_MULTI_VMID_CLIENT', 'IH_PERF_SEL',
'IH_PERF_SEL_BIF_LINE0_FALLING',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF0',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF1',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF10',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF11',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF12',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF13',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF14',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF15',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF16',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF17',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF18',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF19',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF2',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF20',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF21',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF22',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF23',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF24',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF25',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF26',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF27',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF28',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF29',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF3',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF30',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF4',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF5',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF6',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF7',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF8',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF9',
'IH_PERF_SEL_BIF_LINE0_RISING',
'IH_PERF_SEL_BIF_LINE0_RISING_VF0',
'IH_PERF_SEL_BIF_LINE0_RISING_VF1',
'IH_PERF_SEL_BIF_LINE0_RISING_VF10',
'IH_PERF_SEL_BIF_LINE0_RISING_VF11',
'IH_PERF_SEL_BIF_LINE0_RISING_VF12',
'IH_PERF_SEL_BIF_LINE0_RISING_VF13',
'IH_PERF_SEL_BIF_LINE0_RISING_VF14',
'IH_PERF_SEL_BIF_LINE0_RISING_VF15',
'IH_PERF_SEL_BIF_LINE0_RISING_VF16',
'IH_PERF_SEL_BIF_LINE0_RISING_VF17',
'IH_PERF_SEL_BIF_LINE0_RISING_VF18',
'IH_PERF_SEL_BIF_LINE0_RISING_VF19',
'IH_PERF_SEL_BIF_LINE0_RISING_VF2',
'IH_PERF_SEL_BIF_LINE0_RISING_VF20',
'IH_PERF_SEL_BIF_LINE0_RISING_VF21',
'IH_PERF_SEL_BIF_LINE0_RISING_VF22',
'IH_PERF_SEL_BIF_LINE0_RISING_VF23',
'IH_PERF_SEL_BIF_LINE0_RISING_VF24',
'IH_PERF_SEL_BIF_LINE0_RISING_VF25',
'IH_PERF_SEL_BIF_LINE0_RISING_VF26',
'IH_PERF_SEL_BIF_LINE0_RISING_VF27',
'IH_PERF_SEL_BIF_LINE0_RISING_VF28',
'IH_PERF_SEL_BIF_LINE0_RISING_VF29',
'IH_PERF_SEL_BIF_LINE0_RISING_VF3',
'IH_PERF_SEL_BIF_LINE0_RISING_VF30',
'IH_PERF_SEL_BIF_LINE0_RISING_VF4',
'IH_PERF_SEL_BIF_LINE0_RISING_VF5',
'IH_PERF_SEL_BIF_LINE0_RISING_VF6',
'IH_PERF_SEL_BIF_LINE0_RISING_VF7',
'IH_PERF_SEL_BIF_LINE0_RISING_VF8',
'IH_PERF_SEL_BIF_LINE0_RISING_VF9',
'IH_PERF_SEL_BUFFER_FIFO_FULL', 'IH_PERF_SEL_BUFFER_IDLE',
'IH_PERF_SEL_CLIENT0_INT', 'IH_PERF_SEL_CLIENT10_INT',
'IH_PERF_SEL_CLIENT11_INT', 'IH_PERF_SEL_CLIENT12_INT',
'IH_PERF_SEL_CLIENT13_INT', 'IH_PERF_SEL_CLIENT14_INT',
'IH_PERF_SEL_CLIENT15_INT', 'IH_PERF_SEL_CLIENT16_INT',
'IH_PERF_SEL_CLIENT17_INT', 'IH_PERF_SEL_CLIENT18_INT',
'IH_PERF_SEL_CLIENT19_INT', 'IH_PERF_SEL_CLIENT1_INT',
'IH_PERF_SEL_CLIENT20_INT', 'IH_PERF_SEL_CLIENT21_INT',
'IH_PERF_SEL_CLIENT22_INT', 'IH_PERF_SEL_CLIENT23_INT',
'IH_PERF_SEL_CLIENT24_INT', 'IH_PERF_SEL_CLIENT25_INT',
'IH_PERF_SEL_CLIENT26_INT', 'IH_PERF_SEL_CLIENT27_INT',
'IH_PERF_SEL_CLIENT28_INT', 'IH_PERF_SEL_CLIENT29_INT',
'IH_PERF_SEL_CLIENT2_INT', 'IH_PERF_SEL_CLIENT30_INT',
'IH_PERF_SEL_CLIENT31_INT', 'IH_PERF_SEL_CLIENT3_INT',
'IH_PERF_SEL_CLIENT4_INT', 'IH_PERF_SEL_CLIENT5_INT',
'IH_PERF_SEL_CLIENT6_INT', 'IH_PERF_SEL_CLIENT7_INT',
'IH_PERF_SEL_CLIENT8_INT', 'IH_PERF_SEL_CLIENT9_INT',
'IH_PERF_SEL_CLIENT_CREDIT_ERROR', 'IH_PERF_SEL_COOKIE_REC_ERROR',
'IH_PERF_SEL_CYCLE', 'IH_PERF_SEL_IDLE', 'IH_PERF_SEL_INPUT_IDLE',
'IH_PERF_SEL_MC_WR_CLEAN_PENDING',
'IH_PERF_SEL_MC_WR_CLEAN_STALL', 'IH_PERF_SEL_MC_WR_COUNT',
'IH_PERF_SEL_MC_WR_IDLE', 'IH_PERF_SEL_MC_WR_STALL',
'IH_PERF_SEL_RB0_FULL', 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF17',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF18',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF19',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF20',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF21',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF22',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF23',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF24',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF25',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF26',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF27',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF28',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF29',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF30',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB0_FULL_VF0',
'IH_PERF_SEL_RB0_FULL_VF1', 'IH_PERF_SEL_RB0_FULL_VF10',
'IH_PERF_SEL_RB0_FULL_VF11', 'IH_PERF_SEL_RB0_FULL_VF12',
'IH_PERF_SEL_RB0_FULL_VF13', 'IH_PERF_SEL_RB0_FULL_VF14',
'IH_PERF_SEL_RB0_FULL_VF15', 'IH_PERF_SEL_RB0_FULL_VF16',
'IH_PERF_SEL_RB0_FULL_VF17', 'IH_PERF_SEL_RB0_FULL_VF18',
'IH_PERF_SEL_RB0_FULL_VF19', 'IH_PERF_SEL_RB0_FULL_VF2',
'IH_PERF_SEL_RB0_FULL_VF20', 'IH_PERF_SEL_RB0_FULL_VF21',
'IH_PERF_SEL_RB0_FULL_VF22', 'IH_PERF_SEL_RB0_FULL_VF23',
'IH_PERF_SEL_RB0_FULL_VF24', 'IH_PERF_SEL_RB0_FULL_VF25',
'IH_PERF_SEL_RB0_FULL_VF26', 'IH_PERF_SEL_RB0_FULL_VF27',
'IH_PERF_SEL_RB0_FULL_VF28', 'IH_PERF_SEL_RB0_FULL_VF29',
'IH_PERF_SEL_RB0_FULL_VF3', 'IH_PERF_SEL_RB0_FULL_VF30',
'IH_PERF_SEL_RB0_FULL_VF4', 'IH_PERF_SEL_RB0_FULL_VF5',
'IH_PERF_SEL_RB0_FULL_VF6', 'IH_PERF_SEL_RB0_FULL_VF7',
'IH_PERF_SEL_RB0_FULL_VF8', 'IH_PERF_SEL_RB0_FULL_VF9',
'IH_PERF_SEL_RB0_LOAD_RPTR', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF11',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF12',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF13',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF14',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF15',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF16',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF17',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF18',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF19', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF20',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF21',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF22',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF23',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF24',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF25',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF26',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF27',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF28',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF29', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF30', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB0_OVERFLOW',
'IH_PERF_SEL_RB0_OVERFLOW_VF0', 'IH_PERF_SEL_RB0_OVERFLOW_VF1',
'IH_PERF_SEL_RB0_OVERFLOW_VF10', 'IH_PERF_SEL_RB0_OVERFLOW_VF11',
'IH_PERF_SEL_RB0_OVERFLOW_VF12', 'IH_PERF_SEL_RB0_OVERFLOW_VF13',
'IH_PERF_SEL_RB0_OVERFLOW_VF14', 'IH_PERF_SEL_RB0_OVERFLOW_VF15',
'IH_PERF_SEL_RB0_OVERFLOW_VF16', 'IH_PERF_SEL_RB0_OVERFLOW_VF17',
'IH_PERF_SEL_RB0_OVERFLOW_VF18', 'IH_PERF_SEL_RB0_OVERFLOW_VF19',
'IH_PERF_SEL_RB0_OVERFLOW_VF2', 'IH_PERF_SEL_RB0_OVERFLOW_VF20',
'IH_PERF_SEL_RB0_OVERFLOW_VF21', 'IH_PERF_SEL_RB0_OVERFLOW_VF22',
'IH_PERF_SEL_RB0_OVERFLOW_VF23', 'IH_PERF_SEL_RB0_OVERFLOW_VF24',
'IH_PERF_SEL_RB0_OVERFLOW_VF25', 'IH_PERF_SEL_RB0_OVERFLOW_VF26',
'IH_PERF_SEL_RB0_OVERFLOW_VF27', 'IH_PERF_SEL_RB0_OVERFLOW_VF28',
'IH_PERF_SEL_RB0_OVERFLOW_VF29', 'IH_PERF_SEL_RB0_OVERFLOW_VF3',
'IH_PERF_SEL_RB0_OVERFLOW_VF30', 'IH_PERF_SEL_RB0_OVERFLOW_VF4',
'IH_PERF_SEL_RB0_OVERFLOW_VF5', 'IH_PERF_SEL_RB0_OVERFLOW_VF6',
'IH_PERF_SEL_RB0_OVERFLOW_VF7', 'IH_PERF_SEL_RB0_OVERFLOW_VF8',
'IH_PERF_SEL_RB0_OVERFLOW_VF9', 'IH_PERF_SEL_RB0_RPTR_WRAP',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF10',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF11',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF12',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF13',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF14',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF15',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF16',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF17',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF18',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF19', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF20',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF21',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF22',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF23',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF24',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF25',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF26',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF27',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF28',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF29', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF30', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRAP',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF10',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF11',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF12',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF13',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF14',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF15',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF16',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF17',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF18',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF19', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF20',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF21',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF22',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF23',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF24',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF25',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF26',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF27',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF28',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF29', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF30', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF16',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF17',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF18',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF19',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF20',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF21',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF22',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF23',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF24',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF25',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF26',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF27',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF28',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF29',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF30',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 'IH_PERF_SEL_RB1_FULL',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF17',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF18',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF19',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF20',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF21',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF22',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF23',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF24',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF25',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF26',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF27',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF28',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF29',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF30',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB1_FULL_VF0',
'IH_PERF_SEL_RB1_FULL_VF1', 'IH_PERF_SEL_RB1_FULL_VF10',
'IH_PERF_SEL_RB1_FULL_VF11', 'IH_PERF_SEL_RB1_FULL_VF12',
'IH_PERF_SEL_RB1_FULL_VF13', 'IH_PERF_SEL_RB1_FULL_VF14',
'IH_PERF_SEL_RB1_FULL_VF15', 'IH_PERF_SEL_RB1_FULL_VF16',
'IH_PERF_SEL_RB1_FULL_VF17', 'IH_PERF_SEL_RB1_FULL_VF18',
'IH_PERF_SEL_RB1_FULL_VF19', 'IH_PERF_SEL_RB1_FULL_VF2',
'IH_PERF_SEL_RB1_FULL_VF20', 'IH_PERF_SEL_RB1_FULL_VF21',
'IH_PERF_SEL_RB1_FULL_VF22', 'IH_PERF_SEL_RB1_FULL_VF23',
'IH_PERF_SEL_RB1_FULL_VF24', 'IH_PERF_SEL_RB1_FULL_VF25',
'IH_PERF_SEL_RB1_FULL_VF26', 'IH_PERF_SEL_RB1_FULL_VF27',
'IH_PERF_SEL_RB1_FULL_VF28', 'IH_PERF_SEL_RB1_FULL_VF29',
'IH_PERF_SEL_RB1_FULL_VF3', 'IH_PERF_SEL_RB1_FULL_VF30',
'IH_PERF_SEL_RB1_FULL_VF4', 'IH_PERF_SEL_RB1_FULL_VF5',
'IH_PERF_SEL_RB1_FULL_VF6', 'IH_PERF_SEL_RB1_FULL_VF7',
'IH_PERF_SEL_RB1_FULL_VF8', 'IH_PERF_SEL_RB1_FULL_VF9',
'IH_PERF_SEL_RB1_LOAD_RPTR', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF11',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF12',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF13',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF14',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF15',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF16',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF17',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF18',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF19', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF20',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF21',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF22',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF23',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF24',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF25',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF26',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF27',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF28',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF29', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF30', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB1_OVERFLOW',
'IH_PERF_SEL_RB1_OVERFLOW_VF0', 'IH_PERF_SEL_RB1_OVERFLOW_VF1',
'IH_PERF_SEL_RB1_OVERFLOW_VF10', 'IH_PERF_SEL_RB1_OVERFLOW_VF11',
'IH_PERF_SEL_RB1_OVERFLOW_VF12', 'IH_PERF_SEL_RB1_OVERFLOW_VF13',
'IH_PERF_SEL_RB1_OVERFLOW_VF14', 'IH_PERF_SEL_RB1_OVERFLOW_VF15',
'IH_PERF_SEL_RB1_OVERFLOW_VF16', 'IH_PERF_SEL_RB1_OVERFLOW_VF17',
'IH_PERF_SEL_RB1_OVERFLOW_VF18', 'IH_PERF_SEL_RB1_OVERFLOW_VF19',
'IH_PERF_SEL_RB1_OVERFLOW_VF2', 'IH_PERF_SEL_RB1_OVERFLOW_VF20',
'IH_PERF_SEL_RB1_OVERFLOW_VF21', 'IH_PERF_SEL_RB1_OVERFLOW_VF22',
'IH_PERF_SEL_RB1_OVERFLOW_VF23', 'IH_PERF_SEL_RB1_OVERFLOW_VF24',
'IH_PERF_SEL_RB1_OVERFLOW_VF25', 'IH_PERF_SEL_RB1_OVERFLOW_VF26',
'IH_PERF_SEL_RB1_OVERFLOW_VF27', 'IH_PERF_SEL_RB1_OVERFLOW_VF28',
'IH_PERF_SEL_RB1_OVERFLOW_VF29', 'IH_PERF_SEL_RB1_OVERFLOW_VF3',
'IH_PERF_SEL_RB1_OVERFLOW_VF30', 'IH_PERF_SEL_RB1_OVERFLOW_VF4',
'IH_PERF_SEL_RB1_OVERFLOW_VF5', 'IH_PERF_SEL_RB1_OVERFLOW_VF6',
'IH_PERF_SEL_RB1_OVERFLOW_VF7', 'IH_PERF_SEL_RB1_OVERFLOW_VF8',
'IH_PERF_SEL_RB1_OVERFLOW_VF9', 'IH_PERF_SEL_RB1_RPTR_WRAP',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF10',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF11',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF12',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF13',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF14',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF15',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF16',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF17',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF18',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF19', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF20',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF21',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF22',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF23',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF24',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF25',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF26',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF27',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF28',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF29', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF30', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB1_WPTR_WRAP',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF10',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF11',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF12',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF13',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF14',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF15',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF16',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF17',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF18',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF19', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF20',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF21',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF22',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF23',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF24',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF25',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF26',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF27',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF28',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF29', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF30', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_FULL',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF17',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF18',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF19',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF20',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF21',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF22',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF23',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF24',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF25',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF26',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF27',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF28',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF29',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF30',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB2_FULL_VF0',
'IH_PERF_SEL_RB2_FULL_VF1', 'IH_PERF_SEL_RB2_FULL_VF10',
'IH_PERF_SEL_RB2_FULL_VF11', 'IH_PERF_SEL_RB2_FULL_VF12',
'IH_PERF_SEL_RB2_FULL_VF13', 'IH_PERF_SEL_RB2_FULL_VF14',
'IH_PERF_SEL_RB2_FULL_VF15', 'IH_PERF_SEL_RB2_FULL_VF16',
'IH_PERF_SEL_RB2_FULL_VF17', 'IH_PERF_SEL_RB2_FULL_VF18',
'IH_PERF_SEL_RB2_FULL_VF19', 'IH_PERF_SEL_RB2_FULL_VF2',
'IH_PERF_SEL_RB2_FULL_VF20', 'IH_PERF_SEL_RB2_FULL_VF21',
'IH_PERF_SEL_RB2_FULL_VF22', 'IH_PERF_SEL_RB2_FULL_VF23',
'IH_PERF_SEL_RB2_FULL_VF24', 'IH_PERF_SEL_RB2_FULL_VF25',
'IH_PERF_SEL_RB2_FULL_VF26', 'IH_PERF_SEL_RB2_FULL_VF27',
'IH_PERF_SEL_RB2_FULL_VF28', 'IH_PERF_SEL_RB2_FULL_VF29',
'IH_PERF_SEL_RB2_FULL_VF3', 'IH_PERF_SEL_RB2_FULL_VF30',
'IH_PERF_SEL_RB2_FULL_VF4', 'IH_PERF_SEL_RB2_FULL_VF5',
'IH_PERF_SEL_RB2_FULL_VF6', 'IH_PERF_SEL_RB2_FULL_VF7',
'IH_PERF_SEL_RB2_FULL_VF8', 'IH_PERF_SEL_RB2_FULL_VF9',
'IH_PERF_SEL_RB2_LOAD_RPTR', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF11',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF12',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF13',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF14',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF15',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF16',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF17',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF18',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF19', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF20',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF21',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF22',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF23',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF24',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF25',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF26',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF27',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF28',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF29', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF30', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB2_OVERFLOW',
'IH_PERF_SEL_RB2_OVERFLOW_VF0', 'IH_PERF_SEL_RB2_OVERFLOW_VF1',
'IH_PERF_SEL_RB2_OVERFLOW_VF10', 'IH_PERF_SEL_RB2_OVERFLOW_VF11',
'IH_PERF_SEL_RB2_OVERFLOW_VF12', 'IH_PERF_SEL_RB2_OVERFLOW_VF13',
'IH_PERF_SEL_RB2_OVERFLOW_VF14', 'IH_PERF_SEL_RB2_OVERFLOW_VF15',
'IH_PERF_SEL_RB2_OVERFLOW_VF16', 'IH_PERF_SEL_RB2_OVERFLOW_VF17',
'IH_PERF_SEL_RB2_OVERFLOW_VF18', 'IH_PERF_SEL_RB2_OVERFLOW_VF19',
'IH_PERF_SEL_RB2_OVERFLOW_VF2', 'IH_PERF_SEL_RB2_OVERFLOW_VF20',
'IH_PERF_SEL_RB2_OVERFLOW_VF21', 'IH_PERF_SEL_RB2_OVERFLOW_VF22',
'IH_PERF_SEL_RB2_OVERFLOW_VF23', 'IH_PERF_SEL_RB2_OVERFLOW_VF24',
'IH_PERF_SEL_RB2_OVERFLOW_VF25', 'IH_PERF_SEL_RB2_OVERFLOW_VF26',
'IH_PERF_SEL_RB2_OVERFLOW_VF27', 'IH_PERF_SEL_RB2_OVERFLOW_VF28',
'IH_PERF_SEL_RB2_OVERFLOW_VF29', 'IH_PERF_SEL_RB2_OVERFLOW_VF3',
'IH_PERF_SEL_RB2_OVERFLOW_VF30', 'IH_PERF_SEL_RB2_OVERFLOW_VF4',
'IH_PERF_SEL_RB2_OVERFLOW_VF5', 'IH_PERF_SEL_RB2_OVERFLOW_VF6',
'IH_PERF_SEL_RB2_OVERFLOW_VF7', 'IH_PERF_SEL_RB2_OVERFLOW_VF8',
'IH_PERF_SEL_RB2_OVERFLOW_VF9', 'IH_PERF_SEL_RB2_RPTR_WRAP',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF10',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF11',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF12',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF13',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF14',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF15',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF16',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF17',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF18',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF19', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF20',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF21',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF22',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF23',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF24',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF25',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF26',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF27',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF28',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF29', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF30', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_WPTR_WRAP',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF10',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF11',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF12',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF13',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF14',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF15',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF16',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF17',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF18',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF19', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF20',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF21',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF22',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF23',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF24',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF25',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF26',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF27',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF28',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF29', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF30', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 'IH_PERF_SEL_SELF_IV_VALID',
'IH_PERF_SEL_STORM_CLIENT_INT_DROP',
'IH_REGISTER_WRITE_INTERFACE', 'IH_RING_ID',
'IH_RING_ID_INTERRUPT', 'IH_RING_ID_REQUEST',
'IH_RING_ID_RESERVED', 'IH_RING_ID_TRANSLATION',
'IH_VF_RB_SELECT', 'IH_VF_RB_SELECT_CLIENT_FCN_ID',
'IH_VF_RB_SELECT_IH_FCN_ID', 'IH_VF_RB_SELECT_PF',
'IH_VF_RB_SELECT_RESERVED', 'IMG_DATA_FORMAT',
'IMG_DATA_FORMAT_1', 'IMG_DATA_FORMAT_10_10_10_2',
'IMG_DATA_FORMAT_10_11_11', 'IMG_DATA_FORMAT_11_11_10',
'IMG_DATA_FORMAT_16', 'IMG_DATA_FORMAT_16_16',
'IMG_DATA_FORMAT_16_16_16_16', 'IMG_DATA_FORMAT_1_5_5_5',
'IMG_DATA_FORMAT_1_REVERSED', 'IMG_DATA_FORMAT_24_8',
'IMG_DATA_FORMAT_2_10_10_10', 'IMG_DATA_FORMAT_32',
'IMG_DATA_FORMAT_32_32', 'IMG_DATA_FORMAT_32_32_32',
'IMG_DATA_FORMAT_32_32_32_32',
'IMG_DATA_FORMAT_32_AS_32_32_32_32', 'IMG_DATA_FORMAT_4_4',
'IMG_DATA_FORMAT_4_4_4_4', 'IMG_DATA_FORMAT_5_5_5_1',
'IMG_DATA_FORMAT_5_6_5', 'IMG_DATA_FORMAT_5_9_9_9',
'IMG_DATA_FORMAT_6E4', 'IMG_DATA_FORMAT_6_5_5',
'IMG_DATA_FORMAT_8', 'IMG_DATA_FORMAT_8_24',
'IMG_DATA_FORMAT_8_8', 'IMG_DATA_FORMAT_8_8_8_8',
'IMG_DATA_FORMAT_BC1', 'IMG_DATA_FORMAT_BC2',
'IMG_DATA_FORMAT_BC3', 'IMG_DATA_FORMAT_BC4',
'IMG_DATA_FORMAT_BC5', 'IMG_DATA_FORMAT_BC6',
'IMG_DATA_FORMAT_BC7', 'IMG_DATA_FORMAT_BG_RG',
'IMG_DATA_FORMAT_FMASK16_S16_F1', 'IMG_DATA_FORMAT_FMASK16_S8_F2',
'IMG_DATA_FORMAT_FMASK32_S16_F2', 'IMG_DATA_FORMAT_FMASK32_S8_F4',
'IMG_DATA_FORMAT_FMASK32_S8_F8', 'IMG_DATA_FORMAT_FMASK64_S16_F4',
'IMG_DATA_FORMAT_FMASK64_S16_F8', 'IMG_DATA_FORMAT_FMASK8_S2_F1',
'IMG_DATA_FORMAT_FMASK8_S2_F2', 'IMG_DATA_FORMAT_FMASK8_S4_F1',
'IMG_DATA_FORMAT_FMASK8_S4_F2', 'IMG_DATA_FORMAT_FMASK8_S4_F4',
'IMG_DATA_FORMAT_FMASK8_S8_F1', 'IMG_DATA_FORMAT_GB_GR',
'IMG_DATA_FORMAT_INVALID', 'IMG_DATA_FORMAT_MM_10_11_11',
'IMG_DATA_FORMAT_MM_10_IN_16', 'IMG_DATA_FORMAT_MM_10_IN_16_16',
'IMG_DATA_FORMAT_MM_10_IN_16_16_16_16',
'IMG_DATA_FORMAT_MM_16_16_16_16', 'IMG_DATA_FORMAT_MM_2_10_10_10',
'IMG_DATA_FORMAT_MM_8', 'IMG_DATA_FORMAT_MM_8_8',
'IMG_DATA_FORMAT_MM_8_8_8_8', 'IMG_DATA_FORMAT_MM_VYUY8',
'IMG_DATA_FORMAT_RESERVED_100', 'IMG_DATA_FORMAT_RESERVED_101',
'IMG_DATA_FORMAT_RESERVED_102', 'IMG_DATA_FORMAT_RESERVED_103',
'IMG_DATA_FORMAT_RESERVED_104', 'IMG_DATA_FORMAT_RESERVED_105',
'IMG_DATA_FORMAT_RESERVED_106', 'IMG_DATA_FORMAT_RESERVED_107',
'IMG_DATA_FORMAT_RESERVED_108', 'IMG_DATA_FORMAT_RESERVED_109',
'IMG_DATA_FORMAT_RESERVED_110', 'IMG_DATA_FORMAT_RESERVED_111',
'IMG_DATA_FORMAT_RESERVED_112', 'IMG_DATA_FORMAT_RESERVED_113',
'IMG_DATA_FORMAT_RESERVED_114', 'IMG_DATA_FORMAT_RESERVED_115',
'IMG_DATA_FORMAT_RESERVED_116', 'IMG_DATA_FORMAT_RESERVED_117',
'IMG_DATA_FORMAT_RESERVED_118', 'IMG_DATA_FORMAT_RESERVED_119',
'IMG_DATA_FORMAT_RESERVED_120', 'IMG_DATA_FORMAT_RESERVED_121',
'IMG_DATA_FORMAT_RESERVED_122', 'IMG_DATA_FORMAT_RESERVED_123',
'IMG_DATA_FORMAT_RESERVED_124', 'IMG_DATA_FORMAT_RESERVED_125',
'IMG_DATA_FORMAT_RESERVED_126', 'IMG_DATA_FORMAT_RESERVED_127',
'IMG_DATA_FORMAT_RESERVED_15', 'IMG_DATA_FORMAT_RESERVED_23',
'IMG_DATA_FORMAT_RESERVED_24', 'IMG_DATA_FORMAT_RESERVED_25',
'IMG_DATA_FORMAT_RESERVED_26', 'IMG_DATA_FORMAT_RESERVED_27',
'IMG_DATA_FORMAT_RESERVED_28', 'IMG_DATA_FORMAT_RESERVED_29',
'IMG_DATA_FORMAT_RESERVED_30', 'IMG_DATA_FORMAT_RESERVED_42',
'IMG_DATA_FORMAT_RESERVED_43', 'IMG_DATA_FORMAT_RESERVED_61',
'IMG_DATA_FORMAT_RESERVED_62', 'IMG_DATA_FORMAT_RESERVED_75',
'IMG_DATA_FORMAT_RESERVED_86', 'IMG_DATA_FORMAT_RESERVED_87',
'IMG_DATA_FORMAT_RESERVED_88', 'IMG_DATA_FORMAT_RESERVED_89',
'IMG_DATA_FORMAT_RESERVED_90', 'IMG_DATA_FORMAT_RESERVED_91',
'IMG_DATA_FORMAT_RESERVED_92', 'IMG_DATA_FORMAT_RESERVED_93',
'IMG_DATA_FORMAT_RESERVED_94', 'IMG_DATA_FORMAT_RESERVED_95',
'IMG_DATA_FORMAT_RESERVED_96', 'IMG_DATA_FORMAT_RESERVED_97',
'IMG_DATA_FORMAT_RESERVED_98', 'IMG_DATA_FORMAT_RESERVED_99',
'IMG_DATA_FORMAT_X24_8_32', 'IMG_FMT', 'IMG_FMT_10_10_10_2_SINT',
'IMG_FMT_10_10_10_2_SNORM', 'IMG_FMT_10_10_10_2_SSCALED',
'IMG_FMT_10_10_10_2_UINT', 'IMG_FMT_10_10_10_2_UNORM',
'IMG_FMT_10_10_10_2_USCALED', 'IMG_FMT_10_11_11_FLOAT',
'IMG_FMT_10_11_11_SINT', 'IMG_FMT_10_11_11_SNORM',
'IMG_FMT_10_11_11_SSCALED', 'IMG_FMT_10_11_11_UINT',
'IMG_FMT_10_11_11_UNORM', 'IMG_FMT_10_11_11_USCALED',
'IMG_FMT_11_11_10_FLOAT', 'IMG_FMT_11_11_10_SINT',
'IMG_FMT_11_11_10_SNORM', 'IMG_FMT_11_11_10_SSCALED',
'IMG_FMT_11_11_10_UINT', 'IMG_FMT_11_11_10_UNORM',
'IMG_FMT_11_11_10_USCALED', 'IMG_FMT_16_16_16_16_FLOAT',
'IMG_FMT_16_16_16_16_SINT', 'IMG_FMT_16_16_16_16_SNORM',
'IMG_FMT_16_16_16_16_SSCALED', 'IMG_FMT_16_16_16_16_UINT',
'IMG_FMT_16_16_16_16_UNORM', 'IMG_FMT_16_16_16_16_USCALED',
'IMG_FMT_16_16_FLOAT', 'IMG_FMT_16_16_SINT',
'IMG_FMT_16_16_SNORM', 'IMG_FMT_16_16_SSCALED',
'IMG_FMT_16_16_UINT', 'IMG_FMT_16_16_UNORM',
'IMG_FMT_16_16_USCALED', 'IMG_FMT_16_FLOAT', 'IMG_FMT_16_SINT',
'IMG_FMT_16_SNORM', 'IMG_FMT_16_SSCALED', 'IMG_FMT_16_UINT',
'IMG_FMT_16_UNORM', 'IMG_FMT_16_USCALED', 'IMG_FMT_1_5_5_5_UNORM',
'IMG_FMT_1_REVERSED_UNORM', 'IMG_FMT_1_UNORM',
'IMG_FMT_24_8_UINT', 'IMG_FMT_24_8_UNORM',
'IMG_FMT_2_10_10_10_SINT', 'IMG_FMT_2_10_10_10_SNORM',
'IMG_FMT_2_10_10_10_SSCALED', 'IMG_FMT_2_10_10_10_UINT',
'IMG_FMT_2_10_10_10_UNORM', 'IMG_FMT_2_10_10_10_USCALED',
'IMG_FMT_32_32_32_32_FLOAT', 'IMG_FMT_32_32_32_32_SINT',
'IMG_FMT_32_32_32_32_UINT', 'IMG_FMT_32_32_32_FLOAT',
'IMG_FMT_32_32_32_SINT', 'IMG_FMT_32_32_32_UINT',
'IMG_FMT_32_32_FLOAT', 'IMG_FMT_32_32_SINT', 'IMG_FMT_32_32_UINT',
'IMG_FMT_32_FLOAT', 'IMG_FMT_32_FLOAT_CLAMP', 'IMG_FMT_32_SINT',
'IMG_FMT_32_UINT', 'IMG_FMT_4_4_4_4_UNORM', 'IMG_FMT_4_4_UNORM',
'IMG_FMT_5_5_5_1_UNORM', 'IMG_FMT_5_6_5_UNORM',
'IMG_FMT_5_9_9_9_FLOAT', 'IMG_FMT_6E4_FLOAT', 'IMG_FMT_8_24_UINT',
'IMG_FMT_8_24_UNORM', 'IMG_FMT_8_8_8_8_SINT',
'IMG_FMT_8_8_8_8_SNORM', 'IMG_FMT_8_8_8_8_SRGB',
'IMG_FMT_8_8_8_8_SSCALED', 'IMG_FMT_8_8_8_8_UINT',
'IMG_FMT_8_8_8_8_UNORM', 'IMG_FMT_8_8_8_8_USCALED',
'IMG_FMT_8_8_SINT', 'IMG_FMT_8_8_SNORM', 'IMG_FMT_8_8_SRGB',
'IMG_FMT_8_8_SSCALED', 'IMG_FMT_8_8_UINT', 'IMG_FMT_8_8_UNORM',
'IMG_FMT_8_8_USCALED', 'IMG_FMT_8_SINT', 'IMG_FMT_8_SNORM',
'IMG_FMT_8_SRGB', 'IMG_FMT_8_SSCALED', 'IMG_FMT_8_UINT',
'IMG_FMT_8_UNORM', 'IMG_FMT_8_USCALED', 'IMG_FMT_BC1_SRGB',
'IMG_FMT_BC1_UNORM', 'IMG_FMT_BC2_SRGB', 'IMG_FMT_BC2_UNORM',
'IMG_FMT_BC3_SRGB', 'IMG_FMT_BC3_UNORM', 'IMG_FMT_BC4_SNORM',
'IMG_FMT_BC4_UNORM', 'IMG_FMT_BC5_SNORM', 'IMG_FMT_BC5_UNORM',
'IMG_FMT_BC6_SFLOAT', 'IMG_FMT_BC6_UFLOAT', 'IMG_FMT_BC7_SRGB',
'IMG_FMT_BC7_UNORM', 'IMG_FMT_BG_RG_SNORM', 'IMG_FMT_BG_RG_SRGB',
'IMG_FMT_BG_RG_UINT', 'IMG_FMT_BG_RG_UNORM',
'IMG_FMT_FMASK16_S16_F1', 'IMG_FMT_FMASK16_S8_F2',
'IMG_FMT_FMASK32_S16_F2', 'IMG_FMT_FMASK32_S8_F4',
'IMG_FMT_FMASK32_S8_F8', 'IMG_FMT_FMASK64_S16_F4',
'IMG_FMT_FMASK64_S16_F8', 'IMG_FMT_FMASK8_S2_F1',
'IMG_FMT_FMASK8_S2_F2', 'IMG_FMT_FMASK8_S4_F1',
'IMG_FMT_FMASK8_S4_F2', 'IMG_FMT_FMASK8_S4_F4',
'IMG_FMT_FMASK8_S8_F1', 'IMG_FMT_GB_GR_SNORM',
'IMG_FMT_GB_GR_SRGB', 'IMG_FMT_GB_GR_UINT', 'IMG_FMT_GB_GR_UNORM',
'IMG_FMT_INVALID', 'IMG_FMT_MM_10_11_11_UINT',
'IMG_FMT_MM_10_11_11_UNORM', 'IMG_FMT_MM_10_IN_16_16_16_16_UINT',
'IMG_FMT_MM_10_IN_16_16_16_16_UNORM',
'IMG_FMT_MM_10_IN_16_16_UINT', 'IMG_FMT_MM_10_IN_16_16_UNORM',
'IMG_FMT_MM_10_IN_16_UINT', 'IMG_FMT_MM_10_IN_16_UNORM',
'IMG_FMT_MM_16_16_16_16_UINT', 'IMG_FMT_MM_16_16_16_16_UNORM',
'IMG_FMT_MM_2_10_10_10_UINT', 'IMG_FMT_MM_2_10_10_10_UNORM',
'IMG_FMT_MM_8_8_8_8_UINT', 'IMG_FMT_MM_8_8_8_8_UNORM',
'IMG_FMT_MM_8_8_UINT', 'IMG_FMT_MM_8_8_UNORM',
'IMG_FMT_MM_8_UINT', 'IMG_FMT_MM_8_UNORM',
'IMG_FMT_MM_VYUY8_UINT', 'IMG_FMT_MM_VYUY8_UNORM',
'IMG_FMT_RESERVED_100', 'IMG_FMT_RESERVED_101',
'IMG_FMT_RESERVED_102', 'IMG_FMT_RESERVED_103',
'IMG_FMT_RESERVED_104', 'IMG_FMT_RESERVED_105',
'IMG_FMT_RESERVED_106', 'IMG_FMT_RESERVED_107',
'IMG_FMT_RESERVED_108', 'IMG_FMT_RESERVED_109',
'IMG_FMT_RESERVED_110', 'IMG_FMT_RESERVED_111',
'IMG_FMT_RESERVED_112', 'IMG_FMT_RESERVED_113',
'IMG_FMT_RESERVED_114', 'IMG_FMT_RESERVED_115',
'IMG_FMT_RESERVED_116', 'IMG_FMT_RESERVED_117',
'IMG_FMT_RESERVED_118', 'IMG_FMT_RESERVED_119',
'IMG_FMT_RESERVED_120', 'IMG_FMT_RESERVED_121',
'IMG_FMT_RESERVED_122', 'IMG_FMT_RESERVED_123',
'IMG_FMT_RESERVED_124', 'IMG_FMT_RESERVED_125',
'IMG_FMT_RESERVED_126', 'IMG_FMT_RESERVED_127',
'IMG_FMT_RESERVED_155', 'IMG_FMT_RESERVED_285',
'IMG_FMT_RESERVED_286', 'IMG_FMT_RESERVED_287',
'IMG_FMT_RESERVED_288', 'IMG_FMT_RESERVED_289',
'IMG_FMT_RESERVED_290', 'IMG_FMT_RESERVED_291',
'IMG_FMT_RESERVED_292', 'IMG_FMT_RESERVED_293',
'IMG_FMT_RESERVED_294', 'IMG_FMT_RESERVED_295',
'IMG_FMT_RESERVED_296', 'IMG_FMT_RESERVED_297',
'IMG_FMT_RESERVED_298', 'IMG_FMT_RESERVED_299',
'IMG_FMT_RESERVED_300', 'IMG_FMT_RESERVED_301',
'IMG_FMT_RESERVED_302', 'IMG_FMT_RESERVED_303',
'IMG_FMT_RESERVED_304', 'IMG_FMT_RESERVED_305',
'IMG_FMT_RESERVED_306', 'IMG_FMT_RESERVED_307',
'IMG_FMT_RESERVED_308', 'IMG_FMT_RESERVED_309',
'IMG_FMT_RESERVED_310', 'IMG_FMT_RESERVED_311',
'IMG_FMT_RESERVED_312', 'IMG_FMT_RESERVED_313',
'IMG_FMT_RESERVED_314', 'IMG_FMT_RESERVED_315',
'IMG_FMT_RESERVED_316', 'IMG_FMT_RESERVED_317',
'IMG_FMT_RESERVED_318', 'IMG_FMT_RESERVED_319',
'IMG_FMT_RESERVED_320', 'IMG_FMT_RESERVED_321',
'IMG_FMT_RESERVED_322', 'IMG_FMT_RESERVED_323',
'IMG_FMT_RESERVED_324', 'IMG_FMT_RESERVED_325',
'IMG_FMT_RESERVED_326', 'IMG_FMT_RESERVED_327',
'IMG_FMT_RESERVED_328', 'IMG_FMT_RESERVED_329',
'IMG_FMT_RESERVED_330', 'IMG_FMT_RESERVED_331',
'IMG_FMT_RESERVED_332', 'IMG_FMT_RESERVED_333',
'IMG_FMT_RESERVED_334', 'IMG_FMT_RESERVED_335',
'IMG_FMT_RESERVED_336', 'IMG_FMT_RESERVED_337',
'IMG_FMT_RESERVED_338', 'IMG_FMT_RESERVED_339',
'IMG_FMT_RESERVED_340', 'IMG_FMT_RESERVED_341',
'IMG_FMT_RESERVED_342', 'IMG_FMT_RESERVED_343',
'IMG_FMT_RESERVED_344', 'IMG_FMT_RESERVED_345',
'IMG_FMT_RESERVED_346', 'IMG_FMT_RESERVED_347',
'IMG_FMT_RESERVED_348', 'IMG_FMT_RESERVED_349',
'IMG_FMT_RESERVED_350', 'IMG_FMT_RESERVED_351',
'IMG_FMT_RESERVED_352', 'IMG_FMT_RESERVED_353',
'IMG_FMT_RESERVED_354', 'IMG_FMT_RESERVED_355',
'IMG_FMT_RESERVED_356', 'IMG_FMT_RESERVED_357',
'IMG_FMT_RESERVED_358', 'IMG_FMT_RESERVED_359',
'IMG_FMT_RESERVED_360', 'IMG_FMT_RESERVED_361',
'IMG_FMT_RESERVED_362', 'IMG_FMT_RESERVED_363',
'IMG_FMT_RESERVED_364', 'IMG_FMT_RESERVED_365',
'IMG_FMT_RESERVED_366', 'IMG_FMT_RESERVED_367',
'IMG_FMT_RESERVED_368', 'IMG_FMT_RESERVED_369',
'IMG_FMT_RESERVED_370', 'IMG_FMT_RESERVED_371',
'IMG_FMT_RESERVED_372', 'IMG_FMT_RESERVED_373',
'IMG_FMT_RESERVED_374', 'IMG_FMT_RESERVED_375',
'IMG_FMT_RESERVED_376', 'IMG_FMT_RESERVED_377',
'IMG_FMT_RESERVED_378', 'IMG_FMT_RESERVED_379',
'IMG_FMT_RESERVED_380', 'IMG_FMT_RESERVED_381',
'IMG_FMT_RESERVED_382', 'IMG_FMT_RESERVED_383',
'IMG_FMT_RESERVED_384', 'IMG_FMT_RESERVED_385',
'IMG_FMT_RESERVED_386', 'IMG_FMT_RESERVED_387',
'IMG_FMT_RESERVED_388', 'IMG_FMT_RESERVED_389',
'IMG_FMT_RESERVED_390', 'IMG_FMT_RESERVED_391',
'IMG_FMT_RESERVED_392', 'IMG_FMT_RESERVED_393',
'IMG_FMT_RESERVED_394', 'IMG_FMT_RESERVED_395',
'IMG_FMT_RESERVED_396', 'IMG_FMT_RESERVED_397',
'IMG_FMT_RESERVED_398', 'IMG_FMT_RESERVED_399',
'IMG_FMT_RESERVED_400', 'IMG_FMT_RESERVED_401',
'IMG_FMT_RESERVED_402', 'IMG_FMT_RESERVED_403',
'IMG_FMT_RESERVED_404', 'IMG_FMT_RESERVED_405',
'IMG_FMT_RESERVED_406', 'IMG_FMT_RESERVED_407',
'IMG_FMT_RESERVED_408', 'IMG_FMT_RESERVED_409',
'IMG_FMT_RESERVED_410', 'IMG_FMT_RESERVED_411',
'IMG_FMT_RESERVED_412', 'IMG_FMT_RESERVED_413',
'IMG_FMT_RESERVED_414', 'IMG_FMT_RESERVED_415',
'IMG_FMT_RESERVED_416', 'IMG_FMT_RESERVED_417',
'IMG_FMT_RESERVED_418', 'IMG_FMT_RESERVED_419',
'IMG_FMT_RESERVED_420', 'IMG_FMT_RESERVED_421',
'IMG_FMT_RESERVED_422', 'IMG_FMT_RESERVED_423',
'IMG_FMT_RESERVED_424', 'IMG_FMT_RESERVED_425',
'IMG_FMT_RESERVED_426', 'IMG_FMT_RESERVED_427',
'IMG_FMT_RESERVED_428', 'IMG_FMT_RESERVED_429',
'IMG_FMT_RESERVED_430', 'IMG_FMT_RESERVED_431',
'IMG_FMT_RESERVED_432', 'IMG_FMT_RESERVED_433',
'IMG_FMT_RESERVED_434', 'IMG_FMT_RESERVED_435',
'IMG_FMT_RESERVED_436', 'IMG_FMT_RESERVED_437',
'IMG_FMT_RESERVED_438', 'IMG_FMT_RESERVED_439',
'IMG_FMT_RESERVED_440', 'IMG_FMT_RESERVED_441',
'IMG_FMT_RESERVED_442', 'IMG_FMT_RESERVED_443',
'IMG_FMT_RESERVED_444', 'IMG_FMT_RESERVED_445',
'IMG_FMT_RESERVED_446', 'IMG_FMT_RESERVED_447',
'IMG_FMT_RESERVED_448', 'IMG_FMT_RESERVED_449',
'IMG_FMT_RESERVED_450', 'IMG_FMT_RESERVED_451',
'IMG_FMT_RESERVED_452', 'IMG_FMT_RESERVED_453',
'IMG_FMT_RESERVED_454', 'IMG_FMT_RESERVED_455',
'IMG_FMT_RESERVED_456', 'IMG_FMT_RESERVED_457',
'IMG_FMT_RESERVED_458', 'IMG_FMT_RESERVED_459',
'IMG_FMT_RESERVED_460', 'IMG_FMT_RESERVED_461',
'IMG_FMT_RESERVED_462', 'IMG_FMT_RESERVED_463',
'IMG_FMT_RESERVED_464', 'IMG_FMT_RESERVED_465',
'IMG_FMT_RESERVED_466', 'IMG_FMT_RESERVED_467',
'IMG_FMT_RESERVED_468', 'IMG_FMT_RESERVED_469',
'IMG_FMT_RESERVED_470', 'IMG_FMT_RESERVED_471',
'IMG_FMT_RESERVED_472', 'IMG_FMT_RESERVED_473',
'IMG_FMT_RESERVED_474', 'IMG_FMT_RESERVED_475',
'IMG_FMT_RESERVED_476', 'IMG_FMT_RESERVED_477',
'IMG_FMT_RESERVED_478', 'IMG_FMT_RESERVED_479',
'IMG_FMT_RESERVED_480', 'IMG_FMT_RESERVED_481',
'IMG_FMT_RESERVED_482', 'IMG_FMT_RESERVED_483',
'IMG_FMT_RESERVED_484', 'IMG_FMT_RESERVED_485',
'IMG_FMT_RESERVED_486', 'IMG_FMT_RESERVED_487',
'IMG_FMT_RESERVED_488', 'IMG_FMT_RESERVED_489',
'IMG_FMT_RESERVED_490', 'IMG_FMT_RESERVED_491',
'IMG_FMT_RESERVED_492', 'IMG_FMT_RESERVED_493',
'IMG_FMT_RESERVED_494', 'IMG_FMT_RESERVED_495',
'IMG_FMT_RESERVED_496', 'IMG_FMT_RESERVED_497',
'IMG_FMT_RESERVED_498', 'IMG_FMT_RESERVED_499',
'IMG_FMT_RESERVED_500', 'IMG_FMT_RESERVED_501',
'IMG_FMT_RESERVED_502', 'IMG_FMT_RESERVED_503',
'IMG_FMT_RESERVED_504', 'IMG_FMT_RESERVED_505',
'IMG_FMT_RESERVED_506', 'IMG_FMT_RESERVED_507',
'IMG_FMT_RESERVED_508', 'IMG_FMT_RESERVED_509',
'IMG_FMT_RESERVED_510', 'IMG_FMT_RESERVED_511',
'IMG_FMT_RESERVED_78', 'IMG_FMT_RESERVED_79',
'IMG_FMT_RESERVED_80', 'IMG_FMT_RESERVED_81',
'IMG_FMT_RESERVED_82', 'IMG_FMT_RESERVED_83',
'IMG_FMT_RESERVED_84', 'IMG_FMT_RESERVED_85',
'IMG_FMT_RESERVED_86', 'IMG_FMT_RESERVED_87',
'IMG_FMT_RESERVED_88', 'IMG_FMT_RESERVED_89',
'IMG_FMT_RESERVED_90', 'IMG_FMT_RESERVED_91',
'IMG_FMT_RESERVED_92', 'IMG_FMT_RESERVED_93',
'IMG_FMT_RESERVED_94', 'IMG_FMT_RESERVED_95',
'IMG_FMT_RESERVED_96', 'IMG_FMT_RESERVED_97',
'IMG_FMT_RESERVED_98', 'IMG_FMT_RESERVED_99',
'IMG_FMT_X24_8_32_FLOAT', 'IMG_FMT_X24_8_32_UINT',
'IMG_NUM_FORMAT', 'IMG_NUM_FORMAT_FLOAT', 'IMG_NUM_FORMAT_FMASK',
'IMG_NUM_FORMAT_FMASK_16_16_1', 'IMG_NUM_FORMAT_FMASK_16_8_2',
'IMG_NUM_FORMAT_FMASK_32_16_2', 'IMG_NUM_FORMAT_FMASK_32_8_4',
'IMG_NUM_FORMAT_FMASK_32_8_8', 'IMG_NUM_FORMAT_FMASK_64_16_4',
'IMG_NUM_FORMAT_FMASK_64_16_8', 'IMG_NUM_FORMAT_FMASK_8_2_1',
'IMG_NUM_FORMAT_FMASK_8_2_2', 'IMG_NUM_FORMAT_FMASK_8_4_1',
'IMG_NUM_FORMAT_FMASK_8_4_2', 'IMG_NUM_FORMAT_FMASK_8_4_4',
'IMG_NUM_FORMAT_FMASK_8_8_1', 'IMG_NUM_FORMAT_FMASK_RESERVED_13',
'IMG_NUM_FORMAT_FMASK_RESERVED_14',
'IMG_NUM_FORMAT_FMASK_RESERVED_15', 'IMG_NUM_FORMAT_N_IN_16',
'IMG_NUM_FORMAT_N_IN_16_RESERVED_0',
'IMG_NUM_FORMAT_N_IN_16_RESERVED_10',
'IMG_NUM_FORMAT_N_IN_16_RESERVED_11',
'IMG_NUM_FORMAT_N_IN_16_RESERVED_12',
'IMG_NUM_FORMAT_N_IN_16_RESERVED_13',
'IMG_NUM_FORMAT_N_IN_16_RESERVED_14',
'IMG_NUM_FORMAT_N_IN_16_RESERVED_15',
'IMG_NUM_FORMAT_N_IN_16_RESERVED_3',
'IMG_NUM_FORMAT_N_IN_16_RESERVED_6',
'IMG_NUM_FORMAT_N_IN_16_RESERVED_9',
'IMG_NUM_FORMAT_N_IN_16_UINT_10', 'IMG_NUM_FORMAT_N_IN_16_UINT_9',
'IMG_NUM_FORMAT_N_IN_16_UNORM_10',
'IMG_NUM_FORMAT_N_IN_16_UNORM_9',
'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10',
'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9',
'IMG_NUM_FORMAT_RESERVED_14', 'IMG_NUM_FORMAT_RESERVED_15',
'IMG_NUM_FORMAT_RESERVED_8', 'IMG_NUM_FORMAT_SINT',
'IMG_NUM_FORMAT_SNORM', 'IMG_NUM_FORMAT_SNORM_NZ',
'IMG_NUM_FORMAT_SRGB', 'IMG_NUM_FORMAT_SSCALED',
'IMG_NUM_FORMAT_UBINT', 'IMG_NUM_FORMAT_UBNORM',
'IMG_NUM_FORMAT_UBNORM_NZ', 'IMG_NUM_FORMAT_UBSCALED',
'IMG_NUM_FORMAT_UINT', 'IMG_NUM_FORMAT_UNORM',
'IMG_NUM_FORMAT_USCALED',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID',
'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', 'INPUT_INNER_COVERAGE',
'INST_ID_ECC_INTERRUPT_MSG', 'INST_ID_HOST_REG_TRAP_MSG',
'INST_ID_HW_TRAP', 'INST_ID_KILL_SEQ', 'INST_ID_PRIV_START',
'INST_ID_SPI_WREXEC', 'INST_ID_TTRACE_NEW_PC_MSG',
'INTERRUPT_LINE_ASSERTED', 'INTERRUPT_LINE_NOT_ASSERTED',
'INT_DISABLED', 'INT_ENABLED', 'INT_LEVEL', 'INT_MASK',
'INT_PULSE', 'INVALID_REG_ACCESS_TYPE', 'IP_USB_PD_REVISION_ID',
'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD',
'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP',
'IQ_SCH_WAVE_MSG', 'IQ_SEM_REARM', 'JITTER_REMOVE_DISABLE',
'LATE_Z', 'LB_ALPHA_DISABLE', 'LB_ALPHA_EN', 'LB_ALPHA_ENABLE',
'LB_INTERLEAVE_DISABLE', 'LB_INTERLEAVE_EN',
'LB_INTERLEAVE_ENABLE', 'LEFT_EYE', 'LEGACY_NUM_BANKS',
'LEGACY_PIPE_INTERLEAVE', 'LEGACY_PIPE_INTERLEAVE_256B',
'LEGACY_PIPE_INTERLEAVE_512B', 'LINESTRIP', 'LS_STAGE_OFF',
'LS_STAGE_ON', 'LUT_2CFG_MEMORY_A', 'LUT_2CFG_MEMORY_B',
'LUT_2CFG_NO_MEMORY', 'LUT_2_MODE_BYPASS', 'LUT_2_MODE_RAMA_LUT',
'LUT_2_MODE_RAMB_LUT', 'LUT_4CFG_MEMORY_A', 'LUT_4CFG_MEMORY_B',
'LUT_4CFG_NO_MEMORY', 'LUT_4CFG_ROM_A', 'LUT_4CFG_ROM_B',
'LUT_4_MODE_BYPASS', 'LUT_4_MODE_RAMA_LUT', 'LUT_4_MODE_RAMB_LUT',
'LUT_4_MODE_ROMA_LUT', 'LUT_4_MODE_ROMB_LUT',
'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS',
'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH',
'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', 'MACRO_TILE_ASPECT',
'MASTER_UPDATE_LOCK_DB_FIELD_BOTH',
'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED',
'MASTER_UPDATE_LOCK_DB_FIELD_TOP',
'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH',
'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT',
'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED',
'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT',
'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK',
'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE',
'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE',
'MASTER_UPDATE_LOCK_SEL', 'MASTER_UPDATE_LOCK_SEL_0',
'MASTER_UPDATE_LOCK_SEL_1', 'MASTER_UPDATE_LOCK_SEL_2',
'MASTER_UPDATE_LOCK_SEL_3', 'MASTER_UPDATE_LOCK_SEL_4',
'MASTER_UPDATE_LOCK_SEL_5',
'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK',
'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE',
'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP',
'MAX_COMPRESSED_FRAGS', 'MEM_ARB_MODE_AGE', 'MEM_ARB_MODE_BOTH',
'MEM_ARB_MODE_FIXED', 'MEM_ARB_MODE_WEIGHT', 'MEM_PWR_DIS_CTRL',
'MEM_PWR_FORCE_CTRL', 'MEM_PWR_FORCE_CTRL2', 'MEM_PWR_SEL_CTRL',
'MEM_PWR_SEL_CTRL2', 'METADATA_HUBP_SEL', 'METADATA_HUBP_SEL_0',
'METADATA_HUBP_SEL_1', 'METADATA_HUBP_SEL_2',
'METADATA_HUBP_SEL_3', 'METADATA_HUBP_SEL_4',
'METADATA_HUBP_SEL_5', 'METADATA_HUBP_SEL_RESERVED',
'METADATA_STREAM_DP', 'METADATA_STREAM_DVE',
'METADATA_STREAM_TYPE_SEL', 'META_CHUNK_SIZE',
'META_CHUNK_SIZE_1KB', 'META_CHUNK_SIZE_2KB',
'META_CHUNK_SIZE_4KB', 'META_CHUNK_SIZE_8KB', 'META_LINEAR',
'META_SURF_LINEAR', 'META_SURF_TILED', 'ME_ID0', 'ME_ID1',
'ME_ID2', 'ME_ID3', 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK',
'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN',
'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL',
'MICRO_TILE_MODE_DISPLAY_2D', 'MICRO_TILE_MODE_DISPLAY_3D',
'MICRO_TILE_MODE_LINEAR', 'MICRO_TILE_MODE_NEW',
'MICRO_TILE_MODE_RENDER_TARGET', 'MICRO_TILE_MODE_STD_2D',
'MICRO_TILE_MODE_STD_3D', 'MICRO_TILE_MODE_Z',
'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK',
'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN',
'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MIN_CHUNK_SIZE',
'MIN_CHUNK_SIZE_1024B', 'MIN_CHUNK_SIZE_256B',
'MIN_CHUNK_SIZE_512B', 'MIN_META_CHUNK_SIZE',
'MIN_META_CHUNK_SIZE_128B', 'MIN_META_CHUNK_SIZE_256B',
'MIN_META_CHUNK_SIZE_64B', 'MMHUBBUB_XFC_FRAME_MODE_ENUM',
'MMHUBBUB_XFC_FULL_FRAME_MODE', 'MMHUBBUB_XFC_PARTIAL_FRAME_MODE',
'MMHUBBUB_XFC_PIXEL_FORMAT_ENUM', 'MMHUBBUB_XFC_PIXEL_IS_32BPP',
'MMHUBBUB_XFC_PIXEL_IS_64BPP',
'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM',
'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB',
'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB',
'MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS',
'MMHUBBUB_XFC_XFCMON_MODE_ENUM',
'MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT',
'MMHUBBUB_XFC_XFCMON_MODE_PERIODS', 'MONO_10LSB', 'MONO_10MSB',
'MONO_12LSB', 'MONO_12MSB', 'MONO_16', 'MONO_2BIT', 'MONO_8',
'MPCC_BG_COLOR_BPC', 'MPCC_BG_COLOR_BPC_10bit',
'MPCC_BG_COLOR_BPC_11bit', 'MPCC_BG_COLOR_BPC_12bit',
'MPCC_BG_COLOR_BPC_8bit', 'MPCC_BG_COLOR_BPC_9bit',
'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY',
'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE',
'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED',
'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE',
'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE',
'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE',
'MPCC_CONTROL_MPCC_BOT_GAIN_MODE',
'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0',
'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', 'MPCC_CONTROL_MPCC_MODE',
'MPCC_CONTROL_MPCC_MODE_BYPASS',
'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING',
'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY',
'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH',
'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL',
'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA',
'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB',
'MPCC_OGAM_MODE_0', 'MPCC_OGAM_MODE_1', 'MPCC_OGAM_MODE_2',
'MPCC_OGAM_MODE_MPCC_OGAM_MODE', 'MPCC_OGAM_MODE_RSV',
'MPCC_SM_CONTROL_MPCC_SM_EN', 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE',
'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE',
'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT',
'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE',
'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED',
'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT',
'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE',
'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE',
'MPCC_SM_CONTROL_MPCC_SM_MODE',
'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING',
'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING',
'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING',
'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE',
'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK',
'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE',
'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE',
'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK',
'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE',
'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE',
'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET',
'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE',
'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET',
'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE',
'MPC_CFG_ADR_VUPDATE_LOCK_SET',
'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE',
'MPC_CFG_CFG_VUPDATE_LOCK_SET',
'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE',
'MPC_CFG_CUR_VUPDATE_LOCK_SET',
'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', 'MPC_CFG_MPC_TEST_CLK_SEL',
'MPC_CFG_MPC_TEST_CLK_SEL_0', 'MPC_CFG_MPC_TEST_CLK_SEL_1',
'MPC_CFG_MPC_TEST_CLK_SEL_2', 'MPC_CFG_MPC_TEST_CLK_SEL_3',
'MPC_CRC_CALC_INTERLACE_MODE', 'MPC_CRC_CALC_MODE',
'MPC_CRC_CALC_STEREO_MODE', 'MPC_CRC_CONTINUOUS_MODE',
'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM',
'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH',
'MPC_CRC_INTERLACE_MODE_BOTTOM', 'MPC_CRC_INTERLACE_MODE_TOP',
'MPC_CRC_ONE_SHOT_MODE', 'MPC_CRC_SOURCE_SELECT',
'MPC_CRC_SOURCE_SEL_DPP', 'MPC_CRC_SOURCE_SEL_DWB',
'MPC_CRC_SOURCE_SEL_OPP', 'MPC_CRC_SOURCE_SEL_OTHER',
'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH',
'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT',
'MPC_CRC_STEREO_MODE_LEFT', 'MPC_CRC_STEREO_MODE_RIGHT',
'MPC_OCSC_COEF_FORMAT', 'MPC_OCSC_COEF_FORMAT_S2_13',
'MPC_OCSC_COEF_FORMAT_S3_12', 'MPC_OUT_CSC_MODE',
'MPC_OUT_CSC_MODE_0', 'MPC_OUT_CSC_MODE_1', 'MPC_OUT_CSC_MODE_2',
'MPC_OUT_CSC_MODE_RSV',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH',
'MPC_OUT_RATE_CONTROL_DISABLE_SET',
'MPC_OUT_RATE_CONTROL_SET_DISABLE',
'MPC_OUT_RATE_CONTROL_SET_ENABLE', 'MPTE_GROUP_SIZE',
'MPTE_GROUP_SIZE_1024B', 'MPTE_GROUP_SIZE_128B',
'MPTE_GROUP_SIZE_2048B', 'MPTE_GROUP_SIZE_256B',
'MPTE_GROUP_SIZE_4096B', 'MPTE_GROUP_SIZE_512B',
'MPTE_GROUP_SIZE_64B', 'MPTE_GROUP_SIZE_8192B',
'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED',
'MTYPE', 'MTYPE_CC', 'MTYPE_C_RO_S', 'MTYPE_C_RO_US',
'MTYPE_C_RW_S', 'MTYPE_C_RW_US', 'MTYPE_NC', 'MTYPE_RESERVED_1',
'MTYPE_RESERVED_5', 'MTYPE_RESERVED_7', 'MTYPE_UC', 'MTYPE_WC',
'MULT_16', 'MULT_8', 'MacroTileAspect', 'MemArbMode',
'MicroTileMode', 'MultiGPUTileSize', 'NON_BYPASS', 'NOT_SENT',
'NO_DIST', 'NO_DIV', 'NO_FORCE', 'NO_FORCE_REQ',
'NO_FORCE_REQUEST', 'NO_MIN_CHUNK_SIZE', 'NO_MIN_META_CHUNK_SIZE',
'NO_OUTSTANDING_REQ', 'NUMBER_FLOAT', 'NUMBER_SINT',
'NUMBER_SNORM', 'NUMBER_SRGB', 'NUMBER_SSCALED', 'NUMBER_UINT',
'NUMBER_UNORM', 'NUMBER_USCALED', 'NUM_BANKS',
'NUM_BANKS_BC_ENUM', 'NUM_PIPES', 'NUM_PIPES_BC_ENUM',
'NUM_RB_PER_SE', 'NUM_SE', 'NUM_SIMD_PER_CU',
'NonDispTilingOrder', 'NumBanks', 'NumBanksConfig', 'NumGPUs',
'NumLowerPipes', 'NumMaxCompressedFragments', 'NumPipes',
'NumRbPerShaderEngine', 'NumShaderEngines', 'OBUF_BYPASS_DIS',
'OBUF_BYPASS_EN', 'OBUF_BYPASS_SEL', 'OBUF_FULL',
'OBUF_FULL_RECOUT', 'OBUF_HALF_RECOUT',
'OBUF_IS_HALF_RECOUT_WIDTH_SEL', 'OBUF_RECOUT',
'OBUF_USE_FULL_BUFFER_SEL', 'OFFCHIP_HS_DEALLOC', 'OFF_SEQ',
'ONE_BANK', 'ONE_FRAGMENT', 'ONE_PIPE', 'ONE_RB_PER_SE',
'ONE_SHADER_ENGIN', 'ON_SEQ', 'OPP_PIPE_CLOCK_DISABLE',
'OPP_PIPE_CLOCK_ENABLE', 'OPP_PIPE_CLOCK_ENABLE_CONTROL',
'OPP_PIPE_CRC_CONT_EN', 'OPP_PIPE_CRC_DISABLE', 'OPP_PIPE_CRC_EN',
'OPP_PIPE_CRC_ENABLE', 'OPP_PIPE_CRC_INTERLACE_EN',
'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED',
'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE',
'OPP_PIPE_CRC_INTERLACE_MODE',
'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD',
'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD',
'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM',
'OPP_PIPE_CRC_INTERLACE_MODE_TOP', 'OPP_PIPE_CRC_MODE_CONTINUOUS',
'OPP_PIPE_CRC_MODE_ONE_SHOT', 'OPP_PIPE_CRC_ONE_SHOT_PENDING',
'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING',
'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING',
'OPP_PIPE_CRC_PIXEL_SELECT',
'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS',
'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS',
'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS',
'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED',
'OPP_PIPE_CRC_SOURCE_SELECT', 'OPP_PIPE_CRC_SOURCE_SELECT_FMT',
'OPP_PIPE_CRC_SOURCE_SELECT_SFT', 'OPP_PIPE_CRC_STEREO_EN',
'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO',
'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO',
'OPP_PIPE_CRC_STEREO_MODE',
'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE',
'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE',
'OPP_PIPE_CRC_STEREO_MODE_LEFT', 'OPP_PIPE_CRC_STEREO_MODE_RIGHT',
'OPP_PIPE_DIGTIAL_BYPASS_CONTROL',
'OPP_PIPE_DIGTIAL_BYPASS_DISABLE',
'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', 'OPP_TEST_CLK_SEL_CONTROL',
'OPP_TEST_CLK_SEL_DISPCLK_ABM0', 'OPP_TEST_CLK_SEL_DISPCLK_OPP0',
'OPP_TEST_CLK_SEL_DISPCLK_OPP1', 'OPP_TEST_CLK_SEL_DISPCLK_OPP2',
'OPP_TEST_CLK_SEL_DISPCLK_OPP3', 'OPP_TEST_CLK_SEL_DISPCLK_OPP4',
'OPP_TEST_CLK_SEL_DISPCLK_OPP5', 'OPP_TEST_CLK_SEL_DISPCLK_P',
'OPP_TEST_CLK_SEL_DISPCLK_R', 'OPP_TEST_CLK_SEL_RESERVED0',
'OPP_TOP_CLOCK_DISABLED_STATUS', 'OPP_TOP_CLOCK_ENABLED_STATUS',
'OPP_TOP_CLOCK_ENABLE_STATUS', 'OPP_TOP_CLOCK_GATING_CONTROL',
'OPP_TOP_CLOCK_GATING_DISABLED', 'OPP_TOP_CLOCK_GATING_ENABLED',
'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', 'OPT_COMB_MAX',
'OPT_COMB_MIN', 'OPT_COMB_NONE', 'OPT_COMB_REVSUBTRACT',
'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED',
'OTG_ADD_PIXEL', 'OTG_ADD_PIXEL_FORCE', 'OTG_ADD_PIXEL_NOOP',
'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN',
'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE',
'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE',
'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE',
'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE',
'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED',
'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE',
'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE',
'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE',
'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL',
'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP',
'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL',
'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY',
'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE',
'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE',
'OTG_CONTROL_OTG_MASTER_EN', 'OTG_CONTROL_OTG_MASTER_EN_FALSE',
'OTG_CONTROL_OTG_MASTER_EN_TRUE', 'OTG_CONTROL_OTG_SOF_PULL_EN',
'OTG_CONTROL_OTG_SOF_PULL_EN_FALSE',
'OTG_CONTROL_OTG_SOF_PULL_EN_TRUE',
'OTG_CONTROL_OTG_START_POINT_CNTL',
'OTG_CONTROL_OTG_START_POINT_CNTL_DP',
'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL',
'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN',
'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE',
'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE',
'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT',
'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0',
'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1',
'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2',
'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3',
'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE',
'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE',
'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE',
'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE',
'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1',
'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2',
'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3',
'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE',
'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE',
'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE',
'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE',
'OTG_CRC_CNTL_OTG_CRC_CONT_EN',
'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE',
'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', 'OTG_CRC_CNTL_OTG_CRC_EN',
'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT',
'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS',
'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE',
'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE',
'OTG_DROP_PIXEL', 'OTG_DROP_PIXEL_FORCE', 'OTG_DROP_PIXEL_NOOP',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME',
'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN',
'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE',
'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE',
'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE',
'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR',
'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE',
'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE',
'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE',
'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE',
'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE',
'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE',
'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE',
'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE',
'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE',
'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR',
'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE',
'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE',
'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE',
'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE',
'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE',
'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE',
'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE',
'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE',
'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT',
'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE',
'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE',
'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY',
'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE',
'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5',
'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD',
'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL',
'OTG_GSL_MASTER_MODE', 'OTG_GSL_MASTER_MODE_0',
'OTG_GSL_MASTER_MODE_1', 'OTG_GSL_MASTER_MODE_2',
'OTG_GSL_MASTER_MODE_3', 'OTG_HORZ_REPETITION_COUNT',
'OTG_HORZ_REPETITION_COUNT_0', 'OTG_HORZ_REPETITION_COUNT_1',
'OTG_HORZ_REPETITION_COUNT_10', 'OTG_HORZ_REPETITION_COUNT_11',
'OTG_HORZ_REPETITION_COUNT_12', 'OTG_HORZ_REPETITION_COUNT_13',
'OTG_HORZ_REPETITION_COUNT_14', 'OTG_HORZ_REPETITION_COUNT_15',
'OTG_HORZ_REPETITION_COUNT_2', 'OTG_HORZ_REPETITION_COUNT_3',
'OTG_HORZ_REPETITION_COUNT_4', 'OTG_HORZ_REPETITION_COUNT_5',
'OTG_HORZ_REPETITION_COUNT_6', 'OTG_HORZ_REPETITION_COUNT_7',
'OTG_HORZ_REPETITION_COUNT_8', 'OTG_HORZ_REPETITION_COUNT_9',
'OTG_H_SYNC_A_POL', 'OTG_H_SYNC_A_POL_HIGH',
'OTG_H_SYNC_A_POL_LOW', 'OTG_H_TIMING_DIV_BY2',
'OTG_H_TIMING_DIV_BY2_FALSE', 'OTG_H_TIMING_DIV_BY2_TRUE',
'OTG_H_TIMING_DIV_BY2_UPDATE_MODE',
'OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0',
'OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE',
'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE',
'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE',
'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE',
'OTG_MASTER_UPDATE_LOCK_GSL_EN',
'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE',
'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE',
'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE',
'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG',
'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE',
'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL',
'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR',
'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE',
'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE',
'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR',
'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE',
'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE', 'OTG_PIPE_ABORT',
'OTG_PIPE_ABORT_0', 'OTG_PIPE_ABORT_1',
'OTG_PTI_CONTROL_OTG_PIT_EN', 'OTG_PTI_CONTROL_OTG_PIT_EN_FALSE',
'OTG_PTI_CONTROL_OTG_PIT_EN_TRUE',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB',
'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR',
'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE',
'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE',
'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY',
'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE',
'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE',
'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN',
'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE',
'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE',
'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN',
'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE',
'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE',
'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY',
'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE',
'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON',
'OTG_STEREO_CONTROL_OTG_STEREO_EN',
'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE',
'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE',
'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY',
'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE',
'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE',
'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY',
'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE',
'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT',
'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR',
'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE',
'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1',
'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN',
'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE',
'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3',
'OTG_TRIGA_FREQUENCY_SELECT', 'OTG_TRIGA_FREQUENCY_SELECT_0',
'OTG_TRIGA_FREQUENCY_SELECT_1', 'OTG_TRIGA_FREQUENCY_SELECT_2',
'OTG_TRIGA_FREQUENCY_SELECT_3',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3',
'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR',
'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE',
'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1',
'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN',
'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE',
'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3',
'OTG_TRIGB_FREQUENCY_SELECT', 'OTG_TRIGB_FREQUENCY_SELECT_0',
'OTG_TRIGB_FREQUENCY_SELECT_1', 'OTG_TRIGB_FREQUENCY_SELECT_2',
'OTG_TRIGB_FREQUENCY_SELECT_3',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3',
'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK',
'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE',
'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB',
'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR',
'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE',
'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE',
'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE',
'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE',
'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE',
'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR',
'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE',
'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE',
'OTG_V_SYNC_A_POL', 'OTG_V_SYNC_A_POL_HIGH',
'OTG_V_SYNC_A_POL_LOW',
'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD',
'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0',
'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE',
'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN',
'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE',
'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE',
'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK',
'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE',
'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE',
'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR',
'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE',
'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE',
'OUTPUT_LINE', 'OUTPUT_POINT',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ',
'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', 'OUTSTANDING_REQ',
'OVERRUN', 'P16_32x32_16x16', 'P16_32x32_8x16', 'P16_ADDR_SURF',
'P2', 'P4_16x16', 'P4_16x32', 'P4_32x32', 'P4_8x16',
'P8_16x16_8x16', 'P8_16x32_16x16', 'P8_16x32_8x16',
'P8_32x32_16x16', 'P8_32x32_16x32', 'P8_32x32_8x16',
'P8_32x64_32x32', 'PART_FRAC_EVEN', 'PART_FRAC_ODD',
'PART_INTEGER', 'PART_POW2', 'PATCHES', 'PERFCOUNTER_ACTIVE',
'PERFCOUNTER_CNT0_STATE', 'PERFCOUNTER_CNT0_STATE_FREEZE',
'PERFCOUNTER_CNT0_STATE_HW', 'PERFCOUNTER_CNT0_STATE_RESET',
'PERFCOUNTER_CNT0_STATE_START', 'PERFCOUNTER_CNT1_STATE',
'PERFCOUNTER_CNT1_STATE_FREEZE', 'PERFCOUNTER_CNT1_STATE_HW',
'PERFCOUNTER_CNT1_STATE_RESET', 'PERFCOUNTER_CNT1_STATE_START',
'PERFCOUNTER_CNT2_STATE', 'PERFCOUNTER_CNT2_STATE_FREEZE',
'PERFCOUNTER_CNT2_STATE_HW', 'PERFCOUNTER_CNT2_STATE_RESET',
'PERFCOUNTER_CNT2_STATE_START', 'PERFCOUNTER_CNT3_STATE',
'PERFCOUNTER_CNT3_STATE_FREEZE', 'PERFCOUNTER_CNT3_STATE_HW',
'PERFCOUNTER_CNT3_STATE_RESET', 'PERFCOUNTER_CNT3_STATE_START',
'PERFCOUNTER_CNT4_STATE', 'PERFCOUNTER_CNT4_STATE_FREEZE',
'PERFCOUNTER_CNT4_STATE_HW', 'PERFCOUNTER_CNT4_STATE_RESET',
'PERFCOUNTER_CNT4_STATE_START', 'PERFCOUNTER_CNT5_STATE',
'PERFCOUNTER_CNT5_STATE_FREEZE', 'PERFCOUNTER_CNT5_STATE_HW',
'PERFCOUNTER_CNT5_STATE_RESET', 'PERFCOUNTER_CNT5_STATE_START',
'PERFCOUNTER_CNT6_STATE', 'PERFCOUNTER_CNT6_STATE_FREEZE',
'PERFCOUNTER_CNT6_STATE_HW', 'PERFCOUNTER_CNT6_STATE_RESET',
'PERFCOUNTER_CNT6_STATE_START', 'PERFCOUNTER_CNT7_STATE',
'PERFCOUNTER_CNT7_STATE_FREEZE', 'PERFCOUNTER_CNT7_STATE_HW',
'PERFCOUNTER_CNT7_STATE_RESET', 'PERFCOUNTER_CNT7_STATE_START',
'PERFCOUNTER_CNTL_SEL', 'PERFCOUNTER_CNTL_SEL_0',
'PERFCOUNTER_CNTL_SEL_1', 'PERFCOUNTER_CNTL_SEL_2',
'PERFCOUNTER_CNTL_SEL_3', 'PERFCOUNTER_CNTL_SEL_4',
'PERFCOUNTER_CNTL_SEL_5', 'PERFCOUNTER_CNTL_SEL_6',
'PERFCOUNTER_CNTL_SEL_7', 'PERFCOUNTER_CNTOFF_START_DIS',
'PERFCOUNTER_CNTOFF_START_DISABLE',
'PERFCOUNTER_CNTOFF_START_ENABLE',
'PERFCOUNTER_COUNTED_VALUE_TYPE',
'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC',
'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX',
'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL',
'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0',
'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16',
'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0',
'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36',
'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF',
'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_HW_STOP1_0',
'PERFCOUNTER_HW_STOP1_1', 'PERFCOUNTER_HW_STOP1_SEL',
'PERFCOUNTER_HW_STOP2_0', 'PERFCOUNTER_HW_STOP2_1',
'PERFCOUNTER_HW_STOP2_SEL', 'PERFCOUNTER_INC_MODE',
'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB',
'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE',
'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE',
'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE',
'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL',
'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE',
'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK',
'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE',
'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN',
'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE',
'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL',
'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START',
'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL',
'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1',
'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL',
'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL',
'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3',
'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL',
'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL',
'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5',
'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL',
'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL',
'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7',
'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL',
'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR',
'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN',
'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE',
'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE',
'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE',
'PERFMON_COUNTER_MODE_ACCUM',
'PERFMON_COUNTER_MODE_ACTIVE_CYCLES',
'PERFMON_COUNTER_MODE_CYCLES_EQ_HI',
'PERFMON_COUNTER_MODE_CYCLES_GE_HI',
'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT',
'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT',
'PERFMON_COUNTER_MODE_DIRTY',
'PERFMON_COUNTER_MODE_INACTIVE_CYCLES',
'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED',
'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE',
'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP',
'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP',
'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5',
'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7',
'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1',
'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE',
'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET',
'PERFMON_STATE_START', 'PERF_CLIENT_UTCL1_INFLIGHT',
'PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_10_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_11_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_12_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_13_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_14_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_15_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_1_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_2_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_3_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_4_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_5_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_6_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_7_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_8_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_9_VALID_DWORDS_THIS_CACHELINE',
'PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE',
'PERF_INDEX_RECEIVE_QUALIFIED_BUSY',
'PERF_INDEX_RECEIVE_QUALIFIED_STARVED',
'PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO',
'PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE',
'PERF_INDEX_REQUEST_QUALIFIED_BUSY',
'PERF_INDEX_REQUEST_QUALIFIED_STARVED',
'PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO',
'PERF_INDEX_REQUEST_WAITING_ON_TOKENS', 'PERF_PAPC_CCGSM_BUSY',
'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED',
'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE',
'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP',
'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY',
'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP',
'PERF_PAPC_CLIPSM_WAIT_CLIPGA',
'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM',
'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH',
'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY',
'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY',
'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED',
'PERF_PAPC_CLPRIM_STARVED_CCGSM',
'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12',
'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT',
'PERF_PAPC_CLPR_CLIP_PLANE_NEAR',
'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT',
'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM',
'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM',
'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM',
'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE',
'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM',
'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM',
'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM',
'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM',
'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM',
'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM',
'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM',
'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM',
'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2',
'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4',
'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8',
'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13',
'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM',
'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_DISABLE_PIPE',
'PERF_PAPC_PASX_FIRST_DEAD', 'PERF_PAPC_PASX_FIRST_VECTOR',
'PERF_PAPC_PASX_REC_BUSY', 'PERF_PAPC_PASX_REC_IDLE',
'PERF_PAPC_PASX_REC_STALLED',
'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN',
'PERF_PAPC_PASX_REC_STALLED_POS_MEM',
'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ',
'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE',
'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_SE0_FIRST_VECTOR',
'PERF_PAPC_PASX_SE0_REQ', 'PERF_PAPC_PASX_SE0_SECOND_VECTOR',
'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 'PERF_PAPC_PASX_SE1_REQ',
'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 'PERF_PAPC_PASX_SECOND_DEAD',
'PERF_PAPC_PASX_SECOND_VECTOR', 'PERF_PAPC_PASX_VTX_KILL_DISCARD',
'PERF_PAPC_PASX_VTX_NAN_DISCARD',
'PERF_PAPC_PA_INPUT_END_OF_PACKET',
'PERF_PAPC_PA_INPUT_EVENT_FLAG',
'PERF_PAPC_PA_INPUT_EXTENDED_EVENT',
'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT',
'PERF_PAPC_PA_INPUT_NULL_PRIM', 'PERF_PAPC_PA_INPUT_PRIM',
'PERF_PAPC_PA_REG_SCLK_VLD', 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM',
'PERF_PAPC_SU_BUSY', 'PERF_PAPC_SU_CULLED_PRIM',
'PERF_PAPC_SU_DYN_SCLK_VLD', 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM',
'PERF_PAPC_SU_IDLE', 'PERF_PAPC_SU_INPUT_CLIP_PRIM',
'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL',
'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM',
'PERF_PAPC_SU_INPUT_PRIM_DUAL',
'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL',
'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL',
'PERF_PAPC_SU_OUTPUT_CLIP_PRIM',
'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL',
'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG',
'PERF_PAPC_SU_OUTPUT_EVENT_FLAG',
'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT',
'PERF_PAPC_SU_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK',
'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL',
'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE',
'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM',
'PERF_PAPC_SU_OUTPUT_PRIM_DUAL',
'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK',
'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE',
'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT',
'PERF_PAPC_SU_POLYMODE_BACK_CULL',
'PERF_PAPC_SU_POLYMODE_FACE_CULL',
'PERF_PAPC_SU_POLYMODE_FRONT_CULL',
'PERF_PAPC_SU_POLYMODE_INVALID_FILL',
'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE01_OUTPUT_PRIM',
'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE01_STALLED_SC',
'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET',
'PERF_PAPC_SU_SE0_OUTPUT_EOPG',
'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT',
'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE0_OUTPUT_PRIM',
'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE0_STALLED_SC',
'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET',
'PERF_PAPC_SU_SE1_OUTPUT_EOPG',
'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT',
'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE1_OUTPUT_PRIM',
'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE1_STALLED_SC',
'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET',
'PERF_PAPC_SU_SE2_OUTPUT_EOPG',
'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE2_OUTPUT_PRIM',
'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE2_STALLED_SC',
'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET',
'PERF_PAPC_SU_SE3_OUTPUT_EOPG',
'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE3_OUTPUT_PRIM',
'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE3_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC',
'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM',
'PERF_PAWD_DEALLOC_FIFO_IS_FULL',
'PERF_PAWD_DEALLOC_WAITING_TO_BE_READ',
'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL',
'PERF_PA_FETCH_TO_SXIF_FIFO_FULL',
'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL',
'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND',
'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND',
'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED',
'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND',
'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND',
'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED',
'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND',
'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND',
'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED',
'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND',
'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND',
'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED',
'PERF_PA_VERTEX_FIFO_FULL',
'PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE',
'PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE',
'PERF_POS_REQ_QUALIFIED_BUSY', 'PERF_POS_REQ_QUALIFIED_STARVED',
'PERF_POS_REQ_REUSE_0_NEW_VERTS_THIS_PRIM',
'PERF_POS_REQ_REUSE_1_NEW_VERTS_THIS_PRIM',
'PERF_POS_REQ_REUSE_2_NEW_VERTS_THIS_PRIM',
'PERF_POS_REQ_REUSE_3_NEW_VERTS_THIS_PRIM',
'PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO',
'PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO',
'PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO',
'PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO',
'PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO',
'PERF_POS_REQ_STALLED_BY_NO_TOKENS',
'PERF_POS_REQ_STALLED_BY_UTCL1',
'PERF_POS_REQ_STARVED_BY_NO_PRIM',
'PERF_POS_RET_1_CACHELINE_POSITION_USED',
'PERF_POS_RET_2_CACHELINE_POSITION_USED',
'PERF_POS_RET_3_CACHELINE_POSITION_USED',
'PERF_POS_RET_4_CACHELINE_POSITION_USED',
'PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE',
'PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO',
'PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO',
'PERF_POS_RET_QUALIFIED_BUSY', 'PERF_POS_RET_QUALIFIED_STARVED',
'PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE',
'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT',
'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT',
'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT',
'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT',
'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT',
'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT',
'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT',
'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT',
'PERF_SHOOTDOWN_WAIT_ALL_CLEAN', 'PERF_SHOOTDOWN_WAIT_DEASSERT',
'PERF_SHOOTDOWN_WAIT_ON_UTCL1',
'PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX',
'PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION',
'PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND',
'PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_',
'PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_',
'PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_',
'PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_',
'PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD',
'PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD',
'PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD',
'PERF_SIDEBAND_FIFO_VMID_FIFO_FULL',
'PERF_SIDEBAND_INVALID_REFETCH',
'PERF_SIDEBAND_POP_BIT_FIFO_FULL', 'PERF_SIDEBAND_QUALIFIED_BUSY',
'PERF_SIDEBAND_QUALIFIED_STARVED',
'PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY',
'PERF_SIDEBAND_WAITING_ON_RETURNED_DATA',
'PERF_SIDEBAND_WAITING_ON_UTCL1', 'PERF_SMALL_PRIM_CULL_PRIM_1X1',
'PERF_SMALL_PRIM_CULL_PRIM_1X2', 'PERF_SMALL_PRIM_CULL_PRIM_1X3',
'PERF_SMALL_PRIM_CULL_PRIM_1XN', 'PERF_SMALL_PRIM_CULL_PRIM_2X1',
'PERF_SMALL_PRIM_CULL_PRIM_2X2', 'PERF_SMALL_PRIM_CULL_PRIM_2X3',
'PERF_SMALL_PRIM_CULL_PRIM_2XN', 'PERF_SMALL_PRIM_CULL_PRIM_3X1',
'PERF_SMALL_PRIM_CULL_PRIM_3X2',
'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT',
'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT',
'PERF_SMALL_PRIM_CULL_PRIM_NX1', 'PERF_SMALL_PRIM_CULL_PRIM_NX2',
'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT',
'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', 'PERF_TCIF_BUSY',
'PERF_TCIF_INDEX_RDREQ', 'PERF_TCIF_POSITION_RDREQ',
'PERF_TCIF_SIDEBAND_RDREQ',
'PERF_TCIF_STALLING_CLIENT_NO_CREDITS',
'PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE',
'PERF_TC_INDEX_LATENCY_BIN0', 'PERF_TC_INDEX_LATENCY_BIN1',
'PERF_TC_INDEX_LATENCY_BIN10', 'PERF_TC_INDEX_LATENCY_BIN11',
'PERF_TC_INDEX_LATENCY_BIN12', 'PERF_TC_INDEX_LATENCY_BIN13',
'PERF_TC_INDEX_LATENCY_BIN14', 'PERF_TC_INDEX_LATENCY_BIN15',
'PERF_TC_INDEX_LATENCY_BIN2', 'PERF_TC_INDEX_LATENCY_BIN3',
'PERF_TC_INDEX_LATENCY_BIN4', 'PERF_TC_INDEX_LATENCY_BIN5',
'PERF_TC_INDEX_LATENCY_BIN6', 'PERF_TC_INDEX_LATENCY_BIN7',
'PERF_TC_INDEX_LATENCY_BIN8', 'PERF_TC_INDEX_LATENCY_BIN9',
'PERF_TC_POSITION_LATENCY_BIN0', 'PERF_TC_POSITION_LATENCY_BIN1',
'PERF_TC_POSITION_LATENCY_BIN10',
'PERF_TC_POSITION_LATENCY_BIN11',
'PERF_TC_POSITION_LATENCY_BIN12',
'PERF_TC_POSITION_LATENCY_BIN13',
'PERF_TC_POSITION_LATENCY_BIN14',
'PERF_TC_POSITION_LATENCY_BIN15', 'PERF_TC_POSITION_LATENCY_BIN2',
'PERF_TC_POSITION_LATENCY_BIN3', 'PERF_TC_POSITION_LATENCY_BIN4',
'PERF_TC_POSITION_LATENCY_BIN5', 'PERF_TC_POSITION_LATENCY_BIN6',
'PERF_TC_POSITION_LATENCY_BIN7', 'PERF_TC_POSITION_LATENCY_BIN8',
'PERF_TC_POSITION_LATENCY_BIN9', 'PERF_TC_STREAM0_DATA_AVAILABLE',
'PERF_TC_STREAM1_DATA_AVAILABLE',
'PERF_TC_STREAM2_DATA_AVAILABLE', 'PERF_UTCL1_LFIFO_FULL',
'PERF_UTCL1_PERMISSION_MISS_CLIENT0',
'PERF_UTCL1_PERMISSION_MISS_CLIENT1',
'PERF_UTCL1_PERMISSION_MISS_CLIENT2',
'PERF_UTCL1_REQUEST_CLIENT0', 'PERF_UTCL1_REQUEST_CLIENT1',
'PERF_UTCL1_REQUEST_CLIENT2', 'PERF_UTCL1_STALL_INFLIGHT_MAX',
'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0',
'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1',
'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2',
'PERF_UTCL1_STALL_LRU_INFLIGHT', 'PERF_UTCL1_STALL_MISSFIFO_FULL',
'PERF_UTCL1_STALL_MULTI_MISS',
'PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS',
'PERF_UTCL1_TRANSLATION_HIT_CLIENT0',
'PERF_UTCL1_TRANSLATION_HIT_CLIENT1',
'PERF_UTCL1_TRANSLATION_HIT_CLIENT2',
'PERF_UTCL1_TRANSLATION_MISS_CLIENT0',
'PERF_UTCL1_TRANSLATION_MISS_CLIENT1',
'PERF_UTCL1_TRANSLATION_MISS_CLIENT2',
'PERF_UTCL1_UTCL2_INFLIGHT', 'PERF_UTCL1_UTCL2_REQ',
'PERF_UTCL1_UTCL2_RET', 'PERF_UTC_INDEX_DRIVER_BUSY',
'PERF_UTC_INDEX_DRIVER_STALLING_CLIENT',
'PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1',
'PERF_UTC_INDEX_RECEIVER_BUSY',
'PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER',
'PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1',
'PERF_UTC_POSITION_DRIVER_BUSY',
'PERF_UTC_POSITION_DRIVER_STALLING_CLIENT',
'PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1',
'PERF_UTC_POSITION_RECEIVER_BUSY',
'PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER',
'PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1',
'PERF_UTC_SIDEBAND_DRIVER_BUSY',
'PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT',
'PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1',
'PERF_UTC_SIDEBAND_RECEIVER_BUSY',
'PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER',
'PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1',
'PERF_WRITING_TO_SIDEBAND_MEMORY', 'PERSISTENT_SPACE_END',
'PERSISTENT_SPACE_START', 'PH_PERFCNT_SEL', 'PH_SC0_ARB_BUSY',
'PH_SC0_ARB_EOP_POP_SYNC_POP', 'PH_SC0_ARB_EVENT_SYNC_POP',
'PH_SC0_ARB_PA_BUSY_SOP', 'PH_SC0_ARB_STALLED_FROM_BELOW',
'PH_SC0_ARB_STARVED_FROM_ABOVE',
'PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC0_BUSY_CNT_NOT_ZERO',
'PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC0_CREDIT_AT_MAX',
'PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_SC0_EOP_SYNC_WINDOW', 'PH_SC0_GFX_PIPE0_TO_1_TRANSITION',
'PH_SC0_GFX_PIPE1_TO_0_TRANSITION',
'PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION',
'PH_SC0_PA0_DATA_FIFO_EOP_RD', 'PH_SC0_PA0_DATA_FIFO_RD',
'PH_SC0_PA0_DATA_FIFO_WE', 'PH_SC0_PA0_DEALLOC_4_0_RD',
'PH_SC0_PA0_EOPG_WE', 'PH_SC0_PA0_EOP_WE', 'PH_SC0_PA0_EVENT_WE',
'PH_SC0_PA0_FIFO_EMPTY', 'PH_SC0_PA0_FIFO_FULL',
'PH_SC0_PA0_FPOV_WE', 'PH_SC0_PA0_LPOV_WE', 'PH_SC0_PA0_NULL_WE',
'PH_SC0_PA1_DATA_FIFO_EOP_RD', 'PH_SC0_PA1_DATA_FIFO_RD',
'PH_SC0_PA1_DATA_FIFO_WE', 'PH_SC0_PA1_DEALLOC_4_0_RD',
'PH_SC0_PA1_EOPG_WE', 'PH_SC0_PA1_EOP_WE', 'PH_SC0_PA1_EVENT_WE',
'PH_SC0_PA1_FIFO_EMPTY', 'PH_SC0_PA1_FIFO_FULL',
'PH_SC0_PA1_FPOV_WE', 'PH_SC0_PA1_LPOV_WE', 'PH_SC0_PA1_NULL_WE',
'PH_SC0_PA2_DATA_FIFO_EOP_RD', 'PH_SC0_PA2_DATA_FIFO_RD',
'PH_SC0_PA2_DATA_FIFO_WE', 'PH_SC0_PA2_DEALLOC_4_0_RD',
'PH_SC0_PA2_EOPG_WE', 'PH_SC0_PA2_EOP_WE', 'PH_SC0_PA2_EVENT_WE',
'PH_SC0_PA2_FIFO_EMPTY', 'PH_SC0_PA2_FIFO_FULL',
'PH_SC0_PA2_FPOV_WE', 'PH_SC0_PA2_LPOV_WE', 'PH_SC0_PA2_NULL_WE',
'PH_SC0_PA3_DATA_FIFO_EOP_RD', 'PH_SC0_PA3_DATA_FIFO_RD',
'PH_SC0_PA3_DATA_FIFO_WE', 'PH_SC0_PA3_DEALLOC_4_0_RD',
'PH_SC0_PA3_EOPG_WE', 'PH_SC0_PA3_EOP_WE', 'PH_SC0_PA3_EVENT_WE',
'PH_SC0_PA3_FIFO_EMPTY', 'PH_SC0_PA3_FIFO_FULL',
'PH_SC0_PA3_FPOV_WE', 'PH_SC0_PA3_LPOV_WE', 'PH_SC0_PA3_NULL_WE',
'PH_SC0_PA4_DATA_FIFO_EOP_RD', 'PH_SC0_PA4_DATA_FIFO_RD',
'PH_SC0_PA4_DATA_FIFO_WE', 'PH_SC0_PA4_DEALLOC_4_0_RD',
'PH_SC0_PA4_EOPG_WE', 'PH_SC0_PA4_EOP_WE', 'PH_SC0_PA4_EVENT_WE',
'PH_SC0_PA4_FIFO_EMPTY', 'PH_SC0_PA4_FIFO_FULL',
'PH_SC0_PA4_FPOV_WE', 'PH_SC0_PA4_LPOV_WE', 'PH_SC0_PA4_NULL_WE',
'PH_SC0_PA5_DATA_FIFO_EOP_RD', 'PH_SC0_PA5_DATA_FIFO_RD',
'PH_SC0_PA5_DATA_FIFO_WE', 'PH_SC0_PA5_DEALLOC_4_0_RD',
'PH_SC0_PA5_EOPG_WE', 'PH_SC0_PA5_EOP_WE', 'PH_SC0_PA5_EVENT_WE',
'PH_SC0_PA5_FIFO_EMPTY', 'PH_SC0_PA5_FIFO_FULL',
'PH_SC0_PA5_FPOV_WE', 'PH_SC0_PA5_LPOV_WE', 'PH_SC0_PA5_NULL_WE',
'PH_SC0_PA6_DATA_FIFO_EOP_RD', 'PH_SC0_PA6_DATA_FIFO_RD',
'PH_SC0_PA6_DATA_FIFO_WE', 'PH_SC0_PA6_DEALLOC_4_0_RD',
'PH_SC0_PA6_EOPG_WE', 'PH_SC0_PA6_EOP_WE', 'PH_SC0_PA6_EVENT_WE',
'PH_SC0_PA6_FIFO_EMPTY', 'PH_SC0_PA6_FIFO_FULL',
'PH_SC0_PA6_FPOV_WE', 'PH_SC0_PA6_LPOV_WE', 'PH_SC0_PA6_NULL_WE',
'PH_SC0_PA7_DATA_FIFO_EOP_RD', 'PH_SC0_PA7_DATA_FIFO_RD',
'PH_SC0_PA7_DATA_FIFO_WE', 'PH_SC0_PA7_DEALLOC_4_0_RD',
'PH_SC0_PA7_EOPG_WE', 'PH_SC0_PA7_EOP_WE', 'PH_SC0_PA7_EVENT_WE',
'PH_SC0_PA7_FIFO_EMPTY', 'PH_SC0_PA7_FIFO_FULL',
'PH_SC0_PA7_FPOV_WE', 'PH_SC0_PA7_LPOV_WE', 'PH_SC0_PA7_NULL_WE',
'PH_SC0_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC0_SEND',
'PH_SC0_SRPS_WINDOW_VALID', 'PH_SC1_ARB_BUSY',
'PH_SC1_ARB_EOP_POP_SYNC_POP', 'PH_SC1_ARB_EVENT_SYNC_POP',
'PH_SC1_ARB_PA_BUSY_SOP', 'PH_SC1_ARB_STALLED_FROM_BELOW',
'PH_SC1_ARB_STARVED_FROM_ABOVE',
'PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC1_BUSY_CNT_NOT_ZERO',
'PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC1_CREDIT_AT_MAX',
'PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_SC1_EOP_SYNC_WINDOW', 'PH_SC1_GFX_PIPE0_TO_1_TRANSITION',
'PH_SC1_GFX_PIPE1_TO_0_TRANSITION',
'PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_SC1_PA0_DATA_FIFO_EOP_RD', 'PH_SC1_PA0_DATA_FIFO_RD',
'PH_SC1_PA0_DATA_FIFO_WE', 'PH_SC1_PA0_DEALLOC_4_0_RD',
'PH_SC1_PA0_EOPG_WE', 'PH_SC1_PA0_EOP_WE', 'PH_SC1_PA0_EVENT_WE',
'PH_SC1_PA0_FIFO_EMPTY', 'PH_SC1_PA0_FIFO_FULL',
'PH_SC1_PA0_FPOV_WE', 'PH_SC1_PA0_LPOV_WE', 'PH_SC1_PA0_NULL_WE',
'PH_SC1_PA1_DATA_FIFO_EOP_RD', 'PH_SC1_PA1_DATA_FIFO_RD',
'PH_SC1_PA1_DATA_FIFO_WE', 'PH_SC1_PA1_DEALLOC_4_0_RD',
'PH_SC1_PA1_EOPG_WE', 'PH_SC1_PA1_EOP_WE', 'PH_SC1_PA1_EVENT_WE',
'PH_SC1_PA1_FIFO_EMPTY', 'PH_SC1_PA1_FIFO_FULL',
'PH_SC1_PA1_FPOV_WE', 'PH_SC1_PA1_LPOV_WE', 'PH_SC1_PA1_NULL_WE',
'PH_SC1_PA2_DATA_FIFO_EOP_RD', 'PH_SC1_PA2_DATA_FIFO_RD',
'PH_SC1_PA2_DATA_FIFO_WE', 'PH_SC1_PA2_DEALLOC_4_0_RD',
'PH_SC1_PA2_EOPG_WE', 'PH_SC1_PA2_EOP_WE', 'PH_SC1_PA2_EVENT_WE',
'PH_SC1_PA2_FIFO_EMPTY', 'PH_SC1_PA2_FIFO_FULL',
'PH_SC1_PA2_FPOV_WE', 'PH_SC1_PA2_LPOV_WE', 'PH_SC1_PA2_NULL_WE',
'PH_SC1_PA3_DATA_FIFO_EOP_RD', 'PH_SC1_PA3_DATA_FIFO_RD',
'PH_SC1_PA3_DATA_FIFO_WE', 'PH_SC1_PA3_DEALLOC_4_0_RD',
'PH_SC1_PA3_EOPG_WE', 'PH_SC1_PA3_EOP_WE', 'PH_SC1_PA3_EVENT_WE',
'PH_SC1_PA3_FIFO_EMPTY', 'PH_SC1_PA3_FIFO_FULL',
'PH_SC1_PA3_FPOV_WE', 'PH_SC1_PA3_LPOV_WE', 'PH_SC1_PA3_NULL_WE',
'PH_SC1_PA4_DATA_FIFO_EOP_RD', 'PH_SC1_PA4_DATA_FIFO_RD',
'PH_SC1_PA4_DATA_FIFO_WE', 'PH_SC1_PA4_DEALLOC_4_0_RD',
'PH_SC1_PA4_EOPG_WE', 'PH_SC1_PA4_EOP_WE', 'PH_SC1_PA4_EVENT_WE',
'PH_SC1_PA4_FIFO_EMPTY', 'PH_SC1_PA4_FIFO_FULL',
'PH_SC1_PA4_FPOV_WE', 'PH_SC1_PA4_LPOV_WE', 'PH_SC1_PA4_NULL_WE',
'PH_SC1_PA5_DATA_FIFO_EOP_RD', 'PH_SC1_PA5_DATA_FIFO_RD',
'PH_SC1_PA5_DATA_FIFO_WE', 'PH_SC1_PA5_DEALLOC_4_0_RD',
'PH_SC1_PA5_EOPG_WE', 'PH_SC1_PA5_EOP_WE', 'PH_SC1_PA5_EVENT_WE',
'PH_SC1_PA5_FIFO_EMPTY', 'PH_SC1_PA5_FIFO_FULL',
'PH_SC1_PA5_FPOV_WE', 'PH_SC1_PA5_LPOV_WE', 'PH_SC1_PA5_NULL_WE',
'PH_SC1_PA6_DATA_FIFO_EOP_RD', 'PH_SC1_PA6_DATA_FIFO_RD',
'PH_SC1_PA6_DATA_FIFO_WE', 'PH_SC1_PA6_DEALLOC_4_0_RD',
'PH_SC1_PA6_EOPG_WE', 'PH_SC1_PA6_EOP_WE', 'PH_SC1_PA6_EVENT_WE',
'PH_SC1_PA6_FIFO_EMPTY', 'PH_SC1_PA6_FIFO_FULL',
'PH_SC1_PA6_FPOV_WE', 'PH_SC1_PA6_LPOV_WE', 'PH_SC1_PA6_NULL_WE',
'PH_SC1_PA7_DATA_FIFO_EOP_RD', 'PH_SC1_PA7_DATA_FIFO_RD',
'PH_SC1_PA7_DATA_FIFO_WE', 'PH_SC1_PA7_DEALLOC_4_0_RD',
'PH_SC1_PA7_EOPG_WE', 'PH_SC1_PA7_EOP_WE', 'PH_SC1_PA7_EVENT_WE',
'PH_SC1_PA7_FIFO_EMPTY', 'PH_SC1_PA7_FIFO_FULL',
'PH_SC1_PA7_FPOV_WE', 'PH_SC1_PA7_LPOV_WE', 'PH_SC1_PA7_NULL_WE',
'PH_SC1_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC1_SEND',
'PH_SC1_SRPS_WINDOW_VALID', 'PH_SC2_ARB_BUSY',
'PH_SC2_ARB_EOP_POP_SYNC_POP', 'PH_SC2_ARB_EVENT_SYNC_POP',
'PH_SC2_ARB_PA_BUSY_SOP', 'PH_SC2_ARB_STALLED_FROM_BELOW',
'PH_SC2_ARB_STARVED_FROM_ABOVE',
'PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC2_BUSY_CNT_NOT_ZERO',
'PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC2_CREDIT_AT_MAX',
'PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_SC2_EOP_SYNC_WINDOW', 'PH_SC2_GFX_PIPE0_TO_1_TRANSITION',
'PH_SC2_GFX_PIPE1_TO_0_TRANSITION',
'PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_SC2_PA0_DATA_FIFO_EOP_RD', 'PH_SC2_PA0_DATA_FIFO_RD',
'PH_SC2_PA0_DATA_FIFO_WE', 'PH_SC2_PA0_DEALLOC_4_0_RD',
'PH_SC2_PA0_EOPG_WE', 'PH_SC2_PA0_EOP_WE', 'PH_SC2_PA0_EVENT_WE',
'PH_SC2_PA0_FIFO_EMPTY', 'PH_SC2_PA0_FIFO_FULL',
'PH_SC2_PA0_FPOV_WE', 'PH_SC2_PA0_LPOV_WE', 'PH_SC2_PA0_NULL_WE',
'PH_SC2_PA1_DATA_FIFO_EOP_RD', 'PH_SC2_PA1_DATA_FIFO_RD',
'PH_SC2_PA1_DATA_FIFO_WE', 'PH_SC2_PA1_DEALLOC_4_0_RD',
'PH_SC2_PA1_EOPG_WE', 'PH_SC2_PA1_EOP_WE', 'PH_SC2_PA1_EVENT_WE',
'PH_SC2_PA1_FIFO_EMPTY', 'PH_SC2_PA1_FIFO_FULL',
'PH_SC2_PA1_FPOV_WE', 'PH_SC2_PA1_LPOV_WE', 'PH_SC2_PA1_NULL_WE',
'PH_SC2_PA2_DATA_FIFO_EOP_RD', 'PH_SC2_PA2_DATA_FIFO_RD',
'PH_SC2_PA2_DATA_FIFO_WE', 'PH_SC2_PA2_DEALLOC_4_0_RD',
'PH_SC2_PA2_EOPG_WE', 'PH_SC2_PA2_EOP_WE', 'PH_SC2_PA2_EVENT_WE',
'PH_SC2_PA2_FIFO_EMPTY', 'PH_SC2_PA2_FIFO_FULL',
'PH_SC2_PA2_FPOV_WE', 'PH_SC2_PA2_LPOV_WE', 'PH_SC2_PA2_NULL_WE',
'PH_SC2_PA3_DATA_FIFO_EOP_RD', 'PH_SC2_PA3_DATA_FIFO_RD',
'PH_SC2_PA3_DATA_FIFO_WE', 'PH_SC2_PA3_DEALLOC_4_0_RD',
'PH_SC2_PA3_EOPG_WE', 'PH_SC2_PA3_EOP_WE', 'PH_SC2_PA3_EVENT_WE',
'PH_SC2_PA3_FIFO_EMPTY', 'PH_SC2_PA3_FIFO_FULL',
'PH_SC2_PA3_FPOV_WE', 'PH_SC2_PA3_LPOV_WE', 'PH_SC2_PA3_NULL_WE',
'PH_SC2_PA4_DATA_FIFO_EOP_RD', 'PH_SC2_PA4_DATA_FIFO_RD',
'PH_SC2_PA4_DATA_FIFO_WE', 'PH_SC2_PA4_DEALLOC_4_0_RD',
'PH_SC2_PA4_EOPG_WE', 'PH_SC2_PA4_EOP_WE', 'PH_SC2_PA4_EVENT_WE',
'PH_SC2_PA4_FIFO_EMPTY', 'PH_SC2_PA4_FIFO_FULL',
'PH_SC2_PA4_FPOV_WE', 'PH_SC2_PA4_LPOV_WE', 'PH_SC2_PA4_NULL_WE',
'PH_SC2_PA5_DATA_FIFO_EOP_RD', 'PH_SC2_PA5_DATA_FIFO_RD',
'PH_SC2_PA5_DATA_FIFO_WE', 'PH_SC2_PA5_DEALLOC_4_0_RD',
'PH_SC2_PA5_EOPG_WE', 'PH_SC2_PA5_EOP_WE', 'PH_SC2_PA5_EVENT_WE',
'PH_SC2_PA5_FIFO_EMPTY', 'PH_SC2_PA5_FIFO_FULL',
'PH_SC2_PA5_FPOV_WE', 'PH_SC2_PA5_LPOV_WE', 'PH_SC2_PA5_NULL_WE',
'PH_SC2_PA6_DATA_FIFO_EOP_RD', 'PH_SC2_PA6_DATA_FIFO_RD',
'PH_SC2_PA6_DATA_FIFO_WE', 'PH_SC2_PA6_DEALLOC_4_0_RD',
'PH_SC2_PA6_EOPG_WE', 'PH_SC2_PA6_EOP_WE', 'PH_SC2_PA6_EVENT_WE',
'PH_SC2_PA6_FIFO_EMPTY', 'PH_SC2_PA6_FIFO_FULL',
'PH_SC2_PA6_FPOV_WE', 'PH_SC2_PA6_LPOV_WE', 'PH_SC2_PA6_NULL_WE',
'PH_SC2_PA7_DATA_FIFO_EOP_RD', 'PH_SC2_PA7_DATA_FIFO_RD',
'PH_SC2_PA7_DATA_FIFO_WE', 'PH_SC2_PA7_DEALLOC_4_0_RD',
'PH_SC2_PA7_EOPG_WE', 'PH_SC2_PA7_EOP_WE', 'PH_SC2_PA7_EVENT_WE',
'PH_SC2_PA7_FIFO_EMPTY', 'PH_SC2_PA7_FIFO_FULL',
'PH_SC2_PA7_FPOV_WE', 'PH_SC2_PA7_LPOV_WE', 'PH_SC2_PA7_NULL_WE',
'PH_SC2_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC2_SEND',
'PH_SC2_SRPS_WINDOW_VALID', 'PH_SC3_ARB_BUSY',
'PH_SC3_ARB_EOP_POP_SYNC_POP', 'PH_SC3_ARB_EVENT_SYNC_POP',
'PH_SC3_ARB_PA_BUSY_SOP', 'PH_SC3_ARB_STALLED_FROM_BELOW',
'PH_SC3_ARB_STARVED_FROM_ABOVE',
'PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC3_BUSY_CNT_NOT_ZERO',
'PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC3_CREDIT_AT_MAX',
'PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_SC3_EOP_SYNC_WINDOW', 'PH_SC3_GFX_PIPE0_TO_1_TRANSITION',
'PH_SC3_GFX_PIPE1_TO_0_TRANSITION',
'PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_SC3_PA0_DATA_FIFO_EOP_RD', 'PH_SC3_PA0_DATA_FIFO_RD',
'PH_SC3_PA0_DATA_FIFO_WE', 'PH_SC3_PA0_DEALLOC_4_0_RD',
'PH_SC3_PA0_EOPG_WE', 'PH_SC3_PA0_EOP_WE', 'PH_SC3_PA0_EVENT_WE',
'PH_SC3_PA0_FIFO_EMPTY', 'PH_SC3_PA0_FIFO_FULL',
'PH_SC3_PA0_FPOV_WE', 'PH_SC3_PA0_LPOV_WE', 'PH_SC3_PA0_NULL_WE',
'PH_SC3_PA1_DATA_FIFO_EOP_RD', 'PH_SC3_PA1_DATA_FIFO_RD',
'PH_SC3_PA1_DATA_FIFO_WE', 'PH_SC3_PA1_DEALLOC_4_0_RD',
'PH_SC3_PA1_EOPG_WE', 'PH_SC3_PA1_EOP_WE', 'PH_SC3_PA1_EVENT_WE',
'PH_SC3_PA1_FIFO_EMPTY', 'PH_SC3_PA1_FIFO_FULL',
'PH_SC3_PA1_FPOV_WE', 'PH_SC3_PA1_LPOV_WE', 'PH_SC3_PA1_NULL_WE',
'PH_SC3_PA2_DATA_FIFO_EOP_RD', 'PH_SC3_PA2_DATA_FIFO_RD',
'PH_SC3_PA2_DATA_FIFO_WE', 'PH_SC3_PA2_DEALLOC_4_0_RD',
'PH_SC3_PA2_EOPG_WE', 'PH_SC3_PA2_EOP_WE', 'PH_SC3_PA2_EVENT_WE',
'PH_SC3_PA2_FIFO_EMPTY', 'PH_SC3_PA2_FIFO_FULL',
'PH_SC3_PA2_FPOV_WE', 'PH_SC3_PA2_LPOV_WE', 'PH_SC3_PA2_NULL_WE',
'PH_SC3_PA3_DATA_FIFO_EOP_RD', 'PH_SC3_PA3_DATA_FIFO_RD',
'PH_SC3_PA3_DATA_FIFO_WE', 'PH_SC3_PA3_DEALLOC_4_0_RD',
'PH_SC3_PA3_EOPG_WE', 'PH_SC3_PA3_EOP_WE', 'PH_SC3_PA3_EVENT_WE',
'PH_SC3_PA3_FIFO_EMPTY', 'PH_SC3_PA3_FIFO_FULL',
'PH_SC3_PA3_FPOV_WE', 'PH_SC3_PA3_LPOV_WE', 'PH_SC3_PA3_NULL_WE',
'PH_SC3_PA4_DATA_FIFO_EOP_RD', 'PH_SC3_PA4_DATA_FIFO_RD',
'PH_SC3_PA4_DATA_FIFO_WE', 'PH_SC3_PA4_DEALLOC_4_0_RD',
'PH_SC3_PA4_EOPG_WE', 'PH_SC3_PA4_EOP_WE', 'PH_SC3_PA4_EVENT_WE',
'PH_SC3_PA4_FIFO_EMPTY', 'PH_SC3_PA4_FIFO_FULL',
'PH_SC3_PA4_FPOV_WE', 'PH_SC3_PA4_LPOV_WE', 'PH_SC3_PA4_NULL_WE',
'PH_SC3_PA5_DATA_FIFO_EOP_RD', 'PH_SC3_PA5_DATA_FIFO_RD',
'PH_SC3_PA5_DATA_FIFO_WE', 'PH_SC3_PA5_DEALLOC_4_0_RD',
'PH_SC3_PA5_EOPG_WE', 'PH_SC3_PA5_EOP_WE', 'PH_SC3_PA5_EVENT_WE',
'PH_SC3_PA5_FIFO_EMPTY', 'PH_SC3_PA5_FIFO_FULL',
'PH_SC3_PA5_FPOV_WE', 'PH_SC3_PA5_LPOV_WE', 'PH_SC3_PA5_NULL_WE',
'PH_SC3_PA6_DATA_FIFO_EOP_RD', 'PH_SC3_PA6_DATA_FIFO_RD',
'PH_SC3_PA6_DATA_FIFO_WE', 'PH_SC3_PA6_DEALLOC_4_0_RD',
'PH_SC3_PA6_EOPG_WE', 'PH_SC3_PA6_EOP_WE', 'PH_SC3_PA6_EVENT_WE',
'PH_SC3_PA6_FIFO_EMPTY', 'PH_SC3_PA6_FIFO_FULL',
'PH_SC3_PA6_FPOV_WE', 'PH_SC3_PA6_LPOV_WE', 'PH_SC3_PA6_NULL_WE',
'PH_SC3_PA7_DATA_FIFO_EOP_RD', 'PH_SC3_PA7_DATA_FIFO_RD',
'PH_SC3_PA7_DATA_FIFO_WE', 'PH_SC3_PA7_DEALLOC_4_0_RD',
'PH_SC3_PA7_EOPG_WE', 'PH_SC3_PA7_EOP_WE', 'PH_SC3_PA7_EVENT_WE',
'PH_SC3_PA7_FIFO_EMPTY', 'PH_SC3_PA7_FIFO_FULL',
'PH_SC3_PA7_FPOV_WE', 'PH_SC3_PA7_LPOV_WE', 'PH_SC3_PA7_NULL_WE',
'PH_SC3_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC3_SEND',
'PH_SC3_SRPS_WINDOW_VALID', 'PH_SC4_ARB_BUSY',
'PH_SC4_ARB_EOP_POP_SYNC_POP', 'PH_SC4_ARB_EVENT_SYNC_POP',
'PH_SC4_ARB_PA_BUSY_SOP', 'PH_SC4_ARB_STALLED_FROM_BELOW',
'PH_SC4_ARB_STARVED_FROM_ABOVE',
'PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC4_BUSY_CNT_NOT_ZERO',
'PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC4_CREDIT_AT_MAX',
'PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_SC4_EOP_SYNC_WINDOW', 'PH_SC4_GFX_PIPE0_TO_1_TRANSITION',
'PH_SC4_GFX_PIPE1_TO_0_TRANSITION',
'PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_SC4_PA0_DATA_FIFO_EOP_RD', 'PH_SC4_PA0_DATA_FIFO_RD',
'PH_SC4_PA0_DATA_FIFO_WE', 'PH_SC4_PA0_DEALLOC_4_0_RD',
'PH_SC4_PA0_EOPG_WE', 'PH_SC4_PA0_EOP_WE', 'PH_SC4_PA0_EVENT_WE',
'PH_SC4_PA0_FIFO_EMPTY', 'PH_SC4_PA0_FIFO_FULL',
'PH_SC4_PA0_FPOV_WE', 'PH_SC4_PA0_LPOV_WE', 'PH_SC4_PA0_NULL_WE',
'PH_SC4_PA1_DATA_FIFO_EOP_RD', 'PH_SC4_PA1_DATA_FIFO_RD',
'PH_SC4_PA1_DATA_FIFO_WE', 'PH_SC4_PA1_DEALLOC_4_0_RD',
'PH_SC4_PA1_EOPG_WE', 'PH_SC4_PA1_EOP_WE', 'PH_SC4_PA1_EVENT_WE',
'PH_SC4_PA1_FIFO_EMPTY', 'PH_SC4_PA1_FIFO_FULL',
'PH_SC4_PA1_FPOV_WE', 'PH_SC4_PA1_LPOV_WE', 'PH_SC4_PA1_NULL_WE',
'PH_SC4_PA2_DATA_FIFO_EOP_RD', 'PH_SC4_PA2_DATA_FIFO_RD',
'PH_SC4_PA2_DATA_FIFO_WE', 'PH_SC4_PA2_DEALLOC_4_0_RD',
'PH_SC4_PA2_EOPG_WE', 'PH_SC4_PA2_EOP_WE', 'PH_SC4_PA2_EVENT_WE',
'PH_SC4_PA2_FIFO_EMPTY', 'PH_SC4_PA2_FIFO_FULL',
'PH_SC4_PA2_FPOV_WE', 'PH_SC4_PA2_LPOV_WE', 'PH_SC4_PA2_NULL_WE',
'PH_SC4_PA3_DATA_FIFO_EOP_RD', 'PH_SC4_PA3_DATA_FIFO_RD',
'PH_SC4_PA3_DATA_FIFO_WE', 'PH_SC4_PA3_DEALLOC_4_0_RD',
'PH_SC4_PA3_EOPG_WE', 'PH_SC4_PA3_EOP_WE', 'PH_SC4_PA3_EVENT_WE',
'PH_SC4_PA3_FIFO_EMPTY', 'PH_SC4_PA3_FIFO_FULL',
'PH_SC4_PA3_FPOV_WE', 'PH_SC4_PA3_LPOV_WE', 'PH_SC4_PA3_NULL_WE',
'PH_SC4_PA4_DATA_FIFO_EOP_RD', 'PH_SC4_PA4_DATA_FIFO_RD',
'PH_SC4_PA4_DATA_FIFO_WE', 'PH_SC4_PA4_DEALLOC_4_0_RD',
'PH_SC4_PA4_EOPG_WE', 'PH_SC4_PA4_EOP_WE', 'PH_SC4_PA4_EVENT_WE',
'PH_SC4_PA4_FIFO_EMPTY', 'PH_SC4_PA4_FIFO_FULL',
'PH_SC4_PA4_FPOV_WE', 'PH_SC4_PA4_LPOV_WE', 'PH_SC4_PA4_NULL_WE',
'PH_SC4_PA5_DATA_FIFO_EOP_RD', 'PH_SC4_PA5_DATA_FIFO_RD',
'PH_SC4_PA5_DATA_FIFO_WE', 'PH_SC4_PA5_DEALLOC_4_0_RD',
'PH_SC4_PA5_EOPG_WE', 'PH_SC4_PA5_EOP_WE', 'PH_SC4_PA5_EVENT_WE',
'PH_SC4_PA5_FIFO_EMPTY', 'PH_SC4_PA5_FIFO_FULL',
'PH_SC4_PA5_FPOV_WE', 'PH_SC4_PA5_LPOV_WE', 'PH_SC4_PA5_NULL_WE',
'PH_SC4_PA6_DATA_FIFO_EOP_RD', 'PH_SC4_PA6_DATA_FIFO_RD',
'PH_SC4_PA6_DATA_FIFO_WE', 'PH_SC4_PA6_DEALLOC_4_0_RD',
'PH_SC4_PA6_EOPG_WE', 'PH_SC4_PA6_EOP_WE', 'PH_SC4_PA6_EVENT_WE',
'PH_SC4_PA6_FIFO_EMPTY', 'PH_SC4_PA6_FIFO_FULL',
'PH_SC4_PA6_FPOV_WE', 'PH_SC4_PA6_LPOV_WE', 'PH_SC4_PA6_NULL_WE',
'PH_SC4_PA7_DATA_FIFO_EOP_RD', 'PH_SC4_PA7_DATA_FIFO_RD',
'PH_SC4_PA7_DATA_FIFO_WE', 'PH_SC4_PA7_DEALLOC_4_0_RD',
'PH_SC4_PA7_EOPG_WE', 'PH_SC4_PA7_EOP_WE', 'PH_SC4_PA7_EVENT_WE',
'PH_SC4_PA7_FIFO_EMPTY', 'PH_SC4_PA7_FIFO_FULL',
'PH_SC4_PA7_FPOV_WE', 'PH_SC4_PA7_LPOV_WE', 'PH_SC4_PA7_NULL_WE',
'PH_SC4_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC4_SEND',
'PH_SC4_SRPS_WINDOW_VALID', 'PH_SC5_ARB_BUSY',
'PH_SC5_ARB_EOP_POP_SYNC_POP', 'PH_SC5_ARB_EVENT_SYNC_POP',
'PH_SC5_ARB_PA_BUSY_SOP', 'PH_SC5_ARB_STALLED_FROM_BELOW',
'PH_SC5_ARB_STARVED_FROM_ABOVE',
'PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC5_BUSY_CNT_NOT_ZERO',
'PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC5_CREDIT_AT_MAX',
'PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_SC5_EOP_SYNC_WINDOW', 'PH_SC5_GFX_PIPE0_TO_1_TRANSITION',
'PH_SC5_GFX_PIPE1_TO_0_TRANSITION',
'PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_SC5_PA0_DATA_FIFO_EOP_RD', 'PH_SC5_PA0_DATA_FIFO_RD',
'PH_SC5_PA0_DATA_FIFO_WE', 'PH_SC5_PA0_DEALLOC_4_0_RD',
'PH_SC5_PA0_EOPG_WE', 'PH_SC5_PA0_EOP_WE', 'PH_SC5_PA0_EVENT_WE',
'PH_SC5_PA0_FIFO_EMPTY', 'PH_SC5_PA0_FIFO_FULL',
'PH_SC5_PA0_FPOV_WE', 'PH_SC5_PA0_LPOV_WE', 'PH_SC5_PA0_NULL_WE',
'PH_SC5_PA1_DATA_FIFO_EOP_RD', 'PH_SC5_PA1_DATA_FIFO_RD',
'PH_SC5_PA1_DATA_FIFO_WE', 'PH_SC5_PA1_DEALLOC_4_0_RD',
'PH_SC5_PA1_EOPG_WE', 'PH_SC5_PA1_EOP_WE', 'PH_SC5_PA1_EVENT_WE',
'PH_SC5_PA1_FIFO_EMPTY', 'PH_SC5_PA1_FIFO_FULL',
'PH_SC5_PA1_FPOV_WE', 'PH_SC5_PA1_LPOV_WE', 'PH_SC5_PA1_NULL_WE',
'PH_SC5_PA2_DATA_FIFO_EOP_RD', 'PH_SC5_PA2_DATA_FIFO_RD',
'PH_SC5_PA2_DATA_FIFO_WE', 'PH_SC5_PA2_DEALLOC_4_0_RD',
'PH_SC5_PA2_EOPG_WE', 'PH_SC5_PA2_EOP_WE', 'PH_SC5_PA2_EVENT_WE',
'PH_SC5_PA2_FIFO_EMPTY', 'PH_SC5_PA2_FIFO_FULL',
'PH_SC5_PA2_FPOV_WE', 'PH_SC5_PA2_LPOV_WE', 'PH_SC5_PA2_NULL_WE',
'PH_SC5_PA3_DATA_FIFO_EOP_RD', 'PH_SC5_PA3_DATA_FIFO_RD',
'PH_SC5_PA3_DATA_FIFO_WE', 'PH_SC5_PA3_DEALLOC_4_0_RD',
'PH_SC5_PA3_EOPG_WE', 'PH_SC5_PA3_EOP_WE', 'PH_SC5_PA3_EVENT_WE',
'PH_SC5_PA3_FIFO_EMPTY', 'PH_SC5_PA3_FIFO_FULL',
'PH_SC5_PA3_FPOV_WE', 'PH_SC5_PA3_LPOV_WE', 'PH_SC5_PA3_NULL_WE',
'PH_SC5_PA4_DATA_FIFO_EOP_RD', 'PH_SC5_PA4_DATA_FIFO_RD',
'PH_SC5_PA4_DATA_FIFO_WE', 'PH_SC5_PA4_DEALLOC_4_0_RD',
'PH_SC5_PA4_EOPG_WE', 'PH_SC5_PA4_EOP_WE', 'PH_SC5_PA4_EVENT_WE',
'PH_SC5_PA4_FIFO_EMPTY', 'PH_SC5_PA4_FIFO_FULL',
'PH_SC5_PA4_FPOV_WE', 'PH_SC5_PA4_LPOV_WE', 'PH_SC5_PA4_NULL_WE',
'PH_SC5_PA5_DATA_FIFO_EOP_RD', 'PH_SC5_PA5_DATA_FIFO_RD',
'PH_SC5_PA5_DATA_FIFO_WE', 'PH_SC5_PA5_DEALLOC_4_0_RD',
'PH_SC5_PA5_EOPG_WE', 'PH_SC5_PA5_EOP_WE', 'PH_SC5_PA5_EVENT_WE',
'PH_SC5_PA5_FIFO_EMPTY', 'PH_SC5_PA5_FIFO_FULL',
'PH_SC5_PA5_FPOV_WE', 'PH_SC5_PA5_LPOV_WE', 'PH_SC5_PA5_NULL_WE',
'PH_SC5_PA6_DATA_FIFO_EOP_RD', 'PH_SC5_PA6_DATA_FIFO_RD',
'PH_SC5_PA6_DATA_FIFO_WE', 'PH_SC5_PA6_DEALLOC_4_0_RD',
'PH_SC5_PA6_EOPG_WE', 'PH_SC5_PA6_EOP_WE', 'PH_SC5_PA6_EVENT_WE',
'PH_SC5_PA6_FIFO_EMPTY', 'PH_SC5_PA6_FIFO_FULL',
'PH_SC5_PA6_FPOV_WE', 'PH_SC5_PA6_LPOV_WE', 'PH_SC5_PA6_NULL_WE',
'PH_SC5_PA7_DATA_FIFO_EOP_RD', 'PH_SC5_PA7_DATA_FIFO_RD',
'PH_SC5_PA7_DATA_FIFO_WE', 'PH_SC5_PA7_DEALLOC_4_0_RD',
'PH_SC5_PA7_EOPG_WE', 'PH_SC5_PA7_EOP_WE', 'PH_SC5_PA7_EVENT_WE',
'PH_SC5_PA7_FIFO_EMPTY', 'PH_SC5_PA7_FIFO_FULL',
'PH_SC5_PA7_FPOV_WE', 'PH_SC5_PA7_LPOV_WE', 'PH_SC5_PA7_NULL_WE',
'PH_SC5_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC5_SEND',
'PH_SC5_SRPS_WINDOW_VALID', 'PH_SC6_ARB_BUSY',
'PH_SC6_ARB_EOP_POP_SYNC_POP', 'PH_SC6_ARB_EVENT_SYNC_POP',
'PH_SC6_ARB_PA_BUSY_SOP', 'PH_SC6_ARB_STALLED_FROM_BELOW',
'PH_SC6_ARB_STARVED_FROM_ABOVE',
'PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC6_BUSY_CNT_NOT_ZERO',
'PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC6_CREDIT_AT_MAX',
'PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_SC6_EOP_SYNC_WINDOW', 'PH_SC6_GFX_PIPE0_TO_1_TRANSITION',
'PH_SC6_GFX_PIPE1_TO_0_TRANSITION',
'PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_SC6_PA0_DATA_FIFO_EOP_RD', 'PH_SC6_PA0_DATA_FIFO_RD',
'PH_SC6_PA0_DATA_FIFO_WE', 'PH_SC6_PA0_DEALLOC_4_0_RD',
'PH_SC6_PA0_EOPG_WE', 'PH_SC6_PA0_EOP_WE', 'PH_SC6_PA0_EVENT_WE',
'PH_SC6_PA0_FIFO_EMPTY', 'PH_SC6_PA0_FIFO_FULL',
'PH_SC6_PA0_FPOV_WE', 'PH_SC6_PA0_LPOV_WE', 'PH_SC6_PA0_NULL_WE',
'PH_SC6_PA1_DATA_FIFO_EOP_RD', 'PH_SC6_PA1_DATA_FIFO_RD',
'PH_SC6_PA1_DATA_FIFO_WE', 'PH_SC6_PA1_DEALLOC_4_0_RD',
'PH_SC6_PA1_EOPG_WE', 'PH_SC6_PA1_EOP_WE', 'PH_SC6_PA1_EVENT_WE',
'PH_SC6_PA1_FIFO_EMPTY', 'PH_SC6_PA1_FIFO_FULL',
'PH_SC6_PA1_FPOV_WE', 'PH_SC6_PA1_LPOV_WE', 'PH_SC6_PA1_NULL_WE',
'PH_SC6_PA2_DATA_FIFO_EOP_RD', 'PH_SC6_PA2_DATA_FIFO_RD',
'PH_SC6_PA2_DATA_FIFO_WE', 'PH_SC6_PA2_DEALLOC_4_0_RD',
'PH_SC6_PA2_EOPG_WE', 'PH_SC6_PA2_EOP_WE', 'PH_SC6_PA2_EVENT_WE',
'PH_SC6_PA2_FIFO_EMPTY', 'PH_SC6_PA2_FIFO_FULL',
'PH_SC6_PA2_FPOV_WE', 'PH_SC6_PA2_LPOV_WE', 'PH_SC6_PA2_NULL_WE',
'PH_SC6_PA3_DATA_FIFO_EOP_RD', 'PH_SC6_PA3_DATA_FIFO_RD',
'PH_SC6_PA3_DATA_FIFO_WE', 'PH_SC6_PA3_DEALLOC_4_0_RD',
'PH_SC6_PA3_EOPG_WE', 'PH_SC6_PA3_EOP_WE', 'PH_SC6_PA3_EVENT_WE',
'PH_SC6_PA3_FIFO_EMPTY', 'PH_SC6_PA3_FIFO_FULL',
'PH_SC6_PA3_FPOV_WE', 'PH_SC6_PA3_LPOV_WE', 'PH_SC6_PA3_NULL_WE',
'PH_SC6_PA4_DATA_FIFO_EOP_RD', 'PH_SC6_PA4_DATA_FIFO_RD',
'PH_SC6_PA4_DATA_FIFO_WE', 'PH_SC6_PA4_DEALLOC_4_0_RD',
'PH_SC6_PA4_EOPG_WE', 'PH_SC6_PA4_EOP_WE', 'PH_SC6_PA4_EVENT_WE',
'PH_SC6_PA4_FIFO_EMPTY', 'PH_SC6_PA4_FIFO_FULL',
'PH_SC6_PA4_FPOV_WE', 'PH_SC6_PA4_LPOV_WE', 'PH_SC6_PA4_NULL_WE',
'PH_SC6_PA5_DATA_FIFO_EOP_RD', 'PH_SC6_PA5_DATA_FIFO_RD',
'PH_SC6_PA5_DATA_FIFO_WE', 'PH_SC6_PA5_DEALLOC_4_0_RD',
'PH_SC6_PA5_EOPG_WE', 'PH_SC6_PA5_EOP_WE', 'PH_SC6_PA5_EVENT_WE',
'PH_SC6_PA5_FIFO_EMPTY', 'PH_SC6_PA5_FIFO_FULL',
'PH_SC6_PA5_FPOV_WE', 'PH_SC6_PA5_LPOV_WE', 'PH_SC6_PA5_NULL_WE',
'PH_SC6_PA6_DATA_FIFO_EOP_RD', 'PH_SC6_PA6_DATA_FIFO_RD',
'PH_SC6_PA6_DATA_FIFO_WE', 'PH_SC6_PA6_DEALLOC_4_0_RD',
'PH_SC6_PA6_EOPG_WE', 'PH_SC6_PA6_EOP_WE', 'PH_SC6_PA6_EVENT_WE',
'PH_SC6_PA6_FIFO_EMPTY', 'PH_SC6_PA6_FIFO_FULL',
'PH_SC6_PA6_FPOV_WE', 'PH_SC6_PA6_LPOV_WE', 'PH_SC6_PA6_NULL_WE',
'PH_SC6_PA7_DATA_FIFO_EOP_RD', 'PH_SC6_PA7_DATA_FIFO_RD',
'PH_SC6_PA7_DATA_FIFO_WE', 'PH_SC6_PA7_DEALLOC_4_0_RD',
'PH_SC6_PA7_EOPG_WE', 'PH_SC6_PA7_EOP_WE', 'PH_SC6_PA7_EVENT_WE',
'PH_SC6_PA7_FIFO_EMPTY', 'PH_SC6_PA7_FIFO_FULL',
'PH_SC6_PA7_FPOV_WE', 'PH_SC6_PA7_LPOV_WE', 'PH_SC6_PA7_NULL_WE',
'PH_SC6_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC6_SEND',
'PH_SC6_SRPS_WINDOW_VALID', 'PH_SC7_ARB_BUSY',
'PH_SC7_ARB_EOP_POP_SYNC_POP', 'PH_SC7_ARB_EVENT_SYNC_POP',
'PH_SC7_ARB_PA_BUSY_SOP', 'PH_SC7_ARB_STALLED_FROM_BELOW',
'PH_SC7_ARB_STARVED_FROM_ABOVE',
'PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC7_BUSY_CNT_NOT_ZERO',
'PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC7_CREDIT_AT_MAX',
'PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_SC7_EOP_SYNC_WINDOW', 'PH_SC7_GFX_PIPE0_TO_1_TRANSITION',
'PH_SC7_GFX_PIPE1_TO_0_TRANSITION',
'PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_SC7_PA0_DATA_FIFO_EOP_RD', 'PH_SC7_PA0_DATA_FIFO_RD',
'PH_SC7_PA0_DATA_FIFO_WE', 'PH_SC7_PA0_DEALLOC_4_0_RD',
'PH_SC7_PA0_EOPG_WE', 'PH_SC7_PA0_EOP_WE', 'PH_SC7_PA0_EVENT_WE',
'PH_SC7_PA0_FIFO_EMPTY', 'PH_SC7_PA0_FIFO_FULL',
'PH_SC7_PA0_FPOV_WE', 'PH_SC7_PA0_LPOV_WE', 'PH_SC7_PA0_NULL_WE',
'PH_SC7_PA1_DATA_FIFO_EOP_RD', 'PH_SC7_PA1_DATA_FIFO_RD',
'PH_SC7_PA1_DATA_FIFO_WE', 'PH_SC7_PA1_DEALLOC_4_0_RD',
'PH_SC7_PA1_EOPG_WE', 'PH_SC7_PA1_EOP_WE', 'PH_SC7_PA1_EVENT_WE',
'PH_SC7_PA1_FIFO_EMPTY', 'PH_SC7_PA1_FIFO_FULL',
'PH_SC7_PA1_FPOV_WE', 'PH_SC7_PA1_LPOV_WE', 'PH_SC7_PA1_NULL_WE',
'PH_SC7_PA2_DATA_FIFO_EOP_RD', 'PH_SC7_PA2_DATA_FIFO_RD',
'PH_SC7_PA2_DATA_FIFO_WE', 'PH_SC7_PA2_DEALLOC_4_0_RD',
'PH_SC7_PA2_EOPG_WE', 'PH_SC7_PA2_EOP_WE', 'PH_SC7_PA2_EVENT_WE',
'PH_SC7_PA2_FIFO_EMPTY', 'PH_SC7_PA2_FIFO_FULL',
'PH_SC7_PA2_FPOV_WE', 'PH_SC7_PA2_LPOV_WE', 'PH_SC7_PA2_NULL_WE',
'PH_SC7_PA3_DATA_FIFO_EOP_RD', 'PH_SC7_PA3_DATA_FIFO_RD',
'PH_SC7_PA3_DATA_FIFO_WE', 'PH_SC7_PA3_DEALLOC_4_0_RD',
'PH_SC7_PA3_EOPG_WE', 'PH_SC7_PA3_EOP_WE', 'PH_SC7_PA3_EVENT_WE',
'PH_SC7_PA3_FIFO_EMPTY', 'PH_SC7_PA3_FIFO_FULL',
'PH_SC7_PA3_FPOV_WE', 'PH_SC7_PA3_LPOV_WE', 'PH_SC7_PA3_NULL_WE',
'PH_SC7_PA4_DATA_FIFO_EOP_RD', 'PH_SC7_PA4_DATA_FIFO_RD',
'PH_SC7_PA4_DATA_FIFO_WE', 'PH_SC7_PA4_DEALLOC_4_0_RD',
'PH_SC7_PA4_EOPG_WE', 'PH_SC7_PA4_EOP_WE', 'PH_SC7_PA4_EVENT_WE',
'PH_SC7_PA4_FIFO_EMPTY', 'PH_SC7_PA4_FIFO_FULL',
'PH_SC7_PA4_FPOV_WE', 'PH_SC7_PA4_LPOV_WE', 'PH_SC7_PA4_NULL_WE',
'PH_SC7_PA5_DATA_FIFO_EOP_RD', 'PH_SC7_PA5_DATA_FIFO_RD',
'PH_SC7_PA5_DATA_FIFO_WE', 'PH_SC7_PA5_DEALLOC_4_0_RD',
'PH_SC7_PA5_EOPG_WE', 'PH_SC7_PA5_EOP_WE', 'PH_SC7_PA5_EVENT_WE',
'PH_SC7_PA5_FIFO_EMPTY', 'PH_SC7_PA5_FIFO_FULL',
'PH_SC7_PA5_FPOV_WE', 'PH_SC7_PA5_LPOV_WE', 'PH_SC7_PA5_NULL_WE',
'PH_SC7_PA6_DATA_FIFO_EOP_RD', 'PH_SC7_PA6_DATA_FIFO_RD',
'PH_SC7_PA6_DATA_FIFO_WE', 'PH_SC7_PA6_DEALLOC_4_0_RD',
'PH_SC7_PA6_EOPG_WE', 'PH_SC7_PA6_EOP_WE', 'PH_SC7_PA6_EVENT_WE',
'PH_SC7_PA6_FIFO_EMPTY', 'PH_SC7_PA6_FIFO_FULL',
'PH_SC7_PA6_FPOV_WE', 'PH_SC7_PA6_LPOV_WE', 'PH_SC7_PA6_NULL_WE',
'PH_SC7_PA7_DATA_FIFO_EOP_RD', 'PH_SC7_PA7_DATA_FIFO_RD',
'PH_SC7_PA7_DATA_FIFO_WE', 'PH_SC7_PA7_DEALLOC_4_0_RD',
'PH_SC7_PA7_EOPG_WE', 'PH_SC7_PA7_EOP_WE', 'PH_SC7_PA7_EVENT_WE',
'PH_SC7_PA7_FIFO_EMPTY', 'PH_SC7_PA7_FIFO_FULL',
'PH_SC7_PA7_FPOV_WE', 'PH_SC7_PA7_LPOV_WE', 'PH_SC7_PA7_NULL_WE',
'PH_SC7_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC7_SEND',
'PH_SC7_SRPS_WINDOW_VALID', 'PIPELINESTAT_START',
'PIPELINESTAT_STOP', 'PIPE_ALIGNED', 'PIPE_ALIGNED_SURF',
'PIPE_CONFIG', 'PIPE_ID0', 'PIPE_ID1', 'PIPE_ID2', 'PIPE_ID3',
'PIPE_INTERLEAVE', 'PIPE_INTERLEAVE_1KB', 'PIPE_INTERLEAVE_256B',
'PIPE_INTERLEAVE_512B', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF',
'PIPE_PIXEL_RATE_PLL_SOURCE',
'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL',
'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE',
'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL',
'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIPE_UNALIGNED_SURF',
'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1',
'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE', 'PIXEL_DEPTH_10BPC',
'PIXEL_DEPTH_8BPC', 'PIXEL_PIPE_OCCLUSION_COUNT_0',
'PIXEL_PIPE_OCCLUSION_COUNT_1', 'PIXEL_PIPE_OCCLUSION_COUNT_2',
'PIXEL_PIPE_OCCLUSION_COUNT_3', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0',
'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1',
'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0',
'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL',
'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET',
'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS',
'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS',
'PIX_DYNAMIC_EXPANSION', 'PIX_EXPAND_MODE', 'PIX_ZERO_EXPANSION',
'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE',
'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM_ASSERT_RESET',
'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', 'POINTLIST',
'POST_CLAMP_TF0', 'POST_CLAMP_TF1', 'POWER_STATE_ENUM',
'POWER_STATE_ENUM_DS', 'POWER_STATE_ENUM_LS',
'POWER_STATE_ENUM_ON', 'POWER_STATE_ENUM_SD', 'PRE_CLAMP_TF0',
'PRE_CLAMP_TF1', 'PROG_SEQ', 'PSLC_ASAP', 'PSLC_AUTO',
'PSLC_COUNTDOWN', 'PSLC_ON_HANG_ONLY', 'PS_DONE',
'PS_PARTIAL_FLUSH', 'PTE_ROW_HEIGHT_LINEAR',
'PTE_ROW_HEIGHT_LINEAR_1024L', 'PTE_ROW_HEIGHT_LINEAR_128L',
'PTE_ROW_HEIGHT_LINEAR_16L', 'PTE_ROW_HEIGHT_LINEAR_256L',
'PTE_ROW_HEIGHT_LINEAR_32L', 'PTE_ROW_HEIGHT_LINEAR_512L',
'PTE_ROW_HEIGHT_LINEAR_64L', 'PTE_ROW_HEIGHT_LINEAR_8L',
'PerfCounter_Vals', 'PipeConfig', 'PipeInterleaveSize',
'PipeTiling', 'PixelPipeCounterId', 'PixelPipeStride', 'PkrMap',
'PkrXsel', 'PkrXsel2', 'PkrYsel', 'QuadExportFormat',
'QuadExportFormatOld', 'RAMA_ACCESS', 'RAMB_ACCESS', 'RANGE_00',
'RANGE_FF', 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1',
'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3',
'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1',
'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3',
'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1',
'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3',
'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1',
'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3',
'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1',
'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3',
'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1',
'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3',
'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1',
'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1',
'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1',
'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3',
'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE',
'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE',
'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE',
'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE',
'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE',
'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE',
'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE',
'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0',
'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2',
'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0',
'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2',
'RASTER_CONFIG_SE_PAIR_MAP_3',
'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE',
'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE',
'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE',
'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE',
'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE',
'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE',
'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE',
'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE',
'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', 'RB_ALIGNED',
'RB_ALIGNED_META_SURF', 'RB_UNALIGNED_META_SURF',
'RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN',
'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS',
'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON',
'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN',
'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS',
'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON',
'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN',
'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS',
'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN',
'RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET',
'RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET',
'RDPCSTX_CNTL_RDPCS_TX_FIFO_EN',
'RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN',
'RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET',
'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE',
'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK',
'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE',
'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK',
'RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK',
'RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK',
'RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF',
'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL',
'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL',
'RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE',
'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE',
'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE',
'RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV',
'RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV',
'RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV',
'RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL',
'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT',
'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE',
'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH',
'RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE',
'RDPCS_CBUS_SOFT_RESET_DISABLE', 'RDPCS_CBUS_SOFT_RESET_ENABLE',
'RDPCS_DPALT_4LANE_TOGGLE_2LANE',
'RDPCS_DPALT_4LANE_TOGGLE_4LANE',
'RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE',
'RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE',
'RDPCS_DPALT_DISABLE_TOGGLE_DISABLE',
'RDPCS_DPALT_DISABLE_TOGGLE_ENABLE',
'RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE',
'RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE',
'RDPCS_EXT_REFCLK_DISABLE', 'RDPCS_EXT_REFCLK_ENABLE',
'RDPCS_EXT_REFCLK_EN_DISABLE', 'RDPCS_EXT_REFCLK_EN_ENABLE',
'RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY',
'RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3',
'RDPCS_MEM_POWER_CTRL_POFF_FOR_SD',
'RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD',
'RDPCS_MEM_PWR_DEEP_SLEEP', 'RDPCS_MEM_PWR_LIGHT_SLEEP',
'RDPCS_MEM_PWR_NO_FORCE', 'RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP',
'RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP',
'RDPCS_MEM_PWR_PWR_STATE_ON', 'RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN',
'RDPCS_MEM_PWR_SHUT_DOWN', 'RDPCS_PHY_CR_MUX_SEL_FOR_DC',
'RDPCS_PHY_CR_MUX_SEL_FOR_USB', 'RDPCS_PHY_CR_PARA_SEL_CR',
'RDPCS_PHY_CR_PARA_SEL_JTAG', 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8',
'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1',
'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16',
'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2',
'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3',
'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8',
'RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT',
'RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT', 'RDPCS_PHY_DP_TX_RATE',
'RDPCS_PHY_DP_TX_RATE_DIV2', 'RDPCS_PHY_DP_TX_RATE_DIV4',
'RDPCS_PHY_DP_TX_TERM_CTRL_40', 'RDPCS_PHY_DP_TX_TERM_CTRL_42',
'RDPCS_PHY_DP_TX_TERM_CTRL_44', 'RDPCS_PHY_DP_TX_TERM_CTRL_46',
'RDPCS_PHY_DP_TX_TERM_CTRL_48', 'RDPCS_PHY_DP_TX_TERM_CTRL_50',
'RDPCS_PHY_DP_TX_TERM_CTRL_52', 'RDPCS_PHY_DP_TX_TERM_CTRL_54',
'RDPCS_PHY_DP_TX_WIDTH_10', 'RDPCS_PHY_DP_TX_WIDTH_16',
'RDPCS_PHY_DP_TX_WIDTH_20', 'RDPCS_PHY_DP_TX_WIDTH_8',
'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0',
'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1',
'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2',
'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3',
'RDPCS_PHY_REF_RANGE_0', 'RDPCS_PHY_REF_RANGE_1',
'RDPCS_PHY_REF_RANGE_2', 'RDPCS_PHY_REF_RANGE_3',
'RDPCS_PHY_REF_RANGE_4', 'RDPCS_PHY_REF_RANGE_5',
'RDPCS_PHY_REF_RANGE_6', 'RDPCS_PHY_REF_RANGE_7',
'RDPCS_REG_FIFO_ERROR_MASK_DISABLE',
'RDPCS_REG_FIFO_ERROR_MASK_ENABLE', 'RDPCS_SRAMCLK_BYPASS',
'RDPCS_SRAMCLK_DISABLE', 'RDPCS_SRAMCLK_ENABLE',
'RDPCS_SRAMCLK_GATE_DISABLE', 'RDPCS_SRAMCLK_GATE_ENABLE',
'RDPCS_SRAMCLK_NOT_BYPASS', 'RDPCS_SRAM_EXT_LD_DONE',
'RDPCS_SRAM_EXT_LD_NOT_DONE', 'RDPCS_SRAM_INIT_DONE',
'RDPCS_SRAM_INIT_NOT_DONE', 'RDPCS_SRAM_SRAM_RESET_DISABLE',
'RDPCS_SYMCLK_DIV2_CLOCK_OFF', 'RDPCS_SYMCLK_DIV2_CLOCK_ON',
'RDPCS_SYMCLK_DIV2_DISABLE', 'RDPCS_SYMCLK_DIV2_ENABLE',
'RDPCS_SYMCLK_DIV2_GATE_DISABLE', 'RDPCS_SYMCLK_DIV2_GATE_ENABLE',
'RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF', 'RDPCS_SYMCLK_SRAMCLK_CLOCK_ON',
'RDPCS_TEST_CLK_SEL', 'RDPCS_TEST_CLK_SEL_CFGCLK',
'RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK',
'RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK',
'RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK',
'RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK',
'RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK',
'RDPCS_TEST_CLK_SEL_EXT_CR_CLK',
'RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK',
'RDPCS_TEST_CLK_SEL_NONE', 'RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK',
'RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk', 'RDPCS_TEST_CLK_SEL_SRAMCLK',
'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS',
'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4',
'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS',
'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4',
'RDPCS_TEST_CLK_SEL_dtb_out0', 'RDPCS_TEST_CLK_SEL_dtb_out1',
'RDPCS_TX_FIFO_DISABLE', 'RDPCS_TX_FIFO_ENABLE',
'RDPCS_TX_FIFO_ERROR_MASK_DISABLE',
'RDPCS_TX_FIFO_ERROR_MASK_ENABLE', 'RDPCS_TX_FIFO_LANE_DISABLE',
'RDPCS_TX_FIFO_LANE_ENABLE', 'RDPCS_TX_SOFT_RESET_DISABLE',
'RDPCS_TX_SOFT_RESET_ENABLE',
'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE',
'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE', 'READ_256_BITS',
'READ_512_BITS', 'READ_SEQ', 'RECTLIST', 'REFCLK_CLOCK_EN',
'REFCLK_CLOCK_EN_ALLOW_SRC_SEL', 'REFCLK_CLOCK_EN_XTALIN_CLK',
'REFCLK_SRC_SEL', 'REFCLK_SRC_SEL_CPL_REFCLK',
'REFCLK_SRC_SEL_PCIE_REFCLK', 'REFER_TO_DP_SOF',
'REFER_TO_OTG_SOF', 'REF_ALWAYS', 'REF_EQUAL', 'REF_GEQUAL',
'REF_GREATER', 'REF_LEQUAL', 'REF_LESS', 'REF_NEVER',
'REF_NOTEQUAL', 'REG_UNALLOCATED_ADDR_READ',
'REG_UNALLOCATED_ADDR_WRITE', 'REG_VIRTUAL_READ',
'REG_VIRTUAL_WRITE', 'RESERVED_60', 'RESERVED_61', 'RESERVED_62',
'RESERVED_63', 'RESERVED_88', 'RESERVED_89', 'RESERVED_90',
'RESERVED_91', 'RESERVED_ES', 'RESERVED_LS', 'RESERVED_RDPOLICY',
'RESERVED_VS', 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', 'RE_Z',
'RGB111110_FIX', 'RGB111110_FLOAT', 'RGB565', 'RGBA1010102',
'RGBA16161616_10LSB', 'RGBA16161616_10MSB', 'RGBA16161616_12LSB',
'RGBA16161616_12MSB', 'RGBA16161616_FLOAT', 'RGBA16161616_SNORM',
'RGBA16161616_UNORM', 'RGBA4444', 'RGBA5551', 'RGBA8888',
'RIGHT_EYE', 'RINGID0', 'RINGID1', 'RINGID2', 'RINGID3',
'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL',
'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED',
'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED',
'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL',
'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED',
'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED',
'RMIPerfSel', 'RMI_CID', 'RMI_CID_CC', 'RMI_CID_CM', 'RMI_CID_DC',
'RMI_CID_FC', 'RMI_CID_S', 'RMI_CID_TILE', 'RMI_CID_Z',
'RMI_CID_ZPCPSD', 'RMI_PERF_SEL_BUSY',
'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR',
'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB',
'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR',
'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB',
'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0',
'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1',
'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2',
'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3',
'RMI_PERF_SEL_DYN_CLK_CMN_VLD', 'RMI_PERF_SEL_DYN_CLK_PERF_VLD',
'RMI_PERF_SEL_DYN_CLK_RB_VLD', 'RMI_PERF_SEL_EVENT_SEND',
'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ',
'RMI_PERF_SEL_LAT_FIFO_FULL',
'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ',
'RMI_PERF_SEL_LAT_FIFO_NUM_USED',
'RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC',
'RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2', 'RMI_PERF_SEL_NONE',
'RMI_PERF_SEL_PERF_WINDOW', 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR',
'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB',
'RMI_PERF_SEL_POP_DEMUX_RTS_RTR',
'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB',
'RMI_PERF_SEL_POP_XNACK_RTSB_RTR',
'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB',
'RMI_PERF_SEL_POP_XNACK_RTS_RTR',
'RMI_PERF_SEL_POP_XNACK_RTS_RTRB',
'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR',
'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB',
'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR',
'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB',
'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT',
'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT',
'RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS',
'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT',
'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY',
'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR',
'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB',
'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR',
'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB',
'RMI_PERF_SEL_PRT_FIFO_BUSY', 'RMI_PERF_SEL_PRT_FIFO_NUM_USED',
'RMI_PERF_SEL_PRT_FIFO_REQ',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID',
'RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID',
'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID',
'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID',
'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID0',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID1',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID2',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID3',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID4',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID5',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID6',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID7',
'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY',
'RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY',
'RMI_PERF_SEL_RB_RMI_RD_BUSY',
'RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY',
'RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX', 'RMI_PERF_SEL_RB_RMI_RD_IDLE',
'RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY',
'RMI_PERF_SEL_RB_RMI_RD_STALL', 'RMI_PERF_SEL_RB_RMI_RD_STARVE',
'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID',
'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID',
'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID0',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID1',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID2',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID3',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID4',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID5',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID6',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID7',
'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY',
'RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY',
'RMI_PERF_SEL_RB_RMI_WR_BUSY',
'RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY',
'RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX', 'RMI_PERF_SEL_RB_RMI_WR_IDLE',
'RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY',
'RMI_PERF_SEL_RB_RMI_WR_STALL', 'RMI_PERF_SEL_RB_RMI_WR_STARVE',
'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR',
'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB',
'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR',
'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB',
'RMI_PERF_SEL_REG_CLK_VLD', 'RMI_PERF_SEL_REORDER_FIFO_BUSY',
'RMI_PERF_SEL_REORDER_FIFO_REQ',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9',
'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9',
'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3',
'RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID',
'RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID',
'RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND',
'RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND',
'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID0',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID1',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID2',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID3',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID4',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID5',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID6',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID7',
'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID',
'RMI_PERF_SEL_RMI_TC_REQ_BUSY',
'RMI_PERF_SEL_RMI_TC_STALL_ALLREQ',
'RMI_PERF_SEL_RMI_TC_STALL_RDREQ',
'RMI_PERF_SEL_RMI_TC_STALL_WRREQ',
'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID0',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID1',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID2',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID3',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID4',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID5',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID6',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID7',
'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID',
'RMI_PERF_SEL_RMI_UTC_BUSY', 'RMI_PERF_SEL_RMI_UTC_REQ',
'RMI_PERF_SEL_SKID_FIFO_BUSY', 'RMI_PERF_SEL_SKID_FIFO_DEPTH',
'RMI_PERF_SEL_SKID_FIFO_IN_RTS', 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB',
'RMI_PERF_SEL_SKID_FIFO_OUT_RTS',
'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB', 'RMI_PERF_SEL_SKID_FIFO_REQ',
'RMI_PERF_SEL_TCIW_BUSY', 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT',
'RMI_PERF_SEL_TCIW_REQ',
'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID',
'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID',
'RMI_PERF_SEL_UTCL1_BUSY', 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL',
'RMI_PERF_SEL_UTCL1_LFIFO_FULL',
'RMI_PERF_SEL_UTCL1_PERMISSION_MISS',
'RMI_PERF_SEL_UTCL1_REQUEST',
'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX',
'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES',
'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT',
'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL',
'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS',
'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS',
'RMI_PERF_SEL_UTCL1_TRANSLATION_HIT',
'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS',
'RMI_PERF_SEL_UTCL1_UTCL2_REQ', 'RMI_PERF_SEL_UTC_POP_RTSB_RTR',
'RMI_PERF_SEL_UTC_POP_RTSB_RTRB', 'RMI_PERF_SEL_UTC_POP_RTS_RTR',
'RMI_PERF_SEL_UTC_POP_RTS_RTRB',
'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR',
'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB',
'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR',
'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB',
'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR',
'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR',
'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR',
'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR',
'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR',
'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR',
'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB',
'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR',
'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB',
'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR',
'RMI_PERF_SEL_XNACK_FIFO_BUSY', 'RMI_PERF_SEL_XNACK_FIFO_FULL',
'RMI_PERF_SEL_XNACK_FIFO_NUM_USED',
'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR',
'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB',
'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR',
'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB', 'ROM_SIGNATURE',
'ROTATED_MICRO_TILING', 'ROTATE_0_DEGREES', 'ROTATE_180_DEGREES',
'ROTATE_270_DEGREES', 'ROTATE_90_DEGREES', 'ROTATION_ANGLE',
'ROUND_BY_HALF', 'ROUND_TRUNCATE', 'RRDPCS_PHY_DP_TX_PSTATE_HOLD',
'RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF',
'RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN',
'RRDPCS_PHY_DP_TX_PSTATE_POWER_UP', 'RST_PIX_CNT', 'RSV_TAG_RAM',
'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', 'ReadPolicy', 'ReadSize',
'Reserved_0x00', 'RingCounterControl', 'RoundMode', 'RowSize',
'RowTiling', 'SAMPLE_PIPELINESTAT', 'SAMPLE_STREAMOUTSTATS',
'SAMPLE_STREAMOUTSTATS1', 'SAMPLE_STREAMOUTSTATS2',
'SAMPLE_STREAMOUTSTATS3', 'SCL_2TAP_HARDCODE', 'SCL_ALPHA_COEF',
'SCL_ALPHA_COEF_ALPHA', 'SCL_ALPHA_COEF_LUMA', 'SCL_AUTOCAL_MODE',
'SCL_BOUNDARY', 'SCL_BOUNDARY_BLACK', 'SCL_BOUNDARY_EDGE',
'SCL_CHROMA_COEF', 'SCL_CHROMA_COEF_CHROMA',
'SCL_CHROMA_COEF_LUMA', 'SCL_COEF_2TAP_HARDCODE_OFF',
'SCL_COEF_2TAP_HARDCODE_ON', 'SCL_COEF_ALPHA_HORZ_FILTER',
'SCL_COEF_ALPHA_VERT_FILTER', 'SCL_COEF_CHROMA_HORZ_FILTER',
'SCL_COEF_CHROMA_VERT_FILTER', 'SCL_COEF_FILTER_TYPE_SEL',
'SCL_COEF_LUMA_HORZ_FILTER', 'SCL_COEF_LUMA_VERT_FILTER',
'SCL_COEF_RAM_SEL', 'SCL_COEF_RAM_SEL_0', 'SCL_COEF_RAM_SEL_1',
'SCL_SHARP_DISABLE', 'SCL_SHARP_EN', 'SCL_SHARP_ENABLE',
'SC_BACKEND_BUSY', 'SC_BACKEND_PRIM_FIFO_FULL', 'SC_BB_DISCARD',
'SC_BCI_CREDIT_AT_MAX', 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND',
'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_BCI_SEND',
'SC_BM_BUSY', 'SC_BUSY_CNT_NOT_ZERO',
'SC_BUSY_PROCESSING_MULTICYCLE_PRIM',
'SC_DB0_TILE_INTERFACE_BUSY',
'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX',
'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND',
'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'SC_DB0_TILE_INTERFACE_SEND', 'SC_DB0_TILE_INTERFACE_SEND_EVENT',
'SC_DB0_TILE_INTERFACE_SEND_SOP',
'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT',
'SC_DB1_TILE_INTERFACE_BUSY',
'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX',
'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND',
'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'SC_DB1_TILE_INTERFACE_SEND', 'SC_DB1_TILE_INTERFACE_SEND_EVENT',
'SC_DB1_TILE_INTERFACE_SEND_SOP',
'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT',
'SC_EARLYZ_QUAD_COUNT', 'SC_EARLYZ_QUAD_WITH_1_PIX',
'SC_EARLYZ_QUAD_WITH_2_PIX', 'SC_EARLYZ_QUAD_WITH_3_PIX',
'SC_EARLYZ_QUAD_WITH_4_PIX', 'SC_EOP_SYNC_WINDOW',
'SC_FULL_FULL_QUAD', 'SC_FULL_HALF_QUAD', 'SC_FULL_QTR_QUAD',
'SC_GRP0_DYN_SCLK_BUSY', 'SC_GRP1_DYN_SCLK_BUSY',
'SC_GRP2_DYN_SCLK_BUSY', 'SC_GRP3_DYN_SCLK_BUSY',
'SC_GRP4_DYN_SCLK_BUSY', 'SC_GRP5_DYN_SCLK_BUSY',
'SC_GRP6_DYN_SCLK_BUSY', 'SC_GRP7_DYN_SCLK_BUSY',
'SC_GRP8_DYN_SCLK_BUSY', 'SC_GRP9_DYN_SCLK_BUSY',
'SC_HALF_FULL_QUAD', 'SC_HALF_HALF_QUAD', 'SC_HALF_LSB',
'SC_HALF_QTR_QUAD', 'SC_LSB_ONE_SIDED', 'SC_LSB_TWO_SIDED',
'SC_MULTICYCLE_BUBBLE_FREEZE', 'SC_P0_DETAIL_QUAD_COUNT',
'SC_P0_DETAIL_QUAD_WITH_1_PIX', 'SC_P0_DETAIL_QUAD_WITH_2_PIX',
'SC_P0_DETAIL_QUAD_WITH_3_PIX', 'SC_P0_DETAIL_QUAD_WITH_4_PIX',
'SC_P0_HIZ_QUAD_COUNT', 'SC_P0_HIZ_QUAD_PER_TILE_H0',
'SC_P0_HIZ_QUAD_PER_TILE_H1', 'SC_P0_HIZ_QUAD_PER_TILE_H10',
'SC_P0_HIZ_QUAD_PER_TILE_H11', 'SC_P0_HIZ_QUAD_PER_TILE_H12',
'SC_P0_HIZ_QUAD_PER_TILE_H13', 'SC_P0_HIZ_QUAD_PER_TILE_H14',
'SC_P0_HIZ_QUAD_PER_TILE_H15', 'SC_P0_HIZ_QUAD_PER_TILE_H16',
'SC_P0_HIZ_QUAD_PER_TILE_H2', 'SC_P0_HIZ_QUAD_PER_TILE_H3',
'SC_P0_HIZ_QUAD_PER_TILE_H4', 'SC_P0_HIZ_QUAD_PER_TILE_H5',
'SC_P0_HIZ_QUAD_PER_TILE_H6', 'SC_P0_HIZ_QUAD_PER_TILE_H7',
'SC_P0_HIZ_QUAD_PER_TILE_H8', 'SC_P0_HIZ_QUAD_PER_TILE_H9',
'SC_P0_HIZ_TILE_COUNT', 'SC_P1_DETAIL_QUAD_COUNT',
'SC_P1_DETAIL_QUAD_WITH_1_PIX', 'SC_P1_DETAIL_QUAD_WITH_2_PIX',
'SC_P1_DETAIL_QUAD_WITH_3_PIX', 'SC_P1_DETAIL_QUAD_WITH_4_PIX',
'SC_P1_HIZ_QUAD_COUNT', 'SC_P1_HIZ_QUAD_PER_TILE_H0',
'SC_P1_HIZ_QUAD_PER_TILE_H1', 'SC_P1_HIZ_QUAD_PER_TILE_H10',
'SC_P1_HIZ_QUAD_PER_TILE_H11', 'SC_P1_HIZ_QUAD_PER_TILE_H12',
'SC_P1_HIZ_QUAD_PER_TILE_H13', 'SC_P1_HIZ_QUAD_PER_TILE_H14',
'SC_P1_HIZ_QUAD_PER_TILE_H15', 'SC_P1_HIZ_QUAD_PER_TILE_H16',
'SC_P1_HIZ_QUAD_PER_TILE_H2', 'SC_P1_HIZ_QUAD_PER_TILE_H3',
'SC_P1_HIZ_QUAD_PER_TILE_H4', 'SC_P1_HIZ_QUAD_PER_TILE_H5',
'SC_P1_HIZ_QUAD_PER_TILE_H6', 'SC_P1_HIZ_QUAD_PER_TILE_H7',
'SC_P1_HIZ_QUAD_PER_TILE_H8', 'SC_P1_HIZ_QUAD_PER_TILE_H9',
'SC_P1_HIZ_TILE_COUNT', 'SC_P2_DETAIL_QUAD_COUNT',
'SC_P2_DETAIL_QUAD_WITH_1_PIX', 'SC_P2_DETAIL_QUAD_WITH_2_PIX',
'SC_P2_DETAIL_QUAD_WITH_3_PIX', 'SC_P2_DETAIL_QUAD_WITH_4_PIX',
'SC_P2_HIZ_QUAD_COUNT', 'SC_P2_HIZ_QUAD_PER_TILE_H0',
'SC_P2_HIZ_QUAD_PER_TILE_H1', 'SC_P2_HIZ_QUAD_PER_TILE_H10',
'SC_P2_HIZ_QUAD_PER_TILE_H11', 'SC_P2_HIZ_QUAD_PER_TILE_H12',
'SC_P2_HIZ_QUAD_PER_TILE_H13', 'SC_P2_HIZ_QUAD_PER_TILE_H14',
'SC_P2_HIZ_QUAD_PER_TILE_H15', 'SC_P2_HIZ_QUAD_PER_TILE_H16',
'SC_P2_HIZ_QUAD_PER_TILE_H2', 'SC_P2_HIZ_QUAD_PER_TILE_H3',
'SC_P2_HIZ_QUAD_PER_TILE_H4', 'SC_P2_HIZ_QUAD_PER_TILE_H5',
'SC_P2_HIZ_QUAD_PER_TILE_H6', 'SC_P2_HIZ_QUAD_PER_TILE_H7',
'SC_P2_HIZ_QUAD_PER_TILE_H8', 'SC_P2_HIZ_QUAD_PER_TILE_H9',
'SC_P2_HIZ_TILE_COUNT', 'SC_P3_DETAIL_QUAD_COUNT',
'SC_P3_DETAIL_QUAD_WITH_1_PIX', 'SC_P3_DETAIL_QUAD_WITH_2_PIX',
'SC_P3_DETAIL_QUAD_WITH_3_PIX', 'SC_P3_DETAIL_QUAD_WITH_4_PIX',
'SC_P3_HIZ_QUAD_COUNT', 'SC_P3_HIZ_QUAD_PER_TILE_H0',
'SC_P3_HIZ_QUAD_PER_TILE_H1', 'SC_P3_HIZ_QUAD_PER_TILE_H10',
'SC_P3_HIZ_QUAD_PER_TILE_H11', 'SC_P3_HIZ_QUAD_PER_TILE_H12',
'SC_P3_HIZ_QUAD_PER_TILE_H13', 'SC_P3_HIZ_QUAD_PER_TILE_H14',
'SC_P3_HIZ_QUAD_PER_TILE_H15', 'SC_P3_HIZ_QUAD_PER_TILE_H16',
'SC_P3_HIZ_QUAD_PER_TILE_H2', 'SC_P3_HIZ_QUAD_PER_TILE_H3',
'SC_P3_HIZ_QUAD_PER_TILE_H4', 'SC_P3_HIZ_QUAD_PER_TILE_H5',
'SC_P3_HIZ_QUAD_PER_TILE_H6', 'SC_P3_HIZ_QUAD_PER_TILE_H7',
'SC_P3_HIZ_QUAD_PER_TILE_H8', 'SC_P3_HIZ_QUAD_PER_TILE_H9',
'SC_P3_HIZ_TILE_COUNT', 'SC_PA0_SC_DATA_FIFO_EOPG_RD',
'SC_PA0_SC_DATA_FIFO_EOP_RD', 'SC_PA0_SC_DATA_FIFO_RD',
'SC_PA0_SC_DATA_FIFO_WE', 'SC_PA0_SC_DEALLOC_0_RD',
'SC_PA0_SC_DEALLOC_1_RD', 'SC_PA0_SC_EOPG_WE', 'SC_PA0_SC_EOP_WE',
'SC_PA0_SC_EVENT_WE', 'SC_PA0_SC_FPOV_WE', 'SC_PA0_SC_LPOV_WE',
'SC_PA0_SC_NULL_DEALLOC_WE', 'SC_PA0_SC_NULL_WE',
'SC_PA1_SC_DATA_FIFO_EOPG_RD', 'SC_PA1_SC_DATA_FIFO_EOP_RD',
'SC_PA1_SC_DATA_FIFO_RD', 'SC_PA1_SC_DATA_FIFO_WE',
'SC_PA1_SC_DEALLOC_0_RD', 'SC_PA1_SC_DEALLOC_1_RD',
'SC_PA1_SC_EOPG_WE', 'SC_PA1_SC_EOP_WE', 'SC_PA1_SC_EVENT_WE',
'SC_PA1_SC_FPOV_WE', 'SC_PA1_SC_LPOV_WE',
'SC_PA1_SC_NULL_DEALLOC_WE', 'SC_PA1_SC_NULL_WE',
'SC_PA2_SC_DATA_FIFO_EOPG_RD', 'SC_PA2_SC_DATA_FIFO_EOP_RD',
'SC_PA2_SC_DATA_FIFO_RD', 'SC_PA2_SC_DATA_FIFO_WE',
'SC_PA2_SC_DEALLOC_0_RD', 'SC_PA2_SC_DEALLOC_1_RD',
'SC_PA2_SC_EOPG_WE', 'SC_PA2_SC_EOP_WE', 'SC_PA2_SC_EVENT_WE',
'SC_PA2_SC_FPOV_WE', 'SC_PA2_SC_LPOV_WE',
'SC_PA2_SC_NULL_DEALLOC_WE', 'SC_PA2_SC_NULL_WE',
'SC_PA3_SC_DATA_FIFO_EOPG_RD', 'SC_PA3_SC_DATA_FIFO_EOP_RD',
'SC_PA3_SC_DATA_FIFO_RD', 'SC_PA3_SC_DATA_FIFO_WE',
'SC_PA3_SC_DEALLOC_0_RD', 'SC_PA3_SC_DEALLOC_1_RD',
'SC_PA3_SC_EOPG_WE', 'SC_PA3_SC_EOP_WE', 'SC_PA3_SC_EVENT_WE',
'SC_PA3_SC_FPOV_WE', 'SC_PA3_SC_LPOV_WE',
'SC_PA3_SC_NULL_DEALLOC_WE', 'SC_PA3_SC_NULL_WE',
'SC_PA_SC_DEALLOC_0_0_WE', 'SC_PA_SC_DEALLOC_0_1_WE',
'SC_PA_SC_DEALLOC_1_0_WE', 'SC_PA_SC_DEALLOC_1_1_WE',
'SC_PA_SC_DEALLOC_2_0_WE', 'SC_PA_SC_DEALLOC_2_1_WE',
'SC_PA_SC_DEALLOC_3_0_WE', 'SC_PA_SC_DEALLOC_3_1_WE',
'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL',
'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE',
'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE',
'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH',
'SC_PBB_BATCH_BREAK_DUE_TO_EVENT',
'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT',
'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE',
'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH',
'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT',
'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV',
'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT',
'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE',
'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE',
'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT',
'SC_PBB_BATCH_BREAK_DUE_TO_PRIM',
'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER',
'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW',
'SC_PBB_BATCH_HIST_NUM_CONTEXTS',
'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES',
'SC_PBB_BATCH_HIST_NUM_PRIMS',
'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS',
'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM',
'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS',
'SC_PBB_BIN_HIST_NUM_CONTEXTS',
'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES',
'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY',
'SC_PBB_BUSY_AND_NO_SENDS', 'SC_PBB_END_OF_BATCH',
'SC_PBB_END_OF_BIN',
'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN',
'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW',
'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION',
'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS',
'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH',
'SC_PBB_STALLS_PA_DUE_TO_NO_TILES',
'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB',
'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL',
'SC_PKR_4X2_FILL_QUAD', 'SC_PKR_4X2_QUAD_SPLIT',
'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV',
'SC_PKR_END_OF_VECTOR', 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE',
'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP',
'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX',
'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', 'SC_PK_BUSY',
'SC_PK_DEALLOC_WAVE_BREAK', 'SC_PK_MAX_DEALLOC_FORCE_EOV',
'SC_POPS_FORCE_EOV', 'SC_POPS_INTRA_WAVE_OVERLAPS',
'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY',
'SC_PS_ARB_EOP_POP_SYNC_POP', 'SC_PS_ARB_EVENT_SYNC_POP',
'SC_PS_ARB_NULL_PRIM_BUBBLE_POP',
'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH',
'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO',
'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY',
'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE',
'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP',
'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_PA0_SC_FIFO_EMPTY',
'SC_PS_PA0_SC_FIFO_FULL', 'SC_PS_PA1_SC_FIFO_EMPTY',
'SC_PS_PA1_SC_FIFO_FULL', 'SC_PS_PA2_SC_FIFO_EMPTY',
'SC_PS_PA2_SC_FIFO_FULL', 'SC_PS_PA3_SC_FIFO_EMPTY',
'SC_PS_PA3_SC_FIFO_FULL', 'SC_PS_TO_BE_SCLK_GATE_STALL',
'SC_PS_TS_EVENT_FIFO_POP', 'SC_PS_TS_EVENT_FIFO_PUSH',
'SC_PW_BM_PASS_EMPTY_PRIM', 'SC_QTR_FULL_QUAD',
'SC_QTR_HALF_QUAD', 'SC_QTR_QTR_QUAD', 'SC_QZ0_QUAD_COUNT',
'SC_QZ0_QUAD_PER_TILE_H0', 'SC_QZ0_QUAD_PER_TILE_H1',
'SC_QZ0_QUAD_PER_TILE_H10', 'SC_QZ0_QUAD_PER_TILE_H11',
'SC_QZ0_QUAD_PER_TILE_H12', 'SC_QZ0_QUAD_PER_TILE_H13',
'SC_QZ0_QUAD_PER_TILE_H14', 'SC_QZ0_QUAD_PER_TILE_H15',
'SC_QZ0_QUAD_PER_TILE_H16', 'SC_QZ0_QUAD_PER_TILE_H2',
'SC_QZ0_QUAD_PER_TILE_H3', 'SC_QZ0_QUAD_PER_TILE_H4',
'SC_QZ0_QUAD_PER_TILE_H5', 'SC_QZ0_QUAD_PER_TILE_H6',
'SC_QZ0_QUAD_PER_TILE_H7', 'SC_QZ0_QUAD_PER_TILE_H8',
'SC_QZ0_QUAD_PER_TILE_H9', 'SC_QZ0_TILE_COUNT',
'SC_QZ0_TILE_COVERED_COUNT', 'SC_QZ0_TILE_NOT_COVERED_COUNT',
'SC_QZ1_QUAD_COUNT', 'SC_QZ1_QUAD_PER_TILE_H0',
'SC_QZ1_QUAD_PER_TILE_H1', 'SC_QZ1_QUAD_PER_TILE_H10',
'SC_QZ1_QUAD_PER_TILE_H11', 'SC_QZ1_QUAD_PER_TILE_H12',
'SC_QZ1_QUAD_PER_TILE_H13', 'SC_QZ1_QUAD_PER_TILE_H14',
'SC_QZ1_QUAD_PER_TILE_H15', 'SC_QZ1_QUAD_PER_TILE_H16',
'SC_QZ1_QUAD_PER_TILE_H2', 'SC_QZ1_QUAD_PER_TILE_H3',
'SC_QZ1_QUAD_PER_TILE_H4', 'SC_QZ1_QUAD_PER_TILE_H5',
'SC_QZ1_QUAD_PER_TILE_H6', 'SC_QZ1_QUAD_PER_TILE_H7',
'SC_QZ1_QUAD_PER_TILE_H8', 'SC_QZ1_QUAD_PER_TILE_H9',
'SC_QZ1_TILE_COUNT', 'SC_QZ1_TILE_COVERED_COUNT',
'SC_QZ1_TILE_NOT_COVERED_COUNT', 'SC_QZ2_QUAD_COUNT',
'SC_QZ2_QUAD_PER_TILE_H0', 'SC_QZ2_QUAD_PER_TILE_H1',
'SC_QZ2_QUAD_PER_TILE_H10', 'SC_QZ2_QUAD_PER_TILE_H11',
'SC_QZ2_QUAD_PER_TILE_H12', 'SC_QZ2_QUAD_PER_TILE_H13',
'SC_QZ2_QUAD_PER_TILE_H14', 'SC_QZ2_QUAD_PER_TILE_H15',
'SC_QZ2_QUAD_PER_TILE_H16', 'SC_QZ2_QUAD_PER_TILE_H2',
'SC_QZ2_QUAD_PER_TILE_H3', 'SC_QZ2_QUAD_PER_TILE_H4',
'SC_QZ2_QUAD_PER_TILE_H5', 'SC_QZ2_QUAD_PER_TILE_H6',
'SC_QZ2_QUAD_PER_TILE_H7', 'SC_QZ2_QUAD_PER_TILE_H8',
'SC_QZ2_QUAD_PER_TILE_H9', 'SC_QZ2_TILE_COUNT',
'SC_QZ2_TILE_COVERED_COUNT', 'SC_QZ2_TILE_NOT_COVERED_COUNT',
'SC_QZ3_QUAD_COUNT', 'SC_QZ3_QUAD_PER_TILE_H0',
'SC_QZ3_QUAD_PER_TILE_H1', 'SC_QZ3_QUAD_PER_TILE_H10',
'SC_QZ3_QUAD_PER_TILE_H11', 'SC_QZ3_QUAD_PER_TILE_H12',
'SC_QZ3_QUAD_PER_TILE_H13', 'SC_QZ3_QUAD_PER_TILE_H14',
'SC_QZ3_QUAD_PER_TILE_H15', 'SC_QZ3_QUAD_PER_TILE_H16',
'SC_QZ3_QUAD_PER_TILE_H2', 'SC_QZ3_QUAD_PER_TILE_H3',
'SC_QZ3_QUAD_PER_TILE_H4', 'SC_QZ3_QUAD_PER_TILE_H5',
'SC_QZ3_QUAD_PER_TILE_H6', 'SC_QZ3_QUAD_PER_TILE_H7',
'SC_QZ3_QUAD_PER_TILE_H8', 'SC_QZ3_QUAD_PER_TILE_H9',
'SC_QZ3_TILE_COUNT', 'SC_QZ3_TILE_COVERED_COUNT',
'SC_QZ3_TILE_NOT_COVERED_COUNT', 'SC_QZQP_WINDOW_VALID',
'SC_QZQP_WINDOW_VALID_BUSY', 'SC_REG_SCLK_BUSY', 'SC_RESERVED_0',
'SC_RESERVED_1', 'SC_RESERVED_2', 'SC_RESERVED_3', 'SC_SCB_BUSY',
'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD',
'SC_SC_PS_ENG_MULTICYCLE_BUBBLE', 'SC_SC_SPI_DEALLOC_0_0',
'SC_SC_SPI_DEALLOC_0_1', 'SC_SC_SPI_DEALLOC_0_2',
'SC_SC_SPI_DEALLOC_1_0', 'SC_SC_SPI_DEALLOC_1_1',
'SC_SC_SPI_DEALLOC_1_2', 'SC_SC_SPI_DEALLOC_2_0',
'SC_SC_SPI_DEALLOC_2_1', 'SC_SC_SPI_DEALLOC_2_2',
'SC_SC_SPI_DEALLOC_3_0', 'SC_SC_SPI_DEALLOC_3_1',
'SC_SC_SPI_DEALLOC_3_2', 'SC_SC_SPI_EVENT', 'SC_SC_SPI_FPOV_0',
'SC_SC_SPI_FPOV_1', 'SC_SC_SPI_FPOV_2', 'SC_SC_SPI_FPOV_3',
'SC_SEND_DB_VPZ', 'SC_SPIBC_FULL_FREEZE', 'SC_SPI_CREDIT_AT_MAX',
'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND',
'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_SPI_SEND',
'SC_SRPS_WINDOW_VALID', 'SC_SRPS_WINDOW_VALID_BUSY',
'SC_STALLED_BY_BCI', 'SC_STALLED_BY_DB_QUAD',
'SC_STALLED_BY_DB_TILE', 'SC_STALLED_BY_PRIMFIFO',
'SC_STALLED_BY_QUADFIFO', 'SC_STALLED_BY_SPI',
'SC_STALLED_BY_TILEFIFO', 'SC_STALLED_BY_TILEORDERFIFO',
'SC_STARVED_BY_DB_QUAD', 'SC_STARVED_BY_DB_TILE',
'SC_STARVED_BY_PA', 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL',
'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY',
'SC_SUPERTILE_COUNT',
'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9',
'SC_SUPERTILE_PER_PRIM_H0', 'SC_SUPERTILE_PER_PRIM_H1',
'SC_SUPERTILE_PER_PRIM_H10', 'SC_SUPERTILE_PER_PRIM_H11',
'SC_SUPERTILE_PER_PRIM_H12', 'SC_SUPERTILE_PER_PRIM_H13',
'SC_SUPERTILE_PER_PRIM_H14', 'SC_SUPERTILE_PER_PRIM_H15',
'SC_SUPERTILE_PER_PRIM_H16', 'SC_SUPERTILE_PER_PRIM_H2',
'SC_SUPERTILE_PER_PRIM_H3', 'SC_SUPERTILE_PER_PRIM_H4',
'SC_SUPERTILE_PER_PRIM_H5', 'SC_SUPERTILE_PER_PRIM_H6',
'SC_SUPERTILE_PER_PRIM_H7', 'SC_SUPERTILE_PER_PRIM_H8',
'SC_SUPERTILE_PER_PRIM_H9', 'SC_TILE_PER_PRIM_H0',
'SC_TILE_PER_PRIM_H1', 'SC_TILE_PER_PRIM_H10',
'SC_TILE_PER_PRIM_H11', 'SC_TILE_PER_PRIM_H12',
'SC_TILE_PER_PRIM_H13', 'SC_TILE_PER_PRIM_H14',
'SC_TILE_PER_PRIM_H15', 'SC_TILE_PER_PRIM_H16',
'SC_TILE_PER_PRIM_H2', 'SC_TILE_PER_PRIM_H3',
'SC_TILE_PER_PRIM_H4', 'SC_TILE_PER_PRIM_H5',
'SC_TILE_PER_PRIM_H6', 'SC_TILE_PER_PRIM_H7',
'SC_TILE_PER_PRIM_H8', 'SC_TILE_PER_PRIM_H9',
'SC_TILE_PER_SUPERTILE_H0', 'SC_TILE_PER_SUPERTILE_H1',
'SC_TILE_PER_SUPERTILE_H10', 'SC_TILE_PER_SUPERTILE_H11',
'SC_TILE_PER_SUPERTILE_H12', 'SC_TILE_PER_SUPERTILE_H13',
'SC_TILE_PER_SUPERTILE_H14', 'SC_TILE_PER_SUPERTILE_H15',
'SC_TILE_PER_SUPERTILE_H16', 'SC_TILE_PER_SUPERTILE_H2',
'SC_TILE_PER_SUPERTILE_H3', 'SC_TILE_PER_SUPERTILE_H4',
'SC_TILE_PER_SUPERTILE_H5', 'SC_TILE_PER_SUPERTILE_H6',
'SC_TILE_PER_SUPERTILE_H7', 'SC_TILE_PER_SUPERTILE_H8',
'SC_TILE_PER_SUPERTILE_H9', 'SC_TILE_PICKED_H1',
'SC_TILE_PICKED_H2', 'SC_TILE_PICKED_H3', 'SC_TILE_PICKED_H4',
'SC_TPQZ_WINDOW_VALID', 'SC_TPQZ_WINDOW_VALID_BUSY',
'SC_TRPK_WINDOW_VALID', 'SC_TRPK_WINDOW_VALID_BUSY',
'SDMA_PERF_SEL', 'SDMA_PERF_SEL_CE_AFIFO_FULL',
'SDMA_PERF_SEL_CE_DST_IDLE', 'SDMA_PERF_SEL_CE_INFO1_FULL',
'SDMA_PERF_SEL_CE_INFO_FULL', 'SDMA_PERF_SEL_CE_IN_IDLE',
'SDMA_PERF_SEL_CE_L1_WR_VLD', 'SDMA_PERF_SEL_CE_OUT_IDLE',
'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE',
'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE',
'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL',
'SDMA_PERF_SEL_CPF_SDMA_INVREQ', 'SDMA_PERF_SEL_CTX_CHANGE',
'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION',
'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE',
'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND',
'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND',
'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_EX_IDLE',
'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
'SDMA_PERF_SEL_F32_L1_WR_VLD', 'SDMA_PERF_SEL_GCR_RTN',
'SDMA_PERF_SEL_GCR_SEND', 'SDMA_PERF_SEL_GFX_SELECT',
'SDMA_PERF_SEL_GPUVM_INVREQ_HIGH',
'SDMA_PERF_SEL_GPUVM_INVREQ_LOW', 'SDMA_PERF_SEL_IB_CMD_FULL',
'SDMA_PERF_SEL_IB_CMD_IDLE', 'SDMA_PERF_SEL_IDLE',
'SDMA_PERF_SEL_INT_IDLE', 'SDMA_PERF_SEL_INT_REQ_COUNT',
'SDMA_PERF_SEL_INT_REQ_STALL', 'SDMA_PERF_SEL_INT_RESP_ACCEPTED',
'SDMA_PERF_SEL_INT_RESP_RETRY', 'SDMA_PERF_SEL_L1_RDL2_IDLE',
'SDMA_PERF_SEL_L1_RDMC_IDLE', 'SDMA_PERF_SEL_L1_RD_INV_IDLE',
'SDMA_PERF_SEL_L1_WRL2_IDLE', 'SDMA_PERF_SEL_L1_WRMC_IDLE',
'SDMA_PERF_SEL_L1_WR_INV_IDLE', 'SDMA_PERF_SEL_L2_META_RET_VLD',
'SDMA_PERF_SEL_MC_RD_COUNT', 'SDMA_PERF_SEL_MC_RD_IDLE',
'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE',
'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT',
'SDMA_PERF_SEL_MC_WR_IDLE', 'SDMA_PERF_SEL_META_L2_REQ_SEND',
'SDMA_PERF_SEL_META_REQ_SEND', 'SDMA_PERF_SEL_META_RTN_VLD',
'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER',
'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_PAGE_SELECT',
'SDMA_PERF_SEL_RB_CMD_FULL', 'SDMA_PERF_SEL_RB_CMD_IDLE',
'SDMA_PERF_SEL_RB_EMPTY', 'SDMA_PERF_SEL_RB_FULL',
'SDMA_PERF_SEL_RB_RPTR_WB', 'SDMA_PERF_SEL_RB_RPTR_WRAP',
'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 'SDMA_PERF_SEL_RB_WPTR_WRAP',
'SDMA_PERF_SEL_RD_BA_RTR', 'SDMA_PERF_SEL_REG_IDLE',
'SDMA_PERF_SEL_RLC0_SELECT', 'SDMA_PERF_SEL_RLC1_SELECT',
'SDMA_PERF_SEL_SDMA_CPF_INVACK',
'SDMA_PERF_SEL_SDMA_UTCL2_INVACK',
'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL',
'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND',
'SDMA_PERF_SEL_SDMA_UTCL2_SEND',
'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', 'SDMA_PERF_SEL_SEM_IDLE',
'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL',
'SDMA_PERF_SEL_SEM_RESP_FAIL',
'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE',
'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND',
'SDMA_PERF_SEL_TLBI_RTN', 'SDMA_PERF_SEL_TLBI_SEND',
'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER',
'SDMA_PERF_SEL_UTCL2_FREE', 'SDMA_PERF_SEL_UTCL2_RET_ACK',
'SDMA_PERF_SEL_UTCL2_RET_XNACK',
'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ',
'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL',
'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN',
'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', 'SDMA_PERF_SEL_WR_BA_RTR',
'SEC_GSP0_PRIORITY_HIGH', 'SEC_GSP0_PRIORITY_LOW', 'SEGMENTS_1',
'SEGMENTS_128', 'SEGMENTS_16', 'SEGMENTS_2', 'SEGMENTS_32',
'SEGMENTS_4', 'SEGMENTS_64', 'SEGMENTS_8', 'SEM_ECC_ERROR',
'SEM_PERF_SEL', 'SEM_PERF_SEL_ACP_REQ_SIGNAL',
'SEM_PERF_SEL_ACP_REQ_WAIT', 'SEM_PERF_SEL_ATC_INVALIDATION',
'SEM_PERF_SEL_ATC_REQ', 'SEM_PERF_SEL_ATC_RET',
'SEM_PERF_SEL_ATC_VM_INVALIDATION', 'SEM_PERF_SEL_ATC_XNACK',
'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL',
'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT',
'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL',
'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT',
'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL',
'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT',
'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL',
'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT',
'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL',
'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT',
'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL',
'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT',
'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL',
'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT',
'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL',
'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT',
'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E0_REQ_WAIT',
'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E1_REQ_WAIT',
'SEM_PERF_SEL_CYCLE', 'SEM_PERF_SEL_IDLE',
'SEM_PERF_SEL_ISP_REQ_SIGNAL', 'SEM_PERF_SEL_ISP_REQ_WAIT',
'SEM_PERF_SEL_MC_RD_REQ', 'SEM_PERF_SEL_MC_RD_RET',
'SEM_PERF_SEL_MC_WR_REQ', 'SEM_PERF_SEL_MC_WR_RET',
'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA0_REQ_WAIT',
'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA1_REQ_WAIT',
'SEM_PERF_SEL_UVD_REQ_SIGNAL', 'SEM_PERF_SEL_UVD_REQ_WAIT',
'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 'SEM_PERF_SEL_VCE0_REQ_WAIT',
'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 'SEM_PERF_SEL_VCE1_REQ_WAIT',
'SEM_PERF_SEL_VP8_REQ_SIGNAL', 'SEM_PERF_SEL_VP8_REQ_WAIT',
'SEM_RESP_FAILED', 'SEM_RESP_PASSED', 'SEM_TRANS_ERROR',
'SEND_AT_EARLIEST_TIME', 'SEND_AT_LINK_NUMBER',
'SEND_NORMAL_PACKET', 'SEND_PPS_PACKET', 'SET_FE_ID',
'SET_STATIC_SCREEN_SMU_INTR', 'SH_MEM_ADDRESS_MODE',
'SH_MEM_ADDRESS_MODE_32', 'SH_MEM_ADDRESS_MODE_64',
'SH_MEM_ALIGNMENT_MODE', 'SH_MEM_ALIGNMENT_MODE_DWORD',
'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT',
'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED',
'SH_MEM_RETRY_MODE', 'SH_MEM_RETRY_MODE_ALL',
'SH_MEM_RETRY_MODE_NONE', 'SH_MEM_RETRY_MODE_WRITEATOMIC',
'SIGNED', 'SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE',
'SIMM16_WAITCNT_DEPCTR_SA_SDST_START',
'SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE',
'SIMM16_WAITCNT_DEPCTR_VA_SDST_START',
'SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE',
'SIMM16_WAITCNT_DEPCTR_VA_SSRC_START',
'SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE',
'SIMM16_WAITCNT_DEPCTR_VA_VCC_START',
'SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE',
'SIMM16_WAITCNT_DEPCTR_VA_VDST_START',
'SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE',
'SIMM16_WAITCNT_DEPCTR_VM_VSRC_START',
'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START',
'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START',
'SIMM16_WAITCNT_VM_CNT_HI_SIZE', 'SIMM16_WAITCNT_VM_CNT_HI_START',
'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START',
'SIXTEEN_BANKS', 'SIXTEEN_PIPES', 'SIXTY_FOUR_PIPES', 'SIZE_16K',
'SIZE_8K', 'SMU_INTR_STATUS_CLEAR', 'SMU_INTR_STATUS_NOOP',
'SM_MODE_RESERVED', 'SOFT_RESET', 'SOFT_RESET_0', 'SOFT_RESET_1',
'SO_VGTSTREAMOUT_FLUSH', 'SPI_FOG_EXP', 'SPI_FOG_EXP2',
'SPI_FOG_LINEAR', 'SPI_FOG_MODE', 'SPI_FOG_NONE',
'SPI_LB_WAVES_RSVD', 'SPI_LB_WAVES_SELECT', 'SPI_PERFCNT_SEL',
'SPI_PERF_CLKGATE_ACTIVE_STALL', 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON',
'SPI_PERF_CLKGATE_BUSY_STALL', 'SPI_PERF_CLKGATE_CGTT_DYN_ON',
'SPI_PERF_CLKGATE_CGTT_REG_ON', 'SPI_PERF_CSG_BUSY',
'SPI_PERF_CSG_CRAWLER_STALL', 'SPI_PERF_CSG_EVENT_WAVE',
'SPI_PERF_CSG_NUM_THREADGROUPS', 'SPI_PERF_CSG_WAVE',
'SPI_PERF_CSG_WINDOW_VALID', 'SPI_PERF_CSN_BUSY',
'SPI_PERF_CSN_CRAWLER_STALL', 'SPI_PERF_CSN_EVENT_WAVE',
'SPI_PERF_CSN_NUM_THREADGROUPS', 'SPI_PERF_CSN_WAVE',
'SPI_PERF_CSN_WINDOW_VALID', 'SPI_PERF_ESC_VTX_BUSY',
'SPI_PERF_ESC_VTX_CAC_BUSY', 'SPI_PERF_ESC_VTX_INPUT_STARVED',
'SPI_PERF_ESC_VTX_VSR_FULL', 'SPI_PERF_ESC_VTX_VSR_STALL',
'SPI_PERF_ES_BUSY', 'SPI_PERF_ES_CRAWLER_STALL',
'SPI_PERF_ES_EVENT_WAVE', 'SPI_PERF_ES_FIRST_SUBGRP',
'SPI_PERF_ES_FIRST_WAVE', 'SPI_PERF_ES_LAST_SUBGRP',
'SPI_PERF_ES_LAST_WAVE', 'SPI_PERF_ES_LSHS_DEALLOC',
'SPI_PERF_ES_PERS_UPD_FULL0', 'SPI_PERF_ES_PERS_UPD_FULL1',
'SPI_PERF_ES_WAVE', 'SPI_PERF_ES_WINDOW_VALID',
'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT',
'SPI_PERF_EXP_ARB_PAR_CNT', 'SPI_PERF_EXP_ARB_POS_CNT',
'SPI_PERF_GSC_VTX_BUSY', 'SPI_PERF_GSC_VTX_CAC_BUSY',
'SPI_PERF_GSC_VTX_INPUT_STARVED', 'SPI_PERF_GSC_VTX_VSR_FULL',
'SPI_PERF_GSC_VTX_VSR_STALL', 'SPI_PERF_GS_BUSY',
'SPI_PERF_GS_CRAWLER_STALL', 'SPI_PERF_GS_EVENT_WAVE',
'SPI_PERF_GS_FIRST_SUBGRP', 'SPI_PERF_GS_GRP_FIFO_FULL',
'SPI_PERF_GS_HS_DEALLOC', 'SPI_PERF_GS_LAST_SUBGRP',
'SPI_PERF_GS_NGG_GS_ALLOC_FIFO_EMPTY', 'SPI_PERF_GS_NGG_PC_FULL',
'SPI_PERF_GS_NGG_SE_AT_SYNC_EVENT',
'SPI_PERF_GS_NGG_SE_DEALLOC_PC_SPACE_CNT',
'SPI_PERF_GS_NGG_SE_DOES_NOT_HAVE_BATON',
'SPI_PERF_GS_NGG_SE_FORWARDED_BATON',
'SPI_PERF_GS_NGG_SE_HAS_BATON',
'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT',
'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC',
'SPI_PERF_GS_NGG_SE_SG_ALLOC_PC_SPACE_CNT',
'SPI_PERF_GS_PERS_UPD_FULL0', 'SPI_PERF_GS_PERS_UPD_FULL1',
'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WINDOW_VALID',
'SPI_PERF_HS_BUSY', 'SPI_PERF_HS_CRAWLER_STALL',
'SPI_PERF_HS_EVENT_WAVE', 'SPI_PERF_HS_FIRST_WAVE',
'SPI_PERF_HS_LAST_WAVE', 'SPI_PERF_HS_OFFCHIP_LDS_STALL',
'SPI_PERF_HS_PERS_UPD_FULL0', 'SPI_PERF_HS_PERS_UPD_FULL1',
'SPI_PERF_HS_WAVE', 'SPI_PERF_HS_WINDOW_VALID',
'SPI_PERF_LDS0_PC_VALID', 'SPI_PERF_LDS1_PC_VALID',
'SPI_PERF_LS_BUSY', 'SPI_PERF_LS_CRAWLER_STALL',
'SPI_PERF_LS_EVENT_WAVE', 'SPI_PERF_LS_FIRST_WAVE',
'SPI_PERF_LS_LAST_WAVE', 'SPI_PERF_LS_OFFCHIP_LDS_STALL',
'SPI_PERF_LS_PERS_UPD_FULL0', 'SPI_PERF_LS_PERS_UPD_FULL1',
'SPI_PERF_LS_WAVE', 'SPI_PERF_LS_WINDOW_VALID',
'SPI_PERF_NUM_EXPGRANT_EXPORTS', 'SPI_PERF_NUM_PS_COL_R0_EXPORTS',
'SPI_PERF_NUM_PS_COL_R1_EXPORTS',
'SPI_PERF_NUM_VS_GDS_R0_EXPORTS',
'SPI_PERF_NUM_VS_GDS_R1_EXPORTS',
'SPI_PERF_NUM_VS_PARAM_R0_EXPORTS',
'SPI_PERF_NUM_VS_PARAM_R1_EXPORTS',
'SPI_PERF_NUM_VS_POS_R0_EXPORTS',
'SPI_PERF_NUM_VS_POS_R1_EXPORTS', 'SPI_PERF_PC_ALLOC_ACCUM',
'SPI_PERF_PIX_ALLOC_DB0_STALL', 'SPI_PERF_PIX_ALLOC_DB1_STALL',
'SPI_PERF_PIX_ALLOC_DB2_STALL', 'SPI_PERF_PIX_ALLOC_DB3_STALL',
'SPI_PERF_PIX_ALLOC_DB4_STALL', 'SPI_PERF_PIX_ALLOC_DB5_STALL',
'SPI_PERF_PIX_ALLOC_DB6_STALL', 'SPI_PERF_PIX_ALLOC_DB7_STALL',
'SPI_PERF_PIX_ALLOC_PEND_CNT', 'SPI_PERF_PIX_ALLOC_SCB0_STALL',
'SPI_PERF_PIX_ALLOC_SCB1_STALL', 'SPI_PERF_PIX_ALLOC_SCB2_STALL',
'SPI_PERF_PIX_ALLOC_SCB3_STALL', 'SPI_PERF_PS0_ACTIVE',
'SPI_PERF_PS0_BUSY', 'SPI_PERF_PS0_CNF_BIN2',
'SPI_PERF_PS0_CNF_BIN3', 'SPI_PERF_PS0_CRAWLER_STALL',
'SPI_PERF_PS0_DEALLOC_BIN0', 'SPI_PERF_PS0_EVENT_WAVE',
'SPI_PERF_PS0_FPOS_BIN1_STALL', 'SPI_PERF_PS0_FPOS_BIN2',
'SPI_PERF_PS0_LDS_RES_FULL', 'SPI_PERF_PS0_OPT_WAVE',
'SPI_PERF_PS0_PASS_BIN0', 'SPI_PERF_PS0_PASS_BIN1',
'SPI_PERF_PS0_POPS_WAVE_EXIT', 'SPI_PERF_PS0_POPS_WAVE_SENT',
'SPI_PERF_PS0_PRIM_BIN0', 'SPI_PERF_PS0_PRIM_BIN1',
'SPI_PERF_PS0_WAVE', 'SPI_PERF_PS0_WINDOW_VALID',
'SPI_PERF_PS1_ACTIVE', 'SPI_PERF_PS1_BUSY',
'SPI_PERF_PS1_CNF_BIN2', 'SPI_PERF_PS1_CNF_BIN3',
'SPI_PERF_PS1_CRAWLER_STALL', 'SPI_PERF_PS1_DEALLOC_BIN0',
'SPI_PERF_PS1_EVENT_WAVE', 'SPI_PERF_PS1_FPOS_BIN1_STALL',
'SPI_PERF_PS1_FPOS_BIN2', 'SPI_PERF_PS1_LDS_RES_FULL',
'SPI_PERF_PS1_OPT_WAVE', 'SPI_PERF_PS1_PASS_BIN0',
'SPI_PERF_PS1_PASS_BIN1', 'SPI_PERF_PS1_POPS_WAVE_EXIT',
'SPI_PERF_PS1_POPS_WAVE_SENT', 'SPI_PERF_PS1_PRIM_BIN0',
'SPI_PERF_PS1_PRIM_BIN1', 'SPI_PERF_PS1_WAVE',
'SPI_PERF_PS1_WINDOW_VALID', 'SPI_PERF_PS2_ACTIVE',
'SPI_PERF_PS2_BUSY', 'SPI_PERF_PS2_CNF_BIN2',
'SPI_PERF_PS2_CNF_BIN3', 'SPI_PERF_PS2_CRAWLER_STALL',
'SPI_PERF_PS2_DEALLOC_BIN0', 'SPI_PERF_PS2_EVENT_WAVE',
'SPI_PERF_PS2_FPOS_BIN1_STALL', 'SPI_PERF_PS2_FPOS_BIN2',
'SPI_PERF_PS2_LDS_RES_FULL', 'SPI_PERF_PS2_OPT_WAVE',
'SPI_PERF_PS2_PASS_BIN0', 'SPI_PERF_PS2_PASS_BIN1',
'SPI_PERF_PS2_POPS_WAVE_EXIT', 'SPI_PERF_PS2_POPS_WAVE_SENT',
'SPI_PERF_PS2_PRIM_BIN0', 'SPI_PERF_PS2_PRIM_BIN1',
'SPI_PERF_PS2_WAVE', 'SPI_PERF_PS2_WINDOW_VALID',
'SPI_PERF_PS3_ACTIVE', 'SPI_PERF_PS3_BUSY',
'SPI_PERF_PS3_CNF_BIN2', 'SPI_PERF_PS3_CNF_BIN3',
'SPI_PERF_PS3_CRAWLER_STALL', 'SPI_PERF_PS3_DEALLOC_BIN0',
'SPI_PERF_PS3_EVENT_WAVE', 'SPI_PERF_PS3_FPOS_BIN1_STALL',
'SPI_PERF_PS3_FPOS_BIN2', 'SPI_PERF_PS3_LDS_RES_FULL',
'SPI_PERF_PS3_OPT_WAVE', 'SPI_PERF_PS3_PASS_BIN0',
'SPI_PERF_PS3_PASS_BIN1', 'SPI_PERF_PS3_POPS_WAVE_EXIT',
'SPI_PERF_PS3_POPS_WAVE_SENT', 'SPI_PERF_PS3_PRIM_BIN0',
'SPI_PERF_PS3_PRIM_BIN1', 'SPI_PERF_PS3_WAVE',
'SPI_PERF_PS3_WINDOW_VALID', 'SPI_PERF_PS_PERS_UPD_FULL0',
'SPI_PERF_PS_PERS_UPD_FULL1', 'SPI_PERF_RA_BAR_CU_FULL_CSG',
'SPI_PERF_RA_BAR_CU_FULL_CSN', 'SPI_PERF_RA_BAR_CU_FULL_HS',
'SPI_PERF_RA_BULKY_CU_FULL_CSG', 'SPI_PERF_RA_BULKY_CU_FULL_CSN',
'SPI_PERF_RA_CSG_LOCK', 'SPI_PERF_RA_CSN_LOCK',
'SPI_PERF_RA_GS_LOCK', 'SPI_PERF_RA_HS_LOCK',
'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN',
'SPI_PERF_RA_LDS_CU_FULL_ES', 'SPI_PERF_RA_LDS_CU_FULL_LS',
'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_PIPE_REQ_BIN2',
'SPI_PERF_RA_REQ_NO_ALLOC', 'SPI_PERF_RA_REQ_NO_ALLOC_CSG',
'SPI_PERF_RA_REQ_NO_ALLOC_CSN', 'SPI_PERF_RA_REQ_NO_ALLOC_GS',
'SPI_PERF_RA_REQ_NO_ALLOC_HS', 'SPI_PERF_RA_REQ_NO_ALLOC_PS',
'SPI_PERF_RA_REQ_NO_ALLOC_VS', 'SPI_PERF_RA_RES_STALL_CSG',
'SPI_PERF_RA_RES_STALL_CSN', 'SPI_PERF_RA_RES_STALL_GS',
'SPI_PERF_RA_RES_STALL_HS', 'SPI_PERF_RA_RES_STALL_PS',
'SPI_PERF_RA_RES_STALL_VS', 'SPI_PERF_RA_RSV_UPD',
'SPI_PERF_RA_SGPR_SIMD_FULL_CSG',
'SPI_PERF_RA_SGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_SGPR_SIMD_FULL_GS',
'SPI_PERF_RA_SGPR_SIMD_FULL_HS', 'SPI_PERF_RA_SGPR_SIMD_FULL_PS',
'SPI_PERF_RA_SGPR_SIMD_FULL_VS', 'SPI_PERF_RA_TASK_REQ_BIN3',
'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN',
'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN',
'SPI_PERF_RA_TMP_STALL_GS', 'SPI_PERF_RA_TMP_STALL_HS',
'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_TMP_STALL_VS',
'SPI_PERF_RA_VGPR_SIMD_FULL_CSG',
'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_GS',
'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS',
'SPI_PERF_RA_VGPR_SIMD_FULL_VS', 'SPI_PERF_RA_VS_LOCK',
'SPI_PERF_RA_WAVE_SIMD_FULL_CSG',
'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_GS',
'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS',
'SPI_PERF_RA_WAVE_SIMD_FULL_VS', 'SPI_PERF_RA_WR_CTL_FULL',
'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN',
'SPI_PERF_RA_WVLIM_STALL_GS', 'SPI_PERF_RA_WVLIM_STALL_HS',
'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_RA_WVLIM_STALL_VS',
'SPI_PERF_SWC_CSC_WR', 'SPI_PERF_SWC_CSG_WR',
'SPI_PERF_SWC_GS_WR', 'SPI_PERF_SWC_HS_WR', 'SPI_PERF_SWC_PS_WR',
'SPI_PERF_SWC_VS_WR', 'SPI_PERF_VS_ALLOC_CNT', 'SPI_PERF_VS_BUSY',
'SPI_PERF_VS_CRAWLER_STALL', 'SPI_PERF_VS_EVENT_WAVE',
'SPI_PERF_VS_FIRST_SUBGRP', 'SPI_PERF_VS_FIRST_WAVE',
'SPI_PERF_VS_LAST_SUBGRP', 'SPI_PERF_VS_LAST_WAVE',
'SPI_PERF_VS_LATE_ALLOC_ACCUM', 'SPI_PERF_VS_LATE_ALLOC_FULL',
'SPI_PERF_VS_LSHS_DEALLOC', 'SPI_PERF_VS_PC_ALLOC_CNT',
'SPI_PERF_VS_PC_STALL', 'SPI_PERF_VS_PERS_UPD_FULL0',
'SPI_PERF_VS_PERS_UPD_FULL1', 'SPI_PERF_VS_POS0_STALL',
'SPI_PERF_VS_POS1_STALL', 'SPI_PERF_VS_WAVE',
'SPI_PERF_VS_WINDOW_VALID', 'SPI_PERF_VWC_CSC_WR',
'SPI_PERF_VWC_CSG_WR', 'SPI_PERF_VWC_GS_WR', 'SPI_PERF_VWC_HS_WR',
'SPI_PERF_VWC_PS_WR', 'SPI_PERF_VWC_VS_WR',
'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0',
'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE',
'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', 'SPI_SAMPLE_CNTL',
'SPI_SHADER_1COMP', 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR',
'SPI_SHADER_32_AR', 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R',
'SPI_SHADER_4COMP', 'SPI_SHADER_4COMPRESS',
'SPI_SHADER_EX_FORMAT', 'SPI_SHADER_FORMAT',
'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE',
'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR',
'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR',
'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN',
'SP_PERF_SEL_DUMMY_BEGIN', 'SP_PERF_SEL_DUMMY_LAST',
'SQC_PERF_SEL_DCACHE_ATOMIC', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES',
'SQC_PERF_SEL_DCACHE_CACHE_STALLED',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED',
'SQC_PERF_SEL_DCACHE_FLAT_REQ', 'SQC_PERF_SEL_DCACHE_GCR',
'SQC_PERF_SEL_DCACHE_GCR_HITS',
'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE',
'SQC_PERF_SEL_DCACHE_GCR_WRITEBACK', 'SQC_PERF_SEL_DCACHE_HITS',
'SQC_PERF_SEL_DCACHE_HIT_LRU_READ',
'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL',
'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT',
'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB',
'SQC_PERF_SEL_DCACHE_INPUT_VALIDB',
'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY',
'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB',
'SQC_PERF_SEL_DCACHE_INVAL_ASYNC',
'SQC_PERF_SEL_DCACHE_INVAL_INST', 'SQC_PERF_SEL_DCACHE_MISSES',
'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE',
'SQC_PERF_SEL_DCACHE_NONFLAT_REQ', 'SQC_PERF_SEL_DCACHE_REQ',
'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE',
'SQC_PERF_SEL_DCACHE_REQ_READ_1',
'SQC_PERF_SEL_DCACHE_REQ_READ_16',
'SQC_PERF_SEL_DCACHE_REQ_READ_2',
'SQC_PERF_SEL_DCACHE_REQ_READ_4',
'SQC_PERF_SEL_DCACHE_REQ_READ_8', 'SQC_PERF_SEL_DCACHE_REQ_TIME',
'SQC_PERF_SEL_DCACHE_REQ_WRITE_1',
'SQC_PERF_SEL_DCACHE_REQ_WRITE_2',
'SQC_PERF_SEL_DCACHE_REQ_WRITE_4',
'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT',
'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL',
'SQC_PERF_SEL_DCACHE_UTCL0_ALL_REQ',
'SQC_PERF_SEL_DCACHE_UTCL0_HIT_FIFO_FULL',
'SQC_PERF_SEL_DCACHE_UTCL0_INFLIGHT_LEVEL',
'SQC_PERF_SEL_DCACHE_UTCL0_LFIFO_FULL',
'SQC_PERF_SEL_DCACHE_UTCL0_PERMISSION_MISS',
'SQC_PERF_SEL_DCACHE_UTCL0_REQUEST',
'SQC_PERF_SEL_DCACHE_UTCL0_STALL_INFLIGHT_MAX',
'SQC_PERF_SEL_DCACHE_UTCL0_STALL_LFIFO_NOT_RES',
'SQC_PERF_SEL_DCACHE_UTCL0_STALL_LRU_INFLIGHT',
'SQC_PERF_SEL_DCACHE_UTCL0_STALL_MISSFIFO_FULL',
'SQC_PERF_SEL_DCACHE_UTCL0_STALL_MULTI_MISS',
'SQC_PERF_SEL_DCACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS',
'SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_HIT',
'SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_MISS',
'SQC_PERF_SEL_DCACHE_UTCL0_UTCL1_INFLIGHT',
'SQC_PERF_SEL_DCACHE_UTCL0_XNACK',
'SQC_PERF_SEL_DCACHE_UTCL1_ALL_REQ',
'SQC_PERF_SEL_DCACHE_UTCL1_INFLIGHT_LEVEL',
'SQC_PERF_SEL_DCACHE_WB_ASYNC', 'SQC_PERF_SEL_DCACHE_WB_INST',
'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE',
'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE', 'SQC_PERF_SEL_DUMMY_LAST',
'SQC_PERF_SEL_ICACHE_BUSY_CYCLES',
'SQC_PERF_SEL_ICACHE_CACHE_STALLED',
'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX',
'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO',
'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT',
'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO',
'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO',
'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF',
'SQC_PERF_SEL_ICACHE_GCR', 'SQC_PERF_SEL_ICACHE_GCR_HITS',
'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_ICACHE_HITS',
'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL',
'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT',
'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB',
'SQC_PERF_SEL_ICACHE_INPUT_VALIDB',
'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY',
'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB',
'SQC_PERF_SEL_ICACHE_INVAL_ASYNC',
'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES',
'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_ICACHE_REQ',
'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT',
'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL',
'SQC_PERF_SEL_ICACHE_UTCL0_ALL_REQ',
'SQC_PERF_SEL_ICACHE_UTCL0_INFLIGHT_LEVEL',
'SQC_PERF_SEL_ICACHE_UTCL0_LFIFO_FULL',
'SQC_PERF_SEL_ICACHE_UTCL0_PERMISSION_MISS',
'SQC_PERF_SEL_ICACHE_UTCL0_REQUEST',
'SQC_PERF_SEL_ICACHE_UTCL0_STALL_INFLIGHT_MAX',
'SQC_PERF_SEL_ICACHE_UTCL0_STALL_LFIFO_NOT_RES',
'SQC_PERF_SEL_ICACHE_UTCL0_STALL_LRU_INFLIGHT',
'SQC_PERF_SEL_ICACHE_UTCL0_STALL_MISSFIFO_FULL',
'SQC_PERF_SEL_ICACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS',
'SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_HIT',
'SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_MISS',
'SQC_PERF_SEL_ICACHE_UTCL0_UTCL1_INFLIGHT',
'SQC_PERF_SEL_ICACHE_UTCL0_XNACK',
'SQC_PERF_SEL_ICACHE_UTCL1_ALL_REQ',
'SQC_PERF_SEL_ICACHE_UTCL1_INFLIGHT_LEVEL',
'SQC_PERF_SEL_LDS_ADDR_ACTIVE', 'SQC_PERF_SEL_LDS_ADDR_CONFLICT',
'SQC_PERF_SEL_LDS_ADDR_STALL', 'SQC_PERF_SEL_LDS_ATOMIC_RETURN',
'SQC_PERF_SEL_LDS_BANK_CONFLICT',
'SQC_PERF_SEL_LDS_CMD_FIFO_FULL',
'SQC_PERF_SEL_LDS_DATA_FIFO_FULL',
'SQC_PERF_SEL_LDS_DIRECT_FIFO_FULL_STALL',
'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', 'SQC_PERF_SEL_LDS_IDX_ACTIVE',
'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL',
'SQC_PERF_SEL_LDS_MEM_VIOLATIONS',
'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD',
'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD',
'SQC_PERF_SEL_LDS_UNALIGNED_STALL', 'SQC_PERF_SEL_POWER_ALU_BUSY',
'SQC_PERF_SEL_POWER_GPR_RD', 'SQC_PERF_SEL_POWER_GPR_WR',
'SQC_PERF_SEL_POWER_LDS_BUSY', 'SQC_PERF_SEL_POWER_TEX_BUSY',
'SQC_PERF_SEL_POWER_VALU', 'SQC_PERF_SEL_POWER_VALU0',
'SQC_PERF_SEL_POWER_VALU1', 'SQC_PERF_SEL_POWER_VALU2',
'SQC_PERF_SEL_PT_POWER_STALL', 'SQC_PERF_SEL_SQ_DCACHE_REQS',
'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ',
'SQC_PERF_SEL_TC_DATA_READ_REQ', 'SQC_PERF_SEL_TC_DATA_WRITE_REQ',
'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ',
'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL',
'SQC_PERF_SEL_TC_STARVE', 'SQDEC_BEGIN', 'SQDEC_END',
'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', 'SQG_PERF_SEL_DUMMY_LAST',
'SQG_PERF_SEL_TLB_SHOOTDOWN', 'SQG_PERF_SEL_TLB_SHOOTDOWN_CYCLES',
'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS',
'SQG_PERF_SEL_TTRACE_LOST_PACKETS', 'SQG_PERF_SEL_TTRACE_REQS',
'SQG_PERF_SEL_TTRACE_STALL', 'SQG_PERF_SEL_UTCL0_HIT_FIFO_FULL',
'SQG_PERF_SEL_UTCL0_LFIFO_FULL',
'SQG_PERF_SEL_UTCL0_PERMISSION_MISS',
'SQG_PERF_SEL_UTCL0_REQUEST',
'SQG_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX',
'SQG_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES',
'SQG_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT',
'SQG_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL',
'SQG_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS',
'SQG_PERF_SEL_UTCL0_TRANSLATION_HIT',
'SQG_PERF_SEL_UTCL0_TRANSLATION_MISS',
'SQG_PERF_SEL_UTCL0_UTCL1_REQ', 'SQIND_GLOBAL_REGS_OFFSET',
'SQIND_GLOBAL_REGS_SIZE', 'SQIND_LOCAL_REGS_OFFSET',
'SQIND_LOCAL_REGS_SIZE', 'SQIND_WAVE_HWREGS_OFFSET',
'SQIND_WAVE_HWREGS_SIZE', 'SQIND_WAVE_SGPRS_OFFSET',
'SQIND_WAVE_SGPRS_SIZE', 'SQIND_WAVE_VGPRS_OFFSET',
'SQIND_WAVE_VGPRS_SIZE', 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END',
'SQPERFSDEC_BEGIN', 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN',
'SQPWRDEC_END', 'SQ_CAC_POWER_ALU_BUSY', 'SQ_CAC_POWER_GPR_RD',
'SQ_CAC_POWER_GPR_WR', 'SQ_CAC_POWER_LDS_BUSY',
'SQ_CAC_POWER_SEL', 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU',
'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2',
'SQ_DISPATCHER_GFX_CNT_PER_RING', 'SQ_DISPATCHER_GFX_MIN',
'SQ_EDC_FUE_CNTL_LDS', 'SQ_EDC_FUE_CNTL_SIMD0',
'SQ_EDC_FUE_CNTL_SIMD1', 'SQ_EDC_FUE_CNTL_SIMD2',
'SQ_EDC_FUE_CNTL_SIMD3', 'SQ_EDC_FUE_CNTL_SQ',
'SQ_EDC_FUE_CNTL_TA', 'SQ_EDC_FUE_CNTL_TCP', 'SQ_EDC_FUE_CNTL_TD',
'SQ_EDC_INFO_SOURCE', 'SQ_EDC_INFO_SOURCE_GDS',
'SQ_EDC_INFO_SOURCE_INST', 'SQ_EDC_INFO_SOURCE_INVALID',
'SQ_EDC_INFO_SOURCE_LDS', 'SQ_EDC_INFO_SOURCE_SGPR',
'SQ_EDC_INFO_SOURCE_TA', 'SQ_EDC_INFO_SOURCE_VGPR',
'SQ_EX_MODE_EXCP_ADDR_WATCH0', 'SQ_EX_MODE_EXCP_DIV0',
'SQ_EX_MODE_EXCP_HI_ADDR_WATCH1',
'SQ_EX_MODE_EXCP_HI_ADDR_WATCH2',
'SQ_EX_MODE_EXCP_HI_ADDR_WATCH3', 'SQ_EX_MODE_EXCP_INEXACT',
'SQ_EX_MODE_EXCP_INPUT_DENORM', 'SQ_EX_MODE_EXCP_INT_DIV0',
'SQ_EX_MODE_EXCP_INVALID', 'SQ_EX_MODE_EXCP_MEM_VIOL',
'SQ_EX_MODE_EXCP_OVERFLOW', 'SQ_EX_MODE_EXCP_UNDERFLOW',
'SQ_EX_MODE_EXCP_VALU_BASE', 'SQ_EX_MODE_EXCP_VALU_SIZE',
'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT',
'SQ_IBUF_IB_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_DRET',
'SQ_IBUF_IB_EMPTY_WAIT_GNT', 'SQ_IBUF_IB_IDLE',
'SQ_IBUF_IB_INI_WAIT_DRET', 'SQ_IBUF_IB_INI_WAIT_GNT',
'SQ_IBUF_IB_LE_4DW', 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST',
'SQ_IMG_FILTER_MODE_BLEND', 'SQ_IMG_FILTER_MODE_MAX',
'SQ_IMG_FILTER_MODE_MIN', 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD',
'SQ_IND_CMD_CMD_DEBUG', 'SQ_IND_CMD_CMD_KILL',
'SQ_IND_CMD_CMD_NULL', 'SQ_IND_CMD_CMD_SAVECTX',
'SQ_IND_CMD_CMD_SETFATALHALT', 'SQ_IND_CMD_CMD_SETHALT',
'SQ_IND_CMD_CMD_SET_SPI_PRIO', 'SQ_IND_CMD_CMD_SINGLE_STEP',
'SQ_IND_CMD_CMD_TRAP', 'SQ_IND_CMD_MODE',
'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME',
'SQ_IND_CMD_MODE_BROADCAST_PIPE',
'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE',
'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV',
'SQ_INST_STR_IB_WAVE_INST_SKIP_AV',
'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV',
'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML',
'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT',
'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0',
'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1', 'SQ_INST_STR_ST',
'SQ_INTERRUPT_WORD_ENCODING', 'SQ_INTERRUPT_WORD_ENCODING_AUTO',
'SQ_INTERRUPT_WORD_ENCODING_ERROR',
'SQ_INTERRUPT_WORD_ENCODING_INST', 'SQ_MAX_PGM_SGPRS',
'SQ_MAX_PGM_VGPRS', 'SQ_NON_EVENT', 'SQ_OOB_COMPLETE',
'SQ_OOB_INDEX_AND_OFFSET', 'SQ_OOB_INDEX_ONLY',
'SQ_OOB_NUM_RECORDS_0', 'SQ_OOB_SELECT', 'SQ_PERF_SEL',
'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_BUSY_CYCLES',
'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END',
'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS',
'SQ_PERF_SEL_EXP_BUS0_BUSY', 'SQ_PERF_SEL_EXP_BUS1_BUSY',
'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY',
'SQ_PERF_SEL_EXP_REQ_BUS_STALL', 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL',
'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_REQS',
'SQ_PERF_SEL_IFETCH_XNACK', 'SQ_PERF_SEL_INSTS_ALL',
'SQ_PERF_SEL_INSTS_BRANCH', 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN',
'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN',
'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', 'SQ_PERF_SEL_INSTS_EXP',
'SQ_PERF_SEL_INSTS_EXP_GDS', 'SQ_PERF_SEL_INSTS_FLAT',
'SQ_PERF_SEL_INSTS_FLAT_REPLAY', 'SQ_PERF_SEL_INSTS_GDS',
'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_SALU',
'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM',
'SQ_PERF_SEL_INSTS_SMEM_NORM',
'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY',
'SQ_PERF_SEL_INSTS_SMEM_REPLAY', 'SQ_PERF_SEL_INSTS_TEX',
'SQ_PERF_SEL_INSTS_TEX_LOAD', 'SQ_PERF_SEL_INSTS_TEX_REPLAY',
'SQ_PERF_SEL_INSTS_TEX_STORE', 'SQ_PERF_SEL_INSTS_VALU',
'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED',
'SQ_PERF_SEL_INSTS_VALU_LDS_DIRECT_RD',
'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC',
'SQ_PERF_SEL_INSTS_VALU_TRANS32',
'SQ_PERF_SEL_INSTS_VALU_VINTRP_OP', 'SQ_PERF_SEL_INSTS_WAVE32',
'SQ_PERF_SEL_INSTS_WAVE32_FLAT', 'SQ_PERF_SEL_INSTS_WAVE32_LDS',
'SQ_PERF_SEL_INSTS_WAVE32_TEX',
'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD',
'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE',
'SQ_PERF_SEL_INSTS_WAVE32_VALU',
'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC',
'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32',
'SQ_PERF_SEL_INST_CACHE_REQS', 'SQ_PERF_SEL_INST_CACHE_REQ_STALL',
'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', 'SQ_PERF_SEL_INST_CYCLES_FLAT',
'SQ_PERF_SEL_INST_CYCLES_LDS', 'SQ_PERF_SEL_INST_CYCLES_TEX',
'SQ_PERF_SEL_INST_CYCLES_VALU',
'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC',
'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32',
'SQ_PERF_SEL_INST_CYCLES_VMEM',
'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD',
'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE',
'SQ_PERF_SEL_INST_LEVEL_EXP', 'SQ_PERF_SEL_INST_LEVEL_GDS',
'SQ_PERF_SEL_INST_LEVEL_LDS', 'SQ_PERF_SEL_INST_LEVEL_SMEM',
'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD',
'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', 'SQ_PERF_SEL_ITEMS',
'SQ_PERF_SEL_ITEM_CYCLES_VALU',
'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL',
'SQ_PERF_SEL_LEVEL_WAVES',
'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_SALU',
'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VALU',
'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VMEM', 'SQ_PERF_SEL_MSG',
'SQ_PERF_SEL_MSG_BUS_BUSY', 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL',
'SQ_PERF_SEL_MSG_GSCNT', 'SQ_PERF_SEL_MSG_INTERRUPT',
'SQ_PERF_SEL_NONE', 'SQ_PERF_SEL_QUADS', 'SQ_PERF_SEL_Reserved_1',
'SQ_PERF_SEL_Reserved_10', 'SQ_PERF_SEL_Reserved_11',
'SQ_PERF_SEL_Reserved_12', 'SQ_PERF_SEL_Reserved_13',
'SQ_PERF_SEL_Reserved_14', 'SQ_PERF_SEL_Reserved_15',
'SQ_PERF_SEL_Reserved_16', 'SQ_PERF_SEL_Reserved_17',
'SQ_PERF_SEL_Reserved_18', 'SQ_PERF_SEL_Reserved_2',
'SQ_PERF_SEL_Reserved_3', 'SQ_PERF_SEL_Reserved_4',
'SQ_PERF_SEL_Reserved_5', 'SQ_PERF_SEL_Reserved_6',
'SQ_PERF_SEL_Reserved_7', 'SQ_PERF_SEL_Reserved_8',
'SQ_PERF_SEL_Reserved_9', 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL',
'SQ_PERF_SEL_SALU_PIPE_STALL', 'SQ_PERF_SEL_SALU_SGATHER_STALL',
'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL',
'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL',
'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES',
'SQ_PERF_SEL_SMEM_DCACHE_RETURN_STALL', 'SQ_PERF_SEL_USER0',
'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11',
'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14',
'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3',
'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6',
'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9',
'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1',
'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11',
'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13',
'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15',
'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3',
'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5',
'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7',
'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9',
'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL',
'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES',
'SQ_PERF_SEL_VALU_RETURN_SDST',
'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL',
'SQ_PERF_SEL_VALU_SGATHER_STALL',
'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL',
'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', 'SQ_PERF_SEL_VMEM_BUS_ACTIVE',
'SQ_PERF_SEL_VMEM_BUS_STALL',
'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL',
'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL',
'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL',
'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL',
'SQ_PERF_SEL_VMEM_SECOND_TRY_STALL',
'SQ_PERF_SEL_VMEM_SECOND_TRY_USED',
'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY',
'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', 'SQ_PERF_SEL_WAIT_ANY',
'SQ_PERF_SEL_WAIT_BARRIER', 'SQ_PERF_SEL_WAIT_CNT_ANY',
'SQ_PERF_SEL_WAIT_CNT_EXP', 'SQ_PERF_SEL_WAIT_CNT_LGKM',
'SQ_PERF_SEL_WAIT_CNT_VMVS', 'SQ_PERF_SEL_WAIT_EXP_ALLOC',
'SQ_PERF_SEL_WAIT_IFETCH', 'SQ_PERF_SEL_WAIT_INST_ANY',
'SQ_PERF_SEL_WAIT_INST_BR_MSG', 'SQ_PERF_SEL_WAIT_INST_EXP_GDS',
'SQ_PERF_SEL_WAIT_INST_FLAT', 'SQ_PERF_SEL_WAIT_INST_LDS',
'SQ_PERF_SEL_WAIT_INST_SCA', 'SQ_PERF_SEL_WAIT_INST_TEX',
'SQ_PERF_SEL_WAIT_INST_VALU', 'SQ_PERF_SEL_WAIT_INST_VMEM',
'SQ_PERF_SEL_WAIT_OTHER', 'SQ_PERF_SEL_WAIT_SLEEP',
'SQ_PERF_SEL_WAIT_SLEEP_XNACK', 'SQ_PERF_SEL_WAIT_TTRACE',
'SQ_PERF_SEL_WAVE32_INSTS', 'SQ_PERF_SEL_WAVE32_ITEMS',
'SQ_PERF_SEL_WAVE64_HALF_SKIP', 'SQ_PERF_SEL_WAVE64_INSTS',
'SQ_PERF_SEL_WAVE64_ITEMS', 'SQ_PERF_SEL_WAVES',
'SQ_PERF_SEL_WAVES_32', 'SQ_PERF_SEL_WAVES_64',
'SQ_PERF_SEL_WAVES_EQ_64', 'SQ_PERF_SEL_WAVES_LT_16',
'SQ_PERF_SEL_WAVES_LT_32', 'SQ_PERF_SEL_WAVES_LT_48',
'SQ_PERF_SEL_WAVES_LT_64', 'SQ_PERF_SEL_WAVES_RESTORED',
'SQ_PERF_SEL_WAVES_SAVED', 'SQ_PERF_SEL_WAVE_CYCLES',
'SQ_PERF_SEL_WAVE_READY', 'SQ_PERF_SEL_XNACK_ALL',
'SQ_PERF_SEL_XNACK_FIRST', 'SQ_ROUND_MINUS_INFINITY',
'SQ_ROUND_MODE', 'SQ_ROUND_NEAREST_EVEN',
'SQ_ROUND_PLUS_INFINITY', 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF',
'SQ_RSRC_BUF_RSVD_1', 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3',
'SQ_RSRC_BUF_TYPE', 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0',
'SQ_RSRC_FLAT_RSVD_2', 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE',
'SQ_RSRC_IMG_1D', 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D',
'SQ_RSRC_IMG_2D_ARRAY', 'SQ_RSRC_IMG_2D_MSAA',
'SQ_RSRC_IMG_2D_MSAA_ARRAY', 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE',
'SQ_RSRC_IMG_RSVD_0', 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2',
'SQ_RSRC_IMG_RSVD_3', 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5',
'SQ_RSRC_IMG_RSVD_6', 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE',
'SQ_SEL_0', 'SQ_SEL_1', 'SQ_SEL_N_BC_1', 'SQ_SEL_RESERVED_1',
'SQ_SEL_W', 'SQ_SEL_X', 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z',
'SQ_TEX_ANISO_RATIO', 'SQ_TEX_ANISO_RATIO_1',
'SQ_TEX_ANISO_RATIO_16', 'SQ_TEX_ANISO_RATIO_2',
'SQ_TEX_ANISO_RATIO_4', 'SQ_TEX_ANISO_RATIO_8',
'SQ_TEX_BORDER_COLOR', 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK',
'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE',
'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK',
'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER',
'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE',
'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL',
'SQ_TEX_DEPTH_COMPARE_GREATER',
'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS',
'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER',
'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER',
'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE',
'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ',
'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER',
'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL',
'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER',
'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT',
'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT',
'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR',
'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT',
'SQ_TT_INST_EXCLUDE_EXPGNT234',
'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD', 'SQ_TT_MODE',
'SQ_TT_MODE_DETAIL', 'SQ_TT_MODE_GLOBAL', 'SQ_TT_MODE_OFF',
'SQ_TT_MODE_ON', 'SQ_TT_RT_FREQ', 'SQ_TT_RT_FREQ_1024_CLK',
'SQ_TT_RT_FREQ_4096_CLK', 'SQ_TT_RT_FREQ_NEVER',
'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_IMMED1_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', 'SQ_TT_TOKEN_MASK_COMP_BIT',
'SQ_TT_TOKEN_MASK_COMP_SHIFT', 'SQ_TT_TOKEN_MASK_CONFIG_BIT',
'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', 'SQ_TT_TOKEN_MASK_CONTEXT_BIT',
'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT',
'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', 'SQ_TT_TOKEN_MASK_INST_EXCLUDE',
'SQ_TT_TOKEN_MASK_OTHER_BIT', 'SQ_TT_TOKEN_MASK_OTHER_SHIFT',
'SQ_TT_TOKEN_MASK_READS_BIT', 'SQ_TT_TOKEN_MASK_READS_SHIFT',
'SQ_TT_TOKEN_MASK_REG_INCLUDE',
'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT',
'SQ_TT_TOKEN_MASK_SHDEC_BIT', 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT',
'SQ_TT_TOKEN_MASK_SQDEC_BIT', 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT',
'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT', 'SQ_TT_UTIL_TIMER',
'SQ_TT_UTIL_TIMER_100_CLK', 'SQ_TT_UTIL_TIMER_250_CLK',
'SQ_TT_WAVESTART_MODE', 'SQ_TT_WAVESTART_MODE_ALLOC',
'SQ_TT_WAVESTART_MODE_PBB_ID', 'SQ_TT_WAVESTART_MODE_SHORT',
'SQ_TT_WTYPE_INCLUDE', 'SQ_TT_WTYPE_INCLUDE_CS_BIT',
'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_ES_BIT',
'SQ_TT_WTYPE_INCLUDE_ES_SHIFT', 'SQ_TT_WTYPE_INCLUDE_GS_BIT',
'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_HS_BIT',
'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_LS_BIT',
'SQ_TT_WTYPE_INCLUDE_LS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_PS_BIT',
'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_SHIFT',
'SQ_TT_WTYPE_INCLUDE_VS_BIT', 'SQ_TT_WTYPE_INCLUDE_VS_SHIFT',
'SQ_WATCH_MODES', 'SQ_WATCH_MODE_ALL', 'SQ_WATCH_MODE_ATOMIC',
'SQ_WATCH_MODE_NONREAD', 'SQ_WATCH_MODE_READ',
'SQ_WAVE_IB_ECC_CLEAN', 'SQ_WAVE_IB_ECC_ERR_CONTINUE',
'SQ_WAVE_IB_ECC_ERR_HALT', 'SQ_WAVE_IB_ECC_ST',
'SQ_WAVE_IB_ECC_WITH_ERR_MSG', 'SQ_WAVE_SCHED_MODES',
'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', 'SQ_WAVE_SCHED_MODE_EXPERT',
'SQ_WAVE_SCHED_MODE_NORMAL', 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS',
'SQ_WAVE_TYPE_ES', 'SQ_WAVE_TYPE_GS', 'SQ_WAVE_TYPE_HS',
'SQ_WAVE_TYPE_LS', 'SQ_WAVE_TYPE_PS', 'SQ_WAVE_TYPE_PS0',
'SQ_WAVE_TYPE_PS1', 'SQ_WAVE_TYPE_PS2', 'SQ_WAVE_TYPE_PS3',
'SQ_WAVE_TYPE_VS', 'STALL', 'STATIC_SCREEN_SMU_INTR',
'STATIC_SCREEN_SMU_INTR_NOOP', 'STENCIL_8', 'STENCIL_ADD_CLAMP',
'STENCIL_ADD_WRAP', 'STENCIL_AND', 'STENCIL_INVALID',
'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR',
'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP',
'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP',
'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', 'STEREO_DISABLED',
'STREAM_0_SYNCHRONIZATION',
'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_10_SYNCHRONIZATION',
'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_11_SYNCHRONIZATION',
'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_12_SYNCHRONIZATION',
'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_13_SYNCHRONIZATION',
'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_14_SYNCHRONIZATION',
'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_15_SYNCHRONIZATION',
'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_1_SYNCHRONIZATION',
'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_2_SYNCHRONIZATION',
'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_3_SYNCHRONIZATION',
'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_4_SYNCHRONIZATION',
'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_5_SYNCHRONIZATION',
'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_6_SYNCHRONIZATION',
'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_7_SYNCHRONIZATION',
'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_8_SYNCHRONIZATION',
'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_9_SYNCHRONIZATION',
'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM',
'STRM_PERFMON_STATE_DISABLE_AND_RESET',
'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM',
'STRM_PERFMON_STATE_RESERVED_3',
'STRM_PERFMON_STATE_START_COUNTING',
'STRM_PERFMON_STATE_STOP_COUNTING', 'SURFACE_DCC',
'SURFACE_DCC_IND_64B', 'SURFACE_DCC_IS_IND_64B',
'SURFACE_DCC_IS_NOT_IND_64B', 'SURFACE_FLIP_AWAY_INT_LEVEL',
'SURFACE_FLIP_AWAY_INT_PULSE', 'SURFACE_FLIP_AWAY_INT_TYPE',
'SURFACE_FLIP_INT_LEVEL', 'SURFACE_FLIP_INT_PULSE',
'SURFACE_FLIP_INT_TYPE', 'SURFACE_FLIP_IN_STEREOSYNC',
'SURFACE_FLIP_IN_STEREOSYNC_MODE',
'SURFACE_FLIP_MODE_FOR_STEREOSYNC',
'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED',
'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE',
'SURFACE_FLIP_STEREO_SELECT_DISABLE',
'SURFACE_FLIP_STEREO_SELECT_DISABLED',
'SURFACE_FLIP_STEREO_SELECT_ENABLED',
'SURFACE_FLIP_STEREO_SELECT_POLARITY',
'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT',
'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT',
'SURFACE_FLIP_TYPE', 'SURFACE_FLIP_VUPDATE_SKIP_NUM',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_0',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_1',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_10',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_11',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_12',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_13',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_14',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_15',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_2',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_3',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_4',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_5',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_6',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_7',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_8',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', 'SURFACE_INUSE_IS_LATCHED',
'SURFACE_INUSE_IS_NOT_LATCHED', 'SURFACE_INUSE_RAED_NO_LATCH',
'SURFACE_IS_DCC', 'SURFACE_IS_NOT_DCC', 'SURFACE_IS_NOT_TMZ',
'SURFACE_IS_TMZ', 'SURFACE_I_FLIP', 'SURFACE_PIXEL_FORMAT',
'SURFACE_TMZ', 'SURFACE_UPDATE_IS_LOCKED',
'SURFACE_UPDATE_IS_UNLOCKED', 'SURFACE_UPDATE_LOCK',
'SURFACE_V_FLIP', 'SURF_16_BANK', 'SURF_2_BANK', 'SURF_4_BANK',
'SURF_8_BANK', 'SURF_BANK_HEIGHT_1', 'SURF_BANK_HEIGHT_2',
'SURF_BANK_HEIGHT_4', 'SURF_BANK_HEIGHT_8', 'SURF_BANK_WIDTH_1',
'SURF_BANK_WIDTH_2', 'SURF_BANK_WIDTH_4', 'SURF_BANK_WIDTH_8',
'SURF_MACRO_ASPECT_1', 'SURF_MACRO_ASPECT_2',
'SURF_MACRO_ASPECT_4', 'SURF_MACRO_ASPECT_8',
'SURF_TILE_SPLIT_128B', 'SURF_TILE_SPLIT_1KB',
'SURF_TILE_SPLIT_256B', 'SURF_TILE_SPLIT_2KB',
'SURF_TILE_SPLIT_4KB', 'SURF_TILE_SPLIT_512B',
'SURF_TILE_SPLIT_64B', 'SU_PERFCNT_SEL', 'SWAP_ALT',
'SWAP_ALT_REV', 'SWAP_STD', 'SWAP_STD_REV', 'SWATH_HEIGHT',
'SWATH_HEIGHT_16L', 'SWATH_HEIGHT_1L', 'SWATH_HEIGHT_2L',
'SWATH_HEIGHT_4L', 'SWATH_HEIGHT_8L', 'SWIZZLE_4KB_D',
'SWIZZLE_4KB_D_X', 'SWIZZLE_4KB_S', 'SWIZZLE_4KB_S_X',
'SWIZZLE_64KB_D', 'SWIZZLE_64KB_D_T', 'SWIZZLE_64KB_D_X',
'SWIZZLE_64KB_R_X', 'SWIZZLE_64KB_S', 'SWIZZLE_64KB_S_T',
'SWIZZLE_64KB_S_X', 'SWIZZLE_LINEAR', 'SWIZZLE_MODE_ENUM',
'SWIZZLE_TYPE_ENUM', 'SWIZZLE_VAR_D', 'SWIZZLE_VAR_D_X',
'SWIZZLE_VAR_S', 'SWIZZLE_VAR_S_X', 'SW_256B_D', 'SW_256B_R',
'SW_256B_S', 'SW_4KB_D', 'SW_4KB_D_X', 'SW_4KB_R', 'SW_4KB_R_X',
'SW_4KB_S', 'SW_4KB_S_X', 'SW_4KB_Z', 'SW_4KB_Z_X', 'SW_64KB_D',
'SW_64KB_D_T', 'SW_64KB_D_X', 'SW_64KB_R', 'SW_64KB_R_T',
'SW_64KB_R_X', 'SW_64KB_S', 'SW_64KB_S_T', 'SW_64KB_S_X',
'SW_64KB_Z', 'SW_64KB_Z_T', 'SW_64KB_Z_X', 'SW_D', 'SW_L',
'SW_LINEAR', 'SW_MODE', 'SW_R', 'SW_S', 'SW_VAR_D', 'SW_VAR_D_X',
'SW_VAR_R', 'SW_VAR_R_X', 'SW_VAR_S', 'SW_VAR_S_X', 'SW_VAR_Z',
'SW_VAR_Z_X', 'SW_Z', 'SX_BLEND_OPT', 'SX_CB_RAT_ACK_REQUEST',
'SX_DOWNCONVERT_FORMAT', 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS',
'SX_PERF_SEL_CLOCK', 'SX_PERF_SEL_CLOCK_DROP_STALL',
'SX_PERF_SEL_COL_BUSY', 'SX_PERF_SEL_COL_SCBD0_STALL',
'SX_PERF_SEL_COL_SCBD1_STALL', 'SX_PERF_SEL_COL_SCBD_STALL',
'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB0_HALF_QUADS',
'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS',
'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC',
'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST',
'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS',
'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS',
'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS',
'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC',
'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST',
'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS',
'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS',
'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS',
'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC',
'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST',
'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS',
'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS',
'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS',
'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC',
'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST',
'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS',
'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS',
'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS',
'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC',
'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST',
'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS',
'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS',
'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS',
'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC',
'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST',
'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS',
'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS',
'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS',
'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC',
'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST',
'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS',
'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS',
'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS',
'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC',
'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST',
'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS',
'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS',
'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL',
'SX_PERF_SEL_DB0_PRED_PIXELS', 'SX_PERF_SEL_DB0_SIZE',
'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB1_HALF_QUADS',
'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS',
'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC',
'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST',
'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS',
'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS',
'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS',
'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC',
'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST',
'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS',
'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS',
'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS',
'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC',
'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST',
'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS',
'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS',
'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS',
'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC',
'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST',
'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS',
'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS',
'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS',
'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC',
'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST',
'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS',
'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS',
'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS',
'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC',
'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST',
'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS',
'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS',
'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS',
'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC',
'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST',
'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS',
'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS',
'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS',
'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC',
'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST',
'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS',
'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS',
'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL',
'SX_PERF_SEL_DB1_PRED_PIXELS', 'SX_PERF_SEL_DB1_SIZE',
'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB2_HALF_QUADS',
'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS',
'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC',
'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST',
'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS',
'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS',
'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS',
'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC',
'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST',
'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS',
'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS',
'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS',
'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC',
'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST',
'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS',
'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS',
'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS',
'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC',
'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST',
'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS',
'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS',
'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS',
'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC',
'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST',
'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS',
'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS',
'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS',
'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC',
'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST',
'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS',
'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS',
'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS',
'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC',
'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST',
'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS',
'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS',
'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS',
'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC',
'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST',
'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS',
'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS',
'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL',
'SX_PERF_SEL_DB2_PRED_PIXELS', 'SX_PERF_SEL_DB2_SIZE',
'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB3_HALF_QUADS',
'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS',
'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC',
'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST',
'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS',
'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS',
'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS',
'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC',
'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST',
'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS',
'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS',
'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS',
'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC',
'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST',
'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS',
'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS',
'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS',
'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC',
'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST',
'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS',
'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS',
'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS',
'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC',
'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST',
'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS',
'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS',
'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS',
'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC',
'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST',
'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS',
'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS',
'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS',
'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC',
'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST',
'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS',
'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS',
'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS',
'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC',
'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST',
'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS',
'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS',
'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL',
'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_DB3_SIZE',
'SX_PERF_SEL_GATE_EN1', 'SX_PERF_SEL_GATE_EN2',
'SX_PERF_SEL_GATE_EN3', 'SX_PERF_SEL_GATE_EN4',
'SX_PERF_SEL_GATE_EN5', 'SX_PERF_SEL_GATE_EN6',
'SX_PERF_SEL_GATE_EN7', 'SX_PERF_SEL_GATE_EN8',
'SX_PERF_SEL_IDX_BUSY', 'SX_PERF_SEL_IDX_IDLE_CYCLES',
'SX_PERF_SEL_IDX_REQ', 'SX_PERF_SEL_IDX_REQ_LATENCY',
'SX_PERF_SEL_IDX_RET', 'SX_PERF_SEL_IDX_SCBD_STALL',
'SX_PERF_SEL_IDX_STALL_CYCLES', 'SX_PERF_SEL_PA_IDLE_CYCLES',
'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_REQ',
'SX_PERF_SEL_PA_REQ_LATENCY', 'SX_PERF_SEL_POS_BUSY',
'SX_PERF_SEL_POS_SCBD_STALL', 'SX_PERF_SEL_SH_COLOR_STALL',
'SX_PERF_SEL_SH_COLOR_STARVE', 'SX_PERF_SEL_SH_IDX_STARVE',
'SX_PERF_SEL_SH_POS_STALL', 'SX_PERF_SEL_SH_POS_STARVE',
'SX_PERF_SEL_SPLITMODE', 'SX_RT_EXPORT_10_11_11',
'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR',
'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10',
'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4',
'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8',
'SX_RT_EXPORT_NO_CONVERSION', 'SYMCLK_FE_FORCE_EN',
'SYMCLK_FE_FORCE_EN_DISABLE', 'SYMCLK_FE_FORCE_EN_ENABLE',
'SYMCLK_FE_FORCE_SRC', 'SYMCLK_FE_FORCE_SRC_RESERVED',
'SYMCLK_FE_FORCE_SRC_UNIPHYA', 'SYMCLK_FE_FORCE_SRC_UNIPHYB',
'SYMCLK_FE_FORCE_SRC_UNIPHYC', 'SYMCLK_FE_FORCE_SRC_UNIPHYD',
'SYMCLK_FE_FORCE_SRC_UNIPHYE', 'SYMCLK_FE_FORCE_SRC_UNIPHYF',
'SampleSplit', 'SampleSplitBytes', 'ScMap',
'ScUncertaintyRegionMode', 'ScXsel', 'ScYsel', 'SeEnable',
'SeMap', 'SePairMap', 'SePairXsel', 'SePairYsel', 'SeXsel',
'SeYsel', 'ShaderEngineTileSize', 'SourceFormat', 'Spare_261',
'Spare_285', 'Spare_286', 'StencilFormat', 'StencilOp',
'SurfaceArray', 'SurfaceEndian', 'SurfaceFormat', 'SurfaceNumber',
'SurfaceSwap', 'SurfaceTiling', 'TA_PERFCOUNT_SEL',
'TA_PERF_SEL_NULL', 'TA_PERF_SEL_RESERVED_29',
'TA_PERF_SEL_RESERVED_41', 'TA_PERF_SEL_RESERVED_42',
'TA_PERF_SEL_RESERVED_43',
'TA_PERF_SEL_addr_stalled_by_tc_cycles',
'TA_PERF_SEL_addr_stalled_by_td_cycles',
'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy',
'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles',
'TA_PERF_SEL_addresser_stalled_cycles',
'TA_PERF_SEL_aligner_busy', 'TA_PERF_SEL_aligner_cycles',
'TA_PERF_SEL_aniso_10_cycle_quads',
'TA_PERF_SEL_aniso_12_cycle_quads',
'TA_PERF_SEL_aniso_14_cycle_quads',
'TA_PERF_SEL_aniso_16_cycle_quads',
'TA_PERF_SEL_aniso_1_cycle_quads',
'TA_PERF_SEL_aniso_2_cycle_quads',
'TA_PERF_SEL_aniso_4_cycle_quads',
'TA_PERF_SEL_aniso_6_cycle_quads',
'TA_PERF_SEL_aniso_8_cycle_quads',
'TA_PERF_SEL_aniso_gt1_cycle_quads',
'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles',
'TA_PERF_SEL_aniso_stalled_cycles',
'TA_PERF_SEL_bilin_point_1_cycle_pixels',
'TA_PERF_SEL_buffer_atomic_wavefronts',
'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles',
'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles',
'TA_PERF_SEL_buffer_coalescable_wavefronts',
'TA_PERF_SEL_buffer_coalesced_read_cycles',
'TA_PERF_SEL_buffer_coalesced_write_cycles',
'TA_PERF_SEL_buffer_read_wavefronts',
'TA_PERF_SEL_buffer_total_cycles',
'TA_PERF_SEL_buffer_wavefronts',
'TA_PERF_SEL_buffer_write_wavefronts',
'TA_PERF_SEL_color_1_cycle_pixels',
'TA_PERF_SEL_color_2_cycle_pixels',
'TA_PERF_SEL_color_3_cycle_pixels',
'TA_PERF_SEL_color_4_cycle_pixels',
'TA_PERF_SEL_data_stalled_by_tc_cycles',
'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles',
'TA_PERF_SEL_deriv_stalled_cycles',
'TA_PERF_SEL_first_xnack_on_phase0',
'TA_PERF_SEL_first_xnack_on_phase1',
'TA_PERF_SEL_first_xnack_on_phase2',
'TA_PERF_SEL_first_xnack_on_phase3',
'TA_PERF_SEL_flat_atomic_wavefronts',
'TA_PERF_SEL_flat_coalesceable_wavefronts',
'TA_PERF_SEL_flat_read_wavefronts', 'TA_PERF_SEL_flat_wavefronts',
'TA_PERF_SEL_flat_write_wavefronts', 'TA_PERF_SEL_gradient_busy',
'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy',
'TA_PERF_SEL_image_atomic_wavefronts',
'TA_PERF_SEL_image_read_wavefronts',
'TA_PERF_SEL_image_total_cycles', 'TA_PERF_SEL_image_wavefronts',
'TA_PERF_SEL_image_write_wavefronts',
'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en',
'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en',
'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en',
'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en',
'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en', 'TA_PERF_SEL_lod_busy',
'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_pixels',
'TA_PERF_SEL_mip_2_cycle_pixels',
'TA_PERF_SEL_mipmap_invalid_samples',
'TA_PERF_SEL_mipmap_lod_0_samples',
'TA_PERF_SEL_mipmap_lod_10_samples',
'TA_PERF_SEL_mipmap_lod_11_samples',
'TA_PERF_SEL_mipmap_lod_12_samples',
'TA_PERF_SEL_mipmap_lod_13_samples',
'TA_PERF_SEL_mipmap_lod_14_samples',
'TA_PERF_SEL_mipmap_lod_1_samples',
'TA_PERF_SEL_mipmap_lod_2_samples',
'TA_PERF_SEL_mipmap_lod_3_samples',
'TA_PERF_SEL_mipmap_lod_4_samples',
'TA_PERF_SEL_mipmap_lod_5_samples',
'TA_PERF_SEL_mipmap_lod_6_samples',
'TA_PERF_SEL_mipmap_lod_7_samples',
'TA_PERF_SEL_mipmap_lod_8_samples',
'TA_PERF_SEL_mipmap_lod_9_samples', 'TA_PERF_SEL_reg_sclk_vld',
'TA_PERF_SEL_sh_fifo_addr_busy',
'TA_PERF_SEL_sh_fifo_addr_cycles',
'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles',
'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles',
'TA_PERF_SEL_sh_fifo_busy', 'TA_PERF_SEL_sh_fifo_cmd_busy',
'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles',
'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles',
'TA_PERF_SEL_sh_fifo_data_busy',
'TA_PERF_SEL_sh_fifo_data_cycles',
'TA_PERF_SEL_sh_fifo_data_sfifo_busy',
'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles',
'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles',
'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles',
'TA_PERF_SEL_sh_fifo_data_tfifo_busy',
'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles',
'TA_PERF_SEL_sp_ta_addr_cycles', 'TA_PERF_SEL_sp_ta_data_cycles',
'TA_PERF_SEL_sq_ta_cmd_cycles', 'TA_PERF_SEL_ta_busy',
'TA_PERF_SEL_ta_fa_data_state_cycles',
'TA_PERF_SEL_ta_sh_fifo_starved', 'TA_PERF_SEL_total_wavefronts',
'TA_PERF_SEL_vol_1_cycle_pixels',
'TA_PERF_SEL_vol_2_cycle_pixels', 'TA_PERF_SEL_walker_cycles',
'TA_PERF_SEL_write_path_busy',
'TA_PERF_SEL_write_path_input_cycles',
'TA_PERF_SEL_write_path_output_cycles',
'TA_PERF_SEL_xnack_on_phase0', 'TA_PERF_SEL_xnack_on_phase1',
'TA_PERF_SEL_xnack_on_phase2', 'TA_PERF_SEL_xnack_on_phase3',
'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR',
'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1',
'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3',
'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED',
'TA_TC_REQ_MODES', 'TA_TC_REQ_MODE_BORDER', 'TA_TC_REQ_MODE_BYTE',
'TA_TC_REQ_MODE_BYTE_NV', 'TA_TC_REQ_MODE_DWORD',
'TA_TC_REQ_MODE_NORMAL', 'TA_TC_REQ_MODE_TEX0',
'TA_TC_REQ_MODE_TEX1', 'TA_TC_REQ_MODE_TEX2',
'TCC_CACHE_POLICIES', 'TCC_CACHE_POLICY_LRU',
'TCC_CACHE_POLICY_STREAM', 'TCC_MTYPE', 'TCP_CACHE_POLICIES',
'TCP_CACHE_POLICY_HIT_EVICT', 'TCP_CACHE_POLICY_HIT_LRU',
'TCP_CACHE_POLICY_MISS_EVICT', 'TCP_CACHE_POLICY_MISS_LRU',
'TCP_CACHE_STORE_POLICIES', 'TCP_CACHE_STORE_POLICY_WT_EVICT',
'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_DSM_DATA_SEL',
'TCP_DSM_DISABLE', 'TCP_DSM_INJECT_SEL', 'TCP_DSM_INJECT_SEL0',
'TCP_DSM_INJECT_SEL1', 'TCP_DSM_INJECT_SEL2',
'TCP_DSM_INJECT_SEL3', 'TCP_DSM_SEL0', 'TCP_DSM_SEL1',
'TCP_DSM_SEL_BOTH', 'TCP_DSM_SINGLE_WRITE',
'TCP_DSM_SINGLE_WRITE_DIS', 'TCP_DSM_SINGLE_WRITE_EN',
'TCP_OPCODE_ATOMIC', 'TCP_OPCODE_ATOMIC_CMPSWAP',
'TCP_OPCODE_GATHERH', 'TCP_OPCODE_READ', 'TCP_OPCODE_TYPE',
'TCP_OPCODE_WBINVL1', 'TCP_OPCODE_WRITE', 'TCP_PERFCOUNT_SELECT',
'TCP_PERF_SEL_ALLOC_STALL_CYCLES',
'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES',
'TCP_PERF_SEL_CLIENT_UTCL0_INFLIGHT',
'TCP_PERF_SEL_CORE_REG_SCLK_VLD',
'TCP_PERF_SEL_CP_TCP_INVALIDATE', 'TCP_PERF_SEL_GATE_EN1',
'TCP_PERF_SEL_GATE_EN2',
'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET',
'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET',
'TCP_PERF_SEL_GL1_REQ_READ', 'TCP_PERF_SEL_GL1_REQ_READ_LATENCY',
'TCP_PERF_SEL_GL1_REQ_WRITE',
'TCP_PERF_SEL_GL1_REQ_WRITE_LATENCY',
'TCP_PERF_SEL_HOLE_READ_STALL', 'TCP_PERF_SEL_LFIFO_STALL_CYCLES',
'TCP_PERF_SEL_LOD_STALL_CYCLES',
'TCP_PERF_SEL_PENDING_STALL_CYCLES', 'TCP_PERF_SEL_POWER_STALL',
'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES',
'TCP_PERF_SEL_READFIFO_STALL_CYCLES',
'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES',
'TCP_PERF_SEL_REQ_MISS_TAGRAM0', 'TCP_PERF_SEL_REQ_MISS_TAGRAM1',
'TCP_PERF_SEL_REQ_MISS_TAGRAM2', 'TCP_PERF_SEL_REQ_MISS_TAGRAM3',
'TCP_PERF_SEL_RFIFO_STALL_CYCLES', 'TCP_PERF_SEL_SHOOTDOWN',
'TCP_PERF_SEL_TAGRAM0_REQ', 'TCP_PERF_SEL_TAGRAM1_REQ',
'TCP_PERF_SEL_TAGRAM2_REQ', 'TCP_PERF_SEL_TAGRAM3_REQ',
'TCP_PERF_SEL_TA_REQ', 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET',
'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', 'TCP_PERF_SEL_TA_REQ_READ',
'TCP_PERF_SEL_TA_REQ_STATE_READ', 'TCP_PERF_SEL_TA_REQ_WRITE',
'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES',
'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES',
'TCP_PERF_SEL_TA_TCP_STATE_READ',
'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ',
'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ',
'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_CC_READ_REQ',
'TCP_PERF_SEL_TCC_CC_WRITE_REQ', 'TCP_PERF_SEL_TCC_DCC_REQ',
'TCP_PERF_SEL_TCC_LRU_REQ', 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ',
'TCP_PERF_SEL_TCC_NC_READ_REQ', 'TCP_PERF_SEL_TCC_NC_WRITE_REQ',
'TCP_PERF_SEL_TCC_READ_REQ', 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY',
'TCP_PERF_SEL_TCC_STREAM_REQ', 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ',
'TCP_PERF_SEL_TCC_UC_READ_REQ', 'TCP_PERF_SEL_TCC_UC_WRITE_REQ',
'TCP_PERF_SEL_TCC_WRITE_REQ',
'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY',
'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY', 'TCP_PERF_SEL_TCP_LATENCY',
'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES',
'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES',
'TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES',
'TCP_PERF_SEL_TCR_RDRET_STALL',
'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES',
'TCP_PERF_SEL_TC_TA_XNACK_STALL',
'TCP_PERF_SEL_TD_TCP_STALL_CYCLES', 'TCP_PERF_SEL_TOTAL_ACCESSES',
'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET',
'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET',
'TCP_PERF_SEL_TOTAL_CACHE_ACCESSES',
'TCP_PERF_SEL_TOTAL_HIT_LRU_READ',
'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ',
'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE',
'TCP_PERF_SEL_TOTAL_MISS_LRU_READ',
'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE',
'TCP_PERF_SEL_TOTAL_NON_READ', 'TCP_PERF_SEL_TOTAL_READ',
'TCP_PERF_SEL_TOTAL_WBINVL1', 'TCP_PERF_SEL_TOTAL_WRITE',
'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES',
'TCP_PERF_SEL_UNORDERED_MTYPE_STALL',
'TCP_PERF_SEL_UTCL0_LFIFO_FULL',
'TCP_PERF_SEL_UTCL0_PERMISSION_MISS',
'TCP_PERF_SEL_UTCL0_REQUEST',
'TCP_PERF_SEL_UTCL0_SERIALIZATION_STALL',
'TCP_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX',
'TCP_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES',
'TCP_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT',
'TCP_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL',
'TCP_PERF_SEL_UTCL0_STALL_MULTI_MISS',
'TCP_PERF_SEL_UTCL0_STALL_UTCL2_REQ_OUT_OF_CREDITS',
'TCP_PERF_SEL_UTCL0_TRANSLATION_HIT',
'TCP_PERF_SEL_UTCL0_TRANSLATION_MISS',
'TCP_PERF_SEL_UTCL0_UTCL2_INFLIGHT',
'TCP_PERF_SEL_WRITE_CONFLICT_STALL',
'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES', 'TCP_WATCH_MODES',
'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC',
'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', 'TC_EA_CID',
'TC_EA_CID_CPF', 'TC_EA_CID_CPG', 'TC_EA_CID_DCC',
'TC_EA_CID_FMASK', 'TC_EA_CID_HTILE', 'TC_EA_CID_IA',
'TC_EA_CID_MISC', 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC',
'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA',
'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z',
'TC_MICRO_TILE_MODE', 'TC_NACKS', 'TC_NACK_DATA_ERROR',
'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT',
'TC_NACK_PROTECTION_FAULT', 'TC_ONLY', 'TC_OP',
'TC_OP_ATOMIC_ADD_32', 'TC_OP_ATOMIC_ADD_64',
'TC_OP_ATOMIC_ADD_RTN_32', 'TC_OP_ATOMIC_ADD_RTN_64',
'TC_OP_ATOMIC_AND_32', 'TC_OP_ATOMIC_AND_64',
'TC_OP_ATOMIC_AND_RTN_32', 'TC_OP_ATOMIC_AND_RTN_64',
'TC_OP_ATOMIC_CMPSWAP_32', 'TC_OP_ATOMIC_CMPSWAP_64',
'TC_OP_ATOMIC_CMPSWAP_RTN_32', 'TC_OP_ATOMIC_CMPSWAP_RTN_64',
'TC_OP_ATOMIC_DEC_32', 'TC_OP_ATOMIC_DEC_64',
'TC_OP_ATOMIC_DEC_RTN_32', 'TC_OP_ATOMIC_DEC_RTN_64',
'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64',
'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32',
'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64',
'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32',
'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64',
'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64',
'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64',
'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32',
'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64',
'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32',
'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64',
'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64',
'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64',
'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32',
'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64',
'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32',
'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64',
'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64',
'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64',
'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64',
'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64',
'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64',
'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64',
'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64',
'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64',
'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64',
'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64',
'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64',
'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64',
'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64',
'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64',
'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64',
'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64',
'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64',
'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64',
'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64',
'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS',
'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN',
'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER',
'TC_OP_READ', 'TC_OP_RESERVED_FOP_32_0',
'TC_OP_RESERVED_FOP_32_1', 'TC_OP_RESERVED_FOP_32_2',
'TC_OP_RESERVED_FOP_64_0', 'TC_OP_RESERVED_FOP_64_1',
'TC_OP_RESERVED_FOP_64_2', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1',
'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_1',
'TC_OP_RESERVED_FOP_RTN_32_2', 'TC_OP_RESERVED_FOP_RTN_64_0',
'TC_OP_RESERVED_FOP_RTN_64_1', 'TC_OP_RESERVED_FOP_RTN_64_2',
'TC_OP_RESERVED_NON_FLOAT_32_1', 'TC_OP_RESERVED_NON_FLOAT_32_2',
'TC_OP_RESERVED_NON_FLOAT_32_3', 'TC_OP_RESERVED_NON_FLOAT_32_4',
'TC_OP_RESERVED_NON_FLOAT_64_1', 'TC_OP_RESERVED_NON_FLOAT_64_2',
'TC_OP_RESERVED_NON_FLOAT_64_3', 'TC_OP_RESERVED_NON_FLOAT_64_4',
'TC_OP_RESERVED_NON_FLOAT_RTN_32_0',
'TC_OP_RESERVED_NON_FLOAT_RTN_32_1',
'TC_OP_RESERVED_NON_FLOAT_RTN_32_2',
'TC_OP_RESERVED_NON_FLOAT_RTN_32_3',
'TC_OP_RESERVED_NON_FLOAT_RTN_64_1',
'TC_OP_RESERVED_NON_FLOAT_RTN_64_2',
'TC_OP_RESERVED_NON_FLOAT_RTN_64_3',
'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1',
'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2',
'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC',
'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL',
'TD_PERF_SEL_RESERVED_21', 'TD_PERF_SEL_RESERVED_8',
'TD_PERF_SEL_address_cmd_poison',
'TD_PERF_SEL_bypassLerp_wavefront',
'TD_PERF_SEL_core_state_rams_read',
'TD_PERF_SEL_d16_en_wavefront', 'TD_PERF_SEL_data_poison',
'TD_PERF_SEL_done_scoreboard_bp_due_to_lds',
'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo',
'TD_PERF_SEL_done_scoreboard_is_full',
'TD_PERF_SEL_done_scoreboard_not_empty',
'TD_PERF_SEL_four_comp_wavefront',
'TD_PERF_SEL_gather4_wavefront',
'TD_PERF_SEL_gather4h_packed_wavefront',
'TD_PERF_SEL_gather4h_wavefront',
'TD_PERF_SEL_gather8h_packed_wavefront', 'TD_PERF_SEL_input_busy',
'TD_PERF_SEL_input_state_fifo_full',
'TD_PERF_SEL_ldfptr_wavefront', 'TD_PERF_SEL_lds_stall',
'TD_PERF_SEL_load_wavefront', 'TD_PERF_SEL_lod_warn_from_ta',
'TD_PERF_SEL_min_max_filter_wavefront',
'TD_PERF_SEL_mixmode_instruction', 'TD_PERF_SEL_mixmode_resource',
'TD_PERF_SEL_nofilter_busy',
'TD_PERF_SEL_nofilter_formatters_turned_off',
'TD_PERF_SEL_nofilter_pkr_full',
'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt',
'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt',
'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off',
'TD_PERF_SEL_none', 'TD_PERF_SEL_one_comp_wavefront',
'TD_PERF_SEL_opaque_black_border',
'TD_PERF_SEL_out_of_order_instr',
'TD_PERF_SEL_reference_data_rams_read',
'TD_PERF_SEL_sample_c_wavefront', 'TD_PERF_SEL_sampler_lerp_busy',
'TD_PERF_SEL_sampler_out_busy', 'TD_PERF_SEL_sampler_pkr_full',
'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off',
'TD_PERF_SEL_status_packet', 'TD_PERF_SEL_store_wavefront',
'TD_PERF_SEL_ta_data_stall',
'TD_PERF_SEL_tc_cycling_of_nofilter_instr',
'TD_PERF_SEL_tc_data_stall', 'TD_PERF_SEL_tc_ram_stall',
'TD_PERF_SEL_tc_td_data_fifo_full',
'TD_PERF_SEL_tc_td_ram_fifo_full', 'TD_PERF_SEL_td_busy',
'TD_PERF_SEL_td_cycling_of_nofilter_instr',
'TD_PERF_SEL_three_comp_wavefront', 'TD_PERF_SEL_total_num_instr',
'TD_PERF_SEL_two_comp_wavefront',
'TD_PERF_SEL_user_defined_border',
'TD_PERF_SEL_wavefront_dest_is_lds',
'TD_PERF_SEL_weight_data_rams_read', 'TD_PERF_SEL_white_border',
'TD_PERF_SEL_write_ack_wavefront', 'TESS_ISOLINE', 'TESS_QUAD',
'TESS_TRIANGLE', 'TEST_CLK_DIV_SEL', 'TEST_CLK_SEL',
'TEST_CLK_SEL_0', 'TEST_CLK_SEL_1', 'TEST_CLK_SEL_2',
'TEST_CLK_SEL_3', 'TEST_CLK_SEL_4', 'TEST_CLK_SEL_5',
'TEST_CLK_SEL_6', 'TEST_CLK_SEL_7', 'TEST_CLK_SEL_8',
'TEST_CLOCK_MUX_SELECT_DISPCLK_G',
'TEST_CLOCK_MUX_SELECT_DISPCLK_P',
'TEST_CLOCK_MUX_SELECT_DISPCLK_R',
'TEST_CLOCK_MUX_SELECT_DSCCLK_G',
'TEST_CLOCK_MUX_SELECT_DSCCLK_P',
'TEST_CLOCK_MUX_SELECT_DSCCLK_R', 'TEST_CLOCK_MUX_SELECT_ENUM',
'TEX_BC_SWIZZLE', 'TEX_BC_Swizzle_WXYZ', 'TEX_BC_Swizzle_WZYX',
'TEX_BC_Swizzle_XWYZ', 'TEX_BC_Swizzle_XYZW',
'TEX_BC_Swizzle_YXWZ', 'TEX_BC_Swizzle_ZYXW',
'TEX_BORDER_COLOR_TYPE', 'TEX_BorderColor_OpaqueBlack',
'TEX_BorderColor_OpaqueWhite', 'TEX_BorderColor_Register',
'TEX_BorderColor_TransparentBlack', 'TEX_CHROMA_KEY', 'TEX_CLAMP',
'TEX_COORD_TYPE', 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled',
'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3',
'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder',
'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror',
'TEX_Clamp_MirrorOnceHalfToBorder',
'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast',
'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized',
'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION',
'TEX_DIM', 'TEX_DepthCompareFunction_Always',
'TEX_DepthCompareFunction_Equal',
'TEX_DepthCompareFunction_Greater',
'TEX_DepthCompareFunction_GreaterEqual',
'TEX_DepthCompareFunction_Less',
'TEX_DepthCompareFunction_LessEqual',
'TEX_DepthCompareFunction_Never',
'TEX_DepthCompareFunction_NotEqual', 'TEX_Dim_1D',
'TEX_Dim_1DArray', 'TEX_Dim_2D', 'TEX_Dim_2DArray',
'TEX_Dim_2DArray_MSAA', 'TEX_Dim_2D_MSAA', 'TEX_Dim_3D',
'TEX_Dim_CubeMap', 'TEX_FORMAT_COMP', 'TEX_FormatComp_RESERVED_3',
'TEX_FormatComp_Signed', 'TEX_FormatComp_Unsigned',
'TEX_FormatComp_UnsignedBiased', 'TEX_MAX_ANISO_RATIO',
'TEX_MIP_FILTER', 'TEX_MaxAnisoRatio_16to1',
'TEX_MaxAnisoRatio_1to1', 'TEX_MaxAnisoRatio_2to1',
'TEX_MaxAnisoRatio_4to1', 'TEX_MaxAnisoRatio_8to1',
'TEX_MaxAnisoRatio_RESERVED_5', 'TEX_MaxAnisoRatio_RESERVED_6',
'TEX_MaxAnisoRatio_RESERVED_7', 'TEX_MipFilter_Linear',
'TEX_MipFilter_None', 'TEX_MipFilter_Point',
'TEX_MipFilter_Point_Aniso_Adj', 'TEX_REQUEST_SIZE',
'TEX_RequestSize_128B', 'TEX_RequestSize_2X64B',
'TEX_RequestSize_32B', 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE',
'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid',
'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint',
'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER',
'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point',
'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER',
'THICK_MICRO_TILING', 'THIN_MICRO_TILING', 'THIRTY_TWO_PIPES',
'THREAD_TRACE_DRAW', 'THREAD_TRACE_FINISH', 'THREAD_TRACE_MARKER',
'THREAD_TRACE_START', 'THREAD_TRACE_STOP', 'TILE_SPLIT',
'TMDS_COLOR_FORMAT', 'TMDS_COLOR_FORMAT_DUAL30BPP',
'TMDS_COLOR_FORMAT_RESERVED', 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB',
'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP',
'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN',
'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0',
'TMDS_CTL0_DATA_MODULATION_BIT1',
'TMDS_CTL0_DATA_MODULATION_BIT2',
'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL',
'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED',
'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC',
'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC',
'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED',
'TMDS_CTL0_DATA_SEL8_RANDOM_DATA',
'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA',
'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN',
'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT',
'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION',
'TMDS_CTL1_DATA_MODULATION_BIT0',
'TMDS_CTL1_DATA_MODULATION_BIT1',
'TMDS_CTL1_DATA_MODULATION_BIT2',
'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL',
'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED',
'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC',
'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC',
'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED',
'TMDS_CTL1_DATA_SEL8_BLANK_TIME',
'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED',
'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN',
'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT',
'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION',
'TMDS_CTL2_DATA_MODULATION_BIT0',
'TMDS_CTL2_DATA_MODULATION_BIT1',
'TMDS_CTL2_DATA_MODULATION_BIT2',
'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL',
'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED',
'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC',
'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC',
'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED',
'TMDS_CTL2_DATA_SEL8_BLANK_TIME',
'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED',
'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN',
'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT',
'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION',
'TMDS_CTL3_DATA_MODULATION_BIT0',
'TMDS_CTL3_DATA_MODULATION_BIT1',
'TMDS_CTL3_DATA_MODULATION_BIT2',
'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL',
'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED',
'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC',
'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC',
'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED',
'TMDS_CTL3_DATA_SEL8_BLANK_TIME',
'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED',
'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN',
'TMDS_CTL3_PATTERN_OUT_ENABLE',
'TMDS_DATA_SYNCHRONIZATION_DSINTSEL',
'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS',
'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', 'TMDS_MUX_SELECT',
'TMDS_MUX_SELECT_B', 'TMDS_MUX_SELECT_G', 'TMDS_MUX_SELECT_R',
'TMDS_MUX_SELECT_RESERVED', 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START',
'TMDS_PIXEL_ENCODING', 'TMDS_PIXEL_ENCODING_422',
'TMDS_PIXEL_ENCODING_444_OR_420', 'TMDS_REG_TEST_OUTPUTA_CNTLA',
'TMDS_REG_TEST_OUTPUTA_CNTLA_NA',
'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0',
'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1',
'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2',
'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA',
'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0',
'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1',
'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0',
'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2',
'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG',
'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START',
'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT',
'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT',
'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT',
'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT',
'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA',
'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB',
'TMDS_TRANSMITTER_CONTROL_IDSCKSELA',
'TMDS_TRANSMITTER_CONTROL_IDSCKSELB',
'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN',
'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK',
'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN',
'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK',
'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS',
'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS',
'TMDS_TRANSMITTER_ENABLE_HPD_MASK',
'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK',
'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK',
'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE',
'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE',
'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE',
'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE',
'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON',
'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON',
'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK',
'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK',
'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK',
'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK',
'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE',
'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE',
'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE',
'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE',
'TMDS_TRANSMITTER_PLLSEL_BY_HW',
'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW',
'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD',
'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE',
'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE',
'TMDS_TRANSMITTER_PLL_RST_ON_HPD',
'TMDS_TRANSMITTER_TDCLK_FROM_PADS',
'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK',
'TMDS_TRANSMITTER_TMCLK_FROM_PADS',
'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK',
'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES',
'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES',
'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES',
'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS',
'TRISTRIP', 'TVX_DATA_FORMAT', 'TVX_DST_SEL', 'TVX_DstSel_0f',
'TVX_DstSel_1f', 'TVX_DstSel_Mask', 'TVX_DstSel_RESERVED_6',
'TVX_DstSel_W', 'TVX_DstSel_X', 'TVX_DstSel_Y', 'TVX_DstSel_Z',
'TVX_ENDIAN_SWAP', 'TVX_EndianSwap_8in16', 'TVX_EndianSwap_8in32',
'TVX_EndianSwap_8in64', 'TVX_EndianSwap_None', 'TVX_FMT_1',
'TVX_FMT_10_10_10_2', 'TVX_FMT_10_11_11',
'TVX_FMT_10_11_11_FLOAT', 'TVX_FMT_11_11_10',
'TVX_FMT_11_11_10_FLOAT', 'TVX_FMT_16', 'TVX_FMT_16_16',
'TVX_FMT_16_16_16', 'TVX_FMT_16_16_16_16',
'TVX_FMT_16_16_16_16_FLOAT', 'TVX_FMT_16_16_16_FLOAT',
'TVX_FMT_16_16_FLOAT', 'TVX_FMT_16_FLOAT', 'TVX_FMT_1_5_5_5',
'TVX_FMT_1_REVERSED', 'TVX_FMT_24_8', 'TVX_FMT_24_8_FLOAT',
'TVX_FMT_2_10_10_10', 'TVX_FMT_32', 'TVX_FMT_32_32',
'TVX_FMT_32_32_32', 'TVX_FMT_32_32_32_32',
'TVX_FMT_32_32_32_32_FLOAT', 'TVX_FMT_32_32_32_FLOAT',
'TVX_FMT_32_32_FLOAT', 'TVX_FMT_32_AS_8', 'TVX_FMT_32_AS_8_8',
'TVX_FMT_32_FLOAT', 'TVX_FMT_3_3_2', 'TVX_FMT_4_4',
'TVX_FMT_4_4_4_4', 'TVX_FMT_5_5_5_1', 'TVX_FMT_5_6_5',
'TVX_FMT_5_9_9_9_SHAREDEXP', 'TVX_FMT_6_5_5', 'TVX_FMT_8',
'TVX_FMT_8_24', 'TVX_FMT_8_24_FLOAT', 'TVX_FMT_8_8',
'TVX_FMT_8_8_8', 'TVX_FMT_8_8_8_8', 'TVX_FMT_APC0',
'TVX_FMT_APC1', 'TVX_FMT_APC2', 'TVX_FMT_APC3', 'TVX_FMT_APC4',
'TVX_FMT_APC5', 'TVX_FMT_APC6', 'TVX_FMT_APC7', 'TVX_FMT_BC1',
'TVX_FMT_BC2', 'TVX_FMT_BC3', 'TVX_FMT_BC4', 'TVX_FMT_BC5',
'TVX_FMT_BG_RG', 'TVX_FMT_CTX1', 'TVX_FMT_GB_GR',
'TVX_FMT_INVALID', 'TVX_FMT_RESERVED_33', 'TVX_FMT_RESERVED_36',
'TVX_FMT_RESERVED_4', 'TVX_FMT_RESERVED_63',
'TVX_FMT_X24_8_32_FLOAT', 'TVX_INST', 'TVX_Inst_Gather4',
'TVX_Inst_Gather4_C', 'TVX_Inst_Gather4_C_O',
'TVX_Inst_Gather4_O', 'TVX_Inst_GetBufferResInfo',
'TVX_Inst_GetGradientsH', 'TVX_Inst_GetGradientsV',
'TVX_Inst_GetLOD', 'TVX_Inst_GetNumberOfSamples',
'TVX_Inst_GetTextureResInfo', 'TVX_Inst_KeepGradients',
'TVX_Inst_LD', 'TVX_Inst_NormalVertexFetch', 'TVX_Inst_Pass',
'TVX_Inst_RESERVED_15', 'TVX_Inst_RESERVED_2', 'TVX_Inst_Sample',
'TVX_Inst_Sample_C', 'TVX_Inst_Sample_C_G',
'TVX_Inst_Sample_C_G_LB', 'TVX_Inst_Sample_C_L',
'TVX_Inst_Sample_C_LB', 'TVX_Inst_Sample_C_LZ',
'TVX_Inst_Sample_G', 'TVX_Inst_Sample_G_LB', 'TVX_Inst_Sample_L',
'TVX_Inst_Sample_LB', 'TVX_Inst_Sample_LZ',
'TVX_Inst_SemanticVertexFetch', 'TVX_Inst_SetGradientsH',
'TVX_Inst_SetGradientsV', 'TVX_Inst_SetTextureOffsets',
'TVX_NUM_FORMAT_ALL', 'TVX_NumFormatAll_Int',
'TVX_NumFormatAll_Norm', 'TVX_NumFormatAll_RESERVED_3',
'TVX_NumFormatAll_Scaled', 'TVX_SRC_SEL', 'TVX_SRFModeAll_NZ',
'TVX_SRFModeAll_ZCMO', 'TVX_SRF_MODE_ALL', 'TVX_SrcSel_0f',
'TVX_SrcSel_1f', 'TVX_SrcSel_W', 'TVX_SrcSel_X', 'TVX_SrcSel_Y',
'TVX_SrcSel_Z', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource',
'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource',
'TVX_Type_ValidVertexBuffer', 'TWO_BANKS', 'TWO_FRAGMENTS',
'TWO_PIPES', 'TWO_RB_PER_SE', 'TWO_SHADER_ENGINS', 'TileSplit',
'TileType', 'UCONFIG_SPACE_END', 'UCONFIG_SPACE_START',
'UNCACHED_RD', 'UNCACHED_WR', 'UNDEF', 'UNSIGNED',
'UTCL0FaultType', 'UTCL0RequestType', 'UTCL0_TYPE_BYPASS',
'UTCL0_TYPE_NORMAL', 'UTCL0_TYPE_SHOOTDOWN',
'UTCL0_XNACK_NO_RETRY', 'UTCL0_XNACK_PRT', 'UTCL0_XNACK_RETRY',
'UTCL0_XNACK_SUCCESS', 'UTCL1FaultType', 'UTCL1PerfSel',
'UTCL1RequestType', 'UTCL1_PERF_SEL_BYPASS_REQS',
'UTCL1_PERF_SEL_HITS', 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS',
'UTCL1_PERF_SEL_MISSES', 'UTCL1_PERF_SEL_NONE',
'UTCL1_PERF_SEL_NONRANGE_INV_REQS',
'UTCL1_PERF_SEL_NUM_BIGK_PAGES',
'UTCL1_PERF_SEL_NUM_SMALLK_PAGES',
'UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM',
'UTCL1_PERF_SEL_RANGE_INV_REQS', 'UTCL1_PERF_SEL_REQS',
'UTCL1_PERF_SEL_STALL_MH_CAM_FULL',
'UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL',
'UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS',
'UTCL1_PERF_SEL_TOTAL_UTCL2_REQS', 'UTCL1_TYPE_BYPASS',
'UTCL1_TYPE_NORMAL', 'UTCL1_TYPE_SHOOTDOWN',
'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', 'UTCL1_XNACK_RETRY',
'UTCL1_XNACK_SUCCESS', 'UVDFC_BITSTREAM_ADDR',
'UVDFC_BITSTREAM_SIZE', 'UVDFC_DECODED_ADDR',
'UVDFC_DISPLAY_ADDR', 'UVDFC_DISPLAY_PITCH',
'UVDFC_DISPLAY_TILING', 'UVDFC_EOD', 'UVDFC_FENCE',
'UVDFC_ITBUF_ADDR', 'UVDFC_MBLOCK_ADDR', 'UVDFC_TRAP',
'UVDFirmwareCommand', 'VC_AND_TC', 'VC_ONLY',
'VGT_CACHE_INVALID_MODE', 'VGT_DETECT_ONE', 'VGT_DETECT_ZERO',
'VGT_DIST_MODE', 'VGT_DI_INDEX_SIZE', 'VGT_DI_MAJOR_MODE_SELECT',
'VGT_DI_PRIM_TYPE', 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM',
'VGT_DMA_BUF_RING', 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE',
'VGT_DMA_PTR_UPDATE', 'VGT_DMA_SWAP_16_BIT',
'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', 'VGT_DMA_SWAP_NONE',
'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', 'VGT_FLUSH',
'VGT_GROUP_CONV_SEL', 'VGT_GRP_2D_COPY_RECT_V0',
'VGT_GRP_2D_COPY_RECT_V1', 'VGT_GRP_2D_COPY_RECT_V2',
'VGT_GRP_2D_COPY_RECT_V3', 'VGT_GRP_2D_FILL_RECT',
'VGT_GRP_2D_LINE', 'VGT_GRP_2D_RECT', 'VGT_GRP_2D_TRI',
'VGT_GRP_3D_LINE', 'VGT_GRP_3D_LINE_ADJ', 'VGT_GRP_3D_PATCH',
'VGT_GRP_3D_POINT', 'VGT_GRP_3D_QUAD', 'VGT_GRP_3D_RECT',
'VGT_GRP_3D_TRI', 'VGT_GRP_3D_TRI_ADJ', 'VGT_GRP_AUTO_PRIM',
'VGT_GRP_FAN', 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32',
'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_LIST',
'VGT_GRP_LOOP', 'VGT_GRP_POLYGON', 'VGT_GRP_PRIM_INDEX_LINE',
'VGT_GRP_PRIM_INDEX_QUAD', 'VGT_GRP_PRIM_INDEX_TRI',
'VGT_GRP_PRIM_ORDER', 'VGT_GRP_PRIM_TYPE', 'VGT_GRP_SINT_16',
'VGT_GRP_SINT_32', 'VGT_GRP_STRIP', 'VGT_GRP_UINT_16',
'VGT_GRP_UINT_32', 'VGT_GS_CUT_MODE', 'VGT_GS_MODE_TYPE',
'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', 'VGT_INDEX_32',
'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', 'VGT_OUTPATH_GS_BLOCK',
'VGT_OUTPATH_HS_BLOCK', 'VGT_OUTPATH_PRIM_GEN',
'VGT_OUTPATH_SELECT', 'VGT_OUTPATH_TE_GS_BLOCK',
'VGT_OUTPATH_TE_OUTPUT', 'VGT_OUTPATH_TE_PRIM_GEN',
'VGT_OUTPATH_VTX_REUSE', 'VGT_OUT_2D_RECT', 'VGT_OUT_LINE',
'VGT_OUT_LINE_ADJ', 'VGT_OUT_PATCH', 'VGT_OUT_POINT',
'VGT_OUT_PRIM_TYPE', 'VGT_OUT_RECT_V0', 'VGT_OUT_RECT_V1',
'VGT_OUT_RECT_V2', 'VGT_OUT_RECT_V3', 'VGT_OUT_TRI',
'VGT_OUT_TRI_ADJ', 'VGT_POLICY_BYPASS', 'VGT_POLICY_LRU',
'VGT_POLICY_STREAM', 'VGT_RDREQ_POLICY', 'VGT_STAGES_ES_EN',
'VGT_STAGES_GS_EN', 'VGT_STAGES_HS_EN', 'VGT_STAGES_LS_EN',
'VGT_STAGES_VS_EN', 'VGT_STREAMOUT_RESET', 'VGT_STREAMOUT_SYNC',
'VGT_TESS_PARTITION', 'VGT_TESS_TOPOLOGY', 'VGT_TESS_TYPE',
'VGT_TE_PRIM_INDEX_LINE', 'VGT_TE_PRIM_INDEX_QUAD',
'VGT_TE_PRIM_INDEX_TRI', 'VGT_TE_QUAD', 'VID_ENHANCED_MODE',
'VID_NORMAL_FRAME_MODE', 'VID_STREAM_DISABLE_MASKED',
'VID_STREAM_DISABLE_UNMASK', 'VMEMCMD_RETURN_IN_ORDER',
'VMEMCMD_RETURN_IN_ORDER_READ', 'VMEMCMD_RETURN_ORDER',
'VMEMCMD_RETURN_OUT_OF_ORDER', 'VMID_SZ', 'VMPG_SIZE',
'VMPG_SIZE_4KB', 'VMPG_SIZE_64KB', 'VREADY_AT_OR_AFTER_VSYNC',
'VREADY_BEFORE_VSYNC', 'VSYNC_CNT_LATCH_MASK',
'VSYNC_CNT_LATCH_MASK_0', 'VSYNC_CNT_LATCH_MASK_1',
'VSYNC_CNT_REFCLK_SEL', 'VSYNC_CNT_REFCLK_SEL_0',
'VSYNC_CNT_REFCLK_SEL_1', 'VSYNC_CNT_RESET_SEL',
'VSYNC_CNT_RESET_SEL_0', 'VSYNC_CNT_RESET_SEL_1',
'VS_PARTIAL_FLUSH', 'VS_PS', 'VS_STAGE_COPY_SHADER',
'VS_STAGE_DS', 'VS_STAGE_REAL', 'VTG_SEL_0', 'VTG_SEL_1',
'VTG_SEL_2', 'VTG_SEL_3', 'VTG_SEL_4', 'VTG_SEL_5', 'VTX_CLAMP',
'VTX_Clamp_ClampToNAN', 'VTX_Clamp_ClampToZero', 'VTX_FETCH_TYPE',
'VTX_FORMAT_COMP_ALL', 'VTX_FetchType_InstanceData',
'VTX_FetchType_NoIndexOffset', 'VTX_FetchType_RESERVED_3',
'VTX_FetchType_VertexData', 'VTX_FormatCompAll_Signed',
'VTX_FormatCompAll_Unsigned', 'VTX_MEM_REQUEST_SIZE',
'VTX_MemRequestSize_32B', 'VTX_MemRequestSize_64B',
'WBSCL_BACKPRESSURE_CNT_DISABLE', 'WBSCL_BACKPRESSURE_CNT_ENABLE',
'WBSCL_BACKPRESSURE_CNT_EN_ENUM', 'WBSCL_COEF_CHROMA_HORZ_FILTER',
'WBSCL_COEF_CHROMA_VERT_FILTER', 'WBSCL_COEF_FILTER_TYPE_SEL',
'WBSCL_COEF_LUMA_HORZ_FILTER', 'WBSCL_COEF_LUMA_VERT_FILTER',
'WBSCL_COEF_RAM_FILTER_TYPE_ENUM',
'WBSCL_COEF_RAM_FILTER_TYPE_HC', 'WBSCL_COEF_RAM_FILTER_TYPE_HL',
'WBSCL_COEF_RAM_FILTER_TYPE_VC', 'WBSCL_COEF_RAM_FILTER_TYPE_VL',
'WBSCL_COEF_RAM_PHASE0', 'WBSCL_COEF_RAM_PHASE1',
'WBSCL_COEF_RAM_PHASE2', 'WBSCL_COEF_RAM_PHASE3',
'WBSCL_COEF_RAM_PHASE4', 'WBSCL_COEF_RAM_PHASE5',
'WBSCL_COEF_RAM_PHASE6', 'WBSCL_COEF_RAM_PHASE7',
'WBSCL_COEF_RAM_PHASE8', 'WBSCL_COEF_RAM_PHASE_ENUM',
'WBSCL_COEF_RAM_RD_SEL_0', 'WBSCL_COEF_RAM_RD_SEL_1',
'WBSCL_COEF_RAM_RD_SEL_ENUM', 'WBSCL_COEF_RAM_SEL_0',
'WBSCL_COEF_RAM_SEL_1', 'WBSCL_COEF_RAM_SEL_ENUM',
'WBSCL_COEF_RAM_TAP_COEF_DISABLE',
'WBSCL_COEF_RAM_TAP_COEF_ENABLE',
'WBSCL_COEF_RAM_TAP_COEF_EN_ENUM', 'WBSCL_COEF_RAM_TAP_PAIR_IDX0',
'WBSCL_COEF_RAM_TAP_PAIR_IDX1', 'WBSCL_COEF_RAM_TAP_PAIR_IDX2',
'WBSCL_COEF_RAM_TAP_PAIR_IDX3', 'WBSCL_COEF_RAM_TAP_PAIR_IDX4',
'WBSCL_COEF_RAM_TAP_PAIR_IDX5',
'WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM',
'WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM',
'WBSCL_DATA_OVERFLOW_INT_TYPE_HW',
'WBSCL_DATA_OVERFLOW_INT_TYPE_REG',
'WBSCL_HOST_CONFLICT_INT_TYPE_ENUM',
'WBSCL_HOST_CONFLICT_INT_TYPE_HW',
'WBSCL_HOST_CONFLICT_INT_TYPE_REG', 'WBSCL_LB_MEM_PWR_FORCE_DS',
'WBSCL_LB_MEM_PWR_FORCE_ENUM', 'WBSCL_LB_MEM_PWR_FORCE_LS',
'WBSCL_LB_MEM_PWR_FORCE_NO', 'WBSCL_LB_MEM_PWR_FORCE_SD',
'WBSCL_LB_MEM_PWR_MODE_SEL_DS', 'WBSCL_LB_MEM_PWR_MODE_SEL_ENUM',
'WBSCL_LB_MEM_PWR_MODE_SEL_LS', 'WBSCL_LB_MEM_PWR_MODE_SEL_ON',
'WBSCL_LB_MEM_PWR_MODE_SEL_SD', 'WBSCL_LUT_MEM_PWR_STATE_ENUM',
'WBSCL_LUT_MEM_PWR_STATE_LS', 'WBSCL_LUT_MEM_PWR_STATE_ON',
'WBSCL_LUT_MEM_PWR_STATE_RESERVED2',
'WBSCL_LUT_MEM_PWR_STATE_RESERVED3', 'WBSCL_MEM_PWR_STATE_DS',
'WBSCL_MEM_PWR_STATE_ENUM', 'WBSCL_MEM_PWR_STATE_LS',
'WBSCL_MEM_PWR_STATE_ON', 'WBSCL_MEM_PWR_STATE_SD',
'WBSCL_MODE_SCALING_444_BYPASS',
'WBSCL_MODE_SCALING_444_RGB_ENABLE',
'WBSCL_MODE_SCALING_444_YCBCR_ENABLE',
'WBSCL_MODE_SCALING_YCBCR_ENABLE', 'WBSCL_MODE_SEL',
'WBSCL_NUM_OF_TAPS0', 'WBSCL_NUM_OF_TAPS1', 'WBSCL_NUM_OF_TAPS10',
'WBSCL_NUM_OF_TAPS11', 'WBSCL_NUM_OF_TAPS2', 'WBSCL_NUM_OF_TAPS3',
'WBSCL_NUM_OF_TAPS4', 'WBSCL_NUM_OF_TAPS5', 'WBSCL_NUM_OF_TAPS6',
'WBSCL_NUM_OF_TAPS7', 'WBSCL_NUM_OF_TAPS8', 'WBSCL_NUM_OF_TAPS9',
'WBSCL_NUM_OF_TAPS_ENUM', 'WBSCL_OUTSIDE_PIX_STRATEGY_BLACK',
'WBSCL_OUTSIDE_PIX_STRATEGY_EDGE',
'WBSCL_OUTSIDE_PIX_STRATEGY_ENUM', 'WBSCL_PIXEL_DEPTH',
'WBSCL_STATUS_ACK_CLR', 'WBSCL_STATUS_ACK_ENUM',
'WBSCL_STATUS_ACK_NCLR', 'WBSCL_STATUS_MASK_DISABLE',
'WBSCL_STATUS_MASK_ENABLE', 'WBSCL_STATUS_MASK_ENUM',
'WBSCL_TEST_CRC_CONT_DISABLE', 'WBSCL_TEST_CRC_CONT_ENABLE',
'WBSCL_TEST_CRC_CONT_EN_ENUM', 'WBSCL_TEST_CRC_DISABLE',
'WBSCL_TEST_CRC_ENABLE', 'WBSCL_TEST_CRC_EN_ENUM',
'WBSCL_TEST_CRC_MASKED', 'WBSCL_TEST_CRC_MASK_ENUM',
'WBSCL_TEST_CRC_UNMASKED', 'WB_CLK_GATE_DISABLE',
'WB_CLK_GATE_DIS_ENUM', 'WB_CLK_GATE_ENABLE', 'WB_ENABLE_ENUM',
'WB_EN_DISABLE', 'WB_EN_ENABLE', 'WB_MEM_PWR_DISABLE',
'WB_MEM_PWR_DIS_ENUM', 'WB_MEM_PWR_ENABLE',
'WB_RAM_PW_SAVE_MODE_ENUM', 'WB_RAM_PW_SAVE_MODE_LS',
'WB_RAM_PW_SAVE_MODE_SD', 'WB_SOFT_RESET_ENUM',
'WB_SOFT_RESET_NEG', 'WB_SOFT_RESET_POS', 'WB_TEST_CLK_SEL_ENUM',
'WB_TEST_CLK_SEL_PERM', 'WB_TEST_CLK_SEL_REG',
'WB_TEST_CLK_SEL_WB', 'WB_TEST_CLK_SEL_WBSCL',
'WD_IA_DRAW_REG_XFER', 'WD_IA_DRAW_REG_XFER_GE_CNTL',
'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM',
'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID',
'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN',
'WD_IA_DRAW_SOURCE', 'WD_IA_DRAW_SOURCE_AUTO',
'WD_IA_DRAW_SOURCE_DMA', 'WD_IA_DRAW_SOURCE_IMMD',
'WD_IA_DRAW_SOURCE_OPAQ', 'WD_IA_DRAW_TYPE',
'WD_IA_DRAW_TYPE_DI_MM0', 'WD_IA_DRAW_TYPE_EVENT_ADDR',
'WD_IA_DRAW_TYPE_EVENT_INIT', 'WD_IA_DRAW_TYPE_IMM_DATA',
'WD_IA_DRAW_TYPE_INDX_OFF', 'WD_IA_DRAW_TYPE_MAX_INDX',
'WD_IA_DRAW_TYPE_MIN_INDX', 'WD_IA_DRAW_TYPE_REG_XFER',
'WRITE_BASE_ONLY', 'WRITE_BOTH', 'WritePolicy', 'XNORM',
'XNORM_A', 'XNORM_B', 'XTAL_REF_CLOCK_SOURCE_SEL',
'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK',
'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL',
'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'Y10_CbCr1010_420_PLANAR',
'Y10_CrCb1010_420_PLANAR', 'Y12_CbCr1212_420_PLANAR',
'Y12_CrCb1212_420_PLANAR', 'Y8_CbCr88_420_PLANAR',
'Y8_CrCb88_420_PLANAR', 'YCbYCr10101010_422_PACKED',
'YCbYCr12121212_422_PACKED', 'YCbYCr8888_422_PACKED',
'YCrCbA16161616_10LSB', 'YCrCbA16161616_10MSB',
'YCrCbA16161616_12LSB', 'YCrCbA16161616_12MSB', 'YCrCbA8888',
'YCrYCb10101010_422_PACKED', 'YCrYCb12121212_422_PACKED',
'YCrYCb8888_422_PACKED', 'Y_G_DATA_ON_ALPHA_PORT',
'Y_G_DATA_ON_CB_B_PORT', 'Y_G_DATA_ON_CR_R_PORT',
'Y_G_DATA_ON_Y_G_PORT', 'ZFormat', 'ZLimitSumm', 'ZModeForce',
'ZOrder', 'ZPASS_DISABLE', 'ZPASS_DONE', 'ZPASS_PIXELS',
'ZPASS_SAMPLES', 'ZSamplePosition', 'Z_16', 'Z_24', 'Z_32_FLOAT',
'Z_INVALID', 'Z_SAMPLE_CENTER', 'Z_SAMPLE_CENTROID',
'ZpassControl', '_navi10_ENUM_HEADER', 'ge_assembler_busy',
'ge_assembler_stalled', 'ge_cm_reading_stalled',
'ge_cm_stalled_by_gog', 'ge_cm_stalled_by_gsfetch_done',
'ge_dma_busy', 'ge_dma_lat_bin_0', 'ge_dma_lat_bin_1',
'ge_dma_lat_bin_2', 'ge_dma_lat_bin_3', 'ge_dma_lat_bin_4',
'ge_dma_lat_bin_5', 'ge_dma_lat_bin_6', 'ge_dma_lat_bin_7',
'ge_dma_return', 'ge_dma_utcl1_consecutive_retry_event',
'ge_dma_utcl1_request_event', 'ge_dma_utcl1_retry_event',
'ge_dma_utcl1_stall_event', 'ge_dma_utcl1_stall_utcl2_event',
'ge_dma_utcl1_translation_hit_event',
'ge_dma_utcl1_translation_miss_event',
'ge_dma_utcl2_stall_on_trans', 'ge_dma_utcl2_trans_ack',
'ge_dma_utcl2_trans_xnack', 'ge_ds_cache_hits', 'ge_ds_prims',
'ge_es_done', 'ge_es_done_latency', 'ge_es_flush',
'ge_es_ring_high_water_mark', 'ge_es_thread_groups',
'ge_esthread_stalled_es_rb_full', 'ge_esthread_stalled_spi_bp',
'ge_esvert_stalled_es_tbl', 'ge_esvert_stalled_gs_event',
'ge_esvert_stalled_gs_tbl', 'ge_esvert_stalled_gsprim',
'ge_gea_dma_starved', 'ge_gog_busy', 'ge_gog_out_indx_stalled',
'ge_gog_out_prim_stalled', 'ge_gog_vs_tbl_stalled',
'ge_gs_cache_hits', 'ge_gs_counters_avail_stalled', 'ge_gs_done',
'ge_gs_done_latency', 'ge_gs_event_stall',
'ge_gs_issue_rtr_stalled', 'ge_gs_rb_space_avail_stalled',
'ge_gs_ring_high_water_mark', 'ge_gsprim_stalled_es_tbl',
'ge_gsprim_stalled_esvert', 'ge_gsprim_stalled_gs_event',
'ge_gsprim_stalled_gs_tbl', 'ge_gsthread_stalled', 'ge_hs_done',
'ge_hs_done_latency', 'ge_hs_done_se0', 'ge_hs_done_se1',
'ge_hs_done_se2_reserved', 'ge_hs_done_se3_reserved',
'ge_hs_tfm_stall', 'ge_hs_tgs_active_high_water_mark',
'ge_hs_thread_groups', 'ge_inside_tf_bin_0', 'ge_inside_tf_bin_1',
'ge_inside_tf_bin_2', 'ge_inside_tf_bin_3', 'ge_inside_tf_bin_4',
'ge_inside_tf_bin_5', 'ge_inside_tf_bin_6', 'ge_inside_tf_bin_7',
'ge_inside_tf_bin_8', 'ge_ls_done', 'ge_ls_done_latency',
'ge_null_patch', 'ge_pa_clipp_eop', 'ge_pa_clipp_is_event',
'ge_pa_clipp_new_vtx_vect', 'ge_pa_clipp_null_prim',
'ge_pa_clipp_send', 'ge_pa_clipp_send_not_event',
'ge_pa_clipp_stalled', 'ge_pa_clipp_starved_busy',
'ge_pa_clipp_starved_idle', 'ge_pa_clipp_valid_prim',
'ge_pa_clips_send', 'ge_pa_clips_stalled', 'ge_pa_clipv_send',
'ge_pa_clipv_stalled', 'ge_rbiu_di_fifo_stalled',
'ge_rbiu_di_fifo_starved', 'ge_rbiu_dr_fifo_stalled',
'ge_rbiu_dr_fifo_starved', 'ge_reused_es_indices',
'ge_reused_vs_indices', 'ge_sclk_core_vld', 'ge_sclk_gs_vld',
'ge_sclk_input_vld', 'ge_sclk_leg_gs_arb_vld', 'ge_sclk_ngg_vld',
'ge_sclk_reg_vld', 'ge_sclk_te11_vld', 'ge_sclk_vr_vld',
'ge_sclk_wd_te11_vld', 'ge_spi_esvert_eov',
'ge_spi_esvert_stalled', 'ge_spi_esvert_starved_busy',
'ge_spi_esvert_valid', 'ge_spi_eswave_is_event',
'ge_spi_eswave_send', 'ge_spi_gsprim_cont', 'ge_spi_gsprim_eov',
'ge_spi_gsprim_stalled', 'ge_spi_gsprim_starved_busy',
'ge_spi_gsprim_starved_idle', 'ge_spi_gsprim_valid',
'ge_spi_gssubgrp_is_event', 'ge_spi_gssubgrp_send',
'ge_spi_gswave_is_event', 'ge_spi_gswave_send',
'ge_spi_hsvert_eov', 'ge_spi_hsvert_stalled',
'ge_spi_hsvert_starved_busy', 'ge_spi_hsvert_valid',
'ge_spi_hswave_is_event', 'ge_spi_hswave_send',
'ge_spi_lsvert_eov', 'ge_spi_lsvert_stalled',
'ge_spi_lsvert_starved_busy', 'ge_spi_lsvert_starved_idle',
'ge_spi_lsvert_valid', 'ge_spi_lswave_is_event',
'ge_spi_lswave_send', 'ge_spi_vsvert_eov', 'ge_spi_vsvert_send',
'ge_spi_vsvert_stalled', 'ge_spi_vsvert_starved_busy',
'ge_spi_vsvert_starved_idle', 'ge_spi_vswave_is_event',
'ge_spi_vswave_send', 'ge_starved_on_hs_done', 'ge_stat_busy',
'ge_stat_combined_busy', 'ge_stat_no_dma_busy',
'ge_strmout_stalled', 'ge_te11_busy', 'ge_te11_starved',
'ge_tfreq_lat_bin_0', 'ge_tfreq_lat_bin_1', 'ge_tfreq_lat_bin_2',
'ge_tfreq_lat_bin_3', 'ge_tfreq_lat_bin_4', 'ge_tfreq_lat_bin_5',
'ge_tfreq_lat_bin_6', 'ge_tfreq_lat_bin_7',
'ge_tfreq_utcl1_consecutive_retry_event',
'ge_tfreq_utcl1_request_event', 'ge_tfreq_utcl1_retry_event',
'ge_tfreq_utcl1_stall_event', 'ge_tfreq_utcl1_stall_utcl2_event',
'ge_tfreq_utcl1_translation_hit_event',
'ge_tfreq_utcl1_translation_miss_event',
'ge_tfreq_utcl2_stall_on_trans', 'ge_tfreq_utcl2_trans_ack',
'ge_tfreq_utcl2_trans_xnack', 'ge_vs_cache_hits', 'ge_vs_done',
'ge_vs_pc_stall', 'ge_vs_table_high_water_mark',
'ge_vs_thread_groups', 'ge_vsvert_api_send', 'ge_vsvert_ds_send',
'ge_wait_for_es_done_stalled', 'ge_waveid_stalled']