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openpilot is an open source driver assistance system. openpilot performs the functions of Automated Lane Centering and Adaptive Cruise Control for over 200 supported car makes and models.
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openpilot_comma/tinygrad_repo/tinygrad/runtime/autogen/am/soc24.py

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# mypy: ignore-errors
# -*- coding: utf-8 -*-
#
# TARGET arch is: []
# WORD_SIZE is: 8
# POINTER_SIZE is: 8
# LONGDOUBLE_SIZE is: 16
#
import ctypes
_soc24_ENUM_HEADER = True # macro
CSDATA_TYPE_WIDTH = 0x00000002 # macro
CSDATA_ADDR_WIDTH = 0x00000007 # macro
CSDATA_DATA_WIDTH = 0x00000020 # macro
CSCNTL_TYPE_WIDTH = 0x00000002 # macro
CSCNTL_ADDR_WIDTH = 0x00000007 # macro
CSCNTL_DATA_WIDTH = 0x00000020 # macro
GSTHREADID_SIZE = 0x00000002 # macro
IQ_QUEUE_SLEEP = 0x00000000 # macro
IQ_OFFLOAD_RETRY = 0x00000001 # macro
IQ_SCH_WAVE_MSG = 0x00000002 # macro
IQ_DEQUEUE_RETRY = 0x00000004 # macro
IQ_INTR_TYPE_PQ = 0x00000000 # macro
IQ_INTR_TYPE_IB = 0x00000001 # macro
IQ_INTR_TYPE_MQD = 0x00000002 # macro
VMID_SZ = 0x00000004 # macro
CONFIG_SPACE_START = 0x00002000 # macro
CONFIG_SPACE_END = 0x00009fff # macro
CONFIG_SPACE1_START = 0x00002000 # macro
CONFIG_SPACE1_END = 0x00002bff # macro
CONFIG_SPACE2_START = 0x00003000 # macro
CONFIG_SPACE2_END = 0x00009fff # macro
UCONFIG_SPACE_START = 0x0000c000 # macro
UCONFIG_SPACE_END = 0x0000ffff # macro
PERSISTENT_SPACE_START = 0x00002c00 # macro
PERSISTENT_SPACE_END = 0x00002fff # macro
CONTEXT_SPACE_START = 0x0000a000 # macro
CONTEXT_SPACE_END = 0x0000a3ff # macro
SQ_WAVE_TYPE_PS0 = 0x00000000 # macro
SQ_FLAT = 0x00000000 # macro
SQ_SCRATCH = 0x00000001 # macro
SQ_GLOBAL = 0x00000002 # macro
SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro
SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro
SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro
SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro
SQIND_WAVE_HW_REGS_OFFSET = 0x00000100 # macro
SQIND_WAVE_HW_REGS_SIZE = 0x00000040 # macro
SQIND_WAVE_HOST_REGS_OFFSET = 0x00000140 # macro
SQIND_WAVE_HOST_REGS_SIZE = 0x000000c0 # macro
SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro
SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro
SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro
SQIND_WAVE_VGPRS_SIZE = 0x00000400 # macro
SQ_GFXDEC_BEGIN = 0x0000a000 # macro
SQ_GFXDEC_END = 0x0000c000 # macro
SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro
SQDEC_BEGIN = 0x00002300 # macro
SQDEC_END = 0x000023ff # macro
PFVF_SQDEC_BEGIN = 0x0000a9e0 # macro
PFVF_SQDEC_END = 0x0000a9ff # macro
SQPERFSDEC_BEGIN = 0x0000d9c0 # macro
SQPERFSDEC_END = 0x0000da40 # macro
SQPERFDDEC_BEGIN = 0x0000d1c0 # macro
SQPERFDDEC_END = 0x0000d240 # macro
SQGFXUDEC_BEGIN = 0x0000c330 # macro
SQGFXUDEC_END = 0x0000c380 # macro
SQPWRDEC_BEGIN = 0x0000f08c # macro
SQPWRDEC_END = 0x0000f094 # macro
SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro
SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro
SQ_MAX_PGM_SGPRS = 0x00000068 # macro
SQ_MAX_PGM_VGPRS = 0x00000100 # macro
SQ_EX_EXCP_VALU_BASE = 0x00000000 # macro
SQ_EX_EXCP_VALU_SIZE = 0x00000007 # macro
SQ_EX_EXCP_ALU_INVALID = 0x00000000 # macro
SQ_EX_EXCP_ALU_INPUT_DENORM = 0x00000001 # macro
SQ_EX_EXCP_ALU_FLOAT_DIV0 = 0x00000002 # macro
SQ_EX_EXCP_ALU_OVERFLOW = 0x00000003 # macro
SQ_EX_EXCP_ALU_UNDERFLOW = 0x00000004 # macro
SQ_EX_EXCP_ALU_INEXACT = 0x00000005 # macro
SQ_EX_EXCP_ALU_INT_DIV0 = 0x00000006 # macro
SQ_EX_EXCP_ADDR_WATCH = 0x00000007 # macro
INST_ID_PRIV_START = 0x80000000 # macro
INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro
INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro
INST_ID_HW_TRAP = 0xfffffff2 # macro
INST_ID_KILL_SEQ = 0xfffffff3 # macro
INST_ID_SPI_WREXEC = 0xfffffff4 # macro
INST_ID_HW_TRAP_GET_TBA = 0xfffffff5 # macro
INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro
SIMM16_WAITCNT_EXP_CNT_START = 0x00000000 # macro
SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro
SIMM16_WAITCNT_LGKM_CNT_START = 0x00000004 # macro
SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000006 # macro
SIMM16_WAITCNT_VM_CNT_START = 0x0000000a # macro
SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000006 # macro
SIMM16_WAITCNT_DEPCTR_SA_SDST_START = 0x00000000 # macro
SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VA_VCC_START = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VM_VSRC_START = 0x00000002 # macro
SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE = 0x00000003 # macro
SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START = 0x00000007 # macro
SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VA_SSRC_START = 0x00000008 # macro
SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VA_SDST_START = 0x00000009 # macro
SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE = 0x00000003 # macro
SIMM16_WAITCNT_DEPCTR_VA_VDST_START = 0x0000000c # macro
SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE = 0x00000004 # macro
SIMM16_WAIT_EVENT_EXP_RDY_START = 0x00000000 # macro
SIMM16_WAIT_EVENT_EXP_RDY_SIZE = 0x00000001 # macro
SQ_WAVE_IB_DEP_SA_SDST_SIZE = 0x00000004 # macro
SQ_WAVE_IB_DEP_SA_EXEC_SIZE = 0x00000002 # macro
SQ_WAVE_IB_DEP_SA_M0_SIZE = 0x00000001 # macro
SQ_WAVE_IB_DEP_VM_VSRC_SIZE = 0x00000004 # macro
SQ_WAVE_IB_DEP_HOLD_CNT_SIZE = 0x00000001 # macro
SQ_WAVE_IB_DEP_VA_SSRC_SIZE = 0x00000003 # macro
SQ_WAVE_IB_DEP_VA_SDST_SIZE = 0x00000004 # macro
SQ_WAVE_IB_DEP_VA_VCC_SIZE = 0x00000003 # macro
SQ_WAVE_IB_DEP_VA_EXEC_SIZE = 0x00000002 # macro
SQ_WAVE_IB_DEP_VA_VDST_SIZE = 0x00000005 # macro
SQ_WAVE_IB_DEP_LDS_DIR_SIZE = 0x00000003 # macro
SQ_ARB_STATE_ISSUED_BRMSG = 0x00000000 # macro
SQ_ARB_STATE_ISSUED_EXPORT = 0x00000001 # macro
SQ_ARB_STATE_ISSUED_LDS_DIRECT = 0x00000002 # macro
SQ_ARB_STATE_ISSUED_LDS = 0x00000003 # macro
SQ_ARB_STATE_ISSUED_TEX = 0x00000004 # macro
SQ_ARB_STATE_ISSUED_SCALAR = 0x00000005 # macro
SQ_ARB_STATE_ISSUED_VALU = 0x00000006 # macro
SQ_ARB_STATE_STALLED_BRMSG = 0x00000008 # macro
SQ_ARB_STATE_STALLED_EXPORT = 0x00000009 # macro
SQ_ARB_STATE_STALLED_LDS_DIRECT = 0x0000000a # macro
SQ_ARB_STATE_STALLED_LDS = 0x0000000b # macro
SQ_ARB_STATE_STALLED_TEX = 0x0000000c # macro
SQ_ARB_STATE_STALLED_SCALAR = 0x0000000d # macro
SQ_ARB_STATE_STALLED_VALU = 0x0000000e # macro
ROM_SIGNATURE = 0x0000aa55 # macro
# values for enumeration 'CP_PERFMON_ENABLE_MODE'
CP_PERFMON_ENABLE_MODE__enumvalues = {
0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT',
1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1',
2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE',
3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE',
}
CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0
CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1
CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2
CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3
CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CP_PERFMON_STATE'
CP_PERFMON_STATE__enumvalues = {
0: 'CP_PERFMON_STATE_DISABLE_AND_RESET',
1: 'CP_PERFMON_STATE_START_COUNTING',
2: 'CP_PERFMON_STATE_STOP_COUNTING',
3: 'CP_PERFMON_STATE_RESERVED_3',
4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM',
5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM',
}
CP_PERFMON_STATE_DISABLE_AND_RESET = 0
CP_PERFMON_STATE_START_COUNTING = 1
CP_PERFMON_STATE_STOP_COUNTING = 2
CP_PERFMON_STATE_RESERVED_3 = 3
CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4
CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5
CP_PERFMON_STATE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_NUM_SIMD_PER_CU'
ENUM_NUM_SIMD_PER_CU__enumvalues = {
2: 'NUM_SIMD_PER_CU',
}
NUM_SIMD_PER_CU = 2
ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum
# values for enumeration 'GATCL1RequestType'
GATCL1RequestType__enumvalues = {
0: 'GATCL1_TYPE_NORMAL',
1: 'GATCL1_TYPE_SHOOTDOWN',
2: 'GATCL1_TYPE_BYPASS',
}
GATCL1_TYPE_NORMAL = 0
GATCL1_TYPE_SHOOTDOWN = 1
GATCL1_TYPE_BYPASS = 2
GATCL1RequestType = ctypes.c_uint32 # enum
# values for enumeration 'GL0V_CACHE_POLICIES'
GL0V_CACHE_POLICIES__enumvalues = {
0: 'GL0V_CACHE_POLICY_MISS_LRU',
1: 'GL0V_CACHE_POLICY_MISS_EVICT',
2: 'GL0V_CACHE_POLICY_HIT_LRU',
3: 'GL0V_CACHE_POLICY_HIT_EVICT',
4: 'GL0V_CACHE_POLICY_MISS_INVAL',
}
GL0V_CACHE_POLICY_MISS_LRU = 0
GL0V_CACHE_POLICY_MISS_EVICT = 1
GL0V_CACHE_POLICY_HIT_LRU = 2
GL0V_CACHE_POLICY_HIT_EVICT = 3
GL0V_CACHE_POLICY_MISS_INVAL = 4
GL0V_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'GL1_CACHE_POLICIES'
GL1_CACHE_POLICIES__enumvalues = {
0: 'GL1_CACHE_POLICY_MISS_LRU',
1: 'GL1_CACHE_POLICY_MISS_EVICT',
2: 'GL1_CACHE_POLICY_HIT_LRU',
3: 'GL1_CACHE_POLICY_HIT_EVICT',
}
GL1_CACHE_POLICY_MISS_LRU = 0
GL1_CACHE_POLICY_MISS_EVICT = 1
GL1_CACHE_POLICY_HIT_LRU = 2
GL1_CACHE_POLICY_HIT_EVICT = 3
GL1_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'GL1_CACHE_STORE_POLICIES'
GL1_CACHE_STORE_POLICIES__enumvalues = {
0: 'GL1_CACHE_STORE_POLICY_BYPASS',
}
GL1_CACHE_STORE_POLICY_BYPASS = 0
GL1_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'GL2_CACHE_POLICIES'
GL2_CACHE_POLICIES__enumvalues = {
0: 'GL2_CACHE_POLICY_LRU',
1: 'GL2_CACHE_POLICY_STREAM',
2: 'GL2_CACHE_POLICY_NOA',
3: 'GL2_CACHE_POLICY_BYPASS',
}
GL2_CACHE_POLICY_LRU = 0
GL2_CACHE_POLICY_STREAM = 1
GL2_CACHE_POLICY_NOA = 2
GL2_CACHE_POLICY_BYPASS = 3
GL2_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'GL2_NACKS'
GL2_NACKS__enumvalues = {
0: 'GL2_NACK_NO_FAULT',
1: 'GL2_NACK_PAGE_FAULT',
2: 'GL2_NACK_PROTECTION_FAULT',
3: 'GL2_NACK_DATA_ERROR',
}
GL2_NACK_NO_FAULT = 0
GL2_NACK_PAGE_FAULT = 1
GL2_NACK_PROTECTION_FAULT = 2
GL2_NACK_DATA_ERROR = 3
GL2_NACKS = ctypes.c_uint32 # enum
# values for enumeration 'GL2_OP'
GL2_OP__enumvalues = {
0: 'GL2_OP_READ',
1: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32',
2: 'GL2_OP_ATOMIC_FMIN_RTN_32',
3: 'GL2_OP_ATOMIC_FMAX_RTN_32',
4: 'GL2_OP_ATOMIC_PK_ADD_FP16_RTN',
5: 'GL2_OP_ATOMIC_FADD_RTN_32',
6: 'GL2_OP_ATOMIC_PK_ADD_BF16_RTN',
7: 'GL2_OP_ATOMIC_SWAP_RTN_32',
8: 'GL2_OP_ATOMIC_CMPSWAP_RTN_32',
9: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32',
10: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32',
11: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32',
12: 'GL2_OP_PROBE_FILTER',
13: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32',
14: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2',
15: 'GL2_OP_ATOMIC_ADD_RTN_32',
16: 'GL2_OP_ATOMIC_SUB_RTN_32',
17: 'GL2_OP_ATOMIC_SMIN_RTN_32',
18: 'GL2_OP_ATOMIC_UMIN_RTN_32',
19: 'GL2_OP_ATOMIC_SMAX_RTN_32',
20: 'GL2_OP_ATOMIC_UMAX_RTN_32',
21: 'GL2_OP_ATOMIC_AND_RTN_32',
22: 'GL2_OP_ATOMIC_OR_RTN_32',
23: 'GL2_OP_ATOMIC_XOR_RTN_32',
24: 'GL2_OP_ATOMIC_INC_RTN_32',
25: 'GL2_OP_ATOMIC_DEC_RTN_32',
26: 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32',
27: 'GL2_OP_ATOMIC_COND_SUB_RTN_32',
29: 'GL2_OP_UTC_PROBE',
30: 'GL2_OP_LOAD_RESERVE',
32: 'GL2_OP_WRITE',
33: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64',
34: 'GL2_OP_ATOMIC_FMIN_RTN_64',
35: 'GL2_OP_ATOMIC_FMAX_RTN_64',
39: 'GL2_OP_ATOMIC_SWAP_RTN_64',
40: 'GL2_OP_ATOMIC_CMPSWAP_RTN_64',
41: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64',
42: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64',
43: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64',
47: 'GL2_OP_ATOMIC_ADD_RTN_64',
48: 'GL2_OP_ATOMIC_SUB_RTN_64',
49: 'GL2_OP_ATOMIC_SMIN_RTN_64',
50: 'GL2_OP_ATOMIC_UMIN_RTN_64',
51: 'GL2_OP_ATOMIC_SMAX_RTN_64',
52: 'GL2_OP_ATOMIC_UMAX_RTN_64',
53: 'GL2_OP_ATOMIC_AND_RTN_64',
54: 'GL2_OP_ATOMIC_OR_RTN_64',
55: 'GL2_OP_ATOMIC_XOR_RTN_64',
56: 'GL2_OP_ATOMIC_INC_RTN_64',
57: 'GL2_OP_ATOMIC_DEC_RTN_64',
59: 'GL2_OP_WRITE_ZERO_SIZE',
61: 'GL2_OP_GL2_INV',
62: 'GL2_OP_ATOMIC_STORE_COND_RTN',
64: 'GL2_OP_GL1_INV',
65: 'GL2_OP_ATOMIC_FCMPSWAP_32',
66: 'GL2_OP_ATOMIC_FMIN_32',
67: 'GL2_OP_ATOMIC_FMAX_32',
68: 'GL2_OP_ATOMIC_PK_ADD_FP16',
69: 'GL2_OP_ATOMIC_FADD_32',
70: 'GL2_OP_ATOMIC_PK_ADD_BF16',
71: 'GL2_OP_ATOMIC_SWAP_32',
72: 'GL2_OP_ATOMIC_CMPSWAP_32',
73: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32',
74: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32',
75: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32',
76: 'GL2_OP_ATOMIC_UMIN_8',
77: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32',
79: 'GL2_OP_ATOMIC_ADD_32',
80: 'GL2_OP_ATOMIC_SUB_32',
81: 'GL2_OP_ATOMIC_SMIN_32',
82: 'GL2_OP_ATOMIC_UMIN_32',
83: 'GL2_OP_ATOMIC_SMAX_32',
84: 'GL2_OP_ATOMIC_UMAX_32',
85: 'GL2_OP_ATOMIC_AND_32',
86: 'GL2_OP_ATOMIC_OR_32',
87: 'GL2_OP_ATOMIC_XOR_32',
88: 'GL2_OP_ATOMIC_INC_32',
89: 'GL2_OP_ATOMIC_DEC_32',
91: 'GL2_OP_NOP_RTN0',
93: 'GL2_OP_GL2_WB',
94: 'GL2_OP_FORCE_EXISTING_DATA_TO_DECOMPRESS',
97: 'GL2_OP_ATOMIC_FCMPSWAP_64',
98: 'GL2_OP_ATOMIC_FMIN_64',
99: 'GL2_OP_ATOMIC_FMAX_64',
103: 'GL2_OP_ATOMIC_SWAP_64',
104: 'GL2_OP_ATOMIC_CMPSWAP_64',
105: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64',
106: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64',
107: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64',
111: 'GL2_OP_ATOMIC_ADD_64',
112: 'GL2_OP_ATOMIC_SUB_64',
113: 'GL2_OP_ATOMIC_SMIN_64',
114: 'GL2_OP_ATOMIC_UMIN_64',
115: 'GL2_OP_ATOMIC_SMAX_64',
116: 'GL2_OP_ATOMIC_UMAX_64',
117: 'GL2_OP_ATOMIC_AND_64',
118: 'GL2_OP_ATOMIC_OR_64',
119: 'GL2_OP_ATOMIC_XOR_64',
120: 'GL2_OP_ATOMIC_INC_64',
121: 'GL2_OP_ATOMIC_DEC_64',
122: 'GL2_OP_ATOMIC_UMAX_8',
123: 'GL2_OP_NOP_ACK',
125: 'GL2_OP_GL2_WBINV',
126: 'GL2_OP_READ_COMPRESSION_KEY',
}
GL2_OP_READ = 0
GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 1
GL2_OP_ATOMIC_FMIN_RTN_32 = 2
GL2_OP_ATOMIC_FMAX_RTN_32 = 3
GL2_OP_ATOMIC_PK_ADD_FP16_RTN = 4
GL2_OP_ATOMIC_FADD_RTN_32 = 5
GL2_OP_ATOMIC_PK_ADD_BF16_RTN = 6
GL2_OP_ATOMIC_SWAP_RTN_32 = 7
GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 8
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11
GL2_OP_PROBE_FILTER = 12
GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13
GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14
GL2_OP_ATOMIC_ADD_RTN_32 = 15
GL2_OP_ATOMIC_SUB_RTN_32 = 16
GL2_OP_ATOMIC_SMIN_RTN_32 = 17
GL2_OP_ATOMIC_UMIN_RTN_32 = 18
GL2_OP_ATOMIC_SMAX_RTN_32 = 19
GL2_OP_ATOMIC_UMAX_RTN_32 = 20
GL2_OP_ATOMIC_AND_RTN_32 = 21
GL2_OP_ATOMIC_OR_RTN_32 = 22
GL2_OP_ATOMIC_XOR_RTN_32 = 23
GL2_OP_ATOMIC_INC_RTN_32 = 24
GL2_OP_ATOMIC_DEC_RTN_32 = 25
GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 26
GL2_OP_ATOMIC_COND_SUB_RTN_32 = 27
GL2_OP_UTC_PROBE = 29
GL2_OP_LOAD_RESERVE = 30
GL2_OP_WRITE = 32
GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 33
GL2_OP_ATOMIC_FMIN_RTN_64 = 34
GL2_OP_ATOMIC_FMAX_RTN_64 = 35
GL2_OP_ATOMIC_SWAP_RTN_64 = 39
GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 40
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43
GL2_OP_ATOMIC_ADD_RTN_64 = 47
GL2_OP_ATOMIC_SUB_RTN_64 = 48
GL2_OP_ATOMIC_SMIN_RTN_64 = 49
GL2_OP_ATOMIC_UMIN_RTN_64 = 50
GL2_OP_ATOMIC_SMAX_RTN_64 = 51
GL2_OP_ATOMIC_UMAX_RTN_64 = 52
GL2_OP_ATOMIC_AND_RTN_64 = 53
GL2_OP_ATOMIC_OR_RTN_64 = 54
GL2_OP_ATOMIC_XOR_RTN_64 = 55
GL2_OP_ATOMIC_INC_RTN_64 = 56
GL2_OP_ATOMIC_DEC_RTN_64 = 57
GL2_OP_WRITE_ZERO_SIZE = 59
GL2_OP_GL2_INV = 61
GL2_OP_ATOMIC_STORE_COND_RTN = 62
GL2_OP_GL1_INV = 64
GL2_OP_ATOMIC_FCMPSWAP_32 = 65
GL2_OP_ATOMIC_FMIN_32 = 66
GL2_OP_ATOMIC_FMAX_32 = 67
GL2_OP_ATOMIC_PK_ADD_FP16 = 68
GL2_OP_ATOMIC_FADD_32 = 69
GL2_OP_ATOMIC_PK_ADD_BF16 = 70
GL2_OP_ATOMIC_SWAP_32 = 71
GL2_OP_ATOMIC_CMPSWAP_32 = 72
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75
GL2_OP_ATOMIC_UMIN_8 = 76
GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77
GL2_OP_ATOMIC_ADD_32 = 79
GL2_OP_ATOMIC_SUB_32 = 80
GL2_OP_ATOMIC_SMIN_32 = 81
GL2_OP_ATOMIC_UMIN_32 = 82
GL2_OP_ATOMIC_SMAX_32 = 83
GL2_OP_ATOMIC_UMAX_32 = 84
GL2_OP_ATOMIC_AND_32 = 85
GL2_OP_ATOMIC_OR_32 = 86
GL2_OP_ATOMIC_XOR_32 = 87
GL2_OP_ATOMIC_INC_32 = 88
GL2_OP_ATOMIC_DEC_32 = 89
GL2_OP_NOP_RTN0 = 91
GL2_OP_GL2_WB = 93
GL2_OP_FORCE_EXISTING_DATA_TO_DECOMPRESS = 94
GL2_OP_ATOMIC_FCMPSWAP_64 = 97
GL2_OP_ATOMIC_FMIN_64 = 98
GL2_OP_ATOMIC_FMAX_64 = 99
GL2_OP_ATOMIC_SWAP_64 = 103
GL2_OP_ATOMIC_CMPSWAP_64 = 104
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107
GL2_OP_ATOMIC_ADD_64 = 111
GL2_OP_ATOMIC_SUB_64 = 112
GL2_OP_ATOMIC_SMIN_64 = 113
GL2_OP_ATOMIC_UMIN_64 = 114
GL2_OP_ATOMIC_SMAX_64 = 115
GL2_OP_ATOMIC_UMAX_64 = 116
GL2_OP_ATOMIC_AND_64 = 117
GL2_OP_ATOMIC_OR_64 = 118
GL2_OP_ATOMIC_XOR_64 = 119
GL2_OP_ATOMIC_INC_64 = 120
GL2_OP_ATOMIC_DEC_64 = 121
GL2_OP_ATOMIC_UMAX_8 = 122
GL2_OP_NOP_ACK = 123
GL2_OP_GL2_WBINV = 125
GL2_OP_READ_COMPRESSION_KEY = 126
GL2_OP = ctypes.c_uint32 # enum
# values for enumeration 'GL2_OP_MASKS'
GL2_OP_MASKS__enumvalues = {
8: 'GL2_OP_MASK_FLUSH_DENROM',
32: 'GL2_OP_MASK_64',
64: 'GL2_OP_MASK_NO_RTN',
}
GL2_OP_MASK_FLUSH_DENROM = 8
GL2_OP_MASK_64 = 32
GL2_OP_MASK_NO_RTN = 64
GL2_OP_MASKS = ctypes.c_uint32 # enum
# values for enumeration 'Hdp_SurfaceEndian'
Hdp_SurfaceEndian__enumvalues = {
0: 'HDP_ENDIAN_NONE',
1: 'HDP_ENDIAN_8IN16',
2: 'HDP_ENDIAN_8IN32',
3: 'HDP_ENDIAN_8IN64',
}
HDP_ENDIAN_NONE = 0
HDP_ENDIAN_8IN16 = 1
HDP_ENDIAN_8IN32 = 2
HDP_ENDIAN_8IN64 = 3
Hdp_SurfaceEndian = ctypes.c_uint32 # enum
# values for enumeration 'MTYPE'
MTYPE__enumvalues = {
0: 'MTYPE_C_RW_US',
1: 'MTYPE_RESERVED_1',
2: 'MTYPE_C_RO_S',
3: 'MTYPE_UC',
4: 'MTYPE_C_RW_S',
5: 'MTYPE_RESERVED_5',
6: 'MTYPE_C_RO_US',
7: 'MTYPE_RESERVED_7',
}
MTYPE_C_RW_US = 0
MTYPE_RESERVED_1 = 1
MTYPE_C_RO_S = 2
MTYPE_UC = 3
MTYPE_C_RW_S = 4
MTYPE_RESERVED_5 = 5
MTYPE_C_RO_US = 6
MTYPE_RESERVED_7 = 7
MTYPE = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_COUNTER_MODE'
PERFMON_COUNTER_MODE__enumvalues = {
0: 'PERFMON_COUNTER_MODE_ACCUM',
1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES',
2: 'PERFMON_COUNTER_MODE_MAX',
3: 'PERFMON_COUNTER_MODE_DIRTY',
4: 'PERFMON_COUNTER_MODE_SAMPLE',
5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT',
6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT',
7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI',
8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI',
9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES',
15: 'PERFMON_COUNTER_MODE_RESERVED',
}
PERFMON_COUNTER_MODE_ACCUM = 0
PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1
PERFMON_COUNTER_MODE_MAX = 2
PERFMON_COUNTER_MODE_DIRTY = 3
PERFMON_COUNTER_MODE_SAMPLE = 4
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6
PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7
PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8
PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9
PERFMON_COUNTER_MODE_RESERVED = 15
PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_SPM_MODE'
PERFMON_SPM_MODE__enumvalues = {
0: 'PERFMON_SPM_MODE_OFF',
1: 'PERFMON_SPM_MODE_16BIT_CLAMP',
2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP',
3: 'PERFMON_SPM_MODE_32BIT_CLAMP',
4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP',
5: 'PERFMON_SPM_MODE_RESERVED_5',
6: 'PERFMON_SPM_MODE_RESERVED_6',
7: 'PERFMON_SPM_MODE_RESERVED_7',
8: 'PERFMON_SPM_MODE_TEST_MODE_0',
9: 'PERFMON_SPM_MODE_TEST_MODE_1',
10: 'PERFMON_SPM_MODE_TEST_MODE_2',
}
PERFMON_SPM_MODE_OFF = 0
PERFMON_SPM_MODE_16BIT_CLAMP = 1
PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2
PERFMON_SPM_MODE_32BIT_CLAMP = 3
PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4
PERFMON_SPM_MODE_RESERVED_5 = 5
PERFMON_SPM_MODE_RESERVED_6 = 6
PERFMON_SPM_MODE_RESERVED_7 = 7
PERFMON_SPM_MODE_TEST_MODE_0 = 8
PERFMON_SPM_MODE_TEST_MODE_1 = 9
PERFMON_SPM_MODE_TEST_MODE_2 = 10
PERFMON_SPM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'READ_COMPRESSION_MODE'
READ_COMPRESSION_MODE__enumvalues = {
0: 'COMPRESSION_MODE_BYPASS_COMPRESSION',
1: 'COMPRESSION_MODE_READ_RAW_COMPRESSED_DATA',
2: 'COMPRESSION_MODE_READ_DECOMPRESSED',
}
COMPRESSION_MODE_BYPASS_COMPRESSION = 0
COMPRESSION_MODE_READ_RAW_COMPRESSED_DATA = 1
COMPRESSION_MODE_READ_DECOMPRESSED = 2
READ_COMPRESSION_MODE = ctypes.c_uint32 # enum
# values for enumeration 'ReadPolicy'
ReadPolicy__enumvalues = {
0: 'CACHE_LRU_RD',
1: 'CACHE_STREAM_RD',
2: 'CACHE_NOA',
3: 'RESERVED_RDPOLICY',
}
CACHE_LRU_RD = 0
CACHE_STREAM_RD = 1
CACHE_NOA = 2
RESERVED_RDPOLICY = 3
ReadPolicy = ctypes.c_uint32 # enum
# values for enumeration 'SCOPE'
SCOPE__enumvalues = {
0: 'SCOPE_CU',
1: 'SCOPE_SE',
2: 'SCOPE_DEV',
3: 'SCOPE_SYS',
}
SCOPE_CU = 0
SCOPE_SE = 1
SCOPE_DEV = 2
SCOPE_SYS = 3
SCOPE = ctypes.c_uint32 # enum
# values for enumeration 'SDMA_PERFMON_SEL'
SDMA_PERFMON_SEL__enumvalues = {
0: 'SDMA_PERFMON_SEL_CYCLE',
1: 'SDMA_PERFMON_SEL_IDLE',
2: 'SDMA_PERFMON_SEL_REG_IDLE',
3: 'SDMA_PERFMON_SEL_RB_EMPTY',
4: 'SDMA_PERFMON_SEL_RB_FULL',
5: 'SDMA_PERFMON_SEL_RB_WPTR_WRAP',
6: 'SDMA_PERFMON_SEL_RB_RPTR_WRAP',
7: 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ',
8: 'SDMA_PERFMON_SEL_RB_RPTR_WB',
9: 'SDMA_PERFMON_SEL_RB_CMD_IDLE',
10: 'SDMA_PERFMON_SEL_RB_CMD_FULL',
11: 'SDMA_PERFMON_SEL_IB_CMD_IDLE',
12: 'SDMA_PERFMON_SEL_IB_CMD_FULL',
13: 'SDMA_PERFMON_SEL_EX_IDLE',
14: 'SDMA_PERFMON_SEL_SRBM_REG_SEND',
15: 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
16: 'SDMA_PERFMON_SEL_WR_BA_RTR',
17: 'SDMA_PERFMON_SEL_MC_WR_IDLE',
18: 'SDMA_PERFMON_SEL_MC_WR_COUNT',
19: 'SDMA_PERFMON_SEL_RD_BA_RTR',
20: 'SDMA_PERFMON_SEL_MC_RD_IDLE',
21: 'SDMA_PERFMON_SEL_MC_RD_COUNT',
22: 'SDMA_PERFMON_SEL_MC_RD_RET_STALL',
23: 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE',
26: 'SDMA_PERFMON_SEL_SEM_IDLE',
27: 'SDMA_PERFMON_SEL_SEM_REQ_STALL',
28: 'SDMA_PERFMON_SEL_SEM_REQ_COUNT',
29: 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE',
30: 'SDMA_PERFMON_SEL_SEM_RESP_FAIL',
31: 'SDMA_PERFMON_SEL_SEM_RESP_PASS',
32: 'SDMA_PERFMON_SEL_INT_IDLE',
33: 'SDMA_PERFMON_SEL_INT_REQ_STALL',
34: 'SDMA_PERFMON_SEL_INT_REQ_COUNT',
35: 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED',
36: 'SDMA_PERFMON_SEL_INT_RESP_RETRY',
37: 'SDMA_PERFMON_SEL_NUM_PACKET',
39: 'SDMA_PERFMON_SEL_CE_WREQ_IDLE',
40: 'SDMA_PERFMON_SEL_CE_WR_IDLE',
41: 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE',
42: 'SDMA_PERFMON_SEL_CE_RREQ_IDLE',
43: 'SDMA_PERFMON_SEL_CE_OUT_IDLE',
44: 'SDMA_PERFMON_SEL_CE_IN_IDLE',
45: 'SDMA_PERFMON_SEL_CE_DST_IDLE',
48: 'SDMA_PERFMON_SEL_CE_AFIFO_FULL',
49: 'SDMA_PERFMON_SEL_DUMMY_0',
50: 'SDMA_PERFMON_SEL_DUMMY_1',
51: 'SDMA_PERFMON_SEL_CE_INFO_FULL',
52: 'SDMA_PERFMON_SEL_CE_INFO1_FULL',
53: 'SDMA_PERFMON_SEL_CE_RD_STALL',
54: 'SDMA_PERFMON_SEL_CE_WR_STALL',
55: 'SDMA_PERFMON_SEL_QUEUE0_SELECT',
56: 'SDMA_PERFMON_SEL_QUEUE1_SELECT',
57: 'SDMA_PERFMON_SEL_QUEUE2_SELECT',
58: 'SDMA_PERFMON_SEL_QUEUE3_SELECT',
59: 'SDMA_PERFMON_SEL_CTX_CHANGE',
60: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED',
61: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION',
62: 'SDMA_PERFMON_SEL_DOORBELL',
63: 'SDMA_PERFMON_SEL_MCU_L1_WR_VLD',
64: 'SDMA_PERFMON_SEL_CE_L1_WR_VLD',
65: 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ',
66: 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK',
67: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ',
68: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK',
69: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL',
70: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL',
71: 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK',
72: 'SDMA_PERFMON_SEL_UTCL2_RET_ACK',
73: 'SDMA_PERFMON_SEL_UTCL2_FREE',
74: 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND',
75: 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND',
76: 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND',
77: 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND',
78: 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND',
79: 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH',
80: 'SDMA_PERFMON_SEL_GPUVM_INV_LOW',
81: 'SDMA_PERFMON_SEL_L1_WRL2_IDLE',
82: 'SDMA_PERFMON_SEL_L1_RDL2_IDLE',
83: 'SDMA_PERFMON_SEL_L1_WRMC_IDLE',
84: 'SDMA_PERFMON_SEL_L1_RDMC_IDLE',
85: 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE',
86: 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE',
87: 'SDMA_PERFMON_SEL_META_L2_REQ_SEND',
88: 'SDMA_PERFMON_SEL_L2_META_RET_VLD',
89: 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND',
90: 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN',
91: 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND',
92: 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN',
93: 'SDMA_PERFMON_SEL_META_REQ_SEND',
94: 'SDMA_PERFMON_SEL_META_RTN_VLD',
95: 'SDMA_PERFMON_SEL_TLBI_SEND',
96: 'SDMA_PERFMON_SEL_TLBI_RTN',
97: 'SDMA_PERFMON_SEL_GCR_SEND',
98: 'SDMA_PERFMON_SEL_GCR_RTN',
99: 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER',
100: 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER',
}
SDMA_PERFMON_SEL_CYCLE = 0
SDMA_PERFMON_SEL_IDLE = 1
SDMA_PERFMON_SEL_REG_IDLE = 2
SDMA_PERFMON_SEL_RB_EMPTY = 3
SDMA_PERFMON_SEL_RB_FULL = 4
SDMA_PERFMON_SEL_RB_WPTR_WRAP = 5
SDMA_PERFMON_SEL_RB_RPTR_WRAP = 6
SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 7
SDMA_PERFMON_SEL_RB_RPTR_WB = 8
SDMA_PERFMON_SEL_RB_CMD_IDLE = 9
SDMA_PERFMON_SEL_RB_CMD_FULL = 10
SDMA_PERFMON_SEL_IB_CMD_IDLE = 11
SDMA_PERFMON_SEL_IB_CMD_FULL = 12
SDMA_PERFMON_SEL_EX_IDLE = 13
SDMA_PERFMON_SEL_SRBM_REG_SEND = 14
SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15
SDMA_PERFMON_SEL_WR_BA_RTR = 16
SDMA_PERFMON_SEL_MC_WR_IDLE = 17
SDMA_PERFMON_SEL_MC_WR_COUNT = 18
SDMA_PERFMON_SEL_RD_BA_RTR = 19
SDMA_PERFMON_SEL_MC_RD_IDLE = 20
SDMA_PERFMON_SEL_MC_RD_COUNT = 21
SDMA_PERFMON_SEL_MC_RD_RET_STALL = 22
SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 23
SDMA_PERFMON_SEL_SEM_IDLE = 26
SDMA_PERFMON_SEL_SEM_REQ_STALL = 27
SDMA_PERFMON_SEL_SEM_REQ_COUNT = 28
SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 29
SDMA_PERFMON_SEL_SEM_RESP_FAIL = 30
SDMA_PERFMON_SEL_SEM_RESP_PASS = 31
SDMA_PERFMON_SEL_INT_IDLE = 32
SDMA_PERFMON_SEL_INT_REQ_STALL = 33
SDMA_PERFMON_SEL_INT_REQ_COUNT = 34
SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 35
SDMA_PERFMON_SEL_INT_RESP_RETRY = 36
SDMA_PERFMON_SEL_NUM_PACKET = 37
SDMA_PERFMON_SEL_CE_WREQ_IDLE = 39
SDMA_PERFMON_SEL_CE_WR_IDLE = 40
SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 41
SDMA_PERFMON_SEL_CE_RREQ_IDLE = 42
SDMA_PERFMON_SEL_CE_OUT_IDLE = 43
SDMA_PERFMON_SEL_CE_IN_IDLE = 44
SDMA_PERFMON_SEL_CE_DST_IDLE = 45
SDMA_PERFMON_SEL_CE_AFIFO_FULL = 48
SDMA_PERFMON_SEL_DUMMY_0 = 49
SDMA_PERFMON_SEL_DUMMY_1 = 50
SDMA_PERFMON_SEL_CE_INFO_FULL = 51
SDMA_PERFMON_SEL_CE_INFO1_FULL = 52
SDMA_PERFMON_SEL_CE_RD_STALL = 53
SDMA_PERFMON_SEL_CE_WR_STALL = 54
SDMA_PERFMON_SEL_QUEUE0_SELECT = 55
SDMA_PERFMON_SEL_QUEUE1_SELECT = 56
SDMA_PERFMON_SEL_QUEUE2_SELECT = 57
SDMA_PERFMON_SEL_QUEUE3_SELECT = 58
SDMA_PERFMON_SEL_CTX_CHANGE = 59
SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 60
SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 61
SDMA_PERFMON_SEL_DOORBELL = 62
SDMA_PERFMON_SEL_MCU_L1_WR_VLD = 63
SDMA_PERFMON_SEL_CE_L1_WR_VLD = 64
SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 65
SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 66
SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 67
SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 68
SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 69
SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 70
SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 71
SDMA_PERFMON_SEL_UTCL2_RET_ACK = 72
SDMA_PERFMON_SEL_UTCL2_FREE = 73
SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 74
SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 75
SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 76
SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 77
SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 78
SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 79
SDMA_PERFMON_SEL_GPUVM_INV_LOW = 80
SDMA_PERFMON_SEL_L1_WRL2_IDLE = 81
SDMA_PERFMON_SEL_L1_RDL2_IDLE = 82
SDMA_PERFMON_SEL_L1_WRMC_IDLE = 83
SDMA_PERFMON_SEL_L1_RDMC_IDLE = 84
SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 85
SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 86
SDMA_PERFMON_SEL_META_L2_REQ_SEND = 87
SDMA_PERFMON_SEL_L2_META_RET_VLD = 88
SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 89
SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 90
SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 91
SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 92
SDMA_PERFMON_SEL_META_REQ_SEND = 93
SDMA_PERFMON_SEL_META_RTN_VLD = 94
SDMA_PERFMON_SEL_TLBI_SEND = 95
SDMA_PERFMON_SEL_TLBI_RTN = 96
SDMA_PERFMON_SEL_GCR_SEND = 97
SDMA_PERFMON_SEL_GCR_RTN = 98
SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 99
SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 100
SDMA_PERFMON_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SDMA_PERF_SEL'
SDMA_PERF_SEL__enumvalues = {
0: 'SDMA_PERF_SEL_CYCLE',
1: 'SDMA_PERF_SEL_IDLE',
2: 'SDMA_PERF_SEL_REG_IDLE',
3: 'SDMA_PERF_SEL_RB_EMPTY',
4: 'SDMA_PERF_SEL_RB_FULL',
5: 'SDMA_PERF_SEL_RB_WPTR_WRAP',
6: 'SDMA_PERF_SEL_RB_RPTR_WRAP',
7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ',
8: 'SDMA_PERF_SEL_RB_RPTR_WB',
9: 'SDMA_PERF_SEL_RB_CMD_IDLE',
10: 'SDMA_PERF_SEL_RB_CMD_FULL',
11: 'SDMA_PERF_SEL_IB_CMD_IDLE',
12: 'SDMA_PERF_SEL_IB_CMD_FULL',
13: 'SDMA_PERF_SEL_EX_IDLE',
14: 'SDMA_PERF_SEL_SRBM_REG_SEND',
15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
16: 'SDMA_PERF_SEL_MC_WR_IDLE',
17: 'SDMA_PERF_SEL_MC_WR_COUNT',
18: 'SDMA_PERF_SEL_MC_RD_IDLE',
19: 'SDMA_PERF_SEL_MC_RD_COUNT',
20: 'SDMA_PERF_SEL_MC_RD_RET_STALL',
21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE',
24: 'SDMA_PERF_SEL_SEM_IDLE',
25: 'SDMA_PERF_SEL_SEM_REQ_STALL',
26: 'SDMA_PERF_SEL_SEM_REQ_COUNT',
27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE',
28: 'SDMA_PERF_SEL_SEM_RESP_FAIL',
29: 'SDMA_PERF_SEL_SEM_RESP_PASS',
30: 'SDMA_PERF_SEL_INT_IDLE',
31: 'SDMA_PERF_SEL_INT_REQ_STALL',
32: 'SDMA_PERF_SEL_INT_REQ_COUNT',
33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED',
34: 'SDMA_PERF_SEL_INT_RESP_RETRY',
35: 'SDMA_PERF_SEL_NUM_PACKET',
37: 'SDMA_PERF_SEL_CE_WREQ_IDLE',
38: 'SDMA_PERF_SEL_CE_WR_IDLE',
39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE',
40: 'SDMA_PERF_SEL_CE_RREQ_IDLE',
41: 'SDMA_PERF_SEL_CE_OUT_IDLE',
42: 'SDMA_PERF_SEL_CE_IN_IDLE',
43: 'SDMA_PERF_SEL_CE_DST_IDLE',
46: 'SDMA_PERF_SEL_CE_AFIFO_FULL',
47: 'SDMA_PERF_SEL_DUMMY_0',
48: 'SDMA_PERF_SEL_DUMMY_1',
49: 'SDMA_PERF_SEL_CE_INFO_FULL',
50: 'SDMA_PERF_SEL_CE_INFO1_FULL',
51: 'SDMA_PERF_SEL_CE_RD_STALL',
52: 'SDMA_PERF_SEL_CE_WR_STALL',
53: 'SDMA_PERF_SEL_QUEUE0_SELECT',
54: 'SDMA_PERF_SEL_QUEUE1_SELECT',
55: 'SDMA_PERF_SEL_QUEUE2_SELECT',
56: 'SDMA_PERF_SEL_QUEUE3_SELECT',
57: 'SDMA_PERF_SEL_CTX_CHANGE',
58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED',
59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION',
60: 'SDMA_PERF_SEL_DOORBELL',
61: 'SDMA_PERF_SEL_RD_BA_RTR',
62: 'SDMA_PERF_SEL_WR_BA_RTR',
63: 'SDMA_PERF_SEL_MCU_L1_WR_VLD',
64: 'SDMA_PERF_SEL_CE_L1_WR_VLD',
65: 'SDMA_PERF_SEL_CPF_SDMA_INVREQ',
66: 'SDMA_PERF_SEL_SDMA_CPF_INVACK',
67: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ',
68: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK',
69: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL',
70: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL',
71: 'SDMA_PERF_SEL_UTCL2_RET_XNACK',
72: 'SDMA_PERF_SEL_UTCL2_RET_ACK',
73: 'SDMA_PERF_SEL_UTCL2_FREE',
74: 'SDMA_PERF_SEL_SDMA_UTCL2_SEND',
75: 'SDMA_PERF_SEL_DMA_L1_WR_SEND',
76: 'SDMA_PERF_SEL_DMA_L1_RD_SEND',
77: 'SDMA_PERF_SEL_DMA_MC_WR_SEND',
78: 'SDMA_PERF_SEL_DMA_MC_RD_SEND',
79: 'SDMA_PERF_SEL_GPUVM_INV_HIGH',
80: 'SDMA_PERF_SEL_GPUVM_INV_LOW',
81: 'SDMA_PERF_SEL_L1_WRL2_IDLE',
82: 'SDMA_PERF_SEL_L1_RDL2_IDLE',
83: 'SDMA_PERF_SEL_L1_WRMC_IDLE',
84: 'SDMA_PERF_SEL_L1_RDMC_IDLE',
85: 'SDMA_PERF_SEL_L1_WR_INV_IDLE',
86: 'SDMA_PERF_SEL_L1_RD_INV_IDLE',
87: 'SDMA_PERF_SEL_META_L2_REQ_SEND',
88: 'SDMA_PERF_SEL_L2_META_RET_VLD',
89: 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND',
90: 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN',
91: 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND',
92: 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN',
93: 'SDMA_PERF_SEL_META_REQ_SEND',
94: 'SDMA_PERF_SEL_META_RTN_VLD',
95: 'SDMA_PERF_SEL_TLBI_SEND',
96: 'SDMA_PERF_SEL_TLBI_RTN',
97: 'SDMA_PERF_SEL_GCR_SEND',
98: 'SDMA_PERF_SEL_GCR_RTN',
99: 'SDMA_PERF_SEL_CGCG_FENCE',
100: 'SDMA_PERF_SEL_CE_CH_WR_REQ',
101: 'SDMA_PERF_SEL_CE_CH_WR_RET',
102: 'SDMA_PERF_SEL_MCU_CH_WR_REQ',
103: 'SDMA_PERF_SEL_MCU_CH_WR_RET',
104: 'SDMA_PERF_SEL_CE_OR_MCU_CH_RD_REQ',
105: 'SDMA_PERF_SEL_CE_OR_MCU_CH_RD_RET',
106: 'SDMA_PERF_SEL_RB_CH_RD_REQ',
107: 'SDMA_PERF_SEL_RB_CH_RD_RET',
108: 'SDMA_PERF_SEL_IB_CH_RD_REQ',
109: 'SDMA_PERF_SEL_IB_CH_RD_RET',
110: 'SDMA_PERF_SEL_WPTR_CH_RD_REQ',
111: 'SDMA_PERF_SEL_WPTR_CH_RD_RET',
112: 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ',
113: 'SDMA_PERF_SEL_UTCL1_UTCL2_RET',
114: 'SDMA_PERF_SEL_CMD_OP_MATCH',
115: 'SDMA_PERF_SEL_CMD_OP_START',
116: 'SDMA_PERF_SEL_CMD_OP_END',
117: 'SDMA_PERF_SEL_CE_BUSY',
118: 'SDMA_PERF_SEL_CE_BUSY_START',
119: 'SDMA_PERF_SEL_CE_BUSY_END',
120: 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER',
121: 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_START',
122: 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_END',
123: 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND',
124: 'SDMA_PERF_SEL_CH_CE_WRRET_VALID',
125: 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND',
126: 'SDMA_PERF_SEL_CH_CE_RDRET_VALID',
127: 'SDMA_PERF_SEL_QUEUE4_SELECT',
128: 'SDMA_PERF_SEL_QUEUE5_SELECT',
129: 'SDMA_PERF_SEL_QUEUE6_SELECT',
130: 'SDMA_PERF_SEL_QUEUE7_SELECT',
}
SDMA_PERF_SEL_CYCLE = 0
SDMA_PERF_SEL_IDLE = 1
SDMA_PERF_SEL_REG_IDLE = 2
SDMA_PERF_SEL_RB_EMPTY = 3
SDMA_PERF_SEL_RB_FULL = 4
SDMA_PERF_SEL_RB_WPTR_WRAP = 5
SDMA_PERF_SEL_RB_RPTR_WRAP = 6
SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7
SDMA_PERF_SEL_RB_RPTR_WB = 8
SDMA_PERF_SEL_RB_CMD_IDLE = 9
SDMA_PERF_SEL_RB_CMD_FULL = 10
SDMA_PERF_SEL_IB_CMD_IDLE = 11
SDMA_PERF_SEL_IB_CMD_FULL = 12
SDMA_PERF_SEL_EX_IDLE = 13
SDMA_PERF_SEL_SRBM_REG_SEND = 14
SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15
SDMA_PERF_SEL_MC_WR_IDLE = 16
SDMA_PERF_SEL_MC_WR_COUNT = 17
SDMA_PERF_SEL_MC_RD_IDLE = 18
SDMA_PERF_SEL_MC_RD_COUNT = 19
SDMA_PERF_SEL_MC_RD_RET_STALL = 20
SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21
SDMA_PERF_SEL_SEM_IDLE = 24
SDMA_PERF_SEL_SEM_REQ_STALL = 25
SDMA_PERF_SEL_SEM_REQ_COUNT = 26
SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27
SDMA_PERF_SEL_SEM_RESP_FAIL = 28
SDMA_PERF_SEL_SEM_RESP_PASS = 29
SDMA_PERF_SEL_INT_IDLE = 30
SDMA_PERF_SEL_INT_REQ_STALL = 31
SDMA_PERF_SEL_INT_REQ_COUNT = 32
SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33
SDMA_PERF_SEL_INT_RESP_RETRY = 34
SDMA_PERF_SEL_NUM_PACKET = 35
SDMA_PERF_SEL_CE_WREQ_IDLE = 37
SDMA_PERF_SEL_CE_WR_IDLE = 38
SDMA_PERF_SEL_CE_SPLIT_IDLE = 39
SDMA_PERF_SEL_CE_RREQ_IDLE = 40
SDMA_PERF_SEL_CE_OUT_IDLE = 41
SDMA_PERF_SEL_CE_IN_IDLE = 42
SDMA_PERF_SEL_CE_DST_IDLE = 43
SDMA_PERF_SEL_CE_AFIFO_FULL = 46
SDMA_PERF_SEL_DUMMY_0 = 47
SDMA_PERF_SEL_DUMMY_1 = 48
SDMA_PERF_SEL_CE_INFO_FULL = 49
SDMA_PERF_SEL_CE_INFO1_FULL = 50
SDMA_PERF_SEL_CE_RD_STALL = 51
SDMA_PERF_SEL_CE_WR_STALL = 52
SDMA_PERF_SEL_QUEUE0_SELECT = 53
SDMA_PERF_SEL_QUEUE1_SELECT = 54
SDMA_PERF_SEL_QUEUE2_SELECT = 55
SDMA_PERF_SEL_QUEUE3_SELECT = 56
SDMA_PERF_SEL_CTX_CHANGE = 57
SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58
SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59
SDMA_PERF_SEL_DOORBELL = 60
SDMA_PERF_SEL_RD_BA_RTR = 61
SDMA_PERF_SEL_WR_BA_RTR = 62
SDMA_PERF_SEL_MCU_L1_WR_VLD = 63
SDMA_PERF_SEL_CE_L1_WR_VLD = 64
SDMA_PERF_SEL_CPF_SDMA_INVREQ = 65
SDMA_PERF_SEL_SDMA_CPF_INVACK = 66
SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 67
SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 68
SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 69
SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 70
SDMA_PERF_SEL_UTCL2_RET_XNACK = 71
SDMA_PERF_SEL_UTCL2_RET_ACK = 72
SDMA_PERF_SEL_UTCL2_FREE = 73
SDMA_PERF_SEL_SDMA_UTCL2_SEND = 74
SDMA_PERF_SEL_DMA_L1_WR_SEND = 75
SDMA_PERF_SEL_DMA_L1_RD_SEND = 76
SDMA_PERF_SEL_DMA_MC_WR_SEND = 77
SDMA_PERF_SEL_DMA_MC_RD_SEND = 78
SDMA_PERF_SEL_GPUVM_INV_HIGH = 79
SDMA_PERF_SEL_GPUVM_INV_LOW = 80
SDMA_PERF_SEL_L1_WRL2_IDLE = 81
SDMA_PERF_SEL_L1_RDL2_IDLE = 82
SDMA_PERF_SEL_L1_WRMC_IDLE = 83
SDMA_PERF_SEL_L1_RDMC_IDLE = 84
SDMA_PERF_SEL_L1_WR_INV_IDLE = 85
SDMA_PERF_SEL_L1_RD_INV_IDLE = 86
SDMA_PERF_SEL_META_L2_REQ_SEND = 87
SDMA_PERF_SEL_L2_META_RET_VLD = 88
SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 89
SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 90
SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 91
SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 92
SDMA_PERF_SEL_META_REQ_SEND = 93
SDMA_PERF_SEL_META_RTN_VLD = 94
SDMA_PERF_SEL_TLBI_SEND = 95
SDMA_PERF_SEL_TLBI_RTN = 96
SDMA_PERF_SEL_GCR_SEND = 97
SDMA_PERF_SEL_GCR_RTN = 98
SDMA_PERF_SEL_CGCG_FENCE = 99
SDMA_PERF_SEL_CE_CH_WR_REQ = 100
SDMA_PERF_SEL_CE_CH_WR_RET = 101
SDMA_PERF_SEL_MCU_CH_WR_REQ = 102
SDMA_PERF_SEL_MCU_CH_WR_RET = 103
SDMA_PERF_SEL_CE_OR_MCU_CH_RD_REQ = 104
SDMA_PERF_SEL_CE_OR_MCU_CH_RD_RET = 105
SDMA_PERF_SEL_RB_CH_RD_REQ = 106
SDMA_PERF_SEL_RB_CH_RD_RET = 107
SDMA_PERF_SEL_IB_CH_RD_REQ = 108
SDMA_PERF_SEL_IB_CH_RD_RET = 109
SDMA_PERF_SEL_WPTR_CH_RD_REQ = 110
SDMA_PERF_SEL_WPTR_CH_RD_RET = 111
SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 112
SDMA_PERF_SEL_UTCL1_UTCL2_RET = 113
SDMA_PERF_SEL_CMD_OP_MATCH = 114
SDMA_PERF_SEL_CMD_OP_START = 115
SDMA_PERF_SEL_CMD_OP_END = 116
SDMA_PERF_SEL_CE_BUSY = 117
SDMA_PERF_SEL_CE_BUSY_START = 118
SDMA_PERF_SEL_CE_BUSY_END = 119
SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER = 120
SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_START = 121
SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_END = 122
SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 123
SDMA_PERF_SEL_CH_CE_WRRET_VALID = 124
SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 125
SDMA_PERF_SEL_CH_CE_RDRET_VALID = 126
SDMA_PERF_SEL_QUEUE4_SELECT = 127
SDMA_PERF_SEL_QUEUE5_SELECT = 128
SDMA_PERF_SEL_QUEUE6_SELECT = 129
SDMA_PERF_SEL_QUEUE7_SELECT = 130
SDMA_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SPM_PERFMON_STATE'
SPM_PERFMON_STATE__enumvalues = {
0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET',
1: 'STRM_PERFMON_STATE_START_COUNTING',
2: 'STRM_PERFMON_STATE_STOP_COUNTING',
3: 'STRM_PERFMON_STATE_RESERVED_3',
4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM',
5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM',
}
STRM_PERFMON_STATE_DISABLE_AND_RESET = 0
STRM_PERFMON_STATE_START_COUNTING = 1
STRM_PERFMON_STATE_STOP_COUNTING = 2
STRM_PERFMON_STATE_RESERVED_3 = 3
STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4
STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5
SPM_PERFMON_STATE = ctypes.c_uint32 # enum
# values for enumeration 'TCC_MTYPE'
TCC_MTYPE__enumvalues = {
0: 'MTYPE_NC',
1: 'MTYPE_WC',
2: 'MTYPE_CC',
}
MTYPE_NC = 0
MTYPE_WC = 1
MTYPE_CC = 2
TCC_MTYPE = ctypes.c_uint32 # enum
# values for enumeration 'UTCL0FaultType'
UTCL0FaultType__enumvalues = {
0: 'UTCL0_XNACK_SUCCESS',
1: 'UTCL0_XNACK_RETRY',
2: 'UTCL0_XNACK_PRT',
3: 'UTCL0_XNACK_NO_RETRY',
}
UTCL0_XNACK_SUCCESS = 0
UTCL0_XNACK_RETRY = 1
UTCL0_XNACK_PRT = 2
UTCL0_XNACK_NO_RETRY = 3
UTCL0FaultType = ctypes.c_uint32 # enum
# values for enumeration 'UTCL0RequestType'
UTCL0RequestType__enumvalues = {
0: 'UTCL0_TYPE_NORMAL',
1: 'UTCL0_TYPE_SHOOTDOWN',
2: 'UTCL0_TYPE_BYPASS',
}
UTCL0_TYPE_NORMAL = 0
UTCL0_TYPE_SHOOTDOWN = 1
UTCL0_TYPE_BYPASS = 2
UTCL0RequestType = ctypes.c_uint32 # enum
# values for enumeration 'UTCL1FaultType'
UTCL1FaultType__enumvalues = {
0: 'UTCL1_XNACK_SUCCESS',
1: 'UTCL1_XNACK_RETRY',
2: 'UTCL1_XNACK_PRT',
3: 'UTCL1_XNACK_NO_RETRY',
}
UTCL1_XNACK_SUCCESS = 0
UTCL1_XNACK_RETRY = 1
UTCL1_XNACK_PRT = 2
UTCL1_XNACK_NO_RETRY = 3
UTCL1FaultType = ctypes.c_uint32 # enum
# values for enumeration 'UTCL1RequestType'
UTCL1RequestType__enumvalues = {
0: 'UTCL1_TYPE_NORMAL',
1: 'UTCL1_TYPE_SHOOTDOWN',
2: 'UTCL1_TYPE_BYPASS',
}
UTCL1_TYPE_NORMAL = 0
UTCL1_TYPE_SHOOTDOWN = 1
UTCL1_TYPE_BYPASS = 2
UTCL1RequestType = ctypes.c_uint32 # enum
# values for enumeration 'WRITE_COMPRESSION_MODE'
WRITE_COMPRESSION_MODE__enumvalues = {
0: 'COMPRESSION_MODE_BYPASS_METADATA_CACHE',
1: 'COMPRESSION_MODE_COMPRESSION_ENABLED',
2: 'COMPRESSION_MODE_WRITE_COMPRESSION_DISABLED',
}
COMPRESSION_MODE_BYPASS_METADATA_CACHE = 0
COMPRESSION_MODE_COMPRESSION_ENABLED = 1
COMPRESSION_MODE_WRITE_COMPRESSION_DISABLED = 2
WRITE_COMPRESSION_MODE = ctypes.c_uint32 # enum
# values for enumeration 'WritePolicy'
WritePolicy__enumvalues = {
0: 'CACHE_LRU_WR',
1: 'CACHE_STREAM',
2: 'CACHE_NOA_WR',
3: 'CACHE_BYPASS',
}
CACHE_LRU_WR = 0
CACHE_STREAM = 1
CACHE_NOA_WR = 2
CACHE_BYPASS = 3
WritePolicy = ctypes.c_uint32 # enum
# values for enumeration 'COLOR_KEYER_ENABLE'
COLOR_KEYER_ENABLE__enumvalues = {
0: 'COLOR_KEY_EN',
1: 'COLOR_KEY_DIS',
}
COLOR_KEY_EN = 0
COLOR_KEY_DIS = 1
COLOR_KEYER_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'COLOR_KEYER_MODE'
COLOR_KEYER_MODE__enumvalues = {
0: 'FORCE_00',
1: 'FORCE_FF',
2: 'RANGE_00',
3: 'RANGE_FF',
}
FORCE_00 = 0
FORCE_FF = 1
RANGE_00 = 2
RANGE_FF = 3
COLOR_KEYER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DENORM_TRUNCATE'
DENORM_TRUNCATE__enumvalues = {
0: 'CNVC_ROUND',
1: 'CNVC_TRUNCATE',
}
CNVC_ROUND = 0
CNVC_TRUNCATE = 1
DENORM_TRUNCATE = ctypes.c_uint32 # enum
# values for enumeration 'FORMAT_CROSSBAR'
FORMAT_CROSSBAR__enumvalues = {
0: 'FORMAT_CROSSBAR_R',
1: 'FORMAT_CROSSBAR_G',
2: 'FORMAT_CROSSBAR_B',
}
FORMAT_CROSSBAR_R = 0
FORMAT_CROSSBAR_G = 1
FORMAT_CROSSBAR_B = 2
FORMAT_CROSSBAR = ctypes.c_uint32 # enum
# values for enumeration 'LUMA_KEYER_ENABLE'
LUMA_KEYER_ENABLE__enumvalues = {
0: 'LUMA_KEY_EN',
1: 'LUMA_KEY_DIS',
}
LUMA_KEY_EN = 0
LUMA_KEY_DIS = 1
LUMA_KEYER_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'PIX_EXPAND_MODE'
PIX_EXPAND_MODE__enumvalues = {
0: 'PIX_DYNAMIC_EXPANSION',
1: 'PIX_ZERO_EXPANSION',
}
PIX_DYNAMIC_EXPANSION = 0
PIX_ZERO_EXPANSION = 1
PIX_EXPAND_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PRE_CSC_MODE_ENUM'
PRE_CSC_MODE_ENUM__enumvalues = {
0: 'PRE_CSC_BYPASS',
1: 'PRE_CSC_SET_A',
2: 'PRE_CSC_SET_B',
}
PRE_CSC_BYPASS = 0
PRE_CSC_SET_A = 1
PRE_CSC_SET_B = 2
PRE_CSC_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'PRE_DEGAM_MODE'
PRE_DEGAM_MODE__enumvalues = {
0: 'PRE_DEGAM_BYPASS',
1: 'PRE_DEGAM_ENABLE',
}
PRE_DEGAM_BYPASS = 0
PRE_DEGAM_ENABLE = 1
PRE_DEGAM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PRE_DEGAM_SELECT'
PRE_DEGAM_SELECT__enumvalues = {
0: 'PRE_DEGAM_SRGB',
1: 'PRE_DEGAM_GAMMA_22',
2: 'PRE_DEGAM_GAMMA_24',
3: 'PRE_DEGAM_GAMMA_26',
4: 'PRE_DEGAM_BT2020',
5: 'PRE_DEGAM_BT2100PQ',
6: 'PRE_DEGAM_BT2100HLG',
}
PRE_DEGAM_SRGB = 0
PRE_DEGAM_GAMMA_22 = 1
PRE_DEGAM_GAMMA_24 = 2
PRE_DEGAM_GAMMA_26 = 3
PRE_DEGAM_BT2020 = 4
PRE_DEGAM_BT2100PQ = 5
PRE_DEGAM_BT2100HLG = 6
PRE_DEGAM_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_PIXEL_FORMAT'
SURFACE_PIXEL_FORMAT__enumvalues = {
1: 'ARGB1555',
2: 'RGBA5551',
3: 'RGB565',
4: 'BGR565',
5: 'ARGB4444',
6: 'RGBA4444',
8: 'ARGB8888',
9: 'RGBA8888',
10: 'ARGB2101010',
11: 'RGBA1010102',
12: 'AYCrCb8888',
13: 'YCrCbA8888',
14: 'ACrYCb8888',
15: 'CrYCbA8888',
16: 'ARGB16161616_10MSB',
17: 'RGBA16161616_10MSB',
18: 'ARGB16161616_10LSB',
19: 'RGBA16161616_10LSB',
20: 'ARGB16161616_12MSB',
21: 'RGBA16161616_12MSB',
22: 'ARGB16161616_12LSB',
23: 'RGBA16161616_12LSB',
24: 'ARGB16161616_FLOAT',
25: 'RGBA16161616_FLOAT',
26: 'ARGB16161616_UNORM',
27: 'RGBA16161616_UNORM',
28: 'ARGB16161616_SNORM',
29: 'RGBA16161616_SNORM',
32: 'AYCrCb16161616_10MSB',
33: 'AYCrCb16161616_10LSB',
34: 'YCrCbA16161616_10MSB',
35: 'YCrCbA16161616_10LSB',
36: 'ACrYCb16161616_10MSB',
37: 'ACrYCb16161616_10LSB',
38: 'CrYCbA16161616_10MSB',
39: 'CrYCbA16161616_10LSB',
40: 'AYCrCb16161616_12MSB',
41: 'AYCrCb16161616_12LSB',
42: 'YCrCbA16161616_12MSB',
43: 'YCrCbA16161616_12LSB',
44: 'ACrYCb16161616_12MSB',
45: 'ACrYCb16161616_12LSB',
46: 'CrYCbA16161616_12MSB',
47: 'CrYCbA16161616_12LSB',
64: 'Y8_CrCb88_420_PLANAR',
65: 'Y8_CbCr88_420_PLANAR',
66: 'Y10_CrCb1010_420_PLANAR',
67: 'Y10_CbCr1010_420_PLANAR',
68: 'Y12_CrCb1212_420_PLANAR',
69: 'Y12_CbCr1212_420_PLANAR',
72: 'YCrYCb8888_422_PACKED',
73: 'YCbYCr8888_422_PACKED',
74: 'CrYCbY8888_422_PACKED',
75: 'CbYCrY8888_422_PACKED',
76: 'YCrYCb10101010_422_PACKED',
77: 'YCbYCr10101010_422_PACKED',
78: 'CrYCbY10101010_422_PACKED',
79: 'CbYCrY10101010_422_PACKED',
80: 'YCrYCb12121212_422_PACKED',
81: 'YCbYCr12121212_422_PACKED',
82: 'CrYCbY12121212_422_PACKED',
83: 'CbYCrY12121212_422_PACKED',
112: 'RGB111110_FIX',
113: 'BGR101111_FIX',
114: 'ACrYCb2101010',
115: 'CrYCbA1010102',
116: 'RGBE',
118: 'RGB111110_FLOAT',
119: 'BGR101111_FLOAT',
120: 'MONO_8',
121: 'MONO_10MSB',
122: 'MONO_10LSB',
123: 'MONO_12MSB',
124: 'MONO_12LSB',
125: 'MONO_16',
}
ARGB1555 = 1
RGBA5551 = 2
RGB565 = 3
BGR565 = 4
ARGB4444 = 5
RGBA4444 = 6
ARGB8888 = 8
RGBA8888 = 9
ARGB2101010 = 10
RGBA1010102 = 11
AYCrCb8888 = 12
YCrCbA8888 = 13
ACrYCb8888 = 14
CrYCbA8888 = 15
ARGB16161616_10MSB = 16
RGBA16161616_10MSB = 17
ARGB16161616_10LSB = 18
RGBA16161616_10LSB = 19
ARGB16161616_12MSB = 20
RGBA16161616_12MSB = 21
ARGB16161616_12LSB = 22
RGBA16161616_12LSB = 23
ARGB16161616_FLOAT = 24
RGBA16161616_FLOAT = 25
ARGB16161616_UNORM = 26
RGBA16161616_UNORM = 27
ARGB16161616_SNORM = 28
RGBA16161616_SNORM = 29
AYCrCb16161616_10MSB = 32
AYCrCb16161616_10LSB = 33
YCrCbA16161616_10MSB = 34
YCrCbA16161616_10LSB = 35
ACrYCb16161616_10MSB = 36
ACrYCb16161616_10LSB = 37
CrYCbA16161616_10MSB = 38
CrYCbA16161616_10LSB = 39
AYCrCb16161616_12MSB = 40
AYCrCb16161616_12LSB = 41
YCrCbA16161616_12MSB = 42
YCrCbA16161616_12LSB = 43
ACrYCb16161616_12MSB = 44
ACrYCb16161616_12LSB = 45
CrYCbA16161616_12MSB = 46
CrYCbA16161616_12LSB = 47
Y8_CrCb88_420_PLANAR = 64
Y8_CbCr88_420_PLANAR = 65
Y10_CrCb1010_420_PLANAR = 66
Y10_CbCr1010_420_PLANAR = 67
Y12_CrCb1212_420_PLANAR = 68
Y12_CbCr1212_420_PLANAR = 69
YCrYCb8888_422_PACKED = 72
YCbYCr8888_422_PACKED = 73
CrYCbY8888_422_PACKED = 74
CbYCrY8888_422_PACKED = 75
YCrYCb10101010_422_PACKED = 76
YCbYCr10101010_422_PACKED = 77
CrYCbY10101010_422_PACKED = 78
CbYCrY10101010_422_PACKED = 79
YCrYCb12121212_422_PACKED = 80
YCbYCr12121212_422_PACKED = 81
CrYCbY12121212_422_PACKED = 82
CbYCrY12121212_422_PACKED = 83
RGB111110_FIX = 112
BGR101111_FIX = 113
ACrYCb2101010 = 114
CrYCbA1010102 = 115
RGBE = 116
RGB111110_FLOAT = 118
BGR101111_FLOAT = 119
MONO_8 = 120
MONO_10MSB = 121
MONO_10LSB = 122
MONO_12MSB = 123
MONO_12LSB = 124
MONO_16 = 125
SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'XNORM'
XNORM__enumvalues = {
0: 'XNORM_A',
1: 'XNORM_B',
}
XNORM_A = 0
XNORM_B = 1
XNORM = ctypes.c_uint32 # enum
# values for enumeration 'CUR_ENABLE'
CUR_ENABLE__enumvalues = {
0: 'CUR_DIS',
1: 'CUR_EN',
}
CUR_DIS = 0
CUR_EN = 1
CUR_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'CUR_EXPAND_MODE'
CUR_EXPAND_MODE__enumvalues = {
0: 'CUR_DYNAMIC_EXPANSION',
1: 'CUR_ZERO_EXPANSION',
}
CUR_DYNAMIC_EXPANSION = 0
CUR_ZERO_EXPANSION = 1
CUR_EXPAND_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CUR_INV_CLAMP'
CUR_INV_CLAMP__enumvalues = {
0: 'CUR_CLAMP_DIS',
1: 'CUR_CLAMP_EN',
}
CUR_CLAMP_DIS = 0
CUR_CLAMP_EN = 1
CUR_INV_CLAMP = ctypes.c_uint32 # enum
# values for enumeration 'CUR_MATRIX_COEF_FORMAT_ENUM'
CUR_MATRIX_COEF_FORMAT_ENUM__enumvalues = {
0: 'CUR_MATRIX_FIX_S2_13',
1: 'CUR_MATRIX_FIX_S3_12',
}
CUR_MATRIX_FIX_S2_13 = 0
CUR_MATRIX_FIX_S3_12 = 1
CUR_MATRIX_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CUR_MODE'
CUR_MODE__enumvalues = {
0: 'MONO_2BIT',
1: 'COLOR_24BIT_1BIT_AND',
2: 'COLOR_24BIT_8BIT_ALPHA_PREMULT',
3: 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT',
4: 'COLOR_64BIT_FP_PREMULT',
5: 'COLOR_64BIT_FP_UNPREMULT',
}
MONO_2BIT = 0
COLOR_24BIT_1BIT_AND = 1
COLOR_24BIT_8BIT_ALPHA_PREMULT = 2
COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3
COLOR_64BIT_FP_PREMULT = 4
COLOR_64BIT_FP_UNPREMULT = 5
CUR_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CUR_PENDING'
CUR_PENDING__enumvalues = {
0: 'CUR_NOT_PENDING',
1: 'CUR_YES_PENDING',
}
CUR_NOT_PENDING = 0
CUR_YES_PENDING = 1
CUR_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'CUR_ROM_EN'
CUR_ROM_EN__enumvalues = {
0: 'CUR_FP_NO_ROM',
1: 'CUR_FP_USE_ROM',
}
CUR_FP_NO_ROM = 0
CUR_FP_USE_ROM = 1
CUR_ROM_EN = ctypes.c_uint32 # enum
# values for enumeration 'COEF_RAM_SELECT_RD'
COEF_RAM_SELECT_RD__enumvalues = {
0: 'COEF_RAM_SELECT_BACK',
1: 'COEF_RAM_SELECT_CURRENT',
}
COEF_RAM_SELECT_BACK = 0
COEF_RAM_SELECT_CURRENT = 1
COEF_RAM_SELECT_RD = ctypes.c_uint32 # enum
# values for enumeration 'DSCL_MODE_SEL'
DSCL_MODE_SEL__enumvalues = {
0: 'DSCL_MODE_SCALING_444_BYPASS',
1: 'DSCL_MODE_SCALING_444_RGB_ENABLE',
2: 'DSCL_MODE_SCALING_444_YCBCR_ENABLE',
3: 'DSCL_MODE_SCALING_YCBCR_ENABLE',
4: 'DSCL_MODE_LUMA_SCALING_BYPASS',
5: 'DSCL_MODE_CHROMA_SCALING_BYPASS',
6: 'DSCL_MODE_DSCL_BYPASS',
}
DSCL_MODE_SCALING_444_BYPASS = 0
DSCL_MODE_SCALING_444_RGB_ENABLE = 1
DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2
DSCL_MODE_SCALING_YCBCR_ENABLE = 3
DSCL_MODE_LUMA_SCALING_BYPASS = 4
DSCL_MODE_CHROMA_SCALING_BYPASS = 5
DSCL_MODE_DSCL_BYPASS = 6
DSCL_MODE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'ISHARP_FMT_MODE_ENUM'
ISHARP_FMT_MODE_ENUM__enumvalues = {
0: 'ISHARP_FMT_MODE_0',
1: 'ISHARP_FMT_MODE_1',
}
ISHARP_FMT_MODE_0 = 0
ISHARP_FMT_MODE_1 = 1
ISHARP_FMT_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'ISHARP_LBA_MODE_ENUM'
ISHARP_LBA_MODE_ENUM__enumvalues = {
0: 'ISHARP_LBA_MODE_0',
1: 'ISHARP_LBA_MODE_1',
}
ISHARP_LBA_MODE_0 = 0
ISHARP_LBA_MODE_1 = 1
ISHARP_LBA_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'ISHARP_NOISEDET_MODE_ENUM'
ISHARP_NOISEDET_MODE_ENUM__enumvalues = {
0: 'ISHARP_NOISEDET_MODE_0',
1: 'ISHARP_NOISEDET_MODE_1',
2: 'ISHARP_NOISEDET_MODE_2',
3: 'ISHARP_NOISEDET_MODE_3',
}
ISHARP_NOISEDET_MODE_0 = 0
ISHARP_NOISEDET_MODE_1 = 1
ISHARP_NOISEDET_MODE_2 = 2
ISHARP_NOISEDET_MODE_3 = 3
ISHARP_NOISEDET_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'LB_ALPHA_EN'
LB_ALPHA_EN__enumvalues = {
0: 'LB_ALPHA_DISABLE',
1: 'LB_ALPHA_ENABLE',
}
LB_ALPHA_DISABLE = 0
LB_ALPHA_ENABLE = 1
LB_ALPHA_EN = ctypes.c_uint32 # enum
# values for enumeration 'LB_INTERLEAVE_EN'
LB_INTERLEAVE_EN__enumvalues = {
0: 'LB_INTERLEAVE_DISABLE',
1: 'LB_INTERLEAVE_ENABLE',
}
LB_INTERLEAVE_DISABLE = 0
LB_INTERLEAVE_ENABLE = 1
LB_INTERLEAVE_EN = ctypes.c_uint32 # enum
# values for enumeration 'LB_MEMORY_CONFIG'
LB_MEMORY_CONFIG__enumvalues = {
0: 'LB_MEMORY_CONFIG_0',
1: 'LB_MEMORY_CONFIG_1',
2: 'LB_MEMORY_CONFIG_2',
3: 'LB_MEMORY_CONFIG_3',
}
LB_MEMORY_CONFIG_0 = 0
LB_MEMORY_CONFIG_1 = 1
LB_MEMORY_CONFIG_2 = 2
LB_MEMORY_CONFIG_3 = 3
LB_MEMORY_CONFIG = ctypes.c_uint32 # enum
# values for enumeration 'MATRIX_MODE_ENUM'
MATRIX_MODE_ENUM__enumvalues = {
0: 'MATRIX_MODE_0',
1: 'MATRIX_MODE_1',
}
MATRIX_MODE_0 = 0
MATRIX_MODE_1 = 1
MATRIX_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'OBUF_BYPASS_SEL'
OBUF_BYPASS_SEL__enumvalues = {
0: 'OBUF_BYPASS_DIS',
1: 'OBUF_BYPASS_EN',
}
OBUF_BYPASS_DIS = 0
OBUF_BYPASS_EN = 1
OBUF_BYPASS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OBUF_IS_HALF_RECOUT_WIDTH_SEL'
OBUF_IS_HALF_RECOUT_WIDTH_SEL__enumvalues = {
0: 'OBUF_FULL_RECOUT',
1: 'OBUF_HALF_RECOUT',
}
OBUF_FULL_RECOUT = 0
OBUF_HALF_RECOUT = 1
OBUF_IS_HALF_RECOUT_WIDTH_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OBUF_USE_FULL_BUFFER_SEL'
OBUF_USE_FULL_BUFFER_SEL__enumvalues = {
0: 'OBUF_RECOUT',
1: 'OBUF_FULL',
}
OBUF_RECOUT = 0
OBUF_FULL = 1
OBUF_USE_FULL_BUFFER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SCL_2TAP_HARDCODE'
SCL_2TAP_HARDCODE__enumvalues = {
0: 'SCL_COEF_2TAP_HARDCODE_OFF',
1: 'SCL_COEF_2TAP_HARDCODE_ON',
}
SCL_COEF_2TAP_HARDCODE_OFF = 0
SCL_COEF_2TAP_HARDCODE_ON = 1
SCL_2TAP_HARDCODE = ctypes.c_uint32 # enum
# values for enumeration 'SCL_ALPHA_COEF'
SCL_ALPHA_COEF__enumvalues = {
0: 'SCL_ALPHA_COEF_FIRST',
1: 'SCL_ALPHA_COEF_SECOND',
}
SCL_ALPHA_COEF_FIRST = 0
SCL_ALPHA_COEF_SECOND = 1
SCL_ALPHA_COEF = ctypes.c_uint32 # enum
# values for enumeration 'SCL_AUTOCAL_MODE'
SCL_AUTOCAL_MODE__enumvalues = {
0: 'AUTOCAL_MODE_OFF',
1: 'AUTOCAL_MODE_AUTOSCALE',
2: 'AUTOCAL_MODE_AUTOCENTER',
3: 'AUTOCAL_MODE_AUTOREPLICATE',
}
AUTOCAL_MODE_OFF = 0
AUTOCAL_MODE_AUTOSCALE = 1
AUTOCAL_MODE_AUTOCENTER = 2
AUTOCAL_MODE_AUTOREPLICATE = 3
SCL_AUTOCAL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SCL_BOUNDARY'
SCL_BOUNDARY__enumvalues = {
0: 'SCL_BOUNDARY_EDGE',
1: 'SCL_BOUNDARY_BLACK',
}
SCL_BOUNDARY_EDGE = 0
SCL_BOUNDARY_BLACK = 1
SCL_BOUNDARY = ctypes.c_uint32 # enum
# values for enumeration 'SCL_CHROMA_COEF'
SCL_CHROMA_COEF__enumvalues = {
0: 'SCL_CHROMA_COEF_FIRST',
1: 'SCL_CHROMA_COEF_SECOND',
}
SCL_CHROMA_COEF_FIRST = 0
SCL_CHROMA_COEF_SECOND = 1
SCL_CHROMA_COEF = ctypes.c_uint32 # enum
# values for enumeration 'SCL_COEF_FILTER_TYPE_SEL'
SCL_COEF_FILTER_TYPE_SEL__enumvalues = {
0: 'SCL_COEF_LUMA_VERT_FILTER',
1: 'SCL_COEF_LUMA_HORZ_FILTER',
2: 'SCL_COEF_CHROMA_VERT_FILTER',
3: 'SCL_COEF_CHROMA_HORZ_FILTER',
4: 'SCL_COEF_SC_VERT_FILTER',
5: 'SCL_COEF_SC_HORZ_FILTER',
}
SCL_COEF_LUMA_VERT_FILTER = 0
SCL_COEF_LUMA_HORZ_FILTER = 1
SCL_COEF_CHROMA_VERT_FILTER = 2
SCL_COEF_CHROMA_HORZ_FILTER = 3
SCL_COEF_SC_VERT_FILTER = 4
SCL_COEF_SC_HORZ_FILTER = 5
SCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SCL_COEF_RAM_SEL'
SCL_COEF_RAM_SEL__enumvalues = {
0: 'SCL_COEF_RAM_SEL_0',
1: 'SCL_COEF_RAM_SEL_1',
}
SCL_COEF_RAM_SEL_0 = 0
SCL_COEF_RAM_SEL_1 = 1
SCL_COEF_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SCL_SHARP_EN'
SCL_SHARP_EN__enumvalues = {
0: 'SCL_SHARP_DISABLE',
1: 'SCL_SHARP_ENABLE',
}
SCL_SHARP_DISABLE = 0
SCL_SHARP_ENABLE = 1
SCL_SHARP_EN = ctypes.c_uint32 # enum
# values for enumeration 'CMC_3DLUT_30BIT_ENUM'
CMC_3DLUT_30BIT_ENUM__enumvalues = {
0: 'CMC_3DLUT_36BIT',
1: 'CMC_3DLUT_30BIT',
}
CMC_3DLUT_36BIT = 0
CMC_3DLUT_30BIT = 1
CMC_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CMC_3DLUT_RAM_SEL'
CMC_3DLUT_RAM_SEL__enumvalues = {
0: 'CMC_RAM0_ACCESS',
1: 'CMC_RAM1_ACCESS',
2: 'CMC_RAM2_ACCESS',
3: 'CMC_RAM3_ACCESS',
}
CMC_RAM0_ACCESS = 0
CMC_RAM1_ACCESS = 1
CMC_RAM2_ACCESS = 2
CMC_RAM3_ACCESS = 3
CMC_3DLUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CMC_3DLUT_SIZE_ENUM'
CMC_3DLUT_SIZE_ENUM__enumvalues = {
0: 'CMC_3DLUT_17CUBE',
1: 'CMC_3DLUT_9CUBE',
}
CMC_3DLUT_17CUBE = 0
CMC_3DLUT_9CUBE = 1
CMC_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CMC_LUT_2_CONFIG_ENUM'
CMC_LUT_2_CONFIG_ENUM__enumvalues = {
0: 'CMC_LUT_2CFG_NO_MEMORY',
1: 'CMC_LUT_2CFG_MEMORY_A',
2: 'CMC_LUT_2CFG_MEMORY_B',
}
CMC_LUT_2CFG_NO_MEMORY = 0
CMC_LUT_2CFG_MEMORY_A = 1
CMC_LUT_2CFG_MEMORY_B = 2
CMC_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CMC_LUT_2_MODE_ENUM'
CMC_LUT_2_MODE_ENUM__enumvalues = {
0: 'CMC_LUT_2_MODE_BYPASS',
1: 'CMC_LUT_2_MODE_RAMA_LUT',
2: 'CMC_LUT_2_MODE_RAMB_LUT',
}
CMC_LUT_2_MODE_BYPASS = 0
CMC_LUT_2_MODE_RAMA_LUT = 1
CMC_LUT_2_MODE_RAMB_LUT = 2
CMC_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CMC_LUT_NUM_SEG'
CMC_LUT_NUM_SEG__enumvalues = {
0: 'CMC_SEGMENTS_1',
1: 'CMC_SEGMENTS_2',
2: 'CMC_SEGMENTS_4',
3: 'CMC_SEGMENTS_8',
4: 'CMC_SEGMENTS_16',
5: 'CMC_SEGMENTS_32',
6: 'CMC_SEGMENTS_64',
7: 'CMC_SEGMENTS_128',
}
CMC_SEGMENTS_1 = 0
CMC_SEGMENTS_2 = 1
CMC_SEGMENTS_4 = 2
CMC_SEGMENTS_8 = 3
CMC_SEGMENTS_16 = 4
CMC_SEGMENTS_32 = 5
CMC_SEGMENTS_64 = 6
CMC_SEGMENTS_128 = 7
CMC_LUT_NUM_SEG = ctypes.c_uint32 # enum
# values for enumeration 'CMC_LUT_RAM_SEL'
CMC_LUT_RAM_SEL__enumvalues = {
0: 'CMC_RAMA_ACCESS',
1: 'CMC_RAMB_ACCESS',
}
CMC_RAMA_ACCESS = 0
CMC_RAMB_ACCESS = 1
CMC_LUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CM_BYPASS'
CM_BYPASS__enumvalues = {
0: 'NON_BYPASS',
1: 'BYPASS_EN',
}
NON_BYPASS = 0
BYPASS_EN = 1
CM_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'CM_COEF_FORMAT_ENUM'
CM_COEF_FORMAT_ENUM__enumvalues = {
0: 'FIX_S2_13',
1: 'FIX_S3_12',
}
FIX_S2_13 = 0
FIX_S3_12 = 1
CM_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_DATA_SIGNED'
CM_DATA_SIGNED__enumvalues = {
0: 'UNSIGNED',
1: 'SIGNED',
}
UNSIGNED = 0
SIGNED = 1
CM_DATA_SIGNED = ctypes.c_uint32 # enum
# values for enumeration 'CM_EN'
CM_EN__enumvalues = {
0: 'CM_DISABLE',
1: 'CM_ENABLE',
}
CM_DISABLE = 0
CM_ENABLE = 1
CM_EN = ctypes.c_uint32 # enum
# values for enumeration 'CM_GAMMA_LUT_MODE_ENUM'
CM_GAMMA_LUT_MODE_ENUM__enumvalues = {
0: 'BYPASS',
1: 'RESERVED_1',
2: 'RAM_LUT',
3: 'RESERVED_3',
}
BYPASS = 0
RESERVED_1 = 1
RAM_LUT = 2
RESERVED_3 = 3
CM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_GAMMA_LUT_PWL_DISABLE_ENUM'
CM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = {
0: 'ENABLE_PWL',
1: 'DISABLE_PWL',
}
ENABLE_PWL = 0
DISABLE_PWL = 1
CM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_GAMMA_LUT_SEL_ENUM'
CM_GAMMA_LUT_SEL_ENUM__enumvalues = {
0: 'RAMA',
1: 'RAMB',
}
RAMA = 0
RAMB = 1
CM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_2_CONFIG_ENUM'
CM_LUT_2_CONFIG_ENUM__enumvalues = {
0: 'LUT_2CFG_NO_MEMORY',
1: 'LUT_2CFG_MEMORY_A',
2: 'LUT_2CFG_MEMORY_B',
}
LUT_2CFG_NO_MEMORY = 0
LUT_2CFG_MEMORY_A = 1
LUT_2CFG_MEMORY_B = 2
CM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_2_MODE_ENUM'
CM_LUT_2_MODE_ENUM__enumvalues = {
0: 'LUT_2_MODE_BYPASS',
1: 'LUT_2_MODE_RAMA_LUT',
2: 'LUT_2_MODE_RAMB_LUT',
}
LUT_2_MODE_BYPASS = 0
LUT_2_MODE_RAMA_LUT = 1
LUT_2_MODE_RAMB_LUT = 2
CM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_4_CONFIG_ENUM'
CM_LUT_4_CONFIG_ENUM__enumvalues = {
0: 'LUT_4CFG_NO_MEMORY',
1: 'LUT_4CFG_ROM_A',
2: 'LUT_4CFG_ROM_B',
3: 'LUT_4CFG_MEMORY_A',
4: 'LUT_4CFG_MEMORY_B',
}
LUT_4CFG_NO_MEMORY = 0
LUT_4CFG_ROM_A = 1
LUT_4CFG_ROM_B = 2
LUT_4CFG_MEMORY_A = 3
LUT_4CFG_MEMORY_B = 4
CM_LUT_4_CONFIG_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_4_MODE_ENUM'
CM_LUT_4_MODE_ENUM__enumvalues = {
0: 'LUT_4_MODE_BYPASS',
1: 'LUT_4_MODE_ROMA_LUT',
2: 'LUT_4_MODE_ROMB_LUT',
3: 'LUT_4_MODE_RAMA_LUT',
4: 'LUT_4_MODE_RAMB_LUT',
}
LUT_4_MODE_BYPASS = 0
LUT_4_MODE_ROMA_LUT = 1
LUT_4_MODE_ROMB_LUT = 2
LUT_4_MODE_RAMA_LUT = 3
LUT_4_MODE_RAMB_LUT = 4
CM_LUT_4_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_CONFIG_MODE'
CM_LUT_CONFIG_MODE__enumvalues = {
0: 'DIFFERENT_RGB',
1: 'ALL_USE_R',
}
DIFFERENT_RGB = 0
ALL_USE_R = 1
CM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_NUM_SEG'
CM_LUT_NUM_SEG__enumvalues = {
0: 'SEGMENTS_1',
1: 'SEGMENTS_2',
2: 'SEGMENTS_4',
3: 'SEGMENTS_8',
4: 'SEGMENTS_16',
5: 'SEGMENTS_32',
6: 'SEGMENTS_64',
7: 'SEGMENTS_128',
}
SEGMENTS_1 = 0
SEGMENTS_2 = 1
SEGMENTS_4 = 2
SEGMENTS_8 = 3
SEGMENTS_16 = 4
SEGMENTS_32 = 5
SEGMENTS_64 = 6
SEGMENTS_128 = 7
CM_LUT_NUM_SEG = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_RAM_SEL'
CM_LUT_RAM_SEL__enumvalues = {
0: 'RAMA_ACCESS',
1: 'RAMB_ACCESS',
}
RAMA_ACCESS = 0
RAMB_ACCESS = 1
CM_LUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_READ_COLOR_SEL'
CM_LUT_READ_COLOR_SEL__enumvalues = {
0: 'BLUE_LUT',
1: 'GREEN_LUT',
2: 'RED_LUT',
}
BLUE_LUT = 0
GREEN_LUT = 1
RED_LUT = 2
CM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_READ_DBG'
CM_LUT_READ_DBG__enumvalues = {
0: 'DISABLE_DEBUG',
1: 'ENABLE_DEBUG',
}
DISABLE_DEBUG = 0
ENABLE_DEBUG = 1
CM_LUT_READ_DBG = ctypes.c_uint32 # enum
# values for enumeration 'CM_PENDING'
CM_PENDING__enumvalues = {
0: 'CM_NOT_PENDING',
1: 'CM_YES_PENDING',
}
CM_NOT_PENDING = 0
CM_YES_PENDING = 1
CM_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'CM_POST_CSC_MODE_ENUM'
CM_POST_CSC_MODE_ENUM__enumvalues = {
0: 'BYPASS_POST_CSC',
1: 'COEF_POST_CSC',
2: 'COEF_POST_CSC_B',
}
BYPASS_POST_CSC = 0
COEF_POST_CSC = 1
COEF_POST_CSC_B = 2
CM_POST_CSC_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_WRITE_BASE_ONLY'
CM_WRITE_BASE_ONLY__enumvalues = {
0: 'WRITE_BOTH',
1: 'WRITE_BASE_ONLY',
}
WRITE_BOTH = 0
WRITE_BASE_ONLY = 1
CM_WRITE_BASE_ONLY = ctypes.c_uint32 # enum
# values for enumeration 'CRC_CUR_SEL'
CRC_CUR_SEL__enumvalues = {
0: 'CRC_CUR_0',
1: 'CRC_CUR_1',
}
CRC_CUR_0 = 0
CRC_CUR_1 = 1
CRC_CUR_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_INTERLACE_SEL'
CRC_INTERLACE_SEL__enumvalues = {
0: 'CRC_INTERLACE_0',
1: 'CRC_INTERLACE_1',
2: 'CRC_INTERLACE_2',
3: 'CRC_INTERLACE_3',
}
CRC_INTERLACE_0 = 0
CRC_INTERLACE_1 = 1
CRC_INTERLACE_2 = 2
CRC_INTERLACE_3 = 3
CRC_INTERLACE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_IN_PIX_SEL'
CRC_IN_PIX_SEL__enumvalues = {
0: 'CRC_IN_PIX_0',
1: 'CRC_IN_PIX_1',
2: 'CRC_IN_PIX_2',
3: 'CRC_IN_PIX_3',
4: 'CRC_IN_PIX_4',
5: 'CRC_IN_PIX_5',
6: 'CRC_IN_PIX_6',
7: 'CRC_IN_PIX_7',
}
CRC_IN_PIX_0 = 0
CRC_IN_PIX_1 = 1
CRC_IN_PIX_2 = 2
CRC_IN_PIX_3 = 3
CRC_IN_PIX_4 = 4
CRC_IN_PIX_5 = 5
CRC_IN_PIX_6 = 6
CRC_IN_PIX_7 = 7
CRC_IN_PIX_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_SRC_SEL'
CRC_SRC_SEL__enumvalues = {
0: 'CRC_SRC_0',
1: 'CRC_SRC_1',
2: 'CRC_SRC_2',
3: 'CRC_SRC_3',
}
CRC_SRC_0 = 0
CRC_SRC_1 = 1
CRC_SRC_2 = 2
CRC_SRC_3 = 3
CRC_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_STEREO_SEL'
CRC_STEREO_SEL__enumvalues = {
0: 'CRC_STEREO_0',
1: 'CRC_STEREO_1',
2: 'CRC_STEREO_2',
3: 'CRC_STEREO_3',
}
CRC_STEREO_0 = 0
CRC_STEREO_1 = 1
CRC_STEREO_2 = 2
CRC_STEREO_3 = 3
CRC_STEREO_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TEST_CLK_SEL'
TEST_CLK_SEL__enumvalues = {
0: 'TEST_CLK_SEL_0',
1: 'TEST_CLK_SEL_1',
2: 'TEST_CLK_SEL_2',
3: 'TEST_CLK_SEL_3',
4: 'TEST_CLK_SEL_4',
5: 'TEST_CLK_SEL_5',
6: 'TEST_CLK_SEL_6',
7: 'TEST_CLK_SEL_7',
}
TEST_CLK_SEL_0 = 0
TEST_CLK_SEL_1 = 1
TEST_CLK_SEL_2 = 2
TEST_CLK_SEL_3 = 3
TEST_CLK_SEL_4 = 4
TEST_CLK_SEL_5 = 5
TEST_CLK_SEL_6 = 6
TEST_CLK_SEL_7 = 7
TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_ACTIVE'
PERFCOUNTER_ACTIVE__enumvalues = {
0: 'PERFCOUNTER_IS_IDLE',
1: 'PERFCOUNTER_IS_ACTIVE',
}
PERFCOUNTER_IS_IDLE = 0
PERFCOUNTER_IS_ACTIVE = 1
PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT0_STATE'
PERFCOUNTER_CNT0_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT0_STATE_RESET',
1: 'PERFCOUNTER_CNT0_STATE_START',
2: 'PERFCOUNTER_CNT0_STATE_FREEZE',
3: 'PERFCOUNTER_CNT0_STATE_HW',
}
PERFCOUNTER_CNT0_STATE_RESET = 0
PERFCOUNTER_CNT0_STATE_START = 1
PERFCOUNTER_CNT0_STATE_FREEZE = 2
PERFCOUNTER_CNT0_STATE_HW = 3
PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT1_STATE'
PERFCOUNTER_CNT1_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT1_STATE_RESET',
1: 'PERFCOUNTER_CNT1_STATE_START',
2: 'PERFCOUNTER_CNT1_STATE_FREEZE',
3: 'PERFCOUNTER_CNT1_STATE_HW',
}
PERFCOUNTER_CNT1_STATE_RESET = 0
PERFCOUNTER_CNT1_STATE_START = 1
PERFCOUNTER_CNT1_STATE_FREEZE = 2
PERFCOUNTER_CNT1_STATE_HW = 3
PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT2_STATE'
PERFCOUNTER_CNT2_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT2_STATE_RESET',
1: 'PERFCOUNTER_CNT2_STATE_START',
2: 'PERFCOUNTER_CNT2_STATE_FREEZE',
3: 'PERFCOUNTER_CNT2_STATE_HW',
}
PERFCOUNTER_CNT2_STATE_RESET = 0
PERFCOUNTER_CNT2_STATE_START = 1
PERFCOUNTER_CNT2_STATE_FREEZE = 2
PERFCOUNTER_CNT2_STATE_HW = 3
PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT3_STATE'
PERFCOUNTER_CNT3_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT3_STATE_RESET',
1: 'PERFCOUNTER_CNT3_STATE_START',
2: 'PERFCOUNTER_CNT3_STATE_FREEZE',
3: 'PERFCOUNTER_CNT3_STATE_HW',
}
PERFCOUNTER_CNT3_STATE_RESET = 0
PERFCOUNTER_CNT3_STATE_START = 1
PERFCOUNTER_CNT3_STATE_FREEZE = 2
PERFCOUNTER_CNT3_STATE_HW = 3
PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT4_STATE'
PERFCOUNTER_CNT4_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT4_STATE_RESET',
1: 'PERFCOUNTER_CNT4_STATE_START',
2: 'PERFCOUNTER_CNT4_STATE_FREEZE',
3: 'PERFCOUNTER_CNT4_STATE_HW',
}
PERFCOUNTER_CNT4_STATE_RESET = 0
PERFCOUNTER_CNT4_STATE_START = 1
PERFCOUNTER_CNT4_STATE_FREEZE = 2
PERFCOUNTER_CNT4_STATE_HW = 3
PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT5_STATE'
PERFCOUNTER_CNT5_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT5_STATE_RESET',
1: 'PERFCOUNTER_CNT5_STATE_START',
2: 'PERFCOUNTER_CNT5_STATE_FREEZE',
3: 'PERFCOUNTER_CNT5_STATE_HW',
}
PERFCOUNTER_CNT5_STATE_RESET = 0
PERFCOUNTER_CNT5_STATE_START = 1
PERFCOUNTER_CNT5_STATE_FREEZE = 2
PERFCOUNTER_CNT5_STATE_HW = 3
PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT6_STATE'
PERFCOUNTER_CNT6_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT6_STATE_RESET',
1: 'PERFCOUNTER_CNT6_STATE_START',
2: 'PERFCOUNTER_CNT6_STATE_FREEZE',
3: 'PERFCOUNTER_CNT6_STATE_HW',
}
PERFCOUNTER_CNT6_STATE_RESET = 0
PERFCOUNTER_CNT6_STATE_START = 1
PERFCOUNTER_CNT6_STATE_FREEZE = 2
PERFCOUNTER_CNT6_STATE_HW = 3
PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT7_STATE'
PERFCOUNTER_CNT7_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT7_STATE_RESET',
1: 'PERFCOUNTER_CNT7_STATE_START',
2: 'PERFCOUNTER_CNT7_STATE_FREEZE',
3: 'PERFCOUNTER_CNT7_STATE_HW',
}
PERFCOUNTER_CNT7_STATE_RESET = 0
PERFCOUNTER_CNT7_STATE_START = 1
PERFCOUNTER_CNT7_STATE_FREEZE = 2
PERFCOUNTER_CNT7_STATE_HW = 3
PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNTL_SEL'
PERFCOUNTER_CNTL_SEL__enumvalues = {
0: 'PERFCOUNTER_CNTL_SEL_0',
1: 'PERFCOUNTER_CNTL_SEL_1',
2: 'PERFCOUNTER_CNTL_SEL_2',
3: 'PERFCOUNTER_CNTL_SEL_3',
4: 'PERFCOUNTER_CNTL_SEL_4',
5: 'PERFCOUNTER_CNTL_SEL_5',
6: 'PERFCOUNTER_CNTL_SEL_6',
7: 'PERFCOUNTER_CNTL_SEL_7',
}
PERFCOUNTER_CNTL_SEL_0 = 0
PERFCOUNTER_CNTL_SEL_1 = 1
PERFCOUNTER_CNTL_SEL_2 = 2
PERFCOUNTER_CNTL_SEL_3 = 3
PERFCOUNTER_CNTL_SEL_4 = 4
PERFCOUNTER_CNTL_SEL_5 = 5
PERFCOUNTER_CNTL_SEL_6 = 6
PERFCOUNTER_CNTL_SEL_7 = 7
PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS'
PERFCOUNTER_CNTOFF_START_DIS__enumvalues = {
0: 'PERFCOUNTER_CNTOFF_START_ENABLE',
1: 'PERFCOUNTER_CNTOFF_START_DISABLE',
}
PERFCOUNTER_CNTOFF_START_ENABLE = 0
PERFCOUNTER_CNTOFF_START_DISABLE = 1
PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE'
PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = {
0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC',
1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX',
2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN',
}
PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0
PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1
PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2
PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CVALUE_SEL'
PERFCOUNTER_CVALUE_SEL__enumvalues = {
0: 'PERFCOUNTER_CVALUE_SEL_47_0',
1: 'PERFCOUNTER_CVALUE_SEL_15_0',
2: 'PERFCOUNTER_CVALUE_SEL_31_16',
3: 'PERFCOUNTER_CVALUE_SEL_47_32',
4: 'PERFCOUNTER_CVALUE_SEL_11_0',
5: 'PERFCOUNTER_CVALUE_SEL_23_12',
6: 'PERFCOUNTER_CVALUE_SEL_35_24',
7: 'PERFCOUNTER_CVALUE_SEL_47_36',
}
PERFCOUNTER_CVALUE_SEL_47_0 = 0
PERFCOUNTER_CVALUE_SEL_15_0 = 1
PERFCOUNTER_CVALUE_SEL_31_16 = 2
PERFCOUNTER_CVALUE_SEL_47_32 = 3
PERFCOUNTER_CVALUE_SEL_11_0 = 4
PERFCOUNTER_CVALUE_SEL_23_12 = 5
PERFCOUNTER_CVALUE_SEL_35_24 = 6
PERFCOUNTER_CVALUE_SEL_47_36 = 7
PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL'
PERFCOUNTER_HW_CNTL_SEL__enumvalues = {
0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN',
1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF',
}
PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0
PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1
PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_HW_STOP1_SEL'
PERFCOUNTER_HW_STOP1_SEL__enumvalues = {
0: 'PERFCOUNTER_HW_STOP1_0',
1: 'PERFCOUNTER_HW_STOP1_1',
}
PERFCOUNTER_HW_STOP1_0 = 0
PERFCOUNTER_HW_STOP1_1 = 1
PERFCOUNTER_HW_STOP1_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_HW_STOP2_SEL'
PERFCOUNTER_HW_STOP2_SEL__enumvalues = {
0: 'PERFCOUNTER_HW_STOP2_0',
1: 'PERFCOUNTER_HW_STOP2_1',
}
PERFCOUNTER_HW_STOP2_0 = 0
PERFCOUNTER_HW_STOP2_1 = 1
PERFCOUNTER_HW_STOP2_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_INC_MODE'
PERFCOUNTER_INC_MODE__enumvalues = {
0: 'PERFCOUNTER_INC_MODE_MULTI_BIT',
1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE',
2: 'PERFCOUNTER_INC_MODE_LSB',
3: 'PERFCOUNTER_INC_MODE_POS_EDGE',
4: 'PERFCOUNTER_INC_MODE_NEG_EDGE',
}
PERFCOUNTER_INC_MODE_MULTI_BIT = 0
PERFCOUNTER_INC_MODE_BOTH_EDGE = 1
PERFCOUNTER_INC_MODE_LSB = 2
PERFCOUNTER_INC_MODE_POS_EDGE = 3
PERFCOUNTER_INC_MODE_NEG_EDGE = 4
PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_INT_EN'
PERFCOUNTER_INT_EN__enumvalues = {
0: 'PERFCOUNTER_INT_DISABLE',
1: 'PERFCOUNTER_INT_ENABLE',
}
PERFCOUNTER_INT_DISABLE = 0
PERFCOUNTER_INT_ENABLE = 1
PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_INT_TYPE'
PERFCOUNTER_INT_TYPE__enumvalues = {
0: 'PERFCOUNTER_INT_TYPE_LEVEL',
1: 'PERFCOUNTER_INT_TYPE_PULSE',
}
PERFCOUNTER_INT_TYPE_LEVEL = 0
PERFCOUNTER_INT_TYPE_PULSE = 1
PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_OFF_MASK'
PERFCOUNTER_OFF_MASK__enumvalues = {
0: 'PERFCOUNTER_OFF_MASK_DISABLE',
1: 'PERFCOUNTER_OFF_MASK_ENABLE',
}
PERFCOUNTER_OFF_MASK_DISABLE = 0
PERFCOUNTER_OFF_MASK_ENABLE = 1
PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_RESTART_EN'
PERFCOUNTER_RESTART_EN__enumvalues = {
0: 'PERFCOUNTER_RESTART_DISABLE',
1: 'PERFCOUNTER_RESTART_ENABLE',
}
PERFCOUNTER_RESTART_DISABLE = 0
PERFCOUNTER_RESTART_ENABLE = 1
PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_RUNEN_MODE'
PERFCOUNTER_RUNEN_MODE__enumvalues = {
0: 'PERFCOUNTER_RUNEN_MODE_LEVEL',
1: 'PERFCOUNTER_RUNEN_MODE_EDGE',
}
PERFCOUNTER_RUNEN_MODE_LEVEL = 0
PERFCOUNTER_RUNEN_MODE_EDGE = 1
PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL0'
PERFCOUNTER_STATE_SEL0__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL0_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL0_LOCAL',
}
PERFCOUNTER_STATE_SEL0_GLOBAL = 0
PERFCOUNTER_STATE_SEL0_LOCAL = 1
PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL1'
PERFCOUNTER_STATE_SEL1__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL1_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL1_LOCAL',
}
PERFCOUNTER_STATE_SEL1_GLOBAL = 0
PERFCOUNTER_STATE_SEL1_LOCAL = 1
PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL2'
PERFCOUNTER_STATE_SEL2__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL2_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL2_LOCAL',
}
PERFCOUNTER_STATE_SEL2_GLOBAL = 0
PERFCOUNTER_STATE_SEL2_LOCAL = 1
PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL3'
PERFCOUNTER_STATE_SEL3__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL3_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL3_LOCAL',
}
PERFCOUNTER_STATE_SEL3_GLOBAL = 0
PERFCOUNTER_STATE_SEL3_LOCAL = 1
PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL4'
PERFCOUNTER_STATE_SEL4__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL4_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL4_LOCAL',
}
PERFCOUNTER_STATE_SEL4_GLOBAL = 0
PERFCOUNTER_STATE_SEL4_LOCAL = 1
PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL5'
PERFCOUNTER_STATE_SEL5__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL5_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL5_LOCAL',
}
PERFCOUNTER_STATE_SEL5_GLOBAL = 0
PERFCOUNTER_STATE_SEL5_LOCAL = 1
PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL6'
PERFCOUNTER_STATE_SEL6__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL6_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL6_LOCAL',
}
PERFCOUNTER_STATE_SEL6_GLOBAL = 0
PERFCOUNTER_STATE_SEL6_LOCAL = 1
PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL7'
PERFCOUNTER_STATE_SEL7__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL7_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL7_LOCAL',
}
PERFCOUNTER_STATE_SEL7_GLOBAL = 0
PERFCOUNTER_STATE_SEL7_LOCAL = 1
PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_CNTOFF_AND_OR'
PERFMON_CNTOFF_AND_OR__enumvalues = {
0: 'PERFMON_CNTOFF_OR',
1: 'PERFMON_CNTOFF_AND',
}
PERFMON_CNTOFF_OR = 0
PERFMON_CNTOFF_AND = 1
PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_CNTOFF_INT_EN'
PERFMON_CNTOFF_INT_EN__enumvalues = {
0: 'PERFMON_CNTOFF_INT_DISABLE',
1: 'PERFMON_CNTOFF_INT_ENABLE',
}
PERFMON_CNTOFF_INT_DISABLE = 0
PERFMON_CNTOFF_INT_ENABLE = 1
PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_CNTOFF_INT_TYPE'
PERFMON_CNTOFF_INT_TYPE__enumvalues = {
0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL',
1: 'PERFMON_CNTOFF_INT_TYPE_PULSE',
}
PERFMON_CNTOFF_INT_TYPE_LEVEL = 0
PERFMON_CNTOFF_INT_TYPE_PULSE = 1
PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_STATE'
PERFMON_STATE__enumvalues = {
0: 'PERFMON_STATE_RESET',
1: 'PERFMON_STATE_START',
2: 'PERFMON_STATE_FREEZE',
3: 'PERFMON_STATE_HW',
}
PERFMON_STATE_RESET = 0
PERFMON_STATE_START = 1
PERFMON_STATE_FREEZE = 2
PERFMON_STATE_HW = 3
PERFMON_STATE = ctypes.c_uint32 # enum
# values for enumeration 'BIGK_FRAGMENT_SIZE'
BIGK_FRAGMENT_SIZE__enumvalues = {
0: 'VM_PG_SIZE_4KB',
1: 'VM_PG_SIZE_8KB',
2: 'VM_PG_SIZE_16KB',
3: 'VM_PG_SIZE_32KB',
4: 'VM_PG_SIZE_64KB',
5: 'VM_PG_SIZE_128KB',
6: 'VM_PG_SIZE_256KB',
7: 'VM_PG_SIZE_512KB',
8: 'VM_PG_SIZE_1MB',
9: 'VM_PG_SIZE_2MB',
10: 'VM_PG_SIZE_4MB',
11: 'VM_PG_SIZE_8MB',
12: 'VM_PG_SIZE_16MB',
13: 'VM_PG_SIZE_32MB',
14: 'VM_PG_SIZE_64MB',
15: 'VM_PG_SIZE_128MB',
}
VM_PG_SIZE_4KB = 0
VM_PG_SIZE_8KB = 1
VM_PG_SIZE_16KB = 2
VM_PG_SIZE_32KB = 3
VM_PG_SIZE_64KB = 4
VM_PG_SIZE_128KB = 5
VM_PG_SIZE_256KB = 6
VM_PG_SIZE_512KB = 7
VM_PG_SIZE_1MB = 8
VM_PG_SIZE_2MB = 9
VM_PG_SIZE_4MB = 10
VM_PG_SIZE_8MB = 11
VM_PG_SIZE_16MB = 12
VM_PG_SIZE_32MB = 13
VM_PG_SIZE_64MB = 14
VM_PG_SIZE_128MB = 15
BIGK_FRAGMENT_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'CHUNK_SIZE'
CHUNK_SIZE__enumvalues = {
0: 'CHUNK_SIZE_1KB',
1: 'CHUNK_SIZE_2KB',
2: 'CHUNK_SIZE_4KB',
3: 'CHUNK_SIZE_8KB',
4: 'CHUNK_SIZE_16KB',
5: 'CHUNK_SIZE_32KB',
6: 'CHUNK_SIZE_64KB',
}
CHUNK_SIZE_1KB = 0
CHUNK_SIZE_2KB = 1
CHUNK_SIZE_4KB = 2
CHUNK_SIZE_8KB = 3
CHUNK_SIZE_16KB = 4
CHUNK_SIZE_32KB = 5
CHUNK_SIZE_64KB = 6
CHUNK_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'DPTE_GROUP_SIZE'
DPTE_GROUP_SIZE__enumvalues = {
0: 'DPTE_GROUP_SIZE_64B',
1: 'DPTE_GROUP_SIZE_128B',
2: 'DPTE_GROUP_SIZE_256B',
3: 'DPTE_GROUP_SIZE_512B',
4: 'DPTE_GROUP_SIZE_1024B',
5: 'DPTE_GROUP_SIZE_2048B',
}
DPTE_GROUP_SIZE_64B = 0
DPTE_GROUP_SIZE_128B = 1
DPTE_GROUP_SIZE_256B = 2
DPTE_GROUP_SIZE_512B = 3
DPTE_GROUP_SIZE_1024B = 4
DPTE_GROUP_SIZE_2048B = 5
DPTE_GROUP_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'FORCE_ONE_ROW_FOR_FRAME'
FORCE_ONE_ROW_FOR_FRAME__enumvalues = {
0: 'FORCE_ONE_ROW_FOR_FRAME_0',
1: 'FORCE_ONE_ROW_FOR_FRAME_1',
}
FORCE_ONE_ROW_FOR_FRAME_0 = 0
FORCE_ONE_ROW_FOR_FRAME_1 = 1
FORCE_ONE_ROW_FOR_FRAME = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_BLANK_EN'
HUBP_BLANK_EN__enumvalues = {
0: 'HUBP_BLANK_SW_DEASSERT',
1: 'HUBP_BLANK_SW_ASSERT',
}
HUBP_BLANK_SW_DEASSERT = 0
HUBP_BLANK_SW_ASSERT = 1
HUBP_BLANK_EN = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_IN_BLANK'
HUBP_IN_BLANK__enumvalues = {
0: 'HUBP_IN_ACTIVE',
1: 'HUBP_IN_VBLANK',
}
HUBP_IN_ACTIVE = 0
HUBP_IN_VBLANK = 1
HUBP_IN_BLANK = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_MEASURE_WIN_MODE_DCFCLK'
HUBP_MEASURE_WIN_MODE_DCFCLK__enumvalues = {
0: 'HUBP_MEASURE_WIN_MODE_DCFCLK_0',
1: 'HUBP_MEASURE_WIN_MODE_DCFCLK_1',
2: 'HUBP_MEASURE_WIN_MODE_DCFCLK_2',
3: 'HUBP_MEASURE_WIN_MODE_DCFCLK_3',
}
HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0
HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 1
HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 2
HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 3
HUBP_MEASURE_WIN_MODE_DCFCLK = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_NO_OUTSTANDING_REQ'
HUBP_NO_OUTSTANDING_REQ__enumvalues = {
0: 'OUTSTANDING_REQ',
1: 'NO_OUTSTANDING_REQ',
}
OUTSTANDING_REQ = 0
NO_OUTSTANDING_REQ = 1
HUBP_NO_OUTSTANDING_REQ = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_SOFT_RESET'
HUBP_SOFT_RESET__enumvalues = {
0: 'HUBP_SOFT_RESET_ON',
1: 'HUBP_SOFT_RESET_OFF',
}
HUBP_SOFT_RESET_ON = 0
HUBP_SOFT_RESET_OFF = 1
HUBP_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_TTU_DISABLE'
HUBP_TTU_DISABLE__enumvalues = {
0: 'HUBP_TTU_ENABLED',
1: 'HUBP_TTU_DISABLED',
}
HUBP_TTU_ENABLED = 0
HUBP_TTU_DISABLED = 1
HUBP_TTU_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_VREADY_AT_OR_AFTER_VSYNC'
HUBP_VREADY_AT_OR_AFTER_VSYNC__enumvalues = {
0: 'VREADY_BEFORE_VSYNC',
1: 'VREADY_AT_OR_AFTER_VSYNC',
}
VREADY_BEFORE_VSYNC = 0
VREADY_AT_OR_AFTER_VSYNC = 1
HUBP_VREADY_AT_OR_AFTER_VSYNC = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_VTG_SEL'
HUBP_VTG_SEL__enumvalues = {
0: 'VTG_SEL_0',
1: 'VTG_SEL_1',
2: 'VTG_SEL_2',
3: 'VTG_SEL_3',
4: 'VTG_SEL_4',
5: 'VTG_SEL_5',
}
VTG_SEL_0 = 0
VTG_SEL_1 = 1
VTG_SEL_2 = 2
VTG_SEL_3 = 3
VTG_SEL_4 = 4
VTG_SEL_5 = 5
HUBP_VTG_SEL = ctypes.c_uint32 # enum
# values for enumeration 'H_MIRROR_EN'
H_MIRROR_EN__enumvalues = {
0: 'HW_MIRRORING_DISABLE',
1: 'HW_MIRRORING_ENABLE',
}
HW_MIRRORING_DISABLE = 0
HW_MIRRORING_ENABLE = 1
H_MIRROR_EN = ctypes.c_uint32 # enum
# values for enumeration 'LEGACY_PIPE_INTERLEAVE'
LEGACY_PIPE_INTERLEAVE__enumvalues = {
0: 'LEGACY_PIPE_INTERLEAVE_256B',
1: 'LEGACY_PIPE_INTERLEAVE_512B',
}
LEGACY_PIPE_INTERLEAVE_256B = 0
LEGACY_PIPE_INTERLEAVE_512B = 1
LEGACY_PIPE_INTERLEAVE = ctypes.c_uint32 # enum
# values for enumeration 'META_CHUNK_SIZE'
META_CHUNK_SIZE__enumvalues = {
0: 'META_CHUNK_SIZE_1KB',
1: 'META_CHUNK_SIZE_2KB',
2: 'META_CHUNK_SIZE_4KB',
3: 'META_CHUNK_SIZE_8KB',
}
META_CHUNK_SIZE_1KB = 0
META_CHUNK_SIZE_2KB = 1
META_CHUNK_SIZE_4KB = 2
META_CHUNK_SIZE_8KB = 3
META_CHUNK_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'META_LINEAR'
META_LINEAR__enumvalues = {
0: 'META_SURF_TILED',
1: 'META_SURF_LINEAR',
}
META_SURF_TILED = 0
META_SURF_LINEAR = 1
META_LINEAR = ctypes.c_uint32 # enum
# values for enumeration 'MIN_CHUNK_SIZE'
MIN_CHUNK_SIZE__enumvalues = {
0: 'NO_MIN_CHUNK_SIZE',
1: 'MIN_CHUNK_SIZE_256B',
2: 'MIN_CHUNK_SIZE_512B',
3: 'MIN_CHUNK_SIZE_1024B',
}
NO_MIN_CHUNK_SIZE = 0
MIN_CHUNK_SIZE_256B = 1
MIN_CHUNK_SIZE_512B = 2
MIN_CHUNK_SIZE_1024B = 3
MIN_CHUNK_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'MIN_META_CHUNK_SIZE'
MIN_META_CHUNK_SIZE__enumvalues = {
0: 'NO_MIN_META_CHUNK_SIZE',
1: 'MIN_META_CHUNK_SIZE_64B',
2: 'MIN_META_CHUNK_SIZE_128B',
3: 'MIN_META_CHUNK_SIZE_256B',
}
NO_MIN_META_CHUNK_SIZE = 0
MIN_META_CHUNK_SIZE_64B = 1
MIN_META_CHUNK_SIZE_128B = 2
MIN_META_CHUNK_SIZE_256B = 3
MIN_META_CHUNK_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_ALIGNED'
PIPE_ALIGNED__enumvalues = {
0: 'PIPE_UNALIGNED_SURF',
1: 'PIPE_ALIGNED_SURF',
}
PIPE_UNALIGNED_SURF = 0
PIPE_ALIGNED_SURF = 1
PIPE_ALIGNED = ctypes.c_uint32 # enum
# values for enumeration 'PTE_BUFFER_MODE'
PTE_BUFFER_MODE__enumvalues = {
0: 'PTE_BUFFER_MODE_0',
1: 'PTE_BUFFER_MODE_1',
}
PTE_BUFFER_MODE_0 = 0
PTE_BUFFER_MODE_1 = 1
PTE_BUFFER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PTE_ROW_HEIGHT_LINEAR'
PTE_ROW_HEIGHT_LINEAR__enumvalues = {
0: 'PTE_ROW_HEIGHT_LINEAR_8L',
1: 'PTE_ROW_HEIGHT_LINEAR_16L',
2: 'PTE_ROW_HEIGHT_LINEAR_32L',
3: 'PTE_ROW_HEIGHT_LINEAR_64L',
4: 'PTE_ROW_HEIGHT_LINEAR_128L',
5: 'PTE_ROW_HEIGHT_LINEAR_256L',
6: 'PTE_ROW_HEIGHT_LINEAR_512L',
7: 'PTE_ROW_HEIGHT_LINEAR_1024L',
}
PTE_ROW_HEIGHT_LINEAR_8L = 0
PTE_ROW_HEIGHT_LINEAR_16L = 1
PTE_ROW_HEIGHT_LINEAR_32L = 2
PTE_ROW_HEIGHT_LINEAR_64L = 3
PTE_ROW_HEIGHT_LINEAR_128L = 4
PTE_ROW_HEIGHT_LINEAR_256L = 5
PTE_ROW_HEIGHT_LINEAR_512L = 6
PTE_ROW_HEIGHT_LINEAR_1024L = 7
PTE_ROW_HEIGHT_LINEAR = ctypes.c_uint32 # enum
# values for enumeration 'ROTATION_ANGLE'
ROTATION_ANGLE__enumvalues = {
0: 'ROTATE_0_DEGREES',
1: 'ROTATE_90_DEGREES',
2: 'ROTATE_180_DEGREES',
3: 'ROTATE_270_DEGREES',
}
ROTATE_0_DEGREES = 0
ROTATE_90_DEGREES = 1
ROTATE_180_DEGREES = 2
ROTATE_270_DEGREES = 3
ROTATION_ANGLE = ctypes.c_uint32 # enum
# values for enumeration 'SWATH_HEIGHT'
SWATH_HEIGHT__enumvalues = {
0: 'SWATH_HEIGHT_1L',
1: 'SWATH_HEIGHT_2L',
2: 'SWATH_HEIGHT_4L',
3: 'SWATH_HEIGHT_8L',
4: 'SWATH_HEIGHT_16L',
}
SWATH_HEIGHT_1L = 0
SWATH_HEIGHT_2L = 1
SWATH_HEIGHT_4L = 2
SWATH_HEIGHT_8L = 3
SWATH_HEIGHT_16L = 4
SWATH_HEIGHT = ctypes.c_uint32 # enum
# values for enumeration 'VMPG_SIZE'
VMPG_SIZE__enumvalues = {
0: 'VMPG_SIZE_4KB',
1: 'VMPG_SIZE_64KB',
}
VMPG_SIZE_4KB = 0
VMPG_SIZE_64KB = 1
VMPG_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'VM_GROUP_SIZE'
VM_GROUP_SIZE__enumvalues = {
0: 'VM_GROUP_SIZE_64B',
1: 'VM_GROUP_SIZE_128B',
2: 'VM_GROUP_SIZE_256B',
3: 'VM_GROUP_SIZE_512B',
4: 'VM_GROUP_SIZE_1024B',
5: 'VM_GROUP_SIZE_2048B',
}
VM_GROUP_SIZE_64B = 0
VM_GROUP_SIZE_128B = 1
VM_GROUP_SIZE_256B = 2
VM_GROUP_SIZE_512B = 3
VM_GROUP_SIZE_1024B = 4
VM_GROUP_SIZE_2048B = 5
VM_GROUP_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'DFQ_MIN_FREE_ENTRIES'
DFQ_MIN_FREE_ENTRIES__enumvalues = {
0: 'DFQ_MIN_FREE_ENTRIES_0',
1: 'DFQ_MIN_FREE_ENTRIES_1',
2: 'DFQ_MIN_FREE_ENTRIES_2',
3: 'DFQ_MIN_FREE_ENTRIES_3',
4: 'DFQ_MIN_FREE_ENTRIES_4',
5: 'DFQ_MIN_FREE_ENTRIES_5',
6: 'DFQ_MIN_FREE_ENTRIES_6',
7: 'DFQ_MIN_FREE_ENTRIES_7',
}
DFQ_MIN_FREE_ENTRIES_0 = 0
DFQ_MIN_FREE_ENTRIES_1 = 1
DFQ_MIN_FREE_ENTRIES_2 = 2
DFQ_MIN_FREE_ENTRIES_3 = 3
DFQ_MIN_FREE_ENTRIES_4 = 4
DFQ_MIN_FREE_ENTRIES_5 = 5
DFQ_MIN_FREE_ENTRIES_6 = 6
DFQ_MIN_FREE_ENTRIES_7 = 7
DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum
# values for enumeration 'DFQ_NUM_ENTRIES'
DFQ_NUM_ENTRIES__enumvalues = {
0: 'DFQ_NUM_ENTRIES_0',
1: 'DFQ_NUM_ENTRIES_1',
2: 'DFQ_NUM_ENTRIES_2',
3: 'DFQ_NUM_ENTRIES_3',
4: 'DFQ_NUM_ENTRIES_4',
5: 'DFQ_NUM_ENTRIES_5',
6: 'DFQ_NUM_ENTRIES_6',
7: 'DFQ_NUM_ENTRIES_7',
8: 'DFQ_NUM_ENTRIES_8',
}
DFQ_NUM_ENTRIES_0 = 0
DFQ_NUM_ENTRIES_1 = 1
DFQ_NUM_ENTRIES_2 = 2
DFQ_NUM_ENTRIES_3 = 3
DFQ_NUM_ENTRIES_4 = 4
DFQ_NUM_ENTRIES_5 = 5
DFQ_NUM_ENTRIES_6 = 6
DFQ_NUM_ENTRIES_7 = 7
DFQ_NUM_ENTRIES_8 = 8
DFQ_NUM_ENTRIES = ctypes.c_uint32 # enum
# values for enumeration 'DFQ_SIZE'
DFQ_SIZE__enumvalues = {
0: 'DFQ_SIZE_0',
1: 'DFQ_SIZE_1',
2: 'DFQ_SIZE_2',
3: 'DFQ_SIZE_3',
4: 'DFQ_SIZE_4',
5: 'DFQ_SIZE_5',
6: 'DFQ_SIZE_6',
7: 'DFQ_SIZE_7',
}
DFQ_SIZE_0 = 0
DFQ_SIZE_1 = 1
DFQ_SIZE_2 = 2
DFQ_SIZE_3 = 3
DFQ_SIZE_4 = 4
DFQ_SIZE_5 = 5
DFQ_SIZE_6 = 6
DFQ_SIZE_7 = 7
DFQ_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_VM_DONE'
DMDATA_VM_DONE__enumvalues = {
0: 'DMDATA_VM_IS_NOT_DONE',
1: 'DMDATA_VM_IS_DONE',
}
DMDATA_VM_IS_NOT_DONE = 0
DMDATA_VM_IS_DONE = 1
DMDATA_VM_DONE = ctypes.c_uint32 # enum
# values for enumeration 'EXPANSION_MODE'
EXPANSION_MODE__enumvalues = {
0: 'EXPANSION_MODE_ZERO',
1: 'EXPANSION_MODE_CONSERVATIVE',
2: 'EXPANSION_MODE_OPTIMAL',
}
EXPANSION_MODE_ZERO = 0
EXPANSION_MODE_CONSERVATIVE = 1
EXPANSION_MODE_OPTIMAL = 2
EXPANSION_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FLIP_RATE'
FLIP_RATE__enumvalues = {
0: 'FLIP_RATE_0',
1: 'FLIP_RATE_1',
2: 'FLIP_RATE_2',
3: 'FLIP_RATE_3',
4: 'FLIP_RATE_4',
5: 'FLIP_RATE_5',
6: 'FLIP_RATE_6',
7: 'FLIP_RATE_7',
}
FLIP_RATE_0 = 0
FLIP_RATE_1 = 1
FLIP_RATE_2 = 2
FLIP_RATE_3 = 3
FLIP_RATE_4 = 4
FLIP_RATE_5 = 5
FLIP_RATE_6 = 6
FLIP_RATE_7 = 7
FLIP_RATE = ctypes.c_uint32 # enum
# values for enumeration 'INT_MASK'
INT_MASK__enumvalues = {
0: 'INT_DISABLED',
1: 'INT_ENABLED',
}
INT_DISABLED = 0
INT_ENABLED = 1
INT_MASK = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_IN_FLUSH_URGENT'
PIPE_IN_FLUSH_URGENT__enumvalues = {
0: 'PIPE_IN_FLUSH_URGENT_ENABLE',
1: 'PIPE_IN_FLUSH_URGENT_DISABLE',
}
PIPE_IN_FLUSH_URGENT_ENABLE = 0
PIPE_IN_FLUSH_URGENT_DISABLE = 1
PIPE_IN_FLUSH_URGENT = ctypes.c_uint32 # enum
# values for enumeration 'PRQ_MRQ_FLUSH_URGENT'
PRQ_MRQ_FLUSH_URGENT__enumvalues = {
0: 'PRQ_MRQ_FLUSH_URGENT_ENABLE',
1: 'PRQ_MRQ_FLUSH_URGENT_DISABLE',
}
PRQ_MRQ_FLUSH_URGENT_ENABLE = 0
PRQ_MRQ_FLUSH_URGENT_DISABLE = 1
PRQ_MRQ_FLUSH_URGENT = ctypes.c_uint32 # enum
# values for enumeration 'ROW_TTU_MODE'
ROW_TTU_MODE__enumvalues = {
0: 'END_OF_ROW_MODE',
1: 'WATERMARK_MODE',
}
END_OF_ROW_MODE = 0
WATERMARK_MODE = 1
ROW_TTU_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_DCC'
SURFACE_DCC__enumvalues = {
0: 'SURFACE_IS_NOT_DCC',
1: 'SURFACE_IS_DCC',
}
SURFACE_IS_NOT_DCC = 0
SURFACE_IS_DCC = 1
SURFACE_DCC = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_DCC_IND_128B'
SURFACE_DCC_IND_128B__enumvalues = {
0: 'SURFACE_DCC_IS_NOT_IND_128B',
1: 'SURFACE_DCC_IS_IND_128B',
}
SURFACE_DCC_IS_NOT_IND_128B = 0
SURFACE_DCC_IS_IND_128B = 1
SURFACE_DCC_IND_128B = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_DCC_IND_64B'
SURFACE_DCC_IND_64B__enumvalues = {
0: 'SURFACE_DCC_IS_NOT_IND_64B',
1: 'SURFACE_DCC_IS_IND_64B',
}
SURFACE_DCC_IS_NOT_IND_64B = 0
SURFACE_DCC_IS_IND_64B = 1
SURFACE_DCC_IND_64B = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_DCC_IND_BLK'
SURFACE_DCC_IND_BLK__enumvalues = {
0: 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED',
1: 'SURFACE_DCC_BLOCK_IS_IND_64B',
2: 'SURFACE_DCC_BLOCK_IS_IND_128B',
3: 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL',
}
SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0
SURFACE_DCC_BLOCK_IS_IND_64B = 1
SURFACE_DCC_BLOCK_IS_IND_128B = 2
SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 3
SURFACE_DCC_IND_BLK = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_AWAY_INT_TYPE'
SURFACE_FLIP_AWAY_INT_TYPE__enumvalues = {
0: 'SURFACE_FLIP_AWAY_INT_LEVEL',
1: 'SURFACE_FLIP_AWAY_INT_PULSE',
}
SURFACE_FLIP_AWAY_INT_LEVEL = 0
SURFACE_FLIP_AWAY_INT_PULSE = 1
SURFACE_FLIP_AWAY_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_EXEC_DEBUG_MODE'
SURFACE_FLIP_EXEC_DEBUG_MODE__enumvalues = {
0: 'SURFACE_FLIP_EXEC_NORMAL_MODE',
1: 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE',
}
SURFACE_FLIP_EXEC_NORMAL_MODE = 0
SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 1
SURFACE_FLIP_EXEC_DEBUG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_INT_TYPE'
SURFACE_FLIP_INT_TYPE__enumvalues = {
0: 'SURFACE_FLIP_INT_LEVEL',
1: 'SURFACE_FLIP_INT_PULSE',
}
SURFACE_FLIP_INT_LEVEL = 0
SURFACE_FLIP_INT_PULSE = 1
SURFACE_FLIP_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_IN_STEREOSYNC'
SURFACE_FLIP_IN_STEREOSYNC__enumvalues = {
0: 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE',
1: 'SURFACE_FLIP_IN_STEREOSYNC_MODE',
}
SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0
SURFACE_FLIP_IN_STEREOSYNC_MODE = 1
SURFACE_FLIP_IN_STEREOSYNC = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_MODE_FOR_STEREOSYNC'
SURFACE_FLIP_MODE_FOR_STEREOSYNC__enumvalues = {
0: 'FLIP_ANY_FRAME',
1: 'FLIP_LEFT_EYE',
2: 'FLIP_RIGHT_EYE',
3: 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED',
}
FLIP_ANY_FRAME = 0
FLIP_LEFT_EYE = 1
FLIP_RIGHT_EYE = 2
SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 3
SURFACE_FLIP_MODE_FOR_STEREOSYNC = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_DISABLE'
SURFACE_FLIP_STEREO_SELECT_DISABLE__enumvalues = {
0: 'SURFACE_FLIP_STEREO_SELECT_ENABLED',
1: 'SURFACE_FLIP_STEREO_SELECT_DISABLED',
}
SURFACE_FLIP_STEREO_SELECT_ENABLED = 0
SURFACE_FLIP_STEREO_SELECT_DISABLED = 1
SURFACE_FLIP_STEREO_SELECT_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_POLARITY'
SURFACE_FLIP_STEREO_SELECT_POLARITY__enumvalues = {
0: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT',
1: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT',
}
SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0
SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 1
SURFACE_FLIP_STEREO_SELECT_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_TYPE'
SURFACE_FLIP_TYPE__enumvalues = {
0: 'SURFACE_V_FLIP',
1: 'SURFACE_I_FLIP',
}
SURFACE_V_FLIP = 0
SURFACE_I_FLIP = 1
SURFACE_FLIP_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_VUPDATE_SKIP_NUM'
SURFACE_FLIP_VUPDATE_SKIP_NUM__enumvalues = {
0: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0',
1: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1',
2: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2',
3: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3',
4: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4',
5: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5',
6: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6',
7: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7',
8: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8',
9: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9',
10: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10',
11: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11',
12: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12',
13: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13',
14: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14',
15: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15',
}
SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0
SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 1
SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 2
SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 3
SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 4
SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 5
SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 6
SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 7
SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 8
SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 9
SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 10
SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 11
SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 12
SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 13
SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 14
SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 15
SURFACE_FLIP_VUPDATE_SKIP_NUM = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_INUSE_RAED_NO_LATCH'
SURFACE_INUSE_RAED_NO_LATCH__enumvalues = {
0: 'SURFACE_INUSE_IS_LATCHED',
1: 'SURFACE_INUSE_IS_NOT_LATCHED',
}
SURFACE_INUSE_IS_LATCHED = 0
SURFACE_INUSE_IS_NOT_LATCHED = 1
SURFACE_INUSE_RAED_NO_LATCH = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_TMZ'
SURFACE_TMZ__enumvalues = {
0: 'SURFACE_IS_NOT_TMZ',
1: 'SURFACE_IS_TMZ',
}
SURFACE_IS_NOT_TMZ = 0
SURFACE_IS_TMZ = 1
SURFACE_TMZ = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_UPDATE_LOCK'
SURFACE_UPDATE_LOCK__enumvalues = {
0: 'SURFACE_UPDATE_IS_UNLOCKED',
1: 'SURFACE_UPDATE_IS_LOCKED',
}
SURFACE_UPDATE_IS_UNLOCKED = 0
SURFACE_UPDATE_IS_LOCKED = 1
SURFACE_UPDATE_LOCK = ctypes.c_uint32 # enum
# values for enumeration 'CROSSBAR_FOR_ALPHA'
CROSSBAR_FOR_ALPHA__enumvalues = {
0: 'ALPHA_DATA_ONTO_ALPHA_PORT',
1: 'Y_G_DATA_ONTO_ALPHA_PORT',
2: 'CB_B_DATA_ONTO_ALPHA_PORT',
3: 'CR_R_DATA_ONTO_ALPHA_PORT',
}
ALPHA_DATA_ONTO_ALPHA_PORT = 0
Y_G_DATA_ONTO_ALPHA_PORT = 1
CB_B_DATA_ONTO_ALPHA_PORT = 2
CR_R_DATA_ONTO_ALPHA_PORT = 3
CROSSBAR_FOR_ALPHA = ctypes.c_uint32 # enum
# values for enumeration 'CROSSBAR_FOR_CB_B'
CROSSBAR_FOR_CB_B__enumvalues = {
0: 'ALPHA_DATA_ONTO_CB_B_PORT',
1: 'Y_G_DATA_ONTO_CB_B_PORT',
2: 'CB_B_DATA_ONTO_CB_B_PORT',
3: 'CR_R_DATA_ONTO_CB_B_PORT',
}
ALPHA_DATA_ONTO_CB_B_PORT = 0
Y_G_DATA_ONTO_CB_B_PORT = 1
CB_B_DATA_ONTO_CB_B_PORT = 2
CR_R_DATA_ONTO_CB_B_PORT = 3
CROSSBAR_FOR_CB_B = ctypes.c_uint32 # enum
# values for enumeration 'CROSSBAR_FOR_CR_R'
CROSSBAR_FOR_CR_R__enumvalues = {
0: 'ALPHA_DATA_ONTO_CR_R_PORT',
1: 'Y_G_DATA_ONTO_CR_R_PORT',
2: 'CB_B_DATA_ONTO_CR_R_PORT',
3: 'CR_R_DATA_ONTO_CR_R_PORT',
}
ALPHA_DATA_ONTO_CR_R_PORT = 0
Y_G_DATA_ONTO_CR_R_PORT = 1
CB_B_DATA_ONTO_CR_R_PORT = 2
CR_R_DATA_ONTO_CR_R_PORT = 3
CROSSBAR_FOR_CR_R = ctypes.c_uint32 # enum
# values for enumeration 'CROSSBAR_FOR_Y_G'
CROSSBAR_FOR_Y_G__enumvalues = {
0: 'ALPHA_DATA_ONTO_Y_G_PORT',
1: 'Y_G_DATA_ONTO_Y_G_PORT',
2: 'CB_B_DATA_ONTO_Y_G_PORT',
3: 'CR_R_DATA_ONTO_Y_G_PORT',
}
ALPHA_DATA_ONTO_Y_G_PORT = 0
Y_G_DATA_ONTO_Y_G_PORT = 1
CB_B_DATA_ONTO_Y_G_PORT = 2
CR_R_DATA_ONTO_Y_G_PORT = 3
CROSSBAR_FOR_Y_G = ctypes.c_uint32 # enum
# values for enumeration 'DETILE_BUFFER_PACKER_ENABLE'
DETILE_BUFFER_PACKER_ENABLE__enumvalues = {
0: 'DETILE_BUFFER_PACKER_IS_DISABLE',
1: 'DETILE_BUFFER_PACKER_IS_ENABLE',
}
DETILE_BUFFER_PACKER_IS_DISABLE = 0
DETILE_BUFFER_PACKER_IS_ENABLE = 1
DETILE_BUFFER_PACKER_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_DIS_MODE'
MEM_PWR_DIS_MODE__enumvalues = {
0: 'MEM_POWER_DIS_MODE_ENABLE',
1: 'MEM_POWER_DIS_MODE_DISABLE',
}
MEM_POWER_DIS_MODE_ENABLE = 0
MEM_POWER_DIS_MODE_DISABLE = 1
MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_FORCE_MODE'
MEM_PWR_FORCE_MODE__enumvalues = {
0: 'MEM_POWER_FORCE_MODE_OFF',
1: 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP',
2: 'MEM_POWER_FORCE_MODE_DEEP_SLEEP',
3: 'MEM_POWER_FORCE_MODE_SHUT_DOWN',
}
MEM_POWER_FORCE_MODE_OFF = 0
MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 1
MEM_POWER_FORCE_MODE_DEEP_SLEEP = 2
MEM_POWER_FORCE_MODE_SHUT_DOWN = 3
MEM_PWR_FORCE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_STATUS'
MEM_PWR_STATUS__enumvalues = {
0: 'MEM_POWER_STATUS_ON',
1: 'MEM_POWER_STATUS_LIGHT_SLEEP',
2: 'MEM_POWER_STATUS_DEEP_SLEEP',
3: 'MEM_POWER_STATUS_SHUT_DOWN',
}
MEM_POWER_STATUS_ON = 0
MEM_POWER_STATUS_LIGHT_SLEEP = 1
MEM_POWER_STATUS_DEEP_SLEEP = 2
MEM_POWER_STATUS_SHUT_DOWN = 3
MEM_PWR_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_INT_MASK_MODE'
PIPE_INT_MASK_MODE__enumvalues = {
0: 'PIPE_INT_MASK_MODE_DISABLE',
1: 'PIPE_INT_MASK_MODE_ENABLE',
}
PIPE_INT_MASK_MODE_DISABLE = 0
PIPE_INT_MASK_MODE_ENABLE = 1
PIPE_INT_MASK_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_INT_TYPE_MODE'
PIPE_INT_TYPE_MODE__enumvalues = {
0: 'PIPE_INT_TYPE_MODE_DISABLE',
1: 'PIPE_INT_TYPE_MODE_ENABLE',
}
PIPE_INT_TYPE_MODE_DISABLE = 0
PIPE_INT_TYPE_MODE_ENABLE = 1
PIPE_INT_TYPE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE'
PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = {
0: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
1: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1',
}
PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0
PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1
PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CROB_MEM_PWR_LIGHT_SLEEP_MODE'
CROB_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = {
0: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
1: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1',
2: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2',
}
CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0
CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1
CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2
CROB_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_2X_MAGNIFY'
CURSOR_2X_MAGNIFY__enumvalues = {
0: 'CURSOR_2X_MAGNIFY_IS_DISABLE',
1: 'CURSOR_2X_MAGNIFY_IS_ENABLE',
}
CURSOR_2X_MAGNIFY_IS_DISABLE = 0
CURSOR_2X_MAGNIFY_IS_ENABLE = 1
CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_ENABLE'
CURSOR_ENABLE__enumvalues = {
0: 'CURSOR_IS_DISABLE',
1: 'CURSOR_IS_ENABLE',
}
CURSOR_IS_DISABLE = 0
CURSOR_IS_ENABLE = 1
CURSOR_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_LINES_PER_CHUNK'
CURSOR_LINES_PER_CHUNK__enumvalues = {
0: 'CURSOR_LINE_PER_CHUNK_1',
1: 'CURSOR_LINE_PER_CHUNK_2',
2: 'CURSOR_LINE_PER_CHUNK_4',
3: 'CURSOR_LINE_PER_CHUNK_8',
4: 'CURSOR_LINE_PER_CHUNK_16',
}
CURSOR_LINE_PER_CHUNK_1 = 0
CURSOR_LINE_PER_CHUNK_2 = 1
CURSOR_LINE_PER_CHUNK_4 = 2
CURSOR_LINE_PER_CHUNK_8 = 3
CURSOR_LINE_PER_CHUNK_16 = 4
CURSOR_LINES_PER_CHUNK = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_MODE'
CURSOR_MODE__enumvalues = {
0: 'CURSOR_MONO_2BIT',
1: 'CURSOR_COLOR_24BIT_1BIT_AND',
2: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT',
3: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT',
4: 'CURSOR_COLOR_64BIT_FP_PREMULT',
5: 'CURSOR_COLOR_64BIT_FP_UNPREMULT',
}
CURSOR_MONO_2BIT = 0
CURSOR_COLOR_24BIT_1BIT_AND = 1
CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 2
CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3
CURSOR_COLOR_64BIT_FP_PREMULT = 4
CURSOR_COLOR_64BIT_FP_UNPREMULT = 5
CURSOR_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_EN'
CURSOR_PERFMON_LATENCY_MEASURE_EN__enumvalues = {
0: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED',
1: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED',
}
CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0
CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 1
CURSOR_PERFMON_LATENCY_MEASURE_EN = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_SEL'
CURSOR_PERFMON_LATENCY_MEASURE_SEL__enumvalues = {
0: 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY',
1: 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY',
}
CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0
CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 1
CURSOR_PERFMON_LATENCY_MEASURE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_PITCH'
CURSOR_PITCH__enumvalues = {
0: 'CURSOR_PITCH_64_PIXELS',
1: 'CURSOR_PITCH_128_PIXELS',
2: 'CURSOR_PITCH_256_PIXELS',
}
CURSOR_PITCH_64_PIXELS = 0
CURSOR_PITCH_128_PIXELS = 1
CURSOR_PITCH_256_PIXELS = 2
CURSOR_PITCH = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_REQ_MODE'
CURSOR_REQ_MODE__enumvalues = {
0: 'CURSOR_REQUEST_NORMALLY',
1: 'CURSOR_REQUEST_EARLY',
}
CURSOR_REQUEST_NORMALLY = 0
CURSOR_REQUEST_EARLY = 1
CURSOR_REQ_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_SNOOP'
CURSOR_SNOOP__enumvalues = {
0: 'CURSOR_IS_NOT_SNOOP',
1: 'CURSOR_IS_SNOOP',
}
CURSOR_IS_NOT_SNOOP = 0
CURSOR_IS_SNOOP = 1
CURSOR_SNOOP = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_STEREO_EN'
CURSOR_STEREO_EN__enumvalues = {
0: 'CURSOR_STEREO_IS_DISABLED',
1: 'CURSOR_STEREO_IS_ENABLED',
}
CURSOR_STEREO_IS_DISABLED = 0
CURSOR_STEREO_IS_ENABLED = 1
CURSOR_STEREO_EN = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_SURFACE_TMZ'
CURSOR_SURFACE_TMZ__enumvalues = {
0: 'CURSOR_SURFACE_IS_NOT_TMZ',
1: 'CURSOR_SURFACE_IS_TMZ',
}
CURSOR_SURFACE_IS_NOT_TMZ = 0
CURSOR_SURFACE_IS_TMZ = 1
CURSOR_SURFACE_TMZ = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_SYSTEM'
CURSOR_SYSTEM__enumvalues = {
0: 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS',
1: 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS',
}
CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0
CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 1
CURSOR_SYSTEM = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS'
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__enumvalues = {
0: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0',
1: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1',
}
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 1
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_DONE'
DMDATA_DONE__enumvalues = {
0: 'DMDATA_NOT_SENT_TO_DIG',
1: 'DMDATA_SENT_TO_DIG',
}
DMDATA_NOT_SENT_TO_DIG = 0
DMDATA_SENT_TO_DIG = 1
DMDATA_DONE = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_MODE'
DMDATA_MODE__enumvalues = {
0: 'DMDATA_SOFTWARE_UPDATE_MODE',
1: 'DMDATA_HARDWARE_UPDATE_MODE',
}
DMDATA_SOFTWARE_UPDATE_MODE = 0
DMDATA_HARDWARE_UPDATE_MODE = 1
DMDATA_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_QOS_MODE'
DMDATA_QOS_MODE__enumvalues = {
0: 'DMDATA_QOS_LEVEL_FROM_TTU',
1: 'DMDATA_QOS_LEVEL_FROM_SOFTWARE',
}
DMDATA_QOS_LEVEL_FROM_TTU = 0
DMDATA_QOS_LEVEL_FROM_SOFTWARE = 1
DMDATA_QOS_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_REPEAT'
DMDATA_REPEAT__enumvalues = {
0: 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY',
1: 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES',
}
DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0
DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 1
DMDATA_REPEAT = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_UNDERFLOW'
DMDATA_UNDERFLOW__enumvalues = {
0: 'DMDATA_NOT_UNDERFLOW',
1: 'DMDATA_UNDERFLOWED',
}
DMDATA_NOT_UNDERFLOW = 0
DMDATA_UNDERFLOWED = 1
DMDATA_UNDERFLOW = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_UNDERFLOW_CLEAR'
DMDATA_UNDERFLOW_CLEAR__enumvalues = {
0: 'DMDATA_DONT_CLEAR',
1: 'DMDATA_CLEAR_UNDERFLOW_STATUS',
}
DMDATA_DONT_CLEAR = 0
DMDATA_CLEAR_UNDERFLOW_STATUS = 1
DMDATA_UNDERFLOW_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_UPDATED'
DMDATA_UPDATED__enumvalues = {
0: 'DMDATA_NOT_UPDATED',
1: 'DMDATA_WAS_UPDATED',
}
DMDATA_NOT_UPDATED = 0
DMDATA_WAS_UPDATED = 1
DMDATA_UPDATED = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_3DLUT_ADDRESSING_MODE'
HUBP_3DLUT_ADDRESSING_MODE__enumvalues = {
0: 'HUBP_3DLUT_SW_LINEAR',
1: 'HUBP_3DLUT_SIMPLE_LINEAR',
}
HUBP_3DLUT_SW_LINEAR = 0
HUBP_3DLUT_SIMPLE_LINEAR = 1
HUBP_3DLUT_ADDRESSING_MODE = ctypes.c_uint32 # enum
# values for enumeration 'RESPONSE_STATUS'
RESPONSE_STATUS__enumvalues = {
0: 'OKAY',
1: 'EXOKAY',
2: 'SLVERR',
3: 'DECERR',
4: 'EARLY',
5: 'OKAY_NODATA',
6: 'PROTVIOL',
7: 'TRANSERR',
8: 'CMPTO',
12: 'CRS',
}
OKAY = 0
EXOKAY = 1
SLVERR = 2
DECERR = 3
EARLY = 4
OKAY_NODATA = 5
PROTVIOL = 6
TRANSERR = 7
CMPTO = 8
CRS = 12
RESPONSE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE'
DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = {
0: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
1: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1',
2: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2',
}
DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0
DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1
DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2
DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DCHUBBUB_MEM_PWR_DIS_MODE'
DCHUBBUB_MEM_PWR_DIS_MODE__enumvalues = {
0: 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE',
1: 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE',
}
DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0
DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 1
DCHUBBUB_MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DCHUBBUB_MEM_PWR_MODE'
DCHUBBUB_MEM_PWR_MODE__enumvalues = {
0: 'DCHUBBUB_MEM_POWER_MODE_OFF',
1: 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP',
2: 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP',
3: 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN',
}
DCHUBBUB_MEM_POWER_MODE_OFF = 0
DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 1
DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 2
DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 3
DCHUBBUB_MEM_PWR_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_3DLUT_FL_FORMAT'
MPC_CFG_3DLUT_FL_FORMAT__enumvalues = {
0: 'MPC_CFG_3DLUT_FL_FORMAT_0',
1: 'MPC_CFG_3DLUT_FL_FORMAT_1',
2: 'MPC_CFG_3DLUT_FL_FORMAT_2',
}
MPC_CFG_3DLUT_FL_FORMAT_0 = 0
MPC_CFG_3DLUT_FL_FORMAT_1 = 1
MPC_CFG_3DLUT_FL_FORMAT_2 = 2
MPC_CFG_3DLUT_FL_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_3DLUT_FL_MODE'
MPC_CFG_3DLUT_FL_MODE__enumvalues = {
0: 'MPC_CFG_3DLUT_FL_MODE_0',
1: 'MPC_CFG_3DLUT_FL_MODE_1',
2: 'MPC_CFG_3DLUT_FL_MODE_2',
3: 'MPC_CFG_3DLUT_FL_MODE_3',
}
MPC_CFG_3DLUT_FL_MODE_0 = 0
MPC_CFG_3DLUT_FL_MODE_1 = 1
MPC_CFG_3DLUT_FL_MODE_2 = 2
MPC_CFG_3DLUT_FL_MODE_3 = 3
MPC_CFG_3DLUT_FL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET'
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET'
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_ADR_VUPDATE_LOCK_SET'
MPC_CFG_ADR_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_ADR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_CFG_VUPDATE_LOCK_SET'
MPC_CFG_CFG_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_CUR_VUPDATE_LOCK_SET'
MPC_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_MPC_TEST_CLK_SEL'
MPC_CFG_MPC_TEST_CLK_SEL__enumvalues = {
0: 'MPC_CFG_MPC_TEST_CLK_SEL_0',
1: 'MPC_CFG_MPC_TEST_CLK_SEL_1',
2: 'MPC_CFG_MPC_TEST_CLK_SEL_2',
3: 'MPC_CFG_MPC_TEST_CLK_SEL_3',
}
MPC_CFG_MPC_TEST_CLK_SEL_0 = 0
MPC_CFG_MPC_TEST_CLK_SEL_1 = 1
MPC_CFG_MPC_TEST_CLK_SEL_2 = 2
MPC_CFG_MPC_TEST_CLK_SEL_3 = 3
MPC_CFG_MPC_TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN'
MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN__enumvalues = {
0: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE',
1: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE',
}
MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0
MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 1
MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CRC_CALC_INTERLACE_MODE'
MPC_CRC_CALC_INTERLACE_MODE__enumvalues = {
0: 'MPC_CRC_INTERLACE_MODE_TOP',
1: 'MPC_CRC_INTERLACE_MODE_BOTTOM',
2: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM',
3: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH',
}
MPC_CRC_INTERLACE_MODE_TOP = 0
MPC_CRC_INTERLACE_MODE_BOTTOM = 1
MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 2
MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 3
MPC_CRC_CALC_INTERLACE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CRC_CALC_MODE'
MPC_CRC_CALC_MODE__enumvalues = {
0: 'MPC_CRC_ONE_SHOT_MODE',
1: 'MPC_CRC_CONTINUOUS_MODE',
}
MPC_CRC_ONE_SHOT_MODE = 0
MPC_CRC_CONTINUOUS_MODE = 1
MPC_CRC_CALC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CRC_CALC_STEREO_MODE'
MPC_CRC_CALC_STEREO_MODE__enumvalues = {
0: 'MPC_CRC_STEREO_MODE_LEFT',
1: 'MPC_CRC_STEREO_MODE_RIGHT',
2: 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT',
3: 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH',
}
MPC_CRC_STEREO_MODE_LEFT = 0
MPC_CRC_STEREO_MODE_RIGHT = 1
MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 2
MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 3
MPC_CRC_CALC_STEREO_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CRC_SOURCE_SELECT'
MPC_CRC_SOURCE_SELECT__enumvalues = {
0: 'MPC_CRC_SOURCE_SEL_DPP',
1: 'MPC_CRC_SOURCE_SEL_OPP',
2: 'MPC_CRC_SOURCE_SEL_DWB',
3: 'MPC_CRC_SOURCE_SEL_OTHER',
}
MPC_CRC_SOURCE_SEL_DPP = 0
MPC_CRC_SOURCE_SEL_OPP = 1
MPC_CRC_SOURCE_SEL_DWB = 2
MPC_CRC_SOURCE_SEL_OTHER = 3
MPC_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OCSC_COEF_FORMAT'
MPC_OCSC_COEF_FORMAT__enumvalues = {
0: 'MPC_OCSC_COEF_FORMAT_S2_13',
1: 'MPC_OCSC_COEF_FORMAT_S3_12',
}
MPC_OCSC_COEF_FORMAT_S2_13 = 0
MPC_OCSC_COEF_FORMAT_S3_12 = 1
MPC_OCSC_COEF_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN'
MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN__enumvalues = {
0: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE',
1: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE',
}
MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0
MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 1
MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OUT_CSC_MODE'
MPC_OUT_CSC_MODE__enumvalues = {
0: 'MPC_OUT_CSC_MODE_0',
1: 'MPC_OUT_CSC_MODE_1',
2: 'MPC_OUT_CSC_MODE_2',
3: 'MPC_OUT_CSC_MODE_RSV',
}
MPC_OUT_CSC_MODE_0 = 0
MPC_OUT_CSC_MODE_1 = 1
MPC_OUT_CSC_MODE_2 = 2
MPC_OUT_CSC_MODE_RSV = 3
MPC_OUT_CSC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE'
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE__enumvalues = {
0: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS',
1: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS',
2: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS',
3: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS',
4: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS',
5: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS',
6: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS',
7: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH',
}
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 1
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 2
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 3
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 4
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 5
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 6
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 7
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OUT_RATE_CONTROL_DISABLE_SET'
MPC_OUT_RATE_CONTROL_DISABLE_SET__enumvalues = {
0: 'MPC_OUT_RATE_CONTROL_SET_ENABLE',
1: 'MPC_OUT_RATE_CONTROL_SET_DISABLE',
}
MPC_OUT_RATE_CONTROL_SET_ENABLE = 0
MPC_OUT_RATE_CONTROL_SET_DISABLE = 1
MPC_OUT_RATE_CONTROL_DISABLE_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_BG_COLOR_BPC'
MPCC_BG_COLOR_BPC__enumvalues = {
0: 'MPCC_BG_COLOR_BPC_8bit',
1: 'MPCC_BG_COLOR_BPC_9bit',
2: 'MPCC_BG_COLOR_BPC_10bit',
3: 'MPCC_BG_COLOR_BPC_11bit',
4: 'MPCC_BG_COLOR_BPC_12bit',
}
MPCC_BG_COLOR_BPC_8bit = 0
MPCC_BG_COLOR_BPC_9bit = 1
MPCC_BG_COLOR_BPC_10bit = 2
MPCC_BG_COLOR_BPC_11bit = 3
MPCC_BG_COLOR_BPC_12bit = 4
MPCC_BG_COLOR_BPC = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY'
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY__enumvalues = {
0: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE',
1: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE',
}
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 1
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE'
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE__enumvalues = {
0: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA',
1: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN',
2: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA',
3: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED',
}
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 2
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 3
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE'
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE__enumvalues = {
0: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE',
1: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE',
}
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 1
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE'
MPCC_CONTROL_MPCC_BOT_GAIN_MODE__enumvalues = {
0: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0',
1: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1',
}
MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0
MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 1
MPCC_CONTROL_MPCC_BOT_GAIN_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_MODE'
MPCC_CONTROL_MPCC_MODE__enumvalues = {
0: 'MPCC_CONTROL_MPCC_MODE_BYPASS',
1: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH',
2: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY',
3: 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING',
}
MPCC_CONTROL_MPCC_MODE_BYPASS = 0
MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 1
MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 2
MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 3
MPCC_CONTROL_MPCC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_EN'
MPCC_SM_CONTROL_MPCC_SM_EN__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE',
1: 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE',
}
MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0
MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 1
MPCC_SM_CONTROL_MPCC_SM_EN = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT'
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE',
1: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE',
}
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 1
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL'
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE',
1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED',
2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW',
3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH',
}
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL'
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE',
1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED',
2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW',
3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH',
}
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 1
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT'
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE',
1: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE',
}
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 1
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_MODE'
MPCC_SM_CONTROL_MPCC_SM_MODE__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE',
2: 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING',
4: 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING',
6: 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING',
}
MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0
MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 2
MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 4
MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6
MPCC_SM_CONTROL_MPCC_SM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM'
MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = {
0: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13',
1: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12',
}
MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0
MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1
MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_GAMUT_REMAP_MODE_ENUM'
MPCC_GAMUT_REMAP_MODE_ENUM__enumvalues = {
0: 'MPCC_GAMUT_REMAP_MODE_0',
1: 'MPCC_GAMUT_REMAP_MODE_1',
2: 'MPCC_GAMUT_REMAP_MODE_2',
3: 'MPCC_GAMUT_REMAP_MODE_RSV',
}
MPCC_GAMUT_REMAP_MODE_0 = 0
MPCC_GAMUT_REMAP_MODE_1 = 1
MPCC_GAMUT_REMAP_MODE_2 = 2
MPCC_GAMUT_REMAP_MODE_RSV = 3
MPCC_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_2_CONFIG_ENUM'
MPCC_OGAM_LUT_2_CONFIG_ENUM__enumvalues = {
0: 'MPCC_OGAM_LUT_2CFG_NO_MEMORY',
1: 'MPCC_OGAM_LUT_2CFG_MEMORY_A',
2: 'MPCC_OGAM_LUT_2CFG_MEMORY_B',
}
MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0
MPCC_OGAM_LUT_2CFG_MEMORY_A = 1
MPCC_OGAM_LUT_2CFG_MEMORY_B = 2
MPCC_OGAM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_CONFIG_MODE'
MPCC_OGAM_LUT_CONFIG_MODE__enumvalues = {
0: 'MPCC_OGAM_DIFFERENT_RGB',
1: 'MPCC_OGAM_ALL_USE_R',
}
MPCC_OGAM_DIFFERENT_RGB = 0
MPCC_OGAM_ALL_USE_R = 1
MPCC_OGAM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM'
MPCC_OGAM_LUT_PWL_DISABLE_ENUM__enumvalues = {
0: 'MPCC_OGAM_ENABLE_PWL',
1: 'MPCC_OGAM_DISABLE_PWL',
}
MPCC_OGAM_ENABLE_PWL = 0
MPCC_OGAM_DISABLE_PWL = 1
MPCC_OGAM_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL'
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL__enumvalues = {
0: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA',
1: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB',
}
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 1
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_RAM_SEL'
MPCC_OGAM_LUT_RAM_SEL__enumvalues = {
0: 'MPCC_OGAM_RAMA_ACCESS',
1: 'MPCC_OGAM_RAMB_ACCESS',
}
MPCC_OGAM_RAMA_ACCESS = 0
MPCC_OGAM_RAMB_ACCESS = 1
MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_READ_COLOR_SEL'
MPCC_OGAM_LUT_READ_COLOR_SEL__enumvalues = {
0: 'MPCC_OGAM_BLUE_LUT',
1: 'MPCC_OGAM_GREEN_LUT',
2: 'MPCC_OGAM_RED_LUT',
}
MPCC_OGAM_BLUE_LUT = 0
MPCC_OGAM_GREEN_LUT = 1
MPCC_OGAM_RED_LUT = 2
MPCC_OGAM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_READ_DBG'
MPCC_OGAM_LUT_READ_DBG__enumvalues = {
0: 'MPCC_OGAM_DISABLE_DEBUG',
1: 'MPCC_OGAM_ENABLE_DEBUG',
}
MPCC_OGAM_DISABLE_DEBUG = 0
MPCC_OGAM_ENABLE_DEBUG = 1
MPCC_OGAM_LUT_READ_DBG = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_SEL_ENUM'
MPCC_OGAM_LUT_SEL_ENUM__enumvalues = {
0: 'MPCC_OGAM_RAMA',
1: 'MPCC_OGAM_RAMB',
}
MPCC_OGAM_RAMA = 0
MPCC_OGAM_RAMB = 1
MPCC_OGAM_LUT_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM'
MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM__enumvalues = {
0: 'MPCC_OGAM_MODE_0',
1: 'MPCC_OGAM_MODE_RSV1',
2: 'MPCC_OGAM_MODE_2',
3: 'MPCC_OGAM_MODE_RSV',
}
MPCC_OGAM_MODE_0 = 0
MPCC_OGAM_MODE_RSV1 = 1
MPCC_OGAM_MODE_2 = 2
MPCC_OGAM_MODE_RSV = 3
MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_NUM_SEG'
MPCC_OGAM_NUM_SEG__enumvalues = {
0: 'MPCC_OGAM_SEGMENTS_1',
1: 'MPCC_OGAM_SEGMENTS_2',
2: 'MPCC_OGAM_SEGMENTS_4',
3: 'MPCC_OGAM_SEGMENTS_8',
4: 'MPCC_OGAM_SEGMENTS_16',
5: 'MPCC_OGAM_SEGMENTS_32',
6: 'MPCC_OGAM_SEGMENTS_64',
7: 'MPCC_OGAM_SEGMENTS_128',
}
MPCC_OGAM_SEGMENTS_1 = 0
MPCC_OGAM_SEGMENTS_2 = 1
MPCC_OGAM_SEGMENTS_4 = 2
MPCC_OGAM_SEGMENTS_8 = 3
MPCC_OGAM_SEGMENTS_16 = 4
MPCC_OGAM_SEGMENTS_32 = 5
MPCC_OGAM_SEGMENTS_64 = 6
MPCC_OGAM_SEGMENTS_128 = 7
MPCC_OGAM_NUM_SEG = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN'
MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN__enumvalues = {
0: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE',
1: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE',
}
MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0
MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 1
MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_3DLUT_30BIT_ENUM'
MPCC_MCM_3DLUT_30BIT_ENUM__enumvalues = {
0: 'MPCC_MCM_3DLUT_36BIT',
1: 'MPCC_MCM_3DLUT_30BIT',
}
MPCC_MCM_3DLUT_36BIT = 0
MPCC_MCM_3DLUT_30BIT = 1
MPCC_MCM_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_3DLUT_RAM_SEL'
MPCC_MCM_3DLUT_RAM_SEL__enumvalues = {
0: 'MPCC_MCM_RAM0_ACCESS',
1: 'MPCC_MCM_RAM1_ACCESS',
2: 'MPCC_MCM_RAM2_ACCESS',
3: 'MPCC_MCM_RAM3_ACCESS',
}
MPCC_MCM_RAM0_ACCESS = 0
MPCC_MCM_RAM1_ACCESS = 1
MPCC_MCM_RAM2_ACCESS = 2
MPCC_MCM_RAM3_ACCESS = 3
MPCC_MCM_3DLUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_3DLUT_SIZE_ENUM'
MPCC_MCM_3DLUT_SIZE_ENUM__enumvalues = {
0: 'MPCC_MCM_3DLUT_17CUBE',
1: 'MPCC_MCM_3DLUT_9CUBE',
}
MPCC_MCM_3DLUT_17CUBE = 0
MPCC_MCM_3DLUT_9CUBE = 1
MPCC_MCM_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_GAMMA_LUT_MODE_ENUM'
MPCC_MCM_GAMMA_LUT_MODE_ENUM__enumvalues = {
0: 'MPCC_MCM_GAMMA_LUT_BYPASS',
1: 'MPCC_MCM_GAMMA_LUT_RESERVED_1',
2: 'MPCC_MCM_GAMMA_LUT_RAM_LUT',
3: 'MPCC_MCM_GAMMA_LUT_RESERVED_3',
}
MPCC_MCM_GAMMA_LUT_BYPASS = 0
MPCC_MCM_GAMMA_LUT_RESERVED_1 = 1
MPCC_MCM_GAMMA_LUT_RAM_LUT = 2
MPCC_MCM_GAMMA_LUT_RESERVED_3 = 3
MPCC_MCM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM'
MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = {
0: 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL',
1: 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL',
}
MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0
MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 1
MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_GAMMA_LUT_SEL_ENUM'
MPCC_MCM_GAMMA_LUT_SEL_ENUM__enumvalues = {
0: 'MPCC_MCM_GAMMA_LUT_RAMA',
1: 'MPCC_MCM_GAMMA_LUT_RAMB',
}
MPCC_MCM_GAMMA_LUT_RAMA = 0
MPCC_MCM_GAMMA_LUT_RAMB = 1
MPCC_MCM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM'
MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = {
0: 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S2_13',
1: 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S3_12',
}
MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0
MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1
MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_GAMUT_REMAP_MODE_ENUM'
MPCC_MCM_GAMUT_REMAP_MODE_ENUM__enumvalues = {
0: 'MPCC_MCM_GAMUT_REMAP_MODE_0',
1: 'MPCC_MCM_GAMUT_REMAP_MODE_1',
2: 'MPCC_MCM_GAMUT_REMAP_MODE_2',
3: 'MPCC_MCM_GAMUT_REMAP_MODE_RSV',
}
MPCC_MCM_GAMUT_REMAP_MODE_0 = 0
MPCC_MCM_GAMUT_REMAP_MODE_1 = 1
MPCC_MCM_GAMUT_REMAP_MODE_2 = 2
MPCC_MCM_GAMUT_REMAP_MODE_RSV = 3
MPCC_MCM_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_LUT_2_MODE_ENUM'
MPCC_MCM_LUT_2_MODE_ENUM__enumvalues = {
0: 'MPCC_MCM_LUT_2_MODE_BYPASS',
1: 'MPCC_MCM_LUT_2_MODE_RAMA_LUT',
2: 'MPCC_MCM_LUT_2_MODE_RAMB_LUT',
}
MPCC_MCM_LUT_2_MODE_BYPASS = 0
MPCC_MCM_LUT_2_MODE_RAMA_LUT = 1
MPCC_MCM_LUT_2_MODE_RAMB_LUT = 2
MPCC_MCM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_LUT_CONFIG_MODE'
MPCC_MCM_LUT_CONFIG_MODE__enumvalues = {
0: 'MPCC_MCM_LUT_DIFFERENT_RGB',
1: 'MPCC_MCM_LUT_ALL_USE_R',
}
MPCC_MCM_LUT_DIFFERENT_RGB = 0
MPCC_MCM_LUT_ALL_USE_R = 1
MPCC_MCM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_LUT_NUM_SEG'
MPCC_MCM_LUT_NUM_SEG__enumvalues = {
0: 'MPCC_MCM_LUT_SEGMENTS_1',
1: 'MPCC_MCM_LUT_SEGMENTS_2',
2: 'MPCC_MCM_LUT_SEGMENTS_4',
3: 'MPCC_MCM_LUT_SEGMENTS_8',
4: 'MPCC_MCM_LUT_SEGMENTS_16',
5: 'MPCC_MCM_LUT_SEGMENTS_32',
6: 'MPCC_MCM_LUT_SEGMENTS_64',
7: 'MPCC_MCM_LUT_SEGMENTS_128',
}
MPCC_MCM_LUT_SEGMENTS_1 = 0
MPCC_MCM_LUT_SEGMENTS_2 = 1
MPCC_MCM_LUT_SEGMENTS_4 = 2
MPCC_MCM_LUT_SEGMENTS_8 = 3
MPCC_MCM_LUT_SEGMENTS_16 = 4
MPCC_MCM_LUT_SEGMENTS_32 = 5
MPCC_MCM_LUT_SEGMENTS_64 = 6
MPCC_MCM_LUT_SEGMENTS_128 = 7
MPCC_MCM_LUT_NUM_SEG = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_LUT_RAM_SEL'
MPCC_MCM_LUT_RAM_SEL__enumvalues = {
0: 'MPCC_MCM_LUT_RAMA_ACCESS',
1: 'MPCC_MCM_LUT_RAMB_ACCESS',
}
MPCC_MCM_LUT_RAMA_ACCESS = 0
MPCC_MCM_LUT_RAMB_ACCESS = 1
MPCC_MCM_LUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_LUT_READ_COLOR_SEL'
MPCC_MCM_LUT_READ_COLOR_SEL__enumvalues = {
0: 'MPCC_MCM_LUT_BLUE_LUT',
1: 'MPCC_MCM_LUT_GREEN_LUT',
2: 'MPCC_MCM_LUT_RED_LUT',
}
MPCC_MCM_LUT_BLUE_LUT = 0
MPCC_MCM_LUT_GREEN_LUT = 1
MPCC_MCM_LUT_RED_LUT = 2
MPCC_MCM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_LUT_READ_DBG'
MPCC_MCM_LUT_READ_DBG__enumvalues = {
0: 'MPCC_MCM_LUT_DISABLE_DEBUG',
1: 'MPCC_MCM_LUT_ENABLE_DEBUG',
}
MPCC_MCM_LUT_DISABLE_DEBUG = 0
MPCC_MCM_LUT_ENABLE_DEBUG = 1
MPCC_MCM_LUT_READ_DBG = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_MEM_PWR_FORCE_ENUM'
MPCC_MCM_MEM_PWR_FORCE_ENUM__enumvalues = {
0: 'MPCC_MCM_MEM_PWR_FORCE_DIS',
1: 'MPCC_MCM_MEM_PWR_FORCE_LS',
2: 'MPCC_MCM_MEM_PWR_FORCE_DS',
3: 'MPCC_MCM_MEM_PWR_FORCE_SD',
}
MPCC_MCM_MEM_PWR_FORCE_DIS = 0
MPCC_MCM_MEM_PWR_FORCE_LS = 1
MPCC_MCM_MEM_PWR_FORCE_DS = 2
MPCC_MCM_MEM_PWR_FORCE_SD = 3
MPCC_MCM_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_MEM_PWR_STATE_ENUM'
MPCC_MCM_MEM_PWR_STATE_ENUM__enumvalues = {
0: 'MPCC_MCM_MEM_PWR_STATE_ON',
1: 'MPCC_MCM_MEM_PWR_STATE_LS',
2: 'MPCC_MCM_MEM_PWR_STATE_DS',
3: 'MPCC_MCM_MEM_PWR_STATE_SD',
}
MPCC_MCM_MEM_PWR_STATE_ON = 0
MPCC_MCM_MEM_PWR_STATE_LS = 1
MPCC_MCM_MEM_PWR_STATE_DS = 2
MPCC_MCM_MEM_PWR_STATE_SD = 3
MPCC_MCM_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_BIT_DEPTH'
ENUM_DPG_BIT_DEPTH__enumvalues = {
0: 'ENUM_DPG_BIT_DEPTH_6BPC',
1: 'ENUM_DPG_BIT_DEPTH_8BPC',
2: 'ENUM_DPG_BIT_DEPTH_10BPC',
3: 'ENUM_DPG_BIT_DEPTH_12BPC',
}
ENUM_DPG_BIT_DEPTH_6BPC = 0
ENUM_DPG_BIT_DEPTH_8BPC = 1
ENUM_DPG_BIT_DEPTH_10BPC = 2
ENUM_DPG_BIT_DEPTH_12BPC = 3
ENUM_DPG_BIT_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_DYNAMIC_RANGE'
ENUM_DPG_DYNAMIC_RANGE__enumvalues = {
0: 'ENUM_DPG_DYNAMIC_RANGE_VESA',
1: 'ENUM_DPG_DYNAMIC_RANGE_CEA',
}
ENUM_DPG_DYNAMIC_RANGE_VESA = 0
ENUM_DPG_DYNAMIC_RANGE_CEA = 1
ENUM_DPG_DYNAMIC_RANGE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_EN'
ENUM_DPG_EN__enumvalues = {
0: 'ENUM_DPG_DISABLE',
1: 'ENUM_DPG_ENABLE',
}
ENUM_DPG_DISABLE = 0
ENUM_DPG_ENABLE = 1
ENUM_DPG_EN = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_FIELD_POLARITY'
ENUM_DPG_FIELD_POLARITY__enumvalues = {
0: 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD',
1: 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN',
}
ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0
ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1
ENUM_DPG_FIELD_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_MODE'
ENUM_DPG_MODE__enumvalues = {
0: 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK',
1: 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK',
2: 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK',
3: 'ENUM_DPG_MODE_VERTICAL_BAR',
4: 'ENUM_DPG_MODE_HORIZONTAL_BAR',
5: 'ENUM_DPG_MODE_RGB_SINGLE_RAMP',
6: 'ENUM_DPG_MODE_RGB_DUAL_RAMP',
7: 'ENUM_DPG_MODE_RGB_XR_BIAS',
}
ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0
ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 1
ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 2
ENUM_DPG_MODE_VERTICAL_BAR = 3
ENUM_DPG_MODE_HORIZONTAL_BAR = 4
ENUM_DPG_MODE_RGB_SINGLE_RAMP = 5
ENUM_DPG_MODE_RGB_DUAL_RAMP = 6
ENUM_DPG_MODE_RGB_XR_BIAS = 7
ENUM_DPG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMTMEM_PWR_DIS_CTRL'
FMTMEM_PWR_DIS_CTRL__enumvalues = {
0: 'FMTMEM_ENABLE_MEM_PWR_CTRL',
1: 'FMTMEM_DISABLE_MEM_PWR_CTRL',
}
FMTMEM_ENABLE_MEM_PWR_CTRL = 0
FMTMEM_DISABLE_MEM_PWR_CTRL = 1
FMTMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'FMTMEM_PWR_FORCE_CTRL'
FMTMEM_PWR_FORCE_CTRL__enumvalues = {
0: 'FMTMEM_NO_FORCE_REQUEST',
1: 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST',
3: 'FMTMEM_FORCE_SHUT_DOWN_REQUEST',
}
FMTMEM_NO_FORCE_REQUEST = 0
FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 1
FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 2
FMTMEM_FORCE_SHUT_DOWN_REQUEST = 3
FMTMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL'
FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei',
1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi',
2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi',
3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED',
}
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3
FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL'
FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A',
1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B',
2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C',
3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D',
}
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3
FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL'
FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E',
1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F',
2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G',
3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED',
}
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3
FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH'
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP',
1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP',
2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP',
}
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH'
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP',
1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP',
2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP',
}
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL'
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2',
1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4',
}
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH'
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP',
1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP',
2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP',
}
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE'
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION',
1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING',
}
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT'
FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = {
0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC',
1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC',
2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC',
3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC',
4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1',
5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2',
6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3',
7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE',
}
FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0
FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1
FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2
FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6
FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7
FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS'
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = {
0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE',
1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE',
}
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING'
FMT_CONTROL_PIXEL_ENCODING__enumvalues = {
0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444',
1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422',
2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420',
3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED',
}
FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0
FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1
FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2
FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3
FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE'
FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = {
0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP',
1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE',
2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP',
3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED',
}
FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0
FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1
FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2
FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3
FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER'
FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = {
0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR',
1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB',
}
FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0
FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1
FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum
# values for enumeration 'FMT_DEBUG_CNTL_COLOR_SELECT'
FMT_DEBUG_CNTL_COLOR_SELECT__enumvalues = {
0: 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE',
1: 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN',
2: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1',
3: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2',
}
FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0
FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 1
FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 2
FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 3
FMT_DEBUG_CNTL_COLOR_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'FMT_DYNAMIC_EXP_MODE'
FMT_DYNAMIC_EXP_MODE__enumvalues = {
0: 'FMT_DYNAMIC_EXP_MODE_10to12',
1: 'FMT_DYNAMIC_EXP_MODE_8to12',
}
FMT_DYNAMIC_EXP_MODE_10to12 = 0
FMT_DYNAMIC_EXP_MODE_8to12 = 1
FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMT_FRAME_RANDOM_ENABLE_CONTROL'
FMT_FRAME_RANDOM_ENABLE_CONTROL__enumvalues = {
0: 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME',
1: 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE',
}
FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0
FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 1
FMT_FRAME_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_POWER_STATE_ENUM'
FMT_POWER_STATE_ENUM__enumvalues = {
0: 'FMT_POWER_STATE_ENUM_ON',
1: 'FMT_POWER_STATE_ENUM_LS',
2: 'FMT_POWER_STATE_ENUM_DS',
3: 'FMT_POWER_STATE_ENUM_SD',
}
FMT_POWER_STATE_ENUM_ON = 0
FMT_POWER_STATE_ENUM_LS = 1
FMT_POWER_STATE_ENUM_DS = 2
FMT_POWER_STATE_ENUM_SD = 3
FMT_POWER_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'FMT_RGB_RANDOM_ENABLE_CONTROL'
FMT_RGB_RANDOM_ENABLE_CONTROL__enumvalues = {
0: 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE',
1: 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE',
}
FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0
FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 1
FMT_RGB_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL'
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL__enumvalues = {
0: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP',
1: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1',
2: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2',
3: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED',
}
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 1
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 2
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 3
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_SPATIAL_DITHER_MODE'
FMT_SPATIAL_DITHER_MODE__enumvalues = {
0: 'FMT_SPATIAL_DITHER_MODE_0',
1: 'FMT_SPATIAL_DITHER_MODE_1',
2: 'FMT_SPATIAL_DITHER_MODE_2',
3: 'FMT_SPATIAL_DITHER_MODE_3',
}
FMT_SPATIAL_DITHER_MODE_0 = 0
FMT_SPATIAL_DITHER_MODE_1 = 1
FMT_SPATIAL_DITHER_MODE_2 = 2
FMT_SPATIAL_DITHER_MODE_3 = 3
FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMT_STEREOSYNC_OVERRIDE_CONTROL'
FMT_STEREOSYNC_OVERRIDE_CONTROL__enumvalues = {
0: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0',
1: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1',
}
FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0
FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 1
FMT_STEREOSYNC_OVERRIDE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0'
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = {
0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR',
1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB',
}
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum
# values for enumeration 'OPPBUF_DISPLAY_SEGMENTATION'
OPPBUF_DISPLAY_SEGMENTATION__enumvalues = {
0: 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT',
1: 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT',
2: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT',
3: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT',
4: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT',
}
OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0
OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1
OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2
OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3
OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4
OPPBUF_DISPLAY_SEGMENTATION = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CLOCK_ENABLE_CONTROL'
OPP_PIPE_CLOCK_ENABLE_CONTROL__enumvalues = {
0: 'OPP_PIPE_CLOCK_DISABLE',
1: 'OPP_PIPE_CLOCK_ENABLE',
}
OPP_PIPE_CLOCK_DISABLE = 0
OPP_PIPE_CLOCK_ENABLE = 1
OPP_PIPE_CLOCK_ENABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL'
OPP_PIPE_DIGTIAL_BYPASS_CONTROL__enumvalues = {
0: 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE',
1: 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE',
}
OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0
OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 1
OPP_PIPE_DIGTIAL_BYPASS_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_CONT_EN'
OPP_PIPE_CRC_CONT_EN__enumvalues = {
0: 'OPP_PIPE_CRC_MODE_ONE_SHOT',
1: 'OPP_PIPE_CRC_MODE_CONTINUOUS',
}
OPP_PIPE_CRC_MODE_ONE_SHOT = 0
OPP_PIPE_CRC_MODE_CONTINUOUS = 1
OPP_PIPE_CRC_CONT_EN = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_EN'
OPP_PIPE_CRC_EN__enumvalues = {
0: 'OPP_PIPE_CRC_DISABLE',
1: 'OPP_PIPE_CRC_ENABLE',
}
OPP_PIPE_CRC_DISABLE = 0
OPP_PIPE_CRC_ENABLE = 1
OPP_PIPE_CRC_EN = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_INTERLACE_EN'
OPP_PIPE_CRC_INTERLACE_EN__enumvalues = {
0: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE',
1: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED',
}
OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0
OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 1
OPP_PIPE_CRC_INTERLACE_EN = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_INTERLACE_MODE'
OPP_PIPE_CRC_INTERLACE_MODE__enumvalues = {
0: 'OPP_PIPE_CRC_INTERLACE_MODE_TOP',
1: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM',
2: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD',
3: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD',
}
OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0
OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 1
OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 2
OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 3
OPP_PIPE_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_ONE_SHOT_PENDING'
OPP_PIPE_CRC_ONE_SHOT_PENDING__enumvalues = {
0: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING',
1: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING',
}
OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0
OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 1
OPP_PIPE_CRC_ONE_SHOT_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_PIXEL_SELECT'
OPP_PIPE_CRC_PIXEL_SELECT__enumvalues = {
0: 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS',
1: 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED',
2: 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS',
3: 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS',
}
OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0
OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 1
OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 2
OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 3
OPP_PIPE_CRC_PIXEL_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_SOURCE_SELECT'
OPP_PIPE_CRC_SOURCE_SELECT__enumvalues = {
0: 'OPP_PIPE_CRC_SOURCE_SELECT_FMT',
1: 'OPP_PIPE_CRC_SOURCE_SELECT_SFT',
}
OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0
OPP_PIPE_CRC_SOURCE_SELECT_SFT = 1
OPP_PIPE_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_STEREO_EN'
OPP_PIPE_CRC_STEREO_EN__enumvalues = {
0: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO',
1: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO',
}
OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0
OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 1
OPP_PIPE_CRC_STEREO_EN = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_STEREO_MODE'
OPP_PIPE_CRC_STEREO_MODE__enumvalues = {
0: 'OPP_PIPE_CRC_STEREO_MODE_LEFT',
1: 'OPP_PIPE_CRC_STEREO_MODE_RIGHT',
2: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE',
3: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE',
}
OPP_PIPE_CRC_STEREO_MODE_LEFT = 0
OPP_PIPE_CRC_STEREO_MODE_RIGHT = 1
OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 2
OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 3
OPP_PIPE_CRC_STEREO_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OPP_TEST_CLK_SEL_CONTROL'
OPP_TEST_CLK_SEL_CONTROL__enumvalues = {
0: 'OPP_TEST_CLK_SEL_DISPCLK_P',
1: 'OPP_TEST_CLK_SEL_DISPCLK_R',
2: 'OPP_TEST_CLK_SEL_DISPCLK_ABM0',
3: 'OPP_TEST_CLK_SEL_DISPCLK_ABM1',
4: 'OPP_TEST_CLK_SEL_DISPCLK_ABM2',
5: 'OPP_TEST_CLK_SEL_DISPCLK_ABM3',
6: 'OPP_TEST_CLK_SEL_RESERVED0',
7: 'OPP_TEST_CLK_SEL_RESERVED1',
8: 'OPP_TEST_CLK_SEL_DISPCLK_OPP0',
9: 'OPP_TEST_CLK_SEL_DISPCLK_OPP1',
10: 'OPP_TEST_CLK_SEL_DISPCLK_OPP2',
11: 'OPP_TEST_CLK_SEL_DISPCLK_OPP3',
12: 'OPP_TEST_CLK_SEL_RESERVED2',
13: 'OPP_TEST_CLK_SEL_RESERVED3',
}
OPP_TEST_CLK_SEL_DISPCLK_P = 0
OPP_TEST_CLK_SEL_DISPCLK_R = 1
OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 2
OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 3
OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 4
OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 5
OPP_TEST_CLK_SEL_RESERVED0 = 6
OPP_TEST_CLK_SEL_RESERVED1 = 7
OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 8
OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 9
OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 10
OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 11
OPP_TEST_CLK_SEL_RESERVED2 = 12
OPP_TEST_CLK_SEL_RESERVED3 = 13
OPP_TEST_CLK_SEL_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_TOP_CLOCK_ENABLE_STATUS'
OPP_TOP_CLOCK_ENABLE_STATUS__enumvalues = {
0: 'OPP_TOP_CLOCK_DISABLED_STATUS',
1: 'OPP_TOP_CLOCK_ENABLED_STATUS',
}
OPP_TOP_CLOCK_DISABLED_STATUS = 0
OPP_TOP_CLOCK_ENABLED_STATUS = 1
OPP_TOP_CLOCK_ENABLE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'OPP_TOP_CLOCK_GATING_CONTROL'
OPP_TOP_CLOCK_GATING_CONTROL__enumvalues = {
0: 'OPP_TOP_CLOCK_GATING_ENABLED',
1: 'OPP_TOP_CLOCK_GATING_DISABLED',
}
OPP_TOP_CLOCK_GATING_ENABLED = 0
OPP_TOP_CLOCK_GATING_DISABLED = 1
OPP_TOP_CLOCK_GATING_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK'
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = {
0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE',
1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE',
}
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum
# values for enumeration 'MASTER_UPDATE_LOCK_SEL'
MASTER_UPDATE_LOCK_SEL__enumvalues = {
0: 'MASTER_UPDATE_LOCK_SEL_0',
1: 'MASTER_UPDATE_LOCK_SEL_1',
2: 'MASTER_UPDATE_LOCK_SEL_2',
3: 'MASTER_UPDATE_LOCK_SEL_3',
4: 'MASTER_UPDATE_LOCK_SEL_RESERVED4',
5: 'MASTER_UPDATE_LOCK_SEL_RESERVED5',
}
MASTER_UPDATE_LOCK_SEL_0 = 0
MASTER_UPDATE_LOCK_SEL_1 = 1
MASTER_UPDATE_LOCK_SEL_2 = 2
MASTER_UPDATE_LOCK_SEL_3 = 3
MASTER_UPDATE_LOCK_SEL_RESERVED4 = 4
MASTER_UPDATE_LOCK_SEL_RESERVED5 = 5
MASTER_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE'
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = {
0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH',
1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP',
2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM',
3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED',
}
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 1
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 2
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN'
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN__enumvalues = {
0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE',
1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE',
}
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 1
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB'
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB__enumvalues = {
0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE',
1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE',
}
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 1
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum
# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR'
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = {
0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE',
1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE',
}
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE'
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = {
0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH',
1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE',
2: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE',
3: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED',
}
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL'
OTG_CONTROL_OTG_DISABLE_POINT_CNTL__enumvalues = {
0: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE',
1: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT',
2: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE',
3: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST',
}
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 2
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 3
OTG_CONTROL_OTG_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL'
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL__enumvalues = {
0: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL',
1: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP',
}
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 1
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY'
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY__enumvalues = {
0: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE',
1: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE',
}
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 1
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_MASTER_EN'
OTG_CONTROL_OTG_MASTER_EN__enumvalues = {
0: 'OTG_CONTROL_OTG_MASTER_EN_FALSE',
1: 'OTG_CONTROL_OTG_MASTER_EN_TRUE',
}
OTG_CONTROL_OTG_MASTER_EN_FALSE = 0
OTG_CONTROL_OTG_MASTER_EN_TRUE = 1
OTG_CONTROL_OTG_MASTER_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_OUT_MUX'
OTG_CONTROL_OTG_OUT_MUX__enumvalues = {
0: 'OTG_CONTROL_OTG_OUT_MUX_0',
1: 'OTG_CONTROL_OTG_OUT_MUX_1',
2: 'OTG_CONTROL_OTG_OUT_MUX_2',
}
OTG_CONTROL_OTG_OUT_MUX_0 = 0
OTG_CONTROL_OTG_OUT_MUX_1 = 1
OTG_CONTROL_OTG_OUT_MUX_2 = 2
OTG_CONTROL_OTG_OUT_MUX = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_START_POINT_CNTL'
OTG_CONTROL_OTG_START_POINT_CNTL__enumvalues = {
0: 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL',
1: 'OTG_CONTROL_OTG_START_POINT_CNTL_DP',
}
OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0
OTG_CONTROL_OTG_START_POINT_CNTL_DP = 1
OTG_CONTROL_OTG_START_POINT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN'
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN__enumvalues = {
0: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE',
1: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE',
}
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 1
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC1_EN'
OTG_CRC_CNTL_OTG_CRC1_EN__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE',
1: 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE',
}
OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0
OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 1
OTG_CRC_CNTL_OTG_CRC1_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_EN'
OTG_CRC_CNTL_OTG_CRC_CONT_EN__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE',
1: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE',
}
OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0
OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 1
OTG_CRC_CNTL_OTG_CRC_CONT_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE'
OTG_CRC_CNTL_OTG_CRC_CONT_MODE__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET',
1: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET',
}
OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0
OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 1
OTG_CRC_CNTL_OTG_CRC_CONT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_EN'
OTG_CRC_CNTL_OTG_CRC_EN__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE',
1: 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE',
}
OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0
OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 1
OTG_CRC_CNTL_OTG_CRC_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE'
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP',
1: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM',
2: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM',
3: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD',
}
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 1
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 3
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE'
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT',
1: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT',
2: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES',
3: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS',
}
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 1
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 2
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 3
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS'
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE',
1: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE',
}
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT'
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB',
1: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B',
2: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB',
3: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B',
4: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB',
5: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B',
6: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB',
7: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B',
}
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 1
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 2
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 3
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 4
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 5
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 6
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 7
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT'
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB',
1: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B',
2: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB',
3: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B',
4: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB',
5: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B',
6: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB',
7: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B',
}
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 1
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 2
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 3
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 4
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 5
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 6
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 7
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DIG_UPDATE_VCOUNT_MODE'
OTG_DIG_UPDATE_VCOUNT_MODE__enumvalues = {
0: 'OTG_DIG_UPDATE_VCOUNT_0',
1: 'OTG_DIG_UPDATE_VCOUNT_1',
}
OTG_DIG_UPDATE_VCOUNT_0 = 0
OTG_DIG_UPDATE_VCOUNT_1 = 1
OTG_DIG_UPDATE_VCOUNT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE'
OTG_DLPC_CONTROL_OTG_RESYNC_MODE__enumvalues = {
0: 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE_0',
1: 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE_1',
}
OTG_DLPC_CONTROL_OTG_RESYNC_MODE_0 = 0
OTG_DLPC_CONTROL_OTG_RESYNC_MODE_1 = 1
OTG_DLPC_CONTROL_OTG_RESYNC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE'
OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE__enumvalues = {
0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0',
1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1',
2: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2',
3: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3',
}
OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0
OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 1
OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 2
OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 3
OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY'
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY__enumvalues = {
0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE',
1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE',
}
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 1
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME'
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME__enumvalues = {
0: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME',
1: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME',
2: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME',
3: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME',
}
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 1
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 2
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 3
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN'
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN__enumvalues = {
0: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE',
1: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE',
}
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 1
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY'
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY__enumvalues = {
0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE',
1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE',
}
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 1
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY'
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY__enumvalues = {
0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE',
1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE',
}
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 1
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT'
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT__enumvalues = {
0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0',
1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1',
2: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA',
3: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB',
4: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC',
5: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD',
6: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE',
7: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF',
8: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1',
9: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2',
10: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA',
11: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK',
12: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA',
13: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK',
14: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
15: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED',
16: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK',
17: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC',
18: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA',
19: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB',
}
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 1
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 2
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 3
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 4
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 5
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 6
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 7
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 8
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 9
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 10
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 11
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 12
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 13
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 14
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 15
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 16
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 17
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 18
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 19
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK'
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK__enumvalues = {
0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE',
1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE',
}
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 1
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR'
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR__enumvalues = {
0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE',
1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE',
}
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 1
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE'
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE__enumvalues = {
0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE',
1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT',
2: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT',
3: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED',
}
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 1
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 3
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL'
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = {
0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE',
1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE',
}
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL'
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL__enumvalues = {
0: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0',
1: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1',
2: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2',
3: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3',
4: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4',
5: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5',
}
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 1
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 2
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 3
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 4
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 5
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL'
OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL__enumvalues = {
0: 'DIG_UPDATE_EYE_SEL_BOTH',
1: 'DIG_UPDATE_EYE_SEL_LEFT',
2: 'DIG_UPDATE_EYE_SEL_RIGHT',
}
DIG_UPDATE_EYE_SEL_BOTH = 0
DIG_UPDATE_EYE_SEL_LEFT = 1
DIG_UPDATE_EYE_SEL_RIGHT = 2
OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL'
OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL__enumvalues = {
0: 'DIG_UPDATE_FIELD_SEL_BOTH',
1: 'DIG_UPDATE_FIELD_SEL_TOP',
2: 'DIG_UPDATE_FIELD_SEL_BOTTOM',
3: 'DIG_UPDATE_FIELD_SEL_RESERVED',
}
DIG_UPDATE_FIELD_SEL_BOTH = 0
DIG_UPDATE_FIELD_SEL_TOP = 1
DIG_UPDATE_FIELD_SEL_BOTTOM = 2
DIG_UPDATE_FIELD_SEL_RESERVED = 3
OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD'
OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD__enumvalues = {
0: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH',
1: 'MASTER_UPDATE_LOCK_DB_FIELD_TOP',
2: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM',
3: 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED',
}
MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0
MASTER_UPDATE_LOCK_DB_FIELD_TOP = 1
MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 2
MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 3
OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL'
OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL__enumvalues = {
0: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH',
1: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT',
2: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT',
3: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED',
}
MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0
MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 1
MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 2
MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 3
OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_UPDATE_LOCK_EN'
OTG_GLOBAL_UPDATE_LOCK_EN__enumvalues = {
0: 'OTG_GLOBAL_UPDATE_LOCK_DISABLE',
1: 'OTG_GLOBAL_UPDATE_LOCK_ENABLE',
}
OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0
OTG_GLOBAL_UPDATE_LOCK_ENABLE = 1
OTG_GLOBAL_UPDATE_LOCK_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GSL_MASTER_MODE'
OTG_GSL_MASTER_MODE__enumvalues = {
0: 'OTG_GSL_MASTER_MODE_0',
1: 'OTG_GSL_MASTER_MODE_1',
2: 'OTG_GSL_MASTER_MODE_2',
3: 'OTG_GSL_MASTER_MODE_3',
}
OTG_GSL_MASTER_MODE_0 = 0
OTG_GSL_MASTER_MODE_1 = 1
OTG_GSL_MASTER_MODE_2 = 2
OTG_GSL_MASTER_MODE_3 = 3
OTG_GSL_MASTER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_HORZ_REPETITION_COUNT'
OTG_HORZ_REPETITION_COUNT__enumvalues = {
0: 'OTG_HORZ_REPETITION_COUNT_0',
1: 'OTG_HORZ_REPETITION_COUNT_1',
2: 'OTG_HORZ_REPETITION_COUNT_2',
3: 'OTG_HORZ_REPETITION_COUNT_3',
4: 'OTG_HORZ_REPETITION_COUNT_4',
5: 'OTG_HORZ_REPETITION_COUNT_5',
6: 'OTG_HORZ_REPETITION_COUNT_6',
7: 'OTG_HORZ_REPETITION_COUNT_7',
8: 'OTG_HORZ_REPETITION_COUNT_8',
9: 'OTG_HORZ_REPETITION_COUNT_9',
10: 'OTG_HORZ_REPETITION_COUNT_10',
11: 'OTG_HORZ_REPETITION_COUNT_11',
12: 'OTG_HORZ_REPETITION_COUNT_12',
13: 'OTG_HORZ_REPETITION_COUNT_13',
14: 'OTG_HORZ_REPETITION_COUNT_14',
15: 'OTG_HORZ_REPETITION_COUNT_15',
}
OTG_HORZ_REPETITION_COUNT_0 = 0
OTG_HORZ_REPETITION_COUNT_1 = 1
OTG_HORZ_REPETITION_COUNT_2 = 2
OTG_HORZ_REPETITION_COUNT_3 = 3
OTG_HORZ_REPETITION_COUNT_4 = 4
OTG_HORZ_REPETITION_COUNT_5 = 5
OTG_HORZ_REPETITION_COUNT_6 = 6
OTG_HORZ_REPETITION_COUNT_7 = 7
OTG_HORZ_REPETITION_COUNT_8 = 8
OTG_HORZ_REPETITION_COUNT_9 = 9
OTG_HORZ_REPETITION_COUNT_10 = 10
OTG_HORZ_REPETITION_COUNT_11 = 11
OTG_HORZ_REPETITION_COUNT_12 = 12
OTG_HORZ_REPETITION_COUNT_13 = 13
OTG_HORZ_REPETITION_COUNT_14 = 14
OTG_HORZ_REPETITION_COUNT_15 = 15
OTG_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_H_SYNC_A_POL'
OTG_H_SYNC_A_POL__enumvalues = {
0: 'OTG_H_SYNC_A_POL_HIGH',
1: 'OTG_H_SYNC_A_POL_LOW',
}
OTG_H_SYNC_A_POL_HIGH = 0
OTG_H_SYNC_A_POL_LOW = 1
OTG_H_SYNC_A_POL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_H_TIMING_DIV_MODE'
OTG_H_TIMING_DIV_MODE__enumvalues = {
0: 'OTG_H_TIMING_DIV_MODE_NO_DIV',
1: 'OTG_H_TIMING_DIV_MODE_DIV_BY2',
2: 'OTG_H_TIMING_DIV_MODE_RESERVED',
3: 'OTG_H_TIMING_DIV_MODE_DIV_BY4',
}
OTG_H_TIMING_DIV_MODE_NO_DIV = 0
OTG_H_TIMING_DIV_MODE_DIV_BY2 = 1
OTG_H_TIMING_DIV_MODE_RESERVED = 2
OTG_H_TIMING_DIV_MODE_DIV_BY4 = 3
OTG_H_TIMING_DIV_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_H_TIMING_DIV_MODE_MANUAL'
OTG_H_TIMING_DIV_MODE_MANUAL__enumvalues = {
0: 'OTG_H_TIMING_DIV_MODE_AUTO',
1: 'OTG_H_TIMING_DIV_MODE_NOAUTO',
}
OTG_H_TIMING_DIV_MODE_AUTO = 0
OTG_H_TIMING_DIV_MODE_NOAUTO = 1
OTG_H_TIMING_DIV_MODE_MANUAL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE'
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE__enumvalues = {
0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE',
1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE',
}
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 1
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD'
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD__enumvalues = {
0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT',
1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM',
2: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP',
3: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2',
}
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 1
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 2
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE'
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = {
0: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE',
1: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE',
}
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_MASTER_UPDATE_LOCK_DB_EN'
OTG_MASTER_UPDATE_LOCK_DB_EN__enumvalues = {
0: 'OTG_MASTER_UPDATE_LOCK_DISABLE',
1: 'OTG_MASTER_UPDATE_LOCK_ENABLE',
}
OTG_MASTER_UPDATE_LOCK_DISABLE = 0
OTG_MASTER_UPDATE_LOCK_ENABLE = 1
OTG_MASTER_UPDATE_LOCK_DB_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_MASTER_UPDATE_LOCK_GSL_EN'
OTG_MASTER_UPDATE_LOCK_GSL_EN__enumvalues = {
0: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE',
1: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE',
}
OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0
OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 1
OTG_MASTER_UPDATE_LOCK_GSL_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE'
OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE__enumvalues = {
0: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0',
1: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1',
}
OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0
OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 1
OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL'
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = {
0: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE',
1: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA',
2: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB',
3: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED',
}
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR'
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR__enumvalues = {
0: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE',
1: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE',
}
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 1
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR'
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE',
}
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 1
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE'
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE',
}
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 1
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE'
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE',
}
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 1
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE'
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE',
}
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 1
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE'
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON',
}
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL'
OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL__enumvalues = {
0: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE',
1: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE',
}
OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0
OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 1
OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EN'
OTG_STEREO_CONTROL_OTG_STEREO_EN__enumvalues = {
0: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE',
1: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE',
}
OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0
OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 1
OTG_STEREO_CONTROL_OTG_STEREO_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY'
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY__enumvalues = {
0: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE',
1: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE',
}
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 1
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY'
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = {
0: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE',
1: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE',
}
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE'
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE__enumvalues = {
0: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO',
1: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT',
2: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT',
3: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED',
}
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 1
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 2
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 3
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR'
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE',
}
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 1
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT'
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE',
2: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA',
3: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB',
4: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA',
5: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1',
6: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC',
7: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD',
}
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 1
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 2
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 3
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 4
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 5
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 6
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 7
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN'
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE',
}
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 1
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT'
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1',
2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2',
3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3',
4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4',
5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5',
}
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 1
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 2
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 3
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 4
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 5
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT'
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN',
2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN',
3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN',
4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN',
5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN',
6: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN',
7: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN',
8: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN',
9: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN',
10: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN',
11: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1',
12: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2',
13: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN',
14: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14',
15: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK',
16: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP',
17: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING',
18: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF',
19: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC',
20: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC',
21: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL',
22: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
23: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1',
24: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING',
}
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 1
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 2
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 3
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 4
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 5
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 6
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 7
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 8
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 9
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 10
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 11
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 12
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 13
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 14
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 15
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 16
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 17
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 18
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 19
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 20
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 23
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 24
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL'
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__enumvalues = {
0: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0',
1: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1',
2: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2',
3: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3',
}
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 1
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 2
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 3
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_FREQUENCY_SELECT'
OTG_TRIGA_FREQUENCY_SELECT__enumvalues = {
0: 'OTG_TRIGA_FREQUENCY_SELECT_0',
1: 'OTG_TRIGA_FREQUENCY_SELECT_1',
2: 'OTG_TRIGA_FREQUENCY_SELECT_2',
3: 'OTG_TRIGA_FREQUENCY_SELECT_3',
}
OTG_TRIGA_FREQUENCY_SELECT_0 = 0
OTG_TRIGA_FREQUENCY_SELECT_1 = 1
OTG_TRIGA_FREQUENCY_SELECT_2 = 2
OTG_TRIGA_FREQUENCY_SELECT_3 = 3
OTG_TRIGA_FREQUENCY_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL'
OTG_TRIGA_RISING_EDGE_DETECT_CNTL__enumvalues = {
0: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0',
1: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1',
2: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2',
3: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3',
}
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 1
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 2
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 3
OTG_TRIGA_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR'
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE',
}
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 1
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT'
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE',
2: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA',
3: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB',
4: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA',
5: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1',
6: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC',
7: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD',
}
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 1
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 2
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 3
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 4
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 5
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 6
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 7
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN'
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE',
}
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 1
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT'
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1',
2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2',
3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3',
4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4',
5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5',
}
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 1
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 2
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 3
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 4
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 5
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT'
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN',
2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN',
3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN',
4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN',
5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN',
6: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN',
7: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN',
8: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN',
9: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN',
10: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN',
11: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1',
12: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2',
13: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN',
14: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14',
15: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK',
16: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP',
17: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING',
18: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF',
19: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC',
20: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC',
21: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL',
22: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
23: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1',
24: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING',
}
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 1
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 2
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 3
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 4
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 5
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 6
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 7
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 8
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 9
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 10
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 11
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 12
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 13
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 14
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 15
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 16
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 17
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 18
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 19
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 20
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 23
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 24
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL'
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__enumvalues = {
0: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0',
1: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1',
2: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2',
3: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3',
}
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 1
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 2
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 3
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_FREQUENCY_SELECT'
OTG_TRIGB_FREQUENCY_SELECT__enumvalues = {
0: 'OTG_TRIGB_FREQUENCY_SELECT_0',
1: 'OTG_TRIGB_FREQUENCY_SELECT_1',
2: 'OTG_TRIGB_FREQUENCY_SELECT_2',
3: 'OTG_TRIGB_FREQUENCY_SELECT_3',
}
OTG_TRIGB_FREQUENCY_SELECT_0 = 0
OTG_TRIGB_FREQUENCY_SELECT_1 = 1
OTG_TRIGB_FREQUENCY_SELECT_2 = 2
OTG_TRIGB_FREQUENCY_SELECT_3 = 3
OTG_TRIGB_FREQUENCY_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL'
OTG_TRIGB_RISING_EDGE_DETECT_CNTL__enumvalues = {
0: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0',
1: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1',
2: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2',
3: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3',
}
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 1
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 2
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 3
OTG_TRIGB_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK'
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK__enumvalues = {
0: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE',
1: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE',
}
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 1
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR'
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE',
1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE',
}
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE'
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE',
}
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE'
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE',
}
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY'
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE',
1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE',
}
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR'
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE',
1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE',
}
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE'
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE',
}
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE'
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE',
}
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR'
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE',
1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE',
}
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE'
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE',
}
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE'
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE',
}
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE'
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE__enumvalues = {
0: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE',
1: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA',
2: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB',
3: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED',
}
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 3
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR'
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = {
0: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE',
1: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE',
}
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR'
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR__enumvalues = {
0: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE',
1: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE',
}
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 1
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VUPDATE_BLOCK_DISABLE'
OTG_VUPDATE_BLOCK_DISABLE__enumvalues = {
0: 'OTG_VUPDATE_BLOCK_DISABLE_OFF',
1: 'OTG_VUPDATE_BLOCK_DISABLE_ON',
}
OTG_VUPDATE_BLOCK_DISABLE_OFF = 0
OTG_VUPDATE_BLOCK_DISABLE_ON = 1
OTG_VUPDATE_BLOCK_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_SYNC_A_POL'
OTG_V_SYNC_A_POL__enumvalues = {
0: 'OTG_V_SYNC_A_POL_HIGH',
1: 'OTG_V_SYNC_A_POL_LOW',
}
OTG_V_SYNC_A_POL_HIGH = 0
OTG_V_SYNC_A_POL_LOW = 1
OTG_V_SYNC_A_POL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_SYNC_MODE'
OTG_V_SYNC_MODE__enumvalues = {
0: 'OTG_V_SYNC_MODE_HSYNC',
1: 'OTG_V_SYNC_MODE_HBLANK',
}
OTG_V_SYNC_MODE_HSYNC = 0
OTG_V_SYNC_MODE_HBLANK = 1
OTG_V_SYNC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD'
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0',
1: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1',
}
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 1
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT'
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE',
1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE',
}
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 1
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC'
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE',
1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE',
}
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL'
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE',
1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE',
}
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 1
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL'
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE',
1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE',
}
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 1
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK'
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__enumvalues = {
0: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE',
1: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE',
}
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 1
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK = ctypes.c_uint32 # enum
# values for enumeration 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL'
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL__enumvalues = {
0: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0',
1: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1',
2: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2',
3: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3',
4: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4',
5: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5',
}
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 1
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 2
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 3
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 4
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 5
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DC_DMCUB_INT_TYPE'
DC_DMCUB_INT_TYPE__enumvalues = {
0: 'INT_LEVEL',
1: 'INT_PULSE',
}
INT_LEVEL = 0
INT_PULSE = 1
DC_DMCUB_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DC_DMCUB_TIMER_WINDOW'
DC_DMCUB_TIMER_WINDOW__enumvalues = {
0: 'BITS_31_0',
1: 'BITS_32_1',
2: 'BITS_33_2',
3: 'BITS_34_3',
4: 'BITS_35_4',
5: 'BITS_36_5',
6: 'BITS_37_6',
7: 'BITS_38_7',
}
BITS_31_0 = 0
BITS_32_1 = 1
BITS_33_2 = 2
BITS_34_3 = 3
BITS_35_4 = 4
BITS_36_5 = 5
BITS_37_6 = 6
BITS_38_7 = 7
DC_DMCUB_TIMER_WINDOW = ctypes.c_uint32 # enum
# values for enumeration 'INVALID_REG_ACCESS_TYPE'
INVALID_REG_ACCESS_TYPE__enumvalues = {
0: 'REG_UNALLOCATED_ADDR_WRITE',
1: 'REG_UNALLOCATED_ADDR_READ',
2: 'REG_VIRTUAL_WRITE',
3: 'REG_VIRTUAL_READ',
4: 'REG_SECURE_VIOLATE_WRITE',
5: 'REG_SECURE_VIOLATE_READ',
}
REG_UNALLOCATED_ADDR_WRITE = 0
REG_UNALLOCATED_ADDR_READ = 1
REG_VIRTUAL_WRITE = 2
REG_VIRTUAL_READ = 3
REG_SECURE_VIOLATE_WRITE = 4
REG_SECURE_VIOLATE_READ = 5
INVALID_REG_ACCESS_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DMU_DC_GPU_TIMER_READ_SELECT'
DMU_DC_GPU_TIMER_READ_SELECT__enumvalues = {
0: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0',
1: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1',
2: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2',
3: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3',
4: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4',
5: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5',
6: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6',
7: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7',
8: 'RESERVED_8',
9: 'RESERVED_9',
10: 'RESERVED_10',
11: 'RESERVED_11',
12: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12',
13: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13',
14: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14',
15: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15',
16: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16',
17: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17',
18: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18',
19: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19',
20: 'RESERVED_20',
21: 'RESERVED_21',
22: 'RESERVED_22',
23: 'RESERVED_23',
24: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24',
25: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25',
26: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26',
27: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27',
28: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28',
29: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29',
30: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30',
31: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31',
32: 'RESERVED_32',
33: 'RESERVED_33',
34: 'RESERVED_34',
35: 'RESERVED_35',
36: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36',
37: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37',
38: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38',
39: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39',
40: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40',
41: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41',
42: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42',
43: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43',
44: 'RESERVED_44',
45: 'RESERVED_45',
46: 'RESERVED_46',
47: 'RESERVED_47',
48: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48',
49: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49',
50: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50',
51: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51',
52: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52',
53: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53',
54: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54',
55: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55',
56: 'RESERVED_56',
57: 'RESERVED_57',
58: 'RESERVED_58',
59: 'RESERVED_59',
60: 'RESERVED_60',
61: 'RESERVED_61',
62: 'RESERVED_62',
63: 'RESERVED_63',
64: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64',
65: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65',
66: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66',
67: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67',
68: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68',
69: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69',
70: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70',
71: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71',
72: 'RESERVED_72',
73: 'RESERVED_73',
74: 'RESERVED_74',
75: 'RESERVED_75',
76: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76',
77: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77',
78: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78',
79: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79',
80: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80',
81: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81',
82: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82',
83: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83',
84: 'RESERVED_84',
85: 'RESERVED_85',
86: 'RESERVED_86',
87: 'RESERVED_87',
88: 'RESERVED_88',
89: 'RESERVED_89',
90: 'RESERVED_90',
91: 'RESERVED_91',
}
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 1
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 2
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 3
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 4
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 5
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 6
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 7
RESERVED_8 = 8
RESERVED_9 = 9
RESERVED_10 = 10
RESERVED_11 = 11
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 12
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 13
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 14
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 15
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 16
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 17
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 18
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 19
RESERVED_20 = 20
RESERVED_21 = 21
RESERVED_22 = 22
RESERVED_23 = 23
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 24
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 25
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 26
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 27
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 28
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 29
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 30
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 31
RESERVED_32 = 32
RESERVED_33 = 33
RESERVED_34 = 34
RESERVED_35 = 35
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 36
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 37
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 38
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 39
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 40
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 41
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 42
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 43
RESERVED_44 = 44
RESERVED_45 = 45
RESERVED_46 = 46
RESERVED_47 = 47
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 48
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 49
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 50
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 51
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 52
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 53
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 54
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 55
RESERVED_56 = 56
RESERVED_57 = 57
RESERVED_58 = 58
RESERVED_59 = 59
RESERVED_60 = 60
RESERVED_61 = 61
RESERVED_62 = 62
RESERVED_63 = 63
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 64
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 65
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 66
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 67
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 68
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 69
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 70
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 71
RESERVED_72 = 72
RESERVED_73 = 73
RESERVED_74 = 74
RESERVED_75 = 75
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 76
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 77
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 78
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 79
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 80
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 81
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 82
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 83
RESERVED_84 = 84
RESERVED_85 = 85
RESERVED_86 = 86
RESERVED_87 = 87
RESERVED_88 = 88
RESERVED_89 = 89
RESERVED_90 = 90
RESERVED_91 = 91
DMU_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DMU_DC_GPU_TIMER_START_POSITION'
DMU_DC_GPU_TIMER_START_POSITION__enumvalues = {
0: 'DMU_GPU_TIMER_START_0_END_27',
1: 'DMU_GPU_TIMER_START_1_END_28',
2: 'DMU_GPU_TIMER_START_2_END_29',
3: 'DMU_GPU_TIMER_START_3_END_30',
4: 'DMU_GPU_TIMER_START_4_END_31',
5: 'DMU_GPU_TIMER_START_6_END_33',
6: 'DMU_GPU_TIMER_START_8_END_35',
7: 'DMU_GPU_TIMER_START_10_END_37',
}
DMU_GPU_TIMER_START_0_END_27 = 0
DMU_GPU_TIMER_START_1_END_28 = 1
DMU_GPU_TIMER_START_2_END_29 = 2
DMU_GPU_TIMER_START_3_END_30 = 3
DMU_GPU_TIMER_START_4_END_31 = 4
DMU_GPU_TIMER_START_6_END_33 = 5
DMU_GPU_TIMER_START_8_END_35 = 6
DMU_GPU_TIMER_START_10_END_37 = 7
DMU_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum
# values for enumeration 'IHC_INTERRUPT_DEST'
IHC_INTERRUPT_DEST__enumvalues = {
0: 'INTERRUPT_SENT_TO_IH',
1: 'INTERRUPT_SENT_TO_DMCUB',
}
INTERRUPT_SENT_TO_IH = 0
INTERRUPT_SENT_TO_DMCUB = 1
IHC_INTERRUPT_DEST = ctypes.c_uint32 # enum
# values for enumeration 'IHC_INTERRUPT_LINE_STATUS'
IHC_INTERRUPT_LINE_STATUS__enumvalues = {
0: 'INTERRUPT_LINE_NOT_ASSERTED',
1: 'INTERRUPT_LINE_ASSERTED',
}
INTERRUPT_LINE_NOT_ASSERTED = 0
INTERRUPT_LINE_ASSERTED = 1
IHC_INTERRUPT_LINE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'DC_SMU_INTERRUPT_ENABLE'
DC_SMU_INTERRUPT_ENABLE__enumvalues = {
0: 'DISABLE_THE_INTERRUPT',
1: 'ENABLE_THE_INTERRUPT',
}
DISABLE_THE_INTERRUPT = 0
ENABLE_THE_INTERRUPT = 1
DC_SMU_INTERRUPT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'DMU_CLOCK_ON'
DMU_CLOCK_ON__enumvalues = {
0: 'DMU_CLOCK_STATUS_ON',
1: 'DMU_CLOCK_STATUS_OFF',
}
DMU_CLOCK_STATUS_ON = 0
DMU_CLOCK_STATUS_OFF = 1
DMU_CLOCK_ON = ctypes.c_uint32 # enum
# values for enumeration 'SMU_INTR'
SMU_INTR__enumvalues = {
0: 'SMU_MSG_INTR_NOOP',
1: 'SET_SMU_MSG_INTR',
}
SMU_MSG_INTR_NOOP = 0
SET_SMU_MSG_INTR = 1
SMU_INTR = ctypes.c_uint32 # enum
# values for enumeration 'ALLOW_SR_ON_TRANS_REQ'
ALLOW_SR_ON_TRANS_REQ__enumvalues = {
0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE',
1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE',
}
ALLOW_SR_ON_TRANS_REQ_ENABLE = 0
ALLOW_SR_ON_TRANS_REQ_DISABLE = 1
ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum
# values for enumeration 'AMCLOCK_ENABLE'
AMCLOCK_ENABLE__enumvalues = {
0: 'ENABLE_AMCLK0',
1: 'ENABLE_AMCLK1',
}
ENABLE_AMCLK0 = 0
ENABLE_AMCLK1 = 1
AMCLOCK_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'CLEAR_SMU_INTR'
CLEAR_SMU_INTR__enumvalues = {
0: 'SMU_INTR_STATUS_NOOP',
1: 'SMU_INTR_STATUS_CLEAR',
}
SMU_INTR_STATUS_NOOP = 0
SMU_INTR_STATUS_CLEAR = 1
CLEAR_SMU_INTR = ctypes.c_uint32 # enum
# values for enumeration 'CLOCK_BRANCH_SOFT_RESET'
CLOCK_BRANCH_SOFT_RESET__enumvalues = {
0: 'CLOCK_BRANCH_SOFT_RESET_NOOP',
1: 'CLOCK_BRANCH_SOFT_RESET_FORCE',
}
CLOCK_BRANCH_SOFT_RESET_NOOP = 0
CLOCK_BRANCH_SOFT_RESET_FORCE = 1
CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL'
DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = {
0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0',
1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1',
2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2',
3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3',
4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED',
}
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 1
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 2
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 3
DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 4
DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL'
DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = {
0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0',
1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2',
}
DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0
DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 1
DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_AUDIO_DTO_SEL'
DCCG_AUDIO_DTO_SEL__enumvalues = {
0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0',
1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1',
2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO',
}
DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0
DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1
DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2
DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO'
DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = {
0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP',
1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP',
}
DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0
DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1
DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_DBG_BLOCK_SEL'
DCCG_DBG_BLOCK_SEL__enumvalues = {
0: 'DCCG_DBG_BLOCK_SEL_DCCG',
1: 'DCCG_DBG_BLOCK_SEL_PMON',
2: 'DCCG_DBG_BLOCK_SEL_PMON2',
}
DCCG_DBG_BLOCK_SEL_DCCG = 0
DCCG_DBG_BLOCK_SEL_PMON = 1
DCCG_DBG_BLOCK_SEL_PMON2 = 2
DCCG_DBG_BLOCK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_DBG_EN'
DCCG_DBG_EN__enumvalues = {
0: 'DCCG_DBG_EN_DISABLE',
1: 'DCCG_DBG_EN_ENABLE',
}
DCCG_DBG_EN_DISABLE = 0
DCCG_DBG_EN_ENABLE = 1
DCCG_DBG_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_DEEP_COLOR_CNTL'
DCCG_DEEP_COLOR_CNTL__enumvalues = {
0: 'DCCG_DEEP_COLOR_DTO_DISABLE',
1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO',
2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO',
3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO',
}
DCCG_DEEP_COLOR_DTO_DISABLE = 0
DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1
DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2
DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3
DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN'
DCCG_FIFO_ERRDET_OVR_EN__enumvalues = {
0: 'DCCG_FIFO_ERRDET_OVR_DISABLE',
1: 'DCCG_FIFO_ERRDET_OVR_ENABLE',
}
DCCG_FIFO_ERRDET_OVR_DISABLE = 0
DCCG_FIFO_ERRDET_OVR_ENABLE = 1
DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_FIFO_ERRDET_RESET'
DCCG_FIFO_ERRDET_RESET__enumvalues = {
0: 'DCCG_FIFO_ERRDET_RESET_NOOP',
1: 'DCCG_FIFO_ERRDET_RESET_FORCE',
}
DCCG_FIFO_ERRDET_RESET_NOOP = 0
DCCG_FIFO_ERRDET_RESET_FORCE = 1
DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_FIFO_ERRDET_STATE'
DCCG_FIFO_ERRDET_STATE__enumvalues = {
0: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION',
1: 'DCCG_FIFO_ERRDET_STATE_DETECTION',
}
DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0
DCCG_FIFO_ERRDET_STATE_DETECTION = 1
DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_PERF_MODE_HSYNC'
DCCG_PERF_MODE_HSYNC__enumvalues = {
0: 'DCCG_PERF_MODE_HSYNC_NOOP',
1: 'DCCG_PERF_MODE_HSYNC_START',
}
DCCG_PERF_MODE_HSYNC_NOOP = 0
DCCG_PERF_MODE_HSYNC_START = 1
DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_PERF_MODE_VSYNC'
DCCG_PERF_MODE_VSYNC__enumvalues = {
0: 'DCCG_PERF_MODE_VSYNC_NOOP',
1: 'DCCG_PERF_MODE_VSYNC_START',
}
DCCG_PERF_MODE_VSYNC_NOOP = 0
DCCG_PERF_MODE_VSYNC_START = 1
DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_PERF_OTG_SELECT'
DCCG_PERF_OTG_SELECT__enumvalues = {
0: 'DCCG_PERF_SEL_OTG0',
1: 'DCCG_PERF_SEL_OTG1',
2: 'DCCG_PERF_SEL_OTG2',
3: 'DCCG_PERF_SEL_OTG3',
4: 'DCCG_PERF_SEL_RESERVED',
}
DCCG_PERF_SEL_OTG0 = 0
DCCG_PERF_SEL_OTG1 = 1
DCCG_PERF_SEL_OTG2 = 2
DCCG_PERF_SEL_OTG3 = 3
DCCG_PERF_SEL_RESERVED = 4
DCCG_PERF_OTG_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_PERF_RUN'
DCCG_PERF_RUN__enumvalues = {
0: 'DCCG_PERF_RUN_NOOP',
1: 'DCCG_PERF_RUN_START',
}
DCCG_PERF_RUN_NOOP = 0
DCCG_PERF_RUN_START = 1
DCCG_PERF_RUN = ctypes.c_uint32 # enum
# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS'
DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = {
0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE',
1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE',
}
DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0
DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1
DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum
# values for enumeration 'DIO_FIFO_ERROR'
DIO_FIFO_ERROR__enumvalues = {
0: 'DIO_FIFO_ERROR_00',
1: 'DIO_FIFO_ERROR_01',
2: 'DIO_FIFO_ERROR_10',
3: 'DIO_FIFO_ERROR_11',
}
DIO_FIFO_ERROR_00 = 0
DIO_FIFO_ERROR_01 = 1
DIO_FIFO_ERROR_10 = 2
DIO_FIFO_ERROR_11 = 3
DIO_FIFO_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'DISABLE_CLOCK_GATING'
DISABLE_CLOCK_GATING__enumvalues = {
0: 'CLOCK_GATING_ENABLED',
1: 'CLOCK_GATING_DISABLED',
}
CLOCK_GATING_ENABLED = 0
CLOCK_GATING_DISABLED = 1
DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum
# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO'
DISABLE_CLOCK_GATING_IN_DCO__enumvalues = {
0: 'CLOCK_GATING_ENABLED_IN_DCO',
1: 'CLOCK_GATING_DISABLED_IN_DCO',
}
CLOCK_GATING_ENABLED_IN_DCO = 0
CLOCK_GATING_DISABLED_IN_DCO = 1
DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum
# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE'
DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = {
0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING',
1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING',
}
DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0
DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1
DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'DISPCLK_FREQ_RAMP_DONE'
DISPCLK_FREQ_RAMP_DONE__enumvalues = {
0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS',
1: 'DISPCLK_FREQ_RAMP_COMPLETED',
}
DISPCLK_FREQ_RAMP_IN_PROGRESS = 0
DISPCLK_FREQ_RAMP_COMPLETED = 1
DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum
# values for enumeration 'DPREFCLK_SRC_SEL'
DPREFCLK_SRC_SEL__enumvalues = {
0: 'DPREFCLK_SRC_SEL_CK',
1: 'DPREFCLK_SRC_SEL_P0PLL',
2: 'DPREFCLK_SRC_SEL_P1PLL',
3: 'DPREFCLK_SRC_SEL_P2PLL',
}
DPREFCLK_SRC_SEL_CK = 0
DPREFCLK_SRC_SEL_P0PLL = 1
DPREFCLK_SRC_SEL_P1PLL = 2
DPREFCLK_SRC_SEL_P2PLL = 3
DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DP_DTO_DS_DISABLE'
DP_DTO_DS_DISABLE__enumvalues = {
0: 'DP_DTO_DESPREAD_DISABLE',
1: 'DP_DTO_DESPREAD_ENABLE',
}
DP_DTO_DESPREAD_DISABLE = 0
DP_DTO_DESPREAD_ENABLE = 1
DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'DS_HW_CAL_ENABLE'
DS_HW_CAL_ENABLE__enumvalues = {
0: 'DS_HW_CAL_DIS',
1: 'DS_HW_CAL_EN',
}
DS_HW_CAL_DIS = 0
DS_HW_CAL_EN = 1
DS_HW_CAL_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'DS_REF_SRC'
DS_REF_SRC__enumvalues = {
0: 'DS_REF_IS_XTALIN',
1: 'DS_REF_IS_EXT_GENLOCK',
2: 'DS_REF_IS_PCIE',
}
DS_REF_IS_XTALIN = 0
DS_REF_IS_EXT_GENLOCK = 1
DS_REF_IS_PCIE = 2
DS_REF_SRC = ctypes.c_uint32 # enum
# values for enumeration 'DVO_ENABLE_RST'
DVO_ENABLE_RST__enumvalues = {
0: 'DVO_ENABLE_RST_DISABLE',
1: 'DVO_ENABLE_RST_ENABLE',
}
DVO_ENABLE_RST_DISABLE = 0
DVO_ENABLE_RST_ENABLE = 1
DVO_ENABLE_RST = ctypes.c_uint32 # enum
# values for enumeration 'ENABLE'
ENABLE__enumvalues = {
0: 'DISABLE_THE_FEATURE',
1: 'ENABLE_THE_FEATURE',
}
DISABLE_THE_FEATURE = 0
ENABLE_THE_FEATURE = 1
ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'ENABLE_CLOCK'
ENABLE_CLOCK__enumvalues = {
0: 'ENABLE_THE_REFCLK',
1: 'ENABLE_THE_FUNC_CLOCK',
}
ENABLE_THE_REFCLK = 0
ENABLE_THE_FUNC_CLOCK = 1
ENABLE_CLOCK = ctypes.c_uint32 # enum
# values for enumeration 'FORCE_DISABLE_CLOCK'
FORCE_DISABLE_CLOCK__enumvalues = {
0: 'NOT_FORCE_THE_CLOCK_DISABLED',
1: 'FORCE_THE_CLOCK_DISABLED',
}
NOT_FORCE_THE_CLOCK_DISABLED = 0
FORCE_THE_CLOCK_DISABLED = 1
FORCE_DISABLE_CLOCK = ctypes.c_uint32 # enum
# values for enumeration 'HDMICHARCLK_SRC_SEL'
HDMICHARCLK_SRC_SEL__enumvalues = {
0: 'HDMICHARCLK_SRC_SEL_UNIPHYA',
1: 'HDMICHARCLK_SRC_SEL_UNIPHYB',
2: 'HDMICHARCLK_SRC_SEL_UNIPHYC',
3: 'HDMICHARCLK_SRC_SEL_UNIPHYD',
4: 'HDMICHARCLK_SRC_SEL_SRC_RESERVED',
}
HDMICHARCLK_SRC_SEL_UNIPHYA = 0
HDMICHARCLK_SRC_SEL_UNIPHYB = 1
HDMICHARCLK_SRC_SEL_UNIPHYC = 2
HDMICHARCLK_SRC_SEL_UNIPHYD = 3
HDMICHARCLK_SRC_SEL_SRC_RESERVED = 4
HDMICHARCLK_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'HDMISTREAMCLK_SRC_SEL'
HDMISTREAMCLK_SRC_SEL__enumvalues = {
0: 'SEL_DTBCLK_P0',
1: 'SEL_DTBCLK_P1',
2: 'SEL_DTBCLK_P2',
3: 'SEL_DTBCLK_P3',
}
SEL_DTBCLK_P0 = 0
SEL_DTBCLK_P1 = 1
SEL_DTBCLK_P2 = 2
SEL_DTBCLK_P3 = 3
HDMISTREAMCLK_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'JITTER_REMOVE_DISABLE'
JITTER_REMOVE_DISABLE__enumvalues = {
0: 'ENABLE_JITTER_REMOVAL',
1: 'DISABLE_JITTER_REMOVAL',
}
ENABLE_JITTER_REMOVAL = 0
DISABLE_JITTER_REMOVAL = 1
JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL'
MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = {
0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN',
1: 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK',
}
MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0
MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1
MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL'
MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = {
0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN',
1: 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK',
}
MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0
MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1
MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_ADD_PIXEL'
OTG_ADD_PIXEL__enumvalues = {
0: 'OTG_ADD_PIXEL_NOOP',
1: 'OTG_ADD_PIXEL_FORCE',
}
OTG_ADD_PIXEL_NOOP = 0
OTG_ADD_PIXEL_FORCE = 1
OTG_ADD_PIXEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DROP_PIXEL'
OTG_DROP_PIXEL__enumvalues = {
0: 'OTG_DROP_PIXEL_NOOP',
1: 'OTG_DROP_PIXEL_FORCE',
}
OTG_DROP_PIXEL_NOOP = 0
OTG_DROP_PIXEL_FORCE = 1
OTG_DROP_PIXEL = ctypes.c_uint32 # enum
# values for enumeration 'PHYSYMCLK_FORCE_EN'
PHYSYMCLK_FORCE_EN__enumvalues = {
0: 'PHYSYMCLK_FORCE_EN_DISABLE',
1: 'PHYSYMCLK_FORCE_EN_ENABLE',
}
PHYSYMCLK_FORCE_EN_DISABLE = 0
PHYSYMCLK_FORCE_EN_ENABLE = 1
PHYSYMCLK_FORCE_EN = ctypes.c_uint32 # enum
# values for enumeration 'PHYSYMCLK_FORCE_SRC_SEL'
PHYSYMCLK_FORCE_SRC_SEL__enumvalues = {
0: 'PHYSYMCLK_FORCE_SRC_SYMCLK',
1: 'PHYSYMCLK_FORCE_SRC_PHYD18CLK',
2: 'PHYSYMCLK_FORCE_SRC_PHYD32CLK',
}
PHYSYMCLK_FORCE_SRC_SYMCLK = 0
PHYSYMCLK_FORCE_SRC_PHYD18CLK = 1
PHYSYMCLK_FORCE_SRC_PHYD32CLK = 2
PHYSYMCLK_FORCE_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE'
PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = {
0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA',
1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB',
2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC',
3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD',
4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED',
}
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3
PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 4
PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE'
PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = {
0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL',
1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL',
}
PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0
PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1
PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_PIXEL_RATE_SOURCE'
PIPE_PIXEL_RATE_SOURCE__enumvalues = {
0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL',
1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL',
2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL',
}
PIPE_PIXEL_RATE_SOURCE_P0PLL = 0
PIPE_PIXEL_RATE_SOURCE_P1PLL = 1
PIPE_PIXEL_RATE_SOURCE_P2PLL = 2
PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'PLL_CFG_IF_SOFT_RESET'
PLL_CFG_IF_SOFT_RESET__enumvalues = {
0: 'PLL_CFG_IF_SOFT_RESET_NOOP',
1: 'PLL_CFG_IF_SOFT_RESET_FORCE',
}
PLL_CFG_IF_SOFT_RESET_NOOP = 0
PLL_CFG_IF_SOFT_RESET_FORCE = 1
PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'SYMCLK_FE_SRC'
SYMCLK_FE_SRC__enumvalues = {
0: 'SYMCLK_FE_SRC_UNIPHYA',
1: 'SYMCLK_FE_SRC_UNIPHYB',
2: 'SYMCLK_FE_SRC_UNIPHYC',
3: 'SYMCLK_FE_SRC_UNIPHYD',
4: 'SYMCLK_FE_SRC_RESERVED',
}
SYMCLK_FE_SRC_UNIPHYA = 0
SYMCLK_FE_SRC_UNIPHYB = 1
SYMCLK_FE_SRC_UNIPHYC = 2
SYMCLK_FE_SRC_UNIPHYD = 3
SYMCLK_FE_SRC_RESERVED = 4
SYMCLK_FE_SRC = ctypes.c_uint32 # enum
# values for enumeration 'TEST_CLK_DIV_SEL'
TEST_CLK_DIV_SEL__enumvalues = {
0: 'NO_DIV',
1: 'DIV_2',
2: 'DIV_4',
3: 'DIV_8',
}
NO_DIV = 0
DIV_2 = 1
DIV_4 = 2
DIV_8 = 3
TEST_CLK_DIV_SEL = ctypes.c_uint32 # enum
# values for enumeration 'VSYNC_CNT_LATCH_MASK'
VSYNC_CNT_LATCH_MASK__enumvalues = {
0: 'VSYNC_CNT_LATCH_MASK_0',
1: 'VSYNC_CNT_LATCH_MASK_1',
}
VSYNC_CNT_LATCH_MASK_0 = 0
VSYNC_CNT_LATCH_MASK_1 = 1
VSYNC_CNT_LATCH_MASK = ctypes.c_uint32 # enum
# values for enumeration 'VSYNC_CNT_RESET_SEL'
VSYNC_CNT_RESET_SEL__enumvalues = {
0: 'VSYNC_CNT_RESET_SEL_0',
1: 'VSYNC_CNT_RESET_SEL_1',
}
VSYNC_CNT_RESET_SEL_0 = 0
VSYNC_CNT_RESET_SEL_1 = 1
VSYNC_CNT_RESET_SEL = ctypes.c_uint32 # enum
# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL'
XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = {
0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN',
1: 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK',
}
XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0
XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 1
XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'XTAL_REF_SEL'
XTAL_REF_SEL__enumvalues = {
0: 'XTAL_REF_SEL_1X',
1: 'XTAL_REF_SEL_2X',
}
XTAL_REF_SEL_1X = 0
XTAL_REF_SEL_2X = 1
XTAL_REF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_8B10B_CUR_DISP'
DPHY_8B10B_CUR_DISP__enumvalues = {
0: 'DPHY_8B10B_CUR_DISP_ZERO',
1: 'DPHY_8B10B_CUR_DISP_ONE',
}
DPHY_8B10B_CUR_DISP_ZERO = 0
DPHY_8B10B_CUR_DISP_ONE = 1
DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_8B10B_RESET'
DPHY_8B10B_RESET__enumvalues = {
0: 'DPHY_8B10B_NOT_RESET',
1: 'DPHY_8B10B_RESETET',
}
DPHY_8B10B_NOT_RESET = 0
DPHY_8B10B_RESETET = 1
DPHY_8B10B_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ATEST_SEL_LANE0'
DPHY_ATEST_SEL_LANE0__enumvalues = {
0: 'DPHY_ATEST_LANE0_PRBS_PATTERN',
1: 'DPHY_ATEST_LANE0_REG_PATTERN',
}
DPHY_ATEST_LANE0_PRBS_PATTERN = 0
DPHY_ATEST_LANE0_REG_PATTERN = 1
DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ATEST_SEL_LANE1'
DPHY_ATEST_SEL_LANE1__enumvalues = {
0: 'DPHY_ATEST_LANE1_PRBS_PATTERN',
1: 'DPHY_ATEST_LANE1_REG_PATTERN',
}
DPHY_ATEST_LANE1_PRBS_PATTERN = 0
DPHY_ATEST_LANE1_REG_PATTERN = 1
DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ATEST_SEL_LANE2'
DPHY_ATEST_SEL_LANE2__enumvalues = {
0: 'DPHY_ATEST_LANE2_PRBS_PATTERN',
1: 'DPHY_ATEST_LANE2_REG_PATTERN',
}
DPHY_ATEST_LANE2_PRBS_PATTERN = 0
DPHY_ATEST_LANE2_REG_PATTERN = 1
DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ATEST_SEL_LANE3'
DPHY_ATEST_SEL_LANE3__enumvalues = {
0: 'DPHY_ATEST_LANE3_PRBS_PATTERN',
1: 'DPHY_ATEST_LANE3_REG_PATTERN',
}
DPHY_ATEST_LANE3_PRBS_PATTERN = 0
DPHY_ATEST_LANE3_REG_PATTERN = 1
DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_BYPASS'
DPHY_BYPASS__enumvalues = {
0: 'DPHY_8B10B_OUTPUT',
1: 'DPHY_DBG_OUTPUT',
}
DPHY_8B10B_OUTPUT = 0
DPHY_DBG_OUTPUT = 1
DPHY_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_CONT_EN'
DPHY_CRC_CONT_EN__enumvalues = {
0: 'DPHY_CRC_ONE_SHOT',
1: 'DPHY_CRC_CONTINUOUS',
}
DPHY_CRC_ONE_SHOT = 0
DPHY_CRC_CONTINUOUS = 1
DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_EN'
DPHY_CRC_EN__enumvalues = {
0: 'DPHY_CRC_DISABLED',
1: 'DPHY_CRC_ENABLED',
}
DPHY_CRC_DISABLED = 0
DPHY_CRC_ENABLED = 1
DPHY_CRC_EN = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_FIELD'
DPHY_CRC_FIELD__enumvalues = {
0: 'DPHY_CRC_START_FROM_TOP_FIELD',
1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD',
}
DPHY_CRC_START_FROM_TOP_FIELD = 0
DPHY_CRC_START_FROM_BOTTOM_FIELD = 1
DPHY_CRC_FIELD = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK'
DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = {
0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK',
1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED',
}
DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0
DPHY_CRC_MST_PHASE_ERROR_ACKED = 1
DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_SEL'
DPHY_CRC_SEL__enumvalues = {
0: 'DPHY_CRC_LANE0_SELECTED',
1: 'DPHY_CRC_LANE1_SELECTED',
2: 'DPHY_CRC_LANE2_SELECTED',
3: 'DPHY_CRC_LANE3_SELECTED',
}
DPHY_CRC_LANE0_SELECTED = 0
DPHY_CRC_LANE1_SELECTED = 1
DPHY_CRC_LANE2_SELECTED = 2
DPHY_CRC_LANE3_SELECTED = 3
DPHY_CRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_FEC_ENABLE'
DPHY_FEC_ENABLE__enumvalues = {
0: 'DPHY_FEC_DISABLED',
1: 'DPHY_FEC_ENABLED',
}
DPHY_FEC_DISABLED = 0
DPHY_FEC_ENABLED = 1
DPHY_FEC_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_FEC_READY'
DPHY_FEC_READY__enumvalues = {
0: 'DPHY_FEC_READY_EN',
1: 'DPHY_FEC_READY_DIS',
}
DPHY_FEC_READY_EN = 0
DPHY_FEC_READY_DIS = 1
DPHY_FEC_READY = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_LOAD_BS_COUNT_START'
DPHY_LOAD_BS_COUNT_START__enumvalues = {
0: 'DPHY_LOAD_BS_COUNT_STARTED',
1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED',
}
DPHY_LOAD_BS_COUNT_STARTED = 0
DPHY_LOAD_BS_COUNT_NOT_STARTED = 1
DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_PRBS_EN'
DPHY_PRBS_EN__enumvalues = {
0: 'DPHY_PRBS_DISABLE',
1: 'DPHY_PRBS_ENABLE',
}
DPHY_PRBS_DISABLE = 0
DPHY_PRBS_ENABLE = 1
DPHY_PRBS_EN = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_PRBS_SEL'
DPHY_PRBS_SEL__enumvalues = {
0: 'DPHY_PRBS7_SELECTED',
1: 'DPHY_PRBS23_SELECTED',
2: 'DPHY_PRBS11_SELECTED',
}
DPHY_PRBS7_SELECTED = 0
DPHY_PRBS23_SELECTED = 1
DPHY_PRBS11_SELECTED = 2
DPHY_PRBS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE'
DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = {
0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0',
1: 'DPHY_FAST_TRAINING_CAPABLE',
}
DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0
DPHY_FAST_TRAINING_CAPABLE = 1
DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_SKEW_BYPASS'
DPHY_SKEW_BYPASS__enumvalues = {
0: 'DPHY_WITH_SKEW',
1: 'DPHY_NO_SKEW',
}
DPHY_WITH_SKEW = 0
DPHY_NO_SKEW = 1
DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM'
DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM__enumvalues = {
0: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET',
1: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET',
}
DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0
DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 1
DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_SW_FAST_TRAINING_START'
DPHY_SW_FAST_TRAINING_START__enumvalues = {
0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED',
1: 'DPHY_SW_FAST_TRAINING_STARTED',
}
DPHY_SW_FAST_TRAINING_NOT_STARTED = 0
DPHY_SW_FAST_TRAINING_STARTED = 1
DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_TRAINING_PATTERN_SEL'
DPHY_TRAINING_PATTERN_SEL__enumvalues = {
0: 'DPHY_TRAINING_PATTERN_1',
1: 'DPHY_TRAINING_PATTERN_2',
2: 'DPHY_TRAINING_PATTERN_3',
3: 'DPHY_TRAINING_PATTERN_4',
}
DPHY_TRAINING_PATTERN_1 = 0
DPHY_TRAINING_PATTERN_2 = 1
DPHY_TRAINING_PATTERN_3 = 2
DPHY_TRAINING_PATTERN_4 = 3
DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DP_COMPONENT_DEPTH'
DP_COMPONENT_DEPTH__enumvalues = {
0: 'DP_COMPONENT_DEPTH_6BPC',
1: 'DP_COMPONENT_DEPTH_8BPC',
2: 'DP_COMPONENT_DEPTH_10BPC',
3: 'DP_COMPONENT_DEPTH_12BPC',
4: 'DP_COMPONENT_DEPTH_16BPC',
}
DP_COMPONENT_DEPTH_6BPC = 0
DP_COMPONENT_DEPTH_8BPC = 1
DP_COMPONENT_DEPTH_10BPC = 2
DP_COMPONENT_DEPTH_12BPC = 3
DP_COMPONENT_DEPTH_16BPC = 4
DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'DP_COMPRESSED_PIXEL_FORMAT'
DP_COMPRESSED_PIXEL_FORMAT__enumvalues = {
0: 'DP_DSC_444_S422',
1: 'DP_DSC_N422_N420',
}
DP_DSC_444_S422 = 0
DP_DSC_N422_N420 = 1
DP_COMPRESSED_PIXEL_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_8B10B_EXT_DISP'
DP_DPHY_8B10B_EXT_DISP__enumvalues = {
0: 'DP_DPHY_8B10B_EXT_DISP_ZERO',
1: 'DP_DPHY_8B10B_EXT_DISP_ONE',
}
DP_DPHY_8B10B_EXT_DISP_ZERO = 0
DP_DPHY_8B10B_EXT_DISP_ONE = 1
DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK'
DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = {
0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED',
1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED',
}
DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0
DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1
DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK'
DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = {
0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED',
1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED',
}
DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0
DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1
DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN'
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = {
0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED',
1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED',
}
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE'
DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = {
0: 'DP_DPHY_HBR2_PASS_THROUGH',
1: 'DP_DPHY_HBR2_PATTERN_1',
2: 'DP_DPHY_HBR2_PATTERN_2_NEG',
3: 'DP_DPHY_HBR2_PATTERN_3',
6: 'DP_DPHY_HBR2_PATTERN_2_POS',
}
DP_DPHY_HBR2_PASS_THROUGH = 0
DP_DPHY_HBR2_PATTERN_1 = 1
DP_DPHY_HBR2_PATTERN_2_NEG = 2
DP_DPHY_HBR2_PATTERN_3 = 3
DP_DPHY_HBR2_PATTERN_2_POS = 6
DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_LINK_TRAINING_COMPLETE'
DP_LINK_TRAINING_COMPLETE__enumvalues = {
0: 'DP_LINK_TRAINING_NOT_COMPLETE',
1: 'DP_LINK_TRAINING_ALREADY_COMPLETE',
}
DP_LINK_TRAINING_NOT_COMPLETE = 0
DP_LINK_TRAINING_ALREADY_COMPLETE = 1
DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum
# values for enumeration 'DP_LINK_TRAINING_SWITCH_MODE'
DP_LINK_TRAINING_SWITCH_MODE__enumvalues = {
0: 'DP_LINK_TRAINING_SWITCH_TO_IDLE',
1: 'DP_LINK_TRAINING_SWITCH_TO_VIDEO',
}
DP_LINK_TRAINING_SWITCH_TO_IDLE = 0
DP_LINK_TRAINING_SWITCH_TO_VIDEO = 1
DP_LINK_TRAINING_SWITCH_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_ML_PHY_SEQ_MODE'
DP_ML_PHY_SEQ_MODE__enumvalues = {
0: 'DP_ML_PHY_SEQ_LINE_NUM',
1: 'DP_ML_PHY_SEQ_IMMEDIATE',
}
DP_ML_PHY_SEQ_LINE_NUM = 0
DP_ML_PHY_SEQ_IMMEDIATE = 1
DP_ML_PHY_SEQ_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN'
DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = {
0: 'MSA_V_TIMING_OVERRIDE_DISABLED',
1: 'MSA_V_TIMING_OVERRIDE_ENABLED',
}
MSA_V_TIMING_OVERRIDE_DISABLED = 0
MSA_V_TIMING_OVERRIDE_ENABLED = 1
DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_BLANK_CODE'
DP_MSE_BLANK_CODE__enumvalues = {
0: 'DP_MSE_BLANK_CODE_SF_FILLED',
1: 'DP_MSE_BLANK_CODE_ZERO_FILLED',
}
DP_MSE_BLANK_CODE_SF_FILLED = 0
DP_MSE_BLANK_CODE_ZERO_FILLED = 1
DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_LINK_LINE'
DP_MSE_LINK_LINE__enumvalues = {
0: 'DP_MSE_LINK_LINE_32_MTP_LONG',
1: 'DP_MSE_LINK_LINE_64_MTP_LONG',
2: 'DP_MSE_LINK_LINE_128_MTP_LONG',
3: 'DP_MSE_LINK_LINE_256_MTP_LONG',
}
DP_MSE_LINK_LINE_32_MTP_LONG = 0
DP_MSE_LINK_LINE_64_MTP_LONG = 1
DP_MSE_LINK_LINE_128_MTP_LONG = 2
DP_MSE_LINK_LINE_256_MTP_LONG = 3
DP_MSE_LINK_LINE = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_TIMESTAMP_MODE'
DP_MSE_TIMESTAMP_MODE__enumvalues = {
0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE',
1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE',
}
DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0
DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1
DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_ZERO_ENCODER'
DP_MSE_ZERO_ENCODER__enumvalues = {
0: 'DP_MSE_NOT_ZERO_FE_ENCODER',
1: 'DP_MSE_ZERO_FE_ENCODER',
}
DP_MSE_NOT_ZERO_FE_ENCODER = 0
DP_MSE_ZERO_FE_ENCODER = 1
DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSO_NUM_OF_SST_LINKS'
DP_MSO_NUM_OF_SST_LINKS__enumvalues = {
0: 'DP_MSO_ONE_SSTLINK',
1: 'DP_MSO_TWO_SSTLINK',
2: 'DP_MSO_FOUR_SSTLINK',
}
DP_MSO_ONE_SSTLINK = 0
DP_MSO_TWO_SSTLINK = 1
DP_MSO_FOUR_SSTLINK = 2
DP_MSO_NUM_OF_SST_LINKS = ctypes.c_uint32 # enum
# values for enumeration 'DP_PIXEL_ENCODING'
DP_PIXEL_ENCODING__enumvalues = {
0: 'DP_PIXEL_ENCODING_RGB_YCBCR444',
1: 'DP_PIXEL_ENCODING_YCBCR422',
2: 'DP_PIXEL_ENCODING_YCBCR420',
3: 'DP_PIXEL_ENCODING_Y_ONLY',
}
DP_PIXEL_ENCODING_RGB_YCBCR444 = 0
DP_PIXEL_ENCODING_YCBCR422 = 1
DP_PIXEL_ENCODING_YCBCR420 = 2
DP_PIXEL_ENCODING_Y_ONLY = 3
DP_PIXEL_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'DP_PIXEL_ENCODING_TYPE'
DP_PIXEL_ENCODING_TYPE__enumvalues = {
0: 'DP_PIXEL_ENCODING_UNCOMPRESSED',
1: 'DP_PIXEL_ENCODING_COMPRESSED',
}
DP_PIXEL_ENCODING_UNCOMPRESSED = 0
DP_PIXEL_ENCODING_COMPRESSED = 1
DP_PIXEL_ENCODING_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE'
DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = {
0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ',
1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED',
}
DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0
DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1
DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_ASP_PRIORITY'
DP_SEC_ASP_PRIORITY__enumvalues = {
0: 'DP_SEC_ASP_LOW_PRIORITY',
1: 'DP_SEC_ASP_HIGH_PRIORITY',
}
DP_SEC_ASP_LOW_PRIORITY = 0
DP_SEC_ASP_HIGH_PRIORITY = 1
DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_AUDIO_MUTE'
DP_SEC_AUDIO_MUTE__enumvalues = {
0: 'DP_SEC_AUDIO_MUTE_HW_CTRL',
1: 'DP_SEC_AUDIO_MUTE_SW_CTRL',
}
DP_SEC_AUDIO_MUTE_HW_CTRL = 0
DP_SEC_AUDIO_MUTE_SW_CTRL = 1
DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_COLLISION_ACK'
DP_SEC_COLLISION_ACK__enumvalues = {
0: 'DP_SEC_COLLISION_ACK_NO_EFFECT',
1: 'DP_SEC_COLLISION_ACK_CLR_FLAG',
}
DP_SEC_COLLISION_ACK_NO_EFFECT = 0
DP_SEC_COLLISION_ACK_CLR_FLAG = 1
DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_GSP0_PRIORITY'
DP_SEC_GSP0_PRIORITY__enumvalues = {
0: 'SEC_GSP0_PRIORITY_LOW',
1: 'SEC_GSP0_PRIORITY_HIGH',
}
SEC_GSP0_PRIORITY_LOW = 0
SEC_GSP0_PRIORITY_HIGH = 1
DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_GSP_SEND'
DP_SEC_GSP_SEND__enumvalues = {
0: 'NOT_SENT',
1: 'FORCE_SENT',
}
NOT_SENT = 0
FORCE_SENT = 1
DP_SEC_GSP_SEND = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_GSP_SEND_ANY_LINE'
DP_SEC_GSP_SEND_ANY_LINE__enumvalues = {
0: 'SEND_AT_LINK_NUMBER',
1: 'SEND_AT_EARLIEST_TIME',
}
SEND_AT_LINK_NUMBER = 0
SEND_AT_EARLIEST_TIME = 1
DP_SEC_GSP_SEND_ANY_LINE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_GSP_SEND_PPS'
DP_SEC_GSP_SEND_PPS__enumvalues = {
0: 'SEND_NORMAL_PACKET',
1: 'SEND_PPS_PACKET',
}
SEND_NORMAL_PACKET = 0
SEND_PPS_PACKET = 1
DP_SEC_GSP_SEND_PPS = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_LINE_REFERENCE'
DP_SEC_LINE_REFERENCE__enumvalues = {
0: 'REFER_TO_DP_SOF',
1: 'REFER_TO_OTG_SOF',
}
REFER_TO_DP_SOF = 0
REFER_TO_OTG_SOF = 1
DP_SEC_LINE_REFERENCE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_TIMESTAMP_MODE'
DP_SEC_TIMESTAMP_MODE__enumvalues = {
0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE',
1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE',
}
DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0
DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1
DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_STEER_OUTPUT_PIXEL_PER_CYCLE'
DP_STEER_OUTPUT_PIXEL_PER_CYCLE__enumvalues = {
0: 'DP_STEER_1_PIX_PER_CYCLE',
1: 'DP_STEER_2_PIX_PER_CYCLE',
2: 'DP_STEER_4_PIX_PER_CYCLE',
3: 'DP_STEER_8_PIX_PER_CYCLE',
}
DP_STEER_1_PIX_PER_CYCLE = 0
DP_STEER_2_PIX_PER_CYCLE = 1
DP_STEER_4_PIX_PER_CYCLE = 2
DP_STEER_8_PIX_PER_CYCLE = 3
DP_STEER_OUTPUT_PIXEL_PER_CYCLE = ctypes.c_uint32 # enum
# values for enumeration 'DP_STEER_OVERFLOW_ACK'
DP_STEER_OVERFLOW_ACK__enumvalues = {
0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT',
1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT',
}
DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0
DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1
DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_STEER_OVERFLOW_MASK'
DP_STEER_OVERFLOW_MASK__enumvalues = {
0: 'DP_STEER_OVERFLOW_MASKED',
1: 'DP_STEER_OVERFLOW_UNMASK',
}
DP_STEER_OVERFLOW_MASKED = 0
DP_STEER_OVERFLOW_UNMASK = 1
DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DP_SYNC_POLARITY'
DP_SYNC_POLARITY__enumvalues = {
0: 'DP_SYNC_POLARITY_ACTIVE_HIGH',
1: 'DP_SYNC_POLARITY_ACTIVE_LOW',
}
DP_SYNC_POLARITY_ACTIVE_HIGH = 0
DP_SYNC_POLARITY_ACTIVE_LOW = 1
DP_SYNC_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_TU_OVERFLOW_ACK'
DP_TU_OVERFLOW_ACK__enumvalues = {
0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT',
1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT',
}
DP_TU_OVERFLOW_ACK_NO_EFFECT = 0
DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1
DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_UDI_LANES'
DP_UDI_LANES__enumvalues = {
0: 'DP_UDI_1_LANE',
1: 'DP_UDI_2_LANES',
2: 'DP_UDI_LANES_RESERVED',
3: 'DP_UDI_4_LANES',
}
DP_UDI_1_LANE = 0
DP_UDI_2_LANES = 1
DP_UDI_LANES_RESERVED = 2
DP_UDI_4_LANES = 3
DP_UDI_LANES = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE'
DP_VID_ENHANCED_FRAME_MODE__enumvalues = {
0: 'VID_NORMAL_FRAME_MODE',
1: 'VID_ENHANCED_MODE',
}
VID_NORMAL_FRAME_MODE = 0
VID_ENHANCED_MODE = 1
DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE'
DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = {
0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE',
1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START',
}
DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0
DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1
DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_M_N_GEN_EN'
DP_VID_M_N_GEN_EN__enumvalues = {
0: 'DP_VID_M_N_PROGRAMMED_VIA_REG',
1: 'DP_VID_M_N_CALC_AUTO',
}
DP_VID_M_N_PROGRAMMED_VIA_REG = 0
DP_VID_M_N_CALC_AUTO = 1
DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_N_INTERVAL'
DP_VID_N_INTERVAL__enumvalues = {
0: 'DP_VID_1X_Nvid',
1: 'DP_VID_2X_Nvid',
2: 'DP_VID_4X_Nvid',
3: 'DP_VID_8X_Nvid',
}
DP_VID_1X_Nvid = 0
DP_VID_2X_Nvid = 1
DP_VID_4X_Nvid = 2
DP_VID_8X_Nvid = 3
DP_VID_N_INTERVAL = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_STREAM_DISABLE_ACK'
DP_VID_STREAM_DISABLE_ACK__enumvalues = {
0: 'ID_STREAM_DISABLE_NO_ACK',
1: 'ID_STREAM_DISABLE_ACKED',
}
ID_STREAM_DISABLE_NO_ACK = 0
ID_STREAM_DISABLE_ACKED = 1
DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_STREAM_DISABLE_MASK'
DP_VID_STREAM_DISABLE_MASK__enumvalues = {
0: 'VID_STREAM_DISABLE_MASKED',
1: 'VID_STREAM_DISABLE_UNMASK',
}
VID_STREAM_DISABLE_MASKED = 0
VID_STREAM_DISABLE_UNMASK = 1
DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_STREAM_DIS_DEFER'
DP_VID_STREAM_DIS_DEFER__enumvalues = {
0: 'DP_VID_STREAM_DIS_NO_DEFER',
1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK',
2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK',
}
DP_VID_STREAM_DIS_NO_DEFER = 0
DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1
DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2
DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_VBID_FIELD_POL'
DP_VID_VBID_FIELD_POL__enumvalues = {
0: 'DP_VID_VBID_FIELD_POL_NORMAL',
1: 'DP_VID_VBID_FIELD_POL_INV',
}
DP_VID_VBID_FIELD_POL_NORMAL = 0
DP_VID_VBID_FIELD_POL_INV = 1
DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum
# values for enumeration 'FEC_ACTIVE_STATUS'
FEC_ACTIVE_STATUS__enumvalues = {
0: 'DPHY_FEC_NOT_ACTIVE',
1: 'DPHY_FEC_ACTIVE',
}
DPHY_FEC_NOT_ACTIVE = 0
DPHY_FEC_ACTIVE = 1
FEC_ACTIVE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'DIG_BE_CNTL_HPD_SELECT'
DIG_BE_CNTL_HPD_SELECT__enumvalues = {
0: 'DIG_BE_CNTL_HPD1',
1: 'DIG_BE_CNTL_HPD2',
2: 'DIG_BE_CNTL_HPD3',
3: 'DIG_BE_CNTL_HPD4',
4: 'DIG_BE_CNTL_NO_HPD',
}
DIG_BE_CNTL_HPD1 = 0
DIG_BE_CNTL_HPD2 = 1
DIG_BE_CNTL_HPD3 = 2
DIG_BE_CNTL_HPD4 = 3
DIG_BE_CNTL_NO_HPD = 4
DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DIG_BE_CNTL_MODE'
DIG_BE_CNTL_MODE__enumvalues = {
0: 'DIG_BE_DP_SST_MODE',
1: 'DIG_BE_RESERVED1',
2: 'DIG_BE_TMDS_DVI_MODE',
3: 'DIG_BE_TMDS_HDMI_MODE',
4: 'DIG_BE_RESERVED4',
5: 'DIG_BE_DP_MST_MODE',
6: 'DIG_BE_RESERVED2',
7: 'DIG_BE_RESERVED3',
}
DIG_BE_DP_SST_MODE = 0
DIG_BE_RESERVED1 = 1
DIG_BE_TMDS_DVI_MODE = 2
DIG_BE_TMDS_HDMI_MODE = 3
DIG_BE_RESERVED4 = 4
DIG_BE_DP_MST_MODE = 5
DIG_BE_RESERVED2 = 6
DIG_BE_RESERVED3 = 7
DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DIG_DIGITAL_BYPASS_ENABLE'
DIG_DIGITAL_BYPASS_ENABLE__enumvalues = {
0: 'DIG_DIGITAL_BYPASS_OFF',
1: 'DIG_DIGITAL_BYPASS_ON',
}
DIG_DIGITAL_BYPASS_OFF = 0
DIG_DIGITAL_BYPASS_ON = 1
DIG_DIGITAL_BYPASS_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'DIG_DIGITAL_BYPASS_SEL'
DIG_DIGITAL_BYPASS_SEL__enumvalues = {
0: 'DIG_DIGITAL_BYPASS_SEL_BYPASS',
1: 'DIG_DIGITAL_BYPASS_SEL_36BPP',
2: 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB',
3: 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB',
4: 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB',
5: 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB',
6: 'DIG_DIGITAL_BYPASS_SEL_ALPHA',
}
DIG_DIGITAL_BYPASS_SEL_BYPASS = 0
DIG_DIGITAL_BYPASS_SEL_36BPP = 1
DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 2
DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 3
DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 4
DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 5
DIG_DIGITAL_BYPASS_SEL_ALPHA = 6
DIG_DIGITAL_BYPASS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT'
DIG_FE_CNTL_SOURCE_SELECT__enumvalues = {
0: 'DIG_FE_SOURCE_FROM_OTG0',
1: 'DIG_FE_SOURCE_FROM_OTG1',
2: 'DIG_FE_SOURCE_FROM_OTG2',
3: 'DIG_FE_SOURCE_FROM_OTG3',
4: 'DIG_FE_SOURCE_RESERVED',
}
DIG_FE_SOURCE_FROM_OTG0 = 0
DIG_FE_SOURCE_FROM_OTG1 = 1
DIG_FE_SOURCE_FROM_OTG2 = 2
DIG_FE_SOURCE_FROM_OTG3 = 3
DIG_FE_SOURCE_RESERVED = 4
DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT'
DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = {
0: 'DIG_FE_STEREOSYNC_FROM_OTG0',
1: 'DIG_FE_STEREOSYNC_FROM_OTG1',
2: 'DIG_FE_STEREOSYNC_FROM_OTG2',
3: 'DIG_FE_STEREOSYNC_FROM_OTG3',
4: 'DIG_FE_STEREOSYNC_RESERVED',
}
DIG_FE_STEREOSYNC_FROM_OTG0 = 0
DIG_FE_STEREOSYNC_FROM_OTG1 = 1
DIG_FE_STEREOSYNC_FROM_OTG2 = 2
DIG_FE_STEREOSYNC_FROM_OTG3 = 3
DIG_FE_STEREOSYNC_RESERVED = 4
DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX'
DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX__enumvalues = {
0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX',
1: 'DIG_FIFO_FORCE_RECOMP_MINMAX',
}
DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0
DIG_FIFO_FORCE_RECOMP_MINMAX = 1
DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL'
DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL__enumvalues = {
0: 'DIG_FIFO_USE_OVERWRITE_LEVEL',
1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL',
}
DIG_FIFO_USE_OVERWRITE_LEVEL = 0
DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1
DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_FORCE_RECAL_AVERAGE'
DIG_FIFO_FORCE_RECAL_AVERAGE__enumvalues = {
0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE',
1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL',
}
DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0
DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1
DIG_FIFO_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE'
DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__enumvalues = {
0: 'DIG_FIFO_1_PIX_PER_CYCLE',
1: 'DIG_FIFO_2_PIX_PER_CYCLE',
2: 'DIG_FIFO_4_PIX_PER_CYCLE',
3: 'DIG_FIFO_8_PIX_PER_CYCLE',
}
DIG_FIFO_1_PIX_PER_CYCLE = 0
DIG_FIFO_2_PIX_PER_CYCLE = 1
DIG_FIFO_4_PIX_PER_CYCLE = 2
DIG_FIFO_8_PIX_PER_CYCLE = 3
DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR'
DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR__enumvalues = {
0: 'DIG_FIFO_NO_ERROR_OCCURRED',
1: 'DIG_FIFO_UNDERFLOW_OCCURRED',
2: 'DIG_FIFO_OVERFLOW_OCCURRED',
}
DIG_FIFO_NO_ERROR_OCCURRED = 0
DIG_FIFO_UNDERFLOW_OCCURRED = 1
DIG_FIFO_OVERFLOW_OCCURRED = 2
DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC'
DIG_FIFO_READ_CLOCK_SRC__enumvalues = {
0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG',
1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE',
}
DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0
DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1
DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum
# values for enumeration 'DIG_MODE'
DIG_MODE__enumvalues = {
0: 'DP_SST_MODE',
1: 'RESERVED1',
2: 'TMDS_DVI_MODE',
3: 'TMDS_HDMI_MODE',
4: 'RESERVED4',
5: 'DP_MST_MODE',
6: 'RESERVED2',
7: 'RESERVED3',
}
DP_SST_MODE = 0
RESERVED1 = 1
TMDS_DVI_MODE = 2
TMDS_HDMI_MODE = 3
RESERVED4 = 4
DP_MST_MODE = 5
RESERVED2 = 6
RESERVED3 = 7
DIG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL'
DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = {
0: 'DIG_OUTPUT_CRC_ON_LINK0',
1: 'DIG_OUTPUT_CRC_ON_LINK1',
}
DIG_OUTPUT_CRC_ON_LINK0 = 0
DIG_OUTPUT_CRC_ON_LINK1 = 1
DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL'
DIG_OUTPUT_CRC_DATA_SEL__enumvalues = {
0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME',
1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY',
2: 'DIG_OUTPUT_CRC_FOR_VBI',
3: 'DIG_OUTPUT_CRC_FOR_AUDIO',
}
DIG_OUTPUT_CRC_FOR_FULLFRAME = 0
DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1
DIG_OUTPUT_CRC_FOR_VBI = 2
DIG_OUTPUT_CRC_FOR_AUDIO = 3
DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT'
DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = {
0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS',
1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH',
}
DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0
DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1
DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN'
DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = {
0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE',
1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG',
}
DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0
DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1
DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL'
DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = {
0: 'DIG_10BIT_TEST_PATTERN',
1: 'DIG_ALTERNATING_TEST_PATTERN',
}
DIG_10BIT_TEST_PATTERN = 0
DIG_ALTERNATING_TEST_PATTERN = 1
DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN'
DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = {
0: 'DIG_TEST_PATTERN_NORMAL',
1: 'DIG_TEST_PATTERN_RANDOM',
}
DIG_TEST_PATTERN_NORMAL = 0
DIG_TEST_PATTERN_RANDOM = 1
DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET'
DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = {
0: 'DIG_RANDOM_PATTERN_ENABLED',
1: 'DIG_RANDOM_PATTERN_RESETED',
}
DIG_RANDOM_PATTERN_ENABLED = 0
DIG_RANDOM_PATTERN_RESETED = 1
DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN'
DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = {
0: 'DIG_IN_NORMAL_OPERATION',
1: 'DIG_IN_DEBUG_MODE',
}
DIG_IN_NORMAL_OPERATION = 0
DIG_IN_DEBUG_MODE = 1
DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACP_SEND'
HDMI_ACP_SEND__enumvalues = {
0: 'HDMI_ACP_NOT_SEND',
1: 'HDMI_ACP_PKT_SEND',
}
HDMI_ACP_NOT_SEND = 0
HDMI_ACP_PKT_SEND = 1
HDMI_ACP_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY'
HDMI_ACR_AUDIO_PRIORITY__enumvalues = {
0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE',
1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT',
}
HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0
HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1
HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_CONT'
HDMI_ACR_CONT__enumvalues = {
0: 'HDMI_ACR_CONT_DISABLE',
1: 'HDMI_ACR_CONT_ENABLE',
}
HDMI_ACR_CONT_DISABLE = 0
HDMI_ACR_CONT_ENABLE = 1
HDMI_ACR_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_N_MULTIPLE'
HDMI_ACR_N_MULTIPLE__enumvalues = {
0: 'HDMI_ACR_0_MULTIPLE_RESERVED',
1: 'HDMI_ACR_1_MULTIPLE',
2: 'HDMI_ACR_2_MULTIPLE',
3: 'HDMI_ACR_3_MULTIPLE_RESERVED',
4: 'HDMI_ACR_4_MULTIPLE',
5: 'HDMI_ACR_5_MULTIPLE_RESERVED',
6: 'HDMI_ACR_6_MULTIPLE_RESERVED',
7: 'HDMI_ACR_7_MULTIPLE_RESERVED',
}
HDMI_ACR_0_MULTIPLE_RESERVED = 0
HDMI_ACR_1_MULTIPLE = 1
HDMI_ACR_2_MULTIPLE = 2
HDMI_ACR_3_MULTIPLE_RESERVED = 3
HDMI_ACR_4_MULTIPLE = 4
HDMI_ACR_5_MULTIPLE_RESERVED = 5
HDMI_ACR_6_MULTIPLE_RESERVED = 6
HDMI_ACR_7_MULTIPLE_RESERVED = 7
HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_SELECT'
HDMI_ACR_SELECT__enumvalues = {
0: 'HDMI_ACR_SELECT_HW',
1: 'HDMI_ACR_SELECT_32K',
2: 'HDMI_ACR_SELECT_44K',
3: 'HDMI_ACR_SELECT_48K',
}
HDMI_ACR_SELECT_HW = 0
HDMI_ACR_SELECT_32K = 1
HDMI_ACR_SELECT_44K = 2
HDMI_ACR_SELECT_48K = 3
HDMI_ACR_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_SEND'
HDMI_ACR_SEND__enumvalues = {
0: 'HDMI_ACR_NOT_SEND',
1: 'HDMI_ACR_PKT_SEND',
}
HDMI_ACR_NOT_SEND = 0
HDMI_ACR_PKT_SEND = 1
HDMI_ACR_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_SOURCE'
HDMI_ACR_SOURCE__enumvalues = {
0: 'HDMI_ACR_SOURCE_HW',
1: 'HDMI_ACR_SOURCE_SW',
}
HDMI_ACR_SOURCE_HW = 0
HDMI_ACR_SOURCE_SW = 1
HDMI_ACR_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_AUDIO_DELAY_EN'
HDMI_AUDIO_DELAY_EN__enumvalues = {
0: 'HDMI_AUDIO_DELAY_DISABLE',
1: 'HDMI_AUDIO_DELAY_58CLK',
2: 'HDMI_AUDIO_DELAY_56CLK',
3: 'HDMI_AUDIO_DELAY_RESERVED',
}
HDMI_AUDIO_DELAY_DISABLE = 0
HDMI_AUDIO_DELAY_58CLK = 1
HDMI_AUDIO_DELAY_56CLK = 2
HDMI_AUDIO_DELAY_RESERVED = 3
HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_AUDIO_INFO_CONT'
HDMI_AUDIO_INFO_CONT__enumvalues = {
0: 'HDMI_AUDIO_INFO_CONT_DISABLE',
1: 'HDMI_AUDIO_INFO_CONT_ENABLE',
}
HDMI_AUDIO_INFO_CONT_DISABLE = 0
HDMI_AUDIO_INFO_CONT_ENABLE = 1
HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_AUDIO_INFO_SEND'
HDMI_AUDIO_INFO_SEND__enumvalues = {
0: 'HDMI_AUDIO_INFO_NOT_SEND',
1: 'HDMI_AUDIO_INFO_PKT_SEND',
}
HDMI_AUDIO_INFO_NOT_SEND = 0
HDMI_AUDIO_INFO_PKT_SEND = 1
HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE'
HDMI_CLOCK_CHANNEL_RATE__enumvalues = {
0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE',
1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE',
}
HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0
HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1
HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_DATA_SCRAMBLE_EN'
HDMI_DATA_SCRAMBLE_EN__enumvalues = {
0: 'HDMI_DATA_SCRAMBLE_DISABLE',
1: 'HDMI_DATA_SCRAMBLE_ENABLE',
}
HDMI_DATA_SCRAMBLE_DISABLE = 0
HDMI_DATA_SCRAMBLE_ENABLE = 1
HDMI_DATA_SCRAMBLE_EN = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_DEEP_COLOR_DEPTH'
HDMI_DEEP_COLOR_DEPTH__enumvalues = {
0: 'HDMI_DEEP_COLOR_DEPTH_24BPP',
1: 'HDMI_DEEP_COLOR_DEPTH_30BPP',
2: 'HDMI_DEEP_COLOR_DEPTH_36BPP',
3: 'HDMI_DEEP_COLOR_DEPTH_48BPP',
}
HDMI_DEEP_COLOR_DEPTH_24BPP = 0
HDMI_DEEP_COLOR_DEPTH_30BPP = 1
HDMI_DEEP_COLOR_DEPTH_36BPP = 2
HDMI_DEEP_COLOR_DEPTH_48BPP = 3
HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_DEFAULT_PAHSE'
HDMI_DEFAULT_PAHSE__enumvalues = {
0: 'HDMI_DEFAULT_PHASE_IS_0',
1: 'HDMI_DEFAULT_PHASE_IS_1',
}
HDMI_DEFAULT_PHASE_IS_0 = 0
HDMI_DEFAULT_PHASE_IS_1 = 1
HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ERROR_ACK'
HDMI_ERROR_ACK__enumvalues = {
0: 'HDMI_ERROR_ACK_INT',
1: 'HDMI_ERROR_NOT_ACK',
}
HDMI_ERROR_ACK_INT = 0
HDMI_ERROR_NOT_ACK = 1
HDMI_ERROR_ACK = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ERROR_MASK'
HDMI_ERROR_MASK__enumvalues = {
0: 'HDMI_ERROR_MASK_INT',
1: 'HDMI_ERROR_NOT_MASK',
}
HDMI_ERROR_MASK_INT = 0
HDMI_ERROR_NOT_MASK = 1
HDMI_ERROR_MASK = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GC_AVMUTE'
HDMI_GC_AVMUTE__enumvalues = {
0: 'HDMI_GC_AVMUTE_SET',
1: 'HDMI_GC_AVMUTE_UNSET',
}
HDMI_GC_AVMUTE_SET = 0
HDMI_GC_AVMUTE_UNSET = 1
HDMI_GC_AVMUTE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GC_AVMUTE_CONT'
HDMI_GC_AVMUTE_CONT__enumvalues = {
0: 'HDMI_GC_AVMUTE_CONT_DISABLE',
1: 'HDMI_GC_AVMUTE_CONT_ENABLE',
}
HDMI_GC_AVMUTE_CONT_DISABLE = 0
HDMI_GC_AVMUTE_CONT_ENABLE = 1
HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GC_CONT'
HDMI_GC_CONT__enumvalues = {
0: 'HDMI_GC_CONT_DISABLE',
1: 'HDMI_GC_CONT_ENABLE',
}
HDMI_GC_CONT_DISABLE = 0
HDMI_GC_CONT_ENABLE = 1
HDMI_GC_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GC_SEND'
HDMI_GC_SEND__enumvalues = {
0: 'HDMI_GC_NOT_SEND',
1: 'HDMI_GC_PKT_SEND',
}
HDMI_GC_NOT_SEND = 0
HDMI_GC_PKT_SEND = 1
HDMI_GC_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GENERIC_CONT'
HDMI_GENERIC_CONT__enumvalues = {
0: 'HDMI_GENERIC_CONT_DISABLE',
1: 'HDMI_GENERIC_CONT_ENABLE',
}
HDMI_GENERIC_CONT_DISABLE = 0
HDMI_GENERIC_CONT_ENABLE = 1
HDMI_GENERIC_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GENERIC_SEND'
HDMI_GENERIC_SEND__enumvalues = {
0: 'HDMI_GENERIC_NOT_SEND',
1: 'HDMI_GENERIC_PKT_SEND',
}
HDMI_GENERIC_NOT_SEND = 0
HDMI_GENERIC_PKT_SEND = 1
HDMI_GENERIC_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ISRC_CONT'
HDMI_ISRC_CONT__enumvalues = {
0: 'HDMI_ISRC_CONT_DISABLE',
1: 'HDMI_ISRC_CONT_ENABLE',
}
HDMI_ISRC_CONT_DISABLE = 0
HDMI_ISRC_CONT_ENABLE = 1
HDMI_ISRC_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ISRC_SEND'
HDMI_ISRC_SEND__enumvalues = {
0: 'HDMI_ISRC_NOT_SEND',
1: 'HDMI_ISRC_PKT_SEND',
}
HDMI_ISRC_NOT_SEND = 0
HDMI_ISRC_PKT_SEND = 1
HDMI_ISRC_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_KEEPOUT_MODE'
HDMI_KEEPOUT_MODE__enumvalues = {
0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC',
1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC',
}
HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0
HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1
HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_METADATA_ENABLE'
HDMI_METADATA_ENABLE__enumvalues = {
0: 'HDMI_METADATA_NOT_SEND',
1: 'HDMI_METADATA_PKT_SEND',
}
HDMI_METADATA_NOT_SEND = 0
HDMI_METADATA_PKT_SEND = 1
HDMI_METADATA_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_MPEG_INFO_CONT'
HDMI_MPEG_INFO_CONT__enumvalues = {
0: 'HDMI_MPEG_INFO_CONT_DISABLE',
1: 'HDMI_MPEG_INFO_CONT_ENABLE',
}
HDMI_MPEG_INFO_CONT_DISABLE = 0
HDMI_MPEG_INFO_CONT_ENABLE = 1
HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_MPEG_INFO_SEND'
HDMI_MPEG_INFO_SEND__enumvalues = {
0: 'HDMI_MPEG_INFO_NOT_SEND',
1: 'HDMI_MPEG_INFO_PKT_SEND',
}
HDMI_MPEG_INFO_NOT_SEND = 0
HDMI_MPEG_INFO_PKT_SEND = 1
HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED'
HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = {
0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE',
1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE',
}
HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0
HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1
HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_NULL_SEND'
HDMI_NULL_SEND__enumvalues = {
0: 'HDMI_NULL_NOT_SEND',
1: 'HDMI_NULL_PKT_SEND',
}
HDMI_NULL_NOT_SEND = 0
HDMI_NULL_PKT_SEND = 1
HDMI_NULL_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_PACKET_GEN_VERSION'
HDMI_PACKET_GEN_VERSION__enumvalues = {
0: 'HDMI_PACKET_GEN_VERSION_OLD',
1: 'HDMI_PACKET_GEN_VERSION_NEW',
}
HDMI_PACKET_GEN_VERSION_OLD = 0
HDMI_PACKET_GEN_VERSION_NEW = 1
HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_PACKET_LINE_REFERENCE'
HDMI_PACKET_LINE_REFERENCE__enumvalues = {
0: 'HDMI_PKT_LINE_REF_VSYNC',
1: 'HDMI_PKT_LINE_REF_OTGSOF',
}
HDMI_PKT_LINE_REF_VSYNC = 0
HDMI_PKT_LINE_REF_OTGSOF = 1
HDMI_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE'
HDMI_PACKING_PHASE_OVERRIDE__enumvalues = {
0: 'HDMI_PACKING_PHASE_SET_BY_HW',
1: 'HDMI_PACKING_PHASE_SET_BY_SW',
}
HDMI_PACKING_PHASE_SET_BY_HW = 0
HDMI_PACKING_PHASE_SET_BY_SW = 1
HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT'
LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = {
0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS',
1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH',
}
LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0
LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1
LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_COLOR_FORMAT'
TMDS_COLOR_FORMAT__enumvalues = {
0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP',
1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB',
2: 'TMDS_COLOR_FORMAT_DUAL30BPP',
3: 'TMDS_COLOR_FORMAT_RESERVED',
}
TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0
TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1
TMDS_COLOR_FORMAT_DUAL30BPP = 2
TMDS_COLOR_FORMAT_RESERVED = 3
TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL0_DATA_INVERT'
TMDS_CTL0_DATA_INVERT__enumvalues = {
0: 'TMDS_CTL0_DATA_NORMAL',
1: 'TMDS_CTL0_DATA_INVERT_EN',
}
TMDS_CTL0_DATA_NORMAL = 0
TMDS_CTL0_DATA_INVERT_EN = 1
TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL0_DATA_MODULATION'
TMDS_CTL0_DATA_MODULATION__enumvalues = {
0: 'TMDS_CTL0_DATA_MODULATION_DISABLE',
1: 'TMDS_CTL0_DATA_MODULATION_BIT0',
2: 'TMDS_CTL0_DATA_MODULATION_BIT1',
3: 'TMDS_CTL0_DATA_MODULATION_BIT2',
}
TMDS_CTL0_DATA_MODULATION_DISABLE = 0
TMDS_CTL0_DATA_MODULATION_BIT0 = 1
TMDS_CTL0_DATA_MODULATION_BIT1 = 2
TMDS_CTL0_DATA_MODULATION_BIT2 = 3
TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL0_DATA_SEL'
TMDS_CTL0_DATA_SEL__enumvalues = {
0: 'TMDS_CTL0_DATA_SEL0_RESERVED',
1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE',
2: 'TMDS_CTL0_DATA_SEL2_VSYNC',
3: 'TMDS_CTL0_DATA_SEL3_RESERVED',
4: 'TMDS_CTL0_DATA_SEL4_HSYNC',
5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED',
6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA',
7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA',
}
TMDS_CTL0_DATA_SEL0_RESERVED = 0
TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1
TMDS_CTL0_DATA_SEL2_VSYNC = 2
TMDS_CTL0_DATA_SEL3_RESERVED = 3
TMDS_CTL0_DATA_SEL4_HSYNC = 4
TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5
TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6
TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7
TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN'
TMDS_CTL0_PATTERN_OUT_EN__enumvalues = {
0: 'TMDS_CTL0_PATTERN_OUT_DISABLE',
1: 'TMDS_CTL0_PATTERN_OUT_ENABLE',
}
TMDS_CTL0_PATTERN_OUT_DISABLE = 0
TMDS_CTL0_PATTERN_OUT_ENABLE = 1
TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL1_DATA_INVERT'
TMDS_CTL1_DATA_INVERT__enumvalues = {
0: 'TMDS_CTL1_DATA_NORMAL',
1: 'TMDS_CTL1_DATA_INVERT_EN',
}
TMDS_CTL1_DATA_NORMAL = 0
TMDS_CTL1_DATA_INVERT_EN = 1
TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL1_DATA_MODULATION'
TMDS_CTL1_DATA_MODULATION__enumvalues = {
0: 'TMDS_CTL1_DATA_MODULATION_DISABLE',
1: 'TMDS_CTL1_DATA_MODULATION_BIT0',
2: 'TMDS_CTL1_DATA_MODULATION_BIT1',
3: 'TMDS_CTL1_DATA_MODULATION_BIT2',
}
TMDS_CTL1_DATA_MODULATION_DISABLE = 0
TMDS_CTL1_DATA_MODULATION_BIT0 = 1
TMDS_CTL1_DATA_MODULATION_BIT1 = 2
TMDS_CTL1_DATA_MODULATION_BIT2 = 3
TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL1_DATA_SEL'
TMDS_CTL1_DATA_SEL__enumvalues = {
0: 'TMDS_CTL1_DATA_SEL0_RESERVED',
1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE',
2: 'TMDS_CTL1_DATA_SEL2_VSYNC',
3: 'TMDS_CTL1_DATA_SEL3_RESERVED',
4: 'TMDS_CTL1_DATA_SEL4_HSYNC',
5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED',
6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME',
7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED',
}
TMDS_CTL1_DATA_SEL0_RESERVED = 0
TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1
TMDS_CTL1_DATA_SEL2_VSYNC = 2
TMDS_CTL1_DATA_SEL3_RESERVED = 3
TMDS_CTL1_DATA_SEL4_HSYNC = 4
TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5
TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6
TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7
TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN'
TMDS_CTL1_PATTERN_OUT_EN__enumvalues = {
0: 'TMDS_CTL1_PATTERN_OUT_DISABLE',
1: 'TMDS_CTL1_PATTERN_OUT_ENABLE',
}
TMDS_CTL1_PATTERN_OUT_DISABLE = 0
TMDS_CTL1_PATTERN_OUT_ENABLE = 1
TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL2_DATA_INVERT'
TMDS_CTL2_DATA_INVERT__enumvalues = {
0: 'TMDS_CTL2_DATA_NORMAL',
1: 'TMDS_CTL2_DATA_INVERT_EN',
}
TMDS_CTL2_DATA_NORMAL = 0
TMDS_CTL2_DATA_INVERT_EN = 1
TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL2_DATA_MODULATION'
TMDS_CTL2_DATA_MODULATION__enumvalues = {
0: 'TMDS_CTL2_DATA_MODULATION_DISABLE',
1: 'TMDS_CTL2_DATA_MODULATION_BIT0',
2: 'TMDS_CTL2_DATA_MODULATION_BIT1',
3: 'TMDS_CTL2_DATA_MODULATION_BIT2',
}
TMDS_CTL2_DATA_MODULATION_DISABLE = 0
TMDS_CTL2_DATA_MODULATION_BIT0 = 1
TMDS_CTL2_DATA_MODULATION_BIT1 = 2
TMDS_CTL2_DATA_MODULATION_BIT2 = 3
TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL2_DATA_SEL'
TMDS_CTL2_DATA_SEL__enumvalues = {
0: 'TMDS_CTL2_DATA_SEL0_RESERVED',
1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE',
2: 'TMDS_CTL2_DATA_SEL2_VSYNC',
3: 'TMDS_CTL2_DATA_SEL3_RESERVED',
4: 'TMDS_CTL2_DATA_SEL4_HSYNC',
5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED',
6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME',
7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED',
}
TMDS_CTL2_DATA_SEL0_RESERVED = 0
TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1
TMDS_CTL2_DATA_SEL2_VSYNC = 2
TMDS_CTL2_DATA_SEL3_RESERVED = 3
TMDS_CTL2_DATA_SEL4_HSYNC = 4
TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5
TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6
TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7
TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN'
TMDS_CTL2_PATTERN_OUT_EN__enumvalues = {
0: 'TMDS_CTL2_PATTERN_OUT_DISABLE',
1: 'TMDS_CTL2_PATTERN_OUT_ENABLE',
}
TMDS_CTL2_PATTERN_OUT_DISABLE = 0
TMDS_CTL2_PATTERN_OUT_ENABLE = 1
TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL3_DATA_INVERT'
TMDS_CTL3_DATA_INVERT__enumvalues = {
0: 'TMDS_CTL3_DATA_NORMAL',
1: 'TMDS_CTL3_DATA_INVERT_EN',
}
TMDS_CTL3_DATA_NORMAL = 0
TMDS_CTL3_DATA_INVERT_EN = 1
TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL3_DATA_MODULATION'
TMDS_CTL3_DATA_MODULATION__enumvalues = {
0: 'TMDS_CTL3_DATA_MODULATION_DISABLE',
1: 'TMDS_CTL3_DATA_MODULATION_BIT0',
2: 'TMDS_CTL3_DATA_MODULATION_BIT1',
3: 'TMDS_CTL3_DATA_MODULATION_BIT2',
}
TMDS_CTL3_DATA_MODULATION_DISABLE = 0
TMDS_CTL3_DATA_MODULATION_BIT0 = 1
TMDS_CTL3_DATA_MODULATION_BIT1 = 2
TMDS_CTL3_DATA_MODULATION_BIT2 = 3
TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL3_DATA_SEL'
TMDS_CTL3_DATA_SEL__enumvalues = {
0: 'TMDS_CTL3_DATA_SEL0_RESERVED',
1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE',
2: 'TMDS_CTL3_DATA_SEL2_VSYNC',
3: 'TMDS_CTL3_DATA_SEL3_RESERVED',
4: 'TMDS_CTL3_DATA_SEL4_HSYNC',
5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED',
6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME',
7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED',
}
TMDS_CTL3_DATA_SEL0_RESERVED = 0
TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1
TMDS_CTL3_DATA_SEL2_VSYNC = 2
TMDS_CTL3_DATA_SEL3_RESERVED = 3
TMDS_CTL3_DATA_SEL4_HSYNC = 4
TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5
TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6
TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7
TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN'
TMDS_CTL3_PATTERN_OUT_EN__enumvalues = {
0: 'TMDS_CTL3_PATTERN_OUT_DISABLE',
1: 'TMDS_CTL3_PATTERN_OUT_ENABLE',
}
TMDS_CTL3_PATTERN_OUT_DISABLE = 0
TMDS_CTL3_PATTERN_OUT_ENABLE = 1
TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL'
TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = {
0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS',
1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL',
}
TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0
TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1
TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_PIXEL_ENCODING'
TMDS_PIXEL_ENCODING__enumvalues = {
0: 'TMDS_PIXEL_ENCODING_444_OR_420',
1: 'TMDS_PIXEL_ENCODING_422',
}
TMDS_PIXEL_ENCODING_444_OR_420 = 0
TMDS_PIXEL_ENCODING_422 = 1
TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA'
TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = {
0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0',
1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1',
2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2',
3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA',
}
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2
TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3
TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB'
TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = {
0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0',
1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1',
2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2',
3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA',
}
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2
TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3
TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG'
TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = {
0: 'TMDS_STEREOSYNC_CTL0',
1: 'TMDS_STEREOSYNC_CTL1',
2: 'TMDS_STEREOSYNC_CTL2',
3: 'TMDS_STEREOSYNC_CTL3',
}
TMDS_STEREOSYNC_CTL0 = 0
TMDS_STEREOSYNC_CTL1 = 1
TMDS_STEREOSYNC_CTL2 = 2
TMDS_STEREOSYNC_CTL3 = 3
TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_SYNC_PHASE'
TMDS_SYNC_PHASE__enumvalues = {
0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START',
1: 'TMDS_SYNC_PHASE_ON_FRAME_START',
}
TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0
TMDS_SYNC_PHASE_ON_FRAME_START = 1
TMDS_SYNC_PHASE = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA'
TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = {
0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT',
1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT',
}
TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0
TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1
TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB'
TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = {
0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT',
1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT',
}
TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0
TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1
TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA'
TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = {
0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK',
1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK',
}
TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0
TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1
TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB'
TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = {
0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK',
1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK',
}
TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0
TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1
TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN'
TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = {
0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW',
1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW',
}
TMDS_TRANSMITTER_PLLSEL_BY_HW = 0
TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1
TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK'
TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE',
1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON',
2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON',
3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE',
}
TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3
TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN'
TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = {
0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE',
1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE',
}
TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0
TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1
TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK'
TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD',
1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD',
}
TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0
TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1
TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS'
TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = {
0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK',
1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS',
}
TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0
TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1
TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS'
TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = {
0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK',
1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS',
}
TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0
TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1
TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK'
TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE',
1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE',
}
TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0
TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1
TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK'
TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE',
1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE',
}
TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0
TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1
TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK'
TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE',
1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE',
}
TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0
TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1
TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ACK'
DOUT_I2C_ACK__enumvalues = {
0: 'DOUT_I2C_NO_ACK',
1: 'DOUT_I2C_ACK_TO_CLEAN',
}
DOUT_I2C_NO_ACK = 0
DOUT_I2C_ACK_TO_CLEAN = 1
DOUT_I2C_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER'
DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = {
0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER',
1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER',
}
DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0
DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1
DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG'
DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = {
0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG',
1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG',
}
DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0
DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1
DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO'
DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = {
0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED',
1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED',
}
DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0
DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1
DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY'
DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = {
0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL',
1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH',
2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED',
3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED',
}
DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0
DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1
DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2
DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3
DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ'
DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = {
0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ',
1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ',
}
DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0
DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1
DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_DBG_REF_SEL'
DOUT_I2C_CONTROL_DBG_REF_SEL__enumvalues = {
0: 'DOUT_I2C_CONTROL_NORMAL_DEBUG',
1: 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG',
}
DOUT_I2C_CONTROL_NORMAL_DEBUG = 0
DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 1
DOUT_I2C_CONTROL_DBG_REF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT'
DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = {
0: 'DOUT_I2C_CONTROL_SELECT_DDC1',
1: 'DOUT_I2C_CONTROL_SELECT_DDC2',
2: 'DOUT_I2C_CONTROL_SELECT_DDC3',
3: 'DOUT_I2C_CONTROL_SELECT_DDC4',
4: 'DOUT_I2C_CONTROL_SELECT_DDCVGA',
}
DOUT_I2C_CONTROL_SELECT_DDC1 = 0
DOUT_I2C_CONTROL_SELECT_DDC2 = 1
DOUT_I2C_CONTROL_SELECT_DDC3 = 2
DOUT_I2C_CONTROL_SELECT_DDC4 = 3
DOUT_I2C_CONTROL_SELECT_DDCVGA = 4
DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_GO'
DOUT_I2C_CONTROL_GO__enumvalues = {
0: 'DOUT_I2C_CONTROL_STOP_TRANSFER',
1: 'DOUT_I2C_CONTROL_START_TRANSFER',
}
DOUT_I2C_CONTROL_STOP_TRANSFER = 0
DOUT_I2C_CONTROL_START_TRANSFER = 1
DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET'
DOUT_I2C_CONTROL_SEND_RESET__enumvalues = {
0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET',
1: 'DOUT_I2C_CONTROL__SEND_RESET',
}
DOUT_I2C_CONTROL__NOT_SEND_RESET = 0
DOUT_I2C_CONTROL__SEND_RESET = 1
DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH'
DOUT_I2C_CONTROL_SEND_RESET_LENGTH__enumvalues = {
0: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9',
1: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10',
}
DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0
DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 1
DOUT_I2C_CONTROL_SEND_RESET_LENGTH = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET'
DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = {
0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER',
1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER',
}
DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0
DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1
DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET'
DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = {
0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS',
1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS',
}
DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0
DOUT_I2C_CONTROL_RESET_SW_STATUS = 1
DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT'
DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = {
0: 'DOUT_I2C_CONTROL_TRANS0',
1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1',
2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2',
3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3',
}
DOUT_I2C_CONTROL_TRANS0 = 0
DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1
DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2
DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3
DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE'
DOUT_I2C_DATA_INDEX_WRITE__enumvalues = {
0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE',
1: 'DOUT_I2C_DATA__INDEX_WRITE',
}
DOUT_I2C_DATA__NOT_INDEX_WRITE = 0
DOUT_I2C_DATA__INDEX_WRITE = 1
DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN'
DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = {
0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR',
1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL',
}
DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0
DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1
DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN'
DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = {
0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR',
1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA',
}
DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0
DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1
DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL'
DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = {
0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS',
1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS',
}
DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0
DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1
DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE'
DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = {
0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT',
1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT',
}
DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0
DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1
DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD'
DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = {
0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO',
1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE',
2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE',
3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE',
}
DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0
DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1
DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2
DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3
DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET'
DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = {
0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION',
1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION',
}
DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0
DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1
DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE'
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = {
0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL',
1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE',
}
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK'
DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = {
0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS',
1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS',
}
DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0
DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1
DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum
# values for enumeration 'CLOCK_GATING_EN'
CLOCK_GATING_EN__enumvalues = {
0: 'CLOCK_GATING_ENABLE',
1: 'CLOCK_GATING_DISABLE',
}
CLOCK_GATING_ENABLE = 0
CLOCK_GATING_DISABLE = 1
CLOCK_GATING_EN = ctypes.c_uint32 # enum
# values for enumeration 'DAC_MUX_SELECT'
DAC_MUX_SELECT__enumvalues = {
0: 'DAC_MUX_SELECT_DACA',
1: 'DAC_MUX_SELECT_DACB',
}
DAC_MUX_SELECT_DACA = 0
DAC_MUX_SELECT_DACB = 1
DAC_MUX_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_DIS_CTRL'
DIOMEM_PWR_DIS_CTRL__enumvalues = {
0: 'DIOMEM_ENABLE_MEM_PWR_CTRL',
1: 'DIOMEM_DISABLE_MEM_PWR_CTRL',
}
DIOMEM_ENABLE_MEM_PWR_CTRL = 0
DIOMEM_DISABLE_MEM_PWR_CTRL = 1
DIOMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_FORCE_CTRL'
DIOMEM_PWR_FORCE_CTRL__enumvalues = {
0: 'DIOMEM_NO_FORCE_REQUEST',
1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST',
3: 'DIOMEM_FORCE_SHUT_DOWN_REQUEST',
}
DIOMEM_NO_FORCE_REQUEST = 0
DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 1
DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 2
DIOMEM_FORCE_SHUT_DOWN_REQUEST = 3
DIOMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_FORCE_CTRL2'
DIOMEM_PWR_FORCE_CTRL2__enumvalues = {
0: 'DIOMEM_NO_FORCE_REQ',
1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQ',
}
DIOMEM_NO_FORCE_REQ = 0
DIOMEM_FORCE_LIGHT_SLEEP_REQ = 1
DIOMEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_SEL_CTRL'
DIOMEM_PWR_SEL_CTRL__enumvalues = {
0: 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE',
1: 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE',
2: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE',
}
DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0
DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 1
DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 2
DIOMEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_SEL_CTRL2'
DIOMEM_PWR_SEL_CTRL2__enumvalues = {
0: 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN',
1: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN',
}
DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0
DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 1
DIOMEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum
# values for enumeration 'DIO_CLOCK_GATING_DISABLE'
DIO_CLOCK_GATING_DISABLE__enumvalues = {
0: 'DIO_CLOCK_GATING_EN',
1: 'DIO_CLOCK_GATING_DIS',
}
DIO_CLOCK_GATING_EN = 0
DIO_CLOCK_GATING_DIS = 1
DIO_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'DIO_DBG_BLOCK_SEL'
DIO_DBG_BLOCK_SEL__enumvalues = {
0: 'DIO_DBG_BLOCK_SEL_DIO',
11: 'DIO_DBG_BLOCK_SEL_DIGFE_A',
12: 'DIO_DBG_BLOCK_SEL_DIGFE_B',
13: 'DIO_DBG_BLOCK_SEL_DIGFE_C',
14: 'DIO_DBG_BLOCK_SEL_DIGFE_D',
18: 'DIO_DBG_BLOCK_SEL_DIGA',
19: 'DIO_DBG_BLOCK_SEL_DIGB',
20: 'DIO_DBG_BLOCK_SEL_DIGC',
21: 'DIO_DBG_BLOCK_SEL_DIGD',
25: 'DIO_DBG_BLOCK_SEL_DPFE_A',
26: 'DIO_DBG_BLOCK_SEL_DPFE_B',
27: 'DIO_DBG_BLOCK_SEL_DPFE_C',
28: 'DIO_DBG_BLOCK_SEL_DPFE_D',
32: 'DIO_DBG_BLOCK_SEL_DPA',
33: 'DIO_DBG_BLOCK_SEL_DPB',
34: 'DIO_DBG_BLOCK_SEL_DPC',
35: 'DIO_DBG_BLOCK_SEL_DPD',
39: 'DIO_DBG_BLOCK_SEL_AUX0',
40: 'DIO_DBG_BLOCK_SEL_AUX1',
41: 'DIO_DBG_BLOCK_SEL_AUX2',
42: 'DIO_DBG_BLOCK_SEL_AUX3',
45: 'DIO_DBG_BLOCK_SEL_PERFMON_DIO',
46: 'DIO_DBG_BLOCK_SEL_RESERVED',
}
DIO_DBG_BLOCK_SEL_DIO = 0
DIO_DBG_BLOCK_SEL_DIGFE_A = 11
DIO_DBG_BLOCK_SEL_DIGFE_B = 12
DIO_DBG_BLOCK_SEL_DIGFE_C = 13
DIO_DBG_BLOCK_SEL_DIGFE_D = 14
DIO_DBG_BLOCK_SEL_DIGA = 18
DIO_DBG_BLOCK_SEL_DIGB = 19
DIO_DBG_BLOCK_SEL_DIGC = 20
DIO_DBG_BLOCK_SEL_DIGD = 21
DIO_DBG_BLOCK_SEL_DPFE_A = 25
DIO_DBG_BLOCK_SEL_DPFE_B = 26
DIO_DBG_BLOCK_SEL_DPFE_C = 27
DIO_DBG_BLOCK_SEL_DPFE_D = 28
DIO_DBG_BLOCK_SEL_DPA = 32
DIO_DBG_BLOCK_SEL_DPB = 33
DIO_DBG_BLOCK_SEL_DPC = 34
DIO_DBG_BLOCK_SEL_DPD = 35
DIO_DBG_BLOCK_SEL_AUX0 = 39
DIO_DBG_BLOCK_SEL_AUX1 = 40
DIO_DBG_BLOCK_SEL_AUX2 = 41
DIO_DBG_BLOCK_SEL_AUX3 = 42
DIO_DBG_BLOCK_SEL_PERFMON_DIO = 45
DIO_DBG_BLOCK_SEL_RESERVED = 46
DIO_DBG_BLOCK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE'
DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = {
0: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL',
1: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE',
}
DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0
DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1
DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DIO_DCN_ACTIVE_STATUS'
ENUM_DIO_DCN_ACTIVE_STATUS__enumvalues = {
0: 'ENUM_DCN_NOT_ACTIVE',
1: 'ENUM_DCN_ACTIVE',
}
ENUM_DCN_NOT_ACTIVE = 0
ENUM_DCN_ACTIVE = 1
ENUM_DIO_DCN_ACTIVE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_STEREOSYNC_SEL'
GENERIC_STEREOSYNC_SEL__enumvalues = {
0: 'GENERIC_STEREOSYNC_SEL_D1',
1: 'GENERIC_STEREOSYNC_SEL_D2',
2: 'GENERIC_STEREOSYNC_SEL_D3',
3: 'GENERIC_STEREOSYNC_SEL_D4',
4: 'GENERIC_STEREOSYNC_SEL_RESERVED',
}
GENERIC_STEREOSYNC_SEL_D1 = 0
GENERIC_STEREOSYNC_SEL_D2 = 1
GENERIC_STEREOSYNC_SEL_D3 = 2
GENERIC_STEREOSYNC_SEL_D4 = 3
GENERIC_STEREOSYNC_SEL_RESERVED = 4
GENERIC_STEREOSYNC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PM_ASSERT_RESET'
PM_ASSERT_RESET__enumvalues = {
0: 'PM_ASSERT_RESET_0',
1: 'PM_ASSERT_RESET_1',
}
PM_ASSERT_RESET_0 = 0
PM_ASSERT_RESET_1 = 1
PM_ASSERT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'SOFT_RESET'
SOFT_RESET__enumvalues = {
0: 'SOFT_RESET_0',
1: 'SOFT_RESET_1',
}
SOFT_RESET_0 = 0
SOFT_RESET_1 = 1
SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_MUX_SELECT'
TMDS_MUX_SELECT__enumvalues = {
0: 'TMDS_MUX_SELECT_B',
1: 'TMDS_MUX_SELECT_G',
2: 'TMDS_MUX_SELECT_R',
3: 'TMDS_MUX_SELECT_RESERVED',
}
TMDS_MUX_SELECT_B = 0
TMDS_MUX_SELECT_G = 1
TMDS_MUX_SELECT_R = 2
TMDS_MUX_SELECT_RESERVED = 3
TMDS_MUX_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET'
DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET__enumvalues = {
0: 'DIG_STREAM_MAPPER_LINK0',
1: 'DIG_STREAM_MAPPER_LINK1',
2: 'DIG_STREAM_MAPPER_LINK2',
3: 'DIG_STREAM_MAPPER_LINK3',
4: 'DIG_STREAM_MAPPER_LINK6',
}
DIG_STREAM_MAPPER_LINK0 = 0
DIG_STREAM_MAPPER_LINK1 = 1
DIG_STREAM_MAPPER_LINK2 = 2
DIG_STREAM_MAPPER_LINK3 = 3
DIG_STREAM_MAPPER_LINK6 = 4
DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET = ctypes.c_uint32 # enum
# values for enumeration 'DME_MEM_POWER_STATE_ENUM'
DME_MEM_POWER_STATE_ENUM__enumvalues = {
0: 'DME_MEM_POWER_STATE_ENUM_ON',
1: 'DME_MEM_POWER_STATE_ENUM_LS',
2: 'DME_MEM_POWER_STATE_ENUM_DS',
3: 'DME_MEM_POWER_STATE_ENUM_SD',
}
DME_MEM_POWER_STATE_ENUM_ON = 0
DME_MEM_POWER_STATE_ENUM_LS = 1
DME_MEM_POWER_STATE_ENUM_DS = 2
DME_MEM_POWER_STATE_ENUM_SD = 3
DME_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DME_MEM_PWR_DIS_CTRL'
DME_MEM_PWR_DIS_CTRL__enumvalues = {
0: 'DME_MEM_ENABLE_MEM_PWR_CTRL',
1: 'DME_MEM_DISABLE_MEM_PWR_CTRL',
}
DME_MEM_ENABLE_MEM_PWR_CTRL = 0
DME_MEM_DISABLE_MEM_PWR_CTRL = 1
DME_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'DME_MEM_PWR_FORCE_CTRL'
DME_MEM_PWR_FORCE_CTRL__enumvalues = {
0: 'DME_MEM_NO_FORCE_REQUEST',
1: 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST',
3: 'DME_MEM_FORCE_SHUT_DOWN_REQUEST',
}
DME_MEM_NO_FORCE_REQUEST = 0
DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1
DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 2
DME_MEM_FORCE_SHUT_DOWN_REQUEST = 3
DME_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'METADATA_HUBP_SEL'
METADATA_HUBP_SEL__enumvalues = {
0: 'METADATA_HUBP_SEL_0',
1: 'METADATA_HUBP_SEL_1',
2: 'METADATA_HUBP_SEL_2',
3: 'METADATA_HUBP_SEL_3',
4: 'METADATA_HUBP_SEL_RESERVED',
}
METADATA_HUBP_SEL_0 = 0
METADATA_HUBP_SEL_1 = 1
METADATA_HUBP_SEL_2 = 2
METADATA_HUBP_SEL_3 = 3
METADATA_HUBP_SEL_RESERVED = 4
METADATA_HUBP_SEL = ctypes.c_uint32 # enum
# values for enumeration 'METADATA_STREAM_TYPE_SEL'
METADATA_STREAM_TYPE_SEL__enumvalues = {
0: 'METADATA_STREAM_DP',
1: 'METADATA_STREAM_DVE',
}
METADATA_STREAM_DP = 0
METADATA_STREAM_DVE = 1
METADATA_STREAM_TYPE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'VPG_MEM_PWR_DIS_CTRL'
VPG_MEM_PWR_DIS_CTRL__enumvalues = {
0: 'VPG_MEM_ENABLE_MEM_PWR_CTRL',
1: 'VPG_MEM_DISABLE_MEM_PWR_CTRL',
}
VPG_MEM_ENABLE_MEM_PWR_CTRL = 0
VPG_MEM_DISABLE_MEM_PWR_CTRL = 1
VPG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'VPG_MEM_PWR_FORCE_CTRL'
VPG_MEM_PWR_FORCE_CTRL__enumvalues = {
0: 'VPG_MEM_NO_FORCE_REQ',
1: 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ',
}
VPG_MEM_NO_FORCE_REQ = 0
VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 1
VPG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_ACP_TYPE'
AFMT_ACP_TYPE__enumvalues = {
0: 'ACP_TYPE_GENERIC_AUDIO',
1: 'ACP_TYPE_ICE60958_AUDIO',
2: 'ACP_TYPE_DVD_AUDIO',
3: 'ACP_TYPE_SUPER_AUDIO_CD',
}
ACP_TYPE_GENERIC_AUDIO = 0
ACP_TYPE_ICE60958_AUDIO = 1
ACP_TYPE_DVD_AUDIO = 2
ACP_TYPE_SUPER_AUDIO_CD = 3
AFMT_ACP_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL'
AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = {
0: 'AFMT_AUDIO_CRC_CH0_SIG',
1: 'AFMT_AUDIO_CRC_CH1_SIG',
2: 'AFMT_AUDIO_CRC_CH2_SIG',
3: 'AFMT_AUDIO_CRC_CH3_SIG',
4: 'AFMT_AUDIO_CRC_CH4_SIG',
5: 'AFMT_AUDIO_CRC_CH5_SIG',
6: 'AFMT_AUDIO_CRC_CH6_SIG',
7: 'AFMT_AUDIO_CRC_CH7_SIG',
8: 'AFMT_AUDIO_CRC_RESERVED_8',
9: 'AFMT_AUDIO_CRC_RESERVED_9',
10: 'AFMT_AUDIO_CRC_RESERVED_10',
11: 'AFMT_AUDIO_CRC_RESERVED_11',
12: 'AFMT_AUDIO_CRC_RESERVED_12',
13: 'AFMT_AUDIO_CRC_RESERVED_13',
14: 'AFMT_AUDIO_CRC_RESERVED_14',
15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT',
}
AFMT_AUDIO_CRC_CH0_SIG = 0
AFMT_AUDIO_CRC_CH1_SIG = 1
AFMT_AUDIO_CRC_CH2_SIG = 2
AFMT_AUDIO_CRC_CH3_SIG = 3
AFMT_AUDIO_CRC_CH4_SIG = 4
AFMT_AUDIO_CRC_CH5_SIG = 5
AFMT_AUDIO_CRC_CH6_SIG = 6
AFMT_AUDIO_CRC_CH7_SIG = 7
AFMT_AUDIO_CRC_RESERVED_8 = 8
AFMT_AUDIO_CRC_RESERVED_9 = 9
AFMT_AUDIO_CRC_RESERVED_10 = 10
AFMT_AUDIO_CRC_RESERVED_11 = 11
AFMT_AUDIO_CRC_RESERVED_12 = 12
AFMT_AUDIO_CRC_RESERVED_13 = 13
AFMT_AUDIO_CRC_RESERVED_14 = 14
AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15
AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT'
AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = {
0: 'AFMT_AUDIO_CRC_ONESHOT',
1: 'AFMT_AUDIO_CRC_AUTO_RESTART',
}
AFMT_AUDIO_CRC_ONESHOT = 0
AFMT_AUDIO_CRC_AUTO_RESTART = 1
AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE'
AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = {
0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT',
1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT',
}
AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0
AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1
AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD'
AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = {
0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS',
1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER',
}
AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0
AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1
AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND'
AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = {
0: 'AFMT_AUDIO_PACKET_SENT_DISABLED',
1: 'AFMT_AUDIO_PACKET_SENT_ENABLED',
}
AFMT_AUDIO_PACKET_SENT_DISABLED = 0
AFMT_AUDIO_PACKET_SENT_ENABLED = 1
AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS'
AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = {
0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED',
1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED',
}
AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0
AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1
AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT'
AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = {
0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0',
1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1',
2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2',
3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3',
4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4',
5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5',
}
AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0
AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1
AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2
AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3
AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4
AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5
AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS'
AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = {
0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS',
1: 'HDMI_SEND_MAX_AUDIO_PACKETS',
}
HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0
HDMI_SEND_MAX_AUDIO_PACKETS = 1
AFMT_HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE'
AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = {
0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK',
1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS',
}
AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0
AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1
AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK'
AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = {
0: 'AFMT_INTERRUPT_DISABLE',
1: 'AFMT_INTERRUPT_ENABLE',
}
AFMT_INTERRUPT_DISABLE = 0
AFMT_INTERRUPT_ENABLE = 1
AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_MEM_PWR_DIS_CTRL'
AFMT_MEM_PWR_DIS_CTRL__enumvalues = {
0: 'AFMT_MEM_ENABLE_MEM_PWR_CTRL',
1: 'AFMT_MEM_DISABLE_MEM_PWR_CTRL',
}
AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0
AFMT_MEM_DISABLE_MEM_PWR_CTRL = 1
AFMT_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_MEM_PWR_FORCE_CTRL'
AFMT_MEM_PWR_FORCE_CTRL__enumvalues = {
0: 'AFMT_MEM_NO_FORCE_REQUEST',
1: 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST',
3: 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST',
}
AFMT_MEM_NO_FORCE_REQUEST = 0
AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1
AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 2
AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 3
AFMT_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN'
AFMT_RAMP_CONTROL0_SIGN__enumvalues = {
0: 'AFMT_RAMP_SIGNED',
1: 'AFMT_RAMP_UNSIGNED',
}
AFMT_RAMP_SIGNED = 0
AFMT_RAMP_UNSIGNED = 1
AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE'
AFMT_VBI_PACKET_CONTROL_ACP_SOURCE__enumvalues = {
0: 'AFMT_ACP_SOURCE_FROM_AZALIA',
1: 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS',
}
AFMT_ACP_SOURCE_FROM_AZALIA = 0
AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 1
AFMT_VBI_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'AUDIO_LAYOUT_SELECT'
AUDIO_LAYOUT_SELECT__enumvalues = {
0: 'AUDIO_LAYOUT_0',
1: 'AUDIO_LAYOUT_1',
}
AUDIO_LAYOUT_0 = 0
AUDIO_LAYOUT_1 = 1
AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DCOH_TEST_CLOCK_MUX_SELECT_ENUM'
DCOH_TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = {
0: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_P',
1: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_R',
2: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX1',
3: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX2',
4: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX3',
5: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX4',
6: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX5',
7: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX6',
8: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_P',
9: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_R',
10: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX1',
11: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX2',
12: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX3',
13: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX4',
14: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX5',
15: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX6',
16: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK0',
17: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK1',
18: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK2',
19: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK3',
20: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK4',
21: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK5',
22: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK6',
23: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK7',
24: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYASYMCLK',
25: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYBSYMCLK',
26: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYCSYMCLK',
27: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYDSYMCLK',
28: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYESYMCLK',
29: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYFSYMCLK',
30: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYGSYMCLK',
}
DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0
DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_R = 1
DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX1 = 2
DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX2 = 3
DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX3 = 4
DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX4 = 5
DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX5 = 6
DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX6 = 7
DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_P = 8
DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_R = 9
DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX1 = 10
DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX2 = 11
DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX3 = 12
DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX4 = 13
DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX5 = 14
DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX6 = 15
DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK0 = 16
DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK1 = 17
DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK2 = 18
DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK3 = 19
DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK4 = 20
DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK5 = 21
DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK6 = 22
DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK7 = 23
DCOH_TEST_CLOCK_MUX_SELECT_PHYASYMCLK = 24
DCOH_TEST_CLOCK_MUX_SELECT_PHYBSYMCLK = 25
DCOH_TEST_CLOCK_MUX_SELECT_PHYCSYMCLK = 26
DCOH_TEST_CLOCK_MUX_SELECT_PHYDSYMCLK = 27
DCOH_TEST_CLOCK_MUX_SELECT_PHYESYMCLK = 28
DCOH_TEST_CLOCK_MUX_SELECT_PHYFSYMCLK = 29
DCOH_TEST_CLOCK_MUX_SELECT_PHYGSYMCLK = 30
DCOH_TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM'
DCOH_TOP_CLOCK_GATING_DISABLE_ENUM__enumvalues = {
0: 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_ENABLED',
1: 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_DISABLED',
}
DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_ENABLED = 0
DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_DISABLED = 1
DCOH_TOP_CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DCOH_TOP_ENABLE_ENUM'
DCOH_TOP_ENABLE_ENUM__enumvalues = {
0: 'DCOH_TOP_ENABLE_ENUM_DISABLED',
1: 'DCOH_TOP_ENABLE_ENUM_ENABLED',
}
DCOH_TOP_ENABLE_ENUM_DISABLED = 0
DCOH_TOP_ENABLE_ENUM_ENABLED = 1
DCOH_TOP_ENABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'PHY_MUX_ENABLE_ENUM'
PHY_MUX_ENABLE_ENUM__enumvalues = {
0: 'PHY_MUX_ENABLE_ENUM_DISABLED',
1: 'PHY_MUX_ENABLE_ENUM_ENABLED',
}
PHY_MUX_ENABLE_ENUM_DISABLED = 0
PHY_MUX_ENABLE_ENUM_ENABLED = 1
PHY_MUX_ENABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY'
DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = {
0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW',
1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW',
2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC',
3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS',
}
DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0
DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1
DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2
DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3
DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG'
DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = {
0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG',
1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG',
}
DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0
DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1
DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ'
DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = {
0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ',
1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ',
}
DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0
DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1
DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ARB_STATUS'
DP_AUX_ARB_STATUS__enumvalues = {
0: 'DP_AUX_IDLE',
1: 'DP_AUX_IN_USE_LS',
2: 'DP_AUX_IN_USE_GTC',
3: 'DP_AUX_IN_USE_SW',
4: 'DP_AUX_IN_USE_PHYWAKE',
}
DP_AUX_IDLE = 0
DP_AUX_IN_USE_LS = 1
DP_AUX_IN_USE_GTC = 2
DP_AUX_IN_USE_SW = 3
DP_AUX_IN_USE_PHYWAKE = 4
DP_AUX_ARB_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_CONTROL_HPD_SEL'
DP_AUX_CONTROL_HPD_SEL__enumvalues = {
0: 'DP_AUX_CONTROL_HPD1_SELECTED',
1: 'DP_AUX_CONTROL_HPD2_SELECTED',
2: 'DP_AUX_CONTROL_HPD3_SELECTED',
3: 'DP_AUX_CONTROL_HPD4_SELECTED',
4: 'DP_AUX_CONTROL_NO_HPD_SELECTED',
}
DP_AUX_CONTROL_HPD1_SELECTED = 0
DP_AUX_CONTROL_HPD2_SELECTED = 1
DP_AUX_CONTROL_HPD3_SELECTED = 2
DP_AUX_CONTROL_HPD4_SELECTED = 3
DP_AUX_CONTROL_NO_HPD_SELECTED = 4
DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_CONTROL_TEST_MODE'
DP_AUX_CONTROL_TEST_MODE__enumvalues = {
0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE',
1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE',
}
DP_AUX_CONTROL_TEST_MODE_DISABLE = 0
DP_AUX_CONTROL_TEST_MODE_ENABLE = 1
DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK'
DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = {
0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK',
1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK',
}
ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0
ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1
DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT'
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
}
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START'
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START',
1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START',
}
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP'
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP',
1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP',
}
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN'
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES',
1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES',
2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES',
3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED',
}
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN'
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS',
1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS',
2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS',
3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS',
}
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW'
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD',
1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD',
2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD',
3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD',
4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD',
5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD',
6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD',
7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD',
}
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW'
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD',
1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD',
2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD',
3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD',
4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD',
5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD',
6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD',
7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD',
}
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7
DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD'
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = {
0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2',
1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4',
2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8',
3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16',
4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32',
5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64',
6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128',
7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256',
}
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7
DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY'
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = {
0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0',
1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US',
2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US',
3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US',
4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US',
5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US',
}
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE'
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = {
0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ',
1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ',
2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ',
3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ',
}
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL'
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = {
0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK',
1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF',
}
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK'
DP_AUX_ERR_OCCURRED_ACK__enumvalues = {
0: 'DP_AUX_ERR_OCCURRED__NOT_ACK',
1: 'DP_AUX_ERR_OCCURRED__ACK',
}
DP_AUX_ERR_OCCURRED__NOT_ACK = 0
DP_AUX_ERR_OCCURRED__ACK = 1
DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ'
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = {
0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX',
1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX',
}
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW'
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = {
0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US',
1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US',
2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US',
3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US',
}
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT'
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = {
0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS',
1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS',
2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS',
3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED',
}
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN'
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = {
0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0',
1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64',
2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128',
3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256',
}
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_INT_ACK'
DP_AUX_INT_ACK__enumvalues = {
0: 'DP_AUX_INT__NOT_ACK',
1: 'DP_AUX_INT__ACK',
}
DP_AUX_INT__NOT_ACK = 0
DP_AUX_INT__ACK = 1
DP_AUX_INT_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_LS_UPDATE_ACK'
DP_AUX_LS_UPDATE_ACK__enumvalues = {
0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK',
1: 'DP_AUX_INT_LS_UPDATE_ACK',
}
DP_AUX_INT_LS_UPDATE_NOT_ACK = 0
DP_AUX_INT_LS_UPDATE_ACK = 1
DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_PHY_WAKE_PRIORITY'
DP_AUX_PHY_WAKE_PRIORITY__enumvalues = {
0: 'DP_AUX_PHY_WAKE_HIGH_PRIORITY',
1: 'DP_AUX_PHY_WAKE_LOW_PRIORITY',
}
DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0
DP_AUX_PHY_WAKE_LOW_PRIORITY = 1
DP_AUX_PHY_WAKE_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK'
DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = {
0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK',
1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK',
}
DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0
DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1
DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_RESET'
DP_AUX_RESET__enumvalues = {
0: 'DP_AUX_RESET_DEASSERTED',
1: 'DP_AUX_RESET_ASSERTED',
}
DP_AUX_RESET_DEASSERTED = 0
DP_AUX_RESET_ASSERTED = 1
DP_AUX_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_RESET_DONE'
DP_AUX_RESET_DONE__enumvalues = {
0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE',
1: 'DP_AUX_RESET_SEQUENCE_DONE',
}
DP_AUX_RESET_SEQUENCE_NOT_DONE = 0
DP_AUX_RESET_SEQUENCE_DONE = 1
DP_AUX_RESET_DONE = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_RX_TIMEOUT_LEN_MUL'
DP_AUX_RX_TIMEOUT_LEN_MUL__enumvalues = {
0: 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL',
1: 'DP_AUX_RX_TIMEOUT_LEN_MUL_2',
2: 'DP_AUX_RX_TIMEOUT_LEN_MUL_4',
3: 'DP_AUX_RX_TIMEOUT_LEN_MUL_8',
}
DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0
DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 1
DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 2
DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 3
DP_AUX_RX_TIMEOUT_LEN_MUL = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG'
DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = {
0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG',
1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG',
}
DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0
DP_AUX_SW_CONTROL_LS_READ__TRIG = 1
DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO'
DP_AUX_SW_CONTROL_SW_GO__enumvalues = {
0: 'DP_AUX_SW_CONTROL_SW__NOT_GO',
1: 'DP_AUX_SW_CONTROL_SW__GO',
}
DP_AUX_SW_CONTROL_SW__NOT_GO = 0
DP_AUX_SW_CONTROL_SW__GO = 1
DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_TX_PRECHARGE_LEN_MUL'
DP_AUX_TX_PRECHARGE_LEN_MUL__enumvalues = {
0: 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL',
1: 'DP_AUX_TX_PRECHARGE_LEN_MUL_2',
2: 'DP_AUX_TX_PRECHARGE_LEN_MUL_4',
3: 'DP_AUX_TX_PRECHARGE_LEN_MUL_8',
}
DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0
DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 1
DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 2
DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 3
DP_AUX_TX_PRECHARGE_LEN_MUL = ctypes.c_uint32 # enum
# values for enumeration 'HPD_INT_CONTROL_ACK'
HPD_INT_CONTROL_ACK__enumvalues = {
0: 'HPD_INT_CONTROL_ACK_0',
1: 'HPD_INT_CONTROL_ACK_1',
}
HPD_INT_CONTROL_ACK_0 = 0
HPD_INT_CONTROL_ACK_1 = 1
HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum
# values for enumeration 'HPD_INT_CONTROL_POLARITY'
HPD_INT_CONTROL_POLARITY__enumvalues = {
0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON',
1: 'HPD_INT_CONTROL_GEN_INT_ON_CON',
}
HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0
HPD_INT_CONTROL_GEN_INT_ON_CON = 1
HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK'
HPD_INT_CONTROL_RX_INT_ACK__enumvalues = {
0: 'HPD_INT_CONTROL_RX_INT_ACK_0',
1: 'HPD_INT_CONTROL_RX_INT_ACK_1',
}
HPD_INT_CONTROL_RX_INT_ACK_0 = 0
HPD_INT_CONTROL_RX_INT_ACK_1 = 1
HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum
# values for enumeration 'HPO_TOP_CLOCK_GATING_DISABLE'
HPO_TOP_CLOCK_GATING_DISABLE__enumvalues = {
0: 'HPO_TOP_CLOCK_GATING_EN',
1: 'HPO_TOP_CLOCK_GATING_DIS',
}
HPO_TOP_CLOCK_GATING_EN = 0
HPO_TOP_CLOCK_GATING_DIS = 1
HPO_TOP_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'HPO_TOP_TEST_CLK_SEL'
HPO_TOP_TEST_CLK_SEL__enumvalues = {
0: 'HPO_TOP_PERMANENT_DISPCLK',
1: 'HPO_TOP_REGISTER_GATED_DISPCLK',
2: 'HPO_TOP_PERMANENT_SOCCLK',
3: 'HPO_TOP_TEST_CLOCK_RESERVED',
4: 'HPO_TOP_PERMANENT_HDMISTREAMCLK0',
5: 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0',
6: 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0',
7: 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0',
8: 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0',
9: 'HPO_TOP_PERMANENT_HDMICHARCLK0',
10: 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0',
11: 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0',
}
HPO_TOP_PERMANENT_DISPCLK = 0
HPO_TOP_REGISTER_GATED_DISPCLK = 1
HPO_TOP_PERMANENT_SOCCLK = 2
HPO_TOP_TEST_CLOCK_RESERVED = 3
HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 4
HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 5
HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 6
HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 7
HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 8
HPO_TOP_PERMANENT_HDMICHARCLK0 = 9
HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 10
HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 11
HPO_TOP_TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET'
DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET__enumvalues = {
0: 'DP_STREAM_MAPPER_LINK0',
1: 'DP_STREAM_MAPPER_LINK1',
2: 'DP_STREAM_MAPPER_LINK2',
3: 'DP_STREAM_MAPPER_LINK3',
4: 'DP_STREAM_MAPPER_RESERVED',
}
DP_STREAM_MAPPER_LINK0 = 0
DP_STREAM_MAPPER_LINK1 = 1
DP_STREAM_MAPPER_LINK2 = 2
DP_STREAM_MAPPER_LINK3 = 3
DP_STREAM_MAPPER_RESERVED = 4
DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET = ctypes.c_uint32 # enum
# values for enumeration 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR'
DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = {
0: 'DP_STREAM_ENC_NO_ERROR_OCCURRED',
1: 'DP_STREAM_ENC_UNDERFLOW_OCCURRED',
2: 'DP_STREAM_ENC_OVERFLOW_OCCURRED',
}
DP_STREAM_ENC_NO_ERROR_OCCURRED = 0
DP_STREAM_ENC_UNDERFLOW_OCCURRED = 1
DP_STREAM_ENC_OVERFLOW_OCCURRED = 2
DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT'
DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = {
0: 'DP_STREAM_ENC_HARDWARE',
1: 'DP_STREAM_ENC_PROGRAMMABLE',
}
DP_STREAM_ENC_HARDWARE = 0
DP_STREAM_ENC_PROGRAMMABLE = 1
DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DP_STREAM_ENC_READ_CLOCK_CONTROL'
DP_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = {
0: 'DP_STREAM_ENC_DCCG',
1: 'DP_STREAM_ENC_DISPLAY_PIPE',
}
DP_STREAM_ENC_DCCG = 0
DP_STREAM_ENC_DISPLAY_PIPE = 1
DP_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'DP_STREAM_ENC_RESET_CONTROL'
DP_STREAM_ENC_RESET_CONTROL__enumvalues = {
0: 'DP_STREAM_ENC_NOT_RESET',
1: 'DP_STREAM_ENC_RESET',
}
DP_STREAM_ENC_NOT_RESET = 0
DP_STREAM_ENC_RESET = 1
DP_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'DP_STREAM_ENC_STREAM_ACTIVE'
DP_STREAM_ENC_STREAM_ACTIVE__enumvalues = {
0: 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE',
1: 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE',
}
DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0
DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1
DP_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_AUDIO_MUTE'
ENUM_DP_SYM32_ENC_AUDIO_MUTE__enumvalues = {
0: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED',
1: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED',
}
DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0
DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 1
ENUM_DP_SYM32_ENC_AUDIO_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE'
ENUM_DP_SYM32_ENC_CONTINUOUS_MODE__enumvalues = {
0: 'DP_SYM32_ENC_ONE_SHOT_MODE',
1: 'DP_SYM32_ENC_CONTINUOUS_MODE',
}
DP_SYM32_ENC_ONE_SHOT_MODE = 0
DP_SYM32_ENC_CONTINUOUS_MODE = 1
ENUM_DP_SYM32_ENC_CONTINUOUS_MODE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_CRC_VALID'
ENUM_DP_SYM32_ENC_CRC_VALID__enumvalues = {
0: 'DP_SYM32_ENC_CRC_NOT_VALID',
1: 'DP_SYM32_ENC_CRC_VALID',
}
DP_SYM32_ENC_CRC_NOT_VALID = 0
DP_SYM32_ENC_CRC_VALID = 1
ENUM_DP_SYM32_ENC_CRC_VALID = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH'
ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH__enumvalues = {
0: 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC',
1: 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC',
2: 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC',
3: 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC',
}
DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0
DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 1
DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 2
DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 3
ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_ENABLE'
ENUM_DP_SYM32_ENC_ENABLE__enumvalues = {
0: 'DP_SYM32_ENC_DISABLE',
1: 'DP_SYM32_ENC_ENABLE',
}
DP_SYM32_ENC_DISABLE = 0
DP_SYM32_ENC_ENABLE = 1
ENUM_DP_SYM32_ENC_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED'
ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED__enumvalues = {
0: 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED',
1: 'DP_SYM32_ENC_GSP_DEADLINE_MISSED',
}
DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0
DP_SYM32_ENC_GSP_DEADLINE_MISSED = 1
ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION'
ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION__enumvalues = {
0: 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER',
1: 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME',
}
DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0
DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 1
ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE'
ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE__enumvalues = {
0: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32',
1: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0',
2: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1',
3: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128',
}
DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0
DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 1
DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 2
DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 3
ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING'
ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING__enumvalues = {
0: 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING',
1: 'DP_SYM32_ENC_GSP_TRIGGER_PENDING',
}
DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0
DP_SYM32_ENC_GSP_TRIGGER_PENDING = 1
ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM'
ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM__enumvalues = {
0: 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST',
1: 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST',
2: 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST',
3: 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST',
}
DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0
DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 1
DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 2
DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 3
ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS'
ENUM_DP_SYM32_ENC_OVERFLOW_STATUS__enumvalues = {
0: 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED',
1: 'DP_SYM32_ENC_OVERFLOW_OCCURRED',
}
DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0
DP_SYM32_ENC_OVERFLOW_OCCURRED = 1
ENUM_DP_SYM32_ENC_OVERFLOW_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_PENDING'
ENUM_DP_SYM32_ENC_PENDING__enumvalues = {
0: 'DP_SYM32_ENC_NOT_PENDING',
1: 'DP_SYM32_ENC_PENDING',
}
DP_SYM32_ENC_NOT_PENDING = 0
DP_SYM32_ENC_PENDING = 1
ENUM_DP_SYM32_ENC_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING'
ENUM_DP_SYM32_ENC_PIXEL_ENCODING__enumvalues = {
0: 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444',
1: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422',
2: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420',
3: 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY',
}
DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0
DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 1
DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 2
DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 3
ENUM_DP_SYM32_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE'
ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE__enumvalues = {
0: 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT',
1: 'DP_SYM32_ENC_COMPRESSED_FORMAT',
}
DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0
DP_SYM32_ENC_COMPRESSED_FORMAT = 1
ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM'
ENUM_DP_SYM32_ENC_POWER_STATE_ENUM__enumvalues = {
0: 'DP_SYM32_ENC_POWER_STATE_ENUM_ON',
1: 'DP_SYM32_ENC_POWER_STATE_ENUM_LS',
2: 'DP_SYM32_ENC_POWER_STATE_ENUM_DS',
3: 'DP_SYM32_ENC_POWER_STATE_ENUM_SD',
}
DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0
DP_SYM32_ENC_POWER_STATE_ENUM_LS = 1
DP_SYM32_ENC_POWER_STATE_ENUM_DS = 2
DP_SYM32_ENC_POWER_STATE_ENUM_SD = 3
ENUM_DP_SYM32_ENC_POWER_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_RESET'
ENUM_DP_SYM32_ENC_RESET__enumvalues = {
0: 'DP_SYM32_ENC_NOT_RESET',
1: 'DP_SYM32_ENC_RESET',
}
DP_SYM32_ENC_NOT_RESET = 0
DP_SYM32_ENC_RESET = 1
ENUM_DP_SYM32_ENC_RESET = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_SDP_PRIORITY'
ENUM_DP_SYM32_ENC_SDP_PRIORITY__enumvalues = {
0: 'DP_SYM32_ENC_SDP_LOW_PRIORITY',
1: 'DP_SYM32_ENC_SDP_HIGH_PRIORITY',
}
DP_SYM32_ENC_SDP_LOW_PRIORITY = 0
DP_SYM32_ENC_SDP_HIGH_PRIORITY = 1
ENUM_DP_SYM32_ENC_SDP_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_SOF_REFERENCE'
ENUM_DP_SYM32_ENC_SOF_REFERENCE__enumvalues = {
0: 'DP_SYM32_ENC_DP_SOF',
1: 'DP_SYM32_ENC_OTG_SOF',
}
DP_SYM32_ENC_DP_SOF = 0
DP_SYM32_ENC_OTG_SOF = 1
ENUM_DP_SYM32_ENC_SOF_REFERENCE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER'
ENUM_DP_SYM32_ENC_VID_STREAM_DEFER__enumvalues = {
0: 'DP_SYM32_ENC_VID_STREAM_NO_DEFER',
1: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK',
2: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK',
}
DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0
DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 1
DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 2
ENUM_DP_SYM32_ENC_VID_STREAM_DEFER = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT'
ENUM_DP_DPHY_SYM32_CRC_END_EVENT__enumvalues = {
0: 'DP_DPHY_SYM32_CRC_END_LLCP',
1: 'DP_DPHY_SYM32_CRC_END_PS_ONLY',
2: 'DP_DPHY_SYM32_CRC_END_PS_LT_SR',
3: 'DP_DPHY_SYM32_CRC_END_PS_ANY',
}
DP_DPHY_SYM32_CRC_END_LLCP = 0
DP_DPHY_SYM32_CRC_END_PS_ONLY = 1
DP_DPHY_SYM32_CRC_END_PS_LT_SR = 2
DP_DPHY_SYM32_CRC_END_PS_ANY = 3
ENUM_DP_DPHY_SYM32_CRC_END_EVENT = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT'
ENUM_DP_DPHY_SYM32_CRC_START_EVENT__enumvalues = {
0: 'DP_DPHY_SYM32_CRC_START_LLCP',
1: 'DP_DPHY_SYM32_CRC_START_PS_ONLY',
2: 'DP_DPHY_SYM32_CRC_START_PS_LT_SR',
3: 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR',
4: 'DP_DPHY_SYM32_CRC_START_TP_START',
}
DP_DPHY_SYM32_CRC_START_LLCP = 0
DP_DPHY_SYM32_CRC_START_PS_ONLY = 1
DP_DPHY_SYM32_CRC_START_PS_LT_SR = 2
DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 3
DP_DPHY_SYM32_CRC_START_TP_START = 4
ENUM_DP_DPHY_SYM32_CRC_START_EVENT = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE'
ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE__enumvalues = {
0: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER',
1: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER',
2: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX',
}
DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0
DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 1
DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 2
ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS'
ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS__enumvalues = {
0: 'DP_DPHY_SYM32_CRC_USE_END_EVENT',
1: 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS',
}
DP_DPHY_SYM32_CRC_USE_END_EVENT = 0
DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 1
ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_ENABLE'
ENUM_DP_DPHY_SYM32_ENABLE__enumvalues = {
0: 'DP_DPHY_SYM32_DISABLE',
1: 'DP_DPHY_SYM32_ENABLE',
}
DP_DPHY_SYM32_DISABLE = 0
DP_DPHY_SYM32_ENABLE = 1
ENUM_DP_DPHY_SYM32_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_MODE'
ENUM_DP_DPHY_SYM32_MODE__enumvalues = {
0: 'DP_DPHY_SYM32_LT_TPS1',
1: 'DP_DPHY_SYM32_LT_TPS2',
2: 'DP_DPHY_SYM32_ACTIVE',
3: 'DP_DPHY_SYM32_TEST',
}
DP_DPHY_SYM32_LT_TPS1 = 0
DP_DPHY_SYM32_LT_TPS2 = 1
DP_DPHY_SYM32_ACTIVE = 2
DP_DPHY_SYM32_TEST = 3
ENUM_DP_DPHY_SYM32_MODE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_NUM_LANES'
ENUM_DP_DPHY_SYM32_NUM_LANES__enumvalues = {
0: 'DP_DPHY_SYM32_1LANE',
1: 'DP_DPHY_SYM32_2LANE',
2: 'DP_DPHY_SYM32_RESERVED',
3: 'DP_DPHY_SYM32_4LANE',
}
DP_DPHY_SYM32_1LANE = 0
DP_DPHY_SYM32_2LANE = 1
DP_DPHY_SYM32_RESERVED = 2
DP_DPHY_SYM32_4LANE = 3
ENUM_DP_DPHY_SYM32_NUM_LANES = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_OUTPUT_MODE'
ENUM_DP_DPHY_SYM32_OUTPUT_MODE__enumvalues = {
0: 'DP_DPHY_SYM32_OUTPUT_PHY',
1: 'DP_DPHY_SYM32_OUTPUT_DPIA',
}
DP_DPHY_SYM32_OUTPUT_PHY = 0
DP_DPHY_SYM32_OUTPUT_DPIA = 1
ENUM_DP_DPHY_SYM32_OUTPUT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING'
ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING__enumvalues = {
0: 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING',
1: 'DP_DPHY_SYM32_RATE_UPDATE_PENDING',
}
DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0
DP_DPHY_SYM32_RATE_UPDATE_PENDING = 1
ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET'
ENUM_DP_DPHY_SYM32_RESET__enumvalues = {
0: 'DP_DPHY_SYM32_NOT_RESET',
1: 'DP_DPHY_SYM32_RESET',
}
DP_DPHY_SYM32_NOT_RESET = 0
DP_DPHY_SYM32_RESET = 1
ENUM_DP_DPHY_SYM32_RESET = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET_STATUS'
ENUM_DP_DPHY_SYM32_RESET_STATUS__enumvalues = {
0: 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED',
1: 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED',
}
DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0
DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 1
ENUM_DP_DPHY_SYM32_RESET_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE'
ENUM_DP_DPHY_SYM32_SAT_UPDATE__enumvalues = {
0: 'DP_DPHY_SYM32_SAT_NO_UPDATE',
1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE',
2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE',
}
DP_DPHY_SYM32_SAT_NO_UPDATE = 0
DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 1
DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 2
ENUM_DP_DPHY_SYM32_SAT_UPDATE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING'
ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING__enumvalues = {
0: 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING',
1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING',
2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING',
}
DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0
DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 1
DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 2
ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS'
ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS__enumvalues = {
0: 'DP_DPHY_SYM32_SCHEDULER_OFF',
1: 'DP_DPHY_SYM32_SCHEDULER_ASLEEP',
2: 'DP_DPHY_SYM32_SCHEDULER_AWAKE',
}
DP_DPHY_SYM32_SCHEDULER_OFF = 0
DP_DPHY_SYM32_SCHEDULER_ASLEEP = 1
DP_DPHY_SYM32_SCHEDULER_AWAKE = 2
ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_STATUS'
ENUM_DP_DPHY_SYM32_STATUS__enumvalues = {
0: 'DP_DPHY_SYM32_STATUS_IDLE',
1: 'DP_DPHY_SYM32_STATUS_ENABLED',
}
DP_DPHY_SYM32_STATUS_IDLE = 0
DP_DPHY_SYM32_STATUS_ENABLED = 1
ENUM_DP_DPHY_SYM32_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE'
ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE__enumvalues = {
0: 'DP_DPHY_SYM32_STREAM_OVR_NONE',
1: 'DP_DPHY_SYM32_STREAM_OVR_REPLACE',
2: 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS',
}
DP_DPHY_SYM32_STREAM_OVR_NONE = 0
DP_DPHY_SYM32_STREAM_OVR_REPLACE = 1
DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 2
ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE'
ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE__enumvalues = {
0: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA',
1: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL',
}
DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0
DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 1
ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL'
ENUM_DP_DPHY_SYM32_TP_PRBS_SEL__enumvalues = {
0: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7',
1: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9',
2: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11',
3: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15',
4: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23',
5: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31',
}
DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0
DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 1
DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 2
DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 3
DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 4
DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 5
ENUM_DP_DPHY_SYM32_TP_PRBS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_SELECT'
ENUM_DP_DPHY_SYM32_TP_SELECT__enumvalues = {
0: 'DP_DPHY_SYM32_TP_SELECT_TPS1',
1: 'DP_DPHY_SYM32_TP_SELECT_TPS2',
2: 'DP_DPHY_SYM32_TP_SELECT_PRBS',
3: 'DP_DPHY_SYM32_TP_SELECT_CUSTOM',
4: 'DP_DPHY_SYM32_TP_SELECT_SQUARE',
}
DP_DPHY_SYM32_TP_SELECT_TPS1 = 0
DP_DPHY_SYM32_TP_SELECT_TPS2 = 1
DP_DPHY_SYM32_TP_SELECT_PRBS = 2
DP_DPHY_SYM32_TP_SELECT_CUSTOM = 3
DP_DPHY_SYM32_TP_SELECT_SQUARE = 4
ENUM_DP_DPHY_SYM32_TP_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'APG_AUDIO_CRC_CONTROL_CH_SEL'
APG_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = {
0: 'APG_AUDIO_CRC_CH0_SIG',
1: 'APG_AUDIO_CRC_CH1_SIG',
2: 'APG_AUDIO_CRC_CH2_SIG',
3: 'APG_AUDIO_CRC_CH3_SIG',
4: 'APG_AUDIO_CRC_CH4_SIG',
5: 'APG_AUDIO_CRC_CH5_SIG',
6: 'APG_AUDIO_CRC_CH6_SIG',
7: 'APG_AUDIO_CRC_CH7_SIG',
8: 'APG_AUDIO_CRC_RESERVED_8',
9: 'APG_AUDIO_CRC_RESERVED_9',
10: 'APG_AUDIO_CRC_RESERVED_10',
11: 'APG_AUDIO_CRC_RESERVED_11',
12: 'APG_AUDIO_CRC_RESERVED_12',
13: 'APG_AUDIO_CRC_RESERVED_13',
14: 'APG_AUDIO_CRC_RESERVED_14',
15: 'APG_AUDIO_CRC_RESERVED_15',
}
APG_AUDIO_CRC_CH0_SIG = 0
APG_AUDIO_CRC_CH1_SIG = 1
APG_AUDIO_CRC_CH2_SIG = 2
APG_AUDIO_CRC_CH3_SIG = 3
APG_AUDIO_CRC_CH4_SIG = 4
APG_AUDIO_CRC_CH5_SIG = 5
APG_AUDIO_CRC_CH6_SIG = 6
APG_AUDIO_CRC_CH7_SIG = 7
APG_AUDIO_CRC_RESERVED_8 = 8
APG_AUDIO_CRC_RESERVED_9 = 9
APG_AUDIO_CRC_RESERVED_10 = 10
APG_AUDIO_CRC_RESERVED_11 = 11
APG_AUDIO_CRC_RESERVED_12 = 12
APG_AUDIO_CRC_RESERVED_13 = 13
APG_AUDIO_CRC_RESERVED_14 = 14
APG_AUDIO_CRC_RESERVED_15 = 15
APG_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum
# values for enumeration 'APG_AUDIO_CRC_CONTROL_CONT'
APG_AUDIO_CRC_CONTROL_CONT__enumvalues = {
0: 'APG_AUDIO_CRC_ONESHOT',
1: 'APG_AUDIO_CRC_CONTINUOUS',
}
APG_AUDIO_CRC_ONESHOT = 0
APG_AUDIO_CRC_CONTINUOUS = 1
APG_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum
# values for enumeration 'APG_DBG_ACP_TYPE'
APG_DBG_ACP_TYPE__enumvalues = {
0: 'APG_ACP_TYPE_GENERIC_AUDIO',
1: 'APG_ACP_TYPE_ICE60958_AUDIO',
2: 'APG_ACP_TYPE_DVD_AUDIO',
3: 'APG_ACP_TYPE_SUPER_AUDIO_CD',
}
APG_ACP_TYPE_GENERIC_AUDIO = 0
APG_ACP_TYPE_ICE60958_AUDIO = 1
APG_ACP_TYPE_DVD_AUDIO = 2
APG_ACP_TYPE_SUPER_AUDIO_CD = 3
APG_DBG_ACP_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'APG_DBG_AUDIO_DTO_BASE'
APG_DBG_AUDIO_DTO_BASE__enumvalues = {
0: 'BASE_RATE_48KHZ',
1: 'BASE_RATE_44P1KHZ',
}
BASE_RATE_48KHZ = 0
BASE_RATE_44P1KHZ = 1
APG_DBG_AUDIO_DTO_BASE = ctypes.c_uint32 # enum
# values for enumeration 'APG_DBG_AUDIO_DTO_DIV'
APG_DBG_AUDIO_DTO_DIV__enumvalues = {
0: 'DIVISOR_BY1',
1: 'DIVISOR_BY2_RESERVED',
2: 'DIVISOR_BY3',
3: 'DIVISOR_BY4_RESERVED',
4: 'DIVISOR_BY5_RESERVED',
5: 'DIVISOR_BY6_RESERVED',
6: 'DIVISOR_BY7_RESERVED',
7: 'DIVISOR_BY8_RESERVED',
}
DIVISOR_BY1 = 0
DIVISOR_BY2_RESERVED = 1
DIVISOR_BY3 = 2
DIVISOR_BY4_RESERVED = 3
DIVISOR_BY5_RESERVED = 4
DIVISOR_BY6_RESERVED = 5
DIVISOR_BY7_RESERVED = 6
DIVISOR_BY8_RESERVED = 7
APG_DBG_AUDIO_DTO_DIV = ctypes.c_uint32 # enum
# values for enumeration 'APG_DBG_AUDIO_DTO_MULTI'
APG_DBG_AUDIO_DTO_MULTI__enumvalues = {
0: 'MULTIPLE_BY1',
1: 'MULTIPLE_BY2',
2: 'MULTIPLE_BY3_RESERVED',
3: 'MULTIPLE_BY4',
4: 'MULTIPLE_RESERVED',
}
MULTIPLE_BY1 = 0
MULTIPLE_BY2 = 1
MULTIPLE_BY3_RESERVED = 2
MULTIPLE_BY4 = 3
MULTIPLE_RESERVED = 4
APG_DBG_AUDIO_DTO_MULTI = ctypes.c_uint32 # enum
# values for enumeration 'APG_DBG_MUX_SEL'
APG_DBG_MUX_SEL__enumvalues = {
0: 'APG_FUNCTIONAL_MODE',
1: 'APG_DEBUG_AUDIO_MODE',
}
APG_FUNCTIONAL_MODE = 0
APG_DEBUG_AUDIO_MODE = 1
APG_DBG_MUX_SEL = ctypes.c_uint32 # enum
# values for enumeration 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE'
APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = {
0: 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ',
1: 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED',
}
APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0
APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1
APG_DP_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'APG_MEM_POWER_STATE'
APG_MEM_POWER_STATE__enumvalues = {
0: 'APG_MEM_POWER_STATE_ON',
1: 'APG_MEM_POWER_STATE_LS',
2: 'APG_MEM_POWER_STATE_DS',
3: 'APG_MEM_POWER_STATE_SD',
}
APG_MEM_POWER_STATE_ON = 0
APG_MEM_POWER_STATE_LS = 1
APG_MEM_POWER_STATE_DS = 2
APG_MEM_POWER_STATE_SD = 3
APG_MEM_POWER_STATE = ctypes.c_uint32 # enum
# values for enumeration 'APG_MEM_PWR_DIS_CTRL'
APG_MEM_PWR_DIS_CTRL__enumvalues = {
0: 'APG_MEM_ENABLE_MEM_PWR_CTRL',
1: 'APG_MEM_DISABLE_MEM_PWR_CTRL',
}
APG_MEM_ENABLE_MEM_PWR_CTRL = 0
APG_MEM_DISABLE_MEM_PWR_CTRL = 1
APG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'APG_MEM_PWR_FORCE_CTRL'
APG_MEM_PWR_FORCE_CTRL__enumvalues = {
0: 'APG_MEM_NO_FORCE_REQUEST',
1: 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST',
3: 'APG_MEM_FORCE_SHUT_DOWN_REQUEST',
}
APG_MEM_NO_FORCE_REQUEST = 0
APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1
APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 2
APG_MEM_FORCE_SHUT_DOWN_REQUEST = 3
APG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'APG_PACKET_CONTROL_ACP_SOURCE'
APG_PACKET_CONTROL_ACP_SOURCE__enumvalues = {
0: 'APG_ACP_SOURCE_NO_OVERRIDE',
1: 'APG_ACP_OVERRIDE',
}
APG_ACP_SOURCE_NO_OVERRIDE = 0
APG_ACP_OVERRIDE = 1
APG_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE'
APG_PACKET_CONTROL_AUDIO_INFO_SOURCE__enumvalues = {
0: 'APG_INFOFRAME_SOURCE_NO_OVERRIDE',
1: 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS',
}
APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0
APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 1
APG_PACKET_CONTROL_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'APG_RAMP_CONTROL_SIGN'
APG_RAMP_CONTROL_SIGN__enumvalues = {
0: 'APG_RAMP_SIGNED',
1: 'APG_RAMP_UNSIGNED',
}
APG_RAMP_SIGNED = 0
APG_RAMP_UNSIGNED = 1
APG_RAMP_CONTROL_SIGN = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL'
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = {
0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1',
1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2',
2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3',
3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4',
4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5',
5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6',
}
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL'
DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = {
0: 'DCIO_TEST_CLK_SEL_DISPCLK',
1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK',
2: 'DCIO_TEST_CLK_SEL_SOCCLK',
}
DCIO_TEST_CLK_SEL_DISPCLK = 0
DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1
DCIO_TEST_CLK_SEL_SOCCLK = 2
DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS'
DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = {
0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE',
1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE',
}
DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0
DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1
DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DBG_ASYNC_4BIT_SEL'
DCIO_DBG_ASYNC_4BIT_SEL__enumvalues = {
0: 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0',
1: 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4',
2: 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8',
3: 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12',
4: 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16',
5: 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20',
6: 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24',
7: 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28',
}
DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0
DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 1
DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 2
DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 3
DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 4
DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 5
DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 6
DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 7
DCIO_DBG_ASYNC_4BIT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DBG_ASYNC_BLOCK_SEL'
DCIO_DBG_ASYNC_BLOCK_SEL__enumvalues = {
0: 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE',
1: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG',
2: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO',
3: 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO',
}
DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0
DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 1
DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 2
DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 3
DCIO_DBG_ASYNC_BLOCK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET'
DCIO_DCRXPHY_SOFT_RESET__enumvalues = {
0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT',
1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT',
}
DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0
DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1
DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERICA_SEL'
DCIO_DC_GENERICA_SEL__enumvalues = {
1: 'DCIO_GENERICA_SEL_STEREOSYNC',
10: 'DCIO_GENERICA_SEL_GENERICA_DCCG',
11: 'DCIO_GENERICA_SEL_SYNCEN',
}
DCIO_GENERICA_SEL_STEREOSYNC = 1
DCIO_GENERICA_SEL_GENERICA_DCCG = 10
DCIO_GENERICA_SEL_SYNCEN = 11
DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERICB_SEL'
DCIO_DC_GENERICB_SEL__enumvalues = {
1: 'DCIO_GENERICB_SEL_STEREOSYNC',
10: 'DCIO_GENERICB_SEL_GENERICB_DCCG',
11: 'DCIO_GENERICB_SEL_SYNCEN',
}
DCIO_GENERICB_SEL_STEREOSYNC = 1
DCIO_GENERICB_SEL_GENERICB_DCCG = 10
DCIO_GENERICB_SEL_SYNCEN = 11
DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL'
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = {
0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2',
1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2',
2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2',
3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2',
4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2',
5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2',
6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2',
}
DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0
DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1
DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2
DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3
DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4
DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5
DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL'
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = {
0: 'DCIO_UNIPHYA_FBDIV_CLK',
1: 'DCIO_UNIPHYB_FBDIV_CLK',
2: 'DCIO_UNIPHYC_FBDIV_CLK',
3: 'DCIO_UNIPHYD_FBDIV_CLK',
4: 'DCIO_UNIPHYE_FBDIV_CLK',
5: 'DCIO_UNIPHYF_FBDIV_CLK',
6: 'DCIO_UNIPHYG_FBDIV_CLK',
}
DCIO_UNIPHYA_FBDIV_CLK = 0
DCIO_UNIPHYB_FBDIV_CLK = 1
DCIO_UNIPHYC_FBDIV_CLK = 2
DCIO_UNIPHYD_FBDIV_CLK = 3
DCIO_UNIPHYE_FBDIV_CLK = 4
DCIO_UNIPHYF_FBDIV_CLK = 5
DCIO_UNIPHYG_FBDIV_CLK = 6
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL'
DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = {
0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK',
1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK',
2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK',
3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK',
4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK',
5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK',
6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK',
}
DCIO_UNIPHYA_FBDIV_SSC_CLK = 0
DCIO_UNIPHYB_FBDIV_SSC_CLK = 1
DCIO_UNIPHYC_FBDIV_SSC_CLK = 2
DCIO_UNIPHYD_FBDIV_SSC_CLK = 3
DCIO_UNIPHYE_FBDIV_SSC_CLK = 4
DCIO_UNIPHYF_FBDIV_SSC_CLK = 5
DCIO_UNIPHYG_FBDIV_SSC_CLK = 6
DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL'
DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = {
0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK',
1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK',
2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK',
3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK',
4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK',
5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK',
6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK',
}
DCIO_UNIPHYA_TEST_REFDIV_CLK = 0
DCIO_UNIPHYB_TEST_REFDIV_CLK = 1
DCIO_UNIPHYC_TEST_REFDIV_CLK = 2
DCIO_UNIPHYD_TEST_REFDIV_CLK = 3
DCIO_UNIPHYE_TEST_REFDIV_CLK = 4
DCIO_UNIPHYF_TEST_REFDIV_CLK = 5
DCIO_UNIPHYG_TEST_REFDIV_CLK = 6
DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE'
DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE__enumvalues = {
0: 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL',
1: 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP',
}
DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0
DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 1
DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT'
DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = {
0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE',
1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE',
2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP',
3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP',
4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM',
5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM',
}
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 2
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 3
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 4
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 5
DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION'
DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = {
0: 'DCIO_GPU_TIMER_START_0_END_27',
1: 'DCIO_GPU_TIMER_START_1_END_28',
2: 'DCIO_GPU_TIMER_START_2_END_29',
3: 'DCIO_GPU_TIMER_START_3_END_30',
4: 'DCIO_GPU_TIMER_START_4_END_31',
5: 'DCIO_GPU_TIMER_START_6_END_33',
6: 'DCIO_GPU_TIMER_START_8_END_35',
7: 'DCIO_GPU_TIMER_START_10_END_37',
}
DCIO_GPU_TIMER_START_0_END_27 = 0
DCIO_GPU_TIMER_START_1_END_28 = 1
DCIO_GPU_TIMER_START_2_END_29 = 2
DCIO_GPU_TIMER_START_3_END_30 = 3
DCIO_GPU_TIMER_START_4_END_31 = 4
DCIO_GPU_TIMER_START_6_END_33 = 5
DCIO_GPU_TIMER_START_8_END_35 = 6
DCIO_GPU_TIMER_START_10_END_37 = 7
DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL'
DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = {
0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE',
1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1',
2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2',
3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3',
}
DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2
DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3
DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DIO_EXT_VSYNC_MASK'
DCIO_DIO_EXT_VSYNC_MASK__enumvalues = {
0: 'DCIO_EXT_VSYNC_MASK_NONE',
1: 'DCIO_EXT_VSYNC_MASK_PIPE0',
2: 'DCIO_EXT_VSYNC_MASK_PIPE1',
3: 'DCIO_EXT_VSYNC_MASK_PIPE2',
4: 'DCIO_EXT_VSYNC_MASK_PIPE3',
5: 'DCIO_EXT_VSYNC_MASK_PIPE4',
6: 'DCIO_EXT_VSYNC_MASK_PIPE5',
7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE',
}
DCIO_EXT_VSYNC_MASK_NONE = 0
DCIO_EXT_VSYNC_MASK_PIPE0 = 1
DCIO_EXT_VSYNC_MASK_PIPE1 = 2
DCIO_EXT_VSYNC_MASK_PIPE2 = 3
DCIO_EXT_VSYNC_MASK_PIPE3 = 4
DCIO_EXT_VSYNC_MASK_PIPE4 = 5
DCIO_EXT_VSYNC_MASK_PIPE5 = 6
DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7
DCIO_DIO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DIO_OTG_EXT_VSYNC_MUX'
DCIO_DIO_OTG_EXT_VSYNC_MUX__enumvalues = {
0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB',
1: 'DCIO_EXT_VSYNC_MUX_OTG0',
2: 'DCIO_EXT_VSYNC_MUX_OTG1',
3: 'DCIO_EXT_VSYNC_MUX_OTG2',
4: 'DCIO_EXT_VSYNC_MUX_OTG3',
5: 'DCIO_EXT_VSYNC_MUX_OTG4',
6: 'DCIO_EXT_VSYNC_MUX_OTG5',
7: 'DCIO_EXT_VSYNC_MUX_GENERICB',
}
DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0
DCIO_EXT_VSYNC_MUX_OTG0 = 1
DCIO_EXT_VSYNC_MUX_OTG1 = 2
DCIO_EXT_VSYNC_MUX_OTG2 = 3
DCIO_EXT_VSYNC_MUX_OTG3 = 4
DCIO_EXT_VSYNC_MUX_OTG4 = 5
DCIO_EXT_VSYNC_MUX_OTG5 = 6
DCIO_EXT_VSYNC_MUX_GENERICB = 7
DCIO_DIO_OTG_EXT_VSYNC_MUX = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK'
DCIO_DPCS_INTERRUPT_MASK__enumvalues = {
0: 'DCIO_DPCS_INTERRUPT_DISABLE',
1: 'DCIO_DPCS_INTERRUPT_ENABLE',
}
DCIO_DPCS_INTERRUPT_DISABLE = 0
DCIO_DPCS_INTERRUPT_ENABLE = 1
DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE'
DCIO_DPCS_INTERRUPT_TYPE__enumvalues = {
0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED',
1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED',
}
DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0
DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1
DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK'
DCIO_GENLK_CLK_GSL_MASK__enumvalues = {
0: 'DCIO_GENLK_CLK_GSL_MASK_NO',
1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING',
2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO',
}
DCIO_GENLK_CLK_GSL_MASK_NO = 0
DCIO_GENLK_CLK_GSL_MASK_TIMING = 1
DCIO_GENLK_CLK_GSL_MASK_STEREO = 2
DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK'
DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = {
0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO',
1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING',
2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO',
}
DCIO_GENLK_VSYNC_GSL_MASK_NO = 0
DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1
DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2
DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_GSL_SEL'
DCIO_GSL_SEL__enumvalues = {
0: 'DCIO_GSL_SEL_GROUP_0',
1: 'DCIO_GSL_SEL_GROUP_1',
2: 'DCIO_GSL_SEL_GROUP_2',
}
DCIO_GSL_SEL_GROUP_0 = 0
DCIO_GSL_SEL_GROUP_1 = 1
DCIO_GSL_SEL_GROUP_2 = 2
DCIO_GSL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_PHY_HPO_ENC_SRC_SEL'
DCIO_PHY_HPO_ENC_SRC_SEL__enumvalues = {
0: 'HPO_SRC0',
1: 'HPO_SRC_RESERVED',
}
HPO_SRC0 = 0
HPO_SRC_RESERVED = 1
DCIO_PHY_HPO_ENC_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK'
DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = {
0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO',
1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING',
2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO',
}
DCIO_SWAPLOCK_A_GSL_MASK_NO = 0
DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1
DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2
DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK'
DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = {
0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO',
1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING',
2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO',
}
DCIO_SWAPLOCK_B_GSL_MASK_NO = 0
DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1
DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2
DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE'
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = {
0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0',
1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1',
2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2',
3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3',
}
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL'
DCIO_UNIPHY_IMPCAL_SEL__enumvalues = {
0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE',
1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY',
}
DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0
DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1
DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT'
DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = {
0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION',
1: 'DCIO_UNIPHY_CHANNEL_INVERTED',
}
DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0
DCIO_UNIPHY_CHANNEL_INVERTED = 1
DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK'
DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = {
0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW',
1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW',
2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED',
3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED',
}
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3
DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_ALL_PWR_OK'
DCIOCHIP_AUX_ALL_PWR_OK__enumvalues = {
0: 'DCIOCHIP_AUX_ALL_PWR_OK_0',
1: 'DCIOCHIP_AUX_ALL_PWR_OK_1',
}
DCIOCHIP_AUX_ALL_PWR_OK_0 = 0
DCIOCHIP_AUX_ALL_PWR_OK_1 = 1
DCIOCHIP_AUX_ALL_PWR_OK = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_CSEL0P9'
DCIOCHIP_AUX_CSEL0P9__enumvalues = {
0: 'DCIOCHIP_AUX_CSEL_DEC1P0',
1: 'DCIOCHIP_AUX_CSEL_DEC0P9',
}
DCIOCHIP_AUX_CSEL_DEC1P0 = 0
DCIOCHIP_AUX_CSEL_DEC0P9 = 1
DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_CSEL1P1'
DCIOCHIP_AUX_CSEL1P1__enumvalues = {
0: 'DCIOCHIP_AUX_CSEL_INC1P0',
1: 'DCIOCHIP_AUX_CSEL_INC1P1',
}
DCIOCHIP_AUX_CSEL_INC1P0 = 0
DCIOCHIP_AUX_CSEL_INC1P1 = 1
DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL'
DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = {
0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW',
1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0',
2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1',
3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH',
}
DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0
DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1
DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2
DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3
DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_HYS_TUNE'
DCIOCHIP_AUX_HYS_TUNE__enumvalues = {
0: 'DCIOCHIP_AUX_HYS_TUNE_0',
1: 'DCIOCHIP_AUX_HYS_TUNE_1',
2: 'DCIOCHIP_AUX_HYS_TUNE_2',
3: 'DCIOCHIP_AUX_HYS_TUNE_3',
}
DCIOCHIP_AUX_HYS_TUNE_0 = 0
DCIOCHIP_AUX_HYS_TUNE_1 = 1
DCIOCHIP_AUX_HYS_TUNE_2 = 2
DCIOCHIP_AUX_HYS_TUNE_3 = 3
DCIOCHIP_AUX_HYS_TUNE = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_RECEIVER_SEL'
DCIOCHIP_AUX_RECEIVER_SEL__enumvalues = {
0: 'DCIOCHIP_AUX_RECEIVER_SEL_0',
1: 'DCIOCHIP_AUX_RECEIVER_SEL_1',
2: 'DCIOCHIP_AUX_RECEIVER_SEL_2',
3: 'DCIOCHIP_AUX_RECEIVER_SEL_3',
}
DCIOCHIP_AUX_RECEIVER_SEL_0 = 0
DCIOCHIP_AUX_RECEIVER_SEL_1 = 1
DCIOCHIP_AUX_RECEIVER_SEL_2 = 2
DCIOCHIP_AUX_RECEIVER_SEL_3 = 3
DCIOCHIP_AUX_RECEIVER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_RSEL0P9'
DCIOCHIP_AUX_RSEL0P9__enumvalues = {
0: 'DCIOCHIP_AUX_RSEL_DEC1P0',
1: 'DCIOCHIP_AUX_RSEL_DEC0P9',
}
DCIOCHIP_AUX_RSEL_DEC1P0 = 0
DCIOCHIP_AUX_RSEL_DEC0P9 = 1
DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_RSEL1P1'
DCIOCHIP_AUX_RSEL1P1__enumvalues = {
0: 'DCIOCHIP_AUX_RSEL_INC1P0',
1: 'DCIOCHIP_AUX_RSEL_INC1P1',
}
DCIOCHIP_AUX_RSEL_INC1P0 = 0
DCIOCHIP_AUX_RSEL_INC1P1 = 1
DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_SPIKESEL'
DCIOCHIP_AUX_SPIKESEL__enumvalues = {
0: 'DCIOCHIP_AUX_SPIKESEL_50NS',
1: 'DCIOCHIP_AUX_SPIKESEL_10NS',
}
DCIOCHIP_AUX_SPIKESEL_50NS = 0
DCIOCHIP_AUX_SPIKESEL_10NS = 1
DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_VOD_TUNE'
DCIOCHIP_AUX_VOD_TUNE__enumvalues = {
0: 'DCIOCHIP_AUX_VOD_TUNE_0',
1: 'DCIOCHIP_AUX_VOD_TUNE_1',
2: 'DCIOCHIP_AUX_VOD_TUNE_2',
3: 'DCIOCHIP_AUX_VOD_TUNE_3',
}
DCIOCHIP_AUX_VOD_TUNE_0 = 0
DCIOCHIP_AUX_VOD_TUNE_1 = 1
DCIOCHIP_AUX_VOD_TUNE_2 = 2
DCIOCHIP_AUX_VOD_TUNE_3 = 3
DCIOCHIP_AUX_VOD_TUNE = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_GPIO_MASK_EN'
DCIOCHIP_GPIO_MASK_EN__enumvalues = {
0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE',
1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE',
}
DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0
DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1
DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_HPD_SEL'
DCIOCHIP_HPD_SEL__enumvalues = {
0: 'DCIOCHIP_HPD_SEL_ASYNC',
1: 'DCIOCHIP_HPD_SEL_CLOCKED',
}
DCIOCHIP_HPD_SEL_ASYNC = 0
DCIOCHIP_HPD_SEL_CLOCKED = 1
DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_I2C_COMPSEL'
DCIOCHIP_I2C_COMPSEL__enumvalues = {
0: 'DCIOCHIP_I2C_REC_SCHMIT',
1: 'DCIOCHIP_I2C_REC_COMPARATOR',
}
DCIOCHIP_I2C_REC_SCHMIT = 0
DCIOCHIP_I2C_REC_COMPARATOR = 1
DCIOCHIP_I2C_COMPSEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_I2C_FALLSLEWSEL'
DCIOCHIP_I2C_FALLSLEWSEL__enumvalues = {
0: 'DCIOCHIP_I2C_FALLSLEWSEL_00',
1: 'DCIOCHIP_I2C_FALLSLEWSEL_01',
2: 'DCIOCHIP_I2C_FALLSLEWSEL_10',
3: 'DCIOCHIP_I2C_FALLSLEWSEL_11',
}
DCIOCHIP_I2C_FALLSLEWSEL_00 = 0
DCIOCHIP_I2C_FALLSLEWSEL_01 = 1
DCIOCHIP_I2C_FALLSLEWSEL_10 = 2
DCIOCHIP_I2C_FALLSLEWSEL_11 = 3
DCIOCHIP_I2C_FALLSLEWSEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_I2C_RECEIVER_SEL'
DCIOCHIP_I2C_RECEIVER_SEL__enumvalues = {
0: 'DCIOCHIP_I2C_RECEIVER_SEL_0',
1: 'DCIOCHIP_I2C_RECEIVER_SEL_1',
2: 'DCIOCHIP_I2C_RECEIVER_SEL_2',
3: 'DCIOCHIP_I2C_RECEIVER_SEL_3',
}
DCIOCHIP_I2C_RECEIVER_SEL_0 = 0
DCIOCHIP_I2C_RECEIVER_SEL_1 = 1
DCIOCHIP_I2C_RECEIVER_SEL_2 = 2
DCIOCHIP_I2C_RECEIVER_SEL_3 = 3
DCIOCHIP_I2C_RECEIVER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_I2C_VPH_1V2_EN'
DCIOCHIP_I2C_VPH_1V2_EN__enumvalues = {
0: 'DCIOCHIP_I2C_VPH_1V2_EN_0',
1: 'DCIOCHIP_I2C_VPH_1V2_EN_1',
}
DCIOCHIP_I2C_VPH_1V2_EN_0 = 0
DCIOCHIP_I2C_VPH_1V2_EN_1 = 1
DCIOCHIP_I2C_VPH_1V2_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_INVERT'
DCIOCHIP_INVERT__enumvalues = {
0: 'DCIOCHIP_POL_NON_INVERT',
1: 'DCIOCHIP_POL_INVERT',
}
DCIOCHIP_POL_NON_INVERT = 0
DCIOCHIP_POL_INVERT = 1
DCIOCHIP_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_MASK'
DCIOCHIP_MASK__enumvalues = {
0: 'DCIOCHIP_MASK_DISABLE',
1: 'DCIOCHIP_MASK_ENABLE',
}
DCIOCHIP_MASK_DISABLE = 0
DCIOCHIP_MASK_ENABLE = 1
DCIOCHIP_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_PAD_MODE'
DCIOCHIP_PAD_MODE__enumvalues = {
0: 'DCIOCHIP_PAD_MODE_DDC',
1: 'DCIOCHIP_PAD_MODE_DP',
}
DCIOCHIP_PAD_MODE_DDC = 0
DCIOCHIP_PAD_MODE_DP = 1
DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_PD_EN'
DCIOCHIP_PD_EN__enumvalues = {
0: 'DCIOCHIP_PD_EN_NOTALLOW',
1: 'DCIOCHIP_PD_EN_ALLOW',
}
DCIOCHIP_PD_EN_NOTALLOW = 0
DCIOCHIP_PD_EN_ALLOW = 1
DCIOCHIP_PD_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL'
DCIOCHIP_REF_27_SRC_SEL__enumvalues = {
0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER',
1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER',
2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS',
3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS',
}
DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1
DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3
DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE'
PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = {
0: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE',
1: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE',
}
PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0
PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1
PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN'
PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__enumvalues = {
0: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL',
1: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM',
}
PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0
PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 1
PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT'
PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT__enumvalues = {
0: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL',
1: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1',
2: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2',
3: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3',
}
PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0
PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 1
PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 2
PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 3
PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN'
PWRSEQ_BL_PWM_CNTL_BL_PWM_EN__enumvalues = {
0: 'PWRSEQ_BL_PWM_DISABLE',
1: 'PWRSEQ_BL_PWM_ENABLE',
}
PWRSEQ_BL_PWM_DISABLE = 0
PWRSEQ_BL_PWM_ENABLE = 1
PWRSEQ_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN'
PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = {
0: 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE',
1: 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE',
}
PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0
PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 1
PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN'
PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = {
0: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE',
1: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE',
}
PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0
PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1
PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN'
PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = {
0: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM',
1: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM',
}
PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0
PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1
PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_GRP1_REG_LOCK'
PWRSEQ_BL_PWM_GRP1_REG_LOCK__enumvalues = {
0: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE',
1: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE',
}
PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0
PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 1
PWRSEQ_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START'
PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = {
0: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE',
1: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE',
}
PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0
PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1
PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_GPIO_MASK_EN'
PWRSEQ_GPIO_MASK_EN__enumvalues = {
0: 'PWRSEQ_GPIO_MASK_EN_HARDWARE',
1: 'PWRSEQ_GPIO_MASK_EN_SOFTWARE',
}
PWRSEQ_GPIO_MASK_EN_HARDWARE = 0
PWRSEQ_GPIO_MASK_EN_SOFTWARE = 1
PWRSEQ_GPIO_MASK_EN = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON'
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON__enumvalues = {
0: 'PWRSEQ_PANEL_BLON_OFF',
1: 'PWRSEQ_PANEL_BLON_ON',
}
PWRSEQ_PANEL_BLON_OFF = 0
PWRSEQ_PANEL_BLON_ON = 1
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL'
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL__enumvalues = {
0: 'PWRSEQ_PANEL_BLON_POL_NON_INVERT',
1: 'PWRSEQ_PANEL_BLON_POL_INVERT',
}
PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0
PWRSEQ_PANEL_BLON_POL_INVERT = 1
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON'
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON__enumvalues = {
0: 'PWRSEQ_PANEL_DIGON_OFF',
1: 'PWRSEQ_PANEL_DIGON_ON',
}
PWRSEQ_PANEL_DIGON_OFF = 0
PWRSEQ_PANEL_DIGON_ON = 1
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL'
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL__enumvalues = {
0: 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT',
1: 'PWRSEQ_PANEL_DIGON_POL_INVERT',
}
PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0
PWRSEQ_PANEL_DIGON_POL_INVERT = 1
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL'
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL__enumvalues = {
0: 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT',
1: 'PWRSEQ_PANEL_SYNCEN_POL_INVERT',
}
PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0
PWRSEQ_PANEL_SYNCEN_POL_INVERT = 1
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE'
PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE__enumvalues = {
0: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF',
1: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON',
}
PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0
PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 1
PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN'
PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN__enumvalues = {
0: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON',
1: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE',
}
PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0
PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 1
PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum
# values for enumeration 'AZ_CORB_SIZE'
AZ_CORB_SIZE__enumvalues = {
0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED',
1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED',
2: 'AZ_CORB_SIZE_256ENTRIES',
3: 'AZ_CORB_SIZE_RESERVED',
}
AZ_CORB_SIZE_2ENTRIES_RESERVED = 0
AZ_CORB_SIZE_16ENTRIES_RESERVED = 1
AZ_CORB_SIZE_256ENTRIES = 2
AZ_CORB_SIZE_RESERVED = 3
AZ_CORB_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'AZ_GLOBAL_CAPABILITIES'
AZ_GLOBAL_CAPABILITIES__enumvalues = {
0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED',
1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED',
}
AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0
AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1
AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum
# values for enumeration 'AZ_RIRB_SIZE'
AZ_RIRB_SIZE__enumvalues = {
0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED',
1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED',
2: 'AZ_RIRB_SIZE_256ENTRIES',
3: 'AZ_RIRB_SIZE_UNDEFINED',
}
AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0
AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1
AZ_RIRB_SIZE_256ENTRIES = 2
AZ_RIRB_SIZE_UNDEFINED = 3
AZ_RIRB_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET'
AZ_RIRB_WRITE_POINTER_RESET__enumvalues = {
0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET',
1: 'AZ_RIRB_WRITE_POINTER_DO_RESET',
}
AZ_RIRB_WRITE_POINTER_NOT_RESET = 0
AZ_RIRB_WRITE_POINTER_DO_RESET = 1
AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum
# values for enumeration 'AZ_STATE_CHANGE_STATUS'
AZ_STATE_CHANGE_STATUS__enumvalues = {
0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT',
1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT',
}
AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0
AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1
AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'CORB_READ_POINTER_RESET'
CORB_READ_POINTER_RESET__enumvalues = {
0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET',
1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET',
}
CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0
CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1
CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE'
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = {
0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE',
1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE',
}
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL'
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = {
0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE',
1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE',
}
GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED'
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = {
0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED',
1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED',
}
GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS'
GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = {
0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET',
1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET',
}
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1
GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED'
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = {
0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED',
1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED',
}
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum
# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE'
GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = {
0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE',
1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE',
}
ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0
ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1
GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum
# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET'
GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = {
0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET',
1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET',
}
CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0
CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1
GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum
# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL'
GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = {
0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED',
1: 'FLUSH_CONTROL_FLUSH_STARTED',
}
FLUSH_CONTROL_FLUSH_NOT_STARTED = 0
FLUSH_CONTROL_FLUSH_STARTED = 1
GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS'
GLOBAL_STATUS_FLUSH_STATUS__enumvalues = {
0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED',
1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED',
}
GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0
GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1
GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY'
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = {
0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY',
1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY',
}
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum
# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID'
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = {
0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID',
1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID',
}
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum
# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL'
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = {
0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED',
1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED',
}
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL'
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = {
0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED',
1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED',
}
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_0_SYNCHRONIZATION'
STREAM_0_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_10_SYNCHRONIZATION'
STREAM_10_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_11_SYNCHRONIZATION'
STREAM_11_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_12_SYNCHRONIZATION'
STREAM_12_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_13_SYNCHRONIZATION'
STREAM_13_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_14_SYNCHRONIZATION'
STREAM_14_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_15_SYNCHRONIZATION'
STREAM_15_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_1_SYNCHRONIZATION'
STREAM_1_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_2_SYNCHRONIZATION'
STREAM_2_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_3_SYNCHRONIZATION'
STREAM_3_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_4_SYNCHRONIZATION'
STREAM_4_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_5_SYNCHRONIZATION'
STREAM_5_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_6_SYNCHRONIZATION'
STREAM_6_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_7_SYNCHRONIZATION'
STREAM_7_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_8_SYNCHRONIZATION'
STREAM_8_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_9_SYNCHRONIZATION'
STREAM_9_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16',
2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20',
3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24',
4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2',
2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3',
3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4',
4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5',
5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6',
6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7',
7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8',
8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE'
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1',
2: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2',
3: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3',
4: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4',
5: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5',
6: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6',
7: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7',
8: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8',
9: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9',
10: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10',
11: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11',
12: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12',
13: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13',
14: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14',
15: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15',
}
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 1
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 2
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 3
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 4
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 5
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 6
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 7
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 8
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 9
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 10
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 11
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 12
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 13
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 14
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 15
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT'
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN',
}
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE'
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED',
}
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE'
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN',
}
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET'
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = {
0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET',
1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC',
}
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_DIS_CTRL'
MEM_PWR_DIS_CTRL__enumvalues = {
0: 'ENABLE_MEM_PWR_CTRL',
1: 'DISABLE_MEM_PWR_CTRL',
}
ENABLE_MEM_PWR_CTRL = 0
DISABLE_MEM_PWR_CTRL = 1
MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_FORCE_CTRL'
MEM_PWR_FORCE_CTRL__enumvalues = {
0: 'NO_FORCE_REQUEST',
1: 'FORCE_LIGHT_SLEEP_REQUEST',
2: 'FORCE_DEEP_SLEEP_REQUEST',
3: 'FORCE_SHUT_DOWN_REQUEST',
}
NO_FORCE_REQUEST = 0
FORCE_LIGHT_SLEEP_REQUEST = 1
FORCE_DEEP_SLEEP_REQUEST = 2
FORCE_SHUT_DOWN_REQUEST = 3
MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_FORCE_CTRL2'
MEM_PWR_FORCE_CTRL2__enumvalues = {
0: 'NO_FORCE_REQ',
1: 'FORCE_LIGHT_SLEEP_REQ',
}
NO_FORCE_REQ = 0
FORCE_LIGHT_SLEEP_REQ = 1
MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_SEL_CTRL'
MEM_PWR_SEL_CTRL__enumvalues = {
0: 'DYNAMIC_SHUT_DOWN_ENABLE',
1: 'DYNAMIC_DEEP_SLEEP_ENABLE',
2: 'DYNAMIC_LIGHT_SLEEP_ENABLE',
}
DYNAMIC_SHUT_DOWN_ENABLE = 0
DYNAMIC_DEEP_SLEEP_ENABLE = 1
DYNAMIC_LIGHT_SLEEP_ENABLE = 2
MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_SEL_CTRL2'
MEM_PWR_SEL_CTRL2__enumvalues = {
0: 'DYNAMIC_DEEP_SLEEP_EN',
1: 'DYNAMIC_LIGHT_SLEEP_EN',
}
DYNAMIC_DEEP_SLEEP_EN = 0
DYNAMIC_LIGHT_SLEEP_EN = 1
MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum
# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY'
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = {
0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL',
1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6',
2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5',
3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4',
4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3',
5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2',
6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1',
7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0',
}
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum
# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY'
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = {
0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL',
1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6',
2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5',
3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4',
4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3',
5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2',
6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1',
7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0',
}
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16',
2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20',
3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24',
4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2',
2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3',
3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4',
4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5',
5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6',
6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7',
7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8',
8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET'
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = {
0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET',
1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET',
}
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum
# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL'
AZ_LATENCY_COUNTER_CONTROL__enumvalues = {
0: 'AZ_LATENCY_COUNTER_NO_RESET',
1: 'AZ_LATENCY_COUNTER_RESET_DONE',
}
AZ_LATENCY_COUNTER_NO_RESET = 0
AZ_LATENCY_COUNTER_RESET_DONE = 1
AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16',
2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20',
3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24',
4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2',
2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3',
3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4',
4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5',
5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6',
6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7',
7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8',
8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED',
9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED',
10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED',
11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED',
12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED',
13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED',
14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED',
15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED',
9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE'
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE',
1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE',
}
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE'
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY',
1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY',
}
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED',
9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED',
9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED',
9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_BITS_PER_COMPONENT_ENUM'
DSCC_BITS_PER_COMPONENT_ENUM__enumvalues = {
8: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT',
10: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT',
12: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT',
}
DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8
DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10
DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12
DSCC_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_DSC_VERSION_MAJOR_ENUM'
DSCC_DSC_VERSION_MAJOR_ENUM__enumvalues = {
1: 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION',
}
DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 1
DSCC_DSC_VERSION_MAJOR_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_DSC_VERSION_MINOR_ENUM'
DSCC_DSC_VERSION_MINOR_ENUM__enumvalues = {
1: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION',
2: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION',
}
DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 1
DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 2
DSCC_DSC_VERSION_MINOR_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_ENABLE_ENUM'
DSCC_ENABLE_ENUM__enumvalues = {
0: 'DSCC_ENABLE_ENUM_DISABLED',
1: 'DSCC_ENABLE_ENUM_ENABLED',
}
DSCC_ENABLE_ENUM_DISABLED = 0
DSCC_ENABLE_ENUM_ENABLED = 1
DSCC_ENABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_ICH_RESET_ENUM'
DSCC_ICH_RESET_ENUM__enumvalues = {
1: 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET',
2: 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET',
4: 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET',
8: 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET',
}
DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 1
DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 2
DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 4
DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 8
DSCC_ICH_RESET_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_LINEBUF_DEPTH_ENUM'
DSCC_LINEBUF_DEPTH_ENUM__enumvalues = {
8: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT',
9: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT',
10: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT',
11: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT',
12: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT',
13: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT',
}
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 8
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 9
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 10
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 11
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 12
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 13
DSCC_LINEBUF_DEPTH_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_MEM_PWR_DIS_ENUM'
DSCC_MEM_PWR_DIS_ENUM__enumvalues = {
0: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN',
1: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS',
}
DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0
DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 1
DSCC_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_MEM_PWR_FORCE_ENUM'
DSCC_MEM_PWR_FORCE_ENUM__enumvalues = {
0: 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST',
1: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST',
3: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST',
}
DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0
DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 1
DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 2
DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 3
DSCC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'POWER_STATE_ENUM'
POWER_STATE_ENUM__enumvalues = {
0: 'POWER_STATE_ENUM_ON',
1: 'POWER_STATE_ENUM_LS',
2: 'POWER_STATE_ENUM_DS',
3: 'POWER_STATE_ENUM_SD',
}
POWER_STATE_ENUM_ON = 0
POWER_STATE_ENUM_LS = 1
POWER_STATE_ENUM_DS = 2
POWER_STATE_ENUM_SD = 3
POWER_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCCIF_BITS_PER_COMPONENT_ENUM'
DSCCIF_BITS_PER_COMPONENT_ENUM__enumvalues = {
8: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT',
10: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT',
12: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT',
}
DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8
DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10
DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12
DSCCIF_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCCIF_ENABLE_ENUM'
DSCCIF_ENABLE_ENUM__enumvalues = {
0: 'DSCCIF_ENABLE_ENUM_DISABLED',
1: 'DSCCIF_ENABLE_ENUM_ENABLED',
}
DSCCIF_ENABLE_ENUM_DISABLED = 0
DSCCIF_ENABLE_ENUM_ENABLED = 1
DSCCIF_ENABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM'
DSCCIF_INPUT_PIXEL_FORMAT_ENUM__enumvalues = {
0: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB',
1: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444',
2: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422',
3: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422',
4: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420',
}
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 1
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 2
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 3
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 4
DSCCIF_INPUT_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CLOCK_GATING_DISABLE_ENUM'
CLOCK_GATING_DISABLE_ENUM__enumvalues = {
0: 'CLOCK_GATING_DISABLE_ENUM_ENABLED',
1: 'CLOCK_GATING_DISABLE_ENUM_DISABLED',
}
CLOCK_GATING_DISABLE_ENUM_ENABLED = 0
CLOCK_GATING_DISABLE_ENUM_DISABLED = 1
CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'ENABLE_ENUM'
ENABLE_ENUM__enumvalues = {
0: 'ENABLE_ENUM_DISABLED',
1: 'ENABLE_ENUM_ENABLED',
}
ENABLE_ENUM_DISABLED = 0
ENABLE_ENUM_ENABLED = 1
ENABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'TEST_CLOCK_MUX_SELECT_ENUM'
TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = {
0: 'TEST_CLOCK_MUX_SELECT_DISPCLK_P',
1: 'TEST_CLOCK_MUX_SELECT_DISPCLK_G',
2: 'TEST_CLOCK_MUX_SELECT_DISPCLK_R',
3: 'TEST_CLOCK_MUX_SELECT_DSCCLK_P',
4: 'TEST_CLOCK_MUX_SELECT_DSCCLK_G',
5: 'TEST_CLOCK_MUX_SELECT_DSCCLK_R',
6: 'TEST_CLOCK_MUX_SELECT_DSCCLK_D',
}
TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0
TEST_CLOCK_MUX_SELECT_DISPCLK_G = 1
TEST_CLOCK_MUX_SELECT_DISPCLK_R = 2
TEST_CLOCK_MUX_SELECT_DSCCLK_P = 3
TEST_CLOCK_MUX_SELECT_DSCCLK_G = 4
TEST_CLOCK_MUX_SELECT_DSCCLK_R = 5
TEST_CLOCK_MUX_SELECT_DSCCLK_D = 6
TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_CRC_CONT_EN_ENUM'
DWB_CRC_CONT_EN_ENUM__enumvalues = {
0: 'DWB_CRC_CONT_EN_ONE_SHOT',
1: 'DWB_CRC_CONT_EN_CONT',
}
DWB_CRC_CONT_EN_ONE_SHOT = 0
DWB_CRC_CONT_EN_CONT = 1
DWB_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_CRC_SRC_SEL_ENUM'
DWB_CRC_SRC_SEL_ENUM__enumvalues = {
0: 'DWB_CRC_SRC_SEL_DWB_IN',
1: 'DWB_CRC_SRC_SEL_OGAM_OUT',
2: 'DWB_CRC_SRC_SEL_DWB_OUT',
}
DWB_CRC_SRC_SEL_DWB_IN = 0
DWB_CRC_SRC_SEL_OGAM_OUT = 1
DWB_CRC_SRC_SEL_DWB_OUT = 2
DWB_CRC_SRC_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM'
DWB_DATA_OVERFLOW_INT_TYPE_ENUM__enumvalues = {
0: 'DWB_DATA_OVERFLOW_INT_TYPE_0',
1: 'DWB_DATA_OVERFLOW_INT_TYPE_1',
}
DWB_DATA_OVERFLOW_INT_TYPE_0 = 0
DWB_DATA_OVERFLOW_INT_TYPE_1 = 1
DWB_DATA_OVERFLOW_INT_TYPE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_DATA_OVERFLOW_TYPE_ENUM'
DWB_DATA_OVERFLOW_TYPE_ENUM__enumvalues = {
0: 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW',
1: 'DWB_DATA_OVERFLOW_TYPE_BUFFER',
2: 'DWB_DATA_OVERFLOW_TYPE_VUPDATE',
3: 'DWB_DATA_OVERFLOW_TYPE_VREADY',
}
DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0
DWB_DATA_OVERFLOW_TYPE_BUFFER = 1
DWB_DATA_OVERFLOW_TYPE_VUPDATE = 2
DWB_DATA_OVERFLOW_TYPE_VREADY = 3
DWB_DATA_OVERFLOW_TYPE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_DEBUG_SEL_ENUM'
DWB_DEBUG_SEL_ENUM__enumvalues = {
0: 'DWB_DEBUG_SEL_FC',
1: 'DWB_DEBUG_SEL_RESERVED',
2: 'DWB_DEBUG_SEL_DWBCP',
3: 'DWB_DEBUG_SEL_PERFMON',
}
DWB_DEBUG_SEL_FC = 0
DWB_DEBUG_SEL_RESERVED = 1
DWB_DEBUG_SEL_DWBCP = 2
DWB_DEBUG_SEL_PERFMON = 3
DWB_DEBUG_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_MEM_PWR_FORCE_ENUM'
DWB_MEM_PWR_FORCE_ENUM__enumvalues = {
0: 'DWB_MEM_PWR_FORCE_DIS',
1: 'DWB_MEM_PWR_FORCE_LS',
2: 'DWB_MEM_PWR_FORCE_DS',
3: 'DWB_MEM_PWR_FORCE_SD',
}
DWB_MEM_PWR_FORCE_DIS = 0
DWB_MEM_PWR_FORCE_LS = 1
DWB_MEM_PWR_FORCE_DS = 2
DWB_MEM_PWR_FORCE_SD = 3
DWB_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_MEM_PWR_STATE_ENUM'
DWB_MEM_PWR_STATE_ENUM__enumvalues = {
0: 'DWB_MEM_PWR_STATE_ON',
1: 'DWB_MEM_PWR_STATE_LS',
2: 'DWB_MEM_PWR_STATE_DS',
3: 'DWB_MEM_PWR_STATE_SD',
}
DWB_MEM_PWR_STATE_ON = 0
DWB_MEM_PWR_STATE_LS = 1
DWB_MEM_PWR_STATE_DS = 2
DWB_MEM_PWR_STATE_SD = 3
DWB_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_TEST_CLK_SEL_ENUM'
DWB_TEST_CLK_SEL_ENUM__enumvalues = {
0: 'DWB_TEST_CLK_SEL_R',
1: 'DWB_TEST_CLK_SEL_G',
2: 'DWB_TEST_CLK_SEL_P',
}
DWB_TEST_CLK_SEL_R = 0
DWB_TEST_CLK_SEL_G = 1
DWB_TEST_CLK_SEL_P = 2
DWB_TEST_CLK_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'FC_EYE_SELECTION_ENUM'
FC_EYE_SELECTION_ENUM__enumvalues = {
0: 'FC_EYE_SELECTION_STEREO_DIS',
1: 'FC_EYE_SELECTION_LEFT_EYE',
2: 'FC_EYE_SELECTION_RIGHT_EYE',
}
FC_EYE_SELECTION_STEREO_DIS = 0
FC_EYE_SELECTION_LEFT_EYE = 1
FC_EYE_SELECTION_RIGHT_EYE = 2
FC_EYE_SELECTION_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'FC_FRAME_CAPTURE_RATE_ENUM'
FC_FRAME_CAPTURE_RATE_ENUM__enumvalues = {
0: 'FC_FRAME_CAPTURE_RATE_FULL',
1: 'FC_FRAME_CAPTURE_RATE_HALF',
2: 'FC_FRAME_CAPTURE_RATE_THIRD',
3: 'FC_FRAME_CAPTURE_RATE_QUARTER',
}
FC_FRAME_CAPTURE_RATE_FULL = 0
FC_FRAME_CAPTURE_RATE_HALF = 1
FC_FRAME_CAPTURE_RATE_THIRD = 2
FC_FRAME_CAPTURE_RATE_QUARTER = 3
FC_FRAME_CAPTURE_RATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'FC_STEREO_EYE_POLARITY_ENUM'
FC_STEREO_EYE_POLARITY_ENUM__enumvalues = {
0: 'FC_STEREO_EYE_POLARITY_LEFT',
1: 'FC_STEREO_EYE_POLARITY_RIGHT',
}
FC_STEREO_EYE_POLARITY_LEFT = 0
FC_STEREO_EYE_POLARITY_RIGHT = 1
FC_STEREO_EYE_POLARITY_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM'
DWB_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = {
0: 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13',
1: 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12',
}
DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0
DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1
DWB_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_GAMUT_REMAP_MODE_ENUM'
DWB_GAMUT_REMAP_MODE_ENUM__enumvalues = {
0: 'DWB_GAMUT_REMAP_MODE_BYPASS',
1: 'DWB_GAMUT_REMAP_MODE_COEF_A',
2: 'DWB_GAMUT_REMAP_MODE_COEF_B',
3: 'DWB_GAMUT_REMAP_MODE_RESERVED',
}
DWB_GAMUT_REMAP_MODE_BYPASS = 0
DWB_GAMUT_REMAP_MODE_COEF_A = 1
DWB_GAMUT_REMAP_MODE_COEF_B = 2
DWB_GAMUT_REMAP_MODE_RESERVED = 3
DWB_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_LUT_NUM_SEG'
DWB_LUT_NUM_SEG__enumvalues = {
0: 'DWB_SEGMENTS_1',
1: 'DWB_SEGMENTS_2',
2: 'DWB_SEGMENTS_4',
3: 'DWB_SEGMENTS_8',
4: 'DWB_SEGMENTS_16',
5: 'DWB_SEGMENTS_32',
6: 'DWB_SEGMENTS_64',
7: 'DWB_SEGMENTS_128',
}
DWB_SEGMENTS_1 = 0
DWB_SEGMENTS_2 = 1
DWB_SEGMENTS_4 = 2
DWB_SEGMENTS_8 = 3
DWB_SEGMENTS_16 = 4
DWB_SEGMENTS_32 = 5
DWB_SEGMENTS_64 = 6
DWB_SEGMENTS_128 = 7
DWB_LUT_NUM_SEG = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_LUT_CONFIG_MODE_ENUM'
DWB_OGAM_LUT_CONFIG_MODE_ENUM__enumvalues = {
0: 'DWB_OGAM_LUT_CONFIG_MODE_DIFF',
1: 'DWB_OGAM_LUT_CONFIG_MODE_SAME',
}
DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0
DWB_OGAM_LUT_CONFIG_MODE_SAME = 1
DWB_OGAM_LUT_CONFIG_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_LUT_HOST_SEL_ENUM'
DWB_OGAM_LUT_HOST_SEL_ENUM__enumvalues = {
0: 'DWB_OGAM_LUT_HOST_SEL_RAMA',
1: 'DWB_OGAM_LUT_HOST_SEL_RAMB',
}
DWB_OGAM_LUT_HOST_SEL_RAMA = 0
DWB_OGAM_LUT_HOST_SEL_RAMB = 1
DWB_OGAM_LUT_HOST_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM'
DWB_OGAM_LUT_READ_COLOR_SEL_ENUM__enumvalues = {
0: 'DWB_OGAM_LUT_READ_COLOR_SEL_B',
1: 'DWB_OGAM_LUT_READ_COLOR_SEL_G',
2: 'DWB_OGAM_LUT_READ_COLOR_SEL_R',
3: 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED',
}
DWB_OGAM_LUT_READ_COLOR_SEL_B = 0
DWB_OGAM_LUT_READ_COLOR_SEL_G = 1
DWB_OGAM_LUT_READ_COLOR_SEL_R = 2
DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 3
DWB_OGAM_LUT_READ_COLOR_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_LUT_READ_DBG_ENUM'
DWB_OGAM_LUT_READ_DBG_ENUM__enumvalues = {
0: 'DWB_OGAM_LUT_READ_DBG_DISABLE',
1: 'DWB_OGAM_LUT_READ_DBG_ENABLE',
}
DWB_OGAM_LUT_READ_DBG_DISABLE = 0
DWB_OGAM_LUT_READ_DBG_ENABLE = 1
DWB_OGAM_LUT_READ_DBG_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_MODE_ENUM'
DWB_OGAM_MODE_ENUM__enumvalues = {
0: 'DWB_OGAM_MODE_BYPASS',
1: 'DWB_OGAM_MODE_RESERVED',
2: 'DWB_OGAM_MODE_RAM_LUT_ENABLED',
}
DWB_OGAM_MODE_BYPASS = 0
DWB_OGAM_MODE_RESERVED = 1
DWB_OGAM_MODE_RAM_LUT_ENABLED = 2
DWB_OGAM_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_PWL_DISABLE_ENUM'
DWB_OGAM_PWL_DISABLE_ENUM__enumvalues = {
0: 'DWB_OGAM_PWL_DISABLE_FALSE',
1: 'DWB_OGAM_PWL_DISABLE_TRUE',
}
DWB_OGAM_PWL_DISABLE_FALSE = 0
DWB_OGAM_PWL_DISABLE_TRUE = 1
DWB_OGAM_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_SELECT_ENUM'
DWB_OGAM_SELECT_ENUM__enumvalues = {
0: 'DWB_OGAM_SELECT_A',
1: 'DWB_OGAM_SELECT_B',
}
DWB_OGAM_SELECT_A = 0
DWB_OGAM_SELECT_B = 1
DWB_OGAM_SELECT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN'
RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN__enumvalues = {
0: 'RDPCS_EXT_REFCLK_DISABLE',
1: 'RDPCS_EXT_REFCLK_ENABLE',
}
RDPCS_EXT_REFCLK_DISABLE = 0
RDPCS_EXT_REFCLK_ENABLE = 1
RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON'
RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON__enumvalues = {
0: 'RDPCS_OCLACLK_CLOCK_OFF',
1: 'RDPCS_OCLACLK_CLOCK_ON',
}
RDPCS_OCLACLK_CLOCK_OFF = 0
RDPCS_OCLACLK_CLOCK_ON = 1
RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN'
RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN__enumvalues = {
0: 'RDPCS_OCLACLK_DISABLE',
1: 'RDPCS_OCLACLK_ENABLE',
}
RDPCS_OCLACLK_DISABLE = 0
RDPCS_OCLACLK_ENABLE = 1
RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS'
RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS__enumvalues = {
0: 'RDPCS_OCLACLK_GATE_ENABLE',
1: 'RDPCS_OCLACLK_GATE_DISABLE',
}
RDPCS_OCLACLK_GATE_ENABLE = 0
RDPCS_OCLACLK_GATE_DISABLE = 1
RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON'
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON__enumvalues = {
0: 'RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF',
1: 'RDPCS_SYMCLK_SRAMCLK_CLOCK_ON',
}
RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF = 0
RDPCS_SYMCLK_SRAMCLK_CLOCK_ON = 1
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN'
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN__enumvalues = {
0: 'RDPCS_SRAMCLK_DISABLE',
1: 'RDPCS_SRAMCLK_ENABLE',
}
RDPCS_SRAMCLK_DISABLE = 0
RDPCS_SRAMCLK_ENABLE = 1
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS'
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS__enumvalues = {
0: 'RDPCS_SRAMCLK_GATE_ENABLE',
1: 'RDPCS_SRAMCLK_GATE_DISABLE',
}
RDPCS_SRAMCLK_GATE_ENABLE = 0
RDPCS_SRAMCLK_GATE_DISABLE = 1
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS'
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS__enumvalues = {
0: 'RDPCS_SRAMCLK_NOT_PASS',
1: 'RDPCS_SRAMCLK_PASS',
}
RDPCS_SRAMCLK_NOT_PASS = 0
RDPCS_SRAMCLK_PASS = 1
RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON'
RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON__enumvalues = {
0: 'RDPCS_TX_CLK_CLOCK_OFF',
1: 'RDPCS_TX_CLK_CLOCK_ON',
}
RDPCS_TX_CLK_CLOCK_OFF = 0
RDPCS_TX_CLK_CLOCK_ON = 1
RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN'
RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN__enumvalues = {
0: 'RDPCS_TX_CLK_DISABLE',
1: 'RDPCS_TX_CLK_ENABLE',
}
RDPCS_TX_CLK_DISABLE = 0
RDPCS_TX_CLK_ENABLE = 1
RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS'
RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS__enumvalues = {
0: 'RDPCS_TX_CLK_GATE_ENABLE',
1: 'RDPCS_TX_CLK_GATE_DISABLE',
}
RDPCS_TX_CLK_GATE_ENABLE = 0
RDPCS_TX_CLK_GATE_DISABLE = 1
RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CLOCK_CNTL_TX_CLK_EN'
RDPCSTX_CLOCK_CNTL_TX_CLK_EN__enumvalues = {
0: 'RDPCS_EXT_REFCLK_EN_DISABLE',
1: 'RDPCS_EXT_REFCLK_EN_ENABLE',
}
RDPCS_EXT_REFCLK_EN_DISABLE = 0
RDPCS_EXT_REFCLK_EN_ENABLE = 1
RDPCSTX_CLOCK_CNTL_TX_CLK_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET'
RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET__enumvalues = {
0: 'RDPCS_CBUS_SOFT_RESET_DISABLE',
1: 'RDPCS_CBUS_SOFT_RESET_ENABLE',
}
RDPCS_CBUS_SOFT_RESET_DISABLE = 0
RDPCS_CBUS_SOFT_RESET_ENABLE = 1
RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET'
RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET__enumvalues = {
0: 'RDPCS_SRAM_SRAM_RESET_DISABLE',
1: 'RDPCS_SRAM_SRAM_RESET_ENABLE',
}
RDPCS_SRAM_SRAM_RESET_DISABLE = 0
RDPCS_SRAM_SRAM_RESET_ENABLE = 1
RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_FIFO_EN'
RDPCSTX_CNTL_RDPCS_TX_FIFO_EN__enumvalues = {
0: 'RDPCS_TX_FIFO_DISABLE',
1: 'RDPCS_TX_FIFO_ENABLE',
}
RDPCS_TX_FIFO_DISABLE = 0
RDPCS_TX_FIFO_ENABLE = 1
RDPCSTX_CNTL_RDPCS_TX_FIFO_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN'
RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN__enumvalues = {
0: 'RDPCS_TX_FIFO_LANE_DISABLE',
1: 'RDPCS_TX_FIFO_LANE_ENABLE',
}
RDPCS_TX_FIFO_LANE_DISABLE = 0
RDPCS_TX_FIFO_LANE_ENABLE = 1
RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET'
RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET__enumvalues = {
0: 'RDPCS_TX_SOFT_RESET_DISABLE',
1: 'RDPCS_TX_SOFT_RESET_ENABLE',
}
RDPCS_TX_SOFT_RESET_DISABLE = 0
RDPCS_TX_SOFT_RESET_ENABLE = 1
RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_FIFO_EMPTY'
RDPCSTX_FIFO_EMPTY__enumvalues = {
0: 'RDPCSTX_FIFO_NOT_EMPTY',
1: 'RDPCSTX_FIFO_IS_EMPTY',
}
RDPCSTX_FIFO_NOT_EMPTY = 0
RDPCSTX_FIFO_IS_EMPTY = 1
RDPCSTX_FIFO_EMPTY = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_FIFO_FULL'
RDPCSTX_FIFO_FULL__enumvalues = {
0: 'RDPCSTX_FIFO_NOT_FULL',
1: 'RDPCSTX_FIFO_IS_FULL',
}
RDPCSTX_FIFO_NOT_FULL = 0
RDPCSTX_FIFO_IS_FULL = 1
RDPCSTX_FIFO_FULL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE'
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE__enumvalues = {
0: 'RDPCS_DPALT_4LANE_TOGGLE_2LANE',
1: 'RDPCS_DPALT_4LANE_TOGGLE_4LANE',
}
RDPCS_DPALT_4LANE_TOGGLE_2LANE = 0
RDPCS_DPALT_4LANE_TOGGLE_4LANE = 1
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK'
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK__enumvalues = {
0: 'RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE',
1: 'RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE',
}
RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0
RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE = 1
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE'
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE__enumvalues = {
0: 'RDPCS_DPALT_DISABLE_TOGGLE_ENABLE',
1: 'RDPCS_DPALT_DISABLE_TOGGLE_DISABLE',
}
RDPCS_DPALT_DISABLE_TOGGLE_ENABLE = 0
RDPCS_DPALT_DISABLE_TOGGLE_DISABLE = 1
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK'
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK__enumvalues = {
0: 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE',
1: 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE',
}
RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0
RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 1
RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK'
RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK__enumvalues = {
0: 'RDPCS_REG_FIFO_ERROR_MASK_DISABLE',
1: 'RDPCS_REG_FIFO_ERROR_MASK_ENABLE',
}
RDPCS_REG_FIFO_ERROR_MASK_DISABLE = 0
RDPCS_REG_FIFO_ERROR_MASK_ENABLE = 1
RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK'
RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK__enumvalues = {
0: 'RDPCS_TX_FIFO_ERROR_MASK_DISABLE',
1: 'RDPCS_TX_FIFO_ERROR_MASK_ENABLE',
}
RDPCS_TX_FIFO_ERROR_MASK_DISABLE = 0
RDPCS_TX_FIFO_ERROR_MASK_ENABLE = 1
RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL'
RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL__enumvalues = {
0: 'RDPCS_PHY_CR_MUX_SEL_FOR_USB',
1: 'RDPCS_PHY_CR_MUX_SEL_FOR_DC',
}
RDPCS_PHY_CR_MUX_SEL_FOR_USB = 0
RDPCS_PHY_CR_MUX_SEL_FOR_DC = 1
RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL'
RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL__enumvalues = {
0: 'RDPCS_PHY_CR_PARA_SEL_JTAG',
1: 'RDPCS_PHY_CR_PARA_SEL_CR',
}
RDPCS_PHY_CR_PARA_SEL_JTAG = 0
RDPCS_PHY_CR_PARA_SEL_CR = 1
RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE'
RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE__enumvalues = {
0: 'RDPCS_PHY_REF_RANGE_0',
1: 'RDPCS_PHY_REF_RANGE_1',
2: 'RDPCS_PHY_REF_RANGE_2',
3: 'RDPCS_PHY_REF_RANGE_3',
4: 'RDPCS_PHY_REF_RANGE_4',
5: 'RDPCS_PHY_REF_RANGE_5',
6: 'RDPCS_PHY_REF_RANGE_6',
7: 'RDPCS_PHY_REF_RANGE_7',
}
RDPCS_PHY_REF_RANGE_0 = 0
RDPCS_PHY_REF_RANGE_1 = 1
RDPCS_PHY_REF_RANGE_2 = 2
RDPCS_PHY_REF_RANGE_3 = 3
RDPCS_PHY_REF_RANGE_4 = 4
RDPCS_PHY_REF_RANGE_5 = 5
RDPCS_PHY_REF_RANGE_6 = 6
RDPCS_PHY_REF_RANGE_7 = 7
RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE'
RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE__enumvalues = {
0: 'RDPCS_SRAM_EXT_LD_NOT_DONE',
1: 'RDPCS_SRAM_EXT_LD_DONE',
}
RDPCS_SRAM_EXT_LD_NOT_DONE = 0
RDPCS_SRAM_EXT_LD_DONE = 1
RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE'
RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE__enumvalues = {
0: 'RDPCS_SRAM_INIT_NOT_DONE',
1: 'RDPCS_SRAM_INIT_DONE',
}
RDPCS_SRAM_INIT_NOT_DONE = 0
RDPCS_SRAM_INIT_DONE = 1
RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV'
RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__enumvalues = {
0: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1',
1: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2',
2: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3',
3: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8',
4: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16',
}
RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1 = 0
RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2 = 1
RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3 = 2
RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8 = 3
RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16 = 4
RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV'
RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__enumvalues = {
0: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0',
1: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1',
2: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2',
3: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3',
}
RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0
RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 1
RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 2
RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 3
RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV'
RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__enumvalues = {
0: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV',
1: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2',
2: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4',
3: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8',
4: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3',
5: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5',
6: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6',
7: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10',
}
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2 = 1
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4 = 2
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8 = 3
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3 = 4
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5 = 5
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6 = 6
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10 = 7
RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL'
RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL__enumvalues = {
0: 'RDPCS_PHY_DP_TX_TERM_CTRL_54',
1: 'RDPCS_PHY_DP_TX_TERM_CTRL_52',
2: 'RDPCS_PHY_DP_TX_TERM_CTRL_50',
3: 'RDPCS_PHY_DP_TX_TERM_CTRL_48',
4: 'RDPCS_PHY_DP_TX_TERM_CTRL_46',
5: 'RDPCS_PHY_DP_TX_TERM_CTRL_44',
6: 'RDPCS_PHY_DP_TX_TERM_CTRL_42',
7: 'RDPCS_PHY_DP_TX_TERM_CTRL_40',
}
RDPCS_PHY_DP_TX_TERM_CTRL_54 = 0
RDPCS_PHY_DP_TX_TERM_CTRL_52 = 1
RDPCS_PHY_DP_TX_TERM_CTRL_50 = 2
RDPCS_PHY_DP_TX_TERM_CTRL_48 = 3
RDPCS_PHY_DP_TX_TERM_CTRL_46 = 4
RDPCS_PHY_DP_TX_TERM_CTRL_44 = 5
RDPCS_PHY_DP_TX_TERM_CTRL_42 = 6
RDPCS_PHY_DP_TX_TERM_CTRL_40 = 7
RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT'
RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT__enumvalues = {
0: 'RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT',
1: 'RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT',
}
RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0
RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT = 1
RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE'
RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE__enumvalues = {
0: 'RDPCS_PHY_DP_TX_RATE',
1: 'RDPCS_PHY_DP_TX_RATE_DIV2',
2: 'RDPCS_PHY_DP_TX_RATE_DIV4',
}
RDPCS_PHY_DP_TX_RATE = 0
RDPCS_PHY_DP_TX_RATE_DIV2 = 1
RDPCS_PHY_DP_TX_RATE_DIV4 = 2
RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH'
RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH__enumvalues = {
0: 'RDPCS_PHY_DP_TX_WIDTH_8',
1: 'RDPCS_PHY_DP_TX_WIDTH_10',
2: 'RDPCS_PHY_DP_TX_WIDTH_16',
3: 'RDPCS_PHY_DP_TX_WIDTH_20',
}
RDPCS_PHY_DP_TX_WIDTH_8 = 0
RDPCS_PHY_DP_TX_WIDTH_10 = 1
RDPCS_PHY_DP_TX_WIDTH_16 = 2
RDPCS_PHY_DP_TX_WIDTH_20 = 3
RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE'
RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE__enumvalues = {
0: 'RRDPCS_PHY_DP_TX_PSTATE_POWER_UP',
1: 'RRDPCS_PHY_DP_TX_PSTATE_HOLD',
2: 'RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF',
3: 'RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN',
}
RRDPCS_PHY_DP_TX_PSTATE_POWER_UP = 0
RRDPCS_PHY_DP_TX_PSTATE_HOLD = 1
RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF = 2
RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN = 3
RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_PHY_REF_ALT_CLK_EN'
RDPCSTX_PHY_REF_ALT_CLK_EN__enumvalues = {
0: 'RDPCS_PHY_REF_ALT_CLK_DISABLE',
1: 'RDPCS_PHY_REF_ALT_CLK_ENABLE',
}
RDPCS_PHY_REF_ALT_CLK_DISABLE = 0
RDPCS_PHY_REF_ALT_CLK_ENABLE = 1
RDPCSTX_PHY_REF_ALT_CLK_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSTX_TX_FIFO_DISABLED_MASK'
RDPCSTX_TX_FIFO_DISABLED_MASK__enumvalues = {
0: 'RDPCSTX_TX_FIFO_DISABLED_MASK_DISABLE',
1: 'RDPCSTX_TX_FIFO_DISABLED_MASK_ENABLE',
}
RDPCSTX_TX_FIFO_DISABLED_MASK_DISABLE = 0
RDPCSTX_TX_FIFO_DISABLED_MASK_ENABLE = 1
RDPCSTX_TX_FIFO_DISABLED_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCS_DBG_OCLA_SEL'
RDPCS_DBG_OCLA_SEL__enumvalues = {
0: 'RDPCS_DBG_OCLA_SEL_MON_OUT_7_0',
1: 'RDPCS_DBG_OCLA_SEL_MON_OUT_15_8',
2: 'RDPCS_DBG_OCLA_SEL_MON_OUT_23_16',
3: 'RDPCS_DBG_OCLA_SEL_MON_OUT_31_24',
4: 'RDPCS_DBG_OCLA_SEL_MON_OUT_39_32',
5: 'RDPCS_DBG_OCLA_SEL_MON_OUT_47_40',
6: 'RDPCS_DBG_OCLA_SEL_MON_OUT_55_48',
7: 'RDPCS_DBG_OCLA_SEL_MON_OUT_63_56',
}
RDPCS_DBG_OCLA_SEL_MON_OUT_7_0 = 0
RDPCS_DBG_OCLA_SEL_MON_OUT_15_8 = 1
RDPCS_DBG_OCLA_SEL_MON_OUT_23_16 = 2
RDPCS_DBG_OCLA_SEL_MON_OUT_31_24 = 3
RDPCS_DBG_OCLA_SEL_MON_OUT_39_32 = 4
RDPCS_DBG_OCLA_SEL_MON_OUT_47_40 = 5
RDPCS_DBG_OCLA_SEL_MON_OUT_55_48 = 6
RDPCS_DBG_OCLA_SEL_MON_OUT_63_56 = 7
RDPCS_DBG_OCLA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCS_TEST_CLK_SEL'
RDPCS_TEST_CLK_SEL__enumvalues = {
0: 'RDPCS_TEST_CLK_SEL_NONE',
1: 'RDPCS_TEST_CLK_SEL_CFGCLK',
2: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS',
3: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS',
4: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4',
5: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4',
6: 'RDPCS_TEST_CLK_SEL_SRAMCLK',
7: 'RDPCS_TEST_CLK_SEL_EXT_CR_CLK',
8: 'RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK',
9: 'RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK',
10: 'RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK',
11: 'RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK',
12: 'RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK',
13: 'RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK',
14: 'RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK',
15: 'RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk',
16: 'RDPCS_TEST_CLK_SEL_dtb_out0',
17: 'RDPCS_TEST_CLK_SEL_dtb_out1',
}
RDPCS_TEST_CLK_SEL_NONE = 0
RDPCS_TEST_CLK_SEL_CFGCLK = 1
RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 2
RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 3
RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 4
RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 5
RDPCS_TEST_CLK_SEL_SRAMCLK = 6
RDPCS_TEST_CLK_SEL_EXT_CR_CLK = 7
RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK = 8
RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK = 9
RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK = 10
RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK = 11
RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 12
RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 13
RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK = 14
RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk = 15
RDPCS_TEST_CLK_SEL_dtb_out0 = 16
RDPCS_TEST_CLK_SEL_dtb_out1 = 17
RDPCS_TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB'
RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB__enumvalues = {
0: 'RDPCS_LANE_PACK_FROM_MSB_DISABLE',
1: 'RDPCS_LANE_PACK_FROM_MSB_ENABLE',
}
RDPCS_LANE_PACK_FROM_MSB_DISABLE = 0
RDPCS_LANE_PACK_FROM_MSB_ENABLE = 1
RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB = ctypes.c_uint32 # enum
# values for enumeration 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE'
RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE__enumvalues = {
0: 'RDPCS_MEM_PWR_NO_FORCE',
1: 'RDPCS_MEM_PWR_LIGHT_SLEEP',
2: 'RDPCS_MEM_PWR_DEEP_SLEEP',
3: 'RDPCS_MEM_PWR_SHUT_DOWN',
}
RDPCS_MEM_PWR_NO_FORCE = 0
RDPCS_MEM_PWR_LIGHT_SLEEP = 1
RDPCS_MEM_PWR_DEEP_SLEEP = 2
RDPCS_MEM_PWR_SHUT_DOWN = 3
RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE'
RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE__enumvalues = {
0: 'RDPCS_MEM_PWR_PWR_STATE_ON',
1: 'RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP',
2: 'RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP',
3: 'RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN',
}
RDPCS_MEM_PWR_PWR_STATE_ON = 0
RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 1
RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP = 2
RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN = 3
RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE = ctypes.c_uint32 # enum
# values for enumeration 'RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK'
RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK__enumvalues = {
0: 'RDPCS_LANE_BIT_ORDER_REVERSE_DISABLE',
1: 'RDPCS_LANE_BIT_ORDER_REVERSE_ENABLE',
}
RDPCS_LANE_BIT_ORDER_REVERSE_DISABLE = 0
RDPCS_LANE_BIT_ORDER_REVERSE_ENABLE = 1
RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK = ctypes.c_uint32 # enum
# values for enumeration 'RLC_DOORBELL_MODE'
RLC_DOORBELL_MODE__enumvalues = {
0: 'RLC_DOORBELL_MODE_DISABLE',
1: 'RLC_DOORBELL_MODE_ENABLE',
2: 'RLC_DOORBELL_MODE_ENABLE_PF',
3: 'RLC_DOORBELL_MODE_ENABLE_PF_VF',
}
RLC_DOORBELL_MODE_DISABLE = 0
RLC_DOORBELL_MODE_ENABLE = 1
RLC_DOORBELL_MODE_ENABLE_PF = 2
RLC_DOORBELL_MODE_ENABLE_PF_VF = 3
RLC_DOORBELL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'RLC_PERFCOUNTER_SEL'
RLC_PERFCOUNTER_SEL__enumvalues = {
0: 'RLC_PERF_SEL_POWER_FEATURE_0',
1: 'RLC_PERF_SEL_POWER_FEATURE_1',
2: 'RLC_PERF_SEL_CP_INTERRUPT',
3: 'RLC_PERF_SEL_GRBM_INTERRUPT',
4: 'RLC_PERF_SEL_SPM_INTERRUPT',
5: 'RLC_PERF_SEL_IH_INTERRUPT',
6: 'RLC_PERF_SEL_SERDES_COMMAND_WRITE',
}
RLC_PERF_SEL_POWER_FEATURE_0 = 0
RLC_PERF_SEL_POWER_FEATURE_1 = 1
RLC_PERF_SEL_CP_INTERRUPT = 2
RLC_PERF_SEL_GRBM_INTERRUPT = 3
RLC_PERF_SEL_SPM_INTERRUPT = 4
RLC_PERF_SEL_IH_INTERRUPT = 5
RLC_PERF_SEL_SERDES_COMMAND_WRITE = 6
RLC_PERFCOUNTER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'RLC_PERFMON_STATE'
RLC_PERFMON_STATE__enumvalues = {
0: 'RLC_PERFMON_STATE_RESET',
1: 'RLC_PERFMON_STATE_ENABLE',
2: 'RLC_PERFMON_STATE_DISABLE',
3: 'RLC_PERFMON_STATE_RESERVED_3',
4: 'RLC_PERFMON_STATE_RESERVED_4',
5: 'RLC_PERFMON_STATE_RESERVED_5',
6: 'RLC_PERFMON_STATE_RESERVED_6',
7: 'RLC_PERFMON_STATE_ROLLOVER',
}
RLC_PERFMON_STATE_RESET = 0
RLC_PERFMON_STATE_ENABLE = 1
RLC_PERFMON_STATE_DISABLE = 2
RLC_PERFMON_STATE_RESERVED_3 = 3
RLC_PERFMON_STATE_RESERVED_4 = 4
RLC_PERFMON_STATE_RESERVED_5 = 5
RLC_PERFMON_STATE_RESERVED_6 = 6
RLC_PERFMON_STATE_ROLLOVER = 7
RLC_PERFMON_STATE = ctypes.c_uint32 # enum
# values for enumeration 'RSPM_CMD'
RSPM_CMD__enumvalues = {
0: 'RSPM_CMD_INVALID',
1: 'RSPM_CMD_IDLE',
2: 'RSPM_CMD_CALIBRATE',
3: 'RSPM_CMD_SPM_RESET',
4: 'RSPM_CMD_SPM_START',
5: 'RSPM_CMD_SPM_STOP',
6: 'RSPM_CMD_PERF_RESET',
7: 'RSPM_CMD_PERF_SAMPLE',
8: 'RSPM_CMD_PROF_START',
9: 'RSPM_CMD_PROF_STOP',
10: 'RSPM_CMD_FORCE_SAMPLE',
}
RSPM_CMD_INVALID = 0
RSPM_CMD_IDLE = 1
RSPM_CMD_CALIBRATE = 2
RSPM_CMD_SPM_RESET = 3
RSPM_CMD_SPM_START = 4
RSPM_CMD_SPM_STOP = 5
RSPM_CMD_PERF_RESET = 6
RSPM_CMD_PERF_SAMPLE = 7
RSPM_CMD_PROF_START = 8
RSPM_CMD_PROF_STOP = 9
RSPM_CMD_FORCE_SAMPLE = 10
RSPM_CMD = ctypes.c_uint32 # enum
# values for enumeration 'CSCNTL_TYPE'
CSCNTL_TYPE__enumvalues = {
0: 'CSCNTL_TYPE_TG',
1: 'CSCNTL_TYPE_STATE',
2: 'CSCNTL_TYPE_EVENT',
3: 'CSCNTL_TYPE_PRIVATE',
}
CSCNTL_TYPE_TG = 0
CSCNTL_TYPE_STATE = 1
CSCNTL_TYPE_EVENT = 2
CSCNTL_TYPE_PRIVATE = 3
CSCNTL_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'CSDATA_TYPE'
CSDATA_TYPE__enumvalues = {
0: 'CSDATA_TYPE_TG',
1: 'CSDATA_TYPE_STATE',
2: 'CSDATA_TYPE_EVENT',
3: 'CSDATA_TYPE_PRIVATE',
}
CSDATA_TYPE_TG = 0
CSDATA_TYPE_STATE = 1
CSDATA_TYPE_EVENT = 2
CSDATA_TYPE_PRIVATE = 3
CSDATA_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'GE1_PERFCOUNT_SELECT'
GE1_PERFCOUNT_SELECT__enumvalues = {
0: 'ge1_assembler_busy',
1: 'ge1_assembler_stalled',
2: 'ge1_dma_busy',
3: 'ge1_dma_lat_bin_0',
4: 'ge1_dma_lat_bin_1',
5: 'ge1_dma_lat_bin_2',
6: 'ge1_dma_lat_bin_3',
7: 'ge1_dma_lat_bin_4',
8: 'ge1_dma_lat_bin_5',
9: 'ge1_dma_lat_bin_6',
10: 'ge1_dma_lat_bin_7',
11: 'ge1_dma_return_cl0',
12: 'ge1_dma_return_cl1',
13: 'ge1_dma_utcl1_consecutive_retry_event',
14: 'ge1_dma_utcl1_request_event',
15: 'ge1_dma_utcl1_retry_event',
16: 'ge1_dma_utcl1_stall_event',
17: 'ge1_dma_utcl1_stall_utcl2_event',
18: 'ge1_dma_utcl1_translation_hit_event',
19: 'ge1_dma_utcl1_translation_miss_event',
20: 'ge1_assembler_dma_starved',
21: 'ge1_rbiu_di_fifo_stalled_p0',
22: 'ge1_rbiu_di_fifo_starved_p0',
23: 'ge1_rbiu_dr_fifo_stalled_p0',
24: 'ge1_rbiu_dr_fifo_starved_p0',
25: 'ge1_sclk_reg_vld',
26: 'ge1_stat_busy',
27: 'ge1_stat_no_dma_busy',
28: 'ge1_pipe0_to_pipe1',
29: 'ge1_pipe1_to_pipe0',
30: 'ge1_dma_return_size_cl0',
31: 'ge1_dma_return_size_cl1',
32: 'ge1_small_draws_one_instance',
33: 'ge1_sclk_input_vld',
34: 'ge1_prim_group_limit_hit',
35: 'ge1_unopt_multi_instance_draws',
36: 'ge1_rbiu_di_fifo_stalled_p1',
37: 'ge1_rbiu_di_fifo_starved_p1',
38: 'ge1_rbiu_dr_fifo_stalled_p1',
39: 'ge1_rbiu_dr_fifo_starved_p1',
}
ge1_assembler_busy = 0
ge1_assembler_stalled = 1
ge1_dma_busy = 2
ge1_dma_lat_bin_0 = 3
ge1_dma_lat_bin_1 = 4
ge1_dma_lat_bin_2 = 5
ge1_dma_lat_bin_3 = 6
ge1_dma_lat_bin_4 = 7
ge1_dma_lat_bin_5 = 8
ge1_dma_lat_bin_6 = 9
ge1_dma_lat_bin_7 = 10
ge1_dma_return_cl0 = 11
ge1_dma_return_cl1 = 12
ge1_dma_utcl1_consecutive_retry_event = 13
ge1_dma_utcl1_request_event = 14
ge1_dma_utcl1_retry_event = 15
ge1_dma_utcl1_stall_event = 16
ge1_dma_utcl1_stall_utcl2_event = 17
ge1_dma_utcl1_translation_hit_event = 18
ge1_dma_utcl1_translation_miss_event = 19
ge1_assembler_dma_starved = 20
ge1_rbiu_di_fifo_stalled_p0 = 21
ge1_rbiu_di_fifo_starved_p0 = 22
ge1_rbiu_dr_fifo_stalled_p0 = 23
ge1_rbiu_dr_fifo_starved_p0 = 24
ge1_sclk_reg_vld = 25
ge1_stat_busy = 26
ge1_stat_no_dma_busy = 27
ge1_pipe0_to_pipe1 = 28
ge1_pipe1_to_pipe0 = 29
ge1_dma_return_size_cl0 = 30
ge1_dma_return_size_cl1 = 31
ge1_small_draws_one_instance = 32
ge1_sclk_input_vld = 33
ge1_prim_group_limit_hit = 34
ge1_unopt_multi_instance_draws = 35
ge1_rbiu_di_fifo_stalled_p1 = 36
ge1_rbiu_di_fifo_starved_p1 = 37
ge1_rbiu_dr_fifo_stalled_p1 = 38
ge1_rbiu_dr_fifo_starved_p1 = 39
GE1_PERFCOUNT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'GE2_DIST_PERFCOUNT_SELECT'
GE2_DIST_PERFCOUNT_SELECT__enumvalues = {
0: 'ge_dist_hs_done',
1: 'ge_dist_hs_done_latency_se0',
2: 'ge_dist_hs_done_latency_se1',
3: 'ge_dist_hs_done_latency_se2',
4: 'ge_dist_hs_done_latency_se3',
5: 'ge_dist_hs_done_latency_se4',
6: 'ge_dist_hs_done_latency_se5',
7: 'ge_dist_hs_done_latency_se6',
8: 'ge_dist_hs_done_latency_se7',
9: 'ge_dist_inside_tf_bin_0',
10: 'ge_dist_inside_tf_bin_1',
11: 'ge_dist_inside_tf_bin_2',
12: 'ge_dist_inside_tf_bin_3',
13: 'ge_dist_inside_tf_bin_4',
14: 'ge_dist_inside_tf_bin_5',
15: 'ge_dist_inside_tf_bin_6',
16: 'ge_dist_inside_tf_bin_7',
17: 'ge_dist_inside_tf_bin_8',
18: 'ge_dist_null_patch',
19: 'ge_dist_sclk_core_vld',
20: 'ge_dist_sclk_wd_te11_vld',
21: 'ge_dist_tfreq_lat_bin_0',
22: 'ge_dist_tfreq_lat_bin_1',
23: 'ge_dist_tfreq_lat_bin_2',
24: 'ge_dist_tfreq_lat_bin_3',
25: 'ge_dist_tfreq_lat_bin_4',
26: 'ge_dist_tfreq_lat_bin_5',
27: 'ge_dist_tfreq_lat_bin_6',
28: 'ge_dist_tfreq_lat_bin_7',
29: 'ge_dist_tfreq_utcl1_consecutive_retry_event',
30: 'ge_dist_tfreq_utcl1_request_event',
31: 'ge_dist_tfreq_utcl1_retry_event',
32: 'ge_dist_tfreq_utcl1_stall_event',
33: 'ge_dist_tfreq_utcl1_stall_utcl2_event',
34: 'ge_dist_tfreq_utcl1_translation_hit_event',
35: 'ge_dist_tfreq_utcl1_translation_miss_event',
36: 'ge_dist_pc_feorder_fifo_full',
37: 'ge_dist_pc_ge_manager_busy',
38: 'ge_dist_sclk_input_vld',
39: 'ge_dist_wd_te11_busy',
40: 'ge_dist_te11_starved',
41: 'ge_dist_switch_mode_stall',
42: 'ge_all_tf_eq',
43: 'ge_all_tf2',
44: 'ge_all_tf3',
45: 'ge_all_tf4',
46: 'ge_all_tf5',
47: 'ge_all_tf6',
48: 'ge_se0_te11_starved_on_hs_done',
49: 'ge_se1_te11_starved_on_hs_done',
50: 'ge_se2_te11_starved_on_hs_done',
51: 'ge_se3_te11_starved_on_hs_done',
52: 'ge_se4_te11_starved_on_hs_done',
53: 'ge_se5_te11_starved_on_hs_done',
54: 'ge_se6_te11_starved_on_hs_done',
55: 'ge_se7_te11_starved_on_hs_done',
56: 'ge_dist_op_fifo_full_starve',
57: 'ge_dist_hs_done_se0',
58: 'ge_dist_hs_done_se1',
59: 'ge_dist_hs_done_se2',
60: 'ge_dist_hs_done_se3',
61: 'ge_dist_hs_done_se4',
62: 'ge_dist_hs_done_se5',
63: 'ge_dist_hs_done_se6',
64: 'ge_dist_hs_done_se7',
65: 'ge_dist_hs_done_latency',
66: 'ge_dist_distributer_busy',
67: 'ge_tf_ret_data_stalling_hs_done',
68: 'ge_num_of_no_dist_patches',
69: 'ge_num_of_donut_dist_patches',
70: 'ge_num_of_patch_dist_patches',
71: 'ge_num_of_se_switches_due_to_patch_accum',
72: 'ge_num_of_se_switches_due_to_donut',
73: 'ge_num_of_se_switches_due_to_trap',
74: 'ge_num_of_hs_dealloc_events',
75: 'ge_agm_gcr_req',
76: 'ge_agm_gcr_tag_stall',
77: 'ge_agm_gcr_crd_stall',
78: 'ge_agm_gcr_stall',
79: 'ge_agm_gcr_latency',
80: 'ge_distclk_vld',
81: 'ge_dist_indx_fifos_full_and_empty',
82: 'ge_hs_done_all_tf0_se0',
83: 'ge_hs_done_all_tf0_se1',
84: 'ge_hs_done_all_tf0_se2',
85: 'ge_hs_done_all_tf0_se3',
86: 'ge_hs_done_all_tf0_se4',
87: 'ge_hs_done_all_tf0_se5',
88: 'ge_hs_done_all_tf0_se6',
89: 'ge_hs_done_all_tf0_se7',
90: 'ge_hs_done_all_tf1_se0',
91: 'ge_hs_done_all_tf1_se1',
92: 'ge_hs_done_all_tf1_se2',
93: 'ge_hs_done_all_tf1_se3',
94: 'ge_hs_done_all_tf1_se4',
95: 'ge_hs_done_all_tf1_se5',
96: 'ge_hs_done_all_tf1_se6',
97: 'ge_hs_done_all_tf1_se7',
98: 'ge_agm_gcr_req_outstanding',
99: 'ge_agm_gcr_req_amount',
100: 'ge_agm_gcr_combine',
}
ge_dist_hs_done = 0
ge_dist_hs_done_latency_se0 = 1
ge_dist_hs_done_latency_se1 = 2
ge_dist_hs_done_latency_se2 = 3
ge_dist_hs_done_latency_se3 = 4
ge_dist_hs_done_latency_se4 = 5
ge_dist_hs_done_latency_se5 = 6
ge_dist_hs_done_latency_se6 = 7
ge_dist_hs_done_latency_se7 = 8
ge_dist_inside_tf_bin_0 = 9
ge_dist_inside_tf_bin_1 = 10
ge_dist_inside_tf_bin_2 = 11
ge_dist_inside_tf_bin_3 = 12
ge_dist_inside_tf_bin_4 = 13
ge_dist_inside_tf_bin_5 = 14
ge_dist_inside_tf_bin_6 = 15
ge_dist_inside_tf_bin_7 = 16
ge_dist_inside_tf_bin_8 = 17
ge_dist_null_patch = 18
ge_dist_sclk_core_vld = 19
ge_dist_sclk_wd_te11_vld = 20
ge_dist_tfreq_lat_bin_0 = 21
ge_dist_tfreq_lat_bin_1 = 22
ge_dist_tfreq_lat_bin_2 = 23
ge_dist_tfreq_lat_bin_3 = 24
ge_dist_tfreq_lat_bin_4 = 25
ge_dist_tfreq_lat_bin_5 = 26
ge_dist_tfreq_lat_bin_6 = 27
ge_dist_tfreq_lat_bin_7 = 28
ge_dist_tfreq_utcl1_consecutive_retry_event = 29
ge_dist_tfreq_utcl1_request_event = 30
ge_dist_tfreq_utcl1_retry_event = 31
ge_dist_tfreq_utcl1_stall_event = 32
ge_dist_tfreq_utcl1_stall_utcl2_event = 33
ge_dist_tfreq_utcl1_translation_hit_event = 34
ge_dist_tfreq_utcl1_translation_miss_event = 35
ge_dist_pc_feorder_fifo_full = 36
ge_dist_pc_ge_manager_busy = 37
ge_dist_sclk_input_vld = 38
ge_dist_wd_te11_busy = 39
ge_dist_te11_starved = 40
ge_dist_switch_mode_stall = 41
ge_all_tf_eq = 42
ge_all_tf2 = 43
ge_all_tf3 = 44
ge_all_tf4 = 45
ge_all_tf5 = 46
ge_all_tf6 = 47
ge_se0_te11_starved_on_hs_done = 48
ge_se1_te11_starved_on_hs_done = 49
ge_se2_te11_starved_on_hs_done = 50
ge_se3_te11_starved_on_hs_done = 51
ge_se4_te11_starved_on_hs_done = 52
ge_se5_te11_starved_on_hs_done = 53
ge_se6_te11_starved_on_hs_done = 54
ge_se7_te11_starved_on_hs_done = 55
ge_dist_op_fifo_full_starve = 56
ge_dist_hs_done_se0 = 57
ge_dist_hs_done_se1 = 58
ge_dist_hs_done_se2 = 59
ge_dist_hs_done_se3 = 60
ge_dist_hs_done_se4 = 61
ge_dist_hs_done_se5 = 62
ge_dist_hs_done_se6 = 63
ge_dist_hs_done_se7 = 64
ge_dist_hs_done_latency = 65
ge_dist_distributer_busy = 66
ge_tf_ret_data_stalling_hs_done = 67
ge_num_of_no_dist_patches = 68
ge_num_of_donut_dist_patches = 69
ge_num_of_patch_dist_patches = 70
ge_num_of_se_switches_due_to_patch_accum = 71
ge_num_of_se_switches_due_to_donut = 72
ge_num_of_se_switches_due_to_trap = 73
ge_num_of_hs_dealloc_events = 74
ge_agm_gcr_req = 75
ge_agm_gcr_tag_stall = 76
ge_agm_gcr_crd_stall = 77
ge_agm_gcr_stall = 78
ge_agm_gcr_latency = 79
ge_distclk_vld = 80
ge_dist_indx_fifos_full_and_empty = 81
ge_hs_done_all_tf0_se0 = 82
ge_hs_done_all_tf0_se1 = 83
ge_hs_done_all_tf0_se2 = 84
ge_hs_done_all_tf0_se3 = 85
ge_hs_done_all_tf0_se4 = 86
ge_hs_done_all_tf0_se5 = 87
ge_hs_done_all_tf0_se6 = 88
ge_hs_done_all_tf0_se7 = 89
ge_hs_done_all_tf1_se0 = 90
ge_hs_done_all_tf1_se1 = 91
ge_hs_done_all_tf1_se2 = 92
ge_hs_done_all_tf1_se3 = 93
ge_hs_done_all_tf1_se4 = 94
ge_hs_done_all_tf1_se5 = 95
ge_hs_done_all_tf1_se6 = 96
ge_hs_done_all_tf1_se7 = 97
ge_agm_gcr_req_outstanding = 98
ge_agm_gcr_req_amount = 99
ge_agm_gcr_combine = 100
GE2_DIST_PERFCOUNT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'GE2_SE_PERFCOUNT_SELECT'
GE2_SE_PERFCOUNT_SELECT__enumvalues = {
0: 'ge_se_ds_prims',
1: 'ge_se_es_thread_groups',
2: 'ge_se_esvert_stalled_gsprim',
3: 'ge_se_hs_tfm_stall',
4: 'ge_se_hs_tgs_active_high_water_mark',
5: 'ge_se_hs_thread_groups',
6: 'ge_se_reused_es_indices',
7: 'ge_se_sclk_ngg_vld',
8: 'ge_se_sclk_te11_vld',
9: 'ge_se_spi_esvert_eov',
10: 'ge_se_spi_esvert_stalled',
11: 'ge_se_spi_esvert_starved_busy',
12: 'ge_se_spi_esvert_valid',
13: 'ge_se_spi_gsprim_cont',
14: 'ge_se_spi_gsprim_eov',
15: 'ge_se_spi_gsprim_stalled',
16: 'ge_se_spi_gsprim_starved_busy',
17: 'ge_se_spi_gsprim_valid',
18: 'ge_se_spi_gssubgrp_is_event',
19: 'ge_se_spi_gssubgrp_send',
20: 'ge_se_spi_hsvert_eov',
21: 'ge_se_spi_hsvert_stalled',
22: 'ge_se_spi_hsvert_starved_busy',
23: 'ge_se_spi_hsvert_valid',
24: 'ge_se_spi_hsgrp_is_event',
25: 'ge_se_spi_hsgrp_send',
26: 'ge_se_spi_lsvert_eov',
27: 'ge_se_spi_lsvert_stalled',
28: 'ge_se_spi_lsvert_starved_busy',
29: 'ge_se_spi_lsvert_valid',
30: 'ge_se_spi_hsvert_fifo_full_stall',
31: 'ge_se_spi_tgrp_fifo_stall',
32: 'ge_spi_hsgrp_spi_stall',
33: 'ge_se_spi_gssubgrp_event_window_active',
34: 'ge_se_hs_input_stall',
35: 'ge_se_sending_vert_or_prim',
36: 'ge_se_sclk_input_vld',
37: 'ge_spi_lswave_fifo_full_stall',
38: 'ge_spi_hswave_fifo_full_stall',
39: 'ge_hs_tif_stall',
40: 'ge_csb_spi_bp',
41: 'ge_ngg_starving_for_wave_id',
42: 'ge_pa0_csb_eop',
43: 'ge_ngg_starved_idle',
44: 'ge_gsprim_send',
45: 'ge_esvert_send',
46: 'ge_ngg_starved_after_work',
47: 'ge_ngg_subgrp_fifo_stall',
48: 'ge_ngg_ord_id_req_stall',
49: 'ge_ngg_indx_bus_stall',
50: 'ge_hs_stall_tfmm_fifo_full',
51: 'ge_gs_issue_rtr_stalled',
52: 'ge_gsprim_stalled_esvert',
53: 'ge_gsthread_stalled',
54: 'ge_ngg_attr_grp_alloc',
55: 'ge_ngg_attr_discard_alloc',
56: 'ge_ngg_pc_space_not_avail',
57: 'ge_ngg_agm_req_stall',
58: 'ge_ngg_spi_esvert_partial_eov',
59: 'ge_ngg_spi_gsprim_partial_eov',
60: 'ge_spi_gsgrp_valid',
61: 'ge_ngg_attr_grp_latency',
62: 'ge_ngg_reuse_prim_limit_hit',
63: 'ge_ngg_reuse_vert_limit_hit',
64: 'ge_te11_con_stall',
65: 'ge_te11_compactor_starved',
66: 'ge_ngg_stall_tess_off_tess_on',
67: 'ge_ngg_stall_tess_on_tess_off',
68: 'ge_merged_lses_vert_stalled',
69: 'ge_merged_hsgs_vert_stalled',
70: 'ge_merged_hsgs_grp_stalled',
71: 'ge_merge_lses_fifo_blocked',
72: 'ge_merge_hsgs_fifo_blocked',
73: 'ge_merge_lses_vert_switch',
74: 'ge_merge_hsgs_vert_switch',
75: 'ge_merge_hsgs_grp_switch',
76: 'ge_merge_gsgrp_rdy_pending_verts',
77: 'ge_merge_hsgrp_rdy_pending_verts',
78: 'ge_se_ds_cache_hits',
79: 'ge_se_api_vs_verts',
80: 'ge_se_api_ds_verts',
81: 'ge_se_combined_busy',
82: 'ge_spi_lsvert_send',
83: 'ge_spi_hsvert_send',
84: 'ge_ngg_attr_grp_wasted',
85: 'ge_spi_gssubgrp_stalled',
86: 'ge_ngg_attr_null_dealloc',
87: 'ge_ngg_busy_base',
}
ge_se_ds_prims = 0
ge_se_es_thread_groups = 1
ge_se_esvert_stalled_gsprim = 2
ge_se_hs_tfm_stall = 3
ge_se_hs_tgs_active_high_water_mark = 4
ge_se_hs_thread_groups = 5
ge_se_reused_es_indices = 6
ge_se_sclk_ngg_vld = 7
ge_se_sclk_te11_vld = 8
ge_se_spi_esvert_eov = 9
ge_se_spi_esvert_stalled = 10
ge_se_spi_esvert_starved_busy = 11
ge_se_spi_esvert_valid = 12
ge_se_spi_gsprim_cont = 13
ge_se_spi_gsprim_eov = 14
ge_se_spi_gsprim_stalled = 15
ge_se_spi_gsprim_starved_busy = 16
ge_se_spi_gsprim_valid = 17
ge_se_spi_gssubgrp_is_event = 18
ge_se_spi_gssubgrp_send = 19
ge_se_spi_hsvert_eov = 20
ge_se_spi_hsvert_stalled = 21
ge_se_spi_hsvert_starved_busy = 22
ge_se_spi_hsvert_valid = 23
ge_se_spi_hsgrp_is_event = 24
ge_se_spi_hsgrp_send = 25
ge_se_spi_lsvert_eov = 26
ge_se_spi_lsvert_stalled = 27
ge_se_spi_lsvert_starved_busy = 28
ge_se_spi_lsvert_valid = 29
ge_se_spi_hsvert_fifo_full_stall = 30
ge_se_spi_tgrp_fifo_stall = 31
ge_spi_hsgrp_spi_stall = 32
ge_se_spi_gssubgrp_event_window_active = 33
ge_se_hs_input_stall = 34
ge_se_sending_vert_or_prim = 35
ge_se_sclk_input_vld = 36
ge_spi_lswave_fifo_full_stall = 37
ge_spi_hswave_fifo_full_stall = 38
ge_hs_tif_stall = 39
ge_csb_spi_bp = 40
ge_ngg_starving_for_wave_id = 41
ge_pa0_csb_eop = 42
ge_ngg_starved_idle = 43
ge_gsprim_send = 44
ge_esvert_send = 45
ge_ngg_starved_after_work = 46
ge_ngg_subgrp_fifo_stall = 47
ge_ngg_ord_id_req_stall = 48
ge_ngg_indx_bus_stall = 49
ge_hs_stall_tfmm_fifo_full = 50
ge_gs_issue_rtr_stalled = 51
ge_gsprim_stalled_esvert = 52
ge_gsthread_stalled = 53
ge_ngg_attr_grp_alloc = 54
ge_ngg_attr_discard_alloc = 55
ge_ngg_pc_space_not_avail = 56
ge_ngg_agm_req_stall = 57
ge_ngg_spi_esvert_partial_eov = 58
ge_ngg_spi_gsprim_partial_eov = 59
ge_spi_gsgrp_valid = 60
ge_ngg_attr_grp_latency = 61
ge_ngg_reuse_prim_limit_hit = 62
ge_ngg_reuse_vert_limit_hit = 63
ge_te11_con_stall = 64
ge_te11_compactor_starved = 65
ge_ngg_stall_tess_off_tess_on = 66
ge_ngg_stall_tess_on_tess_off = 67
ge_merged_lses_vert_stalled = 68
ge_merged_hsgs_vert_stalled = 69
ge_merged_hsgs_grp_stalled = 70
ge_merge_lses_fifo_blocked = 71
ge_merge_hsgs_fifo_blocked = 72
ge_merge_lses_vert_switch = 73
ge_merge_hsgs_vert_switch = 74
ge_merge_hsgs_grp_switch = 75
ge_merge_gsgrp_rdy_pending_verts = 76
ge_merge_hsgrp_rdy_pending_verts = 77
ge_se_ds_cache_hits = 78
ge_se_api_vs_verts = 79
ge_se_api_ds_verts = 80
ge_se_combined_busy = 81
ge_spi_lsvert_send = 82
ge_spi_hsvert_send = 83
ge_ngg_attr_grp_wasted = 84
ge_spi_gssubgrp_stalled = 85
ge_ngg_attr_null_dealloc = 86
ge_ngg_busy_base = 87
GE2_SE_PERFCOUNT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DETECT_ONE'
VGT_DETECT_ONE__enumvalues = {
0: 'ENABLE_TF1_OPT',
1: 'DISABLE_TF1_OPT',
}
ENABLE_TF1_OPT = 0
DISABLE_TF1_OPT = 1
VGT_DETECT_ONE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DETECT_ZERO'
VGT_DETECT_ZERO__enumvalues = {
0: 'ENABLE_TF0_OPT',
1: 'DISABLE_TF0_OPT',
}
ENABLE_TF0_OPT = 0
DISABLE_TF0_OPT = 1
VGT_DETECT_ZERO = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DIST_MODE'
VGT_DIST_MODE__enumvalues = {
0: 'NO_DIST',
1: 'PATCHES',
2: 'DONUTS',
3: 'TRAPEZOIDS',
}
NO_DIST = 0
PATCHES = 1
DONUTS = 2
TRAPEZOIDS = 3
VGT_DIST_MODE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DI_INDEX_SIZE'
VGT_DI_INDEX_SIZE__enumvalues = {
0: 'DI_INDEX_SIZE_16_BIT',
1: 'DI_INDEX_SIZE_32_BIT',
2: 'DI_INDEX_SIZE_8_BIT',
}
DI_INDEX_SIZE_16_BIT = 0
DI_INDEX_SIZE_32_BIT = 1
DI_INDEX_SIZE_8_BIT = 2
VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DI_PRIM_TYPE'
VGT_DI_PRIM_TYPE__enumvalues = {
0: 'DI_PT_NONE',
1: 'DI_PT_POINTLIST',
2: 'DI_PT_LINELIST',
3: 'DI_PT_LINESTRIP',
4: 'DI_PT_TRILIST',
5: 'DI_PT_TRIFAN',
6: 'DI_PT_TRISTRIP',
7: 'DI_PT_2D_RECTANGLE',
8: 'DI_PT_UNUSED_1',
9: 'DI_PT_PATCH',
10: 'DI_PT_LINELIST_ADJ',
11: 'DI_PT_LINESTRIP_ADJ',
12: 'DI_PT_TRILIST_ADJ',
13: 'DI_PT_TRISTRIP_ADJ',
14: 'DI_PT_UNUSED_3',
15: 'DI_PT_UNUSED_4',
16: 'DI_PT_UNUSED_5',
17: 'DI_PT_RECTLIST',
18: 'DI_PT_LINELOOP',
19: 'DI_PT_QUADLIST',
20: 'DI_PT_QUADSTRIP',
21: 'DI_PT_POLYGON',
}
DI_PT_NONE = 0
DI_PT_POINTLIST = 1
DI_PT_LINELIST = 2
DI_PT_LINESTRIP = 3
DI_PT_TRILIST = 4
DI_PT_TRIFAN = 5
DI_PT_TRISTRIP = 6
DI_PT_2D_RECTANGLE = 7
DI_PT_UNUSED_1 = 8
DI_PT_PATCH = 9
DI_PT_LINELIST_ADJ = 10
DI_PT_LINESTRIP_ADJ = 11
DI_PT_TRILIST_ADJ = 12
DI_PT_TRISTRIP_ADJ = 13
DI_PT_UNUSED_3 = 14
DI_PT_UNUSED_4 = 15
DI_PT_UNUSED_5 = 16
DI_PT_RECTLIST = 17
DI_PT_LINELOOP = 18
DI_PT_QUADLIST = 19
DI_PT_QUADSTRIP = 20
DI_PT_POLYGON = 21
VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DI_SOURCE_SELECT'
VGT_DI_SOURCE_SELECT__enumvalues = {
0: 'DI_SRC_SEL_DMA',
1: 'DI_SRC_SEL_IMMEDIATE',
2: 'DI_SRC_SEL_AUTO_INDEX',
3: 'DI_SRC_SEL_RESERVED',
}
DI_SRC_SEL_DMA = 0
DI_SRC_SEL_IMMEDIATE = 1
DI_SRC_SEL_AUTO_INDEX = 2
DI_SRC_SEL_RESERVED = 3
VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DMA_BUF_TYPE'
VGT_DMA_BUF_TYPE__enumvalues = {
0: 'VGT_DMA_BUF_MEM',
1: 'VGT_DMA_BUF_RING',
2: 'VGT_DMA_BUF_SETUP',
3: 'VGT_DMA_PTR_UPDATE',
}
VGT_DMA_BUF_MEM = 0
VGT_DMA_BUF_RING = 1
VGT_DMA_BUF_SETUP = 2
VGT_DMA_PTR_UPDATE = 3
VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DMA_SWAP_MODE'
VGT_DMA_SWAP_MODE__enumvalues = {
0: 'VGT_DMA_SWAP_NONE',
1: 'VGT_DMA_SWAP_16_BIT',
2: 'VGT_DMA_SWAP_32_BIT',
3: 'VGT_DMA_SWAP_WORD',
}
VGT_DMA_SWAP_NONE = 0
VGT_DMA_SWAP_16_BIT = 1
VGT_DMA_SWAP_32_BIT = 2
VGT_DMA_SWAP_WORD = 3
VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_EVENT_TYPE'
VGT_EVENT_TYPE__enumvalues = {
0: 'Reserved_0x00',
1: 'SAMPLE_STREAMOUTSTATS1',
2: 'SAMPLE_STREAMOUTSTATS2',
3: 'SAMPLE_STREAMOUTSTATS3',
4: 'CACHE_FLUSH_TS',
5: 'CONTEXT_DONE',
6: 'CACHE_FLUSH',
7: 'CS_PARTIAL_FLUSH',
8: 'VGT_STREAMOUT_SYNC',
9: 'EVENT_STATE_CHANGE',
10: 'VGT_STREAMOUT_RESET',
11: 'END_OF_PIPE_INCR_DE',
12: 'END_OF_PIPE_IB_END',
13: 'RST_PIX_CNT',
14: 'BREAK_BATCH',
15: 'VS_PARTIAL_FLUSH',
16: 'PS_PARTIAL_FLUSH',
17: 'FLUSH_HS_OUTPUT',
18: 'FLUSH_DFSM',
19: 'RESET_TO_LOWEST_VGT',
20: 'CACHE_FLUSH_AND_INV_TS_EVENT',
21: 'WAIT_SYNC',
22: 'CACHE_FLUSH_AND_INV_EVENT',
23: 'PERFCOUNTER_START',
24: 'PERFCOUNTER_STOP',
25: 'PIPELINESTAT_START',
26: 'PIPELINESTAT_STOP',
27: 'PERFCOUNTER_SAMPLE',
28: 'FLUSH_ES_OUTPUT',
29: 'BIN_CONF_OVERRIDE_CHECK',
30: 'SAMPLE_PIPELINESTAT',
31: 'SO_VGTSTREAMOUT_FLUSH',
32: 'SAMPLE_STREAMOUTSTATS',
33: 'RESET_VTX_CNT',
34: 'BLOCK_CONTEXT_DONE',
35: 'CS_CONTEXT_DONE',
36: 'VGT_FLUSH',
37: 'TGID_ROLLOVER',
38: 'SQ_NON_EVENT',
39: 'SC_SEND_DB_VPZ',
40: 'BOTTOM_OF_PIPE_TS',
41: 'FLUSH_SX_TS',
42: 'DB_CACHE_FLUSH_AND_INV',
43: 'FLUSH_AND_INV_DB_DATA_TS',
44: 'FLUSH_AND_INV_DB_META',
45: 'FLUSH_AND_INV_CB_DATA_TS',
46: 'FLUSH_AND_INV_CB_META',
47: 'CS_DONE',
48: 'PS_DONE',
49: 'FLUSH_AND_INV_CB_PIXEL_DATA',
50: 'SX_CB_RAT_ACK_REQUEST',
51: 'THREAD_TRACE_START',
52: 'THREAD_TRACE_STOP',
53: 'THREAD_TRACE_MARKER',
54: 'THREAD_TRACE_DRAW',
55: 'THREAD_TRACE_FINISH',
56: 'PIXEL_PIPE_STAT_CONTROL',
57: 'PIXEL_PIPE_STAT_DUMP',
58: 'PIXEL_PIPE_STAT_RESET',
59: 'CONTEXT_SUSPEND',
60: 'OFFCHIP_HS_DEALLOC',
61: 'ENABLE_NGG_PIPELINE',
62: 'ENABLE_PIPELINE_NOT_USED',
63: 'DRAW_DONE',
}
Reserved_0x00 = 0
SAMPLE_STREAMOUTSTATS1 = 1
SAMPLE_STREAMOUTSTATS2 = 2
SAMPLE_STREAMOUTSTATS3 = 3
CACHE_FLUSH_TS = 4
CONTEXT_DONE = 5
CACHE_FLUSH = 6
CS_PARTIAL_FLUSH = 7
VGT_STREAMOUT_SYNC = 8
EVENT_STATE_CHANGE = 9
VGT_STREAMOUT_RESET = 10
END_OF_PIPE_INCR_DE = 11
END_OF_PIPE_IB_END = 12
RST_PIX_CNT = 13
BREAK_BATCH = 14
VS_PARTIAL_FLUSH = 15
PS_PARTIAL_FLUSH = 16
FLUSH_HS_OUTPUT = 17
FLUSH_DFSM = 18
RESET_TO_LOWEST_VGT = 19
CACHE_FLUSH_AND_INV_TS_EVENT = 20
WAIT_SYNC = 21
CACHE_FLUSH_AND_INV_EVENT = 22
PERFCOUNTER_START = 23
PERFCOUNTER_STOP = 24
PIPELINESTAT_START = 25
PIPELINESTAT_STOP = 26
PERFCOUNTER_SAMPLE = 27
FLUSH_ES_OUTPUT = 28
BIN_CONF_OVERRIDE_CHECK = 29
SAMPLE_PIPELINESTAT = 30
SO_VGTSTREAMOUT_FLUSH = 31
SAMPLE_STREAMOUTSTATS = 32
RESET_VTX_CNT = 33
BLOCK_CONTEXT_DONE = 34
CS_CONTEXT_DONE = 35
VGT_FLUSH = 36
TGID_ROLLOVER = 37
SQ_NON_EVENT = 38
SC_SEND_DB_VPZ = 39
BOTTOM_OF_PIPE_TS = 40
FLUSH_SX_TS = 41
DB_CACHE_FLUSH_AND_INV = 42
FLUSH_AND_INV_DB_DATA_TS = 43
FLUSH_AND_INV_DB_META = 44
FLUSH_AND_INV_CB_DATA_TS = 45
FLUSH_AND_INV_CB_META = 46
CS_DONE = 47
PS_DONE = 48
FLUSH_AND_INV_CB_PIXEL_DATA = 49
SX_CB_RAT_ACK_REQUEST = 50
THREAD_TRACE_START = 51
THREAD_TRACE_STOP = 52
THREAD_TRACE_MARKER = 53
THREAD_TRACE_DRAW = 54
THREAD_TRACE_FINISH = 55
PIXEL_PIPE_STAT_CONTROL = 56
PIXEL_PIPE_STAT_DUMP = 57
PIXEL_PIPE_STAT_RESET = 58
CONTEXT_SUSPEND = 59
OFFCHIP_HS_DEALLOC = 60
ENABLE_NGG_PIPELINE = 61
ENABLE_PIPELINE_NOT_USED = 62
DRAW_DONE = 63
VGT_EVENT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_GROUP_CONV_SEL'
VGT_GROUP_CONV_SEL__enumvalues = {
0: 'VGT_GRP_INDEX_16',
1: 'VGT_GRP_INDEX_32',
2: 'VGT_GRP_UINT_16',
3: 'VGT_GRP_UINT_32',
4: 'VGT_GRP_SINT_16',
5: 'VGT_GRP_SINT_32',
6: 'VGT_GRP_FLOAT_32',
7: 'VGT_GRP_AUTO_PRIM',
8: 'VGT_GRP_FIX_1_23_TO_FLOAT',
}
VGT_GRP_INDEX_16 = 0
VGT_GRP_INDEX_32 = 1
VGT_GRP_UINT_16 = 2
VGT_GRP_UINT_32 = 3
VGT_GRP_SINT_16 = 4
VGT_GRP_SINT_32 = 5
VGT_GRP_FLOAT_32 = 6
VGT_GRP_AUTO_PRIM = 7
VGT_GRP_FIX_1_23_TO_FLOAT = 8
VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum
# values for enumeration 'VGT_GS_MODE_TYPE'
VGT_GS_MODE_TYPE__enumvalues = {
0: 'GS_OFF',
1: 'GS_SCENARIO_A',
2: 'GS_SCENARIO_B',
3: 'GS_SCENARIO_G',
4: 'GS_SCENARIO_C',
5: 'SPRITE_EN',
}
GS_OFF = 0
GS_SCENARIO_A = 1
GS_SCENARIO_B = 2
GS_SCENARIO_G = 3
GS_SCENARIO_C = 4
SPRITE_EN = 5
VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_GS_OUTPRIM_TYPE'
VGT_GS_OUTPRIM_TYPE__enumvalues = {
0: 'POINTLIST',
1: 'LINESTRIP',
2: 'TRISTRIP',
3: 'RECT_2D',
4: 'RECTLIST',
}
POINTLIST = 0
LINESTRIP = 1
TRISTRIP = 2
RECT_2D = 3
RECTLIST = 4
VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_INDEX_TYPE_MODE'
VGT_INDEX_TYPE_MODE__enumvalues = {
0: 'VGT_INDEX_16',
1: 'VGT_INDEX_32',
2: 'VGT_INDEX_8',
}
VGT_INDEX_16 = 0
VGT_INDEX_32 = 1
VGT_INDEX_8 = 2
VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_OUTPATH_SELECT'
VGT_OUTPATH_SELECT__enumvalues = {
0: 'VGT_OUTPATH_VTX_REUSE',
1: 'VGT_OUTPATH_GS_BLOCK',
2: 'VGT_OUTPATH_HS_BLOCK',
3: 'VGT_OUTPATH_PRIM_GEN',
4: 'VGT_OUTPATH_TE_PRIM_GEN',
5: 'VGT_OUTPATH_TE_GS_BLOCK',
6: 'VGT_OUTPATH_TE_OUTPUT',
}
VGT_OUTPATH_VTX_REUSE = 0
VGT_OUTPATH_GS_BLOCK = 1
VGT_OUTPATH_HS_BLOCK = 2
VGT_OUTPATH_PRIM_GEN = 3
VGT_OUTPATH_TE_PRIM_GEN = 4
VGT_OUTPATH_TE_GS_BLOCK = 5
VGT_OUTPATH_TE_OUTPUT = 6
VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'VGT_OUT_PRIM_TYPE'
VGT_OUT_PRIM_TYPE__enumvalues = {
0: 'VGT_OUT_POINT',
1: 'VGT_OUT_LINE',
2: 'VGT_OUT_TRI',
3: 'VGT_OUT_2D_RECT',
4: 'VGT_OUT_RECT_V0',
5: 'VGT_OUT_DUMMY_1',
6: 'VGT_OUT_DUMMY_2',
7: 'VGT_OUT_DUMMY_3',
8: 'VGT_OUT_PATCH',
9: 'VGT_OUT_LINE_ADJ',
10: 'VGT_OUT_TRI_ADJ',
}
VGT_OUT_POINT = 0
VGT_OUT_LINE = 1
VGT_OUT_TRI = 2
VGT_OUT_2D_RECT = 3
VGT_OUT_RECT_V0 = 4
VGT_OUT_DUMMY_1 = 5
VGT_OUT_DUMMY_2 = 6
VGT_OUT_DUMMY_3 = 7
VGT_OUT_PATCH = 8
VGT_OUT_LINE_ADJ = 9
VGT_OUT_TRI_ADJ = 10
VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_RDREQ_POLICY'
VGT_RDREQ_POLICY__enumvalues = {
0: 'VGT_POLICY_LRU',
1: 'VGT_POLICY_STREAM',
2: 'VGT_POLICY_BYPASS',
}
VGT_POLICY_LRU = 0
VGT_POLICY_STREAM = 1
VGT_POLICY_BYPASS = 2
VGT_RDREQ_POLICY = ctypes.c_uint32 # enum
# values for enumeration 'VGT_SPEC_DATA_READ'
VGT_SPEC_DATA_READ__enumvalues = {
0: 'VGT_SPEC_DATA_READ_AUTO',
1: 'VGT_SPEC_DATA_READ_FORCE_ON',
2: 'VGT_SPEC_DATA_READ_FORCE_OFF',
}
VGT_SPEC_DATA_READ_AUTO = 0
VGT_SPEC_DATA_READ_FORCE_ON = 1
VGT_SPEC_DATA_READ_FORCE_OFF = 2
VGT_SPEC_DATA_READ = ctypes.c_uint32 # enum
# values for enumeration 'VGT_STAGES_GS_EN'
VGT_STAGES_GS_EN__enumvalues = {
0: 'GS_STAGE_OFF',
1: 'GS_STAGE_ON',
}
GS_STAGE_OFF = 0
GS_STAGE_ON = 1
VGT_STAGES_GS_EN = ctypes.c_uint32 # enum
# values for enumeration 'VGT_STAGES_HS_EN'
VGT_STAGES_HS_EN__enumvalues = {
0: 'HS_STAGE_OFF',
1: 'HS_STAGE_ON',
}
HS_STAGE_OFF = 0
HS_STAGE_ON = 1
VGT_STAGES_HS_EN = ctypes.c_uint32 # enum
# values for enumeration 'VGT_TEMPORAL'
VGT_TEMPORAL__enumvalues = {
0: 'VGT_TEMPORAL_NORMAL',
1: 'VGT_TEMPORAL_HIGH_PRIORITY',
2: 'VGT_TEMPORAL_STREAM',
3: 'VGT_TEMPORAL_DISCARD',
}
VGT_TEMPORAL_NORMAL = 0
VGT_TEMPORAL_HIGH_PRIORITY = 1
VGT_TEMPORAL_STREAM = 2
VGT_TEMPORAL_DISCARD = 3
VGT_TEMPORAL = ctypes.c_uint32 # enum
# values for enumeration 'VGT_TESS_PARTITION'
VGT_TESS_PARTITION__enumvalues = {
0: 'PART_INTEGER',
1: 'PART_POW2',
2: 'PART_FRAC_ODD',
3: 'PART_FRAC_EVEN',
}
PART_INTEGER = 0
PART_POW2 = 1
PART_FRAC_ODD = 2
PART_FRAC_EVEN = 3
VGT_TESS_PARTITION = ctypes.c_uint32 # enum
# values for enumeration 'VGT_TESS_TOPOLOGY'
VGT_TESS_TOPOLOGY__enumvalues = {
0: 'OUTPUT_POINT',
1: 'OUTPUT_LINE',
2: 'OUTPUT_TRIANGLE_CW',
3: 'OUTPUT_TRIANGLE_CCW',
}
OUTPUT_POINT = 0
OUTPUT_LINE = 1
OUTPUT_TRIANGLE_CW = 2
OUTPUT_TRIANGLE_CCW = 3
VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum
# values for enumeration 'VGT_TESS_TYPE'
VGT_TESS_TYPE__enumvalues = {
0: 'TESS_ISOLINE',
1: 'TESS_TRIANGLE',
2: 'TESS_QUAD',
}
TESS_ISOLINE = 0
TESS_TRIANGLE = 1
TESS_QUAD = 2
VGT_TESS_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'WD_IA_DRAW_REG_XFER'
WD_IA_DRAW_REG_XFER__enumvalues = {
0: 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID',
1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN',
2: 'WD_IA_DRAW_REG_XFER_VGT_GS_OUT_PRIM_TYPE',
3: 'WD_IA_DRAW_REG_XFER_GE_CNTL',
4: 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVE_TYPE',
5: 'WD_IA_DRAW_REG_XFER_GFX_PIPE_CONTROL',
6: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN',
7: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM',
8: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1',
9: 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC',
10: 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE',
11: 'WD_IA_DRAW_REG_XFER_VGT_DRAW_PAYLOAD_CNTL',
12: 'WD_IA_DRAW_REG_XFER_GE_STEREO_CNTL',
13: 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_RESET',
14: 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_EN',
15: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR1',
16: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR2',
17: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR3',
18: 'WD_IA_DRAW_REG_XFER_GE_VRS_RATE',
19: 'WD_IA_DRAW_REG_XFER_GE_PC_ALLOC',
20: 'WD_IA_DRAW_REG_XFER_SPI_SHADER_GS_OUT_CONFIG_PS',
21: 'WD_IA_DRAW_REG_XFER_GE_GS_THROTTLE',
}
WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 0
WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1
WD_IA_DRAW_REG_XFER_VGT_GS_OUT_PRIM_TYPE = 2
WD_IA_DRAW_REG_XFER_GE_CNTL = 3
WD_IA_DRAW_REG_XFER_VGT_PRIMITIVE_TYPE = 4
WD_IA_DRAW_REG_XFER_GFX_PIPE_CONTROL = 5
WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 6
WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 7
WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 8
WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 9
WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 10
WD_IA_DRAW_REG_XFER_VGT_DRAW_PAYLOAD_CNTL = 11
WD_IA_DRAW_REG_XFER_GE_STEREO_CNTL = 12
WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_RESET = 13
WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_EN = 14
WD_IA_DRAW_REG_XFER_GE_USER_VGPR1 = 15
WD_IA_DRAW_REG_XFER_GE_USER_VGPR2 = 16
WD_IA_DRAW_REG_XFER_GE_USER_VGPR3 = 17
WD_IA_DRAW_REG_XFER_GE_VRS_RATE = 18
WD_IA_DRAW_REG_XFER_GE_PC_ALLOC = 19
WD_IA_DRAW_REG_XFER_SPI_SHADER_GS_OUT_CONFIG_PS = 20
WD_IA_DRAW_REG_XFER_GE_GS_THROTTLE = 21
WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum
# values for enumeration 'WD_IA_DRAW_SOURCE'
WD_IA_DRAW_SOURCE__enumvalues = {
0: 'WD_IA_DRAW_SOURCE_DMA',
1: 'WD_IA_DRAW_SOURCE_IMMD',
2: 'WD_IA_DRAW_SOURCE_AUTO',
3: 'WD_IA_DRAW_SOURCE_OPAQ',
}
WD_IA_DRAW_SOURCE_DMA = 0
WD_IA_DRAW_SOURCE_IMMD = 1
WD_IA_DRAW_SOURCE_AUTO = 2
WD_IA_DRAW_SOURCE_OPAQ = 3
WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'WD_IA_DRAW_TYPE'
WD_IA_DRAW_TYPE__enumvalues = {
0: 'WD_IA_DRAW_TYPE_DI_MM0',
1: 'WD_IA_DRAW_TYPE_INDX_OFF',
2: 'WD_IA_DRAW_TYPE_EVENT_INIT',
3: 'WD_IA_DRAW_TYPE_EVENT_ADDR',
4: 'WD_IA_DRAW_TYPE_REG_XFER',
5: 'WD_IA_DRAW_TYPE_MIN_INDX',
6: 'WD_IA_DRAW_TYPE_MAX_INDX',
7: 'WD_IA_DRAW_TYPE_IMM_DATA',
}
WD_IA_DRAW_TYPE_DI_MM0 = 0
WD_IA_DRAW_TYPE_INDX_OFF = 1
WD_IA_DRAW_TYPE_EVENT_INIT = 2
WD_IA_DRAW_TYPE_EVENT_ADDR = 3
WD_IA_DRAW_TYPE_REG_XFER = 4
WD_IA_DRAW_TYPE_MIN_INDX = 5
WD_IA_DRAW_TYPE_MAX_INDX = 6
WD_IA_DRAW_TYPE_IMM_DATA = 7
WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'CHA_PERF_SEL'
CHA_PERF_SEL__enumvalues = {
0: 'CHA_PERF_SEL_BUSY',
1: 'CHA_PERF_SEL_STALL_CHC0',
2: 'CHA_PERF_SEL_STALL_CHC1',
3: 'CHA_PERF_SEL_STALL_CHC2',
4: 'CHA_PERF_SEL_STALL_CHC3',
5: 'CHA_PERF_SEL_REQUEST_CHC0',
6: 'CHA_PERF_SEL_REQUEST_CHC1',
7: 'CHA_PERF_SEL_REQUEST_CHC2',
8: 'CHA_PERF_SEL_REQUEST_CHC3',
9: 'CHA_PERF_SEL_MEM_32B_WDS_CHC0',
10: 'CHA_PERF_SEL_MEM_32B_WDS_CHC1',
11: 'CHA_PERF_SEL_MEM_32B_WDS_CHC2',
12: 'CHA_PERF_SEL_MEM_32B_WDS_CHC3',
13: 'CHA_PERF_SEL_IO_32B_WDS_CHC0',
14: 'CHA_PERF_SEL_IO_32B_WDS_CHC1',
15: 'CHA_PERF_SEL_IO_32B_WDS_CHC2',
16: 'CHA_PERF_SEL_IO_32B_WDS_CHC3',
17: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0',
18: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1',
19: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2',
20: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3',
21: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0',
22: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1',
23: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2',
24: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3',
25: 'CHA_PERF_SEL_ARB_REQUESTS',
26: 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL',
27: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0',
28: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1',
29: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2',
30: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3',
31: 'CHA_PERF_SEL_CYCLE',
}
CHA_PERF_SEL_BUSY = 0
CHA_PERF_SEL_STALL_CHC0 = 1
CHA_PERF_SEL_STALL_CHC1 = 2
CHA_PERF_SEL_STALL_CHC2 = 3
CHA_PERF_SEL_STALL_CHC3 = 4
CHA_PERF_SEL_REQUEST_CHC0 = 5
CHA_PERF_SEL_REQUEST_CHC1 = 6
CHA_PERF_SEL_REQUEST_CHC2 = 7
CHA_PERF_SEL_REQUEST_CHC3 = 8
CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 9
CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 10
CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 11
CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 12
CHA_PERF_SEL_IO_32B_WDS_CHC0 = 13
CHA_PERF_SEL_IO_32B_WDS_CHC1 = 14
CHA_PERF_SEL_IO_32B_WDS_CHC2 = 15
CHA_PERF_SEL_IO_32B_WDS_CHC3 = 16
CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 17
CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 18
CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 19
CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 20
CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 21
CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 22
CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 23
CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 24
CHA_PERF_SEL_ARB_REQUESTS = 25
CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 26
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 27
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 28
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 29
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 30
CHA_PERF_SEL_CYCLE = 31
CHA_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CHC_PERF_SEL'
CHC_PERF_SEL__enumvalues = {
0: 'CHC_PERF_SEL_CYCLE',
1: 'CHC_PERF_SEL_BUSY',
2: 'CHC_PERF_SEL_STARVE',
3: 'CHC_PERF_SEL_ARB_RET_LEVEL',
4: 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY',
5: 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY',
6: 'CHC_PERF_SEL_REQ',
7: 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET',
8: 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET',
9: 'CHC_PERF_SEL_REQ_NOP_ACK',
10: 'CHC_PERF_SEL_REQ_NOP_RTN0',
11: 'CHC_PERF_SEL_REQ_READ',
12: 'CHC_PERF_SEL_REQ_READ_128B',
13: 'CHC_PERF_SEL_REQ_READ_32B',
14: 'CHC_PERF_SEL_REQ_READ_64B',
15: 'CHC_PERF_SEL_REQ_WRITE',
16: 'CHC_PERF_SEL_REQ_WRITE_32B',
17: 'CHC_PERF_SEL_REQ_WRITE_64B',
18: 'CHC_PERF_SEL_STALL_GL2_GL1',
19: 'CHC_PERF_SEL_STALL_BUFFER_FULL',
20: 'CHC_PERF_SEL_REQ_CLIENT0',
21: 'CHC_PERF_SEL_REQ_CLIENT1',
22: 'CHC_PERF_SEL_REQ_CLIENT2',
23: 'CHC_PERF_SEL_REQ_CLIENT3',
24: 'CHC_PERF_SEL_REQ_CLIENT4',
25: 'CHC_PERF_SEL_REQ_CLIENT5',
26: 'CHC_PERF_SEL_REQ_CLIENT6',
27: 'CHC_PERF_SEL_REQ_CLIENT7',
28: 'CHC_PERF_SEL_REQ_CLIENT8',
29: 'CHC_PERF_SEL_REQ_CLIENT9',
30: 'CHC_PERF_SEL_REQ_CLIENT10',
31: 'CHC_PERF_SEL_REQ_CLIENT11',
32: 'CHC_PERF_SEL_REQ_CLIENT12',
33: 'CHC_PERF_SEL_REQ_CLIENT13',
34: 'CHC_PERF_SEL_REQ_CLIENT14',
35: 'CHC_PERF_SEL_REQ_CLIENT15',
36: 'CHC_PERF_SEL_REQ_CLIENT16',
37: 'CHC_PERF_SEL_REQ_CLIENT17',
38: 'CHC_PERF_SEL_REQ_CLIENT18',
39: 'CHC_PERF_SEL_REQ_CLIENT19',
40: 'CHC_PERF_SEL_REQ_CLIENT20',
41: 'CHC_PERF_SEL_REQ_CLIENT21',
42: 'CHC_PERF_SEL_REQ_CLIENT22',
43: 'CHC_PERF_SEL_REQ_CLIENT23',
}
CHC_PERF_SEL_CYCLE = 0
CHC_PERF_SEL_BUSY = 1
CHC_PERF_SEL_STARVE = 2
CHC_PERF_SEL_ARB_RET_LEVEL = 3
CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 4
CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5
CHC_PERF_SEL_REQ = 6
CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 7
CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8
CHC_PERF_SEL_REQ_NOP_ACK = 9
CHC_PERF_SEL_REQ_NOP_RTN0 = 10
CHC_PERF_SEL_REQ_READ = 11
CHC_PERF_SEL_REQ_READ_128B = 12
CHC_PERF_SEL_REQ_READ_32B = 13
CHC_PERF_SEL_REQ_READ_64B = 14
CHC_PERF_SEL_REQ_WRITE = 15
CHC_PERF_SEL_REQ_WRITE_32B = 16
CHC_PERF_SEL_REQ_WRITE_64B = 17
CHC_PERF_SEL_STALL_GL2_GL1 = 18
CHC_PERF_SEL_STALL_BUFFER_FULL = 19
CHC_PERF_SEL_REQ_CLIENT0 = 20
CHC_PERF_SEL_REQ_CLIENT1 = 21
CHC_PERF_SEL_REQ_CLIENT2 = 22
CHC_PERF_SEL_REQ_CLIENT3 = 23
CHC_PERF_SEL_REQ_CLIENT4 = 24
CHC_PERF_SEL_REQ_CLIENT5 = 25
CHC_PERF_SEL_REQ_CLIENT6 = 26
CHC_PERF_SEL_REQ_CLIENT7 = 27
CHC_PERF_SEL_REQ_CLIENT8 = 28
CHC_PERF_SEL_REQ_CLIENT9 = 29
CHC_PERF_SEL_REQ_CLIENT10 = 30
CHC_PERF_SEL_REQ_CLIENT11 = 31
CHC_PERF_SEL_REQ_CLIENT12 = 32
CHC_PERF_SEL_REQ_CLIENT13 = 33
CHC_PERF_SEL_REQ_CLIENT14 = 34
CHC_PERF_SEL_REQ_CLIENT15 = 35
CHC_PERF_SEL_REQ_CLIENT16 = 36
CHC_PERF_SEL_REQ_CLIENT17 = 37
CHC_PERF_SEL_REQ_CLIENT18 = 38
CHC_PERF_SEL_REQ_CLIENT19 = 39
CHC_PERF_SEL_REQ_CLIENT20 = 40
CHC_PERF_SEL_REQ_CLIENT21 = 41
CHC_PERF_SEL_REQ_CLIENT22 = 42
CHC_PERF_SEL_REQ_CLIENT23 = 43
CHC_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_PERF_SEL'
GRBM_PERF_SEL__enumvalues = {
0: 'GRBM_PERF_SEL_COUNT',
1: 'GRBM_PERF_SEL_USER_DEFINED',
2: 'GRBM_PERF_SEL_GUI_ACTIVE',
3: 'GRBM_PERF_SEL_CP_BUSY',
4: 'GRBM_PERF_SEL_CP_COHER_BUSY',
5: 'GRBM_PERF_SEL_CP_DMA_BUSY',
6: 'GRBM_PERF_SEL_CB_BUSY',
7: 'GRBM_PERF_SEL_DB_BUSY',
8: 'GRBM_PERF_SEL_PA_BUSY',
9: 'GRBM_PERF_SEL_SC_BUSY',
11: 'GRBM_PERF_SEL_SPI_BUSY',
12: 'GRBM_PERF_SEL_SX_BUSY',
13: 'GRBM_PERF_SEL_TA_BUSY',
14: 'GRBM_PERF_SEL_CB_CLEAN',
15: 'GRBM_PERF_SEL_DB_CLEAN',
26: 'GRBM_PERF_SEL_BCI_BUSY',
27: 'GRBM_PERF_SEL_RLC_BUSY',
28: 'GRBM_PERF_SEL_TCP_BUSY',
29: 'GRBM_PERF_SEL_CPG_BUSY',
30: 'GRBM_PERF_SEL_CPC_BUSY',
31: 'GRBM_PERF_SEL_CPF_BUSY',
32: 'GRBM_PERF_SEL_GE_BUSY',
33: 'GRBM_PERF_SEL_GE_NO_DMA_BUSY',
34: 'GRBM_PERF_SEL_UTCL2_BUSY',
35: 'GRBM_PERF_SEL_EA_BUSY',
39: 'GRBM_PERF_SEL_UTCL1_BUSY',
40: 'GRBM_PERF_SEL_GL2CC_BUSY',
41: 'GRBM_PERF_SEL_SDMA_BUSY',
42: 'GRBM_PERF_SEL_CH_BUSY',
44: 'GRBM_PERF_SEL_PMM_BUSY',
45: 'GRBM_PERF_SEL_GUS_BUSY',
46: 'GRBM_PERF_SEL_GL1CC_BUSY',
47: 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY',
48: 'GRBM_PERF_SEL_GL1XCC_BUSY',
49: 'GRBM_PERF_SEL_PC_BUSY',
}
GRBM_PERF_SEL_COUNT = 0
GRBM_PERF_SEL_USER_DEFINED = 1
GRBM_PERF_SEL_GUI_ACTIVE = 2
GRBM_PERF_SEL_CP_BUSY = 3
GRBM_PERF_SEL_CP_COHER_BUSY = 4
GRBM_PERF_SEL_CP_DMA_BUSY = 5
GRBM_PERF_SEL_CB_BUSY = 6
GRBM_PERF_SEL_DB_BUSY = 7
GRBM_PERF_SEL_PA_BUSY = 8
GRBM_PERF_SEL_SC_BUSY = 9
GRBM_PERF_SEL_SPI_BUSY = 11
GRBM_PERF_SEL_SX_BUSY = 12
GRBM_PERF_SEL_TA_BUSY = 13
GRBM_PERF_SEL_CB_CLEAN = 14
GRBM_PERF_SEL_DB_CLEAN = 15
GRBM_PERF_SEL_BCI_BUSY = 26
GRBM_PERF_SEL_RLC_BUSY = 27
GRBM_PERF_SEL_TCP_BUSY = 28
GRBM_PERF_SEL_CPG_BUSY = 29
GRBM_PERF_SEL_CPC_BUSY = 30
GRBM_PERF_SEL_CPF_BUSY = 31
GRBM_PERF_SEL_GE_BUSY = 32
GRBM_PERF_SEL_GE_NO_DMA_BUSY = 33
GRBM_PERF_SEL_UTCL2_BUSY = 34
GRBM_PERF_SEL_EA_BUSY = 35
GRBM_PERF_SEL_UTCL1_BUSY = 39
GRBM_PERF_SEL_GL2CC_BUSY = 40
GRBM_PERF_SEL_SDMA_BUSY = 41
GRBM_PERF_SEL_CH_BUSY = 42
GRBM_PERF_SEL_PMM_BUSY = 44
GRBM_PERF_SEL_GUS_BUSY = 45
GRBM_PERF_SEL_GL1CC_BUSY = 46
GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 47
GRBM_PERF_SEL_GL1XCC_BUSY = 48
GRBM_PERF_SEL_PC_BUSY = 49
GRBM_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPC_LATENCY_STATS_SEL'
CPC_LATENCY_STATS_SEL__enumvalues = {
0: 'CPC_LATENCY_STATS_SEL_XACK_MAX',
1: 'CPC_LATENCY_STATS_SEL_XACK_MIN',
2: 'CPC_LATENCY_STATS_SEL_XACK_LAST',
3: 'CPC_LATENCY_STATS_SEL_XNACK_MAX',
4: 'CPC_LATENCY_STATS_SEL_XNACK_MIN',
5: 'CPC_LATENCY_STATS_SEL_XNACK_LAST',
6: 'CPC_LATENCY_STATS_SEL_INVAL_MAX',
7: 'CPC_LATENCY_STATS_SEL_INVAL_MIN',
8: 'CPC_LATENCY_STATS_SEL_INVAL_LAST',
}
CPC_LATENCY_STATS_SEL_XACK_MAX = 0
CPC_LATENCY_STATS_SEL_XACK_MIN = 1
CPC_LATENCY_STATS_SEL_XACK_LAST = 2
CPC_LATENCY_STATS_SEL_XNACK_MAX = 3
CPC_LATENCY_STATS_SEL_XNACK_MIN = 4
CPC_LATENCY_STATS_SEL_XNACK_LAST = 5
CPC_LATENCY_STATS_SEL_INVAL_MAX = 6
CPC_LATENCY_STATS_SEL_INVAL_MIN = 7
CPC_LATENCY_STATS_SEL_INVAL_LAST = 8
CPC_LATENCY_STATS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPC_PERFCOUNT_SEL'
CPC_PERFCOUNT_SEL__enumvalues = {
0: 'CPC_PERF_SEL_ALWAYS_COUNT',
1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE',
2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION',
5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE',
6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY',
7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF',
8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ',
9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_READ',
10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_WRITE',
11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ',
12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF',
13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE',
14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY',
15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF',
16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ',
17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_READ',
18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_WRITE',
19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ',
20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF',
21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE',
22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS',
24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION',
25: 'CPC_PERF_SEL_CPC_STAT_BUSY',
26: 'CPC_PERF_SEL_CPC_STAT_IDLE',
27: 'CPC_PERF_SEL_CPC_STAT_STALL',
28: 'CPC_PERF_SEL_CPC_TCIU_BUSY',
29: 'CPC_PERF_SEL_CPC_TCIU_IDLE',
30: 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY',
31: 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE',
32: 'CPC_PERF_SEL_CPC_UTCL2IU_STALL',
33: 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY',
34: 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY',
35: 'CPC_PERF_SEL_CPC_GCRIU_BUSY',
36: 'CPC_PERF_SEL_CPC_GCRIU_IDLE',
37: 'CPC_PERF_SEL_CPC_GCRIU_STALL',
38: 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
39: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ',
40: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ',
41: 'CPC_PERF_SEL_CPC_UTCL2IU_XACK',
42: 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK',
43: 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT',
44: 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS',
45: 'CPC_PERF_SEL_MES_THREAD0',
46: 'CPC_PERF_SEL_MES_THREAD1',
47: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS',
48: 'CPC_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
49: 'CPC_PERF_SEL_TCIU_READ_REQUEST_SENT',
50: 'CPC_PERF_SEL_GUS_WRITE_REQUEST_SENT',
51: 'CPC_PERF_SEL_GUS_READ_REQUEST_SENT',
52: 'CPC_PERF_SEL_MEC_THREAD0',
53: 'CPC_PERF_SEL_MEC_THREAD1',
54: 'CPC_PERF_SEL_MEC_THREAD2',
55: 'CPC_PERF_SEL_MEC_THREAD3',
}
CPC_PERF_SEL_ALWAYS_COUNT = 0
CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1
CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2
CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8
CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_READ = 9
CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_WRITE = 10
CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11
CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12
CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16
CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_READ = 17
CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_WRITE = 18
CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19
CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20
CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21
CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22
CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23
CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24
CPC_PERF_SEL_CPC_STAT_BUSY = 25
CPC_PERF_SEL_CPC_STAT_IDLE = 26
CPC_PERF_SEL_CPC_STAT_STALL = 27
CPC_PERF_SEL_CPC_TCIU_BUSY = 28
CPC_PERF_SEL_CPC_TCIU_IDLE = 29
CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 30
CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 31
CPC_PERF_SEL_CPC_UTCL2IU_STALL = 32
CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 33
CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 34
CPC_PERF_SEL_CPC_GCRIU_BUSY = 35
CPC_PERF_SEL_CPC_GCRIU_IDLE = 36
CPC_PERF_SEL_CPC_GCRIU_STALL = 37
CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 38
CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 39
CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 40
CPC_PERF_SEL_CPC_UTCL2IU_XACK = 41
CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 42
CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 43
CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 44
CPC_PERF_SEL_MES_THREAD0 = 45
CPC_PERF_SEL_MES_THREAD1 = 46
CPC_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 47
CPC_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 48
CPC_PERF_SEL_TCIU_READ_REQUEST_SENT = 49
CPC_PERF_SEL_GUS_WRITE_REQUEST_SENT = 50
CPC_PERF_SEL_GUS_READ_REQUEST_SENT = 51
CPC_PERF_SEL_MEC_THREAD0 = 52
CPC_PERF_SEL_MEC_THREAD1 = 53
CPC_PERF_SEL_MEC_THREAD2 = 54
CPC_PERF_SEL_MEC_THREAD3 = 55
CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPF_LATENCY_STATS_SEL'
CPF_LATENCY_STATS_SEL__enumvalues = {
0: 'CPF_LATENCY_STATS_SEL_XACK_MAX',
1: 'CPF_LATENCY_STATS_SEL_XACK_MIN',
2: 'CPF_LATENCY_STATS_SEL_XACK_LAST',
3: 'CPF_LATENCY_STATS_SEL_XNACK_MAX',
4: 'CPF_LATENCY_STATS_SEL_XNACK_MIN',
5: 'CPF_LATENCY_STATS_SEL_XNACK_LAST',
6: 'CPF_LATENCY_STATS_SEL_READ_MAX',
7: 'CPF_LATENCY_STATS_SEL_READ_MIN',
8: 'CPF_LATENCY_STATS_SEL_READ_LAST',
9: 'CPF_LATENCY_STATS_SEL_INVAL_MAX',
10: 'CPF_LATENCY_STATS_SEL_INVAL_MIN',
11: 'CPF_LATENCY_STATS_SEL_INVAL_LAST',
}
CPF_LATENCY_STATS_SEL_XACK_MAX = 0
CPF_LATENCY_STATS_SEL_XACK_MIN = 1
CPF_LATENCY_STATS_SEL_XACK_LAST = 2
CPF_LATENCY_STATS_SEL_XNACK_MAX = 3
CPF_LATENCY_STATS_SEL_XNACK_MIN = 4
CPF_LATENCY_STATS_SEL_XNACK_LAST = 5
CPF_LATENCY_STATS_SEL_READ_MAX = 6
CPF_LATENCY_STATS_SEL_READ_MIN = 7
CPF_LATENCY_STATS_SEL_READ_LAST = 8
CPF_LATENCY_STATS_SEL_INVAL_MAX = 9
CPF_LATENCY_STATS_SEL_INVAL_MIN = 10
CPF_LATENCY_STATS_SEL_INVAL_LAST = 11
CPF_LATENCY_STATS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPF_PERFCOUNTWINDOW_SEL'
CPF_PERFCOUNTWINDOW_SEL__enumvalues = {
0: 'CPF_PERFWINDOW_SEL_CSF',
1: 'CPF_PERFWINDOW_SEL_HQD1',
2: 'CPF_PERFWINDOW_SEL_HQD2',
3: 'CPF_PERFWINDOW_SEL_RDMA',
4: 'CPF_PERFWINDOW_SEL_RWPP',
}
CPF_PERFWINDOW_SEL_CSF = 0
CPF_PERFWINDOW_SEL_HQD1 = 1
CPF_PERFWINDOW_SEL_HQD2 = 2
CPF_PERFWINDOW_SEL_RDMA = 3
CPF_PERFWINDOW_SEL_RWPP = 4
CPF_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPF_PERFCOUNT_SEL'
CPF_PERFCOUNT_SEL__enumvalues = {
0: 'CPF_PERF_SEL_ALWAYS_COUNT',
2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE',
3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS',
4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING',
5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1',
6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2',
7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE',
10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR',
11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS',
12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT',
13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID',
14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID',
15: 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT',
16: 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT',
17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS',
19: 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION',
20: 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION',
21: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE',
22: 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
23: 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT',
24: 'CPF_PERF_SEL_CPF_STAT_BUSY',
25: 'CPF_PERF_SEL_CPF_STAT_IDLE',
26: 'CPF_PERF_SEL_CPF_STAT_STALL',
27: 'CPF_PERF_SEL_CPF_TCIU_BUSY',
28: 'CPF_PERF_SEL_CPF_TCIU_IDLE',
29: 'CPF_PERF_SEL_CPF_TCIU_STALL',
30: 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY',
31: 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE',
32: 'CPF_PERF_SEL_CPF_UTCL2IU_STALL',
33: 'CPF_PERF_SEL_CPF_GCRIU_BUSY',
34: 'CPF_PERF_SEL_CPF_GCRIU_IDLE',
35: 'CPF_PERF_SEL_CPF_GCRIU_STALL',
36: 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
37: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB',
38: 'CPF_PERF_SEL_CPF_UTCL2IU_XACK',
39: 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK',
40: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ',
41: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE',
42: 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY',
43: 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY',
}
CPF_PERF_SEL_ALWAYS_COUNT = 0
CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2
CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 7
CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10
CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11
CPF_PERF_SEL_GRBM_DWORDS_SENT = 12
CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13
CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14
CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 15
CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 16
CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17
CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18
CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 19
CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 20
CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 21
CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 22
CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 23
CPF_PERF_SEL_CPF_STAT_BUSY = 24
CPF_PERF_SEL_CPF_STAT_IDLE = 25
CPF_PERF_SEL_CPF_STAT_STALL = 26
CPF_PERF_SEL_CPF_TCIU_BUSY = 27
CPF_PERF_SEL_CPF_TCIU_IDLE = 28
CPF_PERF_SEL_CPF_TCIU_STALL = 29
CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 30
CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 31
CPF_PERF_SEL_CPF_UTCL2IU_STALL = 32
CPF_PERF_SEL_CPF_GCRIU_BUSY = 33
CPF_PERF_SEL_CPF_GCRIU_IDLE = 34
CPF_PERF_SEL_CPF_GCRIU_STALL = 35
CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 36
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 37
CPF_PERF_SEL_CPF_UTCL2IU_XACK = 38
CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 39
CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 40
CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 41
CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 42
CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 43
CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPF_SCRATCH_REG_ATOMIC_OP'
CPF_SCRATCH_REG_ATOMIC_OP__enumvalues = {
0: 'CPF_SCRATCH_REG_ATOMIC_ADD',
1: 'CPF_SCRATCH_REG_ATOMIC_SUB',
2: 'CPF_SCRATCH_REG_ATOMIC_OR',
3: 'CPF_SCRATCH_REG_ATOMIC_AND',
4: 'CPF_SCRATCH_REG_ATOMIC_NOT',
5: 'CPF_SCRATCH_REG_ATOMIC_MIN',
6: 'CPF_SCRATCH_REG_ATOMIC_MAX',
7: 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP',
}
CPF_SCRATCH_REG_ATOMIC_ADD = 0
CPF_SCRATCH_REG_ATOMIC_SUB = 1
CPF_SCRATCH_REG_ATOMIC_OR = 2
CPF_SCRATCH_REG_ATOMIC_AND = 3
CPF_SCRATCH_REG_ATOMIC_NOT = 4
CPF_SCRATCH_REG_ATOMIC_MIN = 5
CPF_SCRATCH_REG_ATOMIC_MAX = 6
CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 7
CPF_SCRATCH_REG_ATOMIC_OP = ctypes.c_uint32 # enum
# values for enumeration 'CPG_LATENCY_STATS_SEL'
CPG_LATENCY_STATS_SEL__enumvalues = {
0: 'CPG_LATENCY_STATS_SEL_XACK_MAX',
1: 'CPG_LATENCY_STATS_SEL_XACK_MIN',
2: 'CPG_LATENCY_STATS_SEL_XACK_LAST',
3: 'CPG_LATENCY_STATS_SEL_XNACK_MAX',
4: 'CPG_LATENCY_STATS_SEL_XNACK_MIN',
5: 'CPG_LATENCY_STATS_SEL_XNACK_LAST',
6: 'CPG_LATENCY_STATS_SEL_WRITE_MAX',
7: 'CPG_LATENCY_STATS_SEL_WRITE_MIN',
8: 'CPG_LATENCY_STATS_SEL_WRITE_LAST',
9: 'CPG_LATENCY_STATS_SEL_READ_MAX',
10: 'CPG_LATENCY_STATS_SEL_READ_MIN',
11: 'CPG_LATENCY_STATS_SEL_READ_LAST',
12: 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX',
13: 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN',
14: 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST',
15: 'CPG_LATENCY_STATS_SEL_INVAL_MAX',
16: 'CPG_LATENCY_STATS_SEL_INVAL_MIN',
17: 'CPG_LATENCY_STATS_SEL_INVAL_LAST',
}
CPG_LATENCY_STATS_SEL_XACK_MAX = 0
CPG_LATENCY_STATS_SEL_XACK_MIN = 1
CPG_LATENCY_STATS_SEL_XACK_LAST = 2
CPG_LATENCY_STATS_SEL_XNACK_MAX = 3
CPG_LATENCY_STATS_SEL_XNACK_MIN = 4
CPG_LATENCY_STATS_SEL_XNACK_LAST = 5
CPG_LATENCY_STATS_SEL_WRITE_MAX = 6
CPG_LATENCY_STATS_SEL_WRITE_MIN = 7
CPG_LATENCY_STATS_SEL_WRITE_LAST = 8
CPG_LATENCY_STATS_SEL_READ_MAX = 9
CPG_LATENCY_STATS_SEL_READ_MIN = 10
CPG_LATENCY_STATS_SEL_READ_LAST = 11
CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 12
CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 13
CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 14
CPG_LATENCY_STATS_SEL_INVAL_MAX = 15
CPG_LATENCY_STATS_SEL_INVAL_MIN = 16
CPG_LATENCY_STATS_SEL_INVAL_LAST = 17
CPG_LATENCY_STATS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPG_PERFCOUNTWINDOW_SEL'
CPG_PERFCOUNTWINDOW_SEL__enumvalues = {
0: 'CPG_PERFWINDOW_SEL_PFP',
1: 'CPG_PERFWINDOW_SEL_ME',
2: 'CPG_PERFWINDOW_SEL_CE',
3: 'CPG_PERFWINDOW_SEL_MES',
4: 'CPG_PERFWINDOW_SEL_MEC1',
5: 'CPG_PERFWINDOW_SEL_MEC2',
6: 'CPG_PERFWINDOW_SEL_DFY',
7: 'CPG_PERFWINDOW_SEL_DMA',
8: 'CPG_PERFWINDOW_SEL_SHADOW',
9: 'CPG_PERFWINDOW_SEL_RB',
10: 'CPG_PERFWINDOW_SEL_CEDMA',
11: 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR',
12: 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR',
13: 'CPG_PERFWINDOW_SEL_PQ1',
14: 'CPG_PERFWINDOW_SEL_PQ2',
15: 'CPG_PERFWINDOW_SEL_PQ3',
16: 'CPG_PERFWINDOW_SEL_MEMWR',
17: 'CPG_PERFWINDOW_SEL_MEMRD',
18: 'CPG_PERFWINDOW_SEL_VGT0',
19: 'CPG_PERFWINDOW_SEL_VGT1',
20: 'CPG_PERFWINDOW_SEL_APPEND',
21: 'CPG_PERFWINDOW_SEL_QURD',
22: 'CPG_PERFWINDOW_SEL_DDID',
23: 'CPG_PERFWINDOW_SEL_SR',
24: 'CPG_PERFWINDOW_SEL_QU_EOP',
25: 'CPG_PERFWINDOW_SEL_QU_STRM',
26: 'CPG_PERFWINDOW_SEL_QU_PIPE',
27: 'CPG_PERFWINDOW_SEL_RESERVED1',
28: 'CPG_PERFWINDOW_SEL_CPC_IC',
29: 'CPG_PERFWINDOW_SEL_RESERVED2',
30: 'CPG_PERFWINDOW_SEL_CPG_IC',
}
CPG_PERFWINDOW_SEL_PFP = 0
CPG_PERFWINDOW_SEL_ME = 1
CPG_PERFWINDOW_SEL_CE = 2
CPG_PERFWINDOW_SEL_MES = 3
CPG_PERFWINDOW_SEL_MEC1 = 4
CPG_PERFWINDOW_SEL_MEC2 = 5
CPG_PERFWINDOW_SEL_DFY = 6
CPG_PERFWINDOW_SEL_DMA = 7
CPG_PERFWINDOW_SEL_SHADOW = 8
CPG_PERFWINDOW_SEL_RB = 9
CPG_PERFWINDOW_SEL_CEDMA = 10
CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 11
CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 12
CPG_PERFWINDOW_SEL_PQ1 = 13
CPG_PERFWINDOW_SEL_PQ2 = 14
CPG_PERFWINDOW_SEL_PQ3 = 15
CPG_PERFWINDOW_SEL_MEMWR = 16
CPG_PERFWINDOW_SEL_MEMRD = 17
CPG_PERFWINDOW_SEL_VGT0 = 18
CPG_PERFWINDOW_SEL_VGT1 = 19
CPG_PERFWINDOW_SEL_APPEND = 20
CPG_PERFWINDOW_SEL_QURD = 21
CPG_PERFWINDOW_SEL_DDID = 22
CPG_PERFWINDOW_SEL_SR = 23
CPG_PERFWINDOW_SEL_QU_EOP = 24
CPG_PERFWINDOW_SEL_QU_STRM = 25
CPG_PERFWINDOW_SEL_QU_PIPE = 26
CPG_PERFWINDOW_SEL_RESERVED1 = 27
CPG_PERFWINDOW_SEL_CPC_IC = 28
CPG_PERFWINDOW_SEL_RESERVED2 = 29
CPG_PERFWINDOW_SEL_CPG_IC = 30
CPG_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPG_PERFCOUNT_SEL'
CPG_PERFCOUNT_SEL__enumvalues = {
0: 'CPG_PERF_SEL_ALWAYS_COUNT',
1: 'CPG_PERF_SEL_RBIU_FIFO_FULL',
4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT',
5: 'CPG_PERF_SEL_ME_PARSER_BUSY',
6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS',
7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS',
9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS',
10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS',
11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS',
12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ',
13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ',
14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX',
15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS',
16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE',
17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM',
18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY',
19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY',
20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY',
21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ',
22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP',
23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ',
24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX',
25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU',
26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS',
27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH',
28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER',
29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER',
31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY',
32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID',
33: 'CPG_PERF_SEL_REGISTER_CLK_VALID',
34: 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT',
35: 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT',
36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP',
37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE',
38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO',
39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO',
41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ',
42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG',
43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER',
44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE',
45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS',
46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS',
48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION',
49: 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
50: 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT',
51: 'CPG_PERF_SEL_CPG_STAT_BUSY',
52: 'CPG_PERF_SEL_CPG_STAT_IDLE',
53: 'CPG_PERF_SEL_CPG_STAT_STALL',
54: 'CPG_PERF_SEL_CPG_TCIU_BUSY',
55: 'CPG_PERF_SEL_CPG_TCIU_IDLE',
56: 'CPG_PERF_SEL_CPG_TCIU_STALL',
57: 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY',
58: 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE',
59: 'CPG_PERF_SEL_CPG_UTCL2IU_STALL',
60: 'CPG_PERF_SEL_CPG_GCRIU_BUSY',
61: 'CPG_PERF_SEL_CPG_GCRIU_IDLE',
62: 'CPG_PERF_SEL_CPG_GCRIU_STALL',
63: 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
64: 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY',
65: 'CPG_PERF_SEL_CPG_UTCL2IU_XACK',
66: 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK',
67: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY',
68: 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT',
69: 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS',
70: 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT',
71: 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS',
72: 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT',
73: 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS',
74: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1',
75: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1',
76: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2',
77: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2',
78: 'CPG_PERF_SEL_DMA_BUSY',
79: 'CPG_PERF_SEL_DMA_STARVED',
80: 'CPG_PERF_SEL_DMA_STALLED',
81: 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL',
82: 'CPG_PERF_SEL_PFP_PWS_STALLED0',
83: 'CPG_PERF_SEL_ME_PWS_STALLED0',
84: 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS0',
85: 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS0',
86: 'CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL0',
87: 'CPG_PERF_SEL_PFP_PWS_STALLED1',
88: 'CPG_PERF_SEL_ME_PWS_STALLED1',
89: 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS1',
90: 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS1',
91: 'CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL1',
}
CPG_PERF_SEL_ALWAYS_COUNT = 0
CPG_PERF_SEL_RBIU_FIFO_FULL = 1
CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4
CPG_PERF_SEL_ME_PARSER_BUSY = 5
CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6
CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7
CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9
CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10
CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11
CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12
CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13
CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14
CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15
CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16
CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17
CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18
CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19
CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20
CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21
CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22
CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23
CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24
CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25
CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26
CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27
CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28
CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29
CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31
CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32
CPG_PERF_SEL_REGISTER_CLK_VALID = 33
CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 34
CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 35
CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36
CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37
CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38
CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39
CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41
CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42
CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43
CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44
CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45
CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46
CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47
CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48
CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 49
CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 50
CPG_PERF_SEL_CPG_STAT_BUSY = 51
CPG_PERF_SEL_CPG_STAT_IDLE = 52
CPG_PERF_SEL_CPG_STAT_STALL = 53
CPG_PERF_SEL_CPG_TCIU_BUSY = 54
CPG_PERF_SEL_CPG_TCIU_IDLE = 55
CPG_PERF_SEL_CPG_TCIU_STALL = 56
CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 57
CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 58
CPG_PERF_SEL_CPG_UTCL2IU_STALL = 59
CPG_PERF_SEL_CPG_GCRIU_BUSY = 60
CPG_PERF_SEL_CPG_GCRIU_IDLE = 61
CPG_PERF_SEL_CPG_GCRIU_STALL = 62
CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 63
CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 64
CPG_PERF_SEL_CPG_UTCL2IU_XACK = 65
CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 66
CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 67
CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 68
CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 69
CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 70
CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 71
CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 72
CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 73
CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 74
CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 75
CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 76
CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 77
CPG_PERF_SEL_DMA_BUSY = 78
CPG_PERF_SEL_DMA_STARVED = 79
CPG_PERF_SEL_DMA_STALLED = 80
CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 81
CPG_PERF_SEL_PFP_PWS_STALLED0 = 82
CPG_PERF_SEL_ME_PWS_STALLED0 = 83
CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS0 = 84
CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS0 = 85
CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL0 = 86
CPG_PERF_SEL_PFP_PWS_STALLED1 = 87
CPG_PERF_SEL_ME_PWS_STALLED1 = 88
CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS1 = 89
CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS1 = 90
CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL1 = 91
CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CP_ALPHA_TAG_RAM_SEL'
CP_ALPHA_TAG_RAM_SEL__enumvalues = {
0: 'CPG_TAG_RAM',
1: 'CPC_TAG_RAM',
2: 'CPF_TAG_RAM',
3: 'RSV_TAG_RAM',
}
CPG_TAG_RAM = 0
CPC_TAG_RAM = 1
CPF_TAG_RAM = 2
RSV_TAG_RAM = 3
CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CP_DDID_CNTL_MODE'
CP_DDID_CNTL_MODE__enumvalues = {
0: 'STALL',
1: 'OVERRUN',
}
STALL = 0
OVERRUN = 1
CP_DDID_CNTL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CP_DDID_CNTL_SIZE'
CP_DDID_CNTL_SIZE__enumvalues = {
0: 'SIZE_8K',
1: 'SIZE_16K',
}
SIZE_8K = 0
SIZE_16K = 1
CP_DDID_CNTL_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'CP_DDID_CNTL_VMID_SEL'
CP_DDID_CNTL_VMID_SEL__enumvalues = {
0: 'DDID_VMID_PIPE',
1: 'DDID_VMID_CNTL',
}
DDID_VMID_PIPE = 0
DDID_VMID_CNTL = 1
CP_DDID_CNTL_VMID_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CP_ME_ID'
CP_ME_ID__enumvalues = {
0: 'ME_ID0',
1: 'ME_ID1',
2: 'ME_ID2',
3: 'ME_ID3',
}
ME_ID0 = 0
ME_ID1 = 1
ME_ID2 = 2
ME_ID3 = 3
CP_ME_ID = ctypes.c_uint32 # enum
# values for enumeration 'CP_PIPE_ID'
CP_PIPE_ID__enumvalues = {
0: 'PIPE_ID0',
1: 'PIPE_ID1',
2: 'PIPE_ID2',
3: 'PIPE_ID3',
}
PIPE_ID0 = 0
PIPE_ID1 = 1
PIPE_ID2 = 2
PIPE_ID3 = 3
CP_PIPE_ID = ctypes.c_uint32 # enum
# values for enumeration 'CP_RING_ID'
CP_RING_ID__enumvalues = {
0: 'RINGID0',
1: 'RINGID1',
2: 'RINGID2',
3: 'RINGID3',
}
RINGID0 = 0
RINGID1 = 1
RINGID2 = 2
RINGID3 = 3
CP_RING_ID = ctypes.c_uint32 # enum
# values for enumeration 'GCRPerfSel'
GCRPerfSel__enumvalues = {
0: 'GCR_PERF_SEL_NONE',
1: 'GCR_PERF_SEL_SDMA0_ALL_REQ',
2: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ',
3: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ',
4: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ',
5: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ',
6: 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ',
7: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ',
8: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ',
9: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ',
10: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ',
11: 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ',
12: 'GCR_PERF_SEL_SDMA0_METADATA_REQ',
13: 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ',
14: 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ',
15: 'GCR_PERF_SEL_SDMA0_TCP_REQ',
16: 'GCR_PERF_SEL_SDMA0_GL1_TLB_SHOOTDOWN_REQ',
17: 'GCR_PERF_SEL_SDMA1_ALL_REQ',
18: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ',
19: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ',
20: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ',
21: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ',
22: 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ',
23: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ',
24: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ',
25: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ',
26: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ',
27: 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ',
28: 'GCR_PERF_SEL_SDMA1_METADATA_REQ',
29: 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ',
30: 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ',
31: 'GCR_PERF_SEL_SDMA1_TCP_REQ',
32: 'GCR_PERF_SEL_SDMA1_GL1_TLB_SHOOTDOWN_REQ',
33: 'GCR_PERF_SEL_CPC_ALL_REQ',
34: 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ',
35: 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ',
36: 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ',
37: 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ',
38: 'GCR_PERF_SEL_CPC_GL2_ALL_REQ',
39: 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ',
40: 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ',
41: 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ',
42: 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ',
43: 'GCR_PERF_SEL_CPC_GL1_ALL_REQ',
44: 'GCR_PERF_SEL_CPC_METADATA_REQ',
45: 'GCR_PERF_SEL_CPC_SQC_DATA_REQ',
46: 'GCR_PERF_SEL_CPC_SQC_INST_REQ',
47: 'GCR_PERF_SEL_CPC_TCP_REQ',
48: 'GCR_PERF_SEL_CPC_GL1_TLB_SHOOTDOWN_REQ',
49: 'GCR_PERF_SEL_CPG_ALL_REQ',
50: 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ',
51: 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ',
52: 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ',
53: 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ',
54: 'GCR_PERF_SEL_CPG_GL2_ALL_REQ',
55: 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ',
56: 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ',
57: 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ',
58: 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ',
59: 'GCR_PERF_SEL_CPG_GL1_ALL_REQ',
60: 'GCR_PERF_SEL_CPG_METADATA_REQ',
61: 'GCR_PERF_SEL_CPG_SQC_DATA_REQ',
62: 'GCR_PERF_SEL_CPG_SQC_INST_REQ',
63: 'GCR_PERF_SEL_CPG_TCP_REQ',
64: 'GCR_PERF_SEL_CPG_GL1_TLB_SHOOTDOWN_REQ',
65: 'GCR_PERF_SEL_CPF_ALL_REQ',
66: 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ',
67: 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ',
68: 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ',
69: 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ',
70: 'GCR_PERF_SEL_CPF_GL2_ALL_REQ',
71: 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ',
72: 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ',
73: 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ',
74: 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ',
75: 'GCR_PERF_SEL_CPF_GL1_ALL_REQ',
76: 'GCR_PERF_SEL_CPF_METADATA_REQ',
77: 'GCR_PERF_SEL_CPF_SQC_DATA_REQ',
78: 'GCR_PERF_SEL_CPF_SQC_INST_REQ',
79: 'GCR_PERF_SEL_CPF_TCP_REQ',
80: 'GCR_PERF_SEL_CPF_GL1_TLB_SHOOTDOWN_REQ',
81: 'GCR_PERF_SEL_VIRT_REQ',
82: 'GCR_PERF_SEL_PHY_REQ',
83: 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ',
84: 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ',
85: 'GCR_PERF_SEL_ALL_REQ',
86: 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ',
87: 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ',
88: 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ',
89: 'GCR_PERF_SEL_UTCL2_REQ',
90: 'GCR_PERF_SEL_UTCL2_RET',
91: 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT',
92: 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ',
93: 'GCR_PERF_SEL_UTCL2_FILTERED_RET',
94: 'GCR_PERF_SEL_PMM_ABIT_NUM_FLUSH',
95: 'GCR_PERF_SEL_PMM_ABIT_FLUSH_ONGOING',
96: 'GCR_PERF_SEL_PMM_NUM_INTERRUPT',
97: 'GCR_PERF_SEL_PMM_STALL_PMM_IH_CREDITS',
98: 'GCR_PERF_SEL_PMM_INTERRUPT_READY_TO_SEND',
99: 'GCR_PERF_SEL_PMM_ABIT_TIMER_FLUSH',
100: 'GCR_PERF_SEL_PMM_ABIT_FORCE_FLUSH',
101: 'GCR_PERF_SEL_PMM_ABIT_FLUSH_INTERRUPT',
102: 'GCR_PERF_SEL_PMM_ALOG_INTERRUPT',
103: 'GCR_PERF_SEL_PMM_MAM_FLUSH_REQ',
104: 'GCR_PERF_SEL_PMM_MAM_FLUSH_RESP',
105: 'GCR_PERF_SEL_PMM_RLC_CGCG_REQ',
106: 'GCR_PERF_SEL_PMM_RLC_CGCG_RESP',
107: 'GCR_PERF_SEL_RLC_ALL_REQ',
108: 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ',
109: 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ',
110: 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ',
111: 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ',
112: 'GCR_PERF_SEL_RLC_GL2_ALL_REQ',
113: 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ',
114: 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ',
115: 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ',
116: 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ',
117: 'GCR_PERF_SEL_RLC_GL1_ALL_REQ',
118: 'GCR_PERF_SEL_RLC_METADATA_REQ',
119: 'GCR_PERF_SEL_RLC_SQC_DATA_REQ',
120: 'GCR_PERF_SEL_RLC_SQC_INST_REQ',
121: 'GCR_PERF_SEL_RLC_TCP_REQ',
122: 'GCR_PERF_SEL_RLC_GL1_TLB_SHOOTDOWN_REQ',
123: 'GCR_PERF_SEL_PM_ALL_REQ',
124: 'GCR_PERF_SEL_PM_GL2_RANGE_REQ',
125: 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ',
126: 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ',
127: 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ',
128: 'GCR_PERF_SEL_PM_GL2_ALL_REQ',
129: 'GCR_PERF_SEL_PM_GL1_RANGE_REQ',
130: 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ',
131: 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ',
132: 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ',
133: 'GCR_PERF_SEL_PM_GL1_ALL_REQ',
134: 'GCR_PERF_SEL_PM_METADATA_REQ',
135: 'GCR_PERF_SEL_PM_SQC_DATA_REQ',
136: 'GCR_PERF_SEL_PM_SQC_INST_REQ',
137: 'GCR_PERF_SEL_PM_TCP_REQ',
138: 'GCR_PERF_SEL_PM_GL1_TLB_SHOOTDOWN_REQ',
139: 'GCR_PERF_SEL_PIO_ALL_REQ',
140: 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ',
141: 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ',
142: 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ',
143: 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ',
144: 'GCR_PERF_SEL_PIO_GL2_ALL_REQ',
145: 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ',
146: 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ',
147: 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ',
148: 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ',
149: 'GCR_PERF_SEL_PIO_GL1_ALL_REQ',
150: 'GCR_PERF_SEL_PIO_METADATA_REQ',
151: 'GCR_PERF_SEL_PIO_SQC_DATA_REQ',
152: 'GCR_PERF_SEL_PIO_SQC_INST_REQ',
153: 'GCR_PERF_SEL_PIO_TCP_REQ',
154: 'GCR_PERF_SEL_PIO_GL1_TLB_SHOOTDOWN_REQ',
}
GCR_PERF_SEL_NONE = 0
GCR_PERF_SEL_SDMA0_ALL_REQ = 1
GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 2
GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 3
GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 4
GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 5
GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 6
GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 7
GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 8
GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 9
GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 10
GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 11
GCR_PERF_SEL_SDMA0_METADATA_REQ = 12
GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 13
GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 14
GCR_PERF_SEL_SDMA0_TCP_REQ = 15
GCR_PERF_SEL_SDMA0_GL1_TLB_SHOOTDOWN_REQ = 16
GCR_PERF_SEL_SDMA1_ALL_REQ = 17
GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 18
GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 19
GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 20
GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 21
GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 22
GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 23
GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 24
GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 25
GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 26
GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 27
GCR_PERF_SEL_SDMA1_METADATA_REQ = 28
GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 29
GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 30
GCR_PERF_SEL_SDMA1_TCP_REQ = 31
GCR_PERF_SEL_SDMA1_GL1_TLB_SHOOTDOWN_REQ = 32
GCR_PERF_SEL_CPC_ALL_REQ = 33
GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 34
GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 35
GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 36
GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 37
GCR_PERF_SEL_CPC_GL2_ALL_REQ = 38
GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 39
GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 40
GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 41
GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 42
GCR_PERF_SEL_CPC_GL1_ALL_REQ = 43
GCR_PERF_SEL_CPC_METADATA_REQ = 44
GCR_PERF_SEL_CPC_SQC_DATA_REQ = 45
GCR_PERF_SEL_CPC_SQC_INST_REQ = 46
GCR_PERF_SEL_CPC_TCP_REQ = 47
GCR_PERF_SEL_CPC_GL1_TLB_SHOOTDOWN_REQ = 48
GCR_PERF_SEL_CPG_ALL_REQ = 49
GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 50
GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 51
GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 52
GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 53
GCR_PERF_SEL_CPG_GL2_ALL_REQ = 54
GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 55
GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 56
GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 57
GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 58
GCR_PERF_SEL_CPG_GL1_ALL_REQ = 59
GCR_PERF_SEL_CPG_METADATA_REQ = 60
GCR_PERF_SEL_CPG_SQC_DATA_REQ = 61
GCR_PERF_SEL_CPG_SQC_INST_REQ = 62
GCR_PERF_SEL_CPG_TCP_REQ = 63
GCR_PERF_SEL_CPG_GL1_TLB_SHOOTDOWN_REQ = 64
GCR_PERF_SEL_CPF_ALL_REQ = 65
GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 66
GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 67
GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 68
GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 69
GCR_PERF_SEL_CPF_GL2_ALL_REQ = 70
GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 71
GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 72
GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 73
GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 74
GCR_PERF_SEL_CPF_GL1_ALL_REQ = 75
GCR_PERF_SEL_CPF_METADATA_REQ = 76
GCR_PERF_SEL_CPF_SQC_DATA_REQ = 77
GCR_PERF_SEL_CPF_SQC_INST_REQ = 78
GCR_PERF_SEL_CPF_TCP_REQ = 79
GCR_PERF_SEL_CPF_GL1_TLB_SHOOTDOWN_REQ = 80
GCR_PERF_SEL_VIRT_REQ = 81
GCR_PERF_SEL_PHY_REQ = 82
GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 83
GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 84
GCR_PERF_SEL_ALL_REQ = 85
GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 86
GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 87
GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 88
GCR_PERF_SEL_UTCL2_REQ = 89
GCR_PERF_SEL_UTCL2_RET = 90
GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 91
GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 92
GCR_PERF_SEL_UTCL2_FILTERED_RET = 93
GCR_PERF_SEL_PMM_ABIT_NUM_FLUSH = 94
GCR_PERF_SEL_PMM_ABIT_FLUSH_ONGOING = 95
GCR_PERF_SEL_PMM_NUM_INTERRUPT = 96
GCR_PERF_SEL_PMM_STALL_PMM_IH_CREDITS = 97
GCR_PERF_SEL_PMM_INTERRUPT_READY_TO_SEND = 98
GCR_PERF_SEL_PMM_ABIT_TIMER_FLUSH = 99
GCR_PERF_SEL_PMM_ABIT_FORCE_FLUSH = 100
GCR_PERF_SEL_PMM_ABIT_FLUSH_INTERRUPT = 101
GCR_PERF_SEL_PMM_ALOG_INTERRUPT = 102
GCR_PERF_SEL_PMM_MAM_FLUSH_REQ = 103
GCR_PERF_SEL_PMM_MAM_FLUSH_RESP = 104
GCR_PERF_SEL_PMM_RLC_CGCG_REQ = 105
GCR_PERF_SEL_PMM_RLC_CGCG_RESP = 106
GCR_PERF_SEL_RLC_ALL_REQ = 107
GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 108
GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 109
GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 110
GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 111
GCR_PERF_SEL_RLC_GL2_ALL_REQ = 112
GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 113
GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 114
GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 115
GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 116
GCR_PERF_SEL_RLC_GL1_ALL_REQ = 117
GCR_PERF_SEL_RLC_METADATA_REQ = 118
GCR_PERF_SEL_RLC_SQC_DATA_REQ = 119
GCR_PERF_SEL_RLC_SQC_INST_REQ = 120
GCR_PERF_SEL_RLC_TCP_REQ = 121
GCR_PERF_SEL_RLC_GL1_TLB_SHOOTDOWN_REQ = 122
GCR_PERF_SEL_PM_ALL_REQ = 123
GCR_PERF_SEL_PM_GL2_RANGE_REQ = 124
GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 125
GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 126
GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 127
GCR_PERF_SEL_PM_GL2_ALL_REQ = 128
GCR_PERF_SEL_PM_GL1_RANGE_REQ = 129
GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 130
GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 131
GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 132
GCR_PERF_SEL_PM_GL1_ALL_REQ = 133
GCR_PERF_SEL_PM_METADATA_REQ = 134
GCR_PERF_SEL_PM_SQC_DATA_REQ = 135
GCR_PERF_SEL_PM_SQC_INST_REQ = 136
GCR_PERF_SEL_PM_TCP_REQ = 137
GCR_PERF_SEL_PM_GL1_TLB_SHOOTDOWN_REQ = 138
GCR_PERF_SEL_PIO_ALL_REQ = 139
GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 140
GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 141
GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 142
GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 143
GCR_PERF_SEL_PIO_GL2_ALL_REQ = 144
GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 145
GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 146
GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 147
GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 148
GCR_PERF_SEL_PIO_GL1_ALL_REQ = 149
GCR_PERF_SEL_PIO_METADATA_REQ = 150
GCR_PERF_SEL_PIO_SQC_DATA_REQ = 151
GCR_PERF_SEL_PIO_SQC_INST_REQ = 152
GCR_PERF_SEL_PIO_TCP_REQ = 153
GCR_PERF_SEL_PIO_GL1_TLB_SHOOTDOWN_REQ = 154
GCRPerfSel = ctypes.c_uint32 # enum
# values for enumeration 'GC_EA_CPWD_PERFCOUNT_SEL'
GC_EA_CPWD_PERFCOUNT_SEL__enumvalues = {
0: 'GC_EA_CPWD_PERF_SEL_ALWAYS_COUNT',
1: 'GC_EA_CPWD_PERF_SEL_RDRAM_NUM_BANKS_VLD',
2: 'GC_EA_CPWD_PERF_SEL_RDRAM_REQ_PER_CLIGRP',
3: 'GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP',
4: 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START0',
5: 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END0',
6: 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START1',
7: 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END1',
8: 'GC_EA_CPWD_PERF_SEL_WDRAM_NUM_BANKS_VLD',
9: 'GC_EA_CPWD_PERF_SEL_WDRAM_REQ_PER_CLIGRP',
10: 'GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP',
11: 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START0',
12: 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END0',
13: 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START1',
14: 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END1',
15: 'GC_EA_CPWD_PERF_SEL_RGMI_NUM_BANKS_VLD',
16: 'GC_EA_CPWD_PERF_SEL_RGMI_REQ_PER_CLIGRP',
17: 'GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR',
18: 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START0',
19: 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END0',
20: 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START1',
21: 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END1',
22: 'GC_EA_CPWD_PERF_SEL_WGMI_NUM_BANKS_VLD',
23: 'GC_EA_CPWD_PERF_SEL_WGMI_REQ_PER_CLIGRP',
24: 'GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP',
25: 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START0',
26: 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END0',
27: 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START1',
28: 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END1',
29: 'GC_EA_CPWD_PERF_SEL_RIO_REQ_PER_CLIGRP',
30: 'GC_EA_CPWD_PERF_SEL_RIO_SIZE_REQ',
31: 'GC_EA_CPWD_PERF_SEL_RIO_GRP0_SIZE_REQ',
32: 'GC_EA_CPWD_PERF_SEL_RIO_GRP1_SIZE_REQ',
33: 'GC_EA_CPWD_PERF_SEL_RIO_GRP2_SIZE_REQ',
34: 'GC_EA_CPWD_PERF_SEL_RIO_GRP3_SIZE_REQ',
35: 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START0',
36: 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END0',
37: 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START1',
38: 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END1',
39: 'GC_EA_CPWD_PERF_SEL_WIO_REQ_PER_CLIGRP',
40: 'GC_EA_CPWD_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP',
41: 'GC_EA_CPWD_PERF_SEL_WIO_SIZE_REQ',
42: 'GC_EA_CPWD_PERF_SEL_WIO_GRP0_SIZE_REQ',
43: 'GC_EA_CPWD_PERF_SEL_WIO_GRP1_SIZE_REQ',
44: 'GC_EA_CPWD_PERF_SEL_WIO_GRP2_SIZE_REQ',
45: 'GC_EA_CPWD_PERF_SEL_WIO_GRP3_SIZE_REQ',
46: 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START0',
47: 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END0',
48: 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START1',
49: 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END1',
50: 'GC_EA_CPWD_PERF_SEL_SARB_REQ_PER_VC',
51: 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_REQ_PER_VC',
52: 'GC_EA_CPWD_PERF_SEL_SARB_GMI_REQ_PER_VC',
53: 'GC_EA_CPWD_PERF_SEL_SARB_IO_REQ_PER_VC',
54: 'GC_EA_CPWD_PERF_SEL_SARB_SIZE_REQ',
55: 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_SIZE_REQ',
56: 'GC_EA_CPWD_PERF_SEL_SARB_GMI_SIZE_REQ',
57: 'GC_EA_CPWD_PERF_SEL_SARB_IO_SIZE_REQ',
58: 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START0',
59: 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END0',
60: 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START1',
61: 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END1',
62: 'GC_EA_CPWD_PERF_SEL_SARB_BUSY',
63: 'GC_EA_CPWD_PERF_SEL_SARB_STALLED',
64: 'GC_EA_CPWD_PERF_SEL_SARB_STARVING',
65: 'GC_EA_CPWD_PERF_SEL_SARB_IDLE',
66: 'GC_EA_CPWD_PERF_SEL_RRET_VLD',
67: 'GC_EA_CPWD_PERF_SEL_WRET_VLD',
68: 'GC_EA_CPWD_PERF_SEL_PRB_REQ',
69: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_EVICT',
70: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_REQ_VLD',
71: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT',
72: 'GC_EA_CPWD_PERF_SEL_MAM_NUM_DQRY',
73: 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT',
74: 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED',
75: 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_COMPLETED',
76: 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_ONGOING',
77: 'GC_EA_CPWD_PERF_SEL_RDRAM_SIZE_REQ',
78: 'GC_EA_CPWD_PERF_SEL_WDRAM_SIZE_REQ',
79: 'GC_EA_CPWD_PERF_SEL_RGMI_SIZE_REQ',
80: 'GC_EA_CPWD_PERF_SEL_WGMI_SIZE_REQ',
81: 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_RW_TURN_AROUND',
82: 'GC_EA_CPWD_PERF_SEL_SARB_GMI_RW_TURN_AROUND',
83: 'GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH',
84: 'GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH',
85: 'GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH',
86: 'GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH',
87: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_EVICT',
88: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_REQ_VLD',
89: 'GC_EA_CPWD_PERF_SEL_SARB_COHERENT_SIZE_REQ',
90: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT_EVICT',
91: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_LRU_EVICT',
92: 'GC_EA_CPWD_PERF_SEL_MAM_FLUSH_REQ',
93: 'GC_EA_CPWD_PERF_SEL_MAM_FLUSH_RESP',
94: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT_EVICT',
95: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_LRU_EVICT',
96: 'GC_EA_CPWD_PERF_SEL_MAM_DQRY_ONGOING',
97: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT',
}
GC_EA_CPWD_PERF_SEL_ALWAYS_COUNT = 0
GC_EA_CPWD_PERF_SEL_RDRAM_NUM_BANKS_VLD = 1
GC_EA_CPWD_PERF_SEL_RDRAM_REQ_PER_CLIGRP = 2
GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP = 3
GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START0 = 4
GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END0 = 5
GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START1 = 6
GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END1 = 7
GC_EA_CPWD_PERF_SEL_WDRAM_NUM_BANKS_VLD = 8
GC_EA_CPWD_PERF_SEL_WDRAM_REQ_PER_CLIGRP = 9
GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP = 10
GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START0 = 11
GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END0 = 12
GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START1 = 13
GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END1 = 14
GC_EA_CPWD_PERF_SEL_RGMI_NUM_BANKS_VLD = 15
GC_EA_CPWD_PERF_SEL_RGMI_REQ_PER_CLIGRP = 16
GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR = 17
GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START0 = 18
GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END0 = 19
GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START1 = 20
GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END1 = 21
GC_EA_CPWD_PERF_SEL_WGMI_NUM_BANKS_VLD = 22
GC_EA_CPWD_PERF_SEL_WGMI_REQ_PER_CLIGRP = 23
GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP = 24
GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START0 = 25
GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END0 = 26
GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START1 = 27
GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END1 = 28
GC_EA_CPWD_PERF_SEL_RIO_REQ_PER_CLIGRP = 29
GC_EA_CPWD_PERF_SEL_RIO_SIZE_REQ = 30
GC_EA_CPWD_PERF_SEL_RIO_GRP0_SIZE_REQ = 31
GC_EA_CPWD_PERF_SEL_RIO_GRP1_SIZE_REQ = 32
GC_EA_CPWD_PERF_SEL_RIO_GRP2_SIZE_REQ = 33
GC_EA_CPWD_PERF_SEL_RIO_GRP3_SIZE_REQ = 34
GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START0 = 35
GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END0 = 36
GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START1 = 37
GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END1 = 38
GC_EA_CPWD_PERF_SEL_WIO_REQ_PER_CLIGRP = 39
GC_EA_CPWD_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP = 40
GC_EA_CPWD_PERF_SEL_WIO_SIZE_REQ = 41
GC_EA_CPWD_PERF_SEL_WIO_GRP0_SIZE_REQ = 42
GC_EA_CPWD_PERF_SEL_WIO_GRP1_SIZE_REQ = 43
GC_EA_CPWD_PERF_SEL_WIO_GRP2_SIZE_REQ = 44
GC_EA_CPWD_PERF_SEL_WIO_GRP3_SIZE_REQ = 45
GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START0 = 46
GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END0 = 47
GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START1 = 48
GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END1 = 49
GC_EA_CPWD_PERF_SEL_SARB_REQ_PER_VC = 50
GC_EA_CPWD_PERF_SEL_SARB_DRAM_REQ_PER_VC = 51
GC_EA_CPWD_PERF_SEL_SARB_GMI_REQ_PER_VC = 52
GC_EA_CPWD_PERF_SEL_SARB_IO_REQ_PER_VC = 53
GC_EA_CPWD_PERF_SEL_SARB_SIZE_REQ = 54
GC_EA_CPWD_PERF_SEL_SARB_DRAM_SIZE_REQ = 55
GC_EA_CPWD_PERF_SEL_SARB_GMI_SIZE_REQ = 56
GC_EA_CPWD_PERF_SEL_SARB_IO_SIZE_REQ = 57
GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START0 = 58
GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END0 = 59
GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START1 = 60
GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END1 = 61
GC_EA_CPWD_PERF_SEL_SARB_BUSY = 62
GC_EA_CPWD_PERF_SEL_SARB_STALLED = 63
GC_EA_CPWD_PERF_SEL_SARB_STARVING = 64
GC_EA_CPWD_PERF_SEL_SARB_IDLE = 65
GC_EA_CPWD_PERF_SEL_RRET_VLD = 66
GC_EA_CPWD_PERF_SEL_WRET_VLD = 67
GC_EA_CPWD_PERF_SEL_PRB_REQ = 68
GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_EVICT = 69
GC_EA_CPWD_PERF_SEL_MAM_ARAM_REQ_VLD = 70
GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT = 71
GC_EA_CPWD_PERF_SEL_MAM_NUM_DQRY = 72
GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT = 73
GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED = 74
GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_COMPLETED = 75
GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_ONGOING = 76
GC_EA_CPWD_PERF_SEL_RDRAM_SIZE_REQ = 77
GC_EA_CPWD_PERF_SEL_WDRAM_SIZE_REQ = 78
GC_EA_CPWD_PERF_SEL_RGMI_SIZE_REQ = 79
GC_EA_CPWD_PERF_SEL_WGMI_SIZE_REQ = 80
GC_EA_CPWD_PERF_SEL_SARB_DRAM_RW_TURN_AROUND = 81
GC_EA_CPWD_PERF_SEL_SARB_GMI_RW_TURN_AROUND = 82
GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 83
GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 84
GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 85
GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 86
GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_EVICT = 87
GC_EA_CPWD_PERF_SEL_MAM_DBIT_REQ_VLD = 88
GC_EA_CPWD_PERF_SEL_SARB_COHERENT_SIZE_REQ = 89
GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT_EVICT = 90
GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_LRU_EVICT = 91
GC_EA_CPWD_PERF_SEL_MAM_FLUSH_REQ = 92
GC_EA_CPWD_PERF_SEL_MAM_FLUSH_RESP = 93
GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT_EVICT = 94
GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_LRU_EVICT = 95
GC_EA_CPWD_PERF_SEL_MAM_DQRY_ONGOING = 96
GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT = 97
GC_EA_CPWD_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GCVML2_SPM_PERF_SEL'
GCVML2_SPM_PERF_SEL__enumvalues = {
0: 'GCVML2_SPM_PERF_SEL_EVENT_0',
1: 'GCVML2_SPM_PERF_SEL_EVENT_1',
2: 'GCVML2_SPM_PERF_SEL_EVENT_2',
3: 'GCVML2_SPM_PERF_SEL_EVENT_3',
4: 'GCVML2_SPM_PERF_SEL_EVENT_4',
5: 'GCVML2_SPM_PERF_SEL_EVENT_5',
6: 'GCVML2_SPM_PERF_SEL_EVENT_6',
7: 'GCVML2_SPM_PERF_SEL_EVENT_7',
8: 'GCVML2_SPM_PERF_SEL_EVENT_8',
9: 'GCVML2_SPM_PERF_SEL_EVENT_9',
10: 'GCVML2_SPM_PERF_SEL_EVENT_10',
11: 'GCVML2_SPM_PERF_SEL_EVENT_11',
12: 'GCVML2_SPM_PERF_SEL_EVENT_12',
13: 'GCVML2_SPM_PERF_SEL_EVENT_13',
14: 'GCVML2_SPM_PERF_SEL_EVENT_14',
15: 'GCVML2_SPM_PERF_SEL_EVENT_15',
16: 'GCVML2_SPM_PERF_SEL_EVENT_16',
17: 'GCVML2_SPM_PERF_SEL_EVENT_17',
18: 'GCVML2_SPM_PERF_SEL_EVENT_18',
19: 'GCVML2_SPM_PERF_SEL_EVENT_19',
20: 'GCVML2_SPM_PERF_SEL_EVENT_20',
21: 'GCVML2_SPM_PERF_SEL_EVENT_21',
22: 'GCVML2_SPM_PERF_SEL_EVENT_22',
23: 'GCVML2_SPM_PERF_SEL_EVENT_23',
24: 'GCVML2_SPM_PERF_SEL_EVENT_24',
25: 'GCVML2_SPM_PERF_SEL_EVENT_25',
26: 'GCVML2_SPM_PERF_SEL_EVENT_26',
27: 'GCVML2_SPM_PERF_SEL_EVENT_27',
28: 'GCVML2_SPM_PERF_SEL_EVENT_28',
29: 'GCVML2_SPM_PERF_SEL_EVENT_29',
30: 'GCVML2_SPM_PERF_SEL_EVENT_30',
31: 'GCVML2_SPM_PERF_SEL_EVENT_31',
32: 'GCVML2_SPM_PERF_SEL_EVENT_32',
33: 'GCVML2_SPM_PERF_SEL_EVENT_33',
34: 'GCVML2_SPM_PERF_SEL_EVENT_34',
35: 'GCVML2_SPM_PERF_SEL_EVENT_35',
36: 'GCVML2_SPM_PERF_SEL_EVENT_36',
37: 'GCVML2_SPM_PERF_SEL_EVENT_37',
38: 'GCVML2_SPM_PERF_SEL_EVENT_38',
39: 'GCVML2_SPM_PERF_SEL_EVENT_39',
40: 'GCVML2_SPM_PERF_SEL_EVENT_40',
41: 'GCVML2_SPM_PERF_SEL_EVENT_41',
42: 'GCVML2_SPM_PERF_SEL_EVENT_42',
43: 'GCVML2_SPM_PERF_SEL_EVENT_43',
44: 'GCVML2_SPM_PERF_SEL_EVENT_44',
45: 'GCVML2_SPM_PERF_SEL_EVENT_45',
46: 'GCVML2_SPM_PERF_SEL_EVENT_46',
47: 'GCVML2_SPM_PERF_SEL_EVENT_47',
48: 'GCVML2_SPM_PERF_SEL_EVENT_48',
49: 'GCVML2_SPM_PERF_SEL_EVENT_49',
50: 'GCVML2_SPM_PERF_SEL_EVENT_50',
51: 'GCVML2_SPM_PERF_SEL_EVENT_51',
52: 'GCVML2_SPM_PERF_SEL_EVENT_52',
53: 'GCVML2_SPM_PERF_SEL_EVENT_53',
54: 'GCVML2_SPM_PERF_SEL_EVENT_54',
55: 'GCVML2_SPM_PERF_SEL_EVENT_55',
56: 'GCVML2_SPM_PERF_SEL_EVENT_56',
57: 'GCVML2_SPM_PERF_SEL_EVENT_57',
58: 'GCVML2_SPM_PERF_SEL_EVENT_58',
59: 'GCVML2_SPM_PERF_SEL_EVENT_59',
60: 'GCVML2_SPM_PERF_SEL_EVENT_60',
61: 'GCVML2_SPM_PERF_SEL_EVENT_61',
62: 'GCVML2_SPM_PERF_SEL_EVENT_62',
63: 'GCVML2_SPM_PERF_SEL_EVENT_63',
64: 'GCVML2_SPM_PERF_SEL_EVENT_64',
65: 'GCVML2_SPM_PERF_SEL_EVENT_65',
66: 'GCVML2_SPM_PERF_SEL_EVENT_66',
67: 'GCVML2_SPM_PERF_SEL_EVENT_67',
68: 'GCVML2_SPM_PERF_SEL_EVENT_68',
69: 'GCVML2_SPM_PERF_SEL_EVENT_69',
70: 'GCVML2_SPM_PERF_SEL_EVENT_70',
71: 'GCVML2_SPM_PERF_SEL_EVENT_71',
72: 'GCVML2_SPM_PERF_SEL_EVENT_72',
73: 'GCVML2_SPM_PERF_SEL_EVENT_73',
74: 'GCVML2_SPM_PERF_SEL_EVENT_74',
75: 'GCVML2_SPM_PERF_SEL_EVENT_75',
76: 'GCVML2_SPM_PERF_SEL_EVENT_76',
77: 'GCVML2_SPM_PERF_SEL_EVENT_77',
78: 'GCVML2_SPM_PERF_SEL_EVENT_78',
79: 'GCVML2_SPM_PERF_SEL_EVENT_79',
80: 'GCVML2_SPM_PERF_SEL_EVENT_80',
81: 'GCVML2_SPM_PERF_SEL_EVENT_81',
82: 'GCVML2_SPM_PERF_SEL_EVENT_82',
83: 'GCVML2_SPM_PERF_SEL_EVENT_83',
84: 'GCVML2_SPM_PERF_SEL_EVENT_84',
85: 'GCVML2_SPM_PERF_SEL_EVENT_85',
86: 'GCVML2_SPM_PERF_SEL_EVENT_86',
87: 'GCVML2_SPM_PERF_SEL_EVENT_87',
88: 'GCVML2_SPM_PERF_SEL_EVENT_88',
89: 'GCVML2_SPM_PERF_SEL_EVENT_89',
90: 'GCVML2_SPM_PERF_SEL_EVENT_90',
}
GCVML2_SPM_PERF_SEL_EVENT_0 = 0
GCVML2_SPM_PERF_SEL_EVENT_1 = 1
GCVML2_SPM_PERF_SEL_EVENT_2 = 2
GCVML2_SPM_PERF_SEL_EVENT_3 = 3
GCVML2_SPM_PERF_SEL_EVENT_4 = 4
GCVML2_SPM_PERF_SEL_EVENT_5 = 5
GCVML2_SPM_PERF_SEL_EVENT_6 = 6
GCVML2_SPM_PERF_SEL_EVENT_7 = 7
GCVML2_SPM_PERF_SEL_EVENT_8 = 8
GCVML2_SPM_PERF_SEL_EVENT_9 = 9
GCVML2_SPM_PERF_SEL_EVENT_10 = 10
GCVML2_SPM_PERF_SEL_EVENT_11 = 11
GCVML2_SPM_PERF_SEL_EVENT_12 = 12
GCVML2_SPM_PERF_SEL_EVENT_13 = 13
GCVML2_SPM_PERF_SEL_EVENT_14 = 14
GCVML2_SPM_PERF_SEL_EVENT_15 = 15
GCVML2_SPM_PERF_SEL_EVENT_16 = 16
GCVML2_SPM_PERF_SEL_EVENT_17 = 17
GCVML2_SPM_PERF_SEL_EVENT_18 = 18
GCVML2_SPM_PERF_SEL_EVENT_19 = 19
GCVML2_SPM_PERF_SEL_EVENT_20 = 20
GCVML2_SPM_PERF_SEL_EVENT_21 = 21
GCVML2_SPM_PERF_SEL_EVENT_22 = 22
GCVML2_SPM_PERF_SEL_EVENT_23 = 23
GCVML2_SPM_PERF_SEL_EVENT_24 = 24
GCVML2_SPM_PERF_SEL_EVENT_25 = 25
GCVML2_SPM_PERF_SEL_EVENT_26 = 26
GCVML2_SPM_PERF_SEL_EVENT_27 = 27
GCVML2_SPM_PERF_SEL_EVENT_28 = 28
GCVML2_SPM_PERF_SEL_EVENT_29 = 29
GCVML2_SPM_PERF_SEL_EVENT_30 = 30
GCVML2_SPM_PERF_SEL_EVENT_31 = 31
GCVML2_SPM_PERF_SEL_EVENT_32 = 32
GCVML2_SPM_PERF_SEL_EVENT_33 = 33
GCVML2_SPM_PERF_SEL_EVENT_34 = 34
GCVML2_SPM_PERF_SEL_EVENT_35 = 35
GCVML2_SPM_PERF_SEL_EVENT_36 = 36
GCVML2_SPM_PERF_SEL_EVENT_37 = 37
GCVML2_SPM_PERF_SEL_EVENT_38 = 38
GCVML2_SPM_PERF_SEL_EVENT_39 = 39
GCVML2_SPM_PERF_SEL_EVENT_40 = 40
GCVML2_SPM_PERF_SEL_EVENT_41 = 41
GCVML2_SPM_PERF_SEL_EVENT_42 = 42
GCVML2_SPM_PERF_SEL_EVENT_43 = 43
GCVML2_SPM_PERF_SEL_EVENT_44 = 44
GCVML2_SPM_PERF_SEL_EVENT_45 = 45
GCVML2_SPM_PERF_SEL_EVENT_46 = 46
GCVML2_SPM_PERF_SEL_EVENT_47 = 47
GCVML2_SPM_PERF_SEL_EVENT_48 = 48
GCVML2_SPM_PERF_SEL_EVENT_49 = 49
GCVML2_SPM_PERF_SEL_EVENT_50 = 50
GCVML2_SPM_PERF_SEL_EVENT_51 = 51
GCVML2_SPM_PERF_SEL_EVENT_52 = 52
GCVML2_SPM_PERF_SEL_EVENT_53 = 53
GCVML2_SPM_PERF_SEL_EVENT_54 = 54
GCVML2_SPM_PERF_SEL_EVENT_55 = 55
GCVML2_SPM_PERF_SEL_EVENT_56 = 56
GCVML2_SPM_PERF_SEL_EVENT_57 = 57
GCVML2_SPM_PERF_SEL_EVENT_58 = 58
GCVML2_SPM_PERF_SEL_EVENT_59 = 59
GCVML2_SPM_PERF_SEL_EVENT_60 = 60
GCVML2_SPM_PERF_SEL_EVENT_61 = 61
GCVML2_SPM_PERF_SEL_EVENT_62 = 62
GCVML2_SPM_PERF_SEL_EVENT_63 = 63
GCVML2_SPM_PERF_SEL_EVENT_64 = 64
GCVML2_SPM_PERF_SEL_EVENT_65 = 65
GCVML2_SPM_PERF_SEL_EVENT_66 = 66
GCVML2_SPM_PERF_SEL_EVENT_67 = 67
GCVML2_SPM_PERF_SEL_EVENT_68 = 68
GCVML2_SPM_PERF_SEL_EVENT_69 = 69
GCVML2_SPM_PERF_SEL_EVENT_70 = 70
GCVML2_SPM_PERF_SEL_EVENT_71 = 71
GCVML2_SPM_PERF_SEL_EVENT_72 = 72
GCVML2_SPM_PERF_SEL_EVENT_73 = 73
GCVML2_SPM_PERF_SEL_EVENT_74 = 74
GCVML2_SPM_PERF_SEL_EVENT_75 = 75
GCVML2_SPM_PERF_SEL_EVENT_76 = 76
GCVML2_SPM_PERF_SEL_EVENT_77 = 77
GCVML2_SPM_PERF_SEL_EVENT_78 = 78
GCVML2_SPM_PERF_SEL_EVENT_79 = 79
GCVML2_SPM_PERF_SEL_EVENT_80 = 80
GCVML2_SPM_PERF_SEL_EVENT_81 = 81
GCVML2_SPM_PERF_SEL_EVENT_82 = 82
GCVML2_SPM_PERF_SEL_EVENT_83 = 83
GCVML2_SPM_PERF_SEL_EVENT_84 = 84
GCVML2_SPM_PERF_SEL_EVENT_85 = 85
GCVML2_SPM_PERF_SEL_EVENT_86 = 86
GCVML2_SPM_PERF_SEL_EVENT_87 = 87
GCVML2_SPM_PERF_SEL_EVENT_88 = 88
GCVML2_SPM_PERF_SEL_EVENT_89 = 89
GCVML2_SPM_PERF_SEL_EVENT_90 = 90
GCVML2_SPM_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GCUTCL2_PERF_SEL'
GCUTCL2_PERF_SEL__enumvalues = {
0: 'GCUTCL2_PERF_SEL_EVENT_0',
1: 'GCUTCL2_PERF_SEL_EVENT_1',
2: 'GCUTCL2_PERF_SEL_EVENT_2',
3: 'GCUTCL2_PERF_SEL_EVENT_3',
4: 'GCUTCL2_PERF_SEL_EVENT_4',
5: 'GCUTCL2_PERF_SEL_EVENT_5',
6: 'GCUTCL2_PERF_SEL_EVENT_6',
7: 'GCUTCL2_PERF_SEL_EVENT_7',
8: 'GCUTCL2_PERF_SEL_EVENT_8',
9: 'GCUTCL2_PERF_SEL_EVENT_9',
10: 'GCUTCL2_PERF_SEL_EVENT_10',
11: 'GCUTCL2_PERF_SEL_EVENT_11',
12: 'GCUTCL2_PERF_SEL_EVENT_12',
13: 'GCUTCL2_PERF_SEL_EVENT_13',
14: 'GCUTCL2_PERF_SEL_EVENT_14',
15: 'GCUTCL2_PERF_SEL_EVENT_15',
16: 'GCUTCL2_PERF_SEL_EVENT_16',
17: 'GCUTCL2_PERF_SEL_EVENT_17',
18: 'GCUTCL2_PERF_SEL_EVENT_18',
19: 'GCUTCL2_PERF_SEL_EVENT_19',
20: 'GCUTCL2_PERF_SEL_EVENT_20',
21: 'GCUTCL2_PERF_SEL_EVENT_21',
22: 'GCUTCL2_PERF_SEL_EVENT_22',
23: 'GCUTCL2_PERF_SEL_EVENT_23',
24: 'GCUTCL2_PERF_SEL_EVENT_24',
25: 'GCUTCL2_PERF_SEL_EVENT_25',
26: 'GCUTCL2_PERF_SEL_EVENT_26',
27: 'GCUTCL2_PERF_SEL_EVENT_27',
28: 'GCUTCL2_PERF_SEL_EVENT_28',
29: 'GCUTCL2_PERF_SEL_EVENT_29',
30: 'GCUTCL2_PERF_SEL_EVENT_30',
31: 'GCUTCL2_PERF_SEL_EVENT_31',
32: 'GCUTCL2_PERF_SEL_EVENT_32',
33: 'GCUTCL2_PERF_SEL_EVENT_33',
34: 'GCUTCL2_PERF_SEL_EVENT_34',
35: 'GCUTCL2_PERF_SEL_EVENT_35',
36: 'GCUTCL2_PERF_SEL_EVENT_36',
}
GCUTCL2_PERF_SEL_EVENT_0 = 0
GCUTCL2_PERF_SEL_EVENT_1 = 1
GCUTCL2_PERF_SEL_EVENT_2 = 2
GCUTCL2_PERF_SEL_EVENT_3 = 3
GCUTCL2_PERF_SEL_EVENT_4 = 4
GCUTCL2_PERF_SEL_EVENT_5 = 5
GCUTCL2_PERF_SEL_EVENT_6 = 6
GCUTCL2_PERF_SEL_EVENT_7 = 7
GCUTCL2_PERF_SEL_EVENT_8 = 8
GCUTCL2_PERF_SEL_EVENT_9 = 9
GCUTCL2_PERF_SEL_EVENT_10 = 10
GCUTCL2_PERF_SEL_EVENT_11 = 11
GCUTCL2_PERF_SEL_EVENT_12 = 12
GCUTCL2_PERF_SEL_EVENT_13 = 13
GCUTCL2_PERF_SEL_EVENT_14 = 14
GCUTCL2_PERF_SEL_EVENT_15 = 15
GCUTCL2_PERF_SEL_EVENT_16 = 16
GCUTCL2_PERF_SEL_EVENT_17 = 17
GCUTCL2_PERF_SEL_EVENT_18 = 18
GCUTCL2_PERF_SEL_EVENT_19 = 19
GCUTCL2_PERF_SEL_EVENT_20 = 20
GCUTCL2_PERF_SEL_EVENT_21 = 21
GCUTCL2_PERF_SEL_EVENT_22 = 22
GCUTCL2_PERF_SEL_EVENT_23 = 23
GCUTCL2_PERF_SEL_EVENT_24 = 24
GCUTCL2_PERF_SEL_EVENT_25 = 25
GCUTCL2_PERF_SEL_EVENT_26 = 26
GCUTCL2_PERF_SEL_EVENT_27 = 27
GCUTCL2_PERF_SEL_EVENT_28 = 28
GCUTCL2_PERF_SEL_EVENT_29 = 29
GCUTCL2_PERF_SEL_EVENT_30 = 30
GCUTCL2_PERF_SEL_EVENT_31 = 31
GCUTCL2_PERF_SEL_EVENT_32 = 32
GCUTCL2_PERF_SEL_EVENT_33 = 33
GCUTCL2_PERF_SEL_EVENT_34 = 34
GCUTCL2_PERF_SEL_EVENT_35 = 35
GCUTCL2_PERF_SEL_EVENT_36 = 36
GCUTCL2_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GCVML2_PERF_SEL'
GCVML2_PERF_SEL__enumvalues = {
0: 'GCVML2_PERF_SEL_EVENT_0',
1: 'GCVML2_PERF_SEL_EVENT_1',
2: 'GCVML2_PERF_SEL_EVENT_2',
3: 'GCVML2_PERF_SEL_EVENT_3',
4: 'GCVML2_PERF_SEL_EVENT_4',
5: 'GCVML2_PERF_SEL_EVENT_5',
6: 'GCVML2_PERF_SEL_EVENT_6',
7: 'GCVML2_PERF_SEL_EVENT_7',
8: 'GCVML2_PERF_SEL_EVENT_8',
9: 'GCVML2_PERF_SEL_EVENT_9',
10: 'GCVML2_PERF_SEL_EVENT_10',
11: 'GCVML2_PERF_SEL_EVENT_11',
12: 'GCVML2_PERF_SEL_EVENT_12',
13: 'GCVML2_PERF_SEL_EVENT_13',
14: 'GCVML2_PERF_SEL_EVENT_14',
15: 'GCVML2_PERF_SEL_EVENT_15',
16: 'GCVML2_PERF_SEL_EVENT_16',
17: 'GCVML2_PERF_SEL_EVENT_17',
18: 'GCVML2_PERF_SEL_EVENT_18',
19: 'GCVML2_PERF_SEL_EVENT_19',
20: 'GCVML2_PERF_SEL_EVENT_20',
21: 'GCVML2_PERF_SEL_EVENT_21',
22: 'GCVML2_PERF_SEL_EVENT_22',
23: 'GCVML2_PERF_SEL_EVENT_23',
24: 'GCVML2_PERF_SEL_EVENT_24',
25: 'GCVML2_PERF_SEL_EVENT_25',
26: 'GCVML2_PERF_SEL_EVENT_26',
27: 'GCVML2_PERF_SEL_EVENT_27',
28: 'GCVML2_PERF_SEL_EVENT_28',
29: 'GCVML2_PERF_SEL_EVENT_29',
30: 'GCVML2_PERF_SEL_EVENT_30',
31: 'GCVML2_PERF_SEL_EVENT_31',
32: 'GCVML2_PERF_SEL_EVENT_32',
33: 'GCVML2_PERF_SEL_EVENT_33',
34: 'GCVML2_PERF_SEL_EVENT_34',
35: 'GCVML2_PERF_SEL_EVENT_35',
36: 'GCVML2_PERF_SEL_EVENT_36',
37: 'GCVML2_PERF_SEL_EVENT_37',
38: 'GCVML2_PERF_SEL_EVENT_38',
39: 'GCVML2_PERF_SEL_EVENT_39',
40: 'GCVML2_PERF_SEL_EVENT_40',
41: 'GCVML2_PERF_SEL_EVENT_41',
42: 'GCVML2_PERF_SEL_EVENT_42',
43: 'GCVML2_PERF_SEL_EVENT_43',
44: 'GCVML2_PERF_SEL_EVENT_44',
45: 'GCVML2_PERF_SEL_EVENT_45',
46: 'GCVML2_PERF_SEL_EVENT_46',
47: 'GCVML2_PERF_SEL_EVENT_47',
48: 'GCVML2_PERF_SEL_EVENT_48',
49: 'GCVML2_PERF_SEL_EVENT_49',
50: 'GCVML2_PERF_SEL_EVENT_50',
51: 'GCVML2_PERF_SEL_EVENT_51',
52: 'GCVML2_PERF_SEL_EVENT_52',
53: 'GCVML2_PERF_SEL_EVENT_53',
54: 'GCVML2_PERF_SEL_EVENT_54',
55: 'GCVML2_PERF_SEL_EVENT_55',
56: 'GCVML2_PERF_SEL_EVENT_56',
57: 'GCVML2_PERF_SEL_EVENT_57',
58: 'GCVML2_PERF_SEL_EVENT_58',
59: 'GCVML2_PERF_SEL_EVENT_59',
60: 'GCVML2_PERF_SEL_EVENT_60',
61: 'GCVML2_PERF_SEL_EVENT_61',
62: 'GCVML2_PERF_SEL_EVENT_62',
63: 'GCVML2_PERF_SEL_EVENT_63',
64: 'GCVML2_PERF_SEL_EVENT_64',
65: 'GCVML2_PERF_SEL_EVENT_65',
66: 'GCVML2_PERF_SEL_EVENT_66',
67: 'GCVML2_PERF_SEL_EVENT_67',
68: 'GCVML2_PERF_SEL_EVENT_68',
69: 'GCVML2_PERF_SEL_EVENT_69',
70: 'GCVML2_PERF_SEL_EVENT_70',
71: 'GCVML2_PERF_SEL_EVENT_71',
72: 'GCVML2_PERF_SEL_EVENT_72',
73: 'GCVML2_PERF_SEL_EVENT_73',
74: 'GCVML2_PERF_SEL_EVENT_74',
75: 'GCVML2_PERF_SEL_EVENT_75',
76: 'GCVML2_PERF_SEL_EVENT_76',
77: 'GCVML2_PERF_SEL_EVENT_77',
78: 'GCVML2_PERF_SEL_EVENT_78',
79: 'GCVML2_PERF_SEL_EVENT_79',
80: 'GCVML2_PERF_SEL_EVENT_80',
81: 'GCVML2_PERF_SEL_EVENT_81',
82: 'GCVML2_PERF_SEL_EVENT_82',
83: 'GCVML2_PERF_SEL_EVENT_83',
84: 'GCVML2_PERF_SEL_EVENT_84',
85: 'GCVML2_PERF_SEL_EVENT_85',
86: 'GCVML2_PERF_SEL_EVENT_86',
87: 'GCVML2_PERF_SEL_EVENT_87',
88: 'GCVML2_PERF_SEL_EVENT_88',
89: 'GCVML2_PERF_SEL_EVENT_89',
90: 'GCVML2_PERF_SEL_EVENT_90',
}
GCVML2_PERF_SEL_EVENT_0 = 0
GCVML2_PERF_SEL_EVENT_1 = 1
GCVML2_PERF_SEL_EVENT_2 = 2
GCVML2_PERF_SEL_EVENT_3 = 3
GCVML2_PERF_SEL_EVENT_4 = 4
GCVML2_PERF_SEL_EVENT_5 = 5
GCVML2_PERF_SEL_EVENT_6 = 6
GCVML2_PERF_SEL_EVENT_7 = 7
GCVML2_PERF_SEL_EVENT_8 = 8
GCVML2_PERF_SEL_EVENT_9 = 9
GCVML2_PERF_SEL_EVENT_10 = 10
GCVML2_PERF_SEL_EVENT_11 = 11
GCVML2_PERF_SEL_EVENT_12 = 12
GCVML2_PERF_SEL_EVENT_13 = 13
GCVML2_PERF_SEL_EVENT_14 = 14
GCVML2_PERF_SEL_EVENT_15 = 15
GCVML2_PERF_SEL_EVENT_16 = 16
GCVML2_PERF_SEL_EVENT_17 = 17
GCVML2_PERF_SEL_EVENT_18 = 18
GCVML2_PERF_SEL_EVENT_19 = 19
GCVML2_PERF_SEL_EVENT_20 = 20
GCVML2_PERF_SEL_EVENT_21 = 21
GCVML2_PERF_SEL_EVENT_22 = 22
GCVML2_PERF_SEL_EVENT_23 = 23
GCVML2_PERF_SEL_EVENT_24 = 24
GCVML2_PERF_SEL_EVENT_25 = 25
GCVML2_PERF_SEL_EVENT_26 = 26
GCVML2_PERF_SEL_EVENT_27 = 27
GCVML2_PERF_SEL_EVENT_28 = 28
GCVML2_PERF_SEL_EVENT_29 = 29
GCVML2_PERF_SEL_EVENT_30 = 30
GCVML2_PERF_SEL_EVENT_31 = 31
GCVML2_PERF_SEL_EVENT_32 = 32
GCVML2_PERF_SEL_EVENT_33 = 33
GCVML2_PERF_SEL_EVENT_34 = 34
GCVML2_PERF_SEL_EVENT_35 = 35
GCVML2_PERF_SEL_EVENT_36 = 36
GCVML2_PERF_SEL_EVENT_37 = 37
GCVML2_PERF_SEL_EVENT_38 = 38
GCVML2_PERF_SEL_EVENT_39 = 39
GCVML2_PERF_SEL_EVENT_40 = 40
GCVML2_PERF_SEL_EVENT_41 = 41
GCVML2_PERF_SEL_EVENT_42 = 42
GCVML2_PERF_SEL_EVENT_43 = 43
GCVML2_PERF_SEL_EVENT_44 = 44
GCVML2_PERF_SEL_EVENT_45 = 45
GCVML2_PERF_SEL_EVENT_46 = 46
GCVML2_PERF_SEL_EVENT_47 = 47
GCVML2_PERF_SEL_EVENT_48 = 48
GCVML2_PERF_SEL_EVENT_49 = 49
GCVML2_PERF_SEL_EVENT_50 = 50
GCVML2_PERF_SEL_EVENT_51 = 51
GCVML2_PERF_SEL_EVENT_52 = 52
GCVML2_PERF_SEL_EVENT_53 = 53
GCVML2_PERF_SEL_EVENT_54 = 54
GCVML2_PERF_SEL_EVENT_55 = 55
GCVML2_PERF_SEL_EVENT_56 = 56
GCVML2_PERF_SEL_EVENT_57 = 57
GCVML2_PERF_SEL_EVENT_58 = 58
GCVML2_PERF_SEL_EVENT_59 = 59
GCVML2_PERF_SEL_EVENT_60 = 60
GCVML2_PERF_SEL_EVENT_61 = 61
GCVML2_PERF_SEL_EVENT_62 = 62
GCVML2_PERF_SEL_EVENT_63 = 63
GCVML2_PERF_SEL_EVENT_64 = 64
GCVML2_PERF_SEL_EVENT_65 = 65
GCVML2_PERF_SEL_EVENT_66 = 66
GCVML2_PERF_SEL_EVENT_67 = 67
GCVML2_PERF_SEL_EVENT_68 = 68
GCVML2_PERF_SEL_EVENT_69 = 69
GCVML2_PERF_SEL_EVENT_70 = 70
GCVML2_PERF_SEL_EVENT_71 = 71
GCVML2_PERF_SEL_EVENT_72 = 72
GCVML2_PERF_SEL_EVENT_73 = 73
GCVML2_PERF_SEL_EVENT_74 = 74
GCVML2_PERF_SEL_EVENT_75 = 75
GCVML2_PERF_SEL_EVENT_76 = 76
GCVML2_PERF_SEL_EVENT_77 = 77
GCVML2_PERF_SEL_EVENT_78 = 78
GCVML2_PERF_SEL_EVENT_79 = 79
GCVML2_PERF_SEL_EVENT_80 = 80
GCVML2_PERF_SEL_EVENT_81 = 81
GCVML2_PERF_SEL_EVENT_82 = 82
GCVML2_PERF_SEL_EVENT_83 = 83
GCVML2_PERF_SEL_EVENT_84 = 84
GCVML2_PERF_SEL_EVENT_85 = 85
GCVML2_PERF_SEL_EVENT_86 = 86
GCVML2_PERF_SEL_EVENT_87 = 87
GCVML2_PERF_SEL_EVENT_88 = 88
GCVML2_PERF_SEL_EVENT_89 = 89
GCVML2_PERF_SEL_EVENT_90 = 90
GCVML2_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'BlendOp'
BlendOp__enumvalues = {
0: 'BLEND_ZERO',
1: 'BLEND_ONE',
2: 'BLEND_SRC_COLOR',
3: 'BLEND_ONE_MINUS_SRC_COLOR',
4: 'BLEND_SRC_ALPHA',
5: 'BLEND_ONE_MINUS_SRC_ALPHA',
6: 'BLEND_DST_ALPHA',
7: 'BLEND_ONE_MINUS_DST_ALPHA',
8: 'BLEND_DST_COLOR',
9: 'BLEND_ONE_MINUS_DST_COLOR',
10: 'BLEND_SRC_ALPHA_SATURATE',
11: 'BLEND_CONSTANT_COLOR',
12: 'BLEND_ONE_MINUS_CONSTANT_COLOR',
13: 'BLEND_SRC1_COLOR',
14: 'BLEND_INV_SRC1_COLOR',
15: 'BLEND_SRC1_ALPHA',
16: 'BLEND_INV_SRC1_ALPHA',
17: 'BLEND_CONSTANT_ALPHA',
18: 'BLEND_ONE_MINUS_CONSTANT_ALPHA',
}
BLEND_ZERO = 0
BLEND_ONE = 1
BLEND_SRC_COLOR = 2
BLEND_ONE_MINUS_SRC_COLOR = 3
BLEND_SRC_ALPHA = 4
BLEND_ONE_MINUS_SRC_ALPHA = 5
BLEND_DST_ALPHA = 6
BLEND_ONE_MINUS_DST_ALPHA = 7
BLEND_DST_COLOR = 8
BLEND_ONE_MINUS_DST_COLOR = 9
BLEND_SRC_ALPHA_SATURATE = 10
BLEND_CONSTANT_COLOR = 11
BLEND_ONE_MINUS_CONSTANT_COLOR = 12
BLEND_SRC1_COLOR = 13
BLEND_INV_SRC1_COLOR = 14
BLEND_SRC1_ALPHA = 15
BLEND_INV_SRC1_ALPHA = 16
BLEND_CONSTANT_ALPHA = 17
BLEND_ONE_MINUS_CONSTANT_ALPHA = 18
BlendOp = ctypes.c_uint32 # enum
GL__ZERO = BLEND_ZERO # macro
GL__ONE = BLEND_ONE # macro
GL__SRC_COLOR = BLEND_SRC_COLOR # macro
GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro
GL__DST_COLOR = BLEND_DST_COLOR # macro
GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro
GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro
GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro
GL__DST_ALPHA = BLEND_DST_ALPHA # macro
GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro
GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro
GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro
GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro
GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro
GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro
# values for enumeration 'BlendOpt'
BlendOpt__enumvalues = {
0: 'FORCE_OPT_AUTO',
1: 'FORCE_OPT_DISABLE',
2: 'FORCE_OPT_ENABLE_IF_SRC_A_0',
3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0',
4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0',
5: 'FORCE_OPT_ENABLE_IF_SRC_A_1',
6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1',
7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1',
}
FORCE_OPT_AUTO = 0
FORCE_OPT_DISABLE = 1
FORCE_OPT_ENABLE_IF_SRC_A_0 = 2
FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3
FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4
FORCE_OPT_ENABLE_IF_SRC_A_1 = 5
FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6
FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7
BlendOpt = ctypes.c_uint32 # enum
# values for enumeration 'CBMode'
CBMode__enumvalues = {
0: 'CB_DISABLE',
1: 'CB_NORMAL',
2: 'CB_ELIMINATE_FAST_CLEAR',
3: 'CB_DCC_DECOMPRESS',
4: 'CB_RESERVED',
}
CB_DISABLE = 0
CB_NORMAL = 1
CB_ELIMINATE_FAST_CLEAR = 2
CB_DCC_DECOMPRESS = 3
CB_RESERVED = 4
CBMode = ctypes.c_uint32 # enum
# values for enumeration 'CBPerfClearFilterSel'
CBPerfClearFilterSel__enumvalues = {
0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR',
1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR',
}
CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0
CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1
CBPerfClearFilterSel = ctypes.c_uint32 # enum
# values for enumeration 'CBPerfOpFilterSel'
CBPerfOpFilterSel__enumvalues = {
0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY',
1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION',
2: 'CB_PERF_OP_FILTER_SEL_RESOLVE',
3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS',
4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS',
5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR',
}
CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0
CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1
CB_PERF_OP_FILTER_SEL_RESOLVE = 2
CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3
CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4
CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5
CBPerfOpFilterSel = ctypes.c_uint32 # enum
# values for enumeration 'CBPerfSel'
CBPerfSel__enumvalues = {
1: 'CB_PERF_SEL_BUSY',
2: 'CB_PERF_SEL_DRAWN_BUSY',
3: 'CB_PERF_SEL_DRAWN_PIXEL',
4: 'CB_PERF_SEL_DRAWN_QUAD',
5: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT',
15: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY',
16: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB',
17: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY',
18: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB',
21: 'CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST',
22: 'CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST_IN_FLIGHT',
23: 'CB_PERF_SEL_CC_CRW_GLX_REQ_WRITE_REQUEST',
24: 'CB_PERF_SEL_CC_CRW_GLX_SRC_WRITE_CYCLES',
25: 'CB_PERF_SEL_CC_FDCC_COMPRESS_FRAG_TIDS_IN',
26: 'CB_PERF_SEL_CC_FDCC_DECOMPRESS_FRAG_TIDS_OUT',
50: 'CB_PERF_SEL_EVENT',
51: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS',
52: 'CB_PERF_SEL_EVENT_CONTEXT_DONE',
53: 'CB_PERF_SEL_EVENT_CACHE_FLUSH',
54: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT',
55: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT',
56: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS',
57: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META',
58: 'CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS',
60: 'CB_PERF_SEL_STATIC_CLOCK_EN',
61: 'CB_PERF_SEL_PERFMON_CLOCK_EN',
62: 'CB_PERF_SEL_BLEND_CLOCK_EN',
63: 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN',
64: 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN',
65: 'CB_PERF_SEL_GRBM_CLOCK_EN',
66: 'CB_PERF_SEL_MEMARB_CLOCK_EN',
67: 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN',
68: 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN',
69: 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN',
70: 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN',
71: 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN',
72: 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN',
73: 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN',
74: 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN',
75: 'CB_PERF_SEL_EVENTS_CLK_EN',
80: 'CB_PERF_SEL_CC_TAG_HIT',
81: 'CB_PERF_SEL_CC_CACHE_TAG_MISS',
82: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS',
83: 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT',
88: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL',
89: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL',
90: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL',
91: 'CB_PERF_SEL_CC_CACHE_STALL',
92: 'CB_PERF_SEL_CC_CACHE_FLUSH',
93: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED',
94: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION',
95: 'CB_PERF_SEL_CC_CACHE_QBLOCKS_FLUSHED',
96: 'CB_PERF_SEL_CC_CACHE_DIRTY_QBLOCKS_FLUSHED',
97: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC',
98: 'CB_PERF_SEL_CCC_IN_EVICT_HAZARD_STALL',
99: 'CB_PERF_SEL_CCC_COLOR_RESOURCE_PANIC',
100: 'CB_PERF_SEL_CCC_FMASK_RESOURCE_PANIC',
101: 'CB_PERF_SEL_CCC_FREE_WAYS_PANIC',
102: 'CB_PERF_SEL_CCC_SKID_FIFO_FULL',
103: 'CB_PERF_SEL_CCC_SKID_FIFO_STALL',
104: 'CB_PERF_SEL_CCC_COLOR_RESOURCE_STALL',
105: 'CB_PERF_SEL_CCC_FMASK_RESOURCE_STALL',
106: 'CB_PERF_SEL_CCC_FREE_WAYS_STALL',
110: 'CB_PERF_SEL_BE_SRCFIFO_FULL',
111: 'CB_PERF_SEL_BE_RDLATFIFO_FULL',
112: 'CB_PERF_SEL_RDLAT_FIFO_QUAD_RESIDENCY_STALL',
113: 'CB_PERF_SEL_CC_QUADFRAG_VALID_READY',
114: 'CB_PERF_SEL_CC_QUADFRAG_VALID_READYB',
115: 'CB_PERF_SEL_CC_QUADFRAG_VALIDB_READY',
116: 'CB_PERF_SEL_CC_QUADFRAG_VALIDB_READYB',
118: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READY',
119: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READYB',
120: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READY',
121: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READYB',
150: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH',
151: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT',
152: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT',
180: 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED',
181: 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED',
182: 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED',
183: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST',
184: 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT',
185: 'CB_PERF_SEL_BLEND_STALL_ON_CACHE_ACCESS',
186: 'CB_PERF_SEL_BLEND_COLLISION_DUE_TO_CACHE_WRITE',
187: 'CB_PERF_SEL_BLEND_RAW_HAZARD_STALL',
190: 'CB_PERF_SEL_BE_CS_FILLRATE_1X2',
191: 'CB_PERF_SEL_BE_CS_FILLRATE_2X1',
192: 'CB_PERF_SEL_BE_CS_FILLRATE_2X2',
250: 'CB_PERF_SEL_FORMAT_IS_32_R',
251: 'CB_PERF_SEL_FORMAT_IS_32_AR',
252: 'CB_PERF_SEL_FORMAT_IS_32_GR',
253: 'CB_PERF_SEL_FORMAT_IS_32_ABGR',
254: 'CB_PERF_SEL_FORMAT_IS_FP16_ABGR',
255: 'CB_PERF_SEL_FORMAT_IS_SIGNED16_ABGR',
256: 'CB_PERF_SEL_FORMAT_IS_UNSIGNED16_ABGR',
257: 'CB_PERF_SEL_FORMAT_IS_32BPP_8PIX',
258: 'CB_PERF_SEL_FORMAT_IS_16_16_UNSIGNED_8PIX',
259: 'CB_PERF_SEL_FORMAT_IS_16_16_SIGNED_8PIX',
260: 'CB_PERF_SEL_FORMAT_IS_16_16_FLOAT_8PIX',
261: 'CB_PERF_SEL_EXPORT_ADDED_1_FRAGMENT',
262: 'CB_PERF_SEL_EXPORT_ADDED_2_FRAGMENTS',
263: 'CB_PERF_SEL_EXPORT_ADDED_3_FRAGMENTS',
264: 'CB_PERF_SEL_EXPORT_ADDED_4_FRAGMENTS',
265: 'CB_PERF_SEL_EXPORT_ADDED_5_FRAGMENTS',
266: 'CB_PERF_SEL_EXPORT_ADDED_6_FRAGMENTS',
267: 'CB_PERF_SEL_EXPORT_ADDED_7_FRAGMENTS',
268: 'CB_PERF_SEL_EXPORT_BLEND_OPT_DONT_READ_DST',
269: 'CB_PERF_SEL_EXPORT_BLEND_OPT_BLEND_BYPASS',
270: 'CB_PERF_SEL_EXPORT_BLEND_OPT_DISCARD_PIXELS',
271: 'CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_BEFORE_UPDATE',
272: 'CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_AFTER_UPDATE',
273: 'CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_BEFORE_UPDATE',
274: 'CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_AFTER_UPDATE',
275: 'CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_BEFORE_UPDATE',
276: 'CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_AFTER_UPDATE',
277: 'CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_BEFORE_UPDATE',
278: 'CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_AFTER_UPDATE',
279: 'CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_BEFORE_UPDATE',
280: 'CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_AFTER_UPDATE',
281: 'CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_BEFORE_UPDATE',
282: 'CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_AFTER_UPDATE',
283: 'CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_BEFORE_UPDATE',
284: 'CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_AFTER_UPDATE',
285: 'CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_BEFORE_UPDATE',
286: 'CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_AFTER_UPDATE',
287: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_0',
288: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_1',
289: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_2',
290: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_3',
291: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_4',
292: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_5',
293: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_6',
294: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_7',
295: 'CB_PERF_SEL_EXPORT_REMOVED_1_FRAGMENT',
296: 'CB_PERF_SEL_EXPORT_REMOVED_2_FRAGMENTS',
297: 'CB_PERF_SEL_EXPORT_REMOVED_3_FRAGMENTS',
298: 'CB_PERF_SEL_EXPORT_REMOVED_4_FRAGMENTS',
299: 'CB_PERF_SEL_EXPORT_REMOVED_5_FRAGMENTS',
300: 'CB_PERF_SEL_EXPORT_REMOVED_6_FRAGMENTS',
301: 'CB_PERF_SEL_EXPORT_REMOVED_7_FRAGMENTS',
302: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_0',
303: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_1',
304: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_2',
305: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_3',
306: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_4',
307: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_5',
308: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_6',
309: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_7',
310: 'CB_PERF_SEL_EXPORT_KILLED_BY_COLOR_INVALID',
311: 'CB_PERF_SEL_EXPORT_KILLED_BY_DISCARD_PIXEL',
312: 'CB_PERF_SEL_EXPORT_KILLED_BY_NULL_SAMPLE_MASK',
313: 'CB_PERF_SEL_EXPORT_KILLED_BY_NULL_TARGET_SHADER_MASK',
}
CB_PERF_SEL_BUSY = 1
CB_PERF_SEL_DRAWN_BUSY = 2
CB_PERF_SEL_DRAWN_PIXEL = 3
CB_PERF_SEL_DRAWN_QUAD = 4
CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 5
CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 15
CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 16
CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 17
CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 18
CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST = 21
CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST_IN_FLIGHT = 22
CB_PERF_SEL_CC_CRW_GLX_REQ_WRITE_REQUEST = 23
CB_PERF_SEL_CC_CRW_GLX_SRC_WRITE_CYCLES = 24
CB_PERF_SEL_CC_FDCC_COMPRESS_FRAG_TIDS_IN = 25
CB_PERF_SEL_CC_FDCC_DECOMPRESS_FRAG_TIDS_OUT = 26
CB_PERF_SEL_EVENT = 50
CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 51
CB_PERF_SEL_EVENT_CONTEXT_DONE = 52
CB_PERF_SEL_EVENT_CACHE_FLUSH = 53
CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 54
CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 55
CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 56
CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 57
CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS = 58
CB_PERF_SEL_STATIC_CLOCK_EN = 60
CB_PERF_SEL_PERFMON_CLOCK_EN = 61
CB_PERF_SEL_BLEND_CLOCK_EN = 62
CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 63
CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 64
CB_PERF_SEL_GRBM_CLOCK_EN = 65
CB_PERF_SEL_MEMARB_CLOCK_EN = 66
CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 67
CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 68
CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 69
CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 70
CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 71
CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 72
CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 73
CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 74
CB_PERF_SEL_EVENTS_CLK_EN = 75
CB_PERF_SEL_CC_TAG_HIT = 80
CB_PERF_SEL_CC_CACHE_TAG_MISS = 81
CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 82
CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 83
CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 88
CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 89
CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 90
CB_PERF_SEL_CC_CACHE_STALL = 91
CB_PERF_SEL_CC_CACHE_FLUSH = 92
CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 93
CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 94
CB_PERF_SEL_CC_CACHE_QBLOCKS_FLUSHED = 95
CB_PERF_SEL_CC_CACHE_DIRTY_QBLOCKS_FLUSHED = 96
CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 97
CB_PERF_SEL_CCC_IN_EVICT_HAZARD_STALL = 98
CB_PERF_SEL_CCC_COLOR_RESOURCE_PANIC = 99
CB_PERF_SEL_CCC_FMASK_RESOURCE_PANIC = 100
CB_PERF_SEL_CCC_FREE_WAYS_PANIC = 101
CB_PERF_SEL_CCC_SKID_FIFO_FULL = 102
CB_PERF_SEL_CCC_SKID_FIFO_STALL = 103
CB_PERF_SEL_CCC_COLOR_RESOURCE_STALL = 104
CB_PERF_SEL_CCC_FMASK_RESOURCE_STALL = 105
CB_PERF_SEL_CCC_FREE_WAYS_STALL = 106
CB_PERF_SEL_BE_SRCFIFO_FULL = 110
CB_PERF_SEL_BE_RDLATFIFO_FULL = 111
CB_PERF_SEL_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 112
CB_PERF_SEL_CC_QUADFRAG_VALID_READY = 113
CB_PERF_SEL_CC_QUADFRAG_VALID_READYB = 114
CB_PERF_SEL_CC_QUADFRAG_VALIDB_READY = 115
CB_PERF_SEL_CC_QUADFRAG_VALIDB_READYB = 116
CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READY = 118
CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READYB = 119
CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READY = 120
CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READYB = 121
CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 150
CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 151
CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 152
CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 180
CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 181
CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 182
CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 183
CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 184
CB_PERF_SEL_BLEND_STALL_ON_CACHE_ACCESS = 185
CB_PERF_SEL_BLEND_COLLISION_DUE_TO_CACHE_WRITE = 186
CB_PERF_SEL_BLEND_RAW_HAZARD_STALL = 187
CB_PERF_SEL_BE_CS_FILLRATE_1X2 = 190
CB_PERF_SEL_BE_CS_FILLRATE_2X1 = 191
CB_PERF_SEL_BE_CS_FILLRATE_2X2 = 192
CB_PERF_SEL_FORMAT_IS_32_R = 250
CB_PERF_SEL_FORMAT_IS_32_AR = 251
CB_PERF_SEL_FORMAT_IS_32_GR = 252
CB_PERF_SEL_FORMAT_IS_32_ABGR = 253
CB_PERF_SEL_FORMAT_IS_FP16_ABGR = 254
CB_PERF_SEL_FORMAT_IS_SIGNED16_ABGR = 255
CB_PERF_SEL_FORMAT_IS_UNSIGNED16_ABGR = 256
CB_PERF_SEL_FORMAT_IS_32BPP_8PIX = 257
CB_PERF_SEL_FORMAT_IS_16_16_UNSIGNED_8PIX = 258
CB_PERF_SEL_FORMAT_IS_16_16_SIGNED_8PIX = 259
CB_PERF_SEL_FORMAT_IS_16_16_FLOAT_8PIX = 260
CB_PERF_SEL_EXPORT_ADDED_1_FRAGMENT = 261
CB_PERF_SEL_EXPORT_ADDED_2_FRAGMENTS = 262
CB_PERF_SEL_EXPORT_ADDED_3_FRAGMENTS = 263
CB_PERF_SEL_EXPORT_ADDED_4_FRAGMENTS = 264
CB_PERF_SEL_EXPORT_ADDED_5_FRAGMENTS = 265
CB_PERF_SEL_EXPORT_ADDED_6_FRAGMENTS = 266
CB_PERF_SEL_EXPORT_ADDED_7_FRAGMENTS = 267
CB_PERF_SEL_EXPORT_BLEND_OPT_DONT_READ_DST = 268
CB_PERF_SEL_EXPORT_BLEND_OPT_BLEND_BYPASS = 269
CB_PERF_SEL_EXPORT_BLEND_OPT_DISCARD_PIXELS = 270
CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_BEFORE_UPDATE = 271
CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_AFTER_UPDATE = 272
CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_BEFORE_UPDATE = 273
CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_AFTER_UPDATE = 274
CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_BEFORE_UPDATE = 275
CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_AFTER_UPDATE = 276
CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_BEFORE_UPDATE = 277
CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_AFTER_UPDATE = 278
CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_BEFORE_UPDATE = 279
CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_AFTER_UPDATE = 280
CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_BEFORE_UPDATE = 281
CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_AFTER_UPDATE = 282
CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_BEFORE_UPDATE = 283
CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_AFTER_UPDATE = 284
CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_BEFORE_UPDATE = 285
CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_AFTER_UPDATE = 286
CB_PERF_SEL_EXPORT_READS_FRAGMENT_0 = 287
CB_PERF_SEL_EXPORT_READS_FRAGMENT_1 = 288
CB_PERF_SEL_EXPORT_READS_FRAGMENT_2 = 289
CB_PERF_SEL_EXPORT_READS_FRAGMENT_3 = 290
CB_PERF_SEL_EXPORT_READS_FRAGMENT_4 = 291
CB_PERF_SEL_EXPORT_READS_FRAGMENT_5 = 292
CB_PERF_SEL_EXPORT_READS_FRAGMENT_6 = 293
CB_PERF_SEL_EXPORT_READS_FRAGMENT_7 = 294
CB_PERF_SEL_EXPORT_REMOVED_1_FRAGMENT = 295
CB_PERF_SEL_EXPORT_REMOVED_2_FRAGMENTS = 296
CB_PERF_SEL_EXPORT_REMOVED_3_FRAGMENTS = 297
CB_PERF_SEL_EXPORT_REMOVED_4_FRAGMENTS = 298
CB_PERF_SEL_EXPORT_REMOVED_5_FRAGMENTS = 299
CB_PERF_SEL_EXPORT_REMOVED_6_FRAGMENTS = 300
CB_PERF_SEL_EXPORT_REMOVED_7_FRAGMENTS = 301
CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_0 = 302
CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_1 = 303
CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_2 = 304
CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_3 = 305
CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_4 = 306
CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_5 = 307
CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_6 = 308
CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_7 = 309
CB_PERF_SEL_EXPORT_KILLED_BY_COLOR_INVALID = 310
CB_PERF_SEL_EXPORT_KILLED_BY_DISCARD_PIXEL = 311
CB_PERF_SEL_EXPORT_KILLED_BY_NULL_SAMPLE_MASK = 312
CB_PERF_SEL_EXPORT_KILLED_BY_NULL_TARGET_SHADER_MASK = 313
CBPerfSel = ctypes.c_uint32 # enum
# values for enumeration 'CombFunc'
CombFunc__enumvalues = {
0: 'COMB_DST_PLUS_SRC',
1: 'COMB_SRC_MINUS_DST',
2: 'COMB_MIN_DST_SRC',
3: 'COMB_MAX_DST_SRC',
4: 'COMB_DST_MINUS_SRC',
}
COMB_DST_PLUS_SRC = 0
COMB_SRC_MINUS_DST = 1
COMB_MIN_DST_SRC = 2
COMB_MAX_DST_SRC = 3
COMB_DST_MINUS_SRC = 4
CombFunc = ctypes.c_uint32 # enum
# values for enumeration 'MemArbMode'
MemArbMode__enumvalues = {
0: 'MEM_ARB_MODE_FIXED',
1: 'MEM_ARB_MODE_AGE',
2: 'MEM_ARB_MODE_WEIGHT',
3: 'MEM_ARB_MODE_BOTH',
}
MEM_ARB_MODE_FIXED = 0
MEM_ARB_MODE_AGE = 1
MEM_ARB_MODE_WEIGHT = 2
MEM_ARB_MODE_BOTH = 3
MemArbMode = ctypes.c_uint32 # enum
# values for enumeration 'PH_PERFCNT_SEL'
PH_PERFCNT_SEL__enumvalues = {
0: 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID',
1: 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
2: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES',
3: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
4: 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW',
5: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE',
6: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
7: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
8: 'PH_PERF_SEL_SC0_ARB_BUSY',
9: 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP',
10: 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP',
11: 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP',
12: 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE',
13: 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW',
14: 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM',
15: 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO',
16: 'PH_PERF_SEL_SC0_SEND',
17: 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND',
18: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX',
19: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND',
20: 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION',
21: 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION',
22: 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION',
23: 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
24: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD',
25: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE',
26: 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY',
27: 'PH_PERF_SEL_SC0_PA0_FIFO_FULL',
28: 'PH_PERF_SEL_SC0_PA0_NULL_WE',
29: 'PH_PERF_SEL_SC0_PA0_EVENT_WE',
30: 'PH_PERF_SEL_SC0_PA0_FPOV_WE',
31: 'PH_PERF_SEL_SC0_PA0_FPOP_WE',
32: 'PH_PERF_SEL_SC0_PA0_EOP_WE',
33: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD',
34: 'PH_PERF_SEL_SC0_PA0_EOPG_WE',
35: 'PH_PERF_SEL_SC0_PA0_DEALLOC_WE',
36: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD',
37: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE',
38: 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY',
39: 'PH_PERF_SEL_SC0_PA1_FIFO_FULL',
40: 'PH_PERF_SEL_SC0_PA1_NULL_WE',
41: 'PH_PERF_SEL_SC0_PA1_EVENT_WE',
42: 'PH_PERF_SEL_SC0_PA1_FPOV_WE',
43: 'PH_PERF_SEL_SC0_PA1_FPOP_WE',
44: 'PH_PERF_SEL_SC0_PA1_EOP_WE',
45: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD',
46: 'PH_PERF_SEL_SC0_PA1_EOPG_WE',
47: 'PH_PERF_SEL_SC0_PA1_DEALLOC_WE',
48: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD',
49: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE',
50: 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY',
51: 'PH_PERF_SEL_SC0_PA2_FIFO_FULL',
52: 'PH_PERF_SEL_SC0_PA2_NULL_WE',
53: 'PH_PERF_SEL_SC0_PA2_EVENT_WE',
54: 'PH_PERF_SEL_SC0_PA2_FPOV_WE',
55: 'PH_PERF_SEL_SC0_PA2_FPOP_WE',
56: 'PH_PERF_SEL_SC0_PA2_EOP_WE',
57: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD',
58: 'PH_PERF_SEL_SC0_PA2_EOPG_WE',
59: 'PH_PERF_SEL_SC0_PA2_DEALLOC_WE',
60: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD',
61: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE',
62: 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY',
63: 'PH_PERF_SEL_SC0_PA3_FIFO_FULL',
64: 'PH_PERF_SEL_SC0_PA3_NULL_WE',
65: 'PH_PERF_SEL_SC0_PA3_EVENT_WE',
66: 'PH_PERF_SEL_SC0_PA3_FPOV_WE',
67: 'PH_PERF_SEL_SC0_PA3_FPOP_WE',
68: 'PH_PERF_SEL_SC0_PA3_EOP_WE',
69: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD',
70: 'PH_PERF_SEL_SC0_PA3_EOPG_WE',
71: 'PH_PERF_SEL_SC0_PA3_DEALLOC_WE',
72: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD',
73: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE',
74: 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY',
75: 'PH_PERF_SEL_SC0_PA4_FIFO_FULL',
76: 'PH_PERF_SEL_SC0_PA4_NULL_WE',
77: 'PH_PERF_SEL_SC0_PA4_EVENT_WE',
78: 'PH_PERF_SEL_SC0_PA4_FPOV_WE',
79: 'PH_PERF_SEL_SC0_PA4_FPOP_WE',
80: 'PH_PERF_SEL_SC0_PA4_EOP_WE',
81: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD',
82: 'PH_PERF_SEL_SC0_PA4_EOPG_WE',
83: 'PH_PERF_SEL_SC0_PA4_DEALLOC_WE',
84: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD',
85: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE',
86: 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY',
87: 'PH_PERF_SEL_SC0_PA5_FIFO_FULL',
88: 'PH_PERF_SEL_SC0_PA5_NULL_WE',
89: 'PH_PERF_SEL_SC0_PA5_EVENT_WE',
90: 'PH_PERF_SEL_SC0_PA5_FPOV_WE',
91: 'PH_PERF_SEL_SC0_PA5_FPOP_WE',
92: 'PH_PERF_SEL_SC0_PA5_EOP_WE',
93: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD',
94: 'PH_PERF_SEL_SC0_PA5_EOPG_WE',
95: 'PH_PERF_SEL_SC0_PA5_DEALLOC_WE',
96: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD',
97: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE',
98: 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY',
99: 'PH_PERF_SEL_SC0_PA6_FIFO_FULL',
100: 'PH_PERF_SEL_SC0_PA6_NULL_WE',
101: 'PH_PERF_SEL_SC0_PA6_EVENT_WE',
102: 'PH_PERF_SEL_SC0_PA6_FPOV_WE',
103: 'PH_PERF_SEL_SC0_PA6_FPOP_WE',
104: 'PH_PERF_SEL_SC0_PA6_EOP_WE',
105: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD',
106: 'PH_PERF_SEL_SC0_PA6_EOPG_WE',
107: 'PH_PERF_SEL_SC0_PA6_DEALLOC_WE',
108: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD',
109: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE',
110: 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY',
111: 'PH_PERF_SEL_SC0_PA7_FIFO_FULL',
112: 'PH_PERF_SEL_SC0_PA7_NULL_WE',
113: 'PH_PERF_SEL_SC0_PA7_EVENT_WE',
114: 'PH_PERF_SEL_SC0_PA7_FPOV_WE',
115: 'PH_PERF_SEL_SC0_PA7_FPOP_WE',
116: 'PH_PERF_SEL_SC0_PA7_EOP_WE',
117: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD',
118: 'PH_PERF_SEL_SC0_PA7_EOPG_WE',
119: 'PH_PERF_SEL_SC0_PA7_DEALLOC_WE',
120: 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID',
121: 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
122: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES',
123: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
124: 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW',
125: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE',
126: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
127: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
128: 'PH_PERF_SEL_SC1_ARB_BUSY',
129: 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP',
130: 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP',
131: 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP',
132: 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE',
133: 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW',
134: 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM',
135: 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO',
136: 'PH_PERF_SEL_SC1_SEND',
137: 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND',
138: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX',
139: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND',
140: 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION',
141: 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION',
142: 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
143: 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
144: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD',
145: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE',
146: 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY',
147: 'PH_PERF_SEL_SC1_PA0_FIFO_FULL',
148: 'PH_PERF_SEL_SC1_PA0_NULL_WE',
149: 'PH_PERF_SEL_SC1_PA0_EVENT_WE',
150: 'PH_PERF_SEL_SC1_PA0_FPOV_WE',
151: 'PH_PERF_SEL_SC1_PA0_FPOP_WE',
152: 'PH_PERF_SEL_SC1_PA0_EOP_WE',
153: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD',
154: 'PH_PERF_SEL_SC1_PA0_EOPG_WE',
155: 'PH_PERF_SEL_SC1_PA0_DEALLOC_WE',
156: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD',
157: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE',
158: 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY',
159: 'PH_PERF_SEL_SC1_PA1_FIFO_FULL',
160: 'PH_PERF_SEL_SC1_PA1_NULL_WE',
161: 'PH_PERF_SEL_SC1_PA1_EVENT_WE',
162: 'PH_PERF_SEL_SC1_PA1_FPOV_WE',
163: 'PH_PERF_SEL_SC1_PA1_FPOP_WE',
164: 'PH_PERF_SEL_SC1_PA1_EOP_WE',
165: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD',
166: 'PH_PERF_SEL_SC1_PA1_EOPG_WE',
167: 'PH_PERF_SEL_SC1_PA1_DEALLOC_WE',
168: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD',
169: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE',
170: 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY',
171: 'PH_PERF_SEL_SC1_PA2_FIFO_FULL',
172: 'PH_PERF_SEL_SC1_PA2_NULL_WE',
173: 'PH_PERF_SEL_SC1_PA2_EVENT_WE',
174: 'PH_PERF_SEL_SC1_PA2_FPOV_WE',
175: 'PH_PERF_SEL_SC1_PA2_FPOP_WE',
176: 'PH_PERF_SEL_SC1_PA2_EOP_WE',
177: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD',
178: 'PH_PERF_SEL_SC1_PA2_EOPG_WE',
179: 'PH_PERF_SEL_SC1_PA2_DEALLOC_WE',
180: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD',
181: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE',
182: 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY',
183: 'PH_PERF_SEL_SC1_PA3_FIFO_FULL',
184: 'PH_PERF_SEL_SC1_PA3_NULL_WE',
185: 'PH_PERF_SEL_SC1_PA3_EVENT_WE',
186: 'PH_PERF_SEL_SC1_PA3_FPOV_WE',
187: 'PH_PERF_SEL_SC1_PA3_FPOP_WE',
188: 'PH_PERF_SEL_SC1_PA3_EOP_WE',
189: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD',
190: 'PH_PERF_SEL_SC1_PA3_EOPG_WE',
191: 'PH_PERF_SEL_SC1_PA3_DEALLOC_WE',
192: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD',
193: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE',
194: 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY',
195: 'PH_PERF_SEL_SC1_PA4_FIFO_FULL',
196: 'PH_PERF_SEL_SC1_PA4_NULL_WE',
197: 'PH_PERF_SEL_SC1_PA4_EVENT_WE',
198: 'PH_PERF_SEL_SC1_PA4_FPOV_WE',
199: 'PH_PERF_SEL_SC1_PA4_FPOP_WE',
200: 'PH_PERF_SEL_SC1_PA4_EOP_WE',
201: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD',
202: 'PH_PERF_SEL_SC1_PA4_EOPG_WE',
203: 'PH_PERF_SEL_SC1_PA4_DEALLOC_WE',
204: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD',
205: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE',
206: 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY',
207: 'PH_PERF_SEL_SC1_PA5_FIFO_FULL',
208: 'PH_PERF_SEL_SC1_PA5_NULL_WE',
209: 'PH_PERF_SEL_SC1_PA5_EVENT_WE',
210: 'PH_PERF_SEL_SC1_PA5_FPOV_WE',
211: 'PH_PERF_SEL_SC1_PA5_FPOP_WE',
212: 'PH_PERF_SEL_SC1_PA5_EOP_WE',
213: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD',
214: 'PH_PERF_SEL_SC1_PA5_EOPG_WE',
215: 'PH_PERF_SEL_SC1_PA5_DEALLOC_WE',
216: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD',
217: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE',
218: 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY',
219: 'PH_PERF_SEL_SC1_PA6_FIFO_FULL',
220: 'PH_PERF_SEL_SC1_PA6_NULL_WE',
221: 'PH_PERF_SEL_SC1_PA6_EVENT_WE',
222: 'PH_PERF_SEL_SC1_PA6_FPOV_WE',
223: 'PH_PERF_SEL_SC1_PA6_FPOP_WE',
224: 'PH_PERF_SEL_SC1_PA6_EOP_WE',
225: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD',
226: 'PH_PERF_SEL_SC1_PA6_EOPG_WE',
227: 'PH_PERF_SEL_SC1_PA6_DEALLOC_WE',
228: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD',
229: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE',
230: 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY',
231: 'PH_PERF_SEL_SC1_PA7_FIFO_FULL',
232: 'PH_PERF_SEL_SC1_PA7_NULL_WE',
233: 'PH_PERF_SEL_SC1_PA7_EVENT_WE',
234: 'PH_PERF_SEL_SC1_PA7_FPOV_WE',
235: 'PH_PERF_SEL_SC1_PA7_FPOP_WE',
236: 'PH_PERF_SEL_SC1_PA7_EOP_WE',
237: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD',
238: 'PH_PERF_SEL_SC1_PA7_EOPG_WE',
239: 'PH_PERF_SEL_SC1_PA7_DEALLOC_WE',
240: 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID',
241: 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
242: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES',
243: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
244: 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW',
245: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE',
246: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
247: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
248: 'PH_PERF_SEL_SC2_ARB_BUSY',
249: 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP',
250: 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP',
251: 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP',
252: 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE',
253: 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW',
254: 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM',
255: 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO',
256: 'PH_PERF_SEL_SC2_SEND',
257: 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND',
258: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX',
259: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND',
260: 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION',
261: 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION',
262: 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
263: 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
264: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD',
265: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE',
266: 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY',
267: 'PH_PERF_SEL_SC2_PA0_FIFO_FULL',
268: 'PH_PERF_SEL_SC2_PA0_NULL_WE',
269: 'PH_PERF_SEL_SC2_PA0_EVENT_WE',
270: 'PH_PERF_SEL_SC2_PA0_FPOV_WE',
271: 'PH_PERF_SEL_SC2_PA0_FPOP_WE',
272: 'PH_PERF_SEL_SC2_PA0_EOP_WE',
273: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD',
274: 'PH_PERF_SEL_SC2_PA0_EOPG_WE',
275: 'PH_PERF_SEL_SC2_PA0_DEALLOC_WE',
276: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD',
277: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE',
278: 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY',
279: 'PH_PERF_SEL_SC2_PA1_FIFO_FULL',
280: 'PH_PERF_SEL_SC2_PA1_NULL_WE',
281: 'PH_PERF_SEL_SC2_PA1_EVENT_WE',
282: 'PH_PERF_SEL_SC2_PA1_FPOV_WE',
283: 'PH_PERF_SEL_SC2_PA1_FPOP_WE',
284: 'PH_PERF_SEL_SC2_PA1_EOP_WE',
285: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD',
286: 'PH_PERF_SEL_SC2_PA1_EOPG_WE',
287: 'PH_PERF_SEL_SC2_PA1_DEALLOC_WE',
288: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD',
289: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE',
290: 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY',
291: 'PH_PERF_SEL_SC2_PA2_FIFO_FULL',
292: 'PH_PERF_SEL_SC2_PA2_NULL_WE',
293: 'PH_PERF_SEL_SC2_PA2_EVENT_WE',
294: 'PH_PERF_SEL_SC2_PA2_FPOV_WE',
295: 'PH_PERF_SEL_SC2_PA2_FPOP_WE',
296: 'PH_PERF_SEL_SC2_PA2_EOP_WE',
297: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD',
298: 'PH_PERF_SEL_SC2_PA2_EOPG_WE',
299: 'PH_PERF_SEL_SC2_PA2_DEALLOC_WE',
300: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD',
301: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE',
302: 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY',
303: 'PH_PERF_SEL_SC2_PA3_FIFO_FULL',
304: 'PH_PERF_SEL_SC2_PA3_NULL_WE',
305: 'PH_PERF_SEL_SC2_PA3_EVENT_WE',
306: 'PH_PERF_SEL_SC2_PA3_FPOV_WE',
307: 'PH_PERF_SEL_SC2_PA3_FPOP_WE',
308: 'PH_PERF_SEL_SC2_PA3_EOP_WE',
309: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD',
310: 'PH_PERF_SEL_SC2_PA3_EOPG_WE',
311: 'PH_PERF_SEL_SC2_PA3_DEALLOC_WE',
312: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD',
313: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE',
314: 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY',
315: 'PH_PERF_SEL_SC2_PA4_FIFO_FULL',
316: 'PH_PERF_SEL_SC2_PA4_NULL_WE',
317: 'PH_PERF_SEL_SC2_PA4_EVENT_WE',
318: 'PH_PERF_SEL_SC2_PA4_FPOV_WE',
319: 'PH_PERF_SEL_SC2_PA4_FPOP_WE',
320: 'PH_PERF_SEL_SC2_PA4_EOP_WE',
321: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD',
322: 'PH_PERF_SEL_SC2_PA4_EOPG_WE',
323: 'PH_PERF_SEL_SC2_PA4_DEALLOC_WE',
324: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD',
325: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE',
326: 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY',
327: 'PH_PERF_SEL_SC2_PA5_FIFO_FULL',
328: 'PH_PERF_SEL_SC2_PA5_NULL_WE',
329: 'PH_PERF_SEL_SC2_PA5_EVENT_WE',
330: 'PH_PERF_SEL_SC2_PA5_FPOV_WE',
331: 'PH_PERF_SEL_SC2_PA5_FPOP_WE',
332: 'PH_PERF_SEL_SC2_PA5_EOP_WE',
333: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD',
334: 'PH_PERF_SEL_SC2_PA5_EOPG_WE',
335: 'PH_PERF_SEL_SC2_PA5_DEALLOC_WE',
336: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD',
337: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE',
338: 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY',
339: 'PH_PERF_SEL_SC2_PA6_FIFO_FULL',
340: 'PH_PERF_SEL_SC2_PA6_NULL_WE',
341: 'PH_PERF_SEL_SC2_PA6_EVENT_WE',
342: 'PH_PERF_SEL_SC2_PA6_FPOV_WE',
343: 'PH_PERF_SEL_SC2_PA6_FPOP_WE',
344: 'PH_PERF_SEL_SC2_PA6_EOP_WE',
345: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD',
346: 'PH_PERF_SEL_SC2_PA6_EOPG_WE',
347: 'PH_PERF_SEL_SC2_PA6_DEALLOC_WE',
348: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD',
349: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE',
350: 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY',
351: 'PH_PERF_SEL_SC2_PA7_FIFO_FULL',
352: 'PH_PERF_SEL_SC2_PA7_NULL_WE',
353: 'PH_PERF_SEL_SC2_PA7_EVENT_WE',
354: 'PH_PERF_SEL_SC2_PA7_FPOV_WE',
355: 'PH_PERF_SEL_SC2_PA7_FPOP_WE',
356: 'PH_PERF_SEL_SC2_PA7_EOP_WE',
357: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD',
358: 'PH_PERF_SEL_SC2_PA7_EOPG_WE',
359: 'PH_PERF_SEL_SC2_PA7_DEALLOC_WE',
360: 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID',
361: 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
362: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES',
363: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
364: 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW',
365: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE',
366: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
367: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
368: 'PH_PERF_SEL_SC3_ARB_BUSY',
369: 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP',
370: 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP',
371: 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP',
372: 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE',
373: 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW',
374: 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM',
375: 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO',
376: 'PH_PERF_SEL_SC3_SEND',
377: 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND',
378: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX',
379: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND',
380: 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION',
381: 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION',
382: 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
383: 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
384: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD',
385: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE',
386: 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY',
387: 'PH_PERF_SEL_SC3_PA0_FIFO_FULL',
388: 'PH_PERF_SEL_SC3_PA0_NULL_WE',
389: 'PH_PERF_SEL_SC3_PA0_EVENT_WE',
390: 'PH_PERF_SEL_SC3_PA0_FPOV_WE',
391: 'PH_PERF_SEL_SC3_PA0_FPOP_WE',
392: 'PH_PERF_SEL_SC3_PA0_EOP_WE',
393: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD',
394: 'PH_PERF_SEL_SC3_PA0_EOPG_WE',
395: 'PH_PERF_SEL_SC3_PA0_DEALLOC_WE',
396: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD',
397: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE',
398: 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY',
399: 'PH_PERF_SEL_SC3_PA1_FIFO_FULL',
400: 'PH_PERF_SEL_SC3_PA1_NULL_WE',
401: 'PH_PERF_SEL_SC3_PA1_EVENT_WE',
402: 'PH_PERF_SEL_SC3_PA1_FPOV_WE',
403: 'PH_PERF_SEL_SC3_PA1_FPOP_WE',
404: 'PH_PERF_SEL_SC3_PA1_EOP_WE',
405: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD',
406: 'PH_PERF_SEL_SC3_PA1_EOPG_WE',
407: 'PH_PERF_SEL_SC3_PA1_DEALLOC_WE',
408: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD',
409: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE',
410: 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY',
411: 'PH_PERF_SEL_SC3_PA2_FIFO_FULL',
412: 'PH_PERF_SEL_SC3_PA2_NULL_WE',
413: 'PH_PERF_SEL_SC3_PA2_EVENT_WE',
414: 'PH_PERF_SEL_SC3_PA2_FPOV_WE',
415: 'PH_PERF_SEL_SC3_PA2_FPOP_WE',
416: 'PH_PERF_SEL_SC3_PA2_EOP_WE',
417: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD',
418: 'PH_PERF_SEL_SC3_PA2_EOPG_WE',
419: 'PH_PERF_SEL_SC3_PA2_DEALLOC_WE',
420: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD',
421: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE',
422: 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY',
423: 'PH_PERF_SEL_SC3_PA3_FIFO_FULL',
424: 'PH_PERF_SEL_SC3_PA3_NULL_WE',
425: 'PH_PERF_SEL_SC3_PA3_EVENT_WE',
426: 'PH_PERF_SEL_SC3_PA3_FPOV_WE',
427: 'PH_PERF_SEL_SC3_PA3_FPOP_WE',
428: 'PH_PERF_SEL_SC3_PA3_EOP_WE',
429: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD',
430: 'PH_PERF_SEL_SC3_PA3_EOPG_WE',
431: 'PH_PERF_SEL_SC3_PA3_DEALLOC_WE',
432: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD',
433: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE',
434: 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY',
435: 'PH_PERF_SEL_SC3_PA4_FIFO_FULL',
436: 'PH_PERF_SEL_SC3_PA4_NULL_WE',
437: 'PH_PERF_SEL_SC3_PA4_EVENT_WE',
438: 'PH_PERF_SEL_SC3_PA4_FPOV_WE',
439: 'PH_PERF_SEL_SC3_PA4_FPOP_WE',
440: 'PH_PERF_SEL_SC3_PA4_EOP_WE',
441: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD',
442: 'PH_PERF_SEL_SC3_PA4_EOPG_WE',
443: 'PH_PERF_SEL_SC3_PA4_DEALLOC_WE',
444: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD',
445: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE',
446: 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY',
447: 'PH_PERF_SEL_SC3_PA5_FIFO_FULL',
448: 'PH_PERF_SEL_SC3_PA5_NULL_WE',
449: 'PH_PERF_SEL_SC3_PA5_EVENT_WE',
450: 'PH_PERF_SEL_SC3_PA5_FPOV_WE',
451: 'PH_PERF_SEL_SC3_PA5_FPOP_WE',
452: 'PH_PERF_SEL_SC3_PA5_EOP_WE',
453: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD',
454: 'PH_PERF_SEL_SC3_PA5_EOPG_WE',
455: 'PH_PERF_SEL_SC3_PA5_DEALLOC_WE',
456: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD',
457: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE',
458: 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY',
459: 'PH_PERF_SEL_SC3_PA6_FIFO_FULL',
460: 'PH_PERF_SEL_SC3_PA6_NULL_WE',
461: 'PH_PERF_SEL_SC3_PA6_EVENT_WE',
462: 'PH_PERF_SEL_SC3_PA6_FPOV_WE',
463: 'PH_PERF_SEL_SC3_PA6_FPOP_WE',
464: 'PH_PERF_SEL_SC3_PA6_EOP_WE',
465: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD',
466: 'PH_PERF_SEL_SC3_PA6_EOPG_WE',
467: 'PH_PERF_SEL_SC3_PA6_DEALLOC_WE',
468: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD',
469: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE',
470: 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY',
471: 'PH_PERF_SEL_SC3_PA7_FIFO_FULL',
472: 'PH_PERF_SEL_SC3_PA7_NULL_WE',
473: 'PH_PERF_SEL_SC3_PA7_EVENT_WE',
474: 'PH_PERF_SEL_SC3_PA7_FPOV_WE',
475: 'PH_PERF_SEL_SC3_PA7_FPOP_WE',
476: 'PH_PERF_SEL_SC3_PA7_EOP_WE',
477: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD',
478: 'PH_PERF_SEL_SC3_PA7_EOPG_WE',
479: 'PH_PERF_SEL_SC3_PA7_DEALLOC_WE',
480: 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID',
481: 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
482: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES',
483: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
484: 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW',
485: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE',
486: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
487: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
488: 'PH_PERF_SEL_SC4_ARB_BUSY',
489: 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP',
490: 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP',
491: 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP',
492: 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE',
493: 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW',
494: 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM',
495: 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO',
496: 'PH_PERF_SEL_SC4_SEND',
497: 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND',
498: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX',
499: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND',
500: 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION',
501: 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION',
502: 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
503: 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
504: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD',
505: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE',
506: 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY',
507: 'PH_PERF_SEL_SC4_PA0_FIFO_FULL',
508: 'PH_PERF_SEL_SC4_PA0_NULL_WE',
509: 'PH_PERF_SEL_SC4_PA0_EVENT_WE',
510: 'PH_PERF_SEL_SC4_PA0_FPOV_WE',
511: 'PH_PERF_SEL_SC4_PA0_FPOP_WE',
512: 'PH_PERF_SEL_SC4_PA0_EOP_WE',
513: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD',
514: 'PH_PERF_SEL_SC4_PA0_EOPG_WE',
515: 'PH_PERF_SEL_SC4_PA0_DEALLOC_WE',
516: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD',
517: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE',
518: 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY',
519: 'PH_PERF_SEL_SC4_PA1_FIFO_FULL',
520: 'PH_PERF_SEL_SC4_PA1_NULL_WE',
521: 'PH_PERF_SEL_SC4_PA1_EVENT_WE',
522: 'PH_PERF_SEL_SC4_PA1_FPOV_WE',
523: 'PH_PERF_SEL_SC4_PA1_FPOP_WE',
524: 'PH_PERF_SEL_SC4_PA1_EOP_WE',
525: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD',
526: 'PH_PERF_SEL_SC4_PA1_EOPG_WE',
527: 'PH_PERF_SEL_SC4_PA1_DEALLOC_WE',
528: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD',
529: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE',
530: 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY',
531: 'PH_PERF_SEL_SC4_PA2_FIFO_FULL',
532: 'PH_PERF_SEL_SC4_PA2_NULL_WE',
533: 'PH_PERF_SEL_SC4_PA2_EVENT_WE',
534: 'PH_PERF_SEL_SC4_PA2_FPOV_WE',
535: 'PH_PERF_SEL_SC4_PA2_FPOP_WE',
536: 'PH_PERF_SEL_SC4_PA2_EOP_WE',
537: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD',
538: 'PH_PERF_SEL_SC4_PA2_EOPG_WE',
539: 'PH_PERF_SEL_SC4_PA2_DEALLOC_WE',
540: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD',
541: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE',
542: 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY',
543: 'PH_PERF_SEL_SC4_PA3_FIFO_FULL',
544: 'PH_PERF_SEL_SC4_PA3_NULL_WE',
545: 'PH_PERF_SEL_SC4_PA3_EVENT_WE',
546: 'PH_PERF_SEL_SC4_PA3_FPOV_WE',
547: 'PH_PERF_SEL_SC4_PA3_FPOP_WE',
548: 'PH_PERF_SEL_SC4_PA3_EOP_WE',
549: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD',
550: 'PH_PERF_SEL_SC4_PA3_EOPG_WE',
551: 'PH_PERF_SEL_SC4_PA3_DEALLOC_WE',
552: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD',
553: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE',
554: 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY',
555: 'PH_PERF_SEL_SC4_PA4_FIFO_FULL',
556: 'PH_PERF_SEL_SC4_PA4_NULL_WE',
557: 'PH_PERF_SEL_SC4_PA4_EVENT_WE',
558: 'PH_PERF_SEL_SC4_PA4_FPOV_WE',
559: 'PH_PERF_SEL_SC4_PA4_FPOP_WE',
560: 'PH_PERF_SEL_SC4_PA4_EOP_WE',
561: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD',
562: 'PH_PERF_SEL_SC4_PA4_EOPG_WE',
563: 'PH_PERF_SEL_SC4_PA4_DEALLOC_WE',
564: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD',
565: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE',
566: 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY',
567: 'PH_PERF_SEL_SC4_PA5_FIFO_FULL',
568: 'PH_PERF_SEL_SC4_PA5_NULL_WE',
569: 'PH_PERF_SEL_SC4_PA5_EVENT_WE',
570: 'PH_PERF_SEL_SC4_PA5_FPOV_WE',
571: 'PH_PERF_SEL_SC4_PA5_FPOP_WE',
572: 'PH_PERF_SEL_SC4_PA5_EOP_WE',
573: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD',
574: 'PH_PERF_SEL_SC4_PA5_EOPG_WE',
575: 'PH_PERF_SEL_SC4_PA5_DEALLOC_WE',
576: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD',
577: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE',
578: 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY',
579: 'PH_PERF_SEL_SC4_PA6_FIFO_FULL',
580: 'PH_PERF_SEL_SC4_PA6_NULL_WE',
581: 'PH_PERF_SEL_SC4_PA6_EVENT_WE',
582: 'PH_PERF_SEL_SC4_PA6_FPOV_WE',
583: 'PH_PERF_SEL_SC4_PA6_FPOP_WE',
584: 'PH_PERF_SEL_SC4_PA6_EOP_WE',
585: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD',
586: 'PH_PERF_SEL_SC4_PA6_EOPG_WE',
587: 'PH_PERF_SEL_SC4_PA6_DEALLOC_WE',
588: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD',
589: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE',
590: 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY',
591: 'PH_PERF_SEL_SC4_PA7_FIFO_FULL',
592: 'PH_PERF_SEL_SC4_PA7_NULL_WE',
593: 'PH_PERF_SEL_SC4_PA7_EVENT_WE',
594: 'PH_PERF_SEL_SC4_PA7_FPOV_WE',
595: 'PH_PERF_SEL_SC4_PA7_FPOP_WE',
596: 'PH_PERF_SEL_SC4_PA7_EOP_WE',
597: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD',
598: 'PH_PERF_SEL_SC4_PA7_EOPG_WE',
599: 'PH_PERF_SEL_SC4_PA7_DEALLOC_WE',
600: 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID',
601: 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
602: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES',
603: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
604: 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW',
605: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE',
606: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
607: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
608: 'PH_PERF_SEL_SC5_ARB_BUSY',
609: 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP',
610: 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP',
611: 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP',
612: 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE',
613: 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW',
614: 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM',
615: 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO',
616: 'PH_PERF_SEL_SC5_SEND',
617: 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND',
618: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX',
619: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND',
620: 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION',
621: 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION',
622: 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
623: 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
624: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD',
625: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE',
626: 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY',
627: 'PH_PERF_SEL_SC5_PA0_FIFO_FULL',
628: 'PH_PERF_SEL_SC5_PA0_NULL_WE',
629: 'PH_PERF_SEL_SC5_PA0_EVENT_WE',
630: 'PH_PERF_SEL_SC5_PA0_FPOV_WE',
631: 'PH_PERF_SEL_SC5_PA0_FPOP_WE',
632: 'PH_PERF_SEL_SC5_PA0_EOP_WE',
633: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD',
634: 'PH_PERF_SEL_SC5_PA0_EOPG_WE',
635: 'PH_PERF_SEL_SC5_PA0_DEALLOC_WE',
636: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD',
637: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE',
638: 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY',
639: 'PH_PERF_SEL_SC5_PA1_FIFO_FULL',
640: 'PH_PERF_SEL_SC5_PA1_NULL_WE',
641: 'PH_PERF_SEL_SC5_PA1_EVENT_WE',
642: 'PH_PERF_SEL_SC5_PA1_FPOV_WE',
643: 'PH_PERF_SEL_SC5_PA1_FPOP_WE',
644: 'PH_PERF_SEL_SC5_PA1_EOP_WE',
645: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD',
646: 'PH_PERF_SEL_SC5_PA1_EOPG_WE',
647: 'PH_PERF_SEL_SC5_PA1_DEALLOC_WE',
648: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD',
649: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE',
650: 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY',
651: 'PH_PERF_SEL_SC5_PA2_FIFO_FULL',
652: 'PH_PERF_SEL_SC5_PA2_NULL_WE',
653: 'PH_PERF_SEL_SC5_PA2_EVENT_WE',
654: 'PH_PERF_SEL_SC5_PA2_FPOV_WE',
655: 'PH_PERF_SEL_SC5_PA2_FPOP_WE',
656: 'PH_PERF_SEL_SC5_PA2_EOP_WE',
657: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD',
658: 'PH_PERF_SEL_SC5_PA2_EOPG_WE',
659: 'PH_PERF_SEL_SC5_PA2_DEALLOC_WE',
660: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD',
661: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE',
662: 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY',
663: 'PH_PERF_SEL_SC5_PA3_FIFO_FULL',
664: 'PH_PERF_SEL_SC5_PA3_NULL_WE',
665: 'PH_PERF_SEL_SC5_PA3_EVENT_WE',
666: 'PH_PERF_SEL_SC5_PA3_FPOV_WE',
667: 'PH_PERF_SEL_SC5_PA3_FPOP_WE',
668: 'PH_PERF_SEL_SC5_PA3_EOP_WE',
669: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD',
670: 'PH_PERF_SEL_SC5_PA3_EOPG_WE',
671: 'PH_PERF_SEL_SC5_PA3_DEALLOC_WE',
672: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD',
673: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE',
674: 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY',
675: 'PH_PERF_SEL_SC5_PA4_FIFO_FULL',
676: 'PH_PERF_SEL_SC5_PA4_NULL_WE',
677: 'PH_PERF_SEL_SC5_PA4_EVENT_WE',
678: 'PH_PERF_SEL_SC5_PA4_FPOV_WE',
679: 'PH_PERF_SEL_SC5_PA4_FPOP_WE',
680: 'PH_PERF_SEL_SC5_PA4_EOP_WE',
681: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD',
682: 'PH_PERF_SEL_SC5_PA4_EOPG_WE',
683: 'PH_PERF_SEL_SC5_PA4_DEALLOC_WE',
684: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD',
685: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE',
686: 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY',
687: 'PH_PERF_SEL_SC5_PA5_FIFO_FULL',
688: 'PH_PERF_SEL_SC5_PA5_NULL_WE',
689: 'PH_PERF_SEL_SC5_PA5_EVENT_WE',
690: 'PH_PERF_SEL_SC5_PA5_FPOV_WE',
691: 'PH_PERF_SEL_SC5_PA5_FPOP_WE',
692: 'PH_PERF_SEL_SC5_PA5_EOP_WE',
693: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD',
694: 'PH_PERF_SEL_SC5_PA5_EOPG_WE',
695: 'PH_PERF_SEL_SC5_PA5_DEALLOC_WE',
696: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD',
697: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE',
698: 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY',
699: 'PH_PERF_SEL_SC5_PA6_FIFO_FULL',
700: 'PH_PERF_SEL_SC5_PA6_NULL_WE',
701: 'PH_PERF_SEL_SC5_PA6_EVENT_WE',
702: 'PH_PERF_SEL_SC5_PA6_FPOV_WE',
703: 'PH_PERF_SEL_SC5_PA6_FPOP_WE',
704: 'PH_PERF_SEL_SC5_PA6_EOP_WE',
705: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD',
706: 'PH_PERF_SEL_SC5_PA6_EOPG_WE',
707: 'PH_PERF_SEL_SC5_PA6_DEALLOC_WE',
708: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD',
709: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE',
710: 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY',
711: 'PH_PERF_SEL_SC5_PA7_FIFO_FULL',
712: 'PH_PERF_SEL_SC5_PA7_NULL_WE',
713: 'PH_PERF_SEL_SC5_PA7_EVENT_WE',
714: 'PH_PERF_SEL_SC5_PA7_FPOV_WE',
715: 'PH_PERF_SEL_SC5_PA7_FPOP_WE',
716: 'PH_PERF_SEL_SC5_PA7_EOP_WE',
717: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD',
718: 'PH_PERF_SEL_SC5_PA7_EOPG_WE',
719: 'PH_PERF_SEL_SC5_PA7_DEALLOC_WE',
720: 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID',
721: 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
722: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES',
723: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
724: 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW',
725: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE',
726: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
727: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
728: 'PH_PERF_SEL_SC6_ARB_BUSY',
729: 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP',
730: 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP',
731: 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP',
732: 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE',
733: 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW',
734: 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM',
735: 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO',
736: 'PH_PERF_SEL_SC6_SEND',
737: 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND',
738: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX',
739: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND',
740: 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION',
741: 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION',
742: 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
743: 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
744: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD',
745: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE',
746: 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY',
747: 'PH_PERF_SEL_SC6_PA0_FIFO_FULL',
748: 'PH_PERF_SEL_SC6_PA0_NULL_WE',
749: 'PH_PERF_SEL_SC6_PA0_EVENT_WE',
750: 'PH_PERF_SEL_SC6_PA0_FPOV_WE',
751: 'PH_PERF_SEL_SC6_PA0_FPOP_WE',
752: 'PH_PERF_SEL_SC6_PA0_EOP_WE',
753: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD',
754: 'PH_PERF_SEL_SC6_PA0_EOPG_WE',
755: 'PH_PERF_SEL_SC6_PA0_DEALLOC_WE',
756: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD',
757: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE',
758: 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY',
759: 'PH_PERF_SEL_SC6_PA1_FIFO_FULL',
760: 'PH_PERF_SEL_SC6_PA1_NULL_WE',
761: 'PH_PERF_SEL_SC6_PA1_EVENT_WE',
762: 'PH_PERF_SEL_SC6_PA1_FPOV_WE',
763: 'PH_PERF_SEL_SC6_PA1_FPOP_WE',
764: 'PH_PERF_SEL_SC6_PA1_EOP_WE',
765: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD',
766: 'PH_PERF_SEL_SC6_PA1_EOPG_WE',
767: 'PH_PERF_SEL_SC6_PA1_DEALLOC_WE',
768: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD',
769: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE',
770: 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY',
771: 'PH_PERF_SEL_SC6_PA2_FIFO_FULL',
772: 'PH_PERF_SEL_SC6_PA2_NULL_WE',
773: 'PH_PERF_SEL_SC6_PA2_EVENT_WE',
774: 'PH_PERF_SEL_SC6_PA2_FPOV_WE',
775: 'PH_PERF_SEL_SC6_PA2_FPOP_WE',
776: 'PH_PERF_SEL_SC6_PA2_EOP_WE',
777: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD',
778: 'PH_PERF_SEL_SC6_PA2_EOPG_WE',
779: 'PH_PERF_SEL_SC6_PA2_DEALLOC_WE',
780: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD',
781: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE',
782: 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY',
783: 'PH_PERF_SEL_SC6_PA3_FIFO_FULL',
784: 'PH_PERF_SEL_SC6_PA3_NULL_WE',
785: 'PH_PERF_SEL_SC6_PA3_EVENT_WE',
786: 'PH_PERF_SEL_SC6_PA3_FPOV_WE',
787: 'PH_PERF_SEL_SC6_PA3_FPOP_WE',
788: 'PH_PERF_SEL_SC6_PA3_EOP_WE',
789: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD',
790: 'PH_PERF_SEL_SC6_PA3_EOPG_WE',
791: 'PH_PERF_SEL_SC6_PA3_DEALLOC_WE',
792: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD',
793: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE',
794: 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY',
795: 'PH_PERF_SEL_SC6_PA4_FIFO_FULL',
796: 'PH_PERF_SEL_SC6_PA4_NULL_WE',
797: 'PH_PERF_SEL_SC6_PA4_EVENT_WE',
798: 'PH_PERF_SEL_SC6_PA4_FPOV_WE',
799: 'PH_PERF_SEL_SC6_PA4_FPOP_WE',
800: 'PH_PERF_SEL_SC6_PA4_EOP_WE',
801: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD',
802: 'PH_PERF_SEL_SC6_PA4_EOPG_WE',
803: 'PH_PERF_SEL_SC6_PA4_DEALLOC_WE',
804: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD',
805: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE',
806: 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY',
807: 'PH_PERF_SEL_SC6_PA5_FIFO_FULL',
808: 'PH_PERF_SEL_SC6_PA5_NULL_WE',
809: 'PH_PERF_SEL_SC6_PA5_EVENT_WE',
810: 'PH_PERF_SEL_SC6_PA5_FPOV_WE',
811: 'PH_PERF_SEL_SC6_PA5_FPOP_WE',
812: 'PH_PERF_SEL_SC6_PA5_EOP_WE',
813: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD',
814: 'PH_PERF_SEL_SC6_PA5_EOPG_WE',
815: 'PH_PERF_SEL_SC6_PA5_DEALLOC_WE',
816: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD',
817: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE',
818: 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY',
819: 'PH_PERF_SEL_SC6_PA6_FIFO_FULL',
820: 'PH_PERF_SEL_SC6_PA6_NULL_WE',
821: 'PH_PERF_SEL_SC6_PA6_EVENT_WE',
822: 'PH_PERF_SEL_SC6_PA6_FPOV_WE',
823: 'PH_PERF_SEL_SC6_PA6_FPOP_WE',
824: 'PH_PERF_SEL_SC6_PA6_EOP_WE',
825: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD',
826: 'PH_PERF_SEL_SC6_PA6_EOPG_WE',
827: 'PH_PERF_SEL_SC6_PA6_DEALLOC_WE',
828: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD',
829: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE',
830: 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY',
831: 'PH_PERF_SEL_SC6_PA7_FIFO_FULL',
832: 'PH_PERF_SEL_SC6_PA7_NULL_WE',
833: 'PH_PERF_SEL_SC6_PA7_EVENT_WE',
834: 'PH_PERF_SEL_SC6_PA7_FPOV_WE',
835: 'PH_PERF_SEL_SC6_PA7_FPOP_WE',
836: 'PH_PERF_SEL_SC6_PA7_EOP_WE',
837: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD',
838: 'PH_PERF_SEL_SC6_PA7_EOPG_WE',
839: 'PH_PERF_SEL_SC6_PA7_DEALLOC_WE',
840: 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID',
841: 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
842: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES',
843: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
844: 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW',
845: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE',
846: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
847: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
848: 'PH_PERF_SEL_SC7_ARB_BUSY',
849: 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP',
850: 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP',
851: 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP',
852: 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE',
853: 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW',
854: 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM',
855: 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO',
856: 'PH_PERF_SEL_SC7_SEND',
857: 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND',
858: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX',
859: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND',
860: 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION',
861: 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION',
862: 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
863: 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
864: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD',
865: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE',
866: 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY',
867: 'PH_PERF_SEL_SC7_PA0_FIFO_FULL',
868: 'PH_PERF_SEL_SC7_PA0_NULL_WE',
869: 'PH_PERF_SEL_SC7_PA0_EVENT_WE',
870: 'PH_PERF_SEL_SC7_PA0_FPOV_WE',
871: 'PH_PERF_SEL_SC7_PA0_FPOP_WE',
872: 'PH_PERF_SEL_SC7_PA0_EOP_WE',
873: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD',
874: 'PH_PERF_SEL_SC7_PA0_EOPG_WE',
875: 'PH_PERF_SEL_SC7_PA0_DEALLOC_WE',
876: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD',
877: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE',
878: 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY',
879: 'PH_PERF_SEL_SC7_PA1_FIFO_FULL',
880: 'PH_PERF_SEL_SC7_PA1_NULL_WE',
881: 'PH_PERF_SEL_SC7_PA1_EVENT_WE',
882: 'PH_PERF_SEL_SC7_PA1_FPOV_WE',
883: 'PH_PERF_SEL_SC7_PA1_FPOP_WE',
884: 'PH_PERF_SEL_SC7_PA1_EOP_WE',
885: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD',
886: 'PH_PERF_SEL_SC7_PA1_EOPG_WE',
887: 'PH_PERF_SEL_SC7_PA1_DEALLOC_WE',
888: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD',
889: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE',
890: 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY',
891: 'PH_PERF_SEL_SC7_PA2_FIFO_FULL',
892: 'PH_PERF_SEL_SC7_PA2_NULL_WE',
893: 'PH_PERF_SEL_SC7_PA2_EVENT_WE',
894: 'PH_PERF_SEL_SC7_PA2_FPOV_WE',
895: 'PH_PERF_SEL_SC7_PA2_FPOP_WE',
896: 'PH_PERF_SEL_SC7_PA2_EOP_WE',
897: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD',
898: 'PH_PERF_SEL_SC7_PA2_EOPG_WE',
899: 'PH_PERF_SEL_SC7_PA2_DEALLOC_WE',
900: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD',
901: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE',
902: 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY',
903: 'PH_PERF_SEL_SC7_PA3_FIFO_FULL',
904: 'PH_PERF_SEL_SC7_PA3_NULL_WE',
905: 'PH_PERF_SEL_SC7_PA3_EVENT_WE',
906: 'PH_PERF_SEL_SC7_PA3_FPOV_WE',
907: 'PH_PERF_SEL_SC7_PA3_FPOP_WE',
908: 'PH_PERF_SEL_SC7_PA3_EOP_WE',
909: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD',
910: 'PH_PERF_SEL_SC7_PA3_EOPG_WE',
911: 'PH_PERF_SEL_SC7_PA3_DEALLOC_WE',
912: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD',
913: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE',
914: 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY',
915: 'PH_PERF_SEL_SC7_PA4_FIFO_FULL',
916: 'PH_PERF_SEL_SC7_PA4_NULL_WE',
917: 'PH_PERF_SEL_SC7_PA4_EVENT_WE',
918: 'PH_PERF_SEL_SC7_PA4_FPOV_WE',
919: 'PH_PERF_SEL_SC7_PA4_FPOP_WE',
920: 'PH_PERF_SEL_SC7_PA4_EOP_WE',
921: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD',
922: 'PH_PERF_SEL_SC7_PA4_EOPG_WE',
923: 'PH_PERF_SEL_SC7_PA4_DEALLOC_WE',
924: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD',
925: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE',
926: 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY',
927: 'PH_PERF_SEL_SC7_PA5_FIFO_FULL',
928: 'PH_PERF_SEL_SC7_PA5_NULL_WE',
929: 'PH_PERF_SEL_SC7_PA5_EVENT_WE',
930: 'PH_PERF_SEL_SC7_PA5_FPOV_WE',
931: 'PH_PERF_SEL_SC7_PA5_FPOP_WE',
932: 'PH_PERF_SEL_SC7_PA5_EOP_WE',
933: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD',
934: 'PH_PERF_SEL_SC7_PA5_EOPG_WE',
935: 'PH_PERF_SEL_SC7_PA5_DEALLOC_WE',
936: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD',
937: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE',
938: 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY',
939: 'PH_PERF_SEL_SC7_PA6_FIFO_FULL',
940: 'PH_PERF_SEL_SC7_PA6_NULL_WE',
941: 'PH_PERF_SEL_SC7_PA6_EVENT_WE',
942: 'PH_PERF_SEL_SC7_PA6_FPOV_WE',
943: 'PH_PERF_SEL_SC7_PA6_FPOP_WE',
944: 'PH_PERF_SEL_SC7_PA6_EOP_WE',
945: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD',
946: 'PH_PERF_SEL_SC7_PA6_EOPG_WE',
947: 'PH_PERF_SEL_SC7_PA6_DEALLOC_WE',
948: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD',
949: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE',
950: 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY',
951: 'PH_PERF_SEL_SC7_PA7_FIFO_FULL',
952: 'PH_PERF_SEL_SC7_PA7_NULL_WE',
953: 'PH_PERF_SEL_SC7_PA7_EVENT_WE',
954: 'PH_PERF_SEL_SC7_PA7_FPOV_WE',
955: 'PH_PERF_SEL_SC7_PA7_FPOP_WE',
956: 'PH_PERF_SEL_SC7_PA7_EOP_WE',
957: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD',
958: 'PH_PERF_SEL_SC7_PA7_EOPG_WE',
959: 'PH_PERF_SEL_SC7_PA7_DEALLOC_WE',
960: 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW',
961: 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW',
962: 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW',
963: 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW',
964: 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW',
965: 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW',
966: 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW',
967: 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW',
968: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE',
969: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE',
970: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE',
971: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE',
972: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE',
973: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE',
974: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE',
975: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE',
976: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
977: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
978: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
979: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
980: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
981: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
982: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
983: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
984: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
985: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
986: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
987: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
988: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
989: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
990: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
991: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
992: 'PH_PERF_SC0_FIFO_STATUS_0',
993: 'PH_PERF_SC0_FIFO_STATUS_1',
994: 'PH_PERF_SC0_FIFO_STATUS_2',
995: 'PH_PERF_SC0_FIFO_STATUS_3',
996: 'PH_PERF_SC1_FIFO_STATUS_0',
997: 'PH_PERF_SC1_FIFO_STATUS_1',
998: 'PH_PERF_SC1_FIFO_STATUS_2',
999: 'PH_PERF_SC1_FIFO_STATUS_3',
1000: 'PH_PERF_SC2_FIFO_STATUS_0',
1001: 'PH_PERF_SC2_FIFO_STATUS_1',
1002: 'PH_PERF_SC2_FIFO_STATUS_2',
1003: 'PH_PERF_SC2_FIFO_STATUS_3',
1004: 'PH_PERF_SC3_FIFO_STATUS_0',
1005: 'PH_PERF_SC3_FIFO_STATUS_1',
1006: 'PH_PERF_SC3_FIFO_STATUS_2',
1007: 'PH_PERF_SC3_FIFO_STATUS_3',
1008: 'PH_PERF_SC4_FIFO_STATUS_0',
1009: 'PH_PERF_SC4_FIFO_STATUS_1',
1010: 'PH_PERF_SC4_FIFO_STATUS_2',
1011: 'PH_PERF_SC4_FIFO_STATUS_3',
1012: 'PH_PERF_SC5_FIFO_STATUS_0',
1013: 'PH_PERF_SC5_FIFO_STATUS_1',
1014: 'PH_PERF_SC5_FIFO_STATUS_2',
1015: 'PH_PERF_SC5_FIFO_STATUS_3',
1016: 'PH_PERF_SC6_FIFO_STATUS_0',
1017: 'PH_PERF_SC6_FIFO_STATUS_1',
1018: 'PH_PERF_SC6_FIFO_STATUS_2',
1019: 'PH_PERF_SC6_FIFO_STATUS_3',
1020: 'PH_PERF_SC7_FIFO_STATUS_0',
1021: 'PH_PERF_SC7_FIFO_STATUS_1',
1022: 'PH_PERF_SC7_FIFO_STATUS_2',
1023: 'PH_PERF_SC7_FIFO_STATUS_3',
}
PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0
PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 1
PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 2
PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 3
PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 4
PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 5
PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 6
PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 7
PH_PERF_SEL_SC0_ARB_BUSY = 8
PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 9
PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 10
PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 11
PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 12
PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 13
PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 14
PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 15
PH_PERF_SEL_SC0_SEND = 16
PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 17
PH_PERF_SEL_SC0_CREDIT_AT_MAX = 18
PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 19
PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 20
PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 21
PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 22
PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 23
PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 24
PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 25
PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 26
PH_PERF_SEL_SC0_PA0_FIFO_FULL = 27
PH_PERF_SEL_SC0_PA0_NULL_WE = 28
PH_PERF_SEL_SC0_PA0_EVENT_WE = 29
PH_PERF_SEL_SC0_PA0_FPOV_WE = 30
PH_PERF_SEL_SC0_PA0_FPOP_WE = 31
PH_PERF_SEL_SC0_PA0_EOP_WE = 32
PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 33
PH_PERF_SEL_SC0_PA0_EOPG_WE = 34
PH_PERF_SEL_SC0_PA0_DEALLOC_WE = 35
PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 36
PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 37
PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 38
PH_PERF_SEL_SC0_PA1_FIFO_FULL = 39
PH_PERF_SEL_SC0_PA1_NULL_WE = 40
PH_PERF_SEL_SC0_PA1_EVENT_WE = 41
PH_PERF_SEL_SC0_PA1_FPOV_WE = 42
PH_PERF_SEL_SC0_PA1_FPOP_WE = 43
PH_PERF_SEL_SC0_PA1_EOP_WE = 44
PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 45
PH_PERF_SEL_SC0_PA1_EOPG_WE = 46
PH_PERF_SEL_SC0_PA1_DEALLOC_WE = 47
PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 48
PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 49
PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 50
PH_PERF_SEL_SC0_PA2_FIFO_FULL = 51
PH_PERF_SEL_SC0_PA2_NULL_WE = 52
PH_PERF_SEL_SC0_PA2_EVENT_WE = 53
PH_PERF_SEL_SC0_PA2_FPOV_WE = 54
PH_PERF_SEL_SC0_PA2_FPOP_WE = 55
PH_PERF_SEL_SC0_PA2_EOP_WE = 56
PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 57
PH_PERF_SEL_SC0_PA2_EOPG_WE = 58
PH_PERF_SEL_SC0_PA2_DEALLOC_WE = 59
PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 60
PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 61
PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 62
PH_PERF_SEL_SC0_PA3_FIFO_FULL = 63
PH_PERF_SEL_SC0_PA3_NULL_WE = 64
PH_PERF_SEL_SC0_PA3_EVENT_WE = 65
PH_PERF_SEL_SC0_PA3_FPOV_WE = 66
PH_PERF_SEL_SC0_PA3_FPOP_WE = 67
PH_PERF_SEL_SC0_PA3_EOP_WE = 68
PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 69
PH_PERF_SEL_SC0_PA3_EOPG_WE = 70
PH_PERF_SEL_SC0_PA3_DEALLOC_WE = 71
PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 72
PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 73
PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 74
PH_PERF_SEL_SC0_PA4_FIFO_FULL = 75
PH_PERF_SEL_SC0_PA4_NULL_WE = 76
PH_PERF_SEL_SC0_PA4_EVENT_WE = 77
PH_PERF_SEL_SC0_PA4_FPOV_WE = 78
PH_PERF_SEL_SC0_PA4_FPOP_WE = 79
PH_PERF_SEL_SC0_PA4_EOP_WE = 80
PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 81
PH_PERF_SEL_SC0_PA4_EOPG_WE = 82
PH_PERF_SEL_SC0_PA4_DEALLOC_WE = 83
PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 84
PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 85
PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 86
PH_PERF_SEL_SC0_PA5_FIFO_FULL = 87
PH_PERF_SEL_SC0_PA5_NULL_WE = 88
PH_PERF_SEL_SC0_PA5_EVENT_WE = 89
PH_PERF_SEL_SC0_PA5_FPOV_WE = 90
PH_PERF_SEL_SC0_PA5_FPOP_WE = 91
PH_PERF_SEL_SC0_PA5_EOP_WE = 92
PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 93
PH_PERF_SEL_SC0_PA5_EOPG_WE = 94
PH_PERF_SEL_SC0_PA5_DEALLOC_WE = 95
PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 96
PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 97
PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 98
PH_PERF_SEL_SC0_PA6_FIFO_FULL = 99
PH_PERF_SEL_SC0_PA6_NULL_WE = 100
PH_PERF_SEL_SC0_PA6_EVENT_WE = 101
PH_PERF_SEL_SC0_PA6_FPOV_WE = 102
PH_PERF_SEL_SC0_PA6_FPOP_WE = 103
PH_PERF_SEL_SC0_PA6_EOP_WE = 104
PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 105
PH_PERF_SEL_SC0_PA6_EOPG_WE = 106
PH_PERF_SEL_SC0_PA6_DEALLOC_WE = 107
PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 108
PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 109
PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 110
PH_PERF_SEL_SC0_PA7_FIFO_FULL = 111
PH_PERF_SEL_SC0_PA7_NULL_WE = 112
PH_PERF_SEL_SC0_PA7_EVENT_WE = 113
PH_PERF_SEL_SC0_PA7_FPOV_WE = 114
PH_PERF_SEL_SC0_PA7_FPOP_WE = 115
PH_PERF_SEL_SC0_PA7_EOP_WE = 116
PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 117
PH_PERF_SEL_SC0_PA7_EOPG_WE = 118
PH_PERF_SEL_SC0_PA7_DEALLOC_WE = 119
PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 120
PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 121
PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 122
PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 123
PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 124
PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 125
PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 126
PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 127
PH_PERF_SEL_SC1_ARB_BUSY = 128
PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 129
PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 130
PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 131
PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 132
PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 133
PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 134
PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 135
PH_PERF_SEL_SC1_SEND = 136
PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 137
PH_PERF_SEL_SC1_CREDIT_AT_MAX = 138
PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 139
PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 140
PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 141
PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 142
PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 143
PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 144
PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 145
PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 146
PH_PERF_SEL_SC1_PA0_FIFO_FULL = 147
PH_PERF_SEL_SC1_PA0_NULL_WE = 148
PH_PERF_SEL_SC1_PA0_EVENT_WE = 149
PH_PERF_SEL_SC1_PA0_FPOV_WE = 150
PH_PERF_SEL_SC1_PA0_FPOP_WE = 151
PH_PERF_SEL_SC1_PA0_EOP_WE = 152
PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 153
PH_PERF_SEL_SC1_PA0_EOPG_WE = 154
PH_PERF_SEL_SC1_PA0_DEALLOC_WE = 155
PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 156
PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 157
PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 158
PH_PERF_SEL_SC1_PA1_FIFO_FULL = 159
PH_PERF_SEL_SC1_PA1_NULL_WE = 160
PH_PERF_SEL_SC1_PA1_EVENT_WE = 161
PH_PERF_SEL_SC1_PA1_FPOV_WE = 162
PH_PERF_SEL_SC1_PA1_FPOP_WE = 163
PH_PERF_SEL_SC1_PA1_EOP_WE = 164
PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 165
PH_PERF_SEL_SC1_PA1_EOPG_WE = 166
PH_PERF_SEL_SC1_PA1_DEALLOC_WE = 167
PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 168
PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 169
PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 170
PH_PERF_SEL_SC1_PA2_FIFO_FULL = 171
PH_PERF_SEL_SC1_PA2_NULL_WE = 172
PH_PERF_SEL_SC1_PA2_EVENT_WE = 173
PH_PERF_SEL_SC1_PA2_FPOV_WE = 174
PH_PERF_SEL_SC1_PA2_FPOP_WE = 175
PH_PERF_SEL_SC1_PA2_EOP_WE = 176
PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 177
PH_PERF_SEL_SC1_PA2_EOPG_WE = 178
PH_PERF_SEL_SC1_PA2_DEALLOC_WE = 179
PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 180
PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 181
PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 182
PH_PERF_SEL_SC1_PA3_FIFO_FULL = 183
PH_PERF_SEL_SC1_PA3_NULL_WE = 184
PH_PERF_SEL_SC1_PA3_EVENT_WE = 185
PH_PERF_SEL_SC1_PA3_FPOV_WE = 186
PH_PERF_SEL_SC1_PA3_FPOP_WE = 187
PH_PERF_SEL_SC1_PA3_EOP_WE = 188
PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 189
PH_PERF_SEL_SC1_PA3_EOPG_WE = 190
PH_PERF_SEL_SC1_PA3_DEALLOC_WE = 191
PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 192
PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 193
PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 194
PH_PERF_SEL_SC1_PA4_FIFO_FULL = 195
PH_PERF_SEL_SC1_PA4_NULL_WE = 196
PH_PERF_SEL_SC1_PA4_EVENT_WE = 197
PH_PERF_SEL_SC1_PA4_FPOV_WE = 198
PH_PERF_SEL_SC1_PA4_FPOP_WE = 199
PH_PERF_SEL_SC1_PA4_EOP_WE = 200
PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 201
PH_PERF_SEL_SC1_PA4_EOPG_WE = 202
PH_PERF_SEL_SC1_PA4_DEALLOC_WE = 203
PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 204
PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 205
PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 206
PH_PERF_SEL_SC1_PA5_FIFO_FULL = 207
PH_PERF_SEL_SC1_PA5_NULL_WE = 208
PH_PERF_SEL_SC1_PA5_EVENT_WE = 209
PH_PERF_SEL_SC1_PA5_FPOV_WE = 210
PH_PERF_SEL_SC1_PA5_FPOP_WE = 211
PH_PERF_SEL_SC1_PA5_EOP_WE = 212
PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 213
PH_PERF_SEL_SC1_PA5_EOPG_WE = 214
PH_PERF_SEL_SC1_PA5_DEALLOC_WE = 215
PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 216
PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 217
PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 218
PH_PERF_SEL_SC1_PA6_FIFO_FULL = 219
PH_PERF_SEL_SC1_PA6_NULL_WE = 220
PH_PERF_SEL_SC1_PA6_EVENT_WE = 221
PH_PERF_SEL_SC1_PA6_FPOV_WE = 222
PH_PERF_SEL_SC1_PA6_FPOP_WE = 223
PH_PERF_SEL_SC1_PA6_EOP_WE = 224
PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 225
PH_PERF_SEL_SC1_PA6_EOPG_WE = 226
PH_PERF_SEL_SC1_PA6_DEALLOC_WE = 227
PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 228
PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 229
PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 230
PH_PERF_SEL_SC1_PA7_FIFO_FULL = 231
PH_PERF_SEL_SC1_PA7_NULL_WE = 232
PH_PERF_SEL_SC1_PA7_EVENT_WE = 233
PH_PERF_SEL_SC1_PA7_FPOV_WE = 234
PH_PERF_SEL_SC1_PA7_FPOP_WE = 235
PH_PERF_SEL_SC1_PA7_EOP_WE = 236
PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 237
PH_PERF_SEL_SC1_PA7_EOPG_WE = 238
PH_PERF_SEL_SC1_PA7_DEALLOC_WE = 239
PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 240
PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 241
PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 242
PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 243
PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 244
PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 245
PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 246
PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 247
PH_PERF_SEL_SC2_ARB_BUSY = 248
PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 249
PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 250
PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 251
PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 252
PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 253
PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 254
PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 255
PH_PERF_SEL_SC2_SEND = 256
PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 257
PH_PERF_SEL_SC2_CREDIT_AT_MAX = 258
PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 259
PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 260
PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 261
PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 262
PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 263
PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 264
PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 265
PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 266
PH_PERF_SEL_SC2_PA0_FIFO_FULL = 267
PH_PERF_SEL_SC2_PA0_NULL_WE = 268
PH_PERF_SEL_SC2_PA0_EVENT_WE = 269
PH_PERF_SEL_SC2_PA0_FPOV_WE = 270
PH_PERF_SEL_SC2_PA0_FPOP_WE = 271
PH_PERF_SEL_SC2_PA0_EOP_WE = 272
PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 273
PH_PERF_SEL_SC2_PA0_EOPG_WE = 274
PH_PERF_SEL_SC2_PA0_DEALLOC_WE = 275
PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 276
PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 277
PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 278
PH_PERF_SEL_SC2_PA1_FIFO_FULL = 279
PH_PERF_SEL_SC2_PA1_NULL_WE = 280
PH_PERF_SEL_SC2_PA1_EVENT_WE = 281
PH_PERF_SEL_SC2_PA1_FPOV_WE = 282
PH_PERF_SEL_SC2_PA1_FPOP_WE = 283
PH_PERF_SEL_SC2_PA1_EOP_WE = 284
PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 285
PH_PERF_SEL_SC2_PA1_EOPG_WE = 286
PH_PERF_SEL_SC2_PA1_DEALLOC_WE = 287
PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 288
PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 289
PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 290
PH_PERF_SEL_SC2_PA2_FIFO_FULL = 291
PH_PERF_SEL_SC2_PA2_NULL_WE = 292
PH_PERF_SEL_SC2_PA2_EVENT_WE = 293
PH_PERF_SEL_SC2_PA2_FPOV_WE = 294
PH_PERF_SEL_SC2_PA2_FPOP_WE = 295
PH_PERF_SEL_SC2_PA2_EOP_WE = 296
PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 297
PH_PERF_SEL_SC2_PA2_EOPG_WE = 298
PH_PERF_SEL_SC2_PA2_DEALLOC_WE = 299
PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 300
PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 301
PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 302
PH_PERF_SEL_SC2_PA3_FIFO_FULL = 303
PH_PERF_SEL_SC2_PA3_NULL_WE = 304
PH_PERF_SEL_SC2_PA3_EVENT_WE = 305
PH_PERF_SEL_SC2_PA3_FPOV_WE = 306
PH_PERF_SEL_SC2_PA3_FPOP_WE = 307
PH_PERF_SEL_SC2_PA3_EOP_WE = 308
PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 309
PH_PERF_SEL_SC2_PA3_EOPG_WE = 310
PH_PERF_SEL_SC2_PA3_DEALLOC_WE = 311
PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 312
PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 313
PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 314
PH_PERF_SEL_SC2_PA4_FIFO_FULL = 315
PH_PERF_SEL_SC2_PA4_NULL_WE = 316
PH_PERF_SEL_SC2_PA4_EVENT_WE = 317
PH_PERF_SEL_SC2_PA4_FPOV_WE = 318
PH_PERF_SEL_SC2_PA4_FPOP_WE = 319
PH_PERF_SEL_SC2_PA4_EOP_WE = 320
PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 321
PH_PERF_SEL_SC2_PA4_EOPG_WE = 322
PH_PERF_SEL_SC2_PA4_DEALLOC_WE = 323
PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 324
PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 325
PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 326
PH_PERF_SEL_SC2_PA5_FIFO_FULL = 327
PH_PERF_SEL_SC2_PA5_NULL_WE = 328
PH_PERF_SEL_SC2_PA5_EVENT_WE = 329
PH_PERF_SEL_SC2_PA5_FPOV_WE = 330
PH_PERF_SEL_SC2_PA5_FPOP_WE = 331
PH_PERF_SEL_SC2_PA5_EOP_WE = 332
PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 333
PH_PERF_SEL_SC2_PA5_EOPG_WE = 334
PH_PERF_SEL_SC2_PA5_DEALLOC_WE = 335
PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 336
PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 337
PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 338
PH_PERF_SEL_SC2_PA6_FIFO_FULL = 339
PH_PERF_SEL_SC2_PA6_NULL_WE = 340
PH_PERF_SEL_SC2_PA6_EVENT_WE = 341
PH_PERF_SEL_SC2_PA6_FPOV_WE = 342
PH_PERF_SEL_SC2_PA6_FPOP_WE = 343
PH_PERF_SEL_SC2_PA6_EOP_WE = 344
PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 345
PH_PERF_SEL_SC2_PA6_EOPG_WE = 346
PH_PERF_SEL_SC2_PA6_DEALLOC_WE = 347
PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 348
PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 349
PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 350
PH_PERF_SEL_SC2_PA7_FIFO_FULL = 351
PH_PERF_SEL_SC2_PA7_NULL_WE = 352
PH_PERF_SEL_SC2_PA7_EVENT_WE = 353
PH_PERF_SEL_SC2_PA7_FPOV_WE = 354
PH_PERF_SEL_SC2_PA7_FPOP_WE = 355
PH_PERF_SEL_SC2_PA7_EOP_WE = 356
PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 357
PH_PERF_SEL_SC2_PA7_EOPG_WE = 358
PH_PERF_SEL_SC2_PA7_DEALLOC_WE = 359
PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 360
PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 361
PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 362
PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 363
PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 364
PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 365
PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 366
PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 367
PH_PERF_SEL_SC3_ARB_BUSY = 368
PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 369
PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 370
PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 371
PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 372
PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 373
PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 374
PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 375
PH_PERF_SEL_SC3_SEND = 376
PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 377
PH_PERF_SEL_SC3_CREDIT_AT_MAX = 378
PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 379
PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 380
PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 381
PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 382
PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 383
PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 384
PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 385
PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 386
PH_PERF_SEL_SC3_PA0_FIFO_FULL = 387
PH_PERF_SEL_SC3_PA0_NULL_WE = 388
PH_PERF_SEL_SC3_PA0_EVENT_WE = 389
PH_PERF_SEL_SC3_PA0_FPOV_WE = 390
PH_PERF_SEL_SC3_PA0_FPOP_WE = 391
PH_PERF_SEL_SC3_PA0_EOP_WE = 392
PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 393
PH_PERF_SEL_SC3_PA0_EOPG_WE = 394
PH_PERF_SEL_SC3_PA0_DEALLOC_WE = 395
PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 396
PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 397
PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 398
PH_PERF_SEL_SC3_PA1_FIFO_FULL = 399
PH_PERF_SEL_SC3_PA1_NULL_WE = 400
PH_PERF_SEL_SC3_PA1_EVENT_WE = 401
PH_PERF_SEL_SC3_PA1_FPOV_WE = 402
PH_PERF_SEL_SC3_PA1_FPOP_WE = 403
PH_PERF_SEL_SC3_PA1_EOP_WE = 404
PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 405
PH_PERF_SEL_SC3_PA1_EOPG_WE = 406
PH_PERF_SEL_SC3_PA1_DEALLOC_WE = 407
PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 408
PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 409
PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 410
PH_PERF_SEL_SC3_PA2_FIFO_FULL = 411
PH_PERF_SEL_SC3_PA2_NULL_WE = 412
PH_PERF_SEL_SC3_PA2_EVENT_WE = 413
PH_PERF_SEL_SC3_PA2_FPOV_WE = 414
PH_PERF_SEL_SC3_PA2_FPOP_WE = 415
PH_PERF_SEL_SC3_PA2_EOP_WE = 416
PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 417
PH_PERF_SEL_SC3_PA2_EOPG_WE = 418
PH_PERF_SEL_SC3_PA2_DEALLOC_WE = 419
PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 420
PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 421
PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 422
PH_PERF_SEL_SC3_PA3_FIFO_FULL = 423
PH_PERF_SEL_SC3_PA3_NULL_WE = 424
PH_PERF_SEL_SC3_PA3_EVENT_WE = 425
PH_PERF_SEL_SC3_PA3_FPOV_WE = 426
PH_PERF_SEL_SC3_PA3_FPOP_WE = 427
PH_PERF_SEL_SC3_PA3_EOP_WE = 428
PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 429
PH_PERF_SEL_SC3_PA3_EOPG_WE = 430
PH_PERF_SEL_SC3_PA3_DEALLOC_WE = 431
PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 432
PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 433
PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 434
PH_PERF_SEL_SC3_PA4_FIFO_FULL = 435
PH_PERF_SEL_SC3_PA4_NULL_WE = 436
PH_PERF_SEL_SC3_PA4_EVENT_WE = 437
PH_PERF_SEL_SC3_PA4_FPOV_WE = 438
PH_PERF_SEL_SC3_PA4_FPOP_WE = 439
PH_PERF_SEL_SC3_PA4_EOP_WE = 440
PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 441
PH_PERF_SEL_SC3_PA4_EOPG_WE = 442
PH_PERF_SEL_SC3_PA4_DEALLOC_WE = 443
PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 444
PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 445
PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 446
PH_PERF_SEL_SC3_PA5_FIFO_FULL = 447
PH_PERF_SEL_SC3_PA5_NULL_WE = 448
PH_PERF_SEL_SC3_PA5_EVENT_WE = 449
PH_PERF_SEL_SC3_PA5_FPOV_WE = 450
PH_PERF_SEL_SC3_PA5_FPOP_WE = 451
PH_PERF_SEL_SC3_PA5_EOP_WE = 452
PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 453
PH_PERF_SEL_SC3_PA5_EOPG_WE = 454
PH_PERF_SEL_SC3_PA5_DEALLOC_WE = 455
PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 456
PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 457
PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 458
PH_PERF_SEL_SC3_PA6_FIFO_FULL = 459
PH_PERF_SEL_SC3_PA6_NULL_WE = 460
PH_PERF_SEL_SC3_PA6_EVENT_WE = 461
PH_PERF_SEL_SC3_PA6_FPOV_WE = 462
PH_PERF_SEL_SC3_PA6_FPOP_WE = 463
PH_PERF_SEL_SC3_PA6_EOP_WE = 464
PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 465
PH_PERF_SEL_SC3_PA6_EOPG_WE = 466
PH_PERF_SEL_SC3_PA6_DEALLOC_WE = 467
PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 468
PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 469
PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 470
PH_PERF_SEL_SC3_PA7_FIFO_FULL = 471
PH_PERF_SEL_SC3_PA7_NULL_WE = 472
PH_PERF_SEL_SC3_PA7_EVENT_WE = 473
PH_PERF_SEL_SC3_PA7_FPOV_WE = 474
PH_PERF_SEL_SC3_PA7_FPOP_WE = 475
PH_PERF_SEL_SC3_PA7_EOP_WE = 476
PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 477
PH_PERF_SEL_SC3_PA7_EOPG_WE = 478
PH_PERF_SEL_SC3_PA7_DEALLOC_WE = 479
PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 480
PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 481
PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 482
PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 483
PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 484
PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 485
PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 486
PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 487
PH_PERF_SEL_SC4_ARB_BUSY = 488
PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 489
PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 490
PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 491
PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 492
PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 493
PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 494
PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 495
PH_PERF_SEL_SC4_SEND = 496
PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 497
PH_PERF_SEL_SC4_CREDIT_AT_MAX = 498
PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 499
PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 500
PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 501
PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 502
PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 503
PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 504
PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 505
PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 506
PH_PERF_SEL_SC4_PA0_FIFO_FULL = 507
PH_PERF_SEL_SC4_PA0_NULL_WE = 508
PH_PERF_SEL_SC4_PA0_EVENT_WE = 509
PH_PERF_SEL_SC4_PA0_FPOV_WE = 510
PH_PERF_SEL_SC4_PA0_FPOP_WE = 511
PH_PERF_SEL_SC4_PA0_EOP_WE = 512
PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 513
PH_PERF_SEL_SC4_PA0_EOPG_WE = 514
PH_PERF_SEL_SC4_PA0_DEALLOC_WE = 515
PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 516
PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 517
PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 518
PH_PERF_SEL_SC4_PA1_FIFO_FULL = 519
PH_PERF_SEL_SC4_PA1_NULL_WE = 520
PH_PERF_SEL_SC4_PA1_EVENT_WE = 521
PH_PERF_SEL_SC4_PA1_FPOV_WE = 522
PH_PERF_SEL_SC4_PA1_FPOP_WE = 523
PH_PERF_SEL_SC4_PA1_EOP_WE = 524
PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 525
PH_PERF_SEL_SC4_PA1_EOPG_WE = 526
PH_PERF_SEL_SC4_PA1_DEALLOC_WE = 527
PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 528
PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 529
PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 530
PH_PERF_SEL_SC4_PA2_FIFO_FULL = 531
PH_PERF_SEL_SC4_PA2_NULL_WE = 532
PH_PERF_SEL_SC4_PA2_EVENT_WE = 533
PH_PERF_SEL_SC4_PA2_FPOV_WE = 534
PH_PERF_SEL_SC4_PA2_FPOP_WE = 535
PH_PERF_SEL_SC4_PA2_EOP_WE = 536
PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 537
PH_PERF_SEL_SC4_PA2_EOPG_WE = 538
PH_PERF_SEL_SC4_PA2_DEALLOC_WE = 539
PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 540
PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 541
PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 542
PH_PERF_SEL_SC4_PA3_FIFO_FULL = 543
PH_PERF_SEL_SC4_PA3_NULL_WE = 544
PH_PERF_SEL_SC4_PA3_EVENT_WE = 545
PH_PERF_SEL_SC4_PA3_FPOV_WE = 546
PH_PERF_SEL_SC4_PA3_FPOP_WE = 547
PH_PERF_SEL_SC4_PA3_EOP_WE = 548
PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 549
PH_PERF_SEL_SC4_PA3_EOPG_WE = 550
PH_PERF_SEL_SC4_PA3_DEALLOC_WE = 551
PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 552
PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 553
PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 554
PH_PERF_SEL_SC4_PA4_FIFO_FULL = 555
PH_PERF_SEL_SC4_PA4_NULL_WE = 556
PH_PERF_SEL_SC4_PA4_EVENT_WE = 557
PH_PERF_SEL_SC4_PA4_FPOV_WE = 558
PH_PERF_SEL_SC4_PA4_FPOP_WE = 559
PH_PERF_SEL_SC4_PA4_EOP_WE = 560
PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 561
PH_PERF_SEL_SC4_PA4_EOPG_WE = 562
PH_PERF_SEL_SC4_PA4_DEALLOC_WE = 563
PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 564
PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 565
PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 566
PH_PERF_SEL_SC4_PA5_FIFO_FULL = 567
PH_PERF_SEL_SC4_PA5_NULL_WE = 568
PH_PERF_SEL_SC4_PA5_EVENT_WE = 569
PH_PERF_SEL_SC4_PA5_FPOV_WE = 570
PH_PERF_SEL_SC4_PA5_FPOP_WE = 571
PH_PERF_SEL_SC4_PA5_EOP_WE = 572
PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 573
PH_PERF_SEL_SC4_PA5_EOPG_WE = 574
PH_PERF_SEL_SC4_PA5_DEALLOC_WE = 575
PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 576
PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 577
PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 578
PH_PERF_SEL_SC4_PA6_FIFO_FULL = 579
PH_PERF_SEL_SC4_PA6_NULL_WE = 580
PH_PERF_SEL_SC4_PA6_EVENT_WE = 581
PH_PERF_SEL_SC4_PA6_FPOV_WE = 582
PH_PERF_SEL_SC4_PA6_FPOP_WE = 583
PH_PERF_SEL_SC4_PA6_EOP_WE = 584
PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 585
PH_PERF_SEL_SC4_PA6_EOPG_WE = 586
PH_PERF_SEL_SC4_PA6_DEALLOC_WE = 587
PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 588
PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 589
PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 590
PH_PERF_SEL_SC4_PA7_FIFO_FULL = 591
PH_PERF_SEL_SC4_PA7_NULL_WE = 592
PH_PERF_SEL_SC4_PA7_EVENT_WE = 593
PH_PERF_SEL_SC4_PA7_FPOV_WE = 594
PH_PERF_SEL_SC4_PA7_FPOP_WE = 595
PH_PERF_SEL_SC4_PA7_EOP_WE = 596
PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 597
PH_PERF_SEL_SC4_PA7_EOPG_WE = 598
PH_PERF_SEL_SC4_PA7_DEALLOC_WE = 599
PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 600
PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 601
PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 602
PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 603
PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 604
PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 605
PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 606
PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 607
PH_PERF_SEL_SC5_ARB_BUSY = 608
PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 609
PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 610
PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 611
PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 612
PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 613
PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 614
PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 615
PH_PERF_SEL_SC5_SEND = 616
PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 617
PH_PERF_SEL_SC5_CREDIT_AT_MAX = 618
PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 619
PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 620
PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 621
PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 622
PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 623
PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 624
PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 625
PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 626
PH_PERF_SEL_SC5_PA0_FIFO_FULL = 627
PH_PERF_SEL_SC5_PA0_NULL_WE = 628
PH_PERF_SEL_SC5_PA0_EVENT_WE = 629
PH_PERF_SEL_SC5_PA0_FPOV_WE = 630
PH_PERF_SEL_SC5_PA0_FPOP_WE = 631
PH_PERF_SEL_SC5_PA0_EOP_WE = 632
PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 633
PH_PERF_SEL_SC5_PA0_EOPG_WE = 634
PH_PERF_SEL_SC5_PA0_DEALLOC_WE = 635
PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 636
PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 637
PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 638
PH_PERF_SEL_SC5_PA1_FIFO_FULL = 639
PH_PERF_SEL_SC5_PA1_NULL_WE = 640
PH_PERF_SEL_SC5_PA1_EVENT_WE = 641
PH_PERF_SEL_SC5_PA1_FPOV_WE = 642
PH_PERF_SEL_SC5_PA1_FPOP_WE = 643
PH_PERF_SEL_SC5_PA1_EOP_WE = 644
PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 645
PH_PERF_SEL_SC5_PA1_EOPG_WE = 646
PH_PERF_SEL_SC5_PA1_DEALLOC_WE = 647
PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 648
PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 649
PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 650
PH_PERF_SEL_SC5_PA2_FIFO_FULL = 651
PH_PERF_SEL_SC5_PA2_NULL_WE = 652
PH_PERF_SEL_SC5_PA2_EVENT_WE = 653
PH_PERF_SEL_SC5_PA2_FPOV_WE = 654
PH_PERF_SEL_SC5_PA2_FPOP_WE = 655
PH_PERF_SEL_SC5_PA2_EOP_WE = 656
PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 657
PH_PERF_SEL_SC5_PA2_EOPG_WE = 658
PH_PERF_SEL_SC5_PA2_DEALLOC_WE = 659
PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 660
PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 661
PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 662
PH_PERF_SEL_SC5_PA3_FIFO_FULL = 663
PH_PERF_SEL_SC5_PA3_NULL_WE = 664
PH_PERF_SEL_SC5_PA3_EVENT_WE = 665
PH_PERF_SEL_SC5_PA3_FPOV_WE = 666
PH_PERF_SEL_SC5_PA3_FPOP_WE = 667
PH_PERF_SEL_SC5_PA3_EOP_WE = 668
PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 669
PH_PERF_SEL_SC5_PA3_EOPG_WE = 670
PH_PERF_SEL_SC5_PA3_DEALLOC_WE = 671
PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 672
PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 673
PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 674
PH_PERF_SEL_SC5_PA4_FIFO_FULL = 675
PH_PERF_SEL_SC5_PA4_NULL_WE = 676
PH_PERF_SEL_SC5_PA4_EVENT_WE = 677
PH_PERF_SEL_SC5_PA4_FPOV_WE = 678
PH_PERF_SEL_SC5_PA4_FPOP_WE = 679
PH_PERF_SEL_SC5_PA4_EOP_WE = 680
PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 681
PH_PERF_SEL_SC5_PA4_EOPG_WE = 682
PH_PERF_SEL_SC5_PA4_DEALLOC_WE = 683
PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 684
PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 685
PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 686
PH_PERF_SEL_SC5_PA5_FIFO_FULL = 687
PH_PERF_SEL_SC5_PA5_NULL_WE = 688
PH_PERF_SEL_SC5_PA5_EVENT_WE = 689
PH_PERF_SEL_SC5_PA5_FPOV_WE = 690
PH_PERF_SEL_SC5_PA5_FPOP_WE = 691
PH_PERF_SEL_SC5_PA5_EOP_WE = 692
PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 693
PH_PERF_SEL_SC5_PA5_EOPG_WE = 694
PH_PERF_SEL_SC5_PA5_DEALLOC_WE = 695
PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 696
PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 697
PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 698
PH_PERF_SEL_SC5_PA6_FIFO_FULL = 699
PH_PERF_SEL_SC5_PA6_NULL_WE = 700
PH_PERF_SEL_SC5_PA6_EVENT_WE = 701
PH_PERF_SEL_SC5_PA6_FPOV_WE = 702
PH_PERF_SEL_SC5_PA6_FPOP_WE = 703
PH_PERF_SEL_SC5_PA6_EOP_WE = 704
PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 705
PH_PERF_SEL_SC5_PA6_EOPG_WE = 706
PH_PERF_SEL_SC5_PA6_DEALLOC_WE = 707
PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 708
PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 709
PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 710
PH_PERF_SEL_SC5_PA7_FIFO_FULL = 711
PH_PERF_SEL_SC5_PA7_NULL_WE = 712
PH_PERF_SEL_SC5_PA7_EVENT_WE = 713
PH_PERF_SEL_SC5_PA7_FPOV_WE = 714
PH_PERF_SEL_SC5_PA7_FPOP_WE = 715
PH_PERF_SEL_SC5_PA7_EOP_WE = 716
PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 717
PH_PERF_SEL_SC5_PA7_EOPG_WE = 718
PH_PERF_SEL_SC5_PA7_DEALLOC_WE = 719
PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 720
PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 721
PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 722
PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 723
PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 724
PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 725
PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 726
PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 727
PH_PERF_SEL_SC6_ARB_BUSY = 728
PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 729
PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 730
PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 731
PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 732
PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 733
PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 734
PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 735
PH_PERF_SEL_SC6_SEND = 736
PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 737
PH_PERF_SEL_SC6_CREDIT_AT_MAX = 738
PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 739
PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 740
PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 741
PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 742
PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 743
PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 744
PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 745
PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 746
PH_PERF_SEL_SC6_PA0_FIFO_FULL = 747
PH_PERF_SEL_SC6_PA0_NULL_WE = 748
PH_PERF_SEL_SC6_PA0_EVENT_WE = 749
PH_PERF_SEL_SC6_PA0_FPOV_WE = 750
PH_PERF_SEL_SC6_PA0_FPOP_WE = 751
PH_PERF_SEL_SC6_PA0_EOP_WE = 752
PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 753
PH_PERF_SEL_SC6_PA0_EOPG_WE = 754
PH_PERF_SEL_SC6_PA0_DEALLOC_WE = 755
PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 756
PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 757
PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 758
PH_PERF_SEL_SC6_PA1_FIFO_FULL = 759
PH_PERF_SEL_SC6_PA1_NULL_WE = 760
PH_PERF_SEL_SC6_PA1_EVENT_WE = 761
PH_PERF_SEL_SC6_PA1_FPOV_WE = 762
PH_PERF_SEL_SC6_PA1_FPOP_WE = 763
PH_PERF_SEL_SC6_PA1_EOP_WE = 764
PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 765
PH_PERF_SEL_SC6_PA1_EOPG_WE = 766
PH_PERF_SEL_SC6_PA1_DEALLOC_WE = 767
PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 768
PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 769
PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 770
PH_PERF_SEL_SC6_PA2_FIFO_FULL = 771
PH_PERF_SEL_SC6_PA2_NULL_WE = 772
PH_PERF_SEL_SC6_PA2_EVENT_WE = 773
PH_PERF_SEL_SC6_PA2_FPOV_WE = 774
PH_PERF_SEL_SC6_PA2_FPOP_WE = 775
PH_PERF_SEL_SC6_PA2_EOP_WE = 776
PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 777
PH_PERF_SEL_SC6_PA2_EOPG_WE = 778
PH_PERF_SEL_SC6_PA2_DEALLOC_WE = 779
PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 780
PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 781
PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 782
PH_PERF_SEL_SC6_PA3_FIFO_FULL = 783
PH_PERF_SEL_SC6_PA3_NULL_WE = 784
PH_PERF_SEL_SC6_PA3_EVENT_WE = 785
PH_PERF_SEL_SC6_PA3_FPOV_WE = 786
PH_PERF_SEL_SC6_PA3_FPOP_WE = 787
PH_PERF_SEL_SC6_PA3_EOP_WE = 788
PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 789
PH_PERF_SEL_SC6_PA3_EOPG_WE = 790
PH_PERF_SEL_SC6_PA3_DEALLOC_WE = 791
PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 792
PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 793
PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 794
PH_PERF_SEL_SC6_PA4_FIFO_FULL = 795
PH_PERF_SEL_SC6_PA4_NULL_WE = 796
PH_PERF_SEL_SC6_PA4_EVENT_WE = 797
PH_PERF_SEL_SC6_PA4_FPOV_WE = 798
PH_PERF_SEL_SC6_PA4_FPOP_WE = 799
PH_PERF_SEL_SC6_PA4_EOP_WE = 800
PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 801
PH_PERF_SEL_SC6_PA4_EOPG_WE = 802
PH_PERF_SEL_SC6_PA4_DEALLOC_WE = 803
PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 804
PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 805
PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 806
PH_PERF_SEL_SC6_PA5_FIFO_FULL = 807
PH_PERF_SEL_SC6_PA5_NULL_WE = 808
PH_PERF_SEL_SC6_PA5_EVENT_WE = 809
PH_PERF_SEL_SC6_PA5_FPOV_WE = 810
PH_PERF_SEL_SC6_PA5_FPOP_WE = 811
PH_PERF_SEL_SC6_PA5_EOP_WE = 812
PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 813
PH_PERF_SEL_SC6_PA5_EOPG_WE = 814
PH_PERF_SEL_SC6_PA5_DEALLOC_WE = 815
PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 816
PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 817
PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 818
PH_PERF_SEL_SC6_PA6_FIFO_FULL = 819
PH_PERF_SEL_SC6_PA6_NULL_WE = 820
PH_PERF_SEL_SC6_PA6_EVENT_WE = 821
PH_PERF_SEL_SC6_PA6_FPOV_WE = 822
PH_PERF_SEL_SC6_PA6_FPOP_WE = 823
PH_PERF_SEL_SC6_PA6_EOP_WE = 824
PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 825
PH_PERF_SEL_SC6_PA6_EOPG_WE = 826
PH_PERF_SEL_SC6_PA6_DEALLOC_WE = 827
PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 828
PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 829
PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 830
PH_PERF_SEL_SC6_PA7_FIFO_FULL = 831
PH_PERF_SEL_SC6_PA7_NULL_WE = 832
PH_PERF_SEL_SC6_PA7_EVENT_WE = 833
PH_PERF_SEL_SC6_PA7_FPOV_WE = 834
PH_PERF_SEL_SC6_PA7_FPOP_WE = 835
PH_PERF_SEL_SC6_PA7_EOP_WE = 836
PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 837
PH_PERF_SEL_SC6_PA7_EOPG_WE = 838
PH_PERF_SEL_SC6_PA7_DEALLOC_WE = 839
PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 840
PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 841
PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 842
PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 843
PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 844
PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 845
PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 846
PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 847
PH_PERF_SEL_SC7_ARB_BUSY = 848
PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 849
PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 850
PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 851
PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 852
PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 853
PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 854
PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 855
PH_PERF_SEL_SC7_SEND = 856
PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 857
PH_PERF_SEL_SC7_CREDIT_AT_MAX = 858
PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 859
PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 860
PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 861
PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 862
PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 863
PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 864
PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 865
PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 866
PH_PERF_SEL_SC7_PA0_FIFO_FULL = 867
PH_PERF_SEL_SC7_PA0_NULL_WE = 868
PH_PERF_SEL_SC7_PA0_EVENT_WE = 869
PH_PERF_SEL_SC7_PA0_FPOV_WE = 870
PH_PERF_SEL_SC7_PA0_FPOP_WE = 871
PH_PERF_SEL_SC7_PA0_EOP_WE = 872
PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 873
PH_PERF_SEL_SC7_PA0_EOPG_WE = 874
PH_PERF_SEL_SC7_PA0_DEALLOC_WE = 875
PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 876
PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 877
PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 878
PH_PERF_SEL_SC7_PA1_FIFO_FULL = 879
PH_PERF_SEL_SC7_PA1_NULL_WE = 880
PH_PERF_SEL_SC7_PA1_EVENT_WE = 881
PH_PERF_SEL_SC7_PA1_FPOV_WE = 882
PH_PERF_SEL_SC7_PA1_FPOP_WE = 883
PH_PERF_SEL_SC7_PA1_EOP_WE = 884
PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 885
PH_PERF_SEL_SC7_PA1_EOPG_WE = 886
PH_PERF_SEL_SC7_PA1_DEALLOC_WE = 887
PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 888
PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 889
PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 890
PH_PERF_SEL_SC7_PA2_FIFO_FULL = 891
PH_PERF_SEL_SC7_PA2_NULL_WE = 892
PH_PERF_SEL_SC7_PA2_EVENT_WE = 893
PH_PERF_SEL_SC7_PA2_FPOV_WE = 894
PH_PERF_SEL_SC7_PA2_FPOP_WE = 895
PH_PERF_SEL_SC7_PA2_EOP_WE = 896
PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 897
PH_PERF_SEL_SC7_PA2_EOPG_WE = 898
PH_PERF_SEL_SC7_PA2_DEALLOC_WE = 899
PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 900
PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 901
PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 902
PH_PERF_SEL_SC7_PA3_FIFO_FULL = 903
PH_PERF_SEL_SC7_PA3_NULL_WE = 904
PH_PERF_SEL_SC7_PA3_EVENT_WE = 905
PH_PERF_SEL_SC7_PA3_FPOV_WE = 906
PH_PERF_SEL_SC7_PA3_FPOP_WE = 907
PH_PERF_SEL_SC7_PA3_EOP_WE = 908
PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 909
PH_PERF_SEL_SC7_PA3_EOPG_WE = 910
PH_PERF_SEL_SC7_PA3_DEALLOC_WE = 911
PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 912
PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 913
PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 914
PH_PERF_SEL_SC7_PA4_FIFO_FULL = 915
PH_PERF_SEL_SC7_PA4_NULL_WE = 916
PH_PERF_SEL_SC7_PA4_EVENT_WE = 917
PH_PERF_SEL_SC7_PA4_FPOV_WE = 918
PH_PERF_SEL_SC7_PA4_FPOP_WE = 919
PH_PERF_SEL_SC7_PA4_EOP_WE = 920
PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 921
PH_PERF_SEL_SC7_PA4_EOPG_WE = 922
PH_PERF_SEL_SC7_PA4_DEALLOC_WE = 923
PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 924
PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 925
PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 926
PH_PERF_SEL_SC7_PA5_FIFO_FULL = 927
PH_PERF_SEL_SC7_PA5_NULL_WE = 928
PH_PERF_SEL_SC7_PA5_EVENT_WE = 929
PH_PERF_SEL_SC7_PA5_FPOV_WE = 930
PH_PERF_SEL_SC7_PA5_FPOP_WE = 931
PH_PERF_SEL_SC7_PA5_EOP_WE = 932
PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 933
PH_PERF_SEL_SC7_PA5_EOPG_WE = 934
PH_PERF_SEL_SC7_PA5_DEALLOC_WE = 935
PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 936
PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 937
PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 938
PH_PERF_SEL_SC7_PA6_FIFO_FULL = 939
PH_PERF_SEL_SC7_PA6_NULL_WE = 940
PH_PERF_SEL_SC7_PA6_EVENT_WE = 941
PH_PERF_SEL_SC7_PA6_FPOV_WE = 942
PH_PERF_SEL_SC7_PA6_FPOP_WE = 943
PH_PERF_SEL_SC7_PA6_EOP_WE = 944
PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 945
PH_PERF_SEL_SC7_PA6_EOPG_WE = 946
PH_PERF_SEL_SC7_PA6_DEALLOC_WE = 947
PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 948
PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 949
PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 950
PH_PERF_SEL_SC7_PA7_FIFO_FULL = 951
PH_PERF_SEL_SC7_PA7_NULL_WE = 952
PH_PERF_SEL_SC7_PA7_EVENT_WE = 953
PH_PERF_SEL_SC7_PA7_FPOV_WE = 954
PH_PERF_SEL_SC7_PA7_FPOP_WE = 955
PH_PERF_SEL_SC7_PA7_EOP_WE = 956
PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 957
PH_PERF_SEL_SC7_PA7_EOPG_WE = 958
PH_PERF_SEL_SC7_PA7_DEALLOC_WE = 959
PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 960
PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 961
PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 962
PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 963
PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 964
PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 965
PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 966
PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 967
PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 968
PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 969
PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 970
PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 971
PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 972
PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 973
PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 974
PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 975
PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 976
PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 977
PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 978
PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 979
PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 980
PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 981
PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 982
PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 983
PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 984
PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 985
PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 986
PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 987
PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 988
PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 989
PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 990
PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 991
PH_PERF_SC0_FIFO_STATUS_0 = 992
PH_PERF_SC0_FIFO_STATUS_1 = 993
PH_PERF_SC0_FIFO_STATUS_2 = 994
PH_PERF_SC0_FIFO_STATUS_3 = 995
PH_PERF_SC1_FIFO_STATUS_0 = 996
PH_PERF_SC1_FIFO_STATUS_1 = 997
PH_PERF_SC1_FIFO_STATUS_2 = 998
PH_PERF_SC1_FIFO_STATUS_3 = 999
PH_PERF_SC2_FIFO_STATUS_0 = 1000
PH_PERF_SC2_FIFO_STATUS_1 = 1001
PH_PERF_SC2_FIFO_STATUS_2 = 1002
PH_PERF_SC2_FIFO_STATUS_3 = 1003
PH_PERF_SC3_FIFO_STATUS_0 = 1004
PH_PERF_SC3_FIFO_STATUS_1 = 1005
PH_PERF_SC3_FIFO_STATUS_2 = 1006
PH_PERF_SC3_FIFO_STATUS_3 = 1007
PH_PERF_SC4_FIFO_STATUS_0 = 1008
PH_PERF_SC4_FIFO_STATUS_1 = 1009
PH_PERF_SC4_FIFO_STATUS_2 = 1010
PH_PERF_SC4_FIFO_STATUS_3 = 1011
PH_PERF_SC5_FIFO_STATUS_0 = 1012
PH_PERF_SC5_FIFO_STATUS_1 = 1013
PH_PERF_SC5_FIFO_STATUS_2 = 1014
PH_PERF_SC5_FIFO_STATUS_3 = 1015
PH_PERF_SC6_FIFO_STATUS_0 = 1016
PH_PERF_SC6_FIFO_STATUS_1 = 1017
PH_PERF_SC6_FIFO_STATUS_2 = 1018
PH_PERF_SC6_FIFO_STATUS_3 = 1019
PH_PERF_SC7_FIFO_STATUS_0 = 1020
PH_PERF_SC7_FIFO_STATUS_1 = 1021
PH_PERF_SC7_FIFO_STATUS_2 = 1022
PH_PERF_SC7_FIFO_STATUS_3 = 1023
PH_PERFCNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PhSPIstatusMode'
PhSPIstatusMode__enumvalues = {
0: 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT',
1: 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT',
2: 'PH_SPI_MODE_DISABLED',
}
PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0
PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 1
PH_SPI_MODE_DISABLED = 2
PhSPIstatusMode = ctypes.c_uint32 # enum
# values for enumeration 'BinEventCntl'
BinEventCntl__enumvalues = {
0: 'BINNER_BREAK_BATCH',
1: 'BINNER_PIPELINE',
2: 'BINNER_DROP',
3: 'BINNER_PIPELINE_BREAK',
}
BINNER_BREAK_BATCH = 0
BINNER_PIPELINE = 1
BINNER_DROP = 2
BINNER_PIPELINE_BREAK = 3
BinEventCntl = ctypes.c_uint32 # enum
# values for enumeration 'BinMapMode'
BinMapMode__enumvalues = {
0: 'BIN_MAP_MODE_NONE',
1: 'BIN_MAP_MODE_RTA_INDEX',
2: 'BIN_MAP_MODE_POPS',
}
BIN_MAP_MODE_NONE = 0
BIN_MAP_MODE_RTA_INDEX = 1
BIN_MAP_MODE_POPS = 2
BinMapMode = ctypes.c_uint32 # enum
# values for enumeration 'BinSizeExtend'
BinSizeExtend__enumvalues = {
0: 'BIN_SIZE_32_PIXELS',
1: 'BIN_SIZE_64_PIXELS',
2: 'BIN_SIZE_128_PIXELS',
3: 'BIN_SIZE_256_PIXELS',
4: 'BIN_SIZE_512_PIXELS',
}
BIN_SIZE_32_PIXELS = 0
BIN_SIZE_64_PIXELS = 1
BIN_SIZE_128_PIXELS = 2
BIN_SIZE_256_PIXELS = 3
BIN_SIZE_512_PIXELS = 4
BinSizeExtend = ctypes.c_uint32 # enum
# values for enumeration 'BinningMode'
BinningMode__enumvalues = {
0: 'BINNING_ALLOWED',
1: 'FORCE_BINNING_ON',
2: 'BINNING_ONE_PRIM_PER_BATCH',
3: 'BINNING_DISABLED',
}
BINNING_ALLOWED = 0
FORCE_BINNING_ON = 1
BINNING_ONE_PRIM_PER_BATCH = 2
BINNING_DISABLED = 3
BinningMode = ctypes.c_uint32 # enum
# values for enumeration 'PkrMap'
PkrMap__enumvalues = {
0: 'RASTER_CONFIG_PKR_MAP_0',
1: 'RASTER_CONFIG_PKR_MAP_1',
2: 'RASTER_CONFIG_PKR_MAP_2',
3: 'RASTER_CONFIG_PKR_MAP_3',
}
RASTER_CONFIG_PKR_MAP_0 = 0
RASTER_CONFIG_PKR_MAP_1 = 1
RASTER_CONFIG_PKR_MAP_2 = 2
RASTER_CONFIG_PKR_MAP_3 = 3
PkrMap = ctypes.c_uint32 # enum
# values for enumeration 'PkrXsel'
PkrXsel__enumvalues = {
0: 'RASTER_CONFIG_PKR_XSEL_0',
1: 'RASTER_CONFIG_PKR_XSEL_1',
2: 'RASTER_CONFIG_PKR_XSEL_2',
3: 'RASTER_CONFIG_PKR_XSEL_3',
}
RASTER_CONFIG_PKR_XSEL_0 = 0
RASTER_CONFIG_PKR_XSEL_1 = 1
RASTER_CONFIG_PKR_XSEL_2 = 2
RASTER_CONFIG_PKR_XSEL_3 = 3
PkrXsel = ctypes.c_uint32 # enum
# values for enumeration 'PkrXsel2'
PkrXsel2__enumvalues = {
0: 'RASTER_CONFIG_PKR_XSEL2_0',
1: 'RASTER_CONFIG_PKR_XSEL2_1',
2: 'RASTER_CONFIG_PKR_XSEL2_2',
3: 'RASTER_CONFIG_PKR_XSEL2_3',
}
RASTER_CONFIG_PKR_XSEL2_0 = 0
RASTER_CONFIG_PKR_XSEL2_1 = 1
RASTER_CONFIG_PKR_XSEL2_2 = 2
RASTER_CONFIG_PKR_XSEL2_3 = 3
PkrXsel2 = ctypes.c_uint32 # enum
# values for enumeration 'PkrYsel'
PkrYsel__enumvalues = {
0: 'RASTER_CONFIG_PKR_YSEL_0',
1: 'RASTER_CONFIG_PKR_YSEL_1',
2: 'RASTER_CONFIG_PKR_YSEL_2',
3: 'RASTER_CONFIG_PKR_YSEL_3',
}
RASTER_CONFIG_PKR_YSEL_0 = 0
RASTER_CONFIG_PKR_YSEL_1 = 1
RASTER_CONFIG_PKR_YSEL_2 = 2
RASTER_CONFIG_PKR_YSEL_3 = 3
PkrYsel = ctypes.c_uint32 # enum
# values for enumeration 'RbMap'
RbMap__enumvalues = {
0: 'RASTER_CONFIG_RB_MAP_0',
1: 'RASTER_CONFIG_RB_MAP_1',
2: 'RASTER_CONFIG_RB_MAP_2',
3: 'RASTER_CONFIG_RB_MAP_3',
}
RASTER_CONFIG_RB_MAP_0 = 0
RASTER_CONFIG_RB_MAP_1 = 1
RASTER_CONFIG_RB_MAP_2 = 2
RASTER_CONFIG_RB_MAP_3 = 3
RbMap = ctypes.c_uint32 # enum
# values for enumeration 'RbXsel'
RbXsel__enumvalues = {
0: 'RASTER_CONFIG_RB_XSEL_0',
1: 'RASTER_CONFIG_RB_XSEL_1',
}
RASTER_CONFIG_RB_XSEL_0 = 0
RASTER_CONFIG_RB_XSEL_1 = 1
RbXsel = ctypes.c_uint32 # enum
# values for enumeration 'RbXsel2'
RbXsel2__enumvalues = {
0: 'RASTER_CONFIG_RB_XSEL2_0',
1: 'RASTER_CONFIG_RB_XSEL2_1',
2: 'RASTER_CONFIG_RB_XSEL2_2',
3: 'RASTER_CONFIG_RB_XSEL2_3',
}
RASTER_CONFIG_RB_XSEL2_0 = 0
RASTER_CONFIG_RB_XSEL2_1 = 1
RASTER_CONFIG_RB_XSEL2_2 = 2
RASTER_CONFIG_RB_XSEL2_3 = 3
RbXsel2 = ctypes.c_uint32 # enum
# values for enumeration 'RbYsel'
RbYsel__enumvalues = {
0: 'RASTER_CONFIG_RB_YSEL_0',
1: 'RASTER_CONFIG_RB_YSEL_1',
}
RASTER_CONFIG_RB_YSEL_0 = 0
RASTER_CONFIG_RB_YSEL_1 = 1
RbYsel = ctypes.c_uint32 # enum
# values for enumeration 'SC_PERFCNT_SEL'
SC_PERFCNT_SEL__enumvalues = {
0: 'SC_SRPS_WINDOW_VALID',
1: 'SC_PSSW_WINDOW_VALID',
2: 'SC_TPQZ_WINDOW_VALID',
3: 'SC_QZQP_WINDOW_VALID',
4: 'SC_TRPK_WINDOW_VALID',
5: 'SC_SRPS_WINDOW_VALID_BUSY',
6: 'SC_PSSW_WINDOW_VALID_BUSY',
7: 'SC_TPQZ_WINDOW_VALID_BUSY',
8: 'SC_QZQP_WINDOW_VALID_BUSY',
9: 'SC_TRPK_WINDOW_VALID_BUSY',
10: 'SC_STARVED_BY_PA',
11: 'SC_STALLED_BY_PRIMFIFO',
12: 'SC_STALLED_BY_DB_TILE',
13: 'SC_STARVED_BY_DB_TILE',
14: 'SC_STALLED_BY_TILEORDERFIFO',
15: 'SC_STALLED_BY_TILEFIFO',
16: 'SC_STALLED_BY_DB_QUAD',
17: 'SC_STARVED_BY_DB_QUAD',
18: 'SC_STALLED_BY_QUADFIFO',
19: 'SC_STALLED_BY_BCI',
20: 'SC_STALLED_BY_SPI',
21: 'SC_SCISSOR_DISCARD',
22: 'SC_BB_DISCARD',
23: 'SC_SUPERTILE_COUNT',
24: 'SC_SUPERTILE_PER_PRIM_H0',
25: 'SC_SUPERTILE_PER_PRIM_H1',
26: 'SC_SUPERTILE_PER_PRIM_H2',
27: 'SC_SUPERTILE_PER_PRIM_H3',
28: 'SC_SUPERTILE_PER_PRIM_H4',
29: 'SC_SUPERTILE_PER_PRIM_H5',
30: 'SC_SUPERTILE_PER_PRIM_H6',
31: 'SC_SUPERTILE_PER_PRIM_H7',
32: 'SC_SUPERTILE_PER_PRIM_H8',
33: 'SC_SUPERTILE_PER_PRIM_H9',
34: 'SC_SUPERTILE_PER_PRIM_H10',
35: 'SC_SUPERTILE_PER_PRIM_H11',
36: 'SC_SUPERTILE_PER_PRIM_H12',
37: 'SC_SUPERTILE_PER_PRIM_H13',
38: 'SC_SUPERTILE_PER_PRIM_H14',
39: 'SC_SUPERTILE_PER_PRIM_H15',
40: 'SC_SUPERTILE_PER_PRIM_H16',
41: 'SC_TILE_PER_PRIM_H0',
42: 'SC_TILE_PER_PRIM_H1',
43: 'SC_TILE_PER_PRIM_H2',
44: 'SC_TILE_PER_PRIM_H3',
45: 'SC_TILE_PER_PRIM_H4',
46: 'SC_TILE_PER_PRIM_H5',
47: 'SC_TILE_PER_PRIM_H6',
48: 'SC_TILE_PER_PRIM_H7',
49: 'SC_TILE_PER_PRIM_H8',
50: 'SC_TILE_PER_PRIM_H9',
51: 'SC_TILE_PER_PRIM_H10',
52: 'SC_TILE_PER_PRIM_H11',
53: 'SC_TILE_PER_PRIM_H12',
54: 'SC_TILE_PER_PRIM_H13',
55: 'SC_TILE_PER_PRIM_H14',
56: 'SC_TILE_PER_PRIM_H15',
57: 'SC_TILE_PER_PRIM_H16',
58: 'SC_TILE_PER_SUPERTILE_H0',
59: 'SC_TILE_PER_SUPERTILE_H1',
60: 'SC_TILE_PER_SUPERTILE_H2',
61: 'SC_TILE_PER_SUPERTILE_H3',
62: 'SC_TILE_PER_SUPERTILE_H4',
63: 'SC_TILE_PER_SUPERTILE_H5',
64: 'SC_TILE_PER_SUPERTILE_H6',
65: 'SC_TILE_PER_SUPERTILE_H7',
66: 'SC_TILE_PER_SUPERTILE_H8',
67: 'SC_TILE_PER_SUPERTILE_H9',
68: 'SC_TILE_PER_SUPERTILE_H10',
69: 'SC_TILE_PER_SUPERTILE_H11',
70: 'SC_TILE_PER_SUPERTILE_H12',
71: 'SC_TILE_PER_SUPERTILE_H13',
72: 'SC_TILE_PER_SUPERTILE_H14',
73: 'SC_TILE_PER_SUPERTILE_H15',
74: 'SC_TILE_PER_SUPERTILE_H16',
75: 'SC_TILE_PICKED_H1',
76: 'SC_PERF_SEL_RESERVED_76',
77: 'SC_PERF_SEL_RESERVED_77',
78: 'SC_PERF_SEL_RESERVED_78',
79: 'SC_QZ0_TILE_COUNT',
80: 'SC_PERF_SEL_RESERVED_80',
81: 'SC_PERF_SEL_RESERVED_81',
82: 'SC_PERF_SEL_RESERVED_82',
83: 'SC_QZ0_TILE_COVERED_COUNT',
84: 'SC_PERF_SEL_RESERVED_84',
85: 'SC_PERF_SEL_RESERVED_85',
86: 'SC_PERF_SEL_RESERVED_86',
87: 'SC_QZ0_TILE_NOT_COVERED_COUNT',
88: 'SC_PERF_SEL_RESERVED_88',
89: 'SC_PERF_SEL_RESERVED_89',
90: 'SC_PERF_SEL_RESERVED_90',
91: 'SC_QZ0_QUAD_PER_TILE_H0',
92: 'SC_QZ0_QUAD_PER_TILE_H1',
93: 'SC_QZ0_QUAD_PER_TILE_H2',
94: 'SC_QZ0_QUAD_PER_TILE_H3',
95: 'SC_QZ0_QUAD_PER_TILE_H4',
96: 'SC_QZ0_QUAD_PER_TILE_H5',
97: 'SC_QZ0_QUAD_PER_TILE_H6',
98: 'SC_QZ0_QUAD_PER_TILE_H7',
99: 'SC_QZ0_QUAD_PER_TILE_H8',
100: 'SC_QZ0_QUAD_PER_TILE_H9',
101: 'SC_QZ0_QUAD_PER_TILE_H10',
102: 'SC_QZ0_QUAD_PER_TILE_H11',
103: 'SC_QZ0_QUAD_PER_TILE_H12',
104: 'SC_QZ0_QUAD_PER_TILE_H13',
105: 'SC_QZ0_QUAD_PER_TILE_H14',
106: 'SC_QZ0_QUAD_PER_TILE_H15',
107: 'SC_QZ0_QUAD_PER_TILE_H16',
108: 'SC_PERF_SEL_RESERVED_108',
109: 'SC_PERF_SEL_RESERVED_109',
110: 'SC_PERF_SEL_RESERVED_110',
111: 'SC_PERF_SEL_RESERVED_111',
112: 'SC_PERF_SEL_RESERVED_112',
113: 'SC_PERF_SEL_RESERVED_113',
114: 'SC_PERF_SEL_RESERVED_114',
115: 'SC_PERF_SEL_RESERVED_115',
116: 'SC_PERF_SEL_RESERVED_116',
117: 'SC_PERF_SEL_RESERVED_117',
118: 'SC_PERF_SEL_RESERVED_118',
119: 'SC_PERF_SEL_RESERVED_119',
120: 'SC_PERF_SEL_RESERVED_120',
121: 'SC_PERF_SEL_RESERVED_121',
122: 'SC_PERF_SEL_RESERVED_122',
123: 'SC_PERF_SEL_RESERVED_123',
124: 'SC_PERF_SEL_RESERVED_124',
125: 'SC_PERF_SEL_RESERVED_125',
126: 'SC_PERF_SEL_RESERVED_126',
127: 'SC_PERF_SEL_RESERVED_127',
128: 'SC_PERF_SEL_RESERVED_128',
129: 'SC_PERF_SEL_RESERVED_129',
130: 'SC_PERF_SEL_RESERVED_130',
131: 'SC_PERF_SEL_RESERVED_131',
132: 'SC_PERF_SEL_RESERVED_132',
133: 'SC_PERF_SEL_RESERVED_133',
134: 'SC_PERF_SEL_RESERVED_134',
135: 'SC_PERF_SEL_RESERVED_135',
136: 'SC_PERF_SEL_RESERVED_136',
137: 'SC_PERF_SEL_RESERVED_137',
138: 'SC_PERF_SEL_RESERVED_138',
139: 'SC_PERF_SEL_RESERVED_139',
140: 'SC_PERF_SEL_RESERVED_140',
141: 'SC_PERF_SEL_RESERVED_141',
142: 'SC_PERF_SEL_RESERVED_142',
143: 'SC_PERF_SEL_RESERVED_143',
144: 'SC_PERF_SEL_RESERVED_144',
145: 'SC_PERF_SEL_RESERVED_145',
146: 'SC_PERF_SEL_RESERVED_146',
147: 'SC_PERF_SEL_RESERVED_147',
148: 'SC_PERF_SEL_RESERVED_148',
149: 'SC_PERF_SEL_RESERVED_149',
150: 'SC_PERF_SEL_RESERVED_150',
151: 'SC_PERF_SEL_RESERVED_151',
152: 'SC_PERF_SEL_RESERVED_152',
153: 'SC_PERF_SEL_RESERVED_153',
154: 'SC_PERF_SEL_RESERVED_154',
155: 'SC_PERF_SEL_RESERVED_155',
156: 'SC_PERF_SEL_RESERVED_156',
157: 'SC_PERF_SEL_RESERVED_157',
158: 'SC_PERF_SEL_RESERVED_158',
159: 'SC_QZ0_QUAD_COUNT',
160: 'SC_PERF_SEL_RESERVED_160',
161: 'SC_PERF_SEL_RESERVED_161',
162: 'SC_PERF_SEL_RESERVED_162',
163: 'SC_P0_HIZ_TILE_COUNT',
164: 'SC_PERF_SEL_RESERVED_164',
165: 'SC_PERF_SEL_RESERVED_165',
166: 'SC_PERF_SEL_RESERVED_166',
167: 'SC_P0_HIZ_QUAD_PER_TILE_H0',
168: 'SC_P0_HIZ_QUAD_PER_TILE_H1',
169: 'SC_P0_HIZ_QUAD_PER_TILE_H2',
170: 'SC_P0_HIZ_QUAD_PER_TILE_H3',
171: 'SC_P0_HIZ_QUAD_PER_TILE_H4',
172: 'SC_P0_HIZ_QUAD_PER_TILE_H5',
173: 'SC_P0_HIZ_QUAD_PER_TILE_H6',
174: 'SC_P0_HIZ_QUAD_PER_TILE_H7',
175: 'SC_P0_HIZ_QUAD_PER_TILE_H8',
176: 'SC_P0_HIZ_QUAD_PER_TILE_H9',
177: 'SC_P0_HIZ_QUAD_PER_TILE_H10',
178: 'SC_P0_HIZ_QUAD_PER_TILE_H11',
179: 'SC_P0_HIZ_QUAD_PER_TILE_H12',
180: 'SC_P0_HIZ_QUAD_PER_TILE_H13',
181: 'SC_P0_HIZ_QUAD_PER_TILE_H14',
182: 'SC_P0_HIZ_QUAD_PER_TILE_H15',
183: 'SC_P0_HIZ_QUAD_PER_TILE_H16',
184: 'SC_PERF_SEL_RESERVED_184',
185: 'SC_PERF_SEL_RESERVED_185',
186: 'SC_PERF_SEL_RESERVED_186',
187: 'SC_PERF_SEL_RESERVED_187',
188: 'SC_PERF_SEL_RESERVED_188',
189: 'SC_PERF_SEL_RESERVED_189',
190: 'SC_PERF_SEL_RESERVED_190',
191: 'SC_PERF_SEL_RESERVED_191',
192: 'SC_PERF_SEL_RESERVED_192',
193: 'SC_PERF_SEL_RESERVED_193',
194: 'SC_PERF_SEL_RESERVED_194',
195: 'SC_PERF_SEL_RESERVED_195',
196: 'SC_PERF_SEL_RESERVED_196',
197: 'SC_PERF_SEL_RESERVED_197',
198: 'SC_PERF_SEL_RESERVED_198',
199: 'SC_PERF_SEL_RESERVED_199',
200: 'SC_PERF_SEL_RESERVED_200',
201: 'SC_PERF_SEL_RESERVED_201',
202: 'SC_PERF_SEL_RESERVED_202',
203: 'SC_PERF_SEL_RESERVED_203',
204: 'SC_PERF_SEL_RESERVED_204',
205: 'SC_PERF_SEL_RESERVED_205',
206: 'SC_PERF_SEL_RESERVED_206',
207: 'SC_PERF_SEL_RESERVED_207',
208: 'SC_PERF_SEL_RESERVED_208',
209: 'SC_PERF_SEL_RESERVED_209',
210: 'SC_PERF_SEL_RESERVED_210',
211: 'SC_PERF_SEL_RESERVED_211',
212: 'SC_PERF_SEL_RESERVED_212',
213: 'SC_PERF_SEL_RESERVED_213',
214: 'SC_PERF_SEL_RESERVED_214',
215: 'SC_PERF_SEL_RESERVED_215',
216: 'SC_PERF_SEL_RESERVED_216',
217: 'SC_PERF_SEL_RESERVED_217',
218: 'SC_PERF_SEL_RESERVED_218',
219: 'SC_PERF_SEL_RESERVED_219',
220: 'SC_PERF_SEL_RESERVED_220',
221: 'SC_PERF_SEL_RESERVED_221',
222: 'SC_PERF_SEL_RESERVED_222',
223: 'SC_PERF_SEL_RESERVED_223',
224: 'SC_PERF_SEL_RESERVED_224',
225: 'SC_PERF_SEL_RESERVED_225',
226: 'SC_PERF_SEL_RESERVED_226',
227: 'SC_PERF_SEL_RESERVED_227',
228: 'SC_PERF_SEL_RESERVED_228',
229: 'SC_PERF_SEL_RESERVED_229',
230: 'SC_PERF_SEL_RESERVED_230',
231: 'SC_PERF_SEL_RESERVED_231',
232: 'SC_PERF_SEL_RESERVED_232',
233: 'SC_PERF_SEL_RESERVED_233',
234: 'SC_PERF_SEL_RESERVED_234',
235: 'SC_P0_HIZ_QUAD_COUNT',
236: 'SC_PERF_SEL_RESERVED_236',
237: 'SC_PERF_SEL_RESERVED_237',
238: 'SC_PERF_SEL_RESERVED_238',
239: 'SC_P0_DETAIL_QUAD_COUNT',
240: 'SC_PERF_SEL_RESERVED_240',
241: 'SC_PERF_SEL_RESERVED_241',
242: 'SC_PERF_SEL_RESERVED_242',
243: 'SC_P0_DETAIL_QUAD_WITH_1_PIX',
244: 'SC_P0_DETAIL_QUAD_WITH_2_PIX',
245: 'SC_P0_DETAIL_QUAD_WITH_3_PIX',
246: 'SC_P0_DETAIL_QUAD_WITH_4_PIX',
247: 'SC_PERF_SEL_RESERVED_247',
248: 'SC_PERF_SEL_RESERVED_248',
249: 'SC_PERF_SEL_RESERVED_249',
250: 'SC_PERF_SEL_RESERVED_250',
251: 'SC_PERF_SEL_RESERVED_251',
252: 'SC_PERF_SEL_RESERVED_252',
253: 'SC_PERF_SEL_RESERVED_253',
254: 'SC_PERF_SEL_RESERVED_254',
255: 'SC_PERF_SEL_RESERVED_255',
256: 'SC_PERF_SEL_RESERVED_256',
257: 'SC_PERF_SEL_RESERVED_257',
258: 'SC_PERF_SEL_RESERVED_258',
259: 'SC_EARLYZ_QUAD_COUNT',
260: 'SC_EARLYZ_QUAD_WITH_1_PIX',
261: 'SC_EARLYZ_QUAD_WITH_2_PIX',
262: 'SC_EARLYZ_QUAD_WITH_3_PIX',
263: 'SC_EARLYZ_QUAD_WITH_4_PIX',
264: 'SC_PKR_QUAD_PER_ROW_H1',
265: 'SC_PKR_QUAD_PER_ROW_H2',
266: 'SC_PKR_4X2_QUAD_SPLIT',
267: 'SC_PKR_4X2_FILL_QUAD',
268: 'SC_PKR_END_OF_VECTOR',
269: 'SC_PKR_CONTROL_XFER',
270: 'SC_PKR_DBHANG_FORCE_EOV',
271: 'SC_REG_SCLK_BUSY',
272: 'SC_GRP0_DYN_SCLK_BUSY',
273: 'SC_GRP1_DYN_SCLK_BUSY',
274: 'SC_GRP2_DYN_SCLK_BUSY',
275: 'SC_GRP3_DYN_SCLK_BUSY',
276: 'SC_GRP4_DYN_SCLK_BUSY',
277: 'SC_PA0_SC_DATA_FIFO_RD',
278: 'SC_PA0_SC_DATA_FIFO_WE',
279: 'SC_PERF_SEL_RESERVED_279',
280: 'SC_PERF_SEL_RESERVED_280',
281: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
282: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES',
283: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
284: 'SC_PS_ARB_STALLED_FROM_BELOW',
285: 'SC_PS_ARB_STARVED_FROM_ABOVE',
286: 'SC_PS_ARB_SC_BUSY',
287: 'SC_PS_ARB_PA_SC_BUSY',
288: 'SC_PERF_SEL_RESERVED_288',
289: 'SC_PERF_SEL_RESERVED_289',
290: 'SC_PERF_SEL_RESERVED_290',
291: 'SC_PERF_SEL_RESERVED_291',
292: 'SC_PA_SC_DEALLOC_2_0_WE',
293: 'SC_PERF_SEL_RESERVED_293',
294: 'SC_PERF_SEL_RESERVED_294',
295: 'SC_PERF_SEL_RESERVED_295',
296: 'SC_PERF_SEL_RESERVED_296',
297: 'SC_PERF_SEL_RESERVED_297',
298: 'SC_PERF_SEL_RESERVED_298',
299: 'SC_PERF_SEL_RESERVED_299',
300: 'SC_PA0_SC_EOP_WE',
301: 'SC_PERF_SEL_RESERVED_301',
302: 'SC_PA0_SC_EVENT_WE',
303: 'SC_PERF_SEL_RESERVED_303',
304: 'SC_PERF_SEL_RESERVED_304',
305: 'SC_PERF_SEL_RESERVED_305',
306: 'SC_PERF_SEL_RESERVED_306',
307: 'SC_PERF_SEL_RESERVED_307',
308: 'SC_PERF_SEL_RESERVED_308',
309: 'SC_PERF_SEL_RESERVED_309',
310: 'SC_PERF_SEL_RESERVED_310',
311: 'SC_PERF_SEL_RESERVED_311',
312: 'SC_PERF_SEL_RESERVED_312',
313: 'SC_PERF_SEL_RESERVED_313',
314: 'SC_PERF_SEL_RESERVED_314',
315: 'SC_PERF_SEL_RESERVED_315',
316: 'SC_PERF_SEL_RESERVED_316',
317: 'SC_PERF_SEL_RESERVED_317',
318: 'SC_PA_SC_FPOV_WE',
319: 'SC_PERF_SEL_RESERVED_319',
320: 'SC_PERF_SEL_RESERVED_320',
321: 'SC_PERF_SEL_RESERVED_321',
322: 'SC_PERF_SEL_RESERVED_322',
323: 'SC_PERF_SEL_RESERVED_323',
324: 'SC_PERF_SEL_RESERVED_324',
325: 'SC_PERF_SEL_RESERVED_325',
326: 'SC_SPI_DEALLOC_4_0',
327: 'SC_SPI_DEALLOC_7_5',
328: 'SC_PERF_SEL_RESERVED_328',
329: 'SC_PERF_SEL_RESERVED_329',
330: 'SC_PERF_SEL_RESERVED_330',
331: 'SC_PERF_SEL_RESERVED_331',
332: 'SC_PERF_SEL_RESERVED_332',
333: 'SC_PERF_SEL_RESERVED_333',
334: 'SC_PERF_SEL_RESERVED_334',
335: 'SC_PERF_SEL_RESERVED_335',
336: 'SC_PERF_SEL_RESERVED_336',
337: 'SC_PERF_SEL_RESERVED_337',
338: 'SC_SPI_FPOV_4_0',
339: 'SC_SPI_FPOV_7_5',
340: 'SC_PERF_SEL_RESERVED_340',
341: 'SC_PERF_SEL_RESERVED_341',
342: 'SC_SPI_EVENT',
343: 'SC_PS_TS_EVENT_FIFO_PUSH',
344: 'SC_PS_TS_EVENT_FIFO_POP',
345: 'SC_PS_CTX_DONE_FIFO_PUSH',
346: 'SC_PS_CTX_DONE_FIFO_POP',
347: 'SC_PERF_SEL_RESERVED_347',
348: 'SC_PERF_SEL_RESERVED_348',
349: 'SC_PA0_SC_NULL_WE',
350: 'SC_PA0_SC_NULL_DEALLOC_WE',
351: 'SC_PERF_SEL_RESERVED_351',
352: 'SC_PA0_SC_DATA_FIFO_EOP_RD',
353: 'SC_PA0_SC_DEALLOC_2_0_RD',
354: 'SC_PERF_SEL_RESERVED_354',
355: 'SC_PERF_SEL_RESERVED_355',
356: 'SC_PERF_SEL_RESERVED_356',
357: 'SC_PERF_SEL_RESERVED_357',
358: 'SC_PERF_SEL_RESERVED_358',
359: 'SC_PERF_SEL_RESERVED_359',
360: 'SC_PERF_SEL_RESERVED_360',
361: 'SC_PERF_SEL_RESERVED_361',
362: 'SC_PERF_SEL_RESERVED_362',
363: 'SC_PERF_SEL_RESERVED_363',
364: 'SC_PERF_SEL_RESERVED_364',
365: 'SC_PERF_SEL_RESERVED_365',
366: 'SC_PERF_SEL_RESERVED_366',
367: 'SC_PERF_SEL_RESERVED_367',
368: 'SC_PERF_SEL_RESERVED_368',
369: 'SC_PERF_SEL_RESERVED_369',
370: 'SC_PERF_SEL_RESERVED_370',
371: 'SC_PERF_SEL_RESERVED_371',
372: 'SC_PERF_SEL_RESERVED_372',
373: 'SC_PS_PA0_SC_FIFO_EMPTY',
374: 'SC_PS_PA0_SC_FIFO_FULL',
375: 'SC_PERF_SEL_RESERVED_375',
376: 'SC_PERF_SEL_RESERVED_376',
377: 'SC_PERF_SEL_RESERVED_377',
378: 'SC_PERF_SEL_RESERVED_378',
379: 'SC_PERF_SEL_RESERVED_379',
380: 'SC_PERF_SEL_RESERVED_380',
381: 'SC_PERF_SEL_RESERVED_381',
382: 'SC_PERF_SEL_RESERVED_382',
383: 'SC_PERF_SEL_RESERVED_383',
384: 'SC_PERF_SEL_RESERVED_384',
385: 'SC_PERF_SEL_RESERVED_385',
386: 'SC_BUSY_CNT_NOT_ZERO',
387: 'SC_BM_BUSY',
388: 'SC_BACKEND_BUSY',
389: 'SC_SCF_SCB_INTERFACE_BUSY',
390: 'SC_SCB_BUSY',
391: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY',
392: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL',
393: 'SC_PBB_BIN_HIST_NUM_PRIMS',
394: 'SC_PBB_BATCH_HIST_NUM_PRIMS',
395: 'SC_PBB_BIN_HIST_NUM_CONTEXTS',
396: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS',
397: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES',
398: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES',
399: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS',
400: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS',
401: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM',
402: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW',
403: 'SC_PBB_BUSY',
404: 'SC_PBB_BUSY_AND_NO_SENDS',
405: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES',
406: 'SC_PBB_NUM_BINS',
407: 'SC_PBB_END_OF_BIN',
408: 'SC_PBB_END_OF_BATCH',
409: 'SC_PBB_PRIMBIN_PROCESSED',
410: 'SC_PBB_PRIM_ADDED_TO_BATCH',
411: 'SC_PBB_NONBINNED_PRIM',
412: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB',
413: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB',
414: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION',
415: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW',
416: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN',
417: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE',
418: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE',
419: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM',
420: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE',
421: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT',
422: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT',
423: 'SC_PERF_SEL_RESERVED_423',
424: 'SC_PERF_SEL_RESERVED_424',
425: 'SC_PERF_SEL_RESERVED_425',
426: 'SC_PERF_SEL_RESERVED_426',
427: 'SC_PERF_SEL_RESERVED_427',
428: 'SC_PERF_SEL_RESERVED_428',
429: 'SC_PERF_SEL_RESERVED_429',
430: 'SC_PERF_SEL_RESERVED_430',
431: 'SC_PERF_SEL_RESERVED_431',
432: 'SC_PERF_SEL_RESERVED_432',
433: 'SC_PERF_SEL_RESERVED_433',
434: 'SC_PERF_SEL_RESERVED_434',
435: 'SC_PERF_SEL_RESERVED_435',
436: 'SC_PERF_SEL_RESERVED_436',
437: 'SC_GRP5_DYN_SCLK_BUSY',
438: 'SC_GRP6_DYN_SCLK_BUSY',
439: 'SC_GRP7_DYN_SCLK_BUSY',
440: 'SC_GRP8_DYN_SCLK_BUSY',
441: 'SC_GRP9_DYN_SCLK_BUSY',
442: 'SC_PS_TO_BE_SCLK_GATE_STALL',
443: 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL',
444: 'SC_PK_BUSY',
445: 'SC_PK_MAX_DEALLOC_FORCE_EOV',
446: 'SC_PK_DEALLOC_WAVE_BREAK',
447: 'SC_SPI_SEND',
448: 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND',
449: 'SC_SPI_CREDIT_AT_MAX',
450: 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND',
451: 'SC_BCI_SEND',
452: 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND',
453: 'SC_BCI_CREDIT_AT_MAX',
454: 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND',
455: 'SC_SPIBC_FULL_FREEZE',
456: 'SC_PW_BM_PASS_EMPTY_PRIM',
457: 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM',
458: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0',
459: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1',
460: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2',
461: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3',
462: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4',
463: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5',
464: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6',
465: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7',
466: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8',
467: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9',
468: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10',
469: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11',
470: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12',
471: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13',
472: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14',
473: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15',
474: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16',
475: 'SC_DB0_TILE_INTERFACE_BUSY',
476: 'SC_DB0_TILE_INTERFACE_SEND',
477: 'SC_DB0_TILE_INTERFACE_SEND_EVENT',
478: 'SC_PERF_SEL_RESERVED_478',
479: 'SC_PERF_SEL_RESERVED_479',
480: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND',
481: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX',
482: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND',
483: 'SC_PERF_SEL_RESERVED_483',
484: 'SC_PERF_SEL_RESERVED_484',
485: 'SC_PERF_SEL_RESERVED_485',
486: 'SC_PERF_SEL_RESERVED_486',
487: 'SC_PERF_SEL_RESERVED_487',
488: 'SC_PERF_SEL_RESERVED_488',
489: 'SC_PERF_SEL_RESERVED_489',
490: 'SC_PERF_SEL_RESERVED_490',
491: 'SC_BACKEND_PRIM_FIFO_FULL',
492: 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER',
493: 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH',
494: 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH',
495: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT',
496: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT',
497: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV',
498: 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE',
499: 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE',
500: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT',
501: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET',
502: 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE',
503: 'SC_STALLED_BY_DB0_TILEFIFO',
504: 'SC_DB0_QUAD_INTF_SEND',
505: 'SC_DB0_QUAD_INTF_BUSY',
506: 'SC_DB0_QUAD_INTF_STALLED_BY_DB',
507: 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX',
508: 'SC_DB0_QUAD_INTF_IDLE',
509: 'SC_PERF_SEL_RESERVED_509',
510: 'SC_PERF_SEL_RESERVED_510',
511: 'SC_PERF_SEL_RESERVED_511',
512: 'SC_PERF_SEL_RESERVED_512',
513: 'SC_PERF_SEL_RESERVED_513',
514: 'SC_PERF_SEL_RESERVED_514',
515: 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION',
516: 'SC_PKR_WAVE_BREAK_FULL_TILE',
517: 'SC_RESERVED_60',
518: 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN',
519: 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT',
520: 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL',
521: 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL',
522: 'SC_DB0_TILE_MASK_FIFO_FULL',
523: 'SC_PERF_SEL_RESERVED_523',
524: 'SC_PERF_SEL_RESERVED_524',
525: 'SC_PERF_SEL_RESERVED_525',
526: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL',
527: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL',
528: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL',
529: 'SC_PS_PM_PFF_PW_FULL',
530: 'SC_PS_PM_ZFF_PW_FULL',
531: 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL',
532: 'SC_PERF_SEL_RESERVED_532',
533: 'SC_PERF_SEL_RESERVED_533',
534: 'SC_PERF_SEL_RESERVED_534',
535: 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H',
536: 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H',
537: 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H',
538: 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H',
539: 'SC_PERF_SEL_RESERVED_539',
540: 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H',
541: 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H',
542: 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H',
543: 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H',
544: 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H',
545: 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H',
546: 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H',
547: 'SC_PK_PM_OREO_CONFLICT_QUAD_FORCE_EOV_WAVE_BRK_1H',
548: 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H',
549: 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H',
550: 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H',
551: 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H',
552: 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD',
553: 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD',
554: 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD',
555: 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD',
556: 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD',
557: 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD',
558: 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD',
559: 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD',
560: 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD',
561: 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD',
562: 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD',
563: 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD',
564: 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD',
565: 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD',
566: 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD',
567: 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD',
568: 'SC_PERF_SEL_RESERVED_568',
569: 'SC_PBB_RESERVED',
570: 'SC_BM_BE0_STALLED',
571: 'SC_BM_BE1_STALLED',
572: 'SC_BM_BE2_STALLED',
573: 'SC_BM_BE3_STALLED',
574: 'SC_BM_MULTI_ACCUM_1_BE_STALLED',
575: 'SC_BM_MULTI_ACCUM_2_BE_STALLED',
576: 'SC_BM_MULTI_ACCUM_3_BE_STALLED',
577: 'SC_BM_MULTI_ACCUM_4_BE_STALLED',
578: 'SC_PBB_READ_PH0',
579: 'SC_PBB_READ_DEALLOC_4_0',
580: 'SC_PBB_READ_DEALLOC_7_5',
581: 'SC_PBB_READ_FPOG_4_0',
582: 'SC_PBB_READ_FPOG_7_5',
583: 'SC_VRC_SECTOR_HIT',
584: 'SC_VRC_TAG_MISS',
585: 'SC_VRC_SECTOR_MISS',
586: 'SC_VRC_LRU_EVICT_STALL',
587: 'SC_VRC_LRU_EVICT_SCHEDULED_EVICT_STALL',
588: 'SC_VRC_LRU_EVICT_PENDING_EVICT_STALL',
589: 'SC_VRC_REEVICTION_STALL',
590: 'SC_VRC_EVICT_NONZERO_INFLIGHT_STALL',
591: 'SC_VRC_REPLACE_SCHEDULED_EVICT_STALL',
592: 'SC_VRC_REPLACE_PENDING_EVICT_STALL',
593: 'SC_VRC_REPLACE_FLUSH_IN_PROGRESS_STALL',
594: 'SC_VRC_INFLIGHT_COUNTER_MAXIMUM_STALL',
595: 'SC_VRC_READ_OUTPUT_STALL',
596: 'SC_VRC_WRITE_OUTPUT_STALL',
597: 'SC_VRC_ACK_OUTPUT_STALL',
598: 'SC_VRC_FLUSH_EVICT_STALL',
599: 'SC_VRC_FLUSH_REFLUSH_STALL',
600: 'SC_VRC_FLUSH_FIP_HIT_STALL',
601: 'SC_VRC_FLUSH_WRREQ_DRAIN_STALL',
602: 'SC_VRC_FLUSH_DONE_STALL',
603: 'SC_VRC_FLUSH_STALL',
604: 'SC_VRC_STALL',
605: 'SC_VRC_FLUSH',
606: 'SC_VRC_SECTORS_FLUSHED',
607: 'SC_VRC_DIRTY_SECTORS_FLUSHED',
608: 'SC_VRC_TAGS_FLUSHED',
609: 'SC_VRC_HPF_REQ',
610: 'SC_VRC_HPF_EVENT',
611: 'SC_VRC_HPF_STALLED',
612: 'SC_VRC_PROBE_ACK_TILES',
613: 'SC_VRC_GL1X_RD_REQ',
614: 'SC_VRC_GL1X_WR_REQ',
615: 'SC_VRC_GL1X_SRC_XFR',
616: 'SC_VRC_GL1X_RD_RET',
617: 'SC_VRC_GL1X_WR_ACK',
618: 'SC_VRC_GL1X_RD_XNACK',
619: 'SC_VRC_GL1X_WR_XNACK',
620: 'SC_VRC_GL1X_REQ_STALLED',
621: 'SC_VRC_GL1X_SRC_STALLED',
622: 'SC_VRC_RATEMEM_WE_CNT',
623: 'SC_VRC_RATEMEM_RE_CNT',
624: 'SC_VRC_HINTMEM_WE_CNT',
625: 'SC_VRC_HINTMEM_RE_CNT',
626: 'SC_VRC_BUSY',
627: 'SC_GL1X_BUSY',
628: 'SC_BE_VRS_RD_REQ',
629: 'SC_BE_VRS_RD_REQ_STALLED',
630: 'SC_BE_VRS_RD_REQ_HIT',
631: 'SC_BE_VRS_RD_RET',
632: 'SC_BE_VRS_RD_RET_STALLED',
633: 'SC_BE_VRS_FB_RET',
634: 'SC_BE_VRS_FB_RET_STALLED',
635: 'SC_BE_VRS_FB_RET_HIT',
636: 'SC_VRS_BE_BUSY',
637: 'SC_PWS_CS_EVENTS_PWS_ENABLE',
638: 'SC_PWS_PS_EVENTS_PWS_ENABLE',
639: 'SC_PWS_TS_EVENTS_PWS_ENABLE',
640: 'SC_PWS_STALLED',
641: 'SC_PWS_P0_CS_SYNC_COMPLETE',
642: 'SC_PWS_P0_PS_SYNC_COMPLETE',
643: 'SC_PWS_P0_TS_SYNC_COMPLETE',
644: 'SC_PWS_P1_CS_SYNC_COMPLETE',
645: 'SC_PWS_P1_PS_SYNC_COMPLETE',
646: 'SC_PWS_P1_TS_SYNC_COMPLETE',
647: 'SC_PKR_PC_NO_CREDITS',
648: 'SC_PKR_PC_STALLED',
649: 'SC_PKR_PC_SEND',
650: 'SC_PKR_PC_SEND_PRIM_VALID_1',
651: 'SC_PKR_PC_SEND_PRIM_VALID_0',
652: 'SC_PKR_PC_SEND_TRUE_PRIM',
653: 'SC_PKR_PC_SEND_EOV',
654: 'SC_PKR_PC_SEND_EVENT',
655: 'SC_PKR_DB_WAVE_STALL',
656: 'SC_PKR_PSINVOC_SEDC_FIFO_FULL',
657: 'SC_PKR_OREO_STALLED_BY_NO_VALID_WAIVE_ID',
658: 'SC_PKR_SPI_QUAD_COUNT',
659: 'SC_PKR_DB_OREO_WAVE_QUAD_COUNT',
660: 'SC_PKR_BCI_QUAD_NEW_PRIM',
661: 'SC_SPI_WAVE_STALLED_BY_SPI',
}
SC_SRPS_WINDOW_VALID = 0
SC_PSSW_WINDOW_VALID = 1
SC_TPQZ_WINDOW_VALID = 2
SC_QZQP_WINDOW_VALID = 3
SC_TRPK_WINDOW_VALID = 4
SC_SRPS_WINDOW_VALID_BUSY = 5
SC_PSSW_WINDOW_VALID_BUSY = 6
SC_TPQZ_WINDOW_VALID_BUSY = 7
SC_QZQP_WINDOW_VALID_BUSY = 8
SC_TRPK_WINDOW_VALID_BUSY = 9
SC_STARVED_BY_PA = 10
SC_STALLED_BY_PRIMFIFO = 11
SC_STALLED_BY_DB_TILE = 12
SC_STARVED_BY_DB_TILE = 13
SC_STALLED_BY_TILEORDERFIFO = 14
SC_STALLED_BY_TILEFIFO = 15
SC_STALLED_BY_DB_QUAD = 16
SC_STARVED_BY_DB_QUAD = 17
SC_STALLED_BY_QUADFIFO = 18
SC_STALLED_BY_BCI = 19
SC_STALLED_BY_SPI = 20
SC_SCISSOR_DISCARD = 21
SC_BB_DISCARD = 22
SC_SUPERTILE_COUNT = 23
SC_SUPERTILE_PER_PRIM_H0 = 24
SC_SUPERTILE_PER_PRIM_H1 = 25
SC_SUPERTILE_PER_PRIM_H2 = 26
SC_SUPERTILE_PER_PRIM_H3 = 27
SC_SUPERTILE_PER_PRIM_H4 = 28
SC_SUPERTILE_PER_PRIM_H5 = 29
SC_SUPERTILE_PER_PRIM_H6 = 30
SC_SUPERTILE_PER_PRIM_H7 = 31
SC_SUPERTILE_PER_PRIM_H8 = 32
SC_SUPERTILE_PER_PRIM_H9 = 33
SC_SUPERTILE_PER_PRIM_H10 = 34
SC_SUPERTILE_PER_PRIM_H11 = 35
SC_SUPERTILE_PER_PRIM_H12 = 36
SC_SUPERTILE_PER_PRIM_H13 = 37
SC_SUPERTILE_PER_PRIM_H14 = 38
SC_SUPERTILE_PER_PRIM_H15 = 39
SC_SUPERTILE_PER_PRIM_H16 = 40
SC_TILE_PER_PRIM_H0 = 41
SC_TILE_PER_PRIM_H1 = 42
SC_TILE_PER_PRIM_H2 = 43
SC_TILE_PER_PRIM_H3 = 44
SC_TILE_PER_PRIM_H4 = 45
SC_TILE_PER_PRIM_H5 = 46
SC_TILE_PER_PRIM_H6 = 47
SC_TILE_PER_PRIM_H7 = 48
SC_TILE_PER_PRIM_H8 = 49
SC_TILE_PER_PRIM_H9 = 50
SC_TILE_PER_PRIM_H10 = 51
SC_TILE_PER_PRIM_H11 = 52
SC_TILE_PER_PRIM_H12 = 53
SC_TILE_PER_PRIM_H13 = 54
SC_TILE_PER_PRIM_H14 = 55
SC_TILE_PER_PRIM_H15 = 56
SC_TILE_PER_PRIM_H16 = 57
SC_TILE_PER_SUPERTILE_H0 = 58
SC_TILE_PER_SUPERTILE_H1 = 59
SC_TILE_PER_SUPERTILE_H2 = 60
SC_TILE_PER_SUPERTILE_H3 = 61
SC_TILE_PER_SUPERTILE_H4 = 62
SC_TILE_PER_SUPERTILE_H5 = 63
SC_TILE_PER_SUPERTILE_H6 = 64
SC_TILE_PER_SUPERTILE_H7 = 65
SC_TILE_PER_SUPERTILE_H8 = 66
SC_TILE_PER_SUPERTILE_H9 = 67
SC_TILE_PER_SUPERTILE_H10 = 68
SC_TILE_PER_SUPERTILE_H11 = 69
SC_TILE_PER_SUPERTILE_H12 = 70
SC_TILE_PER_SUPERTILE_H13 = 71
SC_TILE_PER_SUPERTILE_H14 = 72
SC_TILE_PER_SUPERTILE_H15 = 73
SC_TILE_PER_SUPERTILE_H16 = 74
SC_TILE_PICKED_H1 = 75
SC_PERF_SEL_RESERVED_76 = 76
SC_PERF_SEL_RESERVED_77 = 77
SC_PERF_SEL_RESERVED_78 = 78
SC_QZ0_TILE_COUNT = 79
SC_PERF_SEL_RESERVED_80 = 80
SC_PERF_SEL_RESERVED_81 = 81
SC_PERF_SEL_RESERVED_82 = 82
SC_QZ0_TILE_COVERED_COUNT = 83
SC_PERF_SEL_RESERVED_84 = 84
SC_PERF_SEL_RESERVED_85 = 85
SC_PERF_SEL_RESERVED_86 = 86
SC_QZ0_TILE_NOT_COVERED_COUNT = 87
SC_PERF_SEL_RESERVED_88 = 88
SC_PERF_SEL_RESERVED_89 = 89
SC_PERF_SEL_RESERVED_90 = 90
SC_QZ0_QUAD_PER_TILE_H0 = 91
SC_QZ0_QUAD_PER_TILE_H1 = 92
SC_QZ0_QUAD_PER_TILE_H2 = 93
SC_QZ0_QUAD_PER_TILE_H3 = 94
SC_QZ0_QUAD_PER_TILE_H4 = 95
SC_QZ0_QUAD_PER_TILE_H5 = 96
SC_QZ0_QUAD_PER_TILE_H6 = 97
SC_QZ0_QUAD_PER_TILE_H7 = 98
SC_QZ0_QUAD_PER_TILE_H8 = 99
SC_QZ0_QUAD_PER_TILE_H9 = 100
SC_QZ0_QUAD_PER_TILE_H10 = 101
SC_QZ0_QUAD_PER_TILE_H11 = 102
SC_QZ0_QUAD_PER_TILE_H12 = 103
SC_QZ0_QUAD_PER_TILE_H13 = 104
SC_QZ0_QUAD_PER_TILE_H14 = 105
SC_QZ0_QUAD_PER_TILE_H15 = 106
SC_QZ0_QUAD_PER_TILE_H16 = 107
SC_PERF_SEL_RESERVED_108 = 108
SC_PERF_SEL_RESERVED_109 = 109
SC_PERF_SEL_RESERVED_110 = 110
SC_PERF_SEL_RESERVED_111 = 111
SC_PERF_SEL_RESERVED_112 = 112
SC_PERF_SEL_RESERVED_113 = 113
SC_PERF_SEL_RESERVED_114 = 114
SC_PERF_SEL_RESERVED_115 = 115
SC_PERF_SEL_RESERVED_116 = 116
SC_PERF_SEL_RESERVED_117 = 117
SC_PERF_SEL_RESERVED_118 = 118
SC_PERF_SEL_RESERVED_119 = 119
SC_PERF_SEL_RESERVED_120 = 120
SC_PERF_SEL_RESERVED_121 = 121
SC_PERF_SEL_RESERVED_122 = 122
SC_PERF_SEL_RESERVED_123 = 123
SC_PERF_SEL_RESERVED_124 = 124
SC_PERF_SEL_RESERVED_125 = 125
SC_PERF_SEL_RESERVED_126 = 126
SC_PERF_SEL_RESERVED_127 = 127
SC_PERF_SEL_RESERVED_128 = 128
SC_PERF_SEL_RESERVED_129 = 129
SC_PERF_SEL_RESERVED_130 = 130
SC_PERF_SEL_RESERVED_131 = 131
SC_PERF_SEL_RESERVED_132 = 132
SC_PERF_SEL_RESERVED_133 = 133
SC_PERF_SEL_RESERVED_134 = 134
SC_PERF_SEL_RESERVED_135 = 135
SC_PERF_SEL_RESERVED_136 = 136
SC_PERF_SEL_RESERVED_137 = 137
SC_PERF_SEL_RESERVED_138 = 138
SC_PERF_SEL_RESERVED_139 = 139
SC_PERF_SEL_RESERVED_140 = 140
SC_PERF_SEL_RESERVED_141 = 141
SC_PERF_SEL_RESERVED_142 = 142
SC_PERF_SEL_RESERVED_143 = 143
SC_PERF_SEL_RESERVED_144 = 144
SC_PERF_SEL_RESERVED_145 = 145
SC_PERF_SEL_RESERVED_146 = 146
SC_PERF_SEL_RESERVED_147 = 147
SC_PERF_SEL_RESERVED_148 = 148
SC_PERF_SEL_RESERVED_149 = 149
SC_PERF_SEL_RESERVED_150 = 150
SC_PERF_SEL_RESERVED_151 = 151
SC_PERF_SEL_RESERVED_152 = 152
SC_PERF_SEL_RESERVED_153 = 153
SC_PERF_SEL_RESERVED_154 = 154
SC_PERF_SEL_RESERVED_155 = 155
SC_PERF_SEL_RESERVED_156 = 156
SC_PERF_SEL_RESERVED_157 = 157
SC_PERF_SEL_RESERVED_158 = 158
SC_QZ0_QUAD_COUNT = 159
SC_PERF_SEL_RESERVED_160 = 160
SC_PERF_SEL_RESERVED_161 = 161
SC_PERF_SEL_RESERVED_162 = 162
SC_P0_HIZ_TILE_COUNT = 163
SC_PERF_SEL_RESERVED_164 = 164
SC_PERF_SEL_RESERVED_165 = 165
SC_PERF_SEL_RESERVED_166 = 166
SC_P0_HIZ_QUAD_PER_TILE_H0 = 167
SC_P0_HIZ_QUAD_PER_TILE_H1 = 168
SC_P0_HIZ_QUAD_PER_TILE_H2 = 169
SC_P0_HIZ_QUAD_PER_TILE_H3 = 170
SC_P0_HIZ_QUAD_PER_TILE_H4 = 171
SC_P0_HIZ_QUAD_PER_TILE_H5 = 172
SC_P0_HIZ_QUAD_PER_TILE_H6 = 173
SC_P0_HIZ_QUAD_PER_TILE_H7 = 174
SC_P0_HIZ_QUAD_PER_TILE_H8 = 175
SC_P0_HIZ_QUAD_PER_TILE_H9 = 176
SC_P0_HIZ_QUAD_PER_TILE_H10 = 177
SC_P0_HIZ_QUAD_PER_TILE_H11 = 178
SC_P0_HIZ_QUAD_PER_TILE_H12 = 179
SC_P0_HIZ_QUAD_PER_TILE_H13 = 180
SC_P0_HIZ_QUAD_PER_TILE_H14 = 181
SC_P0_HIZ_QUAD_PER_TILE_H15 = 182
SC_P0_HIZ_QUAD_PER_TILE_H16 = 183
SC_PERF_SEL_RESERVED_184 = 184
SC_PERF_SEL_RESERVED_185 = 185
SC_PERF_SEL_RESERVED_186 = 186
SC_PERF_SEL_RESERVED_187 = 187
SC_PERF_SEL_RESERVED_188 = 188
SC_PERF_SEL_RESERVED_189 = 189
SC_PERF_SEL_RESERVED_190 = 190
SC_PERF_SEL_RESERVED_191 = 191
SC_PERF_SEL_RESERVED_192 = 192
SC_PERF_SEL_RESERVED_193 = 193
SC_PERF_SEL_RESERVED_194 = 194
SC_PERF_SEL_RESERVED_195 = 195
SC_PERF_SEL_RESERVED_196 = 196
SC_PERF_SEL_RESERVED_197 = 197
SC_PERF_SEL_RESERVED_198 = 198
SC_PERF_SEL_RESERVED_199 = 199
SC_PERF_SEL_RESERVED_200 = 200
SC_PERF_SEL_RESERVED_201 = 201
SC_PERF_SEL_RESERVED_202 = 202
SC_PERF_SEL_RESERVED_203 = 203
SC_PERF_SEL_RESERVED_204 = 204
SC_PERF_SEL_RESERVED_205 = 205
SC_PERF_SEL_RESERVED_206 = 206
SC_PERF_SEL_RESERVED_207 = 207
SC_PERF_SEL_RESERVED_208 = 208
SC_PERF_SEL_RESERVED_209 = 209
SC_PERF_SEL_RESERVED_210 = 210
SC_PERF_SEL_RESERVED_211 = 211
SC_PERF_SEL_RESERVED_212 = 212
SC_PERF_SEL_RESERVED_213 = 213
SC_PERF_SEL_RESERVED_214 = 214
SC_PERF_SEL_RESERVED_215 = 215
SC_PERF_SEL_RESERVED_216 = 216
SC_PERF_SEL_RESERVED_217 = 217
SC_PERF_SEL_RESERVED_218 = 218
SC_PERF_SEL_RESERVED_219 = 219
SC_PERF_SEL_RESERVED_220 = 220
SC_PERF_SEL_RESERVED_221 = 221
SC_PERF_SEL_RESERVED_222 = 222
SC_PERF_SEL_RESERVED_223 = 223
SC_PERF_SEL_RESERVED_224 = 224
SC_PERF_SEL_RESERVED_225 = 225
SC_PERF_SEL_RESERVED_226 = 226
SC_PERF_SEL_RESERVED_227 = 227
SC_PERF_SEL_RESERVED_228 = 228
SC_PERF_SEL_RESERVED_229 = 229
SC_PERF_SEL_RESERVED_230 = 230
SC_PERF_SEL_RESERVED_231 = 231
SC_PERF_SEL_RESERVED_232 = 232
SC_PERF_SEL_RESERVED_233 = 233
SC_PERF_SEL_RESERVED_234 = 234
SC_P0_HIZ_QUAD_COUNT = 235
SC_PERF_SEL_RESERVED_236 = 236
SC_PERF_SEL_RESERVED_237 = 237
SC_PERF_SEL_RESERVED_238 = 238
SC_P0_DETAIL_QUAD_COUNT = 239
SC_PERF_SEL_RESERVED_240 = 240
SC_PERF_SEL_RESERVED_241 = 241
SC_PERF_SEL_RESERVED_242 = 242
SC_P0_DETAIL_QUAD_WITH_1_PIX = 243
SC_P0_DETAIL_QUAD_WITH_2_PIX = 244
SC_P0_DETAIL_QUAD_WITH_3_PIX = 245
SC_P0_DETAIL_QUAD_WITH_4_PIX = 246
SC_PERF_SEL_RESERVED_247 = 247
SC_PERF_SEL_RESERVED_248 = 248
SC_PERF_SEL_RESERVED_249 = 249
SC_PERF_SEL_RESERVED_250 = 250
SC_PERF_SEL_RESERVED_251 = 251
SC_PERF_SEL_RESERVED_252 = 252
SC_PERF_SEL_RESERVED_253 = 253
SC_PERF_SEL_RESERVED_254 = 254
SC_PERF_SEL_RESERVED_255 = 255
SC_PERF_SEL_RESERVED_256 = 256
SC_PERF_SEL_RESERVED_257 = 257
SC_PERF_SEL_RESERVED_258 = 258
SC_EARLYZ_QUAD_COUNT = 259
SC_EARLYZ_QUAD_WITH_1_PIX = 260
SC_EARLYZ_QUAD_WITH_2_PIX = 261
SC_EARLYZ_QUAD_WITH_3_PIX = 262
SC_EARLYZ_QUAD_WITH_4_PIX = 263
SC_PKR_QUAD_PER_ROW_H1 = 264
SC_PKR_QUAD_PER_ROW_H2 = 265
SC_PKR_4X2_QUAD_SPLIT = 266
SC_PKR_4X2_FILL_QUAD = 267
SC_PKR_END_OF_VECTOR = 268
SC_PKR_CONTROL_XFER = 269
SC_PKR_DBHANG_FORCE_EOV = 270
SC_REG_SCLK_BUSY = 271
SC_GRP0_DYN_SCLK_BUSY = 272
SC_GRP1_DYN_SCLK_BUSY = 273
SC_GRP2_DYN_SCLK_BUSY = 274
SC_GRP3_DYN_SCLK_BUSY = 275
SC_GRP4_DYN_SCLK_BUSY = 276
SC_PA0_SC_DATA_FIFO_RD = 277
SC_PA0_SC_DATA_FIFO_WE = 278
SC_PERF_SEL_RESERVED_279 = 279
SC_PERF_SEL_RESERVED_280 = 280
SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 281
SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 282
SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 283
SC_PS_ARB_STALLED_FROM_BELOW = 284
SC_PS_ARB_STARVED_FROM_ABOVE = 285
SC_PS_ARB_SC_BUSY = 286
SC_PS_ARB_PA_SC_BUSY = 287
SC_PERF_SEL_RESERVED_288 = 288
SC_PERF_SEL_RESERVED_289 = 289
SC_PERF_SEL_RESERVED_290 = 290
SC_PERF_SEL_RESERVED_291 = 291
SC_PA_SC_DEALLOC_2_0_WE = 292
SC_PERF_SEL_RESERVED_293 = 293
SC_PERF_SEL_RESERVED_294 = 294
SC_PERF_SEL_RESERVED_295 = 295
SC_PERF_SEL_RESERVED_296 = 296
SC_PERF_SEL_RESERVED_297 = 297
SC_PERF_SEL_RESERVED_298 = 298
SC_PERF_SEL_RESERVED_299 = 299
SC_PA0_SC_EOP_WE = 300
SC_PERF_SEL_RESERVED_301 = 301
SC_PA0_SC_EVENT_WE = 302
SC_PERF_SEL_RESERVED_303 = 303
SC_PERF_SEL_RESERVED_304 = 304
SC_PERF_SEL_RESERVED_305 = 305
SC_PERF_SEL_RESERVED_306 = 306
SC_PERF_SEL_RESERVED_307 = 307
SC_PERF_SEL_RESERVED_308 = 308
SC_PERF_SEL_RESERVED_309 = 309
SC_PERF_SEL_RESERVED_310 = 310
SC_PERF_SEL_RESERVED_311 = 311
SC_PERF_SEL_RESERVED_312 = 312
SC_PERF_SEL_RESERVED_313 = 313
SC_PERF_SEL_RESERVED_314 = 314
SC_PERF_SEL_RESERVED_315 = 315
SC_PERF_SEL_RESERVED_316 = 316
SC_PERF_SEL_RESERVED_317 = 317
SC_PA_SC_FPOV_WE = 318
SC_PERF_SEL_RESERVED_319 = 319
SC_PERF_SEL_RESERVED_320 = 320
SC_PERF_SEL_RESERVED_321 = 321
SC_PERF_SEL_RESERVED_322 = 322
SC_PERF_SEL_RESERVED_323 = 323
SC_PERF_SEL_RESERVED_324 = 324
SC_PERF_SEL_RESERVED_325 = 325
SC_SPI_DEALLOC_4_0 = 326
SC_SPI_DEALLOC_7_5 = 327
SC_PERF_SEL_RESERVED_328 = 328
SC_PERF_SEL_RESERVED_329 = 329
SC_PERF_SEL_RESERVED_330 = 330
SC_PERF_SEL_RESERVED_331 = 331
SC_PERF_SEL_RESERVED_332 = 332
SC_PERF_SEL_RESERVED_333 = 333
SC_PERF_SEL_RESERVED_334 = 334
SC_PERF_SEL_RESERVED_335 = 335
SC_PERF_SEL_RESERVED_336 = 336
SC_PERF_SEL_RESERVED_337 = 337
SC_SPI_FPOV_4_0 = 338
SC_SPI_FPOV_7_5 = 339
SC_PERF_SEL_RESERVED_340 = 340
SC_PERF_SEL_RESERVED_341 = 341
SC_SPI_EVENT = 342
SC_PS_TS_EVENT_FIFO_PUSH = 343
SC_PS_TS_EVENT_FIFO_POP = 344
SC_PS_CTX_DONE_FIFO_PUSH = 345
SC_PS_CTX_DONE_FIFO_POP = 346
SC_PERF_SEL_RESERVED_347 = 347
SC_PERF_SEL_RESERVED_348 = 348
SC_PA0_SC_NULL_WE = 349
SC_PA0_SC_NULL_DEALLOC_WE = 350
SC_PERF_SEL_RESERVED_351 = 351
SC_PA0_SC_DATA_FIFO_EOP_RD = 352
SC_PA0_SC_DEALLOC_2_0_RD = 353
SC_PERF_SEL_RESERVED_354 = 354
SC_PERF_SEL_RESERVED_355 = 355
SC_PERF_SEL_RESERVED_356 = 356
SC_PERF_SEL_RESERVED_357 = 357
SC_PERF_SEL_RESERVED_358 = 358
SC_PERF_SEL_RESERVED_359 = 359
SC_PERF_SEL_RESERVED_360 = 360
SC_PERF_SEL_RESERVED_361 = 361
SC_PERF_SEL_RESERVED_362 = 362
SC_PERF_SEL_RESERVED_363 = 363
SC_PERF_SEL_RESERVED_364 = 364
SC_PERF_SEL_RESERVED_365 = 365
SC_PERF_SEL_RESERVED_366 = 366
SC_PERF_SEL_RESERVED_367 = 367
SC_PERF_SEL_RESERVED_368 = 368
SC_PERF_SEL_RESERVED_369 = 369
SC_PERF_SEL_RESERVED_370 = 370
SC_PERF_SEL_RESERVED_371 = 371
SC_PERF_SEL_RESERVED_372 = 372
SC_PS_PA0_SC_FIFO_EMPTY = 373
SC_PS_PA0_SC_FIFO_FULL = 374
SC_PERF_SEL_RESERVED_375 = 375
SC_PERF_SEL_RESERVED_376 = 376
SC_PERF_SEL_RESERVED_377 = 377
SC_PERF_SEL_RESERVED_378 = 378
SC_PERF_SEL_RESERVED_379 = 379
SC_PERF_SEL_RESERVED_380 = 380
SC_PERF_SEL_RESERVED_381 = 381
SC_PERF_SEL_RESERVED_382 = 382
SC_PERF_SEL_RESERVED_383 = 383
SC_PERF_SEL_RESERVED_384 = 384
SC_PERF_SEL_RESERVED_385 = 385
SC_BUSY_CNT_NOT_ZERO = 386
SC_BM_BUSY = 387
SC_BACKEND_BUSY = 388
SC_SCF_SCB_INTERFACE_BUSY = 389
SC_SCB_BUSY = 390
SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 391
SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 392
SC_PBB_BIN_HIST_NUM_PRIMS = 393
SC_PBB_BATCH_HIST_NUM_PRIMS = 394
SC_PBB_BIN_HIST_NUM_CONTEXTS = 395
SC_PBB_BATCH_HIST_NUM_CONTEXTS = 396
SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 397
SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 398
SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 399
SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 400
SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 401
SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 402
SC_PBB_BUSY = 403
SC_PBB_BUSY_AND_NO_SENDS = 404
SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 405
SC_PBB_NUM_BINS = 406
SC_PBB_END_OF_BIN = 407
SC_PBB_END_OF_BATCH = 408
SC_PBB_PRIMBIN_PROCESSED = 409
SC_PBB_PRIM_ADDED_TO_BATCH = 410
SC_PBB_NONBINNED_PRIM = 411
SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 412
SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 413
SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 414
SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 415
SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 416
SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 417
SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 418
SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 419
SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 420
SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 421
SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 422
SC_PERF_SEL_RESERVED_423 = 423
SC_PERF_SEL_RESERVED_424 = 424
SC_PERF_SEL_RESERVED_425 = 425
SC_PERF_SEL_RESERVED_426 = 426
SC_PERF_SEL_RESERVED_427 = 427
SC_PERF_SEL_RESERVED_428 = 428
SC_PERF_SEL_RESERVED_429 = 429
SC_PERF_SEL_RESERVED_430 = 430
SC_PERF_SEL_RESERVED_431 = 431
SC_PERF_SEL_RESERVED_432 = 432
SC_PERF_SEL_RESERVED_433 = 433
SC_PERF_SEL_RESERVED_434 = 434
SC_PERF_SEL_RESERVED_435 = 435
SC_PERF_SEL_RESERVED_436 = 436
SC_GRP5_DYN_SCLK_BUSY = 437
SC_GRP6_DYN_SCLK_BUSY = 438
SC_GRP7_DYN_SCLK_BUSY = 439
SC_GRP8_DYN_SCLK_BUSY = 440
SC_GRP9_DYN_SCLK_BUSY = 441
SC_PS_TO_BE_SCLK_GATE_STALL = 442
SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 443
SC_PK_BUSY = 444
SC_PK_MAX_DEALLOC_FORCE_EOV = 445
SC_PK_DEALLOC_WAVE_BREAK = 446
SC_SPI_SEND = 447
SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 448
SC_SPI_CREDIT_AT_MAX = 449
SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 450
SC_BCI_SEND = 451
SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 452
SC_BCI_CREDIT_AT_MAX = 453
SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 454
SC_SPIBC_FULL_FREEZE = 455
SC_PW_BM_PASS_EMPTY_PRIM = 456
SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 457
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 458
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 459
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 460
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 461
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 462
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 463
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 464
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 465
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 466
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 467
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 468
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 469
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 470
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 471
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 472
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 473
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 474
SC_DB0_TILE_INTERFACE_BUSY = 475
SC_DB0_TILE_INTERFACE_SEND = 476
SC_DB0_TILE_INTERFACE_SEND_EVENT = 477
SC_PERF_SEL_RESERVED_478 = 478
SC_PERF_SEL_RESERVED_479 = 479
SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 480
SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 481
SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 482
SC_PERF_SEL_RESERVED_483 = 483
SC_PERF_SEL_RESERVED_484 = 484
SC_PERF_SEL_RESERVED_485 = 485
SC_PERF_SEL_RESERVED_486 = 486
SC_PERF_SEL_RESERVED_487 = 487
SC_PERF_SEL_RESERVED_488 = 488
SC_PERF_SEL_RESERVED_489 = 489
SC_PERF_SEL_RESERVED_490 = 490
SC_BACKEND_PRIM_FIFO_FULL = 491
SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 492
SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 493
SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 494
SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 495
SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 496
SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 497
SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 498
SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 499
SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 500
SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 501
SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 502
SC_STALLED_BY_DB0_TILEFIFO = 503
SC_DB0_QUAD_INTF_SEND = 504
SC_DB0_QUAD_INTF_BUSY = 505
SC_DB0_QUAD_INTF_STALLED_BY_DB = 506
SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 507
SC_DB0_QUAD_INTF_IDLE = 508
SC_PERF_SEL_RESERVED_509 = 509
SC_PERF_SEL_RESERVED_510 = 510
SC_PERF_SEL_RESERVED_511 = 511
SC_PERF_SEL_RESERVED_512 = 512
SC_PERF_SEL_RESERVED_513 = 513
SC_PERF_SEL_RESERVED_514 = 514
SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 515
SC_PKR_WAVE_BREAK_FULL_TILE = 516
SC_RESERVED_60 = 517
SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 518
SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 519
SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 520
SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 521
SC_DB0_TILE_MASK_FIFO_FULL = 522
SC_PERF_SEL_RESERVED_523 = 523
SC_PERF_SEL_RESERVED_524 = 524
SC_PERF_SEL_RESERVED_525 = 525
SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 526
SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 527
SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 528
SC_PS_PM_PFF_PW_FULL = 529
SC_PS_PM_ZFF_PW_FULL = 530
SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 531
SC_PERF_SEL_RESERVED_532 = 532
SC_PERF_SEL_RESERVED_533 = 533
SC_PERF_SEL_RESERVED_534 = 534
SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 535
SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 536
SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 537
SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 538
SC_PERF_SEL_RESERVED_539 = 539
SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 540
SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 541
SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 542
SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 543
SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 544
SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 545
SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 546
SC_PK_PM_OREO_CONFLICT_QUAD_FORCE_EOV_WAVE_BRK_1H = 547
SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 548
SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 549
SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 550
SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 551
SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 552
SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 553
SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 554
SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 555
SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 556
SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 557
SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 558
SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 559
SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 560
SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 561
SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 562
SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 563
SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 564
SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 565
SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 566
SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 567
SC_PERF_SEL_RESERVED_568 = 568
SC_PBB_RESERVED = 569
SC_BM_BE0_STALLED = 570
SC_BM_BE1_STALLED = 571
SC_BM_BE2_STALLED = 572
SC_BM_BE3_STALLED = 573
SC_BM_MULTI_ACCUM_1_BE_STALLED = 574
SC_BM_MULTI_ACCUM_2_BE_STALLED = 575
SC_BM_MULTI_ACCUM_3_BE_STALLED = 576
SC_BM_MULTI_ACCUM_4_BE_STALLED = 577
SC_PBB_READ_PH0 = 578
SC_PBB_READ_DEALLOC_4_0 = 579
SC_PBB_READ_DEALLOC_7_5 = 580
SC_PBB_READ_FPOG_4_0 = 581
SC_PBB_READ_FPOG_7_5 = 582
SC_VRC_SECTOR_HIT = 583
SC_VRC_TAG_MISS = 584
SC_VRC_SECTOR_MISS = 585
SC_VRC_LRU_EVICT_STALL = 586
SC_VRC_LRU_EVICT_SCHEDULED_EVICT_STALL = 587
SC_VRC_LRU_EVICT_PENDING_EVICT_STALL = 588
SC_VRC_REEVICTION_STALL = 589
SC_VRC_EVICT_NONZERO_INFLIGHT_STALL = 590
SC_VRC_REPLACE_SCHEDULED_EVICT_STALL = 591
SC_VRC_REPLACE_PENDING_EVICT_STALL = 592
SC_VRC_REPLACE_FLUSH_IN_PROGRESS_STALL = 593
SC_VRC_INFLIGHT_COUNTER_MAXIMUM_STALL = 594
SC_VRC_READ_OUTPUT_STALL = 595
SC_VRC_WRITE_OUTPUT_STALL = 596
SC_VRC_ACK_OUTPUT_STALL = 597
SC_VRC_FLUSH_EVICT_STALL = 598
SC_VRC_FLUSH_REFLUSH_STALL = 599
SC_VRC_FLUSH_FIP_HIT_STALL = 600
SC_VRC_FLUSH_WRREQ_DRAIN_STALL = 601
SC_VRC_FLUSH_DONE_STALL = 602
SC_VRC_FLUSH_STALL = 603
SC_VRC_STALL = 604
SC_VRC_FLUSH = 605
SC_VRC_SECTORS_FLUSHED = 606
SC_VRC_DIRTY_SECTORS_FLUSHED = 607
SC_VRC_TAGS_FLUSHED = 608
SC_VRC_HPF_REQ = 609
SC_VRC_HPF_EVENT = 610
SC_VRC_HPF_STALLED = 611
SC_VRC_PROBE_ACK_TILES = 612
SC_VRC_GL1X_RD_REQ = 613
SC_VRC_GL1X_WR_REQ = 614
SC_VRC_GL1X_SRC_XFR = 615
SC_VRC_GL1X_RD_RET = 616
SC_VRC_GL1X_WR_ACK = 617
SC_VRC_GL1X_RD_XNACK = 618
SC_VRC_GL1X_WR_XNACK = 619
SC_VRC_GL1X_REQ_STALLED = 620
SC_VRC_GL1X_SRC_STALLED = 621
SC_VRC_RATEMEM_WE_CNT = 622
SC_VRC_RATEMEM_RE_CNT = 623
SC_VRC_HINTMEM_WE_CNT = 624
SC_VRC_HINTMEM_RE_CNT = 625
SC_VRC_BUSY = 626
SC_GL1X_BUSY = 627
SC_BE_VRS_RD_REQ = 628
SC_BE_VRS_RD_REQ_STALLED = 629
SC_BE_VRS_RD_REQ_HIT = 630
SC_BE_VRS_RD_RET = 631
SC_BE_VRS_RD_RET_STALLED = 632
SC_BE_VRS_FB_RET = 633
SC_BE_VRS_FB_RET_STALLED = 634
SC_BE_VRS_FB_RET_HIT = 635
SC_VRS_BE_BUSY = 636
SC_PWS_CS_EVENTS_PWS_ENABLE = 637
SC_PWS_PS_EVENTS_PWS_ENABLE = 638
SC_PWS_TS_EVENTS_PWS_ENABLE = 639
SC_PWS_STALLED = 640
SC_PWS_P0_CS_SYNC_COMPLETE = 641
SC_PWS_P0_PS_SYNC_COMPLETE = 642
SC_PWS_P0_TS_SYNC_COMPLETE = 643
SC_PWS_P1_CS_SYNC_COMPLETE = 644
SC_PWS_P1_PS_SYNC_COMPLETE = 645
SC_PWS_P1_TS_SYNC_COMPLETE = 646
SC_PKR_PC_NO_CREDITS = 647
SC_PKR_PC_STALLED = 648
SC_PKR_PC_SEND = 649
SC_PKR_PC_SEND_PRIM_VALID_1 = 650
SC_PKR_PC_SEND_PRIM_VALID_0 = 651
SC_PKR_PC_SEND_TRUE_PRIM = 652
SC_PKR_PC_SEND_EOV = 653
SC_PKR_PC_SEND_EVENT = 654
SC_PKR_DB_WAVE_STALL = 655
SC_PKR_PSINVOC_SEDC_FIFO_FULL = 656
SC_PKR_OREO_STALLED_BY_NO_VALID_WAIVE_ID = 657
SC_PKR_SPI_QUAD_COUNT = 658
SC_PKR_DB_OREO_WAVE_QUAD_COUNT = 659
SC_PKR_BCI_QUAD_NEW_PRIM = 660
SC_SPI_WAVE_STALLED_BY_SPI = 661
SC_PERFCNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'ScMap'
ScMap__enumvalues = {
0: 'RASTER_CONFIG_SC_MAP_0',
1: 'RASTER_CONFIG_SC_MAP_1',
2: 'RASTER_CONFIG_SC_MAP_2',
3: 'RASTER_CONFIG_SC_MAP_3',
}
RASTER_CONFIG_SC_MAP_0 = 0
RASTER_CONFIG_SC_MAP_1 = 1
RASTER_CONFIG_SC_MAP_2 = 2
RASTER_CONFIG_SC_MAP_3 = 3
ScMap = ctypes.c_uint32 # enum
# values for enumeration 'ScUncertaintyRegionMode'
ScUncertaintyRegionMode__enumvalues = {
0: 'SC_HALF_LSB',
1: 'SC_LSB_ONE_SIDED',
2: 'SC_LSB_TWO_SIDED',
}
SC_HALF_LSB = 0
SC_LSB_ONE_SIDED = 1
SC_LSB_TWO_SIDED = 2
ScUncertaintyRegionMode = ctypes.c_uint32 # enum
# values for enumeration 'ScUncertaintyRegionMult'
ScUncertaintyRegionMult__enumvalues = {
0: 'SC_UR_1X',
1: 'SC_UR_2X',
2: 'SC_UR_4X',
3: 'SC_UR_8X',
}
SC_UR_1X = 0
SC_UR_2X = 1
SC_UR_4X = 2
SC_UR_8X = 3
ScUncertaintyRegionMult = ctypes.c_uint32 # enum
# values for enumeration 'ScXsel'
ScXsel__enumvalues = {
0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3
ScXsel = ctypes.c_uint32 # enum
# values for enumeration 'ScYsel'
ScYsel__enumvalues = {
0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3
ScYsel = ctypes.c_uint32 # enum
# values for enumeration 'SeMap'
SeMap__enumvalues = {
0: 'RASTER_CONFIG_SE_MAP_0',
1: 'RASTER_CONFIG_SE_MAP_1',
2: 'RASTER_CONFIG_SE_MAP_2',
3: 'RASTER_CONFIG_SE_MAP_3',
}
RASTER_CONFIG_SE_MAP_0 = 0
RASTER_CONFIG_SE_MAP_1 = 1
RASTER_CONFIG_SE_MAP_2 = 2
RASTER_CONFIG_SE_MAP_3 = 3
SeMap = ctypes.c_uint32 # enum
# values for enumeration 'SePairMap'
SePairMap__enumvalues = {
0: 'RASTER_CONFIG_SE_PAIR_MAP_0',
1: 'RASTER_CONFIG_SE_PAIR_MAP_1',
2: 'RASTER_CONFIG_SE_PAIR_MAP_2',
3: 'RASTER_CONFIG_SE_PAIR_MAP_3',
}
RASTER_CONFIG_SE_PAIR_MAP_0 = 0
RASTER_CONFIG_SE_PAIR_MAP_1 = 1
RASTER_CONFIG_SE_PAIR_MAP_2 = 2
RASTER_CONFIG_SE_PAIR_MAP_3 = 3
SePairMap = ctypes.c_uint32 # enum
# values for enumeration 'SePairXsel'
SePairXsel__enumvalues = {
0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3
SePairXsel = ctypes.c_uint32 # enum
# values for enumeration 'SePairYsel'
SePairYsel__enumvalues = {
0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3
SePairYsel = ctypes.c_uint32 # enum
# values for enumeration 'SeXsel'
SeXsel__enumvalues = {
0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3
SeXsel = ctypes.c_uint32 # enum
# values for enumeration 'SeYsel'
SeYsel__enumvalues = {
0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3
SeYsel = ctypes.c_uint32 # enum
# values for enumeration 'VRSCombinerModeSC'
VRSCombinerModeSC__enumvalues = {
0: 'SC_VRS_COMB_MODE_PASSTHRU',
1: 'SC_VRS_COMB_MODE_OVERRIDE',
2: 'SC_VRS_COMB_MODE_MIN',
3: 'SC_VRS_COMB_MODE_MAX',
4: 'SC_VRS_COMB_MODE_SATURATE',
}
SC_VRS_COMB_MODE_PASSTHRU = 0
SC_VRS_COMB_MODE_OVERRIDE = 1
SC_VRS_COMB_MODE_MIN = 2
SC_VRS_COMB_MODE_MAX = 3
SC_VRS_COMB_MODE_SATURATE = 4
VRSCombinerModeSC = ctypes.c_uint32 # enum
# values for enumeration 'VRSrate'
VRSrate__enumvalues = {
0: 'VRS_SHADING_RATE_1X1',
1: 'VRS_SHADING_RATE_1X2',
2: 'VRS_SHADING_RATE_UNDEFINED0',
3: 'VRS_SHADING_RATE_UNDEFINED1',
4: 'VRS_SHADING_RATE_2X1',
5: 'VRS_SHADING_RATE_2X2',
6: 'VRS_SHADING_RATE_2X4',
7: 'VRS_SHADING_RATE_UNDEFINED2',
8: 'VRS_SHADING_RATE_UNDEFINED3',
9: 'VRS_SHADING_RATE_4X2',
10: 'VRS_SHADING_RATE_4X4',
11: 'VRS_SHADING_RATE_UNDEFINED4',
12: 'VRS_SHADING_RATE_16X_SSAA',
13: 'VRS_SHADING_RATE_8X_SSAA',
14: 'VRS_SHADING_RATE_4X_SSAA',
15: 'VRS_SHADING_RATE_2X_SSAA',
}
VRS_SHADING_RATE_1X1 = 0
VRS_SHADING_RATE_1X2 = 1
VRS_SHADING_RATE_UNDEFINED0 = 2
VRS_SHADING_RATE_UNDEFINED1 = 3
VRS_SHADING_RATE_2X1 = 4
VRS_SHADING_RATE_2X2 = 5
VRS_SHADING_RATE_2X4 = 6
VRS_SHADING_RATE_UNDEFINED2 = 7
VRS_SHADING_RATE_UNDEFINED3 = 8
VRS_SHADING_RATE_4X2 = 9
VRS_SHADING_RATE_4X4 = 10
VRS_SHADING_RATE_UNDEFINED4 = 11
VRS_SHADING_RATE_16X_SSAA = 12
VRS_SHADING_RATE_8X_SSAA = 13
VRS_SHADING_RATE_4X_SSAA = 14
VRS_SHADING_RATE_2X_SSAA = 15
VRSrate = ctypes.c_uint32 # enum
# values for enumeration 'TC_EA_CID'
TC_EA_CID__enumvalues = {
0: 'TC_EA_CID_RT',
1: 'TC_EA_CID_FMASK',
2: 'TC_EA_CID_DCC',
3: 'TC_EA_CID_TCPMETA',
4: 'TC_EA_CID_Z',
5: 'TC_EA_CID_STENCIL',
6: 'TC_EA_CID_HTILE',
7: 'TC_EA_CID_MISC',
8: 'TC_EA_CID_TCP',
9: 'TC_EA_CID_SQC',
10: 'TC_EA_CID_CPF',
11: 'TC_EA_CID_CPG',
12: 'TC_EA_CID_IA',
13: 'TC_EA_CID_WD',
14: 'TC_EA_CID_PA',
15: 'TC_EA_CID_UTCL2_TPI',
}
TC_EA_CID_RT = 0
TC_EA_CID_FMASK = 1
TC_EA_CID_DCC = 2
TC_EA_CID_TCPMETA = 3
TC_EA_CID_Z = 4
TC_EA_CID_STENCIL = 5
TC_EA_CID_HTILE = 6
TC_EA_CID_MISC = 7
TC_EA_CID_TCP = 8
TC_EA_CID_SQC = 9
TC_EA_CID_CPF = 10
TC_EA_CID_CPG = 11
TC_EA_CID_IA = 12
TC_EA_CID_WD = 13
TC_EA_CID_PA = 14
TC_EA_CID_UTCL2_TPI = 15
TC_EA_CID = ctypes.c_uint32 # enum
# values for enumeration 'TC_NACKS'
TC_NACKS__enumvalues = {
0: 'TC_NACK_NO_FAULT',
1: 'TC_NACK_PAGE_FAULT',
2: 'TC_NACK_PROTECTION_FAULT',
3: 'TC_NACK_DATA_ERROR',
}
TC_NACK_NO_FAULT = 0
TC_NACK_PAGE_FAULT = 1
TC_NACK_PROTECTION_FAULT = 2
TC_NACK_DATA_ERROR = 3
TC_NACKS = ctypes.c_uint32 # enum
# values for enumeration 'TC_OP'
TC_OP__enumvalues = {
0: 'TC_OP_READ',
1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32',
2: 'TC_OP_ATOMIC_FMIN_RTN_32',
3: 'TC_OP_ATOMIC_FMAX_RTN_32',
4: 'TC_OP_RESERVED_FOP_RTN_32_0',
5: 'TC_OP_RESERVED_FADD_RTN_32',
6: 'TC_OP_RESERVED_FOP_RTN_32_2',
7: 'TC_OP_ATOMIC_SWAP_RTN_32',
8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32',
9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32',
10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32',
11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32',
12: 'TC_OP_PROBE_FILTER',
13: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32',
14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2',
15: 'TC_OP_ATOMIC_ADD_RTN_32',
16: 'TC_OP_ATOMIC_SUB_RTN_32',
17: 'TC_OP_ATOMIC_SMIN_RTN_32',
18: 'TC_OP_ATOMIC_UMIN_RTN_32',
19: 'TC_OP_ATOMIC_SMAX_RTN_32',
20: 'TC_OP_ATOMIC_UMAX_RTN_32',
21: 'TC_OP_ATOMIC_AND_RTN_32',
22: 'TC_OP_ATOMIC_OR_RTN_32',
23: 'TC_OP_ATOMIC_XOR_RTN_32',
24: 'TC_OP_ATOMIC_INC_RTN_32',
25: 'TC_OP_ATOMIC_DEC_RTN_32',
26: 'TC_OP_WBINVL1_VOL',
27: 'TC_OP_WBINVL1_SD',
28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0',
29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1',
30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2',
31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3',
32: 'TC_OP_WRITE',
33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64',
34: 'TC_OP_ATOMIC_FMIN_RTN_64',
35: 'TC_OP_ATOMIC_FMAX_RTN_64',
36: 'TC_OP_RESERVED_FOP_RTN_64_0',
37: 'TC_OP_RESERVED_FOP_RTN_64_1',
38: 'TC_OP_RESERVED_FOP_RTN_64_2',
39: 'TC_OP_ATOMIC_SWAP_RTN_64',
40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64',
41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64',
42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64',
43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64',
44: 'TC_OP_WBINVL2_SD',
45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0',
46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1',
47: 'TC_OP_ATOMIC_ADD_RTN_64',
48: 'TC_OP_ATOMIC_SUB_RTN_64',
49: 'TC_OP_ATOMIC_SMIN_RTN_64',
50: 'TC_OP_ATOMIC_UMIN_RTN_64',
51: 'TC_OP_ATOMIC_SMAX_RTN_64',
52: 'TC_OP_ATOMIC_UMAX_RTN_64',
53: 'TC_OP_ATOMIC_AND_RTN_64',
54: 'TC_OP_ATOMIC_OR_RTN_64',
55: 'TC_OP_ATOMIC_XOR_RTN_64',
56: 'TC_OP_ATOMIC_INC_RTN_64',
57: 'TC_OP_ATOMIC_DEC_RTN_64',
58: 'TC_OP_WBL2_NC',
59: 'TC_OP_WBL2_WC',
60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1',
61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2',
62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3',
63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4',
64: 'TC_OP_WBINVL1',
65: 'TC_OP_ATOMIC_FCMPSWAP_32',
66: 'TC_OP_ATOMIC_FMIN_32',
67: 'TC_OP_ATOMIC_FMAX_32',
68: 'TC_OP_RESERVED_FOP_32_0',
69: 'TC_OP_RESERVED_FADD_32',
70: 'TC_OP_RESERVED_FOP_32_2',
71: 'TC_OP_ATOMIC_SWAP_32',
72: 'TC_OP_ATOMIC_CMPSWAP_32',
73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32',
74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32',
75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32',
76: 'TC_OP_INV_METADATA',
77: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32',
78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2',
79: 'TC_OP_ATOMIC_ADD_32',
80: 'TC_OP_ATOMIC_SUB_32',
81: 'TC_OP_ATOMIC_SMIN_32',
82: 'TC_OP_ATOMIC_UMIN_32',
83: 'TC_OP_ATOMIC_SMAX_32',
84: 'TC_OP_ATOMIC_UMAX_32',
85: 'TC_OP_ATOMIC_AND_32',
86: 'TC_OP_ATOMIC_OR_32',
87: 'TC_OP_ATOMIC_XOR_32',
88: 'TC_OP_ATOMIC_INC_32',
89: 'TC_OP_ATOMIC_DEC_32',
90: 'TC_OP_INVL2_NC',
91: 'TC_OP_NOP_RTN0',
92: 'TC_OP_RESERVED_NON_FLOAT_32_1',
93: 'TC_OP_RESERVED_NON_FLOAT_32_2',
94: 'TC_OP_RESERVED_NON_FLOAT_32_3',
95: 'TC_OP_RESERVED_NON_FLOAT_32_4',
96: 'TC_OP_WBINVL2',
97: 'TC_OP_ATOMIC_FCMPSWAP_64',
98: 'TC_OP_ATOMIC_FMIN_64',
99: 'TC_OP_ATOMIC_FMAX_64',
100: 'TC_OP_RESERVED_FOP_64_0',
101: 'TC_OP_RESERVED_FOP_64_1',
102: 'TC_OP_RESERVED_FOP_64_2',
103: 'TC_OP_ATOMIC_SWAP_64',
104: 'TC_OP_ATOMIC_CMPSWAP_64',
105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64',
106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64',
107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64',
108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0',
109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1',
110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2',
111: 'TC_OP_ATOMIC_ADD_64',
112: 'TC_OP_ATOMIC_SUB_64',
113: 'TC_OP_ATOMIC_SMIN_64',
114: 'TC_OP_ATOMIC_UMIN_64',
115: 'TC_OP_ATOMIC_SMAX_64',
116: 'TC_OP_ATOMIC_UMAX_64',
117: 'TC_OP_ATOMIC_AND_64',
118: 'TC_OP_ATOMIC_OR_64',
119: 'TC_OP_ATOMIC_XOR_64',
120: 'TC_OP_ATOMIC_INC_64',
121: 'TC_OP_ATOMIC_DEC_64',
122: 'TC_OP_WBINVL2_NC',
123: 'TC_OP_NOP_ACK',
124: 'TC_OP_RESERVED_NON_FLOAT_64_1',
125: 'TC_OP_RESERVED_NON_FLOAT_64_2',
126: 'TC_OP_RESERVED_NON_FLOAT_64_3',
127: 'TC_OP_RESERVED_NON_FLOAT_64_4',
}
TC_OP_READ = 0
TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1
TC_OP_ATOMIC_FMIN_RTN_32 = 2
TC_OP_ATOMIC_FMAX_RTN_32 = 3
TC_OP_RESERVED_FOP_RTN_32_0 = 4
TC_OP_RESERVED_FADD_RTN_32 = 5
TC_OP_RESERVED_FOP_RTN_32_2 = 6
TC_OP_ATOMIC_SWAP_RTN_32 = 7
TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11
TC_OP_PROBE_FILTER = 12
TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14
TC_OP_ATOMIC_ADD_RTN_32 = 15
TC_OP_ATOMIC_SUB_RTN_32 = 16
TC_OP_ATOMIC_SMIN_RTN_32 = 17
TC_OP_ATOMIC_UMIN_RTN_32 = 18
TC_OP_ATOMIC_SMAX_RTN_32 = 19
TC_OP_ATOMIC_UMAX_RTN_32 = 20
TC_OP_ATOMIC_AND_RTN_32 = 21
TC_OP_ATOMIC_OR_RTN_32 = 22
TC_OP_ATOMIC_XOR_RTN_32 = 23
TC_OP_ATOMIC_INC_RTN_32 = 24
TC_OP_ATOMIC_DEC_RTN_32 = 25
TC_OP_WBINVL1_VOL = 26
TC_OP_WBINVL1_SD = 27
TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28
TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29
TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30
TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31
TC_OP_WRITE = 32
TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33
TC_OP_ATOMIC_FMIN_RTN_64 = 34
TC_OP_ATOMIC_FMAX_RTN_64 = 35
TC_OP_RESERVED_FOP_RTN_64_0 = 36
TC_OP_RESERVED_FOP_RTN_64_1 = 37
TC_OP_RESERVED_FOP_RTN_64_2 = 38
TC_OP_ATOMIC_SWAP_RTN_64 = 39
TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43
TC_OP_WBINVL2_SD = 44
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46
TC_OP_ATOMIC_ADD_RTN_64 = 47
TC_OP_ATOMIC_SUB_RTN_64 = 48
TC_OP_ATOMIC_SMIN_RTN_64 = 49
TC_OP_ATOMIC_UMIN_RTN_64 = 50
TC_OP_ATOMIC_SMAX_RTN_64 = 51
TC_OP_ATOMIC_UMAX_RTN_64 = 52
TC_OP_ATOMIC_AND_RTN_64 = 53
TC_OP_ATOMIC_OR_RTN_64 = 54
TC_OP_ATOMIC_XOR_RTN_64 = 55
TC_OP_ATOMIC_INC_RTN_64 = 56
TC_OP_ATOMIC_DEC_RTN_64 = 57
TC_OP_WBL2_NC = 58
TC_OP_WBL2_WC = 59
TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60
TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61
TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62
TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63
TC_OP_WBINVL1 = 64
TC_OP_ATOMIC_FCMPSWAP_32 = 65
TC_OP_ATOMIC_FMIN_32 = 66
TC_OP_ATOMIC_FMAX_32 = 67
TC_OP_RESERVED_FOP_32_0 = 68
TC_OP_RESERVED_FADD_32 = 69
TC_OP_RESERVED_FOP_32_2 = 70
TC_OP_ATOMIC_SWAP_32 = 71
TC_OP_ATOMIC_CMPSWAP_32 = 72
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75
TC_OP_INV_METADATA = 76
TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77
TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78
TC_OP_ATOMIC_ADD_32 = 79
TC_OP_ATOMIC_SUB_32 = 80
TC_OP_ATOMIC_SMIN_32 = 81
TC_OP_ATOMIC_UMIN_32 = 82
TC_OP_ATOMIC_SMAX_32 = 83
TC_OP_ATOMIC_UMAX_32 = 84
TC_OP_ATOMIC_AND_32 = 85
TC_OP_ATOMIC_OR_32 = 86
TC_OP_ATOMIC_XOR_32 = 87
TC_OP_ATOMIC_INC_32 = 88
TC_OP_ATOMIC_DEC_32 = 89
TC_OP_INVL2_NC = 90
TC_OP_NOP_RTN0 = 91
TC_OP_RESERVED_NON_FLOAT_32_1 = 92
TC_OP_RESERVED_NON_FLOAT_32_2 = 93
TC_OP_RESERVED_NON_FLOAT_32_3 = 94
TC_OP_RESERVED_NON_FLOAT_32_4 = 95
TC_OP_WBINVL2 = 96
TC_OP_ATOMIC_FCMPSWAP_64 = 97
TC_OP_ATOMIC_FMIN_64 = 98
TC_OP_ATOMIC_FMAX_64 = 99
TC_OP_RESERVED_FOP_64_0 = 100
TC_OP_RESERVED_FOP_64_1 = 101
TC_OP_RESERVED_FOP_64_2 = 102
TC_OP_ATOMIC_SWAP_64 = 103
TC_OP_ATOMIC_CMPSWAP_64 = 104
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110
TC_OP_ATOMIC_ADD_64 = 111
TC_OP_ATOMIC_SUB_64 = 112
TC_OP_ATOMIC_SMIN_64 = 113
TC_OP_ATOMIC_UMIN_64 = 114
TC_OP_ATOMIC_SMAX_64 = 115
TC_OP_ATOMIC_UMAX_64 = 116
TC_OP_ATOMIC_AND_64 = 117
TC_OP_ATOMIC_OR_64 = 118
TC_OP_ATOMIC_XOR_64 = 119
TC_OP_ATOMIC_INC_64 = 120
TC_OP_ATOMIC_DEC_64 = 121
TC_OP_WBINVL2_NC = 122
TC_OP_NOP_ACK = 123
TC_OP_RESERVED_NON_FLOAT_64_1 = 124
TC_OP_RESERVED_NON_FLOAT_64_2 = 125
TC_OP_RESERVED_NON_FLOAT_64_3 = 126
TC_OP_RESERVED_NON_FLOAT_64_4 = 127
TC_OP = ctypes.c_uint32 # enum
# values for enumeration 'TC_OP_MASKS'
TC_OP_MASKS__enumvalues = {
8: 'TC_OP_MASK_FLUSH_DENROM',
32: 'TC_OP_MASK_64',
64: 'TC_OP_MASK_NO_RTN',
}
TC_OP_MASK_FLUSH_DENROM = 8
TC_OP_MASK_64 = 32
TC_OP_MASK_NO_RTN = 64
TC_OP_MASKS = ctypes.c_uint32 # enum
# values for enumeration 'CLKGATE_BASE_MODE'
CLKGATE_BASE_MODE__enumvalues = {
0: 'MULT_8',
1: 'MULT_16',
}
MULT_8 = 0
MULT_16 = 1
CLKGATE_BASE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CLKGATE_SM_MODE'
CLKGATE_SM_MODE__enumvalues = {
0: 'ON_SEQ',
1: 'OFF_SEQ',
2: 'PROG_SEQ',
3: 'READ_SEQ',
4: 'SM_MODE_RESERVED',
}
ON_SEQ = 0
OFF_SEQ = 1
PROG_SEQ = 2
READ_SEQ = 3
SM_MODE_RESERVED = 4
CLKGATE_SM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CovToShaderSel'
CovToShaderSel__enumvalues = {
0: 'INPUT_COVERAGE',
1: 'INPUT_INNER_COVERAGE',
2: 'INPUT_DEPTH_COVERAGE',
3: 'RAW',
}
INPUT_COVERAGE = 0
INPUT_INNER_COVERAGE = 1
INPUT_DEPTH_COVERAGE = 2
RAW = 3
CovToShaderSel = ctypes.c_uint32 # enum
# values for enumeration 'PC_PERFCNT_SEL'
PC_PERFCNT_SEL__enumvalues = {
0: 'PC_PERF_SC_PC_PTR_SEND0',
1: 'PC_PERF_SC_PC_PTR_VALID0',
2: 'PC_PERF_SC_FPOSG0',
3: 'PC_PERF_SC_FPOSG_WAIT0',
4: 'PC_PERF_SC_WAIT_SYNC0',
5: 'PC_PERF_SC_PQ_FREEZE0',
6: 'PC_PERF_PKR0_FPOSG_EQ1',
7: 'PC_PERF_PKR0_FPOSG_GT1',
8: 'PC_PERF_PKR0_FPOSG_GT16',
9: 'PC_PERF_PKR0_FPOSG_GT64',
10: 'PC_PERF_PKR0_FPOSG_GT128',
11: 'PC_PERF_PKR0_FPOSG_OUT_OF_WAVE',
12: 'PC_PERF_PKR0_NUM_PROBES',
13: 'PC_PERF_PKR0_PRIMS_PER_PROBE_EQ1',
14: 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT1',
15: 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT2',
16: 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT4',
17: 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT8',
18: 'PC_PERF_PKR0_NUM_WAVES',
19: 'PC_PERF_PKR0_PRIMS_PER_WAVE_EQ1',
20: 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT1',
21: 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT2',
22: 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT4',
23: 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT8',
24: 'PC_PERF_PKR0_PROBES_PER_WAVE_EQ1',
25: 'PC_PERF_PKR0_PROBES_PER_WAVE_GT1',
26: 'PC_PERF_PKR0_PROBES_PER_WAVE_GT2',
27: 'PC_PERF_PKR0_PROBES_PER_WAVE_GT4',
28: 'PC_PERF_PKR0_PROBES_PER_WAVE_GT8',
29: 'PC_PERF_PKR0_PRIMS_REUSE',
30: 'PC_PERF_SC_PC_PTR_SEND1',
31: 'PC_PERF_SC_PC_PTR_VALID1',
32: 'PC_PERF_SC_FPOSG1',
33: 'PC_PERF_SC_FPOSG_WAIT1',
34: 'PC_PERF_SC_WAIT_SYNC1',
35: 'PC_PERF_SC_PQ_FREEZE1',
36: 'PC_PERF_PKR1_FPOSG_EQ1',
37: 'PC_PERF_PKR1_FPOSG_GT1',
38: 'PC_PERF_PKR1_FPOSG_GT16',
39: 'PC_PERF_PKR1_FPOSG_GT64',
40: 'PC_PERF_PKR1_FPOSG_GT128',
41: 'PC_PERF_PKR1_FPOSG_OUT_OF_WAVE',
42: 'PC_PERF_PKR1_NUM_PROBES',
43: 'PC_PERF_PKR1_PRIMS_PER_PROBE_EQ1',
44: 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT1',
45: 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT2',
46: 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT4',
47: 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT8',
48: 'PC_PERF_PKR1_NUM_WAVES',
49: 'PC_PERF_PKR1_PRIMS_PER_WAVE_EQ1',
50: 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT1',
51: 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT2',
52: 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT4',
53: 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT8',
54: 'PC_PERF_PKR1_PROBES_PER_WAVE_EQ1',
55: 'PC_PERF_PKR1_PROBES_PER_WAVE_GT1',
56: 'PC_PERF_PKR1_PROBES_PER_WAVE_GT2',
57: 'PC_PERF_PKR1_PROBES_PER_WAVE_GT4',
58: 'PC_PERF_PKR1_PROBES_PER_WAVE_GT8',
59: 'PC_PERF_PKR1_PRIMS_REUSE',
60: 'PC_PERF_SC_PC_PTR_SEND2',
61: 'PC_PERF_SC_PC_PTR_VALID2',
62: 'PC_PERF_SC_FPOSG2',
63: 'PC_PERF_SC_FPOSG_WAIT2',
64: 'PC_PERF_SC_WAIT_SYNC2',
65: 'PC_PERF_SC_PQ_FREEZE2',
66: 'PC_PERF_PKR2_FPOSG_EQ1',
67: 'PC_PERF_PKR2_FPOSG_GT1',
68: 'PC_PERF_PKR2_FPOSG_GT16',
69: 'PC_PERF_PKR2_FPOSG_GT64',
70: 'PC_PERF_PKR2_FPOSG_GT128',
71: 'PC_PERF_PKR2_FPOSG_OUT_OF_WAVE',
72: 'PC_PERF_PKR2_NUM_PROBES',
73: 'PC_PERF_PKR2_PRIMS_PER_PROBE_EQ1',
74: 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT1',
75: 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT2',
76: 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT4',
77: 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT8',
78: 'PC_PERF_PKR2_NUM_WAVES',
79: 'PC_PERF_PKR2_PRIMS_PER_WAVE_EQ1',
80: 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT1',
81: 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT2',
82: 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT4',
83: 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT8',
84: 'PC_PERF_PKR2_PROBES_PER_WAVE_EQ1',
85: 'PC_PERF_PKR2_PROBES_PER_WAVE_GT1',
86: 'PC_PERF_PKR2_PROBES_PER_WAVE_GT2',
87: 'PC_PERF_PKR2_PROBES_PER_WAVE_GT4',
88: 'PC_PERF_PKR2_PROBES_PER_WAVE_GT8',
89: 'PC_PERF_PKR2_PRIMS_REUSE',
90: 'PC_PERF_SC_PC_PTR_SEND3',
91: 'PC_PERF_SC_PC_PTR_VALID3',
92: 'PC_PERF_SC_FPOSG3',
93: 'PC_PERF_SC_FPOSG_WAIT3',
94: 'PC_PERF_SC_WAIT_SYNC3',
95: 'PC_PERF_SC_PQ_FREEZE3',
96: 'PC_PERF_PKR3_FPOSG_EQ1',
97: 'PC_PERF_PKR3_FPOSG_GT1',
98: 'PC_PERF_PKR3_FPOSG_GT16',
99: 'PC_PERF_PKR3_FPOSG_GT64',
100: 'PC_PERF_PKR3_FPOSG_GT128',
101: 'PC_PERF_PKR3_FPOSG_OUT_OF_WAVE',
102: 'PC_PERF_PKR3_NUM_PROBES',
103: 'PC_PERF_PKR3_PRIMS_PER_PROBE_EQ1',
104: 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT1',
105: 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT2',
106: 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT4',
107: 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT8',
108: 'PC_PERF_PKR3_NUM_WAVES',
109: 'PC_PERF_PKR3_PRIMS_PER_WAVE_EQ1',
110: 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT1',
111: 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT2',
112: 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT4',
113: 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT8',
114: 'PC_PERF_PKR3_PROBES_PER_WAVE_EQ1',
115: 'PC_PERF_PKR3_PROBES_PER_WAVE_GT1',
116: 'PC_PERF_PKR3_PROBES_PER_WAVE_GT2',
117: 'PC_PERF_PKR3_PROBES_PER_WAVE_GT4',
118: 'PC_PERF_PKR3_PROBES_PER_WAVE_GT8',
119: 'PC_PERF_PKR3_PRIMS_REUSE',
120: 'PC_PERF_SC_MW_FREEZE',
121: 'PC_PERF_SC_NUM_PROBES',
122: 'PC_PERF_SC_NUM_WAVES',
123: 'PC_PERF_SC_NUM_SPLIT_WAVES',
124: 'PC_PERF_GE_GSDONE',
125: 'PC_PERF_PKR0_GSDONE_WHILE_IDLE',
126: 'PC_PERF_PKR1_GSDONE_WHILE_IDLE',
127: 'PC_PERF_PKR2_GSDONE_WHILE_IDLE',
128: 'PC_PERF_PKR3_GSDONE_WHILE_IDLE',
129: 'PC_PERF_PC_SPI_PROBE_FREEZE',
130: 'PC_PERF_PC_SPI_PROBE_OUT_OF_CREDIT',
131: 'PC_PERF_MW_RTN_ADDR_FREEZE',
132: 'PC_PERF_MW_PROBE_CNT_FREEZE',
133: 'PC_PERF_MW_GL1H_REQ_FREEZE',
134: 'PC_PERF_MW_GL1H_NUM_REQS',
135: 'PC_PERF_MW_DLINE_ALLOC',
136: 'PC_PERF_MW_DLINE_DEALLOC',
137: 'PC_PERF_MW_TAGLINE_ALLOC',
138: 'PC_PERF_MW_TAGLINE_DEALLOC',
139: 'PC_PERF_MW_PHY_DLINE_FULL_STALL',
140: 'PC_PERF_MW_CACHE_CNTL_FULL_STALL',
141: 'PC_PERF_MW_STAMP_LIMIT_STALL',
142: 'PC_PERF_MW_CACHE_MISS',
143: 'PC_PERF_MW_CACHE_HIT',
144: 'PC_PERF_MW_CACHE_REUSE',
145: 'PC_PERF_MW_DEALLOC_HIT',
146: 'PC_PERF_PC_MEM_BANK_CONF0',
147: 'PC_PERF_PC_MEM_BANK_CONF1',
148: 'PC_PERF_PC_LDS_VERTEX_REUSE0',
149: 'PC_PERF_PC_LDS_CNTL_VALID0',
150: 'PC_PERF_PC_LDS_VERTEX_REUSE1',
151: 'PC_PERF_PC_LDS_CNTL_VALID1',
152: 'PC_PERF_GRBM_BUSY',
153: 'PC_PERF_GL1_RTN_CNT_GTE1',
154: 'PC_PERF_GL1_RTN_CNT_GT512',
155: 'PC_PERF_GL1_RTN_CNT_GT768',
156: 'PC_PERF_LWC0_PROBE_ORDER_STALL',
157: 'PC_PERF_LWC0_PC_MEM_READ_STALL',
158: 'PC_PERF_LWC0_PKR2_SA_BDRY_CROSSING',
159: 'PC_PERF_LWC0_PKR3_SA_BDRY_CROSSING',
160: 'PC_PERF_LWC1_PROBE_ORDER_STALL',
161: 'PC_PERF_LWC1_PC_MEM_READ_STALL',
162: 'PC_PERF_LWC1_PKR0_SA_BDRY_CROSSING',
163: 'PC_PERF_LWC1_PKR1_SA_BDRY_CROSSING',
164: 'PC_PERF_NUM_PSWAVE',
}
PC_PERF_SC_PC_PTR_SEND0 = 0
PC_PERF_SC_PC_PTR_VALID0 = 1
PC_PERF_SC_FPOSG0 = 2
PC_PERF_SC_FPOSG_WAIT0 = 3
PC_PERF_SC_WAIT_SYNC0 = 4
PC_PERF_SC_PQ_FREEZE0 = 5
PC_PERF_PKR0_FPOSG_EQ1 = 6
PC_PERF_PKR0_FPOSG_GT1 = 7
PC_PERF_PKR0_FPOSG_GT16 = 8
PC_PERF_PKR0_FPOSG_GT64 = 9
PC_PERF_PKR0_FPOSG_GT128 = 10
PC_PERF_PKR0_FPOSG_OUT_OF_WAVE = 11
PC_PERF_PKR0_NUM_PROBES = 12
PC_PERF_PKR0_PRIMS_PER_PROBE_EQ1 = 13
PC_PERF_PKR0_PRIMS_PER_PROBE_GT1 = 14
PC_PERF_PKR0_PRIMS_PER_PROBE_GT2 = 15
PC_PERF_PKR0_PRIMS_PER_PROBE_GT4 = 16
PC_PERF_PKR0_PRIMS_PER_PROBE_GT8 = 17
PC_PERF_PKR0_NUM_WAVES = 18
PC_PERF_PKR0_PRIMS_PER_WAVE_EQ1 = 19
PC_PERF_PKR0_PRIMS_PER_WAVE_GT1 = 20
PC_PERF_PKR0_PRIMS_PER_WAVE_GT2 = 21
PC_PERF_PKR0_PRIMS_PER_WAVE_GT4 = 22
PC_PERF_PKR0_PRIMS_PER_WAVE_GT8 = 23
PC_PERF_PKR0_PROBES_PER_WAVE_EQ1 = 24
PC_PERF_PKR0_PROBES_PER_WAVE_GT1 = 25
PC_PERF_PKR0_PROBES_PER_WAVE_GT2 = 26
PC_PERF_PKR0_PROBES_PER_WAVE_GT4 = 27
PC_PERF_PKR0_PROBES_PER_WAVE_GT8 = 28
PC_PERF_PKR0_PRIMS_REUSE = 29
PC_PERF_SC_PC_PTR_SEND1 = 30
PC_PERF_SC_PC_PTR_VALID1 = 31
PC_PERF_SC_FPOSG1 = 32
PC_PERF_SC_FPOSG_WAIT1 = 33
PC_PERF_SC_WAIT_SYNC1 = 34
PC_PERF_SC_PQ_FREEZE1 = 35
PC_PERF_PKR1_FPOSG_EQ1 = 36
PC_PERF_PKR1_FPOSG_GT1 = 37
PC_PERF_PKR1_FPOSG_GT16 = 38
PC_PERF_PKR1_FPOSG_GT64 = 39
PC_PERF_PKR1_FPOSG_GT128 = 40
PC_PERF_PKR1_FPOSG_OUT_OF_WAVE = 41
PC_PERF_PKR1_NUM_PROBES = 42
PC_PERF_PKR1_PRIMS_PER_PROBE_EQ1 = 43
PC_PERF_PKR1_PRIMS_PER_PROBE_GT1 = 44
PC_PERF_PKR1_PRIMS_PER_PROBE_GT2 = 45
PC_PERF_PKR1_PRIMS_PER_PROBE_GT4 = 46
PC_PERF_PKR1_PRIMS_PER_PROBE_GT8 = 47
PC_PERF_PKR1_NUM_WAVES = 48
PC_PERF_PKR1_PRIMS_PER_WAVE_EQ1 = 49
PC_PERF_PKR1_PRIMS_PER_WAVE_GT1 = 50
PC_PERF_PKR1_PRIMS_PER_WAVE_GT2 = 51
PC_PERF_PKR1_PRIMS_PER_WAVE_GT4 = 52
PC_PERF_PKR1_PRIMS_PER_WAVE_GT8 = 53
PC_PERF_PKR1_PROBES_PER_WAVE_EQ1 = 54
PC_PERF_PKR1_PROBES_PER_WAVE_GT1 = 55
PC_PERF_PKR1_PROBES_PER_WAVE_GT2 = 56
PC_PERF_PKR1_PROBES_PER_WAVE_GT4 = 57
PC_PERF_PKR1_PROBES_PER_WAVE_GT8 = 58
PC_PERF_PKR1_PRIMS_REUSE = 59
PC_PERF_SC_PC_PTR_SEND2 = 60
PC_PERF_SC_PC_PTR_VALID2 = 61
PC_PERF_SC_FPOSG2 = 62
PC_PERF_SC_FPOSG_WAIT2 = 63
PC_PERF_SC_WAIT_SYNC2 = 64
PC_PERF_SC_PQ_FREEZE2 = 65
PC_PERF_PKR2_FPOSG_EQ1 = 66
PC_PERF_PKR2_FPOSG_GT1 = 67
PC_PERF_PKR2_FPOSG_GT16 = 68
PC_PERF_PKR2_FPOSG_GT64 = 69
PC_PERF_PKR2_FPOSG_GT128 = 70
PC_PERF_PKR2_FPOSG_OUT_OF_WAVE = 71
PC_PERF_PKR2_NUM_PROBES = 72
PC_PERF_PKR2_PRIMS_PER_PROBE_EQ1 = 73
PC_PERF_PKR2_PRIMS_PER_PROBE_GT1 = 74
PC_PERF_PKR2_PRIMS_PER_PROBE_GT2 = 75
PC_PERF_PKR2_PRIMS_PER_PROBE_GT4 = 76
PC_PERF_PKR2_PRIMS_PER_PROBE_GT8 = 77
PC_PERF_PKR2_NUM_WAVES = 78
PC_PERF_PKR2_PRIMS_PER_WAVE_EQ1 = 79
PC_PERF_PKR2_PRIMS_PER_WAVE_GT1 = 80
PC_PERF_PKR2_PRIMS_PER_WAVE_GT2 = 81
PC_PERF_PKR2_PRIMS_PER_WAVE_GT4 = 82
PC_PERF_PKR2_PRIMS_PER_WAVE_GT8 = 83
PC_PERF_PKR2_PROBES_PER_WAVE_EQ1 = 84
PC_PERF_PKR2_PROBES_PER_WAVE_GT1 = 85
PC_PERF_PKR2_PROBES_PER_WAVE_GT2 = 86
PC_PERF_PKR2_PROBES_PER_WAVE_GT4 = 87
PC_PERF_PKR2_PROBES_PER_WAVE_GT8 = 88
PC_PERF_PKR2_PRIMS_REUSE = 89
PC_PERF_SC_PC_PTR_SEND3 = 90
PC_PERF_SC_PC_PTR_VALID3 = 91
PC_PERF_SC_FPOSG3 = 92
PC_PERF_SC_FPOSG_WAIT3 = 93
PC_PERF_SC_WAIT_SYNC3 = 94
PC_PERF_SC_PQ_FREEZE3 = 95
PC_PERF_PKR3_FPOSG_EQ1 = 96
PC_PERF_PKR3_FPOSG_GT1 = 97
PC_PERF_PKR3_FPOSG_GT16 = 98
PC_PERF_PKR3_FPOSG_GT64 = 99
PC_PERF_PKR3_FPOSG_GT128 = 100
PC_PERF_PKR3_FPOSG_OUT_OF_WAVE = 101
PC_PERF_PKR3_NUM_PROBES = 102
PC_PERF_PKR3_PRIMS_PER_PROBE_EQ1 = 103
PC_PERF_PKR3_PRIMS_PER_PROBE_GT1 = 104
PC_PERF_PKR3_PRIMS_PER_PROBE_GT2 = 105
PC_PERF_PKR3_PRIMS_PER_PROBE_GT4 = 106
PC_PERF_PKR3_PRIMS_PER_PROBE_GT8 = 107
PC_PERF_PKR3_NUM_WAVES = 108
PC_PERF_PKR3_PRIMS_PER_WAVE_EQ1 = 109
PC_PERF_PKR3_PRIMS_PER_WAVE_GT1 = 110
PC_PERF_PKR3_PRIMS_PER_WAVE_GT2 = 111
PC_PERF_PKR3_PRIMS_PER_WAVE_GT4 = 112
PC_PERF_PKR3_PRIMS_PER_WAVE_GT8 = 113
PC_PERF_PKR3_PROBES_PER_WAVE_EQ1 = 114
PC_PERF_PKR3_PROBES_PER_WAVE_GT1 = 115
PC_PERF_PKR3_PROBES_PER_WAVE_GT2 = 116
PC_PERF_PKR3_PROBES_PER_WAVE_GT4 = 117
PC_PERF_PKR3_PROBES_PER_WAVE_GT8 = 118
PC_PERF_PKR3_PRIMS_REUSE = 119
PC_PERF_SC_MW_FREEZE = 120
PC_PERF_SC_NUM_PROBES = 121
PC_PERF_SC_NUM_WAVES = 122
PC_PERF_SC_NUM_SPLIT_WAVES = 123
PC_PERF_GE_GSDONE = 124
PC_PERF_PKR0_GSDONE_WHILE_IDLE = 125
PC_PERF_PKR1_GSDONE_WHILE_IDLE = 126
PC_PERF_PKR2_GSDONE_WHILE_IDLE = 127
PC_PERF_PKR3_GSDONE_WHILE_IDLE = 128
PC_PERF_PC_SPI_PROBE_FREEZE = 129
PC_PERF_PC_SPI_PROBE_OUT_OF_CREDIT = 130
PC_PERF_MW_RTN_ADDR_FREEZE = 131
PC_PERF_MW_PROBE_CNT_FREEZE = 132
PC_PERF_MW_GL1H_REQ_FREEZE = 133
PC_PERF_MW_GL1H_NUM_REQS = 134
PC_PERF_MW_DLINE_ALLOC = 135
PC_PERF_MW_DLINE_DEALLOC = 136
PC_PERF_MW_TAGLINE_ALLOC = 137
PC_PERF_MW_TAGLINE_DEALLOC = 138
PC_PERF_MW_PHY_DLINE_FULL_STALL = 139
PC_PERF_MW_CACHE_CNTL_FULL_STALL = 140
PC_PERF_MW_STAMP_LIMIT_STALL = 141
PC_PERF_MW_CACHE_MISS = 142
PC_PERF_MW_CACHE_HIT = 143
PC_PERF_MW_CACHE_REUSE = 144
PC_PERF_MW_DEALLOC_HIT = 145
PC_PERF_PC_MEM_BANK_CONF0 = 146
PC_PERF_PC_MEM_BANK_CONF1 = 147
PC_PERF_PC_LDS_VERTEX_REUSE0 = 148
PC_PERF_PC_LDS_CNTL_VALID0 = 149
PC_PERF_PC_LDS_VERTEX_REUSE1 = 150
PC_PERF_PC_LDS_CNTL_VALID1 = 151
PC_PERF_GRBM_BUSY = 152
PC_PERF_GL1_RTN_CNT_GTE1 = 153
PC_PERF_GL1_RTN_CNT_GT512 = 154
PC_PERF_GL1_RTN_CNT_GT768 = 155
PC_PERF_LWC0_PROBE_ORDER_STALL = 156
PC_PERF_LWC0_PC_MEM_READ_STALL = 157
PC_PERF_LWC0_PKR2_SA_BDRY_CROSSING = 158
PC_PERF_LWC0_PKR3_SA_BDRY_CROSSING = 159
PC_PERF_LWC1_PROBE_ORDER_STALL = 160
PC_PERF_LWC1_PC_MEM_READ_STALL = 161
PC_PERF_LWC1_PKR0_SA_BDRY_CROSSING = 162
PC_PERF_LWC1_PKR1_SA_BDRY_CROSSING = 163
PC_PERF_NUM_PSWAVE = 164
PC_PERFCNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SPI_FOG_MODE'
SPI_FOG_MODE__enumvalues = {
0: 'SPI_FOG_NONE',
1: 'SPI_FOG_EXP',
2: 'SPI_FOG_EXP2',
3: 'SPI_FOG_LINEAR',
}
SPI_FOG_NONE = 0
SPI_FOG_EXP = 1
SPI_FOG_EXP2 = 2
SPI_FOG_LINEAR = 3
SPI_FOG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SPI_LB_WAVES_SELECT'
SPI_LB_WAVES_SELECT__enumvalues = {
0: 'HS_GS',
1: 'PS',
2: 'CS_NA',
3: 'SPI_LB_WAVES_RSVD',
}
HS_GS = 0
PS = 1
CS_NA = 2
SPI_LB_WAVES_RSVD = 3
SPI_LB_WAVES_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'SPI_PERFCNT_SEL'
SPI_PERFCNT_SEL__enumvalues = {
1: 'SPI_PERF_GS_WINDOW_VALID',
2: 'SPI_PERF_GS_BUSY',
3: 'SPI_PERF_GS_CRAWLER_STALL',
4: 'SPI_PERF_GS_EVENT_WAVE',
5: 'SPI_PERF_GS_WAVE',
6: 'SPI_PERF_GS_PERS_UPD_FULL0',
7: 'SPI_PERF_GS_PERS_UPD_FULL1',
8: 'SPI_PERF_GS_FIRST_SUBGRP',
9: 'SPI_PERF_GS_HS_DEALLOC',
10: 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT',
11: 'SPI_PERF_GS_POS0_STALL',
12: 'SPI_PERF_GS_POS1_STALL',
13: 'SPI_PERF_GS_INDX0_STALL',
14: 'SPI_PERF_GS_INDX1_STALL',
15: 'SPI_PERF_GS_PWS_STALL',
16: 'SPI_PERF_GS_GRP_LIFETIME',
17: 'SPI_PERF_GS_WAVE_IN_FLIGHT',
18: 'SPI_PERF_GS_GRP_LIFETIME_SAMPLE',
21: 'SPI_PERF_HS_WINDOW_VALID',
22: 'SPI_PERF_HS_BUSY',
23: 'SPI_PERF_HS_CRAWLER_STALL',
24: 'SPI_PERF_HS_FIRST_WAVE',
26: 'SPI_PERF_HS_EVENT_WAVE',
27: 'SPI_PERF_HS_WAVE',
28: 'SPI_PERF_HS_PERS_UPD_FULL0',
29: 'SPI_PERF_HS_PERS_UPD_FULL1',
30: 'SPI_PERF_HS_PWS_STALL',
31: 'SPI_PERF_HS_WAVE_IN_FLIGHT',
37: 'SPI_PERF_CSGN_WINDOW_VALID',
38: 'SPI_PERF_CSGN_BUSY',
39: 'SPI_PERF_CSGN_NUM_THREADGROUPS',
40: 'SPI_PERF_CSGN_CRAWLER_STALL',
41: 'SPI_PERF_CSGN_EVENT_WAVE',
42: 'SPI_PERF_CSGN_WAVE',
43: 'SPI_PERF_CSGN_PWS_STALL',
44: 'SPI_PERF_CSGN_WAVE_IN_FLIGHT',
45: 'SPI_PERF_CSN_WINDOW_VALID',
46: 'SPI_PERF_CSN_BUSY',
47: 'SPI_PERF_CSN_NUM_THREADGROUPS',
48: 'SPI_PERF_CSN_CRAWLER_STALL',
49: 'SPI_PERF_CSN_EVENT_WAVE',
50: 'SPI_PERF_CSN_WAVE',
51: 'SPI_PERF_CSN_WAVE_IN_FLIGHT',
53: 'SPI_PERF_PS0_WINDOW_VALID',
54: 'SPI_PERF_PS1_WINDOW_VALID',
55: 'SPI_PERF_PS2_WINDOW_VALID',
56: 'SPI_PERF_PS3_WINDOW_VALID',
57: 'SPI_PERF_PS0_BUSY',
58: 'SPI_PERF_PS1_BUSY',
59: 'SPI_PERF_PS2_BUSY',
60: 'SPI_PERF_PS3_BUSY',
61: 'SPI_PERF_PS0_ACTIVE',
62: 'SPI_PERF_PS1_ACTIVE',
63: 'SPI_PERF_PS2_ACTIVE',
64: 'SPI_PERF_PS3_ACTIVE',
65: 'SPI_PERF_PS0_DEALLOC',
66: 'SPI_PERF_PS1_DEALLOC',
67: 'SPI_PERF_PS2_DEALLOC',
68: 'SPI_PERF_PS3_DEALLOC',
69: 'SPI_PERF_PS0_EVENT_WAVE',
70: 'SPI_PERF_PS1_EVENT_WAVE',
71: 'SPI_PERF_PS2_EVENT_WAVE',
72: 'SPI_PERF_PS3_EVENT_WAVE',
73: 'SPI_PERF_PS0_WAVE',
74: 'SPI_PERF_PS1_WAVE',
75: 'SPI_PERF_PS2_WAVE',
76: 'SPI_PERF_PS3_WAVE',
77: 'SPI_PERF_PS0_OPT_WAVE',
78: 'SPI_PERF_PS1_OPT_WAVE',
79: 'SPI_PERF_PS2_OPT_WAVE',
80: 'SPI_PERF_PS3_OPT_WAVE',
81: 'SPI_PERF_PS0_PRIM_BIN0',
82: 'SPI_PERF_PS1_PRIM_BIN0',
83: 'SPI_PERF_PS2_PRIM_BIN0',
84: 'SPI_PERF_PS3_PRIM_BIN0',
85: 'SPI_PERF_PS0_PRIM_BIN1',
86: 'SPI_PERF_PS1_PRIM_BIN1',
87: 'SPI_PERF_PS2_PRIM_BIN1',
88: 'SPI_PERF_PS3_PRIM_BIN1',
89: 'SPI_PERF_PS0_CRAWLER_STALL',
90: 'SPI_PERF_PS1_CRAWLER_STALL',
91: 'SPI_PERF_PS2_CRAWLER_STALL',
92: 'SPI_PERF_PS3_CRAWLER_STALL',
93: 'SPI_PERF_PS_PERS_UPD_FULL0',
94: 'SPI_PERF_PS_PERS_UPD_FULL1',
95: 'SPI_PERF_PS0_2_WAVE_GROUPS',
96: 'SPI_PERF_PS1_2_WAVE_GROUPS',
97: 'SPI_PERF_PS2_2_WAVE_GROUPS',
98: 'SPI_PERF_PS3_2_WAVE_GROUPS',
99: 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY',
100: 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY',
101: 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY',
102: 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY',
103: 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS',
104: 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS',
105: 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS',
106: 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS',
107: 'SPI_PERF_PS_PWS_STALL',
108: 'SPI_PERF_PS0_LDS_DONE_FULL',
109: 'SPI_PERF_PS1_LDS_DONE_FULL',
110: 'SPI_PERF_PS2_LDS_DONE_FULL',
111: 'SPI_PERF_PS3_LDS_DONE_FULL',
112: 'SPI_PERF_PS0_DEALLOC_FULL',
113: 'SPI_PERF_PS1_DEALLOC_FULL',
114: 'SPI_PERF_PS2_DEALLOC_FULL',
115: 'SPI_PERF_PS3_DEALLOC_FULL',
116: 'SPI_PERF_PS0_WAVE_IN_FLIGHT',
117: 'SPI_PERF_PS1_WAVE_IN_FLIGHT',
118: 'SPI_PERF_PS2_WAVE_IN_FLIGHT',
119: 'SPI_PERF_PS3_WAVE_IN_FLIGHT',
133: 'SPI_PERF_RA_GS_LDS_OCCUPANCY',
134: 'SPI_PERF_RA_GS_VGPR_OCCUPANCY',
135: 'SPI_PERF_RA_PS_LDS_OCCUPANCY',
136: 'SPI_PERF_RA_PS_VGPR_OCCUPANCY',
137: 'SPI_PERF_RA_SPI_THROTTLE',
138: 'SPI_PERF_RA_PH_THROTTLE',
139: 'SPI_PERF_RA_PC_PROBE_STALL_PS',
140: 'SPI_PERF_RA_PC_PSWAVE_STALL_PS',
141: 'SPI_PERF_RA_PIPE_REQ_BIN2',
142: 'SPI_PERF_RA_TASK_REQ_BIN3',
143: 'SPI_PERF_RA_WR_CTL_FULL',
144: 'SPI_PERF_RA_REQ_NO_ALLOC',
145: 'SPI_PERF_RA_REQ_NO_ALLOC_PS',
146: 'SPI_PERF_RA_REQ_NO_ALLOC_GS',
147: 'SPI_PERF_RA_REQ_NO_ALLOC_HS',
148: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG',
149: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN',
150: 'SPI_PERF_RA_RES_STALL_PS',
151: 'SPI_PERF_RA_RES_STALL_GS',
152: 'SPI_PERF_RA_RES_STALL_HS',
153: 'SPI_PERF_RA_RES_STALL_CSG',
154: 'SPI_PERF_RA_RES_STALL_CSN',
155: 'SPI_PERF_RA_TMP_STALL_PS',
156: 'SPI_PERF_RA_TMP_STALL_GS',
157: 'SPI_PERF_RA_TMP_STALL_HS',
158: 'SPI_PERF_RA_TMP_STALL_CSG',
159: 'SPI_PERF_RA_TMP_STALL_CSN',
160: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS',
161: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS',
162: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS',
163: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG',
164: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN',
165: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS',
166: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS',
167: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS',
168: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG',
169: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN',
170: 'SPI_PERF_RA_LDS_CU_FULL_PS',
171: 'SPI_PERF_RA_LDS_CU_FULL_HS',
172: 'SPI_PERF_RA_LDS_CU_FULL_GS',
173: 'SPI_PERF_RA_LDS_CU_FULL_CSG',
174: 'SPI_PERF_RA_LDS_CU_FULL_CSN',
175: 'SPI_PERF_RA_BAR_CU_FULL_PS',
176: 'SPI_PERF_RA_BAR_CU_FULL_GS',
177: 'SPI_PERF_RA_BAR_CU_FULL_HS',
178: 'SPI_PERF_RA_BAR_CU_FULL_CSG',
179: 'SPI_PERF_RA_BAR_CU_FULL_CSN',
180: 'SPI_PERF_RA_BULKY_CU_FULL_CSG',
181: 'SPI_PERF_RA_BULKY_CU_FULL_CSN',
182: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG',
183: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN',
184: 'SPI_PERF_RA_WVLIM_STALL_PS',
185: 'SPI_PERF_RA_WVLIM_STALL_GS',
186: 'SPI_PERF_RA_WVLIM_STALL_HS',
187: 'SPI_PERF_RA_WVLIM_STALL_CSG',
188: 'SPI_PERF_RA_WVLIM_STALL_CSN',
189: 'SPI_PERF_RA_GS_LOCK',
190: 'SPI_PERF_RA_HS_LOCK',
191: 'SPI_PERF_RA_CSG_LOCK',
192: 'SPI_PERF_RA_CSN_LOCK',
193: 'SPI_PERF_RA_RSV_UPD',
194: 'SPI_PERF_RA_PRE_ALLOC_STALL',
195: 'SPI_PERF_RA_GFX_UNDER_TUNNEL',
196: 'SPI_PERF_RA_CSC_UNDER_TUNNEL',
197: 'SPI_PERF_RA_WVALLOC_STALL',
198: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS',
199: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS',
200: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS',
201: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS',
202: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS',
203: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS',
204: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS',
205: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS',
206: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS',
207: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS',
208: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS',
209: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS',
210: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG',
211: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG',
212: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG',
213: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG',
214: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN',
215: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN',
216: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN',
217: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN',
218: 'SPI_PERF_EXP_ARB_COL_CNT',
219: 'SPI_PERF_EXP_ARB_POS_CNT',
220: 'SPI_PERF_EXP_ARB_GDS_CNT',
221: 'SPI_PERF_EXP_ARB_IDX_CNT',
222: 'SPI_PERF_EXP_WITH_CONFLICT',
223: 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR',
224: 'SPI_PERF_GS_EXP_DONE',
225: 'SPI_PERF_PS_EXP_DONE',
226: 'SPI_PERF_PS_EXP_ARB_CONFLICT',
227: 'SPI_PERF_GS_SCBD_IDX_CLEANUP',
228: 'SPI_PERF_GS_SCBD_POS_CLEANUP',
229: 'SPI_PERF_PS_EXP_ALLOC',
230: 'SPI_PERF_PS0_WAVEID_STARVED',
231: 'SPI_PERF_PS1_WAVEID_STARVED',
232: 'SPI_PERF_PS2_WAVEID_STARVED',
233: 'SPI_PERF_PS3_WAVEID_STARVED',
234: 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT',
235: 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT',
236: 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT',
237: 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT',
238: 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS',
239: 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS',
240: 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS',
241: 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS',
242: 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS',
243: 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS',
244: 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS',
245: 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS',
246: 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS',
247: 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS',
248: 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS',
249: 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS',
250: 'SPI_PERF_NUM_EXPGRANT_EXPORTS',
251: 'SPI_PERF_GS_ALLOC_IDX',
252: 'SPI_PERF_GS_ALLOC_POS',
253: 'SPI_PERF_PIX_ALLOC_PEND_CNT',
254: 'SPI_PERF_EXPORT_SCB0_STALL',
255: 'SPI_PERF_EXPORT_SCB1_STALL',
256: 'SPI_PERF_EXPORT_SCB2_STALL',
257: 'SPI_PERF_EXPORT_SCB3_STALL',
258: 'SPI_PERF_EXPORT_DB0_STALL',
259: 'SPI_PERF_EXPORT_DB1_STALL',
260: 'SPI_PERF_EXPORT_DB2_STALL',
261: 'SPI_PERF_EXPORT_DB3_STALL',
262: 'SPI_PERF_EXPORT_DB4_STALL',
263: 'SPI_PERF_EXPORT_DB5_STALL',
264: 'SPI_PERF_EXPORT_DB6_STALL',
265: 'SPI_PERF_EXPORT_DB7_STALL',
266: 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC',
267: 'SPI_PERF_GS_NGG_STALL_MSG_VAL',
268: 'SPI_PERF_SWC_PS_WR',
269: 'SPI_PERF_SWC_GS_WR',
270: 'SPI_PERF_SWC_HS_WR',
271: 'SPI_PERF_SWC_CSGN_WR',
272: 'SPI_PERF_SWC_CSN_WR',
273: 'SPI_PERF_VWC_PS_WR',
274: 'SPI_PERF_VWC_ES_WR',
275: 'SPI_PERF_VWC_GS_WR',
276: 'SPI_PERF_VWC_LS_WR',
277: 'SPI_PERF_VWC_HS_WR',
278: 'SPI_PERF_VWC_CSGN_WR',
279: 'SPI_PERF_VWC_CSN_WR',
280: 'SPI_PERF_EXP_THROT_UPSTEP',
281: 'SPI_PERF_EXP_THROT_DOWNSTEP',
282: 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED',
283: 'SPI_PERF_BUSY',
284: 'SPI_PERF_ALL_PS_WAVE',
285: 'SPI_PERF_ALL_PS_WAVE_IN_FLIGHT',
286: 'SPI_PERF_ALL_WAVE',
287: 'SPI_PERF_ALL_WAVE_IN_FLIGHT',
288: 'SPI_PERF_RA_REQ_ALLOC',
289: 'SPI_PERF_VGPR_INIT',
290: 'SPI_PERF_SGPR_INIT',
291: 'SPI_PERF_VGPR_ALLOC_LEVEL',
292: 'SPI_PERF_LDS_ALLOC_LEVEL',
293: 'SPI_PERF_GFX_TEMP_ALLOC_LEVEL',
294: 'SPI_PERF_CSG_TEMP_ALLOC_LEVEL',
295: 'SPI_PERF_CSN_TEMP_ALLOC_LEVEL',
296: 'SPI_PERF_ALL_WAVE_RESTORED',
297: 'SPI_PERF_ALL_WAVE_SAVED',
298: 'SPI_PERF_ALL_WAVE_W32',
299: 'SPI_PERF_ALL_WAVE_W64',
300: 'SPI_PERF_ALL_WAVE_ITEMS',
301: 'SPI_PERF_ALL_WAVE_ITEMS_W32',
302: 'SPI_PERF_ALL_WAVE_ITEMS_W64',
303: 'SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_STALL',
304: 'SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_LEVEL',
305: 'SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_STALL',
306: 'SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_CU_LEVEL',
}
SPI_PERF_GS_WINDOW_VALID = 1
SPI_PERF_GS_BUSY = 2
SPI_PERF_GS_CRAWLER_STALL = 3
SPI_PERF_GS_EVENT_WAVE = 4
SPI_PERF_GS_WAVE = 5
SPI_PERF_GS_PERS_UPD_FULL0 = 6
SPI_PERF_GS_PERS_UPD_FULL1 = 7
SPI_PERF_GS_FIRST_SUBGRP = 8
SPI_PERF_GS_HS_DEALLOC = 9
SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 10
SPI_PERF_GS_POS0_STALL = 11
SPI_PERF_GS_POS1_STALL = 12
SPI_PERF_GS_INDX0_STALL = 13
SPI_PERF_GS_INDX1_STALL = 14
SPI_PERF_GS_PWS_STALL = 15
SPI_PERF_GS_GRP_LIFETIME = 16
SPI_PERF_GS_WAVE_IN_FLIGHT = 17
SPI_PERF_GS_GRP_LIFETIME_SAMPLE = 18
SPI_PERF_HS_WINDOW_VALID = 21
SPI_PERF_HS_BUSY = 22
SPI_PERF_HS_CRAWLER_STALL = 23
SPI_PERF_HS_FIRST_WAVE = 24
SPI_PERF_HS_EVENT_WAVE = 26
SPI_PERF_HS_WAVE = 27
SPI_PERF_HS_PERS_UPD_FULL0 = 28
SPI_PERF_HS_PERS_UPD_FULL1 = 29
SPI_PERF_HS_PWS_STALL = 30
SPI_PERF_HS_WAVE_IN_FLIGHT = 31
SPI_PERF_CSGN_WINDOW_VALID = 37
SPI_PERF_CSGN_BUSY = 38
SPI_PERF_CSGN_NUM_THREADGROUPS = 39
SPI_PERF_CSGN_CRAWLER_STALL = 40
SPI_PERF_CSGN_EVENT_WAVE = 41
SPI_PERF_CSGN_WAVE = 42
SPI_PERF_CSGN_PWS_STALL = 43
SPI_PERF_CSGN_WAVE_IN_FLIGHT = 44
SPI_PERF_CSN_WINDOW_VALID = 45
SPI_PERF_CSN_BUSY = 46
SPI_PERF_CSN_NUM_THREADGROUPS = 47
SPI_PERF_CSN_CRAWLER_STALL = 48
SPI_PERF_CSN_EVENT_WAVE = 49
SPI_PERF_CSN_WAVE = 50
SPI_PERF_CSN_WAVE_IN_FLIGHT = 51
SPI_PERF_PS0_WINDOW_VALID = 53
SPI_PERF_PS1_WINDOW_VALID = 54
SPI_PERF_PS2_WINDOW_VALID = 55
SPI_PERF_PS3_WINDOW_VALID = 56
SPI_PERF_PS0_BUSY = 57
SPI_PERF_PS1_BUSY = 58
SPI_PERF_PS2_BUSY = 59
SPI_PERF_PS3_BUSY = 60
SPI_PERF_PS0_ACTIVE = 61
SPI_PERF_PS1_ACTIVE = 62
SPI_PERF_PS2_ACTIVE = 63
SPI_PERF_PS3_ACTIVE = 64
SPI_PERF_PS0_DEALLOC = 65
SPI_PERF_PS1_DEALLOC = 66
SPI_PERF_PS2_DEALLOC = 67
SPI_PERF_PS3_DEALLOC = 68
SPI_PERF_PS0_EVENT_WAVE = 69
SPI_PERF_PS1_EVENT_WAVE = 70
SPI_PERF_PS2_EVENT_WAVE = 71
SPI_PERF_PS3_EVENT_WAVE = 72
SPI_PERF_PS0_WAVE = 73
SPI_PERF_PS1_WAVE = 74
SPI_PERF_PS2_WAVE = 75
SPI_PERF_PS3_WAVE = 76
SPI_PERF_PS0_OPT_WAVE = 77
SPI_PERF_PS1_OPT_WAVE = 78
SPI_PERF_PS2_OPT_WAVE = 79
SPI_PERF_PS3_OPT_WAVE = 80
SPI_PERF_PS0_PRIM_BIN0 = 81
SPI_PERF_PS1_PRIM_BIN0 = 82
SPI_PERF_PS2_PRIM_BIN0 = 83
SPI_PERF_PS3_PRIM_BIN0 = 84
SPI_PERF_PS0_PRIM_BIN1 = 85
SPI_PERF_PS1_PRIM_BIN1 = 86
SPI_PERF_PS2_PRIM_BIN1 = 87
SPI_PERF_PS3_PRIM_BIN1 = 88
SPI_PERF_PS0_CRAWLER_STALL = 89
SPI_PERF_PS1_CRAWLER_STALL = 90
SPI_PERF_PS2_CRAWLER_STALL = 91
SPI_PERF_PS3_CRAWLER_STALL = 92
SPI_PERF_PS_PERS_UPD_FULL0 = 93
SPI_PERF_PS_PERS_UPD_FULL1 = 94
SPI_PERF_PS0_2_WAVE_GROUPS = 95
SPI_PERF_PS1_2_WAVE_GROUPS = 96
SPI_PERF_PS2_2_WAVE_GROUPS = 97
SPI_PERF_PS3_2_WAVE_GROUPS = 98
SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 99
SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 100
SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 101
SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 102
SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 103
SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 104
SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 105
SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 106
SPI_PERF_PS_PWS_STALL = 107
SPI_PERF_PS0_LDS_DONE_FULL = 108
SPI_PERF_PS1_LDS_DONE_FULL = 109
SPI_PERF_PS2_LDS_DONE_FULL = 110
SPI_PERF_PS3_LDS_DONE_FULL = 111
SPI_PERF_PS0_DEALLOC_FULL = 112
SPI_PERF_PS1_DEALLOC_FULL = 113
SPI_PERF_PS2_DEALLOC_FULL = 114
SPI_PERF_PS3_DEALLOC_FULL = 115
SPI_PERF_PS0_WAVE_IN_FLIGHT = 116
SPI_PERF_PS1_WAVE_IN_FLIGHT = 117
SPI_PERF_PS2_WAVE_IN_FLIGHT = 118
SPI_PERF_PS3_WAVE_IN_FLIGHT = 119
SPI_PERF_RA_GS_LDS_OCCUPANCY = 133
SPI_PERF_RA_GS_VGPR_OCCUPANCY = 134
SPI_PERF_RA_PS_LDS_OCCUPANCY = 135
SPI_PERF_RA_PS_VGPR_OCCUPANCY = 136
SPI_PERF_RA_SPI_THROTTLE = 137
SPI_PERF_RA_PH_THROTTLE = 138
SPI_PERF_RA_PC_PROBE_STALL_PS = 139
SPI_PERF_RA_PC_PSWAVE_STALL_PS = 140
SPI_PERF_RA_PIPE_REQ_BIN2 = 141
SPI_PERF_RA_TASK_REQ_BIN3 = 142
SPI_PERF_RA_WR_CTL_FULL = 143
SPI_PERF_RA_REQ_NO_ALLOC = 144
SPI_PERF_RA_REQ_NO_ALLOC_PS = 145
SPI_PERF_RA_REQ_NO_ALLOC_GS = 146
SPI_PERF_RA_REQ_NO_ALLOC_HS = 147
SPI_PERF_RA_REQ_NO_ALLOC_CSG = 148
SPI_PERF_RA_REQ_NO_ALLOC_CSN = 149
SPI_PERF_RA_RES_STALL_PS = 150
SPI_PERF_RA_RES_STALL_GS = 151
SPI_PERF_RA_RES_STALL_HS = 152
SPI_PERF_RA_RES_STALL_CSG = 153
SPI_PERF_RA_RES_STALL_CSN = 154
SPI_PERF_RA_TMP_STALL_PS = 155
SPI_PERF_RA_TMP_STALL_GS = 156
SPI_PERF_RA_TMP_STALL_HS = 157
SPI_PERF_RA_TMP_STALL_CSG = 158
SPI_PERF_RA_TMP_STALL_CSN = 159
SPI_PERF_RA_WAVE_SIMD_FULL_PS = 160
SPI_PERF_RA_WAVE_SIMD_FULL_GS = 161
SPI_PERF_RA_WAVE_SIMD_FULL_HS = 162
SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 163
SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 164
SPI_PERF_RA_VGPR_SIMD_FULL_PS = 165
SPI_PERF_RA_VGPR_SIMD_FULL_GS = 166
SPI_PERF_RA_VGPR_SIMD_FULL_HS = 167
SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 168
SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 169
SPI_PERF_RA_LDS_CU_FULL_PS = 170
SPI_PERF_RA_LDS_CU_FULL_HS = 171
SPI_PERF_RA_LDS_CU_FULL_GS = 172
SPI_PERF_RA_LDS_CU_FULL_CSG = 173
SPI_PERF_RA_LDS_CU_FULL_CSN = 174
SPI_PERF_RA_BAR_CU_FULL_PS = 175
SPI_PERF_RA_BAR_CU_FULL_GS = 176
SPI_PERF_RA_BAR_CU_FULL_HS = 177
SPI_PERF_RA_BAR_CU_FULL_CSG = 178
SPI_PERF_RA_BAR_CU_FULL_CSN = 179
SPI_PERF_RA_BULKY_CU_FULL_CSG = 180
SPI_PERF_RA_BULKY_CU_FULL_CSN = 181
SPI_PERF_RA_TGLIM_CU_FULL_CSG = 182
SPI_PERF_RA_TGLIM_CU_FULL_CSN = 183
SPI_PERF_RA_WVLIM_STALL_PS = 184
SPI_PERF_RA_WVLIM_STALL_GS = 185
SPI_PERF_RA_WVLIM_STALL_HS = 186
SPI_PERF_RA_WVLIM_STALL_CSG = 187
SPI_PERF_RA_WVLIM_STALL_CSN = 188
SPI_PERF_RA_GS_LOCK = 189
SPI_PERF_RA_HS_LOCK = 190
SPI_PERF_RA_CSG_LOCK = 191
SPI_PERF_RA_CSN_LOCK = 192
SPI_PERF_RA_RSV_UPD = 193
SPI_PERF_RA_PRE_ALLOC_STALL = 194
SPI_PERF_RA_GFX_UNDER_TUNNEL = 195
SPI_PERF_RA_CSC_UNDER_TUNNEL = 196
SPI_PERF_RA_WVALLOC_STALL = 197
SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 198
SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 199
SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 200
SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 201
SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 202
SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 203
SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 204
SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 205
SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 206
SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 207
SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 208
SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 209
SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 210
SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 211
SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 212
SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 213
SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 214
SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 215
SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 216
SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 217
SPI_PERF_EXP_ARB_COL_CNT = 218
SPI_PERF_EXP_ARB_POS_CNT = 219
SPI_PERF_EXP_ARB_GDS_CNT = 220
SPI_PERF_EXP_ARB_IDX_CNT = 221
SPI_PERF_EXP_WITH_CONFLICT = 222
SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 223
SPI_PERF_GS_EXP_DONE = 224
SPI_PERF_PS_EXP_DONE = 225
SPI_PERF_PS_EXP_ARB_CONFLICT = 226
SPI_PERF_GS_SCBD_IDX_CLEANUP = 227
SPI_PERF_GS_SCBD_POS_CLEANUP = 228
SPI_PERF_PS_EXP_ALLOC = 229
SPI_PERF_PS0_WAVEID_STARVED = 230
SPI_PERF_PS1_WAVEID_STARVED = 231
SPI_PERF_PS2_WAVEID_STARVED = 232
SPI_PERF_PS3_WAVEID_STARVED = 233
SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 234
SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 235
SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 236
SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 237
SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 238
SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 239
SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 240
SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 241
SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 242
SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 243
SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 244
SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 245
SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 246
SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 247
SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 248
SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 249
SPI_PERF_NUM_EXPGRANT_EXPORTS = 250
SPI_PERF_GS_ALLOC_IDX = 251
SPI_PERF_GS_ALLOC_POS = 252
SPI_PERF_PIX_ALLOC_PEND_CNT = 253
SPI_PERF_EXPORT_SCB0_STALL = 254
SPI_PERF_EXPORT_SCB1_STALL = 255
SPI_PERF_EXPORT_SCB2_STALL = 256
SPI_PERF_EXPORT_SCB3_STALL = 257
SPI_PERF_EXPORT_DB0_STALL = 258
SPI_PERF_EXPORT_DB1_STALL = 259
SPI_PERF_EXPORT_DB2_STALL = 260
SPI_PERF_EXPORT_DB3_STALL = 261
SPI_PERF_EXPORT_DB4_STALL = 262
SPI_PERF_EXPORT_DB5_STALL = 263
SPI_PERF_EXPORT_DB6_STALL = 264
SPI_PERF_EXPORT_DB7_STALL = 265
SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 266
SPI_PERF_GS_NGG_STALL_MSG_VAL = 267
SPI_PERF_SWC_PS_WR = 268
SPI_PERF_SWC_GS_WR = 269
SPI_PERF_SWC_HS_WR = 270
SPI_PERF_SWC_CSGN_WR = 271
SPI_PERF_SWC_CSN_WR = 272
SPI_PERF_VWC_PS_WR = 273
SPI_PERF_VWC_ES_WR = 274
SPI_PERF_VWC_GS_WR = 275
SPI_PERF_VWC_LS_WR = 276
SPI_PERF_VWC_HS_WR = 277
SPI_PERF_VWC_CSGN_WR = 278
SPI_PERF_VWC_CSN_WR = 279
SPI_PERF_EXP_THROT_UPSTEP = 280
SPI_PERF_EXP_THROT_DOWNSTEP = 281
SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 282
SPI_PERF_BUSY = 283
SPI_PERF_ALL_PS_WAVE = 284
SPI_PERF_ALL_PS_WAVE_IN_FLIGHT = 285
SPI_PERF_ALL_WAVE = 286
SPI_PERF_ALL_WAVE_IN_FLIGHT = 287
SPI_PERF_RA_REQ_ALLOC = 288
SPI_PERF_VGPR_INIT = 289
SPI_PERF_SGPR_INIT = 290
SPI_PERF_VGPR_ALLOC_LEVEL = 291
SPI_PERF_LDS_ALLOC_LEVEL = 292
SPI_PERF_GFX_TEMP_ALLOC_LEVEL = 293
SPI_PERF_CSG_TEMP_ALLOC_LEVEL = 294
SPI_PERF_CSN_TEMP_ALLOC_LEVEL = 295
SPI_PERF_ALL_WAVE_RESTORED = 296
SPI_PERF_ALL_WAVE_SAVED = 297
SPI_PERF_ALL_WAVE_W32 = 298
SPI_PERF_ALL_WAVE_W64 = 299
SPI_PERF_ALL_WAVE_ITEMS = 300
SPI_PERF_ALL_WAVE_ITEMS_W32 = 301
SPI_PERF_ALL_WAVE_ITEMS_W64 = 302
SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_STALL = 303
SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_LEVEL = 304
SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_STALL = 305
SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_CU_LEVEL = 306
SPI_PERFCNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE'
SPI_PNT_SPRITE_OVERRIDE__enumvalues = {
0: 'SPI_PNT_SPRITE_SEL_0',
1: 'SPI_PNT_SPRITE_SEL_1',
2: 'SPI_PNT_SPRITE_SEL_S',
3: 'SPI_PNT_SPRITE_SEL_T',
4: 'SPI_PNT_SPRITE_SEL_NONE',
}
SPI_PNT_SPRITE_SEL_0 = 0
SPI_PNT_SPRITE_SEL_1 = 1
SPI_PNT_SPRITE_SEL_S = 2
SPI_PNT_SPRITE_SEL_T = 3
SPI_PNT_SPRITE_SEL_NONE = 4
SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'SPI_PS_LDS_GROUP_SIZE'
SPI_PS_LDS_GROUP_SIZE__enumvalues = {
0: 'SPI_PS_LDS_GROUP_1',
1: 'SPI_PS_LDS_GROUP_2',
2: 'SPI_PS_LDS_GROUP_4',
}
SPI_PS_LDS_GROUP_1 = 0
SPI_PS_LDS_GROUP_2 = 1
SPI_PS_LDS_GROUP_4 = 2
SPI_PS_LDS_GROUP_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'SPI_SAMPLE_CNTL'
SPI_SAMPLE_CNTL__enumvalues = {
0: 'CENTROIDS_ONLY',
1: 'CENTERS_ONLY',
2: 'CENTROIDS_AND_CENTERS',
3: 'UNDEF',
}
CENTROIDS_ONLY = 0
CENTERS_ONLY = 1
CENTROIDS_AND_CENTERS = 2
UNDEF = 3
SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'SPI_SHADER_EX_FORMAT'
SPI_SHADER_EX_FORMAT__enumvalues = {
0: 'SPI_SHADER_ZERO',
1: 'SPI_SHADER_32_R',
2: 'SPI_SHADER_32_GR',
3: 'SPI_SHADER_32_AR',
4: 'SPI_SHADER_FP16_ABGR',
5: 'SPI_SHADER_UNORM16_ABGR',
6: 'SPI_SHADER_SNORM16_ABGR',
7: 'SPI_SHADER_UINT16_ABGR',
8: 'SPI_SHADER_SINT16_ABGR',
9: 'SPI_SHADER_32_ABGR',
}
SPI_SHADER_ZERO = 0
SPI_SHADER_32_R = 1
SPI_SHADER_32_GR = 2
SPI_SHADER_32_AR = 3
SPI_SHADER_FP16_ABGR = 4
SPI_SHADER_UNORM16_ABGR = 5
SPI_SHADER_SNORM16_ABGR = 6
SPI_SHADER_UINT16_ABGR = 7
SPI_SHADER_SINT16_ABGR = 8
SPI_SHADER_32_ABGR = 9
SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'SPI_SHADER_FORMAT'
SPI_SHADER_FORMAT__enumvalues = {
0: 'SPI_SHADER_NONE',
1: 'SPI_SHADER_1COMP',
2: 'SPI_SHADER_2COMP',
3: 'SPI_SHADER_4COMPRESS',
4: 'SPI_SHADER_4COMP',
}
SPI_SHADER_NONE = 0
SPI_SHADER_1COMP = 1
SPI_SHADER_2COMP = 2
SPI_SHADER_4COMPRESS = 3
SPI_SHADER_4COMP = 4
SPI_SHADER_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'SH_MEM_ADDRESS_MODE'
SH_MEM_ADDRESS_MODE__enumvalues = {
0: 'SH_MEM_ADDRESS_MODE_64',
1: 'SH_MEM_ADDRESS_MODE_32',
}
SH_MEM_ADDRESS_MODE_64 = 0
SH_MEM_ADDRESS_MODE_32 = 1
SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SH_MEM_ALIGNMENT_MODE'
SH_MEM_ALIGNMENT_MODE__enumvalues = {
0: 'SH_MEM_ALIGNMENT_MODE_DWORD',
1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT',
2: 'SH_MEM_ALIGNMENT_MODE_STRICT',
3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED',
}
SH_MEM_ALIGNMENT_MODE_DWORD = 0
SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1
SH_MEM_ALIGNMENT_MODE_STRICT = 2
SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3
SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SQG_PERF_SEL'
SQG_PERF_SEL__enumvalues = {
0: 'SQG_PERF_SEL_NONE',
1: 'SQG_PERF_SEL_MSG_BUS_BUSY',
2: 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY',
3: 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY',
4: 'SQG_PERF_SEL_EXP_BUS0_BUSY',
5: 'SQG_PERF_SEL_EXP_BUS1_BUSY',
6: 'SQG_PERF_SEL_TTRACE_WRITE_DATA',
7: 'SQG_PERF_SEL_TTRACE_STALL',
8: 'SQG_PERF_SEL_TTRACE_LOST_PACKETS',
9: 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH',
10: 'SQG_PERF_SEL_EVENTS',
11: 'SQG_PERF_SEL_WAVES_RESTORED',
12: 'SQG_PERF_SEL_WAVES_SAVED',
13: 'SQG_PERF_SEL_ACCUM_PREV',
14: 'SQG_PERF_SEL_CYCLES',
15: 'SQG_PERF_SEL_BUSY_CYCLES',
16: 'SQG_PERF_SEL_WAVE_CYCLES',
17: 'SQG_PERF_SEL_MSG',
18: 'SQG_PERF_SEL_MSG_INTERRUPT',
19: 'SQG_PERF_SEL_WAVES',
20: 'SQG_PERF_SEL_WAVES_32',
21: 'SQG_PERF_SEL_WAVES_64',
22: 'SQG_PERF_SEL_LEVEL_WAVES',
23: 'SQG_PERF_SEL_ITEMS',
24: 'SQG_PERF_SEL_WAVE32_ITEMS',
25: 'SQG_PERF_SEL_WAVE64_ITEMS',
26: 'SQG_PERF_SEL_PS_QUADS',
27: 'SQG_PERF_SEL_WAVES_EQ_64',
28: 'SQG_PERF_SEL_WAVES_EQ_32',
29: 'SQG_PERF_SEL_WAVES_LT_64',
30: 'SQG_PERF_SEL_WAVES_LT_48',
31: 'SQG_PERF_SEL_WAVES_LT_32',
32: 'SQG_PERF_SEL_WAVES_LT_16',
33: 'SQG_PERF_SEL_REFCLKS',
34: 'SQG_PERF_SEL_WAVES_WGP_TAKEOVER',
35: 'SQG_PERF_SEL_WAVES_DYN_VGPR',
36: 'SQG_PERF_SEL_ITEMS_PS',
37: 'SQG_PERF_SEL_ITEMS_GS',
38: 'SQG_PERF_SEL_ITEMS_HS',
39: 'SQG_PERF_SEL_ITEMS_CS',
40: 'SQG_PERF_SEL_WAVES_VEC32',
41: 'SQG_PERF_SEL_WAVES_PS_VEC32',
42: 'SQG_PERF_SEL_WAVES_GS_VEC32',
43: 'SQG_PERF_SEL_WAVES_HS_VEC32',
44: 'SQG_PERF_SEL_WAVES_CS_VEC32',
45: 'SQG_PERF_SEL_LEVEL_WGP_ACTIVE',
46: 'SQG_PERF_SEL_DUMMY_LAST',
}
SQG_PERF_SEL_NONE = 0
SQG_PERF_SEL_MSG_BUS_BUSY = 1
SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 2
SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 3
SQG_PERF_SEL_EXP_BUS0_BUSY = 4
SQG_PERF_SEL_EXP_BUS1_BUSY = 5
SQG_PERF_SEL_TTRACE_WRITE_DATA = 6
SQG_PERF_SEL_TTRACE_STALL = 7
SQG_PERF_SEL_TTRACE_LOST_PACKETS = 8
SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 9
SQG_PERF_SEL_EVENTS = 10
SQG_PERF_SEL_WAVES_RESTORED = 11
SQG_PERF_SEL_WAVES_SAVED = 12
SQG_PERF_SEL_ACCUM_PREV = 13
SQG_PERF_SEL_CYCLES = 14
SQG_PERF_SEL_BUSY_CYCLES = 15
SQG_PERF_SEL_WAVE_CYCLES = 16
SQG_PERF_SEL_MSG = 17
SQG_PERF_SEL_MSG_INTERRUPT = 18
SQG_PERF_SEL_WAVES = 19
SQG_PERF_SEL_WAVES_32 = 20
SQG_PERF_SEL_WAVES_64 = 21
SQG_PERF_SEL_LEVEL_WAVES = 22
SQG_PERF_SEL_ITEMS = 23
SQG_PERF_SEL_WAVE32_ITEMS = 24
SQG_PERF_SEL_WAVE64_ITEMS = 25
SQG_PERF_SEL_PS_QUADS = 26
SQG_PERF_SEL_WAVES_EQ_64 = 27
SQG_PERF_SEL_WAVES_EQ_32 = 28
SQG_PERF_SEL_WAVES_LT_64 = 29
SQG_PERF_SEL_WAVES_LT_48 = 30
SQG_PERF_SEL_WAVES_LT_32 = 31
SQG_PERF_SEL_WAVES_LT_16 = 32
SQG_PERF_SEL_REFCLKS = 33
SQG_PERF_SEL_WAVES_WGP_TAKEOVER = 34
SQG_PERF_SEL_WAVES_DYN_VGPR = 35
SQG_PERF_SEL_ITEMS_PS = 36
SQG_PERF_SEL_ITEMS_GS = 37
SQG_PERF_SEL_ITEMS_HS = 38
SQG_PERF_SEL_ITEMS_CS = 39
SQG_PERF_SEL_WAVES_VEC32 = 40
SQG_PERF_SEL_WAVES_PS_VEC32 = 41
SQG_PERF_SEL_WAVES_GS_VEC32 = 42
SQG_PERF_SEL_WAVES_HS_VEC32 = 43
SQG_PERF_SEL_WAVES_CS_VEC32 = 44
SQG_PERF_SEL_LEVEL_WGP_ACTIVE = 45
SQG_PERF_SEL_DUMMY_LAST = 46
SQG_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SQ_CAC_POWER_SEL'
SQ_CAC_POWER_SEL__enumvalues = {
0: 'SQ_CAC_POWER_VALU',
1: 'SQ_CAC_POWER_VALU0',
2: 'SQ_CAC_POWER_VALU1',
3: 'SQ_CAC_POWER_VALU2',
4: 'SQ_CAC_POWER_GPR_RD',
5: 'SQ_CAC_POWER_GPR_WR',
6: 'SQ_CAC_POWER_LDS_BUSY',
7: 'SQ_CAC_POWER_ALU_BUSY',
8: 'SQ_CAC_POWER_TEX_BUSY',
}
SQ_CAC_POWER_VALU = 0
SQ_CAC_POWER_VALU0 = 1
SQ_CAC_POWER_VALU1 = 2
SQ_CAC_POWER_VALU2 = 3
SQ_CAC_POWER_GPR_RD = 4
SQ_CAC_POWER_GPR_WR = 5
SQ_CAC_POWER_LDS_BUSY = 6
SQ_CAC_POWER_ALU_BUSY = 7
SQ_CAC_POWER_TEX_BUSY = 8
SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SQ_EDC_INFO_SOURCE'
SQ_EDC_INFO_SOURCE__enumvalues = {
0: 'SQ_EDC_INFO_SOURCE_INVALID',
1: 'SQ_EDC_INFO_SOURCE_INST',
2: 'SQ_EDC_INFO_SOURCE_SGPR',
3: 'SQ_EDC_INFO_SOURCE_VGPR',
4: 'SQ_EDC_INFO_SOURCE_LDS',
5: 'SQ_EDC_INFO_SOURCE_GDS',
6: 'SQ_EDC_INFO_SOURCE_TA',
}
SQ_EDC_INFO_SOURCE_INVALID = 0
SQ_EDC_INFO_SOURCE_INST = 1
SQ_EDC_INFO_SOURCE_SGPR = 2
SQ_EDC_INFO_SOURCE_VGPR = 3
SQ_EDC_INFO_SOURCE_LDS = 4
SQ_EDC_INFO_SOURCE_GDS = 5
SQ_EDC_INFO_SOURCE_TA = 6
SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_IBUF_ST'
SQ_IBUF_ST__enumvalues = {
0: 'SQ_IBUF_IB_IDLE',
1: 'SQ_IBUF_IB_INI_WAIT_GNT',
2: 'SQ_IBUF_IB_INI_WAIT_DRET',
3: 'SQ_IBUF_IB_LE_4DW',
4: 'SQ_IBUF_IB_WAIT_DRET',
5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET',
6: 'SQ_IBUF_IB_DRET',
7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT',
}
SQ_IBUF_IB_IDLE = 0
SQ_IBUF_IB_INI_WAIT_GNT = 1
SQ_IBUF_IB_INI_WAIT_DRET = 2
SQ_IBUF_IB_LE_4DW = 3
SQ_IBUF_IB_WAIT_DRET = 4
SQ_IBUF_IB_EMPTY_WAIT_DRET = 5
SQ_IBUF_IB_DRET = 6
SQ_IBUF_IB_EMPTY_WAIT_GNT = 7
SQ_IBUF_ST = ctypes.c_uint32 # enum
# values for enumeration 'SQ_IMG_FILTER_TYPE'
SQ_IMG_FILTER_TYPE__enumvalues = {
0: 'SQ_IMG_FILTER_MODE_BLEND',
1: 'SQ_IMG_FILTER_MODE_MIN',
2: 'SQ_IMG_FILTER_MODE_MAX',
}
SQ_IMG_FILTER_MODE_BLEND = 0
SQ_IMG_FILTER_MODE_MIN = 1
SQ_IMG_FILTER_MODE_MAX = 2
SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_IND_CMD_CMD'
SQ_IND_CMD_CMD__enumvalues = {
0: 'SQ_IND_CMD_CMD_NULL',
1: 'SQ_IND_CMD_CMD_SETHALT',
2: 'SQ_IND_CMD_CMD_SAVECTX',
3: 'SQ_IND_CMD_CMD_KILL',
4: 'SQ_IND_CMD_CMD_TRAP_AFTER_INST',
5: 'SQ_IND_CMD_CMD_TRAP',
6: 'SQ_IND_CMD_CMD_SET_SYS_PRIO',
7: 'SQ_IND_CMD_CMD_SETFATALHALT',
8: 'SQ_IND_CMD_CMD_SINGLE_STEP',
}
SQ_IND_CMD_CMD_NULL = 0
SQ_IND_CMD_CMD_SETHALT = 1
SQ_IND_CMD_CMD_SAVECTX = 2
SQ_IND_CMD_CMD_KILL = 3
SQ_IND_CMD_CMD_TRAP_AFTER_INST = 4
SQ_IND_CMD_CMD_TRAP = 5
SQ_IND_CMD_CMD_SET_SYS_PRIO = 6
SQ_IND_CMD_CMD_SETFATALHALT = 7
SQ_IND_CMD_CMD_SINGLE_STEP = 8
SQ_IND_CMD_CMD = ctypes.c_uint32 # enum
# values for enumeration 'SQ_IND_CMD_MODE'
SQ_IND_CMD_MODE__enumvalues = {
0: 'SQ_IND_CMD_MODE_SINGLE',
1: 'SQ_IND_CMD_MODE_BROADCAST',
2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE',
3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE',
4: 'SQ_IND_CMD_MODE_BROADCAST_ME',
}
SQ_IND_CMD_MODE_SINGLE = 0
SQ_IND_CMD_MODE_BROADCAST = 1
SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2
SQ_IND_CMD_MODE_BROADCAST_PIPE = 3
SQ_IND_CMD_MODE_BROADCAST_ME = 4
SQ_IND_CMD_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_INST_STR_ST'
SQ_INST_STR_ST__enumvalues = {
0: 'SQ_INST_STR_IB_WAVE_NORML',
1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV',
2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV',
3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV',
4: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT',
5: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT',
}
SQ_INST_STR_IB_WAVE_NORML = 0
SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1
SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2
SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3
SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 4
SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 5
SQ_INST_STR_ST = ctypes.c_uint32 # enum
# values for enumeration 'SQ_INST_TYPE'
SQ_INST_TYPE__enumvalues = {
0: 'SQ_INST_TYPE_VALU',
1: 'SQ_INST_TYPE_SCALAR',
2: 'SQ_INST_TYPE_TEX',
3: 'SQ_INST_TYPE_LDS',
4: 'SQ_INST_TYPE_LDS_DIRECT',
5: 'SQ_INST_TYPE_EXP',
6: 'SQ_INST_TYPE_MSG',
7: 'SQ_INST_TYPE_BARRIER',
8: 'SQ_INST_TYPE_BRANCH_NOT_TAKEN',
9: 'SQ_INST_TYPE_BRANCH_TAKEN',
10: 'SQ_INST_TYPE_JUMP',
11: 'SQ_INST_TYPE_OTHER',
12: 'SQ_INST_TYPE_NONE',
13: 'SQ_INST_TYPE_DUAL_VALU',
14: 'SQ_INST_TYPE_FLAT',
15: 'SQ_INST_TYPE_VALU_MATRIX',
}
SQ_INST_TYPE_VALU = 0
SQ_INST_TYPE_SCALAR = 1
SQ_INST_TYPE_TEX = 2
SQ_INST_TYPE_LDS = 3
SQ_INST_TYPE_LDS_DIRECT = 4
SQ_INST_TYPE_EXP = 5
SQ_INST_TYPE_MSG = 6
SQ_INST_TYPE_BARRIER = 7
SQ_INST_TYPE_BRANCH_NOT_TAKEN = 8
SQ_INST_TYPE_BRANCH_TAKEN = 9
SQ_INST_TYPE_JUMP = 10
SQ_INST_TYPE_OTHER = 11
SQ_INST_TYPE_NONE = 12
SQ_INST_TYPE_DUAL_VALU = 13
SQ_INST_TYPE_FLAT = 14
SQ_INST_TYPE_VALU_MATRIX = 15
SQ_INST_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_LLC_CTL'
SQ_LLC_CTL__enumvalues = {
0: 'SQ_LLC_0',
1: 'SQ_LLC_1',
2: 'SQ_LLC_RSVD_2',
3: 'SQ_LLC_BYPASS',
}
SQ_LLC_0 = 0
SQ_LLC_1 = 1
SQ_LLC_RSVD_2 = 2
SQ_LLC_BYPASS = 3
SQ_LLC_CTL = ctypes.c_uint32 # enum
# values for enumeration 'SQ_NO_INST_ISSUE'
SQ_NO_INST_ISSUE__enumvalues = {
0: 'SQ_NO_INST_ISSUE_NO_INSTS',
1: 'SQ_NO_INST_ISSUE_ALU_DEP',
2: 'SQ_NO_INST_ISSUE_S_WAITCNT',
3: 'SQ_NO_INST_ISSUE_NO_ARB_WIN',
4: 'SQ_NO_INST_ISSUE_SLEEP_WAIT',
5: 'SQ_NO_INST_ISSUE_BARRIER_WAIT',
6: 'SQ_NO_INST_ISSUE_OTHER',
7: 'SQ_NO_INST_ISSUE_INTERNAL',
}
SQ_NO_INST_ISSUE_NO_INSTS = 0
SQ_NO_INST_ISSUE_ALU_DEP = 1
SQ_NO_INST_ISSUE_S_WAITCNT = 2
SQ_NO_INST_ISSUE_NO_ARB_WIN = 3
SQ_NO_INST_ISSUE_SLEEP_WAIT = 4
SQ_NO_INST_ISSUE_BARRIER_WAIT = 5
SQ_NO_INST_ISSUE_OTHER = 6
SQ_NO_INST_ISSUE_INTERNAL = 7
SQ_NO_INST_ISSUE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_OOB_SELECT'
SQ_OOB_SELECT__enumvalues = {
0: 'SQ_OOB_INDEX_AND_OFFSET',
1: 'SQ_OOB_INDEX_ONLY',
2: 'SQ_OOB_NUM_RECORDS_0',
3: 'SQ_OOB_COMPLETE',
}
SQ_OOB_INDEX_AND_OFFSET = 0
SQ_OOB_INDEX_ONLY = 1
SQ_OOB_NUM_RECORDS_0 = 2
SQ_OOB_COMPLETE = 3
SQ_OOB_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'SQ_PERF_SEL'
SQ_PERF_SEL__enumvalues = {
0: 'SQ_PERF_SEL_NONE',
1: 'SQ_PERF_SEL_ACCUM_PREV',
2: 'SQ_PERF_SEL_CYCLES',
3: 'SQ_PERF_SEL_BUSY_CYCLES',
4: 'SQ_PERF_SEL_WAVES',
5: 'SQ_PERF_SEL_WAVES_32',
6: 'SQ_PERF_SEL_WAVES_64',
7: 'SQ_PERF_SEL_LEVEL_WAVES',
8: 'SQ_PERF_SEL_ITEMS',
9: 'SQ_PERF_SEL_WAVE32_ITEMS',
10: 'SQ_PERF_SEL_WAVE64_ITEMS',
11: 'SQ_PERF_SEL_PS_QUADS',
12: 'SQ_PERF_SEL_EVENTS',
13: 'SQ_PERF_SEL_WAVES_EQ_32',
14: 'SQ_PERF_SEL_WAVES_EQ_64',
15: 'SQ_PERF_SEL_WAVES_LT_64',
16: 'SQ_PERF_SEL_WAVES_LT_48',
17: 'SQ_PERF_SEL_WAVES_LT_32',
18: 'SQ_PERF_SEL_WAVES_LT_16',
19: 'SQ_PERF_SEL_WAVES_RESTORED',
20: 'SQ_PERF_SEL_WAVES_SAVED',
21: 'SQ_PERF_SEL_MSG',
22: 'SQ_PERF_SEL_MSG_INTERRUPT',
23: 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH',
24: 'SQ_PERF_SEL_WAVE_CYCLES',
25: 'SQ_PERF_SEL_WAVE_READY',
26: 'SQ_PERF_SEL_WAIT_INST_ANY',
27: 'SQ_PERF_SEL_WAIT_ANY',
28: 'SQ_PERF_SEL_WAIT_CNT_ANY',
29: 'SQ_PERF_SEL_WAIT_CNT_LOAD',
30: 'SQ_PERF_SEL_WAIT_CNT_STORE',
31: 'SQ_PERF_SEL_WAIT_TTRACE',
32: 'SQ_PERF_SEL_WAIT_IFETCH',
33: 'SQ_PERF_SEL_WAIT_BARRIER',
34: 'SQ_PERF_SEL_WAIT_EXP_ALLOC',
35: 'SQ_PERF_SEL_WAIT_SLEEP',
36: 'SQ_PERF_SEL_WAIT_DELAY_ALU',
37: 'SQ_PERF_SEL_WAIT_DEPCTR',
38: 'SQ_PERF_SEL_WAIT_OTHER',
39: 'SQ_PERF_SEL_INSTS_ALL',
40: 'SQ_PERF_SEL_INSTS_BRANCH',
41: 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN',
42: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN',
43: 'SQ_PERF_SEL_INSTS_EXP',
44: 'SQ_PERF_SEL_INSTS_FLAT',
45: 'SQ_PERF_SEL_INSTS_LDS',
46: 'SQ_PERF_SEL_INSTS_SALU',
47: 'SQ_PERF_SEL_INSTS_SMEM',
48: 'SQ_PERF_SEL_INSTS_SMEM_NORM',
49: 'SQ_PERF_SEL_INSTS_SENDMSG',
50: 'SQ_PERF_SEL_INSTS_VALU',
51: 'SQ_PERF_SEL_INSTS_VALU_TRANS32',
52: 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC',
53: 'SQ_PERF_SEL_INSTS_TEX',
54: 'SQ_PERF_SEL_INSTS_TEX_LOAD',
55: 'SQ_PERF_SEL_INSTS_TEX_STORE',
56: 'SQ_PERF_SEL_INSTS_DELAY_ALU',
57: 'SQ_PERF_SEL_INSTS_INTERNAL',
58: 'SQ_PERF_SEL_INSTS_VEC32',
59: 'SQ_PERF_SEL_INSTS_VEC32_FLAT',
60: 'SQ_PERF_SEL_INSTS_VEC32_LDS',
61: 'SQ_PERF_SEL_INSTS_VEC32_VALU',
62: 'SQ_PERF_SEL_VEC32_INSTS_EXP',
63: 'SQ_PERF_SEL_INSTS_VEC32_VALU_TRANS32',
64: 'SQ_PERF_SEL_INSTS_VEC32_VALU_NO_COEXEC',
65: 'SQ_PERF_SEL_INSTS_VEC32_TEX',
66: 'SQ_PERF_SEL_INSTS_VEC32_TEX_LOAD',
67: 'SQ_PERF_SEL_INSTS_VEC32_TEX_STORE',
68: 'SQ_PERF_SEL_ITEM_CYCLES_VALU',
69: 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES',
70: 'SQ_PERF_SEL_WAVE32_INSTS',
71: 'SQ_PERF_SEL_WAVE64_INSTS',
72: 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED',
73: 'SQ_PERF_SEL_WAVE64_HALF_SKIP',
74: 'SQ_PERF_SEL_INST_LEVEL_EXP',
75: 'SQ_PERF_SEL_INST_LEVEL_LDS',
76: 'SQ_PERF_SEL_INST_LEVEL_SMEM',
77: 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD',
78: 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE',
79: 'SQ_PERF_SEL_IFETCH_REQS',
80: 'SQ_PERF_SEL_IFETCH_LEVEL',
81: 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL',
82: 'SQ_PERF_SEL_VALU_SGATHER_STALL',
83: 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL',
84: 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL',
85: 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL',
86: 'SQ_PERF_SEL_SALU_SGATHER_STALL',
87: 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL',
88: 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL',
89: 'SQ_PERF_SEL_INST_ISSUE_SMEM_STALL',
90: 'SQ_PERF_SEL_INST_ISSUE_ALL_STALL',
91: 'SQ_PERF_SEL_INST_ISSUE_VALU_STALL',
92: 'SQ_PERF_SEL_INST_ISSUE_SALU_STALL',
93: 'SQ_PERF_SEL_INST_ISSUE_TEX_STALL',
94: 'SQ_PERF_SEL_INST_ISSUE_LDS_STALL',
96: 'SQ_PERF_SEL_INST_ISSUE_EXP_STALL',
97: 'SQ_PERF_SEL_INST_WAITCNT_STALL',
98: 'SQ_PERF_SEL_INST_BARRIER_STALL',
99: 'SQ_PERF_SEL_INST_CYCLES_VALU',
100: 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32',
101: 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC',
102: 'SQ_PERF_SEL_INST_CYCLES_VMEM',
103: 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD',
104: 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE',
105: 'SQ_PERF_SEL_INST_CYCLES_LDS',
106: 'SQ_PERF_SEL_INST_CYCLES_TEX',
107: 'SQ_PERF_SEL_INST_CYCLES_FLAT',
108: 'SQ_PERF_SEL_INST_CYCLES_EXP',
109: 'SQ_PERF_SEL_VALU_STARVE',
110: 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL',
111: 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL',
112: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL',
113: 'SQ_PERF_SEL_VMEM_BUS_ACTIVE',
114: 'SQ_PERF_SEL_VMEM_BUS_STALL',
115: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL',
116: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL',
117: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL',
118: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL',
119: 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY',
120: 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY',
121: 'SQ_PERF_SEL_SALU_PIPE_STALL',
122: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES',
123: 'SQ_PERF_SEL_MSG_BUS_BUSY',
124: 'SQ_PERF_SEL_EXP_REQ_BUS_STALL',
125: 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY',
126: 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY',
127: 'SQ_PERF_SEL_EXP_BUS0_BUSY',
128: 'SQ_PERF_SEL_EXP_BUS1_BUSY',
129: 'SQ_PERF_SEL_INST_CACHE_REQ_STALL',
130: 'SQ_PERF_SEL_USER0',
131: 'SQ_PERF_SEL_USER1',
132: 'SQ_PERF_SEL_USER2',
133: 'SQ_PERF_SEL_USER3',
134: 'SQ_PERF_SEL_USER4',
135: 'SQ_PERF_SEL_USER5',
136: 'SQ_PERF_SEL_USER6',
137: 'SQ_PERF_SEL_USER7',
138: 'SQ_PERF_SEL_USER8',
139: 'SQ_PERF_SEL_USER9',
140: 'SQ_PERF_SEL_USER10',
141: 'SQ_PERF_SEL_USER11',
142: 'SQ_PERF_SEL_USER12',
143: 'SQ_PERF_SEL_USER13',
144: 'SQ_PERF_SEL_USER14',
145: 'SQ_PERF_SEL_USER15',
146: 'SQ_PERF_SEL_USER_LEVEL0',
147: 'SQ_PERF_SEL_USER_LEVEL1',
148: 'SQ_PERF_SEL_USER_LEVEL2',
149: 'SQ_PERF_SEL_USER_LEVEL3',
150: 'SQ_PERF_SEL_USER_LEVEL4',
151: 'SQ_PERF_SEL_USER_LEVEL5',
152: 'SQ_PERF_SEL_USER_LEVEL6',
153: 'SQ_PERF_SEL_USER_LEVEL7',
154: 'SQ_PERF_SEL_USER_LEVEL8',
155: 'SQ_PERF_SEL_USER_LEVEL9',
156: 'SQ_PERF_SEL_USER_LEVEL10',
157: 'SQ_PERF_SEL_USER_LEVEL11',
158: 'SQ_PERF_SEL_USER_LEVEL12',
159: 'SQ_PERF_SEL_USER_LEVEL13',
160: 'SQ_PERF_SEL_USER_LEVEL14',
161: 'SQ_PERF_SEL_USER_LEVEL15',
162: 'SQ_PERF_SEL_VALU_RETURN_SDST',
163: 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT',
164: 'SQ_PERF_SEL_INSTS_VALU_TRANS',
165: 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD',
166: 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD',
167: 'SQ_PERF_SEL_INSTS_VEC32_LDS_PARAM_LOAD',
168: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64',
169: 'SQ_PERF_SEL_INSTS_VALU_VINTERP',
170: 'SQ_PERF_SEL_INSTS_VEC32_VALU_VINTERP',
171: 'SQ_PERF_SEL_OVERFLOW_PREV',
172: 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32',
173: 'SQ_PERF_SEL_INSTS_VALU_1_PASS',
174: 'SQ_PERF_SEL_INSTS_VALU_2_PASS',
175: 'SQ_PERF_SEL_INSTS_VALU_4_PASS',
176: 'SQ_PERF_SEL_INSTS_VALU_DP',
177: 'SQ_PERF_SEL_SP_CONST_CYCLES',
178: 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES',
179: 'SQ_PERF_SEL_ITEMS_VALU',
180: 'SQ_PERF_SEL_ITEMS_MAX_VALU',
181: 'SQ_PERF_SEL_ITEM_CYCLES_VMEM',
182: 'SQ_PERF_SEL_INSTS_DELAY_ALU_COISSUE',
183: 'SQ_PERF_SEL_INSTS_FLAT_LOAD',
184: 'SQ_PERF_SEL_INSTS_FLAT_STORE',
185: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_16BIT',
186: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_32BIT',
187: 'SQ_PERF_SEL_INSTS_NON_VALU_EXEC_SKIPPED',
188: 'SQ_PERF_SEL_INSTS_BARRIER_LOCK',
189: 'SQ_PERF_SEL_INSTS_WAKEUP',
190: 'SQ_PERF_SEL_IS_CACHE_REQ',
191: 'SQ_PERF_SEL_INSTS_SALU_PS',
192: 'SQ_PERF_SEL_INSTS_SALU_GS',
193: 'SQ_PERF_SEL_INSTS_SALU_HS',
194: 'SQ_PERF_SEL_INSTS_SALU_CS',
195: 'SQ_PERF_SEL_INSTS_SMEM_PS',
196: 'SQ_PERF_SEL_INSTS_SMEM_GS',
197: 'SQ_PERF_SEL_INSTS_SMEM_HS',
198: 'SQ_PERF_SEL_INSTS_SMEM_CS',
199: 'SQ_PERF_SEL_INSTS_VEC32_TEX_PS',
200: 'SQ_PERF_SEL_INSTS_VEC32_TEX_GS',
201: 'SQ_PERF_SEL_INSTS_VEC32_TEX_HS',
202: 'SQ_PERF_SEL_INSTS_VEC32_TEX_CS',
203: 'SQ_PERF_SEL_INSTS_VEC32_VALU_PS',
204: 'SQ_PERF_SEL_INSTS_VEC32_VALU_GS',
205: 'SQ_PERF_SEL_INSTS_VEC32_VALU_HS',
206: 'SQ_PERF_SEL_INSTS_VEC32_VALU_CS',
207: 'SQ_PERF_SEL_WAIT_CNT_SAMPLE',
209: 'SQ_PERF_SEL_WAIT_CNT_KM',
210: 'SQ_PERF_SEL_WAIT_CNT_DS',
211: 'SQ_PERF_SEL_WAIT_CNT_EXP',
212: 'SQ_PERF_SEL_INSTS_SALU_FLOAT',
213: 'SQ_PERF_SEL_INSTS_VGPR_ALLOC',
214: 'SQ_PERF_SEL_INSTS_VGPR_ALLOC_FAIL',
215: 'SQ_PERF_SEL_INSTS_LOCK',
216: 'SQ_PERF_SEL_INSTS_VALU_COISSUE',
217: 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_LOAD',
218: 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_STORE',
219: 'SQ_PERF_SEL_IS_CACHE_MISS',
220: 'SQ_PERF_SEL_IS_CACHE_DUP_MISS',
221: 'SQ_PERF_SEL_INST_CYCLES_VMEM_ATOMIC',
222: 'SQ_PERF_SEL_INSTS_TEX_BLOCK_LOAD',
224: 'SQ_PERF_SEL_INSTS_TEX_SAMPLE',
225: 'SQ_PERF_SEL_INSTS_TEX_ATOMIC_RTN',
226: 'SQ_PERF_SEL_INSTS_TEX_BLOCK_STORE',
227: 'SQ_PERF_SEL_INSTS_TEX_ATOMIC_NORTN',
228: 'SQ_PERF_SEL_INSTS_GLOBAL_SCRATCH',
229: 'SQ_PERF_SEL_INSTS_WMMA_LOAD',
230: 'SQ_PERF_SEL_INSTS_FLAT_ATOMIC',
231: 'SQ_PERF_SEL_INSTS_EXP_MRT',
232: 'SQ_PERF_SEL_INSTS_EXP_Z',
233: 'SQ_PERF_SEL_INSTS_VEC32_VALU_WMMA',
234: 'SQ_PERF_SEL_INSTS_VEC32_LDS_LOAD',
235: 'SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_RTN',
236: 'SQ_PERF_SEL_INSTS_VEC32_LDS_STORE',
237: 'SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_NORTN',
239: 'SQ_PERF_SEL_INSTS_VEC32_LDS_OTHER',
241: 'SQ_PERF_SEL_INSTS_VEC32_TEX_SAMPLE',
242: 'SQ_PERF_SEL_INSTS_VEC32_TEX_ATOMIC',
243: 'SQ_PERF_SEL_INSTS_VEC32_FLAT_LOAD',
244: 'SQ_PERF_SEL_INSTS_VEC32_FLAT_STORE',
245: 'SQ_PERF_SEL_INSTS_VEC32_FLAT_ATOMIC',
246: 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH',
247: 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_LOAD',
248: 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_STORE',
249: 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_ATOMIC',
250: 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS',
251: 'SQ_PERF_SEL_DUMMY_END',
287: 'SQ_PERF_SEL_DUMMY_LAST',
288: 'SQC_PERF_SEL_LDS_BANK_CONFLICT',
289: 'SQC_PERF_SEL_LDS_ADDR_CONFLICT',
290: 'SQC_PERF_SEL_LDS_UNALIGNED_STALL',
291: 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS',
292: 'SQC_PERF_SEL_LDS_ATOMIC_RETURN',
293: 'SQC_PERF_SEL_LDS_IDX_ACTIVE',
294: 'SQC_PERF_SEL_LDS_ADDR_STALL',
295: 'SQC_PERF_SEL_LDS_ADDR_ACTIVE',
296: 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD',
297: 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD',
298: 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL',
299: 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES',
300: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES',
301: 'SQC_PERF_SEL_ICACHE_REQ',
302: 'SQC_PERF_SEL_ICACHE_HITS',
303: 'SQC_PERF_SEL_ICACHE_MISSES',
304: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE',
305: 'SQC_PERF_SEL_ICACHE_INVAL_INST',
306: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC',
307: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL',
308: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL',
309: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL',
310: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL',
311: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL',
312: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB',
313: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB',
314: 'SQC_PERF_SEL_TC_REQ',
315: 'SQC_PERF_SEL_TC_INST_REQ',
316: 'SQC_PERF_SEL_TC_DATA_READ_REQ',
317: 'SQC_PERF_SEL_TC_STALL',
318: 'SQC_PERF_SEL_TC_STARVE',
319: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT',
320: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB',
321: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED',
322: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX',
323: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT',
324: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES',
325: 'SQC_PERF_SEL_DCACHE_REQ',
326: 'SQC_PERF_SEL_DCACHE_HITS',
327: 'SQC_PERF_SEL_DCACHE_MISSES',
328: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE',
329: 'SQC_PERF_SEL_DCACHE_INVAL_INST',
330: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC',
331: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ',
332: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT',
333: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB',
334: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED',
335: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX',
336: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT',
337: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT',
338: 'SQC_PERF_SEL_DCACHE_REQ_READ_1',
339: 'SQC_PERF_SEL_DCACHE_REQ_READ_2',
340: 'SQC_PERF_SEL_DCACHE_REQ_READ_4',
341: 'SQC_PERF_SEL_DCACHE_REQ_READ_8',
342: 'SQC_PERF_SEL_DCACHE_REQ_READ_16',
343: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE',
344: 'SQC_PERF_SEL_SQ_DCACHE_REQS',
345: 'SQC_PERF_SEL_DCACHE_FLAT_REQ',
346: 'SQC_PERF_SEL_TD_VGPR_BUSY',
347: 'SQC_PERF_SEL_LDS_VGPR_BUSY',
348: 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL',
349: 'SQC_PERF_SEL_ICACHE_GCR',
350: 'SQC_PERF_SEL_ICACHE_GCR_HITS',
351: 'SQC_PERF_SEL_DCACHE_GCR',
352: 'SQC_PERF_SEL_DCACHE_GCR_HITS',
353: 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE',
354: 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE',
355: 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL',
356: 'SQC_PERF_SEL_ICACHE_PREFETCH_REQ_CACHELINES',
357: 'SQC_PERF_SEL_DCACHE_PREFETCH_REQ_CACHELINES',
358: 'SQC_PERF_SEL_ICACHE_PREFETCH_MISSES',
359: 'SQC_PERF_SEL_DCACHE_PREFETCH_MISSES',
360: 'SQC_PERF_SEL_LDS_BANKCONF_LOAD_CNT',
361: 'SQC_PERF_SEL_LDS_BANKCONF_STORE_CNT',
362: 'SQC_PERF_SEL_LDS_BANKCONF_ATOMIC_CNT',
363: 'SQC_PERF_SEL_LDS_ACTIVE_LOAD_CNT',
364: 'SQC_PERF_SEL_LDS_ACTIVE_STORE_CNT',
365: 'SQC_PERF_SEL_LDS_ACTIVE_ATOMIC_CNT',
366: 'SQC_PERF_SEL_LDS_STORE_DWORDS',
367: 'SQC_PERF_SEL_LDS_LOAD_DWORDS',
368: 'SQC_PERF_SEL_LDS_ATOMIC_DWORDS',
369: 'SQC_PERF_SEL_LDS_LDS_EXECUTION_STALL',
370: 'SQC_PERF_SEL_DUMMY_LAST',
448: 'SP_PERF_SEL_DST_BUF_ALLOC_STALL',
449: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS',
450: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI',
451: 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY',
452: 'SP_PERF_SEL_DST_BUF_ODD_DIRTY',
453: 'SP_PERF_SEL_SRC_CACHE_HIT_B0',
454: 'SP_PERF_SEL_SRC_CACHE_HIT_B1',
455: 'SP_PERF_SEL_SRC_CACHE_HIT_B2',
456: 'SP_PERF_SEL_SRC_CACHE_HIT_B3',
457: 'SP_PERF_SEL_SRC_CACHE_PROBE_B0',
458: 'SP_PERF_SEL_SRC_CACHE_PROBE_B1',
459: 'SP_PERF_SEL_SRC_CACHE_PROBE_B2',
460: 'SP_PERF_SEL_SRC_CACHE_PROBE_B3',
461: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0',
462: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1',
463: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2',
464: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3',
465: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0',
466: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1',
467: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2',
468: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3',
469: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0',
470: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1',
471: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2',
472: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3',
473: 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL',
474: 'SP_PERF_SEL_VALU_OPERAND',
475: 'SP_PERF_SEL_VALU_VGPR_OPERAND',
476: 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF',
477: 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE',
478: 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS',
479: 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL',
480: 'SP_PERF_SEL_VALU_STALL',
481: 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY',
482: 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY',
483: 'SP_PERF_SEL_VALU_STALL_VDST_FWD',
484: 'SP_PERF_SEL_VALU_STALL_SDST_FWD',
485: 'SP_PERF_SEL_VALU_STALL_DST_STALL',
486: 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY',
487: 'SP_PERF_SEL_VGPR_VMEM_RD',
488: 'SP_PERF_SEL_VGPR_EXP_RD',
489: 'SP_PERF_SEL_VGPR_SPI_WR',
490: 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR',
491: 'SP_PERF_SEL_VGPR_WR',
492: 'SP_PERF_SEL_VGPR_RD',
493: 'SP_PERF_SEL_VGPR_WR_KILL',
494: 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_EXP',
495: 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_LDS',
496: 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_TEX',
497: 'SP_PERF_SEL_DUMMY_LAST',
511: 'SQ_PERF_SEL_NONE2',
}
SQ_PERF_SEL_NONE = 0
SQ_PERF_SEL_ACCUM_PREV = 1
SQ_PERF_SEL_CYCLES = 2
SQ_PERF_SEL_BUSY_CYCLES = 3
SQ_PERF_SEL_WAVES = 4
SQ_PERF_SEL_WAVES_32 = 5
SQ_PERF_SEL_WAVES_64 = 6
SQ_PERF_SEL_LEVEL_WAVES = 7
SQ_PERF_SEL_ITEMS = 8
SQ_PERF_SEL_WAVE32_ITEMS = 9
SQ_PERF_SEL_WAVE64_ITEMS = 10
SQ_PERF_SEL_PS_QUADS = 11
SQ_PERF_SEL_EVENTS = 12
SQ_PERF_SEL_WAVES_EQ_32 = 13
SQ_PERF_SEL_WAVES_EQ_64 = 14
SQ_PERF_SEL_WAVES_LT_64 = 15
SQ_PERF_SEL_WAVES_LT_48 = 16
SQ_PERF_SEL_WAVES_LT_32 = 17
SQ_PERF_SEL_WAVES_LT_16 = 18
SQ_PERF_SEL_WAVES_RESTORED = 19
SQ_PERF_SEL_WAVES_SAVED = 20
SQ_PERF_SEL_MSG = 21
SQ_PERF_SEL_MSG_INTERRUPT = 22
SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 23
SQ_PERF_SEL_WAVE_CYCLES = 24
SQ_PERF_SEL_WAVE_READY = 25
SQ_PERF_SEL_WAIT_INST_ANY = 26
SQ_PERF_SEL_WAIT_ANY = 27
SQ_PERF_SEL_WAIT_CNT_ANY = 28
SQ_PERF_SEL_WAIT_CNT_LOAD = 29
SQ_PERF_SEL_WAIT_CNT_STORE = 30
SQ_PERF_SEL_WAIT_TTRACE = 31
SQ_PERF_SEL_WAIT_IFETCH = 32
SQ_PERF_SEL_WAIT_BARRIER = 33
SQ_PERF_SEL_WAIT_EXP_ALLOC = 34
SQ_PERF_SEL_WAIT_SLEEP = 35
SQ_PERF_SEL_WAIT_DELAY_ALU = 36
SQ_PERF_SEL_WAIT_DEPCTR = 37
SQ_PERF_SEL_WAIT_OTHER = 38
SQ_PERF_SEL_INSTS_ALL = 39
SQ_PERF_SEL_INSTS_BRANCH = 40
SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 41
SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 42
SQ_PERF_SEL_INSTS_EXP = 43
SQ_PERF_SEL_INSTS_FLAT = 44
SQ_PERF_SEL_INSTS_LDS = 45
SQ_PERF_SEL_INSTS_SALU = 46
SQ_PERF_SEL_INSTS_SMEM = 47
SQ_PERF_SEL_INSTS_SMEM_NORM = 48
SQ_PERF_SEL_INSTS_SENDMSG = 49
SQ_PERF_SEL_INSTS_VALU = 50
SQ_PERF_SEL_INSTS_VALU_TRANS32 = 51
SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 52
SQ_PERF_SEL_INSTS_TEX = 53
SQ_PERF_SEL_INSTS_TEX_LOAD = 54
SQ_PERF_SEL_INSTS_TEX_STORE = 55
SQ_PERF_SEL_INSTS_DELAY_ALU = 56
SQ_PERF_SEL_INSTS_INTERNAL = 57
SQ_PERF_SEL_INSTS_VEC32 = 58
SQ_PERF_SEL_INSTS_VEC32_FLAT = 59
SQ_PERF_SEL_INSTS_VEC32_LDS = 60
SQ_PERF_SEL_INSTS_VEC32_VALU = 61
SQ_PERF_SEL_VEC32_INSTS_EXP = 62
SQ_PERF_SEL_INSTS_VEC32_VALU_TRANS32 = 63
SQ_PERF_SEL_INSTS_VEC32_VALU_NO_COEXEC = 64
SQ_PERF_SEL_INSTS_VEC32_TEX = 65
SQ_PERF_SEL_INSTS_VEC32_TEX_LOAD = 66
SQ_PERF_SEL_INSTS_VEC32_TEX_STORE = 67
SQ_PERF_SEL_ITEM_CYCLES_VALU = 68
SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 69
SQ_PERF_SEL_WAVE32_INSTS = 70
SQ_PERF_SEL_WAVE64_INSTS = 71
SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 72
SQ_PERF_SEL_WAVE64_HALF_SKIP = 73
SQ_PERF_SEL_INST_LEVEL_EXP = 74
SQ_PERF_SEL_INST_LEVEL_LDS = 75
SQ_PERF_SEL_INST_LEVEL_SMEM = 76
SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 77
SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 78
SQ_PERF_SEL_IFETCH_REQS = 79
SQ_PERF_SEL_IFETCH_LEVEL = 80
SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 81
SQ_PERF_SEL_VALU_SGATHER_STALL = 82
SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 83
SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 84
SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 85
SQ_PERF_SEL_SALU_SGATHER_STALL = 86
SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 87
SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 88
SQ_PERF_SEL_INST_ISSUE_SMEM_STALL = 89
SQ_PERF_SEL_INST_ISSUE_ALL_STALL = 90
SQ_PERF_SEL_INST_ISSUE_VALU_STALL = 91
SQ_PERF_SEL_INST_ISSUE_SALU_STALL = 92
SQ_PERF_SEL_INST_ISSUE_TEX_STALL = 93
SQ_PERF_SEL_INST_ISSUE_LDS_STALL = 94
SQ_PERF_SEL_INST_ISSUE_EXP_STALL = 96
SQ_PERF_SEL_INST_WAITCNT_STALL = 97
SQ_PERF_SEL_INST_BARRIER_STALL = 98
SQ_PERF_SEL_INST_CYCLES_VALU = 99
SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 100
SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 101
SQ_PERF_SEL_INST_CYCLES_VMEM = 102
SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 103
SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 104
SQ_PERF_SEL_INST_CYCLES_LDS = 105
SQ_PERF_SEL_INST_CYCLES_TEX = 106
SQ_PERF_SEL_INST_CYCLES_FLAT = 107
SQ_PERF_SEL_INST_CYCLES_EXP = 108
SQ_PERF_SEL_VALU_STARVE = 109
SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 110
SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 111
SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 112
SQ_PERF_SEL_VMEM_BUS_ACTIVE = 113
SQ_PERF_SEL_VMEM_BUS_STALL = 114
SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 115
SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 116
SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 117
SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 118
SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 119
SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 120
SQ_PERF_SEL_SALU_PIPE_STALL = 121
SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 122
SQ_PERF_SEL_MSG_BUS_BUSY = 123
SQ_PERF_SEL_EXP_REQ_BUS_STALL = 124
SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 125
SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 126
SQ_PERF_SEL_EXP_BUS0_BUSY = 127
SQ_PERF_SEL_EXP_BUS1_BUSY = 128
SQ_PERF_SEL_INST_CACHE_REQ_STALL = 129
SQ_PERF_SEL_USER0 = 130
SQ_PERF_SEL_USER1 = 131
SQ_PERF_SEL_USER2 = 132
SQ_PERF_SEL_USER3 = 133
SQ_PERF_SEL_USER4 = 134
SQ_PERF_SEL_USER5 = 135
SQ_PERF_SEL_USER6 = 136
SQ_PERF_SEL_USER7 = 137
SQ_PERF_SEL_USER8 = 138
SQ_PERF_SEL_USER9 = 139
SQ_PERF_SEL_USER10 = 140
SQ_PERF_SEL_USER11 = 141
SQ_PERF_SEL_USER12 = 142
SQ_PERF_SEL_USER13 = 143
SQ_PERF_SEL_USER14 = 144
SQ_PERF_SEL_USER15 = 145
SQ_PERF_SEL_USER_LEVEL0 = 146
SQ_PERF_SEL_USER_LEVEL1 = 147
SQ_PERF_SEL_USER_LEVEL2 = 148
SQ_PERF_SEL_USER_LEVEL3 = 149
SQ_PERF_SEL_USER_LEVEL4 = 150
SQ_PERF_SEL_USER_LEVEL5 = 151
SQ_PERF_SEL_USER_LEVEL6 = 152
SQ_PERF_SEL_USER_LEVEL7 = 153
SQ_PERF_SEL_USER_LEVEL8 = 154
SQ_PERF_SEL_USER_LEVEL9 = 155
SQ_PERF_SEL_USER_LEVEL10 = 156
SQ_PERF_SEL_USER_LEVEL11 = 157
SQ_PERF_SEL_USER_LEVEL12 = 158
SQ_PERF_SEL_USER_LEVEL13 = 159
SQ_PERF_SEL_USER_LEVEL14 = 160
SQ_PERF_SEL_USER_LEVEL15 = 161
SQ_PERF_SEL_VALU_RETURN_SDST = 162
SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 163
SQ_PERF_SEL_INSTS_VALU_TRANS = 164
SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 165
SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 166
SQ_PERF_SEL_INSTS_VEC32_LDS_PARAM_LOAD = 167
SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 168
SQ_PERF_SEL_INSTS_VALU_VINTERP = 169
SQ_PERF_SEL_INSTS_VEC32_VALU_VINTERP = 170
SQ_PERF_SEL_OVERFLOW_PREV = 171
SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 172
SQ_PERF_SEL_INSTS_VALU_1_PASS = 173
SQ_PERF_SEL_INSTS_VALU_2_PASS = 174
SQ_PERF_SEL_INSTS_VALU_4_PASS = 175
SQ_PERF_SEL_INSTS_VALU_DP = 176
SQ_PERF_SEL_SP_CONST_CYCLES = 177
SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 178
SQ_PERF_SEL_ITEMS_VALU = 179
SQ_PERF_SEL_ITEMS_MAX_VALU = 180
SQ_PERF_SEL_ITEM_CYCLES_VMEM = 181
SQ_PERF_SEL_INSTS_DELAY_ALU_COISSUE = 182
SQ_PERF_SEL_INSTS_FLAT_LOAD = 183
SQ_PERF_SEL_INSTS_FLAT_STORE = 184
SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_16BIT = 185
SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_32BIT = 186
SQ_PERF_SEL_INSTS_NON_VALU_EXEC_SKIPPED = 187
SQ_PERF_SEL_INSTS_BARRIER_LOCK = 188
SQ_PERF_SEL_INSTS_WAKEUP = 189
SQ_PERF_SEL_IS_CACHE_REQ = 190
SQ_PERF_SEL_INSTS_SALU_PS = 191
SQ_PERF_SEL_INSTS_SALU_GS = 192
SQ_PERF_SEL_INSTS_SALU_HS = 193
SQ_PERF_SEL_INSTS_SALU_CS = 194
SQ_PERF_SEL_INSTS_SMEM_PS = 195
SQ_PERF_SEL_INSTS_SMEM_GS = 196
SQ_PERF_SEL_INSTS_SMEM_HS = 197
SQ_PERF_SEL_INSTS_SMEM_CS = 198
SQ_PERF_SEL_INSTS_VEC32_TEX_PS = 199
SQ_PERF_SEL_INSTS_VEC32_TEX_GS = 200
SQ_PERF_SEL_INSTS_VEC32_TEX_HS = 201
SQ_PERF_SEL_INSTS_VEC32_TEX_CS = 202
SQ_PERF_SEL_INSTS_VEC32_VALU_PS = 203
SQ_PERF_SEL_INSTS_VEC32_VALU_GS = 204
SQ_PERF_SEL_INSTS_VEC32_VALU_HS = 205
SQ_PERF_SEL_INSTS_VEC32_VALU_CS = 206
SQ_PERF_SEL_WAIT_CNT_SAMPLE = 207
SQ_PERF_SEL_WAIT_CNT_KM = 209
SQ_PERF_SEL_WAIT_CNT_DS = 210
SQ_PERF_SEL_WAIT_CNT_EXP = 211
SQ_PERF_SEL_INSTS_SALU_FLOAT = 212
SQ_PERF_SEL_INSTS_VGPR_ALLOC = 213
SQ_PERF_SEL_INSTS_VGPR_ALLOC_FAIL = 214
SQ_PERF_SEL_INSTS_LOCK = 215
SQ_PERF_SEL_INSTS_VALU_COISSUE = 216
SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_LOAD = 217
SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_STORE = 218
SQ_PERF_SEL_IS_CACHE_MISS = 219
SQ_PERF_SEL_IS_CACHE_DUP_MISS = 220
SQ_PERF_SEL_INST_CYCLES_VMEM_ATOMIC = 221
SQ_PERF_SEL_INSTS_TEX_BLOCK_LOAD = 222
SQ_PERF_SEL_INSTS_TEX_SAMPLE = 224
SQ_PERF_SEL_INSTS_TEX_ATOMIC_RTN = 225
SQ_PERF_SEL_INSTS_TEX_BLOCK_STORE = 226
SQ_PERF_SEL_INSTS_TEX_ATOMIC_NORTN = 227
SQ_PERF_SEL_INSTS_GLOBAL_SCRATCH = 228
SQ_PERF_SEL_INSTS_WMMA_LOAD = 229
SQ_PERF_SEL_INSTS_FLAT_ATOMIC = 230
SQ_PERF_SEL_INSTS_EXP_MRT = 231
SQ_PERF_SEL_INSTS_EXP_Z = 232
SQ_PERF_SEL_INSTS_VEC32_VALU_WMMA = 233
SQ_PERF_SEL_INSTS_VEC32_LDS_LOAD = 234
SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_RTN = 235
SQ_PERF_SEL_INSTS_VEC32_LDS_STORE = 236
SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_NORTN = 237
SQ_PERF_SEL_INSTS_VEC32_LDS_OTHER = 239
SQ_PERF_SEL_INSTS_VEC32_TEX_SAMPLE = 241
SQ_PERF_SEL_INSTS_VEC32_TEX_ATOMIC = 242
SQ_PERF_SEL_INSTS_VEC32_FLAT_LOAD = 243
SQ_PERF_SEL_INSTS_VEC32_FLAT_STORE = 244
SQ_PERF_SEL_INSTS_VEC32_FLAT_ATOMIC = 245
SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH = 246
SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_LOAD = 247
SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_STORE = 248
SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_ATOMIC = 249
SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS = 250
SQ_PERF_SEL_DUMMY_END = 251
SQ_PERF_SEL_DUMMY_LAST = 287
SQC_PERF_SEL_LDS_BANK_CONFLICT = 288
SQC_PERF_SEL_LDS_ADDR_CONFLICT = 289
SQC_PERF_SEL_LDS_UNALIGNED_STALL = 290
SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 291
SQC_PERF_SEL_LDS_ATOMIC_RETURN = 292
SQC_PERF_SEL_LDS_IDX_ACTIVE = 293
SQC_PERF_SEL_LDS_ADDR_STALL = 294
SQC_PERF_SEL_LDS_ADDR_ACTIVE = 295
SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 296
SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 297
SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 298
SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 299
SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 300
SQC_PERF_SEL_ICACHE_REQ = 301
SQC_PERF_SEL_ICACHE_HITS = 302
SQC_PERF_SEL_ICACHE_MISSES = 303
SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 304
SQC_PERF_SEL_ICACHE_INVAL_INST = 305
SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 306
SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 307
SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 308
SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 309
SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 310
SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 311
SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 312
SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 313
SQC_PERF_SEL_TC_REQ = 314
SQC_PERF_SEL_TC_INST_REQ = 315
SQC_PERF_SEL_TC_DATA_READ_REQ = 316
SQC_PERF_SEL_TC_STALL = 317
SQC_PERF_SEL_TC_STARVE = 318
SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 319
SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 320
SQC_PERF_SEL_ICACHE_CACHE_STALLED = 321
SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 322
SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 323
SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 324
SQC_PERF_SEL_DCACHE_REQ = 325
SQC_PERF_SEL_DCACHE_HITS = 326
SQC_PERF_SEL_DCACHE_MISSES = 327
SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 328
SQC_PERF_SEL_DCACHE_INVAL_INST = 329
SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 330
SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 331
SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 332
SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 333
SQC_PERF_SEL_DCACHE_CACHE_STALLED = 334
SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 335
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 336
SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 337
SQC_PERF_SEL_DCACHE_REQ_READ_1 = 338
SQC_PERF_SEL_DCACHE_REQ_READ_2 = 339
SQC_PERF_SEL_DCACHE_REQ_READ_4 = 340
SQC_PERF_SEL_DCACHE_REQ_READ_8 = 341
SQC_PERF_SEL_DCACHE_REQ_READ_16 = 342
SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 343
SQC_PERF_SEL_SQ_DCACHE_REQS = 344
SQC_PERF_SEL_DCACHE_FLAT_REQ = 345
SQC_PERF_SEL_TD_VGPR_BUSY = 346
SQC_PERF_SEL_LDS_VGPR_BUSY = 347
SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 348
SQC_PERF_SEL_ICACHE_GCR = 349
SQC_PERF_SEL_ICACHE_GCR_HITS = 350
SQC_PERF_SEL_DCACHE_GCR = 351
SQC_PERF_SEL_DCACHE_GCR_HITS = 352
SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 353
SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 354
SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 355
SQC_PERF_SEL_ICACHE_PREFETCH_REQ_CACHELINES = 356
SQC_PERF_SEL_DCACHE_PREFETCH_REQ_CACHELINES = 357
SQC_PERF_SEL_ICACHE_PREFETCH_MISSES = 358
SQC_PERF_SEL_DCACHE_PREFETCH_MISSES = 359
SQC_PERF_SEL_LDS_BANKCONF_LOAD_CNT = 360
SQC_PERF_SEL_LDS_BANKCONF_STORE_CNT = 361
SQC_PERF_SEL_LDS_BANKCONF_ATOMIC_CNT = 362
SQC_PERF_SEL_LDS_ACTIVE_LOAD_CNT = 363
SQC_PERF_SEL_LDS_ACTIVE_STORE_CNT = 364
SQC_PERF_SEL_LDS_ACTIVE_ATOMIC_CNT = 365
SQC_PERF_SEL_LDS_STORE_DWORDS = 366
SQC_PERF_SEL_LDS_LOAD_DWORDS = 367
SQC_PERF_SEL_LDS_ATOMIC_DWORDS = 368
SQC_PERF_SEL_LDS_LDS_EXECUTION_STALL = 369
SQC_PERF_SEL_DUMMY_LAST = 370
SP_PERF_SEL_DST_BUF_ALLOC_STALL = 448
SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 449
SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 450
SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 451
SP_PERF_SEL_DST_BUF_ODD_DIRTY = 452
SP_PERF_SEL_SRC_CACHE_HIT_B0 = 453
SP_PERF_SEL_SRC_CACHE_HIT_B1 = 454
SP_PERF_SEL_SRC_CACHE_HIT_B2 = 455
SP_PERF_SEL_SRC_CACHE_HIT_B3 = 456
SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 457
SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 458
SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 459
SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 460
SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 461
SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 462
SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 463
SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 464
SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 465
SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 466
SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 467
SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 468
SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 469
SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 470
SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 471
SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 472
SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 473
SP_PERF_SEL_VALU_OPERAND = 474
SP_PERF_SEL_VALU_VGPR_OPERAND = 475
SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 476
SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 477
SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 478
SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 479
SP_PERF_SEL_VALU_STALL = 480
SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 481
SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 482
SP_PERF_SEL_VALU_STALL_VDST_FWD = 483
SP_PERF_SEL_VALU_STALL_SDST_FWD = 484
SP_PERF_SEL_VALU_STALL_DST_STALL = 485
SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 486
SP_PERF_SEL_VGPR_VMEM_RD = 487
SP_PERF_SEL_VGPR_EXP_RD = 488
SP_PERF_SEL_VGPR_SPI_WR = 489
SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 490
SP_PERF_SEL_VGPR_WR = 491
SP_PERF_SEL_VGPR_RD = 492
SP_PERF_SEL_VGPR_WR_KILL = 493
SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_EXP = 494
SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_LDS = 495
SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_TEX = 496
SP_PERF_SEL_DUMMY_LAST = 497
SQ_PERF_SEL_NONE2 = 511
SQ_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SQ_ROUND_MODE'
SQ_ROUND_MODE__enumvalues = {
0: 'SQ_ROUND_NEAREST_EVEN',
1: 'SQ_ROUND_PLUS_INFINITY',
2: 'SQ_ROUND_MINUS_INFINITY',
3: 'SQ_ROUND_TO_ZERO',
}
SQ_ROUND_NEAREST_EVEN = 0
SQ_ROUND_PLUS_INFINITY = 1
SQ_ROUND_MINUS_INFINITY = 2
SQ_ROUND_TO_ZERO = 3
SQ_ROUND_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_RSRC_BUF_TYPE'
SQ_RSRC_BUF_TYPE__enumvalues = {
0: 'SQ_RSRC_BUF',
1: 'SQ_RSRC_BUF_RSVD_1',
2: 'SQ_RSRC_BUF_RSVD_2',
3: 'SQ_RSRC_BUF_RSVD_3',
}
SQ_RSRC_BUF = 0
SQ_RSRC_BUF_RSVD_1 = 1
SQ_RSRC_BUF_RSVD_2 = 2
SQ_RSRC_BUF_RSVD_3 = 3
SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_RSRC_FLAT_TYPE'
SQ_RSRC_FLAT_TYPE__enumvalues = {
0: 'SQ_RSRC_FLAT_RSVD_0',
1: 'SQ_RSRC_FLAT',
2: 'SQ_RSRC_FLAT_RSVD_2',
3: 'SQ_RSRC_FLAT_RSVD_3',
}
SQ_RSRC_FLAT_RSVD_0 = 0
SQ_RSRC_FLAT = 1
SQ_RSRC_FLAT_RSVD_2 = 2
SQ_RSRC_FLAT_RSVD_3 = 3
SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_RSRC_IMG_TYPE'
SQ_RSRC_IMG_TYPE__enumvalues = {
0: 'SQ_RSRC_IMG_RSVD_0',
1: 'SQ_RSRC_IMG_RSVD_1',
2: 'SQ_RSRC_IMG_RSVD_2',
3: 'SQ_RSRC_IMG_RSVD_3',
4: 'SQ_RSRC_IMG_RSVD_4',
5: 'SQ_RSRC_IMG_RSVD_5',
6: 'SQ_RSRC_IMG_RSVD_6',
7: 'SQ_RSRC_IMG_RSVD_7',
8: 'SQ_RSRC_IMG_1D',
9: 'SQ_RSRC_IMG_2D',
10: 'SQ_RSRC_IMG_3D',
11: 'SQ_RSRC_IMG_CUBE',
12: 'SQ_RSRC_IMG_1D_ARRAY',
13: 'SQ_RSRC_IMG_2D_ARRAY',
14: 'SQ_RSRC_IMG_2D_MSAA',
15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY',
}
SQ_RSRC_IMG_RSVD_0 = 0
SQ_RSRC_IMG_RSVD_1 = 1
SQ_RSRC_IMG_RSVD_2 = 2
SQ_RSRC_IMG_RSVD_3 = 3
SQ_RSRC_IMG_RSVD_4 = 4
SQ_RSRC_IMG_RSVD_5 = 5
SQ_RSRC_IMG_RSVD_6 = 6
SQ_RSRC_IMG_RSVD_7 = 7
SQ_RSRC_IMG_1D = 8
SQ_RSRC_IMG_2D = 9
SQ_RSRC_IMG_3D = 10
SQ_RSRC_IMG_CUBE = 11
SQ_RSRC_IMG_1D_ARRAY = 12
SQ_RSRC_IMG_2D_ARRAY = 13
SQ_RSRC_IMG_2D_MSAA = 14
SQ_RSRC_IMG_2D_MSAA_ARRAY = 15
SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_SEL_XYZW01'
SQ_SEL_XYZW01__enumvalues = {
0: 'SQ_SEL_0',
1: 'SQ_SEL_1',
2: 'SQ_SEL_N_BC_1',
3: 'SQ_SEL_RESERVED_1',
4: 'SQ_SEL_X',
5: 'SQ_SEL_Y',
6: 'SQ_SEL_Z',
7: 'SQ_SEL_W',
}
SQ_SEL_0 = 0
SQ_SEL_1 = 1
SQ_SEL_N_BC_1 = 2
SQ_SEL_RESERVED_1 = 3
SQ_SEL_X = 4
SQ_SEL_Y = 5
SQ_SEL_Z = 6
SQ_SEL_W = 7
SQ_SEL_XYZW01 = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_ANISO_RATIO'
SQ_TEX_ANISO_RATIO__enumvalues = {
0: 'SQ_TEX_ANISO_RATIO_1',
1: 'SQ_TEX_ANISO_RATIO_2',
2: 'SQ_TEX_ANISO_RATIO_4',
3: 'SQ_TEX_ANISO_RATIO_8',
4: 'SQ_TEX_ANISO_RATIO_16',
}
SQ_TEX_ANISO_RATIO_1 = 0
SQ_TEX_ANISO_RATIO_2 = 1
SQ_TEX_ANISO_RATIO_4 = 2
SQ_TEX_ANISO_RATIO_8 = 3
SQ_TEX_ANISO_RATIO_16 = 4
SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_BORDER_COLOR'
SQ_TEX_BORDER_COLOR__enumvalues = {
0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK',
1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK',
2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE',
3: 'SQ_TEX_BORDER_COLOR_REGISTER',
}
SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0
SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1
SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2
SQ_TEX_BORDER_COLOR_REGISTER = 3
SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_CLAMP'
SQ_TEX_CLAMP__enumvalues = {
0: 'SQ_TEX_WRAP',
1: 'SQ_TEX_MIRROR',
2: 'SQ_TEX_CLAMP_LAST_TEXEL',
3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL',
4: 'SQ_TEX_CLAMP_HALF_BORDER',
5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER',
6: 'SQ_TEX_CLAMP_BORDER',
7: 'SQ_TEX_MIRROR_ONCE_BORDER',
}
SQ_TEX_WRAP = 0
SQ_TEX_MIRROR = 1
SQ_TEX_CLAMP_LAST_TEXEL = 2
SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3
SQ_TEX_CLAMP_HALF_BORDER = 4
SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5
SQ_TEX_CLAMP_BORDER = 6
SQ_TEX_MIRROR_ONCE_BORDER = 7
SQ_TEX_CLAMP = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_DEPTH_COMPARE'
SQ_TEX_DEPTH_COMPARE__enumvalues = {
0: 'SQ_TEX_DEPTH_COMPARE_NEVER',
1: 'SQ_TEX_DEPTH_COMPARE_LESS',
2: 'SQ_TEX_DEPTH_COMPARE_EQUAL',
3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL',
4: 'SQ_TEX_DEPTH_COMPARE_GREATER',
5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL',
6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL',
7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS',
}
SQ_TEX_DEPTH_COMPARE_NEVER = 0
SQ_TEX_DEPTH_COMPARE_LESS = 1
SQ_TEX_DEPTH_COMPARE_EQUAL = 2
SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3
SQ_TEX_DEPTH_COMPARE_GREATER = 4
SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5
SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6
SQ_TEX_DEPTH_COMPARE_ALWAYS = 7
SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_MIP_FILTER'
SQ_TEX_MIP_FILTER__enumvalues = {
0: 'SQ_TEX_MIP_FILTER_NONE',
1: 'SQ_TEX_MIP_FILTER_POINT',
2: 'SQ_TEX_MIP_FILTER_LINEAR',
3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ',
}
SQ_TEX_MIP_FILTER_NONE = 0
SQ_TEX_MIP_FILTER_POINT = 1
SQ_TEX_MIP_FILTER_LINEAR = 2
SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3
SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_XY_FILTER'
SQ_TEX_XY_FILTER__enumvalues = {
0: 'SQ_TEX_XY_FILTER_POINT',
1: 'SQ_TEX_XY_FILTER_BILINEAR',
2: 'SQ_TEX_XY_FILTER_ANISO_POINT',
3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR',
}
SQ_TEX_XY_FILTER_POINT = 0
SQ_TEX_XY_FILTER_BILINEAR = 1
SQ_TEX_XY_FILTER_ANISO_POINT = 2
SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3
SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_Z_FILTER'
SQ_TEX_Z_FILTER__enumvalues = {
0: 'SQ_TEX_Z_FILTER_NONE',
1: 'SQ_TEX_Z_FILTER_POINT',
2: 'SQ_TEX_Z_FILTER_LINEAR',
}
SQ_TEX_Z_FILTER_NONE = 0
SQ_TEX_Z_FILTER_POINT = 1
SQ_TEX_Z_FILTER_LINEAR = 2
SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'SQ_WATCH_MODES'
SQ_WATCH_MODES__enumvalues = {
0: 'SQ_WATCH_MODE_READ',
1: 'SQ_WATCH_MODE_NONREAD',
2: 'SQ_WATCH_MODE_ATOMIC',
3: 'SQ_WATCH_MODE_ALL',
}
SQ_WATCH_MODE_READ = 0
SQ_WATCH_MODE_NONREAD = 1
SQ_WATCH_MODE_ATOMIC = 2
SQ_WATCH_MODE_ALL = 3
SQ_WATCH_MODES = ctypes.c_uint32 # enum
# values for enumeration 'SQ_WAVE_FWD_PROG_INTERVAL'
SQ_WAVE_FWD_PROG_INTERVAL__enumvalues = {
0: 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER',
1: 'SQ_WAVE_FWD_PROG_INTERVAL_256',
2: 'SQ_WAVE_FWD_PROG_INTERVAL_1024',
3: 'SQ_WAVE_FWD_PROG_INTERVAL_4096',
}
SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0
SQ_WAVE_FWD_PROG_INTERVAL_256 = 1
SQ_WAVE_FWD_PROG_INTERVAL_1024 = 2
SQ_WAVE_FWD_PROG_INTERVAL_4096 = 3
SQ_WAVE_FWD_PROG_INTERVAL = ctypes.c_uint32 # enum
# values for enumeration 'SQ_WAVE_SCHED_MODES'
SQ_WAVE_SCHED_MODES__enumvalues = {
0: 'SQ_WAVE_SCHED_MODE_NORMAL',
1: 'SQ_WAVE_SCHED_MODE_EXPERT',
2: 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST_VM_VSRC',
}
SQ_WAVE_SCHED_MODE_NORMAL = 0
SQ_WAVE_SCHED_MODE_EXPERT = 1
SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST_VM_VSRC = 2
SQ_WAVE_SCHED_MODES = ctypes.c_uint32 # enum
# values for enumeration 'SQ_WAVE_TYPE'
SQ_WAVE_TYPE__enumvalues = {
0: 'SQ_WAVE_TYPE_PS',
1: 'SQ_WAVE_TYPE_RSVD0',
2: 'SQ_WAVE_TYPE_GS',
3: 'SQ_WAVE_TYPE_RSVD1',
4: 'SQ_WAVE_TYPE_HS',
5: 'SQ_WAVE_TYPE_RSVD2',
6: 'SQ_WAVE_TYPE_CS',
7: 'SQ_WAVE_TYPE_PS1',
8: 'SQ_WAVE_TYPE_PS2',
9: 'SQ_WAVE_TYPE_PS3',
}
SQ_WAVE_TYPE_PS = 0
SQ_WAVE_TYPE_RSVD0 = 1
SQ_WAVE_TYPE_GS = 2
SQ_WAVE_TYPE_RSVD1 = 3
SQ_WAVE_TYPE_HS = 4
SQ_WAVE_TYPE_RSVD2 = 5
SQ_WAVE_TYPE_CS = 6
SQ_WAVE_TYPE_PS1 = 7
SQ_WAVE_TYPE_PS2 = 8
SQ_WAVE_TYPE_PS3 = 9
SQ_WAVE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'GL1A_PERF_SEL'
GL1A_PERF_SEL__enumvalues = {
0: 'GL1A_PERF_SEL_BUSY',
1: 'GL1A_PERF_SEL_STALL_GL1C0',
2: 'GL1A_PERF_SEL_STALL_GL1C1',
3: 'GL1A_PERF_SEL_STALL_GL1C2',
4: 'GL1A_PERF_SEL_STALL_GL1C3',
5: 'GL1A_PERF_SEL_REQUEST_GL1C0',
6: 'GL1A_PERF_SEL_REQUEST_GL1C1',
7: 'GL1A_PERF_SEL_REQUEST_GL1C2',
8: 'GL1A_PERF_SEL_REQUEST_GL1C3',
9: 'GL1A_PERF_SEL_WDS_32B_GL1C0',
10: 'GL1A_PERF_SEL_WDS_32B_GL1C1',
11: 'GL1A_PERF_SEL_WDS_32B_GL1C2',
12: 'GL1A_PERF_SEL_WDS_32B_GL1C3',
13: 'GL1A_PERF_SEL_BURST_COUNT_GL1C0',
14: 'GL1A_PERF_SEL_BURST_COUNT_GL1C1',
15: 'GL1A_PERF_SEL_BURST_COUNT_GL1C2',
16: 'GL1A_PERF_SEL_BURST_COUNT_GL1C3',
17: 'GL1A_PERF_SEL_ARB_REQUESTS',
18: 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL',
19: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0',
20: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1',
21: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2',
22: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3',
23: 'GL1A_PERF_SEL_CYCLE',
}
GL1A_PERF_SEL_BUSY = 0
GL1A_PERF_SEL_STALL_GL1C0 = 1
GL1A_PERF_SEL_STALL_GL1C1 = 2
GL1A_PERF_SEL_STALL_GL1C2 = 3
GL1A_PERF_SEL_STALL_GL1C3 = 4
GL1A_PERF_SEL_REQUEST_GL1C0 = 5
GL1A_PERF_SEL_REQUEST_GL1C1 = 6
GL1A_PERF_SEL_REQUEST_GL1C2 = 7
GL1A_PERF_SEL_REQUEST_GL1C3 = 8
GL1A_PERF_SEL_WDS_32B_GL1C0 = 9
GL1A_PERF_SEL_WDS_32B_GL1C1 = 10
GL1A_PERF_SEL_WDS_32B_GL1C2 = 11
GL1A_PERF_SEL_WDS_32B_GL1C3 = 12
GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 13
GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 14
GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 15
GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 16
GL1A_PERF_SEL_ARB_REQUESTS = 17
GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 18
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 19
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 20
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 21
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 22
GL1A_PERF_SEL_CYCLE = 23
GL1A_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL1C_PERF_SEL'
GL1C_PERF_SEL__enumvalues = {
0: 'GL1C_PERF_SEL_CYCLE',
1: 'GL1C_PERF_SEL_BUSY',
2: 'GL1C_PERF_SEL_STARVE',
3: 'GL1C_PERF_SEL_ARB_RET_LEVEL',
4: 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY',
5: 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY',
6: 'GL1C_PERF_SEL_REQ',
7: 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET',
8: 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET',
9: 'GL1C_PERF_SEL_REQ_NOP_ACK',
10: 'GL1C_PERF_SEL_REQ_NOP_RTN0',
11: 'GL1C_PERF_SEL_REQ_READ',
12: 'GL1C_PERF_SEL_REQ_READ_128B',
13: 'GL1C_PERF_SEL_REQ_READ_32B',
14: 'GL1C_PERF_SEL_REQ_READ_64B',
15: 'GL1C_PERF_SEL_REQ_WRITE',
16: 'GL1C_PERF_SEL_REQ_WRITE_32B',
17: 'GL1C_PERF_SEL_REQ_WRITE_64B',
18: 'GL1C_PERF_SEL_STALL_GL2_GL1',
19: 'GL1C_PERF_SEL_STALL_BUFFER_FULL',
20: 'GL1C_PERF_SEL_STALL_VM',
21: 'GL1C_PERF_SEL_REQ_CLIENT0',
22: 'GL1C_PERF_SEL_REQ_CLIENT1',
23: 'GL1C_PERF_SEL_REQ_CLIENT2',
24: 'GL1C_PERF_SEL_REQ_CLIENT3',
25: 'GL1C_PERF_SEL_REQ_CLIENT4',
26: 'GL1C_PERF_SEL_REQ_CLIENT5',
27: 'GL1C_PERF_SEL_REQ_CLIENT6',
28: 'GL1C_PERF_SEL_REQ_CLIENT7',
29: 'GL1C_PERF_SEL_REQ_CLIENT8',
30: 'GL1C_PERF_SEL_REQ_CLIENT9',
31: 'GL1C_PERF_SEL_REQ_CLIENT10',
32: 'GL1C_PERF_SEL_REQ_CLIENT11',
33: 'GL1C_PERF_SEL_REQ_CLIENT12',
34: 'GL1C_PERF_SEL_REQ_CLIENT13',
35: 'GL1C_PERF_SEL_REQ_CLIENT14',
36: 'GL1C_PERF_SEL_REQ_CLIENT15',
37: 'GL1C_PERF_SEL_REQ_CLIENT16',
38: 'GL1C_PERF_SEL_REQ_CLIENT17',
39: 'GL1C_PERF_SEL_REQ_CLIENT18',
40: 'GL1C_PERF_SEL_REQ_CLIENT19',
41: 'GL1C_PERF_SEL_REQ_CLIENT20',
42: 'GL1C_PERF_SEL_REQ_CLIENT21',
43: 'GL1C_PERF_SEL_REQ_CLIENT22',
44: 'GL1C_PERF_SEL_REQ_CLIENT23',
45: 'GL1C_PERF_SEL_REQ_CLIENT24',
46: 'GL1C_PERF_SEL_REQ_CLIENT25',
47: 'GL1C_PERF_SEL_REQ_CLIENT26',
48: 'GL1C_PERF_SEL_REQ_CLIENT27',
49: 'GL1C_PERF_SEL_UTCL0_REQUEST',
50: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT',
51: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS',
52: 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS',
53: 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS',
54: 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL',
55: 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX',
56: 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES',
57: 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT',
58: 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL',
59: 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS',
60: 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS',
61: 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT',
62: 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT',
63: 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT',
64: 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ',
65: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT',
66: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT',
67: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT',
68: 'GL1C_PERF_SEL_UTCL0_GPA3_REQUEST',
}
GL1C_PERF_SEL_CYCLE = 0
GL1C_PERF_SEL_BUSY = 1
GL1C_PERF_SEL_STARVE = 2
GL1C_PERF_SEL_ARB_RET_LEVEL = 3
GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 4
GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5
GL1C_PERF_SEL_REQ = 6
GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 7
GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8
GL1C_PERF_SEL_REQ_NOP_ACK = 9
GL1C_PERF_SEL_REQ_NOP_RTN0 = 10
GL1C_PERF_SEL_REQ_READ = 11
GL1C_PERF_SEL_REQ_READ_128B = 12
GL1C_PERF_SEL_REQ_READ_32B = 13
GL1C_PERF_SEL_REQ_READ_64B = 14
GL1C_PERF_SEL_REQ_WRITE = 15
GL1C_PERF_SEL_REQ_WRITE_32B = 16
GL1C_PERF_SEL_REQ_WRITE_64B = 17
GL1C_PERF_SEL_STALL_GL2_GL1 = 18
GL1C_PERF_SEL_STALL_BUFFER_FULL = 19
GL1C_PERF_SEL_STALL_VM = 20
GL1C_PERF_SEL_REQ_CLIENT0 = 21
GL1C_PERF_SEL_REQ_CLIENT1 = 22
GL1C_PERF_SEL_REQ_CLIENT2 = 23
GL1C_PERF_SEL_REQ_CLIENT3 = 24
GL1C_PERF_SEL_REQ_CLIENT4 = 25
GL1C_PERF_SEL_REQ_CLIENT5 = 26
GL1C_PERF_SEL_REQ_CLIENT6 = 27
GL1C_PERF_SEL_REQ_CLIENT7 = 28
GL1C_PERF_SEL_REQ_CLIENT8 = 29
GL1C_PERF_SEL_REQ_CLIENT9 = 30
GL1C_PERF_SEL_REQ_CLIENT10 = 31
GL1C_PERF_SEL_REQ_CLIENT11 = 32
GL1C_PERF_SEL_REQ_CLIENT12 = 33
GL1C_PERF_SEL_REQ_CLIENT13 = 34
GL1C_PERF_SEL_REQ_CLIENT14 = 35
GL1C_PERF_SEL_REQ_CLIENT15 = 36
GL1C_PERF_SEL_REQ_CLIENT16 = 37
GL1C_PERF_SEL_REQ_CLIENT17 = 38
GL1C_PERF_SEL_REQ_CLIENT18 = 39
GL1C_PERF_SEL_REQ_CLIENT19 = 40
GL1C_PERF_SEL_REQ_CLIENT20 = 41
GL1C_PERF_SEL_REQ_CLIENT21 = 42
GL1C_PERF_SEL_REQ_CLIENT22 = 43
GL1C_PERF_SEL_REQ_CLIENT23 = 44
GL1C_PERF_SEL_REQ_CLIENT24 = 45
GL1C_PERF_SEL_REQ_CLIENT25 = 46
GL1C_PERF_SEL_REQ_CLIENT26 = 47
GL1C_PERF_SEL_REQ_CLIENT27 = 48
GL1C_PERF_SEL_UTCL0_REQUEST = 49
GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 50
GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 51
GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 52
GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 53
GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 54
GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 55
GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 56
GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 57
GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 58
GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 59
GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 60
GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 61
GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 62
GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 63
GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 64
GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 65
GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 66
GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 67
GL1C_PERF_SEL_UTCL0_GPA3_REQUEST = 68
GL1C_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL1XA_PERF_SEL'
GL1XA_PERF_SEL__enumvalues = {
0: 'GL1XA_PERF_SEL_BUSY',
1: 'GL1XA_PERF_SEL_STALL_GL1XC0',
2: 'GL1XA_PERF_SEL_STALL_GL1XC1',
3: 'GL1XA_PERF_SEL_STALL_GL1XC2',
4: 'GL1XA_PERF_SEL_STALL_GL1XC3',
5: 'GL1XA_PERF_SEL_REQUEST_GL1XC0',
6: 'GL1XA_PERF_SEL_REQUEST_GL1XC1',
7: 'GL1XA_PERF_SEL_REQUEST_GL1XC2',
8: 'GL1XA_PERF_SEL_REQUEST_GL1XC3',
9: 'GL1XA_PERF_SEL_WDS_32B_GL1XC0',
10: 'GL1XA_PERF_SEL_WDS_32B_GL1XC1',
11: 'GL1XA_PERF_SEL_WDS_32B_GL1XC2',
12: 'GL1XA_PERF_SEL_WDS_32B_GL1XC3',
13: 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC0',
14: 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC1',
15: 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC2',
16: 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC3',
17: 'GL1XA_PERF_SEL_ARB_REQUESTS',
18: 'GL1XA_PERF_SEL_REQ_INFLIGHT_LEVEL',
19: 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC0',
20: 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC1',
21: 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC2',
22: 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC3',
23: 'GL1XA_PERF_SEL_CYCLE',
}
GL1XA_PERF_SEL_BUSY = 0
GL1XA_PERF_SEL_STALL_GL1XC0 = 1
GL1XA_PERF_SEL_STALL_GL1XC1 = 2
GL1XA_PERF_SEL_STALL_GL1XC2 = 3
GL1XA_PERF_SEL_STALL_GL1XC3 = 4
GL1XA_PERF_SEL_REQUEST_GL1XC0 = 5
GL1XA_PERF_SEL_REQUEST_GL1XC1 = 6
GL1XA_PERF_SEL_REQUEST_GL1XC2 = 7
GL1XA_PERF_SEL_REQUEST_GL1XC3 = 8
GL1XA_PERF_SEL_WDS_32B_GL1XC0 = 9
GL1XA_PERF_SEL_WDS_32B_GL1XC1 = 10
GL1XA_PERF_SEL_WDS_32B_GL1XC2 = 11
GL1XA_PERF_SEL_WDS_32B_GL1XC3 = 12
GL1XA_PERF_SEL_BURST_COUNT_GL1XC0 = 13
GL1XA_PERF_SEL_BURST_COUNT_GL1XC1 = 14
GL1XA_PERF_SEL_BURST_COUNT_GL1XC2 = 15
GL1XA_PERF_SEL_BURST_COUNT_GL1XC3 = 16
GL1XA_PERF_SEL_ARB_REQUESTS = 17
GL1XA_PERF_SEL_REQ_INFLIGHT_LEVEL = 18
GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC0 = 19
GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC1 = 20
GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC2 = 21
GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC3 = 22
GL1XA_PERF_SEL_CYCLE = 23
GL1XA_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL1XC_PERF_SEL'
GL1XC_PERF_SEL__enumvalues = {
0: 'GL1XC_PERF_SEL_CYCLE',
1: 'GL1XC_PERF_SEL_BUSY',
2: 'GL1XC_PERF_SEL_STARVE',
3: 'GL1XC_PERF_SEL_ARB_RET_LEVEL',
4: 'GL1XC_PERF_SEL_GL2_REQ_READ_LATENCY',
5: 'GL1XC_PERF_SEL_GL2_REQ_WRITE_LATENCY',
6: 'GL1XC_PERF_SEL_REQ',
7: 'GL1XC_PERF_SEL_REQ_ATOMIC_WITH_RET',
8: 'GL1XC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET',
9: 'GL1XC_PERF_SEL_REQ_NOP_ACK',
10: 'GL1XC_PERF_SEL_REQ_NOP_RTN0',
11: 'GL1XC_PERF_SEL_REQ_READ',
12: 'GL1XC_PERF_SEL_REQ_READ_128B',
13: 'GL1XC_PERF_SEL_REQ_READ_32B',
14: 'GL1XC_PERF_SEL_REQ_READ_64B',
15: 'GL1XC_PERF_SEL_REQ_WRITE',
16: 'GL1XC_PERF_SEL_REQ_WRITE_32B',
17: 'GL1XC_PERF_SEL_REQ_WRITE_64B',
18: 'GL1XC_PERF_SEL_STALL_GL2_GL1',
19: 'GL1XC_PERF_SEL_STALL_BUFFER_FULL',
20: 'GL1XC_PERF_SEL_STALL_VM',
21: 'GL1XC_PERF_SEL_REQ_CLIENT0',
22: 'GL1XC_PERF_SEL_REQ_CLIENT1',
23: 'GL1XC_PERF_SEL_REQ_CLIENT2',
24: 'GL1XC_PERF_SEL_REQ_CLIENT3',
25: 'GL1XC_PERF_SEL_REQ_CLIENT4',
26: 'GL1XC_PERF_SEL_REQ_CLIENT5',
27: 'GL1XC_PERF_SEL_REQ_CLIENT6',
28: 'GL1XC_PERF_SEL_REQ_CLIENT7',
29: 'GL1XC_PERF_SEL_REQ_CLIENT8',
30: 'GL1XC_PERF_SEL_REQ_CLIENT9',
31: 'GL1XC_PERF_SEL_REQ_CLIENT10',
32: 'GL1XC_PERF_SEL_REQ_CLIENT11',
33: 'GL1XC_PERF_SEL_REQ_CLIENT12',
34: 'GL1XC_PERF_SEL_REQ_CLIENT13',
35: 'GL1XC_PERF_SEL_REQ_CLIENT14',
36: 'GL1XC_PERF_SEL_REQ_CLIENT15',
37: 'GL1XC_PERF_SEL_REQ_CLIENT16',
38: 'GL1XC_PERF_SEL_REQ_CLIENT17',
39: 'GL1XC_PERF_SEL_REQ_CLIENT18',
40: 'GL1XC_PERF_SEL_REQ_CLIENT19',
41: 'GL1XC_PERF_SEL_REQ_CLIENT20',
42: 'GL1XC_PERF_SEL_REQ_CLIENT21',
43: 'GL1XC_PERF_SEL_REQ_CLIENT22',
44: 'GL1XC_PERF_SEL_REQ_CLIENT23',
45: 'GL1XC_PERF_SEL_REQ_CLIENT24',
46: 'GL1XC_PERF_SEL_REQ_CLIENT25',
47: 'GL1XC_PERF_SEL_REQ_CLIENT26',
48: 'GL1XC_PERF_SEL_REQ_CLIENT27',
49: 'GL1XC_PERF_SEL_UTCL0_REQUEST',
50: 'GL1XC_PERF_SEL_UTCL0_TRANSLATION_HIT',
51: 'GL1XC_PERF_SEL_UTCL0_TRANSLATION_MISS',
52: 'GL1XC_PERF_SEL_UTCL0_PERMISSION_MISS',
53: 'GL1XC_PERF_SEL_UTCL0_MISS_UNDER_MISS',
54: 'GL1XC_PERF_SEL_UTCL0_LFIFO_FULL',
55: 'GL1XC_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX',
56: 'GL1XC_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES',
57: 'GL1XC_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT',
58: 'GL1XC_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL',
59: 'GL1XC_PERF_SEL_UTCL0_STALL_MULTI_MISS',
60: 'GL1XC_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS',
61: 'GL1XC_PERF_SEL_UTCL0_UTCL1_PERM_FAULT',
62: 'GL1XC_PERF_SEL_CLIENT_UTCL0_INFLIGHT',
63: 'GL1XC_PERF_SEL_UTCL0_UTCL1_INFLIGHT',
64: 'GL1XC_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ',
65: 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT',
66: 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT',
67: 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT',
68: 'GL1XC_PERF_SEL_UTCL0_GPA3_REQUEST',
}
GL1XC_PERF_SEL_CYCLE = 0
GL1XC_PERF_SEL_BUSY = 1
GL1XC_PERF_SEL_STARVE = 2
GL1XC_PERF_SEL_ARB_RET_LEVEL = 3
GL1XC_PERF_SEL_GL2_REQ_READ_LATENCY = 4
GL1XC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5
GL1XC_PERF_SEL_REQ = 6
GL1XC_PERF_SEL_REQ_ATOMIC_WITH_RET = 7
GL1XC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8
GL1XC_PERF_SEL_REQ_NOP_ACK = 9
GL1XC_PERF_SEL_REQ_NOP_RTN0 = 10
GL1XC_PERF_SEL_REQ_READ = 11
GL1XC_PERF_SEL_REQ_READ_128B = 12
GL1XC_PERF_SEL_REQ_READ_32B = 13
GL1XC_PERF_SEL_REQ_READ_64B = 14
GL1XC_PERF_SEL_REQ_WRITE = 15
GL1XC_PERF_SEL_REQ_WRITE_32B = 16
GL1XC_PERF_SEL_REQ_WRITE_64B = 17
GL1XC_PERF_SEL_STALL_GL2_GL1 = 18
GL1XC_PERF_SEL_STALL_BUFFER_FULL = 19
GL1XC_PERF_SEL_STALL_VM = 20
GL1XC_PERF_SEL_REQ_CLIENT0 = 21
GL1XC_PERF_SEL_REQ_CLIENT1 = 22
GL1XC_PERF_SEL_REQ_CLIENT2 = 23
GL1XC_PERF_SEL_REQ_CLIENT3 = 24
GL1XC_PERF_SEL_REQ_CLIENT4 = 25
GL1XC_PERF_SEL_REQ_CLIENT5 = 26
GL1XC_PERF_SEL_REQ_CLIENT6 = 27
GL1XC_PERF_SEL_REQ_CLIENT7 = 28
GL1XC_PERF_SEL_REQ_CLIENT8 = 29
GL1XC_PERF_SEL_REQ_CLIENT9 = 30
GL1XC_PERF_SEL_REQ_CLIENT10 = 31
GL1XC_PERF_SEL_REQ_CLIENT11 = 32
GL1XC_PERF_SEL_REQ_CLIENT12 = 33
GL1XC_PERF_SEL_REQ_CLIENT13 = 34
GL1XC_PERF_SEL_REQ_CLIENT14 = 35
GL1XC_PERF_SEL_REQ_CLIENT15 = 36
GL1XC_PERF_SEL_REQ_CLIENT16 = 37
GL1XC_PERF_SEL_REQ_CLIENT17 = 38
GL1XC_PERF_SEL_REQ_CLIENT18 = 39
GL1XC_PERF_SEL_REQ_CLIENT19 = 40
GL1XC_PERF_SEL_REQ_CLIENT20 = 41
GL1XC_PERF_SEL_REQ_CLIENT21 = 42
GL1XC_PERF_SEL_REQ_CLIENT22 = 43
GL1XC_PERF_SEL_REQ_CLIENT23 = 44
GL1XC_PERF_SEL_REQ_CLIENT24 = 45
GL1XC_PERF_SEL_REQ_CLIENT25 = 46
GL1XC_PERF_SEL_REQ_CLIENT26 = 47
GL1XC_PERF_SEL_REQ_CLIENT27 = 48
GL1XC_PERF_SEL_UTCL0_REQUEST = 49
GL1XC_PERF_SEL_UTCL0_TRANSLATION_HIT = 50
GL1XC_PERF_SEL_UTCL0_TRANSLATION_MISS = 51
GL1XC_PERF_SEL_UTCL0_PERMISSION_MISS = 52
GL1XC_PERF_SEL_UTCL0_MISS_UNDER_MISS = 53
GL1XC_PERF_SEL_UTCL0_LFIFO_FULL = 54
GL1XC_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 55
GL1XC_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 56
GL1XC_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 57
GL1XC_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 58
GL1XC_PERF_SEL_UTCL0_STALL_MULTI_MISS = 59
GL1XC_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 60
GL1XC_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 61
GL1XC_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 62
GL1XC_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 63
GL1XC_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 64
GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 65
GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 66
GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 67
GL1XC_PERF_SEL_UTCL0_GPA3_REQUEST = 68
GL1XC_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBMH_PERF_SEL'
GRBMH_PERF_SEL__enumvalues = {
0: 'GRBMH_PERF_SEL_COUNT',
1: 'GRBMH_PERF_SEL_USER_DEFINED',
2: 'GRBMH_PERF_SEL_CB_BUSY',
3: 'GRBMH_PERF_SEL_CB_CLEAN',
4: 'GRBMH_PERF_SEL_DB_BUSY',
5: 'GRBMH_PERF_SEL_DB_CLEAN',
6: 'GRBMH_PERF_SEL_SC_BUSY',
7: 'GRBMH_PERF_SEL_SC_CLEAN',
9: 'GRBMH_PERF_SEL_SPI_BUSY',
10: 'GRBMH_PERF_SEL_SX_BUSY',
11: 'GRBMH_PERF_SEL_TA_BUSY',
12: 'GRBMH_PERF_SEL_EA_BUSY',
13: 'GRBMH_PERF_SEL_EA_LINK_BUSY',
14: 'GRBMH_PERF_SEL_PA_BUSY',
15: 'GRBMH_PERF_SEL_BCI_BUSY',
16: 'GRBMH_PERF_SEL_GL2A_BUSY',
17: 'GRBMH_PERF_SEL_GL2C_BUSY',
18: 'GRBMH_PERF_SEL_UTCL1_BUSY',
19: 'GRBMH_PERF_SEL_TCP_BUSY',
20: 'GRBMH_PERF_SEL_GL1A_BUSY',
21: 'GRBMH_PERF_SEL_GL1CC_BUSY',
22: 'GRBMH_PERF_SEL_GL1XCC_BUSY',
23: 'GRBMH_PERF_SEL_PC_BUSY',
24: 'GRBMH_PERF_SEL_GE_BUSY',
25: 'GRBMH_PERF_SEL_RLC_BUSY',
}
GRBMH_PERF_SEL_COUNT = 0
GRBMH_PERF_SEL_USER_DEFINED = 1
GRBMH_PERF_SEL_CB_BUSY = 2
GRBMH_PERF_SEL_CB_CLEAN = 3
GRBMH_PERF_SEL_DB_BUSY = 4
GRBMH_PERF_SEL_DB_CLEAN = 5
GRBMH_PERF_SEL_SC_BUSY = 6
GRBMH_PERF_SEL_SC_CLEAN = 7
GRBMH_PERF_SEL_SPI_BUSY = 9
GRBMH_PERF_SEL_SX_BUSY = 10
GRBMH_PERF_SEL_TA_BUSY = 11
GRBMH_PERF_SEL_EA_BUSY = 12
GRBMH_PERF_SEL_EA_LINK_BUSY = 13
GRBMH_PERF_SEL_PA_BUSY = 14
GRBMH_PERF_SEL_BCI_BUSY = 15
GRBMH_PERF_SEL_GL2A_BUSY = 16
GRBMH_PERF_SEL_GL2C_BUSY = 17
GRBMH_PERF_SEL_UTCL1_BUSY = 18
GRBMH_PERF_SEL_TCP_BUSY = 19
GRBMH_PERF_SEL_GL1A_BUSY = 20
GRBMH_PERF_SEL_GL1CC_BUSY = 21
GRBMH_PERF_SEL_GL1XCC_BUSY = 22
GRBMH_PERF_SEL_PC_BUSY = 23
GRBMH_PERF_SEL_GE_BUSY = 24
GRBMH_PERF_SEL_RLC_BUSY = 25
GRBMH_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TA_PERFCOUNT_SEL'
TA_PERFCOUNT_SEL__enumvalues = {
0: 'TA_PERF_SEL_NULL',
1: 'TA_PERF_SEL_image_sampler_has_offset_instructions',
2: 'TA_PERF_SEL_image_sampler_has_bias_instructions',
3: 'TA_PERF_SEL_image_sampler_has_reference_instructions',
4: 'TA_PERF_SEL_image_sampler_has_ds_instructions',
5: 'TA_PERF_SEL_image_sampler_has_dt_instructions',
6: 'TA_PERF_SEL_image_sampler_has_dr_instructions',
7: 'TA_PERF_SEL_gradient_busy',
8: 'TA_PERF_SEL_gradient_fifo_busy',
9: 'TA_PERF_SEL_lod_busy',
10: 'TA_PERF_SEL_lod_fifo_busy',
11: 'TA_PERF_SEL_addresser_busy',
12: 'TA_PERF_SEL_addresser_fifo_busy',
13: 'TA_PERF_SEL_aligner_busy',
14: 'TA_PERF_SEL_write_path_busy',
15: 'TA_PERF_SEL_ta_busy',
16: 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions',
17: 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions',
18: 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions',
19: 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions',
20: 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions',
21: 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions',
22: 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions',
23: 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions',
24: 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions',
25: 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions',
26: 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions',
27: 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions',
28: 'TA_PERF_SEL_image_sampler_has_t_instructions',
29: 'TA_PERF_SEL_image_sampler_has_r_instructions',
30: 'TA_PERF_SEL_image_sampler_has_q_instructions',
32: 'TA_PERF_SEL_total_wavefronts',
33: 'TA_PERF_SEL_gradient_cycles',
34: 'TA_PERF_SEL_walker_cycles',
35: 'TA_PERF_SEL_aligner_cycles',
36: 'TA_PERF_SEL_image_wavefronts',
37: 'TA_PERF_SEL_image_read_wavefronts',
38: 'TA_PERF_SEL_image_store_wavefronts',
39: 'TA_PERF_SEL_image_atomic_wavefronts',
40: 'TA_PERF_SEL_image_sampler_total_cycles',
41: 'TA_PERF_SEL_image_nosampler_total_cycles',
42: 'TA_PERF_SEL_flat_total_cycles',
44: 'TA_PERF_SEL_buffer_wavefronts',
45: 'TA_PERF_SEL_buffer_load_wavefronts',
46: 'TA_PERF_SEL_buffer_store_wavefronts',
47: 'TA_PERF_SEL_buffer_atomic_wavefronts',
49: 'TA_PERF_SEL_buffer_total_cycles',
50: 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions',
51: 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions',
52: 'TA_PERF_SEL_buffer_has_index_instructions',
53: 'TA_PERF_SEL_buffer_has_offset_instructions',
54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles',
55: 'TA_PERF_SEL_addr_stalled_by_td_cycles',
56: 'TA_PERF_SEL_image_sampler_wavefronts',
57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles',
58: 'TA_PERF_SEL_addresser_stalled_cycles',
59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles',
60: 'TA_PERF_SEL_aniso_stalled_cycles',
61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles',
62: 'TA_PERF_SEL_deriv_stalled_cycles',
63: 'TA_PERF_SEL_aniso_gt1_cycle_quads',
64: 'TA_PERF_SEL_color_1_cycle_quads',
65: 'TA_PERF_SEL_color_2_cycle_quads',
66: 'TA_PERF_SEL_color_3_cycle_quads',
68: 'TA_PERF_SEL_mip_1_cycle_quads',
69: 'TA_PERF_SEL_mip_2_cycle_quads',
70: 'TA_PERF_SEL_vol_1_cycle_quads',
71: 'TA_PERF_SEL_vol_2_cycle_quads',
72: 'TA_PERF_SEL_sampler_op_quads',
73: 'TA_PERF_SEL_mipmap_lod_0_samples',
74: 'TA_PERF_SEL_mipmap_lod_1_samples',
75: 'TA_PERF_SEL_mipmap_lod_2_samples',
76: 'TA_PERF_SEL_mipmap_lod_3_samples',
77: 'TA_PERF_SEL_mipmap_lod_4_samples',
78: 'TA_PERF_SEL_mipmap_lod_5_samples',
79: 'TA_PERF_SEL_mipmap_lod_6_samples',
80: 'TA_PERF_SEL_mipmap_lod_7_samples',
81: 'TA_PERF_SEL_mipmap_lod_8_samples',
82: 'TA_PERF_SEL_mipmap_lod_9_samples',
83: 'TA_PERF_SEL_mipmap_lod_10_samples',
84: 'TA_PERF_SEL_mipmap_lod_11_samples',
85: 'TA_PERF_SEL_mipmap_lod_12_samples',
86: 'TA_PERF_SEL_mipmap_lod_13_samples',
87: 'TA_PERF_SEL_mipmap_lod_14_samples',
88: 'TA_PERF_SEL_mipmap_invalid_samples',
89: 'TA_PERF_SEL_aniso_1_cycle_quads',
90: 'TA_PERF_SEL_aniso_2_cycle_quads',
91: 'TA_PERF_SEL_aniso_4_cycle_quads',
92: 'TA_PERF_SEL_aniso_6_cycle_quads',
93: 'TA_PERF_SEL_aniso_8_cycle_quads',
94: 'TA_PERF_SEL_aniso_10_cycle_quads',
95: 'TA_PERF_SEL_aniso_12_cycle_quads',
96: 'TA_PERF_SEL_aniso_14_cycle_quads',
97: 'TA_PERF_SEL_aniso_16_cycle_quads',
98: 'TA_PERF_SEL_store_write_data_input_cycles',
99: 'TA_PERF_SEL_store_write_data_output_cycles',
100: 'TA_PERF_SEL_flat_wavefronts',
101: 'TA_PERF_SEL_flat_load_wavefronts',
102: 'TA_PERF_SEL_flat_store_wavefronts',
103: 'TA_PERF_SEL_flat_atomic_wavefronts',
104: 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions',
105: 'TA_PERF_SEL_register_clk_valid_cycles',
106: 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles',
107: 'TA_PERF_SEL_harvestable_clk_enabled_cycles',
108: 'TA_PERF_SEL_flat_2_address_input_vgpr_instructions',
109: 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles',
110: 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles',
112: 'TA_PERF_SEL_mipmap_lod_15_samples',
113: 'TA_PERF_SEL_mipmap_lod_16_samples',
114: 'TA_PERF_SEL_store_2_write_data_vgpr_instructions',
115: 'TA_PERF_SEL_store_3_write_data_vgpr_instructions',
116: 'TA_PERF_SEL_store_4_write_data_vgpr_instructions',
117: 'TA_PERF_SEL_store_has_x_instructions',
118: 'TA_PERF_SEL_store_has_y_instructions',
119: 'TA_PERF_SEL_store_has_z_instructions',
120: 'TA_PERF_SEL_store_has_w_instructions',
121: 'TA_PERF_SEL_image_nosampler_has_t_instructions',
122: 'TA_PERF_SEL_image_nosampler_has_r_instructions',
123: 'TA_PERF_SEL_image_nosampler_has_q_instructions',
124: 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions',
125: 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions',
126: 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions',
127: 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions',
128: 'TA_PERF_SEL_in_busy',
129: 'TA_PERF_SEL_in_fifos_busy',
130: 'TA_PERF_SEL_in_cfifo_busy',
131: 'TA_PERF_SEL_in_qfifo_busy',
132: 'TA_PERF_SEL_in_wfifo_busy',
133: 'TA_PERF_SEL_in_rfifo_busy',
134: 'TA_PERF_SEL_bf_busy',
135: 'TA_PERF_SEL_ns_busy',
136: 'TA_PERF_SEL_smp_busy_ns_idle',
137: 'TA_PERF_SEL_smp_idle_ns_busy',
144: 'TA_PERF_SEL_vmemcmd_cycles',
145: 'TA_PERF_SEL_vmemreq_cycles',
146: 'TA_PERF_SEL_in_waiting_on_req_cycles',
150: 'TA_PERF_SEL_in_addr_cycles',
151: 'TA_PERF_SEL_in_data_cycles',
160: 'TA_PERF_SEL_point_sampled_quads',
162: 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions',
163: 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions',
164: 'TA_PERF_SEL_atomic_write_data_input_cycles',
165: 'TA_PERF_SEL_atomic_write_data_output_cycles',
173: 'TA_PERF_SEL_num_unlit_nodes_ta_opt',
174: 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input',
175: 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob',
192: 'TA_PERF_SEL_image_sampler_1_op_burst',
193: 'TA_PERF_SEL_image_sampler_2to3_op_burst',
194: 'TA_PERF_SEL_image_sampler_4to7_op_burst',
195: 'TA_PERF_SEL_image_sampler_ge8_op_burst',
196: 'TA_PERF_SEL_image_linked_1_op_burst',
197: 'TA_PERF_SEL_image_linked_2to3_op_burst',
198: 'TA_PERF_SEL_image_linked_4to7_op_burst',
199: 'TA_PERF_SEL_image_linked_ge8_op_burst',
204: 'TA_PERF_SEL_image_nosampler_1_op_burst',
205: 'TA_PERF_SEL_image_nosampler_2to3_op_burst',
206: 'TA_PERF_SEL_image_nosampler_4to31_op_burst',
207: 'TA_PERF_SEL_image_nosampler_ge32_op_burst',
208: 'TA_PERF_SEL_buffer_flat_1_op_burst',
209: 'TA_PERF_SEL_buffer_flat_2to3_op_burst',
210: 'TA_PERF_SEL_buffer_flat_4to31_op_burst',
211: 'TA_PERF_SEL_buffer_flat_ge32_op_burst',
212: 'TA_PERF_SEL_write_1_op_burst',
213: 'TA_PERF_SEL_write_2to3_op_burst',
214: 'TA_PERF_SEL_write_4to31_op_burst',
215: 'TA_PERF_SEL_write_ge32_op_burst',
216: 'TA_PERF_SEL_ibubble_1_cycle_burst',
217: 'TA_PERF_SEL_ibubble_2to3_cycle_burst',
218: 'TA_PERF_SEL_ibubble_4to15_cycle_burst',
219: 'TA_PERF_SEL_ibubble_16to31_cycle_burst',
220: 'TA_PERF_SEL_ibubble_32to63_cycle_burst',
221: 'TA_PERF_SEL_ibubble_ge64_cycle_burst',
224: 'TA_PERF_SEL_sampler_clk_valid_cycles',
225: 'TA_PERF_SEL_nonsampler_clk_valid_cycles',
226: 'TA_PERF_SEL_buffer_flat_clk_valid_cycles',
227: 'TA_PERF_SEL_write_data_clk_valid_cycles',
228: 'TA_PERF_SEL_gradient_clk_valid_cycles',
229: 'TA_PERF_SEL_lod_aniso_clk_valid_cycles',
230: 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles',
231: 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles',
232: 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles',
233: 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles',
234: 'TA_PERF_SEL_aligner_clk_valid_cycles',
235: 'TA_PERF_SEL_tcreq_clk_valid_cycles',
}
TA_PERF_SEL_NULL = 0
TA_PERF_SEL_image_sampler_has_offset_instructions = 1
TA_PERF_SEL_image_sampler_has_bias_instructions = 2
TA_PERF_SEL_image_sampler_has_reference_instructions = 3
TA_PERF_SEL_image_sampler_has_ds_instructions = 4
TA_PERF_SEL_image_sampler_has_dt_instructions = 5
TA_PERF_SEL_image_sampler_has_dr_instructions = 6
TA_PERF_SEL_gradient_busy = 7
TA_PERF_SEL_gradient_fifo_busy = 8
TA_PERF_SEL_lod_busy = 9
TA_PERF_SEL_lod_fifo_busy = 10
TA_PERF_SEL_addresser_busy = 11
TA_PERF_SEL_addresser_fifo_busy = 12
TA_PERF_SEL_aligner_busy = 13
TA_PERF_SEL_write_path_busy = 14
TA_PERF_SEL_ta_busy = 15
TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 16
TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 17
TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 18
TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 19
TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 20
TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 21
TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 22
TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 23
TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 24
TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 25
TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 26
TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 27
TA_PERF_SEL_image_sampler_has_t_instructions = 28
TA_PERF_SEL_image_sampler_has_r_instructions = 29
TA_PERF_SEL_image_sampler_has_q_instructions = 30
TA_PERF_SEL_total_wavefronts = 32
TA_PERF_SEL_gradient_cycles = 33
TA_PERF_SEL_walker_cycles = 34
TA_PERF_SEL_aligner_cycles = 35
TA_PERF_SEL_image_wavefronts = 36
TA_PERF_SEL_image_read_wavefronts = 37
TA_PERF_SEL_image_store_wavefronts = 38
TA_PERF_SEL_image_atomic_wavefronts = 39
TA_PERF_SEL_image_sampler_total_cycles = 40
TA_PERF_SEL_image_nosampler_total_cycles = 41
TA_PERF_SEL_flat_total_cycles = 42
TA_PERF_SEL_buffer_wavefronts = 44
TA_PERF_SEL_buffer_load_wavefronts = 45
TA_PERF_SEL_buffer_store_wavefronts = 46
TA_PERF_SEL_buffer_atomic_wavefronts = 47
TA_PERF_SEL_buffer_total_cycles = 49
TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 50
TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 51
TA_PERF_SEL_buffer_has_index_instructions = 52
TA_PERF_SEL_buffer_has_offset_instructions = 53
TA_PERF_SEL_addr_stalled_by_tc_cycles = 54
TA_PERF_SEL_addr_stalled_by_td_cycles = 55
TA_PERF_SEL_image_sampler_wavefronts = 56
TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57
TA_PERF_SEL_addresser_stalled_cycles = 58
TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59
TA_PERF_SEL_aniso_stalled_cycles = 60
TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61
TA_PERF_SEL_deriv_stalled_cycles = 62
TA_PERF_SEL_aniso_gt1_cycle_quads = 63
TA_PERF_SEL_color_1_cycle_quads = 64
TA_PERF_SEL_color_2_cycle_quads = 65
TA_PERF_SEL_color_3_cycle_quads = 66
TA_PERF_SEL_mip_1_cycle_quads = 68
TA_PERF_SEL_mip_2_cycle_quads = 69
TA_PERF_SEL_vol_1_cycle_quads = 70
TA_PERF_SEL_vol_2_cycle_quads = 71
TA_PERF_SEL_sampler_op_quads = 72
TA_PERF_SEL_mipmap_lod_0_samples = 73
TA_PERF_SEL_mipmap_lod_1_samples = 74
TA_PERF_SEL_mipmap_lod_2_samples = 75
TA_PERF_SEL_mipmap_lod_3_samples = 76
TA_PERF_SEL_mipmap_lod_4_samples = 77
TA_PERF_SEL_mipmap_lod_5_samples = 78
TA_PERF_SEL_mipmap_lod_6_samples = 79
TA_PERF_SEL_mipmap_lod_7_samples = 80
TA_PERF_SEL_mipmap_lod_8_samples = 81
TA_PERF_SEL_mipmap_lod_9_samples = 82
TA_PERF_SEL_mipmap_lod_10_samples = 83
TA_PERF_SEL_mipmap_lod_11_samples = 84
TA_PERF_SEL_mipmap_lod_12_samples = 85
TA_PERF_SEL_mipmap_lod_13_samples = 86
TA_PERF_SEL_mipmap_lod_14_samples = 87
TA_PERF_SEL_mipmap_invalid_samples = 88
TA_PERF_SEL_aniso_1_cycle_quads = 89
TA_PERF_SEL_aniso_2_cycle_quads = 90
TA_PERF_SEL_aniso_4_cycle_quads = 91
TA_PERF_SEL_aniso_6_cycle_quads = 92
TA_PERF_SEL_aniso_8_cycle_quads = 93
TA_PERF_SEL_aniso_10_cycle_quads = 94
TA_PERF_SEL_aniso_12_cycle_quads = 95
TA_PERF_SEL_aniso_14_cycle_quads = 96
TA_PERF_SEL_aniso_16_cycle_quads = 97
TA_PERF_SEL_store_write_data_input_cycles = 98
TA_PERF_SEL_store_write_data_output_cycles = 99
TA_PERF_SEL_flat_wavefronts = 100
TA_PERF_SEL_flat_load_wavefronts = 101
TA_PERF_SEL_flat_store_wavefronts = 102
TA_PERF_SEL_flat_atomic_wavefronts = 103
TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 104
TA_PERF_SEL_register_clk_valid_cycles = 105
TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 106
TA_PERF_SEL_harvestable_clk_enabled_cycles = 107
TA_PERF_SEL_flat_2_address_input_vgpr_instructions = 108
TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 109
TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 110
TA_PERF_SEL_mipmap_lod_15_samples = 112
TA_PERF_SEL_mipmap_lod_16_samples = 113
TA_PERF_SEL_store_2_write_data_vgpr_instructions = 114
TA_PERF_SEL_store_3_write_data_vgpr_instructions = 115
TA_PERF_SEL_store_4_write_data_vgpr_instructions = 116
TA_PERF_SEL_store_has_x_instructions = 117
TA_PERF_SEL_store_has_y_instructions = 118
TA_PERF_SEL_store_has_z_instructions = 119
TA_PERF_SEL_store_has_w_instructions = 120
TA_PERF_SEL_image_nosampler_has_t_instructions = 121
TA_PERF_SEL_image_nosampler_has_r_instructions = 122
TA_PERF_SEL_image_nosampler_has_q_instructions = 123
TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 124
TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 125
TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 126
TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 127
TA_PERF_SEL_in_busy = 128
TA_PERF_SEL_in_fifos_busy = 129
TA_PERF_SEL_in_cfifo_busy = 130
TA_PERF_SEL_in_qfifo_busy = 131
TA_PERF_SEL_in_wfifo_busy = 132
TA_PERF_SEL_in_rfifo_busy = 133
TA_PERF_SEL_bf_busy = 134
TA_PERF_SEL_ns_busy = 135
TA_PERF_SEL_smp_busy_ns_idle = 136
TA_PERF_SEL_smp_idle_ns_busy = 137
TA_PERF_SEL_vmemcmd_cycles = 144
TA_PERF_SEL_vmemreq_cycles = 145
TA_PERF_SEL_in_waiting_on_req_cycles = 146
TA_PERF_SEL_in_addr_cycles = 150
TA_PERF_SEL_in_data_cycles = 151
TA_PERF_SEL_point_sampled_quads = 160
TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 162
TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 163
TA_PERF_SEL_atomic_write_data_input_cycles = 164
TA_PERF_SEL_atomic_write_data_output_cycles = 165
TA_PERF_SEL_num_unlit_nodes_ta_opt = 173
TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 174
TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 175
TA_PERF_SEL_image_sampler_1_op_burst = 192
TA_PERF_SEL_image_sampler_2to3_op_burst = 193
TA_PERF_SEL_image_sampler_4to7_op_burst = 194
TA_PERF_SEL_image_sampler_ge8_op_burst = 195
TA_PERF_SEL_image_linked_1_op_burst = 196
TA_PERF_SEL_image_linked_2to3_op_burst = 197
TA_PERF_SEL_image_linked_4to7_op_burst = 198
TA_PERF_SEL_image_linked_ge8_op_burst = 199
TA_PERF_SEL_image_nosampler_1_op_burst = 204
TA_PERF_SEL_image_nosampler_2to3_op_burst = 205
TA_PERF_SEL_image_nosampler_4to31_op_burst = 206
TA_PERF_SEL_image_nosampler_ge32_op_burst = 207
TA_PERF_SEL_buffer_flat_1_op_burst = 208
TA_PERF_SEL_buffer_flat_2to3_op_burst = 209
TA_PERF_SEL_buffer_flat_4to31_op_burst = 210
TA_PERF_SEL_buffer_flat_ge32_op_burst = 211
TA_PERF_SEL_write_1_op_burst = 212
TA_PERF_SEL_write_2to3_op_burst = 213
TA_PERF_SEL_write_4to31_op_burst = 214
TA_PERF_SEL_write_ge32_op_burst = 215
TA_PERF_SEL_ibubble_1_cycle_burst = 216
TA_PERF_SEL_ibubble_2to3_cycle_burst = 217
TA_PERF_SEL_ibubble_4to15_cycle_burst = 218
TA_PERF_SEL_ibubble_16to31_cycle_burst = 219
TA_PERF_SEL_ibubble_32to63_cycle_burst = 220
TA_PERF_SEL_ibubble_ge64_cycle_burst = 221
TA_PERF_SEL_sampler_clk_valid_cycles = 224
TA_PERF_SEL_nonsampler_clk_valid_cycles = 225
TA_PERF_SEL_buffer_flat_clk_valid_cycles = 226
TA_PERF_SEL_write_data_clk_valid_cycles = 227
TA_PERF_SEL_gradient_clk_valid_cycles = 228
TA_PERF_SEL_lod_aniso_clk_valid_cycles = 229
TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 230
TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 231
TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 232
TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 233
TA_PERF_SEL_aligner_clk_valid_cycles = 234
TA_PERF_SEL_tcreq_clk_valid_cycles = 235
TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TEX_BC_SWIZZLE'
TEX_BC_SWIZZLE__enumvalues = {
0: 'TEX_BC_Swizzle_XYZW',
1: 'TEX_BC_Swizzle_XWYZ',
2: 'TEX_BC_Swizzle_WZYX',
3: 'TEX_BC_Swizzle_WXYZ',
4: 'TEX_BC_Swizzle_ZYXW',
5: 'TEX_BC_Swizzle_YXWZ',
}
TEX_BC_Swizzle_XYZW = 0
TEX_BC_Swizzle_XWYZ = 1
TEX_BC_Swizzle_WZYX = 2
TEX_BC_Swizzle_WXYZ = 3
TEX_BC_Swizzle_ZYXW = 4
TEX_BC_Swizzle_YXWZ = 5
TEX_BC_SWIZZLE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_BORDER_COLOR_TYPE'
TEX_BORDER_COLOR_TYPE__enumvalues = {
0: 'TEX_BorderColor_TransparentBlack',
1: 'TEX_BorderColor_OpaqueBlack',
2: 'TEX_BorderColor_OpaqueWhite',
3: 'TEX_BorderColor_Register',
}
TEX_BorderColor_TransparentBlack = 0
TEX_BorderColor_OpaqueBlack = 1
TEX_BorderColor_OpaqueWhite = 2
TEX_BorderColor_Register = 3
TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_CHROMA_KEY'
TEX_CHROMA_KEY__enumvalues = {
0: 'TEX_ChromaKey_Disabled',
1: 'TEX_ChromaKey_Kill',
2: 'TEX_ChromaKey_Blend',
3: 'TEX_ChromaKey_RESERVED_3',
}
TEX_ChromaKey_Disabled = 0
TEX_ChromaKey_Kill = 1
TEX_ChromaKey_Blend = 2
TEX_ChromaKey_RESERVED_3 = 3
TEX_CHROMA_KEY = ctypes.c_uint32 # enum
# values for enumeration 'TEX_CLAMP'
TEX_CLAMP__enumvalues = {
0: 'TEX_Clamp_Repeat',
1: 'TEX_Clamp_Mirror',
2: 'TEX_Clamp_ClampToLast',
3: 'TEX_Clamp_MirrorOnceToLast',
4: 'TEX_Clamp_ClampHalfToBorder',
5: 'TEX_Clamp_MirrorOnceHalfToBorder',
6: 'TEX_Clamp_ClampToBorder',
7: 'TEX_Clamp_MirrorOnceToBorder',
}
TEX_Clamp_Repeat = 0
TEX_Clamp_Mirror = 1
TEX_Clamp_ClampToLast = 2
TEX_Clamp_MirrorOnceToLast = 3
TEX_Clamp_ClampHalfToBorder = 4
TEX_Clamp_MirrorOnceHalfToBorder = 5
TEX_Clamp_ClampToBorder = 6
TEX_Clamp_MirrorOnceToBorder = 7
TEX_CLAMP = ctypes.c_uint32 # enum
# values for enumeration 'TEX_COORD_TYPE'
TEX_COORD_TYPE__enumvalues = {
0: 'TEX_CoordType_Unnormalized',
1: 'TEX_CoordType_Normalized',
}
TEX_CoordType_Unnormalized = 0
TEX_CoordType_Normalized = 1
TEX_COORD_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION'
TEX_DEPTH_COMPARE_FUNCTION__enumvalues = {
0: 'TEX_DepthCompareFunction_Never',
1: 'TEX_DepthCompareFunction_Less',
2: 'TEX_DepthCompareFunction_Equal',
3: 'TEX_DepthCompareFunction_LessEqual',
4: 'TEX_DepthCompareFunction_Greater',
5: 'TEX_DepthCompareFunction_NotEqual',
6: 'TEX_DepthCompareFunction_GreaterEqual',
7: 'TEX_DepthCompareFunction_Always',
}
TEX_DepthCompareFunction_Never = 0
TEX_DepthCompareFunction_Less = 1
TEX_DepthCompareFunction_Equal = 2
TEX_DepthCompareFunction_LessEqual = 3
TEX_DepthCompareFunction_Greater = 4
TEX_DepthCompareFunction_NotEqual = 5
TEX_DepthCompareFunction_GreaterEqual = 6
TEX_DepthCompareFunction_Always = 7
TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum
# values for enumeration 'TEX_FORMAT_COMP'
TEX_FORMAT_COMP__enumvalues = {
0: 'TEX_FormatComp_Unsigned',
1: 'TEX_FormatComp_Signed',
2: 'TEX_FormatComp_UnsignedBiased',
3: 'TEX_FormatComp_RESERVED_3',
}
TEX_FormatComp_Unsigned = 0
TEX_FormatComp_Signed = 1
TEX_FormatComp_UnsignedBiased = 2
TEX_FormatComp_RESERVED_3 = 3
TEX_FORMAT_COMP = ctypes.c_uint32 # enum
# values for enumeration 'TEX_MAX_ANISO_RATIO'
TEX_MAX_ANISO_RATIO__enumvalues = {
0: 'TEX_MaxAnisoRatio_1to1',
1: 'TEX_MaxAnisoRatio_2to1',
2: 'TEX_MaxAnisoRatio_4to1',
3: 'TEX_MaxAnisoRatio_8to1',
4: 'TEX_MaxAnisoRatio_16to1',
5: 'TEX_MaxAnisoRatio_RESERVED_5',
6: 'TEX_MaxAnisoRatio_RESERVED_6',
7: 'TEX_MaxAnisoRatio_RESERVED_7',
}
TEX_MaxAnisoRatio_1to1 = 0
TEX_MaxAnisoRatio_2to1 = 1
TEX_MaxAnisoRatio_4to1 = 2
TEX_MaxAnisoRatio_8to1 = 3
TEX_MaxAnisoRatio_16to1 = 4
TEX_MaxAnisoRatio_RESERVED_5 = 5
TEX_MaxAnisoRatio_RESERVED_6 = 6
TEX_MaxAnisoRatio_RESERVED_7 = 7
TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum
# values for enumeration 'TEX_MIP_FILTER'
TEX_MIP_FILTER__enumvalues = {
0: 'TEX_MipFilter_None',
1: 'TEX_MipFilter_Point',
2: 'TEX_MipFilter_Linear',
3: 'TEX_MipFilter_Point_Aniso_Adj',
}
TEX_MipFilter_None = 0
TEX_MipFilter_Point = 1
TEX_MipFilter_Linear = 2
TEX_MipFilter_Point_Aniso_Adj = 3
TEX_MIP_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'TEX_REQUEST_SIZE'
TEX_REQUEST_SIZE__enumvalues = {
0: 'TEX_RequestSize_32B',
1: 'TEX_RequestSize_64B',
2: 'TEX_RequestSize_128B',
3: 'TEX_RequestSize_2X64B',
}
TEX_RequestSize_32B = 0
TEX_RequestSize_64B = 1
TEX_RequestSize_128B = 2
TEX_RequestSize_2X64B = 3
TEX_REQUEST_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_SAMPLER_TYPE'
TEX_SAMPLER_TYPE__enumvalues = {
0: 'TEX_SamplerType_Invalid',
1: 'TEX_SamplerType_Valid',
}
TEX_SamplerType_Invalid = 0
TEX_SamplerType_Valid = 1
TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_XY_FILTER'
TEX_XY_FILTER__enumvalues = {
0: 'TEX_XYFilter_Point',
1: 'TEX_XYFilter_Linear',
2: 'TEX_XYFilter_AnisoPoint',
3: 'TEX_XYFilter_AnisoLinear',
}
TEX_XYFilter_Point = 0
TEX_XYFilter_Linear = 1
TEX_XYFilter_AnisoPoint = 2
TEX_XYFilter_AnisoLinear = 3
TEX_XY_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'TEX_Z_FILTER'
TEX_Z_FILTER__enumvalues = {
0: 'TEX_ZFilter_None',
1: 'TEX_ZFilter_Point',
2: 'TEX_ZFilter_Linear',
3: 'TEX_ZFilter_RESERVED_3',
}
TEX_ZFilter_None = 0
TEX_ZFilter_Point = 1
TEX_ZFilter_Linear = 2
TEX_ZFilter_RESERVED_3 = 3
TEX_Z_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'TVX_TYPE'
TVX_TYPE__enumvalues = {
0: 'TVX_Type_InvalidTextureResource',
1: 'TVX_Type_InvalidVertexBuffer',
2: 'TVX_Type_ValidTextureResource',
3: 'TVX_Type_ValidVertexBuffer',
}
TVX_Type_InvalidTextureResource = 0
TVX_Type_InvalidVertexBuffer = 1
TVX_Type_ValidTextureResource = 2
TVX_Type_ValidVertexBuffer = 3
TVX_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'TA_TC_ADDR_MODES'
TA_TC_ADDR_MODES__enumvalues = {
0: 'TA_TC_ADDR_MODE_DEFAULT',
1: 'TA_TC_ADDR_MODE_COMP0',
2: 'TA_TC_ADDR_MODE_COMP1',
3: 'TA_TC_ADDR_MODE_COMP2',
4: 'TA_TC_ADDR_MODE_COMP3',
5: 'TA_TC_ADDR_MODE_UNALIGNED',
6: 'TA_TC_ADDR_MODE_BORDER_COLOR',
}
TA_TC_ADDR_MODE_DEFAULT = 0
TA_TC_ADDR_MODE_COMP0 = 1
TA_TC_ADDR_MODE_COMP1 = 2
TA_TC_ADDR_MODE_COMP2 = 3
TA_TC_ADDR_MODE_COMP3 = 4
TA_TC_ADDR_MODE_UNALIGNED = 5
TA_TC_ADDR_MODE_BORDER_COLOR = 6
TA_TC_ADDR_MODES = ctypes.c_uint32 # enum
# values for enumeration 'TA_TC_REQ_MODES'
TA_TC_REQ_MODES__enumvalues = {
0: 'TA_TC_REQ_MODE_BORDER',
1: 'TA_TC_REQ_MODE_TEX2',
2: 'TA_TC_REQ_MODE_TEX1',
3: 'TA_TC_REQ_MODE_TEX0',
4: 'TA_TC_REQ_MODE_NORMAL',
5: 'TA_TC_REQ_MODE_DWORD',
6: 'TA_TC_REQ_MODE_BYTE',
7: 'TA_TC_REQ_MODE_BYTE_NV',
}
TA_TC_REQ_MODE_BORDER = 0
TA_TC_REQ_MODE_TEX2 = 1
TA_TC_REQ_MODE_TEX1 = 2
TA_TC_REQ_MODE_TEX0 = 3
TA_TC_REQ_MODE_NORMAL = 4
TA_TC_REQ_MODE_DWORD = 5
TA_TC_REQ_MODE_BYTE = 6
TA_TC_REQ_MODE_BYTE_NV = 7
TA_TC_REQ_MODES = ctypes.c_uint32 # enum
# values for enumeration 'TCP_CACHE_POLICIES'
TCP_CACHE_POLICIES__enumvalues = {
0: 'TCP_CACHE_POLICY_MISS_LRU',
1: 'TCP_CACHE_POLICY_MISS_EVICT',
2: 'TCP_CACHE_POLICY_HIT_LRU',
3: 'TCP_CACHE_POLICY_HIT_EVICT',
}
TCP_CACHE_POLICY_MISS_LRU = 0
TCP_CACHE_POLICY_MISS_EVICT = 1
TCP_CACHE_POLICY_HIT_LRU = 2
TCP_CACHE_POLICY_HIT_EVICT = 3
TCP_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'TCP_CACHE_STORE_POLICIES'
TCP_CACHE_STORE_POLICIES__enumvalues = {
0: 'TCP_CACHE_STORE_POLICY_WT_LRU',
1: 'TCP_CACHE_STORE_POLICY_WT_EVICT',
}
TCP_CACHE_STORE_POLICY_WT_LRU = 0
TCP_CACHE_STORE_POLICY_WT_EVICT = 1
TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'TCP_COMPRESSION_BYPASS'
TCP_COMPRESSION_BYPASS__enumvalues = {
0: 'TCP_COMPRESSION_BYPASS_DIS',
1: 'TCP_COMPRESSION_BYPASS_EN',
}
TCP_COMPRESSION_BYPASS_DIS = 0
TCP_COMPRESSION_BYPASS_EN = 1
TCP_COMPRESSION_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'TCP_COMPRESSION_OVERRIDE'
TCP_COMPRESSION_OVERRIDE__enumvalues = {
0: 'TCP_COMPRESSION_OVERRIDE_DIS',
1: 'TCP_COMPRESSION_OVERRIDE_EN',
}
TCP_COMPRESSION_OVERRIDE_DIS = 0
TCP_COMPRESSION_OVERRIDE_EN = 1
TCP_COMPRESSION_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'TCP_OPCODE_TYPE'
TCP_OPCODE_TYPE__enumvalues = {
0: 'TCP_OPCODE_READ',
1: 'TCP_OPCODE_WRITE',
2: 'TCP_OPCODE_ATOMIC',
3: 'TCP_OPCODE_INV',
4: 'TCP_OPCODE_ATOMIC_CMPSWAP',
5: 'TCP_OPCODE_SAMPLER',
6: 'TCP_OPCODE_LOAD',
7: 'TCP_OPCODE_GATHERH',
}
TCP_OPCODE_READ = 0
TCP_OPCODE_WRITE = 1
TCP_OPCODE_ATOMIC = 2
TCP_OPCODE_INV = 3
TCP_OPCODE_ATOMIC_CMPSWAP = 4
TCP_OPCODE_SAMPLER = 5
TCP_OPCODE_LOAD = 6
TCP_OPCODE_GATHERH = 7
TCP_OPCODE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'TCP_PERFCOUNT_SELECT'
TCP_PERFCOUNT_SELECT__enumvalues = {
0: 'TCP_PERF_SEL_GATE_EN1',
1: 'TCP_PERF_SEL_GATE_EN2',
2: 'TCP_PERF_SEL_TA_REQ',
3: 'TCP_PERF_SEL_TA_REQ_STATE_READ',
4: 'TCP_PERF_SEL_TA_REQ_READ',
5: 'TCP_PERF_SEL_TA_REQ_WRITE',
6: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET',
7: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET',
8: 'TCP_PERF_SEL_TA_REQ_GL0_INV',
9: 'TCP_PERF_SEL_REQ',
10: 'TCP_PERF_SEL_REQ_READ',
12: 'TCP_PERF_SEL_REQ_READ_HIT_LRU',
13: 'TCP_PERF_SEL_REQ_READ_MISS_EVICT',
14: 'TCP_PERF_SEL_REQ_WRITE',
15: 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT',
16: 'TCP_PERF_SEL_REQ_NON_READ',
17: 'TCP_PERF_SEL_REQ_MISS',
18: 'TCP_PERF_SEL_REQ_TAGBANK0_SET0',
19: 'TCP_PERF_SEL_REQ_TAGBANK0_SET1',
20: 'TCP_PERF_SEL_REQ_TAGBANK1_SET0',
21: 'TCP_PERF_SEL_REQ_TAGBANK1_SET1',
22: 'TCP_PERF_SEL_REQ_TAGBANK2_SET0',
23: 'TCP_PERF_SEL_REQ_TAGBANK2_SET1',
24: 'TCP_PERF_SEL_REQ_TAGBANK3_SET0',
25: 'TCP_PERF_SEL_REQ_TAGBANK3_SET1',
26: 'TCP_PERF_SEL_REQ_MISS_TAGBANK0',
27: 'TCP_PERF_SEL_REQ_MISS_TAGBANK1',
28: 'TCP_PERF_SEL_REQ_MISS_TAGBANK2',
29: 'TCP_PERF_SEL_REQ_MISS_TAGBANK3',
30: 'TCP_PERF_SEL_GL1_REQ_READ',
31: 'TCP_PERF_SEL_GL1_REQ_READ_128B',
32: 'TCP_PERF_SEL_GL1_REQ_READ_64B',
33: 'TCP_PERF_SEL_GL1_REQ_WRITE',
34: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET',
35: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET',
36: 'TCP_PERF_SEL_GL1_READ_LATENCY',
37: 'TCP_PERF_SEL_GL1_WRITE_LATENCY',
38: 'TCP_PERF_SEL_TCP_LATENCY',
39: 'TCP_PERF_SEL_TCP_TA_REQ_STALL',
40: 'TCP_PERF_SEL_TA_TCP_REQ_STARVE',
41: 'TCP_PERF_SEL_DATA_FIFO_STALL',
42: 'TCP_PERF_SEL_LOD_STALL',
43: 'TCP_PERF_SEL_POWER_STALL',
44: 'TCP_PERF_SEL_ALLOC_STALL',
46: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL',
47: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL',
48: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL',
49: 'TCP_PERF_SEL_LFIFO_STALL',
50: 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL',
51: 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE',
52: 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL',
53: 'TCP_PERF_SEL_GL1_GRANT_READ_STALL',
54: 'TCP_PERF_SEL_GL1_PENDING_STALL',
55: 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL',
56: 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL',
57: 'TCP_PERF_SEL_READ_DATACONFLICT_STALL',
58: 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL',
59: 'TCP_PERF_SEL_TD_TCP_STALL',
60: 'TCP_PERF_SEL_TA_REQ_BUFFERNOP',
61: 'TCP_PERF_SEL_WRITECOMBINE_ENDCLAUSE',
62: 'TCP_PERF_SEL_TAGFAKE_EOW',
63: 'TCP_PERF_SEL_REQ_TAG_MATCH_AND_NOT_VALID',
64: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_0',
65: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_1to2',
66: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_3to4',
67: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_5to8',
68: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_9to16',
70: 'TCP_PERF_SEL_BURST_BIN_READHIT_0',
71: 'TCP_PERF_SEL_BURST_BIN_READHIT_1',
72: 'TCP_PERF_SEL_BURST_BIN_READHIT_2to4',
73: 'TCP_PERF_SEL_BURST_BIN_READHIT_5to8',
74: 'TCP_PERF_SEL_BURST_BIN_READHIT_9to16',
75: 'TCP_PERF_SEL_BURST_BIN_READHIT_gt16',
76: 'TCP_PERF_SEL_TA_TC_REQ_EN_SUM',
77: 'TCP_PERF_SEL_GL1_REQ_LU',
78: 'TCP_PERF_SEL_REQ_TAG_MATCH_AND_LU_INVALIDATE',
}
TCP_PERF_SEL_GATE_EN1 = 0
TCP_PERF_SEL_GATE_EN2 = 1
TCP_PERF_SEL_TA_REQ = 2
TCP_PERF_SEL_TA_REQ_STATE_READ = 3
TCP_PERF_SEL_TA_REQ_READ = 4
TCP_PERF_SEL_TA_REQ_WRITE = 5
TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 6
TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 7
TCP_PERF_SEL_TA_REQ_GL0_INV = 8
TCP_PERF_SEL_REQ = 9
TCP_PERF_SEL_REQ_READ = 10
TCP_PERF_SEL_REQ_READ_HIT_LRU = 12
TCP_PERF_SEL_REQ_READ_MISS_EVICT = 13
TCP_PERF_SEL_REQ_WRITE = 14
TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 15
TCP_PERF_SEL_REQ_NON_READ = 16
TCP_PERF_SEL_REQ_MISS = 17
TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 18
TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 19
TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 20
TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 21
TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 22
TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 23
TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 24
TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 25
TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 26
TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 27
TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 28
TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 29
TCP_PERF_SEL_GL1_REQ_READ = 30
TCP_PERF_SEL_GL1_REQ_READ_128B = 31
TCP_PERF_SEL_GL1_REQ_READ_64B = 32
TCP_PERF_SEL_GL1_REQ_WRITE = 33
TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 34
TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 35
TCP_PERF_SEL_GL1_READ_LATENCY = 36
TCP_PERF_SEL_GL1_WRITE_LATENCY = 37
TCP_PERF_SEL_TCP_LATENCY = 38
TCP_PERF_SEL_TCP_TA_REQ_STALL = 39
TCP_PERF_SEL_TA_TCP_REQ_STARVE = 40
TCP_PERF_SEL_DATA_FIFO_STALL = 41
TCP_PERF_SEL_LOD_STALL = 42
TCP_PERF_SEL_POWER_STALL = 43
TCP_PERF_SEL_ALLOC_STALL = 44
TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 46
TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 47
TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 48
TCP_PERF_SEL_LFIFO_STALL = 49
TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 50
TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 51
TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 52
TCP_PERF_SEL_GL1_GRANT_READ_STALL = 53
TCP_PERF_SEL_GL1_PENDING_STALL = 54
TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 55
TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 56
TCP_PERF_SEL_READ_DATACONFLICT_STALL = 57
TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 58
TCP_PERF_SEL_TD_TCP_STALL = 59
TCP_PERF_SEL_TA_REQ_BUFFERNOP = 60
TCP_PERF_SEL_WRITECOMBINE_ENDCLAUSE = 61
TCP_PERF_SEL_TAGFAKE_EOW = 62
TCP_PERF_SEL_REQ_TAG_MATCH_AND_NOT_VALID = 63
TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_0 = 64
TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_1to2 = 65
TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_3to4 = 66
TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_5to8 = 67
TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_9to16 = 68
TCP_PERF_SEL_BURST_BIN_READHIT_0 = 70
TCP_PERF_SEL_BURST_BIN_READHIT_1 = 71
TCP_PERF_SEL_BURST_BIN_READHIT_2to4 = 72
TCP_PERF_SEL_BURST_BIN_READHIT_5to8 = 73
TCP_PERF_SEL_BURST_BIN_READHIT_9to16 = 74
TCP_PERF_SEL_BURST_BIN_READHIT_gt16 = 75
TCP_PERF_SEL_TA_TC_REQ_EN_SUM = 76
TCP_PERF_SEL_GL1_REQ_LU = 77
TCP_PERF_SEL_REQ_TAG_MATCH_AND_LU_INVALIDATE = 78
TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'TCP_WATCH_MODES'
TCP_WATCH_MODES__enumvalues = {
0: 'TCP_WATCH_MODE_READ',
1: 'TCP_WATCH_MODE_NONREAD',
2: 'TCP_WATCH_MODE_ATOMIC',
3: 'TCP_WATCH_MODE_ALL',
}
TCP_WATCH_MODE_READ = 0
TCP_WATCH_MODE_NONREAD = 1
TCP_WATCH_MODE_ATOMIC = 2
TCP_WATCH_MODE_ALL = 3
TCP_WATCH_MODES = ctypes.c_uint32 # enum
# values for enumeration 'TCP_WRITE_COMPRESSION_DISABLE'
TCP_WRITE_COMPRESSION_DISABLE__enumvalues = {
0: 'TCP_WRITE_COMPRESSION_DISABLE_DIS',
1: 'TCP_WRITE_COMPRESSION_DISABLE_EN',
}
TCP_WRITE_COMPRESSION_DISABLE_DIS = 0
TCP_WRITE_COMPRESSION_DISABLE_EN = 1
TCP_WRITE_COMPRESSION_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'TD_PERFCOUNT_SEL'
TD_PERFCOUNT_SEL__enumvalues = {
0: 'TD_PERF_SEL_none',
1: 'TD_PERF_SEL_td_busy',
2: 'TD_PERF_SEL_input_busy',
3: 'TD_PERF_SEL_sampler_lerp_busy',
4: 'TD_PERF_SEL_sampler_out_busy',
5: 'TD_PERF_SEL_nofilter_busy',
7: 'TD_PERF_SEL_sampler_core_sclk_en',
8: 'TD_PERF_SEL_sampler_preformatter_sclk_en',
9: 'TD_PERF_SEL_sampler_bilerp_sclk_en',
10: 'TD_PERF_SEL_sampler_bypass_sclk_en',
11: 'TD_PERF_SEL_sampler_minmax_sclk_en',
12: 'TD_PERF_SEL_sampler_accum_sclk_en',
13: 'TD_PERF_SEL_sampler_format_flt_sclk_en',
14: 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en',
15: 'TD_PERF_SEL_sampler_out_sclk_en',
16: 'TD_PERF_SEL_nofilter_sclk_en',
17: 'TD_PERF_SEL_nofilter_d32_sclk_en',
18: 'TD_PERF_SEL_nofilter_d16_sclk_en',
26: 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off',
27: 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off',
28: 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time',
32: 'TD_PERF_SEL_core_state_ram_max_cnt',
33: 'TD_PERF_SEL_core_state_rams_read',
34: 'TD_PERF_SEL_weight_data_rams_read',
35: 'TD_PERF_SEL_reference_data_rams_read',
36: 'TD_PERF_SEL_tc_td_ram_fifo_full',
37: 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt',
38: 'TD_PERF_SEL_tc_td_data_fifo_full',
39: 'TD_PERF_SEL_input_state_fifo_full',
40: 'TD_PERF_SEL_ta_data_stall',
41: 'TD_PERF_SEL_tc_data_stall',
42: 'TD_PERF_SEL_tc_ram_stall',
43: 'TD_PERF_SEL_lds_stall',
44: 'TD_PERF_SEL_sampler_pkr_full',
45: 'TD_PERF_SEL_sampler_pkr_full_due_to_arb',
46: 'TD_PERF_SEL_nofilter_pkr_full',
47: 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb',
50: 'TD_PERF_SEL_gather4_instr',
51: 'TD_PERF_SEL_gather4h_instr',
52: 'TD_PERF_SEL_getlod_instr',
54: 'TD_PERF_SEL_sample_instr',
55: 'TD_PERF_SEL_sample_c_instr',
56: 'TD_PERF_SEL_load_instr',
57: 'TD_PERF_SEL_ps_load_instr',
58: 'TD_PERF_SEL_write_ack_instr',
59: 'TD_PERF_SEL_d16_en_instr',
60: 'TD_PERF_SEL_bypassLerp_instr',
61: 'TD_PERF_SEL_min_max_filter_instr',
62: 'TD_PERF_SEL_one_comp_return_instr',
63: 'TD_PERF_SEL_two_comp_return_instr',
64: 'TD_PERF_SEL_three_comp_return_instr',
65: 'TD_PERF_SEL_four_comp_return_instr',
66: 'TD_PERF_SEL_user_defined_border',
67: 'TD_PERF_SEL_white_border',
68: 'TD_PERF_SEL_opaque_black_border',
69: 'TD_PERF_SEL_lod_warn_from_ta',
70: 'TD_PERF_SEL_instruction_dest_is_lds',
71: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles',
72: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles',
73: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles',
74: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles',
75: 'TD_PERF_SEL_out_of_order_instr',
76: 'TD_PERF_SEL_total_num_instr',
77: 'TD_PERF_SEL_total_num_instr_with_perf_wdw',
78: 'TD_PERF_SEL_total_num_sampler_instr',
79: 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw',
80: 'TD_PERF_SEL_total_num_nofilter_instr',
81: 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw',
84: 'TD_PERF_SEL_mixmode_instr',
85: 'TD_PERF_SEL_mixmode_resource',
86: 'TD_PERF_SEL_status_packet',
89: 'TD_PERF_SEL_done_scoreboard_max_stored_cnt',
90: 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt',
91: 'TD_PERF_SEL_done_scoreboard_not_empty',
92: 'TD_PERF_SEL_done_scoreboard_is_full',
93: 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo',
94: 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds',
95: 'TD_PERF_SEL_nofilter_formatters_turned_on',
96: 'TD_PERF_SEL_nofilter_insert_extra_comps',
97: 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt',
98: 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt',
99: 'TD_PERF_SEL_msaa_load_instr',
100: 'TD_PERF_SEL_blend_prt_with_prt_default_0',
102: 'TD_PERF_SEL_resmap_instr',
103: 'TD_PERF_SEL_prt_ack_instr',
104: 'TD_PERF_SEL_resmap_with_volume_filtering',
105: 'TD_PERF_SEL_resmap_with_aniso_filtering',
106: 'TD_PERF_SEL_resmap_with_no_more_filtering',
107: 'TD_PERF_SEL_resmap_with_cubemap_corner',
131: 'TD_PERF_SEL_burst_bin_preempting_nofilter_1',
132: 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4',
133: 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7',
134: 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16',
135: 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16',
136: 'TD_PERF_SEL_burst_bin_sampler_1',
137: 'TD_PERF_SEL_burst_bin_sampler_2to8',
138: 'TD_PERF_SEL_burst_bin_sampler_9to16',
139: 'TD_PERF_SEL_burst_bin_sampler_gt16',
140: 'TD_PERF_SEL_burst_bin_gather_1',
141: 'TD_PERF_SEL_burst_bin_gather_2to8',
142: 'TD_PERF_SEL_burst_bin_gather_9to16',
143: 'TD_PERF_SEL_burst_bin_gather_gt16',
144: 'TD_PERF_SEL_burst_bin_nofilter_1',
145: 'TD_PERF_SEL_burst_bin_nofilter_2to4',
146: 'TD_PERF_SEL_burst_bin_nofilter_5to7',
147: 'TD_PERF_SEL_burst_bin_nofilter_8to16',
148: 'TD_PERF_SEL_burst_bin_nofilter_gt16',
170: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0',
171: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1',
172: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31',
173: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127',
174: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511',
175: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511',
176: 'TD_PERF_SEL_bubble_bin_lds_stall_1to3',
177: 'TD_PERF_SEL_bubble_bin_lds_stall_4to7',
178: 'TD_PERF_SEL_bubble_bin_lds_stall_8to15',
179: 'TD_PERF_SEL_bubble_bin_lds_stall_gt15',
180: 'TD_PERF_SEL_preempting_nofilter_max_cnt',
181: 'TD_PERF_SEL_sampler_lerp0_active',
182: 'TD_PERF_SEL_sampler_lerp1_active',
183: 'TD_PERF_SEL_sampler_lerp2_active',
184: 'TD_PERF_SEL_sampler_lerp3_active',
185: 'TD_PERF_SEL_sampler_lerp4_active',
186: 'TD_PERF_SEL_sampler_lerp5_active',
187: 'TD_PERF_SEL_sampler_lerp6_active',
188: 'TD_PERF_SEL_sampler_lerp7_active',
189: 'TD_PERF_SEL_nofilter_total_num_comps_to_lds',
190: 'TD_PERF_SEL_nofilter_byte_cycling_4cycles',
191: 'TD_PERF_SEL_nofilter_byte_cycling_8cycles',
192: 'TD_PERF_SEL_nofilter_byte_cycling_16cycles',
193: 'TD_PERF_SEL_nofilter_dword_cycling_2cycles',
194: 'TD_PERF_SEL_nofilter_dword_cycling_4cycles',
195: 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full',
200: 'TD_PERF_SEL_store_preempts_a_load',
201: 'TD_PERF_SEL_sample_2x_instr',
202: 'TD_PERF_SEL_gather4_2x_instr',
203: 'TD_PERF_SEL_gather4h_2x_instr',
204: 'TD_PERF_SEL_getlod_2x_instr',
205: 'TD_PERF_SEL_resmap_2x_instr',
206: 'TD_PERF_SEL_2x_sampler_op_with_1_unlit_quad',
207: 'TD_PERF_SEL_2x_sampler_op_with_both_quads_unlit',
208: 'TD_PERF_SEL_tri_proc_node_override_slot0',
209: 'TD_PERF_SEL_tri_run_intersect_ahs_slot0',
210: 'TD_PERF_SEL_tri_run_ahs_slot0',
231: 'TD_PERF_SEL_tri_proc_node_override_slot1',
232: 'TD_PERF_SEL_tri_run_intersect_ahs_slot1',
233: 'TD_PERF_SEL_tri_run_ahs_slot1',
241: 'TD_PERF_SEL_instance_mask_culled',
242: 'TD_PERF_SEL_box_opaque_culled',
243: 'TD_PERF_SEL_box_non_opaque_culled',
244: 'TD_PERF_SEL_box_with_triangle_children_only_culled',
245: 'TD_PERF_SEL_box_with_procedural_children_only_culled',
246: 'TD_PERF_SEL_triangle_opaque_culled',
247: 'TD_PERF_SEL_triangle_non_opaque_culled',
248: 'TD_PERF_SEL_triangle_front_facing_culled',
249: 'TD_PERF_SEL_triangle_back_facing_culled',
}
TD_PERF_SEL_none = 0
TD_PERF_SEL_td_busy = 1
TD_PERF_SEL_input_busy = 2
TD_PERF_SEL_sampler_lerp_busy = 3
TD_PERF_SEL_sampler_out_busy = 4
TD_PERF_SEL_nofilter_busy = 5
TD_PERF_SEL_sampler_core_sclk_en = 7
TD_PERF_SEL_sampler_preformatter_sclk_en = 8
TD_PERF_SEL_sampler_bilerp_sclk_en = 9
TD_PERF_SEL_sampler_bypass_sclk_en = 10
TD_PERF_SEL_sampler_minmax_sclk_en = 11
TD_PERF_SEL_sampler_accum_sclk_en = 12
TD_PERF_SEL_sampler_format_flt_sclk_en = 13
TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 14
TD_PERF_SEL_sampler_out_sclk_en = 15
TD_PERF_SEL_nofilter_sclk_en = 16
TD_PERF_SEL_nofilter_d32_sclk_en = 17
TD_PERF_SEL_nofilter_d16_sclk_en = 18
TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 26
TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 27
TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 28
TD_PERF_SEL_core_state_ram_max_cnt = 32
TD_PERF_SEL_core_state_rams_read = 33
TD_PERF_SEL_weight_data_rams_read = 34
TD_PERF_SEL_reference_data_rams_read = 35
TD_PERF_SEL_tc_td_ram_fifo_full = 36
TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 37
TD_PERF_SEL_tc_td_data_fifo_full = 38
TD_PERF_SEL_input_state_fifo_full = 39
TD_PERF_SEL_ta_data_stall = 40
TD_PERF_SEL_tc_data_stall = 41
TD_PERF_SEL_tc_ram_stall = 42
TD_PERF_SEL_lds_stall = 43
TD_PERF_SEL_sampler_pkr_full = 44
TD_PERF_SEL_sampler_pkr_full_due_to_arb = 45
TD_PERF_SEL_nofilter_pkr_full = 46
TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 47
TD_PERF_SEL_gather4_instr = 50
TD_PERF_SEL_gather4h_instr = 51
TD_PERF_SEL_getlod_instr = 52
TD_PERF_SEL_sample_instr = 54
TD_PERF_SEL_sample_c_instr = 55
TD_PERF_SEL_load_instr = 56
TD_PERF_SEL_ps_load_instr = 57
TD_PERF_SEL_write_ack_instr = 58
TD_PERF_SEL_d16_en_instr = 59
TD_PERF_SEL_bypassLerp_instr = 60
TD_PERF_SEL_min_max_filter_instr = 61
TD_PERF_SEL_one_comp_return_instr = 62
TD_PERF_SEL_two_comp_return_instr = 63
TD_PERF_SEL_three_comp_return_instr = 64
TD_PERF_SEL_four_comp_return_instr = 65
TD_PERF_SEL_user_defined_border = 66
TD_PERF_SEL_white_border = 67
TD_PERF_SEL_opaque_black_border = 68
TD_PERF_SEL_lod_warn_from_ta = 69
TD_PERF_SEL_instruction_dest_is_lds = 70
TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 71
TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 72
TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 73
TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 74
TD_PERF_SEL_out_of_order_instr = 75
TD_PERF_SEL_total_num_instr = 76
TD_PERF_SEL_total_num_instr_with_perf_wdw = 77
TD_PERF_SEL_total_num_sampler_instr = 78
TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 79
TD_PERF_SEL_total_num_nofilter_instr = 80
TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 81
TD_PERF_SEL_mixmode_instr = 84
TD_PERF_SEL_mixmode_resource = 85
TD_PERF_SEL_status_packet = 86
TD_PERF_SEL_done_scoreboard_max_stored_cnt = 89
TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 90
TD_PERF_SEL_done_scoreboard_not_empty = 91
TD_PERF_SEL_done_scoreboard_is_full = 92
TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 93
TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 94
TD_PERF_SEL_nofilter_formatters_turned_on = 95
TD_PERF_SEL_nofilter_insert_extra_comps = 96
TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 97
TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 98
TD_PERF_SEL_msaa_load_instr = 99
TD_PERF_SEL_blend_prt_with_prt_default_0 = 100
TD_PERF_SEL_resmap_instr = 102
TD_PERF_SEL_prt_ack_instr = 103
TD_PERF_SEL_resmap_with_volume_filtering = 104
TD_PERF_SEL_resmap_with_aniso_filtering = 105
TD_PERF_SEL_resmap_with_no_more_filtering = 106
TD_PERF_SEL_resmap_with_cubemap_corner = 107
TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 131
TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 132
TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 133
TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 134
TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 135
TD_PERF_SEL_burst_bin_sampler_1 = 136
TD_PERF_SEL_burst_bin_sampler_2to8 = 137
TD_PERF_SEL_burst_bin_sampler_9to16 = 138
TD_PERF_SEL_burst_bin_sampler_gt16 = 139
TD_PERF_SEL_burst_bin_gather_1 = 140
TD_PERF_SEL_burst_bin_gather_2to8 = 141
TD_PERF_SEL_burst_bin_gather_9to16 = 142
TD_PERF_SEL_burst_bin_gather_gt16 = 143
TD_PERF_SEL_burst_bin_nofilter_1 = 144
TD_PERF_SEL_burst_bin_nofilter_2to4 = 145
TD_PERF_SEL_burst_bin_nofilter_5to7 = 146
TD_PERF_SEL_burst_bin_nofilter_8to16 = 147
TD_PERF_SEL_burst_bin_nofilter_gt16 = 148
TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 170
TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 171
TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 172
TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 173
TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 174
TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 175
TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 176
TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 177
TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 178
TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 179
TD_PERF_SEL_preempting_nofilter_max_cnt = 180
TD_PERF_SEL_sampler_lerp0_active = 181
TD_PERF_SEL_sampler_lerp1_active = 182
TD_PERF_SEL_sampler_lerp2_active = 183
TD_PERF_SEL_sampler_lerp3_active = 184
TD_PERF_SEL_sampler_lerp4_active = 185
TD_PERF_SEL_sampler_lerp5_active = 186
TD_PERF_SEL_sampler_lerp6_active = 187
TD_PERF_SEL_sampler_lerp7_active = 188
TD_PERF_SEL_nofilter_total_num_comps_to_lds = 189
TD_PERF_SEL_nofilter_byte_cycling_4cycles = 190
TD_PERF_SEL_nofilter_byte_cycling_8cycles = 191
TD_PERF_SEL_nofilter_byte_cycling_16cycles = 192
TD_PERF_SEL_nofilter_dword_cycling_2cycles = 193
TD_PERF_SEL_nofilter_dword_cycling_4cycles = 194
TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 195
TD_PERF_SEL_store_preempts_a_load = 200
TD_PERF_SEL_sample_2x_instr = 201
TD_PERF_SEL_gather4_2x_instr = 202
TD_PERF_SEL_gather4h_2x_instr = 203
TD_PERF_SEL_getlod_2x_instr = 204
TD_PERF_SEL_resmap_2x_instr = 205
TD_PERF_SEL_2x_sampler_op_with_1_unlit_quad = 206
TD_PERF_SEL_2x_sampler_op_with_both_quads_unlit = 207
TD_PERF_SEL_tri_proc_node_override_slot0 = 208
TD_PERF_SEL_tri_run_intersect_ahs_slot0 = 209
TD_PERF_SEL_tri_run_ahs_slot0 = 210
TD_PERF_SEL_tri_proc_node_override_slot1 = 231
TD_PERF_SEL_tri_run_intersect_ahs_slot1 = 232
TD_PERF_SEL_tri_run_ahs_slot1 = 233
TD_PERF_SEL_instance_mask_culled = 241
TD_PERF_SEL_box_opaque_culled = 242
TD_PERF_SEL_box_non_opaque_culled = 243
TD_PERF_SEL_box_with_triangle_children_only_culled = 244
TD_PERF_SEL_box_with_procedural_children_only_culled = 245
TD_PERF_SEL_triangle_opaque_culled = 246
TD_PERF_SEL_triangle_non_opaque_culled = 247
TD_PERF_SEL_triangle_front_facing_culled = 248
TD_PERF_SEL_triangle_back_facing_culled = 249
TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL2A_PERF_SEL'
GL2A_PERF_SEL__enumvalues = {
0: 'GL2A_PERF_SEL_NONE',
1: 'GL2A_PERF_SEL_CYCLE',
2: 'GL2A_PERF_SEL_BUSY',
3: 'GL2A_PERF_SEL_REQ_GL2C0',
4: 'GL2A_PERF_SEL_REQ_GL2C1',
5: 'GL2A_PERF_SEL_REQ_GL2C2',
6: 'GL2A_PERF_SEL_REQ_GL2C3',
7: 'GL2A_PERF_SEL_REQ_GL2C4',
8: 'GL2A_PERF_SEL_REQ_GL2C5',
9: 'GL2A_PERF_SEL_REQ_GL2C6',
10: 'GL2A_PERF_SEL_REQ_GL2C7',
19: 'GL2A_PERF_SEL_REQ_BURST_GL2C0',
20: 'GL2A_PERF_SEL_REQ_BURST_GL2C1',
21: 'GL2A_PERF_SEL_REQ_BURST_GL2C2',
22: 'GL2A_PERF_SEL_REQ_BURST_GL2C3',
23: 'GL2A_PERF_SEL_REQ_BURST_GL2C4',
24: 'GL2A_PERF_SEL_REQ_BURST_GL2C5',
25: 'GL2A_PERF_SEL_REQ_BURST_GL2C6',
26: 'GL2A_PERF_SEL_REQ_BURST_GL2C7',
27: 'GL2A_PERF_SEL_REQ_STALL_GL2C0',
28: 'GL2A_PERF_SEL_REQ_STALL_GL2C1',
29: 'GL2A_PERF_SEL_REQ_STALL_GL2C2',
30: 'GL2A_PERF_SEL_REQ_STALL_GL2C3',
31: 'GL2A_PERF_SEL_REQ_STALL_GL2C4',
32: 'GL2A_PERF_SEL_REQ_STALL_GL2C5',
33: 'GL2A_PERF_SEL_REQ_STALL_GL2C6',
34: 'GL2A_PERF_SEL_REQ_STALL_GL2C7',
35: 'GL2A_PERF_SEL_RTN_STALL_GL2C0',
36: 'GL2A_PERF_SEL_RTN_STALL_GL2C1',
37: 'GL2A_PERF_SEL_RTN_STALL_GL2C2',
38: 'GL2A_PERF_SEL_RTN_STALL_GL2C3',
39: 'GL2A_PERF_SEL_RTN_STALL_GL2C4',
40: 'GL2A_PERF_SEL_RTN_STALL_GL2C5',
41: 'GL2A_PERF_SEL_RTN_STALL_GL2C6',
42: 'GL2A_PERF_SEL_RTN_STALL_GL2C7',
43: 'GL2A_PERF_SEL_RTN_CLIENT0',
44: 'GL2A_PERF_SEL_RTN_CLIENT1',
45: 'GL2A_PERF_SEL_RTN_CLIENT2',
46: 'GL2A_PERF_SEL_RTN_CLIENT3',
47: 'GL2A_PERF_SEL_RTN_CLIENT4',
48: 'GL2A_PERF_SEL_RTN_CLIENT5',
49: 'GL2A_PERF_SEL_RTN_CLIENT6',
50: 'GL2A_PERF_SEL_RTN_CLIENT7',
51: 'GL2A_PERF_SEL_RTN_CLIENT8',
52: 'GL2A_PERF_SEL_RTN_CLIENT9',
53: 'GL2A_PERF_SEL_RTN_CLIENT10',
54: 'GL2A_PERF_SEL_RTN_CLIENT11',
55: 'GL2A_PERF_SEL_RTN_CLIENT12',
56: 'GL2A_PERF_SEL_RTN_CLIENT13',
57: 'GL2A_PERF_SEL_RTN_CLIENT14',
58: 'GL2A_PERF_SEL_RTN_CLIENT15',
59: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0',
60: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1',
61: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2',
62: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3',
63: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4',
64: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5',
65: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6',
66: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7',
67: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8',
68: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9',
69: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10',
70: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11',
71: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12',
72: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13',
73: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14',
74: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15',
75: 'GL2A_PERF_SEL_REQ_BURST_CLIENT0',
76: 'GL2A_PERF_SEL_REQ_BURST_CLIENT1',
77: 'GL2A_PERF_SEL_REQ_BURST_CLIENT2',
78: 'GL2A_PERF_SEL_REQ_BURST_CLIENT3',
79: 'GL2A_PERF_SEL_REQ_BURST_CLIENT4',
80: 'GL2A_PERF_SEL_REQ_BURST_CLIENT5',
81: 'GL2A_PERF_SEL_REQ_BURST_CLIENT6',
82: 'GL2A_PERF_SEL_REQ_BURST_CLIENT7',
83: 'GL2A_PERF_SEL_REQ_BURST_CLIENT8',
84: 'GL2A_PERF_SEL_REQ_BURST_CLIENT9',
85: 'GL2A_PERF_SEL_REQ_BURST_CLIENT10',
86: 'GL2A_PERF_SEL_REQ_BURST_CLIENT11',
87: 'GL2A_PERF_SEL_REQ_BURST_CLIENT12',
88: 'GL2A_PERF_SEL_REQ_BURST_CLIENT13',
89: 'GL2A_PERF_SEL_REQ_BURST_CLIENT14',
90: 'GL2A_PERF_SEL_REQ_BURST_CLIENT15',
91: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0',
92: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1',
93: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2',
94: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3',
95: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4',
96: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5',
97: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6',
98: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7',
99: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8',
100: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9',
101: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10',
103: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11',
104: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12',
105: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13',
106: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14',
107: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15',
}
GL2A_PERF_SEL_NONE = 0
GL2A_PERF_SEL_CYCLE = 1
GL2A_PERF_SEL_BUSY = 2
GL2A_PERF_SEL_REQ_GL2C0 = 3
GL2A_PERF_SEL_REQ_GL2C1 = 4
GL2A_PERF_SEL_REQ_GL2C2 = 5
GL2A_PERF_SEL_REQ_GL2C3 = 6
GL2A_PERF_SEL_REQ_GL2C4 = 7
GL2A_PERF_SEL_REQ_GL2C5 = 8
GL2A_PERF_SEL_REQ_GL2C6 = 9
GL2A_PERF_SEL_REQ_GL2C7 = 10
GL2A_PERF_SEL_REQ_BURST_GL2C0 = 19
GL2A_PERF_SEL_REQ_BURST_GL2C1 = 20
GL2A_PERF_SEL_REQ_BURST_GL2C2 = 21
GL2A_PERF_SEL_REQ_BURST_GL2C3 = 22
GL2A_PERF_SEL_REQ_BURST_GL2C4 = 23
GL2A_PERF_SEL_REQ_BURST_GL2C5 = 24
GL2A_PERF_SEL_REQ_BURST_GL2C6 = 25
GL2A_PERF_SEL_REQ_BURST_GL2C7 = 26
GL2A_PERF_SEL_REQ_STALL_GL2C0 = 27
GL2A_PERF_SEL_REQ_STALL_GL2C1 = 28
GL2A_PERF_SEL_REQ_STALL_GL2C2 = 29
GL2A_PERF_SEL_REQ_STALL_GL2C3 = 30
GL2A_PERF_SEL_REQ_STALL_GL2C4 = 31
GL2A_PERF_SEL_REQ_STALL_GL2C5 = 32
GL2A_PERF_SEL_REQ_STALL_GL2C6 = 33
GL2A_PERF_SEL_REQ_STALL_GL2C7 = 34
GL2A_PERF_SEL_RTN_STALL_GL2C0 = 35
GL2A_PERF_SEL_RTN_STALL_GL2C1 = 36
GL2A_PERF_SEL_RTN_STALL_GL2C2 = 37
GL2A_PERF_SEL_RTN_STALL_GL2C3 = 38
GL2A_PERF_SEL_RTN_STALL_GL2C4 = 39
GL2A_PERF_SEL_RTN_STALL_GL2C5 = 40
GL2A_PERF_SEL_RTN_STALL_GL2C6 = 41
GL2A_PERF_SEL_RTN_STALL_GL2C7 = 42
GL2A_PERF_SEL_RTN_CLIENT0 = 43
GL2A_PERF_SEL_RTN_CLIENT1 = 44
GL2A_PERF_SEL_RTN_CLIENT2 = 45
GL2A_PERF_SEL_RTN_CLIENT3 = 46
GL2A_PERF_SEL_RTN_CLIENT4 = 47
GL2A_PERF_SEL_RTN_CLIENT5 = 48
GL2A_PERF_SEL_RTN_CLIENT6 = 49
GL2A_PERF_SEL_RTN_CLIENT7 = 50
GL2A_PERF_SEL_RTN_CLIENT8 = 51
GL2A_PERF_SEL_RTN_CLIENT9 = 52
GL2A_PERF_SEL_RTN_CLIENT10 = 53
GL2A_PERF_SEL_RTN_CLIENT11 = 54
GL2A_PERF_SEL_RTN_CLIENT12 = 55
GL2A_PERF_SEL_RTN_CLIENT13 = 56
GL2A_PERF_SEL_RTN_CLIENT14 = 57
GL2A_PERF_SEL_RTN_CLIENT15 = 58
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 59
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 60
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 61
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 62
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 63
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 64
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 65
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 66
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 67
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 68
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 69
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 70
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 71
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 72
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 73
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 74
GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 75
GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 76
GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 77
GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 78
GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 79
GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 80
GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 81
GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 82
GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 83
GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 84
GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 85
GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 86
GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 87
GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 88
GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 89
GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 90
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 91
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 92
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 93
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 94
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 95
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 96
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 97
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 98
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 99
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 100
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 101
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 103
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 104
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 105
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 106
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 107
GL2A_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL2C_PERF_SEL'
GL2C_PERF_SEL__enumvalues = {
0: 'GL2C_PERF_SEL_NONE',
1: 'GL2C_PERF_SEL_CYCLE',
2: 'GL2C_PERF_SEL_BUSY',
3: 'GL2C_PERF_SEL_REQ',
4: 'GL2C_PERF_SEL_VOL_REQ',
5: 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ',
6: 'GL2C_PERF_SEL_READ',
7: 'GL2C_PERF_SEL_WRITE',
8: 'GL2C_PERF_SEL_ATOMIC',
9: 'GL2C_PERF_SEL_NOP_ACK',
10: 'GL2C_PERF_SEL_NOP_RTN0',
11: 'GL2C_PERF_SEL_COMPRESSED_READ_REQ',
12: 'GL2C_PERF_SEL_METADATA_READ_REQ',
13: 'GL2C_PERF_SEL_CLIENT0_REQ',
14: 'GL2C_PERF_SEL_CLIENT1_REQ',
15: 'GL2C_PERF_SEL_CLIENT2_REQ',
16: 'GL2C_PERF_SEL_CLIENT3_REQ',
17: 'GL2C_PERF_SEL_CLIENT4_REQ',
18: 'GL2C_PERF_SEL_CLIENT5_REQ',
19: 'GL2C_PERF_SEL_CLIENT6_REQ',
20: 'GL2C_PERF_SEL_CLIENT7_REQ',
21: 'GL2C_PERF_SEL_CLIENT8_REQ',
22: 'GL2C_PERF_SEL_CLIENT9_REQ',
23: 'GL2C_PERF_SEL_CLIENT10_REQ',
24: 'GL2C_PERF_SEL_CLIENT11_REQ',
25: 'GL2C_PERF_SEL_CLIENT12_REQ',
26: 'GL2C_PERF_SEL_CLIENT13_REQ',
27: 'GL2C_PERF_SEL_CLIENT14_REQ',
28: 'GL2C_PERF_SEL_CLIENT15_REQ',
29: 'GL2C_PERF_SEL_C_RW_S_REQ',
30: 'GL2C_PERF_SEL_C_RW_US_REQ',
31: 'GL2C_PERF_SEL_C_RO_S_REQ',
32: 'GL2C_PERF_SEL_C_RO_US_REQ',
33: 'GL2C_PERF_SEL_UC_REQ',
34: 'GL2C_PERF_SEL_LRU_REQ',
35: 'GL2C_PERF_SEL_STREAM_REQ',
36: 'GL2C_PERF_SEL_BYPASS_REQ',
37: 'GL2C_PERF_SEL_NOA_REQ',
38: 'GL2C_PERF_SEL_SHARED_REQ',
39: 'GL2C_PERF_SEL_HIT',
40: 'GL2C_PERF_SEL_MISS',
41: 'GL2C_PERF_SEL_FULL_HIT',
42: 'GL2C_PERF_SEL_PARTIAL_32B_HIT',
43: 'GL2C_PERF_SEL_PARTIAL_64B_HIT',
44: 'GL2C_PERF_SEL_PARTIAL_96B_HIT',
45: 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT',
46: 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT',
47: 'GL2C_PERF_SEL_UNCACHED_WRITE',
48: 'GL2C_PERF_SEL_WRITEBACK',
49: 'GL2C_PERF_SEL_NORMAL_WRITEBACK',
50: 'GL2C_PERF_SEL_EVICT',
51: 'GL2C_PERF_SEL_NORMAL_EVICT',
52: 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE',
53: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0',
54: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1',
55: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2',
56: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3',
57: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4',
58: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5',
59: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6',
60: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7',
61: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8',
62: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9',
63: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10',
64: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11',
65: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12',
66: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13',
67: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14',
68: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15',
69: 'GL2C_PERF_SEL_READ_32_REQ',
70: 'GL2C_PERF_SEL_READ_64_REQ',
71: 'GL2C_PERF_SEL_READ_128_REQ',
72: 'GL2C_PERF_SEL_WRITE_32_REQ',
73: 'GL2C_PERF_SEL_WRITE_64_REQ',
74: 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ',
75: 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ',
76: 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ',
77: 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ',
78: 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ',
79: 'GL2C_PERF_SEL_MC_WRREQ',
80: 'GL2C_PERF_SEL_EA_WRREQ_SNOOP',
81: 'GL2C_PERF_SEL_EA_WRREQ_64B',
82: 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B',
83: 'GL2C_PERF_SEL_MC_WRREQ_STALL',
84: 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL',
85: 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL',
86: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL',
87: 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL',
88: 'GL2C_PERF_SEL_MC_WRREQ_LEVEL',
89: 'GL2C_PERF_SEL_EA_ATOMIC',
90: 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL',
91: 'GL2C_PERF_SEL_MC_RDREQ',
92: 'GL2C_PERF_SEL_EA_RDREQ_SNOOP',
93: 'GL2C_PERF_SEL_EA_RDREQ_SPLIT',
94: 'GL2C_PERF_SEL_EA_RDREQ_32B',
95: 'GL2C_PERF_SEL_EA_RDREQ_64B',
96: 'GL2C_PERF_SEL_EA_RDREQ_96B',
97: 'GL2C_PERF_SEL_EA_RDREQ_128B',
98: 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B',
99: 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B',
100: 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL',
101: 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL',
102: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL',
103: 'GL2C_PERF_SEL_MC_RDREQ_LEVEL',
104: 'GL2C_PERF_SEL_EA_RDREQ_DRAM',
105: 'GL2C_PERF_SEL_EA_WRREQ_DRAM',
106: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B',
107: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B',
108: 'GL2C_PERF_SEL_ONION_READ',
109: 'GL2C_PERF_SEL_ONION_WRITE',
110: 'GL2C_PERF_SEL_IO_READ',
111: 'GL2C_PERF_SEL_IO_WRITE',
112: 'GL2C_PERF_SEL_GARLIC_READ',
113: 'GL2C_PERF_SEL_GARLIC_WRITE',
114: 'GL2C_PERF_SEL_EA_OUTSTANDING',
115: 'GL2C_PERF_SEL_LATENCY_FIFO_FULL',
116: 'GL2C_PERF_SEL_SRC_FIFO_FULL',
117: 'GL2C_PERF_SEL_TAG_STALL',
118: 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL',
119: 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL',
120: 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL',
121: 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL',
122: 'GL2C_PERF_SEL_TAG_READ_DST_STALL',
123: 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT',
124: 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT',
125: 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE',
126: 'GL2C_PERF_SEL_BUBBLE',
127: 'GL2C_PERF_SEL_IB_REQ',
128: 'GL2C_PERF_SEL_IB_STALL',
129: 'GL2C_PERF_SEL_IB_TAG_STALL',
130: 'GL2C_PERF_SEL_RETURN_ACK',
131: 'GL2C_PERF_SEL_RETURN_DATA',
132: 'GL2C_PERF_SEL_EA_RDRET_NACK',
133: 'GL2C_PERF_SEL_EA_WRRET_NACK',
134: 'GL2C_PERF_SEL_GL2A_LEVEL',
135: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START',
136: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START',
137: 'GL2C_PERF_SEL_GCR_INV',
138: 'GL2C_PERF_SEL_GCR_WB',
139: 'GL2C_PERF_SEL_GCR_DISCARD',
140: 'GL2C_PERF_SEL_GCR_RANGE',
141: 'GL2C_PERF_SEL_GCR_ALL',
142: 'GL2C_PERF_SEL_GCR_VOL',
143: 'GL2C_PERF_SEL_GCR_UNSHARED',
144: 'GL2C_PERF_SEL_GCR_GL2_INV_ALL',
145: 'GL2C_PERF_SEL_GCR_GL2_WB_ALL',
146: 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE',
147: 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE',
148: 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE',
149: 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT',
150: 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT',
151: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE',
152: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE',
153: 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK',
154: 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE',
155: 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT',
156: 'GL2C_PERF_SEL_GCR_INVL2_VOL_START',
157: 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE',
158: 'GL2C_PERF_SEL_GCR_WBL2_VOL_START',
159: 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE',
160: 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT',
161: 'GL2C_PERF_SEL_GCR_WBINVL2_START',
162: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16',
163: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17',
164: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18',
165: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19',
}
GL2C_PERF_SEL_NONE = 0
GL2C_PERF_SEL_CYCLE = 1
GL2C_PERF_SEL_BUSY = 2
GL2C_PERF_SEL_REQ = 3
GL2C_PERF_SEL_VOL_REQ = 4
GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 5
GL2C_PERF_SEL_READ = 6
GL2C_PERF_SEL_WRITE = 7
GL2C_PERF_SEL_ATOMIC = 8
GL2C_PERF_SEL_NOP_ACK = 9
GL2C_PERF_SEL_NOP_RTN0 = 10
GL2C_PERF_SEL_COMPRESSED_READ_REQ = 11
GL2C_PERF_SEL_METADATA_READ_REQ = 12
GL2C_PERF_SEL_CLIENT0_REQ = 13
GL2C_PERF_SEL_CLIENT1_REQ = 14
GL2C_PERF_SEL_CLIENT2_REQ = 15
GL2C_PERF_SEL_CLIENT3_REQ = 16
GL2C_PERF_SEL_CLIENT4_REQ = 17
GL2C_PERF_SEL_CLIENT5_REQ = 18
GL2C_PERF_SEL_CLIENT6_REQ = 19
GL2C_PERF_SEL_CLIENT7_REQ = 20
GL2C_PERF_SEL_CLIENT8_REQ = 21
GL2C_PERF_SEL_CLIENT9_REQ = 22
GL2C_PERF_SEL_CLIENT10_REQ = 23
GL2C_PERF_SEL_CLIENT11_REQ = 24
GL2C_PERF_SEL_CLIENT12_REQ = 25
GL2C_PERF_SEL_CLIENT13_REQ = 26
GL2C_PERF_SEL_CLIENT14_REQ = 27
GL2C_PERF_SEL_CLIENT15_REQ = 28
GL2C_PERF_SEL_C_RW_S_REQ = 29
GL2C_PERF_SEL_C_RW_US_REQ = 30
GL2C_PERF_SEL_C_RO_S_REQ = 31
GL2C_PERF_SEL_C_RO_US_REQ = 32
GL2C_PERF_SEL_UC_REQ = 33
GL2C_PERF_SEL_LRU_REQ = 34
GL2C_PERF_SEL_STREAM_REQ = 35
GL2C_PERF_SEL_BYPASS_REQ = 36
GL2C_PERF_SEL_NOA_REQ = 37
GL2C_PERF_SEL_SHARED_REQ = 38
GL2C_PERF_SEL_HIT = 39
GL2C_PERF_SEL_MISS = 40
GL2C_PERF_SEL_FULL_HIT = 41
GL2C_PERF_SEL_PARTIAL_32B_HIT = 42
GL2C_PERF_SEL_PARTIAL_64B_HIT = 43
GL2C_PERF_SEL_PARTIAL_96B_HIT = 44
GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 45
GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 46
GL2C_PERF_SEL_UNCACHED_WRITE = 47
GL2C_PERF_SEL_WRITEBACK = 48
GL2C_PERF_SEL_NORMAL_WRITEBACK = 49
GL2C_PERF_SEL_EVICT = 50
GL2C_PERF_SEL_NORMAL_EVICT = 51
GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 52
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 53
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 54
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 55
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 56
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 57
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 58
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 59
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 60
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 61
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 62
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 63
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 64
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 65
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 66
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 67
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 68
GL2C_PERF_SEL_READ_32_REQ = 69
GL2C_PERF_SEL_READ_64_REQ = 70
GL2C_PERF_SEL_READ_128_REQ = 71
GL2C_PERF_SEL_WRITE_32_REQ = 72
GL2C_PERF_SEL_WRITE_64_REQ = 73
GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 74
GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 75
GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 76
GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 77
GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 78
GL2C_PERF_SEL_MC_WRREQ = 79
GL2C_PERF_SEL_EA_WRREQ_SNOOP = 80
GL2C_PERF_SEL_EA_WRREQ_64B = 81
GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 82
GL2C_PERF_SEL_MC_WRREQ_STALL = 83
GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 84
GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 85
GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 86
GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 87
GL2C_PERF_SEL_MC_WRREQ_LEVEL = 88
GL2C_PERF_SEL_EA_ATOMIC = 89
GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 90
GL2C_PERF_SEL_MC_RDREQ = 91
GL2C_PERF_SEL_EA_RDREQ_SNOOP = 92
GL2C_PERF_SEL_EA_RDREQ_SPLIT = 93
GL2C_PERF_SEL_EA_RDREQ_32B = 94
GL2C_PERF_SEL_EA_RDREQ_64B = 95
GL2C_PERF_SEL_EA_RDREQ_96B = 96
GL2C_PERF_SEL_EA_RDREQ_128B = 97
GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 98
GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 99
GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 100
GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 101
GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 102
GL2C_PERF_SEL_MC_RDREQ_LEVEL = 103
GL2C_PERF_SEL_EA_RDREQ_DRAM = 104
GL2C_PERF_SEL_EA_WRREQ_DRAM = 105
GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 106
GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 107
GL2C_PERF_SEL_ONION_READ = 108
GL2C_PERF_SEL_ONION_WRITE = 109
GL2C_PERF_SEL_IO_READ = 110
GL2C_PERF_SEL_IO_WRITE = 111
GL2C_PERF_SEL_GARLIC_READ = 112
GL2C_PERF_SEL_GARLIC_WRITE = 113
GL2C_PERF_SEL_EA_OUTSTANDING = 114
GL2C_PERF_SEL_LATENCY_FIFO_FULL = 115
GL2C_PERF_SEL_SRC_FIFO_FULL = 116
GL2C_PERF_SEL_TAG_STALL = 117
GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 118
GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 119
GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 120
GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 121
GL2C_PERF_SEL_TAG_READ_DST_STALL = 122
GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 123
GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 124
GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 125
GL2C_PERF_SEL_BUBBLE = 126
GL2C_PERF_SEL_IB_REQ = 127
GL2C_PERF_SEL_IB_STALL = 128
GL2C_PERF_SEL_IB_TAG_STALL = 129
GL2C_PERF_SEL_RETURN_ACK = 130
GL2C_PERF_SEL_RETURN_DATA = 131
GL2C_PERF_SEL_EA_RDRET_NACK = 132
GL2C_PERF_SEL_EA_WRRET_NACK = 133
GL2C_PERF_SEL_GL2A_LEVEL = 134
GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 135
GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 136
GL2C_PERF_SEL_GCR_INV = 137
GL2C_PERF_SEL_GCR_WB = 138
GL2C_PERF_SEL_GCR_DISCARD = 139
GL2C_PERF_SEL_GCR_RANGE = 140
GL2C_PERF_SEL_GCR_ALL = 141
GL2C_PERF_SEL_GCR_VOL = 142
GL2C_PERF_SEL_GCR_UNSHARED = 143
GL2C_PERF_SEL_GCR_GL2_INV_ALL = 144
GL2C_PERF_SEL_GCR_GL2_WB_ALL = 145
GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 146
GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 147
GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 148
GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 149
GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 150
GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 151
GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 152
GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 153
GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 154
GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 155
GL2C_PERF_SEL_GCR_INVL2_VOL_START = 156
GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 157
GL2C_PERF_SEL_GCR_WBL2_VOL_START = 158
GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 159
GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 160
GL2C_PERF_SEL_GCR_WBINVL2_START = 161
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 162
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 163
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 164
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 165
GL2C_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SX_BLEND_OPT'
SX_BLEND_OPT__enumvalues = {
0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL',
1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE',
2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0',
3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1',
4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0',
5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1',
6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0',
7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE',
}
BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0
BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1
BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2
BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3
BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4
BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5
BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6
BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7
SX_BLEND_OPT = ctypes.c_uint32 # enum
# values for enumeration 'SX_DOWNCONVERT_FORMAT'
SX_DOWNCONVERT_FORMAT__enumvalues = {
0: 'SX_RT_EXPORT_NO_CONVERSION',
1: 'SX_RT_EXPORT_32_R',
2: 'SX_RT_EXPORT_32_A',
3: 'SX_RT_EXPORT_10_11_11',
4: 'SX_RT_EXPORT_2_10_10_10',
5: 'SX_RT_EXPORT_8_8_8_8',
6: 'SX_RT_EXPORT_5_6_5',
7: 'SX_RT_EXPORT_1_5_5_5',
8: 'SX_RT_EXPORT_4_4_4_4',
9: 'SX_RT_EXPORT_16_16_GR',
10: 'SX_RT_EXPORT_16_16_AR',
11: 'SX_RT_EXPORT_9_9_9_E5',
12: 'SX_RT_EXPORT_2_10_10_10_7E3',
13: 'SX_RT_EXPORT_2_10_10_10_6E4',
}
SX_RT_EXPORT_NO_CONVERSION = 0
SX_RT_EXPORT_32_R = 1
SX_RT_EXPORT_32_A = 2
SX_RT_EXPORT_10_11_11 = 3
SX_RT_EXPORT_2_10_10_10 = 4
SX_RT_EXPORT_8_8_8_8 = 5
SX_RT_EXPORT_5_6_5 = 6
SX_RT_EXPORT_1_5_5_5 = 7
SX_RT_EXPORT_4_4_4_4 = 8
SX_RT_EXPORT_16_16_GR = 9
SX_RT_EXPORT_16_16_AR = 10
SX_RT_EXPORT_9_9_9_E5 = 11
SX_RT_EXPORT_2_10_10_10_7E3 = 12
SX_RT_EXPORT_2_10_10_10_6E4 = 13
SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'SX_OPT_COMB_FCN'
SX_OPT_COMB_FCN__enumvalues = {
0: 'OPT_COMB_NONE',
1: 'OPT_COMB_ADD',
2: 'OPT_COMB_SUBTRACT',
3: 'OPT_COMB_MIN',
4: 'OPT_COMB_MAX',
5: 'OPT_COMB_REVSUBTRACT',
6: 'OPT_COMB_BLEND_DISABLED',
7: 'OPT_COMB_SAFE_ADD',
}
OPT_COMB_NONE = 0
OPT_COMB_ADD = 1
OPT_COMB_SUBTRACT = 2
OPT_COMB_MIN = 3
OPT_COMB_MAX = 4
OPT_COMB_REVSUBTRACT = 5
OPT_COMB_BLEND_DISABLED = 6
OPT_COMB_SAFE_ADD = 7
SX_OPT_COMB_FCN = ctypes.c_uint32 # enum
# values for enumeration 'SX_PERFCOUNTER_VALS'
SX_PERFCOUNTER_VALS__enumvalues = {
0: 'SX_PERF_SEL_PA_IDLE_CYCLES',
1: 'SX_PERF_SEL_PA_REQ',
2: 'SX_PERF_SEL_PA_POS',
3: 'SX_PERF_SEL_CLOCK',
4: 'SX_PERF_SEL_GATE_EN1',
5: 'SX_PERF_SEL_GATE_EN2',
6: 'SX_PERF_SEL_GATE_EN3',
7: 'SX_PERF_SEL_GATE_EN4',
8: 'SX_PERF_SEL_SH_POS_STARVE',
9: 'SX_PERF_SEL_SH_COLOR_STARVE',
10: 'SX_PERF_SEL_SH_POS_STALL',
11: 'SX_PERF_SEL_SH_COLOR_STALL',
12: 'SX_PERF_SEL_DB0_PIXELS',
13: 'SX_PERF_SEL_DB0_HALF_QUADS',
14: 'SX_PERF_SEL_DB0_PIXEL_STALL',
15: 'SX_PERF_SEL_DB0_PIXEL_IDLE',
16: 'SX_PERF_SEL_DB0_PRED_PIXELS',
17: 'SX_PERF_SEL_DB1_PIXELS',
18: 'SX_PERF_SEL_DB1_HALF_QUADS',
19: 'SX_PERF_SEL_DB1_PIXEL_STALL',
20: 'SX_PERF_SEL_DB1_PIXEL_IDLE',
21: 'SX_PERF_SEL_DB1_PRED_PIXELS',
22: 'SX_PERF_SEL_DB2_PIXELS',
23: 'SX_PERF_SEL_DB2_HALF_QUADS',
24: 'SX_PERF_SEL_DB2_PIXEL_STALL',
25: 'SX_PERF_SEL_DB2_PIXEL_IDLE',
26: 'SX_PERF_SEL_DB2_PRED_PIXELS',
27: 'SX_PERF_SEL_DB3_PIXELS',
28: 'SX_PERF_SEL_DB3_HALF_QUADS',
29: 'SX_PERF_SEL_DB3_PIXEL_STALL',
30: 'SX_PERF_SEL_DB3_PIXEL_IDLE',
31: 'SX_PERF_SEL_DB3_PRED_PIXELS',
32: 'SX_PERF_SEL_COL_BUSY',
33: 'SX_PERF_SEL_POS_BUSY',
34: 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS',
35: 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST',
36: 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC',
37: 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS',
38: 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS',
39: 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS',
40: 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST',
41: 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC',
42: 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS',
43: 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS',
44: 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS',
45: 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST',
46: 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC',
47: 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS',
48: 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS',
49: 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS',
50: 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST',
51: 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC',
52: 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS',
53: 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS',
54: 'SX_PERF_SEL_PA_REQ_LATENCY',
55: 'SX_PERF_SEL_POS_SCBD_STALL',
56: 'SX_PERF_SEL_CLOCK_DROP_STALL',
57: 'SX_PERF_SEL_GATE_EN5',
58: 'SX_PERF_SEL_GATE_EN6',
59: 'SX_PERF_SEL_DB0_SIZE',
60: 'SX_PERF_SEL_DB1_SIZE',
61: 'SX_PERF_SEL_DB2_SIZE',
62: 'SX_PERF_SEL_DB3_SIZE',
63: 'SX_PERF_SEL_IDX_STALL_CYCLES',
64: 'SX_PERF_SEL_IDX_IDLE_CYCLES',
65: 'SX_PERF_SEL_IDX_REQ',
66: 'SX_PERF_SEL_IDX_RET',
67: 'SX_PERF_SEL_IDX_REQ_LATENCY',
68: 'SX_PERF_SEL_IDX_SCBD_STALL',
69: 'SX_PERF_SEL_GATE_EN7',
70: 'SX_PERF_SEL_GATE_EN8',
71: 'SX_PERF_SEL_SH_IDX_STARVE',
72: 'SX_PERF_SEL_IDX_BUSY',
73: 'SX_PERF_SEL_PA_POS_BANK_CONF',
74: 'SX_PERF_SEL_DB0_END_OF_WAVE',
75: 'SX_PERF_SEL_DB0_4X2_DISCARD',
76: 'SX_PERF_SEL_DB1_END_OF_WAVE',
77: 'SX_PERF_SEL_DB1_4X2_DISCARD',
78: 'SX_PERF_SEL_DB2_END_OF_WAVE',
79: 'SX_PERF_SEL_DB2_4X2_DISCARD',
80: 'SX_PERF_SEL_DB3_END_OF_WAVE',
81: 'SX_PERF_SEL_DB3_4X2_DISCARD',
}
SX_PERF_SEL_PA_IDLE_CYCLES = 0
SX_PERF_SEL_PA_REQ = 1
SX_PERF_SEL_PA_POS = 2
SX_PERF_SEL_CLOCK = 3
SX_PERF_SEL_GATE_EN1 = 4
SX_PERF_SEL_GATE_EN2 = 5
SX_PERF_SEL_GATE_EN3 = 6
SX_PERF_SEL_GATE_EN4 = 7
SX_PERF_SEL_SH_POS_STARVE = 8
SX_PERF_SEL_SH_COLOR_STARVE = 9
SX_PERF_SEL_SH_POS_STALL = 10
SX_PERF_SEL_SH_COLOR_STALL = 11
SX_PERF_SEL_DB0_PIXELS = 12
SX_PERF_SEL_DB0_HALF_QUADS = 13
SX_PERF_SEL_DB0_PIXEL_STALL = 14
SX_PERF_SEL_DB0_PIXEL_IDLE = 15
SX_PERF_SEL_DB0_PRED_PIXELS = 16
SX_PERF_SEL_DB1_PIXELS = 17
SX_PERF_SEL_DB1_HALF_QUADS = 18
SX_PERF_SEL_DB1_PIXEL_STALL = 19
SX_PERF_SEL_DB1_PIXEL_IDLE = 20
SX_PERF_SEL_DB1_PRED_PIXELS = 21
SX_PERF_SEL_DB2_PIXELS = 22
SX_PERF_SEL_DB2_HALF_QUADS = 23
SX_PERF_SEL_DB2_PIXEL_STALL = 24
SX_PERF_SEL_DB2_PIXEL_IDLE = 25
SX_PERF_SEL_DB2_PRED_PIXELS = 26
SX_PERF_SEL_DB3_PIXELS = 27
SX_PERF_SEL_DB3_HALF_QUADS = 28
SX_PERF_SEL_DB3_PIXEL_STALL = 29
SX_PERF_SEL_DB3_PIXEL_IDLE = 30
SX_PERF_SEL_DB3_PRED_PIXELS = 31
SX_PERF_SEL_COL_BUSY = 32
SX_PERF_SEL_POS_BUSY = 33
SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 34
SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 35
SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 36
SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 37
SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 38
SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 39
SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 40
SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 41
SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 42
SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 43
SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 44
SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 45
SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 46
SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 47
SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 48
SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 49
SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 50
SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 51
SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 52
SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 53
SX_PERF_SEL_PA_REQ_LATENCY = 54
SX_PERF_SEL_POS_SCBD_STALL = 55
SX_PERF_SEL_CLOCK_DROP_STALL = 56
SX_PERF_SEL_GATE_EN5 = 57
SX_PERF_SEL_GATE_EN6 = 58
SX_PERF_SEL_DB0_SIZE = 59
SX_PERF_SEL_DB1_SIZE = 60
SX_PERF_SEL_DB2_SIZE = 61
SX_PERF_SEL_DB3_SIZE = 62
SX_PERF_SEL_IDX_STALL_CYCLES = 63
SX_PERF_SEL_IDX_IDLE_CYCLES = 64
SX_PERF_SEL_IDX_REQ = 65
SX_PERF_SEL_IDX_RET = 66
SX_PERF_SEL_IDX_REQ_LATENCY = 67
SX_PERF_SEL_IDX_SCBD_STALL = 68
SX_PERF_SEL_GATE_EN7 = 69
SX_PERF_SEL_GATE_EN8 = 70
SX_PERF_SEL_SH_IDX_STARVE = 71
SX_PERF_SEL_IDX_BUSY = 72
SX_PERF_SEL_PA_POS_BANK_CONF = 73
SX_PERF_SEL_DB0_END_OF_WAVE = 74
SX_PERF_SEL_DB0_4X2_DISCARD = 75
SX_PERF_SEL_DB1_END_OF_WAVE = 76
SX_PERF_SEL_DB1_4X2_DISCARD = 77
SX_PERF_SEL_DB2_END_OF_WAVE = 78
SX_PERF_SEL_DB2_4X2_DISCARD = 79
SX_PERF_SEL_DB3_END_OF_WAVE = 80
SX_PERF_SEL_DB3_4X2_DISCARD = 81
SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum
# values for enumeration 'CompareFrag'
CompareFrag__enumvalues = {
0: 'FRAG_NEVER',
1: 'FRAG_LESS',
2: 'FRAG_EQUAL',
3: 'FRAG_LEQUAL',
4: 'FRAG_GREATER',
5: 'FRAG_NOTEQUAL',
6: 'FRAG_GEQUAL',
7: 'FRAG_ALWAYS',
}
FRAG_NEVER = 0
FRAG_LESS = 1
FRAG_EQUAL = 2
FRAG_LEQUAL = 3
FRAG_GREATER = 4
FRAG_NOTEQUAL = 5
FRAG_GEQUAL = 6
FRAG_ALWAYS = 7
CompareFrag = ctypes.c_uint32 # enum
# values for enumeration 'ConservativeZExport'
ConservativeZExport__enumvalues = {
0: 'EXPORT_ANY_Z',
1: 'EXPORT_LESS_THAN_Z',
2: 'EXPORT_GREATER_THAN_Z',
3: 'EXPORT_RESERVED',
}
EXPORT_ANY_Z = 0
EXPORT_LESS_THAN_Z = 1
EXPORT_GREATER_THAN_Z = 2
EXPORT_RESERVED = 3
ConservativeZExport = ctypes.c_uint32 # enum
# values for enumeration 'DbMemArbWatermarks'
DbMemArbWatermarks__enumvalues = {
0: 'TRANSFERRED_64_BYTES',
1: 'TRANSFERRED_128_BYTES',
2: 'TRANSFERRED_256_BYTES',
3: 'TRANSFERRED_512_BYTES',
4: 'TRANSFERRED_1024_BYTES',
5: 'TRANSFERRED_2048_BYTES',
6: 'TRANSFERRED_4096_BYTES',
7: 'TRANSFERRED_8192_BYTES',
}
TRANSFERRED_64_BYTES = 0
TRANSFERRED_128_BYTES = 1
TRANSFERRED_256_BYTES = 2
TRANSFERRED_512_BYTES = 3
TRANSFERRED_1024_BYTES = 4
TRANSFERRED_2048_BYTES = 5
TRANSFERRED_4096_BYTES = 6
TRANSFERRED_8192_BYTES = 7
DbMemArbWatermarks = ctypes.c_uint32 # enum
# values for enumeration 'DbPRTFaultBehavior'
DbPRTFaultBehavior__enumvalues = {
0: 'FAULT_ZERO',
1: 'FAULT_ONE',
2: 'FAULT_FAIL',
3: 'FAULT_PASS',
}
FAULT_ZERO = 0
FAULT_ONE = 1
FAULT_FAIL = 2
FAULT_PASS = 3
DbPRTFaultBehavior = ctypes.c_uint32 # enum
# values for enumeration 'DbPSLControl'
DbPSLControl__enumvalues = {
0: 'PSLC_AUTO',
1: 'PSLC_ON_HANG_ONLY',
2: 'PSLC_ASAP',
3: 'PSLC_COUNTDOWN',
}
PSLC_AUTO = 0
PSLC_ON_HANG_ONLY = 1
PSLC_ASAP = 2
PSLC_COUNTDOWN = 3
DbPSLControl = ctypes.c_uint32 # enum
# values for enumeration 'ForceControl'
ForceControl__enumvalues = {
0: 'FORCE_OFF',
1: 'FORCE_ENABLE',
2: 'FORCE_DISABLE',
3: 'FORCE_RESERVED',
}
FORCE_OFF = 0
FORCE_ENABLE = 1
FORCE_DISABLE = 2
FORCE_RESERVED = 3
ForceControl = ctypes.c_uint32 # enum
# values for enumeration 'GLCompressionMode'
GLCompressionMode__enumvalues = {
0: 'DB_DEFAULT',
1: 'DB_BYPASS',
2: 'DB_COMP_WR_DISABLE',
3: 'DB_BYPASS_WR_DISABLE',
}
DB_DEFAULT = 0
DB_BYPASS = 1
DB_COMP_WR_DISABLE = 2
DB_BYPASS_WR_DISABLE = 3
GLCompressionMode = ctypes.c_uint32 # enum
# values for enumeration 'OreoMode'
OreoMode__enumvalues = {
0: 'OMODE_BLEND',
1: 'OMODE_O_THEN_B',
2: 'OMODE_P_THEN_O_THEN_B',
3: 'OMODE_RESERVED_3',
}
OMODE_BLEND = 0
OMODE_O_THEN_B = 1
OMODE_P_THEN_O_THEN_B = 2
OMODE_RESERVED_3 = 3
OreoMode = ctypes.c_uint32 # enum
# values for enumeration 'PerfCounter_Vals'
PerfCounter_Vals__enumvalues = {
0: 'DB_PERF_SEL_SC_DB_tile_sends',
1: 'DB_PERF_SEL_SC_DB_tile_busy',
2: 'DB_PERF_SEL_SC_DB_tile_stalls',
3: 'DB_PERF_SEL_SC_DB_tile_events',
4: 'DB_PERF_SEL_SC_DB_tile_tiles',
5: 'DB_PERF_SEL_SC_DB_tile_covered',
6: 'DB_PERF_SEL_hiz_tc_read_starved',
7: 'DB_PERF_SEL_hiz_tc_write_stall',
8: 'DB_PERF_SEL_hiz_tile_culled',
9: 'DB_PERF_SEL_his_tile_culled',
10: 'DB_PERF_SEL_DB_SC_tile_sends',
11: 'DB_PERF_SEL_DB_SC_tile_busy',
12: 'DB_PERF_SEL_DB_SC_tile_stalls',
13: 'DB_PERF_SEL_DB_SC_tile_df_stalls',
14: 'DB_PERF_SEL_DB_SC_tile_tiles',
15: 'DB_PERF_SEL_DB_SC_tile_culled',
16: 'DB_PERF_SEL_DB_SC_tile_hier_kill',
17: 'DB_PERF_SEL_DB_SC_tile_fast_ops',
18: 'DB_PERF_SEL_DB_SC_tile_no_ops',
19: 'DB_PERF_SEL_DB_SC_tile_tile_rate',
20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill',
21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops',
22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops',
23: 'DB_PERF_SEL_SC_DB_quad_sends',
24: 'DB_PERF_SEL_SC_DB_quad_busy',
25: 'DB_PERF_SEL_SC_DB_quad_squads',
26: 'DB_PERF_SEL_SC_DB_quad_tiles',
27: 'DB_PERF_SEL_SC_DB_quad_pixels',
28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles',
29: 'DB_PERF_SEL_DB_SC_quad_sends',
30: 'DB_PERF_SEL_DB_SC_quad_busy',
31: 'DB_PERF_SEL_DB_SC_quad_stalls',
32: 'DB_PERF_SEL_DB_SC_quad_tiles',
33: 'DB_PERF_SEL_DB_SC_quad_lit_quad',
34: 'DB_PERF_SEL_DB_CB_export_events',
37: 'DB_PERF_SEL_SX_DB_quad_sends',
38: 'DB_PERF_SEL_SX_DB_quad_busy',
39: 'DB_PERF_SEL_SX_DB_quad_stalls',
40: 'DB_PERF_SEL_SX_DB_quad_quads',
41: 'DB_PERF_SEL_SX_DB_quad_pixels',
42: 'DB_PERF_SEL_SX_DB_quad_exports',
43: 'DB_PERF_SEL_SH_quads_outstanding_sum',
44: 'DB_PERF_SEL_DB_CB_export_sends',
45: 'DB_PERF_SEL_DB_CB_export_busy',
46: 'DB_PERF_SEL_DB_CB_export_stalls',
47: 'DB_PERF_SEL_DB_CB_export_quads',
48: 'DB_PERF_SEL_tile_rd_sends',
49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum',
50: 'DB_PERF_SEL_quad_rd_sends',
51: 'DB_PERF_SEL_quad_rd_busy',
52: 'DB_PERF_SEL_quad_rd_mi_stall',
53: 'DB_PERF_SEL_quad_rd_rw_collision',
54: 'DB_PERF_SEL_quad_rd_tag_stall',
55: 'DB_PERF_SEL_quad_rd_32byte_reqs',
56: 'DB_PERF_SEL_quad_rd_panic',
57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum',
58: 'DB_PERF_SEL_quad_rdret_sends',
59: 'DB_PERF_SEL_quad_rdret_busy',
60: 'DB_PERF_SEL_tile_wr_sends',
61: 'DB_PERF_SEL_tile_wr_acks',
62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum',
63: 'DB_PERF_SEL_quad_wr_sends',
64: 'DB_PERF_SEL_quad_wr_busy',
65: 'DB_PERF_SEL_quad_wr_mi_stall',
66: 'DB_PERF_SEL_quad_wr_coherency_stall',
67: 'DB_PERF_SEL_quad_wr_acks',
68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum',
69: 'DB_PERF_SEL_Tile_Cache_misses',
70: 'DB_PERF_SEL_Tile_Cache_hits',
71: 'DB_PERF_SEL_Tile_Cache_flushes',
72: 'DB_PERF_SEL_Tile_Cache_surface_stall',
73: 'DB_PERF_SEL_Tile_Cache_starves',
74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve',
75: 'DB_PERF_SEL_tcp_dispatcher_reads',
76: 'DB_PERF_SEL_tcp_prefetcher_reads',
77: 'DB_PERF_SEL_tcp_preloader_reads',
78: 'DB_PERF_SEL_tcp_dispatcher_flushes',
79: 'DB_PERF_SEL_tcp_prefetcher_flushes',
80: 'DB_PERF_SEL_tcp_preloader_flushes',
81: 'DB_PERF_SEL_Depth_Tile_Cache_sends',
82: 'DB_PERF_SEL_Depth_Tile_Cache_busy',
83: 'DB_PERF_SEL_Depth_Tile_Cache_starves',
84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked',
85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall',
86: 'DB_PERF_SEL_Depth_Tile_Cache_misses',
87: 'DB_PERF_SEL_Depth_Tile_Cache_hits',
88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes',
89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile',
90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop',
91: 'DB_PERF_SEL_Depth_Tile_Cache_event',
92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees',
93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees',
94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve',
95: 'DB_PERF_SEL_Stencil_Cache_misses',
96: 'DB_PERF_SEL_Stencil_Cache_hits',
97: 'DB_PERF_SEL_Stencil_Cache_flushes',
98: 'DB_PERF_SEL_Stencil_Cache_starves',
99: 'DB_PERF_SEL_Stencil_Cache_frees',
100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses',
101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits',
102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes',
103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves',
104: 'DB_PERF_SEL_Z_Cache_pmask_misses',
105: 'DB_PERF_SEL_Z_Cache_pmask_hits',
106: 'DB_PERF_SEL_Z_Cache_pmask_flushes',
107: 'DB_PERF_SEL_Z_Cache_pmask_starves',
108: 'DB_PERF_SEL_Z_Cache_frees',
109: 'DB_PERF_SEL_Plane_Cache_misses',
110: 'DB_PERF_SEL_Plane_Cache_hits',
111: 'DB_PERF_SEL_Plane_Cache_flushes',
112: 'DB_PERF_SEL_Plane_Cache_starves',
113: 'DB_PERF_SEL_Plane_Cache_frees',
114: 'DB_PERF_SEL_flush_expanded_stencil',
115: 'DB_PERF_SEL_flush_compressed_stencil',
116: 'DB_PERF_SEL_flush_single_stencil',
117: 'DB_PERF_SEL_planes_flushed',
118: 'DB_PERF_SEL_flush_1plane',
119: 'DB_PERF_SEL_flush_2plane',
120: 'DB_PERF_SEL_flush_3plane',
121: 'DB_PERF_SEL_flush_4plane',
122: 'DB_PERF_SEL_flush_5plane',
123: 'DB_PERF_SEL_flush_6plane',
124: 'DB_PERF_SEL_flush_7plane',
125: 'DB_PERF_SEL_flush_8plane',
126: 'DB_PERF_SEL_flush_9plane',
127: 'DB_PERF_SEL_flush_10plane',
128: 'DB_PERF_SEL_flush_11plane',
129: 'DB_PERF_SEL_flush_12plane',
130: 'DB_PERF_SEL_flush_13plane',
131: 'DB_PERF_SEL_flush_14plane',
132: 'DB_PERF_SEL_flush_15plane',
133: 'DB_PERF_SEL_flush_16plane',
134: 'DB_PERF_SEL_flush_expanded_z',
135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done',
136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done',
137: 'DB_PERF_SEL_dk_tile_sends',
138: 'DB_PERF_SEL_dk_tile_busy',
139: 'DB_PERF_SEL_dk_tile_quad_starves',
140: 'DB_PERF_SEL_dk_tile_stalls',
141: 'DB_PERF_SEL_dk_squad_sends',
142: 'DB_PERF_SEL_dk_squad_busy',
143: 'DB_PERF_SEL_dk_squad_stalls',
144: 'DB_PERF_SEL_Op_Pipe_Busy',
145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall',
146: 'DB_PERF_SEL_qc_busy',
147: 'DB_PERF_SEL_qc_xfc',
148: 'DB_PERF_SEL_qc_conflicts',
149: 'DB_PERF_SEL_qc_full_stall',
150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ',
151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ',
152: 'DB_PERF_SEL_tsc_insert_summarize_stall',
153: 'DB_PERF_SEL_tl_busy',
154: 'DB_PERF_SEL_tl_dtc_read_starved',
155: 'DB_PERF_SEL_tl_z_fetch_stall',
156: 'DB_PERF_SEL_tl_stencil_stall',
157: 'DB_PERF_SEL_tl_z_decompress_stall',
158: 'DB_PERF_SEL_tl_stencil_locked_stall',
159: 'DB_PERF_SEL_tl_events',
160: 'DB_PERF_SEL_tl_summarize_squads',
161: 'DB_PERF_SEL_tl_flush_expand_squads',
162: 'DB_PERF_SEL_tl_expand_squads',
163: 'DB_PERF_SEL_tl_preZ_squads',
164: 'DB_PERF_SEL_tl_postZ_squads',
165: 'DB_PERF_SEL_tl_preZ_noop_squads',
166: 'DB_PERF_SEL_tl_postZ_noop_squads',
167: 'DB_PERF_SEL_tl_tile_ops',
168: 'DB_PERF_SEL_tl_in_xfc',
169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall',
170: 'DB_PERF_SEL_tl_in_fast_z_stall',
171: 'DB_PERF_SEL_tl_out_xfc',
172: 'DB_PERF_SEL_tl_out_squads',
173: 'DB_PERF_SEL_zf_plane_multicycle',
174: 'DB_PERF_SEL_PostZ_Samples_passing_Z',
175: 'DB_PERF_SEL_PostZ_Samples_failing_Z',
176: 'DB_PERF_SEL_PostZ_Samples_failing_S',
177: 'DB_PERF_SEL_PreZ_Samples_passing_Z',
178: 'DB_PERF_SEL_PreZ_Samples_failing_Z',
179: 'DB_PERF_SEL_PreZ_Samples_failing_S',
180: 'DB_PERF_SEL_ts_tc_update_stall',
181: 'DB_PERF_SEL_sc_kick_start',
182: 'DB_PERF_SEL_sc_kick_end',
183: 'DB_PERF_SEL_clock_reg_active',
184: 'DB_PERF_SEL_clock_main_active',
185: 'DB_PERF_SEL_clock_mem_export_active',
186: 'DB_PERF_SEL_esr_ps_out_busy',
187: 'DB_PERF_SEL_esr_ps_lqf_busy',
188: 'DB_PERF_SEL_esr_ps_lqf_stall',
189: 'DB_PERF_SEL_etr_out_send',
190: 'DB_PERF_SEL_etr_out_busy',
191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall',
193: 'DB_PERF_SEL_etr_out_esr_stall',
194: 'DB_PERF_SEL_esr_ps_vic_busy',
195: 'DB_PERF_SEL_esr_ps_vic_stall',
196: 'DB_PERF_SEL_esr_eot_fwd_busy',
197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad',
198: 'DB_PERF_SEL_esr_eot_fwd_forward',
199: 'DB_PERF_SEL_esr_sqq_zi_busy',
200: 'DB_PERF_SEL_esr_sqq_zi_stall',
201: 'DB_PERF_SEL_postzl_sq_pt_busy',
202: 'DB_PERF_SEL_postzl_sq_pt_stall',
203: 'DB_PERF_SEL_postzl_se_busy',
204: 'DB_PERF_SEL_postzl_se_stall',
205: 'DB_PERF_SEL_postzl_partial_launch',
206: 'DB_PERF_SEL_postzl_full_launch',
207: 'DB_PERF_SEL_postzl_partial_waiting',
208: 'DB_PERF_SEL_postzl_tile_mem_stall',
209: 'DB_PERF_SEL_postzl_tile_init_stall',
210: 'DB_PERF_SEL_prezl_tile_mem_stall',
211: 'DB_PERF_SEL_prezl_tile_init_stall',
212: 'DB_PERF_SEL_dtt_sm_clash_stall',
213: 'DB_PERF_SEL_dtt_sm_slot_stall',
214: 'DB_PERF_SEL_dtt_sm_miss_stall',
215: 'DB_PERF_SEL_mi_rdreq_busy',
216: 'DB_PERF_SEL_mi_rdreq_stall',
217: 'DB_PERF_SEL_mi_wrreq_busy',
218: 'DB_PERF_SEL_mi_wrreq_stall',
219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop',
220: 'DB_PERF_SEL_dkg_tile_rate_tile',
221: 'DB_PERF_SEL_prezl_src_in_sends',
222: 'DB_PERF_SEL_prezl_src_in_stall',
223: 'DB_PERF_SEL_prezl_src_in_squads',
224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled',
225: 'DB_PERF_SEL_prezl_src_in_tile_rate',
226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled',
227: 'DB_PERF_SEL_prezl_src_out_stall',
228: 'DB_PERF_SEL_postzl_src_in_sends',
229: 'DB_PERF_SEL_postzl_src_in_stall',
230: 'DB_PERF_SEL_postzl_src_in_squads',
231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled',
232: 'DB_PERF_SEL_postzl_src_in_tile_rate',
233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled',
234: 'DB_PERF_SEL_postzl_src_out_stall',
235: 'DB_PERF_SEL_esr_ps_src_in_sends',
236: 'DB_PERF_SEL_esr_ps_src_in_stall',
237: 'DB_PERF_SEL_esr_ps_src_in_squads',
238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled',
239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate',
240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled',
241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate',
242: 'DB_PERF_SEL_esr_ps_src_out_stall',
243: 'DB_PERF_SEL_depth_bounds_tile_culled',
244: 'DB_PERF_SEL_PreZ_Samples_failing_DB',
245: 'DB_PERF_SEL_PostZ_Samples_failing_DB',
246: 'DB_PERF_SEL_flush_compressed',
247: 'DB_PERF_SEL_flush_plane_le4',
248: 'DB_PERF_SEL_tiles_z_fully_summarized',
249: 'DB_PERF_SEL_tiles_stencil_fully_summarized',
250: 'DB_PERF_SEL_tiles_z_clear_on_expclear',
251: 'DB_PERF_SEL_tiles_s_clear_on_expclear',
252: 'DB_PERF_SEL_tiles_decomp_on_expclear',
253: 'DB_PERF_SEL_tiles_compressed_to_decompressed',
254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy',
255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy',
256: 'DB_PERF_SEL_di_dt_stall',
258: 'DB_PERF_SEL_DB_SC_s_tile_rate',
259: 'DB_PERF_SEL_DB_SC_c_tile_rate',
260: 'DB_PERF_SEL_DB_SC_z_tile_rate',
261: 'DB_PERF_SEL_DB_CB_export_export_quads',
262: 'DB_PERF_SEL_DB_CB_export_double_format',
263: 'DB_PERF_SEL_DB_CB_export_fast_format',
264: 'DB_PERF_SEL_DB_CB_export_slow_format',
265: 'DB_PERF_SEL_CB_DB_rdreq_sends',
266: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends',
267: 'DB_PERF_SEL_CB_DB_wrreq_sends',
268: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends',
269: 'DB_PERF_SEL_DB_CB_rdret_ack',
270: 'DB_PERF_SEL_DB_CB_rdret_nack',
271: 'DB_PERF_SEL_DB_CB_wrret_ack',
272: 'DB_PERF_SEL_DB_CB_wrret_nack',
273: 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall',
274: 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall',
275: 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall',
276: 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall',
277: 'DB_PERF_SEL_unmapped_z_tile_culled',
278: 'DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_DB_DATA_TS',
279: 'DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_CB_PIXEL_DATA',
280: 'DB_PERF_SEL_DB_CB_export_is_event_BOTTOM_OF_PIPE_TS',
281: 'DB_PERF_SEL_DB_CB_export_waiting_for_perfcounter_stop_event',
282: 'DB_PERF_SEL_DB_CB_export_fmt_32bpp_8pix',
283: 'DB_PERF_SEL_DB_CB_export_fmt_16_16_unsigned_8pix',
284: 'DB_PERF_SEL_DB_CB_export_fmt_16_16_signed_8pix',
285: 'DB_PERF_SEL_DB_CB_export_fmt_16_16_float_8pix',
286: 'DB_PERF_SEL_DB_CB_export_num_pixels_need_blending',
287: 'DB_PERF_SEL_DB_CB_context_dones',
288: 'DB_PERF_SEL_DB_CB_eop_dones',
289: 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed',
290: 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled',
291: 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read',
292: 'DB_PERF_SEL_SC_DB_tile_backface',
293: 'DB_PERF_SEL_SC_DB_quad_quads',
294: 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel',
295: 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels',
296: 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels',
297: 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels',
298: 'DB_PERF_SEL_DB_SC_quad_double_quad',
299: 'DB_PERF_SEL_SX_DB_quad_export_quads',
300: 'DB_PERF_SEL_SX_DB_quad_double_format',
301: 'DB_PERF_SEL_SX_DB_quad_fast_format',
302: 'DB_PERF_SEL_SX_DB_quad_slow_format',
303: 'DB_PERF_SEL_quad_rd_sends_unc',
304: 'DB_PERF_SEL_quad_rd_mi_stall_unc',
305: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0',
306: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1',
307: 'DB_PERF_SEL_SC_DB_quad_quads_pipe0',
308: 'DB_PERF_SEL_SC_DB_quad_quads_pipe1',
309: 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits',
310: 'DB_PERF_SEL_noz_waiting_for_postz_done',
311: 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x1',
312: 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x1',
313: 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x2',
314: 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x2',
315: 'DB_PERF_SEL_RMI_rd_tile_32byte_req',
316: 'DB_PERF_SEL_RMI_rd_z_32byte_req',
317: 'DB_PERF_SEL_RMI_rd_s_32byte_req',
318: 'DB_PERF_SEL_RMI_wr_tile_32byte_req',
319: 'DB_PERF_SEL_RMI_wr_z_32byte_req',
320: 'DB_PERF_SEL_RMI_wr_s_32byte_req',
321: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req',
322: 'DB_PERF_SEL_RMI_rd_tile_32byte_ret',
323: 'DB_PERF_SEL_RMI_rd_z_32byte_ret',
324: 'DB_PERF_SEL_RMI_rd_s_32byte_ret',
325: 'DB_PERF_SEL_RMI_wr_tile_32byte_ack',
326: 'DB_PERF_SEL_RMI_wr_z_32byte_ack',
327: 'DB_PERF_SEL_RMI_wr_s_32byte_ack',
328: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack',
329: 'DB_PERF_SEL_esr_vic_sqq_busy',
330: 'DB_PERF_SEL_esr_vic_sqq_stall',
331: 'DB_PERF_SEL_esr_psi_vic_tile_rate',
332: 'DB_PERF_SEL_esr_vic_footprint_match_2x2',
333: 'DB_PERF_SEL_esr_vic_footprint_match_2x1',
334: 'DB_PERF_SEL_esr_vic_footprint_match_1x2',
335: 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels',
336: 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels',
337: 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels',
338: 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1',
339: 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1',
340: 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut',
341: 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut',
342: 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt',
343: 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt',
344: 'DB_PERF_SEL_ts_events_pws_enable',
345: 'DB_PERF_SEL_ps_events_pws_enable',
346: 'DB_PERF_SEL_cs_events_pws_enable',
347: 'DB_PERF_SEL_DB_SC_quad_noz_tiles',
348: 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad',
349: 'DB_PERF_SEL_DB_SC_quad_conflicts',
350: 'DB_PERF_SEL_SC_DB_quad_vrs_1x1',
351: 'DB_PERF_SEL_SC_DB_quad_vrs_1x2',
352: 'DB_PERF_SEL_SC_DB_quad_vrs_2x1',
353: 'DB_PERF_SEL_SC_DB_quad_vrs_2x2',
354: 'DB_PERF_SEL_SC_DB_quad_vrs_2x_ssaa',
355: 'DB_PERF_SEL_SC_DB_quad_vrs_4x_ssaa',
356: 'DB_PERF_SEL_SC_DB_quad_vrs_8x_ssaa',
357: 'DB_PERF_SEL_SC_DB_wave_sends',
358: 'DB_PERF_SEL_SC_DB_wave_busy',
359: 'DB_PERF_SEL_SC_DB_wave_quads',
360: 'DB_PERF_SEL_SC_DB_wave_id_wrapped',
361: 'DB_PERF_SEL_DB_SC_wave_sends',
362: 'DB_PERF_SEL_DB_SC_wave_busy',
363: 'DB_PERF_SEL_DB_SC_wave_stalls',
364: 'DB_PERF_SEL_DB_SC_wave_conflict',
365: 'DB_PERF_SEL_DB_SC_wave_hard_conflict',
366: 'DB_PERF_SEL_DB_SC_wave_id_wrapped',
367: 'DB_PERF_SEL_SX_DB_quad_waves',
368: 'DB_PERF_SEL_pws_stall',
369: 'DB_PERF_SEL_pws_liveness_stall_dtt_tag',
370: 'DB_PERF_SEL_pws_liveness_stall_tcp_cache_mgr',
371: 'DB_PERF_SEL_OREO_TT_load',
372: 'DB_PERF_SEL_OREO_TT_read',
373: 'DB_PERF_SEL_OREO_TT_stalls',
374: 'DB_PERF_SEL_OREO_ST_load',
375: 'DB_PERF_SEL_OREO_ST_read',
376: 'DB_PERF_SEL_OREO_ST_stalls',
377: 'DB_PERF_SEL_OREO_WT_load',
378: 'DB_PERF_SEL_OREO_WT_read',
379: 'DB_PERF_SEL_OREO_SB_misses',
380: 'DB_PERF_SEL_OREO_SB_hits',
381: 'DB_PERF_SEL_OREO_SB_evicts',
382: 'DB_PERF_SEL_OREO_SB_stalls',
383: 'DB_PERF_SEL_OREO_Events_load',
384: 'DB_PERF_SEL_OREO_Events_transition',
385: 'DB_PERF_SEL_OREO_Events_non_transition',
386: 'DB_PERF_SEL_OREO_Events_delayed',
387: 'DB_PERF_SEL_OREO_Events_stalls',
}
DB_PERF_SEL_SC_DB_tile_sends = 0
DB_PERF_SEL_SC_DB_tile_busy = 1
DB_PERF_SEL_SC_DB_tile_stalls = 2
DB_PERF_SEL_SC_DB_tile_events = 3
DB_PERF_SEL_SC_DB_tile_tiles = 4
DB_PERF_SEL_SC_DB_tile_covered = 5
DB_PERF_SEL_hiz_tc_read_starved = 6
DB_PERF_SEL_hiz_tc_write_stall = 7
DB_PERF_SEL_hiz_tile_culled = 8
DB_PERF_SEL_his_tile_culled = 9
DB_PERF_SEL_DB_SC_tile_sends = 10
DB_PERF_SEL_DB_SC_tile_busy = 11
DB_PERF_SEL_DB_SC_tile_stalls = 12
DB_PERF_SEL_DB_SC_tile_df_stalls = 13
DB_PERF_SEL_DB_SC_tile_tiles = 14
DB_PERF_SEL_DB_SC_tile_culled = 15
DB_PERF_SEL_DB_SC_tile_hier_kill = 16
DB_PERF_SEL_DB_SC_tile_fast_ops = 17
DB_PERF_SEL_DB_SC_tile_no_ops = 18
DB_PERF_SEL_DB_SC_tile_tile_rate = 19
DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20
DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21
DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22
DB_PERF_SEL_SC_DB_quad_sends = 23
DB_PERF_SEL_SC_DB_quad_busy = 24
DB_PERF_SEL_SC_DB_quad_squads = 25
DB_PERF_SEL_SC_DB_quad_tiles = 26
DB_PERF_SEL_SC_DB_quad_pixels = 27
DB_PERF_SEL_SC_DB_quad_killed_tiles = 28
DB_PERF_SEL_DB_SC_quad_sends = 29
DB_PERF_SEL_DB_SC_quad_busy = 30
DB_PERF_SEL_DB_SC_quad_stalls = 31
DB_PERF_SEL_DB_SC_quad_tiles = 32
DB_PERF_SEL_DB_SC_quad_lit_quad = 33
DB_PERF_SEL_DB_CB_export_events = 34
DB_PERF_SEL_SX_DB_quad_sends = 37
DB_PERF_SEL_SX_DB_quad_busy = 38
DB_PERF_SEL_SX_DB_quad_stalls = 39
DB_PERF_SEL_SX_DB_quad_quads = 40
DB_PERF_SEL_SX_DB_quad_pixels = 41
DB_PERF_SEL_SX_DB_quad_exports = 42
DB_PERF_SEL_SH_quads_outstanding_sum = 43
DB_PERF_SEL_DB_CB_export_sends = 44
DB_PERF_SEL_DB_CB_export_busy = 45
DB_PERF_SEL_DB_CB_export_stalls = 46
DB_PERF_SEL_DB_CB_export_quads = 47
DB_PERF_SEL_tile_rd_sends = 48
DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49
DB_PERF_SEL_quad_rd_sends = 50
DB_PERF_SEL_quad_rd_busy = 51
DB_PERF_SEL_quad_rd_mi_stall = 52
DB_PERF_SEL_quad_rd_rw_collision = 53
DB_PERF_SEL_quad_rd_tag_stall = 54
DB_PERF_SEL_quad_rd_32byte_reqs = 55
DB_PERF_SEL_quad_rd_panic = 56
DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57
DB_PERF_SEL_quad_rdret_sends = 58
DB_PERF_SEL_quad_rdret_busy = 59
DB_PERF_SEL_tile_wr_sends = 60
DB_PERF_SEL_tile_wr_acks = 61
DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62
DB_PERF_SEL_quad_wr_sends = 63
DB_PERF_SEL_quad_wr_busy = 64
DB_PERF_SEL_quad_wr_mi_stall = 65
DB_PERF_SEL_quad_wr_coherency_stall = 66
DB_PERF_SEL_quad_wr_acks = 67
DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68
DB_PERF_SEL_Tile_Cache_misses = 69
DB_PERF_SEL_Tile_Cache_hits = 70
DB_PERF_SEL_Tile_Cache_flushes = 71
DB_PERF_SEL_Tile_Cache_surface_stall = 72
DB_PERF_SEL_Tile_Cache_starves = 73
DB_PERF_SEL_Tile_Cache_mem_return_starve = 74
DB_PERF_SEL_tcp_dispatcher_reads = 75
DB_PERF_SEL_tcp_prefetcher_reads = 76
DB_PERF_SEL_tcp_preloader_reads = 77
DB_PERF_SEL_tcp_dispatcher_flushes = 78
DB_PERF_SEL_tcp_prefetcher_flushes = 79
DB_PERF_SEL_tcp_preloader_flushes = 80
DB_PERF_SEL_Depth_Tile_Cache_sends = 81
DB_PERF_SEL_Depth_Tile_Cache_busy = 82
DB_PERF_SEL_Depth_Tile_Cache_starves = 83
DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84
DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85
DB_PERF_SEL_Depth_Tile_Cache_misses = 86
DB_PERF_SEL_Depth_Tile_Cache_hits = 87
DB_PERF_SEL_Depth_Tile_Cache_flushes = 88
DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89
DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90
DB_PERF_SEL_Depth_Tile_Cache_event = 91
DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92
DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93
DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94
DB_PERF_SEL_Stencil_Cache_misses = 95
DB_PERF_SEL_Stencil_Cache_hits = 96
DB_PERF_SEL_Stencil_Cache_flushes = 97
DB_PERF_SEL_Stencil_Cache_starves = 98
DB_PERF_SEL_Stencil_Cache_frees = 99
DB_PERF_SEL_Z_Cache_separate_Z_misses = 100
DB_PERF_SEL_Z_Cache_separate_Z_hits = 101
DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102
DB_PERF_SEL_Z_Cache_separate_Z_starves = 103
DB_PERF_SEL_Z_Cache_pmask_misses = 104
DB_PERF_SEL_Z_Cache_pmask_hits = 105
DB_PERF_SEL_Z_Cache_pmask_flushes = 106
DB_PERF_SEL_Z_Cache_pmask_starves = 107
DB_PERF_SEL_Z_Cache_frees = 108
DB_PERF_SEL_Plane_Cache_misses = 109
DB_PERF_SEL_Plane_Cache_hits = 110
DB_PERF_SEL_Plane_Cache_flushes = 111
DB_PERF_SEL_Plane_Cache_starves = 112
DB_PERF_SEL_Plane_Cache_frees = 113
DB_PERF_SEL_flush_expanded_stencil = 114
DB_PERF_SEL_flush_compressed_stencil = 115
DB_PERF_SEL_flush_single_stencil = 116
DB_PERF_SEL_planes_flushed = 117
DB_PERF_SEL_flush_1plane = 118
DB_PERF_SEL_flush_2plane = 119
DB_PERF_SEL_flush_3plane = 120
DB_PERF_SEL_flush_4plane = 121
DB_PERF_SEL_flush_5plane = 122
DB_PERF_SEL_flush_6plane = 123
DB_PERF_SEL_flush_7plane = 124
DB_PERF_SEL_flush_8plane = 125
DB_PERF_SEL_flush_9plane = 126
DB_PERF_SEL_flush_10plane = 127
DB_PERF_SEL_flush_11plane = 128
DB_PERF_SEL_flush_12plane = 129
DB_PERF_SEL_flush_13plane = 130
DB_PERF_SEL_flush_14plane = 131
DB_PERF_SEL_flush_15plane = 132
DB_PERF_SEL_flush_16plane = 133
DB_PERF_SEL_flush_expanded_z = 134
DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135
DB_PERF_SEL_reZ_waiting_for_postZ_done = 136
DB_PERF_SEL_dk_tile_sends = 137
DB_PERF_SEL_dk_tile_busy = 138
DB_PERF_SEL_dk_tile_quad_starves = 139
DB_PERF_SEL_dk_tile_stalls = 140
DB_PERF_SEL_dk_squad_sends = 141
DB_PERF_SEL_dk_squad_busy = 142
DB_PERF_SEL_dk_squad_stalls = 143
DB_PERF_SEL_Op_Pipe_Busy = 144
DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145
DB_PERF_SEL_qc_busy = 146
DB_PERF_SEL_qc_xfc = 147
DB_PERF_SEL_qc_conflicts = 148
DB_PERF_SEL_qc_full_stall = 149
DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150
DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151
DB_PERF_SEL_tsc_insert_summarize_stall = 152
DB_PERF_SEL_tl_busy = 153
DB_PERF_SEL_tl_dtc_read_starved = 154
DB_PERF_SEL_tl_z_fetch_stall = 155
DB_PERF_SEL_tl_stencil_stall = 156
DB_PERF_SEL_tl_z_decompress_stall = 157
DB_PERF_SEL_tl_stencil_locked_stall = 158
DB_PERF_SEL_tl_events = 159
DB_PERF_SEL_tl_summarize_squads = 160
DB_PERF_SEL_tl_flush_expand_squads = 161
DB_PERF_SEL_tl_expand_squads = 162
DB_PERF_SEL_tl_preZ_squads = 163
DB_PERF_SEL_tl_postZ_squads = 164
DB_PERF_SEL_tl_preZ_noop_squads = 165
DB_PERF_SEL_tl_postZ_noop_squads = 166
DB_PERF_SEL_tl_tile_ops = 167
DB_PERF_SEL_tl_in_xfc = 168
DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169
DB_PERF_SEL_tl_in_fast_z_stall = 170
DB_PERF_SEL_tl_out_xfc = 171
DB_PERF_SEL_tl_out_squads = 172
DB_PERF_SEL_zf_plane_multicycle = 173
DB_PERF_SEL_PostZ_Samples_passing_Z = 174
DB_PERF_SEL_PostZ_Samples_failing_Z = 175
DB_PERF_SEL_PostZ_Samples_failing_S = 176
DB_PERF_SEL_PreZ_Samples_passing_Z = 177
DB_PERF_SEL_PreZ_Samples_failing_Z = 178
DB_PERF_SEL_PreZ_Samples_failing_S = 179
DB_PERF_SEL_ts_tc_update_stall = 180
DB_PERF_SEL_sc_kick_start = 181
DB_PERF_SEL_sc_kick_end = 182
DB_PERF_SEL_clock_reg_active = 183
DB_PERF_SEL_clock_main_active = 184
DB_PERF_SEL_clock_mem_export_active = 185
DB_PERF_SEL_esr_ps_out_busy = 186
DB_PERF_SEL_esr_ps_lqf_busy = 187
DB_PERF_SEL_esr_ps_lqf_stall = 188
DB_PERF_SEL_etr_out_send = 189
DB_PERF_SEL_etr_out_busy = 190
DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191
DB_PERF_SEL_etr_out_esr_stall = 193
DB_PERF_SEL_esr_ps_vic_busy = 194
DB_PERF_SEL_esr_ps_vic_stall = 195
DB_PERF_SEL_esr_eot_fwd_busy = 196
DB_PERF_SEL_esr_eot_fwd_holding_squad = 197
DB_PERF_SEL_esr_eot_fwd_forward = 198
DB_PERF_SEL_esr_sqq_zi_busy = 199
DB_PERF_SEL_esr_sqq_zi_stall = 200
DB_PERF_SEL_postzl_sq_pt_busy = 201
DB_PERF_SEL_postzl_sq_pt_stall = 202
DB_PERF_SEL_postzl_se_busy = 203
DB_PERF_SEL_postzl_se_stall = 204
DB_PERF_SEL_postzl_partial_launch = 205
DB_PERF_SEL_postzl_full_launch = 206
DB_PERF_SEL_postzl_partial_waiting = 207
DB_PERF_SEL_postzl_tile_mem_stall = 208
DB_PERF_SEL_postzl_tile_init_stall = 209
DB_PERF_SEL_prezl_tile_mem_stall = 210
DB_PERF_SEL_prezl_tile_init_stall = 211
DB_PERF_SEL_dtt_sm_clash_stall = 212
DB_PERF_SEL_dtt_sm_slot_stall = 213
DB_PERF_SEL_dtt_sm_miss_stall = 214
DB_PERF_SEL_mi_rdreq_busy = 215
DB_PERF_SEL_mi_rdreq_stall = 216
DB_PERF_SEL_mi_wrreq_busy = 217
DB_PERF_SEL_mi_wrreq_stall = 218
DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219
DB_PERF_SEL_dkg_tile_rate_tile = 220
DB_PERF_SEL_prezl_src_in_sends = 221
DB_PERF_SEL_prezl_src_in_stall = 222
DB_PERF_SEL_prezl_src_in_squads = 223
DB_PERF_SEL_prezl_src_in_squads_unrolled = 224
DB_PERF_SEL_prezl_src_in_tile_rate = 225
DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226
DB_PERF_SEL_prezl_src_out_stall = 227
DB_PERF_SEL_postzl_src_in_sends = 228
DB_PERF_SEL_postzl_src_in_stall = 229
DB_PERF_SEL_postzl_src_in_squads = 230
DB_PERF_SEL_postzl_src_in_squads_unrolled = 231
DB_PERF_SEL_postzl_src_in_tile_rate = 232
DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233
DB_PERF_SEL_postzl_src_out_stall = 234
DB_PERF_SEL_esr_ps_src_in_sends = 235
DB_PERF_SEL_esr_ps_src_in_stall = 236
DB_PERF_SEL_esr_ps_src_in_squads = 237
DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238
DB_PERF_SEL_esr_ps_src_in_tile_rate = 239
DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240
DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241
DB_PERF_SEL_esr_ps_src_out_stall = 242
DB_PERF_SEL_depth_bounds_tile_culled = 243
DB_PERF_SEL_PreZ_Samples_failing_DB = 244
DB_PERF_SEL_PostZ_Samples_failing_DB = 245
DB_PERF_SEL_flush_compressed = 246
DB_PERF_SEL_flush_plane_le4 = 247
DB_PERF_SEL_tiles_z_fully_summarized = 248
DB_PERF_SEL_tiles_stencil_fully_summarized = 249
DB_PERF_SEL_tiles_z_clear_on_expclear = 250
DB_PERF_SEL_tiles_s_clear_on_expclear = 251
DB_PERF_SEL_tiles_decomp_on_expclear = 252
DB_PERF_SEL_tiles_compressed_to_decompressed = 253
DB_PERF_SEL_Op_Pipe_Prez_Busy = 254
DB_PERF_SEL_Op_Pipe_Postz_Busy = 255
DB_PERF_SEL_di_dt_stall = 256
DB_PERF_SEL_DB_SC_s_tile_rate = 258
DB_PERF_SEL_DB_SC_c_tile_rate = 259
DB_PERF_SEL_DB_SC_z_tile_rate = 260
DB_PERF_SEL_DB_CB_export_export_quads = 261
DB_PERF_SEL_DB_CB_export_double_format = 262
DB_PERF_SEL_DB_CB_export_fast_format = 263
DB_PERF_SEL_DB_CB_export_slow_format = 264
DB_PERF_SEL_CB_DB_rdreq_sends = 265
DB_PERF_SEL_CB_DB_rdreq_prt_sends = 266
DB_PERF_SEL_CB_DB_wrreq_sends = 267
DB_PERF_SEL_CB_DB_wrreq_prt_sends = 268
DB_PERF_SEL_DB_CB_rdret_ack = 269
DB_PERF_SEL_DB_CB_rdret_nack = 270
DB_PERF_SEL_DB_CB_wrret_ack = 271
DB_PERF_SEL_DB_CB_wrret_nack = 272
DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 273
DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 274
DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 275
DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 276
DB_PERF_SEL_unmapped_z_tile_culled = 277
DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_DB_DATA_TS = 278
DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 279
DB_PERF_SEL_DB_CB_export_is_event_BOTTOM_OF_PIPE_TS = 280
DB_PERF_SEL_DB_CB_export_waiting_for_perfcounter_stop_event = 281
DB_PERF_SEL_DB_CB_export_fmt_32bpp_8pix = 282
DB_PERF_SEL_DB_CB_export_fmt_16_16_unsigned_8pix = 283
DB_PERF_SEL_DB_CB_export_fmt_16_16_signed_8pix = 284
DB_PERF_SEL_DB_CB_export_fmt_16_16_float_8pix = 285
DB_PERF_SEL_DB_CB_export_num_pixels_need_blending = 286
DB_PERF_SEL_DB_CB_context_dones = 287
DB_PERF_SEL_DB_CB_eop_dones = 288
DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 289
DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 290
DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 291
DB_PERF_SEL_SC_DB_tile_backface = 292
DB_PERF_SEL_SC_DB_quad_quads = 293
DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 294
DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 295
DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 296
DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 297
DB_PERF_SEL_DB_SC_quad_double_quad = 298
DB_PERF_SEL_SX_DB_quad_export_quads = 299
DB_PERF_SEL_SX_DB_quad_double_format = 300
DB_PERF_SEL_SX_DB_quad_fast_format = 301
DB_PERF_SEL_SX_DB_quad_slow_format = 302
DB_PERF_SEL_quad_rd_sends_unc = 303
DB_PERF_SEL_quad_rd_mi_stall_unc = 304
DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 305
DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 306
DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 307
DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 308
DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 309
DB_PERF_SEL_noz_waiting_for_postz_done = 310
DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x1 = 311
DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x1 = 312
DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x2 = 313
DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x2 = 314
DB_PERF_SEL_RMI_rd_tile_32byte_req = 315
DB_PERF_SEL_RMI_rd_z_32byte_req = 316
DB_PERF_SEL_RMI_rd_s_32byte_req = 317
DB_PERF_SEL_RMI_wr_tile_32byte_req = 318
DB_PERF_SEL_RMI_wr_z_32byte_req = 319
DB_PERF_SEL_RMI_wr_s_32byte_req = 320
DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 321
DB_PERF_SEL_RMI_rd_tile_32byte_ret = 322
DB_PERF_SEL_RMI_rd_z_32byte_ret = 323
DB_PERF_SEL_RMI_rd_s_32byte_ret = 324
DB_PERF_SEL_RMI_wr_tile_32byte_ack = 325
DB_PERF_SEL_RMI_wr_z_32byte_ack = 326
DB_PERF_SEL_RMI_wr_s_32byte_ack = 327
DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 328
DB_PERF_SEL_esr_vic_sqq_busy = 329
DB_PERF_SEL_esr_vic_sqq_stall = 330
DB_PERF_SEL_esr_psi_vic_tile_rate = 331
DB_PERF_SEL_esr_vic_footprint_match_2x2 = 332
DB_PERF_SEL_esr_vic_footprint_match_2x1 = 333
DB_PERF_SEL_esr_vic_footprint_match_1x2 = 334
DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 335
DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 336
DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 337
DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 338
DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 339
DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 340
DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 341
DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 342
DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 343
DB_PERF_SEL_ts_events_pws_enable = 344
DB_PERF_SEL_ps_events_pws_enable = 345
DB_PERF_SEL_cs_events_pws_enable = 346
DB_PERF_SEL_DB_SC_quad_noz_tiles = 347
DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 348
DB_PERF_SEL_DB_SC_quad_conflicts = 349
DB_PERF_SEL_SC_DB_quad_vrs_1x1 = 350
DB_PERF_SEL_SC_DB_quad_vrs_1x2 = 351
DB_PERF_SEL_SC_DB_quad_vrs_2x1 = 352
DB_PERF_SEL_SC_DB_quad_vrs_2x2 = 353
DB_PERF_SEL_SC_DB_quad_vrs_2x_ssaa = 354
DB_PERF_SEL_SC_DB_quad_vrs_4x_ssaa = 355
DB_PERF_SEL_SC_DB_quad_vrs_8x_ssaa = 356
DB_PERF_SEL_SC_DB_wave_sends = 357
DB_PERF_SEL_SC_DB_wave_busy = 358
DB_PERF_SEL_SC_DB_wave_quads = 359
DB_PERF_SEL_SC_DB_wave_id_wrapped = 360
DB_PERF_SEL_DB_SC_wave_sends = 361
DB_PERF_SEL_DB_SC_wave_busy = 362
DB_PERF_SEL_DB_SC_wave_stalls = 363
DB_PERF_SEL_DB_SC_wave_conflict = 364
DB_PERF_SEL_DB_SC_wave_hard_conflict = 365
DB_PERF_SEL_DB_SC_wave_id_wrapped = 366
DB_PERF_SEL_SX_DB_quad_waves = 367
DB_PERF_SEL_pws_stall = 368
DB_PERF_SEL_pws_liveness_stall_dtt_tag = 369
DB_PERF_SEL_pws_liveness_stall_tcp_cache_mgr = 370
DB_PERF_SEL_OREO_TT_load = 371
DB_PERF_SEL_OREO_TT_read = 372
DB_PERF_SEL_OREO_TT_stalls = 373
DB_PERF_SEL_OREO_ST_load = 374
DB_PERF_SEL_OREO_ST_read = 375
DB_PERF_SEL_OREO_ST_stalls = 376
DB_PERF_SEL_OREO_WT_load = 377
DB_PERF_SEL_OREO_WT_read = 378
DB_PERF_SEL_OREO_SB_misses = 379
DB_PERF_SEL_OREO_SB_hits = 380
DB_PERF_SEL_OREO_SB_evicts = 381
DB_PERF_SEL_OREO_SB_stalls = 382
DB_PERF_SEL_OREO_Events_load = 383
DB_PERF_SEL_OREO_Events_transition = 384
DB_PERF_SEL_OREO_Events_non_transition = 385
DB_PERF_SEL_OREO_Events_delayed = 386
DB_PERF_SEL_OREO_Events_stalls = 387
PerfCounter_Vals = ctypes.c_uint32 # enum
# values for enumeration 'PixelPipeCounterId'
PixelPipeCounterId__enumvalues = {
0: 'PIXEL_PIPE_OCCLUSION_COUNT_0',
1: 'PIXEL_PIPE_OCCLUSION_COUNT_1',
2: 'PIXEL_PIPE_OCCLUSION_COUNT_2',
3: 'PIXEL_PIPE_OCCLUSION_COUNT_3',
4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0',
5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0',
6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1',
7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1',
}
PIXEL_PIPE_OCCLUSION_COUNT_0 = 0
PIXEL_PIPE_OCCLUSION_COUNT_1 = 1
PIXEL_PIPE_OCCLUSION_COUNT_2 = 2
PIXEL_PIPE_OCCLUSION_COUNT_3 = 3
PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4
PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5
PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6
PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7
PixelPipeCounterId = ctypes.c_uint32 # enum
# values for enumeration 'PixelPipeStride'
PixelPipeStride__enumvalues = {
0: 'PIXEL_PIPE_STRIDE_32_BITS',
1: 'PIXEL_PIPE_STRIDE_64_BITS',
2: 'PIXEL_PIPE_STRIDE_128_BITS',
3: 'PIXEL_PIPE_STRIDE_256_BITS',
}
PIXEL_PIPE_STRIDE_32_BITS = 0
PIXEL_PIPE_STRIDE_64_BITS = 1
PIXEL_PIPE_STRIDE_128_BITS = 2
PIXEL_PIPE_STRIDE_256_BITS = 3
PixelPipeStride = ctypes.c_uint32 # enum
# values for enumeration 'RingCounterControl'
RingCounterControl__enumvalues = {
0: 'COUNTER_RING_SPLIT',
1: 'COUNTER_RING_0',
2: 'COUNTER_RING_1',
}
COUNTER_RING_SPLIT = 0
COUNTER_RING_0 = 1
COUNTER_RING_1 = 2
RingCounterControl = ctypes.c_uint32 # enum
# values for enumeration 'StencilOp'
StencilOp__enumvalues = {
0: 'STENCIL_KEEP',
1: 'STENCIL_ZERO',
2: 'STENCIL_ONES',
3: 'STENCIL_REPLACE_TEST',
4: 'STENCIL_REPLACE_OP',
5: 'STENCIL_ADD_CLAMP',
6: 'STENCIL_SUB_CLAMP',
7: 'STENCIL_INVERT',
8: 'STENCIL_ADD_WRAP',
9: 'STENCIL_SUB_WRAP',
10: 'STENCIL_AND',
11: 'STENCIL_OR',
12: 'STENCIL_XOR',
13: 'STENCIL_NAND',
14: 'STENCIL_NOR',
15: 'STENCIL_XNOR',
}
STENCIL_KEEP = 0
STENCIL_ZERO = 1
STENCIL_ONES = 2
STENCIL_REPLACE_TEST = 3
STENCIL_REPLACE_OP = 4
STENCIL_ADD_CLAMP = 5
STENCIL_SUB_CLAMP = 6
STENCIL_INVERT = 7
STENCIL_ADD_WRAP = 8
STENCIL_SUB_WRAP = 9
STENCIL_AND = 10
STENCIL_OR = 11
STENCIL_XOR = 12
STENCIL_NAND = 13
STENCIL_NOR = 14
STENCIL_XNOR = 15
StencilOp = ctypes.c_uint32 # enum
# values for enumeration 'ZLimitSumm'
ZLimitSumm__enumvalues = {
0: 'FORCE_SUMM_OFF',
1: 'FORCE_SUMM_MINZ',
2: 'FORCE_SUMM_MAXZ',
3: 'FORCE_SUMM_BOTH',
}
FORCE_SUMM_OFF = 0
FORCE_SUMM_MINZ = 1
FORCE_SUMM_MAXZ = 2
FORCE_SUMM_BOTH = 3
ZLimitSumm = ctypes.c_uint32 # enum
# values for enumeration 'ZModeForce'
ZModeForce__enumvalues = {
0: 'NO_FORCE',
1: 'FORCE_EARLY_Z',
2: 'FORCE_LATE_Z',
3: 'FORCE_RE_Z',
}
NO_FORCE = 0
FORCE_EARLY_Z = 1
FORCE_LATE_Z = 2
FORCE_RE_Z = 3
ZModeForce = ctypes.c_uint32 # enum
# values for enumeration 'ZOrder'
ZOrder__enumvalues = {
0: 'LATE_Z',
1: 'EARLY_Z_THEN_LATE_Z',
2: 'RE_Z',
3: 'EARLY_Z_THEN_RE_Z',
}
LATE_Z = 0
EARLY_Z_THEN_LATE_Z = 1
RE_Z = 2
EARLY_Z_THEN_RE_Z = 3
ZOrder = ctypes.c_uint32 # enum
# values for enumeration 'ZSamplePosition'
ZSamplePosition__enumvalues = {
0: 'Z_SAMPLE_CENTER',
1: 'Z_SAMPLE_CENTROID',
}
Z_SAMPLE_CENTER = 0
Z_SAMPLE_CENTROID = 1
ZSamplePosition = ctypes.c_uint32 # enum
# values for enumeration 'SU_PERFCNT_SEL'
SU_PERFCNT_SEL__enumvalues = {
0: 'PERF_PAPC_PASX_REQ',
6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD',
7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD',
8: 'PERF_CLPR_INPUT_PRIM',
9: 'PERF_CLPR_INPUT_NULL_PRIM',
10: 'PERF_CLPR_INPUT_EVENT',
11: 'PERF_CLPR_INPUT_FIRST_OF_SUBGROUP',
12: 'PERF_CLPR_INPUT_END_OF_PACKET',
13: 'PERF_CLPR_INPUT_EXTENDED_EVENT',
14: 'PERF_PAPC_CLPR_CULL_PRIM',
15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM',
16: 'PERF_PAPC_CLPR_VV_CULL_PRIM',
17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM',
18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM',
19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM',
20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM',
21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM',
22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM',
23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM',
24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE',
25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1',
26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2',
27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3',
28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4',
29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8',
30: 'PERF_CLPR_CLIP_PLANE_CNT_9_PLUS',
31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR',
32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR',
33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT',
34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT',
35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP',
36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM',
38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM',
39: 'PERF_PAPC_CLSM_NULL_PRIM',
40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM',
41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM',
42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1',
43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2',
44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3',
45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4',
46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8',
47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_PLUS',
48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM',
49: 'PERF_PAPC_SU_INPUT_PRIM',
50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM',
51: 'PERF_PAPC_SU_INPUT_NULL_PRIM',
52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL',
53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL',
54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM',
55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM',
56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM',
57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL',
58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL',
59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL',
60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL',
61: 'PERF_PAPC_SU_OUTPUT_PRIM',
62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM',
63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM',
64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG',
65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT',
66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET',
67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE',
68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK',
69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT',
70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE',
71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK',
72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT',
73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL',
74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL',
75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL',
76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL',
77: 'PERF_PAPC_PASX_REQ_IDLE',
78: 'PERF_PAPC_PASX_REQ_BUSY',
79: 'PERF_PAPC_PASX_REQ_STALLED',
80: 'PERF_PAPC_PASX_REC_IDLE',
81: 'PERF_PAPC_PASX_REC_BUSY',
82: 'PERF_PAPC_PASX_REC_STARVED_SX',
83: 'PERF_PAPC_PASX_REC_STALLED',
84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM',
85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN',
86: 'PERF_PAPC_CCGSM_IDLE',
87: 'PERF_PAPC_CCGSM_BUSY',
88: 'PERF_PAPC_CCGSM_STALLED',
89: 'PERF_PAPC_CLPRIM_IDLE',
90: 'PERF_PAPC_CLPRIM_BUSY',
91: 'PERF_PAPC_CLPRIM_STALLED',
92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM',
93: 'PERF_PAPC_CLIPSM_IDLE',
94: 'PERF_PAPC_CLIPSM_BUSY',
95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH',
96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ',
97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA',
98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP',
99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM',
100: 'PERF_PAPC_CLIPGA_IDLE',
101: 'PERF_PAPC_CLIPGA_BUSY',
102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP',
103: 'PERF_PAPC_CLIPGA_STALLED',
104: 'PERF_PAPC_CLIP_IDLE',
105: 'PERF_PAPC_CLIP_BUSY',
106: 'PERF_PAPC_SU_IDLE',
107: 'PERF_PAPC_SU_BUSY',
108: 'PERF_PAPC_SU_STARVED_CLIP',
109: 'PERF_PAPC_SU_STALLED_SC',
110: 'PERF_PAPC_CL_DYN_SCLK_VLD',
111: 'PERF_PAPC_SU_DYN_SCLK_VLD',
112: 'PERF_PAPC_PA_REG_SCLK_VLD',
120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL',
121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL',
123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM',
124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM',
125: 'PERF_PAPC_SU_ALL_OUTPUT_PRIM',
126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM',
127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM',
128: 'PERF_PAPC_SU_ALL_OUTPUT_NULL_PRIM',
131: 'PERF_PAPC_SU_SE0_STALLED_SC',
132: 'PERF_PAPC_SU_SE1_STALLED_SC',
133: 'PERF_PAPC_SU_ALL_STALLED_SC',
134: 'PERF_PAPC_CLSM_CLIPPING_PRIM',
135: 'PERF_PAPC_SU_CULLED_PRIM',
136: 'PERF_PAPC_SU_OUTPUT_EOPG',
137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL',
138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL',
139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM',
140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM',
141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM',
142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM',
151: 'PERF_PAPC_SU_SE2_STALLED_SC',
152: 'PERF_PAPC_SU_SE3_STALLED_SC',
153: 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT',
154: 'PERF_SMALL_PRIM_CULL_PRIM_1X1',
155: 'PERF_SMALL_PRIM_CULL_PRIM_2X1',
156: 'PERF_SMALL_PRIM_CULL_PRIM_1X2',
157: 'PERF_SMALL_PRIM_CULL_PRIM_2X2',
158: 'PERF_SMALL_PRIM_CULL_PRIM_3X1',
159: 'PERF_SMALL_PRIM_CULL_PRIM_1X3',
160: 'PERF_SMALL_PRIM_CULL_PRIM_3X2',
161: 'PERF_SMALL_PRIM_CULL_PRIM_2X3',
162: 'PERF_SMALL_PRIM_CULL_PRIM_NX1',
163: 'PERF_SMALL_PRIM_CULL_PRIM_1XN',
164: 'PERF_SMALL_PRIM_CULL_PRIM_NX2',
165: 'PERF_SMALL_PRIM_CULL_PRIM_2XN',
169: 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT',
170: 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT',
171: 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT',
172: 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT',
173: 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT',
174: 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT',
175: 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT',
176: 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT',
177: 'PERF_PA_VERTEX_FIFO_FULL',
178: 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL',
179: 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL',
183: 'PERF_ENGG_CSB_MACHINE_IS_STARVED',
184: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY',
185: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI',
186: 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL',
188: 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL',
189: 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT',
190: 'PERF_ENGG_CSB_PRIM_COUNT_EQ0',
191: 'PERF_ENGG_CSB_NULL_SUBGROUP',
192: 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP',
193: 'PERF_ENGG_CSB_GE_MEMORY_FULL',
194: 'PERF_ENGG_CSB_GE_MEMORY_EMPTY',
195: 'PERF_ENGG_CSB_SPI_MEMORY_FULL',
196: 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY',
224: 'PERF_ENGG_INDEX_REQ_NULL_REQUEST',
225: 'PERF_ENGG_INDEX_RET_0_NEW_VERTS_THIS_PRIM',
226: 'PERF_ENGG_INDEX_RET_1_NEW_VERTS_THIS_PRIM',
227: 'PERF_ENGG_INDEX_RET_2_NEW_VERTS_THIS_PRIM',
228: 'PERF_ENGG_INDEX_RET_3_NEW_VERTS_THIS_PRIM',
229: 'PERF_ENGG_INDEX_REQ_STARVED',
230: 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL',
231: 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL',
232: 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS',
233: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL',
234: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY',
235: 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL',
236: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB',
237: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS',
238: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO',
239: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO',
240: 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT',
241: 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP',
242: 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0',
243: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL',
244: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL',
245: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL',
246: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL',
247: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL',
248: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL',
249: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL',
250: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL',
251: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL',
252: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL',
258: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO',
259: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO',
260: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB',
261: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM',
262: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE',
263: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE',
264: 'PERF_ENGG_POS_REQ_STARVED',
265: 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO',
266: 'PERF_ENGG_BUSY',
267: 'PERF_CLIPSM_CULL_PRIMS_CNT',
268: 'PERF_PH_SEND_1_SC',
269: 'PERF_PH_SEND_2_SC',
270: 'PERF_PH_SEND_3_SC',
271: 'PERF_PH_SEND_4_SC',
272: 'PERF_OUTPUT_PRIM_1_SC',
273: 'PERF_OUTPUT_PRIM_2_SC',
274: 'PERF_OUTPUT_PRIM_3_SC',
275: 'PERF_OUTPUT_PRIM_4_SC',
276: 'PERF_PASX_POS_VECTOR',
277: 'PERF_PASX_MISC_VECTOR',
278: 'PERF_PASX_CCDIST0_VECTOR',
279: 'PERF_PASX_CCDIST1_VECTOR',
280: 'PERF_PASX_STEREO_POS_VECTOR',
281: 'PERF_CLPR_INPUT_SEND',
282: 'PERF_SU_INPUT_SEND',
283: 'PERF_SU_OUTPUT_SEND',
284: 'PERF_PAPC_SU_SE4_PRIM_FILTER_CULL',
285: 'PERF_PAPC_SU_SE5_PRIM_FILTER_CULL',
286: 'PERF_PAPC_SU_SE4_OUTPUT_PRIM',
287: 'PERF_PAPC_SU_SE5_OUTPUT_PRIM',
288: 'PERF_PAPC_SU_SE4_OUTPUT_NULL_PRIM',
289: 'PERF_PAPC_SU_SE5_OUTPUT_NULL_PRIM',
290: 'PERF_PAPC_SU_SE4_STALLED_SC',
291: 'PERF_PAPC_SU_SE5_STALLED_SC',
292: 'PERF_ENGG_INDEX_RET0_NEW_VERTS',
293: 'PERF_ENGG_INDEX_RET1_NEW_VERTS',
294: 'PERF_ENGG_INDEX_RET2_NEW_VERTS',
295: 'PERF_ENGG_INDEX_RET3_NEW_VERTS',
296: 'PERF_ENGG_INDEX_RET4_NEW_VERTS',
297: 'PERF_ENGG_INDEX_RET5_NEW_VERTS',
298: 'PERF_ENGG_INDEX_RET6_NEW_VERTS',
299: 'PERF_ENGG_INDEX_RET7_NEW_VERTS',
300: 'PERF_ENGG_INDEX_RET8_NEW_VERTS',
301: 'PERF_ENGG_INDEX_RET9_NEW_VERTS',
302: 'PERF_ENGG_INDEX_RET10_NEW_VERTS',
303: 'PERF_ENGG_INDEX_RET11_NEW_VERTS',
304: 'PERF_ENGG_INDEX_RET12_NEW_VERTS',
305: 'PERF_PH_SEND_5_SC',
306: 'PERF_PH_SEND_6_SC',
307: 'PERF_OUTPUT_PRIM_5_SC',
308: 'PERF_OUTPUT_PRIM_6_SC',
309: 'PERF_CLPR_BACK_PRIM',
310: 'PERF_PA_BUSY',
}
PERF_PAPC_PASX_REQ = 0
PERF_PAPC_PASX_VTX_KILL_DISCARD = 6
PERF_PAPC_PASX_VTX_NAN_DISCARD = 7
PERF_CLPR_INPUT_PRIM = 8
PERF_CLPR_INPUT_NULL_PRIM = 9
PERF_CLPR_INPUT_EVENT = 10
PERF_CLPR_INPUT_FIRST_OF_SUBGROUP = 11
PERF_CLPR_INPUT_END_OF_PACKET = 12
PERF_CLPR_INPUT_EXTENDED_EVENT = 13
PERF_PAPC_CLPR_CULL_PRIM = 14
PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15
PERF_PAPC_CLPR_VV_CULL_PRIM = 16
PERF_PAPC_CLPR_UCP_CULL_PRIM = 17
PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18
PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19
PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20
PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21
PERF_PAPC_CLPR_VV_CLIP_PRIM = 22
PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23
PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24
PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25
PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26
PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27
PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28
PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29
PERF_CLPR_CLIP_PLANE_CNT_9_PLUS = 30
PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31
PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32
PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33
PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34
PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35
PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36
PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38
PERF_PAPC_CLSM_NULL_PRIM = 39
PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40
PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41
PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42
PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43
PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44
PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45
PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46
PERF_PAPC_CLSM_OUT_PRIM_CNT_9_PLUS = 47
PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48
PERF_PAPC_SU_INPUT_PRIM = 49
PERF_PAPC_SU_INPUT_CLIP_PRIM = 50
PERF_PAPC_SU_INPUT_NULL_PRIM = 51
PERF_PAPC_SU_INPUT_PRIM_DUAL = 52
PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53
PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54
PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55
PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56
PERF_PAPC_SU_POLYMODE_FACE_CULL = 57
PERF_PAPC_SU_POLYMODE_BACK_CULL = 58
PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59
PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60
PERF_PAPC_SU_OUTPUT_PRIM = 61
PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62
PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63
PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64
PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65
PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66
PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67
PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68
PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69
PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70
PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71
PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72
PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73
PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74
PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75
PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76
PERF_PAPC_PASX_REQ_IDLE = 77
PERF_PAPC_PASX_REQ_BUSY = 78
PERF_PAPC_PASX_REQ_STALLED = 79
PERF_PAPC_PASX_REC_IDLE = 80
PERF_PAPC_PASX_REC_BUSY = 81
PERF_PAPC_PASX_REC_STARVED_SX = 82
PERF_PAPC_PASX_REC_STALLED = 83
PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84
PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85
PERF_PAPC_CCGSM_IDLE = 86
PERF_PAPC_CCGSM_BUSY = 87
PERF_PAPC_CCGSM_STALLED = 88
PERF_PAPC_CLPRIM_IDLE = 89
PERF_PAPC_CLPRIM_BUSY = 90
PERF_PAPC_CLPRIM_STALLED = 91
PERF_PAPC_CLPRIM_STARVED_CCGSM = 92
PERF_PAPC_CLIPSM_IDLE = 93
PERF_PAPC_CLIPSM_BUSY = 94
PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95
PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96
PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97
PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98
PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99
PERF_PAPC_CLIPGA_IDLE = 100
PERF_PAPC_CLIPGA_BUSY = 101
PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102
PERF_PAPC_CLIPGA_STALLED = 103
PERF_PAPC_CLIP_IDLE = 104
PERF_PAPC_CLIP_BUSY = 105
PERF_PAPC_SU_IDLE = 106
PERF_PAPC_SU_BUSY = 107
PERF_PAPC_SU_STARVED_CLIP = 108
PERF_PAPC_SU_STALLED_SC = 109
PERF_PAPC_CL_DYN_SCLK_VLD = 110
PERF_PAPC_SU_DYN_SCLK_VLD = 111
PERF_PAPC_PA_REG_SCLK_VLD = 112
PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120
PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121
PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123
PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124
PERF_PAPC_SU_ALL_OUTPUT_PRIM = 125
PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126
PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127
PERF_PAPC_SU_ALL_OUTPUT_NULL_PRIM = 128
PERF_PAPC_SU_SE0_STALLED_SC = 131
PERF_PAPC_SU_SE1_STALLED_SC = 132
PERF_PAPC_SU_ALL_STALLED_SC = 133
PERF_PAPC_CLSM_CLIPPING_PRIM = 134
PERF_PAPC_SU_CULLED_PRIM = 135
PERF_PAPC_SU_OUTPUT_EOPG = 136
PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137
PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138
PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139
PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140
PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141
PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142
PERF_PAPC_SU_SE2_STALLED_SC = 151
PERF_PAPC_SU_SE3_STALLED_SC = 152
PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 153
PERF_SMALL_PRIM_CULL_PRIM_1X1 = 154
PERF_SMALL_PRIM_CULL_PRIM_2X1 = 155
PERF_SMALL_PRIM_CULL_PRIM_1X2 = 156
PERF_SMALL_PRIM_CULL_PRIM_2X2 = 157
PERF_SMALL_PRIM_CULL_PRIM_3X1 = 158
PERF_SMALL_PRIM_CULL_PRIM_1X3 = 159
PERF_SMALL_PRIM_CULL_PRIM_3X2 = 160
PERF_SMALL_PRIM_CULL_PRIM_2X3 = 161
PERF_SMALL_PRIM_CULL_PRIM_NX1 = 162
PERF_SMALL_PRIM_CULL_PRIM_1XN = 163
PERF_SMALL_PRIM_CULL_PRIM_NX2 = 164
PERF_SMALL_PRIM_CULL_PRIM_2XN = 165
PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 169
PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 170
PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 171
PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 172
PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 173
PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 174
PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 175
PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 176
PERF_PA_VERTEX_FIFO_FULL = 177
PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 178
PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 179
PERF_ENGG_CSB_MACHINE_IS_STARVED = 183
PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 184
PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 185
PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 186
PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 188
PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 189
PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 190
PERF_ENGG_CSB_NULL_SUBGROUP = 191
PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 192
PERF_ENGG_CSB_GE_MEMORY_FULL = 193
PERF_ENGG_CSB_GE_MEMORY_EMPTY = 194
PERF_ENGG_CSB_SPI_MEMORY_FULL = 195
PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 196
PERF_ENGG_INDEX_REQ_NULL_REQUEST = 224
PERF_ENGG_INDEX_RET_0_NEW_VERTS_THIS_PRIM = 225
PERF_ENGG_INDEX_RET_1_NEW_VERTS_THIS_PRIM = 226
PERF_ENGG_INDEX_RET_2_NEW_VERTS_THIS_PRIM = 227
PERF_ENGG_INDEX_RET_3_NEW_VERTS_THIS_PRIM = 228
PERF_ENGG_INDEX_REQ_STARVED = 229
PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 230
PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 231
PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 232
PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 233
PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 234
PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 235
PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 236
PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 237
PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 238
PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 239
PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 240
PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 241
PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 242
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 243
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 244
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 245
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 246
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 247
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 248
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 249
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 250
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 251
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 252
PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 258
PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 259
PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 260
PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 261
PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 262
PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 263
PERF_ENGG_POS_REQ_STARVED = 264
PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 265
PERF_ENGG_BUSY = 266
PERF_CLIPSM_CULL_PRIMS_CNT = 267
PERF_PH_SEND_1_SC = 268
PERF_PH_SEND_2_SC = 269
PERF_PH_SEND_3_SC = 270
PERF_PH_SEND_4_SC = 271
PERF_OUTPUT_PRIM_1_SC = 272
PERF_OUTPUT_PRIM_2_SC = 273
PERF_OUTPUT_PRIM_3_SC = 274
PERF_OUTPUT_PRIM_4_SC = 275
PERF_PASX_POS_VECTOR = 276
PERF_PASX_MISC_VECTOR = 277
PERF_PASX_CCDIST0_VECTOR = 278
PERF_PASX_CCDIST1_VECTOR = 279
PERF_PASX_STEREO_POS_VECTOR = 280
PERF_CLPR_INPUT_SEND = 281
PERF_SU_INPUT_SEND = 282
PERF_SU_OUTPUT_SEND = 283
PERF_PAPC_SU_SE4_PRIM_FILTER_CULL = 284
PERF_PAPC_SU_SE5_PRIM_FILTER_CULL = 285
PERF_PAPC_SU_SE4_OUTPUT_PRIM = 286
PERF_PAPC_SU_SE5_OUTPUT_PRIM = 287
PERF_PAPC_SU_SE4_OUTPUT_NULL_PRIM = 288
PERF_PAPC_SU_SE5_OUTPUT_NULL_PRIM = 289
PERF_PAPC_SU_SE4_STALLED_SC = 290
PERF_PAPC_SU_SE5_STALLED_SC = 291
PERF_ENGG_INDEX_RET0_NEW_VERTS = 292
PERF_ENGG_INDEX_RET1_NEW_VERTS = 293
PERF_ENGG_INDEX_RET2_NEW_VERTS = 294
PERF_ENGG_INDEX_RET3_NEW_VERTS = 295
PERF_ENGG_INDEX_RET4_NEW_VERTS = 296
PERF_ENGG_INDEX_RET5_NEW_VERTS = 297
PERF_ENGG_INDEX_RET6_NEW_VERTS = 298
PERF_ENGG_INDEX_RET7_NEW_VERTS = 299
PERF_ENGG_INDEX_RET8_NEW_VERTS = 300
PERF_ENGG_INDEX_RET9_NEW_VERTS = 301
PERF_ENGG_INDEX_RET10_NEW_VERTS = 302
PERF_ENGG_INDEX_RET11_NEW_VERTS = 303
PERF_ENGG_INDEX_RET12_NEW_VERTS = 304
PERF_PH_SEND_5_SC = 305
PERF_PH_SEND_6_SC = 306
PERF_OUTPUT_PRIM_5_SC = 307
PERF_OUTPUT_PRIM_6_SC = 308
PERF_CLPR_BACK_PRIM = 309
PERF_PA_BUSY = 310
SU_PERFCNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'RMIPerfSel'
RMIPerfSel__enumvalues = {
0: 'RMI_PERF_SEL_NONE',
1: 'RMI_PERF_SEL_BUSY',
2: 'RMI_PERF_SEL_REG_CLK_VLD',
3: 'RMI_PERF_SEL_DYN_CLK_CMN_VLD',
4: 'RMI_PERF_SEL_DYN_CLK_RB_VLD',
5: 'RMI_PERF_SEL_DYN_CLK_PERF_VLD',
6: 'RMI_PERF_SEL_PERF_WINDOW',
7: 'RMI_PERF_SEL_EVENT_SEND',
8: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID',
9: 'RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY',
10: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0',
11: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1',
12: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2',
13: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3',
14: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4',
15: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5',
16: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6',
17: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7',
18: 'RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID',
19: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID',
20: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID',
21: 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY',
22: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID',
23: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0',
24: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1',
25: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2',
26: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3',
27: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4',
28: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5',
29: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6',
30: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7',
31: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0',
32: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1',
33: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2',
34: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3',
35: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID',
36: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID',
37: 'RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY',
38: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0',
39: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1',
40: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2',
41: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3',
42: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4',
43: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5',
44: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6',
45: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7',
46: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0',
47: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1',
48: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2',
49: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3',
50: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4',
51: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5',
52: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6',
53: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7',
54: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID',
55: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID',
56: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID',
57: 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY',
58: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID',
59: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0',
60: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1',
61: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2',
62: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3',
63: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4',
64: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5',
65: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6',
66: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7',
67: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0',
68: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1',
69: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2',
70: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3',
71: 'RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX',
72: 'RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY',
73: 'RMI_PERF_SEL_RB_RMI_WR_IDLE',
74: 'RMI_PERF_SEL_RB_RMI_WR_STARVE',
75: 'RMI_PERF_SEL_RB_RMI_WR_STALL',
76: 'RMI_PERF_SEL_RB_RMI_WR_BUSY',
77: 'RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY',
78: 'RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX',
79: 'RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY',
80: 'RMI_PERF_SEL_RB_RMI_RD_IDLE',
81: 'RMI_PERF_SEL_RB_RMI_RD_STARVE',
82: 'RMI_PERF_SEL_RB_RMI_RD_STALL',
83: 'RMI_PERF_SEL_RB_RMI_RD_BUSY',
84: 'RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY',
85: 'RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID',
86: 'RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID',
87: 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID',
88: 'RMI_PERF_SEL_RMI_TC_REQ_BUSY',
89: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0',
90: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1',
91: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2',
92: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3',
93: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4',
94: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5',
95: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6',
96: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7',
97: 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID',
98: 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID',
99: 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID',
100: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0',
101: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1',
102: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2',
103: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3',
104: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4',
105: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5',
106: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6',
107: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7',
108: 'RMI_PERF_SEL_RMI_TC_STALL_RDREQ',
109: 'RMI_PERF_SEL_RMI_TC_STALL_WRREQ',
110: 'RMI_PERF_SEL_RMI_TC_STALL_ALLREQ',
111: 'RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND',
112: 'RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND',
113: 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID',
114: 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID',
115: 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT',
116: 'RMI_PERF_SEL_TCIW_REQ',
117: 'RMI_PERF_SEL_TCIW_BUSY',
118: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR',
119: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR',
120: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB',
121: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB',
122: 'RMI_PERF_SEL_REORDER_FIFO_REQ',
123: 'RMI_PERF_SEL_REORDER_FIFO_BUSY',
124: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID',
125: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0',
126: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1',
127: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2',
128: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3',
129: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4',
130: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5',
131: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6',
132: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7',
133: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_READ_RTS_RTR',
134: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_WRITE_RTS_RTR',
135: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_IN0_RTS_RTR',
136: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_IN1_RTS_RTR',
137: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_CB_RTS_RTR',
138: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_DB_RTS_RTR',
}
RMI_PERF_SEL_NONE = 0
RMI_PERF_SEL_BUSY = 1
RMI_PERF_SEL_REG_CLK_VLD = 2
RMI_PERF_SEL_DYN_CLK_CMN_VLD = 3
RMI_PERF_SEL_DYN_CLK_RB_VLD = 4
RMI_PERF_SEL_DYN_CLK_PERF_VLD = 5
RMI_PERF_SEL_PERF_WINDOW = 6
RMI_PERF_SEL_EVENT_SEND = 7
RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 8
RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY = 9
RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 10
RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 11
RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 12
RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 13
RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 14
RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 15
RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 16
RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 17
RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID = 18
RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 19
RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 20
RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 21
RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 22
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 23
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 24
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 25
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 26
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 27
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 28
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 29
RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 30
RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 31
RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 32
RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 33
RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 34
RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 35
RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 36
RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY = 37
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 38
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 39
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 40
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 41
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 42
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 43
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 44
RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 45
RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 46
RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 47
RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 48
RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 49
RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 50
RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 51
RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 52
RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 53
RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 54
RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 55
RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 56
RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 57
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 58
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 59
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 60
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 61
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 62
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 63
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 64
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 65
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 66
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 67
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 68
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 69
RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 70
RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX = 71
RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY = 72
RMI_PERF_SEL_RB_RMI_WR_IDLE = 73
RMI_PERF_SEL_RB_RMI_WR_STARVE = 74
RMI_PERF_SEL_RB_RMI_WR_STALL = 75
RMI_PERF_SEL_RB_RMI_WR_BUSY = 76
RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY = 77
RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX = 78
RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY = 79
RMI_PERF_SEL_RB_RMI_RD_IDLE = 80
RMI_PERF_SEL_RB_RMI_RD_STARVE = 81
RMI_PERF_SEL_RB_RMI_RD_STALL = 82
RMI_PERF_SEL_RB_RMI_RD_BUSY = 83
RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY = 84
RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID = 85
RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID = 86
RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 87
RMI_PERF_SEL_RMI_TC_REQ_BUSY = 88
RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 89
RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 90
RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 91
RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 92
RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 93
RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 94
RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 95
RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 96
RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 97
RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 98
RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 99
RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 100
RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 101
RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 102
RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 103
RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 104
RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 105
RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 106
RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 107
RMI_PERF_SEL_RMI_TC_STALL_RDREQ = 108
RMI_PERF_SEL_RMI_TC_STALL_WRREQ = 109
RMI_PERF_SEL_RMI_TC_STALL_ALLREQ = 110
RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND = 111
RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND = 112
RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 113
RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 114
RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 115
RMI_PERF_SEL_TCIW_REQ = 116
RMI_PERF_SEL_TCIW_BUSY = 117
RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 118
RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 119
RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 120
RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 121
RMI_PERF_SEL_REORDER_FIFO_REQ = 122
RMI_PERF_SEL_REORDER_FIFO_BUSY = 123
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 124
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 125
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 126
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 127
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 128
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 129
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 130
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 131
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 132
RMI_PERF_SEL_CONSUMER_PROBEGEN_READ_RTS_RTR = 133
RMI_PERF_SEL_CONSUMER_PROBEGEN_WRITE_RTS_RTR = 134
RMI_PERF_SEL_CONSUMER_PROBEGEN_IN0_RTS_RTR = 135
RMI_PERF_SEL_CONSUMER_PROBEGEN_IN1_RTS_RTR = 136
RMI_PERF_SEL_CONSUMER_PROBEGEN_CB_RTS_RTR = 137
RMI_PERF_SEL_CONSUMER_PROBEGEN_DB_RTS_RTR = 138
RMIPerfSel = ctypes.c_uint32 # enum
# values for enumeration 'UTCL1PerfSel'
UTCL1PerfSel__enumvalues = {
0: 'UTCL1_PERF_SEL_NONE',
1: 'UTCL1_PERF_SEL_REQS',
2: 'UTCL1_PERF_SEL_HITS',
3: 'UTCL1_PERF_SEL_MISSES',
4: 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT',
5: 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT',
6: 'UTCL1_PERF_SEL_UTCL2_REQS',
7: 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY',
8: 'UTCL1_PERF_SEL_UTCL2_RET_FAULT',
9: 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS',
10: 'UTCL1_PERF_SEL_STALL_MH_FULL',
11: 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM',
12: 'UTCL1_PERF_SEL_UTCL2_RET_CNT',
13: 'UTCL1_PERF_SEL_RTNS',
14: 'UTCL1_PERF_SEL_XLAT_REQ_BUSY',
15: 'UTCL1_PERF_SEL_RANGE_INVREQS',
16: 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS',
17: 'UTCL1_PERF_SEL_BYPASS_REQS',
18: 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS',
19: 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT',
20: 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT',
21: 'UTCL1_PERF_SEL_CP_INVREQS',
22: 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS',
23: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4K_64K',
24: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_64K_256K',
25: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_256K_512K',
26: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_512K_1M',
27: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_1M_2M',
28: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_2M_4M',
29: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4M_8M',
30: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_8M_16M',
31: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_16M_32M',
32: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_32M_INF',
33: 'UTCL1_PERF_SEL_UTCL2_REQ_SQUASHED_NUM',
34: 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_0',
35: 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_1',
36: 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_2',
37: 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_3',
38: 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_0',
39: 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_1',
40: 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_2',
41: 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_3',
42: 'UTCL1_PERF_SEL_UTCL1_UTCL2_INVACKS',
43: 'UTCL1_PERF_SEL_UTCL0_UTCL1_INVACKS',
44: 'UTCL1_PERF_SEL_HITS_PG_SIZE_1',
45: 'UTCL1_PERF_SEL_HITS_PG_SIZE_2',
46: 'UTCL1_PERF_SEL_HITS_PG_SIZE_3',
47: 'UTCL1_PERF_SEL_HITS_PG_SIZE_4',
48: 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_0',
49: 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_1',
50: 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_2',
51: 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_3',
52: 'UTCL1_PERF_SEL_AVG_INV_LATENCY',
53: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC0',
54: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC1',
55: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC2',
56: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC3',
57: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC0',
58: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC1',
59: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC2',
60: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC3',
61: 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC0',
62: 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC1',
63: 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC2',
64: 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC3',
65: 'UTCL1_PERF_SEL_ALOG_INTERRUPT',
66: 'UTCL1_PERF_SEL_ALOG_INTERRUPT_DROPPED',
67: 'UTCL1_PERF_SEL_ALOG_CACHE_REQ',
68: 'UTCL1_PERF_SEL_ALOG_CACHE_HIT',
69: 'UTCL1_PERF_SEL_ALOG_STALL_PMM_CREDITS',
}
UTCL1_PERF_SEL_NONE = 0
UTCL1_PERF_SEL_REQS = 1
UTCL1_PERF_SEL_HITS = 2
UTCL1_PERF_SEL_MISSES = 3
UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 4
UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 5
UTCL1_PERF_SEL_UTCL2_REQS = 6
UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 7
UTCL1_PERF_SEL_UTCL2_RET_FAULT = 8
UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 9
UTCL1_PERF_SEL_STALL_MH_FULL = 10
UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 11
UTCL1_PERF_SEL_UTCL2_RET_CNT = 12
UTCL1_PERF_SEL_RTNS = 13
UTCL1_PERF_SEL_XLAT_REQ_BUSY = 14
UTCL1_PERF_SEL_RANGE_INVREQS = 15
UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 16
UTCL1_PERF_SEL_BYPASS_REQS = 17
UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 18
UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 19
UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 20
UTCL1_PERF_SEL_CP_INVREQS = 21
UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 22
UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4K_64K = 23
UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_64K_256K = 24
UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_256K_512K = 25
UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_512K_1M = 26
UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_1M_2M = 27
UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_2M_4M = 28
UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4M_8M = 29
UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_8M_16M = 30
UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_16M_32M = 31
UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_32M_INF = 32
UTCL1_PERF_SEL_UTCL2_REQ_SQUASHED_NUM = 33
UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_0 = 34
UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_1 = 35
UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_2 = 36
UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_3 = 37
UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_0 = 38
UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_1 = 39
UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_2 = 40
UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_3 = 41
UTCL1_PERF_SEL_UTCL1_UTCL2_INVACKS = 42
UTCL1_PERF_SEL_UTCL0_UTCL1_INVACKS = 43
UTCL1_PERF_SEL_HITS_PG_SIZE_1 = 44
UTCL1_PERF_SEL_HITS_PG_SIZE_2 = 45
UTCL1_PERF_SEL_HITS_PG_SIZE_3 = 46
UTCL1_PERF_SEL_HITS_PG_SIZE_4 = 47
UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_0 = 48
UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_1 = 49
UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_2 = 50
UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_3 = 51
UTCL1_PERF_SEL_AVG_INV_LATENCY = 52
UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC0 = 53
UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC1 = 54
UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC2 = 55
UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC3 = 56
UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC0 = 57
UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC1 = 58
UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC2 = 59
UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC3 = 60
UTCL1_PERF_SEL_EVICTIONS_NUM_CC0 = 61
UTCL1_PERF_SEL_EVICTIONS_NUM_CC1 = 62
UTCL1_PERF_SEL_EVICTIONS_NUM_CC2 = 63
UTCL1_PERF_SEL_EVICTIONS_NUM_CC3 = 64
UTCL1_PERF_SEL_ALOG_INTERRUPT = 65
UTCL1_PERF_SEL_ALOG_INTERRUPT_DROPPED = 66
UTCL1_PERF_SEL_ALOG_CACHE_REQ = 67
UTCL1_PERF_SEL_ALOG_CACHE_HIT = 68
UTCL1_PERF_SEL_ALOG_STALL_PMM_CREDITS = 69
UTCL1PerfSel = ctypes.c_uint32 # enum
# values for enumeration 'GC_EA_SE_PERFCOUNT_SEL'
GC_EA_SE_PERFCOUNT_SEL__enumvalues = {
0: 'GC_EA_SE_PERF_SEL_ALWAYS_COUNT',
1: 'GC_EA_SE_PERF_SEL_RDRAM_NUM_BANKS_VLD',
2: 'GC_EA_SE_PERF_SEL_RDRAM_REQ_PER_CLIGRP',
3: 'GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP',
4: 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START0',
5: 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END0',
6: 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START1',
7: 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END1',
8: 'GC_EA_SE_PERF_SEL_WDRAM_NUM_BANKS_VLD',
9: 'GC_EA_SE_PERF_SEL_WDRAM_REQ_PER_CLIGRP',
10: 'GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP',
11: 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START0',
12: 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END0',
13: 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START1',
14: 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END1',
15: 'GC_EA_SE_PERF_SEL_RGMI_NUM_BANKS_VLD',
16: 'GC_EA_SE_PERF_SEL_RGMI_REQ_PER_CLIGRP',
17: 'GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR',
18: 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_START0',
19: 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_END0',
20: 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_START1',
21: 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_END1',
22: 'GC_EA_SE_PERF_SEL_WGMI_NUM_BANKS_VLD',
23: 'GC_EA_SE_PERF_SEL_WGMI_REQ_PER_CLIGRP',
24: 'GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP',
25: 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_START0',
26: 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_END0',
27: 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_START1',
28: 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_END1',
29: 'GC_EA_SE_PERF_SEL_RIO_REQ_PER_CLIGRP',
30: 'GC_EA_SE_PERF_SEL_RIO_SIZE_REQ',
31: 'GC_EA_SE_PERF_SEL_RIO_GRP0_SIZE_REQ',
32: 'GC_EA_SE_PERF_SEL_RIO_GRP1_SIZE_REQ',
33: 'GC_EA_SE_PERF_SEL_RIO_GRP2_SIZE_REQ',
34: 'GC_EA_SE_PERF_SEL_RIO_GRP3_SIZE_REQ',
35: 'GC_EA_SE_PERF_SEL_RIO_LATENCY_START0',
36: 'GC_EA_SE_PERF_SEL_RIO_LATENCY_END0',
37: 'GC_EA_SE_PERF_SEL_RIO_LATENCY_START1',
38: 'GC_EA_SE_PERF_SEL_RIO_LATENCY_END1',
39: 'GC_EA_SE_PERF_SEL_WIO_REQ_PER_CLIGRP',
40: 'GC_EA_SE_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP',
41: 'GC_EA_SE_PERF_SEL_WIO_SIZE_REQ',
42: 'GC_EA_SE_PERF_SEL_WIO_GRP0_SIZE_REQ',
43: 'GC_EA_SE_PERF_SEL_WIO_GRP1_SIZE_REQ',
44: 'GC_EA_SE_PERF_SEL_WIO_GRP2_SIZE_REQ',
45: 'GC_EA_SE_PERF_SEL_WIO_GRP3_SIZE_REQ',
46: 'GC_EA_SE_PERF_SEL_WIO_LATENCY_START0',
47: 'GC_EA_SE_PERF_SEL_WIO_LATENCY_END0',
48: 'GC_EA_SE_PERF_SEL_WIO_LATENCY_START1',
49: 'GC_EA_SE_PERF_SEL_WIO_LATENCY_END1',
50: 'GC_EA_SE_PERF_SEL_SARB_REQ_PER_VC',
51: 'GC_EA_SE_PERF_SEL_SARB_DRAM_REQ_PER_VC',
52: 'GC_EA_SE_PERF_SEL_SARB_GMI_REQ_PER_VC',
53: 'GC_EA_SE_PERF_SEL_SARB_IO_REQ_PER_VC',
54: 'GC_EA_SE_PERF_SEL_SARB_SIZE_REQ',
55: 'GC_EA_SE_PERF_SEL_SARB_DRAM_SIZE_REQ',
56: 'GC_EA_SE_PERF_SEL_SARB_GMI_SIZE_REQ',
57: 'GC_EA_SE_PERF_SEL_SARB_IO_SIZE_REQ',
58: 'GC_EA_SE_PERF_SEL_SARB_LATENCY_START0',
59: 'GC_EA_SE_PERF_SEL_SARB_LATENCY_END0',
60: 'GC_EA_SE_PERF_SEL_SARB_LATENCY_START1',
61: 'GC_EA_SE_PERF_SEL_SARB_LATENCY_END1',
62: 'GC_EA_SE_PERF_SEL_SARB_BUSY',
63: 'GC_EA_SE_PERF_SEL_SARB_STALLED',
64: 'GC_EA_SE_PERF_SEL_SARB_STARVING',
65: 'GC_EA_SE_PERF_SEL_SARB_IDLE',
66: 'GC_EA_SE_PERF_SEL_RRET_VLD',
67: 'GC_EA_SE_PERF_SEL_WRET_VLD',
68: 'GC_EA_SE_PERF_SEL_PRB_REQ',
69: 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_EVICT',
70: 'GC_EA_SE_PERF_SEL_MAM_ARAM_REQ_VLD',
71: 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT',
72: 'GC_EA_SE_PERF_SEL_MAM_NUM_DQRY',
73: 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT',
74: 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED',
75: 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_COMPLETED',
76: 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_ONGOING',
77: 'GC_EA_SE_PERF_SEL_RDRAM_SIZE_REQ',
78: 'GC_EA_SE_PERF_SEL_WDRAM_SIZE_REQ',
79: 'GC_EA_SE_PERF_SEL_RGMI_SIZE_REQ',
80: 'GC_EA_SE_PERF_SEL_WGMI_SIZE_REQ',
81: 'GC_EA_SE_PERF_SEL_SARB_DRAM_RW_TURN_AROUND',
82: 'GC_EA_SE_PERF_SEL_SARB_GMI_RW_TURN_AROUND',
83: 'GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH',
84: 'GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH',
85: 'GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH',
86: 'GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH',
87: 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_EVICT',
88: 'GC_EA_SE_PERF_SEL_MAM_DBIT_REQ_VLD',
89: 'GC_EA_SE_PERF_SEL_SARB_COHERENT_SIZE_REQ',
90: 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT_EVICT',
91: 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_LRU_EVICT',
92: 'GC_EA_SE_PERF_SEL_MAM_FLUSH_REQ',
93: 'GC_EA_SE_PERF_SEL_MAM_FLUSH_RESP',
94: 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT_EVICT',
95: 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_LRU_EVICT',
96: 'GC_EA_SE_PERF_SEL_MAM_DQRY_ONGOING',
97: 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT',
}
GC_EA_SE_PERF_SEL_ALWAYS_COUNT = 0
GC_EA_SE_PERF_SEL_RDRAM_NUM_BANKS_VLD = 1
GC_EA_SE_PERF_SEL_RDRAM_REQ_PER_CLIGRP = 2
GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP = 3
GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START0 = 4
GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END0 = 5
GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START1 = 6
GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END1 = 7
GC_EA_SE_PERF_SEL_WDRAM_NUM_BANKS_VLD = 8
GC_EA_SE_PERF_SEL_WDRAM_REQ_PER_CLIGRP = 9
GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP = 10
GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START0 = 11
GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END0 = 12
GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START1 = 13
GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END1 = 14
GC_EA_SE_PERF_SEL_RGMI_NUM_BANKS_VLD = 15
GC_EA_SE_PERF_SEL_RGMI_REQ_PER_CLIGRP = 16
GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR = 17
GC_EA_SE_PERF_SEL_RGMI_LATENCY_START0 = 18
GC_EA_SE_PERF_SEL_RGMI_LATENCY_END0 = 19
GC_EA_SE_PERF_SEL_RGMI_LATENCY_START1 = 20
GC_EA_SE_PERF_SEL_RGMI_LATENCY_END1 = 21
GC_EA_SE_PERF_SEL_WGMI_NUM_BANKS_VLD = 22
GC_EA_SE_PERF_SEL_WGMI_REQ_PER_CLIGRP = 23
GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP = 24
GC_EA_SE_PERF_SEL_WGMI_LATENCY_START0 = 25
GC_EA_SE_PERF_SEL_WGMI_LATENCY_END0 = 26
GC_EA_SE_PERF_SEL_WGMI_LATENCY_START1 = 27
GC_EA_SE_PERF_SEL_WGMI_LATENCY_END1 = 28
GC_EA_SE_PERF_SEL_RIO_REQ_PER_CLIGRP = 29
GC_EA_SE_PERF_SEL_RIO_SIZE_REQ = 30
GC_EA_SE_PERF_SEL_RIO_GRP0_SIZE_REQ = 31
GC_EA_SE_PERF_SEL_RIO_GRP1_SIZE_REQ = 32
GC_EA_SE_PERF_SEL_RIO_GRP2_SIZE_REQ = 33
GC_EA_SE_PERF_SEL_RIO_GRP3_SIZE_REQ = 34
GC_EA_SE_PERF_SEL_RIO_LATENCY_START0 = 35
GC_EA_SE_PERF_SEL_RIO_LATENCY_END0 = 36
GC_EA_SE_PERF_SEL_RIO_LATENCY_START1 = 37
GC_EA_SE_PERF_SEL_RIO_LATENCY_END1 = 38
GC_EA_SE_PERF_SEL_WIO_REQ_PER_CLIGRP = 39
GC_EA_SE_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP = 40
GC_EA_SE_PERF_SEL_WIO_SIZE_REQ = 41
GC_EA_SE_PERF_SEL_WIO_GRP0_SIZE_REQ = 42
GC_EA_SE_PERF_SEL_WIO_GRP1_SIZE_REQ = 43
GC_EA_SE_PERF_SEL_WIO_GRP2_SIZE_REQ = 44
GC_EA_SE_PERF_SEL_WIO_GRP3_SIZE_REQ = 45
GC_EA_SE_PERF_SEL_WIO_LATENCY_START0 = 46
GC_EA_SE_PERF_SEL_WIO_LATENCY_END0 = 47
GC_EA_SE_PERF_SEL_WIO_LATENCY_START1 = 48
GC_EA_SE_PERF_SEL_WIO_LATENCY_END1 = 49
GC_EA_SE_PERF_SEL_SARB_REQ_PER_VC = 50
GC_EA_SE_PERF_SEL_SARB_DRAM_REQ_PER_VC = 51
GC_EA_SE_PERF_SEL_SARB_GMI_REQ_PER_VC = 52
GC_EA_SE_PERF_SEL_SARB_IO_REQ_PER_VC = 53
GC_EA_SE_PERF_SEL_SARB_SIZE_REQ = 54
GC_EA_SE_PERF_SEL_SARB_DRAM_SIZE_REQ = 55
GC_EA_SE_PERF_SEL_SARB_GMI_SIZE_REQ = 56
GC_EA_SE_PERF_SEL_SARB_IO_SIZE_REQ = 57
GC_EA_SE_PERF_SEL_SARB_LATENCY_START0 = 58
GC_EA_SE_PERF_SEL_SARB_LATENCY_END0 = 59
GC_EA_SE_PERF_SEL_SARB_LATENCY_START1 = 60
GC_EA_SE_PERF_SEL_SARB_LATENCY_END1 = 61
GC_EA_SE_PERF_SEL_SARB_BUSY = 62
GC_EA_SE_PERF_SEL_SARB_STALLED = 63
GC_EA_SE_PERF_SEL_SARB_STARVING = 64
GC_EA_SE_PERF_SEL_SARB_IDLE = 65
GC_EA_SE_PERF_SEL_RRET_VLD = 66
GC_EA_SE_PERF_SEL_WRET_VLD = 67
GC_EA_SE_PERF_SEL_PRB_REQ = 68
GC_EA_SE_PERF_SEL_MAM_ARAM_FA_EVICT = 69
GC_EA_SE_PERF_SEL_MAM_ARAM_REQ_VLD = 70
GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT = 71
GC_EA_SE_PERF_SEL_MAM_NUM_DQRY = 72
GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT = 73
GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED = 74
GC_EA_SE_PERF_SEL_MAM_AFLUSH_COMPLETED = 75
GC_EA_SE_PERF_SEL_MAM_AFLUSH_ONGOING = 76
GC_EA_SE_PERF_SEL_RDRAM_SIZE_REQ = 77
GC_EA_SE_PERF_SEL_WDRAM_SIZE_REQ = 78
GC_EA_SE_PERF_SEL_RGMI_SIZE_REQ = 79
GC_EA_SE_PERF_SEL_WGMI_SIZE_REQ = 80
GC_EA_SE_PERF_SEL_SARB_DRAM_RW_TURN_AROUND = 81
GC_EA_SE_PERF_SEL_SARB_GMI_RW_TURN_AROUND = 82
GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 83
GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 84
GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 85
GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 86
GC_EA_SE_PERF_SEL_MAM_DBIT_FA_EVICT = 87
GC_EA_SE_PERF_SEL_MAM_DBIT_REQ_VLD = 88
GC_EA_SE_PERF_SEL_SARB_COHERENT_SIZE_REQ = 89
GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT_EVICT = 90
GC_EA_SE_PERF_SEL_MAM_ARAM_FA_LRU_EVICT = 91
GC_EA_SE_PERF_SEL_MAM_FLUSH_REQ = 92
GC_EA_SE_PERF_SEL_MAM_FLUSH_RESP = 93
GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT_EVICT = 94
GC_EA_SE_PERF_SEL_MAM_DBIT_FA_LRU_EVICT = 95
GC_EA_SE_PERF_SEL_MAM_DQRY_ONGOING = 96
GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT = 97
GC_EA_SE_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'LSDMA_PERF_SEL'
LSDMA_PERF_SEL__enumvalues = {
0: 'LSDMA_PERF_SEL_CYCLE',
1: 'LSDMA_PERF_SEL_IDLE',
2: 'LSDMA_PERF_SEL_REG_IDLE',
3: 'LSDMA_PERF_SEL_RB_EMPTY',
4: 'LSDMA_PERF_SEL_RB_FULL',
5: 'LSDMA_PERF_SEL_RB_WPTR_WRAP',
6: 'LSDMA_PERF_SEL_RB_RPTR_WRAP',
7: 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ',
8: 'LSDMA_PERF_SEL_RB_RPTR_WB',
9: 'LSDMA_PERF_SEL_RB_CMD_IDLE',
10: 'LSDMA_PERF_SEL_RB_CMD_FULL',
11: 'LSDMA_PERF_SEL_IB_CMD_IDLE',
12: 'LSDMA_PERF_SEL_IB_CMD_FULL',
13: 'LSDMA_PERF_SEL_EX_IDLE',
14: 'LSDMA_PERF_SEL_SRBM_REG_SEND',
15: 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
16: 'LSDMA_PERF_SEL_MC_WR_IDLE',
17: 'LSDMA_PERF_SEL_MC_WR_COUNT',
18: 'LSDMA_PERF_SEL_MC_RD_IDLE',
19: 'LSDMA_PERF_SEL_MC_RD_COUNT',
20: 'LSDMA_PERF_SEL_MC_RD_RET_STALL',
21: 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE',
24: 'LSDMA_PERF_SEL_SEM_IDLE',
25: 'LSDMA_PERF_SEL_SEM_REQ_STALL',
26: 'LSDMA_PERF_SEL_SEM_REQ_COUNT',
27: 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE',
28: 'LSDMA_PERF_SEL_SEM_RESP_FAIL',
29: 'LSDMA_PERF_SEL_SEM_RESP_PASS',
30: 'LSDMA_PERF_SEL_INT_IDLE',
31: 'LSDMA_PERF_SEL_INT_REQ_STALL',
32: 'LSDMA_PERF_SEL_INT_REQ_COUNT',
33: 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED',
34: 'LSDMA_PERF_SEL_INT_RESP_RETRY',
35: 'LSDMA_PERF_SEL_NUM_PACKET',
37: 'LSDMA_PERF_SEL_CE_WREQ_IDLE',
38: 'LSDMA_PERF_SEL_CE_WR_IDLE',
39: 'LSDMA_PERF_SEL_CE_SPLIT_IDLE',
40: 'LSDMA_PERF_SEL_CE_RREQ_IDLE',
41: 'LSDMA_PERF_SEL_CE_OUT_IDLE',
42: 'LSDMA_PERF_SEL_CE_IN_IDLE',
43: 'LSDMA_PERF_SEL_CE_DST_IDLE',
46: 'LSDMA_PERF_SEL_CE_AFIFO_FULL',
47: 'LSDMA_PERF_SEL_DUMMY_0',
48: 'LSDMA_PERF_SEL_DUMMY_1',
49: 'LSDMA_PERF_SEL_CE_INFO_FULL',
50: 'LSDMA_PERF_SEL_CE_INFO1_FULL',
51: 'LSDMA_PERF_SEL_CE_RD_STALL',
52: 'LSDMA_PERF_SEL_CE_WR_STALL',
53: 'LSDMA_PERF_SEL_GFX_SELECT',
54: 'LSDMA_PERF_SEL_RLC0_SELECT',
55: 'LSDMA_PERF_SEL_RLC1_SELECT',
56: 'LSDMA_PERF_SEL_PAGE_SELECT',
57: 'LSDMA_PERF_SEL_CTX_CHANGE',
58: 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED',
59: 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION',
60: 'LSDMA_PERF_SEL_DOORBELL',
61: 'LSDMA_PERF_SEL_RD_BA_RTR',
62: 'LSDMA_PERF_SEL_WR_BA_RTR',
63: 'LSDMA_PERF_SEL_F32_L1_WR_VLD',
64: 'LSDMA_PERF_SEL_CE_L1_WR_VLD',
65: 'LSDMA_PERF_SEL_CE_L1_STALL',
66: 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH',
67: 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH',
68: 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH',
69: 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH',
70: 'LSDMA_PERF_SEL_ATCL2_RET_XNACK',
71: 'LSDMA_PERF_SEL_ATCL2_RET_ACK',
72: 'LSDMA_PERF_SEL_ATCL2_FREE',
73: 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND',
74: 'LSDMA_PERF_SEL_DMA_L1_WR_SEND',
75: 'LSDMA_PERF_SEL_DMA_L1_RD_SEND',
76: 'LSDMA_PERF_SEL_DMA_MC_WR_SEND',
77: 'LSDMA_PERF_SEL_DMA_MC_RD_SEND',
78: 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE',
79: 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE',
80: 'LSDMA_PERF_SEL_L1_WRL2_IDLE',
81: 'LSDMA_PERF_SEL_L1_RDL2_IDLE',
82: 'LSDMA_PERF_SEL_L1_WRMC_IDLE',
83: 'LSDMA_PERF_SEL_L1_RDMC_IDLE',
84: 'LSDMA_PERF_SEL_L1_WR_INV_IDLE',
85: 'LSDMA_PERF_SEL_L1_RD_INV_IDLE',
86: 'LSDMA_PERF_SEL_L1_WR_INV_EN',
87: 'LSDMA_PERF_SEL_L1_RD_INV_EN',
88: 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR',
89: 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR',
90: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR',
91: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD',
92: 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT',
93: 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT',
94: 'LSDMA_PERF_SEL_L1_INV_MIDDLE',
95: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ',
96: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET',
97: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ',
98: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET',
99: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ',
100: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET',
101: 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ',
102: 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET',
103: 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ',
104: 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET',
105: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ',
106: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET',
107: 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ',
108: 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET',
109: 'LSDMA_PERF_SEL_CMD_OP_MATCH',
110: 'LSDMA_PERF_SEL_CMD_OP_START',
111: 'LSDMA_PERF_SEL_CMD_OP_END',
112: 'LSDMA_PERF_SEL_CE_BUSY',
113: 'LSDMA_PERF_SEL_CE_BUSY_START',
114: 'LSDMA_PERF_SEL_CE_BUSY_END',
115: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER',
116: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START',
117: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END',
118: 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND',
119: 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID',
120: 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND',
121: 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID',
122: 'LSDMA_PERF_SEL_DRAM_ECC',
123: 'LSDMA_PERF_SEL_NACK_GEN_ERR',
}
LSDMA_PERF_SEL_CYCLE = 0
LSDMA_PERF_SEL_IDLE = 1
LSDMA_PERF_SEL_REG_IDLE = 2
LSDMA_PERF_SEL_RB_EMPTY = 3
LSDMA_PERF_SEL_RB_FULL = 4
LSDMA_PERF_SEL_RB_WPTR_WRAP = 5
LSDMA_PERF_SEL_RB_RPTR_WRAP = 6
LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 7
LSDMA_PERF_SEL_RB_RPTR_WB = 8
LSDMA_PERF_SEL_RB_CMD_IDLE = 9
LSDMA_PERF_SEL_RB_CMD_FULL = 10
LSDMA_PERF_SEL_IB_CMD_IDLE = 11
LSDMA_PERF_SEL_IB_CMD_FULL = 12
LSDMA_PERF_SEL_EX_IDLE = 13
LSDMA_PERF_SEL_SRBM_REG_SEND = 14
LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15
LSDMA_PERF_SEL_MC_WR_IDLE = 16
LSDMA_PERF_SEL_MC_WR_COUNT = 17
LSDMA_PERF_SEL_MC_RD_IDLE = 18
LSDMA_PERF_SEL_MC_RD_COUNT = 19
LSDMA_PERF_SEL_MC_RD_RET_STALL = 20
LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21
LSDMA_PERF_SEL_SEM_IDLE = 24
LSDMA_PERF_SEL_SEM_REQ_STALL = 25
LSDMA_PERF_SEL_SEM_REQ_COUNT = 26
LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27
LSDMA_PERF_SEL_SEM_RESP_FAIL = 28
LSDMA_PERF_SEL_SEM_RESP_PASS = 29
LSDMA_PERF_SEL_INT_IDLE = 30
LSDMA_PERF_SEL_INT_REQ_STALL = 31
LSDMA_PERF_SEL_INT_REQ_COUNT = 32
LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 33
LSDMA_PERF_SEL_INT_RESP_RETRY = 34
LSDMA_PERF_SEL_NUM_PACKET = 35
LSDMA_PERF_SEL_CE_WREQ_IDLE = 37
LSDMA_PERF_SEL_CE_WR_IDLE = 38
LSDMA_PERF_SEL_CE_SPLIT_IDLE = 39
LSDMA_PERF_SEL_CE_RREQ_IDLE = 40
LSDMA_PERF_SEL_CE_OUT_IDLE = 41
LSDMA_PERF_SEL_CE_IN_IDLE = 42
LSDMA_PERF_SEL_CE_DST_IDLE = 43
LSDMA_PERF_SEL_CE_AFIFO_FULL = 46
LSDMA_PERF_SEL_DUMMY_0 = 47
LSDMA_PERF_SEL_DUMMY_1 = 48
LSDMA_PERF_SEL_CE_INFO_FULL = 49
LSDMA_PERF_SEL_CE_INFO1_FULL = 50
LSDMA_PERF_SEL_CE_RD_STALL = 51
LSDMA_PERF_SEL_CE_WR_STALL = 52
LSDMA_PERF_SEL_GFX_SELECT = 53
LSDMA_PERF_SEL_RLC0_SELECT = 54
LSDMA_PERF_SEL_RLC1_SELECT = 55
LSDMA_PERF_SEL_PAGE_SELECT = 56
LSDMA_PERF_SEL_CTX_CHANGE = 57
LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58
LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59
LSDMA_PERF_SEL_DOORBELL = 60
LSDMA_PERF_SEL_RD_BA_RTR = 61
LSDMA_PERF_SEL_WR_BA_RTR = 62
LSDMA_PERF_SEL_F32_L1_WR_VLD = 63
LSDMA_PERF_SEL_CE_L1_WR_VLD = 64
LSDMA_PERF_SEL_CE_L1_STALL = 65
LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 66
LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 67
LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 68
LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 69
LSDMA_PERF_SEL_ATCL2_RET_XNACK = 70
LSDMA_PERF_SEL_ATCL2_RET_ACK = 71
LSDMA_PERF_SEL_ATCL2_FREE = 72
LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 73
LSDMA_PERF_SEL_DMA_L1_WR_SEND = 74
LSDMA_PERF_SEL_DMA_L1_RD_SEND = 75
LSDMA_PERF_SEL_DMA_MC_WR_SEND = 76
LSDMA_PERF_SEL_DMA_MC_RD_SEND = 77
LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 78
LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 79
LSDMA_PERF_SEL_L1_WRL2_IDLE = 80
LSDMA_PERF_SEL_L1_RDL2_IDLE = 81
LSDMA_PERF_SEL_L1_WRMC_IDLE = 82
LSDMA_PERF_SEL_L1_RDMC_IDLE = 83
LSDMA_PERF_SEL_L1_WR_INV_IDLE = 84
LSDMA_PERF_SEL_L1_RD_INV_IDLE = 85
LSDMA_PERF_SEL_L1_WR_INV_EN = 86
LSDMA_PERF_SEL_L1_RD_INV_EN = 87
LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 88
LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 89
LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 90
LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 91
LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 92
LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 93
LSDMA_PERF_SEL_L1_INV_MIDDLE = 94
LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 95
LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 96
LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 97
LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 98
LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 99
LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 100
LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 101
LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 102
LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 103
LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 104
LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 105
LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 106
LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 107
LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 108
LSDMA_PERF_SEL_CMD_OP_MATCH = 109
LSDMA_PERF_SEL_CMD_OP_START = 110
LSDMA_PERF_SEL_CMD_OP_END = 111
LSDMA_PERF_SEL_CE_BUSY = 112
LSDMA_PERF_SEL_CE_BUSY_START = 113
LSDMA_PERF_SEL_CE_BUSY_END = 114
LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 115
LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 116
LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 117
LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 118
LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 119
LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 120
LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 121
LSDMA_PERF_SEL_DRAM_ECC = 122
LSDMA_PERF_SEL_NACK_GEN_ERR = 123
LSDMA_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'EFC_SURFACE_PIXEL_FORMAT'
EFC_SURFACE_PIXEL_FORMAT__enumvalues = {
1: 'EFC_ARGB1555',
2: 'EFC_RGBA5551',
3: 'EFC_RGB565',
4: 'EFC_BGR565',
5: 'EFC_ARGB4444',
6: 'EFC_RGBA4444',
8: 'EFC_ARGB8888',
9: 'EFC_RGBA8888',
10: 'EFC_ARGB2101010',
11: 'EFC_RGBA1010102',
12: 'EFC_AYCrCb8888',
13: 'EFC_YCrCbA8888',
14: 'EFC_ACrYCb8888',
15: 'EFC_CrYCbA8888',
16: 'EFC_ARGB16161616_10MSB',
17: 'EFC_RGBA16161616_10MSB',
18: 'EFC_ARGB16161616_10LSB',
19: 'EFC_RGBA16161616_10LSB',
20: 'EFC_ARGB16161616_12MSB',
21: 'EFC_RGBA16161616_12MSB',
22: 'EFC_ARGB16161616_12LSB',
23: 'EFC_RGBA16161616_12LSB',
24: 'EFC_ARGB16161616_FLOAT',
25: 'EFC_RGBA16161616_FLOAT',
26: 'EFC_ARGB16161616_UNORM',
27: 'EFC_RGBA16161616_UNORM',
28: 'EFC_ARGB16161616_SNORM',
29: 'EFC_RGBA16161616_SNORM',
32: 'EFC_AYCrCb16161616_10MSB',
33: 'EFC_AYCrCb16161616_10LSB',
34: 'EFC_YCrCbA16161616_10MSB',
35: 'EFC_YCrCbA16161616_10LSB',
36: 'EFC_ACrYCb16161616_10MSB',
37: 'EFC_ACrYCb16161616_10LSB',
38: 'EFC_CrYCbA16161616_10MSB',
39: 'EFC_CrYCbA16161616_10LSB',
40: 'EFC_AYCrCb16161616_12MSB',
41: 'EFC_AYCrCb16161616_12LSB',
42: 'EFC_YCrCbA16161616_12MSB',
43: 'EFC_YCrCbA16161616_12LSB',
44: 'EFC_ACrYCb16161616_12MSB',
45: 'EFC_ACrYCb16161616_12LSB',
46: 'EFC_CrYCbA16161616_12MSB',
47: 'EFC_CrYCbA16161616_12LSB',
64: 'EFC_Y8_CrCb88_420_PLANAR',
65: 'EFC_Y8_CbCr88_420_PLANAR',
66: 'EFC_Y10_CrCb1010_420_PLANAR',
67: 'EFC_Y10_CbCr1010_420_PLANAR',
68: 'EFC_Y12_CrCb1212_420_PLANAR',
69: 'EFC_Y12_CbCr1212_420_PLANAR',
72: 'EFC_YCrYCb8888_422_PACKED',
73: 'EFC_YCbYCr8888_422_PACKED',
74: 'EFC_CrYCbY8888_422_PACKED',
75: 'EFC_CbYCrY8888_422_PACKED',
76: 'EFC_YCrYCb10101010_422_PACKED',
77: 'EFC_YCbYCr10101010_422_PACKED',
78: 'EFC_CrYCbY10101010_422_PACKED',
79: 'EFC_CbYCrY10101010_422_PACKED',
80: 'EFC_YCrYCb12121212_422_PACKED',
81: 'EFC_YCbYCr12121212_422_PACKED',
82: 'EFC_CrYCbY12121212_422_PACKED',
83: 'EFC_CbYCrY12121212_422_PACKED',
112: 'EFC_RGB111110_FIX',
113: 'EFC_BGR101111_FIX',
114: 'EFC_ACrYCb2101010',
115: 'EFC_CrYCbA1010102',
118: 'EFC_RGB111110_FLOAT',
119: 'EFC_BGR101111_FLOAT',
120: 'EFC_MONO_8',
121: 'EFC_MONO_10MSB',
122: 'EFC_MONO_10LSB',
123: 'EFC_MONO_12MSB',
124: 'EFC_MONO_12LSB',
125: 'EFC_MONO_16',
}
EFC_ARGB1555 = 1
EFC_RGBA5551 = 2
EFC_RGB565 = 3
EFC_BGR565 = 4
EFC_ARGB4444 = 5
EFC_RGBA4444 = 6
EFC_ARGB8888 = 8
EFC_RGBA8888 = 9
EFC_ARGB2101010 = 10
EFC_RGBA1010102 = 11
EFC_AYCrCb8888 = 12
EFC_YCrCbA8888 = 13
EFC_ACrYCb8888 = 14
EFC_CrYCbA8888 = 15
EFC_ARGB16161616_10MSB = 16
EFC_RGBA16161616_10MSB = 17
EFC_ARGB16161616_10LSB = 18
EFC_RGBA16161616_10LSB = 19
EFC_ARGB16161616_12MSB = 20
EFC_RGBA16161616_12MSB = 21
EFC_ARGB16161616_12LSB = 22
EFC_RGBA16161616_12LSB = 23
EFC_ARGB16161616_FLOAT = 24
EFC_RGBA16161616_FLOAT = 25
EFC_ARGB16161616_UNORM = 26
EFC_RGBA16161616_UNORM = 27
EFC_ARGB16161616_SNORM = 28
EFC_RGBA16161616_SNORM = 29
EFC_AYCrCb16161616_10MSB = 32
EFC_AYCrCb16161616_10LSB = 33
EFC_YCrCbA16161616_10MSB = 34
EFC_YCrCbA16161616_10LSB = 35
EFC_ACrYCb16161616_10MSB = 36
EFC_ACrYCb16161616_10LSB = 37
EFC_CrYCbA16161616_10MSB = 38
EFC_CrYCbA16161616_10LSB = 39
EFC_AYCrCb16161616_12MSB = 40
EFC_AYCrCb16161616_12LSB = 41
EFC_YCrCbA16161616_12MSB = 42
EFC_YCrCbA16161616_12LSB = 43
EFC_ACrYCb16161616_12MSB = 44
EFC_ACrYCb16161616_12LSB = 45
EFC_CrYCbA16161616_12MSB = 46
EFC_CrYCbA16161616_12LSB = 47
EFC_Y8_CrCb88_420_PLANAR = 64
EFC_Y8_CbCr88_420_PLANAR = 65
EFC_Y10_CrCb1010_420_PLANAR = 66
EFC_Y10_CbCr1010_420_PLANAR = 67
EFC_Y12_CrCb1212_420_PLANAR = 68
EFC_Y12_CbCr1212_420_PLANAR = 69
EFC_YCrYCb8888_422_PACKED = 72
EFC_YCbYCr8888_422_PACKED = 73
EFC_CrYCbY8888_422_PACKED = 74
EFC_CbYCrY8888_422_PACKED = 75
EFC_YCrYCb10101010_422_PACKED = 76
EFC_YCbYCr10101010_422_PACKED = 77
EFC_CrYCbY10101010_422_PACKED = 78
EFC_CbYCrY10101010_422_PACKED = 79
EFC_YCrYCb12121212_422_PACKED = 80
EFC_YCbYCr12121212_422_PACKED = 81
EFC_CrYCbY12121212_422_PACKED = 82
EFC_CbYCrY12121212_422_PACKED = 83
EFC_RGB111110_FIX = 112
EFC_BGR101111_FIX = 113
EFC_ACrYCb2101010 = 114
EFC_CrYCbA1010102 = 115
EFC_RGB111110_FLOAT = 118
EFC_BGR101111_FLOAT = 119
EFC_MONO_8 = 120
EFC_MONO_10MSB = 121
EFC_MONO_10LSB = 122
EFC_MONO_12MSB = 123
EFC_MONO_12LSB = 124
EFC_MONO_16 = 125
EFC_SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum
__all__ = \
['ACCEPT_UNSOLICITED_RESPONSE_ENABLE',
'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ACP_TYPE_DVD_AUDIO',
'ACP_TYPE_GENERIC_AUDIO', 'ACP_TYPE_ICE60958_AUDIO',
'ACP_TYPE_SUPER_AUDIO_CD', 'ACrYCb16161616_10LSB',
'ACrYCb16161616_10MSB', 'ACrYCb16161616_12LSB',
'ACrYCb16161616_12MSB', 'ACrYCb2101010', 'ACrYCb8888',
'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS',
'AFMT_ACP_SOURCE_FROM_AZALIA', 'AFMT_ACP_TYPE',
'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT',
'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG',
'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG',
'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG',
'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG',
'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL',
'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE',
'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10',
'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12',
'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14',
'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9',
'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT',
'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT',
'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS',
'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER',
'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD',
'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND',
'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS',
'AFMT_AUDIO_PACKET_SENT_DISABLED',
'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM0',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM1',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM2',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM3',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM4',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM5',
'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS',
'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE',
'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS',
'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK',
'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE',
'AFMT_INTERRUPT_STATUS_CHG_MASK', 'AFMT_MEM_DISABLE_MEM_PWR_CTRL',
'AFMT_MEM_ENABLE_MEM_PWR_CTRL',
'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST',
'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST',
'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', 'AFMT_MEM_NO_FORCE_REQUEST',
'AFMT_MEM_PWR_DIS_CTRL', 'AFMT_MEM_PWR_FORCE_CTRL',
'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED',
'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED',
'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED',
'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE', 'ALLOW_SR_ON_TRANS_REQ',
'ALLOW_SR_ON_TRANS_REQ_DISABLE', 'ALLOW_SR_ON_TRANS_REQ_ENABLE',
'ALL_USE_R', 'ALPHA_DATA_ONTO_ALPHA_PORT',
'ALPHA_DATA_ONTO_CB_B_PORT', 'ALPHA_DATA_ONTO_CR_R_PORT',
'ALPHA_DATA_ONTO_Y_G_PORT',
'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK',
'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 'AMCLOCK_ENABLE',
'APG_ACP_OVERRIDE', 'APG_ACP_SOURCE_NO_OVERRIDE',
'APG_ACP_TYPE_DVD_AUDIO', 'APG_ACP_TYPE_GENERIC_AUDIO',
'APG_ACP_TYPE_ICE60958_AUDIO', 'APG_ACP_TYPE_SUPER_AUDIO_CD',
'APG_AUDIO_CRC_CH0_SIG', 'APG_AUDIO_CRC_CH1_SIG',
'APG_AUDIO_CRC_CH2_SIG', 'APG_AUDIO_CRC_CH3_SIG',
'APG_AUDIO_CRC_CH4_SIG', 'APG_AUDIO_CRC_CH5_SIG',
'APG_AUDIO_CRC_CH6_SIG', 'APG_AUDIO_CRC_CH7_SIG',
'APG_AUDIO_CRC_CONTINUOUS', 'APG_AUDIO_CRC_CONTROL_CH_SEL',
'APG_AUDIO_CRC_CONTROL_CONT', 'APG_AUDIO_CRC_ONESHOT',
'APG_AUDIO_CRC_RESERVED_10', 'APG_AUDIO_CRC_RESERVED_11',
'APG_AUDIO_CRC_RESERVED_12', 'APG_AUDIO_CRC_RESERVED_13',
'APG_AUDIO_CRC_RESERVED_14', 'APG_AUDIO_CRC_RESERVED_15',
'APG_AUDIO_CRC_RESERVED_8', 'APG_AUDIO_CRC_RESERVED_9',
'APG_DBG_ACP_TYPE', 'APG_DBG_AUDIO_DTO_BASE',
'APG_DBG_AUDIO_DTO_DIV', 'APG_DBG_AUDIO_DTO_MULTI',
'APG_DBG_MUX_SEL', 'APG_DEBUG_AUDIO_MODE',
'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ',
'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE',
'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED',
'APG_FUNCTIONAL_MODE', 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS',
'APG_INFOFRAME_SOURCE_NO_OVERRIDE',
'APG_MEM_DISABLE_MEM_PWR_CTRL', 'APG_MEM_ENABLE_MEM_PWR_CTRL',
'APG_MEM_FORCE_DEEP_SLEEP_REQUEST',
'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST',
'APG_MEM_FORCE_SHUT_DOWN_REQUEST', 'APG_MEM_NO_FORCE_REQUEST',
'APG_MEM_POWER_STATE', 'APG_MEM_POWER_STATE_DS',
'APG_MEM_POWER_STATE_LS', 'APG_MEM_POWER_STATE_ON',
'APG_MEM_POWER_STATE_SD', 'APG_MEM_PWR_DIS_CTRL',
'APG_MEM_PWR_FORCE_CTRL', 'APG_PACKET_CONTROL_ACP_SOURCE',
'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE', 'APG_RAMP_CONTROL_SIGN',
'APG_RAMP_SIGNED', 'APG_RAMP_UNSIGNED', 'ARGB1555',
'ARGB16161616_10LSB', 'ARGB16161616_10MSB', 'ARGB16161616_12LSB',
'ARGB16161616_12MSB', 'ARGB16161616_FLOAT', 'ARGB16161616_SNORM',
'ARGB16161616_UNORM', 'ARGB2101010', 'ARGB4444', 'ARGB8888',
'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', 'AUDIO_LAYOUT_SELECT',
'AUTOCAL_MODE_AUTOCENTER', 'AUTOCAL_MODE_AUTOREPLICATE',
'AUTOCAL_MODE_AUTOSCALE', 'AUTOCAL_MODE_OFF',
'AYCrCb16161616_10LSB', 'AYCrCb16161616_10MSB',
'AYCrCb16161616_12LSB', 'AYCrCb16161616_12MSB', 'AYCrCb8888',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE',
'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE',
'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE',
'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY',
'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE',
'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO',
'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET',
'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET',
'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9',
'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN',
'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT',
'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE',
'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED',
'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE',
'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED',
'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE',
'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN',
'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF',
'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET',
'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET',
'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC',
'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED',
'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED',
'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES',
'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED',
'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED',
'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET',
'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE',
'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES',
'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED',
'AZ_RIRB_WRITE_POINTER_DO_RESET',
'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET',
'AZ_STATE_CHANGE_STATUS',
'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT',
'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'BASE_RATE_44P1KHZ',
'BASE_RATE_48KHZ', 'BGR101111_FIX', 'BGR101111_FLOAT', 'BGR565',
'BIGK_FRAGMENT_SIZE', 'BINNER_BREAK_BATCH', 'BINNER_DROP',
'BINNER_PIPELINE', 'BINNER_PIPELINE_BREAK', 'BINNING_ALLOWED',
'BINNING_DISABLED', 'BINNING_ONE_PRIM_PER_BATCH',
'BIN_CONF_OVERRIDE_CHECK', 'BIN_MAP_MODE_NONE',
'BIN_MAP_MODE_POPS', 'BIN_MAP_MODE_RTA_INDEX',
'BIN_SIZE_128_PIXELS', 'BIN_SIZE_256_PIXELS',
'BIN_SIZE_32_PIXELS', 'BIN_SIZE_512_PIXELS', 'BIN_SIZE_64_PIXELS',
'BITS_31_0', 'BITS_32_1', 'BITS_33_2', 'BITS_34_3', 'BITS_35_4',
'BITS_36_5', 'BITS_37_6', 'BITS_38_7', 'BLEND_CONSTANT_ALPHA',
'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR',
'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE',
'BLEND_ONE_MINUS_CONSTANT_ALPHA',
'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA',
'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA',
'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1',
'BLEND_OPT_PRESERVE_A1_IGNORE_A0',
'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE',
'BLEND_OPT_PRESERVE_C0_IGNORE_C1',
'BLEND_OPT_PRESERVE_C1_IGNORE_C0',
'BLEND_OPT_PRESERVE_NONE_IGNORE_A0',
'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL',
'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA',
'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE',
'BLEND_SRC_COLOR', 'BLEND_ZERO', 'BLOCK_CONTEXT_DONE', 'BLUE_LUT',
'BOTTOM_OF_PIPE_TS', 'BREAK_BATCH', 'BYPASS', 'BYPASS_EN',
'BYPASS_POST_CSC', 'BinEventCntl', 'BinMapMode', 'BinSizeExtend',
'BinningMode', 'BlendOp', 'BlendOpt', 'CACHE_BYPASS',
'CACHE_FLUSH', 'CACHE_FLUSH_AND_INV_EVENT',
'CACHE_FLUSH_AND_INV_TS_EVENT', 'CACHE_FLUSH_TS', 'CACHE_LRU_RD',
'CACHE_LRU_WR', 'CACHE_NOA', 'CACHE_NOA_WR', 'CACHE_STREAM',
'CACHE_STREAM_RD', 'CBMode', 'CBPerfClearFilterSel',
'CBPerfOpFilterSel', 'CBPerfSel', 'CB_B_DATA_ONTO_ALPHA_PORT',
'CB_B_DATA_ONTO_CB_B_PORT', 'CB_B_DATA_ONTO_CR_R_PORT',
'CB_B_DATA_ONTO_Y_G_PORT', 'CB_DCC_DECOMPRESS', 'CB_DISABLE',
'CB_ELIMINATE_FAST_CLEAR', 'CB_NORMAL',
'CB_PERF_CLEAR_FILTER_SEL_CLEAR',
'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR',
'CB_PERF_OP_FILTER_SEL_DECOMPRESS',
'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR',
'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS',
'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION',
'CB_PERF_OP_FILTER_SEL_RESOLVE',
'CB_PERF_OP_FILTER_SEL_WRITE_ONLY',
'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN',
'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN',
'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN',
'CB_PERF_SEL_BACKEND_READ_CLOCK_EN',
'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN',
'CB_PERF_SEL_BE_CS_FILLRATE_1X2',
'CB_PERF_SEL_BE_CS_FILLRATE_2X1',
'CB_PERF_SEL_BE_CS_FILLRATE_2X2', 'CB_PERF_SEL_BE_RDLATFIFO_FULL',
'CB_PERF_SEL_BE_SRCFIFO_FULL', 'CB_PERF_SEL_BLEND_CLOCK_EN',
'CB_PERF_SEL_BLEND_COLLISION_DUE_TO_CACHE_WRITE',
'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST',
'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED',
'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED',
'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED',
'CB_PERF_SEL_BLEND_RAW_HAZARD_STALL',
'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT',
'CB_PERF_SEL_BLEND_STALL_ON_CACHE_ACCESS', 'CB_PERF_SEL_BUSY',
'CB_PERF_SEL_CCC_COLOR_RESOURCE_PANIC',
'CB_PERF_SEL_CCC_COLOR_RESOURCE_STALL',
'CB_PERF_SEL_CCC_FMASK_RESOURCE_PANIC',
'CB_PERF_SEL_CCC_FMASK_RESOURCE_STALL',
'CB_PERF_SEL_CCC_FREE_WAYS_PANIC',
'CB_PERF_SEL_CCC_FREE_WAYS_STALL',
'CB_PERF_SEL_CCC_IN_EVICT_HAZARD_STALL',
'CB_PERF_SEL_CCC_SKID_FIFO_FULL',
'CB_PERF_SEL_CCC_SKID_FIFO_STALL',
'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READY',
'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READYB',
'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READY',
'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READYB',
'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL',
'CB_PERF_SEL_CC_CACHE_DIRTY_QBLOCKS_FLUSHED',
'CB_PERF_SEL_CC_CACHE_FLUSH',
'CB_PERF_SEL_CC_CACHE_QBLOCKS_FLUSHED',
'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC',
'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL',
'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED',
'CB_PERF_SEL_CC_CACHE_SECTOR_HIT',
'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL',
'CB_PERF_SEL_CC_CACHE_TAG_MISS',
'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION',
'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL',
'CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST',
'CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST_IN_FLIGHT',
'CB_PERF_SEL_CC_CRW_GLX_REQ_WRITE_REQUEST',
'CB_PERF_SEL_CC_CRW_GLX_SRC_WRITE_CYCLES',
'CB_PERF_SEL_CC_FDCC_COMPRESS_FRAG_TIDS_IN',
'CB_PERF_SEL_CC_FDCC_DECOMPRESS_FRAG_TIDS_OUT',
'CB_PERF_SEL_CC_QUADFRAG_VALIDB_READY',
'CB_PERF_SEL_CC_QUADFRAG_VALIDB_READYB',
'CB_PERF_SEL_CC_QUADFRAG_VALID_READY',
'CB_PERF_SEL_CC_QUADFRAG_VALID_READYB', 'CB_PERF_SEL_CC_TAG_HIT',
'CB_PERF_SEL_COLOR_STORE_CLOCK_EN',
'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY',
'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB',
'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY',
'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', 'CB_PERF_SEL_DRAWN_BUSY',
'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD',
'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_EVENT',
'CB_PERF_SEL_EVENTS_CLK_EN',
'CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS',
'CB_PERF_SEL_EVENT_CACHE_FLUSH',
'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT',
'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT',
'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS',
'CB_PERF_SEL_EVENT_CONTEXT_DONE',
'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS',
'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META',
'CB_PERF_SEL_EXPORT_ADDED_1_FRAGMENT',
'CB_PERF_SEL_EXPORT_ADDED_2_FRAGMENTS',
'CB_PERF_SEL_EXPORT_ADDED_3_FRAGMENTS',
'CB_PERF_SEL_EXPORT_ADDED_4_FRAGMENTS',
'CB_PERF_SEL_EXPORT_ADDED_5_FRAGMENTS',
'CB_PERF_SEL_EXPORT_ADDED_6_FRAGMENTS',
'CB_PERF_SEL_EXPORT_ADDED_7_FRAGMENTS',
'CB_PERF_SEL_EXPORT_BLEND_OPT_BLEND_BYPASS',
'CB_PERF_SEL_EXPORT_BLEND_OPT_DISCARD_PIXELS',
'CB_PERF_SEL_EXPORT_BLEND_OPT_DONT_READ_DST',
'CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_AFTER_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_BEFORE_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_AFTER_UPDATE',
'CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_BEFORE_UPDATE',
'CB_PERF_SEL_EXPORT_KILLED_BY_COLOR_INVALID',
'CB_PERF_SEL_EXPORT_KILLED_BY_DISCARD_PIXEL',
'CB_PERF_SEL_EXPORT_KILLED_BY_NULL_SAMPLE_MASK',
'CB_PERF_SEL_EXPORT_KILLED_BY_NULL_TARGET_SHADER_MASK',
'CB_PERF_SEL_EXPORT_READS_FRAGMENT_0',
'CB_PERF_SEL_EXPORT_READS_FRAGMENT_1',
'CB_PERF_SEL_EXPORT_READS_FRAGMENT_2',
'CB_PERF_SEL_EXPORT_READS_FRAGMENT_3',
'CB_PERF_SEL_EXPORT_READS_FRAGMENT_4',
'CB_PERF_SEL_EXPORT_READS_FRAGMENT_5',
'CB_PERF_SEL_EXPORT_READS_FRAGMENT_6',
'CB_PERF_SEL_EXPORT_READS_FRAGMENT_7',
'CB_PERF_SEL_EXPORT_REMOVED_1_FRAGMENT',
'CB_PERF_SEL_EXPORT_REMOVED_2_FRAGMENTS',
'CB_PERF_SEL_EXPORT_REMOVED_3_FRAGMENTS',
'CB_PERF_SEL_EXPORT_REMOVED_4_FRAGMENTS',
'CB_PERF_SEL_EXPORT_REMOVED_5_FRAGMENTS',
'CB_PERF_SEL_EXPORT_REMOVED_6_FRAGMENTS',
'CB_PERF_SEL_EXPORT_REMOVED_7_FRAGMENTS',
'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_0',
'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_1',
'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_2',
'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_3',
'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_4',
'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_5',
'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_6',
'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_7',
'CB_PERF_SEL_FORMAT_IS_16_16_FLOAT_8PIX',
'CB_PERF_SEL_FORMAT_IS_16_16_SIGNED_8PIX',
'CB_PERF_SEL_FORMAT_IS_16_16_UNSIGNED_8PIX',
'CB_PERF_SEL_FORMAT_IS_32BPP_8PIX',
'CB_PERF_SEL_FORMAT_IS_32_ABGR', 'CB_PERF_SEL_FORMAT_IS_32_AR',
'CB_PERF_SEL_FORMAT_IS_32_GR', 'CB_PERF_SEL_FORMAT_IS_32_R',
'CB_PERF_SEL_FORMAT_IS_FP16_ABGR',
'CB_PERF_SEL_FORMAT_IS_SIGNED16_ABGR',
'CB_PERF_SEL_FORMAT_IS_UNSIGNED16_ABGR',
'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN',
'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN',
'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN',
'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN',
'CB_PERF_SEL_GRBM_CLOCK_EN', 'CB_PERF_SEL_MEMARB_CLOCK_EN',
'CB_PERF_SEL_PERFMON_CLOCK_EN',
'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH',
'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT',
'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT',
'CB_PERF_SEL_RDLAT_FIFO_QUAD_RESIDENCY_STALL',
'CB_PERF_SEL_STATIC_CLOCK_EN', 'CB_RESERVED',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL',
'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY',
'CHA_PERF_SEL', 'CHA_PERF_SEL_ARB_REQUESTS', 'CHA_PERF_SEL_BUSY',
'CHA_PERF_SEL_CYCLE', 'CHA_PERF_SEL_IO_32B_WDS_CHC0',
'CHA_PERF_SEL_IO_32B_WDS_CHC1', 'CHA_PERF_SEL_IO_32B_WDS_CHC2',
'CHA_PERF_SEL_IO_32B_WDS_CHC3',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC0',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC1',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC2',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC3',
'CHA_PERF_SEL_MEM_32B_WDS_CHC0', 'CHA_PERF_SEL_MEM_32B_WDS_CHC1',
'CHA_PERF_SEL_MEM_32B_WDS_CHC2', 'CHA_PERF_SEL_MEM_32B_WDS_CHC3',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', 'CHA_PERF_SEL_REQUEST_CHC0',
'CHA_PERF_SEL_REQUEST_CHC1', 'CHA_PERF_SEL_REQUEST_CHC2',
'CHA_PERF_SEL_REQUEST_CHC3', 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL',
'CHA_PERF_SEL_STALL_CHC0', 'CHA_PERF_SEL_STALL_CHC1',
'CHA_PERF_SEL_STALL_CHC2', 'CHA_PERF_SEL_STALL_CHC3',
'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0',
'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1',
'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2',
'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', 'CHC_PERF_SEL',
'CHC_PERF_SEL_ARB_RET_LEVEL', 'CHC_PERF_SEL_BUSY',
'CHC_PERF_SEL_CYCLE', 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY',
'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHC_PERF_SEL_REQ',
'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET',
'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHC_PERF_SEL_REQ_CLIENT0',
'CHC_PERF_SEL_REQ_CLIENT1', 'CHC_PERF_SEL_REQ_CLIENT10',
'CHC_PERF_SEL_REQ_CLIENT11', 'CHC_PERF_SEL_REQ_CLIENT12',
'CHC_PERF_SEL_REQ_CLIENT13', 'CHC_PERF_SEL_REQ_CLIENT14',
'CHC_PERF_SEL_REQ_CLIENT15', 'CHC_PERF_SEL_REQ_CLIENT16',
'CHC_PERF_SEL_REQ_CLIENT17', 'CHC_PERF_SEL_REQ_CLIENT18',
'CHC_PERF_SEL_REQ_CLIENT19', 'CHC_PERF_SEL_REQ_CLIENT2',
'CHC_PERF_SEL_REQ_CLIENT20', 'CHC_PERF_SEL_REQ_CLIENT21',
'CHC_PERF_SEL_REQ_CLIENT22', 'CHC_PERF_SEL_REQ_CLIENT23',
'CHC_PERF_SEL_REQ_CLIENT3', 'CHC_PERF_SEL_REQ_CLIENT4',
'CHC_PERF_SEL_REQ_CLIENT5', 'CHC_PERF_SEL_REQ_CLIENT6',
'CHC_PERF_SEL_REQ_CLIENT7', 'CHC_PERF_SEL_REQ_CLIENT8',
'CHC_PERF_SEL_REQ_CLIENT9', 'CHC_PERF_SEL_REQ_NOP_ACK',
'CHC_PERF_SEL_REQ_NOP_RTN0', 'CHC_PERF_SEL_REQ_READ',
'CHC_PERF_SEL_REQ_READ_128B', 'CHC_PERF_SEL_REQ_READ_32B',
'CHC_PERF_SEL_REQ_READ_64B', 'CHC_PERF_SEL_REQ_WRITE',
'CHC_PERF_SEL_REQ_WRITE_32B', 'CHC_PERF_SEL_REQ_WRITE_64B',
'CHC_PERF_SEL_STALL_BUFFER_FULL', 'CHC_PERF_SEL_STALL_GL2_GL1',
'CHC_PERF_SEL_STARVE', 'CHUNK_SIZE', 'CHUNK_SIZE_16KB',
'CHUNK_SIZE_1KB', 'CHUNK_SIZE_2KB', 'CHUNK_SIZE_32KB',
'CHUNK_SIZE_4KB', 'CHUNK_SIZE_64KB', 'CHUNK_SIZE_8KB',
'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', 'CLKGATE_SM_MODE',
'CLOCK_BRANCH_SOFT_RESET', 'CLOCK_BRANCH_SOFT_RESET_FORCE',
'CLOCK_BRANCH_SOFT_RESET_NOOP', 'CLOCK_GATING_DISABLE',
'CLOCK_GATING_DISABLED', 'CLOCK_GATING_DISABLED_IN_DCO',
'CLOCK_GATING_DISABLE_ENUM', 'CLOCK_GATING_DISABLE_ENUM_DISABLED',
'CLOCK_GATING_DISABLE_ENUM_ENABLED', 'CLOCK_GATING_EN',
'CLOCK_GATING_ENABLE', 'CLOCK_GATING_ENABLED',
'CLOCK_GATING_ENABLED_IN_DCO', 'CMC_3DLUT_17CUBE',
'CMC_3DLUT_30BIT', 'CMC_3DLUT_30BIT_ENUM', 'CMC_3DLUT_36BIT',
'CMC_3DLUT_9CUBE', 'CMC_3DLUT_RAM_SEL', 'CMC_3DLUT_SIZE_ENUM',
'CMC_LUT_2CFG_MEMORY_A', 'CMC_LUT_2CFG_MEMORY_B',
'CMC_LUT_2CFG_NO_MEMORY', 'CMC_LUT_2_CONFIG_ENUM',
'CMC_LUT_2_MODE_BYPASS', 'CMC_LUT_2_MODE_ENUM',
'CMC_LUT_2_MODE_RAMA_LUT', 'CMC_LUT_2_MODE_RAMB_LUT',
'CMC_LUT_NUM_SEG', 'CMC_LUT_RAM_SEL', 'CMC_RAM0_ACCESS',
'CMC_RAM1_ACCESS', 'CMC_RAM2_ACCESS', 'CMC_RAM3_ACCESS',
'CMC_RAMA_ACCESS', 'CMC_RAMB_ACCESS', 'CMC_SEGMENTS_1',
'CMC_SEGMENTS_128', 'CMC_SEGMENTS_16', 'CMC_SEGMENTS_2',
'CMC_SEGMENTS_32', 'CMC_SEGMENTS_4', 'CMC_SEGMENTS_64',
'CMC_SEGMENTS_8', 'CMPTO', 'CM_BYPASS', 'CM_COEF_FORMAT_ENUM',
'CM_DATA_SIGNED', 'CM_DISABLE', 'CM_EN', 'CM_ENABLE',
'CM_GAMMA_LUT_MODE_ENUM', 'CM_GAMMA_LUT_PWL_DISABLE_ENUM',
'CM_GAMMA_LUT_SEL_ENUM', 'CM_LUT_2_CONFIG_ENUM',
'CM_LUT_2_MODE_ENUM', 'CM_LUT_4_CONFIG_ENUM',
'CM_LUT_4_MODE_ENUM', 'CM_LUT_CONFIG_MODE', 'CM_LUT_NUM_SEG',
'CM_LUT_RAM_SEL', 'CM_LUT_READ_COLOR_SEL', 'CM_LUT_READ_DBG',
'CM_NOT_PENDING', 'CM_PENDING', 'CM_POST_CSC_MODE_ENUM',
'CM_WRITE_BASE_ONLY', 'CM_YES_PENDING', 'CNVC_ROUND',
'CNVC_TRUNCATE', 'COEF_POST_CSC', 'COEF_POST_CSC_B',
'COEF_RAM_SELECT_BACK', 'COEF_RAM_SELECT_CURRENT',
'COEF_RAM_SELECT_RD', 'COLOR_24BIT_1BIT_AND',
'COLOR_24BIT_8BIT_ALPHA_PREMULT',
'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', 'COLOR_64BIT_FP_PREMULT',
'COLOR_64BIT_FP_UNPREMULT', 'COLOR_KEYER_ENABLE',
'COLOR_KEYER_MODE', 'COLOR_KEY_DIS', 'COLOR_KEY_EN',
'COMB_DST_MINUS_SRC', 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC',
'COMB_MIN_DST_SRC', 'COMB_SRC_MINUS_DST',
'COMPRESSION_MODE_BYPASS_COMPRESSION',
'COMPRESSION_MODE_BYPASS_METADATA_CACHE',
'COMPRESSION_MODE_COMPRESSION_ENABLED',
'COMPRESSION_MODE_READ_DECOMPRESSED',
'COMPRESSION_MODE_READ_RAW_COMPRESSED_DATA',
'COMPRESSION_MODE_WRITE_COMPRESSION_DISABLED',
'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', 'CONFIG_SPACE2_END',
'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', 'CONFIG_SPACE_START',
'CONTEXT_DONE', 'CONTEXT_SPACE_END', 'CONTEXT_SPACE_START',
'CONTEXT_SUSPEND', 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET',
'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET',
'CORB_READ_POINTER_RESET',
'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET',
'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0',
'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_LATENCY_STATS_SEL',
'CPC_LATENCY_STATS_SEL_INVAL_LAST',
'CPC_LATENCY_STATS_SEL_INVAL_MAX',
'CPC_LATENCY_STATS_SEL_INVAL_MIN',
'CPC_LATENCY_STATS_SEL_XACK_LAST',
'CPC_LATENCY_STATS_SEL_XACK_MAX',
'CPC_LATENCY_STATS_SEL_XACK_MIN',
'CPC_LATENCY_STATS_SEL_XNACK_LAST',
'CPC_LATENCY_STATS_SEL_XNACK_MAX',
'CPC_LATENCY_STATS_SEL_XNACK_MIN', 'CPC_PERFCOUNT_SEL',
'CPC_PERF_SEL_ALWAYS_COUNT', 'CPC_PERF_SEL_CPC_GCRIU_BUSY',
'CPC_PERF_SEL_CPC_GCRIU_IDLE', 'CPC_PERF_SEL_CPC_GCRIU_STALL',
'CPC_PERF_SEL_CPC_STAT_BUSY', 'CPC_PERF_SEL_CPC_STAT_IDLE',
'CPC_PERF_SEL_CPC_STAT_STALL', 'CPC_PERF_SEL_CPC_TCIU_BUSY',
'CPC_PERF_SEL_CPC_TCIU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY',
'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_STALL',
'CPC_PERF_SEL_CPC_UTCL2IU_XACK', 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK',
'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
'CPC_PERF_SEL_GUS_READ_REQUEST_SENT',
'CPC_PERF_SEL_GUS_WRITE_REQUEST_SENT',
'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE',
'CPC_PERF_SEL_ME1_DC0_SPI_BUSY',
'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ',
'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_READ',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_WRITE',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ',
'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE',
'CPC_PERF_SEL_ME2_DC1_SPI_BUSY',
'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ',
'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_READ',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_WRITE',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ',
'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT',
'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', 'CPC_PERF_SEL_MEC_THREAD0',
'CPC_PERF_SEL_MEC_THREAD1', 'CPC_PERF_SEL_MEC_THREAD2',
'CPC_PERF_SEL_MEC_THREAD3', 'CPC_PERF_SEL_MES_THREAD0',
'CPC_PERF_SEL_MES_THREAD1',
'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION',
'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE',
'CPC_PERF_SEL_TCIU_READ_REQUEST_SENT',
'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE',
'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS',
'CPC_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION',
'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM',
'CPF_LATENCY_STATS_SEL', 'CPF_LATENCY_STATS_SEL_INVAL_LAST',
'CPF_LATENCY_STATS_SEL_INVAL_MAX',
'CPF_LATENCY_STATS_SEL_INVAL_MIN',
'CPF_LATENCY_STATS_SEL_READ_LAST',
'CPF_LATENCY_STATS_SEL_READ_MAX',
'CPF_LATENCY_STATS_SEL_READ_MIN',
'CPF_LATENCY_STATS_SEL_XACK_LAST',
'CPF_LATENCY_STATS_SEL_XACK_MAX',
'CPF_LATENCY_STATS_SEL_XACK_MIN',
'CPF_LATENCY_STATS_SEL_XNACK_LAST',
'CPF_LATENCY_STATS_SEL_XNACK_MAX',
'CPF_LATENCY_STATS_SEL_XNACK_MIN', 'CPF_PERFCOUNTWINDOW_SEL',
'CPF_PERFCOUNT_SEL', 'CPF_PERFWINDOW_SEL_CSF',
'CPF_PERFWINDOW_SEL_HQD1', 'CPF_PERFWINDOW_SEL_HQD2',
'CPF_PERFWINDOW_SEL_RDMA', 'CPF_PERFWINDOW_SEL_RWPP',
'CPF_PERF_SEL_ALWAYS_COUNT',
'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION',
'CPF_PERF_SEL_CPF_GCRIU_BUSY', 'CPF_PERF_SEL_CPF_GCRIU_IDLE',
'CPF_PERF_SEL_CPF_GCRIU_STALL', 'CPF_PERF_SEL_CPF_STAT_BUSY',
'CPF_PERF_SEL_CPF_STAT_IDLE', 'CPF_PERF_SEL_CPF_STAT_STALL',
'CPF_PERF_SEL_CPF_TCIU_BUSY', 'CPF_PERF_SEL_CPF_TCIU_IDLE',
'CPF_PERF_SEL_CPF_TCIU_STALL', 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY',
'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', 'CPF_PERF_SEL_CPF_UTCL2IU_STALL',
'CPF_PERF_SEL_CPF_UTCL2IU_XACK', 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK',
'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE',
'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ',
'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY',
'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE',
'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS',
'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR',
'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID',
'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION',
'CPF_PERF_SEL_GRBM_DWORDS_SENT',
'CPF_PERF_SEL_GUS_READ_REQUEST_SENT',
'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT',
'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE',
'CPF_PERF_SEL_REGISTER_CLOCK_VALID',
'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT',
'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE',
'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS',
'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS',
'CPF_SCRATCH_REG_ATOMIC_ADD', 'CPF_SCRATCH_REG_ATOMIC_AND',
'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', 'CPF_SCRATCH_REG_ATOMIC_MAX',
'CPF_SCRATCH_REG_ATOMIC_MIN', 'CPF_SCRATCH_REG_ATOMIC_NOT',
'CPF_SCRATCH_REG_ATOMIC_OP', 'CPF_SCRATCH_REG_ATOMIC_OR',
'CPF_SCRATCH_REG_ATOMIC_SUB', 'CPF_TAG_RAM',
'CPG_LATENCY_STATS_SEL', 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST',
'CPG_LATENCY_STATS_SEL_ATOMIC_MAX',
'CPG_LATENCY_STATS_SEL_ATOMIC_MIN',
'CPG_LATENCY_STATS_SEL_INVAL_LAST',
'CPG_LATENCY_STATS_SEL_INVAL_MAX',
'CPG_LATENCY_STATS_SEL_INVAL_MIN',
'CPG_LATENCY_STATS_SEL_READ_LAST',
'CPG_LATENCY_STATS_SEL_READ_MAX',
'CPG_LATENCY_STATS_SEL_READ_MIN',
'CPG_LATENCY_STATS_SEL_WRITE_LAST',
'CPG_LATENCY_STATS_SEL_WRITE_MAX',
'CPG_LATENCY_STATS_SEL_WRITE_MIN',
'CPG_LATENCY_STATS_SEL_XACK_LAST',
'CPG_LATENCY_STATS_SEL_XACK_MAX',
'CPG_LATENCY_STATS_SEL_XACK_MIN',
'CPG_LATENCY_STATS_SEL_XNACK_LAST',
'CPG_LATENCY_STATS_SEL_XNACK_MAX',
'CPG_LATENCY_STATS_SEL_XNACK_MIN', 'CPG_PERFCOUNTWINDOW_SEL',
'CPG_PERFCOUNT_SEL', 'CPG_PERFWINDOW_SEL_APPEND',
'CPG_PERFWINDOW_SEL_CE', 'CPG_PERFWINDOW_SEL_CEDMA',
'CPG_PERFWINDOW_SEL_CPC_IC', 'CPG_PERFWINDOW_SEL_CPG_IC',
'CPG_PERFWINDOW_SEL_DDID', 'CPG_PERFWINDOW_SEL_DFY',
'CPG_PERFWINDOW_SEL_DMA', 'CPG_PERFWINDOW_SEL_ME',
'CPG_PERFWINDOW_SEL_MEC1', 'CPG_PERFWINDOW_SEL_MEC2',
'CPG_PERFWINDOW_SEL_MEMRD', 'CPG_PERFWINDOW_SEL_MEMWR',
'CPG_PERFWINDOW_SEL_MES', 'CPG_PERFWINDOW_SEL_PFP',
'CPG_PERFWINDOW_SEL_PQ1', 'CPG_PERFWINDOW_SEL_PQ2',
'CPG_PERFWINDOW_SEL_PQ3', 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR',
'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', 'CPG_PERFWINDOW_SEL_QURD',
'CPG_PERFWINDOW_SEL_QU_EOP', 'CPG_PERFWINDOW_SEL_QU_PIPE',
'CPG_PERFWINDOW_SEL_QU_STRM', 'CPG_PERFWINDOW_SEL_RB',
'CPG_PERFWINDOW_SEL_RESERVED1', 'CPG_PERFWINDOW_SEL_RESERVED2',
'CPG_PERFWINDOW_SEL_SHADOW', 'CPG_PERFWINDOW_SEL_SR',
'CPG_PERFWINDOW_SEL_VGT0', 'CPG_PERFWINDOW_SEL_VGT1',
'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', 'CPG_PERF_SEL_ALWAYS_COUNT',
'CPG_PERF_SEL_CE_INSTR_CACHE_HIT',
'CPG_PERF_SEL_CE_INSTR_CACHE_MISS',
'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG',
'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ',
'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER',
'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO',
'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO',
'CPG_PERF_SEL_CE_STALL_RAM_DUMP',
'CPG_PERF_SEL_CE_STALL_RAM_WRITE',
'CPG_PERF_SEL_COUNT_TYPE0_PACKETS',
'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 'CPG_PERF_SEL_CPG_GCRIU_BUSY',
'CPG_PERF_SEL_CPG_GCRIU_IDLE', 'CPG_PERF_SEL_CPG_GCRIU_STALL',
'CPG_PERF_SEL_CPG_STAT_BUSY', 'CPG_PERF_SEL_CPG_STAT_IDLE',
'CPG_PERF_SEL_CPG_STAT_STALL', 'CPG_PERF_SEL_CPG_TCIU_BUSY',
'CPG_PERF_SEL_CPG_TCIU_IDLE', 'CPG_PERF_SEL_CPG_TCIU_STALL',
'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE',
'CPG_PERF_SEL_CPG_UTCL2IU_STALL', 'CPG_PERF_SEL_CPG_UTCL2IU_XACK',
'CPG_PERF_SEL_CPG_UTCL2IU_XNACK',
'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS',
'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT',
'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS',
'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS',
'CPG_PERF_SEL_DMA_BUSY',
'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL',
'CPG_PERF_SEL_DMA_STALLED', 'CPG_PERF_SEL_DMA_STARVED',
'CPG_PERF_SEL_DYNAMIC_CLK_VALID',
'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
'CPG_PERF_SEL_GUS_READ_REQUEST_SENT',
'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT',
'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY',
'CPG_PERF_SEL_ME_INSTR_CACHE_HIT',
'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', 'CPG_PERF_SEL_ME_PARSER_BUSY',
'CPG_PERF_SEL_ME_PWS_STALLED0', 'CPG_PERF_SEL_ME_PWS_STALLED1',
'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP',
'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ',
'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX',
'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH',
'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS',
'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU',
'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER',
'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER',
'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT',
'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS',
'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1',
'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2',
'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1',
'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2',
'CPG_PERF_SEL_PFP_PWS_STALLED0', 'CPG_PERF_SEL_PFP_PWS_STALLED1',
'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ',
'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY',
'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY',
'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY',
'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY',
'CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL0',
'CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL1',
'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS0',
'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS1',
'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS0',
'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS1',
'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE',
'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM',
'CPG_PERF_SEL_RBIU_FIFO_FULL',
'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ',
'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ',
'CPG_PERF_SEL_REGISTER_CLK_VALID',
'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX',
'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS',
'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT',
'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE',
'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS',
'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION',
'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM',
'CP_ALPHA_TAG_RAM_SEL', 'CP_DDID_CNTL_MODE', 'CP_DDID_CNTL_SIZE',
'CP_DDID_CNTL_VMID_SEL', 'CP_ME_ID', 'CP_PERFMON_ENABLE_MODE',
'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT',
'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE',
'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE',
'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE',
'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM',
'CP_PERFMON_STATE_DISABLE_AND_RESET',
'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM',
'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING',
'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID',
'CRC_CUR_0', 'CRC_CUR_1', 'CRC_CUR_SEL', 'CRC_INTERLACE_0',
'CRC_INTERLACE_1', 'CRC_INTERLACE_2', 'CRC_INTERLACE_3',
'CRC_INTERLACE_SEL', 'CRC_IN_PIX_0', 'CRC_IN_PIX_1',
'CRC_IN_PIX_2', 'CRC_IN_PIX_3', 'CRC_IN_PIX_4', 'CRC_IN_PIX_5',
'CRC_IN_PIX_6', 'CRC_IN_PIX_7', 'CRC_IN_PIX_SEL', 'CRC_SRC_0',
'CRC_SRC_1', 'CRC_SRC_2', 'CRC_SRC_3', 'CRC_SRC_SEL',
'CRC_STEREO_0', 'CRC_STEREO_1', 'CRC_STEREO_2', 'CRC_STEREO_3',
'CRC_STEREO_SEL', 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1',
'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2',
'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
'CROB_MEM_PWR_LIGHT_SLEEP_MODE', 'CROSSBAR_FOR_ALPHA',
'CROSSBAR_FOR_CB_B', 'CROSSBAR_FOR_CR_R', 'CROSSBAR_FOR_Y_G',
'CRS', 'CR_R_DATA_ONTO_ALPHA_PORT', 'CR_R_DATA_ONTO_CB_B_PORT',
'CR_R_DATA_ONTO_CR_R_PORT', 'CR_R_DATA_ONTO_Y_G_PORT',
'CSCNTL_ADDR_WIDTH', 'CSCNTL_DATA_WIDTH', 'CSCNTL_TYPE',
'CSCNTL_TYPE_EVENT', 'CSCNTL_TYPE_PRIVATE', 'CSCNTL_TYPE_STATE',
'CSCNTL_TYPE_TG', 'CSCNTL_TYPE_WIDTH', 'CSDATA_ADDR_WIDTH',
'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', 'CSDATA_TYPE_EVENT',
'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', 'CSDATA_TYPE_TG',
'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', 'CS_DONE', 'CS_NA',
'CS_PARTIAL_FLUSH', 'CURSOR_2X_MAGNIFY',
'CURSOR_2X_MAGNIFY_IS_DISABLE', 'CURSOR_2X_MAGNIFY_IS_ENABLE',
'CURSOR_COLOR_24BIT_1BIT_AND',
'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT',
'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT',
'CURSOR_COLOR_64BIT_FP_PREMULT',
'CURSOR_COLOR_64BIT_FP_UNPREMULT', 'CURSOR_ENABLE',
'CURSOR_IN_GUEST_PHYSICAL_ADDRESS',
'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', 'CURSOR_IS_DISABLE',
'CURSOR_IS_ENABLE', 'CURSOR_IS_NOT_SNOOP', 'CURSOR_IS_SNOOP',
'CURSOR_LINES_PER_CHUNK', 'CURSOR_LINE_PER_CHUNK_1',
'CURSOR_LINE_PER_CHUNK_16', 'CURSOR_LINE_PER_CHUNK_2',
'CURSOR_LINE_PER_CHUNK_4', 'CURSOR_LINE_PER_CHUNK_8',
'CURSOR_MODE', 'CURSOR_MONO_2BIT',
'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY',
'CURSOR_PERFMON_LATENCY_MEASURE_EN',
'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED',
'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED',
'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY',
'CURSOR_PERFMON_LATENCY_MEASURE_SEL', 'CURSOR_PITCH',
'CURSOR_PITCH_128_PIXELS', 'CURSOR_PITCH_256_PIXELS',
'CURSOR_PITCH_64_PIXELS', 'CURSOR_REQUEST_EARLY',
'CURSOR_REQUEST_NORMALLY', 'CURSOR_REQ_MODE', 'CURSOR_SNOOP',
'CURSOR_STEREO_EN', 'CURSOR_STEREO_IS_DISABLED',
'CURSOR_STEREO_IS_ENABLED', 'CURSOR_SURFACE_IS_NOT_TMZ',
'CURSOR_SURFACE_IS_TMZ', 'CURSOR_SURFACE_TMZ', 'CURSOR_SYSTEM',
'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS',
'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0',
'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1',
'CUR_CLAMP_DIS', 'CUR_CLAMP_EN', 'CUR_DIS',
'CUR_DYNAMIC_EXPANSION', 'CUR_EN', 'CUR_ENABLE',
'CUR_EXPAND_MODE', 'CUR_FP_NO_ROM', 'CUR_FP_USE_ROM',
'CUR_INV_CLAMP', 'CUR_MATRIX_COEF_FORMAT_ENUM',
'CUR_MATRIX_FIX_S2_13', 'CUR_MATRIX_FIX_S3_12', 'CUR_MODE',
'CUR_NOT_PENDING', 'CUR_PENDING', 'CUR_ROM_EN', 'CUR_YES_PENDING',
'CUR_ZERO_EXPANSION', 'CbYCrY10101010_422_PACKED',
'CbYCrY12121212_422_PACKED', 'CbYCrY8888_422_PACKED', 'CombFunc',
'CompareFrag', 'ConservativeZExport', 'CovToShaderSel',
'CrYCbA1010102', 'CrYCbA16161616_10LSB', 'CrYCbA16161616_10MSB',
'CrYCbA16161616_12LSB', 'CrYCbA16161616_12MSB', 'CrYCbA8888',
'CrYCbY10101010_422_PACKED', 'CrYCbY12121212_422_PACKED',
'CrYCbY8888_422_PACKED', 'DAC_MUX_SELECT', 'DAC_MUX_SELECT_DACA',
'DAC_MUX_SELECT_DACB', 'DB_BYPASS', 'DB_BYPASS_WR_DISABLE',
'DB_CACHE_FLUSH_AND_INV', 'DB_COMP_WR_DISABLE', 'DB_DEFAULT',
'DB_PERF_SEL_CB_DB_rdreq_prt_sends',
'DB_PERF_SEL_CB_DB_rdreq_sends',
'DB_PERF_SEL_CB_DB_wrreq_prt_sends',
'DB_PERF_SEL_CB_DB_wrreq_sends',
'DB_PERF_SEL_DB_CB_context_dones', 'DB_PERF_SEL_DB_CB_eop_dones',
'DB_PERF_SEL_DB_CB_export_busy',
'DB_PERF_SEL_DB_CB_export_double_format',
'DB_PERF_SEL_DB_CB_export_events',
'DB_PERF_SEL_DB_CB_export_export_quads',
'DB_PERF_SEL_DB_CB_export_fast_format',
'DB_PERF_SEL_DB_CB_export_fmt_16_16_float_8pix',
'DB_PERF_SEL_DB_CB_export_fmt_16_16_signed_8pix',
'DB_PERF_SEL_DB_CB_export_fmt_16_16_unsigned_8pix',
'DB_PERF_SEL_DB_CB_export_fmt_32bpp_8pix',
'DB_PERF_SEL_DB_CB_export_is_event_BOTTOM_OF_PIPE_TS',
'DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_CB_PIXEL_DATA',
'DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_DB_DATA_TS',
'DB_PERF_SEL_DB_CB_export_num_pixels_need_blending',
'DB_PERF_SEL_DB_CB_export_quads',
'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x1',
'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x2',
'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x1',
'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x2',
'DB_PERF_SEL_DB_CB_export_sends',
'DB_PERF_SEL_DB_CB_export_slow_format',
'DB_PERF_SEL_DB_CB_export_stalls',
'DB_PERF_SEL_DB_CB_export_waiting_for_perfcounter_stop_event',
'DB_PERF_SEL_DB_CB_rdret_ack', 'DB_PERF_SEL_DB_CB_rdret_nack',
'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack',
'DB_PERF_SEL_DB_SC_c_tile_rate', 'DB_PERF_SEL_DB_SC_quad_busy',
'DB_PERF_SEL_DB_SC_quad_conflicts',
'DB_PERF_SEL_DB_SC_quad_double_quad',
'DB_PERF_SEL_DB_SC_quad_lit_noz_quad',
'DB_PERF_SEL_DB_SC_quad_lit_quad',
'DB_PERF_SEL_DB_SC_quad_noz_tiles',
'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels',
'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels',
'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels',
'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel',
'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels',
'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels',
'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels',
'DB_PERF_SEL_DB_SC_quad_sends', 'DB_PERF_SEL_DB_SC_quad_stalls',
'DB_PERF_SEL_DB_SC_quad_tiles', 'DB_PERF_SEL_DB_SC_s_tile_rate',
'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled',
'DB_PERF_SEL_DB_SC_tile_df_stalls',
'DB_PERF_SEL_DB_SC_tile_fast_ops',
'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops',
'DB_PERF_SEL_DB_SC_tile_fast_z_ops',
'DB_PERF_SEL_DB_SC_tile_hier_kill',
'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends',
'DB_PERF_SEL_DB_SC_tile_ssaa_kill',
'DB_PERF_SEL_DB_SC_tile_stalls',
'DB_PERF_SEL_DB_SC_tile_tile_rate',
'DB_PERF_SEL_DB_SC_tile_tiles', 'DB_PERF_SEL_DB_SC_wave_busy',
'DB_PERF_SEL_DB_SC_wave_conflict',
'DB_PERF_SEL_DB_SC_wave_hard_conflict',
'DB_PERF_SEL_DB_SC_wave_id_wrapped',
'DB_PERF_SEL_DB_SC_wave_sends', 'DB_PERF_SEL_DB_SC_wave_stalls',
'DB_PERF_SEL_DB_SC_z_tile_rate',
'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall',
'DB_PERF_SEL_Depth_Tile_Cache_busy',
'DB_PERF_SEL_Depth_Tile_Cache_data_frees',
'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop',
'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked',
'DB_PERF_SEL_Depth_Tile_Cache_event',
'DB_PERF_SEL_Depth_Tile_Cache_flushes',
'DB_PERF_SEL_Depth_Tile_Cache_hits',
'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve',
'DB_PERF_SEL_Depth_Tile_Cache_misses',
'DB_PERF_SEL_Depth_Tile_Cache_noop_tile',
'DB_PERF_SEL_Depth_Tile_Cache_sends',
'DB_PERF_SEL_Depth_Tile_Cache_starves',
'DB_PERF_SEL_Depth_Tile_Cache_tile_frees',
'DB_PERF_SEL_MI_psd_req_wrack_counter_stall',
'DB_PERF_SEL_MI_quad_req_wrack_counter_stall',
'DB_PERF_SEL_MI_tile_req_wrack_counter_stall',
'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall',
'DB_PERF_SEL_OREO_Events_delayed', 'DB_PERF_SEL_OREO_Events_load',
'DB_PERF_SEL_OREO_Events_non_transition',
'DB_PERF_SEL_OREO_Events_stalls',
'DB_PERF_SEL_OREO_Events_transition',
'DB_PERF_SEL_OREO_SB_evicts', 'DB_PERF_SEL_OREO_SB_hits',
'DB_PERF_SEL_OREO_SB_misses', 'DB_PERF_SEL_OREO_SB_stalls',
'DB_PERF_SEL_OREO_ST_load', 'DB_PERF_SEL_OREO_ST_read',
'DB_PERF_SEL_OREO_ST_stalls', 'DB_PERF_SEL_OREO_TT_load',
'DB_PERF_SEL_OREO_TT_read', 'DB_PERF_SEL_OREO_TT_stalls',
'DB_PERF_SEL_OREO_WT_load', 'DB_PERF_SEL_OREO_WT_read',
'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall',
'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy',
'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits',
'DB_PERF_SEL_Plane_Cache_flushes',
'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits',
'DB_PERF_SEL_Plane_Cache_misses',
'DB_PERF_SEL_Plane_Cache_starves',
'DB_PERF_SEL_PostZ_Samples_failing_DB',
'DB_PERF_SEL_PostZ_Samples_failing_S',
'DB_PERF_SEL_PostZ_Samples_failing_Z',
'DB_PERF_SEL_PostZ_Samples_passing_Z',
'DB_PERF_SEL_PreZ_Samples_failing_DB',
'DB_PERF_SEL_PreZ_Samples_failing_S',
'DB_PERF_SEL_PreZ_Samples_failing_Z',
'DB_PERF_SEL_PreZ_Samples_passing_Z',
'DB_PERF_SEL_RMI_rd_s_32byte_req',
'DB_PERF_SEL_RMI_rd_s_32byte_ret',
'DB_PERF_SEL_RMI_rd_tile_32byte_req',
'DB_PERF_SEL_RMI_rd_tile_32byte_ret',
'DB_PERF_SEL_RMI_rd_z_32byte_req',
'DB_PERF_SEL_RMI_rd_z_32byte_ret',
'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack',
'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req',
'DB_PERF_SEL_RMI_wr_s_32byte_ack',
'DB_PERF_SEL_RMI_wr_s_32byte_req',
'DB_PERF_SEL_RMI_wr_tile_32byte_ack',
'DB_PERF_SEL_RMI_wr_tile_32byte_req',
'DB_PERF_SEL_RMI_wr_z_32byte_ack',
'DB_PERF_SEL_RMI_wr_z_32byte_req', 'DB_PERF_SEL_SC_DB_quad_busy',
'DB_PERF_SEL_SC_DB_quad_killed_tiles',
'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_quads',
'DB_PERF_SEL_SC_DB_quad_quads_pipe0',
'DB_PERF_SEL_SC_DB_quad_quads_pipe1',
'DB_PERF_SEL_SC_DB_quad_sends', 'DB_PERF_SEL_SC_DB_quad_squads',
'DB_PERF_SEL_SC_DB_quad_tiles', 'DB_PERF_SEL_SC_DB_quad_vrs_1x1',
'DB_PERF_SEL_SC_DB_quad_vrs_1x2',
'DB_PERF_SEL_SC_DB_quad_vrs_2x1',
'DB_PERF_SEL_SC_DB_quad_vrs_2x2',
'DB_PERF_SEL_SC_DB_quad_vrs_2x_ssaa',
'DB_PERF_SEL_SC_DB_quad_vrs_4x_ssaa',
'DB_PERF_SEL_SC_DB_quad_vrs_8x_ssaa',
'DB_PERF_SEL_SC_DB_tile_backface', 'DB_PERF_SEL_SC_DB_tile_busy',
'DB_PERF_SEL_SC_DB_tile_covered', 'DB_PERF_SEL_SC_DB_tile_events',
'DB_PERF_SEL_SC_DB_tile_sends', 'DB_PERF_SEL_SC_DB_tile_stalls',
'DB_PERF_SEL_SC_DB_tile_tiles',
'DB_PERF_SEL_SC_DB_tile_tiles_pipe0',
'DB_PERF_SEL_SC_DB_tile_tiles_pipe1',
'DB_PERF_SEL_SC_DB_wave_busy',
'DB_PERF_SEL_SC_DB_wave_id_wrapped',
'DB_PERF_SEL_SC_DB_wave_quads', 'DB_PERF_SEL_SC_DB_wave_sends',
'DB_PERF_SEL_SH_quads_outstanding_sum',
'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled',
'DB_PERF_SEL_SX_DB_quad_all_pixels_killed',
'DB_PERF_SEL_SX_DB_quad_busy',
'DB_PERF_SEL_SX_DB_quad_double_format',
'DB_PERF_SEL_SX_DB_quad_export_quads',
'DB_PERF_SEL_SX_DB_quad_exports',
'DB_PERF_SEL_SX_DB_quad_fast_format',
'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read',
'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads',
'DB_PERF_SEL_SX_DB_quad_sends',
'DB_PERF_SEL_SX_DB_quad_slow_format',
'DB_PERF_SEL_SX_DB_quad_stalls', 'DB_PERF_SEL_SX_DB_quad_waves',
'DB_PERF_SEL_Stencil_Cache_flushes',
'DB_PERF_SEL_Stencil_Cache_frees',
'DB_PERF_SEL_Stencil_Cache_hits',
'DB_PERF_SEL_Stencil_Cache_misses',
'DB_PERF_SEL_Stencil_Cache_starves',
'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits',
'DB_PERF_SEL_Tile_Cache_mem_return_starve',
'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves',
'DB_PERF_SEL_Tile_Cache_surface_stall',
'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes',
'DB_PERF_SEL_Z_Cache_pmask_hits',
'DB_PERF_SEL_Z_Cache_pmask_misses',
'DB_PERF_SEL_Z_Cache_pmask_starves',
'DB_PERF_SEL_Z_Cache_separate_Z_flushes',
'DB_PERF_SEL_Z_Cache_separate_Z_hits',
'DB_PERF_SEL_Z_Cache_separate_Z_misses',
'DB_PERF_SEL_Z_Cache_separate_Z_starves',
'DB_PERF_SEL_clock_main_active',
'DB_PERF_SEL_clock_mem_export_active',
'DB_PERF_SEL_clock_reg_active',
'DB_PERF_SEL_cs_events_pws_enable',
'DB_PERF_SEL_depth_bounds_tile_culled', 'DB_PERF_SEL_di_dt_stall',
'DB_PERF_SEL_dk_squad_busy', 'DB_PERF_SEL_dk_squad_sends',
'DB_PERF_SEL_dk_squad_stalls', 'DB_PERF_SEL_dk_tile_busy',
'DB_PERF_SEL_dk_tile_quad_starves', 'DB_PERF_SEL_dk_tile_sends',
'DB_PERF_SEL_dk_tile_stalls', 'DB_PERF_SEL_dkg_tile_rate_tile',
'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall',
'DB_PERF_SEL_dtt_sm_slot_stall',
'DB_PERF_SEL_earlyZ_waiting_for_postZ_done',
'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward',
'DB_PERF_SEL_esr_eot_fwd_holding_squad',
'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall',
'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_src_in_sends',
'DB_PERF_SEL_esr_ps_src_in_squads',
'DB_PERF_SEL_esr_ps_src_in_squads_unrolled',
'DB_PERF_SEL_esr_ps_src_in_stall',
'DB_PERF_SEL_esr_ps_src_in_tile_rate',
'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled',
'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate',
'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_ps_vic_busy',
'DB_PERF_SEL_esr_ps_vic_stall',
'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut',
'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut',
'DB_PERF_SEL_esr_psi_vic_tile_rate',
'DB_PERF_SEL_esr_sqq_zi_busy', 'DB_PERF_SEL_esr_sqq_zi_stall',
'DB_PERF_SEL_esr_vic_footprint_match_1x2',
'DB_PERF_SEL_esr_vic_footprint_match_2x1',
'DB_PERF_SEL_esr_vic_footprint_match_2x2',
'DB_PERF_SEL_esr_vic_sqq_busy', 'DB_PERF_SEL_esr_vic_sqq_stall',
'DB_PERF_SEL_etr_out_busy', 'DB_PERF_SEL_etr_out_esr_stall',
'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall',
'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane',
'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane',
'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane',
'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane',
'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane',
'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane',
'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane',
'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane',
'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed',
'DB_PERF_SEL_flush_compressed_stencil',
'DB_PERF_SEL_flush_expanded_stencil',
'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4',
'DB_PERF_SEL_flush_single_stencil',
'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1',
'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1',
'DB_PERF_SEL_his_tile_culled', 'DB_PERF_SEL_hiz_tc_read_starved',
'DB_PERF_SEL_hiz_tc_write_stall', 'DB_PERF_SEL_hiz_tile_culled',
'DB_PERF_SEL_mi_quad_rd_outstanding_sum',
'DB_PERF_SEL_mi_quad_wr_outstanding_sum',
'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall',
'DB_PERF_SEL_mi_tile_rd_outstanding_sum',
'DB_PERF_SEL_mi_tile_wr_outstanding_sum',
'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall',
'DB_PERF_SEL_noz_waiting_for_postz_done',
'DB_PERF_SEL_planes_flushed',
'DB_PERF_SEL_postz_ps_invoked_pixel_cnt',
'DB_PERF_SEL_postzl_full_launch',
'DB_PERF_SEL_postzl_partial_launch',
'DB_PERF_SEL_postzl_partial_waiting',
'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall',
'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall',
'DB_PERF_SEL_postzl_src_in_sends',
'DB_PERF_SEL_postzl_src_in_squads',
'DB_PERF_SEL_postzl_src_in_squads_unrolled',
'DB_PERF_SEL_postzl_src_in_stall',
'DB_PERF_SEL_postzl_src_in_tile_rate',
'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled',
'DB_PERF_SEL_postzl_src_out_stall',
'DB_PERF_SEL_postzl_tile_init_stall',
'DB_PERF_SEL_postzl_tile_mem_stall',
'DB_PERF_SEL_prez_ps_invoked_pixel_cnt',
'DB_PERF_SEL_prezl_src_in_sends',
'DB_PERF_SEL_prezl_src_in_squads',
'DB_PERF_SEL_prezl_src_in_squads_unrolled',
'DB_PERF_SEL_prezl_src_in_stall',
'DB_PERF_SEL_prezl_src_in_tile_rate',
'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled',
'DB_PERF_SEL_prezl_src_out_stall',
'DB_PERF_SEL_prezl_tile_init_stall',
'DB_PERF_SEL_prezl_tile_mem_stall',
'DB_PERF_SEL_ps_events_pws_enable',
'DB_PERF_SEL_pws_liveness_stall_dtt_tag',
'DB_PERF_SEL_pws_liveness_stall_tcp_cache_mgr',
'DB_PERF_SEL_pws_stall', 'DB_PERF_SEL_qc_busy',
'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall',
'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ',
'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc',
'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy',
'DB_PERF_SEL_quad_rd_mi_stall',
'DB_PERF_SEL_quad_rd_mi_stall_unc', 'DB_PERF_SEL_quad_rd_panic',
'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends',
'DB_PERF_SEL_quad_rd_sends_unc', 'DB_PERF_SEL_quad_rd_tag_stall',
'DB_PERF_SEL_quad_rdret_busy', 'DB_PERF_SEL_quad_rdret_sends',
'DB_PERF_SEL_quad_wr_acks', 'DB_PERF_SEL_quad_wr_busy',
'DB_PERF_SEL_quad_wr_coherency_stall',
'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends',
'DB_PERF_SEL_reZ_waiting_for_postZ_done',
'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop',
'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start',
'DB_PERF_SEL_tcp_dispatcher_flushes',
'DB_PERF_SEL_tcp_dispatcher_reads',
'DB_PERF_SEL_tcp_prefetcher_flushes',
'DB_PERF_SEL_tcp_prefetcher_reads',
'DB_PERF_SEL_tcp_preloader_flushes',
'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends',
'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends',
'DB_PERF_SEL_tiles_compressed_to_decompressed',
'DB_PERF_SEL_tiles_decomp_on_expclear',
'DB_PERF_SEL_tiles_s_clear_on_expclear',
'DB_PERF_SEL_tiles_stencil_fully_summarized',
'DB_PERF_SEL_tiles_z_clear_on_expclear',
'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy',
'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events',
'DB_PERF_SEL_tl_expand_squads',
'DB_PERF_SEL_tl_flush_expand_squads',
'DB_PERF_SEL_tl_in_fast_z_stall',
'DB_PERF_SEL_tl_in_single_stencil_expand_stall',
'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads',
'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads',
'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads',
'DB_PERF_SEL_tl_preZ_squads',
'DB_PERF_SEL_tl_stencil_locked_stall',
'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads',
'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall',
'DB_PERF_SEL_tl_z_fetch_stall',
'DB_PERF_SEL_ts_events_pws_enable',
'DB_PERF_SEL_ts_tc_update_stall',
'DB_PERF_SEL_tsc_insert_summarize_stall',
'DB_PERF_SEL_unmapped_z_tile_culled',
'DB_PERF_SEL_zf_plane_multicycle', 'DCCG_AUDIO_DTO0_SOURCE_SEL',
'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0',
'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1',
'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2',
'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3',
'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED',
'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0',
'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', 'DCCG_AUDIO_DTO_SEL',
'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1',
'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO',
'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP',
'DCCG_AUDIO_DTO_USE_512FBR_DTO',
'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DBG_BLOCK_SEL',
'DCCG_DBG_BLOCK_SEL_DCCG', 'DCCG_DBG_BLOCK_SEL_PMON',
'DCCG_DBG_BLOCK_SEL_PMON2', 'DCCG_DBG_EN', 'DCCG_DBG_EN_DISABLE',
'DCCG_DBG_EN_ENABLE', 'DCCG_DEEP_COLOR_CNTL',
'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO',
'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE',
'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN',
'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET',
'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP',
'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION',
'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_MODE_HSYNC',
'DCCG_PERF_MODE_HSYNC_NOOP', 'DCCG_PERF_MODE_HSYNC_START',
'DCCG_PERF_MODE_VSYNC', 'DCCG_PERF_MODE_VSYNC_NOOP',
'DCCG_PERF_MODE_VSYNC_START', 'DCCG_PERF_OTG_SELECT',
'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START',
'DCCG_PERF_SEL_OTG0', 'DCCG_PERF_SEL_OTG1', 'DCCG_PERF_SEL_OTG2',
'DCCG_PERF_SEL_OTG3', 'DCCG_PERF_SEL_RESERVED',
'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1',
'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2',
'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE',
'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE',
'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE',
'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP',
'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP',
'DCHUBBUB_MEM_POWER_MODE_OFF',
'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', 'DCHUBBUB_MEM_PWR_DIS_MODE',
'DCHUBBUB_MEM_PWR_MODE', 'DCIOCHIP_AUX_ALL_PWR_OK',
'DCIOCHIP_AUX_ALL_PWR_OK_0', 'DCIOCHIP_AUX_ALL_PWR_OK_1',
'DCIOCHIP_AUX_CSEL0P9', 'DCIOCHIP_AUX_CSEL1P1',
'DCIOCHIP_AUX_CSEL_DEC0P9', 'DCIOCHIP_AUX_CSEL_DEC1P0',
'DCIOCHIP_AUX_CSEL_INC1P0', 'DCIOCHIP_AUX_CSEL_INC1P1',
'DCIOCHIP_AUX_FALLSLEWSEL', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0',
'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW',
'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_HYS_TUNE',
'DCIOCHIP_AUX_HYS_TUNE_0', 'DCIOCHIP_AUX_HYS_TUNE_1',
'DCIOCHIP_AUX_HYS_TUNE_2', 'DCIOCHIP_AUX_HYS_TUNE_3',
'DCIOCHIP_AUX_RECEIVER_SEL', 'DCIOCHIP_AUX_RECEIVER_SEL_0',
'DCIOCHIP_AUX_RECEIVER_SEL_1', 'DCIOCHIP_AUX_RECEIVER_SEL_2',
'DCIOCHIP_AUX_RECEIVER_SEL_3', 'DCIOCHIP_AUX_RSEL0P9',
'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9',
'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0',
'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL',
'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS',
'DCIOCHIP_AUX_VOD_TUNE', 'DCIOCHIP_AUX_VOD_TUNE_0',
'DCIOCHIP_AUX_VOD_TUNE_1', 'DCIOCHIP_AUX_VOD_TUNE_2',
'DCIOCHIP_AUX_VOD_TUNE_3', 'DCIOCHIP_GPIO_MASK_EN',
'DCIOCHIP_GPIO_MASK_EN_HARDWARE',
'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL',
'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED',
'DCIOCHIP_I2C_COMPSEL', 'DCIOCHIP_I2C_FALLSLEWSEL',
'DCIOCHIP_I2C_FALLSLEWSEL_00', 'DCIOCHIP_I2C_FALLSLEWSEL_01',
'DCIOCHIP_I2C_FALLSLEWSEL_10', 'DCIOCHIP_I2C_FALLSLEWSEL_11',
'DCIOCHIP_I2C_RECEIVER_SEL', 'DCIOCHIP_I2C_RECEIVER_SEL_0',
'DCIOCHIP_I2C_RECEIVER_SEL_1', 'DCIOCHIP_I2C_RECEIVER_SEL_2',
'DCIOCHIP_I2C_RECEIVER_SEL_3', 'DCIOCHIP_I2C_REC_COMPARATOR',
'DCIOCHIP_I2C_REC_SCHMIT', 'DCIOCHIP_I2C_VPH_1V2_EN',
'DCIOCHIP_I2C_VPH_1V2_EN_0', 'DCIOCHIP_I2C_VPH_1V2_EN_1',
'DCIOCHIP_INVERT', 'DCIOCHIP_MASK', 'DCIOCHIP_MASK_DISABLE',
'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE',
'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN',
'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW',
'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT',
'DCIOCHIP_REF_27_SRC_SEL',
'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS',
'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER',
'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS',
'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6',
'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL',
'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS',
'DCIO_DBG_ASYNC_4BIT_SEL', 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8',
'DCIO_DBG_ASYNC_4BIT_SEL_15TO12',
'DCIO_DBG_ASYNC_4BIT_SEL_19TO16',
'DCIO_DBG_ASYNC_4BIT_SEL_23TO20',
'DCIO_DBG_ASYNC_4BIT_SEL_27TO24',
'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0',
'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 'DCIO_DBG_ASYNC_BLOCK_SEL',
'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO',
'DCIO_DBG_ASYNC_BLOCK_SEL_DIO',
'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', 'DCIO_DCRXPHY_SOFT_RESET',
'DCIO_DCRXPHY_SOFT_RESET_ASSERT',
'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', 'DCIO_DC_GENERICA_SEL',
'DCIO_DC_GENERICB_SEL',
'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL',
'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL',
'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL',
'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL',
'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE',
'DCIO_DC_GPU_TIMER_READ_SELECT',
'DCIO_DC_GPU_TIMER_START_POSITION',
'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL',
'DCIO_DIO_EXT_VSYNC_MASK', 'DCIO_DIO_OTG_EXT_VSYNC_MUX',
'DCIO_DISPCLK_R_DCIO_GATE_DISABLE',
'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE',
'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK',
'DCIO_DPCS_INTERRUPT_TYPE',
'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED',
'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED',
'DCIO_DPRX_LOOPBACK_ENABLE_LOOP',
'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 'DCIO_EXT_VSYNC_MASK_NONE',
'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', 'DCIO_EXT_VSYNC_MASK_PIPE0',
'DCIO_EXT_VSYNC_MASK_PIPE1', 'DCIO_EXT_VSYNC_MASK_PIPE2',
'DCIO_EXT_VSYNC_MASK_PIPE3', 'DCIO_EXT_VSYNC_MASK_PIPE4',
'DCIO_EXT_VSYNC_MASK_PIPE5', 'DCIO_EXT_VSYNC_MUX_GENERICB',
'DCIO_EXT_VSYNC_MUX_OTG0', 'DCIO_EXT_VSYNC_MUX_OTG1',
'DCIO_EXT_VSYNC_MUX_OTG2', 'DCIO_EXT_VSYNC_MUX_OTG3',
'DCIO_EXT_VSYNC_MUX_OTG4', 'DCIO_EXT_VSYNC_MUX_OTG5',
'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', 'DCIO_GENERICA_SEL_GENERICA_DCCG',
'DCIO_GENERICA_SEL_STEREOSYNC', 'DCIO_GENERICA_SEL_SYNCEN',
'DCIO_GENERICB_SEL_GENERICB_DCCG', 'DCIO_GENERICB_SEL_STEREOSYNC',
'DCIO_GENERICB_SEL_SYNCEN', 'DCIO_GENLK_CLK_GSL_MASK',
'DCIO_GENLK_CLK_GSL_MASK_NO', 'DCIO_GENLK_CLK_GSL_MASK_STEREO',
'DCIO_GENLK_CLK_GSL_MASK_TIMING',
'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE',
'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1',
'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2',
'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3',
'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO',
'DCIO_GENLK_VSYNC_GSL_MASK_STEREO',
'DCIO_GENLK_VSYNC_GSL_MASK_TIMING',
'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP',
'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM',
'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE',
'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP',
'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM',
'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE',
'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37',
'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29',
'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31',
'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35',
'DCIO_GSL_SEL', 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1',
'DCIO_GSL_SEL_GROUP_2', 'DCIO_PHY_HPO_ENC_SRC_SEL',
'DCIO_SWAPLOCK_A_GSL_MASK', 'DCIO_SWAPLOCK_A_GSL_MASK_NO',
'DCIO_SWAPLOCK_A_GSL_MASK_STEREO',
'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK',
'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO',
'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK',
'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SOCCLK',
'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK',
'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK',
'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK',
'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK',
'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK',
'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK',
'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK',
'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED',
'DCIO_UNIPHY_CHANNEL_NO_INVERSION',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL',
'DCIO_UNIPHY_IMPCAL_SEL_BINARY',
'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE',
'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT',
'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK',
'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW',
'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED',
'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED',
'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW',
'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX1',
'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX2',
'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX3',
'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX4',
'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX5',
'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX6',
'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_P',
'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_R',
'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK0',
'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK1',
'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK2',
'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK3',
'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK4',
'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK5',
'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK6',
'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK7',
'DCOH_TEST_CLOCK_MUX_SELECT_ENUM',
'DCOH_TEST_CLOCK_MUX_SELECT_PHYASYMCLK',
'DCOH_TEST_CLOCK_MUX_SELECT_PHYBSYMCLK',
'DCOH_TEST_CLOCK_MUX_SELECT_PHYCSYMCLK',
'DCOH_TEST_CLOCK_MUX_SELECT_PHYDSYMCLK',
'DCOH_TEST_CLOCK_MUX_SELECT_PHYESYMCLK',
'DCOH_TEST_CLOCK_MUX_SELECT_PHYFSYMCLK',
'DCOH_TEST_CLOCK_MUX_SELECT_PHYGSYMCLK',
'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX1',
'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX2',
'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX3',
'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX4',
'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX5',
'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX6',
'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_P',
'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_R',
'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM',
'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_DISABLED',
'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_ENABLED',
'DCOH_TOP_ENABLE_ENUM', 'DCOH_TOP_ENABLE_ENUM_DISABLED',
'DCOH_TOP_ENABLE_ENUM_ENABLED', 'DC_DMCUB_INT_TYPE',
'DC_DMCUB_TIMER_WINDOW', 'DC_MEM_GLOBAL_PWR_REQ_DIS',
'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE',
'DC_SMU_INTERRUPT_ENABLE', 'DDID_VMID_CNTL', 'DDID_VMID_PIPE',
'DECERR', 'DENORM_TRUNCATE', 'DETILE_BUFFER_PACKER_ENABLE',
'DETILE_BUFFER_PACKER_IS_DISABLE',
'DETILE_BUFFER_PACKER_IS_ENABLE', 'DFQ_MIN_FREE_ENTRIES',
'DFQ_MIN_FREE_ENTRIES_0', 'DFQ_MIN_FREE_ENTRIES_1',
'DFQ_MIN_FREE_ENTRIES_2', 'DFQ_MIN_FREE_ENTRIES_3',
'DFQ_MIN_FREE_ENTRIES_4', 'DFQ_MIN_FREE_ENTRIES_5',
'DFQ_MIN_FREE_ENTRIES_6', 'DFQ_MIN_FREE_ENTRIES_7',
'DFQ_NUM_ENTRIES', 'DFQ_NUM_ENTRIES_0', 'DFQ_NUM_ENTRIES_1',
'DFQ_NUM_ENTRIES_2', 'DFQ_NUM_ENTRIES_3', 'DFQ_NUM_ENTRIES_4',
'DFQ_NUM_ENTRIES_5', 'DFQ_NUM_ENTRIES_6', 'DFQ_NUM_ENTRIES_7',
'DFQ_NUM_ENTRIES_8', 'DFQ_SIZE', 'DFQ_SIZE_0', 'DFQ_SIZE_1',
'DFQ_SIZE_2', 'DFQ_SIZE_3', 'DFQ_SIZE_4', 'DFQ_SIZE_5',
'DFQ_SIZE_6', 'DFQ_SIZE_7', 'DIFFERENT_RGB',
'DIG_10BIT_TEST_PATTERN', 'DIG_ALTERNATING_TEST_PATTERN',
'DIG_BE_CNTL_HPD1', 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3',
'DIG_BE_CNTL_HPD4', 'DIG_BE_CNTL_HPD_SELECT', 'DIG_BE_CNTL_MODE',
'DIG_BE_CNTL_NO_HPD', 'DIG_BE_DP_MST_MODE', 'DIG_BE_DP_SST_MODE',
'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', 'DIG_BE_RESERVED3',
'DIG_BE_RESERVED4', 'DIG_BE_TMDS_DVI_MODE',
'DIG_BE_TMDS_HDMI_MODE', 'DIG_DIGITAL_BYPASS_ENABLE',
'DIG_DIGITAL_BYPASS_OFF', 'DIG_DIGITAL_BYPASS_ON',
'DIG_DIGITAL_BYPASS_SEL', 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB',
'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB',
'DIG_DIGITAL_BYPASS_SEL_36BPP',
'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB',
'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB',
'DIG_DIGITAL_BYPASS_SEL_ALPHA', 'DIG_DIGITAL_BYPASS_SEL_BYPASS',
'DIG_FE_CNTL_SOURCE_SELECT', 'DIG_FE_CNTL_STEREOSYNC_SELECT',
'DIG_FE_SOURCE_FROM_OTG0', 'DIG_FE_SOURCE_FROM_OTG1',
'DIG_FE_SOURCE_FROM_OTG2', 'DIG_FE_SOURCE_FROM_OTG3',
'DIG_FE_SOURCE_RESERVED', 'DIG_FE_STEREOSYNC_FROM_OTG0',
'DIG_FE_STEREOSYNC_FROM_OTG1', 'DIG_FE_STEREOSYNC_FROM_OTG2',
'DIG_FE_STEREOSYNC_FROM_OTG3', 'DIG_FE_STEREOSYNC_RESERVED',
'DIG_FIFO_1_PIX_PER_CYCLE', 'DIG_FIFO_2_PIX_PER_CYCLE',
'DIG_FIFO_4_PIX_PER_CYCLE', 'DIG_FIFO_8_PIX_PER_CYCLE',
'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX',
'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL',
'DIG_FIFO_FORCE_RECAL_AVERAGE',
'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL',
'DIG_FIFO_FORCE_RECOMP_MINMAX',
'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE',
'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_NO_ERROR_OCCURRED',
'DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE', 'DIG_FIFO_OVERFLOW_OCCURRED',
'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR', 'DIG_FIFO_READ_CLOCK_SRC',
'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG',
'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE',
'DIG_FIFO_UNDERFLOW_OCCURRED', 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL',
'DIG_FIFO_USE_OVERWRITE_LEVEL', 'DIG_IN_DEBUG_MODE',
'DIG_IN_NORMAL_OPERATION', 'DIG_MODE',
'DIG_OUTPUT_CRC_CNTL_LINK_SEL', 'DIG_OUTPUT_CRC_DATA_SEL',
'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', 'DIG_OUTPUT_CRC_FOR_AUDIO',
'DIG_OUTPUT_CRC_FOR_FULLFRAME', 'DIG_OUTPUT_CRC_FOR_VBI',
'DIG_OUTPUT_CRC_ON_LINK0', 'DIG_OUTPUT_CRC_ON_LINK1',
'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED',
'DIG_RANDOM_PATTERN_SEED_RAN_PAT',
'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS',
'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH',
'DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET',
'DIG_STREAM_MAPPER_LINK0', 'DIG_STREAM_MAPPER_LINK1',
'DIG_STREAM_MAPPER_LINK2', 'DIG_STREAM_MAPPER_LINK3',
'DIG_STREAM_MAPPER_LINK6',
'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG',
'DIG_TEST_PATTERN_EXTERNAL_RESET_EN',
'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE',
'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL',
'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM',
'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN',
'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET',
'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', 'DIG_UPDATE_EYE_SEL_BOTH',
'DIG_UPDATE_EYE_SEL_LEFT', 'DIG_UPDATE_EYE_SEL_RIGHT',
'DIG_UPDATE_FIELD_SEL_BOTH', 'DIG_UPDATE_FIELD_SEL_BOTTOM',
'DIG_UPDATE_FIELD_SEL_RESERVED', 'DIG_UPDATE_FIELD_SEL_TOP',
'DIOMEM_DISABLE_MEM_PWR_CTRL', 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN',
'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE',
'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN',
'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE',
'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', 'DIOMEM_ENABLE_MEM_PWR_CTRL',
'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', 'DIOMEM_FORCE_LIGHT_SLEEP_REQ',
'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST',
'DIOMEM_FORCE_SHUT_DOWN_REQUEST', 'DIOMEM_NO_FORCE_REQ',
'DIOMEM_NO_FORCE_REQUEST', 'DIOMEM_PWR_DIS_CTRL',
'DIOMEM_PWR_FORCE_CTRL', 'DIOMEM_PWR_FORCE_CTRL2',
'DIOMEM_PWR_SEL_CTRL', 'DIOMEM_PWR_SEL_CTRL2',
'DIO_CLOCK_GATING_DIS', 'DIO_CLOCK_GATING_DISABLE',
'DIO_CLOCK_GATING_EN', 'DIO_DBG_BLOCK_SEL',
'DIO_DBG_BLOCK_SEL_AUX0', 'DIO_DBG_BLOCK_SEL_AUX1',
'DIO_DBG_BLOCK_SEL_AUX2', 'DIO_DBG_BLOCK_SEL_AUX3',
'DIO_DBG_BLOCK_SEL_DIGA', 'DIO_DBG_BLOCK_SEL_DIGB',
'DIO_DBG_BLOCK_SEL_DIGC', 'DIO_DBG_BLOCK_SEL_DIGD',
'DIO_DBG_BLOCK_SEL_DIGFE_A', 'DIO_DBG_BLOCK_SEL_DIGFE_B',
'DIO_DBG_BLOCK_SEL_DIGFE_C', 'DIO_DBG_BLOCK_SEL_DIGFE_D',
'DIO_DBG_BLOCK_SEL_DIO', 'DIO_DBG_BLOCK_SEL_DPA',
'DIO_DBG_BLOCK_SEL_DPB', 'DIO_DBG_BLOCK_SEL_DPC',
'DIO_DBG_BLOCK_SEL_DPD', 'DIO_DBG_BLOCK_SEL_DPFE_A',
'DIO_DBG_BLOCK_SEL_DPFE_B', 'DIO_DBG_BLOCK_SEL_DPFE_C',
'DIO_DBG_BLOCK_SEL_DPFE_D', 'DIO_DBG_BLOCK_SEL_PERFMON_DIO',
'DIO_DBG_BLOCK_SEL_RESERVED', 'DIO_FIFO_ERROR',
'DIO_FIFO_ERROR_00', 'DIO_FIFO_ERROR_01', 'DIO_FIFO_ERROR_10',
'DIO_FIFO_ERROR_11',
'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE',
'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL',
'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', 'DISABLE_CLOCK_GATING',
'DISABLE_CLOCK_GATING_IN_DCO', 'DISABLE_DEBUG',
'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', 'DISABLE_PWL',
'DISABLE_TF0_OPT', 'DISABLE_TF1_OPT', 'DISABLE_THE_FEATURE',
'DISABLE_THE_INTERRUPT', 'DISPCLK_CHG_FWD_CORR_DISABLE',
'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING',
'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING',
'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE',
'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DIVISOR_BY1',
'DIVISOR_BY2_RESERVED', 'DIVISOR_BY3', 'DIVISOR_BY4_RESERVED',
'DIVISOR_BY5_RESERVED', 'DIVISOR_BY6_RESERVED',
'DIVISOR_BY7_RESERVED', 'DIVISOR_BY8_RESERVED', 'DIV_2', 'DIV_4',
'DIV_8', 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT',
'DI_INDEX_SIZE_8_BIT', 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST',
'DI_PT_LINELIST_ADJ', 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP',
'DI_PT_LINESTRIP_ADJ', 'DI_PT_NONE', 'DI_PT_PATCH',
'DI_PT_POINTLIST', 'DI_PT_POLYGON', 'DI_PT_QUADLIST',
'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', 'DI_PT_TRIFAN',
'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', 'DI_PT_TRISTRIP',
'DI_PT_TRISTRIP_ADJ', 'DI_PT_UNUSED_1', 'DI_PT_UNUSED_3',
'DI_PT_UNUSED_4', 'DI_PT_UNUSED_5', 'DI_SRC_SEL_AUTO_INDEX',
'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', 'DI_SRC_SEL_RESERVED',
'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE',
'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE',
'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE',
'DMDATA_CLEAR_UNDERFLOW_STATUS', 'DMDATA_DONE',
'DMDATA_DONT_CLEAR', 'DMDATA_HARDWARE_UPDATE_MODE', 'DMDATA_MODE',
'DMDATA_NOT_SENT_TO_DIG', 'DMDATA_NOT_UNDERFLOW',
'DMDATA_NOT_UPDATED', 'DMDATA_QOS_LEVEL_FROM_SOFTWARE',
'DMDATA_QOS_LEVEL_FROM_TTU', 'DMDATA_QOS_MODE', 'DMDATA_REPEAT',
'DMDATA_SENT_TO_DIG', 'DMDATA_SOFTWARE_UPDATE_MODE',
'DMDATA_UNDERFLOW', 'DMDATA_UNDERFLOWED',
'DMDATA_UNDERFLOW_CLEAR', 'DMDATA_UPDATED',
'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES',
'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', 'DMDATA_VM_DONE',
'DMDATA_VM_IS_DONE', 'DMDATA_VM_IS_NOT_DONE',
'DMDATA_WAS_UPDATED', 'DME_MEM_DISABLE_MEM_PWR_CTRL',
'DME_MEM_ENABLE_MEM_PWR_CTRL', 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST',
'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST',
'DME_MEM_FORCE_SHUT_DOWN_REQUEST', 'DME_MEM_NO_FORCE_REQUEST',
'DME_MEM_POWER_STATE_ENUM', 'DME_MEM_POWER_STATE_ENUM_DS',
'DME_MEM_POWER_STATE_ENUM_LS', 'DME_MEM_POWER_STATE_ENUM_ON',
'DME_MEM_POWER_STATE_ENUM_SD', 'DME_MEM_PWR_DIS_CTRL',
'DME_MEM_PWR_FORCE_CTRL', 'DMU_CLOCK_ON', 'DMU_CLOCK_STATUS_OFF',
'DMU_CLOCK_STATUS_ON', 'DMU_DC_GPU_TIMER_READ_SELECT',
'DMU_DC_GPU_TIMER_START_POSITION',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71',
'DMU_GPU_TIMER_START_0_END_27', 'DMU_GPU_TIMER_START_10_END_37',
'DMU_GPU_TIMER_START_1_END_28', 'DMU_GPU_TIMER_START_2_END_29',
'DMU_GPU_TIMER_START_3_END_30', 'DMU_GPU_TIMER_START_4_END_31',
'DMU_GPU_TIMER_START_6_END_33', 'DMU_GPU_TIMER_START_8_END_35',
'DONUTS', 'DOUT_I2C_ACK', 'DOUT_I2C_ACK_TO_CLEAN',
'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER',
'DOUT_I2C_ARBITRATION_ABORT_XFER',
'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG',
'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG',
'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG',
'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER',
'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO',
'DOUT_I2C_ARBITRATION_SW_PRIORITY',
'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED',
'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED',
'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH',
'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL',
'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED',
'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED',
'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ',
'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ',
'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ',
'DOUT_I2C_CONTROL_DBG_REF_SEL', 'DOUT_I2C_CONTROL_DDC_SELECT',
'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', 'DOUT_I2C_CONTROL_GO',
'DOUT_I2C_CONTROL_NORMAL_DEBUG',
'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER',
'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS',
'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER',
'DOUT_I2C_CONTROL_RESET_SW_STATUS',
'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2',
'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4',
'DOUT_I2C_CONTROL_SELECT_DDCVGA', 'DOUT_I2C_CONTROL_SEND_RESET',
'DOUT_I2C_CONTROL_SEND_RESET_LENGTH',
'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER',
'DOUT_I2C_CONTROL_STOP_TRANSFER',
'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0',
'DOUT_I2C_CONTROL_TRANS0_TRANS1',
'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2',
'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3',
'DOUT_I2C_CONTROL_TRANSACTION_COUNT',
'DOUT_I2C_CONTROL__NOT_SEND_RESET',
'DOUT_I2C_CONTROL__SEND_RESET',
'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10',
'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9',
'DOUT_I2C_DATA_INDEX_WRITE', 'DOUT_I2C_DATA__INDEX_WRITE',
'DOUT_I2C_DATA__NOT_INDEX_WRITE',
'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR',
'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL',
'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT',
'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT',
'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE',
'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL',
'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA',
'DOUT_I2C_DDC_SPEED_THRESHOLD',
'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO',
'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE',
'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE',
'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE',
'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET',
'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION',
'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION',
'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE',
'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL',
'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE',
'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS',
'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS',
'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DPHY_8B10B_CUR_DISP',
'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO',
'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET',
'DPHY_8B10B_RESETET', 'DPHY_ATEST_LANE0_PRBS_PATTERN',
'DPHY_ATEST_LANE0_REG_PATTERN', 'DPHY_ATEST_LANE1_PRBS_PATTERN',
'DPHY_ATEST_LANE1_REG_PATTERN', 'DPHY_ATEST_LANE2_PRBS_PATTERN',
'DPHY_ATEST_LANE2_REG_PATTERN', 'DPHY_ATEST_LANE3_PRBS_PATTERN',
'DPHY_ATEST_LANE3_REG_PATTERN', 'DPHY_ATEST_SEL_LANE0',
'DPHY_ATEST_SEL_LANE1', 'DPHY_ATEST_SEL_LANE2',
'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', 'DPHY_CRC_CONTINUOUS',
'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', 'DPHY_CRC_EN',
'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', 'DPHY_CRC_LANE0_SELECTED',
'DPHY_CRC_LANE1_SELECTED', 'DPHY_CRC_LANE2_SELECTED',
'DPHY_CRC_LANE3_SELECTED', 'DPHY_CRC_MST_PHASE_ERROR_ACK',
'DPHY_CRC_MST_PHASE_ERROR_ACKED',
'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT',
'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD',
'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT',
'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0',
'DPHY_FEC_ACTIVE', 'DPHY_FEC_DISABLED', 'DPHY_FEC_ENABLE',
'DPHY_FEC_ENABLED', 'DPHY_FEC_NOT_ACTIVE', 'DPHY_FEC_READY',
'DPHY_FEC_READY_DIS', 'DPHY_FEC_READY_EN',
'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START',
'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW',
'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED',
'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN',
'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL',
'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SKEW_BYPASS',
'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM',
'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET',
'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET',
'DPHY_SW_FAST_TRAINING_NOT_STARTED',
'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED',
'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2',
'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4',
'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL',
'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL',
'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL',
'DPTE_GROUP_SIZE', 'DPTE_GROUP_SIZE_1024B',
'DPTE_GROUP_SIZE_128B', 'DPTE_GROUP_SIZE_2048B',
'DPTE_GROUP_SIZE_256B', 'DPTE_GROUP_SIZE_512B',
'DPTE_GROUP_SIZE_64B', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY',
'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW',
'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW',
'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS',
'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC',
'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG',
'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ',
'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG',
'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG',
'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ',
'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', 'DP_AUX_ARB_STATUS',
'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED',
'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED',
'DP_AUX_CONTROL_HPD_SEL', 'DP_AUX_CONTROL_NO_HPD_SELECTED',
'DP_AUX_CONTROL_TEST_MODE', 'DP_AUX_CONTROL_TEST_MODE_DISABLE',
'DP_AUX_CONTROL_TEST_MODE_ENABLE',
'DP_AUX_DEFINITE_ERR_REACHED_ACK',
'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START',
'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD',
'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START',
'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP',
'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START',
'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF',
'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK',
'DP_AUX_ERR_OCCURRED__NOT_ACK',
'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX',
'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ',
'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64',
'DP_AUX_IDLE', 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK',
'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK',
'DP_AUX_INT__NOT_ACK', 'DP_AUX_IN_USE_GTC', 'DP_AUX_IN_USE_LS',
'DP_AUX_IN_USE_PHYWAKE', 'DP_AUX_IN_USE_SW',
'DP_AUX_LS_UPDATE_ACK', 'DP_AUX_PHY_WAKE_HIGH_PRIORITY',
'DP_AUX_PHY_WAKE_LOW_PRIORITY', 'DP_AUX_PHY_WAKE_PRIORITY',
'DP_AUX_POTENTIAL_ERR_REACHED_ACK',
'DP_AUX_POTENTIAL_ERR_REACHED__ACK',
'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET',
'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED',
'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE',
'DP_AUX_RESET_SEQUENCE_NOT_DONE', 'DP_AUX_RX_TIMEOUT_LEN_MUL',
'DP_AUX_RX_TIMEOUT_LEN_MUL_2', 'DP_AUX_RX_TIMEOUT_LEN_MUL_4',
'DP_AUX_RX_TIMEOUT_LEN_MUL_8', 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL',
'DP_AUX_SW_CONTROL_LS_READ_TRIG',
'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG',
'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO',
'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO',
'DP_AUX_TX_PRECHARGE_LEN_MUL', 'DP_AUX_TX_PRECHARGE_LEN_MUL_2',
'DP_AUX_TX_PRECHARGE_LEN_MUL_4', 'DP_AUX_TX_PRECHARGE_LEN_MUL_8',
'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', 'DP_COMPONENT_DEPTH',
'DP_COMPONENT_DEPTH_10BPC', 'DP_COMPONENT_DEPTH_12BPC',
'DP_COMPONENT_DEPTH_16BPC', 'DP_COMPONENT_DEPTH_6BPC',
'DP_COMPONENT_DEPTH_8BPC', 'DP_COMPRESSED_PIXEL_FORMAT',
'DP_DPHY_8B10B_EXT_DISP', 'DP_DPHY_8B10B_EXT_DISP_ONE',
'DP_DPHY_8B10B_EXT_DISP_ZERO',
'DP_DPHY_FAST_TRAINING_COMPLETE_ACK',
'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED',
'DP_DPHY_FAST_TRAINING_COMPLETE_MASK',
'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED',
'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED',
'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED',
'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED',
'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN',
'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED',
'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1',
'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS',
'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE',
'DP_DPHY_SYM32_1LANE', 'DP_DPHY_SYM32_2LANE',
'DP_DPHY_SYM32_4LANE', 'DP_DPHY_SYM32_ACTIVE',
'DP_DPHY_SYM32_CRC_END_LLCP', 'DP_DPHY_SYM32_CRC_END_PS_ANY',
'DP_DPHY_SYM32_CRC_END_PS_LT_SR', 'DP_DPHY_SYM32_CRC_END_PS_ONLY',
'DP_DPHY_SYM32_CRC_START_LLCP',
'DP_DPHY_SYM32_CRC_START_PS_LT_SR',
'DP_DPHY_SYM32_CRC_START_PS_ONLY',
'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR',
'DP_DPHY_SYM32_CRC_START_TP_START',
'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER',
'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER',
'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX',
'DP_DPHY_SYM32_CRC_USE_END_EVENT',
'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', 'DP_DPHY_SYM32_DISABLE',
'DP_DPHY_SYM32_ENABLE', 'DP_DPHY_SYM32_LT_TPS1',
'DP_DPHY_SYM32_LT_TPS2', 'DP_DPHY_SYM32_NOT_RESET',
'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING',
'DP_DPHY_SYM32_OUTPUT_DPIA', 'DP_DPHY_SYM32_OUTPUT_PHY',
'DP_DPHY_SYM32_RATE_UPDATE_PENDING', 'DP_DPHY_SYM32_RESERVED',
'DP_DPHY_SYM32_RESET', 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED',
'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED',
'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE',
'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING',
'DP_DPHY_SYM32_SAT_NO_UPDATE',
'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING',
'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE',
'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING',
'DP_DPHY_SYM32_SCHEDULER_ASLEEP', 'DP_DPHY_SYM32_SCHEDULER_AWAKE',
'DP_DPHY_SYM32_SCHEDULER_OFF', 'DP_DPHY_SYM32_STATUS_ENABLED',
'DP_DPHY_SYM32_STATUS_IDLE', 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS',
'DP_DPHY_SYM32_STREAM_OVR_NONE',
'DP_DPHY_SYM32_STREAM_OVR_REPLACE',
'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL',
'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', 'DP_DPHY_SYM32_TEST',
'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11',
'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15',
'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23',
'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31',
'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7',
'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9',
'DP_DPHY_SYM32_TP_SELECT_CUSTOM', 'DP_DPHY_SYM32_TP_SELECT_PRBS',
'DP_DPHY_SYM32_TP_SELECT_SQUARE', 'DP_DPHY_SYM32_TP_SELECT_TPS1',
'DP_DPHY_SYM32_TP_SELECT_TPS2', 'DP_DSC_444_S422',
'DP_DSC_N422_N420', 'DP_DTO_DESPREAD_DISABLE',
'DP_DTO_DESPREAD_ENABLE', 'DP_DTO_DS_DISABLE',
'DP_LINK_TRAINING_ALREADY_COMPLETE', 'DP_LINK_TRAINING_COMPLETE',
'DP_LINK_TRAINING_NOT_COMPLETE', 'DP_LINK_TRAINING_SWITCH_MODE',
'DP_LINK_TRAINING_SWITCH_TO_IDLE',
'DP_LINK_TRAINING_SWITCH_TO_VIDEO', 'DP_ML_PHY_SEQ_IMMEDIATE',
'DP_ML_PHY_SEQ_LINE_NUM', 'DP_ML_PHY_SEQ_MODE',
'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE',
'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED',
'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG',
'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG',
'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER',
'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE',
'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE',
'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER',
'DP_MSO_FOUR_SSTLINK', 'DP_MSO_NUM_OF_SST_LINKS',
'DP_MSO_ONE_SSTLINK', 'DP_MSO_TWO_SSTLINK', 'DP_MST_MODE',
'DP_PIXEL_ENCODING', 'DP_PIXEL_ENCODING_COMPRESSED',
'DP_PIXEL_ENCODING_RGB_YCBCR444', 'DP_PIXEL_ENCODING_TYPE',
'DP_PIXEL_ENCODING_UNCOMPRESSED', 'DP_PIXEL_ENCODING_YCBCR420',
'DP_PIXEL_ENCODING_YCBCR422', 'DP_PIXEL_ENCODING_Y_ONLY',
'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ',
'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE',
'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED',
'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY',
'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE',
'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL',
'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG',
'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY',
'DP_SEC_GSP_SEND', 'DP_SEC_GSP_SEND_ANY_LINE',
'DP_SEC_GSP_SEND_PPS', 'DP_SEC_LINE_REFERENCE',
'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', 'DP_SEC_TIMESTAMP_MODE',
'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 'DP_SST_MODE',
'DP_STEER_1_PIX_PER_CYCLE', 'DP_STEER_2_PIX_PER_CYCLE',
'DP_STEER_4_PIX_PER_CYCLE', 'DP_STEER_8_PIX_PER_CYCLE',
'DP_STEER_OUTPUT_PIXEL_PER_CYCLE', 'DP_STEER_OVERFLOW_ACK',
'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT',
'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK',
'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK',
'DP_STREAM_ENC_DCCG', 'DP_STREAM_ENC_DISPLAY_PIPE',
'DP_STREAM_ENC_HARDWARE', 'DP_STREAM_ENC_NOT_RESET',
'DP_STREAM_ENC_NO_ERROR_OCCURRED',
'DP_STREAM_ENC_OVERFLOW_OCCURRED',
'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR',
'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT',
'DP_STREAM_ENC_PROGRAMMABLE', 'DP_STREAM_ENC_READ_CLOCK_CONTROL',
'DP_STREAM_ENC_RESET', 'DP_STREAM_ENC_RESET_CONTROL',
'DP_STREAM_ENC_STREAM_ACTIVE', 'DP_STREAM_ENC_UNDERFLOW_OCCURRED',
'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE',
'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE',
'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET',
'DP_STREAM_MAPPER_LINK0', 'DP_STREAM_MAPPER_LINK1',
'DP_STREAM_MAPPER_LINK2', 'DP_STREAM_MAPPER_LINK3',
'DP_STREAM_MAPPER_RESERVED', 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC',
'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC',
'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC',
'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC',
'DP_SYM32_ENC_COMPRESSED_FORMAT', 'DP_SYM32_ENC_CONTINUOUS_MODE',
'DP_SYM32_ENC_CRC_NOT_VALID', 'DP_SYM32_ENC_CRC_VALID',
'DP_SYM32_ENC_DISABLE', 'DP_SYM32_ENC_DP_SOF',
'DP_SYM32_ENC_ENABLE', 'DP_SYM32_ENC_GSP_DEADLINE_MISSED',
'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED',
'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128',
'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32',
'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0',
'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1',
'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME',
'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER',
'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING',
'DP_SYM32_ENC_GSP_TRIGGER_PENDING',
'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST',
'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST',
'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST',
'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST',
'DP_SYM32_ENC_NOT_PENDING', 'DP_SYM32_ENC_NOT_RESET',
'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', 'DP_SYM32_ENC_ONE_SHOT_MODE',
'DP_SYM32_ENC_OTG_SOF', 'DP_SYM32_ENC_OVERFLOW_OCCURRED',
'DP_SYM32_ENC_PENDING',
'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444',
'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420',
'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422',
'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY',
'DP_SYM32_ENC_POWER_STATE_ENUM_DS',
'DP_SYM32_ENC_POWER_STATE_ENUM_LS',
'DP_SYM32_ENC_POWER_STATE_ENUM_ON',
'DP_SYM32_ENC_POWER_STATE_ENUM_SD', 'DP_SYM32_ENC_RESET',
'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED',
'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED',
'DP_SYM32_ENC_SDP_HIGH_PRIORITY', 'DP_SYM32_ENC_SDP_LOW_PRIORITY',
'DP_SYM32_ENC_UNCOMPRESSED_FORMAT',
'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK',
'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK',
'DP_SYM32_ENC_VID_STREAM_NO_DEFER', 'DP_SYNC_POLARITY',
'DP_SYNC_POLARITY_ACTIVE_HIGH', 'DP_SYNC_POLARITY_ACTIVE_LOW',
'DP_TU_OVERFLOW_ACK', 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT',
'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_UDI_1_LANE', 'DP_UDI_2_LANES',
'DP_UDI_4_LANES', 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED',
'DP_VID_1X_Nvid', 'DP_VID_2X_Nvid', 'DP_VID_4X_Nvid',
'DP_VID_8X_Nvid', 'DP_VID_ENHANCED_FRAME_MODE',
'DP_VID_M_N_CALC_AUTO',
'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE',
'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START',
'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN',
'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_N_INTERVAL',
'DP_VID_STREAM_DISABLE_ACK', 'DP_VID_STREAM_DISABLE_MASK',
'DP_VID_STREAM_DIS_DEFER', 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK',
'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER',
'DP_VID_VBID_FIELD_POL', 'DP_VID_VBID_FIELD_POL_INV',
'DP_VID_VBID_FIELD_POL_NORMAL', 'DRAW_DONE',
'DSCCIF_BITS_PER_COMPONENT_ENUM',
'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT',
'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT',
'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT',
'DSCCIF_ENABLE_ENUM', 'DSCCIF_ENABLE_ENUM_DISABLED',
'DSCCIF_ENABLE_ENUM_ENABLED', 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444',
'DSCC_BITS_PER_COMPONENT_ENUM',
'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT',
'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT',
'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT',
'DSCC_DSC_VERSION_MAJOR_ENUM',
'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION',
'DSCC_DSC_VERSION_MINOR_ENUM',
'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION',
'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION',
'DSCC_ENABLE_ENUM', 'DSCC_ENABLE_ENUM_DISABLED',
'DSCC_ENABLE_ENUM_ENABLED', 'DSCC_ICH_RESET_ENUM',
'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET',
'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET',
'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET',
'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', 'DSCC_LINEBUF_DEPTH_ENUM',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT',
'DSCC_MEM_PWR_DIS_ENUM', 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS',
'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', 'DSCC_MEM_PWR_FORCE_ENUM',
'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST',
'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST',
'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST',
'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST',
'DSCL_MODE_CHROMA_SCALING_BYPASS', 'DSCL_MODE_DSCL_BYPASS',
'DSCL_MODE_LUMA_SCALING_BYPASS', 'DSCL_MODE_SCALING_444_BYPASS',
'DSCL_MODE_SCALING_444_RGB_ENABLE',
'DSCL_MODE_SCALING_444_YCBCR_ENABLE',
'DSCL_MODE_SCALING_YCBCR_ENABLE', 'DSCL_MODE_SEL',
'DS_HW_CAL_DIS', 'DS_HW_CAL_EN', 'DS_HW_CAL_ENABLE',
'DS_REF_IS_EXT_GENLOCK', 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN',
'DS_REF_SRC', 'DVO_ENABLE_RST', 'DVO_ENABLE_RST_DISABLE',
'DVO_ENABLE_RST_ENABLE', 'DWB_CRC_CONT_EN_CONT',
'DWB_CRC_CONT_EN_ENUM', 'DWB_CRC_CONT_EN_ONE_SHOT',
'DWB_CRC_SRC_SEL_DWB_IN', 'DWB_CRC_SRC_SEL_DWB_OUT',
'DWB_CRC_SRC_SEL_ENUM', 'DWB_CRC_SRC_SEL_OGAM_OUT',
'DWB_DATA_OVERFLOW_INT_TYPE_0', 'DWB_DATA_OVERFLOW_INT_TYPE_1',
'DWB_DATA_OVERFLOW_INT_TYPE_ENUM',
'DWB_DATA_OVERFLOW_TYPE_BUFFER', 'DWB_DATA_OVERFLOW_TYPE_ENUM',
'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW',
'DWB_DATA_OVERFLOW_TYPE_VREADY', 'DWB_DATA_OVERFLOW_TYPE_VUPDATE',
'DWB_DEBUG_SEL_DWBCP', 'DWB_DEBUG_SEL_ENUM', 'DWB_DEBUG_SEL_FC',
'DWB_DEBUG_SEL_PERFMON', 'DWB_DEBUG_SEL_RESERVED',
'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM',
'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13',
'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12',
'DWB_GAMUT_REMAP_MODE_BYPASS', 'DWB_GAMUT_REMAP_MODE_COEF_A',
'DWB_GAMUT_REMAP_MODE_COEF_B', 'DWB_GAMUT_REMAP_MODE_ENUM',
'DWB_GAMUT_REMAP_MODE_RESERVED', 'DWB_LUT_NUM_SEG',
'DWB_MEM_PWR_FORCE_DIS', 'DWB_MEM_PWR_FORCE_DS',
'DWB_MEM_PWR_FORCE_ENUM', 'DWB_MEM_PWR_FORCE_LS',
'DWB_MEM_PWR_FORCE_SD', 'DWB_MEM_PWR_STATE_DS',
'DWB_MEM_PWR_STATE_ENUM', 'DWB_MEM_PWR_STATE_LS',
'DWB_MEM_PWR_STATE_ON', 'DWB_MEM_PWR_STATE_SD',
'DWB_OGAM_LUT_CONFIG_MODE_DIFF', 'DWB_OGAM_LUT_CONFIG_MODE_ENUM',
'DWB_OGAM_LUT_CONFIG_MODE_SAME', 'DWB_OGAM_LUT_HOST_SEL_ENUM',
'DWB_OGAM_LUT_HOST_SEL_RAMA', 'DWB_OGAM_LUT_HOST_SEL_RAMB',
'DWB_OGAM_LUT_READ_COLOR_SEL_B',
'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM',
'DWB_OGAM_LUT_READ_COLOR_SEL_G', 'DWB_OGAM_LUT_READ_COLOR_SEL_R',
'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED',
'DWB_OGAM_LUT_READ_DBG_DISABLE', 'DWB_OGAM_LUT_READ_DBG_ENABLE',
'DWB_OGAM_LUT_READ_DBG_ENUM', 'DWB_OGAM_MODE_BYPASS',
'DWB_OGAM_MODE_ENUM', 'DWB_OGAM_MODE_RAM_LUT_ENABLED',
'DWB_OGAM_MODE_RESERVED', 'DWB_OGAM_PWL_DISABLE_ENUM',
'DWB_OGAM_PWL_DISABLE_FALSE', 'DWB_OGAM_PWL_DISABLE_TRUE',
'DWB_OGAM_SELECT_A', 'DWB_OGAM_SELECT_B', 'DWB_OGAM_SELECT_ENUM',
'DWB_SEGMENTS_1', 'DWB_SEGMENTS_128', 'DWB_SEGMENTS_16',
'DWB_SEGMENTS_2', 'DWB_SEGMENTS_32', 'DWB_SEGMENTS_4',
'DWB_SEGMENTS_64', 'DWB_SEGMENTS_8', 'DWB_TEST_CLK_SEL_ENUM',
'DWB_TEST_CLK_SEL_G', 'DWB_TEST_CLK_SEL_P', 'DWB_TEST_CLK_SEL_R',
'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE',
'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE',
'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks',
'DbPRTFaultBehavior', 'DbPSLControl', 'EARLY',
'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z',
'EFC_ACrYCb16161616_10LSB', 'EFC_ACrYCb16161616_10MSB',
'EFC_ACrYCb16161616_12LSB', 'EFC_ACrYCb16161616_12MSB',
'EFC_ACrYCb2101010', 'EFC_ACrYCb8888', 'EFC_ARGB1555',
'EFC_ARGB16161616_10LSB', 'EFC_ARGB16161616_10MSB',
'EFC_ARGB16161616_12LSB', 'EFC_ARGB16161616_12MSB',
'EFC_ARGB16161616_FLOAT', 'EFC_ARGB16161616_SNORM',
'EFC_ARGB16161616_UNORM', 'EFC_ARGB2101010', 'EFC_ARGB4444',
'EFC_ARGB8888', 'EFC_AYCrCb16161616_10LSB',
'EFC_AYCrCb16161616_10MSB', 'EFC_AYCrCb16161616_12LSB',
'EFC_AYCrCb16161616_12MSB', 'EFC_AYCrCb8888', 'EFC_BGR101111_FIX',
'EFC_BGR101111_FLOAT', 'EFC_BGR565',
'EFC_CbYCrY10101010_422_PACKED', 'EFC_CbYCrY12121212_422_PACKED',
'EFC_CbYCrY8888_422_PACKED', 'EFC_CrYCbA1010102',
'EFC_CrYCbA16161616_10LSB', 'EFC_CrYCbA16161616_10MSB',
'EFC_CrYCbA16161616_12LSB', 'EFC_CrYCbA16161616_12MSB',
'EFC_CrYCbA8888', 'EFC_CrYCbY10101010_422_PACKED',
'EFC_CrYCbY12121212_422_PACKED', 'EFC_CrYCbY8888_422_PACKED',
'EFC_MONO_10LSB', 'EFC_MONO_10MSB', 'EFC_MONO_12LSB',
'EFC_MONO_12MSB', 'EFC_MONO_16', 'EFC_MONO_8',
'EFC_RGB111110_FIX', 'EFC_RGB111110_FLOAT', 'EFC_RGB565',
'EFC_RGBA1010102', 'EFC_RGBA16161616_10LSB',
'EFC_RGBA16161616_10MSB', 'EFC_RGBA16161616_12LSB',
'EFC_RGBA16161616_12MSB', 'EFC_RGBA16161616_FLOAT',
'EFC_RGBA16161616_SNORM', 'EFC_RGBA16161616_UNORM',
'EFC_RGBA4444', 'EFC_RGBA5551', 'EFC_RGBA8888',
'EFC_SURFACE_PIXEL_FORMAT', 'EFC_Y10_CbCr1010_420_PLANAR',
'EFC_Y10_CrCb1010_420_PLANAR', 'EFC_Y12_CbCr1212_420_PLANAR',
'EFC_Y12_CrCb1212_420_PLANAR', 'EFC_Y8_CbCr88_420_PLANAR',
'EFC_Y8_CrCb88_420_PLANAR', 'EFC_YCbYCr10101010_422_PACKED',
'EFC_YCbYCr12121212_422_PACKED', 'EFC_YCbYCr8888_422_PACKED',
'EFC_YCrCbA16161616_10LSB', 'EFC_YCrCbA16161616_10MSB',
'EFC_YCrCbA16161616_12LSB', 'EFC_YCrCbA16161616_12MSB',
'EFC_YCrCbA8888', 'EFC_YCrYCb10101010_422_PACKED',
'EFC_YCrYCb12121212_422_PACKED', 'EFC_YCrYCb8888_422_PACKED',
'ENABLE', 'ENABLE_AMCLK0', 'ENABLE_AMCLK1', 'ENABLE_CLOCK',
'ENABLE_DEBUG', 'ENABLE_ENUM', 'ENABLE_ENUM_DISABLED',
'ENABLE_ENUM_ENABLED', 'ENABLE_JITTER_REMOVAL',
'ENABLE_MEM_PWR_CTRL', 'ENABLE_NGG_PIPELINE',
'ENABLE_PIPELINE_NOT_USED', 'ENABLE_PWL', 'ENABLE_TF0_OPT',
'ENABLE_TF1_OPT', 'ENABLE_THE_FEATURE', 'ENABLE_THE_FUNC_CLOCK',
'ENABLE_THE_INTERRUPT', 'ENABLE_THE_REFCLK', 'END_OF_PIPE_IB_END',
'END_OF_PIPE_INCR_DE', 'END_OF_ROW_MODE', 'ENUM_DCN_ACTIVE',
'ENUM_DCN_NOT_ACTIVE', 'ENUM_DIO_DCN_ACTIVE_STATUS',
'ENUM_DPG_BIT_DEPTH', 'ENUM_DPG_BIT_DEPTH_10BPC',
'ENUM_DPG_BIT_DEPTH_12BPC', 'ENUM_DPG_BIT_DEPTH_6BPC',
'ENUM_DPG_BIT_DEPTH_8BPC', 'ENUM_DPG_DISABLE',
'ENUM_DPG_DYNAMIC_RANGE', 'ENUM_DPG_DYNAMIC_RANGE_CEA',
'ENUM_DPG_DYNAMIC_RANGE_VESA', 'ENUM_DPG_EN', 'ENUM_DPG_ENABLE',
'ENUM_DPG_FIELD_POLARITY',
'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD',
'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', 'ENUM_DPG_MODE',
'ENUM_DPG_MODE_HORIZONTAL_BAR', 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK',
'ENUM_DPG_MODE_RGB_DUAL_RAMP', 'ENUM_DPG_MODE_RGB_SINGLE_RAMP',
'ENUM_DPG_MODE_RGB_XR_BIAS', 'ENUM_DPG_MODE_VERTICAL_BAR',
'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK',
'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK',
'ENUM_DP_DPHY_SYM32_CRC_END_EVENT',
'ENUM_DP_DPHY_SYM32_CRC_START_EVENT',
'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE',
'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS',
'ENUM_DP_DPHY_SYM32_ENABLE', 'ENUM_DP_DPHY_SYM32_MODE',
'ENUM_DP_DPHY_SYM32_NUM_LANES', 'ENUM_DP_DPHY_SYM32_OUTPUT_MODE',
'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING',
'ENUM_DP_DPHY_SYM32_RESET', 'ENUM_DP_DPHY_SYM32_RESET_STATUS',
'ENUM_DP_DPHY_SYM32_SAT_UPDATE',
'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING',
'ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS',
'ENUM_DP_DPHY_SYM32_STATUS',
'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE',
'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE',
'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL', 'ENUM_DP_DPHY_SYM32_TP_SELECT',
'ENUM_DP_SYM32_ENC_AUDIO_MUTE',
'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE',
'ENUM_DP_SYM32_ENC_CRC_VALID',
'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH',
'ENUM_DP_SYM32_ENC_ENABLE',
'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED',
'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION',
'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE',
'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING',
'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM',
'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS', 'ENUM_DP_SYM32_ENC_PENDING',
'ENUM_DP_SYM32_ENC_PIXEL_ENCODING',
'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE',
'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM', 'ENUM_DP_SYM32_ENC_RESET',
'ENUM_DP_SYM32_ENC_SDP_PRIORITY',
'ENUM_DP_SYM32_ENC_SOF_REFERENCE',
'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER', 'ENUM_NUM_SIMD_PER_CU',
'EVENT_STATE_CHANGE', 'EXOKAY', 'EXPANSION_MODE',
'EXPANSION_MODE_CONSERVATIVE', 'EXPANSION_MODE_OPTIMAL',
'EXPANSION_MODE_ZERO', 'EXPORT_ANY_Z', 'EXPORT_GREATER_THAN_Z',
'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'FAULT_FAIL',
'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', 'FC_EYE_SELECTION_ENUM',
'FC_EYE_SELECTION_LEFT_EYE', 'FC_EYE_SELECTION_RIGHT_EYE',
'FC_EYE_SELECTION_STEREO_DIS', 'FC_FRAME_CAPTURE_RATE_ENUM',
'FC_FRAME_CAPTURE_RATE_FULL', 'FC_FRAME_CAPTURE_RATE_HALF',
'FC_FRAME_CAPTURE_RATE_QUARTER', 'FC_FRAME_CAPTURE_RATE_THIRD',
'FC_STEREO_EYE_POLARITY_ENUM', 'FC_STEREO_EYE_POLARITY_LEFT',
'FC_STEREO_EYE_POLARITY_RIGHT', 'FEC_ACTIVE_STATUS', 'FIX_S2_13',
'FIX_S3_12', 'FLIP_ANY_FRAME', 'FLIP_LEFT_EYE', 'FLIP_RATE',
'FLIP_RATE_0', 'FLIP_RATE_1', 'FLIP_RATE_2', 'FLIP_RATE_3',
'FLIP_RATE_4', 'FLIP_RATE_5', 'FLIP_RATE_6', 'FLIP_RATE_7',
'FLIP_RIGHT_EYE', 'FLUSH_AND_INV_CB_DATA_TS',
'FLUSH_AND_INV_CB_META', 'FLUSH_AND_INV_CB_PIXEL_DATA',
'FLUSH_AND_INV_DB_DATA_TS', 'FLUSH_AND_INV_DB_META',
'FLUSH_CONTROL_FLUSH_NOT_STARTED', 'FLUSH_CONTROL_FLUSH_STARTED',
'FLUSH_DFSM', 'FLUSH_ES_OUTPUT', 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS',
'FMTMEM_DISABLE_MEM_PWR_CTRL', 'FMTMEM_ENABLE_MEM_PWR_CTRL',
'FMTMEM_FORCE_DEEP_SLEEP_REQUEST',
'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST',
'FMTMEM_FORCE_SHUT_DOWN_REQUEST', 'FMTMEM_NO_FORCE_REQUEST',
'FMTMEM_PWR_DIS_CTRL', 'FMTMEM_PWR_FORCE_CTRL',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED',
'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH',
'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP',
'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP',
'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION',
'FMT_CLAMP_CNTL_COLOR_FORMAT',
'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC',
'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC',
'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC',
'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC',
'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE',
'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1',
'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2',
'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3',
'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS',
'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE',
'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE',
'FMT_CONTROL_PIXEL_ENCODING',
'FMT_CONTROL_PIXEL_ENCODING_RESERVED',
'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444',
'FMT_CONTROL_PIXEL_ENCODING_YCBCR420',
'FMT_CONTROL_PIXEL_ENCODING_YCBCR422',
'FMT_CONTROL_SUBSAMPLING_MODE',
'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE',
'FMT_CONTROL_SUBSAMPLING_MODE_DROP',
'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP',
'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED',
'FMT_CONTROL_SUBSAMPLING_ORDER',
'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR',
'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB',
'FMT_DEBUG_CNTL_COLOR_SELECT', 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE',
'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN',
'FMT_DEBUG_CNTL_COLOR_SELECT_RED1',
'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', 'FMT_DYNAMIC_EXP_MODE',
'FMT_DYNAMIC_EXP_MODE_10to12', 'FMT_DYNAMIC_EXP_MODE_8to12',
'FMT_FRAME_RANDOM_ENABLE_CONTROL',
'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME',
'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', 'FMT_POWER_STATE_ENUM',
'FMT_POWER_STATE_ENUM_DS', 'FMT_POWER_STATE_ENUM_LS',
'FMT_POWER_STATE_ENUM_ON', 'FMT_POWER_STATE_ENUM_SD',
'FMT_RGB_RANDOM_ENABLE_CONTROL',
'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE',
'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED',
'FMT_SPATIAL_DITHER_MODE', 'FMT_SPATIAL_DITHER_MODE_0',
'FMT_SPATIAL_DITHER_MODE_1', 'FMT_SPATIAL_DITHER_MODE_2',
'FMT_SPATIAL_DITHER_MODE_3', 'FMT_STEREOSYNC_OVERRIDE_CONTROL',
'FMT_STEREOSYNC_OVERRIDE_CONTROL_0',
'FMT_STEREOSYNC_OVERRIDE_CONTROL_1',
'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0',
'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR',
'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', 'FORCE_00',
'FORCE_BINNING_ON', 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE',
'FORCE_DISABLE_CLOCK', 'FORCE_EARLY_Z', 'FORCE_ENABLE',
'FORCE_FF', 'FORCE_LATE_Z', 'FORCE_LIGHT_SLEEP_REQ',
'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF',
'FORCE_ONE_ROW_FOR_FRAME', 'FORCE_ONE_ROW_FOR_FRAME_0',
'FORCE_ONE_ROW_FOR_FRAME_1', 'FORCE_OPT_AUTO',
'FORCE_OPT_DISABLE', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0',
'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0',
'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0',
'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z',
'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH',
'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF',
'FORCE_THE_CLOCK_DISABLED', 'FORMAT_CROSSBAR',
'FORMAT_CROSSBAR_B', 'FORMAT_CROSSBAR_G', 'FORMAT_CROSSBAR_R',
'FRAG_ALWAYS', 'FRAG_EQUAL', 'FRAG_GEQUAL', 'FRAG_GREATER',
'FRAG_LEQUAL', 'FRAG_LESS', 'FRAG_NEVER', 'FRAG_NOTEQUAL',
'ForceControl', 'GATCL1RequestType', 'GATCL1_TYPE_BYPASS',
'GATCL1_TYPE_NORMAL', 'GATCL1_TYPE_SHOOTDOWN', 'GCRPerfSel',
'GCR_PERF_SEL_ALL_REQ',
'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ',
'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ',
'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ',
'GCR_PERF_SEL_CPC_ALL_REQ', 'GCR_PERF_SEL_CPC_GL1_ALL_REQ',
'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPC_GL1_RANGE_REQ',
'GCR_PERF_SEL_CPC_GL1_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_CPC_GL2_ALL_REQ',
'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPC_METADATA_REQ',
'GCR_PERF_SEL_CPC_SQC_DATA_REQ', 'GCR_PERF_SEL_CPC_SQC_INST_REQ',
'GCR_PERF_SEL_CPC_TCP_REQ', 'GCR_PERF_SEL_CPF_ALL_REQ',
'GCR_PERF_SEL_CPF_GL1_ALL_REQ',
'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPF_GL1_RANGE_REQ',
'GCR_PERF_SEL_CPF_GL1_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_CPF_GL2_ALL_REQ',
'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPF_METADATA_REQ',
'GCR_PERF_SEL_CPF_SQC_DATA_REQ', 'GCR_PERF_SEL_CPF_SQC_INST_REQ',
'GCR_PERF_SEL_CPF_TCP_REQ', 'GCR_PERF_SEL_CPG_ALL_REQ',
'GCR_PERF_SEL_CPG_GL1_ALL_REQ',
'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPG_GL1_RANGE_REQ',
'GCR_PERF_SEL_CPG_GL1_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_CPG_GL2_ALL_REQ',
'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPG_METADATA_REQ',
'GCR_PERF_SEL_CPG_SQC_DATA_REQ', 'GCR_PERF_SEL_CPG_SQC_INST_REQ',
'GCR_PERF_SEL_CPG_TCP_REQ', 'GCR_PERF_SEL_NONE',
'GCR_PERF_SEL_PHY_REQ', 'GCR_PERF_SEL_PIO_ALL_REQ',
'GCR_PERF_SEL_PIO_GL1_ALL_REQ',
'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_PIO_GL1_RANGE_REQ',
'GCR_PERF_SEL_PIO_GL1_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_PIO_GL2_ALL_REQ',
'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', 'GCR_PERF_SEL_PIO_METADATA_REQ',
'GCR_PERF_SEL_PIO_SQC_DATA_REQ', 'GCR_PERF_SEL_PIO_SQC_INST_REQ',
'GCR_PERF_SEL_PIO_TCP_REQ',
'GCR_PERF_SEL_PMM_ABIT_FLUSH_INTERRUPT',
'GCR_PERF_SEL_PMM_ABIT_FLUSH_ONGOING',
'GCR_PERF_SEL_PMM_ABIT_FORCE_FLUSH',
'GCR_PERF_SEL_PMM_ABIT_NUM_FLUSH',
'GCR_PERF_SEL_PMM_ABIT_TIMER_FLUSH',
'GCR_PERF_SEL_PMM_ALOG_INTERRUPT',
'GCR_PERF_SEL_PMM_INTERRUPT_READY_TO_SEND',
'GCR_PERF_SEL_PMM_MAM_FLUSH_REQ',
'GCR_PERF_SEL_PMM_MAM_FLUSH_RESP',
'GCR_PERF_SEL_PMM_NUM_INTERRUPT', 'GCR_PERF_SEL_PMM_RLC_CGCG_REQ',
'GCR_PERF_SEL_PMM_RLC_CGCG_RESP',
'GCR_PERF_SEL_PMM_STALL_PMM_IH_CREDITS',
'GCR_PERF_SEL_PM_ALL_REQ', 'GCR_PERF_SEL_PM_GL1_ALL_REQ',
'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_PM_GL1_RANGE_REQ',
'GCR_PERF_SEL_PM_GL1_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_PM_GL2_ALL_REQ',
'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_PM_GL2_RANGE_REQ', 'GCR_PERF_SEL_PM_METADATA_REQ',
'GCR_PERF_SEL_PM_SQC_DATA_REQ', 'GCR_PERF_SEL_PM_SQC_INST_REQ',
'GCR_PERF_SEL_PM_TCP_REQ', 'GCR_PERF_SEL_RLC_ALL_REQ',
'GCR_PERF_SEL_RLC_GL1_ALL_REQ',
'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_RLC_GL1_RANGE_REQ',
'GCR_PERF_SEL_RLC_GL1_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_RLC_GL2_ALL_REQ',
'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', 'GCR_PERF_SEL_RLC_METADATA_REQ',
'GCR_PERF_SEL_RLC_SQC_DATA_REQ', 'GCR_PERF_SEL_RLC_SQC_INST_REQ',
'GCR_PERF_SEL_RLC_TCP_REQ', 'GCR_PERF_SEL_SDMA0_ALL_REQ',
'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ',
'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ',
'GCR_PERF_SEL_SDMA0_GL1_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ',
'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ',
'GCR_PERF_SEL_SDMA0_METADATA_REQ',
'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ',
'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA0_TCP_REQ',
'GCR_PERF_SEL_SDMA1_ALL_REQ', 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ',
'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ',
'GCR_PERF_SEL_SDMA1_GL1_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ',
'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ',
'GCR_PERF_SEL_SDMA1_METADATA_REQ',
'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ',
'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA1_TCP_REQ',
'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ',
'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ',
'GCR_PERF_SEL_UTCL2_FILTERED_RET',
'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ',
'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT',
'GCR_PERF_SEL_UTCL2_REQ', 'GCR_PERF_SEL_UTCL2_RET',
'GCR_PERF_SEL_VIRT_REQ', 'GCUTCL2_PERF_SEL',
'GCUTCL2_PERF_SEL_EVENT_0', 'GCUTCL2_PERF_SEL_EVENT_1',
'GCUTCL2_PERF_SEL_EVENT_10', 'GCUTCL2_PERF_SEL_EVENT_11',
'GCUTCL2_PERF_SEL_EVENT_12', 'GCUTCL2_PERF_SEL_EVENT_13',
'GCUTCL2_PERF_SEL_EVENT_14', 'GCUTCL2_PERF_SEL_EVENT_15',
'GCUTCL2_PERF_SEL_EVENT_16', 'GCUTCL2_PERF_SEL_EVENT_17',
'GCUTCL2_PERF_SEL_EVENT_18', 'GCUTCL2_PERF_SEL_EVENT_19',
'GCUTCL2_PERF_SEL_EVENT_2', 'GCUTCL2_PERF_SEL_EVENT_20',
'GCUTCL2_PERF_SEL_EVENT_21', 'GCUTCL2_PERF_SEL_EVENT_22',
'GCUTCL2_PERF_SEL_EVENT_23', 'GCUTCL2_PERF_SEL_EVENT_24',
'GCUTCL2_PERF_SEL_EVENT_25', 'GCUTCL2_PERF_SEL_EVENT_26',
'GCUTCL2_PERF_SEL_EVENT_27', 'GCUTCL2_PERF_SEL_EVENT_28',
'GCUTCL2_PERF_SEL_EVENT_29', 'GCUTCL2_PERF_SEL_EVENT_3',
'GCUTCL2_PERF_SEL_EVENT_30', 'GCUTCL2_PERF_SEL_EVENT_31',
'GCUTCL2_PERF_SEL_EVENT_32', 'GCUTCL2_PERF_SEL_EVENT_33',
'GCUTCL2_PERF_SEL_EVENT_34', 'GCUTCL2_PERF_SEL_EVENT_35',
'GCUTCL2_PERF_SEL_EVENT_36', 'GCUTCL2_PERF_SEL_EVENT_4',
'GCUTCL2_PERF_SEL_EVENT_5', 'GCUTCL2_PERF_SEL_EVENT_6',
'GCUTCL2_PERF_SEL_EVENT_7', 'GCUTCL2_PERF_SEL_EVENT_8',
'GCUTCL2_PERF_SEL_EVENT_9', 'GCVML2_PERF_SEL',
'GCVML2_PERF_SEL_EVENT_0', 'GCVML2_PERF_SEL_EVENT_1',
'GCVML2_PERF_SEL_EVENT_10', 'GCVML2_PERF_SEL_EVENT_11',
'GCVML2_PERF_SEL_EVENT_12', 'GCVML2_PERF_SEL_EVENT_13',
'GCVML2_PERF_SEL_EVENT_14', 'GCVML2_PERF_SEL_EVENT_15',
'GCVML2_PERF_SEL_EVENT_16', 'GCVML2_PERF_SEL_EVENT_17',
'GCVML2_PERF_SEL_EVENT_18', 'GCVML2_PERF_SEL_EVENT_19',
'GCVML2_PERF_SEL_EVENT_2', 'GCVML2_PERF_SEL_EVENT_20',
'GCVML2_PERF_SEL_EVENT_21', 'GCVML2_PERF_SEL_EVENT_22',
'GCVML2_PERF_SEL_EVENT_23', 'GCVML2_PERF_SEL_EVENT_24',
'GCVML2_PERF_SEL_EVENT_25', 'GCVML2_PERF_SEL_EVENT_26',
'GCVML2_PERF_SEL_EVENT_27', 'GCVML2_PERF_SEL_EVENT_28',
'GCVML2_PERF_SEL_EVENT_29', 'GCVML2_PERF_SEL_EVENT_3',
'GCVML2_PERF_SEL_EVENT_30', 'GCVML2_PERF_SEL_EVENT_31',
'GCVML2_PERF_SEL_EVENT_32', 'GCVML2_PERF_SEL_EVENT_33',
'GCVML2_PERF_SEL_EVENT_34', 'GCVML2_PERF_SEL_EVENT_35',
'GCVML2_PERF_SEL_EVENT_36', 'GCVML2_PERF_SEL_EVENT_37',
'GCVML2_PERF_SEL_EVENT_38', 'GCVML2_PERF_SEL_EVENT_39',
'GCVML2_PERF_SEL_EVENT_4', 'GCVML2_PERF_SEL_EVENT_40',
'GCVML2_PERF_SEL_EVENT_41', 'GCVML2_PERF_SEL_EVENT_42',
'GCVML2_PERF_SEL_EVENT_43', 'GCVML2_PERF_SEL_EVENT_44',
'GCVML2_PERF_SEL_EVENT_45', 'GCVML2_PERF_SEL_EVENT_46',
'GCVML2_PERF_SEL_EVENT_47', 'GCVML2_PERF_SEL_EVENT_48',
'GCVML2_PERF_SEL_EVENT_49', 'GCVML2_PERF_SEL_EVENT_5',
'GCVML2_PERF_SEL_EVENT_50', 'GCVML2_PERF_SEL_EVENT_51',
'GCVML2_PERF_SEL_EVENT_52', 'GCVML2_PERF_SEL_EVENT_53',
'GCVML2_PERF_SEL_EVENT_54', 'GCVML2_PERF_SEL_EVENT_55',
'GCVML2_PERF_SEL_EVENT_56', 'GCVML2_PERF_SEL_EVENT_57',
'GCVML2_PERF_SEL_EVENT_58', 'GCVML2_PERF_SEL_EVENT_59',
'GCVML2_PERF_SEL_EVENT_6', 'GCVML2_PERF_SEL_EVENT_60',
'GCVML2_PERF_SEL_EVENT_61', 'GCVML2_PERF_SEL_EVENT_62',
'GCVML2_PERF_SEL_EVENT_63', 'GCVML2_PERF_SEL_EVENT_64',
'GCVML2_PERF_SEL_EVENT_65', 'GCVML2_PERF_SEL_EVENT_66',
'GCVML2_PERF_SEL_EVENT_67', 'GCVML2_PERF_SEL_EVENT_68',
'GCVML2_PERF_SEL_EVENT_69', 'GCVML2_PERF_SEL_EVENT_7',
'GCVML2_PERF_SEL_EVENT_70', 'GCVML2_PERF_SEL_EVENT_71',
'GCVML2_PERF_SEL_EVENT_72', 'GCVML2_PERF_SEL_EVENT_73',
'GCVML2_PERF_SEL_EVENT_74', 'GCVML2_PERF_SEL_EVENT_75',
'GCVML2_PERF_SEL_EVENT_76', 'GCVML2_PERF_SEL_EVENT_77',
'GCVML2_PERF_SEL_EVENT_78', 'GCVML2_PERF_SEL_EVENT_79',
'GCVML2_PERF_SEL_EVENT_8', 'GCVML2_PERF_SEL_EVENT_80',
'GCVML2_PERF_SEL_EVENT_81', 'GCVML2_PERF_SEL_EVENT_82',
'GCVML2_PERF_SEL_EVENT_83', 'GCVML2_PERF_SEL_EVENT_84',
'GCVML2_PERF_SEL_EVENT_85', 'GCVML2_PERF_SEL_EVENT_86',
'GCVML2_PERF_SEL_EVENT_87', 'GCVML2_PERF_SEL_EVENT_88',
'GCVML2_PERF_SEL_EVENT_89', 'GCVML2_PERF_SEL_EVENT_9',
'GCVML2_PERF_SEL_EVENT_90', 'GCVML2_SPM_PERF_SEL',
'GCVML2_SPM_PERF_SEL_EVENT_0', 'GCVML2_SPM_PERF_SEL_EVENT_1',
'GCVML2_SPM_PERF_SEL_EVENT_10', 'GCVML2_SPM_PERF_SEL_EVENT_11',
'GCVML2_SPM_PERF_SEL_EVENT_12', 'GCVML2_SPM_PERF_SEL_EVENT_13',
'GCVML2_SPM_PERF_SEL_EVENT_14', 'GCVML2_SPM_PERF_SEL_EVENT_15',
'GCVML2_SPM_PERF_SEL_EVENT_16', 'GCVML2_SPM_PERF_SEL_EVENT_17',
'GCVML2_SPM_PERF_SEL_EVENT_18', 'GCVML2_SPM_PERF_SEL_EVENT_19',
'GCVML2_SPM_PERF_SEL_EVENT_2', 'GCVML2_SPM_PERF_SEL_EVENT_20',
'GCVML2_SPM_PERF_SEL_EVENT_21', 'GCVML2_SPM_PERF_SEL_EVENT_22',
'GCVML2_SPM_PERF_SEL_EVENT_23', 'GCVML2_SPM_PERF_SEL_EVENT_24',
'GCVML2_SPM_PERF_SEL_EVENT_25', 'GCVML2_SPM_PERF_SEL_EVENT_26',
'GCVML2_SPM_PERF_SEL_EVENT_27', 'GCVML2_SPM_PERF_SEL_EVENT_28',
'GCVML2_SPM_PERF_SEL_EVENT_29', 'GCVML2_SPM_PERF_SEL_EVENT_3',
'GCVML2_SPM_PERF_SEL_EVENT_30', 'GCVML2_SPM_PERF_SEL_EVENT_31',
'GCVML2_SPM_PERF_SEL_EVENT_32', 'GCVML2_SPM_PERF_SEL_EVENT_33',
'GCVML2_SPM_PERF_SEL_EVENT_34', 'GCVML2_SPM_PERF_SEL_EVENT_35',
'GCVML2_SPM_PERF_SEL_EVENT_36', 'GCVML2_SPM_PERF_SEL_EVENT_37',
'GCVML2_SPM_PERF_SEL_EVENT_38', 'GCVML2_SPM_PERF_SEL_EVENT_39',
'GCVML2_SPM_PERF_SEL_EVENT_4', 'GCVML2_SPM_PERF_SEL_EVENT_40',
'GCVML2_SPM_PERF_SEL_EVENT_41', 'GCVML2_SPM_PERF_SEL_EVENT_42',
'GCVML2_SPM_PERF_SEL_EVENT_43', 'GCVML2_SPM_PERF_SEL_EVENT_44',
'GCVML2_SPM_PERF_SEL_EVENT_45', 'GCVML2_SPM_PERF_SEL_EVENT_46',
'GCVML2_SPM_PERF_SEL_EVENT_47', 'GCVML2_SPM_PERF_SEL_EVENT_48',
'GCVML2_SPM_PERF_SEL_EVENT_49', 'GCVML2_SPM_PERF_SEL_EVENT_5',
'GCVML2_SPM_PERF_SEL_EVENT_50', 'GCVML2_SPM_PERF_SEL_EVENT_51',
'GCVML2_SPM_PERF_SEL_EVENT_52', 'GCVML2_SPM_PERF_SEL_EVENT_53',
'GCVML2_SPM_PERF_SEL_EVENT_54', 'GCVML2_SPM_PERF_SEL_EVENT_55',
'GCVML2_SPM_PERF_SEL_EVENT_56', 'GCVML2_SPM_PERF_SEL_EVENT_57',
'GCVML2_SPM_PERF_SEL_EVENT_58', 'GCVML2_SPM_PERF_SEL_EVENT_59',
'GCVML2_SPM_PERF_SEL_EVENT_6', 'GCVML2_SPM_PERF_SEL_EVENT_60',
'GCVML2_SPM_PERF_SEL_EVENT_61', 'GCVML2_SPM_PERF_SEL_EVENT_62',
'GCVML2_SPM_PERF_SEL_EVENT_63', 'GCVML2_SPM_PERF_SEL_EVENT_64',
'GCVML2_SPM_PERF_SEL_EVENT_65', 'GCVML2_SPM_PERF_SEL_EVENT_66',
'GCVML2_SPM_PERF_SEL_EVENT_67', 'GCVML2_SPM_PERF_SEL_EVENT_68',
'GCVML2_SPM_PERF_SEL_EVENT_69', 'GCVML2_SPM_PERF_SEL_EVENT_7',
'GCVML2_SPM_PERF_SEL_EVENT_70', 'GCVML2_SPM_PERF_SEL_EVENT_71',
'GCVML2_SPM_PERF_SEL_EVENT_72', 'GCVML2_SPM_PERF_SEL_EVENT_73',
'GCVML2_SPM_PERF_SEL_EVENT_74', 'GCVML2_SPM_PERF_SEL_EVENT_75',
'GCVML2_SPM_PERF_SEL_EVENT_76', 'GCVML2_SPM_PERF_SEL_EVENT_77',
'GCVML2_SPM_PERF_SEL_EVENT_78', 'GCVML2_SPM_PERF_SEL_EVENT_79',
'GCVML2_SPM_PERF_SEL_EVENT_8', 'GCVML2_SPM_PERF_SEL_EVENT_80',
'GCVML2_SPM_PERF_SEL_EVENT_81', 'GCVML2_SPM_PERF_SEL_EVENT_82',
'GCVML2_SPM_PERF_SEL_EVENT_83', 'GCVML2_SPM_PERF_SEL_EVENT_84',
'GCVML2_SPM_PERF_SEL_EVENT_85', 'GCVML2_SPM_PERF_SEL_EVENT_86',
'GCVML2_SPM_PERF_SEL_EVENT_87', 'GCVML2_SPM_PERF_SEL_EVENT_88',
'GCVML2_SPM_PERF_SEL_EVENT_89', 'GCVML2_SPM_PERF_SEL_EVENT_9',
'GCVML2_SPM_PERF_SEL_EVENT_90', 'GC_EA_CPWD_PERFCOUNT_SEL',
'GC_EA_CPWD_PERF_SEL_ALWAYS_COUNT',
'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_COMPLETED',
'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT',
'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED',
'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_ONGOING',
'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_EVICT',
'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT',
'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT_EVICT',
'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_LRU_EVICT',
'GC_EA_CPWD_PERF_SEL_MAM_ARAM_REQ_VLD',
'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_EVICT',
'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT',
'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT_EVICT',
'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_LRU_EVICT',
'GC_EA_CPWD_PERF_SEL_MAM_DBIT_REQ_VLD',
'GC_EA_CPWD_PERF_SEL_MAM_DQRY_ONGOING',
'GC_EA_CPWD_PERF_SEL_MAM_FLUSH_REQ',
'GC_EA_CPWD_PERF_SEL_MAM_FLUSH_RESP',
'GC_EA_CPWD_PERF_SEL_MAM_NUM_DQRY', 'GC_EA_CPWD_PERF_SEL_PRB_REQ',
'GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH',
'GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP',
'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END0',
'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END1',
'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START0',
'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START1',
'GC_EA_CPWD_PERF_SEL_RDRAM_NUM_BANKS_VLD',
'GC_EA_CPWD_PERF_SEL_RDRAM_REQ_PER_CLIGRP',
'GC_EA_CPWD_PERF_SEL_RDRAM_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH',
'GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR',
'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END0',
'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END1',
'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START0',
'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START1',
'GC_EA_CPWD_PERF_SEL_RGMI_NUM_BANKS_VLD',
'GC_EA_CPWD_PERF_SEL_RGMI_REQ_PER_CLIGRP',
'GC_EA_CPWD_PERF_SEL_RGMI_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_RIO_GRP0_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_RIO_GRP1_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_RIO_GRP2_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_RIO_GRP3_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END0',
'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END1',
'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START0',
'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START1',
'GC_EA_CPWD_PERF_SEL_RIO_REQ_PER_CLIGRP',
'GC_EA_CPWD_PERF_SEL_RIO_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_RRET_VLD', 'GC_EA_CPWD_PERF_SEL_SARB_BUSY',
'GC_EA_CPWD_PERF_SEL_SARB_COHERENT_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_SARB_DRAM_REQ_PER_VC',
'GC_EA_CPWD_PERF_SEL_SARB_DRAM_RW_TURN_AROUND',
'GC_EA_CPWD_PERF_SEL_SARB_DRAM_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_SARB_GMI_REQ_PER_VC',
'GC_EA_CPWD_PERF_SEL_SARB_GMI_RW_TURN_AROUND',
'GC_EA_CPWD_PERF_SEL_SARB_GMI_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_SARB_IDLE',
'GC_EA_CPWD_PERF_SEL_SARB_IO_REQ_PER_VC',
'GC_EA_CPWD_PERF_SEL_SARB_IO_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END0',
'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END1',
'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START0',
'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START1',
'GC_EA_CPWD_PERF_SEL_SARB_REQ_PER_VC',
'GC_EA_CPWD_PERF_SEL_SARB_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_SARB_STALLED',
'GC_EA_CPWD_PERF_SEL_SARB_STARVING',
'GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH',
'GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP',
'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END0',
'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END1',
'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START0',
'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START1',
'GC_EA_CPWD_PERF_SEL_WDRAM_NUM_BANKS_VLD',
'GC_EA_CPWD_PERF_SEL_WDRAM_REQ_PER_CLIGRP',
'GC_EA_CPWD_PERF_SEL_WDRAM_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH',
'GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP',
'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END0',
'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END1',
'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START0',
'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START1',
'GC_EA_CPWD_PERF_SEL_WGMI_NUM_BANKS_VLD',
'GC_EA_CPWD_PERF_SEL_WGMI_REQ_PER_CLIGRP',
'GC_EA_CPWD_PERF_SEL_WGMI_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP',
'GC_EA_CPWD_PERF_SEL_WIO_GRP0_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_WIO_GRP1_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_WIO_GRP2_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_WIO_GRP3_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END0',
'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END1',
'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START0',
'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START1',
'GC_EA_CPWD_PERF_SEL_WIO_REQ_PER_CLIGRP',
'GC_EA_CPWD_PERF_SEL_WIO_SIZE_REQ',
'GC_EA_CPWD_PERF_SEL_WRET_VLD', 'GC_EA_SE_PERFCOUNT_SEL',
'GC_EA_SE_PERF_SEL_ALWAYS_COUNT',
'GC_EA_SE_PERF_SEL_MAM_AFLUSH_COMPLETED',
'GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT',
'GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED',
'GC_EA_SE_PERF_SEL_MAM_AFLUSH_ONGOING',
'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_EVICT',
'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT',
'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT_EVICT',
'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_LRU_EVICT',
'GC_EA_SE_PERF_SEL_MAM_ARAM_REQ_VLD',
'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_EVICT',
'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT',
'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT_EVICT',
'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_LRU_EVICT',
'GC_EA_SE_PERF_SEL_MAM_DBIT_REQ_VLD',
'GC_EA_SE_PERF_SEL_MAM_DQRY_ONGOING',
'GC_EA_SE_PERF_SEL_MAM_FLUSH_REQ',
'GC_EA_SE_PERF_SEL_MAM_FLUSH_RESP',
'GC_EA_SE_PERF_SEL_MAM_NUM_DQRY', 'GC_EA_SE_PERF_SEL_PRB_REQ',
'GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH',
'GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP',
'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END0',
'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END1',
'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START0',
'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START1',
'GC_EA_SE_PERF_SEL_RDRAM_NUM_BANKS_VLD',
'GC_EA_SE_PERF_SEL_RDRAM_REQ_PER_CLIGRP',
'GC_EA_SE_PERF_SEL_RDRAM_SIZE_REQ',
'GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH',
'GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR',
'GC_EA_SE_PERF_SEL_RGMI_LATENCY_END0',
'GC_EA_SE_PERF_SEL_RGMI_LATENCY_END1',
'GC_EA_SE_PERF_SEL_RGMI_LATENCY_START0',
'GC_EA_SE_PERF_SEL_RGMI_LATENCY_START1',
'GC_EA_SE_PERF_SEL_RGMI_NUM_BANKS_VLD',
'GC_EA_SE_PERF_SEL_RGMI_REQ_PER_CLIGRP',
'GC_EA_SE_PERF_SEL_RGMI_SIZE_REQ',
'GC_EA_SE_PERF_SEL_RIO_GRP0_SIZE_REQ',
'GC_EA_SE_PERF_SEL_RIO_GRP1_SIZE_REQ',
'GC_EA_SE_PERF_SEL_RIO_GRP2_SIZE_REQ',
'GC_EA_SE_PERF_SEL_RIO_GRP3_SIZE_REQ',
'GC_EA_SE_PERF_SEL_RIO_LATENCY_END0',
'GC_EA_SE_PERF_SEL_RIO_LATENCY_END1',
'GC_EA_SE_PERF_SEL_RIO_LATENCY_START0',
'GC_EA_SE_PERF_SEL_RIO_LATENCY_START1',
'GC_EA_SE_PERF_SEL_RIO_REQ_PER_CLIGRP',
'GC_EA_SE_PERF_SEL_RIO_SIZE_REQ', 'GC_EA_SE_PERF_SEL_RRET_VLD',
'GC_EA_SE_PERF_SEL_SARB_BUSY',
'GC_EA_SE_PERF_SEL_SARB_COHERENT_SIZE_REQ',
'GC_EA_SE_PERF_SEL_SARB_DRAM_REQ_PER_VC',
'GC_EA_SE_PERF_SEL_SARB_DRAM_RW_TURN_AROUND',
'GC_EA_SE_PERF_SEL_SARB_DRAM_SIZE_REQ',
'GC_EA_SE_PERF_SEL_SARB_GMI_REQ_PER_VC',
'GC_EA_SE_PERF_SEL_SARB_GMI_RW_TURN_AROUND',
'GC_EA_SE_PERF_SEL_SARB_GMI_SIZE_REQ',
'GC_EA_SE_PERF_SEL_SARB_IDLE',
'GC_EA_SE_PERF_SEL_SARB_IO_REQ_PER_VC',
'GC_EA_SE_PERF_SEL_SARB_IO_SIZE_REQ',
'GC_EA_SE_PERF_SEL_SARB_LATENCY_END0',
'GC_EA_SE_PERF_SEL_SARB_LATENCY_END1',
'GC_EA_SE_PERF_SEL_SARB_LATENCY_START0',
'GC_EA_SE_PERF_SEL_SARB_LATENCY_START1',
'GC_EA_SE_PERF_SEL_SARB_REQ_PER_VC',
'GC_EA_SE_PERF_SEL_SARB_SIZE_REQ',
'GC_EA_SE_PERF_SEL_SARB_STALLED',
'GC_EA_SE_PERF_SEL_SARB_STARVING',
'GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH',
'GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP',
'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END0',
'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END1',
'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START0',
'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START1',
'GC_EA_SE_PERF_SEL_WDRAM_NUM_BANKS_VLD',
'GC_EA_SE_PERF_SEL_WDRAM_REQ_PER_CLIGRP',
'GC_EA_SE_PERF_SEL_WDRAM_SIZE_REQ',
'GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH',
'GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP',
'GC_EA_SE_PERF_SEL_WGMI_LATENCY_END0',
'GC_EA_SE_PERF_SEL_WGMI_LATENCY_END1',
'GC_EA_SE_PERF_SEL_WGMI_LATENCY_START0',
'GC_EA_SE_PERF_SEL_WGMI_LATENCY_START1',
'GC_EA_SE_PERF_SEL_WGMI_NUM_BANKS_VLD',
'GC_EA_SE_PERF_SEL_WGMI_REQ_PER_CLIGRP',
'GC_EA_SE_PERF_SEL_WGMI_SIZE_REQ',
'GC_EA_SE_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP',
'GC_EA_SE_PERF_SEL_WIO_GRP0_SIZE_REQ',
'GC_EA_SE_PERF_SEL_WIO_GRP1_SIZE_REQ',
'GC_EA_SE_PERF_SEL_WIO_GRP2_SIZE_REQ',
'GC_EA_SE_PERF_SEL_WIO_GRP3_SIZE_REQ',
'GC_EA_SE_PERF_SEL_WIO_LATENCY_END0',
'GC_EA_SE_PERF_SEL_WIO_LATENCY_END1',
'GC_EA_SE_PERF_SEL_WIO_LATENCY_START0',
'GC_EA_SE_PERF_SEL_WIO_LATENCY_START1',
'GC_EA_SE_PERF_SEL_WIO_REQ_PER_CLIGRP',
'GC_EA_SE_PERF_SEL_WIO_SIZE_REQ', 'GC_EA_SE_PERF_SEL_WRET_VLD',
'GE1_PERFCOUNT_SELECT', 'GE2_DIST_PERFCOUNT_SELECT',
'GE2_SE_PERFCOUNT_SELECT',
'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE',
'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE',
'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL',
'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED',
'GENERIC_STEREOSYNC_SEL', 'GENERIC_STEREOSYNC_SEL_D1',
'GENERIC_STEREOSYNC_SEL_D2', 'GENERIC_STEREOSYNC_SEL_D3',
'GENERIC_STEREOSYNC_SEL_D4', 'GENERIC_STEREOSYNC_SEL_RESERVED',
'GL0V_CACHE_POLICIES', 'GL0V_CACHE_POLICY_HIT_EVICT',
'GL0V_CACHE_POLICY_HIT_LRU', 'GL0V_CACHE_POLICY_MISS_EVICT',
'GL0V_CACHE_POLICY_MISS_INVAL', 'GL0V_CACHE_POLICY_MISS_LRU',
'GL1A_PERF_SEL', 'GL1A_PERF_SEL_ARB_REQUESTS',
'GL1A_PERF_SEL_BURST_COUNT_GL1C0',
'GL1A_PERF_SEL_BURST_COUNT_GL1C1',
'GL1A_PERF_SEL_BURST_COUNT_GL1C2',
'GL1A_PERF_SEL_BURST_COUNT_GL1C3', 'GL1A_PERF_SEL_BUSY',
'GL1A_PERF_SEL_CYCLE', 'GL1A_PERF_SEL_REQUEST_GL1C0',
'GL1A_PERF_SEL_REQUEST_GL1C1', 'GL1A_PERF_SEL_REQUEST_GL1C2',
'GL1A_PERF_SEL_REQUEST_GL1C3', 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL',
'GL1A_PERF_SEL_STALL_GL1C0', 'GL1A_PERF_SEL_STALL_GL1C1',
'GL1A_PERF_SEL_STALL_GL1C2', 'GL1A_PERF_SEL_STALL_GL1C3',
'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0',
'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1',
'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2',
'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3',
'GL1A_PERF_SEL_WDS_32B_GL1C0', 'GL1A_PERF_SEL_WDS_32B_GL1C1',
'GL1A_PERF_SEL_WDS_32B_GL1C2', 'GL1A_PERF_SEL_WDS_32B_GL1C3',
'GL1C_PERF_SEL', 'GL1C_PERF_SEL_ARB_RET_LEVEL',
'GL1C_PERF_SEL_BUSY', 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT',
'GL1C_PERF_SEL_CYCLE', 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY',
'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'GL1C_PERF_SEL_REQ',
'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET',
'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', 'GL1C_PERF_SEL_REQ_CLIENT0',
'GL1C_PERF_SEL_REQ_CLIENT1', 'GL1C_PERF_SEL_REQ_CLIENT10',
'GL1C_PERF_SEL_REQ_CLIENT11', 'GL1C_PERF_SEL_REQ_CLIENT12',
'GL1C_PERF_SEL_REQ_CLIENT13', 'GL1C_PERF_SEL_REQ_CLIENT14',
'GL1C_PERF_SEL_REQ_CLIENT15', 'GL1C_PERF_SEL_REQ_CLIENT16',
'GL1C_PERF_SEL_REQ_CLIENT17', 'GL1C_PERF_SEL_REQ_CLIENT18',
'GL1C_PERF_SEL_REQ_CLIENT19', 'GL1C_PERF_SEL_REQ_CLIENT2',
'GL1C_PERF_SEL_REQ_CLIENT20', 'GL1C_PERF_SEL_REQ_CLIENT21',
'GL1C_PERF_SEL_REQ_CLIENT22', 'GL1C_PERF_SEL_REQ_CLIENT23',
'GL1C_PERF_SEL_REQ_CLIENT24', 'GL1C_PERF_SEL_REQ_CLIENT25',
'GL1C_PERF_SEL_REQ_CLIENT26', 'GL1C_PERF_SEL_REQ_CLIENT27',
'GL1C_PERF_SEL_REQ_CLIENT3', 'GL1C_PERF_SEL_REQ_CLIENT4',
'GL1C_PERF_SEL_REQ_CLIENT5', 'GL1C_PERF_SEL_REQ_CLIENT6',
'GL1C_PERF_SEL_REQ_CLIENT7', 'GL1C_PERF_SEL_REQ_CLIENT8',
'GL1C_PERF_SEL_REQ_CLIENT9', 'GL1C_PERF_SEL_REQ_NOP_ACK',
'GL1C_PERF_SEL_REQ_NOP_RTN0', 'GL1C_PERF_SEL_REQ_READ',
'GL1C_PERF_SEL_REQ_READ_128B', 'GL1C_PERF_SEL_REQ_READ_32B',
'GL1C_PERF_SEL_REQ_READ_64B', 'GL1C_PERF_SEL_REQ_WRITE',
'GL1C_PERF_SEL_REQ_WRITE_32B', 'GL1C_PERF_SEL_REQ_WRITE_64B',
'GL1C_PERF_SEL_STALL_BUFFER_FULL', 'GL1C_PERF_SEL_STALL_GL2_GL1',
'GL1C_PERF_SEL_STALL_VM', 'GL1C_PERF_SEL_STARVE',
'GL1C_PERF_SEL_UTCL0_GPA3_REQUEST',
'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ',
'GL1C_PERF_SEL_UTCL0_LFIFO_FULL',
'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS',
'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS',
'GL1C_PERF_SEL_UTCL0_REQUEST',
'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX',
'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES',
'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT',
'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL',
'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS',
'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS',
'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT',
'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS',
'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT',
'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT',
'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT',
'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT',
'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', 'GL1XA_PERF_SEL',
'GL1XA_PERF_SEL_ARB_REQUESTS',
'GL1XA_PERF_SEL_BURST_COUNT_GL1XC0',
'GL1XA_PERF_SEL_BURST_COUNT_GL1XC1',
'GL1XA_PERF_SEL_BURST_COUNT_GL1XC2',
'GL1XA_PERF_SEL_BURST_COUNT_GL1XC3', 'GL1XA_PERF_SEL_BUSY',
'GL1XA_PERF_SEL_CYCLE', 'GL1XA_PERF_SEL_REQUEST_GL1XC0',
'GL1XA_PERF_SEL_REQUEST_GL1XC1', 'GL1XA_PERF_SEL_REQUEST_GL1XC2',
'GL1XA_PERF_SEL_REQUEST_GL1XC3',
'GL1XA_PERF_SEL_REQ_INFLIGHT_LEVEL',
'GL1XA_PERF_SEL_STALL_GL1XC0', 'GL1XA_PERF_SEL_STALL_GL1XC1',
'GL1XA_PERF_SEL_STALL_GL1XC2', 'GL1XA_PERF_SEL_STALL_GL1XC3',
'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC0',
'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC1',
'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC2',
'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC3',
'GL1XA_PERF_SEL_WDS_32B_GL1XC0', 'GL1XA_PERF_SEL_WDS_32B_GL1XC1',
'GL1XA_PERF_SEL_WDS_32B_GL1XC2', 'GL1XA_PERF_SEL_WDS_32B_GL1XC3',
'GL1XC_PERF_SEL', 'GL1XC_PERF_SEL_ARB_RET_LEVEL',
'GL1XC_PERF_SEL_BUSY', 'GL1XC_PERF_SEL_CLIENT_UTCL0_INFLIGHT',
'GL1XC_PERF_SEL_CYCLE', 'GL1XC_PERF_SEL_GL2_REQ_READ_LATENCY',
'GL1XC_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'GL1XC_PERF_SEL_REQ',
'GL1XC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET',
'GL1XC_PERF_SEL_REQ_ATOMIC_WITH_RET',
'GL1XC_PERF_SEL_REQ_CLIENT0', 'GL1XC_PERF_SEL_REQ_CLIENT1',
'GL1XC_PERF_SEL_REQ_CLIENT10', 'GL1XC_PERF_SEL_REQ_CLIENT11',
'GL1XC_PERF_SEL_REQ_CLIENT12', 'GL1XC_PERF_SEL_REQ_CLIENT13',
'GL1XC_PERF_SEL_REQ_CLIENT14', 'GL1XC_PERF_SEL_REQ_CLIENT15',
'GL1XC_PERF_SEL_REQ_CLIENT16', 'GL1XC_PERF_SEL_REQ_CLIENT17',
'GL1XC_PERF_SEL_REQ_CLIENT18', 'GL1XC_PERF_SEL_REQ_CLIENT19',
'GL1XC_PERF_SEL_REQ_CLIENT2', 'GL1XC_PERF_SEL_REQ_CLIENT20',
'GL1XC_PERF_SEL_REQ_CLIENT21', 'GL1XC_PERF_SEL_REQ_CLIENT22',
'GL1XC_PERF_SEL_REQ_CLIENT23', 'GL1XC_PERF_SEL_REQ_CLIENT24',
'GL1XC_PERF_SEL_REQ_CLIENT25', 'GL1XC_PERF_SEL_REQ_CLIENT26',
'GL1XC_PERF_SEL_REQ_CLIENT27', 'GL1XC_PERF_SEL_REQ_CLIENT3',
'GL1XC_PERF_SEL_REQ_CLIENT4', 'GL1XC_PERF_SEL_REQ_CLIENT5',
'GL1XC_PERF_SEL_REQ_CLIENT6', 'GL1XC_PERF_SEL_REQ_CLIENT7',
'GL1XC_PERF_SEL_REQ_CLIENT8', 'GL1XC_PERF_SEL_REQ_CLIENT9',
'GL1XC_PERF_SEL_REQ_NOP_ACK', 'GL1XC_PERF_SEL_REQ_NOP_RTN0',
'GL1XC_PERF_SEL_REQ_READ', 'GL1XC_PERF_SEL_REQ_READ_128B',
'GL1XC_PERF_SEL_REQ_READ_32B', 'GL1XC_PERF_SEL_REQ_READ_64B',
'GL1XC_PERF_SEL_REQ_WRITE', 'GL1XC_PERF_SEL_REQ_WRITE_32B',
'GL1XC_PERF_SEL_REQ_WRITE_64B',
'GL1XC_PERF_SEL_STALL_BUFFER_FULL',
'GL1XC_PERF_SEL_STALL_GL2_GL1', 'GL1XC_PERF_SEL_STALL_VM',
'GL1XC_PERF_SEL_STARVE', 'GL1XC_PERF_SEL_UTCL0_GPA3_REQUEST',
'GL1XC_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ',
'GL1XC_PERF_SEL_UTCL0_LFIFO_FULL',
'GL1XC_PERF_SEL_UTCL0_MISS_UNDER_MISS',
'GL1XC_PERF_SEL_UTCL0_PERMISSION_MISS',
'GL1XC_PERF_SEL_UTCL0_REQUEST',
'GL1XC_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX',
'GL1XC_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES',
'GL1XC_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT',
'GL1XC_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL',
'GL1XC_PERF_SEL_UTCL0_STALL_MULTI_MISS',
'GL1XC_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS',
'GL1XC_PERF_SEL_UTCL0_TRANSLATION_HIT',
'GL1XC_PERF_SEL_UTCL0_TRANSLATION_MISS',
'GL1XC_PERF_SEL_UTCL0_UTCL1_INFLIGHT',
'GL1XC_PERF_SEL_UTCL0_UTCL1_PERM_FAULT',
'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT',
'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT',
'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT',
'GL1_CACHE_POLICIES', 'GL1_CACHE_POLICY_HIT_EVICT',
'GL1_CACHE_POLICY_HIT_LRU', 'GL1_CACHE_POLICY_MISS_EVICT',
'GL1_CACHE_POLICY_MISS_LRU', 'GL1_CACHE_STORE_POLICIES',
'GL1_CACHE_STORE_POLICY_BYPASS', 'GL2A_PERF_SEL',
'GL2A_PERF_SEL_BUSY', 'GL2A_PERF_SEL_CYCLE', 'GL2A_PERF_SEL_NONE',
'GL2A_PERF_SEL_REQ_BURST_CLIENT0',
'GL2A_PERF_SEL_REQ_BURST_CLIENT1',
'GL2A_PERF_SEL_REQ_BURST_CLIENT10',
'GL2A_PERF_SEL_REQ_BURST_CLIENT11',
'GL2A_PERF_SEL_REQ_BURST_CLIENT12',
'GL2A_PERF_SEL_REQ_BURST_CLIENT13',
'GL2A_PERF_SEL_REQ_BURST_CLIENT14',
'GL2A_PERF_SEL_REQ_BURST_CLIENT15',
'GL2A_PERF_SEL_REQ_BURST_CLIENT2',
'GL2A_PERF_SEL_REQ_BURST_CLIENT3',
'GL2A_PERF_SEL_REQ_BURST_CLIENT4',
'GL2A_PERF_SEL_REQ_BURST_CLIENT5',
'GL2A_PERF_SEL_REQ_BURST_CLIENT6',
'GL2A_PERF_SEL_REQ_BURST_CLIENT7',
'GL2A_PERF_SEL_REQ_BURST_CLIENT8',
'GL2A_PERF_SEL_REQ_BURST_CLIENT9',
'GL2A_PERF_SEL_REQ_BURST_GL2C0', 'GL2A_PERF_SEL_REQ_BURST_GL2C1',
'GL2A_PERF_SEL_REQ_BURST_GL2C2', 'GL2A_PERF_SEL_REQ_BURST_GL2C3',
'GL2A_PERF_SEL_REQ_BURST_GL2C4', 'GL2A_PERF_SEL_REQ_BURST_GL2C5',
'GL2A_PERF_SEL_REQ_BURST_GL2C6', 'GL2A_PERF_SEL_REQ_BURST_GL2C7',
'GL2A_PERF_SEL_REQ_GL2C0', 'GL2A_PERF_SEL_REQ_GL2C1',
'GL2A_PERF_SEL_REQ_GL2C2', 'GL2A_PERF_SEL_REQ_GL2C3',
'GL2A_PERF_SEL_REQ_GL2C4', 'GL2A_PERF_SEL_REQ_GL2C5',
'GL2A_PERF_SEL_REQ_GL2C6', 'GL2A_PERF_SEL_REQ_GL2C7',
'GL2A_PERF_SEL_REQ_STALL_GL2C0', 'GL2A_PERF_SEL_REQ_STALL_GL2C1',
'GL2A_PERF_SEL_REQ_STALL_GL2C2', 'GL2A_PERF_SEL_REQ_STALL_GL2C3',
'GL2A_PERF_SEL_REQ_STALL_GL2C4', 'GL2A_PERF_SEL_REQ_STALL_GL2C5',
'GL2A_PERF_SEL_REQ_STALL_GL2C6', 'GL2A_PERF_SEL_REQ_STALL_GL2C7',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9',
'GL2A_PERF_SEL_RTN_CLIENT0', 'GL2A_PERF_SEL_RTN_CLIENT1',
'GL2A_PERF_SEL_RTN_CLIENT10', 'GL2A_PERF_SEL_RTN_CLIENT11',
'GL2A_PERF_SEL_RTN_CLIENT12', 'GL2A_PERF_SEL_RTN_CLIENT13',
'GL2A_PERF_SEL_RTN_CLIENT14', 'GL2A_PERF_SEL_RTN_CLIENT15',
'GL2A_PERF_SEL_RTN_CLIENT2', 'GL2A_PERF_SEL_RTN_CLIENT3',
'GL2A_PERF_SEL_RTN_CLIENT4', 'GL2A_PERF_SEL_RTN_CLIENT5',
'GL2A_PERF_SEL_RTN_CLIENT6', 'GL2A_PERF_SEL_RTN_CLIENT7',
'GL2A_PERF_SEL_RTN_CLIENT8', 'GL2A_PERF_SEL_RTN_CLIENT9',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9',
'GL2A_PERF_SEL_RTN_STALL_GL2C0', 'GL2A_PERF_SEL_RTN_STALL_GL2C1',
'GL2A_PERF_SEL_RTN_STALL_GL2C2', 'GL2A_PERF_SEL_RTN_STALL_GL2C3',
'GL2A_PERF_SEL_RTN_STALL_GL2C4', 'GL2A_PERF_SEL_RTN_STALL_GL2C5',
'GL2A_PERF_SEL_RTN_STALL_GL2C6', 'GL2A_PERF_SEL_RTN_STALL_GL2C7',
'GL2C_PERF_SEL', 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT',
'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT',
'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE',
'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE',
'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK',
'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START',
'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START',
'GL2C_PERF_SEL_ATOMIC', 'GL2C_PERF_SEL_BUBBLE',
'GL2C_PERF_SEL_BUSY', 'GL2C_PERF_SEL_BYPASS_REQ',
'GL2C_PERF_SEL_CLIENT0_REQ', 'GL2C_PERF_SEL_CLIENT10_REQ',
'GL2C_PERF_SEL_CLIENT11_REQ', 'GL2C_PERF_SEL_CLIENT12_REQ',
'GL2C_PERF_SEL_CLIENT13_REQ', 'GL2C_PERF_SEL_CLIENT14_REQ',
'GL2C_PERF_SEL_CLIENT15_REQ', 'GL2C_PERF_SEL_CLIENT1_REQ',
'GL2C_PERF_SEL_CLIENT2_REQ', 'GL2C_PERF_SEL_CLIENT3_REQ',
'GL2C_PERF_SEL_CLIENT4_REQ', 'GL2C_PERF_SEL_CLIENT5_REQ',
'GL2C_PERF_SEL_CLIENT6_REQ', 'GL2C_PERF_SEL_CLIENT7_REQ',
'GL2C_PERF_SEL_CLIENT8_REQ', 'GL2C_PERF_SEL_CLIENT9_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_REQ', 'GL2C_PERF_SEL_CYCLE',
'GL2C_PERF_SEL_C_RO_S_REQ', 'GL2C_PERF_SEL_C_RO_US_REQ',
'GL2C_PERF_SEL_C_RW_S_REQ', 'GL2C_PERF_SEL_C_RW_US_REQ',
'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'GL2C_PERF_SEL_EA_ATOMIC',
'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', 'GL2C_PERF_SEL_EA_OUTSTANDING',
'GL2C_PERF_SEL_EA_RDREQ_128B', 'GL2C_PERF_SEL_EA_RDREQ_32B',
'GL2C_PERF_SEL_EA_RDREQ_64B', 'GL2C_PERF_SEL_EA_RDREQ_96B',
'GL2C_PERF_SEL_EA_RDREQ_DRAM', 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B',
'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL',
'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL',
'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL',
'GL2C_PERF_SEL_EA_RDREQ_SNOOP', 'GL2C_PERF_SEL_EA_RDREQ_SPLIT',
'GL2C_PERF_SEL_EA_RDRET_NACK',
'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B',
'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', 'GL2C_PERF_SEL_EA_WRREQ_64B',
'GL2C_PERF_SEL_EA_WRREQ_DRAM', 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B',
'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL',
'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL',
'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL',
'GL2C_PERF_SEL_EA_WRREQ_SNOOP', 'GL2C_PERF_SEL_EA_WRRET_NACK',
'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', 'GL2C_PERF_SEL_EVICT',
'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', 'GL2C_PERF_SEL_FULL_HIT',
'GL2C_PERF_SEL_GARLIC_READ', 'GL2C_PERF_SEL_GARLIC_WRITE',
'GL2C_PERF_SEL_GCR_ALL', 'GL2C_PERF_SEL_GCR_DISCARD',
'GL2C_PERF_SEL_GCR_GL2_INV_ALL',
'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', 'GL2C_PERF_SEL_GCR_GL2_WB_ALL',
'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE',
'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', 'GL2C_PERF_SEL_GCR_INV',
'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE',
'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT',
'GL2C_PERF_SEL_GCR_INVL2_VOL_START', 'GL2C_PERF_SEL_GCR_RANGE',
'GL2C_PERF_SEL_GCR_UNSHARED', 'GL2C_PERF_SEL_GCR_VOL',
'GL2C_PERF_SEL_GCR_WB', 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE',
'GL2C_PERF_SEL_GCR_WBINVL2_EVICT',
'GL2C_PERF_SEL_GCR_WBINVL2_START',
'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE',
'GL2C_PERF_SEL_GCR_WBL2_VOL_START', 'GL2C_PERF_SEL_GL2A_LEVEL',
'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', 'GL2C_PERF_SEL_HIT',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', 'GL2C_PERF_SEL_IB_REQ',
'GL2C_PERF_SEL_IB_STALL', 'GL2C_PERF_SEL_IB_TAG_STALL',
'GL2C_PERF_SEL_IO_READ', 'GL2C_PERF_SEL_IO_WRITE',
'GL2C_PERF_SEL_LATENCY_FIFO_FULL', 'GL2C_PERF_SEL_LRU_REQ',
'GL2C_PERF_SEL_MC_RDREQ', 'GL2C_PERF_SEL_MC_RDREQ_LEVEL',
'GL2C_PERF_SEL_MC_WRREQ', 'GL2C_PERF_SEL_MC_WRREQ_LEVEL',
'GL2C_PERF_SEL_MC_WRREQ_STALL', 'GL2C_PERF_SEL_METADATA_READ_REQ',
'GL2C_PERF_SEL_MISS', 'GL2C_PERF_SEL_NOA_REQ',
'GL2C_PERF_SEL_NONE', 'GL2C_PERF_SEL_NOP_ACK',
'GL2C_PERF_SEL_NOP_RTN0', 'GL2C_PERF_SEL_NORMAL_EVICT',
'GL2C_PERF_SEL_NORMAL_WRITEBACK', 'GL2C_PERF_SEL_ONION_READ',
'GL2C_PERF_SEL_ONION_WRITE', 'GL2C_PERF_SEL_PARTIAL_32B_HIT',
'GL2C_PERF_SEL_PARTIAL_64B_HIT', 'GL2C_PERF_SEL_PARTIAL_96B_HIT',
'GL2C_PERF_SEL_READ', 'GL2C_PERF_SEL_READ_128_REQ',
'GL2C_PERF_SEL_READ_32_REQ', 'GL2C_PERF_SEL_READ_64_REQ',
'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE',
'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', 'GL2C_PERF_SEL_REQ',
'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', 'GL2C_PERF_SEL_RETURN_ACK',
'GL2C_PERF_SEL_RETURN_DATA', 'GL2C_PERF_SEL_SHARED_REQ',
'GL2C_PERF_SEL_SRC_FIFO_FULL', 'GL2C_PERF_SEL_STREAM_REQ',
'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL',
'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL',
'GL2C_PERF_SEL_TAG_READ_DST_STALL', 'GL2C_PERF_SEL_TAG_STALL',
'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL',
'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL',
'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 'GL2C_PERF_SEL_UC_REQ',
'GL2C_PERF_SEL_UNCACHED_WRITE', 'GL2C_PERF_SEL_VOL_REQ',
'GL2C_PERF_SEL_WRITE', 'GL2C_PERF_SEL_WRITEBACK',
'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT',
'GL2C_PERF_SEL_WRITE_32_REQ', 'GL2C_PERF_SEL_WRITE_64_REQ',
'GL2_CACHE_POLICIES', 'GL2_CACHE_POLICY_BYPASS',
'GL2_CACHE_POLICY_LRU', 'GL2_CACHE_POLICY_NOA',
'GL2_CACHE_POLICY_STREAM', 'GL2_NACKS', 'GL2_NACK_DATA_ERROR',
'GL2_NACK_NO_FAULT', 'GL2_NACK_PAGE_FAULT',
'GL2_NACK_PROTECTION_FAULT', 'GL2_OP', 'GL2_OP_ATOMIC_ADD_32',
'GL2_OP_ATOMIC_ADD_64', 'GL2_OP_ATOMIC_ADD_RTN_32',
'GL2_OP_ATOMIC_ADD_RTN_64', 'GL2_OP_ATOMIC_AND_32',
'GL2_OP_ATOMIC_AND_64', 'GL2_OP_ATOMIC_AND_RTN_32',
'GL2_OP_ATOMIC_AND_RTN_64', 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32',
'GL2_OP_ATOMIC_CMPSWAP_32', 'GL2_OP_ATOMIC_CMPSWAP_64',
'GL2_OP_ATOMIC_CMPSWAP_RTN_32', 'GL2_OP_ATOMIC_CMPSWAP_RTN_64',
'GL2_OP_ATOMIC_COND_SUB_RTN_32', 'GL2_OP_ATOMIC_DEC_32',
'GL2_OP_ATOMIC_DEC_64', 'GL2_OP_ATOMIC_DEC_RTN_32',
'GL2_OP_ATOMIC_DEC_RTN_64', 'GL2_OP_ATOMIC_FADD_32',
'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32',
'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32',
'GL2_OP_ATOMIC_FADD_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_32',
'GL2_OP_ATOMIC_FCMPSWAP_64',
'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32',
'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64',
'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32',
'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64',
'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64',
'GL2_OP_ATOMIC_FMAX_32', 'GL2_OP_ATOMIC_FMAX_64',
'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32',
'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64',
'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32',
'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64',
'GL2_OP_ATOMIC_FMAX_RTN_32', 'GL2_OP_ATOMIC_FMAX_RTN_64',
'GL2_OP_ATOMIC_FMIN_32', 'GL2_OP_ATOMIC_FMIN_64',
'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32',
'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64',
'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32',
'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64',
'GL2_OP_ATOMIC_FMIN_RTN_32', 'GL2_OP_ATOMIC_FMIN_RTN_64',
'GL2_OP_ATOMIC_INC_32', 'GL2_OP_ATOMIC_INC_64',
'GL2_OP_ATOMIC_INC_RTN_32', 'GL2_OP_ATOMIC_INC_RTN_64',
'GL2_OP_ATOMIC_OR_32', 'GL2_OP_ATOMIC_OR_64',
'GL2_OP_ATOMIC_OR_RTN_32', 'GL2_OP_ATOMIC_OR_RTN_64',
'GL2_OP_ATOMIC_PK_ADD_BF16', 'GL2_OP_ATOMIC_PK_ADD_BF16_RTN',
'GL2_OP_ATOMIC_PK_ADD_FP16', 'GL2_OP_ATOMIC_PK_ADD_FP16_RTN',
'GL2_OP_ATOMIC_SMAX_32', 'GL2_OP_ATOMIC_SMAX_64',
'GL2_OP_ATOMIC_SMAX_RTN_32', 'GL2_OP_ATOMIC_SMAX_RTN_64',
'GL2_OP_ATOMIC_SMIN_32', 'GL2_OP_ATOMIC_SMIN_64',
'GL2_OP_ATOMIC_SMIN_RTN_32', 'GL2_OP_ATOMIC_SMIN_RTN_64',
'GL2_OP_ATOMIC_STORE_COND_RTN', 'GL2_OP_ATOMIC_SUB_32',
'GL2_OP_ATOMIC_SUB_64', 'GL2_OP_ATOMIC_SUB_RTN_32',
'GL2_OP_ATOMIC_SUB_RTN_64', 'GL2_OP_ATOMIC_SWAP_32',
'GL2_OP_ATOMIC_SWAP_64', 'GL2_OP_ATOMIC_SWAP_RTN_32',
'GL2_OP_ATOMIC_SWAP_RTN_64', 'GL2_OP_ATOMIC_UMAX_32',
'GL2_OP_ATOMIC_UMAX_64', 'GL2_OP_ATOMIC_UMAX_8',
'GL2_OP_ATOMIC_UMAX_RTN_32', 'GL2_OP_ATOMIC_UMAX_RTN_64',
'GL2_OP_ATOMIC_UMIN_32', 'GL2_OP_ATOMIC_UMIN_64',
'GL2_OP_ATOMIC_UMIN_8', 'GL2_OP_ATOMIC_UMIN_RTN_32',
'GL2_OP_ATOMIC_UMIN_RTN_64', 'GL2_OP_ATOMIC_XOR_32',
'GL2_OP_ATOMIC_XOR_64', 'GL2_OP_ATOMIC_XOR_RTN_32',
'GL2_OP_ATOMIC_XOR_RTN_64',
'GL2_OP_FORCE_EXISTING_DATA_TO_DECOMPRESS', 'GL2_OP_GL1_INV',
'GL2_OP_GL2_INV', 'GL2_OP_GL2_WB', 'GL2_OP_GL2_WBINV',
'GL2_OP_LOAD_RESERVE', 'GL2_OP_MASKS', 'GL2_OP_MASK_64',
'GL2_OP_MASK_FLUSH_DENROM', 'GL2_OP_MASK_NO_RTN',
'GL2_OP_NOP_ACK', 'GL2_OP_NOP_RTN0', 'GL2_OP_PROBE_FILTER',
'GL2_OP_READ', 'GL2_OP_READ_COMPRESSION_KEY',
'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', 'GL2_OP_UTC_PROBE',
'GL2_OP_WRITE', 'GL2_OP_WRITE_ZERO_SIZE', 'GLCompressionMode',
'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE',
'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL',
'GLOBAL_STATUS_FLUSH_STATUS',
'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED',
'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED',
'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA',
'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA',
'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA',
'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA',
'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA',
'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO',
'GRBMH_PERF_SEL', 'GRBMH_PERF_SEL_BCI_BUSY',
'GRBMH_PERF_SEL_CB_BUSY', 'GRBMH_PERF_SEL_CB_CLEAN',
'GRBMH_PERF_SEL_COUNT', 'GRBMH_PERF_SEL_DB_BUSY',
'GRBMH_PERF_SEL_DB_CLEAN', 'GRBMH_PERF_SEL_EA_BUSY',
'GRBMH_PERF_SEL_EA_LINK_BUSY', 'GRBMH_PERF_SEL_GE_BUSY',
'GRBMH_PERF_SEL_GL1A_BUSY', 'GRBMH_PERF_SEL_GL1CC_BUSY',
'GRBMH_PERF_SEL_GL1XCC_BUSY', 'GRBMH_PERF_SEL_GL2A_BUSY',
'GRBMH_PERF_SEL_GL2C_BUSY', 'GRBMH_PERF_SEL_PA_BUSY',
'GRBMH_PERF_SEL_PC_BUSY', 'GRBMH_PERF_SEL_RLC_BUSY',
'GRBMH_PERF_SEL_SC_BUSY', 'GRBMH_PERF_SEL_SC_CLEAN',
'GRBMH_PERF_SEL_SPI_BUSY', 'GRBMH_PERF_SEL_SX_BUSY',
'GRBMH_PERF_SEL_TA_BUSY', 'GRBMH_PERF_SEL_TCP_BUSY',
'GRBMH_PERF_SEL_USER_DEFINED', 'GRBMH_PERF_SEL_UTCL1_BUSY',
'GRBM_PERF_SEL', 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY',
'GRBM_PERF_SEL_BCI_BUSY', 'GRBM_PERF_SEL_CB_BUSY',
'GRBM_PERF_SEL_CB_CLEAN', 'GRBM_PERF_SEL_CH_BUSY',
'GRBM_PERF_SEL_COUNT', 'GRBM_PERF_SEL_CPC_BUSY',
'GRBM_PERF_SEL_CPF_BUSY', 'GRBM_PERF_SEL_CPG_BUSY',
'GRBM_PERF_SEL_CP_BUSY', 'GRBM_PERF_SEL_CP_COHER_BUSY',
'GRBM_PERF_SEL_CP_DMA_BUSY', 'GRBM_PERF_SEL_DB_BUSY',
'GRBM_PERF_SEL_DB_CLEAN', 'GRBM_PERF_SEL_EA_BUSY',
'GRBM_PERF_SEL_GE_BUSY', 'GRBM_PERF_SEL_GE_NO_DMA_BUSY',
'GRBM_PERF_SEL_GL1CC_BUSY', 'GRBM_PERF_SEL_GL1XCC_BUSY',
'GRBM_PERF_SEL_GL2CC_BUSY', 'GRBM_PERF_SEL_GUI_ACTIVE',
'GRBM_PERF_SEL_GUS_BUSY', 'GRBM_PERF_SEL_PA_BUSY',
'GRBM_PERF_SEL_PC_BUSY', 'GRBM_PERF_SEL_PMM_BUSY',
'GRBM_PERF_SEL_RLC_BUSY', 'GRBM_PERF_SEL_SC_BUSY',
'GRBM_PERF_SEL_SDMA_BUSY', 'GRBM_PERF_SEL_SPI_BUSY',
'GRBM_PERF_SEL_SX_BUSY', 'GRBM_PERF_SEL_TA_BUSY',
'GRBM_PERF_SEL_TCP_BUSY', 'GRBM_PERF_SEL_USER_DEFINED',
'GRBM_PERF_SEL_UTCL1_BUSY', 'GRBM_PERF_SEL_UTCL2_BUSY',
'GREEN_LUT', 'GSTHREADID_SIZE', 'GS_OFF', 'GS_SCENARIO_A',
'GS_SCENARIO_B', 'GS_SCENARIO_C', 'GS_SCENARIO_G', 'GS_STAGE_OFF',
'GS_STAGE_ON', 'HDMICHARCLK_SRC_SEL',
'HDMICHARCLK_SRC_SEL_SRC_RESERVED', 'HDMICHARCLK_SRC_SEL_UNIPHYA',
'HDMICHARCLK_SRC_SEL_UNIPHYB', 'HDMICHARCLK_SRC_SEL_UNIPHYC',
'HDMICHARCLK_SRC_SEL_UNIPHYD', 'HDMISTREAMCLK_SRC_SEL',
'HDMI_ACP_NOT_SEND', 'HDMI_ACP_PKT_SEND', 'HDMI_ACP_SEND',
'HDMI_ACR_0_MULTIPLE_RESERVED', 'HDMI_ACR_1_MULTIPLE',
'HDMI_ACR_2_MULTIPLE', 'HDMI_ACR_3_MULTIPLE_RESERVED',
'HDMI_ACR_4_MULTIPLE', 'HDMI_ACR_5_MULTIPLE_RESERVED',
'HDMI_ACR_6_MULTIPLE_RESERVED', 'HDMI_ACR_7_MULTIPLE_RESERVED',
'HDMI_ACR_AUDIO_PRIORITY', 'HDMI_ACR_CONT',
'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE',
'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE',
'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE',
'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K',
'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K',
'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE',
'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW',
'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK',
'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN',
'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT',
'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE',
'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND',
'HDMI_AUDIO_INFO_SEND',
'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT',
'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE',
'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE',
'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DATA_SCRAMBLE_DISABLE',
'HDMI_DATA_SCRAMBLE_EN', 'HDMI_DATA_SCRAMBLE_ENABLE',
'HDMI_DEEP_COLOR_DEPTH', 'HDMI_DEEP_COLOR_DEPTH_24BPP',
'HDMI_DEEP_COLOR_DEPTH_30BPP', 'HDMI_DEEP_COLOR_DEPTH_36BPP',
'HDMI_DEEP_COLOR_DEPTH_48BPP', 'HDMI_DEFAULT_PAHSE',
'HDMI_DEFAULT_PHASE_IS_0', 'HDMI_DEFAULT_PHASE_IS_1',
'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', 'HDMI_ERROR_MASK',
'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK',
'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE',
'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_GC_AVMUTE',
'HDMI_GC_AVMUTE_CONT', 'HDMI_GC_AVMUTE_CONT_DISABLE',
'HDMI_GC_AVMUTE_CONT_ENABLE', 'HDMI_GC_AVMUTE_SET',
'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', 'HDMI_GC_CONT_DISABLE',
'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', 'HDMI_GC_PKT_SEND',
'HDMI_GC_SEND', 'HDMI_GENERIC_CONT', 'HDMI_GENERIC_CONT_DISABLE',
'HDMI_GENERIC_CONT_ENABLE', 'HDMI_GENERIC_NOT_SEND',
'HDMI_GENERIC_PKT_SEND', 'HDMI_GENERIC_SEND', 'HDMI_ISRC_CONT',
'HDMI_ISRC_CONT_DISABLE', 'HDMI_ISRC_CONT_ENABLE',
'HDMI_ISRC_NOT_SEND', 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND',
'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC',
'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE',
'HDMI_METADATA_ENABLE', 'HDMI_METADATA_NOT_SEND',
'HDMI_METADATA_PKT_SEND', 'HDMI_MPEG_INFO_CONT',
'HDMI_MPEG_INFO_CONT_DISABLE', 'HDMI_MPEG_INFO_CONT_ENABLE',
'HDMI_MPEG_INFO_NOT_SEND', 'HDMI_MPEG_INFO_PKT_SEND',
'HDMI_MPEG_INFO_SEND', 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS',
'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND',
'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION',
'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD',
'HDMI_PACKET_LINE_REFERENCE', 'HDMI_PACKING_PHASE_OVERRIDE',
'HDMI_PACKING_PHASE_SET_BY_HW', 'HDMI_PACKING_PHASE_SET_BY_SW',
'HDMI_PKT_LINE_REF_OTGSOF', 'HDMI_PKT_LINE_REF_VSYNC',
'HDMI_SEND_MAX_AUDIO_PACKETS', 'HDP_ENDIAN_8IN16',
'HDP_ENDIAN_8IN32', 'HDP_ENDIAN_8IN64', 'HDP_ENDIAN_NONE',
'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0',
'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON',
'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY',
'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0',
'HPD_INT_CONTROL_RX_INT_ACK_1', 'HPO_SRC0', 'HPO_SRC_RESERVED',
'HPO_TOP_CLOCK_GATING_DIS', 'HPO_TOP_CLOCK_GATING_DISABLE',
'HPO_TOP_CLOCK_GATING_EN',
'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0',
'HPO_TOP_FEATURE_GATED_HDMICHARCLK0',
'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0',
'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0',
'HPO_TOP_PERMANENT_DISPCLK', 'HPO_TOP_PERMANENT_HDMICHARCLK0',
'HPO_TOP_PERMANENT_HDMISTREAMCLK0', 'HPO_TOP_PERMANENT_SOCCLK',
'HPO_TOP_REGISTER_GATED_DISPCLK',
'HPO_TOP_REGISTER_GATED_HDMICHARCLK0',
'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', 'HPO_TOP_TEST_CLK_SEL',
'HPO_TOP_TEST_CLOCK_RESERVED', 'HS_GS', 'HS_STAGE_OFF',
'HS_STAGE_ON', 'HUBP_3DLUT_ADDRESSING_MODE',
'HUBP_3DLUT_SIMPLE_LINEAR', 'HUBP_3DLUT_SW_LINEAR',
'HUBP_BLANK_EN', 'HUBP_BLANK_SW_ASSERT', 'HUBP_BLANK_SW_DEASSERT',
'HUBP_IN_ACTIVE', 'HUBP_IN_BLANK', 'HUBP_IN_VBLANK',
'HUBP_MEASURE_WIN_MODE_DCFCLK', 'HUBP_MEASURE_WIN_MODE_DCFCLK_0',
'HUBP_MEASURE_WIN_MODE_DCFCLK_1',
'HUBP_MEASURE_WIN_MODE_DCFCLK_2',
'HUBP_MEASURE_WIN_MODE_DCFCLK_3', 'HUBP_NO_OUTSTANDING_REQ',
'HUBP_SOFT_RESET', 'HUBP_SOFT_RESET_OFF', 'HUBP_SOFT_RESET_ON',
'HUBP_TTU_DISABLE', 'HUBP_TTU_DISABLED', 'HUBP_TTU_ENABLED',
'HUBP_VREADY_AT_OR_AFTER_VSYNC', 'HUBP_VTG_SEL',
'HW_MIRRORING_DISABLE', 'HW_MIRRORING_ENABLE', 'H_MIRROR_EN',
'Hdp_SurfaceEndian', 'ID_STREAM_DISABLE_ACKED',
'ID_STREAM_DISABLE_NO_ACK', 'IHC_INTERRUPT_DEST',
'IHC_INTERRUPT_LINE_STATUS',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID',
'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', 'INPUT_INNER_COVERAGE',
'INST_ID_ECC_INTERRUPT_MSG', 'INST_ID_HOST_REG_TRAP_MSG',
'INST_ID_HW_TRAP', 'INST_ID_HW_TRAP_GET_TBA', 'INST_ID_KILL_SEQ',
'INST_ID_PRIV_START', 'INST_ID_SPI_WREXEC',
'INST_ID_TTRACE_NEW_PC_MSG', 'INTERRUPT_LINE_ASSERTED',
'INTERRUPT_LINE_NOT_ASSERTED', 'INTERRUPT_SENT_TO_DMCUB',
'INTERRUPT_SENT_TO_IH', 'INT_DISABLED', 'INT_ENABLED',
'INT_LEVEL', 'INT_MASK', 'INT_PULSE', 'INVALID_REG_ACCESS_TYPE',
'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD',
'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP',
'IQ_SCH_WAVE_MSG', 'ISHARP_FMT_MODE_0', 'ISHARP_FMT_MODE_1',
'ISHARP_FMT_MODE_ENUM', 'ISHARP_LBA_MODE_0', 'ISHARP_LBA_MODE_1',
'ISHARP_LBA_MODE_ENUM', 'ISHARP_NOISEDET_MODE_0',
'ISHARP_NOISEDET_MODE_1', 'ISHARP_NOISEDET_MODE_2',
'ISHARP_NOISEDET_MODE_3', 'ISHARP_NOISEDET_MODE_ENUM',
'JITTER_REMOVE_DISABLE', 'LATE_Z', 'LB_ALPHA_DISABLE',
'LB_ALPHA_EN', 'LB_ALPHA_ENABLE', 'LB_INTERLEAVE_DISABLE',
'LB_INTERLEAVE_EN', 'LB_INTERLEAVE_ENABLE', 'LB_MEMORY_CONFIG',
'LB_MEMORY_CONFIG_0', 'LB_MEMORY_CONFIG_1', 'LB_MEMORY_CONFIG_2',
'LB_MEMORY_CONFIG_3', 'LEGACY_PIPE_INTERLEAVE',
'LEGACY_PIPE_INTERLEAVE_256B', 'LEGACY_PIPE_INTERLEAVE_512B',
'LINESTRIP', 'LSDMA_PERF_SEL', 'LSDMA_PERF_SEL_ATCL2_FREE',
'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH',
'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH',
'LSDMA_PERF_SEL_ATCL2_RET_ACK', 'LSDMA_PERF_SEL_ATCL2_RET_XNACK',
'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ',
'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET',
'LSDMA_PERF_SEL_CE_AFIFO_FULL', 'LSDMA_PERF_SEL_CE_BUSY',
'LSDMA_PERF_SEL_CE_BUSY_END', 'LSDMA_PERF_SEL_CE_BUSY_START',
'LSDMA_PERF_SEL_CE_DST_IDLE', 'LSDMA_PERF_SEL_CE_INFO1_FULL',
'LSDMA_PERF_SEL_CE_INFO_FULL', 'LSDMA_PERF_SEL_CE_IN_IDLE',
'LSDMA_PERF_SEL_CE_L1_STALL', 'LSDMA_PERF_SEL_CE_L1_WR_VLD',
'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND',
'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND',
'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ',
'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET',
'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ',
'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET',
'LSDMA_PERF_SEL_CE_OUT_IDLE', 'LSDMA_PERF_SEL_CE_RD_STALL',
'LSDMA_PERF_SEL_CE_RREQ_IDLE', 'LSDMA_PERF_SEL_CE_SPLIT_IDLE',
'LSDMA_PERF_SEL_CE_WREQ_IDLE', 'LSDMA_PERF_SEL_CE_WR_IDLE',
'LSDMA_PERF_SEL_CE_WR_STALL', 'LSDMA_PERF_SEL_CMD_OP_END',
'LSDMA_PERF_SEL_CMD_OP_MATCH', 'LSDMA_PERF_SEL_CMD_OP_START',
'LSDMA_PERF_SEL_CTX_CHANGE',
'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION',
'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'LSDMA_PERF_SEL_CYCLE',
'LSDMA_PERF_SEL_DMA_L1_RD_SEND', 'LSDMA_PERF_SEL_DMA_L1_WR_SEND',
'LSDMA_PERF_SEL_DMA_MC_RD_SEND', 'LSDMA_PERF_SEL_DMA_MC_WR_SEND',
'LSDMA_PERF_SEL_DOORBELL', 'LSDMA_PERF_SEL_DRAM_ECC',
'LSDMA_PERF_SEL_DUMMY_0', 'LSDMA_PERF_SEL_DUMMY_1',
'LSDMA_PERF_SEL_EX_IDLE',
'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
'LSDMA_PERF_SEL_F32_L1_WR_VLD',
'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER',
'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END',
'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START',
'LSDMA_PERF_SEL_GFX_SELECT', 'LSDMA_PERF_SEL_IB_CMD_FULL',
'LSDMA_PERF_SEL_IB_CMD_IDLE', 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ',
'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_IDLE',
'LSDMA_PERF_SEL_INT_IDLE', 'LSDMA_PERF_SEL_INT_REQ_COUNT',
'LSDMA_PERF_SEL_INT_REQ_STALL',
'LSDMA_PERF_SEL_INT_RESP_ACCEPTED',
'LSDMA_PERF_SEL_INT_RESP_RETRY',
'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD',
'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR',
'LSDMA_PERF_SEL_L1_INV_MIDDLE', 'LSDMA_PERF_SEL_L1_RDL2_IDLE',
'LSDMA_PERF_SEL_L1_RDMC_IDLE', 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE',
'LSDMA_PERF_SEL_L1_RD_INV_EN', 'LSDMA_PERF_SEL_L1_RD_INV_IDLE',
'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR',
'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT',
'LSDMA_PERF_SEL_L1_WRL2_IDLE', 'LSDMA_PERF_SEL_L1_WRMC_IDLE',
'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', 'LSDMA_PERF_SEL_L1_WR_INV_EN',
'LSDMA_PERF_SEL_L1_WR_INV_IDLE',
'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR',
'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT',
'LSDMA_PERF_SEL_MC_RD_COUNT', 'LSDMA_PERF_SEL_MC_RD_IDLE',
'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE',
'LSDMA_PERF_SEL_MC_RD_RET_STALL', 'LSDMA_PERF_SEL_MC_WR_COUNT',
'LSDMA_PERF_SEL_MC_WR_IDLE',
'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID',
'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID',
'LSDMA_PERF_SEL_NACK_GEN_ERR', 'LSDMA_PERF_SEL_NUM_PACKET',
'LSDMA_PERF_SEL_PAGE_SELECT', 'LSDMA_PERF_SEL_RB_CMD_FULL',
'LSDMA_PERF_SEL_RB_CMD_IDLE', 'LSDMA_PERF_SEL_RB_EMPTY',
'LSDMA_PERF_SEL_RB_FULL', 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ',
'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_RB_RPTR_WB',
'LSDMA_PERF_SEL_RB_RPTR_WRAP', 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ',
'LSDMA_PERF_SEL_RB_WPTR_WRAP', 'LSDMA_PERF_SEL_RD_BA_RTR',
'LSDMA_PERF_SEL_REG_IDLE', 'LSDMA_PERF_SEL_RLC0_SELECT',
'LSDMA_PERF_SEL_RLC1_SELECT', 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND',
'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH',
'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 'LSDMA_PERF_SEL_SEM_IDLE',
'LSDMA_PERF_SEL_SEM_REQ_COUNT', 'LSDMA_PERF_SEL_SEM_REQ_STALL',
'LSDMA_PERF_SEL_SEM_RESP_FAIL',
'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE',
'LSDMA_PERF_SEL_SEM_RESP_PASS', 'LSDMA_PERF_SEL_SRBM_REG_SEND',
'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ',
'LSDMA_PERF_SEL_UTCL1_UTCL2_RET',
'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ',
'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', 'LSDMA_PERF_SEL_WR_BA_RTR',
'LUMA_KEYER_ENABLE', 'LUMA_KEY_DIS', 'LUMA_KEY_EN',
'LUT_2CFG_MEMORY_A', 'LUT_2CFG_MEMORY_B', 'LUT_2CFG_NO_MEMORY',
'LUT_2_MODE_BYPASS', 'LUT_2_MODE_RAMA_LUT', 'LUT_2_MODE_RAMB_LUT',
'LUT_4CFG_MEMORY_A', 'LUT_4CFG_MEMORY_B', 'LUT_4CFG_NO_MEMORY',
'LUT_4CFG_ROM_A', 'LUT_4CFG_ROM_B', 'LUT_4_MODE_BYPASS',
'LUT_4_MODE_RAMA_LUT', 'LUT_4_MODE_RAMB_LUT',
'LUT_4_MODE_ROMA_LUT', 'LUT_4_MODE_ROMB_LUT',
'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS',
'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH',
'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT',
'MASTER_UPDATE_LOCK_DB_FIELD_BOTH',
'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM',
'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED',
'MASTER_UPDATE_LOCK_DB_FIELD_TOP',
'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH',
'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT',
'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED',
'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT',
'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK',
'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE',
'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE',
'MASTER_UPDATE_LOCK_SEL', 'MASTER_UPDATE_LOCK_SEL_0',
'MASTER_UPDATE_LOCK_SEL_1', 'MASTER_UPDATE_LOCK_SEL_2',
'MASTER_UPDATE_LOCK_SEL_3', 'MASTER_UPDATE_LOCK_SEL_RESERVED4',
'MASTER_UPDATE_LOCK_SEL_RESERVED5',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP',
'MATRIX_MODE_0', 'MATRIX_MODE_1', 'MATRIX_MODE_ENUM',
'MEM_ARB_MODE_AGE', 'MEM_ARB_MODE_BOTH', 'MEM_ARB_MODE_FIXED',
'MEM_ARB_MODE_WEIGHT', 'MEM_POWER_DIS_MODE_DISABLE',
'MEM_POWER_DIS_MODE_ENABLE', 'MEM_POWER_FORCE_MODE_DEEP_SLEEP',
'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', 'MEM_POWER_FORCE_MODE_OFF',
'MEM_POWER_FORCE_MODE_SHUT_DOWN', 'MEM_POWER_STATUS_DEEP_SLEEP',
'MEM_POWER_STATUS_LIGHT_SLEEP', 'MEM_POWER_STATUS_ON',
'MEM_POWER_STATUS_SHUT_DOWN', 'MEM_PWR_DIS_CTRL',
'MEM_PWR_DIS_MODE', 'MEM_PWR_FORCE_CTRL', 'MEM_PWR_FORCE_CTRL2',
'MEM_PWR_FORCE_MODE', 'MEM_PWR_SEL_CTRL', 'MEM_PWR_SEL_CTRL2',
'MEM_PWR_STATUS', 'METADATA_HUBP_SEL', 'METADATA_HUBP_SEL_0',
'METADATA_HUBP_SEL_1', 'METADATA_HUBP_SEL_2',
'METADATA_HUBP_SEL_3', 'METADATA_HUBP_SEL_RESERVED',
'METADATA_STREAM_DP', 'METADATA_STREAM_DVE',
'METADATA_STREAM_TYPE_SEL', 'META_CHUNK_SIZE',
'META_CHUNK_SIZE_1KB', 'META_CHUNK_SIZE_2KB',
'META_CHUNK_SIZE_4KB', 'META_CHUNK_SIZE_8KB', 'META_LINEAR',
'META_SURF_LINEAR', 'META_SURF_TILED', 'ME_ID0', 'ME_ID1',
'ME_ID2', 'ME_ID3', 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK',
'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN',
'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL',
'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK',
'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN',
'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MIN_CHUNK_SIZE',
'MIN_CHUNK_SIZE_1024B', 'MIN_CHUNK_SIZE_256B',
'MIN_CHUNK_SIZE_512B', 'MIN_META_CHUNK_SIZE',
'MIN_META_CHUNK_SIZE_128B', 'MIN_META_CHUNK_SIZE_256B',
'MIN_META_CHUNK_SIZE_64B', 'MONO_10LSB', 'MONO_10MSB',
'MONO_12LSB', 'MONO_12MSB', 'MONO_16', 'MONO_2BIT', 'MONO_8',
'MPCC_BG_COLOR_BPC', 'MPCC_BG_COLOR_BPC_10bit',
'MPCC_BG_COLOR_BPC_11bit', 'MPCC_BG_COLOR_BPC_12bit',
'MPCC_BG_COLOR_BPC_8bit', 'MPCC_BG_COLOR_BPC_9bit',
'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY',
'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE',
'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED',
'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE',
'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE',
'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE',
'MPCC_CONTROL_MPCC_BOT_GAIN_MODE',
'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0',
'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', 'MPCC_CONTROL_MPCC_MODE',
'MPCC_CONTROL_MPCC_MODE_BYPASS',
'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING',
'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY',
'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH',
'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM',
'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13',
'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', 'MPCC_GAMUT_REMAP_MODE_0',
'MPCC_GAMUT_REMAP_MODE_1', 'MPCC_GAMUT_REMAP_MODE_2',
'MPCC_GAMUT_REMAP_MODE_ENUM', 'MPCC_GAMUT_REMAP_MODE_RSV',
'MPCC_MCM_3DLUT_17CUBE', 'MPCC_MCM_3DLUT_30BIT',
'MPCC_MCM_3DLUT_30BIT_ENUM', 'MPCC_MCM_3DLUT_36BIT',
'MPCC_MCM_3DLUT_9CUBE', 'MPCC_MCM_3DLUT_RAM_SEL',
'MPCC_MCM_3DLUT_SIZE_ENUM', 'MPCC_MCM_GAMMA_LUT_BYPASS',
'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL',
'MPCC_MCM_GAMMA_LUT_MODE_ENUM',
'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM', 'MPCC_MCM_GAMMA_LUT_RAMA',
'MPCC_MCM_GAMMA_LUT_RAMB', 'MPCC_MCM_GAMMA_LUT_RAM_LUT',
'MPCC_MCM_GAMMA_LUT_RESERVED_1', 'MPCC_MCM_GAMMA_LUT_RESERVED_3',
'MPCC_MCM_GAMMA_LUT_SEL_ENUM',
'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM',
'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S2_13',
'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S3_12',
'MPCC_MCM_GAMUT_REMAP_MODE_0', 'MPCC_MCM_GAMUT_REMAP_MODE_1',
'MPCC_MCM_GAMUT_REMAP_MODE_2', 'MPCC_MCM_GAMUT_REMAP_MODE_ENUM',
'MPCC_MCM_GAMUT_REMAP_MODE_RSV', 'MPCC_MCM_LUT_2_MODE_BYPASS',
'MPCC_MCM_LUT_2_MODE_ENUM', 'MPCC_MCM_LUT_2_MODE_RAMA_LUT',
'MPCC_MCM_LUT_2_MODE_RAMB_LUT', 'MPCC_MCM_LUT_ALL_USE_R',
'MPCC_MCM_LUT_BLUE_LUT', 'MPCC_MCM_LUT_CONFIG_MODE',
'MPCC_MCM_LUT_DIFFERENT_RGB', 'MPCC_MCM_LUT_DISABLE_DEBUG',
'MPCC_MCM_LUT_ENABLE_DEBUG', 'MPCC_MCM_LUT_GREEN_LUT',
'MPCC_MCM_LUT_NUM_SEG', 'MPCC_MCM_LUT_RAMA_ACCESS',
'MPCC_MCM_LUT_RAMB_ACCESS', 'MPCC_MCM_LUT_RAM_SEL',
'MPCC_MCM_LUT_READ_COLOR_SEL', 'MPCC_MCM_LUT_READ_DBG',
'MPCC_MCM_LUT_RED_LUT', 'MPCC_MCM_LUT_SEGMENTS_1',
'MPCC_MCM_LUT_SEGMENTS_128', 'MPCC_MCM_LUT_SEGMENTS_16',
'MPCC_MCM_LUT_SEGMENTS_2', 'MPCC_MCM_LUT_SEGMENTS_32',
'MPCC_MCM_LUT_SEGMENTS_4', 'MPCC_MCM_LUT_SEGMENTS_64',
'MPCC_MCM_LUT_SEGMENTS_8', 'MPCC_MCM_MEM_PWR_FORCE_DIS',
'MPCC_MCM_MEM_PWR_FORCE_DS', 'MPCC_MCM_MEM_PWR_FORCE_ENUM',
'MPCC_MCM_MEM_PWR_FORCE_LS', 'MPCC_MCM_MEM_PWR_FORCE_SD',
'MPCC_MCM_MEM_PWR_STATE_DS', 'MPCC_MCM_MEM_PWR_STATE_ENUM',
'MPCC_MCM_MEM_PWR_STATE_LS', 'MPCC_MCM_MEM_PWR_STATE_ON',
'MPCC_MCM_MEM_PWR_STATE_SD', 'MPCC_MCM_RAM0_ACCESS',
'MPCC_MCM_RAM1_ACCESS', 'MPCC_MCM_RAM2_ACCESS',
'MPCC_MCM_RAM3_ACCESS', 'MPCC_OGAM_ALL_USE_R',
'MPCC_OGAM_BLUE_LUT', 'MPCC_OGAM_DIFFERENT_RGB',
'MPCC_OGAM_DISABLE_DEBUG', 'MPCC_OGAM_DISABLE_PWL',
'MPCC_OGAM_ENABLE_DEBUG', 'MPCC_OGAM_ENABLE_PWL',
'MPCC_OGAM_GREEN_LUT', 'MPCC_OGAM_LUT_2CFG_MEMORY_A',
'MPCC_OGAM_LUT_2CFG_MEMORY_B', 'MPCC_OGAM_LUT_2CFG_NO_MEMORY',
'MPCC_OGAM_LUT_2_CONFIG_ENUM', 'MPCC_OGAM_LUT_CONFIG_MODE',
'MPCC_OGAM_LUT_PWL_DISABLE_ENUM',
'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL',
'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA',
'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB',
'MPCC_OGAM_LUT_RAM_SEL', 'MPCC_OGAM_LUT_READ_COLOR_SEL',
'MPCC_OGAM_LUT_READ_DBG', 'MPCC_OGAM_LUT_SEL_ENUM',
'MPCC_OGAM_MODE_0', 'MPCC_OGAM_MODE_2',
'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM', 'MPCC_OGAM_MODE_RSV',
'MPCC_OGAM_MODE_RSV1', 'MPCC_OGAM_NUM_SEG', 'MPCC_OGAM_RAMA',
'MPCC_OGAM_RAMA_ACCESS', 'MPCC_OGAM_RAMB',
'MPCC_OGAM_RAMB_ACCESS', 'MPCC_OGAM_RED_LUT',
'MPCC_OGAM_SEGMENTS_1', 'MPCC_OGAM_SEGMENTS_128',
'MPCC_OGAM_SEGMENTS_16', 'MPCC_OGAM_SEGMENTS_2',
'MPCC_OGAM_SEGMENTS_32', 'MPCC_OGAM_SEGMENTS_4',
'MPCC_OGAM_SEGMENTS_64', 'MPCC_OGAM_SEGMENTS_8',
'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN',
'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE',
'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE',
'MPCC_SM_CONTROL_MPCC_SM_EN', 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE',
'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE',
'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT',
'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE',
'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED',
'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT',
'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE',
'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE',
'MPCC_SM_CONTROL_MPCC_SM_MODE',
'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING',
'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING',
'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING',
'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE',
'MPC_CFG_3DLUT_FL_FORMAT', 'MPC_CFG_3DLUT_FL_FORMAT_0',
'MPC_CFG_3DLUT_FL_FORMAT_1', 'MPC_CFG_3DLUT_FL_FORMAT_2',
'MPC_CFG_3DLUT_FL_MODE', 'MPC_CFG_3DLUT_FL_MODE_0',
'MPC_CFG_3DLUT_FL_MODE_1', 'MPC_CFG_3DLUT_FL_MODE_2',
'MPC_CFG_3DLUT_FL_MODE_3', 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET',
'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE',
'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET',
'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE',
'MPC_CFG_ADR_VUPDATE_LOCK_SET',
'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE',
'MPC_CFG_CFG_VUPDATE_LOCK_SET',
'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE',
'MPC_CFG_CUR_VUPDATE_LOCK_SET',
'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', 'MPC_CFG_MPC_TEST_CLK_SEL',
'MPC_CFG_MPC_TEST_CLK_SEL_0', 'MPC_CFG_MPC_TEST_CLK_SEL_1',
'MPC_CFG_MPC_TEST_CLK_SEL_2', 'MPC_CFG_MPC_TEST_CLK_SEL_3',
'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN',
'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE',
'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE',
'MPC_CRC_CALC_INTERLACE_MODE', 'MPC_CRC_CALC_MODE',
'MPC_CRC_CALC_STEREO_MODE', 'MPC_CRC_CONTINUOUS_MODE',
'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM',
'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH',
'MPC_CRC_INTERLACE_MODE_BOTTOM', 'MPC_CRC_INTERLACE_MODE_TOP',
'MPC_CRC_ONE_SHOT_MODE', 'MPC_CRC_SOURCE_SELECT',
'MPC_CRC_SOURCE_SEL_DPP', 'MPC_CRC_SOURCE_SEL_DWB',
'MPC_CRC_SOURCE_SEL_OPP', 'MPC_CRC_SOURCE_SEL_OTHER',
'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH',
'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT',
'MPC_CRC_STEREO_MODE_LEFT', 'MPC_CRC_STEREO_MODE_RIGHT',
'MPC_OCSC_COEF_FORMAT', 'MPC_OCSC_COEF_FORMAT_S2_13',
'MPC_OCSC_COEF_FORMAT_S3_12',
'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN',
'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE',
'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE',
'MPC_OUT_CSC_MODE', 'MPC_OUT_CSC_MODE_0', 'MPC_OUT_CSC_MODE_1',
'MPC_OUT_CSC_MODE_2', 'MPC_OUT_CSC_MODE_RSV',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH',
'MPC_OUT_RATE_CONTROL_DISABLE_SET',
'MPC_OUT_RATE_CONTROL_SET_DISABLE',
'MPC_OUT_RATE_CONTROL_SET_ENABLE',
'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED',
'MTYPE', 'MTYPE_CC', 'MTYPE_C_RO_S', 'MTYPE_C_RO_US',
'MTYPE_C_RW_S', 'MTYPE_C_RW_US', 'MTYPE_NC', 'MTYPE_RESERVED_1',
'MTYPE_RESERVED_5', 'MTYPE_RESERVED_7', 'MTYPE_UC', 'MTYPE_WC',
'MULTIPLE_BY1', 'MULTIPLE_BY2', 'MULTIPLE_BY3_RESERVED',
'MULTIPLE_BY4', 'MULTIPLE_RESERVED', 'MULT_16', 'MULT_8',
'MemArbMode', 'NON_BYPASS', 'NOT_FORCE_THE_CLOCK_DISABLED',
'NOT_SENT', 'NO_DIST', 'NO_DIV', 'NO_FORCE', 'NO_FORCE_REQ',
'NO_FORCE_REQUEST', 'NO_MIN_CHUNK_SIZE', 'NO_MIN_META_CHUNK_SIZE',
'NO_OUTSTANDING_REQ', 'NUM_SIMD_PER_CU', 'OBUF_BYPASS_DIS',
'OBUF_BYPASS_EN', 'OBUF_BYPASS_SEL', 'OBUF_FULL',
'OBUF_FULL_RECOUT', 'OBUF_HALF_RECOUT',
'OBUF_IS_HALF_RECOUT_WIDTH_SEL', 'OBUF_RECOUT',
'OBUF_USE_FULL_BUFFER_SEL', 'OFFCHIP_HS_DEALLOC', 'OFF_SEQ',
'OKAY', 'OKAY_NODATA', 'OMODE_BLEND', 'OMODE_O_THEN_B',
'OMODE_P_THEN_O_THEN_B', 'OMODE_RESERVED_3', 'ON_SEQ',
'OPPBUF_DISPLAY_SEGMENTATION',
'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT',
'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT',
'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT',
'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT',
'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT',
'OPP_PIPE_CLOCK_DISABLE', 'OPP_PIPE_CLOCK_ENABLE',
'OPP_PIPE_CLOCK_ENABLE_CONTROL', 'OPP_PIPE_CRC_CONT_EN',
'OPP_PIPE_CRC_DISABLE', 'OPP_PIPE_CRC_EN', 'OPP_PIPE_CRC_ENABLE',
'OPP_PIPE_CRC_INTERLACE_EN',
'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED',
'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE',
'OPP_PIPE_CRC_INTERLACE_MODE',
'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD',
'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD',
'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM',
'OPP_PIPE_CRC_INTERLACE_MODE_TOP', 'OPP_PIPE_CRC_MODE_CONTINUOUS',
'OPP_PIPE_CRC_MODE_ONE_SHOT', 'OPP_PIPE_CRC_ONE_SHOT_PENDING',
'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING',
'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING',
'OPP_PIPE_CRC_PIXEL_SELECT',
'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS',
'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS',
'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS',
'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED',
'OPP_PIPE_CRC_SOURCE_SELECT', 'OPP_PIPE_CRC_SOURCE_SELECT_FMT',
'OPP_PIPE_CRC_SOURCE_SELECT_SFT', 'OPP_PIPE_CRC_STEREO_EN',
'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO',
'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO',
'OPP_PIPE_CRC_STEREO_MODE',
'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE',
'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE',
'OPP_PIPE_CRC_STEREO_MODE_LEFT', 'OPP_PIPE_CRC_STEREO_MODE_RIGHT',
'OPP_PIPE_DIGTIAL_BYPASS_CONTROL',
'OPP_PIPE_DIGTIAL_BYPASS_DISABLE',
'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', 'OPP_TEST_CLK_SEL_CONTROL',
'OPP_TEST_CLK_SEL_DISPCLK_ABM0', 'OPP_TEST_CLK_SEL_DISPCLK_ABM1',
'OPP_TEST_CLK_SEL_DISPCLK_ABM2', 'OPP_TEST_CLK_SEL_DISPCLK_ABM3',
'OPP_TEST_CLK_SEL_DISPCLK_OPP0', 'OPP_TEST_CLK_SEL_DISPCLK_OPP1',
'OPP_TEST_CLK_SEL_DISPCLK_OPP2', 'OPP_TEST_CLK_SEL_DISPCLK_OPP3',
'OPP_TEST_CLK_SEL_DISPCLK_P', 'OPP_TEST_CLK_SEL_DISPCLK_R',
'OPP_TEST_CLK_SEL_RESERVED0', 'OPP_TEST_CLK_SEL_RESERVED1',
'OPP_TEST_CLK_SEL_RESERVED2', 'OPP_TEST_CLK_SEL_RESERVED3',
'OPP_TOP_CLOCK_DISABLED_STATUS', 'OPP_TOP_CLOCK_ENABLED_STATUS',
'OPP_TOP_CLOCK_ENABLE_STATUS', 'OPP_TOP_CLOCK_GATING_CONTROL',
'OPP_TOP_CLOCK_GATING_DISABLED', 'OPP_TOP_CLOCK_GATING_ENABLED',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5',
'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', 'OPT_COMB_MAX',
'OPT_COMB_MIN', 'OPT_COMB_NONE', 'OPT_COMB_REVSUBTRACT',
'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED',
'OTG_ADD_PIXEL', 'OTG_ADD_PIXEL_FORCE', 'OTG_ADD_PIXEL_NOOP',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE',
'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL',
'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP',
'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL',
'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY',
'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE',
'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE',
'OTG_CONTROL_OTG_MASTER_EN', 'OTG_CONTROL_OTG_MASTER_EN_FALSE',
'OTG_CONTROL_OTG_MASTER_EN_TRUE', 'OTG_CONTROL_OTG_OUT_MUX',
'OTG_CONTROL_OTG_OUT_MUX_0', 'OTG_CONTROL_OTG_OUT_MUX_1',
'OTG_CONTROL_OTG_OUT_MUX_2', 'OTG_CONTROL_OTG_START_POINT_CNTL',
'OTG_CONTROL_OTG_START_POINT_CNTL_DP',
'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL',
'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN',
'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE',
'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE',
'OTG_CRC_CNTL_OTG_CRC1_EN', 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE',
'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', 'OTG_CRC_CNTL_OTG_CRC_CONT_EN',
'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE',
'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE',
'OTG_CRC_CNTL_OTG_CRC_CONT_MODE',
'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET',
'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', 'OTG_CRC_CNTL_OTG_CRC_EN',
'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT',
'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS',
'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE',
'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B',
'OTG_DIG_UPDATE_VCOUNT_0', 'OTG_DIG_UPDATE_VCOUNT_1',
'OTG_DIG_UPDATE_VCOUNT_MODE', 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE',
'OTG_DLPC_CONTROL_OTG_RESYNC_MODE_0',
'OTG_DLPC_CONTROL_OTG_RESYNC_MODE_1',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE',
'OTG_DROP_PIXEL', 'OTG_DROP_PIXEL_FORCE', 'OTG_DROP_PIXEL_NOOP',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME',
'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN',
'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE',
'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5',
'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL',
'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL',
'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD',
'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL',
'OTG_GLOBAL_UPDATE_LOCK_DISABLE', 'OTG_GLOBAL_UPDATE_LOCK_EN',
'OTG_GLOBAL_UPDATE_LOCK_ENABLE', 'OTG_GSL_MASTER_MODE',
'OTG_GSL_MASTER_MODE_0', 'OTG_GSL_MASTER_MODE_1',
'OTG_GSL_MASTER_MODE_2', 'OTG_GSL_MASTER_MODE_3',
'OTG_HORZ_REPETITION_COUNT', 'OTG_HORZ_REPETITION_COUNT_0',
'OTG_HORZ_REPETITION_COUNT_1', 'OTG_HORZ_REPETITION_COUNT_10',
'OTG_HORZ_REPETITION_COUNT_11', 'OTG_HORZ_REPETITION_COUNT_12',
'OTG_HORZ_REPETITION_COUNT_13', 'OTG_HORZ_REPETITION_COUNT_14',
'OTG_HORZ_REPETITION_COUNT_15', 'OTG_HORZ_REPETITION_COUNT_2',
'OTG_HORZ_REPETITION_COUNT_3', 'OTG_HORZ_REPETITION_COUNT_4',
'OTG_HORZ_REPETITION_COUNT_5', 'OTG_HORZ_REPETITION_COUNT_6',
'OTG_HORZ_REPETITION_COUNT_7', 'OTG_HORZ_REPETITION_COUNT_8',
'OTG_HORZ_REPETITION_COUNT_9', 'OTG_H_SYNC_A_POL',
'OTG_H_SYNC_A_POL_HIGH', 'OTG_H_SYNC_A_POL_LOW',
'OTG_H_TIMING_DIV_MODE', 'OTG_H_TIMING_DIV_MODE_AUTO',
'OTG_H_TIMING_DIV_MODE_DIV_BY2', 'OTG_H_TIMING_DIV_MODE_DIV_BY4',
'OTG_H_TIMING_DIV_MODE_MANUAL', 'OTG_H_TIMING_DIV_MODE_NOAUTO',
'OTG_H_TIMING_DIV_MODE_NO_DIV', 'OTG_H_TIMING_DIV_MODE_RESERVED',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE',
'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE',
'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE',
'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE',
'OTG_MASTER_UPDATE_LOCK_DB_EN', 'OTG_MASTER_UPDATE_LOCK_DISABLE',
'OTG_MASTER_UPDATE_LOCK_ENABLE', 'OTG_MASTER_UPDATE_LOCK_GSL_EN',
'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE',
'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE',
'OTG_MASTER_UPDATE_LOCK_VCOUNT_0',
'OTG_MASTER_UPDATE_LOCK_VCOUNT_1',
'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB',
'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR',
'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE',
'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON',
'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL',
'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE',
'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE',
'OTG_STEREO_CONTROL_OTG_STEREO_EN',
'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE',
'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE',
'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY',
'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE',
'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE',
'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY',
'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE',
'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT',
'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR',
'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE',
'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1',
'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN',
'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE',
'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3',
'OTG_TRIGA_FREQUENCY_SELECT', 'OTG_TRIGA_FREQUENCY_SELECT_0',
'OTG_TRIGA_FREQUENCY_SELECT_1', 'OTG_TRIGA_FREQUENCY_SELECT_2',
'OTG_TRIGA_FREQUENCY_SELECT_3',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3',
'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR',
'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE',
'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1',
'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN',
'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE',
'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3',
'OTG_TRIGB_FREQUENCY_SELECT', 'OTG_TRIGB_FREQUENCY_SELECT_0',
'OTG_TRIGB_FREQUENCY_SELECT_1', 'OTG_TRIGB_FREQUENCY_SELECT_2',
'OTG_TRIGB_FREQUENCY_SELECT_3',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3',
'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK',
'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE',
'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB',
'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR',
'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE',
'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE',
'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR',
'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE',
'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE',
'OTG_VUPDATE_BLOCK_DISABLE', 'OTG_VUPDATE_BLOCK_DISABLE_OFF',
'OTG_VUPDATE_BLOCK_DISABLE_ON', 'OTG_V_SYNC_A_POL',
'OTG_V_SYNC_A_POL_HIGH', 'OTG_V_SYNC_A_POL_LOW',
'OTG_V_SYNC_MODE', 'OTG_V_SYNC_MODE_HBLANK',
'OTG_V_SYNC_MODE_HSYNC',
'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD',
'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0',
'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE',
'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK',
'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE',
'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE',
'OUTPUT_LINE', 'OUTPUT_POINT',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ',
'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', 'OUTSTANDING_REQ',
'OVERRUN', 'OreoMode', 'PART_FRAC_EVEN', 'PART_FRAC_ODD',
'PART_INTEGER', 'PART_POW2', 'PATCHES', 'PC_PERFCNT_SEL',
'PC_PERF_GE_GSDONE', 'PC_PERF_GL1_RTN_CNT_GT512',
'PC_PERF_GL1_RTN_CNT_GT768', 'PC_PERF_GL1_RTN_CNT_GTE1',
'PC_PERF_GRBM_BUSY', 'PC_PERF_LWC0_PC_MEM_READ_STALL',
'PC_PERF_LWC0_PKR2_SA_BDRY_CROSSING',
'PC_PERF_LWC0_PKR3_SA_BDRY_CROSSING',
'PC_PERF_LWC0_PROBE_ORDER_STALL',
'PC_PERF_LWC1_PC_MEM_READ_STALL',
'PC_PERF_LWC1_PKR0_SA_BDRY_CROSSING',
'PC_PERF_LWC1_PKR1_SA_BDRY_CROSSING',
'PC_PERF_LWC1_PROBE_ORDER_STALL',
'PC_PERF_MW_CACHE_CNTL_FULL_STALL', 'PC_PERF_MW_CACHE_HIT',
'PC_PERF_MW_CACHE_MISS', 'PC_PERF_MW_CACHE_REUSE',
'PC_PERF_MW_DEALLOC_HIT', 'PC_PERF_MW_DLINE_ALLOC',
'PC_PERF_MW_DLINE_DEALLOC', 'PC_PERF_MW_GL1H_NUM_REQS',
'PC_PERF_MW_GL1H_REQ_FREEZE', 'PC_PERF_MW_PHY_DLINE_FULL_STALL',
'PC_PERF_MW_PROBE_CNT_FREEZE', 'PC_PERF_MW_RTN_ADDR_FREEZE',
'PC_PERF_MW_STAMP_LIMIT_STALL', 'PC_PERF_MW_TAGLINE_ALLOC',
'PC_PERF_MW_TAGLINE_DEALLOC', 'PC_PERF_NUM_PSWAVE',
'PC_PERF_PC_LDS_CNTL_VALID0', 'PC_PERF_PC_LDS_CNTL_VALID1',
'PC_PERF_PC_LDS_VERTEX_REUSE0', 'PC_PERF_PC_LDS_VERTEX_REUSE1',
'PC_PERF_PC_MEM_BANK_CONF0', 'PC_PERF_PC_MEM_BANK_CONF1',
'PC_PERF_PC_SPI_PROBE_FREEZE',
'PC_PERF_PC_SPI_PROBE_OUT_OF_CREDIT', 'PC_PERF_PKR0_FPOSG_EQ1',
'PC_PERF_PKR0_FPOSG_GT1', 'PC_PERF_PKR0_FPOSG_GT128',
'PC_PERF_PKR0_FPOSG_GT16', 'PC_PERF_PKR0_FPOSG_GT64',
'PC_PERF_PKR0_FPOSG_OUT_OF_WAVE',
'PC_PERF_PKR0_GSDONE_WHILE_IDLE', 'PC_PERF_PKR0_NUM_PROBES',
'PC_PERF_PKR0_NUM_WAVES', 'PC_PERF_PKR0_PRIMS_PER_PROBE_EQ1',
'PC_PERF_PKR0_PRIMS_PER_PROBE_GT1',
'PC_PERF_PKR0_PRIMS_PER_PROBE_GT2',
'PC_PERF_PKR0_PRIMS_PER_PROBE_GT4',
'PC_PERF_PKR0_PRIMS_PER_PROBE_GT8',
'PC_PERF_PKR0_PRIMS_PER_WAVE_EQ1',
'PC_PERF_PKR0_PRIMS_PER_WAVE_GT1',
'PC_PERF_PKR0_PRIMS_PER_WAVE_GT2',
'PC_PERF_PKR0_PRIMS_PER_WAVE_GT4',
'PC_PERF_PKR0_PRIMS_PER_WAVE_GT8', 'PC_PERF_PKR0_PRIMS_REUSE',
'PC_PERF_PKR0_PROBES_PER_WAVE_EQ1',
'PC_PERF_PKR0_PROBES_PER_WAVE_GT1',
'PC_PERF_PKR0_PROBES_PER_WAVE_GT2',
'PC_PERF_PKR0_PROBES_PER_WAVE_GT4',
'PC_PERF_PKR0_PROBES_PER_WAVE_GT8', 'PC_PERF_PKR1_FPOSG_EQ1',
'PC_PERF_PKR1_FPOSG_GT1', 'PC_PERF_PKR1_FPOSG_GT128',
'PC_PERF_PKR1_FPOSG_GT16', 'PC_PERF_PKR1_FPOSG_GT64',
'PC_PERF_PKR1_FPOSG_OUT_OF_WAVE',
'PC_PERF_PKR1_GSDONE_WHILE_IDLE', 'PC_PERF_PKR1_NUM_PROBES',
'PC_PERF_PKR1_NUM_WAVES', 'PC_PERF_PKR1_PRIMS_PER_PROBE_EQ1',
'PC_PERF_PKR1_PRIMS_PER_PROBE_GT1',
'PC_PERF_PKR1_PRIMS_PER_PROBE_GT2',
'PC_PERF_PKR1_PRIMS_PER_PROBE_GT4',
'PC_PERF_PKR1_PRIMS_PER_PROBE_GT8',
'PC_PERF_PKR1_PRIMS_PER_WAVE_EQ1',
'PC_PERF_PKR1_PRIMS_PER_WAVE_GT1',
'PC_PERF_PKR1_PRIMS_PER_WAVE_GT2',
'PC_PERF_PKR1_PRIMS_PER_WAVE_GT4',
'PC_PERF_PKR1_PRIMS_PER_WAVE_GT8', 'PC_PERF_PKR1_PRIMS_REUSE',
'PC_PERF_PKR1_PROBES_PER_WAVE_EQ1',
'PC_PERF_PKR1_PROBES_PER_WAVE_GT1',
'PC_PERF_PKR1_PROBES_PER_WAVE_GT2',
'PC_PERF_PKR1_PROBES_PER_WAVE_GT4',
'PC_PERF_PKR1_PROBES_PER_WAVE_GT8', 'PC_PERF_PKR2_FPOSG_EQ1',
'PC_PERF_PKR2_FPOSG_GT1', 'PC_PERF_PKR2_FPOSG_GT128',
'PC_PERF_PKR2_FPOSG_GT16', 'PC_PERF_PKR2_FPOSG_GT64',
'PC_PERF_PKR2_FPOSG_OUT_OF_WAVE',
'PC_PERF_PKR2_GSDONE_WHILE_IDLE', 'PC_PERF_PKR2_NUM_PROBES',
'PC_PERF_PKR2_NUM_WAVES', 'PC_PERF_PKR2_PRIMS_PER_PROBE_EQ1',
'PC_PERF_PKR2_PRIMS_PER_PROBE_GT1',
'PC_PERF_PKR2_PRIMS_PER_PROBE_GT2',
'PC_PERF_PKR2_PRIMS_PER_PROBE_GT4',
'PC_PERF_PKR2_PRIMS_PER_PROBE_GT8',
'PC_PERF_PKR2_PRIMS_PER_WAVE_EQ1',
'PC_PERF_PKR2_PRIMS_PER_WAVE_GT1',
'PC_PERF_PKR2_PRIMS_PER_WAVE_GT2',
'PC_PERF_PKR2_PRIMS_PER_WAVE_GT4',
'PC_PERF_PKR2_PRIMS_PER_WAVE_GT8', 'PC_PERF_PKR2_PRIMS_REUSE',
'PC_PERF_PKR2_PROBES_PER_WAVE_EQ1',
'PC_PERF_PKR2_PROBES_PER_WAVE_GT1',
'PC_PERF_PKR2_PROBES_PER_WAVE_GT2',
'PC_PERF_PKR2_PROBES_PER_WAVE_GT4',
'PC_PERF_PKR2_PROBES_PER_WAVE_GT8', 'PC_PERF_PKR3_FPOSG_EQ1',
'PC_PERF_PKR3_FPOSG_GT1', 'PC_PERF_PKR3_FPOSG_GT128',
'PC_PERF_PKR3_FPOSG_GT16', 'PC_PERF_PKR3_FPOSG_GT64',
'PC_PERF_PKR3_FPOSG_OUT_OF_WAVE',
'PC_PERF_PKR3_GSDONE_WHILE_IDLE', 'PC_PERF_PKR3_NUM_PROBES',
'PC_PERF_PKR3_NUM_WAVES', 'PC_PERF_PKR3_PRIMS_PER_PROBE_EQ1',
'PC_PERF_PKR3_PRIMS_PER_PROBE_GT1',
'PC_PERF_PKR3_PRIMS_PER_PROBE_GT2',
'PC_PERF_PKR3_PRIMS_PER_PROBE_GT4',
'PC_PERF_PKR3_PRIMS_PER_PROBE_GT8',
'PC_PERF_PKR3_PRIMS_PER_WAVE_EQ1',
'PC_PERF_PKR3_PRIMS_PER_WAVE_GT1',
'PC_PERF_PKR3_PRIMS_PER_WAVE_GT2',
'PC_PERF_PKR3_PRIMS_PER_WAVE_GT4',
'PC_PERF_PKR3_PRIMS_PER_WAVE_GT8', 'PC_PERF_PKR3_PRIMS_REUSE',
'PC_PERF_PKR3_PROBES_PER_WAVE_EQ1',
'PC_PERF_PKR3_PROBES_PER_WAVE_GT1',
'PC_PERF_PKR3_PROBES_PER_WAVE_GT2',
'PC_PERF_PKR3_PROBES_PER_WAVE_GT4',
'PC_PERF_PKR3_PROBES_PER_WAVE_GT8', 'PC_PERF_SC_FPOSG0',
'PC_PERF_SC_FPOSG1', 'PC_PERF_SC_FPOSG2', 'PC_PERF_SC_FPOSG3',
'PC_PERF_SC_FPOSG_WAIT0', 'PC_PERF_SC_FPOSG_WAIT1',
'PC_PERF_SC_FPOSG_WAIT2', 'PC_PERF_SC_FPOSG_WAIT3',
'PC_PERF_SC_MW_FREEZE', 'PC_PERF_SC_NUM_PROBES',
'PC_PERF_SC_NUM_SPLIT_WAVES', 'PC_PERF_SC_NUM_WAVES',
'PC_PERF_SC_PC_PTR_SEND0', 'PC_PERF_SC_PC_PTR_SEND1',
'PC_PERF_SC_PC_PTR_SEND2', 'PC_PERF_SC_PC_PTR_SEND3',
'PC_PERF_SC_PC_PTR_VALID0', 'PC_PERF_SC_PC_PTR_VALID1',
'PC_PERF_SC_PC_PTR_VALID2', 'PC_PERF_SC_PC_PTR_VALID3',
'PC_PERF_SC_PQ_FREEZE0', 'PC_PERF_SC_PQ_FREEZE1',
'PC_PERF_SC_PQ_FREEZE2', 'PC_PERF_SC_PQ_FREEZE3',
'PC_PERF_SC_WAIT_SYNC0', 'PC_PERF_SC_WAIT_SYNC1',
'PC_PERF_SC_WAIT_SYNC2', 'PC_PERF_SC_WAIT_SYNC3',
'PERFCOUNTER_ACTIVE', 'PERFCOUNTER_CNT0_STATE',
'PERFCOUNTER_CNT0_STATE_FREEZE', 'PERFCOUNTER_CNT0_STATE_HW',
'PERFCOUNTER_CNT0_STATE_RESET', 'PERFCOUNTER_CNT0_STATE_START',
'PERFCOUNTER_CNT1_STATE', 'PERFCOUNTER_CNT1_STATE_FREEZE',
'PERFCOUNTER_CNT1_STATE_HW', 'PERFCOUNTER_CNT1_STATE_RESET',
'PERFCOUNTER_CNT1_STATE_START', 'PERFCOUNTER_CNT2_STATE',
'PERFCOUNTER_CNT2_STATE_FREEZE', 'PERFCOUNTER_CNT2_STATE_HW',
'PERFCOUNTER_CNT2_STATE_RESET', 'PERFCOUNTER_CNT2_STATE_START',
'PERFCOUNTER_CNT3_STATE', 'PERFCOUNTER_CNT3_STATE_FREEZE',
'PERFCOUNTER_CNT3_STATE_HW', 'PERFCOUNTER_CNT3_STATE_RESET',
'PERFCOUNTER_CNT3_STATE_START', 'PERFCOUNTER_CNT4_STATE',
'PERFCOUNTER_CNT4_STATE_FREEZE', 'PERFCOUNTER_CNT4_STATE_HW',
'PERFCOUNTER_CNT4_STATE_RESET', 'PERFCOUNTER_CNT4_STATE_START',
'PERFCOUNTER_CNT5_STATE', 'PERFCOUNTER_CNT5_STATE_FREEZE',
'PERFCOUNTER_CNT5_STATE_HW', 'PERFCOUNTER_CNT5_STATE_RESET',
'PERFCOUNTER_CNT5_STATE_START', 'PERFCOUNTER_CNT6_STATE',
'PERFCOUNTER_CNT6_STATE_FREEZE', 'PERFCOUNTER_CNT6_STATE_HW',
'PERFCOUNTER_CNT6_STATE_RESET', 'PERFCOUNTER_CNT6_STATE_START',
'PERFCOUNTER_CNT7_STATE', 'PERFCOUNTER_CNT7_STATE_FREEZE',
'PERFCOUNTER_CNT7_STATE_HW', 'PERFCOUNTER_CNT7_STATE_RESET',
'PERFCOUNTER_CNT7_STATE_START', 'PERFCOUNTER_CNTL_SEL',
'PERFCOUNTER_CNTL_SEL_0', 'PERFCOUNTER_CNTL_SEL_1',
'PERFCOUNTER_CNTL_SEL_2', 'PERFCOUNTER_CNTL_SEL_3',
'PERFCOUNTER_CNTL_SEL_4', 'PERFCOUNTER_CNTL_SEL_5',
'PERFCOUNTER_CNTL_SEL_6', 'PERFCOUNTER_CNTL_SEL_7',
'PERFCOUNTER_CNTOFF_START_DIS',
'PERFCOUNTER_CNTOFF_START_DISABLE',
'PERFCOUNTER_CNTOFF_START_ENABLE',
'PERFCOUNTER_COUNTED_VALUE_TYPE',
'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC',
'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX',
'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL',
'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0',
'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16',
'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0',
'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36',
'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF',
'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_HW_STOP1_0',
'PERFCOUNTER_HW_STOP1_1', 'PERFCOUNTER_HW_STOP1_SEL',
'PERFCOUNTER_HW_STOP2_0', 'PERFCOUNTER_HW_STOP2_1',
'PERFCOUNTER_HW_STOP2_SEL', 'PERFCOUNTER_INC_MODE',
'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB',
'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE',
'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE',
'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE',
'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL',
'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE',
'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK',
'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE',
'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN',
'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE',
'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL',
'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START',
'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL',
'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1',
'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL',
'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL',
'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3',
'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL',
'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL',
'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5',
'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL',
'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL',
'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7',
'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL',
'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR',
'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN',
'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE',
'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE',
'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE',
'PERFMON_COUNTER_MODE_ACCUM',
'PERFMON_COUNTER_MODE_ACTIVE_CYCLES',
'PERFMON_COUNTER_MODE_CYCLES_EQ_HI',
'PERFMON_COUNTER_MODE_CYCLES_GE_HI',
'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT',
'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT',
'PERFMON_COUNTER_MODE_DIRTY',
'PERFMON_COUNTER_MODE_INACTIVE_CYCLES',
'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED',
'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE',
'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP',
'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP',
'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5',
'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7',
'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1',
'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE',
'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET',
'PERFMON_STATE_START', 'PERF_CLIPSM_CULL_PRIMS_CNT',
'PERF_CLPR_BACK_PRIM', 'PERF_CLPR_CLIP_PLANE_CNT_9_PLUS',
'PERF_CLPR_INPUT_END_OF_PACKET', 'PERF_CLPR_INPUT_EVENT',
'PERF_CLPR_INPUT_EXTENDED_EVENT',
'PERF_CLPR_INPUT_FIRST_OF_SUBGROUP', 'PERF_CLPR_INPUT_NULL_PRIM',
'PERF_CLPR_INPUT_PRIM', 'PERF_CLPR_INPUT_SEND', 'PERF_ENGG_BUSY',
'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL',
'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT',
'PERF_ENGG_CSB_GE_MEMORY_EMPTY', 'PERF_ENGG_CSB_GE_MEMORY_FULL',
'PERF_ENGG_CSB_GE_SENDING_SUBGROUP',
'PERF_ENGG_CSB_MACHINE_IS_STARVED',
'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY',
'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI',
'PERF_ENGG_CSB_NULL_SUBGROUP',
'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL',
'PERF_ENGG_CSB_PRIM_COUNT_EQ0', 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY',
'PERF_ENGG_CSB_SPI_MEMORY_FULL',
'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE',
'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE',
'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO',
'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO',
'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB',
'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM',
'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL',
'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL',
'PERF_ENGG_INDEX_REQ_NULL_REQUEST',
'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS',
'PERF_ENGG_INDEX_REQ_STARVED', 'PERF_ENGG_INDEX_RET0_NEW_VERTS',
'PERF_ENGG_INDEX_RET10_NEW_VERTS',
'PERF_ENGG_INDEX_RET11_NEW_VERTS',
'PERF_ENGG_INDEX_RET12_NEW_VERTS',
'PERF_ENGG_INDEX_RET1_NEW_VERTS',
'PERF_ENGG_INDEX_RET2_NEW_VERTS',
'PERF_ENGG_INDEX_RET3_NEW_VERTS',
'PERF_ENGG_INDEX_RET4_NEW_VERTS',
'PERF_ENGG_INDEX_RET5_NEW_VERTS',
'PERF_ENGG_INDEX_RET6_NEW_VERTS',
'PERF_ENGG_INDEX_RET7_NEW_VERTS',
'PERF_ENGG_INDEX_RET8_NEW_VERTS',
'PERF_ENGG_INDEX_RET9_NEW_VERTS',
'PERF_ENGG_INDEX_RET_0_NEW_VERTS_THIS_PRIM',
'PERF_ENGG_INDEX_RET_1_NEW_VERTS_THIS_PRIM',
'PERF_ENGG_INDEX_RET_2_NEW_VERTS_THIS_PRIM',
'PERF_ENGG_INDEX_RET_3_NEW_VERTS_THIS_PRIM',
'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY',
'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL',
'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO',
'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT',
'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL',
'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0',
'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO',
'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO',
'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB',
'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS',
'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL',
'PERF_ENGG_POS_REQ_STARVED', 'PERF_OUTPUT_PRIM_1_SC',
'PERF_OUTPUT_PRIM_2_SC', 'PERF_OUTPUT_PRIM_3_SC',
'PERF_OUTPUT_PRIM_4_SC', 'PERF_OUTPUT_PRIM_5_SC',
'PERF_OUTPUT_PRIM_6_SC', 'PERF_PAPC_CCGSM_BUSY',
'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED',
'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE',
'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP',
'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY',
'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP',
'PERF_PAPC_CLIPSM_WAIT_CLIPGA',
'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM',
'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH',
'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY',
'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY',
'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED',
'PERF_PAPC_CLPRIM_STARVED_CCGSM',
'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8',
'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT',
'PERF_PAPC_CLPR_CLIP_PLANE_NEAR',
'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT',
'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM',
'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM',
'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE',
'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM',
'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM',
'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM',
'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM',
'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM',
'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM',
'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM',
'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM',
'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2',
'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4',
'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8',
'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_PLUS',
'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM',
'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_REC_BUSY',
'PERF_PAPC_PASX_REC_IDLE', 'PERF_PAPC_PASX_REC_STALLED',
'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN',
'PERF_PAPC_PASX_REC_STALLED_POS_MEM',
'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ',
'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE',
'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_VTX_KILL_DISCARD',
'PERF_PAPC_PASX_VTX_NAN_DISCARD', 'PERF_PAPC_PA_REG_SCLK_VLD',
'PERF_PAPC_SU_ALL_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_ALL_OUTPUT_PRIM', 'PERF_PAPC_SU_ALL_STALLED_SC',
'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', 'PERF_PAPC_SU_BUSY',
'PERF_PAPC_SU_CULLED_PRIM', 'PERF_PAPC_SU_DYN_SCLK_VLD',
'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', 'PERF_PAPC_SU_IDLE',
'PERF_PAPC_SU_INPUT_CLIP_PRIM',
'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL',
'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM',
'PERF_PAPC_SU_INPUT_PRIM_DUAL',
'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL',
'PERF_PAPC_SU_OUTPUT_CLIP_PRIM',
'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL',
'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG',
'PERF_PAPC_SU_OUTPUT_EVENT_FLAG',
'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT',
'PERF_PAPC_SU_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK',
'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL',
'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE',
'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM',
'PERF_PAPC_SU_OUTPUT_PRIM_DUAL',
'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK',
'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE',
'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT',
'PERF_PAPC_SU_POLYMODE_BACK_CULL',
'PERF_PAPC_SU_POLYMODE_FACE_CULL',
'PERF_PAPC_SU_POLYMODE_FRONT_CULL',
'PERF_PAPC_SU_POLYMODE_INVALID_FILL',
'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE0_OUTPUT_PRIM',
'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE0_STALLED_SC',
'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE1_OUTPUT_PRIM',
'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE1_STALLED_SC',
'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE2_OUTPUT_PRIM',
'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE2_STALLED_SC',
'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE3_OUTPUT_PRIM',
'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE3_STALLED_SC',
'PERF_PAPC_SU_SE4_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE4_OUTPUT_PRIM',
'PERF_PAPC_SU_SE4_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE4_STALLED_SC',
'PERF_PAPC_SU_SE5_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE5_OUTPUT_PRIM',
'PERF_PAPC_SU_SE5_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE5_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC',
'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM',
'PERF_PASX_CCDIST0_VECTOR', 'PERF_PASX_CCDIST1_VECTOR',
'PERF_PASX_MISC_VECTOR', 'PERF_PASX_POS_VECTOR',
'PERF_PASX_STEREO_POS_VECTOR', 'PERF_PA_BUSY',
'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL',
'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', 'PERF_PA_VERTEX_FIFO_FULL',
'PERF_PH_SEND_1_SC', 'PERF_PH_SEND_2_SC', 'PERF_PH_SEND_3_SC',
'PERF_PH_SEND_4_SC', 'PERF_PH_SEND_5_SC', 'PERF_PH_SEND_6_SC',
'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT',
'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT',
'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT',
'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT',
'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT',
'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT',
'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT',
'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT',
'PERF_SMALL_PRIM_CULL_PRIM_1X1', 'PERF_SMALL_PRIM_CULL_PRIM_1X2',
'PERF_SMALL_PRIM_CULL_PRIM_1X3', 'PERF_SMALL_PRIM_CULL_PRIM_1XN',
'PERF_SMALL_PRIM_CULL_PRIM_2X1', 'PERF_SMALL_PRIM_CULL_PRIM_2X2',
'PERF_SMALL_PRIM_CULL_PRIM_2X3', 'PERF_SMALL_PRIM_CULL_PRIM_2XN',
'PERF_SMALL_PRIM_CULL_PRIM_3X1', 'PERF_SMALL_PRIM_CULL_PRIM_3X2',
'PERF_SMALL_PRIM_CULL_PRIM_NX1', 'PERF_SMALL_PRIM_CULL_PRIM_NX2',
'PERF_SU_INPUT_SEND', 'PERF_SU_OUTPUT_SEND',
'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', 'PERSISTENT_SPACE_END',
'PERSISTENT_SPACE_START', 'PFVF_SQDEC_BEGIN', 'PFVF_SQDEC_END',
'PHYSYMCLK_FORCE_EN', 'PHYSYMCLK_FORCE_EN_DISABLE',
'PHYSYMCLK_FORCE_EN_ENABLE', 'PHYSYMCLK_FORCE_SRC_PHYD18CLK',
'PHYSYMCLK_FORCE_SRC_PHYD32CLK', 'PHYSYMCLK_FORCE_SRC_SEL',
'PHYSYMCLK_FORCE_SRC_SYMCLK', 'PHY_MUX_ENABLE_ENUM',
'PHY_MUX_ENABLE_ENUM_DISABLED', 'PHY_MUX_ENABLE_ENUM_ENABLED',
'PH_PERFCNT_SEL', 'PH_PERF_SC0_FIFO_STATUS_0',
'PH_PERF_SC0_FIFO_STATUS_1', 'PH_PERF_SC0_FIFO_STATUS_2',
'PH_PERF_SC0_FIFO_STATUS_3', 'PH_PERF_SC1_FIFO_STATUS_0',
'PH_PERF_SC1_FIFO_STATUS_1', 'PH_PERF_SC1_FIFO_STATUS_2',
'PH_PERF_SC1_FIFO_STATUS_3', 'PH_PERF_SC2_FIFO_STATUS_0',
'PH_PERF_SC2_FIFO_STATUS_1', 'PH_PERF_SC2_FIFO_STATUS_2',
'PH_PERF_SC2_FIFO_STATUS_3', 'PH_PERF_SC3_FIFO_STATUS_0',
'PH_PERF_SC3_FIFO_STATUS_1', 'PH_PERF_SC3_FIFO_STATUS_2',
'PH_PERF_SC3_FIFO_STATUS_3', 'PH_PERF_SC4_FIFO_STATUS_0',
'PH_PERF_SC4_FIFO_STATUS_1', 'PH_PERF_SC4_FIFO_STATUS_2',
'PH_PERF_SC4_FIFO_STATUS_3', 'PH_PERF_SC5_FIFO_STATUS_0',
'PH_PERF_SC5_FIFO_STATUS_1', 'PH_PERF_SC5_FIFO_STATUS_2',
'PH_PERF_SC5_FIFO_STATUS_3', 'PH_PERF_SC6_FIFO_STATUS_0',
'PH_PERF_SC6_FIFO_STATUS_1', 'PH_PERF_SC6_FIFO_STATUS_2',
'PH_PERF_SC6_FIFO_STATUS_3', 'PH_PERF_SC7_FIFO_STATUS_0',
'PH_PERF_SC7_FIFO_STATUS_1', 'PH_PERF_SC7_FIFO_STATUS_2',
'PH_PERF_SC7_FIFO_STATUS_3',
'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC0_ARB_BUSY',
'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC0_CREDIT_AT_MAX',
'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA0_EOPG_WE',
'PH_PERF_SEL_SC0_PA0_EOP_WE', 'PH_PERF_SEL_SC0_PA0_EVENT_WE',
'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA0_FIFO_FULL',
'PH_PERF_SEL_SC0_PA0_FPOP_WE', 'PH_PERF_SEL_SC0_PA0_FPOV_WE',
'PH_PERF_SEL_SC0_PA0_NULL_WE',
'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA1_EOPG_WE',
'PH_PERF_SEL_SC0_PA1_EOP_WE', 'PH_PERF_SEL_SC0_PA1_EVENT_WE',
'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA1_FIFO_FULL',
'PH_PERF_SEL_SC0_PA1_FPOP_WE', 'PH_PERF_SEL_SC0_PA1_FPOV_WE',
'PH_PERF_SEL_SC0_PA1_NULL_WE',
'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA2_EOPG_WE',
'PH_PERF_SEL_SC0_PA2_EOP_WE', 'PH_PERF_SEL_SC0_PA2_EVENT_WE',
'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA2_FIFO_FULL',
'PH_PERF_SEL_SC0_PA2_FPOP_WE', 'PH_PERF_SEL_SC0_PA2_FPOV_WE',
'PH_PERF_SEL_SC0_PA2_NULL_WE',
'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA3_EOPG_WE',
'PH_PERF_SEL_SC0_PA3_EOP_WE', 'PH_PERF_SEL_SC0_PA3_EVENT_WE',
'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA3_FIFO_FULL',
'PH_PERF_SEL_SC0_PA3_FPOP_WE', 'PH_PERF_SEL_SC0_PA3_FPOV_WE',
'PH_PERF_SEL_SC0_PA3_NULL_WE',
'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA4_EOPG_WE',
'PH_PERF_SEL_SC0_PA4_EOP_WE', 'PH_PERF_SEL_SC0_PA4_EVENT_WE',
'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA4_FIFO_FULL',
'PH_PERF_SEL_SC0_PA4_FPOP_WE', 'PH_PERF_SEL_SC0_PA4_FPOV_WE',
'PH_PERF_SEL_SC0_PA4_NULL_WE',
'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA5_EOPG_WE',
'PH_PERF_SEL_SC0_PA5_EOP_WE', 'PH_PERF_SEL_SC0_PA5_EVENT_WE',
'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA5_FIFO_FULL',
'PH_PERF_SEL_SC0_PA5_FPOP_WE', 'PH_PERF_SEL_SC0_PA5_FPOV_WE',
'PH_PERF_SEL_SC0_PA5_NULL_WE',
'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA6_EOPG_WE',
'PH_PERF_SEL_SC0_PA6_EOP_WE', 'PH_PERF_SEL_SC0_PA6_EVENT_WE',
'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA6_FIFO_FULL',
'PH_PERF_SEL_SC0_PA6_FPOP_WE', 'PH_PERF_SEL_SC0_PA6_FPOV_WE',
'PH_PERF_SEL_SC0_PA6_NULL_WE',
'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA7_EOPG_WE',
'PH_PERF_SEL_SC0_PA7_EOP_WE', 'PH_PERF_SEL_SC0_PA7_EVENT_WE',
'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA7_FIFO_FULL',
'PH_PERF_SEL_SC0_PA7_FPOP_WE', 'PH_PERF_SEL_SC0_PA7_FPOV_WE',
'PH_PERF_SEL_SC0_PA7_NULL_WE',
'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC0_SEND', 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC1_ARB_BUSY',
'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC1_CREDIT_AT_MAX',
'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA0_EOPG_WE',
'PH_PERF_SEL_SC1_PA0_EOP_WE', 'PH_PERF_SEL_SC1_PA0_EVENT_WE',
'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA0_FIFO_FULL',
'PH_PERF_SEL_SC1_PA0_FPOP_WE', 'PH_PERF_SEL_SC1_PA0_FPOV_WE',
'PH_PERF_SEL_SC1_PA0_NULL_WE',
'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA1_EOPG_WE',
'PH_PERF_SEL_SC1_PA1_EOP_WE', 'PH_PERF_SEL_SC1_PA1_EVENT_WE',
'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA1_FIFO_FULL',
'PH_PERF_SEL_SC1_PA1_FPOP_WE', 'PH_PERF_SEL_SC1_PA1_FPOV_WE',
'PH_PERF_SEL_SC1_PA1_NULL_WE',
'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA2_EOPG_WE',
'PH_PERF_SEL_SC1_PA2_EOP_WE', 'PH_PERF_SEL_SC1_PA2_EVENT_WE',
'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA2_FIFO_FULL',
'PH_PERF_SEL_SC1_PA2_FPOP_WE', 'PH_PERF_SEL_SC1_PA2_FPOV_WE',
'PH_PERF_SEL_SC1_PA2_NULL_WE',
'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA3_EOPG_WE',
'PH_PERF_SEL_SC1_PA3_EOP_WE', 'PH_PERF_SEL_SC1_PA3_EVENT_WE',
'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA3_FIFO_FULL',
'PH_PERF_SEL_SC1_PA3_FPOP_WE', 'PH_PERF_SEL_SC1_PA3_FPOV_WE',
'PH_PERF_SEL_SC1_PA3_NULL_WE',
'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA4_EOPG_WE',
'PH_PERF_SEL_SC1_PA4_EOP_WE', 'PH_PERF_SEL_SC1_PA4_EVENT_WE',
'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA4_FIFO_FULL',
'PH_PERF_SEL_SC1_PA4_FPOP_WE', 'PH_PERF_SEL_SC1_PA4_FPOV_WE',
'PH_PERF_SEL_SC1_PA4_NULL_WE',
'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA5_EOPG_WE',
'PH_PERF_SEL_SC1_PA5_EOP_WE', 'PH_PERF_SEL_SC1_PA5_EVENT_WE',
'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA5_FIFO_FULL',
'PH_PERF_SEL_SC1_PA5_FPOP_WE', 'PH_PERF_SEL_SC1_PA5_FPOV_WE',
'PH_PERF_SEL_SC1_PA5_NULL_WE',
'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA6_EOPG_WE',
'PH_PERF_SEL_SC1_PA6_EOP_WE', 'PH_PERF_SEL_SC1_PA6_EVENT_WE',
'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA6_FIFO_FULL',
'PH_PERF_SEL_SC1_PA6_FPOP_WE', 'PH_PERF_SEL_SC1_PA6_FPOV_WE',
'PH_PERF_SEL_SC1_PA6_NULL_WE',
'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA7_EOPG_WE',
'PH_PERF_SEL_SC1_PA7_EOP_WE', 'PH_PERF_SEL_SC1_PA7_EVENT_WE',
'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA7_FIFO_FULL',
'PH_PERF_SEL_SC1_PA7_FPOP_WE', 'PH_PERF_SEL_SC1_PA7_FPOV_WE',
'PH_PERF_SEL_SC1_PA7_NULL_WE',
'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC1_SEND', 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC2_ARB_BUSY',
'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC2_CREDIT_AT_MAX',
'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA0_EOPG_WE',
'PH_PERF_SEL_SC2_PA0_EOP_WE', 'PH_PERF_SEL_SC2_PA0_EVENT_WE',
'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA0_FIFO_FULL',
'PH_PERF_SEL_SC2_PA0_FPOP_WE', 'PH_PERF_SEL_SC2_PA0_FPOV_WE',
'PH_PERF_SEL_SC2_PA0_NULL_WE',
'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA1_EOPG_WE',
'PH_PERF_SEL_SC2_PA1_EOP_WE', 'PH_PERF_SEL_SC2_PA1_EVENT_WE',
'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA1_FIFO_FULL',
'PH_PERF_SEL_SC2_PA1_FPOP_WE', 'PH_PERF_SEL_SC2_PA1_FPOV_WE',
'PH_PERF_SEL_SC2_PA1_NULL_WE',
'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA2_EOPG_WE',
'PH_PERF_SEL_SC2_PA2_EOP_WE', 'PH_PERF_SEL_SC2_PA2_EVENT_WE',
'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA2_FIFO_FULL',
'PH_PERF_SEL_SC2_PA2_FPOP_WE', 'PH_PERF_SEL_SC2_PA2_FPOV_WE',
'PH_PERF_SEL_SC2_PA2_NULL_WE',
'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA3_EOPG_WE',
'PH_PERF_SEL_SC2_PA3_EOP_WE', 'PH_PERF_SEL_SC2_PA3_EVENT_WE',
'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA3_FIFO_FULL',
'PH_PERF_SEL_SC2_PA3_FPOP_WE', 'PH_PERF_SEL_SC2_PA3_FPOV_WE',
'PH_PERF_SEL_SC2_PA3_NULL_WE',
'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA4_EOPG_WE',
'PH_PERF_SEL_SC2_PA4_EOP_WE', 'PH_PERF_SEL_SC2_PA4_EVENT_WE',
'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA4_FIFO_FULL',
'PH_PERF_SEL_SC2_PA4_FPOP_WE', 'PH_PERF_SEL_SC2_PA4_FPOV_WE',
'PH_PERF_SEL_SC2_PA4_NULL_WE',
'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA5_EOPG_WE',
'PH_PERF_SEL_SC2_PA5_EOP_WE', 'PH_PERF_SEL_SC2_PA5_EVENT_WE',
'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA5_FIFO_FULL',
'PH_PERF_SEL_SC2_PA5_FPOP_WE', 'PH_PERF_SEL_SC2_PA5_FPOV_WE',
'PH_PERF_SEL_SC2_PA5_NULL_WE',
'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA6_EOPG_WE',
'PH_PERF_SEL_SC2_PA6_EOP_WE', 'PH_PERF_SEL_SC2_PA6_EVENT_WE',
'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA6_FIFO_FULL',
'PH_PERF_SEL_SC2_PA6_FPOP_WE', 'PH_PERF_SEL_SC2_PA6_FPOV_WE',
'PH_PERF_SEL_SC2_PA6_NULL_WE',
'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA7_EOPG_WE',
'PH_PERF_SEL_SC2_PA7_EOP_WE', 'PH_PERF_SEL_SC2_PA7_EVENT_WE',
'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA7_FIFO_FULL',
'PH_PERF_SEL_SC2_PA7_FPOP_WE', 'PH_PERF_SEL_SC2_PA7_FPOV_WE',
'PH_PERF_SEL_SC2_PA7_NULL_WE',
'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC2_SEND', 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC3_ARB_BUSY',
'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC3_CREDIT_AT_MAX',
'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA0_EOPG_WE',
'PH_PERF_SEL_SC3_PA0_EOP_WE', 'PH_PERF_SEL_SC3_PA0_EVENT_WE',
'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA0_FIFO_FULL',
'PH_PERF_SEL_SC3_PA0_FPOP_WE', 'PH_PERF_SEL_SC3_PA0_FPOV_WE',
'PH_PERF_SEL_SC3_PA0_NULL_WE',
'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA1_EOPG_WE',
'PH_PERF_SEL_SC3_PA1_EOP_WE', 'PH_PERF_SEL_SC3_PA1_EVENT_WE',
'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA1_FIFO_FULL',
'PH_PERF_SEL_SC3_PA1_FPOP_WE', 'PH_PERF_SEL_SC3_PA1_FPOV_WE',
'PH_PERF_SEL_SC3_PA1_NULL_WE',
'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA2_EOPG_WE',
'PH_PERF_SEL_SC3_PA2_EOP_WE', 'PH_PERF_SEL_SC3_PA2_EVENT_WE',
'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA2_FIFO_FULL',
'PH_PERF_SEL_SC3_PA2_FPOP_WE', 'PH_PERF_SEL_SC3_PA2_FPOV_WE',
'PH_PERF_SEL_SC3_PA2_NULL_WE',
'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA3_EOPG_WE',
'PH_PERF_SEL_SC3_PA3_EOP_WE', 'PH_PERF_SEL_SC3_PA3_EVENT_WE',
'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA3_FIFO_FULL',
'PH_PERF_SEL_SC3_PA3_FPOP_WE', 'PH_PERF_SEL_SC3_PA3_FPOV_WE',
'PH_PERF_SEL_SC3_PA3_NULL_WE',
'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA4_EOPG_WE',
'PH_PERF_SEL_SC3_PA4_EOP_WE', 'PH_PERF_SEL_SC3_PA4_EVENT_WE',
'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA4_FIFO_FULL',
'PH_PERF_SEL_SC3_PA4_FPOP_WE', 'PH_PERF_SEL_SC3_PA4_FPOV_WE',
'PH_PERF_SEL_SC3_PA4_NULL_WE',
'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA5_EOPG_WE',
'PH_PERF_SEL_SC3_PA5_EOP_WE', 'PH_PERF_SEL_SC3_PA5_EVENT_WE',
'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA5_FIFO_FULL',
'PH_PERF_SEL_SC3_PA5_FPOP_WE', 'PH_PERF_SEL_SC3_PA5_FPOV_WE',
'PH_PERF_SEL_SC3_PA5_NULL_WE',
'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA6_EOPG_WE',
'PH_PERF_SEL_SC3_PA6_EOP_WE', 'PH_PERF_SEL_SC3_PA6_EVENT_WE',
'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA6_FIFO_FULL',
'PH_PERF_SEL_SC3_PA6_FPOP_WE', 'PH_PERF_SEL_SC3_PA6_FPOV_WE',
'PH_PERF_SEL_SC3_PA6_NULL_WE',
'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA7_EOPG_WE',
'PH_PERF_SEL_SC3_PA7_EOP_WE', 'PH_PERF_SEL_SC3_PA7_EVENT_WE',
'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA7_FIFO_FULL',
'PH_PERF_SEL_SC3_PA7_FPOP_WE', 'PH_PERF_SEL_SC3_PA7_FPOV_WE',
'PH_PERF_SEL_SC3_PA7_NULL_WE',
'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC3_SEND', 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC4_ARB_BUSY',
'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC4_CREDIT_AT_MAX',
'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA0_EOPG_WE',
'PH_PERF_SEL_SC4_PA0_EOP_WE', 'PH_PERF_SEL_SC4_PA0_EVENT_WE',
'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA0_FIFO_FULL',
'PH_PERF_SEL_SC4_PA0_FPOP_WE', 'PH_PERF_SEL_SC4_PA0_FPOV_WE',
'PH_PERF_SEL_SC4_PA0_NULL_WE',
'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA1_EOPG_WE',
'PH_PERF_SEL_SC4_PA1_EOP_WE', 'PH_PERF_SEL_SC4_PA1_EVENT_WE',
'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA1_FIFO_FULL',
'PH_PERF_SEL_SC4_PA1_FPOP_WE', 'PH_PERF_SEL_SC4_PA1_FPOV_WE',
'PH_PERF_SEL_SC4_PA1_NULL_WE',
'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA2_EOPG_WE',
'PH_PERF_SEL_SC4_PA2_EOP_WE', 'PH_PERF_SEL_SC4_PA2_EVENT_WE',
'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA2_FIFO_FULL',
'PH_PERF_SEL_SC4_PA2_FPOP_WE', 'PH_PERF_SEL_SC4_PA2_FPOV_WE',
'PH_PERF_SEL_SC4_PA2_NULL_WE',
'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA3_EOPG_WE',
'PH_PERF_SEL_SC4_PA3_EOP_WE', 'PH_PERF_SEL_SC4_PA3_EVENT_WE',
'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA3_FIFO_FULL',
'PH_PERF_SEL_SC4_PA3_FPOP_WE', 'PH_PERF_SEL_SC4_PA3_FPOV_WE',
'PH_PERF_SEL_SC4_PA3_NULL_WE',
'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA4_EOPG_WE',
'PH_PERF_SEL_SC4_PA4_EOP_WE', 'PH_PERF_SEL_SC4_PA4_EVENT_WE',
'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA4_FIFO_FULL',
'PH_PERF_SEL_SC4_PA4_FPOP_WE', 'PH_PERF_SEL_SC4_PA4_FPOV_WE',
'PH_PERF_SEL_SC4_PA4_NULL_WE',
'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA5_EOPG_WE',
'PH_PERF_SEL_SC4_PA5_EOP_WE', 'PH_PERF_SEL_SC4_PA5_EVENT_WE',
'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA5_FIFO_FULL',
'PH_PERF_SEL_SC4_PA5_FPOP_WE', 'PH_PERF_SEL_SC4_PA5_FPOV_WE',
'PH_PERF_SEL_SC4_PA5_NULL_WE',
'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA6_EOPG_WE',
'PH_PERF_SEL_SC4_PA6_EOP_WE', 'PH_PERF_SEL_SC4_PA6_EVENT_WE',
'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA6_FIFO_FULL',
'PH_PERF_SEL_SC4_PA6_FPOP_WE', 'PH_PERF_SEL_SC4_PA6_FPOV_WE',
'PH_PERF_SEL_SC4_PA6_NULL_WE',
'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA7_EOPG_WE',
'PH_PERF_SEL_SC4_PA7_EOP_WE', 'PH_PERF_SEL_SC4_PA7_EVENT_WE',
'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA7_FIFO_FULL',
'PH_PERF_SEL_SC4_PA7_FPOP_WE', 'PH_PERF_SEL_SC4_PA7_FPOV_WE',
'PH_PERF_SEL_SC4_PA7_NULL_WE',
'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC4_SEND', 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC5_ARB_BUSY',
'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC5_CREDIT_AT_MAX',
'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA0_EOPG_WE',
'PH_PERF_SEL_SC5_PA0_EOP_WE', 'PH_PERF_SEL_SC5_PA0_EVENT_WE',
'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA0_FIFO_FULL',
'PH_PERF_SEL_SC5_PA0_FPOP_WE', 'PH_PERF_SEL_SC5_PA0_FPOV_WE',
'PH_PERF_SEL_SC5_PA0_NULL_WE',
'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA1_EOPG_WE',
'PH_PERF_SEL_SC5_PA1_EOP_WE', 'PH_PERF_SEL_SC5_PA1_EVENT_WE',
'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA1_FIFO_FULL',
'PH_PERF_SEL_SC5_PA1_FPOP_WE', 'PH_PERF_SEL_SC5_PA1_FPOV_WE',
'PH_PERF_SEL_SC5_PA1_NULL_WE',
'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA2_EOPG_WE',
'PH_PERF_SEL_SC5_PA2_EOP_WE', 'PH_PERF_SEL_SC5_PA2_EVENT_WE',
'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA2_FIFO_FULL',
'PH_PERF_SEL_SC5_PA2_FPOP_WE', 'PH_PERF_SEL_SC5_PA2_FPOV_WE',
'PH_PERF_SEL_SC5_PA2_NULL_WE',
'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA3_EOPG_WE',
'PH_PERF_SEL_SC5_PA3_EOP_WE', 'PH_PERF_SEL_SC5_PA3_EVENT_WE',
'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA3_FIFO_FULL',
'PH_PERF_SEL_SC5_PA3_FPOP_WE', 'PH_PERF_SEL_SC5_PA3_FPOV_WE',
'PH_PERF_SEL_SC5_PA3_NULL_WE',
'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA4_EOPG_WE',
'PH_PERF_SEL_SC5_PA4_EOP_WE', 'PH_PERF_SEL_SC5_PA4_EVENT_WE',
'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA4_FIFO_FULL',
'PH_PERF_SEL_SC5_PA4_FPOP_WE', 'PH_PERF_SEL_SC5_PA4_FPOV_WE',
'PH_PERF_SEL_SC5_PA4_NULL_WE',
'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA5_EOPG_WE',
'PH_PERF_SEL_SC5_PA5_EOP_WE', 'PH_PERF_SEL_SC5_PA5_EVENT_WE',
'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA5_FIFO_FULL',
'PH_PERF_SEL_SC5_PA5_FPOP_WE', 'PH_PERF_SEL_SC5_PA5_FPOV_WE',
'PH_PERF_SEL_SC5_PA5_NULL_WE',
'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA6_EOPG_WE',
'PH_PERF_SEL_SC5_PA6_EOP_WE', 'PH_PERF_SEL_SC5_PA6_EVENT_WE',
'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA6_FIFO_FULL',
'PH_PERF_SEL_SC5_PA6_FPOP_WE', 'PH_PERF_SEL_SC5_PA6_FPOV_WE',
'PH_PERF_SEL_SC5_PA6_NULL_WE',
'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA7_EOPG_WE',
'PH_PERF_SEL_SC5_PA7_EOP_WE', 'PH_PERF_SEL_SC5_PA7_EVENT_WE',
'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA7_FIFO_FULL',
'PH_PERF_SEL_SC5_PA7_FPOP_WE', 'PH_PERF_SEL_SC5_PA7_FPOV_WE',
'PH_PERF_SEL_SC5_PA7_NULL_WE',
'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC5_SEND', 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC6_ARB_BUSY',
'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC6_CREDIT_AT_MAX',
'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA0_EOPG_WE',
'PH_PERF_SEL_SC6_PA0_EOP_WE', 'PH_PERF_SEL_SC6_PA0_EVENT_WE',
'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA0_FIFO_FULL',
'PH_PERF_SEL_SC6_PA0_FPOP_WE', 'PH_PERF_SEL_SC6_PA0_FPOV_WE',
'PH_PERF_SEL_SC6_PA0_NULL_WE',
'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA1_EOPG_WE',
'PH_PERF_SEL_SC6_PA1_EOP_WE', 'PH_PERF_SEL_SC6_PA1_EVENT_WE',
'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA1_FIFO_FULL',
'PH_PERF_SEL_SC6_PA1_FPOP_WE', 'PH_PERF_SEL_SC6_PA1_FPOV_WE',
'PH_PERF_SEL_SC6_PA1_NULL_WE',
'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA2_EOPG_WE',
'PH_PERF_SEL_SC6_PA2_EOP_WE', 'PH_PERF_SEL_SC6_PA2_EVENT_WE',
'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA2_FIFO_FULL',
'PH_PERF_SEL_SC6_PA2_FPOP_WE', 'PH_PERF_SEL_SC6_PA2_FPOV_WE',
'PH_PERF_SEL_SC6_PA2_NULL_WE',
'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA3_EOPG_WE',
'PH_PERF_SEL_SC6_PA3_EOP_WE', 'PH_PERF_SEL_SC6_PA3_EVENT_WE',
'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA3_FIFO_FULL',
'PH_PERF_SEL_SC6_PA3_FPOP_WE', 'PH_PERF_SEL_SC6_PA3_FPOV_WE',
'PH_PERF_SEL_SC6_PA3_NULL_WE',
'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA4_EOPG_WE',
'PH_PERF_SEL_SC6_PA4_EOP_WE', 'PH_PERF_SEL_SC6_PA4_EVENT_WE',
'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA4_FIFO_FULL',
'PH_PERF_SEL_SC6_PA4_FPOP_WE', 'PH_PERF_SEL_SC6_PA4_FPOV_WE',
'PH_PERF_SEL_SC6_PA4_NULL_WE',
'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA5_EOPG_WE',
'PH_PERF_SEL_SC6_PA5_EOP_WE', 'PH_PERF_SEL_SC6_PA5_EVENT_WE',
'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA5_FIFO_FULL',
'PH_PERF_SEL_SC6_PA5_FPOP_WE', 'PH_PERF_SEL_SC6_PA5_FPOV_WE',
'PH_PERF_SEL_SC6_PA5_NULL_WE',
'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA6_EOPG_WE',
'PH_PERF_SEL_SC6_PA6_EOP_WE', 'PH_PERF_SEL_SC6_PA6_EVENT_WE',
'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA6_FIFO_FULL',
'PH_PERF_SEL_SC6_PA6_FPOP_WE', 'PH_PERF_SEL_SC6_PA6_FPOV_WE',
'PH_PERF_SEL_SC6_PA6_NULL_WE',
'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA7_EOPG_WE',
'PH_PERF_SEL_SC6_PA7_EOP_WE', 'PH_PERF_SEL_SC6_PA7_EVENT_WE',
'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA7_FIFO_FULL',
'PH_PERF_SEL_SC6_PA7_FPOP_WE', 'PH_PERF_SEL_SC6_PA7_FPOV_WE',
'PH_PERF_SEL_SC6_PA7_NULL_WE',
'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC6_SEND', 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC7_ARB_BUSY',
'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC7_CREDIT_AT_MAX',
'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA0_EOPG_WE',
'PH_PERF_SEL_SC7_PA0_EOP_WE', 'PH_PERF_SEL_SC7_PA0_EVENT_WE',
'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA0_FIFO_FULL',
'PH_PERF_SEL_SC7_PA0_FPOP_WE', 'PH_PERF_SEL_SC7_PA0_FPOV_WE',
'PH_PERF_SEL_SC7_PA0_NULL_WE',
'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA1_EOPG_WE',
'PH_PERF_SEL_SC7_PA1_EOP_WE', 'PH_PERF_SEL_SC7_PA1_EVENT_WE',
'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA1_FIFO_FULL',
'PH_PERF_SEL_SC7_PA1_FPOP_WE', 'PH_PERF_SEL_SC7_PA1_FPOV_WE',
'PH_PERF_SEL_SC7_PA1_NULL_WE',
'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA2_EOPG_WE',
'PH_PERF_SEL_SC7_PA2_EOP_WE', 'PH_PERF_SEL_SC7_PA2_EVENT_WE',
'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA2_FIFO_FULL',
'PH_PERF_SEL_SC7_PA2_FPOP_WE', 'PH_PERF_SEL_SC7_PA2_FPOV_WE',
'PH_PERF_SEL_SC7_PA2_NULL_WE',
'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA3_EOPG_WE',
'PH_PERF_SEL_SC7_PA3_EOP_WE', 'PH_PERF_SEL_SC7_PA3_EVENT_WE',
'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA3_FIFO_FULL',
'PH_PERF_SEL_SC7_PA3_FPOP_WE', 'PH_PERF_SEL_SC7_PA3_FPOV_WE',
'PH_PERF_SEL_SC7_PA3_NULL_WE',
'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA4_EOPG_WE',
'PH_PERF_SEL_SC7_PA4_EOP_WE', 'PH_PERF_SEL_SC7_PA4_EVENT_WE',
'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA4_FIFO_FULL',
'PH_PERF_SEL_SC7_PA4_FPOP_WE', 'PH_PERF_SEL_SC7_PA4_FPOV_WE',
'PH_PERF_SEL_SC7_PA4_NULL_WE',
'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA5_EOPG_WE',
'PH_PERF_SEL_SC7_PA5_EOP_WE', 'PH_PERF_SEL_SC7_PA5_EVENT_WE',
'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA5_FIFO_FULL',
'PH_PERF_SEL_SC7_PA5_FPOP_WE', 'PH_PERF_SEL_SC7_PA5_FPOV_WE',
'PH_PERF_SEL_SC7_PA5_NULL_WE',
'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA6_EOPG_WE',
'PH_PERF_SEL_SC7_PA6_EOP_WE', 'PH_PERF_SEL_SC7_PA6_EVENT_WE',
'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA6_FIFO_FULL',
'PH_PERF_SEL_SC7_PA6_FPOP_WE', 'PH_PERF_SEL_SC7_PA6_FPOV_WE',
'PH_PERF_SEL_SC7_PA6_NULL_WE',
'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA7_EOPG_WE',
'PH_PERF_SEL_SC7_PA7_EOP_WE', 'PH_PERF_SEL_SC7_PA7_EVENT_WE',
'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA7_FIFO_FULL',
'PH_PERF_SEL_SC7_PA7_FPOP_WE', 'PH_PERF_SEL_SC7_PA7_FPOV_WE',
'PH_PERF_SEL_SC7_PA7_NULL_WE',
'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC7_SEND', 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID',
'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT',
'PH_SPI_MODE_DISABLED', 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT',
'PIPELINESTAT_START', 'PIPELINESTAT_STOP', 'PIPE_ALIGNED',
'PIPE_ALIGNED_SURF', 'PIPE_ID0', 'PIPE_ID1', 'PIPE_ID2',
'PIPE_ID3', 'PIPE_INT_MASK_MODE', 'PIPE_INT_MASK_MODE_DISABLE',
'PIPE_INT_MASK_MODE_ENABLE', 'PIPE_INT_TYPE_MODE',
'PIPE_INT_TYPE_MODE_DISABLE', 'PIPE_INT_TYPE_MODE_ENABLE',
'PIPE_IN_FLUSH_URGENT', 'PIPE_IN_FLUSH_URGENT_DISABLE',
'PIPE_IN_FLUSH_URGENT_ENABLE', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD',
'PIPE_PIXEL_RATE_PLL_SOURCE',
'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL',
'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE',
'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL',
'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIPE_UNALIGNED_SURF',
'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1',
'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE', 'PIXEL_PIPE_OCCLUSION_COUNT_0',
'PIXEL_PIPE_OCCLUSION_COUNT_1', 'PIXEL_PIPE_OCCLUSION_COUNT_2',
'PIXEL_PIPE_OCCLUSION_COUNT_3', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0',
'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1',
'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0',
'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL',
'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET',
'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS',
'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS',
'PIX_DYNAMIC_EXPANSION', 'PIX_EXPAND_MODE', 'PIX_ZERO_EXPANSION',
'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE',
'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM_ASSERT_RESET',
'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', 'POINTLIST',
'POWER_STATE_ENUM', 'POWER_STATE_ENUM_DS', 'POWER_STATE_ENUM_LS',
'POWER_STATE_ENUM_ON', 'POWER_STATE_ENUM_SD', 'PRE_CSC_BYPASS',
'PRE_CSC_MODE_ENUM', 'PRE_CSC_SET_A', 'PRE_CSC_SET_B',
'PRE_DEGAM_BT2020', 'PRE_DEGAM_BT2100HLG', 'PRE_DEGAM_BT2100PQ',
'PRE_DEGAM_BYPASS', 'PRE_DEGAM_ENABLE', 'PRE_DEGAM_GAMMA_22',
'PRE_DEGAM_GAMMA_24', 'PRE_DEGAM_GAMMA_26', 'PRE_DEGAM_MODE',
'PRE_DEGAM_SELECT', 'PRE_DEGAM_SRGB', 'PROG_SEQ', 'PROTVIOL',
'PRQ_MRQ_FLUSH_URGENT', 'PRQ_MRQ_FLUSH_URGENT_DISABLE',
'PRQ_MRQ_FLUSH_URGENT_ENABLE', 'PS', 'PSLC_ASAP', 'PSLC_AUTO',
'PSLC_COUNTDOWN', 'PSLC_ON_HANG_ONLY', 'PS_DONE',
'PS_PARTIAL_FLUSH', 'PTE_BUFFER_MODE', 'PTE_BUFFER_MODE_0',
'PTE_BUFFER_MODE_1', 'PTE_ROW_HEIGHT_LINEAR',
'PTE_ROW_HEIGHT_LINEAR_1024L', 'PTE_ROW_HEIGHT_LINEAR_128L',
'PTE_ROW_HEIGHT_LINEAR_16L', 'PTE_ROW_HEIGHT_LINEAR_256L',
'PTE_ROW_HEIGHT_LINEAR_32L', 'PTE_ROW_HEIGHT_LINEAR_512L',
'PTE_ROW_HEIGHT_LINEAR_64L', 'PTE_ROW_HEIGHT_LINEAR_8L',
'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE',
'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN',
'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT',
'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN',
'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN',
'PWRSEQ_BL_PWM_DISABLE', 'PWRSEQ_BL_PWM_ENABLE',
'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE',
'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE',
'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE',
'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN',
'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE',
'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN',
'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM',
'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM',
'PWRSEQ_BL_PWM_GRP1_REG_LOCK',
'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE',
'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE',
'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START',
'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE',
'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE',
'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE',
'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE',
'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL',
'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM',
'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1',
'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2',
'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3',
'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL',
'PWRSEQ_GPIO_MASK_EN', 'PWRSEQ_GPIO_MASK_EN_HARDWARE',
'PWRSEQ_GPIO_MASK_EN_SOFTWARE', 'PWRSEQ_PANEL_BLON_OFF',
'PWRSEQ_PANEL_BLON_ON', 'PWRSEQ_PANEL_BLON_POL_INVERT',
'PWRSEQ_PANEL_BLON_POL_NON_INVERT', 'PWRSEQ_PANEL_DIGON_OFF',
'PWRSEQ_PANEL_DIGON_ON', 'PWRSEQ_PANEL_DIGON_POL_INVERT',
'PWRSEQ_PANEL_DIGON_POL_NON_INVERT',
'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON',
'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL',
'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON',
'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL',
'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL',
'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE',
'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN',
'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF',
'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON',
'PWRSEQ_PANEL_SYNCEN_POL_INVERT',
'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT',
'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON',
'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', 'PerfCounter_Vals',
'PhSPIstatusMode', 'PixelPipeCounterId', 'PixelPipeStride',
'PkrMap', 'PkrXsel', 'PkrXsel2', 'PkrYsel', 'RAMA', 'RAMA_ACCESS',
'RAMB', 'RAMB_ACCESS', 'RAM_LUT', 'RANGE_00', 'RANGE_FF',
'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1',
'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3',
'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1',
'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3',
'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1',
'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3',
'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1',
'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3',
'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1',
'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3',
'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1',
'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3',
'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1',
'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1',
'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1',
'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3',
'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE',
'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE',
'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE',
'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE',
'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE',
'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE',
'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE',
'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0',
'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2',
'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0',
'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2',
'RASTER_CONFIG_SE_PAIR_MAP_3',
'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE',
'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE',
'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE',
'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE',
'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE',
'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE',
'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE',
'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE',
'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW',
'RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN',
'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON',
'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN',
'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS',
'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON',
'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN',
'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS',
'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS',
'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON',
'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN',
'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS',
'RDPCSTX_CLOCK_CNTL_TX_CLK_EN',
'RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET',
'RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET',
'RDPCSTX_CNTL_RDPCS_TX_FIFO_EN',
'RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN',
'RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET', 'RDPCSTX_FIFO_EMPTY',
'RDPCSTX_FIFO_FULL', 'RDPCSTX_FIFO_IS_EMPTY',
'RDPCSTX_FIFO_IS_FULL', 'RDPCSTX_FIFO_NOT_EMPTY',
'RDPCSTX_FIFO_NOT_FULL',
'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE',
'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK',
'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE',
'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK',
'RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK',
'RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK',
'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL',
'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL',
'RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE',
'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE',
'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE',
'RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV',
'RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV',
'RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV',
'RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL',
'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT',
'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE',
'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH',
'RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE',
'RDPCSTX_PHY_REF_ALT_CLK_EN', 'RDPCSTX_TX_FIFO_DISABLED_MASK',
'RDPCSTX_TX_FIFO_DISABLED_MASK_DISABLE',
'RDPCSTX_TX_FIFO_DISABLED_MASK_ENABLE',
'RDPCS_CBUS_SOFT_RESET_DISABLE', 'RDPCS_CBUS_SOFT_RESET_ENABLE',
'RDPCS_DBG_OCLA_SEL', 'RDPCS_DBG_OCLA_SEL_MON_OUT_15_8',
'RDPCS_DBG_OCLA_SEL_MON_OUT_23_16',
'RDPCS_DBG_OCLA_SEL_MON_OUT_31_24',
'RDPCS_DBG_OCLA_SEL_MON_OUT_39_32',
'RDPCS_DBG_OCLA_SEL_MON_OUT_47_40',
'RDPCS_DBG_OCLA_SEL_MON_OUT_55_48',
'RDPCS_DBG_OCLA_SEL_MON_OUT_63_56',
'RDPCS_DBG_OCLA_SEL_MON_OUT_7_0',
'RDPCS_DPALT_4LANE_TOGGLE_2LANE',
'RDPCS_DPALT_4LANE_TOGGLE_4LANE',
'RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE',
'RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE',
'RDPCS_DPALT_DISABLE_TOGGLE_DISABLE',
'RDPCS_DPALT_DISABLE_TOGGLE_ENABLE',
'RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE',
'RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE',
'RDPCS_EXT_REFCLK_DISABLE', 'RDPCS_EXT_REFCLK_ENABLE',
'RDPCS_EXT_REFCLK_EN_DISABLE', 'RDPCS_EXT_REFCLK_EN_ENABLE',
'RDPCS_LANE_BIT_ORDER_REVERSE_DISABLE',
'RDPCS_LANE_BIT_ORDER_REVERSE_ENABLE',
'RDPCS_LANE_PACK_FROM_MSB_DISABLE',
'RDPCS_LANE_PACK_FROM_MSB_ENABLE', 'RDPCS_MEM_PWR_DEEP_SLEEP',
'RDPCS_MEM_PWR_LIGHT_SLEEP', 'RDPCS_MEM_PWR_NO_FORCE',
'RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP',
'RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP',
'RDPCS_MEM_PWR_PWR_STATE_ON', 'RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN',
'RDPCS_MEM_PWR_SHUT_DOWN', 'RDPCS_OCLACLK_CLOCK_OFF',
'RDPCS_OCLACLK_CLOCK_ON', 'RDPCS_OCLACLK_DISABLE',
'RDPCS_OCLACLK_ENABLE', 'RDPCS_OCLACLK_GATE_DISABLE',
'RDPCS_OCLACLK_GATE_ENABLE', 'RDPCS_PHY_CR_MUX_SEL_FOR_DC',
'RDPCS_PHY_CR_MUX_SEL_FOR_USB', 'RDPCS_PHY_CR_PARA_SEL_CR',
'RDPCS_PHY_CR_PARA_SEL_JTAG', 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6',
'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8',
'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1',
'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16',
'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2',
'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3',
'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8',
'RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT',
'RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT', 'RDPCS_PHY_DP_TX_RATE',
'RDPCS_PHY_DP_TX_RATE_DIV2', 'RDPCS_PHY_DP_TX_RATE_DIV4',
'RDPCS_PHY_DP_TX_TERM_CTRL_40', 'RDPCS_PHY_DP_TX_TERM_CTRL_42',
'RDPCS_PHY_DP_TX_TERM_CTRL_44', 'RDPCS_PHY_DP_TX_TERM_CTRL_46',
'RDPCS_PHY_DP_TX_TERM_CTRL_48', 'RDPCS_PHY_DP_TX_TERM_CTRL_50',
'RDPCS_PHY_DP_TX_TERM_CTRL_52', 'RDPCS_PHY_DP_TX_TERM_CTRL_54',
'RDPCS_PHY_DP_TX_WIDTH_10', 'RDPCS_PHY_DP_TX_WIDTH_16',
'RDPCS_PHY_DP_TX_WIDTH_20', 'RDPCS_PHY_DP_TX_WIDTH_8',
'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0',
'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1',
'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2',
'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3',
'RDPCS_PHY_REF_ALT_CLK_DISABLE', 'RDPCS_PHY_REF_ALT_CLK_ENABLE',
'RDPCS_PHY_REF_RANGE_0', 'RDPCS_PHY_REF_RANGE_1',
'RDPCS_PHY_REF_RANGE_2', 'RDPCS_PHY_REF_RANGE_3',
'RDPCS_PHY_REF_RANGE_4', 'RDPCS_PHY_REF_RANGE_5',
'RDPCS_PHY_REF_RANGE_6', 'RDPCS_PHY_REF_RANGE_7',
'RDPCS_REG_FIFO_ERROR_MASK_DISABLE',
'RDPCS_REG_FIFO_ERROR_MASK_ENABLE', 'RDPCS_SRAMCLK_DISABLE',
'RDPCS_SRAMCLK_ENABLE', 'RDPCS_SRAMCLK_GATE_DISABLE',
'RDPCS_SRAMCLK_GATE_ENABLE', 'RDPCS_SRAMCLK_NOT_PASS',
'RDPCS_SRAMCLK_PASS', 'RDPCS_SRAM_EXT_LD_DONE',
'RDPCS_SRAM_EXT_LD_NOT_DONE', 'RDPCS_SRAM_INIT_DONE',
'RDPCS_SRAM_INIT_NOT_DONE', 'RDPCS_SRAM_SRAM_RESET_DISABLE',
'RDPCS_SRAM_SRAM_RESET_ENABLE', 'RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF',
'RDPCS_SYMCLK_SRAMCLK_CLOCK_ON', 'RDPCS_TEST_CLK_SEL',
'RDPCS_TEST_CLK_SEL_CFGCLK',
'RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK',
'RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK',
'RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK',
'RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK',
'RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK',
'RDPCS_TEST_CLK_SEL_EXT_CR_CLK',
'RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK',
'RDPCS_TEST_CLK_SEL_NONE', 'RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK',
'RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk', 'RDPCS_TEST_CLK_SEL_SRAMCLK',
'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS',
'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4',
'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS',
'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4',
'RDPCS_TEST_CLK_SEL_dtb_out0', 'RDPCS_TEST_CLK_SEL_dtb_out1',
'RDPCS_TX_CLK_CLOCK_OFF', 'RDPCS_TX_CLK_CLOCK_ON',
'RDPCS_TX_CLK_DISABLE', 'RDPCS_TX_CLK_ENABLE',
'RDPCS_TX_CLK_GATE_DISABLE', 'RDPCS_TX_CLK_GATE_ENABLE',
'RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB', 'RDPCS_TX_FIFO_DISABLE',
'RDPCS_TX_FIFO_ENABLE', 'RDPCS_TX_FIFO_ERROR_MASK_DISABLE',
'RDPCS_TX_FIFO_ERROR_MASK_ENABLE', 'RDPCS_TX_FIFO_LANE_DISABLE',
'RDPCS_TX_FIFO_LANE_ENABLE', 'RDPCS_TX_SOFT_RESET_DISABLE',
'RDPCS_TX_SOFT_RESET_ENABLE',
'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE',
'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE',
'READ_COMPRESSION_MODE', 'READ_SEQ', 'RECTLIST', 'RECT_2D',
'RED_LUT', 'REFER_TO_DP_SOF', 'REFER_TO_OTG_SOF',
'REG_SECURE_VIOLATE_READ', 'REG_SECURE_VIOLATE_WRITE',
'REG_UNALLOCATED_ADDR_READ', 'REG_UNALLOCATED_ADDR_WRITE',
'REG_VIRTUAL_READ', 'REG_VIRTUAL_WRITE', 'RESERVED1', 'RESERVED2',
'RESERVED3', 'RESERVED4', 'RESERVED_1', 'RESERVED_10',
'RESERVED_11', 'RESERVED_20', 'RESERVED_21', 'RESERVED_22',
'RESERVED_23', 'RESERVED_3', 'RESERVED_32', 'RESERVED_33',
'RESERVED_34', 'RESERVED_35', 'RESERVED_44', 'RESERVED_45',
'RESERVED_46', 'RESERVED_47', 'RESERVED_56', 'RESERVED_57',
'RESERVED_58', 'RESERVED_59', 'RESERVED_60', 'RESERVED_61',
'RESERVED_62', 'RESERVED_63', 'RESERVED_72', 'RESERVED_73',
'RESERVED_74', 'RESERVED_75', 'RESERVED_8', 'RESERVED_84',
'RESERVED_85', 'RESERVED_86', 'RESERVED_87', 'RESERVED_88',
'RESERVED_89', 'RESERVED_9', 'RESERVED_90', 'RESERVED_91',
'RESERVED_RDPOLICY', 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT',
'RESPONSE_STATUS', 'RE_Z', 'RGB111110_FIX', 'RGB111110_FLOAT',
'RGB565', 'RGBA1010102', 'RGBA16161616_10LSB',
'RGBA16161616_10MSB', 'RGBA16161616_12LSB', 'RGBA16161616_12MSB',
'RGBA16161616_FLOAT', 'RGBA16161616_SNORM', 'RGBA16161616_UNORM',
'RGBA4444', 'RGBA5551', 'RGBA8888', 'RGBE', 'RINGID0', 'RINGID1',
'RINGID2', 'RINGID3', 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL',
'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED',
'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED',
'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL',
'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED',
'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED',
'RLC_DOORBELL_MODE', 'RLC_DOORBELL_MODE_DISABLE',
'RLC_DOORBELL_MODE_ENABLE', 'RLC_DOORBELL_MODE_ENABLE_PF',
'RLC_DOORBELL_MODE_ENABLE_PF_VF', 'RLC_PERFCOUNTER_SEL',
'RLC_PERFMON_STATE', 'RLC_PERFMON_STATE_DISABLE',
'RLC_PERFMON_STATE_ENABLE', 'RLC_PERFMON_STATE_RESERVED_3',
'RLC_PERFMON_STATE_RESERVED_4', 'RLC_PERFMON_STATE_RESERVED_5',
'RLC_PERFMON_STATE_RESERVED_6', 'RLC_PERFMON_STATE_RESET',
'RLC_PERFMON_STATE_ROLLOVER', 'RLC_PERF_SEL_CP_INTERRUPT',
'RLC_PERF_SEL_GRBM_INTERRUPT', 'RLC_PERF_SEL_IH_INTERRUPT',
'RLC_PERF_SEL_POWER_FEATURE_0', 'RLC_PERF_SEL_POWER_FEATURE_1',
'RLC_PERF_SEL_SERDES_COMMAND_WRITE', 'RLC_PERF_SEL_SPM_INTERRUPT',
'RMIPerfSel', 'RMI_PERF_SEL_BUSY',
'RMI_PERF_SEL_CONSUMER_PROBEGEN_CB_RTS_RTR',
'RMI_PERF_SEL_CONSUMER_PROBEGEN_DB_RTS_RTR',
'RMI_PERF_SEL_CONSUMER_PROBEGEN_IN0_RTS_RTR',
'RMI_PERF_SEL_CONSUMER_PROBEGEN_IN1_RTS_RTR',
'RMI_PERF_SEL_CONSUMER_PROBEGEN_READ_RTS_RTR',
'RMI_PERF_SEL_CONSUMER_PROBEGEN_WRITE_RTS_RTR',
'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR',
'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB',
'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR',
'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB',
'RMI_PERF_SEL_DYN_CLK_CMN_VLD', 'RMI_PERF_SEL_DYN_CLK_PERF_VLD',
'RMI_PERF_SEL_DYN_CLK_RB_VLD', 'RMI_PERF_SEL_EVENT_SEND',
'RMI_PERF_SEL_NONE', 'RMI_PERF_SEL_PERF_WINDOW',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7',
'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID',
'RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID',
'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID',
'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID',
'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID0',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID1',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID2',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID3',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID4',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID5',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID6',
'RMI_PERF_SEL_RB_RMI_RDREQ_CID7',
'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY',
'RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY',
'RMI_PERF_SEL_RB_RMI_RD_BUSY',
'RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY',
'RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX', 'RMI_PERF_SEL_RB_RMI_RD_IDLE',
'RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY',
'RMI_PERF_SEL_RB_RMI_RD_STALL', 'RMI_PERF_SEL_RB_RMI_RD_STARVE',
'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID',
'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID',
'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID0',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID1',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID2',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID3',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID4',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID5',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID6',
'RMI_PERF_SEL_RB_RMI_WRREQ_CID7',
'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY',
'RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY',
'RMI_PERF_SEL_RB_RMI_WR_BUSY',
'RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY',
'RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX', 'RMI_PERF_SEL_RB_RMI_WR_IDLE',
'RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY',
'RMI_PERF_SEL_RB_RMI_WR_STALL', 'RMI_PERF_SEL_RB_RMI_WR_STARVE',
'RMI_PERF_SEL_REG_CLK_VLD', 'RMI_PERF_SEL_REORDER_FIFO_BUSY',
'RMI_PERF_SEL_REORDER_FIFO_REQ',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2',
'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6',
'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2',
'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3',
'RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID',
'RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID',
'RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND',
'RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND',
'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID0',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID1',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID2',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID3',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID4',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID5',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID6',
'RMI_PERF_SEL_RMI_TC_RDREQ_CID7',
'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID',
'RMI_PERF_SEL_RMI_TC_REQ_BUSY',
'RMI_PERF_SEL_RMI_TC_STALL_ALLREQ',
'RMI_PERF_SEL_RMI_TC_STALL_RDREQ',
'RMI_PERF_SEL_RMI_TC_STALL_WRREQ',
'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID0',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID1',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID2',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID3',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID4',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID5',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID6',
'RMI_PERF_SEL_RMI_TC_WRREQ_CID7',
'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID',
'RMI_PERF_SEL_TCIW_BUSY', 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT',
'RMI_PERF_SEL_TCIW_REQ',
'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID',
'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', 'ROM_SIGNATURE',
'ROTATE_0_DEGREES', 'ROTATE_180_DEGREES', 'ROTATE_270_DEGREES',
'ROTATE_90_DEGREES', 'ROTATION_ANGLE', 'ROW_TTU_MODE',
'RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK',
'RRDPCS_PHY_DP_TX_PSTATE_HOLD',
'RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF',
'RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN',
'RRDPCS_PHY_DP_TX_PSTATE_POWER_UP', 'RSPM_CMD',
'RSPM_CMD_CALIBRATE', 'RSPM_CMD_FORCE_SAMPLE', 'RSPM_CMD_IDLE',
'RSPM_CMD_INVALID', 'RSPM_CMD_PERF_RESET', 'RSPM_CMD_PERF_SAMPLE',
'RSPM_CMD_PROF_START', 'RSPM_CMD_PROF_STOP', 'RSPM_CMD_SPM_RESET',
'RSPM_CMD_SPM_START', 'RSPM_CMD_SPM_STOP', 'RST_PIX_CNT',
'RSV_TAG_RAM', 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel',
'ReadPolicy', 'Reserved_0x00', 'RingCounterControl',
'SAMPLE_PIPELINESTAT', 'SAMPLE_STREAMOUTSTATS',
'SAMPLE_STREAMOUTSTATS1', 'SAMPLE_STREAMOUTSTATS2',
'SAMPLE_STREAMOUTSTATS3', 'SCL_2TAP_HARDCODE', 'SCL_ALPHA_COEF',
'SCL_ALPHA_COEF_FIRST', 'SCL_ALPHA_COEF_SECOND',
'SCL_AUTOCAL_MODE', 'SCL_BOUNDARY', 'SCL_BOUNDARY_BLACK',
'SCL_BOUNDARY_EDGE', 'SCL_CHROMA_COEF', 'SCL_CHROMA_COEF_FIRST',
'SCL_CHROMA_COEF_SECOND', 'SCL_COEF_2TAP_HARDCODE_OFF',
'SCL_COEF_2TAP_HARDCODE_ON', 'SCL_COEF_CHROMA_HORZ_FILTER',
'SCL_COEF_CHROMA_VERT_FILTER', 'SCL_COEF_FILTER_TYPE_SEL',
'SCL_COEF_LUMA_HORZ_FILTER', 'SCL_COEF_LUMA_VERT_FILTER',
'SCL_COEF_RAM_SEL', 'SCL_COEF_RAM_SEL_0', 'SCL_COEF_RAM_SEL_1',
'SCL_COEF_SC_HORZ_FILTER', 'SCL_COEF_SC_VERT_FILTER',
'SCL_SHARP_DISABLE', 'SCL_SHARP_EN', 'SCL_SHARP_ENABLE', 'SCOPE',
'SCOPE_CU', 'SCOPE_DEV', 'SCOPE_SE', 'SCOPE_SYS',
'SC_BACKEND_BUSY', 'SC_BACKEND_PRIM_FIFO_FULL', 'SC_BB_DISCARD',
'SC_BCI_CREDIT_AT_MAX', 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND',
'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_BCI_SEND',
'SC_BE_VRS_FB_RET', 'SC_BE_VRS_FB_RET_HIT',
'SC_BE_VRS_FB_RET_STALLED', 'SC_BE_VRS_RD_REQ',
'SC_BE_VRS_RD_REQ_HIT', 'SC_BE_VRS_RD_REQ_STALLED',
'SC_BE_VRS_RD_RET', 'SC_BE_VRS_RD_RET_STALLED',
'SC_BM_BE0_STALLED', 'SC_BM_BE1_STALLED', 'SC_BM_BE2_STALLED',
'SC_BM_BE3_STALLED', 'SC_BM_BUSY',
'SC_BM_MULTI_ACCUM_1_BE_STALLED',
'SC_BM_MULTI_ACCUM_2_BE_STALLED',
'SC_BM_MULTI_ACCUM_3_BE_STALLED',
'SC_BM_MULTI_ACCUM_4_BE_STALLED', 'SC_BUSY_CNT_NOT_ZERO',
'SC_DB0_QUAD_INTF_BUSY', 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX',
'SC_DB0_QUAD_INTF_IDLE', 'SC_DB0_QUAD_INTF_SEND',
'SC_DB0_QUAD_INTF_STALLED_BY_DB', 'SC_DB0_TILE_INTERFACE_BUSY',
'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX',
'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND',
'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'SC_DB0_TILE_INTERFACE_SEND', 'SC_DB0_TILE_INTERFACE_SEND_EVENT',
'SC_DB0_TILE_MASK_FIFO_FULL',
'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL',
'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL',
'SC_EARLYZ_QUAD_COUNT', 'SC_EARLYZ_QUAD_WITH_1_PIX',
'SC_EARLYZ_QUAD_WITH_2_PIX', 'SC_EARLYZ_QUAD_WITH_3_PIX',
'SC_EARLYZ_QUAD_WITH_4_PIX', 'SC_GL1X_BUSY',
'SC_GRP0_DYN_SCLK_BUSY', 'SC_GRP1_DYN_SCLK_BUSY',
'SC_GRP2_DYN_SCLK_BUSY', 'SC_GRP3_DYN_SCLK_BUSY',
'SC_GRP4_DYN_SCLK_BUSY', 'SC_GRP5_DYN_SCLK_BUSY',
'SC_GRP6_DYN_SCLK_BUSY', 'SC_GRP7_DYN_SCLK_BUSY',
'SC_GRP8_DYN_SCLK_BUSY', 'SC_GRP9_DYN_SCLK_BUSY', 'SC_HALF_LSB',
'SC_LSB_ONE_SIDED', 'SC_LSB_TWO_SIDED', 'SC_P0_DETAIL_QUAD_COUNT',
'SC_P0_DETAIL_QUAD_WITH_1_PIX', 'SC_P0_DETAIL_QUAD_WITH_2_PIX',
'SC_P0_DETAIL_QUAD_WITH_3_PIX', 'SC_P0_DETAIL_QUAD_WITH_4_PIX',
'SC_P0_HIZ_QUAD_COUNT', 'SC_P0_HIZ_QUAD_PER_TILE_H0',
'SC_P0_HIZ_QUAD_PER_TILE_H1', 'SC_P0_HIZ_QUAD_PER_TILE_H10',
'SC_P0_HIZ_QUAD_PER_TILE_H11', 'SC_P0_HIZ_QUAD_PER_TILE_H12',
'SC_P0_HIZ_QUAD_PER_TILE_H13', 'SC_P0_HIZ_QUAD_PER_TILE_H14',
'SC_P0_HIZ_QUAD_PER_TILE_H15', 'SC_P0_HIZ_QUAD_PER_TILE_H16',
'SC_P0_HIZ_QUAD_PER_TILE_H2', 'SC_P0_HIZ_QUAD_PER_TILE_H3',
'SC_P0_HIZ_QUAD_PER_TILE_H4', 'SC_P0_HIZ_QUAD_PER_TILE_H5',
'SC_P0_HIZ_QUAD_PER_TILE_H6', 'SC_P0_HIZ_QUAD_PER_TILE_H7',
'SC_P0_HIZ_QUAD_PER_TILE_H8', 'SC_P0_HIZ_QUAD_PER_TILE_H9',
'SC_P0_HIZ_TILE_COUNT', 'SC_PA0_SC_DATA_FIFO_EOP_RD',
'SC_PA0_SC_DATA_FIFO_RD', 'SC_PA0_SC_DATA_FIFO_WE',
'SC_PA0_SC_DEALLOC_2_0_RD', 'SC_PA0_SC_EOP_WE',
'SC_PA0_SC_EVENT_WE', 'SC_PA0_SC_NULL_DEALLOC_WE',
'SC_PA0_SC_NULL_WE', 'SC_PA_SC_DEALLOC_2_0_WE',
'SC_PA_SC_FPOV_WE', 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL',
'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE',
'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE',
'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH',
'SC_PBB_BATCH_BREAK_DUE_TO_EVENT',
'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT',
'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE',
'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE',
'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH',
'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT',
'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT',
'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV',
'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT',
'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE',
'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE',
'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT',
'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET',
'SC_PBB_BATCH_BREAK_DUE_TO_PRIM',
'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER',
'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW',
'SC_PBB_BATCH_HIST_NUM_CONTEXTS',
'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES',
'SC_PBB_BATCH_HIST_NUM_PRIMS',
'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS',
'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM',
'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS',
'SC_PBB_BIN_HIST_NUM_CONTEXTS',
'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES',
'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY',
'SC_PBB_BUSY_AND_NO_SENDS',
'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', 'SC_PBB_END_OF_BATCH',
'SC_PBB_END_OF_BIN',
'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN',
'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW',
'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION',
'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS',
'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH',
'SC_PBB_READ_DEALLOC_4_0', 'SC_PBB_READ_DEALLOC_7_5',
'SC_PBB_READ_FPOG_4_0', 'SC_PBB_READ_FPOG_7_5', 'SC_PBB_READ_PH0',
'SC_PBB_RESERVED', 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES',
'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB',
'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL',
'SC_PERF_SEL_RESERVED_108', 'SC_PERF_SEL_RESERVED_109',
'SC_PERF_SEL_RESERVED_110', 'SC_PERF_SEL_RESERVED_111',
'SC_PERF_SEL_RESERVED_112', 'SC_PERF_SEL_RESERVED_113',
'SC_PERF_SEL_RESERVED_114', 'SC_PERF_SEL_RESERVED_115',
'SC_PERF_SEL_RESERVED_116', 'SC_PERF_SEL_RESERVED_117',
'SC_PERF_SEL_RESERVED_118', 'SC_PERF_SEL_RESERVED_119',
'SC_PERF_SEL_RESERVED_120', 'SC_PERF_SEL_RESERVED_121',
'SC_PERF_SEL_RESERVED_122', 'SC_PERF_SEL_RESERVED_123',
'SC_PERF_SEL_RESERVED_124', 'SC_PERF_SEL_RESERVED_125',
'SC_PERF_SEL_RESERVED_126', 'SC_PERF_SEL_RESERVED_127',
'SC_PERF_SEL_RESERVED_128', 'SC_PERF_SEL_RESERVED_129',
'SC_PERF_SEL_RESERVED_130', 'SC_PERF_SEL_RESERVED_131',
'SC_PERF_SEL_RESERVED_132', 'SC_PERF_SEL_RESERVED_133',
'SC_PERF_SEL_RESERVED_134', 'SC_PERF_SEL_RESERVED_135',
'SC_PERF_SEL_RESERVED_136', 'SC_PERF_SEL_RESERVED_137',
'SC_PERF_SEL_RESERVED_138', 'SC_PERF_SEL_RESERVED_139',
'SC_PERF_SEL_RESERVED_140', 'SC_PERF_SEL_RESERVED_141',
'SC_PERF_SEL_RESERVED_142', 'SC_PERF_SEL_RESERVED_143',
'SC_PERF_SEL_RESERVED_144', 'SC_PERF_SEL_RESERVED_145',
'SC_PERF_SEL_RESERVED_146', 'SC_PERF_SEL_RESERVED_147',
'SC_PERF_SEL_RESERVED_148', 'SC_PERF_SEL_RESERVED_149',
'SC_PERF_SEL_RESERVED_150', 'SC_PERF_SEL_RESERVED_151',
'SC_PERF_SEL_RESERVED_152', 'SC_PERF_SEL_RESERVED_153',
'SC_PERF_SEL_RESERVED_154', 'SC_PERF_SEL_RESERVED_155',
'SC_PERF_SEL_RESERVED_156', 'SC_PERF_SEL_RESERVED_157',
'SC_PERF_SEL_RESERVED_158', 'SC_PERF_SEL_RESERVED_160',
'SC_PERF_SEL_RESERVED_161', 'SC_PERF_SEL_RESERVED_162',
'SC_PERF_SEL_RESERVED_164', 'SC_PERF_SEL_RESERVED_165',
'SC_PERF_SEL_RESERVED_166', 'SC_PERF_SEL_RESERVED_184',
'SC_PERF_SEL_RESERVED_185', 'SC_PERF_SEL_RESERVED_186',
'SC_PERF_SEL_RESERVED_187', 'SC_PERF_SEL_RESERVED_188',
'SC_PERF_SEL_RESERVED_189', 'SC_PERF_SEL_RESERVED_190',
'SC_PERF_SEL_RESERVED_191', 'SC_PERF_SEL_RESERVED_192',
'SC_PERF_SEL_RESERVED_193', 'SC_PERF_SEL_RESERVED_194',
'SC_PERF_SEL_RESERVED_195', 'SC_PERF_SEL_RESERVED_196',
'SC_PERF_SEL_RESERVED_197', 'SC_PERF_SEL_RESERVED_198',
'SC_PERF_SEL_RESERVED_199', 'SC_PERF_SEL_RESERVED_200',
'SC_PERF_SEL_RESERVED_201', 'SC_PERF_SEL_RESERVED_202',
'SC_PERF_SEL_RESERVED_203', 'SC_PERF_SEL_RESERVED_204',
'SC_PERF_SEL_RESERVED_205', 'SC_PERF_SEL_RESERVED_206',
'SC_PERF_SEL_RESERVED_207', 'SC_PERF_SEL_RESERVED_208',
'SC_PERF_SEL_RESERVED_209', 'SC_PERF_SEL_RESERVED_210',
'SC_PERF_SEL_RESERVED_211', 'SC_PERF_SEL_RESERVED_212',
'SC_PERF_SEL_RESERVED_213', 'SC_PERF_SEL_RESERVED_214',
'SC_PERF_SEL_RESERVED_215', 'SC_PERF_SEL_RESERVED_216',
'SC_PERF_SEL_RESERVED_217', 'SC_PERF_SEL_RESERVED_218',
'SC_PERF_SEL_RESERVED_219', 'SC_PERF_SEL_RESERVED_220',
'SC_PERF_SEL_RESERVED_221', 'SC_PERF_SEL_RESERVED_222',
'SC_PERF_SEL_RESERVED_223', 'SC_PERF_SEL_RESERVED_224',
'SC_PERF_SEL_RESERVED_225', 'SC_PERF_SEL_RESERVED_226',
'SC_PERF_SEL_RESERVED_227', 'SC_PERF_SEL_RESERVED_228',
'SC_PERF_SEL_RESERVED_229', 'SC_PERF_SEL_RESERVED_230',
'SC_PERF_SEL_RESERVED_231', 'SC_PERF_SEL_RESERVED_232',
'SC_PERF_SEL_RESERVED_233', 'SC_PERF_SEL_RESERVED_234',
'SC_PERF_SEL_RESERVED_236', 'SC_PERF_SEL_RESERVED_237',
'SC_PERF_SEL_RESERVED_238', 'SC_PERF_SEL_RESERVED_240',
'SC_PERF_SEL_RESERVED_241', 'SC_PERF_SEL_RESERVED_242',
'SC_PERF_SEL_RESERVED_247', 'SC_PERF_SEL_RESERVED_248',
'SC_PERF_SEL_RESERVED_249', 'SC_PERF_SEL_RESERVED_250',
'SC_PERF_SEL_RESERVED_251', 'SC_PERF_SEL_RESERVED_252',
'SC_PERF_SEL_RESERVED_253', 'SC_PERF_SEL_RESERVED_254',
'SC_PERF_SEL_RESERVED_255', 'SC_PERF_SEL_RESERVED_256',
'SC_PERF_SEL_RESERVED_257', 'SC_PERF_SEL_RESERVED_258',
'SC_PERF_SEL_RESERVED_279', 'SC_PERF_SEL_RESERVED_280',
'SC_PERF_SEL_RESERVED_288', 'SC_PERF_SEL_RESERVED_289',
'SC_PERF_SEL_RESERVED_290', 'SC_PERF_SEL_RESERVED_291',
'SC_PERF_SEL_RESERVED_293', 'SC_PERF_SEL_RESERVED_294',
'SC_PERF_SEL_RESERVED_295', 'SC_PERF_SEL_RESERVED_296',
'SC_PERF_SEL_RESERVED_297', 'SC_PERF_SEL_RESERVED_298',
'SC_PERF_SEL_RESERVED_299', 'SC_PERF_SEL_RESERVED_301',
'SC_PERF_SEL_RESERVED_303', 'SC_PERF_SEL_RESERVED_304',
'SC_PERF_SEL_RESERVED_305', 'SC_PERF_SEL_RESERVED_306',
'SC_PERF_SEL_RESERVED_307', 'SC_PERF_SEL_RESERVED_308',
'SC_PERF_SEL_RESERVED_309', 'SC_PERF_SEL_RESERVED_310',
'SC_PERF_SEL_RESERVED_311', 'SC_PERF_SEL_RESERVED_312',
'SC_PERF_SEL_RESERVED_313', 'SC_PERF_SEL_RESERVED_314',
'SC_PERF_SEL_RESERVED_315', 'SC_PERF_SEL_RESERVED_316',
'SC_PERF_SEL_RESERVED_317', 'SC_PERF_SEL_RESERVED_319',
'SC_PERF_SEL_RESERVED_320', 'SC_PERF_SEL_RESERVED_321',
'SC_PERF_SEL_RESERVED_322', 'SC_PERF_SEL_RESERVED_323',
'SC_PERF_SEL_RESERVED_324', 'SC_PERF_SEL_RESERVED_325',
'SC_PERF_SEL_RESERVED_328', 'SC_PERF_SEL_RESERVED_329',
'SC_PERF_SEL_RESERVED_330', 'SC_PERF_SEL_RESERVED_331',
'SC_PERF_SEL_RESERVED_332', 'SC_PERF_SEL_RESERVED_333',
'SC_PERF_SEL_RESERVED_334', 'SC_PERF_SEL_RESERVED_335',
'SC_PERF_SEL_RESERVED_336', 'SC_PERF_SEL_RESERVED_337',
'SC_PERF_SEL_RESERVED_340', 'SC_PERF_SEL_RESERVED_341',
'SC_PERF_SEL_RESERVED_347', 'SC_PERF_SEL_RESERVED_348',
'SC_PERF_SEL_RESERVED_351', 'SC_PERF_SEL_RESERVED_354',
'SC_PERF_SEL_RESERVED_355', 'SC_PERF_SEL_RESERVED_356',
'SC_PERF_SEL_RESERVED_357', 'SC_PERF_SEL_RESERVED_358',
'SC_PERF_SEL_RESERVED_359', 'SC_PERF_SEL_RESERVED_360',
'SC_PERF_SEL_RESERVED_361', 'SC_PERF_SEL_RESERVED_362',
'SC_PERF_SEL_RESERVED_363', 'SC_PERF_SEL_RESERVED_364',
'SC_PERF_SEL_RESERVED_365', 'SC_PERF_SEL_RESERVED_366',
'SC_PERF_SEL_RESERVED_367', 'SC_PERF_SEL_RESERVED_368',
'SC_PERF_SEL_RESERVED_369', 'SC_PERF_SEL_RESERVED_370',
'SC_PERF_SEL_RESERVED_371', 'SC_PERF_SEL_RESERVED_372',
'SC_PERF_SEL_RESERVED_375', 'SC_PERF_SEL_RESERVED_376',
'SC_PERF_SEL_RESERVED_377', 'SC_PERF_SEL_RESERVED_378',
'SC_PERF_SEL_RESERVED_379', 'SC_PERF_SEL_RESERVED_380',
'SC_PERF_SEL_RESERVED_381', 'SC_PERF_SEL_RESERVED_382',
'SC_PERF_SEL_RESERVED_383', 'SC_PERF_SEL_RESERVED_384',
'SC_PERF_SEL_RESERVED_385', 'SC_PERF_SEL_RESERVED_423',
'SC_PERF_SEL_RESERVED_424', 'SC_PERF_SEL_RESERVED_425',
'SC_PERF_SEL_RESERVED_426', 'SC_PERF_SEL_RESERVED_427',
'SC_PERF_SEL_RESERVED_428', 'SC_PERF_SEL_RESERVED_429',
'SC_PERF_SEL_RESERVED_430', 'SC_PERF_SEL_RESERVED_431',
'SC_PERF_SEL_RESERVED_432', 'SC_PERF_SEL_RESERVED_433',
'SC_PERF_SEL_RESERVED_434', 'SC_PERF_SEL_RESERVED_435',
'SC_PERF_SEL_RESERVED_436', 'SC_PERF_SEL_RESERVED_478',
'SC_PERF_SEL_RESERVED_479', 'SC_PERF_SEL_RESERVED_483',
'SC_PERF_SEL_RESERVED_484', 'SC_PERF_SEL_RESERVED_485',
'SC_PERF_SEL_RESERVED_486', 'SC_PERF_SEL_RESERVED_487',
'SC_PERF_SEL_RESERVED_488', 'SC_PERF_SEL_RESERVED_489',
'SC_PERF_SEL_RESERVED_490', 'SC_PERF_SEL_RESERVED_509',
'SC_PERF_SEL_RESERVED_510', 'SC_PERF_SEL_RESERVED_511',
'SC_PERF_SEL_RESERVED_512', 'SC_PERF_SEL_RESERVED_513',
'SC_PERF_SEL_RESERVED_514', 'SC_PERF_SEL_RESERVED_523',
'SC_PERF_SEL_RESERVED_524', 'SC_PERF_SEL_RESERVED_525',
'SC_PERF_SEL_RESERVED_532', 'SC_PERF_SEL_RESERVED_533',
'SC_PERF_SEL_RESERVED_534', 'SC_PERF_SEL_RESERVED_539',
'SC_PERF_SEL_RESERVED_568', 'SC_PERF_SEL_RESERVED_76',
'SC_PERF_SEL_RESERVED_77', 'SC_PERF_SEL_RESERVED_78',
'SC_PERF_SEL_RESERVED_80', 'SC_PERF_SEL_RESERVED_81',
'SC_PERF_SEL_RESERVED_82', 'SC_PERF_SEL_RESERVED_84',
'SC_PERF_SEL_RESERVED_85', 'SC_PERF_SEL_RESERVED_86',
'SC_PERF_SEL_RESERVED_88', 'SC_PERF_SEL_RESERVED_89',
'SC_PERF_SEL_RESERVED_90', 'SC_PKR_4X2_FILL_QUAD',
'SC_PKR_4X2_QUAD_SPLIT', 'SC_PKR_BCI_QUAD_NEW_PRIM',
'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV',
'SC_PKR_DB_OREO_WAVE_QUAD_COUNT', 'SC_PKR_DB_WAVE_STALL',
'SC_PKR_END_OF_VECTOR',
'SC_PKR_OREO_STALLED_BY_NO_VALID_WAIVE_ID',
'SC_PKR_PC_NO_CREDITS', 'SC_PKR_PC_SEND', 'SC_PKR_PC_SEND_EOV',
'SC_PKR_PC_SEND_EVENT', 'SC_PKR_PC_SEND_PRIM_VALID_0',
'SC_PKR_PC_SEND_PRIM_VALID_1', 'SC_PKR_PC_SEND_TRUE_PRIM',
'SC_PKR_PC_STALLED', 'SC_PKR_PSINVOC_SEDC_FIFO_FULL',
'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2',
'SC_PKR_SPI_QUAD_COUNT', 'SC_PKR_WAVE_BREAK_FULL_TILE',
'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', 'SC_PK_BUSY',
'SC_PK_DEALLOC_WAVE_BREAK', 'SC_PK_MAX_DEALLOC_FORCE_EOV',
'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H',
'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H',
'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H',
'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H',
'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H',
'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H',
'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H',
'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H',
'SC_PK_PM_FULL_TILE_WAVE_BRK_1H',
'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H',
'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H',
'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H',
'SC_PK_PM_OREO_CONFLICT_QUAD_FORCE_EOV_WAVE_BRK_1H',
'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H',
'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H',
'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD',
'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD',
'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD',
'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD',
'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD',
'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD',
'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD',
'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD',
'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD',
'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD',
'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD',
'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD',
'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD',
'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD',
'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD',
'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD',
'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H',
'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY',
'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY',
'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE',
'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP',
'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_PA0_SC_FIFO_EMPTY',
'SC_PS_PA0_SC_FIFO_FULL', 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL',
'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL',
'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL',
'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL',
'SC_PS_PM_PFF_PW_FULL', 'SC_PS_PM_ZFF_PW_FULL',
'SC_PS_TO_BE_SCLK_GATE_STALL', 'SC_PS_TS_EVENT_FIFO_POP',
'SC_PS_TS_EVENT_FIFO_PUSH', 'SC_PWS_CS_EVENTS_PWS_ENABLE',
'SC_PWS_P0_CS_SYNC_COMPLETE', 'SC_PWS_P0_PS_SYNC_COMPLETE',
'SC_PWS_P0_TS_SYNC_COMPLETE', 'SC_PWS_P1_CS_SYNC_COMPLETE',
'SC_PWS_P1_PS_SYNC_COMPLETE', 'SC_PWS_P1_TS_SYNC_COMPLETE',
'SC_PWS_PS_EVENTS_PWS_ENABLE', 'SC_PWS_STALLED',
'SC_PWS_TS_EVENTS_PWS_ENABLE', 'SC_PW_BM_PASS_EMPTY_PRIM',
'SC_QZ0_QUAD_COUNT', 'SC_QZ0_QUAD_PER_TILE_H0',
'SC_QZ0_QUAD_PER_TILE_H1', 'SC_QZ0_QUAD_PER_TILE_H10',
'SC_QZ0_QUAD_PER_TILE_H11', 'SC_QZ0_QUAD_PER_TILE_H12',
'SC_QZ0_QUAD_PER_TILE_H13', 'SC_QZ0_QUAD_PER_TILE_H14',
'SC_QZ0_QUAD_PER_TILE_H15', 'SC_QZ0_QUAD_PER_TILE_H16',
'SC_QZ0_QUAD_PER_TILE_H2', 'SC_QZ0_QUAD_PER_TILE_H3',
'SC_QZ0_QUAD_PER_TILE_H4', 'SC_QZ0_QUAD_PER_TILE_H5',
'SC_QZ0_QUAD_PER_TILE_H6', 'SC_QZ0_QUAD_PER_TILE_H7',
'SC_QZ0_QUAD_PER_TILE_H8', 'SC_QZ0_QUAD_PER_TILE_H9',
'SC_QZ0_TILE_COUNT', 'SC_QZ0_TILE_COVERED_COUNT',
'SC_QZ0_TILE_NOT_COVERED_COUNT', 'SC_QZQP_WINDOW_VALID',
'SC_QZQP_WINDOW_VALID_BUSY', 'SC_REG_SCLK_BUSY', 'SC_RESERVED_60',
'SC_SCB_BUSY', 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD',
'SC_SEND_DB_VPZ', 'SC_SPIBC_FULL_FREEZE', 'SC_SPI_CREDIT_AT_MAX',
'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND',
'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_SPI_DEALLOC_4_0',
'SC_SPI_DEALLOC_7_5', 'SC_SPI_EVENT', 'SC_SPI_FPOV_4_0',
'SC_SPI_FPOV_7_5', 'SC_SPI_SEND', 'SC_SPI_WAVE_STALLED_BY_SPI',
'SC_SRPS_WINDOW_VALID', 'SC_SRPS_WINDOW_VALID_BUSY',
'SC_STALLED_BY_BCI', 'SC_STALLED_BY_DB0_TILEFIFO',
'SC_STALLED_BY_DB_QUAD', 'SC_STALLED_BY_DB_TILE',
'SC_STALLED_BY_PRIMFIFO', 'SC_STALLED_BY_QUADFIFO',
'SC_STALLED_BY_SPI', 'SC_STALLED_BY_TILEFIFO',
'SC_STALLED_BY_TILEORDERFIFO', 'SC_STARVED_BY_DB_QUAD',
'SC_STARVED_BY_DB_TILE', 'SC_STARVED_BY_PA',
'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL',
'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY',
'SC_SUPERTILE_COUNT',
'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9',
'SC_SUPERTILE_PER_PRIM_H0', 'SC_SUPERTILE_PER_PRIM_H1',
'SC_SUPERTILE_PER_PRIM_H10', 'SC_SUPERTILE_PER_PRIM_H11',
'SC_SUPERTILE_PER_PRIM_H12', 'SC_SUPERTILE_PER_PRIM_H13',
'SC_SUPERTILE_PER_PRIM_H14', 'SC_SUPERTILE_PER_PRIM_H15',
'SC_SUPERTILE_PER_PRIM_H16', 'SC_SUPERTILE_PER_PRIM_H2',
'SC_SUPERTILE_PER_PRIM_H3', 'SC_SUPERTILE_PER_PRIM_H4',
'SC_SUPERTILE_PER_PRIM_H5', 'SC_SUPERTILE_PER_PRIM_H6',
'SC_SUPERTILE_PER_PRIM_H7', 'SC_SUPERTILE_PER_PRIM_H8',
'SC_SUPERTILE_PER_PRIM_H9', 'SC_TILE_PER_PRIM_H0',
'SC_TILE_PER_PRIM_H1', 'SC_TILE_PER_PRIM_H10',
'SC_TILE_PER_PRIM_H11', 'SC_TILE_PER_PRIM_H12',
'SC_TILE_PER_PRIM_H13', 'SC_TILE_PER_PRIM_H14',
'SC_TILE_PER_PRIM_H15', 'SC_TILE_PER_PRIM_H16',
'SC_TILE_PER_PRIM_H2', 'SC_TILE_PER_PRIM_H3',
'SC_TILE_PER_PRIM_H4', 'SC_TILE_PER_PRIM_H5',
'SC_TILE_PER_PRIM_H6', 'SC_TILE_PER_PRIM_H7',
'SC_TILE_PER_PRIM_H8', 'SC_TILE_PER_PRIM_H9',
'SC_TILE_PER_SUPERTILE_H0', 'SC_TILE_PER_SUPERTILE_H1',
'SC_TILE_PER_SUPERTILE_H10', 'SC_TILE_PER_SUPERTILE_H11',
'SC_TILE_PER_SUPERTILE_H12', 'SC_TILE_PER_SUPERTILE_H13',
'SC_TILE_PER_SUPERTILE_H14', 'SC_TILE_PER_SUPERTILE_H15',
'SC_TILE_PER_SUPERTILE_H16', 'SC_TILE_PER_SUPERTILE_H2',
'SC_TILE_PER_SUPERTILE_H3', 'SC_TILE_PER_SUPERTILE_H4',
'SC_TILE_PER_SUPERTILE_H5', 'SC_TILE_PER_SUPERTILE_H6',
'SC_TILE_PER_SUPERTILE_H7', 'SC_TILE_PER_SUPERTILE_H8',
'SC_TILE_PER_SUPERTILE_H9', 'SC_TILE_PICKED_H1',
'SC_TPQZ_WINDOW_VALID', 'SC_TPQZ_WINDOW_VALID_BUSY',
'SC_TRPK_WINDOW_VALID', 'SC_TRPK_WINDOW_VALID_BUSY', 'SC_UR_1X',
'SC_UR_2X', 'SC_UR_4X', 'SC_UR_8X', 'SC_VRC_ACK_OUTPUT_STALL',
'SC_VRC_BUSY', 'SC_VRC_DIRTY_SECTORS_FLUSHED',
'SC_VRC_EVICT_NONZERO_INFLIGHT_STALL', 'SC_VRC_FLUSH',
'SC_VRC_FLUSH_DONE_STALL', 'SC_VRC_FLUSH_EVICT_STALL',
'SC_VRC_FLUSH_FIP_HIT_STALL', 'SC_VRC_FLUSH_REFLUSH_STALL',
'SC_VRC_FLUSH_STALL', 'SC_VRC_FLUSH_WRREQ_DRAIN_STALL',
'SC_VRC_GL1X_RD_REQ', 'SC_VRC_GL1X_RD_RET',
'SC_VRC_GL1X_RD_XNACK', 'SC_VRC_GL1X_REQ_STALLED',
'SC_VRC_GL1X_SRC_STALLED', 'SC_VRC_GL1X_SRC_XFR',
'SC_VRC_GL1X_WR_ACK', 'SC_VRC_GL1X_WR_REQ',
'SC_VRC_GL1X_WR_XNACK', 'SC_VRC_HINTMEM_RE_CNT',
'SC_VRC_HINTMEM_WE_CNT', 'SC_VRC_HPF_EVENT', 'SC_VRC_HPF_REQ',
'SC_VRC_HPF_STALLED', 'SC_VRC_INFLIGHT_COUNTER_MAXIMUM_STALL',
'SC_VRC_LRU_EVICT_PENDING_EVICT_STALL',
'SC_VRC_LRU_EVICT_SCHEDULED_EVICT_STALL',
'SC_VRC_LRU_EVICT_STALL', 'SC_VRC_PROBE_ACK_TILES',
'SC_VRC_RATEMEM_RE_CNT', 'SC_VRC_RATEMEM_WE_CNT',
'SC_VRC_READ_OUTPUT_STALL', 'SC_VRC_REEVICTION_STALL',
'SC_VRC_REPLACE_FLUSH_IN_PROGRESS_STALL',
'SC_VRC_REPLACE_PENDING_EVICT_STALL',
'SC_VRC_REPLACE_SCHEDULED_EVICT_STALL', 'SC_VRC_SECTORS_FLUSHED',
'SC_VRC_SECTOR_HIT', 'SC_VRC_SECTOR_MISS', 'SC_VRC_STALL',
'SC_VRC_TAGS_FLUSHED', 'SC_VRC_TAG_MISS',
'SC_VRC_WRITE_OUTPUT_STALL', 'SC_VRS_BE_BUSY',
'SC_VRS_COMB_MODE_MAX', 'SC_VRS_COMB_MODE_MIN',
'SC_VRS_COMB_MODE_OVERRIDE', 'SC_VRS_COMB_MODE_PASSTHRU',
'SC_VRS_COMB_MODE_SATURATE', 'SDMA_PERFMON_SEL',
'SDMA_PERFMON_SEL_CE_AFIFO_FULL', 'SDMA_PERFMON_SEL_CE_DST_IDLE',
'SDMA_PERFMON_SEL_CE_INFO1_FULL', 'SDMA_PERFMON_SEL_CE_INFO_FULL',
'SDMA_PERFMON_SEL_CE_IN_IDLE', 'SDMA_PERFMON_SEL_CE_L1_WR_VLD',
'SDMA_PERFMON_SEL_CE_OUT_IDLE', 'SDMA_PERFMON_SEL_CE_RD_STALL',
'SDMA_PERFMON_SEL_CE_RREQ_IDLE', 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE',
'SDMA_PERFMON_SEL_CE_WREQ_IDLE', 'SDMA_PERFMON_SEL_CE_WR_IDLE',
'SDMA_PERFMON_SEL_CE_WR_STALL',
'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', 'SDMA_PERFMON_SEL_CTX_CHANGE',
'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION',
'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERFMON_SEL_CYCLE',
'SDMA_PERFMON_SEL_DMA_L1_RD_SEND',
'SDMA_PERFMON_SEL_DMA_L1_WR_SEND',
'SDMA_PERFMON_SEL_DMA_MC_RD_SEND',
'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', 'SDMA_PERFMON_SEL_DOORBELL',
'SDMA_PERFMON_SEL_DUMMY_0', 'SDMA_PERFMON_SEL_DUMMY_1',
'SDMA_PERFMON_SEL_EX_IDLE',
'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
'SDMA_PERFMON_SEL_GCR_RTN', 'SDMA_PERFMON_SEL_GCR_SEND',
'SDMA_PERFMON_SEL_GPUVM_INV_HIGH',
'SDMA_PERFMON_SEL_GPUVM_INV_LOW', 'SDMA_PERFMON_SEL_IB_CMD_FULL',
'SDMA_PERFMON_SEL_IB_CMD_IDLE', 'SDMA_PERFMON_SEL_IDLE',
'SDMA_PERFMON_SEL_INT_IDLE', 'SDMA_PERFMON_SEL_INT_REQ_COUNT',
'SDMA_PERFMON_SEL_INT_REQ_STALL',
'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED',
'SDMA_PERFMON_SEL_INT_RESP_RETRY',
'SDMA_PERFMON_SEL_L1_RDL2_IDLE', 'SDMA_PERFMON_SEL_L1_RDMC_IDLE',
'SDMA_PERFMON_SEL_L1_RD_INV_IDLE',
'SDMA_PERFMON_SEL_L1_WRL2_IDLE', 'SDMA_PERFMON_SEL_L1_WRMC_IDLE',
'SDMA_PERFMON_SEL_L1_WR_INV_IDLE',
'SDMA_PERFMON_SEL_L2_META_RET_VLD',
'SDMA_PERFMON_SEL_MCU_L1_WR_VLD', 'SDMA_PERFMON_SEL_MC_RD_COUNT',
'SDMA_PERFMON_SEL_MC_RD_IDLE',
'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE',
'SDMA_PERFMON_SEL_MC_RD_RET_STALL',
'SDMA_PERFMON_SEL_MC_WR_COUNT', 'SDMA_PERFMON_SEL_MC_WR_IDLE',
'SDMA_PERFMON_SEL_META_L2_REQ_SEND',
'SDMA_PERFMON_SEL_META_REQ_SEND', 'SDMA_PERFMON_SEL_META_RTN_VLD',
'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER',
'SDMA_PERFMON_SEL_NUM_PACKET', 'SDMA_PERFMON_SEL_QUEUE0_SELECT',
'SDMA_PERFMON_SEL_QUEUE1_SELECT',
'SDMA_PERFMON_SEL_QUEUE2_SELECT',
'SDMA_PERFMON_SEL_QUEUE3_SELECT', 'SDMA_PERFMON_SEL_RB_CMD_FULL',
'SDMA_PERFMON_SEL_RB_CMD_IDLE', 'SDMA_PERFMON_SEL_RB_EMPTY',
'SDMA_PERFMON_SEL_RB_FULL', 'SDMA_PERFMON_SEL_RB_RPTR_WB',
'SDMA_PERFMON_SEL_RB_RPTR_WRAP',
'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ',
'SDMA_PERFMON_SEL_RB_WPTR_WRAP', 'SDMA_PERFMON_SEL_RD_BA_RTR',
'SDMA_PERFMON_SEL_REG_IDLE', 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK',
'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK',
'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL',
'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND',
'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND',
'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND',
'SDMA_PERFMON_SEL_SEM_IDLE', 'SDMA_PERFMON_SEL_SEM_REQ_COUNT',
'SDMA_PERFMON_SEL_SEM_REQ_STALL',
'SDMA_PERFMON_SEL_SEM_RESP_FAIL',
'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE',
'SDMA_PERFMON_SEL_SEM_RESP_PASS',
'SDMA_PERFMON_SEL_SRBM_REG_SEND', 'SDMA_PERFMON_SEL_TLBI_RTN',
'SDMA_PERFMON_SEL_TLBI_SEND',
'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER',
'SDMA_PERFMON_SEL_UTCL2_FREE', 'SDMA_PERFMON_SEL_UTCL2_RET_ACK',
'SDMA_PERFMON_SEL_UTCL2_RET_XNACK',
'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ',
'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL',
'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN',
'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN',
'SDMA_PERFMON_SEL_WR_BA_RTR', 'SDMA_PERF_SEL',
'SDMA_PERF_SEL_CE_AFIFO_FULL', 'SDMA_PERF_SEL_CE_BUSY',
'SDMA_PERF_SEL_CE_BUSY_END', 'SDMA_PERF_SEL_CE_BUSY_START',
'SDMA_PERF_SEL_CE_CH_RDREQ_SEND',
'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', 'SDMA_PERF_SEL_CE_CH_WR_REQ',
'SDMA_PERF_SEL_CE_CH_WR_RET', 'SDMA_PERF_SEL_CE_DST_IDLE',
'SDMA_PERF_SEL_CE_INFO1_FULL', 'SDMA_PERF_SEL_CE_INFO_FULL',
'SDMA_PERF_SEL_CE_IN_IDLE', 'SDMA_PERF_SEL_CE_L1_WR_VLD',
'SDMA_PERF_SEL_CE_OR_MCU_CH_RD_REQ',
'SDMA_PERF_SEL_CE_OR_MCU_CH_RD_RET', 'SDMA_PERF_SEL_CE_OUT_IDLE',
'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE',
'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE',
'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL',
'SDMA_PERF_SEL_CGCG_FENCE', 'SDMA_PERF_SEL_CH_CE_RDRET_VALID',
'SDMA_PERF_SEL_CH_CE_WRRET_VALID', 'SDMA_PERF_SEL_CMD_OP_END',
'SDMA_PERF_SEL_CMD_OP_MATCH', 'SDMA_PERF_SEL_CMD_OP_START',
'SDMA_PERF_SEL_CPF_SDMA_INVREQ', 'SDMA_PERF_SEL_CTX_CHANGE',
'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION',
'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE',
'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND',
'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND',
'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_DUMMY_0',
'SDMA_PERF_SEL_DUMMY_1', 'SDMA_PERF_SEL_EX_IDLE',
'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
'SDMA_PERF_SEL_GCR_RTN', 'SDMA_PERF_SEL_GCR_SEND',
'SDMA_PERF_SEL_GPUVM_INV_HIGH', 'SDMA_PERF_SEL_GPUVM_INV_LOW',
'SDMA_PERF_SEL_IB_CH_RD_REQ', 'SDMA_PERF_SEL_IB_CH_RD_RET',
'SDMA_PERF_SEL_IB_CMD_FULL', 'SDMA_PERF_SEL_IB_CMD_IDLE',
'SDMA_PERF_SEL_IDLE', 'SDMA_PERF_SEL_INT_IDLE',
'SDMA_PERF_SEL_INT_REQ_COUNT', 'SDMA_PERF_SEL_INT_REQ_STALL',
'SDMA_PERF_SEL_INT_RESP_ACCEPTED', 'SDMA_PERF_SEL_INT_RESP_RETRY',
'SDMA_PERF_SEL_L1_RDL2_IDLE', 'SDMA_PERF_SEL_L1_RDMC_IDLE',
'SDMA_PERF_SEL_L1_RD_INV_IDLE', 'SDMA_PERF_SEL_L1_WRL2_IDLE',
'SDMA_PERF_SEL_L1_WRMC_IDLE', 'SDMA_PERF_SEL_L1_WR_INV_IDLE',
'SDMA_PERF_SEL_L2_META_RET_VLD', 'SDMA_PERF_SEL_MCU_CH_WR_REQ',
'SDMA_PERF_SEL_MCU_CH_WR_RET', 'SDMA_PERF_SEL_MCU_L1_WR_VLD',
'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER',
'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_END',
'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_START',
'SDMA_PERF_SEL_MC_RD_COUNT', 'SDMA_PERF_SEL_MC_RD_IDLE',
'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE',
'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT',
'SDMA_PERF_SEL_MC_WR_IDLE', 'SDMA_PERF_SEL_META_L2_REQ_SEND',
'SDMA_PERF_SEL_META_REQ_SEND', 'SDMA_PERF_SEL_META_RTN_VLD',
'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_QUEUE0_SELECT',
'SDMA_PERF_SEL_QUEUE1_SELECT', 'SDMA_PERF_SEL_QUEUE2_SELECT',
'SDMA_PERF_SEL_QUEUE3_SELECT', 'SDMA_PERF_SEL_QUEUE4_SELECT',
'SDMA_PERF_SEL_QUEUE5_SELECT', 'SDMA_PERF_SEL_QUEUE6_SELECT',
'SDMA_PERF_SEL_QUEUE7_SELECT', 'SDMA_PERF_SEL_RB_CH_RD_REQ',
'SDMA_PERF_SEL_RB_CH_RD_RET', 'SDMA_PERF_SEL_RB_CMD_FULL',
'SDMA_PERF_SEL_RB_CMD_IDLE', 'SDMA_PERF_SEL_RB_EMPTY',
'SDMA_PERF_SEL_RB_FULL', 'SDMA_PERF_SEL_RB_RPTR_WB',
'SDMA_PERF_SEL_RB_RPTR_WRAP', 'SDMA_PERF_SEL_RB_WPTR_POLL_READ',
'SDMA_PERF_SEL_RB_WPTR_WRAP', 'SDMA_PERF_SEL_RD_BA_RTR',
'SDMA_PERF_SEL_REG_IDLE', 'SDMA_PERF_SEL_SDMA_CPF_INVACK',
'SDMA_PERF_SEL_SDMA_UTCL2_INVACK',
'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL',
'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND',
'SDMA_PERF_SEL_SDMA_UTCL2_SEND',
'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', 'SDMA_PERF_SEL_SEM_IDLE',
'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL',
'SDMA_PERF_SEL_SEM_RESP_FAIL',
'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE',
'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND',
'SDMA_PERF_SEL_TLBI_RTN', 'SDMA_PERF_SEL_TLBI_SEND',
'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', 'SDMA_PERF_SEL_UTCL1_UTCL2_RET',
'SDMA_PERF_SEL_UTCL2_FREE', 'SDMA_PERF_SEL_UTCL2_RET_ACK',
'SDMA_PERF_SEL_UTCL2_RET_XNACK',
'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ',
'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL',
'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN',
'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', 'SDMA_PERF_SEL_WPTR_CH_RD_REQ',
'SDMA_PERF_SEL_WPTR_CH_RD_RET', 'SDMA_PERF_SEL_WR_BA_RTR',
'SEC_GSP0_PRIORITY_HIGH', 'SEC_GSP0_PRIORITY_LOW', 'SEGMENTS_1',
'SEGMENTS_128', 'SEGMENTS_16', 'SEGMENTS_2', 'SEGMENTS_32',
'SEGMENTS_4', 'SEGMENTS_64', 'SEGMENTS_8', 'SEL_DTBCLK_P0',
'SEL_DTBCLK_P1', 'SEL_DTBCLK_P2', 'SEL_DTBCLK_P3',
'SEND_AT_EARLIEST_TIME', 'SEND_AT_LINK_NUMBER',
'SEND_NORMAL_PACKET', 'SEND_PPS_PACKET', 'SET_SMU_MSG_INTR',
'SH_MEM_ADDRESS_MODE', 'SH_MEM_ADDRESS_MODE_32',
'SH_MEM_ADDRESS_MODE_64', 'SH_MEM_ALIGNMENT_MODE',
'SH_MEM_ALIGNMENT_MODE_DWORD',
'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT',
'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED',
'SIGNED', 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE',
'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START',
'SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE',
'SIMM16_WAITCNT_DEPCTR_SA_SDST_START',
'SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE',
'SIMM16_WAITCNT_DEPCTR_VA_SDST_START',
'SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE',
'SIMM16_WAITCNT_DEPCTR_VA_SSRC_START',
'SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE',
'SIMM16_WAITCNT_DEPCTR_VA_VCC_START',
'SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE',
'SIMM16_WAITCNT_DEPCTR_VA_VDST_START',
'SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE',
'SIMM16_WAITCNT_DEPCTR_VM_VSRC_START',
'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START',
'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START',
'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START',
'SIMM16_WAIT_EVENT_EXP_RDY_SIZE',
'SIMM16_WAIT_EVENT_EXP_RDY_START', 'SIZE_16K', 'SIZE_8K',
'SLVERR', 'SMU_INTR', 'SMU_INTR_STATUS_CLEAR',
'SMU_INTR_STATUS_NOOP', 'SMU_MSG_INTR_NOOP', 'SM_MODE_RESERVED',
'SOFT_RESET', 'SOFT_RESET_0', 'SOFT_RESET_1',
'SO_VGTSTREAMOUT_FLUSH', 'SPI_FOG_EXP', 'SPI_FOG_EXP2',
'SPI_FOG_LINEAR', 'SPI_FOG_MODE', 'SPI_FOG_NONE',
'SPI_LB_WAVES_RSVD', 'SPI_LB_WAVES_SELECT', 'SPI_PERFCNT_SEL',
'SPI_PERF_ALL_PS_WAVE', 'SPI_PERF_ALL_PS_WAVE_IN_FLIGHT',
'SPI_PERF_ALL_WAVE', 'SPI_PERF_ALL_WAVE_IN_FLIGHT',
'SPI_PERF_ALL_WAVE_ITEMS', 'SPI_PERF_ALL_WAVE_ITEMS_W32',
'SPI_PERF_ALL_WAVE_ITEMS_W64', 'SPI_PERF_ALL_WAVE_RESTORED',
'SPI_PERF_ALL_WAVE_SAVED', 'SPI_PERF_ALL_WAVE_W32',
'SPI_PERF_ALL_WAVE_W64', 'SPI_PERF_BUSY', 'SPI_PERF_CSGN_BUSY',
'SPI_PERF_CSGN_CRAWLER_STALL', 'SPI_PERF_CSGN_EVENT_WAVE',
'SPI_PERF_CSGN_NUM_THREADGROUPS', 'SPI_PERF_CSGN_PWS_STALL',
'SPI_PERF_CSGN_WAVE', 'SPI_PERF_CSGN_WAVE_IN_FLIGHT',
'SPI_PERF_CSGN_WINDOW_VALID', 'SPI_PERF_CSG_TEMP_ALLOC_LEVEL',
'SPI_PERF_CSN_BUSY', 'SPI_PERF_CSN_CRAWLER_STALL',
'SPI_PERF_CSN_EVENT_WAVE', 'SPI_PERF_CSN_NUM_THREADGROUPS',
'SPI_PERF_CSN_TEMP_ALLOC_LEVEL', 'SPI_PERF_CSN_WAVE',
'SPI_PERF_CSN_WAVE_IN_FLIGHT', 'SPI_PERF_CSN_WINDOW_VALID',
'SPI_PERF_EXPORT_DB0_STALL', 'SPI_PERF_EXPORT_DB1_STALL',
'SPI_PERF_EXPORT_DB2_STALL', 'SPI_PERF_EXPORT_DB3_STALL',
'SPI_PERF_EXPORT_DB4_STALL', 'SPI_PERF_EXPORT_DB5_STALL',
'SPI_PERF_EXPORT_DB6_STALL', 'SPI_PERF_EXPORT_DB7_STALL',
'SPI_PERF_EXPORT_SCB0_STALL', 'SPI_PERF_EXPORT_SCB1_STALL',
'SPI_PERF_EXPORT_SCB2_STALL', 'SPI_PERF_EXPORT_SCB3_STALL',
'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT',
'SPI_PERF_EXP_ARB_IDX_CNT', 'SPI_PERF_EXP_ARB_POS_CNT',
'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED',
'SPI_PERF_EXP_THROT_DOWNSTEP', 'SPI_PERF_EXP_THROT_UPSTEP',
'SPI_PERF_EXP_WITH_CONFLICT', 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR',
'SPI_PERF_GFX_TEMP_ALLOC_LEVEL', 'SPI_PERF_GS_ALLOC_IDX',
'SPI_PERF_GS_ALLOC_POS', 'SPI_PERF_GS_BUSY',
'SPI_PERF_GS_CRAWLER_STALL', 'SPI_PERF_GS_EVENT_WAVE',
'SPI_PERF_GS_EXP_DONE', 'SPI_PERF_GS_FIRST_SUBGRP',
'SPI_PERF_GS_GRP_LIFETIME', 'SPI_PERF_GS_GRP_LIFETIME_SAMPLE',
'SPI_PERF_GS_HS_DEALLOC', 'SPI_PERF_GS_INDX0_STALL',
'SPI_PERF_GS_INDX1_STALL', 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT',
'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC',
'SPI_PERF_GS_NGG_STALL_MSG_VAL', 'SPI_PERF_GS_PERS_UPD_FULL0',
'SPI_PERF_GS_PERS_UPD_FULL1', 'SPI_PERF_GS_POS0_STALL',
'SPI_PERF_GS_POS1_STALL', 'SPI_PERF_GS_PWS_STALL',
'SPI_PERF_GS_SCBD_IDX_CLEANUP', 'SPI_PERF_GS_SCBD_POS_CLEANUP',
'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WAVE_IN_FLIGHT',
'SPI_PERF_GS_WINDOW_VALID', 'SPI_PERF_HS_BUSY',
'SPI_PERF_HS_CRAWLER_STALL', 'SPI_PERF_HS_EVENT_WAVE',
'SPI_PERF_HS_FIRST_WAVE', 'SPI_PERF_HS_PERS_UPD_FULL0',
'SPI_PERF_HS_PERS_UPD_FULL1', 'SPI_PERF_HS_PWS_STALL',
'SPI_PERF_HS_WAVE', 'SPI_PERF_HS_WAVE_IN_FLIGHT',
'SPI_PERF_HS_WINDOW_VALID', 'SPI_PERF_LDS_ALLOC_LEVEL',
'SPI_PERF_NUM_EXPGRANT_EXPORTS',
'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS',
'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS',
'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS',
'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS',
'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS',
'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS',
'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS',
'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS',
'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS',
'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS',
'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS',
'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS',
'SPI_PERF_PIX_ALLOC_PEND_CNT', 'SPI_PERF_PS0_2_WAVE_GROUPS',
'SPI_PERF_PS0_ACTIVE', 'SPI_PERF_PS0_BUSY',
'SPI_PERF_PS0_CRAWLER_STALL', 'SPI_PERF_PS0_DEALLOC',
'SPI_PERF_PS0_DEALLOC_FULL', 'SPI_PERF_PS0_EVENT_WAVE',
'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT',
'SPI_PERF_PS0_LDS_DONE_FULL', 'SPI_PERF_PS0_OPT_WAVE',
'SPI_PERF_PS0_PRIM_BIN0', 'SPI_PERF_PS0_PRIM_BIN1',
'SPI_PERF_PS0_WAVE', 'SPI_PERF_PS0_WAVEID_STARVED',
'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY',
'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS0_WAVE_IN_FLIGHT',
'SPI_PERF_PS0_WINDOW_VALID', 'SPI_PERF_PS1_2_WAVE_GROUPS',
'SPI_PERF_PS1_ACTIVE', 'SPI_PERF_PS1_BUSY',
'SPI_PERF_PS1_CRAWLER_STALL', 'SPI_PERF_PS1_DEALLOC',
'SPI_PERF_PS1_DEALLOC_FULL', 'SPI_PERF_PS1_EVENT_WAVE',
'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT',
'SPI_PERF_PS1_LDS_DONE_FULL', 'SPI_PERF_PS1_OPT_WAVE',
'SPI_PERF_PS1_PRIM_BIN0', 'SPI_PERF_PS1_PRIM_BIN1',
'SPI_PERF_PS1_WAVE', 'SPI_PERF_PS1_WAVEID_STARVED',
'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY',
'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS1_WAVE_IN_FLIGHT',
'SPI_PERF_PS1_WINDOW_VALID', 'SPI_PERF_PS2_2_WAVE_GROUPS',
'SPI_PERF_PS2_ACTIVE', 'SPI_PERF_PS2_BUSY',
'SPI_PERF_PS2_CRAWLER_STALL', 'SPI_PERF_PS2_DEALLOC',
'SPI_PERF_PS2_DEALLOC_FULL', 'SPI_PERF_PS2_EVENT_WAVE',
'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT',
'SPI_PERF_PS2_LDS_DONE_FULL', 'SPI_PERF_PS2_OPT_WAVE',
'SPI_PERF_PS2_PRIM_BIN0', 'SPI_PERF_PS2_PRIM_BIN1',
'SPI_PERF_PS2_WAVE', 'SPI_PERF_PS2_WAVEID_STARVED',
'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY',
'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS2_WAVE_IN_FLIGHT',
'SPI_PERF_PS2_WINDOW_VALID', 'SPI_PERF_PS3_2_WAVE_GROUPS',
'SPI_PERF_PS3_ACTIVE', 'SPI_PERF_PS3_BUSY',
'SPI_PERF_PS3_CRAWLER_STALL', 'SPI_PERF_PS3_DEALLOC',
'SPI_PERF_PS3_DEALLOC_FULL', 'SPI_PERF_PS3_EVENT_WAVE',
'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT',
'SPI_PERF_PS3_LDS_DONE_FULL', 'SPI_PERF_PS3_OPT_WAVE',
'SPI_PERF_PS3_PRIM_BIN0', 'SPI_PERF_PS3_PRIM_BIN1',
'SPI_PERF_PS3_WAVE', 'SPI_PERF_PS3_WAVEID_STARVED',
'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY',
'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS3_WAVE_IN_FLIGHT',
'SPI_PERF_PS3_WINDOW_VALID', 'SPI_PERF_PS_EXP_ALLOC',
'SPI_PERF_PS_EXP_ARB_CONFLICT', 'SPI_PERF_PS_EXP_DONE',
'SPI_PERF_PS_PERS_UPD_FULL0', 'SPI_PERF_PS_PERS_UPD_FULL1',
'SPI_PERF_PS_PWS_STALL', 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG',
'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN',
'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS',
'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS',
'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS',
'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG',
'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN',
'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS',
'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS',
'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS',
'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG',
'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN',
'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS',
'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS',
'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS',
'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG',
'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN',
'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS',
'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS',
'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', 'SPI_PERF_RA_BAR_CU_FULL_CSG',
'SPI_PERF_RA_BAR_CU_FULL_CSN', 'SPI_PERF_RA_BAR_CU_FULL_GS',
'SPI_PERF_RA_BAR_CU_FULL_HS', 'SPI_PERF_RA_BAR_CU_FULL_PS',
'SPI_PERF_RA_BULKY_CU_FULL_CSG', 'SPI_PERF_RA_BULKY_CU_FULL_CSN',
'SPI_PERF_RA_CSC_UNDER_TUNNEL', 'SPI_PERF_RA_CSG_LOCK',
'SPI_PERF_RA_CSN_LOCK', 'SPI_PERF_RA_GFX_UNDER_TUNNEL',
'SPI_PERF_RA_GS_LDS_OCCUPANCY', 'SPI_PERF_RA_GS_LOCK',
'SPI_PERF_RA_GS_VGPR_OCCUPANCY', 'SPI_PERF_RA_HS_LOCK',
'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN',
'SPI_PERF_RA_LDS_CU_FULL_GS', 'SPI_PERF_RA_LDS_CU_FULL_HS',
'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_PC_PROBE_STALL_PS',
'SPI_PERF_RA_PC_PSWAVE_STALL_PS', 'SPI_PERF_RA_PH_THROTTLE',
'SPI_PERF_RA_PIPE_REQ_BIN2', 'SPI_PERF_RA_PRE_ALLOC_STALL',
'SPI_PERF_RA_PS_LDS_OCCUPANCY', 'SPI_PERF_RA_PS_VGPR_OCCUPANCY',
'SPI_PERF_RA_REQ_ALLOC',
'SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_CU_LEVEL',
'SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_STALL',
'SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_LEVEL',
'SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_STALL',
'SPI_PERF_RA_REQ_NO_ALLOC', 'SPI_PERF_RA_REQ_NO_ALLOC_CSG',
'SPI_PERF_RA_REQ_NO_ALLOC_CSN', 'SPI_PERF_RA_REQ_NO_ALLOC_GS',
'SPI_PERF_RA_REQ_NO_ALLOC_HS', 'SPI_PERF_RA_REQ_NO_ALLOC_PS',
'SPI_PERF_RA_RES_STALL_CSG', 'SPI_PERF_RA_RES_STALL_CSN',
'SPI_PERF_RA_RES_STALL_GS', 'SPI_PERF_RA_RES_STALL_HS',
'SPI_PERF_RA_RES_STALL_PS', 'SPI_PERF_RA_RSV_UPD',
'SPI_PERF_RA_SPI_THROTTLE', 'SPI_PERF_RA_TASK_REQ_BIN3',
'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN',
'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN',
'SPI_PERF_RA_TMP_STALL_GS', 'SPI_PERF_RA_TMP_STALL_HS',
'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG',
'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_GS',
'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS',
'SPI_PERF_RA_WAVE_SIMD_FULL_CSG',
'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_GS',
'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS',
'SPI_PERF_RA_WR_CTL_FULL', 'SPI_PERF_RA_WVALLOC_STALL',
'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN',
'SPI_PERF_RA_WVLIM_STALL_GS', 'SPI_PERF_RA_WVLIM_STALL_HS',
'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_SGPR_INIT',
'SPI_PERF_SWC_CSGN_WR', 'SPI_PERF_SWC_CSN_WR',
'SPI_PERF_SWC_GS_WR', 'SPI_PERF_SWC_HS_WR', 'SPI_PERF_SWC_PS_WR',
'SPI_PERF_VGPR_ALLOC_LEVEL', 'SPI_PERF_VGPR_INIT',
'SPI_PERF_VWC_CSGN_WR', 'SPI_PERF_VWC_CSN_WR',
'SPI_PERF_VWC_ES_WR', 'SPI_PERF_VWC_GS_WR', 'SPI_PERF_VWC_HS_WR',
'SPI_PERF_VWC_LS_WR', 'SPI_PERF_VWC_PS_WR',
'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0',
'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE',
'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T',
'SPI_PS_LDS_GROUP_1', 'SPI_PS_LDS_GROUP_2', 'SPI_PS_LDS_GROUP_4',
'SPI_PS_LDS_GROUP_SIZE', 'SPI_SAMPLE_CNTL', 'SPI_SHADER_1COMP',
'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', 'SPI_SHADER_32_AR',
'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', 'SPI_SHADER_4COMP',
'SPI_SHADER_4COMPRESS', 'SPI_SHADER_EX_FORMAT',
'SPI_SHADER_FORMAT', 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE',
'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR',
'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR',
'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN',
'SP_PERF_SEL_DST_BUF_ALLOC_STALL',
'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', 'SP_PERF_SEL_DST_BUF_ODD_DIRTY',
'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI',
'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', 'SP_PERF_SEL_DUMMY_LAST',
'SP_PERF_SEL_SRC_CACHE_HIT_B0', 'SP_PERF_SEL_SRC_CACHE_HIT_B1',
'SP_PERF_SEL_SRC_CACHE_HIT_B2', 'SP_PERF_SEL_SRC_CACHE_HIT_B3',
'SP_PERF_SEL_SRC_CACHE_PROBE_B0',
'SP_PERF_SEL_SRC_CACHE_PROBE_B1',
'SP_PERF_SEL_SRC_CACHE_PROBE_B2',
'SP_PERF_SEL_SRC_CACHE_PROBE_B3',
'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0',
'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1',
'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2',
'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3',
'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0',
'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1',
'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2',
'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3',
'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0',
'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1',
'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2',
'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3',
'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS',
'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE',
'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY',
'SP_PERF_SEL_VALU_OPERAND',
'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF',
'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL',
'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', 'SP_PERF_SEL_VALU_STALL',
'SP_PERF_SEL_VALU_STALL_DST_STALL',
'SP_PERF_SEL_VALU_STALL_SDST_FWD',
'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY',
'SP_PERF_SEL_VALU_STALL_VDST_FWD',
'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY',
'SP_PERF_SEL_VALU_VGPR_OPERAND',
'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_EXP',
'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_LDS',
'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_TEX',
'SP_PERF_SEL_VGPR_EXP_RD', 'SP_PERF_SEL_VGPR_RD',
'SP_PERF_SEL_VGPR_SPI_WR', 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR',
'SP_PERF_SEL_VGPR_VMEM_RD', 'SP_PERF_SEL_VGPR_WR',
'SP_PERF_SEL_VGPR_WR_KILL', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES',
'SQC_PERF_SEL_DCACHE_CACHE_STALLED',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT',
'SQC_PERF_SEL_DCACHE_FLAT_REQ', 'SQC_PERF_SEL_DCACHE_GCR',
'SQC_PERF_SEL_DCACHE_GCR_HITS',
'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_DCACHE_HITS',
'SQC_PERF_SEL_DCACHE_HIT_LRU_READ',
'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL',
'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT',
'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB',
'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB',
'SQC_PERF_SEL_DCACHE_INVAL_ASYNC',
'SQC_PERF_SEL_DCACHE_INVAL_INST', 'SQC_PERF_SEL_DCACHE_MISSES',
'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE',
'SQC_PERF_SEL_DCACHE_PREFETCH_MISSES',
'SQC_PERF_SEL_DCACHE_PREFETCH_REQ_CACHELINES',
'SQC_PERF_SEL_DCACHE_REQ', 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE',
'SQC_PERF_SEL_DCACHE_REQ_READ_1',
'SQC_PERF_SEL_DCACHE_REQ_READ_16',
'SQC_PERF_SEL_DCACHE_REQ_READ_2',
'SQC_PERF_SEL_DCACHE_REQ_READ_4',
'SQC_PERF_SEL_DCACHE_REQ_READ_8',
'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL',
'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT',
'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL',
'SQC_PERF_SEL_DUMMY_LAST', 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES',
'SQC_PERF_SEL_ICACHE_CACHE_STALLED',
'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX',
'SQC_PERF_SEL_ICACHE_GCR', 'SQC_PERF_SEL_ICACHE_GCR_HITS',
'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_ICACHE_HITS',
'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL',
'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT',
'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB',
'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB',
'SQC_PERF_SEL_ICACHE_INVAL_ASYNC',
'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES',
'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE',
'SQC_PERF_SEL_ICACHE_PREFETCH_MISSES',
'SQC_PERF_SEL_ICACHE_PREFETCH_REQ_CACHELINES',
'SQC_PERF_SEL_ICACHE_REQ',
'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT',
'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL',
'SQC_PERF_SEL_LDS_ACTIVE_ATOMIC_CNT',
'SQC_PERF_SEL_LDS_ACTIVE_LOAD_CNT',
'SQC_PERF_SEL_LDS_ACTIVE_STORE_CNT',
'SQC_PERF_SEL_LDS_ADDR_ACTIVE', 'SQC_PERF_SEL_LDS_ADDR_CONFLICT',
'SQC_PERF_SEL_LDS_ADDR_STALL', 'SQC_PERF_SEL_LDS_ATOMIC_DWORDS',
'SQC_PERF_SEL_LDS_ATOMIC_RETURN',
'SQC_PERF_SEL_LDS_BANKCONF_ATOMIC_CNT',
'SQC_PERF_SEL_LDS_BANKCONF_LOAD_CNT',
'SQC_PERF_SEL_LDS_BANKCONF_STORE_CNT',
'SQC_PERF_SEL_LDS_BANK_CONFLICT',
'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', 'SQC_PERF_SEL_LDS_IDX_ACTIVE',
'SQC_PERF_SEL_LDS_LDS_EXECUTION_STALL',
'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL',
'SQC_PERF_SEL_LDS_LOAD_DWORDS', 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS',
'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD',
'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD',
'SQC_PERF_SEL_LDS_STORE_DWORDS',
'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL',
'SQC_PERF_SEL_LDS_UNALIGNED_STALL', 'SQC_PERF_SEL_LDS_VGPR_BUSY',
'SQC_PERF_SEL_SQ_DCACHE_REQS', 'SQC_PERF_SEL_TC_DATA_READ_REQ',
'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ',
'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL',
'SQC_PERF_SEL_TC_STARVE', 'SQC_PERF_SEL_TD_VGPR_BUSY',
'SQDEC_BEGIN', 'SQDEC_END', 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END',
'SQG_PERF_SEL', 'SQG_PERF_SEL_ACCUM_PREV',
'SQG_PERF_SEL_BUSY_CYCLES', 'SQG_PERF_SEL_CYCLES',
'SQG_PERF_SEL_DUMMY_LAST', 'SQG_PERF_SEL_EVENTS',
'SQG_PERF_SEL_EXP_BUS0_BUSY', 'SQG_PERF_SEL_EXP_BUS1_BUSY',
'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY',
'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', 'SQG_PERF_SEL_ITEMS',
'SQG_PERF_SEL_ITEMS_CS', 'SQG_PERF_SEL_ITEMS_GS',
'SQG_PERF_SEL_ITEMS_HS', 'SQG_PERF_SEL_ITEMS_PS',
'SQG_PERF_SEL_LEVEL_WAVES', 'SQG_PERF_SEL_LEVEL_WGP_ACTIVE',
'SQG_PERF_SEL_MSG', 'SQG_PERF_SEL_MSG_BUS_BUSY',
'SQG_PERF_SEL_MSG_INTERRUPT', 'SQG_PERF_SEL_NONE',
'SQG_PERF_SEL_PS_QUADS', 'SQG_PERF_SEL_REFCLKS',
'SQG_PERF_SEL_TTRACE_LOST_PACKETS', 'SQG_PERF_SEL_TTRACE_STALL',
'SQG_PERF_SEL_TTRACE_WRITE_DATA', 'SQG_PERF_SEL_WAVE32_ITEMS',
'SQG_PERF_SEL_WAVE64_ITEMS', 'SQG_PERF_SEL_WAVES',
'SQG_PERF_SEL_WAVES_32', 'SQG_PERF_SEL_WAVES_64',
'SQG_PERF_SEL_WAVES_CS_VEC32', 'SQG_PERF_SEL_WAVES_DYN_VGPR',
'SQG_PERF_SEL_WAVES_EQ_32', 'SQG_PERF_SEL_WAVES_EQ_64',
'SQG_PERF_SEL_WAVES_GS_VEC32', 'SQG_PERF_SEL_WAVES_HS_VEC32',
'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', 'SQG_PERF_SEL_WAVES_LT_16',
'SQG_PERF_SEL_WAVES_LT_32', 'SQG_PERF_SEL_WAVES_LT_48',
'SQG_PERF_SEL_WAVES_LT_64', 'SQG_PERF_SEL_WAVES_PS_VEC32',
'SQG_PERF_SEL_WAVES_RESTORED', 'SQG_PERF_SEL_WAVES_SAVED',
'SQG_PERF_SEL_WAVES_VEC32', 'SQG_PERF_SEL_WAVES_WGP_TAKEOVER',
'SQG_PERF_SEL_WAVE_CYCLES', 'SQIND_GLOBAL_REGS_OFFSET',
'SQIND_GLOBAL_REGS_SIZE', 'SQIND_LOCAL_REGS_OFFSET',
'SQIND_LOCAL_REGS_SIZE', 'SQIND_WAVE_HOST_REGS_OFFSET',
'SQIND_WAVE_HOST_REGS_SIZE', 'SQIND_WAVE_HW_REGS_OFFSET',
'SQIND_WAVE_HW_REGS_SIZE', 'SQIND_WAVE_SGPRS_OFFSET',
'SQIND_WAVE_SGPRS_SIZE', 'SQIND_WAVE_VGPRS_OFFSET',
'SQIND_WAVE_VGPRS_SIZE', 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END',
'SQPERFSDEC_BEGIN', 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN',
'SQPWRDEC_END', 'SQ_ARB_STATE_ISSUED_BRMSG',
'SQ_ARB_STATE_ISSUED_EXPORT', 'SQ_ARB_STATE_ISSUED_LDS',
'SQ_ARB_STATE_ISSUED_LDS_DIRECT', 'SQ_ARB_STATE_ISSUED_SCALAR',
'SQ_ARB_STATE_ISSUED_TEX', 'SQ_ARB_STATE_ISSUED_VALU',
'SQ_ARB_STATE_STALLED_BRMSG', 'SQ_ARB_STATE_STALLED_EXPORT',
'SQ_ARB_STATE_STALLED_LDS', 'SQ_ARB_STATE_STALLED_LDS_DIRECT',
'SQ_ARB_STATE_STALLED_SCALAR', 'SQ_ARB_STATE_STALLED_TEX',
'SQ_ARB_STATE_STALLED_VALU', 'SQ_CAC_POWER_ALU_BUSY',
'SQ_CAC_POWER_GPR_RD', 'SQ_CAC_POWER_GPR_WR',
'SQ_CAC_POWER_LDS_BUSY', 'SQ_CAC_POWER_SEL',
'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU',
'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2',
'SQ_DISPATCHER_GFX_CNT_PER_RING', 'SQ_DISPATCHER_GFX_MIN',
'SQ_EDC_INFO_SOURCE', 'SQ_EDC_INFO_SOURCE_GDS',
'SQ_EDC_INFO_SOURCE_INST', 'SQ_EDC_INFO_SOURCE_INVALID',
'SQ_EDC_INFO_SOURCE_LDS', 'SQ_EDC_INFO_SOURCE_SGPR',
'SQ_EDC_INFO_SOURCE_TA', 'SQ_EDC_INFO_SOURCE_VGPR',
'SQ_EX_EXCP_ADDR_WATCH', 'SQ_EX_EXCP_ALU_FLOAT_DIV0',
'SQ_EX_EXCP_ALU_INEXACT', 'SQ_EX_EXCP_ALU_INPUT_DENORM',
'SQ_EX_EXCP_ALU_INT_DIV0', 'SQ_EX_EXCP_ALU_INVALID',
'SQ_EX_EXCP_ALU_OVERFLOW', 'SQ_EX_EXCP_ALU_UNDERFLOW',
'SQ_EX_EXCP_VALU_BASE', 'SQ_EX_EXCP_VALU_SIZE', 'SQ_FLAT',
'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT',
'SQ_GLOBAL', 'SQ_IBUF_IB_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_DRET',
'SQ_IBUF_IB_EMPTY_WAIT_GNT', 'SQ_IBUF_IB_IDLE',
'SQ_IBUF_IB_INI_WAIT_DRET', 'SQ_IBUF_IB_INI_WAIT_GNT',
'SQ_IBUF_IB_LE_4DW', 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST',
'SQ_IMG_FILTER_MODE_BLEND', 'SQ_IMG_FILTER_MODE_MAX',
'SQ_IMG_FILTER_MODE_MIN', 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD',
'SQ_IND_CMD_CMD_KILL', 'SQ_IND_CMD_CMD_NULL',
'SQ_IND_CMD_CMD_SAVECTX', 'SQ_IND_CMD_CMD_SETFATALHALT',
'SQ_IND_CMD_CMD_SETHALT', 'SQ_IND_CMD_CMD_SET_SYS_PRIO',
'SQ_IND_CMD_CMD_SINGLE_STEP', 'SQ_IND_CMD_CMD_TRAP',
'SQ_IND_CMD_CMD_TRAP_AFTER_INST', 'SQ_IND_CMD_MODE',
'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME',
'SQ_IND_CMD_MODE_BROADCAST_PIPE',
'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE',
'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV',
'SQ_INST_STR_IB_WAVE_INST_SKIP_AV',
'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV',
'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML',
'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', 'SQ_INST_STR_ST',
'SQ_INST_TYPE', 'SQ_INST_TYPE_BARRIER',
'SQ_INST_TYPE_BRANCH_NOT_TAKEN', 'SQ_INST_TYPE_BRANCH_TAKEN',
'SQ_INST_TYPE_DUAL_VALU', 'SQ_INST_TYPE_EXP', 'SQ_INST_TYPE_FLAT',
'SQ_INST_TYPE_JUMP', 'SQ_INST_TYPE_LDS',
'SQ_INST_TYPE_LDS_DIRECT', 'SQ_INST_TYPE_MSG',
'SQ_INST_TYPE_NONE', 'SQ_INST_TYPE_OTHER', 'SQ_INST_TYPE_SCALAR',
'SQ_INST_TYPE_TEX', 'SQ_INST_TYPE_VALU',
'SQ_INST_TYPE_VALU_MATRIX', 'SQ_LLC_0', 'SQ_LLC_1',
'SQ_LLC_BYPASS', 'SQ_LLC_CTL', 'SQ_LLC_RSVD_2',
'SQ_MAX_PGM_SGPRS', 'SQ_MAX_PGM_VGPRS', 'SQ_NON_EVENT',
'SQ_NO_INST_ISSUE', 'SQ_NO_INST_ISSUE_ALU_DEP',
'SQ_NO_INST_ISSUE_BARRIER_WAIT', 'SQ_NO_INST_ISSUE_INTERNAL',
'SQ_NO_INST_ISSUE_NO_ARB_WIN', 'SQ_NO_INST_ISSUE_NO_INSTS',
'SQ_NO_INST_ISSUE_OTHER', 'SQ_NO_INST_ISSUE_SLEEP_WAIT',
'SQ_NO_INST_ISSUE_S_WAITCNT', 'SQ_OOB_COMPLETE',
'SQ_OOB_INDEX_AND_OFFSET', 'SQ_OOB_INDEX_ONLY',
'SQ_OOB_NUM_RECORDS_0', 'SQ_OOB_SELECT', 'SQ_PERF_SEL',
'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_BUSY_CYCLES',
'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END',
'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS',
'SQ_PERF_SEL_EXP_BUS0_BUSY', 'SQ_PERF_SEL_EXP_BUS1_BUSY',
'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY',
'SQ_PERF_SEL_EXP_REQ_BUS_STALL', 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL',
'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_REQS',
'SQ_PERF_SEL_INSTS_ALL', 'SQ_PERF_SEL_INSTS_BARRIER_LOCK',
'SQ_PERF_SEL_INSTS_BRANCH', 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN',
'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', 'SQ_PERF_SEL_INSTS_DELAY_ALU',
'SQ_PERF_SEL_INSTS_DELAY_ALU_COISSUE',
'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', 'SQ_PERF_SEL_INSTS_EXP',
'SQ_PERF_SEL_INSTS_EXP_MRT', 'SQ_PERF_SEL_INSTS_EXP_Z',
'SQ_PERF_SEL_INSTS_FLAT', 'SQ_PERF_SEL_INSTS_FLAT_ATOMIC',
'SQ_PERF_SEL_INSTS_FLAT_LOAD', 'SQ_PERF_SEL_INSTS_FLAT_STORE',
'SQ_PERF_SEL_INSTS_GLOBAL_SCRATCH', 'SQ_PERF_SEL_INSTS_INTERNAL',
'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD',
'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', 'SQ_PERF_SEL_INSTS_LOCK',
'SQ_PERF_SEL_INSTS_NON_VALU_EXEC_SKIPPED',
'SQ_PERF_SEL_INSTS_SALU', 'SQ_PERF_SEL_INSTS_SALU_CS',
'SQ_PERF_SEL_INSTS_SALU_FLOAT', 'SQ_PERF_SEL_INSTS_SALU_GS',
'SQ_PERF_SEL_INSTS_SALU_HS', 'SQ_PERF_SEL_INSTS_SALU_PS',
'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM',
'SQ_PERF_SEL_INSTS_SMEM_CS', 'SQ_PERF_SEL_INSTS_SMEM_GS',
'SQ_PERF_SEL_INSTS_SMEM_HS', 'SQ_PERF_SEL_INSTS_SMEM_NORM',
'SQ_PERF_SEL_INSTS_SMEM_PS', 'SQ_PERF_SEL_INSTS_TEX',
'SQ_PERF_SEL_INSTS_TEX_ATOMIC_NORTN',
'SQ_PERF_SEL_INSTS_TEX_ATOMIC_RTN',
'SQ_PERF_SEL_INSTS_TEX_BLOCK_LOAD',
'SQ_PERF_SEL_INSTS_TEX_BLOCK_STORE', 'SQ_PERF_SEL_INSTS_TEX_LOAD',
'SQ_PERF_SEL_INSTS_TEX_SAMPLE', 'SQ_PERF_SEL_INSTS_TEX_STORE',
'SQ_PERF_SEL_INSTS_VALU', 'SQ_PERF_SEL_INSTS_VALU_1_PASS',
'SQ_PERF_SEL_INSTS_VALU_2_PASS', 'SQ_PERF_SEL_INSTS_VALU_4_PASS',
'SQ_PERF_SEL_INSTS_VALU_COISSUE', 'SQ_PERF_SEL_INSTS_VALU_DP',
'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED',
'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC',
'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64',
'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_16BIT',
'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_32BIT',
'SQ_PERF_SEL_INSTS_VALU_TRANS', 'SQ_PERF_SEL_INSTS_VALU_TRANS32',
'SQ_PERF_SEL_INSTS_VALU_VINTERP', 'SQ_PERF_SEL_INSTS_VEC32',
'SQ_PERF_SEL_INSTS_VEC32_FLAT',
'SQ_PERF_SEL_INSTS_VEC32_FLAT_ATOMIC',
'SQ_PERF_SEL_INSTS_VEC32_FLAT_LOAD',
'SQ_PERF_SEL_INSTS_VEC32_FLAT_STORE',
'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH',
'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_ATOMIC',
'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_LOAD',
'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_STORE',
'SQ_PERF_SEL_INSTS_VEC32_LDS',
'SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_NORTN',
'SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_RTN',
'SQ_PERF_SEL_INSTS_VEC32_LDS_LOAD',
'SQ_PERF_SEL_INSTS_VEC32_LDS_OTHER',
'SQ_PERF_SEL_INSTS_VEC32_LDS_PARAM_LOAD',
'SQ_PERF_SEL_INSTS_VEC32_LDS_STORE',
'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS',
'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_LOAD',
'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_STORE',
'SQ_PERF_SEL_INSTS_VEC32_TEX',
'SQ_PERF_SEL_INSTS_VEC32_TEX_ATOMIC',
'SQ_PERF_SEL_INSTS_VEC32_TEX_CS',
'SQ_PERF_SEL_INSTS_VEC32_TEX_GS',
'SQ_PERF_SEL_INSTS_VEC32_TEX_HS',
'SQ_PERF_SEL_INSTS_VEC32_TEX_LOAD',
'SQ_PERF_SEL_INSTS_VEC32_TEX_PS',
'SQ_PERF_SEL_INSTS_VEC32_TEX_SAMPLE',
'SQ_PERF_SEL_INSTS_VEC32_TEX_STORE',
'SQ_PERF_SEL_INSTS_VEC32_VALU', 'SQ_PERF_SEL_INSTS_VEC32_VALU_CS',
'SQ_PERF_SEL_INSTS_VEC32_VALU_GS',
'SQ_PERF_SEL_INSTS_VEC32_VALU_HS',
'SQ_PERF_SEL_INSTS_VEC32_VALU_NO_COEXEC',
'SQ_PERF_SEL_INSTS_VEC32_VALU_PS',
'SQ_PERF_SEL_INSTS_VEC32_VALU_TRANS32',
'SQ_PERF_SEL_INSTS_VEC32_VALU_VINTERP',
'SQ_PERF_SEL_INSTS_VEC32_VALU_WMMA',
'SQ_PERF_SEL_INSTS_VGPR_ALLOC',
'SQ_PERF_SEL_INSTS_VGPR_ALLOC_FAIL', 'SQ_PERF_SEL_INSTS_WAKEUP',
'SQ_PERF_SEL_INSTS_WMMA_LOAD', 'SQ_PERF_SEL_INST_BARRIER_STALL',
'SQ_PERF_SEL_INST_CACHE_REQ_STALL', 'SQ_PERF_SEL_INST_CYCLES_EXP',
'SQ_PERF_SEL_INST_CYCLES_FLAT', 'SQ_PERF_SEL_INST_CYCLES_LDS',
'SQ_PERF_SEL_INST_CYCLES_TEX', 'SQ_PERF_SEL_INST_CYCLES_VALU',
'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC',
'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32',
'SQ_PERF_SEL_INST_CYCLES_VMEM',
'SQ_PERF_SEL_INST_CYCLES_VMEM_ATOMIC',
'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD',
'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE',
'SQ_PERF_SEL_INST_ISSUE_ALL_STALL',
'SQ_PERF_SEL_INST_ISSUE_EXP_STALL',
'SQ_PERF_SEL_INST_ISSUE_LDS_STALL',
'SQ_PERF_SEL_INST_ISSUE_SALU_STALL',
'SQ_PERF_SEL_INST_ISSUE_SMEM_STALL',
'SQ_PERF_SEL_INST_ISSUE_TEX_STALL',
'SQ_PERF_SEL_INST_ISSUE_VALU_STALL', 'SQ_PERF_SEL_INST_LEVEL_EXP',
'SQ_PERF_SEL_INST_LEVEL_LDS', 'SQ_PERF_SEL_INST_LEVEL_SMEM',
'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD',
'SQ_PERF_SEL_INST_LEVEL_TEX_STORE',
'SQ_PERF_SEL_INST_WAITCNT_STALL', 'SQ_PERF_SEL_IS_CACHE_DUP_MISS',
'SQ_PERF_SEL_IS_CACHE_MISS', 'SQ_PERF_SEL_IS_CACHE_REQ',
'SQ_PERF_SEL_ITEMS', 'SQ_PERF_SEL_ITEMS_MAX_VALU',
'SQ_PERF_SEL_ITEMS_VALU', 'SQ_PERF_SEL_ITEM_CYCLES_VALU',
'SQ_PERF_SEL_ITEM_CYCLES_VMEM',
'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL',
'SQ_PERF_SEL_LEVEL_WAVES', 'SQ_PERF_SEL_MSG',
'SQ_PERF_SEL_MSG_BUS_BUSY', 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL',
'SQ_PERF_SEL_MSG_INTERRUPT', 'SQ_PERF_SEL_NONE',
'SQ_PERF_SEL_NONE2', 'SQ_PERF_SEL_OVERFLOW_PREV',
'SQ_PERF_SEL_PS_QUADS', 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL',
'SQ_PERF_SEL_SALU_PIPE_STALL', 'SQ_PERF_SEL_SALU_SGATHER_STALL',
'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL',
'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES',
'SQ_PERF_SEL_SP_CONST_CYCLES',
'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', 'SQ_PERF_SEL_USER0',
'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11',
'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14',
'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3',
'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6',
'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9',
'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1',
'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11',
'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13',
'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15',
'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3',
'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5',
'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7',
'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9',
'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL',
'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES',
'SQ_PERF_SEL_VALU_RETURN_SDST',
'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL',
'SQ_PERF_SEL_VALU_SGATHER_STALL',
'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL',
'SQ_PERF_SEL_VALU_STARVE', 'SQ_PERF_SEL_VEC32_INSTS_EXP',
'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', 'SQ_PERF_SEL_VMEM_BUS_ACTIVE',
'SQ_PERF_SEL_VMEM_BUS_STALL',
'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL',
'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL',
'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL',
'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL',
'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY',
'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY',
'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT',
'SQ_PERF_SEL_WAIT_ANY', 'SQ_PERF_SEL_WAIT_BARRIER',
'SQ_PERF_SEL_WAIT_CNT_ANY', 'SQ_PERF_SEL_WAIT_CNT_DS',
'SQ_PERF_SEL_WAIT_CNT_EXP', 'SQ_PERF_SEL_WAIT_CNT_KM',
'SQ_PERF_SEL_WAIT_CNT_LOAD', 'SQ_PERF_SEL_WAIT_CNT_SAMPLE',
'SQ_PERF_SEL_WAIT_CNT_STORE', 'SQ_PERF_SEL_WAIT_DELAY_ALU',
'SQ_PERF_SEL_WAIT_DEPCTR', 'SQ_PERF_SEL_WAIT_EXP_ALLOC',
'SQ_PERF_SEL_WAIT_IFETCH', 'SQ_PERF_SEL_WAIT_INST_ANY',
'SQ_PERF_SEL_WAIT_OTHER', 'SQ_PERF_SEL_WAIT_SLEEP',
'SQ_PERF_SEL_WAIT_TTRACE', 'SQ_PERF_SEL_WAVE32_INSTS',
'SQ_PERF_SEL_WAVE32_ITEMS', 'SQ_PERF_SEL_WAVE64_HALF_SKIP',
'SQ_PERF_SEL_WAVE64_INSTS', 'SQ_PERF_SEL_WAVE64_ITEMS',
'SQ_PERF_SEL_WAVES', 'SQ_PERF_SEL_WAVES_32',
'SQ_PERF_SEL_WAVES_64', 'SQ_PERF_SEL_WAVES_EQ_32',
'SQ_PERF_SEL_WAVES_EQ_64', 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH',
'SQ_PERF_SEL_WAVES_LT_16', 'SQ_PERF_SEL_WAVES_LT_32',
'SQ_PERF_SEL_WAVES_LT_48', 'SQ_PERF_SEL_WAVES_LT_64',
'SQ_PERF_SEL_WAVES_RESTORED', 'SQ_PERF_SEL_WAVES_SAVED',
'SQ_PERF_SEL_WAVE_CYCLES', 'SQ_PERF_SEL_WAVE_READY',
'SQ_ROUND_MINUS_INFINITY', 'SQ_ROUND_MODE',
'SQ_ROUND_NEAREST_EVEN', 'SQ_ROUND_PLUS_INFINITY',
'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', 'SQ_RSRC_BUF_RSVD_1',
'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', 'SQ_RSRC_BUF_TYPE',
'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', 'SQ_RSRC_FLAT_RSVD_2',
'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', 'SQ_RSRC_IMG_1D',
'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', 'SQ_RSRC_IMG_2D_ARRAY',
'SQ_RSRC_IMG_2D_MSAA', 'SQ_RSRC_IMG_2D_MSAA_ARRAY',
'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', 'SQ_RSRC_IMG_RSVD_0',
'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', 'SQ_RSRC_IMG_RSVD_3',
'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', 'SQ_RSRC_IMG_RSVD_6',
'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', 'SQ_SCRATCH',
'SQ_SEL_0', 'SQ_SEL_1', 'SQ_SEL_N_BC_1', 'SQ_SEL_RESERVED_1',
'SQ_SEL_W', 'SQ_SEL_X', 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z',
'SQ_TEX_ANISO_RATIO', 'SQ_TEX_ANISO_RATIO_1',
'SQ_TEX_ANISO_RATIO_16', 'SQ_TEX_ANISO_RATIO_2',
'SQ_TEX_ANISO_RATIO_4', 'SQ_TEX_ANISO_RATIO_8',
'SQ_TEX_BORDER_COLOR', 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK',
'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE',
'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK',
'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER',
'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE',
'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL',
'SQ_TEX_DEPTH_COMPARE_GREATER',
'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS',
'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER',
'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER',
'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE',
'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ',
'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER',
'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL',
'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER',
'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT',
'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT',
'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR',
'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', 'SQ_WATCH_MODES',
'SQ_WATCH_MODE_ALL', 'SQ_WATCH_MODE_ATOMIC',
'SQ_WATCH_MODE_NONREAD', 'SQ_WATCH_MODE_READ',
'SQ_WAVE_FWD_PROG_INTERVAL', 'SQ_WAVE_FWD_PROG_INTERVAL_1024',
'SQ_WAVE_FWD_PROG_INTERVAL_256', 'SQ_WAVE_FWD_PROG_INTERVAL_4096',
'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', 'SQ_WAVE_IB_DEP_HOLD_CNT_SIZE',
'SQ_WAVE_IB_DEP_LDS_DIR_SIZE', 'SQ_WAVE_IB_DEP_SA_EXEC_SIZE',
'SQ_WAVE_IB_DEP_SA_M0_SIZE', 'SQ_WAVE_IB_DEP_SA_SDST_SIZE',
'SQ_WAVE_IB_DEP_VA_EXEC_SIZE', 'SQ_WAVE_IB_DEP_VA_SDST_SIZE',
'SQ_WAVE_IB_DEP_VA_SSRC_SIZE', 'SQ_WAVE_IB_DEP_VA_VCC_SIZE',
'SQ_WAVE_IB_DEP_VA_VDST_SIZE', 'SQ_WAVE_IB_DEP_VM_VSRC_SIZE',
'SQ_WAVE_SCHED_MODES',
'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST_VM_VSRC',
'SQ_WAVE_SCHED_MODE_EXPERT', 'SQ_WAVE_SCHED_MODE_NORMAL',
'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', 'SQ_WAVE_TYPE_GS',
'SQ_WAVE_TYPE_HS', 'SQ_WAVE_TYPE_PS', 'SQ_WAVE_TYPE_PS0',
'SQ_WAVE_TYPE_PS1', 'SQ_WAVE_TYPE_PS2', 'SQ_WAVE_TYPE_PS3',
'SQ_WAVE_TYPE_RSVD0', 'SQ_WAVE_TYPE_RSVD1', 'SQ_WAVE_TYPE_RSVD2',
'STALL', 'STENCIL_ADD_CLAMP', 'STENCIL_ADD_WRAP', 'STENCIL_AND',
'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR',
'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP',
'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP',
'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO',
'STREAM_0_SYNCHRONIZATION',
'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_10_SYNCHRONIZATION',
'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_11_SYNCHRONIZATION',
'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_12_SYNCHRONIZATION',
'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_13_SYNCHRONIZATION',
'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_14_SYNCHRONIZATION',
'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_15_SYNCHRONIZATION',
'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_1_SYNCHRONIZATION',
'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_2_SYNCHRONIZATION',
'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_3_SYNCHRONIZATION',
'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_4_SYNCHRONIZATION',
'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_5_SYNCHRONIZATION',
'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_6_SYNCHRONIZATION',
'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_7_SYNCHRONIZATION',
'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_8_SYNCHRONIZATION',
'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_9_SYNCHRONIZATION',
'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM',
'STRM_PERFMON_STATE_DISABLE_AND_RESET',
'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM',
'STRM_PERFMON_STATE_RESERVED_3',
'STRM_PERFMON_STATE_START_COUNTING',
'STRM_PERFMON_STATE_STOP_COUNTING', 'SURFACE_DCC',
'SURFACE_DCC_BLOCK_IS_IND_128B', 'SURFACE_DCC_BLOCK_IS_IND_64B',
'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL',
'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', 'SURFACE_DCC_IND_128B',
'SURFACE_DCC_IND_64B', 'SURFACE_DCC_IND_BLK',
'SURFACE_DCC_IS_IND_128B', 'SURFACE_DCC_IS_IND_64B',
'SURFACE_DCC_IS_NOT_IND_128B', 'SURFACE_DCC_IS_NOT_IND_64B',
'SURFACE_FLIP_AWAY_INT_LEVEL', 'SURFACE_FLIP_AWAY_INT_PULSE',
'SURFACE_FLIP_AWAY_INT_TYPE', 'SURFACE_FLIP_EXEC_DEBUG_MODE',
'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE',
'SURFACE_FLIP_EXEC_NORMAL_MODE', 'SURFACE_FLIP_INT_LEVEL',
'SURFACE_FLIP_INT_PULSE', 'SURFACE_FLIP_INT_TYPE',
'SURFACE_FLIP_IN_STEREOSYNC', 'SURFACE_FLIP_IN_STEREOSYNC_MODE',
'SURFACE_FLIP_MODE_FOR_STEREOSYNC',
'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED',
'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE',
'SURFACE_FLIP_STEREO_SELECT_DISABLE',
'SURFACE_FLIP_STEREO_SELECT_DISABLED',
'SURFACE_FLIP_STEREO_SELECT_ENABLED',
'SURFACE_FLIP_STEREO_SELECT_POLARITY',
'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT',
'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT',
'SURFACE_FLIP_TYPE', 'SURFACE_FLIP_VUPDATE_SKIP_NUM',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_0',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_1',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_10',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_11',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_12',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_13',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_14',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_15',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_2',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_3',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_4',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_5',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_6',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_7',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_8',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', 'SURFACE_INUSE_IS_LATCHED',
'SURFACE_INUSE_IS_NOT_LATCHED', 'SURFACE_INUSE_RAED_NO_LATCH',
'SURFACE_IS_DCC', 'SURFACE_IS_NOT_DCC', 'SURFACE_IS_NOT_TMZ',
'SURFACE_IS_TMZ', 'SURFACE_I_FLIP', 'SURFACE_PIXEL_FORMAT',
'SURFACE_TMZ', 'SURFACE_UPDATE_IS_LOCKED',
'SURFACE_UPDATE_IS_UNLOCKED', 'SURFACE_UPDATE_LOCK',
'SURFACE_V_FLIP', 'SU_PERFCNT_SEL', 'SWATH_HEIGHT',
'SWATH_HEIGHT_16L', 'SWATH_HEIGHT_1L', 'SWATH_HEIGHT_2L',
'SWATH_HEIGHT_4L', 'SWATH_HEIGHT_8L', 'SX_BLEND_OPT',
'SX_CB_RAT_ACK_REQUEST', 'SX_DOWNCONVERT_FORMAT',
'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', 'SX_PERF_SEL_CLOCK',
'SX_PERF_SEL_CLOCK_DROP_STALL', 'SX_PERF_SEL_COL_BUSY',
'SX_PERF_SEL_DB0_4X2_DISCARD', 'SX_PERF_SEL_DB0_END_OF_WAVE',
'SX_PERF_SEL_DB0_HALF_QUADS', 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS',
'SX_PERF_SEL_DB0_MRT_DISCARD_SRC',
'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST',
'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS',
'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS',
'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL',
'SX_PERF_SEL_DB0_PRED_PIXELS', 'SX_PERF_SEL_DB0_SIZE',
'SX_PERF_SEL_DB1_4X2_DISCARD', 'SX_PERF_SEL_DB1_END_OF_WAVE',
'SX_PERF_SEL_DB1_HALF_QUADS', 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS',
'SX_PERF_SEL_DB1_MRT_DISCARD_SRC',
'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST',
'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS',
'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS',
'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL',
'SX_PERF_SEL_DB1_PRED_PIXELS', 'SX_PERF_SEL_DB1_SIZE',
'SX_PERF_SEL_DB2_4X2_DISCARD', 'SX_PERF_SEL_DB2_END_OF_WAVE',
'SX_PERF_SEL_DB2_HALF_QUADS', 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS',
'SX_PERF_SEL_DB2_MRT_DISCARD_SRC',
'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST',
'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS',
'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS',
'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL',
'SX_PERF_SEL_DB2_PRED_PIXELS', 'SX_PERF_SEL_DB2_SIZE',
'SX_PERF_SEL_DB3_4X2_DISCARD', 'SX_PERF_SEL_DB3_END_OF_WAVE',
'SX_PERF_SEL_DB3_HALF_QUADS', 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS',
'SX_PERF_SEL_DB3_MRT_DISCARD_SRC',
'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST',
'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS',
'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS',
'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL',
'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_DB3_SIZE',
'SX_PERF_SEL_GATE_EN1', 'SX_PERF_SEL_GATE_EN2',
'SX_PERF_SEL_GATE_EN3', 'SX_PERF_SEL_GATE_EN4',
'SX_PERF_SEL_GATE_EN5', 'SX_PERF_SEL_GATE_EN6',
'SX_PERF_SEL_GATE_EN7', 'SX_PERF_SEL_GATE_EN8',
'SX_PERF_SEL_IDX_BUSY', 'SX_PERF_SEL_IDX_IDLE_CYCLES',
'SX_PERF_SEL_IDX_REQ', 'SX_PERF_SEL_IDX_REQ_LATENCY',
'SX_PERF_SEL_IDX_RET', 'SX_PERF_SEL_IDX_SCBD_STALL',
'SX_PERF_SEL_IDX_STALL_CYCLES', 'SX_PERF_SEL_PA_IDLE_CYCLES',
'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_POS_BANK_CONF',
'SX_PERF_SEL_PA_REQ', 'SX_PERF_SEL_PA_REQ_LATENCY',
'SX_PERF_SEL_POS_BUSY', 'SX_PERF_SEL_POS_SCBD_STALL',
'SX_PERF_SEL_SH_COLOR_STALL', 'SX_PERF_SEL_SH_COLOR_STARVE',
'SX_PERF_SEL_SH_IDX_STARVE', 'SX_PERF_SEL_SH_POS_STALL',
'SX_PERF_SEL_SH_POS_STARVE', 'SX_RT_EXPORT_10_11_11',
'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR',
'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10',
'SX_RT_EXPORT_2_10_10_10_6E4', 'SX_RT_EXPORT_2_10_10_10_7E3',
'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4',
'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8',
'SX_RT_EXPORT_9_9_9_E5', 'SX_RT_EXPORT_NO_CONVERSION',
'SYMCLK_FE_SRC', 'SYMCLK_FE_SRC_RESERVED',
'SYMCLK_FE_SRC_UNIPHYA', 'SYMCLK_FE_SRC_UNIPHYB',
'SYMCLK_FE_SRC_UNIPHYC', 'SYMCLK_FE_SRC_UNIPHYD', 'ScMap',
'ScUncertaintyRegionMode', 'ScUncertaintyRegionMult', 'ScXsel',
'ScYsel', 'SeMap', 'SePairMap', 'SePairXsel', 'SePairYsel',
'SeXsel', 'SeYsel', 'StencilOp', 'TA_PERFCOUNT_SEL',
'TA_PERF_SEL_NULL', 'TA_PERF_SEL_addr_stalled_by_tc_cycles',
'TA_PERF_SEL_addr_stalled_by_td_cycles',
'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy',
'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles',
'TA_PERF_SEL_addresser_stalled_cycles',
'TA_PERF_SEL_aligner_busy',
'TA_PERF_SEL_aligner_clk_valid_cycles',
'TA_PERF_SEL_aligner_cycles', 'TA_PERF_SEL_aniso_10_cycle_quads',
'TA_PERF_SEL_aniso_12_cycle_quads',
'TA_PERF_SEL_aniso_14_cycle_quads',
'TA_PERF_SEL_aniso_16_cycle_quads',
'TA_PERF_SEL_aniso_1_cycle_quads',
'TA_PERF_SEL_aniso_2_cycle_quads',
'TA_PERF_SEL_aniso_4_cycle_quads',
'TA_PERF_SEL_aniso_6_cycle_quads',
'TA_PERF_SEL_aniso_8_cycle_quads',
'TA_PERF_SEL_aniso_gt1_cycle_quads',
'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles',
'TA_PERF_SEL_aniso_stalled_cycles',
'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions',
'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions',
'TA_PERF_SEL_atomic_write_data_input_cycles',
'TA_PERF_SEL_atomic_write_data_output_cycles',
'TA_PERF_SEL_bf_busy',
'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles',
'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles',
'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions',
'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions',
'TA_PERF_SEL_buffer_atomic_wavefronts',
'TA_PERF_SEL_buffer_flat_1_op_burst',
'TA_PERF_SEL_buffer_flat_2to3_op_burst',
'TA_PERF_SEL_buffer_flat_4to31_op_burst',
'TA_PERF_SEL_buffer_flat_clk_valid_cycles',
'TA_PERF_SEL_buffer_flat_ge32_op_burst',
'TA_PERF_SEL_buffer_has_index_instructions',
'TA_PERF_SEL_buffer_has_offset_instructions',
'TA_PERF_SEL_buffer_load_wavefronts',
'TA_PERF_SEL_buffer_store_wavefronts',
'TA_PERF_SEL_buffer_total_cycles',
'TA_PERF_SEL_buffer_wavefronts',
'TA_PERF_SEL_color_1_cycle_quads',
'TA_PERF_SEL_color_2_cycle_quads',
'TA_PERF_SEL_color_3_cycle_quads',
'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles',
'TA_PERF_SEL_deriv_stalled_cycles',
'TA_PERF_SEL_flat_1_address_input_vgpr_instructions',
'TA_PERF_SEL_flat_2_address_input_vgpr_instructions',
'TA_PERF_SEL_flat_atomic_wavefronts',
'TA_PERF_SEL_flat_load_wavefronts',
'TA_PERF_SEL_flat_store_wavefronts',
'TA_PERF_SEL_flat_total_cycles', 'TA_PERF_SEL_flat_wavefronts',
'TA_PERF_SEL_gradient_busy',
'TA_PERF_SEL_gradient_clk_valid_cycles',
'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy',
'TA_PERF_SEL_harvestable_clk_enabled_cycles',
'TA_PERF_SEL_ibubble_16to31_cycle_burst',
'TA_PERF_SEL_ibubble_1_cycle_burst',
'TA_PERF_SEL_ibubble_2to3_cycle_burst',
'TA_PERF_SEL_ibubble_32to63_cycle_burst',
'TA_PERF_SEL_ibubble_4to15_cycle_burst',
'TA_PERF_SEL_ibubble_ge64_cycle_burst',
'TA_PERF_SEL_image_atomic_wavefronts',
'TA_PERF_SEL_image_linked_1_op_burst',
'TA_PERF_SEL_image_linked_2to3_op_burst',
'TA_PERF_SEL_image_linked_4to7_op_burst',
'TA_PERF_SEL_image_linked_ge8_op_burst',
'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions',
'TA_PERF_SEL_image_nosampler_1_op_burst',
'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions',
'TA_PERF_SEL_image_nosampler_2to3_op_burst',
'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions',
'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions',
'TA_PERF_SEL_image_nosampler_4to31_op_burst',
'TA_PERF_SEL_image_nosampler_ge32_op_burst',
'TA_PERF_SEL_image_nosampler_has_q_instructions',
'TA_PERF_SEL_image_nosampler_has_r_instructions',
'TA_PERF_SEL_image_nosampler_has_t_instructions',
'TA_PERF_SEL_image_nosampler_total_cycles',
'TA_PERF_SEL_image_read_wavefronts',
'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_1_op_burst',
'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_2to3_op_burst',
'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_4to7_op_burst',
'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_ge8_op_burst',
'TA_PERF_SEL_image_sampler_has_bias_instructions',
'TA_PERF_SEL_image_sampler_has_dr_instructions',
'TA_PERF_SEL_image_sampler_has_ds_instructions',
'TA_PERF_SEL_image_sampler_has_dt_instructions',
'TA_PERF_SEL_image_sampler_has_offset_instructions',
'TA_PERF_SEL_image_sampler_has_q_instructions',
'TA_PERF_SEL_image_sampler_has_r_instructions',
'TA_PERF_SEL_image_sampler_has_reference_instructions',
'TA_PERF_SEL_image_sampler_has_t_instructions',
'TA_PERF_SEL_image_sampler_total_cycles',
'TA_PERF_SEL_image_sampler_wavefronts',
'TA_PERF_SEL_image_store_wavefronts',
'TA_PERF_SEL_image_wavefronts', 'TA_PERF_SEL_in_addr_cycles',
'TA_PERF_SEL_in_busy', 'TA_PERF_SEL_in_cfifo_busy',
'TA_PERF_SEL_in_data_cycles', 'TA_PERF_SEL_in_fifos_busy',
'TA_PERF_SEL_in_qfifo_busy', 'TA_PERF_SEL_in_rfifo_busy',
'TA_PERF_SEL_in_waiting_on_req_cycles',
'TA_PERF_SEL_in_wfifo_busy',
'TA_PERF_SEL_lod_aniso_clk_valid_cycles', 'TA_PERF_SEL_lod_busy',
'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_quads',
'TA_PERF_SEL_mip_2_cycle_quads',
'TA_PERF_SEL_mipmap_invalid_samples',
'TA_PERF_SEL_mipmap_lod_0_samples',
'TA_PERF_SEL_mipmap_lod_10_samples',
'TA_PERF_SEL_mipmap_lod_11_samples',
'TA_PERF_SEL_mipmap_lod_12_samples',
'TA_PERF_SEL_mipmap_lod_13_samples',
'TA_PERF_SEL_mipmap_lod_14_samples',
'TA_PERF_SEL_mipmap_lod_15_samples',
'TA_PERF_SEL_mipmap_lod_16_samples',
'TA_PERF_SEL_mipmap_lod_1_samples',
'TA_PERF_SEL_mipmap_lod_2_samples',
'TA_PERF_SEL_mipmap_lod_3_samples',
'TA_PERF_SEL_mipmap_lod_4_samples',
'TA_PERF_SEL_mipmap_lod_5_samples',
'TA_PERF_SEL_mipmap_lod_6_samples',
'TA_PERF_SEL_mipmap_lod_7_samples',
'TA_PERF_SEL_mipmap_lod_8_samples',
'TA_PERF_SEL_mipmap_lod_9_samples',
'TA_PERF_SEL_non_harvestable_clk_enabled_cycles',
'TA_PERF_SEL_nonsampler_clk_valid_cycles', 'TA_PERF_SEL_ns_busy',
'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input',
'TA_PERF_SEL_num_nodes_invalidated_due_to_oob',
'TA_PERF_SEL_num_unlit_nodes_ta_opt',
'TA_PERF_SEL_point_sampled_quads',
'TA_PERF_SEL_register_clk_valid_cycles',
'TA_PERF_SEL_sampler_addressing_clk_valid_cycles',
'TA_PERF_SEL_sampler_clk_valid_cycles',
'TA_PERF_SEL_sampler_op_quads', 'TA_PERF_SEL_smp_busy_ns_idle',
'TA_PERF_SEL_smp_idle_ns_busy',
'TA_PERF_SEL_store_2_write_data_vgpr_instructions',
'TA_PERF_SEL_store_3_write_data_vgpr_instructions',
'TA_PERF_SEL_store_4_write_data_vgpr_instructions',
'TA_PERF_SEL_store_has_w_instructions',
'TA_PERF_SEL_store_has_x_instructions',
'TA_PERF_SEL_store_has_y_instructions',
'TA_PERF_SEL_store_has_z_instructions',
'TA_PERF_SEL_store_write_data_input_cycles',
'TA_PERF_SEL_store_write_data_output_cycles',
'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles',
'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles',
'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles',
'TA_PERF_SEL_ta_busy', 'TA_PERF_SEL_tcreq_clk_valid_cycles',
'TA_PERF_SEL_total_wavefronts', 'TA_PERF_SEL_vmemcmd_cycles',
'TA_PERF_SEL_vmemreq_cycles', 'TA_PERF_SEL_vol_1_cycle_quads',
'TA_PERF_SEL_vol_2_cycle_quads', 'TA_PERF_SEL_walker_cycles',
'TA_PERF_SEL_write_1_op_burst', 'TA_PERF_SEL_write_2to3_op_burst',
'TA_PERF_SEL_write_4to31_op_burst',
'TA_PERF_SEL_write_data_clk_valid_cycles',
'TA_PERF_SEL_write_ge32_op_burst', 'TA_PERF_SEL_write_path_busy',
'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR',
'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1',
'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3',
'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED',
'TA_TC_REQ_MODES', 'TA_TC_REQ_MODE_BORDER', 'TA_TC_REQ_MODE_BYTE',
'TA_TC_REQ_MODE_BYTE_NV', 'TA_TC_REQ_MODE_DWORD',
'TA_TC_REQ_MODE_NORMAL', 'TA_TC_REQ_MODE_TEX0',
'TA_TC_REQ_MODE_TEX1', 'TA_TC_REQ_MODE_TEX2', 'TCC_MTYPE',
'TCP_CACHE_POLICIES', 'TCP_CACHE_POLICY_HIT_EVICT',
'TCP_CACHE_POLICY_HIT_LRU', 'TCP_CACHE_POLICY_MISS_EVICT',
'TCP_CACHE_POLICY_MISS_LRU', 'TCP_CACHE_STORE_POLICIES',
'TCP_CACHE_STORE_POLICY_WT_EVICT',
'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_COMPRESSION_BYPASS',
'TCP_COMPRESSION_BYPASS_DIS', 'TCP_COMPRESSION_BYPASS_EN',
'TCP_COMPRESSION_OVERRIDE', 'TCP_COMPRESSION_OVERRIDE_DIS',
'TCP_COMPRESSION_OVERRIDE_EN', 'TCP_OPCODE_ATOMIC',
'TCP_OPCODE_ATOMIC_CMPSWAP', 'TCP_OPCODE_GATHERH',
'TCP_OPCODE_INV', 'TCP_OPCODE_LOAD', 'TCP_OPCODE_READ',
'TCP_OPCODE_SAMPLER', 'TCP_OPCODE_TYPE', 'TCP_OPCODE_WRITE',
'TCP_PERFCOUNT_SELECT', 'TCP_PERF_SEL_ALLOC_STALL',
'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL',
'TCP_PERF_SEL_BURST_BIN_READHIT_0',
'TCP_PERF_SEL_BURST_BIN_READHIT_1',
'TCP_PERF_SEL_BURST_BIN_READHIT_2to4',
'TCP_PERF_SEL_BURST_BIN_READHIT_5to8',
'TCP_PERF_SEL_BURST_BIN_READHIT_9to16',
'TCP_PERF_SEL_BURST_BIN_READHIT_gt16',
'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_0',
'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_1to2',
'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_3to4',
'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_5to8',
'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_9to16',
'TCP_PERF_SEL_COMP_TEX_LOAD_STALL',
'TCP_PERF_SEL_DATA_FIFO_STALL', 'TCP_PERF_SEL_GATE_EN1',
'TCP_PERF_SEL_GATE_EN2', 'TCP_PERF_SEL_GL1_GRANT_READ_STALL',
'TCP_PERF_SEL_GL1_PENDING_STALL', 'TCP_PERF_SEL_GL1_READ_LATENCY',
'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET',
'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', 'TCP_PERF_SEL_GL1_REQ_LU',
'TCP_PERF_SEL_GL1_REQ_READ', 'TCP_PERF_SEL_GL1_REQ_READ_128B',
'TCP_PERF_SEL_GL1_REQ_READ_64B', 'TCP_PERF_SEL_GL1_REQ_WRITE',
'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE',
'TCP_PERF_SEL_GL1_TCP_RDRET_STALL',
'TCP_PERF_SEL_GL1_WRITE_LATENCY', 'TCP_PERF_SEL_LFIFO_STALL',
'TCP_PERF_SEL_LOD_STALL', 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL',
'TCP_PERF_SEL_POWER_STALL',
'TCP_PERF_SEL_READ_DATACONFLICT_STALL',
'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', 'TCP_PERF_SEL_REQ',
'TCP_PERF_SEL_REQ_MISS', 'TCP_PERF_SEL_REQ_MISS_TAGBANK0',
'TCP_PERF_SEL_REQ_MISS_TAGBANK1',
'TCP_PERF_SEL_REQ_MISS_TAGBANK2',
'TCP_PERF_SEL_REQ_MISS_TAGBANK3', 'TCP_PERF_SEL_REQ_NON_READ',
'TCP_PERF_SEL_REQ_READ', 'TCP_PERF_SEL_REQ_READ_HIT_LRU',
'TCP_PERF_SEL_REQ_READ_MISS_EVICT',
'TCP_PERF_SEL_REQ_TAGBANK0_SET0',
'TCP_PERF_SEL_REQ_TAGBANK0_SET1',
'TCP_PERF_SEL_REQ_TAGBANK1_SET0',
'TCP_PERF_SEL_REQ_TAGBANK1_SET1',
'TCP_PERF_SEL_REQ_TAGBANK2_SET0',
'TCP_PERF_SEL_REQ_TAGBANK2_SET1',
'TCP_PERF_SEL_REQ_TAGBANK3_SET0',
'TCP_PERF_SEL_REQ_TAGBANK3_SET1',
'TCP_PERF_SEL_REQ_TAG_MATCH_AND_LU_INVALIDATE',
'TCP_PERF_SEL_REQ_TAG_MATCH_AND_NOT_VALID',
'TCP_PERF_SEL_REQ_WRITE', 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT',
'TCP_PERF_SEL_TAGFAKE_EOW', 'TCP_PERF_SEL_TA_REQ',
'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET',
'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET',
'TCP_PERF_SEL_TA_REQ_BUFFERNOP', 'TCP_PERF_SEL_TA_REQ_GL0_INV',
'TCP_PERF_SEL_TA_REQ_READ', 'TCP_PERF_SEL_TA_REQ_STATE_READ',
'TCP_PERF_SEL_TA_REQ_WRITE', 'TCP_PERF_SEL_TA_TCP_REQ_STARVE',
'TCP_PERF_SEL_TA_TC_REQ_EN_SUM', 'TCP_PERF_SEL_TCP_LATENCY',
'TCP_PERF_SEL_TCP_TA_REQ_STALL',
'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', 'TCP_PERF_SEL_TD_TCP_STALL',
'TCP_PERF_SEL_WRITECOMBINE_ENDCLAUSE',
'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL',
'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', 'TCP_WATCH_MODES',
'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC',
'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ',
'TCP_WRITE_COMPRESSION_DISABLE',
'TCP_WRITE_COMPRESSION_DISABLE_DIS',
'TCP_WRITE_COMPRESSION_DISABLE_EN', 'TC_EA_CID', 'TC_EA_CID_CPF',
'TC_EA_CID_CPG', 'TC_EA_CID_DCC', 'TC_EA_CID_FMASK',
'TC_EA_CID_HTILE', 'TC_EA_CID_IA', 'TC_EA_CID_MISC',
'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC',
'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA',
'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', 'TC_NACKS',
'TC_NACK_DATA_ERROR', 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT',
'TC_NACK_PROTECTION_FAULT', 'TC_OP', 'TC_OP_ATOMIC_ADD_32',
'TC_OP_ATOMIC_ADD_64', 'TC_OP_ATOMIC_ADD_RTN_32',
'TC_OP_ATOMIC_ADD_RTN_64', 'TC_OP_ATOMIC_AND_32',
'TC_OP_ATOMIC_AND_64', 'TC_OP_ATOMIC_AND_RTN_32',
'TC_OP_ATOMIC_AND_RTN_64', 'TC_OP_ATOMIC_CMPSWAP_32',
'TC_OP_ATOMIC_CMPSWAP_64', 'TC_OP_ATOMIC_CMPSWAP_RTN_32',
'TC_OP_ATOMIC_CMPSWAP_RTN_64', 'TC_OP_ATOMIC_DEC_32',
'TC_OP_ATOMIC_DEC_64', 'TC_OP_ATOMIC_DEC_RTN_32',
'TC_OP_ATOMIC_DEC_RTN_64', 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32',
'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32',
'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64',
'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32',
'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64',
'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32',
'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64',
'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64',
'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64',
'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32',
'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64',
'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32',
'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64',
'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64',
'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64',
'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32',
'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64',
'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32',
'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64',
'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64',
'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64',
'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64',
'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64',
'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64',
'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64',
'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64',
'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64',
'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64',
'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64',
'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64',
'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64',
'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64',
'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64',
'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64',
'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64',
'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64',
'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64',
'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64',
'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS',
'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN',
'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER',
'TC_OP_READ', 'TC_OP_RESERVED_FADD_32',
'TC_OP_RESERVED_FADD_RTN_32', 'TC_OP_RESERVED_FOP_32_0',
'TC_OP_RESERVED_FOP_32_2', 'TC_OP_RESERVED_FOP_64_0',
'TC_OP_RESERVED_FOP_64_1', 'TC_OP_RESERVED_FOP_64_2',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1',
'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_2',
'TC_OP_RESERVED_FOP_RTN_64_0', 'TC_OP_RESERVED_FOP_RTN_64_1',
'TC_OP_RESERVED_FOP_RTN_64_2', 'TC_OP_RESERVED_NON_FLOAT_32_1',
'TC_OP_RESERVED_NON_FLOAT_32_2', 'TC_OP_RESERVED_NON_FLOAT_32_3',
'TC_OP_RESERVED_NON_FLOAT_32_4', 'TC_OP_RESERVED_NON_FLOAT_64_1',
'TC_OP_RESERVED_NON_FLOAT_64_2', 'TC_OP_RESERVED_NON_FLOAT_64_3',
'TC_OP_RESERVED_NON_FLOAT_64_4',
'TC_OP_RESERVED_NON_FLOAT_RTN_32_0',
'TC_OP_RESERVED_NON_FLOAT_RTN_32_1',
'TC_OP_RESERVED_NON_FLOAT_RTN_32_2',
'TC_OP_RESERVED_NON_FLOAT_RTN_32_3',
'TC_OP_RESERVED_NON_FLOAT_RTN_64_1',
'TC_OP_RESERVED_NON_FLOAT_RTN_64_2',
'TC_OP_RESERVED_NON_FLOAT_RTN_64_3',
'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1',
'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2',
'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC',
'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL',
'TD_PERF_SEL_2x_sampler_op_with_1_unlit_quad',
'TD_PERF_SEL_2x_sampler_op_with_both_quads_unlit',
'TD_PERF_SEL_all_pipes_sclk_on_at_same_time',
'TD_PERF_SEL_blend_prt_with_prt_default_0',
'TD_PERF_SEL_box_non_opaque_culled',
'TD_PERF_SEL_box_opaque_culled',
'TD_PERF_SEL_box_with_procedural_children_only_culled',
'TD_PERF_SEL_box_with_triangle_children_only_culled',
'TD_PERF_SEL_bubble_bin_lds_stall_1to3',
'TD_PERF_SEL_bubble_bin_lds_stall_4to7',
'TD_PERF_SEL_bubble_bin_lds_stall_8to15',
'TD_PERF_SEL_bubble_bin_lds_stall_gt15',
'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0',
'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1',
'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511',
'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31',
'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127',
'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511',
'TD_PERF_SEL_burst_bin_gather_1',
'TD_PERF_SEL_burst_bin_gather_2to8',
'TD_PERF_SEL_burst_bin_gather_9to16',
'TD_PERF_SEL_burst_bin_gather_gt16',
'TD_PERF_SEL_burst_bin_nofilter_1',
'TD_PERF_SEL_burst_bin_nofilter_2to4',
'TD_PERF_SEL_burst_bin_nofilter_5to7',
'TD_PERF_SEL_burst_bin_nofilter_8to16',
'TD_PERF_SEL_burst_bin_nofilter_gt16',
'TD_PERF_SEL_burst_bin_preempting_nofilter_1',
'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4',
'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7',
'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16',
'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16',
'TD_PERF_SEL_burst_bin_sampler_1',
'TD_PERF_SEL_burst_bin_sampler_2to8',
'TD_PERF_SEL_burst_bin_sampler_9to16',
'TD_PERF_SEL_burst_bin_sampler_gt16',
'TD_PERF_SEL_bypassLerp_instr',
'TD_PERF_SEL_core_state_ram_max_cnt',
'TD_PERF_SEL_core_state_rams_read', 'TD_PERF_SEL_d16_en_instr',
'TD_PERF_SEL_done_scoreboard_bp_due_to_lds',
'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo',
'TD_PERF_SEL_done_scoreboard_is_full',
'TD_PERF_SEL_done_scoreboard_max_stored_cnt',
'TD_PERF_SEL_done_scoreboard_max_waiting_cnt',
'TD_PERF_SEL_done_scoreboard_not_empty',
'TD_PERF_SEL_four_comp_return_instr',
'TD_PERF_SEL_gather4_2x_instr', 'TD_PERF_SEL_gather4_instr',
'TD_PERF_SEL_gather4h_2x_instr', 'TD_PERF_SEL_gather4h_instr',
'TD_PERF_SEL_getlod_2x_instr', 'TD_PERF_SEL_getlod_instr',
'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full',
'TD_PERF_SEL_input_busy', 'TD_PERF_SEL_input_state_fifo_full',
'TD_PERF_SEL_instance_mask_culled',
'TD_PERF_SEL_instruction_dest_is_lds', 'TD_PERF_SEL_lds_stall',
'TD_PERF_SEL_load_instr', 'TD_PERF_SEL_lod_warn_from_ta',
'TD_PERF_SEL_min_max_filter_instr', 'TD_PERF_SEL_mixmode_instr',
'TD_PERF_SEL_mixmode_resource', 'TD_PERF_SEL_msaa_load_instr',
'TD_PERF_SEL_nofilter_busy',
'TD_PERF_SEL_nofilter_byte_cycling_16cycles',
'TD_PERF_SEL_nofilter_byte_cycling_4cycles',
'TD_PERF_SEL_nofilter_byte_cycling_8cycles',
'TD_PERF_SEL_nofilter_d16_sclk_en',
'TD_PERF_SEL_nofilter_d32_sclk_en',
'TD_PERF_SEL_nofilter_dword_cycling_2cycles',
'TD_PERF_SEL_nofilter_dword_cycling_4cycles',
'TD_PERF_SEL_nofilter_formatters_turned_on',
'TD_PERF_SEL_nofilter_insert_extra_comps',
'TD_PERF_SEL_nofilter_pkr_full',
'TD_PERF_SEL_nofilter_pkr_full_due_to_arb',
'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt',
'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt',
'TD_PERF_SEL_nofilter_sclk_en',
'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off',
'TD_PERF_SEL_nofilter_total_num_comps_to_lds', 'TD_PERF_SEL_none',
'TD_PERF_SEL_one_comp_return_instr',
'TD_PERF_SEL_opaque_black_border',
'TD_PERF_SEL_out_of_order_instr',
'TD_PERF_SEL_preempting_nofilter_max_cnt',
'TD_PERF_SEL_prt_ack_instr', 'TD_PERF_SEL_ps_load_instr',
'TD_PERF_SEL_reference_data_rams_read',
'TD_PERF_SEL_resmap_2x_instr', 'TD_PERF_SEL_resmap_instr',
'TD_PERF_SEL_resmap_with_aniso_filtering',
'TD_PERF_SEL_resmap_with_cubemap_corner',
'TD_PERF_SEL_resmap_with_no_more_filtering',
'TD_PERF_SEL_resmap_with_volume_filtering',
'TD_PERF_SEL_sample_2x_instr', 'TD_PERF_SEL_sample_c_instr',
'TD_PERF_SEL_sample_instr', 'TD_PERF_SEL_sampler_accum_sclk_en',
'TD_PERF_SEL_sampler_bilerp_sclk_en',
'TD_PERF_SEL_sampler_bypass_sclk_en',
'TD_PERF_SEL_sampler_core_sclk_en',
'TD_PERF_SEL_sampler_format_flt_sclk_en',
'TD_PERF_SEL_sampler_format_fxdpt_sclk_en',
'TD_PERF_SEL_sampler_lerp0_active',
'TD_PERF_SEL_sampler_lerp1_active',
'TD_PERF_SEL_sampler_lerp2_active',
'TD_PERF_SEL_sampler_lerp3_active',
'TD_PERF_SEL_sampler_lerp4_active',
'TD_PERF_SEL_sampler_lerp5_active',
'TD_PERF_SEL_sampler_lerp6_active',
'TD_PERF_SEL_sampler_lerp7_active',
'TD_PERF_SEL_sampler_lerp_busy',
'TD_PERF_SEL_sampler_minmax_sclk_en',
'TD_PERF_SEL_sampler_out_busy', 'TD_PERF_SEL_sampler_out_sclk_en',
'TD_PERF_SEL_sampler_pkr_full',
'TD_PERF_SEL_sampler_pkr_full_due_to_arb',
'TD_PERF_SEL_sampler_preformatter_sclk_en',
'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off',
'TD_PERF_SEL_status_packet', 'TD_PERF_SEL_store_preempts_a_load',
'TD_PERF_SEL_ta_data_stall',
'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles',
'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles',
'TD_PERF_SEL_tc_data_stall', 'TD_PERF_SEL_tc_ram_stall',
'TD_PERF_SEL_tc_td_data_fifo_full',
'TD_PERF_SEL_tc_td_ram_fifo_full',
'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', 'TD_PERF_SEL_td_busy',
'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles',
'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles',
'TD_PERF_SEL_three_comp_return_instr',
'TD_PERF_SEL_total_num_instr',
'TD_PERF_SEL_total_num_instr_with_perf_wdw',
'TD_PERF_SEL_total_num_nofilter_instr',
'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw',
'TD_PERF_SEL_total_num_sampler_instr',
'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw',
'TD_PERF_SEL_tri_proc_node_override_slot0',
'TD_PERF_SEL_tri_proc_node_override_slot1',
'TD_PERF_SEL_tri_run_ahs_slot0', 'TD_PERF_SEL_tri_run_ahs_slot1',
'TD_PERF_SEL_tri_run_intersect_ahs_slot0',
'TD_PERF_SEL_tri_run_intersect_ahs_slot1',
'TD_PERF_SEL_triangle_back_facing_culled',
'TD_PERF_SEL_triangle_front_facing_culled',
'TD_PERF_SEL_triangle_non_opaque_culled',
'TD_PERF_SEL_triangle_opaque_culled',
'TD_PERF_SEL_two_comp_return_instr',
'TD_PERF_SEL_user_defined_border',
'TD_PERF_SEL_weight_data_rams_read', 'TD_PERF_SEL_white_border',
'TD_PERF_SEL_write_ack_instr', 'TESS_ISOLINE', 'TESS_QUAD',
'TESS_TRIANGLE', 'TEST_CLK_DIV_SEL', 'TEST_CLK_SEL',
'TEST_CLK_SEL_0', 'TEST_CLK_SEL_1', 'TEST_CLK_SEL_2',
'TEST_CLK_SEL_3', 'TEST_CLK_SEL_4', 'TEST_CLK_SEL_5',
'TEST_CLK_SEL_6', 'TEST_CLK_SEL_7',
'TEST_CLOCK_MUX_SELECT_DISPCLK_G',
'TEST_CLOCK_MUX_SELECT_DISPCLK_P',
'TEST_CLOCK_MUX_SELECT_DISPCLK_R',
'TEST_CLOCK_MUX_SELECT_DSCCLK_D',
'TEST_CLOCK_MUX_SELECT_DSCCLK_G',
'TEST_CLOCK_MUX_SELECT_DSCCLK_P',
'TEST_CLOCK_MUX_SELECT_DSCCLK_R', 'TEST_CLOCK_MUX_SELECT_ENUM',
'TEX_BC_SWIZZLE', 'TEX_BC_Swizzle_WXYZ', 'TEX_BC_Swizzle_WZYX',
'TEX_BC_Swizzle_XWYZ', 'TEX_BC_Swizzle_XYZW',
'TEX_BC_Swizzle_YXWZ', 'TEX_BC_Swizzle_ZYXW',
'TEX_BORDER_COLOR_TYPE', 'TEX_BorderColor_OpaqueBlack',
'TEX_BorderColor_OpaqueWhite', 'TEX_BorderColor_Register',
'TEX_BorderColor_TransparentBlack', 'TEX_CHROMA_KEY', 'TEX_CLAMP',
'TEX_COORD_TYPE', 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled',
'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3',
'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder',
'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror',
'TEX_Clamp_MirrorOnceHalfToBorder',
'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast',
'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized',
'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION',
'TEX_DepthCompareFunction_Always',
'TEX_DepthCompareFunction_Equal',
'TEX_DepthCompareFunction_Greater',
'TEX_DepthCompareFunction_GreaterEqual',
'TEX_DepthCompareFunction_Less',
'TEX_DepthCompareFunction_LessEqual',
'TEX_DepthCompareFunction_Never',
'TEX_DepthCompareFunction_NotEqual', 'TEX_FORMAT_COMP',
'TEX_FormatComp_RESERVED_3', 'TEX_FormatComp_Signed',
'TEX_FormatComp_Unsigned', 'TEX_FormatComp_UnsignedBiased',
'TEX_MAX_ANISO_RATIO', 'TEX_MIP_FILTER',
'TEX_MaxAnisoRatio_16to1', 'TEX_MaxAnisoRatio_1to1',
'TEX_MaxAnisoRatio_2to1', 'TEX_MaxAnisoRatio_4to1',
'TEX_MaxAnisoRatio_8to1', 'TEX_MaxAnisoRatio_RESERVED_5',
'TEX_MaxAnisoRatio_RESERVED_6', 'TEX_MaxAnisoRatio_RESERVED_7',
'TEX_MipFilter_Linear', 'TEX_MipFilter_None',
'TEX_MipFilter_Point', 'TEX_MipFilter_Point_Aniso_Adj',
'TEX_REQUEST_SIZE', 'TEX_RequestSize_128B',
'TEX_RequestSize_2X64B', 'TEX_RequestSize_32B',
'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE',
'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid',
'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint',
'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER',
'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point',
'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER',
'THREAD_TRACE_DRAW', 'THREAD_TRACE_FINISH', 'THREAD_TRACE_MARKER',
'THREAD_TRACE_START', 'THREAD_TRACE_STOP', 'TMDS_COLOR_FORMAT',
'TMDS_COLOR_FORMAT_DUAL30BPP', 'TMDS_COLOR_FORMAT_RESERVED',
'TMDS_COLOR_FORMAT_TWIN30BPP_LSB',
'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP',
'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN',
'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0',
'TMDS_CTL0_DATA_MODULATION_BIT1',
'TMDS_CTL0_DATA_MODULATION_BIT2',
'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL',
'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED',
'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC',
'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC',
'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED',
'TMDS_CTL0_DATA_SEL8_RANDOM_DATA',
'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA',
'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN',
'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT',
'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION',
'TMDS_CTL1_DATA_MODULATION_BIT0',
'TMDS_CTL1_DATA_MODULATION_BIT1',
'TMDS_CTL1_DATA_MODULATION_BIT2',
'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL',
'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED',
'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC',
'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC',
'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED',
'TMDS_CTL1_DATA_SEL8_BLANK_TIME',
'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED',
'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN',
'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT',
'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION',
'TMDS_CTL2_DATA_MODULATION_BIT0',
'TMDS_CTL2_DATA_MODULATION_BIT1',
'TMDS_CTL2_DATA_MODULATION_BIT2',
'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL',
'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED',
'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC',
'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC',
'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED',
'TMDS_CTL2_DATA_SEL8_BLANK_TIME',
'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED',
'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN',
'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT',
'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION',
'TMDS_CTL3_DATA_MODULATION_BIT0',
'TMDS_CTL3_DATA_MODULATION_BIT1',
'TMDS_CTL3_DATA_MODULATION_BIT2',
'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL',
'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED',
'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC',
'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC',
'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED',
'TMDS_CTL3_DATA_SEL8_BLANK_TIME',
'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED',
'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN',
'TMDS_CTL3_PATTERN_OUT_ENABLE',
'TMDS_DATA_SYNCHRONIZATION_DSINTSEL',
'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS',
'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', 'TMDS_DVI_MODE',
'TMDS_HDMI_MODE', 'TMDS_MUX_SELECT', 'TMDS_MUX_SELECT_B',
'TMDS_MUX_SELECT_G', 'TMDS_MUX_SELECT_R',
'TMDS_MUX_SELECT_RESERVED', 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START',
'TMDS_PIXEL_ENCODING', 'TMDS_PIXEL_ENCODING_422',
'TMDS_PIXEL_ENCODING_444_OR_420', 'TMDS_REG_TEST_OUTPUTA_CNTLA',
'TMDS_REG_TEST_OUTPUTA_CNTLA_NA',
'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0',
'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1',
'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2',
'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA',
'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0',
'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1',
'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0',
'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2',
'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG',
'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START',
'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT',
'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT',
'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT',
'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT',
'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA',
'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB',
'TMDS_TRANSMITTER_CONTROL_IDSCKSELA',
'TMDS_TRANSMITTER_CONTROL_IDSCKSELB',
'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN',
'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK',
'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN',
'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK',
'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS',
'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS',
'TMDS_TRANSMITTER_ENABLE_HPD_MASK',
'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK',
'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK',
'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE',
'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE',
'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE',
'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE',
'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON',
'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON',
'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK',
'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK',
'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK',
'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK',
'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE',
'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE',
'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE',
'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE',
'TMDS_TRANSMITTER_PLLSEL_BY_HW',
'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW',
'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD',
'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE',
'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE',
'TMDS_TRANSMITTER_PLL_RST_ON_HPD',
'TMDS_TRANSMITTER_TDCLK_FROM_PADS',
'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK',
'TMDS_TRANSMITTER_TMCLK_FROM_PADS',
'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', 'TRANSERR',
'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES',
'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES',
'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES',
'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS',
'TRISTRIP', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource',
'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource',
'TVX_Type_ValidVertexBuffer', 'UCONFIG_SPACE_END',
'UCONFIG_SPACE_START', 'UNDEF', 'UNSIGNED', 'UTCL0FaultType',
'UTCL0RequestType', 'UTCL0_TYPE_BYPASS', 'UTCL0_TYPE_NORMAL',
'UTCL0_TYPE_SHOOTDOWN', 'UTCL0_XNACK_NO_RETRY', 'UTCL0_XNACK_PRT',
'UTCL0_XNACK_RETRY', 'UTCL0_XNACK_SUCCESS', 'UTCL1FaultType',
'UTCL1PerfSel', 'UTCL1RequestType',
'UTCL1_PERF_SEL_ALOG_CACHE_HIT', 'UTCL1_PERF_SEL_ALOG_CACHE_REQ',
'UTCL1_PERF_SEL_ALOG_INTERRUPT',
'UTCL1_PERF_SEL_ALOG_INTERRUPT_DROPPED',
'UTCL1_PERF_SEL_ALOG_STALL_PMM_CREDITS',
'UTCL1_PERF_SEL_AVG_INV_LATENCY', 'UTCL1_PERF_SEL_BYPASS_REQS',
'UTCL1_PERF_SEL_CP_INVREQS', 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC0',
'UTCL1_PERF_SEL_EVICTIONS_NUM_CC1',
'UTCL1_PERF_SEL_EVICTIONS_NUM_CC2',
'UTCL1_PERF_SEL_EVICTIONS_NUM_CC3', 'UTCL1_PERF_SEL_HITS',
'UTCL1_PERF_SEL_HITS_PG_SIZE_1', 'UTCL1_PERF_SEL_HITS_PG_SIZE_2',
'UTCL1_PERF_SEL_HITS_PG_SIZE_3', 'UTCL1_PERF_SEL_HITS_PG_SIZE_4',
'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS',
'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS',
'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT',
'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', 'UTCL1_PERF_SEL_MISSES',
'UTCL1_PERF_SEL_NONE',
'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC0',
'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC1',
'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC2',
'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC3',
'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC0',
'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC1',
'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC2',
'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC3',
'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_16M_32M',
'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_1M_2M',
'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_256K_512K',
'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_2M_4M',
'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_32M_INF',
'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4K_64K',
'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4M_8M',
'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_512K_1M',
'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_64K_256K',
'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_8M_16M',
'UTCL1_PERF_SEL_RANGE_INVREQS', 'UTCL1_PERF_SEL_REQS',
'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_0',
'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_1',
'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_2',
'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_3',
'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_0',
'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_1',
'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_2',
'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_3', 'UTCL1_PERF_SEL_RTNS',
'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_0',
'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_1',
'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_2',
'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_3',
'UTCL1_PERF_SEL_STALL_MH_FULL',
'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS',
'UTCL1_PERF_SEL_UTCL0_UTCL1_INVACKS',
'UTCL1_PERF_SEL_UTCL1_UTCL2_INVACKS', 'UTCL1_PERF_SEL_UTCL2_REQS',
'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM',
'UTCL1_PERF_SEL_UTCL2_REQ_SQUASHED_NUM',
'UTCL1_PERF_SEL_UTCL2_RET_CNT', 'UTCL1_PERF_SEL_UTCL2_RET_FAULT',
'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT',
'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT',
'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY',
'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS',
'UTCL1_PERF_SEL_XLAT_REQ_BUSY', 'UTCL1_TYPE_BYPASS',
'UTCL1_TYPE_NORMAL', 'UTCL1_TYPE_SHOOTDOWN',
'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', 'UTCL1_XNACK_RETRY',
'UTCL1_XNACK_SUCCESS', 'VGT_DETECT_ONE', 'VGT_DETECT_ZERO',
'VGT_DIST_MODE', 'VGT_DI_INDEX_SIZE', 'VGT_DI_PRIM_TYPE',
'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', 'VGT_DMA_BUF_RING',
'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', 'VGT_DMA_PTR_UPDATE',
'VGT_DMA_SWAP_16_BIT', 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE',
'VGT_DMA_SWAP_NONE', 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE',
'VGT_FLUSH', 'VGT_GROUP_CONV_SEL', 'VGT_GRP_AUTO_PRIM',
'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32',
'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_SINT_16',
'VGT_GRP_SINT_32', 'VGT_GRP_UINT_16', 'VGT_GRP_UINT_32',
'VGT_GS_MODE_TYPE', 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16',
'VGT_INDEX_32', 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE',
'VGT_OUTPATH_GS_BLOCK', 'VGT_OUTPATH_HS_BLOCK',
'VGT_OUTPATH_PRIM_GEN', 'VGT_OUTPATH_SELECT',
'VGT_OUTPATH_TE_GS_BLOCK', 'VGT_OUTPATH_TE_OUTPUT',
'VGT_OUTPATH_TE_PRIM_GEN', 'VGT_OUTPATH_VTX_REUSE',
'VGT_OUT_2D_RECT', 'VGT_OUT_DUMMY_1', 'VGT_OUT_DUMMY_2',
'VGT_OUT_DUMMY_3', 'VGT_OUT_LINE', 'VGT_OUT_LINE_ADJ',
'VGT_OUT_PATCH', 'VGT_OUT_POINT', 'VGT_OUT_PRIM_TYPE',
'VGT_OUT_RECT_V0', 'VGT_OUT_TRI', 'VGT_OUT_TRI_ADJ',
'VGT_POLICY_BYPASS', 'VGT_POLICY_LRU', 'VGT_POLICY_STREAM',
'VGT_RDREQ_POLICY', 'VGT_SPEC_DATA_READ',
'VGT_SPEC_DATA_READ_AUTO', 'VGT_SPEC_DATA_READ_FORCE_OFF',
'VGT_SPEC_DATA_READ_FORCE_ON', 'VGT_STAGES_GS_EN',
'VGT_STAGES_HS_EN', 'VGT_STREAMOUT_RESET', 'VGT_STREAMOUT_SYNC',
'VGT_TEMPORAL', 'VGT_TEMPORAL_DISCARD',
'VGT_TEMPORAL_HIGH_PRIORITY', 'VGT_TEMPORAL_NORMAL',
'VGT_TEMPORAL_STREAM', 'VGT_TESS_PARTITION', 'VGT_TESS_TOPOLOGY',
'VGT_TESS_TYPE', 'VID_ENHANCED_MODE', 'VID_NORMAL_FRAME_MODE',
'VID_STREAM_DISABLE_MASKED', 'VID_STREAM_DISABLE_UNMASK',
'VMID_SZ', 'VMPG_SIZE', 'VMPG_SIZE_4KB', 'VMPG_SIZE_64KB',
'VM_GROUP_SIZE', 'VM_GROUP_SIZE_1024B', 'VM_GROUP_SIZE_128B',
'VM_GROUP_SIZE_2048B', 'VM_GROUP_SIZE_256B', 'VM_GROUP_SIZE_512B',
'VM_GROUP_SIZE_64B', 'VM_PG_SIZE_128KB', 'VM_PG_SIZE_128MB',
'VM_PG_SIZE_16KB', 'VM_PG_SIZE_16MB', 'VM_PG_SIZE_1MB',
'VM_PG_SIZE_256KB', 'VM_PG_SIZE_2MB', 'VM_PG_SIZE_32KB',
'VM_PG_SIZE_32MB', 'VM_PG_SIZE_4KB', 'VM_PG_SIZE_4MB',
'VM_PG_SIZE_512KB', 'VM_PG_SIZE_64KB', 'VM_PG_SIZE_64MB',
'VM_PG_SIZE_8KB', 'VM_PG_SIZE_8MB',
'VPG_MEM_DISABLE_MEM_PWR_CTRL', 'VPG_MEM_ENABLE_MEM_PWR_CTRL',
'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', 'VPG_MEM_NO_FORCE_REQ',
'VPG_MEM_PWR_DIS_CTRL', 'VPG_MEM_PWR_FORCE_CTRL',
'VREADY_AT_OR_AFTER_VSYNC', 'VREADY_BEFORE_VSYNC',
'VRSCombinerModeSC', 'VRS_SHADING_RATE_16X_SSAA',
'VRS_SHADING_RATE_1X1', 'VRS_SHADING_RATE_1X2',
'VRS_SHADING_RATE_2X1', 'VRS_SHADING_RATE_2X2',
'VRS_SHADING_RATE_2X4', 'VRS_SHADING_RATE_2X_SSAA',
'VRS_SHADING_RATE_4X2', 'VRS_SHADING_RATE_4X4',
'VRS_SHADING_RATE_4X_SSAA', 'VRS_SHADING_RATE_8X_SSAA',
'VRS_SHADING_RATE_UNDEFINED0', 'VRS_SHADING_RATE_UNDEFINED1',
'VRS_SHADING_RATE_UNDEFINED2', 'VRS_SHADING_RATE_UNDEFINED3',
'VRS_SHADING_RATE_UNDEFINED4', 'VRSrate', 'VSYNC_CNT_LATCH_MASK',
'VSYNC_CNT_LATCH_MASK_0', 'VSYNC_CNT_LATCH_MASK_1',
'VSYNC_CNT_RESET_SEL', 'VSYNC_CNT_RESET_SEL_0',
'VSYNC_CNT_RESET_SEL_1', 'VS_PARTIAL_FLUSH', 'VTG_SEL_0',
'VTG_SEL_1', 'VTG_SEL_2', 'VTG_SEL_3', 'VTG_SEL_4', 'VTG_SEL_5',
'WAIT_SYNC', 'WATERMARK_MODE', 'WD_IA_DRAW_REG_XFER',
'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC',
'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE',
'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM',
'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1',
'WD_IA_DRAW_REG_XFER_GE_CNTL',
'WD_IA_DRAW_REG_XFER_GE_GS_THROTTLE',
'WD_IA_DRAW_REG_XFER_GE_PC_ALLOC',
'WD_IA_DRAW_REG_XFER_GE_STEREO_CNTL',
'WD_IA_DRAW_REG_XFER_GE_USER_VGPR1',
'WD_IA_DRAW_REG_XFER_GE_USER_VGPR2',
'WD_IA_DRAW_REG_XFER_GE_USER_VGPR3',
'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN',
'WD_IA_DRAW_REG_XFER_GE_VRS_RATE',
'WD_IA_DRAW_REG_XFER_GFX_PIPE_CONTROL',
'WD_IA_DRAW_REG_XFER_SPI_SHADER_GS_OUT_CONFIG_PS',
'WD_IA_DRAW_REG_XFER_VGT_DRAW_PAYLOAD_CNTL',
'WD_IA_DRAW_REG_XFER_VGT_GS_OUT_PRIM_TYPE',
'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID',
'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN',
'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_EN',
'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_RESET',
'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVE_TYPE', 'WD_IA_DRAW_SOURCE',
'WD_IA_DRAW_SOURCE_AUTO', 'WD_IA_DRAW_SOURCE_DMA',
'WD_IA_DRAW_SOURCE_IMMD', 'WD_IA_DRAW_SOURCE_OPAQ',
'WD_IA_DRAW_TYPE', 'WD_IA_DRAW_TYPE_DI_MM0',
'WD_IA_DRAW_TYPE_EVENT_ADDR', 'WD_IA_DRAW_TYPE_EVENT_INIT',
'WD_IA_DRAW_TYPE_IMM_DATA', 'WD_IA_DRAW_TYPE_INDX_OFF',
'WD_IA_DRAW_TYPE_MAX_INDX', 'WD_IA_DRAW_TYPE_MIN_INDX',
'WD_IA_DRAW_TYPE_REG_XFER', 'WRITE_BASE_ONLY', 'WRITE_BOTH',
'WRITE_COMPRESSION_MODE', 'WritePolicy', 'XNORM', 'XNORM_A',
'XNORM_B', 'XTAL_REF_CLOCK_SOURCE_SEL',
'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK',
'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL',
'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'Y10_CbCr1010_420_PLANAR',
'Y10_CrCb1010_420_PLANAR', 'Y12_CbCr1212_420_PLANAR',
'Y12_CrCb1212_420_PLANAR', 'Y8_CbCr88_420_PLANAR',
'Y8_CrCb88_420_PLANAR', 'YCbYCr10101010_422_PACKED',
'YCbYCr12121212_422_PACKED', 'YCbYCr8888_422_PACKED',
'YCrCbA16161616_10LSB', 'YCrCbA16161616_10MSB',
'YCrCbA16161616_12LSB', 'YCrCbA16161616_12MSB', 'YCrCbA8888',
'YCrYCb10101010_422_PACKED', 'YCrYCb12121212_422_PACKED',
'YCrYCb8888_422_PACKED', 'Y_G_DATA_ONTO_ALPHA_PORT',
'Y_G_DATA_ONTO_CB_B_PORT', 'Y_G_DATA_ONTO_CR_R_PORT',
'Y_G_DATA_ONTO_Y_G_PORT', 'ZLimitSumm', 'ZModeForce', 'ZOrder',
'ZSamplePosition', 'Z_SAMPLE_CENTER', 'Z_SAMPLE_CENTROID',
'_soc24_ENUM_HEADER', 'ge1_assembler_busy',
'ge1_assembler_dma_starved', 'ge1_assembler_stalled',
'ge1_dma_busy', 'ge1_dma_lat_bin_0', 'ge1_dma_lat_bin_1',
'ge1_dma_lat_bin_2', 'ge1_dma_lat_bin_3', 'ge1_dma_lat_bin_4',
'ge1_dma_lat_bin_5', 'ge1_dma_lat_bin_6', 'ge1_dma_lat_bin_7',
'ge1_dma_return_cl0', 'ge1_dma_return_cl1',
'ge1_dma_return_size_cl0', 'ge1_dma_return_size_cl1',
'ge1_dma_utcl1_consecutive_retry_event',
'ge1_dma_utcl1_request_event', 'ge1_dma_utcl1_retry_event',
'ge1_dma_utcl1_stall_event', 'ge1_dma_utcl1_stall_utcl2_event',
'ge1_dma_utcl1_translation_hit_event',
'ge1_dma_utcl1_translation_miss_event', 'ge1_pipe0_to_pipe1',
'ge1_pipe1_to_pipe0', 'ge1_prim_group_limit_hit',
'ge1_rbiu_di_fifo_stalled_p0', 'ge1_rbiu_di_fifo_stalled_p1',
'ge1_rbiu_di_fifo_starved_p0', 'ge1_rbiu_di_fifo_starved_p1',
'ge1_rbiu_dr_fifo_stalled_p0', 'ge1_rbiu_dr_fifo_stalled_p1',
'ge1_rbiu_dr_fifo_starved_p0', 'ge1_rbiu_dr_fifo_starved_p1',
'ge1_sclk_input_vld', 'ge1_sclk_reg_vld',
'ge1_small_draws_one_instance', 'ge1_stat_busy',
'ge1_stat_no_dma_busy', 'ge1_unopt_multi_instance_draws',
'ge_agm_gcr_combine', 'ge_agm_gcr_crd_stall',
'ge_agm_gcr_latency', 'ge_agm_gcr_req', 'ge_agm_gcr_req_amount',
'ge_agm_gcr_req_outstanding', 'ge_agm_gcr_stall',
'ge_agm_gcr_tag_stall', 'ge_all_tf2', 'ge_all_tf3', 'ge_all_tf4',
'ge_all_tf5', 'ge_all_tf6', 'ge_all_tf_eq', 'ge_csb_spi_bp',
'ge_dist_distributer_busy', 'ge_dist_hs_done',
'ge_dist_hs_done_latency', 'ge_dist_hs_done_latency_se0',
'ge_dist_hs_done_latency_se1', 'ge_dist_hs_done_latency_se2',
'ge_dist_hs_done_latency_se3', 'ge_dist_hs_done_latency_se4',
'ge_dist_hs_done_latency_se5', 'ge_dist_hs_done_latency_se6',
'ge_dist_hs_done_latency_se7', 'ge_dist_hs_done_se0',
'ge_dist_hs_done_se1', 'ge_dist_hs_done_se2',
'ge_dist_hs_done_se3', 'ge_dist_hs_done_se4',
'ge_dist_hs_done_se5', 'ge_dist_hs_done_se6',
'ge_dist_hs_done_se7', 'ge_dist_indx_fifos_full_and_empty',
'ge_dist_inside_tf_bin_0', 'ge_dist_inside_tf_bin_1',
'ge_dist_inside_tf_bin_2', 'ge_dist_inside_tf_bin_3',
'ge_dist_inside_tf_bin_4', 'ge_dist_inside_tf_bin_5',
'ge_dist_inside_tf_bin_6', 'ge_dist_inside_tf_bin_7',
'ge_dist_inside_tf_bin_8', 'ge_dist_null_patch',
'ge_dist_op_fifo_full_starve', 'ge_dist_pc_feorder_fifo_full',
'ge_dist_pc_ge_manager_busy', 'ge_dist_sclk_core_vld',
'ge_dist_sclk_input_vld', 'ge_dist_sclk_wd_te11_vld',
'ge_dist_switch_mode_stall', 'ge_dist_te11_starved',
'ge_dist_tfreq_lat_bin_0', 'ge_dist_tfreq_lat_bin_1',
'ge_dist_tfreq_lat_bin_2', 'ge_dist_tfreq_lat_bin_3',
'ge_dist_tfreq_lat_bin_4', 'ge_dist_tfreq_lat_bin_5',
'ge_dist_tfreq_lat_bin_6', 'ge_dist_tfreq_lat_bin_7',
'ge_dist_tfreq_utcl1_consecutive_retry_event',
'ge_dist_tfreq_utcl1_request_event',
'ge_dist_tfreq_utcl1_retry_event',
'ge_dist_tfreq_utcl1_stall_event',
'ge_dist_tfreq_utcl1_stall_utcl2_event',
'ge_dist_tfreq_utcl1_translation_hit_event',
'ge_dist_tfreq_utcl1_translation_miss_event',
'ge_dist_wd_te11_busy', 'ge_distclk_vld', 'ge_esvert_send',
'ge_gs_issue_rtr_stalled', 'ge_gsprim_send',
'ge_gsprim_stalled_esvert', 'ge_gsthread_stalled',
'ge_hs_done_all_tf0_se0', 'ge_hs_done_all_tf0_se1',
'ge_hs_done_all_tf0_se2', 'ge_hs_done_all_tf0_se3',
'ge_hs_done_all_tf0_se4', 'ge_hs_done_all_tf0_se5',
'ge_hs_done_all_tf0_se6', 'ge_hs_done_all_tf0_se7',
'ge_hs_done_all_tf1_se0', 'ge_hs_done_all_tf1_se1',
'ge_hs_done_all_tf1_se2', 'ge_hs_done_all_tf1_se3',
'ge_hs_done_all_tf1_se4', 'ge_hs_done_all_tf1_se5',
'ge_hs_done_all_tf1_se6', 'ge_hs_done_all_tf1_se7',
'ge_hs_stall_tfmm_fifo_full', 'ge_hs_tif_stall',
'ge_merge_gsgrp_rdy_pending_verts',
'ge_merge_hsgrp_rdy_pending_verts', 'ge_merge_hsgs_fifo_blocked',
'ge_merge_hsgs_grp_switch', 'ge_merge_hsgs_vert_switch',
'ge_merge_lses_fifo_blocked', 'ge_merge_lses_vert_switch',
'ge_merged_hsgs_grp_stalled', 'ge_merged_hsgs_vert_stalled',
'ge_merged_lses_vert_stalled', 'ge_ngg_agm_req_stall',
'ge_ngg_attr_discard_alloc', 'ge_ngg_attr_grp_alloc',
'ge_ngg_attr_grp_latency', 'ge_ngg_attr_grp_wasted',
'ge_ngg_attr_null_dealloc', 'ge_ngg_busy_base',
'ge_ngg_indx_bus_stall', 'ge_ngg_ord_id_req_stall',
'ge_ngg_pc_space_not_avail', 'ge_ngg_reuse_prim_limit_hit',
'ge_ngg_reuse_vert_limit_hit', 'ge_ngg_spi_esvert_partial_eov',
'ge_ngg_spi_gsprim_partial_eov', 'ge_ngg_stall_tess_off_tess_on',
'ge_ngg_stall_tess_on_tess_off', 'ge_ngg_starved_after_work',
'ge_ngg_starved_idle', 'ge_ngg_starving_for_wave_id',
'ge_ngg_subgrp_fifo_stall', 'ge_num_of_donut_dist_patches',
'ge_num_of_hs_dealloc_events', 'ge_num_of_no_dist_patches',
'ge_num_of_patch_dist_patches',
'ge_num_of_se_switches_due_to_donut',
'ge_num_of_se_switches_due_to_patch_accum',
'ge_num_of_se_switches_due_to_trap', 'ge_pa0_csb_eop',
'ge_se0_te11_starved_on_hs_done',
'ge_se1_te11_starved_on_hs_done',
'ge_se2_te11_starved_on_hs_done',
'ge_se3_te11_starved_on_hs_done',
'ge_se4_te11_starved_on_hs_done',
'ge_se5_te11_starved_on_hs_done',
'ge_se6_te11_starved_on_hs_done',
'ge_se7_te11_starved_on_hs_done', 'ge_se_api_ds_verts',
'ge_se_api_vs_verts', 'ge_se_combined_busy',
'ge_se_ds_cache_hits', 'ge_se_ds_prims', 'ge_se_es_thread_groups',
'ge_se_esvert_stalled_gsprim', 'ge_se_hs_input_stall',
'ge_se_hs_tfm_stall', 'ge_se_hs_tgs_active_high_water_mark',
'ge_se_hs_thread_groups', 'ge_se_reused_es_indices',
'ge_se_sclk_input_vld', 'ge_se_sclk_ngg_vld',
'ge_se_sclk_te11_vld', 'ge_se_sending_vert_or_prim',
'ge_se_spi_esvert_eov', 'ge_se_spi_esvert_stalled',
'ge_se_spi_esvert_starved_busy', 'ge_se_spi_esvert_valid',
'ge_se_spi_gsprim_cont', 'ge_se_spi_gsprim_eov',
'ge_se_spi_gsprim_stalled', 'ge_se_spi_gsprim_starved_busy',
'ge_se_spi_gsprim_valid',
'ge_se_spi_gssubgrp_event_window_active',
'ge_se_spi_gssubgrp_is_event', 'ge_se_spi_gssubgrp_send',
'ge_se_spi_hsgrp_is_event', 'ge_se_spi_hsgrp_send',
'ge_se_spi_hsvert_eov', 'ge_se_spi_hsvert_fifo_full_stall',
'ge_se_spi_hsvert_stalled', 'ge_se_spi_hsvert_starved_busy',
'ge_se_spi_hsvert_valid', 'ge_se_spi_lsvert_eov',
'ge_se_spi_lsvert_stalled', 'ge_se_spi_lsvert_starved_busy',
'ge_se_spi_lsvert_valid', 'ge_se_spi_tgrp_fifo_stall',
'ge_spi_gsgrp_valid', 'ge_spi_gssubgrp_stalled',
'ge_spi_hsgrp_spi_stall', 'ge_spi_hsvert_send',
'ge_spi_hswave_fifo_full_stall', 'ge_spi_lsvert_send',
'ge_spi_lswave_fifo_full_stall', 'ge_te11_compactor_starved',
'ge_te11_con_stall', 'ge_tf_ret_data_stalling_hs_done']