sadmen
/
openpilot_comma
mirror of https://github.com/commaai/openpilot.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
openpilot is an open source driver assistance system. openpilot performs the functions of Automated Lane Centering and Adaptive Cruise Control for over 200 supported car makes and models.
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
6 Commits
45 Branches
82 Tags
6.9 GiB
 
 
 
 
 
 
Tag: Branch: Tree: 3fa0e0e707
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '3fa0e0e707'
${ noResults }
openpilot_comma/tinygrad_repo/tinygrad/runtime/autogen/amd_gpu.py

89131 lines
3.8 MiB
Raw Blame History

# mypy: ignore-errors
# -*- coding: utf-8 -*-
#
# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++']
# WORD_SIZE is: 8
# POINTER_SIZE is: 8
# LONGDOUBLE_SIZE is: 16
#
import ctypes, os
class AsDictMixin:
@classmethod
def as_dict(cls, self):
result = {}
if not isinstance(self, AsDictMixin):
# not a structure, assume it's already a python object
return self
if not hasattr(cls, "_fields_"):
return result
# sys.version_info >= (3, 5)
# for (field, *_) in cls._fields_: # noqa
for field_tuple in cls._fields_: # noqa
field = field_tuple[0]
if field.startswith('PADDING_'):
continue
value = getattr(self, field)
type_ = type(value)
if hasattr(value, "_length_") and hasattr(value, "_type_"):
# array
if not hasattr(type_, "as_dict"):
value = [v for v in value]
else:
type_ = type_._type_
value = [type_.as_dict(v) for v in value]
elif hasattr(value, "contents") and hasattr(value, "_type_"):
# pointer
try:
if not hasattr(type_, "as_dict"):
value = value.contents
else:
type_ = type_._type_
value = type_.as_dict(value.contents)
except ValueError:
# nullptr
value = None
elif isinstance(value, AsDictMixin):
# other structure
value = type_.as_dict(value)
result[field] = value
return result
class Structure(ctypes.Structure, AsDictMixin):
def __init__(self, *args, **kwds):
# We don't want to use positional arguments fill PADDING_* fields
args = dict(zip(self.__class__._field_names_(), args))
args.update(kwds)
super(Structure, self).__init__(**args)
@classmethod
def _field_names_(cls):
if hasattr(cls, '_fields_'):
return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING'))
else:
return ()
@classmethod
def get_type(cls, field):
for f in cls._fields_:
if f[0] == field:
return f[1]
return None
@classmethod
def bind(cls, bound_fields):
fields = {}
for name, type_ in cls._fields_:
if hasattr(type_, "restype"):
if name in bound_fields:
if bound_fields[name] is None:
fields[name] = type_()
else:
# use a closure to capture the callback from the loop scope
fields[name] = (
type_((lambda callback: lambda *args: callback(*args))(
bound_fields[name]))
)
del bound_fields[name]
else:
# default callback implementation (does nothing)
try:
default_ = type_(0).restype().value
except TypeError:
default_ = None
fields[name] = type_((
lambda default_: lambda *args: default_)(default_))
else:
# not a callback function, use default initialization
if name in bound_fields:
fields[name] = bound_fields[name]
del bound_fields[name]
else:
fields[name] = type_()
if len(bound_fields) != 0:
raise ValueError(
"Cannot bind the following unknown callback(s) {}.{}".format(
cls.__name__, bound_fields.keys()
))
return cls(**fields)
class Union(ctypes.Union, AsDictMixin):
pass
HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro
SDMA_OP_COPY = 1 # macro
SDMA_OP_FENCE = 5 # macro
SDMA_OP_TRAP = 6 # macro
SDMA_OP_POLL_REGMEM = 8 # macro
SDMA_OP_ATOMIC = 10 # macro
SDMA_OP_CONST_FILL = 11 # macro
SDMA_OP_TIMESTAMP = 13 # macro
SDMA_OP_GCR = 17 # Variable ctypes.c_uint32
SDMA_SUBOP_COPY_LINEAR = 0 # macro
SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32
SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # macro
SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32
SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32
class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure):
pass
class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [
('op', ctypes.c_uint32, 8),
('sub_op', ctypes.c_uint32, 8),
('extra_info', ctypes.c_uint32, 16),
]
union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0),
('DW_0_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [
('count', ctypes.c_uint32, 22),
('reserved_0', ctypes.c_uint32, 10),
]
union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0),
('DW_1_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [
('reserved_0', ctypes.c_uint32, 16),
('dst_swap', ctypes.c_uint32, 2),
('reserved_1', ctypes.c_uint32, 6),
('src_swap', ctypes.c_uint32, 2),
('reserved_2', ctypes.c_uint32, 6),
]
union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0),
('DW_2_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [
('src_addr_31_0', ctypes.c_uint32, 32),
]
union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0),
('DW_3_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [
('src_addr_63_32', ctypes.c_uint32, 32),
]
union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0),
('DW_4_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [
('dst_addr_31_0', ctypes.c_uint32, 32),
]
union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0),
('DW_5_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [
('dst_addr_63_32', ctypes.c_uint32, 32),
]
union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0),
('DW_6_DATA', ctypes.c_uint32),
]
struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [
('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION),
('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION),
('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION),
('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION),
('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION),
('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION),
('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION),
]
SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure):
pass
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [
('op', ctypes.c_uint32, 8),
('sub_op', ctypes.c_uint32, 8),
('reserved', ctypes.c_uint32, 13),
('element', ctypes.c_uint32, 3),
]
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0),
('DW_0_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [
('src_addr_31_0', ctypes.c_uint32, 32),
]
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0),
('DW_1_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [
('src_addr_63_32', ctypes.c_uint32, 32),
]
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0),
('DW_2_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [
('src_offset_x', ctypes.c_uint32, 14),
('reserved_1', ctypes.c_uint32, 2),
('src_offset_y', ctypes.c_uint32, 14),
('reserved_2', ctypes.c_uint32, 2),
]
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0),
('DW_3_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [
('src_offset_z', ctypes.c_uint32, 11),
('reserved_1', ctypes.c_uint32, 2),
('src_pitch', ctypes.c_uint32, 19),
]
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0),
('DW_4_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [
('src_slice_pitch', ctypes.c_uint32, 28),
('reserved_1', ctypes.c_uint32, 4),
]
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0),
('DW_5_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [
('dst_addr_31_0', ctypes.c_uint32, 32),
]
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0),
('DW_6_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [
('dst_addr_63_32', ctypes.c_uint32, 32),
]
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0),
('DW_7_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [
('dst_offset_x', ctypes.c_uint32, 14),
('reserved_1', ctypes.c_uint32, 2),
('dst_offset_y', ctypes.c_uint32, 14),
('reserved_2', ctypes.c_uint32, 2),
]
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0),
('DW_8_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [
('dst_offset_z', ctypes.c_uint32, 11),
('reserved_1', ctypes.c_uint32, 2),
('dst_pitch', ctypes.c_uint32, 19),
]
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0),
('DW_9_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [
('dst_slice_pitch', ctypes.c_uint32, 28),
('reserved_1', ctypes.c_uint32, 4),
]
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0),
('DW_10_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [
('rect_x', ctypes.c_uint32, 14),
('reserved_1', ctypes.c_uint32, 2),
('rect_y', ctypes.c_uint32, 14),
('reserved_2', ctypes.c_uint32, 2),
]
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0),
('DW_11_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union):
pass
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure):
pass
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [
('rect_z', ctypes.c_uint32, 11),
('reserved_1', ctypes.c_uint32, 5),
('dst_swap', ctypes.c_uint32, 2),
('reserved_2', ctypes.c_uint32, 6),
('src_swap', ctypes.c_uint32, 2),
('reserved_3', ctypes.c_uint32, 6),
]
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0),
('DW_12_DATA', ctypes.c_uint32),
]
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [
('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION),
('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION),
('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION),
('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION),
('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION),
('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION),
('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION),
('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION),
('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION),
('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION),
('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION),
('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION),
('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION),
]
SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG
class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure):
pass
class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union):
pass
class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure):
pass
struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False
struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [
('op', ctypes.c_uint32, 8),
('sub_op', ctypes.c_uint32, 8),
('sw', ctypes.c_uint32, 2),
('reserved_0', ctypes.c_uint32, 12),
('fillsize', ctypes.c_uint32, 2),
]
union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False
union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [
('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0),
('DW_0_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union):
pass
class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure):
pass
struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False
struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [
('dst_addr_31_0', ctypes.c_uint32, 32),
]
union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False
union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [
('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0),
('DW_1_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union):
pass
class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure):
pass
struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False
struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [
('dst_addr_63_32', ctypes.c_uint32, 32),
]
union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False
union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [
('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0),
('DW_2_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union):
pass
class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure):
pass
struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False
struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [
('src_data_31_0', ctypes.c_uint32, 32),
]
union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False
union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [
('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0),
('DW_3_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union):
pass
class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure):
pass
struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False
struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [
('count', ctypes.c_uint32, 22),
('reserved_0', ctypes.c_uint32, 10),
]
union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False
union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [
('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0),
('DW_4_DATA', ctypes.c_uint32),
]
struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False
struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [
('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION),
('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION),
('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION),
('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION),
('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION),
]
SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG
class struct_SDMA_PKT_FENCE_TAG(Structure):
pass
class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union):
pass
class struct_SDMA_PKT_FENCE_TAG_0_0(Structure):
pass
struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False
struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [
('op', ctypes.c_uint32, 8),
('sub_op', ctypes.c_uint32, 8),
('mtype', ctypes.c_uint32, 3),
('gcc', ctypes.c_uint32, 1),
('sys', ctypes.c_uint32, 1),
('pad1', ctypes.c_uint32, 1),
('snp', ctypes.c_uint32, 1),
('gpa', ctypes.c_uint32, 1),
('l2_policy', ctypes.c_uint32, 2),
('reserved_0', ctypes.c_uint32, 6),
]
union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False
union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [
('_0', struct_SDMA_PKT_FENCE_TAG_0_0),
('DW_0_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union):
pass
class struct_SDMA_PKT_FENCE_TAG_1_0(Structure):
pass
struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False
struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [
('addr_31_0', ctypes.c_uint32, 32),
]
union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False
union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [
('_0', struct_SDMA_PKT_FENCE_TAG_1_0),
('DW_1_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union):
pass
class struct_SDMA_PKT_FENCE_TAG_2_0(Structure):
pass
struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False
struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [
('addr_63_32', ctypes.c_uint32, 32),
]
union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False
union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [
('_0', struct_SDMA_PKT_FENCE_TAG_2_0),
('DW_2_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union):
pass
class struct_SDMA_PKT_FENCE_TAG_3_0(Structure):
pass
struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False
struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [
('data', ctypes.c_uint32, 32),
]
union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False
union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [
('_0', struct_SDMA_PKT_FENCE_TAG_3_0),
('DW_3_DATA', ctypes.c_uint32),
]
struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False
struct_SDMA_PKT_FENCE_TAG._fields_ = [
('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION),
('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION),
('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION),
('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION),
]
SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG
class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure):
pass
class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union):
pass
class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure):
pass
struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False
struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [
('op', ctypes.c_uint32, 8),
('sub_op', ctypes.c_uint32, 8),
('reserved_0', ctypes.c_uint32, 10),
('hdp_flush', ctypes.c_uint32, 1),
('reserved_1', ctypes.c_uint32, 1),
('func', ctypes.c_uint32, 3),
('mem_poll', ctypes.c_uint32, 1),
]
union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False
union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [
('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0),
('DW_0_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union):
pass
class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure):
pass
struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False
struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [
('addr_31_0', ctypes.c_uint32, 32),
]
union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False
union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [
('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0),
('DW_1_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union):
pass
class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure):
pass
struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False
struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [
('addr_63_32', ctypes.c_uint32, 32),
]
union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False
union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [
('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0),
('DW_2_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union):
pass
class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure):
pass
struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False
struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [
('value', ctypes.c_uint32, 32),
]
union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False
union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [
('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0),
('DW_3_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union):
pass
class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure):
pass
struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False
struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [
('mask', ctypes.c_uint32, 32),
]
union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False
union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [
('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0),
('DW_4_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union):
pass
class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure):
pass
struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False
struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [
('interval', ctypes.c_uint32, 16),
('retry_count', ctypes.c_uint32, 12),
('reserved_0', ctypes.c_uint32, 4),
]
union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False
union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [
('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0),
('DW_5_DATA', ctypes.c_uint32),
]
struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False
struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [
('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION),
('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION),
('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION),
('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION),
('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION),
('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION),
]
SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG
class struct_SDMA_PKT_ATOMIC_TAG(Structure):
pass
class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union):
pass
class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure):
pass
struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False
struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [
('op', ctypes.c_uint32, 8),
('sub_op', ctypes.c_uint32, 8),
('l', ctypes.c_uint32, 1),
('reserved_0', ctypes.c_uint32, 8),
('operation', ctypes.c_uint32, 7),
]
union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False
union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [
('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0),
('DW_0_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union):
pass
class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure):
pass
struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False
struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [
('addr_31_0', ctypes.c_uint32, 32),
]
union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False
union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [
('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0),
('DW_1_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union):
pass
class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure):
pass
struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False
struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [
('addr_63_32', ctypes.c_uint32, 32),
]
union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False
union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [
('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0),
('DW_2_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union):
pass
class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure):
pass
struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False
struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [
('src_data_31_0', ctypes.c_uint32, 32),
]
union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False
union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [
('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0),
('DW_3_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union):
pass
class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure):
pass
struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False
struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [
('src_data_63_32', ctypes.c_uint32, 32),
]
union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False
union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [
('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0),
('DW_4_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union):
pass
class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure):
pass
struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False
struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [
('cmp_data_31_0', ctypes.c_uint32, 32),
]
union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False
union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [
('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0),
('DW_5_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union):
pass
class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure):
pass
struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False
struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [
('cmp_data_63_32', ctypes.c_uint32, 32),
]
union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False
union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [
('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0),
('DW_6_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union):
pass
class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure):
pass
struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False
struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [
('loop_interval', ctypes.c_uint32, 13),
('reserved_0', ctypes.c_uint32, 19),
]
union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False
union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [
('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0),
('DW_7_DATA', ctypes.c_uint32),
]
struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False
struct_SDMA_PKT_ATOMIC_TAG._fields_ = [
('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION),
('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION),
('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION),
('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION),
('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION),
('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION),
('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION),
('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION),
]
SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG
class struct_SDMA_PKT_TIMESTAMP_TAG(Structure):
pass
class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union):
pass
class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure):
pass
struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False
struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [
('op', ctypes.c_uint32, 8),
('sub_op', ctypes.c_uint32, 8),
('reserved_0', ctypes.c_uint32, 16),
]
union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False
union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [
('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0),
('DW_0_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union):
pass
class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure):
pass
struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False
struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [
('addr_31_0', ctypes.c_uint32, 32),
]
union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False
union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [
('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0),
('DW_1_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union):
pass
class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure):
pass
struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False
struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [
('addr_63_32', ctypes.c_uint32, 32),
]
union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False
union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [
('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0),
('DW_2_DATA', ctypes.c_uint32),
]
struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False
struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [
('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION),
('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION),
('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION),
]
SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG
class struct_SDMA_PKT_TRAP_TAG(Structure):
pass
class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union):
pass
class struct_SDMA_PKT_TRAP_TAG_0_0(Structure):
pass
struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False
struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [
('op', ctypes.c_uint32, 8),
('sub_op', ctypes.c_uint32, 8),
('reserved_0', ctypes.c_uint32, 16),
]
union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False
union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [
('_0', struct_SDMA_PKT_TRAP_TAG_0_0),
('DW_0_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union):
pass
class struct_SDMA_PKT_TRAP_TAG_1_0(Structure):
pass
struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False
struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [
('int_ctx', ctypes.c_uint32, 28),
('reserved_1', ctypes.c_uint32, 4),
]
union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False
union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [
('_0', struct_SDMA_PKT_TRAP_TAG_1_0),
('DW_1_DATA', ctypes.c_uint32),
]
struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False
struct_SDMA_PKT_TRAP_TAG._fields_ = [
('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION),
('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION),
]
SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG
class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure):
pass
struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False
struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [
('DW_0_DATA', ctypes.c_uint32),
('DW_1_DATA', ctypes.c_uint32),
('DW_2_DATA', ctypes.c_uint32),
('DW_3_DATA', ctypes.c_uint32),
('DW_4_DATA', ctypes.c_uint32),
('DW_5_DATA', ctypes.c_uint32),
]
SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG
hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG
class struct_SDMA_PKT_GCR_TAG(Structure):
pass
class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union):
pass
class struct_SDMA_PKT_GCR_TAG_0_0(Structure):
pass
struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False
struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [
('op', ctypes.c_uint32, 8),
('sub_op', ctypes.c_uint32, 8),
('_2', ctypes.c_uint32, 16),
]
union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False
union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [
('_0', struct_SDMA_PKT_GCR_TAG_0_0),
('DW_0_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union):
pass
class struct_SDMA_PKT_GCR_TAG_1_0(Structure):
pass
struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False
struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [
('_0', ctypes.c_uint32, 7),
('BaseVA_LO', ctypes.c_uint32, 25),
]
union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False
union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [
('_0', struct_SDMA_PKT_GCR_TAG_1_0),
('DW_1_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union):
pass
class struct_SDMA_PKT_GCR_TAG_2_0(Structure):
pass
struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False
struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [
('BaseVA_HI', ctypes.c_uint32, 16),
('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2),
('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2),
('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1),
('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1),
('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1),
('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1),
('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1),
('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1),
('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1),
('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2),
('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1),
('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1),
('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1),
]
union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False
union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [
('_0', struct_SDMA_PKT_GCR_TAG_2_0),
('DW_2_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union):
pass
class struct_SDMA_PKT_GCR_TAG_3_0(Structure):
pass
struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False
struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [
('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1),
('GCR_CONTROL_SEQ', ctypes.c_uint32, 2),
('_2', ctypes.c_uint32, 4),
('LimitVA_LO', ctypes.c_uint32, 25),
]
union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False
union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [
('_0', struct_SDMA_PKT_GCR_TAG_3_0),
('DW_3_DATA', ctypes.c_uint32),
]
class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union):
pass
class struct_SDMA_PKT_GCR_TAG_4_0(Structure):
pass
struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False
struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [
('LimitVA_HI', ctypes.c_uint32, 16),
('_1', ctypes.c_uint32, 8),
('VMID', ctypes.c_uint32, 4),
('_3', ctypes.c_uint32, 4),
]
union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False
union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',)
union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [
('_0', struct_SDMA_PKT_GCR_TAG_4_0),
('DW_4_DATA', ctypes.c_uint32),
]
struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False
struct_SDMA_PKT_GCR_TAG._fields_ = [
('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION),
('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION),
('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION),
('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION),
('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION),
]
SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG
NVD_H = True # macro
PACKET_TYPE0 = 0 # macro
PACKET_TYPE1 = 1 # macro
PACKET_TYPE2 = 2 # macro
PACKET_TYPE3 = 3 # macro
def CP_PACKET_GET_TYPE(h): # macro
return (((h)>>30)&3)
def CP_PACKET_GET_COUNT(h): # macro
return (((h)>>16)&0x3FFF)
def CP_PACKET0_GET_REG(h): # macro
return ((h)&0xFFFF)
def CP_PACKET3_GET_OPCODE(h): # macro
return (((h)>>8)&0xFF)
def PACKET0(reg, n): # macro
return ((0<<30)|((reg)&0xFFFF)|((n)&0x3FFF)<<16)
CP_PACKET2 = 0x80000000 # macro
PACKET2_PAD_SHIFT = 0 # macro
PACKET2_PAD_MASK = (0x3fffffff<<0) # macro
# def PACKET2(v): # macro
# return (0x80000000|REG_SET(PACKET2_PAD,(v)))
def PACKET3(op, n): # macro
return ((3<<30)|(((op)&0xFF)<<8)|((n)&0x3FFF)<<16)
def PACKET3_COMPUTE(op, n): # macro
return (PACKET3(op,n)|1<<1)
PACKET3_NOP = 0x10 # macro
PACKET3_SET_BASE = 0x11 # macro
def PACKET3_BASE_INDEX(x): # macro
return ((x)<<0)
CE_PARTITION_BASE = 3 # macro
PACKET3_CLEAR_STATE = 0x12 # macro
PACKET3_INDEX_BUFFER_SIZE = 0x13 # macro
PACKET3_DISPATCH_DIRECT = 0x15 # macro
PACKET3_DISPATCH_INDIRECT = 0x16 # macro
PACKET3_INDIRECT_BUFFER_END = 0x17 # macro
PACKET3_INDIRECT_BUFFER_CNST_END = 0x19 # macro
PACKET3_ATOMIC_GDS = 0x1D # macro
PACKET3_ATOMIC_MEM = 0x1E # macro
PACKET3_OCCLUSION_QUERY = 0x1F # macro
PACKET3_SET_PREDICATION = 0x20 # macro
PACKET3_REG_RMW = 0x21 # macro
PACKET3_COND_EXEC = 0x22 # macro
PACKET3_PRED_EXEC = 0x23 # macro
PACKET3_DRAW_INDIRECT = 0x24 # macro
PACKET3_DRAW_INDEX_INDIRECT = 0x25 # macro
PACKET3_INDEX_BASE = 0x26 # macro
PACKET3_DRAW_INDEX_2 = 0x27 # macro
PACKET3_CONTEXT_CONTROL = 0x28 # macro
PACKET3_INDEX_TYPE = 0x2A # macro
PACKET3_DRAW_INDIRECT_MULTI = 0x2C # macro
PACKET3_DRAW_INDEX_AUTO = 0x2D # macro
PACKET3_NUM_INSTANCES = 0x2F # macro
PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30 # macro
PACKET3_INDIRECT_BUFFER_PRIV = 0x32 # macro
PACKET3_INDIRECT_BUFFER_CNST = 0x33 # macro
PACKET3_COND_INDIRECT_BUFFER_CNST = 0x33 # macro
PACKET3_STRMOUT_BUFFER_UPDATE = 0x34 # macro
PACKET3_DRAW_INDEX_OFFSET_2 = 0x35 # macro
PACKET3_DRAW_PREAMBLE = 0x36 # macro
PACKET3_WRITE_DATA = 0x37 # macro
def WRITE_DATA_DST_SEL(x): # macro
return ((x)<<8)
WR_ONE_ADDR = (1<<16) # macro
WR_CONFIRM = (1<<20) # macro
def WRITE_DATA_CACHE_POLICY(x): # macro
return ((x)<<25)
def WRITE_DATA_ENGINE_SEL(x): # macro
return ((x)<<30)
PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38 # macro
PACKET3_MEM_SEMAPHORE = 0x39 # macro
PACKET3_SEM_USE_MAILBOX = (0x1<<16) # macro
PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1<<20) # macro
PACKET3_SEM_SEL_SIGNAL = (0x6<<29) # macro
PACKET3_SEM_SEL_WAIT = (0x7<<29) # macro
PACKET3_DRAW_INDEX_MULTI_INST = 0x3A # macro
PACKET3_COPY_DW = 0x3B # macro
PACKET3_WAIT_REG_MEM = 0x3C # macro
def WAIT_REG_MEM_FUNCTION(x): # macro
return ((x)<<0)
def WAIT_REG_MEM_MEM_SPACE(x): # macro
return ((x)<<4)
def WAIT_REG_MEM_OPERATION(x): # macro
return ((x)<<6)
def WAIT_REG_MEM_ENGINE(x): # macro
return ((x)<<8)
PACKET3_INDIRECT_BUFFER = 0x3F # macro
INDIRECT_BUFFER_VALID = (1<<23) # macro
def INDIRECT_BUFFER_CACHE_POLICY(x): # macro
return ((x)<<28)
def INDIRECT_BUFFER_PRE_ENB(x): # macro
return ((x)<<21)
def INDIRECT_BUFFER_PRE_RESUME(x): # macro
return ((x)<<30)
PACKET3_COND_INDIRECT_BUFFER = 0x3F # macro
PACKET3_COPY_DATA = 0x40 # macro
PACKET3_CP_DMA = 0x41 # macro
PACKET3_PFP_SYNC_ME = 0x42 # macro
PACKET3_SURFACE_SYNC = 0x43 # macro
PACKET3_ME_INITIALIZE = 0x44 # macro
PACKET3_COND_WRITE = 0x45 # macro
PACKET3_EVENT_WRITE = 0x46 # macro
def EVENT_TYPE(x): # macro
return ((x)<<0)
def EVENT_INDEX(x): # macro
return ((x)<<8)
PACKET3_EVENT_WRITE_EOP = 0x47 # macro
PACKET3_EVENT_WRITE_EOS = 0x48 # macro
PACKET3_RELEASE_MEM = 0x49 # macro
def PACKET3_RELEASE_MEM_EVENT_TYPE(x): # macro
return ((x)<<0)
def PACKET3_RELEASE_MEM_EVENT_INDEX(x): # macro
return ((x)<<8)
PACKET3_RELEASE_MEM_GCR_GLM_WB = (1<<12) # macro
PACKET3_RELEASE_MEM_GCR_GLM_INV = (1<<13) # macro
PACKET3_RELEASE_MEM_GCR_GLV_INV = (1<<14) # macro
PACKET3_RELEASE_MEM_GCR_GL1_INV = (1<<15) # macro
PACKET3_RELEASE_MEM_GCR_GL2_US = (1<<16) # macro
PACKET3_RELEASE_MEM_GCR_GL2_RANGE = (1<<17) # macro
PACKET3_RELEASE_MEM_GCR_GL2_DISCARD = (1<<19) # macro
PACKET3_RELEASE_MEM_GCR_GL2_INV = (1<<20) # macro
PACKET3_RELEASE_MEM_GCR_GL2_WB = (1<<21) # macro
PACKET3_RELEASE_MEM_GCR_SEQ = (1<<22) # macro
def PACKET3_RELEASE_MEM_CACHE_POLICY(x): # macro
return ((x)<<25)
PACKET3_RELEASE_MEM_EXECUTE = (1<<28) # macro
def PACKET3_RELEASE_MEM_DATA_SEL(x): # macro
return ((x)<<29)
def PACKET3_RELEASE_MEM_INT_SEL(x): # macro
return ((x)<<24)
def PACKET3_RELEASE_MEM_DST_SEL(x): # macro
return ((x)<<16)
PACKET3_PREAMBLE_CNTL = 0x4A # macro
PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2<<28) # macro
PACKET3_PREAMBLE_END_CLEAR_STATE = (3<<28) # macro
PACKET3_DMA_DATA = 0x50 # macro
def PACKET3_DMA_DATA_ENGINE(x): # macro
return ((x)<<0)
def PACKET3_DMA_DATA_SRC_CACHE_POLICY(x): # macro
return ((x)<<13)
def PACKET3_DMA_DATA_DST_SEL(x): # macro
return ((x)<<20)
def PACKET3_DMA_DATA_DST_CACHE_POLICY(x): # macro
return ((x)<<25)
def PACKET3_DMA_DATA_SRC_SEL(x): # macro
return ((x)<<29)
PACKET3_DMA_DATA_CP_SYNC = (1<<31) # macro
PACKET3_DMA_DATA_CMD_SAS = (1<<26) # macro
PACKET3_DMA_DATA_CMD_DAS = (1<<27) # macro
PACKET3_DMA_DATA_CMD_SAIC = (1<<28) # macro
PACKET3_DMA_DATA_CMD_DAIC = (1<<29) # macro
PACKET3_DMA_DATA_CMD_RAW_WAIT = (1<<30) # macro
PACKET3_CONTEXT_REG_RMW = 0x51 # macro
PACKET3_GFX_CNTX_UPDATE = 0x52 # macro
PACKET3_BLK_CNTX_UPDATE = 0x53 # macro
PACKET3_INCR_UPDT_STATE = 0x55 # macro
PACKET3_ACQUIRE_MEM = 0x58 # macro
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x): # macro
return ((x)<<0)
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x): # macro
return ((x)<<2)
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x): # macro
return ((x)<<4)
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x): # macro
return ((x)<<5)
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x): # macro
return ((x)<<6)
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x): # macro
return ((x)<<7)
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x): # macro
return ((x)<<8)
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x): # macro
return ((x)<<9)
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x): # macro
return ((x)<<10)
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x): # macro
return ((x)<<11)
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x): # macro
return ((x)<<13)
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x): # macro
return ((x)<<14)
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x): # macro
return ((x)<<15)
def PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x): # macro
return ((x)<<16)
PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA = (1<<18) # macro
PACKET3_REWIND = 0x59 # macro
PACKET3_INTERRUPT = 0x5A # macro
PACKET3_GEN_PDEPTE = 0x5B # macro
PACKET3_INDIRECT_BUFFER_PASID = 0x5C # macro
PACKET3_PRIME_UTCL2 = 0x5D # macro
PACKET3_LOAD_UCONFIG_REG = 0x5E # macro
PACKET3_LOAD_SH_REG = 0x5F # macro
PACKET3_LOAD_CONFIG_REG = 0x60 # macro
PACKET3_LOAD_CONTEXT_REG = 0x61 # macro
PACKET3_LOAD_COMPUTE_STATE = 0x62 # macro
PACKET3_LOAD_SH_REG_INDEX = 0x63 # macro
PACKET3_SET_CONFIG_REG = 0x68 # macro
PACKET3_SET_CONFIG_REG_START = 0x00002000 # macro
PACKET3_SET_CONFIG_REG_END = 0x00002c00 # macro
PACKET3_SET_CONTEXT_REG = 0x69 # macro
PACKET3_SET_CONTEXT_REG_START = 0x0000a000 # macro
PACKET3_SET_CONTEXT_REG_END = 0x0000a400 # macro
PACKET3_SET_CONTEXT_REG_INDEX = 0x6A # macro
PACKET3_SET_VGPR_REG_DI_MULTI = 0x71 # macro
PACKET3_SET_SH_REG_DI = 0x72 # macro
PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73 # macro
PACKET3_SET_SH_REG_DI_MULTI = 0x74 # macro
PACKET3_GFX_PIPE_LOCK = 0x75 # macro
PACKET3_SET_SH_REG = 0x76 # macro
PACKET3_SET_SH_REG_START = 0x00002c00 # macro
PACKET3_SET_SH_REG_END = 0x00003000 # macro
PACKET3_SET_SH_REG_OFFSET = 0x77 # macro
PACKET3_SET_QUEUE_REG = 0x78 # macro
PACKET3_SET_UCONFIG_REG = 0x79 # macro
PACKET3_SET_UCONFIG_REG_START = 0x0000c000 # macro
PACKET3_SET_UCONFIG_REG_END = 0x0000c400 # macro
PACKET3_SET_UCONFIG_REG_INDEX = 0x7A # macro
PACKET3_FORWARD_HEADER = 0x7C # macro
PACKET3_SCRATCH_RAM_WRITE = 0x7D # macro
PACKET3_SCRATCH_RAM_READ = 0x7E # macro
PACKET3_LOAD_CONST_RAM = 0x80 # macro
PACKET3_WRITE_CONST_RAM = 0x81 # macro
PACKET3_DUMP_CONST_RAM = 0x83 # macro
PACKET3_INCREMENT_CE_COUNTER = 0x84 # macro
PACKET3_INCREMENT_DE_COUNTER = 0x85 # macro
PACKET3_WAIT_ON_CE_COUNTER = 0x86 # macro
PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88 # macro
PACKET3_SWITCH_BUFFER = 0x8B # macro
PACKET3_DISPATCH_DRAW_PREAMBLE = 0x8C # macro
PACKET3_DISPATCH_DRAW_PREAMBLE_ACE = 0x8C # macro
PACKET3_DISPATCH_DRAW = 0x8D # macro
PACKET3_DISPATCH_DRAW_ACE = 0x8D # macro
PACKET3_GET_LOD_STATS = 0x8E # macro
PACKET3_DRAW_MULTI_PREAMBLE = 0x8F # macro
PACKET3_FRAME_CONTROL = 0x90 # macro
FRAME_TMZ = (1<<0) # macro
def FRAME_CMD(x): # macro
return ((x)<<28)
PACKET3_INDEX_ATTRIBUTES_INDIRECT = 0x91 # macro
PACKET3_WAIT_REG_MEM64 = 0x93 # macro
PACKET3_COND_PREEMPT = 0x94 # macro
PACKET3_HDP_FLUSH = 0x95 # macro
PACKET3_COPY_DATA_RB = 0x96 # macro
PACKET3_INVALIDATE_TLBS = 0x98 # macro
def PACKET3_INVALIDATE_TLBS_DST_SEL(x): # macro
return ((x)<<0)
def PACKET3_INVALIDATE_TLBS_ALL_HUB(x): # macro
return ((x)<<4)
def PACKET3_INVALIDATE_TLBS_PASID(x): # macro
return ((x)<<5)
PACKET3_AQL_PACKET = 0x99 # macro
PACKET3_DMA_DATA_FILL_MULTI = 0x9A # macro
PACKET3_SET_SH_REG_INDEX = 0x9B # macro
PACKET3_DRAW_INDIRECT_COUNT_MULTI = 0x9C # macro
PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI = 0x9D # macro
PACKET3_DUMP_CONST_RAM_OFFSET = 0x9E # macro
PACKET3_LOAD_CONTEXT_REG_INDEX = 0x9F # macro
PACKET3_SET_RESOURCES = 0xA0 # macro
def PACKET3_SET_RESOURCES_VMID_MASK(x): # macro
return ((x)<<0)
def PACKET3_SET_RESOURCES_UNMAP_LATENTY(x): # macro
return ((x)<<16)
def PACKET3_SET_RESOURCES_QUEUE_TYPE(x): # macro
return ((x)<<29)
PACKET3_MAP_PROCESS = 0xA1 # macro
PACKET3_MAP_QUEUES = 0xA2 # macro
def PACKET3_MAP_QUEUES_QUEUE_SEL(x): # macro
return ((x)<<4)
def PACKET3_MAP_QUEUES_VMID(x): # macro
return ((x)<<8)
def PACKET3_MAP_QUEUES_QUEUE(x): # macro
return ((x)<<13)
def PACKET3_MAP_QUEUES_PIPE(x): # macro
return ((x)<<16)
def PACKET3_MAP_QUEUES_ME(x): # macro
return ((x)<<18)
def PACKET3_MAP_QUEUES_QUEUE_TYPE(x): # macro
return ((x)<<21)
def PACKET3_MAP_QUEUES_ALLOC_FORMAT(x): # macro
return ((x)<<24)
def PACKET3_MAP_QUEUES_ENGINE_SEL(x): # macro
return ((x)<<26)
def PACKET3_MAP_QUEUES_NUM_QUEUES(x): # macro
return ((x)<<29)
def PACKET3_MAP_QUEUES_CHECK_DISABLE(x): # macro
return ((x)<<1)
def PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x): # macro
return ((x)<<2)
PACKET3_UNMAP_QUEUES = 0xA3 # macro
def PACKET3_UNMAP_QUEUES_ACTION(x): # macro
return ((x)<<0)
def PACKET3_UNMAP_QUEUES_QUEUE_SEL(x): # macro
return ((x)<<4)
def PACKET3_UNMAP_QUEUES_ENGINE_SEL(x): # macro
return ((x)<<26)
def PACKET3_UNMAP_QUEUES_NUM_QUEUES(x): # macro
return ((x)<<29)
def PACKET3_UNMAP_QUEUES_PASID(x): # macro
return ((x)<<0)
def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x): # macro
return ((x)<<2)
def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x): # macro
return ((x)<<2)
def PACKET3_UNMAP_QUEUES_RB_WPTR(x): # macro
return ((x)<<0)
def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x): # macro
return ((x)<<2)
def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x): # macro
return ((x)<<2)
PACKET3_QUERY_STATUS = 0xA4 # macro
def PACKET3_QUERY_STATUS_CONTEXT_ID(x): # macro
return ((x)<<0)
def PACKET3_QUERY_STATUS_INTERRUPT_SEL(x): # macro
return ((x)<<28)
def PACKET3_QUERY_STATUS_COMMAND(x): # macro
return ((x)<<30)
def PACKET3_QUERY_STATUS_PASID(x): # macro
return ((x)<<0)
def PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x): # macro
return ((x)<<2)
def PACKET3_QUERY_STATUS_ENG_SEL(x): # macro
return ((x)<<25)
PACKET3_RUN_LIST = 0xA5 # macro
PACKET3_MAP_PROCESS_VM = 0xA6 # macro
PACKET3_SET_Q_PREEMPTION_MODE = 0xF0 # macro
def PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x): # macro
return ((x)<<0)
PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM = (1<<0) # macro
F32_MES_PM4_PACKETS_H = True # macro
uint32_t = True # macro
int32_t = True # macro
PM4_MES_HEADER_DEFINED = True # macro
PM4_MEC_RELEASE_MEM_DEFINED = True # macro
PM4_MEC_WRITE_DATA_DEFINED = True # macro
class union_PM4_MES_TYPE_3_HEADER(Union):
pass
class struct_PM4_MES_TYPE_3_HEADER_0(Structure):
pass
struct_PM4_MES_TYPE_3_HEADER_0._pack_ = 1 # source:False
struct_PM4_MES_TYPE_3_HEADER_0._fields_ = [
('reserved1', ctypes.c_uint32, 8),
('opcode', ctypes.c_uint32, 8),
('count', ctypes.c_uint32, 14),
('type', ctypes.c_uint32, 2),
]
union_PM4_MES_TYPE_3_HEADER._pack_ = 1 # source:False
union_PM4_MES_TYPE_3_HEADER._anonymous_ = ('_0',)
union_PM4_MES_TYPE_3_HEADER._fields_ = [
('_0', struct_PM4_MES_TYPE_3_HEADER_0),
('u32All', ctypes.c_uint32),
]
# values for enumeration 'c_uint32'
c_uint32__enumvalues = {
5: 'event_index__mec_release_mem__end_of_pipe',
6: 'event_index__mec_release_mem__shader_done',
}
event_index__mec_release_mem__end_of_pipe = 5
event_index__mec_release_mem__shader_done = 6
c_uint32 = ctypes.c_uint32 # enum
# values for enumeration 'c_uint32'
c_uint32__enumvalues = {
0: 'cache_policy__mec_release_mem__lru',
1: 'cache_policy__mec_release_mem__stream',
}
cache_policy__mec_release_mem__lru = 0
cache_policy__mec_release_mem__stream = 1
c_uint32 = ctypes.c_uint32 # enum
# values for enumeration 'c_uint32'
c_uint32__enumvalues = {
0: 'pq_exe_status__mec_release_mem__default',
1: 'pq_exe_status__mec_release_mem__phase_update',
}
pq_exe_status__mec_release_mem__default = 0
pq_exe_status__mec_release_mem__phase_update = 1
c_uint32 = ctypes.c_uint32 # enum
# values for enumeration 'c_uint32'
c_uint32__enumvalues = {
0: 'dst_sel__mec_release_mem__memory_controller',
1: 'dst_sel__mec_release_mem__tc_l2',
2: 'dst_sel__mec_release_mem__queue_write_pointer_register',
3: 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit',
}
dst_sel__mec_release_mem__memory_controller = 0
dst_sel__mec_release_mem__tc_l2 = 1
dst_sel__mec_release_mem__queue_write_pointer_register = 2
dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3
c_uint32 = ctypes.c_uint32 # enum
# values for enumeration 'c_uint32'
c_uint32__enumvalues = {
0: 'int_sel__mec_release_mem__none',
1: 'int_sel__mec_release_mem__send_interrupt_only',
2: 'int_sel__mec_release_mem__send_interrupt_after_write_confirm',
3: 'int_sel__mec_release_mem__send_data_after_write_confirm',
4: 'int_sel__mec_release_mem__unconditionally_send_int_ctxid',
5: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare',
6: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare',
}
int_sel__mec_release_mem__none = 0
int_sel__mec_release_mem__send_interrupt_only = 1
int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2
int_sel__mec_release_mem__send_data_after_write_confirm = 3
int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4
int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5
int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6
c_uint32 = ctypes.c_uint32 # enum
# values for enumeration 'c_uint32'
c_uint32__enumvalues = {
0: 'data_sel__mec_release_mem__none',
1: 'data_sel__mec_release_mem__send_32_bit_low',
2: 'data_sel__mec_release_mem__send_64_bit_data',
3: 'data_sel__mec_release_mem__send_gpu_clock_counter',
4: 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo',
5: 'data_sel__mec_release_mem__store_gds_data_to_memory',
}
data_sel__mec_release_mem__none = 0
data_sel__mec_release_mem__send_32_bit_low = 1
data_sel__mec_release_mem__send_64_bit_data = 2
data_sel__mec_release_mem__send_gpu_clock_counter = 3
data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4
data_sel__mec_release_mem__store_gds_data_to_memory = 5
c_uint32 = ctypes.c_uint32 # enum
class struct_pm4_mec_release_mem(Structure):
pass
class union_pm4_mec_release_mem_0(Union):
pass
union_pm4_mec_release_mem_0._pack_ = 1 # source:False
union_pm4_mec_release_mem_0._fields_ = [
('header', union_PM4_MES_TYPE_3_HEADER),
('ordinal1', ctypes.c_uint32),
]
class union_pm4_mec_release_mem_1(Union):
pass
class struct_pm4_mec_release_mem_1_bitfields2(Structure):
pass
struct_pm4_mec_release_mem_1_bitfields2._pack_ = 1 # source:False
struct_pm4_mec_release_mem_1_bitfields2._fields_ = [
('event_type', ctypes.c_uint32, 6),
('reserved1', ctypes.c_uint32, 2),
('event_index', c_uint32, 4),
('tcl1_vol_action_ena', ctypes.c_uint32, 1),
('tc_vol_action_ena', ctypes.c_uint32, 1),
('reserved2', ctypes.c_uint32, 1),
('tc_wb_action_ena', ctypes.c_uint32, 1),
('tcl1_action_ena', ctypes.c_uint32, 1),
('tc_action_ena', ctypes.c_uint32, 1),
('reserved3', ctypes.c_uint32, 1),
('tc_nc_action_ena', ctypes.c_uint32, 1),
('tc_wc_action_ena', ctypes.c_uint32, 1),
('tc_md_action_ena', ctypes.c_uint32, 1),
('reserved4', ctypes.c_uint32, 3),
('cache_policy', c_uint32, 2),
('reserved5', ctypes.c_uint32, 2),
('pq_exe_status', c_uint32, 1),
('reserved6', ctypes.c_uint32, 2),
]
union_pm4_mec_release_mem_1._pack_ = 1 # source:False
union_pm4_mec_release_mem_1._fields_ = [
('bitfields2', struct_pm4_mec_release_mem_1_bitfields2),
('ordinal2', ctypes.c_uint32),
]
class union_pm4_mec_release_mem_2(Union):
pass
class struct_pm4_mec_release_mem_2_bitfields3(Structure):
pass
struct_pm4_mec_release_mem_2_bitfields3._pack_ = 1 # source:False
struct_pm4_mec_release_mem_2_bitfields3._fields_ = [
('reserved7', ctypes.c_uint32, 16),
('dst_sel', c_uint32, 2),
('reserved8', ctypes.c_uint32, 6),
('int_sel', c_uint32, 3),
('reserved9', ctypes.c_uint32, 2),
('data_sel', c_uint32, 3),
]
union_pm4_mec_release_mem_2._pack_ = 1 # source:False
union_pm4_mec_release_mem_2._fields_ = [
('bitfields3', struct_pm4_mec_release_mem_2_bitfields3),
('ordinal3', ctypes.c_uint32),
]
class union_pm4_mec_release_mem_3(Union):
pass
class struct_pm4_mec_release_mem_3_bitfields4(Structure):
pass
struct_pm4_mec_release_mem_3_bitfields4._pack_ = 1 # source:False
struct_pm4_mec_release_mem_3_bitfields4._fields_ = [
('reserved10', ctypes.c_uint32, 2),
('address_lo_32b', ctypes.c_uint32, 30),
]
class struct_pm4_mec_release_mem_3_bitfields4b(Structure):
pass
struct_pm4_mec_release_mem_3_bitfields4b._pack_ = 1 # source:False
struct_pm4_mec_release_mem_3_bitfields4b._fields_ = [
('reserved11', ctypes.c_uint32, 3),
('address_lo_64b', ctypes.c_uint32, 29),
]
union_pm4_mec_release_mem_3._pack_ = 1 # source:False
union_pm4_mec_release_mem_3._fields_ = [
('bitfields4', struct_pm4_mec_release_mem_3_bitfields4),
('bitfields4b', struct_pm4_mec_release_mem_3_bitfields4b),
('reserved12', ctypes.c_uint32),
('ordinal4', ctypes.c_uint32),
]
class union_pm4_mec_release_mem_4(Union):
pass
union_pm4_mec_release_mem_4._pack_ = 1 # source:False
union_pm4_mec_release_mem_4._fields_ = [
('address_hi', ctypes.c_uint32),
('reserved13', ctypes.c_uint32),
('ordinal5', ctypes.c_uint32),
]
class union_pm4_mec_release_mem_5(Union):
pass
class struct_pm4_mec_release_mem_5_bitfields6c(Structure):
pass
struct_pm4_mec_release_mem_5_bitfields6c._pack_ = 1 # source:False
struct_pm4_mec_release_mem_5_bitfields6c._fields_ = [
('dw_offset', ctypes.c_uint32, 16),
('num_dwords', ctypes.c_uint32, 16),
]
union_pm4_mec_release_mem_5._pack_ = 1 # source:False
union_pm4_mec_release_mem_5._fields_ = [
('data_lo', ctypes.c_uint32),
('cmp_data_lo', ctypes.c_uint32),
('bitfields6c', struct_pm4_mec_release_mem_5_bitfields6c),
('reserved14', ctypes.c_uint32),
('ordinal6', ctypes.c_uint32),
]
class union_pm4_mec_release_mem_6(Union):
pass
union_pm4_mec_release_mem_6._pack_ = 1 # source:False
union_pm4_mec_release_mem_6._fields_ = [
('data_hi', ctypes.c_uint32),
('cmp_data_hi', ctypes.c_uint32),
('reserved15', ctypes.c_uint32),
('reserved16', ctypes.c_uint32),
('ordinal7', ctypes.c_uint32),
]
struct_pm4_mec_release_mem._pack_ = 1 # source:False
struct_pm4_mec_release_mem._anonymous_ = ('_0', '_1', '_2', '_3', '_4', '_5', '_6',)
struct_pm4_mec_release_mem._fields_ = [
('_0', union_pm4_mec_release_mem_0),
('_1', union_pm4_mec_release_mem_1),
('_2', union_pm4_mec_release_mem_2),
('_3', union_pm4_mec_release_mem_3),
('_4', union_pm4_mec_release_mem_4),
('_5', union_pm4_mec_release_mem_5),
('_6', union_pm4_mec_release_mem_6),
('int_ctxid', ctypes.c_uint32),
]
# values for enumeration 'WRITE_DATA_dst_sel_enum'
WRITE_DATA_dst_sel_enum__enumvalues = {
0: 'dst_sel___write_data__mem_mapped_register',
2: 'dst_sel___write_data__tc_l2',
3: 'dst_sel___write_data__gds',
5: 'dst_sel___write_data__memory',
6: 'dst_sel___write_data__memory_mapped_adc_persistent_state',
}
dst_sel___write_data__mem_mapped_register = 0
dst_sel___write_data__tc_l2 = 2
dst_sel___write_data__gds = 3
dst_sel___write_data__memory = 5
dst_sel___write_data__memory_mapped_adc_persistent_state = 6
WRITE_DATA_dst_sel_enum = ctypes.c_uint32 # enum
# values for enumeration 'WRITE_DATA_addr_incr_enum'
WRITE_DATA_addr_incr_enum__enumvalues = {
0: 'addr_incr___write_data__increment_address',
1: 'addr_incr___write_data__do_not_increment_address',
}
addr_incr___write_data__increment_address = 0
addr_incr___write_data__do_not_increment_address = 1
WRITE_DATA_addr_incr_enum = ctypes.c_uint32 # enum
# values for enumeration 'WRITE_DATA_wr_confirm_enum'
WRITE_DATA_wr_confirm_enum__enumvalues = {
0: 'wr_confirm___write_data__do_not_wait_for_write_confirmation',
1: 'wr_confirm___write_data__wait_for_write_confirmation',
}
wr_confirm___write_data__do_not_wait_for_write_confirmation = 0
wr_confirm___write_data__wait_for_write_confirmation = 1
WRITE_DATA_wr_confirm_enum = ctypes.c_uint32 # enum
# values for enumeration 'WRITE_DATA_cache_policy_enum'
WRITE_DATA_cache_policy_enum__enumvalues = {
0: 'cache_policy___write_data__lru',
1: 'cache_policy___write_data__stream',
}
cache_policy___write_data__lru = 0
cache_policy___write_data__stream = 1
WRITE_DATA_cache_policy_enum = ctypes.c_uint32 # enum
class struct_pm4_mec_write_data_mmio(Structure):
pass
class union_pm4_mec_write_data_mmio_0(Union):
pass
union_pm4_mec_write_data_mmio_0._pack_ = 1 # source:False
union_pm4_mec_write_data_mmio_0._fields_ = [
('header', union_PM4_MES_TYPE_3_HEADER),
('ordinal1', ctypes.c_uint32),
]
class union_pm4_mec_write_data_mmio_1(Union):
pass
class struct_pm4_mec_write_data_mmio_1_bitfields2(Structure):
pass
struct_pm4_mec_write_data_mmio_1_bitfields2._pack_ = 1 # source:False
struct_pm4_mec_write_data_mmio_1_bitfields2._fields_ = [
('reserved1', ctypes.c_uint32, 8),
('dst_sel', ctypes.c_uint32, 4),
('reserved2', ctypes.c_uint32, 4),
('addr_incr', ctypes.c_uint32, 1),
('reserved3', ctypes.c_uint32, 2),
('resume_vf', ctypes.c_uint32, 1),
('wr_confirm', ctypes.c_uint32, 1),
('reserved4', ctypes.c_uint32, 4),
('cache_policy', ctypes.c_uint32, 2),
('reserved5', ctypes.c_uint32, 5),
]
union_pm4_mec_write_data_mmio_1._pack_ = 1 # source:False
union_pm4_mec_write_data_mmio_1._fields_ = [
('bitfields2', struct_pm4_mec_write_data_mmio_1_bitfields2),
('ordinal2', ctypes.c_uint32),
]
class union_pm4_mec_write_data_mmio_2(Union):
pass
class struct_pm4_mec_write_data_mmio_2_bitfields3(Structure):
pass
struct_pm4_mec_write_data_mmio_2_bitfields3._pack_ = 1 # source:False
struct_pm4_mec_write_data_mmio_2_bitfields3._fields_ = [
('dst_mmreg_addr', ctypes.c_uint32, 18),
('reserved6', ctypes.c_uint32, 14),
]
union_pm4_mec_write_data_mmio_2._pack_ = 1 # source:False
union_pm4_mec_write_data_mmio_2._fields_ = [
('bitfields3', struct_pm4_mec_write_data_mmio_2_bitfields3),
('ordinal3', ctypes.c_uint32),
]
struct_pm4_mec_write_data_mmio._pack_ = 1 # source:False
struct_pm4_mec_write_data_mmio._anonymous_ = ('_0', '_1', '_2',)
struct_pm4_mec_write_data_mmio._fields_ = [
('_0', union_pm4_mec_write_data_mmio_0),
('_1', union_pm4_mec_write_data_mmio_1),
('_2', union_pm4_mec_write_data_mmio_2),
('reserved7', ctypes.c_uint32),
('data', ctypes.c_uint32),
]
# values for enumeration 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT'
c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT__enumvalues = {
20: 'CACHE_FLUSH_AND_INV_TS_EVENT',
}
CACHE_FLUSH_AND_INV_TS_EVENT = 20
c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT = ctypes.c_uint32 # enum
_soc21_ENUM_HEADER = True # macro
SQ_WAVE_TYPE_PS0 = 0x00000000 # macro
SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro
SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro
SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro
SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro
SQIND_WAVE_HWREGS_OFFSET = 0x00000100 # macro
SQIND_WAVE_HWREGS_SIZE = 0x00000100 # macro
SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro
SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro
SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro
SQIND_WAVE_VGPRS_SIZE = 0x00000400 # macro
SQ_GFXDEC_BEGIN = 0x0000a000 # macro
SQ_GFXDEC_END = 0x0000c000 # macro
SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro
SQDEC_BEGIN = 0x00002300 # macro
SQDEC_END = 0x000023ff # macro
SQPERFSDEC_BEGIN = 0x0000d9c0 # macro
SQPERFSDEC_END = 0x0000da40 # macro
SQPERFDDEC_BEGIN = 0x0000d1c0 # macro
SQPERFDDEC_END = 0x0000d240 # macro
SQGFXUDEC_BEGIN = 0x0000c330 # macro
SQGFXUDEC_END = 0x0000c380 # macro
SQPWRDEC_BEGIN = 0x0000f08c # macro
SQPWRDEC_END = 0x0000f094 # macro
SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro
SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro
SQ_MAX_PGM_SGPRS = 0x00000068 # macro
SQ_MAX_PGM_VGPRS = 0x00000100 # macro
SQ_EX_MODE_EXCP_VALU_BASE = 0x00000000 # macro
SQ_EX_MODE_EXCP_VALU_SIZE = 0x00000007 # macro
SQ_EX_MODE_EXCP_INVALID = 0x00000000 # macro
SQ_EX_MODE_EXCP_INPUT_DENORM = 0x00000001 # macro
SQ_EX_MODE_EXCP_DIV0 = 0x00000002 # macro
SQ_EX_MODE_EXCP_OVERFLOW = 0x00000003 # macro
SQ_EX_MODE_EXCP_UNDERFLOW = 0x00000004 # macro
SQ_EX_MODE_EXCP_INEXACT = 0x00000005 # macro
SQ_EX_MODE_EXCP_INT_DIV0 = 0x00000006 # macro
SQ_EX_MODE_EXCP_ADDR_WATCH0 = 0x00000007 # macro
SQ_EX_MODE_EXCP_MEM_VIOL = 0x00000008 # macro
SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 = 0x00000000 # macro
SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 = 0x00000001 # macro
SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 = 0x00000002 # macro
INST_ID_PRIV_START = 0x80000000 # macro
INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro
INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro
INST_ID_HW_TRAP = 0xfffffff2 # macro
INST_ID_KILL_SEQ = 0xfffffff3 # macro
INST_ID_SPI_WREXEC = 0xfffffff4 # macro
INST_ID_HW_TRAP_GET_TBA = 0xfffffff5 # macro
INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro
SIMM16_WAITCNT_EXP_CNT_START = 0x00000000 # macro
SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro
SIMM16_WAITCNT_LGKM_CNT_START = 0x00000004 # macro
SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000006 # macro
SIMM16_WAITCNT_VM_CNT_START = 0x0000000a # macro
SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000006 # macro
SIMM16_WAITCNT_DEPCTR_SA_SDST_START = 0x00000000 # macro
SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VA_VCC_START = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VM_VSRC_START = 0x00000002 # macro
SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE = 0x00000003 # macro
SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START = 0x00000006 # macro
SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VA_SSRC_START = 0x00000007 # macro
SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE = 0x00000001 # macro
SIMM16_WAITCNT_DEPCTR_VA_SDST_START = 0x00000008 # macro
SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE = 0x00000003 # macro
SIMM16_WAITCNT_DEPCTR_VA_VDST_START = 0x0000000b # macro
SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE = 0x00000005 # macro
SIMM16_WAIT_EVENT_EXP_RDY_START = 0x00000000 # macro
SIMM16_WAIT_EVENT_EXP_RDY_SIZE = 0x00000001 # macro
SQ_WAVE_IB_DEP_SA_SDST_SIZE = 0x00000004 # macro
SQ_WAVE_IB_DEP_SA_EXEC_SIZE = 0x00000002 # macro
SQ_WAVE_IB_DEP_SA_M0_SIZE = 0x00000001 # macro
SQ_WAVE_IB_DEP_VM_VSRC_SIZE = 0x00000004 # macro
SQ_WAVE_IB_DEP_HOLD_CNT_SIZE = 0x00000001 # macro
SQ_WAVE_IB_DEP_VA_SSRC_SIZE = 0x00000003 # macro
SQ_WAVE_IB_DEP_VA_SDST_SIZE = 0x00000004 # macro
SQ_WAVE_IB_DEP_VA_VCC_SIZE = 0x00000003 # macro
SQ_WAVE_IB_DEP_VA_EXEC_SIZE = 0x00000002 # macro
SQ_WAVE_IB_DEP_VA_VDST_SIZE = 0x00000005 # macro
SQ_WAVE_IB_DEP_LDS_DIR_SIZE = 0x00000003 # macro
SQ_EDC_FUE_CNTL_SIMD0 = 0x00000000 # macro
SQ_EDC_FUE_CNTL_SIMD1 = 0x00000001 # macro
SQ_EDC_FUE_CNTL_SIMD2 = 0x00000002 # macro
SQ_EDC_FUE_CNTL_SIMD3 = 0x00000003 # macro
SQ_EDC_FUE_CNTL_SQ = 0x00000004 # macro
SQ_EDC_FUE_CNTL_LDS = 0x00000005 # macro
SQ_EDC_FUE_CNTL_TD = 0x00000006 # macro
SQ_EDC_FUE_CNTL_TA = 0x00000007 # macro
SQ_EDC_FUE_CNTL_TCP = 0x00000008 # macro
CSDATA_TYPE_WIDTH = 0x00000002 # macro
CSDATA_ADDR_WIDTH = 0x00000007 # macro
CSDATA_DATA_WIDTH = 0x00000020 # macro
CSCNTL_TYPE_WIDTH = 0x00000002 # macro
CSCNTL_ADDR_WIDTH = 0x00000007 # macro
CSCNTL_DATA_WIDTH = 0x00000020 # macro
GSTHREADID_SIZE = 0x00000002 # macro
GB_TILING_CONFIG_TABLE_SIZE = 0x00000020 # macro
GB_TILING_CONFIG_MACROTABLE_SIZE = 0x00000010 # macro
SEM_ECC_ERROR = 0x00000000 # macro
SEM_TRANS_ERROR = 0x00000001 # macro
SEM_RESP_FAILED = 0x00000002 # macro
SEM_RESP_PASSED = 0x00000003 # macro
IQ_QUEUE_SLEEP = 0x00000000 # macro
IQ_OFFLOAD_RETRY = 0x00000001 # macro
IQ_SCH_WAVE_MSG = 0x00000002 # macro
IQ_SEM_REARM = 0x00000003 # macro
IQ_DEQUEUE_RETRY = 0x00000004 # macro
IQ_INTR_TYPE_PQ = 0x00000000 # macro
IQ_INTR_TYPE_IB = 0x00000001 # macro
IQ_INTR_TYPE_MQD = 0x00000002 # macro
VMID_SZ = 0x00000004 # macro
SRCID_RLC = 0x00000000 # macro
SRCID_RLCV = 0x00000006 # macro
SRCID_SECURE_CP = 0x00000007 # macro
SRCID_NONSECURE_CP = 0x00000001 # macro
SRCID_SECURE_CP_RCIU = 0x00000007 # macro
SRCID_NONSECURE_CP_RCIU = 0x00000001 # macro
CONFIG_SPACE_START = 0x00002000 # macro
CONFIG_SPACE_END = 0x00009fff # macro
CONFIG_SPACE1_START = 0x00002000 # macro
CONFIG_SPACE1_END = 0x00002bff # macro
CONFIG_SPACE2_START = 0x00003000 # macro
CONFIG_SPACE2_END = 0x00009fff # macro
UCONFIG_SPACE_START = 0x0000c000 # macro
UCONFIG_SPACE_END = 0x0000ffff # macro
PERSISTENT_SPACE_START = 0x00002c00 # macro
PERSISTENT_SPACE_END = 0x00002fff # macro
CONTEXT_SPACE_START = 0x0000a000 # macro
CONTEXT_SPACE_END = 0x0000a3ff # macro
ROM_SIGNATURE = 0x0000aa55 # macro
# values for enumeration 'DSM_DATA_SEL'
DSM_DATA_SEL__enumvalues = {
0: 'DSM_DATA_SEL_DISABLE',
1: 'DSM_DATA_SEL_0',
2: 'DSM_DATA_SEL_1',
3: 'DSM_DATA_SEL_BOTH',
}
DSM_DATA_SEL_DISABLE = 0
DSM_DATA_SEL_0 = 1
DSM_DATA_SEL_1 = 2
DSM_DATA_SEL_BOTH = 3
DSM_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DSM_ENABLE_ERROR_INJECT'
DSM_ENABLE_ERROR_INJECT__enumvalues = {
0: 'DSM_ENABLE_ERROR_INJECT_FED_IN',
1: 'DSM_ENABLE_ERROR_INJECT_SINGLE',
2: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE',
3: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED',
}
DSM_ENABLE_ERROR_INJECT_FED_IN = 0
DSM_ENABLE_ERROR_INJECT_SINGLE = 1
DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 2
DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 3
DSM_ENABLE_ERROR_INJECT = ctypes.c_uint32 # enum
# values for enumeration 'DSM_SELECT_INJECT_DELAY'
DSM_SELECT_INJECT_DELAY__enumvalues = {
0: 'DSM_SELECT_INJECT_DELAY_NO_DELAY',
1: 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR',
}
DSM_SELECT_INJECT_DELAY_NO_DELAY = 0
DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 1
DSM_SELECT_INJECT_DELAY = ctypes.c_uint32 # enum
# values for enumeration 'DSM_SINGLE_WRITE'
DSM_SINGLE_WRITE__enumvalues = {
0: 'DSM_SINGLE_WRITE_DIS',
1: 'DSM_SINGLE_WRITE_EN',
}
DSM_SINGLE_WRITE_DIS = 0
DSM_SINGLE_WRITE_EN = 1
DSM_SINGLE_WRITE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_NUM_SIMD_PER_CU'
ENUM_NUM_SIMD_PER_CU__enumvalues = {
2: 'NUM_SIMD_PER_CU',
}
NUM_SIMD_PER_CU = 2
ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum
# values for enumeration 'GATCL1RequestType'
GATCL1RequestType__enumvalues = {
0: 'GATCL1_TYPE_NORMAL',
1: 'GATCL1_TYPE_SHOOTDOWN',
2: 'GATCL1_TYPE_BYPASS',
}
GATCL1_TYPE_NORMAL = 0
GATCL1_TYPE_SHOOTDOWN = 1
GATCL1_TYPE_BYPASS = 2
GATCL1RequestType = ctypes.c_uint32 # enum
# values for enumeration 'GL0V_CACHE_POLICIES'
GL0V_CACHE_POLICIES__enumvalues = {
0: 'GL0V_CACHE_POLICY_MISS_LRU',
1: 'GL0V_CACHE_POLICY_MISS_EVICT',
2: 'GL0V_CACHE_POLICY_HIT_LRU',
3: 'GL0V_CACHE_POLICY_HIT_EVICT',
}
GL0V_CACHE_POLICY_MISS_LRU = 0
GL0V_CACHE_POLICY_MISS_EVICT = 1
GL0V_CACHE_POLICY_HIT_LRU = 2
GL0V_CACHE_POLICY_HIT_EVICT = 3
GL0V_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'GL1_CACHE_POLICIES'
GL1_CACHE_POLICIES__enumvalues = {
0: 'GL1_CACHE_POLICY_MISS_LRU',
1: 'GL1_CACHE_POLICY_MISS_EVICT',
2: 'GL1_CACHE_POLICY_HIT_LRU',
3: 'GL1_CACHE_POLICY_HIT_EVICT',
}
GL1_CACHE_POLICY_MISS_LRU = 0
GL1_CACHE_POLICY_MISS_EVICT = 1
GL1_CACHE_POLICY_HIT_LRU = 2
GL1_CACHE_POLICY_HIT_EVICT = 3
GL1_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'GL1_CACHE_STORE_POLICIES'
GL1_CACHE_STORE_POLICIES__enumvalues = {
0: 'GL1_CACHE_STORE_POLICY_BYPASS',
}
GL1_CACHE_STORE_POLICY_BYPASS = 0
GL1_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'GL2_CACHE_POLICIES'
GL2_CACHE_POLICIES__enumvalues = {
0: 'GL2_CACHE_POLICY_LRU',
1: 'GL2_CACHE_POLICY_STREAM',
2: 'GL2_CACHE_POLICY_NOA',
3: 'GL2_CACHE_POLICY_BYPASS',
}
GL2_CACHE_POLICY_LRU = 0
GL2_CACHE_POLICY_STREAM = 1
GL2_CACHE_POLICY_NOA = 2
GL2_CACHE_POLICY_BYPASS = 3
GL2_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'Hdp_SurfaceEndian'
Hdp_SurfaceEndian__enumvalues = {
0: 'HDP_ENDIAN_NONE',
1: 'HDP_ENDIAN_8IN16',
2: 'HDP_ENDIAN_8IN32',
3: 'HDP_ENDIAN_8IN64',
}
HDP_ENDIAN_NONE = 0
HDP_ENDIAN_8IN16 = 1
HDP_ENDIAN_8IN32 = 2
HDP_ENDIAN_8IN64 = 3
Hdp_SurfaceEndian = ctypes.c_uint32 # enum
# values for enumeration 'MTYPE'
MTYPE__enumvalues = {
0: 'MTYPE_C_RW_US',
1: 'MTYPE_RESERVED_1',
2: 'MTYPE_C_RO_S',
3: 'MTYPE_UC',
4: 'MTYPE_C_RW_S',
5: 'MTYPE_RESERVED_5',
6: 'MTYPE_C_RO_US',
7: 'MTYPE_RESERVED_7',
}
MTYPE_C_RW_US = 0
MTYPE_RESERVED_1 = 1
MTYPE_C_RO_S = 2
MTYPE_UC = 3
MTYPE_C_RW_S = 4
MTYPE_RESERVED_5 = 5
MTYPE_C_RO_US = 6
MTYPE_RESERVED_7 = 7
MTYPE = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_COUNTER_MODE'
PERFMON_COUNTER_MODE__enumvalues = {
0: 'PERFMON_COUNTER_MODE_ACCUM',
1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES',
2: 'PERFMON_COUNTER_MODE_MAX',
3: 'PERFMON_COUNTER_MODE_DIRTY',
4: 'PERFMON_COUNTER_MODE_SAMPLE',
5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT',
6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT',
7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI',
8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI',
9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES',
15: 'PERFMON_COUNTER_MODE_RESERVED',
}
PERFMON_COUNTER_MODE_ACCUM = 0
PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1
PERFMON_COUNTER_MODE_MAX = 2
PERFMON_COUNTER_MODE_DIRTY = 3
PERFMON_COUNTER_MODE_SAMPLE = 4
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6
PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7
PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8
PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9
PERFMON_COUNTER_MODE_RESERVED = 15
PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_SPM_MODE'
PERFMON_SPM_MODE__enumvalues = {
0: 'PERFMON_SPM_MODE_OFF',
1: 'PERFMON_SPM_MODE_16BIT_CLAMP',
2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP',
3: 'PERFMON_SPM_MODE_32BIT_CLAMP',
4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP',
5: 'PERFMON_SPM_MODE_RESERVED_5',
6: 'PERFMON_SPM_MODE_RESERVED_6',
7: 'PERFMON_SPM_MODE_RESERVED_7',
8: 'PERFMON_SPM_MODE_TEST_MODE_0',
9: 'PERFMON_SPM_MODE_TEST_MODE_1',
10: 'PERFMON_SPM_MODE_TEST_MODE_2',
}
PERFMON_SPM_MODE_OFF = 0
PERFMON_SPM_MODE_16BIT_CLAMP = 1
PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2
PERFMON_SPM_MODE_32BIT_CLAMP = 3
PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4
PERFMON_SPM_MODE_RESERVED_5 = 5
PERFMON_SPM_MODE_RESERVED_6 = 6
PERFMON_SPM_MODE_RESERVED_7 = 7
PERFMON_SPM_MODE_TEST_MODE_0 = 8
PERFMON_SPM_MODE_TEST_MODE_1 = 9
PERFMON_SPM_MODE_TEST_MODE_2 = 10
PERFMON_SPM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'RMI_CID'
RMI_CID__enumvalues = {
0: 'RMI_CID_CC',
1: 'RMI_CID_FC',
2: 'RMI_CID_CM',
3: 'RMI_CID_DC',
4: 'RMI_CID_Z',
5: 'RMI_CID_S',
6: 'RMI_CID_TILE',
7: 'RMI_CID_ZPCPSD',
}
RMI_CID_CC = 0
RMI_CID_FC = 1
RMI_CID_CM = 2
RMI_CID_DC = 3
RMI_CID_Z = 4
RMI_CID_S = 5
RMI_CID_TILE = 6
RMI_CID_ZPCPSD = 7
RMI_CID = ctypes.c_uint32 # enum
# values for enumeration 'ReadPolicy'
ReadPolicy__enumvalues = {
0: 'CACHE_LRU_RD',
1: 'CACHE_STREAM_RD',
2: 'CACHE_NOA',
3: 'RESERVED_RDPOLICY',
}
CACHE_LRU_RD = 0
CACHE_STREAM_RD = 1
CACHE_NOA = 2
RESERVED_RDPOLICY = 3
ReadPolicy = ctypes.c_uint32 # enum
# values for enumeration 'SDMA_PERFMON_SEL'
SDMA_PERFMON_SEL__enumvalues = {
0: 'SDMA_PERFMON_SEL_CYCLE',
1: 'SDMA_PERFMON_SEL_IDLE',
2: 'SDMA_PERFMON_SEL_REG_IDLE',
3: 'SDMA_PERFMON_SEL_RB_EMPTY',
4: 'SDMA_PERFMON_SEL_RB_FULL',
5: 'SDMA_PERFMON_SEL_RB_WPTR_WRAP',
6: 'SDMA_PERFMON_SEL_RB_RPTR_WRAP',
7: 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ',
8: 'SDMA_PERFMON_SEL_RB_RPTR_WB',
9: 'SDMA_PERFMON_SEL_RB_CMD_IDLE',
10: 'SDMA_PERFMON_SEL_RB_CMD_FULL',
11: 'SDMA_PERFMON_SEL_IB_CMD_IDLE',
12: 'SDMA_PERFMON_SEL_IB_CMD_FULL',
13: 'SDMA_PERFMON_SEL_EX_IDLE',
14: 'SDMA_PERFMON_SEL_SRBM_REG_SEND',
15: 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
16: 'SDMA_PERFMON_SEL_WR_BA_RTR',
17: 'SDMA_PERFMON_SEL_MC_WR_IDLE',
18: 'SDMA_PERFMON_SEL_MC_WR_COUNT',
19: 'SDMA_PERFMON_SEL_RD_BA_RTR',
20: 'SDMA_PERFMON_SEL_MC_RD_IDLE',
21: 'SDMA_PERFMON_SEL_MC_RD_COUNT',
22: 'SDMA_PERFMON_SEL_MC_RD_RET_STALL',
23: 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE',
26: 'SDMA_PERFMON_SEL_SEM_IDLE',
27: 'SDMA_PERFMON_SEL_SEM_REQ_STALL',
28: 'SDMA_PERFMON_SEL_SEM_REQ_COUNT',
29: 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE',
30: 'SDMA_PERFMON_SEL_SEM_RESP_FAIL',
31: 'SDMA_PERFMON_SEL_SEM_RESP_PASS',
32: 'SDMA_PERFMON_SEL_INT_IDLE',
33: 'SDMA_PERFMON_SEL_INT_REQ_STALL',
34: 'SDMA_PERFMON_SEL_INT_REQ_COUNT',
35: 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED',
36: 'SDMA_PERFMON_SEL_INT_RESP_RETRY',
37: 'SDMA_PERFMON_SEL_NUM_PACKET',
39: 'SDMA_PERFMON_SEL_CE_WREQ_IDLE',
40: 'SDMA_PERFMON_SEL_CE_WR_IDLE',
41: 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE',
42: 'SDMA_PERFMON_SEL_CE_RREQ_IDLE',
43: 'SDMA_PERFMON_SEL_CE_OUT_IDLE',
44: 'SDMA_PERFMON_SEL_CE_IN_IDLE',
45: 'SDMA_PERFMON_SEL_CE_DST_IDLE',
48: 'SDMA_PERFMON_SEL_CE_AFIFO_FULL',
51: 'SDMA_PERFMON_SEL_CE_INFO_FULL',
52: 'SDMA_PERFMON_SEL_CE_INFO1_FULL',
53: 'SDMA_PERFMON_SEL_CE_RD_STALL',
54: 'SDMA_PERFMON_SEL_CE_WR_STALL',
55: 'SDMA_PERFMON_SEL_GFX_SELECT',
56: 'SDMA_PERFMON_SEL_RLC0_SELECT',
57: 'SDMA_PERFMON_SEL_RLC1_SELECT',
58: 'SDMA_PERFMON_SEL_PAGE_SELECT',
59: 'SDMA_PERFMON_SEL_CTX_CHANGE',
60: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED',
61: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION',
62: 'SDMA_PERFMON_SEL_DOORBELL',
63: 'SDMA_PERFMON_SEL_F32_L1_WR_VLD',
64: 'SDMA_PERFMON_SEL_CE_L1_WR_VLD',
65: 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ',
66: 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK',
67: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ',
68: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK',
69: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL',
70: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL',
71: 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK',
72: 'SDMA_PERFMON_SEL_UTCL2_RET_ACK',
73: 'SDMA_PERFMON_SEL_UTCL2_FREE',
74: 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND',
75: 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND',
76: 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND',
77: 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND',
78: 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND',
79: 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH',
80: 'SDMA_PERFMON_SEL_GPUVM_INV_LOW',
81: 'SDMA_PERFMON_SEL_L1_WRL2_IDLE',
82: 'SDMA_PERFMON_SEL_L1_RDL2_IDLE',
83: 'SDMA_PERFMON_SEL_L1_WRMC_IDLE',
84: 'SDMA_PERFMON_SEL_L1_RDMC_IDLE',
85: 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE',
86: 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE',
87: 'SDMA_PERFMON_SEL_META_L2_REQ_SEND',
88: 'SDMA_PERFMON_SEL_L2_META_RET_VLD',
89: 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND',
90: 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN',
91: 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND',
92: 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN',
93: 'SDMA_PERFMON_SEL_META_REQ_SEND',
94: 'SDMA_PERFMON_SEL_META_RTN_VLD',
95: 'SDMA_PERFMON_SEL_TLBI_SEND',
96: 'SDMA_PERFMON_SEL_TLBI_RTN',
97: 'SDMA_PERFMON_SEL_GCR_SEND',
98: 'SDMA_PERFMON_SEL_GCR_RTN',
99: 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER',
100: 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER',
}
SDMA_PERFMON_SEL_CYCLE = 0
SDMA_PERFMON_SEL_IDLE = 1
SDMA_PERFMON_SEL_REG_IDLE = 2
SDMA_PERFMON_SEL_RB_EMPTY = 3
SDMA_PERFMON_SEL_RB_FULL = 4
SDMA_PERFMON_SEL_RB_WPTR_WRAP = 5
SDMA_PERFMON_SEL_RB_RPTR_WRAP = 6
SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 7
SDMA_PERFMON_SEL_RB_RPTR_WB = 8
SDMA_PERFMON_SEL_RB_CMD_IDLE = 9
SDMA_PERFMON_SEL_RB_CMD_FULL = 10
SDMA_PERFMON_SEL_IB_CMD_IDLE = 11
SDMA_PERFMON_SEL_IB_CMD_FULL = 12
SDMA_PERFMON_SEL_EX_IDLE = 13
SDMA_PERFMON_SEL_SRBM_REG_SEND = 14
SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15
SDMA_PERFMON_SEL_WR_BA_RTR = 16
SDMA_PERFMON_SEL_MC_WR_IDLE = 17
SDMA_PERFMON_SEL_MC_WR_COUNT = 18
SDMA_PERFMON_SEL_RD_BA_RTR = 19
SDMA_PERFMON_SEL_MC_RD_IDLE = 20
SDMA_PERFMON_SEL_MC_RD_COUNT = 21
SDMA_PERFMON_SEL_MC_RD_RET_STALL = 22
SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 23
SDMA_PERFMON_SEL_SEM_IDLE = 26
SDMA_PERFMON_SEL_SEM_REQ_STALL = 27
SDMA_PERFMON_SEL_SEM_REQ_COUNT = 28
SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 29
SDMA_PERFMON_SEL_SEM_RESP_FAIL = 30
SDMA_PERFMON_SEL_SEM_RESP_PASS = 31
SDMA_PERFMON_SEL_INT_IDLE = 32
SDMA_PERFMON_SEL_INT_REQ_STALL = 33
SDMA_PERFMON_SEL_INT_REQ_COUNT = 34
SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 35
SDMA_PERFMON_SEL_INT_RESP_RETRY = 36
SDMA_PERFMON_SEL_NUM_PACKET = 37
SDMA_PERFMON_SEL_CE_WREQ_IDLE = 39
SDMA_PERFMON_SEL_CE_WR_IDLE = 40
SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 41
SDMA_PERFMON_SEL_CE_RREQ_IDLE = 42
SDMA_PERFMON_SEL_CE_OUT_IDLE = 43
SDMA_PERFMON_SEL_CE_IN_IDLE = 44
SDMA_PERFMON_SEL_CE_DST_IDLE = 45
SDMA_PERFMON_SEL_CE_AFIFO_FULL = 48
SDMA_PERFMON_SEL_CE_INFO_FULL = 51
SDMA_PERFMON_SEL_CE_INFO1_FULL = 52
SDMA_PERFMON_SEL_CE_RD_STALL = 53
SDMA_PERFMON_SEL_CE_WR_STALL = 54
SDMA_PERFMON_SEL_GFX_SELECT = 55
SDMA_PERFMON_SEL_RLC0_SELECT = 56
SDMA_PERFMON_SEL_RLC1_SELECT = 57
SDMA_PERFMON_SEL_PAGE_SELECT = 58
SDMA_PERFMON_SEL_CTX_CHANGE = 59
SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 60
SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 61
SDMA_PERFMON_SEL_DOORBELL = 62
SDMA_PERFMON_SEL_F32_L1_WR_VLD = 63
SDMA_PERFMON_SEL_CE_L1_WR_VLD = 64
SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 65
SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 66
SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 67
SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 68
SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 69
SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 70
SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 71
SDMA_PERFMON_SEL_UTCL2_RET_ACK = 72
SDMA_PERFMON_SEL_UTCL2_FREE = 73
SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 74
SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 75
SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 76
SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 77
SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 78
SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 79
SDMA_PERFMON_SEL_GPUVM_INV_LOW = 80
SDMA_PERFMON_SEL_L1_WRL2_IDLE = 81
SDMA_PERFMON_SEL_L1_RDL2_IDLE = 82
SDMA_PERFMON_SEL_L1_WRMC_IDLE = 83
SDMA_PERFMON_SEL_L1_RDMC_IDLE = 84
SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 85
SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 86
SDMA_PERFMON_SEL_META_L2_REQ_SEND = 87
SDMA_PERFMON_SEL_L2_META_RET_VLD = 88
SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 89
SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 90
SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 91
SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 92
SDMA_PERFMON_SEL_META_REQ_SEND = 93
SDMA_PERFMON_SEL_META_RTN_VLD = 94
SDMA_PERFMON_SEL_TLBI_SEND = 95
SDMA_PERFMON_SEL_TLBI_RTN = 96
SDMA_PERFMON_SEL_GCR_SEND = 97
SDMA_PERFMON_SEL_GCR_RTN = 98
SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 99
SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 100
SDMA_PERFMON_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SDMA_PERF_SEL'
SDMA_PERF_SEL__enumvalues = {
0: 'SDMA_PERF_SEL_CYCLE',
1: 'SDMA_PERF_SEL_IDLE',
2: 'SDMA_PERF_SEL_REG_IDLE',
3: 'SDMA_PERF_SEL_RB_EMPTY',
4: 'SDMA_PERF_SEL_RB_FULL',
5: 'SDMA_PERF_SEL_RB_WPTR_WRAP',
6: 'SDMA_PERF_SEL_RB_RPTR_WRAP',
7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ',
8: 'SDMA_PERF_SEL_RB_RPTR_WB',
9: 'SDMA_PERF_SEL_RB_CMD_IDLE',
10: 'SDMA_PERF_SEL_RB_CMD_FULL',
11: 'SDMA_PERF_SEL_IB_CMD_IDLE',
12: 'SDMA_PERF_SEL_IB_CMD_FULL',
13: 'SDMA_PERF_SEL_EX_IDLE',
14: 'SDMA_PERF_SEL_SRBM_REG_SEND',
15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
16: 'SDMA_PERF_SEL_MC_WR_IDLE',
17: 'SDMA_PERF_SEL_MC_WR_COUNT',
18: 'SDMA_PERF_SEL_MC_RD_IDLE',
19: 'SDMA_PERF_SEL_MC_RD_COUNT',
20: 'SDMA_PERF_SEL_MC_RD_RET_STALL',
21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE',
24: 'SDMA_PERF_SEL_SEM_IDLE',
25: 'SDMA_PERF_SEL_SEM_REQ_STALL',
26: 'SDMA_PERF_SEL_SEM_REQ_COUNT',
27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE',
28: 'SDMA_PERF_SEL_SEM_RESP_FAIL',
29: 'SDMA_PERF_SEL_SEM_RESP_PASS',
30: 'SDMA_PERF_SEL_INT_IDLE',
31: 'SDMA_PERF_SEL_INT_REQ_STALL',
32: 'SDMA_PERF_SEL_INT_REQ_COUNT',
33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED',
34: 'SDMA_PERF_SEL_INT_RESP_RETRY',
35: 'SDMA_PERF_SEL_NUM_PACKET',
37: 'SDMA_PERF_SEL_CE_WREQ_IDLE',
38: 'SDMA_PERF_SEL_CE_WR_IDLE',
39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE',
40: 'SDMA_PERF_SEL_CE_RREQ_IDLE',
41: 'SDMA_PERF_SEL_CE_OUT_IDLE',
42: 'SDMA_PERF_SEL_CE_IN_IDLE',
43: 'SDMA_PERF_SEL_CE_DST_IDLE',
46: 'SDMA_PERF_SEL_CE_AFIFO_FULL',
49: 'SDMA_PERF_SEL_CE_INFO_FULL',
50: 'SDMA_PERF_SEL_CE_INFO1_FULL',
51: 'SDMA_PERF_SEL_CE_RD_STALL',
52: 'SDMA_PERF_SEL_CE_WR_STALL',
53: 'SDMA_PERF_SEL_GFX_SELECT',
54: 'SDMA_PERF_SEL_RLC0_SELECT',
55: 'SDMA_PERF_SEL_RLC1_SELECT',
56: 'SDMA_PERF_SEL_PAGE_SELECT',
57: 'SDMA_PERF_SEL_CTX_CHANGE',
58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED',
59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION',
60: 'SDMA_PERF_SEL_DOORBELL',
61: 'SDMA_PERF_SEL_RD_BA_RTR',
62: 'SDMA_PERF_SEL_WR_BA_RTR',
63: 'SDMA_PERF_SEL_F32_L1_WR_VLD',
64: 'SDMA_PERF_SEL_CE_L1_WR_VLD',
65: 'SDMA_PERF_SEL_CPF_SDMA_INVREQ',
66: 'SDMA_PERF_SEL_SDMA_CPF_INVACK',
67: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ',
68: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK',
69: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL',
70: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL',
71: 'SDMA_PERF_SEL_UTCL2_RET_XNACK',
72: 'SDMA_PERF_SEL_UTCL2_RET_ACK',
73: 'SDMA_PERF_SEL_UTCL2_FREE',
74: 'SDMA_PERF_SEL_SDMA_UTCL2_SEND',
75: 'SDMA_PERF_SEL_DMA_L1_WR_SEND',
76: 'SDMA_PERF_SEL_DMA_L1_RD_SEND',
77: 'SDMA_PERF_SEL_DMA_MC_WR_SEND',
78: 'SDMA_PERF_SEL_DMA_MC_RD_SEND',
79: 'SDMA_PERF_SEL_GPUVM_INV_HIGH',
80: 'SDMA_PERF_SEL_GPUVM_INV_LOW',
81: 'SDMA_PERF_SEL_L1_WRL2_IDLE',
82: 'SDMA_PERF_SEL_L1_RDL2_IDLE',
83: 'SDMA_PERF_SEL_L1_WRMC_IDLE',
84: 'SDMA_PERF_SEL_L1_RDMC_IDLE',
85: 'SDMA_PERF_SEL_L1_WR_INV_IDLE',
86: 'SDMA_PERF_SEL_L1_RD_INV_IDLE',
87: 'SDMA_PERF_SEL_META_L2_REQ_SEND',
88: 'SDMA_PERF_SEL_L2_META_RET_VLD',
89: 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND',
90: 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN',
91: 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND',
92: 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN',
93: 'SDMA_PERF_SEL_META_REQ_SEND',
94: 'SDMA_PERF_SEL_META_RTN_VLD',
95: 'SDMA_PERF_SEL_TLBI_SEND',
96: 'SDMA_PERF_SEL_TLBI_RTN',
97: 'SDMA_PERF_SEL_GCR_SEND',
98: 'SDMA_PERF_SEL_GCR_RTN',
99: 'SDMA_PERF_SEL_CGCG_FENCE',
100: 'SDMA_PERF_SEL_CE_CH_WR_REQ',
101: 'SDMA_PERF_SEL_CE_CH_WR_RET',
102: 'SDMA_PERF_SEL_F32_CH_WR_REQ',
103: 'SDMA_PERF_SEL_F32_CH_WR_RET',
104: 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ',
105: 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET',
106: 'SDMA_PERF_SEL_RB_CH_RD_REQ',
107: 'SDMA_PERF_SEL_RB_CH_RD_RET',
108: 'SDMA_PERF_SEL_IB_CH_RD_REQ',
109: 'SDMA_PERF_SEL_IB_CH_RD_RET',
110: 'SDMA_PERF_SEL_WPTR_CH_RD_REQ',
111: 'SDMA_PERF_SEL_WPTR_CH_RD_RET',
112: 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ',
113: 'SDMA_PERF_SEL_UTCL1_UTCL2_RET',
114: 'SDMA_PERF_SEL_CMD_OP_MATCH',
115: 'SDMA_PERF_SEL_CMD_OP_START',
116: 'SDMA_PERF_SEL_CMD_OP_END',
117: 'SDMA_PERF_SEL_CE_BUSY',
118: 'SDMA_PERF_SEL_CE_BUSY_START',
119: 'SDMA_PERF_SEL_CE_BUSY_END',
120: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER',
121: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START',
122: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END',
123: 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND',
124: 'SDMA_PERF_SEL_CH_CE_WRRET_VALID',
125: 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND',
126: 'SDMA_PERF_SEL_CH_CE_RDRET_VALID',
}
SDMA_PERF_SEL_CYCLE = 0
SDMA_PERF_SEL_IDLE = 1
SDMA_PERF_SEL_REG_IDLE = 2
SDMA_PERF_SEL_RB_EMPTY = 3
SDMA_PERF_SEL_RB_FULL = 4
SDMA_PERF_SEL_RB_WPTR_WRAP = 5
SDMA_PERF_SEL_RB_RPTR_WRAP = 6
SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7
SDMA_PERF_SEL_RB_RPTR_WB = 8
SDMA_PERF_SEL_RB_CMD_IDLE = 9
SDMA_PERF_SEL_RB_CMD_FULL = 10
SDMA_PERF_SEL_IB_CMD_IDLE = 11
SDMA_PERF_SEL_IB_CMD_FULL = 12
SDMA_PERF_SEL_EX_IDLE = 13
SDMA_PERF_SEL_SRBM_REG_SEND = 14
SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15
SDMA_PERF_SEL_MC_WR_IDLE = 16
SDMA_PERF_SEL_MC_WR_COUNT = 17
SDMA_PERF_SEL_MC_RD_IDLE = 18
SDMA_PERF_SEL_MC_RD_COUNT = 19
SDMA_PERF_SEL_MC_RD_RET_STALL = 20
SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21
SDMA_PERF_SEL_SEM_IDLE = 24
SDMA_PERF_SEL_SEM_REQ_STALL = 25
SDMA_PERF_SEL_SEM_REQ_COUNT = 26
SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27
SDMA_PERF_SEL_SEM_RESP_FAIL = 28
SDMA_PERF_SEL_SEM_RESP_PASS = 29
SDMA_PERF_SEL_INT_IDLE = 30
SDMA_PERF_SEL_INT_REQ_STALL = 31
SDMA_PERF_SEL_INT_REQ_COUNT = 32
SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33
SDMA_PERF_SEL_INT_RESP_RETRY = 34
SDMA_PERF_SEL_NUM_PACKET = 35
SDMA_PERF_SEL_CE_WREQ_IDLE = 37
SDMA_PERF_SEL_CE_WR_IDLE = 38
SDMA_PERF_SEL_CE_SPLIT_IDLE = 39
SDMA_PERF_SEL_CE_RREQ_IDLE = 40
SDMA_PERF_SEL_CE_OUT_IDLE = 41
SDMA_PERF_SEL_CE_IN_IDLE = 42
SDMA_PERF_SEL_CE_DST_IDLE = 43
SDMA_PERF_SEL_CE_AFIFO_FULL = 46
SDMA_PERF_SEL_CE_INFO_FULL = 49
SDMA_PERF_SEL_CE_INFO1_FULL = 50
SDMA_PERF_SEL_CE_RD_STALL = 51
SDMA_PERF_SEL_CE_WR_STALL = 52
SDMA_PERF_SEL_GFX_SELECT = 53
SDMA_PERF_SEL_RLC0_SELECT = 54
SDMA_PERF_SEL_RLC1_SELECT = 55
SDMA_PERF_SEL_PAGE_SELECT = 56
SDMA_PERF_SEL_CTX_CHANGE = 57
SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58
SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59
SDMA_PERF_SEL_DOORBELL = 60
SDMA_PERF_SEL_RD_BA_RTR = 61
SDMA_PERF_SEL_WR_BA_RTR = 62
SDMA_PERF_SEL_F32_L1_WR_VLD = 63
SDMA_PERF_SEL_CE_L1_WR_VLD = 64
SDMA_PERF_SEL_CPF_SDMA_INVREQ = 65
SDMA_PERF_SEL_SDMA_CPF_INVACK = 66
SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 67
SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 68
SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 69
SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 70
SDMA_PERF_SEL_UTCL2_RET_XNACK = 71
SDMA_PERF_SEL_UTCL2_RET_ACK = 72
SDMA_PERF_SEL_UTCL2_FREE = 73
SDMA_PERF_SEL_SDMA_UTCL2_SEND = 74
SDMA_PERF_SEL_DMA_L1_WR_SEND = 75
SDMA_PERF_SEL_DMA_L1_RD_SEND = 76
SDMA_PERF_SEL_DMA_MC_WR_SEND = 77
SDMA_PERF_SEL_DMA_MC_RD_SEND = 78
SDMA_PERF_SEL_GPUVM_INV_HIGH = 79
SDMA_PERF_SEL_GPUVM_INV_LOW = 80
SDMA_PERF_SEL_L1_WRL2_IDLE = 81
SDMA_PERF_SEL_L1_RDL2_IDLE = 82
SDMA_PERF_SEL_L1_WRMC_IDLE = 83
SDMA_PERF_SEL_L1_RDMC_IDLE = 84
SDMA_PERF_SEL_L1_WR_INV_IDLE = 85
SDMA_PERF_SEL_L1_RD_INV_IDLE = 86
SDMA_PERF_SEL_META_L2_REQ_SEND = 87
SDMA_PERF_SEL_L2_META_RET_VLD = 88
SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 89
SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 90
SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 91
SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 92
SDMA_PERF_SEL_META_REQ_SEND = 93
SDMA_PERF_SEL_META_RTN_VLD = 94
SDMA_PERF_SEL_TLBI_SEND = 95
SDMA_PERF_SEL_TLBI_RTN = 96
SDMA_PERF_SEL_GCR_SEND = 97
SDMA_PERF_SEL_GCR_RTN = 98
SDMA_PERF_SEL_CGCG_FENCE = 99
SDMA_PERF_SEL_CE_CH_WR_REQ = 100
SDMA_PERF_SEL_CE_CH_WR_RET = 101
SDMA_PERF_SEL_F32_CH_WR_REQ = 102
SDMA_PERF_SEL_F32_CH_WR_RET = 103
SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ = 104
SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET = 105
SDMA_PERF_SEL_RB_CH_RD_REQ = 106
SDMA_PERF_SEL_RB_CH_RD_RET = 107
SDMA_PERF_SEL_IB_CH_RD_REQ = 108
SDMA_PERF_SEL_IB_CH_RD_RET = 109
SDMA_PERF_SEL_WPTR_CH_RD_REQ = 110
SDMA_PERF_SEL_WPTR_CH_RD_RET = 111
SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 112
SDMA_PERF_SEL_UTCL1_UTCL2_RET = 113
SDMA_PERF_SEL_CMD_OP_MATCH = 114
SDMA_PERF_SEL_CMD_OP_START = 115
SDMA_PERF_SEL_CMD_OP_END = 116
SDMA_PERF_SEL_CE_BUSY = 117
SDMA_PERF_SEL_CE_BUSY_START = 118
SDMA_PERF_SEL_CE_BUSY_END = 119
SDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 120
SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 121
SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 122
SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 123
SDMA_PERF_SEL_CH_CE_WRRET_VALID = 124
SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 125
SDMA_PERF_SEL_CH_CE_RDRET_VALID = 126
SDMA_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TCC_CACHE_POLICIES'
TCC_CACHE_POLICIES__enumvalues = {
0: 'TCC_CACHE_POLICY_LRU',
1: 'TCC_CACHE_POLICY_STREAM',
}
TCC_CACHE_POLICY_LRU = 0
TCC_CACHE_POLICY_STREAM = 1
TCC_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'TCC_MTYPE'
TCC_MTYPE__enumvalues = {
0: 'MTYPE_NC',
1: 'MTYPE_WC',
2: 'MTYPE_CC',
}
MTYPE_NC = 0
MTYPE_WC = 1
MTYPE_CC = 2
TCC_MTYPE = ctypes.c_uint32 # enum
# values for enumeration 'UTCL0FaultType'
UTCL0FaultType__enumvalues = {
0: 'UTCL0_XNACK_SUCCESS',
1: 'UTCL0_XNACK_RETRY',
2: 'UTCL0_XNACK_PRT',
3: 'UTCL0_XNACK_NO_RETRY',
}
UTCL0_XNACK_SUCCESS = 0
UTCL0_XNACK_RETRY = 1
UTCL0_XNACK_PRT = 2
UTCL0_XNACK_NO_RETRY = 3
UTCL0FaultType = ctypes.c_uint32 # enum
# values for enumeration 'UTCL0RequestType'
UTCL0RequestType__enumvalues = {
0: 'UTCL0_TYPE_NORMAL',
1: 'UTCL0_TYPE_SHOOTDOWN',
2: 'UTCL0_TYPE_BYPASS',
}
UTCL0_TYPE_NORMAL = 0
UTCL0_TYPE_SHOOTDOWN = 1
UTCL0_TYPE_BYPASS = 2
UTCL0RequestType = ctypes.c_uint32 # enum
# values for enumeration 'UTCL1FaultType'
UTCL1FaultType__enumvalues = {
0: 'UTCL1_XNACK_SUCCESS',
1: 'UTCL1_XNACK_RETRY',
2: 'UTCL1_XNACK_PRT',
3: 'UTCL1_XNACK_NO_RETRY',
}
UTCL1_XNACK_SUCCESS = 0
UTCL1_XNACK_RETRY = 1
UTCL1_XNACK_PRT = 2
UTCL1_XNACK_NO_RETRY = 3
UTCL1FaultType = ctypes.c_uint32 # enum
# values for enumeration 'UTCL1RequestType'
UTCL1RequestType__enumvalues = {
0: 'UTCL1_TYPE_NORMAL',
1: 'UTCL1_TYPE_SHOOTDOWN',
2: 'UTCL1_TYPE_BYPASS',
}
UTCL1_TYPE_NORMAL = 0
UTCL1_TYPE_SHOOTDOWN = 1
UTCL1_TYPE_BYPASS = 2
UTCL1RequestType = ctypes.c_uint32 # enum
# values for enumeration 'VMEMCMD_RETURN_ORDER'
VMEMCMD_RETURN_ORDER__enumvalues = {
0: 'VMEMCMD_RETURN_OUT_OF_ORDER',
1: 'VMEMCMD_RETURN_IN_ORDER',
2: 'VMEMCMD_RETURN_IN_ORDER_READ',
}
VMEMCMD_RETURN_OUT_OF_ORDER = 0
VMEMCMD_RETURN_IN_ORDER = 1
VMEMCMD_RETURN_IN_ORDER_READ = 2
VMEMCMD_RETURN_ORDER = ctypes.c_uint32 # enum
# values for enumeration 'WritePolicy'
WritePolicy__enumvalues = {
0: 'CACHE_LRU_WR',
1: 'CACHE_STREAM',
2: 'CACHE_NOA_WR',
3: 'CACHE_BYPASS',
}
CACHE_LRU_WR = 0
CACHE_STREAM = 1
CACHE_NOA_WR = 2
CACHE_BYPASS = 3
WritePolicy = ctypes.c_uint32 # enum
# values for enumeration 'CNVC_BYPASS'
CNVC_BYPASS__enumvalues = {
0: 'CNVC_BYPASS_DISABLE',
1: 'CNVC_BYPASS_EN',
}
CNVC_BYPASS_DISABLE = 0
CNVC_BYPASS_EN = 1
CNVC_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'CNVC_COEF_FORMAT_ENUM'
CNVC_COEF_FORMAT_ENUM__enumvalues = {
0: 'CNVC_FIX_S2_13',
1: 'CNVC_FIX_S3_12',
}
CNVC_FIX_S2_13 = 0
CNVC_FIX_S3_12 = 1
CNVC_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CNVC_ENABLE'
CNVC_ENABLE__enumvalues = {
0: 'CNVC_DIS',
1: 'CNVC_EN',
}
CNVC_DIS = 0
CNVC_EN = 1
CNVC_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'CNVC_PENDING'
CNVC_PENDING__enumvalues = {
0: 'CNVC_NOT_PENDING',
1: 'CNVC_YES_PENDING',
}
CNVC_NOT_PENDING = 0
CNVC_YES_PENDING = 1
CNVC_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'COLOR_KEYER_MODE'
COLOR_KEYER_MODE__enumvalues = {
0: 'FORCE_00',
1: 'FORCE_FF',
2: 'RANGE_00',
3: 'RANGE_FF',
}
FORCE_00 = 0
FORCE_FF = 1
RANGE_00 = 2
RANGE_FF = 3
COLOR_KEYER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DENORM_TRUNCATE'
DENORM_TRUNCATE__enumvalues = {
0: 'CNVC_ROUND',
1: 'CNVC_TRUNCATE',
}
CNVC_ROUND = 0
CNVC_TRUNCATE = 1
DENORM_TRUNCATE = ctypes.c_uint32 # enum
# values for enumeration 'FORMAT_CROSSBAR'
FORMAT_CROSSBAR__enumvalues = {
0: 'FORMAT_CROSSBAR_R',
1: 'FORMAT_CROSSBAR_G',
2: 'FORMAT_CROSSBAR_B',
}
FORMAT_CROSSBAR_R = 0
FORMAT_CROSSBAR_G = 1
FORMAT_CROSSBAR_B = 2
FORMAT_CROSSBAR = ctypes.c_uint32 # enum
# values for enumeration 'PIX_EXPAND_MODE'
PIX_EXPAND_MODE__enumvalues = {
0: 'PIX_DYNAMIC_EXPANSION',
1: 'PIX_ZERO_EXPANSION',
}
PIX_DYNAMIC_EXPANSION = 0
PIX_ZERO_EXPANSION = 1
PIX_EXPAND_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PRE_CSC_MODE_ENUM'
PRE_CSC_MODE_ENUM__enumvalues = {
0: 'PRE_CSC_BYPASS',
1: 'PRE_CSC_SET_A',
2: 'PRE_CSC_SET_B',
}
PRE_CSC_BYPASS = 0
PRE_CSC_SET_A = 1
PRE_CSC_SET_B = 2
PRE_CSC_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'PRE_DEGAM_MODE'
PRE_DEGAM_MODE__enumvalues = {
0: 'PRE_DEGAM_BYPASS',
1: 'PRE_DEGAM_ENABLE',
}
PRE_DEGAM_BYPASS = 0
PRE_DEGAM_ENABLE = 1
PRE_DEGAM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PRE_DEGAM_SELECT'
PRE_DEGAM_SELECT__enumvalues = {
0: 'PRE_DEGAM_SRGB',
1: 'PRE_DEGAM_GAMMA_22',
2: 'PRE_DEGAM_GAMMA_24',
3: 'PRE_DEGAM_GAMMA_26',
4: 'PRE_DEGAM_BT2020',
5: 'PRE_DEGAM_BT2100PQ',
6: 'PRE_DEGAM_BT2100HLG',
}
PRE_DEGAM_SRGB = 0
PRE_DEGAM_GAMMA_22 = 1
PRE_DEGAM_GAMMA_24 = 2
PRE_DEGAM_GAMMA_26 = 3
PRE_DEGAM_BT2020 = 4
PRE_DEGAM_BT2100PQ = 5
PRE_DEGAM_BT2100HLG = 6
PRE_DEGAM_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_PIXEL_FORMAT'
SURFACE_PIXEL_FORMAT__enumvalues = {
1: 'ARGB1555',
2: 'RGBA5551',
3: 'RGB565',
4: 'BGR565',
5: 'ARGB4444',
6: 'RGBA4444',
8: 'ARGB8888',
9: 'RGBA8888',
10: 'ARGB2101010',
11: 'RGBA1010102',
12: 'AYCrCb8888',
13: 'YCrCbA8888',
14: 'ACrYCb8888',
15: 'CrYCbA8888',
16: 'ARGB16161616_10MSB',
17: 'RGBA16161616_10MSB',
18: 'ARGB16161616_10LSB',
19: 'RGBA16161616_10LSB',
20: 'ARGB16161616_12MSB',
21: 'RGBA16161616_12MSB',
22: 'ARGB16161616_12LSB',
23: 'RGBA16161616_12LSB',
24: 'ARGB16161616_FLOAT',
25: 'RGBA16161616_FLOAT',
26: 'ARGB16161616_UNORM',
27: 'RGBA16161616_UNORM',
28: 'ARGB16161616_SNORM',
29: 'RGBA16161616_SNORM',
32: 'AYCrCb16161616_10MSB',
33: 'AYCrCb16161616_10LSB',
34: 'YCrCbA16161616_10MSB',
35: 'YCrCbA16161616_10LSB',
36: 'ACrYCb16161616_10MSB',
37: 'ACrYCb16161616_10LSB',
38: 'CrYCbA16161616_10MSB',
39: 'CrYCbA16161616_10LSB',
40: 'AYCrCb16161616_12MSB',
41: 'AYCrCb16161616_12LSB',
42: 'YCrCbA16161616_12MSB',
43: 'YCrCbA16161616_12LSB',
44: 'ACrYCb16161616_12MSB',
45: 'ACrYCb16161616_12LSB',
46: 'CrYCbA16161616_12MSB',
47: 'CrYCbA16161616_12LSB',
64: 'Y8_CrCb88_420_PLANAR',
65: 'Y8_CbCr88_420_PLANAR',
66: 'Y10_CrCb1010_420_PLANAR',
67: 'Y10_CbCr1010_420_PLANAR',
68: 'Y12_CrCb1212_420_PLANAR',
69: 'Y12_CbCr1212_420_PLANAR',
72: 'YCrYCb8888_422_PACKED',
73: 'YCbYCr8888_422_PACKED',
74: 'CrYCbY8888_422_PACKED',
75: 'CbYCrY8888_422_PACKED',
76: 'YCrYCb10101010_422_PACKED',
77: 'YCbYCr10101010_422_PACKED',
78: 'CrYCbY10101010_422_PACKED',
79: 'CbYCrY10101010_422_PACKED',
80: 'YCrYCb12121212_422_PACKED',
81: 'YCbYCr12121212_422_PACKED',
82: 'CrYCbY12121212_422_PACKED',
83: 'CbYCrY12121212_422_PACKED',
112: 'RGB111110_FIX',
113: 'BGR101111_FIX',
114: 'ACrYCb2101010',
115: 'CrYCbA1010102',
116: 'RGBE',
118: 'RGB111110_FLOAT',
119: 'BGR101111_FLOAT',
120: 'MONO_8',
121: 'MONO_10MSB',
122: 'MONO_10LSB',
123: 'MONO_12MSB',
124: 'MONO_12LSB',
125: 'MONO_16',
}
ARGB1555 = 1
RGBA5551 = 2
RGB565 = 3
BGR565 = 4
ARGB4444 = 5
RGBA4444 = 6
ARGB8888 = 8
RGBA8888 = 9
ARGB2101010 = 10
RGBA1010102 = 11
AYCrCb8888 = 12
YCrCbA8888 = 13
ACrYCb8888 = 14
CrYCbA8888 = 15
ARGB16161616_10MSB = 16
RGBA16161616_10MSB = 17
ARGB16161616_10LSB = 18
RGBA16161616_10LSB = 19
ARGB16161616_12MSB = 20
RGBA16161616_12MSB = 21
ARGB16161616_12LSB = 22
RGBA16161616_12LSB = 23
ARGB16161616_FLOAT = 24
RGBA16161616_FLOAT = 25
ARGB16161616_UNORM = 26
RGBA16161616_UNORM = 27
ARGB16161616_SNORM = 28
RGBA16161616_SNORM = 29
AYCrCb16161616_10MSB = 32
AYCrCb16161616_10LSB = 33
YCrCbA16161616_10MSB = 34
YCrCbA16161616_10LSB = 35
ACrYCb16161616_10MSB = 36
ACrYCb16161616_10LSB = 37
CrYCbA16161616_10MSB = 38
CrYCbA16161616_10LSB = 39
AYCrCb16161616_12MSB = 40
AYCrCb16161616_12LSB = 41
YCrCbA16161616_12MSB = 42
YCrCbA16161616_12LSB = 43
ACrYCb16161616_12MSB = 44
ACrYCb16161616_12LSB = 45
CrYCbA16161616_12MSB = 46
CrYCbA16161616_12LSB = 47
Y8_CrCb88_420_PLANAR = 64
Y8_CbCr88_420_PLANAR = 65
Y10_CrCb1010_420_PLANAR = 66
Y10_CbCr1010_420_PLANAR = 67
Y12_CrCb1212_420_PLANAR = 68
Y12_CbCr1212_420_PLANAR = 69
YCrYCb8888_422_PACKED = 72
YCbYCr8888_422_PACKED = 73
CrYCbY8888_422_PACKED = 74
CbYCrY8888_422_PACKED = 75
YCrYCb10101010_422_PACKED = 76
YCbYCr10101010_422_PACKED = 77
CrYCbY10101010_422_PACKED = 78
CbYCrY10101010_422_PACKED = 79
YCrYCb12121212_422_PACKED = 80
YCbYCr12121212_422_PACKED = 81
CrYCbY12121212_422_PACKED = 82
CbYCrY12121212_422_PACKED = 83
RGB111110_FIX = 112
BGR101111_FIX = 113
ACrYCb2101010 = 114
CrYCbA1010102 = 115
RGBE = 116
RGB111110_FLOAT = 118
BGR101111_FLOAT = 119
MONO_8 = 120
MONO_10MSB = 121
MONO_10LSB = 122
MONO_12MSB = 123
MONO_12LSB = 124
MONO_16 = 125
SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'XNORM'
XNORM__enumvalues = {
0: 'XNORM_A',
1: 'XNORM_B',
}
XNORM_A = 0
XNORM_B = 1
XNORM = ctypes.c_uint32 # enum
# values for enumeration 'CUR_ENABLE'
CUR_ENABLE__enumvalues = {
0: 'CUR_DIS',
1: 'CUR_EN',
}
CUR_DIS = 0
CUR_EN = 1
CUR_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'CUR_EXPAND_MODE'
CUR_EXPAND_MODE__enumvalues = {
0: 'CUR_DYNAMIC_EXPANSION',
1: 'CUR_ZERO_EXPANSION',
}
CUR_DYNAMIC_EXPANSION = 0
CUR_ZERO_EXPANSION = 1
CUR_EXPAND_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CUR_INV_CLAMP'
CUR_INV_CLAMP__enumvalues = {
0: 'CUR_CLAMP_DIS',
1: 'CUR_CLAMP_EN',
}
CUR_CLAMP_DIS = 0
CUR_CLAMP_EN = 1
CUR_INV_CLAMP = ctypes.c_uint32 # enum
# values for enumeration 'CUR_MODE'
CUR_MODE__enumvalues = {
0: 'MONO_2BIT',
1: 'COLOR_24BIT_1BIT_AND',
2: 'COLOR_24BIT_8BIT_ALPHA_PREMULT',
3: 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT',
4: 'COLOR_64BIT_FP_PREMULT',
5: 'COLOR_64BIT_FP_UNPREMULT',
}
MONO_2BIT = 0
COLOR_24BIT_1BIT_AND = 1
COLOR_24BIT_8BIT_ALPHA_PREMULT = 2
COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3
COLOR_64BIT_FP_PREMULT = 4
COLOR_64BIT_FP_UNPREMULT = 5
CUR_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CUR_PENDING'
CUR_PENDING__enumvalues = {
0: 'CUR_NOT_PENDING',
1: 'CUR_YES_PENDING',
}
CUR_NOT_PENDING = 0
CUR_YES_PENDING = 1
CUR_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'CUR_ROM_EN'
CUR_ROM_EN__enumvalues = {
0: 'CUR_FP_NO_ROM',
1: 'CUR_FP_USE_ROM',
}
CUR_FP_NO_ROM = 0
CUR_FP_USE_ROM = 1
CUR_ROM_EN = ctypes.c_uint32 # enum
# values for enumeration 'COEF_RAM_SELECT_RD'
COEF_RAM_SELECT_RD__enumvalues = {
0: 'COEF_RAM_SELECT_BACK',
1: 'COEF_RAM_SELECT_CURRENT',
}
COEF_RAM_SELECT_BACK = 0
COEF_RAM_SELECT_CURRENT = 1
COEF_RAM_SELECT_RD = ctypes.c_uint32 # enum
# values for enumeration 'DSCL_MODE_SEL'
DSCL_MODE_SEL__enumvalues = {
0: 'DSCL_MODE_SCALING_444_BYPASS',
1: 'DSCL_MODE_SCALING_444_RGB_ENABLE',
2: 'DSCL_MODE_SCALING_444_YCBCR_ENABLE',
3: 'DSCL_MODE_SCALING_YCBCR_ENABLE',
4: 'DSCL_MODE_LUMA_SCALING_BYPASS',
5: 'DSCL_MODE_CHROMA_SCALING_BYPASS',
6: 'DSCL_MODE_DSCL_BYPASS',
}
DSCL_MODE_SCALING_444_BYPASS = 0
DSCL_MODE_SCALING_444_RGB_ENABLE = 1
DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2
DSCL_MODE_SCALING_YCBCR_ENABLE = 3
DSCL_MODE_LUMA_SCALING_BYPASS = 4
DSCL_MODE_CHROMA_SCALING_BYPASS = 5
DSCL_MODE_DSCL_BYPASS = 6
DSCL_MODE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'LB_ALPHA_EN'
LB_ALPHA_EN__enumvalues = {
0: 'LB_ALPHA_DISABLE',
1: 'LB_ALPHA_ENABLE',
}
LB_ALPHA_DISABLE = 0
LB_ALPHA_ENABLE = 1
LB_ALPHA_EN = ctypes.c_uint32 # enum
# values for enumeration 'LB_INTERLEAVE_EN'
LB_INTERLEAVE_EN__enumvalues = {
0: 'LB_INTERLEAVE_DISABLE',
1: 'LB_INTERLEAVE_ENABLE',
}
LB_INTERLEAVE_DISABLE = 0
LB_INTERLEAVE_ENABLE = 1
LB_INTERLEAVE_EN = ctypes.c_uint32 # enum
# values for enumeration 'LB_MEMORY_CONFIG'
LB_MEMORY_CONFIG__enumvalues = {
0: 'LB_MEMORY_CONFIG_0',
1: 'LB_MEMORY_CONFIG_1',
2: 'LB_MEMORY_CONFIG_2',
3: 'LB_MEMORY_CONFIG_3',
}
LB_MEMORY_CONFIG_0 = 0
LB_MEMORY_CONFIG_1 = 1
LB_MEMORY_CONFIG_2 = 2
LB_MEMORY_CONFIG_3 = 3
LB_MEMORY_CONFIG = ctypes.c_uint32 # enum
# values for enumeration 'OBUF_BYPASS_SEL'
OBUF_BYPASS_SEL__enumvalues = {
0: 'OBUF_BYPASS_DIS',
1: 'OBUF_BYPASS_EN',
}
OBUF_BYPASS_DIS = 0
OBUF_BYPASS_EN = 1
OBUF_BYPASS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OBUF_IS_HALF_RECOUT_WIDTH_SEL'
OBUF_IS_HALF_RECOUT_WIDTH_SEL__enumvalues = {
0: 'OBUF_FULL_RECOUT',
1: 'OBUF_HALF_RECOUT',
}
OBUF_FULL_RECOUT = 0
OBUF_HALF_RECOUT = 1
OBUF_IS_HALF_RECOUT_WIDTH_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OBUF_USE_FULL_BUFFER_SEL'
OBUF_USE_FULL_BUFFER_SEL__enumvalues = {
0: 'OBUF_RECOUT',
1: 'OBUF_FULL',
}
OBUF_RECOUT = 0
OBUF_FULL = 1
OBUF_USE_FULL_BUFFER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SCL_2TAP_HARDCODE'
SCL_2TAP_HARDCODE__enumvalues = {
0: 'SCL_COEF_2TAP_HARDCODE_OFF',
1: 'SCL_COEF_2TAP_HARDCODE_ON',
}
SCL_COEF_2TAP_HARDCODE_OFF = 0
SCL_COEF_2TAP_HARDCODE_ON = 1
SCL_2TAP_HARDCODE = ctypes.c_uint32 # enum
# values for enumeration 'SCL_ALPHA_COEF'
SCL_ALPHA_COEF__enumvalues = {
0: 'SCL_ALPHA_COEF_FIRST',
1: 'SCL_ALPHA_COEF_SECOND',
}
SCL_ALPHA_COEF_FIRST = 0
SCL_ALPHA_COEF_SECOND = 1
SCL_ALPHA_COEF = ctypes.c_uint32 # enum
# values for enumeration 'SCL_AUTOCAL_MODE'
SCL_AUTOCAL_MODE__enumvalues = {
0: 'AUTOCAL_MODE_OFF',
1: 'AUTOCAL_MODE_AUTOSCALE',
2: 'AUTOCAL_MODE_AUTOCENTER',
3: 'AUTOCAL_MODE_AUTOREPLICATE',
}
AUTOCAL_MODE_OFF = 0
AUTOCAL_MODE_AUTOSCALE = 1
AUTOCAL_MODE_AUTOCENTER = 2
AUTOCAL_MODE_AUTOREPLICATE = 3
SCL_AUTOCAL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SCL_BOUNDARY'
SCL_BOUNDARY__enumvalues = {
0: 'SCL_BOUNDARY_EDGE',
1: 'SCL_BOUNDARY_BLACK',
}
SCL_BOUNDARY_EDGE = 0
SCL_BOUNDARY_BLACK = 1
SCL_BOUNDARY = ctypes.c_uint32 # enum
# values for enumeration 'SCL_CHROMA_COEF'
SCL_CHROMA_COEF__enumvalues = {
0: 'SCL_CHROMA_COEF_FIRST',
1: 'SCL_CHROMA_COEF_SECOND',
}
SCL_CHROMA_COEF_FIRST = 0
SCL_CHROMA_COEF_SECOND = 1
SCL_CHROMA_COEF = ctypes.c_uint32 # enum
# values for enumeration 'SCL_COEF_FILTER_TYPE_SEL'
SCL_COEF_FILTER_TYPE_SEL__enumvalues = {
0: 'SCL_COEF_LUMA_VERT_FILTER',
1: 'SCL_COEF_LUMA_HORZ_FILTER',
2: 'SCL_COEF_CHROMA_VERT_FILTER',
3: 'SCL_COEF_CHROMA_HORZ_FILTER',
}
SCL_COEF_LUMA_VERT_FILTER = 0
SCL_COEF_LUMA_HORZ_FILTER = 1
SCL_COEF_CHROMA_VERT_FILTER = 2
SCL_COEF_CHROMA_HORZ_FILTER = 3
SCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SCL_COEF_RAM_SEL'
SCL_COEF_RAM_SEL__enumvalues = {
0: 'SCL_COEF_RAM_SEL_0',
1: 'SCL_COEF_RAM_SEL_1',
}
SCL_COEF_RAM_SEL_0 = 0
SCL_COEF_RAM_SEL_1 = 1
SCL_COEF_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SCL_SHARP_EN'
SCL_SHARP_EN__enumvalues = {
0: 'SCL_SHARP_DISABLE',
1: 'SCL_SHARP_ENABLE',
}
SCL_SHARP_DISABLE = 0
SCL_SHARP_ENABLE = 1
SCL_SHARP_EN = ctypes.c_uint32 # enum
# values for enumeration 'CMC_3DLUT_30BIT_ENUM'
CMC_3DLUT_30BIT_ENUM__enumvalues = {
0: 'CMC_3DLUT_36BIT',
1: 'CMC_3DLUT_30BIT',
}
CMC_3DLUT_36BIT = 0
CMC_3DLUT_30BIT = 1
CMC_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CMC_3DLUT_RAM_SEL'
CMC_3DLUT_RAM_SEL__enumvalues = {
0: 'CMC_RAM0_ACCESS',
1: 'CMC_RAM1_ACCESS',
2: 'CMC_RAM2_ACCESS',
3: 'CMC_RAM3_ACCESS',
}
CMC_RAM0_ACCESS = 0
CMC_RAM1_ACCESS = 1
CMC_RAM2_ACCESS = 2
CMC_RAM3_ACCESS = 3
CMC_3DLUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CMC_3DLUT_SIZE_ENUM'
CMC_3DLUT_SIZE_ENUM__enumvalues = {
0: 'CMC_3DLUT_17CUBE',
1: 'CMC_3DLUT_9CUBE',
}
CMC_3DLUT_17CUBE = 0
CMC_3DLUT_9CUBE = 1
CMC_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CMC_LUT_2_CONFIG_ENUM'
CMC_LUT_2_CONFIG_ENUM__enumvalues = {
0: 'CMC_LUT_2CFG_NO_MEMORY',
1: 'CMC_LUT_2CFG_MEMORY_A',
2: 'CMC_LUT_2CFG_MEMORY_B',
}
CMC_LUT_2CFG_NO_MEMORY = 0
CMC_LUT_2CFG_MEMORY_A = 1
CMC_LUT_2CFG_MEMORY_B = 2
CMC_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CMC_LUT_2_MODE_ENUM'
CMC_LUT_2_MODE_ENUM__enumvalues = {
0: 'CMC_LUT_2_MODE_BYPASS',
1: 'CMC_LUT_2_MODE_RAMA_LUT',
2: 'CMC_LUT_2_MODE_RAMB_LUT',
}
CMC_LUT_2_MODE_BYPASS = 0
CMC_LUT_2_MODE_RAMA_LUT = 1
CMC_LUT_2_MODE_RAMB_LUT = 2
CMC_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CMC_LUT_NUM_SEG'
CMC_LUT_NUM_SEG__enumvalues = {
0: 'CMC_SEGMENTS_1',
1: 'CMC_SEGMENTS_2',
2: 'CMC_SEGMENTS_4',
3: 'CMC_SEGMENTS_8',
4: 'CMC_SEGMENTS_16',
5: 'CMC_SEGMENTS_32',
6: 'CMC_SEGMENTS_64',
7: 'CMC_SEGMENTS_128',
}
CMC_SEGMENTS_1 = 0
CMC_SEGMENTS_2 = 1
CMC_SEGMENTS_4 = 2
CMC_SEGMENTS_8 = 3
CMC_SEGMENTS_16 = 4
CMC_SEGMENTS_32 = 5
CMC_SEGMENTS_64 = 6
CMC_SEGMENTS_128 = 7
CMC_LUT_NUM_SEG = ctypes.c_uint32 # enum
# values for enumeration 'CMC_LUT_RAM_SEL'
CMC_LUT_RAM_SEL__enumvalues = {
0: 'CMC_RAMA_ACCESS',
1: 'CMC_RAMB_ACCESS',
}
CMC_RAMA_ACCESS = 0
CMC_RAMB_ACCESS = 1
CMC_LUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CM_BYPASS'
CM_BYPASS__enumvalues = {
0: 'NON_BYPASS',
1: 'BYPASS_EN',
}
NON_BYPASS = 0
BYPASS_EN = 1
CM_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'CM_COEF_FORMAT_ENUM'
CM_COEF_FORMAT_ENUM__enumvalues = {
0: 'FIX_S2_13',
1: 'FIX_S3_12',
}
FIX_S2_13 = 0
FIX_S3_12 = 1
CM_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_DATA_SIGNED'
CM_DATA_SIGNED__enumvalues = {
0: 'UNSIGNED',
1: 'SIGNED',
}
UNSIGNED = 0
SIGNED = 1
CM_DATA_SIGNED = ctypes.c_uint32 # enum
# values for enumeration 'CM_EN'
CM_EN__enumvalues = {
0: 'CM_DISABLE',
1: 'CM_ENABLE',
}
CM_DISABLE = 0
CM_ENABLE = 1
CM_EN = ctypes.c_uint32 # enum
# values for enumeration 'CM_GAMMA_LUT_MODE_ENUM'
CM_GAMMA_LUT_MODE_ENUM__enumvalues = {
0: 'BYPASS',
1: 'RESERVED_1',
2: 'RAM_LUT',
3: 'RESERVED_3',
}
BYPASS = 0
RESERVED_1 = 1
RAM_LUT = 2
RESERVED_3 = 3
CM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_GAMMA_LUT_PWL_DISABLE_ENUM'
CM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = {
0: 'ENABLE_PWL',
1: 'DISABLE_PWL',
}
ENABLE_PWL = 0
DISABLE_PWL = 1
CM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_GAMMA_LUT_SEL_ENUM'
CM_GAMMA_LUT_SEL_ENUM__enumvalues = {
0: 'RAMA',
1: 'RAMB',
}
RAMA = 0
RAMB = 1
CM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_GAMUT_REMAP_MODE_ENUM'
CM_GAMUT_REMAP_MODE_ENUM__enumvalues = {
0: 'BYPASS_GAMUT',
1: 'GAMUT_COEF',
2: 'GAMUT_COEF_B',
}
BYPASS_GAMUT = 0
GAMUT_COEF = 1
GAMUT_COEF_B = 2
CM_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_2_CONFIG_ENUM'
CM_LUT_2_CONFIG_ENUM__enumvalues = {
0: 'LUT_2CFG_NO_MEMORY',
1: 'LUT_2CFG_MEMORY_A',
2: 'LUT_2CFG_MEMORY_B',
}
LUT_2CFG_NO_MEMORY = 0
LUT_2CFG_MEMORY_A = 1
LUT_2CFG_MEMORY_B = 2
CM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_2_MODE_ENUM'
CM_LUT_2_MODE_ENUM__enumvalues = {
0: 'LUT_2_MODE_BYPASS',
1: 'LUT_2_MODE_RAMA_LUT',
2: 'LUT_2_MODE_RAMB_LUT',
}
LUT_2_MODE_BYPASS = 0
LUT_2_MODE_RAMA_LUT = 1
LUT_2_MODE_RAMB_LUT = 2
CM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_4_CONFIG_ENUM'
CM_LUT_4_CONFIG_ENUM__enumvalues = {
0: 'LUT_4CFG_NO_MEMORY',
1: 'LUT_4CFG_ROM_A',
2: 'LUT_4CFG_ROM_B',
3: 'LUT_4CFG_MEMORY_A',
4: 'LUT_4CFG_MEMORY_B',
}
LUT_4CFG_NO_MEMORY = 0
LUT_4CFG_ROM_A = 1
LUT_4CFG_ROM_B = 2
LUT_4CFG_MEMORY_A = 3
LUT_4CFG_MEMORY_B = 4
CM_LUT_4_CONFIG_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_4_MODE_ENUM'
CM_LUT_4_MODE_ENUM__enumvalues = {
0: 'LUT_4_MODE_BYPASS',
1: 'LUT_4_MODE_ROMA_LUT',
2: 'LUT_4_MODE_ROMB_LUT',
3: 'LUT_4_MODE_RAMA_LUT',
4: 'LUT_4_MODE_RAMB_LUT',
}
LUT_4_MODE_BYPASS = 0
LUT_4_MODE_ROMA_LUT = 1
LUT_4_MODE_ROMB_LUT = 2
LUT_4_MODE_RAMA_LUT = 3
LUT_4_MODE_RAMB_LUT = 4
CM_LUT_4_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_CONFIG_MODE'
CM_LUT_CONFIG_MODE__enumvalues = {
0: 'DIFFERENT_RGB',
1: 'ALL_USE_R',
}
DIFFERENT_RGB = 0
ALL_USE_R = 1
CM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_NUM_SEG'
CM_LUT_NUM_SEG__enumvalues = {
0: 'SEGMENTS_1',
1: 'SEGMENTS_2',
2: 'SEGMENTS_4',
3: 'SEGMENTS_8',
4: 'SEGMENTS_16',
5: 'SEGMENTS_32',
6: 'SEGMENTS_64',
7: 'SEGMENTS_128',
}
SEGMENTS_1 = 0
SEGMENTS_2 = 1
SEGMENTS_4 = 2
SEGMENTS_8 = 3
SEGMENTS_16 = 4
SEGMENTS_32 = 5
SEGMENTS_64 = 6
SEGMENTS_128 = 7
CM_LUT_NUM_SEG = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_RAM_SEL'
CM_LUT_RAM_SEL__enumvalues = {
0: 'RAMA_ACCESS',
1: 'RAMB_ACCESS',
}
RAMA_ACCESS = 0
RAMB_ACCESS = 1
CM_LUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_READ_COLOR_SEL'
CM_LUT_READ_COLOR_SEL__enumvalues = {
0: 'BLUE_LUT',
1: 'GREEN_LUT',
2: 'RED_LUT',
}
BLUE_LUT = 0
GREEN_LUT = 1
RED_LUT = 2
CM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CM_LUT_READ_DBG'
CM_LUT_READ_DBG__enumvalues = {
0: 'DISABLE_DEBUG',
1: 'ENABLE_DEBUG',
}
DISABLE_DEBUG = 0
ENABLE_DEBUG = 1
CM_LUT_READ_DBG = ctypes.c_uint32 # enum
# values for enumeration 'CM_PENDING'
CM_PENDING__enumvalues = {
0: 'CM_NOT_PENDING',
1: 'CM_YES_PENDING',
}
CM_NOT_PENDING = 0
CM_YES_PENDING = 1
CM_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'CM_POST_CSC_MODE_ENUM'
CM_POST_CSC_MODE_ENUM__enumvalues = {
0: 'BYPASS_POST_CSC',
1: 'COEF_POST_CSC',
2: 'COEF_POST_CSC_B',
}
BYPASS_POST_CSC = 0
COEF_POST_CSC = 1
COEF_POST_CSC_B = 2
CM_POST_CSC_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CM_WRITE_BASE_ONLY'
CM_WRITE_BASE_ONLY__enumvalues = {
0: 'WRITE_BOTH',
1: 'WRITE_BASE_ONLY',
}
WRITE_BOTH = 0
WRITE_BASE_ONLY = 1
CM_WRITE_BASE_ONLY = ctypes.c_uint32 # enum
# values for enumeration 'CRC_CUR_SEL'
CRC_CUR_SEL__enumvalues = {
0: 'CRC_CUR_0',
1: 'CRC_CUR_1',
}
CRC_CUR_0 = 0
CRC_CUR_1 = 1
CRC_CUR_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_INTERLACE_SEL'
CRC_INTERLACE_SEL__enumvalues = {
0: 'CRC_INTERLACE_0',
1: 'CRC_INTERLACE_1',
2: 'CRC_INTERLACE_2',
3: 'CRC_INTERLACE_3',
}
CRC_INTERLACE_0 = 0
CRC_INTERLACE_1 = 1
CRC_INTERLACE_2 = 2
CRC_INTERLACE_3 = 3
CRC_INTERLACE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_IN_CUR_SEL'
CRC_IN_CUR_SEL__enumvalues = {
0: 'CRC_IN_CUR_0',
1: 'CRC_IN_CUR_1',
2: 'CRC_IN_CUR_2',
3: 'CRC_IN_CUR_3',
}
CRC_IN_CUR_0 = 0
CRC_IN_CUR_1 = 1
CRC_IN_CUR_2 = 2
CRC_IN_CUR_3 = 3
CRC_IN_CUR_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_IN_PIX_SEL'
CRC_IN_PIX_SEL__enumvalues = {
0: 'CRC_IN_PIX_0',
1: 'CRC_IN_PIX_1',
2: 'CRC_IN_PIX_2',
3: 'CRC_IN_PIX_3',
4: 'CRC_IN_PIX_4',
5: 'CRC_IN_PIX_5',
6: 'CRC_IN_PIX_6',
7: 'CRC_IN_PIX_7',
}
CRC_IN_PIX_0 = 0
CRC_IN_PIX_1 = 1
CRC_IN_PIX_2 = 2
CRC_IN_PIX_3 = 3
CRC_IN_PIX_4 = 4
CRC_IN_PIX_5 = 5
CRC_IN_PIX_6 = 6
CRC_IN_PIX_7 = 7
CRC_IN_PIX_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_SRC_SEL'
CRC_SRC_SEL__enumvalues = {
0: 'CRC_SRC_0',
1: 'CRC_SRC_1',
2: 'CRC_SRC_2',
3: 'CRC_SRC_3',
}
CRC_SRC_0 = 0
CRC_SRC_1 = 1
CRC_SRC_2 = 2
CRC_SRC_3 = 3
CRC_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CRC_STEREO_SEL'
CRC_STEREO_SEL__enumvalues = {
0: 'CRC_STEREO_0',
1: 'CRC_STEREO_1',
2: 'CRC_STEREO_2',
3: 'CRC_STEREO_3',
}
CRC_STEREO_0 = 0
CRC_STEREO_1 = 1
CRC_STEREO_2 = 2
CRC_STEREO_3 = 3
CRC_STEREO_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TEST_CLK_SEL'
TEST_CLK_SEL__enumvalues = {
0: 'TEST_CLK_SEL_0',
1: 'TEST_CLK_SEL_1',
2: 'TEST_CLK_SEL_2',
3: 'TEST_CLK_SEL_3',
4: 'TEST_CLK_SEL_4',
5: 'TEST_CLK_SEL_5',
6: 'TEST_CLK_SEL_6',
7: 'TEST_CLK_SEL_7',
}
TEST_CLK_SEL_0 = 0
TEST_CLK_SEL_1 = 1
TEST_CLK_SEL_2 = 2
TEST_CLK_SEL_3 = 3
TEST_CLK_SEL_4 = 4
TEST_CLK_SEL_5 = 5
TEST_CLK_SEL_6 = 6
TEST_CLK_SEL_7 = 7
TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_ACTIVE'
PERFCOUNTER_ACTIVE__enumvalues = {
0: 'PERFCOUNTER_IS_IDLE',
1: 'PERFCOUNTER_IS_ACTIVE',
}
PERFCOUNTER_IS_IDLE = 0
PERFCOUNTER_IS_ACTIVE = 1
PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT0_STATE'
PERFCOUNTER_CNT0_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT0_STATE_RESET',
1: 'PERFCOUNTER_CNT0_STATE_START',
2: 'PERFCOUNTER_CNT0_STATE_FREEZE',
3: 'PERFCOUNTER_CNT0_STATE_HW',
}
PERFCOUNTER_CNT0_STATE_RESET = 0
PERFCOUNTER_CNT0_STATE_START = 1
PERFCOUNTER_CNT0_STATE_FREEZE = 2
PERFCOUNTER_CNT0_STATE_HW = 3
PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT1_STATE'
PERFCOUNTER_CNT1_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT1_STATE_RESET',
1: 'PERFCOUNTER_CNT1_STATE_START',
2: 'PERFCOUNTER_CNT1_STATE_FREEZE',
3: 'PERFCOUNTER_CNT1_STATE_HW',
}
PERFCOUNTER_CNT1_STATE_RESET = 0
PERFCOUNTER_CNT1_STATE_START = 1
PERFCOUNTER_CNT1_STATE_FREEZE = 2
PERFCOUNTER_CNT1_STATE_HW = 3
PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT2_STATE'
PERFCOUNTER_CNT2_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT2_STATE_RESET',
1: 'PERFCOUNTER_CNT2_STATE_START',
2: 'PERFCOUNTER_CNT2_STATE_FREEZE',
3: 'PERFCOUNTER_CNT2_STATE_HW',
}
PERFCOUNTER_CNT2_STATE_RESET = 0
PERFCOUNTER_CNT2_STATE_START = 1
PERFCOUNTER_CNT2_STATE_FREEZE = 2
PERFCOUNTER_CNT2_STATE_HW = 3
PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT3_STATE'
PERFCOUNTER_CNT3_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT3_STATE_RESET',
1: 'PERFCOUNTER_CNT3_STATE_START',
2: 'PERFCOUNTER_CNT3_STATE_FREEZE',
3: 'PERFCOUNTER_CNT3_STATE_HW',
}
PERFCOUNTER_CNT3_STATE_RESET = 0
PERFCOUNTER_CNT3_STATE_START = 1
PERFCOUNTER_CNT3_STATE_FREEZE = 2
PERFCOUNTER_CNT3_STATE_HW = 3
PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT4_STATE'
PERFCOUNTER_CNT4_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT4_STATE_RESET',
1: 'PERFCOUNTER_CNT4_STATE_START',
2: 'PERFCOUNTER_CNT4_STATE_FREEZE',
3: 'PERFCOUNTER_CNT4_STATE_HW',
}
PERFCOUNTER_CNT4_STATE_RESET = 0
PERFCOUNTER_CNT4_STATE_START = 1
PERFCOUNTER_CNT4_STATE_FREEZE = 2
PERFCOUNTER_CNT4_STATE_HW = 3
PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT5_STATE'
PERFCOUNTER_CNT5_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT5_STATE_RESET',
1: 'PERFCOUNTER_CNT5_STATE_START',
2: 'PERFCOUNTER_CNT5_STATE_FREEZE',
3: 'PERFCOUNTER_CNT5_STATE_HW',
}
PERFCOUNTER_CNT5_STATE_RESET = 0
PERFCOUNTER_CNT5_STATE_START = 1
PERFCOUNTER_CNT5_STATE_FREEZE = 2
PERFCOUNTER_CNT5_STATE_HW = 3
PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT6_STATE'
PERFCOUNTER_CNT6_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT6_STATE_RESET',
1: 'PERFCOUNTER_CNT6_STATE_START',
2: 'PERFCOUNTER_CNT6_STATE_FREEZE',
3: 'PERFCOUNTER_CNT6_STATE_HW',
}
PERFCOUNTER_CNT6_STATE_RESET = 0
PERFCOUNTER_CNT6_STATE_START = 1
PERFCOUNTER_CNT6_STATE_FREEZE = 2
PERFCOUNTER_CNT6_STATE_HW = 3
PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNT7_STATE'
PERFCOUNTER_CNT7_STATE__enumvalues = {
0: 'PERFCOUNTER_CNT7_STATE_RESET',
1: 'PERFCOUNTER_CNT7_STATE_START',
2: 'PERFCOUNTER_CNT7_STATE_FREEZE',
3: 'PERFCOUNTER_CNT7_STATE_HW',
}
PERFCOUNTER_CNT7_STATE_RESET = 0
PERFCOUNTER_CNT7_STATE_START = 1
PERFCOUNTER_CNT7_STATE_FREEZE = 2
PERFCOUNTER_CNT7_STATE_HW = 3
PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNTL_SEL'
PERFCOUNTER_CNTL_SEL__enumvalues = {
0: 'PERFCOUNTER_CNTL_SEL_0',
1: 'PERFCOUNTER_CNTL_SEL_1',
2: 'PERFCOUNTER_CNTL_SEL_2',
3: 'PERFCOUNTER_CNTL_SEL_3',
4: 'PERFCOUNTER_CNTL_SEL_4',
5: 'PERFCOUNTER_CNTL_SEL_5',
6: 'PERFCOUNTER_CNTL_SEL_6',
7: 'PERFCOUNTER_CNTL_SEL_7',
}
PERFCOUNTER_CNTL_SEL_0 = 0
PERFCOUNTER_CNTL_SEL_1 = 1
PERFCOUNTER_CNTL_SEL_2 = 2
PERFCOUNTER_CNTL_SEL_3 = 3
PERFCOUNTER_CNTL_SEL_4 = 4
PERFCOUNTER_CNTL_SEL_5 = 5
PERFCOUNTER_CNTL_SEL_6 = 6
PERFCOUNTER_CNTL_SEL_7 = 7
PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS'
PERFCOUNTER_CNTOFF_START_DIS__enumvalues = {
0: 'PERFCOUNTER_CNTOFF_START_ENABLE',
1: 'PERFCOUNTER_CNTOFF_START_DISABLE',
}
PERFCOUNTER_CNTOFF_START_ENABLE = 0
PERFCOUNTER_CNTOFF_START_DISABLE = 1
PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE'
PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = {
0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC',
1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX',
2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN',
}
PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0
PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1
PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2
PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_CVALUE_SEL'
PERFCOUNTER_CVALUE_SEL__enumvalues = {
0: 'PERFCOUNTER_CVALUE_SEL_47_0',
1: 'PERFCOUNTER_CVALUE_SEL_15_0',
2: 'PERFCOUNTER_CVALUE_SEL_31_16',
3: 'PERFCOUNTER_CVALUE_SEL_47_32',
4: 'PERFCOUNTER_CVALUE_SEL_11_0',
5: 'PERFCOUNTER_CVALUE_SEL_23_12',
6: 'PERFCOUNTER_CVALUE_SEL_35_24',
7: 'PERFCOUNTER_CVALUE_SEL_47_36',
}
PERFCOUNTER_CVALUE_SEL_47_0 = 0
PERFCOUNTER_CVALUE_SEL_15_0 = 1
PERFCOUNTER_CVALUE_SEL_31_16 = 2
PERFCOUNTER_CVALUE_SEL_47_32 = 3
PERFCOUNTER_CVALUE_SEL_11_0 = 4
PERFCOUNTER_CVALUE_SEL_23_12 = 5
PERFCOUNTER_CVALUE_SEL_35_24 = 6
PERFCOUNTER_CVALUE_SEL_47_36 = 7
PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL'
PERFCOUNTER_HW_CNTL_SEL__enumvalues = {
0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN',
1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF',
}
PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0
PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1
PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_HW_STOP1_SEL'
PERFCOUNTER_HW_STOP1_SEL__enumvalues = {
0: 'PERFCOUNTER_HW_STOP1_0',
1: 'PERFCOUNTER_HW_STOP1_1',
}
PERFCOUNTER_HW_STOP1_0 = 0
PERFCOUNTER_HW_STOP1_1 = 1
PERFCOUNTER_HW_STOP1_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_HW_STOP2_SEL'
PERFCOUNTER_HW_STOP2_SEL__enumvalues = {
0: 'PERFCOUNTER_HW_STOP2_0',
1: 'PERFCOUNTER_HW_STOP2_1',
}
PERFCOUNTER_HW_STOP2_0 = 0
PERFCOUNTER_HW_STOP2_1 = 1
PERFCOUNTER_HW_STOP2_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_INC_MODE'
PERFCOUNTER_INC_MODE__enumvalues = {
0: 'PERFCOUNTER_INC_MODE_MULTI_BIT',
1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE',
2: 'PERFCOUNTER_INC_MODE_LSB',
3: 'PERFCOUNTER_INC_MODE_POS_EDGE',
4: 'PERFCOUNTER_INC_MODE_NEG_EDGE',
}
PERFCOUNTER_INC_MODE_MULTI_BIT = 0
PERFCOUNTER_INC_MODE_BOTH_EDGE = 1
PERFCOUNTER_INC_MODE_LSB = 2
PERFCOUNTER_INC_MODE_POS_EDGE = 3
PERFCOUNTER_INC_MODE_NEG_EDGE = 4
PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_INT_EN'
PERFCOUNTER_INT_EN__enumvalues = {
0: 'PERFCOUNTER_INT_DISABLE',
1: 'PERFCOUNTER_INT_ENABLE',
}
PERFCOUNTER_INT_DISABLE = 0
PERFCOUNTER_INT_ENABLE = 1
PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_INT_TYPE'
PERFCOUNTER_INT_TYPE__enumvalues = {
0: 'PERFCOUNTER_INT_TYPE_LEVEL',
1: 'PERFCOUNTER_INT_TYPE_PULSE',
}
PERFCOUNTER_INT_TYPE_LEVEL = 0
PERFCOUNTER_INT_TYPE_PULSE = 1
PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_OFF_MASK'
PERFCOUNTER_OFF_MASK__enumvalues = {
0: 'PERFCOUNTER_OFF_MASK_DISABLE',
1: 'PERFCOUNTER_OFF_MASK_ENABLE',
}
PERFCOUNTER_OFF_MASK_DISABLE = 0
PERFCOUNTER_OFF_MASK_ENABLE = 1
PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_RESTART_EN'
PERFCOUNTER_RESTART_EN__enumvalues = {
0: 'PERFCOUNTER_RESTART_DISABLE',
1: 'PERFCOUNTER_RESTART_ENABLE',
}
PERFCOUNTER_RESTART_DISABLE = 0
PERFCOUNTER_RESTART_ENABLE = 1
PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_RUNEN_MODE'
PERFCOUNTER_RUNEN_MODE__enumvalues = {
0: 'PERFCOUNTER_RUNEN_MODE_LEVEL',
1: 'PERFCOUNTER_RUNEN_MODE_EDGE',
}
PERFCOUNTER_RUNEN_MODE_LEVEL = 0
PERFCOUNTER_RUNEN_MODE_EDGE = 1
PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL0'
PERFCOUNTER_STATE_SEL0__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL0_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL0_LOCAL',
}
PERFCOUNTER_STATE_SEL0_GLOBAL = 0
PERFCOUNTER_STATE_SEL0_LOCAL = 1
PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL1'
PERFCOUNTER_STATE_SEL1__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL1_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL1_LOCAL',
}
PERFCOUNTER_STATE_SEL1_GLOBAL = 0
PERFCOUNTER_STATE_SEL1_LOCAL = 1
PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL2'
PERFCOUNTER_STATE_SEL2__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL2_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL2_LOCAL',
}
PERFCOUNTER_STATE_SEL2_GLOBAL = 0
PERFCOUNTER_STATE_SEL2_LOCAL = 1
PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL3'
PERFCOUNTER_STATE_SEL3__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL3_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL3_LOCAL',
}
PERFCOUNTER_STATE_SEL3_GLOBAL = 0
PERFCOUNTER_STATE_SEL3_LOCAL = 1
PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL4'
PERFCOUNTER_STATE_SEL4__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL4_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL4_LOCAL',
}
PERFCOUNTER_STATE_SEL4_GLOBAL = 0
PERFCOUNTER_STATE_SEL4_LOCAL = 1
PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL5'
PERFCOUNTER_STATE_SEL5__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL5_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL5_LOCAL',
}
PERFCOUNTER_STATE_SEL5_GLOBAL = 0
PERFCOUNTER_STATE_SEL5_LOCAL = 1
PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL6'
PERFCOUNTER_STATE_SEL6__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL6_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL6_LOCAL',
}
PERFCOUNTER_STATE_SEL6_GLOBAL = 0
PERFCOUNTER_STATE_SEL6_LOCAL = 1
PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum
# values for enumeration 'PERFCOUNTER_STATE_SEL7'
PERFCOUNTER_STATE_SEL7__enumvalues = {
0: 'PERFCOUNTER_STATE_SEL7_GLOBAL',
1: 'PERFCOUNTER_STATE_SEL7_LOCAL',
}
PERFCOUNTER_STATE_SEL7_GLOBAL = 0
PERFCOUNTER_STATE_SEL7_LOCAL = 1
PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_CNTOFF_AND_OR'
PERFMON_CNTOFF_AND_OR__enumvalues = {
0: 'PERFMON_CNTOFF_OR',
1: 'PERFMON_CNTOFF_AND',
}
PERFMON_CNTOFF_OR = 0
PERFMON_CNTOFF_AND = 1
PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_CNTOFF_INT_EN'
PERFMON_CNTOFF_INT_EN__enumvalues = {
0: 'PERFMON_CNTOFF_INT_DISABLE',
1: 'PERFMON_CNTOFF_INT_ENABLE',
}
PERFMON_CNTOFF_INT_DISABLE = 0
PERFMON_CNTOFF_INT_ENABLE = 1
PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_CNTOFF_INT_TYPE'
PERFMON_CNTOFF_INT_TYPE__enumvalues = {
0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL',
1: 'PERFMON_CNTOFF_INT_TYPE_PULSE',
}
PERFMON_CNTOFF_INT_TYPE_LEVEL = 0
PERFMON_CNTOFF_INT_TYPE_PULSE = 1
PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'PERFMON_STATE'
PERFMON_STATE__enumvalues = {
0: 'PERFMON_STATE_RESET',
1: 'PERFMON_STATE_START',
2: 'PERFMON_STATE_FREEZE',
3: 'PERFMON_STATE_HW',
}
PERFMON_STATE_RESET = 0
PERFMON_STATE_START = 1
PERFMON_STATE_FREEZE = 2
PERFMON_STATE_HW = 3
PERFMON_STATE = ctypes.c_uint32 # enum
# values for enumeration 'BIGK_FRAGMENT_SIZE'
BIGK_FRAGMENT_SIZE__enumvalues = {
0: 'VM_PG_SIZE_4KB',
1: 'VM_PG_SIZE_8KB',
2: 'VM_PG_SIZE_16KB',
3: 'VM_PG_SIZE_32KB',
4: 'VM_PG_SIZE_64KB',
5: 'VM_PG_SIZE_128KB',
6: 'VM_PG_SIZE_256KB',
7: 'VM_PG_SIZE_512KB',
8: 'VM_PG_SIZE_1024KB',
9: 'VM_PG_SIZE_2048KB',
}
VM_PG_SIZE_4KB = 0
VM_PG_SIZE_8KB = 1
VM_PG_SIZE_16KB = 2
VM_PG_SIZE_32KB = 3
VM_PG_SIZE_64KB = 4
VM_PG_SIZE_128KB = 5
VM_PG_SIZE_256KB = 6
VM_PG_SIZE_512KB = 7
VM_PG_SIZE_1024KB = 8
VM_PG_SIZE_2048KB = 9
BIGK_FRAGMENT_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'CHUNK_SIZE'
CHUNK_SIZE__enumvalues = {
0: 'CHUNK_SIZE_1KB',
1: 'CHUNK_SIZE_2KB',
2: 'CHUNK_SIZE_4KB',
3: 'CHUNK_SIZE_8KB',
4: 'CHUNK_SIZE_16KB',
5: 'CHUNK_SIZE_32KB',
6: 'CHUNK_SIZE_64KB',
}
CHUNK_SIZE_1KB = 0
CHUNK_SIZE_2KB = 1
CHUNK_SIZE_4KB = 2
CHUNK_SIZE_8KB = 3
CHUNK_SIZE_16KB = 4
CHUNK_SIZE_32KB = 5
CHUNK_SIZE_64KB = 6
CHUNK_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'COMPAT_LEVEL'
COMPAT_LEVEL__enumvalues = {
0: 'ADDR_GEN_ZERO',
1: 'ADDR_GEN_ONE',
2: 'ADDR_GEN_TWO',
3: 'ADDR_RESERVED',
}
ADDR_GEN_ZERO = 0
ADDR_GEN_ONE = 1
ADDR_GEN_TWO = 2
ADDR_RESERVED = 3
COMPAT_LEVEL = ctypes.c_uint32 # enum
# values for enumeration 'DPTE_GROUP_SIZE'
DPTE_GROUP_SIZE__enumvalues = {
0: 'DPTE_GROUP_SIZE_64B',
1: 'DPTE_GROUP_SIZE_128B',
2: 'DPTE_GROUP_SIZE_256B',
3: 'DPTE_GROUP_SIZE_512B',
4: 'DPTE_GROUP_SIZE_1024B',
5: 'DPTE_GROUP_SIZE_2048B',
}
DPTE_GROUP_SIZE_64B = 0
DPTE_GROUP_SIZE_128B = 1
DPTE_GROUP_SIZE_256B = 2
DPTE_GROUP_SIZE_512B = 3
DPTE_GROUP_SIZE_1024B = 4
DPTE_GROUP_SIZE_2048B = 5
DPTE_GROUP_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'FORCE_ONE_ROW_FOR_FRAME'
FORCE_ONE_ROW_FOR_FRAME__enumvalues = {
0: 'FORCE_ONE_ROW_FOR_FRAME_0',
1: 'FORCE_ONE_ROW_FOR_FRAME_1',
}
FORCE_ONE_ROW_FOR_FRAME_0 = 0
FORCE_ONE_ROW_FOR_FRAME_1 = 1
FORCE_ONE_ROW_FOR_FRAME = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_BLANK_EN'
HUBP_BLANK_EN__enumvalues = {
0: 'HUBP_BLANK_SW_DEASSERT',
1: 'HUBP_BLANK_SW_ASSERT',
}
HUBP_BLANK_SW_DEASSERT = 0
HUBP_BLANK_SW_ASSERT = 1
HUBP_BLANK_EN = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_IN_BLANK'
HUBP_IN_BLANK__enumvalues = {
0: 'HUBP_IN_ACTIVE',
1: 'HUBP_IN_VBLANK',
}
HUBP_IN_ACTIVE = 0
HUBP_IN_VBLANK = 1
HUBP_IN_BLANK = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_MEASURE_WIN_MODE_DCFCLK'
HUBP_MEASURE_WIN_MODE_DCFCLK__enumvalues = {
0: 'HUBP_MEASURE_WIN_MODE_DCFCLK_0',
1: 'HUBP_MEASURE_WIN_MODE_DCFCLK_1',
2: 'HUBP_MEASURE_WIN_MODE_DCFCLK_2',
3: 'HUBP_MEASURE_WIN_MODE_DCFCLK_3',
}
HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0
HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 1
HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 2
HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 3
HUBP_MEASURE_WIN_MODE_DCFCLK = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_NO_OUTSTANDING_REQ'
HUBP_NO_OUTSTANDING_REQ__enumvalues = {
0: 'OUTSTANDING_REQ',
1: 'NO_OUTSTANDING_REQ',
}
OUTSTANDING_REQ = 0
NO_OUTSTANDING_REQ = 1
HUBP_NO_OUTSTANDING_REQ = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_SOFT_RESET'
HUBP_SOFT_RESET__enumvalues = {
0: 'HUBP_SOFT_RESET_ON',
1: 'HUBP_SOFT_RESET_OFF',
}
HUBP_SOFT_RESET_ON = 0
HUBP_SOFT_RESET_OFF = 1
HUBP_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_TTU_DISABLE'
HUBP_TTU_DISABLE__enumvalues = {
0: 'HUBP_TTU_ENABLED',
1: 'HUBP_TTU_DISABLED',
}
HUBP_TTU_ENABLED = 0
HUBP_TTU_DISABLED = 1
HUBP_TTU_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_VREADY_AT_OR_AFTER_VSYNC'
HUBP_VREADY_AT_OR_AFTER_VSYNC__enumvalues = {
0: 'VREADY_BEFORE_VSYNC',
1: 'VREADY_AT_OR_AFTER_VSYNC',
}
VREADY_BEFORE_VSYNC = 0
VREADY_AT_OR_AFTER_VSYNC = 1
HUBP_VREADY_AT_OR_AFTER_VSYNC = ctypes.c_uint32 # enum
# values for enumeration 'HUBP_VTG_SEL'
HUBP_VTG_SEL__enumvalues = {
0: 'VTG_SEL_0',
1: 'VTG_SEL_1',
2: 'VTG_SEL_2',
3: 'VTG_SEL_3',
4: 'VTG_SEL_4',
5: 'VTG_SEL_5',
}
VTG_SEL_0 = 0
VTG_SEL_1 = 1
VTG_SEL_2 = 2
VTG_SEL_3 = 3
VTG_SEL_4 = 4
VTG_SEL_5 = 5
HUBP_VTG_SEL = ctypes.c_uint32 # enum
# values for enumeration 'H_MIRROR_EN'
H_MIRROR_EN__enumvalues = {
0: 'HW_MIRRORING_DISABLE',
1: 'HW_MIRRORING_ENABLE',
}
HW_MIRRORING_DISABLE = 0
HW_MIRRORING_ENABLE = 1
H_MIRROR_EN = ctypes.c_uint32 # enum
# values for enumeration 'LEGACY_PIPE_INTERLEAVE'
LEGACY_PIPE_INTERLEAVE__enumvalues = {
0: 'LEGACY_PIPE_INTERLEAVE_256B',
1: 'LEGACY_PIPE_INTERLEAVE_512B',
}
LEGACY_PIPE_INTERLEAVE_256B = 0
LEGACY_PIPE_INTERLEAVE_512B = 1
LEGACY_PIPE_INTERLEAVE = ctypes.c_uint32 # enum
# values for enumeration 'META_CHUNK_SIZE'
META_CHUNK_SIZE__enumvalues = {
0: 'META_CHUNK_SIZE_1KB',
1: 'META_CHUNK_SIZE_2KB',
2: 'META_CHUNK_SIZE_4KB',
3: 'META_CHUNK_SIZE_8KB',
}
META_CHUNK_SIZE_1KB = 0
META_CHUNK_SIZE_2KB = 1
META_CHUNK_SIZE_4KB = 2
META_CHUNK_SIZE_8KB = 3
META_CHUNK_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'META_LINEAR'
META_LINEAR__enumvalues = {
0: 'META_SURF_TILED',
1: 'META_SURF_LINEAR',
}
META_SURF_TILED = 0
META_SURF_LINEAR = 1
META_LINEAR = ctypes.c_uint32 # enum
# values for enumeration 'MIN_CHUNK_SIZE'
MIN_CHUNK_SIZE__enumvalues = {
0: 'NO_MIN_CHUNK_SIZE',
1: 'MIN_CHUNK_SIZE_256B',
2: 'MIN_CHUNK_SIZE_512B',
3: 'MIN_CHUNK_SIZE_1024B',
}
NO_MIN_CHUNK_SIZE = 0
MIN_CHUNK_SIZE_256B = 1
MIN_CHUNK_SIZE_512B = 2
MIN_CHUNK_SIZE_1024B = 3
MIN_CHUNK_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'MIN_META_CHUNK_SIZE'
MIN_META_CHUNK_SIZE__enumvalues = {
0: 'NO_MIN_META_CHUNK_SIZE',
1: 'MIN_META_CHUNK_SIZE_64B',
2: 'MIN_META_CHUNK_SIZE_128B',
3: 'MIN_META_CHUNK_SIZE_256B',
}
NO_MIN_META_CHUNK_SIZE = 0
MIN_META_CHUNK_SIZE_64B = 1
MIN_META_CHUNK_SIZE_128B = 2
MIN_META_CHUNK_SIZE_256B = 3
MIN_META_CHUNK_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_ALIGNED'
PIPE_ALIGNED__enumvalues = {
0: 'PIPE_UNALIGNED_SURF',
1: 'PIPE_ALIGNED_SURF',
}
PIPE_UNALIGNED_SURF = 0
PIPE_ALIGNED_SURF = 1
PIPE_ALIGNED = ctypes.c_uint32 # enum
# values for enumeration 'PTE_BUFFER_MODE'
PTE_BUFFER_MODE__enumvalues = {
0: 'PTE_BUFFER_MODE_0',
1: 'PTE_BUFFER_MODE_1',
}
PTE_BUFFER_MODE_0 = 0
PTE_BUFFER_MODE_1 = 1
PTE_BUFFER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PTE_ROW_HEIGHT_LINEAR'
PTE_ROW_HEIGHT_LINEAR__enumvalues = {
0: 'PTE_ROW_HEIGHT_LINEAR_8L',
1: 'PTE_ROW_HEIGHT_LINEAR_16L',
2: 'PTE_ROW_HEIGHT_LINEAR_32L',
3: 'PTE_ROW_HEIGHT_LINEAR_64L',
4: 'PTE_ROW_HEIGHT_LINEAR_128L',
5: 'PTE_ROW_HEIGHT_LINEAR_256L',
6: 'PTE_ROW_HEIGHT_LINEAR_512L',
7: 'PTE_ROW_HEIGHT_LINEAR_1024L',
}
PTE_ROW_HEIGHT_LINEAR_8L = 0
PTE_ROW_HEIGHT_LINEAR_16L = 1
PTE_ROW_HEIGHT_LINEAR_32L = 2
PTE_ROW_HEIGHT_LINEAR_64L = 3
PTE_ROW_HEIGHT_LINEAR_128L = 4
PTE_ROW_HEIGHT_LINEAR_256L = 5
PTE_ROW_HEIGHT_LINEAR_512L = 6
PTE_ROW_HEIGHT_LINEAR_1024L = 7
PTE_ROW_HEIGHT_LINEAR = ctypes.c_uint32 # enum
# values for enumeration 'ROTATION_ANGLE'
ROTATION_ANGLE__enumvalues = {
0: 'ROTATE_0_DEGREES',
1: 'ROTATE_90_DEGREES',
2: 'ROTATE_180_DEGREES',
3: 'ROTATE_270_DEGREES',
}
ROTATE_0_DEGREES = 0
ROTATE_90_DEGREES = 1
ROTATE_180_DEGREES = 2
ROTATE_270_DEGREES = 3
ROTATION_ANGLE = ctypes.c_uint32 # enum
# values for enumeration 'SWATH_HEIGHT'
SWATH_HEIGHT__enumvalues = {
0: 'SWATH_HEIGHT_1L',
1: 'SWATH_HEIGHT_2L',
2: 'SWATH_HEIGHT_4L',
3: 'SWATH_HEIGHT_8L',
4: 'SWATH_HEIGHT_16L',
}
SWATH_HEIGHT_1L = 0
SWATH_HEIGHT_2L = 1
SWATH_HEIGHT_4L = 2
SWATH_HEIGHT_8L = 3
SWATH_HEIGHT_16L = 4
SWATH_HEIGHT = ctypes.c_uint32 # enum
# values for enumeration 'USE_MALL_FOR_CURSOR'
USE_MALL_FOR_CURSOR__enumvalues = {
0: 'USE_MALL_FOR_CURSOR_0',
1: 'USE_MALL_FOR_CURSOR_1',
}
USE_MALL_FOR_CURSOR_0 = 0
USE_MALL_FOR_CURSOR_1 = 1
USE_MALL_FOR_CURSOR = ctypes.c_uint32 # enum
# values for enumeration 'USE_MALL_FOR_PSTATE_CHANGE'
USE_MALL_FOR_PSTATE_CHANGE__enumvalues = {
0: 'USE_MALL_FOR_PSTATE_CHANGE_0',
1: 'USE_MALL_FOR_PSTATE_CHANGE_1',
}
USE_MALL_FOR_PSTATE_CHANGE_0 = 0
USE_MALL_FOR_PSTATE_CHANGE_1 = 1
USE_MALL_FOR_PSTATE_CHANGE = ctypes.c_uint32 # enum
# values for enumeration 'USE_MALL_FOR_STATIC_SCREEN'
USE_MALL_FOR_STATIC_SCREEN__enumvalues = {
0: 'USE_MALL_FOR_STATIC_SCREEN_0',
1: 'USE_MALL_FOR_STATIC_SCREEN_1',
}
USE_MALL_FOR_STATIC_SCREEN_0 = 0
USE_MALL_FOR_STATIC_SCREEN_1 = 1
USE_MALL_FOR_STATIC_SCREEN = ctypes.c_uint32 # enum
# values for enumeration 'VMPG_SIZE'
VMPG_SIZE__enumvalues = {
0: 'VMPG_SIZE_4KB',
1: 'VMPG_SIZE_64KB',
}
VMPG_SIZE_4KB = 0
VMPG_SIZE_64KB = 1
VMPG_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'VM_GROUP_SIZE'
VM_GROUP_SIZE__enumvalues = {
0: 'VM_GROUP_SIZE_64B',
1: 'VM_GROUP_SIZE_128B',
2: 'VM_GROUP_SIZE_256B',
3: 'VM_GROUP_SIZE_512B',
4: 'VM_GROUP_SIZE_1024B',
5: 'VM_GROUP_SIZE_2048B',
}
VM_GROUP_SIZE_64B = 0
VM_GROUP_SIZE_128B = 1
VM_GROUP_SIZE_256B = 2
VM_GROUP_SIZE_512B = 3
VM_GROUP_SIZE_1024B = 4
VM_GROUP_SIZE_2048B = 5
VM_GROUP_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'DFQ_MIN_FREE_ENTRIES'
DFQ_MIN_FREE_ENTRIES__enumvalues = {
0: 'DFQ_MIN_FREE_ENTRIES_0',
1: 'DFQ_MIN_FREE_ENTRIES_1',
2: 'DFQ_MIN_FREE_ENTRIES_2',
3: 'DFQ_MIN_FREE_ENTRIES_3',
4: 'DFQ_MIN_FREE_ENTRIES_4',
5: 'DFQ_MIN_FREE_ENTRIES_5',
6: 'DFQ_MIN_FREE_ENTRIES_6',
7: 'DFQ_MIN_FREE_ENTRIES_7',
}
DFQ_MIN_FREE_ENTRIES_0 = 0
DFQ_MIN_FREE_ENTRIES_1 = 1
DFQ_MIN_FREE_ENTRIES_2 = 2
DFQ_MIN_FREE_ENTRIES_3 = 3
DFQ_MIN_FREE_ENTRIES_4 = 4
DFQ_MIN_FREE_ENTRIES_5 = 5
DFQ_MIN_FREE_ENTRIES_6 = 6
DFQ_MIN_FREE_ENTRIES_7 = 7
DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum
# values for enumeration 'DFQ_NUM_ENTRIES'
DFQ_NUM_ENTRIES__enumvalues = {
0: 'DFQ_NUM_ENTRIES_0',
1: 'DFQ_NUM_ENTRIES_1',
2: 'DFQ_NUM_ENTRIES_2',
3: 'DFQ_NUM_ENTRIES_3',
4: 'DFQ_NUM_ENTRIES_4',
5: 'DFQ_NUM_ENTRIES_5',
6: 'DFQ_NUM_ENTRIES_6',
7: 'DFQ_NUM_ENTRIES_7',
8: 'DFQ_NUM_ENTRIES_8',
}
DFQ_NUM_ENTRIES_0 = 0
DFQ_NUM_ENTRIES_1 = 1
DFQ_NUM_ENTRIES_2 = 2
DFQ_NUM_ENTRIES_3 = 3
DFQ_NUM_ENTRIES_4 = 4
DFQ_NUM_ENTRIES_5 = 5
DFQ_NUM_ENTRIES_6 = 6
DFQ_NUM_ENTRIES_7 = 7
DFQ_NUM_ENTRIES_8 = 8
DFQ_NUM_ENTRIES = ctypes.c_uint32 # enum
# values for enumeration 'DFQ_SIZE'
DFQ_SIZE__enumvalues = {
0: 'DFQ_SIZE_0',
1: 'DFQ_SIZE_1',
2: 'DFQ_SIZE_2',
3: 'DFQ_SIZE_3',
4: 'DFQ_SIZE_4',
5: 'DFQ_SIZE_5',
6: 'DFQ_SIZE_6',
7: 'DFQ_SIZE_7',
}
DFQ_SIZE_0 = 0
DFQ_SIZE_1 = 1
DFQ_SIZE_2 = 2
DFQ_SIZE_3 = 3
DFQ_SIZE_4 = 4
DFQ_SIZE_5 = 5
DFQ_SIZE_6 = 6
DFQ_SIZE_7 = 7
DFQ_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_VM_DONE'
DMDATA_VM_DONE__enumvalues = {
0: 'DMDATA_VM_IS_NOT_DONE',
1: 'DMDATA_VM_IS_DONE',
}
DMDATA_VM_IS_NOT_DONE = 0
DMDATA_VM_IS_DONE = 1
DMDATA_VM_DONE = ctypes.c_uint32 # enum
# values for enumeration 'EXPANSION_MODE'
EXPANSION_MODE__enumvalues = {
0: 'EXPANSION_MODE_ZERO',
1: 'EXPANSION_MODE_CONSERVATIVE',
2: 'EXPANSION_MODE_OPTIMAL',
}
EXPANSION_MODE_ZERO = 0
EXPANSION_MODE_CONSERVATIVE = 1
EXPANSION_MODE_OPTIMAL = 2
EXPANSION_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FLIP_RATE'
FLIP_RATE__enumvalues = {
0: 'FLIP_RATE_0',
1: 'FLIP_RATE_1',
2: 'FLIP_RATE_2',
3: 'FLIP_RATE_3',
4: 'FLIP_RATE_4',
5: 'FLIP_RATE_5',
6: 'FLIP_RATE_6',
7: 'FLIP_RATE_7',
}
FLIP_RATE_0 = 0
FLIP_RATE_1 = 1
FLIP_RATE_2 = 2
FLIP_RATE_3 = 3
FLIP_RATE_4 = 4
FLIP_RATE_5 = 5
FLIP_RATE_6 = 6
FLIP_RATE_7 = 7
FLIP_RATE = ctypes.c_uint32 # enum
# values for enumeration 'INT_MASK'
INT_MASK__enumvalues = {
0: 'INT_DISABLED',
1: 'INT_ENABLED',
}
INT_DISABLED = 0
INT_ENABLED = 1
INT_MASK = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_IN_FLUSH_URGENT'
PIPE_IN_FLUSH_URGENT__enumvalues = {
0: 'PIPE_IN_FLUSH_URGENT_ENABLE',
1: 'PIPE_IN_FLUSH_URGENT_DISABLE',
}
PIPE_IN_FLUSH_URGENT_ENABLE = 0
PIPE_IN_FLUSH_URGENT_DISABLE = 1
PIPE_IN_FLUSH_URGENT = ctypes.c_uint32 # enum
# values for enumeration 'PRQ_MRQ_FLUSH_URGENT'
PRQ_MRQ_FLUSH_URGENT__enumvalues = {
0: 'PRQ_MRQ_FLUSH_URGENT_ENABLE',
1: 'PRQ_MRQ_FLUSH_URGENT_DISABLE',
}
PRQ_MRQ_FLUSH_URGENT_ENABLE = 0
PRQ_MRQ_FLUSH_URGENT_DISABLE = 1
PRQ_MRQ_FLUSH_URGENT = ctypes.c_uint32 # enum
# values for enumeration 'ROW_TTU_MODE'
ROW_TTU_MODE__enumvalues = {
0: 'END_OF_ROW_MODE',
1: 'WATERMARK_MODE',
}
END_OF_ROW_MODE = 0
WATERMARK_MODE = 1
ROW_TTU_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_DCC'
SURFACE_DCC__enumvalues = {
0: 'SURFACE_IS_NOT_DCC',
1: 'SURFACE_IS_DCC',
}
SURFACE_IS_NOT_DCC = 0
SURFACE_IS_DCC = 1
SURFACE_DCC = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_DCC_IND_128B'
SURFACE_DCC_IND_128B__enumvalues = {
0: 'SURFACE_DCC_IS_NOT_IND_128B',
1: 'SURFACE_DCC_IS_IND_128B',
}
SURFACE_DCC_IS_NOT_IND_128B = 0
SURFACE_DCC_IS_IND_128B = 1
SURFACE_DCC_IND_128B = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_DCC_IND_64B'
SURFACE_DCC_IND_64B__enumvalues = {
0: 'SURFACE_DCC_IS_NOT_IND_64B',
1: 'SURFACE_DCC_IS_IND_64B',
}
SURFACE_DCC_IS_NOT_IND_64B = 0
SURFACE_DCC_IS_IND_64B = 1
SURFACE_DCC_IND_64B = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_DCC_IND_BLK'
SURFACE_DCC_IND_BLK__enumvalues = {
0: 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED',
1: 'SURFACE_DCC_BLOCK_IS_IND_64B',
2: 'SURFACE_DCC_BLOCK_IS_IND_128B',
3: 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL',
}
SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0
SURFACE_DCC_BLOCK_IS_IND_64B = 1
SURFACE_DCC_BLOCK_IS_IND_128B = 2
SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 3
SURFACE_DCC_IND_BLK = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_AWAY_INT_TYPE'
SURFACE_FLIP_AWAY_INT_TYPE__enumvalues = {
0: 'SURFACE_FLIP_AWAY_INT_LEVEL',
1: 'SURFACE_FLIP_AWAY_INT_PULSE',
}
SURFACE_FLIP_AWAY_INT_LEVEL = 0
SURFACE_FLIP_AWAY_INT_PULSE = 1
SURFACE_FLIP_AWAY_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_EXEC_DEBUG_MODE'
SURFACE_FLIP_EXEC_DEBUG_MODE__enumvalues = {
0: 'SURFACE_FLIP_EXEC_NORMAL_MODE',
1: 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE',
}
SURFACE_FLIP_EXEC_NORMAL_MODE = 0
SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 1
SURFACE_FLIP_EXEC_DEBUG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_INT_TYPE'
SURFACE_FLIP_INT_TYPE__enumvalues = {
0: 'SURFACE_FLIP_INT_LEVEL',
1: 'SURFACE_FLIP_INT_PULSE',
}
SURFACE_FLIP_INT_LEVEL = 0
SURFACE_FLIP_INT_PULSE = 1
SURFACE_FLIP_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_IN_STEREOSYNC'
SURFACE_FLIP_IN_STEREOSYNC__enumvalues = {
0: 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE',
1: 'SURFACE_FLIP_IN_STEREOSYNC_MODE',
}
SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0
SURFACE_FLIP_IN_STEREOSYNC_MODE = 1
SURFACE_FLIP_IN_STEREOSYNC = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_MODE_FOR_STEREOSYNC'
SURFACE_FLIP_MODE_FOR_STEREOSYNC__enumvalues = {
0: 'FLIP_ANY_FRAME',
1: 'FLIP_LEFT_EYE',
2: 'FLIP_RIGHT_EYE',
3: 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED',
}
FLIP_ANY_FRAME = 0
FLIP_LEFT_EYE = 1
FLIP_RIGHT_EYE = 2
SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 3
SURFACE_FLIP_MODE_FOR_STEREOSYNC = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_DISABLE'
SURFACE_FLIP_STEREO_SELECT_DISABLE__enumvalues = {
0: 'SURFACE_FLIP_STEREO_SELECT_ENABLED',
1: 'SURFACE_FLIP_STEREO_SELECT_DISABLED',
}
SURFACE_FLIP_STEREO_SELECT_ENABLED = 0
SURFACE_FLIP_STEREO_SELECT_DISABLED = 1
SURFACE_FLIP_STEREO_SELECT_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_POLARITY'
SURFACE_FLIP_STEREO_SELECT_POLARITY__enumvalues = {
0: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT',
1: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT',
}
SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0
SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 1
SURFACE_FLIP_STEREO_SELECT_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_TYPE'
SURFACE_FLIP_TYPE__enumvalues = {
0: 'SURFACE_V_FLIP',
1: 'SURFACE_I_FLIP',
}
SURFACE_V_FLIP = 0
SURFACE_I_FLIP = 1
SURFACE_FLIP_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_FLIP_VUPDATE_SKIP_NUM'
SURFACE_FLIP_VUPDATE_SKIP_NUM__enumvalues = {
0: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0',
1: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1',
2: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2',
3: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3',
4: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4',
5: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5',
6: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6',
7: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7',
8: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8',
9: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9',
10: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10',
11: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11',
12: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12',
13: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13',
14: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14',
15: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15',
}
SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0
SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 1
SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 2
SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 3
SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 4
SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 5
SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 6
SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 7
SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 8
SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 9
SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 10
SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 11
SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 12
SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 13
SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 14
SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 15
SURFACE_FLIP_VUPDATE_SKIP_NUM = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_INUSE_RAED_NO_LATCH'
SURFACE_INUSE_RAED_NO_LATCH__enumvalues = {
0: 'SURFACE_INUSE_IS_LATCHED',
1: 'SURFACE_INUSE_IS_NOT_LATCHED',
}
SURFACE_INUSE_IS_LATCHED = 0
SURFACE_INUSE_IS_NOT_LATCHED = 1
SURFACE_INUSE_RAED_NO_LATCH = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_TMZ'
SURFACE_TMZ__enumvalues = {
0: 'SURFACE_IS_NOT_TMZ',
1: 'SURFACE_IS_TMZ',
}
SURFACE_IS_NOT_TMZ = 0
SURFACE_IS_TMZ = 1
SURFACE_TMZ = ctypes.c_uint32 # enum
# values for enumeration 'SURFACE_UPDATE_LOCK'
SURFACE_UPDATE_LOCK__enumvalues = {
0: 'SURFACE_UPDATE_IS_UNLOCKED',
1: 'SURFACE_UPDATE_IS_LOCKED',
}
SURFACE_UPDATE_IS_UNLOCKED = 0
SURFACE_UPDATE_IS_LOCKED = 1
SURFACE_UPDATE_LOCK = ctypes.c_uint32 # enum
# values for enumeration 'CROSSBAR_FOR_ALPHA'
CROSSBAR_FOR_ALPHA__enumvalues = {
0: 'ALPHA_DATA_ONTO_ALPHA_PORT',
1: 'Y_G_DATA_ONTO_ALPHA_PORT',
2: 'CB_B_DATA_ONTO_ALPHA_PORT',
3: 'CR_R_DATA_ONTO_ALPHA_PORT',
}
ALPHA_DATA_ONTO_ALPHA_PORT = 0
Y_G_DATA_ONTO_ALPHA_PORT = 1
CB_B_DATA_ONTO_ALPHA_PORT = 2
CR_R_DATA_ONTO_ALPHA_PORT = 3
CROSSBAR_FOR_ALPHA = ctypes.c_uint32 # enum
# values for enumeration 'CROSSBAR_FOR_CB_B'
CROSSBAR_FOR_CB_B__enumvalues = {
0: 'ALPHA_DATA_ONTO_CB_B_PORT',
1: 'Y_G_DATA_ONTO_CB_B_PORT',
2: 'CB_B_DATA_ONTO_CB_B_PORT',
3: 'CR_R_DATA_ONTO_CB_B_PORT',
}
ALPHA_DATA_ONTO_CB_B_PORT = 0
Y_G_DATA_ONTO_CB_B_PORT = 1
CB_B_DATA_ONTO_CB_B_PORT = 2
CR_R_DATA_ONTO_CB_B_PORT = 3
CROSSBAR_FOR_CB_B = ctypes.c_uint32 # enum
# values for enumeration 'CROSSBAR_FOR_CR_R'
CROSSBAR_FOR_CR_R__enumvalues = {
0: 'ALPHA_DATA_ONTO_CR_R_PORT',
1: 'Y_G_DATA_ONTO_CR_R_PORT',
2: 'CB_B_DATA_ONTO_CR_R_PORT',
3: 'CR_R_DATA_ONTO_CR_R_PORT',
}
ALPHA_DATA_ONTO_CR_R_PORT = 0
Y_G_DATA_ONTO_CR_R_PORT = 1
CB_B_DATA_ONTO_CR_R_PORT = 2
CR_R_DATA_ONTO_CR_R_PORT = 3
CROSSBAR_FOR_CR_R = ctypes.c_uint32 # enum
# values for enumeration 'CROSSBAR_FOR_Y_G'
CROSSBAR_FOR_Y_G__enumvalues = {
0: 'ALPHA_DATA_ONTO_Y_G_PORT',
1: 'Y_G_DATA_ONTO_Y_G_PORT',
2: 'CB_B_DATA_ONTO_Y_G_PORT',
3: 'CR_R_DATA_ONTO_Y_G_PORT',
}
ALPHA_DATA_ONTO_Y_G_PORT = 0
Y_G_DATA_ONTO_Y_G_PORT = 1
CB_B_DATA_ONTO_Y_G_PORT = 2
CR_R_DATA_ONTO_Y_G_PORT = 3
CROSSBAR_FOR_Y_G = ctypes.c_uint32 # enum
# values for enumeration 'DETILE_BUFFER_PACKER_ENABLE'
DETILE_BUFFER_PACKER_ENABLE__enumvalues = {
0: 'DETILE_BUFFER_PACKER_IS_DISABLE',
1: 'DETILE_BUFFER_PACKER_IS_ENABLE',
}
DETILE_BUFFER_PACKER_IS_DISABLE = 0
DETILE_BUFFER_PACKER_IS_ENABLE = 1
DETILE_BUFFER_PACKER_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_DIS_MODE'
MEM_PWR_DIS_MODE__enumvalues = {
0: 'MEM_POWER_DIS_MODE_ENABLE',
1: 'MEM_POWER_DIS_MODE_DISABLE',
}
MEM_POWER_DIS_MODE_ENABLE = 0
MEM_POWER_DIS_MODE_DISABLE = 1
MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_FORCE_MODE'
MEM_PWR_FORCE_MODE__enumvalues = {
0: 'MEM_POWER_FORCE_MODE_OFF',
1: 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP',
2: 'MEM_POWER_FORCE_MODE_DEEP_SLEEP',
3: 'MEM_POWER_FORCE_MODE_SHUT_DOWN',
}
MEM_POWER_FORCE_MODE_OFF = 0
MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 1
MEM_POWER_FORCE_MODE_DEEP_SLEEP = 2
MEM_POWER_FORCE_MODE_SHUT_DOWN = 3
MEM_PWR_FORCE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_STATUS'
MEM_PWR_STATUS__enumvalues = {
0: 'MEM_POWER_STATUS_ON',
1: 'MEM_POWER_STATUS_LIGHT_SLEEP',
2: 'MEM_POWER_STATUS_DEEP_SLEEP',
3: 'MEM_POWER_STATUS_SHUT_DOWN',
}
MEM_POWER_STATUS_ON = 0
MEM_POWER_STATUS_LIGHT_SLEEP = 1
MEM_POWER_STATUS_DEEP_SLEEP = 2
MEM_POWER_STATUS_SHUT_DOWN = 3
MEM_PWR_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_INT_MASK_MODE'
PIPE_INT_MASK_MODE__enumvalues = {
0: 'PIPE_INT_MASK_MODE_DISABLE',
1: 'PIPE_INT_MASK_MODE_ENABLE',
}
PIPE_INT_MASK_MODE_DISABLE = 0
PIPE_INT_MASK_MODE_ENABLE = 1
PIPE_INT_MASK_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_INT_TYPE_MODE'
PIPE_INT_TYPE_MODE__enumvalues = {
0: 'PIPE_INT_TYPE_MODE_DISABLE',
1: 'PIPE_INT_TYPE_MODE_ENABLE',
}
PIPE_INT_TYPE_MODE_DISABLE = 0
PIPE_INT_TYPE_MODE_ENABLE = 1
PIPE_INT_TYPE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE'
PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = {
0: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
1: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1',
}
PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0
PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1
PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CROB_MEM_PWR_LIGHT_SLEEP_MODE'
CROB_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = {
0: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
1: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1',
2: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2',
}
CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0
CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1
CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2
CROB_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_2X_MAGNIFY'
CURSOR_2X_MAGNIFY__enumvalues = {
0: 'CURSOR_2X_MAGNIFY_IS_DISABLE',
1: 'CURSOR_2X_MAGNIFY_IS_ENABLE',
}
CURSOR_2X_MAGNIFY_IS_DISABLE = 0
CURSOR_2X_MAGNIFY_IS_ENABLE = 1
CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_ENABLE'
CURSOR_ENABLE__enumvalues = {
0: 'CURSOR_IS_DISABLE',
1: 'CURSOR_IS_ENABLE',
}
CURSOR_IS_DISABLE = 0
CURSOR_IS_ENABLE = 1
CURSOR_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_LINES_PER_CHUNK'
CURSOR_LINES_PER_CHUNK__enumvalues = {
0: 'CURSOR_LINE_PER_CHUNK_1',
1: 'CURSOR_LINE_PER_CHUNK_2',
2: 'CURSOR_LINE_PER_CHUNK_4',
3: 'CURSOR_LINE_PER_CHUNK_8',
4: 'CURSOR_LINE_PER_CHUNK_16',
}
CURSOR_LINE_PER_CHUNK_1 = 0
CURSOR_LINE_PER_CHUNK_2 = 1
CURSOR_LINE_PER_CHUNK_4 = 2
CURSOR_LINE_PER_CHUNK_8 = 3
CURSOR_LINE_PER_CHUNK_16 = 4
CURSOR_LINES_PER_CHUNK = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_MODE'
CURSOR_MODE__enumvalues = {
0: 'CURSOR_MONO_2BIT',
1: 'CURSOR_COLOR_24BIT_1BIT_AND',
2: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT',
3: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT',
4: 'CURSOR_COLOR_64BIT_FP_PREMULT',
5: 'CURSOR_COLOR_64BIT_FP_UNPREMULT',
}
CURSOR_MONO_2BIT = 0
CURSOR_COLOR_24BIT_1BIT_AND = 1
CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 2
CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3
CURSOR_COLOR_64BIT_FP_PREMULT = 4
CURSOR_COLOR_64BIT_FP_UNPREMULT = 5
CURSOR_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_EN'
CURSOR_PERFMON_LATENCY_MEASURE_EN__enumvalues = {
0: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED',
1: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED',
}
CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0
CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 1
CURSOR_PERFMON_LATENCY_MEASURE_EN = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_SEL'
CURSOR_PERFMON_LATENCY_MEASURE_SEL__enumvalues = {
0: 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY',
1: 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY',
}
CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0
CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 1
CURSOR_PERFMON_LATENCY_MEASURE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_PITCH'
CURSOR_PITCH__enumvalues = {
0: 'CURSOR_PITCH_64_PIXELS',
1: 'CURSOR_PITCH_128_PIXELS',
2: 'CURSOR_PITCH_256_PIXELS',
}
CURSOR_PITCH_64_PIXELS = 0
CURSOR_PITCH_128_PIXELS = 1
CURSOR_PITCH_256_PIXELS = 2
CURSOR_PITCH = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_REQ_MODE'
CURSOR_REQ_MODE__enumvalues = {
0: 'CURSOR_REQUEST_NORMALLY',
1: 'CURSOR_REQUEST_EARLY',
}
CURSOR_REQUEST_NORMALLY = 0
CURSOR_REQUEST_EARLY = 1
CURSOR_REQ_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_SNOOP'
CURSOR_SNOOP__enumvalues = {
0: 'CURSOR_IS_NOT_SNOOP',
1: 'CURSOR_IS_SNOOP',
}
CURSOR_IS_NOT_SNOOP = 0
CURSOR_IS_SNOOP = 1
CURSOR_SNOOP = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_STEREO_EN'
CURSOR_STEREO_EN__enumvalues = {
0: 'CURSOR_STEREO_IS_DISABLED',
1: 'CURSOR_STEREO_IS_ENABLED',
}
CURSOR_STEREO_IS_DISABLED = 0
CURSOR_STEREO_IS_ENABLED = 1
CURSOR_STEREO_EN = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_SURFACE_TMZ'
CURSOR_SURFACE_TMZ__enumvalues = {
0: 'CURSOR_SURFACE_IS_NOT_TMZ',
1: 'CURSOR_SURFACE_IS_TMZ',
}
CURSOR_SURFACE_IS_NOT_TMZ = 0
CURSOR_SURFACE_IS_TMZ = 1
CURSOR_SURFACE_TMZ = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_SYSTEM'
CURSOR_SYSTEM__enumvalues = {
0: 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS',
1: 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS',
}
CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0
CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 1
CURSOR_SYSTEM = ctypes.c_uint32 # enum
# values for enumeration 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS'
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__enumvalues = {
0: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0',
1: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1',
}
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 1
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_DONE'
DMDATA_DONE__enumvalues = {
0: 'DMDATA_NOT_SENT_TO_DIG',
1: 'DMDATA_SENT_TO_DIG',
}
DMDATA_NOT_SENT_TO_DIG = 0
DMDATA_SENT_TO_DIG = 1
DMDATA_DONE = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_MODE'
DMDATA_MODE__enumvalues = {
0: 'DMDATA_SOFTWARE_UPDATE_MODE',
1: 'DMDATA_HARDWARE_UPDATE_MODE',
}
DMDATA_SOFTWARE_UPDATE_MODE = 0
DMDATA_HARDWARE_UPDATE_MODE = 1
DMDATA_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_QOS_MODE'
DMDATA_QOS_MODE__enumvalues = {
0: 'DMDATA_QOS_LEVEL_FROM_TTU',
1: 'DMDATA_QOS_LEVEL_FROM_SOFTWARE',
}
DMDATA_QOS_LEVEL_FROM_TTU = 0
DMDATA_QOS_LEVEL_FROM_SOFTWARE = 1
DMDATA_QOS_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_REPEAT'
DMDATA_REPEAT__enumvalues = {
0: 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY',
1: 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES',
}
DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0
DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 1
DMDATA_REPEAT = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_UNDERFLOW'
DMDATA_UNDERFLOW__enumvalues = {
0: 'DMDATA_NOT_UNDERFLOW',
1: 'DMDATA_UNDERFLOWED',
}
DMDATA_NOT_UNDERFLOW = 0
DMDATA_UNDERFLOWED = 1
DMDATA_UNDERFLOW = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_UNDERFLOW_CLEAR'
DMDATA_UNDERFLOW_CLEAR__enumvalues = {
0: 'DMDATA_DONT_CLEAR',
1: 'DMDATA_CLEAR_UNDERFLOW_STATUS',
}
DMDATA_DONT_CLEAR = 0
DMDATA_CLEAR_UNDERFLOW_STATUS = 1
DMDATA_UNDERFLOW_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'DMDATA_UPDATED'
DMDATA_UPDATED__enumvalues = {
0: 'DMDATA_NOT_UPDATED',
1: 'DMDATA_WAS_UPDATED',
}
DMDATA_NOT_UPDATED = 0
DMDATA_WAS_UPDATED = 1
DMDATA_UPDATED = ctypes.c_uint32 # enum
# values for enumeration 'RESPONSE_STATUS'
RESPONSE_STATUS__enumvalues = {
0: 'OKAY',
1: 'EXOKAY',
2: 'SLVERR',
3: 'DECERR',
4: 'EARLY',
5: 'OKAY_NODATA',
6: 'PROTVIOL',
7: 'TRANSERR',
8: 'CMPTO',
12: 'CRS',
}
OKAY = 0
EXOKAY = 1
SLVERR = 2
DECERR = 3
EARLY = 4
OKAY_NODATA = 5
PROTVIOL = 6
TRANSERR = 7
CMPTO = 8
CRS = 12
RESPONSE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE'
DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = {
0: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
1: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1',
2: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2',
}
DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0
DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1
DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2
DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DCHUBBUB_MEM_PWR_DIS_MODE'
DCHUBBUB_MEM_PWR_DIS_MODE__enumvalues = {
0: 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE',
1: 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE',
}
DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0
DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 1
DCHUBBUB_MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DCHUBBUB_MEM_PWR_MODE'
DCHUBBUB_MEM_PWR_MODE__enumvalues = {
0: 'DCHUBBUB_MEM_POWER_MODE_OFF',
1: 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP',
2: 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP',
3: 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN',
}
DCHUBBUB_MEM_POWER_MODE_OFF = 0
DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 1
DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 2
DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 3
DCHUBBUB_MEM_PWR_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET'
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET'
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_ADR_VUPDATE_LOCK_SET'
MPC_CFG_ADR_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_ADR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_CFG_VUPDATE_LOCK_SET'
MPC_CFG_CFG_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_CUR_VUPDATE_LOCK_SET'
MPC_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = {
0: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE',
1: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE',
}
MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0
MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1
MPC_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_MPC_TEST_CLK_SEL'
MPC_CFG_MPC_TEST_CLK_SEL__enumvalues = {
0: 'MPC_CFG_MPC_TEST_CLK_SEL_0',
1: 'MPC_CFG_MPC_TEST_CLK_SEL_1',
2: 'MPC_CFG_MPC_TEST_CLK_SEL_2',
3: 'MPC_CFG_MPC_TEST_CLK_SEL_3',
}
MPC_CFG_MPC_TEST_CLK_SEL_0 = 0
MPC_CFG_MPC_TEST_CLK_SEL_1 = 1
MPC_CFG_MPC_TEST_CLK_SEL_2 = 2
MPC_CFG_MPC_TEST_CLK_SEL_3 = 3
MPC_CFG_MPC_TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN'
MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN__enumvalues = {
0: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE',
1: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE',
}
MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0
MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 1
MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CRC_CALC_INTERLACE_MODE'
MPC_CRC_CALC_INTERLACE_MODE__enumvalues = {
0: 'MPC_CRC_INTERLACE_MODE_TOP',
1: 'MPC_CRC_INTERLACE_MODE_BOTTOM',
2: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM',
3: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH',
}
MPC_CRC_INTERLACE_MODE_TOP = 0
MPC_CRC_INTERLACE_MODE_BOTTOM = 1
MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 2
MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 3
MPC_CRC_CALC_INTERLACE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CRC_CALC_MODE'
MPC_CRC_CALC_MODE__enumvalues = {
0: 'MPC_CRC_ONE_SHOT_MODE',
1: 'MPC_CRC_CONTINUOUS_MODE',
}
MPC_CRC_ONE_SHOT_MODE = 0
MPC_CRC_CONTINUOUS_MODE = 1
MPC_CRC_CALC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CRC_CALC_STEREO_MODE'
MPC_CRC_CALC_STEREO_MODE__enumvalues = {
0: 'MPC_CRC_STEREO_MODE_LEFT',
1: 'MPC_CRC_STEREO_MODE_RIGHT',
2: 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT',
3: 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH',
}
MPC_CRC_STEREO_MODE_LEFT = 0
MPC_CRC_STEREO_MODE_RIGHT = 1
MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 2
MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 3
MPC_CRC_CALC_STEREO_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_CRC_SOURCE_SELECT'
MPC_CRC_SOURCE_SELECT__enumvalues = {
0: 'MPC_CRC_SOURCE_SEL_DPP',
1: 'MPC_CRC_SOURCE_SEL_OPP',
2: 'MPC_CRC_SOURCE_SEL_DWB',
3: 'MPC_CRC_SOURCE_SEL_OTHER',
}
MPC_CRC_SOURCE_SEL_DPP = 0
MPC_CRC_SOURCE_SEL_OPP = 1
MPC_CRC_SOURCE_SEL_DWB = 2
MPC_CRC_SOURCE_SEL_OTHER = 3
MPC_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'MPC_DEBUG_BUS1_DATA_SELECT'
MPC_DEBUG_BUS1_DATA_SELECT__enumvalues = {
0: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG',
1: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT',
2: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1',
3: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV',
}
MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG = 0
MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT = 1
MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1 = 2
MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV = 3
MPC_DEBUG_BUS1_DATA_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'MPC_DEBUG_BUS2_DATA_SELECT'
MPC_DEBUG_BUS2_DATA_SELECT__enumvalues = {
0: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC',
1: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT',
2: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM',
3: 'MPC_DEBUG_BUS2_DATA_SELECT_RES',
}
MPC_DEBUG_BUS2_DATA_SELECT_MPCC = 0
MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT = 1
MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM = 2
MPC_DEBUG_BUS2_DATA_SELECT_RES = 3
MPC_DEBUG_BUS2_DATA_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT'
MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT__enumvalues = {
0: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID',
1: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID',
2: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID',
3: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID',
4: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA',
5: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA',
6: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1',
7: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID',
}
MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID = 0
MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID = 1
MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID = 2
MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID = 3
MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA = 4
MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA = 5
MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1 = 6
MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID = 7
MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'MPC_DEBUG_BUS_MPCC_BYTE_SELECT'
MPC_DEBUG_BUS_MPCC_BYTE_SELECT__enumvalues = {
0: 'MPC_DEBUG_BUS_MPCC_BYTE0',
1: 'MPC_DEBUG_BUS_MPCC_BYTE1',
2: 'MPC_DEBUG_BUS_MPCC_BYTE2',
3: 'MPC_DEBUG_BUS_MPCC_BYTE3',
}
MPC_DEBUG_BUS_MPCC_BYTE0 = 0
MPC_DEBUG_BUS_MPCC_BYTE1 = 1
MPC_DEBUG_BUS_MPCC_BYTE2 = 2
MPC_DEBUG_BUS_MPCC_BYTE3 = 3
MPC_DEBUG_BUS_MPCC_BYTE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OCSC_COEF_FORMAT'
MPC_OCSC_COEF_FORMAT__enumvalues = {
0: 'MPC_OCSC_COEF_FORMAT_S2_13',
1: 'MPC_OCSC_COEF_FORMAT_S3_12',
}
MPC_OCSC_COEF_FORMAT_S2_13 = 0
MPC_OCSC_COEF_FORMAT_S3_12 = 1
MPC_OCSC_COEF_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN'
MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN__enumvalues = {
0: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE',
1: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE',
}
MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0
MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 1
MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OUT_CSC_MODE'
MPC_OUT_CSC_MODE__enumvalues = {
0: 'MPC_OUT_CSC_MODE_0',
1: 'MPC_OUT_CSC_MODE_1',
2: 'MPC_OUT_CSC_MODE_2',
3: 'MPC_OUT_CSC_MODE_RSV',
}
MPC_OUT_CSC_MODE_0 = 0
MPC_OUT_CSC_MODE_1 = 1
MPC_OUT_CSC_MODE_2 = 2
MPC_OUT_CSC_MODE_RSV = 3
MPC_OUT_CSC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE'
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE__enumvalues = {
0: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS',
1: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS',
2: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS',
3: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS',
4: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS',
5: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS',
6: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS',
7: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH',
}
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 1
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 2
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 3
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 4
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 5
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 6
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 7
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPC_OUT_RATE_CONTROL_DISABLE_SET'
MPC_OUT_RATE_CONTROL_DISABLE_SET__enumvalues = {
0: 'MPC_OUT_RATE_CONTROL_SET_ENABLE',
1: 'MPC_OUT_RATE_CONTROL_SET_DISABLE',
}
MPC_OUT_RATE_CONTROL_SET_ENABLE = 0
MPC_OUT_RATE_CONTROL_SET_DISABLE = 1
MPC_OUT_RATE_CONTROL_DISABLE_SET = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_BG_COLOR_BPC'
MPCC_BG_COLOR_BPC__enumvalues = {
0: 'MPCC_BG_COLOR_BPC_8bit',
1: 'MPCC_BG_COLOR_BPC_9bit',
2: 'MPCC_BG_COLOR_BPC_10bit',
3: 'MPCC_BG_COLOR_BPC_11bit',
4: 'MPCC_BG_COLOR_BPC_12bit',
}
MPCC_BG_COLOR_BPC_8bit = 0
MPCC_BG_COLOR_BPC_9bit = 1
MPCC_BG_COLOR_BPC_10bit = 2
MPCC_BG_COLOR_BPC_11bit = 3
MPCC_BG_COLOR_BPC_12bit = 4
MPCC_BG_COLOR_BPC = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY'
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY__enumvalues = {
0: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE',
1: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE',
}
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 1
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE'
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE__enumvalues = {
0: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA',
1: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN',
2: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA',
3: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED',
}
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 2
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 3
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE'
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE__enumvalues = {
0: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE',
1: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE',
}
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 1
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE'
MPCC_CONTROL_MPCC_BOT_GAIN_MODE__enumvalues = {
0: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0',
1: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1',
}
MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0
MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 1
MPCC_CONTROL_MPCC_BOT_GAIN_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_CONTROL_MPCC_MODE'
MPCC_CONTROL_MPCC_MODE__enumvalues = {
0: 'MPCC_CONTROL_MPCC_MODE_BYPASS',
1: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH',
2: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY',
3: 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING',
}
MPCC_CONTROL_MPCC_MODE_BYPASS = 0
MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 1
MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 2
MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 3
MPCC_CONTROL_MPCC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_EN'
MPCC_SM_CONTROL_MPCC_SM_EN__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE',
1: 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE',
}
MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0
MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 1
MPCC_SM_CONTROL_MPCC_SM_EN = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT'
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE',
1: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE',
}
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 1
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL'
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE',
1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED',
2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW',
3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH',
}
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL'
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE',
1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED',
2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW',
3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH',
}
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 1
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT'
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE',
1: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE',
}
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 1
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_MODE'
MPCC_SM_CONTROL_MPCC_SM_MODE__enumvalues = {
0: 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE',
2: 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING',
4: 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING',
6: 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING',
}
MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0
MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 2
MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 4
MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6
MPCC_SM_CONTROL_MPCC_SM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN'
MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN__enumvalues = {
0: 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE',
1: 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE',
}
MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE = 0
MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE = 1
MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM'
MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = {
0: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13',
1: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12',
}
MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0
MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1
MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_GAMUT_REMAP_MODE_ENUM'
MPCC_GAMUT_REMAP_MODE_ENUM__enumvalues = {
0: 'MPCC_GAMUT_REMAP_MODE_0',
1: 'MPCC_GAMUT_REMAP_MODE_1',
2: 'MPCC_GAMUT_REMAP_MODE_2',
3: 'MPCC_GAMUT_REMAP_MODE_RSV',
}
MPCC_GAMUT_REMAP_MODE_0 = 0
MPCC_GAMUT_REMAP_MODE_1 = 1
MPCC_GAMUT_REMAP_MODE_2 = 2
MPCC_GAMUT_REMAP_MODE_RSV = 3
MPCC_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_2_CONFIG_ENUM'
MPCC_OGAM_LUT_2_CONFIG_ENUM__enumvalues = {
0: 'MPCC_OGAM_LUT_2CFG_NO_MEMORY',
1: 'MPCC_OGAM_LUT_2CFG_MEMORY_A',
2: 'MPCC_OGAM_LUT_2CFG_MEMORY_B',
}
MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0
MPCC_OGAM_LUT_2CFG_MEMORY_A = 1
MPCC_OGAM_LUT_2CFG_MEMORY_B = 2
MPCC_OGAM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_CONFIG_MODE'
MPCC_OGAM_LUT_CONFIG_MODE__enumvalues = {
0: 'MPCC_OGAM_DIFFERENT_RGB',
1: 'MPCC_OGAM_ALL_USE_R',
}
MPCC_OGAM_DIFFERENT_RGB = 0
MPCC_OGAM_ALL_USE_R = 1
MPCC_OGAM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM'
MPCC_OGAM_LUT_PWL_DISABLE_ENUM__enumvalues = {
0: 'MPCC_OGAM_ENABLE_PWL',
1: 'MPCC_OGAM_DISABLE_PWL',
}
MPCC_OGAM_ENABLE_PWL = 0
MPCC_OGAM_DISABLE_PWL = 1
MPCC_OGAM_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL'
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL__enumvalues = {
0: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA',
1: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB',
}
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 1
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_RAM_SEL'
MPCC_OGAM_LUT_RAM_SEL__enumvalues = {
0: 'MPCC_OGAM_RAMA_ACCESS',
1: 'MPCC_OGAM_RAMB_ACCESS',
}
MPCC_OGAM_RAMA_ACCESS = 0
MPCC_OGAM_RAMB_ACCESS = 1
MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_READ_COLOR_SEL'
MPCC_OGAM_LUT_READ_COLOR_SEL__enumvalues = {
0: 'MPCC_OGAM_BLUE_LUT',
1: 'MPCC_OGAM_GREEN_LUT',
2: 'MPCC_OGAM_RED_LUT',
}
MPCC_OGAM_BLUE_LUT = 0
MPCC_OGAM_GREEN_LUT = 1
MPCC_OGAM_RED_LUT = 2
MPCC_OGAM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_READ_DBG'
MPCC_OGAM_LUT_READ_DBG__enumvalues = {
0: 'MPCC_OGAM_DISABLE_DEBUG',
1: 'MPCC_OGAM_ENABLE_DEBUG',
}
MPCC_OGAM_DISABLE_DEBUG = 0
MPCC_OGAM_ENABLE_DEBUG = 1
MPCC_OGAM_LUT_READ_DBG = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_LUT_SEL_ENUM'
MPCC_OGAM_LUT_SEL_ENUM__enumvalues = {
0: 'MPCC_OGAM_RAMA',
1: 'MPCC_OGAM_RAMB',
}
MPCC_OGAM_RAMA = 0
MPCC_OGAM_RAMB = 1
MPCC_OGAM_LUT_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM'
MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM__enumvalues = {
0: 'MPCC_OGAM_MODE_0',
1: 'MPCC_OGAM_MODE_RSV1',
2: 'MPCC_OGAM_MODE_2',
3: 'MPCC_OGAM_MODE_RSV',
}
MPCC_OGAM_MODE_0 = 0
MPCC_OGAM_MODE_RSV1 = 1
MPCC_OGAM_MODE_2 = 2
MPCC_OGAM_MODE_RSV = 3
MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_NUM_SEG'
MPCC_OGAM_NUM_SEG__enumvalues = {
0: 'MPCC_OGAM_SEGMENTS_1',
1: 'MPCC_OGAM_SEGMENTS_2',
2: 'MPCC_OGAM_SEGMENTS_4',
3: 'MPCC_OGAM_SEGMENTS_8',
4: 'MPCC_OGAM_SEGMENTS_16',
5: 'MPCC_OGAM_SEGMENTS_32',
6: 'MPCC_OGAM_SEGMENTS_64',
7: 'MPCC_OGAM_SEGMENTS_128',
}
MPCC_OGAM_SEGMENTS_1 = 0
MPCC_OGAM_SEGMENTS_2 = 1
MPCC_OGAM_SEGMENTS_4 = 2
MPCC_OGAM_SEGMENTS_8 = 3
MPCC_OGAM_SEGMENTS_16 = 4
MPCC_OGAM_SEGMENTS_32 = 5
MPCC_OGAM_SEGMENTS_64 = 6
MPCC_OGAM_SEGMENTS_128 = 7
MPCC_OGAM_NUM_SEG = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN'
MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN__enumvalues = {
0: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE',
1: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE',
}
MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0
MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 1
MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_3DLUT_30BIT_ENUM'
MPCC_MCM_3DLUT_30BIT_ENUM__enumvalues = {
0: 'MPCC_MCM_3DLUT_36BIT',
1: 'MPCC_MCM_3DLUT_30BIT',
}
MPCC_MCM_3DLUT_36BIT = 0
MPCC_MCM_3DLUT_30BIT = 1
MPCC_MCM_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_3DLUT_RAM_SEL'
MPCC_MCM_3DLUT_RAM_SEL__enumvalues = {
0: 'MPCC_MCM_RAM0_ACCESS',
1: 'MPCC_MCM_RAM1_ACCESS',
2: 'MPCC_MCM_RAM2_ACCESS',
3: 'MPCC_MCM_RAM3_ACCESS',
}
MPCC_MCM_RAM0_ACCESS = 0
MPCC_MCM_RAM1_ACCESS = 1
MPCC_MCM_RAM2_ACCESS = 2
MPCC_MCM_RAM3_ACCESS = 3
MPCC_MCM_3DLUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_3DLUT_SIZE_ENUM'
MPCC_MCM_3DLUT_SIZE_ENUM__enumvalues = {
0: 'MPCC_MCM_3DLUT_17CUBE',
1: 'MPCC_MCM_3DLUT_9CUBE',
}
MPCC_MCM_3DLUT_17CUBE = 0
MPCC_MCM_3DLUT_9CUBE = 1
MPCC_MCM_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_GAMMA_LUT_MODE_ENUM'
MPCC_MCM_GAMMA_LUT_MODE_ENUM__enumvalues = {
0: 'MPCC_MCM_GAMMA_LUT_BYPASS',
1: 'MPCC_MCM_GAMMA_LUT_RESERVED_1',
2: 'MPCC_MCM_GAMMA_LUT_RAM_LUT',
3: 'MPCC_MCM_GAMMA_LUT_RESERVED_3',
}
MPCC_MCM_GAMMA_LUT_BYPASS = 0
MPCC_MCM_GAMMA_LUT_RESERVED_1 = 1
MPCC_MCM_GAMMA_LUT_RAM_LUT = 2
MPCC_MCM_GAMMA_LUT_RESERVED_3 = 3
MPCC_MCM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM'
MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = {
0: 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL',
1: 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL',
}
MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0
MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 1
MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_GAMMA_LUT_SEL_ENUM'
MPCC_MCM_GAMMA_LUT_SEL_ENUM__enumvalues = {
0: 'MPCC_MCM_GAMMA_LUT_RAMA',
1: 'MPCC_MCM_GAMMA_LUT_RAMB',
}
MPCC_MCM_GAMMA_LUT_RAMA = 0
MPCC_MCM_GAMMA_LUT_RAMB = 1
MPCC_MCM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_LUT_2_MODE_ENUM'
MPCC_MCM_LUT_2_MODE_ENUM__enumvalues = {
0: 'MPCC_MCM_LUT_2_MODE_BYPASS',
1: 'MPCC_MCM_LUT_2_MODE_RAMA_LUT',
2: 'MPCC_MCM_LUT_2_MODE_RAMB_LUT',
}
MPCC_MCM_LUT_2_MODE_BYPASS = 0
MPCC_MCM_LUT_2_MODE_RAMA_LUT = 1
MPCC_MCM_LUT_2_MODE_RAMB_LUT = 2
MPCC_MCM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_LUT_CONFIG_MODE'
MPCC_MCM_LUT_CONFIG_MODE__enumvalues = {
0: 'MPCC_MCM_LUT_DIFFERENT_RGB',
1: 'MPCC_MCM_LUT_ALL_USE_R',
}
MPCC_MCM_LUT_DIFFERENT_RGB = 0
MPCC_MCM_LUT_ALL_USE_R = 1
MPCC_MCM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_LUT_NUM_SEG'
MPCC_MCM_LUT_NUM_SEG__enumvalues = {
0: 'MPCC_MCM_LUT_SEGMENTS_1',
1: 'MPCC_MCM_LUT_SEGMENTS_2',
2: 'MPCC_MCM_LUT_SEGMENTS_4',
3: 'MPCC_MCM_LUT_SEGMENTS_8',
4: 'MPCC_MCM_LUT_SEGMENTS_16',
5: 'MPCC_MCM_LUT_SEGMENTS_32',
6: 'MPCC_MCM_LUT_SEGMENTS_64',
7: 'MPCC_MCM_LUT_SEGMENTS_128',
}
MPCC_MCM_LUT_SEGMENTS_1 = 0
MPCC_MCM_LUT_SEGMENTS_2 = 1
MPCC_MCM_LUT_SEGMENTS_4 = 2
MPCC_MCM_LUT_SEGMENTS_8 = 3
MPCC_MCM_LUT_SEGMENTS_16 = 4
MPCC_MCM_LUT_SEGMENTS_32 = 5
MPCC_MCM_LUT_SEGMENTS_64 = 6
MPCC_MCM_LUT_SEGMENTS_128 = 7
MPCC_MCM_LUT_NUM_SEG = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_LUT_RAM_SEL'
MPCC_MCM_LUT_RAM_SEL__enumvalues = {
0: 'MPCC_MCM_LUT_RAMA_ACCESS',
1: 'MPCC_MCM_LUT_RAMB_ACCESS',
}
MPCC_MCM_LUT_RAMA_ACCESS = 0
MPCC_MCM_LUT_RAMB_ACCESS = 1
MPCC_MCM_LUT_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_LUT_READ_COLOR_SEL'
MPCC_MCM_LUT_READ_COLOR_SEL__enumvalues = {
0: 'MPCC_MCM_LUT_BLUE_LUT',
1: 'MPCC_MCM_LUT_GREEN_LUT',
2: 'MPCC_MCM_LUT_RED_LUT',
}
MPCC_MCM_LUT_BLUE_LUT = 0
MPCC_MCM_LUT_GREEN_LUT = 1
MPCC_MCM_LUT_RED_LUT = 2
MPCC_MCM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_LUT_READ_DBG'
MPCC_MCM_LUT_READ_DBG__enumvalues = {
0: 'MPCC_MCM_LUT_DISABLE_DEBUG',
1: 'MPCC_MCM_LUT_ENABLE_DEBUG',
}
MPCC_MCM_LUT_DISABLE_DEBUG = 0
MPCC_MCM_LUT_ENABLE_DEBUG = 1
MPCC_MCM_LUT_READ_DBG = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_MEM_PWR_FORCE_ENUM'
MPCC_MCM_MEM_PWR_FORCE_ENUM__enumvalues = {
0: 'MPCC_MCM_MEM_PWR_FORCE_DIS',
1: 'MPCC_MCM_MEM_PWR_FORCE_LS',
2: 'MPCC_MCM_MEM_PWR_FORCE_DS',
3: 'MPCC_MCM_MEM_PWR_FORCE_SD',
}
MPCC_MCM_MEM_PWR_FORCE_DIS = 0
MPCC_MCM_MEM_PWR_FORCE_LS = 1
MPCC_MCM_MEM_PWR_FORCE_DS = 2
MPCC_MCM_MEM_PWR_FORCE_SD = 3
MPCC_MCM_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'MPCC_MCM_MEM_PWR_STATE_ENUM'
MPCC_MCM_MEM_PWR_STATE_ENUM__enumvalues = {
0: 'MPCC_MCM_MEM_PWR_STATE_ON',
1: 'MPCC_MCM_MEM_PWR_STATE_LS',
2: 'MPCC_MCM_MEM_PWR_STATE_DS',
3: 'MPCC_MCM_MEM_PWR_STATE_SD',
}
MPCC_MCM_MEM_PWR_STATE_ON = 0
MPCC_MCM_MEM_PWR_STATE_LS = 1
MPCC_MCM_MEM_PWR_STATE_DS = 2
MPCC_MCM_MEM_PWR_STATE_SD = 3
MPCC_MCM_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_BIT_DEPTH'
ENUM_DPG_BIT_DEPTH__enumvalues = {
0: 'ENUM_DPG_BIT_DEPTH_6BPC',
1: 'ENUM_DPG_BIT_DEPTH_8BPC',
2: 'ENUM_DPG_BIT_DEPTH_10BPC',
3: 'ENUM_DPG_BIT_DEPTH_12BPC',
}
ENUM_DPG_BIT_DEPTH_6BPC = 0
ENUM_DPG_BIT_DEPTH_8BPC = 1
ENUM_DPG_BIT_DEPTH_10BPC = 2
ENUM_DPG_BIT_DEPTH_12BPC = 3
ENUM_DPG_BIT_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_DYNAMIC_RANGE'
ENUM_DPG_DYNAMIC_RANGE__enumvalues = {
0: 'ENUM_DPG_DYNAMIC_RANGE_VESA',
1: 'ENUM_DPG_DYNAMIC_RANGE_CEA',
}
ENUM_DPG_DYNAMIC_RANGE_VESA = 0
ENUM_DPG_DYNAMIC_RANGE_CEA = 1
ENUM_DPG_DYNAMIC_RANGE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_EN'
ENUM_DPG_EN__enumvalues = {
0: 'ENUM_DPG_DISABLE',
1: 'ENUM_DPG_ENABLE',
}
ENUM_DPG_DISABLE = 0
ENUM_DPG_ENABLE = 1
ENUM_DPG_EN = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_FIELD_POLARITY'
ENUM_DPG_FIELD_POLARITY__enumvalues = {
0: 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD',
1: 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN',
}
ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0
ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1
ENUM_DPG_FIELD_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DPG_MODE'
ENUM_DPG_MODE__enumvalues = {
0: 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK',
1: 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK',
2: 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK',
3: 'ENUM_DPG_MODE_VERTICAL_BAR',
4: 'ENUM_DPG_MODE_HORIZONTAL_BAR',
5: 'ENUM_DPG_MODE_RGB_SINGLE_RAMP',
6: 'ENUM_DPG_MODE_RGB_DUAL_RAMP',
7: 'ENUM_DPG_MODE_RGB_XR_BIAS',
}
ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0
ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 1
ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 2
ENUM_DPG_MODE_VERTICAL_BAR = 3
ENUM_DPG_MODE_HORIZONTAL_BAR = 4
ENUM_DPG_MODE_RGB_SINGLE_RAMP = 5
ENUM_DPG_MODE_RGB_DUAL_RAMP = 6
ENUM_DPG_MODE_RGB_XR_BIAS = 7
ENUM_DPG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMTMEM_PWR_DIS_CTRL'
FMTMEM_PWR_DIS_CTRL__enumvalues = {
0: 'FMTMEM_ENABLE_MEM_PWR_CTRL',
1: 'FMTMEM_DISABLE_MEM_PWR_CTRL',
}
FMTMEM_ENABLE_MEM_PWR_CTRL = 0
FMTMEM_DISABLE_MEM_PWR_CTRL = 1
FMTMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'FMTMEM_PWR_FORCE_CTRL'
FMTMEM_PWR_FORCE_CTRL__enumvalues = {
0: 'FMTMEM_NO_FORCE_REQUEST',
1: 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST',
3: 'FMTMEM_FORCE_SHUT_DOWN_REQUEST',
}
FMTMEM_NO_FORCE_REQUEST = 0
FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 1
FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 2
FMTMEM_FORCE_SHUT_DOWN_REQUEST = 3
FMTMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL'
FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei',
1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi',
2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi',
3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED',
}
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3
FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL'
FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A',
1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B',
2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C',
3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D',
}
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3
FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL'
FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E',
1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F',
2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G',
3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED',
}
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3
FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH'
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP',
1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP',
2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP',
}
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH'
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP',
1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP',
2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP',
}
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL'
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2',
1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4',
}
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH'
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP',
1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP',
2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP',
}
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE'
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = {
0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION',
1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING',
}
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT'
FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = {
0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC',
1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC',
2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC',
3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC',
4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1',
5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2',
6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3',
7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE',
}
FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0
FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1
FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2
FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6
FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7
FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS'
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = {
0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE',
1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE',
}
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING'
FMT_CONTROL_PIXEL_ENCODING__enumvalues = {
0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444',
1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422',
2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420',
3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED',
}
FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0
FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1
FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2
FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3
FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE'
FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = {
0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP',
1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE',
2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP',
3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED',
}
FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0
FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1
FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2
FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3
FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER'
FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = {
0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR',
1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB',
}
FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0
FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1
FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum
# values for enumeration 'FMT_DEBUG_CNTL_COLOR_SELECT'
FMT_DEBUG_CNTL_COLOR_SELECT__enumvalues = {
0: 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE',
1: 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN',
2: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1',
3: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2',
}
FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0
FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 1
FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 2
FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 3
FMT_DEBUG_CNTL_COLOR_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'FMT_DYNAMIC_EXP_MODE'
FMT_DYNAMIC_EXP_MODE__enumvalues = {
0: 'FMT_DYNAMIC_EXP_MODE_10to12',
1: 'FMT_DYNAMIC_EXP_MODE_8to12',
}
FMT_DYNAMIC_EXP_MODE_10to12 = 0
FMT_DYNAMIC_EXP_MODE_8to12 = 1
FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMT_FRAME_RANDOM_ENABLE_CONTROL'
FMT_FRAME_RANDOM_ENABLE_CONTROL__enumvalues = {
0: 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME',
1: 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE',
}
FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0
FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 1
FMT_FRAME_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_POWER_STATE_ENUM'
FMT_POWER_STATE_ENUM__enumvalues = {
0: 'FMT_POWER_STATE_ENUM_ON',
1: 'FMT_POWER_STATE_ENUM_LS',
2: 'FMT_POWER_STATE_ENUM_DS',
3: 'FMT_POWER_STATE_ENUM_SD',
}
FMT_POWER_STATE_ENUM_ON = 0
FMT_POWER_STATE_ENUM_LS = 1
FMT_POWER_STATE_ENUM_DS = 2
FMT_POWER_STATE_ENUM_SD = 3
FMT_POWER_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'FMT_RGB_RANDOM_ENABLE_CONTROL'
FMT_RGB_RANDOM_ENABLE_CONTROL__enumvalues = {
0: 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE',
1: 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE',
}
FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0
FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 1
FMT_RGB_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL'
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL__enumvalues = {
0: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP',
1: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1',
2: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2',
3: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED',
}
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 1
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 2
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 3
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_SPATIAL_DITHER_MODE'
FMT_SPATIAL_DITHER_MODE__enumvalues = {
0: 'FMT_SPATIAL_DITHER_MODE_0',
1: 'FMT_SPATIAL_DITHER_MODE_1',
2: 'FMT_SPATIAL_DITHER_MODE_2',
3: 'FMT_SPATIAL_DITHER_MODE_3',
}
FMT_SPATIAL_DITHER_MODE_0 = 0
FMT_SPATIAL_DITHER_MODE_1 = 1
FMT_SPATIAL_DITHER_MODE_2 = 2
FMT_SPATIAL_DITHER_MODE_3 = 3
FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'FMT_STEREOSYNC_OVERRIDE_CONTROL'
FMT_STEREOSYNC_OVERRIDE_CONTROL__enumvalues = {
0: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0',
1: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1',
}
FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0
FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 1
FMT_STEREOSYNC_OVERRIDE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0'
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = {
0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR',
1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB',
}
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum
# values for enumeration 'OPPBUF_DISPLAY_SEGMENTATION'
OPPBUF_DISPLAY_SEGMENTATION__enumvalues = {
0: 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT',
1: 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT',
2: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT',
3: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT',
4: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT',
}
OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0
OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1
OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2
OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3
OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4
OPPBUF_DISPLAY_SEGMENTATION = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CLOCK_ENABLE_CONTROL'
OPP_PIPE_CLOCK_ENABLE_CONTROL__enumvalues = {
0: 'OPP_PIPE_CLOCK_DISABLE',
1: 'OPP_PIPE_CLOCK_ENABLE',
}
OPP_PIPE_CLOCK_DISABLE = 0
OPP_PIPE_CLOCK_ENABLE = 1
OPP_PIPE_CLOCK_ENABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL'
OPP_PIPE_DIGTIAL_BYPASS_CONTROL__enumvalues = {
0: 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE',
1: 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE',
}
OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0
OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 1
OPP_PIPE_DIGTIAL_BYPASS_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_CONT_EN'
OPP_PIPE_CRC_CONT_EN__enumvalues = {
0: 'OPP_PIPE_CRC_MODE_ONE_SHOT',
1: 'OPP_PIPE_CRC_MODE_CONTINUOUS',
}
OPP_PIPE_CRC_MODE_ONE_SHOT = 0
OPP_PIPE_CRC_MODE_CONTINUOUS = 1
OPP_PIPE_CRC_CONT_EN = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_EN'
OPP_PIPE_CRC_EN__enumvalues = {
0: 'OPP_PIPE_CRC_DISABLE',
1: 'OPP_PIPE_CRC_ENABLE',
}
OPP_PIPE_CRC_DISABLE = 0
OPP_PIPE_CRC_ENABLE = 1
OPP_PIPE_CRC_EN = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_INTERLACE_EN'
OPP_PIPE_CRC_INTERLACE_EN__enumvalues = {
0: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE',
1: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED',
}
OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0
OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 1
OPP_PIPE_CRC_INTERLACE_EN = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_INTERLACE_MODE'
OPP_PIPE_CRC_INTERLACE_MODE__enumvalues = {
0: 'OPP_PIPE_CRC_INTERLACE_MODE_TOP',
1: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM',
2: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD',
3: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD',
}
OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0
OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 1
OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 2
OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 3
OPP_PIPE_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_ONE_SHOT_PENDING'
OPP_PIPE_CRC_ONE_SHOT_PENDING__enumvalues = {
0: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING',
1: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING',
}
OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0
OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 1
OPP_PIPE_CRC_ONE_SHOT_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_PIXEL_SELECT'
OPP_PIPE_CRC_PIXEL_SELECT__enumvalues = {
0: 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS',
1: 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED',
2: 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS',
3: 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS',
}
OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0
OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 1
OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 2
OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 3
OPP_PIPE_CRC_PIXEL_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_SOURCE_SELECT'
OPP_PIPE_CRC_SOURCE_SELECT__enumvalues = {
0: 'OPP_PIPE_CRC_SOURCE_SELECT_FMT',
1: 'OPP_PIPE_CRC_SOURCE_SELECT_SFT',
}
OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0
OPP_PIPE_CRC_SOURCE_SELECT_SFT = 1
OPP_PIPE_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_STEREO_EN'
OPP_PIPE_CRC_STEREO_EN__enumvalues = {
0: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO',
1: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO',
}
OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0
OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 1
OPP_PIPE_CRC_STEREO_EN = ctypes.c_uint32 # enum
# values for enumeration 'OPP_PIPE_CRC_STEREO_MODE'
OPP_PIPE_CRC_STEREO_MODE__enumvalues = {
0: 'OPP_PIPE_CRC_STEREO_MODE_LEFT',
1: 'OPP_PIPE_CRC_STEREO_MODE_RIGHT',
2: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE',
3: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE',
}
OPP_PIPE_CRC_STEREO_MODE_LEFT = 0
OPP_PIPE_CRC_STEREO_MODE_RIGHT = 1
OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 2
OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 3
OPP_PIPE_CRC_STEREO_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OPP_ABM_DEBUG_BUS_SELECT_CONTROL'
OPP_ABM_DEBUG_BUS_SELECT_CONTROL__enumvalues = {
0: 'DEBUG_BUS_SELECT_ABM0',
1: 'DEBUG_BUS_SELECT_ABM1',
2: 'DEBUG_BUS_SELECT_ABM2',
3: 'DEBUG_BUS_SELECT_ABM3',
4: 'DEBUG_BUS_SELECT_ABM_RESERVED0',
5: 'DEBUG_BUS_SELECT_ABM_RESERVED1',
}
DEBUG_BUS_SELECT_ABM0 = 0
DEBUG_BUS_SELECT_ABM1 = 1
DEBUG_BUS_SELECT_ABM2 = 2
DEBUG_BUS_SELECT_ABM3 = 3
DEBUG_BUS_SELECT_ABM_RESERVED0 = 4
DEBUG_BUS_SELECT_ABM_RESERVED1 = 5
OPP_ABM_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_DPG_DEBUG_BUS_SELECT_CONTROL'
OPP_DPG_DEBUG_BUS_SELECT_CONTROL__enumvalues = {
0: 'DEBUG_BUS_SELECT_DPG0',
1: 'DEBUG_BUS_SELECT_DPG1',
2: 'DEBUG_BUS_SELECT_DPG2',
3: 'DEBUG_BUS_SELECT_DPG3',
4: 'DEBUG_BUS_SELECT_DPG_RESERVED0',
5: 'DEBUG_BUS_SELECT_DPG_RESERVED1',
}
DEBUG_BUS_SELECT_DPG0 = 0
DEBUG_BUS_SELECT_DPG1 = 1
DEBUG_BUS_SELECT_DPG2 = 2
DEBUG_BUS_SELECT_DPG3 = 3
DEBUG_BUS_SELECT_DPG_RESERVED0 = 4
DEBUG_BUS_SELECT_DPG_RESERVED1 = 5
OPP_DPG_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_FMT_DEBUG_BUS_SELECT_CONTROL'
OPP_FMT_DEBUG_BUS_SELECT_CONTROL__enumvalues = {
0: 'DEBUG_BUS_SELECT_FMT0',
1: 'DEBUG_BUS_SELECT_FMT1',
2: 'DEBUG_BUS_SELECT_FMT2',
3: 'DEBUG_BUS_SELECT_FMT3',
4: 'DEBUG_BUS_SELECT_FMT_RESERVED0',
5: 'DEBUG_BUS_SELECT_FMT_RESERVED1',
}
DEBUG_BUS_SELECT_FMT0 = 0
DEBUG_BUS_SELECT_FMT1 = 1
DEBUG_BUS_SELECT_FMT2 = 2
DEBUG_BUS_SELECT_FMT3 = 3
DEBUG_BUS_SELECT_FMT_RESERVED0 = 4
DEBUG_BUS_SELECT_FMT_RESERVED1 = 5
OPP_FMT_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL'
OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL__enumvalues = {
0: 'DEBUG_BUS_SELECT_OPPBUF0',
1: 'DEBUG_BUS_SELECT_OPPBUF1',
2: 'DEBUG_BUS_SELECT_OPPBUF2',
3: 'DEBUG_BUS_SELECT_OPPBUF3',
4: 'DEBUG_BUS_SELECT_OPPBUF_RESERVED0',
5: 'DEBUG_BUS_SELECT_OPPBUF_RESERVED1',
}
DEBUG_BUS_SELECT_OPPBUF0 = 0
DEBUG_BUS_SELECT_OPPBUF1 = 1
DEBUG_BUS_SELECT_OPPBUF2 = 2
DEBUG_BUS_SELECT_OPPBUF3 = 3
DEBUG_BUS_SELECT_OPPBUF_RESERVED0 = 4
DEBUG_BUS_SELECT_OPPBUF_RESERVED1 = 5
OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL'
OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL__enumvalues = {
0: 'DEBUG_BUS_SELECT_OPP_PIPE0',
1: 'DEBUG_BUS_SELECT_OPP_PIPE1',
2: 'DEBUG_BUS_SELECT_OPP_PIPE2',
3: 'DEBUG_BUS_SELECT_OPP_PIPE3',
4: 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0',
5: 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1',
}
DEBUG_BUS_SELECT_OPP_PIPE0 = 0
DEBUG_BUS_SELECT_OPP_PIPE1 = 1
DEBUG_BUS_SELECT_OPP_PIPE2 = 2
DEBUG_BUS_SELECT_OPP_PIPE3 = 3
DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0 = 4
DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1 = 5
OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_TEST_CLK_SEL_CONTROL'
OPP_TEST_CLK_SEL_CONTROL__enumvalues = {
0: 'OPP_TEST_CLK_SEL_DISPCLK_P',
1: 'OPP_TEST_CLK_SEL_DISPCLK_R',
2: 'OPP_TEST_CLK_SEL_DISPCLK_ABM0',
3: 'OPP_TEST_CLK_SEL_DISPCLK_ABM1',
4: 'OPP_TEST_CLK_SEL_DISPCLK_ABM2',
5: 'OPP_TEST_CLK_SEL_DISPCLK_ABM3',
6: 'OPP_TEST_CLK_SEL_RESERVED0',
7: 'OPP_TEST_CLK_SEL_RESERVED1',
8: 'OPP_TEST_CLK_SEL_DISPCLK_OPP0',
9: 'OPP_TEST_CLK_SEL_DISPCLK_OPP1',
10: 'OPP_TEST_CLK_SEL_DISPCLK_OPP2',
11: 'OPP_TEST_CLK_SEL_DISPCLK_OPP3',
12: 'OPP_TEST_CLK_SEL_RESERVED2',
13: 'OPP_TEST_CLK_SEL_RESERVED3',
}
OPP_TEST_CLK_SEL_DISPCLK_P = 0
OPP_TEST_CLK_SEL_DISPCLK_R = 1
OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 2
OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 3
OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 4
OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 5
OPP_TEST_CLK_SEL_RESERVED0 = 6
OPP_TEST_CLK_SEL_RESERVED1 = 7
OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 8
OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 9
OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 10
OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 11
OPP_TEST_CLK_SEL_RESERVED2 = 12
OPP_TEST_CLK_SEL_RESERVED3 = 13
OPP_TEST_CLK_SEL_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OPP_TOP_CLOCK_ENABLE_STATUS'
OPP_TOP_CLOCK_ENABLE_STATUS__enumvalues = {
0: 'OPP_TOP_CLOCK_DISABLED_STATUS',
1: 'OPP_TOP_CLOCK_ENABLED_STATUS',
}
OPP_TOP_CLOCK_DISABLED_STATUS = 0
OPP_TOP_CLOCK_ENABLED_STATUS = 1
OPP_TOP_CLOCK_ENABLE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'OPP_TOP_CLOCK_GATING_CONTROL'
OPP_TOP_CLOCK_GATING_CONTROL__enumvalues = {
0: 'OPP_TOP_CLOCK_GATING_ENABLED',
1: 'OPP_TOP_CLOCK_GATING_DISABLED',
}
OPP_TOP_CLOCK_GATING_ENABLED = 0
OPP_TOP_CLOCK_GATING_DISABLED = 1
OPP_TOP_CLOCK_GATING_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DSCRM_EN'
ENUM_DSCRM_EN__enumvalues = {
0: 'ENUM_DSCRM_DISABLE',
1: 'ENUM_DSCRM_ENABLE',
}
ENUM_DSCRM_DISABLE = 0
ENUM_DSCRM_ENABLE = 1
ENUM_DSCRM_EN = ctypes.c_uint32 # enum
# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK'
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = {
0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE',
1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE',
}
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum
# values for enumeration 'MASTER_UPDATE_LOCK_SEL'
MASTER_UPDATE_LOCK_SEL__enumvalues = {
0: 'MASTER_UPDATE_LOCK_SEL_0',
1: 'MASTER_UPDATE_LOCK_SEL_1',
2: 'MASTER_UPDATE_LOCK_SEL_2',
3: 'MASTER_UPDATE_LOCK_SEL_3',
4: 'MASTER_UPDATE_LOCK_SEL_RESERVED4',
5: 'MASTER_UPDATE_LOCK_SEL_RESERVED5',
}
MASTER_UPDATE_LOCK_SEL_0 = 0
MASTER_UPDATE_LOCK_SEL_1 = 1
MASTER_UPDATE_LOCK_SEL_2 = 2
MASTER_UPDATE_LOCK_SEL_3 = 3
MASTER_UPDATE_LOCK_SEL_RESERVED4 = 4
MASTER_UPDATE_LOCK_SEL_RESERVED5 = 5
MASTER_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE'
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = {
0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH',
1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP',
2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM',
3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED',
}
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 1
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 2
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN'
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN__enumvalues = {
0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE',
1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE',
}
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 1
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB'
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB__enumvalues = {
0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE',
1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE',
}
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 1
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum
# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR'
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = {
0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE',
1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE',
}
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE'
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = {
0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH',
1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE',
2: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE',
3: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED',
}
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3
OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL'
OTG_CONTROL_OTG_DISABLE_POINT_CNTL__enumvalues = {
0: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE',
1: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT',
2: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE',
3: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST',
}
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 2
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 3
OTG_CONTROL_OTG_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL'
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL__enumvalues = {
0: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL',
1: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP',
}
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 1
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY'
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY__enumvalues = {
0: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE',
1: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE',
}
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 1
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_MASTER_EN'
OTG_CONTROL_OTG_MASTER_EN__enumvalues = {
0: 'OTG_CONTROL_OTG_MASTER_EN_FALSE',
1: 'OTG_CONTROL_OTG_MASTER_EN_TRUE',
}
OTG_CONTROL_OTG_MASTER_EN_FALSE = 0
OTG_CONTROL_OTG_MASTER_EN_TRUE = 1
OTG_CONTROL_OTG_MASTER_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_OUT_MUX'
OTG_CONTROL_OTG_OUT_MUX__enumvalues = {
0: 'OTG_CONTROL_OTG_OUT_MUX_0',
1: 'OTG_CONTROL_OTG_OUT_MUX_1',
2: 'OTG_CONTROL_OTG_OUT_MUX_2',
}
OTG_CONTROL_OTG_OUT_MUX_0 = 0
OTG_CONTROL_OTG_OUT_MUX_1 = 1
OTG_CONTROL_OTG_OUT_MUX_2 = 2
OTG_CONTROL_OTG_OUT_MUX = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CONTROL_OTG_START_POINT_CNTL'
OTG_CONTROL_OTG_START_POINT_CNTL__enumvalues = {
0: 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL',
1: 'OTG_CONTROL_OTG_START_POINT_CNTL_DP',
}
OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0
OTG_CONTROL_OTG_START_POINT_CNTL_DP = 1
OTG_CONTROL_OTG_START_POINT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN'
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN__enumvalues = {
0: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE',
1: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE',
}
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 1
OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC1_EN'
OTG_CRC_CNTL_OTG_CRC1_EN__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE',
1: 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE',
}
OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0
OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 1
OTG_CRC_CNTL_OTG_CRC1_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_EN'
OTG_CRC_CNTL_OTG_CRC_CONT_EN__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE',
1: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE',
}
OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0
OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 1
OTG_CRC_CNTL_OTG_CRC_CONT_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE'
OTG_CRC_CNTL_OTG_CRC_CONT_MODE__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET',
1: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET',
}
OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0
OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 1
OTG_CRC_CNTL_OTG_CRC_CONT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_EN'
OTG_CRC_CNTL_OTG_CRC_EN__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE',
1: 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE',
}
OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0
OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 1
OTG_CRC_CNTL_OTG_CRC_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE'
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP',
1: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM',
2: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM',
3: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD',
}
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 1
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 3
OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE'
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT',
1: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT',
2: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES',
3: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS',
}
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 1
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 2
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 3
OTG_CRC_CNTL_OTG_CRC_STEREO_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS'
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE',
1: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE',
}
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1
OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT'
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB',
1: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B',
2: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB',
3: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B',
4: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB',
5: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B',
6: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB',
7: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B',
}
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 1
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 2
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 3
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 4
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 5
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 6
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 7
OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT'
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT__enumvalues = {
0: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB',
1: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B',
2: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB',
3: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B',
4: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB',
5: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B',
6: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB',
7: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B',
}
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 1
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 2
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 3
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 4
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 5
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 6
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 7
OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DIG_UPDATE_VCOUNT_MODE'
OTG_DIG_UPDATE_VCOUNT_MODE__enumvalues = {
0: 'OTG_DIG_UPDATE_VCOUNT_0',
1: 'OTG_DIG_UPDATE_VCOUNT_1',
}
OTG_DIG_UPDATE_VCOUNT_0 = 0
OTG_DIG_UPDATE_VCOUNT_1 = 1
OTG_DIG_UPDATE_VCOUNT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE'
OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE__enumvalues = {
0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0',
1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1',
2: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2',
3: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3',
}
OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0
OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 1
OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 2
OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 3
OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY'
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY__enumvalues = {
0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE',
1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE',
}
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 1
OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME'
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME__enumvalues = {
0: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME',
1: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME',
2: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME',
3: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME',
}
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 1
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 2
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 3
OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN'
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN__enumvalues = {
0: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE',
1: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE',
}
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 1
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY'
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY__enumvalues = {
0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE',
1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE',
}
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 1
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY'
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY__enumvalues = {
0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE',
1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE',
}
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 1
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT'
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT__enumvalues = {
0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0',
1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1',
2: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA',
3: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB',
4: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC',
5: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD',
6: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE',
7: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF',
8: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1',
9: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2',
10: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA',
11: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK',
12: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA',
13: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK',
14: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
15: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED',
16: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK',
17: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC',
18: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA',
19: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB',
}
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 1
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 2
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 3
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 4
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 5
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 6
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 7
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 8
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 9
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 10
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 11
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 12
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 13
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 14
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 15
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 16
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 17
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 18
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 19
OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK'
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK__enumvalues = {
0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE',
1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE',
}
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 1
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR'
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR__enumvalues = {
0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE',
1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE',
}
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 1
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE'
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE__enumvalues = {
0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE',
1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT',
2: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT',
3: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED',
}
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 1
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 3
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL'
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = {
0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE',
1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE',
}
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL'
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL__enumvalues = {
0: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0',
1: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1',
2: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2',
3: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3',
4: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4',
5: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5',
}
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 1
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 2
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 3
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 4
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 5
OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL'
OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL__enumvalues = {
0: 'DIG_UPDATE_EYE_SEL_BOTH',
1: 'DIG_UPDATE_EYE_SEL_LEFT',
2: 'DIG_UPDATE_EYE_SEL_RIGHT',
}
DIG_UPDATE_EYE_SEL_BOTH = 0
DIG_UPDATE_EYE_SEL_LEFT = 1
DIG_UPDATE_EYE_SEL_RIGHT = 2
OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL'
OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL__enumvalues = {
0: 'DIG_UPDATE_FIELD_SEL_BOTH',
1: 'DIG_UPDATE_FIELD_SEL_TOP',
2: 'DIG_UPDATE_FIELD_SEL_BOTTOM',
3: 'DIG_UPDATE_FIELD_SEL_RESERVED',
}
DIG_UPDATE_FIELD_SEL_BOTH = 0
DIG_UPDATE_FIELD_SEL_TOP = 1
DIG_UPDATE_FIELD_SEL_BOTTOM = 2
DIG_UPDATE_FIELD_SEL_RESERVED = 3
OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD'
OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD__enumvalues = {
0: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH',
1: 'MASTER_UPDATE_LOCK_DB_FIELD_TOP',
2: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM',
3: 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED',
}
MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0
MASTER_UPDATE_LOCK_DB_FIELD_TOP = 1
MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 2
MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 3
OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL'
OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL__enumvalues = {
0: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH',
1: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT',
2: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT',
3: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED',
}
MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0
MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 1
MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 2
MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 3
OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GLOBAL_UPDATE_LOCK_EN'
OTG_GLOBAL_UPDATE_LOCK_EN__enumvalues = {
0: 'OTG_GLOBAL_UPDATE_LOCK_DISABLE',
1: 'OTG_GLOBAL_UPDATE_LOCK_ENABLE',
}
OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0
OTG_GLOBAL_UPDATE_LOCK_ENABLE = 1
OTG_GLOBAL_UPDATE_LOCK_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_GSL_MASTER_MODE'
OTG_GSL_MASTER_MODE__enumvalues = {
0: 'OTG_GSL_MASTER_MODE_0',
1: 'OTG_GSL_MASTER_MODE_1',
2: 'OTG_GSL_MASTER_MODE_2',
3: 'OTG_GSL_MASTER_MODE_3',
}
OTG_GSL_MASTER_MODE_0 = 0
OTG_GSL_MASTER_MODE_1 = 1
OTG_GSL_MASTER_MODE_2 = 2
OTG_GSL_MASTER_MODE_3 = 3
OTG_GSL_MASTER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_HORZ_REPETITION_COUNT'
OTG_HORZ_REPETITION_COUNT__enumvalues = {
0: 'OTG_HORZ_REPETITION_COUNT_0',
1: 'OTG_HORZ_REPETITION_COUNT_1',
2: 'OTG_HORZ_REPETITION_COUNT_2',
3: 'OTG_HORZ_REPETITION_COUNT_3',
4: 'OTG_HORZ_REPETITION_COUNT_4',
5: 'OTG_HORZ_REPETITION_COUNT_5',
6: 'OTG_HORZ_REPETITION_COUNT_6',
7: 'OTG_HORZ_REPETITION_COUNT_7',
8: 'OTG_HORZ_REPETITION_COUNT_8',
9: 'OTG_HORZ_REPETITION_COUNT_9',
10: 'OTG_HORZ_REPETITION_COUNT_10',
11: 'OTG_HORZ_REPETITION_COUNT_11',
12: 'OTG_HORZ_REPETITION_COUNT_12',
13: 'OTG_HORZ_REPETITION_COUNT_13',
14: 'OTG_HORZ_REPETITION_COUNT_14',
15: 'OTG_HORZ_REPETITION_COUNT_15',
}
OTG_HORZ_REPETITION_COUNT_0 = 0
OTG_HORZ_REPETITION_COUNT_1 = 1
OTG_HORZ_REPETITION_COUNT_2 = 2
OTG_HORZ_REPETITION_COUNT_3 = 3
OTG_HORZ_REPETITION_COUNT_4 = 4
OTG_HORZ_REPETITION_COUNT_5 = 5
OTG_HORZ_REPETITION_COUNT_6 = 6
OTG_HORZ_REPETITION_COUNT_7 = 7
OTG_HORZ_REPETITION_COUNT_8 = 8
OTG_HORZ_REPETITION_COUNT_9 = 9
OTG_HORZ_REPETITION_COUNT_10 = 10
OTG_HORZ_REPETITION_COUNT_11 = 11
OTG_HORZ_REPETITION_COUNT_12 = 12
OTG_HORZ_REPETITION_COUNT_13 = 13
OTG_HORZ_REPETITION_COUNT_14 = 14
OTG_HORZ_REPETITION_COUNT_15 = 15
OTG_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_H_SYNC_A_POL'
OTG_H_SYNC_A_POL__enumvalues = {
0: 'OTG_H_SYNC_A_POL_HIGH',
1: 'OTG_H_SYNC_A_POL_LOW',
}
OTG_H_SYNC_A_POL_HIGH = 0
OTG_H_SYNC_A_POL_LOW = 1
OTG_H_SYNC_A_POL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_H_TIMING_DIV_MODE'
OTG_H_TIMING_DIV_MODE__enumvalues = {
0: 'OTG_H_TIMING_DIV_MODE_NO_DIV',
1: 'OTG_H_TIMING_DIV_MODE_DIV_BY2',
2: 'OTG_H_TIMING_DIV_MODE_RESERVED',
3: 'OTG_H_TIMING_DIV_MODE_DIV_BY4',
}
OTG_H_TIMING_DIV_MODE_NO_DIV = 0
OTG_H_TIMING_DIV_MODE_DIV_BY2 = 1
OTG_H_TIMING_DIV_MODE_RESERVED = 2
OTG_H_TIMING_DIV_MODE_DIV_BY4 = 3
OTG_H_TIMING_DIV_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_H_TIMING_DIV_MODE_MANUAL'
OTG_H_TIMING_DIV_MODE_MANUAL__enumvalues = {
0: 'OTG_H_TIMING_DIV_MODE_AUTO',
1: 'OTG_H_TIMING_DIV_MODE_NOAUTO',
}
OTG_H_TIMING_DIV_MODE_AUTO = 0
OTG_H_TIMING_DIV_MODE_NOAUTO = 1
OTG_H_TIMING_DIV_MODE_MANUAL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE'
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE__enumvalues = {
0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE',
1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE',
}
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 1
OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD'
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD__enumvalues = {
0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT',
1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM',
2: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP',
3: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2',
}
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 1
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 2
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3
OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK'
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE'
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE__enumvalues = {
0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE',
1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE',
}
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 1
OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE'
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = {
0: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE',
1: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE',
}
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1
OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_MASTER_UPDATE_LOCK_DB_EN'
OTG_MASTER_UPDATE_LOCK_DB_EN__enumvalues = {
0: 'OTG_MASTER_UPDATE_LOCK_DISABLE',
1: 'OTG_MASTER_UPDATE_LOCK_ENABLE',
}
OTG_MASTER_UPDATE_LOCK_DISABLE = 0
OTG_MASTER_UPDATE_LOCK_ENABLE = 1
OTG_MASTER_UPDATE_LOCK_DB_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_MASTER_UPDATE_LOCK_GSL_EN'
OTG_MASTER_UPDATE_LOCK_GSL_EN__enumvalues = {
0: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE',
1: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE',
}
OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0
OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 1
OTG_MASTER_UPDATE_LOCK_GSL_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE'
OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE__enumvalues = {
0: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0',
1: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1',
}
OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0
OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 1
OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL'
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = {
0: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE',
1: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA',
2: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB',
3: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED',
}
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3
OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR'
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR__enumvalues = {
0: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE',
1: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE',
}
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 1
OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR'
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE',
}
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 1
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE'
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE',
}
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 1
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE'
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE',
}
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 1
OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE'
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE',
}
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 1
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE'
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = {
0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF',
1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON',
}
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1
OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL'
OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL__enumvalues = {
0: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE',
1: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE',
}
OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0
OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 1
OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EN'
OTG_STEREO_CONTROL_OTG_STEREO_EN__enumvalues = {
0: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE',
1: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE',
}
OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0
OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 1
OTG_STEREO_CONTROL_OTG_STEREO_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY'
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY__enumvalues = {
0: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE',
1: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE',
}
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 1
OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY'
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = {
0: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE',
1: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE',
}
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1
OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE'
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE__enumvalues = {
0: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO',
1: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT',
2: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT',
3: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED',
}
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 1
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 2
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 3
OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR'
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE',
}
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 1
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT'
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE',
2: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA',
3: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB',
4: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA',
5: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1',
6: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC',
7: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD',
}
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 1
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 2
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 3
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 4
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 5
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 6
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 7
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN'
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE',
}
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 1
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT'
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1',
2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2',
3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3',
4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4',
5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5',
}
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 1
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 2
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 3
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 4
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 5
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT'
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT__enumvalues = {
0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0',
1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN',
2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN',
3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN',
4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN',
5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN',
6: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN',
7: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN',
8: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN',
9: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN',
10: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN',
11: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1',
12: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2',
13: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN',
14: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14',
15: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK',
16: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP',
17: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING',
18: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF',
19: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC',
20: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC',
21: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL',
22: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
23: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1',
24: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING',
}
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 1
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 2
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 3
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 4
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 5
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 6
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 7
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 8
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 9
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 10
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 11
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 12
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 13
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 14
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 15
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 16
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 17
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 18
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 19
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 20
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 23
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 24
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL'
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__enumvalues = {
0: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0',
1: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1',
2: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2',
3: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3',
}
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 1
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 2
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 3
OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_FREQUENCY_SELECT'
OTG_TRIGA_FREQUENCY_SELECT__enumvalues = {
0: 'OTG_TRIGA_FREQUENCY_SELECT_0',
1: 'OTG_TRIGA_FREQUENCY_SELECT_1',
2: 'OTG_TRIGA_FREQUENCY_SELECT_2',
3: 'OTG_TRIGA_FREQUENCY_SELECT_3',
}
OTG_TRIGA_FREQUENCY_SELECT_0 = 0
OTG_TRIGA_FREQUENCY_SELECT_1 = 1
OTG_TRIGA_FREQUENCY_SELECT_2 = 2
OTG_TRIGA_FREQUENCY_SELECT_3 = 3
OTG_TRIGA_FREQUENCY_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL'
OTG_TRIGA_RISING_EDGE_DETECT_CNTL__enumvalues = {
0: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0',
1: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1',
2: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2',
3: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3',
}
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 1
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 2
OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 3
OTG_TRIGA_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR'
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE',
}
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 1
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT'
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE',
2: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA',
3: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB',
4: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA',
5: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1',
6: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC',
7: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD',
}
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 1
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 2
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 3
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 4
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 5
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 6
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 7
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN'
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE',
}
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 1
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT'
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1',
2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2',
3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3',
4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4',
5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5',
}
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 1
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 2
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 3
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 4
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 5
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT'
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT__enumvalues = {
0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0',
1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN',
2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN',
3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN',
4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN',
5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN',
6: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN',
7: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN',
8: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN',
9: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN',
10: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN',
11: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1',
12: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2',
13: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN',
14: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14',
15: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK',
16: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP',
17: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING',
18: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF',
19: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC',
20: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC',
21: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL',
22: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
23: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1',
24: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING',
}
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 1
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 2
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 3
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 4
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 5
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 6
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 7
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 8
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 9
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 10
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 11
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 12
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 13
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 14
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 15
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 16
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 17
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 18
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 19
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 20
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 23
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 24
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL'
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__enumvalues = {
0: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0',
1: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1',
2: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2',
3: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3',
}
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 1
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 2
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 3
OTG_TRIGB_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_FREQUENCY_SELECT'
OTG_TRIGB_FREQUENCY_SELECT__enumvalues = {
0: 'OTG_TRIGB_FREQUENCY_SELECT_0',
1: 'OTG_TRIGB_FREQUENCY_SELECT_1',
2: 'OTG_TRIGB_FREQUENCY_SELECT_2',
3: 'OTG_TRIGB_FREQUENCY_SELECT_3',
}
OTG_TRIGB_FREQUENCY_SELECT_0 = 0
OTG_TRIGB_FREQUENCY_SELECT_1 = 1
OTG_TRIGB_FREQUENCY_SELECT_2 = 2
OTG_TRIGB_FREQUENCY_SELECT_3 = 3
OTG_TRIGB_FREQUENCY_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL'
OTG_TRIGB_RISING_EDGE_DETECT_CNTL__enumvalues = {
0: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0',
1: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1',
2: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2',
3: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3',
}
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 1
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 2
OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 3
OTG_TRIGB_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK'
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK__enumvalues = {
0: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE',
1: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE',
}
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 1
OTG_UPDATE_LOCK_OTG_UPDATE_LOCK = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR'
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE',
1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE',
}
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE'
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE',
}
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE'
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE',
}
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY'
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE',
1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE',
}
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1
OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR'
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE',
1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE',
}
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE'
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE',
}
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE'
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE',
}
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1
OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR'
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE',
1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE',
}
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE'
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE',
}
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE'
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = {
0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE',
1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE',
}
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1
OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE'
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE__enumvalues = {
0: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE',
1: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA',
2: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB',
3: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED',
}
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 3
OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR'
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = {
0: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE',
1: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE',
}
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1
OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR'
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR__enumvalues = {
0: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE',
1: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE',
}
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 1
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum
# values for enumeration 'OTG_VUPDATE_BLOCK_DISABLE'
OTG_VUPDATE_BLOCK_DISABLE__enumvalues = {
0: 'OTG_VUPDATE_BLOCK_DISABLE_OFF',
1: 'OTG_VUPDATE_BLOCK_DISABLE_ON',
}
OTG_VUPDATE_BLOCK_DISABLE_OFF = 0
OTG_VUPDATE_BLOCK_DISABLE_ON = 1
OTG_VUPDATE_BLOCK_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_SYNC_A_POL'
OTG_V_SYNC_A_POL__enumvalues = {
0: 'OTG_V_SYNC_A_POL_HIGH',
1: 'OTG_V_SYNC_A_POL_LOW',
}
OTG_V_SYNC_A_POL_HIGH = 0
OTG_V_SYNC_A_POL_LOW = 1
OTG_V_SYNC_A_POL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_SYNC_MODE'
OTG_V_SYNC_MODE__enumvalues = {
0: 'OTG_V_SYNC_MODE_HSYNC',
1: 'OTG_V_SYNC_MODE_HBLANK',
}
OTG_V_SYNC_MODE_HSYNC = 0
OTG_V_SYNC_MODE_HBLANK = 1
OTG_V_SYNC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD'
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0',
1: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1',
}
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 1
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT'
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE',
1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE',
}
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 1
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC'
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE',
1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE',
}
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL'
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE',
1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE',
}
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 1
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL'
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL__enumvalues = {
0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE',
1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE',
}
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 1
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK'
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__enumvalues = {
0: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE',
1: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE',
}
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 1
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK = ctypes.c_uint32 # enum
# values for enumeration 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL'
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL__enumvalues = {
0: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0',
1: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1',
2: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2',
3: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3',
4: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4',
5: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5',
}
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 1
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 2
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 3
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 4
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 5
OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DC_DMCUB_INT_TYPE'
DC_DMCUB_INT_TYPE__enumvalues = {
0: 'INT_LEVEL',
1: 'INT_PULSE',
}
INT_LEVEL = 0
INT_PULSE = 1
DC_DMCUB_INT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DC_DMCUB_TIMER_WINDOW'
DC_DMCUB_TIMER_WINDOW__enumvalues = {
0: 'BITS_31_0',
1: 'BITS_32_1',
2: 'BITS_33_2',
3: 'BITS_34_3',
4: 'BITS_35_4',
5: 'BITS_36_5',
6: 'BITS_37_6',
7: 'BITS_38_7',
}
BITS_31_0 = 0
BITS_32_1 = 1
BITS_33_2 = 2
BITS_34_3 = 3
BITS_35_4 = 4
BITS_36_5 = 5
BITS_37_6 = 6
BITS_38_7 = 7
DC_DMCUB_TIMER_WINDOW = ctypes.c_uint32 # enum
# values for enumeration 'INVALID_REG_ACCESS_TYPE'
INVALID_REG_ACCESS_TYPE__enumvalues = {
0: 'REG_UNALLOCATED_ADDR_WRITE',
1: 'REG_UNALLOCATED_ADDR_READ',
2: 'REG_VIRTUAL_WRITE',
3: 'REG_VIRTUAL_READ',
4: 'REG_SECURE_VIOLATE_WRITE',
5: 'REG_SECURE_VIOLATE_READ',
}
REG_UNALLOCATED_ADDR_WRITE = 0
REG_UNALLOCATED_ADDR_READ = 1
REG_VIRTUAL_WRITE = 2
REG_VIRTUAL_READ = 3
REG_SECURE_VIOLATE_WRITE = 4
REG_SECURE_VIOLATE_READ = 5
INVALID_REG_ACCESS_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DMU_DC_GPU_TIMER_READ_SELECT'
DMU_DC_GPU_TIMER_READ_SELECT__enumvalues = {
0: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0',
1: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1',
2: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2',
3: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3',
4: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4',
5: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5',
6: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6',
7: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7',
8: 'RESERVED_8',
9: 'RESERVED_9',
10: 'RESERVED_10',
11: 'RESERVED_11',
12: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12',
13: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13',
14: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14',
15: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15',
16: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16',
17: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17',
18: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18',
19: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19',
20: 'RESERVED_20',
21: 'RESERVED_21',
22: 'RESERVED_22',
23: 'RESERVED_23',
24: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24',
25: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25',
26: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26',
27: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27',
28: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28',
29: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29',
30: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30',
31: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31',
32: 'RESERVED_32',
33: 'RESERVED_33',
34: 'RESERVED_34',
35: 'RESERVED_35',
36: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36',
37: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37',
38: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38',
39: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39',
40: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40',
41: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41',
42: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42',
43: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43',
44: 'RESERVED_44',
45: 'RESERVED_45',
46: 'RESERVED_46',
47: 'RESERVED_47',
48: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48',
49: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49',
50: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50',
51: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51',
52: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52',
53: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53',
54: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54',
55: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55',
56: 'RESERVED_56',
57: 'RESERVED_57',
58: 'RESERVED_58',
59: 'RESERVED_59',
60: 'RESERVED_60',
61: 'RESERVED_61',
62: 'RESERVED_62',
63: 'RESERVED_63',
64: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64',
65: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65',
66: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66',
67: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67',
68: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68',
69: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69',
70: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70',
71: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71',
72: 'RESERVED_72',
73: 'RESERVED_73',
74: 'RESERVED_74',
75: 'RESERVED_75',
76: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76',
77: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77',
78: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78',
79: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79',
80: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80',
81: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81',
82: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82',
83: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83',
84: 'RESERVED_84',
85: 'RESERVED_85',
86: 'RESERVED_86',
87: 'RESERVED_87',
88: 'RESERVED_88',
89: 'RESERVED_89',
90: 'RESERVED_90',
91: 'RESERVED_91',
}
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 1
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 2
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 3
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 4
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 5
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 6
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 7
RESERVED_8 = 8
RESERVED_9 = 9
RESERVED_10 = 10
RESERVED_11 = 11
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 12
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 13
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 14
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 15
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 16
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 17
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 18
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 19
RESERVED_20 = 20
RESERVED_21 = 21
RESERVED_22 = 22
RESERVED_23 = 23
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 24
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 25
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 26
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 27
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 28
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 29
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 30
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 31
RESERVED_32 = 32
RESERVED_33 = 33
RESERVED_34 = 34
RESERVED_35 = 35
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 36
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 37
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 38
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 39
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 40
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 41
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 42
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 43
RESERVED_44 = 44
RESERVED_45 = 45
RESERVED_46 = 46
RESERVED_47 = 47
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 48
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 49
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 50
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 51
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 52
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 53
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 54
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 55
RESERVED_56 = 56
RESERVED_57 = 57
RESERVED_58 = 58
RESERVED_59 = 59
RESERVED_60 = 60
RESERVED_61 = 61
RESERVED_62 = 62
RESERVED_63 = 63
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 64
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 65
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 66
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 67
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 68
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 69
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 70
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 71
RESERVED_72 = 72
RESERVED_73 = 73
RESERVED_74 = 74
RESERVED_75 = 75
DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 76
DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 77
DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 78
DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 79
DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 80
DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 81
DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 82
DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 83
RESERVED_84 = 84
RESERVED_85 = 85
RESERVED_86 = 86
RESERVED_87 = 87
RESERVED_88 = 88
RESERVED_89 = 89
RESERVED_90 = 90
RESERVED_91 = 91
DMU_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DMU_DC_GPU_TIMER_START_POSITION'
DMU_DC_GPU_TIMER_START_POSITION__enumvalues = {
0: 'DMU_GPU_TIMER_START_0_END_27',
1: 'DMU_GPU_TIMER_START_1_END_28',
2: 'DMU_GPU_TIMER_START_2_END_29',
3: 'DMU_GPU_TIMER_START_3_END_30',
4: 'DMU_GPU_TIMER_START_4_END_31',
5: 'DMU_GPU_TIMER_START_6_END_33',
6: 'DMU_GPU_TIMER_START_8_END_35',
7: 'DMU_GPU_TIMER_START_10_END_37',
}
DMU_GPU_TIMER_START_0_END_27 = 0
DMU_GPU_TIMER_START_1_END_28 = 1
DMU_GPU_TIMER_START_2_END_29 = 2
DMU_GPU_TIMER_START_3_END_30 = 3
DMU_GPU_TIMER_START_4_END_31 = 4
DMU_GPU_TIMER_START_6_END_33 = 5
DMU_GPU_TIMER_START_8_END_35 = 6
DMU_GPU_TIMER_START_10_END_37 = 7
DMU_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum
# values for enumeration 'IHC_INTERRUPT_DEST'
IHC_INTERRUPT_DEST__enumvalues = {
0: 'INTERRUPT_SENT_TO_IH',
1: 'INTERRUPT_SENT_TO_DMCUB',
}
INTERRUPT_SENT_TO_IH = 0
INTERRUPT_SENT_TO_DMCUB = 1
IHC_INTERRUPT_DEST = ctypes.c_uint32 # enum
# values for enumeration 'IHC_INTERRUPT_LINE_STATUS'
IHC_INTERRUPT_LINE_STATUS__enumvalues = {
0: 'INTERRUPT_LINE_NOT_ASSERTED',
1: 'INTERRUPT_LINE_ASSERTED',
}
INTERRUPT_LINE_NOT_ASSERTED = 0
INTERRUPT_LINE_ASSERTED = 1
IHC_INTERRUPT_LINE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'DC_SMU_INTERRUPT_ENABLE'
DC_SMU_INTERRUPT_ENABLE__enumvalues = {
0: 'DISABLE_THE_INTERRUPT',
1: 'ENABLE_THE_INTERRUPT',
}
DISABLE_THE_INTERRUPT = 0
ENABLE_THE_INTERRUPT = 1
DC_SMU_INTERRUPT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'DMU_CLOCK_ON'
DMU_CLOCK_ON__enumvalues = {
0: 'DMU_CLOCK_STATUS_ON',
1: 'DMU_CLOCK_STATUS_OFF',
}
DMU_CLOCK_STATUS_ON = 0
DMU_CLOCK_STATUS_OFF = 1
DMU_CLOCK_ON = ctypes.c_uint32 # enum
# values for enumeration 'SMU_INTR'
SMU_INTR__enumvalues = {
0: 'SMU_MSG_INTR_NOOP',
1: 'SET_SMU_MSG_INTR',
}
SMU_MSG_INTR_NOOP = 0
SET_SMU_MSG_INTR = 1
SMU_INTR = ctypes.c_uint32 # enum
# values for enumeration 'ALLOW_SR_ON_TRANS_REQ'
ALLOW_SR_ON_TRANS_REQ__enumvalues = {
0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE',
1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE',
}
ALLOW_SR_ON_TRANS_REQ_ENABLE = 0
ALLOW_SR_ON_TRANS_REQ_DISABLE = 1
ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum
# values for enumeration 'AMCLOCK_ENABLE'
AMCLOCK_ENABLE__enumvalues = {
0: 'ENABLE_AMCLK0',
1: 'ENABLE_AMCLK1',
}
ENABLE_AMCLK0 = 0
ENABLE_AMCLK1 = 1
AMCLOCK_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'CLEAR_SMU_INTR'
CLEAR_SMU_INTR__enumvalues = {
0: 'SMU_INTR_STATUS_NOOP',
1: 'SMU_INTR_STATUS_CLEAR',
}
SMU_INTR_STATUS_NOOP = 0
SMU_INTR_STATUS_CLEAR = 1
CLEAR_SMU_INTR = ctypes.c_uint32 # enum
# values for enumeration 'CLOCK_BRANCH_SOFT_RESET'
CLOCK_BRANCH_SOFT_RESET__enumvalues = {
0: 'CLOCK_BRANCH_SOFT_RESET_NOOP',
1: 'CLOCK_BRANCH_SOFT_RESET_FORCE',
}
CLOCK_BRANCH_SOFT_RESET_NOOP = 0
CLOCK_BRANCH_SOFT_RESET_FORCE = 1
CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL'
DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = {
0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0',
1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1',
2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2',
3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3',
4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED',
}
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 1
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 2
DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 3
DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 4
DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL'
DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = {
0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0',
1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2',
}
DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0
DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 1
DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_AUDIO_DTO_SEL'
DCCG_AUDIO_DTO_SEL__enumvalues = {
0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0',
1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1',
2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO',
3: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK',
}
DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0
DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1
DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2
DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK = 3
DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO'
DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = {
0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP',
1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP',
}
DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0
DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1
DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_DBG_BLOCK_SEL'
DCCG_DBG_BLOCK_SEL__enumvalues = {
0: 'DCCG_DBG_BLOCK_SEL_DCCG',
1: 'DCCG_DBG_BLOCK_SEL_PMON',
2: 'DCCG_DBG_BLOCK_SEL_PMON2',
}
DCCG_DBG_BLOCK_SEL_DCCG = 0
DCCG_DBG_BLOCK_SEL_PMON = 1
DCCG_DBG_BLOCK_SEL_PMON2 = 2
DCCG_DBG_BLOCK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_DBG_EN'
DCCG_DBG_EN__enumvalues = {
0: 'DCCG_DBG_EN_DISABLE',
1: 'DCCG_DBG_EN_ENABLE',
}
DCCG_DBG_EN_DISABLE = 0
DCCG_DBG_EN_ENABLE = 1
DCCG_DBG_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_DEEP_COLOR_CNTL'
DCCG_DEEP_COLOR_CNTL__enumvalues = {
0: 'DCCG_DEEP_COLOR_DTO_DISABLE',
1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO',
2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO',
3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO',
}
DCCG_DEEP_COLOR_DTO_DISABLE = 0
DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1
DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2
DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3
DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN'
DCCG_FIFO_ERRDET_OVR_EN__enumvalues = {
0: 'DCCG_FIFO_ERRDET_OVR_DISABLE',
1: 'DCCG_FIFO_ERRDET_OVR_ENABLE',
}
DCCG_FIFO_ERRDET_OVR_DISABLE = 0
DCCG_FIFO_ERRDET_OVR_ENABLE = 1
DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_FIFO_ERRDET_RESET'
DCCG_FIFO_ERRDET_RESET__enumvalues = {
0: 'DCCG_FIFO_ERRDET_RESET_NOOP',
1: 'DCCG_FIFO_ERRDET_RESET_FORCE',
}
DCCG_FIFO_ERRDET_RESET_NOOP = 0
DCCG_FIFO_ERRDET_RESET_FORCE = 1
DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_FIFO_ERRDET_STATE'
DCCG_FIFO_ERRDET_STATE__enumvalues = {
0: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION',
1: 'DCCG_FIFO_ERRDET_STATE_DETECTION',
}
DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0
DCCG_FIFO_ERRDET_STATE_DETECTION = 1
DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_PERF_MODE_HSYNC'
DCCG_PERF_MODE_HSYNC__enumvalues = {
0: 'DCCG_PERF_MODE_HSYNC_NOOP',
1: 'DCCG_PERF_MODE_HSYNC_START',
}
DCCG_PERF_MODE_HSYNC_NOOP = 0
DCCG_PERF_MODE_HSYNC_START = 1
DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_PERF_MODE_VSYNC'
DCCG_PERF_MODE_VSYNC__enumvalues = {
0: 'DCCG_PERF_MODE_VSYNC_NOOP',
1: 'DCCG_PERF_MODE_VSYNC_START',
}
DCCG_PERF_MODE_VSYNC_NOOP = 0
DCCG_PERF_MODE_VSYNC_START = 1
DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_PERF_OTG_SELECT'
DCCG_PERF_OTG_SELECT__enumvalues = {
0: 'DCCG_PERF_SEL_OTG0',
1: 'DCCG_PERF_SEL_OTG1',
2: 'DCCG_PERF_SEL_OTG2',
3: 'DCCG_PERF_SEL_OTG3',
4: 'DCCG_PERF_SEL_RESERVED',
}
DCCG_PERF_SEL_OTG0 = 0
DCCG_PERF_SEL_OTG1 = 1
DCCG_PERF_SEL_OTG2 = 2
DCCG_PERF_SEL_OTG3 = 3
DCCG_PERF_SEL_RESERVED = 4
DCCG_PERF_OTG_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DCCG_PERF_RUN'
DCCG_PERF_RUN__enumvalues = {
0: 'DCCG_PERF_RUN_NOOP',
1: 'DCCG_PERF_RUN_START',
}
DCCG_PERF_RUN_NOOP = 0
DCCG_PERF_RUN_START = 1
DCCG_PERF_RUN = ctypes.c_uint32 # enum
# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS'
DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = {
0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE',
1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE',
}
DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0
DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1
DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum
# values for enumeration 'DIO_FIFO_ERROR'
DIO_FIFO_ERROR__enumvalues = {
0: 'DIO_FIFO_ERROR_00',
1: 'DIO_FIFO_ERROR_01',
2: 'DIO_FIFO_ERROR_10',
3: 'DIO_FIFO_ERROR_11',
}
DIO_FIFO_ERROR_00 = 0
DIO_FIFO_ERROR_01 = 1
DIO_FIFO_ERROR_10 = 2
DIO_FIFO_ERROR_11 = 3
DIO_FIFO_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'DISABLE_CLOCK_GATING'
DISABLE_CLOCK_GATING__enumvalues = {
0: 'CLOCK_GATING_ENABLED',
1: 'CLOCK_GATING_DISABLED',
}
CLOCK_GATING_ENABLED = 0
CLOCK_GATING_DISABLED = 1
DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum
# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO'
DISABLE_CLOCK_GATING_IN_DCO__enumvalues = {
0: 'CLOCK_GATING_ENABLED_IN_DCO',
1: 'CLOCK_GATING_DISABLED_IN_DCO',
}
CLOCK_GATING_ENABLED_IN_DCO = 0
CLOCK_GATING_DISABLED_IN_DCO = 1
DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum
# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE'
DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = {
0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING',
1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING',
}
DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0
DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1
DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'DISPCLK_FREQ_RAMP_DONE'
DISPCLK_FREQ_RAMP_DONE__enumvalues = {
0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS',
1: 'DISPCLK_FREQ_RAMP_COMPLETED',
}
DISPCLK_FREQ_RAMP_IN_PROGRESS = 0
DISPCLK_FREQ_RAMP_COMPLETED = 1
DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum
# values for enumeration 'DPREFCLK_SRC_SEL'
DPREFCLK_SRC_SEL__enumvalues = {
0: 'DPREFCLK_SRC_SEL_CK',
1: 'DPREFCLK_SRC_SEL_P0PLL',
2: 'DPREFCLK_SRC_SEL_P1PLL',
3: 'DPREFCLK_SRC_SEL_P2PLL',
}
DPREFCLK_SRC_SEL_CK = 0
DPREFCLK_SRC_SEL_P0PLL = 1
DPREFCLK_SRC_SEL_P1PLL = 2
DPREFCLK_SRC_SEL_P2PLL = 3
DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DP_DTO_DS_DISABLE'
DP_DTO_DS_DISABLE__enumvalues = {
0: 'DP_DTO_DESPREAD_DISABLE',
1: 'DP_DTO_DESPREAD_ENABLE',
}
DP_DTO_DESPREAD_DISABLE = 0
DP_DTO_DESPREAD_ENABLE = 1
DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'DS_HW_CAL_ENABLE'
DS_HW_CAL_ENABLE__enumvalues = {
0: 'DS_HW_CAL_DIS',
1: 'DS_HW_CAL_EN',
}
DS_HW_CAL_DIS = 0
DS_HW_CAL_EN = 1
DS_HW_CAL_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'DS_JITTER_COUNT_SRC_SEL'
DS_JITTER_COUNT_SRC_SEL__enumvalues = {
0: 'DS_JITTER_COUNT_SRC_SEL0',
1: 'DS_JITTER_COUNT_SRC_SEL1',
}
DS_JITTER_COUNT_SRC_SEL0 = 0
DS_JITTER_COUNT_SRC_SEL1 = 1
DS_JITTER_COUNT_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DS_REF_SRC'
DS_REF_SRC__enumvalues = {
0: 'DS_REF_IS_XTALIN',
1: 'DS_REF_IS_EXT_GENLOCK',
2: 'DS_REF_IS_PCIE',
}
DS_REF_IS_XTALIN = 0
DS_REF_IS_EXT_GENLOCK = 1
DS_REF_IS_PCIE = 2
DS_REF_SRC = ctypes.c_uint32 # enum
# values for enumeration 'DVOACLKC_IN_PHASE'
DVOACLKC_IN_PHASE__enumvalues = {
0: 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO',
1: 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO',
}
DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0
DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 1
DVOACLKC_IN_PHASE = ctypes.c_uint32 # enum
# values for enumeration 'DVOACLKC_MVP_IN_PHASE'
DVOACLKC_MVP_IN_PHASE__enumvalues = {
0: 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO',
1: 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO',
}
DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0
DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 1
DVOACLKC_MVP_IN_PHASE = ctypes.c_uint32 # enum
# values for enumeration 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE'
DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__enumvalues = {
0: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE',
1: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE',
}
DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0
DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 1
DVOACLKC_MVP_SKEW_PHASE_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'DVOACLKD_IN_PHASE'
DVOACLKD_IN_PHASE__enumvalues = {
0: 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO',
1: 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO',
}
DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0
DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 1
DVOACLKD_IN_PHASE = ctypes.c_uint32 # enum
# values for enumeration 'DVOACLK_COARSE_SKEW_CNTL'
DVOACLK_COARSE_SKEW_CNTL__enumvalues = {
0: 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT',
1: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP',
2: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS',
3: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS',
4: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS',
5: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS',
6: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS',
7: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS',
8: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS',
9: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS',
10: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS',
11: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS',
12: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS',
13: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS',
14: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS',
15: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS',
16: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP',
17: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS',
18: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS',
19: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS',
20: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS',
21: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS',
22: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS',
23: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS',
24: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS',
25: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS',
26: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS',
27: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS',
28: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS',
29: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS',
30: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS',
}
DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0
DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 1
DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 2
DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 3
DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 4
DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 5
DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 6
DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 7
DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 8
DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 9
DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 10
DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 11
DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 12
DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 13
DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 14
DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 15
DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 16
DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 17
DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 18
DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 19
DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 20
DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 21
DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 22
DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 23
DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 24
DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 25
DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 26
DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 27
DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 28
DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 29
DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 30
DVOACLK_COARSE_SKEW_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'DVOACLK_FINE_SKEW_CNTL'
DVOACLK_FINE_SKEW_CNTL__enumvalues = {
0: 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT',
1: 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP',
2: 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS',
3: 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS',
4: 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP',
5: 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS',
6: 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS',
7: 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS',
}
DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0
DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 1
DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 2
DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 3
DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 4
DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 5
DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 6
DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 7
DVOACLK_FINE_SKEW_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'DVO_ENABLE_RST'
DVO_ENABLE_RST__enumvalues = {
0: 'DVO_ENABLE_RST_DISABLE',
1: 'DVO_ENABLE_RST_ENABLE',
}
DVO_ENABLE_RST_DISABLE = 0
DVO_ENABLE_RST_ENABLE = 1
DVO_ENABLE_RST = ctypes.c_uint32 # enum
# values for enumeration 'ENABLE'
ENABLE__enumvalues = {
0: 'DISABLE_THE_FEATURE',
1: 'ENABLE_THE_FEATURE',
}
DISABLE_THE_FEATURE = 0
ENABLE_THE_FEATURE = 1
ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'ENABLE_CLOCK'
ENABLE_CLOCK__enumvalues = {
0: 'ENABLE_THE_REFCLK',
1: 'ENABLE_THE_FUNC_CLOCK',
}
ENABLE_THE_REFCLK = 0
ENABLE_THE_FUNC_CLOCK = 1
ENABLE_CLOCK = ctypes.c_uint32 # enum
# values for enumeration 'FORCE_DISABLE_CLOCK'
FORCE_DISABLE_CLOCK__enumvalues = {
0: 'NOT_FORCE_THE_CLOCK_DISABLED',
1: 'FORCE_THE_CLOCK_DISABLED',
}
NOT_FORCE_THE_CLOCK_DISABLED = 0
FORCE_THE_CLOCK_DISABLED = 1
FORCE_DISABLE_CLOCK = ctypes.c_uint32 # enum
# values for enumeration 'HDMICHARCLK_SRC_SEL'
HDMICHARCLK_SRC_SEL__enumvalues = {
0: 'HDMICHARCLK_SRC_SEL_UNIPHYA',
1: 'HDMICHARCLK_SRC_SEL_UNIPHYB',
2: 'HDMICHARCLK_SRC_SEL_UNIPHYC',
3: 'HDMICHARCLK_SRC_SEL_UNIPHYD',
4: 'HDMICHARCLK_SRC_SEL_UNIPHYE',
5: 'HDMICHARCLK_SRC_SEL_SRC_RESERVED',
}
HDMICHARCLK_SRC_SEL_UNIPHYA = 0
HDMICHARCLK_SRC_SEL_UNIPHYB = 1
HDMICHARCLK_SRC_SEL_UNIPHYC = 2
HDMICHARCLK_SRC_SEL_UNIPHYD = 3
HDMICHARCLK_SRC_SEL_UNIPHYE = 4
HDMICHARCLK_SRC_SEL_SRC_RESERVED = 5
HDMICHARCLK_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'HDMISTREAMCLK_DTO_FORCE_DIS'
HDMISTREAMCLK_DTO_FORCE_DIS__enumvalues = {
0: 'DTO_FORCE_NO_BYPASS',
1: 'DTO_FORCE_BYPASS',
}
DTO_FORCE_NO_BYPASS = 0
DTO_FORCE_BYPASS = 1
HDMISTREAMCLK_DTO_FORCE_DIS = ctypes.c_uint32 # enum
# values for enumeration 'HDMISTREAMCLK_SRC_SEL'
HDMISTREAMCLK_SRC_SEL__enumvalues = {
0: 'SEL_REFCLK0',
1: 'SEL_DTBCLK0',
2: 'SEL_DTBCLK1',
}
SEL_REFCLK0 = 0
SEL_DTBCLK0 = 1
SEL_DTBCLK1 = 2
HDMISTREAMCLK_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'JITTER_REMOVE_DISABLE'
JITTER_REMOVE_DISABLE__enumvalues = {
0: 'ENABLE_JITTER_REMOVAL',
1: 'DISABLE_JITTER_REMOVAL',
}
ENABLE_JITTER_REMOVAL = 0
DISABLE_JITTER_REMOVAL = 1
JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL'
MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = {
0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN',
1: 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK',
}
MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0
MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1
MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL'
MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = {
0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN',
1: 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK',
}
MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0
MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1
MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_ADD_PIXEL'
OTG_ADD_PIXEL__enumvalues = {
0: 'OTG_ADD_PIXEL_NOOP',
1: 'OTG_ADD_PIXEL_FORCE',
}
OTG_ADD_PIXEL_NOOP = 0
OTG_ADD_PIXEL_FORCE = 1
OTG_ADD_PIXEL = ctypes.c_uint32 # enum
# values for enumeration 'OTG_DROP_PIXEL'
OTG_DROP_PIXEL__enumvalues = {
0: 'OTG_DROP_PIXEL_NOOP',
1: 'OTG_DROP_PIXEL_FORCE',
}
OTG_DROP_PIXEL_NOOP = 0
OTG_DROP_PIXEL_FORCE = 1
OTG_DROP_PIXEL = ctypes.c_uint32 # enum
# values for enumeration 'PHYSYMCLK_FORCE_EN'
PHYSYMCLK_FORCE_EN__enumvalues = {
0: 'PHYSYMCLK_FORCE_EN_DISABLE',
1: 'PHYSYMCLK_FORCE_EN_ENABLE',
}
PHYSYMCLK_FORCE_EN_DISABLE = 0
PHYSYMCLK_FORCE_EN_ENABLE = 1
PHYSYMCLK_FORCE_EN = ctypes.c_uint32 # enum
# values for enumeration 'PHYSYMCLK_FORCE_SRC_SEL'
PHYSYMCLK_FORCE_SRC_SEL__enumvalues = {
0: 'PHYSYMCLK_FORCE_SRC_SYMCLK',
1: 'PHYSYMCLK_FORCE_SRC_PHYD18CLK',
2: 'PHYSYMCLK_FORCE_SRC_PHYD32CLK',
}
PHYSYMCLK_FORCE_SRC_SYMCLK = 0
PHYSYMCLK_FORCE_SRC_PHYD18CLK = 1
PHYSYMCLK_FORCE_SRC_PHYD32CLK = 2
PHYSYMCLK_FORCE_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE'
PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = {
0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA',
1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB',
2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC',
3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD',
4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED',
}
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2
PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3
PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 4
PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE'
PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = {
0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL',
1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL',
}
PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0
PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1
PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_PIXEL_RATE_SOURCE'
PIPE_PIXEL_RATE_SOURCE__enumvalues = {
0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL',
1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL',
2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL',
}
PIPE_PIXEL_RATE_SOURCE_P0PLL = 0
PIPE_PIXEL_RATE_SOURCE_P1PLL = 1
PIPE_PIXEL_RATE_SOURCE_P2PLL = 2
PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'PLL_CFG_IF_SOFT_RESET'
PLL_CFG_IF_SOFT_RESET__enumvalues = {
0: 'PLL_CFG_IF_SOFT_RESET_NOOP',
1: 'PLL_CFG_IF_SOFT_RESET_FORCE',
}
PLL_CFG_IF_SOFT_RESET_NOOP = 0
PLL_CFG_IF_SOFT_RESET_FORCE = 1
PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'SYMCLK_FE_FORCE_EN'
SYMCLK_FE_FORCE_EN__enumvalues = {
0: 'SYMCLK_FE_FORCE_EN_DISABLE',
1: 'SYMCLK_FE_FORCE_EN_ENABLE',
}
SYMCLK_FE_FORCE_EN_DISABLE = 0
SYMCLK_FE_FORCE_EN_ENABLE = 1
SYMCLK_FE_FORCE_EN = ctypes.c_uint32 # enum
# values for enumeration 'SYMCLK_FE_FORCE_SRC'
SYMCLK_FE_FORCE_SRC__enumvalues = {
0: 'SYMCLK_FE_FORCE_SRC_UNIPHYA',
1: 'SYMCLK_FE_FORCE_SRC_UNIPHYB',
2: 'SYMCLK_FE_FORCE_SRC_UNIPHYC',
3: 'SYMCLK_FE_FORCE_SRC_UNIPHYD',
4: 'SYMCLK_FE_FORCE_SRC_RESERVED',
}
SYMCLK_FE_FORCE_SRC_UNIPHYA = 0
SYMCLK_FE_FORCE_SRC_UNIPHYB = 1
SYMCLK_FE_FORCE_SRC_UNIPHYC = 2
SYMCLK_FE_FORCE_SRC_UNIPHYD = 3
SYMCLK_FE_FORCE_SRC_RESERVED = 4
SYMCLK_FE_FORCE_SRC = ctypes.c_uint32 # enum
# values for enumeration 'TEST_CLK_DIV_SEL'
TEST_CLK_DIV_SEL__enumvalues = {
0: 'NO_DIV',
1: 'DIV_2',
2: 'DIV_4',
3: 'DIV_8',
}
NO_DIV = 0
DIV_2 = 1
DIV_4 = 2
DIV_8 = 3
TEST_CLK_DIV_SEL = ctypes.c_uint32 # enum
# values for enumeration 'VSYNC_CNT_LATCH_MASK'
VSYNC_CNT_LATCH_MASK__enumvalues = {
0: 'VSYNC_CNT_LATCH_MASK_0',
1: 'VSYNC_CNT_LATCH_MASK_1',
}
VSYNC_CNT_LATCH_MASK_0 = 0
VSYNC_CNT_LATCH_MASK_1 = 1
VSYNC_CNT_LATCH_MASK = ctypes.c_uint32 # enum
# values for enumeration 'VSYNC_CNT_RESET_SEL'
VSYNC_CNT_RESET_SEL__enumvalues = {
0: 'VSYNC_CNT_RESET_SEL_0',
1: 'VSYNC_CNT_RESET_SEL_1',
}
VSYNC_CNT_RESET_SEL_0 = 0
VSYNC_CNT_RESET_SEL_1 = 1
VSYNC_CNT_RESET_SEL = ctypes.c_uint32 # enum
# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL'
XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = {
0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN',
1: 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK',
}
XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0
XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 1
XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'XTAL_REF_SEL'
XTAL_REF_SEL__enumvalues = {
0: 'XTAL_REF_SEL_1X',
1: 'XTAL_REF_SEL_2X',
}
XTAL_REF_SEL_1X = 0
XTAL_REF_SEL_2X = 1
XTAL_REF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'HPD_INT_CONTROL_ACK'
HPD_INT_CONTROL_ACK__enumvalues = {
0: 'HPD_INT_CONTROL_ACK_0',
1: 'HPD_INT_CONTROL_ACK_1',
}
HPD_INT_CONTROL_ACK_0 = 0
HPD_INT_CONTROL_ACK_1 = 1
HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum
# values for enumeration 'HPD_INT_CONTROL_POLARITY'
HPD_INT_CONTROL_POLARITY__enumvalues = {
0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON',
1: 'HPD_INT_CONTROL_GEN_INT_ON_CON',
}
HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0
HPD_INT_CONTROL_GEN_INT_ON_CON = 1
HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK'
HPD_INT_CONTROL_RX_INT_ACK__enumvalues = {
0: 'HPD_INT_CONTROL_RX_INT_ACK_0',
1: 'HPD_INT_CONTROL_RX_INT_ACK_1',
}
HPD_INT_CONTROL_RX_INT_ACK_0 = 0
HPD_INT_CONTROL_RX_INT_ACK_1 = 1
HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_8B10B_CUR_DISP'
DPHY_8B10B_CUR_DISP__enumvalues = {
0: 'DPHY_8B10B_CUR_DISP_ZERO',
1: 'DPHY_8B10B_CUR_DISP_ONE',
}
DPHY_8B10B_CUR_DISP_ZERO = 0
DPHY_8B10B_CUR_DISP_ONE = 1
DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_8B10B_RESET'
DPHY_8B10B_RESET__enumvalues = {
0: 'DPHY_8B10B_NOT_RESET',
1: 'DPHY_8B10B_RESETET',
}
DPHY_8B10B_NOT_RESET = 0
DPHY_8B10B_RESETET = 1
DPHY_8B10B_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_EN'
DPHY_ALT_SCRAMBLER_RESET_EN__enumvalues = {
0: 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE',
1: 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION',
}
DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0
DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 1
DPHY_ALT_SCRAMBLER_RESET_EN = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_SEL'
DPHY_ALT_SCRAMBLER_RESET_SEL__enumvalues = {
0: 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE',
1: 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE',
}
DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0
DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 1
DPHY_ALT_SCRAMBLER_RESET_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ATEST_SEL_LANE0'
DPHY_ATEST_SEL_LANE0__enumvalues = {
0: 'DPHY_ATEST_LANE0_PRBS_PATTERN',
1: 'DPHY_ATEST_LANE0_REG_PATTERN',
}
DPHY_ATEST_LANE0_PRBS_PATTERN = 0
DPHY_ATEST_LANE0_REG_PATTERN = 1
DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ATEST_SEL_LANE1'
DPHY_ATEST_SEL_LANE1__enumvalues = {
0: 'DPHY_ATEST_LANE1_PRBS_PATTERN',
1: 'DPHY_ATEST_LANE1_REG_PATTERN',
}
DPHY_ATEST_LANE1_PRBS_PATTERN = 0
DPHY_ATEST_LANE1_REG_PATTERN = 1
DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ATEST_SEL_LANE2'
DPHY_ATEST_SEL_LANE2__enumvalues = {
0: 'DPHY_ATEST_LANE2_PRBS_PATTERN',
1: 'DPHY_ATEST_LANE2_REG_PATTERN',
}
DPHY_ATEST_LANE2_PRBS_PATTERN = 0
DPHY_ATEST_LANE2_REG_PATTERN = 1
DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_ATEST_SEL_LANE3'
DPHY_ATEST_SEL_LANE3__enumvalues = {
0: 'DPHY_ATEST_LANE3_PRBS_PATTERN',
1: 'DPHY_ATEST_LANE3_REG_PATTERN',
}
DPHY_ATEST_LANE3_PRBS_PATTERN = 0
DPHY_ATEST_LANE3_REG_PATTERN = 1
DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_BYPASS'
DPHY_BYPASS__enumvalues = {
0: 'DPHY_8B10B_OUTPUT',
1: 'DPHY_DBG_OUTPUT',
}
DPHY_8B10B_OUTPUT = 0
DPHY_DBG_OUTPUT = 1
DPHY_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_CONT_EN'
DPHY_CRC_CONT_EN__enumvalues = {
0: 'DPHY_CRC_ONE_SHOT',
1: 'DPHY_CRC_CONTINUOUS',
}
DPHY_CRC_ONE_SHOT = 0
DPHY_CRC_CONTINUOUS = 1
DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_EN'
DPHY_CRC_EN__enumvalues = {
0: 'DPHY_CRC_DISABLED',
1: 'DPHY_CRC_ENABLED',
}
DPHY_CRC_DISABLED = 0
DPHY_CRC_ENABLED = 1
DPHY_CRC_EN = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_FIELD'
DPHY_CRC_FIELD__enumvalues = {
0: 'DPHY_CRC_START_FROM_TOP_FIELD',
1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD',
}
DPHY_CRC_START_FROM_TOP_FIELD = 0
DPHY_CRC_START_FROM_BOTTOM_FIELD = 1
DPHY_CRC_FIELD = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK'
DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = {
0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK',
1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED',
}
DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0
DPHY_CRC_MST_PHASE_ERROR_ACKED = 1
DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_CRC_SEL'
DPHY_CRC_SEL__enumvalues = {
0: 'DPHY_CRC_LANE0_SELECTED',
1: 'DPHY_CRC_LANE1_SELECTED',
2: 'DPHY_CRC_LANE2_SELECTED',
3: 'DPHY_CRC_LANE3_SELECTED',
}
DPHY_CRC_LANE0_SELECTED = 0
DPHY_CRC_LANE1_SELECTED = 1
DPHY_CRC_LANE2_SELECTED = 2
DPHY_CRC_LANE3_SELECTED = 3
DPHY_CRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_FEC_ENABLE'
DPHY_FEC_ENABLE__enumvalues = {
0: 'DPHY_FEC_DISABLED',
1: 'DPHY_FEC_ENABLED',
}
DPHY_FEC_DISABLED = 0
DPHY_FEC_ENABLED = 1
DPHY_FEC_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_FEC_READY'
DPHY_FEC_READY__enumvalues = {
0: 'DPHY_FEC_READY_EN',
1: 'DPHY_FEC_READY_DIS',
}
DPHY_FEC_READY_EN = 0
DPHY_FEC_READY_DIS = 1
DPHY_FEC_READY = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_LOAD_BS_COUNT_START'
DPHY_LOAD_BS_COUNT_START__enumvalues = {
0: 'DPHY_LOAD_BS_COUNT_STARTED',
1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED',
}
DPHY_LOAD_BS_COUNT_STARTED = 0
DPHY_LOAD_BS_COUNT_NOT_STARTED = 1
DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_PRBS_EN'
DPHY_PRBS_EN__enumvalues = {
0: 'DPHY_PRBS_DISABLE',
1: 'DPHY_PRBS_ENABLE',
}
DPHY_PRBS_DISABLE = 0
DPHY_PRBS_ENABLE = 1
DPHY_PRBS_EN = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_PRBS_SEL'
DPHY_PRBS_SEL__enumvalues = {
0: 'DPHY_PRBS7_SELECTED',
1: 'DPHY_PRBS23_SELECTED',
2: 'DPHY_PRBS11_SELECTED',
}
DPHY_PRBS7_SELECTED = 0
DPHY_PRBS23_SELECTED = 1
DPHY_PRBS11_SELECTED = 2
DPHY_PRBS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE'
DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = {
0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0',
1: 'DPHY_FAST_TRAINING_CAPABLE',
}
DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0
DPHY_FAST_TRAINING_CAPABLE = 1
DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_SCRAMBLER_ADVANCE'
DPHY_SCRAMBLER_ADVANCE__enumvalues = {
0: 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY',
1: 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL',
}
DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0
DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 1
DPHY_SCRAMBLER_ADVANCE = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_SCRAMBLER_DIS'
DPHY_SCRAMBLER_DIS__enumvalues = {
0: 'DPHY_SCR_ENABLED',
1: 'DPHY_SCR_DISABLED',
}
DPHY_SCR_ENABLED = 0
DPHY_SCR_DISABLED = 1
DPHY_SCRAMBLER_DIS = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_SCRAMBLER_KCODE'
DPHY_SCRAMBLER_KCODE__enumvalues = {
0: 'DPHY_SCRAMBLER_KCODE_DISABLED',
1: 'DPHY_SCRAMBLER_KCODE_ENABLED',
}
DPHY_SCRAMBLER_KCODE_DISABLED = 0
DPHY_SCRAMBLER_KCODE_ENABLED = 1
DPHY_SCRAMBLER_KCODE = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_SCRAMBLER_SEL'
DPHY_SCRAMBLER_SEL__enumvalues = {
0: 'DPHY_SCRAMBLER_SEL_LANE_DATA',
1: 'DPHY_SCRAMBLER_SEL_DBG_DATA',
}
DPHY_SCRAMBLER_SEL_LANE_DATA = 0
DPHY_SCRAMBLER_SEL_DBG_DATA = 1
DPHY_SCRAMBLER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_SKEW_BYPASS'
DPHY_SKEW_BYPASS__enumvalues = {
0: 'DPHY_WITH_SKEW',
1: 'DPHY_NO_SKEW',
}
DPHY_WITH_SKEW = 0
DPHY_NO_SKEW = 1
DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM'
DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM__enumvalues = {
0: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET',
1: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET',
}
DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0
DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 1
DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_SW_FAST_TRAINING_START'
DPHY_SW_FAST_TRAINING_START__enumvalues = {
0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED',
1: 'DPHY_SW_FAST_TRAINING_STARTED',
}
DPHY_SW_FAST_TRAINING_NOT_STARTED = 0
DPHY_SW_FAST_TRAINING_STARTED = 1
DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum
# values for enumeration 'DPHY_TRAINING_PATTERN_SEL'
DPHY_TRAINING_PATTERN_SEL__enumvalues = {
0: 'DPHY_TRAINING_PATTERN_1',
1: 'DPHY_TRAINING_PATTERN_2',
2: 'DPHY_TRAINING_PATTERN_3',
3: 'DPHY_TRAINING_PATTERN_4',
}
DPHY_TRAINING_PATTERN_1 = 0
DPHY_TRAINING_PATTERN_2 = 1
DPHY_TRAINING_PATTERN_3 = 2
DPHY_TRAINING_PATTERN_4 = 3
DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DP_COMPONENT_DEPTH'
DP_COMPONENT_DEPTH__enumvalues = {
0: 'DP_COMPONENT_DEPTH_6BPC',
1: 'DP_COMPONENT_DEPTH_8BPC',
2: 'DP_COMPONENT_DEPTH_10BPC',
3: 'DP_COMPONENT_DEPTH_12BPC',
4: 'DP_COMPONENT_DEPTH_16BPC',
}
DP_COMPONENT_DEPTH_6BPC = 0
DP_COMPONENT_DEPTH_8BPC = 1
DP_COMPONENT_DEPTH_10BPC = 2
DP_COMPONENT_DEPTH_12BPC = 3
DP_COMPONENT_DEPTH_16BPC = 4
DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'DP_CP_ENCRYPTION_TYPE'
DP_CP_ENCRYPTION_TYPE__enumvalues = {
0: 'DP_CP_ENCRYPTION_TYPE_0',
1: 'DP_CP_ENCRYPTION_TYPE_1',
}
DP_CP_ENCRYPTION_TYPE_0 = 0
DP_CP_ENCRYPTION_TYPE_1 = 1
DP_CP_ENCRYPTION_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_8B10B_EXT_DISP'
DP_DPHY_8B10B_EXT_DISP__enumvalues = {
0: 'DP_DPHY_8B10B_EXT_DISP_ZERO',
1: 'DP_DPHY_8B10B_EXT_DISP_ONE',
}
DP_DPHY_8B10B_EXT_DISP_ZERO = 0
DP_DPHY_8B10B_EXT_DISP_ONE = 1
DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK'
DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = {
0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED',
1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED',
}
DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0
DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1
DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK'
DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = {
0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED',
1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED',
}
DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0
DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1
DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN'
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = {
0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED',
1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED',
}
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum
# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE'
DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = {
0: 'DP_DPHY_HBR2_PASS_THROUGH',
1: 'DP_DPHY_HBR2_PATTERN_1',
2: 'DP_DPHY_HBR2_PATTERN_2_NEG',
3: 'DP_DPHY_HBR2_PATTERN_3',
6: 'DP_DPHY_HBR2_PATTERN_2_POS',
}
DP_DPHY_HBR2_PASS_THROUGH = 0
DP_DPHY_HBR2_PATTERN_1 = 1
DP_DPHY_HBR2_PATTERN_2_NEG = 2
DP_DPHY_HBR2_PATTERN_3 = 3
DP_DPHY_HBR2_PATTERN_2_POS = 6
DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_DSC_MODE'
DP_DSC_MODE__enumvalues = {
0: 'DP_DSC_DISABLE',
1: 'DP_DSC_444_SIMPLE_422',
2: 'DP_DSC_NATIVE_422_420',
}
DP_DSC_DISABLE = 0
DP_DSC_444_SIMPLE_422 = 1
DP_DSC_NATIVE_422_420 = 2
DP_DSC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_EMBEDDED_PANEL_MODE'
DP_EMBEDDED_PANEL_MODE__enumvalues = {
0: 'DP_EXTERNAL_PANEL',
1: 'DP_EMBEDDED_PANEL',
}
DP_EXTERNAL_PANEL = 0
DP_EMBEDDED_PANEL = 1
DP_EMBEDDED_PANEL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_LINK_TRAINING_COMPLETE'
DP_LINK_TRAINING_COMPLETE__enumvalues = {
0: 'DP_LINK_TRAINING_NOT_COMPLETE',
1: 'DP_LINK_TRAINING_ALREADY_COMPLETE',
}
DP_LINK_TRAINING_NOT_COMPLETE = 0
DP_LINK_TRAINING_ALREADY_COMPLETE = 1
DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum
# values for enumeration 'DP_LINK_TRAINING_SWITCH_MODE'
DP_LINK_TRAINING_SWITCH_MODE__enumvalues = {
0: 'DP_LINK_TRAINING_SWITCH_TO_IDLE',
1: 'DP_LINK_TRAINING_SWITCH_TO_VIDEO',
}
DP_LINK_TRAINING_SWITCH_TO_IDLE = 0
DP_LINK_TRAINING_SWITCH_TO_VIDEO = 1
DP_LINK_TRAINING_SWITCH_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_ML_PHY_SEQ_MODE'
DP_ML_PHY_SEQ_MODE__enumvalues = {
0: 'DP_ML_PHY_SEQ_LINE_NUM',
1: 'DP_ML_PHY_SEQ_IMMEDIATE',
}
DP_ML_PHY_SEQ_LINE_NUM = 0
DP_ML_PHY_SEQ_IMMEDIATE = 1
DP_ML_PHY_SEQ_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN'
DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = {
0: 'MSA_V_TIMING_OVERRIDE_DISABLED',
1: 'MSA_V_TIMING_OVERRIDE_ENABLED',
}
MSA_V_TIMING_OVERRIDE_DISABLED = 0
MSA_V_TIMING_OVERRIDE_ENABLED = 1
DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_BLANK_CODE'
DP_MSE_BLANK_CODE__enumvalues = {
0: 'DP_MSE_BLANK_CODE_SF_FILLED',
1: 'DP_MSE_BLANK_CODE_ZERO_FILLED',
}
DP_MSE_BLANK_CODE_SF_FILLED = 0
DP_MSE_BLANK_CODE_ZERO_FILLED = 1
DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_LINK_LINE'
DP_MSE_LINK_LINE__enumvalues = {
0: 'DP_MSE_LINK_LINE_32_MTP_LONG',
1: 'DP_MSE_LINK_LINE_64_MTP_LONG',
2: 'DP_MSE_LINK_LINE_128_MTP_LONG',
3: 'DP_MSE_LINK_LINE_256_MTP_LONG',
}
DP_MSE_LINK_LINE_32_MTP_LONG = 0
DP_MSE_LINK_LINE_64_MTP_LONG = 1
DP_MSE_LINK_LINE_128_MTP_LONG = 2
DP_MSE_LINK_LINE_256_MTP_LONG = 3
DP_MSE_LINK_LINE = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_SAT_ENCRYPT0'
DP_MSE_SAT_ENCRYPT0__enumvalues = {
0: 'DP_MSE_SAT_ENCRYPT0_DISABLED',
1: 'DP_MSE_SAT_ENCRYPT0_ENABLED',
}
DP_MSE_SAT_ENCRYPT0_DISABLED = 0
DP_MSE_SAT_ENCRYPT0_ENABLED = 1
DP_MSE_SAT_ENCRYPT0 = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_SAT_ENCRYPT1'
DP_MSE_SAT_ENCRYPT1__enumvalues = {
0: 'DP_MSE_SAT_ENCRYPT1_DISABLED',
1: 'DP_MSE_SAT_ENCRYPT1_ENABLED',
}
DP_MSE_SAT_ENCRYPT1_DISABLED = 0
DP_MSE_SAT_ENCRYPT1_ENABLED = 1
DP_MSE_SAT_ENCRYPT1 = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_SAT_ENCRYPT2'
DP_MSE_SAT_ENCRYPT2__enumvalues = {
0: 'DP_MSE_SAT_ENCRYPT2_DISABLED',
1: 'DP_MSE_SAT_ENCRYPT2_ENABLED',
}
DP_MSE_SAT_ENCRYPT2_DISABLED = 0
DP_MSE_SAT_ENCRYPT2_ENABLED = 1
DP_MSE_SAT_ENCRYPT2 = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_SAT_ENCRYPT3'
DP_MSE_SAT_ENCRYPT3__enumvalues = {
0: 'DP_MSE_SAT_ENCRYPT3_DISABLED',
1: 'DP_MSE_SAT_ENCRYPT3_ENABLED',
}
DP_MSE_SAT_ENCRYPT3_DISABLED = 0
DP_MSE_SAT_ENCRYPT3_ENABLED = 1
DP_MSE_SAT_ENCRYPT3 = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_SAT_ENCRYPT4'
DP_MSE_SAT_ENCRYPT4__enumvalues = {
0: 'DP_MSE_SAT_ENCRYPT4_DISABLED',
1: 'DP_MSE_SAT_ENCRYPT4_ENABLED',
}
DP_MSE_SAT_ENCRYPT4_DISABLED = 0
DP_MSE_SAT_ENCRYPT4_ENABLED = 1
DP_MSE_SAT_ENCRYPT4 = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_SAT_ENCRYPT5'
DP_MSE_SAT_ENCRYPT5__enumvalues = {
0: 'DP_MSE_SAT_ENCRYPT5_DISABLED',
1: 'DP_MSE_SAT_ENCRYPT5_ENABLED',
}
DP_MSE_SAT_ENCRYPT5_DISABLED = 0
DP_MSE_SAT_ENCRYPT5_ENABLED = 1
DP_MSE_SAT_ENCRYPT5 = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_SAT_UPDATE_ACT'
DP_MSE_SAT_UPDATE_ACT__enumvalues = {
0: 'DP_MSE_SAT_UPDATE_NO_ACTION',
1: 'DP_MSE_SAT_UPDATE_WITH_TRIGGER',
2: 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER',
}
DP_MSE_SAT_UPDATE_NO_ACTION = 0
DP_MSE_SAT_UPDATE_WITH_TRIGGER = 1
DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 2
DP_MSE_SAT_UPDATE_ACT = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_TIMESTAMP_MODE'
DP_MSE_TIMESTAMP_MODE__enumvalues = {
0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE',
1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE',
}
DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0
DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1
DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSE_ZERO_ENCODER'
DP_MSE_ZERO_ENCODER__enumvalues = {
0: 'DP_MSE_NOT_ZERO_FE_ENCODER',
1: 'DP_MSE_ZERO_FE_ENCODER',
}
DP_MSE_NOT_ZERO_FE_ENCODER = 0
DP_MSE_ZERO_FE_ENCODER = 1
DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum
# values for enumeration 'DP_MSO_NUM_OF_SST_LINKS'
DP_MSO_NUM_OF_SST_LINKS__enumvalues = {
0: 'DP_MSO_ONE_SSTLINK',
1: 'DP_MSO_TWO_SSTLINK',
2: 'DP_MSO_FOUR_SSTLINK',
}
DP_MSO_ONE_SSTLINK = 0
DP_MSO_TWO_SSTLINK = 1
DP_MSO_FOUR_SSTLINK = 2
DP_MSO_NUM_OF_SST_LINKS = ctypes.c_uint32 # enum
# values for enumeration 'DP_PIXEL_ENCODING'
DP_PIXEL_ENCODING__enumvalues = {
0: 'DP_PIXEL_ENCODING_RGB444',
1: 'DP_PIXEL_ENCODING_YCBCR422',
2: 'DP_PIXEL_ENCODING_YCBCR444',
3: 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT',
4: 'DP_PIXEL_ENCODING_Y_ONLY',
5: 'DP_PIXEL_ENCODING_YCBCR420',
}
DP_PIXEL_ENCODING_RGB444 = 0
DP_PIXEL_ENCODING_YCBCR422 = 1
DP_PIXEL_ENCODING_YCBCR444 = 2
DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 3
DP_PIXEL_ENCODING_Y_ONLY = 4
DP_PIXEL_ENCODING_YCBCR420 = 5
DP_PIXEL_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'DP_PIXEL_PER_CYCLE_PROCESSING_NUM'
DP_PIXEL_PER_CYCLE_PROCESSING_NUM__enumvalues = {
0: 'DP_ONE_PIXEL_PER_CYCLE',
1: 'DP_TWO_PIXEL_PER_CYCLE',
}
DP_ONE_PIXEL_PER_CYCLE = 0
DP_TWO_PIXEL_PER_CYCLE = 1
DP_PIXEL_PER_CYCLE_PROCESSING_NUM = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE'
DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = {
0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ',
1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED',
}
DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0
DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1
DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_ASP_PRIORITY'
DP_SEC_ASP_PRIORITY__enumvalues = {
0: 'DP_SEC_ASP_LOW_PRIORITY',
1: 'DP_SEC_ASP_HIGH_PRIORITY',
}
DP_SEC_ASP_LOW_PRIORITY = 0
DP_SEC_ASP_HIGH_PRIORITY = 1
DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_AUDIO_MUTE'
DP_SEC_AUDIO_MUTE__enumvalues = {
0: 'DP_SEC_AUDIO_MUTE_HW_CTRL',
1: 'DP_SEC_AUDIO_MUTE_SW_CTRL',
}
DP_SEC_AUDIO_MUTE_HW_CTRL = 0
DP_SEC_AUDIO_MUTE_SW_CTRL = 1
DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_COLLISION_ACK'
DP_SEC_COLLISION_ACK__enumvalues = {
0: 'DP_SEC_COLLISION_ACK_NO_EFFECT',
1: 'DP_SEC_COLLISION_ACK_CLR_FLAG',
}
DP_SEC_COLLISION_ACK_NO_EFFECT = 0
DP_SEC_COLLISION_ACK_CLR_FLAG = 1
DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_GSP0_PRIORITY'
DP_SEC_GSP0_PRIORITY__enumvalues = {
0: 'SEC_GSP0_PRIORITY_LOW',
1: 'SEC_GSP0_PRIORITY_HIGH',
}
SEC_GSP0_PRIORITY_LOW = 0
SEC_GSP0_PRIORITY_HIGH = 1
DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_GSP_SEND'
DP_SEC_GSP_SEND__enumvalues = {
0: 'NOT_SENT',
1: 'FORCE_SENT',
}
NOT_SENT = 0
FORCE_SENT = 1
DP_SEC_GSP_SEND = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_GSP_SEND_ANY_LINE'
DP_SEC_GSP_SEND_ANY_LINE__enumvalues = {
0: 'SEND_AT_LINK_NUMBER',
1: 'SEND_AT_EARLIEST_TIME',
}
SEND_AT_LINK_NUMBER = 0
SEND_AT_EARLIEST_TIME = 1
DP_SEC_GSP_SEND_ANY_LINE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_GSP_SEND_PPS'
DP_SEC_GSP_SEND_PPS__enumvalues = {
0: 'SEND_NORMAL_PACKET',
1: 'SEND_PPS_PACKET',
}
SEND_NORMAL_PACKET = 0
SEND_PPS_PACKET = 1
DP_SEC_GSP_SEND_PPS = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_LINE_REFERENCE'
DP_SEC_LINE_REFERENCE__enumvalues = {
0: 'REFER_TO_DP_SOF',
1: 'REFER_TO_OTG_SOF',
}
REFER_TO_DP_SOF = 0
REFER_TO_OTG_SOF = 1
DP_SEC_LINE_REFERENCE = ctypes.c_uint32 # enum
# values for enumeration 'DP_SEC_TIMESTAMP_MODE'
DP_SEC_TIMESTAMP_MODE__enumvalues = {
0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE',
1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE',
}
DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0
DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1
DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_STEER_OVERFLOW_ACK'
DP_STEER_OVERFLOW_ACK__enumvalues = {
0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT',
1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT',
}
DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0
DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1
DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_STEER_OVERFLOW_MASK'
DP_STEER_OVERFLOW_MASK__enumvalues = {
0: 'DP_STEER_OVERFLOW_MASKED',
1: 'DP_STEER_OVERFLOW_UNMASK',
}
DP_STEER_OVERFLOW_MASKED = 0
DP_STEER_OVERFLOW_UNMASK = 1
DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DP_SYNC_POLARITY'
DP_SYNC_POLARITY__enumvalues = {
0: 'DP_SYNC_POLARITY_ACTIVE_HIGH',
1: 'DP_SYNC_POLARITY_ACTIVE_LOW',
}
DP_SYNC_POLARITY_ACTIVE_HIGH = 0
DP_SYNC_POLARITY_ACTIVE_LOW = 1
DP_SYNC_POLARITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_TU_OVERFLOW_ACK'
DP_TU_OVERFLOW_ACK__enumvalues = {
0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT',
1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT',
}
DP_TU_OVERFLOW_ACK_NO_EFFECT = 0
DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1
DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_UDI_LANES'
DP_UDI_LANES__enumvalues = {
0: 'DP_UDI_1_LANE',
1: 'DP_UDI_2_LANES',
2: 'DP_UDI_LANES_RESERVED',
3: 'DP_UDI_4_LANES',
}
DP_UDI_1_LANE = 0
DP_UDI_2_LANES = 1
DP_UDI_LANES_RESERVED = 2
DP_UDI_4_LANES = 3
DP_UDI_LANES = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE'
DP_VID_ENHANCED_FRAME_MODE__enumvalues = {
0: 'VID_NORMAL_FRAME_MODE',
1: 'VID_ENHANCED_MODE',
}
VID_NORMAL_FRAME_MODE = 0
VID_ENHANCED_MODE = 1
DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE'
DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = {
0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE',
1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START',
}
DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0
DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1
DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_M_N_GEN_EN'
DP_VID_M_N_GEN_EN__enumvalues = {
0: 'DP_VID_M_N_PROGRAMMED_VIA_REG',
1: 'DP_VID_M_N_CALC_AUTO',
}
DP_VID_M_N_PROGRAMMED_VIA_REG = 0
DP_VID_M_N_CALC_AUTO = 1
DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_N_MUL'
DP_VID_N_MUL__enumvalues = {
0: 'DP_VID_M_1X_INPUT_PIXEL_RATE',
1: 'DP_VID_M_2X_INPUT_PIXEL_RATE',
2: 'DP_VID_M_4X_INPUT_PIXEL_RATE',
3: 'DP_VID_M_8X_INPUT_PIXEL_RATE',
}
DP_VID_M_1X_INPUT_PIXEL_RATE = 0
DP_VID_M_2X_INPUT_PIXEL_RATE = 1
DP_VID_M_4X_INPUT_PIXEL_RATE = 2
DP_VID_M_8X_INPUT_PIXEL_RATE = 3
DP_VID_N_MUL = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_STREAM_DISABLE_ACK'
DP_VID_STREAM_DISABLE_ACK__enumvalues = {
0: 'ID_STREAM_DISABLE_NO_ACK',
1: 'ID_STREAM_DISABLE_ACKED',
}
ID_STREAM_DISABLE_NO_ACK = 0
ID_STREAM_DISABLE_ACKED = 1
DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_STREAM_DISABLE_MASK'
DP_VID_STREAM_DISABLE_MASK__enumvalues = {
0: 'VID_STREAM_DISABLE_MASKED',
1: 'VID_STREAM_DISABLE_UNMASK',
}
VID_STREAM_DISABLE_MASKED = 0
VID_STREAM_DISABLE_UNMASK = 1
DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_STREAM_DIS_DEFER'
DP_VID_STREAM_DIS_DEFER__enumvalues = {
0: 'DP_VID_STREAM_DIS_NO_DEFER',
1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK',
2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK',
}
DP_VID_STREAM_DIS_NO_DEFER = 0
DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1
DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2
DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum
# values for enumeration 'DP_VID_VBID_FIELD_POL'
DP_VID_VBID_FIELD_POL__enumvalues = {
0: 'DP_VID_VBID_FIELD_POL_NORMAL',
1: 'DP_VID_VBID_FIELD_POL_INV',
}
DP_VID_VBID_FIELD_POL_NORMAL = 0
DP_VID_VBID_FIELD_POL_INV = 1
DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum
# values for enumeration 'FEC_ACTIVE_STATUS'
FEC_ACTIVE_STATUS__enumvalues = {
0: 'DPHY_FEC_NOT_ACTIVE',
1: 'DPHY_FEC_ACTIVE',
}
DPHY_FEC_NOT_ACTIVE = 0
DPHY_FEC_ACTIVE = 1
FEC_ACTIVE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'DIG_BE_CNTL_HPD_SELECT'
DIG_BE_CNTL_HPD_SELECT__enumvalues = {
0: 'DIG_BE_CNTL_HPD1',
1: 'DIG_BE_CNTL_HPD2',
2: 'DIG_BE_CNTL_HPD3',
3: 'DIG_BE_CNTL_HPD4',
4: 'DIG_BE_CNTL_HPD5',
5: 'DIG_BE_CNTL_NO_HPD',
}
DIG_BE_CNTL_HPD1 = 0
DIG_BE_CNTL_HPD2 = 1
DIG_BE_CNTL_HPD3 = 2
DIG_BE_CNTL_HPD4 = 3
DIG_BE_CNTL_HPD5 = 4
DIG_BE_CNTL_NO_HPD = 5
DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DIG_BE_CNTL_MODE'
DIG_BE_CNTL_MODE__enumvalues = {
0: 'DIG_BE_DP_SST_MODE',
1: 'DIG_BE_RESERVED1',
2: 'DIG_BE_TMDS_DVI_MODE',
3: 'DIG_BE_TMDS_HDMI_MODE',
4: 'DIG_BE_RESERVED4',
5: 'DIG_BE_DP_MST_MODE',
6: 'DIG_BE_RESERVED2',
7: 'DIG_BE_RESERVED3',
}
DIG_BE_DP_SST_MODE = 0
DIG_BE_RESERVED1 = 1
DIG_BE_TMDS_DVI_MODE = 2
DIG_BE_TMDS_HDMI_MODE = 3
DIG_BE_RESERVED4 = 4
DIG_BE_DP_MST_MODE = 5
DIG_BE_RESERVED2 = 6
DIG_BE_RESERVED3 = 7
DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DIG_DIGITAL_BYPASS_ENABLE'
DIG_DIGITAL_BYPASS_ENABLE__enumvalues = {
0: 'DIG_DIGITAL_BYPASS_OFF',
1: 'DIG_DIGITAL_BYPASS_ON',
}
DIG_DIGITAL_BYPASS_OFF = 0
DIG_DIGITAL_BYPASS_ON = 1
DIG_DIGITAL_BYPASS_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'DIG_DIGITAL_BYPASS_SEL'
DIG_DIGITAL_BYPASS_SEL__enumvalues = {
0: 'DIG_DIGITAL_BYPASS_SEL_BYPASS',
1: 'DIG_DIGITAL_BYPASS_SEL_36BPP',
2: 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB',
3: 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB',
4: 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB',
5: 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB',
6: 'DIG_DIGITAL_BYPASS_SEL_ALPHA',
}
DIG_DIGITAL_BYPASS_SEL_BYPASS = 0
DIG_DIGITAL_BYPASS_SEL_36BPP = 1
DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 2
DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 3
DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 4
DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 5
DIG_DIGITAL_BYPASS_SEL_ALPHA = 6
DIG_DIGITAL_BYPASS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT'
DIG_FE_CNTL_SOURCE_SELECT__enumvalues = {
0: 'DIG_FE_SOURCE_FROM_OTG0',
1: 'DIG_FE_SOURCE_FROM_OTG1',
2: 'DIG_FE_SOURCE_FROM_OTG2',
3: 'DIG_FE_SOURCE_FROM_OTG3',
4: 'DIG_FE_SOURCE_RESERVED',
}
DIG_FE_SOURCE_FROM_OTG0 = 0
DIG_FE_SOURCE_FROM_OTG1 = 1
DIG_FE_SOURCE_FROM_OTG2 = 2
DIG_FE_SOURCE_FROM_OTG3 = 3
DIG_FE_SOURCE_RESERVED = 4
DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT'
DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = {
0: 'DIG_FE_STEREOSYNC_FROM_OTG0',
1: 'DIG_FE_STEREOSYNC_FROM_OTG1',
2: 'DIG_FE_STEREOSYNC_FROM_OTG2',
3: 'DIG_FE_STEREOSYNC_FROM_OTG3',
4: 'DIG_FE_STEREOSYNC_RESERVED',
}
DIG_FE_STEREOSYNC_FROM_OTG0 = 0
DIG_FE_STEREOSYNC_FROM_OTG1 = 1
DIG_FE_STEREOSYNC_FROM_OTG2 = 2
DIG_FE_STEREOSYNC_FROM_OTG3 = 3
DIG_FE_STEREOSYNC_RESERVED = 4
DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX'
DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX__enumvalues = {
0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX',
1: 'DIG_FIFO_FORCE_RECOMP_MINMAX',
}
DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0
DIG_FIFO_FORCE_RECOMP_MINMAX = 1
DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL'
DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL__enumvalues = {
0: 'DIG_FIFO_USE_OVERWRITE_LEVEL',
1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL',
}
DIG_FIFO_USE_OVERWRITE_LEVEL = 0
DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1
DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_FORCE_RECAL_AVERAGE'
DIG_FIFO_FORCE_RECAL_AVERAGE__enumvalues = {
0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE',
1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL',
}
DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0
DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1
DIG_FIFO_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_OUTPUT_PROCESSING_MODE'
DIG_FIFO_OUTPUT_PROCESSING_MODE__enumvalues = {
0: 'DIG_FIFO_1_PIX_PER_CYCLE',
1: 'DIG_FIFO_2_PIX_PER_CYCLE',
}
DIG_FIFO_1_PIX_PER_CYCLE = 0
DIG_FIFO_2_PIX_PER_CYCLE = 1
DIG_FIFO_OUTPUT_PROCESSING_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR'
DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR__enumvalues = {
0: 'DIG_FIFO_NO_ERROR_OCCURRED',
1: 'DIG_FIFO_UNDERFLOW_OCCURRED',
2: 'DIG_FIFO_OVERFLOW_OCCURRED',
}
DIG_FIFO_NO_ERROR_OCCURRED = 0
DIG_FIFO_UNDERFLOW_OCCURRED = 1
DIG_FIFO_OVERFLOW_OCCURRED = 2
DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC'
DIG_FIFO_READ_CLOCK_SRC__enumvalues = {
0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG',
1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE',
}
DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0
DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1
DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum
# values for enumeration 'DIG_INPUT_PIXEL_SEL'
DIG_INPUT_PIXEL_SEL__enumvalues = {
0: 'DIG_ALL_PIXEL',
1: 'DIG_EVEN_PIXEL_ONLY',
2: 'DIG_ODD_PIXEL_ONLY',
}
DIG_ALL_PIXEL = 0
DIG_EVEN_PIXEL_ONLY = 1
DIG_ODD_PIXEL_ONLY = 2
DIG_INPUT_PIXEL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL'
DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = {
0: 'DIG_OUTPUT_CRC_ON_LINK0',
1: 'DIG_OUTPUT_CRC_ON_LINK1',
}
DIG_OUTPUT_CRC_ON_LINK0 = 0
DIG_OUTPUT_CRC_ON_LINK1 = 1
DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL'
DIG_OUTPUT_CRC_DATA_SEL__enumvalues = {
0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME',
1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY',
2: 'DIG_OUTPUT_CRC_FOR_VBI',
3: 'DIG_OUTPUT_CRC_FOR_AUDIO',
}
DIG_OUTPUT_CRC_FOR_FULLFRAME = 0
DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1
DIG_OUTPUT_CRC_FOR_VBI = 2
DIG_OUTPUT_CRC_FOR_AUDIO = 3
DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT'
DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = {
0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS',
1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH',
}
DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0
DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1
DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum
# values for enumeration 'DIG_SL_PIXEL_GROUPING'
DIG_SL_PIXEL_GROUPING__enumvalues = {
0: 'DIG_SINGLETON_PIXELS',
1: 'DIG_PAIR_PIXELS',
}
DIG_SINGLETON_PIXELS = 0
DIG_PAIR_PIXELS = 1
DIG_SL_PIXEL_GROUPING = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN'
DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = {
0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE',
1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG',
}
DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0
DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1
DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL'
DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = {
0: 'DIG_10BIT_TEST_PATTERN',
1: 'DIG_ALTERNATING_TEST_PATTERN',
}
DIG_10BIT_TEST_PATTERN = 0
DIG_ALTERNATING_TEST_PATTERN = 1
DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN'
DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = {
0: 'DIG_TEST_PATTERN_NORMAL',
1: 'DIG_TEST_PATTERN_RANDOM',
}
DIG_TEST_PATTERN_NORMAL = 0
DIG_TEST_PATTERN_RANDOM = 1
DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET'
DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = {
0: 'DIG_RANDOM_PATTERN_ENABLED',
1: 'DIG_RANDOM_PATTERN_RESETED',
}
DIG_RANDOM_PATTERN_ENABLED = 0
DIG_RANDOM_PATTERN_RESETED = 1
DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN'
DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = {
0: 'DIG_IN_NORMAL_OPERATION',
1: 'DIG_IN_DEBUG_MODE',
}
DIG_IN_NORMAL_OPERATION = 0
DIG_IN_DEBUG_MODE = 1
DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'DOLBY_VISION_ENABLE'
DOLBY_VISION_ENABLE__enumvalues = {
0: 'DOLBY_VISION_DISABLED',
1: 'DOLBY_VISION_ENABLED',
}
DOLBY_VISION_DISABLED = 0
DOLBY_VISION_ENABLED = 1
DOLBY_VISION_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACP_SEND'
HDMI_ACP_SEND__enumvalues = {
0: 'HDMI_ACP_NOT_SEND',
1: 'HDMI_ACP_PKT_SEND',
}
HDMI_ACP_NOT_SEND = 0
HDMI_ACP_PKT_SEND = 1
HDMI_ACP_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY'
HDMI_ACR_AUDIO_PRIORITY__enumvalues = {
0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE',
1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT',
}
HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0
HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1
HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_CONT'
HDMI_ACR_CONT__enumvalues = {
0: 'HDMI_ACR_CONT_DISABLE',
1: 'HDMI_ACR_CONT_ENABLE',
}
HDMI_ACR_CONT_DISABLE = 0
HDMI_ACR_CONT_ENABLE = 1
HDMI_ACR_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_N_MULTIPLE'
HDMI_ACR_N_MULTIPLE__enumvalues = {
0: 'HDMI_ACR_0_MULTIPLE_RESERVED',
1: 'HDMI_ACR_1_MULTIPLE',
2: 'HDMI_ACR_2_MULTIPLE',
3: 'HDMI_ACR_3_MULTIPLE_RESERVED',
4: 'HDMI_ACR_4_MULTIPLE',
5: 'HDMI_ACR_5_MULTIPLE_RESERVED',
6: 'HDMI_ACR_6_MULTIPLE_RESERVED',
7: 'HDMI_ACR_7_MULTIPLE_RESERVED',
}
HDMI_ACR_0_MULTIPLE_RESERVED = 0
HDMI_ACR_1_MULTIPLE = 1
HDMI_ACR_2_MULTIPLE = 2
HDMI_ACR_3_MULTIPLE_RESERVED = 3
HDMI_ACR_4_MULTIPLE = 4
HDMI_ACR_5_MULTIPLE_RESERVED = 5
HDMI_ACR_6_MULTIPLE_RESERVED = 6
HDMI_ACR_7_MULTIPLE_RESERVED = 7
HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_SELECT'
HDMI_ACR_SELECT__enumvalues = {
0: 'HDMI_ACR_SELECT_HW',
1: 'HDMI_ACR_SELECT_32K',
2: 'HDMI_ACR_SELECT_44K',
3: 'HDMI_ACR_SELECT_48K',
}
HDMI_ACR_SELECT_HW = 0
HDMI_ACR_SELECT_32K = 1
HDMI_ACR_SELECT_44K = 2
HDMI_ACR_SELECT_48K = 3
HDMI_ACR_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_SEND'
HDMI_ACR_SEND__enumvalues = {
0: 'HDMI_ACR_NOT_SEND',
1: 'HDMI_ACR_PKT_SEND',
}
HDMI_ACR_NOT_SEND = 0
HDMI_ACR_PKT_SEND = 1
HDMI_ACR_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ACR_SOURCE'
HDMI_ACR_SOURCE__enumvalues = {
0: 'HDMI_ACR_SOURCE_HW',
1: 'HDMI_ACR_SOURCE_SW',
}
HDMI_ACR_SOURCE_HW = 0
HDMI_ACR_SOURCE_SW = 1
HDMI_ACR_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_AUDIO_DELAY_EN'
HDMI_AUDIO_DELAY_EN__enumvalues = {
0: 'HDMI_AUDIO_DELAY_DISABLE',
1: 'HDMI_AUDIO_DELAY_58CLK',
2: 'HDMI_AUDIO_DELAY_56CLK',
3: 'HDMI_AUDIO_DELAY_RESERVED',
}
HDMI_AUDIO_DELAY_DISABLE = 0
HDMI_AUDIO_DELAY_58CLK = 1
HDMI_AUDIO_DELAY_56CLK = 2
HDMI_AUDIO_DELAY_RESERVED = 3
HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_AUDIO_INFO_CONT'
HDMI_AUDIO_INFO_CONT__enumvalues = {
0: 'HDMI_AUDIO_INFO_CONT_DISABLE',
1: 'HDMI_AUDIO_INFO_CONT_ENABLE',
}
HDMI_AUDIO_INFO_CONT_DISABLE = 0
HDMI_AUDIO_INFO_CONT_ENABLE = 1
HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_AUDIO_INFO_SEND'
HDMI_AUDIO_INFO_SEND__enumvalues = {
0: 'HDMI_AUDIO_INFO_NOT_SEND',
1: 'HDMI_AUDIO_INFO_PKT_SEND',
}
HDMI_AUDIO_INFO_NOT_SEND = 0
HDMI_AUDIO_INFO_PKT_SEND = 1
HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE'
HDMI_CLOCK_CHANNEL_RATE__enumvalues = {
0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE',
1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE',
}
HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0
HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1
HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_DATA_SCRAMBLE_EN'
HDMI_DATA_SCRAMBLE_EN__enumvalues = {
0: 'HDMI_DATA_SCRAMBLE_DISABLE',
1: 'HDMI_DATA_SCRAMBLE_ENABLE',
}
HDMI_DATA_SCRAMBLE_DISABLE = 0
HDMI_DATA_SCRAMBLE_ENABLE = 1
HDMI_DATA_SCRAMBLE_EN = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_DEEP_COLOR_DEPTH'
HDMI_DEEP_COLOR_DEPTH__enumvalues = {
0: 'HDMI_DEEP_COLOR_DEPTH_24BPP',
1: 'HDMI_DEEP_COLOR_DEPTH_30BPP',
2: 'HDMI_DEEP_COLOR_DEPTH_36BPP',
3: 'HDMI_DEEP_COLOR_DEPTH_48BPP',
}
HDMI_DEEP_COLOR_DEPTH_24BPP = 0
HDMI_DEEP_COLOR_DEPTH_30BPP = 1
HDMI_DEEP_COLOR_DEPTH_36BPP = 2
HDMI_DEEP_COLOR_DEPTH_48BPP = 3
HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_DEFAULT_PAHSE'
HDMI_DEFAULT_PAHSE__enumvalues = {
0: 'HDMI_DEFAULT_PHASE_IS_0',
1: 'HDMI_DEFAULT_PHASE_IS_1',
}
HDMI_DEFAULT_PHASE_IS_0 = 0
HDMI_DEFAULT_PHASE_IS_1 = 1
HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ERROR_ACK'
HDMI_ERROR_ACK__enumvalues = {
0: 'HDMI_ERROR_ACK_INT',
1: 'HDMI_ERROR_NOT_ACK',
}
HDMI_ERROR_ACK_INT = 0
HDMI_ERROR_NOT_ACK = 1
HDMI_ERROR_ACK = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ERROR_MASK'
HDMI_ERROR_MASK__enumvalues = {
0: 'HDMI_ERROR_MASK_INT',
1: 'HDMI_ERROR_NOT_MASK',
}
HDMI_ERROR_MASK_INT = 0
HDMI_ERROR_NOT_MASK = 1
HDMI_ERROR_MASK = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GC_AVMUTE'
HDMI_GC_AVMUTE__enumvalues = {
0: 'HDMI_GC_AVMUTE_SET',
1: 'HDMI_GC_AVMUTE_UNSET',
}
HDMI_GC_AVMUTE_SET = 0
HDMI_GC_AVMUTE_UNSET = 1
HDMI_GC_AVMUTE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GC_AVMUTE_CONT'
HDMI_GC_AVMUTE_CONT__enumvalues = {
0: 'HDMI_GC_AVMUTE_CONT_DISABLE',
1: 'HDMI_GC_AVMUTE_CONT_ENABLE',
}
HDMI_GC_AVMUTE_CONT_DISABLE = 0
HDMI_GC_AVMUTE_CONT_ENABLE = 1
HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GC_CONT'
HDMI_GC_CONT__enumvalues = {
0: 'HDMI_GC_CONT_DISABLE',
1: 'HDMI_GC_CONT_ENABLE',
}
HDMI_GC_CONT_DISABLE = 0
HDMI_GC_CONT_ENABLE = 1
HDMI_GC_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GC_SEND'
HDMI_GC_SEND__enumvalues = {
0: 'HDMI_GC_NOT_SEND',
1: 'HDMI_GC_PKT_SEND',
}
HDMI_GC_NOT_SEND = 0
HDMI_GC_PKT_SEND = 1
HDMI_GC_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GENERIC_CONT'
HDMI_GENERIC_CONT__enumvalues = {
0: 'HDMI_GENERIC_CONT_DISABLE',
1: 'HDMI_GENERIC_CONT_ENABLE',
}
HDMI_GENERIC_CONT_DISABLE = 0
HDMI_GENERIC_CONT_ENABLE = 1
HDMI_GENERIC_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_GENERIC_SEND'
HDMI_GENERIC_SEND__enumvalues = {
0: 'HDMI_GENERIC_NOT_SEND',
1: 'HDMI_GENERIC_PKT_SEND',
}
HDMI_GENERIC_NOT_SEND = 0
HDMI_GENERIC_PKT_SEND = 1
HDMI_GENERIC_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ISRC_CONT'
HDMI_ISRC_CONT__enumvalues = {
0: 'HDMI_ISRC_CONT_DISABLE',
1: 'HDMI_ISRC_CONT_ENABLE',
}
HDMI_ISRC_CONT_DISABLE = 0
HDMI_ISRC_CONT_ENABLE = 1
HDMI_ISRC_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_ISRC_SEND'
HDMI_ISRC_SEND__enumvalues = {
0: 'HDMI_ISRC_NOT_SEND',
1: 'HDMI_ISRC_PKT_SEND',
}
HDMI_ISRC_NOT_SEND = 0
HDMI_ISRC_PKT_SEND = 1
HDMI_ISRC_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_KEEPOUT_MODE'
HDMI_KEEPOUT_MODE__enumvalues = {
0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC',
1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC',
}
HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0
HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1
HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_METADATA_ENABLE'
HDMI_METADATA_ENABLE__enumvalues = {
0: 'HDMI_METADATA_NOT_SEND',
1: 'HDMI_METADATA_PKT_SEND',
}
HDMI_METADATA_NOT_SEND = 0
HDMI_METADATA_PKT_SEND = 1
HDMI_METADATA_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_MPEG_INFO_CONT'
HDMI_MPEG_INFO_CONT__enumvalues = {
0: 'HDMI_MPEG_INFO_CONT_DISABLE',
1: 'HDMI_MPEG_INFO_CONT_ENABLE',
}
HDMI_MPEG_INFO_CONT_DISABLE = 0
HDMI_MPEG_INFO_CONT_ENABLE = 1
HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_MPEG_INFO_SEND'
HDMI_MPEG_INFO_SEND__enumvalues = {
0: 'HDMI_MPEG_INFO_NOT_SEND',
1: 'HDMI_MPEG_INFO_PKT_SEND',
}
HDMI_MPEG_INFO_NOT_SEND = 0
HDMI_MPEG_INFO_PKT_SEND = 1
HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED'
HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = {
0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE',
1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE',
}
HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0
HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1
HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_NULL_SEND'
HDMI_NULL_SEND__enumvalues = {
0: 'HDMI_NULL_NOT_SEND',
1: 'HDMI_NULL_PKT_SEND',
}
HDMI_NULL_NOT_SEND = 0
HDMI_NULL_PKT_SEND = 1
HDMI_NULL_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_PACKET_GEN_VERSION'
HDMI_PACKET_GEN_VERSION__enumvalues = {
0: 'HDMI_PACKET_GEN_VERSION_OLD',
1: 'HDMI_PACKET_GEN_VERSION_NEW',
}
HDMI_PACKET_GEN_VERSION_OLD = 0
HDMI_PACKET_GEN_VERSION_NEW = 1
HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_PACKET_LINE_REFERENCE'
HDMI_PACKET_LINE_REFERENCE__enumvalues = {
0: 'HDMI_PKT_LINE_REF_VSYNC',
1: 'HDMI_PKT_LINE_REF_OTGSOF',
}
HDMI_PKT_LINE_REF_VSYNC = 0
HDMI_PKT_LINE_REF_OTGSOF = 1
HDMI_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE'
HDMI_PACKING_PHASE_OVERRIDE__enumvalues = {
0: 'HDMI_PACKING_PHASE_SET_BY_HW',
1: 'HDMI_PACKING_PHASE_SET_BY_SW',
}
HDMI_PACKING_PHASE_SET_BY_HW = 0
HDMI_PACKING_PHASE_SET_BY_SW = 1
HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT'
LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = {
0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS',
1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH',
}
LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0
LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1
LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_COLOR_FORMAT'
TMDS_COLOR_FORMAT__enumvalues = {
0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP',
1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB',
2: 'TMDS_COLOR_FORMAT_DUAL30BPP',
3: 'TMDS_COLOR_FORMAT_RESERVED',
}
TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0
TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1
TMDS_COLOR_FORMAT_DUAL30BPP = 2
TMDS_COLOR_FORMAT_RESERVED = 3
TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL0_DATA_INVERT'
TMDS_CTL0_DATA_INVERT__enumvalues = {
0: 'TMDS_CTL0_DATA_NORMAL',
1: 'TMDS_CTL0_DATA_INVERT_EN',
}
TMDS_CTL0_DATA_NORMAL = 0
TMDS_CTL0_DATA_INVERT_EN = 1
TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL0_DATA_MODULATION'
TMDS_CTL0_DATA_MODULATION__enumvalues = {
0: 'TMDS_CTL0_DATA_MODULATION_DISABLE',
1: 'TMDS_CTL0_DATA_MODULATION_BIT0',
2: 'TMDS_CTL0_DATA_MODULATION_BIT1',
3: 'TMDS_CTL0_DATA_MODULATION_BIT2',
}
TMDS_CTL0_DATA_MODULATION_DISABLE = 0
TMDS_CTL0_DATA_MODULATION_BIT0 = 1
TMDS_CTL0_DATA_MODULATION_BIT1 = 2
TMDS_CTL0_DATA_MODULATION_BIT2 = 3
TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL0_DATA_SEL'
TMDS_CTL0_DATA_SEL__enumvalues = {
0: 'TMDS_CTL0_DATA_SEL0_RESERVED',
1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE',
2: 'TMDS_CTL0_DATA_SEL2_VSYNC',
3: 'TMDS_CTL0_DATA_SEL3_RESERVED',
4: 'TMDS_CTL0_DATA_SEL4_HSYNC',
5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED',
6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA',
7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA',
}
TMDS_CTL0_DATA_SEL0_RESERVED = 0
TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1
TMDS_CTL0_DATA_SEL2_VSYNC = 2
TMDS_CTL0_DATA_SEL3_RESERVED = 3
TMDS_CTL0_DATA_SEL4_HSYNC = 4
TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5
TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6
TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7
TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN'
TMDS_CTL0_PATTERN_OUT_EN__enumvalues = {
0: 'TMDS_CTL0_PATTERN_OUT_DISABLE',
1: 'TMDS_CTL0_PATTERN_OUT_ENABLE',
}
TMDS_CTL0_PATTERN_OUT_DISABLE = 0
TMDS_CTL0_PATTERN_OUT_ENABLE = 1
TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL1_DATA_INVERT'
TMDS_CTL1_DATA_INVERT__enumvalues = {
0: 'TMDS_CTL1_DATA_NORMAL',
1: 'TMDS_CTL1_DATA_INVERT_EN',
}
TMDS_CTL1_DATA_NORMAL = 0
TMDS_CTL1_DATA_INVERT_EN = 1
TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL1_DATA_MODULATION'
TMDS_CTL1_DATA_MODULATION__enumvalues = {
0: 'TMDS_CTL1_DATA_MODULATION_DISABLE',
1: 'TMDS_CTL1_DATA_MODULATION_BIT0',
2: 'TMDS_CTL1_DATA_MODULATION_BIT1',
3: 'TMDS_CTL1_DATA_MODULATION_BIT2',
}
TMDS_CTL1_DATA_MODULATION_DISABLE = 0
TMDS_CTL1_DATA_MODULATION_BIT0 = 1
TMDS_CTL1_DATA_MODULATION_BIT1 = 2
TMDS_CTL1_DATA_MODULATION_BIT2 = 3
TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL1_DATA_SEL'
TMDS_CTL1_DATA_SEL__enumvalues = {
0: 'TMDS_CTL1_DATA_SEL0_RESERVED',
1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE',
2: 'TMDS_CTL1_DATA_SEL2_VSYNC',
3: 'TMDS_CTL1_DATA_SEL3_RESERVED',
4: 'TMDS_CTL1_DATA_SEL4_HSYNC',
5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED',
6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME',
7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED',
}
TMDS_CTL1_DATA_SEL0_RESERVED = 0
TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1
TMDS_CTL1_DATA_SEL2_VSYNC = 2
TMDS_CTL1_DATA_SEL3_RESERVED = 3
TMDS_CTL1_DATA_SEL4_HSYNC = 4
TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5
TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6
TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7
TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN'
TMDS_CTL1_PATTERN_OUT_EN__enumvalues = {
0: 'TMDS_CTL1_PATTERN_OUT_DISABLE',
1: 'TMDS_CTL1_PATTERN_OUT_ENABLE',
}
TMDS_CTL1_PATTERN_OUT_DISABLE = 0
TMDS_CTL1_PATTERN_OUT_ENABLE = 1
TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL2_DATA_INVERT'
TMDS_CTL2_DATA_INVERT__enumvalues = {
0: 'TMDS_CTL2_DATA_NORMAL',
1: 'TMDS_CTL2_DATA_INVERT_EN',
}
TMDS_CTL2_DATA_NORMAL = 0
TMDS_CTL2_DATA_INVERT_EN = 1
TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL2_DATA_MODULATION'
TMDS_CTL2_DATA_MODULATION__enumvalues = {
0: 'TMDS_CTL2_DATA_MODULATION_DISABLE',
1: 'TMDS_CTL2_DATA_MODULATION_BIT0',
2: 'TMDS_CTL2_DATA_MODULATION_BIT1',
3: 'TMDS_CTL2_DATA_MODULATION_BIT2',
}
TMDS_CTL2_DATA_MODULATION_DISABLE = 0
TMDS_CTL2_DATA_MODULATION_BIT0 = 1
TMDS_CTL2_DATA_MODULATION_BIT1 = 2
TMDS_CTL2_DATA_MODULATION_BIT2 = 3
TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL2_DATA_SEL'
TMDS_CTL2_DATA_SEL__enumvalues = {
0: 'TMDS_CTL2_DATA_SEL0_RESERVED',
1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE',
2: 'TMDS_CTL2_DATA_SEL2_VSYNC',
3: 'TMDS_CTL2_DATA_SEL3_RESERVED',
4: 'TMDS_CTL2_DATA_SEL4_HSYNC',
5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED',
6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME',
7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED',
}
TMDS_CTL2_DATA_SEL0_RESERVED = 0
TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1
TMDS_CTL2_DATA_SEL2_VSYNC = 2
TMDS_CTL2_DATA_SEL3_RESERVED = 3
TMDS_CTL2_DATA_SEL4_HSYNC = 4
TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5
TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6
TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7
TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN'
TMDS_CTL2_PATTERN_OUT_EN__enumvalues = {
0: 'TMDS_CTL2_PATTERN_OUT_DISABLE',
1: 'TMDS_CTL2_PATTERN_OUT_ENABLE',
}
TMDS_CTL2_PATTERN_OUT_DISABLE = 0
TMDS_CTL2_PATTERN_OUT_ENABLE = 1
TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL3_DATA_INVERT'
TMDS_CTL3_DATA_INVERT__enumvalues = {
0: 'TMDS_CTL3_DATA_NORMAL',
1: 'TMDS_CTL3_DATA_INVERT_EN',
}
TMDS_CTL3_DATA_NORMAL = 0
TMDS_CTL3_DATA_INVERT_EN = 1
TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL3_DATA_MODULATION'
TMDS_CTL3_DATA_MODULATION__enumvalues = {
0: 'TMDS_CTL3_DATA_MODULATION_DISABLE',
1: 'TMDS_CTL3_DATA_MODULATION_BIT0',
2: 'TMDS_CTL3_DATA_MODULATION_BIT1',
3: 'TMDS_CTL3_DATA_MODULATION_BIT2',
}
TMDS_CTL3_DATA_MODULATION_DISABLE = 0
TMDS_CTL3_DATA_MODULATION_BIT0 = 1
TMDS_CTL3_DATA_MODULATION_BIT1 = 2
TMDS_CTL3_DATA_MODULATION_BIT2 = 3
TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL3_DATA_SEL'
TMDS_CTL3_DATA_SEL__enumvalues = {
0: 'TMDS_CTL3_DATA_SEL0_RESERVED',
1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE',
2: 'TMDS_CTL3_DATA_SEL2_VSYNC',
3: 'TMDS_CTL3_DATA_SEL3_RESERVED',
4: 'TMDS_CTL3_DATA_SEL4_HSYNC',
5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED',
6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME',
7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED',
}
TMDS_CTL3_DATA_SEL0_RESERVED = 0
TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1
TMDS_CTL3_DATA_SEL2_VSYNC = 2
TMDS_CTL3_DATA_SEL3_RESERVED = 3
TMDS_CTL3_DATA_SEL4_HSYNC = 4
TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5
TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6
TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7
TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN'
TMDS_CTL3_PATTERN_OUT_EN__enumvalues = {
0: 'TMDS_CTL3_PATTERN_OUT_DISABLE',
1: 'TMDS_CTL3_PATTERN_OUT_ENABLE',
}
TMDS_CTL3_PATTERN_OUT_DISABLE = 0
TMDS_CTL3_PATTERN_OUT_ENABLE = 1
TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL'
TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = {
0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS',
1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL',
}
TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0
TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1
TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_PIXEL_ENCODING'
TMDS_PIXEL_ENCODING__enumvalues = {
0: 'TMDS_PIXEL_ENCODING_444_OR_420',
1: 'TMDS_PIXEL_ENCODING_422',
}
TMDS_PIXEL_ENCODING_444_OR_420 = 0
TMDS_PIXEL_ENCODING_422 = 1
TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA'
TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = {
0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0',
1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1',
2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2',
3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA',
}
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2
TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3
TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB'
TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = {
0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0',
1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1',
2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2',
3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA',
}
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2
TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3
TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG'
TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = {
0: 'TMDS_STEREOSYNC_CTL0',
1: 'TMDS_STEREOSYNC_CTL1',
2: 'TMDS_STEREOSYNC_CTL2',
3: 'TMDS_STEREOSYNC_CTL3',
}
TMDS_STEREOSYNC_CTL0 = 0
TMDS_STEREOSYNC_CTL1 = 1
TMDS_STEREOSYNC_CTL2 = 2
TMDS_STEREOSYNC_CTL3 = 3
TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_SYNC_PHASE'
TMDS_SYNC_PHASE__enumvalues = {
0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START',
1: 'TMDS_SYNC_PHASE_ON_FRAME_START',
}
TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0
TMDS_SYNC_PHASE_ON_FRAME_START = 1
TMDS_SYNC_PHASE = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA'
TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = {
0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT',
1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT',
}
TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0
TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1
TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB'
TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = {
0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT',
1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT',
}
TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0
TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1
TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA'
TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = {
0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK',
1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK',
}
TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0
TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1
TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB'
TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = {
0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK',
1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK',
}
TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0
TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1
TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN'
TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = {
0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW',
1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW',
}
TMDS_TRANSMITTER_PLLSEL_BY_HW = 0
TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1
TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK'
TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE',
1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON',
2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON',
3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE',
}
TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3
TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN'
TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = {
0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE',
1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE',
}
TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0
TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1
TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK'
TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD',
1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD',
}
TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0
TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1
TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS'
TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = {
0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK',
1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS',
}
TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0
TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1
TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS'
TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = {
0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK',
1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS',
}
TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0
TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1
TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK'
TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE',
1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE',
}
TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0
TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1
TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK'
TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE',
1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE',
}
TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0
TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1
TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK'
TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = {
0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE',
1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE',
}
TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0
TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1
TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY'
DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = {
0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW',
1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW',
2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC',
3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS',
}
DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0
DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1
DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2
DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3
DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG'
DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = {
0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG',
1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG',
}
DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0
DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1
DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ'
DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = {
0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ',
1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ',
}
DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0
DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1
DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ARB_STATUS'
DP_AUX_ARB_STATUS__enumvalues = {
0: 'DP_AUX_IDLE',
1: 'DP_AUX_IN_USE_LS',
2: 'DP_AUX_IN_USE_GTC',
3: 'DP_AUX_IN_USE_SW',
4: 'DP_AUX_IN_USE_PHYWAKE',
}
DP_AUX_IDLE = 0
DP_AUX_IN_USE_LS = 1
DP_AUX_IN_USE_GTC = 2
DP_AUX_IN_USE_SW = 3
DP_AUX_IN_USE_PHYWAKE = 4
DP_AUX_ARB_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_CONTROL_HPD_SEL'
DP_AUX_CONTROL_HPD_SEL__enumvalues = {
0: 'DP_AUX_CONTROL_HPD1_SELECTED',
1: 'DP_AUX_CONTROL_HPD2_SELECTED',
2: 'DP_AUX_CONTROL_HPD3_SELECTED',
3: 'DP_AUX_CONTROL_HPD4_SELECTED',
4: 'DP_AUX_CONTROL_HPD5_SELECTED',
5: 'DP_AUX_CONTROL_NO_HPD_SELECTED',
}
DP_AUX_CONTROL_HPD1_SELECTED = 0
DP_AUX_CONTROL_HPD2_SELECTED = 1
DP_AUX_CONTROL_HPD3_SELECTED = 2
DP_AUX_CONTROL_HPD4_SELECTED = 3
DP_AUX_CONTROL_HPD5_SELECTED = 4
DP_AUX_CONTROL_NO_HPD_SELECTED = 5
DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_CONTROL_TEST_MODE'
DP_AUX_CONTROL_TEST_MODE__enumvalues = {
0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE',
1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE',
}
DP_AUX_CONTROL_TEST_MODE_DISABLE = 0
DP_AUX_CONTROL_TEST_MODE_ENABLE = 1
DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK'
DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = {
0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK',
1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK',
}
ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0
ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1
DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT'
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
}
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START'
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START',
1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START',
}
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP'
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP',
1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP',
}
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1
DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN'
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES',
1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES',
2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES',
3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED',
}
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN'
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS',
1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS',
2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS',
3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS',
}
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW'
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD',
1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD',
2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD',
3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD',
4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD',
5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD',
6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD',
7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD',
}
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW'
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = {
0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD',
1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD',
2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD',
3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD',
4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD',
5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD',
6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD',
7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD',
}
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7
DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD'
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = {
0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2',
1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4',
2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8',
3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16',
4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32',
5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64',
6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128',
7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256',
}
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7
DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY'
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = {
0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0',
1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US',
2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US',
3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US',
4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US',
5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US',
}
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE'
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = {
0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ',
1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ',
2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ',
3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ',
}
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL'
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = {
0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK',
1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF',
}
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK'
DP_AUX_ERR_OCCURRED_ACK__enumvalues = {
0: 'DP_AUX_ERR_OCCURRED__NOT_ACK',
1: 'DP_AUX_ERR_OCCURRED__ACK',
}
DP_AUX_ERR_OCCURRED__NOT_ACK = 0
DP_AUX_ERR_OCCURRED__ACK = 1
DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ'
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = {
0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX',
1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX',
}
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW'
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = {
0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US',
1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US',
2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US',
3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US',
}
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT'
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = {
0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS',
1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS',
2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS',
3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED',
}
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN'
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = {
0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0',
1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64',
2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128',
3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256',
}
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3
DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_INT_ACK'
DP_AUX_INT_ACK__enumvalues = {
0: 'DP_AUX_INT__NOT_ACK',
1: 'DP_AUX_INT__ACK',
}
DP_AUX_INT__NOT_ACK = 0
DP_AUX_INT__ACK = 1
DP_AUX_INT_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_LS_UPDATE_ACK'
DP_AUX_LS_UPDATE_ACK__enumvalues = {
0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK',
1: 'DP_AUX_INT_LS_UPDATE_ACK',
}
DP_AUX_INT_LS_UPDATE_NOT_ACK = 0
DP_AUX_INT_LS_UPDATE_ACK = 1
DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_PHY_WAKE_PRIORITY'
DP_AUX_PHY_WAKE_PRIORITY__enumvalues = {
0: 'DP_AUX_PHY_WAKE_HIGH_PRIORITY',
1: 'DP_AUX_PHY_WAKE_LOW_PRIORITY',
}
DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0
DP_AUX_PHY_WAKE_LOW_PRIORITY = 1
DP_AUX_PHY_WAKE_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK'
DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = {
0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK',
1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK',
}
DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0
DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1
DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_RESET'
DP_AUX_RESET__enumvalues = {
0: 'DP_AUX_RESET_DEASSERTED',
1: 'DP_AUX_RESET_ASSERTED',
}
DP_AUX_RESET_DEASSERTED = 0
DP_AUX_RESET_ASSERTED = 1
DP_AUX_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_RESET_DONE'
DP_AUX_RESET_DONE__enumvalues = {
0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE',
1: 'DP_AUX_RESET_SEQUENCE_DONE',
}
DP_AUX_RESET_SEQUENCE_NOT_DONE = 0
DP_AUX_RESET_SEQUENCE_DONE = 1
DP_AUX_RESET_DONE = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_RX_TIMEOUT_LEN_MUL'
DP_AUX_RX_TIMEOUT_LEN_MUL__enumvalues = {
0: 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL',
1: 'DP_AUX_RX_TIMEOUT_LEN_MUL_2',
2: 'DP_AUX_RX_TIMEOUT_LEN_MUL_4',
3: 'DP_AUX_RX_TIMEOUT_LEN_MUL_8',
}
DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0
DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 1
DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 2
DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 3
DP_AUX_RX_TIMEOUT_LEN_MUL = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG'
DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = {
0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG',
1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG',
}
DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0
DP_AUX_SW_CONTROL_LS_READ__TRIG = 1
DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO'
DP_AUX_SW_CONTROL_SW_GO__enumvalues = {
0: 'DP_AUX_SW_CONTROL_SW__NOT_GO',
1: 'DP_AUX_SW_CONTROL_SW__GO',
}
DP_AUX_SW_CONTROL_SW__NOT_GO = 0
DP_AUX_SW_CONTROL_SW__GO = 1
DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum
# values for enumeration 'DP_AUX_TX_PRECHARGE_LEN_MUL'
DP_AUX_TX_PRECHARGE_LEN_MUL__enumvalues = {
0: 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL',
1: 'DP_AUX_TX_PRECHARGE_LEN_MUL_2',
2: 'DP_AUX_TX_PRECHARGE_LEN_MUL_4',
3: 'DP_AUX_TX_PRECHARGE_LEN_MUL_8',
}
DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0
DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 1
DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 2
DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 3
DP_AUX_TX_PRECHARGE_LEN_MUL = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ACK'
DOUT_I2C_ACK__enumvalues = {
0: 'DOUT_I2C_NO_ACK',
1: 'DOUT_I2C_ACK_TO_CLEAN',
}
DOUT_I2C_NO_ACK = 0
DOUT_I2C_ACK_TO_CLEAN = 1
DOUT_I2C_ACK = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER'
DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = {
0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER',
1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER',
}
DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0
DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1
DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG'
DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = {
0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG',
1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG',
}
DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0
DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1
DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO'
DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = {
0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED',
1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED',
}
DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0
DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1
DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY'
DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = {
0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL',
1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH',
2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED',
3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED',
}
DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0
DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1
DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2
DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3
DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ'
DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = {
0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ',
1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ',
}
DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0
DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1
DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_DBG_REF_SEL'
DOUT_I2C_CONTROL_DBG_REF_SEL__enumvalues = {
0: 'DOUT_I2C_CONTROL_NORMAL_DEBUG',
1: 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG',
}
DOUT_I2C_CONTROL_NORMAL_DEBUG = 0
DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 1
DOUT_I2C_CONTROL_DBG_REF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT'
DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = {
0: 'DOUT_I2C_CONTROL_SELECT_DDC1',
1: 'DOUT_I2C_CONTROL_SELECT_DDC2',
2: 'DOUT_I2C_CONTROL_SELECT_DDC3',
3: 'DOUT_I2C_CONTROL_SELECT_DDC4',
4: 'DOUT_I2C_CONTROL_SELECT_DDC5',
5: 'DOUT_I2C_CONTROL_SELECT_DDCVGA',
}
DOUT_I2C_CONTROL_SELECT_DDC1 = 0
DOUT_I2C_CONTROL_SELECT_DDC2 = 1
DOUT_I2C_CONTROL_SELECT_DDC3 = 2
DOUT_I2C_CONTROL_SELECT_DDC4 = 3
DOUT_I2C_CONTROL_SELECT_DDC5 = 4
DOUT_I2C_CONTROL_SELECT_DDCVGA = 5
DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_GO'
DOUT_I2C_CONTROL_GO__enumvalues = {
0: 'DOUT_I2C_CONTROL_STOP_TRANSFER',
1: 'DOUT_I2C_CONTROL_START_TRANSFER',
}
DOUT_I2C_CONTROL_STOP_TRANSFER = 0
DOUT_I2C_CONTROL_START_TRANSFER = 1
DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET'
DOUT_I2C_CONTROL_SEND_RESET__enumvalues = {
0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET',
1: 'DOUT_I2C_CONTROL__SEND_RESET',
}
DOUT_I2C_CONTROL__NOT_SEND_RESET = 0
DOUT_I2C_CONTROL__SEND_RESET = 1
DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH'
DOUT_I2C_CONTROL_SEND_RESET_LENGTH__enumvalues = {
0: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9',
1: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10',
}
DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0
DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 1
DOUT_I2C_CONTROL_SEND_RESET_LENGTH = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET'
DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = {
0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER',
1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER',
}
DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0
DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1
DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET'
DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = {
0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS',
1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS',
}
DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0
DOUT_I2C_CONTROL_RESET_SW_STATUS = 1
DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT'
DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = {
0: 'DOUT_I2C_CONTROL_TRANS0',
1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1',
2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2',
3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3',
}
DOUT_I2C_CONTROL_TRANS0 = 0
DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1
DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2
DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3
DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE'
DOUT_I2C_DATA_INDEX_WRITE__enumvalues = {
0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE',
1: 'DOUT_I2C_DATA__INDEX_WRITE',
}
DOUT_I2C_DATA__NOT_INDEX_WRITE = 0
DOUT_I2C_DATA__INDEX_WRITE = 1
DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN'
DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = {
0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR',
1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL',
}
DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0
DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1
DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN'
DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = {
0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR',
1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA',
}
DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0
DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1
DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL'
DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = {
0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS',
1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS',
}
DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0
DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1
DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE'
DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = {
0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT',
1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT',
}
DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0
DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1
DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD'
DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = {
0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO',
1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE',
2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE',
3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE',
}
DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0
DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1
DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2
DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3
DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET'
DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = {
0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION',
1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION',
}
DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0
DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1
DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE'
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = {
0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL',
1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE',
}
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1
DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK'
DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = {
0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS',
1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS',
}
DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0
DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1
DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum
# values for enumeration 'CLOCK_GATING_EN'
CLOCK_GATING_EN__enumvalues = {
0: 'CLOCK_GATING_ENABLE',
1: 'CLOCK_GATING_DISABLE',
}
CLOCK_GATING_ENABLE = 0
CLOCK_GATING_DISABLE = 1
CLOCK_GATING_EN = ctypes.c_uint32 # enum
# values for enumeration 'DAC_MUX_SELECT'
DAC_MUX_SELECT__enumvalues = {
0: 'DAC_MUX_SELECT_DACA',
1: 'DAC_MUX_SELECT_DACB',
}
DAC_MUX_SELECT_DACA = 0
DAC_MUX_SELECT_DACB = 1
DAC_MUX_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_DIS_CTRL'
DIOMEM_PWR_DIS_CTRL__enumvalues = {
0: 'DIOMEM_ENABLE_MEM_PWR_CTRL',
1: 'DIOMEM_DISABLE_MEM_PWR_CTRL',
}
DIOMEM_ENABLE_MEM_PWR_CTRL = 0
DIOMEM_DISABLE_MEM_PWR_CTRL = 1
DIOMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_FORCE_CTRL'
DIOMEM_PWR_FORCE_CTRL__enumvalues = {
0: 'DIOMEM_NO_FORCE_REQUEST',
1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST',
3: 'DIOMEM_FORCE_SHUT_DOWN_REQUEST',
}
DIOMEM_NO_FORCE_REQUEST = 0
DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 1
DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 2
DIOMEM_FORCE_SHUT_DOWN_REQUEST = 3
DIOMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_FORCE_CTRL2'
DIOMEM_PWR_FORCE_CTRL2__enumvalues = {
0: 'DIOMEM_NO_FORCE_REQ',
1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQ',
}
DIOMEM_NO_FORCE_REQ = 0
DIOMEM_FORCE_LIGHT_SLEEP_REQ = 1
DIOMEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_SEL_CTRL'
DIOMEM_PWR_SEL_CTRL__enumvalues = {
0: 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE',
1: 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE',
2: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE',
}
DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0
DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 1
DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 2
DIOMEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'DIOMEM_PWR_SEL_CTRL2'
DIOMEM_PWR_SEL_CTRL2__enumvalues = {
0: 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN',
1: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN',
}
DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0
DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 1
DIOMEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum
# values for enumeration 'DIO_DBG_BLOCK_SEL'
DIO_DBG_BLOCK_SEL__enumvalues = {
0: 'DIO_DBG_BLOCK_SEL_DIO',
11: 'DIO_DBG_BLOCK_SEL_DIGFE_A',
12: 'DIO_DBG_BLOCK_SEL_DIGFE_B',
13: 'DIO_DBG_BLOCK_SEL_DIGFE_C',
14: 'DIO_DBG_BLOCK_SEL_DIGFE_D',
15: 'DIO_DBG_BLOCK_SEL_DIGFE_E',
18: 'DIO_DBG_BLOCK_SEL_DIGA',
19: 'DIO_DBG_BLOCK_SEL_DIGB',
20: 'DIO_DBG_BLOCK_SEL_DIGC',
21: 'DIO_DBG_BLOCK_SEL_DIGD',
22: 'DIO_DBG_BLOCK_SEL_DIGE',
25: 'DIO_DBG_BLOCK_SEL_DPFE_A',
26: 'DIO_DBG_BLOCK_SEL_DPFE_B',
27: 'DIO_DBG_BLOCK_SEL_DPFE_C',
28: 'DIO_DBG_BLOCK_SEL_DPFE_D',
29: 'DIO_DBG_BLOCK_SEL_DPFE_E',
32: 'DIO_DBG_BLOCK_SEL_DPA',
33: 'DIO_DBG_BLOCK_SEL_DPB',
34: 'DIO_DBG_BLOCK_SEL_DPC',
35: 'DIO_DBG_BLOCK_SEL_DPD',
36: 'DIO_DBG_BLOCK_SEL_DPE',
39: 'DIO_DBG_BLOCK_SEL_AUX0',
40: 'DIO_DBG_BLOCK_SEL_AUX1',
41: 'DIO_DBG_BLOCK_SEL_AUX2',
42: 'DIO_DBG_BLOCK_SEL_AUX3',
43: 'DIO_DBG_BLOCK_SEL_AUX4',
45: 'DIO_DBG_BLOCK_SEL_PERFMON_DIO',
46: 'DIO_DBG_BLOCK_SEL_RESERVED',
}
DIO_DBG_BLOCK_SEL_DIO = 0
DIO_DBG_BLOCK_SEL_DIGFE_A = 11
DIO_DBG_BLOCK_SEL_DIGFE_B = 12
DIO_DBG_BLOCK_SEL_DIGFE_C = 13
DIO_DBG_BLOCK_SEL_DIGFE_D = 14
DIO_DBG_BLOCK_SEL_DIGFE_E = 15
DIO_DBG_BLOCK_SEL_DIGA = 18
DIO_DBG_BLOCK_SEL_DIGB = 19
DIO_DBG_BLOCK_SEL_DIGC = 20
DIO_DBG_BLOCK_SEL_DIGD = 21
DIO_DBG_BLOCK_SEL_DIGE = 22
DIO_DBG_BLOCK_SEL_DPFE_A = 25
DIO_DBG_BLOCK_SEL_DPFE_B = 26
DIO_DBG_BLOCK_SEL_DPFE_C = 27
DIO_DBG_BLOCK_SEL_DPFE_D = 28
DIO_DBG_BLOCK_SEL_DPFE_E = 29
DIO_DBG_BLOCK_SEL_DPA = 32
DIO_DBG_BLOCK_SEL_DPB = 33
DIO_DBG_BLOCK_SEL_DPC = 34
DIO_DBG_BLOCK_SEL_DPD = 35
DIO_DBG_BLOCK_SEL_DPE = 36
DIO_DBG_BLOCK_SEL_AUX0 = 39
DIO_DBG_BLOCK_SEL_AUX1 = 40
DIO_DBG_BLOCK_SEL_AUX2 = 41
DIO_DBG_BLOCK_SEL_AUX3 = 42
DIO_DBG_BLOCK_SEL_AUX4 = 43
DIO_DBG_BLOCK_SEL_PERFMON_DIO = 45
DIO_DBG_BLOCK_SEL_RESERVED = 46
DIO_DBG_BLOCK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE'
DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = {
0: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL',
1: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE',
}
DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0
DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1
DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE'
DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE__enumvalues = {
0: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0',
1: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1',
}
DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0
DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 1
DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DIO_DCN_ACTIVE_STATUS'
ENUM_DIO_DCN_ACTIVE_STATUS__enumvalues = {
0: 'ENUM_DCN_NOT_ACTIVE',
1: 'ENUM_DCN_ACTIVE',
}
ENUM_DCN_NOT_ACTIVE = 0
ENUM_DCN_ACTIVE = 1
ENUM_DIO_DCN_ACTIVE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_STEREOSYNC_SEL'
GENERIC_STEREOSYNC_SEL__enumvalues = {
0: 'GENERIC_STEREOSYNC_SEL_D1',
1: 'GENERIC_STEREOSYNC_SEL_D2',
2: 'GENERIC_STEREOSYNC_SEL_D3',
3: 'GENERIC_STEREOSYNC_SEL_D4',
4: 'GENERIC_STEREOSYNC_SEL_RESERVED',
}
GENERIC_STEREOSYNC_SEL_D1 = 0
GENERIC_STEREOSYNC_SEL_D2 = 1
GENERIC_STEREOSYNC_SEL_D3 = 2
GENERIC_STEREOSYNC_SEL_D4 = 3
GENERIC_STEREOSYNC_SEL_RESERVED = 4
GENERIC_STEREOSYNC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PM_ASSERT_RESET'
PM_ASSERT_RESET__enumvalues = {
0: 'PM_ASSERT_RESET_0',
1: 'PM_ASSERT_RESET_1',
}
PM_ASSERT_RESET_0 = 0
PM_ASSERT_RESET_1 = 1
PM_ASSERT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'SOFT_RESET'
SOFT_RESET__enumvalues = {
0: 'SOFT_RESET_0',
1: 'SOFT_RESET_1',
}
SOFT_RESET_0 = 0
SOFT_RESET_1 = 1
SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'TMDS_MUX_SELECT'
TMDS_MUX_SELECT__enumvalues = {
0: 'TMDS_MUX_SELECT_B',
1: 'TMDS_MUX_SELECT_G',
2: 'TMDS_MUX_SELECT_R',
3: 'TMDS_MUX_SELECT_RESERVED',
}
TMDS_MUX_SELECT_B = 0
TMDS_MUX_SELECT_G = 1
TMDS_MUX_SELECT_R = 2
TMDS_MUX_SELECT_RESERVED = 3
TMDS_MUX_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DME_MEM_POWER_STATE_ENUM'
DME_MEM_POWER_STATE_ENUM__enumvalues = {
0: 'DME_MEM_POWER_STATE_ENUM_ON',
1: 'DME_MEM_POWER_STATE_ENUM_LS',
2: 'DME_MEM_POWER_STATE_ENUM_DS',
3: 'DME_MEM_POWER_STATE_ENUM_SD',
}
DME_MEM_POWER_STATE_ENUM_ON = 0
DME_MEM_POWER_STATE_ENUM_LS = 1
DME_MEM_POWER_STATE_ENUM_DS = 2
DME_MEM_POWER_STATE_ENUM_SD = 3
DME_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DME_MEM_PWR_DIS_CTRL'
DME_MEM_PWR_DIS_CTRL__enumvalues = {
0: 'DME_MEM_ENABLE_MEM_PWR_CTRL',
1: 'DME_MEM_DISABLE_MEM_PWR_CTRL',
}
DME_MEM_ENABLE_MEM_PWR_CTRL = 0
DME_MEM_DISABLE_MEM_PWR_CTRL = 1
DME_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'DME_MEM_PWR_FORCE_CTRL'
DME_MEM_PWR_FORCE_CTRL__enumvalues = {
0: 'DME_MEM_NO_FORCE_REQUEST',
1: 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST',
3: 'DME_MEM_FORCE_SHUT_DOWN_REQUEST',
}
DME_MEM_NO_FORCE_REQUEST = 0
DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1
DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 2
DME_MEM_FORCE_SHUT_DOWN_REQUEST = 3
DME_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'METADATA_HUBP_SEL'
METADATA_HUBP_SEL__enumvalues = {
0: 'METADATA_HUBP_SEL_0',
1: 'METADATA_HUBP_SEL_1',
2: 'METADATA_HUBP_SEL_2',
3: 'METADATA_HUBP_SEL_3',
4: 'METADATA_HUBP_SEL_RESERVED',
}
METADATA_HUBP_SEL_0 = 0
METADATA_HUBP_SEL_1 = 1
METADATA_HUBP_SEL_2 = 2
METADATA_HUBP_SEL_3 = 3
METADATA_HUBP_SEL_RESERVED = 4
METADATA_HUBP_SEL = ctypes.c_uint32 # enum
# values for enumeration 'METADATA_STREAM_TYPE_SEL'
METADATA_STREAM_TYPE_SEL__enumvalues = {
0: 'METADATA_STREAM_DP',
1: 'METADATA_STREAM_DVE',
}
METADATA_STREAM_DP = 0
METADATA_STREAM_DVE = 1
METADATA_STREAM_TYPE_SEL = ctypes.c_uint32 # enum
# values for enumeration 'VPG_MEM_PWR_DIS_CTRL'
VPG_MEM_PWR_DIS_CTRL__enumvalues = {
0: 'VPG_MEM_ENABLE_MEM_PWR_CTRL',
1: 'VPG_MEM_DISABLE_MEM_PWR_CTRL',
}
VPG_MEM_ENABLE_MEM_PWR_CTRL = 0
VPG_MEM_DISABLE_MEM_PWR_CTRL = 1
VPG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'VPG_MEM_PWR_FORCE_CTRL'
VPG_MEM_PWR_FORCE_CTRL__enumvalues = {
0: 'VPG_MEM_NO_FORCE_REQ',
1: 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ',
}
VPG_MEM_NO_FORCE_REQ = 0
VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 1
VPG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_ACP_TYPE'
AFMT_ACP_TYPE__enumvalues = {
0: 'ACP_TYPE_GENERIC_AUDIO',
1: 'ACP_TYPE_ICE60958_AUDIO',
2: 'ACP_TYPE_DVD_AUDIO',
3: 'ACP_TYPE_SUPER_AUDIO_CD',
}
ACP_TYPE_GENERIC_AUDIO = 0
ACP_TYPE_ICE60958_AUDIO = 1
ACP_TYPE_DVD_AUDIO = 2
ACP_TYPE_SUPER_AUDIO_CD = 3
AFMT_ACP_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL'
AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = {
0: 'AFMT_AUDIO_CRC_CH0_SIG',
1: 'AFMT_AUDIO_CRC_CH1_SIG',
2: 'AFMT_AUDIO_CRC_CH2_SIG',
3: 'AFMT_AUDIO_CRC_CH3_SIG',
4: 'AFMT_AUDIO_CRC_CH4_SIG',
5: 'AFMT_AUDIO_CRC_CH5_SIG',
6: 'AFMT_AUDIO_CRC_CH6_SIG',
7: 'AFMT_AUDIO_CRC_CH7_SIG',
8: 'AFMT_AUDIO_CRC_RESERVED_8',
9: 'AFMT_AUDIO_CRC_RESERVED_9',
10: 'AFMT_AUDIO_CRC_RESERVED_10',
11: 'AFMT_AUDIO_CRC_RESERVED_11',
12: 'AFMT_AUDIO_CRC_RESERVED_12',
13: 'AFMT_AUDIO_CRC_RESERVED_13',
14: 'AFMT_AUDIO_CRC_RESERVED_14',
15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT',
}
AFMT_AUDIO_CRC_CH0_SIG = 0
AFMT_AUDIO_CRC_CH1_SIG = 1
AFMT_AUDIO_CRC_CH2_SIG = 2
AFMT_AUDIO_CRC_CH3_SIG = 3
AFMT_AUDIO_CRC_CH4_SIG = 4
AFMT_AUDIO_CRC_CH5_SIG = 5
AFMT_AUDIO_CRC_CH6_SIG = 6
AFMT_AUDIO_CRC_CH7_SIG = 7
AFMT_AUDIO_CRC_RESERVED_8 = 8
AFMT_AUDIO_CRC_RESERVED_9 = 9
AFMT_AUDIO_CRC_RESERVED_10 = 10
AFMT_AUDIO_CRC_RESERVED_11 = 11
AFMT_AUDIO_CRC_RESERVED_12 = 12
AFMT_AUDIO_CRC_RESERVED_13 = 13
AFMT_AUDIO_CRC_RESERVED_14 = 14
AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15
AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT'
AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = {
0: 'AFMT_AUDIO_CRC_ONESHOT',
1: 'AFMT_AUDIO_CRC_AUTO_RESTART',
}
AFMT_AUDIO_CRC_ONESHOT = 0
AFMT_AUDIO_CRC_AUTO_RESTART = 1
AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE'
AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = {
0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT',
1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT',
}
AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0
AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1
AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD'
AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = {
0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS',
1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER',
}
AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0
AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1
AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND'
AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = {
0: 'AFMT_AUDIO_PACKET_SENT_DISABLED',
1: 'AFMT_AUDIO_PACKET_SENT_ENABLED',
}
AFMT_AUDIO_PACKET_SENT_DISABLED = 0
AFMT_AUDIO_PACKET_SENT_ENABLED = 1
AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS'
AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = {
0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED',
1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED',
}
AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0
AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1
AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT'
AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = {
0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0',
1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1',
2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2',
3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3',
4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4',
5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5',
}
AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0
AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1
AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2
AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3
AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4
AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5
AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS'
AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = {
0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS',
1: 'HDMI_SEND_MAX_AUDIO_PACKETS',
}
HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0
HDMI_SEND_MAX_AUDIO_PACKETS = 1
AFMT_HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE'
AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = {
0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK',
1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS',
}
AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0
AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1
AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK'
AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = {
0: 'AFMT_INTERRUPT_DISABLE',
1: 'AFMT_INTERRUPT_ENABLE',
}
AFMT_INTERRUPT_DISABLE = 0
AFMT_INTERRUPT_ENABLE = 1
AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_MEM_PWR_DIS_CTRL'
AFMT_MEM_PWR_DIS_CTRL__enumvalues = {
0: 'AFMT_MEM_ENABLE_MEM_PWR_CTRL',
1: 'AFMT_MEM_DISABLE_MEM_PWR_CTRL',
}
AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0
AFMT_MEM_DISABLE_MEM_PWR_CTRL = 1
AFMT_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_MEM_PWR_FORCE_CTRL'
AFMT_MEM_PWR_FORCE_CTRL__enumvalues = {
0: 'AFMT_MEM_NO_FORCE_REQUEST',
1: 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST',
3: 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST',
}
AFMT_MEM_NO_FORCE_REQUEST = 0
AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1
AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 2
AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 3
AFMT_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN'
AFMT_RAMP_CONTROL0_SIGN__enumvalues = {
0: 'AFMT_RAMP_SIGNED',
1: 'AFMT_RAMP_UNSIGNED',
}
AFMT_RAMP_SIGNED = 0
AFMT_RAMP_UNSIGNED = 1
AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum
# values for enumeration 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE'
AFMT_VBI_PACKET_CONTROL_ACP_SOURCE__enumvalues = {
0: 'AFMT_ACP_SOURCE_FROM_AZALIA',
1: 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS',
}
AFMT_ACP_SOURCE_FROM_AZALIA = 0
AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 1
AFMT_VBI_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'AUDIO_LAYOUT_SELECT'
AUDIO_LAYOUT_SELECT__enumvalues = {
0: 'AUDIO_LAYOUT_0',
1: 'AUDIO_LAYOUT_1',
}
AUDIO_LAYOUT_0 = 0
AUDIO_LAYOUT_1 = 1
AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'HPO_TOP_CLOCK_GATING_DISABLE'
HPO_TOP_CLOCK_GATING_DISABLE__enumvalues = {
0: 'HPO_TOP_CLOCK_GATING_EN',
1: 'HPO_TOP_CLOCK_GATING_DIS',
}
HPO_TOP_CLOCK_GATING_EN = 0
HPO_TOP_CLOCK_GATING_DIS = 1
HPO_TOP_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum
# values for enumeration 'HPO_TOP_TEST_CLK_SEL'
HPO_TOP_TEST_CLK_SEL__enumvalues = {
0: 'HPO_TOP_PERMANENT_DISPCLK',
1: 'HPO_TOP_REGISTER_GATED_DISPCLK',
2: 'HPO_TOP_PERMANENT_SOCCLK',
3: 'HPO_TOP_TEST_CLOCK_RESERVED',
4: 'HPO_TOP_PERMANENT_HDMISTREAMCLK0',
5: 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0',
6: 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0',
7: 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0',
8: 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0',
9: 'HPO_TOP_PERMANENT_HDMICHARCLK0',
10: 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0',
11: 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0',
}
HPO_TOP_PERMANENT_DISPCLK = 0
HPO_TOP_REGISTER_GATED_DISPCLK = 1
HPO_TOP_PERMANENT_SOCCLK = 2
HPO_TOP_TEST_CLOCK_RESERVED = 3
HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 4
HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 5
HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 6
HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 7
HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 8
HPO_TOP_PERMANENT_HDMICHARCLK0 = 9
HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 10
HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 11
HPO_TOP_TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET'
DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET__enumvalues = {
0: 'DP_STREAM_MAPPER_LINK0',
1: 'DP_STREAM_MAPPER_LINK1',
2: 'DP_STREAM_MAPPER_RESERVED',
}
DP_STREAM_MAPPER_LINK0 = 0
DP_STREAM_MAPPER_LINK1 = 1
DP_STREAM_MAPPER_RESERVED = 2
DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_STREAM_ENC_DB_DISABLE_CONTROL'
HDMI_STREAM_ENC_DB_DISABLE_CONTROL__enumvalues = {
0: 'HDMI_STREAM_ENC_DB_ENABLE',
1: 'HDMI_STREAM_ENC_DB_DISABLE',
}
HDMI_STREAM_ENC_DB_ENABLE = 0
HDMI_STREAM_ENC_DB_DISABLE = 1
HDMI_STREAM_ENC_DB_DISABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_STREAM_ENC_DSC_MODE'
HDMI_STREAM_ENC_DSC_MODE__enumvalues = {
0: 'STREAM_DSC_DISABLE',
1: 'STREAM_DSC_444_RGB',
2: 'STREAM_DSC_NATIVE_422_420',
}
STREAM_DSC_DISABLE = 0
STREAM_DSC_444_RGB = 1
STREAM_DSC_NATIVE_422_420 = 2
HDMI_STREAM_ENC_DSC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_STREAM_ENC_ENABLE_CONTROL'
HDMI_STREAM_ENC_ENABLE_CONTROL__enumvalues = {
0: 'HDMI_STREAM_ENC_DISABLE',
1: 'HDMI_STREAM_ENC_ENABLE',
}
HDMI_STREAM_ENC_DISABLE = 0
HDMI_STREAM_ENC_ENABLE = 1
HDMI_STREAM_ENC_ENABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_STREAM_ENC_ODM_COMBINE_MODE'
HDMI_STREAM_ENC_ODM_COMBINE_MODE__enumvalues = {
0: 'STREAM_ODM_COMBINE_1_SEGMENT',
1: 'STREAM_ODM_COMBINE_2_SEGMENT',
2: 'STREAM_ODM_COMBINE_RESERVED',
3: 'STREAM_ODM_COMBINE_4_SEGMENT',
}
STREAM_ODM_COMBINE_1_SEGMENT = 0
STREAM_ODM_COMBINE_2_SEGMENT = 1
STREAM_ODM_COMBINE_RESERVED = 2
STREAM_ODM_COMBINE_4_SEGMENT = 3
HDMI_STREAM_ENC_ODM_COMBINE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR'
HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = {
0: 'HDMI_STREAM_ENC_NO_ERROR_OCCURRED',
1: 'HDMI_STREAM_ENC_UNDERFLOW_OCCURRED',
2: 'HDMI_STREAM_ENC_OVERFLOW_OCCURRED',
}
HDMI_STREAM_ENC_NO_ERROR_OCCURRED = 0
HDMI_STREAM_ENC_UNDERFLOW_OCCURRED = 1
HDMI_STREAM_ENC_OVERFLOW_OCCURRED = 2
HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT'
HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = {
0: 'HDMI_STREAM_ENC_HARDWARE',
1: 'HDMI_STREAM_ENC_PROGRAMMABLE',
}
HDMI_STREAM_ENC_HARDWARE = 0
HDMI_STREAM_ENC_PROGRAMMABLE = 1
HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_STREAM_ENC_PIXEL_ENCODING'
HDMI_STREAM_ENC_PIXEL_ENCODING__enumvalues = {
0: 'STREAM_PIXEL_ENCODING_444_RGB',
1: 'STREAM_PIXEL_ENCODING_422',
2: 'STREAM_PIXEL_ENCODING_420',
}
STREAM_PIXEL_ENCODING_444_RGB = 0
STREAM_PIXEL_ENCODING_422 = 1
STREAM_PIXEL_ENCODING_420 = 2
HDMI_STREAM_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_STREAM_ENC_READ_CLOCK_CONTROL'
HDMI_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = {
0: 'HDMI_STREAM_ENC_DCCG',
1: 'HDMI_STREAM_ENC_DISPLAY_PIPE',
}
HDMI_STREAM_ENC_DCCG = 0
HDMI_STREAM_ENC_DISPLAY_PIPE = 1
HDMI_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_STREAM_ENC_RESET_CONTROL'
HDMI_STREAM_ENC_RESET_CONTROL__enumvalues = {
0: 'HDMI_STREAM_ENC_NOT_RESET',
1: 'HDMI_STREAM_ENC_RESET',
}
HDMI_STREAM_ENC_NOT_RESET = 0
HDMI_STREAM_ENC_RESET = 1
HDMI_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_STREAM_ENC_STREAM_ACTIVE'
HDMI_STREAM_ENC_STREAM_ACTIVE__enumvalues = {
0: 'HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE',
1: 'HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE',
}
HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0
HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1
HDMI_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum
# values for enumeration 'BORROWBUFFER_MEM_POWER_STATE_ENUM'
BORROWBUFFER_MEM_POWER_STATE_ENUM__enumvalues = {
0: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_ON',
1: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_LS',
2: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_DS',
3: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_SD',
}
BORROWBUFFER_MEM_POWER_STATE_ENUM_ON = 0
BORROWBUFFER_MEM_POWER_STATE_ENUM_LS = 1
BORROWBUFFER_MEM_POWER_STATE_ENUM_DS = 2
BORROWBUFFER_MEM_POWER_STATE_ENUM_SD = 3
BORROWBUFFER_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_BORROW_MODE'
HDMI_BORROW_MODE__enumvalues = {
0: 'TB_BORROW_MODE_NONE',
1: 'TB_BORROW_MODE_ACTIVE',
2: 'TB_BORROW_MODE_BLANK',
3: 'TB_BORROW_MODE_RESERVED',
}
TB_BORROW_MODE_NONE = 0
TB_BORROW_MODE_ACTIVE = 1
TB_BORROW_MODE_BLANK = 2
TB_BORROW_MODE_RESERVED = 3
HDMI_BORROW_MODE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_ACP_SEND'
HDMI_TB_ENC_ACP_SEND__enumvalues = {
0: 'TB_ACP_NOT_SEND',
1: 'TB_ACP_PKT_SEND',
}
TB_ACP_NOT_SEND = 0
TB_ACP_PKT_SEND = 1
HDMI_TB_ENC_ACP_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_ACR_AUDIO_PRIORITY'
HDMI_TB_ENC_ACR_AUDIO_PRIORITY__enumvalues = {
0: 'TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE',
1: 'TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT',
}
TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0
TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1
HDMI_TB_ENC_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_ACR_CONT'
HDMI_TB_ENC_ACR_CONT__enumvalues = {
0: 'TB_ACR_CONT_DISABLE',
1: 'TB_ACR_CONT_ENABLE',
}
TB_ACR_CONT_DISABLE = 0
TB_ACR_CONT_ENABLE = 1
HDMI_TB_ENC_ACR_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_ACR_N_MULTIPLE'
HDMI_TB_ENC_ACR_N_MULTIPLE__enumvalues = {
0: 'TB_ACR_0_MULTIPLE_RESERVED',
1: 'TB_ACR_1_MULTIPLE',
2: 'TB_ACR_2_MULTIPLE',
3: 'TB_ACR_3_MULTIPLE_RESERVED',
4: 'TB_ACR_4_MULTIPLE',
5: 'TB_ACR_5_MULTIPLE_RESERVED',
6: 'TB_ACR_6_MULTIPLE_RESERVED',
7: 'TB_ACR_7_MULTIPLE_RESERVED',
}
TB_ACR_0_MULTIPLE_RESERVED = 0
TB_ACR_1_MULTIPLE = 1
TB_ACR_2_MULTIPLE = 2
TB_ACR_3_MULTIPLE_RESERVED = 3
TB_ACR_4_MULTIPLE = 4
TB_ACR_5_MULTIPLE_RESERVED = 5
TB_ACR_6_MULTIPLE_RESERVED = 6
TB_ACR_7_MULTIPLE_RESERVED = 7
HDMI_TB_ENC_ACR_N_MULTIPLE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_ACR_SELECT'
HDMI_TB_ENC_ACR_SELECT__enumvalues = {
0: 'TB_ACR_SELECT_HW',
1: 'TB_ACR_SELECT_32K',
2: 'TB_ACR_SELECT_44K',
3: 'TB_ACR_SELECT_48K',
}
TB_ACR_SELECT_HW = 0
TB_ACR_SELECT_32K = 1
TB_ACR_SELECT_44K = 2
TB_ACR_SELECT_48K = 3
HDMI_TB_ENC_ACR_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_ACR_SEND'
HDMI_TB_ENC_ACR_SEND__enumvalues = {
0: 'TB_ACR_NOT_SEND',
1: 'TB_ACR_PKT_SEND',
}
TB_ACR_NOT_SEND = 0
TB_ACR_PKT_SEND = 1
HDMI_TB_ENC_ACR_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_ACR_SOURCE'
HDMI_TB_ENC_ACR_SOURCE__enumvalues = {
0: 'TB_ACR_SOURCE_HW',
1: 'TB_ACR_SOURCE_SW',
}
TB_ACR_SOURCE_HW = 0
TB_ACR_SOURCE_SW = 1
HDMI_TB_ENC_ACR_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_AUDIO_INFO_CONT'
HDMI_TB_ENC_AUDIO_INFO_CONT__enumvalues = {
0: 'TB_AUDIO_INFO_CONT_DISABLE',
1: 'TB_AUDIO_INFO_CONT_ENABLE',
}
TB_AUDIO_INFO_CONT_DISABLE = 0
TB_AUDIO_INFO_CONT_ENABLE = 1
HDMI_TB_ENC_AUDIO_INFO_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_AUDIO_INFO_SEND'
HDMI_TB_ENC_AUDIO_INFO_SEND__enumvalues = {
0: 'TB_AUDIO_INFO_NOT_SEND',
1: 'TB_AUDIO_INFO_PKT_SEND',
}
TB_AUDIO_INFO_NOT_SEND = 0
TB_AUDIO_INFO_PKT_SEND = 1
HDMI_TB_ENC_AUDIO_INFO_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_CRC_SRC_SEL'
HDMI_TB_ENC_CRC_SRC_SEL__enumvalues = {
0: 'TB_CRC_TB_ENC_INPUT',
1: 'TB_CRC_DSC_PACKER',
2: 'TB_CRC_DEEP_COLOR_PACKER',
3: 'TB_CRC_ENCRYPTOR_INPUT',
}
TB_CRC_TB_ENC_INPUT = 0
TB_CRC_DSC_PACKER = 1
TB_CRC_DEEP_COLOR_PACKER = 2
TB_CRC_ENCRYPTOR_INPUT = 3
HDMI_TB_ENC_CRC_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_CRC_TYPE'
HDMI_TB_ENC_CRC_TYPE__enumvalues = {
0: 'TB_CRC_ALL_TRIBYTES',
1: 'TB_CRC_ACTIVE_TRIBYTES',
2: 'TB_CRC_DATAISLAND_TRIBYTES',
3: 'TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES',
}
TB_CRC_ALL_TRIBYTES = 0
TB_CRC_ACTIVE_TRIBYTES = 1
TB_CRC_DATAISLAND_TRIBYTES = 2
TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES = 3
HDMI_TB_ENC_CRC_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_DEEP_COLOR_DEPTH'
HDMI_TB_ENC_DEEP_COLOR_DEPTH__enumvalues = {
0: 'TB_DEEP_COLOR_DEPTH_24BPP',
1: 'TB_DEEP_COLOR_DEPTH_30BPP',
2: 'TB_DEEP_COLOR_DEPTH_36BPP',
3: 'TB_DEEP_COLOR_DEPTH_RESERVED',
}
TB_DEEP_COLOR_DEPTH_24BPP = 0
TB_DEEP_COLOR_DEPTH_30BPP = 1
TB_DEEP_COLOR_DEPTH_36BPP = 2
TB_DEEP_COLOR_DEPTH_RESERVED = 3
HDMI_TB_ENC_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_DEFAULT_PAHSE'
HDMI_TB_ENC_DEFAULT_PAHSE__enumvalues = {
0: 'TB_DEFAULT_PHASE_IS_0',
1: 'TB_DEFAULT_PHASE_IS_1',
}
TB_DEFAULT_PHASE_IS_0 = 0
TB_DEFAULT_PHASE_IS_1 = 1
HDMI_TB_ENC_DEFAULT_PAHSE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_DSC_MODE'
HDMI_TB_ENC_DSC_MODE__enumvalues = {
0: 'TB_DSC_DISABLE',
1: 'TB_DSC_444_RGB',
2: 'TB_DSC_NATIVE_422_420',
}
TB_DSC_DISABLE = 0
TB_DSC_444_RGB = 1
TB_DSC_NATIVE_422_420 = 2
HDMI_TB_ENC_DSC_MODE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_ENABLE'
HDMI_TB_ENC_ENABLE__enumvalues = {
0: 'TB_DISABLE',
1: 'TB_ENABLE',
}
TB_DISABLE = 0
TB_ENABLE = 1
HDMI_TB_ENC_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_GC_AVMUTE'
HDMI_TB_ENC_GC_AVMUTE__enumvalues = {
0: 'TB_GC_AVMUTE_SET',
1: 'TB_GC_AVMUTE_UNSET',
}
TB_GC_AVMUTE_SET = 0
TB_GC_AVMUTE_UNSET = 1
HDMI_TB_ENC_GC_AVMUTE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_GC_AVMUTE_CONT'
HDMI_TB_ENC_GC_AVMUTE_CONT__enumvalues = {
0: 'TB_GC_AVMUTE_CONT_DISABLE',
1: 'TB_GC_AVMUTE_CONT_ENABLE',
}
TB_GC_AVMUTE_CONT_DISABLE = 0
TB_GC_AVMUTE_CONT_ENABLE = 1
HDMI_TB_ENC_GC_AVMUTE_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_GC_CONT'
HDMI_TB_ENC_GC_CONT__enumvalues = {
0: 'TB_GC_CONT_DISABLE',
1: 'TB_GC_CONT_ENABLE',
}
TB_GC_CONT_DISABLE = 0
TB_GC_CONT_ENABLE = 1
HDMI_TB_ENC_GC_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_GC_SEND'
HDMI_TB_ENC_GC_SEND__enumvalues = {
0: 'TB_GC_NOT_SEND',
1: 'TB_GC_PKT_SEND',
}
TB_GC_NOT_SEND = 0
TB_GC_PKT_SEND = 1
HDMI_TB_ENC_GC_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_GENERIC_CONT'
HDMI_TB_ENC_GENERIC_CONT__enumvalues = {
0: 'TB_GENERIC_CONT_DISABLE',
1: 'TB_GENERIC_CONT_ENABLE',
}
TB_GENERIC_CONT_DISABLE = 0
TB_GENERIC_CONT_ENABLE = 1
HDMI_TB_ENC_GENERIC_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_GENERIC_LOCK_EN'
HDMI_TB_ENC_GENERIC_LOCK_EN__enumvalues = {
0: 'HDMI_TB_ENC_GENERIC_LOCK_DISABLE',
1: 'HDMI_TB_ENC_GENERIC_LOCK_ENABLE',
}
HDMI_TB_ENC_GENERIC_LOCK_DISABLE = 0
HDMI_TB_ENC_GENERIC_LOCK_ENABLE = 1
HDMI_TB_ENC_GENERIC_LOCK_EN = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_GENERIC_SEND'
HDMI_TB_ENC_GENERIC_SEND__enumvalues = {
0: 'TB_GENERIC_NOT_SEND',
1: 'TB_GENERIC_PKT_SEND',
}
TB_GENERIC_NOT_SEND = 0
TB_GENERIC_PKT_SEND = 1
HDMI_TB_ENC_GENERIC_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_ISRC_CONT'
HDMI_TB_ENC_ISRC_CONT__enumvalues = {
0: 'TB_ISRC_CONT_DISABLE',
1: 'TB_ISRC_CONT_ENABLE',
}
TB_ISRC_CONT_DISABLE = 0
TB_ISRC_CONT_ENABLE = 1
HDMI_TB_ENC_ISRC_CONT = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_ISRC_SEND'
HDMI_TB_ENC_ISRC_SEND__enumvalues = {
0: 'TB_ISRC_NOT_SEND',
1: 'TB_ISRC_PKT_SEND',
}
TB_ISRC_NOT_SEND = 0
TB_ISRC_PKT_SEND = 1
HDMI_TB_ENC_ISRC_SEND = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_METADATA_ENABLE'
HDMI_TB_ENC_METADATA_ENABLE__enumvalues = {
0: 'TB_METADATA_NOT_SEND',
1: 'TB_METADATA_PKT_SEND',
}
TB_METADATA_NOT_SEND = 0
TB_METADATA_PKT_SEND = 1
HDMI_TB_ENC_METADATA_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_PACKET_LINE_REFERENCE'
HDMI_TB_ENC_PACKET_LINE_REFERENCE__enumvalues = {
0: 'TB_PKT_LINE_REF_END_OF_ACTIVE',
1: 'TB_PKT_LINE_REF_OTGSOF',
}
TB_PKT_LINE_REF_END_OF_ACTIVE = 0
TB_PKT_LINE_REF_OTGSOF = 1
HDMI_TB_ENC_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_PIXEL_ENCODING'
HDMI_TB_ENC_PIXEL_ENCODING__enumvalues = {
0: 'TB_PIXEL_ENCODING_444_RGB',
1: 'TB_PIXEL_ENCODING_422',
2: 'TB_PIXEL_ENCODING_420',
}
TB_PIXEL_ENCODING_444_RGB = 0
TB_PIXEL_ENCODING_422 = 1
TB_PIXEL_ENCODING_420 = 2
HDMI_TB_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_RESET'
HDMI_TB_ENC_RESET__enumvalues = {
0: 'TB_NOT_RESET',
1: 'TB_RESET',
}
TB_NOT_RESET = 0
TB_RESET = 1
HDMI_TB_ENC_RESET = ctypes.c_uint32 # enum
# values for enumeration 'HDMI_TB_ENC_SYNC_PHASE'
HDMI_TB_ENC_SYNC_PHASE__enumvalues = {
0: 'TB_NOT_SYNC_PHASE_ON_FRAME_START',
1: 'TB_SYNC_PHASE_ON_FRAME_START',
}
TB_NOT_SYNC_PHASE_ON_FRAME_START = 0
TB_SYNC_PHASE_ON_FRAME_START = 1
HDMI_TB_ENC_SYNC_PHASE = ctypes.c_uint32 # enum
# values for enumeration 'INPUT_FIFO_ERROR_TYPE'
INPUT_FIFO_ERROR_TYPE__enumvalues = {
0: 'TB_NO_ERROR_OCCURRED',
1: 'TB_OVERFLOW_OCCURRED',
}
TB_NO_ERROR_OCCURRED = 0
TB_OVERFLOW_OCCURRED = 1
INPUT_FIFO_ERROR_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR'
DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = {
0: 'DP_STREAM_ENC_NO_ERROR_OCCURRED',
1: 'DP_STREAM_ENC_UNDERFLOW_OCCURRED',
2: 'DP_STREAM_ENC_OVERFLOW_OCCURRED',
}
DP_STREAM_ENC_NO_ERROR_OCCURRED = 0
DP_STREAM_ENC_UNDERFLOW_OCCURRED = 1
DP_STREAM_ENC_OVERFLOW_OCCURRED = 2
DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT'
DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = {
0: 'DP_STREAM_ENC_HARDWARE',
1: 'DP_STREAM_ENC_PROGRAMMABLE',
}
DP_STREAM_ENC_HARDWARE = 0
DP_STREAM_ENC_PROGRAMMABLE = 1
DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DP_STREAM_ENC_READ_CLOCK_CONTROL'
DP_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = {
0: 'DP_STREAM_ENC_DCCG',
1: 'DP_STREAM_ENC_DISPLAY_PIPE',
}
DP_STREAM_ENC_DCCG = 0
DP_STREAM_ENC_DISPLAY_PIPE = 1
DP_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'DP_STREAM_ENC_RESET_CONTROL'
DP_STREAM_ENC_RESET_CONTROL__enumvalues = {
0: 'DP_STREAM_ENC_NOT_RESET',
1: 'DP_STREAM_ENC_RESET',
}
DP_STREAM_ENC_NOT_RESET = 0
DP_STREAM_ENC_RESET = 1
DP_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'DP_STREAM_ENC_STREAM_ACTIVE'
DP_STREAM_ENC_STREAM_ACTIVE__enumvalues = {
0: 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE',
1: 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE',
}
DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0
DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1
DP_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_AUDIO_MUTE'
ENUM_DP_SYM32_ENC_AUDIO_MUTE__enumvalues = {
0: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED',
1: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED',
}
DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0
DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 1
ENUM_DP_SYM32_ENC_AUDIO_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE'
ENUM_DP_SYM32_ENC_CONTINUOUS_MODE__enumvalues = {
0: 'DP_SYM32_ENC_ONE_SHOT_MODE',
1: 'DP_SYM32_ENC_CONTINUOUS_MODE',
}
DP_SYM32_ENC_ONE_SHOT_MODE = 0
DP_SYM32_ENC_CONTINUOUS_MODE = 1
ENUM_DP_SYM32_ENC_CONTINUOUS_MODE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_CRC_VALID'
ENUM_DP_SYM32_ENC_CRC_VALID__enumvalues = {
0: 'DP_SYM32_ENC_CRC_NOT_VALID',
1: 'DP_SYM32_ENC_CRC_VALID',
}
DP_SYM32_ENC_CRC_NOT_VALID = 0
DP_SYM32_ENC_CRC_VALID = 1
ENUM_DP_SYM32_ENC_CRC_VALID = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH'
ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH__enumvalues = {
0: 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC',
1: 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC',
2: 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC',
3: 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC',
}
DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0
DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 1
DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 2
DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 3
ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_ENABLE'
ENUM_DP_SYM32_ENC_ENABLE__enumvalues = {
0: 'DP_SYM32_ENC_DISABLE',
1: 'DP_SYM32_ENC_ENABLE',
}
DP_SYM32_ENC_DISABLE = 0
DP_SYM32_ENC_ENABLE = 1
ENUM_DP_SYM32_ENC_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED'
ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED__enumvalues = {
0: 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED',
1: 'DP_SYM32_ENC_GSP_DEADLINE_MISSED',
}
DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0
DP_SYM32_ENC_GSP_DEADLINE_MISSED = 1
ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION'
ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION__enumvalues = {
0: 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER',
1: 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME',
}
DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0
DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 1
ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE'
ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE__enumvalues = {
0: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32',
1: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0',
2: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1',
3: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128',
}
DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0
DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 1
DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 2
DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 3
ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING'
ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING__enumvalues = {
0: 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING',
1: 'DP_SYM32_ENC_GSP_TRIGGER_PENDING',
}
DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0
DP_SYM32_ENC_GSP_TRIGGER_PENDING = 1
ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM'
ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM__enumvalues = {
0: 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST',
1: 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST',
2: 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST',
3: 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST',
}
DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0
DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 1
DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 2
DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 3
ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS'
ENUM_DP_SYM32_ENC_OVERFLOW_STATUS__enumvalues = {
0: 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED',
1: 'DP_SYM32_ENC_OVERFLOW_OCCURRED',
}
DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0
DP_SYM32_ENC_OVERFLOW_OCCURRED = 1
ENUM_DP_SYM32_ENC_OVERFLOW_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_PENDING'
ENUM_DP_SYM32_ENC_PENDING__enumvalues = {
0: 'DP_SYM32_ENC_NOT_PENDING',
1: 'DP_SYM32_ENC_PENDING',
}
DP_SYM32_ENC_NOT_PENDING = 0
DP_SYM32_ENC_PENDING = 1
ENUM_DP_SYM32_ENC_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING'
ENUM_DP_SYM32_ENC_PIXEL_ENCODING__enumvalues = {
0: 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444',
1: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422',
2: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420',
3: 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY',
}
DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0
DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 1
DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 2
DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 3
ENUM_DP_SYM32_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE'
ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE__enumvalues = {
0: 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT',
1: 'DP_SYM32_ENC_COMPRESSED_FORMAT',
}
DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0
DP_SYM32_ENC_COMPRESSED_FORMAT = 1
ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM'
ENUM_DP_SYM32_ENC_POWER_STATE_ENUM__enumvalues = {
0: 'DP_SYM32_ENC_POWER_STATE_ENUM_ON',
1: 'DP_SYM32_ENC_POWER_STATE_ENUM_LS',
2: 'DP_SYM32_ENC_POWER_STATE_ENUM_DS',
3: 'DP_SYM32_ENC_POWER_STATE_ENUM_SD',
}
DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0
DP_SYM32_ENC_POWER_STATE_ENUM_LS = 1
DP_SYM32_ENC_POWER_STATE_ENUM_DS = 2
DP_SYM32_ENC_POWER_STATE_ENUM_SD = 3
ENUM_DP_SYM32_ENC_POWER_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_RESET'
ENUM_DP_SYM32_ENC_RESET__enumvalues = {
0: 'DP_SYM32_ENC_NOT_RESET',
1: 'DP_SYM32_ENC_RESET',
}
DP_SYM32_ENC_NOT_RESET = 0
DP_SYM32_ENC_RESET = 1
ENUM_DP_SYM32_ENC_RESET = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_SDP_PRIORITY'
ENUM_DP_SYM32_ENC_SDP_PRIORITY__enumvalues = {
0: 'DP_SYM32_ENC_SDP_LOW_PRIORITY',
1: 'DP_SYM32_ENC_SDP_HIGH_PRIORITY',
}
DP_SYM32_ENC_SDP_LOW_PRIORITY = 0
DP_SYM32_ENC_SDP_HIGH_PRIORITY = 1
ENUM_DP_SYM32_ENC_SDP_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_SOF_REFERENCE'
ENUM_DP_SYM32_ENC_SOF_REFERENCE__enumvalues = {
0: 'DP_SYM32_ENC_DP_SOF',
1: 'DP_SYM32_ENC_OTG_SOF',
}
DP_SYM32_ENC_DP_SOF = 0
DP_SYM32_ENC_OTG_SOF = 1
ENUM_DP_SYM32_ENC_SOF_REFERENCE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER'
ENUM_DP_SYM32_ENC_VID_STREAM_DEFER__enumvalues = {
0: 'DP_SYM32_ENC_VID_STREAM_NO_DEFER',
1: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK',
2: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK',
}
DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0
DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 1
DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 2
ENUM_DP_SYM32_ENC_VID_STREAM_DEFER = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT'
ENUM_DP_DPHY_SYM32_CRC_END_EVENT__enumvalues = {
0: 'DP_DPHY_SYM32_CRC_END_LLCP',
1: 'DP_DPHY_SYM32_CRC_END_PS_ONLY',
2: 'DP_DPHY_SYM32_CRC_END_PS_LT_SR',
3: 'DP_DPHY_SYM32_CRC_END_PS_ANY',
}
DP_DPHY_SYM32_CRC_END_LLCP = 0
DP_DPHY_SYM32_CRC_END_PS_ONLY = 1
DP_DPHY_SYM32_CRC_END_PS_LT_SR = 2
DP_DPHY_SYM32_CRC_END_PS_ANY = 3
ENUM_DP_DPHY_SYM32_CRC_END_EVENT = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT'
ENUM_DP_DPHY_SYM32_CRC_START_EVENT__enumvalues = {
0: 'DP_DPHY_SYM32_CRC_START_LLCP',
1: 'DP_DPHY_SYM32_CRC_START_PS_ONLY',
2: 'DP_DPHY_SYM32_CRC_START_PS_LT_SR',
3: 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR',
4: 'DP_DPHY_SYM32_CRC_START_TP_START',
}
DP_DPHY_SYM32_CRC_START_LLCP = 0
DP_DPHY_SYM32_CRC_START_PS_ONLY = 1
DP_DPHY_SYM32_CRC_START_PS_LT_SR = 2
DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 3
DP_DPHY_SYM32_CRC_START_TP_START = 4
ENUM_DP_DPHY_SYM32_CRC_START_EVENT = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE'
ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE__enumvalues = {
0: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER',
1: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER',
2: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX',
}
DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0
DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 1
DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 2
ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS'
ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS__enumvalues = {
0: 'DP_DPHY_SYM32_CRC_USE_END_EVENT',
1: 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS',
}
DP_DPHY_SYM32_CRC_USE_END_EVENT = 0
DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 1
ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_ENABLE'
ENUM_DP_DPHY_SYM32_ENABLE__enumvalues = {
0: 'DP_DPHY_SYM32_DISABLE',
1: 'DP_DPHY_SYM32_ENABLE',
}
DP_DPHY_SYM32_DISABLE = 0
DP_DPHY_SYM32_ENABLE = 1
ENUM_DP_DPHY_SYM32_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE'
ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE__enumvalues = {
0: 'DP_DPHY_SYM32_ENCRYPT_TYPE0',
1: 'DP_DPHY_SYM32_ENCRYPT_TYPE1',
}
DP_DPHY_SYM32_ENCRYPT_TYPE0 = 0
DP_DPHY_SYM32_ENCRYPT_TYPE1 = 1
ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_MODE'
ENUM_DP_DPHY_SYM32_MODE__enumvalues = {
0: 'DP_DPHY_SYM32_LT_TPS1',
1: 'DP_DPHY_SYM32_LT_TPS2',
2: 'DP_DPHY_SYM32_ACTIVE',
3: 'DP_DPHY_SYM32_TEST',
}
DP_DPHY_SYM32_LT_TPS1 = 0
DP_DPHY_SYM32_LT_TPS2 = 1
DP_DPHY_SYM32_ACTIVE = 2
DP_DPHY_SYM32_TEST = 3
ENUM_DP_DPHY_SYM32_MODE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_NUM_LANES'
ENUM_DP_DPHY_SYM32_NUM_LANES__enumvalues = {
0: 'DP_DPHY_SYM32_1LANE',
1: 'DP_DPHY_SYM32_2LANE',
2: 'DP_DPHY_SYM32_RESERVED',
3: 'DP_DPHY_SYM32_4LANE',
}
DP_DPHY_SYM32_1LANE = 0
DP_DPHY_SYM32_2LANE = 1
DP_DPHY_SYM32_RESERVED = 2
DP_DPHY_SYM32_4LANE = 3
ENUM_DP_DPHY_SYM32_NUM_LANES = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING'
ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING__enumvalues = {
0: 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING',
1: 'DP_DPHY_SYM32_RATE_UPDATE_PENDING',
}
DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0
DP_DPHY_SYM32_RATE_UPDATE_PENDING = 1
ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET'
ENUM_DP_DPHY_SYM32_RESET__enumvalues = {
0: 'DP_DPHY_SYM32_NOT_RESET',
1: 'DP_DPHY_SYM32_RESET',
}
DP_DPHY_SYM32_NOT_RESET = 0
DP_DPHY_SYM32_RESET = 1
ENUM_DP_DPHY_SYM32_RESET = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET_STATUS'
ENUM_DP_DPHY_SYM32_RESET_STATUS__enumvalues = {
0: 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED',
1: 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED',
}
DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0
DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 1
ENUM_DP_DPHY_SYM32_RESET_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE'
ENUM_DP_DPHY_SYM32_SAT_UPDATE__enumvalues = {
0: 'DP_DPHY_SYM32_SAT_NO_UPDATE',
1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE',
2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE',
}
DP_DPHY_SYM32_SAT_NO_UPDATE = 0
DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 1
DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 2
ENUM_DP_DPHY_SYM32_SAT_UPDATE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING'
ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING__enumvalues = {
0: 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING',
1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING',
2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING',
}
DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0
DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 1
DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 2
ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_STATUS'
ENUM_DP_DPHY_SYM32_STATUS__enumvalues = {
0: 'DP_DPHY_SYM32_STATUS_IDLE',
1: 'DP_DPHY_SYM32_STATUS_ENABLED',
}
DP_DPHY_SYM32_STATUS_IDLE = 0
DP_DPHY_SYM32_STATUS_ENABLED = 1
ENUM_DP_DPHY_SYM32_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE'
ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE__enumvalues = {
0: 'DP_DPHY_SYM32_STREAM_OVR_NONE',
1: 'DP_DPHY_SYM32_STREAM_OVR_REPLACE',
2: 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS',
}
DP_DPHY_SYM32_STREAM_OVR_NONE = 0
DP_DPHY_SYM32_STREAM_OVR_REPLACE = 1
DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 2
ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE'
ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE__enumvalues = {
0: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA',
1: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL',
}
DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0
DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 1
ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL'
ENUM_DP_DPHY_SYM32_TP_PRBS_SEL__enumvalues = {
0: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7',
1: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9',
2: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11',
3: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15',
4: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23',
5: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31',
}
DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0
DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 1
DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 2
DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 3
DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 4
DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 5
ENUM_DP_DPHY_SYM32_TP_PRBS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_SELECT'
ENUM_DP_DPHY_SYM32_TP_SELECT__enumvalues = {
0: 'DP_DPHY_SYM32_TP_SELECT_TPS1',
1: 'DP_DPHY_SYM32_TP_SELECT_TPS2',
2: 'DP_DPHY_SYM32_TP_SELECT_PRBS',
3: 'DP_DPHY_SYM32_TP_SELECT_CUSTOM',
4: 'DP_DPHY_SYM32_TP_SELECT_SQUARE',
}
DP_DPHY_SYM32_TP_SELECT_TPS1 = 0
DP_DPHY_SYM32_TP_SELECT_TPS2 = 1
DP_DPHY_SYM32_TP_SELECT_PRBS = 2
DP_DPHY_SYM32_TP_SELECT_CUSTOM = 3
DP_DPHY_SYM32_TP_SELECT_SQUARE = 4
ENUM_DP_DPHY_SYM32_TP_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'APG_AUDIO_CRC_CONTROL_CH_SEL'
APG_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = {
0: 'APG_AUDIO_CRC_CH0_SIG',
1: 'APG_AUDIO_CRC_CH1_SIG',
2: 'APG_AUDIO_CRC_CH2_SIG',
3: 'APG_AUDIO_CRC_CH3_SIG',
4: 'APG_AUDIO_CRC_CH4_SIG',
5: 'APG_AUDIO_CRC_CH5_SIG',
6: 'APG_AUDIO_CRC_CH6_SIG',
7: 'APG_AUDIO_CRC_CH7_SIG',
8: 'APG_AUDIO_CRC_RESERVED_8',
9: 'APG_AUDIO_CRC_RESERVED_9',
10: 'APG_AUDIO_CRC_RESERVED_10',
11: 'APG_AUDIO_CRC_RESERVED_11',
12: 'APG_AUDIO_CRC_RESERVED_12',
13: 'APG_AUDIO_CRC_RESERVED_13',
14: 'APG_AUDIO_CRC_RESERVED_14',
15: 'APG_AUDIO_CRC_RESERVED_15',
}
APG_AUDIO_CRC_CH0_SIG = 0
APG_AUDIO_CRC_CH1_SIG = 1
APG_AUDIO_CRC_CH2_SIG = 2
APG_AUDIO_CRC_CH3_SIG = 3
APG_AUDIO_CRC_CH4_SIG = 4
APG_AUDIO_CRC_CH5_SIG = 5
APG_AUDIO_CRC_CH6_SIG = 6
APG_AUDIO_CRC_CH7_SIG = 7
APG_AUDIO_CRC_RESERVED_8 = 8
APG_AUDIO_CRC_RESERVED_9 = 9
APG_AUDIO_CRC_RESERVED_10 = 10
APG_AUDIO_CRC_RESERVED_11 = 11
APG_AUDIO_CRC_RESERVED_12 = 12
APG_AUDIO_CRC_RESERVED_13 = 13
APG_AUDIO_CRC_RESERVED_14 = 14
APG_AUDIO_CRC_RESERVED_15 = 15
APG_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum
# values for enumeration 'APG_AUDIO_CRC_CONTROL_CONT'
APG_AUDIO_CRC_CONTROL_CONT__enumvalues = {
0: 'APG_AUDIO_CRC_ONESHOT',
1: 'APG_AUDIO_CRC_CONTINUOUS',
}
APG_AUDIO_CRC_ONESHOT = 0
APG_AUDIO_CRC_CONTINUOUS = 1
APG_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum
# values for enumeration 'APG_DBG_ACP_TYPE'
APG_DBG_ACP_TYPE__enumvalues = {
0: 'APG_ACP_TYPE_GENERIC_AUDIO',
1: 'APG_ACP_TYPE_ICE60958_AUDIO',
2: 'APG_ACP_TYPE_DVD_AUDIO',
3: 'APG_ACP_TYPE_SUPER_AUDIO_CD',
}
APG_ACP_TYPE_GENERIC_AUDIO = 0
APG_ACP_TYPE_ICE60958_AUDIO = 1
APG_ACP_TYPE_DVD_AUDIO = 2
APG_ACP_TYPE_SUPER_AUDIO_CD = 3
APG_DBG_ACP_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'APG_DBG_AUDIO_DTO_BASE'
APG_DBG_AUDIO_DTO_BASE__enumvalues = {
0: 'BASE_RATE_48KHZ',
1: 'BASE_RATE_44P1KHZ',
}
BASE_RATE_48KHZ = 0
BASE_RATE_44P1KHZ = 1
APG_DBG_AUDIO_DTO_BASE = ctypes.c_uint32 # enum
# values for enumeration 'APG_DBG_AUDIO_DTO_DIV'
APG_DBG_AUDIO_DTO_DIV__enumvalues = {
0: 'DIVISOR_BY1',
1: 'DIVISOR_BY2_RESERVED',
2: 'DIVISOR_BY3',
3: 'DIVISOR_BY4_RESERVED',
4: 'DIVISOR_BY5_RESERVED',
5: 'DIVISOR_BY6_RESERVED',
6: 'DIVISOR_BY7_RESERVED',
7: 'DIVISOR_BY8_RESERVED',
}
DIVISOR_BY1 = 0
DIVISOR_BY2_RESERVED = 1
DIVISOR_BY3 = 2
DIVISOR_BY4_RESERVED = 3
DIVISOR_BY5_RESERVED = 4
DIVISOR_BY6_RESERVED = 5
DIVISOR_BY7_RESERVED = 6
DIVISOR_BY8_RESERVED = 7
APG_DBG_AUDIO_DTO_DIV = ctypes.c_uint32 # enum
# values for enumeration 'APG_DBG_AUDIO_DTO_MULTI'
APG_DBG_AUDIO_DTO_MULTI__enumvalues = {
0: 'MULTIPLE_BY1',
1: 'MULTIPLE_BY2',
2: 'MULTIPLE_BY3_RESERVED',
3: 'MULTIPLE_BY4',
4: 'MULTIPLE_RESERVED',
}
MULTIPLE_BY1 = 0
MULTIPLE_BY2 = 1
MULTIPLE_BY3_RESERVED = 2
MULTIPLE_BY4 = 3
MULTIPLE_RESERVED = 4
APG_DBG_AUDIO_DTO_MULTI = ctypes.c_uint32 # enum
# values for enumeration 'APG_DBG_MUX_SEL'
APG_DBG_MUX_SEL__enumvalues = {
0: 'APG_FUNCTIONAL_MODE',
1: 'APG_DEBUG_AUDIO_MODE',
}
APG_FUNCTIONAL_MODE = 0
APG_DEBUG_AUDIO_MODE = 1
APG_DBG_MUX_SEL = ctypes.c_uint32 # enum
# values for enumeration 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE'
APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = {
0: 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ',
1: 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED',
}
APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0
APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1
APG_DP_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'APG_MEM_POWER_STATE'
APG_MEM_POWER_STATE__enumvalues = {
0: 'APG_MEM_POWER_STATE_ON',
1: 'APG_MEM_POWER_STATE_LS',
2: 'APG_MEM_POWER_STATE_DS',
3: 'APG_MEM_POWER_STATE_SD',
}
APG_MEM_POWER_STATE_ON = 0
APG_MEM_POWER_STATE_LS = 1
APG_MEM_POWER_STATE_DS = 2
APG_MEM_POWER_STATE_SD = 3
APG_MEM_POWER_STATE = ctypes.c_uint32 # enum
# values for enumeration 'APG_MEM_PWR_DIS_CTRL'
APG_MEM_PWR_DIS_CTRL__enumvalues = {
0: 'APG_MEM_ENABLE_MEM_PWR_CTRL',
1: 'APG_MEM_DISABLE_MEM_PWR_CTRL',
}
APG_MEM_ENABLE_MEM_PWR_CTRL = 0
APG_MEM_DISABLE_MEM_PWR_CTRL = 1
APG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'APG_MEM_PWR_FORCE_CTRL'
APG_MEM_PWR_FORCE_CTRL__enumvalues = {
0: 'APG_MEM_NO_FORCE_REQUEST',
1: 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST',
3: 'APG_MEM_FORCE_SHUT_DOWN_REQUEST',
}
APG_MEM_NO_FORCE_REQUEST = 0
APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1
APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 2
APG_MEM_FORCE_SHUT_DOWN_REQUEST = 3
APG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'APG_PACKET_CONTROL_ACP_SOURCE'
APG_PACKET_CONTROL_ACP_SOURCE__enumvalues = {
0: 'APG_ACP_SOURCE_NO_OVERRIDE',
1: 'APG_ACP_OVERRIDE',
}
APG_ACP_SOURCE_NO_OVERRIDE = 0
APG_ACP_OVERRIDE = 1
APG_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE'
APG_PACKET_CONTROL_AUDIO_INFO_SOURCE__enumvalues = {
0: 'APG_INFOFRAME_SOURCE_NO_OVERRIDE',
1: 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS',
}
APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0
APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 1
APG_PACKET_CONTROL_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'APG_RAMP_CONTROL_SIGN'
APG_RAMP_CONTROL_SIGN__enumvalues = {
0: 'APG_RAMP_SIGNED',
1: 'APG_RAMP_UNSIGNED',
}
APG_RAMP_SIGNED = 0
APG_RAMP_UNSIGNED = 1
APG_RAMP_CONTROL_SIGN = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL'
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = {
0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1',
1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2',
2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3',
3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4',
4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5',
5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6',
}
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL'
DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = {
0: 'DCIO_TEST_CLK_SEL_DISPCLK',
1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK',
2: 'DCIO_TEST_CLK_SEL_SOCCLK',
}
DCIO_TEST_CLK_SEL_DISPCLK = 0
DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1
DCIO_TEST_CLK_SEL_SOCCLK = 2
DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS'
DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = {
0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE',
1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE',
}
DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0
DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1
DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DBG_ASYNC_4BIT_SEL'
DCIO_DBG_ASYNC_4BIT_SEL__enumvalues = {
0: 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0',
1: 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4',
2: 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8',
3: 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12',
4: 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16',
5: 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20',
6: 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24',
7: 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28',
}
DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0
DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 1
DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 2
DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 3
DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 4
DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 5
DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 6
DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 7
DCIO_DBG_ASYNC_4BIT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DBG_ASYNC_BLOCK_SEL'
DCIO_DBG_ASYNC_BLOCK_SEL__enumvalues = {
0: 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE',
1: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG',
2: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO',
3: 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO',
}
DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0
DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 1
DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 2
DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 3
DCIO_DBG_ASYNC_BLOCK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET'
DCIO_DCRXPHY_SOFT_RESET__enumvalues = {
0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT',
1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT',
}
DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0
DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1
DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERICA_SEL'
DCIO_DC_GENERICA_SEL__enumvalues = {
1: 'DCIO_GENERICA_SEL_STEREOSYNC',
10: 'DCIO_GENERICA_SEL_GENERICA_DCCG',
11: 'DCIO_GENERICA_SEL_SYNCEN',
}
DCIO_GENERICA_SEL_STEREOSYNC = 1
DCIO_GENERICA_SEL_GENERICA_DCCG = 10
DCIO_GENERICA_SEL_SYNCEN = 11
DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERICB_SEL'
DCIO_DC_GENERICB_SEL__enumvalues = {
1: 'DCIO_GENERICB_SEL_STEREOSYNC',
10: 'DCIO_GENERICB_SEL_GENERICB_DCCG',
11: 'DCIO_GENERICB_SEL_SYNCEN',
}
DCIO_GENERICB_SEL_STEREOSYNC = 1
DCIO_GENERICB_SEL_GENERICB_DCCG = 10
DCIO_GENERICB_SEL_SYNCEN = 11
DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL'
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = {
0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2',
1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2',
2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2',
3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2',
4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2',
5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2',
6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2',
}
DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0
DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1
DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2
DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3
DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4
DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5
DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL'
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = {
0: 'DCIO_UNIPHYA_FBDIV_CLK',
1: 'DCIO_UNIPHYB_FBDIV_CLK',
2: 'DCIO_UNIPHYC_FBDIV_CLK',
3: 'DCIO_UNIPHYD_FBDIV_CLK',
4: 'DCIO_UNIPHYE_FBDIV_CLK',
5: 'DCIO_UNIPHYF_FBDIV_CLK',
6: 'DCIO_UNIPHYG_FBDIV_CLK',
}
DCIO_UNIPHYA_FBDIV_CLK = 0
DCIO_UNIPHYB_FBDIV_CLK = 1
DCIO_UNIPHYC_FBDIV_CLK = 2
DCIO_UNIPHYD_FBDIV_CLK = 3
DCIO_UNIPHYE_FBDIV_CLK = 4
DCIO_UNIPHYF_FBDIV_CLK = 5
DCIO_UNIPHYG_FBDIV_CLK = 6
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL'
DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = {
0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK',
1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK',
2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK',
3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK',
4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK',
5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK',
6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK',
}
DCIO_UNIPHYA_FBDIV_SSC_CLK = 0
DCIO_UNIPHYB_FBDIV_SSC_CLK = 1
DCIO_UNIPHYC_FBDIV_SSC_CLK = 2
DCIO_UNIPHYD_FBDIV_SSC_CLK = 3
DCIO_UNIPHYE_FBDIV_SSC_CLK = 4
DCIO_UNIPHYF_FBDIV_SSC_CLK = 5
DCIO_UNIPHYG_FBDIV_SSC_CLK = 6
DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL'
DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = {
0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK',
1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK',
2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK',
3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK',
4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK',
5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK',
6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK',
}
DCIO_UNIPHYA_TEST_REFDIV_CLK = 0
DCIO_UNIPHYB_TEST_REFDIV_CLK = 1
DCIO_UNIPHYC_TEST_REFDIV_CLK = 2
DCIO_UNIPHYD_TEST_REFDIV_CLK = 3
DCIO_UNIPHYE_TEST_REFDIV_CLK = 4
DCIO_UNIPHYF_TEST_REFDIV_CLK = 5
DCIO_UNIPHYG_TEST_REFDIV_CLK = 6
DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE'
DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE__enumvalues = {
0: 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL',
1: 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP',
}
DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0
DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 1
DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT'
DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = {
0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE',
1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE',
2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP',
3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP',
4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM',
5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM',
}
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 2
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 3
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 4
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 5
DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION'
DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = {
0: 'DCIO_GPU_TIMER_START_0_END_27',
1: 'DCIO_GPU_TIMER_START_1_END_28',
2: 'DCIO_GPU_TIMER_START_2_END_29',
3: 'DCIO_GPU_TIMER_START_3_END_30',
4: 'DCIO_GPU_TIMER_START_4_END_31',
5: 'DCIO_GPU_TIMER_START_6_END_33',
6: 'DCIO_GPU_TIMER_START_8_END_35',
7: 'DCIO_GPU_TIMER_START_10_END_37',
}
DCIO_GPU_TIMER_START_0_END_27 = 0
DCIO_GPU_TIMER_START_1_END_28 = 1
DCIO_GPU_TIMER_START_2_END_29 = 2
DCIO_GPU_TIMER_START_3_END_30 = 3
DCIO_GPU_TIMER_START_4_END_31 = 4
DCIO_GPU_TIMER_START_6_END_33 = 5
DCIO_GPU_TIMER_START_8_END_35 = 6
DCIO_GPU_TIMER_START_10_END_37 = 7
DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL'
DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = {
0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE',
1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1',
2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2',
3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3',
}
DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2
DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3
DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL'
DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL__enumvalues = {
0: 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE',
1: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1',
2: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2',
3: 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED',
}
DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0
DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 1
DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 2
DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 3
DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DIO_EXT_VSYNC_MASK'
DCIO_DIO_EXT_VSYNC_MASK__enumvalues = {
0: 'DCIO_EXT_VSYNC_MASK_NONE',
1: 'DCIO_EXT_VSYNC_MASK_PIPE0',
2: 'DCIO_EXT_VSYNC_MASK_PIPE1',
3: 'DCIO_EXT_VSYNC_MASK_PIPE2',
4: 'DCIO_EXT_VSYNC_MASK_PIPE3',
5: 'DCIO_EXT_VSYNC_MASK_PIPE4',
6: 'DCIO_EXT_VSYNC_MASK_PIPE5',
7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE',
}
DCIO_EXT_VSYNC_MASK_NONE = 0
DCIO_EXT_VSYNC_MASK_PIPE0 = 1
DCIO_EXT_VSYNC_MASK_PIPE1 = 2
DCIO_EXT_VSYNC_MASK_PIPE2 = 3
DCIO_EXT_VSYNC_MASK_PIPE3 = 4
DCIO_EXT_VSYNC_MASK_PIPE4 = 5
DCIO_EXT_VSYNC_MASK_PIPE5 = 6
DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7
DCIO_DIO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DIO_OTG_EXT_VSYNC_MUX'
DCIO_DIO_OTG_EXT_VSYNC_MUX__enumvalues = {
0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB',
1: 'DCIO_EXT_VSYNC_MUX_OTG0',
2: 'DCIO_EXT_VSYNC_MUX_OTG1',
3: 'DCIO_EXT_VSYNC_MUX_OTG2',
4: 'DCIO_EXT_VSYNC_MUX_OTG3',
5: 'DCIO_EXT_VSYNC_MUX_OTG4',
6: 'DCIO_EXT_VSYNC_MUX_OTG5',
7: 'DCIO_EXT_VSYNC_MUX_GENERICB',
}
DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0
DCIO_EXT_VSYNC_MUX_OTG0 = 1
DCIO_EXT_VSYNC_MUX_OTG1 = 2
DCIO_EXT_VSYNC_MUX_OTG2 = 3
DCIO_EXT_VSYNC_MUX_OTG3 = 4
DCIO_EXT_VSYNC_MUX_OTG4 = 5
DCIO_EXT_VSYNC_MUX_OTG5 = 6
DCIO_EXT_VSYNC_MUX_GENERICB = 7
DCIO_DIO_OTG_EXT_VSYNC_MUX = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK'
DCIO_DPCS_INTERRUPT_MASK__enumvalues = {
0: 'DCIO_DPCS_INTERRUPT_DISABLE',
1: 'DCIO_DPCS_INTERRUPT_ENABLE',
}
DCIO_DPCS_INTERRUPT_DISABLE = 0
DCIO_DPCS_INTERRUPT_ENABLE = 1
DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE'
DCIO_DPCS_INTERRUPT_TYPE__enumvalues = {
0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED',
1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED',
}
DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0
DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1
DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_DSYNC_SOFT_RESET'
DCIO_DSYNC_SOFT_RESET__enumvalues = {
0: 'DCIO_DSYNC_SOFT_RESET_DEASSERT',
1: 'DCIO_DSYNC_SOFT_RESET_ASSERT',
}
DCIO_DSYNC_SOFT_RESET_DEASSERT = 0
DCIO_DSYNC_SOFT_RESET_ASSERT = 1
DCIO_DSYNC_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK'
DCIO_GENLK_CLK_GSL_MASK__enumvalues = {
0: 'DCIO_GENLK_CLK_GSL_MASK_NO',
1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING',
2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO',
}
DCIO_GENLK_CLK_GSL_MASK_NO = 0
DCIO_GENLK_CLK_GSL_MASK_TIMING = 1
DCIO_GENLK_CLK_GSL_MASK_STEREO = 2
DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK'
DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = {
0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO',
1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING',
2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO',
}
DCIO_GENLK_VSYNC_GSL_MASK_NO = 0
DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1
DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2
DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_GSL_SEL'
DCIO_GSL_SEL__enumvalues = {
0: 'DCIO_GSL_SEL_GROUP_0',
1: 'DCIO_GSL_SEL_GROUP_1',
2: 'DCIO_GSL_SEL_GROUP_2',
}
DCIO_GSL_SEL_GROUP_0 = 0
DCIO_GSL_SEL_GROUP_1 = 1
DCIO_GSL_SEL_GROUP_2 = 2
DCIO_GSL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_PHY_HPO_ENC_SRC_SEL'
DCIO_PHY_HPO_ENC_SRC_SEL__enumvalues = {
0: 'HPO_SRC0',
1: 'HPO_SRC_RESERVED',
}
HPO_SRC0 = 0
HPO_SRC_RESERVED = 1
DCIO_PHY_HPO_ENC_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK'
DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = {
0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO',
1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING',
2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO',
}
DCIO_SWAPLOCK_A_GSL_MASK_NO = 0
DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1
DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2
DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK'
DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = {
0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO',
1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING',
2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO',
}
DCIO_SWAPLOCK_B_GSL_MASK_NO = 0
DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1
DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2
DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE'
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = {
0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0',
1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1',
2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2',
3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3',
}
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL'
DCIO_UNIPHY_IMPCAL_SEL__enumvalues = {
0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE',
1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY',
}
DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0
DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1
DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT'
DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = {
0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION',
1: 'DCIO_UNIPHY_CHANNEL_INVERTED',
}
DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0
DCIO_UNIPHY_CHANNEL_INVERTED = 1
DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK'
DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = {
0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW',
1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW',
2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED',
3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED',
}
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3
DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_ALL_PWR_OK'
DCIOCHIP_AUX_ALL_PWR_OK__enumvalues = {
0: 'DCIOCHIP_AUX_ALL_PWR_OK_0',
1: 'DCIOCHIP_AUX_ALL_PWR_OK_1',
}
DCIOCHIP_AUX_ALL_PWR_OK_0 = 0
DCIOCHIP_AUX_ALL_PWR_OK_1 = 1
DCIOCHIP_AUX_ALL_PWR_OK = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_CSEL0P9'
DCIOCHIP_AUX_CSEL0P9__enumvalues = {
0: 'DCIOCHIP_AUX_CSEL_DEC1P0',
1: 'DCIOCHIP_AUX_CSEL_DEC0P9',
}
DCIOCHIP_AUX_CSEL_DEC1P0 = 0
DCIOCHIP_AUX_CSEL_DEC0P9 = 1
DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_CSEL1P1'
DCIOCHIP_AUX_CSEL1P1__enumvalues = {
0: 'DCIOCHIP_AUX_CSEL_INC1P0',
1: 'DCIOCHIP_AUX_CSEL_INC1P1',
}
DCIOCHIP_AUX_CSEL_INC1P0 = 0
DCIOCHIP_AUX_CSEL_INC1P1 = 1
DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL'
DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = {
0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW',
1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0',
2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1',
3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH',
}
DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0
DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1
DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2
DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3
DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_HYS_TUNE'
DCIOCHIP_AUX_HYS_TUNE__enumvalues = {
0: 'DCIOCHIP_AUX_HYS_TUNE_0',
1: 'DCIOCHIP_AUX_HYS_TUNE_1',
2: 'DCIOCHIP_AUX_HYS_TUNE_2',
3: 'DCIOCHIP_AUX_HYS_TUNE_3',
}
DCIOCHIP_AUX_HYS_TUNE_0 = 0
DCIOCHIP_AUX_HYS_TUNE_1 = 1
DCIOCHIP_AUX_HYS_TUNE_2 = 2
DCIOCHIP_AUX_HYS_TUNE_3 = 3
DCIOCHIP_AUX_HYS_TUNE = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_RECEIVER_SEL'
DCIOCHIP_AUX_RECEIVER_SEL__enumvalues = {
0: 'DCIOCHIP_AUX_RECEIVER_SEL_0',
1: 'DCIOCHIP_AUX_RECEIVER_SEL_1',
2: 'DCIOCHIP_AUX_RECEIVER_SEL_2',
3: 'DCIOCHIP_AUX_RECEIVER_SEL_3',
}
DCIOCHIP_AUX_RECEIVER_SEL_0 = 0
DCIOCHIP_AUX_RECEIVER_SEL_1 = 1
DCIOCHIP_AUX_RECEIVER_SEL_2 = 2
DCIOCHIP_AUX_RECEIVER_SEL_3 = 3
DCIOCHIP_AUX_RECEIVER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_RSEL0P9'
DCIOCHIP_AUX_RSEL0P9__enumvalues = {
0: 'DCIOCHIP_AUX_RSEL_DEC1P0',
1: 'DCIOCHIP_AUX_RSEL_DEC0P9',
}
DCIOCHIP_AUX_RSEL_DEC1P0 = 0
DCIOCHIP_AUX_RSEL_DEC0P9 = 1
DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_RSEL1P1'
DCIOCHIP_AUX_RSEL1P1__enumvalues = {
0: 'DCIOCHIP_AUX_RSEL_INC1P0',
1: 'DCIOCHIP_AUX_RSEL_INC1P1',
}
DCIOCHIP_AUX_RSEL_INC1P0 = 0
DCIOCHIP_AUX_RSEL_INC1P1 = 1
DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_SPIKESEL'
DCIOCHIP_AUX_SPIKESEL__enumvalues = {
0: 'DCIOCHIP_AUX_SPIKESEL_50NS',
1: 'DCIOCHIP_AUX_SPIKESEL_10NS',
}
DCIOCHIP_AUX_SPIKESEL_50NS = 0
DCIOCHIP_AUX_SPIKESEL_10NS = 1
DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_AUX_VOD_TUNE'
DCIOCHIP_AUX_VOD_TUNE__enumvalues = {
0: 'DCIOCHIP_AUX_VOD_TUNE_0',
1: 'DCIOCHIP_AUX_VOD_TUNE_1',
2: 'DCIOCHIP_AUX_VOD_TUNE_2',
3: 'DCIOCHIP_AUX_VOD_TUNE_3',
}
DCIOCHIP_AUX_VOD_TUNE_0 = 0
DCIOCHIP_AUX_VOD_TUNE_1 = 1
DCIOCHIP_AUX_VOD_TUNE_2 = 2
DCIOCHIP_AUX_VOD_TUNE_3 = 3
DCIOCHIP_AUX_VOD_TUNE = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_GPIO_MASK_EN'
DCIOCHIP_GPIO_MASK_EN__enumvalues = {
0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE',
1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE',
}
DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0
DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1
DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_HPD_SEL'
DCIOCHIP_HPD_SEL__enumvalues = {
0: 'DCIOCHIP_HPD_SEL_ASYNC',
1: 'DCIOCHIP_HPD_SEL_CLOCKED',
}
DCIOCHIP_HPD_SEL_ASYNC = 0
DCIOCHIP_HPD_SEL_CLOCKED = 1
DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_I2C_COMPSEL'
DCIOCHIP_I2C_COMPSEL__enumvalues = {
0: 'DCIOCHIP_I2C_REC_SCHMIT',
1: 'DCIOCHIP_I2C_REC_COMPARATOR',
}
DCIOCHIP_I2C_REC_SCHMIT = 0
DCIOCHIP_I2C_REC_COMPARATOR = 1
DCIOCHIP_I2C_COMPSEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_I2C_FALLSLEWSEL'
DCIOCHIP_I2C_FALLSLEWSEL__enumvalues = {
0: 'DCIOCHIP_I2C_FALLSLEWSEL_00',
1: 'DCIOCHIP_I2C_FALLSLEWSEL_01',
2: 'DCIOCHIP_I2C_FALLSLEWSEL_10',
3: 'DCIOCHIP_I2C_FALLSLEWSEL_11',
}
DCIOCHIP_I2C_FALLSLEWSEL_00 = 0
DCIOCHIP_I2C_FALLSLEWSEL_01 = 1
DCIOCHIP_I2C_FALLSLEWSEL_10 = 2
DCIOCHIP_I2C_FALLSLEWSEL_11 = 3
DCIOCHIP_I2C_FALLSLEWSEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_I2C_RECEIVER_SEL'
DCIOCHIP_I2C_RECEIVER_SEL__enumvalues = {
0: 'DCIOCHIP_I2C_RECEIVER_SEL_0',
1: 'DCIOCHIP_I2C_RECEIVER_SEL_1',
2: 'DCIOCHIP_I2C_RECEIVER_SEL_2',
3: 'DCIOCHIP_I2C_RECEIVER_SEL_3',
}
DCIOCHIP_I2C_RECEIVER_SEL_0 = 0
DCIOCHIP_I2C_RECEIVER_SEL_1 = 1
DCIOCHIP_I2C_RECEIVER_SEL_2 = 2
DCIOCHIP_I2C_RECEIVER_SEL_3 = 3
DCIOCHIP_I2C_RECEIVER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_I2C_VPH_1V2_EN'
DCIOCHIP_I2C_VPH_1V2_EN__enumvalues = {
0: 'DCIOCHIP_I2C_VPH_1V2_EN_0',
1: 'DCIOCHIP_I2C_VPH_1V2_EN_1',
}
DCIOCHIP_I2C_VPH_1V2_EN_0 = 0
DCIOCHIP_I2C_VPH_1V2_EN_1 = 1
DCIOCHIP_I2C_VPH_1V2_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_INVERT'
DCIOCHIP_INVERT__enumvalues = {
0: 'DCIOCHIP_POL_NON_INVERT',
1: 'DCIOCHIP_POL_INVERT',
}
DCIOCHIP_POL_NON_INVERT = 0
DCIOCHIP_POL_INVERT = 1
DCIOCHIP_INVERT = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_MASK'
DCIOCHIP_MASK__enumvalues = {
0: 'DCIOCHIP_MASK_DISABLE',
1: 'DCIOCHIP_MASK_ENABLE',
}
DCIOCHIP_MASK_DISABLE = 0
DCIOCHIP_MASK_ENABLE = 1
DCIOCHIP_MASK = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_PAD_MODE'
DCIOCHIP_PAD_MODE__enumvalues = {
0: 'DCIOCHIP_PAD_MODE_DDC',
1: 'DCIOCHIP_PAD_MODE_DP',
}
DCIOCHIP_PAD_MODE_DDC = 0
DCIOCHIP_PAD_MODE_DP = 1
DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_PD_EN'
DCIOCHIP_PD_EN__enumvalues = {
0: 'DCIOCHIP_PD_EN_NOTALLOW',
1: 'DCIOCHIP_PD_EN_ALLOW',
}
DCIOCHIP_PD_EN_NOTALLOW = 0
DCIOCHIP_PD_EN_ALLOW = 1
DCIOCHIP_PD_EN = ctypes.c_uint32 # enum
# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL'
DCIOCHIP_REF_27_SRC_SEL__enumvalues = {
0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER',
1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER',
2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS',
3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS',
}
DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1
DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3
DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE'
PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = {
0: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE',
1: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE',
}
PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0
PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1
PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN'
PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__enumvalues = {
0: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL',
1: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM',
}
PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0
PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 1
PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT'
PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT__enumvalues = {
0: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL',
1: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1',
2: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2',
3: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3',
}
PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0
PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 1
PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 2
PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 3
PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN'
PWRSEQ_BL_PWM_CNTL_BL_PWM_EN__enumvalues = {
0: 'PWRSEQ_BL_PWM_DISABLE',
1: 'PWRSEQ_BL_PWM_ENABLE',
}
PWRSEQ_BL_PWM_DISABLE = 0
PWRSEQ_BL_PWM_ENABLE = 1
PWRSEQ_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN'
PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = {
0: 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE',
1: 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE',
}
PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0
PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 1
PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN'
PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = {
0: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE',
1: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE',
}
PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0
PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1
PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN'
PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = {
0: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM',
1: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM',
}
PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0
PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1
PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_GRP1_REG_LOCK'
PWRSEQ_BL_PWM_GRP1_REG_LOCK__enumvalues = {
0: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE',
1: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE',
}
PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0
PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 1
PWRSEQ_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START'
PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = {
0: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE',
1: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE',
}
PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0
PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1
PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_GPIO_MASK_EN'
PWRSEQ_GPIO_MASK_EN__enumvalues = {
0: 'PWRSEQ_GPIO_MASK_EN_HARDWARE',
1: 'PWRSEQ_GPIO_MASK_EN_SOFTWARE',
}
PWRSEQ_GPIO_MASK_EN_HARDWARE = 0
PWRSEQ_GPIO_MASK_EN_SOFTWARE = 1
PWRSEQ_GPIO_MASK_EN = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON'
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON__enumvalues = {
0: 'PWRSEQ_PANEL_BLON_OFF',
1: 'PWRSEQ_PANEL_BLON_ON',
}
PWRSEQ_PANEL_BLON_OFF = 0
PWRSEQ_PANEL_BLON_ON = 1
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL'
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL__enumvalues = {
0: 'PWRSEQ_PANEL_BLON_POL_NON_INVERT',
1: 'PWRSEQ_PANEL_BLON_POL_INVERT',
}
PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0
PWRSEQ_PANEL_BLON_POL_INVERT = 1
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON'
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON__enumvalues = {
0: 'PWRSEQ_PANEL_DIGON_OFF',
1: 'PWRSEQ_PANEL_DIGON_ON',
}
PWRSEQ_PANEL_DIGON_OFF = 0
PWRSEQ_PANEL_DIGON_ON = 1
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL'
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL__enumvalues = {
0: 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT',
1: 'PWRSEQ_PANEL_DIGON_POL_INVERT',
}
PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0
PWRSEQ_PANEL_DIGON_POL_INVERT = 1
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL'
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL__enumvalues = {
0: 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT',
1: 'PWRSEQ_PANEL_SYNCEN_POL_INVERT',
}
PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0
PWRSEQ_PANEL_SYNCEN_POL_INVERT = 1
PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE'
PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE__enumvalues = {
0: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF',
1: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON',
}
PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0
PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 1
PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum
# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN'
PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN__enumvalues = {
0: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON',
1: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE',
}
PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0
PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 1
PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum
# values for enumeration 'AZ_CORB_SIZE'
AZ_CORB_SIZE__enumvalues = {
0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED',
1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED',
2: 'AZ_CORB_SIZE_256ENTRIES',
3: 'AZ_CORB_SIZE_RESERVED',
}
AZ_CORB_SIZE_2ENTRIES_RESERVED = 0
AZ_CORB_SIZE_16ENTRIES_RESERVED = 1
AZ_CORB_SIZE_256ENTRIES = 2
AZ_CORB_SIZE_RESERVED = 3
AZ_CORB_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'AZ_GLOBAL_CAPABILITIES'
AZ_GLOBAL_CAPABILITIES__enumvalues = {
0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED',
1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED',
}
AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0
AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1
AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum
# values for enumeration 'AZ_RIRB_SIZE'
AZ_RIRB_SIZE__enumvalues = {
0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED',
1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED',
2: 'AZ_RIRB_SIZE_256ENTRIES',
3: 'AZ_RIRB_SIZE_UNDEFINED',
}
AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0
AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1
AZ_RIRB_SIZE_256ENTRIES = 2
AZ_RIRB_SIZE_UNDEFINED = 3
AZ_RIRB_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET'
AZ_RIRB_WRITE_POINTER_RESET__enumvalues = {
0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET',
1: 'AZ_RIRB_WRITE_POINTER_DO_RESET',
}
AZ_RIRB_WRITE_POINTER_NOT_RESET = 0
AZ_RIRB_WRITE_POINTER_DO_RESET = 1
AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum
# values for enumeration 'AZ_STATE_CHANGE_STATUS'
AZ_STATE_CHANGE_STATUS__enumvalues = {
0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT',
1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT',
}
AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0
AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1
AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'CORB_READ_POINTER_RESET'
CORB_READ_POINTER_RESET__enumvalues = {
0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET',
1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET',
}
CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0
CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1
CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum
# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE'
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = {
0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE',
1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE',
}
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1
DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL'
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = {
0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE',
1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE',
}
GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED'
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = {
0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED',
1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED',
}
GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1
GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS'
GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = {
0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET',
1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET',
}
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1
GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED'
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = {
0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED',
1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED',
}
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1
GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum
# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE'
GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = {
0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE',
1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE',
}
ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0
ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1
GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum
# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET'
GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = {
0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET',
1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET',
}
CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0
CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1
GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum
# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL'
GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = {
0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED',
1: 'FLUSH_CONTROL_FLUSH_STARTED',
}
FLUSH_CONTROL_FLUSH_NOT_STARTED = 0
FLUSH_CONTROL_FLUSH_STARTED = 1
GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS'
GLOBAL_STATUS_FLUSH_STATUS__enumvalues = {
0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED',
1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED',
}
GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0
GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1
GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY'
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = {
0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY',
1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY',
}
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum
# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID'
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = {
0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID',
1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID',
}
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1
IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum
# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL'
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = {
0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED',
1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED',
}
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1
RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL'
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = {
0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED',
1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED',
}
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1
RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_0_SYNCHRONIZATION'
STREAM_0_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_10_SYNCHRONIZATION'
STREAM_10_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_11_SYNCHRONIZATION'
STREAM_11_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_12_SYNCHRONIZATION'
STREAM_12_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_13_SYNCHRONIZATION'
STREAM_13_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_14_SYNCHRONIZATION'
STREAM_14_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_15_SYNCHRONIZATION'
STREAM_15_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_1_SYNCHRONIZATION'
STREAM_1_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_2_SYNCHRONIZATION'
STREAM_2_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_3_SYNCHRONIZATION'
STREAM_3_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED',
1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED',
}
STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0
STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1
STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_4_SYNCHRONIZATION'
STREAM_4_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_5_SYNCHRONIZATION'
STREAM_5_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_6_SYNCHRONIZATION'
STREAM_6_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_7_SYNCHRONIZATION'
STREAM_7_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_8_SYNCHRONIZATION'
STREAM_8_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'STREAM_9_SYNCHRONIZATION'
STREAM_9_SYNCHRONIZATION__enumvalues = {
0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
}
STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0
STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1
STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16',
2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20',
3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24',
4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2',
2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3',
3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4',
4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5',
5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6',
6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7',
7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8',
8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG'
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = {
0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON',
1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON',
}
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1
AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE'
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1',
2: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2',
3: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3',
4: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4',
5: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5',
6: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6',
7: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7',
8: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8',
9: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9',
10: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10',
11: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11',
12: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12',
13: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13',
14: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14',
15: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15',
}
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 1
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 2
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 3
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 4
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 5
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 6
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 7
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 8
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 9
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 10
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 11
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 12
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 13
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 14
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 15
AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT'
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN',
}
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1
AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE'
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE',
}
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1
AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE'
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED',
}
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1
AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE'
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = {
0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF',
1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN',
}
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1
AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET'
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = {
0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET',
1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC',
}
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1
AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_DIS_CTRL'
MEM_PWR_DIS_CTRL__enumvalues = {
0: 'ENABLE_MEM_PWR_CTRL',
1: 'DISABLE_MEM_PWR_CTRL',
}
ENABLE_MEM_PWR_CTRL = 0
DISABLE_MEM_PWR_CTRL = 1
MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_FORCE_CTRL'
MEM_PWR_FORCE_CTRL__enumvalues = {
0: 'NO_FORCE_REQUEST',
1: 'FORCE_LIGHT_SLEEP_REQUEST',
2: 'FORCE_DEEP_SLEEP_REQUEST',
3: 'FORCE_SHUT_DOWN_REQUEST',
}
NO_FORCE_REQUEST = 0
FORCE_LIGHT_SLEEP_REQUEST = 1
FORCE_DEEP_SLEEP_REQUEST = 2
FORCE_SHUT_DOWN_REQUEST = 3
MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_FORCE_CTRL2'
MEM_PWR_FORCE_CTRL2__enumvalues = {
0: 'NO_FORCE_REQ',
1: 'FORCE_LIGHT_SLEEP_REQ',
}
NO_FORCE_REQ = 0
FORCE_LIGHT_SLEEP_REQ = 1
MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_SEL_CTRL'
MEM_PWR_SEL_CTRL__enumvalues = {
0: 'DYNAMIC_SHUT_DOWN_ENABLE',
1: 'DYNAMIC_DEEP_SLEEP_ENABLE',
2: 'DYNAMIC_LIGHT_SLEEP_ENABLE',
}
DYNAMIC_SHUT_DOWN_ENABLE = 0
DYNAMIC_DEEP_SLEEP_ENABLE = 1
DYNAMIC_LIGHT_SLEEP_ENABLE = 2
MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'MEM_PWR_SEL_CTRL2'
MEM_PWR_SEL_CTRL2__enumvalues = {
0: 'DYNAMIC_DEEP_SLEEP_EN',
1: 'DYNAMIC_LIGHT_SLEEP_EN',
}
DYNAMIC_DEEP_SLEEP_EN = 0
DYNAMIC_LIGHT_SLEEP_EN = 1
MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum
# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY'
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = {
0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL',
1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6',
2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5',
3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4',
4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3',
5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2',
6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1',
7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0',
}
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7
CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum
# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY'
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = {
0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL',
1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6',
2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5',
3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4',
4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3',
5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2',
6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1',
7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0',
}
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7
CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16',
2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20',
3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24',
4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2',
2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3',
3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4',
4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5',
5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6',
6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7',
7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8',
8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN'
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED',
1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED',
}
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1
AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE'
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = {
0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF',
1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN',
}
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1
AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET'
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = {
0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET',
1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET',
}
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1
AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum
# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL'
AZ_LATENCY_COUNTER_CONTROL__enumvalues = {
0: 'AZ_LATENCY_COUNTER_NO_RESET',
1: 'AZ_LATENCY_COUNTER_RESET_DONE',
}
AZ_LATENCY_COUNTER_NO_RESET = 0
AZ_LATENCY_COUNTER_RESET_DONE = 1
AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY'
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY',
1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY',
}
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16',
2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20',
3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24',
4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2',
2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3',
3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4',
4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5',
5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6',
6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7',
7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8',
8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED',
9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED',
10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED',
11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED',
12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED',
13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED',
14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED',
15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum
# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE'
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = {
0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ',
1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
}
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED',
9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY'
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
}
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1
AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE'
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE',
1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE',
}
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1
AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE'
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY',
1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY',
}
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED',
9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY'
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED'
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = {
0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
}
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1
AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED',
9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY'
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED',
9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum
# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED'
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = {
0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
}
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1
AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_BITS_PER_COMPONENT_ENUM'
DSCC_BITS_PER_COMPONENT_ENUM__enumvalues = {
8: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT',
10: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT',
12: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT',
}
DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8
DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10
DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12
DSCC_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_DSC_VERSION_MAJOR_ENUM'
DSCC_DSC_VERSION_MAJOR_ENUM__enumvalues = {
1: 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION',
}
DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 1
DSCC_DSC_VERSION_MAJOR_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_DSC_VERSION_MINOR_ENUM'
DSCC_DSC_VERSION_MINOR_ENUM__enumvalues = {
1: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION',
2: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION',
}
DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 1
DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 2
DSCC_DSC_VERSION_MINOR_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_ENABLE_ENUM'
DSCC_ENABLE_ENUM__enumvalues = {
0: 'DSCC_ENABLE_ENUM_DISABLED',
1: 'DSCC_ENABLE_ENUM_ENABLED',
}
DSCC_ENABLE_ENUM_DISABLED = 0
DSCC_ENABLE_ENUM_ENABLED = 1
DSCC_ENABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_ICH_RESET_ENUM'
DSCC_ICH_RESET_ENUM__enumvalues = {
1: 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET',
2: 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET',
4: 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET',
8: 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET',
}
DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 1
DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 2
DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 4
DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 8
DSCC_ICH_RESET_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_LINEBUF_DEPTH_ENUM'
DSCC_LINEBUF_DEPTH_ENUM__enumvalues = {
8: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT',
9: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT',
10: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT',
11: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT',
12: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT',
13: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT',
}
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 8
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 9
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 10
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 11
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 12
DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 13
DSCC_LINEBUF_DEPTH_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_MEM_PWR_DIS_ENUM'
DSCC_MEM_PWR_DIS_ENUM__enumvalues = {
0: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN',
1: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS',
}
DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0
DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 1
DSCC_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCC_MEM_PWR_FORCE_ENUM'
DSCC_MEM_PWR_FORCE_ENUM__enumvalues = {
0: 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST',
1: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST',
2: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST',
3: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST',
}
DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0
DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 1
DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 2
DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 3
DSCC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'POWER_STATE_ENUM'
POWER_STATE_ENUM__enumvalues = {
0: 'POWER_STATE_ENUM_ON',
1: 'POWER_STATE_ENUM_LS',
2: 'POWER_STATE_ENUM_DS',
3: 'POWER_STATE_ENUM_SD',
}
POWER_STATE_ENUM_ON = 0
POWER_STATE_ENUM_LS = 1
POWER_STATE_ENUM_DS = 2
POWER_STATE_ENUM_SD = 3
POWER_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCCIF_BITS_PER_COMPONENT_ENUM'
DSCCIF_BITS_PER_COMPONENT_ENUM__enumvalues = {
8: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT',
10: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT',
12: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT',
}
DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8
DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10
DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12
DSCCIF_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCCIF_ENABLE_ENUM'
DSCCIF_ENABLE_ENUM__enumvalues = {
0: 'DSCCIF_ENABLE_ENUM_DISABLED',
1: 'DSCCIF_ENABLE_ENUM_ENABLED',
}
DSCCIF_ENABLE_ENUM_DISABLED = 0
DSCCIF_ENABLE_ENUM_ENABLED = 1
DSCCIF_ENABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM'
DSCCIF_INPUT_PIXEL_FORMAT_ENUM__enumvalues = {
0: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB',
1: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444',
2: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422',
3: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422',
4: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420',
}
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 1
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 2
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 3
DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 4
DSCCIF_INPUT_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'CLOCK_GATING_DISABLE_ENUM'
CLOCK_GATING_DISABLE_ENUM__enumvalues = {
0: 'CLOCK_GATING_DISABLE_ENUM_ENABLED',
1: 'CLOCK_GATING_DISABLE_ENUM_DISABLED',
}
CLOCK_GATING_DISABLE_ENUM_ENABLED = 0
CLOCK_GATING_DISABLE_ENUM_DISABLED = 1
CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'ENABLE_ENUM'
ENABLE_ENUM__enumvalues = {
0: 'ENABLE_ENUM_DISABLED',
1: 'ENABLE_ENUM_ENABLED',
}
ENABLE_ENUM_DISABLED = 0
ENABLE_ENUM_ENABLED = 1
ENABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'TEST_CLOCK_MUX_SELECT_ENUM'
TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = {
0: 'TEST_CLOCK_MUX_SELECT_DISPCLK_P',
1: 'TEST_CLOCK_MUX_SELECT_DISPCLK_G',
2: 'TEST_CLOCK_MUX_SELECT_DISPCLK_R',
3: 'TEST_CLOCK_MUX_SELECT_DSCCLK_P',
4: 'TEST_CLOCK_MUX_SELECT_DSCCLK_G',
5: 'TEST_CLOCK_MUX_SELECT_DSCCLK_R',
}
TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0
TEST_CLOCK_MUX_SELECT_DISPCLK_G = 1
TEST_CLOCK_MUX_SELECT_DISPCLK_R = 2
TEST_CLOCK_MUX_SELECT_DSCCLK_P = 3
TEST_CLOCK_MUX_SELECT_DSCCLK_G = 4
TEST_CLOCK_MUX_SELECT_DSCCLK_R = 5
TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_CRC_CONT_EN_ENUM'
DWB_CRC_CONT_EN_ENUM__enumvalues = {
0: 'DWB_CRC_CONT_EN_ONE_SHOT',
1: 'DWB_CRC_CONT_EN_CONT',
}
DWB_CRC_CONT_EN_ONE_SHOT = 0
DWB_CRC_CONT_EN_CONT = 1
DWB_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_CRC_SRC_SEL_ENUM'
DWB_CRC_SRC_SEL_ENUM__enumvalues = {
0: 'DWB_CRC_SRC_SEL_DWB_IN',
1: 'DWB_CRC_SRC_SEL_OGAM_OUT',
2: 'DWB_CRC_SRC_SEL_DWB_OUT',
}
DWB_CRC_SRC_SEL_DWB_IN = 0
DWB_CRC_SRC_SEL_OGAM_OUT = 1
DWB_CRC_SRC_SEL_DWB_OUT = 2
DWB_CRC_SRC_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM'
DWB_DATA_OVERFLOW_INT_TYPE_ENUM__enumvalues = {
0: 'DWB_DATA_OVERFLOW_INT_TYPE_0',
1: 'DWB_DATA_OVERFLOW_INT_TYPE_1',
}
DWB_DATA_OVERFLOW_INT_TYPE_0 = 0
DWB_DATA_OVERFLOW_INT_TYPE_1 = 1
DWB_DATA_OVERFLOW_INT_TYPE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_DATA_OVERFLOW_TYPE_ENUM'
DWB_DATA_OVERFLOW_TYPE_ENUM__enumvalues = {
0: 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW',
1: 'DWB_DATA_OVERFLOW_TYPE_BUFFER',
2: 'DWB_DATA_OVERFLOW_TYPE_VUPDATE',
3: 'DWB_DATA_OVERFLOW_TYPE_VREADY',
}
DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0
DWB_DATA_OVERFLOW_TYPE_BUFFER = 1
DWB_DATA_OVERFLOW_TYPE_VUPDATE = 2
DWB_DATA_OVERFLOW_TYPE_VREADY = 3
DWB_DATA_OVERFLOW_TYPE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_DEBUG_SEL_ENUM'
DWB_DEBUG_SEL_ENUM__enumvalues = {
0: 'DWB_DEBUG_SEL_FC',
1: 'DWB_DEBUG_SEL_RESERVED',
2: 'DWB_DEBUG_SEL_DWBCP',
3: 'DWB_DEBUG_SEL_PERFMON',
}
DWB_DEBUG_SEL_FC = 0
DWB_DEBUG_SEL_RESERVED = 1
DWB_DEBUG_SEL_DWBCP = 2
DWB_DEBUG_SEL_PERFMON = 3
DWB_DEBUG_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_MEM_PWR_FORCE_ENUM'
DWB_MEM_PWR_FORCE_ENUM__enumvalues = {
0: 'DWB_MEM_PWR_FORCE_DIS',
1: 'DWB_MEM_PWR_FORCE_LS',
2: 'DWB_MEM_PWR_FORCE_DS',
3: 'DWB_MEM_PWR_FORCE_SD',
}
DWB_MEM_PWR_FORCE_DIS = 0
DWB_MEM_PWR_FORCE_LS = 1
DWB_MEM_PWR_FORCE_DS = 2
DWB_MEM_PWR_FORCE_SD = 3
DWB_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_MEM_PWR_STATE_ENUM'
DWB_MEM_PWR_STATE_ENUM__enumvalues = {
0: 'DWB_MEM_PWR_STATE_ON',
1: 'DWB_MEM_PWR_STATE_LS',
2: 'DWB_MEM_PWR_STATE_DS',
3: 'DWB_MEM_PWR_STATE_SD',
}
DWB_MEM_PWR_STATE_ON = 0
DWB_MEM_PWR_STATE_LS = 1
DWB_MEM_PWR_STATE_DS = 2
DWB_MEM_PWR_STATE_SD = 3
DWB_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_TEST_CLK_SEL_ENUM'
DWB_TEST_CLK_SEL_ENUM__enumvalues = {
0: 'DWB_TEST_CLK_SEL_R',
1: 'DWB_TEST_CLK_SEL_G',
2: 'DWB_TEST_CLK_SEL_P',
}
DWB_TEST_CLK_SEL_R = 0
DWB_TEST_CLK_SEL_G = 1
DWB_TEST_CLK_SEL_P = 2
DWB_TEST_CLK_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'FC_EYE_SELECTION_ENUM'
FC_EYE_SELECTION_ENUM__enumvalues = {
0: 'FC_EYE_SELECTION_STEREO_DIS',
1: 'FC_EYE_SELECTION_LEFT_EYE',
2: 'FC_EYE_SELECTION_RIGHT_EYE',
}
FC_EYE_SELECTION_STEREO_DIS = 0
FC_EYE_SELECTION_LEFT_EYE = 1
FC_EYE_SELECTION_RIGHT_EYE = 2
FC_EYE_SELECTION_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'FC_FRAME_CAPTURE_RATE_ENUM'
FC_FRAME_CAPTURE_RATE_ENUM__enumvalues = {
0: 'FC_FRAME_CAPTURE_RATE_FULL',
1: 'FC_FRAME_CAPTURE_RATE_HALF',
2: 'FC_FRAME_CAPTURE_RATE_THIRD',
3: 'FC_FRAME_CAPTURE_RATE_QUARTER',
}
FC_FRAME_CAPTURE_RATE_FULL = 0
FC_FRAME_CAPTURE_RATE_HALF = 1
FC_FRAME_CAPTURE_RATE_THIRD = 2
FC_FRAME_CAPTURE_RATE_QUARTER = 3
FC_FRAME_CAPTURE_RATE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'FC_STEREO_EYE_POLARITY_ENUM'
FC_STEREO_EYE_POLARITY_ENUM__enumvalues = {
0: 'FC_STEREO_EYE_POLARITY_LEFT',
1: 'FC_STEREO_EYE_POLARITY_RIGHT',
}
FC_STEREO_EYE_POLARITY_LEFT = 0
FC_STEREO_EYE_POLARITY_RIGHT = 1
FC_STEREO_EYE_POLARITY_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM'
DWB_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = {
0: 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13',
1: 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12',
}
DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0
DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1
DWB_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_GAMUT_REMAP_MODE_ENUM'
DWB_GAMUT_REMAP_MODE_ENUM__enumvalues = {
0: 'DWB_GAMUT_REMAP_MODE_BYPASS',
1: 'DWB_GAMUT_REMAP_MODE_COEF_A',
2: 'DWB_GAMUT_REMAP_MODE_COEF_B',
3: 'DWB_GAMUT_REMAP_MODE_RESERVED',
}
DWB_GAMUT_REMAP_MODE_BYPASS = 0
DWB_GAMUT_REMAP_MODE_COEF_A = 1
DWB_GAMUT_REMAP_MODE_COEF_B = 2
DWB_GAMUT_REMAP_MODE_RESERVED = 3
DWB_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_LUT_NUM_SEG'
DWB_LUT_NUM_SEG__enumvalues = {
0: 'DWB_SEGMENTS_1',
1: 'DWB_SEGMENTS_2',
2: 'DWB_SEGMENTS_4',
3: 'DWB_SEGMENTS_8',
4: 'DWB_SEGMENTS_16',
5: 'DWB_SEGMENTS_32',
6: 'DWB_SEGMENTS_64',
7: 'DWB_SEGMENTS_128',
}
DWB_SEGMENTS_1 = 0
DWB_SEGMENTS_2 = 1
DWB_SEGMENTS_4 = 2
DWB_SEGMENTS_8 = 3
DWB_SEGMENTS_16 = 4
DWB_SEGMENTS_32 = 5
DWB_SEGMENTS_64 = 6
DWB_SEGMENTS_128 = 7
DWB_LUT_NUM_SEG = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_LUT_CONFIG_MODE_ENUM'
DWB_OGAM_LUT_CONFIG_MODE_ENUM__enumvalues = {
0: 'DWB_OGAM_LUT_CONFIG_MODE_DIFF',
1: 'DWB_OGAM_LUT_CONFIG_MODE_SAME',
}
DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0
DWB_OGAM_LUT_CONFIG_MODE_SAME = 1
DWB_OGAM_LUT_CONFIG_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_LUT_HOST_SEL_ENUM'
DWB_OGAM_LUT_HOST_SEL_ENUM__enumvalues = {
0: 'DWB_OGAM_LUT_HOST_SEL_RAMA',
1: 'DWB_OGAM_LUT_HOST_SEL_RAMB',
}
DWB_OGAM_LUT_HOST_SEL_RAMA = 0
DWB_OGAM_LUT_HOST_SEL_RAMB = 1
DWB_OGAM_LUT_HOST_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM'
DWB_OGAM_LUT_READ_COLOR_SEL_ENUM__enumvalues = {
0: 'DWB_OGAM_LUT_READ_COLOR_SEL_B',
1: 'DWB_OGAM_LUT_READ_COLOR_SEL_G',
2: 'DWB_OGAM_LUT_READ_COLOR_SEL_R',
3: 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED',
}
DWB_OGAM_LUT_READ_COLOR_SEL_B = 0
DWB_OGAM_LUT_READ_COLOR_SEL_G = 1
DWB_OGAM_LUT_READ_COLOR_SEL_R = 2
DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 3
DWB_OGAM_LUT_READ_COLOR_SEL_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_LUT_READ_DBG_ENUM'
DWB_OGAM_LUT_READ_DBG_ENUM__enumvalues = {
0: 'DWB_OGAM_LUT_READ_DBG_DISABLE',
1: 'DWB_OGAM_LUT_READ_DBG_ENABLE',
}
DWB_OGAM_LUT_READ_DBG_DISABLE = 0
DWB_OGAM_LUT_READ_DBG_ENABLE = 1
DWB_OGAM_LUT_READ_DBG_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_MODE_ENUM'
DWB_OGAM_MODE_ENUM__enumvalues = {
0: 'DWB_OGAM_MODE_BYPASS',
1: 'DWB_OGAM_MODE_RESERVED',
2: 'DWB_OGAM_MODE_RAM_LUT_ENABLED',
}
DWB_OGAM_MODE_BYPASS = 0
DWB_OGAM_MODE_RESERVED = 1
DWB_OGAM_MODE_RAM_LUT_ENABLED = 2
DWB_OGAM_MODE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_PWL_DISABLE_ENUM'
DWB_OGAM_PWL_DISABLE_ENUM__enumvalues = {
0: 'DWB_OGAM_PWL_DISABLE_FALSE',
1: 'DWB_OGAM_PWL_DISABLE_TRUE',
}
DWB_OGAM_PWL_DISABLE_FALSE = 0
DWB_OGAM_PWL_DISABLE_TRUE = 1
DWB_OGAM_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'DWB_OGAM_SELECT_ENUM'
DWB_OGAM_SELECT_ENUM__enumvalues = {
0: 'DWB_OGAM_SELECT_A',
1: 'DWB_OGAM_SELECT_B',
}
DWB_OGAM_SELECT_A = 0
DWB_OGAM_SELECT_B = 1
DWB_OGAM_SELECT_ENUM = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN'
RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN__enumvalues = {
0: 'RDPCSPIPE_EXT_PCLK_EN_DISABLE',
1: 'RDPCSPIPE_EXT_PCLK_EN_ENABLE',
}
RDPCSPIPE_EXT_PCLK_EN_DISABLE = 0
RDPCSPIPE_EXT_PCLK_EN_ENABLE = 1
RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN'
RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN__enumvalues = {
0: 'RDPCSPIPE_APBCLK_DISABLE',
1: 'RDPCSPIPE_APBCLK_ENABLE',
}
RDPCSPIPE_APBCLK_DISABLE = 0
RDPCSPIPE_APBCLK_ENABLE = 1
RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON'
RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON__enumvalues = {
0: 'RDPCS_PIPE_CLK_CLOCK_OFF',
1: 'RDPCS_PIPE_CLK_CLOCK_ON',
}
RDPCS_PIPE_CLK_CLOCK_OFF = 0
RDPCS_PIPE_CLK_CLOCK_ON = 1
RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN'
RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN__enumvalues = {
0: 'RDPCS_PIPE_CLK_DISABLE',
1: 'RDPCS_PIPE_CLK_ENABLE',
}
RDPCS_PIPE_CLK_DISABLE = 0
RDPCS_PIPE_CLK_ENABLE = 1
RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS'
RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS__enumvalues = {
0: 'RDPCS_PIPE_CLK_GATE_ENABLE',
1: 'RDPCS_PIPE_CLK_GATE_DISABLE',
}
RDPCS_PIPE_CLK_GATE_ENABLE = 0
RDPCS_PIPE_CLK_GATE_DISABLE = 1
RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON'
RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON__enumvalues = {
0: 'RDPCS_PIPE_PHYD32CLK_CLOCK_OFF',
1: 'RDPCS_PIPE_PHYD32CLK_CLOCK_ON',
}
RDPCS_PIPE_PHYD32CLK_CLOCK_OFF = 0
RDPCS_PIPE_PHYD32CLK_CLOCK_ON = 1
RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON'
RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON__enumvalues = {
0: 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF',
1: 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON',
}
RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF = 0
RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON = 1
RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN'
RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN__enumvalues = {
0: 'RDPCSPIPE_SRAMCLK_DISABLE',
1: 'RDPCSPIPE_SRAMCLK_ENABLE',
}
RDPCSPIPE_SRAMCLK_DISABLE = 0
RDPCSPIPE_SRAMCLK_ENABLE = 1
RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS'
RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS__enumvalues = {
0: 'RDPCSPIPE_SRAMCLK_GATE_ENABLE',
1: 'RDPCSPIPE_SRAMCLK_GATE_DISABLE',
}
RDPCSPIPE_SRAMCLK_GATE_ENABLE = 0
RDPCSPIPE_SRAMCLK_GATE_DISABLE = 1
RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS'
RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS__enumvalues = {
0: 'RDPCSPIPE_SRAMCLK_NOT_PASS',
1: 'RDPCSPIPE_SRAMCLK_PASS',
}
RDPCSPIPE_SRAMCLK_NOT_PASS = 0
RDPCSPIPE_SRAMCLK_PASS = 1
RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN'
RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN__enumvalues = {
0: 'RDPCS_PIPE_FIFO_DISABLE',
1: 'RDPCS_PIPE_FIFO_ENABLE',
}
RDPCS_PIPE_FIFO_DISABLE = 0
RDPCS_PIPE_FIFO_ENABLE = 1
RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN'
RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN__enumvalues = {
0: 'RDPCS_PIPE_FIFO_LANE_DISABLE',
1: 'RDPCS_PIPE_FIFO_LANE_ENABLE',
}
RDPCS_PIPE_FIFO_LANE_DISABLE = 0
RDPCS_PIPE_FIFO_LANE_ENABLE = 1
RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET'
RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET__enumvalues = {
0: 'RDPCS_PIPE_SOFT_RESET_DISABLE',
1: 'RDPCS_PIPE_SOFT_RESET_ENABLE',
}
RDPCS_PIPE_SOFT_RESET_DISABLE = 0
RDPCS_PIPE_SOFT_RESET_ENABLE = 1
RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET'
RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET__enumvalues = {
0: 'RDPCSPIPE_SRAM_SRAM_RESET_DISABLE',
1: 'RDPCSPIPE_SRAM_SRAM_RESET_ENABLE',
}
RDPCSPIPE_SRAM_SRAM_RESET_DISABLE = 0
RDPCSPIPE_SRAM_SRAM_RESET_ENABLE = 1
RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK'
RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK__enumvalues = {
0: 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE',
1: 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE',
}
RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE = 0
RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE = 1
RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_DBG_OCLA_SEL'
RDPCSPIPE_DBG_OCLA_SEL__enumvalues = {
0: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0',
1: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8',
2: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16',
3: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24',
4: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32',
5: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40',
6: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48',
7: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56',
}
RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0 = 0
RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8 = 1
RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16 = 2
RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24 = 3
RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32 = 4
RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40 = 5
RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48 = 6
RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56 = 7
RDPCSPIPE_DBG_OCLA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_ENC_TYPE'
RDPCSPIPE_ENC_TYPE__enumvalues = {
0: 'HDMI_TMDS_OR_DP_8B10B',
1: 'HDMI_FRL',
2: 'DP_128B132B',
}
HDMI_TMDS_OR_DP_8B10B = 0
HDMI_FRL = 1
DP_128B132B = 2
RDPCSPIPE_ENC_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_FIFO_EMPTY'
RDPCSPIPE_FIFO_EMPTY__enumvalues = {
0: 'RDPCSPIPE_FIFO_NOT_EMPTY',
1: 'RDPCSPIPE_FIFO_IS_EMPTY',
}
RDPCSPIPE_FIFO_NOT_EMPTY = 0
RDPCSPIPE_FIFO_IS_EMPTY = 1
RDPCSPIPE_FIFO_EMPTY = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_FIFO_FULL'
RDPCSPIPE_FIFO_FULL__enumvalues = {
0: 'RDPCSPIPE_FIFO_NOT_FULL',
1: 'RDPCSPIPE_FIFO_IS_FULL',
}
RDPCSPIPE_FIFO_NOT_FULL = 0
RDPCSPIPE_FIFO_IS_FULL = 1
RDPCSPIPE_FIFO_FULL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK'
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK__enumvalues = {
0: 'RDPCSPIPE_APB_PSLVERR_MASK_DISABLE',
1: 'RDPCSPIPE_APB_PSLVERR_MASK_ENABLE',
}
RDPCSPIPE_APB_PSLVERR_MASK_DISABLE = 0
RDPCSPIPE_APB_PSLVERR_MASK_ENABLE = 1
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE'
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE__enumvalues = {
0: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE',
1: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE',
}
RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE = 0
RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE = 1
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK'
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK__enumvalues = {
0: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE',
1: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE',
}
RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0
RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE = 1
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE'
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE__enumvalues = {
0: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE',
1: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE',
}
RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE = 0
RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE = 1
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK'
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK__enumvalues = {
0: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE',
1: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE',
}
RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0
RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 1
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK'
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK__enumvalues = {
0: 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE',
1: 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE',
}
RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE = 0
RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE = 1
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK'
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK__enumvalues = {
0: 'RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE',
1: 'RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE',
}
RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE = 0
RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE = 1
RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK'
RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK__enumvalues = {
0: 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE',
1: 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE',
}
RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE = 0
RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE = 1
RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PACK_MODE'
RDPCSPIPE_PACK_MODE__enumvalues = {
0: 'TIGHT_PACK',
1: 'LOOSE_PACK',
}
TIGHT_PACK = 0
LOOSE_PACK = 1
RDPCSPIPE_PACK_MODE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL'
RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL__enumvalues = {
0: 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB',
1: 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC',
}
RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB = 0
RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC = 1
RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL'
RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL__enumvalues = {
0: 'RDPCSPIPE_PHY_CR_PARA_SEL_JTAG',
1: 'RDPCSPIPE_PHY_CR_PARA_SEL_CR',
}
RDPCSPIPE_PHY_CR_PARA_SEL_JTAG = 0
RDPCSPIPE_PHY_CR_PARA_SEL_CR = 1
RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE'
RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE__enumvalues = {
0: 'RDPCSPIPE_PHY_REF_RANGE_0',
1: 'RDPCSPIPE_PHY_REF_RANGE_1',
2: 'RDPCSPIPE_PHY_REF_RANGE_2',
3: 'RDPCSPIPE_PHY_REF_RANGE_3',
4: 'RDPCSPIPE_PHY_REF_RANGE_4',
5: 'RDPCSPIPE_PHY_REF_RANGE_5',
6: 'RDPCSPIPE_PHY_REF_RANGE_6',
7: 'RDPCSPIPE_PHY_REF_RANGE_7',
}
RDPCSPIPE_PHY_REF_RANGE_0 = 0
RDPCSPIPE_PHY_REF_RANGE_1 = 1
RDPCSPIPE_PHY_REF_RANGE_2 = 2
RDPCSPIPE_PHY_REF_RANGE_3 = 3
RDPCSPIPE_PHY_REF_RANGE_4 = 4
RDPCSPIPE_PHY_REF_RANGE_5 = 5
RDPCSPIPE_PHY_REF_RANGE_6 = 6
RDPCSPIPE_PHY_REF_RANGE_7 = 7
RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE'
RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE__enumvalues = {
0: 'RDPCSPIPE_SRAM_EXT_LD_NOT_DONE',
1: 'RDPCSPIPE_SRAM_EXT_LD_DONE',
}
RDPCSPIPE_SRAM_EXT_LD_NOT_DONE = 0
RDPCSPIPE_SRAM_EXT_LD_DONE = 1
RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE'
RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE__enumvalues = {
0: 'RDPCSPIPE_SRAM_INIT_NOT_DONE',
1: 'RDPCSPIPE_SRAM_INIT_DONE',
}
RDPCSPIPE_SRAM_INIT_NOT_DONE = 0
RDPCSPIPE_SRAM_INIT_DONE = 1
RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV'
RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__enumvalues = {
0: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1',
1: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2',
2: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3',
3: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8',
4: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16',
}
RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1 = 0
RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2 = 1
RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3 = 2
RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8 = 3
RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16 = 4
RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV'
RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__enumvalues = {
0: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0',
1: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1',
2: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2',
3: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3',
}
RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0
RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 1
RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 2
RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 3
RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV'
RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__enumvalues = {
0: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV',
1: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2',
2: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4',
3: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8',
4: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3',
5: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5',
6: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6',
7: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10',
}
RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV = 0
RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2 = 1
RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4 = 2
RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8 = 3
RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3 = 4
RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5 = 5
RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6 = 6
RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10 = 7
RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL'
RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL__enumvalues = {
0: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54',
1: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52',
2: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50',
3: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48',
4: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46',
5: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44',
6: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42',
7: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40',
}
RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54 = 0
RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52 = 1
RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50 = 2
RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48 = 3
RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46 = 4
RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44 = 5
RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42 = 6
RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40 = 7
RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT'
RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT__enumvalues = {
0: 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT',
1: 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT',
}
RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0
RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT = 1
RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE'
RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE__enumvalues = {
0: 'RDPCSPIPE_PHY_DP_TX_RATE',
1: 'RDPCSPIPE_PHY_DP_TX_RATE_DIV2',
2: 'RDPCSPIPE_PHY_DP_TX_RATE_DIV4',
}
RDPCSPIPE_PHY_DP_TX_RATE = 0
RDPCSPIPE_PHY_DP_TX_RATE_DIV2 = 1
RDPCSPIPE_PHY_DP_TX_RATE_DIV4 = 2
RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH'
RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH__enumvalues = {
0: 'RDPCSPIPE_PHY_DP_TX_WIDTH_8',
1: 'RDPCSPIPE_PHY_DP_TX_WIDTH_10',
2: 'RDPCSPIPE_PHY_DP_TX_WIDTH_16',
3: 'RDPCSPIPE_PHY_DP_TX_WIDTH_20',
}
RDPCSPIPE_PHY_DP_TX_WIDTH_8 = 0
RDPCSPIPE_PHY_DP_TX_WIDTH_10 = 1
RDPCSPIPE_PHY_DP_TX_WIDTH_16 = 2
RDPCSPIPE_PHY_DP_TX_WIDTH_20 = 3
RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE'
RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE__enumvalues = {
0: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP',
1: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD',
2: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF',
3: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN',
}
RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP = 0
RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD = 1
RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF = 2
RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN = 3
RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_IF_WIDTH'
RDPCSPIPE_PHY_IF_WIDTH__enumvalues = {
0: 'PHY_IF_WIDTH_10BIT',
1: 'PHY_IF_WIDTH_20BIT',
2: 'PHY_IF_WIDTH_40BIT',
3: 'PHY_IF_WIDTH_80BIT',
}
PHY_IF_WIDTH_10BIT = 0
PHY_IF_WIDTH_20BIT = 1
PHY_IF_WIDTH_40BIT = 2
PHY_IF_WIDTH_80BIT = 3
RDPCSPIPE_PHY_IF_WIDTH = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_RATE'
RDPCSPIPE_PHY_RATE__enumvalues = {
0: 'PHY_DP_RATE_1P62',
1: 'PHY_DP_RATE_2P7',
2: 'PHY_DP_RATE_5P4',
3: 'PHY_DP_RATE_8P1',
4: 'PHY_DP_RATE_2P16',
5: 'PHY_DP_RATE_2P43',
6: 'PHY_DP_RATE_3P24',
7: 'PHY_DP_RATE_4P32',
8: 'PHY_DP_RATE_10P',
9: 'PHY_DP_RATE_13P5',
10: 'PHY_DP_RATE_20P',
15: 'PHY_CUSTOM_RATE',
}
PHY_DP_RATE_1P62 = 0
PHY_DP_RATE_2P7 = 1
PHY_DP_RATE_5P4 = 2
PHY_DP_RATE_8P1 = 3
PHY_DP_RATE_2P16 = 4
PHY_DP_RATE_2P43 = 5
PHY_DP_RATE_3P24 = 6
PHY_DP_RATE_4P32 = 7
PHY_DP_RATE_10P = 8
PHY_DP_RATE_13P5 = 9
PHY_DP_RATE_20P = 10
PHY_CUSTOM_RATE = 15
RDPCSPIPE_PHY_RATE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_PHY_REF_ALT_CLK_EN'
RDPCSPIPE_PHY_REF_ALT_CLK_EN__enumvalues = {
0: 'RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE',
1: 'RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE',
}
RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE = 0
RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE = 1
RDPCSPIPE_PHY_REF_ALT_CLK_EN = ctypes.c_uint32 # enum
# values for enumeration 'RDPCSPIPE_TEST_CLK_SEL'
RDPCSPIPE_TEST_CLK_SEL__enumvalues = {
0: 'RDPCSPIPE_TEST_CLK_SEL_NONE',
1: 'RDPCSPIPE_TEST_CLK_SEL_CFGCLK',
2: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS',
3: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS',
4: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4',
5: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4',
6: 'RDPCSPIPE_TEST_CLK_SEL_SRAMCLK',
7: 'RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK',
8: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK',
9: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK',
10: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK',
11: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK',
12: 'RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK',
13: 'RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK',
14: 'RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK',
15: 'RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk',
16: 'RDPCSPIPE_TEST_CLK_SEL_dtb_out0',
17: 'RDPCSPIPE_TEST_CLK_SEL_dtb_out1',
}
RDPCSPIPE_TEST_CLK_SEL_NONE = 0
RDPCSPIPE_TEST_CLK_SEL_CFGCLK = 1
RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 2
RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 3
RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 4
RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 5
RDPCSPIPE_TEST_CLK_SEL_SRAMCLK = 6
RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK = 7
RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK = 8
RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK = 9
RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK = 10
RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK = 11
RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 12
RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 13
RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK = 14
RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk = 15
RDPCSPIPE_TEST_CLK_SEL_dtb_out0 = 16
RDPCSPIPE_TEST_CLK_SEL_dtb_out1 = 17
RDPCSPIPE_TEST_CLK_SEL = ctypes.c_uint32 # enum
# values for enumeration 'RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB'
RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB__enumvalues = {
0: 'RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE',
1: 'RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE',
}
RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE = 0
RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE = 1
RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB = ctypes.c_uint32 # enum
# values for enumeration 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE'
RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE__enumvalues = {
0: 'RDPCSPIPE_MEM_PWR_NO_FORCE',
1: 'RDPCSPIPE_MEM_PWR_LIGHT_SLEEP',
2: 'RDPCSPIPE_MEM_PWR_DEEP_SLEEP',
3: 'RDPCSPIPE_MEM_PWR_SHUT_DOWN',
}
RDPCSPIPE_MEM_PWR_NO_FORCE = 0
RDPCSPIPE_MEM_PWR_LIGHT_SLEEP = 1
RDPCSPIPE_MEM_PWR_DEEP_SLEEP = 2
RDPCSPIPE_MEM_PWR_SHUT_DOWN = 3
RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE = ctypes.c_uint32 # enum
# values for enumeration 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE'
RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE__enumvalues = {
0: 'RDPCSPIPE_MEM_PWR_PWR_STATE_ON',
1: 'RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP',
2: 'RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP',
3: 'RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN',
}
RDPCSPIPE_MEM_PWR_PWR_STATE_ON = 0
RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 1
RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP = 2
RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN = 3
RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE = ctypes.c_uint32 # enum
# values for enumeration 'RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK'
RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK__enumvalues = {
0: 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE',
1: 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE',
}
RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE = 0
RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE = 1
RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK = ctypes.c_uint32 # enum
# values for enumeration 'GDS_PERFCOUNT_SELECT'
GDS_PERFCOUNT_SELECT__enumvalues = {
0: 'GDS_PERF_SEL_WR_COMP',
1: 'GDS_PERF_SEL_WBUF_WR',
2: 'GDS_PERF_SEL_SE0_NORET',
3: 'GDS_PERF_SEL_SE0_RET',
4: 'GDS_PERF_SEL_SE0_ORD_CNT',
5: 'GDS_PERF_SEL_SE0_2COMP_REQ',
6: 'GDS_PERF_SEL_SE0_ORD_WAVE_VALID',
7: 'GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD',
8: 'GDS_PERF_SEL_SE0_GDS_WR_OP',
9: 'GDS_PERF_SEL_SE0_GDS_RD_OP',
10: 'GDS_PERF_SEL_SE0_GDS_ATOM_OP',
11: 'GDS_PERF_SEL_SE0_GDS_REL_OP',
12: 'GDS_PERF_SEL_SE0_GDS_CMPXCH_OP',
13: 'GDS_PERF_SEL_SE0_GDS_BYTE_OP',
14: 'GDS_PERF_SEL_SE0_GDS_SHORT_OP',
15: 'GDS_PERF_SEL_SE1_NORET',
16: 'GDS_PERF_SEL_SE1_RET',
17: 'GDS_PERF_SEL_SE1_ORD_CNT',
18: 'GDS_PERF_SEL_SE1_2COMP_REQ',
19: 'GDS_PERF_SEL_SE1_ORD_WAVE_VALID',
20: 'GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD',
21: 'GDS_PERF_SEL_SE1_GDS_WR_OP',
22: 'GDS_PERF_SEL_SE1_GDS_RD_OP',
23: 'GDS_PERF_SEL_SE1_GDS_ATOM_OP',
24: 'GDS_PERF_SEL_SE1_GDS_REL_OP',
25: 'GDS_PERF_SEL_SE1_GDS_CMPXCH_OP',
26: 'GDS_PERF_SEL_SE1_GDS_BYTE_OP',
27: 'GDS_PERF_SEL_SE1_GDS_SHORT_OP',
28: 'GDS_PERF_SEL_SE2_NORET',
29: 'GDS_PERF_SEL_SE2_RET',
30: 'GDS_PERF_SEL_SE2_ORD_CNT',
31: 'GDS_PERF_SEL_SE2_2COMP_REQ',
32: 'GDS_PERF_SEL_SE2_ORD_WAVE_VALID',
33: 'GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD',
34: 'GDS_PERF_SEL_SE2_GDS_WR_OP',
35: 'GDS_PERF_SEL_SE2_GDS_RD_OP',
36: 'GDS_PERF_SEL_SE2_GDS_ATOM_OP',
37: 'GDS_PERF_SEL_SE2_GDS_REL_OP',
38: 'GDS_PERF_SEL_SE2_GDS_CMPXCH_OP',
39: 'GDS_PERF_SEL_SE2_GDS_BYTE_OP',
40: 'GDS_PERF_SEL_SE2_GDS_SHORT_OP',
41: 'GDS_PERF_SEL_SE3_NORET',
42: 'GDS_PERF_SEL_SE3_RET',
43: 'GDS_PERF_SEL_SE3_ORD_CNT',
44: 'GDS_PERF_SEL_SE3_2COMP_REQ',
45: 'GDS_PERF_SEL_SE3_ORD_WAVE_VALID',
46: 'GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD',
47: 'GDS_PERF_SEL_SE3_GDS_WR_OP',
48: 'GDS_PERF_SEL_SE3_GDS_RD_OP',
49: 'GDS_PERF_SEL_SE3_GDS_ATOM_OP',
50: 'GDS_PERF_SEL_SE3_GDS_REL_OP',
51: 'GDS_PERF_SEL_SE3_GDS_CMPXCH_OP',
52: 'GDS_PERF_SEL_SE3_GDS_BYTE_OP',
53: 'GDS_PERF_SEL_SE3_GDS_SHORT_OP',
54: 'GDS_PERF_SEL_SE4_NORET',
55: 'GDS_PERF_SEL_SE4_RET',
56: 'GDS_PERF_SEL_SE4_ORD_CNT',
57: 'GDS_PERF_SEL_SE4_2COMP_REQ',
58: 'GDS_PERF_SEL_SE4_ORD_WAVE_VALID',
59: 'GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD',
60: 'GDS_PERF_SEL_SE4_GDS_WR_OP',
61: 'GDS_PERF_SEL_SE4_GDS_RD_OP',
62: 'GDS_PERF_SEL_SE4_GDS_ATOM_OP',
63: 'GDS_PERF_SEL_SE4_GDS_REL_OP',
64: 'GDS_PERF_SEL_SE4_GDS_CMPXCH_OP',
65: 'GDS_PERF_SEL_SE4_GDS_BYTE_OP',
66: 'GDS_PERF_SEL_SE4_GDS_SHORT_OP',
67: 'GDS_PERF_SEL_SE5_NORET',
68: 'GDS_PERF_SEL_SE5_RET',
69: 'GDS_PERF_SEL_SE5_ORD_CNT',
70: 'GDS_PERF_SEL_SE5_2COMP_REQ',
71: 'GDS_PERF_SEL_SE5_ORD_WAVE_VALID',
72: 'GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD',
73: 'GDS_PERF_SEL_SE5_GDS_WR_OP',
74: 'GDS_PERF_SEL_SE5_GDS_RD_OP',
75: 'GDS_PERF_SEL_SE5_GDS_ATOM_OP',
76: 'GDS_PERF_SEL_SE5_GDS_REL_OP',
77: 'GDS_PERF_SEL_SE5_GDS_CMPXCH_OP',
78: 'GDS_PERF_SEL_SE5_GDS_BYTE_OP',
79: 'GDS_PERF_SEL_SE5_GDS_SHORT_OP',
80: 'GDS_PERF_SEL_SE6_NORET',
81: 'GDS_PERF_SEL_SE6_RET',
82: 'GDS_PERF_SEL_SE6_ORD_CNT',
83: 'GDS_PERF_SEL_SE6_2COMP_REQ',
84: 'GDS_PERF_SEL_SE6_ORD_WAVE_VALID',
85: 'GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD',
86: 'GDS_PERF_SEL_SE6_GDS_WR_OP',
87: 'GDS_PERF_SEL_SE6_GDS_RD_OP',
88: 'GDS_PERF_SEL_SE6_GDS_ATOM_OP',
89: 'GDS_PERF_SEL_SE6_GDS_REL_OP',
90: 'GDS_PERF_SEL_SE6_GDS_CMPXCH_OP',
91: 'GDS_PERF_SEL_SE6_GDS_BYTE_OP',
92: 'GDS_PERF_SEL_SE6_GDS_SHORT_OP',
93: 'GDS_PERF_SEL_SE7_NORET',
94: 'GDS_PERF_SEL_SE7_RET',
95: 'GDS_PERF_SEL_SE7_ORD_CNT',
96: 'GDS_PERF_SEL_SE7_2COMP_REQ',
97: 'GDS_PERF_SEL_SE7_ORD_WAVE_VALID',
98: 'GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD',
99: 'GDS_PERF_SEL_SE7_GDS_WR_OP',
100: 'GDS_PERF_SEL_SE7_GDS_RD_OP',
101: 'GDS_PERF_SEL_SE7_GDS_ATOM_OP',
102: 'GDS_PERF_SEL_SE7_GDS_REL_OP',
103: 'GDS_PERF_SEL_SE7_GDS_CMPXCH_OP',
104: 'GDS_PERF_SEL_SE7_GDS_BYTE_OP',
105: 'GDS_PERF_SEL_SE7_GDS_SHORT_OP',
106: 'GDS_PERF_SEL_GWS_RELEASED',
107: 'GDS_PERF_SEL_GWS_BYPASS',
}
GDS_PERF_SEL_WR_COMP = 0
GDS_PERF_SEL_WBUF_WR = 1
GDS_PERF_SEL_SE0_NORET = 2
GDS_PERF_SEL_SE0_RET = 3
GDS_PERF_SEL_SE0_ORD_CNT = 4
GDS_PERF_SEL_SE0_2COMP_REQ = 5
GDS_PERF_SEL_SE0_ORD_WAVE_VALID = 6
GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD = 7
GDS_PERF_SEL_SE0_GDS_WR_OP = 8
GDS_PERF_SEL_SE0_GDS_RD_OP = 9
GDS_PERF_SEL_SE0_GDS_ATOM_OP = 10
GDS_PERF_SEL_SE0_GDS_REL_OP = 11
GDS_PERF_SEL_SE0_GDS_CMPXCH_OP = 12
GDS_PERF_SEL_SE0_GDS_BYTE_OP = 13
GDS_PERF_SEL_SE0_GDS_SHORT_OP = 14
GDS_PERF_SEL_SE1_NORET = 15
GDS_PERF_SEL_SE1_RET = 16
GDS_PERF_SEL_SE1_ORD_CNT = 17
GDS_PERF_SEL_SE1_2COMP_REQ = 18
GDS_PERF_SEL_SE1_ORD_WAVE_VALID = 19
GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD = 20
GDS_PERF_SEL_SE1_GDS_WR_OP = 21
GDS_PERF_SEL_SE1_GDS_RD_OP = 22
GDS_PERF_SEL_SE1_GDS_ATOM_OP = 23
GDS_PERF_SEL_SE1_GDS_REL_OP = 24
GDS_PERF_SEL_SE1_GDS_CMPXCH_OP = 25
GDS_PERF_SEL_SE1_GDS_BYTE_OP = 26
GDS_PERF_SEL_SE1_GDS_SHORT_OP = 27
GDS_PERF_SEL_SE2_NORET = 28
GDS_PERF_SEL_SE2_RET = 29
GDS_PERF_SEL_SE2_ORD_CNT = 30
GDS_PERF_SEL_SE2_2COMP_REQ = 31
GDS_PERF_SEL_SE2_ORD_WAVE_VALID = 32
GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD = 33
GDS_PERF_SEL_SE2_GDS_WR_OP = 34
GDS_PERF_SEL_SE2_GDS_RD_OP = 35
GDS_PERF_SEL_SE2_GDS_ATOM_OP = 36
GDS_PERF_SEL_SE2_GDS_REL_OP = 37
GDS_PERF_SEL_SE2_GDS_CMPXCH_OP = 38
GDS_PERF_SEL_SE2_GDS_BYTE_OP = 39
GDS_PERF_SEL_SE2_GDS_SHORT_OP = 40
GDS_PERF_SEL_SE3_NORET = 41
GDS_PERF_SEL_SE3_RET = 42
GDS_PERF_SEL_SE3_ORD_CNT = 43
GDS_PERF_SEL_SE3_2COMP_REQ = 44
GDS_PERF_SEL_SE3_ORD_WAVE_VALID = 45
GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD = 46
GDS_PERF_SEL_SE3_GDS_WR_OP = 47
GDS_PERF_SEL_SE3_GDS_RD_OP = 48
GDS_PERF_SEL_SE3_GDS_ATOM_OP = 49
GDS_PERF_SEL_SE3_GDS_REL_OP = 50
GDS_PERF_SEL_SE3_GDS_CMPXCH_OP = 51
GDS_PERF_SEL_SE3_GDS_BYTE_OP = 52
GDS_PERF_SEL_SE3_GDS_SHORT_OP = 53
GDS_PERF_SEL_SE4_NORET = 54
GDS_PERF_SEL_SE4_RET = 55
GDS_PERF_SEL_SE4_ORD_CNT = 56
GDS_PERF_SEL_SE4_2COMP_REQ = 57
GDS_PERF_SEL_SE4_ORD_WAVE_VALID = 58
GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD = 59
GDS_PERF_SEL_SE4_GDS_WR_OP = 60
GDS_PERF_SEL_SE4_GDS_RD_OP = 61
GDS_PERF_SEL_SE4_GDS_ATOM_OP = 62
GDS_PERF_SEL_SE4_GDS_REL_OP = 63
GDS_PERF_SEL_SE4_GDS_CMPXCH_OP = 64
GDS_PERF_SEL_SE4_GDS_BYTE_OP = 65
GDS_PERF_SEL_SE4_GDS_SHORT_OP = 66
GDS_PERF_SEL_SE5_NORET = 67
GDS_PERF_SEL_SE5_RET = 68
GDS_PERF_SEL_SE5_ORD_CNT = 69
GDS_PERF_SEL_SE5_2COMP_REQ = 70
GDS_PERF_SEL_SE5_ORD_WAVE_VALID = 71
GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD = 72
GDS_PERF_SEL_SE5_GDS_WR_OP = 73
GDS_PERF_SEL_SE5_GDS_RD_OP = 74
GDS_PERF_SEL_SE5_GDS_ATOM_OP = 75
GDS_PERF_SEL_SE5_GDS_REL_OP = 76
GDS_PERF_SEL_SE5_GDS_CMPXCH_OP = 77
GDS_PERF_SEL_SE5_GDS_BYTE_OP = 78
GDS_PERF_SEL_SE5_GDS_SHORT_OP = 79
GDS_PERF_SEL_SE6_NORET = 80
GDS_PERF_SEL_SE6_RET = 81
GDS_PERF_SEL_SE6_ORD_CNT = 82
GDS_PERF_SEL_SE6_2COMP_REQ = 83
GDS_PERF_SEL_SE6_ORD_WAVE_VALID = 84
GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD = 85
GDS_PERF_SEL_SE6_GDS_WR_OP = 86
GDS_PERF_SEL_SE6_GDS_RD_OP = 87
GDS_PERF_SEL_SE6_GDS_ATOM_OP = 88
GDS_PERF_SEL_SE6_GDS_REL_OP = 89
GDS_PERF_SEL_SE6_GDS_CMPXCH_OP = 90
GDS_PERF_SEL_SE6_GDS_BYTE_OP = 91
GDS_PERF_SEL_SE6_GDS_SHORT_OP = 92
GDS_PERF_SEL_SE7_NORET = 93
GDS_PERF_SEL_SE7_RET = 94
GDS_PERF_SEL_SE7_ORD_CNT = 95
GDS_PERF_SEL_SE7_2COMP_REQ = 96
GDS_PERF_SEL_SE7_ORD_WAVE_VALID = 97
GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD = 98
GDS_PERF_SEL_SE7_GDS_WR_OP = 99
GDS_PERF_SEL_SE7_GDS_RD_OP = 100
GDS_PERF_SEL_SE7_GDS_ATOM_OP = 101
GDS_PERF_SEL_SE7_GDS_REL_OP = 102
GDS_PERF_SEL_SE7_GDS_CMPXCH_OP = 103
GDS_PERF_SEL_SE7_GDS_BYTE_OP = 104
GDS_PERF_SEL_SE7_GDS_SHORT_OP = 105
GDS_PERF_SEL_GWS_RELEASED = 106
GDS_PERF_SEL_GWS_BYPASS = 107
GDS_PERFCOUNT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'BlendOp'
BlendOp__enumvalues = {
0: 'BLEND_ZERO',
1: 'BLEND_ONE',
2: 'BLEND_SRC_COLOR',
3: 'BLEND_ONE_MINUS_SRC_COLOR',
4: 'BLEND_SRC_ALPHA',
5: 'BLEND_ONE_MINUS_SRC_ALPHA',
6: 'BLEND_DST_ALPHA',
7: 'BLEND_ONE_MINUS_DST_ALPHA',
8: 'BLEND_DST_COLOR',
9: 'BLEND_ONE_MINUS_DST_COLOR',
10: 'BLEND_SRC_ALPHA_SATURATE',
11: 'BLEND_CONSTANT_COLOR',
12: 'BLEND_ONE_MINUS_CONSTANT_COLOR',
13: 'BLEND_SRC1_COLOR',
14: 'BLEND_INV_SRC1_COLOR',
15: 'BLEND_SRC1_ALPHA',
16: 'BLEND_INV_SRC1_ALPHA',
17: 'BLEND_CONSTANT_ALPHA',
18: 'BLEND_ONE_MINUS_CONSTANT_ALPHA',
}
BLEND_ZERO = 0
BLEND_ONE = 1
BLEND_SRC_COLOR = 2
BLEND_ONE_MINUS_SRC_COLOR = 3
BLEND_SRC_ALPHA = 4
BLEND_ONE_MINUS_SRC_ALPHA = 5
BLEND_DST_ALPHA = 6
BLEND_ONE_MINUS_DST_ALPHA = 7
BLEND_DST_COLOR = 8
BLEND_ONE_MINUS_DST_COLOR = 9
BLEND_SRC_ALPHA_SATURATE = 10
BLEND_CONSTANT_COLOR = 11
BLEND_ONE_MINUS_CONSTANT_COLOR = 12
BLEND_SRC1_COLOR = 13
BLEND_INV_SRC1_COLOR = 14
BLEND_SRC1_ALPHA = 15
BLEND_INV_SRC1_ALPHA = 16
BLEND_CONSTANT_ALPHA = 17
BLEND_ONE_MINUS_CONSTANT_ALPHA = 18
BlendOp = ctypes.c_uint32 # enum
GL__ZERO = BLEND_ZERO # macro
GL__ONE = BLEND_ONE # macro
GL__SRC_COLOR = BLEND_SRC_COLOR # macro
GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro
GL__DST_COLOR = BLEND_DST_COLOR # macro
GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro
GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro
GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro
GL__DST_ALPHA = BLEND_DST_ALPHA # macro
GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro
GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro
GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro
GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro
GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro
GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro
# values for enumeration 'BlendOpt'
BlendOpt__enumvalues = {
0: 'FORCE_OPT_AUTO',
1: 'FORCE_OPT_DISABLE',
2: 'FORCE_OPT_ENABLE_IF_SRC_A_0',
3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0',
4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0',
5: 'FORCE_OPT_ENABLE_IF_SRC_A_1',
6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1',
7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1',
}
FORCE_OPT_AUTO = 0
FORCE_OPT_DISABLE = 1
FORCE_OPT_ENABLE_IF_SRC_A_0 = 2
FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3
FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4
FORCE_OPT_ENABLE_IF_SRC_A_1 = 5
FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6
FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7
BlendOpt = ctypes.c_uint32 # enum
# values for enumeration 'CBMode'
CBMode__enumvalues = {
0: 'CB_DISABLE',
1: 'CB_NORMAL',
2: 'CB_ELIMINATE_FAST_CLEAR',
3: 'CB_DCC_DECOMPRESS',
4: 'CB_RESERVED',
}
CB_DISABLE = 0
CB_NORMAL = 1
CB_ELIMINATE_FAST_CLEAR = 2
CB_DCC_DECOMPRESS = 3
CB_RESERVED = 4
CBMode = ctypes.c_uint32 # enum
# values for enumeration 'CBPerfClearFilterSel'
CBPerfClearFilterSel__enumvalues = {
0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR',
1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR',
}
CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0
CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1
CBPerfClearFilterSel = ctypes.c_uint32 # enum
# values for enumeration 'CBPerfOpFilterSel'
CBPerfOpFilterSel__enumvalues = {
0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY',
1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION',
2: 'CB_PERF_OP_FILTER_SEL_RESOLVE',
3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS',
4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS',
5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR',
}
CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0
CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1
CB_PERF_OP_FILTER_SEL_RESOLVE = 2
CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3
CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4
CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5
CBPerfOpFilterSel = ctypes.c_uint32 # enum
# values for enumeration 'CBPerfSel'
CBPerfSel__enumvalues = {
0: 'CB_PERF_SEL_NONE',
1: 'CB_PERF_SEL_DRAWN_PIXEL',
2: 'CB_PERF_SEL_DRAWN_QUAD',
3: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT',
4: 'CB_PERF_SEL_DRAWN_TILE',
5: 'CB_PERF_SEL_FILTER_DRAWN_PIXEL',
6: 'CB_PERF_SEL_FILTER_DRAWN_QUAD',
7: 'CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT',
8: 'CB_PERF_SEL_FILTER_DRAWN_TILE',
9: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN',
10: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT',
11: 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN',
12: 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT',
13: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST',
14: 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT',
15: 'CB_PERF_SEL_CC_MC_READ_REQUEST',
16: 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT',
17: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY',
18: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB',
19: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY',
20: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB',
21: 'CB_PERF_SEL_RESERVED_21',
22: 'CB_PERF_SEL_RESERVED_22',
23: 'CB_PERF_SEL_RESERVED_23',
24: 'CB_PERF_SEL_RESERVED_24',
25: 'CB_PERF_SEL_RESERVED_25',
26: 'CB_PERF_SEL_RESERVED_26',
27: 'CB_PERF_SEL_RESERVED_27',
28: 'CB_PERF_SEL_RESERVED_28',
29: 'CB_PERF_SEL_RESERVED_29',
30: 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY',
31: 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB',
32: 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY',
33: 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB',
34: 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY',
35: 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB',
36: 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY',
37: 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB',
38: 'CB_PERF_SEL_RESERVED_38',
39: 'CB_PERF_SEL_RESERVED_39',
40: 'CB_PERF_SEL_RESERVED_40',
41: 'CB_PERF_SEL_RESERVED_41',
42: 'CB_PERF_SEL_RESERVED_42',
43: 'CB_PERF_SEL_RESERVED_43',
44: 'CB_PERF_SEL_RESERVED_44',
45: 'CB_PERF_SEL_RESERVED_45',
46: 'CB_PERF_SEL_RESERVED_46',
47: 'CB_PERF_SEL_RESERVED_47',
48: 'CB_PERF_SEL_RESERVED_48',
49: 'CB_PERF_SEL_RESERVED_49',
50: 'CB_PERF_SEL_STATIC_CLOCK_EN',
51: 'CB_PERF_SEL_PERFMON_CLOCK_EN',
52: 'CB_PERF_SEL_BLEND_CLOCK_EN',
53: 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN',
54: 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN',
55: 'CB_PERF_SEL_GRBM_CLOCK_EN',
56: 'CB_PERF_SEL_MEMARB_CLOCK_EN',
57: 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN',
58: 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN',
59: 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN',
60: 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN',
61: 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN',
62: 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN',
63: 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN',
64: 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN',
65: 'CB_PERF_SEL_RESERVED_65',
66: 'CB_PERF_SEL_RESERVED_66',
67: 'CB_PERF_SEL_RESERVED_67',
68: 'CB_PERF_SEL_RESERVED_68',
69: 'CB_PERF_SEL_RESERVED_69',
70: 'CB_PERF_SEL_RESERVED_70',
71: 'CB_PERF_SEL_RESERVED_71',
72: 'CB_PERF_SEL_RESERVED_72',
73: 'CB_PERF_SEL_RESERVED_73',
74: 'CB_PERF_SEL_RESERVED_74',
75: 'CB_PERF_SEL_RESERVED_75',
76: 'CB_PERF_SEL_RESERVED_76',
77: 'CB_PERF_SEL_RESERVED_77',
78: 'CB_PERF_SEL_RESERVED_78',
79: 'CB_PERF_SEL_RESERVED_79',
80: 'CB_PERF_SEL_RESERVED_80',
81: 'CB_PERF_SEL_RESERVED_81',
82: 'CB_PERF_SEL_RESERVED_82',
83: 'CB_PERF_SEL_RESERVED_83',
84: 'CB_PERF_SEL_RESERVED_84',
85: 'CB_PERF_SEL_RESERVED_85',
86: 'CB_PERF_SEL_RESERVED_86',
87: 'CB_PERF_SEL_RESERVED_87',
88: 'CB_PERF_SEL_RESERVED_88',
89: 'CB_PERF_SEL_RESERVED_89',
90: 'CB_PERF_SEL_RESERVED_90',
91: 'CB_PERF_SEL_RESERVED_91',
92: 'CB_PERF_SEL_RESERVED_92',
93: 'CB_PERF_SEL_RESERVED_93',
94: 'CB_PERF_SEL_RESERVED_94',
95: 'CB_PERF_SEL_RESERVED_95',
96: 'CB_PERF_SEL_RESERVED_96',
97: 'CB_PERF_SEL_RESERVED_97',
98: 'CB_PERF_SEL_RESERVED_98',
99: 'CB_PERF_SEL_RESERVED_99',
100: 'CB_PERF_SEL_CC_TAG_HIT',
101: 'CB_PERF_SEL_CC_CACHE_TAG_MISS',
102: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS',
103: 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT',
104: 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL',
105: 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL',
106: 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL',
107: 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL',
108: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL',
109: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL',
110: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL',
111: 'CB_PERF_SEL_CC_CACHE_STALL',
112: 'CB_PERF_SEL_CC_CACHE_FLUSH',
113: 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED',
114: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION',
115: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED',
116: 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED',
117: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC',
118: 'CB_PERF_SEL_RESERVED_118',
119: 'CB_PERF_SEL_RESERVED_119',
120: 'CB_PERF_SEL_RESERVED_120',
121: 'CB_PERF_SEL_RESERVED_121',
122: 'CB_PERF_SEL_RESERVED_122',
123: 'CB_PERF_SEL_RESERVED_123',
124: 'CB_PERF_SEL_RESERVED_124',
125: 'CB_PERF_SEL_RESERVED_125',
126: 'CB_PERF_SEL_RESERVED_126',
127: 'CB_PERF_SEL_RESERVED_127',
128: 'CB_PERF_SEL_RESERVED_128',
129: 'CB_PERF_SEL_RESERVED_129',
130: 'CB_PERF_SEL_RESERVED_130',
131: 'CB_PERF_SEL_RESERVED_131',
132: 'CB_PERF_SEL_RESERVED_132',
133: 'CB_PERF_SEL_RESERVED_133',
134: 'CB_PERF_SEL_RESERVED_134',
135: 'CB_PERF_SEL_RESERVED_135',
136: 'CB_PERF_SEL_RESERVED_136',
137: 'CB_PERF_SEL_RESERVED_137',
138: 'CB_PERF_SEL_RESERVED_138',
139: 'CB_PERF_SEL_RESERVED_139',
140: 'CB_PERF_SEL_RESERVED_140',
141: 'CB_PERF_SEL_RESERVED_141',
142: 'CB_PERF_SEL_RESERVED_142',
143: 'CB_PERF_SEL_RESERVED_143',
144: 'CB_PERF_SEL_RESERVED_144',
145: 'CB_PERF_SEL_RESERVED_145',
146: 'CB_PERF_SEL_RESERVED_146',
147: 'CB_PERF_SEL_RESERVED_147',
148: 'CB_PERF_SEL_RESERVED_148',
149: 'CB_PERF_SEL_RESERVED_149',
150: 'CB_PERF_SEL_DCC_CACHE_PERF_HIT',
151: 'CB_PERF_SEL_DCC_CACHE_TAG_MISS',
152: 'CB_PERF_SEL_DCC_CACHE_SECTOR_MISS',
153: 'CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL',
154: 'CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL',
155: 'CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL',
156: 'CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL',
157: 'CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL',
158: 'CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL',
159: 'CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL',
160: 'CB_PERF_SEL_DCC_CACHE_STALL',
161: 'CB_PERF_SEL_DCC_CACHE_FLUSH',
162: 'CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED',
163: 'CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED',
164: 'CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED',
165: 'CB_PERF_SEL_RESERVED_165',
166: 'CB_PERF_SEL_RESERVED_166',
167: 'CB_PERF_SEL_RESERVED_167',
168: 'CB_PERF_SEL_RESERVED_168',
169: 'CB_PERF_SEL_RESERVED_169',
170: 'CB_PERF_SEL_RESERVED_170',
171: 'CB_PERF_SEL_RESERVED_171',
172: 'CB_PERF_SEL_RESERVED_172',
173: 'CB_PERF_SEL_RESERVED_173',
174: 'CB_PERF_SEL_RESERVED_174',
175: 'CB_PERF_SEL_RESERVED_175',
176: 'CB_PERF_SEL_RESERVED_176',
177: 'CB_PERF_SEL_RESERVED_177',
178: 'CB_PERF_SEL_RESERVED_178',
179: 'CB_PERF_SEL_RESERVED_179',
180: 'CB_PERF_SEL_RESERVED_180',
181: 'CB_PERF_SEL_RESERVED_181',
182: 'CB_PERF_SEL_RESERVED_182',
183: 'CB_PERF_SEL_RESERVED_183',
184: 'CB_PERF_SEL_RESERVED_184',
185: 'CB_PERF_SEL_RESERVED_185',
186: 'CB_PERF_SEL_RESERVED_186',
187: 'CB_PERF_SEL_RESERVED_187',
188: 'CB_PERF_SEL_RESERVED_188',
189: 'CB_PERF_SEL_RESERVED_189',
190: 'CB_PERF_SEL_RESERVED_190',
191: 'CB_PERF_SEL_RESERVED_191',
192: 'CB_PERF_SEL_RESERVED_192',
193: 'CB_PERF_SEL_RESERVED_193',
194: 'CB_PERF_SEL_RESERVED_194',
195: 'CB_PERF_SEL_RESERVED_195',
196: 'CB_PERF_SEL_RESERVED_196',
197: 'CB_PERF_SEL_RESERVED_197',
198: 'CB_PERF_SEL_RESERVED_198',
199: 'CB_PERF_SEL_RESERVED_199',
200: 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED',
201: 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED',
202: 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED',
203: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST',
204: 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT',
205: 'CB_PERF_SEL_RESERVED_205',
206: 'CB_PERF_SEL_RESERVED_206',
207: 'CB_PERF_SEL_RESERVED_207',
208: 'CB_PERF_SEL_RESERVED_208',
209: 'CB_PERF_SEL_RESERVED_209',
210: 'CB_PERF_SEL_RESERVED_210',
211: 'CB_PERF_SEL_RESERVED_211',
212: 'CB_PERF_SEL_RESERVED_212',
213: 'CB_PERF_SEL_RESERVED_213',
214: 'CB_PERF_SEL_RESERVED_214',
215: 'CB_PERF_SEL_RESERVED_215',
216: 'CB_PERF_SEL_RESERVED_216',
217: 'CB_PERF_SEL_RESERVED_217',
218: 'CB_PERF_SEL_RESERVED_218',
219: 'CB_PERF_SEL_RESERVED_219',
220: 'CB_PERF_SEL_RESERVED_220',
221: 'CB_PERF_SEL_RESERVED_221',
222: 'CB_PERF_SEL_RESERVED_222',
223: 'CB_PERF_SEL_RESERVED_223',
224: 'CB_PERF_SEL_RESERVED_224',
225: 'CB_PERF_SEL_RESERVED_225',
226: 'CB_PERF_SEL_RESERVED_226',
227: 'CB_PERF_SEL_RESERVED_227',
228: 'CB_PERF_SEL_RESERVED_228',
229: 'CB_PERF_SEL_RESERVED_229',
230: 'CB_PERF_SEL_RESERVED_230',
231: 'CB_PERF_SEL_RESERVED_231',
232: 'CB_PERF_SEL_RESERVED_232',
233: 'CB_PERF_SEL_RESERVED_233',
234: 'CB_PERF_SEL_RESERVED_234',
235: 'CB_PERF_SEL_RESERVED_235',
236: 'CB_PERF_SEL_RESERVED_236',
237: 'CB_PERF_SEL_RESERVED_237',
238: 'CB_PERF_SEL_RESERVED_238',
239: 'CB_PERF_SEL_RESERVED_239',
240: 'CB_PERF_SEL_RESERVED_240',
241: 'CB_PERF_SEL_RESERVED_241',
242: 'CB_PERF_SEL_RESERVED_242',
243: 'CB_PERF_SEL_RESERVED_243',
244: 'CB_PERF_SEL_RESERVED_244',
245: 'CB_PERF_SEL_RESERVED_245',
246: 'CB_PERF_SEL_RESERVED_246',
247: 'CB_PERF_SEL_RESERVED_247',
248: 'CB_PERF_SEL_RESERVED_248',
249: 'CB_PERF_SEL_RESERVED_249',
250: 'CB_PERF_SEL_EVENT',
251: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS',
252: 'CB_PERF_SEL_EVENT_CONTEXT_DONE',
253: 'CB_PERF_SEL_EVENT_CACHE_FLUSH',
254: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT',
255: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT',
256: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS',
257: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META',
258: 'CB_PERF_SEL_CC_SURFACE_SYNC',
259: 'CB_PERF_SEL_RESERVED_259',
260: 'CB_PERF_SEL_RESERVED_260',
261: 'CB_PERF_SEL_RESERVED_261',
262: 'CB_PERF_SEL_RESERVED_262',
263: 'CB_PERF_SEL_RESERVED_263',
264: 'CB_PERF_SEL_RESERVED_264',
265: 'CB_PERF_SEL_RESERVED_265',
266: 'CB_PERF_SEL_RESERVED_266',
267: 'CB_PERF_SEL_RESERVED_267',
268: 'CB_PERF_SEL_RESERVED_268',
269: 'CB_PERF_SEL_RESERVED_269',
270: 'CB_PERF_SEL_RESERVED_270',
271: 'CB_PERF_SEL_RESERVED_271',
272: 'CB_PERF_SEL_RESERVED_272',
273: 'CB_PERF_SEL_RESERVED_273',
274: 'CB_PERF_SEL_RESERVED_274',
275: 'CB_PERF_SEL_RESERVED_275',
276: 'CB_PERF_SEL_RESERVED_276',
277: 'CB_PERF_SEL_RESERVED_277',
278: 'CB_PERF_SEL_RESERVED_278',
279: 'CB_PERF_SEL_RESERVED_279',
280: 'CB_PERF_SEL_RESERVED_280',
281: 'CB_PERF_SEL_RESERVED_281',
282: 'CB_PERF_SEL_RESERVED_282',
283: 'CB_PERF_SEL_RESERVED_283',
284: 'CB_PERF_SEL_RESERVED_284',
285: 'CB_PERF_SEL_RESERVED_285',
286: 'CB_PERF_SEL_RESERVED_286',
287: 'CB_PERF_SEL_RESERVED_287',
288: 'CB_PERF_SEL_RESERVED_288',
289: 'CB_PERF_SEL_RESERVED_289',
290: 'CB_PERF_SEL_RESERVED_290',
291: 'CB_PERF_SEL_RESERVED_291',
292: 'CB_PERF_SEL_RESERVED_292',
293: 'CB_PERF_SEL_RESERVED_293',
294: 'CB_PERF_SEL_RESERVED_294',
295: 'CB_PERF_SEL_RESERVED_295',
296: 'CB_PERF_SEL_RESERVED_296',
297: 'CB_PERF_SEL_RESERVED_297',
298: 'CB_PERF_SEL_RESERVED_298',
299: 'CB_PERF_SEL_RESERVED_299',
300: 'CB_PERF_SEL_NACK_CC_READ',
301: 'CB_PERF_SEL_NACK_CC_WRITE',
302: 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT',
303: 'CB_PERF_SEL_RESERVED_303',
304: 'CB_PERF_SEL_RESERVED_304',
305: 'CB_PERF_SEL_RESERVED_305',
306: 'CB_PERF_SEL_RESERVED_306',
307: 'CB_PERF_SEL_RESERVED_307',
308: 'CB_PERF_SEL_RESERVED_308',
309: 'CB_PERF_SEL_RESERVED_309',
310: 'CB_PERF_SEL_RESERVED_310',
311: 'CB_PERF_SEL_RESERVED_311',
312: 'CB_PERF_SEL_RESERVED_312',
313: 'CB_PERF_SEL_RESERVED_313',
314: 'CB_PERF_SEL_RESERVED_314',
315: 'CB_PERF_SEL_RESERVED_315',
316: 'CB_PERF_SEL_RESERVED_316',
317: 'CB_PERF_SEL_RESERVED_317',
318: 'CB_PERF_SEL_RESERVED_318',
319: 'CB_PERF_SEL_RESERVED_319',
320: 'CB_PERF_SEL_RESERVED_320',
321: 'CB_PERF_SEL_RESERVED_321',
322: 'CB_PERF_SEL_RESERVED_322',
323: 'CB_PERF_SEL_RESERVED_323',
324: 'CB_PERF_SEL_RESERVED_324',
325: 'CB_PERF_SEL_RESERVED_325',
326: 'CB_PERF_SEL_RESERVED_326',
327: 'CB_PERF_SEL_RESERVED_327',
328: 'CB_PERF_SEL_RESERVED_328',
329: 'CB_PERF_SEL_RESERVED_329',
330: 'CB_PERF_SEL_RESERVED_330',
331: 'CB_PERF_SEL_RESERVED_331',
332: 'CB_PERF_SEL_RESERVED_332',
333: 'CB_PERF_SEL_RESERVED_333',
334: 'CB_PERF_SEL_RESERVED_334',
335: 'CB_PERF_SEL_RESERVED_335',
336: 'CB_PERF_SEL_RESERVED_336',
337: 'CB_PERF_SEL_RESERVED_337',
338: 'CB_PERF_SEL_RESERVED_338',
339: 'CB_PERF_SEL_RESERVED_339',
340: 'CB_PERF_SEL_RESERVED_340',
341: 'CB_PERF_SEL_RESERVED_341',
342: 'CB_PERF_SEL_RESERVED_342',
343: 'CB_PERF_SEL_RESERVED_343',
344: 'CB_PERF_SEL_RESERVED_344',
345: 'CB_PERF_SEL_RESERVED_345',
346: 'CB_PERF_SEL_RESERVED_346',
347: 'CB_PERF_SEL_RESERVED_347',
348: 'CB_PERF_SEL_RESERVED_348',
349: 'CB_PERF_SEL_RESERVED_349',
350: 'CB_PERF_SEL_RESERVED_350',
351: 'CB_PERF_SEL_RESERVED_351',
352: 'CB_PERF_SEL_RESERVED_352',
353: 'CB_PERF_SEL_RESERVED_353',
354: 'CB_PERF_SEL_RESERVED_354',
355: 'CB_PERF_SEL_RESERVED_355',
356: 'CB_PERF_SEL_RESERVED_356',
357: 'CB_PERF_SEL_RESERVED_357',
358: 'CB_PERF_SEL_RESERVED_358',
359: 'CB_PERF_SEL_RESERVED_359',
360: 'CB_PERF_SEL_RESERVED_360',
361: 'CB_PERF_SEL_RESERVED_361',
362: 'CB_PERF_SEL_RESERVED_362',
363: 'CB_PERF_SEL_RESERVED_363',
364: 'CB_PERF_SEL_RESERVED_364',
365: 'CB_PERF_SEL_RESERVED_365',
366: 'CB_PERF_SEL_RESERVED_366',
367: 'CB_PERF_SEL_RESERVED_367',
368: 'CB_PERF_SEL_RESERVED_368',
369: 'CB_PERF_SEL_RESERVED_369',
370: 'CB_PERF_SEL_RESERVED_370',
371: 'CB_PERF_SEL_RESERVED_371',
372: 'CB_PERF_SEL_RESERVED_372',
373: 'CB_PERF_SEL_RESERVED_373',
374: 'CB_PERF_SEL_RESERVED_374',
375: 'CB_PERF_SEL_RESERVED_375',
376: 'CB_PERF_SEL_RESERVED_376',
377: 'CB_PERF_SEL_RESERVED_377',
378: 'CB_PERF_SEL_RESERVED_378',
379: 'CB_PERF_SEL_RESERVED_379',
380: 'CB_PERF_SEL_RESERVED_380',
381: 'CB_PERF_SEL_RESERVED_381',
382: 'CB_PERF_SEL_RESERVED_382',
383: 'CB_PERF_SEL_RESERVED_383',
384: 'CB_PERF_SEL_RESERVED_384',
385: 'CB_PERF_SEL_RESERVED_385',
386: 'CB_PERF_SEL_RESERVED_386',
387: 'CB_PERF_SEL_RESERVED_387',
388: 'CB_PERF_SEL_RESERVED_388',
389: 'CB_PERF_SEL_RESERVED_389',
390: 'CB_PERF_SEL_RESERVED_390',
391: 'CB_PERF_SEL_RESERVED_391',
392: 'CB_PERF_SEL_RESERVED_392',
393: 'CB_PERF_SEL_RESERVED_393',
394: 'CB_PERF_SEL_RESERVED_394',
395: 'CB_PERF_SEL_RESERVED_395',
396: 'CB_PERF_SEL_RESERVED_396',
397: 'CB_PERF_SEL_RESERVED_397',
398: 'CB_PERF_SEL_RESERVED_398',
399: 'CB_PERF_SEL_RESERVED_399',
400: 'CB_PERF_SEL_RESERVED_400',
401: 'CB_PERF_SEL_RESERVED_401',
402: 'CB_PERF_SEL_RESERVED_402',
403: 'CB_PERF_SEL_RESERVED_403',
404: 'CB_PERF_SEL_RESERVED_404',
405: 'CB_PERF_SEL_RESERVED_405',
406: 'CB_PERF_SEL_RESERVED_406',
407: 'CB_PERF_SEL_RESERVED_407',
408: 'CB_PERF_SEL_RESERVED_408',
409: 'CB_PERF_SEL_RESERVED_409',
410: 'CB_PERF_SEL_RESERVED_410',
411: 'CB_PERF_SEL_RESERVED_411',
412: 'CB_PERF_SEL_RESERVED_412',
413: 'CB_PERF_SEL_RESERVED_413',
414: 'CB_PERF_SEL_RESERVED_414',
415: 'CB_PERF_SEL_RESERVED_415',
416: 'CB_PERF_SEL_RESERVED_416',
417: 'CB_PERF_SEL_RESERVED_417',
418: 'CB_PERF_SEL_RESERVED_418',
419: 'CB_PERF_SEL_RESERVED_419',
420: 'CB_PERF_SEL_RESERVED_420',
421: 'CB_PERF_SEL_RESERVED_421',
422: 'CB_PERF_SEL_RESERVED_422',
423: 'CB_PERF_SEL_RESERVED_423',
424: 'CB_PERF_SEL_RESERVED_424',
425: 'CB_PERF_SEL_RESERVED_425',
426: 'CB_PERF_SEL_RESERVED_426',
427: 'CB_PERF_SEL_RESERVED_427',
428: 'CB_PERF_SEL_RESERVED_428',
429: 'CB_PERF_SEL_RESERVED_429',
430: 'CB_PERF_SEL_RESERVED_430',
431: 'CB_PERF_SEL_RESERVED_431',
432: 'CB_PERF_SEL_RESERVED_432',
433: 'CB_PERF_SEL_RESERVED_433',
434: 'CB_PERF_SEL_RESERVED_434',
435: 'CB_PERF_SEL_RESERVED_435',
436: 'CB_PERF_SEL_RESERVED_436',
437: 'CB_PERF_SEL_RESERVED_437',
438: 'CB_PERF_SEL_RESERVED_438',
439: 'CB_PERF_SEL_RESERVED_439',
440: 'CB_PERF_SEL_RESERVED_440',
441: 'CB_PERF_SEL_RESERVED_441',
442: 'CB_PERF_SEL_RESERVED_442',
443: 'CB_PERF_SEL_RESERVED_443',
444: 'CB_PERF_SEL_RESERVED_444',
445: 'CB_PERF_SEL_RESERVED_445',
446: 'CB_PERF_SEL_RESERVED_446',
447: 'CB_PERF_SEL_RESERVED_447',
448: 'CB_PERF_SEL_RESERVED_448',
449: 'CB_PERF_SEL_RESERVED_449',
450: 'CB_PERF_SEL_RESERVED_450',
451: 'CB_PERF_SEL_RESERVED_451',
452: 'CB_PERF_SEL_RESERVED_452',
453: 'CB_PERF_SEL_RESERVED_453',
454: 'CB_PERF_SEL_RESERVED_454',
455: 'CB_PERF_SEL_RESERVED_455',
456: 'CB_PERF_SEL_RESERVED_456',
457: 'CB_PERF_SEL_RESERVED_457',
458: 'CB_PERF_SEL_RESERVED_458',
459: 'CB_PERF_SEL_RESERVED_459',
460: 'CB_PERF_SEL_RESERVED_460',
461: 'CB_PERF_SEL_RESERVED_461',
462: 'CB_PERF_SEL_RESERVED_462',
463: 'CB_PERF_SEL_RESERVED_463',
464: 'CB_PERF_SEL_RESERVED_464',
465: 'CB_PERF_SEL_RESERVED_465',
}
CB_PERF_SEL_NONE = 0
CB_PERF_SEL_DRAWN_PIXEL = 1
CB_PERF_SEL_DRAWN_QUAD = 2
CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 3
CB_PERF_SEL_DRAWN_TILE = 4
CB_PERF_SEL_FILTER_DRAWN_PIXEL = 5
CB_PERF_SEL_FILTER_DRAWN_QUAD = 6
CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT = 7
CB_PERF_SEL_FILTER_DRAWN_TILE = 8
CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN = 9
CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT = 10
CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN = 11
CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT = 12
CB_PERF_SEL_CC_MC_WRITE_REQUEST = 13
CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 14
CB_PERF_SEL_CC_MC_READ_REQUEST = 15
CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 16
CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 17
CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 18
CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 19
CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 20
CB_PERF_SEL_RESERVED_21 = 21
CB_PERF_SEL_RESERVED_22 = 22
CB_PERF_SEL_RESERVED_23 = 23
CB_PERF_SEL_RESERVED_24 = 24
CB_PERF_SEL_RESERVED_25 = 25
CB_PERF_SEL_RESERVED_26 = 26
CB_PERF_SEL_RESERVED_27 = 27
CB_PERF_SEL_RESERVED_28 = 28
CB_PERF_SEL_RESERVED_29 = 29
CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY = 30
CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB = 31
CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY = 32
CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB = 33
CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY = 34
CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB = 35
CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY = 36
CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB = 37
CB_PERF_SEL_RESERVED_38 = 38
CB_PERF_SEL_RESERVED_39 = 39
CB_PERF_SEL_RESERVED_40 = 40
CB_PERF_SEL_RESERVED_41 = 41
CB_PERF_SEL_RESERVED_42 = 42
CB_PERF_SEL_RESERVED_43 = 43
CB_PERF_SEL_RESERVED_44 = 44
CB_PERF_SEL_RESERVED_45 = 45
CB_PERF_SEL_RESERVED_46 = 46
CB_PERF_SEL_RESERVED_47 = 47
CB_PERF_SEL_RESERVED_48 = 48
CB_PERF_SEL_RESERVED_49 = 49
CB_PERF_SEL_STATIC_CLOCK_EN = 50
CB_PERF_SEL_PERFMON_CLOCK_EN = 51
CB_PERF_SEL_BLEND_CLOCK_EN = 52
CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 53
CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 54
CB_PERF_SEL_GRBM_CLOCK_EN = 55
CB_PERF_SEL_MEMARB_CLOCK_EN = 56
CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 57
CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 58
CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 59
CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 60
CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 61
CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 62
CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 63
CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 64
CB_PERF_SEL_RESERVED_65 = 65
CB_PERF_SEL_RESERVED_66 = 66
CB_PERF_SEL_RESERVED_67 = 67
CB_PERF_SEL_RESERVED_68 = 68
CB_PERF_SEL_RESERVED_69 = 69
CB_PERF_SEL_RESERVED_70 = 70
CB_PERF_SEL_RESERVED_71 = 71
CB_PERF_SEL_RESERVED_72 = 72
CB_PERF_SEL_RESERVED_73 = 73
CB_PERF_SEL_RESERVED_74 = 74
CB_PERF_SEL_RESERVED_75 = 75
CB_PERF_SEL_RESERVED_76 = 76
CB_PERF_SEL_RESERVED_77 = 77
CB_PERF_SEL_RESERVED_78 = 78
CB_PERF_SEL_RESERVED_79 = 79
CB_PERF_SEL_RESERVED_80 = 80
CB_PERF_SEL_RESERVED_81 = 81
CB_PERF_SEL_RESERVED_82 = 82
CB_PERF_SEL_RESERVED_83 = 83
CB_PERF_SEL_RESERVED_84 = 84
CB_PERF_SEL_RESERVED_85 = 85
CB_PERF_SEL_RESERVED_86 = 86
CB_PERF_SEL_RESERVED_87 = 87
CB_PERF_SEL_RESERVED_88 = 88
CB_PERF_SEL_RESERVED_89 = 89
CB_PERF_SEL_RESERVED_90 = 90
CB_PERF_SEL_RESERVED_91 = 91
CB_PERF_SEL_RESERVED_92 = 92
CB_PERF_SEL_RESERVED_93 = 93
CB_PERF_SEL_RESERVED_94 = 94
CB_PERF_SEL_RESERVED_95 = 95
CB_PERF_SEL_RESERVED_96 = 96
CB_PERF_SEL_RESERVED_97 = 97
CB_PERF_SEL_RESERVED_98 = 98
CB_PERF_SEL_RESERVED_99 = 99
CB_PERF_SEL_CC_TAG_HIT = 100
CB_PERF_SEL_CC_CACHE_TAG_MISS = 101
CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 102
CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 103
CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 104
CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 105
CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 106
CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 107
CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 108
CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 109
CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 110
CB_PERF_SEL_CC_CACHE_STALL = 111
CB_PERF_SEL_CC_CACHE_FLUSH = 112
CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 113
CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 114
CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 115
CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 116
CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 117
CB_PERF_SEL_RESERVED_118 = 118
CB_PERF_SEL_RESERVED_119 = 119
CB_PERF_SEL_RESERVED_120 = 120
CB_PERF_SEL_RESERVED_121 = 121
CB_PERF_SEL_RESERVED_122 = 122
CB_PERF_SEL_RESERVED_123 = 123
CB_PERF_SEL_RESERVED_124 = 124
CB_PERF_SEL_RESERVED_125 = 125
CB_PERF_SEL_RESERVED_126 = 126
CB_PERF_SEL_RESERVED_127 = 127
CB_PERF_SEL_RESERVED_128 = 128
CB_PERF_SEL_RESERVED_129 = 129
CB_PERF_SEL_RESERVED_130 = 130
CB_PERF_SEL_RESERVED_131 = 131
CB_PERF_SEL_RESERVED_132 = 132
CB_PERF_SEL_RESERVED_133 = 133
CB_PERF_SEL_RESERVED_134 = 134
CB_PERF_SEL_RESERVED_135 = 135
CB_PERF_SEL_RESERVED_136 = 136
CB_PERF_SEL_RESERVED_137 = 137
CB_PERF_SEL_RESERVED_138 = 138
CB_PERF_SEL_RESERVED_139 = 139
CB_PERF_SEL_RESERVED_140 = 140
CB_PERF_SEL_RESERVED_141 = 141
CB_PERF_SEL_RESERVED_142 = 142
CB_PERF_SEL_RESERVED_143 = 143
CB_PERF_SEL_RESERVED_144 = 144
CB_PERF_SEL_RESERVED_145 = 145
CB_PERF_SEL_RESERVED_146 = 146
CB_PERF_SEL_RESERVED_147 = 147
CB_PERF_SEL_RESERVED_148 = 148
CB_PERF_SEL_RESERVED_149 = 149
CB_PERF_SEL_DCC_CACHE_PERF_HIT = 150
CB_PERF_SEL_DCC_CACHE_TAG_MISS = 151
CB_PERF_SEL_DCC_CACHE_SECTOR_MISS = 152
CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL = 153
CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 154
CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 155
CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 156
CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL = 157
CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL = 158
CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL = 159
CB_PERF_SEL_DCC_CACHE_STALL = 160
CB_PERF_SEL_DCC_CACHE_FLUSH = 161
CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED = 162
CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 163
CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED = 164
CB_PERF_SEL_RESERVED_165 = 165
CB_PERF_SEL_RESERVED_166 = 166
CB_PERF_SEL_RESERVED_167 = 167
CB_PERF_SEL_RESERVED_168 = 168
CB_PERF_SEL_RESERVED_169 = 169
CB_PERF_SEL_RESERVED_170 = 170
CB_PERF_SEL_RESERVED_171 = 171
CB_PERF_SEL_RESERVED_172 = 172
CB_PERF_SEL_RESERVED_173 = 173
CB_PERF_SEL_RESERVED_174 = 174
CB_PERF_SEL_RESERVED_175 = 175
CB_PERF_SEL_RESERVED_176 = 176
CB_PERF_SEL_RESERVED_177 = 177
CB_PERF_SEL_RESERVED_178 = 178
CB_PERF_SEL_RESERVED_179 = 179
CB_PERF_SEL_RESERVED_180 = 180
CB_PERF_SEL_RESERVED_181 = 181
CB_PERF_SEL_RESERVED_182 = 182
CB_PERF_SEL_RESERVED_183 = 183
CB_PERF_SEL_RESERVED_184 = 184
CB_PERF_SEL_RESERVED_185 = 185
CB_PERF_SEL_RESERVED_186 = 186
CB_PERF_SEL_RESERVED_187 = 187
CB_PERF_SEL_RESERVED_188 = 188
CB_PERF_SEL_RESERVED_189 = 189
CB_PERF_SEL_RESERVED_190 = 190
CB_PERF_SEL_RESERVED_191 = 191
CB_PERF_SEL_RESERVED_192 = 192
CB_PERF_SEL_RESERVED_193 = 193
CB_PERF_SEL_RESERVED_194 = 194
CB_PERF_SEL_RESERVED_195 = 195
CB_PERF_SEL_RESERVED_196 = 196
CB_PERF_SEL_RESERVED_197 = 197
CB_PERF_SEL_RESERVED_198 = 198
CB_PERF_SEL_RESERVED_199 = 199
CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 200
CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 201
CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 202
CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 203
CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 204
CB_PERF_SEL_RESERVED_205 = 205
CB_PERF_SEL_RESERVED_206 = 206
CB_PERF_SEL_RESERVED_207 = 207
CB_PERF_SEL_RESERVED_208 = 208
CB_PERF_SEL_RESERVED_209 = 209
CB_PERF_SEL_RESERVED_210 = 210
CB_PERF_SEL_RESERVED_211 = 211
CB_PERF_SEL_RESERVED_212 = 212
CB_PERF_SEL_RESERVED_213 = 213
CB_PERF_SEL_RESERVED_214 = 214
CB_PERF_SEL_RESERVED_215 = 215
CB_PERF_SEL_RESERVED_216 = 216
CB_PERF_SEL_RESERVED_217 = 217
CB_PERF_SEL_RESERVED_218 = 218
CB_PERF_SEL_RESERVED_219 = 219
CB_PERF_SEL_RESERVED_220 = 220
CB_PERF_SEL_RESERVED_221 = 221
CB_PERF_SEL_RESERVED_222 = 222
CB_PERF_SEL_RESERVED_223 = 223
CB_PERF_SEL_RESERVED_224 = 224
CB_PERF_SEL_RESERVED_225 = 225
CB_PERF_SEL_RESERVED_226 = 226
CB_PERF_SEL_RESERVED_227 = 227
CB_PERF_SEL_RESERVED_228 = 228
CB_PERF_SEL_RESERVED_229 = 229
CB_PERF_SEL_RESERVED_230 = 230
CB_PERF_SEL_RESERVED_231 = 231
CB_PERF_SEL_RESERVED_232 = 232
CB_PERF_SEL_RESERVED_233 = 233
CB_PERF_SEL_RESERVED_234 = 234
CB_PERF_SEL_RESERVED_235 = 235
CB_PERF_SEL_RESERVED_236 = 236
CB_PERF_SEL_RESERVED_237 = 237
CB_PERF_SEL_RESERVED_238 = 238
CB_PERF_SEL_RESERVED_239 = 239
CB_PERF_SEL_RESERVED_240 = 240
CB_PERF_SEL_RESERVED_241 = 241
CB_PERF_SEL_RESERVED_242 = 242
CB_PERF_SEL_RESERVED_243 = 243
CB_PERF_SEL_RESERVED_244 = 244
CB_PERF_SEL_RESERVED_245 = 245
CB_PERF_SEL_RESERVED_246 = 246
CB_PERF_SEL_RESERVED_247 = 247
CB_PERF_SEL_RESERVED_248 = 248
CB_PERF_SEL_RESERVED_249 = 249
CB_PERF_SEL_EVENT = 250
CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 251
CB_PERF_SEL_EVENT_CONTEXT_DONE = 252
CB_PERF_SEL_EVENT_CACHE_FLUSH = 253
CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 254
CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 255
CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 256
CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 257
CB_PERF_SEL_CC_SURFACE_SYNC = 258
CB_PERF_SEL_RESERVED_259 = 259
CB_PERF_SEL_RESERVED_260 = 260
CB_PERF_SEL_RESERVED_261 = 261
CB_PERF_SEL_RESERVED_262 = 262
CB_PERF_SEL_RESERVED_263 = 263
CB_PERF_SEL_RESERVED_264 = 264
CB_PERF_SEL_RESERVED_265 = 265
CB_PERF_SEL_RESERVED_266 = 266
CB_PERF_SEL_RESERVED_267 = 267
CB_PERF_SEL_RESERVED_268 = 268
CB_PERF_SEL_RESERVED_269 = 269
CB_PERF_SEL_RESERVED_270 = 270
CB_PERF_SEL_RESERVED_271 = 271
CB_PERF_SEL_RESERVED_272 = 272
CB_PERF_SEL_RESERVED_273 = 273
CB_PERF_SEL_RESERVED_274 = 274
CB_PERF_SEL_RESERVED_275 = 275
CB_PERF_SEL_RESERVED_276 = 276
CB_PERF_SEL_RESERVED_277 = 277
CB_PERF_SEL_RESERVED_278 = 278
CB_PERF_SEL_RESERVED_279 = 279
CB_PERF_SEL_RESERVED_280 = 280
CB_PERF_SEL_RESERVED_281 = 281
CB_PERF_SEL_RESERVED_282 = 282
CB_PERF_SEL_RESERVED_283 = 283
CB_PERF_SEL_RESERVED_284 = 284
CB_PERF_SEL_RESERVED_285 = 285
CB_PERF_SEL_RESERVED_286 = 286
CB_PERF_SEL_RESERVED_287 = 287
CB_PERF_SEL_RESERVED_288 = 288
CB_PERF_SEL_RESERVED_289 = 289
CB_PERF_SEL_RESERVED_290 = 290
CB_PERF_SEL_RESERVED_291 = 291
CB_PERF_SEL_RESERVED_292 = 292
CB_PERF_SEL_RESERVED_293 = 293
CB_PERF_SEL_RESERVED_294 = 294
CB_PERF_SEL_RESERVED_295 = 295
CB_PERF_SEL_RESERVED_296 = 296
CB_PERF_SEL_RESERVED_297 = 297
CB_PERF_SEL_RESERVED_298 = 298
CB_PERF_SEL_RESERVED_299 = 299
CB_PERF_SEL_NACK_CC_READ = 300
CB_PERF_SEL_NACK_CC_WRITE = 301
CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 302
CB_PERF_SEL_RESERVED_303 = 303
CB_PERF_SEL_RESERVED_304 = 304
CB_PERF_SEL_RESERVED_305 = 305
CB_PERF_SEL_RESERVED_306 = 306
CB_PERF_SEL_RESERVED_307 = 307
CB_PERF_SEL_RESERVED_308 = 308
CB_PERF_SEL_RESERVED_309 = 309
CB_PERF_SEL_RESERVED_310 = 310
CB_PERF_SEL_RESERVED_311 = 311
CB_PERF_SEL_RESERVED_312 = 312
CB_PERF_SEL_RESERVED_313 = 313
CB_PERF_SEL_RESERVED_314 = 314
CB_PERF_SEL_RESERVED_315 = 315
CB_PERF_SEL_RESERVED_316 = 316
CB_PERF_SEL_RESERVED_317 = 317
CB_PERF_SEL_RESERVED_318 = 318
CB_PERF_SEL_RESERVED_319 = 319
CB_PERF_SEL_RESERVED_320 = 320
CB_PERF_SEL_RESERVED_321 = 321
CB_PERF_SEL_RESERVED_322 = 322
CB_PERF_SEL_RESERVED_323 = 323
CB_PERF_SEL_RESERVED_324 = 324
CB_PERF_SEL_RESERVED_325 = 325
CB_PERF_SEL_RESERVED_326 = 326
CB_PERF_SEL_RESERVED_327 = 327
CB_PERF_SEL_RESERVED_328 = 328
CB_PERF_SEL_RESERVED_329 = 329
CB_PERF_SEL_RESERVED_330 = 330
CB_PERF_SEL_RESERVED_331 = 331
CB_PERF_SEL_RESERVED_332 = 332
CB_PERF_SEL_RESERVED_333 = 333
CB_PERF_SEL_RESERVED_334 = 334
CB_PERF_SEL_RESERVED_335 = 335
CB_PERF_SEL_RESERVED_336 = 336
CB_PERF_SEL_RESERVED_337 = 337
CB_PERF_SEL_RESERVED_338 = 338
CB_PERF_SEL_RESERVED_339 = 339
CB_PERF_SEL_RESERVED_340 = 340
CB_PERF_SEL_RESERVED_341 = 341
CB_PERF_SEL_RESERVED_342 = 342
CB_PERF_SEL_RESERVED_343 = 343
CB_PERF_SEL_RESERVED_344 = 344
CB_PERF_SEL_RESERVED_345 = 345
CB_PERF_SEL_RESERVED_346 = 346
CB_PERF_SEL_RESERVED_347 = 347
CB_PERF_SEL_RESERVED_348 = 348
CB_PERF_SEL_RESERVED_349 = 349
CB_PERF_SEL_RESERVED_350 = 350
CB_PERF_SEL_RESERVED_351 = 351
CB_PERF_SEL_RESERVED_352 = 352
CB_PERF_SEL_RESERVED_353 = 353
CB_PERF_SEL_RESERVED_354 = 354
CB_PERF_SEL_RESERVED_355 = 355
CB_PERF_SEL_RESERVED_356 = 356
CB_PERF_SEL_RESERVED_357 = 357
CB_PERF_SEL_RESERVED_358 = 358
CB_PERF_SEL_RESERVED_359 = 359
CB_PERF_SEL_RESERVED_360 = 360
CB_PERF_SEL_RESERVED_361 = 361
CB_PERF_SEL_RESERVED_362 = 362
CB_PERF_SEL_RESERVED_363 = 363
CB_PERF_SEL_RESERVED_364 = 364
CB_PERF_SEL_RESERVED_365 = 365
CB_PERF_SEL_RESERVED_366 = 366
CB_PERF_SEL_RESERVED_367 = 367
CB_PERF_SEL_RESERVED_368 = 368
CB_PERF_SEL_RESERVED_369 = 369
CB_PERF_SEL_RESERVED_370 = 370
CB_PERF_SEL_RESERVED_371 = 371
CB_PERF_SEL_RESERVED_372 = 372
CB_PERF_SEL_RESERVED_373 = 373
CB_PERF_SEL_RESERVED_374 = 374
CB_PERF_SEL_RESERVED_375 = 375
CB_PERF_SEL_RESERVED_376 = 376
CB_PERF_SEL_RESERVED_377 = 377
CB_PERF_SEL_RESERVED_378 = 378
CB_PERF_SEL_RESERVED_379 = 379
CB_PERF_SEL_RESERVED_380 = 380
CB_PERF_SEL_RESERVED_381 = 381
CB_PERF_SEL_RESERVED_382 = 382
CB_PERF_SEL_RESERVED_383 = 383
CB_PERF_SEL_RESERVED_384 = 384
CB_PERF_SEL_RESERVED_385 = 385
CB_PERF_SEL_RESERVED_386 = 386
CB_PERF_SEL_RESERVED_387 = 387
CB_PERF_SEL_RESERVED_388 = 388
CB_PERF_SEL_RESERVED_389 = 389
CB_PERF_SEL_RESERVED_390 = 390
CB_PERF_SEL_RESERVED_391 = 391
CB_PERF_SEL_RESERVED_392 = 392
CB_PERF_SEL_RESERVED_393 = 393
CB_PERF_SEL_RESERVED_394 = 394
CB_PERF_SEL_RESERVED_395 = 395
CB_PERF_SEL_RESERVED_396 = 396
CB_PERF_SEL_RESERVED_397 = 397
CB_PERF_SEL_RESERVED_398 = 398
CB_PERF_SEL_RESERVED_399 = 399
CB_PERF_SEL_RESERVED_400 = 400
CB_PERF_SEL_RESERVED_401 = 401
CB_PERF_SEL_RESERVED_402 = 402
CB_PERF_SEL_RESERVED_403 = 403
CB_PERF_SEL_RESERVED_404 = 404
CB_PERF_SEL_RESERVED_405 = 405
CB_PERF_SEL_RESERVED_406 = 406
CB_PERF_SEL_RESERVED_407 = 407
CB_PERF_SEL_RESERVED_408 = 408
CB_PERF_SEL_RESERVED_409 = 409
CB_PERF_SEL_RESERVED_410 = 410
CB_PERF_SEL_RESERVED_411 = 411
CB_PERF_SEL_RESERVED_412 = 412
CB_PERF_SEL_RESERVED_413 = 413
CB_PERF_SEL_RESERVED_414 = 414
CB_PERF_SEL_RESERVED_415 = 415
CB_PERF_SEL_RESERVED_416 = 416
CB_PERF_SEL_RESERVED_417 = 417
CB_PERF_SEL_RESERVED_418 = 418
CB_PERF_SEL_RESERVED_419 = 419
CB_PERF_SEL_RESERVED_420 = 420
CB_PERF_SEL_RESERVED_421 = 421
CB_PERF_SEL_RESERVED_422 = 422
CB_PERF_SEL_RESERVED_423 = 423
CB_PERF_SEL_RESERVED_424 = 424
CB_PERF_SEL_RESERVED_425 = 425
CB_PERF_SEL_RESERVED_426 = 426
CB_PERF_SEL_RESERVED_427 = 427
CB_PERF_SEL_RESERVED_428 = 428
CB_PERF_SEL_RESERVED_429 = 429
CB_PERF_SEL_RESERVED_430 = 430
CB_PERF_SEL_RESERVED_431 = 431
CB_PERF_SEL_RESERVED_432 = 432
CB_PERF_SEL_RESERVED_433 = 433
CB_PERF_SEL_RESERVED_434 = 434
CB_PERF_SEL_RESERVED_435 = 435
CB_PERF_SEL_RESERVED_436 = 436
CB_PERF_SEL_RESERVED_437 = 437
CB_PERF_SEL_RESERVED_438 = 438
CB_PERF_SEL_RESERVED_439 = 439
CB_PERF_SEL_RESERVED_440 = 440
CB_PERF_SEL_RESERVED_441 = 441
CB_PERF_SEL_RESERVED_442 = 442
CB_PERF_SEL_RESERVED_443 = 443
CB_PERF_SEL_RESERVED_444 = 444
CB_PERF_SEL_RESERVED_445 = 445
CB_PERF_SEL_RESERVED_446 = 446
CB_PERF_SEL_RESERVED_447 = 447
CB_PERF_SEL_RESERVED_448 = 448
CB_PERF_SEL_RESERVED_449 = 449
CB_PERF_SEL_RESERVED_450 = 450
CB_PERF_SEL_RESERVED_451 = 451
CB_PERF_SEL_RESERVED_452 = 452
CB_PERF_SEL_RESERVED_453 = 453
CB_PERF_SEL_RESERVED_454 = 454
CB_PERF_SEL_RESERVED_455 = 455
CB_PERF_SEL_RESERVED_456 = 456
CB_PERF_SEL_RESERVED_457 = 457
CB_PERF_SEL_RESERVED_458 = 458
CB_PERF_SEL_RESERVED_459 = 459
CB_PERF_SEL_RESERVED_460 = 460
CB_PERF_SEL_RESERVED_461 = 461
CB_PERF_SEL_RESERVED_462 = 462
CB_PERF_SEL_RESERVED_463 = 463
CB_PERF_SEL_RESERVED_464 = 464
CB_PERF_SEL_RESERVED_465 = 465
CBPerfSel = ctypes.c_uint32 # enum
# values for enumeration 'CBRamList'
CBRamList__enumvalues = {
0: 'CB_DCG_CCC_CAS_TAG_ARRAY',
1: 'CB_DCG_CCC_CAS_FRAG_PTR',
2: 'CB_DCG_CCC_CAS_COLOR_PTR',
3: 'CB_DCG_CCC_CAS_SURF_PARAM',
4: 'CB_DCG_CCC_CAS_KEYID',
5: 'CB_DCG_BACKEND_RDLAT_FIFO',
6: 'CB_DCG_FRONTEND_RDLAT_FIFO',
7: 'CB_DCG_SRC_FIFO',
8: 'CB_DCG_COLOR_STORE',
9: 'CB_DCG_COLOR_STORE_DIRTY_BYTE',
10: 'CB_DCG_FMASK_CACHE_STORE',
11: 'CB_DCG_READ_SKID_FIFO',
12: 'CB_DCG_QUAD_PTR_FIFO',
13: 'CB_DCG_OUTPUT_FIFO',
14: 'CB_DCG_DCC_CACHE',
15: 'CB_DCG_DCC_DIRTY_BITS',
16: 'CB_DCG_QBLOCK_ALLOC',
}
CB_DCG_CCC_CAS_TAG_ARRAY = 0
CB_DCG_CCC_CAS_FRAG_PTR = 1
CB_DCG_CCC_CAS_COLOR_PTR = 2
CB_DCG_CCC_CAS_SURF_PARAM = 3
CB_DCG_CCC_CAS_KEYID = 4
CB_DCG_BACKEND_RDLAT_FIFO = 5
CB_DCG_FRONTEND_RDLAT_FIFO = 6
CB_DCG_SRC_FIFO = 7
CB_DCG_COLOR_STORE = 8
CB_DCG_COLOR_STORE_DIRTY_BYTE = 9
CB_DCG_FMASK_CACHE_STORE = 10
CB_DCG_READ_SKID_FIFO = 11
CB_DCG_QUAD_PTR_FIFO = 12
CB_DCG_OUTPUT_FIFO = 13
CB_DCG_DCC_CACHE = 14
CB_DCG_DCC_DIRTY_BITS = 15
CB_DCG_QBLOCK_ALLOC = 16
CBRamList = ctypes.c_uint32 # enum
# values for enumeration 'CmaskCode'
CmaskCode__enumvalues = {
0: 'CMASK_CLR00_F0',
1: 'CMASK_CLR00_F1',
2: 'CMASK_CLR00_F2',
3: 'CMASK_CLR00_FX',
4: 'CMASK_CLR01_F0',
5: 'CMASK_CLR01_F1',
6: 'CMASK_CLR01_F2',
7: 'CMASK_CLR01_FX',
8: 'CMASK_CLR10_F0',
9: 'CMASK_CLR10_F1',
10: 'CMASK_CLR10_F2',
11: 'CMASK_CLR10_FX',
12: 'CMASK_CLR11_F0',
13: 'CMASK_CLR11_F1',
14: 'CMASK_CLR11_F2',
15: 'CMASK_CLR11_FX',
}
CMASK_CLR00_F0 = 0
CMASK_CLR00_F1 = 1
CMASK_CLR00_F2 = 2
CMASK_CLR00_FX = 3
CMASK_CLR01_F0 = 4
CMASK_CLR01_F1 = 5
CMASK_CLR01_F2 = 6
CMASK_CLR01_FX = 7
CMASK_CLR10_F0 = 8
CMASK_CLR10_F1 = 9
CMASK_CLR10_F2 = 10
CMASK_CLR10_FX = 11
CMASK_CLR11_F0 = 12
CMASK_CLR11_F1 = 13
CMASK_CLR11_F2 = 14
CMASK_CLR11_FX = 15
CmaskCode = ctypes.c_uint32 # enum
# values for enumeration 'CombFunc'
CombFunc__enumvalues = {
0: 'COMB_DST_PLUS_SRC',
1: 'COMB_SRC_MINUS_DST',
2: 'COMB_MIN_DST_SRC',
3: 'COMB_MAX_DST_SRC',
4: 'COMB_DST_MINUS_SRC',
}
COMB_DST_PLUS_SRC = 0
COMB_SRC_MINUS_DST = 1
COMB_MIN_DST_SRC = 2
COMB_MAX_DST_SRC = 3
COMB_DST_MINUS_SRC = 4
CombFunc = ctypes.c_uint32 # enum
# values for enumeration 'MemArbMode'
MemArbMode__enumvalues = {
0: 'MEM_ARB_MODE_FIXED',
1: 'MEM_ARB_MODE_AGE',
2: 'MEM_ARB_MODE_WEIGHT',
3: 'MEM_ARB_MODE_BOTH',
}
MEM_ARB_MODE_FIXED = 0
MEM_ARB_MODE_AGE = 1
MEM_ARB_MODE_WEIGHT = 2
MEM_ARB_MODE_BOTH = 3
MemArbMode = ctypes.c_uint32 # enum
# values for enumeration 'SourceFormat'
SourceFormat__enumvalues = {
0: 'EXPORT_4C_32BPC',
1: 'EXPORT_4C_16BPC',
2: 'EXPORT_2C_32BPC_GR',
3: 'EXPORT_2C_32BPC_AR',
}
EXPORT_4C_32BPC = 0
EXPORT_4C_16BPC = 1
EXPORT_2C_32BPC_GR = 2
EXPORT_2C_32BPC_AR = 3
SourceFormat = ctypes.c_uint32 # enum
# values for enumeration 'BinEventCntl'
BinEventCntl__enumvalues = {
0: 'BINNER_BREAK_BATCH',
1: 'BINNER_PIPELINE',
2: 'BINNER_DROP',
3: 'BINNER_PIPELINE_BREAK',
}
BINNER_BREAK_BATCH = 0
BINNER_PIPELINE = 1
BINNER_DROP = 2
BINNER_PIPELINE_BREAK = 3
BinEventCntl = ctypes.c_uint32 # enum
# values for enumeration 'BinMapMode'
BinMapMode__enumvalues = {
0: 'BIN_MAP_MODE_NONE',
1: 'BIN_MAP_MODE_RTA_INDEX',
2: 'BIN_MAP_MODE_POPS',
}
BIN_MAP_MODE_NONE = 0
BIN_MAP_MODE_RTA_INDEX = 1
BIN_MAP_MODE_POPS = 2
BinMapMode = ctypes.c_uint32 # enum
# values for enumeration 'BinSizeExtend'
BinSizeExtend__enumvalues = {
0: 'BIN_SIZE_32_PIXELS',
1: 'BIN_SIZE_64_PIXELS',
2: 'BIN_SIZE_128_PIXELS',
3: 'BIN_SIZE_256_PIXELS',
4: 'BIN_SIZE_512_PIXELS',
}
BIN_SIZE_32_PIXELS = 0
BIN_SIZE_64_PIXELS = 1
BIN_SIZE_128_PIXELS = 2
BIN_SIZE_256_PIXELS = 3
BIN_SIZE_512_PIXELS = 4
BinSizeExtend = ctypes.c_uint32 # enum
# values for enumeration 'BinningMode'
BinningMode__enumvalues = {
0: 'BINNING_ALLOWED',
1: 'FORCE_BINNING_ON',
2: 'DISABLE_BINNING_USE_NEW_SC',
3: 'DISABLE_BINNING_USE_LEGACY_SC',
}
BINNING_ALLOWED = 0
FORCE_BINNING_ON = 1
DISABLE_BINNING_USE_NEW_SC = 2
DISABLE_BINNING_USE_LEGACY_SC = 3
BinningMode = ctypes.c_uint32 # enum
# values for enumeration 'CovToShaderSel'
CovToShaderSel__enumvalues = {
0: 'INPUT_COVERAGE',
1: 'INPUT_INNER_COVERAGE',
2: 'INPUT_DEPTH_COVERAGE',
3: 'RAW',
}
INPUT_COVERAGE = 0
INPUT_INNER_COVERAGE = 1
INPUT_DEPTH_COVERAGE = 2
RAW = 3
CovToShaderSel = ctypes.c_uint32 # enum
# values for enumeration 'PkrMap'
PkrMap__enumvalues = {
0: 'RASTER_CONFIG_PKR_MAP_0',
1: 'RASTER_CONFIG_PKR_MAP_1',
2: 'RASTER_CONFIG_PKR_MAP_2',
3: 'RASTER_CONFIG_PKR_MAP_3',
}
RASTER_CONFIG_PKR_MAP_0 = 0
RASTER_CONFIG_PKR_MAP_1 = 1
RASTER_CONFIG_PKR_MAP_2 = 2
RASTER_CONFIG_PKR_MAP_3 = 3
PkrMap = ctypes.c_uint32 # enum
# values for enumeration 'PkrXsel'
PkrXsel__enumvalues = {
0: 'RASTER_CONFIG_PKR_XSEL_0',
1: 'RASTER_CONFIG_PKR_XSEL_1',
2: 'RASTER_CONFIG_PKR_XSEL_2',
3: 'RASTER_CONFIG_PKR_XSEL_3',
}
RASTER_CONFIG_PKR_XSEL_0 = 0
RASTER_CONFIG_PKR_XSEL_1 = 1
RASTER_CONFIG_PKR_XSEL_2 = 2
RASTER_CONFIG_PKR_XSEL_3 = 3
PkrXsel = ctypes.c_uint32 # enum
# values for enumeration 'PkrXsel2'
PkrXsel2__enumvalues = {
0: 'RASTER_CONFIG_PKR_XSEL2_0',
1: 'RASTER_CONFIG_PKR_XSEL2_1',
2: 'RASTER_CONFIG_PKR_XSEL2_2',
3: 'RASTER_CONFIG_PKR_XSEL2_3',
}
RASTER_CONFIG_PKR_XSEL2_0 = 0
RASTER_CONFIG_PKR_XSEL2_1 = 1
RASTER_CONFIG_PKR_XSEL2_2 = 2
RASTER_CONFIG_PKR_XSEL2_3 = 3
PkrXsel2 = ctypes.c_uint32 # enum
# values for enumeration 'PkrYsel'
PkrYsel__enumvalues = {
0: 'RASTER_CONFIG_PKR_YSEL_0',
1: 'RASTER_CONFIG_PKR_YSEL_1',
2: 'RASTER_CONFIG_PKR_YSEL_2',
3: 'RASTER_CONFIG_PKR_YSEL_3',
}
RASTER_CONFIG_PKR_YSEL_0 = 0
RASTER_CONFIG_PKR_YSEL_1 = 1
RASTER_CONFIG_PKR_YSEL_2 = 2
RASTER_CONFIG_PKR_YSEL_3 = 3
PkrYsel = ctypes.c_uint32 # enum
# values for enumeration 'RbMap'
RbMap__enumvalues = {
0: 'RASTER_CONFIG_RB_MAP_0',
1: 'RASTER_CONFIG_RB_MAP_1',
2: 'RASTER_CONFIG_RB_MAP_2',
3: 'RASTER_CONFIG_RB_MAP_3',
}
RASTER_CONFIG_RB_MAP_0 = 0
RASTER_CONFIG_RB_MAP_1 = 1
RASTER_CONFIG_RB_MAP_2 = 2
RASTER_CONFIG_RB_MAP_3 = 3
RbMap = ctypes.c_uint32 # enum
# values for enumeration 'RbXsel'
RbXsel__enumvalues = {
0: 'RASTER_CONFIG_RB_XSEL_0',
1: 'RASTER_CONFIG_RB_XSEL_1',
}
RASTER_CONFIG_RB_XSEL_0 = 0
RASTER_CONFIG_RB_XSEL_1 = 1
RbXsel = ctypes.c_uint32 # enum
# values for enumeration 'RbXsel2'
RbXsel2__enumvalues = {
0: 'RASTER_CONFIG_RB_XSEL2_0',
1: 'RASTER_CONFIG_RB_XSEL2_1',
2: 'RASTER_CONFIG_RB_XSEL2_2',
3: 'RASTER_CONFIG_RB_XSEL2_3',
}
RASTER_CONFIG_RB_XSEL2_0 = 0
RASTER_CONFIG_RB_XSEL2_1 = 1
RASTER_CONFIG_RB_XSEL2_2 = 2
RASTER_CONFIG_RB_XSEL2_3 = 3
RbXsel2 = ctypes.c_uint32 # enum
# values for enumeration 'RbYsel'
RbYsel__enumvalues = {
0: 'RASTER_CONFIG_RB_YSEL_0',
1: 'RASTER_CONFIG_RB_YSEL_1',
}
RASTER_CONFIG_RB_YSEL_0 = 0
RASTER_CONFIG_RB_YSEL_1 = 1
RbYsel = ctypes.c_uint32 # enum
# values for enumeration 'SC_PERFCNT_SEL'
SC_PERFCNT_SEL__enumvalues = {
0: 'SC_SRPS_WINDOW_VALID',
1: 'SC_PSSW_WINDOW_VALID',
2: 'SC_TPQZ_WINDOW_VALID',
3: 'SC_QZQP_WINDOW_VALID',
4: 'SC_TRPK_WINDOW_VALID',
5: 'SC_SRPS_WINDOW_VALID_BUSY',
6: 'SC_PSSW_WINDOW_VALID_BUSY',
7: 'SC_TPQZ_WINDOW_VALID_BUSY',
8: 'SC_QZQP_WINDOW_VALID_BUSY',
9: 'SC_TRPK_WINDOW_VALID_BUSY',
10: 'SC_STARVED_BY_PA',
11: 'SC_STALLED_BY_PRIMFIFO',
12: 'SC_STALLED_BY_DB_TILE',
13: 'SC_STARVED_BY_DB_TILE',
14: 'SC_STALLED_BY_TILEORDERFIFO',
15: 'SC_STALLED_BY_TILEFIFO',
16: 'SC_STALLED_BY_DB_QUAD',
17: 'SC_STARVED_BY_DB_QUAD',
18: 'SC_STALLED_BY_QUADFIFO',
19: 'SC_STALLED_BY_BCI',
20: 'SC_STALLED_BY_SPI',
21: 'SC_SCISSOR_DISCARD',
22: 'SC_BB_DISCARD',
23: 'SC_SUPERTILE_COUNT',
24: 'SC_SUPERTILE_PER_PRIM_H0',
25: 'SC_SUPERTILE_PER_PRIM_H1',
26: 'SC_SUPERTILE_PER_PRIM_H2',
27: 'SC_SUPERTILE_PER_PRIM_H3',
28: 'SC_SUPERTILE_PER_PRIM_H4',
29: 'SC_SUPERTILE_PER_PRIM_H5',
30: 'SC_SUPERTILE_PER_PRIM_H6',
31: 'SC_SUPERTILE_PER_PRIM_H7',
32: 'SC_SUPERTILE_PER_PRIM_H8',
33: 'SC_SUPERTILE_PER_PRIM_H9',
34: 'SC_SUPERTILE_PER_PRIM_H10',
35: 'SC_SUPERTILE_PER_PRIM_H11',
36: 'SC_SUPERTILE_PER_PRIM_H12',
37: 'SC_SUPERTILE_PER_PRIM_H13',
38: 'SC_SUPERTILE_PER_PRIM_H14',
39: 'SC_SUPERTILE_PER_PRIM_H15',
40: 'SC_SUPERTILE_PER_PRIM_H16',
41: 'SC_TILE_PER_PRIM_H0',
42: 'SC_TILE_PER_PRIM_H1',
43: 'SC_TILE_PER_PRIM_H2',
44: 'SC_TILE_PER_PRIM_H3',
45: 'SC_TILE_PER_PRIM_H4',
46: 'SC_TILE_PER_PRIM_H5',
47: 'SC_TILE_PER_PRIM_H6',
48: 'SC_TILE_PER_PRIM_H7',
49: 'SC_TILE_PER_PRIM_H8',
50: 'SC_TILE_PER_PRIM_H9',
51: 'SC_TILE_PER_PRIM_H10',
52: 'SC_TILE_PER_PRIM_H11',
53: 'SC_TILE_PER_PRIM_H12',
54: 'SC_TILE_PER_PRIM_H13',
55: 'SC_TILE_PER_PRIM_H14',
56: 'SC_TILE_PER_PRIM_H15',
57: 'SC_TILE_PER_PRIM_H16',
58: 'SC_TILE_PER_SUPERTILE_H0',
59: 'SC_TILE_PER_SUPERTILE_H1',
60: 'SC_TILE_PER_SUPERTILE_H2',
61: 'SC_TILE_PER_SUPERTILE_H3',
62: 'SC_TILE_PER_SUPERTILE_H4',
63: 'SC_TILE_PER_SUPERTILE_H5',
64: 'SC_TILE_PER_SUPERTILE_H6',
65: 'SC_TILE_PER_SUPERTILE_H7',
66: 'SC_TILE_PER_SUPERTILE_H8',
67: 'SC_TILE_PER_SUPERTILE_H9',
68: 'SC_TILE_PER_SUPERTILE_H10',
69: 'SC_TILE_PER_SUPERTILE_H11',
70: 'SC_TILE_PER_SUPERTILE_H12',
71: 'SC_TILE_PER_SUPERTILE_H13',
72: 'SC_TILE_PER_SUPERTILE_H14',
73: 'SC_TILE_PER_SUPERTILE_H15',
74: 'SC_TILE_PER_SUPERTILE_H16',
75: 'SC_TILE_PICKED_H1',
76: 'SC_TILE_PICKED_H2',
77: 'SC_TILE_PICKED_H3',
78: 'SC_TILE_PICKED_H4',
79: 'SC_QZ0_TILE_COUNT',
80: 'SC_QZ1_TILE_COUNT',
81: 'SC_QZ2_TILE_COUNT',
82: 'SC_QZ3_TILE_COUNT',
83: 'SC_QZ0_TILE_COVERED_COUNT',
84: 'SC_QZ1_TILE_COVERED_COUNT',
85: 'SC_QZ2_TILE_COVERED_COUNT',
86: 'SC_QZ3_TILE_COVERED_COUNT',
87: 'SC_QZ0_TILE_NOT_COVERED_COUNT',
88: 'SC_QZ1_TILE_NOT_COVERED_COUNT',
89: 'SC_QZ2_TILE_NOT_COVERED_COUNT',
90: 'SC_QZ3_TILE_NOT_COVERED_COUNT',
91: 'SC_QZ0_QUAD_PER_TILE_H0',
92: 'SC_QZ0_QUAD_PER_TILE_H1',
93: 'SC_QZ0_QUAD_PER_TILE_H2',
94: 'SC_QZ0_QUAD_PER_TILE_H3',
95: 'SC_QZ0_QUAD_PER_TILE_H4',
96: 'SC_QZ0_QUAD_PER_TILE_H5',
97: 'SC_QZ0_QUAD_PER_TILE_H6',
98: 'SC_QZ0_QUAD_PER_TILE_H7',
99: 'SC_QZ0_QUAD_PER_TILE_H8',
100: 'SC_QZ0_QUAD_PER_TILE_H9',
101: 'SC_QZ0_QUAD_PER_TILE_H10',
102: 'SC_QZ0_QUAD_PER_TILE_H11',
103: 'SC_QZ0_QUAD_PER_TILE_H12',
104: 'SC_QZ0_QUAD_PER_TILE_H13',
105: 'SC_QZ0_QUAD_PER_TILE_H14',
106: 'SC_QZ0_QUAD_PER_TILE_H15',
107: 'SC_QZ0_QUAD_PER_TILE_H16',
108: 'SC_QZ1_QUAD_PER_TILE_H0',
109: 'SC_QZ1_QUAD_PER_TILE_H1',
110: 'SC_QZ1_QUAD_PER_TILE_H2',
111: 'SC_QZ1_QUAD_PER_TILE_H3',
112: 'SC_QZ1_QUAD_PER_TILE_H4',
113: 'SC_QZ1_QUAD_PER_TILE_H5',
114: 'SC_QZ1_QUAD_PER_TILE_H6',
115: 'SC_QZ1_QUAD_PER_TILE_H7',
116: 'SC_QZ1_QUAD_PER_TILE_H8',
117: 'SC_QZ1_QUAD_PER_TILE_H9',
118: 'SC_QZ1_QUAD_PER_TILE_H10',
119: 'SC_QZ1_QUAD_PER_TILE_H11',
120: 'SC_QZ1_QUAD_PER_TILE_H12',
121: 'SC_QZ1_QUAD_PER_TILE_H13',
122: 'SC_QZ1_QUAD_PER_TILE_H14',
123: 'SC_QZ1_QUAD_PER_TILE_H15',
124: 'SC_QZ1_QUAD_PER_TILE_H16',
125: 'SC_QZ2_QUAD_PER_TILE_H0',
126: 'SC_QZ2_QUAD_PER_TILE_H1',
127: 'SC_QZ2_QUAD_PER_TILE_H2',
128: 'SC_QZ2_QUAD_PER_TILE_H3',
129: 'SC_QZ2_QUAD_PER_TILE_H4',
130: 'SC_QZ2_QUAD_PER_TILE_H5',
131: 'SC_QZ2_QUAD_PER_TILE_H6',
132: 'SC_QZ2_QUAD_PER_TILE_H7',
133: 'SC_QZ2_QUAD_PER_TILE_H8',
134: 'SC_QZ2_QUAD_PER_TILE_H9',
135: 'SC_QZ2_QUAD_PER_TILE_H10',
136: 'SC_QZ2_QUAD_PER_TILE_H11',
137: 'SC_QZ2_QUAD_PER_TILE_H12',
138: 'SC_QZ2_QUAD_PER_TILE_H13',
139: 'SC_QZ2_QUAD_PER_TILE_H14',
140: 'SC_QZ2_QUAD_PER_TILE_H15',
141: 'SC_QZ2_QUAD_PER_TILE_H16',
142: 'SC_QZ3_QUAD_PER_TILE_H0',
143: 'SC_QZ3_QUAD_PER_TILE_H1',
144: 'SC_QZ3_QUAD_PER_TILE_H2',
145: 'SC_QZ3_QUAD_PER_TILE_H3',
146: 'SC_QZ3_QUAD_PER_TILE_H4',
147: 'SC_QZ3_QUAD_PER_TILE_H5',
148: 'SC_QZ3_QUAD_PER_TILE_H6',
149: 'SC_QZ3_QUAD_PER_TILE_H7',
150: 'SC_QZ3_QUAD_PER_TILE_H8',
151: 'SC_QZ3_QUAD_PER_TILE_H9',
152: 'SC_QZ3_QUAD_PER_TILE_H10',
153: 'SC_QZ3_QUAD_PER_TILE_H11',
154: 'SC_QZ3_QUAD_PER_TILE_H12',
155: 'SC_QZ3_QUAD_PER_TILE_H13',
156: 'SC_QZ3_QUAD_PER_TILE_H14',
157: 'SC_QZ3_QUAD_PER_TILE_H15',
158: 'SC_QZ3_QUAD_PER_TILE_H16',
159: 'SC_QZ0_QUAD_COUNT',
160: 'SC_QZ1_QUAD_COUNT',
161: 'SC_QZ2_QUAD_COUNT',
162: 'SC_QZ3_QUAD_COUNT',
163: 'SC_P0_HIZ_TILE_COUNT',
164: 'SC_P1_HIZ_TILE_COUNT',
165: 'SC_P2_HIZ_TILE_COUNT',
166: 'SC_P3_HIZ_TILE_COUNT',
167: 'SC_P0_HIZ_QUAD_PER_TILE_H0',
168: 'SC_P0_HIZ_QUAD_PER_TILE_H1',
169: 'SC_P0_HIZ_QUAD_PER_TILE_H2',
170: 'SC_P0_HIZ_QUAD_PER_TILE_H3',
171: 'SC_P0_HIZ_QUAD_PER_TILE_H4',
172: 'SC_P0_HIZ_QUAD_PER_TILE_H5',
173: 'SC_P0_HIZ_QUAD_PER_TILE_H6',
174: 'SC_P0_HIZ_QUAD_PER_TILE_H7',
175: 'SC_P0_HIZ_QUAD_PER_TILE_H8',
176: 'SC_P0_HIZ_QUAD_PER_TILE_H9',
177: 'SC_P0_HIZ_QUAD_PER_TILE_H10',
178: 'SC_P0_HIZ_QUAD_PER_TILE_H11',
179: 'SC_P0_HIZ_QUAD_PER_TILE_H12',
180: 'SC_P0_HIZ_QUAD_PER_TILE_H13',
181: 'SC_P0_HIZ_QUAD_PER_TILE_H14',
182: 'SC_P0_HIZ_QUAD_PER_TILE_H15',
183: 'SC_P0_HIZ_QUAD_PER_TILE_H16',
184: 'SC_P1_HIZ_QUAD_PER_TILE_H0',
185: 'SC_P1_HIZ_QUAD_PER_TILE_H1',
186: 'SC_P1_HIZ_QUAD_PER_TILE_H2',
187: 'SC_P1_HIZ_QUAD_PER_TILE_H3',
188: 'SC_P1_HIZ_QUAD_PER_TILE_H4',
189: 'SC_P1_HIZ_QUAD_PER_TILE_H5',
190: 'SC_P1_HIZ_QUAD_PER_TILE_H6',
191: 'SC_P1_HIZ_QUAD_PER_TILE_H7',
192: 'SC_P1_HIZ_QUAD_PER_TILE_H8',
193: 'SC_P1_HIZ_QUAD_PER_TILE_H9',
194: 'SC_P1_HIZ_QUAD_PER_TILE_H10',
195: 'SC_P1_HIZ_QUAD_PER_TILE_H11',
196: 'SC_P1_HIZ_QUAD_PER_TILE_H12',
197: 'SC_P1_HIZ_QUAD_PER_TILE_H13',
198: 'SC_P1_HIZ_QUAD_PER_TILE_H14',
199: 'SC_P1_HIZ_QUAD_PER_TILE_H15',
200: 'SC_P1_HIZ_QUAD_PER_TILE_H16',
201: 'SC_P2_HIZ_QUAD_PER_TILE_H0',
202: 'SC_P2_HIZ_QUAD_PER_TILE_H1',
203: 'SC_P2_HIZ_QUAD_PER_TILE_H2',
204: 'SC_P2_HIZ_QUAD_PER_TILE_H3',
205: 'SC_P2_HIZ_QUAD_PER_TILE_H4',
206: 'SC_P2_HIZ_QUAD_PER_TILE_H5',
207: 'SC_P2_HIZ_QUAD_PER_TILE_H6',
208: 'SC_P2_HIZ_QUAD_PER_TILE_H7',
209: 'SC_P2_HIZ_QUAD_PER_TILE_H8',
210: 'SC_P2_HIZ_QUAD_PER_TILE_H9',
211: 'SC_P2_HIZ_QUAD_PER_TILE_H10',
212: 'SC_P2_HIZ_QUAD_PER_TILE_H11',
213: 'SC_P2_HIZ_QUAD_PER_TILE_H12',
214: 'SC_P2_HIZ_QUAD_PER_TILE_H13',
215: 'SC_P2_HIZ_QUAD_PER_TILE_H14',
216: 'SC_P2_HIZ_QUAD_PER_TILE_H15',
217: 'SC_P2_HIZ_QUAD_PER_TILE_H16',
218: 'SC_P3_HIZ_QUAD_PER_TILE_H0',
219: 'SC_P3_HIZ_QUAD_PER_TILE_H1',
220: 'SC_P3_HIZ_QUAD_PER_TILE_H2',
221: 'SC_P3_HIZ_QUAD_PER_TILE_H3',
222: 'SC_P3_HIZ_QUAD_PER_TILE_H4',
223: 'SC_P3_HIZ_QUAD_PER_TILE_H5',
224: 'SC_P3_HIZ_QUAD_PER_TILE_H6',
225: 'SC_P3_HIZ_QUAD_PER_TILE_H7',
226: 'SC_P3_HIZ_QUAD_PER_TILE_H8',
227: 'SC_P3_HIZ_QUAD_PER_TILE_H9',
228: 'SC_P3_HIZ_QUAD_PER_TILE_H10',
229: 'SC_P3_HIZ_QUAD_PER_TILE_H11',
230: 'SC_P3_HIZ_QUAD_PER_TILE_H12',
231: 'SC_P3_HIZ_QUAD_PER_TILE_H13',
232: 'SC_P3_HIZ_QUAD_PER_TILE_H14',
233: 'SC_P3_HIZ_QUAD_PER_TILE_H15',
234: 'SC_P3_HIZ_QUAD_PER_TILE_H16',
235: 'SC_P0_HIZ_QUAD_COUNT',
236: 'SC_P1_HIZ_QUAD_COUNT',
237: 'SC_P2_HIZ_QUAD_COUNT',
238: 'SC_P3_HIZ_QUAD_COUNT',
239: 'SC_P0_DETAIL_QUAD_COUNT',
240: 'SC_P1_DETAIL_QUAD_COUNT',
241: 'SC_P2_DETAIL_QUAD_COUNT',
242: 'SC_P3_DETAIL_QUAD_COUNT',
243: 'SC_P0_DETAIL_QUAD_WITH_1_PIX',
244: 'SC_P0_DETAIL_QUAD_WITH_2_PIX',
245: 'SC_P0_DETAIL_QUAD_WITH_3_PIX',
246: 'SC_P0_DETAIL_QUAD_WITH_4_PIX',
247: 'SC_P1_DETAIL_QUAD_WITH_1_PIX',
248: 'SC_P1_DETAIL_QUAD_WITH_2_PIX',
249: 'SC_P1_DETAIL_QUAD_WITH_3_PIX',
250: 'SC_P1_DETAIL_QUAD_WITH_4_PIX',
251: 'SC_P2_DETAIL_QUAD_WITH_1_PIX',
252: 'SC_P2_DETAIL_QUAD_WITH_2_PIX',
253: 'SC_P2_DETAIL_QUAD_WITH_3_PIX',
254: 'SC_P2_DETAIL_QUAD_WITH_4_PIX',
255: 'SC_P3_DETAIL_QUAD_WITH_1_PIX',
256: 'SC_P3_DETAIL_QUAD_WITH_2_PIX',
257: 'SC_P3_DETAIL_QUAD_WITH_3_PIX',
258: 'SC_P3_DETAIL_QUAD_WITH_4_PIX',
259: 'SC_EARLYZ_QUAD_COUNT',
260: 'SC_EARLYZ_QUAD_WITH_1_PIX',
261: 'SC_EARLYZ_QUAD_WITH_2_PIX',
262: 'SC_EARLYZ_QUAD_WITH_3_PIX',
263: 'SC_EARLYZ_QUAD_WITH_4_PIX',
264: 'SC_PKR_QUAD_PER_ROW_H1',
265: 'SC_PKR_QUAD_PER_ROW_H2',
266: 'SC_PKR_4X2_QUAD_SPLIT',
267: 'SC_PKR_4X2_FILL_QUAD',
268: 'SC_PKR_END_OF_VECTOR',
269: 'SC_PKR_CONTROL_XFER',
270: 'SC_PKR_DBHANG_FORCE_EOV',
271: 'SC_REG_SCLK_BUSY',
272: 'SC_GRP0_DYN_SCLK_BUSY',
273: 'SC_GRP1_DYN_SCLK_BUSY',
274: 'SC_GRP2_DYN_SCLK_BUSY',
275: 'SC_GRP3_DYN_SCLK_BUSY',
276: 'SC_GRP4_DYN_SCLK_BUSY',
277: 'SC_PA0_SC_DATA_FIFO_RD',
278: 'SC_PA0_SC_DATA_FIFO_WE',
279: 'SC_PA1_SC_DATA_FIFO_RD',
280: 'SC_PA1_SC_DATA_FIFO_WE',
281: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
282: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES',
283: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
284: 'SC_PS_ARB_STALLED_FROM_BELOW',
285: 'SC_PS_ARB_STARVED_FROM_ABOVE',
286: 'SC_PS_ARB_SC_BUSY',
287: 'SC_PS_ARB_PA_SC_BUSY',
288: 'SC_PA2_SC_DATA_FIFO_RD',
289: 'SC_PA2_SC_DATA_FIFO_WE',
290: 'SC_PA3_SC_DATA_FIFO_RD',
291: 'SC_PA3_SC_DATA_FIFO_WE',
292: 'SC_PA_SC_DEALLOC_0_0_WE',
293: 'SC_PA_SC_DEALLOC_0_1_WE',
294: 'SC_PA_SC_DEALLOC_1_0_WE',
295: 'SC_PA_SC_DEALLOC_1_1_WE',
296: 'SC_PA_SC_DEALLOC_2_0_WE',
297: 'SC_PA_SC_DEALLOC_2_1_WE',
298: 'SC_PA_SC_DEALLOC_3_0_WE',
299: 'SC_PA_SC_DEALLOC_3_1_WE',
300: 'SC_PA0_SC_EOP_WE',
301: 'SC_PA0_SC_EOPG_WE',
302: 'SC_PA0_SC_EVENT_WE',
303: 'SC_PA1_SC_EOP_WE',
304: 'SC_PA1_SC_EOPG_WE',
305: 'SC_PA1_SC_EVENT_WE',
306: 'SC_PA2_SC_EOP_WE',
307: 'SC_PA2_SC_EOPG_WE',
308: 'SC_PA2_SC_EVENT_WE',
309: 'SC_PA3_SC_EOP_WE',
310: 'SC_PA3_SC_EOPG_WE',
311: 'SC_PA3_SC_EVENT_WE',
312: 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO',
313: 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH',
314: 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP',
315: 'SC_PS_ARB_EOP_POP_SYNC_POP',
316: 'SC_PS_ARB_EVENT_SYNC_POP',
317: 'SC_PS_ENG_MULTICYCLE_BUBBLE',
318: 'SC_PA0_SC_FPOV_WE',
319: 'SC_PA1_SC_FPOV_WE',
320: 'SC_PA2_SC_FPOV_WE',
321: 'SC_PA3_SC_FPOV_WE',
322: 'SC_PA0_SC_LPOV_WE',
323: 'SC_PA1_SC_LPOV_WE',
324: 'SC_PA2_SC_LPOV_WE',
325: 'SC_PA3_SC_LPOV_WE',
326: 'SC_SPI_DEALLOC_0_0',
327: 'SC_SPI_DEALLOC_0_1',
328: 'SC_SPI_DEALLOC_0_2',
329: 'SC_SPI_DEALLOC_1_0',
330: 'SC_SPI_DEALLOC_1_1',
331: 'SC_SPI_DEALLOC_1_2',
332: 'SC_SPI_DEALLOC_2_0',
333: 'SC_SPI_DEALLOC_2_1',
334: 'SC_SPI_DEALLOC_2_2',
335: 'SC_SPI_DEALLOC_3_0',
336: 'SC_SPI_DEALLOC_3_1',
337: 'SC_SPI_DEALLOC_3_2',
338: 'SC_SPI_FPOV_0',
339: 'SC_SPI_FPOV_1',
340: 'SC_SPI_FPOV_2',
341: 'SC_SPI_FPOV_3',
342: 'SC_SPI_EVENT',
343: 'SC_PS_TS_EVENT_FIFO_PUSH',
344: 'SC_PS_TS_EVENT_FIFO_POP',
345: 'SC_PS_CTX_DONE_FIFO_PUSH',
346: 'SC_PS_CTX_DONE_FIFO_POP',
347: 'SC_MULTICYCLE_BUBBLE_FREEZE',
348: 'SC_EOP_SYNC_WINDOW',
349: 'SC_PA0_SC_NULL_WE',
350: 'SC_PA0_SC_NULL_DEALLOC_WE',
351: 'SC_PA0_SC_DATA_FIFO_EOPG_RD',
352: 'SC_PA0_SC_DATA_FIFO_EOP_RD',
353: 'SC_PA0_SC_DEALLOC_0_RD',
354: 'SC_PA0_SC_DEALLOC_1_RD',
355: 'SC_PA1_SC_DATA_FIFO_EOPG_RD',
356: 'SC_PA1_SC_DATA_FIFO_EOP_RD',
357: 'SC_PA1_SC_DEALLOC_0_RD',
358: 'SC_PA1_SC_DEALLOC_1_RD',
359: 'SC_PA1_SC_NULL_WE',
360: 'SC_PA1_SC_NULL_DEALLOC_WE',
361: 'SC_PA2_SC_DATA_FIFO_EOPG_RD',
362: 'SC_PA2_SC_DATA_FIFO_EOP_RD',
363: 'SC_PA2_SC_DEALLOC_0_RD',
364: 'SC_PA2_SC_DEALLOC_1_RD',
365: 'SC_PA2_SC_NULL_WE',
366: 'SC_PA2_SC_NULL_DEALLOC_WE',
367: 'SC_PA3_SC_DATA_FIFO_EOPG_RD',
368: 'SC_PA3_SC_DATA_FIFO_EOP_RD',
369: 'SC_PA3_SC_DEALLOC_0_RD',
370: 'SC_PA3_SC_DEALLOC_1_RD',
371: 'SC_PA3_SC_NULL_WE',
372: 'SC_PA3_SC_NULL_DEALLOC_WE',
373: 'SC_PS_PA0_SC_FIFO_EMPTY',
374: 'SC_PS_PA0_SC_FIFO_FULL',
375: 'SC_RESERVED_0',
376: 'SC_PS_PA1_SC_FIFO_EMPTY',
377: 'SC_PS_PA1_SC_FIFO_FULL',
378: 'SC_RESERVED_1',
379: 'SC_PS_PA2_SC_FIFO_EMPTY',
380: 'SC_PS_PA2_SC_FIFO_FULL',
381: 'SC_RESERVED_2',
382: 'SC_PS_PA3_SC_FIFO_EMPTY',
383: 'SC_PS_PA3_SC_FIFO_FULL',
384: 'SC_RESERVED_3',
385: 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM',
386: 'SC_BUSY_CNT_NOT_ZERO',
387: 'SC_BM_BUSY',
388: 'SC_BACKEND_BUSY',
389: 'SC_SCF_SCB_INTERFACE_BUSY',
390: 'SC_SCB_BUSY',
391: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY',
392: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL',
393: 'SC_PBB_BIN_HIST_NUM_PRIMS',
394: 'SC_PBB_BATCH_HIST_NUM_PRIMS',
395: 'SC_PBB_BIN_HIST_NUM_CONTEXTS',
396: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS',
397: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES',
398: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES',
399: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS',
400: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS',
401: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM',
402: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW',
403: 'SC_PBB_BUSY',
404: 'SC_PBB_BUSY_AND_NO_SENDS',
405: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES',
406: 'SC_PBB_NUM_BINS',
407: 'SC_PBB_END_OF_BIN',
408: 'SC_PBB_END_OF_BATCH',
409: 'SC_PBB_PRIMBIN_PROCESSED',
410: 'SC_PBB_PRIM_ADDED_TO_BATCH',
411: 'SC_PBB_NONBINNED_PRIM',
412: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB',
413: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB',
414: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION',
415: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW',
416: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN',
417: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE',
418: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE',
419: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM',
420: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE',
421: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT',
422: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT',
423: 'SC_POPS_INTRA_WAVE_OVERLAPS',
424: 'SC_POPS_FORCE_EOV',
425: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX',
426: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP',
427: 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE',
428: 'SC_FULL_FULL_QUAD',
429: 'SC_FULL_HALF_QUAD',
430: 'SC_FULL_QTR_QUAD',
431: 'SC_HALF_FULL_QUAD',
432: 'SC_HALF_HALF_QUAD',
433: 'SC_HALF_QTR_QUAD',
434: 'SC_QTR_FULL_QUAD',
435: 'SC_QTR_HALF_QUAD',
436: 'SC_QTR_QTR_QUAD',
437: 'SC_GRP5_DYN_SCLK_BUSY',
438: 'SC_GRP6_DYN_SCLK_BUSY',
439: 'SC_GRP7_DYN_SCLK_BUSY',
440: 'SC_GRP8_DYN_SCLK_BUSY',
441: 'SC_GRP9_DYN_SCLK_BUSY',
442: 'SC_PS_TO_BE_SCLK_GATE_STALL',
443: 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL',
444: 'SC_PK_BUSY',
445: 'SC_PK_MAX_DEALLOC_FORCE_EOV',
446: 'SC_PK_DEALLOC_WAVE_BREAK',
447: 'SC_SPI_SEND',
448: 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND',
449: 'SC_SPI_CREDIT_AT_MAX',
450: 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND',
451: 'SC_BCI_SEND',
452: 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND',
453: 'SC_BCI_CREDIT_AT_MAX',
454: 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND',
455: 'SC_SPIBC_FULL_FREEZE',
456: 'SC_PW_BM_PASS_EMPTY_PRIM',
457: 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM',
458: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0',
459: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1',
460: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2',
461: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3',
462: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4',
463: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5',
464: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6',
465: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7',
466: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8',
467: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9',
468: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10',
469: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11',
470: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12',
471: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13',
472: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14',
473: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15',
474: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16',
475: 'SC_DB0_TILE_INTERFACE_BUSY',
476: 'SC_DB0_TILE_INTERFACE_SEND',
477: 'SC_DB0_TILE_INTERFACE_SEND_EVENT',
478: 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT',
479: 'SC_DB0_TILE_INTERFACE_SEND_SOP',
480: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND',
481: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX',
482: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND',
483: 'SC_DB1_TILE_INTERFACE_BUSY',
484: 'SC_DB1_TILE_INTERFACE_SEND',
485: 'SC_DB1_TILE_INTERFACE_SEND_EVENT',
486: 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT',
487: 'SC_DB1_TILE_INTERFACE_SEND_SOP',
488: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND',
489: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX',
490: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND',
491: 'SC_BACKEND_PRIM_FIFO_FULL',
492: 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER',
493: 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH',
494: 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH',
495: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT',
496: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT',
497: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV',
498: 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE',
499: 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE',
500: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT',
501: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET',
502: 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE',
503: 'SC_STALLED_BY_DB0_TILEFIFO',
504: 'SC_DB0_QUAD_INTF_SEND',
505: 'SC_DB0_QUAD_INTF_BUSY',
506: 'SC_DB0_QUAD_INTF_STALLED_BY_DB',
507: 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX',
508: 'SC_DB0_QUAD_INTF_IDLE',
509: 'SC_DB1_QUAD_INTF_SEND',
510: 'SC_STALLED_BY_DB1_TILEFIFO',
511: 'SC_DB1_QUAD_INTF_BUSY',
512: 'SC_DB1_QUAD_INTF_STALLED_BY_DB',
513: 'SC_DB1_QUAD_INTF_CREDIT_AT_MAX',
514: 'SC_DB1_QUAD_INTF_IDLE',
515: 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION',
516: 'SC_PKR_WAVE_BREAK_FULL_TILE',
517: 'SC_FSR_WALKED',
518: 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN',
519: 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT',
520: 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL',
521: 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL',
522: 'SC_DB0_TILE_MASK_FIFO_FULL',
523: 'SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL',
524: 'SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL',
525: 'SC_DB1_TILE_MASK_FIFO_FULL',
526: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL',
527: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL',
528: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL',
529: 'SC_PS_PM_PFF_PW_FULL',
530: 'SC_PS_PM_ZFF_PW_FULL',
531: 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL',
532: 'SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H',
533: 'SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H',
534: 'SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H',
535: 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H',
536: 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H',
537: 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H',
538: 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H',
539: 'SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H',
540: 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H',
541: 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H',
542: 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H',
543: 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H',
544: 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H',
545: 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H',
546: 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H',
547: 'SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H',
548: 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H',
549: 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H',
550: 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H',
551: 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H',
552: 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD',
553: 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD',
554: 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD',
555: 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD',
556: 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD',
557: 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD',
558: 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD',
559: 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD',
560: 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD',
561: 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD',
562: 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD',
563: 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD',
564: 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD',
565: 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD',
566: 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD',
567: 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD',
568: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE',
569: 'SC_PBB_RESERVED',
570: 'SC_BM_BE0_STALLED',
571: 'SC_BM_BE1_STALLED',
572: 'SC_BM_BE2_STALLED',
573: 'SC_BM_BE3_STALLED',
574: 'SC_BM_MULTI_ACCUM_1_BE_STALLED',
575: 'SC_BM_MULTI_ACCUM_2_BE_STALLED',
576: 'SC_BM_MULTI_ACCUM_3_BE_STALLED',
577: 'SC_BM_MULTI_ACCUM_4_BE_STALLED',
}
SC_SRPS_WINDOW_VALID = 0
SC_PSSW_WINDOW_VALID = 1
SC_TPQZ_WINDOW_VALID = 2
SC_QZQP_WINDOW_VALID = 3
SC_TRPK_WINDOW_VALID = 4
SC_SRPS_WINDOW_VALID_BUSY = 5
SC_PSSW_WINDOW_VALID_BUSY = 6
SC_TPQZ_WINDOW_VALID_BUSY = 7
SC_QZQP_WINDOW_VALID_BUSY = 8
SC_TRPK_WINDOW_VALID_BUSY = 9
SC_STARVED_BY_PA = 10
SC_STALLED_BY_PRIMFIFO = 11
SC_STALLED_BY_DB_TILE = 12
SC_STARVED_BY_DB_TILE = 13
SC_STALLED_BY_TILEORDERFIFO = 14
SC_STALLED_BY_TILEFIFO = 15
SC_STALLED_BY_DB_QUAD = 16
SC_STARVED_BY_DB_QUAD = 17
SC_STALLED_BY_QUADFIFO = 18
SC_STALLED_BY_BCI = 19
SC_STALLED_BY_SPI = 20
SC_SCISSOR_DISCARD = 21
SC_BB_DISCARD = 22
SC_SUPERTILE_COUNT = 23
SC_SUPERTILE_PER_PRIM_H0 = 24
SC_SUPERTILE_PER_PRIM_H1 = 25
SC_SUPERTILE_PER_PRIM_H2 = 26
SC_SUPERTILE_PER_PRIM_H3 = 27
SC_SUPERTILE_PER_PRIM_H4 = 28
SC_SUPERTILE_PER_PRIM_H5 = 29
SC_SUPERTILE_PER_PRIM_H6 = 30
SC_SUPERTILE_PER_PRIM_H7 = 31
SC_SUPERTILE_PER_PRIM_H8 = 32
SC_SUPERTILE_PER_PRIM_H9 = 33
SC_SUPERTILE_PER_PRIM_H10 = 34
SC_SUPERTILE_PER_PRIM_H11 = 35
SC_SUPERTILE_PER_PRIM_H12 = 36
SC_SUPERTILE_PER_PRIM_H13 = 37
SC_SUPERTILE_PER_PRIM_H14 = 38
SC_SUPERTILE_PER_PRIM_H15 = 39
SC_SUPERTILE_PER_PRIM_H16 = 40
SC_TILE_PER_PRIM_H0 = 41
SC_TILE_PER_PRIM_H1 = 42
SC_TILE_PER_PRIM_H2 = 43
SC_TILE_PER_PRIM_H3 = 44
SC_TILE_PER_PRIM_H4 = 45
SC_TILE_PER_PRIM_H5 = 46
SC_TILE_PER_PRIM_H6 = 47
SC_TILE_PER_PRIM_H7 = 48
SC_TILE_PER_PRIM_H8 = 49
SC_TILE_PER_PRIM_H9 = 50
SC_TILE_PER_PRIM_H10 = 51
SC_TILE_PER_PRIM_H11 = 52
SC_TILE_PER_PRIM_H12 = 53
SC_TILE_PER_PRIM_H13 = 54
SC_TILE_PER_PRIM_H14 = 55
SC_TILE_PER_PRIM_H15 = 56
SC_TILE_PER_PRIM_H16 = 57
SC_TILE_PER_SUPERTILE_H0 = 58
SC_TILE_PER_SUPERTILE_H1 = 59
SC_TILE_PER_SUPERTILE_H2 = 60
SC_TILE_PER_SUPERTILE_H3 = 61
SC_TILE_PER_SUPERTILE_H4 = 62
SC_TILE_PER_SUPERTILE_H5 = 63
SC_TILE_PER_SUPERTILE_H6 = 64
SC_TILE_PER_SUPERTILE_H7 = 65
SC_TILE_PER_SUPERTILE_H8 = 66
SC_TILE_PER_SUPERTILE_H9 = 67
SC_TILE_PER_SUPERTILE_H10 = 68
SC_TILE_PER_SUPERTILE_H11 = 69
SC_TILE_PER_SUPERTILE_H12 = 70
SC_TILE_PER_SUPERTILE_H13 = 71
SC_TILE_PER_SUPERTILE_H14 = 72
SC_TILE_PER_SUPERTILE_H15 = 73
SC_TILE_PER_SUPERTILE_H16 = 74
SC_TILE_PICKED_H1 = 75
SC_TILE_PICKED_H2 = 76
SC_TILE_PICKED_H3 = 77
SC_TILE_PICKED_H4 = 78
SC_QZ0_TILE_COUNT = 79
SC_QZ1_TILE_COUNT = 80
SC_QZ2_TILE_COUNT = 81
SC_QZ3_TILE_COUNT = 82
SC_QZ0_TILE_COVERED_COUNT = 83
SC_QZ1_TILE_COVERED_COUNT = 84
SC_QZ2_TILE_COVERED_COUNT = 85
SC_QZ3_TILE_COVERED_COUNT = 86
SC_QZ0_TILE_NOT_COVERED_COUNT = 87
SC_QZ1_TILE_NOT_COVERED_COUNT = 88
SC_QZ2_TILE_NOT_COVERED_COUNT = 89
SC_QZ3_TILE_NOT_COVERED_COUNT = 90
SC_QZ0_QUAD_PER_TILE_H0 = 91
SC_QZ0_QUAD_PER_TILE_H1 = 92
SC_QZ0_QUAD_PER_TILE_H2 = 93
SC_QZ0_QUAD_PER_TILE_H3 = 94
SC_QZ0_QUAD_PER_TILE_H4 = 95
SC_QZ0_QUAD_PER_TILE_H5 = 96
SC_QZ0_QUAD_PER_TILE_H6 = 97
SC_QZ0_QUAD_PER_TILE_H7 = 98
SC_QZ0_QUAD_PER_TILE_H8 = 99
SC_QZ0_QUAD_PER_TILE_H9 = 100
SC_QZ0_QUAD_PER_TILE_H10 = 101
SC_QZ0_QUAD_PER_TILE_H11 = 102
SC_QZ0_QUAD_PER_TILE_H12 = 103
SC_QZ0_QUAD_PER_TILE_H13 = 104
SC_QZ0_QUAD_PER_TILE_H14 = 105
SC_QZ0_QUAD_PER_TILE_H15 = 106
SC_QZ0_QUAD_PER_TILE_H16 = 107
SC_QZ1_QUAD_PER_TILE_H0 = 108
SC_QZ1_QUAD_PER_TILE_H1 = 109
SC_QZ1_QUAD_PER_TILE_H2 = 110
SC_QZ1_QUAD_PER_TILE_H3 = 111
SC_QZ1_QUAD_PER_TILE_H4 = 112
SC_QZ1_QUAD_PER_TILE_H5 = 113
SC_QZ1_QUAD_PER_TILE_H6 = 114
SC_QZ1_QUAD_PER_TILE_H7 = 115
SC_QZ1_QUAD_PER_TILE_H8 = 116
SC_QZ1_QUAD_PER_TILE_H9 = 117
SC_QZ1_QUAD_PER_TILE_H10 = 118
SC_QZ1_QUAD_PER_TILE_H11 = 119
SC_QZ1_QUAD_PER_TILE_H12 = 120
SC_QZ1_QUAD_PER_TILE_H13 = 121
SC_QZ1_QUAD_PER_TILE_H14 = 122
SC_QZ1_QUAD_PER_TILE_H15 = 123
SC_QZ1_QUAD_PER_TILE_H16 = 124
SC_QZ2_QUAD_PER_TILE_H0 = 125
SC_QZ2_QUAD_PER_TILE_H1 = 126
SC_QZ2_QUAD_PER_TILE_H2 = 127
SC_QZ2_QUAD_PER_TILE_H3 = 128
SC_QZ2_QUAD_PER_TILE_H4 = 129
SC_QZ2_QUAD_PER_TILE_H5 = 130
SC_QZ2_QUAD_PER_TILE_H6 = 131
SC_QZ2_QUAD_PER_TILE_H7 = 132
SC_QZ2_QUAD_PER_TILE_H8 = 133
SC_QZ2_QUAD_PER_TILE_H9 = 134
SC_QZ2_QUAD_PER_TILE_H10 = 135
SC_QZ2_QUAD_PER_TILE_H11 = 136
SC_QZ2_QUAD_PER_TILE_H12 = 137
SC_QZ2_QUAD_PER_TILE_H13 = 138
SC_QZ2_QUAD_PER_TILE_H14 = 139
SC_QZ2_QUAD_PER_TILE_H15 = 140
SC_QZ2_QUAD_PER_TILE_H16 = 141
SC_QZ3_QUAD_PER_TILE_H0 = 142
SC_QZ3_QUAD_PER_TILE_H1 = 143
SC_QZ3_QUAD_PER_TILE_H2 = 144
SC_QZ3_QUAD_PER_TILE_H3 = 145
SC_QZ3_QUAD_PER_TILE_H4 = 146
SC_QZ3_QUAD_PER_TILE_H5 = 147
SC_QZ3_QUAD_PER_TILE_H6 = 148
SC_QZ3_QUAD_PER_TILE_H7 = 149
SC_QZ3_QUAD_PER_TILE_H8 = 150
SC_QZ3_QUAD_PER_TILE_H9 = 151
SC_QZ3_QUAD_PER_TILE_H10 = 152
SC_QZ3_QUAD_PER_TILE_H11 = 153
SC_QZ3_QUAD_PER_TILE_H12 = 154
SC_QZ3_QUAD_PER_TILE_H13 = 155
SC_QZ3_QUAD_PER_TILE_H14 = 156
SC_QZ3_QUAD_PER_TILE_H15 = 157
SC_QZ3_QUAD_PER_TILE_H16 = 158
SC_QZ0_QUAD_COUNT = 159
SC_QZ1_QUAD_COUNT = 160
SC_QZ2_QUAD_COUNT = 161
SC_QZ3_QUAD_COUNT = 162
SC_P0_HIZ_TILE_COUNT = 163
SC_P1_HIZ_TILE_COUNT = 164
SC_P2_HIZ_TILE_COUNT = 165
SC_P3_HIZ_TILE_COUNT = 166
SC_P0_HIZ_QUAD_PER_TILE_H0 = 167
SC_P0_HIZ_QUAD_PER_TILE_H1 = 168
SC_P0_HIZ_QUAD_PER_TILE_H2 = 169
SC_P0_HIZ_QUAD_PER_TILE_H3 = 170
SC_P0_HIZ_QUAD_PER_TILE_H4 = 171
SC_P0_HIZ_QUAD_PER_TILE_H5 = 172
SC_P0_HIZ_QUAD_PER_TILE_H6 = 173
SC_P0_HIZ_QUAD_PER_TILE_H7 = 174
SC_P0_HIZ_QUAD_PER_TILE_H8 = 175
SC_P0_HIZ_QUAD_PER_TILE_H9 = 176
SC_P0_HIZ_QUAD_PER_TILE_H10 = 177
SC_P0_HIZ_QUAD_PER_TILE_H11 = 178
SC_P0_HIZ_QUAD_PER_TILE_H12 = 179
SC_P0_HIZ_QUAD_PER_TILE_H13 = 180
SC_P0_HIZ_QUAD_PER_TILE_H14 = 181
SC_P0_HIZ_QUAD_PER_TILE_H15 = 182
SC_P0_HIZ_QUAD_PER_TILE_H16 = 183
SC_P1_HIZ_QUAD_PER_TILE_H0 = 184
SC_P1_HIZ_QUAD_PER_TILE_H1 = 185
SC_P1_HIZ_QUAD_PER_TILE_H2 = 186
SC_P1_HIZ_QUAD_PER_TILE_H3 = 187
SC_P1_HIZ_QUAD_PER_TILE_H4 = 188
SC_P1_HIZ_QUAD_PER_TILE_H5 = 189
SC_P1_HIZ_QUAD_PER_TILE_H6 = 190
SC_P1_HIZ_QUAD_PER_TILE_H7 = 191
SC_P1_HIZ_QUAD_PER_TILE_H8 = 192
SC_P1_HIZ_QUAD_PER_TILE_H9 = 193
SC_P1_HIZ_QUAD_PER_TILE_H10 = 194
SC_P1_HIZ_QUAD_PER_TILE_H11 = 195
SC_P1_HIZ_QUAD_PER_TILE_H12 = 196
SC_P1_HIZ_QUAD_PER_TILE_H13 = 197
SC_P1_HIZ_QUAD_PER_TILE_H14 = 198
SC_P1_HIZ_QUAD_PER_TILE_H15 = 199
SC_P1_HIZ_QUAD_PER_TILE_H16 = 200
SC_P2_HIZ_QUAD_PER_TILE_H0 = 201
SC_P2_HIZ_QUAD_PER_TILE_H1 = 202
SC_P2_HIZ_QUAD_PER_TILE_H2 = 203
SC_P2_HIZ_QUAD_PER_TILE_H3 = 204
SC_P2_HIZ_QUAD_PER_TILE_H4 = 205
SC_P2_HIZ_QUAD_PER_TILE_H5 = 206
SC_P2_HIZ_QUAD_PER_TILE_H6 = 207
SC_P2_HIZ_QUAD_PER_TILE_H7 = 208
SC_P2_HIZ_QUAD_PER_TILE_H8 = 209
SC_P2_HIZ_QUAD_PER_TILE_H9 = 210
SC_P2_HIZ_QUAD_PER_TILE_H10 = 211
SC_P2_HIZ_QUAD_PER_TILE_H11 = 212
SC_P2_HIZ_QUAD_PER_TILE_H12 = 213
SC_P2_HIZ_QUAD_PER_TILE_H13 = 214
SC_P2_HIZ_QUAD_PER_TILE_H14 = 215
SC_P2_HIZ_QUAD_PER_TILE_H15 = 216
SC_P2_HIZ_QUAD_PER_TILE_H16 = 217
SC_P3_HIZ_QUAD_PER_TILE_H0 = 218
SC_P3_HIZ_QUAD_PER_TILE_H1 = 219
SC_P3_HIZ_QUAD_PER_TILE_H2 = 220
SC_P3_HIZ_QUAD_PER_TILE_H3 = 221
SC_P3_HIZ_QUAD_PER_TILE_H4 = 222
SC_P3_HIZ_QUAD_PER_TILE_H5 = 223
SC_P3_HIZ_QUAD_PER_TILE_H6 = 224
SC_P3_HIZ_QUAD_PER_TILE_H7 = 225
SC_P3_HIZ_QUAD_PER_TILE_H8 = 226
SC_P3_HIZ_QUAD_PER_TILE_H9 = 227
SC_P3_HIZ_QUAD_PER_TILE_H10 = 228
SC_P3_HIZ_QUAD_PER_TILE_H11 = 229
SC_P3_HIZ_QUAD_PER_TILE_H12 = 230
SC_P3_HIZ_QUAD_PER_TILE_H13 = 231
SC_P3_HIZ_QUAD_PER_TILE_H14 = 232
SC_P3_HIZ_QUAD_PER_TILE_H15 = 233
SC_P3_HIZ_QUAD_PER_TILE_H16 = 234
SC_P0_HIZ_QUAD_COUNT = 235
SC_P1_HIZ_QUAD_COUNT = 236
SC_P2_HIZ_QUAD_COUNT = 237
SC_P3_HIZ_QUAD_COUNT = 238
SC_P0_DETAIL_QUAD_COUNT = 239
SC_P1_DETAIL_QUAD_COUNT = 240
SC_P2_DETAIL_QUAD_COUNT = 241
SC_P3_DETAIL_QUAD_COUNT = 242
SC_P0_DETAIL_QUAD_WITH_1_PIX = 243
SC_P0_DETAIL_QUAD_WITH_2_PIX = 244
SC_P0_DETAIL_QUAD_WITH_3_PIX = 245
SC_P0_DETAIL_QUAD_WITH_4_PIX = 246
SC_P1_DETAIL_QUAD_WITH_1_PIX = 247
SC_P1_DETAIL_QUAD_WITH_2_PIX = 248
SC_P1_DETAIL_QUAD_WITH_3_PIX = 249
SC_P1_DETAIL_QUAD_WITH_4_PIX = 250
SC_P2_DETAIL_QUAD_WITH_1_PIX = 251
SC_P2_DETAIL_QUAD_WITH_2_PIX = 252
SC_P2_DETAIL_QUAD_WITH_3_PIX = 253
SC_P2_DETAIL_QUAD_WITH_4_PIX = 254
SC_P3_DETAIL_QUAD_WITH_1_PIX = 255
SC_P3_DETAIL_QUAD_WITH_2_PIX = 256
SC_P3_DETAIL_QUAD_WITH_3_PIX = 257
SC_P3_DETAIL_QUAD_WITH_4_PIX = 258
SC_EARLYZ_QUAD_COUNT = 259
SC_EARLYZ_QUAD_WITH_1_PIX = 260
SC_EARLYZ_QUAD_WITH_2_PIX = 261
SC_EARLYZ_QUAD_WITH_3_PIX = 262
SC_EARLYZ_QUAD_WITH_4_PIX = 263
SC_PKR_QUAD_PER_ROW_H1 = 264
SC_PKR_QUAD_PER_ROW_H2 = 265
SC_PKR_4X2_QUAD_SPLIT = 266
SC_PKR_4X2_FILL_QUAD = 267
SC_PKR_END_OF_VECTOR = 268
SC_PKR_CONTROL_XFER = 269
SC_PKR_DBHANG_FORCE_EOV = 270
SC_REG_SCLK_BUSY = 271
SC_GRP0_DYN_SCLK_BUSY = 272
SC_GRP1_DYN_SCLK_BUSY = 273
SC_GRP2_DYN_SCLK_BUSY = 274
SC_GRP3_DYN_SCLK_BUSY = 275
SC_GRP4_DYN_SCLK_BUSY = 276
SC_PA0_SC_DATA_FIFO_RD = 277
SC_PA0_SC_DATA_FIFO_WE = 278
SC_PA1_SC_DATA_FIFO_RD = 279
SC_PA1_SC_DATA_FIFO_WE = 280
SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 281
SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 282
SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 283
SC_PS_ARB_STALLED_FROM_BELOW = 284
SC_PS_ARB_STARVED_FROM_ABOVE = 285
SC_PS_ARB_SC_BUSY = 286
SC_PS_ARB_PA_SC_BUSY = 287
SC_PA2_SC_DATA_FIFO_RD = 288
SC_PA2_SC_DATA_FIFO_WE = 289
SC_PA3_SC_DATA_FIFO_RD = 290
SC_PA3_SC_DATA_FIFO_WE = 291
SC_PA_SC_DEALLOC_0_0_WE = 292
SC_PA_SC_DEALLOC_0_1_WE = 293
SC_PA_SC_DEALLOC_1_0_WE = 294
SC_PA_SC_DEALLOC_1_1_WE = 295
SC_PA_SC_DEALLOC_2_0_WE = 296
SC_PA_SC_DEALLOC_2_1_WE = 297
SC_PA_SC_DEALLOC_3_0_WE = 298
SC_PA_SC_DEALLOC_3_1_WE = 299
SC_PA0_SC_EOP_WE = 300
SC_PA0_SC_EOPG_WE = 301
SC_PA0_SC_EVENT_WE = 302
SC_PA1_SC_EOP_WE = 303
SC_PA1_SC_EOPG_WE = 304
SC_PA1_SC_EVENT_WE = 305
SC_PA2_SC_EOP_WE = 306
SC_PA2_SC_EOPG_WE = 307
SC_PA2_SC_EVENT_WE = 308
SC_PA3_SC_EOP_WE = 309
SC_PA3_SC_EOPG_WE = 310
SC_PA3_SC_EVENT_WE = 311
SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 312
SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 313
SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 314
SC_PS_ARB_EOP_POP_SYNC_POP = 315
SC_PS_ARB_EVENT_SYNC_POP = 316
SC_PS_ENG_MULTICYCLE_BUBBLE = 317
SC_PA0_SC_FPOV_WE = 318
SC_PA1_SC_FPOV_WE = 319
SC_PA2_SC_FPOV_WE = 320
SC_PA3_SC_FPOV_WE = 321
SC_PA0_SC_LPOV_WE = 322
SC_PA1_SC_LPOV_WE = 323
SC_PA2_SC_LPOV_WE = 324
SC_PA3_SC_LPOV_WE = 325
SC_SPI_DEALLOC_0_0 = 326
SC_SPI_DEALLOC_0_1 = 327
SC_SPI_DEALLOC_0_2 = 328
SC_SPI_DEALLOC_1_0 = 329
SC_SPI_DEALLOC_1_1 = 330
SC_SPI_DEALLOC_1_2 = 331
SC_SPI_DEALLOC_2_0 = 332
SC_SPI_DEALLOC_2_1 = 333
SC_SPI_DEALLOC_2_2 = 334
SC_SPI_DEALLOC_3_0 = 335
SC_SPI_DEALLOC_3_1 = 336
SC_SPI_DEALLOC_3_2 = 337
SC_SPI_FPOV_0 = 338
SC_SPI_FPOV_1 = 339
SC_SPI_FPOV_2 = 340
SC_SPI_FPOV_3 = 341
SC_SPI_EVENT = 342
SC_PS_TS_EVENT_FIFO_PUSH = 343
SC_PS_TS_EVENT_FIFO_POP = 344
SC_PS_CTX_DONE_FIFO_PUSH = 345
SC_PS_CTX_DONE_FIFO_POP = 346
SC_MULTICYCLE_BUBBLE_FREEZE = 347
SC_EOP_SYNC_WINDOW = 348
SC_PA0_SC_NULL_WE = 349
SC_PA0_SC_NULL_DEALLOC_WE = 350
SC_PA0_SC_DATA_FIFO_EOPG_RD = 351
SC_PA0_SC_DATA_FIFO_EOP_RD = 352
SC_PA0_SC_DEALLOC_0_RD = 353
SC_PA0_SC_DEALLOC_1_RD = 354
SC_PA1_SC_DATA_FIFO_EOPG_RD = 355
SC_PA1_SC_DATA_FIFO_EOP_RD = 356
SC_PA1_SC_DEALLOC_0_RD = 357
SC_PA1_SC_DEALLOC_1_RD = 358
SC_PA1_SC_NULL_WE = 359
SC_PA1_SC_NULL_DEALLOC_WE = 360
SC_PA2_SC_DATA_FIFO_EOPG_RD = 361
SC_PA2_SC_DATA_FIFO_EOP_RD = 362
SC_PA2_SC_DEALLOC_0_RD = 363
SC_PA2_SC_DEALLOC_1_RD = 364
SC_PA2_SC_NULL_WE = 365
SC_PA2_SC_NULL_DEALLOC_WE = 366
SC_PA3_SC_DATA_FIFO_EOPG_RD = 367
SC_PA3_SC_DATA_FIFO_EOP_RD = 368
SC_PA3_SC_DEALLOC_0_RD = 369
SC_PA3_SC_DEALLOC_1_RD = 370
SC_PA3_SC_NULL_WE = 371
SC_PA3_SC_NULL_DEALLOC_WE = 372
SC_PS_PA0_SC_FIFO_EMPTY = 373
SC_PS_PA0_SC_FIFO_FULL = 374
SC_RESERVED_0 = 375
SC_PS_PA1_SC_FIFO_EMPTY = 376
SC_PS_PA1_SC_FIFO_FULL = 377
SC_RESERVED_1 = 378
SC_PS_PA2_SC_FIFO_EMPTY = 379
SC_PS_PA2_SC_FIFO_FULL = 380
SC_RESERVED_2 = 381
SC_PS_PA3_SC_FIFO_EMPTY = 382
SC_PS_PA3_SC_FIFO_FULL = 383
SC_RESERVED_3 = 384
SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 385
SC_BUSY_CNT_NOT_ZERO = 386
SC_BM_BUSY = 387
SC_BACKEND_BUSY = 388
SC_SCF_SCB_INTERFACE_BUSY = 389
SC_SCB_BUSY = 390
SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 391
SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 392
SC_PBB_BIN_HIST_NUM_PRIMS = 393
SC_PBB_BATCH_HIST_NUM_PRIMS = 394
SC_PBB_BIN_HIST_NUM_CONTEXTS = 395
SC_PBB_BATCH_HIST_NUM_CONTEXTS = 396
SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 397
SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 398
SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 399
SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 400
SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 401
SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 402
SC_PBB_BUSY = 403
SC_PBB_BUSY_AND_NO_SENDS = 404
SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 405
SC_PBB_NUM_BINS = 406
SC_PBB_END_OF_BIN = 407
SC_PBB_END_OF_BATCH = 408
SC_PBB_PRIMBIN_PROCESSED = 409
SC_PBB_PRIM_ADDED_TO_BATCH = 410
SC_PBB_NONBINNED_PRIM = 411
SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 412
SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 413
SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 414
SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 415
SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 416
SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 417
SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 418
SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 419
SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 420
SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 421
SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 422
SC_POPS_INTRA_WAVE_OVERLAPS = 423
SC_POPS_FORCE_EOV = 424
SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 425
SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 426
SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 427
SC_FULL_FULL_QUAD = 428
SC_FULL_HALF_QUAD = 429
SC_FULL_QTR_QUAD = 430
SC_HALF_FULL_QUAD = 431
SC_HALF_HALF_QUAD = 432
SC_HALF_QTR_QUAD = 433
SC_QTR_FULL_QUAD = 434
SC_QTR_HALF_QUAD = 435
SC_QTR_QTR_QUAD = 436
SC_GRP5_DYN_SCLK_BUSY = 437
SC_GRP6_DYN_SCLK_BUSY = 438
SC_GRP7_DYN_SCLK_BUSY = 439
SC_GRP8_DYN_SCLK_BUSY = 440
SC_GRP9_DYN_SCLK_BUSY = 441
SC_PS_TO_BE_SCLK_GATE_STALL = 442
SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 443
SC_PK_BUSY = 444
SC_PK_MAX_DEALLOC_FORCE_EOV = 445
SC_PK_DEALLOC_WAVE_BREAK = 446
SC_SPI_SEND = 447
SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 448
SC_SPI_CREDIT_AT_MAX = 449
SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 450
SC_BCI_SEND = 451
SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 452
SC_BCI_CREDIT_AT_MAX = 453
SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 454
SC_SPIBC_FULL_FREEZE = 455
SC_PW_BM_PASS_EMPTY_PRIM = 456
SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 457
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 458
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 459
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 460
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 461
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 462
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 463
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 464
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 465
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 466
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 467
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 468
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 469
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 470
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 471
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 472
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 473
SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 474
SC_DB0_TILE_INTERFACE_BUSY = 475
SC_DB0_TILE_INTERFACE_SEND = 476
SC_DB0_TILE_INTERFACE_SEND_EVENT = 477
SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 478
SC_DB0_TILE_INTERFACE_SEND_SOP = 479
SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 480
SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 481
SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 482
SC_DB1_TILE_INTERFACE_BUSY = 483
SC_DB1_TILE_INTERFACE_SEND = 484
SC_DB1_TILE_INTERFACE_SEND_EVENT = 485
SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 486
SC_DB1_TILE_INTERFACE_SEND_SOP = 487
SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 488
SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 489
SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 490
SC_BACKEND_PRIM_FIFO_FULL = 491
SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 492
SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 493
SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 494
SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 495
SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 496
SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 497
SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 498
SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 499
SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 500
SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 501
SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 502
SC_STALLED_BY_DB0_TILEFIFO = 503
SC_DB0_QUAD_INTF_SEND = 504
SC_DB0_QUAD_INTF_BUSY = 505
SC_DB0_QUAD_INTF_STALLED_BY_DB = 506
SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 507
SC_DB0_QUAD_INTF_IDLE = 508
SC_DB1_QUAD_INTF_SEND = 509
SC_STALLED_BY_DB1_TILEFIFO = 510
SC_DB1_QUAD_INTF_BUSY = 511
SC_DB1_QUAD_INTF_STALLED_BY_DB = 512
SC_DB1_QUAD_INTF_CREDIT_AT_MAX = 513
SC_DB1_QUAD_INTF_IDLE = 514
SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 515
SC_PKR_WAVE_BREAK_FULL_TILE = 516
SC_FSR_WALKED = 517
SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 518
SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 519
SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 520
SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 521
SC_DB0_TILE_MASK_FIFO_FULL = 522
SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL = 523
SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 524
SC_DB1_TILE_MASK_FIFO_FULL = 525
SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 526
SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 527
SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 528
SC_PS_PM_PFF_PW_FULL = 529
SC_PS_PM_ZFF_PW_FULL = 530
SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 531
SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H = 532
SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 533
SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 534
SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 535
SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 536
SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 537
SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 538
SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H = 539
SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 540
SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 541
SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 542
SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 543
SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 544
SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 545
SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 546
SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H = 547
SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 548
SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 549
SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 550
SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 551
SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 552
SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 553
SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 554
SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 555
SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 556
SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 557
SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 558
SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 559
SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 560
SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 561
SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 562
SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 563
SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 564
SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 565
SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 566
SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 567
SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE = 568
SC_PBB_RESERVED = 569
SC_BM_BE0_STALLED = 570
SC_BM_BE1_STALLED = 571
SC_BM_BE2_STALLED = 572
SC_BM_BE3_STALLED = 573
SC_BM_MULTI_ACCUM_1_BE_STALLED = 574
SC_BM_MULTI_ACCUM_2_BE_STALLED = 575
SC_BM_MULTI_ACCUM_3_BE_STALLED = 576
SC_BM_MULTI_ACCUM_4_BE_STALLED = 577
SC_PERFCNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'ScMap'
ScMap__enumvalues = {
0: 'RASTER_CONFIG_SC_MAP_0',
1: 'RASTER_CONFIG_SC_MAP_1',
2: 'RASTER_CONFIG_SC_MAP_2',
3: 'RASTER_CONFIG_SC_MAP_3',
}
RASTER_CONFIG_SC_MAP_0 = 0
RASTER_CONFIG_SC_MAP_1 = 1
RASTER_CONFIG_SC_MAP_2 = 2
RASTER_CONFIG_SC_MAP_3 = 3
ScMap = ctypes.c_uint32 # enum
# values for enumeration 'ScUncertaintyRegionMode'
ScUncertaintyRegionMode__enumvalues = {
0: 'SC_HALF_LSB',
1: 'SC_LSB_ONE_SIDED',
2: 'SC_LSB_TWO_SIDED',
}
SC_HALF_LSB = 0
SC_LSB_ONE_SIDED = 1
SC_LSB_TWO_SIDED = 2
ScUncertaintyRegionMode = ctypes.c_uint32 # enum
# values for enumeration 'ScUncertaintyRegionMult'
ScUncertaintyRegionMult__enumvalues = {
0: 'SC_UR_1X',
1: 'SC_UR_2X',
2: 'SC_UR_4X',
3: 'SC_UR_8X',
}
SC_UR_1X = 0
SC_UR_2X = 1
SC_UR_4X = 2
SC_UR_8X = 3
ScUncertaintyRegionMult = ctypes.c_uint32 # enum
# values for enumeration 'ScXsel'
ScXsel__enumvalues = {
0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3
ScXsel = ctypes.c_uint32 # enum
# values for enumeration 'ScYsel'
ScYsel__enumvalues = {
0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3
ScYsel = ctypes.c_uint32 # enum
# values for enumeration 'SeMap'
SeMap__enumvalues = {
0: 'RASTER_CONFIG_SE_MAP_0',
1: 'RASTER_CONFIG_SE_MAP_1',
2: 'RASTER_CONFIG_SE_MAP_2',
3: 'RASTER_CONFIG_SE_MAP_3',
}
RASTER_CONFIG_SE_MAP_0 = 0
RASTER_CONFIG_SE_MAP_1 = 1
RASTER_CONFIG_SE_MAP_2 = 2
RASTER_CONFIG_SE_MAP_3 = 3
SeMap = ctypes.c_uint32 # enum
# values for enumeration 'SePairMap'
SePairMap__enumvalues = {
0: 'RASTER_CONFIG_SE_PAIR_MAP_0',
1: 'RASTER_CONFIG_SE_PAIR_MAP_1',
2: 'RASTER_CONFIG_SE_PAIR_MAP_2',
3: 'RASTER_CONFIG_SE_PAIR_MAP_3',
}
RASTER_CONFIG_SE_PAIR_MAP_0 = 0
RASTER_CONFIG_SE_PAIR_MAP_1 = 1
RASTER_CONFIG_SE_PAIR_MAP_2 = 2
RASTER_CONFIG_SE_PAIR_MAP_3 = 3
SePairMap = ctypes.c_uint32 # enum
# values for enumeration 'SePairXsel'
SePairXsel__enumvalues = {
0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3
SePairXsel = ctypes.c_uint32 # enum
# values for enumeration 'SePairYsel'
SePairYsel__enumvalues = {
0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3
SePairYsel = ctypes.c_uint32 # enum
# values for enumeration 'SeXsel'
SeXsel__enumvalues = {
0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3
SeXsel = ctypes.c_uint32 # enum
# values for enumeration 'SeYsel'
SeYsel__enumvalues = {
0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE',
1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE',
2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE',
3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE',
}
RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0
RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1
RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2
RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3
SeYsel = ctypes.c_uint32 # enum
# values for enumeration 'VRSCombinerModeSC'
VRSCombinerModeSC__enumvalues = {
0: 'SC_VRS_COMB_MODE_PASSTHRU',
1: 'SC_VRS_COMB_MODE_OVERRIDE',
2: 'SC_VRS_COMB_MODE_MIN',
3: 'SC_VRS_COMB_MODE_MAX',
4: 'SC_VRS_COMB_MODE_SATURATE',
}
SC_VRS_COMB_MODE_PASSTHRU = 0
SC_VRS_COMB_MODE_OVERRIDE = 1
SC_VRS_COMB_MODE_MIN = 2
SC_VRS_COMB_MODE_MAX = 3
SC_VRS_COMB_MODE_SATURATE = 4
VRSCombinerModeSC = ctypes.c_uint32 # enum
# values for enumeration 'VRSrate'
VRSrate__enumvalues = {
0: 'VRS_SHADING_RATE_1X1',
1: 'VRS_SHADING_RATE_1X2',
2: 'VRS_SHADING_RATE_UNDEFINED0',
3: 'VRS_SHADING_RATE_UNDEFINED1',
4: 'VRS_SHADING_RATE_2X1',
5: 'VRS_SHADING_RATE_2X2',
6: 'VRS_SHADING_RATE_2X4',
7: 'VRS_SHADING_RATE_UNDEFINED2',
8: 'VRS_SHADING_RATE_UNDEFINED3',
9: 'VRS_SHADING_RATE_4X2',
10: 'VRS_SHADING_RATE_4X4',
11: 'VRS_SHADING_RATE_UNDEFINED4',
12: 'VRS_SHADING_RATE_16X_SSAA',
13: 'VRS_SHADING_RATE_8X_SSAA',
14: 'VRS_SHADING_RATE_4X_SSAA',
15: 'VRS_SHADING_RATE_2X_SSAA',
}
VRS_SHADING_RATE_1X1 = 0
VRS_SHADING_RATE_1X2 = 1
VRS_SHADING_RATE_UNDEFINED0 = 2
VRS_SHADING_RATE_UNDEFINED1 = 3
VRS_SHADING_RATE_2X1 = 4
VRS_SHADING_RATE_2X2 = 5
VRS_SHADING_RATE_2X4 = 6
VRS_SHADING_RATE_UNDEFINED2 = 7
VRS_SHADING_RATE_UNDEFINED3 = 8
VRS_SHADING_RATE_4X2 = 9
VRS_SHADING_RATE_4X4 = 10
VRS_SHADING_RATE_UNDEFINED4 = 11
VRS_SHADING_RATE_16X_SSAA = 12
VRS_SHADING_RATE_8X_SSAA = 13
VRS_SHADING_RATE_4X_SSAA = 14
VRS_SHADING_RATE_2X_SSAA = 15
VRSrate = ctypes.c_uint32 # enum
# values for enumeration 'TC_EA_CID'
TC_EA_CID__enumvalues = {
0: 'TC_EA_CID_RT',
1: 'TC_EA_CID_FMASK',
2: 'TC_EA_CID_DCC',
3: 'TC_EA_CID_TCPMETA',
4: 'TC_EA_CID_Z',
5: 'TC_EA_CID_STENCIL',
6: 'TC_EA_CID_HTILE',
7: 'TC_EA_CID_MISC',
8: 'TC_EA_CID_TCP',
9: 'TC_EA_CID_SQC',
10: 'TC_EA_CID_CPF',
11: 'TC_EA_CID_CPG',
12: 'TC_EA_CID_IA',
13: 'TC_EA_CID_WD',
14: 'TC_EA_CID_PA',
15: 'TC_EA_CID_UTCL2_TPI',
}
TC_EA_CID_RT = 0
TC_EA_CID_FMASK = 1
TC_EA_CID_DCC = 2
TC_EA_CID_TCPMETA = 3
TC_EA_CID_Z = 4
TC_EA_CID_STENCIL = 5
TC_EA_CID_HTILE = 6
TC_EA_CID_MISC = 7
TC_EA_CID_TCP = 8
TC_EA_CID_SQC = 9
TC_EA_CID_CPF = 10
TC_EA_CID_CPG = 11
TC_EA_CID_IA = 12
TC_EA_CID_WD = 13
TC_EA_CID_PA = 14
TC_EA_CID_UTCL2_TPI = 15
TC_EA_CID = ctypes.c_uint32 # enum
# values for enumeration 'TC_NACKS'
TC_NACKS__enumvalues = {
0: 'TC_NACK_NO_FAULT',
1: 'TC_NACK_PAGE_FAULT',
2: 'TC_NACK_PROTECTION_FAULT',
3: 'TC_NACK_DATA_ERROR',
}
TC_NACK_NO_FAULT = 0
TC_NACK_PAGE_FAULT = 1
TC_NACK_PROTECTION_FAULT = 2
TC_NACK_DATA_ERROR = 3
TC_NACKS = ctypes.c_uint32 # enum
# values for enumeration 'TC_OP'
TC_OP__enumvalues = {
0: 'TC_OP_READ',
1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32',
2: 'TC_OP_ATOMIC_FMIN_RTN_32',
3: 'TC_OP_ATOMIC_FMAX_RTN_32',
4: 'TC_OP_RESERVED_FOP_RTN_32_0',
5: 'TC_OP_RESERVED_FADD_RTN_32',
6: 'TC_OP_RESERVED_FOP_RTN_32_2',
7: 'TC_OP_ATOMIC_SWAP_RTN_32',
8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32',
9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32',
10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32',
11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32',
12: 'TC_OP_PROBE_FILTER',
13: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32',
14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2',
15: 'TC_OP_ATOMIC_ADD_RTN_32',
16: 'TC_OP_ATOMIC_SUB_RTN_32',
17: 'TC_OP_ATOMIC_SMIN_RTN_32',
18: 'TC_OP_ATOMIC_UMIN_RTN_32',
19: 'TC_OP_ATOMIC_SMAX_RTN_32',
20: 'TC_OP_ATOMIC_UMAX_RTN_32',
21: 'TC_OP_ATOMIC_AND_RTN_32',
22: 'TC_OP_ATOMIC_OR_RTN_32',
23: 'TC_OP_ATOMIC_XOR_RTN_32',
24: 'TC_OP_ATOMIC_INC_RTN_32',
25: 'TC_OP_ATOMIC_DEC_RTN_32',
26: 'TC_OP_WBINVL1_VOL',
27: 'TC_OP_WBINVL1_SD',
28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0',
29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1',
30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2',
31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3',
32: 'TC_OP_WRITE',
33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64',
34: 'TC_OP_ATOMIC_FMIN_RTN_64',
35: 'TC_OP_ATOMIC_FMAX_RTN_64',
36: 'TC_OP_RESERVED_FOP_RTN_64_0',
37: 'TC_OP_RESERVED_FOP_RTN_64_1',
38: 'TC_OP_RESERVED_FOP_RTN_64_2',
39: 'TC_OP_ATOMIC_SWAP_RTN_64',
40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64',
41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64',
42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64',
43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64',
44: 'TC_OP_WBINVL2_SD',
45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0',
46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1',
47: 'TC_OP_ATOMIC_ADD_RTN_64',
48: 'TC_OP_ATOMIC_SUB_RTN_64',
49: 'TC_OP_ATOMIC_SMIN_RTN_64',
50: 'TC_OP_ATOMIC_UMIN_RTN_64',
51: 'TC_OP_ATOMIC_SMAX_RTN_64',
52: 'TC_OP_ATOMIC_UMAX_RTN_64',
53: 'TC_OP_ATOMIC_AND_RTN_64',
54: 'TC_OP_ATOMIC_OR_RTN_64',
55: 'TC_OP_ATOMIC_XOR_RTN_64',
56: 'TC_OP_ATOMIC_INC_RTN_64',
57: 'TC_OP_ATOMIC_DEC_RTN_64',
58: 'TC_OP_WBL2_NC',
59: 'TC_OP_WBL2_WC',
60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1',
61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2',
62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3',
63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4',
64: 'TC_OP_WBINVL1',
65: 'TC_OP_ATOMIC_FCMPSWAP_32',
66: 'TC_OP_ATOMIC_FMIN_32',
67: 'TC_OP_ATOMIC_FMAX_32',
68: 'TC_OP_RESERVED_FOP_32_0',
69: 'TC_OP_RESERVED_FADD_32',
70: 'TC_OP_RESERVED_FOP_32_2',
71: 'TC_OP_ATOMIC_SWAP_32',
72: 'TC_OP_ATOMIC_CMPSWAP_32',
73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32',
74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32',
75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32',
76: 'TC_OP_INV_METADATA',
77: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32',
78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2',
79: 'TC_OP_ATOMIC_ADD_32',
80: 'TC_OP_ATOMIC_SUB_32',
81: 'TC_OP_ATOMIC_SMIN_32',
82: 'TC_OP_ATOMIC_UMIN_32',
83: 'TC_OP_ATOMIC_SMAX_32',
84: 'TC_OP_ATOMIC_UMAX_32',
85: 'TC_OP_ATOMIC_AND_32',
86: 'TC_OP_ATOMIC_OR_32',
87: 'TC_OP_ATOMIC_XOR_32',
88: 'TC_OP_ATOMIC_INC_32',
89: 'TC_OP_ATOMIC_DEC_32',
90: 'TC_OP_INVL2_NC',
91: 'TC_OP_NOP_RTN0',
92: 'TC_OP_RESERVED_NON_FLOAT_32_1',
93: 'TC_OP_RESERVED_NON_FLOAT_32_2',
94: 'TC_OP_RESERVED_NON_FLOAT_32_3',
95: 'TC_OP_RESERVED_NON_FLOAT_32_4',
96: 'TC_OP_WBINVL2',
97: 'TC_OP_ATOMIC_FCMPSWAP_64',
98: 'TC_OP_ATOMIC_FMIN_64',
99: 'TC_OP_ATOMIC_FMAX_64',
100: 'TC_OP_RESERVED_FOP_64_0',
101: 'TC_OP_RESERVED_FOP_64_1',
102: 'TC_OP_RESERVED_FOP_64_2',
103: 'TC_OP_ATOMIC_SWAP_64',
104: 'TC_OP_ATOMIC_CMPSWAP_64',
105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64',
106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64',
107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64',
108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0',
109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1',
110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2',
111: 'TC_OP_ATOMIC_ADD_64',
112: 'TC_OP_ATOMIC_SUB_64',
113: 'TC_OP_ATOMIC_SMIN_64',
114: 'TC_OP_ATOMIC_UMIN_64',
115: 'TC_OP_ATOMIC_SMAX_64',
116: 'TC_OP_ATOMIC_UMAX_64',
117: 'TC_OP_ATOMIC_AND_64',
118: 'TC_OP_ATOMIC_OR_64',
119: 'TC_OP_ATOMIC_XOR_64',
120: 'TC_OP_ATOMIC_INC_64',
121: 'TC_OP_ATOMIC_DEC_64',
122: 'TC_OP_WBINVL2_NC',
123: 'TC_OP_NOP_ACK',
124: 'TC_OP_RESERVED_NON_FLOAT_64_1',
125: 'TC_OP_RESERVED_NON_FLOAT_64_2',
126: 'TC_OP_RESERVED_NON_FLOAT_64_3',
127: 'TC_OP_RESERVED_NON_FLOAT_64_4',
}
TC_OP_READ = 0
TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1
TC_OP_ATOMIC_FMIN_RTN_32 = 2
TC_OP_ATOMIC_FMAX_RTN_32 = 3
TC_OP_RESERVED_FOP_RTN_32_0 = 4
TC_OP_RESERVED_FADD_RTN_32 = 5
TC_OP_RESERVED_FOP_RTN_32_2 = 6
TC_OP_ATOMIC_SWAP_RTN_32 = 7
TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11
TC_OP_PROBE_FILTER = 12
TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14
TC_OP_ATOMIC_ADD_RTN_32 = 15
TC_OP_ATOMIC_SUB_RTN_32 = 16
TC_OP_ATOMIC_SMIN_RTN_32 = 17
TC_OP_ATOMIC_UMIN_RTN_32 = 18
TC_OP_ATOMIC_SMAX_RTN_32 = 19
TC_OP_ATOMIC_UMAX_RTN_32 = 20
TC_OP_ATOMIC_AND_RTN_32 = 21
TC_OP_ATOMIC_OR_RTN_32 = 22
TC_OP_ATOMIC_XOR_RTN_32 = 23
TC_OP_ATOMIC_INC_RTN_32 = 24
TC_OP_ATOMIC_DEC_RTN_32 = 25
TC_OP_WBINVL1_VOL = 26
TC_OP_WBINVL1_SD = 27
TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28
TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29
TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30
TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31
TC_OP_WRITE = 32
TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33
TC_OP_ATOMIC_FMIN_RTN_64 = 34
TC_OP_ATOMIC_FMAX_RTN_64 = 35
TC_OP_RESERVED_FOP_RTN_64_0 = 36
TC_OP_RESERVED_FOP_RTN_64_1 = 37
TC_OP_RESERVED_FOP_RTN_64_2 = 38
TC_OP_ATOMIC_SWAP_RTN_64 = 39
TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43
TC_OP_WBINVL2_SD = 44
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46
TC_OP_ATOMIC_ADD_RTN_64 = 47
TC_OP_ATOMIC_SUB_RTN_64 = 48
TC_OP_ATOMIC_SMIN_RTN_64 = 49
TC_OP_ATOMIC_UMIN_RTN_64 = 50
TC_OP_ATOMIC_SMAX_RTN_64 = 51
TC_OP_ATOMIC_UMAX_RTN_64 = 52
TC_OP_ATOMIC_AND_RTN_64 = 53
TC_OP_ATOMIC_OR_RTN_64 = 54
TC_OP_ATOMIC_XOR_RTN_64 = 55
TC_OP_ATOMIC_INC_RTN_64 = 56
TC_OP_ATOMIC_DEC_RTN_64 = 57
TC_OP_WBL2_NC = 58
TC_OP_WBL2_WC = 59
TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60
TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61
TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62
TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63
TC_OP_WBINVL1 = 64
TC_OP_ATOMIC_FCMPSWAP_32 = 65
TC_OP_ATOMIC_FMIN_32 = 66
TC_OP_ATOMIC_FMAX_32 = 67
TC_OP_RESERVED_FOP_32_0 = 68
TC_OP_RESERVED_FADD_32 = 69
TC_OP_RESERVED_FOP_32_2 = 70
TC_OP_ATOMIC_SWAP_32 = 71
TC_OP_ATOMIC_CMPSWAP_32 = 72
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75
TC_OP_INV_METADATA = 76
TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77
TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78
TC_OP_ATOMIC_ADD_32 = 79
TC_OP_ATOMIC_SUB_32 = 80
TC_OP_ATOMIC_SMIN_32 = 81
TC_OP_ATOMIC_UMIN_32 = 82
TC_OP_ATOMIC_SMAX_32 = 83
TC_OP_ATOMIC_UMAX_32 = 84
TC_OP_ATOMIC_AND_32 = 85
TC_OP_ATOMIC_OR_32 = 86
TC_OP_ATOMIC_XOR_32 = 87
TC_OP_ATOMIC_INC_32 = 88
TC_OP_ATOMIC_DEC_32 = 89
TC_OP_INVL2_NC = 90
TC_OP_NOP_RTN0 = 91
TC_OP_RESERVED_NON_FLOAT_32_1 = 92
TC_OP_RESERVED_NON_FLOAT_32_2 = 93
TC_OP_RESERVED_NON_FLOAT_32_3 = 94
TC_OP_RESERVED_NON_FLOAT_32_4 = 95
TC_OP_WBINVL2 = 96
TC_OP_ATOMIC_FCMPSWAP_64 = 97
TC_OP_ATOMIC_FMIN_64 = 98
TC_OP_ATOMIC_FMAX_64 = 99
TC_OP_RESERVED_FOP_64_0 = 100
TC_OP_RESERVED_FOP_64_1 = 101
TC_OP_RESERVED_FOP_64_2 = 102
TC_OP_ATOMIC_SWAP_64 = 103
TC_OP_ATOMIC_CMPSWAP_64 = 104
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110
TC_OP_ATOMIC_ADD_64 = 111
TC_OP_ATOMIC_SUB_64 = 112
TC_OP_ATOMIC_SMIN_64 = 113
TC_OP_ATOMIC_UMIN_64 = 114
TC_OP_ATOMIC_SMAX_64 = 115
TC_OP_ATOMIC_UMAX_64 = 116
TC_OP_ATOMIC_AND_64 = 117
TC_OP_ATOMIC_OR_64 = 118
TC_OP_ATOMIC_XOR_64 = 119
TC_OP_ATOMIC_INC_64 = 120
TC_OP_ATOMIC_DEC_64 = 121
TC_OP_WBINVL2_NC = 122
TC_OP_NOP_ACK = 123
TC_OP_RESERVED_NON_FLOAT_64_1 = 124
TC_OP_RESERVED_NON_FLOAT_64_2 = 125
TC_OP_RESERVED_NON_FLOAT_64_3 = 126
TC_OP_RESERVED_NON_FLOAT_64_4 = 127
TC_OP = ctypes.c_uint32 # enum
# values for enumeration 'TC_OP_MASKS'
TC_OP_MASKS__enumvalues = {
8: 'TC_OP_MASK_FLUSH_DENROM',
32: 'TC_OP_MASK_64',
64: 'TC_OP_MASK_NO_RTN',
}
TC_OP_MASK_FLUSH_DENROM = 8
TC_OP_MASK_64 = 32
TC_OP_MASK_NO_RTN = 64
TC_OP_MASKS = ctypes.c_uint32 # enum
# values for enumeration 'GL2_EA_CID'
GL2_EA_CID__enumvalues = {
0: 'GL2_EA_CID_CLIENT',
1: 'GL2_EA_CID_SDMA',
2: 'GL2_EA_CID_RLC',
3: 'GL2_EA_CID_SQC',
4: 'GL2_EA_CID_CP',
5: 'GL2_EA_CID_CPDMA',
6: 'GL2_EA_CID_UTCL2',
7: 'GL2_EA_CID_RT',
8: 'GL2_EA_CID_FMASK',
9: 'GL2_EA_CID_DCC',
10: 'GL2_EA_CID_Z_STENCIL',
11: 'GL2_EA_CID_ZPCPSD',
12: 'GL2_EA_CID_HTILE',
13: 'GL2_EA_CID_MES',
15: 'GL2_EA_CID_TCPMETA',
}
GL2_EA_CID_CLIENT = 0
GL2_EA_CID_SDMA = 1
GL2_EA_CID_RLC = 2
GL2_EA_CID_SQC = 3
GL2_EA_CID_CP = 4
GL2_EA_CID_CPDMA = 5
GL2_EA_CID_UTCL2 = 6
GL2_EA_CID_RT = 7
GL2_EA_CID_FMASK = 8
GL2_EA_CID_DCC = 9
GL2_EA_CID_Z_STENCIL = 10
GL2_EA_CID_ZPCPSD = 11
GL2_EA_CID_HTILE = 12
GL2_EA_CID_MES = 13
GL2_EA_CID_TCPMETA = 15
GL2_EA_CID = ctypes.c_uint32 # enum
# values for enumeration 'GL2_NACKS'
GL2_NACKS__enumvalues = {
0: 'GL2_NACK_NO_FAULT',
1: 'GL2_NACK_PAGE_FAULT',
2: 'GL2_NACK_PROTECTION_FAULT',
3: 'GL2_NACK_DATA_ERROR',
}
GL2_NACK_NO_FAULT = 0
GL2_NACK_PAGE_FAULT = 1
GL2_NACK_PROTECTION_FAULT = 2
GL2_NACK_DATA_ERROR = 3
GL2_NACKS = ctypes.c_uint32 # enum
# values for enumeration 'GL2_OP'
GL2_OP__enumvalues = {
0: 'GL2_OP_READ',
1: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32',
2: 'GL2_OP_ATOMIC_FMIN_RTN_32',
3: 'GL2_OP_ATOMIC_FMAX_RTN_32',
7: 'GL2_OP_ATOMIC_SWAP_RTN_32',
8: 'GL2_OP_ATOMIC_CMPSWAP_RTN_32',
9: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32',
10: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32',
11: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32',
12: 'GL2_OP_PROBE_FILTER',
13: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32',
14: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2',
15: 'GL2_OP_ATOMIC_ADD_RTN_32',
16: 'GL2_OP_ATOMIC_SUB_RTN_32',
17: 'GL2_OP_ATOMIC_SMIN_RTN_32',
18: 'GL2_OP_ATOMIC_UMIN_RTN_32',
19: 'GL2_OP_ATOMIC_SMAX_RTN_32',
20: 'GL2_OP_ATOMIC_UMAX_RTN_32',
21: 'GL2_OP_ATOMIC_AND_RTN_32',
22: 'GL2_OP_ATOMIC_OR_RTN_32',
23: 'GL2_OP_ATOMIC_XOR_RTN_32',
24: 'GL2_OP_ATOMIC_INC_RTN_32',
25: 'GL2_OP_ATOMIC_DEC_RTN_32',
26: 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32',
32: 'GL2_OP_WRITE',
33: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64',
34: 'GL2_OP_ATOMIC_FMIN_RTN_64',
35: 'GL2_OP_ATOMIC_FMAX_RTN_64',
39: 'GL2_OP_ATOMIC_SWAP_RTN_64',
40: 'GL2_OP_ATOMIC_CMPSWAP_RTN_64',
41: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64',
42: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64',
43: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64',
47: 'GL2_OP_ATOMIC_ADD_RTN_64',
48: 'GL2_OP_ATOMIC_SUB_RTN_64',
49: 'GL2_OP_ATOMIC_SMIN_RTN_64',
50: 'GL2_OP_ATOMIC_UMIN_RTN_64',
51: 'GL2_OP_ATOMIC_SMAX_RTN_64',
52: 'GL2_OP_ATOMIC_UMAX_RTN_64',
53: 'GL2_OP_ATOMIC_AND_RTN_64',
54: 'GL2_OP_ATOMIC_OR_RTN_64',
55: 'GL2_OP_ATOMIC_XOR_RTN_64',
56: 'GL2_OP_ATOMIC_INC_RTN_64',
57: 'GL2_OP_ATOMIC_DEC_RTN_64',
64: 'GL2_OP_GL1_INV',
65: 'GL2_OP_ATOMIC_FCMPSWAP_32',
66: 'GL2_OP_ATOMIC_FMIN_32',
67: 'GL2_OP_ATOMIC_FMAX_32',
71: 'GL2_OP_ATOMIC_SWAP_32',
72: 'GL2_OP_ATOMIC_CMPSWAP_32',
73: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32',
74: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32',
75: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32',
76: 'GL2_OP_ATOMIC_UMIN_8',
77: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32',
79: 'GL2_OP_ATOMIC_ADD_32',
80: 'GL2_OP_ATOMIC_SUB_32',
81: 'GL2_OP_ATOMIC_SMIN_32',
82: 'GL2_OP_ATOMIC_UMIN_32',
83: 'GL2_OP_ATOMIC_SMAX_32',
84: 'GL2_OP_ATOMIC_UMAX_32',
85: 'GL2_OP_ATOMIC_AND_32',
86: 'GL2_OP_ATOMIC_OR_32',
87: 'GL2_OP_ATOMIC_XOR_32',
88: 'GL2_OP_ATOMIC_INC_32',
89: 'GL2_OP_ATOMIC_DEC_32',
91: 'GL2_OP_NOP_RTN0',
97: 'GL2_OP_ATOMIC_FCMPSWAP_64',
98: 'GL2_OP_ATOMIC_FMIN_64',
99: 'GL2_OP_ATOMIC_FMAX_64',
103: 'GL2_OP_ATOMIC_SWAP_64',
104: 'GL2_OP_ATOMIC_CMPSWAP_64',
105: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64',
106: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64',
107: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64',
111: 'GL2_OP_ATOMIC_ADD_64',
112: 'GL2_OP_ATOMIC_SUB_64',
113: 'GL2_OP_ATOMIC_SMIN_64',
114: 'GL2_OP_ATOMIC_UMIN_64',
115: 'GL2_OP_ATOMIC_SMAX_64',
116: 'GL2_OP_ATOMIC_UMAX_64',
117: 'GL2_OP_ATOMIC_AND_64',
118: 'GL2_OP_ATOMIC_OR_64',
119: 'GL2_OP_ATOMIC_XOR_64',
120: 'GL2_OP_ATOMIC_INC_64',
121: 'GL2_OP_ATOMIC_DEC_64',
122: 'GL2_OP_ATOMIC_UMAX_8',
123: 'GL2_OP_NOP_ACK',
}
GL2_OP_READ = 0
GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 1
GL2_OP_ATOMIC_FMIN_RTN_32 = 2
GL2_OP_ATOMIC_FMAX_RTN_32 = 3
GL2_OP_ATOMIC_SWAP_RTN_32 = 7
GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 8
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11
GL2_OP_PROBE_FILTER = 12
GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13
GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14
GL2_OP_ATOMIC_ADD_RTN_32 = 15
GL2_OP_ATOMIC_SUB_RTN_32 = 16
GL2_OP_ATOMIC_SMIN_RTN_32 = 17
GL2_OP_ATOMIC_UMIN_RTN_32 = 18
GL2_OP_ATOMIC_SMAX_RTN_32 = 19
GL2_OP_ATOMIC_UMAX_RTN_32 = 20
GL2_OP_ATOMIC_AND_RTN_32 = 21
GL2_OP_ATOMIC_OR_RTN_32 = 22
GL2_OP_ATOMIC_XOR_RTN_32 = 23
GL2_OP_ATOMIC_INC_RTN_32 = 24
GL2_OP_ATOMIC_DEC_RTN_32 = 25
GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 26
GL2_OP_WRITE = 32
GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 33
GL2_OP_ATOMIC_FMIN_RTN_64 = 34
GL2_OP_ATOMIC_FMAX_RTN_64 = 35
GL2_OP_ATOMIC_SWAP_RTN_64 = 39
GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 40
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43
GL2_OP_ATOMIC_ADD_RTN_64 = 47
GL2_OP_ATOMIC_SUB_RTN_64 = 48
GL2_OP_ATOMIC_SMIN_RTN_64 = 49
GL2_OP_ATOMIC_UMIN_RTN_64 = 50
GL2_OP_ATOMIC_SMAX_RTN_64 = 51
GL2_OP_ATOMIC_UMAX_RTN_64 = 52
GL2_OP_ATOMIC_AND_RTN_64 = 53
GL2_OP_ATOMIC_OR_RTN_64 = 54
GL2_OP_ATOMIC_XOR_RTN_64 = 55
GL2_OP_ATOMIC_INC_RTN_64 = 56
GL2_OP_ATOMIC_DEC_RTN_64 = 57
GL2_OP_GL1_INV = 64
GL2_OP_ATOMIC_FCMPSWAP_32 = 65
GL2_OP_ATOMIC_FMIN_32 = 66
GL2_OP_ATOMIC_FMAX_32 = 67
GL2_OP_ATOMIC_SWAP_32 = 71
GL2_OP_ATOMIC_CMPSWAP_32 = 72
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75
GL2_OP_ATOMIC_UMIN_8 = 76
GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77
GL2_OP_ATOMIC_ADD_32 = 79
GL2_OP_ATOMIC_SUB_32 = 80
GL2_OP_ATOMIC_SMIN_32 = 81
GL2_OP_ATOMIC_UMIN_32 = 82
GL2_OP_ATOMIC_SMAX_32 = 83
GL2_OP_ATOMIC_UMAX_32 = 84
GL2_OP_ATOMIC_AND_32 = 85
GL2_OP_ATOMIC_OR_32 = 86
GL2_OP_ATOMIC_XOR_32 = 87
GL2_OP_ATOMIC_INC_32 = 88
GL2_OP_ATOMIC_DEC_32 = 89
GL2_OP_NOP_RTN0 = 91
GL2_OP_ATOMIC_FCMPSWAP_64 = 97
GL2_OP_ATOMIC_FMIN_64 = 98
GL2_OP_ATOMIC_FMAX_64 = 99
GL2_OP_ATOMIC_SWAP_64 = 103
GL2_OP_ATOMIC_CMPSWAP_64 = 104
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107
GL2_OP_ATOMIC_ADD_64 = 111
GL2_OP_ATOMIC_SUB_64 = 112
GL2_OP_ATOMIC_SMIN_64 = 113
GL2_OP_ATOMIC_UMIN_64 = 114
GL2_OP_ATOMIC_SMAX_64 = 115
GL2_OP_ATOMIC_UMAX_64 = 116
GL2_OP_ATOMIC_AND_64 = 117
GL2_OP_ATOMIC_OR_64 = 118
GL2_OP_ATOMIC_XOR_64 = 119
GL2_OP_ATOMIC_INC_64 = 120
GL2_OP_ATOMIC_DEC_64 = 121
GL2_OP_ATOMIC_UMAX_8 = 122
GL2_OP_NOP_ACK = 123
GL2_OP = ctypes.c_uint32 # enum
# values for enumeration 'GL2_OP_MASKS'
GL2_OP_MASKS__enumvalues = {
8: 'GL2_OP_MASK_FLUSH_DENROM',
32: 'GL2_OP_MASK_64',
64: 'GL2_OP_MASK_NO_RTN',
}
GL2_OP_MASK_FLUSH_DENROM = 8
GL2_OP_MASK_64 = 32
GL2_OP_MASK_NO_RTN = 64
GL2_OP_MASKS = ctypes.c_uint32 # enum
# values for enumeration 'RLC_DOORBELL_MODE'
RLC_DOORBELL_MODE__enumvalues = {
0: 'RLC_DOORBELL_MODE_DISABLE',
1: 'RLC_DOORBELL_MODE_ENABLE',
2: 'RLC_DOORBELL_MODE_ENABLE_PF',
3: 'RLC_DOORBELL_MODE_ENABLE_PF_VF',
}
RLC_DOORBELL_MODE_DISABLE = 0
RLC_DOORBELL_MODE_ENABLE = 1
RLC_DOORBELL_MODE_ENABLE_PF = 2
RLC_DOORBELL_MODE_ENABLE_PF_VF = 3
RLC_DOORBELL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'RLC_PERFCOUNTER_SEL'
RLC_PERFCOUNTER_SEL__enumvalues = {
0: 'RLC_PERF_SEL_POWER_FEATURE_0',
1: 'RLC_PERF_SEL_POWER_FEATURE_1',
2: 'RLC_PERF_SEL_CP_INTERRUPT',
3: 'RLC_PERF_SEL_GRBM_INTERRUPT',
4: 'RLC_PERF_SEL_SPM_INTERRUPT',
5: 'RLC_PERF_SEL_IH_INTERRUPT',
6: 'RLC_PERF_SEL_SERDES_COMMAND_WRITE',
}
RLC_PERF_SEL_POWER_FEATURE_0 = 0
RLC_PERF_SEL_POWER_FEATURE_1 = 1
RLC_PERF_SEL_CP_INTERRUPT = 2
RLC_PERF_SEL_GRBM_INTERRUPT = 3
RLC_PERF_SEL_SPM_INTERRUPT = 4
RLC_PERF_SEL_IH_INTERRUPT = 5
RLC_PERF_SEL_SERDES_COMMAND_WRITE = 6
RLC_PERFCOUNTER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'RLC_PERFMON_STATE'
RLC_PERFMON_STATE__enumvalues = {
0: 'RLC_PERFMON_STATE_RESET',
1: 'RLC_PERFMON_STATE_ENABLE',
2: 'RLC_PERFMON_STATE_DISABLE',
3: 'RLC_PERFMON_STATE_RESERVED_3',
4: 'RLC_PERFMON_STATE_RESERVED_4',
5: 'RLC_PERFMON_STATE_RESERVED_5',
6: 'RLC_PERFMON_STATE_RESERVED_6',
7: 'RLC_PERFMON_STATE_ROLLOVER',
}
RLC_PERFMON_STATE_RESET = 0
RLC_PERFMON_STATE_ENABLE = 1
RLC_PERFMON_STATE_DISABLE = 2
RLC_PERFMON_STATE_RESERVED_3 = 3
RLC_PERFMON_STATE_RESERVED_4 = 4
RLC_PERFMON_STATE_RESERVED_5 = 5
RLC_PERFMON_STATE_RESERVED_6 = 6
RLC_PERFMON_STATE_ROLLOVER = 7
RLC_PERFMON_STATE = ctypes.c_uint32 # enum
# values for enumeration 'RSPM_CMD'
RSPM_CMD__enumvalues = {
0: 'RSPM_CMD_INVALID',
1: 'RSPM_CMD_IDLE',
2: 'RSPM_CMD_CALIBRATE',
3: 'RSPM_CMD_SPM_RESET',
4: 'RSPM_CMD_SPM_START',
5: 'RSPM_CMD_SPM_STOP',
6: 'RSPM_CMD_PERF_RESET',
7: 'RSPM_CMD_PERF_SAMPLE',
8: 'RSPM_CMD_PROF_START',
9: 'RSPM_CMD_PROF_STOP',
10: 'RSPM_CMD_FORCE_SAMPLE',
}
RSPM_CMD_INVALID = 0
RSPM_CMD_IDLE = 1
RSPM_CMD_CALIBRATE = 2
RSPM_CMD_SPM_RESET = 3
RSPM_CMD_SPM_START = 4
RSPM_CMD_SPM_STOP = 5
RSPM_CMD_PERF_RESET = 6
RSPM_CMD_PERF_SAMPLE = 7
RSPM_CMD_PROF_START = 8
RSPM_CMD_PROF_STOP = 9
RSPM_CMD_FORCE_SAMPLE = 10
RSPM_CMD = ctypes.c_uint32 # enum
# values for enumeration 'CLKGATE_BASE_MODE'
CLKGATE_BASE_MODE__enumvalues = {
0: 'MULT_8',
1: 'MULT_16',
}
MULT_8 = 0
MULT_16 = 1
CLKGATE_BASE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CLKGATE_SM_MODE'
CLKGATE_SM_MODE__enumvalues = {
0: 'ON_SEQ',
1: 'OFF_SEQ',
2: 'PROG_SEQ',
3: 'READ_SEQ',
4: 'SM_MODE_RESERVED',
}
ON_SEQ = 0
OFF_SEQ = 1
PROG_SEQ = 2
READ_SEQ = 3
SM_MODE_RESERVED = 4
CLKGATE_SM_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SPI_FOG_MODE'
SPI_FOG_MODE__enumvalues = {
0: 'SPI_FOG_NONE',
1: 'SPI_FOG_EXP',
2: 'SPI_FOG_EXP2',
3: 'SPI_FOG_LINEAR',
}
SPI_FOG_NONE = 0
SPI_FOG_EXP = 1
SPI_FOG_EXP2 = 2
SPI_FOG_LINEAR = 3
SPI_FOG_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SPI_LB_WAVES_SELECT'
SPI_LB_WAVES_SELECT__enumvalues = {
0: 'HS_GS',
1: 'PS',
2: 'CS_NA',
3: 'SPI_LB_WAVES_RSVD',
}
HS_GS = 0
PS = 1
CS_NA = 2
SPI_LB_WAVES_RSVD = 3
SPI_LB_WAVES_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'SPI_PERFCNT_SEL'
SPI_PERFCNT_SEL__enumvalues = {
1: 'SPI_PERF_GS_WINDOW_VALID',
2: 'SPI_PERF_GS_BUSY',
3: 'SPI_PERF_GS_CRAWLER_STALL',
4: 'SPI_PERF_GS_EVENT_WAVE',
5: 'SPI_PERF_GS_WAVE',
6: 'SPI_PERF_GS_PERS_UPD_FULL0',
7: 'SPI_PERF_GS_PERS_UPD_FULL1',
8: 'SPI_PERF_GS_FIRST_SUBGRP',
9: 'SPI_PERF_GS_HS_DEALLOC',
10: 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT',
11: 'SPI_PERF_GS_POS0_STALL',
12: 'SPI_PERF_GS_POS1_STALL',
13: 'SPI_PERF_GS_INDX0_STALL',
14: 'SPI_PERF_GS_INDX1_STALL',
15: 'SPI_PERF_GS_PWS_STALL',
21: 'SPI_PERF_HS_WINDOW_VALID',
22: 'SPI_PERF_HS_BUSY',
23: 'SPI_PERF_HS_CRAWLER_STALL',
24: 'SPI_PERF_HS_FIRST_WAVE',
25: 'SPI_PERF_HS_OFFCHIP_LDS_STALL',
26: 'SPI_PERF_HS_EVENT_WAVE',
27: 'SPI_PERF_HS_WAVE',
28: 'SPI_PERF_HS_PERS_UPD_FULL0',
29: 'SPI_PERF_HS_PERS_UPD_FULL1',
30: 'SPI_PERF_HS_PWS_STALL',
37: 'SPI_PERF_CSGN_WINDOW_VALID',
38: 'SPI_PERF_CSGN_BUSY',
39: 'SPI_PERF_CSGN_NUM_THREADGROUPS',
40: 'SPI_PERF_CSGN_CRAWLER_STALL',
41: 'SPI_PERF_CSGN_EVENT_WAVE',
42: 'SPI_PERF_CSGN_WAVE',
43: 'SPI_PERF_CSGN_PWS_STALL',
44: 'SPI_PERF_CSN_WINDOW_VALID',
45: 'SPI_PERF_CSN_BUSY',
46: 'SPI_PERF_CSN_NUM_THREADGROUPS',
47: 'SPI_PERF_CSN_CRAWLER_STALL',
48: 'SPI_PERF_CSN_EVENT_WAVE',
49: 'SPI_PERF_CSN_WAVE',
53: 'SPI_PERF_PS0_WINDOW_VALID',
54: 'SPI_PERF_PS1_WINDOW_VALID',
55: 'SPI_PERF_PS2_WINDOW_VALID',
56: 'SPI_PERF_PS3_WINDOW_VALID',
57: 'SPI_PERF_PS0_BUSY',
58: 'SPI_PERF_PS1_BUSY',
59: 'SPI_PERF_PS2_BUSY',
60: 'SPI_PERF_PS3_BUSY',
61: 'SPI_PERF_PS0_ACTIVE',
62: 'SPI_PERF_PS1_ACTIVE',
63: 'SPI_PERF_PS2_ACTIVE',
64: 'SPI_PERF_PS3_ACTIVE',
65: 'SPI_PERF_PS0_DEALLOC',
66: 'SPI_PERF_PS1_DEALLOC',
67: 'SPI_PERF_PS2_DEALLOC',
68: 'SPI_PERF_PS3_DEALLOC',
69: 'SPI_PERF_PS0_EVENT_WAVE',
70: 'SPI_PERF_PS1_EVENT_WAVE',
71: 'SPI_PERF_PS2_EVENT_WAVE',
72: 'SPI_PERF_PS3_EVENT_WAVE',
73: 'SPI_PERF_PS0_WAVE',
74: 'SPI_PERF_PS1_WAVE',
75: 'SPI_PERF_PS2_WAVE',
76: 'SPI_PERF_PS3_WAVE',
77: 'SPI_PERF_PS0_OPT_WAVE',
78: 'SPI_PERF_PS1_OPT_WAVE',
79: 'SPI_PERF_PS2_OPT_WAVE',
80: 'SPI_PERF_PS3_OPT_WAVE',
81: 'SPI_PERF_PS0_PRIM_BIN0',
82: 'SPI_PERF_PS1_PRIM_BIN0',
83: 'SPI_PERF_PS2_PRIM_BIN0',
84: 'SPI_PERF_PS3_PRIM_BIN0',
85: 'SPI_PERF_PS0_PRIM_BIN1',
86: 'SPI_PERF_PS1_PRIM_BIN1',
87: 'SPI_PERF_PS2_PRIM_BIN1',
88: 'SPI_PERF_PS3_PRIM_BIN1',
89: 'SPI_PERF_PS0_CRAWLER_STALL',
90: 'SPI_PERF_PS1_CRAWLER_STALL',
91: 'SPI_PERF_PS2_CRAWLER_STALL',
92: 'SPI_PERF_PS3_CRAWLER_STALL',
93: 'SPI_PERF_PS_PERS_UPD_FULL0',
94: 'SPI_PERF_PS_PERS_UPD_FULL1',
95: 'SPI_PERF_PS0_2_WAVE_GROUPS',
96: 'SPI_PERF_PS1_2_WAVE_GROUPS',
97: 'SPI_PERF_PS2_2_WAVE_GROUPS',
98: 'SPI_PERF_PS3_2_WAVE_GROUPS',
99: 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY',
100: 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY',
101: 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY',
102: 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY',
103: 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS',
104: 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS',
105: 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS',
106: 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS',
107: 'SPI_PERF_PS_PWS_STALL',
141: 'SPI_PERF_RA_PIPE_REQ_BIN2',
142: 'SPI_PERF_RA_TASK_REQ_BIN3',
143: 'SPI_PERF_RA_WR_CTL_FULL',
144: 'SPI_PERF_RA_REQ_NO_ALLOC',
145: 'SPI_PERF_RA_REQ_NO_ALLOC_PS',
146: 'SPI_PERF_RA_REQ_NO_ALLOC_GS',
147: 'SPI_PERF_RA_REQ_NO_ALLOC_HS',
148: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG',
149: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN',
150: 'SPI_PERF_RA_RES_STALL_PS',
151: 'SPI_PERF_RA_RES_STALL_GS',
152: 'SPI_PERF_RA_RES_STALL_HS',
153: 'SPI_PERF_RA_RES_STALL_CSG',
154: 'SPI_PERF_RA_RES_STALL_CSN',
155: 'SPI_PERF_RA_TMP_STALL_PS',
156: 'SPI_PERF_RA_TMP_STALL_GS',
157: 'SPI_PERF_RA_TMP_STALL_HS',
158: 'SPI_PERF_RA_TMP_STALL_CSG',
159: 'SPI_PERF_RA_TMP_STALL_CSN',
160: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS',
161: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS',
162: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS',
163: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG',
164: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN',
165: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS',
166: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS',
167: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS',
168: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG',
169: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN',
170: 'SPI_PERF_RA_LDS_CU_FULL_PS',
171: 'SPI_PERF_RA_LDS_CU_FULL_HS',
172: 'SPI_PERF_RA_LDS_CU_FULL_GS',
173: 'SPI_PERF_RA_LDS_CU_FULL_CSG',
174: 'SPI_PERF_RA_LDS_CU_FULL_CSN',
175: 'SPI_PERF_RA_BAR_CU_FULL_HS',
176: 'SPI_PERF_RA_BAR_CU_FULL_CSG',
177: 'SPI_PERF_RA_BAR_CU_FULL_CSN',
178: 'SPI_PERF_RA_BULKY_CU_FULL_CSG',
179: 'SPI_PERF_RA_BULKY_CU_FULL_CSN',
180: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG',
181: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN',
182: 'SPI_PERF_RA_WVLIM_STALL_PS',
183: 'SPI_PERF_RA_WVLIM_STALL_GS',
184: 'SPI_PERF_RA_WVLIM_STALL_HS',
185: 'SPI_PERF_RA_WVLIM_STALL_CSG',
186: 'SPI_PERF_RA_WVLIM_STALL_CSN',
187: 'SPI_PERF_RA_GS_LOCK',
188: 'SPI_PERF_RA_HS_LOCK',
189: 'SPI_PERF_RA_CSG_LOCK',
190: 'SPI_PERF_RA_CSN_LOCK',
191: 'SPI_PERF_RA_RSV_UPD',
192: 'SPI_PERF_RA_PRE_ALLOC_STALL',
193: 'SPI_PERF_RA_GFX_UNDER_TUNNEL',
194: 'SPI_PERF_RA_CSC_UNDER_TUNNEL',
195: 'SPI_PERF_RA_WVALLOC_STALL',
196: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS',
197: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS',
198: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS',
199: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS',
200: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS',
201: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS',
202: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS',
203: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS',
204: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS',
205: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS',
206: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS',
207: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS',
208: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG',
209: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG',
210: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG',
211: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG',
212: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN',
213: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN',
214: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN',
215: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN',
216: 'SPI_PERF_EXP_ARB_COL_CNT',
217: 'SPI_PERF_EXP_ARB_POS_CNT',
218: 'SPI_PERF_EXP_ARB_GDS_CNT',
219: 'SPI_PERF_EXP_ARB_IDX_CNT',
220: 'SPI_PERF_EXP_WITH_CONFLICT',
221: 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR',
222: 'SPI_PERF_GS_EXP_DONE',
223: 'SPI_PERF_PS_EXP_DONE',
224: 'SPI_PERF_PS_EXP_ARB_CONFLICT',
225: 'SPI_PERF_PS_EXP_ALLOC',
226: 'SPI_PERF_PS0_WAVEID_STARVED',
227: 'SPI_PERF_PS1_WAVEID_STARVED',
228: 'SPI_PERF_PS2_WAVEID_STARVED',
229: 'SPI_PERF_PS3_WAVEID_STARVED',
230: 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT',
231: 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT',
232: 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT',
233: 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT',
234: 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS',
235: 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS',
236: 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS',
237: 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS',
238: 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS',
239: 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS',
240: 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS',
241: 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS',
242: 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS',
243: 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS',
244: 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS',
245: 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS',
246: 'SPI_PERF_NUM_EXPGRANT_EXPORTS',
253: 'SPI_PERF_PIX_ALLOC_PEND_CNT',
254: 'SPI_PERF_EXPORT_SCB0_STALL',
255: 'SPI_PERF_EXPORT_SCB1_STALL',
256: 'SPI_PERF_EXPORT_SCB2_STALL',
257: 'SPI_PERF_EXPORT_SCB3_STALL',
258: 'SPI_PERF_EXPORT_DB0_STALL',
259: 'SPI_PERF_EXPORT_DB1_STALL',
260: 'SPI_PERF_EXPORT_DB2_STALL',
261: 'SPI_PERF_EXPORT_DB3_STALL',
262: 'SPI_PERF_EXPORT_DB4_STALL',
263: 'SPI_PERF_EXPORT_DB5_STALL',
264: 'SPI_PERF_EXPORT_DB6_STALL',
265: 'SPI_PERF_EXPORT_DB7_STALL',
266: 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC',
267: 'SPI_PERF_GS_NGG_STALL_MSG_VAL',
268: 'SPI_PERF_SWC_PS_WR',
269: 'SPI_PERF_SWC_GS_WR',
270: 'SPI_PERF_SWC_HS_WR',
271: 'SPI_PERF_SWC_CSGN_WR',
272: 'SPI_PERF_SWC_CSN_WR',
273: 'SPI_PERF_VWC_PS_WR',
274: 'SPI_PERF_VWC_ES_WR',
275: 'SPI_PERF_VWC_GS_WR',
276: 'SPI_PERF_VWC_LS_WR',
277: 'SPI_PERF_VWC_HS_WR',
278: 'SPI_PERF_VWC_CSGN_WR',
279: 'SPI_PERF_VWC_CSN_WR',
280: 'SPI_PERF_EXP_THROT_UPSTEP',
281: 'SPI_PERF_EXP_THROT_DOWNSTEP',
282: 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED',
283: 'SPI_PERF_BUSY',
}
SPI_PERF_GS_WINDOW_VALID = 1
SPI_PERF_GS_BUSY = 2
SPI_PERF_GS_CRAWLER_STALL = 3
SPI_PERF_GS_EVENT_WAVE = 4
SPI_PERF_GS_WAVE = 5
SPI_PERF_GS_PERS_UPD_FULL0 = 6
SPI_PERF_GS_PERS_UPD_FULL1 = 7
SPI_PERF_GS_FIRST_SUBGRP = 8
SPI_PERF_GS_HS_DEALLOC = 9
SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 10
SPI_PERF_GS_POS0_STALL = 11
SPI_PERF_GS_POS1_STALL = 12
SPI_PERF_GS_INDX0_STALL = 13
SPI_PERF_GS_INDX1_STALL = 14
SPI_PERF_GS_PWS_STALL = 15
SPI_PERF_HS_WINDOW_VALID = 21
SPI_PERF_HS_BUSY = 22
SPI_PERF_HS_CRAWLER_STALL = 23
SPI_PERF_HS_FIRST_WAVE = 24
SPI_PERF_HS_OFFCHIP_LDS_STALL = 25
SPI_PERF_HS_EVENT_WAVE = 26
SPI_PERF_HS_WAVE = 27
SPI_PERF_HS_PERS_UPD_FULL0 = 28
SPI_PERF_HS_PERS_UPD_FULL1 = 29
SPI_PERF_HS_PWS_STALL = 30
SPI_PERF_CSGN_WINDOW_VALID = 37
SPI_PERF_CSGN_BUSY = 38
SPI_PERF_CSGN_NUM_THREADGROUPS = 39
SPI_PERF_CSGN_CRAWLER_STALL = 40
SPI_PERF_CSGN_EVENT_WAVE = 41
SPI_PERF_CSGN_WAVE = 42
SPI_PERF_CSGN_PWS_STALL = 43
SPI_PERF_CSN_WINDOW_VALID = 44
SPI_PERF_CSN_BUSY = 45
SPI_PERF_CSN_NUM_THREADGROUPS = 46
SPI_PERF_CSN_CRAWLER_STALL = 47
SPI_PERF_CSN_EVENT_WAVE = 48
SPI_PERF_CSN_WAVE = 49
SPI_PERF_PS0_WINDOW_VALID = 53
SPI_PERF_PS1_WINDOW_VALID = 54
SPI_PERF_PS2_WINDOW_VALID = 55
SPI_PERF_PS3_WINDOW_VALID = 56
SPI_PERF_PS0_BUSY = 57
SPI_PERF_PS1_BUSY = 58
SPI_PERF_PS2_BUSY = 59
SPI_PERF_PS3_BUSY = 60
SPI_PERF_PS0_ACTIVE = 61
SPI_PERF_PS1_ACTIVE = 62
SPI_PERF_PS2_ACTIVE = 63
SPI_PERF_PS3_ACTIVE = 64
SPI_PERF_PS0_DEALLOC = 65
SPI_PERF_PS1_DEALLOC = 66
SPI_PERF_PS2_DEALLOC = 67
SPI_PERF_PS3_DEALLOC = 68
SPI_PERF_PS0_EVENT_WAVE = 69
SPI_PERF_PS1_EVENT_WAVE = 70
SPI_PERF_PS2_EVENT_WAVE = 71
SPI_PERF_PS3_EVENT_WAVE = 72
SPI_PERF_PS0_WAVE = 73
SPI_PERF_PS1_WAVE = 74
SPI_PERF_PS2_WAVE = 75
SPI_PERF_PS3_WAVE = 76
SPI_PERF_PS0_OPT_WAVE = 77
SPI_PERF_PS1_OPT_WAVE = 78
SPI_PERF_PS2_OPT_WAVE = 79
SPI_PERF_PS3_OPT_WAVE = 80
SPI_PERF_PS0_PRIM_BIN0 = 81
SPI_PERF_PS1_PRIM_BIN0 = 82
SPI_PERF_PS2_PRIM_BIN0 = 83
SPI_PERF_PS3_PRIM_BIN0 = 84
SPI_PERF_PS0_PRIM_BIN1 = 85
SPI_PERF_PS1_PRIM_BIN1 = 86
SPI_PERF_PS2_PRIM_BIN1 = 87
SPI_PERF_PS3_PRIM_BIN1 = 88
SPI_PERF_PS0_CRAWLER_STALL = 89
SPI_PERF_PS1_CRAWLER_STALL = 90
SPI_PERF_PS2_CRAWLER_STALL = 91
SPI_PERF_PS3_CRAWLER_STALL = 92
SPI_PERF_PS_PERS_UPD_FULL0 = 93
SPI_PERF_PS_PERS_UPD_FULL1 = 94
SPI_PERF_PS0_2_WAVE_GROUPS = 95
SPI_PERF_PS1_2_WAVE_GROUPS = 96
SPI_PERF_PS2_2_WAVE_GROUPS = 97
SPI_PERF_PS3_2_WAVE_GROUPS = 98
SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 99
SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 100
SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 101
SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 102
SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 103
SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 104
SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 105
SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 106
SPI_PERF_PS_PWS_STALL = 107
SPI_PERF_RA_PIPE_REQ_BIN2 = 141
SPI_PERF_RA_TASK_REQ_BIN3 = 142
SPI_PERF_RA_WR_CTL_FULL = 143
SPI_PERF_RA_REQ_NO_ALLOC = 144
SPI_PERF_RA_REQ_NO_ALLOC_PS = 145
SPI_PERF_RA_REQ_NO_ALLOC_GS = 146
SPI_PERF_RA_REQ_NO_ALLOC_HS = 147
SPI_PERF_RA_REQ_NO_ALLOC_CSG = 148
SPI_PERF_RA_REQ_NO_ALLOC_CSN = 149
SPI_PERF_RA_RES_STALL_PS = 150
SPI_PERF_RA_RES_STALL_GS = 151
SPI_PERF_RA_RES_STALL_HS = 152
SPI_PERF_RA_RES_STALL_CSG = 153
SPI_PERF_RA_RES_STALL_CSN = 154
SPI_PERF_RA_TMP_STALL_PS = 155
SPI_PERF_RA_TMP_STALL_GS = 156
SPI_PERF_RA_TMP_STALL_HS = 157
SPI_PERF_RA_TMP_STALL_CSG = 158
SPI_PERF_RA_TMP_STALL_CSN = 159
SPI_PERF_RA_WAVE_SIMD_FULL_PS = 160
SPI_PERF_RA_WAVE_SIMD_FULL_GS = 161
SPI_PERF_RA_WAVE_SIMD_FULL_HS = 162
SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 163
SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 164
SPI_PERF_RA_VGPR_SIMD_FULL_PS = 165
SPI_PERF_RA_VGPR_SIMD_FULL_GS = 166
SPI_PERF_RA_VGPR_SIMD_FULL_HS = 167
SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 168
SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 169
SPI_PERF_RA_LDS_CU_FULL_PS = 170
SPI_PERF_RA_LDS_CU_FULL_HS = 171
SPI_PERF_RA_LDS_CU_FULL_GS = 172
SPI_PERF_RA_LDS_CU_FULL_CSG = 173
SPI_PERF_RA_LDS_CU_FULL_CSN = 174
SPI_PERF_RA_BAR_CU_FULL_HS = 175
SPI_PERF_RA_BAR_CU_FULL_CSG = 176
SPI_PERF_RA_BAR_CU_FULL_CSN = 177
SPI_PERF_RA_BULKY_CU_FULL_CSG = 178
SPI_PERF_RA_BULKY_CU_FULL_CSN = 179
SPI_PERF_RA_TGLIM_CU_FULL_CSG = 180
SPI_PERF_RA_TGLIM_CU_FULL_CSN = 181
SPI_PERF_RA_WVLIM_STALL_PS = 182
SPI_PERF_RA_WVLIM_STALL_GS = 183
SPI_PERF_RA_WVLIM_STALL_HS = 184
SPI_PERF_RA_WVLIM_STALL_CSG = 185
SPI_PERF_RA_WVLIM_STALL_CSN = 186
SPI_PERF_RA_GS_LOCK = 187
SPI_PERF_RA_HS_LOCK = 188
SPI_PERF_RA_CSG_LOCK = 189
SPI_PERF_RA_CSN_LOCK = 190
SPI_PERF_RA_RSV_UPD = 191
SPI_PERF_RA_PRE_ALLOC_STALL = 192
SPI_PERF_RA_GFX_UNDER_TUNNEL = 193
SPI_PERF_RA_CSC_UNDER_TUNNEL = 194
SPI_PERF_RA_WVALLOC_STALL = 195
SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 196
SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 197
SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 198
SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 199
SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 200
SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 201
SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 202
SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 203
SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 204
SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 205
SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 206
SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 207
SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 208
SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 209
SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 210
SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 211
SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 212
SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 213
SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 214
SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 215
SPI_PERF_EXP_ARB_COL_CNT = 216
SPI_PERF_EXP_ARB_POS_CNT = 217
SPI_PERF_EXP_ARB_GDS_CNT = 218
SPI_PERF_EXP_ARB_IDX_CNT = 219
SPI_PERF_EXP_WITH_CONFLICT = 220
SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 221
SPI_PERF_GS_EXP_DONE = 222
SPI_PERF_PS_EXP_DONE = 223
SPI_PERF_PS_EXP_ARB_CONFLICT = 224
SPI_PERF_PS_EXP_ALLOC = 225
SPI_PERF_PS0_WAVEID_STARVED = 226
SPI_PERF_PS1_WAVEID_STARVED = 227
SPI_PERF_PS2_WAVEID_STARVED = 228
SPI_PERF_PS3_WAVEID_STARVED = 229
SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 230
SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 231
SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 232
SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 233
SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 234
SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 235
SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 236
SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 237
SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 238
SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 239
SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 240
SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 241
SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 242
SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 243
SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 244
SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 245
SPI_PERF_NUM_EXPGRANT_EXPORTS = 246
SPI_PERF_PIX_ALLOC_PEND_CNT = 253
SPI_PERF_EXPORT_SCB0_STALL = 254
SPI_PERF_EXPORT_SCB1_STALL = 255
SPI_PERF_EXPORT_SCB2_STALL = 256
SPI_PERF_EXPORT_SCB3_STALL = 257
SPI_PERF_EXPORT_DB0_STALL = 258
SPI_PERF_EXPORT_DB1_STALL = 259
SPI_PERF_EXPORT_DB2_STALL = 260
SPI_PERF_EXPORT_DB3_STALL = 261
SPI_PERF_EXPORT_DB4_STALL = 262
SPI_PERF_EXPORT_DB5_STALL = 263
SPI_PERF_EXPORT_DB6_STALL = 264
SPI_PERF_EXPORT_DB7_STALL = 265
SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 266
SPI_PERF_GS_NGG_STALL_MSG_VAL = 267
SPI_PERF_SWC_PS_WR = 268
SPI_PERF_SWC_GS_WR = 269
SPI_PERF_SWC_HS_WR = 270
SPI_PERF_SWC_CSGN_WR = 271
SPI_PERF_SWC_CSN_WR = 272
SPI_PERF_VWC_PS_WR = 273
SPI_PERF_VWC_ES_WR = 274
SPI_PERF_VWC_GS_WR = 275
SPI_PERF_VWC_LS_WR = 276
SPI_PERF_VWC_HS_WR = 277
SPI_PERF_VWC_CSGN_WR = 278
SPI_PERF_VWC_CSN_WR = 279
SPI_PERF_EXP_THROT_UPSTEP = 280
SPI_PERF_EXP_THROT_DOWNSTEP = 281
SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 282
SPI_PERF_BUSY = 283
SPI_PERFCNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE'
SPI_PNT_SPRITE_OVERRIDE__enumvalues = {
0: 'SPI_PNT_SPRITE_SEL_0',
1: 'SPI_PNT_SPRITE_SEL_1',
2: 'SPI_PNT_SPRITE_SEL_S',
3: 'SPI_PNT_SPRITE_SEL_T',
4: 'SPI_PNT_SPRITE_SEL_NONE',
}
SPI_PNT_SPRITE_SEL_0 = 0
SPI_PNT_SPRITE_SEL_1 = 1
SPI_PNT_SPRITE_SEL_S = 2
SPI_PNT_SPRITE_SEL_T = 3
SPI_PNT_SPRITE_SEL_NONE = 4
SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum
# values for enumeration 'SPI_PS_LDS_GROUP_SIZE'
SPI_PS_LDS_GROUP_SIZE__enumvalues = {
0: 'SPI_PS_LDS_GROUP_1',
1: 'SPI_PS_LDS_GROUP_2',
2: 'SPI_PS_LDS_GROUP_4',
}
SPI_PS_LDS_GROUP_1 = 0
SPI_PS_LDS_GROUP_2 = 1
SPI_PS_LDS_GROUP_4 = 2
SPI_PS_LDS_GROUP_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'SPI_SAMPLE_CNTL'
SPI_SAMPLE_CNTL__enumvalues = {
0: 'CENTROIDS_ONLY',
1: 'CENTERS_ONLY',
2: 'CENTROIDS_AND_CENTERS',
3: 'UNDEF',
}
CENTROIDS_ONLY = 0
CENTERS_ONLY = 1
CENTROIDS_AND_CENTERS = 2
UNDEF = 3
SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum
# values for enumeration 'SPI_SHADER_EX_FORMAT'
SPI_SHADER_EX_FORMAT__enumvalues = {
0: 'SPI_SHADER_ZERO',
1: 'SPI_SHADER_32_R',
2: 'SPI_SHADER_32_GR',
3: 'SPI_SHADER_32_AR',
4: 'SPI_SHADER_FP16_ABGR',
5: 'SPI_SHADER_UNORM16_ABGR',
6: 'SPI_SHADER_SNORM16_ABGR',
7: 'SPI_SHADER_UINT16_ABGR',
8: 'SPI_SHADER_SINT16_ABGR',
9: 'SPI_SHADER_32_ABGR',
}
SPI_SHADER_ZERO = 0
SPI_SHADER_32_R = 1
SPI_SHADER_32_GR = 2
SPI_SHADER_32_AR = 3
SPI_SHADER_FP16_ABGR = 4
SPI_SHADER_UNORM16_ABGR = 5
SPI_SHADER_SNORM16_ABGR = 6
SPI_SHADER_UINT16_ABGR = 7
SPI_SHADER_SINT16_ABGR = 8
SPI_SHADER_32_ABGR = 9
SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'SPI_SHADER_FORMAT'
SPI_SHADER_FORMAT__enumvalues = {
0: 'SPI_SHADER_NONE',
1: 'SPI_SHADER_1COMP',
2: 'SPI_SHADER_2COMP',
3: 'SPI_SHADER_4COMPRESS',
4: 'SPI_SHADER_4COMP',
}
SPI_SHADER_NONE = 0
SPI_SHADER_1COMP = 1
SPI_SHADER_2COMP = 2
SPI_SHADER_4COMPRESS = 3
SPI_SHADER_4COMP = 4
SPI_SHADER_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'SH_MEM_ADDRESS_MODE'
SH_MEM_ADDRESS_MODE__enumvalues = {
0: 'SH_MEM_ADDRESS_MODE_64',
1: 'SH_MEM_ADDRESS_MODE_32',
}
SH_MEM_ADDRESS_MODE_64 = 0
SH_MEM_ADDRESS_MODE_32 = 1
SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SH_MEM_ALIGNMENT_MODE'
SH_MEM_ALIGNMENT_MODE__enumvalues = {
0: 'SH_MEM_ALIGNMENT_MODE_DWORD',
1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT',
2: 'SH_MEM_ALIGNMENT_MODE_STRICT',
3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED',
}
SH_MEM_ALIGNMENT_MODE_DWORD = 0
SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1
SH_MEM_ALIGNMENT_MODE_STRICT = 2
SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3
SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SQG_PERF_SEL'
SQG_PERF_SEL__enumvalues = {
0: 'SQG_PERF_SEL_NONE',
1: 'SQG_PERF_SEL_MSG_BUS_BUSY',
2: 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY',
3: 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY',
4: 'SQG_PERF_SEL_EXP_BUS0_BUSY',
5: 'SQG_PERF_SEL_EXP_BUS1_BUSY',
6: 'SQG_PERF_SEL_TTRACE_REQS',
7: 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS',
8: 'SQG_PERF_SEL_TTRACE_STALL',
9: 'SQG_PERF_SEL_TTRACE_LOST_PACKETS',
10: 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH',
11: 'SQG_PERF_SEL_EVENTS',
12: 'SQG_PERF_SEL_WAVES_RESTORED',
13: 'SQG_PERF_SEL_WAVES_SAVED',
14: 'SQG_PERF_SEL_ACCUM_PREV',
15: 'SQG_PERF_SEL_CYCLES',
16: 'SQG_PERF_SEL_BUSY_CYCLES',
17: 'SQG_PERF_SEL_WAVE_CYCLES',
18: 'SQG_PERF_SEL_MSG',
19: 'SQG_PERF_SEL_MSG_INTERRUPT',
20: 'SQG_PERF_SEL_WAVES',
21: 'SQG_PERF_SEL_WAVES_32',
22: 'SQG_PERF_SEL_WAVES_64',
23: 'SQG_PERF_SEL_LEVEL_WAVES',
24: 'SQG_PERF_SEL_ITEMS',
25: 'SQG_PERF_SEL_WAVE32_ITEMS',
26: 'SQG_PERF_SEL_WAVE64_ITEMS',
27: 'SQG_PERF_SEL_PS_QUADS',
28: 'SQG_PERF_SEL_WAVES_EQ_64',
29: 'SQG_PERF_SEL_WAVES_EQ_32',
30: 'SQG_PERF_SEL_WAVES_LT_64',
31: 'SQG_PERF_SEL_WAVES_LT_48',
32: 'SQG_PERF_SEL_WAVES_LT_32',
33: 'SQG_PERF_SEL_WAVES_LT_16',
34: 'SQG_PERF_SEL_DUMMY_LAST',
}
SQG_PERF_SEL_NONE = 0
SQG_PERF_SEL_MSG_BUS_BUSY = 1
SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 2
SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 3
SQG_PERF_SEL_EXP_BUS0_BUSY = 4
SQG_PERF_SEL_EXP_BUS1_BUSY = 5
SQG_PERF_SEL_TTRACE_REQS = 6
SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 7
SQG_PERF_SEL_TTRACE_STALL = 8
SQG_PERF_SEL_TTRACE_LOST_PACKETS = 9
SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 10
SQG_PERF_SEL_EVENTS = 11
SQG_PERF_SEL_WAVES_RESTORED = 12
SQG_PERF_SEL_WAVES_SAVED = 13
SQG_PERF_SEL_ACCUM_PREV = 14
SQG_PERF_SEL_CYCLES = 15
SQG_PERF_SEL_BUSY_CYCLES = 16
SQG_PERF_SEL_WAVE_CYCLES = 17
SQG_PERF_SEL_MSG = 18
SQG_PERF_SEL_MSG_INTERRUPT = 19
SQG_PERF_SEL_WAVES = 20
SQG_PERF_SEL_WAVES_32 = 21
SQG_PERF_SEL_WAVES_64 = 22
SQG_PERF_SEL_LEVEL_WAVES = 23
SQG_PERF_SEL_ITEMS = 24
SQG_PERF_SEL_WAVE32_ITEMS = 25
SQG_PERF_SEL_WAVE64_ITEMS = 26
SQG_PERF_SEL_PS_QUADS = 27
SQG_PERF_SEL_WAVES_EQ_64 = 28
SQG_PERF_SEL_WAVES_EQ_32 = 29
SQG_PERF_SEL_WAVES_LT_64 = 30
SQG_PERF_SEL_WAVES_LT_48 = 31
SQG_PERF_SEL_WAVES_LT_32 = 32
SQG_PERF_SEL_WAVES_LT_16 = 33
SQG_PERF_SEL_DUMMY_LAST = 34
SQG_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SQ_CAC_POWER_SEL'
SQ_CAC_POWER_SEL__enumvalues = {
0: 'SQ_CAC_POWER_VALU',
1: 'SQ_CAC_POWER_VALU0',
2: 'SQ_CAC_POWER_VALU1',
3: 'SQ_CAC_POWER_VALU2',
4: 'SQ_CAC_POWER_GPR_RD',
5: 'SQ_CAC_POWER_GPR_WR',
6: 'SQ_CAC_POWER_LDS_BUSY',
7: 'SQ_CAC_POWER_ALU_BUSY',
8: 'SQ_CAC_POWER_TEX_BUSY',
}
SQ_CAC_POWER_VALU = 0
SQ_CAC_POWER_VALU0 = 1
SQ_CAC_POWER_VALU1 = 2
SQ_CAC_POWER_VALU2 = 3
SQ_CAC_POWER_GPR_RD = 4
SQ_CAC_POWER_GPR_WR = 5
SQ_CAC_POWER_LDS_BUSY = 6
SQ_CAC_POWER_ALU_BUSY = 7
SQ_CAC_POWER_TEX_BUSY = 8
SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SQ_EDC_INFO_SOURCE'
SQ_EDC_INFO_SOURCE__enumvalues = {
0: 'SQ_EDC_INFO_SOURCE_INVALID',
1: 'SQ_EDC_INFO_SOURCE_INST',
2: 'SQ_EDC_INFO_SOURCE_SGPR',
3: 'SQ_EDC_INFO_SOURCE_VGPR',
4: 'SQ_EDC_INFO_SOURCE_LDS',
5: 'SQ_EDC_INFO_SOURCE_GDS',
6: 'SQ_EDC_INFO_SOURCE_TA',
}
SQ_EDC_INFO_SOURCE_INVALID = 0
SQ_EDC_INFO_SOURCE_INST = 1
SQ_EDC_INFO_SOURCE_SGPR = 2
SQ_EDC_INFO_SOURCE_VGPR = 3
SQ_EDC_INFO_SOURCE_LDS = 4
SQ_EDC_INFO_SOURCE_GDS = 5
SQ_EDC_INFO_SOURCE_TA = 6
SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_IBUF_ST'
SQ_IBUF_ST__enumvalues = {
0: 'SQ_IBUF_IB_IDLE',
1: 'SQ_IBUF_IB_INI_WAIT_GNT',
2: 'SQ_IBUF_IB_INI_WAIT_DRET',
3: 'SQ_IBUF_IB_LE_4DW',
4: 'SQ_IBUF_IB_WAIT_DRET',
5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET',
6: 'SQ_IBUF_IB_DRET',
7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT',
}
SQ_IBUF_IB_IDLE = 0
SQ_IBUF_IB_INI_WAIT_GNT = 1
SQ_IBUF_IB_INI_WAIT_DRET = 2
SQ_IBUF_IB_LE_4DW = 3
SQ_IBUF_IB_WAIT_DRET = 4
SQ_IBUF_IB_EMPTY_WAIT_DRET = 5
SQ_IBUF_IB_DRET = 6
SQ_IBUF_IB_EMPTY_WAIT_GNT = 7
SQ_IBUF_ST = ctypes.c_uint32 # enum
# values for enumeration 'SQ_IMG_FILTER_TYPE'
SQ_IMG_FILTER_TYPE__enumvalues = {
0: 'SQ_IMG_FILTER_MODE_BLEND',
1: 'SQ_IMG_FILTER_MODE_MIN',
2: 'SQ_IMG_FILTER_MODE_MAX',
}
SQ_IMG_FILTER_MODE_BLEND = 0
SQ_IMG_FILTER_MODE_MIN = 1
SQ_IMG_FILTER_MODE_MAX = 2
SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_IND_CMD_CMD'
SQ_IND_CMD_CMD__enumvalues = {
0: 'SQ_IND_CMD_CMD_NULL',
1: 'SQ_IND_CMD_CMD_SETHALT',
2: 'SQ_IND_CMD_CMD_SAVECTX',
3: 'SQ_IND_CMD_CMD_KILL',
4: 'SQ_IND_CMD_CMD_TRAP_AFTER_INST',
5: 'SQ_IND_CMD_CMD_TRAP',
6: 'SQ_IND_CMD_CMD_SET_SPI_PRIO',
7: 'SQ_IND_CMD_CMD_SETFATALHALT',
8: 'SQ_IND_CMD_CMD_SINGLE_STEP',
}
SQ_IND_CMD_CMD_NULL = 0
SQ_IND_CMD_CMD_SETHALT = 1
SQ_IND_CMD_CMD_SAVECTX = 2
SQ_IND_CMD_CMD_KILL = 3
SQ_IND_CMD_CMD_TRAP_AFTER_INST = 4
SQ_IND_CMD_CMD_TRAP = 5
SQ_IND_CMD_CMD_SET_SPI_PRIO = 6
SQ_IND_CMD_CMD_SETFATALHALT = 7
SQ_IND_CMD_CMD_SINGLE_STEP = 8
SQ_IND_CMD_CMD = ctypes.c_uint32 # enum
# values for enumeration 'SQ_IND_CMD_MODE'
SQ_IND_CMD_MODE__enumvalues = {
0: 'SQ_IND_CMD_MODE_SINGLE',
1: 'SQ_IND_CMD_MODE_BROADCAST',
2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE',
3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE',
4: 'SQ_IND_CMD_MODE_BROADCAST_ME',
}
SQ_IND_CMD_MODE_SINGLE = 0
SQ_IND_CMD_MODE_BROADCAST = 1
SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2
SQ_IND_CMD_MODE_BROADCAST_PIPE = 3
SQ_IND_CMD_MODE_BROADCAST_ME = 4
SQ_IND_CMD_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_INST_STR_ST'
SQ_INST_STR_ST__enumvalues = {
0: 'SQ_INST_STR_IB_WAVE_NORML',
1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV',
2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV',
3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV',
4: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT',
5: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT',
}
SQ_INST_STR_IB_WAVE_NORML = 0
SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1
SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2
SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3
SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 4
SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 5
SQ_INST_STR_ST = ctypes.c_uint32 # enum
# values for enumeration 'SQ_INST_TYPE'
SQ_INST_TYPE__enumvalues = {
0: 'SQ_INST_TYPE_VALU',
1: 'SQ_INST_TYPE_SCALAR',
2: 'SQ_INST_TYPE_TEX',
3: 'SQ_INST_TYPE_LDS',
4: 'SQ_INST_TYPE_LDS_DIRECT',
5: 'SQ_INST_TYPE_EXP',
6: 'SQ_INST_TYPE_MSG',
7: 'SQ_INST_TYPE_BARRIER',
8: 'SQ_INST_TYPE_BRANCH_NOT_TAKEN',
9: 'SQ_INST_TYPE_BRANCH_TAKEN',
10: 'SQ_INST_TYPE_JUMP',
11: 'SQ_INST_TYPE_OTHER',
12: 'SQ_INST_TYPE_NONE',
}
SQ_INST_TYPE_VALU = 0
SQ_INST_TYPE_SCALAR = 1
SQ_INST_TYPE_TEX = 2
SQ_INST_TYPE_LDS = 3
SQ_INST_TYPE_LDS_DIRECT = 4
SQ_INST_TYPE_EXP = 5
SQ_INST_TYPE_MSG = 6
SQ_INST_TYPE_BARRIER = 7
SQ_INST_TYPE_BRANCH_NOT_TAKEN = 8
SQ_INST_TYPE_BRANCH_TAKEN = 9
SQ_INST_TYPE_JUMP = 10
SQ_INST_TYPE_OTHER = 11
SQ_INST_TYPE_NONE = 12
SQ_INST_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_LLC_CTL'
SQ_LLC_CTL__enumvalues = {
0: 'SQ_LLC_0',
1: 'SQ_LLC_1',
2: 'SQ_LLC_RSVD_2',
3: 'SQ_LLC_BYPASS',
}
SQ_LLC_0 = 0
SQ_LLC_1 = 1
SQ_LLC_RSVD_2 = 2
SQ_LLC_BYPASS = 3
SQ_LLC_CTL = ctypes.c_uint32 # enum
# values for enumeration 'SQ_NO_INST_ISSUE'
SQ_NO_INST_ISSUE__enumvalues = {
0: 'SQ_NO_INST_ISSUE_NO_INSTS',
1: 'SQ_NO_INST_ISSUE_ALU_DEP',
2: 'SQ_NO_INST_ISSUE_S_WAITCNT',
3: 'SQ_NO_INST_ISSUE_NO_ARB_WIN',
4: 'SQ_NO_INST_ISSUE_SLEEP_WAIT',
5: 'SQ_NO_INST_ISSUE_BARRIER_WAIT',
6: 'SQ_NO_INST_ISSUE_OTHER',
}
SQ_NO_INST_ISSUE_NO_INSTS = 0
SQ_NO_INST_ISSUE_ALU_DEP = 1
SQ_NO_INST_ISSUE_S_WAITCNT = 2
SQ_NO_INST_ISSUE_NO_ARB_WIN = 3
SQ_NO_INST_ISSUE_SLEEP_WAIT = 4
SQ_NO_INST_ISSUE_BARRIER_WAIT = 5
SQ_NO_INST_ISSUE_OTHER = 6
SQ_NO_INST_ISSUE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_OOB_SELECT'
SQ_OOB_SELECT__enumvalues = {
0: 'SQ_OOB_INDEX_AND_OFFSET',
1: 'SQ_OOB_INDEX_ONLY',
2: 'SQ_OOB_NUM_RECORDS_0',
3: 'SQ_OOB_COMPLETE',
}
SQ_OOB_INDEX_AND_OFFSET = 0
SQ_OOB_INDEX_ONLY = 1
SQ_OOB_NUM_RECORDS_0 = 2
SQ_OOB_COMPLETE = 3
SQ_OOB_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'SQ_PERF_SEL'
SQ_PERF_SEL__enumvalues = {
0: 'SQ_PERF_SEL_NONE',
1: 'SQ_PERF_SEL_ACCUM_PREV',
2: 'SQ_PERF_SEL_CYCLES',
3: 'SQ_PERF_SEL_BUSY_CYCLES',
4: 'SQ_PERF_SEL_WAVES',
5: 'SQ_PERF_SEL_WAVES_32',
6: 'SQ_PERF_SEL_WAVES_64',
7: 'SQ_PERF_SEL_LEVEL_WAVES',
8: 'SQ_PERF_SEL_ITEMS',
9: 'SQ_PERF_SEL_WAVE32_ITEMS',
10: 'SQ_PERF_SEL_WAVE64_ITEMS',
11: 'SQ_PERF_SEL_PS_QUADS',
12: 'SQ_PERF_SEL_EVENTS',
13: 'SQ_PERF_SEL_WAVES_EQ_32',
14: 'SQ_PERF_SEL_WAVES_EQ_64',
15: 'SQ_PERF_SEL_WAVES_LT_64',
16: 'SQ_PERF_SEL_WAVES_LT_48',
17: 'SQ_PERF_SEL_WAVES_LT_32',
18: 'SQ_PERF_SEL_WAVES_LT_16',
19: 'SQ_PERF_SEL_WAVES_RESTORED',
20: 'SQ_PERF_SEL_WAVES_SAVED',
21: 'SQ_PERF_SEL_MSG',
22: 'SQ_PERF_SEL_MSG_INTERRUPT',
23: 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH',
24: 'SQ_PERF_SEL_WAVE_CYCLES',
25: 'SQ_PERF_SEL_WAVE_READY',
26: 'SQ_PERF_SEL_WAIT_INST_ANY',
27: 'SQ_PERF_SEL_WAIT_INST_VALU',
28: 'SQ_PERF_SEL_WAIT_INST_SCA',
29: 'SQ_PERF_SEL_WAIT_INST_LDS',
30: 'SQ_PERF_SEL_WAIT_INST_TEX',
31: 'SQ_PERF_SEL_WAIT_INST_FLAT',
32: 'SQ_PERF_SEL_WAIT_INST_VMEM',
33: 'SQ_PERF_SEL_WAIT_INST_EXP_GDS',
34: 'SQ_PERF_SEL_WAIT_INST_BR_MSG',
35: 'SQ_PERF_SEL_WAIT_ANY',
36: 'SQ_PERF_SEL_WAIT_CNT_ANY',
37: 'SQ_PERF_SEL_WAIT_CNT_VMVS',
38: 'SQ_PERF_SEL_WAIT_CNT_LGKM',
39: 'SQ_PERF_SEL_WAIT_CNT_EXP',
40: 'SQ_PERF_SEL_WAIT_TTRACE',
41: 'SQ_PERF_SEL_WAIT_IFETCH',
42: 'SQ_PERF_SEL_WAIT_BARRIER',
43: 'SQ_PERF_SEL_WAIT_EXP_ALLOC',
44: 'SQ_PERF_SEL_WAIT_SLEEP',
45: 'SQ_PERF_SEL_WAIT_DELAY_ALU',
46: 'SQ_PERF_SEL_WAIT_DEPCTR',
47: 'SQ_PERF_SEL_WAIT_OTHER',
48: 'SQ_PERF_SEL_INSTS_ALL',
49: 'SQ_PERF_SEL_INSTS_BRANCH',
50: 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN',
51: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN',
52: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS',
53: 'SQ_PERF_SEL_INSTS_EXP_GDS',
54: 'SQ_PERF_SEL_INSTS_GDS',
55: 'SQ_PERF_SEL_INSTS_EXP',
56: 'SQ_PERF_SEL_INSTS_FLAT',
57: 'SQ_PERF_SEL_INSTS_LDS',
58: 'SQ_PERF_SEL_INSTS_SALU',
59: 'SQ_PERF_SEL_INSTS_SMEM',
60: 'SQ_PERF_SEL_INSTS_SMEM_NORM',
61: 'SQ_PERF_SEL_INSTS_SENDMSG',
62: 'SQ_PERF_SEL_INSTS_VALU',
63: 'SQ_PERF_SEL_INSTS_VALU_TRANS32',
64: 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC',
65: 'SQ_PERF_SEL_INSTS_TEX',
66: 'SQ_PERF_SEL_INSTS_TEX_LOAD',
67: 'SQ_PERF_SEL_INSTS_TEX_STORE',
68: 'SQ_PERF_SEL_INSTS_DELAY_ALU',
69: 'SQ_PERF_SEL_INSTS_INTERNAL',
70: 'SQ_PERF_SEL_INSTS_WAVE32',
71: 'SQ_PERF_SEL_INSTS_WAVE32_FLAT',
72: 'SQ_PERF_SEL_INSTS_WAVE32_LDS',
73: 'SQ_PERF_SEL_INSTS_WAVE32_VALU',
74: 'SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS',
75: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32',
76: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC',
77: 'SQ_PERF_SEL_INSTS_WAVE32_TEX',
78: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD',
79: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE',
80: 'SQ_PERF_SEL_ITEM_CYCLES_VALU',
81: 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES',
82: 'SQ_PERF_SEL_WAVE32_INSTS',
83: 'SQ_PERF_SEL_WAVE64_INSTS',
84: 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED',
85: 'SQ_PERF_SEL_WAVE64_HALF_SKIP',
86: 'SQ_PERF_SEL_INST_LEVEL_EXP',
87: 'SQ_PERF_SEL_INST_LEVEL_GDS',
88: 'SQ_PERF_SEL_INST_LEVEL_LDS',
89: 'SQ_PERF_SEL_INST_LEVEL_SMEM',
90: 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD',
91: 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE',
92: 'SQ_PERF_SEL_IFETCH_REQS',
93: 'SQ_PERF_SEL_IFETCH_LEVEL',
94: 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL',
95: 'SQ_PERF_SEL_VALU_SGATHER_STALL',
96: 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL',
97: 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL',
98: 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL',
99: 'SQ_PERF_SEL_SALU_SGATHER_STALL',
100: 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL',
101: 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL',
102: 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL',
103: 'SQ_PERF_SEL_INST_CYCLES_VALU',
104: 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32',
105: 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC',
106: 'SQ_PERF_SEL_INST_CYCLES_VMEM',
107: 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD',
108: 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE',
109: 'SQ_PERF_SEL_INST_CYCLES_LDS',
110: 'SQ_PERF_SEL_INST_CYCLES_TEX',
111: 'SQ_PERF_SEL_INST_CYCLES_FLAT',
112: 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS',
113: 'SQ_PERF_SEL_INST_CYCLES_EXP',
114: 'SQ_PERF_SEL_INST_CYCLES_GDS',
115: 'SQ_PERF_SEL_VALU_STARVE',
116: 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL',
117: 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL',
118: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL',
119: 'SQ_PERF_SEL_VMEM_BUS_ACTIVE',
120: 'SQ_PERF_SEL_VMEM_BUS_STALL',
121: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL',
122: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL',
123: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL',
124: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL',
125: 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY',
126: 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY',
127: 'SQ_PERF_SEL_SALU_PIPE_STALL',
128: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES',
129: 'SQ_PERF_SEL_MSG_BUS_BUSY',
130: 'SQ_PERF_SEL_EXP_REQ_BUS_STALL',
131: 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY',
132: 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY',
133: 'SQ_PERF_SEL_EXP_BUS0_BUSY',
134: 'SQ_PERF_SEL_EXP_BUS1_BUSY',
135: 'SQ_PERF_SEL_INST_CACHE_REQ_STALL',
136: 'SQ_PERF_SEL_USER0',
137: 'SQ_PERF_SEL_USER1',
138: 'SQ_PERF_SEL_USER2',
139: 'SQ_PERF_SEL_USER3',
140: 'SQ_PERF_SEL_USER4',
141: 'SQ_PERF_SEL_USER5',
142: 'SQ_PERF_SEL_USER6',
143: 'SQ_PERF_SEL_USER7',
144: 'SQ_PERF_SEL_USER8',
145: 'SQ_PERF_SEL_USER9',
146: 'SQ_PERF_SEL_USER10',
147: 'SQ_PERF_SEL_USER11',
148: 'SQ_PERF_SEL_USER12',
149: 'SQ_PERF_SEL_USER13',
150: 'SQ_PERF_SEL_USER14',
151: 'SQ_PERF_SEL_USER15',
152: 'SQ_PERF_SEL_USER_LEVEL0',
153: 'SQ_PERF_SEL_USER_LEVEL1',
154: 'SQ_PERF_SEL_USER_LEVEL2',
155: 'SQ_PERF_SEL_USER_LEVEL3',
156: 'SQ_PERF_SEL_USER_LEVEL4',
157: 'SQ_PERF_SEL_USER_LEVEL5',
158: 'SQ_PERF_SEL_USER_LEVEL6',
159: 'SQ_PERF_SEL_USER_LEVEL7',
160: 'SQ_PERF_SEL_USER_LEVEL8',
161: 'SQ_PERF_SEL_USER_LEVEL9',
162: 'SQ_PERF_SEL_USER_LEVEL10',
163: 'SQ_PERF_SEL_USER_LEVEL11',
164: 'SQ_PERF_SEL_USER_LEVEL12',
165: 'SQ_PERF_SEL_USER_LEVEL13',
166: 'SQ_PERF_SEL_USER_LEVEL14',
167: 'SQ_PERF_SEL_USER_LEVEL15',
168: 'SQ_PERF_SEL_VALU_RETURN_SDST',
169: 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT',
170: 'SQ_PERF_SEL_INSTS_VALU_TRANS',
171: 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD',
172: 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD',
173: 'SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD',
174: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64',
175: 'SQ_PERF_SEL_INSTS_VALU_VINTERP',
176: 'SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP',
177: 'SQ_PERF_SEL_OVERFLOW_PREV',
178: 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32',
179: 'SQ_PERF_SEL_INSTS_VALU_1_PASS',
180: 'SQ_PERF_SEL_INSTS_VALU_2_PASS',
181: 'SQ_PERF_SEL_INSTS_VALU_4_PASS',
182: 'SQ_PERF_SEL_INSTS_VALU_DP',
183: 'SQ_PERF_SEL_SP_CONST_CYCLES',
184: 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES',
185: 'SQ_PERF_SEL_ITEMS_VALU',
186: 'SQ_PERF_SEL_ITEMS_MAX_VALU',
187: 'SQ_PERF_SEL_ITEM_CYCLES_VMEM',
188: 'SQ_PERF_SEL_DUMMY_END',
255: 'SQ_PERF_SEL_DUMMY_LAST',
256: 'SQC_PERF_SEL_LDS_BANK_CONFLICT',
257: 'SQC_PERF_SEL_LDS_ADDR_CONFLICT',
258: 'SQC_PERF_SEL_LDS_UNALIGNED_STALL',
259: 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS',
260: 'SQC_PERF_SEL_LDS_ATOMIC_RETURN',
261: 'SQC_PERF_SEL_LDS_IDX_ACTIVE',
262: 'SQC_PERF_SEL_LDS_ADDR_STALL',
263: 'SQC_PERF_SEL_LDS_ADDR_ACTIVE',
264: 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD',
265: 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD',
266: 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL',
267: 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES',
268: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES',
269: 'SQC_PERF_SEL_ICACHE_REQ',
270: 'SQC_PERF_SEL_ICACHE_HITS',
271: 'SQC_PERF_SEL_ICACHE_MISSES',
272: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE',
273: 'SQC_PERF_SEL_ICACHE_INVAL_INST',
274: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC',
275: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL',
276: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL',
277: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL',
278: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL',
279: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL',
280: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB',
281: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB',
282: 'SQC_PERF_SEL_TC_REQ',
283: 'SQC_PERF_SEL_TC_INST_REQ',
284: 'SQC_PERF_SEL_TC_DATA_READ_REQ',
285: 'SQC_PERF_SEL_TC_STALL',
286: 'SQC_PERF_SEL_TC_STARVE',
287: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT',
288: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB',
289: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED',
290: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX',
291: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT',
292: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES',
293: 'SQC_PERF_SEL_DCACHE_REQ',
294: 'SQC_PERF_SEL_DCACHE_HITS',
295: 'SQC_PERF_SEL_DCACHE_MISSES',
296: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE',
297: 'SQC_PERF_SEL_DCACHE_INVAL_INST',
298: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC',
299: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ',
300: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT',
301: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB',
302: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED',
303: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX',
304: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT',
305: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT',
306: 'SQC_PERF_SEL_DCACHE_REQ_READ_1',
307: 'SQC_PERF_SEL_DCACHE_REQ_READ_2',
308: 'SQC_PERF_SEL_DCACHE_REQ_READ_4',
309: 'SQC_PERF_SEL_DCACHE_REQ_READ_8',
310: 'SQC_PERF_SEL_DCACHE_REQ_READ_16',
311: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE',
312: 'SQC_PERF_SEL_SQ_DCACHE_REQS',
313: 'SQC_PERF_SEL_DCACHE_FLAT_REQ',
314: 'SQC_PERF_SEL_TD_VGPR_BUSY',
315: 'SQC_PERF_SEL_LDS_VGPR_BUSY',
316: 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL',
317: 'SQC_PERF_SEL_ICACHE_GCR',
318: 'SQC_PERF_SEL_ICACHE_GCR_HITS',
319: 'SQC_PERF_SEL_DCACHE_GCR',
320: 'SQC_PERF_SEL_DCACHE_GCR_HITS',
321: 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE',
322: 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE',
323: 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL',
324: 'SQC_PERF_SEL_DUMMY_LAST',
448: 'SP_PERF_SEL_DST_BUF_ALLOC_STALL',
449: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS',
450: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI',
451: 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY',
452: 'SP_PERF_SEL_DST_BUF_ODD_DIRTY',
453: 'SP_PERF_SEL_SRC_CACHE_HIT_B0',
454: 'SP_PERF_SEL_SRC_CACHE_HIT_B1',
455: 'SP_PERF_SEL_SRC_CACHE_HIT_B2',
456: 'SP_PERF_SEL_SRC_CACHE_HIT_B3',
457: 'SP_PERF_SEL_SRC_CACHE_PROBE_B0',
458: 'SP_PERF_SEL_SRC_CACHE_PROBE_B1',
459: 'SP_PERF_SEL_SRC_CACHE_PROBE_B2',
460: 'SP_PERF_SEL_SRC_CACHE_PROBE_B3',
461: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0',
462: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1',
463: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2',
464: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3',
465: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0',
466: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1',
467: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2',
468: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3',
469: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0',
470: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1',
471: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2',
472: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3',
473: 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL',
474: 'SP_PERF_SEL_VALU_OPERAND',
475: 'SP_PERF_SEL_VALU_VGPR_OPERAND',
476: 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF',
477: 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE',
478: 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS',
479: 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL',
480: 'SP_PERF_SEL_VALU_STALL',
481: 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY',
482: 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY',
483: 'SP_PERF_SEL_VALU_STALL_VDST_FWD',
484: 'SP_PERF_SEL_VALU_STALL_SDST_FWD',
485: 'SP_PERF_SEL_VALU_STALL_DST_STALL',
486: 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY',
487: 'SP_PERF_SEL_VGPR_VMEM_RD',
488: 'SP_PERF_SEL_VGPR_EXP_RD',
489: 'SP_PERF_SEL_VGPR_SPI_WR',
490: 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR',
491: 'SP_PERF_SEL_VGPR_WR',
492: 'SP_PERF_SEL_VGPR_RD',
493: 'SP_PERF_SEL_DUMMY_LAST',
511: 'SQ_PERF_SEL_NONE2',
}
SQ_PERF_SEL_NONE = 0
SQ_PERF_SEL_ACCUM_PREV = 1
SQ_PERF_SEL_CYCLES = 2
SQ_PERF_SEL_BUSY_CYCLES = 3
SQ_PERF_SEL_WAVES = 4
SQ_PERF_SEL_WAVES_32 = 5
SQ_PERF_SEL_WAVES_64 = 6
SQ_PERF_SEL_LEVEL_WAVES = 7
SQ_PERF_SEL_ITEMS = 8
SQ_PERF_SEL_WAVE32_ITEMS = 9
SQ_PERF_SEL_WAVE64_ITEMS = 10
SQ_PERF_SEL_PS_QUADS = 11
SQ_PERF_SEL_EVENTS = 12
SQ_PERF_SEL_WAVES_EQ_32 = 13
SQ_PERF_SEL_WAVES_EQ_64 = 14
SQ_PERF_SEL_WAVES_LT_64 = 15
SQ_PERF_SEL_WAVES_LT_48 = 16
SQ_PERF_SEL_WAVES_LT_32 = 17
SQ_PERF_SEL_WAVES_LT_16 = 18
SQ_PERF_SEL_WAVES_RESTORED = 19
SQ_PERF_SEL_WAVES_SAVED = 20
SQ_PERF_SEL_MSG = 21
SQ_PERF_SEL_MSG_INTERRUPT = 22
SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 23
SQ_PERF_SEL_WAVE_CYCLES = 24
SQ_PERF_SEL_WAVE_READY = 25
SQ_PERF_SEL_WAIT_INST_ANY = 26
SQ_PERF_SEL_WAIT_INST_VALU = 27
SQ_PERF_SEL_WAIT_INST_SCA = 28
SQ_PERF_SEL_WAIT_INST_LDS = 29
SQ_PERF_SEL_WAIT_INST_TEX = 30
SQ_PERF_SEL_WAIT_INST_FLAT = 31
SQ_PERF_SEL_WAIT_INST_VMEM = 32
SQ_PERF_SEL_WAIT_INST_EXP_GDS = 33
SQ_PERF_SEL_WAIT_INST_BR_MSG = 34
SQ_PERF_SEL_WAIT_ANY = 35
SQ_PERF_SEL_WAIT_CNT_ANY = 36
SQ_PERF_SEL_WAIT_CNT_VMVS = 37
SQ_PERF_SEL_WAIT_CNT_LGKM = 38
SQ_PERF_SEL_WAIT_CNT_EXP = 39
SQ_PERF_SEL_WAIT_TTRACE = 40
SQ_PERF_SEL_WAIT_IFETCH = 41
SQ_PERF_SEL_WAIT_BARRIER = 42
SQ_PERF_SEL_WAIT_EXP_ALLOC = 43
SQ_PERF_SEL_WAIT_SLEEP = 44
SQ_PERF_SEL_WAIT_DELAY_ALU = 45
SQ_PERF_SEL_WAIT_DEPCTR = 46
SQ_PERF_SEL_WAIT_OTHER = 47
SQ_PERF_SEL_INSTS_ALL = 48
SQ_PERF_SEL_INSTS_BRANCH = 49
SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 50
SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 51
SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 52
SQ_PERF_SEL_INSTS_EXP_GDS = 53
SQ_PERF_SEL_INSTS_GDS = 54
SQ_PERF_SEL_INSTS_EXP = 55
SQ_PERF_SEL_INSTS_FLAT = 56
SQ_PERF_SEL_INSTS_LDS = 57
SQ_PERF_SEL_INSTS_SALU = 58
SQ_PERF_SEL_INSTS_SMEM = 59
SQ_PERF_SEL_INSTS_SMEM_NORM = 60
SQ_PERF_SEL_INSTS_SENDMSG = 61
SQ_PERF_SEL_INSTS_VALU = 62
SQ_PERF_SEL_INSTS_VALU_TRANS32 = 63
SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 64
SQ_PERF_SEL_INSTS_TEX = 65
SQ_PERF_SEL_INSTS_TEX_LOAD = 66
SQ_PERF_SEL_INSTS_TEX_STORE = 67
SQ_PERF_SEL_INSTS_DELAY_ALU = 68
SQ_PERF_SEL_INSTS_INTERNAL = 69
SQ_PERF_SEL_INSTS_WAVE32 = 70
SQ_PERF_SEL_INSTS_WAVE32_FLAT = 71
SQ_PERF_SEL_INSTS_WAVE32_LDS = 72
SQ_PERF_SEL_INSTS_WAVE32_VALU = 73
SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS = 74
SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 75
SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 76
SQ_PERF_SEL_INSTS_WAVE32_TEX = 77
SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 78
SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 79
SQ_PERF_SEL_ITEM_CYCLES_VALU = 80
SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 81
SQ_PERF_SEL_WAVE32_INSTS = 82
SQ_PERF_SEL_WAVE64_INSTS = 83
SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 84
SQ_PERF_SEL_WAVE64_HALF_SKIP = 85
SQ_PERF_SEL_INST_LEVEL_EXP = 86
SQ_PERF_SEL_INST_LEVEL_GDS = 87
SQ_PERF_SEL_INST_LEVEL_LDS = 88
SQ_PERF_SEL_INST_LEVEL_SMEM = 89
SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 90
SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 91
SQ_PERF_SEL_IFETCH_REQS = 92
SQ_PERF_SEL_IFETCH_LEVEL = 93
SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 94
SQ_PERF_SEL_VALU_SGATHER_STALL = 95
SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 96
SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 97
SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 98
SQ_PERF_SEL_SALU_SGATHER_STALL = 99
SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 100
SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 101
SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 102
SQ_PERF_SEL_INST_CYCLES_VALU = 103
SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 104
SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 105
SQ_PERF_SEL_INST_CYCLES_VMEM = 106
SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 107
SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 108
SQ_PERF_SEL_INST_CYCLES_LDS = 109
SQ_PERF_SEL_INST_CYCLES_TEX = 110
SQ_PERF_SEL_INST_CYCLES_FLAT = 111
SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 112
SQ_PERF_SEL_INST_CYCLES_EXP = 113
SQ_PERF_SEL_INST_CYCLES_GDS = 114
SQ_PERF_SEL_VALU_STARVE = 115
SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 116
SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 117
SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 118
SQ_PERF_SEL_VMEM_BUS_ACTIVE = 119
SQ_PERF_SEL_VMEM_BUS_STALL = 120
SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 121
SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 122
SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 123
SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 124
SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 125
SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 126
SQ_PERF_SEL_SALU_PIPE_STALL = 127
SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 128
SQ_PERF_SEL_MSG_BUS_BUSY = 129
SQ_PERF_SEL_EXP_REQ_BUS_STALL = 130
SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 131
SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 132
SQ_PERF_SEL_EXP_BUS0_BUSY = 133
SQ_PERF_SEL_EXP_BUS1_BUSY = 134
SQ_PERF_SEL_INST_CACHE_REQ_STALL = 135
SQ_PERF_SEL_USER0 = 136
SQ_PERF_SEL_USER1 = 137
SQ_PERF_SEL_USER2 = 138
SQ_PERF_SEL_USER3 = 139
SQ_PERF_SEL_USER4 = 140
SQ_PERF_SEL_USER5 = 141
SQ_PERF_SEL_USER6 = 142
SQ_PERF_SEL_USER7 = 143
SQ_PERF_SEL_USER8 = 144
SQ_PERF_SEL_USER9 = 145
SQ_PERF_SEL_USER10 = 146
SQ_PERF_SEL_USER11 = 147
SQ_PERF_SEL_USER12 = 148
SQ_PERF_SEL_USER13 = 149
SQ_PERF_SEL_USER14 = 150
SQ_PERF_SEL_USER15 = 151
SQ_PERF_SEL_USER_LEVEL0 = 152
SQ_PERF_SEL_USER_LEVEL1 = 153
SQ_PERF_SEL_USER_LEVEL2 = 154
SQ_PERF_SEL_USER_LEVEL3 = 155
SQ_PERF_SEL_USER_LEVEL4 = 156
SQ_PERF_SEL_USER_LEVEL5 = 157
SQ_PERF_SEL_USER_LEVEL6 = 158
SQ_PERF_SEL_USER_LEVEL7 = 159
SQ_PERF_SEL_USER_LEVEL8 = 160
SQ_PERF_SEL_USER_LEVEL9 = 161
SQ_PERF_SEL_USER_LEVEL10 = 162
SQ_PERF_SEL_USER_LEVEL11 = 163
SQ_PERF_SEL_USER_LEVEL12 = 164
SQ_PERF_SEL_USER_LEVEL13 = 165
SQ_PERF_SEL_USER_LEVEL14 = 166
SQ_PERF_SEL_USER_LEVEL15 = 167
SQ_PERF_SEL_VALU_RETURN_SDST = 168
SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 169
SQ_PERF_SEL_INSTS_VALU_TRANS = 170
SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 171
SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 172
SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD = 173
SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 174
SQ_PERF_SEL_INSTS_VALU_VINTERP = 175
SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP = 176
SQ_PERF_SEL_OVERFLOW_PREV = 177
SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 178
SQ_PERF_SEL_INSTS_VALU_1_PASS = 179
SQ_PERF_SEL_INSTS_VALU_2_PASS = 180
SQ_PERF_SEL_INSTS_VALU_4_PASS = 181
SQ_PERF_SEL_INSTS_VALU_DP = 182
SQ_PERF_SEL_SP_CONST_CYCLES = 183
SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 184
SQ_PERF_SEL_ITEMS_VALU = 185
SQ_PERF_SEL_ITEMS_MAX_VALU = 186
SQ_PERF_SEL_ITEM_CYCLES_VMEM = 187
SQ_PERF_SEL_DUMMY_END = 188
SQ_PERF_SEL_DUMMY_LAST = 255
SQC_PERF_SEL_LDS_BANK_CONFLICT = 256
SQC_PERF_SEL_LDS_ADDR_CONFLICT = 257
SQC_PERF_SEL_LDS_UNALIGNED_STALL = 258
SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 259
SQC_PERF_SEL_LDS_ATOMIC_RETURN = 260
SQC_PERF_SEL_LDS_IDX_ACTIVE = 261
SQC_PERF_SEL_LDS_ADDR_STALL = 262
SQC_PERF_SEL_LDS_ADDR_ACTIVE = 263
SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 264
SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 265
SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 266
SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 267
SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 268
SQC_PERF_SEL_ICACHE_REQ = 269
SQC_PERF_SEL_ICACHE_HITS = 270
SQC_PERF_SEL_ICACHE_MISSES = 271
SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 272
SQC_PERF_SEL_ICACHE_INVAL_INST = 273
SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 274
SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 275
SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 276
SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 277
SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 278
SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 279
SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 280
SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 281
SQC_PERF_SEL_TC_REQ = 282
SQC_PERF_SEL_TC_INST_REQ = 283
SQC_PERF_SEL_TC_DATA_READ_REQ = 284
SQC_PERF_SEL_TC_STALL = 285
SQC_PERF_SEL_TC_STARVE = 286
SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 287
SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 288
SQC_PERF_SEL_ICACHE_CACHE_STALLED = 289
SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 290
SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 291
SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 292
SQC_PERF_SEL_DCACHE_REQ = 293
SQC_PERF_SEL_DCACHE_HITS = 294
SQC_PERF_SEL_DCACHE_MISSES = 295
SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 296
SQC_PERF_SEL_DCACHE_INVAL_INST = 297
SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 298
SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 299
SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 300
SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 301
SQC_PERF_SEL_DCACHE_CACHE_STALLED = 302
SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 303
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 304
SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 305
SQC_PERF_SEL_DCACHE_REQ_READ_1 = 306
SQC_PERF_SEL_DCACHE_REQ_READ_2 = 307
SQC_PERF_SEL_DCACHE_REQ_READ_4 = 308
SQC_PERF_SEL_DCACHE_REQ_READ_8 = 309
SQC_PERF_SEL_DCACHE_REQ_READ_16 = 310
SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 311
SQC_PERF_SEL_SQ_DCACHE_REQS = 312
SQC_PERF_SEL_DCACHE_FLAT_REQ = 313
SQC_PERF_SEL_TD_VGPR_BUSY = 314
SQC_PERF_SEL_LDS_VGPR_BUSY = 315
SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 316
SQC_PERF_SEL_ICACHE_GCR = 317
SQC_PERF_SEL_ICACHE_GCR_HITS = 318
SQC_PERF_SEL_DCACHE_GCR = 319
SQC_PERF_SEL_DCACHE_GCR_HITS = 320
SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 321
SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 322
SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 323
SQC_PERF_SEL_DUMMY_LAST = 324
SP_PERF_SEL_DST_BUF_ALLOC_STALL = 448
SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 449
SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 450
SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 451
SP_PERF_SEL_DST_BUF_ODD_DIRTY = 452
SP_PERF_SEL_SRC_CACHE_HIT_B0 = 453
SP_PERF_SEL_SRC_CACHE_HIT_B1 = 454
SP_PERF_SEL_SRC_CACHE_HIT_B2 = 455
SP_PERF_SEL_SRC_CACHE_HIT_B3 = 456
SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 457
SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 458
SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 459
SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 460
SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 461
SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 462
SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 463
SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 464
SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 465
SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 466
SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 467
SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 468
SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 469
SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 470
SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 471
SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 472
SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 473
SP_PERF_SEL_VALU_OPERAND = 474
SP_PERF_SEL_VALU_VGPR_OPERAND = 475
SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 476
SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 477
SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 478
SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 479
SP_PERF_SEL_VALU_STALL = 480
SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 481
SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 482
SP_PERF_SEL_VALU_STALL_VDST_FWD = 483
SP_PERF_SEL_VALU_STALL_SDST_FWD = 484
SP_PERF_SEL_VALU_STALL_DST_STALL = 485
SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 486
SP_PERF_SEL_VGPR_VMEM_RD = 487
SP_PERF_SEL_VGPR_EXP_RD = 488
SP_PERF_SEL_VGPR_SPI_WR = 489
SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 490
SP_PERF_SEL_VGPR_WR = 491
SP_PERF_SEL_VGPR_RD = 492
SP_PERF_SEL_DUMMY_LAST = 493
SQ_PERF_SEL_NONE2 = 511
SQ_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'SQ_ROUND_MODE'
SQ_ROUND_MODE__enumvalues = {
0: 'SQ_ROUND_NEAREST_EVEN',
1: 'SQ_ROUND_PLUS_INFINITY',
2: 'SQ_ROUND_MINUS_INFINITY',
3: 'SQ_ROUND_TO_ZERO',
}
SQ_ROUND_NEAREST_EVEN = 0
SQ_ROUND_PLUS_INFINITY = 1
SQ_ROUND_MINUS_INFINITY = 2
SQ_ROUND_TO_ZERO = 3
SQ_ROUND_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_RSRC_BUF_TYPE'
SQ_RSRC_BUF_TYPE__enumvalues = {
0: 'SQ_RSRC_BUF',
1: 'SQ_RSRC_BUF_RSVD_1',
2: 'SQ_RSRC_BUF_RSVD_2',
3: 'SQ_RSRC_BUF_RSVD_3',
}
SQ_RSRC_BUF = 0
SQ_RSRC_BUF_RSVD_1 = 1
SQ_RSRC_BUF_RSVD_2 = 2
SQ_RSRC_BUF_RSVD_3 = 3
SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_RSRC_FLAT_TYPE'
SQ_RSRC_FLAT_TYPE__enumvalues = {
0: 'SQ_RSRC_FLAT_RSVD_0',
1: 'SQ_RSRC_FLAT',
2: 'SQ_RSRC_FLAT_RSVD_2',
3: 'SQ_RSRC_FLAT_RSVD_3',
}
SQ_RSRC_FLAT_RSVD_0 = 0
SQ_RSRC_FLAT = 1
SQ_RSRC_FLAT_RSVD_2 = 2
SQ_RSRC_FLAT_RSVD_3 = 3
SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_RSRC_IMG_TYPE'
SQ_RSRC_IMG_TYPE__enumvalues = {
0: 'SQ_RSRC_IMG_RSVD_0',
1: 'SQ_RSRC_IMG_RSVD_1',
2: 'SQ_RSRC_IMG_RSVD_2',
3: 'SQ_RSRC_IMG_RSVD_3',
4: 'SQ_RSRC_IMG_RSVD_4',
5: 'SQ_RSRC_IMG_RSVD_5',
6: 'SQ_RSRC_IMG_RSVD_6',
7: 'SQ_RSRC_IMG_RSVD_7',
8: 'SQ_RSRC_IMG_1D',
9: 'SQ_RSRC_IMG_2D',
10: 'SQ_RSRC_IMG_3D',
11: 'SQ_RSRC_IMG_CUBE',
12: 'SQ_RSRC_IMG_1D_ARRAY',
13: 'SQ_RSRC_IMG_2D_ARRAY',
14: 'SQ_RSRC_IMG_2D_MSAA',
15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY',
}
SQ_RSRC_IMG_RSVD_0 = 0
SQ_RSRC_IMG_RSVD_1 = 1
SQ_RSRC_IMG_RSVD_2 = 2
SQ_RSRC_IMG_RSVD_3 = 3
SQ_RSRC_IMG_RSVD_4 = 4
SQ_RSRC_IMG_RSVD_5 = 5
SQ_RSRC_IMG_RSVD_6 = 6
SQ_RSRC_IMG_RSVD_7 = 7
SQ_RSRC_IMG_1D = 8
SQ_RSRC_IMG_2D = 9
SQ_RSRC_IMG_3D = 10
SQ_RSRC_IMG_CUBE = 11
SQ_RSRC_IMG_1D_ARRAY = 12
SQ_RSRC_IMG_2D_ARRAY = 13
SQ_RSRC_IMG_2D_MSAA = 14
SQ_RSRC_IMG_2D_MSAA_ARRAY = 15
SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_SEL_XYZW01'
SQ_SEL_XYZW01__enumvalues = {
0: 'SQ_SEL_0',
1: 'SQ_SEL_1',
2: 'SQ_SEL_N_BC_1',
3: 'SQ_SEL_RESERVED_1',
4: 'SQ_SEL_X',
5: 'SQ_SEL_Y',
6: 'SQ_SEL_Z',
7: 'SQ_SEL_W',
}
SQ_SEL_0 = 0
SQ_SEL_1 = 1
SQ_SEL_N_BC_1 = 2
SQ_SEL_RESERVED_1 = 3
SQ_SEL_X = 4
SQ_SEL_Y = 5
SQ_SEL_Z = 6
SQ_SEL_W = 7
SQ_SEL_XYZW01 = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_ANISO_RATIO'
SQ_TEX_ANISO_RATIO__enumvalues = {
0: 'SQ_TEX_ANISO_RATIO_1',
1: 'SQ_TEX_ANISO_RATIO_2',
2: 'SQ_TEX_ANISO_RATIO_4',
3: 'SQ_TEX_ANISO_RATIO_8',
4: 'SQ_TEX_ANISO_RATIO_16',
}
SQ_TEX_ANISO_RATIO_1 = 0
SQ_TEX_ANISO_RATIO_2 = 1
SQ_TEX_ANISO_RATIO_4 = 2
SQ_TEX_ANISO_RATIO_8 = 3
SQ_TEX_ANISO_RATIO_16 = 4
SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_BORDER_COLOR'
SQ_TEX_BORDER_COLOR__enumvalues = {
0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK',
1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK',
2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE',
3: 'SQ_TEX_BORDER_COLOR_REGISTER',
}
SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0
SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1
SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2
SQ_TEX_BORDER_COLOR_REGISTER = 3
SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_CLAMP'
SQ_TEX_CLAMP__enumvalues = {
0: 'SQ_TEX_WRAP',
1: 'SQ_TEX_MIRROR',
2: 'SQ_TEX_CLAMP_LAST_TEXEL',
3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL',
4: 'SQ_TEX_CLAMP_HALF_BORDER',
5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER',
6: 'SQ_TEX_CLAMP_BORDER',
7: 'SQ_TEX_MIRROR_ONCE_BORDER',
}
SQ_TEX_WRAP = 0
SQ_TEX_MIRROR = 1
SQ_TEX_CLAMP_LAST_TEXEL = 2
SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3
SQ_TEX_CLAMP_HALF_BORDER = 4
SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5
SQ_TEX_CLAMP_BORDER = 6
SQ_TEX_MIRROR_ONCE_BORDER = 7
SQ_TEX_CLAMP = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_DEPTH_COMPARE'
SQ_TEX_DEPTH_COMPARE__enumvalues = {
0: 'SQ_TEX_DEPTH_COMPARE_NEVER',
1: 'SQ_TEX_DEPTH_COMPARE_LESS',
2: 'SQ_TEX_DEPTH_COMPARE_EQUAL',
3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL',
4: 'SQ_TEX_DEPTH_COMPARE_GREATER',
5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL',
6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL',
7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS',
}
SQ_TEX_DEPTH_COMPARE_NEVER = 0
SQ_TEX_DEPTH_COMPARE_LESS = 1
SQ_TEX_DEPTH_COMPARE_EQUAL = 2
SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3
SQ_TEX_DEPTH_COMPARE_GREATER = 4
SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5
SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6
SQ_TEX_DEPTH_COMPARE_ALWAYS = 7
SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_MIP_FILTER'
SQ_TEX_MIP_FILTER__enumvalues = {
0: 'SQ_TEX_MIP_FILTER_NONE',
1: 'SQ_TEX_MIP_FILTER_POINT',
2: 'SQ_TEX_MIP_FILTER_LINEAR',
3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ',
}
SQ_TEX_MIP_FILTER_NONE = 0
SQ_TEX_MIP_FILTER_POINT = 1
SQ_TEX_MIP_FILTER_LINEAR = 2
SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3
SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_XY_FILTER'
SQ_TEX_XY_FILTER__enumvalues = {
0: 'SQ_TEX_XY_FILTER_POINT',
1: 'SQ_TEX_XY_FILTER_BILINEAR',
2: 'SQ_TEX_XY_FILTER_ANISO_POINT',
3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR',
}
SQ_TEX_XY_FILTER_POINT = 0
SQ_TEX_XY_FILTER_BILINEAR = 1
SQ_TEX_XY_FILTER_ANISO_POINT = 2
SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3
SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TEX_Z_FILTER'
SQ_TEX_Z_FILTER__enumvalues = {
0: 'SQ_TEX_Z_FILTER_NONE',
1: 'SQ_TEX_Z_FILTER_POINT',
2: 'SQ_TEX_Z_FILTER_LINEAR',
}
SQ_TEX_Z_FILTER_NONE = 0
SQ_TEX_Z_FILTER_POINT = 1
SQ_TEX_Z_FILTER_LINEAR = 2
SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_MODE'
SQ_TT_MODE__enumvalues = {
0: 'SQ_TT_MODE_OFF',
1: 'SQ_TT_MODE_ON',
2: 'SQ_TT_MODE_GLOBAL',
3: 'SQ_TT_MODE_DETAIL',
}
SQ_TT_MODE_OFF = 0
SQ_TT_MODE_ON = 1
SQ_TT_MODE_GLOBAL = 2
SQ_TT_MODE_DETAIL = 3
SQ_TT_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_RT_FREQ'
SQ_TT_RT_FREQ__enumvalues = {
0: 'SQ_TT_RT_FREQ_NEVER',
1: 'SQ_TT_RT_FREQ_1024_CLK',
2: 'SQ_TT_RT_FREQ_4096_CLK',
}
SQ_TT_RT_FREQ_NEVER = 0
SQ_TT_RT_FREQ_1024_CLK = 1
SQ_TT_RT_FREQ_4096_CLK = 2
SQ_TT_RT_FREQ = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE'
SQ_TT_TOKEN_MASK_INST_EXCLUDE__enumvalues = {
1: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT',
2: 'SQ_TT_INST_EXCLUDE_EXPGNT234_BIT',
}
SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT = 1
SQ_TT_INST_EXCLUDE_EXPGNT234_BIT = 2
SQ_TT_TOKEN_MASK_INST_EXCLUDE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT'
SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT__enumvalues = {
0: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT',
1: 'SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT',
}
SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT = 0
SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT = 1
SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_TOKEN_MASK_REG_EXCLUDE'
SQ_TT_TOKEN_MASK_REG_EXCLUDE__enumvalues = {
1: 'SQ_TT_REG_EXCLUDE_USER_DATA_BIT',
2: 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT',
4: 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT',
}
SQ_TT_REG_EXCLUDE_USER_DATA_BIT = 1
SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT = 2
SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT = 4
SQ_TT_TOKEN_MASK_REG_EXCLUDE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT'
SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT__enumvalues = {
0: 'SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT',
1: 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT',
2: 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT',
}
SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT = 0
SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT = 1
SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT = 2
SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE'
SQ_TT_TOKEN_MASK_REG_INCLUDE__enumvalues = {
1: 'SQ_TT_TOKEN_MASK_SQDEC_BIT',
2: 'SQ_TT_TOKEN_MASK_SHDEC_BIT',
4: 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT',
8: 'SQ_TT_TOKEN_MASK_COMP_BIT',
16: 'SQ_TT_TOKEN_MASK_CONTEXT_BIT',
32: 'SQ_TT_TOKEN_MASK_CONFIG_BIT',
64: 'SQ_TT_TOKEN_MASK_ALL_BIT',
128: 'SQ_TT_TOKEN_MASK_RSVD_BIT',
}
SQ_TT_TOKEN_MASK_SQDEC_BIT = 1
SQ_TT_TOKEN_MASK_SHDEC_BIT = 2
SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 4
SQ_TT_TOKEN_MASK_COMP_BIT = 8
SQ_TT_TOKEN_MASK_CONTEXT_BIT = 16
SQ_TT_TOKEN_MASK_CONFIG_BIT = 32
SQ_TT_TOKEN_MASK_ALL_BIT = 64
SQ_TT_TOKEN_MASK_RSVD_BIT = 128
SQ_TT_TOKEN_MASK_REG_INCLUDE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT'
SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT__enumvalues = {
0: 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT',
1: 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT',
2: 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT',
3: 'SQ_TT_TOKEN_MASK_COMP_SHIFT',
4: 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT',
5: 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT',
6: 'SQ_TT_TOKEN_MASK_ALL_SHIFT',
7: 'SQ_TT_TOKEN_MASK_RSVD_SHIFT',
}
SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0
SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 1
SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 2
SQ_TT_TOKEN_MASK_COMP_SHIFT = 3
SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 4
SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 5
SQ_TT_TOKEN_MASK_ALL_SHIFT = 6
SQ_TT_TOKEN_MASK_RSVD_SHIFT = 7
SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT'
SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT__enumvalues = {
0: 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT',
1: 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT',
2: 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT',
3: 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT',
4: 'SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT',
5: 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT',
6: 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT',
7: 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT',
8: 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT',
9: 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT',
10: 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT',
11: 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT',
}
SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0
SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 1
SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 2
SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 3
SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT = 4
SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 5
SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 6
SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 7
SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 8
SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 9
SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 10
SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 11
SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_UTIL_TIMER'
SQ_TT_UTIL_TIMER__enumvalues = {
0: 'SQ_TT_UTIL_TIMER_100_CLK',
1: 'SQ_TT_UTIL_TIMER_250_CLK',
}
SQ_TT_UTIL_TIMER_100_CLK = 0
SQ_TT_UTIL_TIMER_250_CLK = 1
SQ_TT_UTIL_TIMER = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_WAVESTART_MODE'
SQ_TT_WAVESTART_MODE__enumvalues = {
0: 'SQ_TT_WAVESTART_MODE_SHORT',
1: 'SQ_TT_WAVESTART_MODE_ALLOC',
2: 'SQ_TT_WAVESTART_MODE_PBB_ID',
}
SQ_TT_WAVESTART_MODE_SHORT = 0
SQ_TT_WAVESTART_MODE_ALLOC = 1
SQ_TT_WAVESTART_MODE_PBB_ID = 2
SQ_TT_WAVESTART_MODE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_WTYPE_INCLUDE'
SQ_TT_WTYPE_INCLUDE__enumvalues = {
1: 'SQ_TT_WTYPE_INCLUDE_PS_BIT',
2: 'SQ_TT_WTYPE_INCLUDE_RSVD0_BIT',
4: 'SQ_TT_WTYPE_INCLUDE_GS_BIT',
8: 'SQ_TT_WTYPE_INCLUDE_RSVD1_BIT',
16: 'SQ_TT_WTYPE_INCLUDE_HS_BIT',
32: 'SQ_TT_WTYPE_INCLUDE_RSVD2_BIT',
64: 'SQ_TT_WTYPE_INCLUDE_CS_BIT',
}
SQ_TT_WTYPE_INCLUDE_PS_BIT = 1
SQ_TT_WTYPE_INCLUDE_RSVD0_BIT = 2
SQ_TT_WTYPE_INCLUDE_GS_BIT = 4
SQ_TT_WTYPE_INCLUDE_RSVD1_BIT = 8
SQ_TT_WTYPE_INCLUDE_HS_BIT = 16
SQ_TT_WTYPE_INCLUDE_RSVD2_BIT = 32
SQ_TT_WTYPE_INCLUDE_CS_BIT = 64
SQ_TT_WTYPE_INCLUDE = ctypes.c_uint32 # enum
# values for enumeration 'SQ_TT_WTYPE_INCLUDE_SHIFT'
SQ_TT_WTYPE_INCLUDE_SHIFT__enumvalues = {
0: 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT',
1: 'SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT',
2: 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT',
3: 'SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT',
4: 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT',
5: 'SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT',
6: 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT',
}
SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0
SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT = 1
SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 2
SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT = 3
SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 4
SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT = 5
SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 6
SQ_TT_WTYPE_INCLUDE_SHIFT = ctypes.c_uint32 # enum
# values for enumeration 'SQ_WATCH_MODES'
SQ_WATCH_MODES__enumvalues = {
0: 'SQ_WATCH_MODE_READ',
1: 'SQ_WATCH_MODE_NONREAD',
2: 'SQ_WATCH_MODE_ATOMIC',
3: 'SQ_WATCH_MODE_ALL',
}
SQ_WATCH_MODE_READ = 0
SQ_WATCH_MODE_NONREAD = 1
SQ_WATCH_MODE_ATOMIC = 2
SQ_WATCH_MODE_ALL = 3
SQ_WATCH_MODES = ctypes.c_uint32 # enum
# values for enumeration 'SQ_WAVE_FWD_PROG_INTERVAL'
SQ_WAVE_FWD_PROG_INTERVAL__enumvalues = {
0: 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER',
1: 'SQ_WAVE_FWD_PROG_INTERVAL_256',
2: 'SQ_WAVE_FWD_PROG_INTERVAL_1024',
3: 'SQ_WAVE_FWD_PROG_INTERVAL_4096',
}
SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0
SQ_WAVE_FWD_PROG_INTERVAL_256 = 1
SQ_WAVE_FWD_PROG_INTERVAL_1024 = 2
SQ_WAVE_FWD_PROG_INTERVAL_4096 = 3
SQ_WAVE_FWD_PROG_INTERVAL = ctypes.c_uint32 # enum
# values for enumeration 'SQ_WAVE_IB_ECC_ST'
SQ_WAVE_IB_ECC_ST__enumvalues = {
0: 'SQ_WAVE_IB_ECC_CLEAN',
1: 'SQ_WAVE_IB_ECC_ERR_CONTINUE',
2: 'SQ_WAVE_IB_ECC_ERR_HALT',
3: 'SQ_WAVE_IB_ECC_WITH_ERR_MSG',
}
SQ_WAVE_IB_ECC_CLEAN = 0
SQ_WAVE_IB_ECC_ERR_CONTINUE = 1
SQ_WAVE_IB_ECC_ERR_HALT = 2
SQ_WAVE_IB_ECC_WITH_ERR_MSG = 3
SQ_WAVE_IB_ECC_ST = ctypes.c_uint32 # enum
# values for enumeration 'SQ_WAVE_SCHED_MODES'
SQ_WAVE_SCHED_MODES__enumvalues = {
0: 'SQ_WAVE_SCHED_MODE_NORMAL',
1: 'SQ_WAVE_SCHED_MODE_EXPERT',
2: 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST',
}
SQ_WAVE_SCHED_MODE_NORMAL = 0
SQ_WAVE_SCHED_MODE_EXPERT = 1
SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 2
SQ_WAVE_SCHED_MODES = ctypes.c_uint32 # enum
# values for enumeration 'SQ_WAVE_TYPE'
SQ_WAVE_TYPE__enumvalues = {
0: 'SQ_WAVE_TYPE_PS',
1: 'SQ_WAVE_TYPE_RSVD0',
2: 'SQ_WAVE_TYPE_GS',
3: 'SQ_WAVE_TYPE_RSVD1',
4: 'SQ_WAVE_TYPE_HS',
5: 'SQ_WAVE_TYPE_RSVD2',
6: 'SQ_WAVE_TYPE_CS',
7: 'SQ_WAVE_TYPE_PS1',
8: 'SQ_WAVE_TYPE_PS2',
9: 'SQ_WAVE_TYPE_PS3',
}
SQ_WAVE_TYPE_PS = 0
SQ_WAVE_TYPE_RSVD0 = 1
SQ_WAVE_TYPE_GS = 2
SQ_WAVE_TYPE_RSVD1 = 3
SQ_WAVE_TYPE_HS = 4
SQ_WAVE_TYPE_RSVD2 = 5
SQ_WAVE_TYPE_CS = 6
SQ_WAVE_TYPE_PS1 = 7
SQ_WAVE_TYPE_PS2 = 8
SQ_WAVE_TYPE_PS3 = 9
SQ_WAVE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'CSCNTL_TYPE'
CSCNTL_TYPE__enumvalues = {
0: 'CSCNTL_TYPE_TG',
1: 'CSCNTL_TYPE_STATE',
2: 'CSCNTL_TYPE_EVENT',
3: 'CSCNTL_TYPE_PRIVATE',
}
CSCNTL_TYPE_TG = 0
CSCNTL_TYPE_STATE = 1
CSCNTL_TYPE_EVENT = 2
CSCNTL_TYPE_PRIVATE = 3
CSCNTL_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'CSDATA_TYPE'
CSDATA_TYPE__enumvalues = {
0: 'CSDATA_TYPE_TG',
1: 'CSDATA_TYPE_STATE',
2: 'CSDATA_TYPE_EVENT',
3: 'CSDATA_TYPE_PRIVATE',
}
CSDATA_TYPE_TG = 0
CSDATA_TYPE_STATE = 1
CSDATA_TYPE_EVENT = 2
CSDATA_TYPE_PRIVATE = 3
CSDATA_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'GE1_PERFCOUNT_SELECT'
GE1_PERFCOUNT_SELECT__enumvalues = {
0: 'ge1_assembler_busy',
1: 'ge1_assembler_stalled',
2: 'ge1_dma_busy',
3: 'ge1_dma_lat_bin_0',
4: 'ge1_dma_lat_bin_1',
5: 'ge1_dma_lat_bin_2',
6: 'ge1_dma_lat_bin_3',
7: 'ge1_dma_lat_bin_4',
8: 'ge1_dma_lat_bin_5',
9: 'ge1_dma_lat_bin_6',
10: 'ge1_dma_lat_bin_7',
11: 'ge1_dma_return_cl0',
12: 'ge1_dma_return_cl1',
13: 'ge1_dma_utcl1_consecutive_retry_event',
14: 'ge1_dma_utcl1_request_event',
15: 'ge1_dma_utcl1_retry_event',
16: 'ge1_dma_utcl1_stall_event',
17: 'ge1_dma_utcl1_stall_utcl2_event',
18: 'ge1_dma_utcl1_translation_hit_event',
19: 'ge1_dma_utcl1_translation_miss_event',
20: 'ge1_assembler_dma_starved',
21: 'ge1_rbiu_di_fifo_stalled_p0',
22: 'ge1_rbiu_di_fifo_starved_p0',
23: 'ge1_rbiu_dr_fifo_stalled_p0',
24: 'ge1_rbiu_dr_fifo_starved_p0',
25: 'ge1_sclk_reg_vld',
26: 'ge1_stat_busy',
27: 'ge1_stat_no_dma_busy',
28: 'ge1_pipe0_to_pipe1',
29: 'ge1_pipe1_to_pipe0',
30: 'ge1_dma_return_size_cl0',
31: 'ge1_dma_return_size_cl1',
32: 'ge1_small_draws_one_instance',
33: 'ge1_sclk_input_vld',
34: 'ge1_prim_group_limit_hit',
35: 'ge1_unopt_multi_instance_draws',
36: 'ge1_rbiu_di_fifo_stalled_p1',
37: 'ge1_rbiu_di_fifo_starved_p1',
38: 'ge1_rbiu_dr_fifo_stalled_p1',
39: 'ge1_rbiu_dr_fifo_starved_p1',
}
ge1_assembler_busy = 0
ge1_assembler_stalled = 1
ge1_dma_busy = 2
ge1_dma_lat_bin_0 = 3
ge1_dma_lat_bin_1 = 4
ge1_dma_lat_bin_2 = 5
ge1_dma_lat_bin_3 = 6
ge1_dma_lat_bin_4 = 7
ge1_dma_lat_bin_5 = 8
ge1_dma_lat_bin_6 = 9
ge1_dma_lat_bin_7 = 10
ge1_dma_return_cl0 = 11
ge1_dma_return_cl1 = 12
ge1_dma_utcl1_consecutive_retry_event = 13
ge1_dma_utcl1_request_event = 14
ge1_dma_utcl1_retry_event = 15
ge1_dma_utcl1_stall_event = 16
ge1_dma_utcl1_stall_utcl2_event = 17
ge1_dma_utcl1_translation_hit_event = 18
ge1_dma_utcl1_translation_miss_event = 19
ge1_assembler_dma_starved = 20
ge1_rbiu_di_fifo_stalled_p0 = 21
ge1_rbiu_di_fifo_starved_p0 = 22
ge1_rbiu_dr_fifo_stalled_p0 = 23
ge1_rbiu_dr_fifo_starved_p0 = 24
ge1_sclk_reg_vld = 25
ge1_stat_busy = 26
ge1_stat_no_dma_busy = 27
ge1_pipe0_to_pipe1 = 28
ge1_pipe1_to_pipe0 = 29
ge1_dma_return_size_cl0 = 30
ge1_dma_return_size_cl1 = 31
ge1_small_draws_one_instance = 32
ge1_sclk_input_vld = 33
ge1_prim_group_limit_hit = 34
ge1_unopt_multi_instance_draws = 35
ge1_rbiu_di_fifo_stalled_p1 = 36
ge1_rbiu_di_fifo_starved_p1 = 37
ge1_rbiu_dr_fifo_stalled_p1 = 38
ge1_rbiu_dr_fifo_starved_p1 = 39
GE1_PERFCOUNT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'GE2_DIST_PERFCOUNT_SELECT'
GE2_DIST_PERFCOUNT_SELECT__enumvalues = {
0: 'ge_dist_hs_done',
1: 'ge_dist_hs_done_latency_se0',
2: 'ge_dist_hs_done_latency_se1',
3: 'ge_dist_hs_done_latency_se2',
4: 'ge_dist_hs_done_latency_se3',
5: 'ge_dist_hs_done_latency_se4',
6: 'ge_dist_hs_done_latency_se5',
7: 'ge_dist_hs_done_latency_se6',
8: 'ge_dist_hs_done_latency_se7',
9: 'ge_dist_inside_tf_bin_0',
10: 'ge_dist_inside_tf_bin_1',
11: 'ge_dist_inside_tf_bin_2',
12: 'ge_dist_inside_tf_bin_3',
13: 'ge_dist_inside_tf_bin_4',
14: 'ge_dist_inside_tf_bin_5',
15: 'ge_dist_inside_tf_bin_6',
16: 'ge_dist_inside_tf_bin_7',
17: 'ge_dist_inside_tf_bin_8',
18: 'ge_dist_null_patch',
19: 'ge_dist_sclk_core_vld',
20: 'ge_dist_sclk_wd_te11_vld',
21: 'ge_dist_tfreq_lat_bin_0',
22: 'ge_dist_tfreq_lat_bin_1',
23: 'ge_dist_tfreq_lat_bin_2',
24: 'ge_dist_tfreq_lat_bin_3',
25: 'ge_dist_tfreq_lat_bin_4',
26: 'ge_dist_tfreq_lat_bin_5',
27: 'ge_dist_tfreq_lat_bin_6',
28: 'ge_dist_tfreq_lat_bin_7',
29: 'ge_dist_tfreq_utcl1_consecutive_retry_event',
30: 'ge_dist_tfreq_utcl1_request_event',
31: 'ge_dist_tfreq_utcl1_retry_event',
32: 'ge_dist_tfreq_utcl1_stall_event',
33: 'ge_dist_tfreq_utcl1_stall_utcl2_event',
34: 'ge_dist_tfreq_utcl1_translation_hit_event',
35: 'ge_dist_tfreq_utcl1_translation_miss_event',
36: 'ge_dist_vs_pc_stall',
37: 'ge_dist_pc_feorder_fifo_full',
38: 'ge_dist_pc_ge_manager_busy',
39: 'ge_dist_pc_req_stall_se0',
40: 'ge_dist_pc_req_stall_se1',
41: 'ge_dist_pc_req_stall_se2',
42: 'ge_dist_pc_req_stall_se3',
43: 'ge_dist_pc_req_stall_se4',
44: 'ge_dist_pc_req_stall_se5',
45: 'ge_dist_pc_req_stall_se6',
46: 'ge_dist_pc_req_stall_se7',
47: 'ge_dist_pc_space_zero',
48: 'ge_dist_sclk_input_vld',
49: 'ge_dist_reserved',
50: 'ge_dist_wd_te11_busy',
51: 'ge_dist_te11_starved',
52: 'ge_dist_switch_mode_stall',
53: 'ge_all_tf_eq',
54: 'ge_all_tf2',
55: 'ge_all_tf3',
56: 'ge_all_tf4',
57: 'ge_all_tf5',
58: 'ge_all_tf6',
59: 'ge_se0_te11_starved_on_hs_done',
60: 'ge_se1_te11_starved_on_hs_done',
61: 'ge_se2_te11_starved_on_hs_done',
62: 'ge_se3_te11_starved_on_hs_done',
63: 'ge_se4_te11_starved_on_hs_done',
64: 'ge_se5_te11_starved_on_hs_done',
65: 'ge_se6_te11_starved_on_hs_done',
66: 'ge_se7_te11_starved_on_hs_done',
67: 'ge_dist_op_fifo_full_starve',
68: 'ge_dist_hs_done_se0',
69: 'ge_dist_hs_done_se1',
70: 'ge_dist_hs_done_se2',
71: 'ge_dist_hs_done_se3',
72: 'ge_dist_hs_done_se4',
73: 'ge_dist_hs_done_se5',
74: 'ge_dist_hs_done_se6',
75: 'ge_dist_hs_done_se7',
76: 'ge_dist_hs_done_latency',
77: 'ge_dist_distributer_busy',
78: 'ge_tf_ret_data_stalling_hs_done',
79: 'ge_num_of_no_dist_patches',
80: 'ge_num_of_donut_dist_patches',
81: 'ge_num_of_patch_dist_patches',
82: 'ge_num_of_se_switches_due_to_patch_accum',
83: 'ge_num_of_se_switches_due_to_donut',
84: 'ge_num_of_se_switches_due_to_trap',
85: 'ge_num_of_hs_alloc_events',
86: 'ge_agm_gcr_req',
87: 'ge_agm_gcr_tag_stall',
88: 'ge_agm_gcr_crd_stall',
89: 'ge_agm_gcr_stall',
90: 'ge_agm_gcr_latency',
91: 'ge_distclk_vld',
}
ge_dist_hs_done = 0
ge_dist_hs_done_latency_se0 = 1
ge_dist_hs_done_latency_se1 = 2
ge_dist_hs_done_latency_se2 = 3
ge_dist_hs_done_latency_se3 = 4
ge_dist_hs_done_latency_se4 = 5
ge_dist_hs_done_latency_se5 = 6
ge_dist_hs_done_latency_se6 = 7
ge_dist_hs_done_latency_se7 = 8
ge_dist_inside_tf_bin_0 = 9
ge_dist_inside_tf_bin_1 = 10
ge_dist_inside_tf_bin_2 = 11
ge_dist_inside_tf_bin_3 = 12
ge_dist_inside_tf_bin_4 = 13
ge_dist_inside_tf_bin_5 = 14
ge_dist_inside_tf_bin_6 = 15
ge_dist_inside_tf_bin_7 = 16
ge_dist_inside_tf_bin_8 = 17
ge_dist_null_patch = 18
ge_dist_sclk_core_vld = 19
ge_dist_sclk_wd_te11_vld = 20
ge_dist_tfreq_lat_bin_0 = 21
ge_dist_tfreq_lat_bin_1 = 22
ge_dist_tfreq_lat_bin_2 = 23
ge_dist_tfreq_lat_bin_3 = 24
ge_dist_tfreq_lat_bin_4 = 25
ge_dist_tfreq_lat_bin_5 = 26
ge_dist_tfreq_lat_bin_6 = 27
ge_dist_tfreq_lat_bin_7 = 28
ge_dist_tfreq_utcl1_consecutive_retry_event = 29
ge_dist_tfreq_utcl1_request_event = 30
ge_dist_tfreq_utcl1_retry_event = 31
ge_dist_tfreq_utcl1_stall_event = 32
ge_dist_tfreq_utcl1_stall_utcl2_event = 33
ge_dist_tfreq_utcl1_translation_hit_event = 34
ge_dist_tfreq_utcl1_translation_miss_event = 35
ge_dist_vs_pc_stall = 36
ge_dist_pc_feorder_fifo_full = 37
ge_dist_pc_ge_manager_busy = 38
ge_dist_pc_req_stall_se0 = 39
ge_dist_pc_req_stall_se1 = 40
ge_dist_pc_req_stall_se2 = 41
ge_dist_pc_req_stall_se3 = 42
ge_dist_pc_req_stall_se4 = 43
ge_dist_pc_req_stall_se5 = 44
ge_dist_pc_req_stall_se6 = 45
ge_dist_pc_req_stall_se7 = 46
ge_dist_pc_space_zero = 47
ge_dist_sclk_input_vld = 48
ge_dist_reserved = 49
ge_dist_wd_te11_busy = 50
ge_dist_te11_starved = 51
ge_dist_switch_mode_stall = 52
ge_all_tf_eq = 53
ge_all_tf2 = 54
ge_all_tf3 = 55
ge_all_tf4 = 56
ge_all_tf5 = 57
ge_all_tf6 = 58
ge_se0_te11_starved_on_hs_done = 59
ge_se1_te11_starved_on_hs_done = 60
ge_se2_te11_starved_on_hs_done = 61
ge_se3_te11_starved_on_hs_done = 62
ge_se4_te11_starved_on_hs_done = 63
ge_se5_te11_starved_on_hs_done = 64
ge_se6_te11_starved_on_hs_done = 65
ge_se7_te11_starved_on_hs_done = 66
ge_dist_op_fifo_full_starve = 67
ge_dist_hs_done_se0 = 68
ge_dist_hs_done_se1 = 69
ge_dist_hs_done_se2 = 70
ge_dist_hs_done_se3 = 71
ge_dist_hs_done_se4 = 72
ge_dist_hs_done_se5 = 73
ge_dist_hs_done_se6 = 74
ge_dist_hs_done_se7 = 75
ge_dist_hs_done_latency = 76
ge_dist_distributer_busy = 77
ge_tf_ret_data_stalling_hs_done = 78
ge_num_of_no_dist_patches = 79
ge_num_of_donut_dist_patches = 80
ge_num_of_patch_dist_patches = 81
ge_num_of_se_switches_due_to_patch_accum = 82
ge_num_of_se_switches_due_to_donut = 83
ge_num_of_se_switches_due_to_trap = 84
ge_num_of_hs_alloc_events = 85
ge_agm_gcr_req = 86
ge_agm_gcr_tag_stall = 87
ge_agm_gcr_crd_stall = 88
ge_agm_gcr_stall = 89
ge_agm_gcr_latency = 90
ge_distclk_vld = 91
GE2_DIST_PERFCOUNT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'GE2_SE_PERFCOUNT_SELECT'
GE2_SE_PERFCOUNT_SELECT__enumvalues = {
0: 'ge_se_ds_prims',
1: 'ge_se_es_thread_groups',
2: 'ge_se_esvert_stalled_gsprim',
3: 'ge_se_hs_tfm_stall',
4: 'ge_se_hs_tgs_active_high_water_mark',
5: 'ge_se_hs_thread_groups',
6: 'ge_se_reused_es_indices',
7: 'ge_se_sclk_ngg_vld',
8: 'ge_se_sclk_te11_vld',
9: 'ge_se_spi_esvert_eov',
10: 'ge_se_spi_esvert_stalled',
11: 'ge_se_spi_esvert_starved_busy',
12: 'ge_se_spi_esvert_valid',
13: 'ge_se_spi_gsprim_cont',
14: 'ge_se_spi_gsprim_eov',
15: 'ge_se_spi_gsprim_stalled',
16: 'ge_se_spi_gsprim_starved_busy',
17: 'ge_se_spi_gsprim_valid',
18: 'ge_se_spi_gssubgrp_is_event',
19: 'ge_se_spi_gssubgrp_send',
20: 'ge_se_spi_hsvert_eov',
21: 'ge_se_spi_hsvert_stalled',
22: 'ge_se_spi_hsvert_starved_busy',
23: 'ge_se_spi_hsvert_valid',
24: 'ge_se_spi_hswave_is_event',
25: 'ge_se_spi_hswave_send',
26: 'ge_se_spi_lsvert_eov',
27: 'ge_se_spi_lsvert_stalled',
28: 'ge_se_spi_lsvert_starved_busy',
29: 'ge_se_spi_lsvert_valid',
30: 'ge_se_spi_hsvert_fifo_full_stall',
31: 'ge_se_spi_tgrp_fifo_stall',
32: 'ge_spi_hsgrp_spi_stall',
33: 'ge_se_spi_gssubgrp_event_window_active',
34: 'ge_se_hs_input_stall',
35: 'ge_se_sending_vert_or_prim',
36: 'ge_se_sclk_input_vld',
37: 'ge_spi_lswave_fifo_full_stall',
38: 'ge_spi_hswave_fifo_full_stall',
39: 'ge_hs_tif_stall',
40: 'ge_csb_spi_bp',
41: 'ge_ngg_starving_for_pc_grant',
42: 'ge_pa0_csb_eop',
43: 'ge_pa1_csb_eop',
44: 'ge_ngg_starved_idle',
45: 'ge_gsprim_send',
46: 'ge_esvert_send',
47: 'ge_ngg_starved_after_work',
48: 'ge_ngg_subgrp_fifo_stall',
49: 'ge_ngg_ord_id_req_stall',
50: 'ge_ngg_indx_bus_stall',
51: 'ge_hs_stall_tfmm_fifo_full',
52: 'ge_gs_issue_rtr_stalled',
53: 'ge_gsprim_stalled_esvert',
54: 'ge_gsthread_stalled',
55: 'ge_te11_stall_prim_funnel',
56: 'ge_te11_stall_vert_funnel',
57: 'ge_ngg_attr_grp_alloc',
58: 'ge_ngg_attr_discard_alloc',
59: 'ge_ngg_pc_space_not_avail',
60: 'ge_ngg_agm_req_stall',
61: 'ge_ngg_spi_esvert_partial_eov',
62: 'ge_ngg_spi_gsprim_partial_eov',
63: 'ge_spi_gsgrp_valid',
64: 'ge_ngg_attr_grp_latency',
65: 'ge_ngg_reuse_prim_limit_hit',
66: 'ge_ngg_reuse_vert_limit_hit',
67: 'ge_te11_con_stall',
68: 'ge_te11_compactor_starved',
69: 'ge_ngg_stall_tess_off_tess_on',
70: 'ge_ngg_stall_tess_on_tess_off',
}
ge_se_ds_prims = 0
ge_se_es_thread_groups = 1
ge_se_esvert_stalled_gsprim = 2
ge_se_hs_tfm_stall = 3
ge_se_hs_tgs_active_high_water_mark = 4
ge_se_hs_thread_groups = 5
ge_se_reused_es_indices = 6
ge_se_sclk_ngg_vld = 7
ge_se_sclk_te11_vld = 8
ge_se_spi_esvert_eov = 9
ge_se_spi_esvert_stalled = 10
ge_se_spi_esvert_starved_busy = 11
ge_se_spi_esvert_valid = 12
ge_se_spi_gsprim_cont = 13
ge_se_spi_gsprim_eov = 14
ge_se_spi_gsprim_stalled = 15
ge_se_spi_gsprim_starved_busy = 16
ge_se_spi_gsprim_valid = 17
ge_se_spi_gssubgrp_is_event = 18
ge_se_spi_gssubgrp_send = 19
ge_se_spi_hsvert_eov = 20
ge_se_spi_hsvert_stalled = 21
ge_se_spi_hsvert_starved_busy = 22
ge_se_spi_hsvert_valid = 23
ge_se_spi_hswave_is_event = 24
ge_se_spi_hswave_send = 25
ge_se_spi_lsvert_eov = 26
ge_se_spi_lsvert_stalled = 27
ge_se_spi_lsvert_starved_busy = 28
ge_se_spi_lsvert_valid = 29
ge_se_spi_hsvert_fifo_full_stall = 30
ge_se_spi_tgrp_fifo_stall = 31
ge_spi_hsgrp_spi_stall = 32
ge_se_spi_gssubgrp_event_window_active = 33
ge_se_hs_input_stall = 34
ge_se_sending_vert_or_prim = 35
ge_se_sclk_input_vld = 36
ge_spi_lswave_fifo_full_stall = 37
ge_spi_hswave_fifo_full_stall = 38
ge_hs_tif_stall = 39
ge_csb_spi_bp = 40
ge_ngg_starving_for_pc_grant = 41
ge_pa0_csb_eop = 42
ge_pa1_csb_eop = 43
ge_ngg_starved_idle = 44
ge_gsprim_send = 45
ge_esvert_send = 46
ge_ngg_starved_after_work = 47
ge_ngg_subgrp_fifo_stall = 48
ge_ngg_ord_id_req_stall = 49
ge_ngg_indx_bus_stall = 50
ge_hs_stall_tfmm_fifo_full = 51
ge_gs_issue_rtr_stalled = 52
ge_gsprim_stalled_esvert = 53
ge_gsthread_stalled = 54
ge_te11_stall_prim_funnel = 55
ge_te11_stall_vert_funnel = 56
ge_ngg_attr_grp_alloc = 57
ge_ngg_attr_discard_alloc = 58
ge_ngg_pc_space_not_avail = 59
ge_ngg_agm_req_stall = 60
ge_ngg_spi_esvert_partial_eov = 61
ge_ngg_spi_gsprim_partial_eov = 62
ge_spi_gsgrp_valid = 63
ge_ngg_attr_grp_latency = 64
ge_ngg_reuse_prim_limit_hit = 65
ge_ngg_reuse_vert_limit_hit = 66
ge_te11_con_stall = 67
ge_te11_compactor_starved = 68
ge_ngg_stall_tess_off_tess_on = 69
ge_ngg_stall_tess_on_tess_off = 70
GE2_SE_PERFCOUNT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DETECT_ONE'
VGT_DETECT_ONE__enumvalues = {
0: 'ENABLE_TF1_OPT',
1: 'DISABLE_TF1_OPT',
}
ENABLE_TF1_OPT = 0
DISABLE_TF1_OPT = 1
VGT_DETECT_ONE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DETECT_ZERO'
VGT_DETECT_ZERO__enumvalues = {
0: 'ENABLE_TF0_OPT',
1: 'DISABLE_TF0_OPT',
}
ENABLE_TF0_OPT = 0
DISABLE_TF0_OPT = 1
VGT_DETECT_ZERO = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DIST_MODE'
VGT_DIST_MODE__enumvalues = {
0: 'NO_DIST',
1: 'PATCHES',
2: 'DONUTS',
3: 'TRAPEZOIDS',
}
NO_DIST = 0
PATCHES = 1
DONUTS = 2
TRAPEZOIDS = 3
VGT_DIST_MODE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DI_INDEX_SIZE'
VGT_DI_INDEX_SIZE__enumvalues = {
0: 'DI_INDEX_SIZE_16_BIT',
1: 'DI_INDEX_SIZE_32_BIT',
2: 'DI_INDEX_SIZE_8_BIT',
}
DI_INDEX_SIZE_16_BIT = 0
DI_INDEX_SIZE_32_BIT = 1
DI_INDEX_SIZE_8_BIT = 2
VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DI_MAJOR_MODE_SELECT'
VGT_DI_MAJOR_MODE_SELECT__enumvalues = {
0: 'DI_MAJOR_MODE_0',
1: 'DI_MAJOR_MODE_1',
}
DI_MAJOR_MODE_0 = 0
DI_MAJOR_MODE_1 = 1
VGT_DI_MAJOR_MODE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DI_PRIM_TYPE'
VGT_DI_PRIM_TYPE__enumvalues = {
0: 'DI_PT_NONE',
1: 'DI_PT_POINTLIST',
2: 'DI_PT_LINELIST',
3: 'DI_PT_LINESTRIP',
4: 'DI_PT_TRILIST',
5: 'DI_PT_TRIFAN',
6: 'DI_PT_TRISTRIP',
7: 'DI_PT_2D_RECTANGLE',
8: 'DI_PT_UNUSED_1',
9: 'DI_PT_PATCH',
10: 'DI_PT_LINELIST_ADJ',
11: 'DI_PT_LINESTRIP_ADJ',
12: 'DI_PT_TRILIST_ADJ',
13: 'DI_PT_TRISTRIP_ADJ',
14: 'DI_PT_UNUSED_3',
15: 'DI_PT_UNUSED_4',
16: 'DI_PT_UNUSED_5',
17: 'DI_PT_RECTLIST',
18: 'DI_PT_LINELOOP',
19: 'DI_PT_QUADLIST',
20: 'DI_PT_QUADSTRIP',
21: 'DI_PT_POLYGON',
}
DI_PT_NONE = 0
DI_PT_POINTLIST = 1
DI_PT_LINELIST = 2
DI_PT_LINESTRIP = 3
DI_PT_TRILIST = 4
DI_PT_TRIFAN = 5
DI_PT_TRISTRIP = 6
DI_PT_2D_RECTANGLE = 7
DI_PT_UNUSED_1 = 8
DI_PT_PATCH = 9
DI_PT_LINELIST_ADJ = 10
DI_PT_LINESTRIP_ADJ = 11
DI_PT_TRILIST_ADJ = 12
DI_PT_TRISTRIP_ADJ = 13
DI_PT_UNUSED_3 = 14
DI_PT_UNUSED_4 = 15
DI_PT_UNUSED_5 = 16
DI_PT_RECTLIST = 17
DI_PT_LINELOOP = 18
DI_PT_QUADLIST = 19
DI_PT_QUADSTRIP = 20
DI_PT_POLYGON = 21
VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DI_SOURCE_SELECT'
VGT_DI_SOURCE_SELECT__enumvalues = {
0: 'DI_SRC_SEL_DMA',
1: 'DI_SRC_SEL_IMMEDIATE',
2: 'DI_SRC_SEL_AUTO_INDEX',
3: 'DI_SRC_SEL_RESERVED',
}
DI_SRC_SEL_DMA = 0
DI_SRC_SEL_IMMEDIATE = 1
DI_SRC_SEL_AUTO_INDEX = 2
DI_SRC_SEL_RESERVED = 3
VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DMA_BUF_TYPE'
VGT_DMA_BUF_TYPE__enumvalues = {
0: 'VGT_DMA_BUF_MEM',
1: 'VGT_DMA_BUF_RING',
2: 'VGT_DMA_BUF_SETUP',
3: 'VGT_DMA_PTR_UPDATE',
}
VGT_DMA_BUF_MEM = 0
VGT_DMA_BUF_RING = 1
VGT_DMA_BUF_SETUP = 2
VGT_DMA_PTR_UPDATE = 3
VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_DMA_SWAP_MODE'
VGT_DMA_SWAP_MODE__enumvalues = {
0: 'VGT_DMA_SWAP_NONE',
1: 'VGT_DMA_SWAP_16_BIT',
2: 'VGT_DMA_SWAP_32_BIT',
3: 'VGT_DMA_SWAP_WORD',
}
VGT_DMA_SWAP_NONE = 0
VGT_DMA_SWAP_16_BIT = 1
VGT_DMA_SWAP_32_BIT = 2
VGT_DMA_SWAP_WORD = 3
VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_EVENT_TYPE'
VGT_EVENT_TYPE__enumvalues = {
0: 'Reserved_0x00',
1: 'SAMPLE_STREAMOUTSTATS1',
2: 'SAMPLE_STREAMOUTSTATS2',
3: 'SAMPLE_STREAMOUTSTATS3',
4: 'CACHE_FLUSH_TS',
5: 'CONTEXT_DONE',
6: 'CACHE_FLUSH',
7: 'CS_PARTIAL_FLUSH',
8: 'VGT_STREAMOUT_SYNC',
9: 'Reserved_0x09',
10: 'VGT_STREAMOUT_RESET',
11: 'END_OF_PIPE_INCR_DE',
12: 'END_OF_PIPE_IB_END',
13: 'RST_PIX_CNT',
14: 'BREAK_BATCH',
15: 'VS_PARTIAL_FLUSH',
16: 'PS_PARTIAL_FLUSH',
17: 'FLUSH_HS_OUTPUT',
18: 'FLUSH_DFSM',
19: 'RESET_TO_LOWEST_VGT',
20: 'CACHE_FLUSH_AND_INV_TS_EVENT',
21: 'WAIT_SYNC',
22: 'CACHE_FLUSH_AND_INV_EVENT',
23: 'PERFCOUNTER_START',
24: 'PERFCOUNTER_STOP',
25: 'PIPELINESTAT_START',
26: 'PIPELINESTAT_STOP',
27: 'PERFCOUNTER_SAMPLE',
28: 'FLUSH_ES_OUTPUT',
29: 'BIN_CONF_OVERRIDE_CHECK',
30: 'SAMPLE_PIPELINESTAT',
31: 'SO_VGTSTREAMOUT_FLUSH',
32: 'SAMPLE_STREAMOUTSTATS',
33: 'RESET_VTX_CNT',
34: 'BLOCK_CONTEXT_DONE',
35: 'CS_CONTEXT_DONE',
36: 'VGT_FLUSH',
37: 'TGID_ROLLOVER',
38: 'SQ_NON_EVENT',
39: 'SC_SEND_DB_VPZ',
40: 'BOTTOM_OF_PIPE_TS',
41: 'FLUSH_SX_TS',
42: 'DB_CACHE_FLUSH_AND_INV',
43: 'FLUSH_AND_INV_DB_DATA_TS',
44: 'FLUSH_AND_INV_DB_META',
45: 'FLUSH_AND_INV_CB_DATA_TS',
46: 'FLUSH_AND_INV_CB_META',
47: 'CS_DONE',
48: 'PS_DONE',
49: 'FLUSH_AND_INV_CB_PIXEL_DATA',
50: 'SX_CB_RAT_ACK_REQUEST',
51: 'THREAD_TRACE_START',
52: 'THREAD_TRACE_STOP',
53: 'THREAD_TRACE_MARKER',
54: 'THREAD_TRACE_DRAW',
55: 'THREAD_TRACE_FINISH',
56: 'PIXEL_PIPE_STAT_CONTROL',
57: 'PIXEL_PIPE_STAT_DUMP',
58: 'PIXEL_PIPE_STAT_RESET',
59: 'CONTEXT_SUSPEND',
60: 'OFFCHIP_HS_DEALLOC',
61: 'ENABLE_NGG_PIPELINE',
62: 'ENABLE_LEGACY_PIPELINE',
63: 'DRAW_DONE',
}
Reserved_0x00 = 0
SAMPLE_STREAMOUTSTATS1 = 1
SAMPLE_STREAMOUTSTATS2 = 2
SAMPLE_STREAMOUTSTATS3 = 3
CACHE_FLUSH_TS = 4
CONTEXT_DONE = 5
CACHE_FLUSH = 6
CS_PARTIAL_FLUSH = 7
VGT_STREAMOUT_SYNC = 8
Reserved_0x09 = 9
VGT_STREAMOUT_RESET = 10
END_OF_PIPE_INCR_DE = 11
END_OF_PIPE_IB_END = 12
RST_PIX_CNT = 13
BREAK_BATCH = 14
VS_PARTIAL_FLUSH = 15
PS_PARTIAL_FLUSH = 16
FLUSH_HS_OUTPUT = 17
FLUSH_DFSM = 18
RESET_TO_LOWEST_VGT = 19
CACHE_FLUSH_AND_INV_TS_EVENT = 20
WAIT_SYNC = 21
CACHE_FLUSH_AND_INV_EVENT = 22
PERFCOUNTER_START = 23
PERFCOUNTER_STOP = 24
PIPELINESTAT_START = 25
PIPELINESTAT_STOP = 26
PERFCOUNTER_SAMPLE = 27
FLUSH_ES_OUTPUT = 28
BIN_CONF_OVERRIDE_CHECK = 29
SAMPLE_PIPELINESTAT = 30
SO_VGTSTREAMOUT_FLUSH = 31
SAMPLE_STREAMOUTSTATS = 32
RESET_VTX_CNT = 33
BLOCK_CONTEXT_DONE = 34
CS_CONTEXT_DONE = 35
VGT_FLUSH = 36
TGID_ROLLOVER = 37
SQ_NON_EVENT = 38
SC_SEND_DB_VPZ = 39
BOTTOM_OF_PIPE_TS = 40
FLUSH_SX_TS = 41
DB_CACHE_FLUSH_AND_INV = 42
FLUSH_AND_INV_DB_DATA_TS = 43
FLUSH_AND_INV_DB_META = 44
FLUSH_AND_INV_CB_DATA_TS = 45
FLUSH_AND_INV_CB_META = 46
CS_DONE = 47
PS_DONE = 48
FLUSH_AND_INV_CB_PIXEL_DATA = 49
SX_CB_RAT_ACK_REQUEST = 50
THREAD_TRACE_START = 51
THREAD_TRACE_STOP = 52
THREAD_TRACE_MARKER = 53
THREAD_TRACE_DRAW = 54
THREAD_TRACE_FINISH = 55
PIXEL_PIPE_STAT_CONTROL = 56
PIXEL_PIPE_STAT_DUMP = 57
PIXEL_PIPE_STAT_RESET = 58
CONTEXT_SUSPEND = 59
OFFCHIP_HS_DEALLOC = 60
ENABLE_NGG_PIPELINE = 61
ENABLE_LEGACY_PIPELINE = 62
DRAW_DONE = 63
VGT_EVENT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_GROUP_CONV_SEL'
VGT_GROUP_CONV_SEL__enumvalues = {
0: 'VGT_GRP_INDEX_16',
1: 'VGT_GRP_INDEX_32',
2: 'VGT_GRP_UINT_16',
3: 'VGT_GRP_UINT_32',
4: 'VGT_GRP_SINT_16',
5: 'VGT_GRP_SINT_32',
6: 'VGT_GRP_FLOAT_32',
7: 'VGT_GRP_AUTO_PRIM',
8: 'VGT_GRP_FIX_1_23_TO_FLOAT',
}
VGT_GRP_INDEX_16 = 0
VGT_GRP_INDEX_32 = 1
VGT_GRP_UINT_16 = 2
VGT_GRP_UINT_32 = 3
VGT_GRP_SINT_16 = 4
VGT_GRP_SINT_32 = 5
VGT_GRP_FLOAT_32 = 6
VGT_GRP_AUTO_PRIM = 7
VGT_GRP_FIX_1_23_TO_FLOAT = 8
VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum
# values for enumeration 'VGT_GS_MODE_TYPE'
VGT_GS_MODE_TYPE__enumvalues = {
0: 'GS_OFF',
1: 'GS_SCENARIO_A',
2: 'GS_SCENARIO_B',
3: 'GS_SCENARIO_G',
4: 'GS_SCENARIO_C',
5: 'SPRITE_EN',
}
GS_OFF = 0
GS_SCENARIO_A = 1
GS_SCENARIO_B = 2
GS_SCENARIO_G = 3
GS_SCENARIO_C = 4
SPRITE_EN = 5
VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_GS_OUTPRIM_TYPE'
VGT_GS_OUTPRIM_TYPE__enumvalues = {
0: 'POINTLIST',
1: 'LINESTRIP',
2: 'TRISTRIP',
3: 'RECT_2D',
4: 'RECTLIST',
}
POINTLIST = 0
LINESTRIP = 1
TRISTRIP = 2
RECT_2D = 3
RECTLIST = 4
VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_INDEX_TYPE_MODE'
VGT_INDEX_TYPE_MODE__enumvalues = {
0: 'VGT_INDEX_16',
1: 'VGT_INDEX_32',
2: 'VGT_INDEX_8',
}
VGT_INDEX_16 = 0
VGT_INDEX_32 = 1
VGT_INDEX_8 = 2
VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_OUTPATH_SELECT'
VGT_OUTPATH_SELECT__enumvalues = {
0: 'VGT_OUTPATH_VTX_REUSE',
1: 'VGT_OUTPATH_GS_BLOCK',
2: 'VGT_OUTPATH_HS_BLOCK',
3: 'VGT_OUTPATH_PRIM_GEN',
4: 'VGT_OUTPATH_TE_PRIM_GEN',
5: 'VGT_OUTPATH_TE_GS_BLOCK',
6: 'VGT_OUTPATH_TE_OUTPUT',
}
VGT_OUTPATH_VTX_REUSE = 0
VGT_OUTPATH_GS_BLOCK = 1
VGT_OUTPATH_HS_BLOCK = 2
VGT_OUTPATH_PRIM_GEN = 3
VGT_OUTPATH_TE_PRIM_GEN = 4
VGT_OUTPATH_TE_GS_BLOCK = 5
VGT_OUTPATH_TE_OUTPUT = 6
VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'VGT_OUT_PRIM_TYPE'
VGT_OUT_PRIM_TYPE__enumvalues = {
0: 'VGT_OUT_POINT',
1: 'VGT_OUT_LINE',
2: 'VGT_OUT_TRI',
3: 'VGT_OUT_RECT_V0',
4: 'VGT_OUT_RECT_V1',
5: 'VGT_OUT_RECT_V2',
6: 'VGT_OUT_RECT_V3',
7: 'VGT_OUT_2D_RECT',
8: 'VGT_TE_QUAD',
9: 'VGT_TE_PRIM_INDEX_LINE',
10: 'VGT_TE_PRIM_INDEX_TRI',
11: 'VGT_TE_PRIM_INDEX_QUAD',
12: 'VGT_OUT_LINE_ADJ',
13: 'VGT_OUT_TRI_ADJ',
14: 'VGT_OUT_PATCH',
}
VGT_OUT_POINT = 0
VGT_OUT_LINE = 1
VGT_OUT_TRI = 2
VGT_OUT_RECT_V0 = 3
VGT_OUT_RECT_V1 = 4
VGT_OUT_RECT_V2 = 5
VGT_OUT_RECT_V3 = 6
VGT_OUT_2D_RECT = 7
VGT_TE_QUAD = 8
VGT_TE_PRIM_INDEX_LINE = 9
VGT_TE_PRIM_INDEX_TRI = 10
VGT_TE_PRIM_INDEX_QUAD = 11
VGT_OUT_LINE_ADJ = 12
VGT_OUT_TRI_ADJ = 13
VGT_OUT_PATCH = 14
VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'VGT_RDREQ_POLICY'
VGT_RDREQ_POLICY__enumvalues = {
0: 'VGT_POLICY_LRU',
1: 'VGT_POLICY_STREAM',
2: 'VGT_POLICY_BYPASS',
}
VGT_POLICY_LRU = 0
VGT_POLICY_STREAM = 1
VGT_POLICY_BYPASS = 2
VGT_RDREQ_POLICY = ctypes.c_uint32 # enum
# values for enumeration 'VGT_STAGES_ES_EN'
VGT_STAGES_ES_EN__enumvalues = {
0: 'ES_STAGE_OFF',
1: 'ES_STAGE_DS',
2: 'ES_STAGE_REAL',
3: 'RESERVED_ES',
}
ES_STAGE_OFF = 0
ES_STAGE_DS = 1
ES_STAGE_REAL = 2
RESERVED_ES = 3
VGT_STAGES_ES_EN = ctypes.c_uint32 # enum
# values for enumeration 'VGT_STAGES_GS_EN'
VGT_STAGES_GS_EN__enumvalues = {
0: 'GS_STAGE_OFF',
1: 'GS_STAGE_ON',
}
GS_STAGE_OFF = 0
GS_STAGE_ON = 1
VGT_STAGES_GS_EN = ctypes.c_uint32 # enum
# values for enumeration 'VGT_STAGES_HS_EN'
VGT_STAGES_HS_EN__enumvalues = {
0: 'HS_STAGE_OFF',
1: 'HS_STAGE_ON',
}
HS_STAGE_OFF = 0
HS_STAGE_ON = 1
VGT_STAGES_HS_EN = ctypes.c_uint32 # enum
# values for enumeration 'VGT_STAGES_LS_EN'
VGT_STAGES_LS_EN__enumvalues = {
0: 'LS_STAGE_OFF',
1: 'LS_STAGE_ON',
2: 'CS_STAGE_ON',
3: 'RESERVED_LS',
}
LS_STAGE_OFF = 0
LS_STAGE_ON = 1
CS_STAGE_ON = 2
RESERVED_LS = 3
VGT_STAGES_LS_EN = ctypes.c_uint32 # enum
# values for enumeration 'VGT_STAGES_VS_EN'
VGT_STAGES_VS_EN__enumvalues = {
0: 'VS_STAGE_REAL',
1: 'VS_STAGE_DS',
2: 'VS_STAGE_COPY_SHADER',
3: 'RESERVED_VS',
}
VS_STAGE_REAL = 0
VS_STAGE_DS = 1
VS_STAGE_COPY_SHADER = 2
RESERVED_VS = 3
VGT_STAGES_VS_EN = ctypes.c_uint32 # enum
# values for enumeration 'VGT_TESS_PARTITION'
VGT_TESS_PARTITION__enumvalues = {
0: 'PART_INTEGER',
1: 'PART_POW2',
2: 'PART_FRAC_ODD',
3: 'PART_FRAC_EVEN',
}
PART_INTEGER = 0
PART_POW2 = 1
PART_FRAC_ODD = 2
PART_FRAC_EVEN = 3
VGT_TESS_PARTITION = ctypes.c_uint32 # enum
# values for enumeration 'VGT_TESS_TOPOLOGY'
VGT_TESS_TOPOLOGY__enumvalues = {
0: 'OUTPUT_POINT',
1: 'OUTPUT_LINE',
2: 'OUTPUT_TRIANGLE_CW',
3: 'OUTPUT_TRIANGLE_CCW',
}
OUTPUT_POINT = 0
OUTPUT_LINE = 1
OUTPUT_TRIANGLE_CW = 2
OUTPUT_TRIANGLE_CCW = 3
VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum
# values for enumeration 'VGT_TESS_TYPE'
VGT_TESS_TYPE__enumvalues = {
0: 'TESS_ISOLINE',
1: 'TESS_TRIANGLE',
2: 'TESS_QUAD',
}
TESS_ISOLINE = 0
TESS_TRIANGLE = 1
TESS_QUAD = 2
VGT_TESS_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'WD_IA_DRAW_REG_XFER'
WD_IA_DRAW_REG_XFER__enumvalues = {
0: 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM',
1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN',
2: 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID',
3: 'WD_IA_DRAW_REG_XFER_GE_CNTL',
4: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN',
5: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM',
6: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1',
7: 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE',
8: 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC',
}
WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0
WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1
WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 2
WD_IA_DRAW_REG_XFER_GE_CNTL = 3
WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 4
WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 5
WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 6
WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 7
WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 8
WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum
# values for enumeration 'WD_IA_DRAW_SOURCE'
WD_IA_DRAW_SOURCE__enumvalues = {
0: 'WD_IA_DRAW_SOURCE_DMA',
1: 'WD_IA_DRAW_SOURCE_IMMD',
2: 'WD_IA_DRAW_SOURCE_AUTO',
3: 'WD_IA_DRAW_SOURCE_OPAQ',
}
WD_IA_DRAW_SOURCE_DMA = 0
WD_IA_DRAW_SOURCE_IMMD = 1
WD_IA_DRAW_SOURCE_AUTO = 2
WD_IA_DRAW_SOURCE_OPAQ = 3
WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum
# values for enumeration 'WD_IA_DRAW_TYPE'
WD_IA_DRAW_TYPE__enumvalues = {
0: 'WD_IA_DRAW_TYPE_DI_MM0',
1: 'WD_IA_DRAW_TYPE_REG_XFER',
2: 'WD_IA_DRAW_TYPE_EVENT_INIT',
3: 'WD_IA_DRAW_TYPE_EVENT_ADDR',
4: 'WD_IA_DRAW_TYPE_MIN_INDX',
5: 'WD_IA_DRAW_TYPE_MAX_INDX',
6: 'WD_IA_DRAW_TYPE_INDX_OFF',
7: 'WD_IA_DRAW_TYPE_IMM_DATA',
}
WD_IA_DRAW_TYPE_DI_MM0 = 0
WD_IA_DRAW_TYPE_REG_XFER = 1
WD_IA_DRAW_TYPE_EVENT_INIT = 2
WD_IA_DRAW_TYPE_EVENT_ADDR = 3
WD_IA_DRAW_TYPE_MIN_INDX = 4
WD_IA_DRAW_TYPE_MAX_INDX = 5
WD_IA_DRAW_TYPE_INDX_OFF = 6
WD_IA_DRAW_TYPE_IMM_DATA = 7
WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'GB_EDC_DED_MODE'
GB_EDC_DED_MODE__enumvalues = {
0: 'GB_EDC_DED_MODE_LOG',
1: 'GB_EDC_DED_MODE_HALT',
2: 'GB_EDC_DED_MODE_INT_HALT',
}
GB_EDC_DED_MODE_LOG = 0
GB_EDC_DED_MODE_HALT = 1
GB_EDC_DED_MODE_INT_HALT = 2
GB_EDC_DED_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CHA_PERF_SEL'
CHA_PERF_SEL__enumvalues = {
0: 'CHA_PERF_SEL_BUSY',
1: 'CHA_PERF_SEL_STALL_CHC0',
2: 'CHA_PERF_SEL_STALL_CHC1',
3: 'CHA_PERF_SEL_STALL_CHC2',
4: 'CHA_PERF_SEL_STALL_CHC3',
5: 'CHA_PERF_SEL_STALL_CHC4',
6: 'CHA_PERF_SEL_STALL_CHC5',
7: 'CHA_PERF_SEL_REQUEST_CHC0',
8: 'CHA_PERF_SEL_REQUEST_CHC1',
9: 'CHA_PERF_SEL_REQUEST_CHC2',
10: 'CHA_PERF_SEL_REQUEST_CHC3',
11: 'CHA_PERF_SEL_REQUEST_CHC4',
12: 'CHA_PERF_SEL_MEM_32B_WDS_CHC0',
13: 'CHA_PERF_SEL_MEM_32B_WDS_CHC1',
14: 'CHA_PERF_SEL_MEM_32B_WDS_CHC2',
15: 'CHA_PERF_SEL_MEM_32B_WDS_CHC3',
16: 'CHA_PERF_SEL_MEM_32B_WDS_CHC4',
17: 'CHA_PERF_SEL_IO_32B_WDS_CHC0',
18: 'CHA_PERF_SEL_IO_32B_WDS_CHC1',
19: 'CHA_PERF_SEL_IO_32B_WDS_CHC2',
20: 'CHA_PERF_SEL_IO_32B_WDS_CHC3',
21: 'CHA_PERF_SEL_IO_32B_WDS_CHC4',
22: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0',
23: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1',
24: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2',
25: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3',
26: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4',
27: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0',
28: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1',
29: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2',
30: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3',
31: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4',
32: 'CHA_PERF_SEL_ARB_REQUESTS',
33: 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL',
34: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0',
35: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1',
36: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2',
37: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3',
38: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4',
39: 'CHA_PERF_SEL_CYCLE',
}
CHA_PERF_SEL_BUSY = 0
CHA_PERF_SEL_STALL_CHC0 = 1
CHA_PERF_SEL_STALL_CHC1 = 2
CHA_PERF_SEL_STALL_CHC2 = 3
CHA_PERF_SEL_STALL_CHC3 = 4
CHA_PERF_SEL_STALL_CHC4 = 5
CHA_PERF_SEL_STALL_CHC5 = 6
CHA_PERF_SEL_REQUEST_CHC0 = 7
CHA_PERF_SEL_REQUEST_CHC1 = 8
CHA_PERF_SEL_REQUEST_CHC2 = 9
CHA_PERF_SEL_REQUEST_CHC3 = 10
CHA_PERF_SEL_REQUEST_CHC4 = 11
CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 12
CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 13
CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 14
CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 15
CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 16
CHA_PERF_SEL_IO_32B_WDS_CHC0 = 17
CHA_PERF_SEL_IO_32B_WDS_CHC1 = 18
CHA_PERF_SEL_IO_32B_WDS_CHC2 = 19
CHA_PERF_SEL_IO_32B_WDS_CHC3 = 20
CHA_PERF_SEL_IO_32B_WDS_CHC4 = 21
CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 22
CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 23
CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 24
CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 25
CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 26
CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 27
CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 28
CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 29
CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 30
CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 31
CHA_PERF_SEL_ARB_REQUESTS = 32
CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 33
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 34
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 35
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 36
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 37
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 38
CHA_PERF_SEL_CYCLE = 39
CHA_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CHCG_PERF_SEL'
CHCG_PERF_SEL__enumvalues = {
0: 'CHCG_PERF_SEL_CYCLE',
1: 'CHCG_PERF_SEL_BUSY',
2: 'CHCG_PERF_SEL_STARVE',
3: 'CHCG_PERF_SEL_ARB_RET_LEVEL',
4: 'CHCG_PERF_SEL_GL2_REQ_READ_LATENCY',
5: 'CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY',
6: 'CHCG_PERF_SEL_REQ',
7: 'CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET',
8: 'CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET',
9: 'CHCG_PERF_SEL_REQ_NOP_ACK',
10: 'CHCG_PERF_SEL_REQ_NOP_RTN0',
11: 'CHCG_PERF_SEL_REQ_READ',
12: 'CHCG_PERF_SEL_REQ_READ_128B',
13: 'CHCG_PERF_SEL_REQ_READ_32B',
14: 'CHCG_PERF_SEL_REQ_READ_64B',
15: 'CHCG_PERF_SEL_REQ_WRITE',
16: 'CHCG_PERF_SEL_REQ_WRITE_32B',
17: 'CHCG_PERF_SEL_REQ_WRITE_64B',
18: 'CHCG_PERF_SEL_STALL_GUS_GL1',
19: 'CHCG_PERF_SEL_STALL_BUFFER_FULL',
20: 'CHCG_PERF_SEL_REQ_CLIENT0',
21: 'CHCG_PERF_SEL_REQ_CLIENT1',
22: 'CHCG_PERF_SEL_REQ_CLIENT2',
23: 'CHCG_PERF_SEL_REQ_CLIENT3',
24: 'CHCG_PERF_SEL_REQ_CLIENT4',
25: 'CHCG_PERF_SEL_REQ_CLIENT5',
26: 'CHCG_PERF_SEL_REQ_CLIENT6',
27: 'CHCG_PERF_SEL_REQ_CLIENT7',
28: 'CHCG_PERF_SEL_REQ_CLIENT8',
29: 'CHCG_PERF_SEL_REQ_CLIENT9',
30: 'CHCG_PERF_SEL_REQ_CLIENT10',
31: 'CHCG_PERF_SEL_REQ_CLIENT11',
32: 'CHCG_PERF_SEL_REQ_CLIENT12',
33: 'CHCG_PERF_SEL_REQ_CLIENT13',
34: 'CHCG_PERF_SEL_REQ_CLIENT14',
35: 'CHCG_PERF_SEL_REQ_CLIENT15',
36: 'CHCG_PERF_SEL_REQ_CLIENT16',
37: 'CHCG_PERF_SEL_REQ_CLIENT17',
38: 'CHCG_PERF_SEL_REQ_CLIENT18',
39: 'CHCG_PERF_SEL_REQ_CLIENT19',
40: 'CHCG_PERF_SEL_REQ_CLIENT20',
41: 'CHCG_PERF_SEL_REQ_CLIENT21',
42: 'CHCG_PERF_SEL_REQ_CLIENT22',
43: 'CHCG_PERF_SEL_REQ_CLIENT23',
}
CHCG_PERF_SEL_CYCLE = 0
CHCG_PERF_SEL_BUSY = 1
CHCG_PERF_SEL_STARVE = 2
CHCG_PERF_SEL_ARB_RET_LEVEL = 3
CHCG_PERF_SEL_GL2_REQ_READ_LATENCY = 4
CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5
CHCG_PERF_SEL_REQ = 6
CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET = 7
CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8
CHCG_PERF_SEL_REQ_NOP_ACK = 9
CHCG_PERF_SEL_REQ_NOP_RTN0 = 10
CHCG_PERF_SEL_REQ_READ = 11
CHCG_PERF_SEL_REQ_READ_128B = 12
CHCG_PERF_SEL_REQ_READ_32B = 13
CHCG_PERF_SEL_REQ_READ_64B = 14
CHCG_PERF_SEL_REQ_WRITE = 15
CHCG_PERF_SEL_REQ_WRITE_32B = 16
CHCG_PERF_SEL_REQ_WRITE_64B = 17
CHCG_PERF_SEL_STALL_GUS_GL1 = 18
CHCG_PERF_SEL_STALL_BUFFER_FULL = 19
CHCG_PERF_SEL_REQ_CLIENT0 = 20
CHCG_PERF_SEL_REQ_CLIENT1 = 21
CHCG_PERF_SEL_REQ_CLIENT2 = 22
CHCG_PERF_SEL_REQ_CLIENT3 = 23
CHCG_PERF_SEL_REQ_CLIENT4 = 24
CHCG_PERF_SEL_REQ_CLIENT5 = 25
CHCG_PERF_SEL_REQ_CLIENT6 = 26
CHCG_PERF_SEL_REQ_CLIENT7 = 27
CHCG_PERF_SEL_REQ_CLIENT8 = 28
CHCG_PERF_SEL_REQ_CLIENT9 = 29
CHCG_PERF_SEL_REQ_CLIENT10 = 30
CHCG_PERF_SEL_REQ_CLIENT11 = 31
CHCG_PERF_SEL_REQ_CLIENT12 = 32
CHCG_PERF_SEL_REQ_CLIENT13 = 33
CHCG_PERF_SEL_REQ_CLIENT14 = 34
CHCG_PERF_SEL_REQ_CLIENT15 = 35
CHCG_PERF_SEL_REQ_CLIENT16 = 36
CHCG_PERF_SEL_REQ_CLIENT17 = 37
CHCG_PERF_SEL_REQ_CLIENT18 = 38
CHCG_PERF_SEL_REQ_CLIENT19 = 39
CHCG_PERF_SEL_REQ_CLIENT20 = 40
CHCG_PERF_SEL_REQ_CLIENT21 = 41
CHCG_PERF_SEL_REQ_CLIENT22 = 42
CHCG_PERF_SEL_REQ_CLIENT23 = 43
CHCG_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CHC_PERF_SEL'
CHC_PERF_SEL__enumvalues = {
0: 'CHC_PERF_SEL_CYCLE',
1: 'CHC_PERF_SEL_BUSY',
2: 'CHC_PERF_SEL_STARVE',
3: 'CHC_PERF_SEL_ARB_RET_LEVEL',
4: 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY',
5: 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY',
6: 'CHC_PERF_SEL_REQ',
7: 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET',
8: 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET',
9: 'CHC_PERF_SEL_REQ_NOP_ACK',
10: 'CHC_PERF_SEL_REQ_NOP_RTN0',
11: 'CHC_PERF_SEL_REQ_READ',
12: 'CHC_PERF_SEL_REQ_READ_128B',
13: 'CHC_PERF_SEL_REQ_READ_32B',
14: 'CHC_PERF_SEL_REQ_READ_64B',
15: 'CHC_PERF_SEL_REQ_WRITE',
16: 'CHC_PERF_SEL_REQ_WRITE_32B',
17: 'CHC_PERF_SEL_REQ_WRITE_64B',
18: 'CHC_PERF_SEL_STALL_GL2_GL1',
19: 'CHC_PERF_SEL_STALL_BUFFER_FULL',
20: 'CHC_PERF_SEL_REQ_CLIENT0',
21: 'CHC_PERF_SEL_REQ_CLIENT1',
22: 'CHC_PERF_SEL_REQ_CLIENT2',
23: 'CHC_PERF_SEL_REQ_CLIENT3',
24: 'CHC_PERF_SEL_REQ_CLIENT4',
25: 'CHC_PERF_SEL_REQ_CLIENT5',
26: 'CHC_PERF_SEL_REQ_CLIENT6',
27: 'CHC_PERF_SEL_REQ_CLIENT7',
28: 'CHC_PERF_SEL_REQ_CLIENT8',
29: 'CHC_PERF_SEL_REQ_CLIENT9',
30: 'CHC_PERF_SEL_REQ_CLIENT10',
31: 'CHC_PERF_SEL_REQ_CLIENT11',
32: 'CHC_PERF_SEL_REQ_CLIENT12',
33: 'CHC_PERF_SEL_REQ_CLIENT13',
34: 'CHC_PERF_SEL_REQ_CLIENT14',
35: 'CHC_PERF_SEL_REQ_CLIENT15',
36: 'CHC_PERF_SEL_REQ_CLIENT16',
37: 'CHC_PERF_SEL_REQ_CLIENT17',
38: 'CHC_PERF_SEL_REQ_CLIENT18',
39: 'CHC_PERF_SEL_REQ_CLIENT19',
40: 'CHC_PERF_SEL_REQ_CLIENT20',
41: 'CHC_PERF_SEL_REQ_CLIENT21',
42: 'CHC_PERF_SEL_REQ_CLIENT22',
43: 'CHC_PERF_SEL_REQ_CLIENT23',
}
CHC_PERF_SEL_CYCLE = 0
CHC_PERF_SEL_BUSY = 1
CHC_PERF_SEL_STARVE = 2
CHC_PERF_SEL_ARB_RET_LEVEL = 3
CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 4
CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5
CHC_PERF_SEL_REQ = 6
CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 7
CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8
CHC_PERF_SEL_REQ_NOP_ACK = 9
CHC_PERF_SEL_REQ_NOP_RTN0 = 10
CHC_PERF_SEL_REQ_READ = 11
CHC_PERF_SEL_REQ_READ_128B = 12
CHC_PERF_SEL_REQ_READ_32B = 13
CHC_PERF_SEL_REQ_READ_64B = 14
CHC_PERF_SEL_REQ_WRITE = 15
CHC_PERF_SEL_REQ_WRITE_32B = 16
CHC_PERF_SEL_REQ_WRITE_64B = 17
CHC_PERF_SEL_STALL_GL2_GL1 = 18
CHC_PERF_SEL_STALL_BUFFER_FULL = 19
CHC_PERF_SEL_REQ_CLIENT0 = 20
CHC_PERF_SEL_REQ_CLIENT1 = 21
CHC_PERF_SEL_REQ_CLIENT2 = 22
CHC_PERF_SEL_REQ_CLIENT3 = 23
CHC_PERF_SEL_REQ_CLIENT4 = 24
CHC_PERF_SEL_REQ_CLIENT5 = 25
CHC_PERF_SEL_REQ_CLIENT6 = 26
CHC_PERF_SEL_REQ_CLIENT7 = 27
CHC_PERF_SEL_REQ_CLIENT8 = 28
CHC_PERF_SEL_REQ_CLIENT9 = 29
CHC_PERF_SEL_REQ_CLIENT10 = 30
CHC_PERF_SEL_REQ_CLIENT11 = 31
CHC_PERF_SEL_REQ_CLIENT12 = 32
CHC_PERF_SEL_REQ_CLIENT13 = 33
CHC_PERF_SEL_REQ_CLIENT14 = 34
CHC_PERF_SEL_REQ_CLIENT15 = 35
CHC_PERF_SEL_REQ_CLIENT16 = 36
CHC_PERF_SEL_REQ_CLIENT17 = 37
CHC_PERF_SEL_REQ_CLIENT18 = 38
CHC_PERF_SEL_REQ_CLIENT19 = 39
CHC_PERF_SEL_REQ_CLIENT20 = 40
CHC_PERF_SEL_REQ_CLIENT21 = 41
CHC_PERF_SEL_REQ_CLIENT22 = 42
CHC_PERF_SEL_REQ_CLIENT23 = 43
CHC_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL1A_PERF_SEL'
GL1A_PERF_SEL__enumvalues = {
0: 'GL1A_PERF_SEL_BUSY',
1: 'GL1A_PERF_SEL_STALL_GL1C0',
2: 'GL1A_PERF_SEL_STALL_GL1C1',
3: 'GL1A_PERF_SEL_STALL_GL1C2',
4: 'GL1A_PERF_SEL_STALL_GL1C3',
5: 'GL1A_PERF_SEL_REQUEST_GL1C0',
6: 'GL1A_PERF_SEL_REQUEST_GL1C1',
7: 'GL1A_PERF_SEL_REQUEST_GL1C2',
8: 'GL1A_PERF_SEL_REQUEST_GL1C3',
9: 'GL1A_PERF_SEL_WDS_32B_GL1C0',
10: 'GL1A_PERF_SEL_WDS_32B_GL1C1',
11: 'GL1A_PERF_SEL_WDS_32B_GL1C2',
12: 'GL1A_PERF_SEL_WDS_32B_GL1C3',
13: 'GL1A_PERF_SEL_BURST_COUNT_GL1C0',
14: 'GL1A_PERF_SEL_BURST_COUNT_GL1C1',
15: 'GL1A_PERF_SEL_BURST_COUNT_GL1C2',
16: 'GL1A_PERF_SEL_BURST_COUNT_GL1C3',
17: 'GL1A_PERF_SEL_ARB_REQUESTS',
18: 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL',
19: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0',
20: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1',
21: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2',
22: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3',
23: 'GL1A_PERF_SEL_CYCLE',
}
GL1A_PERF_SEL_BUSY = 0
GL1A_PERF_SEL_STALL_GL1C0 = 1
GL1A_PERF_SEL_STALL_GL1C1 = 2
GL1A_PERF_SEL_STALL_GL1C2 = 3
GL1A_PERF_SEL_STALL_GL1C3 = 4
GL1A_PERF_SEL_REQUEST_GL1C0 = 5
GL1A_PERF_SEL_REQUEST_GL1C1 = 6
GL1A_PERF_SEL_REQUEST_GL1C2 = 7
GL1A_PERF_SEL_REQUEST_GL1C3 = 8
GL1A_PERF_SEL_WDS_32B_GL1C0 = 9
GL1A_PERF_SEL_WDS_32B_GL1C1 = 10
GL1A_PERF_SEL_WDS_32B_GL1C2 = 11
GL1A_PERF_SEL_WDS_32B_GL1C3 = 12
GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 13
GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 14
GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 15
GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 16
GL1A_PERF_SEL_ARB_REQUESTS = 17
GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 18
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 19
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 20
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 21
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 22
GL1A_PERF_SEL_CYCLE = 23
GL1A_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL1C_PERF_SEL'
GL1C_PERF_SEL__enumvalues = {
0: 'GL1C_PERF_SEL_CYCLE',
1: 'GL1C_PERF_SEL_BUSY',
2: 'GL1C_PERF_SEL_STARVE',
3: 'GL1C_PERF_SEL_ARB_RET_LEVEL',
4: 'GL1C_PERF_SEL_GL2_REQ_READ',
5: 'GL1C_PERF_SEL_GL2_REQ_READ_128B',
6: 'GL1C_PERF_SEL_GL2_REQ_READ_32B',
7: 'GL1C_PERF_SEL_GL2_REQ_READ_64B',
8: 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY',
9: 'GL1C_PERF_SEL_GL2_REQ_WRITE',
10: 'GL1C_PERF_SEL_GL2_REQ_WRITE_32B',
11: 'GL1C_PERF_SEL_GL2_REQ_WRITE_64B',
12: 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY',
13: 'GL1C_PERF_SEL_GL2_REQ_PREFETCH',
14: 'GL1C_PERF_SEL_REQ',
15: 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET',
16: 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET',
17: 'GL1C_PERF_SEL_REQ_SHADER_INV',
18: 'GL1C_PERF_SEL_REQ_MISS',
19: 'GL1C_PERF_SEL_REQ_NOP_ACK',
20: 'GL1C_PERF_SEL_REQ_NOP_RTN0',
21: 'GL1C_PERF_SEL_REQ_READ',
22: 'GL1C_PERF_SEL_REQ_READ_128B',
23: 'GL1C_PERF_SEL_REQ_READ_32B',
24: 'GL1C_PERF_SEL_REQ_READ_64B',
25: 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT',
26: 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU',
27: 'GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT',
28: 'GL1C_PERF_SEL_REQ_WRITE',
29: 'GL1C_PERF_SEL_REQ_WRITE_32B',
30: 'GL1C_PERF_SEL_REQ_WRITE_64B',
31: 'GL1C_PERF_SEL_STALL_GL2_GL1',
32: 'GL1C_PERF_SEL_STALL_LFIFO_FULL',
33: 'GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC',
34: 'GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE',
35: 'GL1C_PERF_SEL_STALL_GCR_INV',
36: 'GL1C_PERF_SEL_STALL_VM',
37: 'GL1C_PERF_SEL_REQ_CLIENT0',
38: 'GL1C_PERF_SEL_REQ_CLIENT1',
39: 'GL1C_PERF_SEL_REQ_CLIENT2',
40: 'GL1C_PERF_SEL_REQ_CLIENT3',
41: 'GL1C_PERF_SEL_REQ_CLIENT4',
42: 'GL1C_PERF_SEL_REQ_CLIENT5',
43: 'GL1C_PERF_SEL_REQ_CLIENT6',
44: 'GL1C_PERF_SEL_REQ_CLIENT7',
45: 'GL1C_PERF_SEL_REQ_CLIENT8',
46: 'GL1C_PERF_SEL_REQ_CLIENT9',
47: 'GL1C_PERF_SEL_REQ_CLIENT10',
48: 'GL1C_PERF_SEL_REQ_CLIENT11',
49: 'GL1C_PERF_SEL_REQ_CLIENT12',
50: 'GL1C_PERF_SEL_REQ_CLIENT13',
51: 'GL1C_PERF_SEL_REQ_CLIENT14',
52: 'GL1C_PERF_SEL_REQ_CLIENT15',
53: 'GL1C_PERF_SEL_REQ_CLIENT16',
54: 'GL1C_PERF_SEL_REQ_CLIENT17',
55: 'GL1C_PERF_SEL_REQ_CLIENT18',
56: 'GL1C_PERF_SEL_REQ_CLIENT19',
57: 'GL1C_PERF_SEL_REQ_CLIENT20',
58: 'GL1C_PERF_SEL_REQ_CLIENT21',
59: 'GL1C_PERF_SEL_REQ_CLIENT22',
60: 'GL1C_PERF_SEL_REQ_CLIENT23',
61: 'GL1C_PERF_SEL_REQ_CLIENT24',
62: 'GL1C_PERF_SEL_REQ_CLIENT25',
63: 'GL1C_PERF_SEL_REQ_CLIENT26',
64: 'GL1C_PERF_SEL_REQ_CLIENT27',
65: 'GL1C_PERF_SEL_UTCL0_REQUEST',
66: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT',
67: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS',
68: 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS',
69: 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS',
70: 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL',
71: 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX',
72: 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES',
73: 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT',
74: 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL',
75: 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS',
76: 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS',
77: 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT',
78: 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT',
79: 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT',
80: 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ',
81: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT',
82: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT',
83: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT',
}
GL1C_PERF_SEL_CYCLE = 0
GL1C_PERF_SEL_BUSY = 1
GL1C_PERF_SEL_STARVE = 2
GL1C_PERF_SEL_ARB_RET_LEVEL = 3
GL1C_PERF_SEL_GL2_REQ_READ = 4
GL1C_PERF_SEL_GL2_REQ_READ_128B = 5
GL1C_PERF_SEL_GL2_REQ_READ_32B = 6
GL1C_PERF_SEL_GL2_REQ_READ_64B = 7
GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 8
GL1C_PERF_SEL_GL2_REQ_WRITE = 9
GL1C_PERF_SEL_GL2_REQ_WRITE_32B = 10
GL1C_PERF_SEL_GL2_REQ_WRITE_64B = 11
GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 12
GL1C_PERF_SEL_GL2_REQ_PREFETCH = 13
GL1C_PERF_SEL_REQ = 14
GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 15
GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 16
GL1C_PERF_SEL_REQ_SHADER_INV = 17
GL1C_PERF_SEL_REQ_MISS = 18
GL1C_PERF_SEL_REQ_NOP_ACK = 19
GL1C_PERF_SEL_REQ_NOP_RTN0 = 20
GL1C_PERF_SEL_REQ_READ = 21
GL1C_PERF_SEL_REQ_READ_128B = 22
GL1C_PERF_SEL_REQ_READ_32B = 23
GL1C_PERF_SEL_REQ_READ_64B = 24
GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT = 25
GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU = 26
GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT = 27
GL1C_PERF_SEL_REQ_WRITE = 28
GL1C_PERF_SEL_REQ_WRITE_32B = 29
GL1C_PERF_SEL_REQ_WRITE_64B = 30
GL1C_PERF_SEL_STALL_GL2_GL1 = 31
GL1C_PERF_SEL_STALL_LFIFO_FULL = 32
GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC = 33
GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE = 34
GL1C_PERF_SEL_STALL_GCR_INV = 35
GL1C_PERF_SEL_STALL_VM = 36
GL1C_PERF_SEL_REQ_CLIENT0 = 37
GL1C_PERF_SEL_REQ_CLIENT1 = 38
GL1C_PERF_SEL_REQ_CLIENT2 = 39
GL1C_PERF_SEL_REQ_CLIENT3 = 40
GL1C_PERF_SEL_REQ_CLIENT4 = 41
GL1C_PERF_SEL_REQ_CLIENT5 = 42
GL1C_PERF_SEL_REQ_CLIENT6 = 43
GL1C_PERF_SEL_REQ_CLIENT7 = 44
GL1C_PERF_SEL_REQ_CLIENT8 = 45
GL1C_PERF_SEL_REQ_CLIENT9 = 46
GL1C_PERF_SEL_REQ_CLIENT10 = 47
GL1C_PERF_SEL_REQ_CLIENT11 = 48
GL1C_PERF_SEL_REQ_CLIENT12 = 49
GL1C_PERF_SEL_REQ_CLIENT13 = 50
GL1C_PERF_SEL_REQ_CLIENT14 = 51
GL1C_PERF_SEL_REQ_CLIENT15 = 52
GL1C_PERF_SEL_REQ_CLIENT16 = 53
GL1C_PERF_SEL_REQ_CLIENT17 = 54
GL1C_PERF_SEL_REQ_CLIENT18 = 55
GL1C_PERF_SEL_REQ_CLIENT19 = 56
GL1C_PERF_SEL_REQ_CLIENT20 = 57
GL1C_PERF_SEL_REQ_CLIENT21 = 58
GL1C_PERF_SEL_REQ_CLIENT22 = 59
GL1C_PERF_SEL_REQ_CLIENT23 = 60
GL1C_PERF_SEL_REQ_CLIENT24 = 61
GL1C_PERF_SEL_REQ_CLIENT25 = 62
GL1C_PERF_SEL_REQ_CLIENT26 = 63
GL1C_PERF_SEL_REQ_CLIENT27 = 64
GL1C_PERF_SEL_UTCL0_REQUEST = 65
GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 66
GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 67
GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 68
GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 69
GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 70
GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 71
GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 72
GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 73
GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 74
GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 75
GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 76
GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 77
GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 78
GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 79
GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 80
GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 81
GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 82
GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 83
GL1C_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL1H_REQ_PERF_SEL'
GL1H_REQ_PERF_SEL__enumvalues = {
0: 'GL1H_REQ_PERF_SEL_BUSY',
1: 'GL1H_REQ_PERF_SEL_STALL_GL1_0',
2: 'GL1H_REQ_PERF_SEL_STALL_GL1_1',
3: 'GL1H_REQ_PERF_SEL_REQUEST_GL1_0',
4: 'GL1H_REQ_PERF_SEL_REQUEST_GL1_1',
5: 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_0',
6: 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_1',
7: 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0',
8: 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1',
9: 'GL1H_REQ_PERF_SEL_ARB_REQUESTS',
10: 'GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL',
11: 'GL1H_REQ_PERF_SEL_CYCLE',
}
GL1H_REQ_PERF_SEL_BUSY = 0
GL1H_REQ_PERF_SEL_STALL_GL1_0 = 1
GL1H_REQ_PERF_SEL_STALL_GL1_1 = 2
GL1H_REQ_PERF_SEL_REQUEST_GL1_0 = 3
GL1H_REQ_PERF_SEL_REQUEST_GL1_1 = 4
GL1H_REQ_PERF_SEL_WDS_32B_GL1_0 = 5
GL1H_REQ_PERF_SEL_WDS_32B_GL1_1 = 6
GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0 = 7
GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1 = 8
GL1H_REQ_PERF_SEL_ARB_REQUESTS = 9
GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL = 10
GL1H_REQ_PERF_SEL_CYCLE = 11
GL1H_REQ_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TA_PERFCOUNT_SEL'
TA_PERFCOUNT_SEL__enumvalues = {
0: 'TA_PERF_SEL_NULL',
1: 'TA_PERF_SEL_image_sampler_has_offset_instructions',
2: 'TA_PERF_SEL_image_sampler_has_bias_instructions',
3: 'TA_PERF_SEL_image_sampler_has_reference_instructions',
4: 'TA_PERF_SEL_image_sampler_has_ds_instructions',
5: 'TA_PERF_SEL_image_sampler_has_dt_instructions',
6: 'TA_PERF_SEL_image_sampler_has_dr_instructions',
7: 'TA_PERF_SEL_gradient_busy',
8: 'TA_PERF_SEL_gradient_fifo_busy',
9: 'TA_PERF_SEL_lod_busy',
10: 'TA_PERF_SEL_lod_fifo_busy',
11: 'TA_PERF_SEL_addresser_busy',
12: 'TA_PERF_SEL_addresser_fifo_busy',
13: 'TA_PERF_SEL_aligner_busy',
14: 'TA_PERF_SEL_write_path_busy',
15: 'TA_PERF_SEL_ta_busy',
16: 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions',
17: 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions',
18: 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions',
19: 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions',
20: 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions',
21: 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions',
22: 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions',
23: 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions',
24: 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions',
25: 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions',
26: 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions',
27: 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions',
28: 'TA_PERF_SEL_image_sampler_has_t_instructions',
29: 'TA_PERF_SEL_image_sampler_has_r_instructions',
30: 'TA_PERF_SEL_image_sampler_has_q_instructions',
32: 'TA_PERF_SEL_total_wavefronts',
33: 'TA_PERF_SEL_gradient_cycles',
34: 'TA_PERF_SEL_walker_cycles',
35: 'TA_PERF_SEL_aligner_cycles',
36: 'TA_PERF_SEL_image_wavefronts',
37: 'TA_PERF_SEL_image_read_wavefronts',
38: 'TA_PERF_SEL_image_store_wavefronts',
39: 'TA_PERF_SEL_image_atomic_wavefronts',
40: 'TA_PERF_SEL_image_sampler_total_cycles',
41: 'TA_PERF_SEL_image_nosampler_total_cycles',
42: 'TA_PERF_SEL_flat_total_cycles',
43: 'TA_PERF_SEL_bvh_total_cycles',
44: 'TA_PERF_SEL_buffer_wavefronts',
45: 'TA_PERF_SEL_buffer_load_wavefronts',
46: 'TA_PERF_SEL_buffer_store_wavefronts',
47: 'TA_PERF_SEL_buffer_atomic_wavefronts',
49: 'TA_PERF_SEL_buffer_total_cycles',
50: 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions',
51: 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions',
52: 'TA_PERF_SEL_buffer_has_index_instructions',
53: 'TA_PERF_SEL_buffer_has_offset_instructions',
54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles',
55: 'TA_PERF_SEL_addr_stalled_by_td_cycles',
56: 'TA_PERF_SEL_image_sampler_wavefronts',
57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles',
58: 'TA_PERF_SEL_addresser_stalled_cycles',
59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles',
60: 'TA_PERF_SEL_aniso_stalled_cycles',
61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles',
62: 'TA_PERF_SEL_deriv_stalled_cycles',
63: 'TA_PERF_SEL_aniso_gt1_cycle_quads',
64: 'TA_PERF_SEL_color_1_cycle_quads',
65: 'TA_PERF_SEL_color_2_cycle_quads',
66: 'TA_PERF_SEL_color_3_cycle_quads',
68: 'TA_PERF_SEL_mip_1_cycle_quads',
69: 'TA_PERF_SEL_mip_2_cycle_quads',
70: 'TA_PERF_SEL_vol_1_cycle_quads',
71: 'TA_PERF_SEL_vol_2_cycle_quads',
72: 'TA_PERF_SEL_sampler_op_quads',
73: 'TA_PERF_SEL_mipmap_lod_0_samples',
74: 'TA_PERF_SEL_mipmap_lod_1_samples',
75: 'TA_PERF_SEL_mipmap_lod_2_samples',
76: 'TA_PERF_SEL_mipmap_lod_3_samples',
77: 'TA_PERF_SEL_mipmap_lod_4_samples',
78: 'TA_PERF_SEL_mipmap_lod_5_samples',
79: 'TA_PERF_SEL_mipmap_lod_6_samples',
80: 'TA_PERF_SEL_mipmap_lod_7_samples',
81: 'TA_PERF_SEL_mipmap_lod_8_samples',
82: 'TA_PERF_SEL_mipmap_lod_9_samples',
83: 'TA_PERF_SEL_mipmap_lod_10_samples',
84: 'TA_PERF_SEL_mipmap_lod_11_samples',
85: 'TA_PERF_SEL_mipmap_lod_12_samples',
86: 'TA_PERF_SEL_mipmap_lod_13_samples',
87: 'TA_PERF_SEL_mipmap_lod_14_samples',
88: 'TA_PERF_SEL_mipmap_invalid_samples',
89: 'TA_PERF_SEL_aniso_1_cycle_quads',
90: 'TA_PERF_SEL_aniso_2_cycle_quads',
91: 'TA_PERF_SEL_aniso_4_cycle_quads',
92: 'TA_PERF_SEL_aniso_6_cycle_quads',
93: 'TA_PERF_SEL_aniso_8_cycle_quads',
94: 'TA_PERF_SEL_aniso_10_cycle_quads',
95: 'TA_PERF_SEL_aniso_12_cycle_quads',
96: 'TA_PERF_SEL_aniso_14_cycle_quads',
97: 'TA_PERF_SEL_aniso_16_cycle_quads',
98: 'TA_PERF_SEL_store_write_data_input_cycles',
99: 'TA_PERF_SEL_store_write_data_output_cycles',
100: 'TA_PERF_SEL_flat_wavefronts',
101: 'TA_PERF_SEL_flat_load_wavefronts',
102: 'TA_PERF_SEL_flat_store_wavefronts',
103: 'TA_PERF_SEL_flat_atomic_wavefronts',
104: 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions',
105: 'TA_PERF_SEL_register_clk_valid_cycles',
106: 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles',
107: 'TA_PERF_SEL_harvestable_clk_enabled_cycles',
108: 'TA_PERF_SEL_harvestable_register_clk_enabled_cycles',
109: 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles',
110: 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles',
114: 'TA_PERF_SEL_store_2_write_data_vgpr_instructions',
115: 'TA_PERF_SEL_store_3_write_data_vgpr_instructions',
116: 'TA_PERF_SEL_store_4_write_data_vgpr_instructions',
117: 'TA_PERF_SEL_store_has_x_instructions',
118: 'TA_PERF_SEL_store_has_y_instructions',
119: 'TA_PERF_SEL_store_has_z_instructions',
120: 'TA_PERF_SEL_store_has_w_instructions',
121: 'TA_PERF_SEL_image_nosampler_has_t_instructions',
122: 'TA_PERF_SEL_image_nosampler_has_r_instructions',
123: 'TA_PERF_SEL_image_nosampler_has_q_instructions',
124: 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions',
125: 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions',
126: 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions',
127: 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions',
128: 'TA_PERF_SEL_in_busy',
129: 'TA_PERF_SEL_in_fifos_busy',
130: 'TA_PERF_SEL_in_cfifo_busy',
131: 'TA_PERF_SEL_in_qfifo_busy',
132: 'TA_PERF_SEL_in_wfifo_busy',
133: 'TA_PERF_SEL_in_rfifo_busy',
134: 'TA_PERF_SEL_bf_busy',
135: 'TA_PERF_SEL_ns_busy',
136: 'TA_PERF_SEL_smp_busy_ns_idle',
137: 'TA_PERF_SEL_smp_idle_ns_busy',
144: 'TA_PERF_SEL_vmemcmd_cycles',
145: 'TA_PERF_SEL_vmemreq_cycles',
146: 'TA_PERF_SEL_in_waiting_on_req_cycles',
150: 'TA_PERF_SEL_in_addr_cycles',
151: 'TA_PERF_SEL_in_data_cycles',
154: 'TA_PERF_SEL_latency_ram_weights_written_cycles',
155: 'TA_PERF_SEL_latency_ram_ws_required_quads',
156: 'TA_PERF_SEL_latency_ram_whv_required_quads',
157: 'TA_PERF_SEL_latency_ram_ws_required_instructions',
158: 'TA_PERF_SEL_latency_ram_whv_required_instructions',
159: 'TA_PERF_SEL_latency_ram_ref_required_instructions',
160: 'TA_PERF_SEL_point_sampled_quads',
162: 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions',
163: 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions',
164: 'TA_PERF_SEL_atomic_write_data_input_cycles',
165: 'TA_PERF_SEL_atomic_write_data_output_cycles',
173: 'TA_PERF_SEL_num_unlit_nodes_ta_opt',
174: 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input',
175: 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob',
176: 'TA_PERF_SEL_num_of_bvh_valid_first_tri',
177: 'TA_PERF_SEL_num_of_bvh_valid_second_tri',
178: 'TA_PERF_SEL_num_of_bvh_valid_third_tri',
179: 'TA_PERF_SEL_num_of_bvh_valid_fourth_tri',
180: 'TA_PERF_SEL_num_of_bvh_valid_fp16_box',
181: 'TA_PERF_SEL_num_of_bvh_valid_fp32_box',
182: 'TA_PERF_SEL_num_of_bvh_invalidated_first_tri',
183: 'TA_PERF_SEL_num_of_bvh_invalidated_second_tri',
184: 'TA_PERF_SEL_num_of_bvh_invalidated_third_tri',
185: 'TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri',
186: 'TA_PERF_SEL_num_of_bvh_invalidated_fp16_box',
187: 'TA_PERF_SEL_num_of_bvh_invalidated_fp32_box',
188: 'TA_PERF_SEL_image_bvh_8_input_vgpr_instructions',
189: 'TA_PERF_SEL_image_bvh_9_input_vgpr_instructions',
190: 'TA_PERF_SEL_image_bvh_11_input_vgpr_instructions',
191: 'TA_PERF_SEL_image_bvh_12_input_vgpr_instructions',
192: 'TA_PERF_SEL_image_sampler_1_op_burst',
193: 'TA_PERF_SEL_image_sampler_2to3_op_burst',
194: 'TA_PERF_SEL_image_sampler_4to7_op_burst',
195: 'TA_PERF_SEL_image_sampler_ge8_op_burst',
196: 'TA_PERF_SEL_image_linked_1_op_burst',
197: 'TA_PERF_SEL_image_linked_2to3_op_burst',
198: 'TA_PERF_SEL_image_linked_4to7_op_burst',
199: 'TA_PERF_SEL_image_linked_ge8_op_burst',
200: 'TA_PERF_SEL_image_bvh_1_op_burst',
201: 'TA_PERF_SEL_image_bvh_2to3_op_burst',
202: 'TA_PERF_SEL_image_bvh_4to7_op_burst',
203: 'TA_PERF_SEL_image_bvh_ge8_op_burst',
204: 'TA_PERF_SEL_image_nosampler_1_op_burst',
205: 'TA_PERF_SEL_image_nosampler_2to3_op_burst',
206: 'TA_PERF_SEL_image_nosampler_4to31_op_burst',
207: 'TA_PERF_SEL_image_nosampler_ge32_op_burst',
208: 'TA_PERF_SEL_buffer_flat_1_op_burst',
209: 'TA_PERF_SEL_buffer_flat_2to3_op_burst',
210: 'TA_PERF_SEL_buffer_flat_4to31_op_burst',
211: 'TA_PERF_SEL_buffer_flat_ge32_op_burst',
212: 'TA_PERF_SEL_write_1_op_burst',
213: 'TA_PERF_SEL_write_2to3_op_burst',
214: 'TA_PERF_SEL_write_4to31_op_burst',
215: 'TA_PERF_SEL_write_ge32_op_burst',
216: 'TA_PERF_SEL_ibubble_1_cycle_burst',
217: 'TA_PERF_SEL_ibubble_2to3_cycle_burst',
218: 'TA_PERF_SEL_ibubble_4to15_cycle_burst',
219: 'TA_PERF_SEL_ibubble_16to31_cycle_burst',
220: 'TA_PERF_SEL_ibubble_32to63_cycle_burst',
221: 'TA_PERF_SEL_ibubble_ge64_cycle_burst',
224: 'TA_PERF_SEL_sampler_clk_valid_cycles',
225: 'TA_PERF_SEL_nonsampler_clk_valid_cycles',
226: 'TA_PERF_SEL_buffer_flat_clk_valid_cycles',
227: 'TA_PERF_SEL_write_data_clk_valid_cycles',
228: 'TA_PERF_SEL_gradient_clk_valid_cycles',
229: 'TA_PERF_SEL_lod_aniso_clk_valid_cycles',
230: 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles',
231: 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles',
232: 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles',
233: 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles',
234: 'TA_PERF_SEL_aligner_clk_valid_cycles',
235: 'TA_PERF_SEL_tcreq_clk_valid_cycles',
}
TA_PERF_SEL_NULL = 0
TA_PERF_SEL_image_sampler_has_offset_instructions = 1
TA_PERF_SEL_image_sampler_has_bias_instructions = 2
TA_PERF_SEL_image_sampler_has_reference_instructions = 3
TA_PERF_SEL_image_sampler_has_ds_instructions = 4
TA_PERF_SEL_image_sampler_has_dt_instructions = 5
TA_PERF_SEL_image_sampler_has_dr_instructions = 6
TA_PERF_SEL_gradient_busy = 7
TA_PERF_SEL_gradient_fifo_busy = 8
TA_PERF_SEL_lod_busy = 9
TA_PERF_SEL_lod_fifo_busy = 10
TA_PERF_SEL_addresser_busy = 11
TA_PERF_SEL_addresser_fifo_busy = 12
TA_PERF_SEL_aligner_busy = 13
TA_PERF_SEL_write_path_busy = 14
TA_PERF_SEL_ta_busy = 15
TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 16
TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 17
TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 18
TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 19
TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 20
TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 21
TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 22
TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 23
TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 24
TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 25
TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 26
TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 27
TA_PERF_SEL_image_sampler_has_t_instructions = 28
TA_PERF_SEL_image_sampler_has_r_instructions = 29
TA_PERF_SEL_image_sampler_has_q_instructions = 30
TA_PERF_SEL_total_wavefronts = 32
TA_PERF_SEL_gradient_cycles = 33
TA_PERF_SEL_walker_cycles = 34
TA_PERF_SEL_aligner_cycles = 35
TA_PERF_SEL_image_wavefronts = 36
TA_PERF_SEL_image_read_wavefronts = 37
TA_PERF_SEL_image_store_wavefronts = 38
TA_PERF_SEL_image_atomic_wavefronts = 39
TA_PERF_SEL_image_sampler_total_cycles = 40
TA_PERF_SEL_image_nosampler_total_cycles = 41
TA_PERF_SEL_flat_total_cycles = 42
TA_PERF_SEL_bvh_total_cycles = 43
TA_PERF_SEL_buffer_wavefronts = 44
TA_PERF_SEL_buffer_load_wavefronts = 45
TA_PERF_SEL_buffer_store_wavefronts = 46
TA_PERF_SEL_buffer_atomic_wavefronts = 47
TA_PERF_SEL_buffer_total_cycles = 49
TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 50
TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 51
TA_PERF_SEL_buffer_has_index_instructions = 52
TA_PERF_SEL_buffer_has_offset_instructions = 53
TA_PERF_SEL_addr_stalled_by_tc_cycles = 54
TA_PERF_SEL_addr_stalled_by_td_cycles = 55
TA_PERF_SEL_image_sampler_wavefronts = 56
TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57
TA_PERF_SEL_addresser_stalled_cycles = 58
TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59
TA_PERF_SEL_aniso_stalled_cycles = 60
TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61
TA_PERF_SEL_deriv_stalled_cycles = 62
TA_PERF_SEL_aniso_gt1_cycle_quads = 63
TA_PERF_SEL_color_1_cycle_quads = 64
TA_PERF_SEL_color_2_cycle_quads = 65
TA_PERF_SEL_color_3_cycle_quads = 66
TA_PERF_SEL_mip_1_cycle_quads = 68
TA_PERF_SEL_mip_2_cycle_quads = 69
TA_PERF_SEL_vol_1_cycle_quads = 70
TA_PERF_SEL_vol_2_cycle_quads = 71
TA_PERF_SEL_sampler_op_quads = 72
TA_PERF_SEL_mipmap_lod_0_samples = 73
TA_PERF_SEL_mipmap_lod_1_samples = 74
TA_PERF_SEL_mipmap_lod_2_samples = 75
TA_PERF_SEL_mipmap_lod_3_samples = 76
TA_PERF_SEL_mipmap_lod_4_samples = 77
TA_PERF_SEL_mipmap_lod_5_samples = 78
TA_PERF_SEL_mipmap_lod_6_samples = 79
TA_PERF_SEL_mipmap_lod_7_samples = 80
TA_PERF_SEL_mipmap_lod_8_samples = 81
TA_PERF_SEL_mipmap_lod_9_samples = 82
TA_PERF_SEL_mipmap_lod_10_samples = 83
TA_PERF_SEL_mipmap_lod_11_samples = 84
TA_PERF_SEL_mipmap_lod_12_samples = 85
TA_PERF_SEL_mipmap_lod_13_samples = 86
TA_PERF_SEL_mipmap_lod_14_samples = 87
TA_PERF_SEL_mipmap_invalid_samples = 88
TA_PERF_SEL_aniso_1_cycle_quads = 89
TA_PERF_SEL_aniso_2_cycle_quads = 90
TA_PERF_SEL_aniso_4_cycle_quads = 91
TA_PERF_SEL_aniso_6_cycle_quads = 92
TA_PERF_SEL_aniso_8_cycle_quads = 93
TA_PERF_SEL_aniso_10_cycle_quads = 94
TA_PERF_SEL_aniso_12_cycle_quads = 95
TA_PERF_SEL_aniso_14_cycle_quads = 96
TA_PERF_SEL_aniso_16_cycle_quads = 97
TA_PERF_SEL_store_write_data_input_cycles = 98
TA_PERF_SEL_store_write_data_output_cycles = 99
TA_PERF_SEL_flat_wavefronts = 100
TA_PERF_SEL_flat_load_wavefronts = 101
TA_PERF_SEL_flat_store_wavefronts = 102
TA_PERF_SEL_flat_atomic_wavefronts = 103
TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 104
TA_PERF_SEL_register_clk_valid_cycles = 105
TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 106
TA_PERF_SEL_harvestable_clk_enabled_cycles = 107
TA_PERF_SEL_harvestable_register_clk_enabled_cycles = 108
TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 109
TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 110
TA_PERF_SEL_store_2_write_data_vgpr_instructions = 114
TA_PERF_SEL_store_3_write_data_vgpr_instructions = 115
TA_PERF_SEL_store_4_write_data_vgpr_instructions = 116
TA_PERF_SEL_store_has_x_instructions = 117
TA_PERF_SEL_store_has_y_instructions = 118
TA_PERF_SEL_store_has_z_instructions = 119
TA_PERF_SEL_store_has_w_instructions = 120
TA_PERF_SEL_image_nosampler_has_t_instructions = 121
TA_PERF_SEL_image_nosampler_has_r_instructions = 122
TA_PERF_SEL_image_nosampler_has_q_instructions = 123
TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 124
TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 125
TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 126
TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 127
TA_PERF_SEL_in_busy = 128
TA_PERF_SEL_in_fifos_busy = 129
TA_PERF_SEL_in_cfifo_busy = 130
TA_PERF_SEL_in_qfifo_busy = 131
TA_PERF_SEL_in_wfifo_busy = 132
TA_PERF_SEL_in_rfifo_busy = 133
TA_PERF_SEL_bf_busy = 134
TA_PERF_SEL_ns_busy = 135
TA_PERF_SEL_smp_busy_ns_idle = 136
TA_PERF_SEL_smp_idle_ns_busy = 137
TA_PERF_SEL_vmemcmd_cycles = 144
TA_PERF_SEL_vmemreq_cycles = 145
TA_PERF_SEL_in_waiting_on_req_cycles = 146
TA_PERF_SEL_in_addr_cycles = 150
TA_PERF_SEL_in_data_cycles = 151
TA_PERF_SEL_latency_ram_weights_written_cycles = 154
TA_PERF_SEL_latency_ram_ws_required_quads = 155
TA_PERF_SEL_latency_ram_whv_required_quads = 156
TA_PERF_SEL_latency_ram_ws_required_instructions = 157
TA_PERF_SEL_latency_ram_whv_required_instructions = 158
TA_PERF_SEL_latency_ram_ref_required_instructions = 159
TA_PERF_SEL_point_sampled_quads = 160
TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 162
TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 163
TA_PERF_SEL_atomic_write_data_input_cycles = 164
TA_PERF_SEL_atomic_write_data_output_cycles = 165
TA_PERF_SEL_num_unlit_nodes_ta_opt = 173
TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 174
TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 175
TA_PERF_SEL_num_of_bvh_valid_first_tri = 176
TA_PERF_SEL_num_of_bvh_valid_second_tri = 177
TA_PERF_SEL_num_of_bvh_valid_third_tri = 178
TA_PERF_SEL_num_of_bvh_valid_fourth_tri = 179
TA_PERF_SEL_num_of_bvh_valid_fp16_box = 180
TA_PERF_SEL_num_of_bvh_valid_fp32_box = 181
TA_PERF_SEL_num_of_bvh_invalidated_first_tri = 182
TA_PERF_SEL_num_of_bvh_invalidated_second_tri = 183
TA_PERF_SEL_num_of_bvh_invalidated_third_tri = 184
TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri = 185
TA_PERF_SEL_num_of_bvh_invalidated_fp16_box = 186
TA_PERF_SEL_num_of_bvh_invalidated_fp32_box = 187
TA_PERF_SEL_image_bvh_8_input_vgpr_instructions = 188
TA_PERF_SEL_image_bvh_9_input_vgpr_instructions = 189
TA_PERF_SEL_image_bvh_11_input_vgpr_instructions = 190
TA_PERF_SEL_image_bvh_12_input_vgpr_instructions = 191
TA_PERF_SEL_image_sampler_1_op_burst = 192
TA_PERF_SEL_image_sampler_2to3_op_burst = 193
TA_PERF_SEL_image_sampler_4to7_op_burst = 194
TA_PERF_SEL_image_sampler_ge8_op_burst = 195
TA_PERF_SEL_image_linked_1_op_burst = 196
TA_PERF_SEL_image_linked_2to3_op_burst = 197
TA_PERF_SEL_image_linked_4to7_op_burst = 198
TA_PERF_SEL_image_linked_ge8_op_burst = 199
TA_PERF_SEL_image_bvh_1_op_burst = 200
TA_PERF_SEL_image_bvh_2to3_op_burst = 201
TA_PERF_SEL_image_bvh_4to7_op_burst = 202
TA_PERF_SEL_image_bvh_ge8_op_burst = 203
TA_PERF_SEL_image_nosampler_1_op_burst = 204
TA_PERF_SEL_image_nosampler_2to3_op_burst = 205
TA_PERF_SEL_image_nosampler_4to31_op_burst = 206
TA_PERF_SEL_image_nosampler_ge32_op_burst = 207
TA_PERF_SEL_buffer_flat_1_op_burst = 208
TA_PERF_SEL_buffer_flat_2to3_op_burst = 209
TA_PERF_SEL_buffer_flat_4to31_op_burst = 210
TA_PERF_SEL_buffer_flat_ge32_op_burst = 211
TA_PERF_SEL_write_1_op_burst = 212
TA_PERF_SEL_write_2to3_op_burst = 213
TA_PERF_SEL_write_4to31_op_burst = 214
TA_PERF_SEL_write_ge32_op_burst = 215
TA_PERF_SEL_ibubble_1_cycle_burst = 216
TA_PERF_SEL_ibubble_2to3_cycle_burst = 217
TA_PERF_SEL_ibubble_4to15_cycle_burst = 218
TA_PERF_SEL_ibubble_16to31_cycle_burst = 219
TA_PERF_SEL_ibubble_32to63_cycle_burst = 220
TA_PERF_SEL_ibubble_ge64_cycle_burst = 221
TA_PERF_SEL_sampler_clk_valid_cycles = 224
TA_PERF_SEL_nonsampler_clk_valid_cycles = 225
TA_PERF_SEL_buffer_flat_clk_valid_cycles = 226
TA_PERF_SEL_write_data_clk_valid_cycles = 227
TA_PERF_SEL_gradient_clk_valid_cycles = 228
TA_PERF_SEL_lod_aniso_clk_valid_cycles = 229
TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 230
TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 231
TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 232
TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 233
TA_PERF_SEL_aligner_clk_valid_cycles = 234
TA_PERF_SEL_tcreq_clk_valid_cycles = 235
TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TEX_BC_SWIZZLE'
TEX_BC_SWIZZLE__enumvalues = {
0: 'TEX_BC_Swizzle_XYZW',
1: 'TEX_BC_Swizzle_XWYZ',
2: 'TEX_BC_Swizzle_WZYX',
3: 'TEX_BC_Swizzle_WXYZ',
4: 'TEX_BC_Swizzle_ZYXW',
5: 'TEX_BC_Swizzle_YXWZ',
}
TEX_BC_Swizzle_XYZW = 0
TEX_BC_Swizzle_XWYZ = 1
TEX_BC_Swizzle_WZYX = 2
TEX_BC_Swizzle_WXYZ = 3
TEX_BC_Swizzle_ZYXW = 4
TEX_BC_Swizzle_YXWZ = 5
TEX_BC_SWIZZLE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_BORDER_COLOR_TYPE'
TEX_BORDER_COLOR_TYPE__enumvalues = {
0: 'TEX_BorderColor_TransparentBlack',
1: 'TEX_BorderColor_OpaqueBlack',
2: 'TEX_BorderColor_OpaqueWhite',
3: 'TEX_BorderColor_Register',
}
TEX_BorderColor_TransparentBlack = 0
TEX_BorderColor_OpaqueBlack = 1
TEX_BorderColor_OpaqueWhite = 2
TEX_BorderColor_Register = 3
TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_CHROMA_KEY'
TEX_CHROMA_KEY__enumvalues = {
0: 'TEX_ChromaKey_Disabled',
1: 'TEX_ChromaKey_Kill',
2: 'TEX_ChromaKey_Blend',
3: 'TEX_ChromaKey_RESERVED_3',
}
TEX_ChromaKey_Disabled = 0
TEX_ChromaKey_Kill = 1
TEX_ChromaKey_Blend = 2
TEX_ChromaKey_RESERVED_3 = 3
TEX_CHROMA_KEY = ctypes.c_uint32 # enum
# values for enumeration 'TEX_CLAMP'
TEX_CLAMP__enumvalues = {
0: 'TEX_Clamp_Repeat',
1: 'TEX_Clamp_Mirror',
2: 'TEX_Clamp_ClampToLast',
3: 'TEX_Clamp_MirrorOnceToLast',
4: 'TEX_Clamp_ClampHalfToBorder',
5: 'TEX_Clamp_MirrorOnceHalfToBorder',
6: 'TEX_Clamp_ClampToBorder',
7: 'TEX_Clamp_MirrorOnceToBorder',
}
TEX_Clamp_Repeat = 0
TEX_Clamp_Mirror = 1
TEX_Clamp_ClampToLast = 2
TEX_Clamp_MirrorOnceToLast = 3
TEX_Clamp_ClampHalfToBorder = 4
TEX_Clamp_MirrorOnceHalfToBorder = 5
TEX_Clamp_ClampToBorder = 6
TEX_Clamp_MirrorOnceToBorder = 7
TEX_CLAMP = ctypes.c_uint32 # enum
# values for enumeration 'TEX_COORD_TYPE'
TEX_COORD_TYPE__enumvalues = {
0: 'TEX_CoordType_Unnormalized',
1: 'TEX_CoordType_Normalized',
}
TEX_CoordType_Unnormalized = 0
TEX_CoordType_Normalized = 1
TEX_COORD_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION'
TEX_DEPTH_COMPARE_FUNCTION__enumvalues = {
0: 'TEX_DepthCompareFunction_Never',
1: 'TEX_DepthCompareFunction_Less',
2: 'TEX_DepthCompareFunction_Equal',
3: 'TEX_DepthCompareFunction_LessEqual',
4: 'TEX_DepthCompareFunction_Greater',
5: 'TEX_DepthCompareFunction_NotEqual',
6: 'TEX_DepthCompareFunction_GreaterEqual',
7: 'TEX_DepthCompareFunction_Always',
}
TEX_DepthCompareFunction_Never = 0
TEX_DepthCompareFunction_Less = 1
TEX_DepthCompareFunction_Equal = 2
TEX_DepthCompareFunction_LessEqual = 3
TEX_DepthCompareFunction_Greater = 4
TEX_DepthCompareFunction_NotEqual = 5
TEX_DepthCompareFunction_GreaterEqual = 6
TEX_DepthCompareFunction_Always = 7
TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum
# values for enumeration 'TEX_FORMAT_COMP'
TEX_FORMAT_COMP__enumvalues = {
0: 'TEX_FormatComp_Unsigned',
1: 'TEX_FormatComp_Signed',
2: 'TEX_FormatComp_UnsignedBiased',
3: 'TEX_FormatComp_RESERVED_3',
}
TEX_FormatComp_Unsigned = 0
TEX_FormatComp_Signed = 1
TEX_FormatComp_UnsignedBiased = 2
TEX_FormatComp_RESERVED_3 = 3
TEX_FORMAT_COMP = ctypes.c_uint32 # enum
# values for enumeration 'TEX_MAX_ANISO_RATIO'
TEX_MAX_ANISO_RATIO__enumvalues = {
0: 'TEX_MaxAnisoRatio_1to1',
1: 'TEX_MaxAnisoRatio_2to1',
2: 'TEX_MaxAnisoRatio_4to1',
3: 'TEX_MaxAnisoRatio_8to1',
4: 'TEX_MaxAnisoRatio_16to1',
5: 'TEX_MaxAnisoRatio_RESERVED_5',
6: 'TEX_MaxAnisoRatio_RESERVED_6',
7: 'TEX_MaxAnisoRatio_RESERVED_7',
}
TEX_MaxAnisoRatio_1to1 = 0
TEX_MaxAnisoRatio_2to1 = 1
TEX_MaxAnisoRatio_4to1 = 2
TEX_MaxAnisoRatio_8to1 = 3
TEX_MaxAnisoRatio_16to1 = 4
TEX_MaxAnisoRatio_RESERVED_5 = 5
TEX_MaxAnisoRatio_RESERVED_6 = 6
TEX_MaxAnisoRatio_RESERVED_7 = 7
TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum
# values for enumeration 'TEX_MIP_FILTER'
TEX_MIP_FILTER__enumvalues = {
0: 'TEX_MipFilter_None',
1: 'TEX_MipFilter_Point',
2: 'TEX_MipFilter_Linear',
3: 'TEX_MipFilter_Point_Aniso_Adj',
}
TEX_MipFilter_None = 0
TEX_MipFilter_Point = 1
TEX_MipFilter_Linear = 2
TEX_MipFilter_Point_Aniso_Adj = 3
TEX_MIP_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'TEX_REQUEST_SIZE'
TEX_REQUEST_SIZE__enumvalues = {
0: 'TEX_RequestSize_32B',
1: 'TEX_RequestSize_64B',
2: 'TEX_RequestSize_128B',
3: 'TEX_RequestSize_2X64B',
}
TEX_RequestSize_32B = 0
TEX_RequestSize_64B = 1
TEX_RequestSize_128B = 2
TEX_RequestSize_2X64B = 3
TEX_REQUEST_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_SAMPLER_TYPE'
TEX_SAMPLER_TYPE__enumvalues = {
0: 'TEX_SamplerType_Invalid',
1: 'TEX_SamplerType_Valid',
}
TEX_SamplerType_Invalid = 0
TEX_SamplerType_Valid = 1
TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'TEX_XY_FILTER'
TEX_XY_FILTER__enumvalues = {
0: 'TEX_XYFilter_Point',
1: 'TEX_XYFilter_Linear',
2: 'TEX_XYFilter_AnisoPoint',
3: 'TEX_XYFilter_AnisoLinear',
}
TEX_XYFilter_Point = 0
TEX_XYFilter_Linear = 1
TEX_XYFilter_AnisoPoint = 2
TEX_XYFilter_AnisoLinear = 3
TEX_XY_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'TEX_Z_FILTER'
TEX_Z_FILTER__enumvalues = {
0: 'TEX_ZFilter_None',
1: 'TEX_ZFilter_Point',
2: 'TEX_ZFilter_Linear',
3: 'TEX_ZFilter_RESERVED_3',
}
TEX_ZFilter_None = 0
TEX_ZFilter_Point = 1
TEX_ZFilter_Linear = 2
TEX_ZFilter_RESERVED_3 = 3
TEX_Z_FILTER = ctypes.c_uint32 # enum
# values for enumeration 'TVX_TYPE'
TVX_TYPE__enumvalues = {
0: 'TVX_Type_InvalidTextureResource',
1: 'TVX_Type_InvalidVertexBuffer',
2: 'TVX_Type_ValidTextureResource',
3: 'TVX_Type_ValidVertexBuffer',
}
TVX_Type_InvalidTextureResource = 0
TVX_Type_InvalidVertexBuffer = 1
TVX_Type_ValidTextureResource = 2
TVX_Type_ValidVertexBuffer = 3
TVX_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'TA_TC_ADDR_MODES'
TA_TC_ADDR_MODES__enumvalues = {
0: 'TA_TC_ADDR_MODE_DEFAULT',
1: 'TA_TC_ADDR_MODE_COMP0',
2: 'TA_TC_ADDR_MODE_COMP1',
3: 'TA_TC_ADDR_MODE_COMP2',
4: 'TA_TC_ADDR_MODE_COMP3',
5: 'TA_TC_ADDR_MODE_UNALIGNED',
6: 'TA_TC_ADDR_MODE_BORDER_COLOR',
}
TA_TC_ADDR_MODE_DEFAULT = 0
TA_TC_ADDR_MODE_COMP0 = 1
TA_TC_ADDR_MODE_COMP1 = 2
TA_TC_ADDR_MODE_COMP2 = 3
TA_TC_ADDR_MODE_COMP3 = 4
TA_TC_ADDR_MODE_UNALIGNED = 5
TA_TC_ADDR_MODE_BORDER_COLOR = 6
TA_TC_ADDR_MODES = ctypes.c_uint32 # enum
# values for enumeration 'TA_TC_REQ_MODES'
TA_TC_REQ_MODES__enumvalues = {
0: 'TA_TC_REQ_MODE_BORDER',
1: 'TA_TC_REQ_MODE_TEX2',
2: 'TA_TC_REQ_MODE_TEX1',
3: 'TA_TC_REQ_MODE_TEX0',
4: 'TA_TC_REQ_MODE_NORMAL',
5: 'TA_TC_REQ_MODE_DWORD',
6: 'TA_TC_REQ_MODE_BYTE',
7: 'TA_TC_REQ_MODE_BYTE_NV',
}
TA_TC_REQ_MODE_BORDER = 0
TA_TC_REQ_MODE_TEX2 = 1
TA_TC_REQ_MODE_TEX1 = 2
TA_TC_REQ_MODE_TEX0 = 3
TA_TC_REQ_MODE_NORMAL = 4
TA_TC_REQ_MODE_DWORD = 5
TA_TC_REQ_MODE_BYTE = 6
TA_TC_REQ_MODE_BYTE_NV = 7
TA_TC_REQ_MODES = ctypes.c_uint32 # enum
# values for enumeration 'TCP_CACHE_POLICIES'
TCP_CACHE_POLICIES__enumvalues = {
0: 'TCP_CACHE_POLICY_MISS_LRU',
1: 'TCP_CACHE_POLICY_MISS_EVICT',
2: 'TCP_CACHE_POLICY_HIT_LRU',
3: 'TCP_CACHE_POLICY_HIT_EVICT',
}
TCP_CACHE_POLICY_MISS_LRU = 0
TCP_CACHE_POLICY_MISS_EVICT = 1
TCP_CACHE_POLICY_HIT_LRU = 2
TCP_CACHE_POLICY_HIT_EVICT = 3
TCP_CACHE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'TCP_CACHE_STORE_POLICIES'
TCP_CACHE_STORE_POLICIES__enumvalues = {
0: 'TCP_CACHE_STORE_POLICY_WT_LRU',
1: 'TCP_CACHE_STORE_POLICY_WT_EVICT',
}
TCP_CACHE_STORE_POLICY_WT_LRU = 0
TCP_CACHE_STORE_POLICY_WT_EVICT = 1
TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum
# values for enumeration 'TCP_DSM_DATA_SEL'
TCP_DSM_DATA_SEL__enumvalues = {
0: 'TCP_DSM_DISABLE',
1: 'TCP_DSM_SEL0',
2: 'TCP_DSM_SEL1',
3: 'TCP_DSM_SEL_BOTH',
}
TCP_DSM_DISABLE = 0
TCP_DSM_SEL0 = 1
TCP_DSM_SEL1 = 2
TCP_DSM_SEL_BOTH = 3
TCP_DSM_DATA_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TCP_DSM_INJECT_SEL'
TCP_DSM_INJECT_SEL__enumvalues = {
0: 'TCP_DSM_INJECT_SEL0',
1: 'TCP_DSM_INJECT_SEL1',
2: 'TCP_DSM_INJECT_SEL2',
3: 'TCP_DSM_INJECT_SEL3',
}
TCP_DSM_INJECT_SEL0 = 0
TCP_DSM_INJECT_SEL1 = 1
TCP_DSM_INJECT_SEL2 = 2
TCP_DSM_INJECT_SEL3 = 3
TCP_DSM_INJECT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'TCP_DSM_SINGLE_WRITE'
TCP_DSM_SINGLE_WRITE__enumvalues = {
0: 'TCP_DSM_SINGLE_WRITE_DIS',
1: 'TCP_DSM_SINGLE_WRITE_EN',
}
TCP_DSM_SINGLE_WRITE_DIS = 0
TCP_DSM_SINGLE_WRITE_EN = 1
TCP_DSM_SINGLE_WRITE = ctypes.c_uint32 # enum
# values for enumeration 'TCP_OPCODE_TYPE'
TCP_OPCODE_TYPE__enumvalues = {
0: 'TCP_OPCODE_READ',
1: 'TCP_OPCODE_WRITE',
2: 'TCP_OPCODE_ATOMIC',
3: 'TCP_OPCODE_INV',
4: 'TCP_OPCODE_ATOMIC_CMPSWAP',
5: 'TCP_OPCODE_SAMPLER',
6: 'TCP_OPCODE_LOAD',
7: 'TCP_OPCODE_GATHERH',
}
TCP_OPCODE_READ = 0
TCP_OPCODE_WRITE = 1
TCP_OPCODE_ATOMIC = 2
TCP_OPCODE_INV = 3
TCP_OPCODE_ATOMIC_CMPSWAP = 4
TCP_OPCODE_SAMPLER = 5
TCP_OPCODE_LOAD = 6
TCP_OPCODE_GATHERH = 7
TCP_OPCODE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'TCP_PERFCOUNT_SELECT'
TCP_PERFCOUNT_SELECT__enumvalues = {
0: 'TCP_PERF_SEL_GATE_EN1',
1: 'TCP_PERF_SEL_GATE_EN2',
2: 'TCP_PERF_SEL_TA_REQ',
3: 'TCP_PERF_SEL_TA_REQ_STATE_READ',
4: 'TCP_PERF_SEL_TA_REQ_READ',
5: 'TCP_PERF_SEL_TA_REQ_WRITE',
6: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET',
7: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET',
8: 'TCP_PERF_SEL_TA_REQ_GL0_INV',
9: 'TCP_PERF_SEL_REQ',
10: 'TCP_PERF_SEL_REQ_READ',
11: 'TCP_PERF_SEL_REQ_READ_HIT_EVICT',
12: 'TCP_PERF_SEL_REQ_READ_HIT_LRU',
13: 'TCP_PERF_SEL_REQ_READ_MISS_EVICT',
14: 'TCP_PERF_SEL_REQ_WRITE',
15: 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT',
16: 'TCP_PERF_SEL_REQ_WRITE_MISS_LRU',
17: 'TCP_PERF_SEL_REQ_NON_READ',
18: 'TCP_PERF_SEL_REQ_MISS',
19: 'TCP_PERF_SEL_REQ_TAGBANK0_SET0',
20: 'TCP_PERF_SEL_REQ_TAGBANK0_SET1',
21: 'TCP_PERF_SEL_REQ_TAGBANK1_SET0',
22: 'TCP_PERF_SEL_REQ_TAGBANK1_SET1',
23: 'TCP_PERF_SEL_REQ_TAGBANK2_SET0',
24: 'TCP_PERF_SEL_REQ_TAGBANK2_SET1',
25: 'TCP_PERF_SEL_REQ_TAGBANK3_SET0',
26: 'TCP_PERF_SEL_REQ_TAGBANK3_SET1',
27: 'TCP_PERF_SEL_REQ_MISS_TAGBANK0',
28: 'TCP_PERF_SEL_REQ_MISS_TAGBANK1',
29: 'TCP_PERF_SEL_REQ_MISS_TAGBANK2',
30: 'TCP_PERF_SEL_REQ_MISS_TAGBANK3',
31: 'TCP_PERF_SEL_GL1_REQ_READ',
32: 'TCP_PERF_SEL_GL1_REQ_READ_128B',
33: 'TCP_PERF_SEL_GL1_REQ_READ_64B',
34: 'TCP_PERF_SEL_GL1_REQ_WRITE',
35: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET',
36: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET',
37: 'TCP_PERF_SEL_GL1_READ_LATENCY',
38: 'TCP_PERF_SEL_GL1_WRITE_LATENCY',
39: 'TCP_PERF_SEL_TCP_LATENCY',
40: 'TCP_PERF_SEL_TCP_TA_REQ_STALL',
41: 'TCP_PERF_SEL_TA_TCP_REQ_STARVE',
42: 'TCP_PERF_SEL_DATA_FIFO_STALL',
43: 'TCP_PERF_SEL_LOD_STALL',
44: 'TCP_PERF_SEL_POWER_STALL',
45: 'TCP_PERF_SEL_ALLOC_STALL',
46: 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL',
47: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL',
48: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL',
49: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL',
50: 'TCP_PERF_SEL_LFIFO_STALL',
51: 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL',
52: 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE',
53: 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL',
54: 'TCP_PERF_SEL_GL1_GRANT_READ_STALL',
55: 'TCP_PERF_SEL_GL1_PENDING_STALL',
56: 'TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL',
57: 'TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL',
58: 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL',
59: 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL',
60: 'TCP_PERF_SEL_READ_DATACONFLICT_STALL',
61: 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL',
62: 'TCP_PERF_SEL_TD_TCP_STALL',
}
TCP_PERF_SEL_GATE_EN1 = 0
TCP_PERF_SEL_GATE_EN2 = 1
TCP_PERF_SEL_TA_REQ = 2
TCP_PERF_SEL_TA_REQ_STATE_READ = 3
TCP_PERF_SEL_TA_REQ_READ = 4
TCP_PERF_SEL_TA_REQ_WRITE = 5
TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 6
TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 7
TCP_PERF_SEL_TA_REQ_GL0_INV = 8
TCP_PERF_SEL_REQ = 9
TCP_PERF_SEL_REQ_READ = 10
TCP_PERF_SEL_REQ_READ_HIT_EVICT = 11
TCP_PERF_SEL_REQ_READ_HIT_LRU = 12
TCP_PERF_SEL_REQ_READ_MISS_EVICT = 13
TCP_PERF_SEL_REQ_WRITE = 14
TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 15
TCP_PERF_SEL_REQ_WRITE_MISS_LRU = 16
TCP_PERF_SEL_REQ_NON_READ = 17
TCP_PERF_SEL_REQ_MISS = 18
TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 19
TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 20
TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 21
TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 22
TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 23
TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 24
TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 25
TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 26
TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 27
TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 28
TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 29
TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 30
TCP_PERF_SEL_GL1_REQ_READ = 31
TCP_PERF_SEL_GL1_REQ_READ_128B = 32
TCP_PERF_SEL_GL1_REQ_READ_64B = 33
TCP_PERF_SEL_GL1_REQ_WRITE = 34
TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 35
TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 36
TCP_PERF_SEL_GL1_READ_LATENCY = 37
TCP_PERF_SEL_GL1_WRITE_LATENCY = 38
TCP_PERF_SEL_TCP_LATENCY = 39
TCP_PERF_SEL_TCP_TA_REQ_STALL = 40
TCP_PERF_SEL_TA_TCP_REQ_STARVE = 41
TCP_PERF_SEL_DATA_FIFO_STALL = 42
TCP_PERF_SEL_LOD_STALL = 43
TCP_PERF_SEL_POWER_STALL = 44
TCP_PERF_SEL_ALLOC_STALL = 45
TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 46
TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 47
TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 48
TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 49
TCP_PERF_SEL_LFIFO_STALL = 50
TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 51
TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 52
TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 53
TCP_PERF_SEL_GL1_GRANT_READ_STALL = 54
TCP_PERF_SEL_GL1_PENDING_STALL = 55
TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL = 56
TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL = 57
TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 58
TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 59
TCP_PERF_SEL_READ_DATACONFLICT_STALL = 60
TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 61
TCP_PERF_SEL_TD_TCP_STALL = 62
TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'TCP_WATCH_MODES'
TCP_WATCH_MODES__enumvalues = {
0: 'TCP_WATCH_MODE_READ',
1: 'TCP_WATCH_MODE_NONREAD',
2: 'TCP_WATCH_MODE_ATOMIC',
3: 'TCP_WATCH_MODE_ALL',
}
TCP_WATCH_MODE_READ = 0
TCP_WATCH_MODE_NONREAD = 1
TCP_WATCH_MODE_ATOMIC = 2
TCP_WATCH_MODE_ALL = 3
TCP_WATCH_MODES = ctypes.c_uint32 # enum
# values for enumeration 'TD_PERFCOUNT_SEL'
TD_PERFCOUNT_SEL__enumvalues = {
0: 'TD_PERF_SEL_none',
1: 'TD_PERF_SEL_td_busy',
2: 'TD_PERF_SEL_input_busy',
3: 'TD_PERF_SEL_sampler_lerp_busy',
4: 'TD_PERF_SEL_sampler_out_busy',
5: 'TD_PERF_SEL_nofilter_busy',
6: 'TD_PERF_SEL_ray_tracing_bvh4_busy',
7: 'TD_PERF_SEL_sampler_core_sclk_en',
8: 'TD_PERF_SEL_sampler_preformatter_sclk_en',
9: 'TD_PERF_SEL_sampler_bilerp_sclk_en',
10: 'TD_PERF_SEL_sampler_bypass_sclk_en',
11: 'TD_PERF_SEL_sampler_minmax_sclk_en',
12: 'TD_PERF_SEL_sampler_accum_sclk_en',
13: 'TD_PERF_SEL_sampler_format_flt_sclk_en',
14: 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en',
15: 'TD_PERF_SEL_sampler_out_sclk_en',
16: 'TD_PERF_SEL_nofilter_sclk_en',
17: 'TD_PERF_SEL_nofilter_d32_sclk_en',
18: 'TD_PERF_SEL_nofilter_d16_sclk_en',
22: 'TD_PERF_SEL_ray_tracing_bvh4_sclk_en',
23: 'TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en',
24: 'TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en',
25: 'TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en',
26: 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off',
27: 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off',
28: 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time',
29: 'TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off',
30: 'TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off',
31: 'TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off',
32: 'TD_PERF_SEL_core_state_ram_max_cnt',
33: 'TD_PERF_SEL_core_state_rams_read',
34: 'TD_PERF_SEL_weight_data_rams_read',
35: 'TD_PERF_SEL_reference_data_rams_read',
36: 'TD_PERF_SEL_tc_td_ram_fifo_full',
37: 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt',
38: 'TD_PERF_SEL_tc_td_data_fifo_full',
39: 'TD_PERF_SEL_input_state_fifo_full',
40: 'TD_PERF_SEL_ta_data_stall',
41: 'TD_PERF_SEL_tc_data_stall',
42: 'TD_PERF_SEL_tc_ram_stall',
43: 'TD_PERF_SEL_lds_stall',
44: 'TD_PERF_SEL_sampler_pkr_full',
45: 'TD_PERF_SEL_sampler_pkr_full_due_to_arb',
46: 'TD_PERF_SEL_nofilter_pkr_full',
47: 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb',
48: 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full',
49: 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb',
50: 'TD_PERF_SEL_gather4_instr',
51: 'TD_PERF_SEL_gather4h_instr',
54: 'TD_PERF_SEL_sample_instr',
55: 'TD_PERF_SEL_sample_c_instr',
56: 'TD_PERF_SEL_load_instr',
57: 'TD_PERF_SEL_ldfptr_instr',
58: 'TD_PERF_SEL_write_ack_instr',
59: 'TD_PERF_SEL_d16_en_instr',
60: 'TD_PERF_SEL_bypassLerp_instr',
61: 'TD_PERF_SEL_min_max_filter_instr',
62: 'TD_PERF_SEL_one_comp_return_instr',
63: 'TD_PERF_SEL_two_comp_return_instr',
64: 'TD_PERF_SEL_three_comp_return_instr',
65: 'TD_PERF_SEL_four_comp_return_instr',
66: 'TD_PERF_SEL_user_defined_border',
67: 'TD_PERF_SEL_white_border',
68: 'TD_PERF_SEL_opaque_black_border',
69: 'TD_PERF_SEL_lod_warn_from_ta',
70: 'TD_PERF_SEL_instruction_dest_is_lds',
71: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles',
72: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles',
73: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles',
74: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles',
75: 'TD_PERF_SEL_out_of_order_instr',
76: 'TD_PERF_SEL_total_num_instr',
77: 'TD_PERF_SEL_total_num_instr_with_perf_wdw',
78: 'TD_PERF_SEL_total_num_sampler_instr',
79: 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw',
80: 'TD_PERF_SEL_total_num_nofilter_instr',
81: 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw',
82: 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr',
83: 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw',
84: 'TD_PERF_SEL_mixmode_instr',
85: 'TD_PERF_SEL_mixmode_resource',
86: 'TD_PERF_SEL_status_packet',
87: 'TD_PERF_SEL_address_cmd_poison',
88: 'TD_PERF_SEL_data_poison',
89: 'TD_PERF_SEL_done_scoreboard_max_stored_cnt',
90: 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt',
91: 'TD_PERF_SEL_done_scoreboard_not_empty',
92: 'TD_PERF_SEL_done_scoreboard_is_full',
93: 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo',
94: 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds',
95: 'TD_PERF_SEL_nofilter_formatters_turned_on',
96: 'TD_PERF_SEL_nofilter_insert_extra_comps',
97: 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt',
98: 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt',
99: 'TD_PERF_SEL_msaa_load_instr',
100: 'TD_PERF_SEL_blend_prt_with_prt_default_0',
101: 'TD_PERF_SEL_blend_prt_with_prt_default_1',
102: 'TD_PERF_SEL_resmap_instr',
103: 'TD_PERF_SEL_prt_ack_instr',
104: 'TD_PERF_SEL_resmap_with_volume_filtering',
105: 'TD_PERF_SEL_resmap_with_aniso_filtering',
106: 'TD_PERF_SEL_resmap_with_no_more_filtering',
107: 'TD_PERF_SEL_resmap_with_cubemap_corner',
108: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0',
109: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1',
110: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2',
111: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4',
112: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8',
113: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16',
114: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31',
115: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32',
116: 'TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node',
117: 'TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node',
118: 'TD_PERF_SEL_ray_tracing_bvh4_tri_node',
119: 'TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node',
120: 'TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node',
121: 'TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node',
122: 'TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node',
123: 'TD_PERF_SEL_ray_tracing_bvh4_box_sort_en',
124: 'TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero',
125: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx',
126: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx',
127: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan',
128: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_misses',
129: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses',
130: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers',
131: 'TD_PERF_SEL_burst_bin_preempting_nofilter_1',
132: 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4',
133: 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7',
134: 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16',
135: 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16',
136: 'TD_PERF_SEL_burst_bin_sampler_1',
137: 'TD_PERF_SEL_burst_bin_sampler_2to8',
138: 'TD_PERF_SEL_burst_bin_sampler_9to16',
139: 'TD_PERF_SEL_burst_bin_sampler_gt16',
140: 'TD_PERF_SEL_burst_bin_gather_1',
141: 'TD_PERF_SEL_burst_bin_gather_2to8',
142: 'TD_PERF_SEL_burst_bin_gather_9to16',
143: 'TD_PERF_SEL_burst_bin_gather_gt16',
144: 'TD_PERF_SEL_burst_bin_nofilter_1',
145: 'TD_PERF_SEL_burst_bin_nofilter_2to4',
146: 'TD_PERF_SEL_burst_bin_nofilter_5to7',
147: 'TD_PERF_SEL_burst_bin_nofilter_8to16',
148: 'TD_PERF_SEL_burst_bin_nofilter_gt16',
149: 'TD_PERF_SEL_burst_bin_bvh4_1',
150: 'TD_PERF_SEL_burst_bin_bvh4_2to8',
151: 'TD_PERF_SEL_burst_bin_bvh4_9to16',
152: 'TD_PERF_SEL_burst_bin_bvh4_gt16',
153: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_1',
154: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4',
155: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7',
156: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16',
157: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16',
158: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1',
159: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8',
160: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16',
161: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16',
162: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1',
163: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8',
164: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16',
165: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16',
166: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1',
167: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8',
168: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16',
169: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16',
170: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0',
171: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1',
172: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31',
173: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127',
174: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511',
175: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511',
176: 'TD_PERF_SEL_bubble_bin_lds_stall_1to3',
177: 'TD_PERF_SEL_bubble_bin_lds_stall_4to7',
178: 'TD_PERF_SEL_bubble_bin_lds_stall_8to15',
179: 'TD_PERF_SEL_bubble_bin_lds_stall_gt15',
180: 'TD_PERF_SEL_preempting_nofilter_max_cnt',
181: 'TD_PERF_SEL_sampler_lerp0_active',
182: 'TD_PERF_SEL_sampler_lerp1_active',
183: 'TD_PERF_SEL_sampler_lerp2_active',
184: 'TD_PERF_SEL_sampler_lerp3_active',
185: 'TD_PERF_SEL_nofilter_total_num_comps_to_lds',
186: 'TD_PERF_SEL_nofilter_byte_cycling_4cycles',
187: 'TD_PERF_SEL_nofilter_byte_cycling_8cycles',
188: 'TD_PERF_SEL_nofilter_byte_cycling_16cycles',
189: 'TD_PERF_SEL_nofilter_dword_cycling_2cycles',
190: 'TD_PERF_SEL_nofilter_dword_cycling_4cycles',
191: 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full',
192: 'TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt',
}
TD_PERF_SEL_none = 0
TD_PERF_SEL_td_busy = 1
TD_PERF_SEL_input_busy = 2
TD_PERF_SEL_sampler_lerp_busy = 3
TD_PERF_SEL_sampler_out_busy = 4
TD_PERF_SEL_nofilter_busy = 5
TD_PERF_SEL_ray_tracing_bvh4_busy = 6
TD_PERF_SEL_sampler_core_sclk_en = 7
TD_PERF_SEL_sampler_preformatter_sclk_en = 8
TD_PERF_SEL_sampler_bilerp_sclk_en = 9
TD_PERF_SEL_sampler_bypass_sclk_en = 10
TD_PERF_SEL_sampler_minmax_sclk_en = 11
TD_PERF_SEL_sampler_accum_sclk_en = 12
TD_PERF_SEL_sampler_format_flt_sclk_en = 13
TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 14
TD_PERF_SEL_sampler_out_sclk_en = 15
TD_PERF_SEL_nofilter_sclk_en = 16
TD_PERF_SEL_nofilter_d32_sclk_en = 17
TD_PERF_SEL_nofilter_d16_sclk_en = 18
TD_PERF_SEL_ray_tracing_bvh4_sclk_en = 22
TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en = 23
TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en = 24
TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en = 25
TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 26
TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 27
TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 28
TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off = 29
TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off = 30
TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off = 31
TD_PERF_SEL_core_state_ram_max_cnt = 32
TD_PERF_SEL_core_state_rams_read = 33
TD_PERF_SEL_weight_data_rams_read = 34
TD_PERF_SEL_reference_data_rams_read = 35
TD_PERF_SEL_tc_td_ram_fifo_full = 36
TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 37
TD_PERF_SEL_tc_td_data_fifo_full = 38
TD_PERF_SEL_input_state_fifo_full = 39
TD_PERF_SEL_ta_data_stall = 40
TD_PERF_SEL_tc_data_stall = 41
TD_PERF_SEL_tc_ram_stall = 42
TD_PERF_SEL_lds_stall = 43
TD_PERF_SEL_sampler_pkr_full = 44
TD_PERF_SEL_sampler_pkr_full_due_to_arb = 45
TD_PERF_SEL_nofilter_pkr_full = 46
TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 47
TD_PERF_SEL_ray_tracing_bvh4_pkr_full = 48
TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb = 49
TD_PERF_SEL_gather4_instr = 50
TD_PERF_SEL_gather4h_instr = 51
TD_PERF_SEL_sample_instr = 54
TD_PERF_SEL_sample_c_instr = 55
TD_PERF_SEL_load_instr = 56
TD_PERF_SEL_ldfptr_instr = 57
TD_PERF_SEL_write_ack_instr = 58
TD_PERF_SEL_d16_en_instr = 59
TD_PERF_SEL_bypassLerp_instr = 60
TD_PERF_SEL_min_max_filter_instr = 61
TD_PERF_SEL_one_comp_return_instr = 62
TD_PERF_SEL_two_comp_return_instr = 63
TD_PERF_SEL_three_comp_return_instr = 64
TD_PERF_SEL_four_comp_return_instr = 65
TD_PERF_SEL_user_defined_border = 66
TD_PERF_SEL_white_border = 67
TD_PERF_SEL_opaque_black_border = 68
TD_PERF_SEL_lod_warn_from_ta = 69
TD_PERF_SEL_instruction_dest_is_lds = 70
TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 71
TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 72
TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 73
TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 74
TD_PERF_SEL_out_of_order_instr = 75
TD_PERF_SEL_total_num_instr = 76
TD_PERF_SEL_total_num_instr_with_perf_wdw = 77
TD_PERF_SEL_total_num_sampler_instr = 78
TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 79
TD_PERF_SEL_total_num_nofilter_instr = 80
TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 81
TD_PERF_SEL_total_num_ray_tracing_bvh4_instr = 82
TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw = 83
TD_PERF_SEL_mixmode_instr = 84
TD_PERF_SEL_mixmode_resource = 85
TD_PERF_SEL_status_packet = 86
TD_PERF_SEL_address_cmd_poison = 87
TD_PERF_SEL_data_poison = 88
TD_PERF_SEL_done_scoreboard_max_stored_cnt = 89
TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 90
TD_PERF_SEL_done_scoreboard_not_empty = 91
TD_PERF_SEL_done_scoreboard_is_full = 92
TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 93
TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 94
TD_PERF_SEL_nofilter_formatters_turned_on = 95
TD_PERF_SEL_nofilter_insert_extra_comps = 96
TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 97
TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 98
TD_PERF_SEL_msaa_load_instr = 99
TD_PERF_SEL_blend_prt_with_prt_default_0 = 100
TD_PERF_SEL_blend_prt_with_prt_default_1 = 101
TD_PERF_SEL_resmap_instr = 102
TD_PERF_SEL_prt_ack_instr = 103
TD_PERF_SEL_resmap_with_volume_filtering = 104
TD_PERF_SEL_resmap_with_aniso_filtering = 105
TD_PERF_SEL_resmap_with_no_more_filtering = 106
TD_PERF_SEL_resmap_with_cubemap_corner = 107
TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0 = 108
TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1 = 109
TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2 = 110
TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4 = 111
TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8 = 112
TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16 = 113
TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31 = 114
TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32 = 115
TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node = 116
TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node = 117
TD_PERF_SEL_ray_tracing_bvh4_tri_node = 118
TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node = 119
TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node = 120
TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node = 121
TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node = 122
TD_PERF_SEL_ray_tracing_bvh4_box_sort_en = 123
TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero = 124
TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx = 125
TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx = 126
TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan = 127
TD_PERF_SEL_ray_tracing_bvh4_num_box_misses = 128
TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses = 129
TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers = 130
TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 131
TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 132
TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 133
TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 134
TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 135
TD_PERF_SEL_burst_bin_sampler_1 = 136
TD_PERF_SEL_burst_bin_sampler_2to8 = 137
TD_PERF_SEL_burst_bin_sampler_9to16 = 138
TD_PERF_SEL_burst_bin_sampler_gt16 = 139
TD_PERF_SEL_burst_bin_gather_1 = 140
TD_PERF_SEL_burst_bin_gather_2to8 = 141
TD_PERF_SEL_burst_bin_gather_9to16 = 142
TD_PERF_SEL_burst_bin_gather_gt16 = 143
TD_PERF_SEL_burst_bin_nofilter_1 = 144
TD_PERF_SEL_burst_bin_nofilter_2to4 = 145
TD_PERF_SEL_burst_bin_nofilter_5to7 = 146
TD_PERF_SEL_burst_bin_nofilter_8to16 = 147
TD_PERF_SEL_burst_bin_nofilter_gt16 = 148
TD_PERF_SEL_burst_bin_bvh4_1 = 149
TD_PERF_SEL_burst_bin_bvh4_2to8 = 150
TD_PERF_SEL_burst_bin_bvh4_9to16 = 151
TD_PERF_SEL_burst_bin_bvh4_gt16 = 152
TD_PERF_SEL_burst_bin_bvh4_box_nodes_1 = 153
TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4 = 154
TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7 = 155
TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16 = 156
TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16 = 157
TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1 = 158
TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8 = 159
TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16 = 160
TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16 = 161
TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1 = 162
TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8 = 163
TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16 = 164
TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16 = 165
TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1 = 166
TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8 = 167
TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16 = 168
TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16 = 169
TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 170
TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 171
TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 172
TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 173
TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 174
TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 175
TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 176
TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 177
TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 178
TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 179
TD_PERF_SEL_preempting_nofilter_max_cnt = 180
TD_PERF_SEL_sampler_lerp0_active = 181
TD_PERF_SEL_sampler_lerp1_active = 182
TD_PERF_SEL_sampler_lerp2_active = 183
TD_PERF_SEL_sampler_lerp3_active = 184
TD_PERF_SEL_nofilter_total_num_comps_to_lds = 185
TD_PERF_SEL_nofilter_byte_cycling_4cycles = 186
TD_PERF_SEL_nofilter_byte_cycling_8cycles = 187
TD_PERF_SEL_nofilter_byte_cycling_16cycles = 188
TD_PERF_SEL_nofilter_dword_cycling_2cycles = 189
TD_PERF_SEL_nofilter_dword_cycling_4cycles = 190
TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 191
TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt = 192
TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL2A_PERF_SEL'
GL2A_PERF_SEL__enumvalues = {
0: 'GL2A_PERF_SEL_NONE',
1: 'GL2A_PERF_SEL_CYCLE',
2: 'GL2A_PERF_SEL_BUSY',
3: 'GL2A_PERF_SEL_REQ_GL2C0',
4: 'GL2A_PERF_SEL_REQ_GL2C1',
5: 'GL2A_PERF_SEL_REQ_GL2C2',
6: 'GL2A_PERF_SEL_REQ_GL2C3',
7: 'GL2A_PERF_SEL_REQ_GL2C4',
8: 'GL2A_PERF_SEL_REQ_GL2C5',
9: 'GL2A_PERF_SEL_REQ_GL2C6',
10: 'GL2A_PERF_SEL_REQ_GL2C7',
11: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0',
12: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1',
13: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2',
14: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3',
15: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4',
16: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5',
17: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6',
18: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7',
19: 'GL2A_PERF_SEL_REQ_BURST_GL2C0',
20: 'GL2A_PERF_SEL_REQ_BURST_GL2C1',
21: 'GL2A_PERF_SEL_REQ_BURST_GL2C2',
22: 'GL2A_PERF_SEL_REQ_BURST_GL2C3',
23: 'GL2A_PERF_SEL_REQ_BURST_GL2C4',
24: 'GL2A_PERF_SEL_REQ_BURST_GL2C5',
25: 'GL2A_PERF_SEL_REQ_BURST_GL2C6',
26: 'GL2A_PERF_SEL_REQ_BURST_GL2C7',
27: 'GL2A_PERF_SEL_REQ_STALL_GL2C0',
28: 'GL2A_PERF_SEL_REQ_STALL_GL2C1',
29: 'GL2A_PERF_SEL_REQ_STALL_GL2C2',
30: 'GL2A_PERF_SEL_REQ_STALL_GL2C3',
31: 'GL2A_PERF_SEL_REQ_STALL_GL2C4',
32: 'GL2A_PERF_SEL_REQ_STALL_GL2C5',
33: 'GL2A_PERF_SEL_REQ_STALL_GL2C6',
34: 'GL2A_PERF_SEL_REQ_STALL_GL2C7',
35: 'GL2A_PERF_SEL_RTN_STALL_GL2C0',
36: 'GL2A_PERF_SEL_RTN_STALL_GL2C1',
37: 'GL2A_PERF_SEL_RTN_STALL_GL2C2',
38: 'GL2A_PERF_SEL_RTN_STALL_GL2C3',
39: 'GL2A_PERF_SEL_RTN_STALL_GL2C4',
40: 'GL2A_PERF_SEL_RTN_STALL_GL2C5',
41: 'GL2A_PERF_SEL_RTN_STALL_GL2C6',
42: 'GL2A_PERF_SEL_RTN_STALL_GL2C7',
43: 'GL2A_PERF_SEL_RTN_CLIENT0',
44: 'GL2A_PERF_SEL_RTN_CLIENT1',
45: 'GL2A_PERF_SEL_RTN_CLIENT2',
46: 'GL2A_PERF_SEL_RTN_CLIENT3',
47: 'GL2A_PERF_SEL_RTN_CLIENT4',
48: 'GL2A_PERF_SEL_RTN_CLIENT5',
49: 'GL2A_PERF_SEL_RTN_CLIENT6',
50: 'GL2A_PERF_SEL_RTN_CLIENT7',
51: 'GL2A_PERF_SEL_RTN_CLIENT8',
52: 'GL2A_PERF_SEL_RTN_CLIENT9',
53: 'GL2A_PERF_SEL_RTN_CLIENT10',
54: 'GL2A_PERF_SEL_RTN_CLIENT11',
55: 'GL2A_PERF_SEL_RTN_CLIENT12',
56: 'GL2A_PERF_SEL_RTN_CLIENT13',
57: 'GL2A_PERF_SEL_RTN_CLIENT14',
58: 'GL2A_PERF_SEL_RTN_CLIENT15',
59: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0',
60: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1',
61: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2',
62: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3',
63: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4',
64: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5',
65: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6',
66: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7',
67: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8',
68: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9',
69: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10',
70: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11',
71: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12',
72: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13',
73: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14',
74: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15',
75: 'GL2A_PERF_SEL_REQ_BURST_CLIENT0',
76: 'GL2A_PERF_SEL_REQ_BURST_CLIENT1',
77: 'GL2A_PERF_SEL_REQ_BURST_CLIENT2',
78: 'GL2A_PERF_SEL_REQ_BURST_CLIENT3',
79: 'GL2A_PERF_SEL_REQ_BURST_CLIENT4',
80: 'GL2A_PERF_SEL_REQ_BURST_CLIENT5',
81: 'GL2A_PERF_SEL_REQ_BURST_CLIENT6',
82: 'GL2A_PERF_SEL_REQ_BURST_CLIENT7',
83: 'GL2A_PERF_SEL_REQ_BURST_CLIENT8',
84: 'GL2A_PERF_SEL_REQ_BURST_CLIENT9',
85: 'GL2A_PERF_SEL_REQ_BURST_CLIENT10',
86: 'GL2A_PERF_SEL_REQ_BURST_CLIENT11',
87: 'GL2A_PERF_SEL_REQ_BURST_CLIENT12',
88: 'GL2A_PERF_SEL_REQ_BURST_CLIENT13',
89: 'GL2A_PERF_SEL_REQ_BURST_CLIENT14',
90: 'GL2A_PERF_SEL_REQ_BURST_CLIENT15',
91: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0',
92: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1',
93: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2',
94: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3',
95: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4',
96: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5',
97: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6',
98: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7',
99: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8',
100: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9',
101: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10',
103: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11',
104: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12',
105: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13',
106: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14',
107: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15',
}
GL2A_PERF_SEL_NONE = 0
GL2A_PERF_SEL_CYCLE = 1
GL2A_PERF_SEL_BUSY = 2
GL2A_PERF_SEL_REQ_GL2C0 = 3
GL2A_PERF_SEL_REQ_GL2C1 = 4
GL2A_PERF_SEL_REQ_GL2C2 = 5
GL2A_PERF_SEL_REQ_GL2C3 = 6
GL2A_PERF_SEL_REQ_GL2C4 = 7
GL2A_PERF_SEL_REQ_GL2C5 = 8
GL2A_PERF_SEL_REQ_GL2C6 = 9
GL2A_PERF_SEL_REQ_GL2C7 = 10
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 11
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 12
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 13
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 14
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 15
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 16
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 17
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 18
GL2A_PERF_SEL_REQ_BURST_GL2C0 = 19
GL2A_PERF_SEL_REQ_BURST_GL2C1 = 20
GL2A_PERF_SEL_REQ_BURST_GL2C2 = 21
GL2A_PERF_SEL_REQ_BURST_GL2C3 = 22
GL2A_PERF_SEL_REQ_BURST_GL2C4 = 23
GL2A_PERF_SEL_REQ_BURST_GL2C5 = 24
GL2A_PERF_SEL_REQ_BURST_GL2C6 = 25
GL2A_PERF_SEL_REQ_BURST_GL2C7 = 26
GL2A_PERF_SEL_REQ_STALL_GL2C0 = 27
GL2A_PERF_SEL_REQ_STALL_GL2C1 = 28
GL2A_PERF_SEL_REQ_STALL_GL2C2 = 29
GL2A_PERF_SEL_REQ_STALL_GL2C3 = 30
GL2A_PERF_SEL_REQ_STALL_GL2C4 = 31
GL2A_PERF_SEL_REQ_STALL_GL2C5 = 32
GL2A_PERF_SEL_REQ_STALL_GL2C6 = 33
GL2A_PERF_SEL_REQ_STALL_GL2C7 = 34
GL2A_PERF_SEL_RTN_STALL_GL2C0 = 35
GL2A_PERF_SEL_RTN_STALL_GL2C1 = 36
GL2A_PERF_SEL_RTN_STALL_GL2C2 = 37
GL2A_PERF_SEL_RTN_STALL_GL2C3 = 38
GL2A_PERF_SEL_RTN_STALL_GL2C4 = 39
GL2A_PERF_SEL_RTN_STALL_GL2C5 = 40
GL2A_PERF_SEL_RTN_STALL_GL2C6 = 41
GL2A_PERF_SEL_RTN_STALL_GL2C7 = 42
GL2A_PERF_SEL_RTN_CLIENT0 = 43
GL2A_PERF_SEL_RTN_CLIENT1 = 44
GL2A_PERF_SEL_RTN_CLIENT2 = 45
GL2A_PERF_SEL_RTN_CLIENT3 = 46
GL2A_PERF_SEL_RTN_CLIENT4 = 47
GL2A_PERF_SEL_RTN_CLIENT5 = 48
GL2A_PERF_SEL_RTN_CLIENT6 = 49
GL2A_PERF_SEL_RTN_CLIENT7 = 50
GL2A_PERF_SEL_RTN_CLIENT8 = 51
GL2A_PERF_SEL_RTN_CLIENT9 = 52
GL2A_PERF_SEL_RTN_CLIENT10 = 53
GL2A_PERF_SEL_RTN_CLIENT11 = 54
GL2A_PERF_SEL_RTN_CLIENT12 = 55
GL2A_PERF_SEL_RTN_CLIENT13 = 56
GL2A_PERF_SEL_RTN_CLIENT14 = 57
GL2A_PERF_SEL_RTN_CLIENT15 = 58
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 59
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 60
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 61
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 62
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 63
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 64
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 65
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 66
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 67
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 68
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 69
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 70
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 71
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 72
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 73
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 74
GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 75
GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 76
GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 77
GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 78
GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 79
GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 80
GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 81
GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 82
GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 83
GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 84
GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 85
GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 86
GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 87
GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 88
GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 89
GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 90
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 91
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 92
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 93
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 94
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 95
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 96
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 97
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 98
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 99
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 100
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 101
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 103
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 104
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 105
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 106
GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 107
GL2A_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GL2C_PERF_SEL'
GL2C_PERF_SEL__enumvalues = {
0: 'GL2C_PERF_SEL_NONE',
1: 'GL2C_PERF_SEL_CYCLE',
2: 'GL2C_PERF_SEL_BUSY',
3: 'GL2C_PERF_SEL_REQ',
4: 'GL2C_PERF_SEL_VOL_REQ',
5: 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ',
6: 'GL2C_PERF_SEL_READ',
7: 'GL2C_PERF_SEL_WRITE',
8: 'GL2C_PERF_SEL_ATOMIC',
9: 'GL2C_PERF_SEL_NOP_ACK',
10: 'GL2C_PERF_SEL_NOP_RTN0',
11: 'GL2C_PERF_SEL_PROBE',
12: 'GL2C_PERF_SEL_PROBE_ALL',
13: 'GL2C_PERF_SEL_INTERNAL_PROBE',
14: 'GL2C_PERF_SEL_COMPRESSED_READ_REQ',
15: 'GL2C_PERF_SEL_METADATA_READ_REQ',
16: 'GL2C_PERF_SEL_CLIENT0_REQ',
17: 'GL2C_PERF_SEL_CLIENT1_REQ',
18: 'GL2C_PERF_SEL_CLIENT2_REQ',
19: 'GL2C_PERF_SEL_CLIENT3_REQ',
20: 'GL2C_PERF_SEL_CLIENT4_REQ',
21: 'GL2C_PERF_SEL_CLIENT5_REQ',
22: 'GL2C_PERF_SEL_CLIENT6_REQ',
23: 'GL2C_PERF_SEL_CLIENT7_REQ',
24: 'GL2C_PERF_SEL_CLIENT8_REQ',
25: 'GL2C_PERF_SEL_CLIENT9_REQ',
26: 'GL2C_PERF_SEL_CLIENT10_REQ',
27: 'GL2C_PERF_SEL_CLIENT11_REQ',
28: 'GL2C_PERF_SEL_CLIENT12_REQ',
29: 'GL2C_PERF_SEL_CLIENT13_REQ',
30: 'GL2C_PERF_SEL_CLIENT14_REQ',
31: 'GL2C_PERF_SEL_CLIENT15_REQ',
32: 'GL2C_PERF_SEL_C_RW_S_REQ',
33: 'GL2C_PERF_SEL_C_RW_US_REQ',
34: 'GL2C_PERF_SEL_C_RO_S_REQ',
35: 'GL2C_PERF_SEL_C_RO_US_REQ',
36: 'GL2C_PERF_SEL_UC_REQ',
37: 'GL2C_PERF_SEL_LRU_REQ',
38: 'GL2C_PERF_SEL_STREAM_REQ',
39: 'GL2C_PERF_SEL_BYPASS_REQ',
40: 'GL2C_PERF_SEL_NOA_REQ',
41: 'GL2C_PERF_SEL_SHARED_REQ',
42: 'GL2C_PERF_SEL_HIT',
43: 'GL2C_PERF_SEL_MISS',
44: 'GL2C_PERF_SEL_FULL_HIT',
45: 'GL2C_PERF_SEL_PARTIAL_32B_HIT',
46: 'GL2C_PERF_SEL_PARTIAL_64B_HIT',
47: 'GL2C_PERF_SEL_PARTIAL_96B_HIT',
48: 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT',
49: 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT',
50: 'GL2C_PERF_SEL_UNCACHED_WRITE',
51: 'GL2C_PERF_SEL_WRITEBACK',
52: 'GL2C_PERF_SEL_NORMAL_WRITEBACK',
53: 'GL2C_PERF_SEL_EVICT',
54: 'GL2C_PERF_SEL_NORMAL_EVICT',
55: 'GL2C_PERF_SEL_PROBE_EVICT',
56: 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE',
57: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0',
58: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1',
59: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2',
60: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3',
61: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4',
62: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5',
63: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6',
64: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7',
65: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8',
66: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9',
67: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10',
68: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11',
69: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12',
70: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13',
71: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14',
72: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15',
73: 'GL2C_PERF_SEL_READ_32_REQ',
74: 'GL2C_PERF_SEL_READ_64_REQ',
75: 'GL2C_PERF_SEL_READ_128_REQ',
76: 'GL2C_PERF_SEL_WRITE_32_REQ',
77: 'GL2C_PERF_SEL_WRITE_64_REQ',
78: 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ',
79: 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ',
80: 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ',
81: 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ',
82: 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ',
83: 'GL2C_PERF_SEL_MC_WRREQ',
84: 'GL2C_PERF_SEL_EA_WRREQ_SNOOP',
85: 'GL2C_PERF_SEL_EA_WRREQ_64B',
86: 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND',
87: 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B',
88: 'GL2C_PERF_SEL_MC_WRREQ_STALL',
89: 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL',
90: 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL',
91: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL',
92: 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL',
93: 'GL2C_PERF_SEL_MC_WRREQ_LEVEL',
94: 'GL2C_PERF_SEL_EA_ATOMIC',
95: 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL',
96: 'GL2C_PERF_SEL_MC_RDREQ',
97: 'GL2C_PERF_SEL_EA_RDREQ_SNOOP',
98: 'GL2C_PERF_SEL_EA_RDREQ_SPLIT',
99: 'GL2C_PERF_SEL_EA_RDREQ_32B',
100: 'GL2C_PERF_SEL_EA_RDREQ_64B',
101: 'GL2C_PERF_SEL_EA_RDREQ_96B',
102: 'GL2C_PERF_SEL_EA_RDREQ_128B',
103: 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B',
104: 'GL2C_PERF_SEL_EA_RD_MDC_32B',
105: 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B',
106: 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL',
107: 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL',
108: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL',
109: 'GL2C_PERF_SEL_MC_RDREQ_LEVEL',
110: 'GL2C_PERF_SEL_EA_RDREQ_DRAM',
111: 'GL2C_PERF_SEL_EA_WRREQ_DRAM',
112: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B',
113: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B',
114: 'GL2C_PERF_SEL_ONION_READ',
115: 'GL2C_PERF_SEL_ONION_WRITE',
116: 'GL2C_PERF_SEL_IO_READ',
117: 'GL2C_PERF_SEL_IO_WRITE',
118: 'GL2C_PERF_SEL_GARLIC_READ',
119: 'GL2C_PERF_SEL_GARLIC_WRITE',
120: 'GL2C_PERF_SEL_EA_OUTSTANDING',
121: 'GL2C_PERF_SEL_LATENCY_FIFO_FULL',
122: 'GL2C_PERF_SEL_SRC_FIFO_FULL',
123: 'GL2C_PERF_SEL_TAG_STALL',
124: 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL',
125: 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL',
126: 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL',
127: 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL',
128: 'GL2C_PERF_SEL_TAG_PROBE_STALL',
129: 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL',
130: 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL',
131: 'GL2C_PERF_SEL_TAG_READ_DST_STALL',
132: 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT',
133: 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT',
134: 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE',
135: 'GL2C_PERF_SEL_BUBBLE',
136: 'GL2C_PERF_SEL_IB_REQ',
137: 'GL2C_PERF_SEL_IB_STALL',
138: 'GL2C_PERF_SEL_IB_TAG_STALL',
139: 'GL2C_PERF_SEL_IB_CM_STALL',
140: 'GL2C_PERF_SEL_RETURN_ACK',
141: 'GL2C_PERF_SEL_RETURN_DATA',
142: 'GL2C_PERF_SEL_EA_RDRET_NACK',
143: 'GL2C_PERF_SEL_EA_WRRET_NACK',
144: 'GL2C_PERF_SEL_GL2A_LEVEL',
145: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION',
146: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED',
147: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START',
148: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START',
149: 'GL2C_PERF_SEL_GCR_INV',
150: 'GL2C_PERF_SEL_GCR_WB',
151: 'GL2C_PERF_SEL_GCR_DISCARD',
152: 'GL2C_PERF_SEL_GCR_RANGE',
153: 'GL2C_PERF_SEL_GCR_ALL',
154: 'GL2C_PERF_SEL_GCR_VOL',
155: 'GL2C_PERF_SEL_GCR_UNSHARED',
156: 'GL2C_PERF_SEL_GCR_MDC_INV',
157: 'GL2C_PERF_SEL_GCR_GL2_INV_ALL',
158: 'GL2C_PERF_SEL_GCR_GL2_WB_ALL',
159: 'GL2C_PERF_SEL_GCR_MDC_INV_ALL',
160: 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE',
161: 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE',
162: 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE',
163: 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE',
164: 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT',
165: 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT',
166: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE',
167: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE',
168: 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK',
169: 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE',
170: 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT',
171: 'GL2C_PERF_SEL_GCR_INVL2_VOL_START',
172: 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE',
173: 'GL2C_PERF_SEL_GCR_WBL2_VOL_START',
174: 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE',
175: 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT',
176: 'GL2C_PERF_SEL_GCR_WBINVL2_START',
177: 'GL2C_PERF_SEL_MDC_INV_METADATA',
178: 'GL2C_PERF_SEL_MDC_REQ',
179: 'GL2C_PERF_SEL_MDC_LEVEL',
180: 'GL2C_PERF_SEL_MDC_TAG_HIT',
181: 'GL2C_PERF_SEL_MDC_SECTOR_HIT',
182: 'GL2C_PERF_SEL_MDC_SECTOR_MISS',
183: 'GL2C_PERF_SEL_MDC_TAG_STALL',
184: 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL',
185: 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL',
186: 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL',
187: 'GL2C_PERF_SEL_CM_CHANNEL0_REQ',
188: 'GL2C_PERF_SEL_CM_CHANNEL1_REQ',
189: 'GL2C_PERF_SEL_CM_CHANNEL2_REQ',
190: 'GL2C_PERF_SEL_CM_CHANNEL3_REQ',
191: 'GL2C_PERF_SEL_CM_CHANNEL4_REQ',
192: 'GL2C_PERF_SEL_CM_CHANNEL5_REQ',
193: 'GL2C_PERF_SEL_CM_CHANNEL6_REQ',
194: 'GL2C_PERF_SEL_CM_CHANNEL7_REQ',
195: 'GL2C_PERF_SEL_CM_CHANNEL8_REQ',
196: 'GL2C_PERF_SEL_CM_CHANNEL9_REQ',
197: 'GL2C_PERF_SEL_CM_CHANNEL10_REQ',
198: 'GL2C_PERF_SEL_CM_CHANNEL11_REQ',
199: 'GL2C_PERF_SEL_CM_CHANNEL12_REQ',
200: 'GL2C_PERF_SEL_CM_CHANNEL13_REQ',
201: 'GL2C_PERF_SEL_CM_CHANNEL14_REQ',
202: 'GL2C_PERF_SEL_CM_CHANNEL15_REQ',
203: 'GL2C_PERF_SEL_CM_CHANNEL16_REQ',
204: 'GL2C_PERF_SEL_CM_CHANNEL17_REQ',
205: 'GL2C_PERF_SEL_CM_CHANNEL18_REQ',
206: 'GL2C_PERF_SEL_CM_CHANNEL19_REQ',
207: 'GL2C_PERF_SEL_CM_CHANNEL20_REQ',
208: 'GL2C_PERF_SEL_CM_CHANNEL21_REQ',
209: 'GL2C_PERF_SEL_CM_CHANNEL22_REQ',
210: 'GL2C_PERF_SEL_CM_CHANNEL23_REQ',
211: 'GL2C_PERF_SEL_CM_CHANNEL24_REQ',
212: 'GL2C_PERF_SEL_CM_CHANNEL25_REQ',
213: 'GL2C_PERF_SEL_CM_CHANNEL26_REQ',
214: 'GL2C_PERF_SEL_CM_CHANNEL27_REQ',
215: 'GL2C_PERF_SEL_CM_CHANNEL28_REQ',
216: 'GL2C_PERF_SEL_CM_CHANNEL29_REQ',
217: 'GL2C_PERF_SEL_CM_CHANNEL30_REQ',
218: 'GL2C_PERF_SEL_CM_CHANNEL31_REQ',
219: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ',
220: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ',
221: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ',
222: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ',
223: 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ',
224: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ',
225: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ',
226: 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ',
227: 'GL2C_PERF_SEL_CM_COMP_READ_REQ',
228: 'GL2C_PERF_SEL_CM_READ_BACK_REQ',
229: 'GL2C_PERF_SEL_CM_METADATA_WR_REQ',
230: 'GL2C_PERF_SEL_CM_WR_ACK_REQ',
231: 'GL2C_PERF_SEL_CM_NO_ACK_REQ',
232: 'GL2C_PERF_SEL_CM_NOOP_REQ',
233: 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ',
234: 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ',
235: 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ',
236: 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ',
237: 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ',
238: 'GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ',
239: 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ',
240: 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ',
241: 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ',
242: 'GL2C_PERF_SEL_CM_RVF_FULL',
243: 'GL2C_PERF_SEL_CM_SDR_FULL',
244: 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL',
245: 'GL2C_PERF_SEL_CM_DCC_STALL',
246: 'GL2C_PERF_SEL_CM_DCC_IN_XFC',
247: 'GL2C_PERF_SEL_CM_DCC_OUT_XFC',
248: 'GL2C_PERF_SEL_CM_DCC_OUT_1x1',
249: 'GL2C_PERF_SEL_CM_DCC_OUT_1x2',
250: 'GL2C_PERF_SEL_CM_DCC_OUT_2x1',
251: 'GL2C_PERF_SEL_CM_DCC_OUT_2x2',
252: 'GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP',
253: 'GL2C_PERF_SEL_CM_DCC_OUT_CONST',
254: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16',
255: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17',
256: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18',
257: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19',
}
GL2C_PERF_SEL_NONE = 0
GL2C_PERF_SEL_CYCLE = 1
GL2C_PERF_SEL_BUSY = 2
GL2C_PERF_SEL_REQ = 3
GL2C_PERF_SEL_VOL_REQ = 4
GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 5
GL2C_PERF_SEL_READ = 6
GL2C_PERF_SEL_WRITE = 7
GL2C_PERF_SEL_ATOMIC = 8
GL2C_PERF_SEL_NOP_ACK = 9
GL2C_PERF_SEL_NOP_RTN0 = 10
GL2C_PERF_SEL_PROBE = 11
GL2C_PERF_SEL_PROBE_ALL = 12
GL2C_PERF_SEL_INTERNAL_PROBE = 13
GL2C_PERF_SEL_COMPRESSED_READ_REQ = 14
GL2C_PERF_SEL_METADATA_READ_REQ = 15
GL2C_PERF_SEL_CLIENT0_REQ = 16
GL2C_PERF_SEL_CLIENT1_REQ = 17
GL2C_PERF_SEL_CLIENT2_REQ = 18
GL2C_PERF_SEL_CLIENT3_REQ = 19
GL2C_PERF_SEL_CLIENT4_REQ = 20
GL2C_PERF_SEL_CLIENT5_REQ = 21
GL2C_PERF_SEL_CLIENT6_REQ = 22
GL2C_PERF_SEL_CLIENT7_REQ = 23
GL2C_PERF_SEL_CLIENT8_REQ = 24
GL2C_PERF_SEL_CLIENT9_REQ = 25
GL2C_PERF_SEL_CLIENT10_REQ = 26
GL2C_PERF_SEL_CLIENT11_REQ = 27
GL2C_PERF_SEL_CLIENT12_REQ = 28
GL2C_PERF_SEL_CLIENT13_REQ = 29
GL2C_PERF_SEL_CLIENT14_REQ = 30
GL2C_PERF_SEL_CLIENT15_REQ = 31
GL2C_PERF_SEL_C_RW_S_REQ = 32
GL2C_PERF_SEL_C_RW_US_REQ = 33
GL2C_PERF_SEL_C_RO_S_REQ = 34
GL2C_PERF_SEL_C_RO_US_REQ = 35
GL2C_PERF_SEL_UC_REQ = 36
GL2C_PERF_SEL_LRU_REQ = 37
GL2C_PERF_SEL_STREAM_REQ = 38
GL2C_PERF_SEL_BYPASS_REQ = 39
GL2C_PERF_SEL_NOA_REQ = 40
GL2C_PERF_SEL_SHARED_REQ = 41
GL2C_PERF_SEL_HIT = 42
GL2C_PERF_SEL_MISS = 43
GL2C_PERF_SEL_FULL_HIT = 44
GL2C_PERF_SEL_PARTIAL_32B_HIT = 45
GL2C_PERF_SEL_PARTIAL_64B_HIT = 46
GL2C_PERF_SEL_PARTIAL_96B_HIT = 47
GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 48
GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 49
GL2C_PERF_SEL_UNCACHED_WRITE = 50
GL2C_PERF_SEL_WRITEBACK = 51
GL2C_PERF_SEL_NORMAL_WRITEBACK = 52
GL2C_PERF_SEL_EVICT = 53
GL2C_PERF_SEL_NORMAL_EVICT = 54
GL2C_PERF_SEL_PROBE_EVICT = 55
GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 56
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 57
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 58
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 59
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 60
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 61
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 62
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 63
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 64
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 65
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 66
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 67
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 68
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 69
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 70
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 71
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 72
GL2C_PERF_SEL_READ_32_REQ = 73
GL2C_PERF_SEL_READ_64_REQ = 74
GL2C_PERF_SEL_READ_128_REQ = 75
GL2C_PERF_SEL_WRITE_32_REQ = 76
GL2C_PERF_SEL_WRITE_64_REQ = 77
GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 78
GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 79
GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 80
GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 81
GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 82
GL2C_PERF_SEL_MC_WRREQ = 83
GL2C_PERF_SEL_EA_WRREQ_SNOOP = 84
GL2C_PERF_SEL_EA_WRREQ_64B = 85
GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 86
GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 87
GL2C_PERF_SEL_MC_WRREQ_STALL = 88
GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 89
GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 90
GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 91
GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 92
GL2C_PERF_SEL_MC_WRREQ_LEVEL = 93
GL2C_PERF_SEL_EA_ATOMIC = 94
GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 95
GL2C_PERF_SEL_MC_RDREQ = 96
GL2C_PERF_SEL_EA_RDREQ_SNOOP = 97
GL2C_PERF_SEL_EA_RDREQ_SPLIT = 98
GL2C_PERF_SEL_EA_RDREQ_32B = 99
GL2C_PERF_SEL_EA_RDREQ_64B = 100
GL2C_PERF_SEL_EA_RDREQ_96B = 101
GL2C_PERF_SEL_EA_RDREQ_128B = 102
GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 103
GL2C_PERF_SEL_EA_RD_MDC_32B = 104
GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 105
GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 106
GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 107
GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 108
GL2C_PERF_SEL_MC_RDREQ_LEVEL = 109
GL2C_PERF_SEL_EA_RDREQ_DRAM = 110
GL2C_PERF_SEL_EA_WRREQ_DRAM = 111
GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 112
GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 113
GL2C_PERF_SEL_ONION_READ = 114
GL2C_PERF_SEL_ONION_WRITE = 115
GL2C_PERF_SEL_IO_READ = 116
GL2C_PERF_SEL_IO_WRITE = 117
GL2C_PERF_SEL_GARLIC_READ = 118
GL2C_PERF_SEL_GARLIC_WRITE = 119
GL2C_PERF_SEL_EA_OUTSTANDING = 120
GL2C_PERF_SEL_LATENCY_FIFO_FULL = 121
GL2C_PERF_SEL_SRC_FIFO_FULL = 122
GL2C_PERF_SEL_TAG_STALL = 123
GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 124
GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 125
GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 126
GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 127
GL2C_PERF_SEL_TAG_PROBE_STALL = 128
GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 129
GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 130
GL2C_PERF_SEL_TAG_READ_DST_STALL = 131
GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 132
GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 133
GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 134
GL2C_PERF_SEL_BUBBLE = 135
GL2C_PERF_SEL_IB_REQ = 136
GL2C_PERF_SEL_IB_STALL = 137
GL2C_PERF_SEL_IB_TAG_STALL = 138
GL2C_PERF_SEL_IB_CM_STALL = 139
GL2C_PERF_SEL_RETURN_ACK = 140
GL2C_PERF_SEL_RETURN_DATA = 141
GL2C_PERF_SEL_EA_RDRET_NACK = 142
GL2C_PERF_SEL_EA_WRRET_NACK = 143
GL2C_PERF_SEL_GL2A_LEVEL = 144
GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 145
GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 146
GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 147
GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 148
GL2C_PERF_SEL_GCR_INV = 149
GL2C_PERF_SEL_GCR_WB = 150
GL2C_PERF_SEL_GCR_DISCARD = 151
GL2C_PERF_SEL_GCR_RANGE = 152
GL2C_PERF_SEL_GCR_ALL = 153
GL2C_PERF_SEL_GCR_VOL = 154
GL2C_PERF_SEL_GCR_UNSHARED = 155
GL2C_PERF_SEL_GCR_MDC_INV = 156
GL2C_PERF_SEL_GCR_GL2_INV_ALL = 157
GL2C_PERF_SEL_GCR_GL2_WB_ALL = 158
GL2C_PERF_SEL_GCR_MDC_INV_ALL = 159
GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 160
GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 161
GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 162
GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 163
GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 164
GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 165
GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 166
GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 167
GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 168
GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 169
GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 170
GL2C_PERF_SEL_GCR_INVL2_VOL_START = 171
GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 172
GL2C_PERF_SEL_GCR_WBL2_VOL_START = 173
GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 174
GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 175
GL2C_PERF_SEL_GCR_WBINVL2_START = 176
GL2C_PERF_SEL_MDC_INV_METADATA = 177
GL2C_PERF_SEL_MDC_REQ = 178
GL2C_PERF_SEL_MDC_LEVEL = 179
GL2C_PERF_SEL_MDC_TAG_HIT = 180
GL2C_PERF_SEL_MDC_SECTOR_HIT = 181
GL2C_PERF_SEL_MDC_SECTOR_MISS = 182
GL2C_PERF_SEL_MDC_TAG_STALL = 183
GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 184
GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 185
GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 186
GL2C_PERF_SEL_CM_CHANNEL0_REQ = 187
GL2C_PERF_SEL_CM_CHANNEL1_REQ = 188
GL2C_PERF_SEL_CM_CHANNEL2_REQ = 189
GL2C_PERF_SEL_CM_CHANNEL3_REQ = 190
GL2C_PERF_SEL_CM_CHANNEL4_REQ = 191
GL2C_PERF_SEL_CM_CHANNEL5_REQ = 192
GL2C_PERF_SEL_CM_CHANNEL6_REQ = 193
GL2C_PERF_SEL_CM_CHANNEL7_REQ = 194
GL2C_PERF_SEL_CM_CHANNEL8_REQ = 195
GL2C_PERF_SEL_CM_CHANNEL9_REQ = 196
GL2C_PERF_SEL_CM_CHANNEL10_REQ = 197
GL2C_PERF_SEL_CM_CHANNEL11_REQ = 198
GL2C_PERF_SEL_CM_CHANNEL12_REQ = 199
GL2C_PERF_SEL_CM_CHANNEL13_REQ = 200
GL2C_PERF_SEL_CM_CHANNEL14_REQ = 201
GL2C_PERF_SEL_CM_CHANNEL15_REQ = 202
GL2C_PERF_SEL_CM_CHANNEL16_REQ = 203
GL2C_PERF_SEL_CM_CHANNEL17_REQ = 204
GL2C_PERF_SEL_CM_CHANNEL18_REQ = 205
GL2C_PERF_SEL_CM_CHANNEL19_REQ = 206
GL2C_PERF_SEL_CM_CHANNEL20_REQ = 207
GL2C_PERF_SEL_CM_CHANNEL21_REQ = 208
GL2C_PERF_SEL_CM_CHANNEL22_REQ = 209
GL2C_PERF_SEL_CM_CHANNEL23_REQ = 210
GL2C_PERF_SEL_CM_CHANNEL24_REQ = 211
GL2C_PERF_SEL_CM_CHANNEL25_REQ = 212
GL2C_PERF_SEL_CM_CHANNEL26_REQ = 213
GL2C_PERF_SEL_CM_CHANNEL27_REQ = 214
GL2C_PERF_SEL_CM_CHANNEL28_REQ = 215
GL2C_PERF_SEL_CM_CHANNEL29_REQ = 216
GL2C_PERF_SEL_CM_CHANNEL30_REQ = 217
GL2C_PERF_SEL_CM_CHANNEL31_REQ = 218
GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 219
GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 220
GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 221
GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ = 222
GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 223
GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 224
GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 225
GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 226
GL2C_PERF_SEL_CM_COMP_READ_REQ = 227
GL2C_PERF_SEL_CM_READ_BACK_REQ = 228
GL2C_PERF_SEL_CM_METADATA_WR_REQ = 229
GL2C_PERF_SEL_CM_WR_ACK_REQ = 230
GL2C_PERF_SEL_CM_NO_ACK_REQ = 231
GL2C_PERF_SEL_CM_NOOP_REQ = 232
GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 233
GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 234
GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 235
GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 236
GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 237
GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ = 238
GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 239
GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 240
GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 241
GL2C_PERF_SEL_CM_RVF_FULL = 242
GL2C_PERF_SEL_CM_SDR_FULL = 243
GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 244
GL2C_PERF_SEL_CM_DCC_STALL = 245
GL2C_PERF_SEL_CM_DCC_IN_XFC = 246
GL2C_PERF_SEL_CM_DCC_OUT_XFC = 247
GL2C_PERF_SEL_CM_DCC_OUT_1x1 = 248
GL2C_PERF_SEL_CM_DCC_OUT_1x2 = 249
GL2C_PERF_SEL_CM_DCC_OUT_2x1 = 250
GL2C_PERF_SEL_CM_DCC_OUT_2x2 = 251
GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP = 252
GL2C_PERF_SEL_CM_DCC_OUT_CONST = 253
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 254
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 255
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 256
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 257
GL2C_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_PERF_SEL'
GRBM_PERF_SEL__enumvalues = {
0: 'GRBM_PERF_SEL_COUNT',
1: 'GRBM_PERF_SEL_USER_DEFINED',
2: 'GRBM_PERF_SEL_GUI_ACTIVE',
3: 'GRBM_PERF_SEL_CP_BUSY',
4: 'GRBM_PERF_SEL_CP_COHER_BUSY',
5: 'GRBM_PERF_SEL_CP_DMA_BUSY',
6: 'GRBM_PERF_SEL_CB_BUSY',
7: 'GRBM_PERF_SEL_DB_BUSY',
8: 'GRBM_PERF_SEL_PA_BUSY',
9: 'GRBM_PERF_SEL_SC_BUSY',
11: 'GRBM_PERF_SEL_SPI_BUSY',
12: 'GRBM_PERF_SEL_SX_BUSY',
13: 'GRBM_PERF_SEL_TA_BUSY',
14: 'GRBM_PERF_SEL_CB_CLEAN',
15: 'GRBM_PERF_SEL_DB_CLEAN',
25: 'GRBM_PERF_SEL_GDS_BUSY',
26: 'GRBM_PERF_SEL_BCI_BUSY',
27: 'GRBM_PERF_SEL_RLC_BUSY',
28: 'GRBM_PERF_SEL_TCP_BUSY',
29: 'GRBM_PERF_SEL_CPG_BUSY',
30: 'GRBM_PERF_SEL_CPC_BUSY',
31: 'GRBM_PERF_SEL_CPF_BUSY',
32: 'GRBM_PERF_SEL_GE_BUSY',
33: 'GRBM_PERF_SEL_GE_NO_DMA_BUSY',
34: 'GRBM_PERF_SEL_UTCL2_BUSY',
35: 'GRBM_PERF_SEL_EA_BUSY',
36: 'GRBM_PERF_SEL_RMI_BUSY',
37: 'GRBM_PERF_SEL_CPAXI_BUSY',
39: 'GRBM_PERF_SEL_UTCL1_BUSY',
40: 'GRBM_PERF_SEL_GL2CC_BUSY',
41: 'GRBM_PERF_SEL_SDMA_BUSY',
42: 'GRBM_PERF_SEL_CH_BUSY',
43: 'GRBM_PERF_SEL_PH_BUSY',
44: 'GRBM_PERF_SEL_PMM_BUSY',
45: 'GRBM_PERF_SEL_GUS_BUSY',
46: 'GRBM_PERF_SEL_GL1CC_BUSY',
47: 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY',
48: 'GRBM_PERF_SEL_GL1H_BUSY',
49: 'GRBM_PERF_SEL_PC_BUSY',
}
GRBM_PERF_SEL_COUNT = 0
GRBM_PERF_SEL_USER_DEFINED = 1
GRBM_PERF_SEL_GUI_ACTIVE = 2
GRBM_PERF_SEL_CP_BUSY = 3
GRBM_PERF_SEL_CP_COHER_BUSY = 4
GRBM_PERF_SEL_CP_DMA_BUSY = 5
GRBM_PERF_SEL_CB_BUSY = 6
GRBM_PERF_SEL_DB_BUSY = 7
GRBM_PERF_SEL_PA_BUSY = 8
GRBM_PERF_SEL_SC_BUSY = 9
GRBM_PERF_SEL_SPI_BUSY = 11
GRBM_PERF_SEL_SX_BUSY = 12
GRBM_PERF_SEL_TA_BUSY = 13
GRBM_PERF_SEL_CB_CLEAN = 14
GRBM_PERF_SEL_DB_CLEAN = 15
GRBM_PERF_SEL_GDS_BUSY = 25
GRBM_PERF_SEL_BCI_BUSY = 26
GRBM_PERF_SEL_RLC_BUSY = 27
GRBM_PERF_SEL_TCP_BUSY = 28
GRBM_PERF_SEL_CPG_BUSY = 29
GRBM_PERF_SEL_CPC_BUSY = 30
GRBM_PERF_SEL_CPF_BUSY = 31
GRBM_PERF_SEL_GE_BUSY = 32
GRBM_PERF_SEL_GE_NO_DMA_BUSY = 33
GRBM_PERF_SEL_UTCL2_BUSY = 34
GRBM_PERF_SEL_EA_BUSY = 35
GRBM_PERF_SEL_RMI_BUSY = 36
GRBM_PERF_SEL_CPAXI_BUSY = 37
GRBM_PERF_SEL_UTCL1_BUSY = 39
GRBM_PERF_SEL_GL2CC_BUSY = 40
GRBM_PERF_SEL_SDMA_BUSY = 41
GRBM_PERF_SEL_CH_BUSY = 42
GRBM_PERF_SEL_PH_BUSY = 43
GRBM_PERF_SEL_PMM_BUSY = 44
GRBM_PERF_SEL_GUS_BUSY = 45
GRBM_PERF_SEL_GL1CC_BUSY = 46
GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 47
GRBM_PERF_SEL_GL1H_BUSY = 48
GRBM_PERF_SEL_PC_BUSY = 49
GRBM_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_SE0_PERF_SEL'
GRBM_SE0_PERF_SEL__enumvalues = {
0: 'GRBM_SE0_PERF_SEL_COUNT',
1: 'GRBM_SE0_PERF_SEL_USER_DEFINED',
2: 'GRBM_SE0_PERF_SEL_CB_BUSY',
3: 'GRBM_SE0_PERF_SEL_DB_BUSY',
4: 'GRBM_SE0_PERF_SEL_SC_BUSY',
6: 'GRBM_SE0_PERF_SEL_SPI_BUSY',
7: 'GRBM_SE0_PERF_SEL_SX_BUSY',
8: 'GRBM_SE0_PERF_SEL_TA_BUSY',
9: 'GRBM_SE0_PERF_SEL_CB_CLEAN',
10: 'GRBM_SE0_PERF_SEL_DB_CLEAN',
12: 'GRBM_SE0_PERF_SEL_PA_BUSY',
14: 'GRBM_SE0_PERF_SEL_BCI_BUSY',
15: 'GRBM_SE0_PERF_SEL_RMI_BUSY',
16: 'GRBM_SE0_PERF_SEL_UTCL1_BUSY',
17: 'GRBM_SE0_PERF_SEL_TCP_BUSY',
18: 'GRBM_SE0_PERF_SEL_GL1CC_BUSY',
19: 'GRBM_SE0_PERF_SEL_GL1H_BUSY',
20: 'GRBM_SE0_PERF_SEL_PC_BUSY',
}
GRBM_SE0_PERF_SEL_COUNT = 0
GRBM_SE0_PERF_SEL_USER_DEFINED = 1
GRBM_SE0_PERF_SEL_CB_BUSY = 2
GRBM_SE0_PERF_SEL_DB_BUSY = 3
GRBM_SE0_PERF_SEL_SC_BUSY = 4
GRBM_SE0_PERF_SEL_SPI_BUSY = 6
GRBM_SE0_PERF_SEL_SX_BUSY = 7
GRBM_SE0_PERF_SEL_TA_BUSY = 8
GRBM_SE0_PERF_SEL_CB_CLEAN = 9
GRBM_SE0_PERF_SEL_DB_CLEAN = 10
GRBM_SE0_PERF_SEL_PA_BUSY = 12
GRBM_SE0_PERF_SEL_BCI_BUSY = 14
GRBM_SE0_PERF_SEL_RMI_BUSY = 15
GRBM_SE0_PERF_SEL_UTCL1_BUSY = 16
GRBM_SE0_PERF_SEL_TCP_BUSY = 17
GRBM_SE0_PERF_SEL_GL1CC_BUSY = 18
GRBM_SE0_PERF_SEL_GL1H_BUSY = 19
GRBM_SE0_PERF_SEL_PC_BUSY = 20
GRBM_SE0_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_SE1_PERF_SEL'
GRBM_SE1_PERF_SEL__enumvalues = {
0: 'GRBM_SE1_PERF_SEL_COUNT',
1: 'GRBM_SE1_PERF_SEL_USER_DEFINED',
2: 'GRBM_SE1_PERF_SEL_CB_BUSY',
3: 'GRBM_SE1_PERF_SEL_DB_BUSY',
4: 'GRBM_SE1_PERF_SEL_SC_BUSY',
6: 'GRBM_SE1_PERF_SEL_SPI_BUSY',
7: 'GRBM_SE1_PERF_SEL_SX_BUSY',
8: 'GRBM_SE1_PERF_SEL_TA_BUSY',
9: 'GRBM_SE1_PERF_SEL_CB_CLEAN',
10: 'GRBM_SE1_PERF_SEL_DB_CLEAN',
12: 'GRBM_SE1_PERF_SEL_PA_BUSY',
14: 'GRBM_SE1_PERF_SEL_BCI_BUSY',
15: 'GRBM_SE1_PERF_SEL_RMI_BUSY',
16: 'GRBM_SE1_PERF_SEL_UTCL1_BUSY',
17: 'GRBM_SE1_PERF_SEL_TCP_BUSY',
18: 'GRBM_SE1_PERF_SEL_GL1CC_BUSY',
19: 'GRBM_SE1_PERF_SEL_GL1H_BUSY',
20: 'GRBM_SE1_PERF_SEL_PC_BUSY',
}
GRBM_SE1_PERF_SEL_COUNT = 0
GRBM_SE1_PERF_SEL_USER_DEFINED = 1
GRBM_SE1_PERF_SEL_CB_BUSY = 2
GRBM_SE1_PERF_SEL_DB_BUSY = 3
GRBM_SE1_PERF_SEL_SC_BUSY = 4
GRBM_SE1_PERF_SEL_SPI_BUSY = 6
GRBM_SE1_PERF_SEL_SX_BUSY = 7
GRBM_SE1_PERF_SEL_TA_BUSY = 8
GRBM_SE1_PERF_SEL_CB_CLEAN = 9
GRBM_SE1_PERF_SEL_DB_CLEAN = 10
GRBM_SE1_PERF_SEL_PA_BUSY = 12
GRBM_SE1_PERF_SEL_BCI_BUSY = 14
GRBM_SE1_PERF_SEL_RMI_BUSY = 15
GRBM_SE1_PERF_SEL_UTCL1_BUSY = 16
GRBM_SE1_PERF_SEL_TCP_BUSY = 17
GRBM_SE1_PERF_SEL_GL1CC_BUSY = 18
GRBM_SE1_PERF_SEL_GL1H_BUSY = 19
GRBM_SE1_PERF_SEL_PC_BUSY = 20
GRBM_SE1_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_SE2_PERF_SEL'
GRBM_SE2_PERF_SEL__enumvalues = {
0: 'GRBM_SE2_PERF_SEL_COUNT',
1: 'GRBM_SE2_PERF_SEL_USER_DEFINED',
2: 'GRBM_SE2_PERF_SEL_CB_BUSY',
3: 'GRBM_SE2_PERF_SEL_DB_BUSY',
4: 'GRBM_SE2_PERF_SEL_SC_BUSY',
6: 'GRBM_SE2_PERF_SEL_SPI_BUSY',
7: 'GRBM_SE2_PERF_SEL_SX_BUSY',
8: 'GRBM_SE2_PERF_SEL_TA_BUSY',
9: 'GRBM_SE2_PERF_SEL_CB_CLEAN',
10: 'GRBM_SE2_PERF_SEL_DB_CLEAN',
12: 'GRBM_SE2_PERF_SEL_PA_BUSY',
14: 'GRBM_SE2_PERF_SEL_BCI_BUSY',
15: 'GRBM_SE2_PERF_SEL_RMI_BUSY',
16: 'GRBM_SE2_PERF_SEL_UTCL1_BUSY',
17: 'GRBM_SE2_PERF_SEL_TCP_BUSY',
18: 'GRBM_SE2_PERF_SEL_GL1CC_BUSY',
19: 'GRBM_SE2_PERF_SEL_GL1H_BUSY',
20: 'GRBM_SE2_PERF_SEL_PC_BUSY',
}
GRBM_SE2_PERF_SEL_COUNT = 0
GRBM_SE2_PERF_SEL_USER_DEFINED = 1
GRBM_SE2_PERF_SEL_CB_BUSY = 2
GRBM_SE2_PERF_SEL_DB_BUSY = 3
GRBM_SE2_PERF_SEL_SC_BUSY = 4
GRBM_SE2_PERF_SEL_SPI_BUSY = 6
GRBM_SE2_PERF_SEL_SX_BUSY = 7
GRBM_SE2_PERF_SEL_TA_BUSY = 8
GRBM_SE2_PERF_SEL_CB_CLEAN = 9
GRBM_SE2_PERF_SEL_DB_CLEAN = 10
GRBM_SE2_PERF_SEL_PA_BUSY = 12
GRBM_SE2_PERF_SEL_BCI_BUSY = 14
GRBM_SE2_PERF_SEL_RMI_BUSY = 15
GRBM_SE2_PERF_SEL_UTCL1_BUSY = 16
GRBM_SE2_PERF_SEL_TCP_BUSY = 17
GRBM_SE2_PERF_SEL_GL1CC_BUSY = 18
GRBM_SE2_PERF_SEL_GL1H_BUSY = 19
GRBM_SE2_PERF_SEL_PC_BUSY = 20
GRBM_SE2_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_SE3_PERF_SEL'
GRBM_SE3_PERF_SEL__enumvalues = {
0: 'GRBM_SE3_PERF_SEL_COUNT',
1: 'GRBM_SE3_PERF_SEL_USER_DEFINED',
2: 'GRBM_SE3_PERF_SEL_CB_BUSY',
3: 'GRBM_SE3_PERF_SEL_DB_BUSY',
4: 'GRBM_SE3_PERF_SEL_SC_BUSY',
6: 'GRBM_SE3_PERF_SEL_SPI_BUSY',
7: 'GRBM_SE3_PERF_SEL_SX_BUSY',
8: 'GRBM_SE3_PERF_SEL_TA_BUSY',
9: 'GRBM_SE3_PERF_SEL_CB_CLEAN',
10: 'GRBM_SE3_PERF_SEL_DB_CLEAN',
12: 'GRBM_SE3_PERF_SEL_PA_BUSY',
14: 'GRBM_SE3_PERF_SEL_BCI_BUSY',
15: 'GRBM_SE3_PERF_SEL_RMI_BUSY',
16: 'GRBM_SE3_PERF_SEL_UTCL1_BUSY',
17: 'GRBM_SE3_PERF_SEL_TCP_BUSY',
18: 'GRBM_SE3_PERF_SEL_GL1CC_BUSY',
19: 'GRBM_SE3_PERF_SEL_GL1H_BUSY',
20: 'GRBM_SE3_PERF_SEL_PC_BUSY',
}
GRBM_SE3_PERF_SEL_COUNT = 0
GRBM_SE3_PERF_SEL_USER_DEFINED = 1
GRBM_SE3_PERF_SEL_CB_BUSY = 2
GRBM_SE3_PERF_SEL_DB_BUSY = 3
GRBM_SE3_PERF_SEL_SC_BUSY = 4
GRBM_SE3_PERF_SEL_SPI_BUSY = 6
GRBM_SE3_PERF_SEL_SX_BUSY = 7
GRBM_SE3_PERF_SEL_TA_BUSY = 8
GRBM_SE3_PERF_SEL_CB_CLEAN = 9
GRBM_SE3_PERF_SEL_DB_CLEAN = 10
GRBM_SE3_PERF_SEL_PA_BUSY = 12
GRBM_SE3_PERF_SEL_BCI_BUSY = 14
GRBM_SE3_PERF_SEL_RMI_BUSY = 15
GRBM_SE3_PERF_SEL_UTCL1_BUSY = 16
GRBM_SE3_PERF_SEL_TCP_BUSY = 17
GRBM_SE3_PERF_SEL_GL1CC_BUSY = 18
GRBM_SE3_PERF_SEL_GL1H_BUSY = 19
GRBM_SE3_PERF_SEL_PC_BUSY = 20
GRBM_SE3_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_SE4_PERF_SEL'
GRBM_SE4_PERF_SEL__enumvalues = {
0: 'GRBM_SE4_PERF_SEL_COUNT',
1: 'GRBM_SE4_PERF_SEL_USER_DEFINED',
2: 'GRBM_SE4_PERF_SEL_CB_BUSY',
3: 'GRBM_SE4_PERF_SEL_DB_BUSY',
4: 'GRBM_SE4_PERF_SEL_SC_BUSY',
6: 'GRBM_SE4_PERF_SEL_SPI_BUSY',
7: 'GRBM_SE4_PERF_SEL_SX_BUSY',
8: 'GRBM_SE4_PERF_SEL_TA_BUSY',
9: 'GRBM_SE4_PERF_SEL_CB_CLEAN',
10: 'GRBM_SE4_PERF_SEL_DB_CLEAN',
12: 'GRBM_SE4_PERF_SEL_PA_BUSY',
14: 'GRBM_SE4_PERF_SEL_BCI_BUSY',
15: 'GRBM_SE4_PERF_SEL_RMI_BUSY',
16: 'GRBM_SE4_PERF_SEL_UTCL1_BUSY',
17: 'GRBM_SE4_PERF_SEL_TCP_BUSY',
18: 'GRBM_SE4_PERF_SEL_GL1CC_BUSY',
19: 'GRBM_SE4_PERF_SEL_GL1H_BUSY',
20: 'GRBM_SE4_PERF_SEL_PC_BUSY',
}
GRBM_SE4_PERF_SEL_COUNT = 0
GRBM_SE4_PERF_SEL_USER_DEFINED = 1
GRBM_SE4_PERF_SEL_CB_BUSY = 2
GRBM_SE4_PERF_SEL_DB_BUSY = 3
GRBM_SE4_PERF_SEL_SC_BUSY = 4
GRBM_SE4_PERF_SEL_SPI_BUSY = 6
GRBM_SE4_PERF_SEL_SX_BUSY = 7
GRBM_SE4_PERF_SEL_TA_BUSY = 8
GRBM_SE4_PERF_SEL_CB_CLEAN = 9
GRBM_SE4_PERF_SEL_DB_CLEAN = 10
GRBM_SE4_PERF_SEL_PA_BUSY = 12
GRBM_SE4_PERF_SEL_BCI_BUSY = 14
GRBM_SE4_PERF_SEL_RMI_BUSY = 15
GRBM_SE4_PERF_SEL_UTCL1_BUSY = 16
GRBM_SE4_PERF_SEL_TCP_BUSY = 17
GRBM_SE4_PERF_SEL_GL1CC_BUSY = 18
GRBM_SE4_PERF_SEL_GL1H_BUSY = 19
GRBM_SE4_PERF_SEL_PC_BUSY = 20
GRBM_SE4_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_SE5_PERF_SEL'
GRBM_SE5_PERF_SEL__enumvalues = {
0: 'GRBM_SE5_PERF_SEL_COUNT',
1: 'GRBM_SE5_PERF_SEL_USER_DEFINED',
2: 'GRBM_SE5_PERF_SEL_CB_BUSY',
3: 'GRBM_SE5_PERF_SEL_DB_BUSY',
4: 'GRBM_SE5_PERF_SEL_SC_BUSY',
6: 'GRBM_SE5_PERF_SEL_SPI_BUSY',
7: 'GRBM_SE5_PERF_SEL_SX_BUSY',
8: 'GRBM_SE5_PERF_SEL_TA_BUSY',
9: 'GRBM_SE5_PERF_SEL_CB_CLEAN',
10: 'GRBM_SE5_PERF_SEL_DB_CLEAN',
12: 'GRBM_SE5_PERF_SEL_PA_BUSY',
14: 'GRBM_SE5_PERF_SEL_BCI_BUSY',
15: 'GRBM_SE5_PERF_SEL_RMI_BUSY',
16: 'GRBM_SE5_PERF_SEL_UTCL1_BUSY',
17: 'GRBM_SE5_PERF_SEL_TCP_BUSY',
18: 'GRBM_SE5_PERF_SEL_GL1CC_BUSY',
19: 'GRBM_SE5_PERF_SEL_GL1H_BUSY',
20: 'GRBM_SE5_PERF_SEL_PC_BUSY',
}
GRBM_SE5_PERF_SEL_COUNT = 0
GRBM_SE5_PERF_SEL_USER_DEFINED = 1
GRBM_SE5_PERF_SEL_CB_BUSY = 2
GRBM_SE5_PERF_SEL_DB_BUSY = 3
GRBM_SE5_PERF_SEL_SC_BUSY = 4
GRBM_SE5_PERF_SEL_SPI_BUSY = 6
GRBM_SE5_PERF_SEL_SX_BUSY = 7
GRBM_SE5_PERF_SEL_TA_BUSY = 8
GRBM_SE5_PERF_SEL_CB_CLEAN = 9
GRBM_SE5_PERF_SEL_DB_CLEAN = 10
GRBM_SE5_PERF_SEL_PA_BUSY = 12
GRBM_SE5_PERF_SEL_BCI_BUSY = 14
GRBM_SE5_PERF_SEL_RMI_BUSY = 15
GRBM_SE5_PERF_SEL_UTCL1_BUSY = 16
GRBM_SE5_PERF_SEL_TCP_BUSY = 17
GRBM_SE5_PERF_SEL_GL1CC_BUSY = 18
GRBM_SE5_PERF_SEL_GL1H_BUSY = 19
GRBM_SE5_PERF_SEL_PC_BUSY = 20
GRBM_SE5_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_SE6_PERF_SEL'
GRBM_SE6_PERF_SEL__enumvalues = {
0: 'GRBM_SE6_PERF_SEL_COUNT',
1: 'GRBM_SE6_PERF_SEL_USER_DEFINED',
2: 'GRBM_SE6_PERF_SEL_CB_BUSY',
3: 'GRBM_SE6_PERF_SEL_DB_BUSY',
4: 'GRBM_SE6_PERF_SEL_SC_BUSY',
6: 'GRBM_SE6_PERF_SEL_SPI_BUSY',
7: 'GRBM_SE6_PERF_SEL_SX_BUSY',
8: 'GRBM_SE6_PERF_SEL_TA_BUSY',
9: 'GRBM_SE6_PERF_SEL_CB_CLEAN',
10: 'GRBM_SE6_PERF_SEL_DB_CLEAN',
12: 'GRBM_SE6_PERF_SEL_PA_BUSY',
14: 'GRBM_SE6_PERF_SEL_BCI_BUSY',
15: 'GRBM_SE6_PERF_SEL_RMI_BUSY',
16: 'GRBM_SE6_PERF_SEL_UTCL1_BUSY',
17: 'GRBM_SE6_PERF_SEL_TCP_BUSY',
18: 'GRBM_SE6_PERF_SEL_GL1CC_BUSY',
19: 'GRBM_SE6_PERF_SEL_GL1H_BUSY',
20: 'GRBM_SE6_PERF_SEL_PC_BUSY',
}
GRBM_SE6_PERF_SEL_COUNT = 0
GRBM_SE6_PERF_SEL_USER_DEFINED = 1
GRBM_SE6_PERF_SEL_CB_BUSY = 2
GRBM_SE6_PERF_SEL_DB_BUSY = 3
GRBM_SE6_PERF_SEL_SC_BUSY = 4
GRBM_SE6_PERF_SEL_SPI_BUSY = 6
GRBM_SE6_PERF_SEL_SX_BUSY = 7
GRBM_SE6_PERF_SEL_TA_BUSY = 8
GRBM_SE6_PERF_SEL_CB_CLEAN = 9
GRBM_SE6_PERF_SEL_DB_CLEAN = 10
GRBM_SE6_PERF_SEL_PA_BUSY = 12
GRBM_SE6_PERF_SEL_BCI_BUSY = 14
GRBM_SE6_PERF_SEL_RMI_BUSY = 15
GRBM_SE6_PERF_SEL_UTCL1_BUSY = 16
GRBM_SE6_PERF_SEL_TCP_BUSY = 17
GRBM_SE6_PERF_SEL_GL1CC_BUSY = 18
GRBM_SE6_PERF_SEL_GL1H_BUSY = 19
GRBM_SE6_PERF_SEL_PC_BUSY = 20
GRBM_SE6_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'GRBM_SE7_PERF_SEL'
GRBM_SE7_PERF_SEL__enumvalues = {
0: 'GRBM_SE7_PERF_SEL_COUNT',
1: 'GRBM_SE7_PERF_SEL_USER_DEFINED',
2: 'GRBM_SE7_PERF_SEL_CB_BUSY',
3: 'GRBM_SE7_PERF_SEL_DB_BUSY',
4: 'GRBM_SE7_PERF_SEL_SC_BUSY',
6: 'GRBM_SE7_PERF_SEL_SPI_BUSY',
7: 'GRBM_SE7_PERF_SEL_SX_BUSY',
8: 'GRBM_SE7_PERF_SEL_TA_BUSY',
9: 'GRBM_SE7_PERF_SEL_CB_CLEAN',
10: 'GRBM_SE7_PERF_SEL_DB_CLEAN',
12: 'GRBM_SE7_PERF_SEL_PA_BUSY',
14: 'GRBM_SE7_PERF_SEL_BCI_BUSY',
15: 'GRBM_SE7_PERF_SEL_RMI_BUSY',
16: 'GRBM_SE7_PERF_SEL_UTCL1_BUSY',
17: 'GRBM_SE7_PERF_SEL_TCP_BUSY',
18: 'GRBM_SE7_PERF_SEL_GL1CC_BUSY',
19: 'GRBM_SE7_PERF_SEL_GL1H_BUSY',
20: 'GRBM_SE7_PERF_SEL_PC_BUSY',
}
GRBM_SE7_PERF_SEL_COUNT = 0
GRBM_SE7_PERF_SEL_USER_DEFINED = 1
GRBM_SE7_PERF_SEL_CB_BUSY = 2
GRBM_SE7_PERF_SEL_DB_BUSY = 3
GRBM_SE7_PERF_SEL_SC_BUSY = 4
GRBM_SE7_PERF_SEL_SPI_BUSY = 6
GRBM_SE7_PERF_SEL_SX_BUSY = 7
GRBM_SE7_PERF_SEL_TA_BUSY = 8
GRBM_SE7_PERF_SEL_CB_CLEAN = 9
GRBM_SE7_PERF_SEL_DB_CLEAN = 10
GRBM_SE7_PERF_SEL_PA_BUSY = 12
GRBM_SE7_PERF_SEL_BCI_BUSY = 14
GRBM_SE7_PERF_SEL_RMI_BUSY = 15
GRBM_SE7_PERF_SEL_UTCL1_BUSY = 16
GRBM_SE7_PERF_SEL_TCP_BUSY = 17
GRBM_SE7_PERF_SEL_GL1CC_BUSY = 18
GRBM_SE7_PERF_SEL_GL1H_BUSY = 19
GRBM_SE7_PERF_SEL_PC_BUSY = 20
GRBM_SE7_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PIPE_COMPAT_LEVEL'
PIPE_COMPAT_LEVEL__enumvalues = {
0: 'GEN_ZERO',
1: 'GEN_ONE',
2: 'GEN_TWO',
3: 'GEN_RESERVED',
}
GEN_ZERO = 0
GEN_ONE = 1
GEN_TWO = 2
GEN_RESERVED = 3
PIPE_COMPAT_LEVEL = ctypes.c_uint32 # enum
# values for enumeration 'CPC_LATENCY_STATS_SEL'
CPC_LATENCY_STATS_SEL__enumvalues = {
0: 'CPC_LATENCY_STATS_SEL_XACK_MAX',
1: 'CPC_LATENCY_STATS_SEL_XACK_MIN',
2: 'CPC_LATENCY_STATS_SEL_XACK_LAST',
3: 'CPC_LATENCY_STATS_SEL_XNACK_MAX',
4: 'CPC_LATENCY_STATS_SEL_XNACK_MIN',
5: 'CPC_LATENCY_STATS_SEL_XNACK_LAST',
6: 'CPC_LATENCY_STATS_SEL_INVAL_MAX',
7: 'CPC_LATENCY_STATS_SEL_INVAL_MIN',
8: 'CPC_LATENCY_STATS_SEL_INVAL_LAST',
}
CPC_LATENCY_STATS_SEL_XACK_MAX = 0
CPC_LATENCY_STATS_SEL_XACK_MIN = 1
CPC_LATENCY_STATS_SEL_XACK_LAST = 2
CPC_LATENCY_STATS_SEL_XNACK_MAX = 3
CPC_LATENCY_STATS_SEL_XNACK_MIN = 4
CPC_LATENCY_STATS_SEL_XNACK_LAST = 5
CPC_LATENCY_STATS_SEL_INVAL_MAX = 6
CPC_LATENCY_STATS_SEL_INVAL_MIN = 7
CPC_LATENCY_STATS_SEL_INVAL_LAST = 8
CPC_LATENCY_STATS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPC_PERFCOUNT_SEL'
CPC_PERFCOUNT_SEL__enumvalues = {
0: 'CPC_PERF_SEL_ALWAYS_COUNT',
1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE',
2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION',
5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE',
6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY',
7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF',
8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ',
9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ',
10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE',
11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ',
12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF',
13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE',
14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY',
15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF',
16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ',
17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ',
18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE',
19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ',
20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF',
21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE',
22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS',
24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION',
25: 'CPC_PERF_SEL_CPC_STAT_BUSY',
26: 'CPC_PERF_SEL_CPC_STAT_IDLE',
27: 'CPC_PERF_SEL_CPC_STAT_STALL',
28: 'CPC_PERF_SEL_CPC_TCIU_BUSY',
29: 'CPC_PERF_SEL_CPC_TCIU_IDLE',
30: 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY',
31: 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE',
32: 'CPC_PERF_SEL_CPC_UTCL2IU_STALL',
33: 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY',
34: 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY',
35: 'CPC_PERF_SEL_CPC_GCRIU_BUSY',
36: 'CPC_PERF_SEL_CPC_GCRIU_IDLE',
37: 'CPC_PERF_SEL_CPC_GCRIU_STALL',
38: 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
39: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ',
40: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ',
41: 'CPC_PERF_SEL_CPC_UTCL2IU_XACK',
42: 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK',
43: 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT',
44: 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS',
45: 'CPC_PERF_SEL_MES_THREAD0',
46: 'CPC_PERF_SEL_MES_THREAD1',
}
CPC_PERF_SEL_ALWAYS_COUNT = 0
CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1
CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2
CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8
CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 9
CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 10
CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11
CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12
CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16
CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 17
CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 18
CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19
CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20
CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21
CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22
CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23
CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24
CPC_PERF_SEL_CPC_STAT_BUSY = 25
CPC_PERF_SEL_CPC_STAT_IDLE = 26
CPC_PERF_SEL_CPC_STAT_STALL = 27
CPC_PERF_SEL_CPC_TCIU_BUSY = 28
CPC_PERF_SEL_CPC_TCIU_IDLE = 29
CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 30
CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 31
CPC_PERF_SEL_CPC_UTCL2IU_STALL = 32
CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 33
CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 34
CPC_PERF_SEL_CPC_GCRIU_BUSY = 35
CPC_PERF_SEL_CPC_GCRIU_IDLE = 36
CPC_PERF_SEL_CPC_GCRIU_STALL = 37
CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 38
CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 39
CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 40
CPC_PERF_SEL_CPC_UTCL2IU_XACK = 41
CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 42
CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 43
CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 44
CPC_PERF_SEL_MES_THREAD0 = 45
CPC_PERF_SEL_MES_THREAD1 = 46
CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPF_LATENCY_STATS_SEL'
CPF_LATENCY_STATS_SEL__enumvalues = {
0: 'CPF_LATENCY_STATS_SEL_XACK_MAX',
1: 'CPF_LATENCY_STATS_SEL_XACK_MIN',
2: 'CPF_LATENCY_STATS_SEL_XACK_LAST',
3: 'CPF_LATENCY_STATS_SEL_XNACK_MAX',
4: 'CPF_LATENCY_STATS_SEL_XNACK_MIN',
5: 'CPF_LATENCY_STATS_SEL_XNACK_LAST',
6: 'CPF_LATENCY_STATS_SEL_READ_MAX',
7: 'CPF_LATENCY_STATS_SEL_READ_MIN',
8: 'CPF_LATENCY_STATS_SEL_READ_LAST',
9: 'CPF_LATENCY_STATS_SEL_INVAL_MAX',
10: 'CPF_LATENCY_STATS_SEL_INVAL_MIN',
11: 'CPF_LATENCY_STATS_SEL_INVAL_LAST',
}
CPF_LATENCY_STATS_SEL_XACK_MAX = 0
CPF_LATENCY_STATS_SEL_XACK_MIN = 1
CPF_LATENCY_STATS_SEL_XACK_LAST = 2
CPF_LATENCY_STATS_SEL_XNACK_MAX = 3
CPF_LATENCY_STATS_SEL_XNACK_MIN = 4
CPF_LATENCY_STATS_SEL_XNACK_LAST = 5
CPF_LATENCY_STATS_SEL_READ_MAX = 6
CPF_LATENCY_STATS_SEL_READ_MIN = 7
CPF_LATENCY_STATS_SEL_READ_LAST = 8
CPF_LATENCY_STATS_SEL_INVAL_MAX = 9
CPF_LATENCY_STATS_SEL_INVAL_MIN = 10
CPF_LATENCY_STATS_SEL_INVAL_LAST = 11
CPF_LATENCY_STATS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPF_PERFCOUNTWINDOW_SEL'
CPF_PERFCOUNTWINDOW_SEL__enumvalues = {
0: 'CPF_PERFWINDOW_SEL_CSF',
1: 'CPF_PERFWINDOW_SEL_HQD1',
2: 'CPF_PERFWINDOW_SEL_HQD2',
3: 'CPF_PERFWINDOW_SEL_RDMA',
4: 'CPF_PERFWINDOW_SEL_RWPP',
}
CPF_PERFWINDOW_SEL_CSF = 0
CPF_PERFWINDOW_SEL_HQD1 = 1
CPF_PERFWINDOW_SEL_HQD2 = 2
CPF_PERFWINDOW_SEL_RDMA = 3
CPF_PERFWINDOW_SEL_RWPP = 4
CPF_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPF_PERFCOUNT_SEL'
CPF_PERFCOUNT_SEL__enumvalues = {
0: 'CPF_PERF_SEL_ALWAYS_COUNT',
2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE',
3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS',
4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING',
5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1',
6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2',
7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE',
10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR',
11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS',
12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT',
13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID',
14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID',
15: 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT',
16: 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT',
17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS',
19: 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION',
20: 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION',
21: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE',
22: 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
23: 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT',
24: 'CPF_PERF_SEL_CPF_STAT_BUSY',
25: 'CPF_PERF_SEL_CPF_STAT_IDLE',
26: 'CPF_PERF_SEL_CPF_STAT_STALL',
27: 'CPF_PERF_SEL_CPF_TCIU_BUSY',
28: 'CPF_PERF_SEL_CPF_TCIU_IDLE',
29: 'CPF_PERF_SEL_CPF_TCIU_STALL',
30: 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY',
31: 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE',
32: 'CPF_PERF_SEL_CPF_UTCL2IU_STALL',
33: 'CPF_PERF_SEL_CPF_GCRIU_BUSY',
34: 'CPF_PERF_SEL_CPF_GCRIU_IDLE',
35: 'CPF_PERF_SEL_CPF_GCRIU_STALL',
36: 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
37: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB',
38: 'CPF_PERF_SEL_CPF_UTCL2IU_XACK',
39: 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK',
40: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ',
41: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE',
42: 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY',
43: 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY',
}
CPF_PERF_SEL_ALWAYS_COUNT = 0
CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2
CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 7
CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10
CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11
CPF_PERF_SEL_GRBM_DWORDS_SENT = 12
CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13
CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14
CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 15
CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 16
CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17
CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18
CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 19
CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 20
CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 21
CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 22
CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 23
CPF_PERF_SEL_CPF_STAT_BUSY = 24
CPF_PERF_SEL_CPF_STAT_IDLE = 25
CPF_PERF_SEL_CPF_STAT_STALL = 26
CPF_PERF_SEL_CPF_TCIU_BUSY = 27
CPF_PERF_SEL_CPF_TCIU_IDLE = 28
CPF_PERF_SEL_CPF_TCIU_STALL = 29
CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 30
CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 31
CPF_PERF_SEL_CPF_UTCL2IU_STALL = 32
CPF_PERF_SEL_CPF_GCRIU_BUSY = 33
CPF_PERF_SEL_CPF_GCRIU_IDLE = 34
CPF_PERF_SEL_CPF_GCRIU_STALL = 35
CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 36
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 37
CPF_PERF_SEL_CPF_UTCL2IU_XACK = 38
CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 39
CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 40
CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 41
CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 42
CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 43
CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPF_SCRATCH_REG_ATOMIC_OP'
CPF_SCRATCH_REG_ATOMIC_OP__enumvalues = {
0: 'CPF_SCRATCH_REG_ATOMIC_ADD',
1: 'CPF_SCRATCH_REG_ATOMIC_SUB',
2: 'CPF_SCRATCH_REG_ATOMIC_OR',
3: 'CPF_SCRATCH_REG_ATOMIC_AND',
4: 'CPF_SCRATCH_REG_ATOMIC_NOT',
5: 'CPF_SCRATCH_REG_ATOMIC_MIN',
6: 'CPF_SCRATCH_REG_ATOMIC_MAX',
7: 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP',
}
CPF_SCRATCH_REG_ATOMIC_ADD = 0
CPF_SCRATCH_REG_ATOMIC_SUB = 1
CPF_SCRATCH_REG_ATOMIC_OR = 2
CPF_SCRATCH_REG_ATOMIC_AND = 3
CPF_SCRATCH_REG_ATOMIC_NOT = 4
CPF_SCRATCH_REG_ATOMIC_MIN = 5
CPF_SCRATCH_REG_ATOMIC_MAX = 6
CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 7
CPF_SCRATCH_REG_ATOMIC_OP = ctypes.c_uint32 # enum
# values for enumeration 'CPG_LATENCY_STATS_SEL'
CPG_LATENCY_STATS_SEL__enumvalues = {
0: 'CPG_LATENCY_STATS_SEL_XACK_MAX',
1: 'CPG_LATENCY_STATS_SEL_XACK_MIN',
2: 'CPG_LATENCY_STATS_SEL_XACK_LAST',
3: 'CPG_LATENCY_STATS_SEL_XNACK_MAX',
4: 'CPG_LATENCY_STATS_SEL_XNACK_MIN',
5: 'CPG_LATENCY_STATS_SEL_XNACK_LAST',
6: 'CPG_LATENCY_STATS_SEL_WRITE_MAX',
7: 'CPG_LATENCY_STATS_SEL_WRITE_MIN',
8: 'CPG_LATENCY_STATS_SEL_WRITE_LAST',
9: 'CPG_LATENCY_STATS_SEL_READ_MAX',
10: 'CPG_LATENCY_STATS_SEL_READ_MIN',
11: 'CPG_LATENCY_STATS_SEL_READ_LAST',
12: 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX',
13: 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN',
14: 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST',
15: 'CPG_LATENCY_STATS_SEL_INVAL_MAX',
16: 'CPG_LATENCY_STATS_SEL_INVAL_MIN',
17: 'CPG_LATENCY_STATS_SEL_INVAL_LAST',
}
CPG_LATENCY_STATS_SEL_XACK_MAX = 0
CPG_LATENCY_STATS_SEL_XACK_MIN = 1
CPG_LATENCY_STATS_SEL_XACK_LAST = 2
CPG_LATENCY_STATS_SEL_XNACK_MAX = 3
CPG_LATENCY_STATS_SEL_XNACK_MIN = 4
CPG_LATENCY_STATS_SEL_XNACK_LAST = 5
CPG_LATENCY_STATS_SEL_WRITE_MAX = 6
CPG_LATENCY_STATS_SEL_WRITE_MIN = 7
CPG_LATENCY_STATS_SEL_WRITE_LAST = 8
CPG_LATENCY_STATS_SEL_READ_MAX = 9
CPG_LATENCY_STATS_SEL_READ_MIN = 10
CPG_LATENCY_STATS_SEL_READ_LAST = 11
CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 12
CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 13
CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 14
CPG_LATENCY_STATS_SEL_INVAL_MAX = 15
CPG_LATENCY_STATS_SEL_INVAL_MIN = 16
CPG_LATENCY_STATS_SEL_INVAL_LAST = 17
CPG_LATENCY_STATS_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPG_PERFCOUNTWINDOW_SEL'
CPG_PERFCOUNTWINDOW_SEL__enumvalues = {
0: 'CPG_PERFWINDOW_SEL_PFP',
1: 'CPG_PERFWINDOW_SEL_ME',
2: 'CPG_PERFWINDOW_SEL_CE',
3: 'CPG_PERFWINDOW_SEL_MES',
4: 'CPG_PERFWINDOW_SEL_MEC1',
5: 'CPG_PERFWINDOW_SEL_MEC2',
6: 'CPG_PERFWINDOW_SEL_DFY',
7: 'CPG_PERFWINDOW_SEL_DMA',
8: 'CPG_PERFWINDOW_SEL_SHADOW',
9: 'CPG_PERFWINDOW_SEL_RB',
10: 'CPG_PERFWINDOW_SEL_CEDMA',
11: 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR',
12: 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR',
13: 'CPG_PERFWINDOW_SEL_PQ1',
14: 'CPG_PERFWINDOW_SEL_PQ2',
15: 'CPG_PERFWINDOW_SEL_PQ3',
16: 'CPG_PERFWINDOW_SEL_MEMWR',
17: 'CPG_PERFWINDOW_SEL_MEMRD',
18: 'CPG_PERFWINDOW_SEL_VGT0',
19: 'CPG_PERFWINDOW_SEL_VGT1',
20: 'CPG_PERFWINDOW_SEL_APPEND',
21: 'CPG_PERFWINDOW_SEL_QURD',
22: 'CPG_PERFWINDOW_SEL_DDID',
23: 'CPG_PERFWINDOW_SEL_SR',
24: 'CPG_PERFWINDOW_SEL_QU_EOP',
25: 'CPG_PERFWINDOW_SEL_QU_STRM',
26: 'CPG_PERFWINDOW_SEL_QU_PIPE',
27: 'CPG_PERFWINDOW_SEL_RESERVED1',
28: 'CPG_PERFWINDOW_SEL_CPC_IC',
29: 'CPG_PERFWINDOW_SEL_RESERVED2',
30: 'CPG_PERFWINDOW_SEL_CPG_IC',
}
CPG_PERFWINDOW_SEL_PFP = 0
CPG_PERFWINDOW_SEL_ME = 1
CPG_PERFWINDOW_SEL_CE = 2
CPG_PERFWINDOW_SEL_MES = 3
CPG_PERFWINDOW_SEL_MEC1 = 4
CPG_PERFWINDOW_SEL_MEC2 = 5
CPG_PERFWINDOW_SEL_DFY = 6
CPG_PERFWINDOW_SEL_DMA = 7
CPG_PERFWINDOW_SEL_SHADOW = 8
CPG_PERFWINDOW_SEL_RB = 9
CPG_PERFWINDOW_SEL_CEDMA = 10
CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 11
CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 12
CPG_PERFWINDOW_SEL_PQ1 = 13
CPG_PERFWINDOW_SEL_PQ2 = 14
CPG_PERFWINDOW_SEL_PQ3 = 15
CPG_PERFWINDOW_SEL_MEMWR = 16
CPG_PERFWINDOW_SEL_MEMRD = 17
CPG_PERFWINDOW_SEL_VGT0 = 18
CPG_PERFWINDOW_SEL_VGT1 = 19
CPG_PERFWINDOW_SEL_APPEND = 20
CPG_PERFWINDOW_SEL_QURD = 21
CPG_PERFWINDOW_SEL_DDID = 22
CPG_PERFWINDOW_SEL_SR = 23
CPG_PERFWINDOW_SEL_QU_EOP = 24
CPG_PERFWINDOW_SEL_QU_STRM = 25
CPG_PERFWINDOW_SEL_QU_PIPE = 26
CPG_PERFWINDOW_SEL_RESERVED1 = 27
CPG_PERFWINDOW_SEL_CPC_IC = 28
CPG_PERFWINDOW_SEL_RESERVED2 = 29
CPG_PERFWINDOW_SEL_CPG_IC = 30
CPG_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CPG_PERFCOUNT_SEL'
CPG_PERFCOUNT_SEL__enumvalues = {
0: 'CPG_PERF_SEL_ALWAYS_COUNT',
1: 'CPG_PERF_SEL_RBIU_FIFO_FULL',
4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT',
5: 'CPG_PERF_SEL_ME_PARSER_BUSY',
6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS',
7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS',
9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS',
10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS',
11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS',
12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ',
13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ',
14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX',
15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS',
16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE',
17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM',
18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY',
19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY',
20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY',
21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ',
22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP',
23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ',
24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX',
25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU',
26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS',
27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH',
28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER',
29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER',
31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY',
32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID',
33: 'CPG_PERF_SEL_REGISTER_CLK_VALID',
34: 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT',
35: 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT',
36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP',
37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE',
38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO',
39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO',
41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ',
42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG',
43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER',
44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE',
45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS',
46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS',
48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION',
49: 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
50: 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT',
51: 'CPG_PERF_SEL_CPG_STAT_BUSY',
52: 'CPG_PERF_SEL_CPG_STAT_IDLE',
53: 'CPG_PERF_SEL_CPG_STAT_STALL',
54: 'CPG_PERF_SEL_CPG_TCIU_BUSY',
55: 'CPG_PERF_SEL_CPG_TCIU_IDLE',
56: 'CPG_PERF_SEL_CPG_TCIU_STALL',
57: 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY',
58: 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE',
59: 'CPG_PERF_SEL_CPG_UTCL2IU_STALL',
60: 'CPG_PERF_SEL_CPG_GCRIU_BUSY',
61: 'CPG_PERF_SEL_CPG_GCRIU_IDLE',
62: 'CPG_PERF_SEL_CPG_GCRIU_STALL',
63: 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
64: 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY',
65: 'CPG_PERF_SEL_CPG_UTCL2IU_XACK',
66: 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK',
67: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY',
68: 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT',
69: 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS',
70: 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT',
71: 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS',
72: 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT',
73: 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS',
74: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1',
75: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1',
76: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2',
77: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2',
78: 'CPG_PERF_SEL_DMA_BUSY',
79: 'CPG_PERF_SEL_DMA_STARVED',
80: 'CPG_PERF_SEL_DMA_STALLED',
81: 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL',
82: 'CPG_PERF_SEL_PFP_PWS_STALLED0',
83: 'CPG_PERF_SEL_ME_PWS_STALLED0',
84: 'CPG_PERF_SEL_PFP_PWS_STALLED1',
85: 'CPG_PERF_SEL_ME_PWS_STALLED1',
}
CPG_PERF_SEL_ALWAYS_COUNT = 0
CPG_PERF_SEL_RBIU_FIFO_FULL = 1
CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4
CPG_PERF_SEL_ME_PARSER_BUSY = 5
CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6
CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7
CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9
CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10
CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11
CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12
CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13
CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14
CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15
CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16
CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17
CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18
CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19
CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20
CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21
CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22
CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23
CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24
CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25
CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26
CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27
CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28
CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29
CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31
CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32
CPG_PERF_SEL_REGISTER_CLK_VALID = 33
CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 34
CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 35
CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36
CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37
CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38
CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39
CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41
CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42
CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43
CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44
CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45
CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46
CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47
CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48
CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 49
CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 50
CPG_PERF_SEL_CPG_STAT_BUSY = 51
CPG_PERF_SEL_CPG_STAT_IDLE = 52
CPG_PERF_SEL_CPG_STAT_STALL = 53
CPG_PERF_SEL_CPG_TCIU_BUSY = 54
CPG_PERF_SEL_CPG_TCIU_IDLE = 55
CPG_PERF_SEL_CPG_TCIU_STALL = 56
CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 57
CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 58
CPG_PERF_SEL_CPG_UTCL2IU_STALL = 59
CPG_PERF_SEL_CPG_GCRIU_BUSY = 60
CPG_PERF_SEL_CPG_GCRIU_IDLE = 61
CPG_PERF_SEL_CPG_GCRIU_STALL = 62
CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 63
CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 64
CPG_PERF_SEL_CPG_UTCL2IU_XACK = 65
CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 66
CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 67
CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 68
CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 69
CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 70
CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 71
CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 72
CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 73
CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 74
CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 75
CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 76
CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 77
CPG_PERF_SEL_DMA_BUSY = 78
CPG_PERF_SEL_DMA_STARVED = 79
CPG_PERF_SEL_DMA_STALLED = 80
CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 81
CPG_PERF_SEL_PFP_PWS_STALLED0 = 82
CPG_PERF_SEL_ME_PWS_STALLED0 = 83
CPG_PERF_SEL_PFP_PWS_STALLED1 = 84
CPG_PERF_SEL_ME_PWS_STALLED1 = 85
CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CP_ALPHA_TAG_RAM_SEL'
CP_ALPHA_TAG_RAM_SEL__enumvalues = {
0: 'CPG_TAG_RAM',
1: 'CPC_TAG_RAM',
2: 'CPF_TAG_RAM',
3: 'RSV_TAG_RAM',
}
CPG_TAG_RAM = 0
CPC_TAG_RAM = 1
CPF_TAG_RAM = 2
RSV_TAG_RAM = 3
CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CP_DDID_CNTL_MODE'
CP_DDID_CNTL_MODE__enumvalues = {
0: 'STALL',
1: 'OVERRUN',
}
STALL = 0
OVERRUN = 1
CP_DDID_CNTL_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CP_DDID_CNTL_SIZE'
CP_DDID_CNTL_SIZE__enumvalues = {
0: 'SIZE_8K',
1: 'SIZE_16K',
}
SIZE_8K = 0
SIZE_16K = 1
CP_DDID_CNTL_SIZE = ctypes.c_uint32 # enum
# values for enumeration 'CP_DDID_CNTL_VMID_SEL'
CP_DDID_CNTL_VMID_SEL__enumvalues = {
0: 'DDID_VMID_PIPE',
1: 'DDID_VMID_CNTL',
}
DDID_VMID_PIPE = 0
DDID_VMID_CNTL = 1
CP_DDID_CNTL_VMID_SEL = ctypes.c_uint32 # enum
# values for enumeration 'CP_ME_ID'
CP_ME_ID__enumvalues = {
0: 'ME_ID0',
1: 'ME_ID1',
2: 'ME_ID2',
3: 'ME_ID3',
}
ME_ID0 = 0
ME_ID1 = 1
ME_ID2 = 2
ME_ID3 = 3
CP_ME_ID = ctypes.c_uint32 # enum
# values for enumeration 'CP_PERFMON_ENABLE_MODE'
CP_PERFMON_ENABLE_MODE__enumvalues = {
0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT',
1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1',
2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE',
3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE',
}
CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0
CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1
CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2
CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3
CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum
# values for enumeration 'CP_PERFMON_STATE'
CP_PERFMON_STATE__enumvalues = {
0: 'CP_PERFMON_STATE_DISABLE_AND_RESET',
1: 'CP_PERFMON_STATE_START_COUNTING',
2: 'CP_PERFMON_STATE_STOP_COUNTING',
3: 'CP_PERFMON_STATE_RESERVED_3',
4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM',
5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM',
}
CP_PERFMON_STATE_DISABLE_AND_RESET = 0
CP_PERFMON_STATE_START_COUNTING = 1
CP_PERFMON_STATE_STOP_COUNTING = 2
CP_PERFMON_STATE_RESERVED_3 = 3
CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4
CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5
CP_PERFMON_STATE = ctypes.c_uint32 # enum
# values for enumeration 'CP_PIPE_ID'
CP_PIPE_ID__enumvalues = {
0: 'PIPE_ID0',
1: 'PIPE_ID1',
2: 'PIPE_ID2',
3: 'PIPE_ID3',
}
PIPE_ID0 = 0
PIPE_ID1 = 1
PIPE_ID2 = 2
PIPE_ID3 = 3
CP_PIPE_ID = ctypes.c_uint32 # enum
# values for enumeration 'CP_RING_ID'
CP_RING_ID__enumvalues = {
0: 'RINGID0',
1: 'RINGID1',
2: 'RINGID2',
3: 'RINGID3',
}
RINGID0 = 0
RINGID1 = 1
RINGID2 = 2
RINGID3 = 3
CP_RING_ID = ctypes.c_uint32 # enum
# values for enumeration 'SPM_PERFMON_STATE'
SPM_PERFMON_STATE__enumvalues = {
0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET',
1: 'STRM_PERFMON_STATE_START_COUNTING',
2: 'STRM_PERFMON_STATE_STOP_COUNTING',
3: 'STRM_PERFMON_STATE_RESERVED_3',
4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM',
5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM',
}
STRM_PERFMON_STATE_DISABLE_AND_RESET = 0
STRM_PERFMON_STATE_START_COUNTING = 1
STRM_PERFMON_STATE_STOP_COUNTING = 2
STRM_PERFMON_STATE_RESERVED_3 = 3
STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4
STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5
SPM_PERFMON_STATE = ctypes.c_uint32 # enum
# values for enumeration 'SX_BLEND_OPT'
SX_BLEND_OPT__enumvalues = {
0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL',
1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE',
2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0',
3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1',
4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0',
5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1',
6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0',
7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE',
}
BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0
BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1
BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2
BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3
BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4
BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5
BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6
BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7
SX_BLEND_OPT = ctypes.c_uint32 # enum
# values for enumeration 'SX_DOWNCONVERT_FORMAT'
SX_DOWNCONVERT_FORMAT__enumvalues = {
0: 'SX_RT_EXPORT_NO_CONVERSION',
1: 'SX_RT_EXPORT_32_R',
2: 'SX_RT_EXPORT_32_A',
3: 'SX_RT_EXPORT_10_11_11',
4: 'SX_RT_EXPORT_2_10_10_10',
5: 'SX_RT_EXPORT_8_8_8_8',
6: 'SX_RT_EXPORT_5_6_5',
7: 'SX_RT_EXPORT_1_5_5_5',
8: 'SX_RT_EXPORT_4_4_4_4',
9: 'SX_RT_EXPORT_16_16_GR',
10: 'SX_RT_EXPORT_16_16_AR',
11: 'SX_RT_EXPORT_9_9_9_E5',
12: 'SX_RT_EXPORT_2_10_10_10_7E3',
13: 'SX_RT_EXPORT_2_10_10_10_6E4',
}
SX_RT_EXPORT_NO_CONVERSION = 0
SX_RT_EXPORT_32_R = 1
SX_RT_EXPORT_32_A = 2
SX_RT_EXPORT_10_11_11 = 3
SX_RT_EXPORT_2_10_10_10 = 4
SX_RT_EXPORT_8_8_8_8 = 5
SX_RT_EXPORT_5_6_5 = 6
SX_RT_EXPORT_1_5_5_5 = 7
SX_RT_EXPORT_4_4_4_4 = 8
SX_RT_EXPORT_16_16_GR = 9
SX_RT_EXPORT_16_16_AR = 10
SX_RT_EXPORT_9_9_9_E5 = 11
SX_RT_EXPORT_2_10_10_10_7E3 = 12
SX_RT_EXPORT_2_10_10_10_6E4 = 13
SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum
# values for enumeration 'SX_OPT_COMB_FCN'
SX_OPT_COMB_FCN__enumvalues = {
0: 'OPT_COMB_NONE',
1: 'OPT_COMB_ADD',
2: 'OPT_COMB_SUBTRACT',
3: 'OPT_COMB_MIN',
4: 'OPT_COMB_MAX',
5: 'OPT_COMB_REVSUBTRACT',
6: 'OPT_COMB_BLEND_DISABLED',
7: 'OPT_COMB_SAFE_ADD',
}
OPT_COMB_NONE = 0
OPT_COMB_ADD = 1
OPT_COMB_SUBTRACT = 2
OPT_COMB_MIN = 3
OPT_COMB_MAX = 4
OPT_COMB_REVSUBTRACT = 5
OPT_COMB_BLEND_DISABLED = 6
OPT_COMB_SAFE_ADD = 7
SX_OPT_COMB_FCN = ctypes.c_uint32 # enum
# values for enumeration 'SX_PERFCOUNTER_VALS'
SX_PERFCOUNTER_VALS__enumvalues = {
0: 'SX_PERF_SEL_PA_IDLE_CYCLES',
1: 'SX_PERF_SEL_PA_REQ',
2: 'SX_PERF_SEL_PA_POS',
3: 'SX_PERF_SEL_CLOCK',
4: 'SX_PERF_SEL_GATE_EN1',
5: 'SX_PERF_SEL_GATE_EN2',
6: 'SX_PERF_SEL_GATE_EN3',
7: 'SX_PERF_SEL_GATE_EN4',
8: 'SX_PERF_SEL_SH_POS_STARVE',
9: 'SX_PERF_SEL_SH_COLOR_STARVE',
10: 'SX_PERF_SEL_SH_POS_STALL',
11: 'SX_PERF_SEL_SH_COLOR_STALL',
12: 'SX_PERF_SEL_DB0_PIXELS',
13: 'SX_PERF_SEL_DB0_HALF_QUADS',
14: 'SX_PERF_SEL_DB0_PIXEL_STALL',
15: 'SX_PERF_SEL_DB0_PIXEL_IDLE',
16: 'SX_PERF_SEL_DB0_PRED_PIXELS',
17: 'SX_PERF_SEL_DB1_PIXELS',
18: 'SX_PERF_SEL_DB1_HALF_QUADS',
19: 'SX_PERF_SEL_DB1_PIXEL_STALL',
20: 'SX_PERF_SEL_DB1_PIXEL_IDLE',
21: 'SX_PERF_SEL_DB1_PRED_PIXELS',
22: 'SX_PERF_SEL_DB2_PIXELS',
23: 'SX_PERF_SEL_DB2_HALF_QUADS',
24: 'SX_PERF_SEL_DB2_PIXEL_STALL',
25: 'SX_PERF_SEL_DB2_PIXEL_IDLE',
26: 'SX_PERF_SEL_DB2_PRED_PIXELS',
27: 'SX_PERF_SEL_DB3_PIXELS',
28: 'SX_PERF_SEL_DB3_HALF_QUADS',
29: 'SX_PERF_SEL_DB3_PIXEL_STALL',
30: 'SX_PERF_SEL_DB3_PIXEL_IDLE',
31: 'SX_PERF_SEL_DB3_PRED_PIXELS',
32: 'SX_PERF_SEL_COL_BUSY',
33: 'SX_PERF_SEL_POS_BUSY',
34: 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS',
35: 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST',
36: 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC',
37: 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS',
38: 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS',
39: 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS',
40: 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST',
41: 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC',
42: 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS',
43: 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS',
44: 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS',
45: 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST',
46: 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC',
47: 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS',
48: 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS',
49: 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS',
50: 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST',
51: 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC',
52: 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS',
53: 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS',
54: 'SX_PERF_SEL_PA_REQ_LATENCY',
55: 'SX_PERF_SEL_POS_SCBD_STALL',
56: 'SX_PERF_SEL_CLOCK_DROP_STALL',
57: 'SX_PERF_SEL_GATE_EN5',
58: 'SX_PERF_SEL_GATE_EN6',
59: 'SX_PERF_SEL_DB0_SIZE',
60: 'SX_PERF_SEL_DB1_SIZE',
61: 'SX_PERF_SEL_DB2_SIZE',
62: 'SX_PERF_SEL_DB3_SIZE',
63: 'SX_PERF_SEL_IDX_STALL_CYCLES',
64: 'SX_PERF_SEL_IDX_IDLE_CYCLES',
65: 'SX_PERF_SEL_IDX_REQ',
66: 'SX_PERF_SEL_IDX_RET',
67: 'SX_PERF_SEL_IDX_REQ_LATENCY',
68: 'SX_PERF_SEL_IDX_SCBD_STALL',
69: 'SX_PERF_SEL_GATE_EN7',
70: 'SX_PERF_SEL_GATE_EN8',
71: 'SX_PERF_SEL_SH_IDX_STARVE',
72: 'SX_PERF_SEL_IDX_BUSY',
73: 'SX_PERF_SEL_PA_POS_BANK_CONF',
74: 'SX_PERF_SEL_DB0_END_OF_WAVE',
75: 'SX_PERF_SEL_DB0_4X2_DISCARD',
76: 'SX_PERF_SEL_DB1_END_OF_WAVE',
77: 'SX_PERF_SEL_DB1_4X2_DISCARD',
78: 'SX_PERF_SEL_DB2_END_OF_WAVE',
79: 'SX_PERF_SEL_DB2_4X2_DISCARD',
80: 'SX_PERF_SEL_DB3_END_OF_WAVE',
81: 'SX_PERF_SEL_DB3_4X2_DISCARD',
}
SX_PERF_SEL_PA_IDLE_CYCLES = 0
SX_PERF_SEL_PA_REQ = 1
SX_PERF_SEL_PA_POS = 2
SX_PERF_SEL_CLOCK = 3
SX_PERF_SEL_GATE_EN1 = 4
SX_PERF_SEL_GATE_EN2 = 5
SX_PERF_SEL_GATE_EN3 = 6
SX_PERF_SEL_GATE_EN4 = 7
SX_PERF_SEL_SH_POS_STARVE = 8
SX_PERF_SEL_SH_COLOR_STARVE = 9
SX_PERF_SEL_SH_POS_STALL = 10
SX_PERF_SEL_SH_COLOR_STALL = 11
SX_PERF_SEL_DB0_PIXELS = 12
SX_PERF_SEL_DB0_HALF_QUADS = 13
SX_PERF_SEL_DB0_PIXEL_STALL = 14
SX_PERF_SEL_DB0_PIXEL_IDLE = 15
SX_PERF_SEL_DB0_PRED_PIXELS = 16
SX_PERF_SEL_DB1_PIXELS = 17
SX_PERF_SEL_DB1_HALF_QUADS = 18
SX_PERF_SEL_DB1_PIXEL_STALL = 19
SX_PERF_SEL_DB1_PIXEL_IDLE = 20
SX_PERF_SEL_DB1_PRED_PIXELS = 21
SX_PERF_SEL_DB2_PIXELS = 22
SX_PERF_SEL_DB2_HALF_QUADS = 23
SX_PERF_SEL_DB2_PIXEL_STALL = 24
SX_PERF_SEL_DB2_PIXEL_IDLE = 25
SX_PERF_SEL_DB2_PRED_PIXELS = 26
SX_PERF_SEL_DB3_PIXELS = 27
SX_PERF_SEL_DB3_HALF_QUADS = 28
SX_PERF_SEL_DB3_PIXEL_STALL = 29
SX_PERF_SEL_DB3_PIXEL_IDLE = 30
SX_PERF_SEL_DB3_PRED_PIXELS = 31
SX_PERF_SEL_COL_BUSY = 32
SX_PERF_SEL_POS_BUSY = 33
SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 34
SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 35
SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 36
SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 37
SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 38
SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 39
SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 40
SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 41
SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 42
SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 43
SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 44
SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 45
SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 46
SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 47
SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 48
SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 49
SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 50
SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 51
SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 52
SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 53
SX_PERF_SEL_PA_REQ_LATENCY = 54
SX_PERF_SEL_POS_SCBD_STALL = 55
SX_PERF_SEL_CLOCK_DROP_STALL = 56
SX_PERF_SEL_GATE_EN5 = 57
SX_PERF_SEL_GATE_EN6 = 58
SX_PERF_SEL_DB0_SIZE = 59
SX_PERF_SEL_DB1_SIZE = 60
SX_PERF_SEL_DB2_SIZE = 61
SX_PERF_SEL_DB3_SIZE = 62
SX_PERF_SEL_IDX_STALL_CYCLES = 63
SX_PERF_SEL_IDX_IDLE_CYCLES = 64
SX_PERF_SEL_IDX_REQ = 65
SX_PERF_SEL_IDX_RET = 66
SX_PERF_SEL_IDX_REQ_LATENCY = 67
SX_PERF_SEL_IDX_SCBD_STALL = 68
SX_PERF_SEL_GATE_EN7 = 69
SX_PERF_SEL_GATE_EN8 = 70
SX_PERF_SEL_SH_IDX_STARVE = 71
SX_PERF_SEL_IDX_BUSY = 72
SX_PERF_SEL_PA_POS_BANK_CONF = 73
SX_PERF_SEL_DB0_END_OF_WAVE = 74
SX_PERF_SEL_DB0_4X2_DISCARD = 75
SX_PERF_SEL_DB1_END_OF_WAVE = 76
SX_PERF_SEL_DB1_4X2_DISCARD = 77
SX_PERF_SEL_DB2_END_OF_WAVE = 78
SX_PERF_SEL_DB2_4X2_DISCARD = 79
SX_PERF_SEL_DB3_END_OF_WAVE = 80
SX_PERF_SEL_DB3_4X2_DISCARD = 81
SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum
# values for enumeration 'CompareFrag'
CompareFrag__enumvalues = {
0: 'FRAG_NEVER',
1: 'FRAG_LESS',
2: 'FRAG_EQUAL',
3: 'FRAG_LEQUAL',
4: 'FRAG_GREATER',
5: 'FRAG_NOTEQUAL',
6: 'FRAG_GEQUAL',
7: 'FRAG_ALWAYS',
}
FRAG_NEVER = 0
FRAG_LESS = 1
FRAG_EQUAL = 2
FRAG_LEQUAL = 3
FRAG_GREATER = 4
FRAG_NOTEQUAL = 5
FRAG_GEQUAL = 6
FRAG_ALWAYS = 7
CompareFrag = ctypes.c_uint32 # enum
# values for enumeration 'ConservativeZExport'
ConservativeZExport__enumvalues = {
0: 'EXPORT_ANY_Z',
1: 'EXPORT_LESS_THAN_Z',
2: 'EXPORT_GREATER_THAN_Z',
3: 'EXPORT_RESERVED',
}
EXPORT_ANY_Z = 0
EXPORT_LESS_THAN_Z = 1
EXPORT_GREATER_THAN_Z = 2
EXPORT_RESERVED = 3
ConservativeZExport = ctypes.c_uint32 # enum
# values for enumeration 'DFSMFlushEvents'
DFSMFlushEvents__enumvalues = {
0: 'DB_FLUSH_AND_INV_DB_DATA_TS',
1: 'DB_FLUSH_AND_INV_DB_META',
2: 'DB_CACHE_FLUSH',
3: 'DB_CACHE_FLUSH_TS',
4: 'DB_CACHE_FLUSH_AND_INV_EVENT',
5: 'DB_CACHE_FLUSH_AND_INV_TS_EVENT',
6: 'DB_VPORT_CHANGED_EVENT',
7: 'DB_CONTEXT_DONE_EVENT',
8: 'DB_BREAK_BATCH_EVENT',
9: 'DB_INVOKE_CHANGE_EVENT',
10: 'DB_CONTEXT_SUSPEND_EVENT',
}
DB_FLUSH_AND_INV_DB_DATA_TS = 0
DB_FLUSH_AND_INV_DB_META = 1
DB_CACHE_FLUSH = 2
DB_CACHE_FLUSH_TS = 3
DB_CACHE_FLUSH_AND_INV_EVENT = 4
DB_CACHE_FLUSH_AND_INV_TS_EVENT = 5
DB_VPORT_CHANGED_EVENT = 6
DB_CONTEXT_DONE_EVENT = 7
DB_BREAK_BATCH_EVENT = 8
DB_INVOKE_CHANGE_EVENT = 9
DB_CONTEXT_SUSPEND_EVENT = 10
DFSMFlushEvents = ctypes.c_uint32 # enum
# values for enumeration 'DbMemArbWatermarks'
DbMemArbWatermarks__enumvalues = {
0: 'TRANSFERRED_64_BYTES',
1: 'TRANSFERRED_128_BYTES',
2: 'TRANSFERRED_256_BYTES',
3: 'TRANSFERRED_512_BYTES',
4: 'TRANSFERRED_1024_BYTES',
5: 'TRANSFERRED_2048_BYTES',
6: 'TRANSFERRED_4096_BYTES',
7: 'TRANSFERRED_8192_BYTES',
}
TRANSFERRED_64_BYTES = 0
TRANSFERRED_128_BYTES = 1
TRANSFERRED_256_BYTES = 2
TRANSFERRED_512_BYTES = 3
TRANSFERRED_1024_BYTES = 4
TRANSFERRED_2048_BYTES = 5
TRANSFERRED_4096_BYTES = 6
TRANSFERRED_8192_BYTES = 7
DbMemArbWatermarks = ctypes.c_uint32 # enum
# values for enumeration 'DbPRTFaultBehavior'
DbPRTFaultBehavior__enumvalues = {
0: 'FAULT_ZERO',
1: 'FAULT_ONE',
2: 'FAULT_FAIL',
3: 'FAULT_PASS',
}
FAULT_ZERO = 0
FAULT_ONE = 1
FAULT_FAIL = 2
FAULT_PASS = 3
DbPRTFaultBehavior = ctypes.c_uint32 # enum
# values for enumeration 'DbPSLControl'
DbPSLControl__enumvalues = {
0: 'PSLC_AUTO',
1: 'PSLC_ON_HANG_ONLY',
2: 'PSLC_ASAP',
3: 'PSLC_COUNTDOWN',
}
PSLC_AUTO = 0
PSLC_ON_HANG_ONLY = 1
PSLC_ASAP = 2
PSLC_COUNTDOWN = 3
DbPSLControl = ctypes.c_uint32 # enum
# values for enumeration 'ForceControl'
ForceControl__enumvalues = {
0: 'FORCE_OFF',
1: 'FORCE_ENABLE',
2: 'FORCE_DISABLE',
3: 'FORCE_RESERVED',
}
FORCE_OFF = 0
FORCE_ENABLE = 1
FORCE_DISABLE = 2
FORCE_RESERVED = 3
ForceControl = ctypes.c_uint32 # enum
# values for enumeration 'OreoMode'
OreoMode__enumvalues = {
0: 'OMODE_BLEND',
1: 'OMODE_O_THEN_B',
2: 'OMODE_P_THEN_O_THEN_B',
3: 'OMODE_RESERVED_3',
}
OMODE_BLEND = 0
OMODE_O_THEN_B = 1
OMODE_P_THEN_O_THEN_B = 2
OMODE_RESERVED_3 = 3
OreoMode = ctypes.c_uint32 # enum
# values for enumeration 'PerfCounter_Vals'
PerfCounter_Vals__enumvalues = {
0: 'DB_PERF_SEL_SC_DB_tile_sends',
1: 'DB_PERF_SEL_SC_DB_tile_busy',
2: 'DB_PERF_SEL_SC_DB_tile_stalls',
3: 'DB_PERF_SEL_SC_DB_tile_events',
4: 'DB_PERF_SEL_SC_DB_tile_tiles',
5: 'DB_PERF_SEL_SC_DB_tile_covered',
6: 'DB_PERF_SEL_hiz_tc_read_starved',
7: 'DB_PERF_SEL_hiz_tc_write_stall',
8: 'DB_PERF_SEL_hiz_tile_culled',
9: 'DB_PERF_SEL_his_tile_culled',
10: 'DB_PERF_SEL_DB_SC_tile_sends',
11: 'DB_PERF_SEL_DB_SC_tile_busy',
12: 'DB_PERF_SEL_DB_SC_tile_stalls',
13: 'DB_PERF_SEL_DB_SC_tile_df_stalls',
14: 'DB_PERF_SEL_DB_SC_tile_tiles',
15: 'DB_PERF_SEL_DB_SC_tile_culled',
16: 'DB_PERF_SEL_DB_SC_tile_hier_kill',
17: 'DB_PERF_SEL_DB_SC_tile_fast_ops',
18: 'DB_PERF_SEL_DB_SC_tile_no_ops',
19: 'DB_PERF_SEL_DB_SC_tile_tile_rate',
20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill',
21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops',
22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops',
23: 'DB_PERF_SEL_SC_DB_quad_sends',
24: 'DB_PERF_SEL_SC_DB_quad_busy',
25: 'DB_PERF_SEL_SC_DB_quad_squads',
26: 'DB_PERF_SEL_SC_DB_quad_tiles',
27: 'DB_PERF_SEL_SC_DB_quad_pixels',
28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles',
29: 'DB_PERF_SEL_DB_SC_quad_sends',
30: 'DB_PERF_SEL_DB_SC_quad_busy',
31: 'DB_PERF_SEL_DB_SC_quad_stalls',
32: 'DB_PERF_SEL_DB_SC_quad_tiles',
33: 'DB_PERF_SEL_DB_SC_quad_lit_quad',
34: 'DB_PERF_SEL_DB_CB_tile_sends',
35: 'DB_PERF_SEL_DB_CB_tile_busy',
36: 'DB_PERF_SEL_DB_CB_tile_stalls',
37: 'DB_PERF_SEL_SX_DB_quad_sends',
38: 'DB_PERF_SEL_SX_DB_quad_busy',
39: 'DB_PERF_SEL_SX_DB_quad_stalls',
40: 'DB_PERF_SEL_SX_DB_quad_quads',
41: 'DB_PERF_SEL_SX_DB_quad_pixels',
42: 'DB_PERF_SEL_SX_DB_quad_exports',
43: 'DB_PERF_SEL_SH_quads_outstanding_sum',
44: 'DB_PERF_SEL_DB_CB_lquad_sends',
45: 'DB_PERF_SEL_DB_CB_lquad_busy',
46: 'DB_PERF_SEL_DB_CB_lquad_stalls',
47: 'DB_PERF_SEL_DB_CB_lquad_quads',
48: 'DB_PERF_SEL_tile_rd_sends',
49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum',
50: 'DB_PERF_SEL_quad_rd_sends',
51: 'DB_PERF_SEL_quad_rd_busy',
52: 'DB_PERF_SEL_quad_rd_mi_stall',
53: 'DB_PERF_SEL_quad_rd_rw_collision',
54: 'DB_PERF_SEL_quad_rd_tag_stall',
55: 'DB_PERF_SEL_quad_rd_32byte_reqs',
56: 'DB_PERF_SEL_quad_rd_panic',
57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum',
58: 'DB_PERF_SEL_quad_rdret_sends',
59: 'DB_PERF_SEL_quad_rdret_busy',
60: 'DB_PERF_SEL_tile_wr_sends',
61: 'DB_PERF_SEL_tile_wr_acks',
62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum',
63: 'DB_PERF_SEL_quad_wr_sends',
64: 'DB_PERF_SEL_quad_wr_busy',
65: 'DB_PERF_SEL_quad_wr_mi_stall',
66: 'DB_PERF_SEL_quad_wr_coherency_stall',
67: 'DB_PERF_SEL_quad_wr_acks',
68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum',
69: 'DB_PERF_SEL_Tile_Cache_misses',
70: 'DB_PERF_SEL_Tile_Cache_hits',
71: 'DB_PERF_SEL_Tile_Cache_flushes',
72: 'DB_PERF_SEL_Tile_Cache_surface_stall',
73: 'DB_PERF_SEL_Tile_Cache_starves',
74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve',
75: 'DB_PERF_SEL_tcp_dispatcher_reads',
76: 'DB_PERF_SEL_tcp_prefetcher_reads',
77: 'DB_PERF_SEL_tcp_preloader_reads',
78: 'DB_PERF_SEL_tcp_dispatcher_flushes',
79: 'DB_PERF_SEL_tcp_prefetcher_flushes',
80: 'DB_PERF_SEL_tcp_preloader_flushes',
81: 'DB_PERF_SEL_Depth_Tile_Cache_sends',
82: 'DB_PERF_SEL_Depth_Tile_Cache_busy',
83: 'DB_PERF_SEL_Depth_Tile_Cache_starves',
84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked',
85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall',
86: 'DB_PERF_SEL_Depth_Tile_Cache_misses',
87: 'DB_PERF_SEL_Depth_Tile_Cache_hits',
88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes',
89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile',
90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop',
91: 'DB_PERF_SEL_Depth_Tile_Cache_event',
92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees',
93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees',
94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve',
95: 'DB_PERF_SEL_Stencil_Cache_misses',
96: 'DB_PERF_SEL_Stencil_Cache_hits',
97: 'DB_PERF_SEL_Stencil_Cache_flushes',
98: 'DB_PERF_SEL_Stencil_Cache_starves',
99: 'DB_PERF_SEL_Stencil_Cache_frees',
100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses',
101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits',
102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes',
103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves',
104: 'DB_PERF_SEL_Z_Cache_pmask_misses',
105: 'DB_PERF_SEL_Z_Cache_pmask_hits',
106: 'DB_PERF_SEL_Z_Cache_pmask_flushes',
107: 'DB_PERF_SEL_Z_Cache_pmask_starves',
108: 'DB_PERF_SEL_Z_Cache_frees',
109: 'DB_PERF_SEL_Plane_Cache_misses',
110: 'DB_PERF_SEL_Plane_Cache_hits',
111: 'DB_PERF_SEL_Plane_Cache_flushes',
112: 'DB_PERF_SEL_Plane_Cache_starves',
113: 'DB_PERF_SEL_Plane_Cache_frees',
114: 'DB_PERF_SEL_flush_expanded_stencil',
115: 'DB_PERF_SEL_flush_compressed_stencil',
116: 'DB_PERF_SEL_flush_single_stencil',
117: 'DB_PERF_SEL_planes_flushed',
118: 'DB_PERF_SEL_flush_1plane',
119: 'DB_PERF_SEL_flush_2plane',
120: 'DB_PERF_SEL_flush_3plane',
121: 'DB_PERF_SEL_flush_4plane',
122: 'DB_PERF_SEL_flush_5plane',
123: 'DB_PERF_SEL_flush_6plane',
124: 'DB_PERF_SEL_flush_7plane',
125: 'DB_PERF_SEL_flush_8plane',
126: 'DB_PERF_SEL_flush_9plane',
127: 'DB_PERF_SEL_flush_10plane',
128: 'DB_PERF_SEL_flush_11plane',
129: 'DB_PERF_SEL_flush_12plane',
130: 'DB_PERF_SEL_flush_13plane',
131: 'DB_PERF_SEL_flush_14plane',
132: 'DB_PERF_SEL_flush_15plane',
133: 'DB_PERF_SEL_flush_16plane',
134: 'DB_PERF_SEL_flush_expanded_z',
135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done',
136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done',
137: 'DB_PERF_SEL_dk_tile_sends',
138: 'DB_PERF_SEL_dk_tile_busy',
139: 'DB_PERF_SEL_dk_tile_quad_starves',
140: 'DB_PERF_SEL_dk_tile_stalls',
141: 'DB_PERF_SEL_dk_squad_sends',
142: 'DB_PERF_SEL_dk_squad_busy',
143: 'DB_PERF_SEL_dk_squad_stalls',
144: 'DB_PERF_SEL_Op_Pipe_Busy',
145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall',
146: 'DB_PERF_SEL_qc_busy',
147: 'DB_PERF_SEL_qc_xfc',
148: 'DB_PERF_SEL_qc_conflicts',
149: 'DB_PERF_SEL_qc_full_stall',
150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ',
151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ',
152: 'DB_PERF_SEL_tsc_insert_summarize_stall',
153: 'DB_PERF_SEL_tl_busy',
154: 'DB_PERF_SEL_tl_dtc_read_starved',
155: 'DB_PERF_SEL_tl_z_fetch_stall',
156: 'DB_PERF_SEL_tl_stencil_stall',
157: 'DB_PERF_SEL_tl_z_decompress_stall',
158: 'DB_PERF_SEL_tl_stencil_locked_stall',
159: 'DB_PERF_SEL_tl_events',
160: 'DB_PERF_SEL_tl_summarize_squads',
161: 'DB_PERF_SEL_tl_flush_expand_squads',
162: 'DB_PERF_SEL_tl_expand_squads',
163: 'DB_PERF_SEL_tl_preZ_squads',
164: 'DB_PERF_SEL_tl_postZ_squads',
165: 'DB_PERF_SEL_tl_preZ_noop_squads',
166: 'DB_PERF_SEL_tl_postZ_noop_squads',
167: 'DB_PERF_SEL_tl_tile_ops',
168: 'DB_PERF_SEL_tl_in_xfc',
169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall',
170: 'DB_PERF_SEL_tl_in_fast_z_stall',
171: 'DB_PERF_SEL_tl_out_xfc',
172: 'DB_PERF_SEL_tl_out_squads',
173: 'DB_PERF_SEL_zf_plane_multicycle',
174: 'DB_PERF_SEL_PostZ_Samples_passing_Z',
175: 'DB_PERF_SEL_PostZ_Samples_failing_Z',
176: 'DB_PERF_SEL_PostZ_Samples_failing_S',
177: 'DB_PERF_SEL_PreZ_Samples_passing_Z',
178: 'DB_PERF_SEL_PreZ_Samples_failing_Z',
179: 'DB_PERF_SEL_PreZ_Samples_failing_S',
180: 'DB_PERF_SEL_ts_tc_update_stall',
181: 'DB_PERF_SEL_sc_kick_start',
182: 'DB_PERF_SEL_sc_kick_end',
183: 'DB_PERF_SEL_clock_reg_active',
184: 'DB_PERF_SEL_clock_main_active',
185: 'DB_PERF_SEL_clock_mem_export_active',
186: 'DB_PERF_SEL_esr_ps_out_busy',
187: 'DB_PERF_SEL_esr_ps_lqf_busy',
188: 'DB_PERF_SEL_esr_ps_lqf_stall',
189: 'DB_PERF_SEL_etr_out_send',
190: 'DB_PERF_SEL_etr_out_busy',
191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall',
192: 'DB_PERF_SEL_etr_out_cb_tile_stall',
193: 'DB_PERF_SEL_etr_out_esr_stall',
194: 'DB_PERF_SEL_esr_ps_vic_busy',
195: 'DB_PERF_SEL_esr_ps_vic_stall',
196: 'DB_PERF_SEL_esr_eot_fwd_busy',
197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad',
198: 'DB_PERF_SEL_esr_eot_fwd_forward',
199: 'DB_PERF_SEL_esr_sqq_zi_busy',
200: 'DB_PERF_SEL_esr_sqq_zi_stall',
201: 'DB_PERF_SEL_postzl_sq_pt_busy',
202: 'DB_PERF_SEL_postzl_sq_pt_stall',
203: 'DB_PERF_SEL_postzl_se_busy',
204: 'DB_PERF_SEL_postzl_se_stall',
205: 'DB_PERF_SEL_postzl_partial_launch',
206: 'DB_PERF_SEL_postzl_full_launch',
207: 'DB_PERF_SEL_postzl_partial_waiting',
208: 'DB_PERF_SEL_postzl_tile_mem_stall',
209: 'DB_PERF_SEL_postzl_tile_init_stall',
210: 'DB_PERF_SEL_prezl_tile_mem_stall',
211: 'DB_PERF_SEL_prezl_tile_init_stall',
212: 'DB_PERF_SEL_dtt_sm_clash_stall',
213: 'DB_PERF_SEL_dtt_sm_slot_stall',
214: 'DB_PERF_SEL_dtt_sm_miss_stall',
215: 'DB_PERF_SEL_mi_rdreq_busy',
216: 'DB_PERF_SEL_mi_rdreq_stall',
217: 'DB_PERF_SEL_mi_wrreq_busy',
218: 'DB_PERF_SEL_mi_wrreq_stall',
219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop',
220: 'DB_PERF_SEL_dkg_tile_rate_tile',
221: 'DB_PERF_SEL_prezl_src_in_sends',
222: 'DB_PERF_SEL_prezl_src_in_stall',
223: 'DB_PERF_SEL_prezl_src_in_squads',
224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled',
225: 'DB_PERF_SEL_prezl_src_in_tile_rate',
226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled',
227: 'DB_PERF_SEL_prezl_src_out_stall',
228: 'DB_PERF_SEL_postzl_src_in_sends',
229: 'DB_PERF_SEL_postzl_src_in_stall',
230: 'DB_PERF_SEL_postzl_src_in_squads',
231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled',
232: 'DB_PERF_SEL_postzl_src_in_tile_rate',
233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled',
234: 'DB_PERF_SEL_postzl_src_out_stall',
235: 'DB_PERF_SEL_esr_ps_src_in_sends',
236: 'DB_PERF_SEL_esr_ps_src_in_stall',
237: 'DB_PERF_SEL_esr_ps_src_in_squads',
238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled',
239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate',
240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled',
241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate',
242: 'DB_PERF_SEL_esr_ps_src_out_stall',
243: 'DB_PERF_SEL_depth_bounds_tile_culled',
244: 'DB_PERF_SEL_PreZ_Samples_failing_DB',
245: 'DB_PERF_SEL_PostZ_Samples_failing_DB',
246: 'DB_PERF_SEL_flush_compressed',
247: 'DB_PERF_SEL_flush_plane_le4',
248: 'DB_PERF_SEL_tiles_z_fully_summarized',
249: 'DB_PERF_SEL_tiles_stencil_fully_summarized',
250: 'DB_PERF_SEL_tiles_z_clear_on_expclear',
251: 'DB_PERF_SEL_tiles_s_clear_on_expclear',
252: 'DB_PERF_SEL_tiles_decomp_on_expclear',
253: 'DB_PERF_SEL_tiles_compressed_to_decompressed',
254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy',
255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy',
256: 'DB_PERF_SEL_di_dt_stall',
257: 'Spare_257',
258: 'DB_PERF_SEL_DB_SC_s_tile_rate',
259: 'DB_PERF_SEL_DB_SC_c_tile_rate',
260: 'DB_PERF_SEL_DB_SC_z_tile_rate',
261: 'DB_PERF_SEL_DB_CB_lquad_export_quads',
262: 'DB_PERF_SEL_DB_CB_lquad_double_format',
263: 'DB_PERF_SEL_DB_CB_lquad_fast_format',
264: 'DB_PERF_SEL_DB_CB_lquad_slow_format',
265: 'DB_PERF_SEL_CB_DB_rdreq_sends',
266: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends',
267: 'DB_PERF_SEL_CB_DB_wrreq_sends',
268: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends',
269: 'DB_PERF_SEL_DB_CB_rdret_ack',
270: 'DB_PERF_SEL_DB_CB_rdret_nack',
271: 'DB_PERF_SEL_DB_CB_wrret_ack',
272: 'DB_PERF_SEL_DB_CB_wrret_nack',
273: 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall',
274: 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall',
275: 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall',
276: 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall',
277: 'DB_PERF_SEL_unmapped_z_tile_culled',
278: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS',
279: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA',
280: 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS',
281: 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event',
282: 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix',
283: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix',
284: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix',
285: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix',
286: 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending',
287: 'DB_PERF_SEL_DB_CB_context_dones',
288: 'DB_PERF_SEL_DB_CB_eop_dones',
289: 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed',
290: 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled',
291: 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read',
292: 'DB_PERF_SEL_SC_DB_tile_backface',
293: 'DB_PERF_SEL_SC_DB_quad_quads',
294: 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel',
295: 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels',
296: 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels',
297: 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels',
298: 'DB_PERF_SEL_DB_SC_quad_double_quad',
299: 'DB_PERF_SEL_SX_DB_quad_export_quads',
300: 'DB_PERF_SEL_SX_DB_quad_double_format',
301: 'DB_PERF_SEL_SX_DB_quad_fast_format',
302: 'DB_PERF_SEL_SX_DB_quad_slow_format',
303: 'DB_PERF_SEL_quad_rd_sends_unc',
304: 'DB_PERF_SEL_quad_rd_mi_stall_unc',
305: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0',
306: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1',
307: 'DB_PERF_SEL_SC_DB_quad_quads_pipe0',
308: 'DB_PERF_SEL_SC_DB_quad_quads_pipe1',
309: 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits',
310: 'DB_PERF_SEL_noz_waiting_for_postz_done',
311: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1',
312: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1',
313: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2',
314: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2',
315: 'DB_PERF_SEL_RMI_rd_tile_32byte_req',
316: 'DB_PERF_SEL_RMI_rd_z_32byte_req',
317: 'DB_PERF_SEL_RMI_rd_s_32byte_req',
318: 'DB_PERF_SEL_RMI_wr_tile_32byte_req',
319: 'DB_PERF_SEL_RMI_wr_z_32byte_req',
320: 'DB_PERF_SEL_RMI_wr_s_32byte_req',
321: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req',
322: 'DB_PERF_SEL_RMI_rd_tile_32byte_ret',
323: 'DB_PERF_SEL_RMI_rd_z_32byte_ret',
324: 'DB_PERF_SEL_RMI_rd_s_32byte_ret',
325: 'DB_PERF_SEL_RMI_wr_tile_32byte_ack',
326: 'DB_PERF_SEL_RMI_wr_z_32byte_ack',
327: 'DB_PERF_SEL_RMI_wr_s_32byte_ack',
328: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack',
329: 'DB_PERF_SEL_esr_vic_sqq_busy',
330: 'DB_PERF_SEL_esr_vic_sqq_stall',
331: 'DB_PERF_SEL_esr_psi_vic_tile_rate',
332: 'DB_PERF_SEL_esr_vic_footprint_match_2x2',
333: 'DB_PERF_SEL_esr_vic_footprint_match_2x1',
334: 'DB_PERF_SEL_esr_vic_footprint_match_1x2',
335: 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels',
336: 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels',
337: 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels',
338: 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1',
339: 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1',
340: 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut',
341: 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut',
342: 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt',
343: 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt',
344: 'DB_PERF_SEL_ts_events_pws_enable',
345: 'DB_PERF_SEL_ps_events_pws_enable',
346: 'DB_PERF_SEL_cs_events_pws_enable',
347: 'DB_PERF_SEL_DB_SC_quad_noz_tiles',
348: 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad',
}
DB_PERF_SEL_SC_DB_tile_sends = 0
DB_PERF_SEL_SC_DB_tile_busy = 1
DB_PERF_SEL_SC_DB_tile_stalls = 2
DB_PERF_SEL_SC_DB_tile_events = 3
DB_PERF_SEL_SC_DB_tile_tiles = 4
DB_PERF_SEL_SC_DB_tile_covered = 5
DB_PERF_SEL_hiz_tc_read_starved = 6
DB_PERF_SEL_hiz_tc_write_stall = 7
DB_PERF_SEL_hiz_tile_culled = 8
DB_PERF_SEL_his_tile_culled = 9
DB_PERF_SEL_DB_SC_tile_sends = 10
DB_PERF_SEL_DB_SC_tile_busy = 11
DB_PERF_SEL_DB_SC_tile_stalls = 12
DB_PERF_SEL_DB_SC_tile_df_stalls = 13
DB_PERF_SEL_DB_SC_tile_tiles = 14
DB_PERF_SEL_DB_SC_tile_culled = 15
DB_PERF_SEL_DB_SC_tile_hier_kill = 16
DB_PERF_SEL_DB_SC_tile_fast_ops = 17
DB_PERF_SEL_DB_SC_tile_no_ops = 18
DB_PERF_SEL_DB_SC_tile_tile_rate = 19
DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20
DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21
DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22
DB_PERF_SEL_SC_DB_quad_sends = 23
DB_PERF_SEL_SC_DB_quad_busy = 24
DB_PERF_SEL_SC_DB_quad_squads = 25
DB_PERF_SEL_SC_DB_quad_tiles = 26
DB_PERF_SEL_SC_DB_quad_pixels = 27
DB_PERF_SEL_SC_DB_quad_killed_tiles = 28
DB_PERF_SEL_DB_SC_quad_sends = 29
DB_PERF_SEL_DB_SC_quad_busy = 30
DB_PERF_SEL_DB_SC_quad_stalls = 31
DB_PERF_SEL_DB_SC_quad_tiles = 32
DB_PERF_SEL_DB_SC_quad_lit_quad = 33
DB_PERF_SEL_DB_CB_tile_sends = 34
DB_PERF_SEL_DB_CB_tile_busy = 35
DB_PERF_SEL_DB_CB_tile_stalls = 36
DB_PERF_SEL_SX_DB_quad_sends = 37
DB_PERF_SEL_SX_DB_quad_busy = 38
DB_PERF_SEL_SX_DB_quad_stalls = 39
DB_PERF_SEL_SX_DB_quad_quads = 40
DB_PERF_SEL_SX_DB_quad_pixels = 41
DB_PERF_SEL_SX_DB_quad_exports = 42
DB_PERF_SEL_SH_quads_outstanding_sum = 43
DB_PERF_SEL_DB_CB_lquad_sends = 44
DB_PERF_SEL_DB_CB_lquad_busy = 45
DB_PERF_SEL_DB_CB_lquad_stalls = 46
DB_PERF_SEL_DB_CB_lquad_quads = 47
DB_PERF_SEL_tile_rd_sends = 48
DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49
DB_PERF_SEL_quad_rd_sends = 50
DB_PERF_SEL_quad_rd_busy = 51
DB_PERF_SEL_quad_rd_mi_stall = 52
DB_PERF_SEL_quad_rd_rw_collision = 53
DB_PERF_SEL_quad_rd_tag_stall = 54
DB_PERF_SEL_quad_rd_32byte_reqs = 55
DB_PERF_SEL_quad_rd_panic = 56
DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57
DB_PERF_SEL_quad_rdret_sends = 58
DB_PERF_SEL_quad_rdret_busy = 59
DB_PERF_SEL_tile_wr_sends = 60
DB_PERF_SEL_tile_wr_acks = 61
DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62
DB_PERF_SEL_quad_wr_sends = 63
DB_PERF_SEL_quad_wr_busy = 64
DB_PERF_SEL_quad_wr_mi_stall = 65
DB_PERF_SEL_quad_wr_coherency_stall = 66
DB_PERF_SEL_quad_wr_acks = 67
DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68
DB_PERF_SEL_Tile_Cache_misses = 69
DB_PERF_SEL_Tile_Cache_hits = 70
DB_PERF_SEL_Tile_Cache_flushes = 71
DB_PERF_SEL_Tile_Cache_surface_stall = 72
DB_PERF_SEL_Tile_Cache_starves = 73
DB_PERF_SEL_Tile_Cache_mem_return_starve = 74
DB_PERF_SEL_tcp_dispatcher_reads = 75
DB_PERF_SEL_tcp_prefetcher_reads = 76
DB_PERF_SEL_tcp_preloader_reads = 77
DB_PERF_SEL_tcp_dispatcher_flushes = 78
DB_PERF_SEL_tcp_prefetcher_flushes = 79
DB_PERF_SEL_tcp_preloader_flushes = 80
DB_PERF_SEL_Depth_Tile_Cache_sends = 81
DB_PERF_SEL_Depth_Tile_Cache_busy = 82
DB_PERF_SEL_Depth_Tile_Cache_starves = 83
DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84
DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85
DB_PERF_SEL_Depth_Tile_Cache_misses = 86
DB_PERF_SEL_Depth_Tile_Cache_hits = 87
DB_PERF_SEL_Depth_Tile_Cache_flushes = 88
DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89
DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90
DB_PERF_SEL_Depth_Tile_Cache_event = 91
DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92
DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93
DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94
DB_PERF_SEL_Stencil_Cache_misses = 95
DB_PERF_SEL_Stencil_Cache_hits = 96
DB_PERF_SEL_Stencil_Cache_flushes = 97
DB_PERF_SEL_Stencil_Cache_starves = 98
DB_PERF_SEL_Stencil_Cache_frees = 99
DB_PERF_SEL_Z_Cache_separate_Z_misses = 100
DB_PERF_SEL_Z_Cache_separate_Z_hits = 101
DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102
DB_PERF_SEL_Z_Cache_separate_Z_starves = 103
DB_PERF_SEL_Z_Cache_pmask_misses = 104
DB_PERF_SEL_Z_Cache_pmask_hits = 105
DB_PERF_SEL_Z_Cache_pmask_flushes = 106
DB_PERF_SEL_Z_Cache_pmask_starves = 107
DB_PERF_SEL_Z_Cache_frees = 108
DB_PERF_SEL_Plane_Cache_misses = 109
DB_PERF_SEL_Plane_Cache_hits = 110
DB_PERF_SEL_Plane_Cache_flushes = 111
DB_PERF_SEL_Plane_Cache_starves = 112
DB_PERF_SEL_Plane_Cache_frees = 113
DB_PERF_SEL_flush_expanded_stencil = 114
DB_PERF_SEL_flush_compressed_stencil = 115
DB_PERF_SEL_flush_single_stencil = 116
DB_PERF_SEL_planes_flushed = 117
DB_PERF_SEL_flush_1plane = 118
DB_PERF_SEL_flush_2plane = 119
DB_PERF_SEL_flush_3plane = 120
DB_PERF_SEL_flush_4plane = 121
DB_PERF_SEL_flush_5plane = 122
DB_PERF_SEL_flush_6plane = 123
DB_PERF_SEL_flush_7plane = 124
DB_PERF_SEL_flush_8plane = 125
DB_PERF_SEL_flush_9plane = 126
DB_PERF_SEL_flush_10plane = 127
DB_PERF_SEL_flush_11plane = 128
DB_PERF_SEL_flush_12plane = 129
DB_PERF_SEL_flush_13plane = 130
DB_PERF_SEL_flush_14plane = 131
DB_PERF_SEL_flush_15plane = 132
DB_PERF_SEL_flush_16plane = 133
DB_PERF_SEL_flush_expanded_z = 134
DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135
DB_PERF_SEL_reZ_waiting_for_postZ_done = 136
DB_PERF_SEL_dk_tile_sends = 137
DB_PERF_SEL_dk_tile_busy = 138
DB_PERF_SEL_dk_tile_quad_starves = 139
DB_PERF_SEL_dk_tile_stalls = 140
DB_PERF_SEL_dk_squad_sends = 141
DB_PERF_SEL_dk_squad_busy = 142
DB_PERF_SEL_dk_squad_stalls = 143
DB_PERF_SEL_Op_Pipe_Busy = 144
DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145
DB_PERF_SEL_qc_busy = 146
DB_PERF_SEL_qc_xfc = 147
DB_PERF_SEL_qc_conflicts = 148
DB_PERF_SEL_qc_full_stall = 149
DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150
DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151
DB_PERF_SEL_tsc_insert_summarize_stall = 152
DB_PERF_SEL_tl_busy = 153
DB_PERF_SEL_tl_dtc_read_starved = 154
DB_PERF_SEL_tl_z_fetch_stall = 155
DB_PERF_SEL_tl_stencil_stall = 156
DB_PERF_SEL_tl_z_decompress_stall = 157
DB_PERF_SEL_tl_stencil_locked_stall = 158
DB_PERF_SEL_tl_events = 159
DB_PERF_SEL_tl_summarize_squads = 160
DB_PERF_SEL_tl_flush_expand_squads = 161
DB_PERF_SEL_tl_expand_squads = 162
DB_PERF_SEL_tl_preZ_squads = 163
DB_PERF_SEL_tl_postZ_squads = 164
DB_PERF_SEL_tl_preZ_noop_squads = 165
DB_PERF_SEL_tl_postZ_noop_squads = 166
DB_PERF_SEL_tl_tile_ops = 167
DB_PERF_SEL_tl_in_xfc = 168
DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169
DB_PERF_SEL_tl_in_fast_z_stall = 170
DB_PERF_SEL_tl_out_xfc = 171
DB_PERF_SEL_tl_out_squads = 172
DB_PERF_SEL_zf_plane_multicycle = 173
DB_PERF_SEL_PostZ_Samples_passing_Z = 174
DB_PERF_SEL_PostZ_Samples_failing_Z = 175
DB_PERF_SEL_PostZ_Samples_failing_S = 176
DB_PERF_SEL_PreZ_Samples_passing_Z = 177
DB_PERF_SEL_PreZ_Samples_failing_Z = 178
DB_PERF_SEL_PreZ_Samples_failing_S = 179
DB_PERF_SEL_ts_tc_update_stall = 180
DB_PERF_SEL_sc_kick_start = 181
DB_PERF_SEL_sc_kick_end = 182
DB_PERF_SEL_clock_reg_active = 183
DB_PERF_SEL_clock_main_active = 184
DB_PERF_SEL_clock_mem_export_active = 185
DB_PERF_SEL_esr_ps_out_busy = 186
DB_PERF_SEL_esr_ps_lqf_busy = 187
DB_PERF_SEL_esr_ps_lqf_stall = 188
DB_PERF_SEL_etr_out_send = 189
DB_PERF_SEL_etr_out_busy = 190
DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191
DB_PERF_SEL_etr_out_cb_tile_stall = 192
DB_PERF_SEL_etr_out_esr_stall = 193
DB_PERF_SEL_esr_ps_vic_busy = 194
DB_PERF_SEL_esr_ps_vic_stall = 195
DB_PERF_SEL_esr_eot_fwd_busy = 196
DB_PERF_SEL_esr_eot_fwd_holding_squad = 197
DB_PERF_SEL_esr_eot_fwd_forward = 198
DB_PERF_SEL_esr_sqq_zi_busy = 199
DB_PERF_SEL_esr_sqq_zi_stall = 200
DB_PERF_SEL_postzl_sq_pt_busy = 201
DB_PERF_SEL_postzl_sq_pt_stall = 202
DB_PERF_SEL_postzl_se_busy = 203
DB_PERF_SEL_postzl_se_stall = 204
DB_PERF_SEL_postzl_partial_launch = 205
DB_PERF_SEL_postzl_full_launch = 206
DB_PERF_SEL_postzl_partial_waiting = 207
DB_PERF_SEL_postzl_tile_mem_stall = 208
DB_PERF_SEL_postzl_tile_init_stall = 209
DB_PERF_SEL_prezl_tile_mem_stall = 210
DB_PERF_SEL_prezl_tile_init_stall = 211
DB_PERF_SEL_dtt_sm_clash_stall = 212
DB_PERF_SEL_dtt_sm_slot_stall = 213
DB_PERF_SEL_dtt_sm_miss_stall = 214
DB_PERF_SEL_mi_rdreq_busy = 215
DB_PERF_SEL_mi_rdreq_stall = 216
DB_PERF_SEL_mi_wrreq_busy = 217
DB_PERF_SEL_mi_wrreq_stall = 218
DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219
DB_PERF_SEL_dkg_tile_rate_tile = 220
DB_PERF_SEL_prezl_src_in_sends = 221
DB_PERF_SEL_prezl_src_in_stall = 222
DB_PERF_SEL_prezl_src_in_squads = 223
DB_PERF_SEL_prezl_src_in_squads_unrolled = 224
DB_PERF_SEL_prezl_src_in_tile_rate = 225
DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226
DB_PERF_SEL_prezl_src_out_stall = 227
DB_PERF_SEL_postzl_src_in_sends = 228
DB_PERF_SEL_postzl_src_in_stall = 229
DB_PERF_SEL_postzl_src_in_squads = 230
DB_PERF_SEL_postzl_src_in_squads_unrolled = 231
DB_PERF_SEL_postzl_src_in_tile_rate = 232
DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233
DB_PERF_SEL_postzl_src_out_stall = 234
DB_PERF_SEL_esr_ps_src_in_sends = 235
DB_PERF_SEL_esr_ps_src_in_stall = 236
DB_PERF_SEL_esr_ps_src_in_squads = 237
DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238
DB_PERF_SEL_esr_ps_src_in_tile_rate = 239
DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240
DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241
DB_PERF_SEL_esr_ps_src_out_stall = 242
DB_PERF_SEL_depth_bounds_tile_culled = 243
DB_PERF_SEL_PreZ_Samples_failing_DB = 244
DB_PERF_SEL_PostZ_Samples_failing_DB = 245
DB_PERF_SEL_flush_compressed = 246
DB_PERF_SEL_flush_plane_le4 = 247
DB_PERF_SEL_tiles_z_fully_summarized = 248
DB_PERF_SEL_tiles_stencil_fully_summarized = 249
DB_PERF_SEL_tiles_z_clear_on_expclear = 250
DB_PERF_SEL_tiles_s_clear_on_expclear = 251
DB_PERF_SEL_tiles_decomp_on_expclear = 252
DB_PERF_SEL_tiles_compressed_to_decompressed = 253
DB_PERF_SEL_Op_Pipe_Prez_Busy = 254
DB_PERF_SEL_Op_Pipe_Postz_Busy = 255
DB_PERF_SEL_di_dt_stall = 256
Spare_257 = 257
DB_PERF_SEL_DB_SC_s_tile_rate = 258
DB_PERF_SEL_DB_SC_c_tile_rate = 259
DB_PERF_SEL_DB_SC_z_tile_rate = 260
DB_PERF_SEL_DB_CB_lquad_export_quads = 261
DB_PERF_SEL_DB_CB_lquad_double_format = 262
DB_PERF_SEL_DB_CB_lquad_fast_format = 263
DB_PERF_SEL_DB_CB_lquad_slow_format = 264
DB_PERF_SEL_CB_DB_rdreq_sends = 265
DB_PERF_SEL_CB_DB_rdreq_prt_sends = 266
DB_PERF_SEL_CB_DB_wrreq_sends = 267
DB_PERF_SEL_CB_DB_wrreq_prt_sends = 268
DB_PERF_SEL_DB_CB_rdret_ack = 269
DB_PERF_SEL_DB_CB_rdret_nack = 270
DB_PERF_SEL_DB_CB_wrret_ack = 271
DB_PERF_SEL_DB_CB_wrret_nack = 272
DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 273
DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 274
DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 275
DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 276
DB_PERF_SEL_unmapped_z_tile_culled = 277
DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 278
DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 279
DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 280
DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 281
DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 282
DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 283
DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 284
DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 285
DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 286
DB_PERF_SEL_DB_CB_context_dones = 287
DB_PERF_SEL_DB_CB_eop_dones = 288
DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 289
DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 290
DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 291
DB_PERF_SEL_SC_DB_tile_backface = 292
DB_PERF_SEL_SC_DB_quad_quads = 293
DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 294
DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 295
DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 296
DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 297
DB_PERF_SEL_DB_SC_quad_double_quad = 298
DB_PERF_SEL_SX_DB_quad_export_quads = 299
DB_PERF_SEL_SX_DB_quad_double_format = 300
DB_PERF_SEL_SX_DB_quad_fast_format = 301
DB_PERF_SEL_SX_DB_quad_slow_format = 302
DB_PERF_SEL_quad_rd_sends_unc = 303
DB_PERF_SEL_quad_rd_mi_stall_unc = 304
DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 305
DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 306
DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 307
DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 308
DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 309
DB_PERF_SEL_noz_waiting_for_postz_done = 310
DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1 = 311
DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1 = 312
DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2 = 313
DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2 = 314
DB_PERF_SEL_RMI_rd_tile_32byte_req = 315
DB_PERF_SEL_RMI_rd_z_32byte_req = 316
DB_PERF_SEL_RMI_rd_s_32byte_req = 317
DB_PERF_SEL_RMI_wr_tile_32byte_req = 318
DB_PERF_SEL_RMI_wr_z_32byte_req = 319
DB_PERF_SEL_RMI_wr_s_32byte_req = 320
DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 321
DB_PERF_SEL_RMI_rd_tile_32byte_ret = 322
DB_PERF_SEL_RMI_rd_z_32byte_ret = 323
DB_PERF_SEL_RMI_rd_s_32byte_ret = 324
DB_PERF_SEL_RMI_wr_tile_32byte_ack = 325
DB_PERF_SEL_RMI_wr_z_32byte_ack = 326
DB_PERF_SEL_RMI_wr_s_32byte_ack = 327
DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 328
DB_PERF_SEL_esr_vic_sqq_busy = 329
DB_PERF_SEL_esr_vic_sqq_stall = 330
DB_PERF_SEL_esr_psi_vic_tile_rate = 331
DB_PERF_SEL_esr_vic_footprint_match_2x2 = 332
DB_PERF_SEL_esr_vic_footprint_match_2x1 = 333
DB_PERF_SEL_esr_vic_footprint_match_1x2 = 334
DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 335
DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 336
DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 337
DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 338
DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 339
DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 340
DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 341
DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 342
DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 343
DB_PERF_SEL_ts_events_pws_enable = 344
DB_PERF_SEL_ps_events_pws_enable = 345
DB_PERF_SEL_cs_events_pws_enable = 346
DB_PERF_SEL_DB_SC_quad_noz_tiles = 347
DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 348
PerfCounter_Vals = ctypes.c_uint32 # enum
# values for enumeration 'PixelPipeCounterId'
PixelPipeCounterId__enumvalues = {
0: 'PIXEL_PIPE_OCCLUSION_COUNT_0',
1: 'PIXEL_PIPE_OCCLUSION_COUNT_1',
2: 'PIXEL_PIPE_OCCLUSION_COUNT_2',
3: 'PIXEL_PIPE_OCCLUSION_COUNT_3',
4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0',
5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0',
6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1',
7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1',
}
PIXEL_PIPE_OCCLUSION_COUNT_0 = 0
PIXEL_PIPE_OCCLUSION_COUNT_1 = 1
PIXEL_PIPE_OCCLUSION_COUNT_2 = 2
PIXEL_PIPE_OCCLUSION_COUNT_3 = 3
PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4
PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5
PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6
PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7
PixelPipeCounterId = ctypes.c_uint32 # enum
# values for enumeration 'PixelPipeStride'
PixelPipeStride__enumvalues = {
0: 'PIXEL_PIPE_STRIDE_32_BITS',
1: 'PIXEL_PIPE_STRIDE_64_BITS',
2: 'PIXEL_PIPE_STRIDE_128_BITS',
3: 'PIXEL_PIPE_STRIDE_256_BITS',
}
PIXEL_PIPE_STRIDE_32_BITS = 0
PIXEL_PIPE_STRIDE_64_BITS = 1
PIXEL_PIPE_STRIDE_128_BITS = 2
PIXEL_PIPE_STRIDE_256_BITS = 3
PixelPipeStride = ctypes.c_uint32 # enum
# values for enumeration 'RingCounterControl'
RingCounterControl__enumvalues = {
0: 'COUNTER_RING_SPLIT',
1: 'COUNTER_RING_0',
2: 'COUNTER_RING_1',
}
COUNTER_RING_SPLIT = 0
COUNTER_RING_0 = 1
COUNTER_RING_1 = 2
RingCounterControl = ctypes.c_uint32 # enum
# values for enumeration 'StencilOp'
StencilOp__enumvalues = {
0: 'STENCIL_KEEP',
1: 'STENCIL_ZERO',
2: 'STENCIL_ONES',
3: 'STENCIL_REPLACE_TEST',
4: 'STENCIL_REPLACE_OP',
5: 'STENCIL_ADD_CLAMP',
6: 'STENCIL_SUB_CLAMP',
7: 'STENCIL_INVERT',
8: 'STENCIL_ADD_WRAP',
9: 'STENCIL_SUB_WRAP',
10: 'STENCIL_AND',
11: 'STENCIL_OR',
12: 'STENCIL_XOR',
13: 'STENCIL_NAND',
14: 'STENCIL_NOR',
15: 'STENCIL_XNOR',
}
STENCIL_KEEP = 0
STENCIL_ZERO = 1
STENCIL_ONES = 2
STENCIL_REPLACE_TEST = 3
STENCIL_REPLACE_OP = 4
STENCIL_ADD_CLAMP = 5
STENCIL_SUB_CLAMP = 6
STENCIL_INVERT = 7
STENCIL_ADD_WRAP = 8
STENCIL_SUB_WRAP = 9
STENCIL_AND = 10
STENCIL_OR = 11
STENCIL_XOR = 12
STENCIL_NAND = 13
STENCIL_NOR = 14
STENCIL_XNOR = 15
StencilOp = ctypes.c_uint32 # enum
# values for enumeration 'ZLimitSumm'
ZLimitSumm__enumvalues = {
0: 'FORCE_SUMM_OFF',
1: 'FORCE_SUMM_MINZ',
2: 'FORCE_SUMM_MAXZ',
3: 'FORCE_SUMM_BOTH',
}
FORCE_SUMM_OFF = 0
FORCE_SUMM_MINZ = 1
FORCE_SUMM_MAXZ = 2
FORCE_SUMM_BOTH = 3
ZLimitSumm = ctypes.c_uint32 # enum
# values for enumeration 'ZModeForce'
ZModeForce__enumvalues = {
0: 'NO_FORCE',
1: 'FORCE_EARLY_Z',
2: 'FORCE_LATE_Z',
3: 'FORCE_RE_Z',
}
NO_FORCE = 0
FORCE_EARLY_Z = 1
FORCE_LATE_Z = 2
FORCE_RE_Z = 3
ZModeForce = ctypes.c_uint32 # enum
# values for enumeration 'ZOrder'
ZOrder__enumvalues = {
0: 'LATE_Z',
1: 'EARLY_Z_THEN_LATE_Z',
2: 'RE_Z',
3: 'EARLY_Z_THEN_RE_Z',
}
LATE_Z = 0
EARLY_Z_THEN_LATE_Z = 1
RE_Z = 2
EARLY_Z_THEN_RE_Z = 3
ZOrder = ctypes.c_uint32 # enum
# values for enumeration 'ZSamplePosition'
ZSamplePosition__enumvalues = {
0: 'Z_SAMPLE_CENTER',
1: 'Z_SAMPLE_CENTROID',
}
Z_SAMPLE_CENTER = 0
Z_SAMPLE_CENTROID = 1
ZSamplePosition = ctypes.c_uint32 # enum
# values for enumeration 'ZpassControl'
ZpassControl__enumvalues = {
0: 'ZPASS_DISABLE',
1: 'ZPASS_SAMPLES',
2: 'ZPASS_PIXELS',
}
ZPASS_DISABLE = 0
ZPASS_SAMPLES = 1
ZPASS_PIXELS = 2
ZpassControl = ctypes.c_uint32 # enum
# values for enumeration 'SU_PERFCNT_SEL'
SU_PERFCNT_SEL__enumvalues = {
0: 'PERF_PAPC_PASX_REQ',
1: 'PERF_PAPC_PASX_DISABLE_PIPE',
2: 'PERF_PAPC_PASX_FIRST_VECTOR',
3: 'PERF_PAPC_PASX_SECOND_VECTOR',
4: 'PERF_PAPC_PASX_FIRST_DEAD',
5: 'PERF_PAPC_PASX_SECOND_DEAD',
6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD',
7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD',
8: 'PERF_PAPC_PA_INPUT_PRIM',
9: 'PERF_PAPC_PA_INPUT_NULL_PRIM',
10: 'PERF_PAPC_PA_INPUT_EVENT_FLAG',
11: 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT',
12: 'PERF_PAPC_PA_INPUT_END_OF_PACKET',
13: 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT',
14: 'PERF_PAPC_CLPR_CULL_PRIM',
15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM',
16: 'PERF_PAPC_CLPR_VV_CULL_PRIM',
17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM',
18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM',
19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM',
20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM',
21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM',
22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM',
23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM',
24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE',
25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1',
26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2',
27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3',
28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4',
29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8',
30: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12',
31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR',
32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR',
33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT',
34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT',
35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP',
36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM',
37: 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM',
38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM',
39: 'PERF_PAPC_CLSM_NULL_PRIM',
40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM',
41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM',
42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1',
43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2',
44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3',
45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4',
46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8',
47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13',
48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM',
49: 'PERF_PAPC_SU_INPUT_PRIM',
50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM',
51: 'PERF_PAPC_SU_INPUT_NULL_PRIM',
52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL',
53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL',
54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM',
55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM',
56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM',
57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL',
58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL',
59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL',
60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL',
61: 'PERF_PAPC_SU_OUTPUT_PRIM',
62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM',
63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM',
64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG',
65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT',
66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET',
67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE',
68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK',
69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT',
70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE',
71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK',
72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT',
73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL',
74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL',
75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL',
76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL',
77: 'PERF_PAPC_PASX_REQ_IDLE',
78: 'PERF_PAPC_PASX_REQ_BUSY',
79: 'PERF_PAPC_PASX_REQ_STALLED',
80: 'PERF_PAPC_PASX_REC_IDLE',
81: 'PERF_PAPC_PASX_REC_BUSY',
82: 'PERF_PAPC_PASX_REC_STARVED_SX',
83: 'PERF_PAPC_PASX_REC_STALLED',
84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM',
85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN',
86: 'PERF_PAPC_CCGSM_IDLE',
87: 'PERF_PAPC_CCGSM_BUSY',
88: 'PERF_PAPC_CCGSM_STALLED',
89: 'PERF_PAPC_CLPRIM_IDLE',
90: 'PERF_PAPC_CLPRIM_BUSY',
91: 'PERF_PAPC_CLPRIM_STALLED',
92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM',
93: 'PERF_PAPC_CLIPSM_IDLE',
94: 'PERF_PAPC_CLIPSM_BUSY',
95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH',
96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ',
97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA',
98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP',
99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM',
100: 'PERF_PAPC_CLIPGA_IDLE',
101: 'PERF_PAPC_CLIPGA_BUSY',
102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP',
103: 'PERF_PAPC_CLIPGA_STALLED',
104: 'PERF_PAPC_CLIP_IDLE',
105: 'PERF_PAPC_CLIP_BUSY',
106: 'PERF_PAPC_SU_IDLE',
107: 'PERF_PAPC_SU_BUSY',
108: 'PERF_PAPC_SU_STARVED_CLIP',
109: 'PERF_PAPC_SU_STALLED_SC',
110: 'PERF_PAPC_CL_DYN_SCLK_VLD',
111: 'PERF_PAPC_SU_DYN_SCLK_VLD',
112: 'PERF_PAPC_PA_REG_SCLK_VLD',
113: 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL',
114: 'PERF_PAPC_PASX_SE0_REQ',
115: 'PERF_PAPC_PASX_SE1_REQ',
116: 'PERF_PAPC_PASX_SE0_FIRST_VECTOR',
117: 'PERF_PAPC_PASX_SE0_SECOND_VECTOR',
118: 'PERF_PAPC_PASX_SE1_FIRST_VECTOR',
119: 'PERF_PAPC_PASX_SE1_SECOND_VECTOR',
120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL',
121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL',
122: 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL',
123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM',
124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM',
125: 'PERF_PAPC_SU_SE01_OUTPUT_PRIM',
126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM',
127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM',
128: 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM',
129: 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT',
130: 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT',
131: 'PERF_PAPC_SU_SE0_STALLED_SC',
132: 'PERF_PAPC_SU_SE1_STALLED_SC',
133: 'PERF_PAPC_SU_SE01_STALLED_SC',
134: 'PERF_PAPC_CLSM_CLIPPING_PRIM',
135: 'PERF_PAPC_SU_CULLED_PRIM',
136: 'PERF_PAPC_SU_OUTPUT_EOPG',
137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL',
138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL',
139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM',
140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM',
141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM',
142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM',
143: 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET',
144: 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET',
145: 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET',
146: 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET',
147: 'PERF_PAPC_SU_SE0_OUTPUT_EOPG',
148: 'PERF_PAPC_SU_SE1_OUTPUT_EOPG',
149: 'PERF_PAPC_SU_SE2_OUTPUT_EOPG',
150: 'PERF_PAPC_SU_SE3_OUTPUT_EOPG',
151: 'PERF_PAPC_SU_SE2_STALLED_SC',
152: 'PERF_PAPC_SU_SE3_STALLED_SC',
153: 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT',
154: 'PERF_SMALL_PRIM_CULL_PRIM_1X1',
155: 'PERF_SMALL_PRIM_CULL_PRIM_2X1',
156: 'PERF_SMALL_PRIM_CULL_PRIM_1X2',
157: 'PERF_SMALL_PRIM_CULL_PRIM_2X2',
158: 'PERF_SMALL_PRIM_CULL_PRIM_3X1',
159: 'PERF_SMALL_PRIM_CULL_PRIM_1X3',
160: 'PERF_SMALL_PRIM_CULL_PRIM_3X2',
161: 'PERF_SMALL_PRIM_CULL_PRIM_2X3',
162: 'PERF_SMALL_PRIM_CULL_PRIM_NX1',
163: 'PERF_SMALL_PRIM_CULL_PRIM_1XN',
164: 'PERF_SMALL_PRIM_CULL_PRIM_NX2',
165: 'PERF_SMALL_PRIM_CULL_PRIM_2XN',
166: 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT',
167: 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT',
168: 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT',
170: 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT',
171: 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT',
172: 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT',
173: 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT',
174: 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT',
175: 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT',
176: 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT',
177: 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT',
179: 'PERF_PA_VERTEX_FIFO_FULL',
180: 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL',
182: 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL',
183: 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL',
185: 'PERF_PA_PIPE0_SWITCHED_GEN',
186: 'PERF_PA_PIPE1_SWITCHED_GEN',
188: 'PERF_ENGG_CSB_MACHINE_IS_STARVED',
189: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY',
190: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI',
191: 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL',
192: 'PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL',
193: 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL',
194: 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT',
195: 'PERF_ENGG_CSB_PRIM_COUNT_EQ0',
196: 'PERF_ENGG_CSB_NULL_SUBGROUP',
197: 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP',
198: 'PERF_ENGG_CSB_GE_MEMORY_FULL',
199: 'PERF_ENGG_CSB_GE_MEMORY_EMPTY',
200: 'PERF_ENGG_CSB_SPI_MEMORY_FULL',
201: 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY',
202: 'PERF_ENGG_CSB_DELAY_BIN00',
203: 'PERF_ENGG_CSB_DELAY_BIN01',
204: 'PERF_ENGG_CSB_DELAY_BIN02',
205: 'PERF_ENGG_CSB_DELAY_BIN03',
206: 'PERF_ENGG_CSB_DELAY_BIN04',
207: 'PERF_ENGG_CSB_DELAY_BIN05',
208: 'PERF_ENGG_CSB_DELAY_BIN06',
209: 'PERF_ENGG_CSB_DELAY_BIN07',
210: 'PERF_ENGG_CSB_DELAY_BIN08',
211: 'PERF_ENGG_CSB_DELAY_BIN09',
212: 'PERF_ENGG_CSB_DELAY_BIN10',
213: 'PERF_ENGG_CSB_DELAY_BIN11',
214: 'PERF_ENGG_CSB_DELAY_BIN12',
215: 'PERF_ENGG_CSB_DELAY_BIN13',
216: 'PERF_ENGG_CSB_DELAY_BIN14',
217: 'PERF_ENGG_CSB_DELAY_BIN15',
218: 'PERF_ENGG_CSB_SPI_DELAY_BIN00',
219: 'PERF_ENGG_CSB_SPI_DELAY_BIN01',
220: 'PERF_ENGG_CSB_SPI_DELAY_BIN02',
221: 'PERF_ENGG_CSB_SPI_DELAY_BIN03',
222: 'PERF_ENGG_CSB_SPI_DELAY_BIN04',
223: 'PERF_ENGG_CSB_SPI_DELAY_BIN05',
224: 'PERF_ENGG_CSB_SPI_DELAY_BIN06',
225: 'PERF_ENGG_CSB_SPI_DELAY_BIN07',
226: 'PERF_ENGG_CSB_SPI_DELAY_BIN08',
227: 'PERF_ENGG_CSB_SPI_DELAY_BIN09',
228: 'PERF_ENGG_CSB_SPI_DELAY_BIN10',
229: 'PERF_ENGG_INDEX_REQ_NULL_REQUEST',
230: 'PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM',
231: 'PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM',
232: 'PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM',
233: 'PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM',
234: 'PERF_ENGG_INDEX_REQ_STARVED',
235: 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL',
236: 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL',
237: 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS',
238: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL',
239: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY',
240: 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL',
241: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB',
242: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS',
243: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO',
244: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO',
245: 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT',
246: 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP',
247: 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0',
248: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL',
249: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL',
250: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL',
251: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL',
252: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL',
253: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL',
254: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL',
255: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL',
256: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL',
257: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL',
258: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS',
259: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS',
260: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS',
261: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS',
262: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS',
263: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO',
264: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO',
265: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB',
266: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM',
267: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE',
268: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE',
269: 'PERF_ENGG_POS_REQ_STARVED',
270: 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO',
271: 'PERF_ENGG_BUSY',
272: 'PERF_CLIPSM_CULL_PRIMS_CNT',
273: 'PERF_PH_SEND_1_SC',
274: 'PERF_PH_SEND_2_SC',
275: 'PERF_PH_SEND_3_SC',
276: 'PERF_PH_SEND_4_SC',
277: 'PERF_OUTPUT_PRIM_1_SC',
278: 'PERF_OUTPUT_PRIM_2_SC',
279: 'PERF_OUTPUT_PRIM_3_SC',
280: 'PERF_OUTPUT_PRIM_4_SC',
}
PERF_PAPC_PASX_REQ = 0
PERF_PAPC_PASX_DISABLE_PIPE = 1
PERF_PAPC_PASX_FIRST_VECTOR = 2
PERF_PAPC_PASX_SECOND_VECTOR = 3
PERF_PAPC_PASX_FIRST_DEAD = 4
PERF_PAPC_PASX_SECOND_DEAD = 5
PERF_PAPC_PASX_VTX_KILL_DISCARD = 6
PERF_PAPC_PASX_VTX_NAN_DISCARD = 7
PERF_PAPC_PA_INPUT_PRIM = 8
PERF_PAPC_PA_INPUT_NULL_PRIM = 9
PERF_PAPC_PA_INPUT_EVENT_FLAG = 10
PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11
PERF_PAPC_PA_INPUT_END_OF_PACKET = 12
PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 13
PERF_PAPC_CLPR_CULL_PRIM = 14
PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15
PERF_PAPC_CLPR_VV_CULL_PRIM = 16
PERF_PAPC_CLPR_UCP_CULL_PRIM = 17
PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18
PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19
PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20
PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21
PERF_PAPC_CLPR_VV_CLIP_PRIM = 22
PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23
PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24
PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25
PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26
PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27
PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28
PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29
PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 30
PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31
PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32
PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33
PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34
PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35
PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36
PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 37
PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38
PERF_PAPC_CLSM_NULL_PRIM = 39
PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40
PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41
PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42
PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43
PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44
PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45
PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46
PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 47
PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48
PERF_PAPC_SU_INPUT_PRIM = 49
PERF_PAPC_SU_INPUT_CLIP_PRIM = 50
PERF_PAPC_SU_INPUT_NULL_PRIM = 51
PERF_PAPC_SU_INPUT_PRIM_DUAL = 52
PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53
PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54
PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55
PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56
PERF_PAPC_SU_POLYMODE_FACE_CULL = 57
PERF_PAPC_SU_POLYMODE_BACK_CULL = 58
PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59
PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60
PERF_PAPC_SU_OUTPUT_PRIM = 61
PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62
PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63
PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64
PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65
PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66
PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67
PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68
PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69
PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70
PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71
PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72
PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73
PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74
PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75
PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76
PERF_PAPC_PASX_REQ_IDLE = 77
PERF_PAPC_PASX_REQ_BUSY = 78
PERF_PAPC_PASX_REQ_STALLED = 79
PERF_PAPC_PASX_REC_IDLE = 80
PERF_PAPC_PASX_REC_BUSY = 81
PERF_PAPC_PASX_REC_STARVED_SX = 82
PERF_PAPC_PASX_REC_STALLED = 83
PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84
PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85
PERF_PAPC_CCGSM_IDLE = 86
PERF_PAPC_CCGSM_BUSY = 87
PERF_PAPC_CCGSM_STALLED = 88
PERF_PAPC_CLPRIM_IDLE = 89
PERF_PAPC_CLPRIM_BUSY = 90
PERF_PAPC_CLPRIM_STALLED = 91
PERF_PAPC_CLPRIM_STARVED_CCGSM = 92
PERF_PAPC_CLIPSM_IDLE = 93
PERF_PAPC_CLIPSM_BUSY = 94
PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95
PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96
PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97
PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98
PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99
PERF_PAPC_CLIPGA_IDLE = 100
PERF_PAPC_CLIPGA_BUSY = 101
PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102
PERF_PAPC_CLIPGA_STALLED = 103
PERF_PAPC_CLIP_IDLE = 104
PERF_PAPC_CLIP_BUSY = 105
PERF_PAPC_SU_IDLE = 106
PERF_PAPC_SU_BUSY = 107
PERF_PAPC_SU_STARVED_CLIP = 108
PERF_PAPC_SU_STALLED_SC = 109
PERF_PAPC_CL_DYN_SCLK_VLD = 110
PERF_PAPC_SU_DYN_SCLK_VLD = 111
PERF_PAPC_PA_REG_SCLK_VLD = 112
PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 113
PERF_PAPC_PASX_SE0_REQ = 114
PERF_PAPC_PASX_SE1_REQ = 115
PERF_PAPC_PASX_SE0_FIRST_VECTOR = 116
PERF_PAPC_PASX_SE0_SECOND_VECTOR = 117
PERF_PAPC_PASX_SE1_FIRST_VECTOR = 118
PERF_PAPC_PASX_SE1_SECOND_VECTOR = 119
PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120
PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121
PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 122
PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123
PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124
PERF_PAPC_SU_SE01_OUTPUT_PRIM = 125
PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126
PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127
PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 128
PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 129
PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 130
PERF_PAPC_SU_SE0_STALLED_SC = 131
PERF_PAPC_SU_SE1_STALLED_SC = 132
PERF_PAPC_SU_SE01_STALLED_SC = 133
PERF_PAPC_CLSM_CLIPPING_PRIM = 134
PERF_PAPC_SU_CULLED_PRIM = 135
PERF_PAPC_SU_OUTPUT_EOPG = 136
PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137
PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138
PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139
PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140
PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141
PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142
PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 143
PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 144
PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 145
PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 146
PERF_PAPC_SU_SE0_OUTPUT_EOPG = 147
PERF_PAPC_SU_SE1_OUTPUT_EOPG = 148
PERF_PAPC_SU_SE2_OUTPUT_EOPG = 149
PERF_PAPC_SU_SE3_OUTPUT_EOPG = 150
PERF_PAPC_SU_SE2_STALLED_SC = 151
PERF_PAPC_SU_SE3_STALLED_SC = 152
PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 153
PERF_SMALL_PRIM_CULL_PRIM_1X1 = 154
PERF_SMALL_PRIM_CULL_PRIM_2X1 = 155
PERF_SMALL_PRIM_CULL_PRIM_1X2 = 156
PERF_SMALL_PRIM_CULL_PRIM_2X2 = 157
PERF_SMALL_PRIM_CULL_PRIM_3X1 = 158
PERF_SMALL_PRIM_CULL_PRIM_1X3 = 159
PERF_SMALL_PRIM_CULL_PRIM_3X2 = 160
PERF_SMALL_PRIM_CULL_PRIM_2X3 = 161
PERF_SMALL_PRIM_CULL_PRIM_NX1 = 162
PERF_SMALL_PRIM_CULL_PRIM_1XN = 163
PERF_SMALL_PRIM_CULL_PRIM_NX2 = 164
PERF_SMALL_PRIM_CULL_PRIM_2XN = 165
PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 166
PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 167
PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 168
PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 170
PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 171
PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 172
PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 173
PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 174
PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 175
PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 176
PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 177
PERF_PA_VERTEX_FIFO_FULL = 179
PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 180
PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 182
PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 183
PERF_PA_PIPE0_SWITCHED_GEN = 185
PERF_PA_PIPE1_SWITCHED_GEN = 186
PERF_ENGG_CSB_MACHINE_IS_STARVED = 188
PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 189
PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 190
PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 191
PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL = 192
PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 193
PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 194
PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 195
PERF_ENGG_CSB_NULL_SUBGROUP = 196
PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 197
PERF_ENGG_CSB_GE_MEMORY_FULL = 198
PERF_ENGG_CSB_GE_MEMORY_EMPTY = 199
PERF_ENGG_CSB_SPI_MEMORY_FULL = 200
PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 201
PERF_ENGG_CSB_DELAY_BIN00 = 202
PERF_ENGG_CSB_DELAY_BIN01 = 203
PERF_ENGG_CSB_DELAY_BIN02 = 204
PERF_ENGG_CSB_DELAY_BIN03 = 205
PERF_ENGG_CSB_DELAY_BIN04 = 206
PERF_ENGG_CSB_DELAY_BIN05 = 207
PERF_ENGG_CSB_DELAY_BIN06 = 208
PERF_ENGG_CSB_DELAY_BIN07 = 209
PERF_ENGG_CSB_DELAY_BIN08 = 210
PERF_ENGG_CSB_DELAY_BIN09 = 211
PERF_ENGG_CSB_DELAY_BIN10 = 212
PERF_ENGG_CSB_DELAY_BIN11 = 213
PERF_ENGG_CSB_DELAY_BIN12 = 214
PERF_ENGG_CSB_DELAY_BIN13 = 215
PERF_ENGG_CSB_DELAY_BIN14 = 216
PERF_ENGG_CSB_DELAY_BIN15 = 217
PERF_ENGG_CSB_SPI_DELAY_BIN00 = 218
PERF_ENGG_CSB_SPI_DELAY_BIN01 = 219
PERF_ENGG_CSB_SPI_DELAY_BIN02 = 220
PERF_ENGG_CSB_SPI_DELAY_BIN03 = 221
PERF_ENGG_CSB_SPI_DELAY_BIN04 = 222
PERF_ENGG_CSB_SPI_DELAY_BIN05 = 223
PERF_ENGG_CSB_SPI_DELAY_BIN06 = 224
PERF_ENGG_CSB_SPI_DELAY_BIN07 = 225
PERF_ENGG_CSB_SPI_DELAY_BIN08 = 226
PERF_ENGG_CSB_SPI_DELAY_BIN09 = 227
PERF_ENGG_CSB_SPI_DELAY_BIN10 = 228
PERF_ENGG_INDEX_REQ_NULL_REQUEST = 229
PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM = 230
PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM = 231
PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM = 232
PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM = 233
PERF_ENGG_INDEX_REQ_STARVED = 234
PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 235
PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 236
PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 237
PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 238
PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 239
PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 240
PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 241
PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 242
PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 243
PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 244
PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 245
PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 246
PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 247
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 248
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 249
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 250
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 251
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 252
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 253
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 254
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 255
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 256
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 257
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS = 258
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS = 259
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS = 260
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS = 261
PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS = 262
PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 263
PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 264
PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 265
PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 266
PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 267
PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 268
PERF_ENGG_POS_REQ_STARVED = 269
PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 270
PERF_ENGG_BUSY = 271
PERF_CLIPSM_CULL_PRIMS_CNT = 272
PERF_PH_SEND_1_SC = 273
PERF_PH_SEND_2_SC = 274
PERF_PH_SEND_3_SC = 275
PERF_PH_SEND_4_SC = 276
PERF_OUTPUT_PRIM_1_SC = 277
PERF_OUTPUT_PRIM_2_SC = 278
PERF_OUTPUT_PRIM_3_SC = 279
PERF_OUTPUT_PRIM_4_SC = 280
SU_PERFCNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PH_PERFCNT_SEL'
PH_PERFCNT_SEL__enumvalues = {
0: 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID',
1: 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
2: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES',
3: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
4: 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW',
5: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE',
6: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
7: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
8: 'PH_PERF_SEL_SC0_ARB_BUSY',
9: 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP',
10: 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP',
11: 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP',
12: 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE',
13: 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW',
14: 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM',
15: 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO',
16: 'PH_PERF_SEL_SC0_SEND',
17: 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND',
18: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX',
19: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND',
20: 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION',
21: 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION',
22: 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION',
23: 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
24: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD',
25: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE',
26: 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY',
27: 'PH_PERF_SEL_SC0_PA0_FIFO_FULL',
28: 'PH_PERF_SEL_SC0_PA0_NULL_WE',
29: 'PH_PERF_SEL_SC0_PA0_EVENT_WE',
30: 'PH_PERF_SEL_SC0_PA0_FPOV_WE',
31: 'PH_PERF_SEL_SC0_PA0_LPOV_WE',
32: 'PH_PERF_SEL_SC0_PA0_EOP_WE',
33: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD',
34: 'PH_PERF_SEL_SC0_PA0_EOPG_WE',
35: 'PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD',
36: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD',
37: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE',
38: 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY',
39: 'PH_PERF_SEL_SC0_PA1_FIFO_FULL',
40: 'PH_PERF_SEL_SC0_PA1_NULL_WE',
41: 'PH_PERF_SEL_SC0_PA1_EVENT_WE',
42: 'PH_PERF_SEL_SC0_PA1_FPOV_WE',
43: 'PH_PERF_SEL_SC0_PA1_LPOV_WE',
44: 'PH_PERF_SEL_SC0_PA1_EOP_WE',
45: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD',
46: 'PH_PERF_SEL_SC0_PA1_EOPG_WE',
47: 'PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD',
48: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD',
49: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE',
50: 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY',
51: 'PH_PERF_SEL_SC0_PA2_FIFO_FULL',
52: 'PH_PERF_SEL_SC0_PA2_NULL_WE',
53: 'PH_PERF_SEL_SC0_PA2_EVENT_WE',
54: 'PH_PERF_SEL_SC0_PA2_FPOV_WE',
55: 'PH_PERF_SEL_SC0_PA2_LPOV_WE',
56: 'PH_PERF_SEL_SC0_PA2_EOP_WE',
57: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD',
58: 'PH_PERF_SEL_SC0_PA2_EOPG_WE',
59: 'PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD',
60: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD',
61: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE',
62: 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY',
63: 'PH_PERF_SEL_SC0_PA3_FIFO_FULL',
64: 'PH_PERF_SEL_SC0_PA3_NULL_WE',
65: 'PH_PERF_SEL_SC0_PA3_EVENT_WE',
66: 'PH_PERF_SEL_SC0_PA3_FPOV_WE',
67: 'PH_PERF_SEL_SC0_PA3_LPOV_WE',
68: 'PH_PERF_SEL_SC0_PA3_EOP_WE',
69: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD',
70: 'PH_PERF_SEL_SC0_PA3_EOPG_WE',
71: 'PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD',
72: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD',
73: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE',
74: 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY',
75: 'PH_PERF_SEL_SC0_PA4_FIFO_FULL',
76: 'PH_PERF_SEL_SC0_PA4_NULL_WE',
77: 'PH_PERF_SEL_SC0_PA4_EVENT_WE',
78: 'PH_PERF_SEL_SC0_PA4_FPOV_WE',
79: 'PH_PERF_SEL_SC0_PA4_LPOV_WE',
80: 'PH_PERF_SEL_SC0_PA4_EOP_WE',
81: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD',
82: 'PH_PERF_SEL_SC0_PA4_EOPG_WE',
83: 'PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD',
84: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD',
85: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE',
86: 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY',
87: 'PH_PERF_SEL_SC0_PA5_FIFO_FULL',
88: 'PH_PERF_SEL_SC0_PA5_NULL_WE',
89: 'PH_PERF_SEL_SC0_PA5_EVENT_WE',
90: 'PH_PERF_SEL_SC0_PA5_FPOV_WE',
91: 'PH_PERF_SEL_SC0_PA5_LPOV_WE',
92: 'PH_PERF_SEL_SC0_PA5_EOP_WE',
93: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD',
94: 'PH_PERF_SEL_SC0_PA5_EOPG_WE',
95: 'PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD',
96: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD',
97: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE',
98: 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY',
99: 'PH_PERF_SEL_SC0_PA6_FIFO_FULL',
100: 'PH_PERF_SEL_SC0_PA6_NULL_WE',
101: 'PH_PERF_SEL_SC0_PA6_EVENT_WE',
102: 'PH_PERF_SEL_SC0_PA6_FPOV_WE',
103: 'PH_PERF_SEL_SC0_PA6_LPOV_WE',
104: 'PH_PERF_SEL_SC0_PA6_EOP_WE',
105: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD',
106: 'PH_PERF_SEL_SC0_PA6_EOPG_WE',
107: 'PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD',
108: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD',
109: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE',
110: 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY',
111: 'PH_PERF_SEL_SC0_PA7_FIFO_FULL',
112: 'PH_PERF_SEL_SC0_PA7_NULL_WE',
113: 'PH_PERF_SEL_SC0_PA7_EVENT_WE',
114: 'PH_PERF_SEL_SC0_PA7_FPOV_WE',
115: 'PH_PERF_SEL_SC0_PA7_LPOV_WE',
116: 'PH_PERF_SEL_SC0_PA7_EOP_WE',
117: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD',
118: 'PH_PERF_SEL_SC0_PA7_EOPG_WE',
119: 'PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD',
120: 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID',
121: 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
122: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES',
123: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
124: 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW',
125: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE',
126: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
127: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
128: 'PH_PERF_SEL_SC1_ARB_BUSY',
129: 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP',
130: 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP',
131: 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP',
132: 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE',
133: 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW',
134: 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM',
135: 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO',
136: 'PH_PERF_SEL_SC1_SEND',
137: 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND',
138: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX',
139: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND',
140: 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION',
141: 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION',
142: 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
143: 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
144: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD',
145: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE',
146: 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY',
147: 'PH_PERF_SEL_SC1_PA0_FIFO_FULL',
148: 'PH_PERF_SEL_SC1_PA0_NULL_WE',
149: 'PH_PERF_SEL_SC1_PA0_EVENT_WE',
150: 'PH_PERF_SEL_SC1_PA0_FPOV_WE',
151: 'PH_PERF_SEL_SC1_PA0_LPOV_WE',
152: 'PH_PERF_SEL_SC1_PA0_EOP_WE',
153: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD',
154: 'PH_PERF_SEL_SC1_PA0_EOPG_WE',
155: 'PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD',
156: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD',
157: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE',
158: 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY',
159: 'PH_PERF_SEL_SC1_PA1_FIFO_FULL',
160: 'PH_PERF_SEL_SC1_PA1_NULL_WE',
161: 'PH_PERF_SEL_SC1_PA1_EVENT_WE',
162: 'PH_PERF_SEL_SC1_PA1_FPOV_WE',
163: 'PH_PERF_SEL_SC1_PA1_LPOV_WE',
164: 'PH_PERF_SEL_SC1_PA1_EOP_WE',
165: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD',
166: 'PH_PERF_SEL_SC1_PA1_EOPG_WE',
167: 'PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD',
168: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD',
169: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE',
170: 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY',
171: 'PH_PERF_SEL_SC1_PA2_FIFO_FULL',
172: 'PH_PERF_SEL_SC1_PA2_NULL_WE',
173: 'PH_PERF_SEL_SC1_PA2_EVENT_WE',
174: 'PH_PERF_SEL_SC1_PA2_FPOV_WE',
175: 'PH_PERF_SEL_SC1_PA2_LPOV_WE',
176: 'PH_PERF_SEL_SC1_PA2_EOP_WE',
177: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD',
178: 'PH_PERF_SEL_SC1_PA2_EOPG_WE',
179: 'PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD',
180: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD',
181: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE',
182: 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY',
183: 'PH_PERF_SEL_SC1_PA3_FIFO_FULL',
184: 'PH_PERF_SEL_SC1_PA3_NULL_WE',
185: 'PH_PERF_SEL_SC1_PA3_EVENT_WE',
186: 'PH_PERF_SEL_SC1_PA3_FPOV_WE',
187: 'PH_PERF_SEL_SC1_PA3_LPOV_WE',
188: 'PH_PERF_SEL_SC1_PA3_EOP_WE',
189: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD',
190: 'PH_PERF_SEL_SC1_PA3_EOPG_WE',
191: 'PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD',
192: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD',
193: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE',
194: 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY',
195: 'PH_PERF_SEL_SC1_PA4_FIFO_FULL',
196: 'PH_PERF_SEL_SC1_PA4_NULL_WE',
197: 'PH_PERF_SEL_SC1_PA4_EVENT_WE',
198: 'PH_PERF_SEL_SC1_PA4_FPOV_WE',
199: 'PH_PERF_SEL_SC1_PA4_LPOV_WE',
200: 'PH_PERF_SEL_SC1_PA4_EOP_WE',
201: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD',
202: 'PH_PERF_SEL_SC1_PA4_EOPG_WE',
203: 'PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD',
204: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD',
205: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE',
206: 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY',
207: 'PH_PERF_SEL_SC1_PA5_FIFO_FULL',
208: 'PH_PERF_SEL_SC1_PA5_NULL_WE',
209: 'PH_PERF_SEL_SC1_PA5_EVENT_WE',
210: 'PH_PERF_SEL_SC1_PA5_FPOV_WE',
211: 'PH_PERF_SEL_SC1_PA5_LPOV_WE',
212: 'PH_PERF_SEL_SC1_PA5_EOP_WE',
213: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD',
214: 'PH_PERF_SEL_SC1_PA5_EOPG_WE',
215: 'PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD',
216: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD',
217: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE',
218: 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY',
219: 'PH_PERF_SEL_SC1_PA6_FIFO_FULL',
220: 'PH_PERF_SEL_SC1_PA6_NULL_WE',
221: 'PH_PERF_SEL_SC1_PA6_EVENT_WE',
222: 'PH_PERF_SEL_SC1_PA6_FPOV_WE',
223: 'PH_PERF_SEL_SC1_PA6_LPOV_WE',
224: 'PH_PERF_SEL_SC1_PA6_EOP_WE',
225: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD',
226: 'PH_PERF_SEL_SC1_PA6_EOPG_WE',
227: 'PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD',
228: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD',
229: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE',
230: 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY',
231: 'PH_PERF_SEL_SC1_PA7_FIFO_FULL',
232: 'PH_PERF_SEL_SC1_PA7_NULL_WE',
233: 'PH_PERF_SEL_SC1_PA7_EVENT_WE',
234: 'PH_PERF_SEL_SC1_PA7_FPOV_WE',
235: 'PH_PERF_SEL_SC1_PA7_LPOV_WE',
236: 'PH_PERF_SEL_SC1_PA7_EOP_WE',
237: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD',
238: 'PH_PERF_SEL_SC1_PA7_EOPG_WE',
239: 'PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD',
240: 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID',
241: 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
242: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES',
243: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
244: 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW',
245: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE',
246: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
247: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
248: 'PH_PERF_SEL_SC2_ARB_BUSY',
249: 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP',
250: 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP',
251: 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP',
252: 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE',
253: 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW',
254: 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM',
255: 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO',
256: 'PH_PERF_SEL_SC2_SEND',
257: 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND',
258: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX',
259: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND',
260: 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION',
261: 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION',
262: 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
263: 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
264: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD',
265: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE',
266: 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY',
267: 'PH_PERF_SEL_SC2_PA0_FIFO_FULL',
268: 'PH_PERF_SEL_SC2_PA0_NULL_WE',
269: 'PH_PERF_SEL_SC2_PA0_EVENT_WE',
270: 'PH_PERF_SEL_SC2_PA0_FPOV_WE',
271: 'PH_PERF_SEL_SC2_PA0_LPOV_WE',
272: 'PH_PERF_SEL_SC2_PA0_EOP_WE',
273: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD',
274: 'PH_PERF_SEL_SC2_PA0_EOPG_WE',
275: 'PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD',
276: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD',
277: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE',
278: 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY',
279: 'PH_PERF_SEL_SC2_PA1_FIFO_FULL',
280: 'PH_PERF_SEL_SC2_PA1_NULL_WE',
281: 'PH_PERF_SEL_SC2_PA1_EVENT_WE',
282: 'PH_PERF_SEL_SC2_PA1_FPOV_WE',
283: 'PH_PERF_SEL_SC2_PA1_LPOV_WE',
284: 'PH_PERF_SEL_SC2_PA1_EOP_WE',
285: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD',
286: 'PH_PERF_SEL_SC2_PA1_EOPG_WE',
287: 'PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD',
288: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD',
289: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE',
290: 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY',
291: 'PH_PERF_SEL_SC2_PA2_FIFO_FULL',
292: 'PH_PERF_SEL_SC2_PA2_NULL_WE',
293: 'PH_PERF_SEL_SC2_PA2_EVENT_WE',
294: 'PH_PERF_SEL_SC2_PA2_FPOV_WE',
295: 'PH_PERF_SEL_SC2_PA2_LPOV_WE',
296: 'PH_PERF_SEL_SC2_PA2_EOP_WE',
297: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD',
298: 'PH_PERF_SEL_SC2_PA2_EOPG_WE',
299: 'PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD',
300: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD',
301: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE',
302: 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY',
303: 'PH_PERF_SEL_SC2_PA3_FIFO_FULL',
304: 'PH_PERF_SEL_SC2_PA3_NULL_WE',
305: 'PH_PERF_SEL_SC2_PA3_EVENT_WE',
306: 'PH_PERF_SEL_SC2_PA3_FPOV_WE',
307: 'PH_PERF_SEL_SC2_PA3_LPOV_WE',
308: 'PH_PERF_SEL_SC2_PA3_EOP_WE',
309: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD',
310: 'PH_PERF_SEL_SC2_PA3_EOPG_WE',
311: 'PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD',
312: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD',
313: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE',
314: 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY',
315: 'PH_PERF_SEL_SC2_PA4_FIFO_FULL',
316: 'PH_PERF_SEL_SC2_PA4_NULL_WE',
317: 'PH_PERF_SEL_SC2_PA4_EVENT_WE',
318: 'PH_PERF_SEL_SC2_PA4_FPOV_WE',
319: 'PH_PERF_SEL_SC2_PA4_LPOV_WE',
320: 'PH_PERF_SEL_SC2_PA4_EOP_WE',
321: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD',
322: 'PH_PERF_SEL_SC2_PA4_EOPG_WE',
323: 'PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD',
324: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD',
325: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE',
326: 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY',
327: 'PH_PERF_SEL_SC2_PA5_FIFO_FULL',
328: 'PH_PERF_SEL_SC2_PA5_NULL_WE',
329: 'PH_PERF_SEL_SC2_PA5_EVENT_WE',
330: 'PH_PERF_SEL_SC2_PA5_FPOV_WE',
331: 'PH_PERF_SEL_SC2_PA5_LPOV_WE',
332: 'PH_PERF_SEL_SC2_PA5_EOP_WE',
333: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD',
334: 'PH_PERF_SEL_SC2_PA5_EOPG_WE',
335: 'PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD',
336: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD',
337: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE',
338: 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY',
339: 'PH_PERF_SEL_SC2_PA6_FIFO_FULL',
340: 'PH_PERF_SEL_SC2_PA6_NULL_WE',
341: 'PH_PERF_SEL_SC2_PA6_EVENT_WE',
342: 'PH_PERF_SEL_SC2_PA6_FPOV_WE',
343: 'PH_PERF_SEL_SC2_PA6_LPOV_WE',
344: 'PH_PERF_SEL_SC2_PA6_EOP_WE',
345: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD',
346: 'PH_PERF_SEL_SC2_PA6_EOPG_WE',
347: 'PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD',
348: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD',
349: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE',
350: 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY',
351: 'PH_PERF_SEL_SC2_PA7_FIFO_FULL',
352: 'PH_PERF_SEL_SC2_PA7_NULL_WE',
353: 'PH_PERF_SEL_SC2_PA7_EVENT_WE',
354: 'PH_PERF_SEL_SC2_PA7_FPOV_WE',
355: 'PH_PERF_SEL_SC2_PA7_LPOV_WE',
356: 'PH_PERF_SEL_SC2_PA7_EOP_WE',
357: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD',
358: 'PH_PERF_SEL_SC2_PA7_EOPG_WE',
359: 'PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD',
360: 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID',
361: 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
362: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES',
363: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
364: 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW',
365: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE',
366: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
367: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
368: 'PH_PERF_SEL_SC3_ARB_BUSY',
369: 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP',
370: 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP',
371: 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP',
372: 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE',
373: 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW',
374: 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM',
375: 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO',
376: 'PH_PERF_SEL_SC3_SEND',
377: 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND',
378: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX',
379: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND',
380: 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION',
381: 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION',
382: 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
383: 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
384: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD',
385: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE',
386: 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY',
387: 'PH_PERF_SEL_SC3_PA0_FIFO_FULL',
388: 'PH_PERF_SEL_SC3_PA0_NULL_WE',
389: 'PH_PERF_SEL_SC3_PA0_EVENT_WE',
390: 'PH_PERF_SEL_SC3_PA0_FPOV_WE',
391: 'PH_PERF_SEL_SC3_PA0_LPOV_WE',
392: 'PH_PERF_SEL_SC3_PA0_EOP_WE',
393: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD',
394: 'PH_PERF_SEL_SC3_PA0_EOPG_WE',
395: 'PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD',
396: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD',
397: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE',
398: 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY',
399: 'PH_PERF_SEL_SC3_PA1_FIFO_FULL',
400: 'PH_PERF_SEL_SC3_PA1_NULL_WE',
401: 'PH_PERF_SEL_SC3_PA1_EVENT_WE',
402: 'PH_PERF_SEL_SC3_PA1_FPOV_WE',
403: 'PH_PERF_SEL_SC3_PA1_LPOV_WE',
404: 'PH_PERF_SEL_SC3_PA1_EOP_WE',
405: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD',
406: 'PH_PERF_SEL_SC3_PA1_EOPG_WE',
407: 'PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD',
408: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD',
409: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE',
410: 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY',
411: 'PH_PERF_SEL_SC3_PA2_FIFO_FULL',
412: 'PH_PERF_SEL_SC3_PA2_NULL_WE',
413: 'PH_PERF_SEL_SC3_PA2_EVENT_WE',
414: 'PH_PERF_SEL_SC3_PA2_FPOV_WE',
415: 'PH_PERF_SEL_SC3_PA2_LPOV_WE',
416: 'PH_PERF_SEL_SC3_PA2_EOP_WE',
417: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD',
418: 'PH_PERF_SEL_SC3_PA2_EOPG_WE',
419: 'PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD',
420: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD',
421: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE',
422: 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY',
423: 'PH_PERF_SEL_SC3_PA3_FIFO_FULL',
424: 'PH_PERF_SEL_SC3_PA3_NULL_WE',
425: 'PH_PERF_SEL_SC3_PA3_EVENT_WE',
426: 'PH_PERF_SEL_SC3_PA3_FPOV_WE',
427: 'PH_PERF_SEL_SC3_PA3_LPOV_WE',
428: 'PH_PERF_SEL_SC3_PA3_EOP_WE',
429: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD',
430: 'PH_PERF_SEL_SC3_PA3_EOPG_WE',
431: 'PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD',
432: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD',
433: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE',
434: 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY',
435: 'PH_PERF_SEL_SC3_PA4_FIFO_FULL',
436: 'PH_PERF_SEL_SC3_PA4_NULL_WE',
437: 'PH_PERF_SEL_SC3_PA4_EVENT_WE',
438: 'PH_PERF_SEL_SC3_PA4_FPOV_WE',
439: 'PH_PERF_SEL_SC3_PA4_LPOV_WE',
440: 'PH_PERF_SEL_SC3_PA4_EOP_WE',
441: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD',
442: 'PH_PERF_SEL_SC3_PA4_EOPG_WE',
443: 'PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD',
444: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD',
445: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE',
446: 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY',
447: 'PH_PERF_SEL_SC3_PA5_FIFO_FULL',
448: 'PH_PERF_SEL_SC3_PA5_NULL_WE',
449: 'PH_PERF_SEL_SC3_PA5_EVENT_WE',
450: 'PH_PERF_SEL_SC3_PA5_FPOV_WE',
451: 'PH_PERF_SEL_SC3_PA5_LPOV_WE',
452: 'PH_PERF_SEL_SC3_PA5_EOP_WE',
453: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD',
454: 'PH_PERF_SEL_SC3_PA5_EOPG_WE',
455: 'PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD',
456: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD',
457: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE',
458: 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY',
459: 'PH_PERF_SEL_SC3_PA6_FIFO_FULL',
460: 'PH_PERF_SEL_SC3_PA6_NULL_WE',
461: 'PH_PERF_SEL_SC3_PA6_EVENT_WE',
462: 'PH_PERF_SEL_SC3_PA6_FPOV_WE',
463: 'PH_PERF_SEL_SC3_PA6_LPOV_WE',
464: 'PH_PERF_SEL_SC3_PA6_EOP_WE',
465: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD',
466: 'PH_PERF_SEL_SC3_PA6_EOPG_WE',
467: 'PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD',
468: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD',
469: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE',
470: 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY',
471: 'PH_PERF_SEL_SC3_PA7_FIFO_FULL',
472: 'PH_PERF_SEL_SC3_PA7_NULL_WE',
473: 'PH_PERF_SEL_SC3_PA7_EVENT_WE',
474: 'PH_PERF_SEL_SC3_PA7_FPOV_WE',
475: 'PH_PERF_SEL_SC3_PA7_LPOV_WE',
476: 'PH_PERF_SEL_SC3_PA7_EOP_WE',
477: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD',
478: 'PH_PERF_SEL_SC3_PA7_EOPG_WE',
479: 'PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD',
480: 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID',
481: 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
482: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES',
483: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
484: 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW',
485: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE',
486: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
487: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
488: 'PH_PERF_SEL_SC4_ARB_BUSY',
489: 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP',
490: 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP',
491: 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP',
492: 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE',
493: 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW',
494: 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM',
495: 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO',
496: 'PH_PERF_SEL_SC4_SEND',
497: 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND',
498: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX',
499: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND',
500: 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION',
501: 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION',
502: 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
503: 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
504: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD',
505: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE',
506: 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY',
507: 'PH_PERF_SEL_SC4_PA0_FIFO_FULL',
508: 'PH_PERF_SEL_SC4_PA0_NULL_WE',
509: 'PH_PERF_SEL_SC4_PA0_EVENT_WE',
510: 'PH_PERF_SEL_SC4_PA0_FPOV_WE',
511: 'PH_PERF_SEL_SC4_PA0_LPOV_WE',
512: 'PH_PERF_SEL_SC4_PA0_EOP_WE',
513: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD',
514: 'PH_PERF_SEL_SC4_PA0_EOPG_WE',
515: 'PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD',
516: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD',
517: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE',
518: 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY',
519: 'PH_PERF_SEL_SC4_PA1_FIFO_FULL',
520: 'PH_PERF_SEL_SC4_PA1_NULL_WE',
521: 'PH_PERF_SEL_SC4_PA1_EVENT_WE',
522: 'PH_PERF_SEL_SC4_PA1_FPOV_WE',
523: 'PH_PERF_SEL_SC4_PA1_LPOV_WE',
524: 'PH_PERF_SEL_SC4_PA1_EOP_WE',
525: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD',
526: 'PH_PERF_SEL_SC4_PA1_EOPG_WE',
527: 'PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD',
528: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD',
529: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE',
530: 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY',
531: 'PH_PERF_SEL_SC4_PA2_FIFO_FULL',
532: 'PH_PERF_SEL_SC4_PA2_NULL_WE',
533: 'PH_PERF_SEL_SC4_PA2_EVENT_WE',
534: 'PH_PERF_SEL_SC4_PA2_FPOV_WE',
535: 'PH_PERF_SEL_SC4_PA2_LPOV_WE',
536: 'PH_PERF_SEL_SC4_PA2_EOP_WE',
537: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD',
538: 'PH_PERF_SEL_SC4_PA2_EOPG_WE',
539: 'PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD',
540: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD',
541: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE',
542: 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY',
543: 'PH_PERF_SEL_SC4_PA3_FIFO_FULL',
544: 'PH_PERF_SEL_SC4_PA3_NULL_WE',
545: 'PH_PERF_SEL_SC4_PA3_EVENT_WE',
546: 'PH_PERF_SEL_SC4_PA3_FPOV_WE',
547: 'PH_PERF_SEL_SC4_PA3_LPOV_WE',
548: 'PH_PERF_SEL_SC4_PA3_EOP_WE',
549: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD',
550: 'PH_PERF_SEL_SC4_PA3_EOPG_WE',
551: 'PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD',
552: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD',
553: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE',
554: 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY',
555: 'PH_PERF_SEL_SC4_PA4_FIFO_FULL',
556: 'PH_PERF_SEL_SC4_PA4_NULL_WE',
557: 'PH_PERF_SEL_SC4_PA4_EVENT_WE',
558: 'PH_PERF_SEL_SC4_PA4_FPOV_WE',
559: 'PH_PERF_SEL_SC4_PA4_LPOV_WE',
560: 'PH_PERF_SEL_SC4_PA4_EOP_WE',
561: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD',
562: 'PH_PERF_SEL_SC4_PA4_EOPG_WE',
563: 'PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD',
564: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD',
565: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE',
566: 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY',
567: 'PH_PERF_SEL_SC4_PA5_FIFO_FULL',
568: 'PH_PERF_SEL_SC4_PA5_NULL_WE',
569: 'PH_PERF_SEL_SC4_PA5_EVENT_WE',
570: 'PH_PERF_SEL_SC4_PA5_FPOV_WE',
571: 'PH_PERF_SEL_SC4_PA5_LPOV_WE',
572: 'PH_PERF_SEL_SC4_PA5_EOP_WE',
573: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD',
574: 'PH_PERF_SEL_SC4_PA5_EOPG_WE',
575: 'PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD',
576: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD',
577: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE',
578: 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY',
579: 'PH_PERF_SEL_SC4_PA6_FIFO_FULL',
580: 'PH_PERF_SEL_SC4_PA6_NULL_WE',
581: 'PH_PERF_SEL_SC4_PA6_EVENT_WE',
582: 'PH_PERF_SEL_SC4_PA6_FPOV_WE',
583: 'PH_PERF_SEL_SC4_PA6_LPOV_WE',
584: 'PH_PERF_SEL_SC4_PA6_EOP_WE',
585: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD',
586: 'PH_PERF_SEL_SC4_PA6_EOPG_WE',
587: 'PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD',
588: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD',
589: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE',
590: 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY',
591: 'PH_PERF_SEL_SC4_PA7_FIFO_FULL',
592: 'PH_PERF_SEL_SC4_PA7_NULL_WE',
593: 'PH_PERF_SEL_SC4_PA7_EVENT_WE',
594: 'PH_PERF_SEL_SC4_PA7_FPOV_WE',
595: 'PH_PERF_SEL_SC4_PA7_LPOV_WE',
596: 'PH_PERF_SEL_SC4_PA7_EOP_WE',
597: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD',
598: 'PH_PERF_SEL_SC4_PA7_EOPG_WE',
599: 'PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD',
600: 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID',
601: 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
602: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES',
603: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
604: 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW',
605: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE',
606: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
607: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
608: 'PH_PERF_SEL_SC5_ARB_BUSY',
609: 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP',
610: 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP',
611: 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP',
612: 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE',
613: 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW',
614: 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM',
615: 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO',
616: 'PH_PERF_SEL_SC5_SEND',
617: 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND',
618: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX',
619: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND',
620: 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION',
621: 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION',
622: 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
623: 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
624: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD',
625: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE',
626: 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY',
627: 'PH_PERF_SEL_SC5_PA0_FIFO_FULL',
628: 'PH_PERF_SEL_SC5_PA0_NULL_WE',
629: 'PH_PERF_SEL_SC5_PA0_EVENT_WE',
630: 'PH_PERF_SEL_SC5_PA0_FPOV_WE',
631: 'PH_PERF_SEL_SC5_PA0_LPOV_WE',
632: 'PH_PERF_SEL_SC5_PA0_EOP_WE',
633: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD',
634: 'PH_PERF_SEL_SC5_PA0_EOPG_WE',
635: 'PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD',
636: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD',
637: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE',
638: 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY',
639: 'PH_PERF_SEL_SC5_PA1_FIFO_FULL',
640: 'PH_PERF_SEL_SC5_PA1_NULL_WE',
641: 'PH_PERF_SEL_SC5_PA1_EVENT_WE',
642: 'PH_PERF_SEL_SC5_PA1_FPOV_WE',
643: 'PH_PERF_SEL_SC5_PA1_LPOV_WE',
644: 'PH_PERF_SEL_SC5_PA1_EOP_WE',
645: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD',
646: 'PH_PERF_SEL_SC5_PA1_EOPG_WE',
647: 'PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD',
648: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD',
649: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE',
650: 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY',
651: 'PH_PERF_SEL_SC5_PA2_FIFO_FULL',
652: 'PH_PERF_SEL_SC5_PA2_NULL_WE',
653: 'PH_PERF_SEL_SC5_PA2_EVENT_WE',
654: 'PH_PERF_SEL_SC5_PA2_FPOV_WE',
655: 'PH_PERF_SEL_SC5_PA2_LPOV_WE',
656: 'PH_PERF_SEL_SC5_PA2_EOP_WE',
657: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD',
658: 'PH_PERF_SEL_SC5_PA2_EOPG_WE',
659: 'PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD',
660: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD',
661: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE',
662: 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY',
663: 'PH_PERF_SEL_SC5_PA3_FIFO_FULL',
664: 'PH_PERF_SEL_SC5_PA3_NULL_WE',
665: 'PH_PERF_SEL_SC5_PA3_EVENT_WE',
666: 'PH_PERF_SEL_SC5_PA3_FPOV_WE',
667: 'PH_PERF_SEL_SC5_PA3_LPOV_WE',
668: 'PH_PERF_SEL_SC5_PA3_EOP_WE',
669: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD',
670: 'PH_PERF_SEL_SC5_PA3_EOPG_WE',
671: 'PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD',
672: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD',
673: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE',
674: 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY',
675: 'PH_PERF_SEL_SC5_PA4_FIFO_FULL',
676: 'PH_PERF_SEL_SC5_PA4_NULL_WE',
677: 'PH_PERF_SEL_SC5_PA4_EVENT_WE',
678: 'PH_PERF_SEL_SC5_PA4_FPOV_WE',
679: 'PH_PERF_SEL_SC5_PA4_LPOV_WE',
680: 'PH_PERF_SEL_SC5_PA4_EOP_WE',
681: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD',
682: 'PH_PERF_SEL_SC5_PA4_EOPG_WE',
683: 'PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD',
684: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD',
685: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE',
686: 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY',
687: 'PH_PERF_SEL_SC5_PA5_FIFO_FULL',
688: 'PH_PERF_SEL_SC5_PA5_NULL_WE',
689: 'PH_PERF_SEL_SC5_PA5_EVENT_WE',
690: 'PH_PERF_SEL_SC5_PA5_FPOV_WE',
691: 'PH_PERF_SEL_SC5_PA5_LPOV_WE',
692: 'PH_PERF_SEL_SC5_PA5_EOP_WE',
693: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD',
694: 'PH_PERF_SEL_SC5_PA5_EOPG_WE',
695: 'PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD',
696: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD',
697: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE',
698: 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY',
699: 'PH_PERF_SEL_SC5_PA6_FIFO_FULL',
700: 'PH_PERF_SEL_SC5_PA6_NULL_WE',
701: 'PH_PERF_SEL_SC5_PA6_EVENT_WE',
702: 'PH_PERF_SEL_SC5_PA6_FPOV_WE',
703: 'PH_PERF_SEL_SC5_PA6_LPOV_WE',
704: 'PH_PERF_SEL_SC5_PA6_EOP_WE',
705: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD',
706: 'PH_PERF_SEL_SC5_PA6_EOPG_WE',
707: 'PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD',
708: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD',
709: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE',
710: 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY',
711: 'PH_PERF_SEL_SC5_PA7_FIFO_FULL',
712: 'PH_PERF_SEL_SC5_PA7_NULL_WE',
713: 'PH_PERF_SEL_SC5_PA7_EVENT_WE',
714: 'PH_PERF_SEL_SC5_PA7_FPOV_WE',
715: 'PH_PERF_SEL_SC5_PA7_LPOV_WE',
716: 'PH_PERF_SEL_SC5_PA7_EOP_WE',
717: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD',
718: 'PH_PERF_SEL_SC5_PA7_EOPG_WE',
719: 'PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD',
720: 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID',
721: 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
722: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES',
723: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
724: 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW',
725: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE',
726: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
727: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
728: 'PH_PERF_SEL_SC6_ARB_BUSY',
729: 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP',
730: 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP',
731: 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP',
732: 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE',
733: 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW',
734: 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM',
735: 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO',
736: 'PH_PERF_SEL_SC6_SEND',
737: 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND',
738: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX',
739: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND',
740: 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION',
741: 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION',
742: 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
743: 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
744: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD',
745: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE',
746: 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY',
747: 'PH_PERF_SEL_SC6_PA0_FIFO_FULL',
748: 'PH_PERF_SEL_SC6_PA0_NULL_WE',
749: 'PH_PERF_SEL_SC6_PA0_EVENT_WE',
750: 'PH_PERF_SEL_SC6_PA0_FPOV_WE',
751: 'PH_PERF_SEL_SC6_PA0_LPOV_WE',
752: 'PH_PERF_SEL_SC6_PA0_EOP_WE',
753: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD',
754: 'PH_PERF_SEL_SC6_PA0_EOPG_WE',
755: 'PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD',
756: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD',
757: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE',
758: 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY',
759: 'PH_PERF_SEL_SC6_PA1_FIFO_FULL',
760: 'PH_PERF_SEL_SC6_PA1_NULL_WE',
761: 'PH_PERF_SEL_SC6_PA1_EVENT_WE',
762: 'PH_PERF_SEL_SC6_PA1_FPOV_WE',
763: 'PH_PERF_SEL_SC6_PA1_LPOV_WE',
764: 'PH_PERF_SEL_SC6_PA1_EOP_WE',
765: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD',
766: 'PH_PERF_SEL_SC6_PA1_EOPG_WE',
767: 'PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD',
768: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD',
769: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE',
770: 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY',
771: 'PH_PERF_SEL_SC6_PA2_FIFO_FULL',
772: 'PH_PERF_SEL_SC6_PA2_NULL_WE',
773: 'PH_PERF_SEL_SC6_PA2_EVENT_WE',
774: 'PH_PERF_SEL_SC6_PA2_FPOV_WE',
775: 'PH_PERF_SEL_SC6_PA2_LPOV_WE',
776: 'PH_PERF_SEL_SC6_PA2_EOP_WE',
777: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD',
778: 'PH_PERF_SEL_SC6_PA2_EOPG_WE',
779: 'PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD',
780: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD',
781: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE',
782: 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY',
783: 'PH_PERF_SEL_SC6_PA3_FIFO_FULL',
784: 'PH_PERF_SEL_SC6_PA3_NULL_WE',
785: 'PH_PERF_SEL_SC6_PA3_EVENT_WE',
786: 'PH_PERF_SEL_SC6_PA3_FPOV_WE',
787: 'PH_PERF_SEL_SC6_PA3_LPOV_WE',
788: 'PH_PERF_SEL_SC6_PA3_EOP_WE',
789: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD',
790: 'PH_PERF_SEL_SC6_PA3_EOPG_WE',
791: 'PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD',
792: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD',
793: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE',
794: 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY',
795: 'PH_PERF_SEL_SC6_PA4_FIFO_FULL',
796: 'PH_PERF_SEL_SC6_PA4_NULL_WE',
797: 'PH_PERF_SEL_SC6_PA4_EVENT_WE',
798: 'PH_PERF_SEL_SC6_PA4_FPOV_WE',
799: 'PH_PERF_SEL_SC6_PA4_LPOV_WE',
800: 'PH_PERF_SEL_SC6_PA4_EOP_WE',
801: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD',
802: 'PH_PERF_SEL_SC6_PA4_EOPG_WE',
803: 'PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD',
804: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD',
805: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE',
806: 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY',
807: 'PH_PERF_SEL_SC6_PA5_FIFO_FULL',
808: 'PH_PERF_SEL_SC6_PA5_NULL_WE',
809: 'PH_PERF_SEL_SC6_PA5_EVENT_WE',
810: 'PH_PERF_SEL_SC6_PA5_FPOV_WE',
811: 'PH_PERF_SEL_SC6_PA5_LPOV_WE',
812: 'PH_PERF_SEL_SC6_PA5_EOP_WE',
813: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD',
814: 'PH_PERF_SEL_SC6_PA5_EOPG_WE',
815: 'PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD',
816: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD',
817: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE',
818: 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY',
819: 'PH_PERF_SEL_SC6_PA6_FIFO_FULL',
820: 'PH_PERF_SEL_SC6_PA6_NULL_WE',
821: 'PH_PERF_SEL_SC6_PA6_EVENT_WE',
822: 'PH_PERF_SEL_SC6_PA6_FPOV_WE',
823: 'PH_PERF_SEL_SC6_PA6_LPOV_WE',
824: 'PH_PERF_SEL_SC6_PA6_EOP_WE',
825: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD',
826: 'PH_PERF_SEL_SC6_PA6_EOPG_WE',
827: 'PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD',
828: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD',
829: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE',
830: 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY',
831: 'PH_PERF_SEL_SC6_PA7_FIFO_FULL',
832: 'PH_PERF_SEL_SC6_PA7_NULL_WE',
833: 'PH_PERF_SEL_SC6_PA7_EVENT_WE',
834: 'PH_PERF_SEL_SC6_PA7_FPOV_WE',
835: 'PH_PERF_SEL_SC6_PA7_LPOV_WE',
836: 'PH_PERF_SEL_SC6_PA7_EOP_WE',
837: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD',
838: 'PH_PERF_SEL_SC6_PA7_EOPG_WE',
839: 'PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD',
840: 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID',
841: 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
842: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES',
843: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
844: 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW',
845: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE',
846: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
847: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
848: 'PH_PERF_SEL_SC7_ARB_BUSY',
849: 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP',
850: 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP',
851: 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP',
852: 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE',
853: 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW',
854: 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM',
855: 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO',
856: 'PH_PERF_SEL_SC7_SEND',
857: 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND',
858: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX',
859: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND',
860: 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION',
861: 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION',
862: 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
863: 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
864: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD',
865: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE',
866: 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY',
867: 'PH_PERF_SEL_SC7_PA0_FIFO_FULL',
868: 'PH_PERF_SEL_SC7_PA0_NULL_WE',
869: 'PH_PERF_SEL_SC7_PA0_EVENT_WE',
870: 'PH_PERF_SEL_SC7_PA0_FPOV_WE',
871: 'PH_PERF_SEL_SC7_PA0_LPOV_WE',
872: 'PH_PERF_SEL_SC7_PA0_EOP_WE',
873: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD',
874: 'PH_PERF_SEL_SC7_PA0_EOPG_WE',
875: 'PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD',
876: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD',
877: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE',
878: 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY',
879: 'PH_PERF_SEL_SC7_PA1_FIFO_FULL',
880: 'PH_PERF_SEL_SC7_PA1_NULL_WE',
881: 'PH_PERF_SEL_SC7_PA1_EVENT_WE',
882: 'PH_PERF_SEL_SC7_PA1_FPOV_WE',
883: 'PH_PERF_SEL_SC7_PA1_LPOV_WE',
884: 'PH_PERF_SEL_SC7_PA1_EOP_WE',
885: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD',
886: 'PH_PERF_SEL_SC7_PA1_EOPG_WE',
887: 'PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD',
888: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD',
889: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE',
890: 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY',
891: 'PH_PERF_SEL_SC7_PA2_FIFO_FULL',
892: 'PH_PERF_SEL_SC7_PA2_NULL_WE',
893: 'PH_PERF_SEL_SC7_PA2_EVENT_WE',
894: 'PH_PERF_SEL_SC7_PA2_FPOV_WE',
895: 'PH_PERF_SEL_SC7_PA2_LPOV_WE',
896: 'PH_PERF_SEL_SC7_PA2_EOP_WE',
897: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD',
898: 'PH_PERF_SEL_SC7_PA2_EOPG_WE',
899: 'PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD',
900: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD',
901: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE',
902: 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY',
903: 'PH_PERF_SEL_SC7_PA3_FIFO_FULL',
904: 'PH_PERF_SEL_SC7_PA3_NULL_WE',
905: 'PH_PERF_SEL_SC7_PA3_EVENT_WE',
906: 'PH_PERF_SEL_SC7_PA3_FPOV_WE',
907: 'PH_PERF_SEL_SC7_PA3_LPOV_WE',
908: 'PH_PERF_SEL_SC7_PA3_EOP_WE',
909: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD',
910: 'PH_PERF_SEL_SC7_PA3_EOPG_WE',
911: 'PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD',
912: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD',
913: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE',
914: 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY',
915: 'PH_PERF_SEL_SC7_PA4_FIFO_FULL',
916: 'PH_PERF_SEL_SC7_PA4_NULL_WE',
917: 'PH_PERF_SEL_SC7_PA4_EVENT_WE',
918: 'PH_PERF_SEL_SC7_PA4_FPOV_WE',
919: 'PH_PERF_SEL_SC7_PA4_LPOV_WE',
920: 'PH_PERF_SEL_SC7_PA4_EOP_WE',
921: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD',
922: 'PH_PERF_SEL_SC7_PA4_EOPG_WE',
923: 'PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD',
924: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD',
925: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE',
926: 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY',
927: 'PH_PERF_SEL_SC7_PA5_FIFO_FULL',
928: 'PH_PERF_SEL_SC7_PA5_NULL_WE',
929: 'PH_PERF_SEL_SC7_PA5_EVENT_WE',
930: 'PH_PERF_SEL_SC7_PA5_FPOV_WE',
931: 'PH_PERF_SEL_SC7_PA5_LPOV_WE',
932: 'PH_PERF_SEL_SC7_PA5_EOP_WE',
933: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD',
934: 'PH_PERF_SEL_SC7_PA5_EOPG_WE',
935: 'PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD',
936: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD',
937: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE',
938: 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY',
939: 'PH_PERF_SEL_SC7_PA6_FIFO_FULL',
940: 'PH_PERF_SEL_SC7_PA6_NULL_WE',
941: 'PH_PERF_SEL_SC7_PA6_EVENT_WE',
942: 'PH_PERF_SEL_SC7_PA6_FPOV_WE',
943: 'PH_PERF_SEL_SC7_PA6_LPOV_WE',
944: 'PH_PERF_SEL_SC7_PA6_EOP_WE',
945: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD',
946: 'PH_PERF_SEL_SC7_PA6_EOPG_WE',
947: 'PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD',
948: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD',
949: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE',
950: 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY',
951: 'PH_PERF_SEL_SC7_PA7_FIFO_FULL',
952: 'PH_PERF_SEL_SC7_PA7_NULL_WE',
953: 'PH_PERF_SEL_SC7_PA7_EVENT_WE',
954: 'PH_PERF_SEL_SC7_PA7_FPOV_WE',
955: 'PH_PERF_SEL_SC7_PA7_LPOV_WE',
956: 'PH_PERF_SEL_SC7_PA7_EOP_WE',
957: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD',
958: 'PH_PERF_SEL_SC7_PA7_EOPG_WE',
959: 'PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD',
960: 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW',
961: 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW',
962: 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW',
963: 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW',
964: 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW',
965: 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW',
966: 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW',
967: 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW',
968: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE',
969: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE',
970: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE',
971: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE',
972: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE',
973: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE',
974: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE',
975: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE',
976: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
977: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
978: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
979: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
980: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
981: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
982: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
983: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
984: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
985: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
986: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
987: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
988: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
989: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
990: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
991: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
992: 'PH_PERF_SC0_FIFO_STATUS_0',
993: 'PH_PERF_SC0_FIFO_STATUS_1',
994: 'PH_PERF_SC0_FIFO_STATUS_2',
995: 'PH_PERF_SC0_FIFO_STATUS_3',
996: 'PH_PERF_SC1_FIFO_STATUS_0',
997: 'PH_PERF_SC1_FIFO_STATUS_1',
998: 'PH_PERF_SC1_FIFO_STATUS_2',
999: 'PH_PERF_SC1_FIFO_STATUS_3',
1000: 'PH_PERF_SC2_FIFO_STATUS_0',
1001: 'PH_PERF_SC2_FIFO_STATUS_1',
1002: 'PH_PERF_SC2_FIFO_STATUS_2',
1003: 'PH_PERF_SC2_FIFO_STATUS_3',
1004: 'PH_PERF_SC3_FIFO_STATUS_0',
1005: 'PH_PERF_SC3_FIFO_STATUS_1',
1006: 'PH_PERF_SC3_FIFO_STATUS_2',
1007: 'PH_PERF_SC3_FIFO_STATUS_3',
1008: 'PH_PERF_SC4_FIFO_STATUS_0',
1009: 'PH_PERF_SC4_FIFO_STATUS_1',
1010: 'PH_PERF_SC4_FIFO_STATUS_2',
1011: 'PH_PERF_SC4_FIFO_STATUS_3',
1012: 'PH_PERF_SC5_FIFO_STATUS_0',
1013: 'PH_PERF_SC5_FIFO_STATUS_1',
1014: 'PH_PERF_SC5_FIFO_STATUS_2',
1015: 'PH_PERF_SC5_FIFO_STATUS_3',
1016: 'PH_PERF_SC6_FIFO_STATUS_0',
1017: 'PH_PERF_SC6_FIFO_STATUS_1',
1018: 'PH_PERF_SC6_FIFO_STATUS_2',
1019: 'PH_PERF_SC6_FIFO_STATUS_3',
1020: 'PH_PERF_SC7_FIFO_STATUS_0',
1021: 'PH_PERF_SC7_FIFO_STATUS_1',
1022: 'PH_PERF_SC7_FIFO_STATUS_2',
1023: 'PH_PERF_SC7_FIFO_STATUS_3',
}
PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0
PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 1
PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 2
PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 3
PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 4
PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 5
PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 6
PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 7
PH_PERF_SEL_SC0_ARB_BUSY = 8
PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 9
PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 10
PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 11
PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 12
PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 13
PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 14
PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 15
PH_PERF_SEL_SC0_SEND = 16
PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 17
PH_PERF_SEL_SC0_CREDIT_AT_MAX = 18
PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 19
PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 20
PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 21
PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 22
PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 23
PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 24
PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 25
PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 26
PH_PERF_SEL_SC0_PA0_FIFO_FULL = 27
PH_PERF_SEL_SC0_PA0_NULL_WE = 28
PH_PERF_SEL_SC0_PA0_EVENT_WE = 29
PH_PERF_SEL_SC0_PA0_FPOV_WE = 30
PH_PERF_SEL_SC0_PA0_LPOV_WE = 31
PH_PERF_SEL_SC0_PA0_EOP_WE = 32
PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 33
PH_PERF_SEL_SC0_PA0_EOPG_WE = 34
PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD = 35
PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 36
PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 37
PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 38
PH_PERF_SEL_SC0_PA1_FIFO_FULL = 39
PH_PERF_SEL_SC0_PA1_NULL_WE = 40
PH_PERF_SEL_SC0_PA1_EVENT_WE = 41
PH_PERF_SEL_SC0_PA1_FPOV_WE = 42
PH_PERF_SEL_SC0_PA1_LPOV_WE = 43
PH_PERF_SEL_SC0_PA1_EOP_WE = 44
PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 45
PH_PERF_SEL_SC0_PA1_EOPG_WE = 46
PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD = 47
PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 48
PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 49
PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 50
PH_PERF_SEL_SC0_PA2_FIFO_FULL = 51
PH_PERF_SEL_SC0_PA2_NULL_WE = 52
PH_PERF_SEL_SC0_PA2_EVENT_WE = 53
PH_PERF_SEL_SC0_PA2_FPOV_WE = 54
PH_PERF_SEL_SC0_PA2_LPOV_WE = 55
PH_PERF_SEL_SC0_PA2_EOP_WE = 56
PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 57
PH_PERF_SEL_SC0_PA2_EOPG_WE = 58
PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD = 59
PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 60
PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 61
PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 62
PH_PERF_SEL_SC0_PA3_FIFO_FULL = 63
PH_PERF_SEL_SC0_PA3_NULL_WE = 64
PH_PERF_SEL_SC0_PA3_EVENT_WE = 65
PH_PERF_SEL_SC0_PA3_FPOV_WE = 66
PH_PERF_SEL_SC0_PA3_LPOV_WE = 67
PH_PERF_SEL_SC0_PA3_EOP_WE = 68
PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 69
PH_PERF_SEL_SC0_PA3_EOPG_WE = 70
PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD = 71
PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 72
PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 73
PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 74
PH_PERF_SEL_SC0_PA4_FIFO_FULL = 75
PH_PERF_SEL_SC0_PA4_NULL_WE = 76
PH_PERF_SEL_SC0_PA4_EVENT_WE = 77
PH_PERF_SEL_SC0_PA4_FPOV_WE = 78
PH_PERF_SEL_SC0_PA4_LPOV_WE = 79
PH_PERF_SEL_SC0_PA4_EOP_WE = 80
PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 81
PH_PERF_SEL_SC0_PA4_EOPG_WE = 82
PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD = 83
PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 84
PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 85
PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 86
PH_PERF_SEL_SC0_PA5_FIFO_FULL = 87
PH_PERF_SEL_SC0_PA5_NULL_WE = 88
PH_PERF_SEL_SC0_PA5_EVENT_WE = 89
PH_PERF_SEL_SC0_PA5_FPOV_WE = 90
PH_PERF_SEL_SC0_PA5_LPOV_WE = 91
PH_PERF_SEL_SC0_PA5_EOP_WE = 92
PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 93
PH_PERF_SEL_SC0_PA5_EOPG_WE = 94
PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD = 95
PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 96
PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 97
PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 98
PH_PERF_SEL_SC0_PA6_FIFO_FULL = 99
PH_PERF_SEL_SC0_PA6_NULL_WE = 100
PH_PERF_SEL_SC0_PA6_EVENT_WE = 101
PH_PERF_SEL_SC0_PA6_FPOV_WE = 102
PH_PERF_SEL_SC0_PA6_LPOV_WE = 103
PH_PERF_SEL_SC0_PA6_EOP_WE = 104
PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 105
PH_PERF_SEL_SC0_PA6_EOPG_WE = 106
PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD = 107
PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 108
PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 109
PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 110
PH_PERF_SEL_SC0_PA7_FIFO_FULL = 111
PH_PERF_SEL_SC0_PA7_NULL_WE = 112
PH_PERF_SEL_SC0_PA7_EVENT_WE = 113
PH_PERF_SEL_SC0_PA7_FPOV_WE = 114
PH_PERF_SEL_SC0_PA7_LPOV_WE = 115
PH_PERF_SEL_SC0_PA7_EOP_WE = 116
PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 117
PH_PERF_SEL_SC0_PA7_EOPG_WE = 118
PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD = 119
PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 120
PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 121
PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 122
PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 123
PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 124
PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 125
PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 126
PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 127
PH_PERF_SEL_SC1_ARB_BUSY = 128
PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 129
PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 130
PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 131
PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 132
PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 133
PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 134
PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 135
PH_PERF_SEL_SC1_SEND = 136
PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 137
PH_PERF_SEL_SC1_CREDIT_AT_MAX = 138
PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 139
PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 140
PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 141
PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 142
PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 143
PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 144
PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 145
PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 146
PH_PERF_SEL_SC1_PA0_FIFO_FULL = 147
PH_PERF_SEL_SC1_PA0_NULL_WE = 148
PH_PERF_SEL_SC1_PA0_EVENT_WE = 149
PH_PERF_SEL_SC1_PA0_FPOV_WE = 150
PH_PERF_SEL_SC1_PA0_LPOV_WE = 151
PH_PERF_SEL_SC1_PA0_EOP_WE = 152
PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 153
PH_PERF_SEL_SC1_PA0_EOPG_WE = 154
PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD = 155
PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 156
PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 157
PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 158
PH_PERF_SEL_SC1_PA1_FIFO_FULL = 159
PH_PERF_SEL_SC1_PA1_NULL_WE = 160
PH_PERF_SEL_SC1_PA1_EVENT_WE = 161
PH_PERF_SEL_SC1_PA1_FPOV_WE = 162
PH_PERF_SEL_SC1_PA1_LPOV_WE = 163
PH_PERF_SEL_SC1_PA1_EOP_WE = 164
PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 165
PH_PERF_SEL_SC1_PA1_EOPG_WE = 166
PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD = 167
PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 168
PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 169
PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 170
PH_PERF_SEL_SC1_PA2_FIFO_FULL = 171
PH_PERF_SEL_SC1_PA2_NULL_WE = 172
PH_PERF_SEL_SC1_PA2_EVENT_WE = 173
PH_PERF_SEL_SC1_PA2_FPOV_WE = 174
PH_PERF_SEL_SC1_PA2_LPOV_WE = 175
PH_PERF_SEL_SC1_PA2_EOP_WE = 176
PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 177
PH_PERF_SEL_SC1_PA2_EOPG_WE = 178
PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD = 179
PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 180
PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 181
PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 182
PH_PERF_SEL_SC1_PA3_FIFO_FULL = 183
PH_PERF_SEL_SC1_PA3_NULL_WE = 184
PH_PERF_SEL_SC1_PA3_EVENT_WE = 185
PH_PERF_SEL_SC1_PA3_FPOV_WE = 186
PH_PERF_SEL_SC1_PA3_LPOV_WE = 187
PH_PERF_SEL_SC1_PA3_EOP_WE = 188
PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 189
PH_PERF_SEL_SC1_PA3_EOPG_WE = 190
PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD = 191
PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 192
PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 193
PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 194
PH_PERF_SEL_SC1_PA4_FIFO_FULL = 195
PH_PERF_SEL_SC1_PA4_NULL_WE = 196
PH_PERF_SEL_SC1_PA4_EVENT_WE = 197
PH_PERF_SEL_SC1_PA4_FPOV_WE = 198
PH_PERF_SEL_SC1_PA4_LPOV_WE = 199
PH_PERF_SEL_SC1_PA4_EOP_WE = 200
PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 201
PH_PERF_SEL_SC1_PA4_EOPG_WE = 202
PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD = 203
PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 204
PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 205
PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 206
PH_PERF_SEL_SC1_PA5_FIFO_FULL = 207
PH_PERF_SEL_SC1_PA5_NULL_WE = 208
PH_PERF_SEL_SC1_PA5_EVENT_WE = 209
PH_PERF_SEL_SC1_PA5_FPOV_WE = 210
PH_PERF_SEL_SC1_PA5_LPOV_WE = 211
PH_PERF_SEL_SC1_PA5_EOP_WE = 212
PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 213
PH_PERF_SEL_SC1_PA5_EOPG_WE = 214
PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD = 215
PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 216
PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 217
PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 218
PH_PERF_SEL_SC1_PA6_FIFO_FULL = 219
PH_PERF_SEL_SC1_PA6_NULL_WE = 220
PH_PERF_SEL_SC1_PA6_EVENT_WE = 221
PH_PERF_SEL_SC1_PA6_FPOV_WE = 222
PH_PERF_SEL_SC1_PA6_LPOV_WE = 223
PH_PERF_SEL_SC1_PA6_EOP_WE = 224
PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 225
PH_PERF_SEL_SC1_PA6_EOPG_WE = 226
PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD = 227
PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 228
PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 229
PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 230
PH_PERF_SEL_SC1_PA7_FIFO_FULL = 231
PH_PERF_SEL_SC1_PA7_NULL_WE = 232
PH_PERF_SEL_SC1_PA7_EVENT_WE = 233
PH_PERF_SEL_SC1_PA7_FPOV_WE = 234
PH_PERF_SEL_SC1_PA7_LPOV_WE = 235
PH_PERF_SEL_SC1_PA7_EOP_WE = 236
PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 237
PH_PERF_SEL_SC1_PA7_EOPG_WE = 238
PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD = 239
PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 240
PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 241
PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 242
PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 243
PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 244
PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 245
PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 246
PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 247
PH_PERF_SEL_SC2_ARB_BUSY = 248
PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 249
PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 250
PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 251
PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 252
PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 253
PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 254
PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 255
PH_PERF_SEL_SC2_SEND = 256
PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 257
PH_PERF_SEL_SC2_CREDIT_AT_MAX = 258
PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 259
PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 260
PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 261
PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 262
PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 263
PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 264
PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 265
PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 266
PH_PERF_SEL_SC2_PA0_FIFO_FULL = 267
PH_PERF_SEL_SC2_PA0_NULL_WE = 268
PH_PERF_SEL_SC2_PA0_EVENT_WE = 269
PH_PERF_SEL_SC2_PA0_FPOV_WE = 270
PH_PERF_SEL_SC2_PA0_LPOV_WE = 271
PH_PERF_SEL_SC2_PA0_EOP_WE = 272
PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 273
PH_PERF_SEL_SC2_PA0_EOPG_WE = 274
PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD = 275
PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 276
PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 277
PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 278
PH_PERF_SEL_SC2_PA1_FIFO_FULL = 279
PH_PERF_SEL_SC2_PA1_NULL_WE = 280
PH_PERF_SEL_SC2_PA1_EVENT_WE = 281
PH_PERF_SEL_SC2_PA1_FPOV_WE = 282
PH_PERF_SEL_SC2_PA1_LPOV_WE = 283
PH_PERF_SEL_SC2_PA1_EOP_WE = 284
PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 285
PH_PERF_SEL_SC2_PA1_EOPG_WE = 286
PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD = 287
PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 288
PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 289
PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 290
PH_PERF_SEL_SC2_PA2_FIFO_FULL = 291
PH_PERF_SEL_SC2_PA2_NULL_WE = 292
PH_PERF_SEL_SC2_PA2_EVENT_WE = 293
PH_PERF_SEL_SC2_PA2_FPOV_WE = 294
PH_PERF_SEL_SC2_PA2_LPOV_WE = 295
PH_PERF_SEL_SC2_PA2_EOP_WE = 296
PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 297
PH_PERF_SEL_SC2_PA2_EOPG_WE = 298
PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD = 299
PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 300
PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 301
PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 302
PH_PERF_SEL_SC2_PA3_FIFO_FULL = 303
PH_PERF_SEL_SC2_PA3_NULL_WE = 304
PH_PERF_SEL_SC2_PA3_EVENT_WE = 305
PH_PERF_SEL_SC2_PA3_FPOV_WE = 306
PH_PERF_SEL_SC2_PA3_LPOV_WE = 307
PH_PERF_SEL_SC2_PA3_EOP_WE = 308
PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 309
PH_PERF_SEL_SC2_PA3_EOPG_WE = 310
PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD = 311
PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 312
PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 313
PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 314
PH_PERF_SEL_SC2_PA4_FIFO_FULL = 315
PH_PERF_SEL_SC2_PA4_NULL_WE = 316
PH_PERF_SEL_SC2_PA4_EVENT_WE = 317
PH_PERF_SEL_SC2_PA4_FPOV_WE = 318
PH_PERF_SEL_SC2_PA4_LPOV_WE = 319
PH_PERF_SEL_SC2_PA4_EOP_WE = 320
PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 321
PH_PERF_SEL_SC2_PA4_EOPG_WE = 322
PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD = 323
PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 324
PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 325
PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 326
PH_PERF_SEL_SC2_PA5_FIFO_FULL = 327
PH_PERF_SEL_SC2_PA5_NULL_WE = 328
PH_PERF_SEL_SC2_PA5_EVENT_WE = 329
PH_PERF_SEL_SC2_PA5_FPOV_WE = 330
PH_PERF_SEL_SC2_PA5_LPOV_WE = 331
PH_PERF_SEL_SC2_PA5_EOP_WE = 332
PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 333
PH_PERF_SEL_SC2_PA5_EOPG_WE = 334
PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD = 335
PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 336
PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 337
PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 338
PH_PERF_SEL_SC2_PA6_FIFO_FULL = 339
PH_PERF_SEL_SC2_PA6_NULL_WE = 340
PH_PERF_SEL_SC2_PA6_EVENT_WE = 341
PH_PERF_SEL_SC2_PA6_FPOV_WE = 342
PH_PERF_SEL_SC2_PA6_LPOV_WE = 343
PH_PERF_SEL_SC2_PA6_EOP_WE = 344
PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 345
PH_PERF_SEL_SC2_PA6_EOPG_WE = 346
PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD = 347
PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 348
PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 349
PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 350
PH_PERF_SEL_SC2_PA7_FIFO_FULL = 351
PH_PERF_SEL_SC2_PA7_NULL_WE = 352
PH_PERF_SEL_SC2_PA7_EVENT_WE = 353
PH_PERF_SEL_SC2_PA7_FPOV_WE = 354
PH_PERF_SEL_SC2_PA7_LPOV_WE = 355
PH_PERF_SEL_SC2_PA7_EOP_WE = 356
PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 357
PH_PERF_SEL_SC2_PA7_EOPG_WE = 358
PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD = 359
PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 360
PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 361
PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 362
PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 363
PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 364
PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 365
PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 366
PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 367
PH_PERF_SEL_SC3_ARB_BUSY = 368
PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 369
PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 370
PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 371
PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 372
PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 373
PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 374
PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 375
PH_PERF_SEL_SC3_SEND = 376
PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 377
PH_PERF_SEL_SC3_CREDIT_AT_MAX = 378
PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 379
PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 380
PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 381
PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 382
PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 383
PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 384
PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 385
PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 386
PH_PERF_SEL_SC3_PA0_FIFO_FULL = 387
PH_PERF_SEL_SC3_PA0_NULL_WE = 388
PH_PERF_SEL_SC3_PA0_EVENT_WE = 389
PH_PERF_SEL_SC3_PA0_FPOV_WE = 390
PH_PERF_SEL_SC3_PA0_LPOV_WE = 391
PH_PERF_SEL_SC3_PA0_EOP_WE = 392
PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 393
PH_PERF_SEL_SC3_PA0_EOPG_WE = 394
PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD = 395
PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 396
PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 397
PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 398
PH_PERF_SEL_SC3_PA1_FIFO_FULL = 399
PH_PERF_SEL_SC3_PA1_NULL_WE = 400
PH_PERF_SEL_SC3_PA1_EVENT_WE = 401
PH_PERF_SEL_SC3_PA1_FPOV_WE = 402
PH_PERF_SEL_SC3_PA1_LPOV_WE = 403
PH_PERF_SEL_SC3_PA1_EOP_WE = 404
PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 405
PH_PERF_SEL_SC3_PA1_EOPG_WE = 406
PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD = 407
PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 408
PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 409
PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 410
PH_PERF_SEL_SC3_PA2_FIFO_FULL = 411
PH_PERF_SEL_SC3_PA2_NULL_WE = 412
PH_PERF_SEL_SC3_PA2_EVENT_WE = 413
PH_PERF_SEL_SC3_PA2_FPOV_WE = 414
PH_PERF_SEL_SC3_PA2_LPOV_WE = 415
PH_PERF_SEL_SC3_PA2_EOP_WE = 416
PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 417
PH_PERF_SEL_SC3_PA2_EOPG_WE = 418
PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD = 419
PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 420
PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 421
PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 422
PH_PERF_SEL_SC3_PA3_FIFO_FULL = 423
PH_PERF_SEL_SC3_PA3_NULL_WE = 424
PH_PERF_SEL_SC3_PA3_EVENT_WE = 425
PH_PERF_SEL_SC3_PA3_FPOV_WE = 426
PH_PERF_SEL_SC3_PA3_LPOV_WE = 427
PH_PERF_SEL_SC3_PA3_EOP_WE = 428
PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 429
PH_PERF_SEL_SC3_PA3_EOPG_WE = 430
PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD = 431
PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 432
PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 433
PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 434
PH_PERF_SEL_SC3_PA4_FIFO_FULL = 435
PH_PERF_SEL_SC3_PA4_NULL_WE = 436
PH_PERF_SEL_SC3_PA4_EVENT_WE = 437
PH_PERF_SEL_SC3_PA4_FPOV_WE = 438
PH_PERF_SEL_SC3_PA4_LPOV_WE = 439
PH_PERF_SEL_SC3_PA4_EOP_WE = 440
PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 441
PH_PERF_SEL_SC3_PA4_EOPG_WE = 442
PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD = 443
PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 444
PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 445
PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 446
PH_PERF_SEL_SC3_PA5_FIFO_FULL = 447
PH_PERF_SEL_SC3_PA5_NULL_WE = 448
PH_PERF_SEL_SC3_PA5_EVENT_WE = 449
PH_PERF_SEL_SC3_PA5_FPOV_WE = 450
PH_PERF_SEL_SC3_PA5_LPOV_WE = 451
PH_PERF_SEL_SC3_PA5_EOP_WE = 452
PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 453
PH_PERF_SEL_SC3_PA5_EOPG_WE = 454
PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD = 455
PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 456
PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 457
PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 458
PH_PERF_SEL_SC3_PA6_FIFO_FULL = 459
PH_PERF_SEL_SC3_PA6_NULL_WE = 460
PH_PERF_SEL_SC3_PA6_EVENT_WE = 461
PH_PERF_SEL_SC3_PA6_FPOV_WE = 462
PH_PERF_SEL_SC3_PA6_LPOV_WE = 463
PH_PERF_SEL_SC3_PA6_EOP_WE = 464
PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 465
PH_PERF_SEL_SC3_PA6_EOPG_WE = 466
PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD = 467
PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 468
PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 469
PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 470
PH_PERF_SEL_SC3_PA7_FIFO_FULL = 471
PH_PERF_SEL_SC3_PA7_NULL_WE = 472
PH_PERF_SEL_SC3_PA7_EVENT_WE = 473
PH_PERF_SEL_SC3_PA7_FPOV_WE = 474
PH_PERF_SEL_SC3_PA7_LPOV_WE = 475
PH_PERF_SEL_SC3_PA7_EOP_WE = 476
PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 477
PH_PERF_SEL_SC3_PA7_EOPG_WE = 478
PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD = 479
PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 480
PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 481
PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 482
PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 483
PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 484
PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 485
PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 486
PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 487
PH_PERF_SEL_SC4_ARB_BUSY = 488
PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 489
PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 490
PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 491
PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 492
PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 493
PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 494
PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 495
PH_PERF_SEL_SC4_SEND = 496
PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 497
PH_PERF_SEL_SC4_CREDIT_AT_MAX = 498
PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 499
PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 500
PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 501
PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 502
PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 503
PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 504
PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 505
PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 506
PH_PERF_SEL_SC4_PA0_FIFO_FULL = 507
PH_PERF_SEL_SC4_PA0_NULL_WE = 508
PH_PERF_SEL_SC4_PA0_EVENT_WE = 509
PH_PERF_SEL_SC4_PA0_FPOV_WE = 510
PH_PERF_SEL_SC4_PA0_LPOV_WE = 511
PH_PERF_SEL_SC4_PA0_EOP_WE = 512
PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 513
PH_PERF_SEL_SC4_PA0_EOPG_WE = 514
PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD = 515
PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 516
PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 517
PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 518
PH_PERF_SEL_SC4_PA1_FIFO_FULL = 519
PH_PERF_SEL_SC4_PA1_NULL_WE = 520
PH_PERF_SEL_SC4_PA1_EVENT_WE = 521
PH_PERF_SEL_SC4_PA1_FPOV_WE = 522
PH_PERF_SEL_SC4_PA1_LPOV_WE = 523
PH_PERF_SEL_SC4_PA1_EOP_WE = 524
PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 525
PH_PERF_SEL_SC4_PA1_EOPG_WE = 526
PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD = 527
PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 528
PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 529
PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 530
PH_PERF_SEL_SC4_PA2_FIFO_FULL = 531
PH_PERF_SEL_SC4_PA2_NULL_WE = 532
PH_PERF_SEL_SC4_PA2_EVENT_WE = 533
PH_PERF_SEL_SC4_PA2_FPOV_WE = 534
PH_PERF_SEL_SC4_PA2_LPOV_WE = 535
PH_PERF_SEL_SC4_PA2_EOP_WE = 536
PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 537
PH_PERF_SEL_SC4_PA2_EOPG_WE = 538
PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD = 539
PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 540
PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 541
PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 542
PH_PERF_SEL_SC4_PA3_FIFO_FULL = 543
PH_PERF_SEL_SC4_PA3_NULL_WE = 544
PH_PERF_SEL_SC4_PA3_EVENT_WE = 545
PH_PERF_SEL_SC4_PA3_FPOV_WE = 546
PH_PERF_SEL_SC4_PA3_LPOV_WE = 547
PH_PERF_SEL_SC4_PA3_EOP_WE = 548
PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 549
PH_PERF_SEL_SC4_PA3_EOPG_WE = 550
PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD = 551
PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 552
PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 553
PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 554
PH_PERF_SEL_SC4_PA4_FIFO_FULL = 555
PH_PERF_SEL_SC4_PA4_NULL_WE = 556
PH_PERF_SEL_SC4_PA4_EVENT_WE = 557
PH_PERF_SEL_SC4_PA4_FPOV_WE = 558
PH_PERF_SEL_SC4_PA4_LPOV_WE = 559
PH_PERF_SEL_SC4_PA4_EOP_WE = 560
PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 561
PH_PERF_SEL_SC4_PA4_EOPG_WE = 562
PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD = 563
PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 564
PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 565
PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 566
PH_PERF_SEL_SC4_PA5_FIFO_FULL = 567
PH_PERF_SEL_SC4_PA5_NULL_WE = 568
PH_PERF_SEL_SC4_PA5_EVENT_WE = 569
PH_PERF_SEL_SC4_PA5_FPOV_WE = 570
PH_PERF_SEL_SC4_PA5_LPOV_WE = 571
PH_PERF_SEL_SC4_PA5_EOP_WE = 572
PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 573
PH_PERF_SEL_SC4_PA5_EOPG_WE = 574
PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD = 575
PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 576
PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 577
PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 578
PH_PERF_SEL_SC4_PA6_FIFO_FULL = 579
PH_PERF_SEL_SC4_PA6_NULL_WE = 580
PH_PERF_SEL_SC4_PA6_EVENT_WE = 581
PH_PERF_SEL_SC4_PA6_FPOV_WE = 582
PH_PERF_SEL_SC4_PA6_LPOV_WE = 583
PH_PERF_SEL_SC4_PA6_EOP_WE = 584
PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 585
PH_PERF_SEL_SC4_PA6_EOPG_WE = 586
PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD = 587
PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 588
PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 589
PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 590
PH_PERF_SEL_SC4_PA7_FIFO_FULL = 591
PH_PERF_SEL_SC4_PA7_NULL_WE = 592
PH_PERF_SEL_SC4_PA7_EVENT_WE = 593
PH_PERF_SEL_SC4_PA7_FPOV_WE = 594
PH_PERF_SEL_SC4_PA7_LPOV_WE = 595
PH_PERF_SEL_SC4_PA7_EOP_WE = 596
PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 597
PH_PERF_SEL_SC4_PA7_EOPG_WE = 598
PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD = 599
PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 600
PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 601
PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 602
PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 603
PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 604
PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 605
PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 606
PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 607
PH_PERF_SEL_SC5_ARB_BUSY = 608
PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 609
PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 610
PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 611
PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 612
PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 613
PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 614
PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 615
PH_PERF_SEL_SC5_SEND = 616
PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 617
PH_PERF_SEL_SC5_CREDIT_AT_MAX = 618
PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 619
PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 620
PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 621
PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 622
PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 623
PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 624
PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 625
PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 626
PH_PERF_SEL_SC5_PA0_FIFO_FULL = 627
PH_PERF_SEL_SC5_PA0_NULL_WE = 628
PH_PERF_SEL_SC5_PA0_EVENT_WE = 629
PH_PERF_SEL_SC5_PA0_FPOV_WE = 630
PH_PERF_SEL_SC5_PA0_LPOV_WE = 631
PH_PERF_SEL_SC5_PA0_EOP_WE = 632
PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 633
PH_PERF_SEL_SC5_PA0_EOPG_WE = 634
PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD = 635
PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 636
PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 637
PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 638
PH_PERF_SEL_SC5_PA1_FIFO_FULL = 639
PH_PERF_SEL_SC5_PA1_NULL_WE = 640
PH_PERF_SEL_SC5_PA1_EVENT_WE = 641
PH_PERF_SEL_SC5_PA1_FPOV_WE = 642
PH_PERF_SEL_SC5_PA1_LPOV_WE = 643
PH_PERF_SEL_SC5_PA1_EOP_WE = 644
PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 645
PH_PERF_SEL_SC5_PA1_EOPG_WE = 646
PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD = 647
PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 648
PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 649
PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 650
PH_PERF_SEL_SC5_PA2_FIFO_FULL = 651
PH_PERF_SEL_SC5_PA2_NULL_WE = 652
PH_PERF_SEL_SC5_PA2_EVENT_WE = 653
PH_PERF_SEL_SC5_PA2_FPOV_WE = 654
PH_PERF_SEL_SC5_PA2_LPOV_WE = 655
PH_PERF_SEL_SC5_PA2_EOP_WE = 656
PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 657
PH_PERF_SEL_SC5_PA2_EOPG_WE = 658
PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD = 659
PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 660
PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 661
PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 662
PH_PERF_SEL_SC5_PA3_FIFO_FULL = 663
PH_PERF_SEL_SC5_PA3_NULL_WE = 664
PH_PERF_SEL_SC5_PA3_EVENT_WE = 665
PH_PERF_SEL_SC5_PA3_FPOV_WE = 666
PH_PERF_SEL_SC5_PA3_LPOV_WE = 667
PH_PERF_SEL_SC5_PA3_EOP_WE = 668
PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 669
PH_PERF_SEL_SC5_PA3_EOPG_WE = 670
PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD = 671
PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 672
PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 673
PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 674
PH_PERF_SEL_SC5_PA4_FIFO_FULL = 675
PH_PERF_SEL_SC5_PA4_NULL_WE = 676
PH_PERF_SEL_SC5_PA4_EVENT_WE = 677
PH_PERF_SEL_SC5_PA4_FPOV_WE = 678
PH_PERF_SEL_SC5_PA4_LPOV_WE = 679
PH_PERF_SEL_SC5_PA4_EOP_WE = 680
PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 681
PH_PERF_SEL_SC5_PA4_EOPG_WE = 682
PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD = 683
PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 684
PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 685
PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 686
PH_PERF_SEL_SC5_PA5_FIFO_FULL = 687
PH_PERF_SEL_SC5_PA5_NULL_WE = 688
PH_PERF_SEL_SC5_PA5_EVENT_WE = 689
PH_PERF_SEL_SC5_PA5_FPOV_WE = 690
PH_PERF_SEL_SC5_PA5_LPOV_WE = 691
PH_PERF_SEL_SC5_PA5_EOP_WE = 692
PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 693
PH_PERF_SEL_SC5_PA5_EOPG_WE = 694
PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD = 695
PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 696
PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 697
PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 698
PH_PERF_SEL_SC5_PA6_FIFO_FULL = 699
PH_PERF_SEL_SC5_PA6_NULL_WE = 700
PH_PERF_SEL_SC5_PA6_EVENT_WE = 701
PH_PERF_SEL_SC5_PA6_FPOV_WE = 702
PH_PERF_SEL_SC5_PA6_LPOV_WE = 703
PH_PERF_SEL_SC5_PA6_EOP_WE = 704
PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 705
PH_PERF_SEL_SC5_PA6_EOPG_WE = 706
PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD = 707
PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 708
PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 709
PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 710
PH_PERF_SEL_SC5_PA7_FIFO_FULL = 711
PH_PERF_SEL_SC5_PA7_NULL_WE = 712
PH_PERF_SEL_SC5_PA7_EVENT_WE = 713
PH_PERF_SEL_SC5_PA7_FPOV_WE = 714
PH_PERF_SEL_SC5_PA7_LPOV_WE = 715
PH_PERF_SEL_SC5_PA7_EOP_WE = 716
PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 717
PH_PERF_SEL_SC5_PA7_EOPG_WE = 718
PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD = 719
PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 720
PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 721
PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 722
PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 723
PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 724
PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 725
PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 726
PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 727
PH_PERF_SEL_SC6_ARB_BUSY = 728
PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 729
PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 730
PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 731
PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 732
PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 733
PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 734
PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 735
PH_PERF_SEL_SC6_SEND = 736
PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 737
PH_PERF_SEL_SC6_CREDIT_AT_MAX = 738
PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 739
PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 740
PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 741
PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 742
PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 743
PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 744
PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 745
PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 746
PH_PERF_SEL_SC6_PA0_FIFO_FULL = 747
PH_PERF_SEL_SC6_PA0_NULL_WE = 748
PH_PERF_SEL_SC6_PA0_EVENT_WE = 749
PH_PERF_SEL_SC6_PA0_FPOV_WE = 750
PH_PERF_SEL_SC6_PA0_LPOV_WE = 751
PH_PERF_SEL_SC6_PA0_EOP_WE = 752
PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 753
PH_PERF_SEL_SC6_PA0_EOPG_WE = 754
PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD = 755
PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 756
PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 757
PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 758
PH_PERF_SEL_SC6_PA1_FIFO_FULL = 759
PH_PERF_SEL_SC6_PA1_NULL_WE = 760
PH_PERF_SEL_SC6_PA1_EVENT_WE = 761
PH_PERF_SEL_SC6_PA1_FPOV_WE = 762
PH_PERF_SEL_SC6_PA1_LPOV_WE = 763
PH_PERF_SEL_SC6_PA1_EOP_WE = 764
PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 765
PH_PERF_SEL_SC6_PA1_EOPG_WE = 766
PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD = 767
PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 768
PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 769
PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 770
PH_PERF_SEL_SC6_PA2_FIFO_FULL = 771
PH_PERF_SEL_SC6_PA2_NULL_WE = 772
PH_PERF_SEL_SC6_PA2_EVENT_WE = 773
PH_PERF_SEL_SC6_PA2_FPOV_WE = 774
PH_PERF_SEL_SC6_PA2_LPOV_WE = 775
PH_PERF_SEL_SC6_PA2_EOP_WE = 776
PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 777
PH_PERF_SEL_SC6_PA2_EOPG_WE = 778
PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD = 779
PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 780
PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 781
PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 782
PH_PERF_SEL_SC6_PA3_FIFO_FULL = 783
PH_PERF_SEL_SC6_PA3_NULL_WE = 784
PH_PERF_SEL_SC6_PA3_EVENT_WE = 785
PH_PERF_SEL_SC6_PA3_FPOV_WE = 786
PH_PERF_SEL_SC6_PA3_LPOV_WE = 787
PH_PERF_SEL_SC6_PA3_EOP_WE = 788
PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 789
PH_PERF_SEL_SC6_PA3_EOPG_WE = 790
PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD = 791
PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 792
PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 793
PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 794
PH_PERF_SEL_SC6_PA4_FIFO_FULL = 795
PH_PERF_SEL_SC6_PA4_NULL_WE = 796
PH_PERF_SEL_SC6_PA4_EVENT_WE = 797
PH_PERF_SEL_SC6_PA4_FPOV_WE = 798
PH_PERF_SEL_SC6_PA4_LPOV_WE = 799
PH_PERF_SEL_SC6_PA4_EOP_WE = 800
PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 801
PH_PERF_SEL_SC6_PA4_EOPG_WE = 802
PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD = 803
PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 804
PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 805
PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 806
PH_PERF_SEL_SC6_PA5_FIFO_FULL = 807
PH_PERF_SEL_SC6_PA5_NULL_WE = 808
PH_PERF_SEL_SC6_PA5_EVENT_WE = 809
PH_PERF_SEL_SC6_PA5_FPOV_WE = 810
PH_PERF_SEL_SC6_PA5_LPOV_WE = 811
PH_PERF_SEL_SC6_PA5_EOP_WE = 812
PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 813
PH_PERF_SEL_SC6_PA5_EOPG_WE = 814
PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD = 815
PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 816
PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 817
PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 818
PH_PERF_SEL_SC6_PA6_FIFO_FULL = 819
PH_PERF_SEL_SC6_PA6_NULL_WE = 820
PH_PERF_SEL_SC6_PA6_EVENT_WE = 821
PH_PERF_SEL_SC6_PA6_FPOV_WE = 822
PH_PERF_SEL_SC6_PA6_LPOV_WE = 823
PH_PERF_SEL_SC6_PA6_EOP_WE = 824
PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 825
PH_PERF_SEL_SC6_PA6_EOPG_WE = 826
PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD = 827
PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 828
PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 829
PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 830
PH_PERF_SEL_SC6_PA7_FIFO_FULL = 831
PH_PERF_SEL_SC6_PA7_NULL_WE = 832
PH_PERF_SEL_SC6_PA7_EVENT_WE = 833
PH_PERF_SEL_SC6_PA7_FPOV_WE = 834
PH_PERF_SEL_SC6_PA7_LPOV_WE = 835
PH_PERF_SEL_SC6_PA7_EOP_WE = 836
PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 837
PH_PERF_SEL_SC6_PA7_EOPG_WE = 838
PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD = 839
PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 840
PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 841
PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 842
PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 843
PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 844
PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 845
PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 846
PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 847
PH_PERF_SEL_SC7_ARB_BUSY = 848
PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 849
PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 850
PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 851
PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 852
PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 853
PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 854
PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 855
PH_PERF_SEL_SC7_SEND = 856
PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 857
PH_PERF_SEL_SC7_CREDIT_AT_MAX = 858
PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 859
PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 860
PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 861
PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 862
PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 863
PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 864
PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 865
PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 866
PH_PERF_SEL_SC7_PA0_FIFO_FULL = 867
PH_PERF_SEL_SC7_PA0_NULL_WE = 868
PH_PERF_SEL_SC7_PA0_EVENT_WE = 869
PH_PERF_SEL_SC7_PA0_FPOV_WE = 870
PH_PERF_SEL_SC7_PA0_LPOV_WE = 871
PH_PERF_SEL_SC7_PA0_EOP_WE = 872
PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 873
PH_PERF_SEL_SC7_PA0_EOPG_WE = 874
PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD = 875
PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 876
PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 877
PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 878
PH_PERF_SEL_SC7_PA1_FIFO_FULL = 879
PH_PERF_SEL_SC7_PA1_NULL_WE = 880
PH_PERF_SEL_SC7_PA1_EVENT_WE = 881
PH_PERF_SEL_SC7_PA1_FPOV_WE = 882
PH_PERF_SEL_SC7_PA1_LPOV_WE = 883
PH_PERF_SEL_SC7_PA1_EOP_WE = 884
PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 885
PH_PERF_SEL_SC7_PA1_EOPG_WE = 886
PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD = 887
PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 888
PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 889
PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 890
PH_PERF_SEL_SC7_PA2_FIFO_FULL = 891
PH_PERF_SEL_SC7_PA2_NULL_WE = 892
PH_PERF_SEL_SC7_PA2_EVENT_WE = 893
PH_PERF_SEL_SC7_PA2_FPOV_WE = 894
PH_PERF_SEL_SC7_PA2_LPOV_WE = 895
PH_PERF_SEL_SC7_PA2_EOP_WE = 896
PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 897
PH_PERF_SEL_SC7_PA2_EOPG_WE = 898
PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD = 899
PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 900
PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 901
PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 902
PH_PERF_SEL_SC7_PA3_FIFO_FULL = 903
PH_PERF_SEL_SC7_PA3_NULL_WE = 904
PH_PERF_SEL_SC7_PA3_EVENT_WE = 905
PH_PERF_SEL_SC7_PA3_FPOV_WE = 906
PH_PERF_SEL_SC7_PA3_LPOV_WE = 907
PH_PERF_SEL_SC7_PA3_EOP_WE = 908
PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 909
PH_PERF_SEL_SC7_PA3_EOPG_WE = 910
PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD = 911
PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 912
PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 913
PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 914
PH_PERF_SEL_SC7_PA4_FIFO_FULL = 915
PH_PERF_SEL_SC7_PA4_NULL_WE = 916
PH_PERF_SEL_SC7_PA4_EVENT_WE = 917
PH_PERF_SEL_SC7_PA4_FPOV_WE = 918
PH_PERF_SEL_SC7_PA4_LPOV_WE = 919
PH_PERF_SEL_SC7_PA4_EOP_WE = 920
PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 921
PH_PERF_SEL_SC7_PA4_EOPG_WE = 922
PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD = 923
PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 924
PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 925
PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 926
PH_PERF_SEL_SC7_PA5_FIFO_FULL = 927
PH_PERF_SEL_SC7_PA5_NULL_WE = 928
PH_PERF_SEL_SC7_PA5_EVENT_WE = 929
PH_PERF_SEL_SC7_PA5_FPOV_WE = 930
PH_PERF_SEL_SC7_PA5_LPOV_WE = 931
PH_PERF_SEL_SC7_PA5_EOP_WE = 932
PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 933
PH_PERF_SEL_SC7_PA5_EOPG_WE = 934
PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD = 935
PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 936
PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 937
PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 938
PH_PERF_SEL_SC7_PA6_FIFO_FULL = 939
PH_PERF_SEL_SC7_PA6_NULL_WE = 940
PH_PERF_SEL_SC7_PA6_EVENT_WE = 941
PH_PERF_SEL_SC7_PA6_FPOV_WE = 942
PH_PERF_SEL_SC7_PA6_LPOV_WE = 943
PH_PERF_SEL_SC7_PA6_EOP_WE = 944
PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 945
PH_PERF_SEL_SC7_PA6_EOPG_WE = 946
PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD = 947
PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 948
PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 949
PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 950
PH_PERF_SEL_SC7_PA7_FIFO_FULL = 951
PH_PERF_SEL_SC7_PA7_NULL_WE = 952
PH_PERF_SEL_SC7_PA7_EVENT_WE = 953
PH_PERF_SEL_SC7_PA7_FPOV_WE = 954
PH_PERF_SEL_SC7_PA7_LPOV_WE = 955
PH_PERF_SEL_SC7_PA7_EOP_WE = 956
PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 957
PH_PERF_SEL_SC7_PA7_EOPG_WE = 958
PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD = 959
PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 960
PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 961
PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 962
PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 963
PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 964
PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 965
PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 966
PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 967
PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 968
PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 969
PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 970
PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 971
PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 972
PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 973
PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 974
PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 975
PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 976
PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 977
PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 978
PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 979
PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 980
PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 981
PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 982
PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 983
PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 984
PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 985
PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 986
PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 987
PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 988
PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 989
PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 990
PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 991
PH_PERF_SC0_FIFO_STATUS_0 = 992
PH_PERF_SC0_FIFO_STATUS_1 = 993
PH_PERF_SC0_FIFO_STATUS_2 = 994
PH_PERF_SC0_FIFO_STATUS_3 = 995
PH_PERF_SC1_FIFO_STATUS_0 = 996
PH_PERF_SC1_FIFO_STATUS_1 = 997
PH_PERF_SC1_FIFO_STATUS_2 = 998
PH_PERF_SC1_FIFO_STATUS_3 = 999
PH_PERF_SC2_FIFO_STATUS_0 = 1000
PH_PERF_SC2_FIFO_STATUS_1 = 1001
PH_PERF_SC2_FIFO_STATUS_2 = 1002
PH_PERF_SC2_FIFO_STATUS_3 = 1003
PH_PERF_SC3_FIFO_STATUS_0 = 1004
PH_PERF_SC3_FIFO_STATUS_1 = 1005
PH_PERF_SC3_FIFO_STATUS_2 = 1006
PH_PERF_SC3_FIFO_STATUS_3 = 1007
PH_PERF_SC4_FIFO_STATUS_0 = 1008
PH_PERF_SC4_FIFO_STATUS_1 = 1009
PH_PERF_SC4_FIFO_STATUS_2 = 1010
PH_PERF_SC4_FIFO_STATUS_3 = 1011
PH_PERF_SC5_FIFO_STATUS_0 = 1012
PH_PERF_SC5_FIFO_STATUS_1 = 1013
PH_PERF_SC5_FIFO_STATUS_2 = 1014
PH_PERF_SC5_FIFO_STATUS_3 = 1015
PH_PERF_SC6_FIFO_STATUS_0 = 1016
PH_PERF_SC6_FIFO_STATUS_1 = 1017
PH_PERF_SC6_FIFO_STATUS_2 = 1018
PH_PERF_SC6_FIFO_STATUS_3 = 1019
PH_PERF_SC7_FIFO_STATUS_0 = 1020
PH_PERF_SC7_FIFO_STATUS_1 = 1021
PH_PERF_SC7_FIFO_STATUS_2 = 1022
PH_PERF_SC7_FIFO_STATUS_3 = 1023
PH_PERFCNT_SEL = ctypes.c_uint32 # enum
# values for enumeration 'PhSPIstatusMode'
PhSPIstatusMode__enumvalues = {
0: 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT',
1: 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT',
2: 'PH_SPI_MODE_DISABLED',
}
PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0
PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 1
PH_SPI_MODE_DISABLED = 2
PhSPIstatusMode = ctypes.c_uint32 # enum
# values for enumeration 'RMIPerfSel'
RMIPerfSel__enumvalues = {
0: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID',
1: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID',
}
RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0
RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 1
RMIPerfSel = ctypes.c_uint32 # enum
# values for enumeration 'GCRPerfSel'
GCRPerfSel__enumvalues = {
0: 'GCR_PERF_SEL_NONE',
1: 'GCR_PERF_SEL_SDMA0_ALL_REQ',
2: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ',
3: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ',
4: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ',
5: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ',
6: 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ',
7: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ',
8: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ',
9: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ',
10: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ',
11: 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ',
12: 'GCR_PERF_SEL_SDMA0_METADATA_REQ',
13: 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ',
14: 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ',
15: 'GCR_PERF_SEL_SDMA0_TCP_REQ',
16: 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ',
17: 'GCR_PERF_SEL_SDMA1_ALL_REQ',
18: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ',
19: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ',
20: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ',
21: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ',
22: 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ',
23: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ',
24: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ',
25: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ',
26: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ',
27: 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ',
28: 'GCR_PERF_SEL_SDMA1_METADATA_REQ',
29: 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ',
30: 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ',
31: 'GCR_PERF_SEL_SDMA1_TCP_REQ',
32: 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ',
33: 'GCR_PERF_SEL_CPC_ALL_REQ',
34: 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ',
35: 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ',
36: 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ',
37: 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ',
38: 'GCR_PERF_SEL_CPC_GL2_ALL_REQ',
39: 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ',
40: 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ',
41: 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ',
42: 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ',
43: 'GCR_PERF_SEL_CPC_GL1_ALL_REQ',
44: 'GCR_PERF_SEL_CPC_METADATA_REQ',
45: 'GCR_PERF_SEL_CPC_SQC_DATA_REQ',
46: 'GCR_PERF_SEL_CPC_SQC_INST_REQ',
47: 'GCR_PERF_SEL_CPC_TCP_REQ',
48: 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ',
49: 'GCR_PERF_SEL_CPG_ALL_REQ',
50: 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ',
51: 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ',
52: 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ',
53: 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ',
54: 'GCR_PERF_SEL_CPG_GL2_ALL_REQ',
55: 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ',
56: 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ',
57: 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ',
58: 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ',
59: 'GCR_PERF_SEL_CPG_GL1_ALL_REQ',
60: 'GCR_PERF_SEL_CPG_METADATA_REQ',
61: 'GCR_PERF_SEL_CPG_SQC_DATA_REQ',
62: 'GCR_PERF_SEL_CPG_SQC_INST_REQ',
63: 'GCR_PERF_SEL_CPG_TCP_REQ',
64: 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ',
65: 'GCR_PERF_SEL_CPF_ALL_REQ',
66: 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ',
67: 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ',
68: 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ',
69: 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ',
70: 'GCR_PERF_SEL_CPF_GL2_ALL_REQ',
71: 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ',
72: 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ',
73: 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ',
74: 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ',
75: 'GCR_PERF_SEL_CPF_GL1_ALL_REQ',
76: 'GCR_PERF_SEL_CPF_METADATA_REQ',
77: 'GCR_PERF_SEL_CPF_SQC_DATA_REQ',
78: 'GCR_PERF_SEL_CPF_SQC_INST_REQ',
79: 'GCR_PERF_SEL_CPF_TCP_REQ',
80: 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ',
81: 'GCR_PERF_SEL_VIRT_REQ',
82: 'GCR_PERF_SEL_PHY_REQ',
83: 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ',
84: 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ',
85: 'GCR_PERF_SEL_ALL_REQ',
86: 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ',
87: 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ',
88: 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ',
89: 'GCR_PERF_SEL_UTCL2_REQ',
90: 'GCR_PERF_SEL_UTCL2_RET',
91: 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT',
92: 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ',
93: 'GCR_PERF_SEL_UTCL2_FILTERED_RET',
94: 'GCR_PERF_SEL_RLC_ALL_REQ',
95: 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ',
96: 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ',
97: 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ',
98: 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ',
99: 'GCR_PERF_SEL_RLC_GL2_ALL_REQ',
100: 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ',
101: 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ',
102: 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ',
103: 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ',
104: 'GCR_PERF_SEL_RLC_GL1_ALL_REQ',
105: 'GCR_PERF_SEL_RLC_METADATA_REQ',
106: 'GCR_PERF_SEL_RLC_SQC_DATA_REQ',
107: 'GCR_PERF_SEL_RLC_SQC_INST_REQ',
108: 'GCR_PERF_SEL_RLC_TCP_REQ',
109: 'GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ',
110: 'GCR_PERF_SEL_PM_ALL_REQ',
111: 'GCR_PERF_SEL_PM_GL2_RANGE_REQ',
112: 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ',
113: 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ',
114: 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ',
115: 'GCR_PERF_SEL_PM_GL2_ALL_REQ',
116: 'GCR_PERF_SEL_PM_GL1_RANGE_REQ',
117: 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ',
118: 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ',
119: 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ',
120: 'GCR_PERF_SEL_PM_GL1_ALL_REQ',
121: 'GCR_PERF_SEL_PM_METADATA_REQ',
122: 'GCR_PERF_SEL_PM_SQC_DATA_REQ',
123: 'GCR_PERF_SEL_PM_SQC_INST_REQ',
124: 'GCR_PERF_SEL_PM_TCP_REQ',
125: 'GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ',
126: 'GCR_PERF_SEL_PIO_ALL_REQ',
127: 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ',
128: 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ',
129: 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ',
130: 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ',
131: 'GCR_PERF_SEL_PIO_GL2_ALL_REQ',
132: 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ',
133: 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ',
134: 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ',
135: 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ',
136: 'GCR_PERF_SEL_PIO_GL1_ALL_REQ',
137: 'GCR_PERF_SEL_PIO_METADATA_REQ',
138: 'GCR_PERF_SEL_PIO_SQC_DATA_REQ',
139: 'GCR_PERF_SEL_PIO_SQC_INST_REQ',
140: 'GCR_PERF_SEL_PIO_TCP_REQ',
141: 'GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ',
}
GCR_PERF_SEL_NONE = 0
GCR_PERF_SEL_SDMA0_ALL_REQ = 1
GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 2
GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 3
GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 4
GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 5
GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 6
GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 7
GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 8
GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 9
GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 10
GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 11
GCR_PERF_SEL_SDMA0_METADATA_REQ = 12
GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 13
GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 14
GCR_PERF_SEL_SDMA0_TCP_REQ = 15
GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 16
GCR_PERF_SEL_SDMA1_ALL_REQ = 17
GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 18
GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 19
GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 20
GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 21
GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 22
GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 23
GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 24
GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 25
GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 26
GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 27
GCR_PERF_SEL_SDMA1_METADATA_REQ = 28
GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 29
GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 30
GCR_PERF_SEL_SDMA1_TCP_REQ = 31
GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 32
GCR_PERF_SEL_CPC_ALL_REQ = 33
GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 34
GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 35
GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 36
GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 37
GCR_PERF_SEL_CPC_GL2_ALL_REQ = 38
GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 39
GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 40
GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 41
GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 42
GCR_PERF_SEL_CPC_GL1_ALL_REQ = 43
GCR_PERF_SEL_CPC_METADATA_REQ = 44
GCR_PERF_SEL_CPC_SQC_DATA_REQ = 45
GCR_PERF_SEL_CPC_SQC_INST_REQ = 46
GCR_PERF_SEL_CPC_TCP_REQ = 47
GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 48
GCR_PERF_SEL_CPG_ALL_REQ = 49
GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 50
GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 51
GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 52
GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 53
GCR_PERF_SEL_CPG_GL2_ALL_REQ = 54
GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 55
GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 56
GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 57
GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 58
GCR_PERF_SEL_CPG_GL1_ALL_REQ = 59
GCR_PERF_SEL_CPG_METADATA_REQ = 60
GCR_PERF_SEL_CPG_SQC_DATA_REQ = 61
GCR_PERF_SEL_CPG_SQC_INST_REQ = 62
GCR_PERF_SEL_CPG_TCP_REQ = 63
GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 64
GCR_PERF_SEL_CPF_ALL_REQ = 65
GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 66
GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 67
GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 68
GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 69
GCR_PERF_SEL_CPF_GL2_ALL_REQ = 70
GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 71
GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 72
GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 73
GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 74
GCR_PERF_SEL_CPF_GL1_ALL_REQ = 75
GCR_PERF_SEL_CPF_METADATA_REQ = 76
GCR_PERF_SEL_CPF_SQC_DATA_REQ = 77
GCR_PERF_SEL_CPF_SQC_INST_REQ = 78
GCR_PERF_SEL_CPF_TCP_REQ = 79
GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 80
GCR_PERF_SEL_VIRT_REQ = 81
GCR_PERF_SEL_PHY_REQ = 82
GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 83
GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 84
GCR_PERF_SEL_ALL_REQ = 85
GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 86
GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 87
GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 88
GCR_PERF_SEL_UTCL2_REQ = 89
GCR_PERF_SEL_UTCL2_RET = 90
GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 91
GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 92
GCR_PERF_SEL_UTCL2_FILTERED_RET = 93
GCR_PERF_SEL_RLC_ALL_REQ = 94
GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 95
GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 96
GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 97
GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 98
GCR_PERF_SEL_RLC_GL2_ALL_REQ = 99
GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 100
GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 101
GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 102
GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 103
GCR_PERF_SEL_RLC_GL1_ALL_REQ = 104
GCR_PERF_SEL_RLC_METADATA_REQ = 105
GCR_PERF_SEL_RLC_SQC_DATA_REQ = 106
GCR_PERF_SEL_RLC_SQC_INST_REQ = 107
GCR_PERF_SEL_RLC_TCP_REQ = 108
GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ = 109
GCR_PERF_SEL_PM_ALL_REQ = 110
GCR_PERF_SEL_PM_GL2_RANGE_REQ = 111
GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 112
GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 113
GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 114
GCR_PERF_SEL_PM_GL2_ALL_REQ = 115
GCR_PERF_SEL_PM_GL1_RANGE_REQ = 116
GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 117
GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 118
GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 119
GCR_PERF_SEL_PM_GL1_ALL_REQ = 120
GCR_PERF_SEL_PM_METADATA_REQ = 121
GCR_PERF_SEL_PM_SQC_DATA_REQ = 122
GCR_PERF_SEL_PM_SQC_INST_REQ = 123
GCR_PERF_SEL_PM_TCP_REQ = 124
GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ = 125
GCR_PERF_SEL_PIO_ALL_REQ = 126
GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 127
GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 128
GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 129
GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 130
GCR_PERF_SEL_PIO_GL2_ALL_REQ = 131
GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 132
GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 133
GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 134
GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 135
GCR_PERF_SEL_PIO_GL1_ALL_REQ = 136
GCR_PERF_SEL_PIO_METADATA_REQ = 137
GCR_PERF_SEL_PIO_SQC_DATA_REQ = 138
GCR_PERF_SEL_PIO_SQC_INST_REQ = 139
GCR_PERF_SEL_PIO_TCP_REQ = 140
GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ = 141
GCRPerfSel = ctypes.c_uint32 # enum
# values for enumeration 'UTCL1PerfSel'
UTCL1PerfSel__enumvalues = {
0: 'UTCL1_PERF_SEL_NONE',
1: 'UTCL1_PERF_SEL_REQS',
2: 'UTCL1_PERF_SEL_HITS',
3: 'UTCL1_PERF_SEL_MISSES',
4: 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT',
5: 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT',
6: 'UTCL1_PERF_SEL_UTCL2_REQS',
7: 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY',
8: 'UTCL1_PERF_SEL_UTCL2_RET_FAULT',
9: 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS',
10: 'UTCL1_PERF_SEL_STALL_MH_FULL',
11: 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM',
12: 'UTCL1_PERF_SEL_UTCL2_RET_CNT',
13: 'UTCL1_PERF_SEL_RTNS',
14: 'UTCL1_PERF_SEL_XLAT_REQ_BUSY',
15: 'UTCL1_PERF_SEL_BYPASS_REQS',
16: 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS',
17: 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT',
18: 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT',
19: 'UTCL1_PERF_SEL_CP_INVREQS',
20: 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS',
21: 'UTCL1_PERF_SEL_RANGE_INVREQS',
22: 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS',
}
UTCL1_PERF_SEL_NONE = 0
UTCL1_PERF_SEL_REQS = 1
UTCL1_PERF_SEL_HITS = 2
UTCL1_PERF_SEL_MISSES = 3
UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 4
UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 5
UTCL1_PERF_SEL_UTCL2_REQS = 6
UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 7
UTCL1_PERF_SEL_UTCL2_RET_FAULT = 8
UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 9
UTCL1_PERF_SEL_STALL_MH_FULL = 10
UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 11
UTCL1_PERF_SEL_UTCL2_RET_CNT = 12
UTCL1_PERF_SEL_RTNS = 13
UTCL1_PERF_SEL_XLAT_REQ_BUSY = 14
UTCL1_PERF_SEL_BYPASS_REQS = 15
UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 16
UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 17
UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 18
UTCL1_PERF_SEL_CP_INVREQS = 19
UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 20
UTCL1_PERF_SEL_RANGE_INVREQS = 21
UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 22
UTCL1PerfSel = ctypes.c_uint32 # enum
# values for enumeration 'IH_CLIENT_TYPE'
IH_CLIENT_TYPE__enumvalues = {
0: 'IH_GFX_VMID_CLIENT',
1: 'IH_MM_VMID_CLIENT',
2: 'IH_MULTI_VMID_CLIENT',
3: 'IH_CLIENT_TYPE_RESERVED',
}
IH_GFX_VMID_CLIENT = 0
IH_MM_VMID_CLIENT = 1
IH_MULTI_VMID_CLIENT = 2
IH_CLIENT_TYPE_RESERVED = 3
IH_CLIENT_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'IH_INTERFACE_TYPE'
IH_INTERFACE_TYPE__enumvalues = {
0: 'IH_LEGACY_INTERFACE',
1: 'IH_REGISTER_WRITE_INTERFACE',
}
IH_LEGACY_INTERFACE = 0
IH_REGISTER_WRITE_INTERFACE = 1
IH_INTERFACE_TYPE = ctypes.c_uint32 # enum
# values for enumeration 'IH_PERF_SEL'
IH_PERF_SEL__enumvalues = {
0: 'IH_PERF_SEL_CYCLE',
1: 'IH_PERF_SEL_IDLE',
2: 'IH_PERF_SEL_INPUT_IDLE',
3: 'IH_PERF_SEL_BUFFER_IDLE',
4: 'IH_PERF_SEL_RB0_FULL',
5: 'IH_PERF_SEL_RB0_OVERFLOW',
6: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK',
7: 'IH_PERF_SEL_RB0_WPTR_WRAP',
8: 'IH_PERF_SEL_RB0_RPTR_WRAP',
9: 'IH_PERF_SEL_MC_WR_IDLE',
10: 'IH_PERF_SEL_MC_WR_COUNT',
11: 'IH_PERF_SEL_MC_WR_STALL',
12: 'IH_PERF_SEL_MC_WR_CLEAN_PENDING',
13: 'IH_PERF_SEL_MC_WR_CLEAN_STALL',
14: 'IH_PERF_SEL_BIF_LINE0_RISING',
15: 'IH_PERF_SEL_BIF_LINE0_FALLING',
16: 'IH_PERF_SEL_RB1_FULL',
17: 'IH_PERF_SEL_RB1_OVERFLOW',
18: 'IH_PERF_SEL_COOKIE_REC_ERROR',
19: 'IH_PERF_SEL_RB1_WPTR_WRAP',
20: 'IH_PERF_SEL_RB1_RPTR_WRAP',
21: 'IH_PERF_SEL_RB2_FULL',
22: 'IH_PERF_SEL_RB2_OVERFLOW',
23: 'IH_PERF_SEL_CLIENT_CREDIT_ERROR',
24: 'IH_PERF_SEL_RB2_WPTR_WRAP',
25: 'IH_PERF_SEL_RB2_RPTR_WRAP',
26: 'IH_PERF_SEL_STORM_CLIENT_INT_DROP',
27: 'IH_PERF_SEL_SELF_IV_VALID',
28: 'IH_PERF_SEL_BUFFER_FIFO_FULL',
29: 'IH_PERF_SEL_RB0_FULL_VF0',
30: 'IH_PERF_SEL_RB0_FULL_VF1',
31: 'IH_PERF_SEL_RB0_FULL_VF2',
32: 'IH_PERF_SEL_RB0_FULL_VF3',
33: 'IH_PERF_SEL_RB0_FULL_VF4',
34: 'IH_PERF_SEL_RB0_FULL_VF5',
35: 'IH_PERF_SEL_RB0_FULL_VF6',
36: 'IH_PERF_SEL_RB0_FULL_VF7',
37: 'IH_PERF_SEL_RB0_FULL_VF8',
38: 'IH_PERF_SEL_RB0_FULL_VF9',
39: 'IH_PERF_SEL_RB0_FULL_VF10',
40: 'IH_PERF_SEL_RB0_FULL_VF11',
41: 'IH_PERF_SEL_RB0_FULL_VF12',
42: 'IH_PERF_SEL_RB0_FULL_VF13',
43: 'IH_PERF_SEL_RB0_FULL_VF14',
44: 'IH_PERF_SEL_RB0_FULL_VF15',
45: 'IH_PERF_SEL_RB0_OVERFLOW_VF0',
46: 'IH_PERF_SEL_RB0_OVERFLOW_VF1',
47: 'IH_PERF_SEL_RB0_OVERFLOW_VF2',
48: 'IH_PERF_SEL_RB0_OVERFLOW_VF3',
49: 'IH_PERF_SEL_RB0_OVERFLOW_VF4',
50: 'IH_PERF_SEL_RB0_OVERFLOW_VF5',
51: 'IH_PERF_SEL_RB0_OVERFLOW_VF6',
52: 'IH_PERF_SEL_RB0_OVERFLOW_VF7',
53: 'IH_PERF_SEL_RB0_OVERFLOW_VF8',
54: 'IH_PERF_SEL_RB0_OVERFLOW_VF9',
55: 'IH_PERF_SEL_RB0_OVERFLOW_VF10',
56: 'IH_PERF_SEL_RB0_OVERFLOW_VF11',
57: 'IH_PERF_SEL_RB0_OVERFLOW_VF12',
58: 'IH_PERF_SEL_RB0_OVERFLOW_VF13',
59: 'IH_PERF_SEL_RB0_OVERFLOW_VF14',
60: 'IH_PERF_SEL_RB0_OVERFLOW_VF15',
61: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0',
62: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1',
63: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2',
64: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3',
65: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4',
66: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5',
67: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6',
68: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7',
69: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8',
70: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9',
71: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10',
72: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11',
73: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12',
74: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13',
75: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14',
76: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15',
77: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0',
78: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1',
79: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2',
80: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3',
81: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4',
82: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5',
83: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6',
84: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7',
85: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8',
86: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9',
87: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10',
88: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11',
89: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12',
90: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13',
91: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14',
92: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15',
93: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0',
94: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1',
95: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2',
96: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3',
97: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4',
98: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5',
99: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6',
100: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7',
101: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8',
102: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9',
103: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10',
104: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11',
105: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12',
106: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13',
107: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14',
108: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15',
109: 'IH_PERF_SEL_BIF_LINE0_RISING_VF0',
110: 'IH_PERF_SEL_BIF_LINE0_RISING_VF1',
111: 'IH_PERF_SEL_BIF_LINE0_RISING_VF2',
112: 'IH_PERF_SEL_BIF_LINE0_RISING_VF3',
113: 'IH_PERF_SEL_BIF_LINE0_RISING_VF4',
114: 'IH_PERF_SEL_BIF_LINE0_RISING_VF5',
115: 'IH_PERF_SEL_BIF_LINE0_RISING_VF6',
116: 'IH_PERF_SEL_BIF_LINE0_RISING_VF7',
117: 'IH_PERF_SEL_BIF_LINE0_RISING_VF8',
118: 'IH_PERF_SEL_BIF_LINE0_RISING_VF9',
119: 'IH_PERF_SEL_BIF_LINE0_RISING_VF10',
120: 'IH_PERF_SEL_BIF_LINE0_RISING_VF11',
121: 'IH_PERF_SEL_BIF_LINE0_RISING_VF12',
122: 'IH_PERF_SEL_BIF_LINE0_RISING_VF13',
123: 'IH_PERF_SEL_BIF_LINE0_RISING_VF14',
124: 'IH_PERF_SEL_BIF_LINE0_RISING_VF15',
125: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0',
126: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1',
127: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2',
128: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3',
129: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4',
130: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5',
131: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6',
132: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7',
133: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8',
134: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9',
135: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10',
136: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11',
137: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12',
138: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13',
139: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14',
140: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15',
141: 'IH_PERF_SEL_CLIENT0_INT',
142: 'IH_PERF_SEL_CLIENT1_INT',
143: 'IH_PERF_SEL_CLIENT2_INT',
144: 'IH_PERF_SEL_CLIENT3_INT',
145: 'IH_PERF_SEL_CLIENT4_INT',
146: 'IH_PERF_SEL_CLIENT5_INT',
147: 'IH_PERF_SEL_CLIENT6_INT',
148: 'IH_PERF_SEL_CLIENT7_INT',
149: 'IH_PERF_SEL_CLIENT8_INT',
150: 'IH_PERF_SEL_CLIENT9_INT',
151: 'IH_PERF_SEL_CLIENT10_INT',
152: 'IH_PERF_SEL_CLIENT11_INT',
153: 'IH_PERF_SEL_CLIENT12_INT',
154: 'IH_PERF_SEL_CLIENT13_INT',
155: 'IH_PERF_SEL_CLIENT14_INT',
156: 'IH_PERF_SEL_CLIENT15_INT',
157: 'IH_PERF_SEL_CLIENT16_INT',
158: 'IH_PERF_SEL_CLIENT17_INT',
159: 'IH_PERF_SEL_CLIENT18_INT',
160: 'IH_PERF_SEL_CLIENT19_INT',
161: 'IH_PERF_SEL_CLIENT20_INT',
162: 'IH_PERF_SEL_CLIENT21_INT',
163: 'IH_PERF_SEL_CLIENT22_INT',
164: 'IH_PERF_SEL_CLIENT23_INT',
165: 'IH_PERF_SEL_CLIENT24_INT',
166: 'IH_PERF_SEL_CLIENT25_INT',
167: 'IH_PERF_SEL_CLIENT26_INT',
168: 'IH_PERF_SEL_CLIENT27_INT',
169: 'IH_PERF_SEL_CLIENT28_INT',
170: 'IH_PERF_SEL_CLIENT29_INT',
171: 'IH_PERF_SEL_CLIENT30_INT',
172: 'IH_PERF_SEL_CLIENT31_INT',
173: 'IH_PERF_SEL_RB1_FULL_VF0',
174: 'IH_PERF_SEL_RB1_FULL_VF1',
175: 'IH_PERF_SEL_RB1_FULL_VF2',
176: 'IH_PERF_SEL_RB1_FULL_VF3',
177: 'IH_PERF_SEL_RB1_FULL_VF4',
178: 'IH_PERF_SEL_RB1_FULL_VF5',
179: 'IH_PERF_SEL_RB1_FULL_VF6',
180: 'IH_PERF_SEL_RB1_FULL_VF7',
181: 'IH_PERF_SEL_RB1_FULL_VF8',
182: 'IH_PERF_SEL_RB1_FULL_VF9',
183: 'IH_PERF_SEL_RB1_FULL_VF10',
184: 'IH_PERF_SEL_RB1_FULL_VF11',
185: 'IH_PERF_SEL_RB1_FULL_VF12',
186: 'IH_PERF_SEL_RB1_FULL_VF13',
187: 'IH_PERF_SEL_RB1_FULL_VF14',
188: 'IH_PERF_SEL_RB1_FULL_VF15',
189: 'IH_PERF_SEL_RB1_OVERFLOW_VF0',
190: 'IH_PERF_SEL_RB1_OVERFLOW_VF1',
191: 'IH_PERF_SEL_RB1_OVERFLOW_VF2',
192: 'IH_PERF_SEL_RB1_OVERFLOW_VF3',
193: 'IH_PERF_SEL_RB1_OVERFLOW_VF4',
194: 'IH_PERF_SEL_RB1_OVERFLOW_VF5',
195: 'IH_PERF_SEL_RB1_OVERFLOW_VF6',
196: 'IH_PERF_SEL_RB1_OVERFLOW_VF7',
197: 'IH_PERF_SEL_RB1_OVERFLOW_VF8',
198: 'IH_PERF_SEL_RB1_OVERFLOW_VF9',
199: 'IH_PERF_SEL_RB1_OVERFLOW_VF10',
200: 'IH_PERF_SEL_RB1_OVERFLOW_VF11',
201: 'IH_PERF_SEL_RB1_OVERFLOW_VF12',
202: 'IH_PERF_SEL_RB1_OVERFLOW_VF13',
203: 'IH_PERF_SEL_RB1_OVERFLOW_VF14',
204: 'IH_PERF_SEL_RB1_OVERFLOW_VF15',
205: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0',
206: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1',
207: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2',
208: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3',
209: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4',
210: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5',
211: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6',
212: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7',
213: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8',
214: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9',
215: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10',
216: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11',
217: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12',
218: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13',
219: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14',
220: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15',
221: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0',
222: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1',
223: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2',
224: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3',
225: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4',
226: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5',
227: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6',
228: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7',
229: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8',
230: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9',
231: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10',
232: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11',
233: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12',
234: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13',
235: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14',
236: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15',
237: 'IH_PERF_SEL_RB2_FULL_VF0',
238: 'IH_PERF_SEL_RB2_FULL_VF1',
239: 'IH_PERF_SEL_RB2_FULL_VF2',
240: 'IH_PERF_SEL_RB2_FULL_VF3',
241: 'IH_PERF_SEL_RB2_FULL_VF4',
242: 'IH_PERF_SEL_RB2_FULL_VF5',
243: 'IH_PERF_SEL_RB2_FULL_VF6',
244: 'IH_PERF_SEL_RB2_FULL_VF7',
245: 'IH_PERF_SEL_RB2_FULL_VF8',
246: 'IH_PERF_SEL_RB2_FULL_VF9',
247: 'IH_PERF_SEL_RB2_FULL_VF10',
248: 'IH_PERF_SEL_RB2_FULL_VF11',
249: 'IH_PERF_SEL_RB2_FULL_VF12',
250: 'IH_PERF_SEL_RB2_FULL_VF13',
251: 'IH_PERF_SEL_RB2_FULL_VF14',
252: 'IH_PERF_SEL_RB2_FULL_VF15',
253: 'IH_PERF_SEL_RB2_OVERFLOW_VF0',
254: 'IH_PERF_SEL_RB2_OVERFLOW_VF1',
255: 'IH_PERF_SEL_RB2_OVERFLOW_VF2',
256: 'IH_PERF_SEL_RB2_OVERFLOW_VF3',
257: 'IH_PERF_SEL_RB2_OVERFLOW_VF4',
258: 'IH_PERF_SEL_RB2_OVERFLOW_VF5',
259: 'IH_PERF_SEL_RB2_OVERFLOW_VF6',
260: 'IH_PERF_SEL_RB2_OVERFLOW_VF7',
261: 'IH_PERF_SEL_RB2_OVERFLOW_VF8',
262: 'IH_PERF_SEL_RB2_OVERFLOW_VF9',
263: 'IH_PERF_SEL_RB2_OVERFLOW_VF10',
264: 'IH_PERF_SEL_RB2_OVERFLOW_VF11',
265: 'IH_PERF_SEL_RB2_OVERFLOW_VF12',
266: 'IH_PERF_SEL_RB2_OVERFLOW_VF13',
267: 'IH_PERF_SEL_RB2_OVERFLOW_VF14',
268: 'IH_PERF_SEL_RB2_OVERFLOW_VF15',
269: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0',
270: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1',
271: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2',
272: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3',
273: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4',
274: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5',
275: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6',
276: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7',
277: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8',
278: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9',
279: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10',
280: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11',
281: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12',
282: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13',
283: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14',
284: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15',
285: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0',
286: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1',
287: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2',
288: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3',
289: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4',
290: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5',
291: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6',
292: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7',
293: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8',
294: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9',
295: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10',
296: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11',
297: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12',
298: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13',
299: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14',
300: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15',
301: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP',
302: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0',
303: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1',
304: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2',
305: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3',
306: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4',
307: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5',
308: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6',
309: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7',
310: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8',
311: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9',
312: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10',
313: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11',
314: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12',
315: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13',
316: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14',
317: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15',
318: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP',
319: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0',
320: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1',
321: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2',
322: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3',
323: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4',
324: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5',
325: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6',
326: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7',
327: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8',
328: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9',
329: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10',
330: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11',
331: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12',
332: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13',
333: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14',
334: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15',
335: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP',
336: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0',
337: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1',
338: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2',
339: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3',
340: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4',
341: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5',
342: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6',
343: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7',
344: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8',
345: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9',
346: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10',
347: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11',
348: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12',
349: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13',
350: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14',
351: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15',
352: 'IH_PERF_SEL_RB0_LOAD_RPTR',
353: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0',
354: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1',
355: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2',
356: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3',
357: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4',
358: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5',
359: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6',
360: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7',
361: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8',
362: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9',
363: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10',
364: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11',
365: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12',
366: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13',
367: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14',
368: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15',
369: 'IH_PERF_SEL_RB1_LOAD_RPTR',
370: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0',
371: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1',
372: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2',
373: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3',
374: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4',
375: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5',
376: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6',
377: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7',
378: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8',
379: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9',
380: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10',
381: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11',
382: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12',
383: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13',
384: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14',
385: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15',
386: 'IH_PERF_SEL_RB2_LOAD_RPTR',
387: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0',
388: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1',
389: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2',
390: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3',
391: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4',
392: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5',
393: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6',
394: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7',
395: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8',
396: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9',
397: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10',
398: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11',
399: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12',
400: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13',
401: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14',
402: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15',
}
IH_PERF_SEL_CYCLE = 0
IH_PERF_SEL_IDLE = 1
IH_PERF_SEL_INPUT_IDLE = 2
IH_PERF_SEL_BUFFER_IDLE = 3
IH_PERF_SEL_RB0_FULL = 4
IH_PERF_SEL_RB0_OVERFLOW = 5
IH_PERF_SEL_RB0_WPTR_WRITEBACK = 6
IH_PERF_SEL_RB0_WPTR_WRAP = 7
IH_PERF_SEL_RB0_RPTR_WRAP = 8
IH_PERF_SEL_MC_WR_IDLE = 9
IH_PERF_SEL_MC_WR_COUNT = 10
IH_PERF_SEL_MC_WR_STALL = 11
IH_PERF_SEL_MC_WR_CLEAN_PENDING = 12
IH_PERF_SEL_MC_WR_CLEAN_STALL = 13
IH_PERF_SEL_BIF_LINE0_RISING = 14
IH_PERF_SEL_BIF_LINE0_FALLING = 15
IH_PERF_SEL_RB1_FULL = 16
IH_PERF_SEL_RB1_OVERFLOW = 17
IH_PERF_SEL_COOKIE_REC_ERROR = 18
IH_PERF_SEL_RB1_WPTR_WRAP = 19
IH_PERF_SEL_RB1_RPTR_WRAP = 20
IH_PERF_SEL_RB2_FULL = 21
IH_PERF_SEL_RB2_OVERFLOW = 22
IH_PERF_SEL_CLIENT_CREDIT_ERROR = 23
IH_PERF_SEL_RB2_WPTR_WRAP = 24
IH_PERF_SEL_RB2_RPTR_WRAP = 25
IH_PERF_SEL_STORM_CLIENT_INT_DROP = 26
IH_PERF_SEL_SELF_IV_VALID = 27
IH_PERF_SEL_BUFFER_FIFO_FULL = 28
IH_PERF_SEL_RB0_FULL_VF0 = 29
IH_PERF_SEL_RB0_FULL_VF1 = 30
IH_PERF_SEL_RB0_FULL_VF2 = 31
IH_PERF_SEL_RB0_FULL_VF3 = 32
IH_PERF_SEL_RB0_FULL_VF4 = 33
IH_PERF_SEL_RB0_FULL_VF5 = 34
IH_PERF_SEL_RB0_FULL_VF6 = 35
IH_PERF_SEL_RB0_FULL_VF7 = 36
IH_PERF_SEL_RB0_FULL_VF8 = 37
IH_PERF_SEL_RB0_FULL_VF9 = 38
IH_PERF_SEL_RB0_FULL_VF10 = 39
IH_PERF_SEL_RB0_FULL_VF11 = 40
IH_PERF_SEL_RB0_FULL_VF12 = 41
IH_PERF_SEL_RB0_FULL_VF13 = 42
IH_PERF_SEL_RB0_FULL_VF14 = 43
IH_PERF_SEL_RB0_FULL_VF15 = 44
IH_PERF_SEL_RB0_OVERFLOW_VF0 = 45
IH_PERF_SEL_RB0_OVERFLOW_VF1 = 46
IH_PERF_SEL_RB0_OVERFLOW_VF2 = 47
IH_PERF_SEL_RB0_OVERFLOW_VF3 = 48
IH_PERF_SEL_RB0_OVERFLOW_VF4 = 49
IH_PERF_SEL_RB0_OVERFLOW_VF5 = 50
IH_PERF_SEL_RB0_OVERFLOW_VF6 = 51
IH_PERF_SEL_RB0_OVERFLOW_VF7 = 52
IH_PERF_SEL_RB0_OVERFLOW_VF8 = 53
IH_PERF_SEL_RB0_OVERFLOW_VF9 = 54
IH_PERF_SEL_RB0_OVERFLOW_VF10 = 55
IH_PERF_SEL_RB0_OVERFLOW_VF11 = 56
IH_PERF_SEL_RB0_OVERFLOW_VF12 = 57
IH_PERF_SEL_RB0_OVERFLOW_VF13 = 58
IH_PERF_SEL_RB0_OVERFLOW_VF14 = 59
IH_PERF_SEL_RB0_OVERFLOW_VF15 = 60
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 61
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 62
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 63
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 64
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 65
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 66
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 67
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 68
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 69
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 70
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 71
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 72
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 73
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 74
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 75
IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 76
IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 77
IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 78
IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 79
IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 80
IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 81
IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 82
IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 83
IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 84
IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 85
IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 86
IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 87
IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 88
IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 89
IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 90
IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 91
IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 92
IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 93
IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 94
IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 95
IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 96
IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 97
IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 98
IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 99
IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 100
IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 101
IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 102
IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 103
IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 104
IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 105
IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 106
IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 107
IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 108
IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 109
IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 110
IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 111
IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 112
IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 113
IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 114
IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 115
IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 116
IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 117
IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 118
IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 119
IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 120
IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 121
IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 122
IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 123
IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 124
IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 125
IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 126
IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 127
IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 128
IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 129
IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 130
IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 131
IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 132
IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 133
IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 134
IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 135
IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 136
IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 137
IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 138
IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 139
IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 140
IH_PERF_SEL_CLIENT0_INT = 141
IH_PERF_SEL_CLIENT1_INT = 142
IH_PERF_SEL_CLIENT2_INT = 143
IH_PERF_SEL_CLIENT3_INT = 144
IH_PERF_SEL_CLIENT4_INT = 145
IH_PERF_SEL_CLIENT5_INT = 146
IH_PERF_SEL_CLIENT6_INT = 147
IH_PERF_SEL_CLIENT7_INT = 148
IH_PERF_SEL_CLIENT8_INT = 149
IH_PERF_SEL_CLIENT9_INT = 150
IH_PERF_SEL_CLIENT10_INT = 151
IH_PERF_SEL_CLIENT11_INT = 152
IH_PERF_SEL_CLIENT12_INT = 153
IH_PERF_SEL_CLIENT13_INT = 154
IH_PERF_SEL_CLIENT14_INT = 155
IH_PERF_SEL_CLIENT15_INT = 156
IH_PERF_SEL_CLIENT16_INT = 157
IH_PERF_SEL_CLIENT17_INT = 158
IH_PERF_SEL_CLIENT18_INT = 159
IH_PERF_SEL_CLIENT19_INT = 160
IH_PERF_SEL_CLIENT20_INT = 161
IH_PERF_SEL_CLIENT21_INT = 162
IH_PERF_SEL_CLIENT22_INT = 163
IH_PERF_SEL_CLIENT23_INT = 164
IH_PERF_SEL_CLIENT24_INT = 165
IH_PERF_SEL_CLIENT25_INT = 166
IH_PERF_SEL_CLIENT26_INT = 167
IH_PERF_SEL_CLIENT27_INT = 168
IH_PERF_SEL_CLIENT28_INT = 169
IH_PERF_SEL_CLIENT29_INT = 170
IH_PERF_SEL_CLIENT30_INT = 171
IH_PERF_SEL_CLIENT31_INT = 172
IH_PERF_SEL_RB1_FULL_VF0 = 173
IH_PERF_SEL_RB1_FULL_VF1 = 174
IH_PERF_SEL_RB1_FULL_VF2 = 175
IH_PERF_SEL_RB1_FULL_VF3 = 176
IH_PERF_SEL_RB1_FULL_VF4 = 177
IH_PERF_SEL_RB1_FULL_VF5 = 178
IH_PERF_SEL_RB1_FULL_VF6 = 179
IH_PERF_SEL_RB1_FULL_VF7 = 180
IH_PERF_SEL_RB1_FULL_VF8 = 181
IH_PERF_SEL_RB1_FULL_VF9 = 182
IH_PERF_SEL_RB1_FULL_VF10 = 183
IH_PERF_SEL_RB1_FULL_VF11 = 184
IH_PERF_SEL_RB1_FULL_VF12 = 185
IH_PERF_SEL_RB1_FULL_VF13 = 186
IH_PERF_SEL_RB1_FULL_VF14 = 187
IH_PERF_SEL_RB1_FULL_VF15 = 188
IH_PERF_SEL_RB1_OVERFLOW_VF0 = 189
IH_PERF_SEL_RB1_OVERFLOW_VF1 = 190
IH_PERF_SEL_RB1_OVERFLOW_VF2 = 191
IH_PERF_SEL_RB1_OVERFLOW_VF3 = 192
IH_PERF_SEL_RB1_OVERFLOW_VF4 = 193
IH_PERF_SEL_RB1_OVERFLOW_VF5 = 194
IH_PERF_SEL_RB1_OVERFLOW_VF6 = 195
IH_PERF_SEL_RB1_OVERFLOW_VF7 = 196
IH_PERF_SEL_RB1_OVERFLOW_VF8 = 197
IH_PERF_SEL_RB1_OVERFLOW_VF9 = 198
IH_PERF_SEL_RB1_OVERFLOW_VF10 = 199
IH_PERF_SEL_RB1_OVERFLOW_VF11 = 200
IH_PERF_SEL_RB1_OVERFLOW_VF12 = 201
IH_PERF_SEL_RB1_OVERFLOW_VF13 = 202
IH_PERF_SEL_RB1_OVERFLOW_VF14 = 203
IH_PERF_SEL_RB1_OVERFLOW_VF15 = 204
IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 205
IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 206
IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 207
IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 208
IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 209
IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 210
IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 211
IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 212
IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 213
IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 214
IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 215
IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 216
IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 217
IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 218
IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 219
IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 220
IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 221
IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 222
IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 223
IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 224
IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 225
IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 226
IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 227
IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 228
IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 229
IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 230
IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 231
IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 232
IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 233
IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 234
IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 235
IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 236
IH_PERF_SEL_RB2_FULL_VF0 = 237
IH_PERF_SEL_RB2_FULL_VF1 = 238
IH_PERF_SEL_RB2_FULL_VF2 = 239
IH_PERF_SEL_RB2_FULL_VF3 = 240
IH_PERF_SEL_RB2_FULL_VF4 = 241
IH_PERF_SEL_RB2_FULL_VF5 = 242
IH_PERF_SEL_RB2_FULL_VF6 = 243
IH_PERF_SEL_RB2_FULL_VF7 = 244
IH_PERF_SEL_RB2_FULL_VF8 = 245
IH_PERF_SEL_RB2_FULL_VF9 = 246
IH_PERF_SEL_RB2_FULL_VF10 = 247
IH_PERF_SEL_RB2_FULL_VF11 = 248
IH_PERF_SEL_RB2_FULL_VF12 = 249
IH_PERF_SEL_RB2_FULL_VF13 = 250
IH_PERF_SEL_RB2_FULL_VF14 = 251
IH_PERF_SEL_RB2_FULL_VF15 = 252
IH_PERF_SEL_RB2_OVERFLOW_VF0 = 253
IH_PERF_SEL_RB2_OVERFLOW_VF1 = 254
IH_PERF_SEL_RB2_OVERFLOW_VF2 = 255
IH_PERF_SEL_RB2_OVERFLOW_VF3 = 256
IH_PERF_SEL_RB2_OVERFLOW_VF4 = 257
IH_PERF_SEL_RB2_OVERFLOW_VF5 = 258
IH_PERF_SEL_RB2_OVERFLOW_VF6 = 259
IH_PERF_SEL_RB2_OVERFLOW_VF7 = 260
IH_PERF_SEL_RB2_OVERFLOW_VF8 = 261
IH_PERF_SEL_RB2_OVERFLOW_VF9 = 262
IH_PERF_SEL_RB2_OVERFLOW_VF10 = 263
IH_PERF_SEL_RB2_OVERFLOW_VF11 = 264
IH_PERF_SEL_RB2_OVERFLOW_VF12 = 265
IH_PERF_SEL_RB2_OVERFLOW_VF13 = 266
IH_PERF_SEL_RB2_OVERFLOW_VF14 = 267
IH_PERF_SEL_RB2_OVERFLOW_VF15 = 268
IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 269
IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 270
IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 271
IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 272
IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 273
IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 274
IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 275
IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 276
IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 277
IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 278
IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 279
IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 280
IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 281
IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 282
IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 283
IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 284
IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 285
IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 286
IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 287
IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 288
IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 289
IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 290
IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 291
IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 292
IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 293
IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 294
IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 295
IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 296
IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 297
IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 298
IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 299
IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 300
IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 301
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 302
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 303
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 304
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 305
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 306
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 307
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 308
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 309
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 310
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 311
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 312
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 313
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 314
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 315
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 316
IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 317
IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 318
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 319
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 320
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 321
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 322
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 323
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 324
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 325
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 326
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 327
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 328
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 329
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 330
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 331
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 332
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 333
IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 334
IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 335
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 336
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 337
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 338
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 339
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 340
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 341
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 342
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 343
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 344
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 345
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 346
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 347
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 348
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 349
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 350
IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 351
IH_PERF_SEL_RB0_LOAD_RPTR = 352
IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 353
IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 354
IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 355
IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 356
IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 357
IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 358
IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 359
IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 360
IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 361
IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 362
IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 363
IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 364
IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 365
IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 366
IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 367
IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 368
IH_PERF_SEL_RB1_LOAD_RPTR = 369
IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 370
IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 371
IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 372
IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 373
IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 374
IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 375
IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 376
IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 377
IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 378
IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 379
IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 380
IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 381
IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 382
IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 383
IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 384
IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 385
IH_PERF_SEL_RB2_LOAD_RPTR = 386
IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 387
IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 388
IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 389
IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 390
IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 391
IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 392
IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 393
IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 394
IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 395
IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 396
IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 397
IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 398
IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 399
IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 400
IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 401
IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 402
IH_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'IH_RING_ID'
IH_RING_ID__enumvalues = {
0: 'IH_RING_ID_INTERRUPT',
1: 'IH_RING_ID_REQUEST',
2: 'IH_RING_ID_TRANSLATION',
3: 'IH_RING_ID_RESERVED',
}
IH_RING_ID_INTERRUPT = 0
IH_RING_ID_REQUEST = 1
IH_RING_ID_TRANSLATION = 2
IH_RING_ID_RESERVED = 3
IH_RING_ID = ctypes.c_uint32 # enum
# values for enumeration 'IH_VF_RB_SELECT'
IH_VF_RB_SELECT__enumvalues = {
0: 'IH_VF_RB_SELECT_CLIENT_FCN_ID',
1: 'IH_VF_RB_SELECT_IH_FCN_ID',
2: 'IH_VF_RB_SELECT_PF',
3: 'IH_VF_RB_SELECT_RESERVED',
}
IH_VF_RB_SELECT_CLIENT_FCN_ID = 0
IH_VF_RB_SELECT_IH_FCN_ID = 1
IH_VF_RB_SELECT_PF = 2
IH_VF_RB_SELECT_RESERVED = 3
IH_VF_RB_SELECT = ctypes.c_uint32 # enum
# values for enumeration 'SEM_PERF_SEL'
SEM_PERF_SEL__enumvalues = {
0: 'SEM_PERF_SEL_CYCLE',
1: 'SEM_PERF_SEL_IDLE',
2: 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL',
3: 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL',
4: 'SEM_PERF_SEL_SDMA2_REQ_SIGNAL',
5: 'SEM_PERF_SEL_SDMA3_REQ_SIGNAL',
6: 'SEM_PERF_SEL_UVD_REQ_SIGNAL',
7: 'SEM_PERF_SEL_UVD1_REQ_SIGNAL',
8: 'SEM_PERF_SEL_VCE0_REQ_SIGNAL',
9: 'SEM_PERF_SEL_ACP_REQ_SIGNAL',
10: 'SEM_PERF_SEL_ISP_REQ_SIGNAL',
11: 'SEM_PERF_SEL_VCE1_REQ_SIGNAL',
12: 'SEM_PERF_SEL_VP8_REQ_SIGNAL',
13: 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL',
14: 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL',
15: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL',
16: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL',
17: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL',
18: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL',
19: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL',
20: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL',
21: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL',
22: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL',
23: 'SEM_PERF_SEL_SDMA0_REQ_WAIT',
24: 'SEM_PERF_SEL_SDMA1_REQ_WAIT',
25: 'SEM_PERF_SEL_SDMA2_REQ_WAIT',
26: 'SEM_PERF_SEL_SDMA3_REQ_WAIT',
27: 'SEM_PERF_SEL_UVD_REQ_WAIT',
28: 'SEM_PERF_SEL_UVD1_REQ_WAIT',
29: 'SEM_PERF_SEL_VCE0_REQ_WAIT',
30: 'SEM_PERF_SEL_ACP_REQ_WAIT',
31: 'SEM_PERF_SEL_ISP_REQ_WAIT',
32: 'SEM_PERF_SEL_VCE1_REQ_WAIT',
33: 'SEM_PERF_SEL_VP8_REQ_WAIT',
34: 'SEM_PERF_SEL_CPG_E0_REQ_WAIT',
35: 'SEM_PERF_SEL_CPG_E1_REQ_WAIT',
36: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT',
37: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT',
38: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT',
39: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT',
40: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT',
41: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT',
42: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT',
43: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT',
44: 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT',
45: 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT',
46: 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT',
47: 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT',
48: 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT',
49: 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT',
50: 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT',
51: 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT',
52: 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT',
53: 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT',
54: 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT',
55: 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT',
56: 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT',
57: 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT',
58: 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT',
59: 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT',
60: 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT',
61: 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT',
62: 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT',
63: 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT',
64: 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT',
65: 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT',
66: 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT',
67: 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT',
68: 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT',
69: 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT',
70: 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT',
71: 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT',
72: 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT',
73: 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT',
74: 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT',
75: 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT',
76: 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT',
77: 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT',
78: 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT',
79: 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT',
80: 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT',
81: 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT',
82: 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT',
83: 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT',
84: 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT',
85: 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT',
86: 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT',
87: 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT',
88: 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT',
89: 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT',
90: 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT',
91: 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT',
92: 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT',
93: 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT',
94: 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT',
95: 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT',
96: 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT',
97: 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT',
98: 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT',
99: 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT',
100: 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT',
101: 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT',
102: 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT',
103: 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT',
104: 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT',
105: 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT',
106: 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT',
107: 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT',
108: 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT',
109: 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT',
110: 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT',
111: 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT',
112: 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT',
113: 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT',
114: 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT',
115: 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT',
116: 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT',
117: 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT',
118: 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT',
119: 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT',
120: 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT',
121: 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT',
122: 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT',
123: 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT',
124: 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT',
125: 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT',
126: 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT',
127: 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT',
128: 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT',
129: 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT',
130: 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT',
131: 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT',
132: 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT',
133: 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT',
134: 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT',
135: 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT',
136: 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT',
137: 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT',
138: 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT',
139: 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT',
140: 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT',
141: 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT',
142: 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT',
143: 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT',
144: 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT',
145: 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT',
146: 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT',
147: 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT',
148: 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT',
149: 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT',
150: 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT',
151: 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT',
152: 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT',
153: 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT',
154: 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT',
155: 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT',
156: 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT',
157: 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT',
158: 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT',
159: 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT',
160: 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT',
161: 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT',
162: 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT',
163: 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT',
164: 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT',
165: 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT',
166: 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT',
167: 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT',
168: 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT',
169: 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT',
170: 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT',
171: 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT',
172: 'SEM_PERF_SEL_MC_RD_REQ',
173: 'SEM_PERF_SEL_MC_RD_RET',
174: 'SEM_PERF_SEL_MC_WR_REQ',
175: 'SEM_PERF_SEL_MC_WR_RET',
176: 'SEM_PERF_SEL_ATC_REQ',
177: 'SEM_PERF_SEL_ATC_RET',
178: 'SEM_PERF_SEL_ATC_XNACK',
179: 'SEM_PERF_SEL_ATC_INVALIDATION',
180: 'SEM_PERF_SEL_ATC_VM_INVALIDATION',
}
SEM_PERF_SEL_CYCLE = 0
SEM_PERF_SEL_IDLE = 1
SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 2
SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 3
SEM_PERF_SEL_SDMA2_REQ_SIGNAL = 4
SEM_PERF_SEL_SDMA3_REQ_SIGNAL = 5
SEM_PERF_SEL_UVD_REQ_SIGNAL = 6
SEM_PERF_SEL_UVD1_REQ_SIGNAL = 7
SEM_PERF_SEL_VCE0_REQ_SIGNAL = 8
SEM_PERF_SEL_ACP_REQ_SIGNAL = 9
SEM_PERF_SEL_ISP_REQ_SIGNAL = 10
SEM_PERF_SEL_VCE1_REQ_SIGNAL = 11
SEM_PERF_SEL_VP8_REQ_SIGNAL = 12
SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 13
SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 14
SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 15
SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 16
SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 17
SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 18
SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 19
SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 20
SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 21
SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 22
SEM_PERF_SEL_SDMA0_REQ_WAIT = 23
SEM_PERF_SEL_SDMA1_REQ_WAIT = 24
SEM_PERF_SEL_SDMA2_REQ_WAIT = 25
SEM_PERF_SEL_SDMA3_REQ_WAIT = 26
SEM_PERF_SEL_UVD_REQ_WAIT = 27
SEM_PERF_SEL_UVD1_REQ_WAIT = 28
SEM_PERF_SEL_VCE0_REQ_WAIT = 29
SEM_PERF_SEL_ACP_REQ_WAIT = 30
SEM_PERF_SEL_ISP_REQ_WAIT = 31
SEM_PERF_SEL_VCE1_REQ_WAIT = 32
SEM_PERF_SEL_VP8_REQ_WAIT = 33
SEM_PERF_SEL_CPG_E0_REQ_WAIT = 34
SEM_PERF_SEL_CPG_E1_REQ_WAIT = 35
SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 36
SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 37
SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 38
SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 39
SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 40
SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 41
SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 42
SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 43
SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 44
SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 45
SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 46
SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 47
SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 48
SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 49
SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 50
SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 51
SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 52
SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 53
SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 54
SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 55
SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 56
SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 57
SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 58
SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 59
SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 60
SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 61
SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 62
SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 63
SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 64
SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 65
SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 66
SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 67
SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 68
SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 69
SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 70
SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 71
SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 72
SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 73
SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 74
SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 75
SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 76
SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 77
SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 78
SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 79
SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 80
SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 81
SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 82
SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 83
SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 84
SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 85
SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 86
SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 87
SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 88
SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 89
SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 90
SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 91
SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 92
SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 93
SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 94
SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 95
SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 96
SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 97
SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 98
SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 99
SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 100
SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 101
SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 102
SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 103
SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 104
SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 105
SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 106
SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 107
SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 108
SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 109
SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 110
SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 111
SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 112
SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 113
SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 114
SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 115
SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 116
SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 117
SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 118
SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 119
SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 120
SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 121
SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 122
SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 123
SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 124
SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 125
SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 126
SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 127
SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 128
SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 129
SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 130
SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 131
SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 132
SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 133
SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 134
SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 135
SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 136
SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 137
SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 138
SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 139
SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 140
SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 141
SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 142
SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 143
SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 144
SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 145
SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 146
SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 147
SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 148
SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 149
SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 150
SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 151
SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 152
SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 153
SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 154
SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 155
SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 156
SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 157
SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 158
SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 159
SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 160
SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 161
SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 162
SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 163
SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 164
SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 165
SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 166
SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 167
SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 168
SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 169
SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 170
SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 171
SEM_PERF_SEL_MC_RD_REQ = 172
SEM_PERF_SEL_MC_RD_RET = 173
SEM_PERF_SEL_MC_WR_REQ = 174
SEM_PERF_SEL_MC_WR_RET = 175
SEM_PERF_SEL_ATC_REQ = 176
SEM_PERF_SEL_ATC_RET = 177
SEM_PERF_SEL_ATC_XNACK = 178
SEM_PERF_SEL_ATC_INVALIDATION = 179
SEM_PERF_SEL_ATC_VM_INVALIDATION = 180
SEM_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'LSDMA_PERF_SEL'
LSDMA_PERF_SEL__enumvalues = {
0: 'LSDMA_PERF_SEL_CYCLE',
1: 'LSDMA_PERF_SEL_IDLE',
2: 'LSDMA_PERF_SEL_REG_IDLE',
3: 'LSDMA_PERF_SEL_RB_EMPTY',
4: 'LSDMA_PERF_SEL_RB_FULL',
5: 'LSDMA_PERF_SEL_RB_WPTR_WRAP',
6: 'LSDMA_PERF_SEL_RB_RPTR_WRAP',
7: 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ',
8: 'LSDMA_PERF_SEL_RB_RPTR_WB',
9: 'LSDMA_PERF_SEL_RB_CMD_IDLE',
10: 'LSDMA_PERF_SEL_RB_CMD_FULL',
11: 'LSDMA_PERF_SEL_IB_CMD_IDLE',
12: 'LSDMA_PERF_SEL_IB_CMD_FULL',
13: 'LSDMA_PERF_SEL_EX_IDLE',
14: 'LSDMA_PERF_SEL_SRBM_REG_SEND',
15: 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
16: 'LSDMA_PERF_SEL_MC_WR_IDLE',
17: 'LSDMA_PERF_SEL_MC_WR_COUNT',
18: 'LSDMA_PERF_SEL_MC_RD_IDLE',
19: 'LSDMA_PERF_SEL_MC_RD_COUNT',
20: 'LSDMA_PERF_SEL_MC_RD_RET_STALL',
21: 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE',
24: 'LSDMA_PERF_SEL_SEM_IDLE',
25: 'LSDMA_PERF_SEL_SEM_REQ_STALL',
26: 'LSDMA_PERF_SEL_SEM_REQ_COUNT',
27: 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE',
28: 'LSDMA_PERF_SEL_SEM_RESP_FAIL',
29: 'LSDMA_PERF_SEL_SEM_RESP_PASS',
30: 'LSDMA_PERF_SEL_INT_IDLE',
31: 'LSDMA_PERF_SEL_INT_REQ_STALL',
32: 'LSDMA_PERF_SEL_INT_REQ_COUNT',
33: 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED',
34: 'LSDMA_PERF_SEL_INT_RESP_RETRY',
35: 'LSDMA_PERF_SEL_NUM_PACKET',
37: 'LSDMA_PERF_SEL_CE_WREQ_IDLE',
38: 'LSDMA_PERF_SEL_CE_WR_IDLE',
39: 'LSDMA_PERF_SEL_CE_SPLIT_IDLE',
40: 'LSDMA_PERF_SEL_CE_RREQ_IDLE',
41: 'LSDMA_PERF_SEL_CE_OUT_IDLE',
42: 'LSDMA_PERF_SEL_CE_IN_IDLE',
43: 'LSDMA_PERF_SEL_CE_DST_IDLE',
46: 'LSDMA_PERF_SEL_CE_AFIFO_FULL',
49: 'LSDMA_PERF_SEL_CE_INFO_FULL',
50: 'LSDMA_PERF_SEL_CE_INFO1_FULL',
51: 'LSDMA_PERF_SEL_CE_RD_STALL',
52: 'LSDMA_PERF_SEL_CE_WR_STALL',
53: 'LSDMA_PERF_SEL_GFX_SELECT',
54: 'LSDMA_PERF_SEL_RLC0_SELECT',
55: 'LSDMA_PERF_SEL_RLC1_SELECT',
56: 'LSDMA_PERF_SEL_PAGE_SELECT',
57: 'LSDMA_PERF_SEL_CTX_CHANGE',
58: 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED',
59: 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION',
60: 'LSDMA_PERF_SEL_DOORBELL',
61: 'LSDMA_PERF_SEL_RD_BA_RTR',
62: 'LSDMA_PERF_SEL_WR_BA_RTR',
63: 'LSDMA_PERF_SEL_F32_L1_WR_VLD',
64: 'LSDMA_PERF_SEL_CE_L1_WR_VLD',
65: 'LSDMA_PERF_SEL_CE_L1_STALL',
66: 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH',
67: 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH',
68: 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH',
69: 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH',
70: 'LSDMA_PERF_SEL_ATCL2_RET_XNACK',
71: 'LSDMA_PERF_SEL_ATCL2_RET_ACK',
72: 'LSDMA_PERF_SEL_ATCL2_FREE',
73: 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND',
74: 'LSDMA_PERF_SEL_DMA_L1_WR_SEND',
75: 'LSDMA_PERF_SEL_DMA_L1_RD_SEND',
76: 'LSDMA_PERF_SEL_DMA_MC_WR_SEND',
77: 'LSDMA_PERF_SEL_DMA_MC_RD_SEND',
78: 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE',
79: 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE',
80: 'LSDMA_PERF_SEL_L1_WRL2_IDLE',
81: 'LSDMA_PERF_SEL_L1_RDL2_IDLE',
82: 'LSDMA_PERF_SEL_L1_WRMC_IDLE',
83: 'LSDMA_PERF_SEL_L1_RDMC_IDLE',
84: 'LSDMA_PERF_SEL_L1_WR_INV_IDLE',
85: 'LSDMA_PERF_SEL_L1_RD_INV_IDLE',
86: 'LSDMA_PERF_SEL_L1_WR_INV_EN',
87: 'LSDMA_PERF_SEL_L1_RD_INV_EN',
88: 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR',
89: 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR',
90: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR',
91: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD',
92: 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT',
93: 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT',
94: 'LSDMA_PERF_SEL_L1_INV_MIDDLE',
95: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ',
96: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET',
97: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ',
98: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET',
99: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ',
100: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET',
101: 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ',
102: 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET',
103: 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ',
104: 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET',
105: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ',
106: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET',
107: 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ',
108: 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET',
109: 'LSDMA_PERF_SEL_CMD_OP_MATCH',
110: 'LSDMA_PERF_SEL_CMD_OP_START',
111: 'LSDMA_PERF_SEL_CMD_OP_END',
112: 'LSDMA_PERF_SEL_CE_BUSY',
113: 'LSDMA_PERF_SEL_CE_BUSY_START',
114: 'LSDMA_PERF_SEL_CE_BUSY_END',
115: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER',
116: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START',
117: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END',
118: 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND',
119: 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID',
120: 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND',
121: 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID',
122: 'LSDMA_PERF_SEL_DRAM_ECC',
123: 'LSDMA_PERF_SEL_NACK_GEN_ERR',
}
LSDMA_PERF_SEL_CYCLE = 0
LSDMA_PERF_SEL_IDLE = 1
LSDMA_PERF_SEL_REG_IDLE = 2
LSDMA_PERF_SEL_RB_EMPTY = 3
LSDMA_PERF_SEL_RB_FULL = 4
LSDMA_PERF_SEL_RB_WPTR_WRAP = 5
LSDMA_PERF_SEL_RB_RPTR_WRAP = 6
LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 7
LSDMA_PERF_SEL_RB_RPTR_WB = 8
LSDMA_PERF_SEL_RB_CMD_IDLE = 9
LSDMA_PERF_SEL_RB_CMD_FULL = 10
LSDMA_PERF_SEL_IB_CMD_IDLE = 11
LSDMA_PERF_SEL_IB_CMD_FULL = 12
LSDMA_PERF_SEL_EX_IDLE = 13
LSDMA_PERF_SEL_SRBM_REG_SEND = 14
LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15
LSDMA_PERF_SEL_MC_WR_IDLE = 16
LSDMA_PERF_SEL_MC_WR_COUNT = 17
LSDMA_PERF_SEL_MC_RD_IDLE = 18
LSDMA_PERF_SEL_MC_RD_COUNT = 19
LSDMA_PERF_SEL_MC_RD_RET_STALL = 20
LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21
LSDMA_PERF_SEL_SEM_IDLE = 24
LSDMA_PERF_SEL_SEM_REQ_STALL = 25
LSDMA_PERF_SEL_SEM_REQ_COUNT = 26
LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27
LSDMA_PERF_SEL_SEM_RESP_FAIL = 28
LSDMA_PERF_SEL_SEM_RESP_PASS = 29
LSDMA_PERF_SEL_INT_IDLE = 30
LSDMA_PERF_SEL_INT_REQ_STALL = 31
LSDMA_PERF_SEL_INT_REQ_COUNT = 32
LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 33
LSDMA_PERF_SEL_INT_RESP_RETRY = 34
LSDMA_PERF_SEL_NUM_PACKET = 35
LSDMA_PERF_SEL_CE_WREQ_IDLE = 37
LSDMA_PERF_SEL_CE_WR_IDLE = 38
LSDMA_PERF_SEL_CE_SPLIT_IDLE = 39
LSDMA_PERF_SEL_CE_RREQ_IDLE = 40
LSDMA_PERF_SEL_CE_OUT_IDLE = 41
LSDMA_PERF_SEL_CE_IN_IDLE = 42
LSDMA_PERF_SEL_CE_DST_IDLE = 43
LSDMA_PERF_SEL_CE_AFIFO_FULL = 46
LSDMA_PERF_SEL_CE_INFO_FULL = 49
LSDMA_PERF_SEL_CE_INFO1_FULL = 50
LSDMA_PERF_SEL_CE_RD_STALL = 51
LSDMA_PERF_SEL_CE_WR_STALL = 52
LSDMA_PERF_SEL_GFX_SELECT = 53
LSDMA_PERF_SEL_RLC0_SELECT = 54
LSDMA_PERF_SEL_RLC1_SELECT = 55
LSDMA_PERF_SEL_PAGE_SELECT = 56
LSDMA_PERF_SEL_CTX_CHANGE = 57
LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58
LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59
LSDMA_PERF_SEL_DOORBELL = 60
LSDMA_PERF_SEL_RD_BA_RTR = 61
LSDMA_PERF_SEL_WR_BA_RTR = 62
LSDMA_PERF_SEL_F32_L1_WR_VLD = 63
LSDMA_PERF_SEL_CE_L1_WR_VLD = 64
LSDMA_PERF_SEL_CE_L1_STALL = 65
LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 66
LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 67
LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 68
LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 69
LSDMA_PERF_SEL_ATCL2_RET_XNACK = 70
LSDMA_PERF_SEL_ATCL2_RET_ACK = 71
LSDMA_PERF_SEL_ATCL2_FREE = 72
LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 73
LSDMA_PERF_SEL_DMA_L1_WR_SEND = 74
LSDMA_PERF_SEL_DMA_L1_RD_SEND = 75
LSDMA_PERF_SEL_DMA_MC_WR_SEND = 76
LSDMA_PERF_SEL_DMA_MC_RD_SEND = 77
LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 78
LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 79
LSDMA_PERF_SEL_L1_WRL2_IDLE = 80
LSDMA_PERF_SEL_L1_RDL2_IDLE = 81
LSDMA_PERF_SEL_L1_WRMC_IDLE = 82
LSDMA_PERF_SEL_L1_RDMC_IDLE = 83
LSDMA_PERF_SEL_L1_WR_INV_IDLE = 84
LSDMA_PERF_SEL_L1_RD_INV_IDLE = 85
LSDMA_PERF_SEL_L1_WR_INV_EN = 86
LSDMA_PERF_SEL_L1_RD_INV_EN = 87
LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 88
LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 89
LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 90
LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 91
LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 92
LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 93
LSDMA_PERF_SEL_L1_INV_MIDDLE = 94
LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 95
LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 96
LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 97
LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 98
LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 99
LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 100
LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 101
LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 102
LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 103
LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 104
LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 105
LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 106
LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 107
LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 108
LSDMA_PERF_SEL_CMD_OP_MATCH = 109
LSDMA_PERF_SEL_CMD_OP_START = 110
LSDMA_PERF_SEL_CMD_OP_END = 111
LSDMA_PERF_SEL_CE_BUSY = 112
LSDMA_PERF_SEL_CE_BUSY_START = 113
LSDMA_PERF_SEL_CE_BUSY_END = 114
LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 115
LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 116
LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 117
LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 118
LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 119
LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 120
LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 121
LSDMA_PERF_SEL_DRAM_ECC = 122
LSDMA_PERF_SEL_NACK_GEN_ERR = 123
LSDMA_PERF_SEL = ctypes.c_uint32 # enum
# values for enumeration 'EFC_SURFACE_PIXEL_FORMAT'
EFC_SURFACE_PIXEL_FORMAT__enumvalues = {
1: 'EFC_ARGB1555',
2: 'EFC_RGBA5551',
3: 'EFC_RGB565',
4: 'EFC_BGR565',
5: 'EFC_ARGB4444',
6: 'EFC_RGBA4444',
8: 'EFC_ARGB8888',
9: 'EFC_RGBA8888',
10: 'EFC_ARGB2101010',
11: 'EFC_RGBA1010102',
12: 'EFC_AYCrCb8888',
13: 'EFC_YCrCbA8888',
14: 'EFC_ACrYCb8888',
15: 'EFC_CrYCbA8888',
16: 'EFC_ARGB16161616_10MSB',
17: 'EFC_RGBA16161616_10MSB',
18: 'EFC_ARGB16161616_10LSB',
19: 'EFC_RGBA16161616_10LSB',
20: 'EFC_ARGB16161616_12MSB',
21: 'EFC_RGBA16161616_12MSB',
22: 'EFC_ARGB16161616_12LSB',
23: 'EFC_RGBA16161616_12LSB',
24: 'EFC_ARGB16161616_FLOAT',
25: 'EFC_RGBA16161616_FLOAT',
26: 'EFC_ARGB16161616_UNORM',
27: 'EFC_RGBA16161616_UNORM',
28: 'EFC_ARGB16161616_SNORM',
29: 'EFC_RGBA16161616_SNORM',
32: 'EFC_AYCrCb16161616_10MSB',
33: 'EFC_AYCrCb16161616_10LSB',
34: 'EFC_YCrCbA16161616_10MSB',
35: 'EFC_YCrCbA16161616_10LSB',
36: 'EFC_ACrYCb16161616_10MSB',
37: 'EFC_ACrYCb16161616_10LSB',
38: 'EFC_CrYCbA16161616_10MSB',
39: 'EFC_CrYCbA16161616_10LSB',
40: 'EFC_AYCrCb16161616_12MSB',
41: 'EFC_AYCrCb16161616_12LSB',
42: 'EFC_YCrCbA16161616_12MSB',
43: 'EFC_YCrCbA16161616_12LSB',
44: 'EFC_ACrYCb16161616_12MSB',
45: 'EFC_ACrYCb16161616_12LSB',
46: 'EFC_CrYCbA16161616_12MSB',
47: 'EFC_CrYCbA16161616_12LSB',
64: 'EFC_Y8_CrCb88_420_PLANAR',
65: 'EFC_Y8_CbCr88_420_PLANAR',
66: 'EFC_Y10_CrCb1010_420_PLANAR',
67: 'EFC_Y10_CbCr1010_420_PLANAR',
68: 'EFC_Y12_CrCb1212_420_PLANAR',
69: 'EFC_Y12_CbCr1212_420_PLANAR',
72: 'EFC_YCrYCb8888_422_PACKED',
73: 'EFC_YCbYCr8888_422_PACKED',
74: 'EFC_CrYCbY8888_422_PACKED',
75: 'EFC_CbYCrY8888_422_PACKED',
76: 'EFC_YCrYCb10101010_422_PACKED',
77: 'EFC_YCbYCr10101010_422_PACKED',
78: 'EFC_CrYCbY10101010_422_PACKED',
79: 'EFC_CbYCrY10101010_422_PACKED',
80: 'EFC_YCrYCb12121212_422_PACKED',
81: 'EFC_YCbYCr12121212_422_PACKED',
82: 'EFC_CrYCbY12121212_422_PACKED',
83: 'EFC_CbYCrY12121212_422_PACKED',
112: 'EFC_RGB111110_FIX',
113: 'EFC_BGR101111_FIX',
114: 'EFC_ACrYCb2101010',
115: 'EFC_CrYCbA1010102',
118: 'EFC_RGB111110_FLOAT',
119: 'EFC_BGR101111_FLOAT',
120: 'EFC_MONO_8',
121: 'EFC_MONO_10MSB',
122: 'EFC_MONO_10LSB',
123: 'EFC_MONO_12MSB',
124: 'EFC_MONO_12LSB',
125: 'EFC_MONO_16',
}
EFC_ARGB1555 = 1
EFC_RGBA5551 = 2
EFC_RGB565 = 3
EFC_BGR565 = 4
EFC_ARGB4444 = 5
EFC_RGBA4444 = 6
EFC_ARGB8888 = 8
EFC_RGBA8888 = 9
EFC_ARGB2101010 = 10
EFC_RGBA1010102 = 11
EFC_AYCrCb8888 = 12
EFC_YCrCbA8888 = 13
EFC_ACrYCb8888 = 14
EFC_CrYCbA8888 = 15
EFC_ARGB16161616_10MSB = 16
EFC_RGBA16161616_10MSB = 17
EFC_ARGB16161616_10LSB = 18
EFC_RGBA16161616_10LSB = 19
EFC_ARGB16161616_12MSB = 20
EFC_RGBA16161616_12MSB = 21
EFC_ARGB16161616_12LSB = 22
EFC_RGBA16161616_12LSB = 23
EFC_ARGB16161616_FLOAT = 24
EFC_RGBA16161616_FLOAT = 25
EFC_ARGB16161616_UNORM = 26
EFC_RGBA16161616_UNORM = 27
EFC_ARGB16161616_SNORM = 28
EFC_RGBA16161616_SNORM = 29
EFC_AYCrCb16161616_10MSB = 32
EFC_AYCrCb16161616_10LSB = 33
EFC_YCrCbA16161616_10MSB = 34
EFC_YCrCbA16161616_10LSB = 35
EFC_ACrYCb16161616_10MSB = 36
EFC_ACrYCb16161616_10LSB = 37
EFC_CrYCbA16161616_10MSB = 38
EFC_CrYCbA16161616_10LSB = 39
EFC_AYCrCb16161616_12MSB = 40
EFC_AYCrCb16161616_12LSB = 41
EFC_YCrCbA16161616_12MSB = 42
EFC_YCrCbA16161616_12LSB = 43
EFC_ACrYCb16161616_12MSB = 44
EFC_ACrYCb16161616_12LSB = 45
EFC_CrYCbA16161616_12MSB = 46
EFC_CrYCbA16161616_12LSB = 47
EFC_Y8_CrCb88_420_PLANAR = 64
EFC_Y8_CbCr88_420_PLANAR = 65
EFC_Y10_CrCb1010_420_PLANAR = 66
EFC_Y10_CbCr1010_420_PLANAR = 67
EFC_Y12_CrCb1212_420_PLANAR = 68
EFC_Y12_CbCr1212_420_PLANAR = 69
EFC_YCrYCb8888_422_PACKED = 72
EFC_YCbYCr8888_422_PACKED = 73
EFC_CrYCbY8888_422_PACKED = 74
EFC_CbYCrY8888_422_PACKED = 75
EFC_YCrYCb10101010_422_PACKED = 76
EFC_YCbYCr10101010_422_PACKED = 77
EFC_CrYCbY10101010_422_PACKED = 78
EFC_CbYCrY10101010_422_PACKED = 79
EFC_YCrYCb12121212_422_PACKED = 80
EFC_YCbYCr12121212_422_PACKED = 81
EFC_CrYCbY12121212_422_PACKED = 82
EFC_CbYCrY12121212_422_PACKED = 83
EFC_RGB111110_FIX = 112
EFC_BGR101111_FIX = 113
EFC_ACrYCb2101010 = 114
EFC_CrYCbA1010102 = 115
EFC_RGB111110_FLOAT = 118
EFC_BGR101111_FLOAT = 119
EFC_MONO_8 = 120
EFC_MONO_10MSB = 121
EFC_MONO_10LSB = 122
EFC_MONO_12MSB = 123
EFC_MONO_12LSB = 124
EFC_MONO_16 = 125
EFC_SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum
__SDMA_V6_0_0_PKT_OPEN_H_ = True # macro
SDMA_OP_NOP = 0 # macro
SDMA_OP_WRITE = 2 # macro
SDMA_OP_INDIRECT = 4 # macro
SDMA_OP_SEM = 7 # macro
SDMA_OP_COND_EXE = 9 # macro
SDMA_OP_PTEPDE = 12 # macro
SDMA_OP_SRBM_WRITE = 14 # macro
SDMA_OP_PRE_EXE = 15 # macro
SDMA_OP_GPUVM_INV = 16 # macro
SDMA_OP_GCR_REQ = 17 # macro
SDMA_OP_DUMMY_TRAP = 32 # macro
SDMA_SUBOP_TIMESTAMP_SET = 0 # macro
SDMA_SUBOP_TIMESTAMP_GET = 1 # macro
SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 # macro
SDMA_SUBOP_COPY_TILED = 1 # macro
SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 # macro
SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 # macro
SDMA_SUBOP_COPY_SOA = 3 # macro
SDMA_SUBOP_COPY_DIRTY_PAGE = 7 # macro
SDMA_SUBOP_COPY_LINEAR_PHY = 8 # macro
SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE = 36 # macro
SDMA_SUBOP_COPY_LINEAR_BC = 16 # macro
SDMA_SUBOP_COPY_TILED_BC = 17 # macro
SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC = 20 # macro
SDMA_SUBOP_COPY_TILED_SUB_WIND_BC = 21 # macro
SDMA_SUBOP_COPY_T2T_SUB_WIND_BC = 22 # macro
SDMA_SUBOP_WRITE_LINEAR = 0 # macro
SDMA_SUBOP_WRITE_TILED = 1 # macro
SDMA_SUBOP_WRITE_TILED_BC = 17 # macro
SDMA_SUBOP_PTEPDE_GEN = 0 # macro
SDMA_SUBOP_PTEPDE_COPY = 1 # macro
SDMA_SUBOP_PTEPDE_RMW = 2 # macro
SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 # macro
SDMA_SUBOP_MEM_INCR = 1 # macro
SDMA_SUBOP_DATA_FILL_MULTI = 1 # macro
SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 # macro
SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 # macro
SDMA_SUBOP_POLL_MEM_VERIFY = 3 # macro
SDMA_SUBOP_VM_INVALIDATION = 4 # macro
HEADER_AGENT_DISPATCH = 4 # macro
HEADER_BARRIER = 5 # macro
SDMA_OP_AQL_COPY = 0 # macro
SDMA_OP_AQL_BARRIER_OR = 0 # macro
SDMA_GCR_RANGE_IS_PA = (1<<18) # macro
def SDMA_GCR_SEQ(x): # macro
return (((x)&0x3)<<16)
SDMA_GCR_GL2_WB = (1<<15) # macro
SDMA_GCR_GL2_INV = (1<<14) # macro
SDMA_GCR_GL2_DISCARD = (1<<13) # macro
def SDMA_GCR_GL2_RANGE(x): # macro
return (((x)&0x3)<<11)
SDMA_GCR_GL2_US = (1<<10) # macro
SDMA_GCR_GL1_INV = (1<<9) # macro
SDMA_GCR_GLV_INV = (1<<8) # macro
SDMA_GCR_GLK_INV = (1<<7) # macro
SDMA_GCR_GLK_WB = (1<<6) # macro
SDMA_GCR_GLM_INV = (1<<5) # macro
SDMA_GCR_GLM_WB = (1<<4) # macro
def SDMA_GCR_GL1_RANGE(x): # macro
return (((x)&0x3)<<2)
def SDMA_GCR_GLI_INV(x): # macro
return (((x)&0x3)<<0)
SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro
SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 # macro
def SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x): # macro
return (((x)&0x00000001)<<16)
SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift = 19 # macro
def SDMA_PKT_COPY_LINEAR_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask = 0x00000001 # macro
SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift = 25 # macro
def SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x): # macro
return (((x)&0x00000001)<<25)
SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro
SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 # macro
def SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x): # macro
return (((x)&0x00000001)<<27)
SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 # macro
SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x3FFFFFFF # macro
SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro
return (((x)&0x3FFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 # macro
SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro
def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset = 2 # macro
SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift = 18 # macro
def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<18)
SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 # macro
SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro
def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset = 2 # macro
SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro
def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<26)
SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro
SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro
SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro
SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro
SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset = 1 # macro
SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask = 0x003FFFFF # macro
SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x): # macro
return (((x)&0x003FFFFF)<<0)
SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset = 2 # macro
SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift = 16 # macro
def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset = 2 # macro
SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask = 0x00000001 # macro
SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift = 19 # macro
def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset = 2 # macro
SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift = 24 # macro
def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset = 2 # macro
SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask = 0x00000001 # macro
SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift = 27 # macro
def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x): # macro
return (((x)&0x00000001)<<27)
SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro
SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro
SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro
SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro
SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 # macro
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset = 0 # macro
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift = 19 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 # macro
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 # macro
SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 # macro
SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF # macro
SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x): # macro
return (((x)&0x003FFFFF)<<0)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask = 0x00000007 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift = 3 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x): # macro
return (((x)&0x00000007)<<3)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift = 6 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x): # macro
return (((x)&0x00000003)<<6)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask = 0x00000001 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift = 8 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_LLC(x): # macro
return (((x)&0x00000001)<<8)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask = 0x00000007 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift = 11 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x): # macro
return (((x)&0x00000007)<<11)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask = 0x00000003 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift = 14 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x): # macro
return (((x)&0x00000003)<<14)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask = 0x00000001 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift = 16 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_LLC(x): # macro
return (((x)&0x00000001)<<16)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 17 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x): # macro
return (((x)&0x00000003)<<17)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x): # macro
return (((x)&0x00000001)<<20)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x): # macro
return (((x)&0x00000001)<<22)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x): # macro
return (((x)&0x00000001)<<23)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x): # macro
return (((x)&0x00000001)<<30)
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 # macro
SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro
SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro
SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro
SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro
SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset = 0 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift = 19 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x): # macro
return (((x)&0x003FFFFF)<<0)
SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset = 1 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask = 0x000000FF # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift = 24 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_ADDR_PAIR_NUM(x): # macro
return (((x)&0x000000FF)<<24)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask = 0x00000007 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift = 3 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x): # macro
return (((x)&0x00000007)<<3)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift = 6 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x): # macro
return (((x)&0x00000003)<<6)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask = 0x00000001 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift = 8 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LLC(x): # macro
return (((x)&0x00000001)<<8)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask = 0x00000007 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift = 11 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x): # macro
return (((x)&0x00000007)<<11)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask = 0x00000003 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift = 14 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x): # macro
return (((x)&0x00000003)<<14)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask = 0x00000001 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift = 16 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_LLC(x): # macro
return (((x)&0x00000001)<<16)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 17 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x): # macro
return (((x)&0x00000003)<<17)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x): # macro
return (((x)&0x00000001)<<20)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x): # macro
return (((x)&0x00000001)<<21)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x): # macro
return (((x)&0x00000001)<<22)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x): # macro
return (((x)&0x00000001)<<23)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x): # macro
return (((x)&0x00000001)<<27)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x): # macro
return (((x)&0x00000001)<<30)
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x): # macro
return (((x)&0x00000001)<<16)
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset = 0 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift = 19 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x): # macro
return (((x)&0x00000001)<<27)
SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x3FFFFFFF # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x): # macro
return (((x)&0x3FFFFFFF)<<0)
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x): # macro
return (((x)&0x00000003)<<8)
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset = 2 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift = 10 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<10)
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset = 2 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift = 18 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<18)
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset = 2 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<26)
SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift = 19 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x): # macro
return (((x)&0x00000007)<<29)
SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x00001FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x): # macro
return (((x)&0x00001FFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x): # macro
return (((x)&0x0007FFFF)<<13)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x): # macro
return (((x)&0x0FFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x00001FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x): # macro
return (((x)&0x00001FFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x): # macro
return (((x)&0x0007FFFF)<<13)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x): # macro
return (((x)&0x0FFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x00001FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x): # macro
return (((x)&0x00001FFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset = 12 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift = 18 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<18)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset = 12 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift = 26 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<26)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift = 19 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset = 3 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_SRC_X(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset = 4 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_SRC_Y(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset = 5 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_SRC_Z(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset = 6 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_SRC_PITCH(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset = 7 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_SRC_SLICE_PITCH_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset = 8 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask = 0x0000FFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_SRC_SLICE_PITCH_47_32(x): # macro
return (((x)&0x0000FFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset = 9 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset = 10 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset = 11 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_DST_X(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset = 12 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_DST_Y(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset = 13 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_DST_Z(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset = 14 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_DST_PITCH(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset = 15 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_DST_SLICE_PITCH_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset = 16 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask = 0x0000FFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SLICE_PITCH_47_32(x): # macro
return (((x)&0x0000FFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset = 16 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift = 16 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset = 16 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift = 18 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_POLICY(x): # macro
return (((x)&0x00000007)<<18)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset = 16 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift = 24 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset = 16 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift = 26 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_POLICY(x): # macro
return (((x)&0x00000007)<<26)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset = 17 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_RECT_X(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset = 18 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_RECT_Y(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset = 19 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_RECT_Z(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset = 0 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask = 0x00000007 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift = 29 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x): # macro
return (((x)&0x00000007)<<29)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset = 3 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset = 3 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift = 16 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset = 4 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask = 0x000007FF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x): # macro
return (((x)&0x000007FF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset = 4 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift = 13 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x): # macro
return (((x)&0x00003FFF)<<13)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset = 5 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x): # macro
return (((x)&0x0FFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset = 8 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset = 8 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift = 16 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset = 9 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask = 0x000007FF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x): # macro
return (((x)&0x000007FF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset = 9 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift = 13 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x): # macro
return (((x)&0x00003FFF)<<13)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset = 10 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x): # macro
return (((x)&0x0FFFFFFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset = 11 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset = 11 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift = 16 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset = 12 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask = 0x000007FF # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift = 0 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x): # macro
return (((x)&0x000007FF)<<0)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset = 12 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift = 16 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset = 12 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask = 0x00000001 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift = 19 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset = 12 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift = 24 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset = 12 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask = 0x00000001 # macro
SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift = 27 # macro
def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x): # macro
return (((x)&0x00000001)<<27)
SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_TILED_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 # macro
SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 # macro
def SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x): # macro
return (((x)&0x00000001)<<16)
SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 # macro
SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_COPY_TILED_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_COPY_TILED_HEADER_cpv_offset = 0 # macro
SDMA_PKT_COPY_TILED_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_HEADER_cpv_shift = 19 # macro
def SDMA_PKT_COPY_TILED_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 # macro
SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 # macro
def SDMA_PKT_COPY_TILED_HEADER_DETILE(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro
SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro
SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 # macro
SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 # macro
def SDMA_PKT_COPY_TILED_DW_3_WIDTH(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 # macro
SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 # macro
def SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 # macro
SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x00001FFF # macro
SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 # macro
def SDMA_PKT_COPY_TILED_DW_4_DEPTH(x): # macro
return (((x)&0x00001FFF)<<16)
SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 # macro
SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 # macro
SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 # macro
def SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x): # macro
return (((x)&0x00000007)<<0)
SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 # macro
SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro
SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 # macro
def SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x): # macro
return (((x)&0x0000001F)<<3)
SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 # macro
SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 # macro
def SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x): # macro
return (((x)&0x00000003)<<9)
SDMA_PKT_COPY_TILED_DW_5_mip_max_offset = 5 # macro
SDMA_PKT_COPY_TILED_DW_5_mip_max_mask = 0x0000000F # macro
SDMA_PKT_COPY_TILED_DW_5_mip_max_shift = 16 # macro
def SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x): # macro
return (((x)&0x0000000F)<<16)
SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 # macro
SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 # macro
def SDMA_PKT_COPY_TILED_DW_6_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 # macro
SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 # macro
def SDMA_PKT_COPY_TILED_DW_6_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 # macro
SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x00001FFF # macro
SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 # macro
def SDMA_PKT_COPY_TILED_DW_7_Z(x): # macro
return (((x)&0x00001FFF)<<0)
SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 # macro
SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 # macro
def SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset = 7 # macro
SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift = 18 # macro
def SDMA_PKT_COPY_TILED_DW_7_LINEAR_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<18)
SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 # macro
SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 # macro
def SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset = 7 # macro
SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift = 26 # macro
def SDMA_PKT_COPY_TILED_DW_7_TILE_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<26)
SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro
SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro
SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 # macro
SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro
SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 # macro
def SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x): # macro
return (((x)&0x0007FFFF)<<0)
SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro
SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro
def SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 # macro
SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x3FFFFFFF # macro
SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 # macro
def SDMA_PKT_COPY_TILED_COUNT_COUNT(x): # macro
return (((x)&0x3FFFFFFF)<<0)
SDMA_PKT_COPY_TILED_BC_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_TILED_BC_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_TILED_BC_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_TILED_BC_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset = 0 # macro
SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift = 31 # macro
def SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro
SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro
SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_BC_DW_3_width_offset = 3 # macro
SDMA_PKT_COPY_TILED_BC_DW_3_width_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_BC_DW_3_width_shift = 0 # macro
def SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_BC_DW_4_height_offset = 4 # macro
SDMA_PKT_COPY_TILED_BC_DW_4_height_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_BC_DW_4_height_shift = 0 # macro
def SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset = 4 # macro
SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask = 0x000007FF # macro
SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift = 16 # macro
def SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x): # macro
return (((x)&0x000007FF)<<16)
SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset = 5 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift = 0 # macro
def SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro
return (((x)&0x00000007)<<0)
SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset = 5 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro
SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift = 3 # macro
def SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x): # macro
return (((x)&0x0000000F)<<3)
SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset = 5 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift = 8 # macro
def SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x): # macro
return (((x)&0x00000007)<<8)
SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro
def SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro
return (((x)&0x00000007)<<11)
SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset = 5 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift = 15 # macro
def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x): # macro
return (((x)&0x00000003)<<15)
SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset = 5 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift = 18 # macro
def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x): # macro
return (((x)&0x00000003)<<18)
SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset = 5 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift = 21 # macro
def SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x): # macro
return (((x)&0x00000003)<<21)
SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset = 5 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift = 24 # macro
def SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset = 5 # macro
SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro
SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift = 26 # macro
def SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x): # macro
return (((x)&0x0000001F)<<26)
SDMA_PKT_COPY_TILED_BC_DW_6_x_offset = 6 # macro
SDMA_PKT_COPY_TILED_BC_DW_6_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_BC_DW_6_x_shift = 0 # macro
def SDMA_PKT_COPY_TILED_BC_DW_6_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_BC_DW_6_y_offset = 6 # macro
SDMA_PKT_COPY_TILED_BC_DW_6_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_BC_DW_6_y_shift = 16 # macro
def SDMA_PKT_COPY_TILED_BC_DW_6_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_TILED_BC_DW_7_z_offset = 7 # macro
SDMA_PKT_COPY_TILED_BC_DW_7_z_mask = 0x000007FF # macro
SDMA_PKT_COPY_TILED_BC_DW_7_z_shift = 0 # macro
def SDMA_PKT_COPY_TILED_BC_DW_7_Z(x): # macro
return (((x)&0x000007FF)<<0)
SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset = 7 # macro
SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift = 16 # macro
def SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset = 7 # macro
SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift = 24 # macro
def SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro
SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro
SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset = 10 # macro
SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro
SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift = 0 # macro
def SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x): # macro
return (((x)&0x0007FFFF)<<0)
SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro
SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro
def SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_BC_COUNT_count_offset = 12 # macro
SDMA_PKT_COPY_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro
SDMA_PKT_COPY_TILED_BC_COUNT_count_shift = 2 # macro
def SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x): # macro
return (((x)&0x000FFFFF)<<2)
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x): # macro
return (((x)&0x00000001)<<16)
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset = 0 # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift = 19 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x): # macro
return (((x)&0x00000001)<<26)
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 # macro
SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x): # macro
return (((x)&0x00000001)<<27)
SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 # macro
SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 # macro
SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 # macro
SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 # macro
SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x00001FFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x): # macro
return (((x)&0x00001FFF)<<16)
SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x): # macro
return (((x)&0x00000007)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x): # macro
return (((x)&0x0000001F)<<3)
SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x): # macro
return (((x)&0x00000003)<<9)
SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset = 7 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask = 0x0000000F # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift = 16 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x): # macro
return (((x)&0x0000000F)<<16)
SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x00001FFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x): # macro
return (((x)&0x00001FFF)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x): # macro
return (((x)&0x00000003)<<8)
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset = 10 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift = 10 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<10)
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset = 10 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift = 18 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<18)
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset = 10 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift = 26 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<26)
SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 # macro
SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 # macro
SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 # macro
SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x): # macro
return (((x)&0x0007FFFF)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 # macro
SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 # macro
SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x3FFFFFFF # macro
SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 # macro
def SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x): # macro
return (((x)&0x3FFFFFFF)<<0)
SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_T2T_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 # macro
SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_COPY_T2T_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_COPY_T2T_HEADER_dcc_offset = 0 # macro
SDMA_PKT_COPY_T2T_HEADER_dcc_mask = 0x00000001 # macro
SDMA_PKT_COPY_T2T_HEADER_dcc_shift = 19 # macro
def SDMA_PKT_COPY_T2T_HEADER_DCC(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_T2T_HEADER_cpv_offset = 0 # macro
SDMA_PKT_COPY_T2T_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_COPY_T2T_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_COPY_T2T_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset = 0 # macro
SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask = 0x00000001 # macro
SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift = 31 # macro
def SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro
SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro
SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 # macro
SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 # macro
def SDMA_PKT_COPY_T2T_DW_3_SRC_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 # macro
SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 # macro
def SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 # macro
SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x00001FFF # macro
SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 # macro
def SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x): # macro
return (((x)&0x00001FFF)<<0)
SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 # macro
SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 # macro
def SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 # macro
SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 # macro
def SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 # macro
SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x00001FFF # macro
SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 # macro
def SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x): # macro
return (((x)&0x00001FFF)<<16)
SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 # macro
SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 # macro
SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 # macro
def SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x): # macro
return (((x)&0x00000007)<<0)
SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 # macro
SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F # macro
SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 # macro
def SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x): # macro
return (((x)&0x0000001F)<<3)
SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 # macro
SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 # macro
def SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x): # macro
return (((x)&0x00000003)<<9)
SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset = 6 # macro
SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask = 0x0000000F # macro
SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift = 16 # macro
def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x): # macro
return (((x)&0x0000000F)<<16)
SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset = 6 # macro
SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask = 0x0000000F # macro
SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift = 20 # macro
def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x): # macro
return (((x)&0x0000000F)<<20)
SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro
SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro
SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 # macro
SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 # macro
def SDMA_PKT_COPY_T2T_DW_9_DST_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 # macro
SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 # macro
def SDMA_PKT_COPY_T2T_DW_9_DST_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 # macro
SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x00001FFF # macro
SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 # macro
def SDMA_PKT_COPY_T2T_DW_10_DST_Z(x): # macro
return (((x)&0x00001FFF)<<0)
SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 # macro
SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 # macro
def SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 # macro
SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 # macro
def SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 # macro
SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x00001FFF # macro
SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 # macro
def SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x): # macro
return (((x)&0x00001FFF)<<16)
SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 # macro
SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 # macro
SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 # macro
def SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x): # macro
return (((x)&0x00000007)<<0)
SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 # macro
SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F # macro
SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 # macro
def SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x): # macro
return (((x)&0x0000001F)<<3)
SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 # macro
SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 # macro
def SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x): # macro
return (((x)&0x00000003)<<9)
SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset = 12 # macro
SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask = 0x0000000F # macro
SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift = 16 # macro
def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x): # macro
return (((x)&0x0000000F)<<16)
SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset = 12 # macro
SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask = 0x0000000F # macro
SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift = 20 # macro
def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x): # macro
return (((x)&0x0000000F)<<20)
SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 # macro
SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 # macro
def SDMA_PKT_COPY_T2T_DW_13_RECT_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 # macro
SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 # macro
def SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 # macro
SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x00001FFF # macro
SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 # macro
def SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x): # macro
return (((x)&0x00001FFF)<<0)
SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 # macro
SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 # macro
def SDMA_PKT_COPY_T2T_DW_14_DST_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset = 14 # macro
SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift = 18 # macro
def SDMA_PKT_COPY_T2T_DW_14_DST_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<18)
SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 # macro
SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 # macro
def SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset = 14 # macro
SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift = 26 # macro
def SDMA_PKT_COPY_T2T_DW_14_SRC_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<26)
SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset = 15 # macro
SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset = 16 # macro
SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset = 17 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask = 0x0000007F # macro
SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift = 0 # macro
def SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x): # macro
return (((x)&0x0000007F)<<0)
SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset = 17 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift = 7 # macro
def SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro
return (((x)&0x00000001)<<7)
SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset = 17 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift = 8 # macro
def SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro
return (((x)&0x00000001)<<8)
SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset = 17 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask = 0x00000007 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift = 9 # macro
def SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x): # macro
return (((x)&0x00000007)<<9)
SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset = 17 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift = 12 # macro
def SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x): # macro
return (((x)&0x00000003)<<12)
SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset = 17 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask = 0x00000001 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift = 14 # macro
def SDMA_PKT_COPY_T2T_META_CONFIG_META_LLC(x): # macro
return (((x)&0x00000001)<<14)
SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset = 17 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift = 24 # macro
def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset = 17 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift = 26 # macro
def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro
return (((x)&0x00000003)<<26)
SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset = 17 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift = 28 # macro
def SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset = 17 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask = 0x00000001 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift = 29 # macro
def SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x): # macro
return (((x)&0x00000001)<<29)
SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset = 17 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask = 0x00000001 # macro
SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift = 31 # macro
def SDMA_PKT_COPY_T2T_META_CONFIG_PIPE_ALIGNED(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_COPY_T2T_BC_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_T2T_BC_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_T2T_BC_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro
SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro
SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset = 3 # macro
SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset = 3 # macro
SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift = 16 # macro
def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset = 4 # macro
SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask = 0x000007FF # macro
SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x): # macro
return (((x)&0x000007FF)<<0)
SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset = 4 # macro
SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift = 16 # macro
def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset = 5 # macro
SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset = 5 # macro
SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask = 0x000007FF # macro
SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift = 16 # macro
def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x): # macro
return (((x)&0x000007FF)<<16)
SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset = 6 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask = 0x00000007 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x): # macro
return (((x)&0x00000007)<<0)
SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset = 6 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask = 0x0000000F # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift = 3 # macro
def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x): # macro
return (((x)&0x0000000F)<<3)
SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset = 6 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask = 0x00000007 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift = 8 # macro
def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x): # macro
return (((x)&0x00000007)<<8)
SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset = 6 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask = 0x00000007 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift = 11 # macro
def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x): # macro
return (((x)&0x00000007)<<11)
SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset = 6 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift = 15 # macro
def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x): # macro
return (((x)&0x00000003)<<15)
SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset = 6 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift = 18 # macro
def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x): # macro
return (((x)&0x00000003)<<18)
SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset = 6 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift = 21 # macro
def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x): # macro
return (((x)&0x00000003)<<21)
SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset = 6 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift = 24 # macro
def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset = 6 # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask = 0x0000001F # macro
SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift = 26 # macro
def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x): # macro
return (((x)&0x0000001F)<<26)
SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro
SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro
SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset = 9 # macro
SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset = 9 # macro
SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift = 16 # macro
def SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset = 10 # macro
SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask = 0x000007FF # macro
SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x): # macro
return (((x)&0x000007FF)<<0)
SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset = 10 # macro
SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift = 16 # macro
def SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset = 11 # macro
SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset = 11 # macro
SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask = 0x00000FFF # macro
SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift = 16 # macro
def SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x): # macro
return (((x)&0x00000FFF)<<16)
SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset = 12 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask = 0x00000007 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x): # macro
return (((x)&0x00000007)<<0)
SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset = 12 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask = 0x0000000F # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift = 3 # macro
def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x): # macro
return (((x)&0x0000000F)<<3)
SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset = 12 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask = 0x00000007 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift = 8 # macro
def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x): # macro
return (((x)&0x00000007)<<8)
SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset = 12 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask = 0x00000007 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift = 11 # macro
def SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x): # macro
return (((x)&0x00000007)<<11)
SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset = 12 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift = 15 # macro
def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x): # macro
return (((x)&0x00000003)<<15)
SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset = 12 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift = 18 # macro
def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x): # macro
return (((x)&0x00000003)<<18)
SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset = 12 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift = 21 # macro
def SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x): # macro
return (((x)&0x00000003)<<21)
SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset = 12 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift = 24 # macro
def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset = 12 # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask = 0x0000001F # macro
SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift = 26 # macro
def SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x): # macro
return (((x)&0x0000001F)<<26)
SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset = 13 # macro
SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset = 13 # macro
SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift = 16 # macro
def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset = 14 # macro
SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask = 0x000007FF # macro
SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift = 0 # macro
def SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x): # macro
return (((x)&0x000007FF)<<0)
SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset = 14 # macro
SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift = 16 # macro
def SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset = 14 # macro
SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift = 24 # macro
def SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 # macro
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset = 0 # macro
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift = 19 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset = 0 # macro
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 # macro
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro
SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro
SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x00001FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x): # macro
return (((x)&0x00001FFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x00001FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x): # macro
return (((x)&0x00001FFF)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x): # macro
return (((x)&0x00000007)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x): # macro
return (((x)&0x0000001F)<<3)
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x): # macro
return (((x)&0x00000003)<<9)
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask = 0x0000000F # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x): # macro
return (((x)&0x0000000F)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask = 0x0000000F # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift = 20 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x): # macro
return (((x)&0x0000000F)<<20)
SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro
SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro
SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x00001FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x): # macro
return (((x)&0x00001FFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x): # macro
return (((x)&0x0FFFFFFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x00001FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x): # macro
return (((x)&0x00001FFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset = 13 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift = 18 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<18)
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset = 13 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift = 26 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<26)
SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset = 14 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset = 15 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset = 16 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask = 0x0000007F # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x): # macro
return (((x)&0x0000007F)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset = 16 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift = 7 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro
return (((x)&0x00000001)<<7)
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset = 16 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift = 8 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro
return (((x)&0x00000001)<<8)
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset = 16 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask = 0x00000007 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift = 9 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x): # macro
return (((x)&0x00000007)<<9)
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset = 16 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift = 12 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x): # macro
return (((x)&0x00000003)<<12)
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset = 16 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift = 14 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_LLC(x): # macro
return (((x)&0x00000001)<<14)
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset = 16 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift = 24 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset = 16 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift = 26 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro
return (((x)&0x00000003)<<26)
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset = 16 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift = 28 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset = 16 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift = 29 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x): # macro
return (((x)&0x00000001)<<29)
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset = 16 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift = 31 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_PIPE_ALIGNED(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset = 0 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask = 0x00000001 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift = 31 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset = 3 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset = 3 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset = 4 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask = 0x000007FF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x): # macro
return (((x)&0x000007FF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset = 4 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset = 5 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset = 5 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask = 0x000007FF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x): # macro
return (((x)&0x000007FF)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask = 0x00000007 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x): # macro
return (((x)&0x00000007)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask = 0x0000000F # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift = 3 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x): # macro
return (((x)&0x0000000F)<<3)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask = 0x00000007 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift = 8 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x): # macro
return (((x)&0x00000007)<<8)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask = 0x00000007 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift = 11 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x): # macro
return (((x)&0x00000007)<<11)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift = 15 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x): # macro
return (((x)&0x00000003)<<15)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift = 18 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x): # macro
return (((x)&0x00000003)<<18)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift = 21 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x): # macro
return (((x)&0x00000003)<<21)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift = 24 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset = 6 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask = 0x0000001F # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift = 26 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x): # macro
return (((x)&0x0000001F)<<26)
SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset = 9 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset = 9 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset = 10 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask = 0x000007FF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x): # macro
return (((x)&0x000007FF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset = 10 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset = 11 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x): # macro
return (((x)&0x0FFFFFFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset = 12 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset = 12 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask = 0x00003FFF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset = 13 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask = 0x000007FF # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift = 0 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x): # macro
return (((x)&0x000007FF)<<0)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset = 13 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift = 16 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset = 13 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift = 24 # macro
def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 # macro
SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 # macro
def SDMA_PKT_COPY_STRUCT_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 # macro
SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset = 0 # macro
SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_COPY_STRUCT_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 # macro
SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 # macro
SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 # macro
def SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 # macro
SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 # macro
SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 # macro
SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 # macro
def SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 # macro
SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 # macro
def SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 # macro
SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF # macro
SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 # macro
def SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x): # macro
return (((x)&0x000007FF)<<0)
SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 # macro
SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 # macro
def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset = 5 # macro
SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift = 18 # macro
def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<18)
SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset = 5 # macro
SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask = 0x00000003 # macro
SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift = 24 # macro
def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset = 5 # macro
SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift = 26 # macro
def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<26)
SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 # macro
SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro
def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 # macro
SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro
def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 # macro
SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 # macro
def SDMA_PKT_WRITE_UNTILED_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 # macro
SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 # macro
SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 # macro
def SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x): # macro
return (((x)&0x00000001)<<16)
SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 # macro
SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset = 0 # macro
SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_WRITE_UNTILED_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro
SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro
SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 # macro
SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF # macro
SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 # macro
def SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x): # macro
return (((x)&0x000FFFFF)<<0)
SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 # macro
SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 # macro
SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 # macro
def SDMA_PKT_WRITE_UNTILED_DW_3_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset = 3 # macro
SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift = 26 # macro
def SDMA_PKT_WRITE_UNTILED_DW_3_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<26)
SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 # macro
SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 # macro
def SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 # macro
SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 # macro
SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 # macro
SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 # macro
def SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x): # macro
return (((x)&0x00000001)<<16)
SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 # macro
SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_WRITE_TILED_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_WRITE_TILED_HEADER_cpv_offset = 0 # macro
SDMA_PKT_WRITE_TILED_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_WRITE_TILED_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_WRITE_TILED_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro
SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro
SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 # macro
SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF # macro
SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 # macro
SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF # macro
SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 # macro
SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x00001FFF # macro
SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 # macro
def SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x): # macro
return (((x)&0x00001FFF)<<16)
SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 # macro
SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 # macro
SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x): # macro
return (((x)&0x00000007)<<0)
SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 # macro
SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro
SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 # macro
def SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x): # macro
return (((x)&0x0000001F)<<3)
SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 # macro
SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 # macro
SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 # macro
def SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x): # macro
return (((x)&0x00000003)<<9)
SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset = 5 # macro
SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask = 0x0000000F # macro
SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift = 16 # macro
def SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x): # macro
return (((x)&0x0000000F)<<16)
SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 # macro
SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF # macro
SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_DW_6_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 # macro
SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF # macro
SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 # macro
def SDMA_PKT_WRITE_TILED_DW_6_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 # macro
SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x00001FFF # macro
SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_DW_7_Z(x): # macro
return (((x)&0x00001FFF)<<0)
SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 # macro
SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 # macro
SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 # macro
def SDMA_PKT_WRITE_TILED_DW_7_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset = 7 # macro
SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift = 26 # macro
def SDMA_PKT_WRITE_TILED_DW_7_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<26)
SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 # macro
SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF # macro
SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_COUNT_COUNT(x): # macro
return (((x)&0x000FFFFF)<<0)
SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 # macro
SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_DATA0_DATA0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset = 0 # macro
SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro
SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro
SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset = 3 # macro
SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask = 0x00003FFF # macro
SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset = 4 # macro
SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask = 0x00003FFF # macro
SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset = 4 # macro
SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask = 0x000007FF # macro
SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift = 16 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x): # macro
return (((x)&0x000007FF)<<16)
SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset = 5 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro
return (((x)&0x00000007)<<0)
SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset = 5 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift = 3 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x): # macro
return (((x)&0x0000000F)<<3)
SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset = 5 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift = 8 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x): # macro
return (((x)&0x00000007)<<8)
SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro
return (((x)&0x00000007)<<11)
SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset = 5 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift = 15 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x): # macro
return (((x)&0x00000003)<<15)
SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset = 5 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift = 18 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x): # macro
return (((x)&0x00000003)<<18)
SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset = 5 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift = 21 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x): # macro
return (((x)&0x00000003)<<21)
SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset = 5 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift = 24 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset = 5 # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro
SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift = 26 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x): # macro
return (((x)&0x0000001F)<<26)
SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset = 6 # macro
SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask = 0x00003FFF # macro
SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_6_X(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset = 6 # macro
SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask = 0x00003FFF # macro
SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift = 16 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset = 7 # macro
SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask = 0x000007FF # macro
SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x): # macro
return (((x)&0x000007FF)<<0)
SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset = 7 # macro
SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask = 0x00000003 # macro
SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift = 24 # macro
def SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset = 8 # macro
SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro
SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift = 2 # macro
def SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x): # macro
return (((x)&0x000FFFFF)<<2)
SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset = 9 # macro
SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift = 0 # macro
def SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 # macro
SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset = 0 # macro
SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset = 0 # macro
SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_PTEPDE_COPY_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 # macro
SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 # macro
SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 # macro
def SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro
SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro
SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro
SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro
SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 # macro
SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 # macro
SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 # macro
SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF # macro
SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x): # macro
return (((x)&0x0007FFFF)<<0)
SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset = 7 # macro
SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift = 22 # macro
def SDMA_PKT_PTEPDE_COPY_COUNT_DST_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<22)
SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset = 7 # macro
SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift = 29 # macro
def SDMA_PKT_PTEPDE_COPY_COUNT_SRC_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<29)
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 # macro
def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x): # macro
return (((x)&0x00000003)<<28)
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 # macro
def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x): # macro
return (((x)&0x00000001)<<30)
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 # macro
def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 # macro
def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF # macro
SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 # macro
def SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x): # macro
return (((x)&0x0001FFFF)<<0)
SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 # macro
def SDMA_PKT_PTEPDE_RMW_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset = 0 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask = 0x00000007 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift = 16 # macro
def SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x): # macro
return (((x)&0x00000007)<<16)
SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 # macro
def SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 # macro
def SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x): # macro
return (((x)&0x00000001)<<20)
SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 # macro
def SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x): # macro
return (((x)&0x00000001)<<22)
SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 # macro
def SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x): # macro
return (((x)&0x00000001)<<23)
SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset = 0 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask = 0x00000003 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift = 24 # macro
def SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset = 0 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask = 0x00000001 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift = 26 # macro
def SDMA_PKT_PTEPDE_RMW_HEADER_LLC_POLICY(x): # macro
return (((x)&0x00000001)<<26)
SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset = 0 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_PTEPDE_RMW_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 # macro
SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 # macro
def SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 # macro
SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 # macro
def SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 # macro
SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 # macro
def SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 # macro
SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 # macro
def SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 # macro
SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 # macro
def SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 # macro
SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 # macro
def SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset = 7 # macro
SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask = 0xFFFFFFFF # macro
SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift = 0 # macro
def SDMA_PKT_PTEPDE_RMW_COUNT_NUM_OF_PTE(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_REGISTER_RMW_HEADER_op_offset = 0 # macro
SDMA_PKT_REGISTER_RMW_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_REGISTER_RMW_HEADER_op_shift = 0 # macro
def SDMA_PKT_REGISTER_RMW_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_REGISTER_RMW_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_REGISTER_RMW_ADDR_addr_offset = 1 # macro
SDMA_PKT_REGISTER_RMW_ADDR_addr_mask = 0x000FFFFF # macro
SDMA_PKT_REGISTER_RMW_ADDR_addr_shift = 0 # macro
def SDMA_PKT_REGISTER_RMW_ADDR_ADDR(x): # macro
return (((x)&0x000FFFFF)<<0)
SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset = 1 # macro
SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask = 0x00000FFF # macro
SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift = 20 # macro
def SDMA_PKT_REGISTER_RMW_ADDR_APERTURE_ID(x): # macro
return (((x)&0x00000FFF)<<20)
SDMA_PKT_REGISTER_RMW_MASK_mask_offset = 2 # macro
SDMA_PKT_REGISTER_RMW_MASK_mask_mask = 0xFFFFFFFF # macro
SDMA_PKT_REGISTER_RMW_MASK_mask_shift = 0 # macro
def SDMA_PKT_REGISTER_RMW_MASK_MASK(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_REGISTER_RMW_VALUE_value_offset = 3 # macro
SDMA_PKT_REGISTER_RMW_VALUE_value_mask = 0xFFFFFFFF # macro
SDMA_PKT_REGISTER_RMW_VALUE_value_shift = 0 # macro
def SDMA_PKT_REGISTER_RMW_VALUE_VALUE(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_REGISTER_RMW_MISC_stride_offset = 4 # macro
SDMA_PKT_REGISTER_RMW_MISC_stride_mask = 0x000FFFFF # macro
SDMA_PKT_REGISTER_RMW_MISC_stride_shift = 0 # macro
def SDMA_PKT_REGISTER_RMW_MISC_STRIDE(x): # macro
return (((x)&0x000FFFFF)<<0)
SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset = 4 # macro
SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask = 0x00000FFF # macro
SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift = 20 # macro
def SDMA_PKT_REGISTER_RMW_MISC_NUM_OF_REG(x): # macro
return (((x)&0x00000FFF)<<20)
SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 # macro
SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 # macro
def SDMA_PKT_WRITE_INCR_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset = 0 # macro
SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift = 24 # macro
def SDMA_PKT_WRITE_INCR_HEADER_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<24)
SDMA_PKT_WRITE_INCR_HEADER_cpv_offset = 0 # macro
SDMA_PKT_WRITE_INCR_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_WRITE_INCR_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_WRITE_INCR_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro
SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro
SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 # macro
SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 # macro
def SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 # macro
SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 # macro
def SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 # macro
SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 # macro
def SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 # macro
SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 # macro
def SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 # macro
SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 # macro
def SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 # macro
SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF # macro
SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 # macro
def SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 # macro
SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF # macro
SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 # macro
def SDMA_PKT_WRITE_INCR_COUNT_COUNT(x): # macro
return (((x)&0x0007FFFF)<<0)
SDMA_PKT_INDIRECT_HEADER_op_offset = 0 # macro
SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_INDIRECT_HEADER_op_shift = 0 # macro
def SDMA_PKT_INDIRECT_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_INDIRECT_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 # macro
SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F # macro
SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 # macro
def SDMA_PKT_INDIRECT_HEADER_VMID(x): # macro
return (((x)&0x0000000F)<<16)
SDMA_PKT_INDIRECT_HEADER_priv_offset = 0 # macro
SDMA_PKT_INDIRECT_HEADER_priv_mask = 0x00000001 # macro
SDMA_PKT_INDIRECT_HEADER_priv_shift = 31 # macro
def SDMA_PKT_INDIRECT_HEADER_PRIV(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 # macro
SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 # macro
def SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 # macro
SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 # macro
def SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 # macro
SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF # macro
SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 # macro
def SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x): # macro
return (((x)&0x000FFFFF)<<0)
SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 # macro
SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 # macro
def SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 # macro
SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 # macro
def SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 # macro
SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 # macro
def SDMA_PKT_SEMAPHORE_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 # macro
SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 # macro
SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 # macro
def SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x): # macro
return (((x)&0x00000001)<<29)
SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 # macro
SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 # macro
SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 # macro
def SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x): # macro
return (((x)&0x00000001)<<30)
SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 # macro
SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 # macro
SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 # macro
def SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 # macro
SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 # macro
def SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 # macro
SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 # macro
def SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_MEM_INCR_HEADER_op_offset = 0 # macro
SDMA_PKT_MEM_INCR_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_MEM_INCR_HEADER_op_shift = 0 # macro
def SDMA_PKT_MEM_INCR_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_MEM_INCR_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_MEM_INCR_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_MEM_INCR_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_MEM_INCR_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset = 0 # macro
SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask = 0x00000003 # macro
SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift = 24 # macro
def SDMA_PKT_MEM_INCR_HEADER_L2_POLICY(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset = 0 # macro
SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask = 0x00000001 # macro
SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift = 26 # macro
def SDMA_PKT_MEM_INCR_HEADER_LLC_POLICY(x): # macro
return (((x)&0x00000001)<<26)
SDMA_PKT_MEM_INCR_HEADER_cpv_offset = 0 # macro
SDMA_PKT_MEM_INCR_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_MEM_INCR_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_MEM_INCR_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset = 1 # macro
SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift = 0 # macro
def SDMA_PKT_MEM_INCR_ADDR_LO_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset = 2 # macro
SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift = 0 # macro
def SDMA_PKT_MEM_INCR_ADDR_HI_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_VM_INVALIDATION_HEADER_op_offset = 0 # macro
SDMA_PKT_VM_INVALIDATION_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_VM_INVALIDATION_HEADER_op_shift = 0 # macro
def SDMA_PKT_VM_INVALIDATION_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset = 0 # macro
SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask = 0x0000001F # macro
SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift = 16 # macro
def SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x): # macro
return (((x)&0x0000001F)<<16)
SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset = 0 # macro
SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask = 0x0000001F # macro
SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift = 24 # macro
def SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x): # macro
return (((x)&0x0000001F)<<24)
SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset = 1 # macro
SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask = 0xFFFFFFFF # macro
SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift = 0 # macro
def SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset = 2 # macro
SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask = 0xFFFFFFFF # macro
SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift = 0 # macro
def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset = 3 # macro
SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask = 0x0000FFFF # macro
SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift = 0 # macro
def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x): # macro
return (((x)&0x0000FFFF)<<0)
SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset = 3 # macro
SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask = 0x0000001F # macro
SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift = 16 # macro
def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x): # macro
return (((x)&0x0000001F)<<16)
SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset = 3 # macro
SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask = 0x000001FF # macro
SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift = 23 # macro
def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x): # macro
return (((x)&0x000001FF)<<23)
SDMA_PKT_FENCE_HEADER_op_offset = 0 # macro
SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_FENCE_HEADER_op_shift = 0 # macro
def SDMA_PKT_FENCE_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_FENCE_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_FENCE_HEADER_mtype_offset = 0 # macro
SDMA_PKT_FENCE_HEADER_mtype_mask = 0x00000007 # macro
SDMA_PKT_FENCE_HEADER_mtype_shift = 16 # macro
def SDMA_PKT_FENCE_HEADER_MTYPE(x): # macro
return (((x)&0x00000007)<<16)
SDMA_PKT_FENCE_HEADER_gcc_offset = 0 # macro
SDMA_PKT_FENCE_HEADER_gcc_mask = 0x00000001 # macro
SDMA_PKT_FENCE_HEADER_gcc_shift = 19 # macro
def SDMA_PKT_FENCE_HEADER_GCC(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_FENCE_HEADER_sys_offset = 0 # macro
SDMA_PKT_FENCE_HEADER_sys_mask = 0x00000001 # macro
SDMA_PKT_FENCE_HEADER_sys_shift = 20 # macro
def SDMA_PKT_FENCE_HEADER_SYS(x): # macro
return (((x)&0x00000001)<<20)
SDMA_PKT_FENCE_HEADER_snp_offset = 0 # macro
SDMA_PKT_FENCE_HEADER_snp_mask = 0x00000001 # macro
SDMA_PKT_FENCE_HEADER_snp_shift = 22 # macro
def SDMA_PKT_FENCE_HEADER_SNP(x): # macro
return (((x)&0x00000001)<<22)
SDMA_PKT_FENCE_HEADER_gpa_offset = 0 # macro
SDMA_PKT_FENCE_HEADER_gpa_mask = 0x00000001 # macro
SDMA_PKT_FENCE_HEADER_gpa_shift = 23 # macro
def SDMA_PKT_FENCE_HEADER_GPA(x): # macro
return (((x)&0x00000001)<<23)
SDMA_PKT_FENCE_HEADER_l2_policy_offset = 0 # macro
SDMA_PKT_FENCE_HEADER_l2_policy_mask = 0x00000003 # macro
SDMA_PKT_FENCE_HEADER_l2_policy_shift = 24 # macro
def SDMA_PKT_FENCE_HEADER_L2_POLICY(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_FENCE_HEADER_llc_policy_offset = 0 # macro
SDMA_PKT_FENCE_HEADER_llc_policy_mask = 0x00000001 # macro
SDMA_PKT_FENCE_HEADER_llc_policy_shift = 26 # macro
def SDMA_PKT_FENCE_HEADER_LLC_POLICY(x): # macro
return (((x)&0x00000001)<<26)
SDMA_PKT_FENCE_HEADER_cpv_offset = 0 # macro
SDMA_PKT_FENCE_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_FENCE_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_FENCE_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 # macro
SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 # macro
def SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 # macro
SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 # macro
def SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_FENCE_DATA_data_offset = 3 # macro
SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF # macro
SDMA_PKT_FENCE_DATA_data_shift = 0 # macro
def SDMA_PKT_FENCE_DATA_DATA(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 # macro
SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 # macro
def SDMA_PKT_SRBM_WRITE_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 # macro
SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F # macro
SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 # macro
def SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x): # macro
return (((x)&0x0000000F)<<28)
SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 # macro
SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF # macro
SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 # macro
def SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x): # macro
return (((x)&0x0003FFFF)<<0)
SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset = 1 # macro
SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask = 0x00000FFF # macro
SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift = 20 # macro
def SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x): # macro
return (((x)&0x00000FFF)<<20)
SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 # macro
SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF # macro
SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 # macro
def SDMA_PKT_SRBM_WRITE_DATA_DATA(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 # macro
SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 # macro
def SDMA_PKT_PRE_EXE_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 # macro
SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF # macro
SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 # macro
def SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x): # macro
return (((x)&0x000000FF)<<16)
SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 # macro
SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro
SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 # macro
def SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_COND_EXE_HEADER_op_offset = 0 # macro
SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_COND_EXE_HEADER_op_shift = 0 # macro
def SDMA_PKT_COND_EXE_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_COND_EXE_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_COND_EXE_HEADER_cache_policy_offset = 0 # macro
SDMA_PKT_COND_EXE_HEADER_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_COND_EXE_HEADER_cache_policy_shift = 24 # macro
def SDMA_PKT_COND_EXE_HEADER_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<24)
SDMA_PKT_COND_EXE_HEADER_cpv_offset = 0 # macro
SDMA_PKT_COND_EXE_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_COND_EXE_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_COND_EXE_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 # macro
SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 # macro
def SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 # macro
SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 # macro
def SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 # macro
SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF # macro
SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 # macro
def SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 # macro
SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro
SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 # macro
def SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro
return (((x)&0x00003FFF)<<0)
SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 # macro
SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 # macro
def SDMA_PKT_CONSTANT_FILL_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 # macro
SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 # macro
SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 # macro
def SDMA_PKT_CONSTANT_FILL_HEADER_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset = 0 # macro
SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift = 24 # macro
def SDMA_PKT_CONSTANT_FILL_HEADER_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<24)
SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset = 0 # macro
SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_CONSTANT_FILL_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 # macro
SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 # macro
SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 # macro
def SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x): # macro
return (((x)&0x00000003)<<30)
SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro
SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro
SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 # macro
SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 # macro
def SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 # macro
SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x3FFFFFFF # macro
SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 # macro
def SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x): # macro
return (((x)&0x3FFFFFFF)<<0)
SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 # macro
SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 # macro
def SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset = 0 # macro
SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift = 24 # macro
def SDMA_PKT_DATA_FILL_MULTI_HEADER_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<24)
SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset = 0 # macro
SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_DATA_FILL_MULTI_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 # macro
SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 # macro
SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 # macro
def SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 # macro
SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF # macro
SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 # macro
def SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 # macro
SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF # macro
SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 # macro
def SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro
SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro
SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 # macro
SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF # macro
SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 # macro
def SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x): # macro
return (((x)&0x03FFFFFF)<<0)
SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 # macro
SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 # macro
def SDMA_PKT_POLL_REGMEM_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset = 0 # macro
SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift = 20 # macro
def SDMA_PKT_POLL_REGMEM_HEADER_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<20)
SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset = 0 # macro
SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift = 24 # macro
def SDMA_PKT_POLL_REGMEM_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<24)
SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 # macro
SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 # macro
SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 # macro
def SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x): # macro
return (((x)&0x00000001)<<26)
SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 # macro
SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 # macro
SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 # macro
def SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x): # macro
return (((x)&0x00000007)<<28)
SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 # macro
SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 # macro
SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 # macro
def SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 # macro
SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 # macro
def SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 # macro
SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 # macro
def SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 # macro
SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 # macro
def SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 # macro
SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 # macro
def SDMA_PKT_POLL_REGMEM_MASK_MASK(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 # macro
SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF # macro
SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 # macro
def SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x): # macro
return (((x)&0x0000FFFF)<<0)
SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 # macro
SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF # macro
SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 # macro
def SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x): # macro
return (((x)&0x00000FFF)<<16)
SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 # macro
SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 # macro
def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset = 0 # macro
SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift = 24 # macro
def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<24)
SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset = 0 # macro
SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 # macro
SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF # macro
SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 # macro
def SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x): # macro
return (((x)&0x3FFFFFFF)<<2)
SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 # macro
SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro
def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 # macro
SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro
def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 # macro
def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 # macro
def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x): # macro
return (((x)&0x00000003)<<16)
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset = 0 # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift = 24 # macro
def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<24)
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset = 0 # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro
def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro
def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 # macro
def SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x): # macro
return (((x)&0x0FFFFFFF)<<4)
SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 # macro
def SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 # macro
SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 # macro
def SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset = 0 # macro
SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift = 24 # macro
def SDMA_PKT_POLL_MEM_VERIFY_HEADER_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<24)
SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset = 0 # macro
SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_POLL_MEM_VERIFY_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 # macro
SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 # macro
SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 # macro
def SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x): # macro
return (((x)&0x00000001)<<31)
SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 # macro
SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 # macro
def SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 # macro
def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 # macro
def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset = 4 # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift = 0 # macro
def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP0_END_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset = 5 # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift = 0 # macro
def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP0_END_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 # macro
def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 # macro
def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro
def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro
def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 # macro
SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 # macro
def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 # macro
SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 # macro
def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 # macro
SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF # macro
SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 # macro
def SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_ATOMIC_HEADER_op_offset = 0 # macro
SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_ATOMIC_HEADER_op_shift = 0 # macro
def SDMA_PKT_ATOMIC_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 # macro
SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 # macro
SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 # macro
def SDMA_PKT_ATOMIC_HEADER_LOOP(x): # macro
return (((x)&0x00000001)<<16)
SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 # macro
SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 # macro
SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 # macro
def SDMA_PKT_ATOMIC_HEADER_TMZ(x): # macro
return (((x)&0x00000001)<<18)
SDMA_PKT_ATOMIC_HEADER_cache_policy_offset = 0 # macro
SDMA_PKT_ATOMIC_HEADER_cache_policy_mask = 0x00000007 # macro
SDMA_PKT_ATOMIC_HEADER_cache_policy_shift = 20 # macro
def SDMA_PKT_ATOMIC_HEADER_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<20)
SDMA_PKT_ATOMIC_HEADER_cpv_offset = 0 # macro
SDMA_PKT_ATOMIC_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_ATOMIC_HEADER_cpv_shift = 24 # macro
def SDMA_PKT_ATOMIC_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<24)
SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 # macro
SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F # macro
SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 # macro
def SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x): # macro
return (((x)&0x0000007F)<<25)
SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 # macro
SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 # macro
def SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 # macro
SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 # macro
def SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 # macro
SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 # macro
def SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 # macro
SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 # macro
def SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 # macro
SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 # macro
def SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 # macro
SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 # macro
def SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 # macro
SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF # macro
SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 # macro
def SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x): # macro
return (((x)&0x00001FFF)<<0)
SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 # macro
SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 # macro
def SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 # macro
SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF # macro
SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 # macro
def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 # macro
SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 # macro
def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 # macro
SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 # macro
def SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset = 0 # macro
SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask = 0x00000003 # macro
SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift = 24 # macro
def SDMA_PKT_TIMESTAMP_GET_HEADER_L2_POLICY(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset = 0 # macro
SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask = 0x00000001 # macro
SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift = 26 # macro
def SDMA_PKT_TIMESTAMP_GET_HEADER_LLC_POLICY(x): # macro
return (((x)&0x00000001)<<26)
SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset = 0 # macro
SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_TIMESTAMP_GET_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro
SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro
SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro
def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro
return (((x)&0x1FFFFFFF)<<3)
SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro
SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro
def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 # macro
def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset = 0 # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask = 0x00000003 # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift = 24 # macro
def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_L2_POLICY(x): # macro
return (((x)&0x00000003)<<24)
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset = 0 # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask = 0x00000001 # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift = 26 # macro
def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_LLC_POLICY(x): # macro
return (((x)&0x00000001)<<26)
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset = 0 # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask = 0x00000001 # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift = 28 # macro
def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro
def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro
return (((x)&0x1FFFFFFF)<<3)
SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro
def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_PKT_TRAP_HEADER_op_offset = 0 # macro
SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_TRAP_HEADER_op_shift = 0 # macro
def SDMA_PKT_TRAP_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_TRAP_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 # macro
SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro
SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 # macro
def SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro
return (((x)&0x0FFFFFFF)<<0)
SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 # macro
SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 # macro
def SDMA_PKT_DUMMY_TRAP_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 # macro
SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro
SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 # macro
def SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro
return (((x)&0x0FFFFFFF)<<0)
SDMA_PKT_GPUVM_INV_HEADER_op_offset = 0 # macro
SDMA_PKT_GPUVM_INV_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_GPUVM_INV_HEADER_op_shift = 0 # macro
def SDMA_PKT_GPUVM_INV_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset = 1 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask = 0x0000FFFF # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift = 0 # macro
def SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x): # macro
return (((x)&0x0000FFFF)<<0)
SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset = 1 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask = 0x00000007 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift = 16 # macro
def SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x): # macro
return (((x)&0x00000007)<<16)
SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset = 1 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask = 0x00000001 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift = 19 # macro
def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x): # macro
return (((x)&0x00000001)<<19)
SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset = 1 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask = 0x00000001 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift = 20 # macro
def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x): # macro
return (((x)&0x00000001)<<20)
SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset = 1 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask = 0x00000001 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift = 21 # macro
def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x): # macro
return (((x)&0x00000001)<<21)
SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset = 1 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask = 0x00000001 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift = 22 # macro
def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x): # macro
return (((x)&0x00000001)<<22)
SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset = 1 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask = 0x00000001 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift = 23 # macro
def SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x): # macro
return (((x)&0x00000001)<<23)
SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset = 1 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask = 0x00000001 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift = 24 # macro
def SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x): # macro
return (((x)&0x00000001)<<24)
SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset = 1 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask = 0x00000001 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift = 25 # macro
def SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x): # macro
return (((x)&0x00000001)<<25)
SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset = 1 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask = 0x00000001 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift = 26 # macro
def SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x): # macro
return (((x)&0x00000001)<<26)
SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset = 2 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask = 0x00000001 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift = 0 # macro
def SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x): # macro
return (((x)&0x00000001)<<0)
SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset = 2 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask = 0x7FFFFFFF # macro
SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift = 1 # macro
def SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x): # macro
return (((x)&0x7FFFFFFF)<<1)
SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset = 3 # macro
SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask = 0x0000003F # macro
SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift = 0 # macro
def SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x): # macro
return (((x)&0x0000003F)<<0)
SDMA_PKT_GCR_REQ_HEADER_op_offset = 0 # macro
SDMA_PKT_GCR_REQ_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_GCR_REQ_HEADER_op_shift = 0 # macro
def SDMA_PKT_GCR_REQ_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_GCR_REQ_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_GCR_REQ_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_GCR_REQ_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset = 1 # macro
SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask = 0x01FFFFFF # macro
SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift = 7 # macro
def SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x): # macro
return (((x)&0x01FFFFFF)<<7)
SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset = 2 # macro
SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask = 0x0000FFFF # macro
SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift = 0 # macro
def SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x): # macro
return (((x)&0x0000FFFF)<<0)
SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset = 2 # macro
SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask = 0x0000FFFF # macro
SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift = 16 # macro
def SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x): # macro
return (((x)&0x0000FFFF)<<16)
SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset = 3 # macro
SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask = 0x00000007 # macro
SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift = 0 # macro
def SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x): # macro
return (((x)&0x00000007)<<0)
SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset = 3 # macro
SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask = 0x01FFFFFF # macro
SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift = 7 # macro
def SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x): # macro
return (((x)&0x01FFFFFF)<<7)
SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset = 4 # macro
SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask = 0x0000FFFF # macro
SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift = 0 # macro
def SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x): # macro
return (((x)&0x0000FFFF)<<0)
SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset = 4 # macro
SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask = 0x0000000F # macro
SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift = 24 # macro
def SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x): # macro
return (((x)&0x0000000F)<<24)
SDMA_PKT_NOP_HEADER_op_offset = 0 # macro
SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF # macro
SDMA_PKT_NOP_HEADER_op_shift = 0 # macro
def SDMA_PKT_NOP_HEADER_OP(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_PKT_NOP_HEADER_sub_op_offset = 0 # macro
SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF # macro
SDMA_PKT_NOP_HEADER_sub_op_shift = 8 # macro
def SDMA_PKT_NOP_HEADER_SUB_OP(x): # macro
return (((x)&0x000000FF)<<8)
SDMA_PKT_NOP_HEADER_count_offset = 0 # macro
SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF # macro
SDMA_PKT_NOP_HEADER_count_shift = 16 # macro
def SDMA_PKT_NOP_HEADER_COUNT(x): # macro
return (((x)&0x00003FFF)<<16)
SDMA_PKT_NOP_DATA0_data0_offset = 1 # macro
SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF # macro
SDMA_PKT_NOP_DATA0_data0_shift = 0 # macro
def SDMA_PKT_NOP_DATA0_DATA0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 # macro
SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF # macro
SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 # macro
def SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 # macro
SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 # macro
SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 # macro
def SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x): # macro
return (((x)&0x00000001)<<8)
SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 # macro
SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 # macro
SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 # macro
def SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro
return (((x)&0x00000003)<<9)
SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 # macro
SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 # macro
SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 # macro
def SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x): # macro
return (((x)&0x00000003)<<11)
SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 # macro
SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 # macro
SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 # macro
def SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x): # macro
return (((x)&0x00000007)<<13)
SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 # macro
SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F # macro
SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 # macro
def SDMA_AQL_PKT_HEADER_HEADER_OP(x): # macro
return (((x)&0x0000000F)<<16)
SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 # macro
SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 # macro
SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 # macro
def SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x): # macro
return (((x)&0x00000007)<<20)
SDMA_AQL_PKT_HEADER_HEADER_cpv_offset = 0 # macro
SDMA_AQL_PKT_HEADER_HEADER_cpv_mask = 0x00000001 # macro
SDMA_AQL_PKT_HEADER_HEADER_cpv_shift = 28 # macro
def SDMA_AQL_PKT_HEADER_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 # macro
def SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x): # macro
return (((x)&0x00000001)<<8)
SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 # macro
def SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro
return (((x)&0x00000003)<<9)
SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 # macro
def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x): # macro
return (((x)&0x00000003)<<11)
SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 # macro
def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x): # macro
return (((x)&0x00000007)<<13)
SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 # macro
def SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x): # macro
return (((x)&0x0000000F)<<16)
SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 # macro
def SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x): # macro
return (((x)&0x00000007)<<20)
SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset = 0 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask = 0x00000001 # macro
SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift = 28 # macro
def SDMA_AQL_PKT_COPY_LINEAR_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 # macro
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 # macro
SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 # macro
SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 # macro
SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro
return (((x)&0x003FFFFF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 # macro
SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro
SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro
def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro
return (((x)&0x00000003)<<16)
SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset = 5 # macro
SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask = 0x00000007 # macro
SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift = 18 # macro
def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<18)
SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 # macro
SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro
SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro
def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro
return (((x)&0x00000003)<<24)
SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset = 5 # macro
SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro
SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro
def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro
return (((x)&0x00000007)<<26)
SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 # macro
SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 # macro
SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 # macro
SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 # macro
SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 # macro
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 # macro
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 # macro
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 # macro
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro
SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro
SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro
def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x): # macro
return (((x)&0x000000FF)<<0)
SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 # macro
def SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x): # macro
return (((x)&0x00000001)<<8)
SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 # macro
def SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro
return (((x)&0x00000003)<<9)
SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 # macro
def SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x): # macro
return (((x)&0x00000003)<<11)
SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 # macro
def SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x): # macro
return (((x)&0x00000007)<<13)
SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 # macro
def SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x): # macro
return (((x)&0x0000000F)<<16)
SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 # macro
def SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x): # macro
return (((x)&0x00000007)<<20)
SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset = 0 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask = 0x00000001 # macro
SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift = 28 # macro
def SDMA_AQL_PKT_BARRIER_OR_HEADER_CPV(x): # macro
return (((x)&0x00000001)<<28)
SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 # macro
SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset = 12 # macro
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask = 0x00000007 # macro
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY0(x): # macro
return (((x)&0x00000007)<<0)
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset = 12 # macro
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask = 0x00000007 # macro
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift = 5 # macro
def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY1(x): # macro
return (((x)&0x00000007)<<5)
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset = 12 # macro
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask = 0x00000007 # macro
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift = 10 # macro
def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY2(x): # macro
return (((x)&0x00000007)<<10)
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset = 12 # macro
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask = 0x00000007 # macro
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift = 15 # macro
def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY3(x): # macro
return (((x)&0x00000007)<<15)
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset = 12 # macro
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask = 0x00000007 # macro
SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift = 20 # macro
def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY4(x): # macro
return (((x)&0x00000007)<<20)
SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 # macro
SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro
SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro
return (((x)&0xFFFFFFFF)<<0)
SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro
SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro
SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro
def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro
return (((x)&0xFFFFFFFF)<<0)
_gc_11_0_0_OFFSET_HEADER = True # macro
regSDMA0_DEC_START = 0x0000 # macro
regSDMA0_DEC_START_BASE_IDX = 0 # macro
regSDMA0_F32_MISC_CNTL = 0x000b # macro
regSDMA0_F32_MISC_CNTL_BASE_IDX = 0 # macro
regSDMA0_GLOBAL_TIMESTAMP_LO = 0x000f # macro
regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro
regSDMA0_GLOBAL_TIMESTAMP_HI = 0x0010 # macro
regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro
regSDMA0_POWER_CNTL = 0x001a # macro
regSDMA0_POWER_CNTL_BASE_IDX = 0 # macro
regSDMA0_CNTL = 0x001c # macro
regSDMA0_CNTL_BASE_IDX = 0 # macro
regSDMA0_CHICKEN_BITS = 0x001d # macro
regSDMA0_CHICKEN_BITS_BASE_IDX = 0 # macro
regSDMA0_GB_ADDR_CONFIG = 0x001e # macro
regSDMA0_GB_ADDR_CONFIG_BASE_IDX = 0 # macro
regSDMA0_GB_ADDR_CONFIG_READ = 0x001f # macro
regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro
regSDMA0_RB_RPTR_FETCH = 0x0020 # macro
regSDMA0_RB_RPTR_FETCH_BASE_IDX = 0 # macro
regSDMA0_RB_RPTR_FETCH_HI = 0x0021 # macro
regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro
regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL = 0x0022 # macro
regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro
regSDMA0_IB_OFFSET_FETCH = 0x0023 # macro
regSDMA0_IB_OFFSET_FETCH_BASE_IDX = 0 # macro
regSDMA0_PROGRAM = 0x0024 # macro
regSDMA0_PROGRAM_BASE_IDX = 0 # macro
regSDMA0_STATUS_REG = 0x0025 # macro
regSDMA0_STATUS_REG_BASE_IDX = 0 # macro
regSDMA0_STATUS1_REG = 0x0026 # macro
regSDMA0_STATUS1_REG_BASE_IDX = 0 # macro
regSDMA0_CNTL1 = 0x0027 # macro
regSDMA0_CNTL1_BASE_IDX = 0 # macro
regSDMA0_HBM_PAGE_CONFIG = 0x0028 # macro
regSDMA0_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro
regSDMA0_UCODE_CHECKSUM = 0x0029 # macro
regSDMA0_UCODE_CHECKSUM_BASE_IDX = 0 # macro
regSDMA0_FREEZE = 0x002b # macro
regSDMA0_FREEZE_BASE_IDX = 0 # macro
regSDMA0_PROCESS_QUANTUM0 = 0x002c # macro
regSDMA0_PROCESS_QUANTUM0_BASE_IDX = 0 # macro
regSDMA0_PROCESS_QUANTUM1 = 0x002d # macro
regSDMA0_PROCESS_QUANTUM1_BASE_IDX = 0 # macro
regSDMA0_WATCHDOG_CNTL = 0x002e # macro
regSDMA0_WATCHDOG_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE_STATUS0 = 0x002f # macro
regSDMA0_QUEUE_STATUS0_BASE_IDX = 0 # macro
regSDMA0_EDC_CONFIG = 0x0032 # macro
regSDMA0_EDC_CONFIG_BASE_IDX = 0 # macro
regSDMA0_BA_THRESHOLD = 0x0033 # macro
regSDMA0_BA_THRESHOLD_BASE_IDX = 0 # macro
regSDMA0_ID = 0x0034 # macro
regSDMA0_ID_BASE_IDX = 0 # macro
regSDMA0_VERSION = 0x0035 # macro
regSDMA0_VERSION_BASE_IDX = 0 # macro
regSDMA0_EDC_COUNTER = 0x0036 # macro
regSDMA0_EDC_COUNTER_BASE_IDX = 0 # macro
regSDMA0_EDC_COUNTER_CLEAR = 0x0037 # macro
regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro
regSDMA0_STATUS2_REG = 0x0038 # macro
regSDMA0_STATUS2_REG_BASE_IDX = 0 # macro
regSDMA0_ATOMIC_CNTL = 0x0039 # macro
regSDMA0_ATOMIC_CNTL_BASE_IDX = 0 # macro
regSDMA0_ATOMIC_PREOP_LO = 0x003a # macro
regSDMA0_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro
regSDMA0_ATOMIC_PREOP_HI = 0x003b # macro
regSDMA0_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro
regSDMA0_UTCL1_CNTL = 0x003c # macro
regSDMA0_UTCL1_CNTL_BASE_IDX = 0 # macro
regSDMA0_UTCL1_WATERMK = 0x003d # macro
regSDMA0_UTCL1_WATERMK_BASE_IDX = 0 # macro
regSDMA0_UTCL1_TIMEOUT = 0x003e # macro
regSDMA0_UTCL1_TIMEOUT_BASE_IDX = 0 # macro
regSDMA0_UTCL1_PAGE = 0x003f # macro
regSDMA0_UTCL1_PAGE_BASE_IDX = 0 # macro
regSDMA0_UTCL1_RD_STATUS = 0x0040 # macro
regSDMA0_UTCL1_RD_STATUS_BASE_IDX = 0 # macro
regSDMA0_UTCL1_WR_STATUS = 0x0041 # macro
regSDMA0_UTCL1_WR_STATUS_BASE_IDX = 0 # macro
regSDMA0_UTCL1_INV0 = 0x0042 # macro
regSDMA0_UTCL1_INV0_BASE_IDX = 0 # macro
regSDMA0_UTCL1_INV1 = 0x0043 # macro
regSDMA0_UTCL1_INV1_BASE_IDX = 0 # macro
regSDMA0_UTCL1_INV2 = 0x0044 # macro
regSDMA0_UTCL1_INV2_BASE_IDX = 0 # macro
regSDMA0_UTCL1_RD_XNACK0 = 0x0045 # macro
regSDMA0_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro
regSDMA0_UTCL1_RD_XNACK1 = 0x0046 # macro
regSDMA0_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro
regSDMA0_UTCL1_WR_XNACK0 = 0x0047 # macro
regSDMA0_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro
regSDMA0_UTCL1_WR_XNACK1 = 0x0048 # macro
regSDMA0_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro
regSDMA0_RELAX_ORDERING_LUT = 0x004a # macro
regSDMA0_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro
regSDMA0_CHICKEN_BITS_2 = 0x004b # macro
regSDMA0_CHICKEN_BITS_2_BASE_IDX = 0 # macro
regSDMA0_STATUS3_REG = 0x004c # macro
regSDMA0_STATUS3_REG_BASE_IDX = 0 # macro
regSDMA0_PHYSICAL_ADDR_LO = 0x004d # macro
regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_PHYSICAL_ADDR_HI = 0x004e # macro
regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_GLOBAL_QUANTUM = 0x004f # macro
regSDMA0_GLOBAL_QUANTUM_BASE_IDX = 0 # macro
regSDMA0_ERROR_LOG = 0x0050 # macro
regSDMA0_ERROR_LOG_BASE_IDX = 0 # macro
regSDMA0_PUB_DUMMY_REG0 = 0x0051 # macro
regSDMA0_PUB_DUMMY_REG0_BASE_IDX = 0 # macro
regSDMA0_PUB_DUMMY_REG1 = 0x0052 # macro
regSDMA0_PUB_DUMMY_REG1_BASE_IDX = 0 # macro
regSDMA0_PUB_DUMMY_REG2 = 0x0053 # macro
regSDMA0_PUB_DUMMY_REG2_BASE_IDX = 0 # macro
regSDMA0_PUB_DUMMY_REG3 = 0x0054 # macro
regSDMA0_PUB_DUMMY_REG3_BASE_IDX = 0 # macro
regSDMA0_F32_COUNTER = 0x0055 # macro
regSDMA0_F32_COUNTER_BASE_IDX = 0 # macro
regSDMA0_CRD_CNTL = 0x005b # macro
regSDMA0_CRD_CNTL_BASE_IDX = 0 # macro
regSDMA0_RLC_CGCG_CTRL = 0x005c # macro
regSDMA0_RLC_CGCG_CTRL_BASE_IDX = 0 # macro
regSDMA0_AQL_STATUS = 0x005f # macro
regSDMA0_AQL_STATUS_BASE_IDX = 0 # macro
regSDMA0_EA_DBIT_ADDR_DATA = 0x0060 # macro
regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro
regSDMA0_EA_DBIT_ADDR_INDEX = 0x0061 # macro
regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro
regSDMA0_TLBI_GCR_CNTL = 0x0062 # macro
regSDMA0_TLBI_GCR_CNTL_BASE_IDX = 0 # macro
regSDMA0_TILING_CONFIG = 0x0063 # macro
regSDMA0_TILING_CONFIG_BASE_IDX = 0 # macro
regSDMA0_INT_STATUS = 0x0070 # macro
regSDMA0_INT_STATUS_BASE_IDX = 0 # macro
regSDMA0_HOLE_ADDR_LO = 0x0072 # macro
regSDMA0_HOLE_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_HOLE_ADDR_HI = 0x0073 # macro
regSDMA0_HOLE_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_CLOCK_GATING_STATUS = 0x0075 # macro
regSDMA0_CLOCK_GATING_STATUS_BASE_IDX = 0 # macro
regSDMA0_STATUS4_REG = 0x0076 # macro
regSDMA0_STATUS4_REG_BASE_IDX = 0 # macro
regSDMA0_SCRATCH_RAM_DATA = 0x0077 # macro
regSDMA0_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro
regSDMA0_SCRATCH_RAM_ADDR = 0x0078 # macro
regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro
regSDMA0_TIMESTAMP_CNTL = 0x0079 # macro
regSDMA0_TIMESTAMP_CNTL_BASE_IDX = 0 # macro
regSDMA0_STATUS5_REG = 0x007a # macro
regSDMA0_STATUS5_REG_BASE_IDX = 0 # macro
regSDMA0_QUEUE_RESET_REQ = 0x007b # macro
regSDMA0_QUEUE_RESET_REQ_BASE_IDX = 0 # macro
regSDMA0_STATUS6_REG = 0x007c # macro
regSDMA0_STATUS6_REG_BASE_IDX = 0 # macro
regSDMA0_UCODE1_CHECKSUM = 0x007d # macro
regSDMA0_UCODE1_CHECKSUM_BASE_IDX = 0 # macro
regSDMA0_CE_CTRL = 0x007e # macro
regSDMA0_CE_CTRL_BASE_IDX = 0 # macro
regSDMA0_FED_STATUS = 0x007f # macro
regSDMA0_FED_STATUS_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_RB_CNTL = 0x0080 # macro
regSDMA0_QUEUE0_RB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_RB_BASE = 0x0081 # macro
regSDMA0_QUEUE0_RB_BASE_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_RB_BASE_HI = 0x0082 # macro
regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_RB_RPTR = 0x0083 # macro
regSDMA0_QUEUE0_RB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_RB_RPTR_HI = 0x0084 # macro
regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_RB_WPTR = 0x0085 # macro
regSDMA0_QUEUE0_RB_WPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_RB_WPTR_HI = 0x0086 # macro
regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_RB_RPTR_ADDR_HI = 0x0088 # macro
regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_RB_RPTR_ADDR_LO = 0x0089 # macro
regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_IB_CNTL = 0x008a # macro
regSDMA0_QUEUE0_IB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_IB_RPTR = 0x008b # macro
regSDMA0_QUEUE0_IB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_IB_OFFSET = 0x008c # macro
regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_IB_BASE_LO = 0x008d # macro
regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_IB_BASE_HI = 0x008e # macro
regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_IB_SIZE = 0x008f # macro
regSDMA0_QUEUE0_IB_SIZE_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_SKIP_CNTL = 0x0090 # macro
regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_CONTEXT_STATUS = 0x0091 # macro
regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_DOORBELL = 0x0092 # macro
regSDMA0_QUEUE0_DOORBELL_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_DOORBELL_LOG = 0x00a9 # macro
regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_DOORBELL_OFFSET = 0x00ab # macro
regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_CSA_ADDR_LO = 0x00ac # macro
regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_CSA_ADDR_HI = 0x00ad # macro
regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_SCHEDULE_CNTL = 0x00ae # macro
regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_IB_SUB_REMAIN = 0x00af # macro
regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_PREEMPT = 0x00b0 # macro
regSDMA0_QUEUE0_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_DUMMY_REG = 0x00b1 # macro
regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI = 0x00b2 # macro
regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO = 0x00b3 # macro
regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_RB_AQL_CNTL = 0x00b4 # macro
regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_MINOR_PTR_UPDATE = 0x00b5 # macro
regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_RB_PREEMPT = 0x00b6 # macro
regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_MIDCMD_DATA0 = 0x00c0 # macro
regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_MIDCMD_DATA1 = 0x00c1 # macro
regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_MIDCMD_DATA2 = 0x00c2 # macro
regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_MIDCMD_DATA3 = 0x00c3 # macro
regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_MIDCMD_DATA4 = 0x00c4 # macro
regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_MIDCMD_DATA5 = 0x00c5 # macro
regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_MIDCMD_DATA6 = 0x00c6 # macro
regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_MIDCMD_DATA7 = 0x00c7 # macro
regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_MIDCMD_DATA8 = 0x00c8 # macro
regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_MIDCMD_DATA9 = 0x00c9 # macro
regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_MIDCMD_DATA10 = 0x00ca # macro
regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA0_QUEUE0_MIDCMD_CNTL = 0x00cb # macro
regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_RB_CNTL = 0x00d8 # macro
regSDMA0_QUEUE1_RB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_RB_BASE = 0x00d9 # macro
regSDMA0_QUEUE1_RB_BASE_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_RB_BASE_HI = 0x00da # macro
regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_RB_RPTR = 0x00db # macro
regSDMA0_QUEUE1_RB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_RB_RPTR_HI = 0x00dc # macro
regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_RB_WPTR = 0x00dd # macro
regSDMA0_QUEUE1_RB_WPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_RB_WPTR_HI = 0x00de # macro
regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_RB_RPTR_ADDR_HI = 0x00e0 # macro
regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_RB_RPTR_ADDR_LO = 0x00e1 # macro
regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_IB_CNTL = 0x00e2 # macro
regSDMA0_QUEUE1_IB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_IB_RPTR = 0x00e3 # macro
regSDMA0_QUEUE1_IB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_IB_OFFSET = 0x00e4 # macro
regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_IB_BASE_LO = 0x00e5 # macro
regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_IB_BASE_HI = 0x00e6 # macro
regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_IB_SIZE = 0x00e7 # macro
regSDMA0_QUEUE1_IB_SIZE_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_SKIP_CNTL = 0x00e8 # macro
regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_CONTEXT_STATUS = 0x00e9 # macro
regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_DOORBELL = 0x00ea # macro
regSDMA0_QUEUE1_DOORBELL_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_DOORBELL_LOG = 0x0101 # macro
regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_DOORBELL_OFFSET = 0x0103 # macro
regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_CSA_ADDR_LO = 0x0104 # macro
regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_CSA_ADDR_HI = 0x0105 # macro
regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_SCHEDULE_CNTL = 0x0106 # macro
regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_IB_SUB_REMAIN = 0x0107 # macro
regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_PREEMPT = 0x0108 # macro
regSDMA0_QUEUE1_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_DUMMY_REG = 0x0109 # macro
regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI = 0x010a # macro
regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO = 0x010b # macro
regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_RB_AQL_CNTL = 0x010c # macro
regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_MINOR_PTR_UPDATE = 0x010d # macro
regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_RB_PREEMPT = 0x010e # macro
regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_MIDCMD_DATA0 = 0x0118 # macro
regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_MIDCMD_DATA1 = 0x0119 # macro
regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_MIDCMD_DATA2 = 0x011a # macro
regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_MIDCMD_DATA3 = 0x011b # macro
regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_MIDCMD_DATA4 = 0x011c # macro
regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_MIDCMD_DATA5 = 0x011d # macro
regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_MIDCMD_DATA6 = 0x011e # macro
regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_MIDCMD_DATA7 = 0x011f # macro
regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_MIDCMD_DATA8 = 0x0120 # macro
regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_MIDCMD_DATA9 = 0x0121 # macro
regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_MIDCMD_DATA10 = 0x0122 # macro
regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA0_QUEUE1_MIDCMD_CNTL = 0x0123 # macro
regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_RB_CNTL = 0x0130 # macro
regSDMA0_QUEUE2_RB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_RB_BASE = 0x0131 # macro
regSDMA0_QUEUE2_RB_BASE_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_RB_BASE_HI = 0x0132 # macro
regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_RB_RPTR = 0x0133 # macro
regSDMA0_QUEUE2_RB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_RB_RPTR_HI = 0x0134 # macro
regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_RB_WPTR = 0x0135 # macro
regSDMA0_QUEUE2_RB_WPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_RB_WPTR_HI = 0x0136 # macro
regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_RB_RPTR_ADDR_HI = 0x0138 # macro
regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_RB_RPTR_ADDR_LO = 0x0139 # macro
regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_IB_CNTL = 0x013a # macro
regSDMA0_QUEUE2_IB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_IB_RPTR = 0x013b # macro
regSDMA0_QUEUE2_IB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_IB_OFFSET = 0x013c # macro
regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_IB_BASE_LO = 0x013d # macro
regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_IB_BASE_HI = 0x013e # macro
regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_IB_SIZE = 0x013f # macro
regSDMA0_QUEUE2_IB_SIZE_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_SKIP_CNTL = 0x0140 # macro
regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_CONTEXT_STATUS = 0x0141 # macro
regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_DOORBELL = 0x0142 # macro
regSDMA0_QUEUE2_DOORBELL_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_DOORBELL_LOG = 0x0159 # macro
regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_DOORBELL_OFFSET = 0x015b # macro
regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_CSA_ADDR_LO = 0x015c # macro
regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_CSA_ADDR_HI = 0x015d # macro
regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_SCHEDULE_CNTL = 0x015e # macro
regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_IB_SUB_REMAIN = 0x015f # macro
regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_PREEMPT = 0x0160 # macro
regSDMA0_QUEUE2_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_DUMMY_REG = 0x0161 # macro
regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI = 0x0162 # macro
regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO = 0x0163 # macro
regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_RB_AQL_CNTL = 0x0164 # macro
regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_MINOR_PTR_UPDATE = 0x0165 # macro
regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_RB_PREEMPT = 0x0166 # macro
regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_MIDCMD_DATA0 = 0x0170 # macro
regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_MIDCMD_DATA1 = 0x0171 # macro
regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_MIDCMD_DATA2 = 0x0172 # macro
regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_MIDCMD_DATA3 = 0x0173 # macro
regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_MIDCMD_DATA4 = 0x0174 # macro
regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_MIDCMD_DATA5 = 0x0175 # macro
regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_MIDCMD_DATA6 = 0x0176 # macro
regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_MIDCMD_DATA7 = 0x0177 # macro
regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_MIDCMD_DATA8 = 0x0178 # macro
regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_MIDCMD_DATA9 = 0x0179 # macro
regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_MIDCMD_DATA10 = 0x017a # macro
regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA0_QUEUE2_MIDCMD_CNTL = 0x017b # macro
regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_RB_CNTL = 0x0188 # macro
regSDMA0_QUEUE3_RB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_RB_BASE = 0x0189 # macro
regSDMA0_QUEUE3_RB_BASE_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_RB_BASE_HI = 0x018a # macro
regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_RB_RPTR = 0x018b # macro
regSDMA0_QUEUE3_RB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_RB_RPTR_HI = 0x018c # macro
regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_RB_WPTR = 0x018d # macro
regSDMA0_QUEUE3_RB_WPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_RB_WPTR_HI = 0x018e # macro
regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_RB_RPTR_ADDR_HI = 0x0190 # macro
regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_RB_RPTR_ADDR_LO = 0x0191 # macro
regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_IB_CNTL = 0x0192 # macro
regSDMA0_QUEUE3_IB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_IB_RPTR = 0x0193 # macro
regSDMA0_QUEUE3_IB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_IB_OFFSET = 0x0194 # macro
regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_IB_BASE_LO = 0x0195 # macro
regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_IB_BASE_HI = 0x0196 # macro
regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_IB_SIZE = 0x0197 # macro
regSDMA0_QUEUE3_IB_SIZE_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_SKIP_CNTL = 0x0198 # macro
regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_CONTEXT_STATUS = 0x0199 # macro
regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_DOORBELL = 0x019a # macro
regSDMA0_QUEUE3_DOORBELL_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_DOORBELL_LOG = 0x01b1 # macro
regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_DOORBELL_OFFSET = 0x01b3 # macro
regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_CSA_ADDR_LO = 0x01b4 # macro
regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_CSA_ADDR_HI = 0x01b5 # macro
regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_SCHEDULE_CNTL = 0x01b6 # macro
regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_IB_SUB_REMAIN = 0x01b7 # macro
regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_PREEMPT = 0x01b8 # macro
regSDMA0_QUEUE3_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_DUMMY_REG = 0x01b9 # macro
regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI = 0x01ba # macro
regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO = 0x01bb # macro
regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_RB_AQL_CNTL = 0x01bc # macro
regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_MINOR_PTR_UPDATE = 0x01bd # macro
regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_RB_PREEMPT = 0x01be # macro
regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_MIDCMD_DATA0 = 0x01c8 # macro
regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_MIDCMD_DATA1 = 0x01c9 # macro
regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_MIDCMD_DATA2 = 0x01ca # macro
regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_MIDCMD_DATA3 = 0x01cb # macro
regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_MIDCMD_DATA4 = 0x01cc # macro
regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_MIDCMD_DATA5 = 0x01cd # macro
regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_MIDCMD_DATA6 = 0x01ce # macro
regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_MIDCMD_DATA7 = 0x01cf # macro
regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_MIDCMD_DATA8 = 0x01d0 # macro
regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_MIDCMD_DATA9 = 0x01d1 # macro
regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_MIDCMD_DATA10 = 0x01d2 # macro
regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA0_QUEUE3_MIDCMD_CNTL = 0x01d3 # macro
regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_RB_CNTL = 0x01e0 # macro
regSDMA0_QUEUE4_RB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_RB_BASE = 0x01e1 # macro
regSDMA0_QUEUE4_RB_BASE_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_RB_BASE_HI = 0x01e2 # macro
regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_RB_RPTR = 0x01e3 # macro
regSDMA0_QUEUE4_RB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_RB_RPTR_HI = 0x01e4 # macro
regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_RB_WPTR = 0x01e5 # macro
regSDMA0_QUEUE4_RB_WPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_RB_WPTR_HI = 0x01e6 # macro
regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_RB_RPTR_ADDR_HI = 0x01e8 # macro
regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_RB_RPTR_ADDR_LO = 0x01e9 # macro
regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_IB_CNTL = 0x01ea # macro
regSDMA0_QUEUE4_IB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_IB_RPTR = 0x01eb # macro
regSDMA0_QUEUE4_IB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_IB_OFFSET = 0x01ec # macro
regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_IB_BASE_LO = 0x01ed # macro
regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_IB_BASE_HI = 0x01ee # macro
regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_IB_SIZE = 0x01ef # macro
regSDMA0_QUEUE4_IB_SIZE_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_SKIP_CNTL = 0x01f0 # macro
regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_CONTEXT_STATUS = 0x01f1 # macro
regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_DOORBELL = 0x01f2 # macro
regSDMA0_QUEUE4_DOORBELL_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_DOORBELL_LOG = 0x0209 # macro
regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_DOORBELL_OFFSET = 0x020b # macro
regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_CSA_ADDR_LO = 0x020c # macro
regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_CSA_ADDR_HI = 0x020d # macro
regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_SCHEDULE_CNTL = 0x020e # macro
regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_IB_SUB_REMAIN = 0x020f # macro
regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_PREEMPT = 0x0210 # macro
regSDMA0_QUEUE4_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_DUMMY_REG = 0x0211 # macro
regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI = 0x0212 # macro
regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO = 0x0213 # macro
regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_RB_AQL_CNTL = 0x0214 # macro
regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_MINOR_PTR_UPDATE = 0x0215 # macro
regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_RB_PREEMPT = 0x0216 # macro
regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_MIDCMD_DATA0 = 0x0220 # macro
regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_MIDCMD_DATA1 = 0x0221 # macro
regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_MIDCMD_DATA2 = 0x0222 # macro
regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_MIDCMD_DATA3 = 0x0223 # macro
regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_MIDCMD_DATA4 = 0x0224 # macro
regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_MIDCMD_DATA5 = 0x0225 # macro
regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_MIDCMD_DATA6 = 0x0226 # macro
regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_MIDCMD_DATA7 = 0x0227 # macro
regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_MIDCMD_DATA8 = 0x0228 # macro
regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_MIDCMD_DATA9 = 0x0229 # macro
regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_MIDCMD_DATA10 = 0x022a # macro
regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA0_QUEUE4_MIDCMD_CNTL = 0x022b # macro
regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_RB_CNTL = 0x0238 # macro
regSDMA0_QUEUE5_RB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_RB_BASE = 0x0239 # macro
regSDMA0_QUEUE5_RB_BASE_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_RB_BASE_HI = 0x023a # macro
regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_RB_RPTR = 0x023b # macro
regSDMA0_QUEUE5_RB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_RB_RPTR_HI = 0x023c # macro
regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_RB_WPTR = 0x023d # macro
regSDMA0_QUEUE5_RB_WPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_RB_WPTR_HI = 0x023e # macro
regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_RB_RPTR_ADDR_HI = 0x0240 # macro
regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_RB_RPTR_ADDR_LO = 0x0241 # macro
regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_IB_CNTL = 0x0242 # macro
regSDMA0_QUEUE5_IB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_IB_RPTR = 0x0243 # macro
regSDMA0_QUEUE5_IB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_IB_OFFSET = 0x0244 # macro
regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_IB_BASE_LO = 0x0245 # macro
regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_IB_BASE_HI = 0x0246 # macro
regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_IB_SIZE = 0x0247 # macro
regSDMA0_QUEUE5_IB_SIZE_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_SKIP_CNTL = 0x0248 # macro
regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_CONTEXT_STATUS = 0x0249 # macro
regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_DOORBELL = 0x024a # macro
regSDMA0_QUEUE5_DOORBELL_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_DOORBELL_LOG = 0x0261 # macro
regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_DOORBELL_OFFSET = 0x0263 # macro
regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_CSA_ADDR_LO = 0x0264 # macro
regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_CSA_ADDR_HI = 0x0265 # macro
regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_SCHEDULE_CNTL = 0x0266 # macro
regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_IB_SUB_REMAIN = 0x0267 # macro
regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_PREEMPT = 0x0268 # macro
regSDMA0_QUEUE5_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_DUMMY_REG = 0x0269 # macro
regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI = 0x026a # macro
regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO = 0x026b # macro
regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_RB_AQL_CNTL = 0x026c # macro
regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_MINOR_PTR_UPDATE = 0x026d # macro
regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_RB_PREEMPT = 0x026e # macro
regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_MIDCMD_DATA0 = 0x0278 # macro
regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_MIDCMD_DATA1 = 0x0279 # macro
regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_MIDCMD_DATA2 = 0x027a # macro
regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_MIDCMD_DATA3 = 0x027b # macro
regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_MIDCMD_DATA4 = 0x027c # macro
regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_MIDCMD_DATA5 = 0x027d # macro
regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_MIDCMD_DATA6 = 0x027e # macro
regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_MIDCMD_DATA7 = 0x027f # macro
regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_MIDCMD_DATA8 = 0x0280 # macro
regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_MIDCMD_DATA9 = 0x0281 # macro
regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_MIDCMD_DATA10 = 0x0282 # macro
regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA0_QUEUE5_MIDCMD_CNTL = 0x0283 # macro
regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_RB_CNTL = 0x0290 # macro
regSDMA0_QUEUE6_RB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_RB_BASE = 0x0291 # macro
regSDMA0_QUEUE6_RB_BASE_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_RB_BASE_HI = 0x0292 # macro
regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_RB_RPTR = 0x0293 # macro
regSDMA0_QUEUE6_RB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_RB_RPTR_HI = 0x0294 # macro
regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_RB_WPTR = 0x0295 # macro
regSDMA0_QUEUE6_RB_WPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_RB_WPTR_HI = 0x0296 # macro
regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_RB_RPTR_ADDR_HI = 0x0298 # macro
regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_RB_RPTR_ADDR_LO = 0x0299 # macro
regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_IB_CNTL = 0x029a # macro
regSDMA0_QUEUE6_IB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_IB_RPTR = 0x029b # macro
regSDMA0_QUEUE6_IB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_IB_OFFSET = 0x029c # macro
regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_IB_BASE_LO = 0x029d # macro
regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_IB_BASE_HI = 0x029e # macro
regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_IB_SIZE = 0x029f # macro
regSDMA0_QUEUE6_IB_SIZE_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_SKIP_CNTL = 0x02a0 # macro
regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_CONTEXT_STATUS = 0x02a1 # macro
regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_DOORBELL = 0x02a2 # macro
regSDMA0_QUEUE6_DOORBELL_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_DOORBELL_LOG = 0x02b9 # macro
regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_DOORBELL_OFFSET = 0x02bb # macro
regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_CSA_ADDR_LO = 0x02bc # macro
regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_CSA_ADDR_HI = 0x02bd # macro
regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_SCHEDULE_CNTL = 0x02be # macro
regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_IB_SUB_REMAIN = 0x02bf # macro
regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_PREEMPT = 0x02c0 # macro
regSDMA0_QUEUE6_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_DUMMY_REG = 0x02c1 # macro
regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI = 0x02c2 # macro
regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO = 0x02c3 # macro
regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_RB_AQL_CNTL = 0x02c4 # macro
regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_MINOR_PTR_UPDATE = 0x02c5 # macro
regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_RB_PREEMPT = 0x02c6 # macro
regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_MIDCMD_DATA0 = 0x02d0 # macro
regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_MIDCMD_DATA1 = 0x02d1 # macro
regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_MIDCMD_DATA2 = 0x02d2 # macro
regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_MIDCMD_DATA3 = 0x02d3 # macro
regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_MIDCMD_DATA4 = 0x02d4 # macro
regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_MIDCMD_DATA5 = 0x02d5 # macro
regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_MIDCMD_DATA6 = 0x02d6 # macro
regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_MIDCMD_DATA7 = 0x02d7 # macro
regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_MIDCMD_DATA8 = 0x02d8 # macro
regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_MIDCMD_DATA9 = 0x02d9 # macro
regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_MIDCMD_DATA10 = 0x02da # macro
regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA0_QUEUE6_MIDCMD_CNTL = 0x02db # macro
regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_RB_CNTL = 0x02e8 # macro
regSDMA0_QUEUE7_RB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_RB_BASE = 0x02e9 # macro
regSDMA0_QUEUE7_RB_BASE_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_RB_BASE_HI = 0x02ea # macro
regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_RB_RPTR = 0x02eb # macro
regSDMA0_QUEUE7_RB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_RB_RPTR_HI = 0x02ec # macro
regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_RB_WPTR = 0x02ed # macro
regSDMA0_QUEUE7_RB_WPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_RB_WPTR_HI = 0x02ee # macro
regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_RB_RPTR_ADDR_HI = 0x02f0 # macro
regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_RB_RPTR_ADDR_LO = 0x02f1 # macro
regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_IB_CNTL = 0x02f2 # macro
regSDMA0_QUEUE7_IB_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_IB_RPTR = 0x02f3 # macro
regSDMA0_QUEUE7_IB_RPTR_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_IB_OFFSET = 0x02f4 # macro
regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_IB_BASE_LO = 0x02f5 # macro
regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_IB_BASE_HI = 0x02f6 # macro
regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_IB_SIZE = 0x02f7 # macro
regSDMA0_QUEUE7_IB_SIZE_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_SKIP_CNTL = 0x02f8 # macro
regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_CONTEXT_STATUS = 0x02f9 # macro
regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_DOORBELL = 0x02fa # macro
regSDMA0_QUEUE7_DOORBELL_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_DOORBELL_LOG = 0x0311 # macro
regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_DOORBELL_OFFSET = 0x0313 # macro
regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_CSA_ADDR_LO = 0x0314 # macro
regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_CSA_ADDR_HI = 0x0315 # macro
regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_SCHEDULE_CNTL = 0x0316 # macro
regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_IB_SUB_REMAIN = 0x0317 # macro
regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_PREEMPT = 0x0318 # macro
regSDMA0_QUEUE7_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_DUMMY_REG = 0x0319 # macro
regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI = 0x031a # macro
regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO = 0x031b # macro
regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_RB_AQL_CNTL = 0x031c # macro
regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_MINOR_PTR_UPDATE = 0x031d # macro
regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_RB_PREEMPT = 0x031e # macro
regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_MIDCMD_DATA0 = 0x0328 # macro
regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_MIDCMD_DATA1 = 0x0329 # macro
regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_MIDCMD_DATA2 = 0x032a # macro
regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_MIDCMD_DATA3 = 0x032b # macro
regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_MIDCMD_DATA4 = 0x032c # macro
regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_MIDCMD_DATA5 = 0x032d # macro
regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_MIDCMD_DATA6 = 0x032e # macro
regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_MIDCMD_DATA7 = 0x032f # macro
regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_MIDCMD_DATA8 = 0x0330 # macro
regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_MIDCMD_DATA9 = 0x0331 # macro
regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_MIDCMD_DATA10 = 0x0332 # macro
regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA0_QUEUE7_MIDCMD_CNTL = 0x0333 # macro
regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA1_DEC_START = 0x0600 # macro
regSDMA1_DEC_START_BASE_IDX = 0 # macro
regSDMA1_F32_MISC_CNTL = 0x060b # macro
regSDMA1_F32_MISC_CNTL_BASE_IDX = 0 # macro
regSDMA1_GLOBAL_TIMESTAMP_LO = 0x060f # macro
regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro
regSDMA1_GLOBAL_TIMESTAMP_HI = 0x0610 # macro
regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro
regSDMA1_POWER_CNTL = 0x061a # macro
regSDMA1_POWER_CNTL_BASE_IDX = 0 # macro
regSDMA1_CNTL = 0x061c # macro
regSDMA1_CNTL_BASE_IDX = 0 # macro
regSDMA1_CHICKEN_BITS = 0x061d # macro
regSDMA1_CHICKEN_BITS_BASE_IDX = 0 # macro
regSDMA1_GB_ADDR_CONFIG = 0x061e # macro
regSDMA1_GB_ADDR_CONFIG_BASE_IDX = 0 # macro
regSDMA1_GB_ADDR_CONFIG_READ = 0x061f # macro
regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro
regSDMA1_RB_RPTR_FETCH = 0x0620 # macro
regSDMA1_RB_RPTR_FETCH_BASE_IDX = 0 # macro
regSDMA1_RB_RPTR_FETCH_HI = 0x0621 # macro
regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro
regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL = 0x0622 # macro
regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro
regSDMA1_IB_OFFSET_FETCH = 0x0623 # macro
regSDMA1_IB_OFFSET_FETCH_BASE_IDX = 0 # macro
regSDMA1_PROGRAM = 0x0624 # macro
regSDMA1_PROGRAM_BASE_IDX = 0 # macro
regSDMA1_STATUS_REG = 0x0625 # macro
regSDMA1_STATUS_REG_BASE_IDX = 0 # macro
regSDMA1_STATUS1_REG = 0x0626 # macro
regSDMA1_STATUS1_REG_BASE_IDX = 0 # macro
regSDMA1_CNTL1 = 0x0627 # macro
regSDMA1_CNTL1_BASE_IDX = 0 # macro
regSDMA1_HBM_PAGE_CONFIG = 0x0628 # macro
regSDMA1_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro
regSDMA1_UCODE_CHECKSUM = 0x0629 # macro
regSDMA1_UCODE_CHECKSUM_BASE_IDX = 0 # macro
regSDMA1_FREEZE = 0x062b # macro
regSDMA1_FREEZE_BASE_IDX = 0 # macro
regSDMA1_PROCESS_QUANTUM0 = 0x062c # macro
regSDMA1_PROCESS_QUANTUM0_BASE_IDX = 0 # macro
regSDMA1_PROCESS_QUANTUM1 = 0x062d # macro
regSDMA1_PROCESS_QUANTUM1_BASE_IDX = 0 # macro
regSDMA1_WATCHDOG_CNTL = 0x062e # macro
regSDMA1_WATCHDOG_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE_STATUS0 = 0x062f # macro
regSDMA1_QUEUE_STATUS0_BASE_IDX = 0 # macro
regSDMA1_EDC_CONFIG = 0x0632 # macro
regSDMA1_EDC_CONFIG_BASE_IDX = 0 # macro
regSDMA1_BA_THRESHOLD = 0x0633 # macro
regSDMA1_BA_THRESHOLD_BASE_IDX = 0 # macro
regSDMA1_ID = 0x0634 # macro
regSDMA1_ID_BASE_IDX = 0 # macro
regSDMA1_VERSION = 0x0635 # macro
regSDMA1_VERSION_BASE_IDX = 0 # macro
regSDMA1_EDC_COUNTER = 0x0636 # macro
regSDMA1_EDC_COUNTER_BASE_IDX = 0 # macro
regSDMA1_EDC_COUNTER_CLEAR = 0x0637 # macro
regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro
regSDMA1_STATUS2_REG = 0x0638 # macro
regSDMA1_STATUS2_REG_BASE_IDX = 0 # macro
regSDMA1_ATOMIC_CNTL = 0x0639 # macro
regSDMA1_ATOMIC_CNTL_BASE_IDX = 0 # macro
regSDMA1_ATOMIC_PREOP_LO = 0x063a # macro
regSDMA1_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro
regSDMA1_ATOMIC_PREOP_HI = 0x063b # macro
regSDMA1_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro
regSDMA1_UTCL1_CNTL = 0x063c # macro
regSDMA1_UTCL1_CNTL_BASE_IDX = 0 # macro
regSDMA1_UTCL1_WATERMK = 0x063d # macro
regSDMA1_UTCL1_WATERMK_BASE_IDX = 0 # macro
regSDMA1_UTCL1_TIMEOUT = 0x063e # macro
regSDMA1_UTCL1_TIMEOUT_BASE_IDX = 0 # macro
regSDMA1_UTCL1_PAGE = 0x063f # macro
regSDMA1_UTCL1_PAGE_BASE_IDX = 0 # macro
regSDMA1_UTCL1_RD_STATUS = 0x0640 # macro
regSDMA1_UTCL1_RD_STATUS_BASE_IDX = 0 # macro
regSDMA1_UTCL1_WR_STATUS = 0x0641 # macro
regSDMA1_UTCL1_WR_STATUS_BASE_IDX = 0 # macro
regSDMA1_UTCL1_INV0 = 0x0642 # macro
regSDMA1_UTCL1_INV0_BASE_IDX = 0 # macro
regSDMA1_UTCL1_INV1 = 0x0643 # macro
regSDMA1_UTCL1_INV1_BASE_IDX = 0 # macro
regSDMA1_UTCL1_INV2 = 0x0644 # macro
regSDMA1_UTCL1_INV2_BASE_IDX = 0 # macro
regSDMA1_UTCL1_RD_XNACK0 = 0x0645 # macro
regSDMA1_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro
regSDMA1_UTCL1_RD_XNACK1 = 0x0646 # macro
regSDMA1_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro
regSDMA1_UTCL1_WR_XNACK0 = 0x0647 # macro
regSDMA1_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro
regSDMA1_UTCL1_WR_XNACK1 = 0x0648 # macro
regSDMA1_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro
regSDMA1_RELAX_ORDERING_LUT = 0x064a # macro
regSDMA1_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro
regSDMA1_CHICKEN_BITS_2 = 0x064b # macro
regSDMA1_CHICKEN_BITS_2_BASE_IDX = 0 # macro
regSDMA1_STATUS3_REG = 0x064c # macro
regSDMA1_STATUS3_REG_BASE_IDX = 0 # macro
regSDMA1_PHYSICAL_ADDR_LO = 0x064d # macro
regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_PHYSICAL_ADDR_HI = 0x064e # macro
regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_GLOBAL_QUANTUM = 0x064f # macro
regSDMA1_GLOBAL_QUANTUM_BASE_IDX = 0 # macro
regSDMA1_ERROR_LOG = 0x0650 # macro
regSDMA1_ERROR_LOG_BASE_IDX = 0 # macro
regSDMA1_PUB_DUMMY_REG0 = 0x0651 # macro
regSDMA1_PUB_DUMMY_REG0_BASE_IDX = 0 # macro
regSDMA1_PUB_DUMMY_REG1 = 0x0652 # macro
regSDMA1_PUB_DUMMY_REG1_BASE_IDX = 0 # macro
regSDMA1_PUB_DUMMY_REG2 = 0x0653 # macro
regSDMA1_PUB_DUMMY_REG2_BASE_IDX = 0 # macro
regSDMA1_PUB_DUMMY_REG3 = 0x0654 # macro
regSDMA1_PUB_DUMMY_REG3_BASE_IDX = 0 # macro
regSDMA1_F32_COUNTER = 0x0655 # macro
regSDMA1_F32_COUNTER_BASE_IDX = 0 # macro
regSDMA1_CRD_CNTL = 0x065b # macro
regSDMA1_CRD_CNTL_BASE_IDX = 0 # macro
regSDMA1_RLC_CGCG_CTRL = 0x065c # macro
regSDMA1_RLC_CGCG_CTRL_BASE_IDX = 0 # macro
regSDMA1_AQL_STATUS = 0x065f # macro
regSDMA1_AQL_STATUS_BASE_IDX = 0 # macro
regSDMA1_EA_DBIT_ADDR_DATA = 0x0660 # macro
regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro
regSDMA1_EA_DBIT_ADDR_INDEX = 0x0661 # macro
regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro
regSDMA1_TLBI_GCR_CNTL = 0x0662 # macro
regSDMA1_TLBI_GCR_CNTL_BASE_IDX = 0 # macro
regSDMA1_TILING_CONFIG = 0x0663 # macro
regSDMA1_TILING_CONFIG_BASE_IDX = 0 # macro
regSDMA1_INT_STATUS = 0x0670 # macro
regSDMA1_INT_STATUS_BASE_IDX = 0 # macro
regSDMA1_HOLE_ADDR_LO = 0x0672 # macro
regSDMA1_HOLE_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_HOLE_ADDR_HI = 0x0673 # macro
regSDMA1_HOLE_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_CLOCK_GATING_STATUS = 0x0675 # macro
regSDMA1_CLOCK_GATING_STATUS_BASE_IDX = 0 # macro
regSDMA1_STATUS4_REG = 0x0676 # macro
regSDMA1_STATUS4_REG_BASE_IDX = 0 # macro
regSDMA1_SCRATCH_RAM_DATA = 0x0677 # macro
regSDMA1_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro
regSDMA1_SCRATCH_RAM_ADDR = 0x0678 # macro
regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro
regSDMA1_TIMESTAMP_CNTL = 0x0679 # macro
regSDMA1_TIMESTAMP_CNTL_BASE_IDX = 0 # macro
regSDMA1_STATUS5_REG = 0x067a # macro
regSDMA1_STATUS5_REG_BASE_IDX = 0 # macro
regSDMA1_QUEUE_RESET_REQ = 0x067b # macro
regSDMA1_QUEUE_RESET_REQ_BASE_IDX = 0 # macro
regSDMA1_STATUS6_REG = 0x067c # macro
regSDMA1_STATUS6_REG_BASE_IDX = 0 # macro
regSDMA1_UCODE1_CHECKSUM = 0x067d # macro
regSDMA1_UCODE1_CHECKSUM_BASE_IDX = 0 # macro
regSDMA1_CE_CTRL = 0x067e # macro
regSDMA1_CE_CTRL_BASE_IDX = 0 # macro
regSDMA1_FED_STATUS = 0x067f # macro
regSDMA1_FED_STATUS_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_RB_CNTL = 0x0680 # macro
regSDMA1_QUEUE0_RB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_RB_BASE = 0x0681 # macro
regSDMA1_QUEUE0_RB_BASE_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_RB_BASE_HI = 0x0682 # macro
regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_RB_RPTR = 0x0683 # macro
regSDMA1_QUEUE0_RB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_RB_RPTR_HI = 0x0684 # macro
regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_RB_WPTR = 0x0685 # macro
regSDMA1_QUEUE0_RB_WPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_RB_WPTR_HI = 0x0686 # macro
regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_RB_RPTR_ADDR_HI = 0x0688 # macro
regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_RB_RPTR_ADDR_LO = 0x0689 # macro
regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_IB_CNTL = 0x068a # macro
regSDMA1_QUEUE0_IB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_IB_RPTR = 0x068b # macro
regSDMA1_QUEUE0_IB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_IB_OFFSET = 0x068c # macro
regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_IB_BASE_LO = 0x068d # macro
regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_IB_BASE_HI = 0x068e # macro
regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_IB_SIZE = 0x068f # macro
regSDMA1_QUEUE0_IB_SIZE_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_SKIP_CNTL = 0x0690 # macro
regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_CONTEXT_STATUS = 0x0691 # macro
regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_DOORBELL = 0x0692 # macro
regSDMA1_QUEUE0_DOORBELL_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_DOORBELL_LOG = 0x06a9 # macro
regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_DOORBELL_OFFSET = 0x06ab # macro
regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_CSA_ADDR_LO = 0x06ac # macro
regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_CSA_ADDR_HI = 0x06ad # macro
regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_SCHEDULE_CNTL = 0x06ae # macro
regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_IB_SUB_REMAIN = 0x06af # macro
regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_PREEMPT = 0x06b0 # macro
regSDMA1_QUEUE0_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_DUMMY_REG = 0x06b1 # macro
regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI = 0x06b2 # macro
regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO = 0x06b3 # macro
regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_RB_AQL_CNTL = 0x06b4 # macro
regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_MINOR_PTR_UPDATE = 0x06b5 # macro
regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_RB_PREEMPT = 0x06b6 # macro
regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_MIDCMD_DATA0 = 0x06c0 # macro
regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_MIDCMD_DATA1 = 0x06c1 # macro
regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_MIDCMD_DATA2 = 0x06c2 # macro
regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_MIDCMD_DATA3 = 0x06c3 # macro
regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_MIDCMD_DATA4 = 0x06c4 # macro
regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_MIDCMD_DATA5 = 0x06c5 # macro
regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_MIDCMD_DATA6 = 0x06c6 # macro
regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_MIDCMD_DATA7 = 0x06c7 # macro
regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_MIDCMD_DATA8 = 0x06c8 # macro
regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_MIDCMD_DATA9 = 0x06c9 # macro
regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_MIDCMD_DATA10 = 0x06ca # macro
regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA1_QUEUE0_MIDCMD_CNTL = 0x06cb # macro
regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_RB_CNTL = 0x06d8 # macro
regSDMA1_QUEUE1_RB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_RB_BASE = 0x06d9 # macro
regSDMA1_QUEUE1_RB_BASE_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_RB_BASE_HI = 0x06da # macro
regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_RB_RPTR = 0x06db # macro
regSDMA1_QUEUE1_RB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_RB_RPTR_HI = 0x06dc # macro
regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_RB_WPTR = 0x06dd # macro
regSDMA1_QUEUE1_RB_WPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_RB_WPTR_HI = 0x06de # macro
regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_RB_RPTR_ADDR_HI = 0x06e0 # macro
regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_RB_RPTR_ADDR_LO = 0x06e1 # macro
regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_IB_CNTL = 0x06e2 # macro
regSDMA1_QUEUE1_IB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_IB_RPTR = 0x06e3 # macro
regSDMA1_QUEUE1_IB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_IB_OFFSET = 0x06e4 # macro
regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_IB_BASE_LO = 0x06e5 # macro
regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_IB_BASE_HI = 0x06e6 # macro
regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_IB_SIZE = 0x06e7 # macro
regSDMA1_QUEUE1_IB_SIZE_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_SKIP_CNTL = 0x06e8 # macro
regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_CONTEXT_STATUS = 0x06e9 # macro
regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_DOORBELL = 0x06ea # macro
regSDMA1_QUEUE1_DOORBELL_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_DOORBELL_LOG = 0x0701 # macro
regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_DOORBELL_OFFSET = 0x0703 # macro
regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_CSA_ADDR_LO = 0x0704 # macro
regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_CSA_ADDR_HI = 0x0705 # macro
regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_SCHEDULE_CNTL = 0x0706 # macro
regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_IB_SUB_REMAIN = 0x0707 # macro
regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_PREEMPT = 0x0708 # macro
regSDMA1_QUEUE1_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_DUMMY_REG = 0x0709 # macro
regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI = 0x070a # macro
regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO = 0x070b # macro
regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_RB_AQL_CNTL = 0x070c # macro
regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_MINOR_PTR_UPDATE = 0x070d # macro
regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_RB_PREEMPT = 0x070e # macro
regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_MIDCMD_DATA0 = 0x0718 # macro
regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_MIDCMD_DATA1 = 0x0719 # macro
regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_MIDCMD_DATA2 = 0x071a # macro
regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_MIDCMD_DATA3 = 0x071b # macro
regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_MIDCMD_DATA4 = 0x071c # macro
regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_MIDCMD_DATA5 = 0x071d # macro
regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_MIDCMD_DATA6 = 0x071e # macro
regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_MIDCMD_DATA7 = 0x071f # macro
regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_MIDCMD_DATA8 = 0x0720 # macro
regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_MIDCMD_DATA9 = 0x0721 # macro
regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_MIDCMD_DATA10 = 0x0722 # macro
regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA1_QUEUE1_MIDCMD_CNTL = 0x0723 # macro
regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_RB_CNTL = 0x0730 # macro
regSDMA1_QUEUE2_RB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_RB_BASE = 0x0731 # macro
regSDMA1_QUEUE2_RB_BASE_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_RB_BASE_HI = 0x0732 # macro
regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_RB_RPTR = 0x0733 # macro
regSDMA1_QUEUE2_RB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_RB_RPTR_HI = 0x0734 # macro
regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_RB_WPTR = 0x0735 # macro
regSDMA1_QUEUE2_RB_WPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_RB_WPTR_HI = 0x0736 # macro
regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_RB_RPTR_ADDR_HI = 0x0738 # macro
regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_RB_RPTR_ADDR_LO = 0x0739 # macro
regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_IB_CNTL = 0x073a # macro
regSDMA1_QUEUE2_IB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_IB_RPTR = 0x073b # macro
regSDMA1_QUEUE2_IB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_IB_OFFSET = 0x073c # macro
regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_IB_BASE_LO = 0x073d # macro
regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_IB_BASE_HI = 0x073e # macro
regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_IB_SIZE = 0x073f # macro
regSDMA1_QUEUE2_IB_SIZE_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_SKIP_CNTL = 0x0740 # macro
regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_CONTEXT_STATUS = 0x0741 # macro
regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_DOORBELL = 0x0742 # macro
regSDMA1_QUEUE2_DOORBELL_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_DOORBELL_LOG = 0x0759 # macro
regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_DOORBELL_OFFSET = 0x075b # macro
regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_CSA_ADDR_LO = 0x075c # macro
regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_CSA_ADDR_HI = 0x075d # macro
regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_SCHEDULE_CNTL = 0x075e # macro
regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_IB_SUB_REMAIN = 0x075f # macro
regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_PREEMPT = 0x0760 # macro
regSDMA1_QUEUE2_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_DUMMY_REG = 0x0761 # macro
regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI = 0x0762 # macro
regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO = 0x0763 # macro
regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_RB_AQL_CNTL = 0x0764 # macro
regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_MINOR_PTR_UPDATE = 0x0765 # macro
regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_RB_PREEMPT = 0x0766 # macro
regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_MIDCMD_DATA0 = 0x0770 # macro
regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_MIDCMD_DATA1 = 0x0771 # macro
regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_MIDCMD_DATA2 = 0x0772 # macro
regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_MIDCMD_DATA3 = 0x0773 # macro
regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_MIDCMD_DATA4 = 0x0774 # macro
regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_MIDCMD_DATA5 = 0x0775 # macro
regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_MIDCMD_DATA6 = 0x0776 # macro
regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_MIDCMD_DATA7 = 0x0777 # macro
regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_MIDCMD_DATA8 = 0x0778 # macro
regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_MIDCMD_DATA9 = 0x0779 # macro
regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_MIDCMD_DATA10 = 0x077a # macro
regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA1_QUEUE2_MIDCMD_CNTL = 0x077b # macro
regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_RB_CNTL = 0x0788 # macro
regSDMA1_QUEUE3_RB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_RB_BASE = 0x0789 # macro
regSDMA1_QUEUE3_RB_BASE_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_RB_BASE_HI = 0x078a # macro
regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_RB_RPTR = 0x078b # macro
regSDMA1_QUEUE3_RB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_RB_RPTR_HI = 0x078c # macro
regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_RB_WPTR = 0x078d # macro
regSDMA1_QUEUE3_RB_WPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_RB_WPTR_HI = 0x078e # macro
regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_RB_RPTR_ADDR_HI = 0x0790 # macro
regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_RB_RPTR_ADDR_LO = 0x0791 # macro
regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_IB_CNTL = 0x0792 # macro
regSDMA1_QUEUE3_IB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_IB_RPTR = 0x0793 # macro
regSDMA1_QUEUE3_IB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_IB_OFFSET = 0x0794 # macro
regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_IB_BASE_LO = 0x0795 # macro
regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_IB_BASE_HI = 0x0796 # macro
regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_IB_SIZE = 0x0797 # macro
regSDMA1_QUEUE3_IB_SIZE_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_SKIP_CNTL = 0x0798 # macro
regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_CONTEXT_STATUS = 0x0799 # macro
regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_DOORBELL = 0x079a # macro
regSDMA1_QUEUE3_DOORBELL_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_DOORBELL_LOG = 0x07b1 # macro
regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_DOORBELL_OFFSET = 0x07b3 # macro
regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_CSA_ADDR_LO = 0x07b4 # macro
regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_CSA_ADDR_HI = 0x07b5 # macro
regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_SCHEDULE_CNTL = 0x07b6 # macro
regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_IB_SUB_REMAIN = 0x07b7 # macro
regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_PREEMPT = 0x07b8 # macro
regSDMA1_QUEUE3_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_DUMMY_REG = 0x07b9 # macro
regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI = 0x07ba # macro
regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO = 0x07bb # macro
regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_RB_AQL_CNTL = 0x07bc # macro
regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_MINOR_PTR_UPDATE = 0x07bd # macro
regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_RB_PREEMPT = 0x07be # macro
regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_MIDCMD_DATA0 = 0x07c8 # macro
regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_MIDCMD_DATA1 = 0x07c9 # macro
regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_MIDCMD_DATA2 = 0x07ca # macro
regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_MIDCMD_DATA3 = 0x07cb # macro
regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_MIDCMD_DATA4 = 0x07cc # macro
regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_MIDCMD_DATA5 = 0x07cd # macro
regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_MIDCMD_DATA6 = 0x07ce # macro
regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_MIDCMD_DATA7 = 0x07cf # macro
regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_MIDCMD_DATA8 = 0x07d0 # macro
regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_MIDCMD_DATA9 = 0x07d1 # macro
regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_MIDCMD_DATA10 = 0x07d2 # macro
regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA1_QUEUE3_MIDCMD_CNTL = 0x07d3 # macro
regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_RB_CNTL = 0x07e0 # macro
regSDMA1_QUEUE4_RB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_RB_BASE = 0x07e1 # macro
regSDMA1_QUEUE4_RB_BASE_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_RB_BASE_HI = 0x07e2 # macro
regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_RB_RPTR = 0x07e3 # macro
regSDMA1_QUEUE4_RB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_RB_RPTR_HI = 0x07e4 # macro
regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_RB_WPTR = 0x07e5 # macro
regSDMA1_QUEUE4_RB_WPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_RB_WPTR_HI = 0x07e6 # macro
regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_RB_RPTR_ADDR_HI = 0x07e8 # macro
regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_RB_RPTR_ADDR_LO = 0x07e9 # macro
regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_IB_CNTL = 0x07ea # macro
regSDMA1_QUEUE4_IB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_IB_RPTR = 0x07eb # macro
regSDMA1_QUEUE4_IB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_IB_OFFSET = 0x07ec # macro
regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_IB_BASE_LO = 0x07ed # macro
regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_IB_BASE_HI = 0x07ee # macro
regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_IB_SIZE = 0x07ef # macro
regSDMA1_QUEUE4_IB_SIZE_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_SKIP_CNTL = 0x07f0 # macro
regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_CONTEXT_STATUS = 0x07f1 # macro
regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_DOORBELL = 0x07f2 # macro
regSDMA1_QUEUE4_DOORBELL_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_DOORBELL_LOG = 0x0809 # macro
regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_DOORBELL_OFFSET = 0x080b # macro
regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_CSA_ADDR_LO = 0x080c # macro
regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_CSA_ADDR_HI = 0x080d # macro
regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_SCHEDULE_CNTL = 0x080e # macro
regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_IB_SUB_REMAIN = 0x080f # macro
regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_PREEMPT = 0x0810 # macro
regSDMA1_QUEUE4_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_DUMMY_REG = 0x0811 # macro
regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI = 0x0812 # macro
regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO = 0x0813 # macro
regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_RB_AQL_CNTL = 0x0814 # macro
regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_MINOR_PTR_UPDATE = 0x0815 # macro
regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_RB_PREEMPT = 0x0816 # macro
regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_MIDCMD_DATA0 = 0x0820 # macro
regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_MIDCMD_DATA1 = 0x0821 # macro
regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_MIDCMD_DATA2 = 0x0822 # macro
regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_MIDCMD_DATA3 = 0x0823 # macro
regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_MIDCMD_DATA4 = 0x0824 # macro
regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_MIDCMD_DATA5 = 0x0825 # macro
regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_MIDCMD_DATA6 = 0x0826 # macro
regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_MIDCMD_DATA7 = 0x0827 # macro
regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_MIDCMD_DATA8 = 0x0828 # macro
regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_MIDCMD_DATA9 = 0x0829 # macro
regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_MIDCMD_DATA10 = 0x082a # macro
regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA1_QUEUE4_MIDCMD_CNTL = 0x082b # macro
regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_RB_CNTL = 0x0838 # macro
regSDMA1_QUEUE5_RB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_RB_BASE = 0x0839 # macro
regSDMA1_QUEUE5_RB_BASE_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_RB_BASE_HI = 0x083a # macro
regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_RB_RPTR = 0x083b # macro
regSDMA1_QUEUE5_RB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_RB_RPTR_HI = 0x083c # macro
regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_RB_WPTR = 0x083d # macro
regSDMA1_QUEUE5_RB_WPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_RB_WPTR_HI = 0x083e # macro
regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_RB_RPTR_ADDR_HI = 0x0840 # macro
regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_RB_RPTR_ADDR_LO = 0x0841 # macro
regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_IB_CNTL = 0x0842 # macro
regSDMA1_QUEUE5_IB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_IB_RPTR = 0x0843 # macro
regSDMA1_QUEUE5_IB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_IB_OFFSET = 0x0844 # macro
regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_IB_BASE_LO = 0x0845 # macro
regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_IB_BASE_HI = 0x0846 # macro
regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_IB_SIZE = 0x0847 # macro
regSDMA1_QUEUE5_IB_SIZE_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_SKIP_CNTL = 0x0848 # macro
regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_CONTEXT_STATUS = 0x0849 # macro
regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_DOORBELL = 0x084a # macro
regSDMA1_QUEUE5_DOORBELL_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_DOORBELL_LOG = 0x0861 # macro
regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_DOORBELL_OFFSET = 0x0863 # macro
regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_CSA_ADDR_LO = 0x0864 # macro
regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_CSA_ADDR_HI = 0x0865 # macro
regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_SCHEDULE_CNTL = 0x0866 # macro
regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_IB_SUB_REMAIN = 0x0867 # macro
regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_PREEMPT = 0x0868 # macro
regSDMA1_QUEUE5_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_DUMMY_REG = 0x0869 # macro
regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI = 0x086a # macro
regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO = 0x086b # macro
regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_RB_AQL_CNTL = 0x086c # macro
regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_MINOR_PTR_UPDATE = 0x086d # macro
regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_RB_PREEMPT = 0x086e # macro
regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_MIDCMD_DATA0 = 0x0878 # macro
regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_MIDCMD_DATA1 = 0x0879 # macro
regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_MIDCMD_DATA2 = 0x087a # macro
regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_MIDCMD_DATA3 = 0x087b # macro
regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_MIDCMD_DATA4 = 0x087c # macro
regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_MIDCMD_DATA5 = 0x087d # macro
regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_MIDCMD_DATA6 = 0x087e # macro
regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_MIDCMD_DATA7 = 0x087f # macro
regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_MIDCMD_DATA8 = 0x0880 # macro
regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_MIDCMD_DATA9 = 0x0881 # macro
regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_MIDCMD_DATA10 = 0x0882 # macro
regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA1_QUEUE5_MIDCMD_CNTL = 0x0883 # macro
regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_RB_CNTL = 0x0890 # macro
regSDMA1_QUEUE6_RB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_RB_BASE = 0x0891 # macro
regSDMA1_QUEUE6_RB_BASE_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_RB_BASE_HI = 0x0892 # macro
regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_RB_RPTR = 0x0893 # macro
regSDMA1_QUEUE6_RB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_RB_RPTR_HI = 0x0894 # macro
regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_RB_WPTR = 0x0895 # macro
regSDMA1_QUEUE6_RB_WPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_RB_WPTR_HI = 0x0896 # macro
regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_RB_RPTR_ADDR_HI = 0x0898 # macro
regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_RB_RPTR_ADDR_LO = 0x0899 # macro
regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_IB_CNTL = 0x089a # macro
regSDMA1_QUEUE6_IB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_IB_RPTR = 0x089b # macro
regSDMA1_QUEUE6_IB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_IB_OFFSET = 0x089c # macro
regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_IB_BASE_LO = 0x089d # macro
regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_IB_BASE_HI = 0x089e # macro
regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_IB_SIZE = 0x089f # macro
regSDMA1_QUEUE6_IB_SIZE_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_SKIP_CNTL = 0x08a0 # macro
regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_CONTEXT_STATUS = 0x08a1 # macro
regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_DOORBELL = 0x08a2 # macro
regSDMA1_QUEUE6_DOORBELL_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_DOORBELL_LOG = 0x08b9 # macro
regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_DOORBELL_OFFSET = 0x08bb # macro
regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_CSA_ADDR_LO = 0x08bc # macro
regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_CSA_ADDR_HI = 0x08bd # macro
regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_SCHEDULE_CNTL = 0x08be # macro
regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_IB_SUB_REMAIN = 0x08bf # macro
regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_PREEMPT = 0x08c0 # macro
regSDMA1_QUEUE6_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_DUMMY_REG = 0x08c1 # macro
regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI = 0x08c2 # macro
regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO = 0x08c3 # macro
regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_RB_AQL_CNTL = 0x08c4 # macro
regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_MINOR_PTR_UPDATE = 0x08c5 # macro
regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_RB_PREEMPT = 0x08c6 # macro
regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_MIDCMD_DATA0 = 0x08d0 # macro
regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_MIDCMD_DATA1 = 0x08d1 # macro
regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_MIDCMD_DATA2 = 0x08d2 # macro
regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_MIDCMD_DATA3 = 0x08d3 # macro
regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_MIDCMD_DATA4 = 0x08d4 # macro
regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_MIDCMD_DATA5 = 0x08d5 # macro
regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_MIDCMD_DATA6 = 0x08d6 # macro
regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_MIDCMD_DATA7 = 0x08d7 # macro
regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_MIDCMD_DATA8 = 0x08d8 # macro
regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_MIDCMD_DATA9 = 0x08d9 # macro
regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_MIDCMD_DATA10 = 0x08da # macro
regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA1_QUEUE6_MIDCMD_CNTL = 0x08db # macro
regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_RB_CNTL = 0x08e8 # macro
regSDMA1_QUEUE7_RB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_RB_BASE = 0x08e9 # macro
regSDMA1_QUEUE7_RB_BASE_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_RB_BASE_HI = 0x08ea # macro
regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_RB_RPTR = 0x08eb # macro
regSDMA1_QUEUE7_RB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_RB_RPTR_HI = 0x08ec # macro
regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_RB_WPTR = 0x08ed # macro
regSDMA1_QUEUE7_RB_WPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_RB_WPTR_HI = 0x08ee # macro
regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_RB_RPTR_ADDR_HI = 0x08f0 # macro
regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_RB_RPTR_ADDR_LO = 0x08f1 # macro
regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_IB_CNTL = 0x08f2 # macro
regSDMA1_QUEUE7_IB_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_IB_RPTR = 0x08f3 # macro
regSDMA1_QUEUE7_IB_RPTR_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_IB_OFFSET = 0x08f4 # macro
regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_IB_BASE_LO = 0x08f5 # macro
regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_IB_BASE_HI = 0x08f6 # macro
regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_IB_SIZE = 0x08f7 # macro
regSDMA1_QUEUE7_IB_SIZE_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_SKIP_CNTL = 0x08f8 # macro
regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_CONTEXT_STATUS = 0x08f9 # macro
regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_DOORBELL = 0x08fa # macro
regSDMA1_QUEUE7_DOORBELL_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_DOORBELL_LOG = 0x0911 # macro
regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_DOORBELL_OFFSET = 0x0913 # macro
regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_CSA_ADDR_LO = 0x0914 # macro
regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_CSA_ADDR_HI = 0x0915 # macro
regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_SCHEDULE_CNTL = 0x0916 # macro
regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_IB_SUB_REMAIN = 0x0917 # macro
regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_PREEMPT = 0x0918 # macro
regSDMA1_QUEUE7_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_DUMMY_REG = 0x0919 # macro
regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI = 0x091a # macro
regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO = 0x091b # macro
regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_RB_AQL_CNTL = 0x091c # macro
regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_MINOR_PTR_UPDATE = 0x091d # macro
regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_RB_PREEMPT = 0x091e # macro
regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_MIDCMD_DATA0 = 0x0928 # macro
regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_MIDCMD_DATA1 = 0x0929 # macro
regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_MIDCMD_DATA2 = 0x092a # macro
regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_MIDCMD_DATA3 = 0x092b # macro
regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_MIDCMD_DATA4 = 0x092c # macro
regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_MIDCMD_DATA5 = 0x092d # macro
regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_MIDCMD_DATA6 = 0x092e # macro
regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_MIDCMD_DATA7 = 0x092f # macro
regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_MIDCMD_DATA8 = 0x0930 # macro
regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_MIDCMD_DATA9 = 0x0931 # macro
regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_MIDCMD_DATA10 = 0x0932 # macro
regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX = 0 # macro
regSDMA1_QUEUE7_MIDCMD_CNTL = 0x0933 # macro
regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX = 0 # macro
regSDMA0_UCODE_ADDR = 0x5880 # macro
regSDMA0_UCODE_ADDR_BASE_IDX = 1 # macro
regSDMA0_UCODE_DATA = 0x5881 # macro
regSDMA0_UCODE_DATA_BASE_IDX = 1 # macro
regSDMA0_UCODE_SELFLOAD_CONTROL = 0x5882 # macro
regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX = 1 # macro
regSDMA0_BROADCAST_UCODE_ADDR = 0x5886 # macro
regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX = 1 # macro
regSDMA0_BROADCAST_UCODE_DATA = 0x5887 # macro
regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX = 1 # macro
regSDMA0_F32_CNTL = 0x589a # macro
regSDMA0_F32_CNTL_BASE_IDX = 1 # macro
regSDMA1_UCODE_ADDR = 0x58a0 # macro
regSDMA1_UCODE_ADDR_BASE_IDX = 1 # macro
regSDMA1_UCODE_DATA = 0x58a1 # macro
regSDMA1_UCODE_DATA_BASE_IDX = 1 # macro
regSDMA1_UCODE_SELFLOAD_CONTROL = 0x58a2 # macro
regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX = 1 # macro
regSDMA1_BROADCAST_UCODE_ADDR = 0x58a6 # macro
regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX = 1 # macro
regSDMA1_BROADCAST_UCODE_DATA = 0x58a7 # macro
regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX = 1 # macro
regSDMA1_F32_CNTL = 0x58ba # macro
regSDMA1_F32_CNTL_BASE_IDX = 1 # macro
regSDMA0_PERFCNT_PERFCOUNTER0_CFG = 0x3e20 # macro
regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
regSDMA0_PERFCNT_PERFCOUNTER1_CFG = 0x3e21 # macro
regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e22 # macro
regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
regSDMA0_PERFCNT_MISC_CNTL = 0x3e23 # macro
regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro
regSDMA0_PERFCOUNTER0_SELECT = 0x3e24 # macro
regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regSDMA0_PERFCOUNTER0_SELECT1 = 0x3e25 # macro
regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regSDMA0_PERFCOUNTER1_SELECT = 0x3e26 # macro
regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regSDMA0_PERFCOUNTER1_SELECT1 = 0x3e27 # macro
regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regSDMA1_PERFCNT_PERFCOUNTER0_CFG = 0x3e2c # macro
regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
regSDMA1_PERFCNT_PERFCOUNTER1_CFG = 0x3e2d # macro
regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e2e # macro
regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
regSDMA1_PERFCNT_MISC_CNTL = 0x3e2f # macro
regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro
regSDMA1_PERFCOUNTER0_SELECT = 0x3e30 # macro
regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regSDMA1_PERFCOUNTER0_SELECT1 = 0x3e31 # macro
regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regSDMA1_PERFCOUNTER1_SELECT = 0x3e32 # macro
regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regSDMA1_PERFCOUNTER1_SELECT1 = 0x3e33 # macro
regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regSDMA0_PERFCNT_PERFCOUNTER_LO = 0x3660 # macro
regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro
regSDMA0_PERFCNT_PERFCOUNTER_HI = 0x3661 # macro
regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro
regSDMA0_PERFCOUNTER0_LO = 0x3662 # macro
regSDMA0_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regSDMA0_PERFCOUNTER0_HI = 0x3663 # macro
regSDMA0_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regSDMA0_PERFCOUNTER1_LO = 0x3664 # macro
regSDMA0_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regSDMA0_PERFCOUNTER1_HI = 0x3665 # macro
regSDMA0_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regSDMA1_PERFCNT_PERFCOUNTER_LO = 0x366c # macro
regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro
regSDMA1_PERFCNT_PERFCOUNTER_HI = 0x366d # macro
regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro
regSDMA1_PERFCOUNTER0_LO = 0x366e # macro
regSDMA1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regSDMA1_PERFCOUNTER0_HI = 0x366f # macro
regSDMA1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regSDMA1_PERFCOUNTER1_LO = 0x3670 # macro
regSDMA1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regSDMA1_PERFCOUNTER1_HI = 0x3671 # macro
regSDMA1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regGRBM_CNTL = 0x0da0 # macro
regGRBM_CNTL_BASE_IDX = 0 # macro
regGRBM_SKEW_CNTL = 0x0da1 # macro
regGRBM_SKEW_CNTL_BASE_IDX = 0 # macro
regGRBM_STATUS2 = 0x0da2 # macro
regGRBM_STATUS2_BASE_IDX = 0 # macro
regGRBM_PWR_CNTL = 0x0da3 # macro
regGRBM_PWR_CNTL_BASE_IDX = 0 # macro
regGRBM_STATUS = 0x0da4 # macro
regGRBM_STATUS_BASE_IDX = 0 # macro
regGRBM_STATUS_SE0 = 0x0da5 # macro
regGRBM_STATUS_SE0_BASE_IDX = 0 # macro
regGRBM_STATUS_SE1 = 0x0da6 # macro
regGRBM_STATUS_SE1_BASE_IDX = 0 # macro
regGRBM_STATUS3 = 0x0da7 # macro
regGRBM_STATUS3_BASE_IDX = 0 # macro
regGRBM_SOFT_RESET = 0x0da8 # macro
regGRBM_SOFT_RESET_BASE_IDX = 0 # macro
regGRBM_GFX_CLKEN_CNTL = 0x0dac # macro
regGRBM_GFX_CLKEN_CNTL_BASE_IDX = 0 # macro
regGRBM_WAIT_IDLE_CLOCKS = 0x0dad # macro
regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX = 0 # macro
regGRBM_STATUS_SE2 = 0x0dae # macro
regGRBM_STATUS_SE2_BASE_IDX = 0 # macro
regGRBM_STATUS_SE3 = 0x0daf # macro
regGRBM_STATUS_SE3_BASE_IDX = 0 # macro
regGRBM_STATUS_SE4 = 0x0db0 # macro
regGRBM_STATUS_SE4_BASE_IDX = 0 # macro
regGRBM_STATUS_SE5 = 0x0db1 # macro
regGRBM_STATUS_SE5_BASE_IDX = 0 # macro
regGRBM_READ_ERROR = 0x0db6 # macro
regGRBM_READ_ERROR_BASE_IDX = 0 # macro
regGRBM_READ_ERROR2 = 0x0db7 # macro
regGRBM_READ_ERROR2_BASE_IDX = 0 # macro
regGRBM_INT_CNTL = 0x0db8 # macro
regGRBM_INT_CNTL_BASE_IDX = 0 # macro
regGRBM_TRAP_OP = 0x0db9 # macro
regGRBM_TRAP_OP_BASE_IDX = 0 # macro
regGRBM_TRAP_ADDR = 0x0dba # macro
regGRBM_TRAP_ADDR_BASE_IDX = 0 # macro
regGRBM_TRAP_ADDR_MSK = 0x0dbb # macro
regGRBM_TRAP_ADDR_MSK_BASE_IDX = 0 # macro
regGRBM_TRAP_WD = 0x0dbc # macro
regGRBM_TRAP_WD_BASE_IDX = 0 # macro
regGRBM_TRAP_WD_MSK = 0x0dbd # macro
regGRBM_TRAP_WD_MSK_BASE_IDX = 0 # macro
regGRBM_DSM_BYPASS = 0x0dbe # macro
regGRBM_DSM_BYPASS_BASE_IDX = 0 # macro
regGRBM_WRITE_ERROR = 0x0dbf # macro
regGRBM_WRITE_ERROR_BASE_IDX = 0 # macro
regGRBM_CHIP_REVISION = 0x0dc1 # macro
regGRBM_CHIP_REVISION_BASE_IDX = 0 # macro
regGRBM_IH_CREDIT = 0x0dc4 # macro
regGRBM_IH_CREDIT_BASE_IDX = 0 # macro
regGRBM_PWR_CNTL2 = 0x0dc5 # macro
regGRBM_PWR_CNTL2_BASE_IDX = 0 # macro
regGRBM_UTCL2_INVAL_RANGE_START = 0x0dc6 # macro
regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX = 0 # macro
regGRBM_UTCL2_INVAL_RANGE_END = 0x0dc7 # macro
regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX = 0 # macro
regGRBM_INVALID_PIPE = 0x0dc9 # macro
regGRBM_INVALID_PIPE_BASE_IDX = 0 # macro
regGRBM_FENCE_RANGE0 = 0x0dca # macro
regGRBM_FENCE_RANGE0_BASE_IDX = 0 # macro
regGRBM_FENCE_RANGE1 = 0x0dcb # macro
regGRBM_FENCE_RANGE1_BASE_IDX = 0 # macro
regGRBM_SCRATCH_REG0 = 0x0de0 # macro
regGRBM_SCRATCH_REG0_BASE_IDX = 0 # macro
regGRBM_SCRATCH_REG1 = 0x0de1 # macro
regGRBM_SCRATCH_REG1_BASE_IDX = 0 # macro
regGRBM_SCRATCH_REG2 = 0x0de2 # macro
regGRBM_SCRATCH_REG2_BASE_IDX = 0 # macro
regGRBM_SCRATCH_REG3 = 0x0de3 # macro
regGRBM_SCRATCH_REG3_BASE_IDX = 0 # macro
regGRBM_SCRATCH_REG4 = 0x0de4 # macro
regGRBM_SCRATCH_REG4_BASE_IDX = 0 # macro
regGRBM_SCRATCH_REG5 = 0x0de5 # macro
regGRBM_SCRATCH_REG5_BASE_IDX = 0 # macro
regGRBM_SCRATCH_REG6 = 0x0de6 # macro
regGRBM_SCRATCH_REG6_BASE_IDX = 0 # macro
regGRBM_SCRATCH_REG7 = 0x0de7 # macro
regGRBM_SCRATCH_REG7_BASE_IDX = 0 # macro
regVIOLATION_DATA_ASYNC_VF_PROG = 0x0df1 # macro
regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX = 0 # macro
regCP_CPC_DEBUG_CNTL = 0x0e20 # macro
regCP_CPC_DEBUG_CNTL_BASE_IDX = 0 # macro
regCP_CPC_DEBUG_DATA = 0x0e21 # macro
regCP_CPC_DEBUG_DATA_BASE_IDX = 0 # macro
regCP_CPC_STATUS = 0x0e24 # macro
regCP_CPC_STATUS_BASE_IDX = 0 # macro
regCP_CPC_BUSY_STAT = 0x0e25 # macro
regCP_CPC_BUSY_STAT_BASE_IDX = 0 # macro
regCP_CPC_STALLED_STAT1 = 0x0e26 # macro
regCP_CPC_STALLED_STAT1_BASE_IDX = 0 # macro
regCP_CPF_STATUS = 0x0e27 # macro
regCP_CPF_STATUS_BASE_IDX = 0 # macro
regCP_CPF_BUSY_STAT = 0x0e28 # macro
regCP_CPF_BUSY_STAT_BASE_IDX = 0 # macro
regCP_CPF_STALLED_STAT1 = 0x0e29 # macro
regCP_CPF_STALLED_STAT1_BASE_IDX = 0 # macro
regCP_CPC_BUSY_STAT2 = 0x0e2a # macro
regCP_CPC_BUSY_STAT2_BASE_IDX = 0 # macro
regCP_CPC_GRBM_FREE_COUNT = 0x0e2b # macro
regCP_CPC_GRBM_FREE_COUNT_BASE_IDX = 0 # macro
regCP_CPC_PRIV_VIOLATION_ADDR = 0x0e2c # macro
regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro
regCP_MEC_ME1_HEADER_DUMP = 0x0e2e # macro
regCP_MEC_ME1_HEADER_DUMP_BASE_IDX = 0 # macro
regCP_MEC_ME2_HEADER_DUMP = 0x0e2f # macro
regCP_MEC_ME2_HEADER_DUMP_BASE_IDX = 0 # macro
regCP_CPC_SCRATCH_INDEX = 0x0e30 # macro
regCP_CPC_SCRATCH_INDEX_BASE_IDX = 0 # macro
regCP_CPC_SCRATCH_DATA = 0x0e31 # macro
regCP_CPC_SCRATCH_DATA_BASE_IDX = 0 # macro
regCP_CPF_GRBM_FREE_COUNT = 0x0e32 # macro
regCP_CPF_GRBM_FREE_COUNT_BASE_IDX = 0 # macro
regCP_CPF_BUSY_STAT2 = 0x0e33 # macro
regCP_CPF_BUSY_STAT2_BASE_IDX = 0 # macro
regCP_CPC_HALT_HYST_COUNT = 0x0e47 # macro
regCP_CPC_HALT_HYST_COUNT_BASE_IDX = 0 # macro
regCP_STALLED_STAT3 = 0x0f3c # macro
regCP_STALLED_STAT3_BASE_IDX = 0 # macro
regCP_STALLED_STAT1 = 0x0f3d # macro
regCP_STALLED_STAT1_BASE_IDX = 0 # macro
regCP_STALLED_STAT2 = 0x0f3e # macro
regCP_STALLED_STAT2_BASE_IDX = 0 # macro
regCP_BUSY_STAT = 0x0f3f # macro
regCP_BUSY_STAT_BASE_IDX = 0 # macro
regCP_STAT = 0x0f40 # macro
regCP_STAT_BASE_IDX = 0 # macro
regCP_ME_HEADER_DUMP = 0x0f41 # macro
regCP_ME_HEADER_DUMP_BASE_IDX = 0 # macro
regCP_PFP_HEADER_DUMP = 0x0f42 # macro
regCP_PFP_HEADER_DUMP_BASE_IDX = 0 # macro
regCP_GRBM_FREE_COUNT = 0x0f43 # macro
regCP_GRBM_FREE_COUNT_BASE_IDX = 0 # macro
regCP_PFP_INSTR_PNTR = 0x0f45 # macro
regCP_PFP_INSTR_PNTR_BASE_IDX = 0 # macro
regCP_ME_INSTR_PNTR = 0x0f46 # macro
regCP_ME_INSTR_PNTR_BASE_IDX = 0 # macro
regCP_MEC1_INSTR_PNTR = 0x0f48 # macro
regCP_MEC1_INSTR_PNTR_BASE_IDX = 0 # macro
regCP_MEC2_INSTR_PNTR = 0x0f49 # macro
regCP_MEC2_INSTR_PNTR_BASE_IDX = 0 # macro
regCP_CSF_STAT = 0x0f54 # macro
regCP_CSF_STAT_BASE_IDX = 0 # macro
regCP_CNTX_STAT = 0x0f58 # macro
regCP_CNTX_STAT_BASE_IDX = 0 # macro
regCP_ME_PREEMPTION = 0x0f59 # macro
regCP_ME_PREEMPTION_BASE_IDX = 0 # macro
regCP_RB1_RPTR = 0x0f5f # macro
regCP_RB1_RPTR_BASE_IDX = 0 # macro
regCP_RB0_RPTR = 0x0f60 # macro
regCP_RB0_RPTR_BASE_IDX = 0 # macro
regCP_RB_RPTR = 0x0f60 # macro
regCP_RB_RPTR_BASE_IDX = 0 # macro
regCP_RB_WPTR_DELAY = 0x0f61 # macro
regCP_RB_WPTR_DELAY_BASE_IDX = 0 # macro
regCP_RB_WPTR_POLL_CNTL = 0x0f62 # macro
regCP_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
regCP_ROQ1_THRESHOLDS = 0x0f75 # macro
regCP_ROQ1_THRESHOLDS_BASE_IDX = 0 # macro
regCP_ROQ2_THRESHOLDS = 0x0f76 # macro
regCP_ROQ2_THRESHOLDS_BASE_IDX = 0 # macro
regCP_STQ_THRESHOLDS = 0x0f77 # macro
regCP_STQ_THRESHOLDS_BASE_IDX = 0 # macro
regCP_MEQ_THRESHOLDS = 0x0f79 # macro
regCP_MEQ_THRESHOLDS_BASE_IDX = 0 # macro
regCP_ROQ_AVAIL = 0x0f7a # macro
regCP_ROQ_AVAIL_BASE_IDX = 0 # macro
regCP_STQ_AVAIL = 0x0f7b # macro
regCP_STQ_AVAIL_BASE_IDX = 0 # macro
regCP_ROQ2_AVAIL = 0x0f7c # macro
regCP_ROQ2_AVAIL_BASE_IDX = 0 # macro
regCP_MEQ_AVAIL = 0x0f7d # macro
regCP_MEQ_AVAIL_BASE_IDX = 0 # macro
regCP_CMD_INDEX = 0x0f7e # macro
regCP_CMD_INDEX_BASE_IDX = 0 # macro
regCP_CMD_DATA = 0x0f7f # macro
regCP_CMD_DATA_BASE_IDX = 0 # macro
regCP_ROQ_RB_STAT = 0x0f80 # macro
regCP_ROQ_RB_STAT_BASE_IDX = 0 # macro
regCP_ROQ_IB1_STAT = 0x0f81 # macro
regCP_ROQ_IB1_STAT_BASE_IDX = 0 # macro
regCP_ROQ_IB2_STAT = 0x0f82 # macro
regCP_ROQ_IB2_STAT_BASE_IDX = 0 # macro
regCP_STQ_STAT = 0x0f83 # macro
regCP_STQ_STAT_BASE_IDX = 0 # macro
regCP_STQ_WR_STAT = 0x0f84 # macro
regCP_STQ_WR_STAT_BASE_IDX = 0 # macro
regCP_MEQ_STAT = 0x0f85 # macro
regCP_MEQ_STAT_BASE_IDX = 0 # macro
regCP_ROQ3_THRESHOLDS = 0x0f8c # macro
regCP_ROQ3_THRESHOLDS_BASE_IDX = 0 # macro
regCP_ROQ_DB_STAT = 0x0f8d # macro
regCP_ROQ_DB_STAT_BASE_IDX = 0 # macro
regCP_DEBUG_CNTL = 0x0f98 # macro
regCP_DEBUG_CNTL_BASE_IDX = 0 # macro
regCP_DEBUG_DATA = 0x0f99 # macro
regCP_DEBUG_DATA_BASE_IDX = 0 # macro
regCP_PRIV_VIOLATION_ADDR = 0x0f9a # macro
regCP_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro
regVGT_DMA_DATA_FIFO_DEPTH = 0x0fcd # macro
regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX = 0 # macro
regVGT_DMA_REQ_FIFO_DEPTH = 0x0fce # macro
regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX = 0 # macro
regVGT_DRAW_INIT_FIFO_DEPTH = 0x0fcf # macro
regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX = 0 # macro
regVGT_MC_LAT_CNTL = 0x0fd6 # macro
regVGT_MC_LAT_CNTL_BASE_IDX = 0 # macro
regIA_UTCL1_STATUS_2 = 0x0fd7 # macro
regIA_UTCL1_STATUS_2_BASE_IDX = 0 # macro
regWD_CNTL_STATUS = 0x0fdf # macro
regWD_CNTL_STATUS_BASE_IDX = 0 # macro
regCC_GC_PRIM_CONFIG = 0x0fe0 # macro
regCC_GC_PRIM_CONFIG_BASE_IDX = 0 # macro
regWD_QOS = 0x0fe2 # macro
regWD_QOS_BASE_IDX = 0 # macro
regWD_UTCL1_CNTL = 0x0fe3 # macro
regWD_UTCL1_CNTL_BASE_IDX = 0 # macro
regWD_UTCL1_STATUS = 0x0fe4 # macro
regWD_UTCL1_STATUS_BASE_IDX = 0 # macro
regIA_UTCL1_CNTL = 0x0fe6 # macro
regIA_UTCL1_CNTL_BASE_IDX = 0 # macro
regIA_UTCL1_STATUS = 0x0fe7 # macro
regIA_UTCL1_STATUS_BASE_IDX = 0 # macro
regCC_GC_SA_UNIT_DISABLE = 0x0fe9 # macro
regCC_GC_SA_UNIT_DISABLE_BASE_IDX = 0 # macro
regGE_RATE_CNTL_1 = 0x0ff4 # macro
regGE_RATE_CNTL_1_BASE_IDX = 0 # macro
regGE_RATE_CNTL_2 = 0x0ff5 # macro
regGE_RATE_CNTL_2_BASE_IDX = 0 # macro
regVGT_SYS_CONFIG = 0x1003 # macro
regVGT_SYS_CONFIG_BASE_IDX = 0 # macro
regGE_PRIV_CONTROL = 0x1004 # macro
regGE_PRIV_CONTROL_BASE_IDX = 0 # macro
regGE_STATUS = 0x1005 # macro
regGE_STATUS_BASE_IDX = 0 # macro
regVGT_GS_MAX_WAVE_ID = 0x1009 # macro
regVGT_GS_MAX_WAVE_ID_BASE_IDX = 0 # macro
regGFX_PIPE_CONTROL = 0x100d # macro
regGFX_PIPE_CONTROL_BASE_IDX = 0 # macro
regCC_GC_SHADER_ARRAY_CONFIG = 0x100f # macro
regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX = 0 # macro
regGE2_SE_CNTL_STATUS = 0x1011 # macro
regGE2_SE_CNTL_STATUS_BASE_IDX = 0 # macro
regGE_SPI_IF_SAFE_REG = 0x1018 # macro
regGE_SPI_IF_SAFE_REG_BASE_IDX = 0 # macro
regGE_PA_IF_SAFE_REG = 0x1019 # macro
regGE_PA_IF_SAFE_REG_BASE_IDX = 0 # macro
regPA_CL_CNTL_STATUS = 0x1024 # macro
regPA_CL_CNTL_STATUS_BASE_IDX = 0 # macro
regPA_CL_ENHANCE = 0x1025 # macro
regPA_CL_ENHANCE_BASE_IDX = 0 # macro
regPA_SU_CNTL_STATUS = 0x1034 # macro
regPA_SU_CNTL_STATUS_BASE_IDX = 0 # macro
regPA_SC_FIFO_DEPTH_CNTL = 0x1035 # macro
regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX = 0 # macro
regSQ_CONFIG = 0x10a0 # macro
regSQ_CONFIG_BASE_IDX = 0 # macro
regSQC_CONFIG = 0x10a1 # macro
regSQC_CONFIG_BASE_IDX = 0 # macro
regLDS_CONFIG = 0x10a2 # macro
regLDS_CONFIG_BASE_IDX = 0 # macro
regSQ_RANDOM_WAVE_PRI = 0x10a3 # macro
regSQ_RANDOM_WAVE_PRI_BASE_IDX = 0 # macro
regSQG_STATUS = 0x10a4 # macro
regSQG_STATUS_BASE_IDX = 0 # macro
regSQ_FIFO_SIZES = 0x10a5 # macro
regSQ_FIFO_SIZES_BASE_IDX = 0 # macro
regSQ_DSM_CNTL = 0x10a6 # macro
regSQ_DSM_CNTL_BASE_IDX = 0 # macro
regSQ_DSM_CNTL2 = 0x10a7 # macro
regSQ_DSM_CNTL2_BASE_IDX = 0 # macro
regSP_CONFIG = 0x10ab # macro
regSP_CONFIG_BASE_IDX = 0 # macro
regSQ_ARB_CONFIG = 0x10ac # macro
regSQ_ARB_CONFIG_BASE_IDX = 0 # macro
regSQ_DEBUG_HOST_TRAP_STATUS = 0x10b6 # macro
regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX = 0 # macro
regSQG_GL1H_STATUS = 0x10b9 # macro
regSQG_GL1H_STATUS_BASE_IDX = 0 # macro
regSQG_CONFIG = 0x10ba # macro
regSQG_CONFIG_BASE_IDX = 0 # macro
regSQ_PERF_SNAPSHOT_CTRL = 0x10bb # macro
regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX = 0 # macro
regCC_GC_SHADER_RATE_CONFIG = 0x10bc # macro
regCC_GC_SHADER_RATE_CONFIG_BASE_IDX = 0 # macro
regSQ_INTERRUPT_AUTO_MASK = 0x10be # macro
regSQ_INTERRUPT_AUTO_MASK_BASE_IDX = 0 # macro
regSQ_INTERRUPT_MSG_CTRL = 0x10bf # macro
regSQ_INTERRUPT_MSG_CTRL_BASE_IDX = 0 # macro
regSQ_WATCH0_ADDR_H = 0x10d0 # macro
regSQ_WATCH0_ADDR_H_BASE_IDX = 0 # macro
regSQ_WATCH0_ADDR_L = 0x10d1 # macro
regSQ_WATCH0_ADDR_L_BASE_IDX = 0 # macro
regSQ_WATCH0_CNTL = 0x10d2 # macro
regSQ_WATCH0_CNTL_BASE_IDX = 0 # macro
regSQ_WATCH1_ADDR_H = 0x10d3 # macro
regSQ_WATCH1_ADDR_H_BASE_IDX = 0 # macro
regSQ_WATCH1_ADDR_L = 0x10d4 # macro
regSQ_WATCH1_ADDR_L_BASE_IDX = 0 # macro
regSQ_WATCH1_CNTL = 0x10d5 # macro
regSQ_WATCH1_CNTL_BASE_IDX = 0 # macro
regSQ_WATCH2_ADDR_H = 0x10d6 # macro
regSQ_WATCH2_ADDR_H_BASE_IDX = 0 # macro
regSQ_WATCH2_ADDR_L = 0x10d7 # macro
regSQ_WATCH2_ADDR_L_BASE_IDX = 0 # macro
regSQ_WATCH2_CNTL = 0x10d8 # macro
regSQ_WATCH2_CNTL_BASE_IDX = 0 # macro
regSQ_WATCH3_ADDR_H = 0x10d9 # macro
regSQ_WATCH3_ADDR_H_BASE_IDX = 0 # macro
regSQ_WATCH3_ADDR_L = 0x10da # macro
regSQ_WATCH3_ADDR_L_BASE_IDX = 0 # macro
regSQ_WATCH3_CNTL = 0x10db # macro
regSQ_WATCH3_CNTL_BASE_IDX = 0 # macro
regSQ_IND_INDEX = 0x1118 # macro
regSQ_IND_INDEX_BASE_IDX = 0 # macro
regSQ_IND_DATA = 0x1119 # macro
regSQ_IND_DATA_BASE_IDX = 0 # macro
regSQ_CMD = 0x111b # macro
regSQ_CMD_BASE_IDX = 0 # macro
regSX_DEBUG_1 = 0x11b8 # macro
regSX_DEBUG_1_BASE_IDX = 0 # macro
regSPI_PS_MAX_WAVE_ID = 0x11da # macro
regSPI_PS_MAX_WAVE_ID_BASE_IDX = 0 # macro
regSPI_GFX_CNTL = 0x11dc # macro
regSPI_GFX_CNTL_BASE_IDX = 0 # macro
regSPI_DSM_CNTL = 0x11e3 # macro
regSPI_DSM_CNTL_BASE_IDX = 0 # macro
regSPI_DSM_CNTL2 = 0x11e4 # macro
regSPI_DSM_CNTL2_BASE_IDX = 0 # macro
regSPI_EDC_CNT = 0x11e5 # macro
regSPI_EDC_CNT_BASE_IDX = 0 # macro
regSPI_CONFIG_PS_CU_EN = 0x11f2 # macro
regSPI_CONFIG_PS_CU_EN_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_CNTL = 0x124a # macro
regSPI_WF_LIFETIME_CNTL_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_LIMIT_0 = 0x124b # macro
regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_LIMIT_1 = 0x124c # macro
regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_LIMIT_2 = 0x124d # macro
regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_LIMIT_3 = 0x124e # macro
regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_LIMIT_4 = 0x124f # macro
regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_LIMIT_5 = 0x1250 # macro
regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_0 = 0x1255 # macro
regSPI_WF_LIFETIME_STATUS_0_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_2 = 0x1257 # macro
regSPI_WF_LIFETIME_STATUS_2_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_4 = 0x1259 # macro
regSPI_WF_LIFETIME_STATUS_4_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_6 = 0x125b # macro
regSPI_WF_LIFETIME_STATUS_6_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_7 = 0x125c # macro
regSPI_WF_LIFETIME_STATUS_7_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_9 = 0x125e # macro
regSPI_WF_LIFETIME_STATUS_9_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_11 = 0x1260 # macro
regSPI_WF_LIFETIME_STATUS_11_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_13 = 0x1262 # macro
regSPI_WF_LIFETIME_STATUS_13_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_14 = 0x1263 # macro
regSPI_WF_LIFETIME_STATUS_14_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_15 = 0x1264 # macro
regSPI_WF_LIFETIME_STATUS_15_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_16 = 0x1265 # macro
regSPI_WF_LIFETIME_STATUS_16_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_17 = 0x1266 # macro
regSPI_WF_LIFETIME_STATUS_17_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_18 = 0x1267 # macro
regSPI_WF_LIFETIME_STATUS_18_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_19 = 0x1268 # macro
regSPI_WF_LIFETIME_STATUS_19_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_20 = 0x1269 # macro
regSPI_WF_LIFETIME_STATUS_20_BASE_IDX = 0 # macro
regSPI_WF_LIFETIME_STATUS_21 = 0x126b # macro
regSPI_WF_LIFETIME_STATUS_21_BASE_IDX = 0 # macro
regSPI_LB_CTR_CTRL = 0x1274 # macro
regSPI_LB_CTR_CTRL_BASE_IDX = 0 # macro
regSPI_LB_WGP_MASK = 0x1275 # macro
regSPI_LB_WGP_MASK_BASE_IDX = 0 # macro
regSPI_LB_DATA_REG = 0x1276 # macro
regSPI_LB_DATA_REG_BASE_IDX = 0 # macro
regSPI_PG_ENABLE_STATIC_WGP_MASK = 0x1277 # macro
regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX = 0 # macro
regSPI_GDS_CREDITS = 0x1278 # macro
regSPI_GDS_CREDITS_BASE_IDX = 0 # macro
regSPI_SX_EXPORT_BUFFER_SIZES = 0x1279 # macro
regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX = 0 # macro
regSPI_SX_SCOREBOARD_BUFFER_SIZES = 0x127a # macro
regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX = 0 # macro
regSPI_CSQ_WF_ACTIVE_STATUS = 0x127b # macro
regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX = 0 # macro
regSPI_CSQ_WF_ACTIVE_COUNT_0 = 0x127c # macro
regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX = 0 # macro
regSPI_CSQ_WF_ACTIVE_COUNT_1 = 0x127d # macro
regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX = 0 # macro
regSPI_CSQ_WF_ACTIVE_COUNT_2 = 0x127e # macro
regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX = 0 # macro
regSPI_CSQ_WF_ACTIVE_COUNT_3 = 0x127f # macro
regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX = 0 # macro
regSPI_LB_DATA_WAVES = 0x1284 # macro
regSPI_LB_DATA_WAVES_BASE_IDX = 0 # macro
regSPI_P0_TRAP_SCREEN_PSBA_LO = 0x128c # macro
regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro
regSPI_P0_TRAP_SCREEN_PSBA_HI = 0x128d # macro
regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro
regSPI_P0_TRAP_SCREEN_PSMA_LO = 0x128e # macro
regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro
regSPI_P0_TRAP_SCREEN_PSMA_HI = 0x128f # macro
regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro
regSPI_P0_TRAP_SCREEN_GPR_MIN = 0x1290 # macro
regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro
regSPI_P1_TRAP_SCREEN_PSBA_LO = 0x1291 # macro
regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro
regSPI_P1_TRAP_SCREEN_PSBA_HI = 0x1292 # macro
regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro
regSPI_P1_TRAP_SCREEN_PSMA_LO = 0x1293 # macro
regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro
regSPI_P1_TRAP_SCREEN_PSMA_HI = 0x1294 # macro
regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro
regSPI_P1_TRAP_SCREEN_GPR_MIN = 0x1295 # macro
regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro
regTD_STATUS = 0x12c6 # macro
regTD_STATUS_BASE_IDX = 0 # macro
regTD_DSM_CNTL = 0x12cf # macro
regTD_DSM_CNTL_BASE_IDX = 0 # macro
regTD_DSM_CNTL2 = 0x12d0 # macro
regTD_DSM_CNTL2_BASE_IDX = 0 # macro
regTD_SCRATCH = 0x12d3 # macro
regTD_SCRATCH_BASE_IDX = 0 # macro
regTA_CNTL = 0x12e1 # macro
regTA_CNTL_BASE_IDX = 0 # macro
regTA_CNTL_AUX = 0x12e2 # macro
regTA_CNTL_AUX_BASE_IDX = 0 # macro
regTA_CNTL2 = 0x12e5 # macro
regTA_CNTL2_BASE_IDX = 0 # macro
regTA_STATUS = 0x12e8 # macro
regTA_STATUS_BASE_IDX = 0 # macro
regTA_SCRATCH = 0x1304 # macro
regTA_SCRATCH_BASE_IDX = 0 # macro
regGDS_CONFIG = 0x1360 # macro
regGDS_CONFIG_BASE_IDX = 0 # macro
regGDS_CNTL_STATUS = 0x1361 # macro
regGDS_CNTL_STATUS_BASE_IDX = 0 # macro
regGDS_ENHANCE = 0x1362 # macro
regGDS_ENHANCE_BASE_IDX = 0 # macro
regGDS_PROTECTION_FAULT = 0x1363 # macro
regGDS_PROTECTION_FAULT_BASE_IDX = 0 # macro
regGDS_VM_PROTECTION_FAULT = 0x1364 # macro
regGDS_VM_PROTECTION_FAULT_BASE_IDX = 0 # macro
regGDS_EDC_CNT = 0x1365 # macro
regGDS_EDC_CNT_BASE_IDX = 0 # macro
regGDS_EDC_GRBM_CNT = 0x1366 # macro
regGDS_EDC_GRBM_CNT_BASE_IDX = 0 # macro
regGDS_EDC_OA_DED = 0x1367 # macro
regGDS_EDC_OA_DED_BASE_IDX = 0 # macro
regGDS_DSM_CNTL = 0x136a # macro
regGDS_DSM_CNTL_BASE_IDX = 0 # macro
regGDS_EDC_OA_PHY_CNT = 0x136b # macro
regGDS_EDC_OA_PHY_CNT_BASE_IDX = 0 # macro
regGDS_EDC_OA_PIPE_CNT = 0x136c # macro
regGDS_EDC_OA_PIPE_CNT_BASE_IDX = 0 # macro
regGDS_DSM_CNTL2 = 0x136d # macro
regGDS_DSM_CNTL2_BASE_IDX = 0 # macro
regDB_DEBUG = 0x13ac # macro
regDB_DEBUG_BASE_IDX = 0 # macro
regDB_DEBUG2 = 0x13ad # macro
regDB_DEBUG2_BASE_IDX = 0 # macro
regDB_DEBUG3 = 0x13ae # macro
regDB_DEBUG3_BASE_IDX = 0 # macro
regDB_DEBUG4 = 0x13af # macro
regDB_DEBUG4_BASE_IDX = 0 # macro
regDB_ETILE_STUTTER_CONTROL = 0x13b0 # macro
regDB_ETILE_STUTTER_CONTROL_BASE_IDX = 0 # macro
regDB_LTILE_STUTTER_CONTROL = 0x13b1 # macro
regDB_LTILE_STUTTER_CONTROL_BASE_IDX = 0 # macro
regDB_EQUAD_STUTTER_CONTROL = 0x13b2 # macro
regDB_EQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro
regDB_LQUAD_STUTTER_CONTROL = 0x13b3 # macro
regDB_LQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro
regDB_CREDIT_LIMIT = 0x13b4 # macro
regDB_CREDIT_LIMIT_BASE_IDX = 0 # macro
regDB_WATERMARKS = 0x13b5 # macro
regDB_WATERMARKS_BASE_IDX = 0 # macro
regDB_SUBTILE_CONTROL = 0x13b6 # macro
regDB_SUBTILE_CONTROL_BASE_IDX = 0 # macro
regDB_FREE_CACHELINES = 0x13b7 # macro
regDB_FREE_CACHELINES_BASE_IDX = 0 # macro
regDB_FIFO_DEPTH1 = 0x13b8 # macro
regDB_FIFO_DEPTH1_BASE_IDX = 0 # macro
regDB_FIFO_DEPTH2 = 0x13b9 # macro
regDB_FIFO_DEPTH2_BASE_IDX = 0 # macro
regDB_LAST_OF_BURST_CONFIG = 0x13ba # macro
regDB_LAST_OF_BURST_CONFIG_BASE_IDX = 0 # macro
regDB_RING_CONTROL = 0x13bb # macro
regDB_RING_CONTROL_BASE_IDX = 0 # macro
regDB_MEM_ARB_WATERMARKS = 0x13bc # macro
regDB_MEM_ARB_WATERMARKS_BASE_IDX = 0 # macro
regDB_FIFO_DEPTH3 = 0x13bd # macro
regDB_FIFO_DEPTH3_BASE_IDX = 0 # macro
regDB_DEBUG6 = 0x13be # macro
regDB_DEBUG6_BASE_IDX = 0 # macro
regDB_EXCEPTION_CONTROL = 0x13bf # macro
regDB_EXCEPTION_CONTROL_BASE_IDX = 0 # macro
regDB_DEBUG7 = 0x13d0 # macro
regDB_DEBUG7_BASE_IDX = 0 # macro
regDB_DEBUG5 = 0x13d1 # macro
regDB_DEBUG5_BASE_IDX = 0 # macro
regDB_FGCG_SRAMS_CLK_CTRL = 0x13d7 # macro
regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX = 0 # macro
regDB_FGCG_INTERFACES_CLK_CTRL = 0x13d8 # macro
regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX = 0 # macro
regDB_FIFO_DEPTH4 = 0x13d9 # macro
regDB_FIFO_DEPTH4_BASE_IDX = 0 # macro
regCC_RB_REDUNDANCY = 0x13dc # macro
regCC_RB_REDUNDANCY_BASE_IDX = 0 # macro
regCC_RB_BACKEND_DISABLE = 0x13dd # macro
regCC_RB_BACKEND_DISABLE_BASE_IDX = 0 # macro
regGB_ADDR_CONFIG = 0x13de # macro
regGB_ADDR_CONFIG_BASE_IDX = 0 # macro
regGB_BACKEND_MAP = 0x13df # macro
regGB_BACKEND_MAP_BASE_IDX = 0 # macro
regGB_GPU_ID = 0x13e0 # macro
regGB_GPU_ID_BASE_IDX = 0 # macro
regCC_RB_DAISY_CHAIN = 0x13e1 # macro
regCC_RB_DAISY_CHAIN_BASE_IDX = 0 # macro
regGB_ADDR_CONFIG_READ = 0x13e2 # macro
regGB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro
regCB_HW_CONTROL_4 = 0x1422 # macro
regCB_HW_CONTROL_4_BASE_IDX = 0 # macro
regCB_HW_CONTROL_3 = 0x1423 # macro
regCB_HW_CONTROL_3_BASE_IDX = 0 # macro
regCB_HW_CONTROL = 0x1424 # macro
regCB_HW_CONTROL_BASE_IDX = 0 # macro
regCB_HW_CONTROL_1 = 0x1425 # macro
regCB_HW_CONTROL_1_BASE_IDX = 0 # macro
regCB_HW_CONTROL_2 = 0x1426 # macro
regCB_HW_CONTROL_2_BASE_IDX = 0 # macro
regCB_DCC_CONFIG = 0x1427 # macro
regCB_DCC_CONFIG_BASE_IDX = 0 # macro
regCB_HW_MEM_ARBITER_RD = 0x1428 # macro
regCB_HW_MEM_ARBITER_RD_BASE_IDX = 0 # macro
regCB_HW_MEM_ARBITER_WR = 0x1429 # macro
regCB_HW_MEM_ARBITER_WR_BASE_IDX = 0 # macro
regCB_FGCG_SRAM_OVERRIDE = 0x142a # macro
regCB_FGCG_SRAM_OVERRIDE_BASE_IDX = 0 # macro
regCB_DCC_CONFIG2 = 0x142b # macro
regCB_DCC_CONFIG2_BASE_IDX = 0 # macro
regCHICKEN_BITS = 0x142d # macro
regCHICKEN_BITS_BASE_IDX = 0 # macro
regCB_CACHE_EVICT_POINTS = 0x142e # macro
regCB_CACHE_EVICT_POINTS_BASE_IDX = 0 # macro
regGCEA_DRAM_RD_CLI2GRP_MAP0 = 0x17a0 # macro
regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro
regGCEA_DRAM_RD_CLI2GRP_MAP1 = 0x17a1 # macro
regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro
regGCEA_DRAM_WR_CLI2GRP_MAP0 = 0x17a2 # macro
regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro
regGCEA_DRAM_WR_CLI2GRP_MAP1 = 0x17a3 # macro
regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro
regGCEA_DRAM_RD_GRP2VC_MAP = 0x17a4 # macro
regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX = 0 # macro
regGCEA_DRAM_WR_GRP2VC_MAP = 0x17a5 # macro
regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX = 0 # macro
regGCEA_DRAM_RD_LAZY = 0x17a6 # macro
regGCEA_DRAM_RD_LAZY_BASE_IDX = 0 # macro
regGCEA_DRAM_WR_LAZY = 0x17a7 # macro
regGCEA_DRAM_WR_LAZY_BASE_IDX = 0 # macro
regGCEA_DRAM_RD_CAM_CNTL = 0x17a8 # macro
regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX = 0 # macro
regGCEA_DRAM_WR_CAM_CNTL = 0x17a9 # macro
regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX = 0 # macro
regGCEA_DRAM_PAGE_BURST = 0x17aa # macro
regGCEA_DRAM_PAGE_BURST_BASE_IDX = 0 # macro
regGCEA_DRAM_RD_PRI_AGE = 0x17ab # macro
regGCEA_DRAM_RD_PRI_AGE_BASE_IDX = 0 # macro
regGCEA_DRAM_WR_PRI_AGE = 0x17ac # macro
regGCEA_DRAM_WR_PRI_AGE_BASE_IDX = 0 # macro
regGCEA_DRAM_RD_PRI_QUEUING = 0x17ad # macro
regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX = 0 # macro
regGCEA_DRAM_WR_PRI_QUEUING = 0x17ae # macro
regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX = 0 # macro
regGCEA_DRAM_RD_PRI_FIXED = 0x17af # macro
regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX = 0 # macro
regGCEA_DRAM_WR_PRI_FIXED = 0x17b0 # macro
regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX = 0 # macro
regGCEA_DRAM_RD_PRI_URGENCY = 0x17b1 # macro
regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX = 0 # macro
regGCEA_DRAM_WR_PRI_URGENCY = 0x17b2 # macro
regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX = 0 # macro
regGCEA_DRAM_RD_PRI_QUANT_PRI1 = 0x17b3 # macro
regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro
regGCEA_DRAM_RD_PRI_QUANT_PRI2 = 0x17b4 # macro
regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro
regGCEA_DRAM_RD_PRI_QUANT_PRI3 = 0x17b5 # macro
regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro
regGCEA_DRAM_WR_PRI_QUANT_PRI1 = 0x17b6 # macro
regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro
regGCEA_DRAM_WR_PRI_QUANT_PRI2 = 0x17b7 # macro
regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro
regGCEA_DRAM_WR_PRI_QUANT_PRI3 = 0x17b8 # macro
regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro
regGCEA_IO_RD_CLI2GRP_MAP0 = 0x187d # macro
regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro
regGCEA_IO_RD_CLI2GRP_MAP1 = 0x187e # macro
regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro
regGCEA_IO_WR_CLI2GRP_MAP0 = 0x187f # macro
regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro
regGCEA_IO_WR_CLI2GRP_MAP1 = 0x1880 # macro
regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro
regGCEA_IO_RD_COMBINE_FLUSH = 0x1881 # macro
regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX = 0 # macro
regGCEA_IO_WR_COMBINE_FLUSH = 0x1882 # macro
regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX = 0 # macro
regGCEA_IO_GROUP_BURST = 0x1883 # macro
regGCEA_IO_GROUP_BURST_BASE_IDX = 0 # macro
regGCEA_IO_RD_PRI_AGE = 0x1884 # macro
regGCEA_IO_RD_PRI_AGE_BASE_IDX = 0 # macro
regGCEA_IO_WR_PRI_AGE = 0x1885 # macro
regGCEA_IO_WR_PRI_AGE_BASE_IDX = 0 # macro
regGCEA_IO_RD_PRI_QUEUING = 0x1886 # macro
regGCEA_IO_RD_PRI_QUEUING_BASE_IDX = 0 # macro
regGCEA_IO_WR_PRI_QUEUING = 0x1887 # macro
regGCEA_IO_WR_PRI_QUEUING_BASE_IDX = 0 # macro
regGCEA_IO_RD_PRI_FIXED = 0x1888 # macro
regGCEA_IO_RD_PRI_FIXED_BASE_IDX = 0 # macro
regGCEA_IO_WR_PRI_FIXED = 0x1889 # macro
regGCEA_IO_WR_PRI_FIXED_BASE_IDX = 0 # macro
regGCEA_IO_RD_PRI_URGENCY = 0x188a # macro
regGCEA_IO_RD_PRI_URGENCY_BASE_IDX = 0 # macro
regGCEA_IO_WR_PRI_URGENCY = 0x188b # macro
regGCEA_IO_WR_PRI_URGENCY_BASE_IDX = 0 # macro
regGCEA_IO_RD_PRI_URGENCY_MASKING = 0x188c # macro
regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro
regGCEA_IO_WR_PRI_URGENCY_MASKING = 0x188d # macro
regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro
regGCEA_IO_RD_PRI_QUANT_PRI1 = 0x188e # macro
regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro
regGCEA_IO_RD_PRI_QUANT_PRI2 = 0x188f # macro
regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro
regGCEA_IO_RD_PRI_QUANT_PRI3 = 0x1890 # macro
regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro
regGCEA_IO_WR_PRI_QUANT_PRI1 = 0x1891 # macro
regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro
regGCEA_IO_WR_PRI_QUANT_PRI2 = 0x1892 # macro
regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro
regGCEA_IO_WR_PRI_QUANT_PRI3 = 0x1893 # macro
regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro
regGCEA_SDP_ARB_FINAL = 0x1896 # macro
regGCEA_SDP_ARB_FINAL_BASE_IDX = 0 # macro
regGCEA_SDP_IO_PRIORITY = 0x1899 # macro
regGCEA_SDP_IO_PRIORITY_BASE_IDX = 0 # macro
regGCEA_SDP_CREDITS = 0x189a # macro
regGCEA_SDP_CREDITS_BASE_IDX = 0 # macro
regGCEA_SDP_TAG_RESERVE0 = 0x189b # macro
regGCEA_SDP_TAG_RESERVE0_BASE_IDX = 0 # macro
regGCEA_SDP_TAG_RESERVE1 = 0x189c # macro
regGCEA_SDP_TAG_RESERVE1_BASE_IDX = 0 # macro
regGCEA_SDP_VCC_RESERVE0 = 0x189d # macro
regGCEA_SDP_VCC_RESERVE0_BASE_IDX = 0 # macro
regGCEA_SDP_VCC_RESERVE1 = 0x189e # macro
regGCEA_SDP_VCC_RESERVE1_BASE_IDX = 0 # macro
regGCEA_MISC = 0x14a2 # macro
regGCEA_MISC_BASE_IDX = 0 # macro
regGCEA_LATENCY_SAMPLING = 0x14a3 # macro
regGCEA_LATENCY_SAMPLING_BASE_IDX = 0 # macro
regGCEA_MAM_CTRL2 = 0x14a9 # macro
regGCEA_MAM_CTRL2_BASE_IDX = 0 # macro
regGCEA_MAM_CTRL = 0x14ab # macro
regGCEA_MAM_CTRL_BASE_IDX = 0 # macro
regGCEA_EDC_CNT = 0x14b2 # macro
regGCEA_EDC_CNT_BASE_IDX = 0 # macro
regGCEA_EDC_CNT2 = 0x14b3 # macro
regGCEA_EDC_CNT2_BASE_IDX = 0 # macro
regGCEA_DSM_CNTL = 0x14b4 # macro
regGCEA_DSM_CNTL_BASE_IDX = 0 # macro
regGCEA_DSM_CNTLA = 0x14b5 # macro
regGCEA_DSM_CNTLA_BASE_IDX = 0 # macro
regGCEA_DSM_CNTLB = 0x14b6 # macro
regGCEA_DSM_CNTLB_BASE_IDX = 0 # macro
regGCEA_DSM_CNTL2 = 0x14b7 # macro
regGCEA_DSM_CNTL2_BASE_IDX = 0 # macro
regGCEA_DSM_CNTL2A = 0x14b8 # macro
regGCEA_DSM_CNTL2A_BASE_IDX = 0 # macro
regGCEA_DSM_CNTL2B = 0x14b9 # macro
regGCEA_DSM_CNTL2B_BASE_IDX = 0 # macro
regGCEA_GL2C_XBR_CREDITS = 0x14ba # macro
regGCEA_GL2C_XBR_CREDITS_BASE_IDX = 0 # macro
regGCEA_GL2C_XBR_MAXBURST = 0x14bb # macro
regGCEA_GL2C_XBR_MAXBURST_BASE_IDX = 0 # macro
regGCEA_PROBE_CNTL = 0x14bc # macro
regGCEA_PROBE_CNTL_BASE_IDX = 0 # macro
regGCEA_PROBE_MAP = 0x14bd # macro
regGCEA_PROBE_MAP_BASE_IDX = 0 # macro
regGCEA_ERR_STATUS = 0x14be # macro
regGCEA_ERR_STATUS_BASE_IDX = 0 # macro
regGCEA_MISC2 = 0x14bf # macro
regGCEA_MISC2_BASE_IDX = 0 # macro
regGCEA_RRET_MEM_RESERVE = 0x1518 # macro
regGCEA_RRET_MEM_RESERVE_BASE_IDX = 0 # macro
regGCEA_EDC_CNT3 = 0x151a # macro
regGCEA_EDC_CNT3_BASE_IDX = 0 # macro
regGCEA_SDP_ENABLE = 0x151e # macro
regGCEA_SDP_ENABLE_BASE_IDX = 0 # macro
regSPI_PQEV_CTRL = 0x14c0 # macro
regSPI_PQEV_CTRL_BASE_IDX = 0 # macro
regSPI_EXP_THROTTLE_CTRL = 0x14c3 # macro
regSPI_EXP_THROTTLE_CTRL_BASE_IDX = 0 # macro
regRMI_GENERAL_CNTL = 0x1880 # macro
regRMI_GENERAL_CNTL_BASE_IDX = 1 # macro
regRMI_GENERAL_CNTL1 = 0x1881 # macro
regRMI_GENERAL_CNTL1_BASE_IDX = 1 # macro
regRMI_GENERAL_STATUS = 0x1882 # macro
regRMI_GENERAL_STATUS_BASE_IDX = 1 # macro
regRMI_SUBBLOCK_STATUS0 = 0x1883 # macro
regRMI_SUBBLOCK_STATUS0_BASE_IDX = 1 # macro
regRMI_SUBBLOCK_STATUS1 = 0x1884 # macro
regRMI_SUBBLOCK_STATUS1_BASE_IDX = 1 # macro
regRMI_SUBBLOCK_STATUS2 = 0x1885 # macro
regRMI_SUBBLOCK_STATUS2_BASE_IDX = 1 # macro
regRMI_SUBBLOCK_STATUS3 = 0x1886 # macro
regRMI_SUBBLOCK_STATUS3_BASE_IDX = 1 # macro
regRMI_XBAR_CONFIG = 0x1887 # macro
regRMI_XBAR_CONFIG_BASE_IDX = 1 # macro
regRMI_PROBE_POP_LOGIC_CNTL = 0x1888 # macro
regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX = 1 # macro
regRMI_UTC_XNACK_N_MISC_CNTL = 0x1889 # macro
regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX = 1 # macro
regRMI_DEMUX_CNTL = 0x188a # macro
regRMI_DEMUX_CNTL_BASE_IDX = 1 # macro
regRMI_UTCL1_CNTL1 = 0x188b # macro
regRMI_UTCL1_CNTL1_BASE_IDX = 1 # macro
regRMI_UTCL1_CNTL2 = 0x188c # macro
regRMI_UTCL1_CNTL2_BASE_IDX = 1 # macro
regRMI_UTC_UNIT_CONFIG = 0x188d # macro
regRMI_UTC_UNIT_CONFIG_BASE_IDX = 1 # macro
regRMI_TCIW_FORMATTER0_CNTL = 0x188e # macro
regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX = 1 # macro
regRMI_TCIW_FORMATTER1_CNTL = 0x188f # macro
regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX = 1 # macro
regRMI_SCOREBOARD_CNTL = 0x1890 # macro
regRMI_SCOREBOARD_CNTL_BASE_IDX = 1 # macro
regRMI_SCOREBOARD_STATUS0 = 0x1891 # macro
regRMI_SCOREBOARD_STATUS0_BASE_IDX = 1 # macro
regRMI_SCOREBOARD_STATUS1 = 0x1892 # macro
regRMI_SCOREBOARD_STATUS1_BASE_IDX = 1 # macro
regRMI_SCOREBOARD_STATUS2 = 0x1893 # macro
regRMI_SCOREBOARD_STATUS2_BASE_IDX = 1 # macro
regRMI_XBAR_ARBITER_CONFIG = 0x1894 # macro
regRMI_XBAR_ARBITER_CONFIG_BASE_IDX = 1 # macro
regRMI_XBAR_ARBITER_CONFIG_1 = 0x1895 # macro
regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX = 1 # macro
regRMI_CLOCK_CNTRL = 0x1896 # macro
regRMI_CLOCK_CNTRL_BASE_IDX = 1 # macro
regRMI_UTCL1_STATUS = 0x1897 # macro
regRMI_UTCL1_STATUS_BASE_IDX = 1 # macro
regRMI_RB_GLX_CID_MAP = 0x1898 # macro
regRMI_RB_GLX_CID_MAP_BASE_IDX = 1 # macro
regRMI_SPARE = 0x189f # macro
regRMI_SPARE_BASE_IDX = 1 # macro
regRMI_SPARE_1 = 0x18a0 # macro
regRMI_SPARE_1_BASE_IDX = 1 # macro
regRMI_SPARE_2 = 0x18a1 # macro
regRMI_SPARE_2_BASE_IDX = 1 # macro
regCC_RMI_REDUNDANCY = 0x18a2 # macro
regCC_RMI_REDUNDANCY_BASE_IDX = 1 # macro
regGCR_PIO_CNTL = 0x1580 # macro
regGCR_PIO_CNTL_BASE_IDX = 0 # macro
regGCR_PIO_DATA = 0x1581 # macro
regGCR_PIO_DATA_BASE_IDX = 0 # macro
regPMM_CNTL = 0x1582 # macro
regPMM_CNTL_BASE_IDX = 0 # macro
regPMM_STATUS = 0x1583 # macro
regPMM_STATUS_BASE_IDX = 0 # macro
regUTCL1_CTRL_1 = 0x158c # macro
regUTCL1_CTRL_1_BASE_IDX = 0 # macro
regUTCL1_ALOG = 0x158f # macro
regUTCL1_ALOG_BASE_IDX = 0 # macro
regUTCL1_STATUS = 0x1594 # macro
regUTCL1_STATUS_BASE_IDX = 0 # macro
regGCMC_VM_NB_TOP_OF_DRAM_SLOT1 = 0x15a4 # macro
regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX = 0 # macro
regGCMC_VM_NB_LOWER_TOP_OF_DRAM2 = 0x15a5 # macro
regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX = 0 # macro
regGCMC_VM_NB_UPPER_TOP_OF_DRAM2 = 0x15a6 # macro
regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX = 0 # macro
regGCMC_VM_FB_OFFSET = 0x15a7 # macro
regGCMC_VM_FB_OFFSET_BASE_IDX = 0 # macro
regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x15a8 # macro
regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX = 0 # macro
regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x15a9 # macro
regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX = 0 # macro
regGCMC_VM_STEERING = 0x15aa # macro
regGCMC_VM_STEERING_BASE_IDX = 0 # macro
regGCMC_MEM_POWER_LS = 0x15ac # macro
regGCMC_MEM_POWER_LS_BASE_IDX = 0 # macro
regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START = 0x15ad # macro
regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX = 0 # macro
regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END = 0x15ae # macro
regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX = 0 # macro
regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START = 0x15af # macro
regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX = 0 # macro
regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END = 0x15b0 # macro
regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX = 0 # macro
regGCMC_VM_APT_CNTL = 0x15b1 # macro
regGCMC_VM_APT_CNTL_BASE_IDX = 0 # macro
regGCMC_VM_LOCAL_FB_ADDRESS_START = 0x15b2 # macro
regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX = 0 # macro
regGCMC_VM_LOCAL_FB_ADDRESS_END = 0x15b3 # macro
regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX = 0 # macro
regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL = 0x15b4 # macro
regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX = 0 # macro
regGCUTCL2_ICG_CTRL = 0x15b5 # macro
regGCUTCL2_ICG_CTRL_BASE_IDX = 0 # macro
regGCUTCL2_CGTT_BUSY_CTRL = 0x15b7 # macro
regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro
regGCMC_VM_FB_NOALLOC_CNTL = 0x15b8 # macro
regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX = 0 # macro
regGCUTCL2_HARVEST_BYPASS_GROUPS = 0x15b9 # macro
regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX = 0 # macro
regGCUTCL2_GROUP_RET_FAULT_STATUS = 0x15bb # macro
regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX = 0 # macro
regGCVM_L2_CNTL = 0x15bc # macro
regGCVM_L2_CNTL_BASE_IDX = 0 # macro
regGCVM_L2_CNTL2 = 0x15bd # macro
regGCVM_L2_CNTL2_BASE_IDX = 0 # macro
regGCVM_L2_CNTL3 = 0x15be # macro
regGCVM_L2_CNTL3_BASE_IDX = 0 # macro
regGCVM_L2_STATUS = 0x15bf # macro
regGCVM_L2_STATUS_BASE_IDX = 0 # macro
regGCVM_DUMMY_PAGE_FAULT_CNTL = 0x15c0 # macro
regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX = 0 # macro
regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 = 0x15c1 # macro
regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 = 0x15c2 # macro
regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_CNTL = 0x15c3 # macro
regGCVM_INVALIDATE_CNTL_BASE_IDX = 0 # macro
regGCVM_L2_PROTECTION_FAULT_CNTL = 0x15c4 # macro
regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX = 0 # macro
regGCVM_L2_PROTECTION_FAULT_CNTL2 = 0x15c5 # macro
regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX = 0 # macro
regGCVM_L2_PROTECTION_FAULT_MM_CNTL3 = 0x15c6 # macro
regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX = 0 # macro
regGCVM_L2_PROTECTION_FAULT_MM_CNTL4 = 0x15c7 # macro
regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX = 0 # macro
regGCVM_L2_PROTECTION_FAULT_STATUS = 0x15c8 # macro
regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX = 0 # macro
regGCVM_L2_PROTECTION_FAULT_ADDR_LO32 = 0x15c9 # macro
regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_L2_PROTECTION_FAULT_ADDR_HI32 = 0x15ca # macro
regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 = 0x15cb # macro
regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 = 0x15cc # macro
regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 = 0x15ce # macro
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 = 0x15cf # macro
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 = 0x15d0 # macro
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 = 0x15d1 # macro
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 = 0x15d2 # macro
regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 = 0x15d3 # macro
regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX = 0 # macro
regGCVM_L2_CNTL4 = 0x15d4 # macro
regGCVM_L2_CNTL4_BASE_IDX = 0 # macro
regGCVM_L2_MM_GROUP_RT_CLASSES = 0x15d5 # macro
regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 # macro
regGCVM_L2_BANK_SELECT_RESERVED_CID = 0x15d6 # macro
regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX = 0 # macro
regGCVM_L2_BANK_SELECT_RESERVED_CID2 = 0x15d7 # macro
regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX = 0 # macro
regGCVM_L2_CACHE_PARITY_CNTL = 0x15d8 # macro
regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX = 0 # macro
regGCVM_L2_ICG_CTRL = 0x15d9 # macro
regGCVM_L2_ICG_CTRL_BASE_IDX = 0 # macro
regGCVM_L2_CNTL5 = 0x15da # macro
regGCVM_L2_CNTL5_BASE_IDX = 0 # macro
regGCVM_L2_GCR_CNTL = 0x15db # macro
regGCVM_L2_GCR_CNTL_BASE_IDX = 0 # macro
regGCVML2_WALKER_MACRO_THROTTLE_TIME = 0x15dc # macro
regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX = 0 # macro
regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT = 0x15dd # macro
regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro
regGCVML2_WALKER_MICRO_THROTTLE_TIME = 0x15de # macro
regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX = 0 # macro
regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT = 0x15df # macro
regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro
regGCVM_L2_CGTT_BUSY_CTRL = 0x15e0 # macro
regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro
regGCVM_L2_PTE_CACHE_DUMP_CNTL = 0x15e1 # macro
regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX = 0 # macro
regGCVM_L2_PTE_CACHE_DUMP_READ = 0x15e2 # macro
regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX = 0 # macro
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO = 0x15e5 # macro
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX = 0 # macro
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI = 0x15e6 # macro
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX = 0 # macro
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO = 0x15e7 # macro
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX = 0 # macro
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI = 0x15e8 # macro
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX = 0 # macro
regGCVM_L2_BANK_SELECT_MASKS = 0x15e9 # macro
regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX = 0 # macro
regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC = 0x15ea # macro
regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX = 0 # macro
regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC = 0x15eb # macro
regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX = 0 # macro
regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC = 0x15ec # macro
regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX = 0 # macro
regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT = 0x15ed # macro
regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX = 0 # macro
regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ = 0x15ee # macro
regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX = 0 # macro
regGCMC_VM_FB_LOCATION_BASE = 0x1678 # macro
regGCMC_VM_FB_LOCATION_BASE_BASE_IDX = 0 # macro
regGCMC_VM_FB_LOCATION_TOP = 0x1679 # macro
regGCMC_VM_FB_LOCATION_TOP_BASE_IDX = 0 # macro
regGCMC_VM_AGP_TOP = 0x167a # macro
regGCMC_VM_AGP_TOP_BASE_IDX = 0 # macro
regGCMC_VM_AGP_BOT = 0x167b # macro
regGCMC_VM_AGP_BOT_BASE_IDX = 0 # macro
regGCMC_VM_AGP_BASE = 0x167c # macro
regGCMC_VM_AGP_BASE_BASE_IDX = 0 # macro
regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x167d # macro
regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX = 0 # macro
regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x167e # macro
regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX = 0 # macro
regGCMC_VM_MX_L1_TLB_CNTL = 0x167f # macro
regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT0_CNTL = 0x1688 # macro
regGCVM_CONTEXT0_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT1_CNTL = 0x1689 # macro
regGCVM_CONTEXT1_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT2_CNTL = 0x168a # macro
regGCVM_CONTEXT2_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT3_CNTL = 0x168b # macro
regGCVM_CONTEXT3_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT4_CNTL = 0x168c # macro
regGCVM_CONTEXT4_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT5_CNTL = 0x168d # macro
regGCVM_CONTEXT5_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT6_CNTL = 0x168e # macro
regGCVM_CONTEXT6_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT7_CNTL = 0x168f # macro
regGCVM_CONTEXT7_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT8_CNTL = 0x1690 # macro
regGCVM_CONTEXT8_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT9_CNTL = 0x1691 # macro
regGCVM_CONTEXT9_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT10_CNTL = 0x1692 # macro
regGCVM_CONTEXT10_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT11_CNTL = 0x1693 # macro
regGCVM_CONTEXT11_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT12_CNTL = 0x1694 # macro
regGCVM_CONTEXT12_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT13_CNTL = 0x1695 # macro
regGCVM_CONTEXT13_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT14_CNTL = 0x1696 # macro
regGCVM_CONTEXT14_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXT15_CNTL = 0x1697 # macro
regGCVM_CONTEXT15_CNTL_BASE_IDX = 0 # macro
regGCVM_CONTEXTS_DISABLE = 0x1698 # macro
regGCVM_CONTEXTS_DISABLE_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG0_SEM = 0x1699 # macro
regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG1_SEM = 0x169a # macro
regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG2_SEM = 0x169b # macro
regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG3_SEM = 0x169c # macro
regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG4_SEM = 0x169d # macro
regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG5_SEM = 0x169e # macro
regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG6_SEM = 0x169f # macro
regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG7_SEM = 0x16a0 # macro
regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG8_SEM = 0x16a1 # macro
regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG9_SEM = 0x16a2 # macro
regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG10_SEM = 0x16a3 # macro
regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG11_SEM = 0x16a4 # macro
regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG12_SEM = 0x16a5 # macro
regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG13_SEM = 0x16a6 # macro
regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG14_SEM = 0x16a7 # macro
regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG15_SEM = 0x16a8 # macro
regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG16_SEM = 0x16a9 # macro
regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG17_SEM = 0x16aa # macro
regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG0_REQ = 0x16ab # macro
regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG1_REQ = 0x16ac # macro
regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG2_REQ = 0x16ad # macro
regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG3_REQ = 0x16ae # macro
regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG4_REQ = 0x16af # macro
regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG5_REQ = 0x16b0 # macro
regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG6_REQ = 0x16b1 # macro
regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG7_REQ = 0x16b2 # macro
regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG8_REQ = 0x16b3 # macro
regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG9_REQ = 0x16b4 # macro
regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG10_REQ = 0x16b5 # macro
regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG11_REQ = 0x16b6 # macro
regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG12_REQ = 0x16b7 # macro
regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG13_REQ = 0x16b8 # macro
regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG14_REQ = 0x16b9 # macro
regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG15_REQ = 0x16ba # macro
regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG16_REQ = 0x16bb # macro
regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG17_REQ = 0x16bc # macro
regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG0_ACK = 0x16bd # macro
regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG1_ACK = 0x16be # macro
regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG2_ACK = 0x16bf # macro
regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG3_ACK = 0x16c0 # macro
regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG4_ACK = 0x16c1 # macro
regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG5_ACK = 0x16c2 # macro
regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG6_ACK = 0x16c3 # macro
regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG7_ACK = 0x16c4 # macro
regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG8_ACK = 0x16c5 # macro
regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG9_ACK = 0x16c6 # macro
regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG10_ACK = 0x16c7 # macro
regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG11_ACK = 0x16c8 # macro
regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG12_ACK = 0x16c9 # macro
regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG13_ACK = 0x16ca # macro
regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG14_ACK = 0x16cb # macro
regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG15_ACK = 0x16cc # macro
regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG16_ACK = 0x16cd # macro
regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG17_ACK = 0x16ce # macro
regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 = 0x16cf # macro
regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 = 0x16d0 # macro
regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 = 0x16d1 # macro
regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 = 0x16d2 # macro
regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 = 0x16d3 # macro
regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 = 0x16d4 # macro
regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 = 0x16d5 # macro
regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 = 0x16d6 # macro
regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 = 0x16d7 # macro
regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 = 0x16d8 # macro
regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 = 0x16d9 # macro
regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 = 0x16da # macro
regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 = 0x16db # macro
regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 = 0x16dc # macro
regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 = 0x16dd # macro
regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 = 0x16de # macro
regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 = 0x16df # macro
regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 = 0x16e0 # macro
regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 = 0x16e1 # macro
regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 = 0x16e2 # macro
regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 = 0x16e3 # macro
regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 = 0x16e4 # macro
regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 = 0x16e5 # macro
regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 = 0x16e6 # macro
regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 = 0x16e7 # macro
regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 = 0x16e8 # macro
regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 = 0x16e9 # macro
regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 = 0x16ea # macro
regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 = 0x16eb # macro
regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 = 0x16ec # macro
regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 = 0x16ed # macro
regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 = 0x16ee # macro
regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 = 0x16ef # macro
regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 = 0x16f0 # macro
regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 = 0x16f1 # macro
regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 = 0x16f2 # macro
regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f3 # macro
regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f4 # macro
regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f5 # macro
regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f6 # macro
regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f7 # macro
regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f8 # macro
regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f9 # macro
regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fa # macro
regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 = 0x16fb # macro
regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fc # macro
regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 = 0x16fd # macro
regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fe # macro
regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 = 0x16ff # macro
regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 = 0x1700 # macro
regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 = 0x1701 # macro
regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 = 0x1702 # macro
regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 = 0x1703 # macro
regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 = 0x1704 # macro
regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 = 0x1705 # macro
regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 = 0x1706 # macro
regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 = 0x1707 # macro
regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 = 0x1708 # macro
regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 = 0x1709 # macro
regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 = 0x170a # macro
regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 = 0x170b # macro
regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 = 0x170c # macro
regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 = 0x170d # macro
regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 = 0x170e # macro
regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 = 0x170f # macro
regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 = 0x1710 # macro
regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 = 0x1711 # macro
regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 = 0x1712 # macro
regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 = 0x1713 # macro
regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 = 0x1714 # macro
regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 = 0x1715 # macro
regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 = 0x1716 # macro
regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 = 0x1717 # macro
regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 = 0x1718 # macro
regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 = 0x1719 # macro
regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 = 0x171a # macro
regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 = 0x171b # macro
regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 = 0x171c # macro
regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 = 0x171d # macro
regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 = 0x171e # macro
regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 = 0x171f # macro
regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 = 0x1720 # macro
regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 = 0x1721 # macro
regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 = 0x1722 # macro
regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 = 0x1723 # macro
regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 = 0x1724 # macro
regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 = 0x1725 # macro
regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 = 0x1726 # macro
regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 = 0x1727 # macro
regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 = 0x1728 # macro
regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 = 0x1729 # macro
regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 = 0x172a # macro
regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 = 0x172b # macro
regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 = 0x172c # macro
regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 = 0x172d # macro
regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 = 0x172e # macro
regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 = 0x172f # macro
regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 = 0x1730 # macro
regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 = 0x1731 # macro
regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 = 0x1732 # macro
regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 = 0x1733 # macro
regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 = 0x1734 # macro
regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 = 0x1735 # macro
regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 = 0x1736 # macro
regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 = 0x1737 # macro
regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 = 0x1738 # macro
regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 = 0x1739 # macro
regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 = 0x173a # macro
regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 = 0x173b # macro
regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 = 0x173c # macro
regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 = 0x173d # macro
regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 = 0x173e # macro
regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 = 0x173f # macro
regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 = 0x1740 # macro
regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 = 0x1741 # macro
regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 = 0x1742 # macro
regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 = 0x1743 # macro
regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 = 0x1744 # macro
regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 = 0x1745 # macro
regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 = 0x1746 # macro
regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 = 0x1747 # macro
regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 = 0x1748 # macro
regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 = 0x1749 # macro
regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 = 0x174a # macro
regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 = 0x174b # macro
regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 = 0x174c # macro
regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 = 0x174d # macro
regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 = 0x174e # macro
regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 = 0x174f # macro
regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 = 0x1750 # macro
regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 = 0x1751 # macro
regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 = 0x1752 # macro
regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1753 # macro
regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1754 # macro
regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1755 # macro
regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1756 # macro
regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1757 # macro
regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1758 # macro
regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1759 # macro
regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175a # macro
regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175b # macro
regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175c # macro
regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175d # macro
regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175e # macro
regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175f # macro
regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1760 # macro
regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1761 # macro
regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1762 # macro
regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1763 # macro
regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
regGCVML2_PERFCOUNTER2_0_LO = 0x34e0 # macro
regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX = 1 # macro
regGCVML2_PERFCOUNTER2_1_LO = 0x34e1 # macro
regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX = 1 # macro
regGCVML2_PERFCOUNTER2_0_HI = 0x34e2 # macro
regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX = 1 # macro
regGCVML2_PERFCOUNTER2_1_HI = 0x34e3 # macro
regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX = 1 # macro
regGCMC_VM_L2_PERFCOUNTER_LO = 0x34e4 # macro
regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX = 1 # macro
regGCMC_VM_L2_PERFCOUNTER_HI = 0x34e5 # macro
regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX = 1 # macro
regGCUTCL2_PERFCOUNTER_LO = 0x34e6 # macro
regGCUTCL2_PERFCOUNTER_LO_BASE_IDX = 1 # macro
regGCUTCL2_PERFCOUNTER_HI = 0x34e7 # macro
regGCUTCL2_PERFCOUNTER_HI_BASE_IDX = 1 # macro
regGCVML2_PERFCOUNTER2_0_SELECT = 0x3d20 # macro
regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX = 1 # macro
regGCVML2_PERFCOUNTER2_1_SELECT = 0x3d21 # macro
regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX = 1 # macro
regGCVML2_PERFCOUNTER2_0_SELECT1 = 0x3d22 # macro
regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX = 1 # macro
regGCVML2_PERFCOUNTER2_1_SELECT1 = 0x3d23 # macro
regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX = 1 # macro
regGCVML2_PERFCOUNTER2_0_MODE = 0x3d24 # macro
regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX = 1 # macro
regGCVML2_PERFCOUNTER2_1_MODE = 0x3d25 # macro
regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX = 1 # macro
regGCMC_VM_L2_PERFCOUNTER0_CFG = 0x3d30 # macro
regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
regGCMC_VM_L2_PERFCOUNTER1_CFG = 0x3d31 # macro
regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
regGCMC_VM_L2_PERFCOUNTER2_CFG = 0x3d32 # macro
regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro
regGCMC_VM_L2_PERFCOUNTER3_CFG = 0x3d33 # macro
regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro
regGCMC_VM_L2_PERFCOUNTER4_CFG = 0x3d34 # macro
regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX = 1 # macro
regGCMC_VM_L2_PERFCOUNTER5_CFG = 0x3d35 # macro
regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX = 1 # macro
regGCMC_VM_L2_PERFCOUNTER6_CFG = 0x3d36 # macro
regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX = 1 # macro
regGCMC_VM_L2_PERFCOUNTER7_CFG = 0x3d37 # macro
regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX = 1 # macro
regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL = 0x3d38 # macro
regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
regGCUTCL2_PERFCOUNTER0_CFG = 0x3d39 # macro
regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
regGCUTCL2_PERFCOUNTER1_CFG = 0x3d3a # macro
regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
regGCUTCL2_PERFCOUNTER2_CFG = 0x3d3b # macro
regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro
regGCUTCL2_PERFCOUNTER3_CFG = 0x3d3c # macro
regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro
regGCUTCL2_PERFCOUNTER_RSLT_CNTL = 0x3d3d # macro
regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF0 = 0x5a80 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF1 = 0x5a81 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF2 = 0x5a82 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF3 = 0x5a83 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF4 = 0x5a84 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF5 = 0x5a85 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF6 = 0x5a86 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF7 = 0x5a87 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF8 = 0x5a88 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF9 = 0x5a89 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF10 = 0x5a8a # macro
regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF11 = 0x5a8b # macro
regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF12 = 0x5a8c # macro
regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF13 = 0x5a8d # macro
regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF14 = 0x5a8e # macro
regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX = 1 # macro
regGCMC_VM_FB_SIZE_OFFSET_VF15 = 0x5a8f # macro
regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX = 1 # macro
regGCUTCL2_TRANSLATION_BYPASS_BY_VMID = 0x5e41 # macro
regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX = 1 # macro
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL = 0x5e44 # macro
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_0 = 0x5e48 # macro
regGCMC_VM_MARC_BASE_LO_0_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_1 = 0x5e49 # macro
regGCMC_VM_MARC_BASE_LO_1_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_2 = 0x5e4a # macro
regGCMC_VM_MARC_BASE_LO_2_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_3 = 0x5e4b # macro
regGCMC_VM_MARC_BASE_LO_3_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_4 = 0x5e4c # macro
regGCMC_VM_MARC_BASE_LO_4_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_5 = 0x5e4d # macro
regGCMC_VM_MARC_BASE_LO_5_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_6 = 0x5e4e # macro
regGCMC_VM_MARC_BASE_LO_6_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_7 = 0x5e4f # macro
regGCMC_VM_MARC_BASE_LO_7_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_8 = 0x5e50 # macro
regGCMC_VM_MARC_BASE_LO_8_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_9 = 0x5e51 # macro
regGCMC_VM_MARC_BASE_LO_9_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_10 = 0x5e52 # macro
regGCMC_VM_MARC_BASE_LO_10_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_11 = 0x5e53 # macro
regGCMC_VM_MARC_BASE_LO_11_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_12 = 0x5e54 # macro
regGCMC_VM_MARC_BASE_LO_12_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_13 = 0x5e55 # macro
regGCMC_VM_MARC_BASE_LO_13_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_14 = 0x5e56 # macro
regGCMC_VM_MARC_BASE_LO_14_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_LO_15 = 0x5e57 # macro
regGCMC_VM_MARC_BASE_LO_15_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_0 = 0x5e58 # macro
regGCMC_VM_MARC_BASE_HI_0_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_1 = 0x5e59 # macro
regGCMC_VM_MARC_BASE_HI_1_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_2 = 0x5e5a # macro
regGCMC_VM_MARC_BASE_HI_2_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_3 = 0x5e5b # macro
regGCMC_VM_MARC_BASE_HI_3_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_4 = 0x5e5c # macro
regGCMC_VM_MARC_BASE_HI_4_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_5 = 0x5e5d # macro
regGCMC_VM_MARC_BASE_HI_5_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_6 = 0x5e5e # macro
regGCMC_VM_MARC_BASE_HI_6_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_7 = 0x5e5f # macro
regGCMC_VM_MARC_BASE_HI_7_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_8 = 0x5e60 # macro
regGCMC_VM_MARC_BASE_HI_8_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_9 = 0x5e61 # macro
regGCMC_VM_MARC_BASE_HI_9_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_10 = 0x5e62 # macro
regGCMC_VM_MARC_BASE_HI_10_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_11 = 0x5e63 # macro
regGCMC_VM_MARC_BASE_HI_11_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_12 = 0x5e64 # macro
regGCMC_VM_MARC_BASE_HI_12_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_13 = 0x5e65 # macro
regGCMC_VM_MARC_BASE_HI_13_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_14 = 0x5e66 # macro
regGCMC_VM_MARC_BASE_HI_14_BASE_IDX = 1 # macro
regGCMC_VM_MARC_BASE_HI_15 = 0x5e67 # macro
regGCMC_VM_MARC_BASE_HI_15_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_0 = 0x5e68 # macro
regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_1 = 0x5e69 # macro
regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_2 = 0x5e6a # macro
regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_3 = 0x5e6b # macro
regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_4 = 0x5e6c # macro
regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_5 = 0x5e6d # macro
regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_6 = 0x5e6e # macro
regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_7 = 0x5e6f # macro
regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_8 = 0x5e70 # macro
regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_9 = 0x5e71 # macro
regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_10 = 0x5e72 # macro
regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_11 = 0x5e73 # macro
regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_12 = 0x5e74 # macro
regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_13 = 0x5e75 # macro
regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_14 = 0x5e76 # macro
regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_LO_15 = 0x5e77 # macro
regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_0 = 0x5e78 # macro
regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_1 = 0x5e79 # macro
regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_2 = 0x5e7a # macro
regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_3 = 0x5e7b # macro
regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_4 = 0x5e7c # macro
regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_5 = 0x5e7d # macro
regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_6 = 0x5e7e # macro
regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_7 = 0x5e7f # macro
regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_8 = 0x5e80 # macro
regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_9 = 0x5e81 # macro
regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_10 = 0x5e82 # macro
regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_11 = 0x5e83 # macro
regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_12 = 0x5e84 # macro
regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_13 = 0x5e85 # macro
regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_14 = 0x5e86 # macro
regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX = 1 # macro
regGCMC_VM_MARC_RELOC_HI_15 = 0x5e87 # macro
regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_0 = 0x5e88 # macro
regGCMC_VM_MARC_LEN_LO_0_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_1 = 0x5e89 # macro
regGCMC_VM_MARC_LEN_LO_1_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_2 = 0x5e8a # macro
regGCMC_VM_MARC_LEN_LO_2_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_3 = 0x5e8b # macro
regGCMC_VM_MARC_LEN_LO_3_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_4 = 0x5e8c # macro
regGCMC_VM_MARC_LEN_LO_4_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_5 = 0x5e8d # macro
regGCMC_VM_MARC_LEN_LO_5_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_6 = 0x5e8e # macro
regGCMC_VM_MARC_LEN_LO_6_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_7 = 0x5e8f # macro
regGCMC_VM_MARC_LEN_LO_7_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_8 = 0x5e90 # macro
regGCMC_VM_MARC_LEN_LO_8_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_9 = 0x5e91 # macro
regGCMC_VM_MARC_LEN_LO_9_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_10 = 0x5e92 # macro
regGCMC_VM_MARC_LEN_LO_10_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_11 = 0x5e93 # macro
regGCMC_VM_MARC_LEN_LO_11_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_12 = 0x5e94 # macro
regGCMC_VM_MARC_LEN_LO_12_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_13 = 0x5e95 # macro
regGCMC_VM_MARC_LEN_LO_13_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_14 = 0x5e96 # macro
regGCMC_VM_MARC_LEN_LO_14_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_LO_15 = 0x5e97 # macro
regGCMC_VM_MARC_LEN_LO_15_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_0 = 0x5e98 # macro
regGCMC_VM_MARC_LEN_HI_0_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_1 = 0x5e99 # macro
regGCMC_VM_MARC_LEN_HI_1_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_2 = 0x5e9a # macro
regGCMC_VM_MARC_LEN_HI_2_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_3 = 0x5e9b # macro
regGCMC_VM_MARC_LEN_HI_3_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_4 = 0x5e9c # macro
regGCMC_VM_MARC_LEN_HI_4_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_5 = 0x5e9d # macro
regGCMC_VM_MARC_LEN_HI_5_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_6 = 0x5e9e # macro
regGCMC_VM_MARC_LEN_HI_6_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_7 = 0x5e9f # macro
regGCMC_VM_MARC_LEN_HI_7_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_8 = 0x5ea0 # macro
regGCMC_VM_MARC_LEN_HI_8_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_9 = 0x5ea1 # macro
regGCMC_VM_MARC_LEN_HI_9_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_10 = 0x5ea2 # macro
regGCMC_VM_MARC_LEN_HI_10_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_11 = 0x5ea3 # macro
regGCMC_VM_MARC_LEN_HI_11_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_12 = 0x5ea4 # macro
regGCMC_VM_MARC_LEN_HI_12_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_13 = 0x5ea5 # macro
regGCMC_VM_MARC_LEN_HI_13_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_14 = 0x5ea6 # macro
regGCMC_VM_MARC_LEN_HI_14_BASE_IDX = 1 # macro
regGCMC_VM_MARC_LEN_HI_15 = 0x5ea7 # macro
regGCMC_VM_MARC_LEN_HI_15_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_0 = 0x5ea8 # macro
regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_1 = 0x5ea9 # macro
regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_2 = 0x5eaa # macro
regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_3 = 0x5eab # macro
regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_4 = 0x5eac # macro
regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_5 = 0x5ead # macro
regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_6 = 0x5eae # macro
regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_7 = 0x5eaf # macro
regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_8 = 0x5eb0 # macro
regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_9 = 0x5eb1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_10 = 0x5eb2 # macro
regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_11 = 0x5eb3 # macro
regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_12 = 0x5eb4 # macro
regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_13 = 0x5eb5 # macro
regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_14 = 0x5eb6 # macro
regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX = 1 # macro
regGCMC_VM_MARC_PFVF_MAPPING_15 = 0x5eb7 # macro
regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX = 1 # macro
regGCUTC_TRANSLATION_FAULT_CNTL0 = 0x5eb8 # macro
regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX = 1 # macro
regGCUTC_TRANSLATION_FAULT_CNTL1 = 0x5eb9 # macro
regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX = 1 # macro
regSPI_SHADER_PGM_RSRC4_PS = 0x19a1 # macro
regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_CHKSUM_PS = 0x19a6 # macro
regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_RSRC3_PS = 0x19a7 # macro
regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_LO_PS = 0x19a8 # macro
regSPI_SHADER_PGM_LO_PS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_HI_PS = 0x19a9 # macro
regSPI_SHADER_PGM_HI_PS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_RSRC1_PS = 0x19aa # macro
regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_RSRC2_PS = 0x19ab # macro
regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_0 = 0x19ac # macro
regSPI_SHADER_USER_DATA_PS_0_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_1 = 0x19ad # macro
regSPI_SHADER_USER_DATA_PS_1_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_2 = 0x19ae # macro
regSPI_SHADER_USER_DATA_PS_2_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_3 = 0x19af # macro
regSPI_SHADER_USER_DATA_PS_3_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_4 = 0x19b0 # macro
regSPI_SHADER_USER_DATA_PS_4_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_5 = 0x19b1 # macro
regSPI_SHADER_USER_DATA_PS_5_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_6 = 0x19b2 # macro
regSPI_SHADER_USER_DATA_PS_6_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_7 = 0x19b3 # macro
regSPI_SHADER_USER_DATA_PS_7_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_8 = 0x19b4 # macro
regSPI_SHADER_USER_DATA_PS_8_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_9 = 0x19b5 # macro
regSPI_SHADER_USER_DATA_PS_9_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_10 = 0x19b6 # macro
regSPI_SHADER_USER_DATA_PS_10_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_11 = 0x19b7 # macro
regSPI_SHADER_USER_DATA_PS_11_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_12 = 0x19b8 # macro
regSPI_SHADER_USER_DATA_PS_12_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_13 = 0x19b9 # macro
regSPI_SHADER_USER_DATA_PS_13_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_14 = 0x19ba # macro
regSPI_SHADER_USER_DATA_PS_14_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_15 = 0x19bb # macro
regSPI_SHADER_USER_DATA_PS_15_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_16 = 0x19bc # macro
regSPI_SHADER_USER_DATA_PS_16_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_17 = 0x19bd # macro
regSPI_SHADER_USER_DATA_PS_17_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_18 = 0x19be # macro
regSPI_SHADER_USER_DATA_PS_18_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_19 = 0x19bf # macro
regSPI_SHADER_USER_DATA_PS_19_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_20 = 0x19c0 # macro
regSPI_SHADER_USER_DATA_PS_20_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_21 = 0x19c1 # macro
regSPI_SHADER_USER_DATA_PS_21_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_22 = 0x19c2 # macro
regSPI_SHADER_USER_DATA_PS_22_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_23 = 0x19c3 # macro
regSPI_SHADER_USER_DATA_PS_23_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_24 = 0x19c4 # macro
regSPI_SHADER_USER_DATA_PS_24_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_25 = 0x19c5 # macro
regSPI_SHADER_USER_DATA_PS_25_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_26 = 0x19c6 # macro
regSPI_SHADER_USER_DATA_PS_26_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_27 = 0x19c7 # macro
regSPI_SHADER_USER_DATA_PS_27_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_28 = 0x19c8 # macro
regSPI_SHADER_USER_DATA_PS_28_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_29 = 0x19c9 # macro
regSPI_SHADER_USER_DATA_PS_29_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_30 = 0x19ca # macro
regSPI_SHADER_USER_DATA_PS_30_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_PS_31 = 0x19cb # macro
regSPI_SHADER_USER_DATA_PS_31_BASE_IDX = 0 # macro
regSPI_SHADER_REQ_CTRL_PS = 0x19d0 # macro
regSPI_SHADER_REQ_CTRL_PS_BASE_IDX = 0 # macro
regSPI_SHADER_USER_ACCUM_PS_0 = 0x19d2 # macro
regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX = 0 # macro
regSPI_SHADER_USER_ACCUM_PS_1 = 0x19d3 # macro
regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX = 0 # macro
regSPI_SHADER_USER_ACCUM_PS_2 = 0x19d4 # macro
regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX = 0 # macro
regSPI_SHADER_USER_ACCUM_PS_3 = 0x19d5 # macro
regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_CHKSUM_GS = 0x1a20 # macro
regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_RSRC4_GS = 0x1a21 # macro
regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_ADDR_LO_GS = 0x1a22 # macro
regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_ADDR_HI_GS = 0x1a23 # macro
regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_LO_ES_GS = 0x1a24 # macro
regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_HI_ES_GS = 0x1a25 # macro
regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_RSRC3_GS = 0x1a27 # macro
regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_LO_GS = 0x1a28 # macro
regSPI_SHADER_PGM_LO_GS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_HI_GS = 0x1a29 # macro
regSPI_SHADER_PGM_HI_GS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_RSRC1_GS = 0x1a2a # macro
regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_RSRC2_GS = 0x1a2b # macro
regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_0 = 0x1a2c # macro
regSPI_SHADER_USER_DATA_GS_0_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_1 = 0x1a2d # macro
regSPI_SHADER_USER_DATA_GS_1_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_2 = 0x1a2e # macro
regSPI_SHADER_USER_DATA_GS_2_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_3 = 0x1a2f # macro
regSPI_SHADER_USER_DATA_GS_3_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_4 = 0x1a30 # macro
regSPI_SHADER_USER_DATA_GS_4_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_5 = 0x1a31 # macro
regSPI_SHADER_USER_DATA_GS_5_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_6 = 0x1a32 # macro
regSPI_SHADER_USER_DATA_GS_6_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_7 = 0x1a33 # macro
regSPI_SHADER_USER_DATA_GS_7_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_8 = 0x1a34 # macro
regSPI_SHADER_USER_DATA_GS_8_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_9 = 0x1a35 # macro
regSPI_SHADER_USER_DATA_GS_9_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_10 = 0x1a36 # macro
regSPI_SHADER_USER_DATA_GS_10_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_11 = 0x1a37 # macro
regSPI_SHADER_USER_DATA_GS_11_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_12 = 0x1a38 # macro
regSPI_SHADER_USER_DATA_GS_12_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_13 = 0x1a39 # macro
regSPI_SHADER_USER_DATA_GS_13_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_14 = 0x1a3a # macro
regSPI_SHADER_USER_DATA_GS_14_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_15 = 0x1a3b # macro
regSPI_SHADER_USER_DATA_GS_15_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_16 = 0x1a3c # macro
regSPI_SHADER_USER_DATA_GS_16_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_17 = 0x1a3d # macro
regSPI_SHADER_USER_DATA_GS_17_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_18 = 0x1a3e # macro
regSPI_SHADER_USER_DATA_GS_18_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_19 = 0x1a3f # macro
regSPI_SHADER_USER_DATA_GS_19_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_20 = 0x1a40 # macro
regSPI_SHADER_USER_DATA_GS_20_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_21 = 0x1a41 # macro
regSPI_SHADER_USER_DATA_GS_21_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_22 = 0x1a42 # macro
regSPI_SHADER_USER_DATA_GS_22_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_23 = 0x1a43 # macro
regSPI_SHADER_USER_DATA_GS_23_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_24 = 0x1a44 # macro
regSPI_SHADER_USER_DATA_GS_24_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_25 = 0x1a45 # macro
regSPI_SHADER_USER_DATA_GS_25_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_26 = 0x1a46 # macro
regSPI_SHADER_USER_DATA_GS_26_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_27 = 0x1a47 # macro
regSPI_SHADER_USER_DATA_GS_27_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_28 = 0x1a48 # macro
regSPI_SHADER_USER_DATA_GS_28_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_29 = 0x1a49 # macro
regSPI_SHADER_USER_DATA_GS_29_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_30 = 0x1a4a # macro
regSPI_SHADER_USER_DATA_GS_30_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_GS_31 = 0x1a4b # macro
regSPI_SHADER_USER_DATA_GS_31_BASE_IDX = 0 # macro
regSPI_SHADER_GS_MESHLET_DIM = 0x1a4c # macro
regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX = 0 # macro
regSPI_SHADER_GS_MESHLET_EXP_ALLOC = 0x1a4d # macro
regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX = 0 # macro
regSPI_SHADER_REQ_CTRL_ESGS = 0x1a50 # macro
regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX = 0 # macro
regSPI_SHADER_USER_ACCUM_ESGS_0 = 0x1a52 # macro
regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX = 0 # macro
regSPI_SHADER_USER_ACCUM_ESGS_1 = 0x1a53 # macro
regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX = 0 # macro
regSPI_SHADER_USER_ACCUM_ESGS_2 = 0x1a54 # macro
regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX = 0 # macro
regSPI_SHADER_USER_ACCUM_ESGS_3 = 0x1a55 # macro
regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_LO_ES = 0x1a68 # macro
regSPI_SHADER_PGM_LO_ES_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_HI_ES = 0x1a69 # macro
regSPI_SHADER_PGM_HI_ES_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_CHKSUM_HS = 0x1aa0 # macro
regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_RSRC4_HS = 0x1aa1 # macro
regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_ADDR_LO_HS = 0x1aa2 # macro
regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_ADDR_HI_HS = 0x1aa3 # macro
regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_LO_LS_HS = 0x1aa4 # macro
regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_HI_LS_HS = 0x1aa5 # macro
regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_RSRC3_HS = 0x1aa7 # macro
regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_LO_HS = 0x1aa8 # macro
regSPI_SHADER_PGM_LO_HS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_HI_HS = 0x1aa9 # macro
regSPI_SHADER_PGM_HI_HS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_RSRC1_HS = 0x1aaa # macro
regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_RSRC2_HS = 0x1aab # macro
regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_0 = 0x1aac # macro
regSPI_SHADER_USER_DATA_HS_0_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_1 = 0x1aad # macro
regSPI_SHADER_USER_DATA_HS_1_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_2 = 0x1aae # macro
regSPI_SHADER_USER_DATA_HS_2_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_3 = 0x1aaf # macro
regSPI_SHADER_USER_DATA_HS_3_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_4 = 0x1ab0 # macro
regSPI_SHADER_USER_DATA_HS_4_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_5 = 0x1ab1 # macro
regSPI_SHADER_USER_DATA_HS_5_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_6 = 0x1ab2 # macro
regSPI_SHADER_USER_DATA_HS_6_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_7 = 0x1ab3 # macro
regSPI_SHADER_USER_DATA_HS_7_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_8 = 0x1ab4 # macro
regSPI_SHADER_USER_DATA_HS_8_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_9 = 0x1ab5 # macro
regSPI_SHADER_USER_DATA_HS_9_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_10 = 0x1ab6 # macro
regSPI_SHADER_USER_DATA_HS_10_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_11 = 0x1ab7 # macro
regSPI_SHADER_USER_DATA_HS_11_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_12 = 0x1ab8 # macro
regSPI_SHADER_USER_DATA_HS_12_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_13 = 0x1ab9 # macro
regSPI_SHADER_USER_DATA_HS_13_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_14 = 0x1aba # macro
regSPI_SHADER_USER_DATA_HS_14_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_15 = 0x1abb # macro
regSPI_SHADER_USER_DATA_HS_15_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_16 = 0x1abc # macro
regSPI_SHADER_USER_DATA_HS_16_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_17 = 0x1abd # macro
regSPI_SHADER_USER_DATA_HS_17_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_18 = 0x1abe # macro
regSPI_SHADER_USER_DATA_HS_18_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_19 = 0x1abf # macro
regSPI_SHADER_USER_DATA_HS_19_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_20 = 0x1ac0 # macro
regSPI_SHADER_USER_DATA_HS_20_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_21 = 0x1ac1 # macro
regSPI_SHADER_USER_DATA_HS_21_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_22 = 0x1ac2 # macro
regSPI_SHADER_USER_DATA_HS_22_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_23 = 0x1ac3 # macro
regSPI_SHADER_USER_DATA_HS_23_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_24 = 0x1ac4 # macro
regSPI_SHADER_USER_DATA_HS_24_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_25 = 0x1ac5 # macro
regSPI_SHADER_USER_DATA_HS_25_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_26 = 0x1ac6 # macro
regSPI_SHADER_USER_DATA_HS_26_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_27 = 0x1ac7 # macro
regSPI_SHADER_USER_DATA_HS_27_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_28 = 0x1ac8 # macro
regSPI_SHADER_USER_DATA_HS_28_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_29 = 0x1ac9 # macro
regSPI_SHADER_USER_DATA_HS_29_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_30 = 0x1aca # macro
regSPI_SHADER_USER_DATA_HS_30_BASE_IDX = 0 # macro
regSPI_SHADER_USER_DATA_HS_31 = 0x1acb # macro
regSPI_SHADER_USER_DATA_HS_31_BASE_IDX = 0 # macro
regSPI_SHADER_REQ_CTRL_LSHS = 0x1ad0 # macro
regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX = 0 # macro
regSPI_SHADER_USER_ACCUM_LSHS_0 = 0x1ad2 # macro
regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX = 0 # macro
regSPI_SHADER_USER_ACCUM_LSHS_1 = 0x1ad3 # macro
regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX = 0 # macro
regSPI_SHADER_USER_ACCUM_LSHS_2 = 0x1ad4 # macro
regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX = 0 # macro
regSPI_SHADER_USER_ACCUM_LSHS_3 = 0x1ad5 # macro
regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_LO_LS = 0x1ae8 # macro
regSPI_SHADER_PGM_LO_LS_BASE_IDX = 0 # macro
regSPI_SHADER_PGM_HI_LS = 0x1ae9 # macro
regSPI_SHADER_PGM_HI_LS_BASE_IDX = 0 # macro
regCOMPUTE_DISPATCH_INITIATOR = 0x1ba0 # macro
regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX = 0 # macro
regCOMPUTE_DIM_X = 0x1ba1 # macro
regCOMPUTE_DIM_X_BASE_IDX = 0 # macro
regCOMPUTE_DIM_Y = 0x1ba2 # macro
regCOMPUTE_DIM_Y_BASE_IDX = 0 # macro
regCOMPUTE_DIM_Z = 0x1ba3 # macro
regCOMPUTE_DIM_Z_BASE_IDX = 0 # macro
regCOMPUTE_START_X = 0x1ba4 # macro
regCOMPUTE_START_X_BASE_IDX = 0 # macro
regCOMPUTE_START_Y = 0x1ba5 # macro
regCOMPUTE_START_Y_BASE_IDX = 0 # macro
regCOMPUTE_START_Z = 0x1ba6 # macro
regCOMPUTE_START_Z_BASE_IDX = 0 # macro
regCOMPUTE_NUM_THREAD_X = 0x1ba7 # macro
regCOMPUTE_NUM_THREAD_X_BASE_IDX = 0 # macro
regCOMPUTE_NUM_THREAD_Y = 0x1ba8 # macro
regCOMPUTE_NUM_THREAD_Y_BASE_IDX = 0 # macro
regCOMPUTE_NUM_THREAD_Z = 0x1ba9 # macro
regCOMPUTE_NUM_THREAD_Z_BASE_IDX = 0 # macro
regCOMPUTE_PIPELINESTAT_ENABLE = 0x1baa # macro
regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX = 0 # macro
regCOMPUTE_PERFCOUNT_ENABLE = 0x1bab # macro
regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX = 0 # macro
regCOMPUTE_PGM_LO = 0x1bac # macro
regCOMPUTE_PGM_LO_BASE_IDX = 0 # macro
regCOMPUTE_PGM_HI = 0x1bad # macro
regCOMPUTE_PGM_HI_BASE_IDX = 0 # macro
regCOMPUTE_DISPATCH_PKT_ADDR_LO = 0x1bae # macro
regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX = 0 # macro
regCOMPUTE_DISPATCH_PKT_ADDR_HI = 0x1baf # macro
regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX = 0 # macro
regCOMPUTE_DISPATCH_SCRATCH_BASE_LO = 0x1bb0 # macro
regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX = 0 # macro
regCOMPUTE_DISPATCH_SCRATCH_BASE_HI = 0x1bb1 # macro
regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX = 0 # macro
regCOMPUTE_PGM_RSRC1 = 0x1bb2 # macro
regCOMPUTE_PGM_RSRC1_BASE_IDX = 0 # macro
regCOMPUTE_PGM_RSRC2 = 0x1bb3 # macro
regCOMPUTE_PGM_RSRC2_BASE_IDX = 0 # macro
regCOMPUTE_VMID = 0x1bb4 # macro
regCOMPUTE_VMID_BASE_IDX = 0 # macro
regCOMPUTE_RESOURCE_LIMITS = 0x1bb5 # macro
regCOMPUTE_RESOURCE_LIMITS_BASE_IDX = 0 # macro
regCOMPUTE_DESTINATION_EN_SE0 = 0x1bb6 # macro
regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX = 0 # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE0 = 0x1bb6 # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX = 0 # macro
regCOMPUTE_DESTINATION_EN_SE1 = 0x1bb7 # macro
regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX = 0 # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE1 = 0x1bb7 # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX = 0 # macro
regCOMPUTE_TMPRING_SIZE = 0x1bb8 # macro
regCOMPUTE_TMPRING_SIZE_BASE_IDX = 0 # macro
regCOMPUTE_DESTINATION_EN_SE2 = 0x1bb9 # macro
regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX = 0 # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE2 = 0x1bb9 # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX = 0 # macro
regCOMPUTE_DESTINATION_EN_SE3 = 0x1bba # macro
regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX = 0 # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE3 = 0x1bba # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX = 0 # macro
regCOMPUTE_RESTART_X = 0x1bbb # macro
regCOMPUTE_RESTART_X_BASE_IDX = 0 # macro
regCOMPUTE_RESTART_Y = 0x1bbc # macro
regCOMPUTE_RESTART_Y_BASE_IDX = 0 # macro
regCOMPUTE_RESTART_Z = 0x1bbd # macro
regCOMPUTE_RESTART_Z_BASE_IDX = 0 # macro
regCOMPUTE_THREAD_TRACE_ENABLE = 0x1bbe # macro
regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX = 0 # macro
regCOMPUTE_MISC_RESERVED = 0x1bbf # macro
regCOMPUTE_MISC_RESERVED_BASE_IDX = 0 # macro
regCOMPUTE_DISPATCH_ID = 0x1bc0 # macro
regCOMPUTE_DISPATCH_ID_BASE_IDX = 0 # macro
regCOMPUTE_THREADGROUP_ID = 0x1bc1 # macro
regCOMPUTE_THREADGROUP_ID_BASE_IDX = 0 # macro
regCOMPUTE_REQ_CTRL = 0x1bc2 # macro
regCOMPUTE_REQ_CTRL_BASE_IDX = 0 # macro
regCOMPUTE_USER_ACCUM_0 = 0x1bc4 # macro
regCOMPUTE_USER_ACCUM_0_BASE_IDX = 0 # macro
regCOMPUTE_USER_ACCUM_1 = 0x1bc5 # macro
regCOMPUTE_USER_ACCUM_1_BASE_IDX = 0 # macro
regCOMPUTE_USER_ACCUM_2 = 0x1bc6 # macro
regCOMPUTE_USER_ACCUM_2_BASE_IDX = 0 # macro
regCOMPUTE_USER_ACCUM_3 = 0x1bc7 # macro
regCOMPUTE_USER_ACCUM_3_BASE_IDX = 0 # macro
regCOMPUTE_PGM_RSRC3 = 0x1bc8 # macro
regCOMPUTE_PGM_RSRC3_BASE_IDX = 0 # macro
regCOMPUTE_DDID_INDEX = 0x1bc9 # macro
regCOMPUTE_DDID_INDEX_BASE_IDX = 0 # macro
regCOMPUTE_SHADER_CHKSUM = 0x1bca # macro
regCOMPUTE_SHADER_CHKSUM_BASE_IDX = 0 # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE4 = 0x1bcb # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX = 0 # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE5 = 0x1bcc # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX = 0 # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE6 = 0x1bcd # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX = 0 # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE7 = 0x1bce # macro
regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX = 0 # macro
regCOMPUTE_DISPATCH_INTERLEAVE = 0x1bcf # macro
regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX = 0 # macro
regCOMPUTE_RELAUNCH = 0x1bd0 # macro
regCOMPUTE_RELAUNCH_BASE_IDX = 0 # macro
regCOMPUTE_WAVE_RESTORE_ADDR_LO = 0x1bd1 # macro
regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX = 0 # macro
regCOMPUTE_WAVE_RESTORE_ADDR_HI = 0x1bd2 # macro
regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX = 0 # macro
regCOMPUTE_RELAUNCH2 = 0x1bd3 # macro
regCOMPUTE_RELAUNCH2_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_0 = 0x1be0 # macro
regCOMPUTE_USER_DATA_0_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_1 = 0x1be1 # macro
regCOMPUTE_USER_DATA_1_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_2 = 0x1be2 # macro
regCOMPUTE_USER_DATA_2_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_3 = 0x1be3 # macro
regCOMPUTE_USER_DATA_3_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_4 = 0x1be4 # macro
regCOMPUTE_USER_DATA_4_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_5 = 0x1be5 # macro
regCOMPUTE_USER_DATA_5_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_6 = 0x1be6 # macro
regCOMPUTE_USER_DATA_6_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_7 = 0x1be7 # macro
regCOMPUTE_USER_DATA_7_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_8 = 0x1be8 # macro
regCOMPUTE_USER_DATA_8_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_9 = 0x1be9 # macro
regCOMPUTE_USER_DATA_9_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_10 = 0x1bea # macro
regCOMPUTE_USER_DATA_10_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_11 = 0x1beb # macro
regCOMPUTE_USER_DATA_11_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_12 = 0x1bec # macro
regCOMPUTE_USER_DATA_12_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_13 = 0x1bed # macro
regCOMPUTE_USER_DATA_13_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_14 = 0x1bee # macro
regCOMPUTE_USER_DATA_14_BASE_IDX = 0 # macro
regCOMPUTE_USER_DATA_15 = 0x1bef # macro
regCOMPUTE_USER_DATA_15_BASE_IDX = 0 # macro
regCOMPUTE_DISPATCH_TUNNEL = 0x1c1d # macro
regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX = 0 # macro
regCOMPUTE_DISPATCH_END = 0x1c1e # macro
regCOMPUTE_DISPATCH_END_BASE_IDX = 0 # macro
regCOMPUTE_NOWHERE = 0x1c1f # macro
regCOMPUTE_NOWHERE_BASE_IDX = 0 # macro
regSH_RESERVED_REG0 = 0x1c20 # macro
regSH_RESERVED_REG0_BASE_IDX = 0 # macro
regSH_RESERVED_REG1 = 0x1c21 # macro
regSH_RESERVED_REG1_BASE_IDX = 0 # macro
regCP_CU_MASK_ADDR_LO = 0x1dd2 # macro
regCP_CU_MASK_ADDR_LO_BASE_IDX = 0 # macro
regCP_CU_MASK_ADDR_HI = 0x1dd3 # macro
regCP_CU_MASK_ADDR_HI_BASE_IDX = 0 # macro
regCP_CU_MASK_CNTL = 0x1dd4 # macro
regCP_CU_MASK_CNTL_BASE_IDX = 0 # macro
regCP_EOPQ_WAIT_TIME = 0x1dd5 # macro
regCP_EOPQ_WAIT_TIME_BASE_IDX = 0 # macro
regCP_CPC_MGCG_SYNC_CNTL = 0x1dd6 # macro
regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX = 0 # macro
regCPC_INT_INFO = 0x1dd7 # macro
regCPC_INT_INFO_BASE_IDX = 0 # macro
regCP_VIRT_STATUS = 0x1dd8 # macro
regCP_VIRT_STATUS_BASE_IDX = 0 # macro
regCPC_INT_ADDR = 0x1dd9 # macro
regCPC_INT_ADDR_BASE_IDX = 0 # macro
regCPC_INT_PASID = 0x1dda # macro
regCPC_INT_PASID_BASE_IDX = 0 # macro
regCP_GFX_ERROR = 0x1ddb # macro
regCP_GFX_ERROR_BASE_IDX = 0 # macro
regCPG_UTCL1_CNTL = 0x1ddc # macro
regCPG_UTCL1_CNTL_BASE_IDX = 0 # macro
regCPC_UTCL1_CNTL = 0x1ddd # macro
regCPC_UTCL1_CNTL_BASE_IDX = 0 # macro
regCPF_UTCL1_CNTL = 0x1dde # macro
regCPF_UTCL1_CNTL_BASE_IDX = 0 # macro
regCP_AQL_SMM_STATUS = 0x1ddf # macro
regCP_AQL_SMM_STATUS_BASE_IDX = 0 # macro
regCP_RB0_BASE = 0x1de0 # macro
regCP_RB0_BASE_BASE_IDX = 0 # macro
regCP_RB_BASE = 0x1de0 # macro
regCP_RB_BASE_BASE_IDX = 0 # macro
regCP_RB0_CNTL = 0x1de1 # macro
regCP_RB0_CNTL_BASE_IDX = 0 # macro
regCP_RB_CNTL = 0x1de1 # macro
regCP_RB_CNTL_BASE_IDX = 0 # macro
regCP_RB_RPTR_WR = 0x1de2 # macro
regCP_RB_RPTR_WR_BASE_IDX = 0 # macro
regCP_RB0_RPTR_ADDR = 0x1de3 # macro
regCP_RB0_RPTR_ADDR_BASE_IDX = 0 # macro
regCP_RB_RPTR_ADDR = 0x1de3 # macro
regCP_RB_RPTR_ADDR_BASE_IDX = 0 # macro
regCP_RB0_RPTR_ADDR_HI = 0x1de4 # macro
regCP_RB0_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regCP_RB_RPTR_ADDR_HI = 0x1de4 # macro
regCP_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regCP_RB0_BUFSZ_MASK = 0x1de5 # macro
regCP_RB0_BUFSZ_MASK_BASE_IDX = 0 # macro
regCP_RB_BUFSZ_MASK = 0x1de5 # macro
regCP_RB_BUFSZ_MASK_BASE_IDX = 0 # macro
regCP_INT_CNTL = 0x1de9 # macro
regCP_INT_CNTL_BASE_IDX = 0 # macro
regCP_INT_STATUS = 0x1dea # macro
regCP_INT_STATUS_BASE_IDX = 0 # macro
regCP_DEVICE_ID = 0x1deb # macro
regCP_DEVICE_ID_BASE_IDX = 0 # macro
regCP_ME0_PIPE_PRIORITY_CNTS = 0x1dec # macro
regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro
regCP_RING_PRIORITY_CNTS = 0x1dec # macro
regCP_RING_PRIORITY_CNTS_BASE_IDX = 0 # macro
regCP_ME0_PIPE0_PRIORITY = 0x1ded # macro
regCP_ME0_PIPE0_PRIORITY_BASE_IDX = 0 # macro
regCP_RING0_PRIORITY = 0x1ded # macro
regCP_RING0_PRIORITY_BASE_IDX = 0 # macro
regCP_ME0_PIPE1_PRIORITY = 0x1dee # macro
regCP_ME0_PIPE1_PRIORITY_BASE_IDX = 0 # macro
regCP_RING1_PRIORITY = 0x1dee # macro
regCP_RING1_PRIORITY_BASE_IDX = 0 # macro
regCP_FATAL_ERROR = 0x1df0 # macro
regCP_FATAL_ERROR_BASE_IDX = 0 # macro
regCP_RB_VMID = 0x1df1 # macro
regCP_RB_VMID_BASE_IDX = 0 # macro
regCP_ME0_PIPE0_VMID = 0x1df2 # macro
regCP_ME0_PIPE0_VMID_BASE_IDX = 0 # macro
regCP_ME0_PIPE1_VMID = 0x1df3 # macro
regCP_ME0_PIPE1_VMID_BASE_IDX = 0 # macro
regCP_RB0_WPTR = 0x1df4 # macro
regCP_RB0_WPTR_BASE_IDX = 0 # macro
regCP_RB_WPTR = 0x1df4 # macro
regCP_RB_WPTR_BASE_IDX = 0 # macro
regCP_RB0_WPTR_HI = 0x1df5 # macro
regCP_RB0_WPTR_HI_BASE_IDX = 0 # macro
regCP_RB_WPTR_HI = 0x1df5 # macro
regCP_RB_WPTR_HI_BASE_IDX = 0 # macro
regCP_RB1_WPTR = 0x1df6 # macro
regCP_RB1_WPTR_BASE_IDX = 0 # macro
regCP_RB1_WPTR_HI = 0x1df7 # macro
regCP_RB1_WPTR_HI_BASE_IDX = 0 # macro
regCP_PROCESS_QUANTUM = 0x1df9 # macro
regCP_PROCESS_QUANTUM_BASE_IDX = 0 # macro
regCP_RB_DOORBELL_RANGE_LOWER = 0x1dfa # macro
regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro
regCP_RB_DOORBELL_RANGE_UPPER = 0x1dfb # macro
regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro
regCP_MEC_DOORBELL_RANGE_LOWER = 0x1dfc # macro
regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro
regCP_MEC_DOORBELL_RANGE_UPPER = 0x1dfd # macro
regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro
regCPG_UTCL1_ERROR = 0x1dfe # macro
regCPG_UTCL1_ERROR_BASE_IDX = 0 # macro
regCPC_UTCL1_ERROR = 0x1dff # macro
regCPC_UTCL1_ERROR_BASE_IDX = 0 # macro
regCP_RB1_BASE = 0x1e00 # macro
regCP_RB1_BASE_BASE_IDX = 0 # macro
regCP_RB1_CNTL = 0x1e01 # macro
regCP_RB1_CNTL_BASE_IDX = 0 # macro
regCP_RB1_RPTR_ADDR = 0x1e02 # macro
regCP_RB1_RPTR_ADDR_BASE_IDX = 0 # macro
regCP_RB1_RPTR_ADDR_HI = 0x1e03 # macro
regCP_RB1_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regCP_RB1_BUFSZ_MASK = 0x1e04 # macro
regCP_RB1_BUFSZ_MASK_BASE_IDX = 0 # macro
regCP_INT_CNTL_RING0 = 0x1e0a # macro
regCP_INT_CNTL_RING0_BASE_IDX = 0 # macro
regCP_INT_CNTL_RING1 = 0x1e0b # macro
regCP_INT_CNTL_RING1_BASE_IDX = 0 # macro
regCP_INT_STATUS_RING0 = 0x1e0d # macro
regCP_INT_STATUS_RING0_BASE_IDX = 0 # macro
regCP_INT_STATUS_RING1 = 0x1e0e # macro
regCP_INT_STATUS_RING1_BASE_IDX = 0 # macro
regCP_ME_F32_INTERRUPT = 0x1e13 # macro
regCP_ME_F32_INTERRUPT_BASE_IDX = 0 # macro
regCP_PFP_F32_INTERRUPT = 0x1e14 # macro
regCP_PFP_F32_INTERRUPT_BASE_IDX = 0 # macro
regCP_MEC1_F32_INTERRUPT = 0x1e16 # macro
regCP_MEC1_F32_INTERRUPT_BASE_IDX = 0 # macro
regCP_MEC2_F32_INTERRUPT = 0x1e17 # macro
regCP_MEC2_F32_INTERRUPT_BASE_IDX = 0 # macro
regCP_PWR_CNTL = 0x1e18 # macro
regCP_PWR_CNTL_BASE_IDX = 0 # macro
regCP_ECC_FIRSTOCCURRENCE = 0x1e1a # macro
regCP_ECC_FIRSTOCCURRENCE_BASE_IDX = 0 # macro
regCP_ECC_FIRSTOCCURRENCE_RING0 = 0x1e1b # macro
regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX = 0 # macro
regCP_ECC_FIRSTOCCURRENCE_RING1 = 0x1e1c # macro
regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX = 0 # macro
regGB_EDC_MODE = 0x1e1e # macro
regGB_EDC_MODE_BASE_IDX = 0 # macro
regCP_DEBUG = 0x1e1f # macro
regCP_DEBUG_BASE_IDX = 0 # macro
regCP_CPC_DEBUG = 0x1e21 # macro
regCP_CPC_DEBUG_BASE_IDX = 0 # macro
regCP_PQ_WPTR_POLL_CNTL = 0x1e23 # macro
regCP_PQ_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
regCP_PQ_WPTR_POLL_CNTL1 = 0x1e24 # macro
regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX = 0 # macro
regCP_ME1_PIPE0_INT_CNTL = 0x1e25 # macro
regCP_ME1_PIPE0_INT_CNTL_BASE_IDX = 0 # macro
regCP_ME1_PIPE1_INT_CNTL = 0x1e26 # macro
regCP_ME1_PIPE1_INT_CNTL_BASE_IDX = 0 # macro
regCP_ME1_PIPE2_INT_CNTL = 0x1e27 # macro
regCP_ME1_PIPE2_INT_CNTL_BASE_IDX = 0 # macro
regCP_ME1_PIPE3_INT_CNTL = 0x1e28 # macro
regCP_ME1_PIPE3_INT_CNTL_BASE_IDX = 0 # macro
regCP_ME2_PIPE0_INT_CNTL = 0x1e29 # macro
regCP_ME2_PIPE0_INT_CNTL_BASE_IDX = 0 # macro
regCP_ME2_PIPE1_INT_CNTL = 0x1e2a # macro
regCP_ME2_PIPE1_INT_CNTL_BASE_IDX = 0 # macro
regCP_ME2_PIPE2_INT_CNTL = 0x1e2b # macro
regCP_ME2_PIPE2_INT_CNTL_BASE_IDX = 0 # macro
regCP_ME2_PIPE3_INT_CNTL = 0x1e2c # macro
regCP_ME2_PIPE3_INT_CNTL_BASE_IDX = 0 # macro
regCP_ME1_PIPE0_INT_STATUS = 0x1e2d # macro
regCP_ME1_PIPE0_INT_STATUS_BASE_IDX = 0 # macro
regCP_ME1_PIPE1_INT_STATUS = 0x1e2e # macro
regCP_ME1_PIPE1_INT_STATUS_BASE_IDX = 0 # macro
regCP_ME1_PIPE2_INT_STATUS = 0x1e2f # macro
regCP_ME1_PIPE2_INT_STATUS_BASE_IDX = 0 # macro
regCP_ME1_PIPE3_INT_STATUS = 0x1e30 # macro
regCP_ME1_PIPE3_INT_STATUS_BASE_IDX = 0 # macro
regCP_ME2_PIPE0_INT_STATUS = 0x1e31 # macro
regCP_ME2_PIPE0_INT_STATUS_BASE_IDX = 0 # macro
regCP_ME2_PIPE1_INT_STATUS = 0x1e32 # macro
regCP_ME2_PIPE1_INT_STATUS_BASE_IDX = 0 # macro
regCP_ME2_PIPE2_INT_STATUS = 0x1e33 # macro
regCP_ME2_PIPE2_INT_STATUS_BASE_IDX = 0 # macro
regCP_ME2_PIPE3_INT_STATUS = 0x1e34 # macro
regCP_ME2_PIPE3_INT_STATUS_BASE_IDX = 0 # macro
regCP_GFX_QUEUE_INDEX = 0x1e37 # macro
regCP_GFX_QUEUE_INDEX_BASE_IDX = 0 # macro
regCC_GC_EDC_CONFIG = 0x1e38 # macro
regCC_GC_EDC_CONFIG_BASE_IDX = 0 # macro
regCP_ME1_PIPE_PRIORITY_CNTS = 0x1e39 # macro
regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro
regCP_ME1_PIPE0_PRIORITY = 0x1e3a # macro
regCP_ME1_PIPE0_PRIORITY_BASE_IDX = 0 # macro
regCP_ME1_PIPE1_PRIORITY = 0x1e3b # macro
regCP_ME1_PIPE1_PRIORITY_BASE_IDX = 0 # macro
regCP_ME1_PIPE2_PRIORITY = 0x1e3c # macro
regCP_ME1_PIPE2_PRIORITY_BASE_IDX = 0 # macro
regCP_ME1_PIPE3_PRIORITY = 0x1e3d # macro
regCP_ME1_PIPE3_PRIORITY_BASE_IDX = 0 # macro
regCP_ME2_PIPE_PRIORITY_CNTS = 0x1e3e # macro
regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro
regCP_ME2_PIPE0_PRIORITY = 0x1e3f # macro
regCP_ME2_PIPE0_PRIORITY_BASE_IDX = 0 # macro
regCP_ME2_PIPE1_PRIORITY = 0x1e40 # macro
regCP_ME2_PIPE1_PRIORITY_BASE_IDX = 0 # macro
regCP_ME2_PIPE2_PRIORITY = 0x1e41 # macro
regCP_ME2_PIPE2_PRIORITY_BASE_IDX = 0 # macro
regCP_ME2_PIPE3_PRIORITY = 0x1e42 # macro
regCP_ME2_PIPE3_PRIORITY_BASE_IDX = 0 # macro
regCP_PFP_PRGRM_CNTR_START = 0x1e44 # macro
regCP_PFP_PRGRM_CNTR_START_BASE_IDX = 0 # macro
regCP_ME_PRGRM_CNTR_START = 0x1e45 # macro
regCP_ME_PRGRM_CNTR_START_BASE_IDX = 0 # macro
regCP_MEC1_PRGRM_CNTR_START = 0x1e46 # macro
regCP_MEC1_PRGRM_CNTR_START_BASE_IDX = 0 # macro
regCP_MEC2_PRGRM_CNTR_START = 0x1e47 # macro
regCP_MEC2_PRGRM_CNTR_START_BASE_IDX = 0 # macro
regCP_PFP_INTR_ROUTINE_START = 0x1e49 # macro
regCP_PFP_INTR_ROUTINE_START_BASE_IDX = 0 # macro
regCP_ME_INTR_ROUTINE_START = 0x1e4a # macro
regCP_ME_INTR_ROUTINE_START_BASE_IDX = 0 # macro
regCP_MEC1_INTR_ROUTINE_START = 0x1e4b # macro
regCP_MEC1_INTR_ROUTINE_START_BASE_IDX = 0 # macro
regCP_MEC2_INTR_ROUTINE_START = 0x1e4c # macro
regCP_MEC2_INTR_ROUTINE_START_BASE_IDX = 0 # macro
regCP_CONTEXT_CNTL = 0x1e4d # macro
regCP_CONTEXT_CNTL_BASE_IDX = 0 # macro
regCP_MAX_CONTEXT = 0x1e4e # macro
regCP_MAX_CONTEXT_BASE_IDX = 0 # macro
regCP_IQ_WAIT_TIME1 = 0x1e4f # macro
regCP_IQ_WAIT_TIME1_BASE_IDX = 0 # macro
regCP_IQ_WAIT_TIME2 = 0x1e50 # macro
regCP_IQ_WAIT_TIME2_BASE_IDX = 0 # macro
regCP_RB0_BASE_HI = 0x1e51 # macro
regCP_RB0_BASE_HI_BASE_IDX = 0 # macro
regCP_RB1_BASE_HI = 0x1e52 # macro
regCP_RB1_BASE_HI_BASE_IDX = 0 # macro
regCP_VMID_RESET = 0x1e53 # macro
regCP_VMID_RESET_BASE_IDX = 0 # macro
regCPC_INT_CNTL = 0x1e54 # macro
regCPC_INT_CNTL_BASE_IDX = 0 # macro
regCPC_INT_STATUS = 0x1e55 # macro
regCPC_INT_STATUS_BASE_IDX = 0 # macro
regCP_VMID_PREEMPT = 0x1e56 # macro
regCP_VMID_PREEMPT_BASE_IDX = 0 # macro
regCPC_INT_CNTX_ID = 0x1e57 # macro
regCPC_INT_CNTX_ID_BASE_IDX = 0 # macro
regCP_PQ_STATUS = 0x1e58 # macro
regCP_PQ_STATUS_BASE_IDX = 0 # macro
regCP_PFP_PRGRM_CNTR_START_HI = 0x1e59 # macro
regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX = 0 # macro
regCP_MAX_DRAW_COUNT = 0x1e5c # macro
regCP_MAX_DRAW_COUNT_BASE_IDX = 0 # macro
regCP_MEC1_F32_INT_DIS = 0x1e5d # macro
regCP_MEC1_F32_INT_DIS_BASE_IDX = 0 # macro
regCP_MEC2_F32_INT_DIS = 0x1e5e # macro
regCP_MEC2_F32_INT_DIS_BASE_IDX = 0 # macro
regCP_VMID_STATUS = 0x1e5f # macro
regCP_VMID_STATUS_BASE_IDX = 0 # macro
regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO = 0x1e60 # macro
regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro
regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI = 0x1e61 # macro
regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro
regCPC_SUSPEND_CTX_SAVE_CONTROL = 0x1e62 # macro
regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro
regCPC_SUSPEND_CNTL_STACK_OFFSET = 0x1e63 # macro
regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro
regCPC_SUSPEND_CNTL_STACK_SIZE = 0x1e64 # macro
regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX = 0 # macro
regCPC_SUSPEND_WG_STATE_OFFSET = 0x1e65 # macro
regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro
regCPC_SUSPEND_CTX_SAVE_SIZE = 0x1e66 # macro
regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX = 0 # macro
regCPC_OS_PIPES = 0x1e67 # macro
regCPC_OS_PIPES_BASE_IDX = 0 # macro
regCP_SUSPEND_RESUME_REQ = 0x1e68 # macro
regCP_SUSPEND_RESUME_REQ_BASE_IDX = 0 # macro
regCP_SUSPEND_CNTL = 0x1e69 # macro
regCP_SUSPEND_CNTL_BASE_IDX = 0 # macro
regCP_IQ_WAIT_TIME3 = 0x1e6a # macro
regCP_IQ_WAIT_TIME3_BASE_IDX = 0 # macro
regCPC_DDID_BASE_ADDR_LO = 0x1e6b # macro
regCPC_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro
regCP_DDID_BASE_ADDR_LO = 0x1e6b # macro
regCP_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro
regCPC_DDID_BASE_ADDR_HI = 0x1e6c # macro
regCPC_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro
regCP_DDID_BASE_ADDR_HI = 0x1e6c # macro
regCP_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro
regCPC_DDID_CNTL = 0x1e6d # macro
regCPC_DDID_CNTL_BASE_IDX = 0 # macro
regCP_DDID_CNTL = 0x1e6d # macro
regCP_DDID_CNTL_BASE_IDX = 0 # macro
regCP_GFX_DDID_INFLIGHT_COUNT = 0x1e6e # macro
regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro
regCP_GFX_DDID_WPTR = 0x1e6f # macro
regCP_GFX_DDID_WPTR_BASE_IDX = 0 # macro
regCP_GFX_DDID_RPTR = 0x1e70 # macro
regCP_GFX_DDID_RPTR_BASE_IDX = 0 # macro
regCP_GFX_DDID_DELTA_RPT_COUNT = 0x1e71 # macro
regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro
regCP_GFX_HPD_STATUS0 = 0x1e72 # macro
regCP_GFX_HPD_STATUS0_BASE_IDX = 0 # macro
regCP_GFX_HPD_CONTROL0 = 0x1e73 # macro
regCP_GFX_HPD_CONTROL0_BASE_IDX = 0 # macro
regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO = 0x1e74 # macro
regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX = 0 # macro
regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI = 0x1e75 # macro
regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX = 0 # macro
regCP_GFX_HPD_OSPRE_FENCE_DATA_LO = 0x1e76 # macro
regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX = 0 # macro
regCP_GFX_HPD_OSPRE_FENCE_DATA_HI = 0x1e77 # macro
regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX = 0 # macro
regCP_GFX_INDEX_MUTEX = 0x1e78 # macro
regCP_GFX_INDEX_MUTEX_BASE_IDX = 0 # macro
regCP_ME_PRGRM_CNTR_START_HI = 0x1e79 # macro
regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX = 0 # macro
regCP_PFP_INTR_ROUTINE_START_HI = 0x1e7a # macro
regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX = 0 # macro
regCP_ME_INTR_ROUTINE_START_HI = 0x1e7b # macro
regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX = 0 # macro
regCP_GFX_MQD_BASE_ADDR = 0x1e7e # macro
regCP_GFX_MQD_BASE_ADDR_BASE_IDX = 0 # macro
regCP_GFX_MQD_BASE_ADDR_HI = 0x1e7f # macro
regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro
regCP_GFX_HQD_ACTIVE = 0x1e80 # macro
regCP_GFX_HQD_ACTIVE_BASE_IDX = 0 # macro
regCP_GFX_HQD_VMID = 0x1e81 # macro
regCP_GFX_HQD_VMID_BASE_IDX = 0 # macro
regCP_GFX_HQD_QUEUE_PRIORITY = 0x1e84 # macro
regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro
regCP_GFX_HQD_QUANTUM = 0x1e85 # macro
regCP_GFX_HQD_QUANTUM_BASE_IDX = 0 # macro
regCP_GFX_HQD_BASE = 0x1e86 # macro
regCP_GFX_HQD_BASE_BASE_IDX = 0 # macro
regCP_GFX_HQD_BASE_HI = 0x1e87 # macro
regCP_GFX_HQD_BASE_HI_BASE_IDX = 0 # macro
regCP_GFX_HQD_RPTR = 0x1e88 # macro
regCP_GFX_HQD_RPTR_BASE_IDX = 0 # macro
regCP_GFX_HQD_RPTR_ADDR = 0x1e89 # macro
regCP_GFX_HQD_RPTR_ADDR_BASE_IDX = 0 # macro
regCP_GFX_HQD_RPTR_ADDR_HI = 0x1e8a # macro
regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX = 0 # macro
regCP_RB_WPTR_POLL_ADDR_LO = 0x1e8b # macro
regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
regCP_RB_WPTR_POLL_ADDR_HI = 0x1e8c # macro
regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regCP_RB_DOORBELL_CONTROL = 0x1e8d # macro
regCP_RB_DOORBELL_CONTROL_BASE_IDX = 0 # macro
regCP_GFX_HQD_OFFSET = 0x1e8e # macro
regCP_GFX_HQD_OFFSET_BASE_IDX = 0 # macro
regCP_GFX_HQD_CNTL = 0x1e8f # macro
regCP_GFX_HQD_CNTL_BASE_IDX = 0 # macro
regCP_GFX_HQD_CSMD_RPTR = 0x1e90 # macro
regCP_GFX_HQD_CSMD_RPTR_BASE_IDX = 0 # macro
regCP_GFX_HQD_WPTR = 0x1e91 # macro
regCP_GFX_HQD_WPTR_BASE_IDX = 0 # macro
regCP_GFX_HQD_WPTR_HI = 0x1e92 # macro
regCP_GFX_HQD_WPTR_HI_BASE_IDX = 0 # macro
regCP_GFX_HQD_DEQUEUE_REQUEST = 0x1e93 # macro
regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro
regCP_GFX_HQD_MAPPED = 0x1e94 # macro
regCP_GFX_HQD_MAPPED_BASE_IDX = 0 # macro
regCP_GFX_HQD_QUE_MGR_CONTROL = 0x1e95 # macro
regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX = 0 # macro
regCP_GFX_HQD_IQ_TIMER = 0x1e96 # macro
regCP_GFX_HQD_IQ_TIMER_BASE_IDX = 0 # macro
regCP_GFX_HQD_HQ_STATUS0 = 0x1e98 # macro
regCP_GFX_HQD_HQ_STATUS0_BASE_IDX = 0 # macro
regCP_GFX_HQD_HQ_CONTROL0 = 0x1e99 # macro
regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro
regCP_GFX_MQD_CONTROL = 0x1e9a # macro
regCP_GFX_MQD_CONTROL_BASE_IDX = 0 # macro
regCP_HQD_GFX_CONTROL = 0x1e9f # macro
regCP_HQD_GFX_CONTROL_BASE_IDX = 0 # macro
regCP_HQD_GFX_STATUS = 0x1ea0 # macro
regCP_HQD_GFX_STATUS_BASE_IDX = 0 # macro
regCP_DMA_WATCH0_ADDR_LO = 0x1ec0 # macro
regCP_DMA_WATCH0_ADDR_LO_BASE_IDX = 0 # macro
regCP_DMA_WATCH0_ADDR_HI = 0x1ec1 # macro
regCP_DMA_WATCH0_ADDR_HI_BASE_IDX = 0 # macro
regCP_DMA_WATCH0_MASK = 0x1ec2 # macro
regCP_DMA_WATCH0_MASK_BASE_IDX = 0 # macro
regCP_DMA_WATCH0_CNTL = 0x1ec3 # macro
regCP_DMA_WATCH0_CNTL_BASE_IDX = 0 # macro
regCP_DMA_WATCH1_ADDR_LO = 0x1ec4 # macro
regCP_DMA_WATCH1_ADDR_LO_BASE_IDX = 0 # macro
regCP_DMA_WATCH1_ADDR_HI = 0x1ec5 # macro
regCP_DMA_WATCH1_ADDR_HI_BASE_IDX = 0 # macro
regCP_DMA_WATCH1_MASK = 0x1ec6 # macro
regCP_DMA_WATCH1_MASK_BASE_IDX = 0 # macro
regCP_DMA_WATCH1_CNTL = 0x1ec7 # macro
regCP_DMA_WATCH1_CNTL_BASE_IDX = 0 # macro
regCP_DMA_WATCH2_ADDR_LO = 0x1ec8 # macro
regCP_DMA_WATCH2_ADDR_LO_BASE_IDX = 0 # macro
regCP_DMA_WATCH2_ADDR_HI = 0x1ec9 # macro
regCP_DMA_WATCH2_ADDR_HI_BASE_IDX = 0 # macro
regCP_DMA_WATCH2_MASK = 0x1eca # macro
regCP_DMA_WATCH2_MASK_BASE_IDX = 0 # macro
regCP_DMA_WATCH2_CNTL = 0x1ecb # macro
regCP_DMA_WATCH2_CNTL_BASE_IDX = 0 # macro
regCP_DMA_WATCH3_ADDR_LO = 0x1ecc # macro
regCP_DMA_WATCH3_ADDR_LO_BASE_IDX = 0 # macro
regCP_DMA_WATCH3_ADDR_HI = 0x1ecd # macro
regCP_DMA_WATCH3_ADDR_HI_BASE_IDX = 0 # macro
regCP_DMA_WATCH3_MASK = 0x1ece # macro
regCP_DMA_WATCH3_MASK_BASE_IDX = 0 # macro
regCP_DMA_WATCH3_CNTL = 0x1ecf # macro
regCP_DMA_WATCH3_CNTL_BASE_IDX = 0 # macro
regCP_DMA_WATCH_STAT_ADDR_LO = 0x1ed0 # macro
regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX = 0 # macro
regCP_DMA_WATCH_STAT_ADDR_HI = 0x1ed1 # macro
regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX = 0 # macro
regCP_DMA_WATCH_STAT = 0x1ed2 # macro
regCP_DMA_WATCH_STAT_BASE_IDX = 0 # macro
regCP_PFP_JT_STAT = 0x1ed3 # macro
regCP_PFP_JT_STAT_BASE_IDX = 0 # macro
regCP_MEC_JT_STAT = 0x1ed5 # macro
regCP_MEC_JT_STAT_BASE_IDX = 0 # macro
regCP_CPC_BUSY_HYSTERESIS = 0x1edb # macro
regCP_CPC_BUSY_HYSTERESIS_BASE_IDX = 0 # macro
regCP_CPF_BUSY_HYSTERESIS1 = 0x1edc # macro
regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX = 0 # macro
regCP_CPF_BUSY_HYSTERESIS2 = 0x1edd # macro
regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX = 0 # macro
regCP_CPG_BUSY_HYSTERESIS1 = 0x1ede # macro
regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX = 0 # macro
regCP_CPG_BUSY_HYSTERESIS2 = 0x1edf # macro
regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX = 0 # macro
regCP_RB_DOORBELL_CLEAR = 0x1f28 # macro
regCP_RB_DOORBELL_CLEAR_BASE_IDX = 0 # macro
regCP_RB0_ACTIVE = 0x1f40 # macro
regCP_RB0_ACTIVE_BASE_IDX = 0 # macro
regCP_RB_ACTIVE = 0x1f40 # macro
regCP_RB_ACTIVE_BASE_IDX = 0 # macro
regCP_RB1_ACTIVE = 0x1f41 # macro
regCP_RB1_ACTIVE_BASE_IDX = 0 # macro
regCP_RB_STATUS = 0x1f43 # macro
regCP_RB_STATUS_BASE_IDX = 0 # macro
regCPG_RCIU_CAM_INDEX = 0x1f44 # macro
regCPG_RCIU_CAM_INDEX_BASE_IDX = 0 # macro
regCPG_RCIU_CAM_DATA = 0x1f45 # macro
regCPG_RCIU_CAM_DATA_BASE_IDX = 0 # macro
regCPG_RCIU_CAM_DATA_PHASE0 = 0x1f45 # macro
regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX = 0 # macro
regCPG_RCIU_CAM_DATA_PHASE1 = 0x1f45 # macro
regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX = 0 # macro
regCPG_RCIU_CAM_DATA_PHASE2 = 0x1f45 # macro
regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX = 0 # macro
regCP_GPU_TIMESTAMP_OFFSET_LO = 0x1f4c # macro
regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX = 0 # macro
regCP_GPU_TIMESTAMP_OFFSET_HI = 0x1f4d # macro
regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX = 0 # macro
regCP_SDMA_DMA_DONE = 0x1f4e # macro
regCP_SDMA_DMA_DONE_BASE_IDX = 0 # macro
regCP_PFP_SDMA_CS = 0x1f4f # macro
regCP_PFP_SDMA_CS_BASE_IDX = 0 # macro
regCP_ME_SDMA_CS = 0x1f50 # macro
regCP_ME_SDMA_CS_BASE_IDX = 0 # macro
regCPF_GCR_CNTL = 0x1f53 # macro
regCPF_GCR_CNTL_BASE_IDX = 0 # macro
regCPG_UTCL1_STATUS = 0x1f54 # macro
regCPG_UTCL1_STATUS_BASE_IDX = 0 # macro
regCPC_UTCL1_STATUS = 0x1f55 # macro
regCPC_UTCL1_STATUS_BASE_IDX = 0 # macro
regCPF_UTCL1_STATUS = 0x1f56 # macro
regCPF_UTCL1_STATUS_BASE_IDX = 0 # macro
regCP_SD_CNTL = 0x1f57 # macro
regCP_SD_CNTL_BASE_IDX = 0 # macro
regCP_SOFT_RESET_CNTL = 0x1f59 # macro
regCP_SOFT_RESET_CNTL_BASE_IDX = 0 # macro
regCP_CPC_GFX_CNTL = 0x1f5a # macro
regCP_CPC_GFX_CNTL_BASE_IDX = 0 # macro
regSPI_ARB_PRIORITY = 0x1f60 # macro
regSPI_ARB_PRIORITY_BASE_IDX = 0 # macro
regSPI_ARB_CYCLES_0 = 0x1f61 # macro
regSPI_ARB_CYCLES_0_BASE_IDX = 0 # macro
regSPI_ARB_CYCLES_1 = 0x1f62 # macro
regSPI_ARB_CYCLES_1_BASE_IDX = 0 # macro
regSPI_WCL_PIPE_PERCENT_GFX = 0x1f67 # macro
regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX = 0 # macro
regSPI_WCL_PIPE_PERCENT_HP3D = 0x1f68 # macro
regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX = 0 # macro
regSPI_WCL_PIPE_PERCENT_CS0 = 0x1f69 # macro
regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX = 0 # macro
regSPI_WCL_PIPE_PERCENT_CS1 = 0x1f6a # macro
regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX = 0 # macro
regSPI_WCL_PIPE_PERCENT_CS2 = 0x1f6b # macro
regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX = 0 # macro
regSPI_WCL_PIPE_PERCENT_CS3 = 0x1f6c # macro
regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX = 0 # macro
regSPI_WCL_PIPE_PERCENT_CS4 = 0x1f6d # macro
regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX = 0 # macro
regSPI_WCL_PIPE_PERCENT_CS5 = 0x1f6e # macro
regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX = 0 # macro
regSPI_WCL_PIPE_PERCENT_CS6 = 0x1f6f # macro
regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX = 0 # macro
regSPI_WCL_PIPE_PERCENT_CS7 = 0x1f70 # macro
regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX = 0 # macro
regSPI_USER_ACCUM_VMID_CNTL = 0x1f71 # macro
regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX = 0 # macro
regSPI_GDBG_PER_VMID_CNTL = 0x1f72 # macro
regSPI_GDBG_PER_VMID_CNTL_BASE_IDX = 0 # macro
regSPI_COMPUTE_QUEUE_RESET = 0x1f73 # macro
regSPI_COMPUTE_QUEUE_RESET_BASE_IDX = 0 # macro
regSPI_COMPUTE_WF_CTX_SAVE = 0x1f74 # macro
regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX = 0 # macro
regCP_HPD_UTCL1_CNTL = 0x1fa3 # macro
regCP_HPD_UTCL1_CNTL_BASE_IDX = 0 # macro
regCP_HPD_UTCL1_ERROR = 0x1fa7 # macro
regCP_HPD_UTCL1_ERROR_BASE_IDX = 0 # macro
regCP_HPD_UTCL1_ERROR_ADDR = 0x1fa8 # macro
regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX = 0 # macro
regCP_MQD_BASE_ADDR = 0x1fa9 # macro
regCP_MQD_BASE_ADDR_BASE_IDX = 0 # macro
regCP_MQD_BASE_ADDR_HI = 0x1faa # macro
regCP_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro
regCP_HQD_ACTIVE = 0x1fab # macro
regCP_HQD_ACTIVE_BASE_IDX = 0 # macro
regCP_HQD_VMID = 0x1fac # macro
regCP_HQD_VMID_BASE_IDX = 0 # macro
regCP_HQD_PERSISTENT_STATE = 0x1fad # macro
regCP_HQD_PERSISTENT_STATE_BASE_IDX = 0 # macro
regCP_HQD_PIPE_PRIORITY = 0x1fae # macro
regCP_HQD_PIPE_PRIORITY_BASE_IDX = 0 # macro
regCP_HQD_QUEUE_PRIORITY = 0x1faf # macro
regCP_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro
regCP_HQD_QUANTUM = 0x1fb0 # macro
regCP_HQD_QUANTUM_BASE_IDX = 0 # macro
regCP_HQD_PQ_BASE = 0x1fb1 # macro
regCP_HQD_PQ_BASE_BASE_IDX = 0 # macro
regCP_HQD_PQ_BASE_HI = 0x1fb2 # macro
regCP_HQD_PQ_BASE_HI_BASE_IDX = 0 # macro
regCP_HQD_PQ_RPTR = 0x1fb3 # macro
regCP_HQD_PQ_RPTR_BASE_IDX = 0 # macro
regCP_HQD_PQ_RPTR_REPORT_ADDR = 0x1fb4 # macro
regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX = 0 # macro
regCP_HQD_PQ_RPTR_REPORT_ADDR_HI = 0x1fb5 # macro
regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX = 0 # macro
regCP_HQD_PQ_WPTR_POLL_ADDR = 0x1fb6 # macro
regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX = 0 # macro
regCP_HQD_PQ_WPTR_POLL_ADDR_HI = 0x1fb7 # macro
regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
regCP_HQD_PQ_DOORBELL_CONTROL = 0x1fb8 # macro
regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX = 0 # macro
regCP_HQD_PQ_CONTROL = 0x1fba # macro
regCP_HQD_PQ_CONTROL_BASE_IDX = 0 # macro
regCP_HQD_IB_BASE_ADDR = 0x1fbb # macro
regCP_HQD_IB_BASE_ADDR_BASE_IDX = 0 # macro
regCP_HQD_IB_BASE_ADDR_HI = 0x1fbc # macro
regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX = 0 # macro
regCP_HQD_IB_RPTR = 0x1fbd # macro
regCP_HQD_IB_RPTR_BASE_IDX = 0 # macro
regCP_HQD_IB_CONTROL = 0x1fbe # macro
regCP_HQD_IB_CONTROL_BASE_IDX = 0 # macro
regCP_HQD_IQ_TIMER = 0x1fbf # macro
regCP_HQD_IQ_TIMER_BASE_IDX = 0 # macro
regCP_HQD_IQ_RPTR = 0x1fc0 # macro
regCP_HQD_IQ_RPTR_BASE_IDX = 0 # macro
regCP_HQD_DEQUEUE_REQUEST = 0x1fc1 # macro
regCP_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro
regCP_HQD_DMA_OFFLOAD = 0x1fc2 # macro
regCP_HQD_DMA_OFFLOAD_BASE_IDX = 0 # macro
regCP_HQD_OFFLOAD = 0x1fc2 # macro
regCP_HQD_OFFLOAD_BASE_IDX = 0 # macro
regCP_HQD_SEMA_CMD = 0x1fc3 # macro
regCP_HQD_SEMA_CMD_BASE_IDX = 0 # macro
regCP_HQD_MSG_TYPE = 0x1fc4 # macro
regCP_HQD_MSG_TYPE_BASE_IDX = 0 # macro
regCP_HQD_ATOMIC0_PREOP_LO = 0x1fc5 # macro
regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX = 0 # macro
regCP_HQD_ATOMIC0_PREOP_HI = 0x1fc6 # macro
regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX = 0 # macro
regCP_HQD_ATOMIC1_PREOP_LO = 0x1fc7 # macro
regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX = 0 # macro
regCP_HQD_ATOMIC1_PREOP_HI = 0x1fc8 # macro
regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX = 0 # macro
regCP_HQD_HQ_SCHEDULER0 = 0x1fc9 # macro
regCP_HQD_HQ_SCHEDULER0_BASE_IDX = 0 # macro
regCP_HQD_HQ_STATUS0 = 0x1fc9 # macro
regCP_HQD_HQ_STATUS0_BASE_IDX = 0 # macro
regCP_HQD_HQ_CONTROL0 = 0x1fca # macro
regCP_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro
regCP_HQD_HQ_SCHEDULER1 = 0x1fca # macro
regCP_HQD_HQ_SCHEDULER1_BASE_IDX = 0 # macro
regCP_MQD_CONTROL = 0x1fcb # macro
regCP_MQD_CONTROL_BASE_IDX = 0 # macro
regCP_HQD_HQ_STATUS1 = 0x1fcc # macro
regCP_HQD_HQ_STATUS1_BASE_IDX = 0 # macro
regCP_HQD_HQ_CONTROL1 = 0x1fcd # macro
regCP_HQD_HQ_CONTROL1_BASE_IDX = 0 # macro
regCP_HQD_EOP_BASE_ADDR = 0x1fce # macro
regCP_HQD_EOP_BASE_ADDR_BASE_IDX = 0 # macro
regCP_HQD_EOP_BASE_ADDR_HI = 0x1fcf # macro
regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX = 0 # macro
regCP_HQD_EOP_CONTROL = 0x1fd0 # macro
regCP_HQD_EOP_CONTROL_BASE_IDX = 0 # macro
regCP_HQD_EOP_RPTR = 0x1fd1 # macro
regCP_HQD_EOP_RPTR_BASE_IDX = 0 # macro
regCP_HQD_EOP_WPTR = 0x1fd2 # macro
regCP_HQD_EOP_WPTR_BASE_IDX = 0 # macro
regCP_HQD_EOP_EVENTS = 0x1fd3 # macro
regCP_HQD_EOP_EVENTS_BASE_IDX = 0 # macro
regCP_HQD_CTX_SAVE_BASE_ADDR_LO = 0x1fd4 # macro
regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro
regCP_HQD_CTX_SAVE_BASE_ADDR_HI = 0x1fd5 # macro
regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro
regCP_HQD_CTX_SAVE_CONTROL = 0x1fd6 # macro
regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro
regCP_HQD_CNTL_STACK_OFFSET = 0x1fd7 # macro
regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro
regCP_HQD_CNTL_STACK_SIZE = 0x1fd8 # macro
regCP_HQD_CNTL_STACK_SIZE_BASE_IDX = 0 # macro
regCP_HQD_WG_STATE_OFFSET = 0x1fd9 # macro
regCP_HQD_WG_STATE_OFFSET_BASE_IDX = 0 # macro
regCP_HQD_CTX_SAVE_SIZE = 0x1fda # macro
regCP_HQD_CTX_SAVE_SIZE_BASE_IDX = 0 # macro
regCP_HQD_GDS_RESOURCE_STATE = 0x1fdb # macro
regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX = 0 # macro
regCP_HQD_ERROR = 0x1fdc # macro
regCP_HQD_ERROR_BASE_IDX = 0 # macro
regCP_HQD_EOP_WPTR_MEM = 0x1fdd # macro
regCP_HQD_EOP_WPTR_MEM_BASE_IDX = 0 # macro
regCP_HQD_AQL_CONTROL = 0x1fde # macro
regCP_HQD_AQL_CONTROL_BASE_IDX = 0 # macro
regCP_HQD_PQ_WPTR_LO = 0x1fdf # macro
regCP_HQD_PQ_WPTR_LO_BASE_IDX = 0 # macro
regCP_HQD_PQ_WPTR_HI = 0x1fe0 # macro
regCP_HQD_PQ_WPTR_HI_BASE_IDX = 0 # macro
regCP_HQD_SUSPEND_CNTL_STACK_OFFSET = 0x1fe1 # macro
regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro
regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT = 0x1fe2 # macro
regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX = 0 # macro
regCP_HQD_SUSPEND_WG_STATE_OFFSET = 0x1fe3 # macro
regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro
regCP_HQD_DDID_RPTR = 0x1fe4 # macro
regCP_HQD_DDID_RPTR_BASE_IDX = 0 # macro
regCP_HQD_DDID_WPTR = 0x1fe5 # macro
regCP_HQD_DDID_WPTR_BASE_IDX = 0 # macro
regCP_HQD_DDID_INFLIGHT_COUNT = 0x1fe6 # macro
regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro
regCP_HQD_DDID_DELTA_RPT_COUNT = 0x1fe7 # macro
regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro
regCP_HQD_DEQUEUE_STATUS = 0x1fe8 # macro
regCP_HQD_DEQUEUE_STATUS_BASE_IDX = 0 # macro
regTCP_WATCH0_ADDR_H = 0x2048 # macro
regTCP_WATCH0_ADDR_H_BASE_IDX = 0 # macro
regTCP_WATCH0_ADDR_L = 0x2049 # macro
regTCP_WATCH0_ADDR_L_BASE_IDX = 0 # macro
regTCP_WATCH0_CNTL = 0x204a # macro
regTCP_WATCH0_CNTL_BASE_IDX = 0 # macro
regTCP_WATCH1_ADDR_H = 0x204b # macro
regTCP_WATCH1_ADDR_H_BASE_IDX = 0 # macro
regTCP_WATCH1_ADDR_L = 0x204c # macro
regTCP_WATCH1_ADDR_L_BASE_IDX = 0 # macro
regTCP_WATCH1_CNTL = 0x204d # macro
regTCP_WATCH1_CNTL_BASE_IDX = 0 # macro
regTCP_WATCH2_ADDR_H = 0x204e # macro
regTCP_WATCH2_ADDR_H_BASE_IDX = 0 # macro
regTCP_WATCH2_ADDR_L = 0x204f # macro
regTCP_WATCH2_ADDR_L_BASE_IDX = 0 # macro
regTCP_WATCH2_CNTL = 0x2050 # macro
regTCP_WATCH2_CNTL_BASE_IDX = 0 # macro
regTCP_WATCH3_ADDR_H = 0x2051 # macro
regTCP_WATCH3_ADDR_H_BASE_IDX = 0 # macro
regTCP_WATCH3_ADDR_L = 0x2052 # macro
regTCP_WATCH3_ADDR_L_BASE_IDX = 0 # macro
regTCP_WATCH3_CNTL = 0x2053 # macro
regTCP_WATCH3_CNTL_BASE_IDX = 0 # macro
regGDS_VMID0_BASE = 0x20a0 # macro
regGDS_VMID0_BASE_BASE_IDX = 0 # macro
regGDS_VMID0_SIZE = 0x20a1 # macro
regGDS_VMID0_SIZE_BASE_IDX = 0 # macro
regGDS_VMID1_BASE = 0x20a2 # macro
regGDS_VMID1_BASE_BASE_IDX = 0 # macro
regGDS_VMID1_SIZE = 0x20a3 # macro
regGDS_VMID1_SIZE_BASE_IDX = 0 # macro
regGDS_VMID2_BASE = 0x20a4 # macro
regGDS_VMID2_BASE_BASE_IDX = 0 # macro
regGDS_VMID2_SIZE = 0x20a5 # macro
regGDS_VMID2_SIZE_BASE_IDX = 0 # macro
regGDS_VMID3_BASE = 0x20a6 # macro
regGDS_VMID3_BASE_BASE_IDX = 0 # macro
regGDS_VMID3_SIZE = 0x20a7 # macro
regGDS_VMID3_SIZE_BASE_IDX = 0 # macro
regGDS_VMID4_BASE = 0x20a8 # macro
regGDS_VMID4_BASE_BASE_IDX = 0 # macro
regGDS_VMID4_SIZE = 0x20a9 # macro
regGDS_VMID4_SIZE_BASE_IDX = 0 # macro
regGDS_VMID5_BASE = 0x20aa # macro
regGDS_VMID5_BASE_BASE_IDX = 0 # macro
regGDS_VMID5_SIZE = 0x20ab # macro
regGDS_VMID5_SIZE_BASE_IDX = 0 # macro
regGDS_VMID6_BASE = 0x20ac # macro
regGDS_VMID6_BASE_BASE_IDX = 0 # macro
regGDS_VMID6_SIZE = 0x20ad # macro
regGDS_VMID6_SIZE_BASE_IDX = 0 # macro
regGDS_VMID7_BASE = 0x20ae # macro
regGDS_VMID7_BASE_BASE_IDX = 0 # macro
regGDS_VMID7_SIZE = 0x20af # macro
regGDS_VMID7_SIZE_BASE_IDX = 0 # macro
regGDS_VMID8_BASE = 0x20b0 # macro
regGDS_VMID8_BASE_BASE_IDX = 0 # macro
regGDS_VMID8_SIZE = 0x20b1 # macro
regGDS_VMID8_SIZE_BASE_IDX = 0 # macro
regGDS_VMID9_BASE = 0x20b2 # macro
regGDS_VMID9_BASE_BASE_IDX = 0 # macro
regGDS_VMID9_SIZE = 0x20b3 # macro
regGDS_VMID9_SIZE_BASE_IDX = 0 # macro
regGDS_VMID10_BASE = 0x20b4 # macro
regGDS_VMID10_BASE_BASE_IDX = 0 # macro
regGDS_VMID10_SIZE = 0x20b5 # macro
regGDS_VMID10_SIZE_BASE_IDX = 0 # macro
regGDS_VMID11_BASE = 0x20b6 # macro
regGDS_VMID11_BASE_BASE_IDX = 0 # macro
regGDS_VMID11_SIZE = 0x20b7 # macro
regGDS_VMID11_SIZE_BASE_IDX = 0 # macro
regGDS_VMID12_BASE = 0x20b8 # macro
regGDS_VMID12_BASE_BASE_IDX = 0 # macro
regGDS_VMID12_SIZE = 0x20b9 # macro
regGDS_VMID12_SIZE_BASE_IDX = 0 # macro
regGDS_VMID13_BASE = 0x20ba # macro
regGDS_VMID13_BASE_BASE_IDX = 0 # macro
regGDS_VMID13_SIZE = 0x20bb # macro
regGDS_VMID13_SIZE_BASE_IDX = 0 # macro
regGDS_VMID14_BASE = 0x20bc # macro
regGDS_VMID14_BASE_BASE_IDX = 0 # macro
regGDS_VMID14_SIZE = 0x20bd # macro
regGDS_VMID14_SIZE_BASE_IDX = 0 # macro
regGDS_VMID15_BASE = 0x20be # macro
regGDS_VMID15_BASE_BASE_IDX = 0 # macro
regGDS_VMID15_SIZE = 0x20bf # macro
regGDS_VMID15_SIZE_BASE_IDX = 0 # macro
regGDS_GWS_VMID0 = 0x20c0 # macro
regGDS_GWS_VMID0_BASE_IDX = 0 # macro
regGDS_GWS_VMID1 = 0x20c1 # macro
regGDS_GWS_VMID1_BASE_IDX = 0 # macro
regGDS_GWS_VMID2 = 0x20c2 # macro
regGDS_GWS_VMID2_BASE_IDX = 0 # macro
regGDS_GWS_VMID3 = 0x20c3 # macro
regGDS_GWS_VMID3_BASE_IDX = 0 # macro
regGDS_GWS_VMID4 = 0x20c4 # macro
regGDS_GWS_VMID4_BASE_IDX = 0 # macro
regGDS_GWS_VMID5 = 0x20c5 # macro
regGDS_GWS_VMID5_BASE_IDX = 0 # macro
regGDS_GWS_VMID6 = 0x20c6 # macro
regGDS_GWS_VMID6_BASE_IDX = 0 # macro
regGDS_GWS_VMID7 = 0x20c7 # macro
regGDS_GWS_VMID7_BASE_IDX = 0 # macro
regGDS_GWS_VMID8 = 0x20c8 # macro
regGDS_GWS_VMID8_BASE_IDX = 0 # macro
regGDS_GWS_VMID9 = 0x20c9 # macro
regGDS_GWS_VMID9_BASE_IDX = 0 # macro
regGDS_GWS_VMID10 = 0x20ca # macro
regGDS_GWS_VMID10_BASE_IDX = 0 # macro
regGDS_GWS_VMID11 = 0x20cb # macro
regGDS_GWS_VMID11_BASE_IDX = 0 # macro
regGDS_GWS_VMID12 = 0x20cc # macro
regGDS_GWS_VMID12_BASE_IDX = 0 # macro
regGDS_GWS_VMID13 = 0x20cd # macro
regGDS_GWS_VMID13_BASE_IDX = 0 # macro
regGDS_GWS_VMID14 = 0x20ce # macro
regGDS_GWS_VMID14_BASE_IDX = 0 # macro
regGDS_GWS_VMID15 = 0x20cf # macro
regGDS_GWS_VMID15_BASE_IDX = 0 # macro
regGDS_OA_VMID0 = 0x20d0 # macro
regGDS_OA_VMID0_BASE_IDX = 0 # macro
regGDS_OA_VMID1 = 0x20d1 # macro
regGDS_OA_VMID1_BASE_IDX = 0 # macro
regGDS_OA_VMID2 = 0x20d2 # macro
regGDS_OA_VMID2_BASE_IDX = 0 # macro
regGDS_OA_VMID3 = 0x20d3 # macro
regGDS_OA_VMID3_BASE_IDX = 0 # macro
regGDS_OA_VMID4 = 0x20d4 # macro
regGDS_OA_VMID4_BASE_IDX = 0 # macro
regGDS_OA_VMID5 = 0x20d5 # macro
regGDS_OA_VMID5_BASE_IDX = 0 # macro
regGDS_OA_VMID6 = 0x20d6 # macro
regGDS_OA_VMID6_BASE_IDX = 0 # macro
regGDS_OA_VMID7 = 0x20d7 # macro
regGDS_OA_VMID7_BASE_IDX = 0 # macro
regGDS_OA_VMID8 = 0x20d8 # macro
regGDS_OA_VMID8_BASE_IDX = 0 # macro
regGDS_OA_VMID9 = 0x20d9 # macro
regGDS_OA_VMID9_BASE_IDX = 0 # macro
regGDS_OA_VMID10 = 0x20da # macro
regGDS_OA_VMID10_BASE_IDX = 0 # macro
regGDS_OA_VMID11 = 0x20db # macro
regGDS_OA_VMID11_BASE_IDX = 0 # macro
regGDS_OA_VMID12 = 0x20dc # macro
regGDS_OA_VMID12_BASE_IDX = 0 # macro
regGDS_OA_VMID13 = 0x20dd # macro
regGDS_OA_VMID13_BASE_IDX = 0 # macro
regGDS_OA_VMID14 = 0x20de # macro
regGDS_OA_VMID14_BASE_IDX = 0 # macro
regGDS_OA_VMID15 = 0x20df # macro
regGDS_OA_VMID15_BASE_IDX = 0 # macro
regGDS_GWS_RESET0 = 0x20e4 # macro
regGDS_GWS_RESET0_BASE_IDX = 0 # macro
regGDS_GWS_RESET1 = 0x20e5 # macro
regGDS_GWS_RESET1_BASE_IDX = 0 # macro
regGDS_GWS_RESOURCE_RESET = 0x20e6 # macro
regGDS_GWS_RESOURCE_RESET_BASE_IDX = 0 # macro
regGDS_COMPUTE_MAX_WAVE_ID = 0x20e8 # macro
regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX = 0 # macro
regGDS_OA_RESET_MASK = 0x20e9 # macro
regGDS_OA_RESET_MASK_BASE_IDX = 0 # macro
regGDS_OA_RESET = 0x20ea # macro
regGDS_OA_RESET_BASE_IDX = 0 # macro
regGDS_CS_CTXSW_STATUS = 0x20ed # macro
regGDS_CS_CTXSW_STATUS_BASE_IDX = 0 # macro
regGDS_CS_CTXSW_CNT0 = 0x20ee # macro
regGDS_CS_CTXSW_CNT0_BASE_IDX = 0 # macro
regGDS_CS_CTXSW_CNT1 = 0x20ef # macro
regGDS_CS_CTXSW_CNT1_BASE_IDX = 0 # macro
regGDS_CS_CTXSW_CNT2 = 0x20f0 # macro
regGDS_CS_CTXSW_CNT2_BASE_IDX = 0 # macro
regGDS_CS_CTXSW_CNT3 = 0x20f1 # macro
regGDS_CS_CTXSW_CNT3_BASE_IDX = 0 # macro
regGDS_GFX_CTXSW_STATUS = 0x20f2 # macro
regGDS_GFX_CTXSW_STATUS_BASE_IDX = 0 # macro
regGDS_PS_CTXSW_CNT0 = 0x20f7 # macro
regGDS_PS_CTXSW_CNT0_BASE_IDX = 0 # macro
regGDS_PS_CTXSW_CNT1 = 0x20f8 # macro
regGDS_PS_CTXSW_CNT1_BASE_IDX = 0 # macro
regGDS_PS_CTXSW_CNT2 = 0x20f9 # macro
regGDS_PS_CTXSW_CNT2_BASE_IDX = 0 # macro
regGDS_PS_CTXSW_CNT3 = 0x20fa # macro
regGDS_PS_CTXSW_CNT3_BASE_IDX = 0 # macro
regGDS_PS_CTXSW_IDX = 0x20fb # macro
regGDS_PS_CTXSW_IDX_BASE_IDX = 0 # macro
regGDS_GS_CTXSW_CNT0 = 0x2117 # macro
regGDS_GS_CTXSW_CNT0_BASE_IDX = 0 # macro
regGDS_GS_CTXSW_CNT1 = 0x2118 # macro
regGDS_GS_CTXSW_CNT1_BASE_IDX = 0 # macro
regGDS_GS_CTXSW_CNT2 = 0x2119 # macro
regGDS_GS_CTXSW_CNT2_BASE_IDX = 0 # macro
regGDS_GS_CTXSW_CNT3 = 0x211a # macro
regGDS_GS_CTXSW_CNT3_BASE_IDX = 0 # macro
regGDS_MEMORY_CLEAN = 0x211f # macro
regGDS_MEMORY_CLEAN_BASE_IDX = 0 # macro
regGUS_IO_RD_COMBINE_FLUSH = 0x2c00 # macro
regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX = 1 # macro
regGUS_IO_WR_COMBINE_FLUSH = 0x2c01 # macro
regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_AGE_RATE = 0x2c02 # macro
regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_AGE_RATE = 0x2c03 # macro
regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_AGE_COEFF = 0x2c04 # macro
regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_AGE_COEFF = 0x2c05 # macro
regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_QUEUING = 0x2c06 # macro
regGUS_IO_RD_PRI_QUEUING_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_QUEUING = 0x2c07 # macro
regGUS_IO_WR_PRI_QUEUING_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_FIXED = 0x2c08 # macro
regGUS_IO_RD_PRI_FIXED_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_FIXED = 0x2c09 # macro
regGUS_IO_WR_PRI_FIXED_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_URGENCY_COEFF = 0x2c0a # macro
regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_URGENCY_COEFF = 0x2c0b # macro
regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_URGENCY_MODE = 0x2c0c # macro
regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_URGENCY_MODE = 0x2c0d # macro
regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_QUANT_PRI1 = 0x2c0e # macro
regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_QUANT_PRI2 = 0x2c0f # macro
regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_QUANT_PRI3 = 0x2c10 # macro
regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_QUANT_PRI4 = 0x2c11 # macro
regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_QUANT_PRI1 = 0x2c12 # macro
regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_QUANT_PRI2 = 0x2c13 # macro
regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_QUANT_PRI3 = 0x2c14 # macro
regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_QUANT_PRI4 = 0x2c15 # macro
regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_QUANT1_PRI1 = 0x2c16 # macro
regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_QUANT1_PRI2 = 0x2c17 # macro
regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_QUANT1_PRI3 = 0x2c18 # macro
regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro
regGUS_IO_RD_PRI_QUANT1_PRI4 = 0x2c19 # macro
regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_QUANT1_PRI1 = 0x2c1a # macro
regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_QUANT1_PRI2 = 0x2c1b # macro
regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_QUANT1_PRI3 = 0x2c1c # macro
regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro
regGUS_IO_WR_PRI_QUANT1_PRI4 = 0x2c1d # macro
regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro
regGUS_DRAM_COMBINE_FLUSH = 0x2c1e # macro
regGUS_DRAM_COMBINE_FLUSH_BASE_IDX = 1 # macro
regGUS_DRAM_COMBINE_RD_WR_EN = 0x2c1f # macro
regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_AGE_RATE = 0x2c20 # macro
regGUS_DRAM_PRI_AGE_RATE_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_AGE_COEFF = 0x2c21 # macro
regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_QUEUING = 0x2c22 # macro
regGUS_DRAM_PRI_QUEUING_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_FIXED = 0x2c23 # macro
regGUS_DRAM_PRI_FIXED_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_URGENCY_COEFF = 0x2c24 # macro
regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_URGENCY_MODE = 0x2c25 # macro
regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_QUANT_PRI1 = 0x2c26 # macro
regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_QUANT_PRI2 = 0x2c27 # macro
regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_QUANT_PRI3 = 0x2c28 # macro
regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_QUANT_PRI4 = 0x2c29 # macro
regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_QUANT_PRI5 = 0x2c2a # macro
regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_QUANT1_PRI1 = 0x2c2b # macro
regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_QUANT1_PRI2 = 0x2c2c # macro
regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_QUANT1_PRI3 = 0x2c2d # macro
regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_QUANT1_PRI4 = 0x2c2e # macro
regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro
regGUS_DRAM_PRI_QUANT1_PRI5 = 0x2c2f # macro
regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX = 1 # macro
regGUS_IO_GROUP_BURST = 0x2c30 # macro
regGUS_IO_GROUP_BURST_BASE_IDX = 1 # macro
regGUS_DRAM_GROUP_BURST = 0x2c31 # macro
regGUS_DRAM_GROUP_BURST_BASE_IDX = 1 # macro
regGUS_SDP_ARB_FINAL = 0x2c32 # macro
regGUS_SDP_ARB_FINAL_BASE_IDX = 1 # macro
regGUS_SDP_QOS_VC_PRIORITY = 0x2c33 # macro
regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX = 1 # macro
regGUS_SDP_CREDITS = 0x2c34 # macro
regGUS_SDP_CREDITS_BASE_IDX = 1 # macro
regGUS_SDP_TAG_RESERVE0 = 0x2c35 # macro
regGUS_SDP_TAG_RESERVE0_BASE_IDX = 1 # macro
regGUS_SDP_TAG_RESERVE1 = 0x2c36 # macro
regGUS_SDP_TAG_RESERVE1_BASE_IDX = 1 # macro
regGUS_SDP_VCC_RESERVE0 = 0x2c37 # macro
regGUS_SDP_VCC_RESERVE0_BASE_IDX = 1 # macro
regGUS_SDP_VCC_RESERVE1 = 0x2c38 # macro
regGUS_SDP_VCC_RESERVE1_BASE_IDX = 1 # macro
regGUS_SDP_VCD_RESERVE0 = 0x2c39 # macro
regGUS_SDP_VCD_RESERVE0_BASE_IDX = 1 # macro
regGUS_SDP_VCD_RESERVE1 = 0x2c3a # macro
regGUS_SDP_VCD_RESERVE1_BASE_IDX = 1 # macro
regGUS_SDP_REQ_CNTL = 0x2c3b # macro
regGUS_SDP_REQ_CNTL_BASE_IDX = 1 # macro
regGUS_MISC = 0x2c3c # macro
regGUS_MISC_BASE_IDX = 1 # macro
regGUS_LATENCY_SAMPLING = 0x2c3d # macro
regGUS_LATENCY_SAMPLING_BASE_IDX = 1 # macro
regGUS_ERR_STATUS = 0x2c3e # macro
regGUS_ERR_STATUS_BASE_IDX = 1 # macro
regGUS_MISC2 = 0x2c3f # macro
regGUS_MISC2_BASE_IDX = 1 # macro
regGUS_SDP_ENABLE = 0x2c45 # macro
regGUS_SDP_ENABLE_BASE_IDX = 1 # macro
regGUS_L1_CH0_CMD_IN = 0x2c46 # macro
regGUS_L1_CH0_CMD_IN_BASE_IDX = 1 # macro
regGUS_L1_CH0_CMD_OUT = 0x2c47 # macro
regGUS_L1_CH0_CMD_OUT_BASE_IDX = 1 # macro
regGUS_L1_CH0_DATA_IN = 0x2c48 # macro
regGUS_L1_CH0_DATA_IN_BASE_IDX = 1 # macro
regGUS_L1_CH0_DATA_OUT = 0x2c49 # macro
regGUS_L1_CH0_DATA_OUT_BASE_IDX = 1 # macro
regGUS_L1_CH0_DATA_U_IN = 0x2c4a # macro
regGUS_L1_CH0_DATA_U_IN_BASE_IDX = 1 # macro
regGUS_L1_CH0_DATA_U_OUT = 0x2c4b # macro
regGUS_L1_CH0_DATA_U_OUT_BASE_IDX = 1 # macro
regGUS_L1_CH1_CMD_IN = 0x2c4c # macro
regGUS_L1_CH1_CMD_IN_BASE_IDX = 1 # macro
regGUS_L1_CH1_CMD_OUT = 0x2c4d # macro
regGUS_L1_CH1_CMD_OUT_BASE_IDX = 1 # macro
regGUS_L1_CH1_DATA_IN = 0x2c4e # macro
regGUS_L1_CH1_DATA_IN_BASE_IDX = 1 # macro
regGUS_L1_CH1_DATA_OUT = 0x2c4f # macro
regGUS_L1_CH1_DATA_OUT_BASE_IDX = 1 # macro
regGUS_L1_CH1_DATA_U_IN = 0x2c50 # macro
regGUS_L1_CH1_DATA_U_IN_BASE_IDX = 1 # macro
regGUS_L1_CH1_DATA_U_OUT = 0x2c51 # macro
regGUS_L1_CH1_DATA_U_OUT_BASE_IDX = 1 # macro
regGUS_L1_SA0_CMD_IN = 0x2c52 # macro
regGUS_L1_SA0_CMD_IN_BASE_IDX = 1 # macro
regGUS_L1_SA0_CMD_OUT = 0x2c53 # macro
regGUS_L1_SA0_CMD_OUT_BASE_IDX = 1 # macro
regGUS_L1_SA0_DATA_IN = 0x2c54 # macro
regGUS_L1_SA0_DATA_IN_BASE_IDX = 1 # macro
regGUS_L1_SA0_DATA_OUT = 0x2c55 # macro
regGUS_L1_SA0_DATA_OUT_BASE_IDX = 1 # macro
regGUS_L1_SA0_DATA_U_IN = 0x2c56 # macro
regGUS_L1_SA0_DATA_U_IN_BASE_IDX = 1 # macro
regGUS_L1_SA0_DATA_U_OUT = 0x2c57 # macro
regGUS_L1_SA0_DATA_U_OUT_BASE_IDX = 1 # macro
regGUS_L1_SA1_CMD_IN = 0x2c58 # macro
regGUS_L1_SA1_CMD_IN_BASE_IDX = 1 # macro
regGUS_L1_SA1_CMD_OUT = 0x2c59 # macro
regGUS_L1_SA1_CMD_OUT_BASE_IDX = 1 # macro
regGUS_L1_SA1_DATA_IN = 0x2c5a # macro
regGUS_L1_SA1_DATA_IN_BASE_IDX = 1 # macro
regGUS_L1_SA1_DATA_OUT = 0x2c5b # macro
regGUS_L1_SA1_DATA_OUT_BASE_IDX = 1 # macro
regGUS_L1_SA1_DATA_U_IN = 0x2c5c # macro
regGUS_L1_SA1_DATA_U_IN_BASE_IDX = 1 # macro
regGUS_L1_SA1_DATA_U_OUT = 0x2c5d # macro
regGUS_L1_SA1_DATA_U_OUT_BASE_IDX = 1 # macro
regGUS_L1_SA2_CMD_IN = 0x2c5e # macro
regGUS_L1_SA2_CMD_IN_BASE_IDX = 1 # macro
regGUS_L1_SA2_CMD_OUT = 0x2c5f # macro
regGUS_L1_SA2_CMD_OUT_BASE_IDX = 1 # macro
regGUS_L1_SA2_DATA_IN = 0x2c60 # macro
regGUS_L1_SA2_DATA_IN_BASE_IDX = 1 # macro
regGUS_L1_SA2_DATA_OUT = 0x2c61 # macro
regGUS_L1_SA2_DATA_OUT_BASE_IDX = 1 # macro
regGUS_L1_SA2_DATA_U_IN = 0x2c62 # macro
regGUS_L1_SA2_DATA_U_IN_BASE_IDX = 1 # macro
regGUS_L1_SA2_DATA_U_OUT = 0x2c63 # macro
regGUS_L1_SA2_DATA_U_OUT_BASE_IDX = 1 # macro
regGUS_L1_SA3_CMD_IN = 0x2c64 # macro
regGUS_L1_SA3_CMD_IN_BASE_IDX = 1 # macro
regGUS_L1_SA3_CMD_OUT = 0x2c65 # macro
regGUS_L1_SA3_CMD_OUT_BASE_IDX = 1 # macro
regGUS_L1_SA3_DATA_IN = 0x2c66 # macro
regGUS_L1_SA3_DATA_IN_BASE_IDX = 1 # macro
regGUS_L1_SA3_DATA_OUT = 0x2c67 # macro
regGUS_L1_SA3_DATA_OUT_BASE_IDX = 1 # macro
regGUS_L1_SA3_DATA_U_IN = 0x2c68 # macro
regGUS_L1_SA3_DATA_U_IN_BASE_IDX = 1 # macro
regGUS_L1_SA3_DATA_U_OUT = 0x2c69 # macro
regGUS_L1_SA3_DATA_U_OUT_BASE_IDX = 1 # macro
regGUS_MISC3 = 0x2c6a # macro
regGUS_MISC3_BASE_IDX = 1 # macro
regGUS_WRRSP_FIFO_CNTL = 0x2c6b # macro
regGUS_WRRSP_FIFO_CNTL_BASE_IDX = 1 # macro
regDB_RENDER_CONTROL = 0x0000 # macro
regDB_RENDER_CONTROL_BASE_IDX = 1 # macro
regDB_COUNT_CONTROL = 0x0001 # macro
regDB_COUNT_CONTROL_BASE_IDX = 1 # macro
regDB_DEPTH_VIEW = 0x0002 # macro
regDB_DEPTH_VIEW_BASE_IDX = 1 # macro
regDB_RENDER_OVERRIDE = 0x0003 # macro
regDB_RENDER_OVERRIDE_BASE_IDX = 1 # macro
regDB_RENDER_OVERRIDE2 = 0x0004 # macro
regDB_RENDER_OVERRIDE2_BASE_IDX = 1 # macro
regDB_HTILE_DATA_BASE = 0x0005 # macro
regDB_HTILE_DATA_BASE_BASE_IDX = 1 # macro
regDB_DEPTH_SIZE_XY = 0x0007 # macro
regDB_DEPTH_SIZE_XY_BASE_IDX = 1 # macro
regDB_DEPTH_BOUNDS_MIN = 0x0008 # macro
regDB_DEPTH_BOUNDS_MIN_BASE_IDX = 1 # macro
regDB_DEPTH_BOUNDS_MAX = 0x0009 # macro
regDB_DEPTH_BOUNDS_MAX_BASE_IDX = 1 # macro
regDB_STENCIL_CLEAR = 0x000a # macro
regDB_STENCIL_CLEAR_BASE_IDX = 1 # macro
regDB_DEPTH_CLEAR = 0x000b # macro
regDB_DEPTH_CLEAR_BASE_IDX = 1 # macro
regPA_SC_SCREEN_SCISSOR_TL = 0x000c # macro
regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX = 1 # macro
regPA_SC_SCREEN_SCISSOR_BR = 0x000d # macro
regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX = 1 # macro
regDB_RESERVED_REG_2 = 0x000f # macro
regDB_RESERVED_REG_2_BASE_IDX = 1 # macro
regDB_Z_INFO = 0x0010 # macro
regDB_Z_INFO_BASE_IDX = 1 # macro
regDB_STENCIL_INFO = 0x0011 # macro
regDB_STENCIL_INFO_BASE_IDX = 1 # macro
regDB_Z_READ_BASE = 0x0012 # macro
regDB_Z_READ_BASE_BASE_IDX = 1 # macro
regDB_STENCIL_READ_BASE = 0x0013 # macro
regDB_STENCIL_READ_BASE_BASE_IDX = 1 # macro
regDB_Z_WRITE_BASE = 0x0014 # macro
regDB_Z_WRITE_BASE_BASE_IDX = 1 # macro
regDB_STENCIL_WRITE_BASE = 0x0015 # macro
regDB_STENCIL_WRITE_BASE_BASE_IDX = 1 # macro
regDB_RESERVED_REG_1 = 0x0016 # macro
regDB_RESERVED_REG_1_BASE_IDX = 1 # macro
regDB_RESERVED_REG_3 = 0x0017 # macro
regDB_RESERVED_REG_3_BASE_IDX = 1 # macro
regDB_Z_READ_BASE_HI = 0x001a # macro
regDB_Z_READ_BASE_HI_BASE_IDX = 1 # macro
regDB_STENCIL_READ_BASE_HI = 0x001b # macro
regDB_STENCIL_READ_BASE_HI_BASE_IDX = 1 # macro
regDB_Z_WRITE_BASE_HI = 0x001c # macro
regDB_Z_WRITE_BASE_HI_BASE_IDX = 1 # macro
regDB_STENCIL_WRITE_BASE_HI = 0x001d # macro
regDB_STENCIL_WRITE_BASE_HI_BASE_IDX = 1 # macro
regDB_HTILE_DATA_BASE_HI = 0x001e # macro
regDB_HTILE_DATA_BASE_HI_BASE_IDX = 1 # macro
regDB_RMI_L2_CACHE_CONTROL = 0x001f # macro
regDB_RMI_L2_CACHE_CONTROL_BASE_IDX = 1 # macro
regTA_BC_BASE_ADDR = 0x0020 # macro
regTA_BC_BASE_ADDR_BASE_IDX = 1 # macro
regTA_BC_BASE_ADDR_HI = 0x0021 # macro
regTA_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro
regCOHER_DEST_BASE_HI_0 = 0x007a # macro
regCOHER_DEST_BASE_HI_0_BASE_IDX = 1 # macro
regCOHER_DEST_BASE_HI_1 = 0x007b # macro
regCOHER_DEST_BASE_HI_1_BASE_IDX = 1 # macro
regCOHER_DEST_BASE_HI_2 = 0x007c # macro
regCOHER_DEST_BASE_HI_2_BASE_IDX = 1 # macro
regCOHER_DEST_BASE_HI_3 = 0x007d # macro
regCOHER_DEST_BASE_HI_3_BASE_IDX = 1 # macro
regCOHER_DEST_BASE_2 = 0x007e # macro
regCOHER_DEST_BASE_2_BASE_IDX = 1 # macro
regCOHER_DEST_BASE_3 = 0x007f # macro
regCOHER_DEST_BASE_3_BASE_IDX = 1 # macro
regPA_SC_WINDOW_OFFSET = 0x0080 # macro
regPA_SC_WINDOW_OFFSET_BASE_IDX = 1 # macro
regPA_SC_WINDOW_SCISSOR_TL = 0x0081 # macro
regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX = 1 # macro
regPA_SC_WINDOW_SCISSOR_BR = 0x0082 # macro
regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX = 1 # macro
regPA_SC_CLIPRECT_RULE = 0x0083 # macro
regPA_SC_CLIPRECT_RULE_BASE_IDX = 1 # macro
regPA_SC_CLIPRECT_0_TL = 0x0084 # macro
regPA_SC_CLIPRECT_0_TL_BASE_IDX = 1 # macro
regPA_SC_CLIPRECT_0_BR = 0x0085 # macro
regPA_SC_CLIPRECT_0_BR_BASE_IDX = 1 # macro
regPA_SC_CLIPRECT_1_TL = 0x0086 # macro
regPA_SC_CLIPRECT_1_TL_BASE_IDX = 1 # macro
regPA_SC_CLIPRECT_1_BR = 0x0087 # macro
regPA_SC_CLIPRECT_1_BR_BASE_IDX = 1 # macro
regPA_SC_CLIPRECT_2_TL = 0x0088 # macro
regPA_SC_CLIPRECT_2_TL_BASE_IDX = 1 # macro
regPA_SC_CLIPRECT_2_BR = 0x0089 # macro
regPA_SC_CLIPRECT_2_BR_BASE_IDX = 1 # macro
regPA_SC_CLIPRECT_3_TL = 0x008a # macro
regPA_SC_CLIPRECT_3_TL_BASE_IDX = 1 # macro
regPA_SC_CLIPRECT_3_BR = 0x008b # macro
regPA_SC_CLIPRECT_3_BR_BASE_IDX = 1 # macro
regPA_SC_EDGERULE = 0x008c # macro
regPA_SC_EDGERULE_BASE_IDX = 1 # macro
regPA_SU_HARDWARE_SCREEN_OFFSET = 0x008d # macro
regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX = 1 # macro
regCB_TARGET_MASK = 0x008e # macro
regCB_TARGET_MASK_BASE_IDX = 1 # macro
regCB_SHADER_MASK = 0x008f # macro
regCB_SHADER_MASK_BASE_IDX = 1 # macro
regPA_SC_GENERIC_SCISSOR_TL = 0x0090 # macro
regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX = 1 # macro
regPA_SC_GENERIC_SCISSOR_BR = 0x0091 # macro
regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX = 1 # macro
regCOHER_DEST_BASE_0 = 0x0092 # macro
regCOHER_DEST_BASE_0_BASE_IDX = 1 # macro
regCOHER_DEST_BASE_1 = 0x0093 # macro
regCOHER_DEST_BASE_1_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_0_TL = 0x0094 # macro
regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_0_BR = 0x0095 # macro
regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_1_TL = 0x0096 # macro
regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_1_BR = 0x0097 # macro
regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_2_TL = 0x0098 # macro
regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_2_BR = 0x0099 # macro
regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_3_TL = 0x009a # macro
regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_3_BR = 0x009b # macro
regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_4_TL = 0x009c # macro
regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_4_BR = 0x009d # macro
regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_5_TL = 0x009e # macro
regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_5_BR = 0x009f # macro
regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_6_TL = 0x00a0 # macro
regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_6_BR = 0x00a1 # macro
regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_7_TL = 0x00a2 # macro
regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_7_BR = 0x00a3 # macro
regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_8_TL = 0x00a4 # macro
regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_8_BR = 0x00a5 # macro
regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_9_TL = 0x00a6 # macro
regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_9_BR = 0x00a7 # macro
regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_10_TL = 0x00a8 # macro
regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_10_BR = 0x00a9 # macro
regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_11_TL = 0x00aa # macro
regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_11_BR = 0x00ab # macro
regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_12_TL = 0x00ac # macro
regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_12_BR = 0x00ad # macro
regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_13_TL = 0x00ae # macro
regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_13_BR = 0x00af # macro
regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_14_TL = 0x00b0 # macro
regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_14_BR = 0x00b1 # macro
regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_15_TL = 0x00b2 # macro
regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX = 1 # macro
regPA_SC_VPORT_SCISSOR_15_BR = 0x00b3 # macro
regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_0 = 0x00b4 # macro
regPA_SC_VPORT_ZMIN_0_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_0 = 0x00b5 # macro
regPA_SC_VPORT_ZMAX_0_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_1 = 0x00b6 # macro
regPA_SC_VPORT_ZMIN_1_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_1 = 0x00b7 # macro
regPA_SC_VPORT_ZMAX_1_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_2 = 0x00b8 # macro
regPA_SC_VPORT_ZMIN_2_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_2 = 0x00b9 # macro
regPA_SC_VPORT_ZMAX_2_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_3 = 0x00ba # macro
regPA_SC_VPORT_ZMIN_3_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_3 = 0x00bb # macro
regPA_SC_VPORT_ZMAX_3_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_4 = 0x00bc # macro
regPA_SC_VPORT_ZMIN_4_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_4 = 0x00bd # macro
regPA_SC_VPORT_ZMAX_4_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_5 = 0x00be # macro
regPA_SC_VPORT_ZMIN_5_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_5 = 0x00bf # macro
regPA_SC_VPORT_ZMAX_5_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_6 = 0x00c0 # macro
regPA_SC_VPORT_ZMIN_6_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_6 = 0x00c1 # macro
regPA_SC_VPORT_ZMAX_6_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_7 = 0x00c2 # macro
regPA_SC_VPORT_ZMIN_7_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_7 = 0x00c3 # macro
regPA_SC_VPORT_ZMAX_7_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_8 = 0x00c4 # macro
regPA_SC_VPORT_ZMIN_8_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_8 = 0x00c5 # macro
regPA_SC_VPORT_ZMAX_8_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_9 = 0x00c6 # macro
regPA_SC_VPORT_ZMIN_9_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_9 = 0x00c7 # macro
regPA_SC_VPORT_ZMAX_9_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_10 = 0x00c8 # macro
regPA_SC_VPORT_ZMIN_10_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_10 = 0x00c9 # macro
regPA_SC_VPORT_ZMAX_10_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_11 = 0x00ca # macro
regPA_SC_VPORT_ZMIN_11_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_11 = 0x00cb # macro
regPA_SC_VPORT_ZMAX_11_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_12 = 0x00cc # macro
regPA_SC_VPORT_ZMIN_12_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_12 = 0x00cd # macro
regPA_SC_VPORT_ZMAX_12_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_13 = 0x00ce # macro
regPA_SC_VPORT_ZMIN_13_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_13 = 0x00cf # macro
regPA_SC_VPORT_ZMAX_13_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_14 = 0x00d0 # macro
regPA_SC_VPORT_ZMIN_14_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_14 = 0x00d1 # macro
regPA_SC_VPORT_ZMAX_14_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMIN_15 = 0x00d2 # macro
regPA_SC_VPORT_ZMIN_15_BASE_IDX = 1 # macro
regPA_SC_VPORT_ZMAX_15 = 0x00d3 # macro
regPA_SC_VPORT_ZMAX_15_BASE_IDX = 1 # macro
regPA_SC_RASTER_CONFIG = 0x00d4 # macro
regPA_SC_RASTER_CONFIG_BASE_IDX = 1 # macro
regPA_SC_RASTER_CONFIG_1 = 0x00d5 # macro
regPA_SC_RASTER_CONFIG_1_BASE_IDX = 1 # macro
regPA_SC_SCREEN_EXTENT_CONTROL = 0x00d6 # macro
regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX = 1 # macro
regPA_SC_TILE_STEERING_OVERRIDE = 0x00d7 # macro
regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX = 1 # macro
regCP_PERFMON_CNTX_CNTL = 0x00d8 # macro
regCP_PERFMON_CNTX_CNTL_BASE_IDX = 1 # macro
regCP_PIPEID = 0x00d9 # macro
regCP_PIPEID_BASE_IDX = 1 # macro
regCP_RINGID = 0x00d9 # macro
regCP_RINGID_BASE_IDX = 1 # macro
regCP_VMID = 0x00da # macro
regCP_VMID_BASE_IDX = 1 # macro
regCONTEXT_RESERVED_REG0 = 0x00db # macro
regCONTEXT_RESERVED_REG0_BASE_IDX = 1 # macro
regCONTEXT_RESERVED_REG1 = 0x00dc # macro
regCONTEXT_RESERVED_REG1_BASE_IDX = 1 # macro
regPA_SC_VRS_OVERRIDE_CNTL = 0x00f4 # macro
regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX = 1 # macro
regPA_SC_VRS_RATE_FEEDBACK_BASE = 0x00f5 # macro
regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX = 1 # macro
regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT = 0x00f6 # macro
regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX = 1 # macro
regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY = 0x00f7 # macro
regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX = 1 # macro
regPA_SC_VRS_RATE_CACHE_CNTL = 0x00f9 # macro
regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX = 1 # macro
regPA_SC_VRS_RATE_BASE = 0x00fc # macro
regPA_SC_VRS_RATE_BASE_BASE_IDX = 1 # macro
regPA_SC_VRS_RATE_BASE_EXT = 0x00fd # macro
regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX = 1 # macro
regPA_SC_VRS_RATE_SIZE_XY = 0x00fe # macro
regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX = 1 # macro
regVGT_MULTI_PRIM_IB_RESET_INDX = 0x0103 # macro
regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX = 1 # macro
regCB_RMI_GL2_CACHE_CONTROL = 0x0104 # macro
regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX = 1 # macro
regCB_BLEND_RED = 0x0105 # macro
regCB_BLEND_RED_BASE_IDX = 1 # macro
regCB_BLEND_GREEN = 0x0106 # macro
regCB_BLEND_GREEN_BASE_IDX = 1 # macro
regCB_BLEND_BLUE = 0x0107 # macro
regCB_BLEND_BLUE_BASE_IDX = 1 # macro
regCB_BLEND_ALPHA = 0x0108 # macro
regCB_BLEND_ALPHA_BASE_IDX = 1 # macro
regCB_FDCC_CONTROL = 0x0109 # macro
regCB_FDCC_CONTROL_BASE_IDX = 1 # macro
regCB_COVERAGE_OUT_CONTROL = 0x010a # macro
regCB_COVERAGE_OUT_CONTROL_BASE_IDX = 1 # macro
regDB_STENCIL_CONTROL = 0x010b # macro
regDB_STENCIL_CONTROL_BASE_IDX = 1 # macro
regDB_STENCILREFMASK = 0x010c # macro
regDB_STENCILREFMASK_BASE_IDX = 1 # macro
regDB_STENCILREFMASK_BF = 0x010d # macro
regDB_STENCILREFMASK_BF_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE = 0x010f # macro
regPA_CL_VPORT_XSCALE_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET = 0x0110 # macro
regPA_CL_VPORT_XOFFSET_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE = 0x0111 # macro
regPA_CL_VPORT_YSCALE_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET = 0x0112 # macro
regPA_CL_VPORT_YOFFSET_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE = 0x0113 # macro
regPA_CL_VPORT_ZSCALE_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET = 0x0114 # macro
regPA_CL_VPORT_ZOFFSET_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_1 = 0x0115 # macro
regPA_CL_VPORT_XSCALE_1_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_1 = 0x0116 # macro
regPA_CL_VPORT_XOFFSET_1_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_1 = 0x0117 # macro
regPA_CL_VPORT_YSCALE_1_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_1 = 0x0118 # macro
regPA_CL_VPORT_YOFFSET_1_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_1 = 0x0119 # macro
regPA_CL_VPORT_ZSCALE_1_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_1 = 0x011a # macro
regPA_CL_VPORT_ZOFFSET_1_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_2 = 0x011b # macro
regPA_CL_VPORT_XSCALE_2_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_2 = 0x011c # macro
regPA_CL_VPORT_XOFFSET_2_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_2 = 0x011d # macro
regPA_CL_VPORT_YSCALE_2_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_2 = 0x011e # macro
regPA_CL_VPORT_YOFFSET_2_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_2 = 0x011f # macro
regPA_CL_VPORT_ZSCALE_2_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_2 = 0x0120 # macro
regPA_CL_VPORT_ZOFFSET_2_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_3 = 0x0121 # macro
regPA_CL_VPORT_XSCALE_3_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_3 = 0x0122 # macro
regPA_CL_VPORT_XOFFSET_3_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_3 = 0x0123 # macro
regPA_CL_VPORT_YSCALE_3_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_3 = 0x0124 # macro
regPA_CL_VPORT_YOFFSET_3_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_3 = 0x0125 # macro
regPA_CL_VPORT_ZSCALE_3_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_3 = 0x0126 # macro
regPA_CL_VPORT_ZOFFSET_3_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_4 = 0x0127 # macro
regPA_CL_VPORT_XSCALE_4_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_4 = 0x0128 # macro
regPA_CL_VPORT_XOFFSET_4_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_4 = 0x0129 # macro
regPA_CL_VPORT_YSCALE_4_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_4 = 0x012a # macro
regPA_CL_VPORT_YOFFSET_4_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_4 = 0x012b # macro
regPA_CL_VPORT_ZSCALE_4_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_4 = 0x012c # macro
regPA_CL_VPORT_ZOFFSET_4_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_5 = 0x012d # macro
regPA_CL_VPORT_XSCALE_5_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_5 = 0x012e # macro
regPA_CL_VPORT_XOFFSET_5_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_5 = 0x012f # macro
regPA_CL_VPORT_YSCALE_5_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_5 = 0x0130 # macro
regPA_CL_VPORT_YOFFSET_5_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_5 = 0x0131 # macro
regPA_CL_VPORT_ZSCALE_5_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_5 = 0x0132 # macro
regPA_CL_VPORT_ZOFFSET_5_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_6 = 0x0133 # macro
regPA_CL_VPORT_XSCALE_6_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_6 = 0x0134 # macro
regPA_CL_VPORT_XOFFSET_6_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_6 = 0x0135 # macro
regPA_CL_VPORT_YSCALE_6_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_6 = 0x0136 # macro
regPA_CL_VPORT_YOFFSET_6_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_6 = 0x0137 # macro
regPA_CL_VPORT_ZSCALE_6_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_6 = 0x0138 # macro
regPA_CL_VPORT_ZOFFSET_6_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_7 = 0x0139 # macro
regPA_CL_VPORT_XSCALE_7_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_7 = 0x013a # macro
regPA_CL_VPORT_XOFFSET_7_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_7 = 0x013b # macro
regPA_CL_VPORT_YSCALE_7_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_7 = 0x013c # macro
regPA_CL_VPORT_YOFFSET_7_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_7 = 0x013d # macro
regPA_CL_VPORT_ZSCALE_7_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_7 = 0x013e # macro
regPA_CL_VPORT_ZOFFSET_7_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_8 = 0x013f # macro
regPA_CL_VPORT_XSCALE_8_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_8 = 0x0140 # macro
regPA_CL_VPORT_XOFFSET_8_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_8 = 0x0141 # macro
regPA_CL_VPORT_YSCALE_8_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_8 = 0x0142 # macro
regPA_CL_VPORT_YOFFSET_8_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_8 = 0x0143 # macro
regPA_CL_VPORT_ZSCALE_8_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_8 = 0x0144 # macro
regPA_CL_VPORT_ZOFFSET_8_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_9 = 0x0145 # macro
regPA_CL_VPORT_XSCALE_9_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_9 = 0x0146 # macro
regPA_CL_VPORT_XOFFSET_9_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_9 = 0x0147 # macro
regPA_CL_VPORT_YSCALE_9_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_9 = 0x0148 # macro
regPA_CL_VPORT_YOFFSET_9_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_9 = 0x0149 # macro
regPA_CL_VPORT_ZSCALE_9_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_9 = 0x014a # macro
regPA_CL_VPORT_ZOFFSET_9_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_10 = 0x014b # macro
regPA_CL_VPORT_XSCALE_10_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_10 = 0x014c # macro
regPA_CL_VPORT_XOFFSET_10_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_10 = 0x014d # macro
regPA_CL_VPORT_YSCALE_10_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_10 = 0x014e # macro
regPA_CL_VPORT_YOFFSET_10_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_10 = 0x014f # macro
regPA_CL_VPORT_ZSCALE_10_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_10 = 0x0150 # macro
regPA_CL_VPORT_ZOFFSET_10_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_11 = 0x0151 # macro
regPA_CL_VPORT_XSCALE_11_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_11 = 0x0152 # macro
regPA_CL_VPORT_XOFFSET_11_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_11 = 0x0153 # macro
regPA_CL_VPORT_YSCALE_11_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_11 = 0x0154 # macro
regPA_CL_VPORT_YOFFSET_11_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_11 = 0x0155 # macro
regPA_CL_VPORT_ZSCALE_11_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_11 = 0x0156 # macro
regPA_CL_VPORT_ZOFFSET_11_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_12 = 0x0157 # macro
regPA_CL_VPORT_XSCALE_12_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_12 = 0x0158 # macro
regPA_CL_VPORT_XOFFSET_12_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_12 = 0x0159 # macro
regPA_CL_VPORT_YSCALE_12_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_12 = 0x015a # macro
regPA_CL_VPORT_YOFFSET_12_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_12 = 0x015b # macro
regPA_CL_VPORT_ZSCALE_12_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_12 = 0x015c # macro
regPA_CL_VPORT_ZOFFSET_12_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_13 = 0x015d # macro
regPA_CL_VPORT_XSCALE_13_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_13 = 0x015e # macro
regPA_CL_VPORT_XOFFSET_13_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_13 = 0x015f # macro
regPA_CL_VPORT_YSCALE_13_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_13 = 0x0160 # macro
regPA_CL_VPORT_YOFFSET_13_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_13 = 0x0161 # macro
regPA_CL_VPORT_ZSCALE_13_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_13 = 0x0162 # macro
regPA_CL_VPORT_ZOFFSET_13_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_14 = 0x0163 # macro
regPA_CL_VPORT_XSCALE_14_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_14 = 0x0164 # macro
regPA_CL_VPORT_XOFFSET_14_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_14 = 0x0165 # macro
regPA_CL_VPORT_YSCALE_14_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_14 = 0x0166 # macro
regPA_CL_VPORT_YOFFSET_14_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_14 = 0x0167 # macro
regPA_CL_VPORT_ZSCALE_14_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_14 = 0x0168 # macro
regPA_CL_VPORT_ZOFFSET_14_BASE_IDX = 1 # macro
regPA_CL_VPORT_XSCALE_15 = 0x0169 # macro
regPA_CL_VPORT_XSCALE_15_BASE_IDX = 1 # macro
regPA_CL_VPORT_XOFFSET_15 = 0x016a # macro
regPA_CL_VPORT_XOFFSET_15_BASE_IDX = 1 # macro
regPA_CL_VPORT_YSCALE_15 = 0x016b # macro
regPA_CL_VPORT_YSCALE_15_BASE_IDX = 1 # macro
regPA_CL_VPORT_YOFFSET_15 = 0x016c # macro
regPA_CL_VPORT_YOFFSET_15_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZSCALE_15 = 0x016d # macro
regPA_CL_VPORT_ZSCALE_15_BASE_IDX = 1 # macro
regPA_CL_VPORT_ZOFFSET_15 = 0x016e # macro
regPA_CL_VPORT_ZOFFSET_15_BASE_IDX = 1 # macro
regPA_CL_UCP_0_X = 0x016f # macro
regPA_CL_UCP_0_X_BASE_IDX = 1 # macro
regPA_CL_UCP_0_Y = 0x0170 # macro
regPA_CL_UCP_0_Y_BASE_IDX = 1 # macro
regPA_CL_UCP_0_Z = 0x0171 # macro
regPA_CL_UCP_0_Z_BASE_IDX = 1 # macro
regPA_CL_UCP_0_W = 0x0172 # macro
regPA_CL_UCP_0_W_BASE_IDX = 1 # macro
regPA_CL_UCP_1_X = 0x0173 # macro
regPA_CL_UCP_1_X_BASE_IDX = 1 # macro
regPA_CL_UCP_1_Y = 0x0174 # macro
regPA_CL_UCP_1_Y_BASE_IDX = 1 # macro
regPA_CL_UCP_1_Z = 0x0175 # macro
regPA_CL_UCP_1_Z_BASE_IDX = 1 # macro
regPA_CL_UCP_1_W = 0x0176 # macro
regPA_CL_UCP_1_W_BASE_IDX = 1 # macro
regPA_CL_UCP_2_X = 0x0177 # macro
regPA_CL_UCP_2_X_BASE_IDX = 1 # macro
regPA_CL_UCP_2_Y = 0x0178 # macro
regPA_CL_UCP_2_Y_BASE_IDX = 1 # macro
regPA_CL_UCP_2_Z = 0x0179 # macro
regPA_CL_UCP_2_Z_BASE_IDX = 1 # macro
regPA_CL_UCP_2_W = 0x017a # macro
regPA_CL_UCP_2_W_BASE_IDX = 1 # macro
regPA_CL_UCP_3_X = 0x017b # macro
regPA_CL_UCP_3_X_BASE_IDX = 1 # macro
regPA_CL_UCP_3_Y = 0x017c # macro
regPA_CL_UCP_3_Y_BASE_IDX = 1 # macro
regPA_CL_UCP_3_Z = 0x017d # macro
regPA_CL_UCP_3_Z_BASE_IDX = 1 # macro
regPA_CL_UCP_3_W = 0x017e # macro
regPA_CL_UCP_3_W_BASE_IDX = 1 # macro
regPA_CL_UCP_4_X = 0x017f # macro
regPA_CL_UCP_4_X_BASE_IDX = 1 # macro
regPA_CL_UCP_4_Y = 0x0180 # macro
regPA_CL_UCP_4_Y_BASE_IDX = 1 # macro
regPA_CL_UCP_4_Z = 0x0181 # macro
regPA_CL_UCP_4_Z_BASE_IDX = 1 # macro
regPA_CL_UCP_4_W = 0x0182 # macro
regPA_CL_UCP_4_W_BASE_IDX = 1 # macro
regPA_CL_UCP_5_X = 0x0183 # macro
regPA_CL_UCP_5_X_BASE_IDX = 1 # macro
regPA_CL_UCP_5_Y = 0x0184 # macro
regPA_CL_UCP_5_Y_BASE_IDX = 1 # macro
regPA_CL_UCP_5_Z = 0x0185 # macro
regPA_CL_UCP_5_Z_BASE_IDX = 1 # macro
regPA_CL_UCP_5_W = 0x0186 # macro
regPA_CL_UCP_5_W_BASE_IDX = 1 # macro
regPA_CL_PROG_NEAR_CLIP_Z = 0x0187 # macro
regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX = 1 # macro
regPA_RATE_CNTL = 0x0188 # macro
regPA_RATE_CNTL_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_0 = 0x0191 # macro
regSPI_PS_INPUT_CNTL_0_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_1 = 0x0192 # macro
regSPI_PS_INPUT_CNTL_1_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_2 = 0x0193 # macro
regSPI_PS_INPUT_CNTL_2_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_3 = 0x0194 # macro
regSPI_PS_INPUT_CNTL_3_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_4 = 0x0195 # macro
regSPI_PS_INPUT_CNTL_4_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_5 = 0x0196 # macro
regSPI_PS_INPUT_CNTL_5_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_6 = 0x0197 # macro
regSPI_PS_INPUT_CNTL_6_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_7 = 0x0198 # macro
regSPI_PS_INPUT_CNTL_7_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_8 = 0x0199 # macro
regSPI_PS_INPUT_CNTL_8_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_9 = 0x019a # macro
regSPI_PS_INPUT_CNTL_9_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_10 = 0x019b # macro
regSPI_PS_INPUT_CNTL_10_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_11 = 0x019c # macro
regSPI_PS_INPUT_CNTL_11_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_12 = 0x019d # macro
regSPI_PS_INPUT_CNTL_12_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_13 = 0x019e # macro
regSPI_PS_INPUT_CNTL_13_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_14 = 0x019f # macro
regSPI_PS_INPUT_CNTL_14_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_15 = 0x01a0 # macro
regSPI_PS_INPUT_CNTL_15_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_16 = 0x01a1 # macro
regSPI_PS_INPUT_CNTL_16_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_17 = 0x01a2 # macro
regSPI_PS_INPUT_CNTL_17_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_18 = 0x01a3 # macro
regSPI_PS_INPUT_CNTL_18_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_19 = 0x01a4 # macro
regSPI_PS_INPUT_CNTL_19_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_20 = 0x01a5 # macro
regSPI_PS_INPUT_CNTL_20_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_21 = 0x01a6 # macro
regSPI_PS_INPUT_CNTL_21_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_22 = 0x01a7 # macro
regSPI_PS_INPUT_CNTL_22_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_23 = 0x01a8 # macro
regSPI_PS_INPUT_CNTL_23_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_24 = 0x01a9 # macro
regSPI_PS_INPUT_CNTL_24_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_25 = 0x01aa # macro
regSPI_PS_INPUT_CNTL_25_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_26 = 0x01ab # macro
regSPI_PS_INPUT_CNTL_26_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_27 = 0x01ac # macro
regSPI_PS_INPUT_CNTL_27_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_28 = 0x01ad # macro
regSPI_PS_INPUT_CNTL_28_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_29 = 0x01ae # macro
regSPI_PS_INPUT_CNTL_29_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_30 = 0x01af # macro
regSPI_PS_INPUT_CNTL_30_BASE_IDX = 1 # macro
regSPI_PS_INPUT_CNTL_31 = 0x01b0 # macro
regSPI_PS_INPUT_CNTL_31_BASE_IDX = 1 # macro
regSPI_VS_OUT_CONFIG = 0x01b1 # macro
regSPI_VS_OUT_CONFIG_BASE_IDX = 1 # macro
regSPI_PS_INPUT_ENA = 0x01b3 # macro
regSPI_PS_INPUT_ENA_BASE_IDX = 1 # macro
regSPI_PS_INPUT_ADDR = 0x01b4 # macro
regSPI_PS_INPUT_ADDR_BASE_IDX = 1 # macro
regSPI_INTERP_CONTROL_0 = 0x01b5 # macro
regSPI_INTERP_CONTROL_0_BASE_IDX = 1 # macro
regSPI_PS_IN_CONTROL = 0x01b6 # macro
regSPI_PS_IN_CONTROL_BASE_IDX = 1 # macro
regSPI_BARYC_CNTL = 0x01b8 # macro
regSPI_BARYC_CNTL_BASE_IDX = 1 # macro
regSPI_TMPRING_SIZE = 0x01ba # macro
regSPI_TMPRING_SIZE_BASE_IDX = 1 # macro
regSPI_GFX_SCRATCH_BASE_LO = 0x01bb # macro
regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX = 1 # macro
regSPI_GFX_SCRATCH_BASE_HI = 0x01bc # macro
regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX = 1 # macro
regSPI_SHADER_IDX_FORMAT = 0x01c2 # macro
regSPI_SHADER_IDX_FORMAT_BASE_IDX = 1 # macro
regSPI_SHADER_POS_FORMAT = 0x01c3 # macro
regSPI_SHADER_POS_FORMAT_BASE_IDX = 1 # macro
regSPI_SHADER_Z_FORMAT = 0x01c4 # macro
regSPI_SHADER_Z_FORMAT_BASE_IDX = 1 # macro
regSPI_SHADER_COL_FORMAT = 0x01c5 # macro
regSPI_SHADER_COL_FORMAT_BASE_IDX = 1 # macro
regSX_PS_DOWNCONVERT_CONTROL = 0x01d4 # macro
regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX = 1 # macro
regSX_PS_DOWNCONVERT = 0x01d5 # macro
regSX_PS_DOWNCONVERT_BASE_IDX = 1 # macro
regSX_BLEND_OPT_EPSILON = 0x01d6 # macro
regSX_BLEND_OPT_EPSILON_BASE_IDX = 1 # macro
regSX_BLEND_OPT_CONTROL = 0x01d7 # macro
regSX_BLEND_OPT_CONTROL_BASE_IDX = 1 # macro
regSX_MRT0_BLEND_OPT = 0x01d8 # macro
regSX_MRT0_BLEND_OPT_BASE_IDX = 1 # macro
regSX_MRT1_BLEND_OPT = 0x01d9 # macro
regSX_MRT1_BLEND_OPT_BASE_IDX = 1 # macro
regSX_MRT2_BLEND_OPT = 0x01da # macro
regSX_MRT2_BLEND_OPT_BASE_IDX = 1 # macro
regSX_MRT3_BLEND_OPT = 0x01db # macro
regSX_MRT3_BLEND_OPT_BASE_IDX = 1 # macro
regSX_MRT4_BLEND_OPT = 0x01dc # macro
regSX_MRT4_BLEND_OPT_BASE_IDX = 1 # macro
regSX_MRT5_BLEND_OPT = 0x01dd # macro
regSX_MRT5_BLEND_OPT_BASE_IDX = 1 # macro
regSX_MRT6_BLEND_OPT = 0x01de # macro
regSX_MRT6_BLEND_OPT_BASE_IDX = 1 # macro
regSX_MRT7_BLEND_OPT = 0x01df # macro
regSX_MRT7_BLEND_OPT_BASE_IDX = 1 # macro
regCB_BLEND0_CONTROL = 0x01e0 # macro
regCB_BLEND0_CONTROL_BASE_IDX = 1 # macro
regCB_BLEND1_CONTROL = 0x01e1 # macro
regCB_BLEND1_CONTROL_BASE_IDX = 1 # macro
regCB_BLEND2_CONTROL = 0x01e2 # macro
regCB_BLEND2_CONTROL_BASE_IDX = 1 # macro
regCB_BLEND3_CONTROL = 0x01e3 # macro
regCB_BLEND3_CONTROL_BASE_IDX = 1 # macro
regCB_BLEND4_CONTROL = 0x01e4 # macro
regCB_BLEND4_CONTROL_BASE_IDX = 1 # macro
regCB_BLEND5_CONTROL = 0x01e5 # macro
regCB_BLEND5_CONTROL_BASE_IDX = 1 # macro
regCB_BLEND6_CONTROL = 0x01e6 # macro
regCB_BLEND6_CONTROL_BASE_IDX = 1 # macro
regCB_BLEND7_CONTROL = 0x01e7 # macro
regCB_BLEND7_CONTROL_BASE_IDX = 1 # macro
regGFX_COPY_STATE = 0x01f4 # macro
regGFX_COPY_STATE_BASE_IDX = 1 # macro
regPA_CL_POINT_X_RAD = 0x01f5 # macro
regPA_CL_POINT_X_RAD_BASE_IDX = 1 # macro
regPA_CL_POINT_Y_RAD = 0x01f6 # macro
regPA_CL_POINT_Y_RAD_BASE_IDX = 1 # macro
regPA_CL_POINT_SIZE = 0x01f7 # macro
regPA_CL_POINT_SIZE_BASE_IDX = 1 # macro
regPA_CL_POINT_CULL_RAD = 0x01f8 # macro
regPA_CL_POINT_CULL_RAD_BASE_IDX = 1 # macro
regVGT_DMA_BASE_HI = 0x01f9 # macro
regVGT_DMA_BASE_HI_BASE_IDX = 1 # macro
regVGT_DMA_BASE = 0x01fa # macro
regVGT_DMA_BASE_BASE_IDX = 1 # macro
regVGT_DRAW_INITIATOR = 0x01fc # macro
regVGT_DRAW_INITIATOR_BASE_IDX = 1 # macro
regVGT_EVENT_ADDRESS_REG = 0x01fe # macro
regVGT_EVENT_ADDRESS_REG_BASE_IDX = 1 # macro
regGE_MAX_OUTPUT_PER_SUBGROUP = 0x01ff # macro
regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX = 1 # macro
regDB_DEPTH_CONTROL = 0x0200 # macro
regDB_DEPTH_CONTROL_BASE_IDX = 1 # macro
regDB_EQAA = 0x0201 # macro
regDB_EQAA_BASE_IDX = 1 # macro
regCB_COLOR_CONTROL = 0x0202 # macro
regCB_COLOR_CONTROL_BASE_IDX = 1 # macro
regDB_SHADER_CONTROL = 0x0203 # macro
regDB_SHADER_CONTROL_BASE_IDX = 1 # macro
regPA_CL_CLIP_CNTL = 0x0204 # macro
regPA_CL_CLIP_CNTL_BASE_IDX = 1 # macro
regPA_SU_SC_MODE_CNTL = 0x0205 # macro
regPA_SU_SC_MODE_CNTL_BASE_IDX = 1 # macro
regPA_CL_VTE_CNTL = 0x0206 # macro
regPA_CL_VTE_CNTL_BASE_IDX = 1 # macro
regPA_CL_VS_OUT_CNTL = 0x0207 # macro
regPA_CL_VS_OUT_CNTL_BASE_IDX = 1 # macro
regPA_CL_NANINF_CNTL = 0x0208 # macro
regPA_CL_NANINF_CNTL_BASE_IDX = 1 # macro
regPA_SU_LINE_STIPPLE_CNTL = 0x0209 # macro
regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX = 1 # macro
regPA_SU_LINE_STIPPLE_SCALE = 0x020a # macro
regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX = 1 # macro
regPA_SU_PRIM_FILTER_CNTL = 0x020b # macro
regPA_SU_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro
regPA_SU_SMALL_PRIM_FILTER_CNTL = 0x020c # macro
regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro
regPA_CL_NGG_CNTL = 0x020e # macro
regPA_CL_NGG_CNTL_BASE_IDX = 1 # macro
regPA_SU_OVER_RASTERIZATION_CNTL = 0x020f # macro
regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX = 1 # macro
regPA_STEREO_CNTL = 0x0210 # macro
regPA_STEREO_CNTL_BASE_IDX = 1 # macro
regPA_STATE_STEREO_X = 0x0211 # macro
regPA_STATE_STEREO_X_BASE_IDX = 1 # macro
regPA_CL_VRS_CNTL = 0x0212 # macro
regPA_CL_VRS_CNTL_BASE_IDX = 1 # macro
regPA_SU_POINT_SIZE = 0x0280 # macro
regPA_SU_POINT_SIZE_BASE_IDX = 1 # macro
regPA_SU_POINT_MINMAX = 0x0281 # macro
regPA_SU_POINT_MINMAX_BASE_IDX = 1 # macro
regPA_SU_LINE_CNTL = 0x0282 # macro
regPA_SU_LINE_CNTL_BASE_IDX = 1 # macro
regPA_SC_LINE_STIPPLE = 0x0283 # macro
regPA_SC_LINE_STIPPLE_BASE_IDX = 1 # macro
regVGT_HOS_MAX_TESS_LEVEL = 0x0286 # macro
regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX = 1 # macro
regVGT_HOS_MIN_TESS_LEVEL = 0x0287 # macro
regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX = 1 # macro
regPA_SC_MODE_CNTL_0 = 0x0292 # macro
regPA_SC_MODE_CNTL_0_BASE_IDX = 1 # macro
regPA_SC_MODE_CNTL_1 = 0x0293 # macro
regPA_SC_MODE_CNTL_1_BASE_IDX = 1 # macro
regVGT_ENHANCE = 0x0294 # macro
regVGT_ENHANCE_BASE_IDX = 1 # macro
regIA_ENHANCE = 0x029c # macro
regIA_ENHANCE_BASE_IDX = 1 # macro
regVGT_DMA_SIZE = 0x029d # macro
regVGT_DMA_SIZE_BASE_IDX = 1 # macro
regVGT_DMA_MAX_SIZE = 0x029e # macro
regVGT_DMA_MAX_SIZE_BASE_IDX = 1 # macro
regVGT_DMA_INDEX_TYPE = 0x029f # macro
regVGT_DMA_INDEX_TYPE_BASE_IDX = 1 # macro
regWD_ENHANCE = 0x02a0 # macro
regWD_ENHANCE_BASE_IDX = 1 # macro
regVGT_PRIMITIVEID_EN = 0x02a1 # macro
regVGT_PRIMITIVEID_EN_BASE_IDX = 1 # macro
regVGT_DMA_NUM_INSTANCES = 0x02a2 # macro
regVGT_DMA_NUM_INSTANCES_BASE_IDX = 1 # macro
regVGT_PRIMITIVEID_RESET = 0x02a3 # macro
regVGT_PRIMITIVEID_RESET_BASE_IDX = 1 # macro
regVGT_EVENT_INITIATOR = 0x02a4 # macro
regVGT_EVENT_INITIATOR_BASE_IDX = 1 # macro
regVGT_DRAW_PAYLOAD_CNTL = 0x02a6 # macro
regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX = 1 # macro
regVGT_ESGS_RING_ITEMSIZE = 0x02ab # macro
regVGT_ESGS_RING_ITEMSIZE_BASE_IDX = 1 # macro
regVGT_REUSE_OFF = 0x02ad # macro
regVGT_REUSE_OFF_BASE_IDX = 1 # macro
regDB_HTILE_SURFACE = 0x02af # macro
regDB_HTILE_SURFACE_BASE_IDX = 1 # macro
regDB_SRESULTS_COMPARE_STATE0 = 0x02b0 # macro
regDB_SRESULTS_COMPARE_STATE0_BASE_IDX = 1 # macro
regDB_SRESULTS_COMPARE_STATE1 = 0x02b1 # macro
regDB_SRESULTS_COMPARE_STATE1_BASE_IDX = 1 # macro
regDB_PRELOAD_CONTROL = 0x02b2 # macro
regDB_PRELOAD_CONTROL_BASE_IDX = 1 # macro
regVGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x02ca # macro
regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX = 1 # macro
regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x02cb # macro
regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX = 1 # macro
regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x02cc # macro
regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX = 1 # macro
regVGT_GS_MAX_VERT_OUT = 0x02ce # macro
regVGT_GS_MAX_VERT_OUT_BASE_IDX = 1 # macro
regGE_NGG_SUBGRP_CNTL = 0x02d3 # macro
regGE_NGG_SUBGRP_CNTL_BASE_IDX = 1 # macro
regVGT_TESS_DISTRIBUTION = 0x02d4 # macro
regVGT_TESS_DISTRIBUTION_BASE_IDX = 1 # macro
regVGT_SHADER_STAGES_EN = 0x02d5 # macro
regVGT_SHADER_STAGES_EN_BASE_IDX = 1 # macro
regVGT_LS_HS_CONFIG = 0x02d6 # macro
regVGT_LS_HS_CONFIG_BASE_IDX = 1 # macro
regVGT_TF_PARAM = 0x02db # macro
regVGT_TF_PARAM_BASE_IDX = 1 # macro
regDB_ALPHA_TO_MASK = 0x02dc # macro
regDB_ALPHA_TO_MASK_BASE_IDX = 1 # macro
regPA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x02de # macro
regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX = 1 # macro
regPA_SU_POLY_OFFSET_CLAMP = 0x02df # macro
regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX = 1 # macro
regPA_SU_POLY_OFFSET_FRONT_SCALE = 0x02e0 # macro
regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX = 1 # macro
regPA_SU_POLY_OFFSET_FRONT_OFFSET = 0x02e1 # macro
regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX = 1 # macro
regPA_SU_POLY_OFFSET_BACK_SCALE = 0x02e2 # macro
regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX = 1 # macro
regPA_SU_POLY_OFFSET_BACK_OFFSET = 0x02e3 # macro
regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX = 1 # macro
regVGT_GS_INSTANCE_CNT = 0x02e4 # macro
regVGT_GS_INSTANCE_CNT_BASE_IDX = 1 # macro
regPA_SC_CENTROID_PRIORITY_0 = 0x02f5 # macro
regPA_SC_CENTROID_PRIORITY_0_BASE_IDX = 1 # macro
regPA_SC_CENTROID_PRIORITY_1 = 0x02f6 # macro
regPA_SC_CENTROID_PRIORITY_1_BASE_IDX = 1 # macro
regPA_SC_LINE_CNTL = 0x02f7 # macro
regPA_SC_LINE_CNTL_BASE_IDX = 1 # macro
regPA_SC_AA_CONFIG = 0x02f8 # macro
regPA_SC_AA_CONFIG_BASE_IDX = 1 # macro
regPA_SU_VTX_CNTL = 0x02f9 # macro
regPA_SU_VTX_CNTL_BASE_IDX = 1 # macro
regPA_CL_GB_VERT_CLIP_ADJ = 0x02fa # macro
regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX = 1 # macro
regPA_CL_GB_VERT_DISC_ADJ = 0x02fb # macro
regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX = 1 # macro
regPA_CL_GB_HORZ_CLIP_ADJ = 0x02fc # macro
regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX = 1 # macro
regPA_CL_GB_HORZ_DISC_ADJ = 0x02fd # macro
regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x02fe # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 = 0x02ff # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 = 0x0300 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 = 0x0301 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 = 0x0302 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 = 0x0303 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 = 0x0304 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 = 0x0305 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 = 0x0306 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 = 0x0307 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 = 0x0308 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 = 0x0309 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 = 0x030a # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 = 0x030b # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 = 0x030c # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX = 1 # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 = 0x030d # macro
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX = 1 # macro
regPA_SC_AA_MASK_X0Y0_X1Y0 = 0x030e # macro
regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX = 1 # macro
regPA_SC_AA_MASK_X0Y1_X1Y1 = 0x030f # macro
regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX = 1 # macro
regPA_SC_SHADER_CONTROL = 0x0310 # macro
regPA_SC_SHADER_CONTROL_BASE_IDX = 1 # macro
regPA_SC_BINNER_CNTL_0 = 0x0311 # macro
regPA_SC_BINNER_CNTL_0_BASE_IDX = 1 # macro
regPA_SC_BINNER_CNTL_1 = 0x0312 # macro
regPA_SC_BINNER_CNTL_1_BASE_IDX = 1 # macro
regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x0313 # macro
regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX = 1 # macro
regPA_SC_NGG_MODE_CNTL = 0x0314 # macro
regPA_SC_NGG_MODE_CNTL_BASE_IDX = 1 # macro
regPA_SC_BINNER_CNTL_2 = 0x0315 # macro
regPA_SC_BINNER_CNTL_2_BASE_IDX = 1 # macro
regCB_COLOR0_BASE = 0x0318 # macro
regCB_COLOR0_BASE_BASE_IDX = 1 # macro
regCB_COLOR0_VIEW = 0x031b # macro
regCB_COLOR0_VIEW_BASE_IDX = 1 # macro
regCB_COLOR0_INFO = 0x031c # macro
regCB_COLOR0_INFO_BASE_IDX = 1 # macro
regCB_COLOR0_ATTRIB = 0x031d # macro
regCB_COLOR0_ATTRIB_BASE_IDX = 1 # macro
regCB_COLOR0_FDCC_CONTROL = 0x031e # macro
regCB_COLOR0_FDCC_CONTROL_BASE_IDX = 1 # macro
regCB_COLOR0_DCC_BASE = 0x0325 # macro
regCB_COLOR0_DCC_BASE_BASE_IDX = 1 # macro
regCB_COLOR1_BASE = 0x0327 # macro
regCB_COLOR1_BASE_BASE_IDX = 1 # macro
regCB_COLOR1_VIEW = 0x032a # macro
regCB_COLOR1_VIEW_BASE_IDX = 1 # macro
regCB_COLOR1_INFO = 0x032b # macro
regCB_COLOR1_INFO_BASE_IDX = 1 # macro
regCB_COLOR1_ATTRIB = 0x032c # macro
regCB_COLOR1_ATTRIB_BASE_IDX = 1 # macro
regCB_COLOR1_FDCC_CONTROL = 0x032d # macro
regCB_COLOR1_FDCC_CONTROL_BASE_IDX = 1 # macro
regCB_COLOR1_DCC_BASE = 0x0334 # macro
regCB_COLOR1_DCC_BASE_BASE_IDX = 1 # macro
regCB_COLOR2_BASE = 0x0336 # macro
regCB_COLOR2_BASE_BASE_IDX = 1 # macro
regCB_COLOR2_VIEW = 0x0339 # macro
regCB_COLOR2_VIEW_BASE_IDX = 1 # macro
regCB_COLOR2_INFO = 0x033a # macro
regCB_COLOR2_INFO_BASE_IDX = 1 # macro
regCB_COLOR2_ATTRIB = 0x033b # macro
regCB_COLOR2_ATTRIB_BASE_IDX = 1 # macro
regCB_COLOR2_FDCC_CONTROL = 0x033c # macro
regCB_COLOR2_FDCC_CONTROL_BASE_IDX = 1 # macro
regCB_COLOR2_DCC_BASE = 0x0343 # macro
regCB_COLOR2_DCC_BASE_BASE_IDX = 1 # macro
regCB_COLOR3_BASE = 0x0345 # macro
regCB_COLOR3_BASE_BASE_IDX = 1 # macro
regCB_COLOR3_VIEW = 0x0348 # macro
regCB_COLOR3_VIEW_BASE_IDX = 1 # macro
regCB_COLOR3_INFO = 0x0349 # macro
regCB_COLOR3_INFO_BASE_IDX = 1 # macro
regCB_COLOR3_ATTRIB = 0x034a # macro
regCB_COLOR3_ATTRIB_BASE_IDX = 1 # macro
regCB_COLOR3_FDCC_CONTROL = 0x034b # macro
regCB_COLOR3_FDCC_CONTROL_BASE_IDX = 1 # macro
regCB_COLOR3_DCC_BASE = 0x0352 # macro
regCB_COLOR3_DCC_BASE_BASE_IDX = 1 # macro
regCB_COLOR4_BASE = 0x0354 # macro
regCB_COLOR4_BASE_BASE_IDX = 1 # macro
regCB_COLOR4_VIEW = 0x0357 # macro
regCB_COLOR4_VIEW_BASE_IDX = 1 # macro
regCB_COLOR4_INFO = 0x0358 # macro
regCB_COLOR4_INFO_BASE_IDX = 1 # macro
regCB_COLOR4_ATTRIB = 0x0359 # macro
regCB_COLOR4_ATTRIB_BASE_IDX = 1 # macro
regCB_COLOR4_FDCC_CONTROL = 0x035a # macro
regCB_COLOR4_FDCC_CONTROL_BASE_IDX = 1 # macro
regCB_COLOR4_DCC_BASE = 0x0361 # macro
regCB_COLOR4_DCC_BASE_BASE_IDX = 1 # macro
regCB_COLOR5_BASE = 0x0363 # macro
regCB_COLOR5_BASE_BASE_IDX = 1 # macro
regCB_COLOR5_VIEW = 0x0366 # macro
regCB_COLOR5_VIEW_BASE_IDX = 1 # macro
regCB_COLOR5_INFO = 0x0367 # macro
regCB_COLOR5_INFO_BASE_IDX = 1 # macro
regCB_COLOR5_ATTRIB = 0x0368 # macro
regCB_COLOR5_ATTRIB_BASE_IDX = 1 # macro
regCB_COLOR5_FDCC_CONTROL = 0x0369 # macro
regCB_COLOR5_FDCC_CONTROL_BASE_IDX = 1 # macro
regCB_COLOR5_DCC_BASE = 0x0370 # macro
regCB_COLOR5_DCC_BASE_BASE_IDX = 1 # macro
regCB_COLOR6_BASE = 0x0372 # macro
regCB_COLOR6_BASE_BASE_IDX = 1 # macro
regCB_COLOR6_VIEW = 0x0375 # macro
regCB_COLOR6_VIEW_BASE_IDX = 1 # macro
regCB_COLOR6_INFO = 0x0376 # macro
regCB_COLOR6_INFO_BASE_IDX = 1 # macro
regCB_COLOR6_ATTRIB = 0x0377 # macro
regCB_COLOR6_ATTRIB_BASE_IDX = 1 # macro
regCB_COLOR6_FDCC_CONTROL = 0x0378 # macro
regCB_COLOR6_FDCC_CONTROL_BASE_IDX = 1 # macro
regCB_COLOR6_DCC_BASE = 0x037f # macro
regCB_COLOR6_DCC_BASE_BASE_IDX = 1 # macro
regCB_COLOR7_BASE = 0x0381 # macro
regCB_COLOR7_BASE_BASE_IDX = 1 # macro
regCB_COLOR7_VIEW = 0x0384 # macro
regCB_COLOR7_VIEW_BASE_IDX = 1 # macro
regCB_COLOR7_INFO = 0x0385 # macro
regCB_COLOR7_INFO_BASE_IDX = 1 # macro
regCB_COLOR7_ATTRIB = 0x0386 # macro
regCB_COLOR7_ATTRIB_BASE_IDX = 1 # macro
regCB_COLOR7_FDCC_CONTROL = 0x0387 # macro
regCB_COLOR7_FDCC_CONTROL_BASE_IDX = 1 # macro
regCB_COLOR7_DCC_BASE = 0x038e # macro
regCB_COLOR7_DCC_BASE_BASE_IDX = 1 # macro
regCB_COLOR0_BASE_EXT = 0x0390 # macro
regCB_COLOR0_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR1_BASE_EXT = 0x0391 # macro
regCB_COLOR1_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR2_BASE_EXT = 0x0392 # macro
regCB_COLOR2_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR3_BASE_EXT = 0x0393 # macro
regCB_COLOR3_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR4_BASE_EXT = 0x0394 # macro
regCB_COLOR4_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR5_BASE_EXT = 0x0395 # macro
regCB_COLOR5_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR6_BASE_EXT = 0x0396 # macro
regCB_COLOR6_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR7_BASE_EXT = 0x0397 # macro
regCB_COLOR7_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR0_DCC_BASE_EXT = 0x03a8 # macro
regCB_COLOR0_DCC_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR1_DCC_BASE_EXT = 0x03a9 # macro
regCB_COLOR1_DCC_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR2_DCC_BASE_EXT = 0x03aa # macro
regCB_COLOR2_DCC_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR3_DCC_BASE_EXT = 0x03ab # macro
regCB_COLOR3_DCC_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR4_DCC_BASE_EXT = 0x03ac # macro
regCB_COLOR4_DCC_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR5_DCC_BASE_EXT = 0x03ad # macro
regCB_COLOR5_DCC_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR6_DCC_BASE_EXT = 0x03ae # macro
regCB_COLOR6_DCC_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR7_DCC_BASE_EXT = 0x03af # macro
regCB_COLOR7_DCC_BASE_EXT_BASE_IDX = 1 # macro
regCB_COLOR0_ATTRIB2 = 0x03b0 # macro
regCB_COLOR0_ATTRIB2_BASE_IDX = 1 # macro
regCB_COLOR1_ATTRIB2 = 0x03b1 # macro
regCB_COLOR1_ATTRIB2_BASE_IDX = 1 # macro
regCB_COLOR2_ATTRIB2 = 0x03b2 # macro
regCB_COLOR2_ATTRIB2_BASE_IDX = 1 # macro
regCB_COLOR3_ATTRIB2 = 0x03b3 # macro
regCB_COLOR3_ATTRIB2_BASE_IDX = 1 # macro
regCB_COLOR4_ATTRIB2 = 0x03b4 # macro
regCB_COLOR4_ATTRIB2_BASE_IDX = 1 # macro
regCB_COLOR5_ATTRIB2 = 0x03b5 # macro
regCB_COLOR5_ATTRIB2_BASE_IDX = 1 # macro
regCB_COLOR6_ATTRIB2 = 0x03b6 # macro
regCB_COLOR6_ATTRIB2_BASE_IDX = 1 # macro
regCB_COLOR7_ATTRIB2 = 0x03b7 # macro
regCB_COLOR7_ATTRIB2_BASE_IDX = 1 # macro
regCB_COLOR0_ATTRIB3 = 0x03b8 # macro
regCB_COLOR0_ATTRIB3_BASE_IDX = 1 # macro
regCB_COLOR1_ATTRIB3 = 0x03b9 # macro
regCB_COLOR1_ATTRIB3_BASE_IDX = 1 # macro
regCB_COLOR2_ATTRIB3 = 0x03ba # macro
regCB_COLOR2_ATTRIB3_BASE_IDX = 1 # macro
regCB_COLOR3_ATTRIB3 = 0x03bb # macro
regCB_COLOR3_ATTRIB3_BASE_IDX = 1 # macro
regCB_COLOR4_ATTRIB3 = 0x03bc # macro
regCB_COLOR4_ATTRIB3_BASE_IDX = 1 # macro
regCB_COLOR5_ATTRIB3 = 0x03bd # macro
regCB_COLOR5_ATTRIB3_BASE_IDX = 1 # macro
regCB_COLOR6_ATTRIB3 = 0x03be # macro
regCB_COLOR6_ATTRIB3_BASE_IDX = 1 # macro
regCB_COLOR7_ATTRIB3 = 0x03bf # macro
regCB_COLOR7_ATTRIB3_BASE_IDX = 1 # macro
regCONFIG_RESERVED_REG0 = 0x0800 # macro
regCONFIG_RESERVED_REG0_BASE_IDX = 1 # macro
regCONFIG_RESERVED_REG1 = 0x0801 # macro
regCONFIG_RESERVED_REG1_BASE_IDX = 1 # macro
regCP_MEC_CNTL = 0x0802 # macro
regCP_MEC_CNTL_BASE_IDX = 1 # macro
regCP_ME_CNTL = 0x0803 # macro
regCP_ME_CNTL_BASE_IDX = 1 # macro
regGRBM_GFX_CNTL = 0x0900 # macro
regGRBM_GFX_CNTL_BASE_IDX = 1 # macro
regGRBM_NOWHERE = 0x0901 # macro
regGRBM_NOWHERE_BASE_IDX = 1 # macro
regPA_SC_VRS_SURFACE_CNTL = 0x0940 # macro
regPA_SC_VRS_SURFACE_CNTL_BASE_IDX = 1 # macro
regPA_SC_ENHANCE = 0x0941 # macro
regPA_SC_ENHANCE_BASE_IDX = 1 # macro
regPA_SC_ENHANCE_1 = 0x0942 # macro
regPA_SC_ENHANCE_1_BASE_IDX = 1 # macro
regPA_SC_ENHANCE_2 = 0x0943 # macro
regPA_SC_ENHANCE_2_BASE_IDX = 1 # macro
regPA_SC_ENHANCE_3 = 0x0944 # macro
regPA_SC_ENHANCE_3_BASE_IDX = 1 # macro
regPA_SC_BINNER_CNTL_OVERRIDE = 0x0946 # macro
regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX = 1 # macro
regPA_SC_PBB_OVERRIDE_FLAG = 0x0947 # macro
regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX = 1 # macro
regPA_SC_DSM_CNTL = 0x0948 # macro
regPA_SC_DSM_CNTL_BASE_IDX = 1 # macro
regPA_SC_TILE_STEERING_CREST_OVERRIDE = 0x0949 # macro
regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX = 1 # macro
regPA_SC_FIFO_SIZE = 0x094a # macro
regPA_SC_FIFO_SIZE_BASE_IDX = 1 # macro
regPA_SC_IF_FIFO_SIZE = 0x094b # macro
regPA_SC_IF_FIFO_SIZE_BASE_IDX = 1 # macro
regPA_SC_PACKER_WAVE_ID_CNTL = 0x094c # macro
regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX = 1 # macro
regPA_SC_ATM_CNTL = 0x094d # macro
regPA_SC_ATM_CNTL_BASE_IDX = 1 # macro
regPA_SC_PKR_WAVE_TABLE_CNTL = 0x094e # macro
regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX = 1 # macro
regPA_SC_FORCE_EOV_MAX_CNTS = 0x094f # macro
regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX = 1 # macro
regPA_SC_BINNER_EVENT_CNTL_0 = 0x0950 # macro
regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX = 1 # macro
regPA_SC_BINNER_EVENT_CNTL_1 = 0x0951 # macro
regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX = 1 # macro
regPA_SC_BINNER_EVENT_CNTL_2 = 0x0952 # macro
regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX = 1 # macro
regPA_SC_BINNER_EVENT_CNTL_3 = 0x0953 # macro
regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX = 1 # macro
regPA_SC_BINNER_TIMEOUT_COUNTER = 0x0954 # macro
regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX = 1 # macro
regPA_SC_BINNER_PERF_CNTL_0 = 0x0955 # macro
regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX = 1 # macro
regPA_SC_BINNER_PERF_CNTL_1 = 0x0956 # macro
regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX = 1 # macro
regPA_SC_BINNER_PERF_CNTL_2 = 0x0957 # macro
regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX = 1 # macro
regPA_SC_BINNER_PERF_CNTL_3 = 0x0958 # macro
regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX = 1 # macro
regPA_SC_P3D_TRAP_SCREEN_HV_LOCK = 0x095b # macro
regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro
regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK = 0x095c # macro
regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro
regPA_SC_TRAP_SCREEN_HV_LOCK = 0x095d # macro
regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro
regPA_PH_INTERFACE_FIFO_SIZE = 0x095e # macro
regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX = 1 # macro
regPA_PH_ENHANCE = 0x095f # macro
regPA_PH_ENHANCE_BASE_IDX = 1 # macro
regPA_SC_VRS_SURFACE_CNTL_1 = 0x0960 # macro
regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX = 1 # macro
regSQ_RUNTIME_CONFIG = 0x09e0 # macro
regSQ_RUNTIME_CONFIG_BASE_IDX = 1 # macro
regSQ_DEBUG_STS_GLOBAL = 0x09e1 # macro
regSQ_DEBUG_STS_GLOBAL_BASE_IDX = 1 # macro
regSQ_DEBUG_STS_GLOBAL2 = 0x09e2 # macro
regSQ_DEBUG_STS_GLOBAL2_BASE_IDX = 1 # macro
regSH_MEM_BASES = 0x09e3 # macro
regSH_MEM_BASES_BASE_IDX = 1 # macro
regSH_MEM_CONFIG = 0x09e4 # macro
regSH_MEM_CONFIG_BASE_IDX = 1 # macro
regSQ_DEBUG = 0x09e5 # macro
regSQ_DEBUG_BASE_IDX = 1 # macro
regSQ_SHADER_TBA_LO = 0x09e6 # macro
regSQ_SHADER_TBA_LO_BASE_IDX = 1 # macro
regSQ_SHADER_TBA_HI = 0x09e7 # macro
regSQ_SHADER_TBA_HI_BASE_IDX = 1 # macro
regSQ_SHADER_TMA_LO = 0x09e8 # macro
regSQ_SHADER_TMA_LO_BASE_IDX = 1 # macro
regSQ_SHADER_TMA_HI = 0x09e9 # macro
regSQ_SHADER_TMA_HI_BASE_IDX = 1 # macro
regCP_DEBUG_2 = 0x1800 # macro
regCP_DEBUG_2_BASE_IDX = 1 # macro
regCP_FETCHER_SOURCE = 0x1801 # macro
regCP_FETCHER_SOURCE_BASE_IDX = 1 # macro
regCP_HPD_MES_ROQ_OFFSETS = 0x1821 # macro
regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX = 1 # macro
regCP_HPD_ROQ_OFFSETS = 0x1821 # macro
regCP_HPD_ROQ_OFFSETS_BASE_IDX = 1 # macro
regCP_HPD_STATUS0 = 0x1822 # macro
regCP_HPD_STATUS0_BASE_IDX = 1 # macro
regDIDT_INDEX_AUTO_INCR_EN = 0x1900 # macro
regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX = 1 # macro
regDIDT_EDC_CTRL = 0x1901 # macro
regDIDT_EDC_CTRL_BASE_IDX = 1 # macro
regDIDT_EDC_THROTTLE_CTRL = 0x1902 # macro
regDIDT_EDC_THROTTLE_CTRL_BASE_IDX = 1 # macro
regDIDT_EDC_THRESHOLD = 0x1903 # macro
regDIDT_EDC_THRESHOLD_BASE_IDX = 1 # macro
regDIDT_EDC_STALL_PATTERN_1_2 = 0x1904 # macro
regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX = 1 # macro
regDIDT_EDC_STALL_PATTERN_3_4 = 0x1905 # macro
regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX = 1 # macro
regDIDT_EDC_STALL_PATTERN_5_6 = 0x1906 # macro
regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX = 1 # macro
regDIDT_EDC_STALL_PATTERN_7 = 0x1907 # macro
regDIDT_EDC_STALL_PATTERN_7_BASE_IDX = 1 # macro
regDIDT_EDC_STATUS = 0x1908 # macro
regDIDT_EDC_STATUS_BASE_IDX = 1 # macro
regDIDT_EDC_DYNAMIC_THRESHOLD_RO = 0x1909 # macro
regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX = 1 # macro
regDIDT_EDC_OVERFLOW = 0x190a # macro
regDIDT_EDC_OVERFLOW_BASE_IDX = 1 # macro
regDIDT_EDC_ROLLING_POWER_DELTA = 0x190b # macro
regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX = 1 # macro
regDIDT_IND_INDEX = 0x190c # macro
regDIDT_IND_INDEX_BASE_IDX = 1 # macro
regDIDT_IND_DATA = 0x190d # macro
regDIDT_IND_DATA_BASE_IDX = 1 # macro
regSPI_GDBG_WAVE_CNTL = 0x1943 # macro
regSPI_GDBG_WAVE_CNTL_BASE_IDX = 1 # macro
regSPI_GDBG_TRAP_CONFIG = 0x1944 # macro
regSPI_GDBG_TRAP_CONFIG_BASE_IDX = 1 # macro
regSPI_GDBG_WAVE_CNTL3 = 0x1945 # macro
regSPI_GDBG_WAVE_CNTL3_BASE_IDX = 1 # macro
regSPI_ARB_CNTL_0 = 0x1949 # macro
regSPI_ARB_CNTL_0_BASE_IDX = 1 # macro
regSPI_FEATURE_CTRL = 0x194a # macro
regSPI_FEATURE_CTRL_BASE_IDX = 1 # macro
regSPI_SHADER_RSRC_LIMIT_CTRL = 0x194b # macro
regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX = 1 # macro
regSPI_COMPUTE_WF_CTX_SAVE_STATUS = 0x194e # macro
regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX = 1 # macro
regTCP_INVALIDATE = 0x19a0 # macro
regTCP_INVALIDATE_BASE_IDX = 1 # macro
regTCP_STATUS = 0x19a1 # macro
regTCP_STATUS_BASE_IDX = 1 # macro
regTCP_CNTL = 0x19a2 # macro
regTCP_CNTL_BASE_IDX = 1 # macro
regTCP_CNTL2 = 0x19a3 # macro
regTCP_CNTL2_BASE_IDX = 1 # macro
regTCP_DEBUG_INDEX = 0x19a5 # macro
regTCP_DEBUG_INDEX_BASE_IDX = 1 # macro
regTCP_DEBUG_DATA = 0x19a6 # macro
regTCP_DEBUG_DATA_BASE_IDX = 1 # macro
regGDS_ENHANCE2 = 0x19b0 # macro
regGDS_ENHANCE2_BASE_IDX = 1 # macro
regGDS_OA_CGPG_RESTORE = 0x19b1 # macro
regGDS_OA_CGPG_RESTORE_BASE_IDX = 1 # macro
regUTCL1_CTRL_0 = 0x1980 # macro
regUTCL1_CTRL_0_BASE_IDX = 1 # macro
regUTCL1_UTCL0_INVREQ_DISABLE = 0x1984 # macro
regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX = 1 # macro
regUTCL1_CTRL_2 = 0x1985 # macro
regUTCL1_CTRL_2_BASE_IDX = 1 # macro
regUTCL1_FIFO_SIZING = 0x1986 # macro
regUTCL1_FIFO_SIZING_BASE_IDX = 1 # macro
regGCRD_SA0_TARGETS_DISABLE = 0x1987 # macro
regGCRD_SA0_TARGETS_DISABLE_BASE_IDX = 1 # macro
regGCRD_SA1_TARGETS_DISABLE = 0x1989 # macro
regGCRD_SA1_TARGETS_DISABLE_BASE_IDX = 1 # macro
regGCRD_CREDIT_SAFE = 0x198a # macro
regGCRD_CREDIT_SAFE_BASE_IDX = 1 # macro
regGCR_GENERAL_CNTL = 0x1990 # macro
regGCR_GENERAL_CNTL_BASE_IDX = 1 # macro
regGCR_CMD_STATUS = 0x1992 # macro
regGCR_CMD_STATUS_BASE_IDX = 1 # macro
regGCR_SPARE = 0x1993 # macro
regGCR_SPARE_BASE_IDX = 1 # macro
regPMM_CNTL2 = 0x1999 # macro
regPMM_CNTL2_BASE_IDX = 1 # macro
regSEDC_GL1_GL2_OVERRIDES = 0x1ac0 # macro
regSEDC_GL1_GL2_OVERRIDES_BASE_IDX = 1 # macro
regGC_CAC_CTRL_1 = 0x1ad0 # macro
regGC_CAC_CTRL_1_BASE_IDX = 1 # macro
regGC_CAC_CTRL_2 = 0x1ad1 # macro
regGC_CAC_CTRL_2_BASE_IDX = 1 # macro
regGC_CAC_AGGR_LOWER = 0x1ad2 # macro
regGC_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
regGC_CAC_AGGR_UPPER = 0x1ad3 # macro
regGC_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
regSE0_CAC_AGGR_LOWER = 0x1ad4 # macro
regSE0_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
regSE0_CAC_AGGR_UPPER = 0x1ad5 # macro
regSE0_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
regSE1_CAC_AGGR_LOWER = 0x1ad6 # macro
regSE1_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
regSE1_CAC_AGGR_UPPER = 0x1ad7 # macro
regSE1_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
regSE2_CAC_AGGR_LOWER = 0x1ad8 # macro
regSE2_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
regSE2_CAC_AGGR_UPPER = 0x1ad9 # macro
regSE2_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
regSE3_CAC_AGGR_LOWER = 0x1ada # macro
regSE3_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
regSE3_CAC_AGGR_UPPER = 0x1adb # macro
regSE3_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
regSE4_CAC_AGGR_LOWER = 0x1adc # macro
regSE4_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
regSE4_CAC_AGGR_UPPER = 0x1add # macro
regSE4_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
regSE5_CAC_AGGR_LOWER = 0x1ade # macro
regSE5_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
regSE5_CAC_AGGR_UPPER = 0x1adf # macro
regSE5_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
regGC_CAC_AGGR_GFXCLK_CYCLE = 0x1ae4 # macro
regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
regSE0_CAC_AGGR_GFXCLK_CYCLE = 0x1ae5 # macro
regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
regSE1_CAC_AGGR_GFXCLK_CYCLE = 0x1ae6 # macro
regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
regSE2_CAC_AGGR_GFXCLK_CYCLE = 0x1ae7 # macro
regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
regSE3_CAC_AGGR_GFXCLK_CYCLE = 0x1ae8 # macro
regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
regSE4_CAC_AGGR_GFXCLK_CYCLE = 0x1ae9 # macro
regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
regSE5_CAC_AGGR_GFXCLK_CYCLE = 0x1aea # macro
regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
regGC_EDC_CTRL = 0x1aed # macro
regGC_EDC_CTRL_BASE_IDX = 1 # macro
regGC_EDC_THRESHOLD = 0x1aee # macro
regGC_EDC_THRESHOLD_BASE_IDX = 1 # macro
regGC_EDC_STRETCH_CTRL = 0x1aef # macro
regGC_EDC_STRETCH_CTRL_BASE_IDX = 1 # macro
regGC_EDC_STRETCH_THRESHOLD = 0x1af0 # macro
regGC_EDC_STRETCH_THRESHOLD_BASE_IDX = 1 # macro
regEDC_HYSTERESIS_CNTL = 0x1af1 # macro
regEDC_HYSTERESIS_CNTL_BASE_IDX = 1 # macro
regGC_THROTTLE_CTRL = 0x1af2 # macro
regGC_THROTTLE_CTRL_BASE_IDX = 1 # macro
regGC_THROTTLE_CTRL1 = 0x1af3 # macro
regGC_THROTTLE_CTRL1_BASE_IDX = 1 # macro
regPCC_STALL_PATTERN_CTRL = 0x1af4 # macro
regPCC_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro
regPWRBRK_STALL_PATTERN_CTRL = 0x1af5 # macro
regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro
regPCC_STALL_PATTERN_1_2 = 0x1af6 # macro
regPCC_STALL_PATTERN_1_2_BASE_IDX = 1 # macro
regPCC_STALL_PATTERN_3_4 = 0x1af7 # macro
regPCC_STALL_PATTERN_3_4_BASE_IDX = 1 # macro
regPCC_STALL_PATTERN_5_6 = 0x1af8 # macro
regPCC_STALL_PATTERN_5_6_BASE_IDX = 1 # macro
regPCC_STALL_PATTERN_7 = 0x1af9 # macro
regPCC_STALL_PATTERN_7_BASE_IDX = 1 # macro
regPWRBRK_STALL_PATTERN_1_2 = 0x1afa # macro
regPWRBRK_STALL_PATTERN_1_2_BASE_IDX = 1 # macro
regPWRBRK_STALL_PATTERN_3_4 = 0x1afb # macro
regPWRBRK_STALL_PATTERN_3_4_BASE_IDX = 1 # macro
regPWRBRK_STALL_PATTERN_5_6 = 0x1afc # macro
regPWRBRK_STALL_PATTERN_5_6_BASE_IDX = 1 # macro
regPWRBRK_STALL_PATTERN_7 = 0x1afd # macro
regPWRBRK_STALL_PATTERN_7_BASE_IDX = 1 # macro
regDIDT_STALL_PATTERN_CTRL = 0x1afe # macro
regDIDT_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro
regDIDT_STALL_PATTERN_1_2 = 0x1aff # macro
regDIDT_STALL_PATTERN_1_2_BASE_IDX = 1 # macro
regDIDT_STALL_PATTERN_3_4 = 0x1b00 # macro
regDIDT_STALL_PATTERN_3_4_BASE_IDX = 1 # macro
regDIDT_STALL_PATTERN_5_6 = 0x1b01 # macro
regDIDT_STALL_PATTERN_5_6_BASE_IDX = 1 # macro
regDIDT_STALL_PATTERN_7 = 0x1b02 # macro
regDIDT_STALL_PATTERN_7_BASE_IDX = 1 # macro
regPCC_PWRBRK_HYSTERESIS_CTRL = 0x1b03 # macro
regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX = 1 # macro
regEDC_STRETCH_PERF_COUNTER = 0x1b04 # macro
regEDC_STRETCH_PERF_COUNTER_BASE_IDX = 1 # macro
regEDC_UNSTRETCH_PERF_COUNTER = 0x1b05 # macro
regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX = 1 # macro
regEDC_STRETCH_NUM_PERF_COUNTER = 0x1b06 # macro
regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX = 1 # macro
regGC_EDC_STATUS = 0x1b07 # macro
regGC_EDC_STATUS_BASE_IDX = 1 # macro
regGC_EDC_OVERFLOW = 0x1b08 # macro
regGC_EDC_OVERFLOW_BASE_IDX = 1 # macro
regGC_EDC_ROLLING_POWER_DELTA = 0x1b09 # macro
regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX = 1 # macro
regGC_THROTTLE_STATUS = 0x1b0a # macro
regGC_THROTTLE_STATUS_BASE_IDX = 1 # macro
regEDC_PERF_COUNTER = 0x1b0b # macro
regEDC_PERF_COUNTER_BASE_IDX = 1 # macro
regPCC_PERF_COUNTER = 0x1b0c # macro
regPCC_PERF_COUNTER_BASE_IDX = 1 # macro
regPWRBRK_PERF_COUNTER = 0x1b0d # macro
regPWRBRK_PERF_COUNTER_BASE_IDX = 1 # macro
regEDC_HYSTERESIS_STAT = 0x1b0e # macro
regEDC_HYSTERESIS_STAT_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_CP_0 = 0x1b10 # macro
regGC_CAC_WEIGHT_CP_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_CP_1 = 0x1b11 # macro
regGC_CAC_WEIGHT_CP_1_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_EA_0 = 0x1b12 # macro
regGC_CAC_WEIGHT_EA_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_EA_1 = 0x1b13 # macro
regGC_CAC_WEIGHT_EA_1_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_EA_2 = 0x1b14 # macro
regGC_CAC_WEIGHT_EA_2_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_UTCL2_ROUTER_0 = 0x1b15 # macro
regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_UTCL2_ROUTER_1 = 0x1b16 # macro
regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_UTCL2_ROUTER_2 = 0x1b17 # macro
regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_UTCL2_ROUTER_3 = 0x1b18 # macro
regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_UTCL2_ROUTER_4 = 0x1b19 # macro
regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_UTCL2_VML2_0 = 0x1b1a # macro
regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_UTCL2_VML2_1 = 0x1b1b # macro
regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_UTCL2_VML2_2 = 0x1b1c # macro
regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_UTCL2_WALKER_0 = 0x1b1d # macro
regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_UTCL2_WALKER_1 = 0x1b1e # macro
regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_UTCL2_WALKER_2 = 0x1b1f # macro
regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GDS_0 = 0x1b20 # macro
regGC_CAC_WEIGHT_GDS_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GDS_1 = 0x1b21 # macro
regGC_CAC_WEIGHT_GDS_1_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GDS_2 = 0x1b22 # macro
regGC_CAC_WEIGHT_GDS_2_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GE_0 = 0x1b23 # macro
regGC_CAC_WEIGHT_GE_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GE_1 = 0x1b24 # macro
regGC_CAC_WEIGHT_GE_1_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GE_2 = 0x1b25 # macro
regGC_CAC_WEIGHT_GE_2_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GE_3 = 0x1b26 # macro
regGC_CAC_WEIGHT_GE_3_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GE_4 = 0x1b27 # macro
regGC_CAC_WEIGHT_GE_4_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GE_5 = 0x1b28 # macro
regGC_CAC_WEIGHT_GE_5_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GE_6 = 0x1b29 # macro
regGC_CAC_WEIGHT_GE_6_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_PMM_0 = 0x1b2e # macro
regGC_CAC_WEIGHT_PMM_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GL2C_0 = 0x1b2f # macro
regGC_CAC_WEIGHT_GL2C_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GL2C_1 = 0x1b30 # macro
regGC_CAC_WEIGHT_GL2C_1_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GL2C_2 = 0x1b31 # macro
regGC_CAC_WEIGHT_GL2C_2_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_PH_0 = 0x1b32 # macro
regGC_CAC_WEIGHT_PH_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_PH_1 = 0x1b33 # macro
regGC_CAC_WEIGHT_PH_1_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_PH_2 = 0x1b34 # macro
regGC_CAC_WEIGHT_PH_2_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_PH_3 = 0x1b35 # macro
regGC_CAC_WEIGHT_PH_3_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_SDMA_0 = 0x1b36 # macro
regGC_CAC_WEIGHT_SDMA_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_SDMA_1 = 0x1b37 # macro
regGC_CAC_WEIGHT_SDMA_1_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_SDMA_2 = 0x1b38 # macro
regGC_CAC_WEIGHT_SDMA_2_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_SDMA_3 = 0x1b39 # macro
regGC_CAC_WEIGHT_SDMA_3_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_SDMA_4 = 0x1b3a # macro
regGC_CAC_WEIGHT_SDMA_4_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_SDMA_5 = 0x1b3b # macro
regGC_CAC_WEIGHT_SDMA_5_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_CHC_0 = 0x1b3c # macro
regGC_CAC_WEIGHT_CHC_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_CHC_1 = 0x1b3d # macro
regGC_CAC_WEIGHT_CHC_1_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GUS_0 = 0x1b3e # macro
regGC_CAC_WEIGHT_GUS_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GUS_1 = 0x1b3f # macro
regGC_CAC_WEIGHT_GUS_1_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_RLC_0 = 0x1b40 # macro
regGC_CAC_WEIGHT_RLC_0_BASE_IDX = 1 # macro
regGC_CAC_WEIGHT_GRBM_0 = 0x1b44 # macro
regGC_CAC_WEIGHT_GRBM_0_BASE_IDX = 1 # macro
regGC_EDC_CLK_MONITOR_CTRL = 0x1b56 # macro
regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX = 1 # macro
regGC_CAC_IND_INDEX = 0x1b58 # macro
regGC_CAC_IND_INDEX_BASE_IDX = 1 # macro
regGC_CAC_IND_DATA = 0x1b59 # macro
regGC_CAC_IND_DATA_BASE_IDX = 1 # macro
regSE_CAC_CTRL_1 = 0x1b70 # macro
regSE_CAC_CTRL_1_BASE_IDX = 1 # macro
regSE_CAC_CTRL_2 = 0x1b71 # macro
regSE_CAC_CTRL_2_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_TA_0 = 0x1b72 # macro
regSE_CAC_WEIGHT_TA_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_TD_0 = 0x1b73 # macro
regSE_CAC_WEIGHT_TD_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_TD_1 = 0x1b74 # macro
regSE_CAC_WEIGHT_TD_1_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_TD_2 = 0x1b75 # macro
regSE_CAC_WEIGHT_TD_2_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_TD_3 = 0x1b76 # macro
regSE_CAC_WEIGHT_TD_3_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_TD_4 = 0x1b77 # macro
regSE_CAC_WEIGHT_TD_4_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_TD_5 = 0x1b78 # macro
regSE_CAC_WEIGHT_TD_5_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_TCP_0 = 0x1b79 # macro
regSE_CAC_WEIGHT_TCP_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_TCP_1 = 0x1b7a # macro
regSE_CAC_WEIGHT_TCP_1_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_TCP_2 = 0x1b7b # macro
regSE_CAC_WEIGHT_TCP_2_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_TCP_3 = 0x1b7c # macro
regSE_CAC_WEIGHT_TCP_3_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SQ_0 = 0x1b7d # macro
regSE_CAC_WEIGHT_SQ_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SQ_1 = 0x1b7e # macro
regSE_CAC_WEIGHT_SQ_1_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SQ_2 = 0x1b7f # macro
regSE_CAC_WEIGHT_SQ_2_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SP_0 = 0x1b80 # macro
regSE_CAC_WEIGHT_SP_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SP_1 = 0x1b81 # macro
regSE_CAC_WEIGHT_SP_1_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_LDS_0 = 0x1b82 # macro
regSE_CAC_WEIGHT_LDS_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_LDS_1 = 0x1b83 # macro
regSE_CAC_WEIGHT_LDS_1_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_LDS_2 = 0x1b84 # macro
regSE_CAC_WEIGHT_LDS_2_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_LDS_3 = 0x1b85 # macro
regSE_CAC_WEIGHT_LDS_3_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SQC_0 = 0x1b87 # macro
regSE_CAC_WEIGHT_SQC_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SQC_1 = 0x1b88 # macro
regSE_CAC_WEIGHT_SQC_1_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_CU_0 = 0x1b89 # macro
regSE_CAC_WEIGHT_CU_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_BCI_0 = 0x1b8a # macro
regSE_CAC_WEIGHT_BCI_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_CB_0 = 0x1b8b # macro
regSE_CAC_WEIGHT_CB_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_CB_1 = 0x1b8c # macro
regSE_CAC_WEIGHT_CB_1_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_CB_2 = 0x1b8d # macro
regSE_CAC_WEIGHT_CB_2_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_CB_3 = 0x1b8e # macro
regSE_CAC_WEIGHT_CB_3_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_CB_4 = 0x1b8f # macro
regSE_CAC_WEIGHT_CB_4_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_CB_5 = 0x1b90 # macro
regSE_CAC_WEIGHT_CB_5_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_CB_6 = 0x1b91 # macro
regSE_CAC_WEIGHT_CB_6_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_CB_7 = 0x1b92 # macro
regSE_CAC_WEIGHT_CB_7_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_CB_8 = 0x1b93 # macro
regSE_CAC_WEIGHT_CB_8_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_CB_9 = 0x1b94 # macro
regSE_CAC_WEIGHT_CB_9_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_CB_10 = 0x1b95 # macro
regSE_CAC_WEIGHT_CB_10_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_CB_11 = 0x1b96 # macro
regSE_CAC_WEIGHT_CB_11_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_DB_0 = 0x1b97 # macro
regSE_CAC_WEIGHT_DB_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_DB_1 = 0x1b98 # macro
regSE_CAC_WEIGHT_DB_1_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_DB_2 = 0x1b99 # macro
regSE_CAC_WEIGHT_DB_2_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_DB_3 = 0x1b9a # macro
regSE_CAC_WEIGHT_DB_3_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_DB_4 = 0x1b9b # macro
regSE_CAC_WEIGHT_DB_4_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_RMI_0 = 0x1b9c # macro
regSE_CAC_WEIGHT_RMI_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_RMI_1 = 0x1b9d # macro
regSE_CAC_WEIGHT_RMI_1_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SX_0 = 0x1b9e # macro
regSE_CAC_WEIGHT_SX_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SXRB_0 = 0x1b9f # macro
regSE_CAC_WEIGHT_SXRB_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_UTCL1_0 = 0x1ba0 # macro
regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_GL1C_0 = 0x1ba1 # macro
regSE_CAC_WEIGHT_GL1C_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_GL1C_1 = 0x1ba2 # macro
regSE_CAC_WEIGHT_GL1C_1_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_GL1C_2 = 0x1ba3 # macro
regSE_CAC_WEIGHT_GL1C_2_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SPI_0 = 0x1ba4 # macro
regSE_CAC_WEIGHT_SPI_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SPI_1 = 0x1ba5 # macro
regSE_CAC_WEIGHT_SPI_1_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SPI_2 = 0x1ba6 # macro
regSE_CAC_WEIGHT_SPI_2_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_PC_0 = 0x1ba7 # macro
regSE_CAC_WEIGHT_PC_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_PA_0 = 0x1ba8 # macro
regSE_CAC_WEIGHT_PA_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_PA_1 = 0x1ba9 # macro
regSE_CAC_WEIGHT_PA_1_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_PA_2 = 0x1baa # macro
regSE_CAC_WEIGHT_PA_2_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_PA_3 = 0x1bab # macro
regSE_CAC_WEIGHT_PA_3_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SC_0 = 0x1bac # macro
regSE_CAC_WEIGHT_SC_0_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SC_1 = 0x1bad # macro
regSE_CAC_WEIGHT_SC_1_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SC_2 = 0x1bae # macro
regSE_CAC_WEIGHT_SC_2_BASE_IDX = 1 # macro
regSE_CAC_WEIGHT_SC_3 = 0x1baf # macro
regSE_CAC_WEIGHT_SC_3_BASE_IDX = 1 # macro
regSE_CAC_WINDOW_AGGR_VALUE = 0x1bb0 # macro
regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX = 1 # macro
regSE_CAC_WINDOW_GFXCLK_CYCLE = 0x1bb1 # macro
regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX = 1 # macro
regSE_CAC_IND_INDEX = 0x1bce # macro
regSE_CAC_IND_INDEX_BASE_IDX = 1 # macro
regSE_CAC_IND_DATA = 0x1bcf # macro
regSE_CAC_IND_DATA_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_0 = 0x1c00 # macro
regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_1 = 0x1c01 # macro
regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_2 = 0x1c02 # macro
regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_3 = 0x1c03 # macro
regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_4 = 0x1c04 # macro
regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_5 = 0x1c05 # macro
regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_6 = 0x1c06 # macro
regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_7 = 0x1c07 # macro
regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_8 = 0x1c08 # macro
regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_9 = 0x1c09 # macro
regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_10 = 0x1c0a # macro
regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_11 = 0x1c0b # macro
regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_12 = 0x1c0c # macro
regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_13 = 0x1c0d # macro
regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_14 = 0x1c0e # macro
regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_CU_15 = 0x1c0f # macro
regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_0 = 0x1c10 # macro
regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_1 = 0x1c11 # macro
regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_2 = 0x1c12 # macro
regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_3 = 0x1c13 # macro
regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_4 = 0x1c14 # macro
regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_5 = 0x1c15 # macro
regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_6 = 0x1c16 # macro
regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_7 = 0x1c17 # macro
regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_8 = 0x1c18 # macro
regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_9 = 0x1c19 # macro
regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_10 = 0x1c1a # macro
regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_11 = 0x1c1b # macro
regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_12 = 0x1c1c # macro
regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_13 = 0x1c1d # macro
regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_14 = 0x1c1e # macro
regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX = 1 # macro
regSPI_RESOURCE_RESERVE_EN_CU_15 = 0x1c1f # macro
regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX = 1 # macro
regCP_EOP_DONE_ADDR_LO = 0x2000 # macro
regCP_EOP_DONE_ADDR_LO_BASE_IDX = 1 # macro
regCP_EOP_DONE_ADDR_HI = 0x2001 # macro
regCP_EOP_DONE_ADDR_HI_BASE_IDX = 1 # macro
regCP_EOP_DONE_DATA_LO = 0x2002 # macro
regCP_EOP_DONE_DATA_LO_BASE_IDX = 1 # macro
regCP_EOP_DONE_DATA_HI = 0x2003 # macro
regCP_EOP_DONE_DATA_HI_BASE_IDX = 1 # macro
regCP_EOP_LAST_FENCE_LO = 0x2004 # macro
regCP_EOP_LAST_FENCE_LO_BASE_IDX = 1 # macro
regCP_EOP_LAST_FENCE_HI = 0x2005 # macro
regCP_EOP_LAST_FENCE_HI_BASE_IDX = 1 # macro
regCP_PIPE_STATS_ADDR_LO = 0x2018 # macro
regCP_PIPE_STATS_ADDR_LO_BASE_IDX = 1 # macro
regCP_PIPE_STATS_ADDR_HI = 0x2019 # macro
regCP_PIPE_STATS_ADDR_HI_BASE_IDX = 1 # macro
regCP_VGT_IAVERT_COUNT_LO = 0x201a # macro
regCP_VGT_IAVERT_COUNT_LO_BASE_IDX = 1 # macro
regCP_VGT_IAVERT_COUNT_HI = 0x201b # macro
regCP_VGT_IAVERT_COUNT_HI_BASE_IDX = 1 # macro
regCP_VGT_IAPRIM_COUNT_LO = 0x201c # macro
regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX = 1 # macro
regCP_VGT_IAPRIM_COUNT_HI = 0x201d # macro
regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX = 1 # macro
regCP_VGT_GSPRIM_COUNT_LO = 0x201e # macro
regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX = 1 # macro
regCP_VGT_GSPRIM_COUNT_HI = 0x201f # macro
regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX = 1 # macro
regCP_VGT_VSINVOC_COUNT_LO = 0x2020 # macro
regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX = 1 # macro
regCP_VGT_VSINVOC_COUNT_HI = 0x2021 # macro
regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX = 1 # macro
regCP_VGT_GSINVOC_COUNT_LO = 0x2022 # macro
regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX = 1 # macro
regCP_VGT_GSINVOC_COUNT_HI = 0x2023 # macro
regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX = 1 # macro
regCP_VGT_HSINVOC_COUNT_LO = 0x2024 # macro
regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX = 1 # macro
regCP_VGT_HSINVOC_COUNT_HI = 0x2025 # macro
regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX = 1 # macro
regCP_VGT_DSINVOC_COUNT_LO = 0x2026 # macro
regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX = 1 # macro
regCP_VGT_DSINVOC_COUNT_HI = 0x2027 # macro
regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX = 1 # macro
regCP_PA_CINVOC_COUNT_LO = 0x2028 # macro
regCP_PA_CINVOC_COUNT_LO_BASE_IDX = 1 # macro
regCP_PA_CINVOC_COUNT_HI = 0x2029 # macro
regCP_PA_CINVOC_COUNT_HI_BASE_IDX = 1 # macro
regCP_PA_CPRIM_COUNT_LO = 0x202a # macro
regCP_PA_CPRIM_COUNT_LO_BASE_IDX = 1 # macro
regCP_PA_CPRIM_COUNT_HI = 0x202b # macro
regCP_PA_CPRIM_COUNT_HI_BASE_IDX = 1 # macro
regCP_SC_PSINVOC_COUNT0_LO = 0x202c # macro
regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX = 1 # macro
regCP_SC_PSINVOC_COUNT0_HI = 0x202d # macro
regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX = 1 # macro
regCP_SC_PSINVOC_COUNT1_LO = 0x202e # macro
regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX = 1 # macro
regCP_SC_PSINVOC_COUNT1_HI = 0x202f # macro
regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX = 1 # macro
regCP_VGT_CSINVOC_COUNT_LO = 0x2030 # macro
regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX = 1 # macro
regCP_VGT_CSINVOC_COUNT_HI = 0x2031 # macro
regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX = 1 # macro
regCP_VGT_ASINVOC_COUNT_LO = 0x2032 # macro
regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX = 1 # macro
regCP_VGT_ASINVOC_COUNT_HI = 0x2033 # macro
regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX = 1 # macro
regCP_PIPE_STATS_CONTROL = 0x203d # macro
regCP_PIPE_STATS_CONTROL_BASE_IDX = 1 # macro
regSCRATCH_REG0 = 0x2040 # macro
regSCRATCH_REG0_BASE_IDX = 1 # macro
regSCRATCH_REG1 = 0x2041 # macro
regSCRATCH_REG1_BASE_IDX = 1 # macro
regSCRATCH_REG2 = 0x2042 # macro
regSCRATCH_REG2_BASE_IDX = 1 # macro
regSCRATCH_REG3 = 0x2043 # macro
regSCRATCH_REG3_BASE_IDX = 1 # macro
regSCRATCH_REG4 = 0x2044 # macro
regSCRATCH_REG4_BASE_IDX = 1 # macro
regSCRATCH_REG5 = 0x2045 # macro
regSCRATCH_REG5_BASE_IDX = 1 # macro
regSCRATCH_REG6 = 0x2046 # macro
regSCRATCH_REG6_BASE_IDX = 1 # macro
regSCRATCH_REG7 = 0x2047 # macro
regSCRATCH_REG7_BASE_IDX = 1 # macro
regSCRATCH_REG_ATOMIC = 0x2048 # macro
regSCRATCH_REG_ATOMIC_BASE_IDX = 1 # macro
regSCRATCH_REG_CMPSWAP_ATOMIC = 0x2048 # macro
regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX = 1 # macro
regCP_APPEND_DDID_CNT = 0x204b # macro
regCP_APPEND_DDID_CNT_BASE_IDX = 1 # macro
regCP_APPEND_DATA_HI = 0x204c # macro
regCP_APPEND_DATA_HI_BASE_IDX = 1 # macro
regCP_APPEND_LAST_CS_FENCE_HI = 0x204d # macro
regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX = 1 # macro
regCP_APPEND_LAST_PS_FENCE_HI = 0x204e # macro
regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX = 1 # macro
regCP_PFP_ATOMIC_PREOP_LO = 0x2052 # macro
regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro
regCP_PFP_ATOMIC_PREOP_HI = 0x2053 # macro
regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro
regCP_PFP_GDS_ATOMIC0_PREOP_LO = 0x2054 # macro
regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro
regCP_PFP_GDS_ATOMIC0_PREOP_HI = 0x2055 # macro
regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro
regCP_PFP_GDS_ATOMIC1_PREOP_LO = 0x2056 # macro
regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro
regCP_PFP_GDS_ATOMIC1_PREOP_HI = 0x2057 # macro
regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro
regCP_APPEND_ADDR_LO = 0x2058 # macro
regCP_APPEND_ADDR_LO_BASE_IDX = 1 # macro
regCP_APPEND_ADDR_HI = 0x2059 # macro
regCP_APPEND_ADDR_HI_BASE_IDX = 1 # macro
regCP_APPEND_DATA = 0x205a # macro
regCP_APPEND_DATA_BASE_IDX = 1 # macro
regCP_APPEND_DATA_LO = 0x205a # macro
regCP_APPEND_DATA_LO_BASE_IDX = 1 # macro
regCP_APPEND_LAST_CS_FENCE = 0x205b # macro
regCP_APPEND_LAST_CS_FENCE_BASE_IDX = 1 # macro
regCP_APPEND_LAST_CS_FENCE_LO = 0x205b # macro
regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX = 1 # macro
regCP_APPEND_LAST_PS_FENCE = 0x205c # macro
regCP_APPEND_LAST_PS_FENCE_BASE_IDX = 1 # macro
regCP_APPEND_LAST_PS_FENCE_LO = 0x205c # macro
regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX = 1 # macro
regCP_ATOMIC_PREOP_LO = 0x205d # macro
regCP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro
regCP_ME_ATOMIC_PREOP_LO = 0x205d # macro
regCP_ME_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro
regCP_ATOMIC_PREOP_HI = 0x205e # macro
regCP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro
regCP_ME_ATOMIC_PREOP_HI = 0x205e # macro
regCP_ME_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro
regCP_GDS_ATOMIC0_PREOP_LO = 0x205f # macro
regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro
regCP_ME_GDS_ATOMIC0_PREOP_LO = 0x205f # macro
regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro
regCP_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro
regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro
regCP_ME_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro
regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro
regCP_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro
regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro
regCP_ME_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro
regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro
regCP_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro
regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro
regCP_ME_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro
regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro
regCP_ME_MC_WADDR_LO = 0x2069 # macro
regCP_ME_MC_WADDR_LO_BASE_IDX = 1 # macro
regCP_ME_MC_WADDR_HI = 0x206a # macro
regCP_ME_MC_WADDR_HI_BASE_IDX = 1 # macro
regCP_ME_MC_WDATA_LO = 0x206b # macro
regCP_ME_MC_WDATA_LO_BASE_IDX = 1 # macro
regCP_ME_MC_WDATA_HI = 0x206c # macro
regCP_ME_MC_WDATA_HI_BASE_IDX = 1 # macro
regCP_ME_MC_RADDR_LO = 0x206d # macro
regCP_ME_MC_RADDR_LO_BASE_IDX = 1 # macro
regCP_ME_MC_RADDR_HI = 0x206e # macro
regCP_ME_MC_RADDR_HI_BASE_IDX = 1 # macro
regCP_SEM_WAIT_TIMER = 0x206f # macro
regCP_SEM_WAIT_TIMER_BASE_IDX = 1 # macro
regCP_SIG_SEM_ADDR_LO = 0x2070 # macro
regCP_SIG_SEM_ADDR_LO_BASE_IDX = 1 # macro
regCP_SIG_SEM_ADDR_HI = 0x2071 # macro
regCP_SIG_SEM_ADDR_HI_BASE_IDX = 1 # macro
regCP_WAIT_REG_MEM_TIMEOUT = 0x2074 # macro
regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX = 1 # macro
regCP_WAIT_SEM_ADDR_LO = 0x2075 # macro
regCP_WAIT_SEM_ADDR_LO_BASE_IDX = 1 # macro
regCP_WAIT_SEM_ADDR_HI = 0x2076 # macro
regCP_WAIT_SEM_ADDR_HI_BASE_IDX = 1 # macro
regCP_DMA_PFP_CONTROL = 0x2077 # macro
regCP_DMA_PFP_CONTROL_BASE_IDX = 1 # macro
regCP_DMA_ME_CONTROL = 0x2078 # macro
regCP_DMA_ME_CONTROL_BASE_IDX = 1 # macro
regCP_DMA_ME_SRC_ADDR = 0x2080 # macro
regCP_DMA_ME_SRC_ADDR_BASE_IDX = 1 # macro
regCP_DMA_ME_SRC_ADDR_HI = 0x2081 # macro
regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX = 1 # macro
regCP_DMA_ME_DST_ADDR = 0x2082 # macro
regCP_DMA_ME_DST_ADDR_BASE_IDX = 1 # macro
regCP_DMA_ME_DST_ADDR_HI = 0x2083 # macro
regCP_DMA_ME_DST_ADDR_HI_BASE_IDX = 1 # macro
regCP_DMA_ME_COMMAND = 0x2084 # macro
regCP_DMA_ME_COMMAND_BASE_IDX = 1 # macro
regCP_DMA_PFP_SRC_ADDR = 0x2085 # macro
regCP_DMA_PFP_SRC_ADDR_BASE_IDX = 1 # macro
regCP_DMA_PFP_SRC_ADDR_HI = 0x2086 # macro
regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX = 1 # macro
regCP_DMA_PFP_DST_ADDR = 0x2087 # macro
regCP_DMA_PFP_DST_ADDR_BASE_IDX = 1 # macro
regCP_DMA_PFP_DST_ADDR_HI = 0x2088 # macro
regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX = 1 # macro
regCP_DMA_PFP_COMMAND = 0x2089 # macro
regCP_DMA_PFP_COMMAND_BASE_IDX = 1 # macro
regCP_DMA_CNTL = 0x208a # macro
regCP_DMA_CNTL_BASE_IDX = 1 # macro
regCP_DMA_READ_TAGS = 0x208b # macro
regCP_DMA_READ_TAGS_BASE_IDX = 1 # macro
regCP_PFP_IB_CONTROL = 0x208d # macro
regCP_PFP_IB_CONTROL_BASE_IDX = 1 # macro
regCP_PFP_LOAD_CONTROL = 0x208e # macro
regCP_PFP_LOAD_CONTROL_BASE_IDX = 1 # macro
regCP_SCRATCH_INDEX = 0x208f # macro
regCP_SCRATCH_INDEX_BASE_IDX = 1 # macro
regCP_SCRATCH_DATA = 0x2090 # macro
regCP_SCRATCH_DATA_BASE_IDX = 1 # macro
regCP_RB_OFFSET = 0x2091 # macro
regCP_RB_OFFSET_BASE_IDX = 1 # macro
regCP_IB2_OFFSET = 0x2093 # macro
regCP_IB2_OFFSET_BASE_IDX = 1 # macro
regCP_IB2_PREAMBLE_BEGIN = 0x2096 # macro
regCP_IB2_PREAMBLE_BEGIN_BASE_IDX = 1 # macro
regCP_IB2_PREAMBLE_END = 0x2097 # macro
regCP_IB2_PREAMBLE_END_BASE_IDX = 1 # macro
regCP_DMA_ME_CMD_ADDR_LO = 0x209c # macro
regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX = 1 # macro
regCP_DMA_ME_CMD_ADDR_HI = 0x209d # macro
regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX = 1 # macro
regCP_DMA_PFP_CMD_ADDR_LO = 0x209e # macro
regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX = 1 # macro
regCP_DMA_PFP_CMD_ADDR_HI = 0x209f # macro
regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX = 1 # macro
regCP_APPEND_CMD_ADDR_LO = 0x20a0 # macro
regCP_APPEND_CMD_ADDR_LO_BASE_IDX = 1 # macro
regCP_APPEND_CMD_ADDR_HI = 0x20a1 # macro
regCP_APPEND_CMD_ADDR_HI_BASE_IDX = 1 # macro
regUCONFIG_RESERVED_REG0 = 0x20a2 # macro
regUCONFIG_RESERVED_REG0_BASE_IDX = 1 # macro
regUCONFIG_RESERVED_REG1 = 0x20a3 # macro
regUCONFIG_RESERVED_REG1_BASE_IDX = 1 # macro
regCP_PA_MSPRIM_COUNT_LO = 0x20a4 # macro
regCP_PA_MSPRIM_COUNT_LO_BASE_IDX = 1 # macro
regCP_PA_MSPRIM_COUNT_HI = 0x20a5 # macro
regCP_PA_MSPRIM_COUNT_HI_BASE_IDX = 1 # macro
regCP_GE_MSINVOC_COUNT_LO = 0x20a6 # macro
regCP_GE_MSINVOC_COUNT_LO_BASE_IDX = 1 # macro
regCP_GE_MSINVOC_COUNT_HI = 0x20a7 # macro
regCP_GE_MSINVOC_COUNT_HI_BASE_IDX = 1 # macro
regCP_IB1_CMD_BUFSZ = 0x20c0 # macro
regCP_IB1_CMD_BUFSZ_BASE_IDX = 1 # macro
regCP_IB2_CMD_BUFSZ = 0x20c1 # macro
regCP_IB2_CMD_BUFSZ_BASE_IDX = 1 # macro
regCP_ST_CMD_BUFSZ = 0x20c2 # macro
regCP_ST_CMD_BUFSZ_BASE_IDX = 1 # macro
regCP_IB1_BASE_LO = 0x20cc # macro
regCP_IB1_BASE_LO_BASE_IDX = 1 # macro
regCP_IB1_BASE_HI = 0x20cd # macro
regCP_IB1_BASE_HI_BASE_IDX = 1 # macro
regCP_IB1_BUFSZ = 0x20ce # macro
regCP_IB1_BUFSZ_BASE_IDX = 1 # macro
regCP_IB2_BASE_LO = 0x20cf # macro
regCP_IB2_BASE_LO_BASE_IDX = 1 # macro
regCP_IB2_BASE_HI = 0x20d0 # macro
regCP_IB2_BASE_HI_BASE_IDX = 1 # macro
regCP_IB2_BUFSZ = 0x20d1 # macro
regCP_IB2_BUFSZ_BASE_IDX = 1 # macro
regCP_ST_BASE_LO = 0x20d2 # macro
regCP_ST_BASE_LO_BASE_IDX = 1 # macro
regCP_ST_BASE_HI = 0x20d3 # macro
regCP_ST_BASE_HI_BASE_IDX = 1 # macro
regCP_ST_BUFSZ = 0x20d4 # macro
regCP_ST_BUFSZ_BASE_IDX = 1 # macro
regCP_EOP_DONE_EVENT_CNTL = 0x20d5 # macro
regCP_EOP_DONE_EVENT_CNTL_BASE_IDX = 1 # macro
regCP_EOP_DONE_DATA_CNTL = 0x20d6 # macro
regCP_EOP_DONE_DATA_CNTL_BASE_IDX = 1 # macro
regCP_EOP_DONE_CNTX_ID = 0x20d7 # macro
regCP_EOP_DONE_CNTX_ID_BASE_IDX = 1 # macro
regCP_DB_BASE_LO = 0x20d8 # macro
regCP_DB_BASE_LO_BASE_IDX = 1 # macro
regCP_DB_BASE_HI = 0x20d9 # macro
regCP_DB_BASE_HI_BASE_IDX = 1 # macro
regCP_DB_BUFSZ = 0x20da # macro
regCP_DB_BUFSZ_BASE_IDX = 1 # macro
regCP_DB_CMD_BUFSZ = 0x20db # macro
regCP_DB_CMD_BUFSZ_BASE_IDX = 1 # macro
regCP_PFP_COMPLETION_STATUS = 0x20ec # macro
regCP_PFP_COMPLETION_STATUS_BASE_IDX = 1 # macro
regCP_PRED_NOT_VISIBLE = 0x20ee # macro
regCP_PRED_NOT_VISIBLE_BASE_IDX = 1 # macro
regCP_PFP_METADATA_BASE_ADDR = 0x20f0 # macro
regCP_PFP_METADATA_BASE_ADDR_BASE_IDX = 1 # macro
regCP_PFP_METADATA_BASE_ADDR_HI = 0x20f1 # macro
regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX = 1 # macro
regCP_DRAW_INDX_INDR_ADDR = 0x20f4 # macro
regCP_DRAW_INDX_INDR_ADDR_BASE_IDX = 1 # macro
regCP_DRAW_INDX_INDR_ADDR_HI = 0x20f5 # macro
regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX = 1 # macro
regCP_DISPATCH_INDR_ADDR = 0x20f6 # macro
regCP_DISPATCH_INDR_ADDR_BASE_IDX = 1 # macro
regCP_DISPATCH_INDR_ADDR_HI = 0x20f7 # macro
regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX = 1 # macro
regCP_INDEX_BASE_ADDR = 0x20f8 # macro
regCP_INDEX_BASE_ADDR_BASE_IDX = 1 # macro
regCP_INDEX_BASE_ADDR_HI = 0x20f9 # macro
regCP_INDEX_BASE_ADDR_HI_BASE_IDX = 1 # macro
regCP_INDEX_TYPE = 0x20fa # macro
regCP_INDEX_TYPE_BASE_IDX = 1 # macro
regCP_GDS_BKUP_ADDR = 0x20fb # macro
regCP_GDS_BKUP_ADDR_BASE_IDX = 1 # macro
regCP_GDS_BKUP_ADDR_HI = 0x20fc # macro
regCP_GDS_BKUP_ADDR_HI_BASE_IDX = 1 # macro
regCP_SAMPLE_STATUS = 0x20fd # macro
regCP_SAMPLE_STATUS_BASE_IDX = 1 # macro
regCP_ME_COHER_CNTL = 0x20fe # macro
regCP_ME_COHER_CNTL_BASE_IDX = 1 # macro
regCP_ME_COHER_SIZE = 0x20ff # macro
regCP_ME_COHER_SIZE_BASE_IDX = 1 # macro
regCP_ME_COHER_SIZE_HI = 0x2100 # macro
regCP_ME_COHER_SIZE_HI_BASE_IDX = 1 # macro
regCP_ME_COHER_BASE = 0x2101 # macro
regCP_ME_COHER_BASE_BASE_IDX = 1 # macro
regCP_ME_COHER_BASE_HI = 0x2102 # macro
regCP_ME_COHER_BASE_HI_BASE_IDX = 1 # macro
regCP_ME_COHER_STATUS = 0x2103 # macro
regCP_ME_COHER_STATUS_BASE_IDX = 1 # macro
regRLC_GPM_PERF_COUNT_0 = 0x2140 # macro
regRLC_GPM_PERF_COUNT_0_BASE_IDX = 1 # macro
regRLC_GPM_PERF_COUNT_1 = 0x2141 # macro
regRLC_GPM_PERF_COUNT_1_BASE_IDX = 1 # macro
regGRBM_GFX_INDEX = 0x2200 # macro
regGRBM_GFX_INDEX_BASE_IDX = 1 # macro
regVGT_PRIMITIVE_TYPE = 0x2242 # macro
regVGT_PRIMITIVE_TYPE_BASE_IDX = 1 # macro
regVGT_INDEX_TYPE = 0x2243 # macro
regVGT_INDEX_TYPE_BASE_IDX = 1 # macro
regGE_MIN_VTX_INDX = 0x2249 # macro
regGE_MIN_VTX_INDX_BASE_IDX = 1 # macro
regGE_INDX_OFFSET = 0x224a # macro
regGE_INDX_OFFSET_BASE_IDX = 1 # macro
regGE_MULTI_PRIM_IB_RESET_EN = 0x224b # macro
regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX = 1 # macro
regVGT_NUM_INDICES = 0x224c # macro
regVGT_NUM_INDICES_BASE_IDX = 1 # macro
regVGT_NUM_INSTANCES = 0x224d # macro
regVGT_NUM_INSTANCES_BASE_IDX = 1 # macro
regVGT_TF_RING_SIZE = 0x224e # macro
regVGT_TF_RING_SIZE_BASE_IDX = 1 # macro
regVGT_HS_OFFCHIP_PARAM = 0x224f # macro
regVGT_HS_OFFCHIP_PARAM_BASE_IDX = 1 # macro
regVGT_TF_MEMORY_BASE = 0x2250 # macro
regVGT_TF_MEMORY_BASE_BASE_IDX = 1 # macro
regGE_MAX_VTX_INDX = 0x2259 # macro
regGE_MAX_VTX_INDX_BASE_IDX = 1 # macro
regVGT_INSTANCE_BASE_ID = 0x225a # macro
regVGT_INSTANCE_BASE_ID_BASE_IDX = 1 # macro
regGE_CNTL = 0x225b # macro
regGE_CNTL_BASE_IDX = 1 # macro
regGE_USER_VGPR1 = 0x225c # macro
regGE_USER_VGPR1_BASE_IDX = 1 # macro
regGE_USER_VGPR2 = 0x225d # macro
regGE_USER_VGPR2_BASE_IDX = 1 # macro
regGE_USER_VGPR3 = 0x225e # macro
regGE_USER_VGPR3_BASE_IDX = 1 # macro
regGE_STEREO_CNTL = 0x225f # macro
regGE_STEREO_CNTL_BASE_IDX = 1 # macro
regGE_PC_ALLOC = 0x2260 # macro
regGE_PC_ALLOC_BASE_IDX = 1 # macro
regVGT_TF_MEMORY_BASE_HI = 0x2261 # macro
regVGT_TF_MEMORY_BASE_HI_BASE_IDX = 1 # macro
regGE_USER_VGPR_EN = 0x2262 # macro
regGE_USER_VGPR_EN_BASE_IDX = 1 # macro
regGE_GS_FAST_LAUNCH_WG_DIM = 0x2264 # macro
regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX = 1 # macro
regGE_GS_FAST_LAUNCH_WG_DIM_1 = 0x2265 # macro
regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX = 1 # macro
regVGT_GS_OUT_PRIM_TYPE = 0x2266 # macro
regVGT_GS_OUT_PRIM_TYPE_BASE_IDX = 1 # macro
regPA_SU_LINE_STIPPLE_VALUE = 0x2280 # macro
regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX = 1 # macro
regPA_SC_LINE_STIPPLE_STATE = 0x2281 # macro
regPA_SC_LINE_STIPPLE_STATE_BASE_IDX = 1 # macro
regPA_SC_SCREEN_EXTENT_MIN_0 = 0x2284 # macro
regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX = 1 # macro
regPA_SC_SCREEN_EXTENT_MAX_0 = 0x2285 # macro
regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX = 1 # macro
regPA_SC_SCREEN_EXTENT_MIN_1 = 0x2286 # macro
regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX = 1 # macro
regPA_SC_SCREEN_EXTENT_MAX_1 = 0x228b # macro
regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX = 1 # macro
regPA_SC_P3D_TRAP_SCREEN_HV_EN = 0x22a0 # macro
regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro
regPA_SC_P3D_TRAP_SCREEN_H = 0x22a1 # macro
regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro
regPA_SC_P3D_TRAP_SCREEN_V = 0x22a2 # macro
regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro
regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE = 0x22a3 # macro
regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro
regPA_SC_P3D_TRAP_SCREEN_COUNT = 0x22a4 # macro
regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro
regPA_SC_HP3D_TRAP_SCREEN_HV_EN = 0x22a8 # macro
regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro
regPA_SC_HP3D_TRAP_SCREEN_H = 0x22a9 # macro
regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro
regPA_SC_HP3D_TRAP_SCREEN_V = 0x22aa # macro
regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro
regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE = 0x22ab # macro
regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro
regPA_SC_HP3D_TRAP_SCREEN_COUNT = 0x22ac # macro
regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro
regPA_SC_TRAP_SCREEN_HV_EN = 0x22b0 # macro
regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro
regPA_SC_TRAP_SCREEN_H = 0x22b1 # macro
regPA_SC_TRAP_SCREEN_H_BASE_IDX = 1 # macro
regPA_SC_TRAP_SCREEN_V = 0x22b2 # macro
regPA_SC_TRAP_SCREEN_V_BASE_IDX = 1 # macro
regPA_SC_TRAP_SCREEN_OCCURRENCE = 0x22b3 # macro
regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro
regPA_SC_TRAP_SCREEN_COUNT = 0x22b4 # macro
regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_USERDATA_0 = 0x2340 # macro
regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_USERDATA_1 = 0x2341 # macro
regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_USERDATA_2 = 0x2342 # macro
regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_USERDATA_3 = 0x2343 # macro
regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_USERDATA_4 = 0x2344 # macro
regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_USERDATA_5 = 0x2345 # macro
regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_USERDATA_6 = 0x2346 # macro
regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_USERDATA_7 = 0x2347 # macro
regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX = 1 # macro
regSQC_CACHES = 0x2348 # macro
regSQC_CACHES_BASE_IDX = 1 # macro
regTA_CS_BC_BASE_ADDR = 0x2380 # macro
regTA_CS_BC_BASE_ADDR_BASE_IDX = 1 # macro
regTA_CS_BC_BASE_ADDR_HI = 0x2381 # macro
regTA_CS_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro
regDB_OCCLUSION_COUNT0_LOW = 0x23c0 # macro
regDB_OCCLUSION_COUNT0_LOW_BASE_IDX = 1 # macro
regDB_OCCLUSION_COUNT0_HI = 0x23c1 # macro
regDB_OCCLUSION_COUNT0_HI_BASE_IDX = 1 # macro
regDB_OCCLUSION_COUNT1_LOW = 0x23c2 # macro
regDB_OCCLUSION_COUNT1_LOW_BASE_IDX = 1 # macro
regDB_OCCLUSION_COUNT1_HI = 0x23c3 # macro
regDB_OCCLUSION_COUNT1_HI_BASE_IDX = 1 # macro
regDB_OCCLUSION_COUNT2_LOW = 0x23c4 # macro
regDB_OCCLUSION_COUNT2_LOW_BASE_IDX = 1 # macro
regDB_OCCLUSION_COUNT2_HI = 0x23c5 # macro
regDB_OCCLUSION_COUNT2_HI_BASE_IDX = 1 # macro
regDB_OCCLUSION_COUNT3_LOW = 0x23c6 # macro
regDB_OCCLUSION_COUNT3_LOW_BASE_IDX = 1 # macro
regDB_OCCLUSION_COUNT3_HI = 0x23c7 # macro
regDB_OCCLUSION_COUNT3_HI_BASE_IDX = 1 # macro
regGDS_RD_ADDR = 0x2400 # macro
regGDS_RD_ADDR_BASE_IDX = 1 # macro
regGDS_RD_DATA = 0x2401 # macro
regGDS_RD_DATA_BASE_IDX = 1 # macro
regGDS_RD_BURST_ADDR = 0x2402 # macro
regGDS_RD_BURST_ADDR_BASE_IDX = 1 # macro
regGDS_RD_BURST_COUNT = 0x2403 # macro
regGDS_RD_BURST_COUNT_BASE_IDX = 1 # macro
regGDS_RD_BURST_DATA = 0x2404 # macro
regGDS_RD_BURST_DATA_BASE_IDX = 1 # macro
regGDS_WR_ADDR = 0x2405 # macro
regGDS_WR_ADDR_BASE_IDX = 1 # macro
regGDS_WR_DATA = 0x2406 # macro
regGDS_WR_DATA_BASE_IDX = 1 # macro
regGDS_WR_BURST_ADDR = 0x2407 # macro
regGDS_WR_BURST_ADDR_BASE_IDX = 1 # macro
regGDS_WR_BURST_DATA = 0x2408 # macro
regGDS_WR_BURST_DATA_BASE_IDX = 1 # macro
regGDS_WRITE_COMPLETE = 0x2409 # macro
regGDS_WRITE_COMPLETE_BASE_IDX = 1 # macro
regGDS_ATOM_CNTL = 0x240a # macro
regGDS_ATOM_CNTL_BASE_IDX = 1 # macro
regGDS_ATOM_COMPLETE = 0x240b # macro
regGDS_ATOM_COMPLETE_BASE_IDX = 1 # macro
regGDS_ATOM_BASE = 0x240c # macro
regGDS_ATOM_BASE_BASE_IDX = 1 # macro
regGDS_ATOM_SIZE = 0x240d # macro
regGDS_ATOM_SIZE_BASE_IDX = 1 # macro
regGDS_ATOM_OFFSET0 = 0x240e # macro
regGDS_ATOM_OFFSET0_BASE_IDX = 1 # macro
regGDS_ATOM_OFFSET1 = 0x240f # macro
regGDS_ATOM_OFFSET1_BASE_IDX = 1 # macro
regGDS_ATOM_DST = 0x2410 # macro
regGDS_ATOM_DST_BASE_IDX = 1 # macro
regGDS_ATOM_OP = 0x2411 # macro
regGDS_ATOM_OP_BASE_IDX = 1 # macro
regGDS_ATOM_SRC0 = 0x2412 # macro
regGDS_ATOM_SRC0_BASE_IDX = 1 # macro
regGDS_ATOM_SRC0_U = 0x2413 # macro
regGDS_ATOM_SRC0_U_BASE_IDX = 1 # macro
regGDS_ATOM_SRC1 = 0x2414 # macro
regGDS_ATOM_SRC1_BASE_IDX = 1 # macro
regGDS_ATOM_SRC1_U = 0x2415 # macro
regGDS_ATOM_SRC1_U_BASE_IDX = 1 # macro
regGDS_ATOM_READ0 = 0x2416 # macro
regGDS_ATOM_READ0_BASE_IDX = 1 # macro
regGDS_ATOM_READ0_U = 0x2417 # macro
regGDS_ATOM_READ0_U_BASE_IDX = 1 # macro
regGDS_ATOM_READ1 = 0x2418 # macro
regGDS_ATOM_READ1_BASE_IDX = 1 # macro
regGDS_ATOM_READ1_U = 0x2419 # macro
regGDS_ATOM_READ1_U_BASE_IDX = 1 # macro
regGDS_GWS_RESOURCE_CNTL = 0x241a # macro
regGDS_GWS_RESOURCE_CNTL_BASE_IDX = 1 # macro
regGDS_GWS_RESOURCE = 0x241b # macro
regGDS_GWS_RESOURCE_BASE_IDX = 1 # macro
regGDS_GWS_RESOURCE_CNT = 0x241c # macro
regGDS_GWS_RESOURCE_CNT_BASE_IDX = 1 # macro
regGDS_OA_CNTL = 0x241d # macro
regGDS_OA_CNTL_BASE_IDX = 1 # macro
regGDS_OA_COUNTER = 0x241e # macro
regGDS_OA_COUNTER_BASE_IDX = 1 # macro
regGDS_OA_ADDRESS = 0x241f # macro
regGDS_OA_ADDRESS_BASE_IDX = 1 # macro
regGDS_OA_INCDEC = 0x2420 # macro
regGDS_OA_INCDEC_BASE_IDX = 1 # macro
regGDS_OA_RING_SIZE = 0x2421 # macro
regGDS_OA_RING_SIZE_BASE_IDX = 1 # macro
regGDS_STRMOUT_DWORDS_WRITTEN_0 = 0x2422 # macro
regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX = 1 # macro
regGDS_STRMOUT_DWORDS_WRITTEN_1 = 0x2423 # macro
regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX = 1 # macro
regGDS_STRMOUT_DWORDS_WRITTEN_2 = 0x2424 # macro
regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX = 1 # macro
regGDS_STRMOUT_DWORDS_WRITTEN_3 = 0x2425 # macro
regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX = 1 # macro
regGDS_GS_0 = 0x2426 # macro
regGDS_GS_0_BASE_IDX = 1 # macro
regGDS_GS_1 = 0x2427 # macro
regGDS_GS_1_BASE_IDX = 1 # macro
regGDS_GS_2 = 0x2428 # macro
regGDS_GS_2_BASE_IDX = 1 # macro
regGDS_GS_3 = 0x2429 # macro
regGDS_GS_3_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_NEEDED_0_LO = 0x242a # macro
regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_NEEDED_0_HI = 0x242b # macro
regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_0_LO = 0x242c # macro
regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_0_HI = 0x242d # macro
regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_NEEDED_1_LO = 0x242e # macro
regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_NEEDED_1_HI = 0x242f # macro
regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_1_LO = 0x2430 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_1_HI = 0x2431 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_NEEDED_2_LO = 0x2432 # macro
regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_NEEDED_2_HI = 0x2433 # macro
regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_2_LO = 0x2434 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_2_HI = 0x2435 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_NEEDED_3_LO = 0x2436 # macro
regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_NEEDED_3_HI = 0x2437 # macro
regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_3_LO = 0x2438 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX = 1 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_3_HI = 0x2439 # macro
regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX = 1 # macro
regSPI_CONFIG_CNTL = 0x2440 # macro
regSPI_CONFIG_CNTL_BASE_IDX = 1 # macro
regSPI_CONFIG_CNTL_1 = 0x2441 # macro
regSPI_CONFIG_CNTL_1_BASE_IDX = 1 # macro
regSPI_CONFIG_CNTL_2 = 0x2442 # macro
regSPI_CONFIG_CNTL_2_BASE_IDX = 1 # macro
regSPI_WAVE_LIMIT_CNTL = 0x2443 # macro
regSPI_WAVE_LIMIT_CNTL_BASE_IDX = 1 # macro
regSPI_GS_THROTTLE_CNTL1 = 0x2444 # macro
regSPI_GS_THROTTLE_CNTL1_BASE_IDX = 1 # macro
regSPI_GS_THROTTLE_CNTL2 = 0x2445 # macro
regSPI_GS_THROTTLE_CNTL2_BASE_IDX = 1 # macro
regSPI_ATTRIBUTE_RING_BASE = 0x2446 # macro
regSPI_ATTRIBUTE_RING_BASE_BASE_IDX = 1 # macro
regSPI_ATTRIBUTE_RING_SIZE = 0x2447 # macro
regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX = 1 # macro
regCP_MES_PRGRM_CNTR_START = 0x2800 # macro
regCP_MES_PRGRM_CNTR_START_BASE_IDX = 1 # macro
regCP_MES_INTR_ROUTINE_START = 0x2801 # macro
regCP_MES_INTR_ROUTINE_START_BASE_IDX = 1 # macro
regCP_MES_MTVEC_LO = 0x2801 # macro
regCP_MES_MTVEC_LO_BASE_IDX = 1 # macro
regCP_MES_INTR_ROUTINE_START_HI = 0x2802 # macro
regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX = 1 # macro
regCP_MES_MTVEC_HI = 0x2802 # macro
regCP_MES_MTVEC_HI_BASE_IDX = 1 # macro
regCP_MES_CNTL = 0x2807 # macro
regCP_MES_CNTL_BASE_IDX = 1 # macro
regCP_MES_PIPE_PRIORITY_CNTS = 0x2808 # macro
regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX = 1 # macro
regCP_MES_PIPE0_PRIORITY = 0x2809 # macro
regCP_MES_PIPE0_PRIORITY_BASE_IDX = 1 # macro
regCP_MES_PIPE1_PRIORITY = 0x280a # macro
regCP_MES_PIPE1_PRIORITY_BASE_IDX = 1 # macro
regCP_MES_PIPE2_PRIORITY = 0x280b # macro
regCP_MES_PIPE2_PRIORITY_BASE_IDX = 1 # macro
regCP_MES_PIPE3_PRIORITY = 0x280c # macro
regCP_MES_PIPE3_PRIORITY_BASE_IDX = 1 # macro
regCP_MES_HEADER_DUMP = 0x280d # macro
regCP_MES_HEADER_DUMP_BASE_IDX = 1 # macro
regCP_MES_MIE_LO = 0x280e # macro
regCP_MES_MIE_LO_BASE_IDX = 1 # macro
regCP_MES_MIE_HI = 0x280f # macro
regCP_MES_MIE_HI_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT = 0x2810 # macro
regCP_MES_INTERRUPT_BASE_IDX = 1 # macro
regCP_MES_SCRATCH_INDEX = 0x2811 # macro
regCP_MES_SCRATCH_INDEX_BASE_IDX = 1 # macro
regCP_MES_SCRATCH_DATA = 0x2812 # macro
regCP_MES_SCRATCH_DATA_BASE_IDX = 1 # macro
regCP_MES_INSTR_PNTR = 0x2813 # macro
regCP_MES_INSTR_PNTR_BASE_IDX = 1 # macro
regCP_MES_MSCRATCH_HI = 0x2814 # macro
regCP_MES_MSCRATCH_HI_BASE_IDX = 1 # macro
regCP_MES_MSCRATCH_LO = 0x2815 # macro
regCP_MES_MSCRATCH_LO_BASE_IDX = 1 # macro
regCP_MES_MSTATUS_LO = 0x2816 # macro
regCP_MES_MSTATUS_LO_BASE_IDX = 1 # macro
regCP_MES_MSTATUS_HI = 0x2817 # macro
regCP_MES_MSTATUS_HI_BASE_IDX = 1 # macro
regCP_MES_MEPC_LO = 0x2818 # macro
regCP_MES_MEPC_LO_BASE_IDX = 1 # macro
regCP_MES_MEPC_HI = 0x2819 # macro
regCP_MES_MEPC_HI_BASE_IDX = 1 # macro
regCP_MES_MCAUSE_LO = 0x281a # macro
regCP_MES_MCAUSE_LO_BASE_IDX = 1 # macro
regCP_MES_MCAUSE_HI = 0x281b # macro
regCP_MES_MCAUSE_HI_BASE_IDX = 1 # macro
regCP_MES_MBADADDR_LO = 0x281c # macro
regCP_MES_MBADADDR_LO_BASE_IDX = 1 # macro
regCP_MES_MBADADDR_HI = 0x281d # macro
regCP_MES_MBADADDR_HI_BASE_IDX = 1 # macro
regCP_MES_MIP_LO = 0x281e # macro
regCP_MES_MIP_LO_BASE_IDX = 1 # macro
regCP_MES_MIP_HI = 0x281f # macro
regCP_MES_MIP_HI_BASE_IDX = 1 # macro
regCP_MES_IC_OP_CNTL = 0x2820 # macro
regCP_MES_IC_OP_CNTL_BASE_IDX = 1 # macro
regCP_MES_MCYCLE_LO = 0x2826 # macro
regCP_MES_MCYCLE_LO_BASE_IDX = 1 # macro
regCP_MES_MCYCLE_HI = 0x2827 # macro
regCP_MES_MCYCLE_HI_BASE_IDX = 1 # macro
regCP_MES_MTIME_LO = 0x2828 # macro
regCP_MES_MTIME_LO_BASE_IDX = 1 # macro
regCP_MES_MTIME_HI = 0x2829 # macro
regCP_MES_MTIME_HI_BASE_IDX = 1 # macro
regCP_MES_MINSTRET_LO = 0x282a # macro
regCP_MES_MINSTRET_LO_BASE_IDX = 1 # macro
regCP_MES_MINSTRET_HI = 0x282b # macro
regCP_MES_MINSTRET_HI_BASE_IDX = 1 # macro
regCP_MES_MISA_LO = 0x282c # macro
regCP_MES_MISA_LO_BASE_IDX = 1 # macro
regCP_MES_MISA_HI = 0x282d # macro
regCP_MES_MISA_HI_BASE_IDX = 1 # macro
regCP_MES_MVENDORID_LO = 0x282e # macro
regCP_MES_MVENDORID_LO_BASE_IDX = 1 # macro
regCP_MES_MVENDORID_HI = 0x282f # macro
regCP_MES_MVENDORID_HI_BASE_IDX = 1 # macro
regCP_MES_MARCHID_LO = 0x2830 # macro
regCP_MES_MARCHID_LO_BASE_IDX = 1 # macro
regCP_MES_MARCHID_HI = 0x2831 # macro
regCP_MES_MARCHID_HI_BASE_IDX = 1 # macro
regCP_MES_MIMPID_LO = 0x2832 # macro
regCP_MES_MIMPID_LO_BASE_IDX = 1 # macro
regCP_MES_MIMPID_HI = 0x2833 # macro
regCP_MES_MIMPID_HI_BASE_IDX = 1 # macro
regCP_MES_MHARTID_LO = 0x2834 # macro
regCP_MES_MHARTID_LO_BASE_IDX = 1 # macro
regCP_MES_MHARTID_HI = 0x2835 # macro
regCP_MES_MHARTID_HI_BASE_IDX = 1 # macro
regCP_MES_DC_BASE_CNTL = 0x2836 # macro
regCP_MES_DC_BASE_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_OP_CNTL = 0x2837 # macro
regCP_MES_DC_OP_CNTL_BASE_IDX = 1 # macro
regCP_MES_MTIMECMP_LO = 0x2838 # macro
regCP_MES_MTIMECMP_LO_BASE_IDX = 1 # macro
regCP_MES_MTIMECMP_HI = 0x2839 # macro
regCP_MES_MTIMECMP_HI_BASE_IDX = 1 # macro
regCP_MES_PROCESS_QUANTUM_PIPE0 = 0x283a # macro
regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX = 1 # macro
regCP_MES_PROCESS_QUANTUM_PIPE1 = 0x283b # macro
regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX = 1 # macro
regCP_MES_DOORBELL_CONTROL1 = 0x283c # macro
regCP_MES_DOORBELL_CONTROL1_BASE_IDX = 1 # macro
regCP_MES_DOORBELL_CONTROL2 = 0x283d # macro
regCP_MES_DOORBELL_CONTROL2_BASE_IDX = 1 # macro
regCP_MES_DOORBELL_CONTROL3 = 0x283e # macro
regCP_MES_DOORBELL_CONTROL3_BASE_IDX = 1 # macro
regCP_MES_DOORBELL_CONTROL4 = 0x283f # macro
regCP_MES_DOORBELL_CONTROL4_BASE_IDX = 1 # macro
regCP_MES_DOORBELL_CONTROL5 = 0x2840 # macro
regCP_MES_DOORBELL_CONTROL5_BASE_IDX = 1 # macro
regCP_MES_DOORBELL_CONTROL6 = 0x2841 # macro
regCP_MES_DOORBELL_CONTROL6_BASE_IDX = 1 # macro
regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR = 0x2842 # macro
regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX = 1 # macro
regCP_MES_GP0_LO = 0x2843 # macro
regCP_MES_GP0_LO_BASE_IDX = 1 # macro
regCP_MES_GP0_HI = 0x2844 # macro
regCP_MES_GP0_HI_BASE_IDX = 1 # macro
regCP_MES_GP1_LO = 0x2845 # macro
regCP_MES_GP1_LO_BASE_IDX = 1 # macro
regCP_MES_GP1_HI = 0x2846 # macro
regCP_MES_GP1_HI_BASE_IDX = 1 # macro
regCP_MES_GP2_LO = 0x2847 # macro
regCP_MES_GP2_LO_BASE_IDX = 1 # macro
regCP_MES_GP2_HI = 0x2848 # macro
regCP_MES_GP2_HI_BASE_IDX = 1 # macro
regCP_MES_GP3_LO = 0x2849 # macro
regCP_MES_GP3_LO_BASE_IDX = 1 # macro
regCP_MES_GP3_HI = 0x284a # macro
regCP_MES_GP3_HI_BASE_IDX = 1 # macro
regCP_MES_GP4_LO = 0x284b # macro
regCP_MES_GP4_LO_BASE_IDX = 1 # macro
regCP_MES_GP4_HI = 0x284c # macro
regCP_MES_GP4_HI_BASE_IDX = 1 # macro
regCP_MES_GP5_LO = 0x284d # macro
regCP_MES_GP5_LO_BASE_IDX = 1 # macro
regCP_MES_GP5_HI = 0x284e # macro
regCP_MES_GP5_HI_BASE_IDX = 1 # macro
regCP_MES_GP6_LO = 0x284f # macro
regCP_MES_GP6_LO_BASE_IDX = 1 # macro
regCP_MES_GP6_HI = 0x2850 # macro
regCP_MES_GP6_HI_BASE_IDX = 1 # macro
regCP_MES_GP7_LO = 0x2851 # macro
regCP_MES_GP7_LO_BASE_IDX = 1 # macro
regCP_MES_GP7_HI = 0x2852 # macro
regCP_MES_GP7_HI_BASE_IDX = 1 # macro
regCP_MES_GP8_LO = 0x2853 # macro
regCP_MES_GP8_LO_BASE_IDX = 1 # macro
regCP_MES_GP8_HI = 0x2854 # macro
regCP_MES_GP8_HI_BASE_IDX = 1 # macro
regCP_MES_GP9_LO = 0x2855 # macro
regCP_MES_GP9_LO_BASE_IDX = 1 # macro
regCP_MES_GP9_HI = 0x2856 # macro
regCP_MES_GP9_HI_BASE_IDX = 1 # macro
regCP_MES_LOCAL_BASE0_LO = 0x2883 # macro
regCP_MES_LOCAL_BASE0_LO_BASE_IDX = 1 # macro
regCP_MES_LOCAL_BASE0_HI = 0x2884 # macro
regCP_MES_LOCAL_BASE0_HI_BASE_IDX = 1 # macro
regCP_MES_LOCAL_MASK0_LO = 0x2885 # macro
regCP_MES_LOCAL_MASK0_LO_BASE_IDX = 1 # macro
regCP_MES_LOCAL_MASK0_HI = 0x2886 # macro
regCP_MES_LOCAL_MASK0_HI_BASE_IDX = 1 # macro
regCP_MES_LOCAL_APERTURE = 0x2887 # macro
regCP_MES_LOCAL_APERTURE_BASE_IDX = 1 # macro
regCP_MES_LOCAL_INSTR_BASE_LO = 0x2888 # macro
regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro
regCP_MES_LOCAL_INSTR_BASE_HI = 0x2889 # macro
regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro
regCP_MES_LOCAL_INSTR_MASK_LO = 0x288a # macro
regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro
regCP_MES_LOCAL_INSTR_MASK_HI = 0x288b # macro
regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro
regCP_MES_LOCAL_INSTR_APERTURE = 0x288c # macro
regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro
regCP_MES_LOCAL_SCRATCH_APERTURE = 0x288d # macro
regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro
regCP_MES_LOCAL_SCRATCH_BASE_LO = 0x288e # macro
regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro
regCP_MES_LOCAL_SCRATCH_BASE_HI = 0x288f # macro
regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro
regCP_MES_PERFCOUNT_CNTL = 0x2899 # macro
regCP_MES_PERFCOUNT_CNTL_BASE_IDX = 1 # macro
regCP_MES_PENDING_INTERRUPT = 0x289a # macro
regCP_MES_PENDING_INTERRUPT_BASE_IDX = 1 # macro
regCP_MES_PRGRM_CNTR_START_HI = 0x289d # macro
regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_16 = 0x289f # macro
regCP_MES_INTERRUPT_DATA_16_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_17 = 0x28a0 # macro
regCP_MES_INTERRUPT_DATA_17_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_18 = 0x28a1 # macro
regCP_MES_INTERRUPT_DATA_18_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_19 = 0x28a2 # macro
regCP_MES_INTERRUPT_DATA_19_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_20 = 0x28a3 # macro
regCP_MES_INTERRUPT_DATA_20_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_21 = 0x28a4 # macro
regCP_MES_INTERRUPT_DATA_21_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_22 = 0x28a5 # macro
regCP_MES_INTERRUPT_DATA_22_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_23 = 0x28a6 # macro
regCP_MES_INTERRUPT_DATA_23_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_24 = 0x28a7 # macro
regCP_MES_INTERRUPT_DATA_24_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_25 = 0x28a8 # macro
regCP_MES_INTERRUPT_DATA_25_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_26 = 0x28a9 # macro
regCP_MES_INTERRUPT_DATA_26_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_27 = 0x28aa # macro
regCP_MES_INTERRUPT_DATA_27_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_28 = 0x28ab # macro
regCP_MES_INTERRUPT_DATA_28_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_29 = 0x28ac # macro
regCP_MES_INTERRUPT_DATA_29_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_30 = 0x28ad # macro
regCP_MES_INTERRUPT_DATA_30_BASE_IDX = 1 # macro
regCP_MES_INTERRUPT_DATA_31 = 0x28ae # macro
regCP_MES_INTERRUPT_DATA_31_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE0_BASE = 0x28af # macro
regCP_MES_DC_APERTURE0_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE0_MASK = 0x28b0 # macro
regCP_MES_DC_APERTURE0_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE0_CNTL = 0x28b1 # macro
regCP_MES_DC_APERTURE0_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE1_BASE = 0x28b2 # macro
regCP_MES_DC_APERTURE1_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE1_MASK = 0x28b3 # macro
regCP_MES_DC_APERTURE1_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE1_CNTL = 0x28b4 # macro
regCP_MES_DC_APERTURE1_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE2_BASE = 0x28b5 # macro
regCP_MES_DC_APERTURE2_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE2_MASK = 0x28b6 # macro
regCP_MES_DC_APERTURE2_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE2_CNTL = 0x28b7 # macro
regCP_MES_DC_APERTURE2_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE3_BASE = 0x28b8 # macro
regCP_MES_DC_APERTURE3_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE3_MASK = 0x28b9 # macro
regCP_MES_DC_APERTURE3_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE3_CNTL = 0x28ba # macro
regCP_MES_DC_APERTURE3_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE4_BASE = 0x28bb # macro
regCP_MES_DC_APERTURE4_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE4_MASK = 0x28bc # macro
regCP_MES_DC_APERTURE4_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE4_CNTL = 0x28bd # macro
regCP_MES_DC_APERTURE4_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE5_BASE = 0x28be # macro
regCP_MES_DC_APERTURE5_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE5_MASK = 0x28bf # macro
regCP_MES_DC_APERTURE5_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE5_CNTL = 0x28c0 # macro
regCP_MES_DC_APERTURE5_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE6_BASE = 0x28c1 # macro
regCP_MES_DC_APERTURE6_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE6_MASK = 0x28c2 # macro
regCP_MES_DC_APERTURE6_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE6_CNTL = 0x28c3 # macro
regCP_MES_DC_APERTURE6_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE7_BASE = 0x28c4 # macro
regCP_MES_DC_APERTURE7_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE7_MASK = 0x28c5 # macro
regCP_MES_DC_APERTURE7_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE7_CNTL = 0x28c6 # macro
regCP_MES_DC_APERTURE7_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE8_BASE = 0x28c7 # macro
regCP_MES_DC_APERTURE8_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE8_MASK = 0x28c8 # macro
regCP_MES_DC_APERTURE8_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE8_CNTL = 0x28c9 # macro
regCP_MES_DC_APERTURE8_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE9_BASE = 0x28ca # macro
regCP_MES_DC_APERTURE9_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE9_MASK = 0x28cb # macro
regCP_MES_DC_APERTURE9_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE9_CNTL = 0x28cc # macro
regCP_MES_DC_APERTURE9_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE10_BASE = 0x28cd # macro
regCP_MES_DC_APERTURE10_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE10_MASK = 0x28ce # macro
regCP_MES_DC_APERTURE10_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE10_CNTL = 0x28cf # macro
regCP_MES_DC_APERTURE10_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE11_BASE = 0x28d0 # macro
regCP_MES_DC_APERTURE11_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE11_MASK = 0x28d1 # macro
regCP_MES_DC_APERTURE11_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE11_CNTL = 0x28d2 # macro
regCP_MES_DC_APERTURE11_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE12_BASE = 0x28d3 # macro
regCP_MES_DC_APERTURE12_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE12_MASK = 0x28d4 # macro
regCP_MES_DC_APERTURE12_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE12_CNTL = 0x28d5 # macro
regCP_MES_DC_APERTURE12_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE13_BASE = 0x28d6 # macro
regCP_MES_DC_APERTURE13_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE13_MASK = 0x28d7 # macro
regCP_MES_DC_APERTURE13_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE13_CNTL = 0x28d8 # macro
regCP_MES_DC_APERTURE13_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE14_BASE = 0x28d9 # macro
regCP_MES_DC_APERTURE14_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE14_MASK = 0x28da # macro
regCP_MES_DC_APERTURE14_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE14_CNTL = 0x28db # macro
regCP_MES_DC_APERTURE14_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE15_BASE = 0x28dc # macro
regCP_MES_DC_APERTURE15_BASE_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE15_MASK = 0x28dd # macro
regCP_MES_DC_APERTURE15_MASK_BASE_IDX = 1 # macro
regCP_MES_DC_APERTURE15_CNTL = 0x28de # macro
regCP_MES_DC_APERTURE15_CNTL_BASE_IDX = 1 # macro
regCP_MEC_RS64_PRGRM_CNTR_START = 0x2900 # macro
regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX = 1 # macro
regCP_MEC_MTVEC_LO = 0x2901 # macro
regCP_MEC_MTVEC_LO_BASE_IDX = 1 # macro
regCP_MEC_MTVEC_HI = 0x2902 # macro
regCP_MEC_MTVEC_HI_BASE_IDX = 1 # macro
regCP_MEC_ISA_CNTL = 0x2903 # macro
regCP_MEC_ISA_CNTL_BASE_IDX = 1 # macro
regCP_MEC_RS64_CNTL = 0x2904 # macro
regCP_MEC_RS64_CNTL_BASE_IDX = 1 # macro
regCP_MEC_MIE_LO = 0x2905 # macro
regCP_MEC_MIE_LO_BASE_IDX = 1 # macro
regCP_MEC_MIE_HI = 0x2906 # macro
regCP_MEC_MIE_HI_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT = 0x2907 # macro
regCP_MEC_RS64_INTERRUPT_BASE_IDX = 1 # macro
regCP_MEC_RS64_INSTR_PNTR = 0x2908 # macro
regCP_MEC_RS64_INSTR_PNTR_BASE_IDX = 1 # macro
regCP_MEC_MIP_LO = 0x2909 # macro
regCP_MEC_MIP_LO_BASE_IDX = 1 # macro
regCP_MEC_MIP_HI = 0x290a # macro
regCP_MEC_MIP_HI_BASE_IDX = 1 # macro
regCP_MEC_DC_BASE_CNTL = 0x290b # macro
regCP_MEC_DC_BASE_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_OP_CNTL = 0x290c # macro
regCP_MEC_DC_OP_CNTL_BASE_IDX = 1 # macro
regCP_MEC_MTIMECMP_LO = 0x290d # macro
regCP_MEC_MTIMECMP_LO_BASE_IDX = 1 # macro
regCP_MEC_MTIMECMP_HI = 0x290e # macro
regCP_MEC_MTIMECMP_HI_BASE_IDX = 1 # macro
regCP_MEC_GP0_LO = 0x2910 # macro
regCP_MEC_GP0_LO_BASE_IDX = 1 # macro
regCP_MEC_GP0_HI = 0x2911 # macro
regCP_MEC_GP0_HI_BASE_IDX = 1 # macro
regCP_MEC_GP1_LO = 0x2912 # macro
regCP_MEC_GP1_LO_BASE_IDX = 1 # macro
regCP_MEC_GP1_HI = 0x2913 # macro
regCP_MEC_GP1_HI_BASE_IDX = 1 # macro
regCP_MEC_GP2_LO = 0x2914 # macro
regCP_MEC_GP2_LO_BASE_IDX = 1 # macro
regCP_MEC_GP2_HI = 0x2915 # macro
regCP_MEC_GP2_HI_BASE_IDX = 1 # macro
regCP_MEC_GP3_LO = 0x2916 # macro
regCP_MEC_GP3_LO_BASE_IDX = 1 # macro
regCP_MEC_GP3_HI = 0x2917 # macro
regCP_MEC_GP3_HI_BASE_IDX = 1 # macro
regCP_MEC_GP4_LO = 0x2918 # macro
regCP_MEC_GP4_LO_BASE_IDX = 1 # macro
regCP_MEC_GP4_HI = 0x2919 # macro
regCP_MEC_GP4_HI_BASE_IDX = 1 # macro
regCP_MEC_GP5_LO = 0x291a # macro
regCP_MEC_GP5_LO_BASE_IDX = 1 # macro
regCP_MEC_GP5_HI = 0x291b # macro
regCP_MEC_GP5_HI_BASE_IDX = 1 # macro
regCP_MEC_GP6_LO = 0x291c # macro
regCP_MEC_GP6_LO_BASE_IDX = 1 # macro
regCP_MEC_GP6_HI = 0x291d # macro
regCP_MEC_GP6_HI_BASE_IDX = 1 # macro
regCP_MEC_GP7_LO = 0x291e # macro
regCP_MEC_GP7_LO_BASE_IDX = 1 # macro
regCP_MEC_GP7_HI = 0x291f # macro
regCP_MEC_GP7_HI_BASE_IDX = 1 # macro
regCP_MEC_GP8_LO = 0x2920 # macro
regCP_MEC_GP8_LO_BASE_IDX = 1 # macro
regCP_MEC_GP8_HI = 0x2921 # macro
regCP_MEC_GP8_HI_BASE_IDX = 1 # macro
regCP_MEC_GP9_LO = 0x2922 # macro
regCP_MEC_GP9_LO_BASE_IDX = 1 # macro
regCP_MEC_GP9_HI = 0x2923 # macro
regCP_MEC_GP9_HI_BASE_IDX = 1 # macro
regCP_MEC_LOCAL_BASE0_LO = 0x2927 # macro
regCP_MEC_LOCAL_BASE0_LO_BASE_IDX = 1 # macro
regCP_MEC_LOCAL_BASE0_HI = 0x2928 # macro
regCP_MEC_LOCAL_BASE0_HI_BASE_IDX = 1 # macro
regCP_MEC_LOCAL_MASK0_LO = 0x2929 # macro
regCP_MEC_LOCAL_MASK0_LO_BASE_IDX = 1 # macro
regCP_MEC_LOCAL_MASK0_HI = 0x292a # macro
regCP_MEC_LOCAL_MASK0_HI_BASE_IDX = 1 # macro
regCP_MEC_LOCAL_APERTURE = 0x292b # macro
regCP_MEC_LOCAL_APERTURE_BASE_IDX = 1 # macro
regCP_MEC_LOCAL_INSTR_BASE_LO = 0x292c # macro
regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro
regCP_MEC_LOCAL_INSTR_BASE_HI = 0x292d # macro
regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro
regCP_MEC_LOCAL_INSTR_MASK_LO = 0x292e # macro
regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro
regCP_MEC_LOCAL_INSTR_MASK_HI = 0x292f # macro
regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro
regCP_MEC_LOCAL_INSTR_APERTURE = 0x2930 # macro
regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro
regCP_MEC_LOCAL_SCRATCH_APERTURE = 0x2931 # macro
regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro
regCP_MEC_LOCAL_SCRATCH_BASE_LO = 0x2932 # macro
regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro
regCP_MEC_LOCAL_SCRATCH_BASE_HI = 0x2933 # macro
regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro
regCP_MEC_RS64_PERFCOUNT_CNTL = 0x2934 # macro
regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX = 1 # macro
regCP_MEC_RS64_PENDING_INTERRUPT = 0x2935 # macro
regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX = 1 # macro
regCP_MEC_RS64_PRGRM_CNTR_START_HI = 0x2938 # macro
regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_16 = 0x293a # macro
regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_17 = 0x293b # macro
regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_18 = 0x293c # macro
regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_19 = 0x293d # macro
regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_20 = 0x293e # macro
regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_21 = 0x293f # macro
regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_22 = 0x2940 # macro
regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_23 = 0x2941 # macro
regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_24 = 0x2942 # macro
regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_25 = 0x2943 # macro
regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_26 = 0x2944 # macro
regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_27 = 0x2945 # macro
regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_28 = 0x2946 # macro
regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_29 = 0x2947 # macro
regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_30 = 0x2948 # macro
regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX = 1 # macro
regCP_MEC_RS64_INTERRUPT_DATA_31 = 0x2949 # macro
regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE0_BASE = 0x294a # macro
regCP_MEC_DC_APERTURE0_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE0_MASK = 0x294b # macro
regCP_MEC_DC_APERTURE0_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE0_CNTL = 0x294c # macro
regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE1_BASE = 0x294d # macro
regCP_MEC_DC_APERTURE1_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE1_MASK = 0x294e # macro
regCP_MEC_DC_APERTURE1_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE1_CNTL = 0x294f # macro
regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE2_BASE = 0x2950 # macro
regCP_MEC_DC_APERTURE2_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE2_MASK = 0x2951 # macro
regCP_MEC_DC_APERTURE2_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE2_CNTL = 0x2952 # macro
regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE3_BASE = 0x2953 # macro
regCP_MEC_DC_APERTURE3_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE3_MASK = 0x2954 # macro
regCP_MEC_DC_APERTURE3_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE3_CNTL = 0x2955 # macro
regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE4_BASE = 0x2956 # macro
regCP_MEC_DC_APERTURE4_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE4_MASK = 0x2957 # macro
regCP_MEC_DC_APERTURE4_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE4_CNTL = 0x2958 # macro
regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE5_BASE = 0x2959 # macro
regCP_MEC_DC_APERTURE5_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE5_MASK = 0x295a # macro
regCP_MEC_DC_APERTURE5_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE5_CNTL = 0x295b # macro
regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE6_BASE = 0x295c # macro
regCP_MEC_DC_APERTURE6_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE6_MASK = 0x295d # macro
regCP_MEC_DC_APERTURE6_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE6_CNTL = 0x295e # macro
regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE7_BASE = 0x295f # macro
regCP_MEC_DC_APERTURE7_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE7_MASK = 0x2960 # macro
regCP_MEC_DC_APERTURE7_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE7_CNTL = 0x2961 # macro
regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE8_BASE = 0x2962 # macro
regCP_MEC_DC_APERTURE8_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE8_MASK = 0x2963 # macro
regCP_MEC_DC_APERTURE8_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE8_CNTL = 0x2964 # macro
regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE9_BASE = 0x2965 # macro
regCP_MEC_DC_APERTURE9_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE9_MASK = 0x2966 # macro
regCP_MEC_DC_APERTURE9_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE9_CNTL = 0x2967 # macro
regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE10_BASE = 0x2968 # macro
regCP_MEC_DC_APERTURE10_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE10_MASK = 0x2969 # macro
regCP_MEC_DC_APERTURE10_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE10_CNTL = 0x296a # macro
regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE11_BASE = 0x296b # macro
regCP_MEC_DC_APERTURE11_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE11_MASK = 0x296c # macro
regCP_MEC_DC_APERTURE11_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE11_CNTL = 0x296d # macro
regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE12_BASE = 0x296e # macro
regCP_MEC_DC_APERTURE12_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE12_MASK = 0x296f # macro
regCP_MEC_DC_APERTURE12_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE12_CNTL = 0x2970 # macro
regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE13_BASE = 0x2971 # macro
regCP_MEC_DC_APERTURE13_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE13_MASK = 0x2972 # macro
regCP_MEC_DC_APERTURE13_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE13_CNTL = 0x2973 # macro
regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE14_BASE = 0x2974 # macro
regCP_MEC_DC_APERTURE14_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE14_MASK = 0x2975 # macro
regCP_MEC_DC_APERTURE14_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE14_CNTL = 0x2976 # macro
regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE15_BASE = 0x2977 # macro
regCP_MEC_DC_APERTURE15_BASE_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE15_MASK = 0x2978 # macro
regCP_MEC_DC_APERTURE15_MASK_BASE_IDX = 1 # macro
regCP_MEC_DC_APERTURE15_CNTL = 0x2979 # macro
regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX = 1 # macro
regCP_CPC_IC_OP_CNTL = 0x297a # macro
regCP_CPC_IC_OP_CNTL_BASE_IDX = 1 # macro
regCP_GFX_CNTL = 0x2a00 # macro
regCP_GFX_CNTL_BASE_IDX = 1 # macro
regCP_GFX_RS64_INTERRUPT0 = 0x2a01 # macro
regCP_GFX_RS64_INTERRUPT0_BASE_IDX = 1 # macro
regCP_GFX_RS64_INTR_EN0 = 0x2a02 # macro
regCP_GFX_RS64_INTR_EN0_BASE_IDX = 1 # macro
regCP_GFX_RS64_INTR_EN1 = 0x2a03 # macro
regCP_GFX_RS64_INTR_EN1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_BASE_CNTL = 0x2a08 # macro
regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_OP_CNTL = 0x2a09 # macro
regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX = 1 # macro
regCP_GFX_RS64_LOCAL_BASE0_LO = 0x2a0a # macro
regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX = 1 # macro
regCP_GFX_RS64_LOCAL_BASE0_HI = 0x2a0b # macro
regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX = 1 # macro
regCP_GFX_RS64_LOCAL_MASK0_LO = 0x2a0c # macro
regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX = 1 # macro
regCP_GFX_RS64_LOCAL_MASK0_HI = 0x2a0d # macro
regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX = 1 # macro
regCP_GFX_RS64_LOCAL_APERTURE = 0x2a0e # macro
regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX = 1 # macro
regCP_GFX_RS64_LOCAL_INSTR_BASE_LO = 0x2a0f # macro
regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro
regCP_GFX_RS64_LOCAL_INSTR_BASE_HI = 0x2a10 # macro
regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro
regCP_GFX_RS64_LOCAL_INSTR_MASK_LO = 0x2a11 # macro
regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro
regCP_GFX_RS64_LOCAL_INSTR_MASK_HI = 0x2a12 # macro
regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro
regCP_GFX_RS64_LOCAL_INSTR_APERTURE = 0x2a13 # macro
regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro
regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE = 0x2a14 # macro
regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro
regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO = 0x2a15 # macro
regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro
regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI = 0x2a16 # macro
regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro
regCP_GFX_RS64_PERFCOUNT_CNTL0 = 0x2a1a # macro
regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_PERFCOUNT_CNTL1 = 0x2a1b # macro
regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_MIP_LO0 = 0x2a1c # macro
regCP_GFX_RS64_MIP_LO0_BASE_IDX = 1 # macro
regCP_GFX_RS64_MIP_LO1 = 0x2a1d # macro
regCP_GFX_RS64_MIP_LO1_BASE_IDX = 1 # macro
regCP_GFX_RS64_MIP_HI0 = 0x2a1e # macro
regCP_GFX_RS64_MIP_HI0_BASE_IDX = 1 # macro
regCP_GFX_RS64_MIP_HI1 = 0x2a1f # macro
regCP_GFX_RS64_MIP_HI1_BASE_IDX = 1 # macro
regCP_GFX_RS64_MTIMECMP_LO0 = 0x2a20 # macro
regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX = 1 # macro
regCP_GFX_RS64_MTIMECMP_LO1 = 0x2a21 # macro
regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX = 1 # macro
regCP_GFX_RS64_MTIMECMP_HI0 = 0x2a22 # macro
regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX = 1 # macro
regCP_GFX_RS64_MTIMECMP_HI1 = 0x2a23 # macro
regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP0_LO0 = 0x2a24 # macro
regCP_GFX_RS64_GP0_LO0_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP0_LO1 = 0x2a25 # macro
regCP_GFX_RS64_GP0_LO1_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP0_HI0 = 0x2a26 # macro
regCP_GFX_RS64_GP0_HI0_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP0_HI1 = 0x2a27 # macro
regCP_GFX_RS64_GP0_HI1_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP1_LO0 = 0x2a28 # macro
regCP_GFX_RS64_GP1_LO0_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP1_LO1 = 0x2a29 # macro
regCP_GFX_RS64_GP1_LO1_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP1_HI0 = 0x2a2a # macro
regCP_GFX_RS64_GP1_HI0_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP1_HI1 = 0x2a2b # macro
regCP_GFX_RS64_GP1_HI1_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP2_LO0 = 0x2a2c # macro
regCP_GFX_RS64_GP2_LO0_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP2_LO1 = 0x2a2d # macro
regCP_GFX_RS64_GP2_LO1_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP2_HI0 = 0x2a2e # macro
regCP_GFX_RS64_GP2_HI0_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP2_HI1 = 0x2a2f # macro
regCP_GFX_RS64_GP2_HI1_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP3_LO0 = 0x2a30 # macro
regCP_GFX_RS64_GP3_LO0_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP3_LO1 = 0x2a31 # macro
regCP_GFX_RS64_GP3_LO1_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP3_HI0 = 0x2a32 # macro
regCP_GFX_RS64_GP3_HI0_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP3_HI1 = 0x2a33 # macro
regCP_GFX_RS64_GP3_HI1_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP4_LO0 = 0x2a34 # macro
regCP_GFX_RS64_GP4_LO0_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP4_LO1 = 0x2a35 # macro
regCP_GFX_RS64_GP4_LO1_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP4_HI0 = 0x2a36 # macro
regCP_GFX_RS64_GP4_HI0_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP4_HI1 = 0x2a37 # macro
regCP_GFX_RS64_GP4_HI1_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP5_LO0 = 0x2a38 # macro
regCP_GFX_RS64_GP5_LO0_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP5_LO1 = 0x2a39 # macro
regCP_GFX_RS64_GP5_LO1_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP5_HI0 = 0x2a3a # macro
regCP_GFX_RS64_GP5_HI0_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP5_HI1 = 0x2a3b # macro
regCP_GFX_RS64_GP5_HI1_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP6_LO = 0x2a3c # macro
regCP_GFX_RS64_GP6_LO_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP6_HI = 0x2a3d # macro
regCP_GFX_RS64_GP6_HI_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP7_LO = 0x2a3e # macro
regCP_GFX_RS64_GP7_LO_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP7_HI = 0x2a3f # macro
regCP_GFX_RS64_GP7_HI_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP8_LO = 0x2a40 # macro
regCP_GFX_RS64_GP8_LO_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP8_HI = 0x2a41 # macro
regCP_GFX_RS64_GP8_HI_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP9_LO = 0x2a42 # macro
regCP_GFX_RS64_GP9_LO_BASE_IDX = 1 # macro
regCP_GFX_RS64_GP9_HI = 0x2a43 # macro
regCP_GFX_RS64_GP9_HI_BASE_IDX = 1 # macro
regCP_GFX_RS64_INSTR_PNTR0 = 0x2a44 # macro
regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX = 1 # macro
regCP_GFX_RS64_INSTR_PNTR1 = 0x2a45 # macro
regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX = 1 # macro
regCP_GFX_RS64_PENDING_INTERRUPT0 = 0x2a46 # macro
regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX = 1 # macro
regCP_GFX_RS64_PENDING_INTERRUPT1 = 0x2a47 # macro
regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE0_BASE0 = 0x2a49 # macro
regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE0_MASK0 = 0x2a4a # macro
regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE0_CNTL0 = 0x2a4b # macro
regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE1_BASE0 = 0x2a4c # macro
regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE1_MASK0 = 0x2a4d # macro
regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE1_CNTL0 = 0x2a4e # macro
regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE2_BASE0 = 0x2a4f # macro
regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE2_MASK0 = 0x2a50 # macro
regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE2_CNTL0 = 0x2a51 # macro
regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE3_BASE0 = 0x2a52 # macro
regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE3_MASK0 = 0x2a53 # macro
regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE3_CNTL0 = 0x2a54 # macro
regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE4_BASE0 = 0x2a55 # macro
regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE4_MASK0 = 0x2a56 # macro
regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE4_CNTL0 = 0x2a57 # macro
regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE5_BASE0 = 0x2a58 # macro
regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE5_MASK0 = 0x2a59 # macro
regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE5_CNTL0 = 0x2a5a # macro
regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE6_BASE0 = 0x2a5b # macro
regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE6_MASK0 = 0x2a5c # macro
regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE6_CNTL0 = 0x2a5d # macro
regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE7_BASE0 = 0x2a5e # macro
regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE7_MASK0 = 0x2a5f # macro
regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE7_CNTL0 = 0x2a60 # macro
regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE8_BASE0 = 0x2a61 # macro
regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE8_MASK0 = 0x2a62 # macro
regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE8_CNTL0 = 0x2a63 # macro
regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE9_BASE0 = 0x2a64 # macro
regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE9_MASK0 = 0x2a65 # macro
regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE9_CNTL0 = 0x2a66 # macro
regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE10_BASE0 = 0x2a67 # macro
regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE10_MASK0 = 0x2a68 # macro
regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE10_CNTL0 = 0x2a69 # macro
regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE11_BASE0 = 0x2a6a # macro
regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE11_MASK0 = 0x2a6b # macro
regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE11_CNTL0 = 0x2a6c # macro
regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE12_BASE0 = 0x2a6d # macro
regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE12_MASK0 = 0x2a6e # macro
regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE12_CNTL0 = 0x2a6f # macro
regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE13_BASE0 = 0x2a70 # macro
regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE13_MASK0 = 0x2a71 # macro
regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE13_CNTL0 = 0x2a72 # macro
regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE14_BASE0 = 0x2a73 # macro
regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE14_MASK0 = 0x2a74 # macro
regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE14_CNTL0 = 0x2a75 # macro
regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE15_BASE0 = 0x2a76 # macro
regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE15_MASK0 = 0x2a77 # macro
regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE15_CNTL0 = 0x2a78 # macro
regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE0_BASE1 = 0x2a79 # macro
regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE0_MASK1 = 0x2a7a # macro
regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE0_CNTL1 = 0x2a7b # macro
regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE1_BASE1 = 0x2a7c # macro
regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE1_MASK1 = 0x2a7d # macro
regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE1_CNTL1 = 0x2a7e # macro
regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE2_BASE1 = 0x2a7f # macro
regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE2_MASK1 = 0x2a80 # macro
regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE2_CNTL1 = 0x2a81 # macro
regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE3_BASE1 = 0x2a82 # macro
regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE3_MASK1 = 0x2a83 # macro
regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE3_CNTL1 = 0x2a84 # macro
regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE4_BASE1 = 0x2a85 # macro
regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE4_MASK1 = 0x2a86 # macro
regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE4_CNTL1 = 0x2a87 # macro
regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE5_BASE1 = 0x2a88 # macro
regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE5_MASK1 = 0x2a89 # macro
regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE5_CNTL1 = 0x2a8a # macro
regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE6_BASE1 = 0x2a8b # macro
regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE6_MASK1 = 0x2a8c # macro
regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE6_CNTL1 = 0x2a8d # macro
regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE7_BASE1 = 0x2a8e # macro
regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE7_MASK1 = 0x2a8f # macro
regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE7_CNTL1 = 0x2a90 # macro
regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE8_BASE1 = 0x2a91 # macro
regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE8_MASK1 = 0x2a92 # macro
regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE8_CNTL1 = 0x2a93 # macro
regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE9_BASE1 = 0x2a94 # macro
regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE9_MASK1 = 0x2a95 # macro
regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE9_CNTL1 = 0x2a96 # macro
regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE10_BASE1 = 0x2a97 # macro
regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE10_MASK1 = 0x2a98 # macro
regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE10_CNTL1 = 0x2a99 # macro
regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE11_BASE1 = 0x2a9a # macro
regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE11_MASK1 = 0x2a9b # macro
regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE11_CNTL1 = 0x2a9c # macro
regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE12_BASE1 = 0x2a9d # macro
regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE12_MASK1 = 0x2a9e # macro
regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE12_CNTL1 = 0x2a9f # macro
regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE13_BASE1 = 0x2aa0 # macro
regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE13_MASK1 = 0x2aa1 # macro
regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE13_CNTL1 = 0x2aa2 # macro
regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE14_BASE1 = 0x2aa3 # macro
regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE14_MASK1 = 0x2aa4 # macro
regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE14_CNTL1 = 0x2aa5 # macro
regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE15_BASE1 = 0x2aa6 # macro
regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE15_MASK1 = 0x2aa7 # macro
regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_APERTURE15_CNTL1 = 0x2aa8 # macro
regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX = 1 # macro
regCP_GFX_RS64_INTERRUPT1 = 0x2aac # macro
regCP_GFX_RS64_INTERRUPT1_BASE_IDX = 1 # macro
regGL1_DRAM_BURST_MASK = 0x2d02 # macro
regGL1_DRAM_BURST_MASK_BASE_IDX = 1 # macro
regGL1_ARB_STATUS = 0x2d03 # macro
regGL1_ARB_STATUS_BASE_IDX = 1 # macro
regGL1I_GL1R_REP_FGCG_OVERRIDE = 0x2d05 # macro
regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX = 1 # macro
regGL1C_STATUS = 0x2d41 # macro
regGL1C_STATUS_BASE_IDX = 1 # macro
regGL1C_UTCL0_CNTL1 = 0x2d42 # macro
regGL1C_UTCL0_CNTL1_BASE_IDX = 1 # macro
regGL1C_UTCL0_CNTL2 = 0x2d43 # macro
regGL1C_UTCL0_CNTL2_BASE_IDX = 1 # macro
regGL1C_UTCL0_STATUS = 0x2d44 # macro
regGL1C_UTCL0_STATUS_BASE_IDX = 1 # macro
regGL1C_UTCL0_RETRY = 0x2d45 # macro
regGL1C_UTCL0_RETRY_BASE_IDX = 1 # macro
regCH_ARB_CTRL = 0x2d80 # macro
regCH_ARB_CTRL_BASE_IDX = 1 # macro
regCH_DRAM_BURST_MASK = 0x2d82 # macro
regCH_DRAM_BURST_MASK_BASE_IDX = 1 # macro
regCH_ARB_STATUS = 0x2d83 # macro
regCH_ARB_STATUS_BASE_IDX = 1 # macro
regCH_DRAM_BURST_CTRL = 0x2d84 # macro
regCH_DRAM_BURST_CTRL_BASE_IDX = 1 # macro
regCHA_CHC_CREDITS = 0x2d88 # macro
regCHA_CHC_CREDITS_BASE_IDX = 1 # macro
regCHA_CLIENT_FREE_DELAY = 0x2d89 # macro
regCHA_CLIENT_FREE_DELAY_BASE_IDX = 1 # macro
regCHI_CHR_REP_FGCG_OVERRIDE = 0x2d8c # macro
regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX = 1 # macro
regCH_VC5_ENABLE = 0x2d94 # macro
regCH_VC5_ENABLE_BASE_IDX = 1 # macro
regCHC_CTRL = 0x2dc0 # macro
regCHC_CTRL_BASE_IDX = 1 # macro
regCHC_STATUS = 0x2dc1 # macro
regCHC_STATUS_BASE_IDX = 1 # macro
regCHCG_CTRL = 0x2dc2 # macro
regCHCG_CTRL_BASE_IDX = 1 # macro
regCHCG_STATUS = 0x2dc3 # macro
regCHCG_STATUS_BASE_IDX = 1 # macro
regGL2C_CTRL = 0x2e00 # macro
regGL2C_CTRL_BASE_IDX = 1 # macro
regGL2C_CTRL2 = 0x2e01 # macro
regGL2C_CTRL2_BASE_IDX = 1 # macro
regGL2C_ADDR_MATCH_MASK = 0x2e03 # macro
regGL2C_ADDR_MATCH_MASK_BASE_IDX = 1 # macro
regGL2C_ADDR_MATCH_SIZE = 0x2e04 # macro
regGL2C_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro
regGL2C_WBINVL2 = 0x2e05 # macro
regGL2C_WBINVL2_BASE_IDX = 1 # macro
regGL2C_SOFT_RESET = 0x2e06 # macro
regGL2C_SOFT_RESET_BASE_IDX = 1 # macro
regGL2C_CM_CTRL0 = 0x2e07 # macro
regGL2C_CM_CTRL0_BASE_IDX = 1 # macro
regGL2C_CM_CTRL1 = 0x2e08 # macro
regGL2C_CM_CTRL1_BASE_IDX = 1 # macro
regGL2C_CM_STALL = 0x2e09 # macro
regGL2C_CM_STALL_BASE_IDX = 1 # macro
regGL2C_CTRL3 = 0x2e0c # macro
regGL2C_CTRL3_BASE_IDX = 1 # macro
regGL2C_LB_CTR_CTRL = 0x2e0d # macro
regGL2C_LB_CTR_CTRL_BASE_IDX = 1 # macro
regGL2C_LB_DATA0 = 0x2e0e # macro
regGL2C_LB_DATA0_BASE_IDX = 1 # macro
regGL2C_LB_DATA1 = 0x2e0f # macro
regGL2C_LB_DATA1_BASE_IDX = 1 # macro
regGL2C_LB_DATA2 = 0x2e10 # macro
regGL2C_LB_DATA2_BASE_IDX = 1 # macro
regGL2C_LB_DATA3 = 0x2e11 # macro
regGL2C_LB_DATA3_BASE_IDX = 1 # macro
regGL2C_LB_CTR_SEL0 = 0x2e12 # macro
regGL2C_LB_CTR_SEL0_BASE_IDX = 1 # macro
regGL2C_LB_CTR_SEL1 = 0x2e13 # macro
regGL2C_LB_CTR_SEL1_BASE_IDX = 1 # macro
regGL2C_CTRL4 = 0x2e17 # macro
regGL2C_CTRL4_BASE_IDX = 1 # macro
regGL2C_DISCARD_STALL_CTRL = 0x2e18 # macro
regGL2C_DISCARD_STALL_CTRL_BASE_IDX = 1 # macro
regGL2A_ADDR_MATCH_CTRL = 0x2e20 # macro
regGL2A_ADDR_MATCH_CTRL_BASE_IDX = 1 # macro
regGL2A_ADDR_MATCH_MASK = 0x2e21 # macro
regGL2A_ADDR_MATCH_MASK_BASE_IDX = 1 # macro
regGL2A_ADDR_MATCH_SIZE = 0x2e22 # macro
regGL2A_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro
regGL2A_PRIORITY_CTRL = 0x2e23 # macro
regGL2A_PRIORITY_CTRL_BASE_IDX = 1 # macro
regGL2A_RESP_THROTTLE_CTRL = 0x2e2a # macro
regGL2A_RESP_THROTTLE_CTRL_BASE_IDX = 1 # macro
regGL1H_ARB_CTRL = 0x2e40 # macro
regGL1H_ARB_CTRL_BASE_IDX = 1 # macro
regGL1H_GL1_CREDITS = 0x2e41 # macro
regGL1H_GL1_CREDITS_BASE_IDX = 1 # macro
regGL1H_BURST_MASK = 0x2e42 # macro
regGL1H_BURST_MASK_BASE_IDX = 1 # macro
regGL1H_BURST_CTRL = 0x2e43 # macro
regGL1H_BURST_CTRL_BASE_IDX = 1 # macro
regGL1H_ARB_STATUS = 0x2e44 # macro
regGL1H_ARB_STATUS_BASE_IDX = 1 # macro
regCPG_PERFCOUNTER1_LO = 0x3000 # macro
regCPG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regCPG_PERFCOUNTER1_HI = 0x3001 # macro
regCPG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regCPG_PERFCOUNTER0_LO = 0x3002 # macro
regCPG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regCPG_PERFCOUNTER0_HI = 0x3003 # macro
regCPG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regCPC_PERFCOUNTER1_LO = 0x3004 # macro
regCPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regCPC_PERFCOUNTER1_HI = 0x3005 # macro
regCPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regCPC_PERFCOUNTER0_LO = 0x3006 # macro
regCPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regCPC_PERFCOUNTER0_HI = 0x3007 # macro
regCPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regCPF_PERFCOUNTER1_LO = 0x3008 # macro
regCPF_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regCPF_PERFCOUNTER1_HI = 0x3009 # macro
regCPF_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regCPF_PERFCOUNTER0_LO = 0x300a # macro
regCPF_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regCPF_PERFCOUNTER0_HI = 0x300b # macro
regCPF_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regCPF_LATENCY_STATS_DATA = 0x300c # macro
regCPF_LATENCY_STATS_DATA_BASE_IDX = 1 # macro
regCPG_LATENCY_STATS_DATA = 0x300d # macro
regCPG_LATENCY_STATS_DATA_BASE_IDX = 1 # macro
regCPC_LATENCY_STATS_DATA = 0x300e # macro
regCPC_LATENCY_STATS_DATA_BASE_IDX = 1 # macro
regGRBM_PERFCOUNTER0_LO = 0x3040 # macro
regGRBM_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regGRBM_PERFCOUNTER0_HI = 0x3041 # macro
regGRBM_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regGRBM_PERFCOUNTER1_LO = 0x3043 # macro
regGRBM_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regGRBM_PERFCOUNTER1_HI = 0x3044 # macro
regGRBM_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regGRBM_SE0_PERFCOUNTER_LO = 0x3045 # macro
regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX = 1 # macro
regGRBM_SE0_PERFCOUNTER_HI = 0x3046 # macro
regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX = 1 # macro
regGRBM_SE1_PERFCOUNTER_LO = 0x3047 # macro
regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX = 1 # macro
regGRBM_SE1_PERFCOUNTER_HI = 0x3048 # macro
regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX = 1 # macro
regGRBM_SE2_PERFCOUNTER_LO = 0x3049 # macro
regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX = 1 # macro
regGRBM_SE2_PERFCOUNTER_HI = 0x304a # macro
regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX = 1 # macro
regGRBM_SE3_PERFCOUNTER_LO = 0x304b # macro
regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX = 1 # macro
regGRBM_SE3_PERFCOUNTER_HI = 0x304c # macro
regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX = 1 # macro
regGRBM_SE4_PERFCOUNTER_LO = 0x304d # macro
regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX = 1 # macro
regGRBM_SE4_PERFCOUNTER_HI = 0x304e # macro
regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX = 1 # macro
regGRBM_SE5_PERFCOUNTER_LO = 0x304f # macro
regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX = 1 # macro
regGRBM_SE5_PERFCOUNTER_HI = 0x3050 # macro
regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX = 1 # macro
regGRBM_SE6_PERFCOUNTER_LO = 0x3051 # macro
regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX = 1 # macro
regGRBM_SE6_PERFCOUNTER_HI = 0x3052 # macro
regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER0_LO = 0x30a4 # macro
regGE1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER0_HI = 0x30a5 # macro
regGE1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER1_LO = 0x30a6 # macro
regGE1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER1_HI = 0x30a7 # macro
regGE1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER2_LO = 0x30a8 # macro
regGE1_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER2_HI = 0x30a9 # macro
regGE1_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER3_LO = 0x30aa # macro
regGE1_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER3_HI = 0x30ab # macro
regGE1_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER0_LO = 0x30ac # macro
regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER0_HI = 0x30ad # macro
regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER1_LO = 0x30ae # macro
regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER1_HI = 0x30af # macro
regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER2_LO = 0x30b0 # macro
regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER2_HI = 0x30b1 # macro
regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER3_LO = 0x30b2 # macro
regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER3_HI = 0x30b3 # macro
regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER0_LO = 0x30b4 # macro
regGE2_SE_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER0_HI = 0x30b5 # macro
regGE2_SE_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER1_LO = 0x30b6 # macro
regGE2_SE_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER1_HI = 0x30b7 # macro
regGE2_SE_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER2_LO = 0x30b8 # macro
regGE2_SE_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER2_HI = 0x30b9 # macro
regGE2_SE_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER3_LO = 0x30ba # macro
regGE2_SE_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER3_HI = 0x30bb # macro
regGE2_SE_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER0_LO = 0x3100 # macro
regPA_SU_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER0_HI = 0x3101 # macro
regPA_SU_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER1_LO = 0x3102 # macro
regPA_SU_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER1_HI = 0x3103 # macro
regPA_SU_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER2_LO = 0x3104 # macro
regPA_SU_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER2_HI = 0x3105 # macro
regPA_SU_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER3_LO = 0x3106 # macro
regPA_SU_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER3_HI = 0x3107 # macro
regPA_SU_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER0_LO = 0x3140 # macro
regPA_SC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER0_HI = 0x3141 # macro
regPA_SC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER1_LO = 0x3142 # macro
regPA_SC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER1_HI = 0x3143 # macro
regPA_SC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER2_LO = 0x3144 # macro
regPA_SC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER2_HI = 0x3145 # macro
regPA_SC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER3_LO = 0x3146 # macro
regPA_SC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER3_HI = 0x3147 # macro
regPA_SC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER4_LO = 0x3148 # macro
regPA_SC_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER4_HI = 0x3149 # macro
regPA_SC_PERFCOUNTER4_HI_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER5_LO = 0x314a # macro
regPA_SC_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER5_HI = 0x314b # macro
regPA_SC_PERFCOUNTER5_HI_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER6_LO = 0x314c # macro
regPA_SC_PERFCOUNTER6_LO_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER6_HI = 0x314d # macro
regPA_SC_PERFCOUNTER6_HI_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER7_LO = 0x314e # macro
regPA_SC_PERFCOUNTER7_LO_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER7_HI = 0x314f # macro
regPA_SC_PERFCOUNTER7_HI_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER0_HI = 0x3180 # macro
regSPI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER0_LO = 0x3181 # macro
regSPI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER1_HI = 0x3182 # macro
regSPI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER1_LO = 0x3183 # macro
regSPI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER2_HI = 0x3184 # macro
regSPI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER2_LO = 0x3185 # macro
regSPI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER3_HI = 0x3186 # macro
regSPI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER3_LO = 0x3187 # macro
regSPI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER4_HI = 0x3188 # macro
regSPI_PERFCOUNTER4_HI_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER4_LO = 0x3189 # macro
regSPI_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER5_HI = 0x318a # macro
regSPI_PERFCOUNTER5_HI_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER5_LO = 0x318b # macro
regSPI_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
regPC_PERFCOUNTER0_HI = 0x318c # macro
regPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regPC_PERFCOUNTER0_LO = 0x318d # macro
regPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regPC_PERFCOUNTER1_HI = 0x318e # macro
regPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regPC_PERFCOUNTER1_LO = 0x318f # macro
regPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regPC_PERFCOUNTER2_HI = 0x3190 # macro
regPC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regPC_PERFCOUNTER2_LO = 0x3191 # macro
regPC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regPC_PERFCOUNTER3_HI = 0x3192 # macro
regPC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regPC_PERFCOUNTER3_LO = 0x3193 # macro
regPC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER0_LO = 0x31c0 # macro
regSQ_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER1_LO = 0x31c2 # macro
regSQ_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER2_LO = 0x31c4 # macro
regSQ_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER3_LO = 0x31c6 # macro
regSQ_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER4_LO = 0x31c8 # macro
regSQ_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER5_LO = 0x31ca # macro
regSQ_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER6_LO = 0x31cc # macro
regSQ_PERFCOUNTER6_LO_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER7_LO = 0x31ce # macro
regSQ_PERFCOUNTER7_LO_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER0_LO = 0x31e4 # macro
regSQG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER0_HI = 0x31e5 # macro
regSQG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER1_LO = 0x31e6 # macro
regSQG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER1_HI = 0x31e7 # macro
regSQG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER2_LO = 0x31e8 # macro
regSQG_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER2_HI = 0x31e9 # macro
regSQG_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER3_LO = 0x31ea # macro
regSQG_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER3_HI = 0x31eb # macro
regSQG_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER4_LO = 0x31ec # macro
regSQG_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER4_HI = 0x31ed # macro
regSQG_PERFCOUNTER4_HI_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER5_LO = 0x31ee # macro
regSQG_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER5_HI = 0x31ef # macro
regSQG_PERFCOUNTER5_HI_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER6_LO = 0x31f0 # macro
regSQG_PERFCOUNTER6_LO_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER6_HI = 0x31f1 # macro
regSQG_PERFCOUNTER6_HI_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER7_LO = 0x31f2 # macro
regSQG_PERFCOUNTER7_LO_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER7_HI = 0x31f3 # macro
regSQG_PERFCOUNTER7_HI_BASE_IDX = 1 # macro
regSX_PERFCOUNTER0_LO = 0x3240 # macro
regSX_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regSX_PERFCOUNTER0_HI = 0x3241 # macro
regSX_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regSX_PERFCOUNTER1_LO = 0x3242 # macro
regSX_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regSX_PERFCOUNTER1_HI = 0x3243 # macro
regSX_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regSX_PERFCOUNTER2_LO = 0x3244 # macro
regSX_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regSX_PERFCOUNTER2_HI = 0x3245 # macro
regSX_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regSX_PERFCOUNTER3_LO = 0x3246 # macro
regSX_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regSX_PERFCOUNTER3_HI = 0x3247 # macro
regSX_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regGCEA_PERFCOUNTER2_LO = 0x3260 # macro
regGCEA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regGCEA_PERFCOUNTER2_HI = 0x3261 # macro
regGCEA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regGCEA_PERFCOUNTER_LO = 0x3262 # macro
regGCEA_PERFCOUNTER_LO_BASE_IDX = 1 # macro
regGCEA_PERFCOUNTER_HI = 0x3263 # macro
regGCEA_PERFCOUNTER_HI_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER0_LO = 0x3280 # macro
regGDS_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER0_HI = 0x3281 # macro
regGDS_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER1_LO = 0x3282 # macro
regGDS_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER1_HI = 0x3283 # macro
regGDS_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER2_LO = 0x3284 # macro
regGDS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER2_HI = 0x3285 # macro
regGDS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER3_LO = 0x3286 # macro
regGDS_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER3_HI = 0x3287 # macro
regGDS_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regTA_PERFCOUNTER0_LO = 0x32c0 # macro
regTA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regTA_PERFCOUNTER0_HI = 0x32c1 # macro
regTA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regTA_PERFCOUNTER1_LO = 0x32c2 # macro
regTA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regTA_PERFCOUNTER1_HI = 0x32c3 # macro
regTA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regTD_PERFCOUNTER0_LO = 0x3300 # macro
regTD_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regTD_PERFCOUNTER0_HI = 0x3301 # macro
regTD_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regTD_PERFCOUNTER1_LO = 0x3302 # macro
regTD_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regTD_PERFCOUNTER1_HI = 0x3303 # macro
regTD_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER0_LO = 0x3340 # macro
regTCP_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER0_HI = 0x3341 # macro
regTCP_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER1_LO = 0x3342 # macro
regTCP_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER1_HI = 0x3343 # macro
regTCP_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER2_LO = 0x3344 # macro
regTCP_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER2_HI = 0x3345 # macro
regTCP_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER3_LO = 0x3346 # macro
regTCP_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER3_HI = 0x3347 # macro
regTCP_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER_FILTER = 0x3348 # macro
regTCP_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER_FILTER2 = 0x3349 # macro
regTCP_PERFCOUNTER_FILTER2_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER_FILTER_EN = 0x334a # macro
regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER0_LO = 0x3380 # macro
regGL2C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER0_HI = 0x3381 # macro
regGL2C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER1_LO = 0x3382 # macro
regGL2C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER1_HI = 0x3383 # macro
regGL2C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER2_LO = 0x3384 # macro
regGL2C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER2_HI = 0x3385 # macro
regGL2C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER3_LO = 0x3386 # macro
regGL2C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER3_HI = 0x3387 # macro
regGL2C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER0_LO = 0x3390 # macro
regGL2A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER0_HI = 0x3391 # macro
regGL2A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER1_LO = 0x3392 # macro
regGL2A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER1_HI = 0x3393 # macro
regGL2A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER2_LO = 0x3394 # macro
regGL2A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER2_HI = 0x3395 # macro
regGL2A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER3_LO = 0x3396 # macro
regGL2A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER3_HI = 0x3397 # macro
regGL2A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regGL1C_PERFCOUNTER0_LO = 0x33a0 # macro
regGL1C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regGL1C_PERFCOUNTER0_HI = 0x33a1 # macro
regGL1C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regGL1C_PERFCOUNTER1_LO = 0x33a2 # macro
regGL1C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regGL1C_PERFCOUNTER1_HI = 0x33a3 # macro
regGL1C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regGL1C_PERFCOUNTER2_LO = 0x33a4 # macro
regGL1C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regGL1C_PERFCOUNTER2_HI = 0x33a5 # macro
regGL1C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regGL1C_PERFCOUNTER3_LO = 0x33a6 # macro
regGL1C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regGL1C_PERFCOUNTER3_HI = 0x33a7 # macro
regGL1C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regCHC_PERFCOUNTER0_LO = 0x33c0 # macro
regCHC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regCHC_PERFCOUNTER0_HI = 0x33c1 # macro
regCHC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regCHC_PERFCOUNTER1_LO = 0x33c2 # macro
regCHC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regCHC_PERFCOUNTER1_HI = 0x33c3 # macro
regCHC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regCHC_PERFCOUNTER2_LO = 0x33c4 # macro
regCHC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regCHC_PERFCOUNTER2_HI = 0x33c5 # macro
regCHC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regCHC_PERFCOUNTER3_LO = 0x33c6 # macro
regCHC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regCHC_PERFCOUNTER3_HI = 0x33c7 # macro
regCHC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regCHCG_PERFCOUNTER0_LO = 0x33c8 # macro
regCHCG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regCHCG_PERFCOUNTER0_HI = 0x33c9 # macro
regCHCG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regCHCG_PERFCOUNTER1_LO = 0x33ca # macro
regCHCG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regCHCG_PERFCOUNTER1_HI = 0x33cb # macro
regCHCG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regCHCG_PERFCOUNTER2_LO = 0x33cc # macro
regCHCG_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regCHCG_PERFCOUNTER2_HI = 0x33cd # macro
regCHCG_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regCHCG_PERFCOUNTER3_LO = 0x33ce # macro
regCHCG_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regCHCG_PERFCOUNTER3_HI = 0x33cf # macro
regCHCG_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regCB_PERFCOUNTER0_LO = 0x3406 # macro
regCB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regCB_PERFCOUNTER0_HI = 0x3407 # macro
regCB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regCB_PERFCOUNTER1_LO = 0x3408 # macro
regCB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regCB_PERFCOUNTER1_HI = 0x3409 # macro
regCB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regCB_PERFCOUNTER2_LO = 0x340a # macro
regCB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regCB_PERFCOUNTER2_HI = 0x340b # macro
regCB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regCB_PERFCOUNTER3_LO = 0x340c # macro
regCB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regCB_PERFCOUNTER3_HI = 0x340d # macro
regCB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regDB_PERFCOUNTER0_LO = 0x3440 # macro
regDB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regDB_PERFCOUNTER0_HI = 0x3441 # macro
regDB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regDB_PERFCOUNTER1_LO = 0x3442 # macro
regDB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regDB_PERFCOUNTER1_HI = 0x3443 # macro
regDB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regDB_PERFCOUNTER2_LO = 0x3444 # macro
regDB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regDB_PERFCOUNTER2_HI = 0x3445 # macro
regDB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regDB_PERFCOUNTER3_LO = 0x3446 # macro
regDB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regDB_PERFCOUNTER3_HI = 0x3447 # macro
regDB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regRLC_PERFCOUNTER0_LO = 0x3480 # macro
regRLC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regRLC_PERFCOUNTER0_HI = 0x3481 # macro
regRLC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regRLC_PERFCOUNTER1_LO = 0x3482 # macro
regRLC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regRLC_PERFCOUNTER1_HI = 0x3483 # macro
regRLC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER0_LO = 0x34c0 # macro
regRMI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER0_HI = 0x34c1 # macro
regRMI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER1_LO = 0x34c2 # macro
regRMI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER1_HI = 0x34c3 # macro
regRMI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER2_LO = 0x34c4 # macro
regRMI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER2_HI = 0x34c5 # macro
regRMI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER3_LO = 0x34c6 # macro
regRMI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER3_HI = 0x34c7 # macro
regRMI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regGCR_PERFCOUNTER0_LO = 0x3520 # macro
regGCR_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regGCR_PERFCOUNTER0_HI = 0x3521 # macro
regGCR_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regGCR_PERFCOUNTER1_LO = 0x3522 # macro
regGCR_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regGCR_PERFCOUNTER1_HI = 0x3523 # macro
regGCR_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER0_LO = 0x3580 # macro
regPA_PH_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER0_HI = 0x3581 # macro
regPA_PH_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER1_LO = 0x3582 # macro
regPA_PH_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER1_HI = 0x3583 # macro
regPA_PH_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER2_LO = 0x3584 # macro
regPA_PH_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER2_HI = 0x3585 # macro
regPA_PH_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER3_LO = 0x3586 # macro
regPA_PH_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER3_HI = 0x3587 # macro
regPA_PH_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER4_LO = 0x3588 # macro
regPA_PH_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER4_HI = 0x3589 # macro
regPA_PH_PERFCOUNTER4_HI_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER5_LO = 0x358a # macro
regPA_PH_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER5_HI = 0x358b # macro
regPA_PH_PERFCOUNTER5_HI_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER6_LO = 0x358c # macro
regPA_PH_PERFCOUNTER6_LO_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER6_HI = 0x358d # macro
regPA_PH_PERFCOUNTER6_HI_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER7_LO = 0x358e # macro
regPA_PH_PERFCOUNTER7_LO_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER7_HI = 0x358f # macro
regPA_PH_PERFCOUNTER7_HI_BASE_IDX = 1 # macro
regUTCL1_PERFCOUNTER0_LO = 0x35a0 # macro
regUTCL1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regUTCL1_PERFCOUNTER0_HI = 0x35a1 # macro
regUTCL1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regUTCL1_PERFCOUNTER1_LO = 0x35a2 # macro
regUTCL1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regUTCL1_PERFCOUNTER1_HI = 0x35a3 # macro
regUTCL1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regUTCL1_PERFCOUNTER2_LO = 0x35a4 # macro
regUTCL1_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regUTCL1_PERFCOUNTER2_HI = 0x35a5 # macro
regUTCL1_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regUTCL1_PERFCOUNTER3_LO = 0x35a6 # macro
regUTCL1_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regUTCL1_PERFCOUNTER3_HI = 0x35a7 # macro
regUTCL1_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regGL1A_PERFCOUNTER0_LO = 0x35c0 # macro
regGL1A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regGL1A_PERFCOUNTER0_HI = 0x35c1 # macro
regGL1A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regGL1A_PERFCOUNTER1_LO = 0x35c2 # macro
regGL1A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regGL1A_PERFCOUNTER1_HI = 0x35c3 # macro
regGL1A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regGL1A_PERFCOUNTER2_LO = 0x35c4 # macro
regGL1A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regGL1A_PERFCOUNTER2_HI = 0x35c5 # macro
regGL1A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regGL1A_PERFCOUNTER3_LO = 0x35c6 # macro
regGL1A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regGL1A_PERFCOUNTER3_HI = 0x35c7 # macro
regGL1A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regGL1H_PERFCOUNTER0_LO = 0x35d0 # macro
regGL1H_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regGL1H_PERFCOUNTER0_HI = 0x35d1 # macro
regGL1H_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regGL1H_PERFCOUNTER1_LO = 0x35d2 # macro
regGL1H_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regGL1H_PERFCOUNTER1_HI = 0x35d3 # macro
regGL1H_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regGL1H_PERFCOUNTER2_LO = 0x35d4 # macro
regGL1H_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regGL1H_PERFCOUNTER2_HI = 0x35d5 # macro
regGL1H_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regGL1H_PERFCOUNTER3_LO = 0x35d6 # macro
regGL1H_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regGL1H_PERFCOUNTER3_HI = 0x35d7 # macro
regGL1H_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regCHA_PERFCOUNTER0_LO = 0x3600 # macro
regCHA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
regCHA_PERFCOUNTER0_HI = 0x3601 # macro
regCHA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
regCHA_PERFCOUNTER1_LO = 0x3602 # macro
regCHA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
regCHA_PERFCOUNTER1_HI = 0x3603 # macro
regCHA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
regCHA_PERFCOUNTER2_LO = 0x3604 # macro
regCHA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regCHA_PERFCOUNTER2_HI = 0x3605 # macro
regCHA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regCHA_PERFCOUNTER3_LO = 0x3606 # macro
regCHA_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
regCHA_PERFCOUNTER3_HI = 0x3607 # macro
regCHA_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
regGUS_PERFCOUNTER2_LO = 0x3640 # macro
regGUS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
regGUS_PERFCOUNTER2_HI = 0x3641 # macro
regGUS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
regGUS_PERFCOUNTER_LO = 0x3642 # macro
regGUS_PERFCOUNTER_LO_BASE_IDX = 1 # macro
regGUS_PERFCOUNTER_HI = 0x3643 # macro
regGUS_PERFCOUNTER_HI_BASE_IDX = 1 # macro
regCPG_PERFCOUNTER1_SELECT = 0x3800 # macro
regCPG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regCPG_PERFCOUNTER0_SELECT1 = 0x3801 # macro
regCPG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regCPG_PERFCOUNTER0_SELECT = 0x3802 # macro
regCPG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regCPC_PERFCOUNTER1_SELECT = 0x3803 # macro
regCPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regCPC_PERFCOUNTER0_SELECT1 = 0x3804 # macro
regCPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regCPF_PERFCOUNTER1_SELECT = 0x3805 # macro
regCPF_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regCPF_PERFCOUNTER0_SELECT1 = 0x3806 # macro
regCPF_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regCPF_PERFCOUNTER0_SELECT = 0x3807 # macro
regCPF_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regCP_PERFMON_CNTL = 0x3808 # macro
regCP_PERFMON_CNTL_BASE_IDX = 1 # macro
regCPC_PERFCOUNTER0_SELECT = 0x3809 # macro
regCPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regCPF_TC_PERF_COUNTER_WINDOW_SELECT = 0x380a # macro
regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro
regCPG_TC_PERF_COUNTER_WINDOW_SELECT = 0x380b # macro
regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro
regCPF_LATENCY_STATS_SELECT = 0x380c # macro
regCPF_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro
regCPG_LATENCY_STATS_SELECT = 0x380d # macro
regCPG_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro
regCPC_LATENCY_STATS_SELECT = 0x380e # macro
regCPC_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro
regCPC_TC_PERF_COUNTER_WINDOW_SELECT = 0x380f # macro
regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro
regCP_DRAW_OBJECT = 0x3810 # macro
regCP_DRAW_OBJECT_BASE_IDX = 1 # macro
regCP_DRAW_OBJECT_COUNTER = 0x3811 # macro
regCP_DRAW_OBJECT_COUNTER_BASE_IDX = 1 # macro
regCP_DRAW_WINDOW_MASK_HI = 0x3812 # macro
regCP_DRAW_WINDOW_MASK_HI_BASE_IDX = 1 # macro
regCP_DRAW_WINDOW_HI = 0x3813 # macro
regCP_DRAW_WINDOW_HI_BASE_IDX = 1 # macro
regCP_DRAW_WINDOW_LO = 0x3814 # macro
regCP_DRAW_WINDOW_LO_BASE_IDX = 1 # macro
regCP_DRAW_WINDOW_CNTL = 0x3815 # macro
regCP_DRAW_WINDOW_CNTL_BASE_IDX = 1 # macro
regGRBM_PERFCOUNTER0_SELECT = 0x3840 # macro
regGRBM_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regGRBM_PERFCOUNTER1_SELECT = 0x3841 # macro
regGRBM_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regGRBM_SE0_PERFCOUNTER_SELECT = 0x3842 # macro
regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
regGRBM_SE1_PERFCOUNTER_SELECT = 0x3843 # macro
regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
regGRBM_SE2_PERFCOUNTER_SELECT = 0x3844 # macro
regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
regGRBM_SE3_PERFCOUNTER_SELECT = 0x3845 # macro
regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
regGRBM_SE4_PERFCOUNTER_SELECT = 0x3846 # macro
regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
regGRBM_SE5_PERFCOUNTER_SELECT = 0x3847 # macro
regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
regGRBM_SE6_PERFCOUNTER_SELECT = 0x3848 # macro
regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
regGRBM_PERFCOUNTER0_SELECT_HI = 0x384d # macro
regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX = 1 # macro
regGRBM_PERFCOUNTER1_SELECT_HI = 0x384e # macro
regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER0_SELECT = 0x38a4 # macro
regGE1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER0_SELECT1 = 0x38a5 # macro
regGE1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER1_SELECT = 0x38a6 # macro
regGE1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER1_SELECT1 = 0x38a7 # macro
regGE1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER2_SELECT = 0x38a8 # macro
regGE1_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER2_SELECT1 = 0x38a9 # macro
regGE1_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER3_SELECT = 0x38aa # macro
regGE1_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regGE1_PERFCOUNTER3_SELECT1 = 0x38ab # macro
regGE1_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER0_SELECT = 0x38ac # macro
regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER0_SELECT1 = 0x38ad # macro
regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER1_SELECT = 0x38ae # macro
regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER1_SELECT1 = 0x38af # macro
regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER2_SELECT = 0x38b0 # macro
regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER2_SELECT1 = 0x38b1 # macro
regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER3_SELECT = 0x38b2 # macro
regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regGE2_DIST_PERFCOUNTER3_SELECT1 = 0x38b3 # macro
regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER0_SELECT = 0x38b4 # macro
regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER0_SELECT1 = 0x38b5 # macro
regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER1_SELECT = 0x38b6 # macro
regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER1_SELECT1 = 0x38b7 # macro
regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER2_SELECT = 0x38b8 # macro
regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER2_SELECT1 = 0x38b9 # macro
regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER3_SELECT = 0x38ba # macro
regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regGE2_SE_PERFCOUNTER3_SELECT1 = 0x38bb # macro
regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER0_SELECT = 0x3900 # macro
regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER0_SELECT1 = 0x3901 # macro
regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER1_SELECT = 0x3902 # macro
regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER1_SELECT1 = 0x3903 # macro
regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER2_SELECT = 0x3904 # macro
regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER2_SELECT1 = 0x3905 # macro
regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER3_SELECT = 0x3906 # macro
regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regPA_SU_PERFCOUNTER3_SELECT1 = 0x3907 # macro
regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER0_SELECT = 0x3940 # macro
regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER0_SELECT1 = 0x3941 # macro
regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER1_SELECT = 0x3942 # macro
regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER2_SELECT = 0x3943 # macro
regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER3_SELECT = 0x3944 # macro
regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER4_SELECT = 0x3945 # macro
regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER5_SELECT = 0x3946 # macro
regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER6_SELECT = 0x3947 # macro
regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro
regPA_SC_PERFCOUNTER7_SELECT = 0x3948 # macro
regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER0_SELECT = 0x3980 # macro
regSPI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER1_SELECT = 0x3981 # macro
regSPI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER2_SELECT = 0x3982 # macro
regSPI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER3_SELECT = 0x3983 # macro
regSPI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER0_SELECT1 = 0x3984 # macro
regSPI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER1_SELECT1 = 0x3985 # macro
regSPI_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER2_SELECT1 = 0x3986 # macro
regSPI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER3_SELECT1 = 0x3987 # macro
regSPI_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER4_SELECT = 0x3988 # macro
regSPI_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER5_SELECT = 0x3989 # macro
regSPI_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
regSPI_PERFCOUNTER_BINS = 0x398a # macro
regSPI_PERFCOUNTER_BINS_BASE_IDX = 1 # macro
regPC_PERFCOUNTER0_SELECT = 0x398c # macro
regPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regPC_PERFCOUNTER1_SELECT = 0x398d # macro
regPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regPC_PERFCOUNTER2_SELECT = 0x398e # macro
regPC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regPC_PERFCOUNTER3_SELECT = 0x398f # macro
regPC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regPC_PERFCOUNTER0_SELECT1 = 0x3990 # macro
regPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regPC_PERFCOUNTER1_SELECT1 = 0x3991 # macro
regPC_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regPC_PERFCOUNTER2_SELECT1 = 0x3992 # macro
regPC_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
regPC_PERFCOUNTER3_SELECT1 = 0x3993 # macro
regPC_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER0_SELECT = 0x39c0 # macro
regSQ_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER1_SELECT = 0x39c1 # macro
regSQ_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER2_SELECT = 0x39c2 # macro
regSQ_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER3_SELECT = 0x39c3 # macro
regSQ_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER4_SELECT = 0x39c4 # macro
regSQ_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER5_SELECT = 0x39c5 # macro
regSQ_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER6_SELECT = 0x39c6 # macro
regSQ_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER7_SELECT = 0x39c7 # macro
regSQ_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER8_SELECT = 0x39c8 # macro
regSQ_PERFCOUNTER8_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER9_SELECT = 0x39c9 # macro
regSQ_PERFCOUNTER9_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER10_SELECT = 0x39ca # macro
regSQ_PERFCOUNTER10_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER11_SELECT = 0x39cb # macro
regSQ_PERFCOUNTER11_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER12_SELECT = 0x39cc # macro
regSQ_PERFCOUNTER12_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER13_SELECT = 0x39cd # macro
regSQ_PERFCOUNTER13_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER14_SELECT = 0x39ce # macro
regSQ_PERFCOUNTER14_SELECT_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER15_SELECT = 0x39cf # macro
regSQ_PERFCOUNTER15_SELECT_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER0_SELECT = 0x39d0 # macro
regSQG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER1_SELECT = 0x39d1 # macro
regSQG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER2_SELECT = 0x39d2 # macro
regSQG_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER3_SELECT = 0x39d3 # macro
regSQG_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER4_SELECT = 0x39d4 # macro
regSQG_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER5_SELECT = 0x39d5 # macro
regSQG_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER6_SELECT = 0x39d6 # macro
regSQG_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER7_SELECT = 0x39d7 # macro
regSQG_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER_CTRL = 0x39d8 # macro
regSQG_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro
regSQG_PERFCOUNTER_CTRL2 = 0x39da # macro
regSQG_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro
regSQG_PERF_SAMPLE_FINISH = 0x39db # macro
regSQG_PERF_SAMPLE_FINISH_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER_CTRL = 0x39e0 # macro
regSQ_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro
regSQ_PERFCOUNTER_CTRL2 = 0x39e2 # macro
regSQ_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_BUF0_BASE = 0x39e8 # macro
regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_BUF0_SIZE = 0x39e9 # macro
regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_BUF1_BASE = 0x39ea # macro
regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_BUF1_SIZE = 0x39eb # macro
regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_CTRL = 0x39ec # macro
regSQ_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_MASK = 0x39ed # macro
regSQ_THREAD_TRACE_MASK_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_TOKEN_MASK = 0x39ee # macro
regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_WPTR = 0x39ef # macro
regSQ_THREAD_TRACE_WPTR_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_STATUS = 0x39f4 # macro
regSQ_THREAD_TRACE_STATUS_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_STATUS2 = 0x39f5 # macro
regSQ_THREAD_TRACE_STATUS2_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_GFX_DRAW_CNTR = 0x39f6 # macro
regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_GFX_MARKER_CNTR = 0x39f7 # macro
regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_HP3D_DRAW_CNTR = 0x39f8 # macro
regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_HP3D_MARKER_CNTR = 0x39f9 # macro
regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX = 1 # macro
regSQ_THREAD_TRACE_DROPPED_CNTR = 0x39fa # macro
regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX = 1 # macro
regGCEA_PERFCOUNTER2_SELECT = 0x3a00 # macro
regGCEA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regGCEA_PERFCOUNTER2_SELECT1 = 0x3a01 # macro
regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
regGCEA_PERFCOUNTER2_MODE = 0x3a02 # macro
regGCEA_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro
regGCEA_PERFCOUNTER0_CFG = 0x3a03 # macro
regGCEA_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
regGCEA_PERFCOUNTER1_CFG = 0x3a04 # macro
regGCEA_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
regGCEA_PERFCOUNTER_RSLT_CNTL = 0x3a05 # macro
regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
regSX_PERFCOUNTER0_SELECT = 0x3a40 # macro
regSX_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regSX_PERFCOUNTER1_SELECT = 0x3a41 # macro
regSX_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regSX_PERFCOUNTER2_SELECT = 0x3a42 # macro
regSX_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regSX_PERFCOUNTER3_SELECT = 0x3a43 # macro
regSX_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regSX_PERFCOUNTER0_SELECT1 = 0x3a44 # macro
regSX_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regSX_PERFCOUNTER1_SELECT1 = 0x3a45 # macro
regSX_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER0_SELECT = 0x3a80 # macro
regGDS_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER1_SELECT = 0x3a81 # macro
regGDS_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER2_SELECT = 0x3a82 # macro
regGDS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER3_SELECT = 0x3a83 # macro
regGDS_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER0_SELECT1 = 0x3a84 # macro
regGDS_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER1_SELECT1 = 0x3a85 # macro
regGDS_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER2_SELECT1 = 0x3a86 # macro
regGDS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
regGDS_PERFCOUNTER3_SELECT1 = 0x3a87 # macro
regGDS_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
regTA_PERFCOUNTER0_SELECT = 0x3ac0 # macro
regTA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regTA_PERFCOUNTER0_SELECT1 = 0x3ac1 # macro
regTA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regTA_PERFCOUNTER1_SELECT = 0x3ac2 # macro
regTA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regTD_PERFCOUNTER0_SELECT = 0x3b00 # macro
regTD_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regTD_PERFCOUNTER0_SELECT1 = 0x3b01 # macro
regTD_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regTD_PERFCOUNTER1_SELECT = 0x3b02 # macro
regTD_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER0_SELECT = 0x3b40 # macro
regTCP_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER0_SELECT1 = 0x3b41 # macro
regTCP_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER1_SELECT = 0x3b42 # macro
regTCP_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER1_SELECT1 = 0x3b43 # macro
regTCP_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER2_SELECT = 0x3b44 # macro
regTCP_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regTCP_PERFCOUNTER3_SELECT = 0x3b45 # macro
regTCP_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER0_SELECT = 0x3b80 # macro
regGL2C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER0_SELECT1 = 0x3b81 # macro
regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER1_SELECT = 0x3b82 # macro
regGL2C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER1_SELECT1 = 0x3b83 # macro
regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER2_SELECT = 0x3b84 # macro
regGL2C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regGL2C_PERFCOUNTER3_SELECT = 0x3b85 # macro
regGL2C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER0_SELECT = 0x3b90 # macro
regGL2A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER0_SELECT1 = 0x3b91 # macro
regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER1_SELECT = 0x3b92 # macro
regGL2A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER1_SELECT1 = 0x3b93 # macro
regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER2_SELECT = 0x3b94 # macro
regGL2A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regGL2A_PERFCOUNTER3_SELECT = 0x3b95 # macro
regGL2A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regGL1C_PERFCOUNTER0_SELECT = 0x3ba0 # macro
regGL1C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regGL1C_PERFCOUNTER0_SELECT1 = 0x3ba1 # macro
regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regGL1C_PERFCOUNTER1_SELECT = 0x3ba2 # macro
regGL1C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regGL1C_PERFCOUNTER2_SELECT = 0x3ba3 # macro
regGL1C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regGL1C_PERFCOUNTER3_SELECT = 0x3ba4 # macro
regGL1C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regCHC_PERFCOUNTER0_SELECT = 0x3bc0 # macro
regCHC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regCHC_PERFCOUNTER0_SELECT1 = 0x3bc1 # macro
regCHC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regCHC_PERFCOUNTER1_SELECT = 0x3bc2 # macro
regCHC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regCHC_PERFCOUNTER2_SELECT = 0x3bc3 # macro
regCHC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regCHC_PERFCOUNTER3_SELECT = 0x3bc4 # macro
regCHC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regCHCG_PERFCOUNTER0_SELECT = 0x3bc6 # macro
regCHCG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regCHCG_PERFCOUNTER0_SELECT1 = 0x3bc7 # macro
regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regCHCG_PERFCOUNTER1_SELECT = 0x3bc8 # macro
regCHCG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regCHCG_PERFCOUNTER2_SELECT = 0x3bc9 # macro
regCHCG_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regCHCG_PERFCOUNTER3_SELECT = 0x3bca # macro
regCHCG_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regCB_PERFCOUNTER_FILTER = 0x3c00 # macro
regCB_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro
regCB_PERFCOUNTER0_SELECT = 0x3c01 # macro
regCB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regCB_PERFCOUNTER0_SELECT1 = 0x3c02 # macro
regCB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regCB_PERFCOUNTER1_SELECT = 0x3c03 # macro
regCB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regCB_PERFCOUNTER2_SELECT = 0x3c04 # macro
regCB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regCB_PERFCOUNTER3_SELECT = 0x3c05 # macro
regCB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regDB_PERFCOUNTER0_SELECT = 0x3c40 # macro
regDB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regDB_PERFCOUNTER0_SELECT1 = 0x3c41 # macro
regDB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regDB_PERFCOUNTER1_SELECT = 0x3c42 # macro
regDB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regDB_PERFCOUNTER1_SELECT1 = 0x3c43 # macro
regDB_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regDB_PERFCOUNTER2_SELECT = 0x3c44 # macro
regDB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regDB_PERFCOUNTER3_SELECT = 0x3c46 # macro
regDB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regRLC_SPM_PERFMON_CNTL = 0x3c80 # macro
regRLC_SPM_PERFMON_CNTL_BASE_IDX = 1 # macro
regRLC_SPM_PERFMON_RING_BASE_LO = 0x3c81 # macro
regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX = 1 # macro
regRLC_SPM_PERFMON_RING_BASE_HI = 0x3c82 # macro
regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX = 1 # macro
regRLC_SPM_PERFMON_RING_SIZE = 0x3c83 # macro
regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX = 1 # macro
regRLC_SPM_RING_WRPTR = 0x3c84 # macro
regRLC_SPM_RING_WRPTR_BASE_IDX = 1 # macro
regRLC_SPM_RING_RDPTR = 0x3c85 # macro
regRLC_SPM_RING_RDPTR_BASE_IDX = 1 # macro
regRLC_SPM_SEGMENT_THRESHOLD = 0x3c86 # macro
regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX = 1 # macro
regRLC_SPM_PERFMON_SEGMENT_SIZE = 0x3c87 # macro
regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX = 1 # macro
regRLC_SPM_GLOBAL_MUXSEL_ADDR = 0x3c88 # macro
regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX = 1 # macro
regRLC_SPM_GLOBAL_MUXSEL_DATA = 0x3c89 # macro
regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX = 1 # macro
regRLC_SPM_SE_MUXSEL_ADDR = 0x3c8a # macro
regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX = 1 # macro
regRLC_SPM_SE_MUXSEL_DATA = 0x3c8b # macro
regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_DATARAM_ADDR = 0x3c92 # macro
regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_DATARAM_DATA = 0x3c93 # macro
regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_SWA_DATARAM_ADDR = 0x3c94 # macro
regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_SWA_DATARAM_DATA = 0x3c95 # macro
regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_CTRLRAM_ADDR = 0x3c96 # macro
regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_CTRLRAM_DATA = 0x3c97 # macro
regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET = 0x3c98 # macro
regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_STATUS = 0x3c99 # macro
regRLC_SPM_ACCUM_STATUS_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_CTRL = 0x3c9a # macro
regRLC_SPM_ACCUM_CTRL_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_MODE = 0x3c9b # macro
regRLC_SPM_ACCUM_MODE_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_THRESHOLD = 0x3c9c # macro
regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_SAMPLES_REQUESTED = 0x3c9d # macro
regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_DATARAM_WRCOUNT = 0x3c9e # macro
regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX = 1 # macro
regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS = 0x3c9f # macro
regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX = 1 # macro
regRLC_SPM_PAUSE = 0x3ca2 # macro
regRLC_SPM_PAUSE_BASE_IDX = 1 # macro
regRLC_SPM_STATUS = 0x3ca3 # macro
regRLC_SPM_STATUS_BASE_IDX = 1 # macro
regRLC_SPM_GFXCLOCK_LOWCOUNT = 0x3ca4 # macro
regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX = 1 # macro
regRLC_SPM_GFXCLOCK_HIGHCOUNT = 0x3ca5 # macro
regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX = 1 # macro
regRLC_SPM_MODE = 0x3cad # macro
regRLC_SPM_MODE_BASE_IDX = 1 # macro
regRLC_SPM_RSPM_REQ_DATA_LO = 0x3cae # macro
regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX = 1 # macro
regRLC_SPM_RSPM_REQ_DATA_HI = 0x3caf # macro
regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX = 1 # macro
regRLC_SPM_RSPM_REQ_OP = 0x3cb0 # macro
regRLC_SPM_RSPM_REQ_OP_BASE_IDX = 1 # macro
regRLC_SPM_RSPM_RET_DATA = 0x3cb1 # macro
regRLC_SPM_RSPM_RET_DATA_BASE_IDX = 1 # macro
regRLC_SPM_RSPM_RET_OP = 0x3cb2 # macro
regRLC_SPM_RSPM_RET_OP_BASE_IDX = 1 # macro
regRLC_SPM_SE_RSPM_REQ_DATA_LO = 0x3cb3 # macro
regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX = 1 # macro
regRLC_SPM_SE_RSPM_REQ_DATA_HI = 0x3cb4 # macro
regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX = 1 # macro
regRLC_SPM_SE_RSPM_REQ_OP = 0x3cb5 # macro
regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX = 1 # macro
regRLC_SPM_SE_RSPM_RET_DATA = 0x3cb6 # macro
regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX = 1 # macro
regRLC_SPM_SE_RSPM_RET_OP = 0x3cb7 # macro
regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX = 1 # macro
regRLC_SPM_RSPM_CMD = 0x3cb8 # macro
regRLC_SPM_RSPM_CMD_BASE_IDX = 1 # macro
regRLC_SPM_RSPM_CMD_ACK = 0x3cb9 # macro
regRLC_SPM_RSPM_CMD_ACK_BASE_IDX = 1 # macro
regRLC_SPM_SPARE = 0x3cbf # macro
regRLC_SPM_SPARE_BASE_IDX = 1 # macro
regRLC_PERFMON_CNTL = 0x3cc0 # macro
regRLC_PERFMON_CNTL_BASE_IDX = 1 # macro
regRLC_PERFCOUNTER0_SELECT = 0x3cc1 # macro
regRLC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regRLC_PERFCOUNTER1_SELECT = 0x3cc2 # macro
regRLC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regRLC_GPU_IOV_PERF_CNT_CNTL = 0x3cc3 # macro
regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX = 1 # macro
regRLC_GPU_IOV_PERF_CNT_WR_ADDR = 0x3cc4 # macro
regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX = 1 # macro
regRLC_GPU_IOV_PERF_CNT_WR_DATA = 0x3cc5 # macro
regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX = 1 # macro
regRLC_GPU_IOV_PERF_CNT_RD_ADDR = 0x3cc6 # macro
regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX = 1 # macro
regRLC_GPU_IOV_PERF_CNT_RD_DATA = 0x3cc7 # macro
regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER0_SELECT = 0x3d00 # macro
regRMI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER0_SELECT1 = 0x3d01 # macro
regRMI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER1_SELECT = 0x3d02 # macro
regRMI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER2_SELECT = 0x3d03 # macro
regRMI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER2_SELECT1 = 0x3d04 # macro
regRMI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
regRMI_PERFCOUNTER3_SELECT = 0x3d05 # macro
regRMI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regRMI_PERF_COUNTER_CNTL = 0x3d06 # macro
regRMI_PERF_COUNTER_CNTL_BASE_IDX = 1 # macro
regGCR_PERFCOUNTER0_SELECT = 0x3d60 # macro
regGCR_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regGCR_PERFCOUNTER0_SELECT1 = 0x3d61 # macro
regGCR_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regGCR_PERFCOUNTER1_SELECT = 0x3d62 # macro
regGCR_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER0_SELECT = 0x3d80 # macro
regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER0_SELECT1 = 0x3d81 # macro
regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER1_SELECT = 0x3d82 # macro
regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER2_SELECT = 0x3d83 # macro
regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER3_SELECT = 0x3d84 # macro
regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER4_SELECT = 0x3d85 # macro
regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER5_SELECT = 0x3d86 # macro
regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER6_SELECT = 0x3d87 # macro
regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER7_SELECT = 0x3d88 # macro
regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER1_SELECT1 = 0x3d90 # macro
regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER2_SELECT1 = 0x3d91 # macro
regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
regPA_PH_PERFCOUNTER3_SELECT1 = 0x3d92 # macro
regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
regUTCL1_PERFCOUNTER0_SELECT = 0x3da0 # macro
regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regUTCL1_PERFCOUNTER1_SELECT = 0x3da1 # macro
regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regUTCL1_PERFCOUNTER2_SELECT = 0x3da2 # macro
regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regUTCL1_PERFCOUNTER3_SELECT = 0x3da3 # macro
regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regGL1A_PERFCOUNTER0_SELECT = 0x3dc0 # macro
regGL1A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regGL1A_PERFCOUNTER0_SELECT1 = 0x3dc1 # macro
regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regGL1A_PERFCOUNTER1_SELECT = 0x3dc2 # macro
regGL1A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regGL1A_PERFCOUNTER2_SELECT = 0x3dc3 # macro
regGL1A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regGL1A_PERFCOUNTER3_SELECT = 0x3dc4 # macro
regGL1A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regGL1H_PERFCOUNTER0_SELECT = 0x3dd0 # macro
regGL1H_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regGL1H_PERFCOUNTER0_SELECT1 = 0x3dd1 # macro
regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regGL1H_PERFCOUNTER1_SELECT = 0x3dd2 # macro
regGL1H_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regGL1H_PERFCOUNTER2_SELECT = 0x3dd3 # macro
regGL1H_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regGL1H_PERFCOUNTER3_SELECT = 0x3dd4 # macro
regGL1H_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regCHA_PERFCOUNTER0_SELECT = 0x3de0 # macro
regCHA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
regCHA_PERFCOUNTER0_SELECT1 = 0x3de1 # macro
regCHA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
regCHA_PERFCOUNTER1_SELECT = 0x3de2 # macro
regCHA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
regCHA_PERFCOUNTER2_SELECT = 0x3de3 # macro
regCHA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regCHA_PERFCOUNTER3_SELECT = 0x3de4 # macro
regCHA_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
regGUS_PERFCOUNTER2_SELECT = 0x3e00 # macro
regGUS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
regGUS_PERFCOUNTER2_SELECT1 = 0x3e01 # macro
regGUS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
regGUS_PERFCOUNTER2_MODE = 0x3e02 # macro
regGUS_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro
regGUS_PERFCOUNTER0_CFG = 0x3e03 # macro
regGUS_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
regGUS_PERFCOUNTER1_CFG = 0x3e04 # macro
regGUS_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
regGUS_PERFCOUNTER_RSLT_CNTL = 0x3e05 # macro
regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
regGRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro
regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro
regGRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro
regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro
regGRTAVFS_GENERAL_0 = 0x4b02 # macro
regGRTAVFS_GENERAL_0_BASE_IDX = 1 # macro
regGRTAVFS_RTAVFS_RD_DATA = 0x4b03 # macro
regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX = 1 # macro
regGRTAVFS_RTAVFS_REG_CTRL = 0x4b04 # macro
regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX = 1 # macro
regGRTAVFS_RTAVFS_REG_STATUS = 0x4b05 # macro
regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX = 1 # macro
regGRTAVFS_TARG_FREQ = 0x4b06 # macro
regGRTAVFS_TARG_FREQ_BASE_IDX = 1 # macro
regGRTAVFS_TARG_VOLT = 0x4b07 # macro
regGRTAVFS_TARG_VOLT_BASE_IDX = 1 # macro
regGRTAVFS_SOFT_RESET = 0x4b0c # macro
regGRTAVFS_SOFT_RESET_BASE_IDX = 1 # macro
regGRTAVFS_PSM_CNTL = 0x4b0d # macro
regGRTAVFS_PSM_CNTL_BASE_IDX = 1 # macro
regGRTAVFS_CLK_CNTL = 0x4b0e # macro
regGRTAVFS_CLK_CNTL_BASE_IDX = 1 # macro
regGRTAVFS_SE_RTAVFS_REG_ADDR = 0x4b40 # macro
regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro
regGRTAVFS_SE_RTAVFS_WR_DATA = 0x4b41 # macro
regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX = 1 # macro
regGRTAVFS_SE_GENERAL_0 = 0x4b42 # macro
regGRTAVFS_SE_GENERAL_0_BASE_IDX = 1 # macro
regGRTAVFS_SE_RTAVFS_RD_DATA = 0x4b43 # macro
regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX = 1 # macro
regGRTAVFS_SE_RTAVFS_REG_CTRL = 0x4b44 # macro
regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX = 1 # macro
regGRTAVFS_SE_RTAVFS_REG_STATUS = 0x4b45 # macro
regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX = 1 # macro
regGRTAVFS_SE_TARG_FREQ = 0x4b46 # macro
regGRTAVFS_SE_TARG_FREQ_BASE_IDX = 1 # macro
regGRTAVFS_SE_TARG_VOLT = 0x4b47 # macro
regGRTAVFS_SE_TARG_VOLT_BASE_IDX = 1 # macro
regGRTAVFS_SE_SOFT_RESET = 0x4b4c # macro
regGRTAVFS_SE_SOFT_RESET_BASE_IDX = 1 # macro
regGRTAVFS_SE_PSM_CNTL = 0x4b4d # macro
regGRTAVFS_SE_PSM_CNTL_BASE_IDX = 1 # macro
regGRTAVFS_SE_CLK_CNTL = 0x4b4e # macro
regGRTAVFS_SE_CLK_CNTL_BASE_IDX = 1 # macro
regRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro
regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro
regRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro
regRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro
regCP_HYP_PFP_UCODE_ADDR = 0x5814 # macro
regCP_HYP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro
regCP_PFP_UCODE_ADDR = 0x5814 # macro
regCP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro
regCP_HYP_PFP_UCODE_DATA = 0x5815 # macro
regCP_HYP_PFP_UCODE_DATA_BASE_IDX = 1 # macro
regCP_PFP_UCODE_DATA = 0x5815 # macro
regCP_PFP_UCODE_DATA_BASE_IDX = 1 # macro
regCP_HYP_ME_UCODE_ADDR = 0x5816 # macro
regCP_HYP_ME_UCODE_ADDR_BASE_IDX = 1 # macro
regCP_ME_RAM_RADDR = 0x5816 # macro
regCP_ME_RAM_RADDR_BASE_IDX = 1 # macro
regCP_ME_RAM_WADDR = 0x5816 # macro
regCP_ME_RAM_WADDR_BASE_IDX = 1 # macro
regCP_HYP_ME_UCODE_DATA = 0x5817 # macro
regCP_HYP_ME_UCODE_DATA_BASE_IDX = 1 # macro
regCP_ME_RAM_DATA = 0x5817 # macro
regCP_ME_RAM_DATA_BASE_IDX = 1 # macro
regCP_HYP_MEC1_UCODE_ADDR = 0x581a # macro
regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX = 1 # macro
regCP_MEC_ME1_UCODE_ADDR = 0x581a # macro
regCP_MEC_ME1_UCODE_ADDR_BASE_IDX = 1 # macro
regCP_HYP_MEC1_UCODE_DATA = 0x581b # macro
regCP_HYP_MEC1_UCODE_DATA_BASE_IDX = 1 # macro
regCP_MEC_ME1_UCODE_DATA = 0x581b # macro
regCP_MEC_ME1_UCODE_DATA_BASE_IDX = 1 # macro
regCP_HYP_MEC2_UCODE_ADDR = 0x581c # macro
regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX = 1 # macro
regCP_MEC_ME2_UCODE_ADDR = 0x581c # macro
regCP_MEC_ME2_UCODE_ADDR_BASE_IDX = 1 # macro
regCP_HYP_MEC2_UCODE_DATA = 0x581d # macro
regCP_HYP_MEC2_UCODE_DATA_BASE_IDX = 1 # macro
regCP_MEC_ME2_UCODE_DATA = 0x581d # macro
regCP_MEC_ME2_UCODE_DATA_BASE_IDX = 1 # macro
regCP_PFP_IC_BASE_LO = 0x5840 # macro
regCP_PFP_IC_BASE_LO_BASE_IDX = 1 # macro
regCP_PFP_IC_BASE_HI = 0x5841 # macro
regCP_PFP_IC_BASE_HI_BASE_IDX = 1 # macro
regCP_PFP_IC_BASE_CNTL = 0x5842 # macro
regCP_PFP_IC_BASE_CNTL_BASE_IDX = 1 # macro
regCP_PFP_IC_OP_CNTL = 0x5843 # macro
regCP_PFP_IC_OP_CNTL_BASE_IDX = 1 # macro
regCP_ME_IC_BASE_LO = 0x5844 # macro
regCP_ME_IC_BASE_LO_BASE_IDX = 1 # macro
regCP_ME_IC_BASE_HI = 0x5845 # macro
regCP_ME_IC_BASE_HI_BASE_IDX = 1 # macro
regCP_ME_IC_BASE_CNTL = 0x5846 # macro
regCP_ME_IC_BASE_CNTL_BASE_IDX = 1 # macro
regCP_ME_IC_OP_CNTL = 0x5847 # macro
regCP_ME_IC_OP_CNTL_BASE_IDX = 1 # macro
regCP_CPC_IC_BASE_LO = 0x584c # macro
regCP_CPC_IC_BASE_LO_BASE_IDX = 1 # macro
regCP_CPC_IC_BASE_HI = 0x584d # macro
regCP_CPC_IC_BASE_HI_BASE_IDX = 1 # macro
regCP_CPC_IC_BASE_CNTL = 0x584e # macro
regCP_CPC_IC_BASE_CNTL_BASE_IDX = 1 # macro
regCP_MES_IC_BASE_LO = 0x5850 # macro
regCP_MES_IC_BASE_LO_BASE_IDX = 1 # macro
regCP_MES_MIBASE_LO = 0x5850 # macro
regCP_MES_MIBASE_LO_BASE_IDX = 1 # macro
regCP_MES_IC_BASE_HI = 0x5851 # macro
regCP_MES_IC_BASE_HI_BASE_IDX = 1 # macro
regCP_MES_MIBASE_HI = 0x5851 # macro
regCP_MES_MIBASE_HI_BASE_IDX = 1 # macro
regCP_MES_IC_BASE_CNTL = 0x5852 # macro
regCP_MES_IC_BASE_CNTL_BASE_IDX = 1 # macro
regCP_MES_DC_BASE_LO = 0x5854 # macro
regCP_MES_DC_BASE_LO_BASE_IDX = 1 # macro
regCP_MES_MDBASE_LO = 0x5854 # macro
regCP_MES_MDBASE_LO_BASE_IDX = 1 # macro
regCP_MES_DC_BASE_HI = 0x5855 # macro
regCP_MES_DC_BASE_HI_BASE_IDX = 1 # macro
regCP_MES_MDBASE_HI = 0x5855 # macro
regCP_MES_MDBASE_HI_BASE_IDX = 1 # macro
regCP_MES_MIBOUND_LO = 0x585b # macro
regCP_MES_MIBOUND_LO_BASE_IDX = 1 # macro
regCP_MES_MIBOUND_HI = 0x585c # macro
regCP_MES_MIBOUND_HI_BASE_IDX = 1 # macro
regCP_MES_MDBOUND_LO = 0x585d # macro
regCP_MES_MDBOUND_LO_BASE_IDX = 1 # macro
regCP_MES_MDBOUND_HI = 0x585e # macro
regCP_MES_MDBOUND_HI_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_BASE0_LO = 0x5863 # macro
regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_BASE1_LO = 0x5864 # macro
regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_BASE0_HI = 0x5865 # macro
regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX = 1 # macro
regCP_GFX_RS64_DC_BASE1_HI = 0x5866 # macro
regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX = 1 # macro
regCP_GFX_RS64_MIBOUND_LO = 0x586c # macro
regCP_GFX_RS64_MIBOUND_LO_BASE_IDX = 1 # macro
regCP_GFX_RS64_MIBOUND_HI = 0x586d # macro
regCP_GFX_RS64_MIBOUND_HI_BASE_IDX = 1 # macro
regCP_MEC_DC_BASE_LO = 0x5870 # macro
regCP_MEC_DC_BASE_LO_BASE_IDX = 1 # macro
regCP_MEC_MDBASE_LO = 0x5870 # macro
regCP_MEC_MDBASE_LO_BASE_IDX = 1 # macro
regCP_MEC_DC_BASE_HI = 0x5871 # macro
regCP_MEC_DC_BASE_HI_BASE_IDX = 1 # macro
regCP_MEC_MDBASE_HI = 0x5871 # macro
regCP_MEC_MDBASE_HI_BASE_IDX = 1 # macro
regCP_MEC_MIBOUND_LO = 0x5872 # macro
regCP_MEC_MIBOUND_LO_BASE_IDX = 1 # macro
regCP_MEC_MIBOUND_HI = 0x5873 # macro
regCP_MEC_MIBOUND_HI_BASE_IDX = 1 # macro
regCP_MEC_MDBOUND_LO = 0x5874 # macro
regCP_MEC_MDBOUND_LO_BASE_IDX = 1 # macro
regCP_MEC_MDBOUND_HI = 0x5875 # macro
regCP_MEC_MDBOUND_HI_BASE_IDX = 1 # macro
regRLC_CNTL = 0x4c00 # macro
regRLC_CNTL_BASE_IDX = 1 # macro
regRLC_F32_UCODE_VERSION = 0x4c03 # macro
regRLC_F32_UCODE_VERSION_BASE_IDX = 1 # macro
regRLC_STAT = 0x4c04 # macro
regRLC_STAT_BASE_IDX = 1 # macro
regRLC_REFCLOCK_TIMESTAMP_LSB = 0x4c0c # macro
regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX = 1 # macro
regRLC_REFCLOCK_TIMESTAMP_MSB = 0x4c0d # macro
regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX = 1 # macro
regRLC_GPM_TIMER_INT_0 = 0x4c0e # macro
regRLC_GPM_TIMER_INT_0_BASE_IDX = 1 # macro
regRLC_GPM_TIMER_INT_1 = 0x4c0f # macro
regRLC_GPM_TIMER_INT_1_BASE_IDX = 1 # macro
regRLC_GPM_TIMER_INT_2 = 0x4c10 # macro
regRLC_GPM_TIMER_INT_2_BASE_IDX = 1 # macro
regRLC_GPM_TIMER_INT_3 = 0x4c11 # macro
regRLC_GPM_TIMER_INT_3_BASE_IDX = 1 # macro
regRLC_GPM_TIMER_INT_4 = 0x4c12 # macro
regRLC_GPM_TIMER_INT_4_BASE_IDX = 1 # macro
regRLC_GPM_TIMER_CTRL = 0x4c13 # macro
regRLC_GPM_TIMER_CTRL_BASE_IDX = 1 # macro
regRLC_GPM_TIMER_STAT = 0x4c14 # macro
regRLC_GPM_TIMER_STAT_BASE_IDX = 1 # macro
regRLC_GPM_LEGACY_INT_STAT = 0x4c16 # macro
regRLC_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro
regRLC_GPM_LEGACY_INT_CLEAR = 0x4c17 # macro
regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX = 1 # macro
regRLC_INT_STAT = 0x4c18 # macro
regRLC_INT_STAT_BASE_IDX = 1 # macro
regRLC_MGCG_CTRL = 0x4c1a # macro
regRLC_MGCG_CTRL_BASE_IDX = 1 # macro
regRLC_JUMP_TABLE_RESTORE = 0x4c1e # macro
regRLC_JUMP_TABLE_RESTORE_BASE_IDX = 1 # macro
regRLC_PG_DELAY_2 = 0x4c1f # macro
regRLC_PG_DELAY_2_BASE_IDX = 1 # macro
regRLC_GPU_CLOCK_COUNT_LSB = 0x4c24 # macro
regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX = 1 # macro
regRLC_GPU_CLOCK_COUNT_MSB = 0x4c25 # macro
regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX = 1 # macro
regRLC_CAPTURE_GPU_CLOCK_COUNT = 0x4c26 # macro
regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX = 1 # macro
regRLC_UCODE_CNTL = 0x4c27 # macro
regRLC_UCODE_CNTL_BASE_IDX = 1 # macro
regRLC_GPM_THREAD_RESET = 0x4c28 # macro
regRLC_GPM_THREAD_RESET_BASE_IDX = 1 # macro
regRLC_GPM_CP_DMA_COMPLETE_T0 = 0x4c29 # macro
regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX = 1 # macro
regRLC_GPM_CP_DMA_COMPLETE_T1 = 0x4c2a # macro
regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX = 1 # macro
regRLC_GPM_THREAD_INVALIDATE_CACHE = 0x4c2b # macro
regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX = 1 # macro
regRLC_CLK_COUNT_GFXCLK_LSB = 0x4c30 # macro
regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX = 1 # macro
regRLC_CLK_COUNT_GFXCLK_MSB = 0x4c31 # macro
regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX = 1 # macro
regRLC_CLK_COUNT_REFCLK_LSB = 0x4c32 # macro
regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX = 1 # macro
regRLC_CLK_COUNT_REFCLK_MSB = 0x4c33 # macro
regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX = 1 # macro
regRLC_CLK_COUNT_CTRL = 0x4c34 # macro
regRLC_CLK_COUNT_CTRL_BASE_IDX = 1 # macro
regRLC_CLK_COUNT_STAT = 0x4c35 # macro
regRLC_CLK_COUNT_STAT_BASE_IDX = 1 # macro
regRLC_RLCG_DOORBELL_CNTL = 0x4c36 # macro
regRLC_RLCG_DOORBELL_CNTL_BASE_IDX = 1 # macro
regRLC_RLCG_DOORBELL_STAT = 0x4c37 # macro
regRLC_RLCG_DOORBELL_STAT_BASE_IDX = 1 # macro
regRLC_RLCG_DOORBELL_0_DATA_LO = 0x4c38 # macro
regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro
regRLC_RLCG_DOORBELL_0_DATA_HI = 0x4c39 # macro
regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro
regRLC_RLCG_DOORBELL_1_DATA_LO = 0x4c3a # macro
regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro
regRLC_RLCG_DOORBELL_1_DATA_HI = 0x4c3b # macro
regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro
regRLC_RLCG_DOORBELL_2_DATA_LO = 0x4c3c # macro
regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro
regRLC_RLCG_DOORBELL_2_DATA_HI = 0x4c3d # macro
regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro
regRLC_RLCG_DOORBELL_3_DATA_LO = 0x4c3e # macro
regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro
regRLC_RLCG_DOORBELL_3_DATA_HI = 0x4c3f # macro
regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro
regRLC_GPU_CLOCK_32_RES_SEL = 0x4c41 # macro
regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX = 1 # macro
regRLC_GPU_CLOCK_32 = 0x4c42 # macro
regRLC_GPU_CLOCK_32_BASE_IDX = 1 # macro
regRLC_PG_CNTL = 0x4c43 # macro
regRLC_PG_CNTL_BASE_IDX = 1 # macro
regRLC_GPM_THREAD_PRIORITY = 0x4c44 # macro
regRLC_GPM_THREAD_PRIORITY_BASE_IDX = 1 # macro
regRLC_GPM_THREAD_ENABLE = 0x4c45 # macro
regRLC_GPM_THREAD_ENABLE_BASE_IDX = 1 # macro
regRLC_RLCG_DOORBELL_RANGE = 0x4c47 # macro
regRLC_RLCG_DOORBELL_RANGE_BASE_IDX = 1 # macro
regRLC_CGTT_MGCG_OVERRIDE = 0x4c48 # macro
regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX = 1 # macro
regRLC_CGCG_CGLS_CTRL = 0x4c49 # macro
regRLC_CGCG_CGLS_CTRL_BASE_IDX = 1 # macro
regRLC_CGCG_RAMP_CTRL = 0x4c4a # macro
regRLC_CGCG_RAMP_CTRL_BASE_IDX = 1 # macro
regRLC_DYN_PG_STATUS = 0x4c4b # macro
regRLC_DYN_PG_STATUS_BASE_IDX = 1 # macro
regRLC_DYN_PG_REQUEST = 0x4c4c # macro
regRLC_DYN_PG_REQUEST_BASE_IDX = 1 # macro
regRLC_PG_DELAY = 0x4c4d # macro
regRLC_PG_DELAY_BASE_IDX = 1 # macro
regRLC_WGP_STATUS = 0x4c4e # macro
regRLC_WGP_STATUS_BASE_IDX = 1 # macro
regRLC_PG_ALWAYS_ON_WGP_MASK = 0x4c53 # macro
regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX = 1 # macro
regRLC_MAX_PG_WGP = 0x4c54 # macro
regRLC_MAX_PG_WGP_BASE_IDX = 1 # macro
regRLC_AUTO_PG_CTRL = 0x4c55 # macro
regRLC_AUTO_PG_CTRL_BASE_IDX = 1 # macro
regRLC_SERDES_RD_INDEX = 0x4c59 # macro
regRLC_SERDES_RD_INDEX_BASE_IDX = 1 # macro
regRLC_SERDES_RD_DATA_0 = 0x4c5a # macro
regRLC_SERDES_RD_DATA_0_BASE_IDX = 1 # macro
regRLC_SERDES_RD_DATA_1 = 0x4c5b # macro
regRLC_SERDES_RD_DATA_1_BASE_IDX = 1 # macro
regRLC_SERDES_RD_DATA_2 = 0x4c5c # macro
regRLC_SERDES_RD_DATA_2_BASE_IDX = 1 # macro
regRLC_SERDES_RD_DATA_3 = 0x4c5d # macro
regRLC_SERDES_RD_DATA_3_BASE_IDX = 1 # macro
regRLC_SERDES_MASK = 0x4c5e # macro
regRLC_SERDES_MASK_BASE_IDX = 1 # macro
regRLC_SERDES_CTRL = 0x4c5f # macro
regRLC_SERDES_CTRL_BASE_IDX = 1 # macro
regRLC_SERDES_DATA = 0x4c60 # macro
regRLC_SERDES_DATA_BASE_IDX = 1 # macro
regRLC_SERDES_BUSY = 0x4c61 # macro
regRLC_SERDES_BUSY_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_0 = 0x4c63 # macro
regRLC_GPM_GENERAL_0_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_1 = 0x4c64 # macro
regRLC_GPM_GENERAL_1_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_2 = 0x4c65 # macro
regRLC_GPM_GENERAL_2_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_3 = 0x4c66 # macro
regRLC_GPM_GENERAL_3_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_4 = 0x4c67 # macro
regRLC_GPM_GENERAL_4_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_5 = 0x4c68 # macro
regRLC_GPM_GENERAL_5_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_6 = 0x4c69 # macro
regRLC_GPM_GENERAL_6_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_7 = 0x4c6a # macro
regRLC_GPM_GENERAL_7_BASE_IDX = 1 # macro
regRLC_STATIC_PG_STATUS = 0x4c6e # macro
regRLC_STATIC_PG_STATUS_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_16 = 0x4c76 # macro
regRLC_GPM_GENERAL_16_BASE_IDX = 1 # macro
regRLC_PG_DELAY_3 = 0x4c78 # macro
regRLC_PG_DELAY_3_BASE_IDX = 1 # macro
regRLC_GPR_REG1 = 0x4c79 # macro
regRLC_GPR_REG1_BASE_IDX = 1 # macro
regRLC_GPR_REG2 = 0x4c7a # macro
regRLC_GPR_REG2_BASE_IDX = 1 # macro
regRLC_GPM_INT_DISABLE_TH0 = 0x4c7c # macro
regRLC_GPM_INT_DISABLE_TH0_BASE_IDX = 1 # macro
regRLC_GPM_LEGACY_INT_DISABLE = 0x4c7d # macro
regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro
regRLC_GPM_INT_FORCE_TH0 = 0x4c7e # macro
regRLC_GPM_INT_FORCE_TH0_BASE_IDX = 1 # macro
regRLC_SRM_CNTL = 0x4c80 # macro
regRLC_SRM_CNTL_BASE_IDX = 1 # macro
regRLC_SRM_GPM_COMMAND_STATUS = 0x4c88 # macro
regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_ADDR_0 = 0x4c8b # macro
regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_ADDR_1 = 0x4c8c # macro
regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_ADDR_2 = 0x4c8d # macro
regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_ADDR_3 = 0x4c8e # macro
regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_ADDR_4 = 0x4c8f # macro
regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_ADDR_5 = 0x4c90 # macro
regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_ADDR_6 = 0x4c91 # macro
regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_ADDR_7 = 0x4c92 # macro
regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_DATA_0 = 0x4c93 # macro
regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_DATA_1 = 0x4c94 # macro
regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_DATA_2 = 0x4c95 # macro
regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_DATA_3 = 0x4c96 # macro
regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_DATA_4 = 0x4c97 # macro
regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_DATA_5 = 0x4c98 # macro
regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_DATA_6 = 0x4c99 # macro
regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX = 1 # macro
regRLC_SRM_INDEX_CNTL_DATA_7 = 0x4c9a # macro
regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX = 1 # macro
regRLC_SRM_STAT = 0x4c9b # macro
regRLC_SRM_STAT_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_8 = 0x4cad # macro
regRLC_GPM_GENERAL_8_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_9 = 0x4cae # macro
regRLC_GPM_GENERAL_9_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_10 = 0x4caf # macro
regRLC_GPM_GENERAL_10_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_11 = 0x4cb0 # macro
regRLC_GPM_GENERAL_11_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_12 = 0x4cb1 # macro
regRLC_GPM_GENERAL_12_BASE_IDX = 1 # macro
regRLC_GPM_UTCL1_CNTL_0 = 0x4cb2 # macro
regRLC_GPM_UTCL1_CNTL_0_BASE_IDX = 1 # macro
regRLC_GPM_UTCL1_CNTL_1 = 0x4cb3 # macro
regRLC_GPM_UTCL1_CNTL_1_BASE_IDX = 1 # macro
regRLC_GPM_UTCL1_CNTL_2 = 0x4cb4 # macro
regRLC_GPM_UTCL1_CNTL_2_BASE_IDX = 1 # macro
regRLC_SPM_UTCL1_CNTL = 0x4cb5 # macro
regRLC_SPM_UTCL1_CNTL_BASE_IDX = 1 # macro
regRLC_UTCL1_STATUS_2 = 0x4cb6 # macro
regRLC_UTCL1_STATUS_2_BASE_IDX = 1 # macro
regRLC_SPM_UTCL1_ERROR_1 = 0x4cbc # macro
regRLC_SPM_UTCL1_ERROR_1_BASE_IDX = 1 # macro
regRLC_SPM_UTCL1_ERROR_2 = 0x4cbd # macro
regRLC_SPM_UTCL1_ERROR_2_BASE_IDX = 1 # macro
regRLC_GPM_UTCL1_TH0_ERROR_1 = 0x4cbe # macro
regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX = 1 # macro
regRLC_GPM_UTCL1_TH0_ERROR_2 = 0x4cc0 # macro
regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX = 1 # macro
regRLC_GPM_UTCL1_TH1_ERROR_1 = 0x4cc1 # macro
regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX = 1 # macro
regRLC_GPM_UTCL1_TH1_ERROR_2 = 0x4cc2 # macro
regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX = 1 # macro
regRLC_GPM_UTCL1_TH2_ERROR_1 = 0x4cc3 # macro
regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX = 1 # macro
regRLC_GPM_UTCL1_TH2_ERROR_2 = 0x4cc4 # macro
regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX = 1 # macro
regRLC_CGCG_CGLS_CTRL_3D = 0x4cc5 # macro
regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX = 1 # macro
regRLC_CGCG_RAMP_CTRL_3D = 0x4cc6 # macro
regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX = 1 # macro
regRLC_SEMAPHORE_0 = 0x4cc7 # macro
regRLC_SEMAPHORE_0_BASE_IDX = 1 # macro
regRLC_SEMAPHORE_1 = 0x4cc8 # macro
regRLC_SEMAPHORE_1_BASE_IDX = 1 # macro
regRLC_SEMAPHORE_2 = 0x4cc9 # macro
regRLC_SEMAPHORE_2_BASE_IDX = 1 # macro
regRLC_SEMAPHORE_3 = 0x4cca # macro
regRLC_SEMAPHORE_3_BASE_IDX = 1 # macro
regRLC_PACE_INT_STAT = 0x4ccc # macro
regRLC_PACE_INT_STAT_BASE_IDX = 1 # macro
regRLC_UTCL1_STATUS = 0x4cd4 # macro
regRLC_UTCL1_STATUS_BASE_IDX = 1 # macro
regRLC_R2I_CNTL_0 = 0x4cd5 # macro
regRLC_R2I_CNTL_0_BASE_IDX = 1 # macro
regRLC_R2I_CNTL_1 = 0x4cd6 # macro
regRLC_R2I_CNTL_1_BASE_IDX = 1 # macro
regRLC_R2I_CNTL_2 = 0x4cd7 # macro
regRLC_R2I_CNTL_2_BASE_IDX = 1 # macro
regRLC_R2I_CNTL_3 = 0x4cd8 # macro
regRLC_R2I_CNTL_3_BASE_IDX = 1 # macro
regRLC_GPM_INT_STAT_TH0 = 0x4cdc # macro
regRLC_GPM_INT_STAT_TH0_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_13 = 0x4cdd # macro
regRLC_GPM_GENERAL_13_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_14 = 0x4cde # macro
regRLC_GPM_GENERAL_14_BASE_IDX = 1 # macro
regRLC_GPM_GENERAL_15 = 0x4cdf # macro
regRLC_GPM_GENERAL_15_BASE_IDX = 1 # macro
regRLC_CAPTURE_GPU_CLOCK_COUNT_1 = 0x4cea # macro
regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX = 1 # macro
regRLC_GPU_CLOCK_COUNT_LSB_2 = 0x4ceb # macro
regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX = 1 # macro
regRLC_GPU_CLOCK_COUNT_MSB_2 = 0x4cec # macro
regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX = 1 # macro
regRLC_PACE_INT_DISABLE = 0x4ced # macro
regRLC_PACE_INT_DISABLE_BASE_IDX = 1 # macro
regRLC_CAPTURE_GPU_CLOCK_COUNT_2 = 0x4cef # macro
regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX = 1 # macro
regRLC_RLCV_DOORBELL_RANGE = 0x4cf0 # macro
regRLC_RLCV_DOORBELL_RANGE_BASE_IDX = 1 # macro
regRLC_RLCV_DOORBELL_CNTL = 0x4cf1 # macro
regRLC_RLCV_DOORBELL_CNTL_BASE_IDX = 1 # macro
regRLC_RLCV_DOORBELL_STAT = 0x4cf2 # macro
regRLC_RLCV_DOORBELL_STAT_BASE_IDX = 1 # macro
regRLC_RLCV_DOORBELL_0_DATA_LO = 0x4cf3 # macro
regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro
regRLC_RLCV_DOORBELL_0_DATA_HI = 0x4cf4 # macro
regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro
regRLC_RLCV_DOORBELL_1_DATA_LO = 0x4cf5 # macro
regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro
regRLC_RLCV_DOORBELL_1_DATA_HI = 0x4cf6 # macro
regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro
regRLC_RLCV_DOORBELL_2_DATA_LO = 0x4cf7 # macro
regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro
regRLC_RLCV_DOORBELL_2_DATA_HI = 0x4cf8 # macro
regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro
regRLC_RLCV_DOORBELL_3_DATA_LO = 0x4cf9 # macro
regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro
regRLC_RLCV_DOORBELL_3_DATA_HI = 0x4cfa # macro
regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro
regRLC_GPU_CLOCK_COUNT_LSB_1 = 0x4cfb # macro
regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX = 1 # macro
regRLC_GPU_CLOCK_COUNT_MSB_1 = 0x4cfc # macro
regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX = 1 # macro
regRLC_RLCV_SPARE_INT = 0x4d00 # macro
regRLC_RLCV_SPARE_INT_BASE_IDX = 1 # macro
regRLC_PACE_TIMER_INT_0 = 0x4d04 # macro
regRLC_PACE_TIMER_INT_0_BASE_IDX = 1 # macro
regRLC_PACE_TIMER_INT_1 = 0x4d05 # macro
regRLC_PACE_TIMER_INT_1_BASE_IDX = 1 # macro
regRLC_PACE_TIMER_CTRL = 0x4d06 # macro
regRLC_PACE_TIMER_CTRL_BASE_IDX = 1 # macro
regRLC_SMU_CLK_REQ = 0x4d08 # macro
regRLC_SMU_CLK_REQ_BASE_IDX = 1 # macro
regRLC_CP_STAT_INVAL_STAT = 0x4d09 # macro
regRLC_CP_STAT_INVAL_STAT_BASE_IDX = 1 # macro
regRLC_CP_STAT_INVAL_CTRL = 0x4d0a # macro
regRLC_CP_STAT_INVAL_CTRL_BASE_IDX = 1 # macro
regRLC_SPARE = 0x4d0b # macro
regRLC_SPARE_BASE_IDX = 1 # macro
regRLC_SPP_CTRL = 0x4d0c # macro
regRLC_SPP_CTRL_BASE_IDX = 1 # macro
regRLC_SPP_SHADER_PROFILE_EN = 0x4d0d # macro
regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX = 1 # macro
regRLC_SPP_SSF_CAPTURE_EN = 0x4d0e # macro
regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX = 1 # macro
regRLC_SPP_SSF_THRESHOLD_0 = 0x4d0f # macro
regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX = 1 # macro
regRLC_SPP_SSF_THRESHOLD_1 = 0x4d10 # macro
regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX = 1 # macro
regRLC_SPP_SSF_THRESHOLD_2 = 0x4d11 # macro
regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX = 1 # macro
regRLC_SPP_INFLIGHT_RD_ADDR = 0x4d12 # macro
regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX = 1 # macro
regRLC_SPP_INFLIGHT_RD_DATA = 0x4d13 # macro
regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX = 1 # macro
regRLC_SPP_PROF_INFO_1 = 0x4d18 # macro
regRLC_SPP_PROF_INFO_1_BASE_IDX = 1 # macro
regRLC_SPP_PROF_INFO_2 = 0x4d19 # macro
regRLC_SPP_PROF_INFO_2_BASE_IDX = 1 # macro
regRLC_SPP_GLOBAL_SH_ID = 0x4d1a # macro
regRLC_SPP_GLOBAL_SH_ID_BASE_IDX = 1 # macro
regRLC_SPP_GLOBAL_SH_ID_VALID = 0x4d1b # macro
regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX = 1 # macro
regRLC_SPP_STATUS = 0x4d1c # macro
regRLC_SPP_STATUS_BASE_IDX = 1 # macro
regRLC_SPP_PVT_STAT_0 = 0x4d1d # macro
regRLC_SPP_PVT_STAT_0_BASE_IDX = 1 # macro
regRLC_SPP_PVT_STAT_1 = 0x4d1e # macro
regRLC_SPP_PVT_STAT_1_BASE_IDX = 1 # macro
regRLC_SPP_PVT_STAT_2 = 0x4d1f # macro
regRLC_SPP_PVT_STAT_2_BASE_IDX = 1 # macro
regRLC_SPP_PVT_STAT_3 = 0x4d20 # macro
regRLC_SPP_PVT_STAT_3_BASE_IDX = 1 # macro
regRLC_SPP_PVT_LEVEL_MAX = 0x4d21 # macro
regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX = 1 # macro
regRLC_SPP_STALL_STATE_UPDATE = 0x4d22 # macro
regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX = 1 # macro
regRLC_SPP_PBB_INFO = 0x4d23 # macro
regRLC_SPP_PBB_INFO_BASE_IDX = 1 # macro
regRLC_SPP_RESET = 0x4d24 # macro
regRLC_SPP_RESET_BASE_IDX = 1 # macro
regRLC_RLCP_DOORBELL_RANGE = 0x4d26 # macro
regRLC_RLCP_DOORBELL_RANGE_BASE_IDX = 1 # macro
regRLC_RLCP_DOORBELL_CNTL = 0x4d27 # macro
regRLC_RLCP_DOORBELL_CNTL_BASE_IDX = 1 # macro
regRLC_RLCP_DOORBELL_STAT = 0x4d28 # macro
regRLC_RLCP_DOORBELL_STAT_BASE_IDX = 1 # macro
regRLC_RLCP_DOORBELL_0_DATA_LO = 0x4d29 # macro
regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro
regRLC_RLCP_DOORBELL_0_DATA_HI = 0x4d2a # macro
regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro
regRLC_RLCP_DOORBELL_1_DATA_LO = 0x4d2b # macro
regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro
regRLC_RLCP_DOORBELL_1_DATA_HI = 0x4d2c # macro
regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro
regRLC_RLCP_DOORBELL_2_DATA_LO = 0x4d2d # macro
regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro
regRLC_RLCP_DOORBELL_2_DATA_HI = 0x4d2e # macro
regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro
regRLC_RLCP_DOORBELL_3_DATA_LO = 0x4d2f # macro
regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro
regRLC_RLCP_DOORBELL_3_DATA_HI = 0x4d30 # macro
regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro
regRLC_CAC_MASK_CNTL = 0x4d45 # macro
regRLC_CAC_MASK_CNTL_BASE_IDX = 1 # macro
regRLC_POWER_RESIDENCY_CNTR_CTRL = 0x4d48 # macro
regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro
regRLC_CLK_RESIDENCY_CNTR_CTRL = 0x4d49 # macro
regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro
regRLC_DS_RESIDENCY_CNTR_CTRL = 0x4d4a # macro
regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro
regRLC_ULV_RESIDENCY_CNTR_CTRL = 0x4d4b # macro
regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro
regRLC_PCC_RESIDENCY_CNTR_CTRL = 0x4d4c # macro
regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro
regRLC_GENERAL_RESIDENCY_CNTR_CTRL = 0x4d4d # macro
regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro
regRLC_POWER_RESIDENCY_EVENT_CNTR = 0x4d50 # macro
regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro
regRLC_CLK_RESIDENCY_EVENT_CNTR = 0x4d51 # macro
regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro
regRLC_DS_RESIDENCY_EVENT_CNTR = 0x4d52 # macro
regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro
regRLC_ULV_RESIDENCY_EVENT_CNTR = 0x4d53 # macro
regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro
regRLC_PCC_RESIDENCY_EVENT_CNTR = 0x4d54 # macro
regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro
regRLC_GENERAL_RESIDENCY_EVENT_CNTR = 0x4d55 # macro
regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro
regRLC_POWER_RESIDENCY_REF_CNTR = 0x4d58 # macro
regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro
regRLC_CLK_RESIDENCY_REF_CNTR = 0x4d59 # macro
regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro
regRLC_DS_RESIDENCY_REF_CNTR = 0x4d5a # macro
regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro
regRLC_ULV_RESIDENCY_REF_CNTR = 0x4d5b # macro
regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro
regRLC_PCC_RESIDENCY_REF_CNTR = 0x4d5c # macro
regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro
regRLC_GENERAL_RESIDENCY_REF_CNTR = 0x4d5d # macro
regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro
regRLC_GFX_IH_CLIENT_CTRL = 0x4d5e # macro
regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX = 1 # macro
regRLC_GFX_IH_ARBITER_STAT = 0x4d5f # macro
regRLC_GFX_IH_ARBITER_STAT_BASE_IDX = 1 # macro
regRLC_GFX_IH_CLIENT_SE_STAT_L = 0x4d60 # macro
regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX = 1 # macro
regRLC_GFX_IH_CLIENT_SE_STAT_H = 0x4d61 # macro
regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX = 1 # macro
regRLC_GFX_IH_CLIENT_SDMA_STAT = 0x4d62 # macro
regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX = 1 # macro
regRLC_GFX_IH_CLIENT_OTHER_STAT = 0x4d63 # macro
regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX = 1 # macro
regRLC_SPM_GLOBAL_DELAY_IND_ADDR = 0x4d64 # macro
regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX = 1 # macro
regRLC_SPM_GLOBAL_DELAY_IND_DATA = 0x4d65 # macro
regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX = 1 # macro
regRLC_SPM_SE_DELAY_IND_ADDR = 0x4d66 # macro
regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX = 1 # macro
regRLC_SPM_SE_DELAY_IND_DATA = 0x4d67 # macro
regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX = 1 # macro
regRLC_LX6_CNTL = 0x4d80 # macro
regRLC_LX6_CNTL_BASE_IDX = 1 # macro
regRLC_XT_CORE_STATUS = 0x4dd4 # macro
regRLC_XT_CORE_STATUS_BASE_IDX = 1 # macro
regRLC_XT_CORE_INTERRUPT = 0x4dd5 # macro
regRLC_XT_CORE_INTERRUPT_BASE_IDX = 1 # macro
regRLC_XT_CORE_FAULT_INFO = 0x4dd6 # macro
regRLC_XT_CORE_FAULT_INFO_BASE_IDX = 1 # macro
regRLC_XT_CORE_ALT_RESET_VEC = 0x4dd7 # macro
regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX = 1 # macro
regRLC_XT_CORE_RESERVED = 0x4dd8 # macro
regRLC_XT_CORE_RESERVED_BASE_IDX = 1 # macro
regRLC_XT_INT_VEC_FORCE = 0x4dd9 # macro
regRLC_XT_INT_VEC_FORCE_BASE_IDX = 1 # macro
regRLC_XT_INT_VEC_CLEAR = 0x4dda # macro
regRLC_XT_INT_VEC_CLEAR_BASE_IDX = 1 # macro
regRLC_XT_INT_VEC_MUX_SEL = 0x4ddb # macro
regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX = 1 # macro
regRLC_XT_INT_VEC_MUX_INT_SEL = 0x4ddc # macro
regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX = 1 # macro
regRLC_GPU_CLOCK_COUNT_SPM_LSB = 0x4de4 # macro
regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX = 1 # macro
regRLC_GPU_CLOCK_COUNT_SPM_MSB = 0x4de5 # macro
regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX = 1 # macro
regRLC_SPM_THREAD_TRACE_CTRL = 0x4de6 # macro
regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro
regRLC_SPP_CAM_ADDR = 0x4de8 # macro
regRLC_SPP_CAM_ADDR_BASE_IDX = 1 # macro
regRLC_SPP_CAM_DATA = 0x4de9 # macro
regRLC_SPP_CAM_DATA_BASE_IDX = 1 # macro
regRLC_SPP_CAM_EXT_ADDR = 0x4dea # macro
regRLC_SPP_CAM_EXT_ADDR_BASE_IDX = 1 # macro
regRLC_SPP_CAM_EXT_DATA = 0x4deb # macro
regRLC_SPP_CAM_EXT_DATA_BASE_IDX = 1 # macro
regRLC_XT_DOORBELL_RANGE = 0x4df5 # macro
regRLC_XT_DOORBELL_RANGE_BASE_IDX = 1 # macro
regRLC_XT_DOORBELL_CNTL = 0x4df6 # macro
regRLC_XT_DOORBELL_CNTL_BASE_IDX = 1 # macro
regRLC_XT_DOORBELL_STAT = 0x4df7 # macro
regRLC_XT_DOORBELL_STAT_BASE_IDX = 1 # macro
regRLC_XT_DOORBELL_0_DATA_LO = 0x4df8 # macro
regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro
regRLC_XT_DOORBELL_0_DATA_HI = 0x4df9 # macro
regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro
regRLC_XT_DOORBELL_1_DATA_LO = 0x4dfa # macro
regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro
regRLC_XT_DOORBELL_1_DATA_HI = 0x4dfb # macro
regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro
regRLC_XT_DOORBELL_2_DATA_LO = 0x4dfc # macro
regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro
regRLC_XT_DOORBELL_2_DATA_HI = 0x4dfd # macro
regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro
regRLC_XT_DOORBELL_3_DATA_LO = 0x4dfe # macro
regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro
regRLC_XT_DOORBELL_3_DATA_HI = 0x4dff # macro
regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro
regRLC_MEM_SLP_CNTL = 0x4e00 # macro
regRLC_MEM_SLP_CNTL_BASE_IDX = 1 # macro
regSMU_RLC_RESPONSE = 0x4e01 # macro
regSMU_RLC_RESPONSE_BASE_IDX = 1 # macro
regRLC_RLCV_SAFE_MODE = 0x4e02 # macro
regRLC_RLCV_SAFE_MODE_BASE_IDX = 1 # macro
regRLC_SMU_SAFE_MODE = 0x4e03 # macro
regRLC_SMU_SAFE_MODE_BASE_IDX = 1 # macro
regRLC_RLCV_COMMAND = 0x4e04 # macro
regRLC_RLCV_COMMAND_BASE_IDX = 1 # macro
regRLC_SMU_MESSAGE = 0x4e05 # macro
regRLC_SMU_MESSAGE_BASE_IDX = 1 # macro
regRLC_SMU_MESSAGE_1 = 0x4e06 # macro
regRLC_SMU_MESSAGE_1_BASE_IDX = 1 # macro
regRLC_SMU_MESSAGE_2 = 0x4e07 # macro
regRLC_SMU_MESSAGE_2_BASE_IDX = 1 # macro
regRLC_SRM_GPM_COMMAND = 0x4e08 # macro
regRLC_SRM_GPM_COMMAND_BASE_IDX = 1 # macro
regRLC_SRM_GPM_ABORT = 0x4e09 # macro
regRLC_SRM_GPM_ABORT_BASE_IDX = 1 # macro
regRLC_SMU_COMMAND = 0x4e0a # macro
regRLC_SMU_COMMAND_BASE_IDX = 1 # macro
regRLC_SMU_ARGUMENT_1 = 0x4e0b # macro
regRLC_SMU_ARGUMENT_1_BASE_IDX = 1 # macro
regRLC_SMU_ARGUMENT_2 = 0x4e0c # macro
regRLC_SMU_ARGUMENT_2_BASE_IDX = 1 # macro
regRLC_SMU_ARGUMENT_3 = 0x4e0d # macro
regRLC_SMU_ARGUMENT_3_BASE_IDX = 1 # macro
regRLC_SMU_ARGUMENT_4 = 0x4e0e # macro
regRLC_SMU_ARGUMENT_4_BASE_IDX = 1 # macro
regRLC_SMU_ARGUMENT_5 = 0x4e0f # macro
regRLC_SMU_ARGUMENT_5_BASE_IDX = 1 # macro
regRLC_IMU_BOOTLOAD_ADDR_HI = 0x4e10 # macro
regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX = 1 # macro
regRLC_IMU_BOOTLOAD_ADDR_LO = 0x4e11 # macro
regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX = 1 # macro
regRLC_IMU_BOOTLOAD_SIZE = 0x4e12 # macro
regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX = 1 # macro
regRLC_IMU_MISC = 0x4e16 # macro
regRLC_IMU_MISC_BASE_IDX = 1 # macro
regRLC_IMU_RESET_VECTOR = 0x4e17 # macro
regRLC_IMU_RESET_VECTOR_BASE_IDX = 1 # macro
regRLC_RLCS_DEC_START = 0x4e60 # macro
regRLC_RLCS_DEC_START_BASE_IDX = 1 # macro
regRLC_RLCS_DEC_DUMP_ADDR = 0x4e61 # macro
regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX = 1 # macro
regRLC_RLCS_EXCEPTION_REG_1 = 0x4e62 # macro
regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX = 1 # macro
regRLC_RLCS_EXCEPTION_REG_2 = 0x4e63 # macro
regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX = 1 # macro
regRLC_RLCS_EXCEPTION_REG_3 = 0x4e64 # macro
regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX = 1 # macro
regRLC_RLCS_EXCEPTION_REG_4 = 0x4e65 # macro
regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX = 1 # macro
regRLC_RLCS_CGCG_REQUEST = 0x4e66 # macro
regRLC_RLCS_CGCG_REQUEST_BASE_IDX = 1 # macro
regRLC_RLCS_CGCG_STATUS = 0x4e67 # macro
regRLC_RLCS_CGCG_STATUS_BASE_IDX = 1 # macro
regRLC_RLCS_SOC_DS_CNTL = 0x4e68 # macro
regRLC_RLCS_SOC_DS_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_GFX_DS_CNTL = 0x4e69 # macro
regRLC_RLCS_GFX_DS_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL = 0x4e6a # macro
regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX = 1 # macro
regRLC_GPM_STAT = 0x4e6b # macro
regRLC_GPM_STAT_BASE_IDX = 1 # macro
regRLC_RLCS_GPM_STAT = 0x4e6b # macro
regRLC_RLCS_GPM_STAT_BASE_IDX = 1 # macro
regRLC_RLCS_ABORTED_PD_SEQUENCE = 0x4e6c # macro
regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX = 1 # macro
regRLC_RLCS_DIDT_FORCE_STALL = 0x4e6d # macro
regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX = 1 # macro
regRLC_RLCS_IOV_CMD_STATUS = 0x4e6e # macro
regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX = 1 # macro
regRLC_RLCS_IOV_CNTX_LOC_SIZE = 0x4e6f # macro
regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX = 1 # macro
regRLC_RLCS_IOV_SCH_BLOCK = 0x4e70 # macro
regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX = 1 # macro
regRLC_RLCS_IOV_VM_BUSY_STATUS = 0x4e71 # macro
regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro
regRLC_RLCS_GPM_STAT_2 = 0x4e72 # macro
regRLC_RLCS_GPM_STAT_2_BASE_IDX = 1 # macro
regRLC_RLCS_GRBM_SOFT_RESET = 0x4e73 # macro
regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX = 1 # macro
regRLC_RLCS_PG_CHANGE_STATUS = 0x4e74 # macro
regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX = 1 # macro
regRLC_RLCS_PG_CHANGE_READ = 0x4e75 # macro
regRLC_RLCS_PG_CHANGE_READ_BASE_IDX = 1 # macro
regRLC_RLCS_IH_SEMAPHORE = 0x4e76 # macro
regRLC_RLCS_IH_SEMAPHORE_BASE_IDX = 1 # macro
regRLC_RLCS_IH_COOKIE_SEMAPHORE = 0x4e77 # macro
regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX = 1 # macro
regRLC_RLCS_WGP_STATUS = 0x4e78 # macro
regRLC_RLCS_WGP_STATUS_BASE_IDX = 1 # macro
regRLC_RLCS_WGP_READ = 0x4e79 # macro
regRLC_RLCS_WGP_READ_BASE_IDX = 1 # macro
regRLC_RLCS_CP_INT_CTRL_1 = 0x4e7a # macro
regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX = 1 # macro
regRLC_RLCS_CP_INT_CTRL_2 = 0x4e7b # macro
regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX = 1 # macro
regRLC_RLCS_CP_INT_INFO_1 = 0x4e7c # macro
regRLC_RLCS_CP_INT_INFO_1_BASE_IDX = 1 # macro
regRLC_RLCS_CP_INT_INFO_2 = 0x4e7d # macro
regRLC_RLCS_CP_INT_INFO_2_BASE_IDX = 1 # macro
regRLC_RLCS_SPM_INT_CTRL = 0x4e7e # macro
regRLC_RLCS_SPM_INT_CTRL_BASE_IDX = 1 # macro
regRLC_RLCS_SPM_INT_INFO_1 = 0x4e7f # macro
regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX = 1 # macro
regRLC_RLCS_SPM_INT_INFO_2 = 0x4e80 # macro
regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX = 1 # macro
regRLC_RLCS_DSM_TRIG = 0x4e81 # macro
regRLC_RLCS_DSM_TRIG_BASE_IDX = 1 # macro
regRLC_RLCS_BOOTLOAD_STATUS = 0x4e82 # macro
regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX = 1 # macro
regRLC_RLCS_POWER_BRAKE_CNTL = 0x4e83 # macro
regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_POWER_BRAKE_CNTL_TH1 = 0x4e84 # macro
regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX = 1 # macro
regRLC_RLCS_GRBM_IDLE_BUSY_STAT = 0x4e85 # macro
regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX = 1 # macro
regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL = 0x4e86 # macro
regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_CMP_IDLE_CNTL = 0x4e87 # macro
regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_0 = 0x4e88 # macro
regRLC_RLCS_GENERAL_0_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_1 = 0x4e89 # macro
regRLC_RLCS_GENERAL_1_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_2 = 0x4e8a # macro
regRLC_RLCS_GENERAL_2_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_3 = 0x4e8b # macro
regRLC_RLCS_GENERAL_3_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_4 = 0x4e8c # macro
regRLC_RLCS_GENERAL_4_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_5 = 0x4e8d # macro
regRLC_RLCS_GENERAL_5_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_6 = 0x4e8e # macro
regRLC_RLCS_GENERAL_6_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_7 = 0x4e8f # macro
regRLC_RLCS_GENERAL_7_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_8 = 0x4e90 # macro
regRLC_RLCS_GENERAL_8_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_9 = 0x4e91 # macro
regRLC_RLCS_GENERAL_9_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_10 = 0x4e92 # macro
regRLC_RLCS_GENERAL_10_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_11 = 0x4e93 # macro
regRLC_RLCS_GENERAL_11_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_12 = 0x4e94 # macro
regRLC_RLCS_GENERAL_12_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_13 = 0x4e95 # macro
regRLC_RLCS_GENERAL_13_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_14 = 0x4e96 # macro
regRLC_RLCS_GENERAL_14_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_15 = 0x4e97 # macro
regRLC_RLCS_GENERAL_15_BASE_IDX = 1 # macro
regRLC_RLCS_GENERAL_16 = 0x4e98 # macro
regRLC_RLCS_GENERAL_16_BASE_IDX = 1 # macro
regRLC_RLCS_AUXILIARY_REG_1 = 0x4ec5 # macro
regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX = 1 # macro
regRLC_RLCS_AUXILIARY_REG_2 = 0x4ec6 # macro
regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX = 1 # macro
regRLC_RLCS_AUXILIARY_REG_3 = 0x4ec7 # macro
regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX = 1 # macro
regRLC_RLCS_AUXILIARY_REG_4 = 0x4ec8 # macro
regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX = 1 # macro
regRLC_RLCS_SPM_SQTT_MODE = 0x4ec9 # macro
regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX = 1 # macro
regRLC_RLCS_CP_DMA_SRCID_OVER = 0x4eca # macro
regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX = 1 # macro
regRLC_RLCS_BOOTLOAD_ID_STATUS1 = 0x4ecb # macro
regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX = 1 # macro
regRLC_RLCS_BOOTLOAD_ID_STATUS2 = 0x4ecc # macro
regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_VIDCHG_CNTL = 0x4ecd # macro
regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_EDC_INT_CNTL = 0x4ece # macro
regRLC_RLCS_EDC_INT_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_KMD_LOG_CNTL1 = 0x4ecf # macro
regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX = 1 # macro
regRLC_RLCS_KMD_LOG_CNTL2 = 0x4ed0 # macro
regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX = 1 # macro
regRLC_RLCS_GPM_LEGACY_INT_STAT = 0x4ed1 # macro
regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro
regRLC_RLCS_GPM_LEGACY_INT_DISABLE = 0x4ed2 # macro
regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro
regRLC_RLCS_SRM_SRCID_CNTL = 0x4ed3 # macro
regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_GCR_DATA_0 = 0x4ed4 # macro
regRLC_RLCS_GCR_DATA_0_BASE_IDX = 1 # macro
regRLC_RLCS_GCR_DATA_1 = 0x4ed5 # macro
regRLC_RLCS_GCR_DATA_1_BASE_IDX = 1 # macro
regRLC_RLCS_GCR_DATA_2 = 0x4ed6 # macro
regRLC_RLCS_GCR_DATA_2_BASE_IDX = 1 # macro
regRLC_RLCS_GCR_DATA_3 = 0x4ed7 # macro
regRLC_RLCS_GCR_DATA_3_BASE_IDX = 1 # macro
regRLC_RLCS_GCR_STATUS = 0x4ed8 # macro
regRLC_RLCS_GCR_STATUS_BASE_IDX = 1 # macro
regRLC_RLCS_PERFMON_CLK_CNTL_UCODE = 0x4ed9 # macro
regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX = 1 # macro
regRLC_RLCS_UTCL2_CNTL = 0x4eda # macro
regRLC_RLCS_UTCL2_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RLC_MSG_DATA0 = 0x4edb # macro
regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RLC_MSG_DATA1 = 0x4edc # macro
regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RLC_MSG_DATA2 = 0x4edd # macro
regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RLC_MSG_DATA3 = 0x4ede # macro
regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RLC_MSG_DATA4 = 0x4edf # macro
regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RLC_MSG_CONTROL = 0x4ee0 # macro
regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RLC_MSG_CNTL = 0x4ee1 # macro
regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_RLC_IMU_MSG_DATA0 = 0x4ee2 # macro
regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX = 1 # macro
regRLC_RLCS_RLC_IMU_MSG_CONTROL = 0x4ee3 # macro
regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX = 1 # macro
regRLC_RLCS_RLC_IMU_MSG_CNTL = 0x4ee4 # macro
regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0 = 0x4ee5 # macro
regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1 = 0x4ee6 # macro
regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RLC_MUTEX_CNTL = 0x4ee7 # macro
regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RLC_STATUS = 0x4ee8 # macro
regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX = 1 # macro
regRLC_RLCS_RLC_IMU_STATUS = 0x4ee9 # macro
regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RAM_DATA_1 = 0x4eea # macro
regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RAM_ADDR_1_LSB = 0x4eeb # macro
regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RAM_ADDR_1_MSB = 0x4eec # macro
regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RAM_DATA_0 = 0x4eed # macro
regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RAM_ADDR_0_LSB = 0x4eee # macro
regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RAM_ADDR_0_MSB = 0x4eef # macro
regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_RAM_CNTL = 0x4ef0 # macro
regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_IMU_GFX_DOORBELL_FENCE = 0x4ef1 # macro
regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX = 1 # macro
regRLC_RLCS_SDMA_INT_CNTL_1 = 0x4ef3 # macro
regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX = 1 # macro
regRLC_RLCS_SDMA_INT_CNTL_2 = 0x4ef4 # macro
regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX = 1 # macro
regRLC_RLCS_SDMA_INT_STAT = 0x4ef5 # macro
regRLC_RLCS_SDMA_INT_STAT_BASE_IDX = 1 # macro
regRLC_RLCS_SDMA_INT_INFO = 0x4ef6 # macro
regRLC_RLCS_SDMA_INT_INFO_BASE_IDX = 1 # macro
regRLC_RLCS_PMM_CGCG_CNTL = 0x4ef7 # macro
regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_GFX_MEM_POWER_CTRL_LO = 0x4ef8 # macro
regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX = 1 # macro
regRLC_RLCS_GFX_RM_CNTL = 0x4efa # macro
regRLC_RLCS_GFX_RM_CNTL_BASE_IDX = 1 # macro
regRLC_RLCS_DEC_END = 0x4fff # macro
regRLC_RLCS_DEC_END_BASE_IDX = 1 # macro
regRLC_SAFE_MODE = 0x0980 # macro
regRLC_SAFE_MODE_BASE_IDX = 1 # macro
regRLC_SPM_SAMPLE_CNT = 0x0981 # macro
regRLC_SPM_SAMPLE_CNT_BASE_IDX = 1 # macro
regRLC_SPM_MC_CNTL = 0x0982 # macro
regRLC_SPM_MC_CNTL_BASE_IDX = 1 # macro
regRLC_SPM_INT_CNTL = 0x0983 # macro
regRLC_SPM_INT_CNTL_BASE_IDX = 1 # macro
regRLC_SPM_INT_STATUS = 0x0984 # macro
regRLC_SPM_INT_STATUS_BASE_IDX = 1 # macro
regRLC_SPM_INT_INFO_1 = 0x0985 # macro
regRLC_SPM_INT_INFO_1_BASE_IDX = 1 # macro
regRLC_SPM_INT_INFO_2 = 0x0986 # macro
regRLC_SPM_INT_INFO_2_BASE_IDX = 1 # macro
regRLC_CSIB_ADDR_LO = 0x0987 # macro
regRLC_CSIB_ADDR_LO_BASE_IDX = 1 # macro
regRLC_CSIB_ADDR_HI = 0x0988 # macro
regRLC_CSIB_ADDR_HI_BASE_IDX = 1 # macro
regRLC_CSIB_LENGTH = 0x0989 # macro
regRLC_CSIB_LENGTH_BASE_IDX = 1 # macro
regRLC_CP_SCHEDULERS = 0x098a # macro
regRLC_CP_SCHEDULERS_BASE_IDX = 1 # macro
regRLC_CP_EOF_INT = 0x098b # macro
regRLC_CP_EOF_INT_BASE_IDX = 1 # macro
regRLC_CP_EOF_INT_CNT = 0x098c # macro
regRLC_CP_EOF_INT_CNT_BASE_IDX = 1 # macro
regRLC_SPARE_INT_0 = 0x098d # macro
regRLC_SPARE_INT_0_BASE_IDX = 1 # macro
regRLC_SPARE_INT_1 = 0x098e # macro
regRLC_SPARE_INT_1_BASE_IDX = 1 # macro
regRLC_SPARE_INT_2 = 0x098f # macro
regRLC_SPARE_INT_2_BASE_IDX = 1 # macro
regRLC_PACE_SPARE_INT = 0x0990 # macro
regRLC_PACE_SPARE_INT_BASE_IDX = 1 # macro
regRLC_PACE_SPARE_INT_1 = 0x0991 # macro
regRLC_PACE_SPARE_INT_1_BASE_IDX = 1 # macro
regRLC_RLCV_SPARE_INT_1 = 0x0992 # macro
regRLC_RLCV_SPARE_INT_1_BASE_IDX = 1 # macro
regCGTS_TCC_DISABLE = 0x5006 # macro
regCGTS_TCC_DISABLE_BASE_IDX = 1 # macro
regCGTT_GS_NGG_CLK_CTRL = 0x5087 # macro
regCGTT_GS_NGG_CLK_CTRL_BASE_IDX = 1 # macro
regCGTT_PA_CLK_CTRL = 0x5088 # macro
regCGTT_PA_CLK_CTRL_BASE_IDX = 1 # macro
regCGTT_SC_CLK_CTRL0 = 0x5089 # macro
regCGTT_SC_CLK_CTRL0_BASE_IDX = 1 # macro
regCGTT_SC_CLK_CTRL1 = 0x508a # macro
regCGTT_SC_CLK_CTRL1_BASE_IDX = 1 # macro
regCGTT_SC_CLK_CTRL2 = 0x508b # macro
regCGTT_SC_CLK_CTRL2_BASE_IDX = 1 # macro
regCGTT_SQG_CLK_CTRL = 0x508d # macro
regCGTT_SQG_CLK_CTRL_BASE_IDX = 1 # macro
regSQ_ALU_CLK_CTRL = 0x508e # macro
regSQ_ALU_CLK_CTRL_BASE_IDX = 1 # macro
regSQ_TEX_CLK_CTRL = 0x508f # macro
regSQ_TEX_CLK_CTRL_BASE_IDX = 1 # macro
regSQ_LDS_CLK_CTRL = 0x5090 # macro
regSQ_LDS_CLK_CTRL_BASE_IDX = 1 # macro
regICG_SP_CLK_CTRL = 0x5093 # macro
regICG_SP_CLK_CTRL_BASE_IDX = 1 # macro
regTA_CGTT_CTRL = 0x509d # macro
regTA_CGTT_CTRL_BASE_IDX = 1 # macro
regDB_CGTT_CLK_CTRL_0 = 0x50a4 # macro
regDB_CGTT_CLK_CTRL_0_BASE_IDX = 1 # macro
regCB_CGTT_SCLK_CTRL = 0x50a8 # macro
regCB_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro
regCGTT_CP_CLK_CTRL = 0x50b0 # macro
regCGTT_CP_CLK_CTRL_BASE_IDX = 1 # macro
regCGTT_CPF_CLK_CTRL = 0x50b1 # macro
regCGTT_CPF_CLK_CTRL_BASE_IDX = 1 # macro
regCGTT_CPC_CLK_CTRL = 0x50b2 # macro
regCGTT_CPC_CLK_CTRL_BASE_IDX = 1 # macro
regCGTT_RLC_CLK_CTRL = 0x50b5 # macro
regCGTT_RLC_CLK_CTRL_BASE_IDX = 1 # macro
regCGTT_SC_CLK_CTRL3 = 0x50bc # macro
regCGTT_SC_CLK_CTRL3_BASE_IDX = 1 # macro
regCGTT_SC_CLK_CTRL4 = 0x50bd # macro
regCGTT_SC_CLK_CTRL4_BASE_IDX = 1 # macro
regGCEA_ICG_CTRL = 0x50c4 # macro
regGCEA_ICG_CTRL_BASE_IDX = 1 # macro
regGL1I_GL1R_MGCG_OVERRIDE = 0x50e4 # macro
regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX = 1 # macro
regGL1H_ICG_CTRL = 0x50e8 # macro
regGL1H_ICG_CTRL_BASE_IDX = 1 # macro
regCHI_CHR_MGCG_OVERRIDE = 0x50e9 # macro
regCHI_CHR_MGCG_OVERRIDE_BASE_IDX = 1 # macro
regICG_GL1C_CLK_CTRL = 0x50ec # macro
regICG_GL1C_CLK_CTRL_BASE_IDX = 1 # macro
regICG_GL1A_CTRL = 0x50f0 # macro
regICG_GL1A_CTRL_BASE_IDX = 1 # macro
regICG_CHA_CTRL = 0x50f1 # macro
regICG_CHA_CTRL_BASE_IDX = 1 # macro
regGUS_ICG_CTRL = 0x50f4 # macro
regGUS_ICG_CTRL_BASE_IDX = 1 # macro
regCGTT_PH_CLK_CTRL0 = 0x50f8 # macro
regCGTT_PH_CLK_CTRL0_BASE_IDX = 1 # macro
regCGTT_PH_CLK_CTRL1 = 0x50f9 # macro
regCGTT_PH_CLK_CTRL1_BASE_IDX = 1 # macro
regCGTT_PH_CLK_CTRL2 = 0x50fa # macro
regCGTT_PH_CLK_CTRL2_BASE_IDX = 1 # macro
regCGTT_PH_CLK_CTRL3 = 0x50fb # macro
regCGTT_PH_CLK_CTRL3_BASE_IDX = 1 # macro
regGFX_ICG_GL2C_CTRL = 0x50fc # macro
regGFX_ICG_GL2C_CTRL_BASE_IDX = 1 # macro
regGFX_ICG_GL2C_CTRL1 = 0x50fd # macro
regGFX_ICG_GL2C_CTRL1_BASE_IDX = 1 # macro
regICG_LDS_CLK_CTRL = 0x5114 # macro
regICG_LDS_CLK_CTRL_BASE_IDX = 1 # macro
regICG_CHC_CLK_CTRL = 0x5140 # macro
regICG_CHC_CLK_CTRL_BASE_IDX = 1 # macro
regICG_CHCG_CLK_CTRL = 0x5144 # macro
regICG_CHCG_CLK_CTRL_BASE_IDX = 1 # macro
regGFX_PIPE_PRIORITY = 0x587f # macro
regGFX_PIPE_PRIORITY_BASE_IDX = 1 # macro
regGRBM_GFX_INDEX_SR_SELECT = 0x5a00 # macro
regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX = 1 # macro
regGRBM_GFX_INDEX_SR_DATA = 0x5a01 # macro
regGRBM_GFX_INDEX_SR_DATA_BASE_IDX = 1 # macro
regGRBM_GFX_CNTL_SR_SELECT = 0x5a02 # macro
regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX = 1 # macro
regGRBM_GFX_CNTL_SR_DATA = 0x5a03 # macro
regGRBM_GFX_CNTL_SR_DATA_BASE_IDX = 1 # macro
regGC_IH_COOKIE_0_PTR = 0x5a07 # macro
regGC_IH_COOKIE_0_PTR_BASE_IDX = 1 # macro
regGRBM_SE_REMAP_CNTL = 0x5a08 # macro
regGRBM_SE_REMAP_CNTL_BASE_IDX = 1 # macro
regRLC_GPU_IOV_VF_ENABLE = 0x5b00 # macro
regRLC_GPU_IOV_VF_ENABLE_BASE_IDX = 1 # macro
regRLC_GPU_IOV_CFG_REG6 = 0x5b06 # macro
regRLC_GPU_IOV_CFG_REG6_BASE_IDX = 1 # macro
regRLC_SDMA0_STATUS = 0x5b18 # macro
regRLC_SDMA0_STATUS_BASE_IDX = 1 # macro
regRLC_SDMA1_STATUS = 0x5b19 # macro
regRLC_SDMA1_STATUS_BASE_IDX = 1 # macro
regRLC_SDMA2_STATUS = 0x5b1a # macro
regRLC_SDMA2_STATUS_BASE_IDX = 1 # macro
regRLC_SDMA3_STATUS = 0x5b1b # macro
regRLC_SDMA3_STATUS_BASE_IDX = 1 # macro
regRLC_SDMA0_BUSY_STATUS = 0x5b1c # macro
regRLC_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro
regRLC_SDMA1_BUSY_STATUS = 0x5b1d # macro
regRLC_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro
regRLC_SDMA2_BUSY_STATUS = 0x5b1e # macro
regRLC_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro
regRLC_SDMA3_BUSY_STATUS = 0x5b1f # macro
regRLC_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_CFG_REG8 = 0x5b20 # macro
regRLC_GPU_IOV_CFG_REG8_BASE_IDX = 1 # macro
regRLC_RLCV_TIMER_INT_0 = 0x5b25 # macro
regRLC_RLCV_TIMER_INT_0_BASE_IDX = 1 # macro
regRLC_RLCV_TIMER_INT_1 = 0x5b26 # macro
regRLC_RLCV_TIMER_INT_1_BASE_IDX = 1 # macro
regRLC_RLCV_TIMER_CTRL = 0x5b27 # macro
regRLC_RLCV_TIMER_CTRL_BASE_IDX = 1 # macro
regRLC_RLCV_TIMER_STAT = 0x5b28 # macro
regRLC_RLCV_TIMER_STAT_BASE_IDX = 1 # macro
regRLC_GPU_IOV_VF_DOORBELL_STATUS = 0x5b2a # macro
regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET = 0x5b2b # macro
regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX = 1 # macro
regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR = 0x5b2c # macro
regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX = 1 # macro
regRLC_GPU_IOV_VF_MASK = 0x5b2d # macro
regRLC_GPU_IOV_VF_MASK_BASE_IDX = 1 # macro
regRLC_HYP_SEMAPHORE_0 = 0x5b2e # macro
regRLC_HYP_SEMAPHORE_0_BASE_IDX = 1 # macro
regRLC_HYP_SEMAPHORE_1 = 0x5b2f # macro
regRLC_HYP_SEMAPHORE_1_BASE_IDX = 1 # macro
regRLC_BUSY_CLK_CNTL = 0x5b30 # macro
regRLC_BUSY_CLK_CNTL_BASE_IDX = 1 # macro
regRLC_CLK_CNTL = 0x5b31 # macro
regRLC_CLK_CNTL_BASE_IDX = 1 # macro
regRLC_PACE_TIMER_STAT = 0x5b33 # macro
regRLC_PACE_TIMER_STAT_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SCH_BLOCK = 0x5b34 # macro
regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX = 1 # macro
regRLC_GPU_IOV_CFG_REG1 = 0x5b35 # macro
regRLC_GPU_IOV_CFG_REG1_BASE_IDX = 1 # macro
regRLC_GPU_IOV_CFG_REG2 = 0x5b36 # macro
regRLC_GPU_IOV_CFG_REG2_BASE_IDX = 1 # macro
regRLC_GPU_IOV_VM_BUSY_STATUS = 0x5b37 # macro
regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SCH_0 = 0x5b38 # macro
regRLC_GPU_IOV_SCH_0_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SCH_3 = 0x5b3a # macro
regRLC_GPU_IOV_SCH_3_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SCH_1 = 0x5b3b # macro
regRLC_GPU_IOV_SCH_1_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SCH_2 = 0x5b3c # macro
regRLC_GPU_IOV_SCH_2_BASE_IDX = 1 # macro
regRLC_PACE_INT_FORCE = 0x5b3d # macro
regRLC_PACE_INT_FORCE_BASE_IDX = 1 # macro
regRLC_PACE_INT_CLEAR = 0x5b3e # macro
regRLC_PACE_INT_CLEAR_BASE_IDX = 1 # macro
regRLC_GPU_IOV_INT_STAT = 0x5b3f # macro
regRLC_GPU_IOV_INT_STAT_BASE_IDX = 1 # macro
regRLC_IH_COOKIE = 0x5b41 # macro
regRLC_IH_COOKIE_BASE_IDX = 1 # macro
regRLC_IH_COOKIE_CNTL = 0x5b42 # macro
regRLC_IH_COOKIE_CNTL_BASE_IDX = 1 # macro
regRLC_HYP_RLCG_UCODE_CHKSUM = 0x5b43 # macro
regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX = 1 # macro
regRLC_HYP_RLCP_UCODE_CHKSUM = 0x5b44 # macro
regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX = 1 # macro
regRLC_HYP_RLCV_UCODE_CHKSUM = 0x5b45 # macro
regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX = 1 # macro
regRLC_GPU_IOV_F32_CNTL = 0x5b46 # macro
regRLC_GPU_IOV_F32_CNTL_BASE_IDX = 1 # macro
regRLC_GPU_IOV_F32_RESET = 0x5b47 # macro
regRLC_GPU_IOV_F32_RESET_BASE_IDX = 1 # macro
regRLC_GPU_IOV_UCODE_ADDR = 0x5b48 # macro
regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX = 1 # macro
regRLC_GPU_IOV_UCODE_DATA = 0x5b49 # macro
regRLC_GPU_IOV_UCODE_DATA_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SMU_RESPONSE = 0x5b4a # macro
regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX = 1 # macro
regRLC_GPU_IOV_F32_INVALIDATE_CACHE = 0x5b4b # macro
regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX = 1 # macro
regRLC_GPU_IOV_RLC_RESPONSE = 0x5b4d # macro
regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX = 1 # macro
regRLC_GPU_IOV_INT_DISABLE = 0x5b4e # macro
regRLC_GPU_IOV_INT_DISABLE_BASE_IDX = 1 # macro
regRLC_GPU_IOV_INT_FORCE = 0x5b4f # macro
regRLC_GPU_IOV_INT_FORCE_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SCRATCH_ADDR = 0x5b50 # macro
regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SCRATCH_DATA = 0x5b51 # macro
regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX = 1 # macro
regRLC_HYP_SEMAPHORE_2 = 0x5b52 # macro
regRLC_HYP_SEMAPHORE_2_BASE_IDX = 1 # macro
regRLC_HYP_SEMAPHORE_3 = 0x5b53 # macro
regRLC_HYP_SEMAPHORE_3_BASE_IDX = 1 # macro
regRLC_GPM_UCODE_ADDR = 0x5b60 # macro
regRLC_GPM_UCODE_ADDR_BASE_IDX = 1 # macro
regRLC_GPM_UCODE_DATA = 0x5b61 # macro
regRLC_GPM_UCODE_DATA_BASE_IDX = 1 # macro
regRLC_GPM_IRAM_ADDR = 0x5b62 # macro
regRLC_GPM_IRAM_ADDR_BASE_IDX = 1 # macro
regRLC_GPM_IRAM_DATA = 0x5b63 # macro
regRLC_GPM_IRAM_DATA_BASE_IDX = 1 # macro
regRLC_RLCP_IRAM_ADDR = 0x5b64 # macro
regRLC_RLCP_IRAM_ADDR_BASE_IDX = 1 # macro
regRLC_RLCP_IRAM_DATA = 0x5b65 # macro
regRLC_RLCP_IRAM_DATA_BASE_IDX = 1 # macro
regRLC_RLCV_IRAM_ADDR = 0x5b66 # macro
regRLC_RLCV_IRAM_ADDR_BASE_IDX = 1 # macro
regRLC_RLCV_IRAM_DATA = 0x5b67 # macro
regRLC_RLCV_IRAM_DATA_BASE_IDX = 1 # macro
regRLC_LX6_DRAM_ADDR = 0x5b68 # macro
regRLC_LX6_DRAM_ADDR_BASE_IDX = 1 # macro
regRLC_LX6_DRAM_DATA = 0x5b69 # macro
regRLC_LX6_DRAM_DATA_BASE_IDX = 1 # macro
regRLC_LX6_IRAM_ADDR = 0x5b6a # macro
regRLC_LX6_IRAM_ADDR_BASE_IDX = 1 # macro
regRLC_LX6_IRAM_DATA = 0x5b6b # macro
regRLC_LX6_IRAM_DATA_BASE_IDX = 1 # macro
regRLC_PACE_UCODE_ADDR = 0x5b6c # macro
regRLC_PACE_UCODE_ADDR_BASE_IDX = 1 # macro
regRLC_PACE_UCODE_DATA = 0x5b6d # macro
regRLC_PACE_UCODE_DATA_BASE_IDX = 1 # macro
regRLC_GPM_SCRATCH_ADDR = 0x5b6e # macro
regRLC_GPM_SCRATCH_ADDR_BASE_IDX = 1 # macro
regRLC_GPM_SCRATCH_DATA = 0x5b6f # macro
regRLC_GPM_SCRATCH_DATA_BASE_IDX = 1 # macro
regRLC_SRM_DRAM_ADDR = 0x5b71 # macro
regRLC_SRM_DRAM_ADDR_BASE_IDX = 1 # macro
regRLC_SRM_DRAM_DATA = 0x5b72 # macro
regRLC_SRM_DRAM_DATA_BASE_IDX = 1 # macro
regRLC_SRM_ARAM_ADDR = 0x5b73 # macro
regRLC_SRM_ARAM_ADDR_BASE_IDX = 1 # macro
regRLC_SRM_ARAM_DATA = 0x5b74 # macro
regRLC_SRM_ARAM_DATA_BASE_IDX = 1 # macro
regRLC_PACE_SCRATCH_ADDR = 0x5b77 # macro
regRLC_PACE_SCRATCH_ADDR_BASE_IDX = 1 # macro
regRLC_PACE_SCRATCH_DATA = 0x5b78 # macro
regRLC_PACE_SCRATCH_DATA_BASE_IDX = 1 # macro
regRLC_GTS_OFFSET_LSB = 0x5b79 # macro
regRLC_GTS_OFFSET_LSB_BASE_IDX = 1 # macro
regRLC_GTS_OFFSET_MSB = 0x5b7a # macro
regRLC_GTS_OFFSET_MSB_BASE_IDX = 1 # macro
regGL2_PIPE_STEER_0 = 0x5b80 # macro
regGL2_PIPE_STEER_0_BASE_IDX = 1 # macro
regGL2_PIPE_STEER_1 = 0x5b81 # macro
regGL2_PIPE_STEER_1_BASE_IDX = 1 # macro
regGL2_PIPE_STEER_2 = 0x5b82 # macro
regGL2_PIPE_STEER_2_BASE_IDX = 1 # macro
regGL2_PIPE_STEER_3 = 0x5b83 # macro
regGL2_PIPE_STEER_3_BASE_IDX = 1 # macro
regGL1_PIPE_STEER = 0x5b84 # macro
regGL1_PIPE_STEER_BASE_IDX = 1 # macro
regCH_PIPE_STEER = 0x5b88 # macro
regCH_PIPE_STEER_BASE_IDX = 1 # macro
regGC_USER_SHADER_ARRAY_CONFIG = 0x5b90 # macro
regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX = 1 # macro
regGC_USER_PRIM_CONFIG = 0x5b91 # macro
regGC_USER_PRIM_CONFIG_BASE_IDX = 1 # macro
regGC_USER_SA_UNIT_DISABLE = 0x5b92 # macro
regGC_USER_SA_UNIT_DISABLE_BASE_IDX = 1 # macro
regGC_USER_RB_REDUNDANCY = 0x5b93 # macro
regGC_USER_RB_REDUNDANCY_BASE_IDX = 1 # macro
regGC_USER_RB_BACKEND_DISABLE = 0x5b94 # macro
regGC_USER_RB_BACKEND_DISABLE_BASE_IDX = 1 # macro
regGC_USER_RMI_REDUNDANCY = 0x5b95 # macro
regGC_USER_RMI_REDUNDANCY_BASE_IDX = 1 # macro
regCGTS_USER_TCC_DISABLE = 0x5b96 # macro
regCGTS_USER_TCC_DISABLE_BASE_IDX = 1 # macro
regGC_USER_SHADER_RATE_CONFIG = 0x5b97 # macro
regGC_USER_SHADER_RATE_CONFIG_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA0_STATUS = 0x5bc0 # macro
regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA1_STATUS = 0x5bc1 # macro
regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA2_STATUS = 0x5bc2 # macro
regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA3_STATUS = 0x5bc3 # macro
regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA4_STATUS = 0x5bc4 # macro
regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA5_STATUS = 0x5bc5 # macro
regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA6_STATUS = 0x5bc6 # macro
regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA7_STATUS = 0x5bc7 # macro
regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA0_BUSY_STATUS = 0x5bc8 # macro
regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA1_BUSY_STATUS = 0x5bc9 # macro
regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA2_BUSY_STATUS = 0x5bca # macro
regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA3_BUSY_STATUS = 0x5bcb # macro
regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA4_BUSY_STATUS = 0x5bcc # macro
regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA5_BUSY_STATUS = 0x5bcd # macro
regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA6_BUSY_STATUS = 0x5bce # macro
regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX = 1 # macro
regRLC_GPU_IOV_SDMA7_BUSY_STATUS = 0x5bcf # macro
regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX = 1 # macro
regCP_MES_DM_INDEX_ADDR = 0x5c00 # macro
regCP_MES_DM_INDEX_ADDR_BASE_IDX = 1 # macro
regCP_MES_DM_INDEX_DATA = 0x5c01 # macro
regCP_MES_DM_INDEX_DATA_BASE_IDX = 1 # macro
regCP_MEC_DM_INDEX_ADDR = 0x5c02 # macro
regCP_MEC_DM_INDEX_ADDR_BASE_IDX = 1 # macro
regCP_MEC_DM_INDEX_DATA = 0x5c03 # macro
regCP_MEC_DM_INDEX_DATA_BASE_IDX = 1 # macro
regCP_GFX_RS64_DM_INDEX_ADDR = 0x5c04 # macro
regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX = 1 # macro
regCP_GFX_RS64_DM_INDEX_DATA = 0x5c05 # macro
regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX = 1 # macro
regCPG_PSP_DEBUG = 0x5c10 # macro
regCPG_PSP_DEBUG_BASE_IDX = 1 # macro
regCPC_PSP_DEBUG = 0x5c11 # macro
regCPC_PSP_DEBUG_BASE_IDX = 1 # macro
regGRBM_SEC_CNTL = 0x5e0d # macro
regGRBM_SEC_CNTL_BASE_IDX = 1 # macro
regGRBM_CAM_INDEX = 0x5e10 # macro
regGRBM_CAM_INDEX_BASE_IDX = 1 # macro
regGRBM_HYP_CAM_INDEX = 0x5e10 # macro
regGRBM_HYP_CAM_INDEX_BASE_IDX = 1 # macro
regGRBM_CAM_DATA = 0x5e11 # macro
regGRBM_CAM_DATA_BASE_IDX = 1 # macro
regGRBM_HYP_CAM_DATA = 0x5e11 # macro
regGRBM_HYP_CAM_DATA_BASE_IDX = 1 # macro
regGRBM_CAM_DATA_UPPER = 0x5e12 # macro
regGRBM_CAM_DATA_UPPER_BASE_IDX = 1 # macro
regGRBM_HYP_CAM_DATA_UPPER = 0x5e12 # macro
regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX = 1 # macro
regRLC_FWL_FIRST_VIOL_ADDR = 0x5f26 # macro
regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_0 = 0x4000 # macro
regGFX_IMU_C2PMSG_0_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_1 = 0x4001 # macro
regGFX_IMU_C2PMSG_1_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_2 = 0x4002 # macro
regGFX_IMU_C2PMSG_2_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_3 = 0x4003 # macro
regGFX_IMU_C2PMSG_3_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_4 = 0x4004 # macro
regGFX_IMU_C2PMSG_4_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_5 = 0x4005 # macro
regGFX_IMU_C2PMSG_5_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_6 = 0x4006 # macro
regGFX_IMU_C2PMSG_6_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_7 = 0x4007 # macro
regGFX_IMU_C2PMSG_7_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_8 = 0x4008 # macro
regGFX_IMU_C2PMSG_8_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_9 = 0x4009 # macro
regGFX_IMU_C2PMSG_9_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_10 = 0x400a # macro
regGFX_IMU_C2PMSG_10_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_11 = 0x400b # macro
regGFX_IMU_C2PMSG_11_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_12 = 0x400c # macro
regGFX_IMU_C2PMSG_12_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_13 = 0x400d # macro
regGFX_IMU_C2PMSG_13_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_14 = 0x400e # macro
regGFX_IMU_C2PMSG_14_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_15 = 0x400f # macro
regGFX_IMU_C2PMSG_15_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_16 = 0x4010 # macro
regGFX_IMU_C2PMSG_16_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_17 = 0x4011 # macro
regGFX_IMU_C2PMSG_17_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_18 = 0x4012 # macro
regGFX_IMU_C2PMSG_18_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_19 = 0x4013 # macro
regGFX_IMU_C2PMSG_19_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_20 = 0x4014 # macro
regGFX_IMU_C2PMSG_20_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_21 = 0x4015 # macro
regGFX_IMU_C2PMSG_21_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_22 = 0x4016 # macro
regGFX_IMU_C2PMSG_22_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_23 = 0x4017 # macro
regGFX_IMU_C2PMSG_23_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_24 = 0x4018 # macro
regGFX_IMU_C2PMSG_24_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_25 = 0x4019 # macro
regGFX_IMU_C2PMSG_25_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_26 = 0x401a # macro
regGFX_IMU_C2PMSG_26_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_27 = 0x401b # macro
regGFX_IMU_C2PMSG_27_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_28 = 0x401c # macro
regGFX_IMU_C2PMSG_28_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_29 = 0x401d # macro
regGFX_IMU_C2PMSG_29_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_30 = 0x401e # macro
regGFX_IMU_C2PMSG_30_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_31 = 0x401f # macro
regGFX_IMU_C2PMSG_31_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_32 = 0x4020 # macro
regGFX_IMU_C2PMSG_32_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_33 = 0x4021 # macro
regGFX_IMU_C2PMSG_33_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_34 = 0x4022 # macro
regGFX_IMU_C2PMSG_34_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_35 = 0x4023 # macro
regGFX_IMU_C2PMSG_35_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_36 = 0x4024 # macro
regGFX_IMU_C2PMSG_36_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_37 = 0x4025 # macro
regGFX_IMU_C2PMSG_37_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_38 = 0x4026 # macro
regGFX_IMU_C2PMSG_38_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_39 = 0x4027 # macro
regGFX_IMU_C2PMSG_39_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_40 = 0x4028 # macro
regGFX_IMU_C2PMSG_40_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_41 = 0x4029 # macro
regGFX_IMU_C2PMSG_41_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_42 = 0x402a # macro
regGFX_IMU_C2PMSG_42_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_43 = 0x402b # macro
regGFX_IMU_C2PMSG_43_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_44 = 0x402c # macro
regGFX_IMU_C2PMSG_44_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_45 = 0x402d # macro
regGFX_IMU_C2PMSG_45_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_46 = 0x402e # macro
regGFX_IMU_C2PMSG_46_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_47 = 0x402f # macro
regGFX_IMU_C2PMSG_47_BASE_IDX = 1 # macro
regGFX_IMU_MSG_FLAGS = 0x403f # macro
regGFX_IMU_MSG_FLAGS_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_ACCESS_CTRL0 = 0x4040 # macro
regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX = 1 # macro
regGFX_IMU_C2PMSG_ACCESS_CTRL1 = 0x4041 # macro
regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX = 1 # macro
regGFX_IMU_PWRMGT_IRQ_CTRL = 0x4042 # macro
regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX = 1 # macro
regGFX_IMU_MP1_MUTEX = 0x4043 # macro
regGFX_IMU_MP1_MUTEX_BASE_IDX = 1 # macro
regGFX_IMU_RLC_DATA_4 = 0x4046 # macro
regGFX_IMU_RLC_DATA_4_BASE_IDX = 1 # macro
regGFX_IMU_RLC_DATA_3 = 0x4047 # macro
regGFX_IMU_RLC_DATA_3_BASE_IDX = 1 # macro
regGFX_IMU_RLC_DATA_2 = 0x4048 # macro
regGFX_IMU_RLC_DATA_2_BASE_IDX = 1 # macro
regGFX_IMU_RLC_DATA_1 = 0x4049 # macro
regGFX_IMU_RLC_DATA_1_BASE_IDX = 1 # macro
regGFX_IMU_RLC_DATA_0 = 0x404a # macro
regGFX_IMU_RLC_DATA_0_BASE_IDX = 1 # macro
regGFX_IMU_RLC_CMD = 0x404b # macro
regGFX_IMU_RLC_CMD_BASE_IDX = 1 # macro
regGFX_IMU_RLC_MUTEX = 0x404c # macro
regGFX_IMU_RLC_MUTEX_BASE_IDX = 1 # macro
regGFX_IMU_RLC_MSG_STATUS = 0x404f # macro
regGFX_IMU_RLC_MSG_STATUS_BASE_IDX = 1 # macro
regRLC_GFX_IMU_DATA_0 = 0x4052 # macro
regRLC_GFX_IMU_DATA_0_BASE_IDX = 1 # macro
regRLC_GFX_IMU_CMD = 0x4053 # macro
regRLC_GFX_IMU_CMD_BASE_IDX = 1 # macro
regGFX_IMU_RLC_STATUS = 0x4054 # macro
regGFX_IMU_RLC_STATUS_BASE_IDX = 1 # macro
regGFX_IMU_STATUS = 0x4055 # macro
regGFX_IMU_STATUS_BASE_IDX = 1 # macro
regGFX_IMU_SOC_DATA = 0x4059 # macro
regGFX_IMU_SOC_DATA_BASE_IDX = 1 # macro
regGFX_IMU_SOC_ADDR = 0x405a # macro
regGFX_IMU_SOC_ADDR_BASE_IDX = 1 # macro
regGFX_IMU_SOC_REQ = 0x405b # macro
regGFX_IMU_SOC_REQ_BASE_IDX = 1 # macro
regGFX_IMU_VF_CTRL = 0x405c # macro
regGFX_IMU_VF_CTRL_BASE_IDX = 1 # macro
regGFX_IMU_TELEMETRY = 0x4060 # macro
regGFX_IMU_TELEMETRY_BASE_IDX = 1 # macro
regGFX_IMU_TELEMETRY_DATA = 0x4061 # macro
regGFX_IMU_TELEMETRY_DATA_BASE_IDX = 1 # macro
regGFX_IMU_TELEMETRY_TEMPERATURE = 0x4062 # macro
regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_0 = 0x4068 # macro
regGFX_IMU_SCRATCH_0_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_1 = 0x4069 # macro
regGFX_IMU_SCRATCH_1_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_2 = 0x406a # macro
regGFX_IMU_SCRATCH_2_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_3 = 0x406b # macro
regGFX_IMU_SCRATCH_3_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_4 = 0x406c # macro
regGFX_IMU_SCRATCH_4_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_5 = 0x406d # macro
regGFX_IMU_SCRATCH_5_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_6 = 0x406e # macro
regGFX_IMU_SCRATCH_6_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_7 = 0x406f # macro
regGFX_IMU_SCRATCH_7_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_8 = 0x4070 # macro
regGFX_IMU_SCRATCH_8_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_9 = 0x4071 # macro
regGFX_IMU_SCRATCH_9_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_10 = 0x4072 # macro
regGFX_IMU_SCRATCH_10_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_11 = 0x4073 # macro
regGFX_IMU_SCRATCH_11_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_12 = 0x4074 # macro
regGFX_IMU_SCRATCH_12_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_13 = 0x4075 # macro
regGFX_IMU_SCRATCH_13_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_14 = 0x4076 # macro
regGFX_IMU_SCRATCH_14_BASE_IDX = 1 # macro
regGFX_IMU_SCRATCH_15 = 0x4077 # macro
regGFX_IMU_SCRATCH_15_BASE_IDX = 1 # macro
regGFX_IMU_FW_GTS_LO = 0x4078 # macro
regGFX_IMU_FW_GTS_LO_BASE_IDX = 1 # macro
regGFX_IMU_FW_GTS_HI = 0x4079 # macro
regGFX_IMU_FW_GTS_HI_BASE_IDX = 1 # macro
regGFX_IMU_GTS_OFFSET_LO = 0x407a # macro
regGFX_IMU_GTS_OFFSET_LO_BASE_IDX = 1 # macro
regGFX_IMU_GTS_OFFSET_HI = 0x407b # macro
regGFX_IMU_GTS_OFFSET_HI_BASE_IDX = 1 # macro
regGFX_IMU_RLC_GTS_OFFSET_LO = 0x407c # macro
regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX = 1 # macro
regGFX_IMU_RLC_GTS_OFFSET_HI = 0x407d # macro
regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX = 1 # macro
regGFX_IMU_CORE_INT_STATUS = 0x407f # macro
regGFX_IMU_CORE_INT_STATUS_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INT_MASK = 0x4080 # macro
regGFX_IMU_PIC_INT_MASK_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INT_LVL = 0x4081 # macro
regGFX_IMU_PIC_INT_LVL_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INT_EDGE = 0x4082 # macro
regGFX_IMU_PIC_INT_EDGE_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INT_PRI_0 = 0x4083 # macro
regGFX_IMU_PIC_INT_PRI_0_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INT_PRI_1 = 0x4084 # macro
regGFX_IMU_PIC_INT_PRI_1_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INT_PRI_2 = 0x4085 # macro
regGFX_IMU_PIC_INT_PRI_2_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INT_PRI_3 = 0x4086 # macro
regGFX_IMU_PIC_INT_PRI_3_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INT_PRI_4 = 0x4087 # macro
regGFX_IMU_PIC_INT_PRI_4_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INT_PRI_5 = 0x4088 # macro
regGFX_IMU_PIC_INT_PRI_5_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INT_PRI_6 = 0x4089 # macro
regGFX_IMU_PIC_INT_PRI_6_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INT_PRI_7 = 0x408a # macro
regGFX_IMU_PIC_INT_PRI_7_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INT_STATUS = 0x408b # macro
regGFX_IMU_PIC_INT_STATUS_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INTR = 0x408c # macro
regGFX_IMU_PIC_INTR_BASE_IDX = 1 # macro
regGFX_IMU_PIC_INTR_ID = 0x408d # macro
regGFX_IMU_PIC_INTR_ID_BASE_IDX = 1 # macro
regGFX_IMU_IH_CTRL_1 = 0x4090 # macro
regGFX_IMU_IH_CTRL_1_BASE_IDX = 1 # macro
regGFX_IMU_IH_CTRL_2 = 0x4091 # macro
regGFX_IMU_IH_CTRL_2_BASE_IDX = 1 # macro
regGFX_IMU_IH_CTRL_3 = 0x4092 # macro
regGFX_IMU_IH_CTRL_3_BASE_IDX = 1 # macro
regGFX_IMU_IH_STATUS = 0x4093 # macro
regGFX_IMU_IH_STATUS_BASE_IDX = 1 # macro
regGFX_IMU_FUSESTRAP = 0x4094 # macro
regGFX_IMU_SMUIO_VIDCHG_CTRL = 0x4098 # macro
regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX = 1 # macro
regGFX_IMU_GFXCLK_BYPASS_CTRL = 0x409c # macro
regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX = 1 # macro
regGFX_IMU_CLK_CTRL = 0x409d # macro
regGFX_IMU_CLK_CTRL_BASE_IDX = 1 # macro
regGFX_IMU_DOORBELL_CONTROL = 0x409e # macro
regGFX_IMU_DOORBELL_CONTROL_BASE_IDX = 1 # macro
regGFX_IMU_RLC_CG_CTRL = 0x40a0 # macro
regGFX_IMU_RLC_CG_CTRL_BASE_IDX = 1 # macro
regGFX_IMU_RLC_THROTTLE_GFX = 0x40a1 # macro
regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX = 1 # macro
regGFX_IMU_RLC_RESET_VECTOR = 0x40a2 # macro
regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX = 1 # macro
regGFX_IMU_RLC_OVERRIDE = 0x40a3 # macro
regGFX_IMU_RLC_OVERRIDE_BASE_IDX = 1 # macro
regGFX_IMU_DPM_CONTROL = 0x40a8 # macro
regGFX_IMU_DPM_CONTROL_BASE_IDX = 1 # macro
regGFX_IMU_DPM_ACC = 0x40a9 # macro
regGFX_IMU_DPM_ACC_BASE_IDX = 1 # macro
regGFX_IMU_DPM_REF_COUNTER = 0x40aa # macro
regGFX_IMU_DPM_REF_COUNTER_BASE_IDX = 1 # macro
regGFX_IMU_RLC_RAM_INDEX = 0x40ac # macro
regGFX_IMU_RLC_RAM_INDEX_BASE_IDX = 1 # macro
regGFX_IMU_RLC_RAM_ADDR_HIGH = 0x40ad # macro
regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX = 1 # macro
regGFX_IMU_RLC_RAM_ADDR_LOW = 0x40ae # macro
regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX = 1 # macro
regGFX_IMU_RLC_RAM_DATA = 0x40af # macro
regGFX_IMU_RLC_RAM_DATA_BASE_IDX = 1 # macro
regGFX_IMU_FENCE_CTRL = 0x40b0 # macro
regGFX_IMU_FENCE_CTRL_BASE_IDX = 1 # macro
regGFX_IMU_FENCE_LOG_INIT = 0x40b1 # macro
regGFX_IMU_FENCE_LOG_INIT_BASE_IDX = 1 # macro
regGFX_IMU_FENCE_LOG_ADDR = 0x40b2 # macro
regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX = 1 # macro
regGFX_IMU_PROGRAM_CTR = 0x40b5 # macro
regGFX_IMU_PROGRAM_CTR_BASE_IDX = 1 # macro
regGFX_IMU_CORE_CTRL = 0x40b6 # macro
regGFX_IMU_CORE_CTRL_BASE_IDX = 1 # macro
regGFX_IMU_CORE_STATUS = 0x40b7 # macro
regGFX_IMU_CORE_STATUS_BASE_IDX = 1 # macro
regGFX_IMU_PWROKRAW = 0x40b8 # macro
regGFX_IMU_PWROKRAW_BASE_IDX = 1 # macro
regGFX_IMU_PWROK = 0x40b9 # macro
regGFX_IMU_PWROK_BASE_IDX = 1 # macro
regGFX_IMU_GAP_PWROK = 0x40ba # macro
regGFX_IMU_GAP_PWROK_BASE_IDX = 1 # macro
regGFX_IMU_RESETn = 0x40bb # macro
regGFX_IMU_RESETn_BASE_IDX = 1 # macro
regGFX_IMU_GFX_RESET_CTRL = 0x40bc # macro
regGFX_IMU_GFX_RESET_CTRL_BASE_IDX = 1 # macro
regGFX_IMU_AEB_OVERRIDE = 0x40bd # macro
regGFX_IMU_AEB_OVERRIDE_BASE_IDX = 1 # macro
regGFX_IMU_VDCI_RESET_CTRL = 0x40be # macro
regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX = 1 # macro
regGFX_IMU_GFX_ISO_CTRL = 0x40bf # macro
regGFX_IMU_GFX_ISO_CTRL_BASE_IDX = 1 # macro
regGFX_IMU_TIMER0_CTRL0 = 0x40c0 # macro
regGFX_IMU_TIMER0_CTRL0_BASE_IDX = 1 # macro
regGFX_IMU_TIMER0_CTRL1 = 0x40c1 # macro
regGFX_IMU_TIMER0_CTRL1_BASE_IDX = 1 # macro
regGFX_IMU_TIMER0_CMP_AUTOINC = 0x40c2 # macro
regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX = 1 # macro
regGFX_IMU_TIMER0_CMP_INTEN = 0x40c3 # macro
regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX = 1 # macro
regGFX_IMU_TIMER0_CMP0 = 0x40c4 # macro
regGFX_IMU_TIMER0_CMP0_BASE_IDX = 1 # macro
regGFX_IMU_TIMER0_CMP1 = 0x40c5 # macro
regGFX_IMU_TIMER0_CMP1_BASE_IDX = 1 # macro
regGFX_IMU_TIMER0_CMP3 = 0x40c7 # macro
regGFX_IMU_TIMER0_CMP3_BASE_IDX = 1 # macro
regGFX_IMU_TIMER0_VALUE = 0x40c8 # macro
regGFX_IMU_TIMER0_VALUE_BASE_IDX = 1 # macro
regGFX_IMU_TIMER1_CTRL0 = 0x40c9 # macro
regGFX_IMU_TIMER1_CTRL0_BASE_IDX = 1 # macro
regGFX_IMU_TIMER1_CTRL1 = 0x40ca # macro
regGFX_IMU_TIMER1_CTRL1_BASE_IDX = 1 # macro
regGFX_IMU_TIMER1_CMP_AUTOINC = 0x40cb # macro
regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX = 1 # macro
regGFX_IMU_TIMER1_CMP_INTEN = 0x40cc # macro
regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX = 1 # macro
regGFX_IMU_TIMER1_CMP0 = 0x40cd # macro
regGFX_IMU_TIMER1_CMP0_BASE_IDX = 1 # macro
regGFX_IMU_TIMER1_CMP1 = 0x40ce # macro
regGFX_IMU_TIMER1_CMP1_BASE_IDX = 1 # macro
regGFX_IMU_TIMER1_CMP3 = 0x40d0 # macro
regGFX_IMU_TIMER1_CMP3_BASE_IDX = 1 # macro
regGFX_IMU_TIMER1_VALUE = 0x40d1 # macro
regGFX_IMU_TIMER1_VALUE_BASE_IDX = 1 # macro
regGFX_IMU_TIMER2_CTRL0 = 0x40d2 # macro
regGFX_IMU_TIMER2_CTRL0_BASE_IDX = 1 # macro
regGFX_IMU_TIMER2_CTRL1 = 0x40d3 # macro
regGFX_IMU_TIMER2_CTRL1_BASE_IDX = 1 # macro
regGFX_IMU_TIMER2_CMP_AUTOINC = 0x40d4 # macro
regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX = 1 # macro
regGFX_IMU_TIMER2_CMP_INTEN = 0x40d5 # macro
regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX = 1 # macro
regGFX_IMU_TIMER2_CMP0 = 0x40d6 # macro
regGFX_IMU_TIMER2_CMP0_BASE_IDX = 1 # macro
regGFX_IMU_TIMER2_CMP1 = 0x40d7 # macro
regGFX_IMU_TIMER2_CMP1_BASE_IDX = 1 # macro
regGFX_IMU_TIMER2_CMP3 = 0x40d9 # macro
regGFX_IMU_TIMER2_CMP3_BASE_IDX = 1 # macro
regGFX_IMU_TIMER2_VALUE = 0x40da # macro
regGFX_IMU_TIMER2_VALUE_BASE_IDX = 1 # macro
regGFX_IMU_FUSE_CTRL = 0x40e0 # macro
regGFX_IMU_FUSE_CTRL_BASE_IDX = 1 # macro
regGFX_IMU_D_RAM_ADDR = 0x40fc # macro
regGFX_IMU_D_RAM_ADDR_BASE_IDX = 1 # macro
regGFX_IMU_D_RAM_DATA = 0x40fd # macro
regGFX_IMU_D_RAM_DATA_BASE_IDX = 1 # macro
regGFX_IMU_GFX_IH_GASKET_CTRL = 0x40ff # macro
regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX = 1 # macro
regGFX_IMU_RLC_BOOTLOADER_ADDR_HI = 0x5f81 # macro
regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX = 1 # macro
regGFX_IMU_RLC_BOOTLOADER_ADDR_LO = 0x5f82 # macro
regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX = 1 # macro
regGFX_IMU_RLC_BOOTLOADER_SIZE = 0x5f83 # macro
regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX = 1 # macro
regGFX_IMU_I_RAM_ADDR = 0x5f90 # macro
regGFX_IMU_I_RAM_ADDR_BASE_IDX = 1 # macro
regGFX_IMU_I_RAM_DATA = 0x5f91 # macro
regGFX_IMU_I_RAM_DATA_BASE_IDX = 1 # macro
ixGC_CAC_ID = 0x0020 # macro
ixGC_CAC_CNTL = 0x0021 # macro
ixGC_CAC_ACC_CP0 = 0x0115 # macro
ixGC_CAC_ACC_CP1 = 0x0116 # macro
ixGC_CAC_ACC_CP2 = 0x0117 # macro
ixGC_CAC_ACC_EA0 = 0x016c # macro
ixGC_CAC_ACC_EA1 = 0x016d # macro
ixGC_CAC_ACC_EA2 = 0x016e # macro
ixGC_CAC_ACC_EA3 = 0x016f # macro
ixGC_CAC_ACC_EA4 = 0x0170 # macro
ixGC_CAC_ACC_EA5 = 0x0171 # macro
ixGC_CAC_ACC_UTCL2_ROUTER0 = 0x0177 # macro
ixGC_CAC_ACC_UTCL2_ROUTER1 = 0x0178 # macro
ixGC_CAC_ACC_UTCL2_ROUTER2 = 0x0179 # macro
ixGC_CAC_ACC_UTCL2_ROUTER3 = 0x017a # macro
ixGC_CAC_ACC_UTCL2_ROUTER4 = 0x017b # macro
ixGC_CAC_ACC_UTCL2_ROUTER5 = 0x017c # macro
ixGC_CAC_ACC_UTCL2_ROUTER6 = 0x017d # macro
ixGC_CAC_ACC_UTCL2_ROUTER7 = 0x017e # macro
ixGC_CAC_ACC_UTCL2_ROUTER8 = 0x017f # macro
ixGC_CAC_ACC_UTCL2_ROUTER9 = 0x0180 # macro
ixGC_CAC_ACC_UTCL2_VML20 = 0x0181 # macro
ixGC_CAC_ACC_UTCL2_VML21 = 0x0182 # macro
ixGC_CAC_ACC_UTCL2_VML22 = 0x0183 # macro
ixGC_CAC_ACC_UTCL2_VML23 = 0x0184 # macro
ixGC_CAC_ACC_UTCL2_VML24 = 0x0185 # macro
ixGC_CAC_ACC_UTCL2_WALKER0 = 0x0186 # macro
ixGC_CAC_ACC_UTCL2_WALKER1 = 0x0187 # macro
ixGC_CAC_ACC_UTCL2_WALKER2 = 0x0188 # macro
ixGC_CAC_ACC_UTCL2_WALKER3 = 0x0189 # macro
ixGC_CAC_ACC_UTCL2_WALKER4 = 0x018a # macro
ixGC_CAC_ACC_GDS0 = 0x0122 # macro
ixGC_CAC_ACC_GDS1 = 0x0123 # macro
ixGC_CAC_ACC_GDS2 = 0x0124 # macro
ixGC_CAC_ACC_GDS3 = 0x0125 # macro
ixGC_CAC_ACC_GDS4 = 0x0126 # macro
ixGC_CAC_ACC_GE0 = 0x0190 # macro
ixGC_CAC_ACC_GE1 = 0x0191 # macro
ixGC_CAC_ACC_GE2 = 0x0192 # macro
ixGC_CAC_ACC_GE3 = 0x0193 # macro
ixGC_CAC_ACC_GE4 = 0x0194 # macro
ixGC_CAC_ACC_GE5 = 0x0195 # macro
ixGC_CAC_ACC_GE6 = 0x0196 # macro
ixGC_CAC_ACC_GE7 = 0x0197 # macro
ixGC_CAC_ACC_GE8 = 0x0198 # macro
ixGC_CAC_ACC_GE9 = 0x0199 # macro
ixGC_CAC_ACC_GE10 = 0x019a # macro
ixGC_CAC_ACC_GE11 = 0x019b # macro
ixGC_CAC_ACC_GE12 = 0x019c # macro
ixGC_CAC_ACC_GE13 = 0x019d # macro
ixGC_CAC_ACC_GE14 = 0x019e # macro
ixGC_CAC_ACC_GE15 = 0x019f # macro
ixGC_CAC_ACC_GE16 = 0x01a0 # macro
ixGC_CAC_ACC_GE17 = 0x01a1 # macro
ixGC_CAC_ACC_GE18 = 0x01a2 # macro
ixGC_CAC_ACC_GE19 = 0x01a3 # macro
ixGC_CAC_ACC_GE20 = 0x01a4 # macro
ixGC_CAC_ACC_PMM0 = 0x01a5 # macro
ixGC_CAC_ACC_GL2C0 = 0x01a6 # macro
ixGC_CAC_ACC_GL2C1 = 0x01a7 # macro
ixGC_CAC_ACC_GL2C2 = 0x01a8 # macro
ixGC_CAC_ACC_GL2C3 = 0x01a9 # macro
ixGC_CAC_ACC_GL2C4 = 0x01aa # macro
ixGC_CAC_ACC_PH0 = 0x01ae # macro
ixGC_CAC_ACC_PH1 = 0x01af # macro
ixGC_CAC_ACC_PH2 = 0x01b0 # macro
ixGC_CAC_ACC_PH3 = 0x01b1 # macro
ixGC_CAC_ACC_PH4 = 0x01b2 # macro
ixGC_CAC_ACC_PH5 = 0x01b3 # macro
ixGC_CAC_ACC_PH6 = 0x01b4 # macro
ixGC_CAC_ACC_PH7 = 0x01b5 # macro
ixGC_CAC_ACC_SDMA0 = 0x01b6 # macro
ixGC_CAC_ACC_SDMA1 = 0x01b7 # macro
ixGC_CAC_ACC_SDMA2 = 0x01b8 # macro
ixGC_CAC_ACC_SDMA3 = 0x01b9 # macro
ixGC_CAC_ACC_SDMA4 = 0x01ba # macro
ixGC_CAC_ACC_SDMA5 = 0x01bb # macro
ixGC_CAC_ACC_SDMA6 = 0x01bc # macro
ixGC_CAC_ACC_SDMA7 = 0x01bd # macro
ixGC_CAC_ACC_SDMA8 = 0x01be # macro
ixGC_CAC_ACC_SDMA9 = 0x01bf # macro
ixGC_CAC_ACC_SDMA10 = 0x01c0 # macro
ixGC_CAC_ACC_SDMA11 = 0x01c1 # macro
ixGC_CAC_ACC_CHC0 = 0x018d # macro
ixGC_CAC_ACC_CHC1 = 0x018e # macro
ixGC_CAC_ACC_CHC2 = 0x018f # macro
ixGC_CAC_ACC_GUS0 = 0x01ab # macro
ixGC_CAC_ACC_GUS1 = 0x01ac # macro
ixGC_CAC_ACC_GUS2 = 0x01ad # macro
ixGC_CAC_ACC_RLC0 = 0x01d0 # macro
ixRELEASE_TO_STALL_LUT_1_8 = 0x0230 # macro
ixRELEASE_TO_STALL_LUT_9_16 = 0x0231 # macro
ixRELEASE_TO_STALL_LUT_17_20 = 0x0232 # macro
ixSTALL_TO_RELEASE_LUT_1_4 = 0x0233 # macro
ixSTALL_TO_RELEASE_LUT_5_7 = 0x0234 # macro
ixSTALL_TO_PWRBRK_LUT_1_4 = 0x0235 # macro
ixSTALL_TO_PWRBRK_LUT_5_7 = 0x0236 # macro
ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 = 0x0237 # macro
ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 = 0x0238 # macro
ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 = 0x0239 # macro
ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 = 0x023a # macro
ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 = 0x023b # macro
ixFIXED_PATTERN_PERF_COUNTER_1 = 0x023c # macro
ixFIXED_PATTERN_PERF_COUNTER_2 = 0x023d # macro
ixFIXED_PATTERN_PERF_COUNTER_3 = 0x023e # macro
ixFIXED_PATTERN_PERF_COUNTER_4 = 0x023f # macro
ixFIXED_PATTERN_PERF_COUNTER_5 = 0x0240 # macro
ixFIXED_PATTERN_PERF_COUNTER_6 = 0x0241 # macro
ixFIXED_PATTERN_PERF_COUNTER_7 = 0x0242 # macro
ixFIXED_PATTERN_PERF_COUNTER_8 = 0x0243 # macro
ixFIXED_PATTERN_PERF_COUNTER_9 = 0x0244 # macro
ixFIXED_PATTERN_PERF_COUNTER_10 = 0x0245 # macro
ixHW_LUT_UPDATE_STATUS = 0x0246 # macro
ixSE_CAC_ID = 0x0000 # macro
ixSE_CAC_CNTL = 0x0001 # macro
ixRTAVFS_REG0 = 0x0000 # macro
ixRTAVFS_REG1 = 0x0001 # macro
ixRTAVFS_REG2 = 0x0002 # macro
ixRTAVFS_REG3 = 0x0003 # macro
ixRTAVFS_REG4 = 0x0004 # macro
ixRTAVFS_REG5 = 0x0005 # macro
ixRTAVFS_REG6 = 0x0006 # macro
ixRTAVFS_REG7 = 0x0007 # macro
ixRTAVFS_REG8 = 0x0008 # macro
ixRTAVFS_REG9 = 0x0009 # macro
ixRTAVFS_REG10 = 0x000a # macro
ixRTAVFS_REG11 = 0x000b # macro
ixRTAVFS_REG12 = 0x000c # macro
ixRTAVFS_REG13 = 0x000d # macro
ixRTAVFS_REG14 = 0x000e # macro
ixRTAVFS_REG15 = 0x000f # macro
ixRTAVFS_REG16 = 0x0010 # macro
ixRTAVFS_REG17 = 0x0011 # macro
ixRTAVFS_REG18 = 0x0012 # macro
ixRTAVFS_REG19 = 0x0013 # macro
ixRTAVFS_REG20 = 0x0014 # macro
ixRTAVFS_REG21 = 0x0015 # macro
ixRTAVFS_REG22 = 0x0016 # macro
ixRTAVFS_REG23 = 0x0017 # macro
ixRTAVFS_REG24 = 0x0018 # macro
ixRTAVFS_REG25 = 0x0019 # macro
ixRTAVFS_REG26 = 0x001a # macro
ixRTAVFS_REG27 = 0x001b # macro
ixRTAVFS_REG28 = 0x001c # macro
ixRTAVFS_REG29 = 0x001d # macro
ixRTAVFS_REG30 = 0x001e # macro
ixRTAVFS_REG31 = 0x001f # macro
ixRTAVFS_REG32 = 0x0020 # macro
ixRTAVFS_REG33 = 0x0021 # macro
ixRTAVFS_REG34 = 0x0022 # macro
ixRTAVFS_REG35 = 0x0023 # macro
ixRTAVFS_REG36 = 0x0024 # macro
ixRTAVFS_REG37 = 0x0025 # macro
ixRTAVFS_REG38 = 0x0026 # macro
ixRTAVFS_REG39 = 0x0027 # macro
ixRTAVFS_REG40 = 0x0028 # macro
ixRTAVFS_REG41 = 0x0029 # macro
ixRTAVFS_REG42 = 0x002a # macro
ixRTAVFS_REG43 = 0x002b # macro
ixRTAVFS_REG44 = 0x002c # macro
ixRTAVFS_REG45 = 0x002d # macro
ixRTAVFS_REG46 = 0x002e # macro
ixRTAVFS_REG47 = 0x002f # macro
ixRTAVFS_REG48 = 0x0030 # macro
ixRTAVFS_REG49 = 0x0031 # macro
ixRTAVFS_REG50 = 0x0032 # macro
ixRTAVFS_REG51 = 0x0033 # macro
ixRTAVFS_REG52 = 0x0034 # macro
ixRTAVFS_REG53 = 0x0035 # macro
ixRTAVFS_REG54 = 0x0036 # macro
ixRTAVFS_REG55 = 0x0037 # macro
ixRTAVFS_REG56 = 0x0038 # macro
ixRTAVFS_REG57 = 0x0039 # macro
ixRTAVFS_REG58 = 0x003a # macro
ixRTAVFS_REG59 = 0x003b # macro
ixRTAVFS_REG60 = 0x003c # macro
ixRTAVFS_REG61 = 0x003d # macro
ixRTAVFS_REG62 = 0x003e # macro
ixRTAVFS_REG63 = 0x003f # macro
ixRTAVFS_REG64 = 0x0040 # macro
ixRTAVFS_REG65 = 0x0041 # macro
ixRTAVFS_REG66 = 0x0042 # macro
ixRTAVFS_REG67 = 0x0043 # macro
ixRTAVFS_REG68 = 0x0044 # macro
ixRTAVFS_REG69 = 0x0045 # macro
ixRTAVFS_REG70 = 0x0046 # macro
ixRTAVFS_REG71 = 0x0047 # macro
ixRTAVFS_REG72 = 0x0048 # macro
ixRTAVFS_REG73 = 0x0049 # macro
ixRTAVFS_REG74 = 0x004a # macro
ixRTAVFS_REG75 = 0x004b # macro
ixRTAVFS_REG76 = 0x004c # macro
ixRTAVFS_REG77 = 0x004d # macro
ixRTAVFS_REG78 = 0x004e # macro
ixRTAVFS_REG79 = 0x004f # macro
ixRTAVFS_REG80 = 0x0050 # macro
ixRTAVFS_REG81 = 0x0051 # macro
ixRTAVFS_REG82 = 0x0052 # macro
ixRTAVFS_REG83 = 0x0053 # macro
ixRTAVFS_REG84 = 0x0054 # macro
ixRTAVFS_REG85 = 0x0055 # macro
ixRTAVFS_REG86 = 0x0056 # macro
ixRTAVFS_REG87 = 0x0057 # macro
ixRTAVFS_REG88 = 0x0058 # macro
ixRTAVFS_REG89 = 0x0059 # macro
ixRTAVFS_REG90 = 0x005a # macro
ixRTAVFS_REG91 = 0x005b # macro
ixRTAVFS_REG92 = 0x005c # macro
ixRTAVFS_REG93 = 0x005d # macro
ixRTAVFS_REG94 = 0x005e # macro
ixRTAVFS_REG95 = 0x005f # macro
ixRTAVFS_REG96 = 0x0060 # macro
ixRTAVFS_REG97 = 0x0061 # macro
ixRTAVFS_REG98 = 0x0062 # macro
ixRTAVFS_REG99 = 0x0063 # macro
ixRTAVFS_REG100 = 0x0064 # macro
ixRTAVFS_REG101 = 0x0065 # macro
ixRTAVFS_REG102 = 0x0066 # macro
ixRTAVFS_REG103 = 0x0067 # macro
ixRTAVFS_REG104 = 0x0068 # macro
ixRTAVFS_REG105 = 0x0069 # macro
ixRTAVFS_REG106 = 0x006a # macro
ixRTAVFS_REG107 = 0x006b # macro
ixRTAVFS_REG108 = 0x006c # macro
ixRTAVFS_REG109 = 0x006d # macro
ixRTAVFS_REG110 = 0x006e # macro
ixRTAVFS_REG111 = 0x006f # macro
ixRTAVFS_REG112 = 0x0070 # macro
ixRTAVFS_REG113 = 0x0071 # macro
ixRTAVFS_REG114 = 0x0072 # macro
ixRTAVFS_REG115 = 0x0073 # macro
ixRTAVFS_REG116 = 0x0074 # macro
ixRTAVFS_REG117 = 0x0075 # macro
ixRTAVFS_REG118 = 0x0076 # macro
ixRTAVFS_REG119 = 0x0077 # macro
ixRTAVFS_REG120 = 0x0078 # macro
ixRTAVFS_REG121 = 0x0079 # macro
ixRTAVFS_REG122 = 0x007a # macro
ixRTAVFS_REG123 = 0x007b # macro
ixRTAVFS_REG124 = 0x007c # macro
ixRTAVFS_REG125 = 0x007d # macro
ixRTAVFS_REG126 = 0x007e # macro
ixRTAVFS_REG127 = 0x007f # macro
ixRTAVFS_REG128 = 0x0080 # macro
ixRTAVFS_REG129 = 0x0081 # macro
ixRTAVFS_REG130 = 0x0082 # macro
ixRTAVFS_REG131 = 0x0083 # macro
ixRTAVFS_REG132 = 0x0084 # macro
ixRTAVFS_REG133 = 0x0085 # macro
ixRTAVFS_REG134 = 0x0086 # macro
ixRTAVFS_REG135 = 0x0087 # macro
ixRTAVFS_REG136 = 0x0088 # macro
ixRTAVFS_REG137 = 0x0089 # macro
ixRTAVFS_REG138 = 0x008a # macro
ixRTAVFS_REG139 = 0x008b # macro
ixRTAVFS_REG140 = 0x008c # macro
ixRTAVFS_REG141 = 0x008d # macro
ixRTAVFS_REG142 = 0x008e # macro
ixRTAVFS_REG143 = 0x008f # macro
ixRTAVFS_REG144 = 0x0090 # macro
ixRTAVFS_REG145 = 0x0091 # macro
ixRTAVFS_REG146 = 0x0092 # macro
ixRTAVFS_REG147 = 0x0093 # macro
ixRTAVFS_REG148 = 0x0094 # macro
ixRTAVFS_REG149 = 0x0095 # macro
ixRTAVFS_REG150 = 0x0096 # macro
ixRTAVFS_REG151 = 0x0097 # macro
ixRTAVFS_REG152 = 0x0098 # macro
ixRTAVFS_REG153 = 0x0099 # macro
ixRTAVFS_REG154 = 0x009a # macro
ixRTAVFS_REG155 = 0x009b # macro
ixRTAVFS_REG156 = 0x009c # macro
ixRTAVFS_REG157 = 0x009d # macro
ixRTAVFS_REG158 = 0x009e # macro
ixRTAVFS_REG159 = 0x009f # macro
ixRTAVFS_REG160 = 0x00a0 # macro
ixRTAVFS_REG161 = 0x00a1 # macro
ixRTAVFS_REG162 = 0x00a2 # macro
ixRTAVFS_REG163 = 0x00a3 # macro
ixRTAVFS_REG164 = 0x00a4 # macro
ixRTAVFS_REG165 = 0x00a5 # macro
ixRTAVFS_REG166 = 0x00a6 # macro
ixRTAVFS_REG167 = 0x00a7 # macro
ixRTAVFS_REG168 = 0x00a8 # macro
ixRTAVFS_REG169 = 0x00a9 # macro
ixRTAVFS_REG170 = 0x00aa # macro
ixRTAVFS_REG171 = 0x00ab # macro
ixRTAVFS_REG172 = 0x00ac # macro
ixRTAVFS_REG173 = 0x00ad # macro
ixRTAVFS_REG174 = 0x00ae # macro
ixRTAVFS_REG175 = 0x00af # macro
ixRTAVFS_REG176 = 0x00b0 # macro
ixRTAVFS_REG177 = 0x00b1 # macro
ixRTAVFS_REG178 = 0x00b2 # macro
ixRTAVFS_REG179 = 0x00b3 # macro
ixRTAVFS_REG180 = 0x00b4 # macro
ixRTAVFS_REG181 = 0x00b5 # macro
ixRTAVFS_REG182 = 0x00b6 # macro
ixRTAVFS_REG183 = 0x00b7 # macro
ixRTAVFS_REG184 = 0x00b8 # macro
ixRTAVFS_REG185 = 0x00b9 # macro
ixRTAVFS_REG186 = 0x00ba # macro
ixRTAVFS_REG187 = 0x00bb # macro
ixRTAVFS_REG188 = 0x00bc # macro
ixRTAVFS_REG189 = 0x00bd # macro
ixRTAVFS_REG190 = 0x00be # macro
ixRTAVFS_REG191 = 0x00bf # macro
ixRTAVFS_REG192 = 0x00c0 # macro
ixRTAVFS_REG193 = 0x00c1 # macro
ixRTAVFS_REG194 = 0x00c2 # macro
ixSQ_DEBUG_STS_LOCAL = 0x0008 # macro
ixSQ_DEBUG_CTRL_LOCAL = 0x0009 # macro
ixSQ_WAVE_ACTIVE = 0x000a # macro
ixSQ_WAVE_VALID_AND_IDLE = 0x000b # macro
ixSQ_WAVE_MODE = 0x0101 # macro
ixSQ_WAVE_STATUS = 0x0102 # macro
ixSQ_WAVE_TRAPSTS = 0x0103 # macro
ixSQ_WAVE_GPR_ALLOC = 0x0105 # macro
ixSQ_WAVE_LDS_ALLOC = 0x0106 # macro
ixSQ_WAVE_IB_STS = 0x0107 # macro
ixSQ_WAVE_PC_LO = 0x0108 # macro
ixSQ_WAVE_PC_HI = 0x0109 # macro
ixSQ_WAVE_IB_DBG1 = 0x010d # macro
ixSQ_WAVE_FLUSH_IB = 0x010e # macro
ixSQ_WAVE_FLAT_SCRATCH_LO = 0x0114 # macro
ixSQ_WAVE_FLAT_SCRATCH_HI = 0x0115 # macro
ixSQ_WAVE_HW_ID1 = 0x0117 # macro
ixSQ_WAVE_HW_ID2 = 0x0118 # macro
ixSQ_WAVE_POPS_PACKER = 0x0119 # macro
ixSQ_WAVE_SCHED_MODE = 0x011a # macro
ixSQ_WAVE_IB_STS2 = 0x011c # macro
ixSQ_WAVE_SHADER_CYCLES = 0x011d # macro
ixSQ_WAVE_TTMP0 = 0x026c # macro
ixSQ_WAVE_TTMP1 = 0x026d # macro
ixSQ_WAVE_TTMP3 = 0x026f # macro
ixSQ_WAVE_TTMP4 = 0x0270 # macro
ixSQ_WAVE_TTMP5 = 0x0271 # macro
ixSQ_WAVE_TTMP6 = 0x0272 # macro
ixSQ_WAVE_TTMP7 = 0x0273 # macro
ixSQ_WAVE_TTMP8 = 0x0274 # macro
ixSQ_WAVE_TTMP9 = 0x0275 # macro
ixSQ_WAVE_TTMP10 = 0x0276 # macro
ixSQ_WAVE_TTMP11 = 0x0277 # macro
ixSQ_WAVE_TTMP12 = 0x0278 # macro
ixSQ_WAVE_TTMP13 = 0x0279 # macro
ixSQ_WAVE_TTMP14 = 0x027a # macro
ixSQ_WAVE_TTMP15 = 0x027b # macro
ixSQ_WAVE_M0 = 0x027c # macro
ixSQ_WAVE_EXEC_LO = 0x027e # macro
ixSQ_WAVE_EXEC_HI = 0x027f # macro
_gc_10_3_0_OFFSET_HEADER = True # macro
mmSQ_DEBUG_STS_GLOBAL = 0x10A9 # macro
mmSQ_DEBUG_STS_GLOBAL_BASE_IDX = 0 # macro
mmSQ_DEBUG_STS_GLOBAL2 = 0x10B0 # macro
mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX = 0 # macro
mmSQ_DEBUG = 0x10B1 # macro
mmSQ_DEBUG_BASE_IDX = 0 # macro
mmSDMA0_DEC_START = 0x0000 # macro
mmSDMA0_DEC_START_BASE_IDX = 0 # macro
mmSDMA0_GLOBAL_TIMESTAMP_LO = 0x000f # macro
mmSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro
mmSDMA0_GLOBAL_TIMESTAMP_HI = 0x0010 # macro
mmSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro
mmSDMA0_PG_CNTL = 0x0016 # macro
mmSDMA0_PG_CNTL_BASE_IDX = 0 # macro
mmSDMA0_PG_CTX_LO = 0x0017 # macro
mmSDMA0_PG_CTX_LO_BASE_IDX = 0 # macro
mmSDMA0_PG_CTX_HI = 0x0018 # macro
mmSDMA0_PG_CTX_HI_BASE_IDX = 0 # macro
mmSDMA0_PG_CTX_CNTL = 0x0019 # macro
mmSDMA0_PG_CTX_CNTL_BASE_IDX = 0 # macro
mmSDMA0_POWER_CNTL = 0x001a # macro
mmSDMA0_POWER_CNTL_BASE_IDX = 0 # macro
mmSDMA0_CLK_CTRL = 0x001b # macro
mmSDMA0_CLK_CTRL_BASE_IDX = 0 # macro
mmSDMA0_CNTL = 0x001c # macro
mmSDMA0_CNTL_BASE_IDX = 0 # macro
mmSDMA0_CHICKEN_BITS = 0x001d # macro
mmSDMA0_CHICKEN_BITS_BASE_IDX = 0 # macro
mmSDMA0_GB_ADDR_CONFIG = 0x001e # macro
mmSDMA0_GB_ADDR_CONFIG_BASE_IDX = 0 # macro
mmSDMA0_GB_ADDR_CONFIG_READ = 0x001f # macro
mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro
mmSDMA0_RB_RPTR_FETCH_HI = 0x0020 # macro
mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro
mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL = 0x0021 # macro
mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RB_RPTR_FETCH = 0x0022 # macro
mmSDMA0_RB_RPTR_FETCH_BASE_IDX = 0 # macro
mmSDMA0_IB_OFFSET_FETCH = 0x0023 # macro
mmSDMA0_IB_OFFSET_FETCH_BASE_IDX = 0 # macro
mmSDMA0_PROGRAM = 0x0024 # macro
mmSDMA0_PROGRAM_BASE_IDX = 0 # macro
mmSDMA0_STATUS_REG = 0x0025 # macro
mmSDMA0_STATUS_REG_BASE_IDX = 0 # macro
mmSDMA0_STATUS1_REG = 0x0026 # macro
mmSDMA0_STATUS1_REG_BASE_IDX = 0 # macro
mmSDMA0_RD_BURST_CNTL = 0x0027 # macro
mmSDMA0_RD_BURST_CNTL_BASE_IDX = 0 # macro
mmSDMA0_HBM_PAGE_CONFIG = 0x0028 # macro
mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro
mmSDMA0_UCODE_CHECKSUM = 0x0029 # macro
mmSDMA0_UCODE_CHECKSUM_BASE_IDX = 0 # macro
mmSDMA0_F32_CNTL = 0x002a # macro
mmSDMA0_F32_CNTL_BASE_IDX = 0 # macro
mmSDMA0_FREEZE = 0x002b # macro
mmSDMA0_FREEZE_BASE_IDX = 0 # macro
mmSDMA0_PHASE0_QUANTUM = 0x002c # macro
mmSDMA0_PHASE0_QUANTUM_BASE_IDX = 0 # macro
mmSDMA0_PHASE1_QUANTUM = 0x002d # macro
mmSDMA0_PHASE1_QUANTUM_BASE_IDX = 0 # macro
mmSDMA0_EDC_CONFIG = 0x0032 # macro
mmSDMA0_EDC_CONFIG_BASE_IDX = 0 # macro
mmSDMA0_BA_THRESHOLD = 0x0033 # macro
mmSDMA0_BA_THRESHOLD_BASE_IDX = 0 # macro
mmSDMA0_ID = 0x0034 # macro
mmSDMA0_ID_BASE_IDX = 0 # macro
mmSDMA0_VERSION = 0x0035 # macro
mmSDMA0_VERSION_BASE_IDX = 0 # macro
mmSDMA0_EDC_COUNTER = 0x0036 # macro
mmSDMA0_EDC_COUNTER_BASE_IDX = 0 # macro
mmSDMA0_EDC_COUNTER_CLEAR = 0x0037 # macro
mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro
mmSDMA0_STATUS2_REG = 0x0038 # macro
mmSDMA0_STATUS2_REG_BASE_IDX = 0 # macro
mmSDMA0_ATOMIC_CNTL = 0x0039 # macro
mmSDMA0_ATOMIC_CNTL_BASE_IDX = 0 # macro
mmSDMA0_ATOMIC_PREOP_LO = 0x003a # macro
mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro
mmSDMA0_ATOMIC_PREOP_HI = 0x003b # macro
mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro
mmSDMA0_UTCL1_CNTL = 0x003c # macro
mmSDMA0_UTCL1_CNTL_BASE_IDX = 0 # macro
mmSDMA0_UTCL1_WATERMK = 0x003d # macro
mmSDMA0_UTCL1_WATERMK_BASE_IDX = 0 # macro
mmSDMA0_UTCL1_RD_STATUS = 0x003e # macro
mmSDMA0_UTCL1_RD_STATUS_BASE_IDX = 0 # macro
mmSDMA0_UTCL1_WR_STATUS = 0x003f # macro
mmSDMA0_UTCL1_WR_STATUS_BASE_IDX = 0 # macro
mmSDMA0_UTCL1_INV0 = 0x0040 # macro
mmSDMA0_UTCL1_INV0_BASE_IDX = 0 # macro
mmSDMA0_UTCL1_INV1 = 0x0041 # macro
mmSDMA0_UTCL1_INV1_BASE_IDX = 0 # macro
mmSDMA0_UTCL1_INV2 = 0x0042 # macro
mmSDMA0_UTCL1_INV2_BASE_IDX = 0 # macro
mmSDMA0_UTCL1_RD_XNACK0 = 0x0043 # macro
mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro
mmSDMA0_UTCL1_RD_XNACK1 = 0x0044 # macro
mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro
mmSDMA0_UTCL1_WR_XNACK0 = 0x0045 # macro
mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro
mmSDMA0_UTCL1_WR_XNACK1 = 0x0046 # macro
mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro
mmSDMA0_UTCL1_TIMEOUT = 0x0047 # macro
mmSDMA0_UTCL1_TIMEOUT_BASE_IDX = 0 # macro
mmSDMA0_UTCL1_PAGE = 0x0048 # macro
mmSDMA0_UTCL1_PAGE_BASE_IDX = 0 # macro
mmSDMA0_RELAX_ORDERING_LUT = 0x004a # macro
mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro
mmSDMA0_CHICKEN_BITS_2 = 0x004b # macro
mmSDMA0_CHICKEN_BITS_2_BASE_IDX = 0 # macro
mmSDMA0_STATUS3_REG = 0x004c # macro
mmSDMA0_STATUS3_REG_BASE_IDX = 0 # macro
mmSDMA0_PHYSICAL_ADDR_LO = 0x004d # macro
mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_PHYSICAL_ADDR_HI = 0x004e # macro
mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_PHASE2_QUANTUM = 0x004f # macro
mmSDMA0_PHASE2_QUANTUM_BASE_IDX = 0 # macro
mmSDMA0_ERROR_LOG = 0x0050 # macro
mmSDMA0_ERROR_LOG_BASE_IDX = 0 # macro
mmSDMA0_PUB_DUMMY_REG0 = 0x0051 # macro
mmSDMA0_PUB_DUMMY_REG0_BASE_IDX = 0 # macro
mmSDMA0_PUB_DUMMY_REG1 = 0x0052 # macro
mmSDMA0_PUB_DUMMY_REG1_BASE_IDX = 0 # macro
mmSDMA0_PUB_DUMMY_REG2 = 0x0053 # macro
mmSDMA0_PUB_DUMMY_REG2_BASE_IDX = 0 # macro
mmSDMA0_PUB_DUMMY_REG3 = 0x0054 # macro
mmSDMA0_PUB_DUMMY_REG3_BASE_IDX = 0 # macro
mmSDMA0_F32_COUNTER = 0x0055 # macro
mmSDMA0_F32_COUNTER_BASE_IDX = 0 # macro
mmSDMA0_CRD_CNTL = 0x005b # macro
mmSDMA0_CRD_CNTL_BASE_IDX = 0 # macro
mmSDMA0_AQL_STATUS = 0x005f # macro
mmSDMA0_AQL_STATUS_BASE_IDX = 0 # macro
mmSDMA0_EA_DBIT_ADDR_DATA = 0x0060 # macro
mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro
mmSDMA0_EA_DBIT_ADDR_INDEX = 0x0061 # macro
mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro
mmSDMA0_TLBI_GCR_CNTL = 0x0062 # macro
mmSDMA0_TLBI_GCR_CNTL_BASE_IDX = 0 # macro
mmSDMA0_TILING_CONFIG = 0x0063 # macro
mmSDMA0_TILING_CONFIG_BASE_IDX = 0 # macro
mmSDMA0_INT_STATUS = 0x0070 # macro
mmSDMA0_INT_STATUS_BASE_IDX = 0 # macro
mmSDMA0_HOLE_ADDR_LO = 0x0072 # macro
mmSDMA0_HOLE_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_HOLE_ADDR_HI = 0x0073 # macro
mmSDMA0_HOLE_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_CLOCK_GATING_REG = 0x0075 # macro
mmSDMA0_CLOCK_GATING_REG_BASE_IDX = 0 # macro
mmSDMA0_STATUS4_REG = 0x0076 # macro
mmSDMA0_STATUS4_REG_BASE_IDX = 0 # macro
mmSDMA0_SCRATCH_RAM_DATA = 0x0077 # macro
mmSDMA0_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro
mmSDMA0_SCRATCH_RAM_ADDR = 0x0078 # macro
mmSDMA0_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro
mmSDMA0_TIMESTAMP_CNTL = 0x0079 # macro
mmSDMA0_TIMESTAMP_CNTL_BASE_IDX = 0 # macro
mmSDMA0_STATUS5_REG = 0x007a # macro
mmSDMA0_STATUS5_REG_BASE_IDX = 0 # macro
mmSDMA0_QUEUE_RESET_REQ = 0x007b # macro
mmSDMA0_QUEUE_RESET_REQ_BASE_IDX = 0 # macro
mmSDMA0_GFX_RB_CNTL = 0x0080 # macro
mmSDMA0_GFX_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_GFX_RB_BASE = 0x0081 # macro
mmSDMA0_GFX_RB_BASE_BASE_IDX = 0 # macro
mmSDMA0_GFX_RB_BASE_HI = 0x0082 # macro
mmSDMA0_GFX_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_GFX_RB_RPTR = 0x0083 # macro
mmSDMA0_GFX_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_GFX_RB_RPTR_HI = 0x0084 # macro
mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_GFX_RB_WPTR = 0x0085 # macro
mmSDMA0_GFX_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA0_GFX_RB_WPTR_HI = 0x0086 # macro
mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_GFX_RB_WPTR_POLL_CNTL = 0x0087 # macro
mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_GFX_RB_RPTR_ADDR_HI = 0x0088 # macro
mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_GFX_RB_RPTR_ADDR_LO = 0x0089 # macro
mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_GFX_IB_CNTL = 0x008a # macro
mmSDMA0_GFX_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_GFX_IB_RPTR = 0x008b # macro
mmSDMA0_GFX_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_GFX_IB_OFFSET = 0x008c # macro
mmSDMA0_GFX_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_GFX_IB_BASE_LO = 0x008d # macro
mmSDMA0_GFX_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA0_GFX_IB_BASE_HI = 0x008e # macro
mmSDMA0_GFX_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_GFX_IB_SIZE = 0x008f # macro
mmSDMA0_GFX_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA0_GFX_SKIP_CNTL = 0x0090 # macro
mmSDMA0_GFX_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA0_GFX_CONTEXT_STATUS = 0x0091 # macro
mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA0_GFX_DOORBELL = 0x0092 # macro
mmSDMA0_GFX_DOORBELL_BASE_IDX = 0 # macro
mmSDMA0_GFX_CONTEXT_CNTL = 0x0093 # macro
mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX = 0 # macro
mmSDMA0_GFX_STATUS = 0x00a8 # macro
mmSDMA0_GFX_STATUS_BASE_IDX = 0 # macro
mmSDMA0_GFX_DOORBELL_LOG = 0x00a9 # macro
mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA0_GFX_WATERMARK = 0x00aa # macro
mmSDMA0_GFX_WATERMARK_BASE_IDX = 0 # macro
mmSDMA0_GFX_DOORBELL_OFFSET = 0x00ab # macro
mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_GFX_CSA_ADDR_LO = 0x00ac # macro
mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_GFX_CSA_ADDR_HI = 0x00ad # macro
mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_GFX_IB_SUB_REMAIN = 0x00af # macro
mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA0_GFX_PREEMPT = 0x00b0 # macro
mmSDMA0_GFX_PREEMPT_BASE_IDX = 0 # macro
mmSDMA0_GFX_DUMMY_REG = 0x00b1 # macro
mmSDMA0_GFX_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI = 0x00b2 # macro
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO = 0x00b3 # macro
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_GFX_RB_AQL_CNTL = 0x00b4 # macro
mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_GFX_MINOR_PTR_UPDATE = 0x00b5 # macro
mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA0_GFX_MIDCMD_DATA0 = 0x00c0 # macro
mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA0_GFX_MIDCMD_DATA1 = 0x00c1 # macro
mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA0_GFX_MIDCMD_DATA2 = 0x00c2 # macro
mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA0_GFX_MIDCMD_DATA3 = 0x00c3 # macro
mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA0_GFX_MIDCMD_DATA4 = 0x00c4 # macro
mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA0_GFX_MIDCMD_DATA5 = 0x00c5 # macro
mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA0_GFX_MIDCMD_DATA6 = 0x00c6 # macro
mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA0_GFX_MIDCMD_DATA7 = 0x00c7 # macro
mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA0_GFX_MIDCMD_DATA8 = 0x00c8 # macro
mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA0_GFX_MIDCMD_DATA9 = 0x00c9 # macro
mmSDMA0_GFX_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA0_GFX_MIDCMD_DATA10 = 0x00ca # macro
mmSDMA0_GFX_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA0_GFX_MIDCMD_CNTL = 0x00cb # macro
mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA0_PAGE_RB_CNTL = 0x00d8 # macro
mmSDMA0_PAGE_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_PAGE_RB_BASE = 0x00d9 # macro
mmSDMA0_PAGE_RB_BASE_BASE_IDX = 0 # macro
mmSDMA0_PAGE_RB_BASE_HI = 0x00da # macro
mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_PAGE_RB_RPTR = 0x00db # macro
mmSDMA0_PAGE_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_PAGE_RB_RPTR_HI = 0x00dc # macro
mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_PAGE_RB_WPTR = 0x00dd # macro
mmSDMA0_PAGE_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA0_PAGE_RB_WPTR_HI = 0x00de # macro
mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_PAGE_RB_WPTR_POLL_CNTL = 0x00df # macro
mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_PAGE_RB_RPTR_ADDR_HI = 0x00e0 # macro
mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_PAGE_RB_RPTR_ADDR_LO = 0x00e1 # macro
mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_PAGE_IB_CNTL = 0x00e2 # macro
mmSDMA0_PAGE_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_PAGE_IB_RPTR = 0x00e3 # macro
mmSDMA0_PAGE_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_PAGE_IB_OFFSET = 0x00e4 # macro
mmSDMA0_PAGE_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_PAGE_IB_BASE_LO = 0x00e5 # macro
mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA0_PAGE_IB_BASE_HI = 0x00e6 # macro
mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_PAGE_IB_SIZE = 0x00e7 # macro
mmSDMA0_PAGE_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA0_PAGE_SKIP_CNTL = 0x00e8 # macro
mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA0_PAGE_CONTEXT_STATUS = 0x00e9 # macro
mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA0_PAGE_DOORBELL = 0x00ea # macro
mmSDMA0_PAGE_DOORBELL_BASE_IDX = 0 # macro
mmSDMA0_PAGE_STATUS = 0x0100 # macro
mmSDMA0_PAGE_STATUS_BASE_IDX = 0 # macro
mmSDMA0_PAGE_DOORBELL_LOG = 0x0101 # macro
mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA0_PAGE_WATERMARK = 0x0102 # macro
mmSDMA0_PAGE_WATERMARK_BASE_IDX = 0 # macro
mmSDMA0_PAGE_DOORBELL_OFFSET = 0x0103 # macro
mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_PAGE_CSA_ADDR_LO = 0x0104 # macro
mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_PAGE_CSA_ADDR_HI = 0x0105 # macro
mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_PAGE_IB_SUB_REMAIN = 0x0107 # macro
mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA0_PAGE_PREEMPT = 0x0108 # macro
mmSDMA0_PAGE_PREEMPT_BASE_IDX = 0 # macro
mmSDMA0_PAGE_DUMMY_REG = 0x0109 # macro
mmSDMA0_PAGE_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI = 0x010a # macro
mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO = 0x010b # macro
mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_PAGE_RB_AQL_CNTL = 0x010c # macro
mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_PAGE_MINOR_PTR_UPDATE = 0x010d # macro
mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA0_PAGE_MIDCMD_DATA0 = 0x0118 # macro
mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA0_PAGE_MIDCMD_DATA1 = 0x0119 # macro
mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA0_PAGE_MIDCMD_DATA2 = 0x011a # macro
mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA0_PAGE_MIDCMD_DATA3 = 0x011b # macro
mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA0_PAGE_MIDCMD_DATA4 = 0x011c # macro
mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA0_PAGE_MIDCMD_DATA5 = 0x011d # macro
mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA0_PAGE_MIDCMD_DATA6 = 0x011e # macro
mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA0_PAGE_MIDCMD_DATA7 = 0x011f # macro
mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA0_PAGE_MIDCMD_DATA8 = 0x0120 # macro
mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA0_PAGE_MIDCMD_DATA9 = 0x0121 # macro
mmSDMA0_PAGE_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA0_PAGE_MIDCMD_DATA10 = 0x0122 # macro
mmSDMA0_PAGE_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA0_PAGE_MIDCMD_CNTL = 0x0123 # macro
mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC0_RB_CNTL = 0x0130 # macro
mmSDMA0_RLC0_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC0_RB_BASE = 0x0131 # macro
mmSDMA0_RLC0_RB_BASE_BASE_IDX = 0 # macro
mmSDMA0_RLC0_RB_BASE_HI = 0x0132 # macro
mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC0_RB_RPTR = 0x0133 # macro
mmSDMA0_RLC0_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC0_RB_RPTR_HI = 0x0134 # macro
mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC0_RB_WPTR = 0x0135 # macro
mmSDMA0_RLC0_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC0_RB_WPTR_HI = 0x0136 # macro
mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC0_RB_WPTR_POLL_CNTL = 0x0137 # macro
mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC0_RB_RPTR_ADDR_HI = 0x0138 # macro
mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC0_RB_RPTR_ADDR_LO = 0x0139 # macro
mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC0_IB_CNTL = 0x013a # macro
mmSDMA0_RLC0_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC0_IB_RPTR = 0x013b # macro
mmSDMA0_RLC0_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC0_IB_OFFSET = 0x013c # macro
mmSDMA0_RLC0_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC0_IB_BASE_LO = 0x013d # macro
mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC0_IB_BASE_HI = 0x013e # macro
mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC0_IB_SIZE = 0x013f # macro
mmSDMA0_RLC0_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA0_RLC0_SKIP_CNTL = 0x0140 # macro
mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC0_CONTEXT_STATUS = 0x0141 # macro
mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC0_DOORBELL = 0x0142 # macro
mmSDMA0_RLC0_DOORBELL_BASE_IDX = 0 # macro
mmSDMA0_RLC0_STATUS = 0x0158 # macro
mmSDMA0_RLC0_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC0_DOORBELL_LOG = 0x0159 # macro
mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA0_RLC0_WATERMARK = 0x015a # macro
mmSDMA0_RLC0_WATERMARK_BASE_IDX = 0 # macro
mmSDMA0_RLC0_DOORBELL_OFFSET = 0x015b # macro
mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC0_CSA_ADDR_LO = 0x015c # macro
mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC0_CSA_ADDR_HI = 0x015d # macro
mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC0_IB_SUB_REMAIN = 0x015f # macro
mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA0_RLC0_PREEMPT = 0x0160 # macro
mmSDMA0_RLC0_PREEMPT_BASE_IDX = 0 # macro
mmSDMA0_RLC0_DUMMY_REG = 0x0161 # macro
mmSDMA0_RLC0_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI = 0x0162 # macro
mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO = 0x0163 # macro
mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC0_RB_AQL_CNTL = 0x0164 # macro
mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC0_MINOR_PTR_UPDATE = 0x0165 # macro
mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA0_RLC0_MIDCMD_DATA0 = 0x0170 # macro
mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA0_RLC0_MIDCMD_DATA1 = 0x0171 # macro
mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA0_RLC0_MIDCMD_DATA2 = 0x0172 # macro
mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA0_RLC0_MIDCMD_DATA3 = 0x0173 # macro
mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA0_RLC0_MIDCMD_DATA4 = 0x0174 # macro
mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA0_RLC0_MIDCMD_DATA5 = 0x0175 # macro
mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA0_RLC0_MIDCMD_DATA6 = 0x0176 # macro
mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA0_RLC0_MIDCMD_DATA7 = 0x0177 # macro
mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA0_RLC0_MIDCMD_DATA8 = 0x0178 # macro
mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA0_RLC0_MIDCMD_DATA9 = 0x0179 # macro
mmSDMA0_RLC0_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA0_RLC0_MIDCMD_DATA10 = 0x017a # macro
mmSDMA0_RLC0_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA0_RLC0_MIDCMD_CNTL = 0x017b # macro
mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC1_RB_CNTL = 0x0188 # macro
mmSDMA0_RLC1_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC1_RB_BASE = 0x0189 # macro
mmSDMA0_RLC1_RB_BASE_BASE_IDX = 0 # macro
mmSDMA0_RLC1_RB_BASE_HI = 0x018a # macro
mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC1_RB_RPTR = 0x018b # macro
mmSDMA0_RLC1_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC1_RB_RPTR_HI = 0x018c # macro
mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC1_RB_WPTR = 0x018d # macro
mmSDMA0_RLC1_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC1_RB_WPTR_HI = 0x018e # macro
mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC1_RB_WPTR_POLL_CNTL = 0x018f # macro
mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC1_RB_RPTR_ADDR_HI = 0x0190 # macro
mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC1_RB_RPTR_ADDR_LO = 0x0191 # macro
mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC1_IB_CNTL = 0x0192 # macro
mmSDMA0_RLC1_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC1_IB_RPTR = 0x0193 # macro
mmSDMA0_RLC1_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC1_IB_OFFSET = 0x0194 # macro
mmSDMA0_RLC1_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC1_IB_BASE_LO = 0x0195 # macro
mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC1_IB_BASE_HI = 0x0196 # macro
mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC1_IB_SIZE = 0x0197 # macro
mmSDMA0_RLC1_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA0_RLC1_SKIP_CNTL = 0x0198 # macro
mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC1_CONTEXT_STATUS = 0x0199 # macro
mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC1_DOORBELL = 0x019a # macro
mmSDMA0_RLC1_DOORBELL_BASE_IDX = 0 # macro
mmSDMA0_RLC1_STATUS = 0x01b0 # macro
mmSDMA0_RLC1_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC1_DOORBELL_LOG = 0x01b1 # macro
mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA0_RLC1_WATERMARK = 0x01b2 # macro
mmSDMA0_RLC1_WATERMARK_BASE_IDX = 0 # macro
mmSDMA0_RLC1_DOORBELL_OFFSET = 0x01b3 # macro
mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC1_CSA_ADDR_LO = 0x01b4 # macro
mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC1_CSA_ADDR_HI = 0x01b5 # macro
mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC1_IB_SUB_REMAIN = 0x01b7 # macro
mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA0_RLC1_PREEMPT = 0x01b8 # macro
mmSDMA0_RLC1_PREEMPT_BASE_IDX = 0 # macro
mmSDMA0_RLC1_DUMMY_REG = 0x01b9 # macro
mmSDMA0_RLC1_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI = 0x01ba # macro
mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO = 0x01bb # macro
mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC1_RB_AQL_CNTL = 0x01bc # macro
mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC1_MINOR_PTR_UPDATE = 0x01bd # macro
mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA0_RLC1_MIDCMD_DATA0 = 0x01c8 # macro
mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA0_RLC1_MIDCMD_DATA1 = 0x01c9 # macro
mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA0_RLC1_MIDCMD_DATA2 = 0x01ca # macro
mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA0_RLC1_MIDCMD_DATA3 = 0x01cb # macro
mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA0_RLC1_MIDCMD_DATA4 = 0x01cc # macro
mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA0_RLC1_MIDCMD_DATA5 = 0x01cd # macro
mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA0_RLC1_MIDCMD_DATA6 = 0x01ce # macro
mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA0_RLC1_MIDCMD_DATA7 = 0x01cf # macro
mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA0_RLC1_MIDCMD_DATA8 = 0x01d0 # macro
mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA0_RLC1_MIDCMD_DATA9 = 0x01d1 # macro
mmSDMA0_RLC1_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA0_RLC1_MIDCMD_DATA10 = 0x01d2 # macro
mmSDMA0_RLC1_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA0_RLC1_MIDCMD_CNTL = 0x01d3 # macro
mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC2_RB_CNTL = 0x01e0 # macro
mmSDMA0_RLC2_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC2_RB_BASE = 0x01e1 # macro
mmSDMA0_RLC2_RB_BASE_BASE_IDX = 0 # macro
mmSDMA0_RLC2_RB_BASE_HI = 0x01e2 # macro
mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC2_RB_RPTR = 0x01e3 # macro
mmSDMA0_RLC2_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC2_RB_RPTR_HI = 0x01e4 # macro
mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC2_RB_WPTR = 0x01e5 # macro
mmSDMA0_RLC2_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC2_RB_WPTR_HI = 0x01e6 # macro
mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC2_RB_WPTR_POLL_CNTL = 0x01e7 # macro
mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC2_RB_RPTR_ADDR_HI = 0x01e8 # macro
mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC2_RB_RPTR_ADDR_LO = 0x01e9 # macro
mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC2_IB_CNTL = 0x01ea # macro
mmSDMA0_RLC2_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC2_IB_RPTR = 0x01eb # macro
mmSDMA0_RLC2_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC2_IB_OFFSET = 0x01ec # macro
mmSDMA0_RLC2_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC2_IB_BASE_LO = 0x01ed # macro
mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC2_IB_BASE_HI = 0x01ee # macro
mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC2_IB_SIZE = 0x01ef # macro
mmSDMA0_RLC2_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA0_RLC2_SKIP_CNTL = 0x01f0 # macro
mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC2_CONTEXT_STATUS = 0x01f1 # macro
mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC2_DOORBELL = 0x01f2 # macro
mmSDMA0_RLC2_DOORBELL_BASE_IDX = 0 # macro
mmSDMA0_RLC2_STATUS = 0x0208 # macro
mmSDMA0_RLC2_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC2_DOORBELL_LOG = 0x0209 # macro
mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA0_RLC2_WATERMARK = 0x020a # macro
mmSDMA0_RLC2_WATERMARK_BASE_IDX = 0 # macro
mmSDMA0_RLC2_DOORBELL_OFFSET = 0x020b # macro
mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC2_CSA_ADDR_LO = 0x020c # macro
mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC2_CSA_ADDR_HI = 0x020d # macro
mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC2_IB_SUB_REMAIN = 0x020f # macro
mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA0_RLC2_PREEMPT = 0x0210 # macro
mmSDMA0_RLC2_PREEMPT_BASE_IDX = 0 # macro
mmSDMA0_RLC2_DUMMY_REG = 0x0211 # macro
mmSDMA0_RLC2_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI = 0x0212 # macro
mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO = 0x0213 # macro
mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC2_RB_AQL_CNTL = 0x0214 # macro
mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC2_MINOR_PTR_UPDATE = 0x0215 # macro
mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA0_RLC2_MIDCMD_DATA0 = 0x0220 # macro
mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA0_RLC2_MIDCMD_DATA1 = 0x0221 # macro
mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA0_RLC2_MIDCMD_DATA2 = 0x0222 # macro
mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA0_RLC2_MIDCMD_DATA3 = 0x0223 # macro
mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA0_RLC2_MIDCMD_DATA4 = 0x0224 # macro
mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA0_RLC2_MIDCMD_DATA5 = 0x0225 # macro
mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA0_RLC2_MIDCMD_DATA6 = 0x0226 # macro
mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA0_RLC2_MIDCMD_DATA7 = 0x0227 # macro
mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA0_RLC2_MIDCMD_DATA8 = 0x0228 # macro
mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA0_RLC2_MIDCMD_DATA9 = 0x0229 # macro
mmSDMA0_RLC2_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA0_RLC2_MIDCMD_DATA10 = 0x022a # macro
mmSDMA0_RLC2_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA0_RLC2_MIDCMD_CNTL = 0x022b # macro
mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC3_RB_CNTL = 0x0238 # macro
mmSDMA0_RLC3_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC3_RB_BASE = 0x0239 # macro
mmSDMA0_RLC3_RB_BASE_BASE_IDX = 0 # macro
mmSDMA0_RLC3_RB_BASE_HI = 0x023a # macro
mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC3_RB_RPTR = 0x023b # macro
mmSDMA0_RLC3_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC3_RB_RPTR_HI = 0x023c # macro
mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC3_RB_WPTR = 0x023d # macro
mmSDMA0_RLC3_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC3_RB_WPTR_HI = 0x023e # macro
mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC3_RB_WPTR_POLL_CNTL = 0x023f # macro
mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC3_RB_RPTR_ADDR_HI = 0x0240 # macro
mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC3_RB_RPTR_ADDR_LO = 0x0241 # macro
mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC3_IB_CNTL = 0x0242 # macro
mmSDMA0_RLC3_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC3_IB_RPTR = 0x0243 # macro
mmSDMA0_RLC3_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC3_IB_OFFSET = 0x0244 # macro
mmSDMA0_RLC3_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC3_IB_BASE_LO = 0x0245 # macro
mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC3_IB_BASE_HI = 0x0246 # macro
mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC3_IB_SIZE = 0x0247 # macro
mmSDMA0_RLC3_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA0_RLC3_SKIP_CNTL = 0x0248 # macro
mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC3_CONTEXT_STATUS = 0x0249 # macro
mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC3_DOORBELL = 0x024a # macro
mmSDMA0_RLC3_DOORBELL_BASE_IDX = 0 # macro
mmSDMA0_RLC3_STATUS = 0x0260 # macro
mmSDMA0_RLC3_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC3_DOORBELL_LOG = 0x0261 # macro
mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA0_RLC3_WATERMARK = 0x0262 # macro
mmSDMA0_RLC3_WATERMARK_BASE_IDX = 0 # macro
mmSDMA0_RLC3_DOORBELL_OFFSET = 0x0263 # macro
mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC3_CSA_ADDR_LO = 0x0264 # macro
mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC3_CSA_ADDR_HI = 0x0265 # macro
mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC3_IB_SUB_REMAIN = 0x0267 # macro
mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA0_RLC3_PREEMPT = 0x0268 # macro
mmSDMA0_RLC3_PREEMPT_BASE_IDX = 0 # macro
mmSDMA0_RLC3_DUMMY_REG = 0x0269 # macro
mmSDMA0_RLC3_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI = 0x026a # macro
mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO = 0x026b # macro
mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC3_RB_AQL_CNTL = 0x026c # macro
mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC3_MINOR_PTR_UPDATE = 0x026d # macro
mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA0_RLC3_MIDCMD_DATA0 = 0x0278 # macro
mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA0_RLC3_MIDCMD_DATA1 = 0x0279 # macro
mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA0_RLC3_MIDCMD_DATA2 = 0x027a # macro
mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA0_RLC3_MIDCMD_DATA3 = 0x027b # macro
mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA0_RLC3_MIDCMD_DATA4 = 0x027c # macro
mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA0_RLC3_MIDCMD_DATA5 = 0x027d # macro
mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA0_RLC3_MIDCMD_DATA6 = 0x027e # macro
mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA0_RLC3_MIDCMD_DATA7 = 0x027f # macro
mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA0_RLC3_MIDCMD_DATA8 = 0x0280 # macro
mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA0_RLC3_MIDCMD_DATA9 = 0x0281 # macro
mmSDMA0_RLC3_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA0_RLC3_MIDCMD_DATA10 = 0x0282 # macro
mmSDMA0_RLC3_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA0_RLC3_MIDCMD_CNTL = 0x0283 # macro
mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC4_RB_CNTL = 0x0290 # macro
mmSDMA0_RLC4_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC4_RB_BASE = 0x0291 # macro
mmSDMA0_RLC4_RB_BASE_BASE_IDX = 0 # macro
mmSDMA0_RLC4_RB_BASE_HI = 0x0292 # macro
mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC4_RB_RPTR = 0x0293 # macro
mmSDMA0_RLC4_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC4_RB_RPTR_HI = 0x0294 # macro
mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC4_RB_WPTR = 0x0295 # macro
mmSDMA0_RLC4_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC4_RB_WPTR_HI = 0x0296 # macro
mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC4_RB_WPTR_POLL_CNTL = 0x0297 # macro
mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC4_RB_RPTR_ADDR_HI = 0x0298 # macro
mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC4_RB_RPTR_ADDR_LO = 0x0299 # macro
mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC4_IB_CNTL = 0x029a # macro
mmSDMA0_RLC4_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC4_IB_RPTR = 0x029b # macro
mmSDMA0_RLC4_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC4_IB_OFFSET = 0x029c # macro
mmSDMA0_RLC4_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC4_IB_BASE_LO = 0x029d # macro
mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC4_IB_BASE_HI = 0x029e # macro
mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC4_IB_SIZE = 0x029f # macro
mmSDMA0_RLC4_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA0_RLC4_SKIP_CNTL = 0x02a0 # macro
mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC4_CONTEXT_STATUS = 0x02a1 # macro
mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC4_DOORBELL = 0x02a2 # macro
mmSDMA0_RLC4_DOORBELL_BASE_IDX = 0 # macro
mmSDMA0_RLC4_STATUS = 0x02b8 # macro
mmSDMA0_RLC4_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC4_DOORBELL_LOG = 0x02b9 # macro
mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA0_RLC4_WATERMARK = 0x02ba # macro
mmSDMA0_RLC4_WATERMARK_BASE_IDX = 0 # macro
mmSDMA0_RLC4_DOORBELL_OFFSET = 0x02bb # macro
mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC4_CSA_ADDR_LO = 0x02bc # macro
mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC4_CSA_ADDR_HI = 0x02bd # macro
mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC4_IB_SUB_REMAIN = 0x02bf # macro
mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA0_RLC4_PREEMPT = 0x02c0 # macro
mmSDMA0_RLC4_PREEMPT_BASE_IDX = 0 # macro
mmSDMA0_RLC4_DUMMY_REG = 0x02c1 # macro
mmSDMA0_RLC4_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI = 0x02c2 # macro
mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO = 0x02c3 # macro
mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC4_RB_AQL_CNTL = 0x02c4 # macro
mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC4_MINOR_PTR_UPDATE = 0x02c5 # macro
mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA0_RLC4_MIDCMD_DATA0 = 0x02d0 # macro
mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA0_RLC4_MIDCMD_DATA1 = 0x02d1 # macro
mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA0_RLC4_MIDCMD_DATA2 = 0x02d2 # macro
mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA0_RLC4_MIDCMD_DATA3 = 0x02d3 # macro
mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA0_RLC4_MIDCMD_DATA4 = 0x02d4 # macro
mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA0_RLC4_MIDCMD_DATA5 = 0x02d5 # macro
mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA0_RLC4_MIDCMD_DATA6 = 0x02d6 # macro
mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA0_RLC4_MIDCMD_DATA7 = 0x02d7 # macro
mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA0_RLC4_MIDCMD_DATA8 = 0x02d8 # macro
mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA0_RLC4_MIDCMD_DATA9 = 0x02d9 # macro
mmSDMA0_RLC4_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA0_RLC4_MIDCMD_DATA10 = 0x02da # macro
mmSDMA0_RLC4_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA0_RLC4_MIDCMD_CNTL = 0x02db # macro
mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC5_RB_CNTL = 0x02e8 # macro
mmSDMA0_RLC5_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC5_RB_BASE = 0x02e9 # macro
mmSDMA0_RLC5_RB_BASE_BASE_IDX = 0 # macro
mmSDMA0_RLC5_RB_BASE_HI = 0x02ea # macro
mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC5_RB_RPTR = 0x02eb # macro
mmSDMA0_RLC5_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC5_RB_RPTR_HI = 0x02ec # macro
mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC5_RB_WPTR = 0x02ed # macro
mmSDMA0_RLC5_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC5_RB_WPTR_HI = 0x02ee # macro
mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC5_RB_WPTR_POLL_CNTL = 0x02ef # macro
mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC5_RB_RPTR_ADDR_HI = 0x02f0 # macro
mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC5_RB_RPTR_ADDR_LO = 0x02f1 # macro
mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC5_IB_CNTL = 0x02f2 # macro
mmSDMA0_RLC5_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC5_IB_RPTR = 0x02f3 # macro
mmSDMA0_RLC5_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC5_IB_OFFSET = 0x02f4 # macro
mmSDMA0_RLC5_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC5_IB_BASE_LO = 0x02f5 # macro
mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC5_IB_BASE_HI = 0x02f6 # macro
mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC5_IB_SIZE = 0x02f7 # macro
mmSDMA0_RLC5_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA0_RLC5_SKIP_CNTL = 0x02f8 # macro
mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC5_CONTEXT_STATUS = 0x02f9 # macro
mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC5_DOORBELL = 0x02fa # macro
mmSDMA0_RLC5_DOORBELL_BASE_IDX = 0 # macro
mmSDMA0_RLC5_STATUS = 0x0310 # macro
mmSDMA0_RLC5_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC5_DOORBELL_LOG = 0x0311 # macro
mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA0_RLC5_WATERMARK = 0x0312 # macro
mmSDMA0_RLC5_WATERMARK_BASE_IDX = 0 # macro
mmSDMA0_RLC5_DOORBELL_OFFSET = 0x0313 # macro
mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC5_CSA_ADDR_LO = 0x0314 # macro
mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC5_CSA_ADDR_HI = 0x0315 # macro
mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC5_IB_SUB_REMAIN = 0x0317 # macro
mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA0_RLC5_PREEMPT = 0x0318 # macro
mmSDMA0_RLC5_PREEMPT_BASE_IDX = 0 # macro
mmSDMA0_RLC5_DUMMY_REG = 0x0319 # macro
mmSDMA0_RLC5_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI = 0x031a # macro
mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO = 0x031b # macro
mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC5_RB_AQL_CNTL = 0x031c # macro
mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC5_MINOR_PTR_UPDATE = 0x031d # macro
mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA0_RLC5_MIDCMD_DATA0 = 0x0328 # macro
mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA0_RLC5_MIDCMD_DATA1 = 0x0329 # macro
mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA0_RLC5_MIDCMD_DATA2 = 0x032a # macro
mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA0_RLC5_MIDCMD_DATA3 = 0x032b # macro
mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA0_RLC5_MIDCMD_DATA4 = 0x032c # macro
mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA0_RLC5_MIDCMD_DATA5 = 0x032d # macro
mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA0_RLC5_MIDCMD_DATA6 = 0x032e # macro
mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA0_RLC5_MIDCMD_DATA7 = 0x032f # macro
mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA0_RLC5_MIDCMD_DATA8 = 0x0330 # macro
mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA0_RLC5_MIDCMD_DATA9 = 0x0331 # macro
mmSDMA0_RLC5_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA0_RLC5_MIDCMD_DATA10 = 0x0332 # macro
mmSDMA0_RLC5_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA0_RLC5_MIDCMD_CNTL = 0x0333 # macro
mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC6_RB_CNTL = 0x0340 # macro
mmSDMA0_RLC6_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC6_RB_BASE = 0x0341 # macro
mmSDMA0_RLC6_RB_BASE_BASE_IDX = 0 # macro
mmSDMA0_RLC6_RB_BASE_HI = 0x0342 # macro
mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC6_RB_RPTR = 0x0343 # macro
mmSDMA0_RLC6_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC6_RB_RPTR_HI = 0x0344 # macro
mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC6_RB_WPTR = 0x0345 # macro
mmSDMA0_RLC6_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC6_RB_WPTR_HI = 0x0346 # macro
mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC6_RB_WPTR_POLL_CNTL = 0x0347 # macro
mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC6_RB_RPTR_ADDR_HI = 0x0348 # macro
mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC6_RB_RPTR_ADDR_LO = 0x0349 # macro
mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC6_IB_CNTL = 0x034a # macro
mmSDMA0_RLC6_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC6_IB_RPTR = 0x034b # macro
mmSDMA0_RLC6_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC6_IB_OFFSET = 0x034c # macro
mmSDMA0_RLC6_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC6_IB_BASE_LO = 0x034d # macro
mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC6_IB_BASE_HI = 0x034e # macro
mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC6_IB_SIZE = 0x034f # macro
mmSDMA0_RLC6_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA0_RLC6_SKIP_CNTL = 0x0350 # macro
mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC6_CONTEXT_STATUS = 0x0351 # macro
mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC6_DOORBELL = 0x0352 # macro
mmSDMA0_RLC6_DOORBELL_BASE_IDX = 0 # macro
mmSDMA0_RLC6_STATUS = 0x0368 # macro
mmSDMA0_RLC6_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC6_DOORBELL_LOG = 0x0369 # macro
mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA0_RLC6_WATERMARK = 0x036a # macro
mmSDMA0_RLC6_WATERMARK_BASE_IDX = 0 # macro
mmSDMA0_RLC6_DOORBELL_OFFSET = 0x036b # macro
mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC6_CSA_ADDR_LO = 0x036c # macro
mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC6_CSA_ADDR_HI = 0x036d # macro
mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC6_IB_SUB_REMAIN = 0x036f # macro
mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA0_RLC6_PREEMPT = 0x0370 # macro
mmSDMA0_RLC6_PREEMPT_BASE_IDX = 0 # macro
mmSDMA0_RLC6_DUMMY_REG = 0x0371 # macro
mmSDMA0_RLC6_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI = 0x0372 # macro
mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO = 0x0373 # macro
mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC6_RB_AQL_CNTL = 0x0374 # macro
mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC6_MINOR_PTR_UPDATE = 0x0375 # macro
mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA0_RLC6_MIDCMD_DATA0 = 0x0380 # macro
mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA0_RLC6_MIDCMD_DATA1 = 0x0381 # macro
mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA0_RLC6_MIDCMD_DATA2 = 0x0382 # macro
mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA0_RLC6_MIDCMD_DATA3 = 0x0383 # macro
mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA0_RLC6_MIDCMD_DATA4 = 0x0384 # macro
mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA0_RLC6_MIDCMD_DATA5 = 0x0385 # macro
mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA0_RLC6_MIDCMD_DATA6 = 0x0386 # macro
mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA0_RLC6_MIDCMD_DATA7 = 0x0387 # macro
mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA0_RLC6_MIDCMD_DATA8 = 0x0388 # macro
mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA0_RLC6_MIDCMD_DATA9 = 0x0389 # macro
mmSDMA0_RLC6_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA0_RLC6_MIDCMD_DATA10 = 0x038a # macro
mmSDMA0_RLC6_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA0_RLC6_MIDCMD_CNTL = 0x038b # macro
mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC7_RB_CNTL = 0x0398 # macro
mmSDMA0_RLC7_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC7_RB_BASE = 0x0399 # macro
mmSDMA0_RLC7_RB_BASE_BASE_IDX = 0 # macro
mmSDMA0_RLC7_RB_BASE_HI = 0x039a # macro
mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC7_RB_RPTR = 0x039b # macro
mmSDMA0_RLC7_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC7_RB_RPTR_HI = 0x039c # macro
mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC7_RB_WPTR = 0x039d # macro
mmSDMA0_RLC7_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC7_RB_WPTR_HI = 0x039e # macro
mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC7_RB_WPTR_POLL_CNTL = 0x039f # macro
mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC7_RB_RPTR_ADDR_HI = 0x03a0 # macro
mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC7_RB_RPTR_ADDR_LO = 0x03a1 # macro
mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC7_IB_CNTL = 0x03a2 # macro
mmSDMA0_RLC7_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC7_IB_RPTR = 0x03a3 # macro
mmSDMA0_RLC7_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA0_RLC7_IB_OFFSET = 0x03a4 # macro
mmSDMA0_RLC7_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC7_IB_BASE_LO = 0x03a5 # macro
mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC7_IB_BASE_HI = 0x03a6 # macro
mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC7_IB_SIZE = 0x03a7 # macro
mmSDMA0_RLC7_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA0_RLC7_SKIP_CNTL = 0x03a8 # macro
mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC7_CONTEXT_STATUS = 0x03a9 # macro
mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC7_DOORBELL = 0x03aa # macro
mmSDMA0_RLC7_DOORBELL_BASE_IDX = 0 # macro
mmSDMA0_RLC7_STATUS = 0x03c0 # macro
mmSDMA0_RLC7_STATUS_BASE_IDX = 0 # macro
mmSDMA0_RLC7_DOORBELL_LOG = 0x03c1 # macro
mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA0_RLC7_WATERMARK = 0x03c2 # macro
mmSDMA0_RLC7_WATERMARK_BASE_IDX = 0 # macro
mmSDMA0_RLC7_DOORBELL_OFFSET = 0x03c3 # macro
mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA0_RLC7_CSA_ADDR_LO = 0x03c4 # macro
mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC7_CSA_ADDR_HI = 0x03c5 # macro
mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC7_IB_SUB_REMAIN = 0x03c7 # macro
mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA0_RLC7_PREEMPT = 0x03c8 # macro
mmSDMA0_RLC7_PREEMPT_BASE_IDX = 0 # macro
mmSDMA0_RLC7_DUMMY_REG = 0x03c9 # macro
mmSDMA0_RLC7_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI = 0x03ca # macro
mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO = 0x03cb # macro
mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA0_RLC7_RB_AQL_CNTL = 0x03cc # macro
mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA0_RLC7_MINOR_PTR_UPDATE = 0x03cd # macro
mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA0_RLC7_MIDCMD_DATA0 = 0x03d8 # macro
mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA0_RLC7_MIDCMD_DATA1 = 0x03d9 # macro
mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA0_RLC7_MIDCMD_DATA2 = 0x03da # macro
mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA0_RLC7_MIDCMD_DATA3 = 0x03db # macro
mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA0_RLC7_MIDCMD_DATA4 = 0x03dc # macro
mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA0_RLC7_MIDCMD_DATA5 = 0x03dd # macro
mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA0_RLC7_MIDCMD_DATA6 = 0x03de # macro
mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA0_RLC7_MIDCMD_DATA7 = 0x03df # macro
mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA0_RLC7_MIDCMD_DATA8 = 0x03e0 # macro
mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA0_RLC7_MIDCMD_DATA9 = 0x03e1 # macro
mmSDMA0_RLC7_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA0_RLC7_MIDCMD_DATA10 = 0x03e2 # macro
mmSDMA0_RLC7_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA0_RLC7_MIDCMD_CNTL = 0x03e3 # macro
mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA1_DEC_START = 0x0600 # macro
mmSDMA1_DEC_START_BASE_IDX = 0 # macro
mmSDMA1_GLOBAL_TIMESTAMP_LO = 0x060f # macro
mmSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro
mmSDMA1_GLOBAL_TIMESTAMP_HI = 0x0610 # macro
mmSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro
mmSDMA1_PG_CNTL = 0x0616 # macro
mmSDMA1_PG_CNTL_BASE_IDX = 0 # macro
mmSDMA1_PG_CTX_LO = 0x0617 # macro
mmSDMA1_PG_CTX_LO_BASE_IDX = 0 # macro
mmSDMA1_PG_CTX_HI = 0x0618 # macro
mmSDMA1_PG_CTX_HI_BASE_IDX = 0 # macro
mmSDMA1_PG_CTX_CNTL = 0x0619 # macro
mmSDMA1_PG_CTX_CNTL_BASE_IDX = 0 # macro
mmSDMA1_POWER_CNTL = 0x061a # macro
mmSDMA1_POWER_CNTL_BASE_IDX = 0 # macro
mmSDMA1_CLK_CTRL = 0x061b # macro
mmSDMA1_CLK_CTRL_BASE_IDX = 0 # macro
mmSDMA1_CNTL = 0x061c # macro
mmSDMA1_CNTL_BASE_IDX = 0 # macro
mmSDMA1_CHICKEN_BITS = 0x061d # macro
mmSDMA1_CHICKEN_BITS_BASE_IDX = 0 # macro
mmSDMA1_GB_ADDR_CONFIG = 0x061e # macro
mmSDMA1_GB_ADDR_CONFIG_BASE_IDX = 0 # macro
mmSDMA1_GB_ADDR_CONFIG_READ = 0x061f # macro
mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro
mmSDMA1_RB_RPTR_FETCH_HI = 0x0620 # macro
mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro
mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL = 0x0621 # macro
mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RB_RPTR_FETCH = 0x0622 # macro
mmSDMA1_RB_RPTR_FETCH_BASE_IDX = 0 # macro
mmSDMA1_IB_OFFSET_FETCH = 0x0623 # macro
mmSDMA1_IB_OFFSET_FETCH_BASE_IDX = 0 # macro
mmSDMA1_PROGRAM = 0x0624 # macro
mmSDMA1_PROGRAM_BASE_IDX = 0 # macro
mmSDMA1_STATUS_REG = 0x0625 # macro
mmSDMA1_STATUS_REG_BASE_IDX = 0 # macro
mmSDMA1_STATUS1_REG = 0x0626 # macro
mmSDMA1_STATUS1_REG_BASE_IDX = 0 # macro
mmSDMA1_RD_BURST_CNTL = 0x0627 # macro
mmSDMA1_RD_BURST_CNTL_BASE_IDX = 0 # macro
mmSDMA1_HBM_PAGE_CONFIG = 0x0628 # macro
mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro
mmSDMA1_UCODE_CHECKSUM = 0x0629 # macro
mmSDMA1_UCODE_CHECKSUM_BASE_IDX = 0 # macro
mmSDMA1_F32_CNTL = 0x062a # macro
mmSDMA1_F32_CNTL_BASE_IDX = 0 # macro
mmSDMA1_FREEZE = 0x062b # macro
mmSDMA1_FREEZE_BASE_IDX = 0 # macro
mmSDMA1_PHASE0_QUANTUM = 0x062c # macro
mmSDMA1_PHASE0_QUANTUM_BASE_IDX = 0 # macro
mmSDMA1_PHASE1_QUANTUM = 0x062d # macro
mmSDMA1_PHASE1_QUANTUM_BASE_IDX = 0 # macro
mmSDMA1_EDC_CONFIG = 0x0632 # macro
mmSDMA1_EDC_CONFIG_BASE_IDX = 0 # macro
mmSDMA1_BA_THRESHOLD = 0x0633 # macro
mmSDMA1_BA_THRESHOLD_BASE_IDX = 0 # macro
mmSDMA1_ID = 0x0634 # macro
mmSDMA1_ID_BASE_IDX = 0 # macro
mmSDMA1_VERSION = 0x0635 # macro
mmSDMA1_VERSION_BASE_IDX = 0 # macro
mmSDMA1_EDC_COUNTER = 0x0636 # macro
mmSDMA1_EDC_COUNTER_BASE_IDX = 0 # macro
mmSDMA1_EDC_COUNTER_CLEAR = 0x0637 # macro
mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro
mmSDMA1_STATUS2_REG = 0x0638 # macro
mmSDMA1_STATUS2_REG_BASE_IDX = 0 # macro
mmSDMA1_ATOMIC_CNTL = 0x0639 # macro
mmSDMA1_ATOMIC_CNTL_BASE_IDX = 0 # macro
mmSDMA1_ATOMIC_PREOP_LO = 0x063a # macro
mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro
mmSDMA1_ATOMIC_PREOP_HI = 0x063b # macro
mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro
mmSDMA1_UTCL1_CNTL = 0x063c # macro
mmSDMA1_UTCL1_CNTL_BASE_IDX = 0 # macro
mmSDMA1_UTCL1_WATERMK = 0x063d # macro
mmSDMA1_UTCL1_WATERMK_BASE_IDX = 0 # macro
mmSDMA1_UTCL1_RD_STATUS = 0x063e # macro
mmSDMA1_UTCL1_RD_STATUS_BASE_IDX = 0 # macro
mmSDMA1_UTCL1_WR_STATUS = 0x063f # macro
mmSDMA1_UTCL1_WR_STATUS_BASE_IDX = 0 # macro
mmSDMA1_UTCL1_INV0 = 0x0640 # macro
mmSDMA1_UTCL1_INV0_BASE_IDX = 0 # macro
mmSDMA1_UTCL1_INV1 = 0x0641 # macro
mmSDMA1_UTCL1_INV1_BASE_IDX = 0 # macro
mmSDMA1_UTCL1_INV2 = 0x0642 # macro
mmSDMA1_UTCL1_INV2_BASE_IDX = 0 # macro
mmSDMA1_UTCL1_RD_XNACK0 = 0x0643 # macro
mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro
mmSDMA1_UTCL1_RD_XNACK1 = 0x0644 # macro
mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro
mmSDMA1_UTCL1_WR_XNACK0 = 0x0645 # macro
mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro
mmSDMA1_UTCL1_WR_XNACK1 = 0x0646 # macro
mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro
mmSDMA1_UTCL1_TIMEOUT = 0x0647 # macro
mmSDMA1_UTCL1_TIMEOUT_BASE_IDX = 0 # macro
mmSDMA1_UTCL1_PAGE = 0x0648 # macro
mmSDMA1_UTCL1_PAGE_BASE_IDX = 0 # macro
mmSDMA1_RELAX_ORDERING_LUT = 0x064a # macro
mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro
mmSDMA1_CHICKEN_BITS_2 = 0x064b # macro
mmSDMA1_CHICKEN_BITS_2_BASE_IDX = 0 # macro
mmSDMA1_STATUS3_REG = 0x064c # macro
mmSDMA1_STATUS3_REG_BASE_IDX = 0 # macro
mmSDMA1_PHYSICAL_ADDR_LO = 0x064d # macro
mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_PHYSICAL_ADDR_HI = 0x064e # macro
mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_PHASE2_QUANTUM = 0x064f # macro
mmSDMA1_PHASE2_QUANTUM_BASE_IDX = 0 # macro
mmSDMA1_ERROR_LOG = 0x0650 # macro
mmSDMA1_ERROR_LOG_BASE_IDX = 0 # macro
mmSDMA1_PUB_DUMMY_REG0 = 0x0651 # macro
mmSDMA1_PUB_DUMMY_REG0_BASE_IDX = 0 # macro
mmSDMA1_PUB_DUMMY_REG1 = 0x0652 # macro
mmSDMA1_PUB_DUMMY_REG1_BASE_IDX = 0 # macro
mmSDMA1_PUB_DUMMY_REG2 = 0x0653 # macro
mmSDMA1_PUB_DUMMY_REG2_BASE_IDX = 0 # macro
mmSDMA1_PUB_DUMMY_REG3 = 0x0654 # macro
mmSDMA1_PUB_DUMMY_REG3_BASE_IDX = 0 # macro
mmSDMA1_F32_COUNTER = 0x0655 # macro
mmSDMA1_F32_COUNTER_BASE_IDX = 0 # macro
mmSDMA1_CRD_CNTL = 0x065b # macro
mmSDMA1_CRD_CNTL_BASE_IDX = 0 # macro
mmSDMA1_AQL_STATUS = 0x065f # macro
mmSDMA1_AQL_STATUS_BASE_IDX = 0 # macro
mmSDMA1_EA_DBIT_ADDR_DATA = 0x0660 # macro
mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro
mmSDMA1_EA_DBIT_ADDR_INDEX = 0x0661 # macro
mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro
mmSDMA1_TLBI_GCR_CNTL = 0x0662 # macro
mmSDMA1_TLBI_GCR_CNTL_BASE_IDX = 0 # macro
mmSDMA1_TILING_CONFIG = 0x0663 # macro
mmSDMA1_TILING_CONFIG_BASE_IDX = 0 # macro
mmSDMA1_INT_STATUS = 0x0670 # macro
mmSDMA1_INT_STATUS_BASE_IDX = 0 # macro
mmSDMA1_HOLE_ADDR_LO = 0x0672 # macro
mmSDMA1_HOLE_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_HOLE_ADDR_HI = 0x0673 # macro
mmSDMA1_HOLE_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_CLOCK_GATING_REG = 0x0675 # macro
mmSDMA1_CLOCK_GATING_REG_BASE_IDX = 0 # macro
mmSDMA1_STATUS4_REG = 0x0676 # macro
mmSDMA1_STATUS4_REG_BASE_IDX = 0 # macro
mmSDMA1_SCRATCH_RAM_DATA = 0x0677 # macro
mmSDMA1_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro
mmSDMA1_SCRATCH_RAM_ADDR = 0x0678 # macro
mmSDMA1_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro
mmSDMA1_TIMESTAMP_CNTL = 0x0679 # macro
mmSDMA1_TIMESTAMP_CNTL_BASE_IDX = 0 # macro
mmSDMA1_STATUS5_REG = 0x067a # macro
mmSDMA1_STATUS5_REG_BASE_IDX = 0 # macro
mmSDMA1_QUEUE_RESET_REQ = 0x067b # macro
mmSDMA1_QUEUE_RESET_REQ_BASE_IDX = 0 # macro
mmSDMA1_GFX_RB_CNTL = 0x0680 # macro
mmSDMA1_GFX_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_GFX_RB_BASE = 0x0681 # macro
mmSDMA1_GFX_RB_BASE_BASE_IDX = 0 # macro
mmSDMA1_GFX_RB_BASE_HI = 0x0682 # macro
mmSDMA1_GFX_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_GFX_RB_RPTR = 0x0683 # macro
mmSDMA1_GFX_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_GFX_RB_RPTR_HI = 0x0684 # macro
mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_GFX_RB_WPTR = 0x0685 # macro
mmSDMA1_GFX_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA1_GFX_RB_WPTR_HI = 0x0686 # macro
mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_GFX_RB_WPTR_POLL_CNTL = 0x0687 # macro
mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_GFX_RB_RPTR_ADDR_HI = 0x0688 # macro
mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_GFX_RB_RPTR_ADDR_LO = 0x0689 # macro
mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_GFX_IB_CNTL = 0x068a # macro
mmSDMA1_GFX_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_GFX_IB_RPTR = 0x068b # macro
mmSDMA1_GFX_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_GFX_IB_OFFSET = 0x068c # macro
mmSDMA1_GFX_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_GFX_IB_BASE_LO = 0x068d # macro
mmSDMA1_GFX_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA1_GFX_IB_BASE_HI = 0x068e # macro
mmSDMA1_GFX_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_GFX_IB_SIZE = 0x068f # macro
mmSDMA1_GFX_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA1_GFX_SKIP_CNTL = 0x0690 # macro
mmSDMA1_GFX_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA1_GFX_CONTEXT_STATUS = 0x0691 # macro
mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA1_GFX_DOORBELL = 0x0692 # macro
mmSDMA1_GFX_DOORBELL_BASE_IDX = 0 # macro
mmSDMA1_GFX_CONTEXT_CNTL = 0x0693 # macro
mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX = 0 # macro
mmSDMA1_GFX_STATUS = 0x06a8 # macro
mmSDMA1_GFX_STATUS_BASE_IDX = 0 # macro
mmSDMA1_GFX_DOORBELL_LOG = 0x06a9 # macro
mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA1_GFX_WATERMARK = 0x06aa # macro
mmSDMA1_GFX_WATERMARK_BASE_IDX = 0 # macro
mmSDMA1_GFX_DOORBELL_OFFSET = 0x06ab # macro
mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_GFX_CSA_ADDR_LO = 0x06ac # macro
mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_GFX_CSA_ADDR_HI = 0x06ad # macro
mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_GFX_IB_SUB_REMAIN = 0x06af # macro
mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA1_GFX_PREEMPT = 0x06b0 # macro
mmSDMA1_GFX_PREEMPT_BASE_IDX = 0 # macro
mmSDMA1_GFX_DUMMY_REG = 0x06b1 # macro
mmSDMA1_GFX_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI = 0x06b2 # macro
mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO = 0x06b3 # macro
mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_GFX_RB_AQL_CNTL = 0x06b4 # macro
mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_GFX_MINOR_PTR_UPDATE = 0x06b5 # macro
mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA1_GFX_MIDCMD_DATA0 = 0x06c0 # macro
mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA1_GFX_MIDCMD_DATA1 = 0x06c1 # macro
mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA1_GFX_MIDCMD_DATA2 = 0x06c2 # macro
mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA1_GFX_MIDCMD_DATA3 = 0x06c3 # macro
mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA1_GFX_MIDCMD_DATA4 = 0x06c4 # macro
mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA1_GFX_MIDCMD_DATA5 = 0x06c5 # macro
mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA1_GFX_MIDCMD_DATA6 = 0x06c6 # macro
mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA1_GFX_MIDCMD_DATA7 = 0x06c7 # macro
mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA1_GFX_MIDCMD_DATA8 = 0x06c8 # macro
mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA1_GFX_MIDCMD_DATA9 = 0x06c9 # macro
mmSDMA1_GFX_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA1_GFX_MIDCMD_DATA10 = 0x06ca # macro
mmSDMA1_GFX_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA1_GFX_MIDCMD_CNTL = 0x06cb # macro
mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA1_PAGE_RB_CNTL = 0x06d8 # macro
mmSDMA1_PAGE_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_PAGE_RB_BASE = 0x06d9 # macro
mmSDMA1_PAGE_RB_BASE_BASE_IDX = 0 # macro
mmSDMA1_PAGE_RB_BASE_HI = 0x06da # macro
mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_PAGE_RB_RPTR = 0x06db # macro
mmSDMA1_PAGE_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_PAGE_RB_RPTR_HI = 0x06dc # macro
mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_PAGE_RB_WPTR = 0x06dd # macro
mmSDMA1_PAGE_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA1_PAGE_RB_WPTR_HI = 0x06de # macro
mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_PAGE_RB_WPTR_POLL_CNTL = 0x06df # macro
mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_PAGE_RB_RPTR_ADDR_HI = 0x06e0 # macro
mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_PAGE_RB_RPTR_ADDR_LO = 0x06e1 # macro
mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_PAGE_IB_CNTL = 0x06e2 # macro
mmSDMA1_PAGE_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_PAGE_IB_RPTR = 0x06e3 # macro
mmSDMA1_PAGE_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_PAGE_IB_OFFSET = 0x06e4 # macro
mmSDMA1_PAGE_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_PAGE_IB_BASE_LO = 0x06e5 # macro
mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA1_PAGE_IB_BASE_HI = 0x06e6 # macro
mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_PAGE_IB_SIZE = 0x06e7 # macro
mmSDMA1_PAGE_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA1_PAGE_SKIP_CNTL = 0x06e8 # macro
mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA1_PAGE_CONTEXT_STATUS = 0x06e9 # macro
mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA1_PAGE_DOORBELL = 0x06ea # macro
mmSDMA1_PAGE_DOORBELL_BASE_IDX = 0 # macro
mmSDMA1_PAGE_STATUS = 0x0700 # macro
mmSDMA1_PAGE_STATUS_BASE_IDX = 0 # macro
mmSDMA1_PAGE_DOORBELL_LOG = 0x0701 # macro
mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA1_PAGE_WATERMARK = 0x0702 # macro
mmSDMA1_PAGE_WATERMARK_BASE_IDX = 0 # macro
mmSDMA1_PAGE_DOORBELL_OFFSET = 0x0703 # macro
mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_PAGE_CSA_ADDR_LO = 0x0704 # macro
mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_PAGE_CSA_ADDR_HI = 0x0705 # macro
mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_PAGE_IB_SUB_REMAIN = 0x0707 # macro
mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA1_PAGE_PREEMPT = 0x0708 # macro
mmSDMA1_PAGE_PREEMPT_BASE_IDX = 0 # macro
mmSDMA1_PAGE_DUMMY_REG = 0x0709 # macro
mmSDMA1_PAGE_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI = 0x070a # macro
mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO = 0x070b # macro
mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_PAGE_RB_AQL_CNTL = 0x070c # macro
mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_PAGE_MINOR_PTR_UPDATE = 0x070d # macro
mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA1_PAGE_MIDCMD_DATA0 = 0x0718 # macro
mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA1_PAGE_MIDCMD_DATA1 = 0x0719 # macro
mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA1_PAGE_MIDCMD_DATA2 = 0x071a # macro
mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA1_PAGE_MIDCMD_DATA3 = 0x071b # macro
mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA1_PAGE_MIDCMD_DATA4 = 0x071c # macro
mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA1_PAGE_MIDCMD_DATA5 = 0x071d # macro
mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA1_PAGE_MIDCMD_DATA6 = 0x071e # macro
mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA1_PAGE_MIDCMD_DATA7 = 0x071f # macro
mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA1_PAGE_MIDCMD_DATA8 = 0x0720 # macro
mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA1_PAGE_MIDCMD_DATA9 = 0x0721 # macro
mmSDMA1_PAGE_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA1_PAGE_MIDCMD_DATA10 = 0x0722 # macro
mmSDMA1_PAGE_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA1_PAGE_MIDCMD_CNTL = 0x0723 # macro
mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC0_RB_CNTL = 0x0730 # macro
mmSDMA1_RLC0_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC0_RB_BASE = 0x0731 # macro
mmSDMA1_RLC0_RB_BASE_BASE_IDX = 0 # macro
mmSDMA1_RLC0_RB_BASE_HI = 0x0732 # macro
mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC0_RB_RPTR = 0x0733 # macro
mmSDMA1_RLC0_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC0_RB_RPTR_HI = 0x0734 # macro
mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC0_RB_WPTR = 0x0735 # macro
mmSDMA1_RLC0_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC0_RB_WPTR_HI = 0x0736 # macro
mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC0_RB_WPTR_POLL_CNTL = 0x0737 # macro
mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC0_RB_RPTR_ADDR_HI = 0x0738 # macro
mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC0_RB_RPTR_ADDR_LO = 0x0739 # macro
mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC0_IB_CNTL = 0x073a # macro
mmSDMA1_RLC0_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC0_IB_RPTR = 0x073b # macro
mmSDMA1_RLC0_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC0_IB_OFFSET = 0x073c # macro
mmSDMA1_RLC0_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC0_IB_BASE_LO = 0x073d # macro
mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC0_IB_BASE_HI = 0x073e # macro
mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC0_IB_SIZE = 0x073f # macro
mmSDMA1_RLC0_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA1_RLC0_SKIP_CNTL = 0x0740 # macro
mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC0_CONTEXT_STATUS = 0x0741 # macro
mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC0_DOORBELL = 0x0742 # macro
mmSDMA1_RLC0_DOORBELL_BASE_IDX = 0 # macro
mmSDMA1_RLC0_STATUS = 0x0758 # macro
mmSDMA1_RLC0_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC0_DOORBELL_LOG = 0x0759 # macro
mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA1_RLC0_WATERMARK = 0x075a # macro
mmSDMA1_RLC0_WATERMARK_BASE_IDX = 0 # macro
mmSDMA1_RLC0_DOORBELL_OFFSET = 0x075b # macro
mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC0_CSA_ADDR_LO = 0x075c # macro
mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC0_CSA_ADDR_HI = 0x075d # macro
mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC0_IB_SUB_REMAIN = 0x075f # macro
mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA1_RLC0_PREEMPT = 0x0760 # macro
mmSDMA1_RLC0_PREEMPT_BASE_IDX = 0 # macro
mmSDMA1_RLC0_DUMMY_REG = 0x0761 # macro
mmSDMA1_RLC0_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI = 0x0762 # macro
mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO = 0x0763 # macro
mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC0_RB_AQL_CNTL = 0x0764 # macro
mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC0_MINOR_PTR_UPDATE = 0x0765 # macro
mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA1_RLC0_MIDCMD_DATA0 = 0x0770 # macro
mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA1_RLC0_MIDCMD_DATA1 = 0x0771 # macro
mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA1_RLC0_MIDCMD_DATA2 = 0x0772 # macro
mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA1_RLC0_MIDCMD_DATA3 = 0x0773 # macro
mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA1_RLC0_MIDCMD_DATA4 = 0x0774 # macro
mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA1_RLC0_MIDCMD_DATA5 = 0x0775 # macro
mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA1_RLC0_MIDCMD_DATA6 = 0x0776 # macro
mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA1_RLC0_MIDCMD_DATA7 = 0x0777 # macro
mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA1_RLC0_MIDCMD_DATA8 = 0x0778 # macro
mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA1_RLC0_MIDCMD_DATA9 = 0x0779 # macro
mmSDMA1_RLC0_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA1_RLC0_MIDCMD_DATA10 = 0x077a # macro
mmSDMA1_RLC0_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA1_RLC0_MIDCMD_CNTL = 0x077b # macro
mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC1_RB_CNTL = 0x0788 # macro
mmSDMA1_RLC1_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC1_RB_BASE = 0x0789 # macro
mmSDMA1_RLC1_RB_BASE_BASE_IDX = 0 # macro
mmSDMA1_RLC1_RB_BASE_HI = 0x078a # macro
mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC1_RB_RPTR = 0x078b # macro
mmSDMA1_RLC1_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC1_RB_RPTR_HI = 0x078c # macro
mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC1_RB_WPTR = 0x078d # macro
mmSDMA1_RLC1_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC1_RB_WPTR_HI = 0x078e # macro
mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC1_RB_WPTR_POLL_CNTL = 0x078f # macro
mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC1_RB_RPTR_ADDR_HI = 0x0790 # macro
mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC1_RB_RPTR_ADDR_LO = 0x0791 # macro
mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC1_IB_CNTL = 0x0792 # macro
mmSDMA1_RLC1_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC1_IB_RPTR = 0x0793 # macro
mmSDMA1_RLC1_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC1_IB_OFFSET = 0x0794 # macro
mmSDMA1_RLC1_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC1_IB_BASE_LO = 0x0795 # macro
mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC1_IB_BASE_HI = 0x0796 # macro
mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC1_IB_SIZE = 0x0797 # macro
mmSDMA1_RLC1_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA1_RLC1_SKIP_CNTL = 0x0798 # macro
mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC1_CONTEXT_STATUS = 0x0799 # macro
mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC1_DOORBELL = 0x079a # macro
mmSDMA1_RLC1_DOORBELL_BASE_IDX = 0 # macro
mmSDMA1_RLC1_STATUS = 0x07b0 # macro
mmSDMA1_RLC1_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC1_DOORBELL_LOG = 0x07b1 # macro
mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA1_RLC1_WATERMARK = 0x07b2 # macro
mmSDMA1_RLC1_WATERMARK_BASE_IDX = 0 # macro
mmSDMA1_RLC1_DOORBELL_OFFSET = 0x07b3 # macro
mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC1_CSA_ADDR_LO = 0x07b4 # macro
mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC1_CSA_ADDR_HI = 0x07b5 # macro
mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC1_IB_SUB_REMAIN = 0x07b7 # macro
mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA1_RLC1_PREEMPT = 0x07b8 # macro
mmSDMA1_RLC1_PREEMPT_BASE_IDX = 0 # macro
mmSDMA1_RLC1_DUMMY_REG = 0x07b9 # macro
mmSDMA1_RLC1_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI = 0x07ba # macro
mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO = 0x07bb # macro
mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC1_RB_AQL_CNTL = 0x07bc # macro
mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC1_MINOR_PTR_UPDATE = 0x07bd # macro
mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA1_RLC1_MIDCMD_DATA0 = 0x07c8 # macro
mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA1_RLC1_MIDCMD_DATA1 = 0x07c9 # macro
mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA1_RLC1_MIDCMD_DATA2 = 0x07ca # macro
mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA1_RLC1_MIDCMD_DATA3 = 0x07cb # macro
mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA1_RLC1_MIDCMD_DATA4 = 0x07cc # macro
mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA1_RLC1_MIDCMD_DATA5 = 0x07cd # macro
mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA1_RLC1_MIDCMD_DATA6 = 0x07ce # macro
mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA1_RLC1_MIDCMD_DATA7 = 0x07cf # macro
mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA1_RLC1_MIDCMD_DATA8 = 0x07d0 # macro
mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA1_RLC1_MIDCMD_DATA9 = 0x07d1 # macro
mmSDMA1_RLC1_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA1_RLC1_MIDCMD_DATA10 = 0x07d2 # macro
mmSDMA1_RLC1_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA1_RLC1_MIDCMD_CNTL = 0x07d3 # macro
mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC2_RB_CNTL = 0x07e0 # macro
mmSDMA1_RLC2_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC2_RB_BASE = 0x07e1 # macro
mmSDMA1_RLC2_RB_BASE_BASE_IDX = 0 # macro
mmSDMA1_RLC2_RB_BASE_HI = 0x07e2 # macro
mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC2_RB_RPTR = 0x07e3 # macro
mmSDMA1_RLC2_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC2_RB_RPTR_HI = 0x07e4 # macro
mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC2_RB_WPTR = 0x07e5 # macro
mmSDMA1_RLC2_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC2_RB_WPTR_HI = 0x07e6 # macro
mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC2_RB_WPTR_POLL_CNTL = 0x07e7 # macro
mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC2_RB_RPTR_ADDR_HI = 0x07e8 # macro
mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC2_RB_RPTR_ADDR_LO = 0x07e9 # macro
mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC2_IB_CNTL = 0x07ea # macro
mmSDMA1_RLC2_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC2_IB_RPTR = 0x07eb # macro
mmSDMA1_RLC2_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC2_IB_OFFSET = 0x07ec # macro
mmSDMA1_RLC2_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC2_IB_BASE_LO = 0x07ed # macro
mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC2_IB_BASE_HI = 0x07ee # macro
mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC2_IB_SIZE = 0x07ef # macro
mmSDMA1_RLC2_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA1_RLC2_SKIP_CNTL = 0x07f0 # macro
mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC2_CONTEXT_STATUS = 0x07f1 # macro
mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC2_DOORBELL = 0x07f2 # macro
mmSDMA1_RLC2_DOORBELL_BASE_IDX = 0 # macro
mmSDMA1_RLC2_STATUS = 0x0808 # macro
mmSDMA1_RLC2_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC2_DOORBELL_LOG = 0x0809 # macro
mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA1_RLC2_WATERMARK = 0x080a # macro
mmSDMA1_RLC2_WATERMARK_BASE_IDX = 0 # macro
mmSDMA1_RLC2_DOORBELL_OFFSET = 0x080b # macro
mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC2_CSA_ADDR_LO = 0x080c # macro
mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC2_CSA_ADDR_HI = 0x080d # macro
mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC2_IB_SUB_REMAIN = 0x080f # macro
mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA1_RLC2_PREEMPT = 0x0810 # macro
mmSDMA1_RLC2_PREEMPT_BASE_IDX = 0 # macro
mmSDMA1_RLC2_DUMMY_REG = 0x0811 # macro
mmSDMA1_RLC2_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI = 0x0812 # macro
mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO = 0x0813 # macro
mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC2_RB_AQL_CNTL = 0x0814 # macro
mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC2_MINOR_PTR_UPDATE = 0x0815 # macro
mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA1_RLC2_MIDCMD_DATA0 = 0x0820 # macro
mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA1_RLC2_MIDCMD_DATA1 = 0x0821 # macro
mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA1_RLC2_MIDCMD_DATA2 = 0x0822 # macro
mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA1_RLC2_MIDCMD_DATA3 = 0x0823 # macro
mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA1_RLC2_MIDCMD_DATA4 = 0x0824 # macro
mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA1_RLC2_MIDCMD_DATA5 = 0x0825 # macro
mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA1_RLC2_MIDCMD_DATA6 = 0x0826 # macro
mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA1_RLC2_MIDCMD_DATA7 = 0x0827 # macro
mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA1_RLC2_MIDCMD_DATA8 = 0x0828 # macro
mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA1_RLC2_MIDCMD_DATA9 = 0x0829 # macro
mmSDMA1_RLC2_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA1_RLC2_MIDCMD_DATA10 = 0x082a # macro
mmSDMA1_RLC2_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA1_RLC2_MIDCMD_CNTL = 0x082b # macro
mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC3_RB_CNTL = 0x0838 # macro
mmSDMA1_RLC3_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC3_RB_BASE = 0x0839 # macro
mmSDMA1_RLC3_RB_BASE_BASE_IDX = 0 # macro
mmSDMA1_RLC3_RB_BASE_HI = 0x083a # macro
mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC3_RB_RPTR = 0x083b # macro
mmSDMA1_RLC3_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC3_RB_RPTR_HI = 0x083c # macro
mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC3_RB_WPTR = 0x083d # macro
mmSDMA1_RLC3_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC3_RB_WPTR_HI = 0x083e # macro
mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC3_RB_WPTR_POLL_CNTL = 0x083f # macro
mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC3_RB_RPTR_ADDR_HI = 0x0840 # macro
mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC3_RB_RPTR_ADDR_LO = 0x0841 # macro
mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC3_IB_CNTL = 0x0842 # macro
mmSDMA1_RLC3_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC3_IB_RPTR = 0x0843 # macro
mmSDMA1_RLC3_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC3_IB_OFFSET = 0x0844 # macro
mmSDMA1_RLC3_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC3_IB_BASE_LO = 0x0845 # macro
mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC3_IB_BASE_HI = 0x0846 # macro
mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC3_IB_SIZE = 0x0847 # macro
mmSDMA1_RLC3_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA1_RLC3_SKIP_CNTL = 0x0848 # macro
mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC3_CONTEXT_STATUS = 0x0849 # macro
mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC3_DOORBELL = 0x084a # macro
mmSDMA1_RLC3_DOORBELL_BASE_IDX = 0 # macro
mmSDMA1_RLC3_STATUS = 0x0860 # macro
mmSDMA1_RLC3_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC3_DOORBELL_LOG = 0x0861 # macro
mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA1_RLC3_WATERMARK = 0x0862 # macro
mmSDMA1_RLC3_WATERMARK_BASE_IDX = 0 # macro
mmSDMA1_RLC3_DOORBELL_OFFSET = 0x0863 # macro
mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC3_CSA_ADDR_LO = 0x0864 # macro
mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC3_CSA_ADDR_HI = 0x0865 # macro
mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC3_IB_SUB_REMAIN = 0x0867 # macro
mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA1_RLC3_PREEMPT = 0x0868 # macro
mmSDMA1_RLC3_PREEMPT_BASE_IDX = 0 # macro
mmSDMA1_RLC3_DUMMY_REG = 0x0869 # macro
mmSDMA1_RLC3_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI = 0x086a # macro
mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO = 0x086b # macro
mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC3_RB_AQL_CNTL = 0x086c # macro
mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC3_MINOR_PTR_UPDATE = 0x086d # macro
mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA1_RLC3_MIDCMD_DATA0 = 0x0878 # macro
mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA1_RLC3_MIDCMD_DATA1 = 0x0879 # macro
mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA1_RLC3_MIDCMD_DATA2 = 0x087a # macro
mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA1_RLC3_MIDCMD_DATA3 = 0x087b # macro
mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA1_RLC3_MIDCMD_DATA4 = 0x087c # macro
mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA1_RLC3_MIDCMD_DATA5 = 0x087d # macro
mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA1_RLC3_MIDCMD_DATA6 = 0x087e # macro
mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA1_RLC3_MIDCMD_DATA7 = 0x087f # macro
mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA1_RLC3_MIDCMD_DATA8 = 0x0880 # macro
mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA1_RLC3_MIDCMD_DATA9 = 0x0881 # macro
mmSDMA1_RLC3_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA1_RLC3_MIDCMD_DATA10 = 0x0882 # macro
mmSDMA1_RLC3_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA1_RLC3_MIDCMD_CNTL = 0x0883 # macro
mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC4_RB_CNTL = 0x0890 # macro
mmSDMA1_RLC4_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC4_RB_BASE = 0x0891 # macro
mmSDMA1_RLC4_RB_BASE_BASE_IDX = 0 # macro
mmSDMA1_RLC4_RB_BASE_HI = 0x0892 # macro
mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC4_RB_RPTR = 0x0893 # macro
mmSDMA1_RLC4_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC4_RB_RPTR_HI = 0x0894 # macro
mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC4_RB_WPTR = 0x0895 # macro
mmSDMA1_RLC4_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC4_RB_WPTR_HI = 0x0896 # macro
mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC4_RB_WPTR_POLL_CNTL = 0x0897 # macro
mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC4_RB_RPTR_ADDR_HI = 0x0898 # macro
mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC4_RB_RPTR_ADDR_LO = 0x0899 # macro
mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC4_IB_CNTL = 0x089a # macro
mmSDMA1_RLC4_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC4_IB_RPTR = 0x089b # macro
mmSDMA1_RLC4_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC4_IB_OFFSET = 0x089c # macro
mmSDMA1_RLC4_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC4_IB_BASE_LO = 0x089d # macro
mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC4_IB_BASE_HI = 0x089e # macro
mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC4_IB_SIZE = 0x089f # macro
mmSDMA1_RLC4_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA1_RLC4_SKIP_CNTL = 0x08a0 # macro
mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC4_CONTEXT_STATUS = 0x08a1 # macro
mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC4_DOORBELL = 0x08a2 # macro
mmSDMA1_RLC4_DOORBELL_BASE_IDX = 0 # macro
mmSDMA1_RLC4_STATUS = 0x08b8 # macro
mmSDMA1_RLC4_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC4_DOORBELL_LOG = 0x08b9 # macro
mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA1_RLC4_WATERMARK = 0x08ba # macro
mmSDMA1_RLC4_WATERMARK_BASE_IDX = 0 # macro
mmSDMA1_RLC4_DOORBELL_OFFSET = 0x08bb # macro
mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC4_CSA_ADDR_LO = 0x08bc # macro
mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC4_CSA_ADDR_HI = 0x08bd # macro
mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC4_IB_SUB_REMAIN = 0x08bf # macro
mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA1_RLC4_PREEMPT = 0x08c0 # macro
mmSDMA1_RLC4_PREEMPT_BASE_IDX = 0 # macro
mmSDMA1_RLC4_DUMMY_REG = 0x08c1 # macro
mmSDMA1_RLC4_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI = 0x08c2 # macro
mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO = 0x08c3 # macro
mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC4_RB_AQL_CNTL = 0x08c4 # macro
mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC4_MINOR_PTR_UPDATE = 0x08c5 # macro
mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA1_RLC4_MIDCMD_DATA0 = 0x08d0 # macro
mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA1_RLC4_MIDCMD_DATA1 = 0x08d1 # macro
mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA1_RLC4_MIDCMD_DATA2 = 0x08d2 # macro
mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA1_RLC4_MIDCMD_DATA3 = 0x08d3 # macro
mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA1_RLC4_MIDCMD_DATA4 = 0x08d4 # macro
mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA1_RLC4_MIDCMD_DATA5 = 0x08d5 # macro
mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA1_RLC4_MIDCMD_DATA6 = 0x08d6 # macro
mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA1_RLC4_MIDCMD_DATA7 = 0x08d7 # macro
mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA1_RLC4_MIDCMD_DATA8 = 0x08d8 # macro
mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA1_RLC4_MIDCMD_DATA9 = 0x08d9 # macro
mmSDMA1_RLC4_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA1_RLC4_MIDCMD_DATA10 = 0x08da # macro
mmSDMA1_RLC4_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA1_RLC4_MIDCMD_CNTL = 0x08db # macro
mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC5_RB_CNTL = 0x08e8 # macro
mmSDMA1_RLC5_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC5_RB_BASE = 0x08e9 # macro
mmSDMA1_RLC5_RB_BASE_BASE_IDX = 0 # macro
mmSDMA1_RLC5_RB_BASE_HI = 0x08ea # macro
mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC5_RB_RPTR = 0x08eb # macro
mmSDMA1_RLC5_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC5_RB_RPTR_HI = 0x08ec # macro
mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC5_RB_WPTR = 0x08ed # macro
mmSDMA1_RLC5_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC5_RB_WPTR_HI = 0x08ee # macro
mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC5_RB_WPTR_POLL_CNTL = 0x08ef # macro
mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC5_RB_RPTR_ADDR_HI = 0x08f0 # macro
mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC5_RB_RPTR_ADDR_LO = 0x08f1 # macro
mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC5_IB_CNTL = 0x08f2 # macro
mmSDMA1_RLC5_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC5_IB_RPTR = 0x08f3 # macro
mmSDMA1_RLC5_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC5_IB_OFFSET = 0x08f4 # macro
mmSDMA1_RLC5_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC5_IB_BASE_LO = 0x08f5 # macro
mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC5_IB_BASE_HI = 0x08f6 # macro
mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC5_IB_SIZE = 0x08f7 # macro
mmSDMA1_RLC5_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA1_RLC5_SKIP_CNTL = 0x08f8 # macro
mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC5_CONTEXT_STATUS = 0x08f9 # macro
mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC5_DOORBELL = 0x08fa # macro
mmSDMA1_RLC5_DOORBELL_BASE_IDX = 0 # macro
mmSDMA1_RLC5_STATUS = 0x0910 # macro
mmSDMA1_RLC5_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC5_DOORBELL_LOG = 0x0911 # macro
mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA1_RLC5_WATERMARK = 0x0912 # macro
mmSDMA1_RLC5_WATERMARK_BASE_IDX = 0 # macro
mmSDMA1_RLC5_DOORBELL_OFFSET = 0x0913 # macro
mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC5_CSA_ADDR_LO = 0x0914 # macro
mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC5_CSA_ADDR_HI = 0x0915 # macro
mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC5_IB_SUB_REMAIN = 0x0917 # macro
mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA1_RLC5_PREEMPT = 0x0918 # macro
mmSDMA1_RLC5_PREEMPT_BASE_IDX = 0 # macro
mmSDMA1_RLC5_DUMMY_REG = 0x0919 # macro
mmSDMA1_RLC5_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI = 0x091a # macro
mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO = 0x091b # macro
mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC5_RB_AQL_CNTL = 0x091c # macro
mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC5_MINOR_PTR_UPDATE = 0x091d # macro
mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA1_RLC5_MIDCMD_DATA0 = 0x0928 # macro
mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA1_RLC5_MIDCMD_DATA1 = 0x0929 # macro
mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA1_RLC5_MIDCMD_DATA2 = 0x092a # macro
mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA1_RLC5_MIDCMD_DATA3 = 0x092b # macro
mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA1_RLC5_MIDCMD_DATA4 = 0x092c # macro
mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA1_RLC5_MIDCMD_DATA5 = 0x092d # macro
mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA1_RLC5_MIDCMD_DATA6 = 0x092e # macro
mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA1_RLC5_MIDCMD_DATA7 = 0x092f # macro
mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA1_RLC5_MIDCMD_DATA8 = 0x0930 # macro
mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA1_RLC5_MIDCMD_DATA9 = 0x0931 # macro
mmSDMA1_RLC5_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA1_RLC5_MIDCMD_DATA10 = 0x0932 # macro
mmSDMA1_RLC5_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA1_RLC5_MIDCMD_CNTL = 0x0933 # macro
mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC6_RB_CNTL = 0x0940 # macro
mmSDMA1_RLC6_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC6_RB_BASE = 0x0941 # macro
mmSDMA1_RLC6_RB_BASE_BASE_IDX = 0 # macro
mmSDMA1_RLC6_RB_BASE_HI = 0x0942 # macro
mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC6_RB_RPTR = 0x0943 # macro
mmSDMA1_RLC6_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC6_RB_RPTR_HI = 0x0944 # macro
mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC6_RB_WPTR = 0x0945 # macro
mmSDMA1_RLC6_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC6_RB_WPTR_HI = 0x0946 # macro
mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC6_RB_WPTR_POLL_CNTL = 0x0947 # macro
mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC6_RB_RPTR_ADDR_HI = 0x0948 # macro
mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC6_RB_RPTR_ADDR_LO = 0x0949 # macro
mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC6_IB_CNTL = 0x094a # macro
mmSDMA1_RLC6_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC6_IB_RPTR = 0x094b # macro
mmSDMA1_RLC6_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC6_IB_OFFSET = 0x094c # macro
mmSDMA1_RLC6_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC6_IB_BASE_LO = 0x094d # macro
mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC6_IB_BASE_HI = 0x094e # macro
mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC6_IB_SIZE = 0x094f # macro
mmSDMA1_RLC6_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA1_RLC6_SKIP_CNTL = 0x0950 # macro
mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC6_CONTEXT_STATUS = 0x0951 # macro
mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC6_DOORBELL = 0x0952 # macro
mmSDMA1_RLC6_DOORBELL_BASE_IDX = 0 # macro
mmSDMA1_RLC6_STATUS = 0x0968 # macro
mmSDMA1_RLC6_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC6_DOORBELL_LOG = 0x0969 # macro
mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA1_RLC6_WATERMARK = 0x096a # macro
mmSDMA1_RLC6_WATERMARK_BASE_IDX = 0 # macro
mmSDMA1_RLC6_DOORBELL_OFFSET = 0x096b # macro
mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC6_CSA_ADDR_LO = 0x096c # macro
mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC6_CSA_ADDR_HI = 0x096d # macro
mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC6_IB_SUB_REMAIN = 0x096f # macro
mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA1_RLC6_PREEMPT = 0x0970 # macro
mmSDMA1_RLC6_PREEMPT_BASE_IDX = 0 # macro
mmSDMA1_RLC6_DUMMY_REG = 0x0971 # macro
mmSDMA1_RLC6_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI = 0x0972 # macro
mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO = 0x0973 # macro
mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC6_RB_AQL_CNTL = 0x0974 # macro
mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC6_MINOR_PTR_UPDATE = 0x0975 # macro
mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA1_RLC6_MIDCMD_DATA0 = 0x0980 # macro
mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA1_RLC6_MIDCMD_DATA1 = 0x0981 # macro
mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA1_RLC6_MIDCMD_DATA2 = 0x0982 # macro
mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA1_RLC6_MIDCMD_DATA3 = 0x0983 # macro
mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA1_RLC6_MIDCMD_DATA4 = 0x0984 # macro
mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA1_RLC6_MIDCMD_DATA5 = 0x0985 # macro
mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA1_RLC6_MIDCMD_DATA6 = 0x0986 # macro
mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA1_RLC6_MIDCMD_DATA7 = 0x0987 # macro
mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA1_RLC6_MIDCMD_DATA8 = 0x0988 # macro
mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA1_RLC6_MIDCMD_DATA9 = 0x0989 # macro
mmSDMA1_RLC6_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA1_RLC6_MIDCMD_DATA10 = 0x098a # macro
mmSDMA1_RLC6_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA1_RLC6_MIDCMD_CNTL = 0x098b # macro
mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC7_RB_CNTL = 0x0998 # macro
mmSDMA1_RLC7_RB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC7_RB_BASE = 0x0999 # macro
mmSDMA1_RLC7_RB_BASE_BASE_IDX = 0 # macro
mmSDMA1_RLC7_RB_BASE_HI = 0x099a # macro
mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC7_RB_RPTR = 0x099b # macro
mmSDMA1_RLC7_RB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC7_RB_RPTR_HI = 0x099c # macro
mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC7_RB_WPTR = 0x099d # macro
mmSDMA1_RLC7_RB_WPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC7_RB_WPTR_HI = 0x099e # macro
mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC7_RB_WPTR_POLL_CNTL = 0x099f # macro
mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC7_RB_RPTR_ADDR_HI = 0x09a0 # macro
mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC7_RB_RPTR_ADDR_LO = 0x09a1 # macro
mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC7_IB_CNTL = 0x09a2 # macro
mmSDMA1_RLC7_IB_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC7_IB_RPTR = 0x09a3 # macro
mmSDMA1_RLC7_IB_RPTR_BASE_IDX = 0 # macro
mmSDMA1_RLC7_IB_OFFSET = 0x09a4 # macro
mmSDMA1_RLC7_IB_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC7_IB_BASE_LO = 0x09a5 # macro
mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC7_IB_BASE_HI = 0x09a6 # macro
mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC7_IB_SIZE = 0x09a7 # macro
mmSDMA1_RLC7_IB_SIZE_BASE_IDX = 0 # macro
mmSDMA1_RLC7_SKIP_CNTL = 0x09a8 # macro
mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC7_CONTEXT_STATUS = 0x09a9 # macro
mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC7_DOORBELL = 0x09aa # macro
mmSDMA1_RLC7_DOORBELL_BASE_IDX = 0 # macro
mmSDMA1_RLC7_STATUS = 0x09c0 # macro
mmSDMA1_RLC7_STATUS_BASE_IDX = 0 # macro
mmSDMA1_RLC7_DOORBELL_LOG = 0x09c1 # macro
mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX = 0 # macro
mmSDMA1_RLC7_WATERMARK = 0x09c2 # macro
mmSDMA1_RLC7_WATERMARK_BASE_IDX = 0 # macro
mmSDMA1_RLC7_DOORBELL_OFFSET = 0x09c3 # macro
mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX = 0 # macro
mmSDMA1_RLC7_CSA_ADDR_LO = 0x09c4 # macro
mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC7_CSA_ADDR_HI = 0x09c5 # macro
mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC7_IB_SUB_REMAIN = 0x09c7 # macro
mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX = 0 # macro
mmSDMA1_RLC7_PREEMPT = 0x09c8 # macro
mmSDMA1_RLC7_PREEMPT_BASE_IDX = 0 # macro
mmSDMA1_RLC7_DUMMY_REG = 0x09c9 # macro
mmSDMA1_RLC7_DUMMY_REG_BASE_IDX = 0 # macro
mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI = 0x09ca # macro
mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO = 0x09cb # macro
mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmSDMA1_RLC7_RB_AQL_CNTL = 0x09cc # macro
mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX = 0 # macro
mmSDMA1_RLC7_MINOR_PTR_UPDATE = 0x09cd # macro
mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
mmSDMA1_RLC7_MIDCMD_DATA0 = 0x09d8 # macro
mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX = 0 # macro
mmSDMA1_RLC7_MIDCMD_DATA1 = 0x09d9 # macro
mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX = 0 # macro
mmSDMA1_RLC7_MIDCMD_DATA2 = 0x09da # macro
mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX = 0 # macro
mmSDMA1_RLC7_MIDCMD_DATA3 = 0x09db # macro
mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX = 0 # macro
mmSDMA1_RLC7_MIDCMD_DATA4 = 0x09dc # macro
mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX = 0 # macro
mmSDMA1_RLC7_MIDCMD_DATA5 = 0x09dd # macro
mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX = 0 # macro
mmSDMA1_RLC7_MIDCMD_DATA6 = 0x09de # macro
mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX = 0 # macro
mmSDMA1_RLC7_MIDCMD_DATA7 = 0x09df # macro
mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX = 0 # macro
mmSDMA1_RLC7_MIDCMD_DATA8 = 0x09e0 # macro
mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX = 0 # macro
mmSDMA1_RLC7_MIDCMD_DATA9 = 0x09e1 # macro
mmSDMA1_RLC7_MIDCMD_DATA9_BASE_IDX = 0 # macro
mmSDMA1_RLC7_MIDCMD_DATA10 = 0x09e2 # macro
mmSDMA1_RLC7_MIDCMD_DATA10_BASE_IDX = 0 # macro
mmSDMA1_RLC7_MIDCMD_CNTL = 0x09e3 # macro
mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX = 0 # macro
mmGRBM_CNTL = 0x0da0 # macro
mmGRBM_CNTL_BASE_IDX = 0 # macro
mmGRBM_SKEW_CNTL = 0x0da1 # macro
mmGRBM_SKEW_CNTL_BASE_IDX = 0 # macro
mmGRBM_STATUS2 = 0x0da2 # macro
mmGRBM_STATUS2_BASE_IDX = 0 # macro
mmGRBM_PWR_CNTL = 0x0da3 # macro
mmGRBM_PWR_CNTL_BASE_IDX = 0 # macro
mmGRBM_STATUS = 0x0da4 # macro
mmGRBM_STATUS_BASE_IDX = 0 # macro
mmGRBM_STATUS_SE0 = 0x0da5 # macro
mmGRBM_STATUS_SE0_BASE_IDX = 0 # macro
mmGRBM_STATUS_SE1 = 0x0da6 # macro
mmGRBM_STATUS_SE1_BASE_IDX = 0 # macro
mmGRBM_STATUS3 = 0x0da7 # macro
mmGRBM_STATUS3_BASE_IDX = 0 # macro
mmGRBM_SOFT_RESET = 0x0da8 # macro
mmGRBM_SOFT_RESET_BASE_IDX = 0 # macro
mmGRBM_GFX_CLKEN_CNTL = 0x0dac # macro
mmGRBM_GFX_CLKEN_CNTL_BASE_IDX = 0 # macro
mmGRBM_WAIT_IDLE_CLOCKS = 0x0dad # macro
mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX = 0 # macro
mmGRBM_STATUS_SE2 = 0x0dae # macro
mmGRBM_STATUS_SE2_BASE_IDX = 0 # macro
mmGRBM_STATUS_SE3 = 0x0daf # macro
mmGRBM_STATUS_SE3_BASE_IDX = 0 # macro
mmGRBM_READ_ERROR = 0x0db6 # macro
mmGRBM_READ_ERROR_BASE_IDX = 0 # macro
mmGRBM_READ_ERROR2 = 0x0db7 # macro
mmGRBM_READ_ERROR2_BASE_IDX = 0 # macro
mmGRBM_INT_CNTL = 0x0db8 # macro
mmGRBM_INT_CNTL_BASE_IDX = 0 # macro
mmGRBM_TRAP_OP = 0x0db9 # macro
mmGRBM_TRAP_OP_BASE_IDX = 0 # macro
mmGRBM_TRAP_ADDR = 0x0dba # macro
mmGRBM_TRAP_ADDR_BASE_IDX = 0 # macro
mmGRBM_TRAP_ADDR_MSK = 0x0dbb # macro
mmGRBM_TRAP_ADDR_MSK_BASE_IDX = 0 # macro
mmGRBM_TRAP_WD = 0x0dbc # macro
mmGRBM_TRAP_WD_BASE_IDX = 0 # macro
mmGRBM_TRAP_WD_MSK = 0x0dbd # macro
mmGRBM_TRAP_WD_MSK_BASE_IDX = 0 # macro
mmGRBM_DSM_BYPASS = 0x0dbe # macro
mmGRBM_DSM_BYPASS_BASE_IDX = 0 # macro
mmGRBM_WRITE_ERROR = 0x0dbf # macro
mmGRBM_WRITE_ERROR_BASE_IDX = 0 # macro
mmGRBM_CHIP_REVISION = 0x0dc1 # macro
mmGRBM_CHIP_REVISION_BASE_IDX = 0 # macro
mmGRBM_GFX_CNTL = 0x0dc2 # macro
mmGRBM_GFX_CNTL_BASE_IDX = 0 # macro
mmGRBM_IH_CREDIT = 0x0dc4 # macro
mmGRBM_IH_CREDIT_BASE_IDX = 0 # macro
mmGRBM_PWR_CNTL2 = 0x0dc5 # macro
mmGRBM_PWR_CNTL2_BASE_IDX = 0 # macro
mmGRBM_UTCL2_INVAL_RANGE_START = 0x0dc6 # macro
mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX = 0 # macro
mmGRBM_UTCL2_INVAL_RANGE_END = 0x0dc7 # macro
mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX = 0 # macro
mmGRBM_FENCE_RANGE0 = 0x0dca # macro
mmGRBM_FENCE_RANGE0_BASE_IDX = 0 # macro
mmGRBM_FENCE_RANGE1 = 0x0dcb # macro
mmGRBM_FENCE_RANGE1_BASE_IDX = 0 # macro
mmGRBM_NOWHERE = 0x0ddf # macro
mmGRBM_NOWHERE_BASE_IDX = 0 # macro
mmGRBM_SCRATCH_REG0 = 0x0de0 # macro
mmGRBM_SCRATCH_REG0_BASE_IDX = 0 # macro
mmGRBM_SCRATCH_REG1 = 0x0de1 # macro
mmGRBM_SCRATCH_REG1_BASE_IDX = 0 # macro
mmGRBM_SCRATCH_REG2 = 0x0de2 # macro
mmGRBM_SCRATCH_REG2_BASE_IDX = 0 # macro
mmGRBM_SCRATCH_REG3 = 0x0de3 # macro
mmGRBM_SCRATCH_REG3_BASE_IDX = 0 # macro
mmGRBM_SCRATCH_REG4 = 0x0de4 # macro
mmGRBM_SCRATCH_REG4_BASE_IDX = 0 # macro
mmGRBM_SCRATCH_REG5 = 0x0de5 # macro
mmGRBM_SCRATCH_REG5_BASE_IDX = 0 # macro
mmGRBM_SCRATCH_REG6 = 0x0de6 # macro
mmGRBM_SCRATCH_REG6_BASE_IDX = 0 # macro
mmGRBM_SCRATCH_REG7 = 0x0de7 # macro
mmGRBM_SCRATCH_REG7_BASE_IDX = 0 # macro
mmVIOLATION_DATA_ASYNC_VF_PROG = 0x0df1 # macro
mmVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX = 0 # macro
mmCP_CPC_STATUS = 0x0e24 # macro
mmCP_CPC_STATUS_BASE_IDX = 0 # macro
mmCP_CPC_BUSY_STAT = 0x0e25 # macro
mmCP_CPC_BUSY_STAT_BASE_IDX = 0 # macro
mmCP_CPC_STALLED_STAT1 = 0x0e26 # macro
mmCP_CPC_STALLED_STAT1_BASE_IDX = 0 # macro
mmCP_CPF_STATUS = 0x0e27 # macro
mmCP_CPF_STATUS_BASE_IDX = 0 # macro
mmCP_CPF_BUSY_STAT = 0x0e28 # macro
mmCP_CPF_BUSY_STAT_BASE_IDX = 0 # macro
mmCP_CPF_STALLED_STAT1 = 0x0e29 # macro
mmCP_CPF_STALLED_STAT1_BASE_IDX = 0 # macro
mmCP_CPC_BUSY_STAT2 = 0x0e2a # macro
mmCP_CPC_BUSY_STAT2_BASE_IDX = 0 # macro
mmCP_CPC_GRBM_FREE_COUNT = 0x0e2b # macro
mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX = 0 # macro
mmCP_CPC_PRIV_VIOLATION_ADDR = 0x0e2c # macro
mmCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro
mmCP_MEC_ME1_HEADER_DUMP = 0x0e2e # macro
mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX = 0 # macro
mmCP_MEC_ME2_HEADER_DUMP = 0x0e2f # macro
mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX = 0 # macro
mmCP_CPC_SCRATCH_INDEX = 0x0e30 # macro
mmCP_CPC_SCRATCH_INDEX_BASE_IDX = 0 # macro
mmCP_CPC_SCRATCH_DATA = 0x0e31 # macro
mmCP_CPC_SCRATCH_DATA_BASE_IDX = 0 # macro
mmCP_CPF_GRBM_FREE_COUNT = 0x0e32 # macro
mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX = 0 # macro
mmCP_CPF_BUSY_STAT2 = 0x0e33 # macro
mmCP_CPF_BUSY_STAT2_BASE_IDX = 0 # macro
mmCONFIG_RESERVED_REG0 = 0x0e34 # macro
mmCONFIG_RESERVED_REG0_BASE_IDX = 0 # macro
mmCONFIG_RESERVED_REG1 = 0x0e35 # macro
mmCONFIG_RESERVED_REG1_BASE_IDX = 0 # macro
mmCP_CPC_HALT_HYST_COUNT = 0x0e47 # macro
mmCP_CPC_HALT_HYST_COUNT_BASE_IDX = 0 # macro
mmCP_CE_COMPARE_COUNT = 0x0e60 # macro
mmCP_CE_COMPARE_COUNT_BASE_IDX = 0 # macro
mmCP_CE_DE_COUNT = 0x0e61 # macro
mmCP_CE_DE_COUNT_BASE_IDX = 0 # macro
mmCP_DE_CE_COUNT = 0x0e62 # macro
mmCP_DE_CE_COUNT_BASE_IDX = 0 # macro
mmCP_DE_LAST_INVAL_COUNT = 0x0e63 # macro
mmCP_DE_LAST_INVAL_COUNT_BASE_IDX = 0 # macro
mmCP_DE_DE_COUNT = 0x0e64 # macro
mmCP_DE_DE_COUNT_BASE_IDX = 0 # macro
mmCP_STALLED_STAT3 = 0x0f3c # macro
mmCP_STALLED_STAT3_BASE_IDX = 0 # macro
mmCP_STALLED_STAT1 = 0x0f3d # macro
mmCP_STALLED_STAT1_BASE_IDX = 0 # macro
mmCP_STALLED_STAT2 = 0x0f3e # macro
mmCP_STALLED_STAT2_BASE_IDX = 0 # macro
mmCP_BUSY_STAT = 0x0f3f # macro
mmCP_BUSY_STAT_BASE_IDX = 0 # macro
mmCP_STAT = 0x0f40 # macro
mmCP_STAT_BASE_IDX = 0 # macro
mmCP_ME_HEADER_DUMP = 0x0f41 # macro
mmCP_ME_HEADER_DUMP_BASE_IDX = 0 # macro
mmCP_PFP_HEADER_DUMP = 0x0f42 # macro
mmCP_PFP_HEADER_DUMP_BASE_IDX = 0 # macro
mmCP_GRBM_FREE_COUNT = 0x0f43 # macro
mmCP_GRBM_FREE_COUNT_BASE_IDX = 0 # macro
mmCP_CE_HEADER_DUMP = 0x0f44 # macro
mmCP_CE_HEADER_DUMP_BASE_IDX = 0 # macro
mmCP_PFP_INSTR_PNTR = 0x0f45 # macro
mmCP_PFP_INSTR_PNTR_BASE_IDX = 0 # macro
mmCP_ME_INSTR_PNTR = 0x0f46 # macro
mmCP_ME_INSTR_PNTR_BASE_IDX = 0 # macro
mmCP_CE_INSTR_PNTR = 0x0f47 # macro
mmCP_CE_INSTR_PNTR_BASE_IDX = 0 # macro
mmCP_MEC1_INSTR_PNTR = 0x0f48 # macro
mmCP_MEC1_INSTR_PNTR_BASE_IDX = 0 # macro
mmCP_MEC2_INSTR_PNTR = 0x0f49 # macro
mmCP_MEC2_INSTR_PNTR_BASE_IDX = 0 # macro
mmCP_CSF_STAT = 0x0f54 # macro
mmCP_CSF_STAT_BASE_IDX = 0 # macro
mmCP_MEC_CNTL = 0x0f55 # macro
mmCP_MEC_CNTL_BASE_IDX = 0 # macro
mmCP_ME_CNTL = 0x0f56 # macro
mmCP_ME_CNTL_BASE_IDX = 0 # macro
mmCP_CNTX_STAT = 0x0f58 # macro
mmCP_CNTX_STAT_BASE_IDX = 0 # macro
mmCP_ME_PREEMPTION = 0x0f59 # macro
mmCP_ME_PREEMPTION_BASE_IDX = 0 # macro
mmCP_ROQ_THRESHOLDS = 0x0f5c # macro
mmCP_ROQ_THRESHOLDS_BASE_IDX = 0 # macro
mmCP_MEQ_STQ_THRESHOLD = 0x0f5d # macro
mmCP_MEQ_STQ_THRESHOLD_BASE_IDX = 0 # macro
mmCP_RB2_RPTR = 0x0f5e # macro
mmCP_RB2_RPTR_BASE_IDX = 0 # macro
mmCP_RB1_RPTR = 0x0f5f # macro
mmCP_RB1_RPTR_BASE_IDX = 0 # macro
mmCP_RB0_RPTR = 0x0f60 # macro
mmCP_RB0_RPTR_BASE_IDX = 0 # macro
mmCP_RB_RPTR = 0x0f60 # macro
mmCP_RB_RPTR_BASE_IDX = 0 # macro
mmCP_RB_WPTR_DELAY = 0x0f61 # macro
mmCP_RB_WPTR_DELAY_BASE_IDX = 0 # macro
mmCP_RB_WPTR_POLL_CNTL = 0x0f62 # macro
mmCP_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmCP_ROQ1_THRESHOLDS = 0x0f75 # macro
mmCP_ROQ1_THRESHOLDS_BASE_IDX = 0 # macro
mmCP_ROQ2_THRESHOLDS = 0x0f76 # macro
mmCP_ROQ2_THRESHOLDS_BASE_IDX = 0 # macro
mmCP_STQ_THRESHOLDS = 0x0f77 # macro
mmCP_STQ_THRESHOLDS_BASE_IDX = 0 # macro
mmCP_QUEUE_THRESHOLDS = 0x0f78 # macro
mmCP_QUEUE_THRESHOLDS_BASE_IDX = 0 # macro
mmCP_MEQ_THRESHOLDS = 0x0f79 # macro
mmCP_MEQ_THRESHOLDS_BASE_IDX = 0 # macro
mmCP_ROQ_AVAIL = 0x0f7a # macro
mmCP_ROQ_AVAIL_BASE_IDX = 0 # macro
mmCP_STQ_AVAIL = 0x0f7b # macro
mmCP_STQ_AVAIL_BASE_IDX = 0 # macro
mmCP_ROQ2_AVAIL = 0x0f7c # macro
mmCP_ROQ2_AVAIL_BASE_IDX = 0 # macro
mmCP_MEQ_AVAIL = 0x0f7d # macro
mmCP_MEQ_AVAIL_BASE_IDX = 0 # macro
mmCP_CMD_INDEX = 0x0f7e # macro
mmCP_CMD_INDEX_BASE_IDX = 0 # macro
mmCP_CMD_DATA = 0x0f7f # macro
mmCP_CMD_DATA_BASE_IDX = 0 # macro
mmCP_ROQ_RB_STAT = 0x0f80 # macro
mmCP_ROQ_RB_STAT_BASE_IDX = 0 # macro
mmCP_ROQ_IB1_STAT = 0x0f81 # macro
mmCP_ROQ_IB1_STAT_BASE_IDX = 0 # macro
mmCP_ROQ_IB2_STAT = 0x0f82 # macro
mmCP_ROQ_IB2_STAT_BASE_IDX = 0 # macro
mmCP_STQ_STAT = 0x0f83 # macro
mmCP_STQ_STAT_BASE_IDX = 0 # macro
mmCP_STQ_WR_STAT = 0x0f84 # macro
mmCP_STQ_WR_STAT_BASE_IDX = 0 # macro
mmCP_MEQ_STAT = 0x0f85 # macro
mmCP_MEQ_STAT_BASE_IDX = 0 # macro
mmCP_CEQ1_AVAIL = 0x0f86 # macro
mmCP_CEQ1_AVAIL_BASE_IDX = 0 # macro
mmCP_CEQ2_AVAIL = 0x0f87 # macro
mmCP_CEQ2_AVAIL_BASE_IDX = 0 # macro
mmCP_CE_ROQ_RB_STAT = 0x0f88 # macro
mmCP_CE_ROQ_RB_STAT_BASE_IDX = 0 # macro
mmCP_CE_ROQ_IB1_STAT = 0x0f89 # macro
mmCP_CE_ROQ_IB1_STAT_BASE_IDX = 0 # macro
mmCP_CE_ROQ_IB2_STAT = 0x0f8a # macro
mmCP_CE_ROQ_IB2_STAT_BASE_IDX = 0 # macro
mmCP_CE_ROQ_DB_STAT = 0x0f8b # macro
mmCP_CE_ROQ_DB_STAT_BASE_IDX = 0 # macro
mmCP_ROQ3_THRESHOLDS = 0x0f8c # macro
mmCP_ROQ3_THRESHOLDS_BASE_IDX = 0 # macro
mmCP_ROQ_DB_STAT = 0x0f8d # macro
mmCP_ROQ_DB_STAT_BASE_IDX = 0 # macro
mmCP_PRIV_VIOLATION_ADDR = 0x0f9a # macro
mmCP_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro
mmVGT_CACHE_INVALIDATION = 0x0fc0 # macro
mmVGT_CACHE_INVALIDATION_BASE_IDX = 0 # macro
mmVGT_ESGS_RING_SIZE = 0x0fc1 # macro
mmVGT_ESGS_RING_SIZE_BASE_IDX = 0 # macro
mmVGT_GSVS_RING_SIZE = 0x0fc2 # macro
mmVGT_GSVS_RING_SIZE_BASE_IDX = 0 # macro
mmVGT_TF_RING_SIZE = 0x0fc3 # macro
mmVGT_TF_RING_SIZE_BASE_IDX = 0 # macro
mmVGT_HS_OFFCHIP_PARAM = 0x0fc4 # macro
mmVGT_HS_OFFCHIP_PARAM_BASE_IDX = 0 # macro
mmVGT_TF_MEMORY_BASE = 0x0fc5 # macro
mmVGT_TF_MEMORY_BASE_BASE_IDX = 0 # macro
mmVGT_TF_MEMORY_BASE_HI = 0x0fc6 # macro
mmVGT_TF_MEMORY_BASE_HI_BASE_IDX = 0 # macro
mmVGT_VTX_VECT_EJECT_REG = 0x0fcc # macro
mmVGT_VTX_VECT_EJECT_REG_BASE_IDX = 0 # macro
mmVGT_DMA_DATA_FIFO_DEPTH = 0x0fcd # macro
mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX = 0 # macro
mmVGT_DMA_REQ_FIFO_DEPTH = 0x0fce # macro
mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX = 0 # macro
mmVGT_DRAW_INIT_FIFO_DEPTH = 0x0fcf # macro
mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX = 0 # macro
mmVGT_LAST_COPY_STATE = 0x0fd0 # macro
mmVGT_LAST_COPY_STATE_BASE_IDX = 0 # macro
mmVGT_FIFO_DEPTHS = 0x0fd4 # macro
mmVGT_FIFO_DEPTHS_BASE_IDX = 0 # macro
mmVGT_GS_VERTEX_REUSE = 0x0fd5 # macro
mmVGT_GS_VERTEX_REUSE_BASE_IDX = 0 # macro
mmVGT_MC_LAT_CNTL = 0x0fd6 # macro
mmVGT_MC_LAT_CNTL_BASE_IDX = 0 # macro
mmIA_UTCL1_STATUS_2 = 0x0fd7 # macro
mmIA_UTCL1_STATUS_2_BASE_IDX = 0 # macro
mmWD_CNTL_STATUS = 0x0fdf # macro
mmWD_CNTL_STATUS_BASE_IDX = 0 # macro
mmCC_GC_PRIM_CONFIG = 0x0fe0 # macro
mmCC_GC_PRIM_CONFIG_BASE_IDX = 0 # macro
mmGC_USER_PRIM_CONFIG = 0x0fe1 # macro
mmGC_USER_PRIM_CONFIG_BASE_IDX = 0 # macro
mmWD_QOS = 0x0fe2 # macro
mmWD_QOS_BASE_IDX = 0 # macro
mmWD_UTCL1_CNTL = 0x0fe3 # macro
mmWD_UTCL1_CNTL_BASE_IDX = 0 # macro
mmWD_UTCL1_STATUS = 0x0fe4 # macro
mmWD_UTCL1_STATUS_BASE_IDX = 0 # macro
mmGE_PC_CNTL = 0x0fe5 # macro
mmGE_PC_CNTL_BASE_IDX = 0 # macro
mmIA_UTCL1_CNTL = 0x0fe6 # macro
mmIA_UTCL1_CNTL_BASE_IDX = 0 # macro
mmIA_UTCL1_STATUS = 0x0fe7 # macro
mmIA_UTCL1_STATUS_BASE_IDX = 0 # macro
mmCC_GC_SA_UNIT_DISABLE = 0x0fe9 # macro
mmCC_GC_SA_UNIT_DISABLE_BASE_IDX = 0 # macro
mmGC_USER_SA_UNIT_DISABLE = 0x0fea # macro
mmGC_USER_SA_UNIT_DISABLE_BASE_IDX = 0 # macro
mmVGT_SYS_CONFIG = 0x1003 # macro
mmVGT_SYS_CONFIG_BASE_IDX = 0 # macro
mmGE_PRIV_CONTROL = 0x1004 # macro
mmGE_PRIV_CONTROL_BASE_IDX = 0 # macro
mmGE_STATUS = 0x1005 # macro
mmGE_STATUS_BASE_IDX = 0 # macro
mmVGT_VS_MAX_WAVE_ID = 0x1008 # macro
mmVGT_VS_MAX_WAVE_ID_BASE_IDX = 0 # macro
mmVGT_GS_MAX_WAVE_ID = 0x1009 # macro
mmVGT_GS_MAX_WAVE_ID_BASE_IDX = 0 # macro
mmCC_GC_SHADER_ARRAY_CONFIG_GEN1 = 0x100a # macro
mmCC_GC_SHADER_ARRAY_CONFIG_GEN1_BASE_IDX = 0 # macro
mmCC_GC_SHADER_ARRAY_CONFIG_GEN0 = 0x100b # macro
mmCC_GC_SHADER_ARRAY_CONFIG_GEN0_BASE_IDX = 0 # macro
mmGFX_PIPE_CONTROL = 0x100d # macro
mmGFX_PIPE_CONTROL_BASE_IDX = 0 # macro
mmCC_GC_SHADER_ARRAY_CONFIG = 0x100f # macro
mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX = 0 # macro
mmGC_USER_SHADER_ARRAY_CONFIG = 0x1010 # macro
mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX = 0 # macro
mmVGT_DMA_PRIMITIVE_TYPE = 0x1011 # macro
mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX = 0 # macro
mmVGT_DMA_CONTROL = 0x1012 # macro
mmVGT_DMA_CONTROL_BASE_IDX = 0 # macro
mmVGT_DMA_LS_HS_CONFIG = 0x1013 # macro
mmVGT_DMA_LS_HS_CONFIG_BASE_IDX = 0 # macro
mmVGT_STRMOUT_DELAY = 0x1015 # macro
mmVGT_STRMOUT_DELAY_BASE_IDX = 0 # macro
mmWD_BUF_RESOURCE_1 = 0x1016 # macro
mmWD_BUF_RESOURCE_1_BASE_IDX = 0 # macro
mmWD_BUF_RESOURCE_2 = 0x1017 # macro
mmWD_BUF_RESOURCE_2_BASE_IDX = 0 # macro
mmPA_CL_CNTL_STATUS = 0x1024 # macro
mmPA_CL_CNTL_STATUS_BASE_IDX = 0 # macro
mmPA_CL_ENHANCE = 0x1025 # macro
mmPA_CL_ENHANCE_BASE_IDX = 0 # macro
mmPA_SU_CNTL_STATUS = 0x1034 # macro
mmPA_SU_CNTL_STATUS_BASE_IDX = 0 # macro
mmPA_SC_FIFO_DEPTH_CNTL = 0x1035 # macro
mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX = 0 # macro
mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK = 0x1060 # macro
mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 0 # macro
mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK = 0x1061 # macro
mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 0 # macro
mmPA_SC_TRAP_SCREEN_HV_LOCK = 0x1062 # macro
mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX = 0 # macro
mmPA_SC_FORCE_EOV_MAX_CNTS = 0x1069 # macro
mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX = 0 # macro
mmPA_SC_BINNER_EVENT_CNTL_0 = 0x106c # macro
mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX = 0 # macro
mmPA_SC_BINNER_EVENT_CNTL_1 = 0x106d # macro
mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX = 0 # macro
mmPA_SC_BINNER_EVENT_CNTL_2 = 0x106e # macro
mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX = 0 # macro
mmPA_SC_BINNER_EVENT_CNTL_3 = 0x106f # macro
mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX = 0 # macro
mmPA_SC_BINNER_TIMEOUT_COUNTER = 0x1070 # macro
mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX = 0 # macro
mmPA_SC_BINNER_PERF_CNTL_0 = 0x1071 # macro
mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX = 0 # macro
mmPA_SC_BINNER_PERF_CNTL_1 = 0x1072 # macro
mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX = 0 # macro
mmPA_SC_BINNER_PERF_CNTL_2 = 0x1073 # macro
mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX = 0 # macro
mmPA_SC_BINNER_PERF_CNTL_3 = 0x1074 # macro
mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX = 0 # macro
mmPA_SC_ENHANCE_2 = 0x107c # macro
mmPA_SC_ENHANCE_2_BASE_IDX = 0 # macro
mmPA_SC_ENHANCE_INTERNAL = 0x107d # macro
mmPA_SC_ENHANCE_INTERNAL_BASE_IDX = 0 # macro
mmPA_SC_BINNER_CNTL_OVERRIDE = 0x107e # macro
mmPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX = 0 # macro
mmPA_SC_PBB_OVERRIDE_FLAG = 0x107f # macro
mmPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX = 0 # macro
mmPA_PH_INTERFACE_FIFO_SIZE = 0x1080 # macro
mmPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX = 0 # macro
mmPA_PH_ENHANCE = 0x1081 # macro
mmPA_PH_ENHANCE_BASE_IDX = 0 # macro
mmPA_SC_BC_WAVE_BREAK = 0x1084 # macro
mmPA_SC_BC_WAVE_BREAK_BASE_IDX = 0 # macro
mmPA_SC_ENHANCE_3 = 0x1085 # macro
mmPA_SC_ENHANCE_3_BASE_IDX = 0 # macro
mmPA_SC_FIFO_SIZE = 0x1093 # macro
mmPA_SC_FIFO_SIZE_BASE_IDX = 0 # macro
mmPA_SC_IF_FIFO_SIZE = 0x1095 # macro
mmPA_SC_IF_FIFO_SIZE_BASE_IDX = 0 # macro
mmPA_SC_PKR_WAVE_TABLE_CNTL = 0x1098 # macro
mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX = 0 # macro
mmPA_SIDEBAND_REQUEST_DELAYS = 0x109b # macro
mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX = 0 # macro
mmPA_SC_ENHANCE = 0x109c # macro
mmPA_SC_ENHANCE_BASE_IDX = 0 # macro
mmPA_SC_ENHANCE_1 = 0x109d # macro
mmPA_SC_ENHANCE_1_BASE_IDX = 0 # macro
mmPA_SC_DSM_CNTL = 0x109e # macro
mmPA_SC_DSM_CNTL_BASE_IDX = 0 # macro
mmPA_SC_TILE_STEERING_CREST_OVERRIDE = 0x109f # macro
mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX = 0 # macro
mmSQ_CONFIG = 0x10a0 # macro
mmSQ_CONFIG_BASE_IDX = 0 # macro
mmSQC_CONFIG = 0x10a1 # macro
mmSQC_CONFIG_BASE_IDX = 0 # macro
mmLDS_CONFIG = 0x10a2 # macro
mmLDS_CONFIG_BASE_IDX = 0 # macro
mmSQ_RANDOM_WAVE_PRI = 0x10a3 # macro
mmSQ_RANDOM_WAVE_PRI_BASE_IDX = 0 # macro
mmSQG_STATUS = 0x10a4 # macro
mmSQG_STATUS_BASE_IDX = 0 # macro
mmSQ_FIFO_SIZES = 0x10a5 # macro
mmSQ_FIFO_SIZES_BASE_IDX = 0 # macro
mmSQ_DSM_CNTL = 0x10a6 # macro
mmSQ_DSM_CNTL_BASE_IDX = 0 # macro
mmSQ_DSM_CNTL2 = 0x10a7 # macro
mmSQ_DSM_CNTL2_BASE_IDX = 0 # macro
mmSQ_RUNTIME_CONFIG = 0x10a8 # macro
mmSQ_RUNTIME_CONFIG_BASE_IDX = 0 # macro
mmSH_MEM_BASES = 0x10aa # macro
mmSH_MEM_BASES_BASE_IDX = 0 # macro
mmSP_CONFIG = 0x10ab # macro
mmSP_CONFIG_BASE_IDX = 0 # macro
mmSQ_ARB_CONFIG = 0x10ac # macro
mmSQ_ARB_CONFIG_BASE_IDX = 0 # macro
mmSH_MEM_CONFIG = 0x10ad # macro
mmSH_MEM_CONFIG_BASE_IDX = 0 # macro
mmSQ_SHADER_TBA_LO = 0x10b2 # macro
mmSQ_SHADER_TBA_LO_BASE_IDX = 0 # macro
mmSQ_SHADER_TBA_HI = 0x10b3 # macro
mmSQ_SHADER_TBA_HI_BASE_IDX = 0 # macro
mmSQ_SHADER_TMA_LO = 0x10b4 # macro
mmSQ_SHADER_TMA_LO_BASE_IDX = 0 # macro
mmSQ_SHADER_TMA_HI = 0x10b5 # macro
mmSQ_SHADER_TMA_HI_BASE_IDX = 0 # macro
mmSQG_UTCL0_CNTL1 = 0x10b7 # macro
mmSQG_UTCL0_CNTL1_BASE_IDX = 0 # macro
mmSQG_UTCL0_CNTL2 = 0x10b8 # macro
mmSQG_UTCL0_CNTL2_BASE_IDX = 0 # macro
mmSQG_UTCL0_STATUS = 0x10b9 # macro
mmSQG_UTCL0_STATUS_BASE_IDX = 0 # macro
mmSQG_CONFIG = 0x10ba # macro
mmSQG_CONFIG_BASE_IDX = 0 # macro
mmCC_GC_SHADER_RATE_CONFIG = 0x10bc # macro
mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX = 0 # macro
mmGC_USER_SHADER_RATE_CONFIG = 0x10bd # macro
mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX = 0 # macro
mmSQ_INTERRUPT_AUTO_MASK = 0x10be # macro
mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX = 0 # macro
mmSQ_INTERRUPT_MSG_CTRL = 0x10bf # macro
mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX = 0 # macro
mmSQ_WATCH0_ADDR_H = 0x10d0 # macro
mmSQ_WATCH0_ADDR_H_BASE_IDX = 0 # macro
mmSQ_WATCH0_ADDR_L = 0x10d1 # macro
mmSQ_WATCH0_ADDR_L_BASE_IDX = 0 # macro
mmSQ_WATCH0_CNTL = 0x10d2 # macro
mmSQ_WATCH0_CNTL_BASE_IDX = 0 # macro
mmSQ_WATCH1_ADDR_H = 0x10d3 # macro
mmSQ_WATCH1_ADDR_H_BASE_IDX = 0 # macro
mmSQ_WATCH1_ADDR_L = 0x10d4 # macro
mmSQ_WATCH1_ADDR_L_BASE_IDX = 0 # macro
mmSQ_WATCH1_CNTL = 0x10d5 # macro
mmSQ_WATCH1_CNTL_BASE_IDX = 0 # macro
mmSQ_WATCH2_ADDR_H = 0x10d6 # macro
mmSQ_WATCH2_ADDR_H_BASE_IDX = 0 # macro
mmSQ_WATCH2_ADDR_L = 0x10d7 # macro
mmSQ_WATCH2_ADDR_L_BASE_IDX = 0 # macro
mmSQ_WATCH2_CNTL = 0x10d8 # macro
mmSQ_WATCH2_CNTL_BASE_IDX = 0 # macro
mmSQ_WATCH3_ADDR_H = 0x10d9 # macro
mmSQ_WATCH3_ADDR_H_BASE_IDX = 0 # macro
mmSQ_WATCH3_ADDR_L = 0x10da # macro
mmSQ_WATCH3_ADDR_L_BASE_IDX = 0 # macro
mmSQ_WATCH3_CNTL = 0x10db # macro
mmSQ_WATCH3_CNTL_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_BUF0_BASE = 0x10e0 # macro
mmSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_BUF0_SIZE = 0x10e1 # macro
mmSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_BUF1_BASE = 0x10e2 # macro
mmSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_BUF1_SIZE = 0x10e3 # macro
mmSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_WPTR = 0x10e4 # macro
mmSQ_THREAD_TRACE_WPTR_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_MASK = 0x10e5 # macro
mmSQ_THREAD_TRACE_MASK_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_TOKEN_MASK = 0x10e6 # macro
mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_CTRL = 0x10e7 # macro
mmSQ_THREAD_TRACE_CTRL_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_STATUS = 0x10e8 # macro
mmSQ_THREAD_TRACE_STATUS_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_DROPPED_CNTR = 0x10e9 # macro
mmSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_GFX_DRAW_CNTR = 0x10eb # macro
mmSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_GFX_MARKER_CNTR = 0x10ec # macro
mmSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR = 0x10ed # macro
mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR = 0x10ee # macro
mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX = 0 # macro
mmSQ_THREAD_TRACE_STATUS2 = 0x10ef # macro
mmSQ_THREAD_TRACE_STATUS2_BASE_IDX = 0 # macro
mmSQ_IND_INDEX = 0x1118 # macro
mmSQ_IND_INDEX_BASE_IDX = 0 # macro
mmSQ_IND_DATA = 0x1119 # macro
mmSQ_IND_DATA_BASE_IDX = 0 # macro
mmSQ_CMD = 0x111b # macro
mmSQ_CMD_BASE_IDX = 0 # macro
mmSQ_TIME_HI = 0x111c # macro
mmSQ_TIME_HI_BASE_IDX = 0 # macro
mmSQ_TIME_LO = 0x111d # macro
mmSQ_TIME_LO_BASE_IDX = 0 # macro
mmSQ_LB_CTR_CTRL = 0x1138 # macro
mmSQ_LB_CTR_CTRL_BASE_IDX = 0 # macro
mmSQ_LB_DATA0 = 0x1139 # macro
mmSQ_LB_DATA0_BASE_IDX = 0 # macro
mmSQ_LB_DATA1 = 0x113a # macro
mmSQ_LB_DATA1_BASE_IDX = 0 # macro
mmSQ_LB_DATA2 = 0x113b # macro
mmSQ_LB_DATA2_BASE_IDX = 0 # macro
mmSQ_LB_DATA3 = 0x113c # macro
mmSQ_LB_DATA3_BASE_IDX = 0 # macro
mmSQ_LB_CTR_SEL0 = 0x113d # macro
mmSQ_LB_CTR_SEL0_BASE_IDX = 0 # macro
mmSQ_LB_CTR_SEL1 = 0x113e # macro
mmSQ_LB_CTR_SEL1_BASE_IDX = 0 # macro
mmSQ_EDC_CNT = 0x1146 # macro
mmSQ_EDC_CNT_BASE_IDX = 0 # macro
mmSQ_EDC_FUE_CNTL = 0x1147 # macro
mmSQ_EDC_FUE_CNTL_BASE_IDX = 0 # macro
mmSQ_WREXEC_EXEC_HI = 0x1151 # macro
mmSQ_WREXEC_EXEC_HI_BASE_IDX = 0 # macro
mmSQ_WREXEC_EXEC_LO = 0x1151 # macro
mmSQ_WREXEC_EXEC_LO_BASE_IDX = 0 # macro
mmSQC_ICACHE_UTCL0_CNTL1 = 0x1173 # macro
mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX = 0 # macro
mmSQC_ICACHE_UTCL0_CNTL2 = 0x1174 # macro
mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX = 0 # macro
mmSQC_DCACHE_UTCL0_CNTL1 = 0x1175 # macro
mmSQC_DCACHE_UTCL0_CNTL1_BASE_IDX = 0 # macro
mmSQC_DCACHE_UTCL0_CNTL2 = 0x1176 # macro
mmSQC_DCACHE_UTCL0_CNTL2_BASE_IDX = 0 # macro
mmSQC_ICACHE_UTCL0_STATUS = 0x1177 # macro
mmSQC_ICACHE_UTCL0_STATUS_BASE_IDX = 0 # macro
mmSQC_DCACHE_UTCL0_STATUS = 0x1178 # macro
mmSQC_DCACHE_UTCL0_STATUS_BASE_IDX = 0 # macro
mmSX_DEBUG_1 = 0x11b8 # macro
mmSX_DEBUG_1_BASE_IDX = 0 # macro
mmSPI_PS_MAX_WAVE_ID = 0x11da # macro
mmSPI_PS_MAX_WAVE_ID_BASE_IDX = 0 # macro
mmSPI_START_PHASE = 0x11db # macro
mmSPI_START_PHASE_BASE_IDX = 0 # macro
mmSPI_GFX_CNTL = 0x11dc # macro
mmSPI_GFX_CNTL_BASE_IDX = 0 # macro
mmSPI_DSM_CNTL = 0x11e3 # macro
mmSPI_DSM_CNTL_BASE_IDX = 0 # macro
mmSPI_DSM_CNTL2 = 0x11e4 # macro
mmSPI_DSM_CNTL2_BASE_IDX = 0 # macro
mmSPI_EDC_CNT = 0x11e5 # macro
mmSPI_EDC_CNT_BASE_IDX = 0 # macro
mmSPI_USER_ACCUM_VMID_CNTL = 0x11eb # macro
mmSPI_USER_ACCUM_VMID_CNTL_BASE_IDX = 0 # macro
mmSPI_CONFIG_CNTL = 0x11ec # macro
mmSPI_CONFIG_CNTL_BASE_IDX = 0 # macro
mmSPI_WAVE_LIMIT_CNTL = 0x11ed # macro
mmSPI_WAVE_LIMIT_CNTL_BASE_IDX = 0 # macro
mmSPI_CONFIG_CNTL_2 = 0x11ee # macro
mmSPI_CONFIG_CNTL_2_BASE_IDX = 0 # macro
mmSPI_CONFIG_CNTL_1 = 0x11ef # macro
mmSPI_CONFIG_CNTL_1_BASE_IDX = 0 # macro
mmSPI_CONFIG_PS_CU_EN = 0x11f2 # macro
mmSPI_CONFIG_PS_CU_EN_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_CNTL = 0x124a # macro
mmSPI_WF_LIFETIME_CNTL_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_LIMIT_0 = 0x124b # macro
mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_LIMIT_1 = 0x124c # macro
mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_LIMIT_2 = 0x124d # macro
mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_LIMIT_3 = 0x124e # macro
mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_LIMIT_4 = 0x124f # macro
mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_LIMIT_5 = 0x1250 # macro
mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_0 = 0x1255 # macro
mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_1 = 0x1256 # macro
mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_2 = 0x1257 # macro
mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_4 = 0x1259 # macro
mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_6 = 0x125b # macro
mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_7 = 0x125c # macro
mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_8 = 0x125d # macro
mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_9 = 0x125e # macro
mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_11 = 0x1260 # macro
mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_13 = 0x1262 # macro
mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_14 = 0x1263 # macro
mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_15 = 0x1264 # macro
mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_16 = 0x1265 # macro
mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_17 = 0x1266 # macro
mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_18 = 0x1267 # macro
mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_19 = 0x1268 # macro
mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_20 = 0x1269 # macro
mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX = 0 # macro
mmSPI_WF_LIFETIME_STATUS_21 = 0x126b # macro
mmSPI_WF_LIFETIME_STATUS_21_BASE_IDX = 0 # macro
mmSPI_LB_CTR_CTRL = 0x1274 # macro
mmSPI_LB_CTR_CTRL_BASE_IDX = 0 # macro
mmSPI_LB_WGP_MASK = 0x1275 # macro
mmSPI_LB_WGP_MASK_BASE_IDX = 0 # macro
mmSPI_LB_DATA_REG = 0x1276 # macro
mmSPI_LB_DATA_REG_BASE_IDX = 0 # macro
mmSPI_PG_ENABLE_STATIC_WGP_MASK = 0x1277 # macro
mmSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX = 0 # macro
mmSPI_GDS_CREDITS = 0x1278 # macro
mmSPI_GDS_CREDITS_BASE_IDX = 0 # macro
mmSPI_SX_EXPORT_BUFFER_SIZES = 0x1279 # macro
mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX = 0 # macro
mmSPI_SX_SCOREBOARD_BUFFER_SIZES = 0x127a # macro
mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX = 0 # macro
mmSPI_CSQ_WF_ACTIVE_STATUS = 0x127b # macro
mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX = 0 # macro
mmSPI_CSQ_WF_ACTIVE_COUNT_0 = 0x127c # macro
mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX = 0 # macro
mmSPI_CSQ_WF_ACTIVE_COUNT_1 = 0x127d # macro
mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX = 0 # macro
mmSPI_CSQ_WF_ACTIVE_COUNT_2 = 0x127e # macro
mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX = 0 # macro
mmSPI_CSQ_WF_ACTIVE_COUNT_3 = 0x127f # macro
mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX = 0 # macro
mmSPI_LB_DATA_WAVES = 0x1284 # macro
mmSPI_LB_DATA_WAVES_BASE_IDX = 0 # macro
mmSPI_LB_DATA_PERWGP_WAVE_HSGS = 0x1285 # macro
mmSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX = 0 # macro
mmSPI_LB_DATA_PERWGP_WAVE_VSPS = 0x1286 # macro
mmSPI_LB_DATA_PERWGP_WAVE_VSPS_BASE_IDX = 0 # macro
mmSPI_LB_DATA_PERWGP_WAVE_CS = 0x1287 # macro
mmSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX = 0 # macro
mmSPI_P0_TRAP_SCREEN_PSBA_LO = 0x128c # macro
mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro
mmSPI_P0_TRAP_SCREEN_PSBA_HI = 0x128d # macro
mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro
mmSPI_P0_TRAP_SCREEN_PSMA_LO = 0x128e # macro
mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro
mmSPI_P0_TRAP_SCREEN_PSMA_HI = 0x128f # macro
mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro
mmSPI_P0_TRAP_SCREEN_GPR_MIN = 0x1290 # macro
mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro
mmSPI_P1_TRAP_SCREEN_PSBA_LO = 0x1291 # macro
mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro
mmSPI_P1_TRAP_SCREEN_PSBA_HI = 0x1292 # macro
mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro
mmSPI_P1_TRAP_SCREEN_PSMA_LO = 0x1293 # macro
mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro
mmSPI_P1_TRAP_SCREEN_PSMA_HI = 0x1294 # macro
mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro
mmSPI_P1_TRAP_SCREEN_GPR_MIN = 0x1295 # macro
mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro
mmTD_STATUS = 0x12c6 # macro
mmTD_STATUS_BASE_IDX = 0 # macro
mmTD_DSM_CNTL = 0x12cf # macro
mmTD_DSM_CNTL_BASE_IDX = 0 # macro
mmTD_DSM_CNTL2 = 0x12d0 # macro
mmTD_DSM_CNTL2_BASE_IDX = 0 # macro
mmTD_SCRATCH = 0x12d3 # macro
mmTD_SCRATCH_BASE_IDX = 0 # macro
mmTA_CNTL = 0x12e1 # macro
mmTA_CNTL_BASE_IDX = 0 # macro
mmTA_RESERVED_010C = 0x12e3 # macro
mmTA_RESERVED_010C_BASE_IDX = 0 # macro
mmTA_STATUS = 0x12e8 # macro
mmTA_STATUS_BASE_IDX = 0 # macro
mmTA_SCRATCH = 0x1304 # macro
mmTA_SCRATCH_BASE_IDX = 0 # macro
mmGDS_CONFIG = 0x1360 # macro
mmGDS_CONFIG_BASE_IDX = 0 # macro
mmGDS_CNTL_STATUS = 0x1361 # macro
mmGDS_CNTL_STATUS_BASE_IDX = 0 # macro
mmGDS_ENHANCE = 0x1362 # macro
mmGDS_ENHANCE_BASE_IDX = 0 # macro
mmGDS_PROTECTION_FAULT = 0x1363 # macro
mmGDS_PROTECTION_FAULT_BASE_IDX = 0 # macro
mmGDS_VM_PROTECTION_FAULT = 0x1364 # macro
mmGDS_VM_PROTECTION_FAULT_BASE_IDX = 0 # macro
mmGDS_EDC_CNT = 0x1365 # macro
mmGDS_EDC_CNT_BASE_IDX = 0 # macro
mmGDS_EDC_GRBM_CNT = 0x1366 # macro
mmGDS_EDC_GRBM_CNT_BASE_IDX = 0 # macro
mmGDS_EDC_OA_DED = 0x1367 # macro
mmGDS_EDC_OA_DED_BASE_IDX = 0 # macro
mmGDS_DSM_CNTL = 0x136a # macro
mmGDS_DSM_CNTL_BASE_IDX = 0 # macro
mmGDS_EDC_OA_PHY_CNT = 0x136b # macro
mmGDS_EDC_OA_PHY_CNT_BASE_IDX = 0 # macro
mmGDS_EDC_OA_PIPE_CNT = 0x136c # macro
mmGDS_EDC_OA_PIPE_CNT_BASE_IDX = 0 # macro
mmGDS_DSM_CNTL2 = 0x136d # macro
mmGDS_DSM_CNTL2_BASE_IDX = 0 # macro
mmGDS_WD_GDS_CSB = 0x136e # macro
mmGDS_WD_GDS_CSB_BASE_IDX = 0 # macro
mmDB_DEBUG = 0x13ac # macro
mmDB_DEBUG_BASE_IDX = 0 # macro
mmDB_DEBUG2 = 0x13ad # macro
mmDB_DEBUG2_BASE_IDX = 0 # macro
mmDB_DEBUG3 = 0x13ae # macro
mmDB_DEBUG3_BASE_IDX = 0 # macro
mmDB_DEBUG4 = 0x13af # macro
mmDB_DEBUG4_BASE_IDX = 0 # macro
mmDB_ETILE_STUTTER_CONTROL = 0x13b0 # macro
mmDB_ETILE_STUTTER_CONTROL_BASE_IDX = 0 # macro
mmDB_LTILE_STUTTER_CONTROL = 0x13b1 # macro
mmDB_LTILE_STUTTER_CONTROL_BASE_IDX = 0 # macro
mmDB_EQUAD_STUTTER_CONTROL = 0x13b2 # macro
mmDB_EQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro
mmDB_LQUAD_STUTTER_CONTROL = 0x13b3 # macro
mmDB_LQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro
mmDB_CREDIT_LIMIT = 0x13b4 # macro
mmDB_CREDIT_LIMIT_BASE_IDX = 0 # macro
mmDB_WATERMARKS = 0x13b5 # macro
mmDB_WATERMARKS_BASE_IDX = 0 # macro
mmDB_SUBTILE_CONTROL = 0x13b6 # macro
mmDB_SUBTILE_CONTROL_BASE_IDX = 0 # macro
mmDB_FREE_CACHELINES = 0x13b7 # macro
mmDB_FREE_CACHELINES_BASE_IDX = 0 # macro
mmDB_FIFO_DEPTH1 = 0x13b8 # macro
mmDB_FIFO_DEPTH1_BASE_IDX = 0 # macro
mmDB_FIFO_DEPTH2 = 0x13b9 # macro
mmDB_FIFO_DEPTH2_BASE_IDX = 0 # macro
mmDB_LAST_OF_BURST_CONFIG = 0x13ba # macro
mmDB_LAST_OF_BURST_CONFIG_BASE_IDX = 0 # macro
mmDB_RING_CONTROL = 0x13bb # macro
mmDB_RING_CONTROL_BASE_IDX = 0 # macro
mmDB_MEM_ARB_WATERMARKS = 0x13bc # macro
mmDB_MEM_ARB_WATERMARKS_BASE_IDX = 0 # macro
mmDB_FIFO_DEPTH3 = 0x13bd # macro
mmDB_FIFO_DEPTH3_BASE_IDX = 0 # macro
mmDB_RMI_BC_GL2_CACHE_CONTROL = 0x13be # macro
mmDB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX = 0 # macro
mmDB_EXCEPTION_CONTROL = 0x13bf # macro
mmDB_EXCEPTION_CONTROL_BASE_IDX = 0 # macro
mmDB_DFSM_CONFIG = 0x13d0 # macro
mmDB_DFSM_CONFIG_BASE_IDX = 0 # macro
mmDB_DEBUG5 = 0x13d1 # macro
mmDB_DEBUG5_BASE_IDX = 0 # macro
mmDB_DFSM_TILES_IN_FLIGHT = 0x13d2 # macro
mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX = 0 # macro
mmDB_DFSM_PRIMS_IN_FLIGHT = 0x13d3 # macro
mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX = 0 # macro
mmDB_DFSM_WATCHDOG = 0x13d4 # macro
mmDB_DFSM_WATCHDOG_BASE_IDX = 0 # macro
mmDB_DFSM_FLUSH_ENABLE = 0x13d5 # macro
mmDB_DFSM_FLUSH_ENABLE_BASE_IDX = 0 # macro
mmDB_DFSM_FLUSH_AUX_EVENT = 0x13d6 # macro
mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX = 0 # macro
mmDB_FGCG_SRAMS_CLK_CTRL = 0x13d7 # macro
mmDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX = 0 # macro
mmDB_FGCG_INTERFACES_CLK_CTRL = 0x13d8 # macro
mmDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX = 0 # macro
mmCC_RB_REDUNDANCY = 0x13dc # macro
mmCC_RB_REDUNDANCY_BASE_IDX = 0 # macro
mmCC_RB_BACKEND_DISABLE = 0x13dd # macro
mmCC_RB_BACKEND_DISABLE_BASE_IDX = 0 # macro
mmGB_ADDR_CONFIG = 0x13de # macro
mmGB_ADDR_CONFIG_BASE_IDX = 0 # macro
mmGB_BACKEND_MAP = 0x13df # macro
mmGB_BACKEND_MAP_BASE_IDX = 0 # macro
mmGB_GPU_ID = 0x13e0 # macro
mmGB_GPU_ID_BASE_IDX = 0 # macro
mmCC_RB_DAISY_CHAIN = 0x13e1 # macro
mmCC_RB_DAISY_CHAIN_BASE_IDX = 0 # macro
mmGB_ADDR_CONFIG_READ = 0x13e2 # macro
mmGB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro
mmCB_HW_CONTROL_4 = 0x1422 # macro
mmCB_HW_CONTROL_4_BASE_IDX = 0 # macro
mmCB_HW_CONTROL_3 = 0x1423 # macro
mmCB_HW_CONTROL_3_BASE_IDX = 0 # macro
mmCB_HW_CONTROL = 0x1424 # macro
mmCB_HW_CONTROL_BASE_IDX = 0 # macro
mmCB_HW_CONTROL_1 = 0x1425 # macro
mmCB_HW_CONTROL_1_BASE_IDX = 0 # macro
mmCB_HW_CONTROL_2 = 0x1426 # macro
mmCB_HW_CONTROL_2_BASE_IDX = 0 # macro
mmCB_DCC_CONFIG = 0x1427 # macro
mmCB_DCC_CONFIG_BASE_IDX = 0 # macro
mmCB_HW_MEM_ARBITER_RD = 0x1428 # macro
mmCB_HW_MEM_ARBITER_RD_BASE_IDX = 0 # macro
mmCB_HW_MEM_ARBITER_WR = 0x1429 # macro
mmCB_HW_MEM_ARBITER_WR_BASE_IDX = 0 # macro
mmCB_RMI_BC_GL2_CACHE_CONTROL = 0x142a # macro
mmCB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX = 0 # macro
mmCB_STUTTER_CONTROL_CMASK_RDLAT = 0x142b # macro
mmCB_STUTTER_CONTROL_CMASK_RDLAT_BASE_IDX = 0 # macro
mmCB_STUTTER_CONTROL_FMASK_RDLAT = 0x142c # macro
mmCB_STUTTER_CONTROL_FMASK_RDLAT_BASE_IDX = 0 # macro
mmCB_STUTTER_CONTROL_COLOR_RDLAT = 0x142d # macro
mmCB_STUTTER_CONTROL_COLOR_RDLAT_BASE_IDX = 0 # macro
mmCB_CACHE_EVICT_POINTS = 0x142e # macro
mmCB_CACHE_EVICT_POINTS_BASE_IDX = 0 # macro
mmGC_USER_RB_REDUNDANCY = 0x147e # macro
mmGC_USER_RB_REDUNDANCY_BASE_IDX = 0 # macro
mmGC_USER_RB_BACKEND_DISABLE = 0x147f # macro
mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX = 0 # macro
mmGCEA_MISC = 0x14a2 # macro
mmGCEA_MISC_BASE_IDX = 0 # macro
mmGCEA_LATENCY_SAMPLING = 0x14a3 # macro
mmGCEA_LATENCY_SAMPLING_BASE_IDX = 0 # macro
mmGCEA_DSM_CNTL = 0x14b4 # macro
mmGCEA_DSM_CNTL_BASE_IDX = 0 # macro
mmGCEA_DSM_CNTLA = 0x14b5 # macro
mmGCEA_DSM_CNTLA_BASE_IDX = 0 # macro
mmGCEA_DSM_CNTLB = 0x14b6 # macro
mmGCEA_DSM_CNTLB_BASE_IDX = 0 # macro
mmGCEA_DSM_CNTL2 = 0x14b7 # macro
mmGCEA_DSM_CNTL2_BASE_IDX = 0 # macro
mmGCEA_DSM_CNTL2A = 0x14b8 # macro
mmGCEA_DSM_CNTL2A_BASE_IDX = 0 # macro
mmGCEA_DSM_CNTL2B = 0x14b9 # macro
mmGCEA_DSM_CNTL2B_BASE_IDX = 0 # macro
mmGCEA_GL2C_XBR_CREDITS = 0x14ba # macro
mmGCEA_GL2C_XBR_CREDITS_BASE_IDX = 0 # macro
mmGCEA_GL2C_XBR_MAXBURST = 0x14bb # macro
mmGCEA_GL2C_XBR_MAXBURST_BASE_IDX = 0 # macro
mmGCEA_PROBE_CNTL = 0x14bc # macro
mmGCEA_PROBE_CNTL_BASE_IDX = 0 # macro
mmGCEA_PROBE_MAP = 0x14bd # macro
mmGCEA_PROBE_MAP_BASE_IDX = 0 # macro
mmGCEA_ERR_STATUS = 0x14be # macro
mmGCEA_ERR_STATUS_BASE_IDX = 0 # macro
mmGCEA_MISC2 = 0x14bf # macro
mmGCEA_MISC2_BASE_IDX = 0 # macro
mmSPI_PQEV_CTRL = 0x14c0 # macro
mmSPI_PQEV_CTRL_BASE_IDX = 0 # macro
mmSPI_EXP_THROTTLE_CTRL = 0x14c3 # macro
mmSPI_EXP_THROTTLE_CTRL_BASE_IDX = 0 # macro
mmGCEA_RRET_MEM_RESERVE = 0x1518 # macro
mmGCEA_RRET_MEM_RESERVE_BASE_IDX = 0 # macro
mmRMI_GENERAL_CNTL = 0x1520 # macro
mmRMI_GENERAL_CNTL_BASE_IDX = 0 # macro
mmRMI_GENERAL_CNTL1 = 0x1521 # macro
mmRMI_GENERAL_CNTL1_BASE_IDX = 0 # macro
mmRMI_GENERAL_STATUS = 0x1522 # macro
mmRMI_GENERAL_STATUS_BASE_IDX = 0 # macro
mmRMI_SUBBLOCK_STATUS0 = 0x1523 # macro
mmRMI_SUBBLOCK_STATUS0_BASE_IDX = 0 # macro
mmRMI_SUBBLOCK_STATUS1 = 0x1524 # macro
mmRMI_SUBBLOCK_STATUS1_BASE_IDX = 0 # macro
mmRMI_SUBBLOCK_STATUS2 = 0x1525 # macro
mmRMI_SUBBLOCK_STATUS2_BASE_IDX = 0 # macro
mmRMI_SUBBLOCK_STATUS3 = 0x1526 # macro
mmRMI_SUBBLOCK_STATUS3_BASE_IDX = 0 # macro
mmRMI_XBAR_CONFIG = 0x1527 # macro
mmRMI_XBAR_CONFIG_BASE_IDX = 0 # macro
mmRMI_PROBE_POP_LOGIC_CNTL = 0x1528 # macro
mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX = 0 # macro
mmRMI_UTC_XNACK_N_MISC_CNTL = 0x1529 # macro
mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX = 0 # macro
mmRMI_DEMUX_CNTL = 0x152a # macro
mmRMI_DEMUX_CNTL_BASE_IDX = 0 # macro
mmRMI_UTCL1_CNTL1 = 0x152b # macro
mmRMI_UTCL1_CNTL1_BASE_IDX = 0 # macro
mmRMI_UTCL1_CNTL2 = 0x152c # macro
mmRMI_UTCL1_CNTL2_BASE_IDX = 0 # macro
mmRMI_UTC_UNIT_CONFIG = 0x152d # macro
mmRMI_UTC_UNIT_CONFIG_BASE_IDX = 0 # macro
mmRMI_TCIW_FORMATTER0_CNTL = 0x152e # macro
mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX = 0 # macro
mmRMI_TCIW_FORMATTER1_CNTL = 0x152f # macro
mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX = 0 # macro
mmRMI_SCOREBOARD_CNTL = 0x1530 # macro
mmRMI_SCOREBOARD_CNTL_BASE_IDX = 0 # macro
mmRMI_SCOREBOARD_STATUS0 = 0x1531 # macro
mmRMI_SCOREBOARD_STATUS0_BASE_IDX = 0 # macro
mmRMI_SCOREBOARD_STATUS1 = 0x1532 # macro
mmRMI_SCOREBOARD_STATUS1_BASE_IDX = 0 # macro
mmRMI_SCOREBOARD_STATUS2 = 0x1533 # macro
mmRMI_SCOREBOARD_STATUS2_BASE_IDX = 0 # macro
mmRMI_XBAR_ARBITER_CONFIG = 0x1534 # macro
mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX = 0 # macro
mmRMI_XBAR_ARBITER_CONFIG_1 = 0x1535 # macro
mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX = 0 # macro
mmRMI_CLOCK_CNTRL = 0x1536 # macro
mmRMI_CLOCK_CNTRL_BASE_IDX = 0 # macro
mmRMI_UTCL1_STATUS = 0x1537 # macro
mmRMI_UTCL1_STATUS_BASE_IDX = 0 # macro
mmRMI_RB_GLX_CID_MAP = 0x1538 # macro
mmRMI_RB_GLX_CID_MAP_BASE_IDX = 0 # macro
mmRMI_SPARE = 0x153f # macro
mmRMI_SPARE_BASE_IDX = 0 # macro
mmRMI_SPARE_1 = 0x1540 # macro
mmRMI_SPARE_1_BASE_IDX = 0 # macro
mmRMI_SPARE_2 = 0x1541 # macro
mmRMI_SPARE_2_BASE_IDX = 0 # macro
mmCC_RMI_REDUNDANCY = 0x1542 # macro
mmCC_RMI_REDUNDANCY_BASE_IDX = 0 # macro
mmGC_USER_RMI_REDUNDANCY = 0x1543 # macro
mmGC_USER_RMI_REDUNDANCY_BASE_IDX = 0 # macro
mmGCR_GENERAL_CNTL = 0x1580 # macro
mmGCR_GENERAL_CNTL_BASE_IDX = 0 # macro
mmGCR_CMD_STATUS = 0x1582 # macro
mmGCR_CMD_STATUS_BASE_IDX = 0 # macro
mmGCR_SPARE = 0x1583 # macro
mmGCR_SPARE_BASE_IDX = 0 # macro
mmPMM_GENERAL_CNTL = 0x1585 # macro
mmPMM_GENERAL_CNTL_BASE_IDX = 0 # macro
mmGCR_PIO_CNTL = 0x1586 # macro
mmGCR_PIO_CNTL_BASE_IDX = 0 # macro
mmGCR_PIO_DATA = 0x1587 # macro
mmGCR_PIO_DATA_BASE_IDX = 0 # macro
mmUTCL1_CTRL = 0x1588 # macro
mmUTCL1_CTRL_BASE_IDX = 0 # macro
mmUTCL1_ALOG = 0x1589 # macro
mmUTCL1_ALOG_BASE_IDX = 0 # macro
mmUTCL1_UTCL0_INVREQ_DISABLE = 0x158a # macro
mmUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX = 0 # macro
mmGCRD_SA_TARGETS_DISABLE = 0x158b # macro
mmGCRD_SA_TARGETS_DISABLE_BASE_IDX = 0 # macro
mmUTCL1_STATUS = 0x158c # macro
mmUTCL1_STATUS_BASE_IDX = 0 # macro
mmGCVM_L2_CNTL = 0x15bc # macro
mmGCVM_L2_CNTL_BASE_IDX = 0 # macro
mmGCVM_L2_CNTL2 = 0x15bd # macro
mmGCVM_L2_CNTL2_BASE_IDX = 0 # macro
mmGCVM_L2_CNTL3 = 0x15be # macro
mmGCVM_L2_CNTL3_BASE_IDX = 0 # macro
mmGCVM_L2_STATUS = 0x15bf # macro
mmGCVM_L2_STATUS_BASE_IDX = 0 # macro
mmGCVM_DUMMY_PAGE_FAULT_CNTL = 0x15c0 # macro
mmGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX = 0 # macro
mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 = 0x15c1 # macro
mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 = 0x15c2 # macro
mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_CNTL = 0x15c3 # macro
mmGCVM_INVALIDATE_CNTL_BASE_IDX = 0 # macro
mmGCVM_L2_PROTECTION_FAULT_CNTL = 0x15c4 # macro
mmGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX = 0 # macro
mmGCVM_L2_PROTECTION_FAULT_CNTL2 = 0x15c5 # macro
mmGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX = 0 # macro
mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3 = 0x15c6 # macro
mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX = 0 # macro
mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4 = 0x15c7 # macro
mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX = 0 # macro
mmGCVM_L2_PROTECTION_FAULT_STATUS = 0x15c8 # macro
mmGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX = 0 # macro
mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32 = 0x15c9 # macro
mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32 = 0x15ca # macro
mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 = 0x15cb # macro
mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 = 0x15cc # macro
mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_DEBUG = 0x15cd # macro
mmGCVM_DEBUG_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 = 0x15ce # macro
mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 = 0x15cf # macro
mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 = 0x15d0 # macro
mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 = 0x15d1 # macro
mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 = 0x15d2 # macro
mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 = 0x15d3 # macro
mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX = 0 # macro
mmGCVM_L2_CNTL4 = 0x15d4 # macro
mmGCVM_L2_CNTL4_BASE_IDX = 0 # macro
mmGCVM_L2_MM_GROUP_RT_CLASSES = 0x15d5 # macro
mmGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 # macro
mmGCVM_L2_BANK_SELECT_RESERVED_CID = 0x15d6 # macro
mmGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX = 0 # macro
mmGCVM_L2_BANK_SELECT_RESERVED_CID2 = 0x15d7 # macro
mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX = 0 # macro
mmGCVM_L2_CACHE_PARITY_CNTL = 0x15d8 # macro
mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX = 0 # macro
mmGCVM_L2_IH_LOG_CNTL = 0x15d9 # macro
mmGCVM_L2_IH_LOG_CNTL_BASE_IDX = 0 # macro
mmGCVM_L2_CNTL5 = 0x15dc # macro
mmGCVM_L2_CNTL5_BASE_IDX = 0 # macro
mmGCVM_L2_GCR_CNTL = 0x15dd # macro
mmGCVM_L2_GCR_CNTL_BASE_IDX = 0 # macro
mmGCVML2_WALKER_MACRO_THROTTLE_TIME = 0x15de # macro
mmGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX = 0 # macro
mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT = 0x15df # macro
mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro
mmGCVML2_WALKER_MICRO_THROTTLE_TIME = 0x15e0 # macro
mmGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX = 0 # macro
mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT = 0x15e1 # macro
mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro
mmGCVM_L2_PTE_CACHE_DUMP_CNTL = 0x15e3 # macro
mmGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX = 0 # macro
mmGCVM_L2_PTE_CACHE_DUMP_READ = 0x15e4 # macro
mmGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX = 0 # macro
mmGCVM_CONTEXT0_CNTL = 0x15fc # macro
mmGCVM_CONTEXT0_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT1_CNTL = 0x15fd # macro
mmGCVM_CONTEXT1_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT2_CNTL = 0x15fe # macro
mmGCVM_CONTEXT2_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT3_CNTL = 0x15ff # macro
mmGCVM_CONTEXT3_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT4_CNTL = 0x1600 # macro
mmGCVM_CONTEXT4_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT5_CNTL = 0x1601 # macro
mmGCVM_CONTEXT5_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT6_CNTL = 0x1602 # macro
mmGCVM_CONTEXT6_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT7_CNTL = 0x1603 # macro
mmGCVM_CONTEXT7_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT8_CNTL = 0x1604 # macro
mmGCVM_CONTEXT8_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT9_CNTL = 0x1605 # macro
mmGCVM_CONTEXT9_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT10_CNTL = 0x1606 # macro
mmGCVM_CONTEXT10_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT11_CNTL = 0x1607 # macro
mmGCVM_CONTEXT11_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT12_CNTL = 0x1608 # macro
mmGCVM_CONTEXT12_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT13_CNTL = 0x1609 # macro
mmGCVM_CONTEXT13_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT14_CNTL = 0x160a # macro
mmGCVM_CONTEXT14_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXT15_CNTL = 0x160b # macro
mmGCVM_CONTEXT15_CNTL_BASE_IDX = 0 # macro
mmGCVM_CONTEXTS_DISABLE = 0x160c # macro
mmGCVM_CONTEXTS_DISABLE_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG0_SEM = 0x160d # macro
mmGCVM_INVALIDATE_ENG0_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG1_SEM = 0x160e # macro
mmGCVM_INVALIDATE_ENG1_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG2_SEM = 0x160f # macro
mmGCVM_INVALIDATE_ENG2_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG3_SEM = 0x1610 # macro
mmGCVM_INVALIDATE_ENG3_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG4_SEM = 0x1611 # macro
mmGCVM_INVALIDATE_ENG4_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG5_SEM = 0x1612 # macro
mmGCVM_INVALIDATE_ENG5_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG6_SEM = 0x1613 # macro
mmGCVM_INVALIDATE_ENG6_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG7_SEM = 0x1614 # macro
mmGCVM_INVALIDATE_ENG7_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG8_SEM = 0x1615 # macro
mmGCVM_INVALIDATE_ENG8_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG9_SEM = 0x1616 # macro
mmGCVM_INVALIDATE_ENG9_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG10_SEM = 0x1617 # macro
mmGCVM_INVALIDATE_ENG10_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG11_SEM = 0x1618 # macro
mmGCVM_INVALIDATE_ENG11_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG12_SEM = 0x1619 # macro
mmGCVM_INVALIDATE_ENG12_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG13_SEM = 0x161a # macro
mmGCVM_INVALIDATE_ENG13_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG14_SEM = 0x161b # macro
mmGCVM_INVALIDATE_ENG14_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG15_SEM = 0x161c # macro
mmGCVM_INVALIDATE_ENG15_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG16_SEM = 0x161d # macro
mmGCVM_INVALIDATE_ENG16_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG17_SEM = 0x161e # macro
mmGCVM_INVALIDATE_ENG17_SEM_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG0_REQ = 0x161f # macro
mmGCVM_INVALIDATE_ENG0_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG1_REQ = 0x1620 # macro
mmGCVM_INVALIDATE_ENG1_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG2_REQ = 0x1621 # macro
mmGCVM_INVALIDATE_ENG2_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG3_REQ = 0x1622 # macro
mmGCVM_INVALIDATE_ENG3_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG4_REQ = 0x1623 # macro
mmGCVM_INVALIDATE_ENG4_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG5_REQ = 0x1624 # macro
mmGCVM_INVALIDATE_ENG5_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG6_REQ = 0x1625 # macro
mmGCVM_INVALIDATE_ENG6_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG7_REQ = 0x1626 # macro
mmGCVM_INVALIDATE_ENG7_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG8_REQ = 0x1627 # macro
mmGCVM_INVALIDATE_ENG8_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG9_REQ = 0x1628 # macro
mmGCVM_INVALIDATE_ENG9_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG10_REQ = 0x1629 # macro
mmGCVM_INVALIDATE_ENG10_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG11_REQ = 0x162a # macro
mmGCVM_INVALIDATE_ENG11_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG12_REQ = 0x162b # macro
mmGCVM_INVALIDATE_ENG12_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG13_REQ = 0x162c # macro
mmGCVM_INVALIDATE_ENG13_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG14_REQ = 0x162d # macro
mmGCVM_INVALIDATE_ENG14_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG15_REQ = 0x162e # macro
mmGCVM_INVALIDATE_ENG15_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG16_REQ = 0x162f # macro
mmGCVM_INVALIDATE_ENG16_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG17_REQ = 0x1630 # macro
mmGCVM_INVALIDATE_ENG17_REQ_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG0_ACK = 0x1631 # macro
mmGCVM_INVALIDATE_ENG0_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG1_ACK = 0x1632 # macro
mmGCVM_INVALIDATE_ENG1_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG2_ACK = 0x1633 # macro
mmGCVM_INVALIDATE_ENG2_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG3_ACK = 0x1634 # macro
mmGCVM_INVALIDATE_ENG3_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG4_ACK = 0x1635 # macro
mmGCVM_INVALIDATE_ENG4_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG5_ACK = 0x1636 # macro
mmGCVM_INVALIDATE_ENG5_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG6_ACK = 0x1637 # macro
mmGCVM_INVALIDATE_ENG6_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG7_ACK = 0x1638 # macro
mmGCVM_INVALIDATE_ENG7_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG8_ACK = 0x1639 # macro
mmGCVM_INVALIDATE_ENG8_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG9_ACK = 0x163a # macro
mmGCVM_INVALIDATE_ENG9_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG10_ACK = 0x163b # macro
mmGCVM_INVALIDATE_ENG10_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG11_ACK = 0x163c # macro
mmGCVM_INVALIDATE_ENG11_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG12_ACK = 0x163d # macro
mmGCVM_INVALIDATE_ENG12_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG13_ACK = 0x163e # macro
mmGCVM_INVALIDATE_ENG13_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG14_ACK = 0x163f # macro
mmGCVM_INVALIDATE_ENG14_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG15_ACK = 0x1640 # macro
mmGCVM_INVALIDATE_ENG15_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG16_ACK = 0x1641 # macro
mmGCVM_INVALIDATE_ENG16_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG17_ACK = 0x1642 # macro
mmGCVM_INVALIDATE_ENG17_ACK_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 = 0x1643 # macro
mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 = 0x1644 # macro
mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 = 0x1645 # macro
mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 = 0x1646 # macro
mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 = 0x1647 # macro
mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 = 0x1648 # macro
mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 = 0x1649 # macro
mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 = 0x164a # macro
mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 = 0x164b # macro
mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 = 0x164c # macro
mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 = 0x164d # macro
mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 = 0x164e # macro
mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 = 0x164f # macro
mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 = 0x1650 # macro
mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 = 0x1651 # macro
mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 = 0x1652 # macro
mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 = 0x1653 # macro
mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 = 0x1654 # macro
mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 = 0x1655 # macro
mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 = 0x1656 # macro
mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 = 0x1657 # macro
mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 = 0x1658 # macro
mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 = 0x1659 # macro
mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 = 0x165a # macro
mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 = 0x165b # macro
mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 = 0x165c # macro
mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 = 0x165d # macro
mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 = 0x165e # macro
mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 = 0x165f # macro
mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 = 0x1660 # macro
mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 = 0x1661 # macro
mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 = 0x1662 # macro
mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 = 0x1663 # macro
mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 = 0x1664 # macro
mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 = 0x1665 # macro
mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 = 0x1666 # macro
mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 = 0x1667 # macro
mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 = 0x1668 # macro
mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 = 0x1669 # macro
mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 = 0x166a # macro
mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 = 0x166b # macro
mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 = 0x166c # macro
mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 = 0x166d # macro
mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 = 0x166e # macro
mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 = 0x166f # macro
mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 = 0x1670 # macro
mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 = 0x1671 # macro
mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 = 0x1672 # macro
mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 = 0x1673 # macro
mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 = 0x1674 # macro
mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 = 0x1675 # macro
mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 = 0x1676 # macro
mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 = 0x1677 # macro
mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 = 0x1678 # macro
mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 = 0x1679 # macro
mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 = 0x167a # macro
mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 = 0x167b # macro
mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 = 0x167c # macro
mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 = 0x167d # macro
mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 = 0x167e # macro
mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 = 0x167f # macro
mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 = 0x1680 # macro
mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 = 0x1681 # macro
mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 = 0x1682 # macro
mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 = 0x1683 # macro
mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 = 0x1684 # macro
mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 = 0x1685 # macro
mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 = 0x1686 # macro
mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 = 0x1687 # macro
mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 = 0x1688 # macro
mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 = 0x1689 # macro
mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 = 0x168a # macro
mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 = 0x168b # macro
mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 = 0x168c # macro
mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 = 0x168d # macro
mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 = 0x168e # macro
mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 = 0x168f # macro
mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 = 0x1690 # macro
mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 = 0x1691 # macro
mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 = 0x1692 # macro
mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 = 0x1693 # macro
mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 = 0x1694 # macro
mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 = 0x1695 # macro
mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 = 0x1696 # macro
mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 = 0x1697 # macro
mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 = 0x1698 # macro
mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 = 0x1699 # macro
mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 = 0x169a # macro
mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 = 0x169b # macro
mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 = 0x169c # macro
mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 = 0x169d # macro
mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 = 0x169e # macro
mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 = 0x169f # macro
mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 = 0x16a0 # macro
mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 = 0x16a1 # macro
mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 = 0x16a2 # macro
mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 = 0x16a3 # macro
mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 = 0x16a4 # macro
mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 = 0x16a5 # macro
mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 = 0x16a6 # macro
mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 = 0x16a7 # macro
mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 = 0x16a8 # macro
mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 = 0x16a9 # macro
mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 = 0x16aa # macro
mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 = 0x16ab # macro
mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 = 0x16ac # macro
mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 = 0x16ad # macro
mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 = 0x16ae # macro
mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 = 0x16af # macro
mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 = 0x16b0 # macro
mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 = 0x16b1 # macro
mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 = 0x16b2 # macro
mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 = 0x16b3 # macro
mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 = 0x16b4 # macro
mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 = 0x16b5 # macro
mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 = 0x16b6 # macro
mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 = 0x16b7 # macro
mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 = 0x16b8 # macro
mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 = 0x16b9 # macro
mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 = 0x16ba # macro
mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 = 0x16bb # macro
mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 = 0x16bc # macro
mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 = 0x16bd # macro
mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 = 0x16be # macro
mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 = 0x16bf # macro
mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 = 0x16c0 # macro
mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 = 0x16c1 # macro
mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 = 0x16c2 # macro
mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 = 0x16c3 # macro
mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 = 0x16c4 # macro
mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 = 0x16c5 # macro
mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 = 0x16c6 # macro
mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16c7 # macro
mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16c8 # macro
mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16c9 # macro
mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16ca # macro
mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16cb # macro
mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16cc # macro
mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16cd # macro
mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16ce # macro
mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16cf # macro
mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d0 # macro
mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d1 # macro
mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d2 # macro
mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d3 # macro
mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d4 # macro
mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d5 # macro
mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d6 # macro
mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d7 # macro
mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
mmGCMC_VM_NB_MMIOBASE = 0x16e0 # macro
mmGCMC_VM_NB_MMIOBASE_BASE_IDX = 0 # macro
mmGCMC_VM_NB_MMIOLIMIT = 0x16e1 # macro
mmGCMC_VM_NB_MMIOLIMIT_BASE_IDX = 0 # macro
mmGCMC_VM_NB_PCI_CTRL = 0x16e2 # macro
mmGCMC_VM_NB_PCI_CTRL_BASE_IDX = 0 # macro
mmGCMC_VM_NB_PCI_ARB = 0x16e3 # macro
mmGCMC_VM_NB_PCI_ARB_BASE_IDX = 0 # macro
mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1 = 0x16e4 # macro
mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX = 0 # macro
mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2 = 0x16e5 # macro
mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX = 0 # macro
mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2 = 0x16e6 # macro
mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX = 0 # macro
mmGCMC_VM_FB_OFFSET = 0x16e7 # macro
mmGCMC_VM_FB_OFFSET_BASE_IDX = 0 # macro
mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x16e8 # macro
mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX = 0 # macro
mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x16e9 # macro
mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX = 0 # macro
mmGCMC_VM_STEERING = 0x16ea # macro
mmGCMC_VM_STEERING_BASE_IDX = 0 # macro
mmGCMC_SHARED_VIRT_RESET_REQ = 0x16eb # macro
mmGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX = 0 # macro
mmGCMC_MEM_POWER_LS = 0x16ec # macro
mmGCMC_MEM_POWER_LS_BASE_IDX = 0 # macro
mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START = 0x16ed # macro
mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX = 0 # macro
mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END = 0x16ee # macro
mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX = 0 # macro
mmGCMC_VM_APT_CNTL = 0x16ef # macro
mmGCMC_VM_APT_CNTL_BASE_IDX = 0 # macro
mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL = 0x16f0 # macro
mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX = 0 # macro
mmGCMC_VM_LOCAL_HBM_ADDRESS_START = 0x16f1 # macro
mmGCMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX = 0 # macro
mmGCMC_VM_LOCAL_HBM_ADDRESS_END = 0x16f2 # macro
mmGCMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX = 0 # macro
mmGCMC_SHARED_ACTIVE_FCN_ID = 0x16f4 # macro
mmGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX = 0 # macro
mmGCMC_SHARED_VIRT_RESET_REQ2 = 0x16f5 # macro
mmGCMC_SHARED_VIRT_RESET_REQ2_BASE_IDX = 0 # macro
mmGCMC_VM_XGMI_LFB_CNTL = 0x16f7 # macro
mmGCMC_VM_XGMI_LFB_CNTL_BASE_IDX = 0 # macro
mmGCMC_VM_XGMI_LFB_SIZE = 0x16f8 # macro
mmGCMC_VM_XGMI_LFB_SIZE_BASE_IDX = 0 # macro
mmGCMC_VM_FB_NOALLOC_CNTL = 0x16f9 # macro
mmGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX = 0 # macro
mmGCUTCL2_HARVEST_BYPASS_GROUPS = 0x16fa # macro
mmGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX = 0 # macro
mmGCMC_VM_FB_LOCATION_BASE = 0x16fc # macro
mmGCMC_VM_FB_LOCATION_BASE_BASE_IDX = 0 # macro
mmGCMC_VM_FB_LOCATION_TOP = 0x16fd # macro
mmGCMC_VM_FB_LOCATION_TOP_BASE_IDX = 0 # macro
mmGCMC_VM_AGP_TOP = 0x16fe # macro
mmGCMC_VM_AGP_TOP_BASE_IDX = 0 # macro
mmGCMC_VM_AGP_BOT = 0x16ff # macro
mmGCMC_VM_AGP_BOT_BASE_IDX = 0 # macro
mmGCMC_VM_AGP_BASE = 0x1700 # macro
mmGCMC_VM_AGP_BASE_BASE_IDX = 0 # macro
mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x1701 # macro
mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX = 0 # macro
mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x1702 # macro
mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX = 0 # macro
mmGCMC_VM_MX_L1_TLB_CNTL = 0x1703 # macro
mmGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX = 0 # macro
mmGCEA_DRAM_RD_CLI2GRP_MAP0 = 0x17a0 # macro
mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro
mmGCEA_DRAM_RD_CLI2GRP_MAP1 = 0x17a1 # macro
mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro
mmGCEA_DRAM_WR_CLI2GRP_MAP0 = 0x17a2 # macro
mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro
mmGCEA_DRAM_WR_CLI2GRP_MAP1 = 0x17a3 # macro
mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro
mmGCEA_DRAM_RD_GRP2VC_MAP = 0x17a4 # macro
mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX = 0 # macro
mmGCEA_DRAM_WR_GRP2VC_MAP = 0x17a5 # macro
mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX = 0 # macro
mmGCEA_DRAM_RD_LAZY = 0x17a6 # macro
mmGCEA_DRAM_RD_LAZY_BASE_IDX = 0 # macro
mmGCEA_DRAM_WR_LAZY = 0x17a7 # macro
mmGCEA_DRAM_WR_LAZY_BASE_IDX = 0 # macro
mmGCEA_DRAM_RD_CAM_CNTL = 0x17a8 # macro
mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX = 0 # macro
mmGCEA_DRAM_WR_CAM_CNTL = 0x17a9 # macro
mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX = 0 # macro
mmGCEA_DRAM_PAGE_BURST = 0x17aa # macro
mmGCEA_DRAM_PAGE_BURST_BASE_IDX = 0 # macro
mmGCEA_DRAM_RD_PRI_AGE = 0x17ab # macro
mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX = 0 # macro
mmGCEA_DRAM_WR_PRI_AGE = 0x17ac # macro
mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX = 0 # macro
mmGCEA_DRAM_RD_PRI_QUEUING = 0x17ad # macro
mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX = 0 # macro
mmGCEA_DRAM_WR_PRI_QUEUING = 0x17ae # macro
mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX = 0 # macro
mmGCEA_DRAM_RD_PRI_FIXED = 0x17af # macro
mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX = 0 # macro
mmGCEA_DRAM_WR_PRI_FIXED = 0x17b0 # macro
mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX = 0 # macro
mmGCEA_DRAM_RD_PRI_URGENCY = 0x17b1 # macro
mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX = 0 # macro
mmGCEA_DRAM_WR_PRI_URGENCY = 0x17b2 # macro
mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX = 0 # macro
mmGCEA_DRAM_RD_PRI_QUANT_PRI1 = 0x17b3 # macro
mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro
mmGCEA_DRAM_RD_PRI_QUANT_PRI2 = 0x17b4 # macro
mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro
mmGCEA_DRAM_RD_PRI_QUANT_PRI3 = 0x17b5 # macro
mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro
mmGCEA_DRAM_WR_PRI_QUANT_PRI1 = 0x17b6 # macro
mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro
mmGCEA_DRAM_WR_PRI_QUANT_PRI2 = 0x17b7 # macro
mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro
mmGCEA_DRAM_WR_PRI_QUANT_PRI3 = 0x17b8 # macro
mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro
mmGCEA_IO_RD_CLI2GRP_MAP0 = 0x187d # macro
mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro
mmGCEA_IO_RD_CLI2GRP_MAP1 = 0x187e # macro
mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro
mmGCEA_IO_WR_CLI2GRP_MAP0 = 0x187f # macro
mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro
mmGCEA_IO_WR_CLI2GRP_MAP1 = 0x1880 # macro
mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro
mmGCEA_IO_RD_COMBINE_FLUSH = 0x1881 # macro
mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX = 0 # macro
mmGCEA_IO_WR_COMBINE_FLUSH = 0x1882 # macro
mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX = 0 # macro
mmGCEA_IO_GROUP_BURST = 0x1883 # macro
mmGCEA_IO_GROUP_BURST_BASE_IDX = 0 # macro
mmGCEA_IO_RD_PRI_AGE = 0x1884 # macro
mmGCEA_IO_RD_PRI_AGE_BASE_IDX = 0 # macro
mmGCEA_IO_WR_PRI_AGE = 0x1885 # macro
mmGCEA_IO_WR_PRI_AGE_BASE_IDX = 0 # macro
mmGCEA_IO_RD_PRI_QUEUING = 0x1886 # macro
mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX = 0 # macro
mmGCEA_IO_WR_PRI_QUEUING = 0x1887 # macro
mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX = 0 # macro
mmGCEA_IO_RD_PRI_FIXED = 0x1888 # macro
mmGCEA_IO_RD_PRI_FIXED_BASE_IDX = 0 # macro
mmGCEA_IO_WR_PRI_FIXED = 0x1889 # macro
mmGCEA_IO_WR_PRI_FIXED_BASE_IDX = 0 # macro
mmGCEA_IO_RD_PRI_URGENCY = 0x188a # macro
mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX = 0 # macro
mmGCEA_IO_WR_PRI_URGENCY = 0x188b # macro
mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX = 0 # macro
mmGCEA_IO_RD_PRI_URGENCY_MASKING = 0x188c # macro
mmGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro
mmGCEA_IO_WR_PRI_URGENCY_MASKING = 0x188d # macro
mmGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro
mmGCEA_IO_RD_PRI_QUANT_PRI1 = 0x188e # macro
mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro
mmGCEA_IO_RD_PRI_QUANT_PRI2 = 0x188f # macro
mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro
mmGCEA_IO_RD_PRI_QUANT_PRI3 = 0x1890 # macro
mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro
mmGCEA_IO_WR_PRI_QUANT_PRI1 = 0x1891 # macro
mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro
mmGCEA_IO_WR_PRI_QUANT_PRI2 = 0x1892 # macro
mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro
mmGCEA_IO_WR_PRI_QUANT_PRI3 = 0x1893 # macro
mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro
mmTCP_INVALIDATE = 0x18a0 # macro
mmTCP_INVALIDATE_BASE_IDX = 0 # macro
mmTCP_STATUS = 0x18a1 # macro
mmTCP_STATUS_BASE_IDX = 0 # macro
mmTCP_EDC_CNT = 0x18b7 # macro
mmTCP_EDC_CNT_BASE_IDX = 0 # macro
mmTCI_STATUS = 0x1901 # macro
mmTCI_STATUS_BASE_IDX = 0 # macro
mmTCI_CNTL_1 = 0x1902 # macro
mmTCI_CNTL_1_BASE_IDX = 0 # macro
mmTCI_CNTL_2 = 0x1903 # macro
mmTCI_CNTL_2_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC4_PS = 0x19a1 # macro
mmSPI_SHADER_PGM_RSRC4_PS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_CHKSUM_PS = 0x19a6 # macro
mmSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC3_PS = 0x19a7 # macro
mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_LO_PS = 0x19a8 # macro
mmSPI_SHADER_PGM_LO_PS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_HI_PS = 0x19a9 # macro
mmSPI_SHADER_PGM_HI_PS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC1_PS = 0x19aa # macro
mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC2_PS = 0x19ab # macro
mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_0 = 0x19ac # macro
mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_1 = 0x19ad # macro
mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_2 = 0x19ae # macro
mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_3 = 0x19af # macro
mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_4 = 0x19b0 # macro
mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_5 = 0x19b1 # macro
mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_6 = 0x19b2 # macro
mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_7 = 0x19b3 # macro
mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_8 = 0x19b4 # macro
mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_9 = 0x19b5 # macro
mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_10 = 0x19b6 # macro
mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_11 = 0x19b7 # macro
mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_12 = 0x19b8 # macro
mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_13 = 0x19b9 # macro
mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_14 = 0x19ba # macro
mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_15 = 0x19bb # macro
mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_16 = 0x19bc # macro
mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_17 = 0x19bd # macro
mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_18 = 0x19be # macro
mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_19 = 0x19bf # macro
mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_20 = 0x19c0 # macro
mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_21 = 0x19c1 # macro
mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_22 = 0x19c2 # macro
mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_23 = 0x19c3 # macro
mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_24 = 0x19c4 # macro
mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_25 = 0x19c5 # macro
mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_26 = 0x19c6 # macro
mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_27 = 0x19c7 # macro
mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_28 = 0x19c8 # macro
mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_29 = 0x19c9 # macro
mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_30 = 0x19ca # macro
mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_PS_31 = 0x19cb # macro
mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX = 0 # macro
mmSPI_SHADER_REQ_CTRL_PS = 0x19d0 # macro
mmSPI_SHADER_REQ_CTRL_PS_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_PS_0 = 0x19d2 # macro
mmSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_PS_1 = 0x19d3 # macro
mmSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_PS_2 = 0x19d4 # macro
mmSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_PS_3 = 0x19d5 # macro
mmSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC4_VS = 0x19e1 # macro
mmSPI_SHADER_PGM_RSRC4_VS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_CHKSUM_VS = 0x19e5 # macro
mmSPI_SHADER_PGM_CHKSUM_VS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC3_VS = 0x19e6 # macro
mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX = 0 # macro
mmSPI_SHADER_LATE_ALLOC_VS = 0x19e7 # macro
mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_LO_VS = 0x19e8 # macro
mmSPI_SHADER_PGM_LO_VS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_HI_VS = 0x19e9 # macro
mmSPI_SHADER_PGM_HI_VS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC1_VS = 0x19ea # macro
mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC2_VS = 0x19eb # macro
mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_0 = 0x19ec # macro
mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_1 = 0x19ed # macro
mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_2 = 0x19ee # macro
mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_3 = 0x19ef # macro
mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_4 = 0x19f0 # macro
mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_5 = 0x19f1 # macro
mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_6 = 0x19f2 # macro
mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_7 = 0x19f3 # macro
mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_8 = 0x19f4 # macro
mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_9 = 0x19f5 # macro
mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_10 = 0x19f6 # macro
mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_11 = 0x19f7 # macro
mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_12 = 0x19f8 # macro
mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_13 = 0x19f9 # macro
mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_14 = 0x19fa # macro
mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_15 = 0x19fb # macro
mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_16 = 0x19fc # macro
mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_17 = 0x19fd # macro
mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_18 = 0x19fe # macro
mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_19 = 0x19ff # macro
mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_20 = 0x1a00 # macro
mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_21 = 0x1a01 # macro
mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_22 = 0x1a02 # macro
mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_23 = 0x1a03 # macro
mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_24 = 0x1a04 # macro
mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_25 = 0x1a05 # macro
mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_26 = 0x1a06 # macro
mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_27 = 0x1a07 # macro
mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_28 = 0x1a08 # macro
mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_29 = 0x1a09 # macro
mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_30 = 0x1a0a # macro
mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_VS_31 = 0x1a0b # macro
mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX = 0 # macro
mmSPI_SHADER_REQ_CTRL_VS = 0x1a10 # macro
mmSPI_SHADER_REQ_CTRL_VS_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_VS_0 = 0x1a12 # macro
mmSPI_SHADER_USER_ACCUM_VS_0_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_VS_1 = 0x1a13 # macro
mmSPI_SHADER_USER_ACCUM_VS_1_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_VS_2 = 0x1a14 # macro
mmSPI_SHADER_USER_ACCUM_VS_2_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_VS_3 = 0x1a15 # macro
mmSPI_SHADER_USER_ACCUM_VS_3_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC2_GS_VS = 0x1a1b # macro
mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_CHKSUM_GS = 0x1a20 # macro
mmSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC4_GS = 0x1a21 # macro
mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_ADDR_LO_GS = 0x1a22 # macro
mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_ADDR_HI_GS = 0x1a23 # macro
mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_LO_ES_GS = 0x1a24 # macro
mmSPI_SHADER_PGM_LO_ES_GS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_HI_ES_GS = 0x1a25 # macro
mmSPI_SHADER_PGM_HI_ES_GS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC3_GS = 0x1a27 # macro
mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_LO_GS = 0x1a28 # macro
mmSPI_SHADER_PGM_LO_GS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_HI_GS = 0x1a29 # macro
mmSPI_SHADER_PGM_HI_GS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC1_GS = 0x1a2a # macro
mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC2_GS = 0x1a2b # macro
mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_0 = 0x1a2c # macro
mmSPI_SHADER_USER_DATA_GS_0_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_1 = 0x1a2d # macro
mmSPI_SHADER_USER_DATA_GS_1_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_2 = 0x1a2e # macro
mmSPI_SHADER_USER_DATA_GS_2_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_3 = 0x1a2f # macro
mmSPI_SHADER_USER_DATA_GS_3_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_4 = 0x1a30 # macro
mmSPI_SHADER_USER_DATA_GS_4_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_5 = 0x1a31 # macro
mmSPI_SHADER_USER_DATA_GS_5_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_6 = 0x1a32 # macro
mmSPI_SHADER_USER_DATA_GS_6_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_7 = 0x1a33 # macro
mmSPI_SHADER_USER_DATA_GS_7_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_8 = 0x1a34 # macro
mmSPI_SHADER_USER_DATA_GS_8_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_9 = 0x1a35 # macro
mmSPI_SHADER_USER_DATA_GS_9_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_10 = 0x1a36 # macro
mmSPI_SHADER_USER_DATA_GS_10_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_11 = 0x1a37 # macro
mmSPI_SHADER_USER_DATA_GS_11_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_12 = 0x1a38 # macro
mmSPI_SHADER_USER_DATA_GS_12_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_13 = 0x1a39 # macro
mmSPI_SHADER_USER_DATA_GS_13_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_14 = 0x1a3a # macro
mmSPI_SHADER_USER_DATA_GS_14_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_15 = 0x1a3b # macro
mmSPI_SHADER_USER_DATA_GS_15_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_16 = 0x1a3c # macro
mmSPI_SHADER_USER_DATA_GS_16_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_17 = 0x1a3d # macro
mmSPI_SHADER_USER_DATA_GS_17_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_18 = 0x1a3e # macro
mmSPI_SHADER_USER_DATA_GS_18_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_19 = 0x1a3f # macro
mmSPI_SHADER_USER_DATA_GS_19_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_20 = 0x1a40 # macro
mmSPI_SHADER_USER_DATA_GS_20_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_21 = 0x1a41 # macro
mmSPI_SHADER_USER_DATA_GS_21_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_22 = 0x1a42 # macro
mmSPI_SHADER_USER_DATA_GS_22_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_23 = 0x1a43 # macro
mmSPI_SHADER_USER_DATA_GS_23_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_24 = 0x1a44 # macro
mmSPI_SHADER_USER_DATA_GS_24_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_25 = 0x1a45 # macro
mmSPI_SHADER_USER_DATA_GS_25_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_26 = 0x1a46 # macro
mmSPI_SHADER_USER_DATA_GS_26_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_27 = 0x1a47 # macro
mmSPI_SHADER_USER_DATA_GS_27_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_28 = 0x1a48 # macro
mmSPI_SHADER_USER_DATA_GS_28_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_29 = 0x1a49 # macro
mmSPI_SHADER_USER_DATA_GS_29_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_30 = 0x1a4a # macro
mmSPI_SHADER_USER_DATA_GS_30_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_GS_31 = 0x1a4b # macro
mmSPI_SHADER_USER_DATA_GS_31_BASE_IDX = 0 # macro
mmSPI_SHADER_REQ_CTRL_ESGS = 0x1a50 # macro
mmSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_ESGS_0 = 0x1a52 # macro
mmSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_ESGS_1 = 0x1a53 # macro
mmSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_ESGS_2 = 0x1a54 # macro
mmSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_ESGS_3 = 0x1a55 # macro
mmSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_LO_ES = 0x1a68 # macro
mmSPI_SHADER_PGM_LO_ES_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_HI_ES = 0x1a69 # macro
mmSPI_SHADER_PGM_HI_ES_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_CHKSUM_HS = 0x1aa0 # macro
mmSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC4_HS = 0x1aa1 # macro
mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_ADDR_LO_HS = 0x1aa2 # macro
mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_ADDR_HI_HS = 0x1aa3 # macro
mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_LO_LS_HS = 0x1aa4 # macro
mmSPI_SHADER_PGM_LO_LS_HS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_HI_LS_HS = 0x1aa5 # macro
mmSPI_SHADER_PGM_HI_LS_HS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC3_HS = 0x1aa7 # macro
mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_LO_HS = 0x1aa8 # macro
mmSPI_SHADER_PGM_LO_HS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_HI_HS = 0x1aa9 # macro
mmSPI_SHADER_PGM_HI_HS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC1_HS = 0x1aaa # macro
mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_RSRC2_HS = 0x1aab # macro
mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_0 = 0x1aac # macro
mmSPI_SHADER_USER_DATA_HS_0_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_1 = 0x1aad # macro
mmSPI_SHADER_USER_DATA_HS_1_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_2 = 0x1aae # macro
mmSPI_SHADER_USER_DATA_HS_2_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_3 = 0x1aaf # macro
mmSPI_SHADER_USER_DATA_HS_3_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_4 = 0x1ab0 # macro
mmSPI_SHADER_USER_DATA_HS_4_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_5 = 0x1ab1 # macro
mmSPI_SHADER_USER_DATA_HS_5_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_6 = 0x1ab2 # macro
mmSPI_SHADER_USER_DATA_HS_6_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_7 = 0x1ab3 # macro
mmSPI_SHADER_USER_DATA_HS_7_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_8 = 0x1ab4 # macro
mmSPI_SHADER_USER_DATA_HS_8_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_9 = 0x1ab5 # macro
mmSPI_SHADER_USER_DATA_HS_9_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_10 = 0x1ab6 # macro
mmSPI_SHADER_USER_DATA_HS_10_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_11 = 0x1ab7 # macro
mmSPI_SHADER_USER_DATA_HS_11_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_12 = 0x1ab8 # macro
mmSPI_SHADER_USER_DATA_HS_12_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_13 = 0x1ab9 # macro
mmSPI_SHADER_USER_DATA_HS_13_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_14 = 0x1aba # macro
mmSPI_SHADER_USER_DATA_HS_14_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_15 = 0x1abb # macro
mmSPI_SHADER_USER_DATA_HS_15_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_16 = 0x1abc # macro
mmSPI_SHADER_USER_DATA_HS_16_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_17 = 0x1abd # macro
mmSPI_SHADER_USER_DATA_HS_17_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_18 = 0x1abe # macro
mmSPI_SHADER_USER_DATA_HS_18_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_19 = 0x1abf # macro
mmSPI_SHADER_USER_DATA_HS_19_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_20 = 0x1ac0 # macro
mmSPI_SHADER_USER_DATA_HS_20_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_21 = 0x1ac1 # macro
mmSPI_SHADER_USER_DATA_HS_21_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_22 = 0x1ac2 # macro
mmSPI_SHADER_USER_DATA_HS_22_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_23 = 0x1ac3 # macro
mmSPI_SHADER_USER_DATA_HS_23_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_24 = 0x1ac4 # macro
mmSPI_SHADER_USER_DATA_HS_24_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_25 = 0x1ac5 # macro
mmSPI_SHADER_USER_DATA_HS_25_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_26 = 0x1ac6 # macro
mmSPI_SHADER_USER_DATA_HS_26_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_27 = 0x1ac7 # macro
mmSPI_SHADER_USER_DATA_HS_27_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_28 = 0x1ac8 # macro
mmSPI_SHADER_USER_DATA_HS_28_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_29 = 0x1ac9 # macro
mmSPI_SHADER_USER_DATA_HS_29_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_30 = 0x1aca # macro
mmSPI_SHADER_USER_DATA_HS_30_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_DATA_HS_31 = 0x1acb # macro
mmSPI_SHADER_USER_DATA_HS_31_BASE_IDX = 0 # macro
mmSPI_SHADER_REQ_CTRL_LSHS = 0x1ad0 # macro
mmSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_LSHS_0 = 0x1ad2 # macro
mmSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_LSHS_1 = 0x1ad3 # macro
mmSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_LSHS_2 = 0x1ad4 # macro
mmSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX = 0 # macro
mmSPI_SHADER_USER_ACCUM_LSHS_3 = 0x1ad5 # macro
mmSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_LO_LS = 0x1ae8 # macro
mmSPI_SHADER_PGM_LO_LS_BASE_IDX = 0 # macro
mmSPI_SHADER_PGM_HI_LS = 0x1ae9 # macro
mmSPI_SHADER_PGM_HI_LS_BASE_IDX = 0 # macro
mmCOMPUTE_DISPATCH_INITIATOR = 0x1ba0 # macro
mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX = 0 # macro
mmCOMPUTE_DIM_X = 0x1ba1 # macro
mmCOMPUTE_DIM_X_BASE_IDX = 0 # macro
mmCOMPUTE_DIM_Y = 0x1ba2 # macro
mmCOMPUTE_DIM_Y_BASE_IDX = 0 # macro
mmCOMPUTE_DIM_Z = 0x1ba3 # macro
mmCOMPUTE_DIM_Z_BASE_IDX = 0 # macro
mmCOMPUTE_START_X = 0x1ba4 # macro
mmCOMPUTE_START_X_BASE_IDX = 0 # macro
mmCOMPUTE_START_Y = 0x1ba5 # macro
mmCOMPUTE_START_Y_BASE_IDX = 0 # macro
mmCOMPUTE_START_Z = 0x1ba6 # macro
mmCOMPUTE_START_Z_BASE_IDX = 0 # macro
mmCOMPUTE_NUM_THREAD_X = 0x1ba7 # macro
mmCOMPUTE_NUM_THREAD_X_BASE_IDX = 0 # macro
mmCOMPUTE_NUM_THREAD_Y = 0x1ba8 # macro
mmCOMPUTE_NUM_THREAD_Y_BASE_IDX = 0 # macro
mmCOMPUTE_NUM_THREAD_Z = 0x1ba9 # macro
mmCOMPUTE_NUM_THREAD_Z_BASE_IDX = 0 # macro
mmCOMPUTE_PIPELINESTAT_ENABLE = 0x1baa # macro
mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX = 0 # macro
mmCOMPUTE_PERFCOUNT_ENABLE = 0x1bab # macro
mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX = 0 # macro
mmCOMPUTE_PGM_LO = 0x1bac # macro
mmCOMPUTE_PGM_LO_BASE_IDX = 0 # macro
mmCOMPUTE_PGM_HI = 0x1bad # macro
mmCOMPUTE_PGM_HI_BASE_IDX = 0 # macro
mmCOMPUTE_DISPATCH_PKT_ADDR_LO = 0x1bae # macro
mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX = 0 # macro
mmCOMPUTE_DISPATCH_PKT_ADDR_HI = 0x1baf # macro
mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX = 0 # macro
mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO = 0x1bb0 # macro
mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX = 0 # macro
mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI = 0x1bb1 # macro
mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX = 0 # macro
mmCOMPUTE_PGM_RSRC1 = 0x1bb2 # macro
mmCOMPUTE_PGM_RSRC1_BASE_IDX = 0 # macro
mmCOMPUTE_PGM_RSRC2 = 0x1bb3 # macro
mmCOMPUTE_PGM_RSRC2_BASE_IDX = 0 # macro
mmCOMPUTE_VMID = 0x1bb4 # macro
mmCOMPUTE_VMID_BASE_IDX = 0 # macro
mmCOMPUTE_RESOURCE_LIMITS = 0x1bb5 # macro
mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX = 0 # macro
mmCOMPUTE_DESTINATION_EN_SE0 = 0x1bb6 # macro
mmCOMPUTE_DESTINATION_EN_SE0_BASE_IDX = 0 # macro
mmCOMPUTE_STATIC_THREAD_MGMT_SE0 = 0x1bb6 # macro
mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX = 0 # macro
mmCOMPUTE_DESTINATION_EN_SE1 = 0x1bb7 # macro
mmCOMPUTE_DESTINATION_EN_SE1_BASE_IDX = 0 # macro
mmCOMPUTE_STATIC_THREAD_MGMT_SE1 = 0x1bb7 # macro
mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX = 0 # macro
mmCOMPUTE_TMPRING_SIZE = 0x1bb8 # macro
mmCOMPUTE_TMPRING_SIZE_BASE_IDX = 0 # macro
mmCOMPUTE_DESTINATION_EN_SE2 = 0x1bb9 # macro
mmCOMPUTE_DESTINATION_EN_SE2_BASE_IDX = 0 # macro
mmCOMPUTE_STATIC_THREAD_MGMT_SE2 = 0x1bb9 # macro
mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX = 0 # macro
mmCOMPUTE_DESTINATION_EN_SE3 = 0x1bba # macro
mmCOMPUTE_DESTINATION_EN_SE3_BASE_IDX = 0 # macro
mmCOMPUTE_STATIC_THREAD_MGMT_SE3 = 0x1bba # macro
mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX = 0 # macro
mmCOMPUTE_RESTART_X = 0x1bbb # macro
mmCOMPUTE_RESTART_X_BASE_IDX = 0 # macro
mmCOMPUTE_RESTART_Y = 0x1bbc # macro
mmCOMPUTE_RESTART_Y_BASE_IDX = 0 # macro
mmCOMPUTE_RESTART_Z = 0x1bbd # macro
mmCOMPUTE_RESTART_Z_BASE_IDX = 0 # macro
mmCOMPUTE_THREAD_TRACE_ENABLE = 0x1bbe # macro
mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX = 0 # macro
mmCOMPUTE_MISC_RESERVED = 0x1bbf # macro
mmCOMPUTE_MISC_RESERVED_BASE_IDX = 0 # macro
mmCOMPUTE_DISPATCH_ID = 0x1bc0 # macro
mmCOMPUTE_DISPATCH_ID_BASE_IDX = 0 # macro
mmCOMPUTE_THREADGROUP_ID = 0x1bc1 # macro
mmCOMPUTE_THREADGROUP_ID_BASE_IDX = 0 # macro
mmCOMPUTE_REQ_CTRL = 0x1bc2 # macro
mmCOMPUTE_REQ_CTRL_BASE_IDX = 0 # macro
mmCOMPUTE_USER_ACCUM_0 = 0x1bc4 # macro
mmCOMPUTE_USER_ACCUM_0_BASE_IDX = 0 # macro
mmCOMPUTE_USER_ACCUM_1 = 0x1bc5 # macro
mmCOMPUTE_USER_ACCUM_1_BASE_IDX = 0 # macro
mmCOMPUTE_USER_ACCUM_2 = 0x1bc6 # macro
mmCOMPUTE_USER_ACCUM_2_BASE_IDX = 0 # macro
mmCOMPUTE_USER_ACCUM_3 = 0x1bc7 # macro
mmCOMPUTE_USER_ACCUM_3_BASE_IDX = 0 # macro
mmCOMPUTE_PGM_RSRC3 = 0x1bc8 # macro
mmCOMPUTE_PGM_RSRC3_BASE_IDX = 0 # macro
mmCOMPUTE_DDID_INDEX = 0x1bc9 # macro
mmCOMPUTE_DDID_INDEX_BASE_IDX = 0 # macro
mmCOMPUTE_SHADER_CHKSUM = 0x1bca # macro
mmCOMPUTE_SHADER_CHKSUM_BASE_IDX = 0 # macro
mmCOMPUTE_RELAUNCH = 0x1bcb # macro
mmCOMPUTE_RELAUNCH_BASE_IDX = 0 # macro
mmCOMPUTE_WAVE_RESTORE_ADDR_LO = 0x1bcc # macro
mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX = 0 # macro
mmCOMPUTE_WAVE_RESTORE_ADDR_HI = 0x1bcd # macro
mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX = 0 # macro
mmCOMPUTE_RELAUNCH2 = 0x1bce # macro
mmCOMPUTE_RELAUNCH2_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_0 = 0x1be0 # macro
mmCOMPUTE_USER_DATA_0_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_1 = 0x1be1 # macro
mmCOMPUTE_USER_DATA_1_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_2 = 0x1be2 # macro
mmCOMPUTE_USER_DATA_2_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_3 = 0x1be3 # macro
mmCOMPUTE_USER_DATA_3_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_4 = 0x1be4 # macro
mmCOMPUTE_USER_DATA_4_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_5 = 0x1be5 # macro
mmCOMPUTE_USER_DATA_5_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_6 = 0x1be6 # macro
mmCOMPUTE_USER_DATA_6_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_7 = 0x1be7 # macro
mmCOMPUTE_USER_DATA_7_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_8 = 0x1be8 # macro
mmCOMPUTE_USER_DATA_8_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_9 = 0x1be9 # macro
mmCOMPUTE_USER_DATA_9_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_10 = 0x1bea # macro
mmCOMPUTE_USER_DATA_10_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_11 = 0x1beb # macro
mmCOMPUTE_USER_DATA_11_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_12 = 0x1bec # macro
mmCOMPUTE_USER_DATA_12_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_13 = 0x1bed # macro
mmCOMPUTE_USER_DATA_13_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_14 = 0x1bee # macro
mmCOMPUTE_USER_DATA_14_BASE_IDX = 0 # macro
mmCOMPUTE_USER_DATA_15 = 0x1bef # macro
mmCOMPUTE_USER_DATA_15_BASE_IDX = 0 # macro
mmCOMPUTE_DISPATCH_TUNNEL = 0x1c1d # macro
mmCOMPUTE_DISPATCH_TUNNEL_BASE_IDX = 0 # macro
mmCOMPUTE_DISPATCH_END = 0x1c1e # macro
mmCOMPUTE_DISPATCH_END_BASE_IDX = 0 # macro
mmCOMPUTE_NOWHERE = 0x1c1f # macro
mmCOMPUTE_NOWHERE_BASE_IDX = 0 # macro
mmSH_RESERVED_REG0 = 0x1c20 # macro
mmSH_RESERVED_REG0_BASE_IDX = 0 # macro
mmSH_RESERVED_REG1 = 0x1c21 # macro
mmSH_RESERVED_REG1_BASE_IDX = 0 # macro
mmCP_EOPQ_WAIT_TIME = 0x1dd5 # macro
mmCP_EOPQ_WAIT_TIME_BASE_IDX = 0 # macro
mmCP_CPC_MGCG_SYNC_CNTL = 0x1dd6 # macro
mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX = 0 # macro
mmCPC_INT_INFO = 0x1dd7 # macro
mmCPC_INT_INFO_BASE_IDX = 0 # macro
mmCP_VIRT_STATUS = 0x1dd8 # macro
mmCP_VIRT_STATUS_BASE_IDX = 0 # macro
mmCPC_INT_ADDR = 0x1dd9 # macro
mmCPC_INT_ADDR_BASE_IDX = 0 # macro
mmCPC_INT_PASID = 0x1dda # macro
mmCPC_INT_PASID_BASE_IDX = 0 # macro
mmCP_GFX_ERROR = 0x1ddb # macro
mmCP_GFX_ERROR_BASE_IDX = 0 # macro
mmCPG_UTCL1_CNTL = 0x1ddc # macro
mmCPG_UTCL1_CNTL_BASE_IDX = 0 # macro
mmCPC_UTCL1_CNTL = 0x1ddd # macro
mmCPC_UTCL1_CNTL_BASE_IDX = 0 # macro
mmCPF_UTCL1_CNTL = 0x1dde # macro
mmCPF_UTCL1_CNTL_BASE_IDX = 0 # macro
mmCP_AQL_SMM_STATUS = 0x1ddf # macro
mmCP_AQL_SMM_STATUS_BASE_IDX = 0 # macro
mmCP_RB0_BASE = 0x1de0 # macro
mmCP_RB0_BASE_BASE_IDX = 0 # macro
mmCP_RB_BASE = 0x1de0 # macro
mmCP_RB_BASE_BASE_IDX = 0 # macro
mmCP_RB0_CNTL = 0x1de1 # macro
mmCP_RB0_CNTL_BASE_IDX = 0 # macro
mmCP_RB_CNTL = 0x1de1 # macro
mmCP_RB_CNTL_BASE_IDX = 0 # macro
mmCP_RB_RPTR_WR = 0x1de2 # macro
mmCP_RB_RPTR_WR_BASE_IDX = 0 # macro
mmCP_RB0_RPTR_ADDR = 0x1de3 # macro
mmCP_RB0_RPTR_ADDR_BASE_IDX = 0 # macro
mmCP_RB_RPTR_ADDR = 0x1de3 # macro
mmCP_RB_RPTR_ADDR_BASE_IDX = 0 # macro
mmCP_RB0_RPTR_ADDR_HI = 0x1de4 # macro
mmCP_RB0_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmCP_RB_RPTR_ADDR_HI = 0x1de4 # macro
mmCP_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmCP_RB0_BUFSZ_MASK = 0x1de5 # macro
mmCP_RB0_BUFSZ_MASK_BASE_IDX = 0 # macro
mmCP_RB_BUFSZ_MASK = 0x1de5 # macro
mmCP_RB_BUFSZ_MASK_BASE_IDX = 0 # macro
mmCP_INT_CNTL = 0x1de9 # macro
mmCP_INT_CNTL_BASE_IDX = 0 # macro
mmCP_INT_STATUS = 0x1dea # macro
mmCP_INT_STATUS_BASE_IDX = 0 # macro
mmCP_DEVICE_ID = 0x1deb # macro
mmCP_DEVICE_ID_BASE_IDX = 0 # macro
mmCP_ME0_PIPE_PRIORITY_CNTS = 0x1dec # macro
mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro
mmCP_RING_PRIORITY_CNTS = 0x1dec # macro
mmCP_RING_PRIORITY_CNTS_BASE_IDX = 0 # macro
mmCP_ME0_PIPE0_PRIORITY = 0x1ded # macro
mmCP_ME0_PIPE0_PRIORITY_BASE_IDX = 0 # macro
mmCP_RING0_PRIORITY = 0x1ded # macro
mmCP_RING0_PRIORITY_BASE_IDX = 0 # macro
mmCP_ME0_PIPE1_PRIORITY = 0x1dee # macro
mmCP_ME0_PIPE1_PRIORITY_BASE_IDX = 0 # macro
mmCP_RING1_PRIORITY = 0x1dee # macro
mmCP_RING1_PRIORITY_BASE_IDX = 0 # macro
mmCP_ME0_PIPE2_PRIORITY = 0x1def # macro
mmCP_ME0_PIPE2_PRIORITY_BASE_IDX = 0 # macro
mmCP_RING2_PRIORITY = 0x1def # macro
mmCP_RING2_PRIORITY_BASE_IDX = 0 # macro
mmCP_FATAL_ERROR = 0x1df0 # macro
mmCP_FATAL_ERROR_BASE_IDX = 0 # macro
mmCP_RB_VMID = 0x1df1 # macro
mmCP_RB_VMID_BASE_IDX = 0 # macro
mmCP_ME0_PIPE0_VMID = 0x1df2 # macro
mmCP_ME0_PIPE0_VMID_BASE_IDX = 0 # macro
mmCP_ME0_PIPE1_VMID = 0x1df3 # macro
mmCP_ME0_PIPE1_VMID_BASE_IDX = 0 # macro
mmCP_RB0_WPTR = 0x1df4 # macro
mmCP_RB0_WPTR_BASE_IDX = 0 # macro
mmCP_RB_WPTR = 0x1df4 # macro
mmCP_RB_WPTR_BASE_IDX = 0 # macro
mmCP_RB0_WPTR_HI = 0x1df5 # macro
mmCP_RB0_WPTR_HI_BASE_IDX = 0 # macro
mmCP_RB_WPTR_HI = 0x1df5 # macro
mmCP_RB_WPTR_HI_BASE_IDX = 0 # macro
mmCP_RB1_WPTR = 0x1df6 # macro
mmCP_RB1_WPTR_BASE_IDX = 0 # macro
mmCP_RB1_WPTR_HI = 0x1df7 # macro
mmCP_RB1_WPTR_HI_BASE_IDX = 0 # macro
mmCP_RB2_WPTR = 0x1df8 # macro
mmCP_RB2_WPTR_BASE_IDX = 0 # macro
mmCP_PROCESS_QUANTUM = 0x1df9 # macro
mmCP_PROCESS_QUANTUM_BASE_IDX = 0 # macro
mmCP_RB_DOORBELL_RANGE_LOWER = 0x1dfa # macro
mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro
mmCP_RB_DOORBELL_RANGE_UPPER = 0x1dfb # macro
mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro
mmCP_MEC_DOORBELL_RANGE_LOWER = 0x1dfc # macro
mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro
mmCP_MEC_DOORBELL_RANGE_UPPER = 0x1dfd # macro
mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro
mmCPG_UTCL1_ERROR = 0x1dfe # macro
mmCPG_UTCL1_ERROR_BASE_IDX = 0 # macro
mmCPC_UTCL1_ERROR = 0x1dff # macro
mmCPC_UTCL1_ERROR_BASE_IDX = 0 # macro
mmCP_RB1_BASE = 0x1e00 # macro
mmCP_RB1_BASE_BASE_IDX = 0 # macro
mmCP_RB1_CNTL = 0x1e01 # macro
mmCP_RB1_CNTL_BASE_IDX = 0 # macro
mmCP_RB1_RPTR_ADDR = 0x1e02 # macro
mmCP_RB1_RPTR_ADDR_BASE_IDX = 0 # macro
mmCP_RB1_RPTR_ADDR_HI = 0x1e03 # macro
mmCP_RB1_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmCP_RB1_BUFSZ_MASK = 0x1e04 # macro
mmCP_RB1_BUFSZ_MASK_BASE_IDX = 0 # macro
mmCP_RB2_BASE = 0x1e05 # macro
mmCP_RB2_BASE_BASE_IDX = 0 # macro
mmCP_RB2_CNTL = 0x1e06 # macro
mmCP_RB2_CNTL_BASE_IDX = 0 # macro
mmCP_RB2_RPTR_ADDR = 0x1e07 # macro
mmCP_RB2_RPTR_ADDR_BASE_IDX = 0 # macro
mmCP_RB2_RPTR_ADDR_HI = 0x1e08 # macro
mmCP_RB2_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmCP_INT_CNTL_RING0 = 0x1e0a # macro
mmCP_INT_CNTL_RING0_BASE_IDX = 0 # macro
mmCP_INT_CNTL_RING1 = 0x1e0b # macro
mmCP_INT_CNTL_RING1_BASE_IDX = 0 # macro
mmCP_INT_CNTL_RING2 = 0x1e0c # macro
mmCP_INT_CNTL_RING2_BASE_IDX = 0 # macro
mmCP_INT_STATUS_RING0 = 0x1e0d # macro
mmCP_INT_STATUS_RING0_BASE_IDX = 0 # macro
mmCP_INT_STATUS_RING1 = 0x1e0e # macro
mmCP_INT_STATUS_RING1_BASE_IDX = 0 # macro
mmCP_INT_STATUS_RING2 = 0x1e0f # macro
mmCP_INT_STATUS_RING2_BASE_IDX = 0 # macro
mmCP_ME_F32_INTERRUPT = 0x1e13 # macro
mmCP_ME_F32_INTERRUPT_BASE_IDX = 0 # macro
mmCP_PFP_F32_INTERRUPT = 0x1e14 # macro
mmCP_PFP_F32_INTERRUPT_BASE_IDX = 0 # macro
mmCP_CE_F32_INTERRUPT = 0x1e15 # macro
mmCP_CE_F32_INTERRUPT_BASE_IDX = 0 # macro
mmCP_MEC1_F32_INTERRUPT = 0x1e16 # macro
mmCP_MEC1_F32_INTERRUPT_BASE_IDX = 0 # macro
mmCP_MEC2_F32_INTERRUPT = 0x1e17 # macro
mmCP_MEC2_F32_INTERRUPT_BASE_IDX = 0 # macro
mmCP_PWR_CNTL = 0x1e18 # macro
mmCP_PWR_CNTL_BASE_IDX = 0 # macro
mmCP_MEM_SLP_CNTL = 0x1e19 # macro
mmCP_MEM_SLP_CNTL_BASE_IDX = 0 # macro
mmCP_ECC_FIRSTOCCURRENCE = 0x1e1a # macro
mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX = 0 # macro
mmCP_ECC_FIRSTOCCURRENCE_RING0 = 0x1e1b # macro
mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX = 0 # macro
mmCP_ECC_FIRSTOCCURRENCE_RING1 = 0x1e1c # macro
mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX = 0 # macro
mmCP_ECC_FIRSTOCCURRENCE_RING2 = 0x1e1d # macro
mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX = 0 # macro
mmGB_EDC_MODE = 0x1e1e # macro
mmGB_EDC_MODE_BASE_IDX = 0 # macro
mmCP_PQ_WPTR_POLL_CNTL = 0x1e23 # macro
mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
mmCP_PQ_WPTR_POLL_CNTL1 = 0x1e24 # macro
mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX = 0 # macro
mmCP_ME1_PIPE0_INT_CNTL = 0x1e25 # macro
mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX = 0 # macro
mmCP_ME1_PIPE1_INT_CNTL = 0x1e26 # macro
mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX = 0 # macro
mmCP_ME1_PIPE2_INT_CNTL = 0x1e27 # macro
mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX = 0 # macro
mmCP_ME1_PIPE3_INT_CNTL = 0x1e28 # macro
mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX = 0 # macro
mmCP_ME2_PIPE0_INT_CNTL = 0x1e29 # macro
mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX = 0 # macro
mmCP_ME2_PIPE1_INT_CNTL = 0x1e2a # macro
mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX = 0 # macro
mmCP_ME2_PIPE2_INT_CNTL = 0x1e2b # macro
mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX = 0 # macro
mmCP_ME2_PIPE3_INT_CNTL = 0x1e2c # macro
mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX = 0 # macro
mmCP_ME1_PIPE0_INT_STATUS = 0x1e2d # macro
mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX = 0 # macro
mmCP_ME1_PIPE1_INT_STATUS = 0x1e2e # macro
mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX = 0 # macro
mmCP_ME1_PIPE2_INT_STATUS = 0x1e2f # macro
mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX = 0 # macro
mmCP_ME1_PIPE3_INT_STATUS = 0x1e30 # macro
mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX = 0 # macro
mmCP_ME2_PIPE0_INT_STATUS = 0x1e31 # macro
mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX = 0 # macro
mmCP_ME2_PIPE1_INT_STATUS = 0x1e32 # macro
mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX = 0 # macro
mmCP_ME2_PIPE2_INT_STATUS = 0x1e33 # macro
mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX = 0 # macro
mmCP_ME2_PIPE3_INT_STATUS = 0x1e34 # macro
mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX = 0 # macro
mmCP_GFX_QUEUE_INDEX = 0x1e37 # macro
mmCP_GFX_QUEUE_INDEX_BASE_IDX = 0 # macro
mmCC_GC_EDC_CONFIG = 0x1e38 # macro
mmCC_GC_EDC_CONFIG_BASE_IDX = 0 # macro
mmCP_ME1_INT_STAT_DEBUG = 0x1e35 # macro
mmCP_ME1_INT_STAT_DEBUG_BASE_IDX = 0 # macro
mmCP_ME2_INT_STAT_DEBUG = 0x1e36 # macro
mmCP_ME2_INT_STAT_DEBUG_BASE_IDX = 0 # macro
mmCP_ME1_PIPE_PRIORITY_CNTS = 0x1e39 # macro
mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro
mmCP_ME1_PIPE0_PRIORITY = 0x1e3a # macro
mmCP_ME1_PIPE0_PRIORITY_BASE_IDX = 0 # macro
mmCP_ME1_PIPE1_PRIORITY = 0x1e3b # macro
mmCP_ME1_PIPE1_PRIORITY_BASE_IDX = 0 # macro
mmCP_ME1_PIPE2_PRIORITY = 0x1e3c # macro
mmCP_ME1_PIPE2_PRIORITY_BASE_IDX = 0 # macro
mmCP_ME1_PIPE3_PRIORITY = 0x1e3d # macro
mmCP_ME1_PIPE3_PRIORITY_BASE_IDX = 0 # macro
mmCP_ME2_PIPE_PRIORITY_CNTS = 0x1e3e # macro
mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro
mmCP_ME2_PIPE0_PRIORITY = 0x1e3f # macro
mmCP_ME2_PIPE0_PRIORITY_BASE_IDX = 0 # macro
mmCP_ME2_PIPE1_PRIORITY = 0x1e40 # macro
mmCP_ME2_PIPE1_PRIORITY_BASE_IDX = 0 # macro
mmCP_ME2_PIPE2_PRIORITY = 0x1e41 # macro
mmCP_ME2_PIPE2_PRIORITY_BASE_IDX = 0 # macro
mmCP_ME2_PIPE3_PRIORITY = 0x1e42 # macro
mmCP_ME2_PIPE3_PRIORITY_BASE_IDX = 0 # macro
mmCP_CE_PRGRM_CNTR_START = 0x1e43 # macro
mmCP_CE_PRGRM_CNTR_START_BASE_IDX = 0 # macro
mmCP_PFP_PRGRM_CNTR_START = 0x1e44 # macro
mmCP_PFP_PRGRM_CNTR_START_BASE_IDX = 0 # macro
mmCP_ME_PRGRM_CNTR_START = 0x1e45 # macro
mmCP_ME_PRGRM_CNTR_START_BASE_IDX = 0 # macro
mmCP_MEC1_PRGRM_CNTR_START = 0x1e46 # macro
mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX = 0 # macro
mmCP_MEC2_PRGRM_CNTR_START = 0x1e47 # macro
mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX = 0 # macro
mmCP_CE_INTR_ROUTINE_START = 0x1e48 # macro
mmCP_CE_INTR_ROUTINE_START_BASE_IDX = 0 # macro
mmCP_PFP_INTR_ROUTINE_START = 0x1e49 # macro
mmCP_PFP_INTR_ROUTINE_START_BASE_IDX = 0 # macro
mmCP_ME_INTR_ROUTINE_START = 0x1e4a # macro
mmCP_ME_INTR_ROUTINE_START_BASE_IDX = 0 # macro
mmCP_MEC1_INTR_ROUTINE_START = 0x1e4b # macro
mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX = 0 # macro
mmCP_MEC2_INTR_ROUTINE_START = 0x1e4c # macro
mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX = 0 # macro
mmCP_CONTEXT_CNTL = 0x1e4d # macro
mmCP_CONTEXT_CNTL_BASE_IDX = 0 # macro
mmCP_MAX_CONTEXT = 0x1e4e # macro
mmCP_MAX_CONTEXT_BASE_IDX = 0 # macro
mmCP_IQ_WAIT_TIME1 = 0x1e4f # macro
mmCP_IQ_WAIT_TIME1_BASE_IDX = 0 # macro
mmCP_IQ_WAIT_TIME2 = 0x1e50 # macro
mmCP_IQ_WAIT_TIME2_BASE_IDX = 0 # macro
mmCP_RB0_BASE_HI = 0x1e51 # macro
mmCP_RB0_BASE_HI_BASE_IDX = 0 # macro
mmCP_RB1_BASE_HI = 0x1e52 # macro
mmCP_RB1_BASE_HI_BASE_IDX = 0 # macro
mmCP_VMID_RESET = 0x1e53 # macro
mmCP_VMID_RESET_BASE_IDX = 0 # macro
mmCPC_INT_CNTL = 0x1e54 # macro
mmCPC_INT_CNTL_BASE_IDX = 0 # macro
mmCPC_INT_STATUS = 0x1e55 # macro
mmCPC_INT_STATUS_BASE_IDX = 0 # macro
mmCP_VMID_PREEMPT = 0x1e56 # macro
mmCP_VMID_PREEMPT_BASE_IDX = 0 # macro
mmCPC_INT_CNTX_ID = 0x1e57 # macro
mmCPC_INT_CNTX_ID_BASE_IDX = 0 # macro
mmCP_PQ_STATUS = 0x1e58 # macro
mmCP_PQ_STATUS_BASE_IDX = 0 # macro
mmCP_MEC1_F32_INT_DIS = 0x1e5d # macro
mmCP_MEC1_F32_INT_DIS_BASE_IDX = 0 # macro
mmCP_MEC2_F32_INT_DIS = 0x1e5e # macro
mmCP_MEC2_F32_INT_DIS_BASE_IDX = 0 # macro
mmCP_VMID_STATUS = 0x1e5f # macro
mmCP_VMID_STATUS_BASE_IDX = 0 # macro
mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO = 0x1e60 # macro
mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro
mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI = 0x1e61 # macro
mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro
mmCPC_SUSPEND_CTX_SAVE_CONTROL = 0x1e62 # macro
mmCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro
mmCPC_SUSPEND_CNTL_STACK_OFFSET = 0x1e63 # macro
mmCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro
mmCPC_SUSPEND_CNTL_STACK_SIZE = 0x1e64 # macro
mmCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX = 0 # macro
mmCPC_SUSPEND_WG_STATE_OFFSET = 0x1e65 # macro
mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro
mmCPC_SUSPEND_CTX_SAVE_SIZE = 0x1e66 # macro
mmCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX = 0 # macro
mmCPC_OS_PIPES = 0x1e67 # macro
mmCPC_OS_PIPES_BASE_IDX = 0 # macro
mmCP_SUSPEND_RESUME_REQ = 0x1e68 # macro
mmCP_SUSPEND_RESUME_REQ_BASE_IDX = 0 # macro
mmCP_SUSPEND_CNTL = 0x1e69 # macro
mmCP_SUSPEND_CNTL_BASE_IDX = 0 # macro
mmCP_IQ_WAIT_TIME3 = 0x1e6a # macro
mmCP_IQ_WAIT_TIME3_BASE_IDX = 0 # macro
mmCPC_DDID_BASE_ADDR_LO = 0x1e6b # macro
mmCPC_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro
mmCP_DDID_BASE_ADDR_LO = 0x1e6b # macro
mmCP_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro
mmCPC_DDID_BASE_ADDR_HI = 0x1e6c # macro
mmCPC_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro
mmCP_DDID_BASE_ADDR_HI = 0x1e6c # macro
mmCP_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro
mmCPC_DDID_CNTL = 0x1e6d # macro
mmCPC_DDID_CNTL_BASE_IDX = 0 # macro
mmCP_DDID_CNTL = 0x1e6d # macro
mmCP_DDID_CNTL_BASE_IDX = 0 # macro
mmCP_GFX_DDID_INFLIGHT_COUNT = 0x1e6e # macro
mmCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro
mmCP_GFX_DDID_WPTR = 0x1e6f # macro
mmCP_GFX_DDID_WPTR_BASE_IDX = 0 # macro
mmCP_GFX_DDID_RPTR = 0x1e70 # macro
mmCP_GFX_DDID_RPTR_BASE_IDX = 0 # macro
mmCP_GFX_DDID_DELTA_RPT_COUNT = 0x1e71 # macro
mmCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro
mmCP_GFX_HPD_STATUS0 = 0x1e72 # macro
mmCP_GFX_HPD_STATUS0_BASE_IDX = 0 # macro
mmCP_GFX_HPD_CONTROL0 = 0x1e73 # macro
mmCP_GFX_HPD_CONTROL0_BASE_IDX = 0 # macro
mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO = 0x1e74 # macro
mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX = 0 # macro
mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI = 0x1e75 # macro
mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX = 0 # macro
mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO = 0x1e76 # macro
mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX = 0 # macro
mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI = 0x1e77 # macro
mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX = 0 # macro
mmCP_GFX_INDEX_MUTEX = 0x1e78 # macro
mmCP_GFX_INDEX_MUTEX_BASE_IDX = 0 # macro
mmCP_GFX_MQD_BASE_ADDR = 0x1e7e # macro
mmCP_GFX_MQD_BASE_ADDR_BASE_IDX = 0 # macro
mmCP_GFX_MQD_BASE_ADDR_HI = 0x1e7f # macro
mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro
mmCP_GFX_HQD_ACTIVE = 0x1e80 # macro
mmCP_GFX_HQD_ACTIVE_BASE_IDX = 0 # macro
mmCP_GFX_HQD_VMID = 0x1e81 # macro
mmCP_GFX_HQD_VMID_BASE_IDX = 0 # macro
mmCP_GFX_HQD_QUEUE_PRIORITY = 0x1e84 # macro
mmCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro
mmCP_GFX_HQD_QUANTUM = 0x1e85 # macro
mmCP_GFX_HQD_QUANTUM_BASE_IDX = 0 # macro
mmCP_GFX_HQD_BASE = 0x1e86 # macro
mmCP_GFX_HQD_BASE_BASE_IDX = 0 # macro
mmCP_GFX_HQD_BASE_HI = 0x1e87 # macro
mmCP_GFX_HQD_BASE_HI_BASE_IDX = 0 # macro
mmCP_GFX_HQD_RPTR = 0x1e88 # macro
mmCP_GFX_HQD_RPTR_BASE_IDX = 0 # macro
mmCP_GFX_HQD_RPTR_ADDR = 0x1e89 # macro
mmCP_GFX_HQD_RPTR_ADDR_BASE_IDX = 0 # macro
mmCP_GFX_HQD_RPTR_ADDR_HI = 0x1e8a # macro
mmCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmCP_RB_WPTR_POLL_ADDR_LO = 0x1e8b # macro
mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmCP_RB_WPTR_POLL_ADDR_HI = 0x1e8c # macro
mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmCP_RB_DOORBELL_CONTROL = 0x1e8d # macro
mmCP_RB_DOORBELL_CONTROL_BASE_IDX = 0 # macro
mmCP_GFX_HQD_OFFSET = 0x1e8e # macro
mmCP_GFX_HQD_OFFSET_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CNTL = 0x1e8f # macro
mmCP_GFX_HQD_CNTL_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CSMD_RPTR = 0x1e90 # macro
mmCP_GFX_HQD_CSMD_RPTR_BASE_IDX = 0 # macro
mmCP_GFX_HQD_WPTR = 0x1e91 # macro
mmCP_GFX_HQD_WPTR_BASE_IDX = 0 # macro
mmCP_GFX_HQD_WPTR_HI = 0x1e92 # macro
mmCP_GFX_HQD_WPTR_HI_BASE_IDX = 0 # macro
mmCP_GFX_HQD_DEQUEUE_REQUEST = 0x1e93 # macro
mmCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro
mmCP_GFX_HQD_MAPPED = 0x1e94 # macro
mmCP_GFX_HQD_MAPPED_BASE_IDX = 0 # macro
mmCP_GFX_HQD_QUE_MGR_CONTROL = 0x1e95 # macro
mmCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX = 0 # macro
mmCP_GFX_HQD_HQ_STATUS0 = 0x1e98 # macro
mmCP_GFX_HQD_HQ_STATUS0_BASE_IDX = 0 # macro
mmCP_GFX_HQD_HQ_CONTROL0 = 0x1e99 # macro
mmCP_GFX_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro
mmCP_GFX_MQD_CONTROL = 0x1e9a # macro
mmCP_GFX_MQD_CONTROL_BASE_IDX = 0 # macro
mmCP_HQD_GFX_CONTROL = 0x1e9f # macro
mmCP_HQD_GFX_CONTROL_BASE_IDX = 0 # macro
mmCP_HQD_GFX_STATUS = 0x1ea0 # macro
mmCP_HQD_GFX_STATUS_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CE_RPTR_WR = 0x1ea1 # macro
mmCP_GFX_HQD_CE_RPTR_WR_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CE_BASE = 0x1ea2 # macro
mmCP_GFX_HQD_CE_BASE_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CE_BASE_HI = 0x1ea3 # macro
mmCP_GFX_HQD_CE_BASE_HI_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CE_RPTR = 0x1ea4 # macro
mmCP_GFX_HQD_CE_RPTR_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CE_RPTR_ADDR = 0x1ea5 # macro
mmCP_GFX_HQD_CE_RPTR_ADDR_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CE_RPTR_ADDR_HI = 0x1ea6 # macro
mmCP_GFX_HQD_CE_RPTR_ADDR_HI_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO = 0x1ea7 # macro
mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI = 0x1ea8 # macro
mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CE_OFFSET = 0x1ea9 # macro
mmCP_GFX_HQD_CE_OFFSET_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CE_CNTL = 0x1eaa # macro
mmCP_GFX_HQD_CE_CNTL_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CE_CSMD_RPTR = 0x1eab # macro
mmCP_GFX_HQD_CE_CSMD_RPTR_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CE_WPTR = 0x1eac # macro
mmCP_GFX_HQD_CE_WPTR_BASE_IDX = 0 # macro
mmCP_GFX_HQD_CE_WPTR_HI = 0x1ead # macro
mmCP_GFX_HQD_CE_WPTR_HI_BASE_IDX = 0 # macro
mmCP_CE_DOORBELL_CONTROL = 0x1eae # macro
mmCP_CE_DOORBELL_CONTROL_BASE_IDX = 0 # macro
mmCP_DMA_WATCH0_ADDR_LO = 0x1ec0 # macro
mmCP_DMA_WATCH0_ADDR_LO_BASE_IDX = 0 # macro
mmCP_DMA_WATCH0_ADDR_HI = 0x1ec1 # macro
mmCP_DMA_WATCH0_ADDR_HI_BASE_IDX = 0 # macro
mmCP_DMA_WATCH0_MASK = 0x1ec2 # macro
mmCP_DMA_WATCH0_MASK_BASE_IDX = 0 # macro
mmCP_DMA_WATCH0_CNTL = 0x1ec3 # macro
mmCP_DMA_WATCH0_CNTL_BASE_IDX = 0 # macro
mmCP_DMA_WATCH1_ADDR_LO = 0x1ec4 # macro
mmCP_DMA_WATCH1_ADDR_LO_BASE_IDX = 0 # macro
mmCP_DMA_WATCH1_ADDR_HI = 0x1ec5 # macro
mmCP_DMA_WATCH1_ADDR_HI_BASE_IDX = 0 # macro
mmCP_DMA_WATCH1_MASK = 0x1ec6 # macro
mmCP_DMA_WATCH1_MASK_BASE_IDX = 0 # macro
mmCP_DMA_WATCH1_CNTL = 0x1ec7 # macro
mmCP_DMA_WATCH1_CNTL_BASE_IDX = 0 # macro
mmCP_DMA_WATCH2_ADDR_LO = 0x1ec8 # macro
mmCP_DMA_WATCH2_ADDR_LO_BASE_IDX = 0 # macro
mmCP_DMA_WATCH2_ADDR_HI = 0x1ec9 # macro
mmCP_DMA_WATCH2_ADDR_HI_BASE_IDX = 0 # macro
mmCP_DMA_WATCH2_MASK = 0x1eca # macro
mmCP_DMA_WATCH2_MASK_BASE_IDX = 0 # macro
mmCP_DMA_WATCH2_CNTL = 0x1ecb # macro
mmCP_DMA_WATCH2_CNTL_BASE_IDX = 0 # macro
mmCP_DMA_WATCH3_ADDR_LO = 0x1ecc # macro
mmCP_DMA_WATCH3_ADDR_LO_BASE_IDX = 0 # macro
mmCP_DMA_WATCH3_ADDR_HI = 0x1ecd # macro
mmCP_DMA_WATCH3_ADDR_HI_BASE_IDX = 0 # macro
mmCP_DMA_WATCH3_MASK = 0x1ece # macro
mmCP_DMA_WATCH3_MASK_BASE_IDX = 0 # macro
mmCP_DMA_WATCH3_CNTL = 0x1ecf # macro
mmCP_DMA_WATCH3_CNTL_BASE_IDX = 0 # macro
mmCP_DMA_WATCH_STAT_ADDR_LO = 0x1ed0 # macro
mmCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX = 0 # macro
mmCP_DMA_WATCH_STAT_ADDR_HI = 0x1ed1 # macro
mmCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX = 0 # macro
mmCP_DMA_WATCH_STAT = 0x1ed2 # macro
mmCP_DMA_WATCH_STAT_BASE_IDX = 0 # macro
mmCP_PFP_JT_STAT = 0x1ed3 # macro
mmCP_PFP_JT_STAT_BASE_IDX = 0 # macro
mmCP_CE_JT_STAT = 0x1ed4 # macro
mmCP_CE_JT_STAT_BASE_IDX = 0 # macro
mmCP_MEC_JT_STAT = 0x1ed5 # macro
mmCP_MEC_JT_STAT_BASE_IDX = 0 # macro
mmCP_FETCHER_SOURCE = 0x1f1e # macro
mmCP_FETCHER_SOURCE_BASE_IDX = 0 # macro
mmCP_CE_CS_PARTITION_INDEX = 0x1f1f # macro
mmCP_CE_CS_PARTITION_INDEX_BASE_IDX = 0 # macro
mmCP_RB_DOORBELL_CLEAR = 0x1f28 # macro
mmCP_RB_DOORBELL_CLEAR_BASE_IDX = 0 # macro
mmCP_RB0_ACTIVE = 0x1f40 # macro
mmCP_RB0_ACTIVE_BASE_IDX = 0 # macro
mmCP_RB_ACTIVE = 0x1f40 # macro
mmCP_RB_ACTIVE_BASE_IDX = 0 # macro
mmCP_RB1_ACTIVE = 0x1f41 # macro
mmCP_RB1_ACTIVE_BASE_IDX = 0 # macro
mmCP_RB_STATUS = 0x1f43 # macro
mmCP_RB_STATUS_BASE_IDX = 0 # macro
mmCPG_RCIU_CAM_INDEX = 0x1f44 # macro
mmCPG_RCIU_CAM_INDEX_BASE_IDX = 0 # macro
mmCPG_RCIU_CAM_DATA = 0x1f45 # macro
mmCPG_RCIU_CAM_DATA_BASE_IDX = 0 # macro
mmCPG_RCIU_CAM_DATA_PHASE0 = 0x1f45 # macro
mmCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX = 0 # macro
mmCPG_RCIU_CAM_DATA_PHASE1 = 0x1f45 # macro
mmCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX = 0 # macro
mmCPG_RCIU_CAM_DATA_PHASE2 = 0x1f45 # macro
mmCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX = 0 # macro
mmCP_GPU_TIMESTAMP_OFFSET_LO = 0x1f4c # macro
mmCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX = 0 # macro
mmCP_GPU_TIMESTAMP_OFFSET_HI = 0x1f4d # macro
mmCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX = 0 # macro
mmCPF_GCR_CNTL = 0x1f53 # macro
mmCPF_GCR_CNTL_BASE_IDX = 0 # macro
mmCPG_UTCL1_STATUS = 0x1f54 # macro
mmCPG_UTCL1_STATUS_BASE_IDX = 0 # macro
mmCPC_UTCL1_STATUS = 0x1f55 # macro
mmCPC_UTCL1_STATUS_BASE_IDX = 0 # macro
mmCPF_UTCL1_STATUS = 0x1f56 # macro
mmCPF_UTCL1_STATUS_BASE_IDX = 0 # macro
mmCP_SD_CNTL = 0x1f57 # macro
mmCP_SD_CNTL_BASE_IDX = 0 # macro
mmCP_SOFT_RESET_CNTL = 0x1f59 # macro
mmCP_SOFT_RESET_CNTL_BASE_IDX = 0 # macro
mmCP_CPC_GFX_CNTL = 0x1f5a # macro
mmCP_CPC_GFX_CNTL_BASE_IDX = 0 # macro
mmSPI_ARB_PRIORITY = 0x1f60 # macro
mmSPI_ARB_PRIORITY_BASE_IDX = 0 # macro
mmSPI_ARB_CYCLES_0 = 0x1f61 # macro
mmSPI_ARB_CYCLES_0_BASE_IDX = 0 # macro
mmSPI_ARB_CYCLES_1 = 0x1f62 # macro
mmSPI_ARB_CYCLES_1_BASE_IDX = 0 # macro
mmSPI_WCL_PIPE_PERCENT_GFX = 0x1f67 # macro
mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX = 0 # macro
mmSPI_WCL_PIPE_PERCENT_HP3D = 0x1f68 # macro
mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX = 0 # macro
mmSPI_WCL_PIPE_PERCENT_CS0 = 0x1f69 # macro
mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX = 0 # macro
mmSPI_WCL_PIPE_PERCENT_CS1 = 0x1f6a # macro
mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX = 0 # macro
mmSPI_WCL_PIPE_PERCENT_CS2 = 0x1f6b # macro
mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX = 0 # macro
mmSPI_WCL_PIPE_PERCENT_CS3 = 0x1f6c # macro
mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX = 0 # macro
mmSPI_GDBG_WAVE_CNTL = 0x1f71 # macro
mmSPI_GDBG_WAVE_CNTL_BASE_IDX = 0 # macro
mmSPI_GDBG_TRAP_CONFIG = 0x1f72 # macro
mmSPI_GDBG_TRAP_CONFIG_BASE_IDX = 0 # macro
mmSPI_GDBG_TRAP_MASK = 0x1f73 # macro
mmSPI_GDBG_TRAP_MASK_BASE_IDX = 0 # macro
mmSPI_GDBG_WAVE_CNTL2 = 0x1f74 # macro
mmSPI_GDBG_WAVE_CNTL2_BASE_IDX = 0 # macro
mmSPI_GDBG_WAVE_CNTL3 = 0x1f75 # macro
mmSPI_GDBG_WAVE_CNTL3_BASE_IDX = 0 # macro
mmSPI_GDBG_TRAP_DATA0 = 0x1f78 # macro
mmSPI_GDBG_TRAP_DATA0_BASE_IDX = 0 # macro
mmSPI_GDBG_TRAP_DATA1 = 0x1f79 # macro
mmSPI_GDBG_TRAP_DATA1_BASE_IDX = 0 # macro
mmSPI_COMPUTE_QUEUE_RESET = 0x1f7b # macro
mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_CU_0 = 0x1f7c # macro
mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_CU_1 = 0x1f7d # macro
mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_CU_2 = 0x1f7e # macro
mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_CU_3 = 0x1f7f # macro
mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_CU_4 = 0x1f80 # macro
mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_CU_5 = 0x1f81 # macro
mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_CU_6 = 0x1f82 # macro
mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_CU_7 = 0x1f83 # macro
mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_CU_8 = 0x1f84 # macro
mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_CU_9 = 0x1f85 # macro
mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_0 = 0x1f86 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_1 = 0x1f87 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_2 = 0x1f88 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_3 = 0x1f89 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_4 = 0x1f8a # macro
mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_5 = 0x1f8b # macro
mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_6 = 0x1f8c # macro
mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_7 = 0x1f8d # macro
mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_8 = 0x1f8e # macro
mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX = 0 # macro
mmSPI_RESOURCE_RESERVE_EN_CU_9 = 0x1f8f # macro
mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX = 0 # macro
mmSPI_COMPUTE_WF_CTX_SAVE = 0x1f9c # macro
mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX = 0 # macro
mmSPI_ARB_CNTL_0 = 0x1f9d # macro
mmSPI_ARB_CNTL_0_BASE_IDX = 0 # macro
mmSPI_FEATURE_CTRL = 0x1f9e # macro
mmSPI_FEATURE_CTRL_BASE_IDX = 0 # macro
mmSPI_SHADER_RSRC_LIMIT_CTRL = 0x1f9f # macro
mmSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX = 0 # macro
mmCP_HPD_MES_ROQ_OFFSETS = 0x1fa4 # macro
mmCP_HPD_MES_ROQ_OFFSETS_BASE_IDX = 0 # macro
mmCP_HPD_ROQ_OFFSETS = 0x1fa4 # macro
mmCP_HPD_ROQ_OFFSETS_BASE_IDX = 0 # macro
mmCP_HPD_STATUS0 = 0x1fa5 # macro
mmCP_HPD_STATUS0_BASE_IDX = 0 # macro
mmCP_HPD_UTCL1_CNTL = 0x1fa6 # macro
mmCP_HPD_UTCL1_CNTL_BASE_IDX = 0 # macro
mmCP_HPD_UTCL1_ERROR = 0x1fa7 # macro
mmCP_HPD_UTCL1_ERROR_BASE_IDX = 0 # macro
mmCP_HPD_UTCL1_ERROR_ADDR = 0x1fa8 # macro
mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX = 0 # macro
mmCP_MQD_BASE_ADDR = 0x1fa9 # macro
mmCP_MQD_BASE_ADDR_BASE_IDX = 0 # macro
mmCP_MQD_BASE_ADDR_HI = 0x1faa # macro
mmCP_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro
mmCP_HQD_ACTIVE = 0x1fab # macro
mmCP_HQD_ACTIVE_BASE_IDX = 0 # macro
mmCP_HQD_VMID = 0x1fac # macro
mmCP_HQD_VMID_BASE_IDX = 0 # macro
mmCP_HQD_PERSISTENT_STATE = 0x1fad # macro
mmCP_HQD_PERSISTENT_STATE_BASE_IDX = 0 # macro
mmCP_HQD_PIPE_PRIORITY = 0x1fae # macro
mmCP_HQD_PIPE_PRIORITY_BASE_IDX = 0 # macro
mmCP_HQD_QUEUE_PRIORITY = 0x1faf # macro
mmCP_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro
mmCP_HQD_QUANTUM = 0x1fb0 # macro
mmCP_HQD_QUANTUM_BASE_IDX = 0 # macro
mmCP_HQD_PQ_BASE = 0x1fb1 # macro
mmCP_HQD_PQ_BASE_BASE_IDX = 0 # macro
mmCP_HQD_PQ_BASE_HI = 0x1fb2 # macro
mmCP_HQD_PQ_BASE_HI_BASE_IDX = 0 # macro
mmCP_HQD_PQ_RPTR = 0x1fb3 # macro
mmCP_HQD_PQ_RPTR_BASE_IDX = 0 # macro
mmCP_HQD_PQ_RPTR_REPORT_ADDR = 0x1fb4 # macro
mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX = 0 # macro
mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI = 0x1fb5 # macro
mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX = 0 # macro
mmCP_HQD_PQ_WPTR_POLL_ADDR = 0x1fb6 # macro
mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX = 0 # macro
mmCP_HQD_PQ_WPTR_POLL_ADDR_HI = 0x1fb7 # macro
mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
mmCP_HQD_PQ_DOORBELL_CONTROL = 0x1fb8 # macro
mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX = 0 # macro
mmCP_HQD_PQ_CONTROL = 0x1fba # macro
mmCP_HQD_PQ_CONTROL_BASE_IDX = 0 # macro
mmCP_HQD_IB_BASE_ADDR = 0x1fbb # macro
mmCP_HQD_IB_BASE_ADDR_BASE_IDX = 0 # macro
mmCP_HQD_IB_BASE_ADDR_HI = 0x1fbc # macro
mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX = 0 # macro
mmCP_HQD_IB_RPTR = 0x1fbd # macro
mmCP_HQD_IB_RPTR_BASE_IDX = 0 # macro
mmCP_HQD_IB_CONTROL = 0x1fbe # macro
mmCP_HQD_IB_CONTROL_BASE_IDX = 0 # macro
mmCP_HQD_IQ_TIMER = 0x1fbf # macro
mmCP_HQD_IQ_TIMER_BASE_IDX = 0 # macro
mmCP_HQD_IQ_RPTR = 0x1fc0 # macro
mmCP_HQD_IQ_RPTR_BASE_IDX = 0 # macro
mmCP_HQD_DEQUEUE_REQUEST = 0x1fc1 # macro
mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro
mmCP_HQD_DMA_OFFLOAD = 0x1fc2 # macro
mmCP_HQD_DMA_OFFLOAD_BASE_IDX = 0 # macro
mmCP_HQD_OFFLOAD = 0x1fc2 # macro
mmCP_HQD_OFFLOAD_BASE_IDX = 0 # macro
mmCP_HQD_SEMA_CMD = 0x1fc3 # macro
mmCP_HQD_SEMA_CMD_BASE_IDX = 0 # macro
mmCP_HQD_MSG_TYPE = 0x1fc4 # macro
mmCP_HQD_MSG_TYPE_BASE_IDX = 0 # macro
mmCP_HQD_ATOMIC0_PREOP_LO = 0x1fc5 # macro
mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX = 0 # macro
mmCP_HQD_ATOMIC0_PREOP_HI = 0x1fc6 # macro
mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX = 0 # macro
mmCP_HQD_ATOMIC1_PREOP_LO = 0x1fc7 # macro
mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX = 0 # macro
mmCP_HQD_ATOMIC1_PREOP_HI = 0x1fc8 # macro
mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX = 0 # macro
mmCP_HQD_HQ_SCHEDULER0 = 0x1fc9 # macro
mmCP_HQD_HQ_SCHEDULER0_BASE_IDX = 0 # macro
mmCP_HQD_HQ_STATUS0 = 0x1fc9 # macro
mmCP_HQD_HQ_STATUS0_BASE_IDX = 0 # macro
mmCP_HQD_HQ_CONTROL0 = 0x1fca # macro
mmCP_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro
mmCP_HQD_HQ_SCHEDULER1 = 0x1fca # macro
mmCP_HQD_HQ_SCHEDULER1_BASE_IDX = 0 # macro
mmCP_MQD_CONTROL = 0x1fcb # macro
mmCP_MQD_CONTROL_BASE_IDX = 0 # macro
mmCP_HQD_HQ_STATUS1 = 0x1fcc # macro
mmCP_HQD_HQ_STATUS1_BASE_IDX = 0 # macro
mmCP_HQD_HQ_CONTROL1 = 0x1fcd # macro
mmCP_HQD_HQ_CONTROL1_BASE_IDX = 0 # macro
mmCP_HQD_EOP_BASE_ADDR = 0x1fce # macro
mmCP_HQD_EOP_BASE_ADDR_BASE_IDX = 0 # macro
mmCP_HQD_EOP_BASE_ADDR_HI = 0x1fcf # macro
mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX = 0 # macro
mmCP_HQD_EOP_CONTROL = 0x1fd0 # macro
mmCP_HQD_EOP_CONTROL_BASE_IDX = 0 # macro
mmCP_HQD_EOP_RPTR = 0x1fd1 # macro
mmCP_HQD_EOP_RPTR_BASE_IDX = 0 # macro
mmCP_HQD_EOP_WPTR = 0x1fd2 # macro
mmCP_HQD_EOP_WPTR_BASE_IDX = 0 # macro
mmCP_HQD_EOP_EVENTS = 0x1fd3 # macro
mmCP_HQD_EOP_EVENTS_BASE_IDX = 0 # macro
mmCP_HQD_CTX_SAVE_BASE_ADDR_LO = 0x1fd4 # macro
mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro
mmCP_HQD_CTX_SAVE_BASE_ADDR_HI = 0x1fd5 # macro
mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro
mmCP_HQD_CTX_SAVE_CONTROL = 0x1fd6 # macro
mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro
mmCP_HQD_CNTL_STACK_OFFSET = 0x1fd7 # macro
mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro
mmCP_HQD_CNTL_STACK_SIZE = 0x1fd8 # macro
mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX = 0 # macro
mmCP_HQD_WG_STATE_OFFSET = 0x1fd9 # macro
mmCP_HQD_WG_STATE_OFFSET_BASE_IDX = 0 # macro
mmCP_HQD_CTX_SAVE_SIZE = 0x1fda # macro
mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX = 0 # macro
mmCP_HQD_GDS_RESOURCE_STATE = 0x1fdb # macro
mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX = 0 # macro
mmCP_HQD_ERROR = 0x1fdc # macro
mmCP_HQD_ERROR_BASE_IDX = 0 # macro
mmCP_HQD_EOP_WPTR_MEM = 0x1fdd # macro
mmCP_HQD_EOP_WPTR_MEM_BASE_IDX = 0 # macro
mmCP_HQD_AQL_CONTROL = 0x1fde # macro
mmCP_HQD_AQL_CONTROL_BASE_IDX = 0 # macro
mmCP_HQD_PQ_WPTR_LO = 0x1fdf # macro
mmCP_HQD_PQ_WPTR_LO_BASE_IDX = 0 # macro
mmCP_HQD_PQ_WPTR_HI = 0x1fe0 # macro
mmCP_HQD_PQ_WPTR_HI_BASE_IDX = 0 # macro
mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET = 0x1fe1 # macro
mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro
mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT = 0x1fe2 # macro
mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX = 0 # macro
mmCP_HQD_SUSPEND_WG_STATE_OFFSET = 0x1fe3 # macro
mmCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro
mmCP_HQD_DDID_RPTR = 0x1fe4 # macro
mmCP_HQD_DDID_RPTR_BASE_IDX = 0 # macro
mmCP_HQD_DDID_WPTR = 0x1fe5 # macro
mmCP_HQD_DDID_WPTR_BASE_IDX = 0 # macro
mmCP_HQD_DDID_INFLIGHT_COUNT = 0x1fe6 # macro
mmCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro
mmCP_HQD_DDID_DELTA_RPT_COUNT = 0x1fe7 # macro
mmCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro
mmCP_HQD_DEQUEUE_STATUS = 0x1fe8 # macro
mmCP_HQD_DEQUEUE_STATUS_BASE_IDX = 0 # macro
mmDIDT_IND_INDEX = 0x2020 # macro
mmDIDT_IND_INDEX_BASE_IDX = 0 # macro
mmDIDT_IND_DATA = 0x2021 # macro
mmDIDT_IND_DATA_BASE_IDX = 0 # macro
mmDIDT_INDEX_AUTO_INCR_EN = 0x2022 # macro
mmDIDT_INDEX_AUTO_INCR_EN_BASE_IDX = 0 # macro
mmGC_CAC_CTRL_1 = 0x2024 # macro
mmGC_CAC_CTRL_1_BASE_IDX = 0 # macro
mmGC_CAC_CTRL_2 = 0x2025 # macro
mmGC_CAC_CTRL_2_BASE_IDX = 0 # macro
mmGC_CAC_AGGR_LOWER = 0x2026 # macro
mmGC_CAC_AGGR_LOWER_BASE_IDX = 0 # macro
mmGC_CAC_AGGR_UPPER = 0x2027 # macro
mmGC_CAC_AGGR_UPPER_BASE_IDX = 0 # macro
mmGC_CAC_SOFT_CTRL = 0x202a # macro
mmGC_CAC_SOFT_CTRL_BASE_IDX = 0 # macro
mmGC_EDC_CTRL = 0x202b # macro
mmGC_EDC_CTRL_BASE_IDX = 0 # macro
mmGC_EDC_THRESHOLD = 0x202c # macro
mmGC_EDC_THRESHOLD_BASE_IDX = 0 # macro
mmGC_EDC_STATUS = 0x202d # macro
mmGC_EDC_STATUS_BASE_IDX = 0 # macro
mmGC_EDC_OVERFLOW = 0x202e # macro
mmGC_EDC_OVERFLOW_BASE_IDX = 0 # macro
mmGC_EDC_ROLLING_POWER_DELTA = 0x202f # macro
mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX = 0 # macro
mmGC_THROTTLE_CTRL = 0x2030 # macro
mmGC_THROTTLE_CTRL_BASE_IDX = 0 # macro
mmGC_THROTTLE_CTRL1 = 0x2031 # macro
mmGC_THROTTLE_CTRL1_BASE_IDX = 0 # macro
mmGC_THROTTLE_STATUS = 0x2032 # macro
mmGC_THROTTLE_STATUS_BASE_IDX = 0 # macro
mmEDC_PERF_COUNTER = 0x2033 # macro
mmEDC_PERF_COUNTER_BASE_IDX = 0 # macro
mmPCC_PERF_COUNTER = 0x2034 # macro
mmPCC_PERF_COUNTER_BASE_IDX = 0 # macro
mmPWRBRK_PERF_COUNTER = 0x2035 # macro
mmPWRBRK_PERF_COUNTER_BASE_IDX = 0 # macro
mmGC_EDC_STRETCH_CTRL = 0x2036 # macro
mmGC_EDC_STRETCH_CTRL_BASE_IDX = 0 # macro
mmGC_EDC_STRETCH_THRESHOLD = 0x2037 # macro
mmGC_EDC_STRETCH_THRESHOLD_BASE_IDX = 0 # macro
mmEDC_HYSTERESIS_CNTL = 0x2038 # macro
mmEDC_HYSTERESIS_CNTL_BASE_IDX = 0 # macro
mmEDC_HYSTERESIS_STAT = 0x2039 # macro
mmEDC_HYSTERESIS_STAT_BASE_IDX = 0 # macro
mmGC_CAC_IND_INDEX = 0x203c # macro
mmGC_CAC_IND_INDEX_BASE_IDX = 0 # macro
mmGC_CAC_IND_DATA = 0x203d # macro
mmGC_CAC_IND_DATA_BASE_IDX = 0 # macro
mmSE_CAC_IND_INDEX = 0x203e # macro
mmSE_CAC_IND_INDEX_BASE_IDX = 0 # macro
mmSE_CAC_IND_DATA = 0x203f # macro
mmSE_CAC_IND_DATA_BASE_IDX = 0 # macro
mmTCP_WATCH0_ADDR_H = 0x2040 # macro
mmTCP_WATCH0_ADDR_H_BASE_IDX = 0 # macro
mmTCP_WATCH0_ADDR_L = 0x2041 # macro
mmTCP_WATCH0_ADDR_L_BASE_IDX = 0 # macro
mmTCP_WATCH0_CNTL = 0x2042 # macro
mmTCP_WATCH0_CNTL_BASE_IDX = 0 # macro
mmTCP_WATCH1_ADDR_H = 0x2043 # macro
mmTCP_WATCH1_ADDR_H_BASE_IDX = 0 # macro
mmTCP_WATCH1_ADDR_L = 0x2044 # macro
mmTCP_WATCH1_ADDR_L_BASE_IDX = 0 # macro
mmTCP_WATCH1_CNTL = 0x2045 # macro
mmTCP_WATCH1_CNTL_BASE_IDX = 0 # macro
mmTCP_WATCH2_ADDR_H = 0x2046 # macro
mmTCP_WATCH2_ADDR_H_BASE_IDX = 0 # macro
mmTCP_WATCH2_ADDR_L = 0x2047 # macro
mmTCP_WATCH2_ADDR_L_BASE_IDX = 0 # macro
mmTCP_WATCH2_CNTL = 0x2048 # macro
mmTCP_WATCH2_CNTL_BASE_IDX = 0 # macro
mmTCP_WATCH3_ADDR_H = 0x2049 # macro
mmTCP_WATCH3_ADDR_H_BASE_IDX = 0 # macro
mmTCP_WATCH3_ADDR_L = 0x204a # macro
mmTCP_WATCH3_ADDR_L_BASE_IDX = 0 # macro
mmTCP_WATCH3_CNTL = 0x204b # macro
mmTCP_WATCH3_CNTL_BASE_IDX = 0 # macro
mmTCP_PERFCOUNTER_FILTER = 0x2059 # macro
mmTCP_PERFCOUNTER_FILTER_BASE_IDX = 0 # macro
mmTCP_PERFCOUNTER_FILTER_EN = 0x205a # macro
mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX = 0 # macro
mmTCP_PERFCOUNTER_FILTER2 = 0x205b # macro
mmTCP_PERFCOUNTER_FILTER2_BASE_IDX = 0 # macro
mmGDS_VMID0_BASE = 0x20a0 # macro
mmGDS_VMID0_BASE_BASE_IDX = 0 # macro
mmGDS_VMID0_SIZE = 0x20a1 # macro
mmGDS_VMID0_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID1_BASE = 0x20a2 # macro
mmGDS_VMID1_BASE_BASE_IDX = 0 # macro
mmGDS_VMID1_SIZE = 0x20a3 # macro
mmGDS_VMID1_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID2_BASE = 0x20a4 # macro
mmGDS_VMID2_BASE_BASE_IDX = 0 # macro
mmGDS_VMID2_SIZE = 0x20a5 # macro
mmGDS_VMID2_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID3_BASE = 0x20a6 # macro
mmGDS_VMID3_BASE_BASE_IDX = 0 # macro
mmGDS_VMID3_SIZE = 0x20a7 # macro
mmGDS_VMID3_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID4_BASE = 0x20a8 # macro
mmGDS_VMID4_BASE_BASE_IDX = 0 # macro
mmGDS_VMID4_SIZE = 0x20a9 # macro
mmGDS_VMID4_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID5_BASE = 0x20aa # macro
mmGDS_VMID5_BASE_BASE_IDX = 0 # macro
mmGDS_VMID5_SIZE = 0x20ab # macro
mmGDS_VMID5_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID6_BASE = 0x20ac # macro
mmGDS_VMID6_BASE_BASE_IDX = 0 # macro
mmGDS_VMID6_SIZE = 0x20ad # macro
mmGDS_VMID6_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID7_BASE = 0x20ae # macro
mmGDS_VMID7_BASE_BASE_IDX = 0 # macro
mmGDS_VMID7_SIZE = 0x20af # macro
mmGDS_VMID7_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID8_BASE = 0x20b0 # macro
mmGDS_VMID8_BASE_BASE_IDX = 0 # macro
mmGDS_VMID8_SIZE = 0x20b1 # macro
mmGDS_VMID8_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID9_BASE = 0x20b2 # macro
mmGDS_VMID9_BASE_BASE_IDX = 0 # macro
mmGDS_VMID9_SIZE = 0x20b3 # macro
mmGDS_VMID9_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID10_BASE = 0x20b4 # macro
mmGDS_VMID10_BASE_BASE_IDX = 0 # macro
mmGDS_VMID10_SIZE = 0x20b5 # macro
mmGDS_VMID10_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID11_BASE = 0x20b6 # macro
mmGDS_VMID11_BASE_BASE_IDX = 0 # macro
mmGDS_VMID11_SIZE = 0x20b7 # macro
mmGDS_VMID11_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID12_BASE = 0x20b8 # macro
mmGDS_VMID12_BASE_BASE_IDX = 0 # macro
mmGDS_VMID12_SIZE = 0x20b9 # macro
mmGDS_VMID12_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID13_BASE = 0x20ba # macro
mmGDS_VMID13_BASE_BASE_IDX = 0 # macro
mmGDS_VMID13_SIZE = 0x20bb # macro
mmGDS_VMID13_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID14_BASE = 0x20bc # macro
mmGDS_VMID14_BASE_BASE_IDX = 0 # macro
mmGDS_VMID14_SIZE = 0x20bd # macro
mmGDS_VMID14_SIZE_BASE_IDX = 0 # macro
mmGDS_VMID15_BASE = 0x20be # macro
mmGDS_VMID15_BASE_BASE_IDX = 0 # macro
mmGDS_VMID15_SIZE = 0x20bf # macro
mmGDS_VMID15_SIZE_BASE_IDX = 0 # macro
mmGDS_GWS_VMID0 = 0x20c0 # macro
mmGDS_GWS_VMID0_BASE_IDX = 0 # macro
mmGDS_GWS_VMID1 = 0x20c1 # macro
mmGDS_GWS_VMID1_BASE_IDX = 0 # macro
mmGDS_GWS_VMID2 = 0x20c2 # macro
mmGDS_GWS_VMID2_BASE_IDX = 0 # macro
mmGDS_GWS_VMID3 = 0x20c3 # macro
mmGDS_GWS_VMID3_BASE_IDX = 0 # macro
mmGDS_GWS_VMID4 = 0x20c4 # macro
mmGDS_GWS_VMID4_BASE_IDX = 0 # macro
mmGDS_GWS_VMID5 = 0x20c5 # macro
mmGDS_GWS_VMID5_BASE_IDX = 0 # macro
mmGDS_GWS_VMID6 = 0x20c6 # macro
mmGDS_GWS_VMID6_BASE_IDX = 0 # macro
mmGDS_GWS_VMID7 = 0x20c7 # macro
mmGDS_GWS_VMID7_BASE_IDX = 0 # macro
mmGDS_GWS_VMID8 = 0x20c8 # macro
mmGDS_GWS_VMID8_BASE_IDX = 0 # macro
mmGDS_GWS_VMID9 = 0x20c9 # macro
mmGDS_GWS_VMID9_BASE_IDX = 0 # macro
mmGDS_GWS_VMID10 = 0x20ca # macro
mmGDS_GWS_VMID10_BASE_IDX = 0 # macro
mmGDS_GWS_VMID11 = 0x20cb # macro
mmGDS_GWS_VMID11_BASE_IDX = 0 # macro
mmGDS_GWS_VMID12 = 0x20cc # macro
mmGDS_GWS_VMID12_BASE_IDX = 0 # macro
mmGDS_GWS_VMID13 = 0x20cd # macro
mmGDS_GWS_VMID13_BASE_IDX = 0 # macro
mmGDS_GWS_VMID14 = 0x20ce # macro
mmGDS_GWS_VMID14_BASE_IDX = 0 # macro
mmGDS_GWS_VMID15 = 0x20cf # macro
mmGDS_GWS_VMID15_BASE_IDX = 0 # macro
mmGDS_OA_VMID0 = 0x20d0 # macro
mmGDS_OA_VMID0_BASE_IDX = 0 # macro
mmGDS_OA_VMID1 = 0x20d1 # macro
mmGDS_OA_VMID1_BASE_IDX = 0 # macro
mmGDS_OA_VMID2 = 0x20d2 # macro
mmGDS_OA_VMID2_BASE_IDX = 0 # macro
mmGDS_OA_VMID3 = 0x20d3 # macro
mmGDS_OA_VMID3_BASE_IDX = 0 # macro
mmGDS_OA_VMID4 = 0x20d4 # macro
mmGDS_OA_VMID4_BASE_IDX = 0 # macro
mmGDS_OA_VMID5 = 0x20d5 # macro
mmGDS_OA_VMID5_BASE_IDX = 0 # macro
mmGDS_OA_VMID6 = 0x20d6 # macro
mmGDS_OA_VMID6_BASE_IDX = 0 # macro
mmGDS_OA_VMID7 = 0x20d7 # macro
mmGDS_OA_VMID7_BASE_IDX = 0 # macro
mmGDS_OA_VMID8 = 0x20d8 # macro
mmGDS_OA_VMID8_BASE_IDX = 0 # macro
mmGDS_OA_VMID9 = 0x20d9 # macro
mmGDS_OA_VMID9_BASE_IDX = 0 # macro
mmGDS_OA_VMID10 = 0x20da # macro
mmGDS_OA_VMID10_BASE_IDX = 0 # macro
mmGDS_OA_VMID11 = 0x20db # macro
mmGDS_OA_VMID11_BASE_IDX = 0 # macro
mmGDS_OA_VMID12 = 0x20dc # macro
mmGDS_OA_VMID12_BASE_IDX = 0 # macro
mmGDS_OA_VMID13 = 0x20dd # macro
mmGDS_OA_VMID13_BASE_IDX = 0 # macro
mmGDS_OA_VMID14 = 0x20de # macro
mmGDS_OA_VMID14_BASE_IDX = 0 # macro
mmGDS_OA_VMID15 = 0x20df # macro
mmGDS_OA_VMID15_BASE_IDX = 0 # macro
mmGDS_GWS_RESET0 = 0x20e4 # macro
mmGDS_GWS_RESET0_BASE_IDX = 0 # macro
mmGDS_GWS_RESET1 = 0x20e5 # macro
mmGDS_GWS_RESET1_BASE_IDX = 0 # macro
mmGDS_GWS_RESOURCE_RESET = 0x20e6 # macro
mmGDS_GWS_RESOURCE_RESET_BASE_IDX = 0 # macro
mmGDS_COMPUTE_MAX_WAVE_ID = 0x20e8 # macro
mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX = 0 # macro
mmGDS_OA_RESET_MASK = 0x20e9 # macro
mmGDS_OA_RESET_MASK_BASE_IDX = 0 # macro
mmGDS_OA_RESET = 0x20ea # macro
mmGDS_OA_RESET_BASE_IDX = 0 # macro
mmGDS_ENHANCE2 = 0x20eb # macro
mmGDS_ENHANCE2_BASE_IDX = 0 # macro
mmGDS_OA_CGPG_RESTORE = 0x20ec # macro
mmGDS_OA_CGPG_RESTORE_BASE_IDX = 0 # macro
mmGDS_CS_CTXSW_STATUS = 0x20ed # macro
mmGDS_CS_CTXSW_STATUS_BASE_IDX = 0 # macro
mmGDS_CS_CTXSW_CNT0 = 0x20ee # macro
mmGDS_CS_CTXSW_CNT0_BASE_IDX = 0 # macro
mmGDS_CS_CTXSW_CNT1 = 0x20ef # macro
mmGDS_CS_CTXSW_CNT1_BASE_IDX = 0 # macro
mmGDS_CS_CTXSW_CNT2 = 0x20f0 # macro
mmGDS_CS_CTXSW_CNT2_BASE_IDX = 0 # macro
mmGDS_CS_CTXSW_CNT3 = 0x20f1 # macro
mmGDS_CS_CTXSW_CNT3_BASE_IDX = 0 # macro
mmGDS_GFX_CTXSW_STATUS = 0x20f2 # macro
mmGDS_GFX_CTXSW_STATUS_BASE_IDX = 0 # macro
mmGDS_VS_CTXSW_CNT0 = 0x20f3 # macro
mmGDS_VS_CTXSW_CNT0_BASE_IDX = 0 # macro
mmGDS_VS_CTXSW_CNT1 = 0x20f4 # macro
mmGDS_VS_CTXSW_CNT1_BASE_IDX = 0 # macro
mmGDS_VS_CTXSW_CNT2 = 0x20f5 # macro
mmGDS_VS_CTXSW_CNT2_BASE_IDX = 0 # macro
mmGDS_VS_CTXSW_CNT3 = 0x20f6 # macro
mmGDS_VS_CTXSW_CNT3_BASE_IDX = 0 # macro
mmGDS_PS_CTXSW_CNT0 = 0x20f7 # macro
mmGDS_PS_CTXSW_CNT0_BASE_IDX = 0 # macro
mmGDS_PS_CTXSW_CNT1 = 0x20f8 # macro
mmGDS_PS_CTXSW_CNT1_BASE_IDX = 0 # macro
mmGDS_PS_CTXSW_CNT2 = 0x20f9 # macro
mmGDS_PS_CTXSW_CNT2_BASE_IDX = 0 # macro
mmGDS_PS_CTXSW_CNT3 = 0x20fa # macro
mmGDS_PS_CTXSW_CNT3_BASE_IDX = 0 # macro
mmGDS_PS_CTXSW_IDX = 0x20fb # macro
mmGDS_PS_CTXSW_IDX_BASE_IDX = 0 # macro
mmGDS_GS_CTXSW_CNT0 = 0x2117 # macro
mmGDS_GS_CTXSW_CNT0_BASE_IDX = 0 # macro
mmGDS_GS_CTXSW_CNT1 = 0x2118 # macro
mmGDS_GS_CTXSW_CNT1_BASE_IDX = 0 # macro
mmGDS_GS_CTXSW_CNT2 = 0x2119 # macro
mmGDS_GS_CTXSW_CNT2_BASE_IDX = 0 # macro
mmGDS_GS_CTXSW_CNT3 = 0x211a # macro
mmGDS_GS_CTXSW_CNT3_BASE_IDX = 0 # macro
mmGDS_MEMORY_CLEAN = 0x211f # macro
mmGDS_MEMORY_CLEAN_BASE_IDX = 0 # macro
mmDB_RENDER_CONTROL = 0x0000 # macro
mmDB_RENDER_CONTROL_BASE_IDX = 1 # macro
mmDB_COUNT_CONTROL = 0x0001 # macro
mmDB_COUNT_CONTROL_BASE_IDX = 1 # macro
mmDB_DEPTH_VIEW = 0x0002 # macro
mmDB_DEPTH_VIEW_BASE_IDX = 1 # macro
mmDB_RENDER_OVERRIDE = 0x0003 # macro
mmDB_RENDER_OVERRIDE_BASE_IDX = 1 # macro
mmDB_RENDER_OVERRIDE2 = 0x0004 # macro
mmDB_RENDER_OVERRIDE2_BASE_IDX = 1 # macro
mmDB_HTILE_DATA_BASE = 0x0005 # macro
mmDB_HTILE_DATA_BASE_BASE_IDX = 1 # macro
mmDB_DEPTH_SIZE_XY = 0x0007 # macro
mmDB_DEPTH_SIZE_XY_BASE_IDX = 1 # macro
mmDB_DEPTH_BOUNDS_MIN = 0x0008 # macro
mmDB_DEPTH_BOUNDS_MIN_BASE_IDX = 1 # macro
mmDB_DEPTH_BOUNDS_MAX = 0x0009 # macro
mmDB_DEPTH_BOUNDS_MAX_BASE_IDX = 1 # macro
mmDB_STENCIL_CLEAR = 0x000a # macro
mmDB_STENCIL_CLEAR_BASE_IDX = 1 # macro
mmDB_DEPTH_CLEAR = 0x000b # macro
mmDB_DEPTH_CLEAR_BASE_IDX = 1 # macro
mmPA_SC_SCREEN_SCISSOR_TL = 0x000c # macro
mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX = 1 # macro
mmPA_SC_SCREEN_SCISSOR_BR = 0x000d # macro
mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX = 1 # macro
mmDB_DFSM_CONTROL = 0x000e # macro
mmDB_DFSM_CONTROL_BASE_IDX = 1 # macro
mmDB_RESERVED_REG_2 = 0x000f # macro
mmDB_RESERVED_REG_2_BASE_IDX = 1 # macro
mmDB_Z_INFO = 0x0010 # macro
mmDB_Z_INFO_BASE_IDX = 1 # macro
mmDB_STENCIL_INFO = 0x0011 # macro
mmDB_STENCIL_INFO_BASE_IDX = 1 # macro
mmDB_Z_READ_BASE = 0x0012 # macro
mmDB_Z_READ_BASE_BASE_IDX = 1 # macro
mmDB_STENCIL_READ_BASE = 0x0013 # macro
mmDB_STENCIL_READ_BASE_BASE_IDX = 1 # macro
mmDB_Z_WRITE_BASE = 0x0014 # macro
mmDB_Z_WRITE_BASE_BASE_IDX = 1 # macro
mmDB_STENCIL_WRITE_BASE = 0x0015 # macro
mmDB_STENCIL_WRITE_BASE_BASE_IDX = 1 # macro
mmDB_RESERVED_REG_1 = 0x0016 # macro
mmDB_RESERVED_REG_1_BASE_IDX = 1 # macro
mmDB_RESERVED_REG_3 = 0x0017 # macro
mmDB_RESERVED_REG_3_BASE_IDX = 1 # macro
mmDB_VRS_OVERRIDE_CNTL = 0x0019 # macro
mmDB_VRS_OVERRIDE_CNTL_BASE_IDX = 1 # macro
mmDB_Z_READ_BASE_HI = 0x001a # macro
mmDB_Z_READ_BASE_HI_BASE_IDX = 1 # macro
mmDB_STENCIL_READ_BASE_HI = 0x001b # macro
mmDB_STENCIL_READ_BASE_HI_BASE_IDX = 1 # macro
mmDB_Z_WRITE_BASE_HI = 0x001c # macro
mmDB_Z_WRITE_BASE_HI_BASE_IDX = 1 # macro
mmDB_STENCIL_WRITE_BASE_HI = 0x001d # macro
mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX = 1 # macro
mmDB_HTILE_DATA_BASE_HI = 0x001e # macro
mmDB_HTILE_DATA_BASE_HI_BASE_IDX = 1 # macro
mmDB_RMI_L2_CACHE_CONTROL = 0x001f # macro
mmDB_RMI_L2_CACHE_CONTROL_BASE_IDX = 1 # macro
mmTA_BC_BASE_ADDR = 0x0020 # macro
mmTA_BC_BASE_ADDR_BASE_IDX = 1 # macro
mmTA_BC_BASE_ADDR_HI = 0x0021 # macro
mmTA_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro
mmCOHER_DEST_BASE_HI_0 = 0x007a # macro
mmCOHER_DEST_BASE_HI_0_BASE_IDX = 1 # macro
mmCOHER_DEST_BASE_HI_1 = 0x007b # macro
mmCOHER_DEST_BASE_HI_1_BASE_IDX = 1 # macro
mmCOHER_DEST_BASE_HI_2 = 0x007c # macro
mmCOHER_DEST_BASE_HI_2_BASE_IDX = 1 # macro
mmCOHER_DEST_BASE_HI_3 = 0x007d # macro
mmCOHER_DEST_BASE_HI_3_BASE_IDX = 1 # macro
mmCOHER_DEST_BASE_2 = 0x007e # macro
mmCOHER_DEST_BASE_2_BASE_IDX = 1 # macro
mmCOHER_DEST_BASE_3 = 0x007f # macro
mmCOHER_DEST_BASE_3_BASE_IDX = 1 # macro
mmPA_SC_WINDOW_OFFSET = 0x0080 # macro
mmPA_SC_WINDOW_OFFSET_BASE_IDX = 1 # macro
mmPA_SC_WINDOW_SCISSOR_TL = 0x0081 # macro
mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX = 1 # macro
mmPA_SC_WINDOW_SCISSOR_BR = 0x0082 # macro
mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX = 1 # macro
mmPA_SC_CLIPRECT_RULE = 0x0083 # macro
mmPA_SC_CLIPRECT_RULE_BASE_IDX = 1 # macro
mmPA_SC_CLIPRECT_0_TL = 0x0084 # macro
mmPA_SC_CLIPRECT_0_TL_BASE_IDX = 1 # macro
mmPA_SC_CLIPRECT_0_BR = 0x0085 # macro
mmPA_SC_CLIPRECT_0_BR_BASE_IDX = 1 # macro
mmPA_SC_CLIPRECT_1_TL = 0x0086 # macro
mmPA_SC_CLIPRECT_1_TL_BASE_IDX = 1 # macro
mmPA_SC_CLIPRECT_1_BR = 0x0087 # macro
mmPA_SC_CLIPRECT_1_BR_BASE_IDX = 1 # macro
mmPA_SC_CLIPRECT_2_TL = 0x0088 # macro
mmPA_SC_CLIPRECT_2_TL_BASE_IDX = 1 # macro
mmPA_SC_CLIPRECT_2_BR = 0x0089 # macro
mmPA_SC_CLIPRECT_2_BR_BASE_IDX = 1 # macro
mmPA_SC_CLIPRECT_3_TL = 0x008a # macro
mmPA_SC_CLIPRECT_3_TL_BASE_IDX = 1 # macro
mmPA_SC_CLIPRECT_3_BR = 0x008b # macro
mmPA_SC_CLIPRECT_3_BR_BASE_IDX = 1 # macro
mmPA_SC_EDGERULE = 0x008c # macro
mmPA_SC_EDGERULE_BASE_IDX = 1 # macro
mmPA_SU_HARDWARE_SCREEN_OFFSET = 0x008d # macro
mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX = 1 # macro
mmCB_TARGET_MASK = 0x008e # macro
mmCB_TARGET_MASK_BASE_IDX = 1 # macro
mmCB_SHADER_MASK = 0x008f # macro
mmCB_SHADER_MASK_BASE_IDX = 1 # macro
mmPA_SC_GENERIC_SCISSOR_TL = 0x0090 # macro
mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX = 1 # macro
mmPA_SC_GENERIC_SCISSOR_BR = 0x0091 # macro
mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX = 1 # macro
mmCOHER_DEST_BASE_0 = 0x0092 # macro
mmCOHER_DEST_BASE_0_BASE_IDX = 1 # macro
mmCOHER_DEST_BASE_1 = 0x0093 # macro
mmCOHER_DEST_BASE_1_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_0_TL = 0x0094 # macro
mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_0_BR = 0x0095 # macro
mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_1_TL = 0x0096 # macro
mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_1_BR = 0x0097 # macro
mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_2_TL = 0x0098 # macro
mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_2_BR = 0x0099 # macro
mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_3_TL = 0x009a # macro
mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_3_BR = 0x009b # macro
mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_4_TL = 0x009c # macro
mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_4_BR = 0x009d # macro
mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_5_TL = 0x009e # macro
mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_5_BR = 0x009f # macro
mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_6_TL = 0x00a0 # macro
mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_6_BR = 0x00a1 # macro
mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_7_TL = 0x00a2 # macro
mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_7_BR = 0x00a3 # macro
mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_8_TL = 0x00a4 # macro
mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_8_BR = 0x00a5 # macro
mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_9_TL = 0x00a6 # macro
mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_9_BR = 0x00a7 # macro
mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_10_TL = 0x00a8 # macro
mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_10_BR = 0x00a9 # macro
mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_11_TL = 0x00aa # macro
mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_11_BR = 0x00ab # macro
mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_12_TL = 0x00ac # macro
mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_12_BR = 0x00ad # macro
mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_13_TL = 0x00ae # macro
mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_13_BR = 0x00af # macro
mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_14_TL = 0x00b0 # macro
mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_14_BR = 0x00b1 # macro
mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_15_TL = 0x00b2 # macro
mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX = 1 # macro
mmPA_SC_VPORT_SCISSOR_15_BR = 0x00b3 # macro
mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_0 = 0x00b4 # macro
mmPA_SC_VPORT_ZMIN_0_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_0 = 0x00b5 # macro
mmPA_SC_VPORT_ZMAX_0_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_1 = 0x00b6 # macro
mmPA_SC_VPORT_ZMIN_1_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_1 = 0x00b7 # macro
mmPA_SC_VPORT_ZMAX_1_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_2 = 0x00b8 # macro
mmPA_SC_VPORT_ZMIN_2_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_2 = 0x00b9 # macro
mmPA_SC_VPORT_ZMAX_2_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_3 = 0x00ba # macro
mmPA_SC_VPORT_ZMIN_3_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_3 = 0x00bb # macro
mmPA_SC_VPORT_ZMAX_3_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_4 = 0x00bc # macro
mmPA_SC_VPORT_ZMIN_4_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_4 = 0x00bd # macro
mmPA_SC_VPORT_ZMAX_4_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_5 = 0x00be # macro
mmPA_SC_VPORT_ZMIN_5_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_5 = 0x00bf # macro
mmPA_SC_VPORT_ZMAX_5_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_6 = 0x00c0 # macro
mmPA_SC_VPORT_ZMIN_6_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_6 = 0x00c1 # macro
mmPA_SC_VPORT_ZMAX_6_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_7 = 0x00c2 # macro
mmPA_SC_VPORT_ZMIN_7_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_7 = 0x00c3 # macro
mmPA_SC_VPORT_ZMAX_7_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_8 = 0x00c4 # macro
mmPA_SC_VPORT_ZMIN_8_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_8 = 0x00c5 # macro
mmPA_SC_VPORT_ZMAX_8_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_9 = 0x00c6 # macro
mmPA_SC_VPORT_ZMIN_9_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_9 = 0x00c7 # macro
mmPA_SC_VPORT_ZMAX_9_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_10 = 0x00c8 # macro
mmPA_SC_VPORT_ZMIN_10_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_10 = 0x00c9 # macro
mmPA_SC_VPORT_ZMAX_10_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_11 = 0x00ca # macro
mmPA_SC_VPORT_ZMIN_11_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_11 = 0x00cb # macro
mmPA_SC_VPORT_ZMAX_11_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_12 = 0x00cc # macro
mmPA_SC_VPORT_ZMIN_12_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_12 = 0x00cd # macro
mmPA_SC_VPORT_ZMAX_12_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_13 = 0x00ce # macro
mmPA_SC_VPORT_ZMIN_13_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_13 = 0x00cf # macro
mmPA_SC_VPORT_ZMAX_13_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_14 = 0x00d0 # macro
mmPA_SC_VPORT_ZMIN_14_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_14 = 0x00d1 # macro
mmPA_SC_VPORT_ZMAX_14_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMIN_15 = 0x00d2 # macro
mmPA_SC_VPORT_ZMIN_15_BASE_IDX = 1 # macro
mmPA_SC_VPORT_ZMAX_15 = 0x00d3 # macro
mmPA_SC_VPORT_ZMAX_15_BASE_IDX = 1 # macro
mmPA_SC_RASTER_CONFIG = 0x00d4 # macro
mmPA_SC_RASTER_CONFIG_BASE_IDX = 1 # macro
mmPA_SC_RASTER_CONFIG_1 = 0x00d5 # macro
mmPA_SC_RASTER_CONFIG_1_BASE_IDX = 1 # macro
mmPA_SC_SCREEN_EXTENT_CONTROL = 0x00d6 # macro
mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX = 1 # macro
mmPA_SC_TILE_STEERING_OVERRIDE = 0x00d7 # macro
mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX = 1 # macro
mmCP_PERFMON_CNTX_CNTL = 0x00d8 # macro
mmCP_PERFMON_CNTX_CNTL_BASE_IDX = 1 # macro
mmCP_PIPEID = 0x00d9 # macro
mmCP_PIPEID_BASE_IDX = 1 # macro
mmCP_RINGID = 0x00d9 # macro
mmCP_RINGID_BASE_IDX = 1 # macro
mmCP_VMID = 0x00da # macro
mmCP_VMID_BASE_IDX = 1 # macro
mmCONTEXT_RESERVED_REG0 = 0x00db # macro
mmCONTEXT_RESERVED_REG0_BASE_IDX = 1 # macro
mmCONTEXT_RESERVED_REG1 = 0x00dc # macro
mmCONTEXT_RESERVED_REG1_BASE_IDX = 1 # macro
mmVGT_MAX_VTX_INDX = 0x0100 # macro
mmVGT_MAX_VTX_INDX_BASE_IDX = 1 # macro
mmVGT_MIN_VTX_INDX = 0x0101 # macro
mmVGT_MIN_VTX_INDX_BASE_IDX = 1 # macro
mmVGT_INDX_OFFSET = 0x0102 # macro
mmVGT_INDX_OFFSET_BASE_IDX = 1 # macro
mmVGT_MULTI_PRIM_IB_RESET_INDX = 0x0103 # macro
mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX = 1 # macro
mmCB_RMI_GL2_CACHE_CONTROL = 0x0104 # macro
mmCB_RMI_GL2_CACHE_CONTROL_BASE_IDX = 1 # macro
mmCB_BLEND_RED = 0x0105 # macro
mmCB_BLEND_RED_BASE_IDX = 1 # macro
mmCB_BLEND_GREEN = 0x0106 # macro
mmCB_BLEND_GREEN_BASE_IDX = 1 # macro
mmCB_BLEND_BLUE = 0x0107 # macro
mmCB_BLEND_BLUE_BASE_IDX = 1 # macro
mmCB_BLEND_ALPHA = 0x0108 # macro
mmCB_BLEND_ALPHA_BASE_IDX = 1 # macro
mmCB_DCC_CONTROL = 0x0109 # macro
mmCB_DCC_CONTROL_BASE_IDX = 1 # macro
mmCB_COVERAGE_OUT_CONTROL = 0x010a # macro
mmCB_COVERAGE_OUT_CONTROL_BASE_IDX = 1 # macro
mmDB_STENCIL_CONTROL = 0x010b # macro
mmDB_STENCIL_CONTROL_BASE_IDX = 1 # macro
mmDB_STENCILREFMASK = 0x010c # macro
mmDB_STENCILREFMASK_BASE_IDX = 1 # macro
mmDB_STENCILREFMASK_BF = 0x010d # macro
mmDB_STENCILREFMASK_BF_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE = 0x010f # macro
mmPA_CL_VPORT_XSCALE_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET = 0x0110 # macro
mmPA_CL_VPORT_XOFFSET_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE = 0x0111 # macro
mmPA_CL_VPORT_YSCALE_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET = 0x0112 # macro
mmPA_CL_VPORT_YOFFSET_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE = 0x0113 # macro
mmPA_CL_VPORT_ZSCALE_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET = 0x0114 # macro
mmPA_CL_VPORT_ZOFFSET_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_1 = 0x0115 # macro
mmPA_CL_VPORT_XSCALE_1_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_1 = 0x0116 # macro
mmPA_CL_VPORT_XOFFSET_1_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_1 = 0x0117 # macro
mmPA_CL_VPORT_YSCALE_1_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_1 = 0x0118 # macro
mmPA_CL_VPORT_YOFFSET_1_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_1 = 0x0119 # macro
mmPA_CL_VPORT_ZSCALE_1_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_1 = 0x011a # macro
mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_2 = 0x011b # macro
mmPA_CL_VPORT_XSCALE_2_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_2 = 0x011c # macro
mmPA_CL_VPORT_XOFFSET_2_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_2 = 0x011d # macro
mmPA_CL_VPORT_YSCALE_2_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_2 = 0x011e # macro
mmPA_CL_VPORT_YOFFSET_2_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_2 = 0x011f # macro
mmPA_CL_VPORT_ZSCALE_2_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_2 = 0x0120 # macro
mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_3 = 0x0121 # macro
mmPA_CL_VPORT_XSCALE_3_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_3 = 0x0122 # macro
mmPA_CL_VPORT_XOFFSET_3_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_3 = 0x0123 # macro
mmPA_CL_VPORT_YSCALE_3_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_3 = 0x0124 # macro
mmPA_CL_VPORT_YOFFSET_3_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_3 = 0x0125 # macro
mmPA_CL_VPORT_ZSCALE_3_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_3 = 0x0126 # macro
mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_4 = 0x0127 # macro
mmPA_CL_VPORT_XSCALE_4_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_4 = 0x0128 # macro
mmPA_CL_VPORT_XOFFSET_4_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_4 = 0x0129 # macro
mmPA_CL_VPORT_YSCALE_4_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_4 = 0x012a # macro
mmPA_CL_VPORT_YOFFSET_4_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_4 = 0x012b # macro
mmPA_CL_VPORT_ZSCALE_4_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_4 = 0x012c # macro
mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_5 = 0x012d # macro
mmPA_CL_VPORT_XSCALE_5_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_5 = 0x012e # macro
mmPA_CL_VPORT_XOFFSET_5_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_5 = 0x012f # macro
mmPA_CL_VPORT_YSCALE_5_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_5 = 0x0130 # macro
mmPA_CL_VPORT_YOFFSET_5_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_5 = 0x0131 # macro
mmPA_CL_VPORT_ZSCALE_5_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_5 = 0x0132 # macro
mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_6 = 0x0133 # macro
mmPA_CL_VPORT_XSCALE_6_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_6 = 0x0134 # macro
mmPA_CL_VPORT_XOFFSET_6_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_6 = 0x0135 # macro
mmPA_CL_VPORT_YSCALE_6_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_6 = 0x0136 # macro
mmPA_CL_VPORT_YOFFSET_6_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_6 = 0x0137 # macro
mmPA_CL_VPORT_ZSCALE_6_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_6 = 0x0138 # macro
mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_7 = 0x0139 # macro
mmPA_CL_VPORT_XSCALE_7_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_7 = 0x013a # macro
mmPA_CL_VPORT_XOFFSET_7_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_7 = 0x013b # macro
mmPA_CL_VPORT_YSCALE_7_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_7 = 0x013c # macro
mmPA_CL_VPORT_YOFFSET_7_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_7 = 0x013d # macro
mmPA_CL_VPORT_ZSCALE_7_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_7 = 0x013e # macro
mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_8 = 0x013f # macro
mmPA_CL_VPORT_XSCALE_8_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_8 = 0x0140 # macro
mmPA_CL_VPORT_XOFFSET_8_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_8 = 0x0141 # macro
mmPA_CL_VPORT_YSCALE_8_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_8 = 0x0142 # macro
mmPA_CL_VPORT_YOFFSET_8_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_8 = 0x0143 # macro
mmPA_CL_VPORT_ZSCALE_8_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_8 = 0x0144 # macro
mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_9 = 0x0145 # macro
mmPA_CL_VPORT_XSCALE_9_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_9 = 0x0146 # macro
mmPA_CL_VPORT_XOFFSET_9_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_9 = 0x0147 # macro
mmPA_CL_VPORT_YSCALE_9_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_9 = 0x0148 # macro
mmPA_CL_VPORT_YOFFSET_9_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_9 = 0x0149 # macro
mmPA_CL_VPORT_ZSCALE_9_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_9 = 0x014a # macro
mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_10 = 0x014b # macro
mmPA_CL_VPORT_XSCALE_10_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_10 = 0x014c # macro
mmPA_CL_VPORT_XOFFSET_10_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_10 = 0x014d # macro
mmPA_CL_VPORT_YSCALE_10_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_10 = 0x014e # macro
mmPA_CL_VPORT_YOFFSET_10_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_10 = 0x014f # macro
mmPA_CL_VPORT_ZSCALE_10_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_10 = 0x0150 # macro
mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_11 = 0x0151 # macro
mmPA_CL_VPORT_XSCALE_11_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_11 = 0x0152 # macro
mmPA_CL_VPORT_XOFFSET_11_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_11 = 0x0153 # macro
mmPA_CL_VPORT_YSCALE_11_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_11 = 0x0154 # macro
mmPA_CL_VPORT_YOFFSET_11_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_11 = 0x0155 # macro
mmPA_CL_VPORT_ZSCALE_11_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_11 = 0x0156 # macro
mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_12 = 0x0157 # macro
mmPA_CL_VPORT_XSCALE_12_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_12 = 0x0158 # macro
mmPA_CL_VPORT_XOFFSET_12_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_12 = 0x0159 # macro
mmPA_CL_VPORT_YSCALE_12_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_12 = 0x015a # macro
mmPA_CL_VPORT_YOFFSET_12_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_12 = 0x015b # macro
mmPA_CL_VPORT_ZSCALE_12_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_12 = 0x015c # macro
mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_13 = 0x015d # macro
mmPA_CL_VPORT_XSCALE_13_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_13 = 0x015e # macro
mmPA_CL_VPORT_XOFFSET_13_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_13 = 0x015f # macro
mmPA_CL_VPORT_YSCALE_13_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_13 = 0x0160 # macro
mmPA_CL_VPORT_YOFFSET_13_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_13 = 0x0161 # macro
mmPA_CL_VPORT_ZSCALE_13_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_13 = 0x0162 # macro
mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_14 = 0x0163 # macro
mmPA_CL_VPORT_XSCALE_14_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_14 = 0x0164 # macro
mmPA_CL_VPORT_XOFFSET_14_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_14 = 0x0165 # macro
mmPA_CL_VPORT_YSCALE_14_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_14 = 0x0166 # macro
mmPA_CL_VPORT_YOFFSET_14_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_14 = 0x0167 # macro
mmPA_CL_VPORT_ZSCALE_14_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_14 = 0x0168 # macro
mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XSCALE_15 = 0x0169 # macro
mmPA_CL_VPORT_XSCALE_15_BASE_IDX = 1 # macro
mmPA_CL_VPORT_XOFFSET_15 = 0x016a # macro
mmPA_CL_VPORT_XOFFSET_15_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YSCALE_15 = 0x016b # macro
mmPA_CL_VPORT_YSCALE_15_BASE_IDX = 1 # macro
mmPA_CL_VPORT_YOFFSET_15 = 0x016c # macro
mmPA_CL_VPORT_YOFFSET_15_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZSCALE_15 = 0x016d # macro
mmPA_CL_VPORT_ZSCALE_15_BASE_IDX = 1 # macro
mmPA_CL_VPORT_ZOFFSET_15 = 0x016e # macro
mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX = 1 # macro
mmPA_CL_UCP_0_X = 0x016f # macro
mmPA_CL_UCP_0_X_BASE_IDX = 1 # macro
mmPA_CL_UCP_0_Y = 0x0170 # macro
mmPA_CL_UCP_0_Y_BASE_IDX = 1 # macro
mmPA_CL_UCP_0_Z = 0x0171 # macro
mmPA_CL_UCP_0_Z_BASE_IDX = 1 # macro
mmPA_CL_UCP_0_W = 0x0172 # macro
mmPA_CL_UCP_0_W_BASE_IDX = 1 # macro
mmPA_CL_UCP_1_X = 0x0173 # macro
mmPA_CL_UCP_1_X_BASE_IDX = 1 # macro
mmPA_CL_UCP_1_Y = 0x0174 # macro
mmPA_CL_UCP_1_Y_BASE_IDX = 1 # macro
mmPA_CL_UCP_1_Z = 0x0175 # macro
mmPA_CL_UCP_1_Z_BASE_IDX = 1 # macro
mmPA_CL_UCP_1_W = 0x0176 # macro
mmPA_CL_UCP_1_W_BASE_IDX = 1 # macro
mmPA_CL_UCP_2_X = 0x0177 # macro
mmPA_CL_UCP_2_X_BASE_IDX = 1 # macro
mmPA_CL_UCP_2_Y = 0x0178 # macro
mmPA_CL_UCP_2_Y_BASE_IDX = 1 # macro
mmPA_CL_UCP_2_Z = 0x0179 # macro
mmPA_CL_UCP_2_Z_BASE_IDX = 1 # macro
mmPA_CL_UCP_2_W = 0x017a # macro
mmPA_CL_UCP_2_W_BASE_IDX = 1 # macro
mmPA_CL_UCP_3_X = 0x017b # macro
mmPA_CL_UCP_3_X_BASE_IDX = 1 # macro
mmPA_CL_UCP_3_Y = 0x017c # macro
mmPA_CL_UCP_3_Y_BASE_IDX = 1 # macro
mmPA_CL_UCP_3_Z = 0x017d # macro
mmPA_CL_UCP_3_Z_BASE_IDX = 1 # macro
mmPA_CL_UCP_3_W = 0x017e # macro
mmPA_CL_UCP_3_W_BASE_IDX = 1 # macro
mmPA_CL_UCP_4_X = 0x017f # macro
mmPA_CL_UCP_4_X_BASE_IDX = 1 # macro
mmPA_CL_UCP_4_Y = 0x0180 # macro
mmPA_CL_UCP_4_Y_BASE_IDX = 1 # macro
mmPA_CL_UCP_4_Z = 0x0181 # macro
mmPA_CL_UCP_4_Z_BASE_IDX = 1 # macro
mmPA_CL_UCP_4_W = 0x0182 # macro
mmPA_CL_UCP_4_W_BASE_IDX = 1 # macro
mmPA_CL_UCP_5_X = 0x0183 # macro
mmPA_CL_UCP_5_X_BASE_IDX = 1 # macro
mmPA_CL_UCP_5_Y = 0x0184 # macro
mmPA_CL_UCP_5_Y_BASE_IDX = 1 # macro
mmPA_CL_UCP_5_Z = 0x0185 # macro
mmPA_CL_UCP_5_Z_BASE_IDX = 1 # macro
mmPA_CL_UCP_5_W = 0x0186 # macro
mmPA_CL_UCP_5_W_BASE_IDX = 1 # macro
mmPA_CL_PROG_NEAR_CLIP_Z = 0x0187 # macro
mmPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_0 = 0x0191 # macro
mmSPI_PS_INPUT_CNTL_0_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_1 = 0x0192 # macro
mmSPI_PS_INPUT_CNTL_1_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_2 = 0x0193 # macro
mmSPI_PS_INPUT_CNTL_2_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_3 = 0x0194 # macro
mmSPI_PS_INPUT_CNTL_3_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_4 = 0x0195 # macro
mmSPI_PS_INPUT_CNTL_4_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_5 = 0x0196 # macro
mmSPI_PS_INPUT_CNTL_5_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_6 = 0x0197 # macro
mmSPI_PS_INPUT_CNTL_6_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_7 = 0x0198 # macro
mmSPI_PS_INPUT_CNTL_7_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_8 = 0x0199 # macro
mmSPI_PS_INPUT_CNTL_8_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_9 = 0x019a # macro
mmSPI_PS_INPUT_CNTL_9_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_10 = 0x019b # macro
mmSPI_PS_INPUT_CNTL_10_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_11 = 0x019c # macro
mmSPI_PS_INPUT_CNTL_11_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_12 = 0x019d # macro
mmSPI_PS_INPUT_CNTL_12_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_13 = 0x019e # macro
mmSPI_PS_INPUT_CNTL_13_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_14 = 0x019f # macro
mmSPI_PS_INPUT_CNTL_14_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_15 = 0x01a0 # macro
mmSPI_PS_INPUT_CNTL_15_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_16 = 0x01a1 # macro
mmSPI_PS_INPUT_CNTL_16_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_17 = 0x01a2 # macro
mmSPI_PS_INPUT_CNTL_17_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_18 = 0x01a3 # macro
mmSPI_PS_INPUT_CNTL_18_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_19 = 0x01a4 # macro
mmSPI_PS_INPUT_CNTL_19_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_20 = 0x01a5 # macro
mmSPI_PS_INPUT_CNTL_20_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_21 = 0x01a6 # macro
mmSPI_PS_INPUT_CNTL_21_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_22 = 0x01a7 # macro
mmSPI_PS_INPUT_CNTL_22_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_23 = 0x01a8 # macro
mmSPI_PS_INPUT_CNTL_23_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_24 = 0x01a9 # macro
mmSPI_PS_INPUT_CNTL_24_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_25 = 0x01aa # macro
mmSPI_PS_INPUT_CNTL_25_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_26 = 0x01ab # macro
mmSPI_PS_INPUT_CNTL_26_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_27 = 0x01ac # macro
mmSPI_PS_INPUT_CNTL_27_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_28 = 0x01ad # macro
mmSPI_PS_INPUT_CNTL_28_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_29 = 0x01ae # macro
mmSPI_PS_INPUT_CNTL_29_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_30 = 0x01af # macro
mmSPI_PS_INPUT_CNTL_30_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_CNTL_31 = 0x01b0 # macro
mmSPI_PS_INPUT_CNTL_31_BASE_IDX = 1 # macro
mmSPI_VS_OUT_CONFIG = 0x01b1 # macro
mmSPI_VS_OUT_CONFIG_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_ENA = 0x01b3 # macro
mmSPI_PS_INPUT_ENA_BASE_IDX = 1 # macro
mmSPI_PS_INPUT_ADDR = 0x01b4 # macro
mmSPI_PS_INPUT_ADDR_BASE_IDX = 1 # macro
mmSPI_INTERP_CONTROL_0 = 0x01b5 # macro
mmSPI_INTERP_CONTROL_0_BASE_IDX = 1 # macro
mmSPI_PS_IN_CONTROL = 0x01b6 # macro
mmSPI_PS_IN_CONTROL_BASE_IDX = 1 # macro
mmSPI_BARYC_CNTL = 0x01b8 # macro
mmSPI_BARYC_CNTL_BASE_IDX = 1 # macro
mmSPI_TMPRING_SIZE = 0x01ba # macro
mmSPI_TMPRING_SIZE_BASE_IDX = 1 # macro
mmSPI_SHADER_IDX_FORMAT = 0x01c2 # macro
mmSPI_SHADER_IDX_FORMAT_BASE_IDX = 1 # macro
mmSPI_SHADER_POS_FORMAT = 0x01c3 # macro
mmSPI_SHADER_POS_FORMAT_BASE_IDX = 1 # macro
mmSPI_SHADER_Z_FORMAT = 0x01c4 # macro
mmSPI_SHADER_Z_FORMAT_BASE_IDX = 1 # macro
mmSPI_SHADER_COL_FORMAT = 0x01c5 # macro
mmSPI_SHADER_COL_FORMAT_BASE_IDX = 1 # macro
mmSX_PS_DOWNCONVERT_CONTROL = 0x01d4 # macro
mmSX_PS_DOWNCONVERT_CONTROL_BASE_IDX = 1 # macro
mmSX_PS_DOWNCONVERT = 0x01d5 # macro
mmSX_PS_DOWNCONVERT_BASE_IDX = 1 # macro
mmSX_BLEND_OPT_EPSILON = 0x01d6 # macro
mmSX_BLEND_OPT_EPSILON_BASE_IDX = 1 # macro
mmSX_BLEND_OPT_CONTROL = 0x01d7 # macro
mmSX_BLEND_OPT_CONTROL_BASE_IDX = 1 # macro
mmSX_MRT0_BLEND_OPT = 0x01d8 # macro
mmSX_MRT0_BLEND_OPT_BASE_IDX = 1 # macro
mmSX_MRT1_BLEND_OPT = 0x01d9 # macro
mmSX_MRT1_BLEND_OPT_BASE_IDX = 1 # macro
mmSX_MRT2_BLEND_OPT = 0x01da # macro
mmSX_MRT2_BLEND_OPT_BASE_IDX = 1 # macro
mmSX_MRT3_BLEND_OPT = 0x01db # macro
mmSX_MRT3_BLEND_OPT_BASE_IDX = 1 # macro
mmSX_MRT4_BLEND_OPT = 0x01dc # macro
mmSX_MRT4_BLEND_OPT_BASE_IDX = 1 # macro
mmSX_MRT5_BLEND_OPT = 0x01dd # macro
mmSX_MRT5_BLEND_OPT_BASE_IDX = 1 # macro
mmSX_MRT6_BLEND_OPT = 0x01de # macro
mmSX_MRT6_BLEND_OPT_BASE_IDX = 1 # macro
mmSX_MRT7_BLEND_OPT = 0x01df # macro
mmSX_MRT7_BLEND_OPT_BASE_IDX = 1 # macro
mmCB_BLEND0_CONTROL = 0x01e0 # macro
mmCB_BLEND0_CONTROL_BASE_IDX = 1 # macro
mmCB_BLEND1_CONTROL = 0x01e1 # macro
mmCB_BLEND1_CONTROL_BASE_IDX = 1 # macro
mmCB_BLEND2_CONTROL = 0x01e2 # macro
mmCB_BLEND2_CONTROL_BASE_IDX = 1 # macro
mmCB_BLEND3_CONTROL = 0x01e3 # macro
mmCB_BLEND3_CONTROL_BASE_IDX = 1 # macro
mmCB_BLEND4_CONTROL = 0x01e4 # macro
mmCB_BLEND4_CONTROL_BASE_IDX = 1 # macro
mmCB_BLEND5_CONTROL = 0x01e5 # macro
mmCB_BLEND5_CONTROL_BASE_IDX = 1 # macro
mmCB_BLEND6_CONTROL = 0x01e6 # macro
mmCB_BLEND6_CONTROL_BASE_IDX = 1 # macro
mmCB_BLEND7_CONTROL = 0x01e7 # macro
mmCB_BLEND7_CONTROL_BASE_IDX = 1 # macro
mmCS_COPY_STATE = 0x01f3 # macro
mmCS_COPY_STATE_BASE_IDX = 1 # macro
mmGFX_COPY_STATE = 0x01f4 # macro
mmGFX_COPY_STATE_BASE_IDX = 1 # macro
mmPA_CL_POINT_X_RAD = 0x01f5 # macro
mmPA_CL_POINT_X_RAD_BASE_IDX = 1 # macro
mmPA_CL_POINT_Y_RAD = 0x01f6 # macro
mmPA_CL_POINT_Y_RAD_BASE_IDX = 1 # macro
mmPA_CL_POINT_SIZE = 0x01f7 # macro
mmPA_CL_POINT_SIZE_BASE_IDX = 1 # macro
mmPA_CL_POINT_CULL_RAD = 0x01f8 # macro
mmPA_CL_POINT_CULL_RAD_BASE_IDX = 1 # macro
mmVGT_DMA_BASE_HI = 0x01f9 # macro
mmVGT_DMA_BASE_HI_BASE_IDX = 1 # macro
mmVGT_DMA_BASE = 0x01fa # macro
mmVGT_DMA_BASE_BASE_IDX = 1 # macro
mmVGT_DRAW_INITIATOR = 0x01fc # macro
mmVGT_DRAW_INITIATOR_BASE_IDX = 1 # macro
mmVGT_IMMED_DATA = 0x01fd # macro
mmVGT_IMMED_DATA_BASE_IDX = 1 # macro
mmVGT_EVENT_ADDRESS_REG = 0x01fe # macro
mmVGT_EVENT_ADDRESS_REG_BASE_IDX = 1 # macro
mmGE_MAX_OUTPUT_PER_SUBGROUP = 0x01ff # macro
mmGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX = 1 # macro
mmDB_DEPTH_CONTROL = 0x0200 # macro
mmDB_DEPTH_CONTROL_BASE_IDX = 1 # macro
mmDB_EQAA = 0x0201 # macro
mmDB_EQAA_BASE_IDX = 1 # macro
mmCB_COLOR_CONTROL = 0x0202 # macro
mmCB_COLOR_CONTROL_BASE_IDX = 1 # macro
mmDB_SHADER_CONTROL = 0x0203 # macro
mmDB_SHADER_CONTROL_BASE_IDX = 1 # macro
mmPA_CL_CLIP_CNTL = 0x0204 # macro
mmPA_CL_CLIP_CNTL_BASE_IDX = 1 # macro
mmPA_SU_SC_MODE_CNTL = 0x0205 # macro
mmPA_SU_SC_MODE_CNTL_BASE_IDX = 1 # macro
mmPA_CL_VTE_CNTL = 0x0206 # macro
mmPA_CL_VTE_CNTL_BASE_IDX = 1 # macro
mmPA_CL_VS_OUT_CNTL = 0x0207 # macro
mmPA_CL_VS_OUT_CNTL_BASE_IDX = 1 # macro
mmPA_CL_NANINF_CNTL = 0x0208 # macro
mmPA_CL_NANINF_CNTL_BASE_IDX = 1 # macro
mmPA_SU_LINE_STIPPLE_CNTL = 0x0209 # macro
mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX = 1 # macro
mmPA_SU_LINE_STIPPLE_SCALE = 0x020a # macro
mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX = 1 # macro
mmPA_SU_PRIM_FILTER_CNTL = 0x020b # macro
mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro
mmPA_SU_SMALL_PRIM_FILTER_CNTL = 0x020c # macro
mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro
mmPA_CL_NGG_CNTL = 0x020e # macro
mmPA_CL_NGG_CNTL_BASE_IDX = 1 # macro
mmPA_SU_OVER_RASTERIZATION_CNTL = 0x020f # macro
mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX = 1 # macro
mmPA_STEREO_CNTL = 0x0210 # macro
mmPA_STEREO_CNTL_BASE_IDX = 1 # macro
mmPA_STATE_STEREO_X = 0x0211 # macro
mmPA_STATE_STEREO_X_BASE_IDX = 1 # macro
mmPA_CL_VRS_CNTL = 0x0212 # macro
mmPA_CL_VRS_CNTL_BASE_IDX = 1 # macro
mmPA_SU_POINT_SIZE = 0x0280 # macro
mmPA_SU_POINT_SIZE_BASE_IDX = 1 # macro
mmPA_SU_POINT_MINMAX = 0x0281 # macro
mmPA_SU_POINT_MINMAX_BASE_IDX = 1 # macro
mmPA_SU_LINE_CNTL = 0x0282 # macro
mmPA_SU_LINE_CNTL_BASE_IDX = 1 # macro
mmPA_SC_LINE_STIPPLE = 0x0283 # macro
mmPA_SC_LINE_STIPPLE_BASE_IDX = 1 # macro
mmVGT_OUTPUT_PATH_CNTL = 0x0284 # macro
mmVGT_OUTPUT_PATH_CNTL_BASE_IDX = 1 # macro
mmVGT_HOS_CNTL = 0x0285 # macro
mmVGT_HOS_CNTL_BASE_IDX = 1 # macro
mmVGT_HOS_MAX_TESS_LEVEL = 0x0286 # macro
mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX = 1 # macro
mmVGT_HOS_MIN_TESS_LEVEL = 0x0287 # macro
mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX = 1 # macro
mmVGT_HOS_REUSE_DEPTH = 0x0288 # macro
mmVGT_HOS_REUSE_DEPTH_BASE_IDX = 1 # macro
mmVGT_GROUP_PRIM_TYPE = 0x0289 # macro
mmVGT_GROUP_PRIM_TYPE_BASE_IDX = 1 # macro
mmVGT_GROUP_FIRST_DECR = 0x028a # macro
mmVGT_GROUP_FIRST_DECR_BASE_IDX = 1 # macro
mmVGT_GROUP_DECR = 0x028b # macro
mmVGT_GROUP_DECR_BASE_IDX = 1 # macro
mmVGT_GROUP_VECT_0_CNTL = 0x028c # macro
mmVGT_GROUP_VECT_0_CNTL_BASE_IDX = 1 # macro
mmVGT_GROUP_VECT_1_CNTL = 0x028d # macro
mmVGT_GROUP_VECT_1_CNTL_BASE_IDX = 1 # macro
mmVGT_GROUP_VECT_0_FMT_CNTL = 0x028e # macro
mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX = 1 # macro
mmVGT_GROUP_VECT_1_FMT_CNTL = 0x028f # macro
mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX = 1 # macro
mmVGT_GS_MODE = 0x0290 # macro
mmVGT_GS_MODE_BASE_IDX = 1 # macro
mmVGT_GS_ONCHIP_CNTL = 0x0291 # macro
mmVGT_GS_ONCHIP_CNTL_BASE_IDX = 1 # macro
mmPA_SC_MODE_CNTL_0 = 0x0292 # macro
mmPA_SC_MODE_CNTL_0_BASE_IDX = 1 # macro
mmPA_SC_MODE_CNTL_1 = 0x0293 # macro
mmPA_SC_MODE_CNTL_1_BASE_IDX = 1 # macro
mmVGT_ENHANCE = 0x0294 # macro
mmVGT_ENHANCE_BASE_IDX = 1 # macro
mmVGT_GS_PER_ES = 0x0295 # macro
mmVGT_GS_PER_ES_BASE_IDX = 1 # macro
mmVGT_ES_PER_GS = 0x0296 # macro
mmVGT_ES_PER_GS_BASE_IDX = 1 # macro
mmVGT_GS_PER_VS = 0x0297 # macro
mmVGT_GS_PER_VS_BASE_IDX = 1 # macro
mmVGT_GSVS_RING_OFFSET_1 = 0x0298 # macro
mmVGT_GSVS_RING_OFFSET_1_BASE_IDX = 1 # macro
mmVGT_GSVS_RING_OFFSET_2 = 0x0299 # macro
mmVGT_GSVS_RING_OFFSET_2_BASE_IDX = 1 # macro
mmVGT_GSVS_RING_OFFSET_3 = 0x029a # macro
mmVGT_GSVS_RING_OFFSET_3_BASE_IDX = 1 # macro
mmVGT_GS_OUT_PRIM_TYPE = 0x029b # macro
mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX = 1 # macro
mmIA_ENHANCE = 0x029c # macro
mmIA_ENHANCE_BASE_IDX = 1 # macro
mmVGT_DMA_SIZE = 0x029d # macro
mmVGT_DMA_SIZE_BASE_IDX = 1 # macro
mmVGT_DMA_MAX_SIZE = 0x029e # macro
mmVGT_DMA_MAX_SIZE_BASE_IDX = 1 # macro
mmVGT_DMA_INDEX_TYPE = 0x029f # macro
mmVGT_DMA_INDEX_TYPE_BASE_IDX = 1 # macro
mmWD_ENHANCE = 0x02a0 # macro
mmWD_ENHANCE_BASE_IDX = 1 # macro
mmVGT_PRIMITIVEID_EN = 0x02a1 # macro
mmVGT_PRIMITIVEID_EN_BASE_IDX = 1 # macro
mmVGT_DMA_NUM_INSTANCES = 0x02a2 # macro
mmVGT_DMA_NUM_INSTANCES_BASE_IDX = 1 # macro
mmVGT_PRIMITIVEID_RESET = 0x02a3 # macro
mmVGT_PRIMITIVEID_RESET_BASE_IDX = 1 # macro
mmVGT_EVENT_INITIATOR = 0x02a4 # macro
mmVGT_EVENT_INITIATOR_BASE_IDX = 1 # macro
mmVGT_MULTI_PRIM_IB_RESET_EN = 0x02a5 # macro
mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX = 1 # macro
mmVGT_DRAW_PAYLOAD_CNTL = 0x02a6 # macro
mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX = 1 # macro
mmVGT_INSTANCE_STEP_RATE_0 = 0x02a8 # macro
mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX = 1 # macro
mmVGT_INSTANCE_STEP_RATE_1 = 0x02a9 # macro
mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX = 1 # macro
mmIA_MULTI_VGT_PARAM = 0x02aa # macro
mmIA_MULTI_VGT_PARAM_BASE_IDX = 1 # macro
mmVGT_ESGS_RING_ITEMSIZE = 0x02ab # macro
mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX = 1 # macro
mmVGT_GSVS_RING_ITEMSIZE = 0x02ac # macro
mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX = 1 # macro
mmVGT_REUSE_OFF = 0x02ad # macro
mmVGT_REUSE_OFF_BASE_IDX = 1 # macro
mmVGT_VTX_CNT_EN = 0x02ae # macro
mmVGT_VTX_CNT_EN_BASE_IDX = 1 # macro
mmDB_HTILE_SURFACE = 0x02af # macro
mmDB_HTILE_SURFACE_BASE_IDX = 1 # macro
mmDB_SRESULTS_COMPARE_STATE0 = 0x02b0 # macro
mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX = 1 # macro
mmDB_SRESULTS_COMPARE_STATE1 = 0x02b1 # macro
mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX = 1 # macro
mmDB_PRELOAD_CONTROL = 0x02b2 # macro
mmDB_PRELOAD_CONTROL_BASE_IDX = 1 # macro
mmVGT_STRMOUT_BUFFER_SIZE_0 = 0x02b4 # macro
mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX = 1 # macro
mmVGT_STRMOUT_VTX_STRIDE_0 = 0x02b5 # macro
mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX = 1 # macro
mmVGT_STRMOUT_BUFFER_OFFSET_0 = 0x02b7 # macro
mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX = 1 # macro
mmVGT_STRMOUT_BUFFER_SIZE_1 = 0x02b8 # macro
mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX = 1 # macro
mmVGT_STRMOUT_VTX_STRIDE_1 = 0x02b9 # macro
mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX = 1 # macro
mmVGT_STRMOUT_BUFFER_OFFSET_1 = 0x02bb # macro
mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX = 1 # macro
mmVGT_STRMOUT_BUFFER_SIZE_2 = 0x02bc # macro
mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX = 1 # macro
mmVGT_STRMOUT_VTX_STRIDE_2 = 0x02bd # macro
mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX = 1 # macro
mmVGT_STRMOUT_BUFFER_OFFSET_2 = 0x02bf # macro
mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX = 1 # macro
mmVGT_STRMOUT_BUFFER_SIZE_3 = 0x02c0 # macro
mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX = 1 # macro
mmVGT_STRMOUT_VTX_STRIDE_3 = 0x02c1 # macro
mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX = 1 # macro
mmVGT_STRMOUT_BUFFER_OFFSET_3 = 0x02c3 # macro
mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX = 1 # macro
mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x02ca # macro
mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX = 1 # macro
mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x02cb # macro
mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX = 1 # macro
mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x02cc # macro
mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX = 1 # macro
mmVGT_GS_MAX_VERT_OUT = 0x02ce # macro
mmVGT_GS_MAX_VERT_OUT_BASE_IDX = 1 # macro
mmGE_NGG_SUBGRP_CNTL = 0x02d3 # macro
mmGE_NGG_SUBGRP_CNTL_BASE_IDX = 1 # macro
mmVGT_TESS_DISTRIBUTION = 0x02d4 # macro
mmVGT_TESS_DISTRIBUTION_BASE_IDX = 1 # macro
mmVGT_SHADER_STAGES_EN = 0x02d5 # macro
mmVGT_SHADER_STAGES_EN_BASE_IDX = 1 # macro
mmVGT_LS_HS_CONFIG = 0x02d6 # macro
mmVGT_LS_HS_CONFIG_BASE_IDX = 1 # macro
mmVGT_GS_VERT_ITEMSIZE = 0x02d7 # macro
mmVGT_GS_VERT_ITEMSIZE_BASE_IDX = 1 # macro
mmVGT_GS_VERT_ITEMSIZE_1 = 0x02d8 # macro
mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX = 1 # macro
mmVGT_GS_VERT_ITEMSIZE_2 = 0x02d9 # macro
mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX = 1 # macro
mmVGT_GS_VERT_ITEMSIZE_3 = 0x02da # macro
mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX = 1 # macro
mmVGT_TF_PARAM = 0x02db # macro
mmVGT_TF_PARAM_BASE_IDX = 1 # macro
mmDB_ALPHA_TO_MASK = 0x02dc # macro
mmDB_ALPHA_TO_MASK_BASE_IDX = 1 # macro
mmVGT_DISPATCH_DRAW_INDEX = 0x02dd # macro
mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX = 1 # macro
mmPA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x02de # macro
mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX = 1 # macro
mmPA_SU_POLY_OFFSET_CLAMP = 0x02df # macro
mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX = 1 # macro
mmPA_SU_POLY_OFFSET_FRONT_SCALE = 0x02e0 # macro
mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX = 1 # macro
mmPA_SU_POLY_OFFSET_FRONT_OFFSET = 0x02e1 # macro
mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX = 1 # macro
mmPA_SU_POLY_OFFSET_BACK_SCALE = 0x02e2 # macro
mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX = 1 # macro
mmPA_SU_POLY_OFFSET_BACK_OFFSET = 0x02e3 # macro
mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX = 1 # macro
mmVGT_GS_INSTANCE_CNT = 0x02e4 # macro
mmVGT_GS_INSTANCE_CNT_BASE_IDX = 1 # macro
mmVGT_STRMOUT_CONFIG = 0x02e5 # macro
mmVGT_STRMOUT_CONFIG_BASE_IDX = 1 # macro
mmVGT_STRMOUT_BUFFER_CONFIG = 0x02e6 # macro
mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX = 1 # macro
mmVGT_DMA_EVENT_INITIATOR = 0x02e7 # macro
mmVGT_DMA_EVENT_INITIATOR_BASE_IDX = 1 # macro
mmPA_SC_CENTROID_PRIORITY_0 = 0x02f5 # macro
mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX = 1 # macro
mmPA_SC_CENTROID_PRIORITY_1 = 0x02f6 # macro
mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX = 1 # macro
mmPA_SC_LINE_CNTL = 0x02f7 # macro
mmPA_SC_LINE_CNTL_BASE_IDX = 1 # macro
mmPA_SC_AA_CONFIG = 0x02f8 # macro
mmPA_SC_AA_CONFIG_BASE_IDX = 1 # macro
mmPA_SU_VTX_CNTL = 0x02f9 # macro
mmPA_SU_VTX_CNTL_BASE_IDX = 1 # macro
mmPA_CL_GB_VERT_CLIP_ADJ = 0x02fa # macro
mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX = 1 # macro
mmPA_CL_GB_VERT_DISC_ADJ = 0x02fb # macro
mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX = 1 # macro
mmPA_CL_GB_HORZ_CLIP_ADJ = 0x02fc # macro
mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX = 1 # macro
mmPA_CL_GB_HORZ_DISC_ADJ = 0x02fd # macro
mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x02fe # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 = 0x02ff # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 = 0x0300 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 = 0x0301 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 = 0x0302 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 = 0x0303 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 = 0x0304 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 = 0x0305 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 = 0x0306 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 = 0x0307 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 = 0x0308 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 = 0x0309 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 = 0x030a # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 = 0x030b # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 = 0x030c # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX = 1 # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 = 0x030d # macro
mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX = 1 # macro
mmPA_SC_AA_MASK_X0Y0_X1Y0 = 0x030e # macro
mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX = 1 # macro
mmPA_SC_AA_MASK_X0Y1_X1Y1 = 0x030f # macro
mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX = 1 # macro
mmPA_SC_SHADER_CONTROL = 0x0310 # macro
mmPA_SC_SHADER_CONTROL_BASE_IDX = 1 # macro
mmPA_SC_BINNER_CNTL_0 = 0x0311 # macro
mmPA_SC_BINNER_CNTL_0_BASE_IDX = 1 # macro
mmPA_SC_BINNER_CNTL_1 = 0x0312 # macro
mmPA_SC_BINNER_CNTL_1_BASE_IDX = 1 # macro
mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x0313 # macro
mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX = 1 # macro
mmPA_SC_NGG_MODE_CNTL = 0x0314 # macro
mmPA_SC_NGG_MODE_CNTL_BASE_IDX = 1 # macro
mmVGT_VERTEX_REUSE_BLOCK_CNTL = 0x0316 # macro
mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX = 1 # macro
mmVGT_OUT_DEALLOC_CNTL = 0x0317 # macro
mmVGT_OUT_DEALLOC_CNTL_BASE_IDX = 1 # macro
mmCB_COLOR0_BASE = 0x0318 # macro
mmCB_COLOR0_BASE_BASE_IDX = 1 # macro
mmCB_COLOR0_PITCH = 0x0319 # macro
mmCB_COLOR0_PITCH_BASE_IDX = 1 # macro
mmCB_COLOR0_SLICE = 0x031a # macro
mmCB_COLOR0_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR0_VIEW = 0x031b # macro
mmCB_COLOR0_VIEW_BASE_IDX = 1 # macro
mmCB_COLOR0_INFO = 0x031c # macro
mmCB_COLOR0_INFO_BASE_IDX = 1 # macro
mmCB_COLOR0_ATTRIB = 0x031d # macro
mmCB_COLOR0_ATTRIB_BASE_IDX = 1 # macro
mmCB_COLOR0_DCC_CONTROL = 0x031e # macro
mmCB_COLOR0_DCC_CONTROL_BASE_IDX = 1 # macro
mmCB_COLOR0_CMASK = 0x031f # macro
mmCB_COLOR0_CMASK_BASE_IDX = 1 # macro
mmCB_COLOR0_CMASK_SLICE = 0x0320 # macro
mmCB_COLOR0_CMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR0_FMASK = 0x0321 # macro
mmCB_COLOR0_FMASK_BASE_IDX = 1 # macro
mmCB_COLOR0_FMASK_SLICE = 0x0322 # macro
mmCB_COLOR0_FMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR0_CLEAR_WORD0 = 0x0323 # macro
mmCB_COLOR0_CLEAR_WORD0_BASE_IDX = 1 # macro
mmCB_COLOR0_CLEAR_WORD1 = 0x0324 # macro
mmCB_COLOR0_CLEAR_WORD1_BASE_IDX = 1 # macro
mmCB_COLOR0_DCC_BASE = 0x0325 # macro
mmCB_COLOR0_DCC_BASE_BASE_IDX = 1 # macro
mmCB_COLOR1_BASE = 0x0327 # macro
mmCB_COLOR1_BASE_BASE_IDX = 1 # macro
mmCB_COLOR1_PITCH = 0x0328 # macro
mmCB_COLOR1_PITCH_BASE_IDX = 1 # macro
mmCB_COLOR1_SLICE = 0x0329 # macro
mmCB_COLOR1_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR1_VIEW = 0x032a # macro
mmCB_COLOR1_VIEW_BASE_IDX = 1 # macro
mmCB_COLOR1_INFO = 0x032b # macro
mmCB_COLOR1_INFO_BASE_IDX = 1 # macro
mmCB_COLOR1_ATTRIB = 0x032c # macro
mmCB_COLOR1_ATTRIB_BASE_IDX = 1 # macro
mmCB_COLOR1_DCC_CONTROL = 0x032d # macro
mmCB_COLOR1_DCC_CONTROL_BASE_IDX = 1 # macro
mmCB_COLOR1_CMASK = 0x032e # macro
mmCB_COLOR1_CMASK_BASE_IDX = 1 # macro
mmCB_COLOR1_CMASK_SLICE = 0x032f # macro
mmCB_COLOR1_CMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR1_FMASK = 0x0330 # macro
mmCB_COLOR1_FMASK_BASE_IDX = 1 # macro
mmCB_COLOR1_FMASK_SLICE = 0x0331 # macro
mmCB_COLOR1_FMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR1_CLEAR_WORD0 = 0x0332 # macro
mmCB_COLOR1_CLEAR_WORD0_BASE_IDX = 1 # macro
mmCB_COLOR1_CLEAR_WORD1 = 0x0333 # macro
mmCB_COLOR1_CLEAR_WORD1_BASE_IDX = 1 # macro
mmCB_COLOR1_DCC_BASE = 0x0334 # macro
mmCB_COLOR1_DCC_BASE_BASE_IDX = 1 # macro
mmCB_COLOR2_BASE = 0x0336 # macro
mmCB_COLOR2_BASE_BASE_IDX = 1 # macro
mmCB_COLOR2_PITCH = 0x0337 # macro
mmCB_COLOR2_PITCH_BASE_IDX = 1 # macro
mmCB_COLOR2_SLICE = 0x0338 # macro
mmCB_COLOR2_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR2_VIEW = 0x0339 # macro
mmCB_COLOR2_VIEW_BASE_IDX = 1 # macro
mmCB_COLOR2_INFO = 0x033a # macro
mmCB_COLOR2_INFO_BASE_IDX = 1 # macro
mmCB_COLOR2_ATTRIB = 0x033b # macro
mmCB_COLOR2_ATTRIB_BASE_IDX = 1 # macro
mmCB_COLOR2_DCC_CONTROL = 0x033c # macro
mmCB_COLOR2_DCC_CONTROL_BASE_IDX = 1 # macro
mmCB_COLOR2_CMASK = 0x033d # macro
mmCB_COLOR2_CMASK_BASE_IDX = 1 # macro
mmCB_COLOR2_CMASK_SLICE = 0x033e # macro
mmCB_COLOR2_CMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR2_FMASK = 0x033f # macro
mmCB_COLOR2_FMASK_BASE_IDX = 1 # macro
mmCB_COLOR2_FMASK_SLICE = 0x0340 # macro
mmCB_COLOR2_FMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR2_CLEAR_WORD0 = 0x0341 # macro
mmCB_COLOR2_CLEAR_WORD0_BASE_IDX = 1 # macro
mmCB_COLOR2_CLEAR_WORD1 = 0x0342 # macro
mmCB_COLOR2_CLEAR_WORD1_BASE_IDX = 1 # macro
mmCB_COLOR2_DCC_BASE = 0x0343 # macro
mmCB_COLOR2_DCC_BASE_BASE_IDX = 1 # macro
mmCB_COLOR3_BASE = 0x0345 # macro
mmCB_COLOR3_BASE_BASE_IDX = 1 # macro
mmCB_COLOR3_PITCH = 0x0346 # macro
mmCB_COLOR3_PITCH_BASE_IDX = 1 # macro
mmCB_COLOR3_SLICE = 0x0347 # macro
mmCB_COLOR3_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR3_VIEW = 0x0348 # macro
mmCB_COLOR3_VIEW_BASE_IDX = 1 # macro
mmCB_COLOR3_INFO = 0x0349 # macro
mmCB_COLOR3_INFO_BASE_IDX = 1 # macro
mmCB_COLOR3_ATTRIB = 0x034a # macro
mmCB_COLOR3_ATTRIB_BASE_IDX = 1 # macro
mmCB_COLOR3_DCC_CONTROL = 0x034b # macro
mmCB_COLOR3_DCC_CONTROL_BASE_IDX = 1 # macro
mmCB_COLOR3_CMASK = 0x034c # macro
mmCB_COLOR3_CMASK_BASE_IDX = 1 # macro
mmCB_COLOR3_CMASK_SLICE = 0x034d # macro
mmCB_COLOR3_CMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR3_FMASK = 0x034e # macro
mmCB_COLOR3_FMASK_BASE_IDX = 1 # macro
mmCB_COLOR3_FMASK_SLICE = 0x034f # macro
mmCB_COLOR3_FMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR3_CLEAR_WORD0 = 0x0350 # macro
mmCB_COLOR3_CLEAR_WORD0_BASE_IDX = 1 # macro
mmCB_COLOR3_CLEAR_WORD1 = 0x0351 # macro
mmCB_COLOR3_CLEAR_WORD1_BASE_IDX = 1 # macro
mmCB_COLOR3_DCC_BASE = 0x0352 # macro
mmCB_COLOR3_DCC_BASE_BASE_IDX = 1 # macro
mmCB_COLOR4_BASE = 0x0354 # macro
mmCB_COLOR4_BASE_BASE_IDX = 1 # macro
mmCB_COLOR4_PITCH = 0x0355 # macro
mmCB_COLOR4_PITCH_BASE_IDX = 1 # macro
mmCB_COLOR4_SLICE = 0x0356 # macro
mmCB_COLOR4_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR4_VIEW = 0x0357 # macro
mmCB_COLOR4_VIEW_BASE_IDX = 1 # macro
mmCB_COLOR4_INFO = 0x0358 # macro
mmCB_COLOR4_INFO_BASE_IDX = 1 # macro
mmCB_COLOR4_ATTRIB = 0x0359 # macro
mmCB_COLOR4_ATTRIB_BASE_IDX = 1 # macro
mmCB_COLOR4_DCC_CONTROL = 0x035a # macro
mmCB_COLOR4_DCC_CONTROL_BASE_IDX = 1 # macro
mmCB_COLOR4_CMASK = 0x035b # macro
mmCB_COLOR4_CMASK_BASE_IDX = 1 # macro
mmCB_COLOR4_CMASK_SLICE = 0x035c # macro
mmCB_COLOR4_CMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR4_FMASK = 0x035d # macro
mmCB_COLOR4_FMASK_BASE_IDX = 1 # macro
mmCB_COLOR4_FMASK_SLICE = 0x035e # macro
mmCB_COLOR4_FMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR4_CLEAR_WORD0 = 0x035f # macro
mmCB_COLOR4_CLEAR_WORD0_BASE_IDX = 1 # macro
mmCB_COLOR4_CLEAR_WORD1 = 0x0360 # macro
mmCB_COLOR4_CLEAR_WORD1_BASE_IDX = 1 # macro
mmCB_COLOR4_DCC_BASE = 0x0361 # macro
mmCB_COLOR4_DCC_BASE_BASE_IDX = 1 # macro
mmCB_COLOR5_BASE = 0x0363 # macro
mmCB_COLOR5_BASE_BASE_IDX = 1 # macro
mmCB_COLOR5_PITCH = 0x0364 # macro
mmCB_COLOR5_PITCH_BASE_IDX = 1 # macro
mmCB_COLOR5_SLICE = 0x0365 # macro
mmCB_COLOR5_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR5_VIEW = 0x0366 # macro
mmCB_COLOR5_VIEW_BASE_IDX = 1 # macro
mmCB_COLOR5_INFO = 0x0367 # macro
mmCB_COLOR5_INFO_BASE_IDX = 1 # macro
mmCB_COLOR5_ATTRIB = 0x0368 # macro
mmCB_COLOR5_ATTRIB_BASE_IDX = 1 # macro
mmCB_COLOR5_DCC_CONTROL = 0x0369 # macro
mmCB_COLOR5_DCC_CONTROL_BASE_IDX = 1 # macro
mmCB_COLOR5_CMASK = 0x036a # macro
mmCB_COLOR5_CMASK_BASE_IDX = 1 # macro
mmCB_COLOR5_CMASK_SLICE = 0x036b # macro
mmCB_COLOR5_CMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR5_FMASK = 0x036c # macro
mmCB_COLOR5_FMASK_BASE_IDX = 1 # macro
mmCB_COLOR5_FMASK_SLICE = 0x036d # macro
mmCB_COLOR5_FMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR5_CLEAR_WORD0 = 0x036e # macro
mmCB_COLOR5_CLEAR_WORD0_BASE_IDX = 1 # macro
mmCB_COLOR5_CLEAR_WORD1 = 0x036f # macro
mmCB_COLOR5_CLEAR_WORD1_BASE_IDX = 1 # macro
mmCB_COLOR5_DCC_BASE = 0x0370 # macro
mmCB_COLOR5_DCC_BASE_BASE_IDX = 1 # macro
mmCB_COLOR6_BASE = 0x0372 # macro
mmCB_COLOR6_BASE_BASE_IDX = 1 # macro
mmCB_COLOR6_PITCH = 0x0373 # macro
mmCB_COLOR6_PITCH_BASE_IDX = 1 # macro
mmCB_COLOR6_SLICE = 0x0374 # macro
mmCB_COLOR6_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR6_VIEW = 0x0375 # macro
mmCB_COLOR6_VIEW_BASE_IDX = 1 # macro
mmCB_COLOR6_INFO = 0x0376 # macro
mmCB_COLOR6_INFO_BASE_IDX = 1 # macro
mmCB_COLOR6_ATTRIB = 0x0377 # macro
mmCB_COLOR6_ATTRIB_BASE_IDX = 1 # macro
mmCB_COLOR6_DCC_CONTROL = 0x0378 # macro
mmCB_COLOR6_DCC_CONTROL_BASE_IDX = 1 # macro
mmCB_COLOR6_CMASK = 0x0379 # macro
mmCB_COLOR6_CMASK_BASE_IDX = 1 # macro
mmCB_COLOR6_CMASK_SLICE = 0x037a # macro
mmCB_COLOR6_CMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR6_FMASK = 0x037b # macro
mmCB_COLOR6_FMASK_BASE_IDX = 1 # macro
mmCB_COLOR6_FMASK_SLICE = 0x037c # macro
mmCB_COLOR6_FMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR6_CLEAR_WORD0 = 0x037d # macro
mmCB_COLOR6_CLEAR_WORD0_BASE_IDX = 1 # macro
mmCB_COLOR6_CLEAR_WORD1 = 0x037e # macro
mmCB_COLOR6_CLEAR_WORD1_BASE_IDX = 1 # macro
mmCB_COLOR6_DCC_BASE = 0x037f # macro
mmCB_COLOR6_DCC_BASE_BASE_IDX = 1 # macro
mmCB_COLOR7_BASE = 0x0381 # macro
mmCB_COLOR7_BASE_BASE_IDX = 1 # macro
mmCB_COLOR7_PITCH = 0x0382 # macro
mmCB_COLOR7_PITCH_BASE_IDX = 1 # macro
mmCB_COLOR7_SLICE = 0x0383 # macro
mmCB_COLOR7_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR7_VIEW = 0x0384 # macro
mmCB_COLOR7_VIEW_BASE_IDX = 1 # macro
mmCB_COLOR7_INFO = 0x0385 # macro
mmCB_COLOR7_INFO_BASE_IDX = 1 # macro
mmCB_COLOR7_ATTRIB = 0x0386 # macro
mmCB_COLOR7_ATTRIB_BASE_IDX = 1 # macro
mmCB_COLOR7_DCC_CONTROL = 0x0387 # macro
mmCB_COLOR7_DCC_CONTROL_BASE_IDX = 1 # macro
mmCB_COLOR7_CMASK = 0x0388 # macro
mmCB_COLOR7_CMASK_BASE_IDX = 1 # macro
mmCB_COLOR7_CMASK_SLICE = 0x0389 # macro
mmCB_COLOR7_CMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR7_FMASK = 0x038a # macro
mmCB_COLOR7_FMASK_BASE_IDX = 1 # macro
mmCB_COLOR7_FMASK_SLICE = 0x038b # macro
mmCB_COLOR7_FMASK_SLICE_BASE_IDX = 1 # macro
mmCB_COLOR7_CLEAR_WORD0 = 0x038c # macro
mmCB_COLOR7_CLEAR_WORD0_BASE_IDX = 1 # macro
mmCB_COLOR7_CLEAR_WORD1 = 0x038d # macro
mmCB_COLOR7_CLEAR_WORD1_BASE_IDX = 1 # macro
mmCB_COLOR7_DCC_BASE = 0x038e # macro
mmCB_COLOR7_DCC_BASE_BASE_IDX = 1 # macro
mmCB_COLOR0_BASE_EXT = 0x0390 # macro
mmCB_COLOR0_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR1_BASE_EXT = 0x0391 # macro
mmCB_COLOR1_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR2_BASE_EXT = 0x0392 # macro
mmCB_COLOR2_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR3_BASE_EXT = 0x0393 # macro
mmCB_COLOR3_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR4_BASE_EXT = 0x0394 # macro
mmCB_COLOR4_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR5_BASE_EXT = 0x0395 # macro
mmCB_COLOR5_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR6_BASE_EXT = 0x0396 # macro
mmCB_COLOR6_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR7_BASE_EXT = 0x0397 # macro
mmCB_COLOR7_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR0_CMASK_BASE_EXT = 0x0398 # macro
mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR1_CMASK_BASE_EXT = 0x0399 # macro
mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR2_CMASK_BASE_EXT = 0x039a # macro
mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR3_CMASK_BASE_EXT = 0x039b # macro
mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR4_CMASK_BASE_EXT = 0x039c # macro
mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR5_CMASK_BASE_EXT = 0x039d # macro
mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR6_CMASK_BASE_EXT = 0x039e # macro
mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR7_CMASK_BASE_EXT = 0x039f # macro
mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR0_FMASK_BASE_EXT = 0x03a0 # macro
mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR1_FMASK_BASE_EXT = 0x03a1 # macro
mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR2_FMASK_BASE_EXT = 0x03a2 # macro
mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR3_FMASK_BASE_EXT = 0x03a3 # macro
mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR4_FMASK_BASE_EXT = 0x03a4 # macro
mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR5_FMASK_BASE_EXT = 0x03a5 # macro
mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR6_FMASK_BASE_EXT = 0x03a6 # macro
mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR7_FMASK_BASE_EXT = 0x03a7 # macro
mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR0_DCC_BASE_EXT = 0x03a8 # macro
mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR1_DCC_BASE_EXT = 0x03a9 # macro
mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR2_DCC_BASE_EXT = 0x03aa # macro
mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR3_DCC_BASE_EXT = 0x03ab # macro
mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR4_DCC_BASE_EXT = 0x03ac # macro
mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR5_DCC_BASE_EXT = 0x03ad # macro
mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR6_DCC_BASE_EXT = 0x03ae # macro
mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR7_DCC_BASE_EXT = 0x03af # macro
mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX = 1 # macro
mmCB_COLOR0_ATTRIB2 = 0x03b0 # macro
mmCB_COLOR0_ATTRIB2_BASE_IDX = 1 # macro
mmCB_COLOR1_ATTRIB2 = 0x03b1 # macro
mmCB_COLOR1_ATTRIB2_BASE_IDX = 1 # macro
mmCB_COLOR2_ATTRIB2 = 0x03b2 # macro
mmCB_COLOR2_ATTRIB2_BASE_IDX = 1 # macro
mmCB_COLOR3_ATTRIB2 = 0x03b3 # macro
mmCB_COLOR3_ATTRIB2_BASE_IDX = 1 # macro
mmCB_COLOR4_ATTRIB2 = 0x03b4 # macro
mmCB_COLOR4_ATTRIB2_BASE_IDX = 1 # macro
mmCB_COLOR5_ATTRIB2 = 0x03b5 # macro
mmCB_COLOR5_ATTRIB2_BASE_IDX = 1 # macro
mmCB_COLOR6_ATTRIB2 = 0x03b6 # macro
mmCB_COLOR6_ATTRIB2_BASE_IDX = 1 # macro
mmCB_COLOR7_ATTRIB2 = 0x03b7 # macro
mmCB_COLOR7_ATTRIB2_BASE_IDX = 1 # macro
mmCB_COLOR0_ATTRIB3 = 0x03b8 # macro
mmCB_COLOR0_ATTRIB3_BASE_IDX = 1 # macro
mmCB_COLOR1_ATTRIB3 = 0x03b9 # macro
mmCB_COLOR1_ATTRIB3_BASE_IDX = 1 # macro
mmCB_COLOR2_ATTRIB3 = 0x03ba # macro
mmCB_COLOR2_ATTRIB3_BASE_IDX = 1 # macro
mmCB_COLOR3_ATTRIB3 = 0x03bb # macro
mmCB_COLOR3_ATTRIB3_BASE_IDX = 1 # macro
mmCB_COLOR4_ATTRIB3 = 0x03bc # macro
mmCB_COLOR4_ATTRIB3_BASE_IDX = 1 # macro
mmCB_COLOR5_ATTRIB3 = 0x03bd # macro
mmCB_COLOR5_ATTRIB3_BASE_IDX = 1 # macro
mmCB_COLOR6_ATTRIB3 = 0x03be # macro
mmCB_COLOR6_ATTRIB3_BASE_IDX = 1 # macro
mmCB_COLOR7_ATTRIB3 = 0x03bf # macro
mmCB_COLOR7_ATTRIB3_BASE_IDX = 1 # macro
mmCP_EOP_DONE_ADDR_LO = 0x2000 # macro
mmCP_EOP_DONE_ADDR_LO_BASE_IDX = 1 # macro
mmCP_EOP_DONE_ADDR_HI = 0x2001 # macro
mmCP_EOP_DONE_ADDR_HI_BASE_IDX = 1 # macro
mmCP_EOP_DONE_DATA_LO = 0x2002 # macro
mmCP_EOP_DONE_DATA_LO_BASE_IDX = 1 # macro
mmCP_EOP_DONE_DATA_HI = 0x2003 # macro
mmCP_EOP_DONE_DATA_HI_BASE_IDX = 1 # macro
mmCP_EOP_LAST_FENCE_LO = 0x2004 # macro
mmCP_EOP_LAST_FENCE_LO_BASE_IDX = 1 # macro
mmCP_EOP_LAST_FENCE_HI = 0x2005 # macro
mmCP_EOP_LAST_FENCE_HI_BASE_IDX = 1 # macro
mmCP_STREAM_OUT_ADDR_LO = 0x2006 # macro
mmCP_STREAM_OUT_ADDR_LO_BASE_IDX = 1 # macro
mmCP_STREAM_OUT_ADDR_HI = 0x2007 # macro
mmCP_STREAM_OUT_ADDR_HI_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT0_LO = 0x2008 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT0_HI = 0x2009 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_NEEDED_COUNT0_LO = 0x200a # macro
mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_NEEDED_COUNT0_HI = 0x200b # macro
mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT1_LO = 0x200c # macro
mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT1_HI = 0x200d # macro
mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_NEEDED_COUNT1_LO = 0x200e # macro
mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_NEEDED_COUNT1_HI = 0x200f # macro
mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT2_LO = 0x2010 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT2_HI = 0x2011 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_NEEDED_COUNT2_LO = 0x2012 # macro
mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_NEEDED_COUNT2_HI = 0x2013 # macro
mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT3_LO = 0x2014 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT3_HI = 0x2015 # macro
mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_NEEDED_COUNT3_LO = 0x2016 # macro
mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX = 1 # macro
mmCP_NUM_PRIM_NEEDED_COUNT3_HI = 0x2017 # macro
mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX = 1 # macro
mmCP_PIPE_STATS_ADDR_LO = 0x2018 # macro
mmCP_PIPE_STATS_ADDR_LO_BASE_IDX = 1 # macro
mmCP_PIPE_STATS_ADDR_HI = 0x2019 # macro
mmCP_PIPE_STATS_ADDR_HI_BASE_IDX = 1 # macro
mmCP_VGT_IAVERT_COUNT_LO = 0x201a # macro
mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX = 1 # macro
mmCP_VGT_IAVERT_COUNT_HI = 0x201b # macro
mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX = 1 # macro
mmCP_VGT_IAPRIM_COUNT_LO = 0x201c # macro
mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX = 1 # macro
mmCP_VGT_IAPRIM_COUNT_HI = 0x201d # macro
mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX = 1 # macro
mmCP_VGT_GSPRIM_COUNT_LO = 0x201e # macro
mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX = 1 # macro
mmCP_VGT_GSPRIM_COUNT_HI = 0x201f # macro
mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX = 1 # macro
mmCP_VGT_VSINVOC_COUNT_LO = 0x2020 # macro
mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX = 1 # macro
mmCP_VGT_VSINVOC_COUNT_HI = 0x2021 # macro
mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX = 1 # macro
mmCP_VGT_GSINVOC_COUNT_LO = 0x2022 # macro
mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX = 1 # macro
mmCP_VGT_GSINVOC_COUNT_HI = 0x2023 # macro
mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX = 1 # macro
mmCP_VGT_HSINVOC_COUNT_LO = 0x2024 # macro
mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX = 1 # macro
mmCP_VGT_HSINVOC_COUNT_HI = 0x2025 # macro
mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX = 1 # macro
mmCP_VGT_DSINVOC_COUNT_LO = 0x2026 # macro
mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX = 1 # macro
mmCP_VGT_DSINVOC_COUNT_HI = 0x2027 # macro
mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX = 1 # macro
mmCP_PA_CINVOC_COUNT_LO = 0x2028 # macro
mmCP_PA_CINVOC_COUNT_LO_BASE_IDX = 1 # macro
mmCP_PA_CINVOC_COUNT_HI = 0x2029 # macro
mmCP_PA_CINVOC_COUNT_HI_BASE_IDX = 1 # macro
mmCP_PA_CPRIM_COUNT_LO = 0x202a # macro
mmCP_PA_CPRIM_COUNT_LO_BASE_IDX = 1 # macro
mmCP_PA_CPRIM_COUNT_HI = 0x202b # macro
mmCP_PA_CPRIM_COUNT_HI_BASE_IDX = 1 # macro
mmCP_SC_PSINVOC_COUNT0_LO = 0x202c # macro
mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX = 1 # macro
mmCP_SC_PSINVOC_COUNT0_HI = 0x202d # macro
mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX = 1 # macro
mmCP_SC_PSINVOC_COUNT1_LO = 0x202e # macro
mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX = 1 # macro
mmCP_SC_PSINVOC_COUNT1_HI = 0x202f # macro
mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX = 1 # macro
mmCP_VGT_CSINVOC_COUNT_LO = 0x2030 # macro
mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX = 1 # macro
mmCP_VGT_CSINVOC_COUNT_HI = 0x2031 # macro
mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX = 1 # macro
mmCP_PIPE_STATS_CONTROL = 0x203d # macro
mmCP_PIPE_STATS_CONTROL_BASE_IDX = 1 # macro
mmCP_STREAM_OUT_CONTROL = 0x203e # macro
mmCP_STREAM_OUT_CONTROL_BASE_IDX = 1 # macro
mmCP_STRMOUT_CNTL = 0x203f # macro
mmCP_STRMOUT_CNTL_BASE_IDX = 1 # macro
mmSCRATCH_REG0 = 0x2040 # macro
mmSCRATCH_REG0_BASE_IDX = 1 # macro
mmSCRATCH_REG1 = 0x2041 # macro
mmSCRATCH_REG1_BASE_IDX = 1 # macro
mmSCRATCH_REG2 = 0x2042 # macro
mmSCRATCH_REG2_BASE_IDX = 1 # macro
mmSCRATCH_REG3 = 0x2043 # macro
mmSCRATCH_REG3_BASE_IDX = 1 # macro
mmSCRATCH_REG4 = 0x2044 # macro
mmSCRATCH_REG4_BASE_IDX = 1 # macro
mmSCRATCH_REG5 = 0x2045 # macro
mmSCRATCH_REG5_BASE_IDX = 1 # macro
mmSCRATCH_REG6 = 0x2046 # macro
mmSCRATCH_REG6_BASE_IDX = 1 # macro
mmSCRATCH_REG7 = 0x2047 # macro
mmSCRATCH_REG7_BASE_IDX = 1 # macro
mmSCRATCH_REG_ATOMIC = 0x2048 # macro
mmSCRATCH_REG_ATOMIC_BASE_IDX = 1 # macro
mmSCRATCH_REG_CMPSWAP_ATOMIC = 0x2048 # macro
mmSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX = 1 # macro
mmCP_APPEND_DDID_CNT = 0x204b # macro
mmCP_APPEND_DDID_CNT_BASE_IDX = 1 # macro
mmCP_APPEND_DATA_HI = 0x204c # macro
mmCP_APPEND_DATA_HI_BASE_IDX = 1 # macro
mmCP_APPEND_LAST_CS_FENCE_HI = 0x204d # macro
mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX = 1 # macro
mmCP_APPEND_LAST_PS_FENCE_HI = 0x204e # macro
mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX = 1 # macro
mmSCRATCH_UMSK = 0x2050 # macro
mmSCRATCH_UMSK_BASE_IDX = 1 # macro
mmSCRATCH_ADDR = 0x2051 # macro
mmSCRATCH_ADDR_BASE_IDX = 1 # macro
mmCP_PFP_ATOMIC_PREOP_LO = 0x2052 # macro
mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro
mmCP_PFP_ATOMIC_PREOP_HI = 0x2053 # macro
mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro
mmCP_PFP_GDS_ATOMIC0_PREOP_LO = 0x2054 # macro
mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro
mmCP_PFP_GDS_ATOMIC0_PREOP_HI = 0x2055 # macro
mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro
mmCP_PFP_GDS_ATOMIC1_PREOP_LO = 0x2056 # macro
mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro
mmCP_PFP_GDS_ATOMIC1_PREOP_HI = 0x2057 # macro
mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro
mmCP_APPEND_ADDR_LO = 0x2058 # macro
mmCP_APPEND_ADDR_LO_BASE_IDX = 1 # macro
mmCP_APPEND_ADDR_HI = 0x2059 # macro
mmCP_APPEND_ADDR_HI_BASE_IDX = 1 # macro
mmCP_APPEND_DATA = 0x205a # macro
mmCP_APPEND_DATA_BASE_IDX = 1 # macro
mmCP_APPEND_DATA_LO = 0x205a # macro
mmCP_APPEND_DATA_LO_BASE_IDX = 1 # macro
mmCP_APPEND_LAST_CS_FENCE = 0x205b # macro
mmCP_APPEND_LAST_CS_FENCE_BASE_IDX = 1 # macro
mmCP_APPEND_LAST_CS_FENCE_LO = 0x205b # macro
mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX = 1 # macro
mmCP_APPEND_LAST_PS_FENCE = 0x205c # macro
mmCP_APPEND_LAST_PS_FENCE_BASE_IDX = 1 # macro
mmCP_APPEND_LAST_PS_FENCE_LO = 0x205c # macro
mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX = 1 # macro
mmCP_ATOMIC_PREOP_LO = 0x205d # macro
mmCP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro
mmCP_ME_ATOMIC_PREOP_LO = 0x205d # macro
mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro
mmCP_ATOMIC_PREOP_HI = 0x205e # macro
mmCP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro
mmCP_ME_ATOMIC_PREOP_HI = 0x205e # macro
mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro
mmCP_GDS_ATOMIC0_PREOP_LO = 0x205f # macro
mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro
mmCP_ME_GDS_ATOMIC0_PREOP_LO = 0x205f # macro
mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro
mmCP_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro
mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro
mmCP_ME_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro
mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro
mmCP_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro
mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro
mmCP_ME_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro
mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro
mmCP_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro
mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro
mmCP_ME_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro
mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro
mmCP_ME_MC_WADDR_LO = 0x2069 # macro
mmCP_ME_MC_WADDR_LO_BASE_IDX = 1 # macro
mmCP_ME_MC_WADDR_HI = 0x206a # macro
mmCP_ME_MC_WADDR_HI_BASE_IDX = 1 # macro
mmCP_ME_MC_WDATA_LO = 0x206b # macro
mmCP_ME_MC_WDATA_LO_BASE_IDX = 1 # macro
mmCP_ME_MC_WDATA_HI = 0x206c # macro
mmCP_ME_MC_WDATA_HI_BASE_IDX = 1 # macro
mmCP_ME_MC_RADDR_LO = 0x206d # macro
mmCP_ME_MC_RADDR_LO_BASE_IDX = 1 # macro
mmCP_ME_MC_RADDR_HI = 0x206e # macro
mmCP_ME_MC_RADDR_HI_BASE_IDX = 1 # macro
mmCP_SEM_WAIT_TIMER = 0x206f # macro
mmCP_SEM_WAIT_TIMER_BASE_IDX = 1 # macro
mmCP_SIG_SEM_ADDR_LO = 0x2070 # macro
mmCP_SIG_SEM_ADDR_LO_BASE_IDX = 1 # macro
mmCP_SIG_SEM_ADDR_HI = 0x2071 # macro
mmCP_SIG_SEM_ADDR_HI_BASE_IDX = 1 # macro
mmCP_WAIT_REG_MEM_TIMEOUT = 0x2074 # macro
mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX = 1 # macro
mmCP_WAIT_SEM_ADDR_LO = 0x2075 # macro
mmCP_WAIT_SEM_ADDR_LO_BASE_IDX = 1 # macro
mmCP_WAIT_SEM_ADDR_HI = 0x2076 # macro
mmCP_WAIT_SEM_ADDR_HI_BASE_IDX = 1 # macro
mmCP_DMA_PFP_CONTROL = 0x2077 # macro
mmCP_DMA_PFP_CONTROL_BASE_IDX = 1 # macro
mmCP_DMA_ME_CONTROL = 0x2078 # macro
mmCP_DMA_ME_CONTROL_BASE_IDX = 1 # macro
mmCP_COHER_BASE_HI = 0x2079 # macro
mmCP_COHER_BASE_HI_BASE_IDX = 1 # macro
mmCP_COHER_START_DELAY = 0x207b # macro
mmCP_COHER_START_DELAY_BASE_IDX = 1 # macro
mmCP_COHER_CNTL = 0x207c # macro
mmCP_COHER_CNTL_BASE_IDX = 1 # macro
mmCP_COHER_SIZE = 0x207d # macro
mmCP_COHER_SIZE_BASE_IDX = 1 # macro
mmCP_COHER_BASE = 0x207e # macro
mmCP_COHER_BASE_BASE_IDX = 1 # macro
mmCP_COHER_STATUS = 0x207f # macro
mmCP_COHER_STATUS_BASE_IDX = 1 # macro
mmCP_DMA_ME_SRC_ADDR = 0x2080 # macro
mmCP_DMA_ME_SRC_ADDR_BASE_IDX = 1 # macro
mmCP_DMA_ME_SRC_ADDR_HI = 0x2081 # macro
mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX = 1 # macro
mmCP_DMA_ME_DST_ADDR = 0x2082 # macro
mmCP_DMA_ME_DST_ADDR_BASE_IDX = 1 # macro
mmCP_DMA_ME_DST_ADDR_HI = 0x2083 # macro
mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX = 1 # macro
mmCP_DMA_ME_COMMAND = 0x2084 # macro
mmCP_DMA_ME_COMMAND_BASE_IDX = 1 # macro
mmCP_DMA_PFP_SRC_ADDR = 0x2085 # macro
mmCP_DMA_PFP_SRC_ADDR_BASE_IDX = 1 # macro
mmCP_DMA_PFP_SRC_ADDR_HI = 0x2086 # macro
mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX = 1 # macro
mmCP_DMA_PFP_DST_ADDR = 0x2087 # macro
mmCP_DMA_PFP_DST_ADDR_BASE_IDX = 1 # macro
mmCP_DMA_PFP_DST_ADDR_HI = 0x2088 # macro
mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX = 1 # macro
mmCP_DMA_PFP_COMMAND = 0x2089 # macro
mmCP_DMA_PFP_COMMAND_BASE_IDX = 1 # macro
mmCP_DMA_CNTL = 0x208a # macro
mmCP_DMA_CNTL_BASE_IDX = 1 # macro
mmCP_DMA_READ_TAGS = 0x208b # macro
mmCP_DMA_READ_TAGS_BASE_IDX = 1 # macro
mmCP_COHER_SIZE_HI = 0x208c # macro
mmCP_COHER_SIZE_HI_BASE_IDX = 1 # macro
mmCP_PFP_IB_CONTROL = 0x208d # macro
mmCP_PFP_IB_CONTROL_BASE_IDX = 1 # macro
mmCP_PFP_LOAD_CONTROL = 0x208e # macro
mmCP_PFP_LOAD_CONTROL_BASE_IDX = 1 # macro
mmCP_SCRATCH_INDEX = 0x208f # macro
mmCP_SCRATCH_INDEX_BASE_IDX = 1 # macro
mmCP_SCRATCH_DATA = 0x2090 # macro
mmCP_SCRATCH_DATA_BASE_IDX = 1 # macro
mmCP_RB_OFFSET = 0x2091 # macro
mmCP_RB_OFFSET_BASE_IDX = 1 # macro
mmCP_IB2_OFFSET = 0x2093 # macro
mmCP_IB2_OFFSET_BASE_IDX = 1 # macro
mmCP_IB2_PREAMBLE_BEGIN = 0x2096 # macro
mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX = 1 # macro
mmCP_IB2_PREAMBLE_END = 0x2097 # macro
mmCP_IB2_PREAMBLE_END_BASE_IDX = 1 # macro
mmCP_CE_IB1_OFFSET = 0x2098 # macro
mmCP_CE_IB1_OFFSET_BASE_IDX = 1 # macro
mmCP_CE_IB2_OFFSET = 0x2099 # macro
mmCP_CE_IB2_OFFSET_BASE_IDX = 1 # macro
mmCP_CE_COUNTER = 0x209a # macro
mmCP_CE_COUNTER_BASE_IDX = 1 # macro
mmCP_DMA_ME_CMD_ADDR_LO = 0x209c # macro
mmCP_DMA_ME_CMD_ADDR_LO_BASE_IDX = 1 # macro
mmCP_DMA_ME_CMD_ADDR_HI = 0x209d # macro
mmCP_DMA_ME_CMD_ADDR_HI_BASE_IDX = 1 # macro
mmCP_DMA_PFP_CMD_ADDR_LO = 0x209e # macro
mmCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX = 1 # macro
mmCP_DMA_PFP_CMD_ADDR_HI = 0x209f # macro
mmCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX = 1 # macro
mmCP_APPEND_CMD_ADDR_LO = 0x20a0 # macro
mmCP_APPEND_CMD_ADDR_LO_BASE_IDX = 1 # macro
mmCP_APPEND_CMD_ADDR_HI = 0x20a1 # macro
mmCP_APPEND_CMD_ADDR_HI_BASE_IDX = 1 # macro
mmUCONFIG_RESERVED_REG0 = 0x20a2 # macro
mmUCONFIG_RESERVED_REG0_BASE_IDX = 1 # macro
mmUCONFIG_RESERVED_REG1 = 0x20a3 # macro
mmUCONFIG_RESERVED_REG1_BASE_IDX = 1 # macro
mmCP_CE_ATOMIC_PREOP_LO = 0x20a8 # macro
mmCP_CE_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro
mmCP_CE_ATOMIC_PREOP_HI = 0x20a9 # macro
mmCP_CE_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro
mmCP_CE_GDS_ATOMIC0_PREOP_LO = 0x20aa # macro
mmCP_CE_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro
mmCP_CE_GDS_ATOMIC0_PREOP_HI = 0x20ab # macro
mmCP_CE_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro
mmCP_CE_GDS_ATOMIC1_PREOP_LO = 0x20ac # macro
mmCP_CE_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro
mmCP_CE_GDS_ATOMIC1_PREOP_HI = 0x20ad # macro
mmCP_CE_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro
mmCP_CE_INIT_CMD_BUFSZ = 0x20bd # macro
mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX = 1 # macro
mmCP_CE_IB1_CMD_BUFSZ = 0x20be # macro
mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX = 1 # macro
mmCP_CE_IB2_CMD_BUFSZ = 0x20bf # macro
mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX = 1 # macro
mmCP_IB2_CMD_BUFSZ = 0x20c1 # macro
mmCP_IB2_CMD_BUFSZ_BASE_IDX = 1 # macro
mmCP_ST_CMD_BUFSZ = 0x20c2 # macro
mmCP_ST_CMD_BUFSZ_BASE_IDX = 1 # macro
mmCP_CE_INIT_BASE_LO = 0x20c3 # macro
mmCP_CE_INIT_BASE_LO_BASE_IDX = 1 # macro
mmCP_CE_INIT_BASE_HI = 0x20c4 # macro
mmCP_CE_INIT_BASE_HI_BASE_IDX = 1 # macro
mmCP_CE_INIT_BUFSZ = 0x20c5 # macro
mmCP_CE_INIT_BUFSZ_BASE_IDX = 1 # macro
mmCP_CE_IB1_BASE_LO = 0x20c6 # macro
mmCP_CE_IB1_BASE_LO_BASE_IDX = 1 # macro
mmCP_CE_IB1_BASE_HI = 0x20c7 # macro
mmCP_CE_IB1_BASE_HI_BASE_IDX = 1 # macro
mmCP_CE_IB1_BUFSZ = 0x20c8 # macro
mmCP_CE_IB1_BUFSZ_BASE_IDX = 1 # macro
mmCP_CE_IB2_BASE_LO = 0x20c9 # macro
mmCP_CE_IB2_BASE_LO_BASE_IDX = 1 # macro
mmCP_CE_IB2_BASE_HI = 0x20ca # macro
mmCP_CE_IB2_BASE_HI_BASE_IDX = 1 # macro
mmCP_CE_IB2_BUFSZ = 0x20cb # macro
mmCP_CE_IB2_BUFSZ_BASE_IDX = 1 # macro
mmCP_IB1_BASE_LO = 0x20cc # macro
mmCP_IB1_BASE_LO_BASE_IDX = 1 # macro
mmCP_IB1_BASE_HI = 0x20cd # macro
mmCP_IB1_BASE_HI_BASE_IDX = 1 # macro
mmCP_IB1_BUFSZ = 0x20ce # macro
mmCP_IB1_BUFSZ_BASE_IDX = 1 # macro
mmCP_IB2_BASE_LO = 0x20cf # macro
mmCP_IB2_BASE_LO_BASE_IDX = 1 # macro
mmCP_IB2_BASE_HI = 0x20d0 # macro
mmCP_IB2_BASE_HI_BASE_IDX = 1 # macro
mmCP_IB2_BUFSZ = 0x20d1 # macro
mmCP_IB2_BUFSZ_BASE_IDX = 1 # macro
mmCP_ST_BASE_LO = 0x20d2 # macro
mmCP_ST_BASE_LO_BASE_IDX = 1 # macro
mmCP_ST_BASE_HI = 0x20d3 # macro
mmCP_ST_BASE_HI_BASE_IDX = 1 # macro
mmCP_ST_BUFSZ = 0x20d4 # macro
mmCP_ST_BUFSZ_BASE_IDX = 1 # macro
mmCP_EOP_DONE_EVENT_CNTL = 0x20d5 # macro
mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX = 1 # macro
mmCP_EOP_DONE_DATA_CNTL = 0x20d6 # macro
mmCP_EOP_DONE_DATA_CNTL_BASE_IDX = 1 # macro
mmCP_EOP_DONE_CNTX_ID = 0x20d7 # macro
mmCP_EOP_DONE_CNTX_ID_BASE_IDX = 1 # macro
mmCP_DB_BASE_LO = 0x20d8 # macro
mmCP_DB_BASE_LO_BASE_IDX = 1 # macro
mmCP_DB_BASE_HI = 0x20d9 # macro
mmCP_DB_BASE_HI_BASE_IDX = 1 # macro
mmCP_DB_BUFSZ = 0x20da # macro
mmCP_DB_BUFSZ_BASE_IDX = 1 # macro
mmCP_DB_CMD_BUFSZ = 0x20db # macro
mmCP_DB_CMD_BUFSZ_BASE_IDX = 1 # macro
mmCP_CE_DB_BASE_LO = 0x20dc # macro
mmCP_CE_DB_BASE_LO_BASE_IDX = 1 # macro
mmCP_CE_DB_BASE_HI = 0x20dd # macro
mmCP_CE_DB_BASE_HI_BASE_IDX = 1 # macro
mmCP_CE_DB_BUFSZ = 0x20de # macro
mmCP_CE_DB_BUFSZ_BASE_IDX = 1 # macro
mmCP_CE_DB_CMD_BUFSZ = 0x20df # macro
mmCP_CE_DB_CMD_BUFSZ_BASE_IDX = 1 # macro
mmCP_PFP_COMPLETION_STATUS = 0x20ec # macro
mmCP_PFP_COMPLETION_STATUS_BASE_IDX = 1 # macro
mmCP_CE_COMPLETION_STATUS = 0x20ed # macro
mmCP_CE_COMPLETION_STATUS_BASE_IDX = 1 # macro
mmCP_PRED_NOT_VISIBLE = 0x20ee # macro
mmCP_PRED_NOT_VISIBLE_BASE_IDX = 1 # macro
mmCP_PFP_METADATA_BASE_ADDR = 0x20f0 # macro
mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX = 1 # macro
mmCP_PFP_METADATA_BASE_ADDR_HI = 0x20f1 # macro
mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX = 1 # macro
mmCP_CE_METADATA_BASE_ADDR = 0x20f2 # macro
mmCP_CE_METADATA_BASE_ADDR_BASE_IDX = 1 # macro
mmCP_CE_METADATA_BASE_ADDR_HI = 0x20f3 # macro
mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX = 1 # macro
mmCP_DRAW_INDX_INDR_ADDR = 0x20f4 # macro
mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX = 1 # macro
mmCP_DRAW_INDX_INDR_ADDR_HI = 0x20f5 # macro
mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX = 1 # macro
mmCP_DISPATCH_INDR_ADDR = 0x20f6 # macro
mmCP_DISPATCH_INDR_ADDR_BASE_IDX = 1 # macro
mmCP_DISPATCH_INDR_ADDR_HI = 0x20f7 # macro
mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX = 1 # macro
mmCP_INDEX_BASE_ADDR = 0x20f8 # macro
mmCP_INDEX_BASE_ADDR_BASE_IDX = 1 # macro
mmCP_INDEX_BASE_ADDR_HI = 0x20f9 # macro
mmCP_INDEX_BASE_ADDR_HI_BASE_IDX = 1 # macro
mmCP_INDEX_TYPE = 0x20fa # macro
mmCP_INDEX_TYPE_BASE_IDX = 1 # macro
mmCP_GDS_BKUP_ADDR = 0x20fb # macro
mmCP_GDS_BKUP_ADDR_BASE_IDX = 1 # macro
mmCP_GDS_BKUP_ADDR_HI = 0x20fc # macro
mmCP_GDS_BKUP_ADDR_HI_BASE_IDX = 1 # macro
mmCP_SAMPLE_STATUS = 0x20fd # macro
mmCP_SAMPLE_STATUS_BASE_IDX = 1 # macro
mmCP_ME_COHER_CNTL = 0x20fe # macro
mmCP_ME_COHER_CNTL_BASE_IDX = 1 # macro
mmCP_ME_COHER_SIZE = 0x20ff # macro
mmCP_ME_COHER_SIZE_BASE_IDX = 1 # macro
mmCP_ME_COHER_SIZE_HI = 0x2100 # macro
mmCP_ME_COHER_SIZE_HI_BASE_IDX = 1 # macro
mmCP_ME_COHER_BASE = 0x2101 # macro
mmCP_ME_COHER_BASE_BASE_IDX = 1 # macro
mmCP_ME_COHER_BASE_HI = 0x2102 # macro
mmCP_ME_COHER_BASE_HI_BASE_IDX = 1 # macro
mmCP_ME_COHER_STATUS = 0x2103 # macro
mmCP_ME_COHER_STATUS_BASE_IDX = 1 # macro
mmRLC_GPM_PERF_COUNT_0 = 0x2140 # macro
mmRLC_GPM_PERF_COUNT_0_BASE_IDX = 1 # macro
mmRLC_GPM_PERF_COUNT_1 = 0x2141 # macro
mmRLC_GPM_PERF_COUNT_1_BASE_IDX = 1 # macro
mmGRBM_GFX_INDEX = 0x2200 # macro
mmGRBM_GFX_INDEX_BASE_IDX = 1 # macro
mmVGT_ESGS_RING_SIZE_UMD = 0x2240 # macro
mmVGT_ESGS_RING_SIZE_UMD_BASE_IDX = 1 # macro
mmVGT_GSVS_RING_SIZE_UMD = 0x2241 # macro
mmVGT_GSVS_RING_SIZE_UMD_BASE_IDX = 1 # macro
mmVGT_PRIMITIVE_TYPE = 0x2242 # macro
mmVGT_PRIMITIVE_TYPE_BASE_IDX = 1 # macro
mmVGT_INDEX_TYPE = 0x2243 # macro
mmVGT_INDEX_TYPE_BASE_IDX = 1 # macro
mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x2244 # macro
mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX = 1 # macro
mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x2245 # macro
mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX = 1 # macro
mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x2246 # macro
mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX = 1 # macro
mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x2247 # macro
mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX = 1 # macro
mmGE_MIN_VTX_INDX = 0x2249 # macro
mmGE_MIN_VTX_INDX_BASE_IDX = 1 # macro
mmGE_INDX_OFFSET = 0x224a # macro
mmGE_INDX_OFFSET_BASE_IDX = 1 # macro
mmGE_MULTI_PRIM_IB_RESET_EN = 0x224b # macro
mmGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX = 1 # macro
mmVGT_NUM_INDICES = 0x224c # macro
mmVGT_NUM_INDICES_BASE_IDX = 1 # macro
mmVGT_NUM_INSTANCES = 0x224d # macro
mmVGT_NUM_INSTANCES_BASE_IDX = 1 # macro
mmVGT_TF_RING_SIZE_UMD = 0x224e # macro
mmVGT_TF_RING_SIZE_UMD_BASE_IDX = 1 # macro
mmVGT_HS_OFFCHIP_PARAM_UMD = 0x224f # macro
mmVGT_HS_OFFCHIP_PARAM_UMD_BASE_IDX = 1 # macro
mmVGT_TF_MEMORY_BASE_UMD = 0x2250 # macro
mmVGT_TF_MEMORY_BASE_UMD_BASE_IDX = 1 # macro
mmGE_DMA_FIRST_INDEX = 0x2251 # macro
mmGE_DMA_FIRST_INDEX_BASE_IDX = 1 # macro
mmWD_POS_BUF_BASE = 0x2252 # macro
mmWD_POS_BUF_BASE_BASE_IDX = 1 # macro
mmWD_POS_BUF_BASE_HI = 0x2253 # macro
mmWD_POS_BUF_BASE_HI_BASE_IDX = 1 # macro
mmWD_CNTL_SB_BUF_BASE = 0x2254 # macro
mmWD_CNTL_SB_BUF_BASE_BASE_IDX = 1 # macro
mmWD_CNTL_SB_BUF_BASE_HI = 0x2255 # macro
mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX = 1 # macro
mmWD_INDEX_BUF_BASE = 0x2256 # macro
mmWD_INDEX_BUF_BASE_BASE_IDX = 1 # macro
mmWD_INDEX_BUF_BASE_HI = 0x2257 # macro
mmWD_INDEX_BUF_BASE_HI_BASE_IDX = 1 # macro
mmIA_MULTI_VGT_PARAM_PIPED = 0x2258 # macro
mmIA_MULTI_VGT_PARAM_PIPED_BASE_IDX = 1 # macro
mmGE_MAX_VTX_INDX = 0x2259 # macro
mmGE_MAX_VTX_INDX_BASE_IDX = 1 # macro
mmVGT_INSTANCE_BASE_ID = 0x225a # macro
mmVGT_INSTANCE_BASE_ID_BASE_IDX = 1 # macro
mmGE_CNTL = 0x225b # macro
mmGE_CNTL_BASE_IDX = 1 # macro
mmGE_USER_VGPR1 = 0x225c # macro
mmGE_USER_VGPR1_BASE_IDX = 1 # macro
mmGE_USER_VGPR2 = 0x225d # macro
mmGE_USER_VGPR2_BASE_IDX = 1 # macro
mmGE_USER_VGPR3 = 0x225e # macro
mmGE_USER_VGPR3_BASE_IDX = 1 # macro
mmGE_STEREO_CNTL = 0x225f # macro
mmGE_STEREO_CNTL_BASE_IDX = 1 # macro
mmGE_PC_ALLOC = 0x2260 # macro
mmGE_PC_ALLOC_BASE_IDX = 1 # macro
mmVGT_TF_MEMORY_BASE_HI_UMD = 0x2261 # macro
mmVGT_TF_MEMORY_BASE_HI_UMD_BASE_IDX = 1 # macro
mmGE_USER_VGPR_EN = 0x2262 # macro
mmGE_USER_VGPR_EN_BASE_IDX = 1 # macro
mmPA_SU_LINE_STIPPLE_VALUE = 0x2280 # macro
mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX = 1 # macro
mmPA_SC_LINE_STIPPLE_STATE = 0x2281 # macro
mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX = 1 # macro
mmPA_SC_SCREEN_EXTENT_MIN_0 = 0x2284 # macro
mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX = 1 # macro
mmPA_SC_SCREEN_EXTENT_MAX_0 = 0x2285 # macro
mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX = 1 # macro
mmPA_SC_SCREEN_EXTENT_MIN_1 = 0x2286 # macro
mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX = 1 # macro
mmPA_SC_SCREEN_EXTENT_MAX_1 = 0x228b # macro
mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX = 1 # macro
mmPA_SC_P3D_TRAP_SCREEN_HV_EN = 0x22a0 # macro
mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro
mmPA_SC_P3D_TRAP_SCREEN_H = 0x22a1 # macro
mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro
mmPA_SC_P3D_TRAP_SCREEN_V = 0x22a2 # macro
mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro
mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE = 0x22a3 # macro
mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro
mmPA_SC_P3D_TRAP_SCREEN_COUNT = 0x22a4 # macro
mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro
mmPA_SC_HP3D_TRAP_SCREEN_HV_EN = 0x22a8 # macro
mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro
mmPA_SC_HP3D_TRAP_SCREEN_H = 0x22a9 # macro
mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro
mmPA_SC_HP3D_TRAP_SCREEN_V = 0x22aa # macro
mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro
mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE = 0x22ab # macro
mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro
mmPA_SC_HP3D_TRAP_SCREEN_COUNT = 0x22ac # macro
mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro
mmPA_SC_TRAP_SCREEN_HV_EN = 0x22b0 # macro
mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro
mmPA_SC_TRAP_SCREEN_H = 0x22b1 # macro
mmPA_SC_TRAP_SCREEN_H_BASE_IDX = 1 # macro
mmPA_SC_TRAP_SCREEN_V = 0x22b2 # macro
mmPA_SC_TRAP_SCREEN_V_BASE_IDX = 1 # macro
mmPA_SC_TRAP_SCREEN_OCCURRENCE = 0x22b3 # macro
mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro
mmPA_SC_TRAP_SCREEN_COUNT = 0x22b4 # macro
mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro
mmSQ_THREAD_TRACE_USERDATA_0 = 0x2340 # macro
mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX = 1 # macro
mmSQ_THREAD_TRACE_USERDATA_1 = 0x2341 # macro
mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX = 1 # macro
mmSQ_THREAD_TRACE_USERDATA_2 = 0x2342 # macro
mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX = 1 # macro
mmSQ_THREAD_TRACE_USERDATA_3 = 0x2343 # macro
mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX = 1 # macro
mmSQ_THREAD_TRACE_USERDATA_4 = 0x2344 # macro
mmSQ_THREAD_TRACE_USERDATA_4_BASE_IDX = 1 # macro
mmSQ_THREAD_TRACE_USERDATA_5 = 0x2345 # macro
mmSQ_THREAD_TRACE_USERDATA_5_BASE_IDX = 1 # macro
mmSQ_THREAD_TRACE_USERDATA_6 = 0x2346 # macro
mmSQ_THREAD_TRACE_USERDATA_6_BASE_IDX = 1 # macro
mmSQ_THREAD_TRACE_USERDATA_7 = 0x2347 # macro
mmSQ_THREAD_TRACE_USERDATA_7_BASE_IDX = 1 # macro
mmSQC_CACHES = 0x2348 # macro
mmSQC_CACHES_BASE_IDX = 1 # macro
mmTA_CS_BC_BASE_ADDR = 0x2380 # macro
mmTA_CS_BC_BASE_ADDR_BASE_IDX = 1 # macro
mmTA_CS_BC_BASE_ADDR_HI = 0x2381 # macro
mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro
mmDB_OCCLUSION_COUNT0_LOW = 0x23c0 # macro
mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX = 1 # macro
mmDB_OCCLUSION_COUNT0_HI = 0x23c1 # macro
mmDB_OCCLUSION_COUNT0_HI_BASE_IDX = 1 # macro
mmDB_OCCLUSION_COUNT1_LOW = 0x23c2 # macro
mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX = 1 # macro
mmDB_OCCLUSION_COUNT1_HI = 0x23c3 # macro
mmDB_OCCLUSION_COUNT1_HI_BASE_IDX = 1 # macro
mmDB_OCCLUSION_COUNT2_LOW = 0x23c4 # macro
mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX = 1 # macro
mmDB_OCCLUSION_COUNT2_HI = 0x23c5 # macro
mmDB_OCCLUSION_COUNT2_HI_BASE_IDX = 1 # macro
mmDB_OCCLUSION_COUNT3_LOW = 0x23c6 # macro
mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX = 1 # macro
mmDB_OCCLUSION_COUNT3_HI = 0x23c7 # macro
mmDB_OCCLUSION_COUNT3_HI_BASE_IDX = 1 # macro
mmDB_ZPASS_COUNT_LOW = 0x23fe # macro
mmDB_ZPASS_COUNT_LOW_BASE_IDX = 1 # macro
mmDB_ZPASS_COUNT_HI = 0x23ff # macro
mmDB_ZPASS_COUNT_HI_BASE_IDX = 1 # macro
mmGDS_RD_ADDR = 0x2400 # macro
mmGDS_RD_ADDR_BASE_IDX = 1 # macro
mmGDS_RD_DATA = 0x2401 # macro
mmGDS_RD_DATA_BASE_IDX = 1 # macro
mmGDS_RD_BURST_ADDR = 0x2402 # macro
mmGDS_RD_BURST_ADDR_BASE_IDX = 1 # macro
mmGDS_RD_BURST_COUNT = 0x2403 # macro
mmGDS_RD_BURST_COUNT_BASE_IDX = 1 # macro
mmGDS_RD_BURST_DATA = 0x2404 # macro
mmGDS_RD_BURST_DATA_BASE_IDX = 1 # macro
mmGDS_WR_ADDR = 0x2405 # macro
mmGDS_WR_ADDR_BASE_IDX = 1 # macro
mmGDS_WR_DATA = 0x2406 # macro
mmGDS_WR_DATA_BASE_IDX = 1 # macro
mmGDS_WR_BURST_ADDR = 0x2407 # macro
mmGDS_WR_BURST_ADDR_BASE_IDX = 1 # macro
mmGDS_WR_BURST_DATA = 0x2408 # macro
mmGDS_WR_BURST_DATA_BASE_IDX = 1 # macro
mmGDS_WRITE_COMPLETE = 0x2409 # macro
mmGDS_WRITE_COMPLETE_BASE_IDX = 1 # macro
mmGDS_ATOM_CNTL = 0x240a # macro
mmGDS_ATOM_CNTL_BASE_IDX = 1 # macro
mmGDS_ATOM_COMPLETE = 0x240b # macro
mmGDS_ATOM_COMPLETE_BASE_IDX = 1 # macro
mmGDS_ATOM_BASE = 0x240c # macro
mmGDS_ATOM_BASE_BASE_IDX = 1 # macro
mmGDS_ATOM_SIZE = 0x240d # macro
mmGDS_ATOM_SIZE_BASE_IDX = 1 # macro
mmGDS_ATOM_OFFSET0 = 0x240e # macro
mmGDS_ATOM_OFFSET0_BASE_IDX = 1 # macro
mmGDS_ATOM_OFFSET1 = 0x240f # macro
mmGDS_ATOM_OFFSET1_BASE_IDX = 1 # macro
mmGDS_ATOM_DST = 0x2410 # macro
mmGDS_ATOM_DST_BASE_IDX = 1 # macro
mmGDS_ATOM_OP = 0x2411 # macro
mmGDS_ATOM_OP_BASE_IDX = 1 # macro
mmGDS_ATOM_SRC0 = 0x2412 # macro
mmGDS_ATOM_SRC0_BASE_IDX = 1 # macro
mmGDS_ATOM_SRC0_U = 0x2413 # macro
mmGDS_ATOM_SRC0_U_BASE_IDX = 1 # macro
mmGDS_ATOM_SRC1 = 0x2414 # macro
mmGDS_ATOM_SRC1_BASE_IDX = 1 # macro
mmGDS_ATOM_SRC1_U = 0x2415 # macro
mmGDS_ATOM_SRC1_U_BASE_IDX = 1 # macro
mmGDS_ATOM_READ0 = 0x2416 # macro
mmGDS_ATOM_READ0_BASE_IDX = 1 # macro
mmGDS_ATOM_READ0_U = 0x2417 # macro
mmGDS_ATOM_READ0_U_BASE_IDX = 1 # macro
mmGDS_ATOM_READ1 = 0x2418 # macro
mmGDS_ATOM_READ1_BASE_IDX = 1 # macro
mmGDS_ATOM_READ1_U = 0x2419 # macro
mmGDS_ATOM_READ1_U_BASE_IDX = 1 # macro
mmGDS_GWS_RESOURCE_CNTL = 0x241a # macro
mmGDS_GWS_RESOURCE_CNTL_BASE_IDX = 1 # macro
mmGDS_GWS_RESOURCE = 0x241b # macro
mmGDS_GWS_RESOURCE_BASE_IDX = 1 # macro
mmGDS_GWS_RESOURCE_CNT = 0x241c # macro
mmGDS_GWS_RESOURCE_CNT_BASE_IDX = 1 # macro
mmGDS_OA_CNTL = 0x241d # macro
mmGDS_OA_CNTL_BASE_IDX = 1 # macro
mmGDS_OA_COUNTER = 0x241e # macro
mmGDS_OA_COUNTER_BASE_IDX = 1 # macro
mmGDS_OA_ADDRESS = 0x241f # macro
mmGDS_OA_ADDRESS_BASE_IDX = 1 # macro
mmGDS_OA_INCDEC = 0x2420 # macro
mmGDS_OA_INCDEC_BASE_IDX = 1 # macro
mmGDS_OA_RING_SIZE = 0x2421 # macro
mmGDS_OA_RING_SIZE_BASE_IDX = 1 # macro
mmSPI_CONFIG_CNTL_REMAP = 0x2440 # macro
mmSPI_CONFIG_CNTL_REMAP_BASE_IDX = 1 # macro
mmSPI_CONFIG_CNTL_1_REMAP = 0x2441 # macro
mmSPI_CONFIG_CNTL_1_REMAP_BASE_IDX = 1 # macro
mmSPI_CONFIG_CNTL_2_REMAP = 0x2442 # macro
mmSPI_CONFIG_CNTL_2_REMAP_BASE_IDX = 1 # macro
mmSPI_WAVE_LIMIT_CNTL_REMAP = 0x2443 # macro
mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX = 1 # macro
mmCP_MES_PRGRM_CNTR_START = 0x2800 # macro
mmCP_MES_PRGRM_CNTR_START_BASE_IDX = 1 # macro
mmCP_MES_INTR_ROUTINE_START = 0x2801 # macro
mmCP_MES_INTR_ROUTINE_START_BASE_IDX = 1 # macro
mmCP_MES_MTVEC_LO = 0x2801 # macro
mmCP_MES_MTVEC_LO_BASE_IDX = 1 # macro
mmCP_MES_MTVEC_HI = 0x2802 # macro
mmCP_MES_MTVEC_HI_BASE_IDX = 1 # macro
mmCP_MES_CNTL = 0x2807 # macro
mmCP_MES_CNTL_BASE_IDX = 1 # macro
mmCP_MES_PIPE_PRIORITY_CNTS = 0x2808 # macro
mmCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX = 1 # macro
mmCP_MES_PIPE0_PRIORITY = 0x2809 # macro
mmCP_MES_PIPE0_PRIORITY_BASE_IDX = 1 # macro
mmCP_MES_PIPE1_PRIORITY = 0x280a # macro
mmCP_MES_PIPE1_PRIORITY_BASE_IDX = 1 # macro
mmCP_MES_PIPE2_PRIORITY = 0x280b # macro
mmCP_MES_PIPE2_PRIORITY_BASE_IDX = 1 # macro
mmCP_MES_PIPE3_PRIORITY = 0x280c # macro
mmCP_MES_PIPE3_PRIORITY_BASE_IDX = 1 # macro
mmCP_MES_HEADER_DUMP = 0x280d # macro
mmCP_MES_HEADER_DUMP_BASE_IDX = 1 # macro
mmCP_MES_MIE_LO = 0x280e # macro
mmCP_MES_MIE_LO_BASE_IDX = 1 # macro
mmCP_MES_MIE_HI = 0x280f # macro
mmCP_MES_MIE_HI_BASE_IDX = 1 # macro
mmCP_MES_INTERRUPT = 0x2810 # macro
mmCP_MES_INTERRUPT_BASE_IDX = 1 # macro
mmCP_MES_SCRATCH_INDEX = 0x2811 # macro
mmCP_MES_SCRATCH_INDEX_BASE_IDX = 1 # macro
mmCP_MES_SCRATCH_DATA = 0x2812 # macro
mmCP_MES_SCRATCH_DATA_BASE_IDX = 1 # macro
mmCP_MES_INSTR_PNTR = 0x2813 # macro
mmCP_MES_INSTR_PNTR_BASE_IDX = 1 # macro
mmCP_MES_MSCRATCH_HI = 0x2814 # macro
mmCP_MES_MSCRATCH_HI_BASE_IDX = 1 # macro
mmCP_MES_MSCRATCH_LO = 0x2815 # macro
mmCP_MES_MSCRATCH_LO_BASE_IDX = 1 # macro
mmCP_MES_MSTATUS_LO = 0x2816 # macro
mmCP_MES_MSTATUS_LO_BASE_IDX = 1 # macro
mmCP_MES_MSTATUS_HI = 0x2817 # macro
mmCP_MES_MSTATUS_HI_BASE_IDX = 1 # macro
mmCP_MES_MEPC_LO = 0x2818 # macro
mmCP_MES_MEPC_LO_BASE_IDX = 1 # macro
mmCP_MES_MEPC_HI = 0x2819 # macro
mmCP_MES_MEPC_HI_BASE_IDX = 1 # macro
mmCP_MES_MCAUSE_LO = 0x281a # macro
mmCP_MES_MCAUSE_LO_BASE_IDX = 1 # macro
mmCP_MES_MCAUSE_HI = 0x281b # macro
mmCP_MES_MCAUSE_HI_BASE_IDX = 1 # macro
mmCP_MES_MBADADDR_LO = 0x281c # macro
mmCP_MES_MBADADDR_LO_BASE_IDX = 1 # macro
mmCP_MES_MBADADDR_HI = 0x281d # macro
mmCP_MES_MBADADDR_HI_BASE_IDX = 1 # macro
mmCP_MES_MIP_LO = 0x281e # macro
mmCP_MES_MIP_LO_BASE_IDX = 1 # macro
mmCP_MES_MIP_HI = 0x281f # macro
mmCP_MES_MIP_HI_BASE_IDX = 1 # macro
mmCP_MES_IC_OP_CNTL = 0x2820 # macro
mmCP_MES_IC_OP_CNTL_BASE_IDX = 1 # macro
mmCP_MES_MCYCLE_LO = 0x2826 # macro
mmCP_MES_MCYCLE_LO_BASE_IDX = 1 # macro
mmCP_MES_MCYCLE_HI = 0x2827 # macro
mmCP_MES_MCYCLE_HI_BASE_IDX = 1 # macro
mmCP_MES_MTIME_LO = 0x2828 # macro
mmCP_MES_MTIME_LO_BASE_IDX = 1 # macro
mmCP_MES_MTIME_HI = 0x2829 # macro
mmCP_MES_MTIME_HI_BASE_IDX = 1 # macro
mmCP_MES_MINSTRET_LO = 0x282a # macro
mmCP_MES_MINSTRET_LO_BASE_IDX = 1 # macro
mmCP_MES_MINSTRET_HI = 0x282b # macro
mmCP_MES_MINSTRET_HI_BASE_IDX = 1 # macro
mmCP_MES_MISA_LO = 0x282c # macro
mmCP_MES_MISA_LO_BASE_IDX = 1 # macro
mmCP_MES_MISA_HI = 0x282d # macro
mmCP_MES_MISA_HI_BASE_IDX = 1 # macro
mmCP_MES_MVENDORID_LO = 0x282e # macro
mmCP_MES_MVENDORID_LO_BASE_IDX = 1 # macro
mmCP_MES_MVENDORID_HI = 0x282f # macro
mmCP_MES_MVENDORID_HI_BASE_IDX = 1 # macro
mmCP_MES_MARCHID_LO = 0x2830 # macro
mmCP_MES_MARCHID_LO_BASE_IDX = 1 # macro
mmCP_MES_MARCHID_HI = 0x2831 # macro
mmCP_MES_MARCHID_HI_BASE_IDX = 1 # macro
mmCP_MES_MIMPID_LO = 0x2832 # macro
mmCP_MES_MIMPID_LO_BASE_IDX = 1 # macro
mmCP_MES_MIMPID_HI = 0x2833 # macro
mmCP_MES_MIMPID_HI_BASE_IDX = 1 # macro
mmCP_MES_MHARTID_LO = 0x2834 # macro
mmCP_MES_MHARTID_LO_BASE_IDX = 1 # macro
mmCP_MES_MHARTID_HI = 0x2835 # macro
mmCP_MES_MHARTID_HI_BASE_IDX = 1 # macro
mmCP_MES_DC_BASE_CNTL = 0x2836 # macro
mmCP_MES_DC_BASE_CNTL_BASE_IDX = 1 # macro
mmCP_MES_DC_OP_CNTL = 0x2837 # macro
mmCP_MES_DC_OP_CNTL_BASE_IDX = 1 # macro
mmCP_MES_MTIMECMP_LO = 0x2838 # macro
mmCP_MES_MTIMECMP_LO_BASE_IDX = 1 # macro
mmCP_MES_MTIMECMP_HI = 0x2839 # macro
mmCP_MES_MTIMECMP_HI_BASE_IDX = 1 # macro
mmCP_MES_PROCESS_QUANTUM_PIPE0 = 0x283a # macro
mmCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX = 1 # macro
mmCP_MES_PROCESS_QUANTUM_PIPE1 = 0x283b # macro
mmCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX = 1 # macro
mmCP_MES_DOORBELL_CONTROL1 = 0x283c # macro
mmCP_MES_DOORBELL_CONTROL1_BASE_IDX = 1 # macro
mmCP_MES_DOORBELL_CONTROL2 = 0x283d # macro
mmCP_MES_DOORBELL_CONTROL2_BASE_IDX = 1 # macro
mmCP_MES_DOORBELL_CONTROL3 = 0x283e # macro
mmCP_MES_DOORBELL_CONTROL3_BASE_IDX = 1 # macro
mmCP_MES_DOORBELL_CONTROL4 = 0x283f # macro
mmCP_MES_DOORBELL_CONTROL4_BASE_IDX = 1 # macro
mmCP_MES_DOORBELL_CONTROL5 = 0x2840 # macro
mmCP_MES_DOORBELL_CONTROL5_BASE_IDX = 1 # macro
mmCP_MES_DOORBELL_CONTROL6 = 0x2841 # macro
mmCP_MES_DOORBELL_CONTROL6_BASE_IDX = 1 # macro
mmCP_MES_GP0_LO = 0x2843 # macro
mmCP_MES_GP0_LO_BASE_IDX = 1 # macro
mmCP_MES_GP0_HI = 0x2844 # macro
mmCP_MES_GP0_HI_BASE_IDX = 1 # macro
mmCP_MES_GP1_LO = 0x2845 # macro
mmCP_MES_GP1_LO_BASE_IDX = 1 # macro
mmCP_MES_GP1_HI = 0x2846 # macro
mmCP_MES_GP1_HI_BASE_IDX = 1 # macro
mmCP_MES_GP2_LO = 0x2847 # macro
mmCP_MES_GP2_LO_BASE_IDX = 1 # macro
mmCP_MES_GP2_HI = 0x2848 # macro
mmCP_MES_GP2_HI_BASE_IDX = 1 # macro
mmCP_MES_GP3_LO = 0x2849 # macro
mmCP_MES_GP3_LO_BASE_IDX = 1 # macro
mmCP_MES_GP3_HI = 0x284a # macro
mmCP_MES_GP3_HI_BASE_IDX = 1 # macro
mmCP_MES_GP4_LO = 0x284b # macro
mmCP_MES_GP4_LO_BASE_IDX = 1 # macro
mmCP_MES_GP4_HI = 0x284c # macro
mmCP_MES_GP4_HI_BASE_IDX = 1 # macro
mmCP_MES_GP5_LO = 0x284d # macro
mmCP_MES_GP5_LO_BASE_IDX = 1 # macro
mmCP_MES_GP5_HI = 0x284e # macro
mmCP_MES_GP5_HI_BASE_IDX = 1 # macro
mmCP_MES_GP6_LO = 0x284f # macro
mmCP_MES_GP6_LO_BASE_IDX = 1 # macro
mmCP_MES_GP6_HI = 0x2850 # macro
mmCP_MES_GP6_HI_BASE_IDX = 1 # macro
mmCP_MES_GP7_LO = 0x2851 # macro
mmCP_MES_GP7_LO_BASE_IDX = 1 # macro
mmCP_MES_GP7_HI = 0x2852 # macro
mmCP_MES_GP7_HI_BASE_IDX = 1 # macro
mmCP_MES_GP8_LO = 0x2853 # macro
mmCP_MES_GP8_LO_BASE_IDX = 1 # macro
mmCP_MES_GP8_HI = 0x2854 # macro
mmCP_MES_GP8_HI_BASE_IDX = 1 # macro
mmCP_MES_GP9_LO = 0x2855 # macro
mmCP_MES_GP9_LO_BASE_IDX = 1 # macro
mmCP_MES_GP9_HI = 0x2856 # macro
mmCP_MES_GP9_HI_BASE_IDX = 1 # macro
mmCP_MES_DM_INDEX_ADDR = 0x2880 # macro
mmCP_MES_DM_INDEX_ADDR_BASE_IDX = 1 # macro
mmCP_MES_DM_INDEX_DATA = 0x2881 # macro
mmCP_MES_DM_INDEX_DATA_BASE_IDX = 1 # macro
mmCP_MES_PERFCOUNT_CNTL = 0x2899 # macro
mmCP_MES_PERFCOUNT_CNTL_BASE_IDX = 1 # macro
mmCP_MES_PENDING_INTERRUPT = 0x289a # macro
mmCP_MES_PENDING_INTERRUPT_BASE_IDX = 1 # macro
mmGUS_IO_RD_COMBINE_FLUSH = 0x2c00 # macro
mmGUS_IO_RD_COMBINE_FLUSH_BASE_IDX = 1 # macro
mmGUS_IO_WR_COMBINE_FLUSH = 0x2c01 # macro
mmGUS_IO_WR_COMBINE_FLUSH_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_AGE_RATE = 0x2c02 # macro
mmGUS_IO_RD_PRI_AGE_RATE_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_AGE_RATE = 0x2c03 # macro
mmGUS_IO_WR_PRI_AGE_RATE_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_AGE_COEFF = 0x2c04 # macro
mmGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_AGE_COEFF = 0x2c05 # macro
mmGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_QUEUING = 0x2c06 # macro
mmGUS_IO_RD_PRI_QUEUING_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_QUEUING = 0x2c07 # macro
mmGUS_IO_WR_PRI_QUEUING_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_FIXED = 0x2c08 # macro
mmGUS_IO_RD_PRI_FIXED_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_FIXED = 0x2c09 # macro
mmGUS_IO_WR_PRI_FIXED_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_URGENCY_COEFF = 0x2c0a # macro
mmGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_URGENCY_COEFF = 0x2c0b # macro
mmGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_URGENCY_MODE = 0x2c0c # macro
mmGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_URGENCY_MODE = 0x2c0d # macro
mmGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_QUANT_PRI1 = 0x2c0e # macro
mmGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_QUANT_PRI2 = 0x2c0f # macro
mmGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_QUANT_PRI3 = 0x2c10 # macro
mmGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_QUANT_PRI4 = 0x2c11 # macro
mmGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_QUANT_PRI1 = 0x2c12 # macro
mmGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_QUANT_PRI2 = 0x2c13 # macro
mmGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_QUANT_PRI3 = 0x2c14 # macro
mmGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_QUANT_PRI4 = 0x2c15 # macro
mmGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_QUANT1_PRI1 = 0x2c16 # macro
mmGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_QUANT1_PRI2 = 0x2c17 # macro
mmGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_QUANT1_PRI3 = 0x2c18 # macro
mmGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro
mmGUS_IO_RD_PRI_QUANT1_PRI4 = 0x2c19 # macro
mmGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_QUANT1_PRI1 = 0x2c1a # macro
mmGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_QUANT1_PRI2 = 0x2c1b # macro
mmGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_QUANT1_PRI3 = 0x2c1c # macro
mmGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro
mmGUS_IO_WR_PRI_QUANT1_PRI4 = 0x2c1d # macro
mmGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro
mmGUS_DRAM_COMBINE_FLUSH = 0x2c1e # macro
mmGUS_DRAM_COMBINE_FLUSH_BASE_IDX = 1 # macro
mmGUS_DRAM_COMBINE_RD_WR_EN = 0x2c1f # macro
mmGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_AGE_RATE = 0x2c20 # macro
mmGUS_DRAM_PRI_AGE_RATE_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_AGE_COEFF = 0x2c21 # macro
mmGUS_DRAM_PRI_AGE_COEFF_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_QUEUING = 0x2c22 # macro
mmGUS_DRAM_PRI_QUEUING_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_FIXED = 0x2c23 # macro
mmGUS_DRAM_PRI_FIXED_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_URGENCY_COEFF = 0x2c24 # macro
mmGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_URGENCY_MODE = 0x2c25 # macro
mmGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_QUANT_PRI1 = 0x2c26 # macro
mmGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_QUANT_PRI2 = 0x2c27 # macro
mmGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_QUANT_PRI3 = 0x2c28 # macro
mmGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_QUANT_PRI4 = 0x2c29 # macro
mmGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_QUANT_PRI5 = 0x2c2a # macro
mmGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_QUANT1_PRI1 = 0x2c2b # macro
mmGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_QUANT1_PRI2 = 0x2c2c # macro
mmGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_QUANT1_PRI3 = 0x2c2d # macro
mmGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_QUANT1_PRI4 = 0x2c2e # macro
mmGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro
mmGUS_DRAM_PRI_QUANT1_PRI5 = 0x2c2f # macro
mmGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX = 1 # macro
mmGUS_IO_GROUP_BURST = 0x2c30 # macro
mmGUS_IO_GROUP_BURST_BASE_IDX = 1 # macro
mmGUS_DRAM_GROUP_BURST = 0x2c31 # macro
mmGUS_DRAM_GROUP_BURST_BASE_IDX = 1 # macro
mmGUS_SDP_ARB_FINAL = 0x2c32 # macro
mmGUS_SDP_ARB_FINAL_BASE_IDX = 1 # macro
mmGUS_SDP_QOS_VC_PRIORITY = 0x2c33 # macro
mmGUS_SDP_QOS_VC_PRIORITY_BASE_IDX = 1 # macro
mmGUS_SDP_CREDITS = 0x2c34 # macro
mmGUS_SDP_CREDITS_BASE_IDX = 1 # macro
mmGUS_SDP_TAG_RESERVE0 = 0x2c35 # macro
mmGUS_SDP_TAG_RESERVE0_BASE_IDX = 1 # macro
mmGUS_SDP_TAG_RESERVE1 = 0x2c36 # macro
mmGUS_SDP_TAG_RESERVE1_BASE_IDX = 1 # macro
mmGUS_SDP_VCC_RESERVE0 = 0x2c37 # macro
mmGUS_SDP_VCC_RESERVE0_BASE_IDX = 1 # macro
mmGUS_SDP_VCC_RESERVE1 = 0x2c38 # macro
mmGUS_SDP_VCC_RESERVE1_BASE_IDX = 1 # macro
mmGUS_SDP_VCD_RESERVE0 = 0x2c39 # macro
mmGUS_SDP_VCD_RESERVE0_BASE_IDX = 1 # macro
mmGUS_SDP_VCD_RESERVE1 = 0x2c3a # macro
mmGUS_SDP_VCD_RESERVE1_BASE_IDX = 1 # macro
mmGUS_SDP_REQ_CNTL = 0x2c3b # macro
mmGUS_SDP_REQ_CNTL_BASE_IDX = 1 # macro
mmGUS_MISC = 0x2c3c # macro
mmGUS_MISC_BASE_IDX = 1 # macro
mmGUS_LATENCY_SAMPLING = 0x2c3d # macro
mmGUS_LATENCY_SAMPLING_BASE_IDX = 1 # macro
mmGUS_ERR_STATUS = 0x2c3e # macro
mmGUS_ERR_STATUS_BASE_IDX = 1 # macro
mmGUS_MISC2 = 0x2c3f # macro
mmGUS_MISC2_BASE_IDX = 1 # macro
mmGUS_SDP_ENABLE = 0x2c45 # macro
mmGUS_SDP_ENABLE_BASE_IDX = 1 # macro
mmGUS_L1_CH0_CMD_IN = 0x2c46 # macro
mmGUS_L1_CH0_CMD_IN_BASE_IDX = 1 # macro
mmGUS_L1_CH0_CMD_OUT = 0x2c47 # macro
mmGUS_L1_CH0_CMD_OUT_BASE_IDX = 1 # macro
mmGUS_L1_CH0_DATA_IN = 0x2c48 # macro
mmGUS_L1_CH0_DATA_IN_BASE_IDX = 1 # macro
mmGUS_L1_CH0_DATA_OUT = 0x2c49 # macro
mmGUS_L1_CH0_DATA_OUT_BASE_IDX = 1 # macro
mmGUS_L1_CH0_DATA_U_IN = 0x2c4a # macro
mmGUS_L1_CH0_DATA_U_IN_BASE_IDX = 1 # macro
mmGUS_L1_CH0_DATA_U_OUT = 0x2c4b # macro
mmGUS_L1_CH0_DATA_U_OUT_BASE_IDX = 1 # macro
mmGUS_L1_CH1_CMD_IN = 0x2c4c # macro
mmGUS_L1_CH1_CMD_IN_BASE_IDX = 1 # macro
mmGUS_L1_CH1_CMD_OUT = 0x2c4d # macro
mmGUS_L1_CH1_CMD_OUT_BASE_IDX = 1 # macro
mmGUS_L1_CH1_DATA_IN = 0x2c4e # macro
mmGUS_L1_CH1_DATA_IN_BASE_IDX = 1 # macro
mmGUS_L1_CH1_DATA_OUT = 0x2c4f # macro
mmGUS_L1_CH1_DATA_OUT_BASE_IDX = 1 # macro
mmGUS_L1_CH1_DATA_U_IN = 0x2c50 # macro
mmGUS_L1_CH1_DATA_U_IN_BASE_IDX = 1 # macro
mmGUS_L1_CH1_DATA_U_OUT = 0x2c51 # macro
mmGUS_L1_CH1_DATA_U_OUT_BASE_IDX = 1 # macro
mmGUS_L1_SA0_CMD_IN = 0x2c52 # macro
mmGUS_L1_SA0_CMD_IN_BASE_IDX = 1 # macro
mmGUS_L1_SA0_CMD_OUT = 0x2c53 # macro
mmGUS_L1_SA0_CMD_OUT_BASE_IDX = 1 # macro
mmGUS_L1_SA0_DATA_IN = 0x2c54 # macro
mmGUS_L1_SA0_DATA_IN_BASE_IDX = 1 # macro
mmGUS_L1_SA0_DATA_OUT = 0x2c55 # macro
mmGUS_L1_SA0_DATA_OUT_BASE_IDX = 1 # macro
mmGUS_L1_SA0_DATA_U_IN = 0x2c56 # macro
mmGUS_L1_SA0_DATA_U_IN_BASE_IDX = 1 # macro
mmGUS_L1_SA0_DATA_U_OUT = 0x2c57 # macro
mmGUS_L1_SA0_DATA_U_OUT_BASE_IDX = 1 # macro
mmGUS_L1_SA1_CMD_IN = 0x2c58 # macro
mmGUS_L1_SA1_CMD_IN_BASE_IDX = 1 # macro
mmGUS_L1_SA1_CMD_OUT = 0x2c59 # macro
mmGUS_L1_SA1_CMD_OUT_BASE_IDX = 1 # macro
mmGUS_L1_SA1_DATA_IN = 0x2c5a # macro
mmGUS_L1_SA1_DATA_IN_BASE_IDX = 1 # macro
mmGUS_L1_SA1_DATA_OUT = 0x2c5b # macro
mmGUS_L1_SA1_DATA_OUT_BASE_IDX = 1 # macro
mmGUS_L1_SA1_DATA_U_IN = 0x2c5c # macro
mmGUS_L1_SA1_DATA_U_IN_BASE_IDX = 1 # macro
mmGUS_L1_SA1_DATA_U_OUT = 0x2c5d # macro
mmGUS_L1_SA1_DATA_U_OUT_BASE_IDX = 1 # macro
mmGUS_L1_SA2_CMD_IN = 0x2c5e # macro
mmGUS_L1_SA2_CMD_IN_BASE_IDX = 1 # macro
mmGUS_L1_SA2_CMD_OUT = 0x2c5f # macro
mmGUS_L1_SA2_CMD_OUT_BASE_IDX = 1 # macro
mmGUS_L1_SA2_DATA_IN = 0x2c60 # macro
mmGUS_L1_SA2_DATA_IN_BASE_IDX = 1 # macro
mmGUS_L1_SA2_DATA_OUT = 0x2c61 # macro
mmGUS_L1_SA2_DATA_OUT_BASE_IDX = 1 # macro
mmGUS_L1_SA2_DATA_U_IN = 0x2c62 # macro
mmGUS_L1_SA2_DATA_U_IN_BASE_IDX = 1 # macro
mmGUS_L1_SA2_DATA_U_OUT = 0x2c63 # macro
mmGUS_L1_SA2_DATA_U_OUT_BASE_IDX = 1 # macro
mmGUS_L1_SA3_CMD_IN = 0x2c64 # macro
mmGUS_L1_SA3_CMD_IN_BASE_IDX = 1 # macro
mmGUS_L1_SA3_CMD_OUT = 0x2c65 # macro
mmGUS_L1_SA3_CMD_OUT_BASE_IDX = 1 # macro
mmGUS_L1_SA3_DATA_IN = 0x2c66 # macro
mmGUS_L1_SA3_DATA_IN_BASE_IDX = 1 # macro
mmGUS_L1_SA3_DATA_OUT = 0x2c67 # macro
mmGUS_L1_SA3_DATA_OUT_BASE_IDX = 1 # macro
mmGUS_L1_SA3_DATA_U_IN = 0x2c68 # macro
mmGUS_L1_SA3_DATA_U_IN_BASE_IDX = 1 # macro
mmGUS_L1_SA3_DATA_U_OUT = 0x2c69 # macro
mmGUS_L1_SA3_DATA_U_OUT_BASE_IDX = 1 # macro
mmGUS_MISC3 = 0x2c6a # macro
mmGUS_MISC3_BASE_IDX = 1 # macro
mmGUS_WRRSP_FIFO_CNTL = 0x2c6b # macro
mmGUS_WRRSP_FIFO_CNTL_BASE_IDX = 1 # macro
mmGL1_DRAM_BURST_MASK = 0x2d02 # macro
mmGL1_DRAM_BURST_MASK_BASE_IDX = 1 # macro
mmGL1_ARB_STATUS = 0x2d03 # macro
mmGL1_ARB_STATUS_BASE_IDX = 1 # macro
mmGL1_PIPE_STEER = 0x2d10 # macro
mmGL1_PIPE_STEER_BASE_IDX = 1 # macro
mmGL1C_STATUS = 0x2d41 # macro
mmGL1C_STATUS_BASE_IDX = 1 # macro
mmGL1C_UTCL0_CNTL2 = 0x2d43 # macro
mmGL1C_UTCL0_CNTL2_BASE_IDX = 1 # macro
mmGL1C_UTCL0_STATUS = 0x2d44 # macro
mmGL1C_UTCL0_STATUS_BASE_IDX = 1 # macro
mmGL1C_UTCL0_RETRY = 0x2d45 # macro
mmGL1C_UTCL0_RETRY_BASE_IDX = 1 # macro
mmCH_ARB_CTRL = 0x2d80 # macro
mmCH_ARB_CTRL_BASE_IDX = 1 # macro
mmCH_DRAM_BURST_MASK = 0x2d82 # macro
mmCH_DRAM_BURST_MASK_BASE_IDX = 1 # macro
mmCH_ARB_STATUS = 0x2d83 # macro
mmCH_ARB_STATUS_BASE_IDX = 1 # macro
mmCH_DRAM_BURST_CTRL = 0x2d84 # macro
mmCH_DRAM_BURST_CTRL_BASE_IDX = 1 # macro
mmCHA_CHC_CREDITS = 0x2d88 # macro
mmCHA_CHC_CREDITS_BASE_IDX = 1 # macro
mmCHA_CLIENT_FREE_DELAY = 0x2d89 # macro
mmCHA_CLIENT_FREE_DELAY_BASE_IDX = 1 # macro
mmCH_PIPE_STEER = 0x2d90 # macro
mmCH_PIPE_STEER_BASE_IDX = 1 # macro
mmCH_VC5_ENABLE = 0x2d94 # macro
mmCH_VC5_ENABLE_BASE_IDX = 1 # macro
mmCHC_CTRL = 0x2dc0 # macro
mmCHC_CTRL_BASE_IDX = 1 # macro
mmCHC_STATUS = 0x2dc1 # macro
mmCHC_STATUS_BASE_IDX = 1 # macro
mmCHCG_CTRL = 0x2dc2 # macro
mmCHCG_CTRL_BASE_IDX = 1 # macro
mmCHCG_STATUS = 0x2dc3 # macro
mmCHCG_STATUS_BASE_IDX = 1 # macro
mmGL2C_CTRL = 0x2e00 # macro
mmGL2C_CTRL_BASE_IDX = 1 # macro
mmGL2C_CTRL2 = 0x2e01 # macro
mmGL2C_CTRL2_BASE_IDX = 1 # macro
mmGL2C_ADDR_MATCH_MASK = 0x2e03 # macro
mmGL2C_ADDR_MATCH_MASK_BASE_IDX = 1 # macro
mmGL2C_ADDR_MATCH_SIZE = 0x2e04 # macro
mmGL2C_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro
mmGL2C_WBINVL2 = 0x2e05 # macro
mmGL2C_WBINVL2_BASE_IDX = 1 # macro
mmGL2C_SOFT_RESET = 0x2e06 # macro
mmGL2C_SOFT_RESET_BASE_IDX = 1 # macro
mmGL2C_CM_CTRL0 = 0x2e07 # macro
mmGL2C_CM_CTRL0_BASE_IDX = 1 # macro
mmGL2C_CM_CTRL1 = 0x2e08 # macro
mmGL2C_CM_CTRL1_BASE_IDX = 1 # macro
mmGL2C_CM_STALL = 0x2e09 # macro
mmGL2C_CM_STALL_BASE_IDX = 1 # macro
mmGL2C_MDC_PF_FLAG_CTRL = 0x2e0a # macro
mmGL2C_MDC_PF_FLAG_CTRL_BASE_IDX = 1 # macro
mmGL2C_LB_CTR_CTRL = 0x2e0d # macro
mmGL2C_LB_CTR_CTRL_BASE_IDX = 1 # macro
mmGL2C_LB_DATA0 = 0x2e0e # macro
mmGL2C_LB_DATA0_BASE_IDX = 1 # macro
mmGL2C_LB_DATA1 = 0x2e0f # macro
mmGL2C_LB_DATA1_BASE_IDX = 1 # macro
mmGL2C_LB_DATA2 = 0x2e10 # macro
mmGL2C_LB_DATA2_BASE_IDX = 1 # macro
mmGL2C_LB_DATA3 = 0x2e11 # macro
mmGL2C_LB_DATA3_BASE_IDX = 1 # macro
mmGL2C_LB_CTR_SEL0 = 0x2e12 # macro
mmGL2C_LB_CTR_SEL0_BASE_IDX = 1 # macro
mmGL2C_LB_CTR_SEL1 = 0x2e13 # macro
mmGL2C_LB_CTR_SEL1_BASE_IDX = 1 # macro
mmGL2A_ADDR_MATCH_CTRL = 0x2e20 # macro
mmGL2A_ADDR_MATCH_CTRL_BASE_IDX = 1 # macro
mmGL2A_ADDR_MATCH_MASK = 0x2e21 # macro
mmGL2A_ADDR_MATCH_MASK_BASE_IDX = 1 # macro
mmGL2A_ADDR_MATCH_SIZE = 0x2e22 # macro
mmGL2A_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro
mmGL2A_PRIORITY_CTRL = 0x2e23 # macro
mmGL2A_PRIORITY_CTRL_BASE_IDX = 1 # macro
mmGL2_PIPE_STEER_0 = 0x2e25 # macro
mmGL2_PIPE_STEER_0_BASE_IDX = 1 # macro
mmGL2_PIPE_STEER_1 = 0x2e26 # macro
mmGL2_PIPE_STEER_1_BASE_IDX = 1 # macro
mmCPG_PERFCOUNTER1_LO = 0x3000 # macro
mmCPG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmCPG_PERFCOUNTER1_HI = 0x3001 # macro
mmCPG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmCPG_PERFCOUNTER0_LO = 0x3002 # macro
mmCPG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmCPG_PERFCOUNTER0_HI = 0x3003 # macro
mmCPG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmCPC_PERFCOUNTER1_LO = 0x3004 # macro
mmCPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmCPC_PERFCOUNTER1_HI = 0x3005 # macro
mmCPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmCPC_PERFCOUNTER0_LO = 0x3006 # macro
mmCPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmCPC_PERFCOUNTER0_HI = 0x3007 # macro
mmCPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmCPF_PERFCOUNTER1_LO = 0x3008 # macro
mmCPF_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmCPF_PERFCOUNTER1_HI = 0x3009 # macro
mmCPF_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmCPF_PERFCOUNTER0_LO = 0x300a # macro
mmCPF_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmCPF_PERFCOUNTER0_HI = 0x300b # macro
mmCPF_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmCPF_LATENCY_STATS_DATA = 0x300c # macro
mmCPF_LATENCY_STATS_DATA_BASE_IDX = 1 # macro
mmCPG_LATENCY_STATS_DATA = 0x300d # macro
mmCPG_LATENCY_STATS_DATA_BASE_IDX = 1 # macro
mmCPC_LATENCY_STATS_DATA = 0x300e # macro
mmCPC_LATENCY_STATS_DATA_BASE_IDX = 1 # macro
mmGRBM_PERFCOUNTER0_LO = 0x3040 # macro
mmGRBM_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmGRBM_PERFCOUNTER0_HI = 0x3041 # macro
mmGRBM_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmGRBM_PERFCOUNTER1_LO = 0x3043 # macro
mmGRBM_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmGRBM_PERFCOUNTER1_HI = 0x3044 # macro
mmGRBM_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmGRBM_SE0_PERFCOUNTER_LO = 0x3045 # macro
mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX = 1 # macro
mmGRBM_SE0_PERFCOUNTER_HI = 0x3046 # macro
mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX = 1 # macro
mmGRBM_SE1_PERFCOUNTER_LO = 0x3047 # macro
mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX = 1 # macro
mmGRBM_SE1_PERFCOUNTER_HI = 0x3048 # macro
mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX = 1 # macro
mmGRBM_SE2_PERFCOUNTER_LO = 0x3049 # macro
mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX = 1 # macro
mmGRBM_SE2_PERFCOUNTER_HI = 0x304a # macro
mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX = 1 # macro
mmGRBM_SE3_PERFCOUNTER_LO = 0x304b # macro
mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX = 1 # macro
mmGRBM_SE3_PERFCOUNTER_HI = 0x304c # macro
mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER0_LO = 0x30a4 # macro
mmGE1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER0_HI = 0x30a5 # macro
mmGE1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER1_LO = 0x30a6 # macro
mmGE1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER1_HI = 0x30a7 # macro
mmGE1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER2_LO = 0x30a8 # macro
mmGE1_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER2_HI = 0x30a9 # macro
mmGE1_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER3_LO = 0x30aa # macro
mmGE1_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER3_HI = 0x30ab # macro
mmGE1_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER0_LO = 0x30ac # macro
mmGE2_DIST_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER0_HI = 0x30ad # macro
mmGE2_DIST_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER1_LO = 0x30ae # macro
mmGE2_DIST_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER1_HI = 0x30af # macro
mmGE2_DIST_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER2_LO = 0x30b0 # macro
mmGE2_DIST_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER2_HI = 0x30b1 # macro
mmGE2_DIST_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER3_LO = 0x30b2 # macro
mmGE2_DIST_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER3_HI = 0x30b3 # macro
mmGE2_DIST_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER0_LO = 0x30b4 # macro
mmGE2_SE_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER0_HI = 0x30b5 # macro
mmGE2_SE_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER1_LO = 0x30b6 # macro
mmGE2_SE_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER1_HI = 0x30b7 # macro
mmGE2_SE_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER2_LO = 0x30b8 # macro
mmGE2_SE_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER2_HI = 0x30b9 # macro
mmGE2_SE_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER3_LO = 0x30ba # macro
mmGE2_SE_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER3_HI = 0x30bb # macro
mmGE2_SE_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER0_LO = 0x3100 # macro
mmPA_SU_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER0_HI = 0x3101 # macro
mmPA_SU_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER1_LO = 0x3102 # macro
mmPA_SU_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER1_HI = 0x3103 # macro
mmPA_SU_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER2_LO = 0x3104 # macro
mmPA_SU_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER2_HI = 0x3105 # macro
mmPA_SU_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER3_LO = 0x3106 # macro
mmPA_SU_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER3_HI = 0x3107 # macro
mmPA_SU_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER0_LO = 0x3140 # macro
mmPA_SC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER0_HI = 0x3141 # macro
mmPA_SC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER1_LO = 0x3142 # macro
mmPA_SC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER1_HI = 0x3143 # macro
mmPA_SC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER2_LO = 0x3144 # macro
mmPA_SC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER2_HI = 0x3145 # macro
mmPA_SC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER3_LO = 0x3146 # macro
mmPA_SC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER3_HI = 0x3147 # macro
mmPA_SC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER4_LO = 0x3148 # macro
mmPA_SC_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER4_HI = 0x3149 # macro
mmPA_SC_PERFCOUNTER4_HI_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER5_LO = 0x314a # macro
mmPA_SC_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER5_HI = 0x314b # macro
mmPA_SC_PERFCOUNTER5_HI_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER6_LO = 0x314c # macro
mmPA_SC_PERFCOUNTER6_LO_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER6_HI = 0x314d # macro
mmPA_SC_PERFCOUNTER6_HI_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER7_LO = 0x314e # macro
mmPA_SC_PERFCOUNTER7_LO_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER7_HI = 0x314f # macro
mmPA_SC_PERFCOUNTER7_HI_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER0_HI = 0x3180 # macro
mmSPI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER0_LO = 0x3181 # macro
mmSPI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER1_HI = 0x3182 # macro
mmSPI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER1_LO = 0x3183 # macro
mmSPI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER2_HI = 0x3184 # macro
mmSPI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER2_LO = 0x3185 # macro
mmSPI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER3_HI = 0x3186 # macro
mmSPI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER3_LO = 0x3187 # macro
mmSPI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER4_HI = 0x3188 # macro
mmSPI_PERFCOUNTER4_HI_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER4_LO = 0x3189 # macro
mmSPI_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER5_HI = 0x318a # macro
mmSPI_PERFCOUNTER5_HI_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER5_LO = 0x318b # macro
mmSPI_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER0_LO = 0x31c0 # macro
mmSQ_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER0_HI = 0x31c1 # macro
mmSQ_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER1_LO = 0x31c2 # macro
mmSQ_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER1_HI = 0x31c3 # macro
mmSQ_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER2_LO = 0x31c4 # macro
mmSQ_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER2_HI = 0x31c5 # macro
mmSQ_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER3_LO = 0x31c6 # macro
mmSQ_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER3_HI = 0x31c7 # macro
mmSQ_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER4_LO = 0x31c8 # macro
mmSQ_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER4_HI = 0x31c9 # macro
mmSQ_PERFCOUNTER4_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER5_LO = 0x31ca # macro
mmSQ_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER5_HI = 0x31cb # macro
mmSQ_PERFCOUNTER5_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER6_LO = 0x31cc # macro
mmSQ_PERFCOUNTER6_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER6_HI = 0x31cd # macro
mmSQ_PERFCOUNTER6_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER7_LO = 0x31ce # macro
mmSQ_PERFCOUNTER7_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER7_HI = 0x31cf # macro
mmSQ_PERFCOUNTER7_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER8_LO = 0x31d0 # macro
mmSQ_PERFCOUNTER8_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER8_HI = 0x31d1 # macro
mmSQ_PERFCOUNTER8_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER9_LO = 0x31d2 # macro
mmSQ_PERFCOUNTER9_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER9_HI = 0x31d3 # macro
mmSQ_PERFCOUNTER9_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER10_LO = 0x31d4 # macro
mmSQ_PERFCOUNTER10_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER10_HI = 0x31d5 # macro
mmSQ_PERFCOUNTER10_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER11_LO = 0x31d6 # macro
mmSQ_PERFCOUNTER11_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER11_HI = 0x31d7 # macro
mmSQ_PERFCOUNTER11_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER12_LO = 0x31d8 # macro
mmSQ_PERFCOUNTER12_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER12_HI = 0x31d9 # macro
mmSQ_PERFCOUNTER12_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER13_LO = 0x31da # macro
mmSQ_PERFCOUNTER13_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER13_HI = 0x31db # macro
mmSQ_PERFCOUNTER13_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER14_LO = 0x31dc # macro
mmSQ_PERFCOUNTER14_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER14_HI = 0x31dd # macro
mmSQ_PERFCOUNTER14_HI_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER15_LO = 0x31de # macro
mmSQ_PERFCOUNTER15_LO_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER15_HI = 0x31df # macro
mmSQ_PERFCOUNTER15_HI_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER0_LO = 0x3240 # macro
mmSX_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER0_HI = 0x3241 # macro
mmSX_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER1_LO = 0x3242 # macro
mmSX_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER1_HI = 0x3243 # macro
mmSX_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER2_LO = 0x3244 # macro
mmSX_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER2_HI = 0x3245 # macro
mmSX_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER3_LO = 0x3246 # macro
mmSX_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER3_HI = 0x3247 # macro
mmSX_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmGCEA_PERFCOUNTER2_LO = 0x3260 # macro
mmGCEA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmGCEA_PERFCOUNTER2_HI = 0x3261 # macro
mmGCEA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmGCEA_PERFCOUNTER_LO = 0x3262 # macro
mmGCEA_PERFCOUNTER_LO_BASE_IDX = 1 # macro
mmGCEA_PERFCOUNTER_HI = 0x3263 # macro
mmGCEA_PERFCOUNTER_HI_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER0_LO = 0x3280 # macro
mmGDS_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER0_HI = 0x3281 # macro
mmGDS_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER1_LO = 0x3282 # macro
mmGDS_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER1_HI = 0x3283 # macro
mmGDS_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER2_LO = 0x3284 # macro
mmGDS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER2_HI = 0x3285 # macro
mmGDS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER3_LO = 0x3286 # macro
mmGDS_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER3_HI = 0x3287 # macro
mmGDS_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmTA_PERFCOUNTER0_LO = 0x32c0 # macro
mmTA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmTA_PERFCOUNTER0_HI = 0x32c1 # macro
mmTA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmTA_PERFCOUNTER1_LO = 0x32c2 # macro
mmTA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmTA_PERFCOUNTER1_HI = 0x32c3 # macro
mmTA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmTD_PERFCOUNTER0_LO = 0x3300 # macro
mmTD_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmTD_PERFCOUNTER0_HI = 0x3301 # macro
mmTD_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmTD_PERFCOUNTER1_LO = 0x3302 # macro
mmTD_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmTD_PERFCOUNTER1_HI = 0x3303 # macro
mmTD_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER0_LO = 0x3340 # macro
mmTCP_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER0_HI = 0x3341 # macro
mmTCP_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER1_LO = 0x3342 # macro
mmTCP_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER1_HI = 0x3343 # macro
mmTCP_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER2_LO = 0x3344 # macro
mmTCP_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER2_HI = 0x3345 # macro
mmTCP_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER3_LO = 0x3346 # macro
mmTCP_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER3_HI = 0x3347 # macro
mmTCP_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER0_LO = 0x3380 # macro
mmGL2C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER0_HI = 0x3381 # macro
mmGL2C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER1_LO = 0x3382 # macro
mmGL2C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER1_HI = 0x3383 # macro
mmGL2C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER2_LO = 0x3384 # macro
mmGL2C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER2_HI = 0x3385 # macro
mmGL2C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER3_LO = 0x3386 # macro
mmGL2C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER3_HI = 0x3387 # macro
mmGL2C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER0_LO = 0x3390 # macro
mmGL2A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER0_HI = 0x3391 # macro
mmGL2A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER1_LO = 0x3392 # macro
mmGL2A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER1_HI = 0x3393 # macro
mmGL2A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER2_LO = 0x3394 # macro
mmGL2A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER2_HI = 0x3395 # macro
mmGL2A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER3_LO = 0x3396 # macro
mmGL2A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER3_HI = 0x3397 # macro
mmGL2A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmGL1C_PERFCOUNTER0_LO = 0x33a0 # macro
mmGL1C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmGL1C_PERFCOUNTER0_HI = 0x33a1 # macro
mmGL1C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmGL1C_PERFCOUNTER1_LO = 0x33a2 # macro
mmGL1C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmGL1C_PERFCOUNTER1_HI = 0x33a3 # macro
mmGL1C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmGL1C_PERFCOUNTER2_LO = 0x33a4 # macro
mmGL1C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmGL1C_PERFCOUNTER2_HI = 0x33a5 # macro
mmGL1C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmGL1C_PERFCOUNTER3_LO = 0x33a6 # macro
mmGL1C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmGL1C_PERFCOUNTER3_HI = 0x33a7 # macro
mmGL1C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmCHC_PERFCOUNTER0_LO = 0x33c0 # macro
mmCHC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmCHC_PERFCOUNTER0_HI = 0x33c1 # macro
mmCHC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmCHC_PERFCOUNTER1_LO = 0x33c2 # macro
mmCHC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmCHC_PERFCOUNTER1_HI = 0x33c3 # macro
mmCHC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmCHC_PERFCOUNTER2_LO = 0x33c4 # macro
mmCHC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmCHC_PERFCOUNTER2_HI = 0x33c5 # macro
mmCHC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmCHC_PERFCOUNTER3_LO = 0x33c6 # macro
mmCHC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmCHC_PERFCOUNTER3_HI = 0x33c7 # macro
mmCHC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmCHCG_PERFCOUNTER0_LO = 0x33c8 # macro
mmCHCG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmCHCG_PERFCOUNTER0_HI = 0x33c9 # macro
mmCHCG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmCHCG_PERFCOUNTER1_LO = 0x33ca # macro
mmCHCG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmCHCG_PERFCOUNTER1_HI = 0x33cb # macro
mmCHCG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmCHCG_PERFCOUNTER2_LO = 0x33cc # macro
mmCHCG_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmCHCG_PERFCOUNTER2_HI = 0x33cd # macro
mmCHCG_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmCHCG_PERFCOUNTER3_LO = 0x33ce # macro
mmCHCG_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmCHCG_PERFCOUNTER3_HI = 0x33cf # macro
mmCHCG_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER0_LO = 0x3406 # macro
mmCB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER0_HI = 0x3407 # macro
mmCB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER1_LO = 0x3408 # macro
mmCB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER1_HI = 0x3409 # macro
mmCB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER2_LO = 0x340a # macro
mmCB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER2_HI = 0x340b # macro
mmCB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER3_LO = 0x340c # macro
mmCB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER3_HI = 0x340d # macro
mmCB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER0_LO = 0x3440 # macro
mmDB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER0_HI = 0x3441 # macro
mmDB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER1_LO = 0x3442 # macro
mmDB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER1_HI = 0x3443 # macro
mmDB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER2_LO = 0x3444 # macro
mmDB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER2_HI = 0x3445 # macro
mmDB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER3_LO = 0x3446 # macro
mmDB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER3_HI = 0x3447 # macro
mmDB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmRLC_PERFCOUNTER0_LO = 0x3480 # macro
mmRLC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmRLC_PERFCOUNTER0_HI = 0x3481 # macro
mmRLC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmRLC_PERFCOUNTER1_LO = 0x3482 # macro
mmRLC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmRLC_PERFCOUNTER1_HI = 0x3483 # macro
mmRLC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER0_LO = 0x34c0 # macro
mmRMI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER0_HI = 0x34c1 # macro
mmRMI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER1_LO = 0x34c2 # macro
mmRMI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER1_HI = 0x34c3 # macro
mmRMI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER2_LO = 0x34c4 # macro
mmRMI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER2_HI = 0x34c5 # macro
mmRMI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER3_LO = 0x34c6 # macro
mmRMI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER3_HI = 0x34c7 # macro
mmRMI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmUTCL1_PERFCOUNTER0_LO = 0x351c # macro
mmUTCL1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmUTCL1_PERFCOUNTER0_HI = 0x351d # macro
mmUTCL1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmUTCL1_PERFCOUNTER1_LO = 0x351e # macro
mmUTCL1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmUTCL1_PERFCOUNTER1_HI = 0x351f # macro
mmUTCL1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmGCR_PERFCOUNTER0_LO = 0x3520 # macro
mmGCR_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmGCR_PERFCOUNTER0_HI = 0x3521 # macro
mmGCR_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmGCR_PERFCOUNTER1_LO = 0x3522 # macro
mmGCR_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmGCR_PERFCOUNTER1_HI = 0x3523 # macro
mmGCR_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER0_LO = 0x3580 # macro
mmPA_PH_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER0_HI = 0x3581 # macro
mmPA_PH_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER1_LO = 0x3582 # macro
mmPA_PH_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER1_HI = 0x3583 # macro
mmPA_PH_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER2_LO = 0x3584 # macro
mmPA_PH_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER2_HI = 0x3585 # macro
mmPA_PH_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER3_LO = 0x3586 # macro
mmPA_PH_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER3_HI = 0x3587 # macro
mmPA_PH_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER4_LO = 0x3588 # macro
mmPA_PH_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER4_HI = 0x3589 # macro
mmPA_PH_PERFCOUNTER4_HI_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER5_LO = 0x358a # macro
mmPA_PH_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER5_HI = 0x358b # macro
mmPA_PH_PERFCOUNTER5_HI_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER6_LO = 0x358c # macro
mmPA_PH_PERFCOUNTER6_LO_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER6_HI = 0x358d # macro
mmPA_PH_PERFCOUNTER6_HI_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER7_LO = 0x358e # macro
mmPA_PH_PERFCOUNTER7_LO_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER7_HI = 0x358f # macro
mmPA_PH_PERFCOUNTER7_HI_BASE_IDX = 1 # macro
mmGL1A_PERFCOUNTER0_LO = 0x35c0 # macro
mmGL1A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmGL1A_PERFCOUNTER0_HI = 0x35c1 # macro
mmGL1A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmGL1A_PERFCOUNTER1_LO = 0x35c2 # macro
mmGL1A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmGL1A_PERFCOUNTER1_HI = 0x35c3 # macro
mmGL1A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmGL1A_PERFCOUNTER2_LO = 0x35c4 # macro
mmGL1A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmGL1A_PERFCOUNTER2_HI = 0x35c5 # macro
mmGL1A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmGL1A_PERFCOUNTER3_LO = 0x35c6 # macro
mmGL1A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmGL1A_PERFCOUNTER3_HI = 0x35c7 # macro
mmGL1A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmCHA_PERFCOUNTER0_LO = 0x3600 # macro
mmCHA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmCHA_PERFCOUNTER0_HI = 0x3601 # macro
mmCHA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmCHA_PERFCOUNTER1_LO = 0x3602 # macro
mmCHA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmCHA_PERFCOUNTER1_HI = 0x3603 # macro
mmCHA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmCHA_PERFCOUNTER2_LO = 0x3604 # macro
mmCHA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmCHA_PERFCOUNTER2_HI = 0x3605 # macro
mmCHA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmCHA_PERFCOUNTER3_LO = 0x3606 # macro
mmCHA_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
mmCHA_PERFCOUNTER3_HI = 0x3607 # macro
mmCHA_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
mmGUS_PERFCOUNTER2_LO = 0x3640 # macro
mmGUS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
mmGUS_PERFCOUNTER2_HI = 0x3641 # macro
mmGUS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
mmGUS_PERFCOUNTER_LO = 0x3642 # macro
mmGUS_PERFCOUNTER_LO_BASE_IDX = 1 # macro
mmGUS_PERFCOUNTER_HI = 0x3643 # macro
mmGUS_PERFCOUNTER_HI_BASE_IDX = 1 # macro
mmGCMC_VM_L2_PERFCOUNTER_LO = 0x34e8 # macro
mmGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX = 1 # macro
mmGCMC_VM_L2_PERFCOUNTER_HI = 0x34e9 # macro
mmGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX = 1 # macro
mmGCUTCL2_PERFCOUNTER_LO = 0x34ea # macro
mmGCUTCL2_PERFCOUNTER_LO_BASE_IDX = 1 # macro
mmGCUTCL2_PERFCOUNTER_HI = 0x34eb # macro
mmGCUTCL2_PERFCOUNTER_HI_BASE_IDX = 1 # macro
mmGCVML2_PERFCOUNTER2_0_LO = 0x34f8 # macro
mmGCVML2_PERFCOUNTER2_0_LO_BASE_IDX = 1 # macro
mmGCVML2_PERFCOUNTER2_1_LO = 0x34f9 # macro
mmGCVML2_PERFCOUNTER2_1_LO_BASE_IDX = 1 # macro
mmGCVML2_PERFCOUNTER2_0_HI = 0x34fa # macro
mmGCVML2_PERFCOUNTER2_0_HI_BASE_IDX = 1 # macro
mmGCVML2_PERFCOUNTER2_1_HI = 0x34fb # macro
mmGCVML2_PERFCOUNTER2_1_HI_BASE_IDX = 1 # macro
mmSDMA0_PERFCNT_PERFCOUNTER_LO = 0x3660 # macro
mmSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro
mmSDMA0_PERFCNT_PERFCOUNTER_HI = 0x3661 # macro
mmSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro
mmSDMA0_PERFCOUNTER0_LO = 0x3662 # macro
mmSDMA0_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmSDMA0_PERFCOUNTER0_HI = 0x3663 # macro
mmSDMA0_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmSDMA0_PERFCOUNTER1_LO = 0x3664 # macro
mmSDMA0_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmSDMA0_PERFCOUNTER1_HI = 0x3665 # macro
mmSDMA0_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmSDMA1_PERFCNT_PERFCOUNTER_LO = 0x366c # macro
mmSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro
mmSDMA1_PERFCNT_PERFCOUNTER_HI = 0x366d # macro
mmSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro
mmSDMA1_PERFCOUNTER0_LO = 0x366e # macro
mmSDMA1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmSDMA1_PERFCOUNTER0_HI = 0x366f # macro
mmSDMA1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmSDMA1_PERFCOUNTER1_LO = 0x3670 # macro
mmSDMA1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmSDMA1_PERFCOUNTER1_HI = 0x3671 # macro
mmSDMA1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmSDMA2_PERFCNT_PERFCOUNTER_LO = 0x3678 # macro
mmSDMA2_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro
mmSDMA2_PERFCNT_PERFCOUNTER_HI = 0x3679 # macro
mmSDMA2_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro
mmSDMA2_PERFCOUNTER0_LO = 0x367a # macro
mmSDMA2_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmSDMA2_PERFCOUNTER0_HI = 0x367b # macro
mmSDMA2_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmSDMA2_PERFCOUNTER1_LO = 0x367c # macro
mmSDMA2_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmSDMA2_PERFCOUNTER1_HI = 0x367d # macro
mmSDMA2_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmSDMA3_PERFCNT_PERFCOUNTER_LO = 0x3684 # macro
mmSDMA3_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro
mmSDMA3_PERFCNT_PERFCOUNTER_HI = 0x3685 # macro
mmSDMA3_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro
mmSDMA3_PERFCOUNTER0_LO = 0x3686 # macro
mmSDMA3_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
mmSDMA3_PERFCOUNTER0_HI = 0x3687 # macro
mmSDMA3_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
mmSDMA3_PERFCOUNTER1_LO = 0x3688 # macro
mmSDMA3_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
mmSDMA3_PERFCOUNTER1_HI = 0x3689 # macro
mmSDMA3_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
mmCPG_PERFCOUNTER1_SELECT = 0x3800 # macro
mmCPG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmCPG_PERFCOUNTER0_SELECT1 = 0x3801 # macro
mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmCPG_PERFCOUNTER0_SELECT = 0x3802 # macro
mmCPG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmCPC_PERFCOUNTER1_SELECT = 0x3803 # macro
mmCPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmCPC_PERFCOUNTER0_SELECT1 = 0x3804 # macro
mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmCPF_PERFCOUNTER1_SELECT = 0x3805 # macro
mmCPF_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmCPF_PERFCOUNTER0_SELECT1 = 0x3806 # macro
mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmCPF_PERFCOUNTER0_SELECT = 0x3807 # macro
mmCPF_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmCP_PERFMON_CNTL = 0x3808 # macro
mmCP_PERFMON_CNTL_BASE_IDX = 1 # macro
mmCPC_PERFCOUNTER0_SELECT = 0x3809 # macro
mmCPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmCPF_TC_PERF_COUNTER_WINDOW_SELECT = 0x380a # macro
mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro
mmCPG_TC_PERF_COUNTER_WINDOW_SELECT = 0x380b # macro
mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro
mmCPF_LATENCY_STATS_SELECT = 0x380c # macro
mmCPF_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro
mmCPG_LATENCY_STATS_SELECT = 0x380d # macro
mmCPG_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro
mmCPC_LATENCY_STATS_SELECT = 0x380e # macro
mmCPC_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro
mmCP_DRAW_OBJECT = 0x3810 # macro
mmCP_DRAW_OBJECT_BASE_IDX = 1 # macro
mmCP_DRAW_OBJECT_COUNTER = 0x3811 # macro
mmCP_DRAW_OBJECT_COUNTER_BASE_IDX = 1 # macro
mmCP_DRAW_WINDOW_MASK_HI = 0x3812 # macro
mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX = 1 # macro
mmCP_DRAW_WINDOW_HI = 0x3813 # macro
mmCP_DRAW_WINDOW_HI_BASE_IDX = 1 # macro
mmCP_DRAW_WINDOW_LO = 0x3814 # macro
mmCP_DRAW_WINDOW_LO_BASE_IDX = 1 # macro
mmCP_DRAW_WINDOW_CNTL = 0x3815 # macro
mmCP_DRAW_WINDOW_CNTL_BASE_IDX = 1 # macro
mmGRBM_PERFCOUNTER0_SELECT = 0x3840 # macro
mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmGRBM_PERFCOUNTER1_SELECT = 0x3841 # macro
mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmGRBM_SE0_PERFCOUNTER_SELECT = 0x3842 # macro
mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
mmGRBM_SE1_PERFCOUNTER_SELECT = 0x3843 # macro
mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
mmGRBM_SE2_PERFCOUNTER_SELECT = 0x3844 # macro
mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
mmGRBM_SE3_PERFCOUNTER_SELECT = 0x3845 # macro
mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
mmGRBM_PERFCOUNTER0_SELECT_HI = 0x384d # macro
mmGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX = 1 # macro
mmGRBM_PERFCOUNTER1_SELECT_HI = 0x384e # macro
mmGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER0_SELECT = 0x38a4 # macro
mmGE1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER0_SELECT1 = 0x38a5 # macro
mmGE1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER1_SELECT = 0x38a6 # macro
mmGE1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER1_SELECT1 = 0x38a7 # macro
mmGE1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER2_SELECT = 0x38a8 # macro
mmGE1_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER2_SELECT1 = 0x38a9 # macro
mmGE1_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER3_SELECT = 0x38aa # macro
mmGE1_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmGE1_PERFCOUNTER3_SELECT1 = 0x38ab # macro
mmGE1_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER0_SELECT = 0x38ac # macro
mmGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER0_SELECT1 = 0x38ad # macro
mmGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER1_SELECT = 0x38ae # macro
mmGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER1_SELECT1 = 0x38af # macro
mmGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER2_SELECT = 0x38b0 # macro
mmGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER2_SELECT1 = 0x38b1 # macro
mmGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER3_SELECT = 0x38b2 # macro
mmGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmGE2_DIST_PERFCOUNTER3_SELECT1 = 0x38b3 # macro
mmGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER0_SELECT = 0x38b4 # macro
mmGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER0_SELECT1 = 0x38b5 # macro
mmGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER1_SELECT = 0x38b6 # macro
mmGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER1_SELECT1 = 0x38b7 # macro
mmGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER2_SELECT = 0x38b8 # macro
mmGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER2_SELECT1 = 0x38b9 # macro
mmGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER3_SELECT = 0x38ba # macro
mmGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmGE2_SE_PERFCOUNTER3_SELECT1 = 0x38bb # macro
mmGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER0_SELECT = 0x3900 # macro
mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER0_SELECT1 = 0x3901 # macro
mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER1_SELECT = 0x3902 # macro
mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER1_SELECT1 = 0x3903 # macro
mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER2_SELECT = 0x3904 # macro
mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER2_SELECT1 = 0x3905 # macro
mmPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER3_SELECT = 0x3906 # macro
mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmPA_SU_PERFCOUNTER3_SELECT1 = 0x3907 # macro
mmPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER0_SELECT = 0x3940 # macro
mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER0_SELECT1 = 0x3941 # macro
mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER1_SELECT = 0x3942 # macro
mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER2_SELECT = 0x3943 # macro
mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER3_SELECT = 0x3944 # macro
mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER4_SELECT = 0x3945 # macro
mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER5_SELECT = 0x3946 # macro
mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER6_SELECT = 0x3947 # macro
mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro
mmPA_SC_PERFCOUNTER7_SELECT = 0x3948 # macro
mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER0_SELECT = 0x3980 # macro
mmSPI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER1_SELECT = 0x3981 # macro
mmSPI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER2_SELECT = 0x3982 # macro
mmSPI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER3_SELECT = 0x3983 # macro
mmSPI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER0_SELECT1 = 0x3984 # macro
mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER1_SELECT1 = 0x3985 # macro
mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER2_SELECT1 = 0x3986 # macro
mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER3_SELECT1 = 0x3987 # macro
mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER4_SELECT = 0x3988 # macro
mmSPI_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER5_SELECT = 0x3989 # macro
mmSPI_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
mmSPI_PERFCOUNTER_BINS = 0x398a # macro
mmSPI_PERFCOUNTER_BINS_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER0_SELECT = 0x39c0 # macro
mmSQ_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER1_SELECT = 0x39c1 # macro
mmSQ_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER2_SELECT = 0x39c2 # macro
mmSQ_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER3_SELECT = 0x39c3 # macro
mmSQ_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER4_SELECT = 0x39c4 # macro
mmSQ_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER5_SELECT = 0x39c5 # macro
mmSQ_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER6_SELECT = 0x39c6 # macro
mmSQ_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER7_SELECT = 0x39c7 # macro
mmSQ_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER8_SELECT = 0x39c8 # macro
mmSQ_PERFCOUNTER8_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER9_SELECT = 0x39c9 # macro
mmSQ_PERFCOUNTER9_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER10_SELECT = 0x39ca # macro
mmSQ_PERFCOUNTER10_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER11_SELECT = 0x39cb # macro
mmSQ_PERFCOUNTER11_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER12_SELECT = 0x39cc # macro
mmSQ_PERFCOUNTER12_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER13_SELECT = 0x39cd # macro
mmSQ_PERFCOUNTER13_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER14_SELECT = 0x39ce # macro
mmSQ_PERFCOUNTER14_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER15_SELECT = 0x39cf # macro
mmSQ_PERFCOUNTER15_SELECT_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER_CTRL = 0x39e0 # macro
mmSQ_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro
mmSQ_PERFCOUNTER_CTRL2 = 0x39e2 # macro
mmSQ_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro
mmGCEA_PERFCOUNTER2_SELECT = 0x3a00 # macro
mmGCEA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmGCEA_PERFCOUNTER2_SELECT1 = 0x3a01 # macro
mmGCEA_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
mmGCEA_PERFCOUNTER2_MODE = 0x3a02 # macro
mmGCEA_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro
mmGCEA_PERFCOUNTER0_CFG = 0x3a03 # macro
mmGCEA_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
mmGCEA_PERFCOUNTER1_CFG = 0x3a04 # macro
mmGCEA_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
mmGCEA_PERFCOUNTER_RSLT_CNTL = 0x3a05 # macro
mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER0_SELECT = 0x3a40 # macro
mmSX_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER1_SELECT = 0x3a41 # macro
mmSX_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER2_SELECT = 0x3a42 # macro
mmSX_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER3_SELECT = 0x3a43 # macro
mmSX_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER0_SELECT1 = 0x3a44 # macro
mmSX_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmSX_PERFCOUNTER1_SELECT1 = 0x3a45 # macro
mmSX_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER0_SELECT = 0x3a80 # macro
mmGDS_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER1_SELECT = 0x3a81 # macro
mmGDS_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER2_SELECT = 0x3a82 # macro
mmGDS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER3_SELECT = 0x3a83 # macro
mmGDS_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER0_SELECT1 = 0x3a84 # macro
mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER1_SELECT1 = 0x3a85 # macro
mmGDS_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER2_SELECT1 = 0x3a86 # macro
mmGDS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
mmGDS_PERFCOUNTER3_SELECT1 = 0x3a87 # macro
mmGDS_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
mmTA_PERFCOUNTER0_SELECT = 0x3ac0 # macro
mmTA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmTA_PERFCOUNTER0_SELECT1 = 0x3ac1 # macro
mmTA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmTA_PERFCOUNTER1_SELECT = 0x3ac2 # macro
mmTA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmTD_PERFCOUNTER0_SELECT = 0x3b00 # macro
mmTD_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmTD_PERFCOUNTER0_SELECT1 = 0x3b01 # macro
mmTD_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmTD_PERFCOUNTER1_SELECT = 0x3b02 # macro
mmTD_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER0_SELECT = 0x3b40 # macro
mmTCP_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER0_SELECT1 = 0x3b41 # macro
mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER1_SELECT = 0x3b42 # macro
mmTCP_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER1_SELECT1 = 0x3b43 # macro
mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER2_SELECT = 0x3b44 # macro
mmTCP_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmTCP_PERFCOUNTER3_SELECT = 0x3b45 # macro
mmTCP_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER0_SELECT = 0x3b80 # macro
mmGL2C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER0_SELECT1 = 0x3b81 # macro
mmGL2C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER1_SELECT = 0x3b82 # macro
mmGL2C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER1_SELECT1 = 0x3b83 # macro
mmGL2C_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER2_SELECT = 0x3b84 # macro
mmGL2C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmGL2C_PERFCOUNTER3_SELECT = 0x3b85 # macro
mmGL2C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER0_SELECT = 0x3b90 # macro
mmGL2A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER0_SELECT1 = 0x3b91 # macro
mmGL2A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER1_SELECT = 0x3b92 # macro
mmGL2A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER1_SELECT1 = 0x3b93 # macro
mmGL2A_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER2_SELECT = 0x3b94 # macro
mmGL2A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmGL2A_PERFCOUNTER3_SELECT = 0x3b95 # macro
mmGL2A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmGL1C_PERFCOUNTER0_SELECT = 0x3ba0 # macro
mmGL1C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmGL1C_PERFCOUNTER0_SELECT1 = 0x3ba1 # macro
mmGL1C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmGL1C_PERFCOUNTER1_SELECT = 0x3ba2 # macro
mmGL1C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmGL1C_PERFCOUNTER2_SELECT = 0x3ba3 # macro
mmGL1C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmGL1C_PERFCOUNTER3_SELECT = 0x3ba4 # macro
mmGL1C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmCHC_PERFCOUNTER0_SELECT = 0x3bc0 # macro
mmCHC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmCHC_PERFCOUNTER0_SELECT1 = 0x3bc1 # macro
mmCHC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmCHC_PERFCOUNTER1_SELECT = 0x3bc2 # macro
mmCHC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmCHC_PERFCOUNTER2_SELECT = 0x3bc3 # macro
mmCHC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmCHC_PERFCOUNTER3_SELECT = 0x3bc4 # macro
mmCHC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmCHCG_PERFCOUNTER0_SELECT = 0x3bc6 # macro
mmCHCG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmCHCG_PERFCOUNTER0_SELECT1 = 0x3bc7 # macro
mmCHCG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmCHCG_PERFCOUNTER1_SELECT = 0x3bc8 # macro
mmCHCG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmCHCG_PERFCOUNTER2_SELECT = 0x3bc9 # macro
mmCHCG_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmCHCG_PERFCOUNTER3_SELECT = 0x3bca # macro
mmCHCG_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER_FILTER = 0x3c00 # macro
mmCB_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER0_SELECT = 0x3c01 # macro
mmCB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER0_SELECT1 = 0x3c02 # macro
mmCB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER1_SELECT = 0x3c03 # macro
mmCB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER2_SELECT = 0x3c04 # macro
mmCB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmCB_PERFCOUNTER3_SELECT = 0x3c05 # macro
mmCB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER0_SELECT = 0x3c40 # macro
mmDB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER0_SELECT1 = 0x3c41 # macro
mmDB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER1_SELECT = 0x3c42 # macro
mmDB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER1_SELECT1 = 0x3c43 # macro
mmDB_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER2_SELECT = 0x3c44 # macro
mmDB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmDB_PERFCOUNTER3_SELECT = 0x3c46 # macro
mmDB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmRLC_SPM_PERFMON_CNTL = 0x3c80 # macro
mmRLC_SPM_PERFMON_CNTL_BASE_IDX = 1 # macro
mmRLC_SPM_PERFMON_RING_BASE_LO = 0x3c81 # macro
mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX = 1 # macro
mmRLC_SPM_PERFMON_RING_BASE_HI = 0x3c82 # macro
mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX = 1 # macro
mmRLC_SPM_PERFMON_RING_SIZE = 0x3c83 # macro
mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX = 1 # macro
mmRLC_SPM_PERFMON_SEGMENT_SIZE = 0x3c84 # macro
mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX = 1 # macro
mmRLC_SPM_RING_RDPTR = 0x3c85 # macro
mmRLC_SPM_RING_RDPTR_BASE_IDX = 1 # macro
mmRLC_SPM_SEGMENT_THRESHOLD = 0x3c86 # macro
mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX = 1 # macro
mmRLC_SPM_SE_MUXSEL_ADDR = 0x3c87 # macro
mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX = 1 # macro
mmRLC_SPM_SE_MUXSEL_DATA = 0x3c88 # macro
mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX = 1 # macro
mmRLC_SPM_GLOBAL_MUXSEL_ADDR = 0x3c89 # macro
mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX = 1 # macro
mmRLC_SPM_GLOBAL_MUXSEL_DATA = 0x3c8a # macro
mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX = 1 # macro
mmRLC_SPM_DESER_START_SKEW = 0x3c8b # macro
mmRLC_SPM_DESER_START_SKEW_BASE_IDX = 1 # macro
mmRLC_SPM_GLOBALS_SAMPLE_SKEW = 0x3c8c # macro
mmRLC_SPM_GLOBALS_SAMPLE_SKEW_BASE_IDX = 1 # macro
mmRLC_SPM_GLOBALS_MUXSEL_SKEW = 0x3c8d # macro
mmRLC_SPM_GLOBALS_MUXSEL_SKEW_BASE_IDX = 1 # macro
mmRLC_SPM_SE_SAMPLE_SKEW = 0x3c8e # macro
mmRLC_SPM_SE_SAMPLE_SKEW_BASE_IDX = 1 # macro
mmRLC_SPM_SE_MUXSEL_SKEW = 0x3c8f # macro
mmRLC_SPM_SE_MUXSEL_SKEW_BASE_IDX = 1 # macro
mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR = 0x3c90 # macro
mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR_BASE_IDX = 1 # macro
mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA = 0x3c91 # macro
mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA_BASE_IDX = 1 # macro
mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR = 0x3c92 # macro
mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR_BASE_IDX = 1 # macro
mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA = 0x3c93 # macro
mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA_BASE_IDX = 1 # macro
mmRLC_SPM_RING_WRPTR = 0x3c94 # macro
mmRLC_SPM_RING_WRPTR_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_DATARAM_ADDR = 0x3c95 # macro
mmRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_DATARAM_DATA = 0x3c96 # macro
mmRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_CTRLRAM_ADDR = 0x3c97 # macro
mmRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_CTRLRAM_DATA = 0x3c98 # macro
mmRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_STATUS = 0x3c99 # macro
mmRLC_SPM_ACCUM_STATUS_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_CTRL = 0x3c9a # macro
mmRLC_SPM_ACCUM_CTRL_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_MODE = 0x3c9b # macro
mmRLC_SPM_ACCUM_MODE_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_THRESHOLD = 0x3c9c # macro
mmRLC_SPM_ACCUM_THRESHOLD_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_SAMPLES_REQUESTED = 0x3c9d # macro
mmRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_DATARAM_WRCOUNT = 0x3c9e # macro
mmRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX = 1 # macro
mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE = 0x3c9f # macro
mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE_BASE_IDX = 1 # macro
mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE = 0x3ca0 # macro
mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE_BASE_IDX = 1 # macro
mmRLC_SPM_VIRT_CTRL = 0x3ca1 # macro
mmRLC_SPM_VIRT_CTRL_BASE_IDX = 1 # macro
mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE = 0x3ca2 # macro
mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE_BASE_IDX = 1 # macro
mmRLC_SPM_VIRT_STATUS = 0x3ca3 # macro
mmRLC_SPM_VIRT_STATUS_BASE_IDX = 1 # macro
mmRLC_SPM_GFXCLOCK_HIGHCOUNT = 0x3ca4 # macro
mmRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX = 1 # macro
mmRLC_SPM_GFXCLOCK_LOWCOUNT = 0x3ca5 # macro
mmRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX = 1 # macro
mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE = 0x3ca6 # macro
mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE_BASE_IDX = 1 # macro
mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET = 0x3ca7 # macro
mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET_BASE_IDX = 1 # macro
mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET = 0x3ca8 # macro
mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR = 0x3ca9 # macro
mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_SWA_DATARAM_DATA = 0x3caa # macro
mmRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET = 0x3cab # macro
mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX = 1 # macro
mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE = 0x3cac # macro
mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE_BASE_IDX = 1 # macro
mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS = 0x3cad # macro
mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX = 1 # macro
mmRLC_PERFMON_CNTL = 0x3cc0 # macro
mmRLC_PERFMON_CNTL_BASE_IDX = 1 # macro
mmRLC_PERFCOUNTER0_SELECT = 0x3cc1 # macro
mmRLC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmRLC_PERFCOUNTER1_SELECT = 0x3cc2 # macro
mmRLC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_PERF_CNT_CNTL = 0x3cc3 # macro
mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_PERF_CNT_WR_ADDR = 0x3cc4 # macro
mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_PERF_CNT_WR_DATA = 0x3cc5 # macro
mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_PERF_CNT_RD_ADDR = 0x3cc6 # macro
mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_PERF_CNT_RD_DATA = 0x3cc7 # macro
mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX = 1 # macro
mmRLC_PERFMON_CLK_CNTL = 0x3ce4 # macro
mmRLC_PERFMON_CLK_CNTL_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER0_SELECT = 0x3d00 # macro
mmRMI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER0_SELECT1 = 0x3d01 # macro
mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER1_SELECT = 0x3d02 # macro
mmRMI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER2_SELECT = 0x3d03 # macro
mmRMI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER2_SELECT1 = 0x3d04 # macro
mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
mmRMI_PERFCOUNTER3_SELECT = 0x3d05 # macro
mmRMI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmRMI_PERF_COUNTER_CNTL = 0x3d06 # macro
mmRMI_PERF_COUNTER_CNTL_BASE_IDX = 1 # macro
mmGCR_PERFCOUNTER0_SELECT = 0x3d60 # macro
mmGCR_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmGCR_PERFCOUNTER0_SELECT1 = 0x3d61 # macro
mmGCR_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmGCR_PERFCOUNTER1_SELECT = 0x3d62 # macro
mmGCR_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmUTCL1_PERFCOUNTER0_SELECT = 0x3d63 # macro
mmUTCL1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmUTCL1_PERFCOUNTER1_SELECT = 0x3d64 # macro
mmUTCL1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER0_SELECT = 0x3d80 # macro
mmPA_PH_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER0_SELECT1 = 0x3d81 # macro
mmPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER1_SELECT = 0x3d82 # macro
mmPA_PH_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER2_SELECT = 0x3d83 # macro
mmPA_PH_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER3_SELECT = 0x3d84 # macro
mmPA_PH_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER4_SELECT = 0x3d85 # macro
mmPA_PH_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER5_SELECT = 0x3d86 # macro
mmPA_PH_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER6_SELECT = 0x3d87 # macro
mmPA_PH_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER7_SELECT = 0x3d88 # macro
mmPA_PH_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER1_SELECT1 = 0x3d90 # macro
mmPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER2_SELECT1 = 0x3d91 # macro
mmPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
mmPA_PH_PERFCOUNTER3_SELECT1 = 0x3d92 # macro
mmPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
mmGL1A_PERFCOUNTER0_SELECT = 0x3dc0 # macro
mmGL1A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmGL1A_PERFCOUNTER0_SELECT1 = 0x3dc1 # macro
mmGL1A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmGL1A_PERFCOUNTER1_SELECT = 0x3dc2 # macro
mmGL1A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmGL1A_PERFCOUNTER2_SELECT = 0x3dc3 # macro
mmGL1A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmGL1A_PERFCOUNTER3_SELECT = 0x3dc4 # macro
mmGL1A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmCHA_PERFCOUNTER0_SELECT = 0x3de0 # macro
mmCHA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmCHA_PERFCOUNTER0_SELECT1 = 0x3de1 # macro
mmCHA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmCHA_PERFCOUNTER1_SELECT = 0x3de2 # macro
mmCHA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmCHA_PERFCOUNTER2_SELECT = 0x3de3 # macro
mmCHA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmCHA_PERFCOUNTER3_SELECT = 0x3de4 # macro
mmCHA_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
mmGUS_PERFCOUNTER2_SELECT = 0x3e00 # macro
mmGUS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
mmGUS_PERFCOUNTER2_SELECT1 = 0x3e01 # macro
mmGUS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
mmGUS_PERFCOUNTER2_MODE = 0x3e02 # macro
mmGUS_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro
mmGUS_PERFCOUNTER0_CFG = 0x3e03 # macro
mmGUS_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
mmGUS_PERFCOUNTER1_CFG = 0x3e04 # macro
mmGUS_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
mmGUS_PERFCOUNTER_RSLT_CNTL = 0x3e05 # macro
mmGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
mmGCMC_VM_L2_PERFCOUNTER0_CFG = 0x3d2c # macro
mmGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
mmGCMC_VM_L2_PERFCOUNTER1_CFG = 0x3d2d # macro
mmGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
mmGCMC_VM_L2_PERFCOUNTER2_CFG = 0x3d2e # macro
mmGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro
mmGCMC_VM_L2_PERFCOUNTER3_CFG = 0x3d2f # macro
mmGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro
mmGCMC_VM_L2_PERFCOUNTER4_CFG = 0x3d30 # macro
mmGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX = 1 # macro
mmGCMC_VM_L2_PERFCOUNTER5_CFG = 0x3d31 # macro
mmGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX = 1 # macro
mmGCMC_VM_L2_PERFCOUNTER6_CFG = 0x3d32 # macro
mmGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX = 1 # macro
mmGCMC_VM_L2_PERFCOUNTER7_CFG = 0x3d33 # macro
mmGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX = 1 # macro
mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL = 0x3d34 # macro
mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
mmGCUTCL2_PERFCOUNTER0_CFG = 0x3d35 # macro
mmGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
mmGCUTCL2_PERFCOUNTER1_CFG = 0x3d36 # macro
mmGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
mmGCUTCL2_PERFCOUNTER2_CFG = 0x3d37 # macro
mmGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro
mmGCUTCL2_PERFCOUNTER3_CFG = 0x3d38 # macro
mmGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro
mmGCUTCL2_PERFCOUNTER_RSLT_CNTL = 0x3d39 # macro
mmGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
mmGCVML2_PERFCOUNTER2_0_SELECT = 0x3d3c # macro
mmGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX = 1 # macro
mmGCVML2_PERFCOUNTER2_1_SELECT = 0x3d3d # macro
mmGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX = 1 # macro
mmGCVML2_PERFCOUNTER2_0_SELECT1 = 0x3d3e # macro
mmGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX = 1 # macro
mmGCVML2_PERFCOUNTER2_1_SELECT1 = 0x3d3f # macro
mmGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX = 1 # macro
mmGCVML2_PERFCOUNTER2_0_MODE = 0x3d40 # macro
mmGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX = 1 # macro
mmGCVML2_PERFCOUNTER2_1_MODE = 0x3d41 # macro
mmGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX = 1 # macro
mmSDMA0_PERFCNT_PERFCOUNTER0_CFG = 0x3e20 # macro
mmSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
mmSDMA0_PERFCNT_PERFCOUNTER1_CFG = 0x3e21 # macro
mmSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e22 # macro
mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
mmSDMA0_PERFCNT_MISC_CNTL = 0x3e23 # macro
mmSDMA0_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro
mmSDMA0_PERFCOUNTER0_SELECT = 0x3e24 # macro
mmSDMA0_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmSDMA0_PERFCOUNTER0_SELECT1 = 0x3e25 # macro
mmSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmSDMA0_PERFCOUNTER1_SELECT = 0x3e26 # macro
mmSDMA0_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmSDMA0_PERFCOUNTER1_SELECT1 = 0x3e27 # macro
mmSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmSDMA1_PERFCNT_PERFCOUNTER0_CFG = 0x3e2c # macro
mmSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
mmSDMA1_PERFCNT_PERFCOUNTER1_CFG = 0x3e2d # macro
mmSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e2e # macro
mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
mmSDMA1_PERFCNT_MISC_CNTL = 0x3e2f # macro
mmSDMA1_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro
mmSDMA1_PERFCOUNTER0_SELECT = 0x3e30 # macro
mmSDMA1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmSDMA1_PERFCOUNTER0_SELECT1 = 0x3e31 # macro
mmSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmSDMA1_PERFCOUNTER1_SELECT = 0x3e32 # macro
mmSDMA1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmSDMA1_PERFCOUNTER1_SELECT1 = 0x3e33 # macro
mmSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmSDMA2_PERFCNT_PERFCOUNTER0_CFG = 0x3e38 # macro
mmSDMA2_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
mmSDMA2_PERFCNT_PERFCOUNTER1_CFG = 0x3e39 # macro
mmSDMA2_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e3a # macro
mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
mmSDMA2_PERFCNT_MISC_CNTL = 0x3e3b # macro
mmSDMA2_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro
mmSDMA2_PERFCOUNTER0_SELECT = 0x3e3c # macro
mmSDMA2_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmSDMA2_PERFCOUNTER0_SELECT1 = 0x3e3d # macro
mmSDMA2_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmSDMA2_PERFCOUNTER1_SELECT = 0x3e3e # macro
mmSDMA2_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmSDMA2_PERFCOUNTER1_SELECT1 = 0x3e3f # macro
mmSDMA2_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmSDMA3_PERFCNT_PERFCOUNTER0_CFG = 0x3e44 # macro
mmSDMA3_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
mmSDMA3_PERFCNT_PERFCOUNTER1_CFG = 0x3e45 # macro
mmSDMA3_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e46 # macro
mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
mmSDMA3_PERFCNT_MISC_CNTL = 0x3e47 # macro
mmSDMA3_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro
mmSDMA3_PERFCOUNTER0_SELECT = 0x3e48 # macro
mmSDMA3_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
mmSDMA3_PERFCOUNTER0_SELECT1 = 0x3e49 # macro
mmSDMA3_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
mmSDMA3_PERFCOUNTER1_SELECT = 0x3e4a # macro
mmSDMA3_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
mmSDMA3_PERFCOUNTER1_SELECT1 = 0x3e4b # macro
mmSDMA3_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
mmGRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro
mmGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro
mmRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro
mmRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro
mmGRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro
mmGRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro
mmRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro
mmRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro
mmGRTAVFS_GENERAL_0 = 0x4b02 # macro
mmGRTAVFS_GENERAL_0_BASE_IDX = 1 # macro
mmGRTAVFS_RTAVFS_RD_DATA = 0x4b03 # macro
mmGRTAVFS_RTAVFS_RD_DATA_BASE_IDX = 1 # macro
mmGRTAVFS_RTAVFS_REG_CTRL = 0x4b04 # macro
mmGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX = 1 # macro
mmGRTAVFS_RTAVFS_REG_STATUS = 0x4b05 # macro
mmGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX = 1 # macro
mmGRTAVFS_TARG_FREQ = 0x4b06 # macro
mmGRTAVFS_TARG_FREQ_BASE_IDX = 1 # macro
mmGRTAVFS_TARG_VOLT = 0x4b07 # macro
mmGRTAVFS_TARG_VOLT_BASE_IDX = 1 # macro
mmGRTAVFS_SOFT_RESET = 0x4b0f # macro
mmGRTAVFS_SOFT_RESET_BASE_IDX = 1 # macro
mmGRTAVFS_PSM_CNTL = 0x4b10 # macro
mmGRTAVFS_PSM_CNTL_BASE_IDX = 1 # macro
mmGRTAVFS_CLK_CNTL = 0x4b11 # macro
mmGRTAVFS_CLK_CNTL_BASE_IDX = 1 # macro
mmRLC_CNTL = 0x4c00 # macro
mmRLC_CNTL_BASE_IDX = 1 # macro
mmRLC_F32_UCODE_VERSION = 0x4c03 # macro
mmRLC_F32_UCODE_VERSION_BASE_IDX = 1 # macro
mmRLC_STAT = 0x4c04 # macro
mmRLC_STAT_BASE_IDX = 1 # macro
mmRLC_MEM_SLP_CNTL = 0x4c06 # macro
mmRLC_MEM_SLP_CNTL_BASE_IDX = 1 # macro
mmSMU_RLC_RESPONSE = 0x4c07 # macro
mmSMU_RLC_RESPONSE_BASE_IDX = 1 # macro
mmRLC_RLCV_SAFE_MODE = 0x4c08 # macro
mmRLC_RLCV_SAFE_MODE_BASE_IDX = 1 # macro
mmRLC_SMU_SAFE_MODE = 0x4c09 # macro
mmRLC_SMU_SAFE_MODE_BASE_IDX = 1 # macro
mmRLC_RLCV_COMMAND = 0x4c0a # macro
mmRLC_RLCV_COMMAND_BASE_IDX = 1 # macro
mmRLC_REFCLOCK_TIMESTAMP_LSB = 0x4c0c # macro
mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX = 1 # macro
mmRLC_REFCLOCK_TIMESTAMP_MSB = 0x4c0d # macro
mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX = 1 # macro
mmRLC_GPM_TIMER_INT_0 = 0x4c0e # macro
mmRLC_GPM_TIMER_INT_0_BASE_IDX = 1 # macro
mmRLC_GPM_TIMER_INT_1 = 0x4c0f # macro
mmRLC_GPM_TIMER_INT_1_BASE_IDX = 1 # macro
mmRLC_GPM_TIMER_INT_2 = 0x4c10 # macro
mmRLC_GPM_TIMER_INT_2_BASE_IDX = 1 # macro
mmRLC_GPM_TIMER_CTRL = 0x4c11 # macro
mmRLC_GPM_TIMER_CTRL_BASE_IDX = 1 # macro
mmRLC_LB_CNTR_MAX_1 = 0x4c12 # macro
mmRLC_LB_CNTR_MAX_1_BASE_IDX = 1 # macro
mmRLC_GPM_TIMER_STAT = 0x4c13 # macro
mmRLC_GPM_TIMER_STAT_BASE_IDX = 1 # macro
mmRLC_GPM_TIMER_INT_3 = 0x4c15 # macro
mmRLC_GPM_TIMER_INT_3_BASE_IDX = 1 # macro
mmRLC_GPM_LEGACY_INT_STAT = 0x4c16 # macro
mmRLC_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro
mmRLC_GPM_LEGACY_INT_CLEAR = 0x4c17 # macro
mmRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX = 1 # macro
mmRLC_INT_STAT = 0x4c18 # macro
mmRLC_INT_STAT_BASE_IDX = 1 # macro
mmRLC_LB_CNTL = 0x4c19 # macro
mmRLC_LB_CNTL_BASE_IDX = 1 # macro
mmRLC_MGCG_CTRL = 0x4c1a # macro
mmRLC_MGCG_CTRL_BASE_IDX = 1 # macro
mmRLC_LB_CNTR_INIT_1 = 0x4c1b # macro
mmRLC_LB_CNTR_INIT_1_BASE_IDX = 1 # macro
mmRLC_LB_CNTR_1 = 0x4c1c # macro
mmRLC_LB_CNTR_1_BASE_IDX = 1 # macro
mmRLC_JUMP_TABLE_RESTORE = 0x4c1e # macro
mmRLC_JUMP_TABLE_RESTORE_BASE_IDX = 1 # macro
mmRLC_PG_DELAY_2 = 0x4c1f # macro
mmRLC_PG_DELAY_2_BASE_IDX = 1 # macro
mmRLC_GPU_CLOCK_COUNT_LSB = 0x4c24 # macro
mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX = 1 # macro
mmRLC_GPU_CLOCK_COUNT_MSB = 0x4c25 # macro
mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX = 1 # macro
mmRLC_CAPTURE_GPU_CLOCK_COUNT = 0x4c26 # macro
mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX = 1 # macro
mmRLC_UCODE_CNTL = 0x4c27 # macro
mmRLC_UCODE_CNTL_BASE_IDX = 1 # macro
mmRLC_GPM_THREAD_RESET = 0x4c28 # macro
mmRLC_GPM_THREAD_RESET_BASE_IDX = 1 # macro
mmRLC_GPM_CP_DMA_COMPLETE_T0 = 0x4c29 # macro
mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX = 1 # macro
mmRLC_GPM_CP_DMA_COMPLETE_T1 = 0x4c2a # macro
mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX = 1 # macro
mmRLC_LB_CNTR_INIT_2 = 0x4c2b # macro
mmRLC_LB_CNTR_INIT_2_BASE_IDX = 1 # macro
mmRLC_LB_CNTR_MAX_2 = 0x4c2c # macro
mmRLC_LB_CNTR_MAX_2_BASE_IDX = 1 # macro
mmRLC_LB_CONFIG_5 = 0x4c2e # macro
mmRLC_LB_CONFIG_5_BASE_IDX = 1 # macro
mmRLC_GPM_TIMER_INT_4 = 0x4c2f # macro
mmRLC_GPM_TIMER_INT_4_BASE_IDX = 1 # macro
mmRLC_CLK_COUNT_GFXCLK_LSB = 0x4c30 # macro
mmRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX = 1 # macro
mmRLC_CLK_COUNT_GFXCLK_MSB = 0x4c31 # macro
mmRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX = 1 # macro
mmRLC_CLK_COUNT_REFCLK_LSB = 0x4c32 # macro
mmRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX = 1 # macro
mmRLC_CLK_COUNT_REFCLK_MSB = 0x4c33 # macro
mmRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX = 1 # macro
mmRLC_CLK_COUNT_CTRL = 0x4c34 # macro
mmRLC_CLK_COUNT_CTRL_BASE_IDX = 1 # macro
mmRLC_CLK_COUNT_STAT = 0x4c35 # macro
mmRLC_CLK_COUNT_STAT_BASE_IDX = 1 # macro
mmRLC_RLCG_DOORBELL_CNTL = 0x4c36 # macro
mmRLC_RLCG_DOORBELL_CNTL_BASE_IDX = 1 # macro
mmRLC_RLCG_DOORBELL_STAT = 0x4c37 # macro
mmRLC_RLCG_DOORBELL_STAT_BASE_IDX = 1 # macro
mmRLC_RLCG_DOORBELL_0_DATA_LO = 0x4c38 # macro
mmRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro
mmRLC_RLCG_DOORBELL_0_DATA_HI = 0x4c39 # macro
mmRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro
mmRLC_RLCG_DOORBELL_1_DATA_LO = 0x4c3a # macro
mmRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro
mmRLC_RLCG_DOORBELL_1_DATA_HI = 0x4c3b # macro
mmRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro
mmRLC_RLCG_DOORBELL_2_DATA_LO = 0x4c3c # macro
mmRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro
mmRLC_RLCG_DOORBELL_2_DATA_HI = 0x4c3d # macro
mmRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro
mmRLC_RLCG_DOORBELL_3_DATA_LO = 0x4c3e # macro
mmRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro
mmRLC_RLCG_DOORBELL_3_DATA_HI = 0x4c3f # macro
mmRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro
mmRLC_GPU_CLOCK_32_RES_SEL = 0x4c41 # macro
mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX = 1 # macro
mmRLC_GPU_CLOCK_32 = 0x4c42 # macro
mmRLC_GPU_CLOCK_32_BASE_IDX = 1 # macro
mmRLC_PG_CNTL = 0x4c43 # macro
mmRLC_PG_CNTL_BASE_IDX = 1 # macro
mmRLC_GPM_THREAD_PRIORITY = 0x4c44 # macro
mmRLC_GPM_THREAD_PRIORITY_BASE_IDX = 1 # macro
mmRLC_GPM_THREAD_ENABLE = 0x4c45 # macro
mmRLC_GPM_THREAD_ENABLE_BASE_IDX = 1 # macro
mmRLC_RLCG_DOORBELL_RANGE = 0x4c47 # macro
mmRLC_RLCG_DOORBELL_RANGE_BASE_IDX = 1 # macro
mmRLC_CGTT_MGCG_OVERRIDE = 0x4c48 # macro
mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX = 1 # macro
mmRLC_CGCG_CGLS_CTRL = 0x4c49 # macro
mmRLC_CGCG_CGLS_CTRL_BASE_IDX = 1 # macro
mmRLC_CGCG_RAMP_CTRL = 0x4c4a # macro
mmRLC_CGCG_RAMP_CTRL_BASE_IDX = 1 # macro
mmRLC_DYN_PG_STATUS = 0x4c4b # macro
mmRLC_DYN_PG_STATUS_BASE_IDX = 1 # macro
mmRLC_DYN_PG_REQUEST = 0x4c4c # macro
mmRLC_DYN_PG_REQUEST_BASE_IDX = 1 # macro
mmRLC_PG_DELAY = 0x4c4d # macro
mmRLC_PG_DELAY_BASE_IDX = 1 # macro
mmRLC_WGP_STATUS = 0x4c4e # macro
mmRLC_WGP_STATUS_BASE_IDX = 1 # macro
mmRLC_LB_INIT_WGP_MASK = 0x4c4f # macro
mmRLC_LB_INIT_WGP_MASK_BASE_IDX = 1 # macro
mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK = 0x4c50 # macro
mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK_BASE_IDX = 1 # macro
mmRLC_LB_PARAMS = 0x4c51 # macro
mmRLC_LB_PARAMS_BASE_IDX = 1 # macro
mmRLC_LB_DELAY = 0x4c52 # macro
mmRLC_LB_DELAY_BASE_IDX = 1 # macro
mmRLC_PG_ALWAYS_ON_WGP_MASK = 0x4c53 # macro
mmRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX = 1 # macro
mmRLC_MAX_PG_WGP = 0x4c54 # macro
mmRLC_MAX_PG_WGP_BASE_IDX = 1 # macro
mmRLC_AUTO_PG_CTRL = 0x4c55 # macro
mmRLC_AUTO_PG_CTRL_BASE_IDX = 1 # macro
mmRLC_SMU_GRBM_REG_SAVE_CTRL = 0x4c56 # macro
mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX = 1 # macro
mmRLC_SERDES_RD_INDEX = 0x4c59 # macro
mmRLC_SERDES_RD_INDEX_BASE_IDX = 1 # macro
mmRLC_SERDES_RD_DATA_0 = 0x4c5a # macro
mmRLC_SERDES_RD_DATA_0_BASE_IDX = 1 # macro
mmRLC_SERDES_RD_DATA_1 = 0x4c5b # macro
mmRLC_SERDES_RD_DATA_1_BASE_IDX = 1 # macro
mmRLC_SERDES_RD_DATA_2 = 0x4c5c # macro
mmRLC_SERDES_RD_DATA_2_BASE_IDX = 1 # macro
mmRLC_SERDES_RD_DATA_3 = 0x4c5d # macro
mmRLC_SERDES_RD_DATA_3_BASE_IDX = 1 # macro
mmRLC_SERDES_MASK = 0x4c5e # macro
mmRLC_SERDES_MASK_BASE_IDX = 1 # macro
mmRLC_SERDES_CTRL = 0x4c5f # macro
mmRLC_SERDES_CTRL_BASE_IDX = 1 # macro
mmRLC_SERDES_DATA = 0x4c60 # macro
mmRLC_SERDES_DATA_BASE_IDX = 1 # macro
mmRLC_SERDES_BUSY = 0x4c61 # macro
mmRLC_SERDES_BUSY_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_0 = 0x4c63 # macro
mmRLC_GPM_GENERAL_0_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_1 = 0x4c64 # macro
mmRLC_GPM_GENERAL_1_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_2 = 0x4c65 # macro
mmRLC_GPM_GENERAL_2_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_3 = 0x4c66 # macro
mmRLC_GPM_GENERAL_3_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_4 = 0x4c67 # macro
mmRLC_GPM_GENERAL_4_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_5 = 0x4c68 # macro
mmRLC_GPM_GENERAL_5_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_6 = 0x4c69 # macro
mmRLC_GPM_GENERAL_6_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_7 = 0x4c6a # macro
mmRLC_GPM_GENERAL_7_BASE_IDX = 1 # macro
mmRLC_STATIC_PG_STATUS = 0x4c6e # macro
mmRLC_STATIC_PG_STATUS_BASE_IDX = 1 # macro
mmRLC_SPM_INT_INFO_1 = 0x4c6f # macro
mmRLC_SPM_INT_INFO_1_BASE_IDX = 1 # macro
mmRLC_SPM_INT_INFO_2 = 0x4c70 # macro
mmRLC_SPM_INT_INFO_2_BASE_IDX = 1 # macro
mmRLC_SPM_MC_CNTL = 0x4c71 # macro
mmRLC_SPM_MC_CNTL_BASE_IDX = 1 # macro
mmRLC_SPM_INT_CNTL = 0x4c72 # macro
mmRLC_SPM_INT_CNTL_BASE_IDX = 1 # macro
mmRLC_SPM_INT_STATUS = 0x4c73 # macro
mmRLC_SPM_INT_STATUS_BASE_IDX = 1 # macro
mmRLC_SMU_MESSAGE = 0x4c76 # macro
mmRLC_SMU_MESSAGE_BASE_IDX = 1 # macro
mmRLC_GPM_LOG_SIZE = 0x4c77 # macro
mmRLC_GPM_LOG_SIZE_BASE_IDX = 1 # macro
mmRLC_PG_DELAY_3 = 0x4c78 # macro
mmRLC_PG_DELAY_3_BASE_IDX = 1 # macro
mmRLC_GPR_REG1 = 0x4c79 # macro
mmRLC_GPR_REG1_BASE_IDX = 1 # macro
mmRLC_GPR_REG2 = 0x4c7a # macro
mmRLC_GPR_REG2_BASE_IDX = 1 # macro
mmRLC_GPM_LOG_CONT = 0x4c7b # macro
mmRLC_GPM_LOG_CONT_BASE_IDX = 1 # macro
mmRLC_GPM_INT_DISABLE_TH0 = 0x4c7c # macro
mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX = 1 # macro
mmRLC_GPM_LEGACY_INT_DISABLE = 0x4c7d # macro
mmRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro
mmRLC_GPM_INT_FORCE_TH0 = 0x4c7e # macro
mmRLC_GPM_INT_FORCE_TH0_BASE_IDX = 1 # macro
mmRLC_SRM_CNTL = 0x4c80 # macro
mmRLC_SRM_CNTL_BASE_IDX = 1 # macro
mmRLC_SRM_GPM_COMMAND = 0x4c87 # macro
mmRLC_SRM_GPM_COMMAND_BASE_IDX = 1 # macro
mmRLC_SRM_GPM_COMMAND_STATUS = 0x4c88 # macro
mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX = 1 # macro
mmRLC_SRM_RLCV_COMMAND = 0x4c89 # macro
mmRLC_SRM_RLCV_COMMAND_BASE_IDX = 1 # macro
mmRLC_SRM_RLCV_COMMAND_STATUS = 0x4c8a # macro
mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_ADDR_0 = 0x4c8b # macro
mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_ADDR_1 = 0x4c8c # macro
mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_ADDR_2 = 0x4c8d # macro
mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_ADDR_3 = 0x4c8e # macro
mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_ADDR_4 = 0x4c8f # macro
mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_ADDR_5 = 0x4c90 # macro
mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_ADDR_6 = 0x4c91 # macro
mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_ADDR_7 = 0x4c92 # macro
mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_DATA_0 = 0x4c93 # macro
mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_DATA_1 = 0x4c94 # macro
mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_DATA_2 = 0x4c95 # macro
mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_DATA_3 = 0x4c96 # macro
mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_DATA_4 = 0x4c97 # macro
mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_DATA_5 = 0x4c98 # macro
mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_DATA_6 = 0x4c99 # macro
mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX = 1 # macro
mmRLC_SRM_INDEX_CNTL_DATA_7 = 0x4c9a # macro
mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX = 1 # macro
mmRLC_SRM_STAT = 0x4c9b # macro
mmRLC_SRM_STAT_BASE_IDX = 1 # macro
mmRLC_SRM_GPM_ABORT = 0x4c9c # macro
mmRLC_SRM_GPM_ABORT_BASE_IDX = 1 # macro
mmRLC_SPARE_INT_2 = 0x4c9d # macro
mmRLC_SPARE_INT_2_BASE_IDX = 1 # macro
mmRLC_RLCV_SPARE_INT_1 = 0x4c9e # macro
mmRLC_RLCV_SPARE_INT_1_BASE_IDX = 1 # macro
mmRLC_PACE_SPARE_INT_1 = 0x4c9f # macro
mmRLC_PACE_SPARE_INT_1_BASE_IDX = 1 # macro
mmRLC_SAFE_MODE = 0x4ca0 # macro
mmRLC_SAFE_MODE_BASE_IDX = 1 # macro
mmRLC_CP_SCHEDULERS = 0x4ca1 # macro
mmRLC_CP_SCHEDULERS_BASE_IDX = 1 # macro
mmRLC_CSIB_ADDR_LO = 0x4ca2 # macro
mmRLC_CSIB_ADDR_LO_BASE_IDX = 1 # macro
mmRLC_CSIB_ADDR_HI = 0x4ca3 # macro
mmRLC_CSIB_ADDR_HI_BASE_IDX = 1 # macro
mmRLC_CSIB_LENGTH = 0x4ca4 # macro
mmRLC_CSIB_LENGTH_BASE_IDX = 1 # macro
mmRLC_SPARE_INT_0 = 0x4ca5 # macro
mmRLC_SPARE_INT_0_BASE_IDX = 1 # macro
mmRLC_CP_EOF_INT_CNT = 0x4ca6 # macro
mmRLC_CP_EOF_INT_CNT_BASE_IDX = 1 # macro
mmRLC_CP_EOF_INT = 0x4ca7 # macro
mmRLC_CP_EOF_INT_BASE_IDX = 1 # macro
mmRLC_SMU_COMMAND = 0x4ca9 # macro
mmRLC_SMU_COMMAND_BASE_IDX = 1 # macro
mmRLC_SMU_ARGUMENT_1 = 0x4cab # macro
mmRLC_SMU_ARGUMENT_1_BASE_IDX = 1 # macro
mmRLC_SMU_ARGUMENT_2 = 0x4cac # macro
mmRLC_SMU_ARGUMENT_2_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_8 = 0x4cad # macro
mmRLC_GPM_GENERAL_8_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_9 = 0x4cae # macro
mmRLC_GPM_GENERAL_9_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_10 = 0x4caf # macro
mmRLC_GPM_GENERAL_10_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_11 = 0x4cb0 # macro
mmRLC_GPM_GENERAL_11_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_12 = 0x4cb1 # macro
mmRLC_GPM_GENERAL_12_BASE_IDX = 1 # macro
mmRLC_GPM_UTCL1_CNTL_0 = 0x4cb2 # macro
mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX = 1 # macro
mmRLC_GPM_UTCL1_CNTL_1 = 0x4cb3 # macro
mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX = 1 # macro
mmRLC_GPM_UTCL1_CNTL_2 = 0x4cb4 # macro
mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX = 1 # macro
mmRLC_SPM_UTCL1_CNTL = 0x4cb5 # macro
mmRLC_SPM_UTCL1_CNTL_BASE_IDX = 1 # macro
mmRLC_UTCL1_STATUS_2 = 0x4cb6 # macro
mmRLC_UTCL1_STATUS_2_BASE_IDX = 1 # macro
mmRLC_LB_CONFIG_2 = 0x4cb8 # macro
mmRLC_LB_CONFIG_2_BASE_IDX = 1 # macro
mmRLC_LB_CONFIG_3 = 0x4cb9 # macro
mmRLC_LB_CONFIG_3_BASE_IDX = 1 # macro
mmRLC_LB_CONFIG_4 = 0x4cba # macro
mmRLC_LB_CONFIG_4_BASE_IDX = 1 # macro
mmRLC_SPM_UTCL1_ERROR_1 = 0x4cbc # macro
mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX = 1 # macro
mmRLC_SPM_UTCL1_ERROR_2 = 0x4cbd # macro
mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX = 1 # macro
mmRLC_GPM_UTCL1_TH0_ERROR_1 = 0x4cbe # macro
mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX = 1 # macro
mmRLC_LB_CONFIG_1 = 0x4cbf # macro
mmRLC_LB_CONFIG_1_BASE_IDX = 1 # macro
mmRLC_GPM_UTCL1_TH0_ERROR_2 = 0x4cc0 # macro
mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX = 1 # macro
mmRLC_GPM_UTCL1_TH1_ERROR_1 = 0x4cc1 # macro
mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX = 1 # macro
mmRLC_GPM_UTCL1_TH1_ERROR_2 = 0x4cc2 # macro
mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX = 1 # macro
mmRLC_GPM_UTCL1_TH2_ERROR_1 = 0x4cc3 # macro
mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX = 1 # macro
mmRLC_GPM_UTCL1_TH2_ERROR_2 = 0x4cc4 # macro
mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX = 1 # macro
mmRLC_CGCG_CGLS_CTRL_3D = 0x4cc5 # macro
mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX = 1 # macro
mmRLC_CGCG_RAMP_CTRL_3D = 0x4cc6 # macro
mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX = 1 # macro
mmRLC_SEMAPHORE_0 = 0x4cc7 # macro
mmRLC_SEMAPHORE_0_BASE_IDX = 1 # macro
mmRLC_SEMAPHORE_1 = 0x4cc8 # macro
mmRLC_SEMAPHORE_1_BASE_IDX = 1 # macro
mmRLC_PACE_INT_STAT = 0x4ccc # macro
mmRLC_PACE_INT_STAT_BASE_IDX = 1 # macro
mmRLC_PREWALKER_UTCL1_CNTL = 0x4ccd # macro
mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX = 1 # macro
mmRLC_PREWALKER_UTCL1_TRIG = 0x4cce # macro
mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX = 1 # macro
mmRLC_PREWALKER_UTCL1_ADDR_LSB = 0x4ccf # macro
mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX = 1 # macro
mmRLC_PREWALKER_UTCL1_ADDR_MSB = 0x4cd0 # macro
mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX = 1 # macro
mmRLC_PREWALKER_UTCL1_SIZE_LSB = 0x4cd1 # macro
mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX = 1 # macro
mmRLC_PREWALKER_UTCL1_SIZE_MSB = 0x4cd2 # macro
mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX = 1 # macro
mmRLC_UTCL1_STATUS = 0x4cd4 # macro
mmRLC_UTCL1_STATUS_BASE_IDX = 1 # macro
mmRLC_R2I_CNTL_0 = 0x4cd5 # macro
mmRLC_R2I_CNTL_0_BASE_IDX = 1 # macro
mmRLC_R2I_CNTL_1 = 0x4cd6 # macro
mmRLC_R2I_CNTL_1_BASE_IDX = 1 # macro
mmRLC_R2I_CNTL_2 = 0x4cd7 # macro
mmRLC_R2I_CNTL_2_BASE_IDX = 1 # macro
mmRLC_R2I_CNTL_3 = 0x4cd8 # macro
mmRLC_R2I_CNTL_3_BASE_IDX = 1 # macro
mmRLC_LB_WGP_STAT = 0x4cda # macro
mmRLC_LB_WGP_STAT_BASE_IDX = 1 # macro
mmRLC_GPM_INT_STAT_TH0 = 0x4cdc # macro
mmRLC_GPM_INT_STAT_TH0_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_13 = 0x4cdd # macro
mmRLC_GPM_GENERAL_13_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_14 = 0x4cde # macro
mmRLC_GPM_GENERAL_14_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_15 = 0x4cdf # macro
mmRLC_GPM_GENERAL_15_BASE_IDX = 1 # macro
mmRLC_SPARE_INT_1 = 0x4ce0 # macro
mmRLC_SPARE_INT_1_BASE_IDX = 1 # macro
mmRLC_SEMAPHORE_2 = 0x4ce3 # macro
mmRLC_SEMAPHORE_2_BASE_IDX = 1 # macro
mmRLC_SEMAPHORE_3 = 0x4ce4 # macro
mmRLC_SEMAPHORE_3_BASE_IDX = 1 # macro
mmRLC_SMU_ARGUMENT_3 = 0x4ce5 # macro
mmRLC_SMU_ARGUMENT_3_BASE_IDX = 1 # macro
mmRLC_SMU_ARGUMENT_4 = 0x4ce6 # macro
mmRLC_SMU_ARGUMENT_4_BASE_IDX = 1 # macro
mmRLC_GPU_CLOCK_COUNT_LSB_1 = 0x4ce8 # macro
mmRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX = 1 # macro
mmRLC_GPU_CLOCK_COUNT_MSB_1 = 0x4ce9 # macro
mmRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX = 1 # macro
mmRLC_CAPTURE_GPU_CLOCK_COUNT_1 = 0x4cea # macro
mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX = 1 # macro
mmRLC_GPU_CLOCK_COUNT_LSB_2 = 0x4ceb # macro
mmRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX = 1 # macro
mmRLC_GPU_CLOCK_COUNT_MSB_2 = 0x4cec # macro
mmRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX = 1 # macro
mmRLC_PACE_INT_DISABLE = 0x4ced # macro
mmRLC_PACE_INT_DISABLE_BASE_IDX = 1 # macro
mmRLC_CAPTURE_GPU_CLOCK_COUNT_2 = 0x4cef # macro
mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX = 1 # macro
mmRLC_RLCV_DOORBELL_RANGE = 0x4cf0 # macro
mmRLC_RLCV_DOORBELL_RANGE_BASE_IDX = 1 # macro
mmRLC_RLCV_DOORBELL_CNTL = 0x4cf1 # macro
mmRLC_RLCV_DOORBELL_CNTL_BASE_IDX = 1 # macro
mmRLC_RLCV_DOORBELL_STAT = 0x4cf2 # macro
mmRLC_RLCV_DOORBELL_STAT_BASE_IDX = 1 # macro
mmRLC_RLCV_DOORBELL_0_DATA_LO = 0x4cf3 # macro
mmRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro
mmRLC_RLCV_DOORBELL_0_DATA_HI = 0x4cf4 # macro
mmRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro
mmRLC_RLCV_DOORBELL_1_DATA_LO = 0x4cf5 # macro
mmRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro
mmRLC_RLCV_DOORBELL_1_DATA_HI = 0x4cf6 # macro
mmRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro
mmRLC_RLCV_DOORBELL_2_DATA_LO = 0x4cf7 # macro
mmRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro
mmRLC_RLCV_DOORBELL_2_DATA_HI = 0x4cf8 # macro
mmRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro
mmRLC_RLCV_DOORBELL_3_DATA_LO = 0x4cf9 # macro
mmRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro
mmRLC_RLCV_DOORBELL_3_DATA_HI = 0x4cfa # macro
mmRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro
mmRLC_RLCV_SPARE_INT = 0x4d00 # macro
mmRLC_RLCV_SPARE_INT_BASE_IDX = 1 # macro
mmRLC_PACE_TIMER_INT_0 = 0x4d04 # macro
mmRLC_PACE_TIMER_INT_0_BASE_IDX = 1 # macro
mmRLC_PACE_TIMER_CTRL = 0x4d05 # macro
mmRLC_PACE_TIMER_CTRL_BASE_IDX = 1 # macro
mmRLC_PACE_TIMER_INT_1 = 0x4d06 # macro
mmRLC_PACE_TIMER_INT_1_BASE_IDX = 1 # macro
mmRLC_PACE_SPARE_INT = 0x4d07 # macro
mmRLC_PACE_SPARE_INT_BASE_IDX = 1 # macro
mmRLC_SMU_CLK_REQ = 0x4d08 # macro
mmRLC_SMU_CLK_REQ_BASE_IDX = 1 # macro
mmRLC_CP_STAT_INVAL_STAT = 0x4d09 # macro
mmRLC_CP_STAT_INVAL_STAT_BASE_IDX = 1 # macro
mmRLC_CP_STAT_INVAL_CTRL = 0x4d0a # macro
mmRLC_CP_STAT_INVAL_CTRL_BASE_IDX = 1 # macro
mmRLC_CLK_STATUS = 0x4d0b # macro
mmRLC_CLK_STATUS_BASE_IDX = 1 # macro
mmRLC_SPP_CTRL = 0x4d0c # macro
mmRLC_SPP_CTRL_BASE_IDX = 1 # macro
mmRLC_SPP_SHADER_PROFILE_EN = 0x4d0d # macro
mmRLC_SPP_SHADER_PROFILE_EN_BASE_IDX = 1 # macro
mmRLC_SPP_SSF_CAPTURE_EN = 0x4d0e # macro
mmRLC_SPP_SSF_CAPTURE_EN_BASE_IDX = 1 # macro
mmRLC_SPP_SSF_THRESHOLD_0 = 0x4d0f # macro
mmRLC_SPP_SSF_THRESHOLD_0_BASE_IDX = 1 # macro
mmRLC_SPP_SSF_THRESHOLD_1 = 0x4d10 # macro
mmRLC_SPP_SSF_THRESHOLD_1_BASE_IDX = 1 # macro
mmRLC_SPP_SSF_THRESHOLD_2 = 0x4d11 # macro
mmRLC_SPP_SSF_THRESHOLD_2_BASE_IDX = 1 # macro
mmRLC_SPP_INFLIGHT_RD_ADDR = 0x4d12 # macro
mmRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX = 1 # macro
mmRLC_SPP_INFLIGHT_RD_DATA = 0x4d13 # macro
mmRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX = 1 # macro
mmRLC_GPM_GENERAL_16 = 0x4d14 # macro
mmRLC_GPM_GENERAL_16_BASE_IDX = 1 # macro
mmRLC_SPP_PROF_INFO_1 = 0x4d18 # macro
mmRLC_SPP_PROF_INFO_1_BASE_IDX = 1 # macro
mmRLC_SPP_PROF_INFO_2 = 0x4d19 # macro
mmRLC_SPP_PROF_INFO_2_BASE_IDX = 1 # macro
mmRLC_SPP_GLOBAL_SH_ID = 0x4d1a # macro
mmRLC_SPP_GLOBAL_SH_ID_BASE_IDX = 1 # macro
mmRLC_SPP_GLOBAL_SH_ID_VALID = 0x4d1b # macro
mmRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX = 1 # macro
mmRLC_SPP_STATUS = 0x4d1c # macro
mmRLC_SPP_STATUS_BASE_IDX = 1 # macro
mmRLC_SPP_PVT_STAT_0 = 0x4d1d # macro
mmRLC_SPP_PVT_STAT_0_BASE_IDX = 1 # macro
mmRLC_SPP_PVT_STAT_1 = 0x4d1e # macro
mmRLC_SPP_PVT_STAT_1_BASE_IDX = 1 # macro
mmRLC_SPP_PVT_STAT_2 = 0x4d1f # macro
mmRLC_SPP_PVT_STAT_2_BASE_IDX = 1 # macro
mmRLC_SPP_PVT_STAT_3 = 0x4d20 # macro
mmRLC_SPP_PVT_STAT_3_BASE_IDX = 1 # macro
mmRLC_SPP_PVT_LEVEL_MAX = 0x4d21 # macro
mmRLC_SPP_PVT_LEVEL_MAX_BASE_IDX = 1 # macro
mmRLC_SPP_STALL_STATE_UPDATE = 0x4d22 # macro
mmRLC_SPP_STALL_STATE_UPDATE_BASE_IDX = 1 # macro
mmRLC_SPP_PBB_INFO = 0x4d23 # macro
mmRLC_SPP_PBB_INFO_BASE_IDX = 1 # macro
mmRLC_SPP_RESET = 0x4d24 # macro
mmRLC_SPP_RESET_BASE_IDX = 1 # macro
mmRLC_SPM_SAMPLE_CNT = 0x4d25 # macro
mmRLC_SPM_SAMPLE_CNT_BASE_IDX = 1 # macro
mmRLC_RLCP_DOORBELL_RANGE = 0x4d26 # macro
mmRLC_RLCP_DOORBELL_RANGE_BASE_IDX = 1 # macro
mmRLC_RLCP_DOORBELL_CNTL = 0x4d27 # macro
mmRLC_RLCP_DOORBELL_CNTL_BASE_IDX = 1 # macro
mmRLC_RLCP_DOORBELL_STAT = 0x4d28 # macro
mmRLC_RLCP_DOORBELL_STAT_BASE_IDX = 1 # macro
mmRLC_RLCP_DOORBELL_0_DATA_LO = 0x4d29 # macro
mmRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro
mmRLC_RLCP_DOORBELL_0_DATA_HI = 0x4d2a # macro
mmRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro
mmRLC_RLCP_DOORBELL_1_DATA_LO = 0x4d2b # macro
mmRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro
mmRLC_RLCP_DOORBELL_1_DATA_HI = 0x4d2c # macro
mmRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro
mmRLC_RLCP_DOORBELL_2_DATA_LO = 0x4d2d # macro
mmRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro
mmRLC_RLCP_DOORBELL_2_DATA_HI = 0x4d2e # macro
mmRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro
mmRLC_RLCP_DOORBELL_3_DATA_LO = 0x4d2f # macro
mmRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro
mmRLC_RLCP_DOORBELL_3_DATA_HI = 0x4d30 # macro
mmRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro
mmRLC_PCC_STRETCH_HYSTERESIS_CNTL = 0x4d44 # macro
mmRLC_PCC_STRETCH_HYSTERESIS_CNTL_BASE_IDX = 1 # macro
mmRLC_CAC_MASK_CNTL = 0x4d45 # macro
mmRLC_CAC_MASK_CNTL_BASE_IDX = 1 # macro
mmRLC_GPU_CLOCK_COUNT_SPM_LSB = 0x4de4 # macro
mmRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX = 1 # macro
mmRLC_GPU_CLOCK_COUNT_SPM_MSB = 0x4de5 # macro
mmRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX = 1 # macro
mmRLC_SPM_THREAD_TRACE_CTRL = 0x4de6 # macro
mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro
mmRLC_LB_CNTR_2 = 0x4de7 # macro
mmRLC_LB_CNTR_2_BASE_IDX = 1 # macro
mmRLC_CPAXI_DOORBELL_MON_CTRL = 0x4df1 # macro
mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX = 1 # macro
mmRLC_CPAXI_DOORBELL_MON_STAT = 0x4df2 # macro
mmRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX = 1 # macro
mmRLC_CPAXI_DOORBELL_MON_DATA_LSB = 0x4df3 # macro
mmRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX = 1 # macro
mmRLC_CPAXI_DOORBELL_MON_DATA_MSB = 0x4df4 # macro
mmRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX = 1 # macro
mmRLC_XT_DOORBELL_RANGE = 0x4df5 # macro
mmRLC_XT_DOORBELL_RANGE_BASE_IDX = 1 # macro
mmRLC_XT_DOORBELL_CNTL = 0x4df6 # macro
mmRLC_XT_DOORBELL_CNTL_BASE_IDX = 1 # macro
mmRLC_XT_DOORBELL_STAT = 0x4df7 # macro
mmRLC_XT_DOORBELL_STAT_BASE_IDX = 1 # macro
mmRLC_XT_DOORBELL_0_DATA_LO = 0x4df8 # macro
mmRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro
mmRLC_XT_DOORBELL_0_DATA_HI = 0x4df9 # macro
mmRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro
mmRLC_XT_DOORBELL_1_DATA_LO = 0x4dfa # macro
mmRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro
mmRLC_XT_DOORBELL_1_DATA_HI = 0x4dfb # macro
mmRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro
mmRLC_XT_DOORBELL_2_DATA_LO = 0x4dfc # macro
mmRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro
mmRLC_XT_DOORBELL_2_DATA_HI = 0x4dfd # macro
mmRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro
mmRLC_XT_DOORBELL_3_DATA_LO = 0x4dfe # macro
mmRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro
mmRLC_XT_DOORBELL_3_DATA_HI = 0x4dff # macro
mmRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro
mmRLC_SPP_CAM_ADDR = 0x4e00 # macro
mmRLC_SPP_CAM_ADDR_BASE_IDX = 1 # macro
mmRLC_SPP_CAM_DATA = 0x4e01 # macro
mmRLC_SPP_CAM_DATA_BASE_IDX = 1 # macro
mmRLC_SPP_CAM_EXT_ADDR = 0x4e02 # macro
mmRLC_SPP_CAM_EXT_ADDR_BASE_IDX = 1 # macro
mmRLC_SPP_CAM_EXT_DATA = 0x4e03 # macro
mmRLC_SPP_CAM_EXT_DATA_BASE_IDX = 1 # macro
mmRLC_PACE_SCRATCH_ADDR = 0x4e04 # macro
mmRLC_PACE_SCRATCH_ADDR_BASE_IDX = 1 # macro
mmRLC_PACE_SCRATCH_DATA = 0x4e05 # macro
mmRLC_PACE_SCRATCH_DATA_BASE_IDX = 1 # macro
mmRLC_RLCS_DEC_START = 0x4e60 # macro
mmRLC_RLCS_DEC_START_BASE_IDX = 1 # macro
mmRLC_RLCS_DEC_DUMP_ADDR = 0x4e61 # macro
mmRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX = 1 # macro
mmRLC_RLCS_EXCEPTION_REG_1 = 0x4e62 # macro
mmRLC_RLCS_EXCEPTION_REG_1_BASE_IDX = 1 # macro
mmRLC_RLCS_EXCEPTION_REG_2 = 0x4e63 # macro
mmRLC_RLCS_EXCEPTION_REG_2_BASE_IDX = 1 # macro
mmRLC_RLCS_EXCEPTION_REG_3 = 0x4e64 # macro
mmRLC_RLCS_EXCEPTION_REG_3_BASE_IDX = 1 # macro
mmRLC_RLCS_EXCEPTION_REG_4 = 0x4e65 # macro
mmRLC_RLCS_EXCEPTION_REG_4_BASE_IDX = 1 # macro
mmRLC_RLCS_GENERAL_6 = 0x4e66 # macro
mmRLC_RLCS_GENERAL_6_BASE_IDX = 1 # macro
mmRLC_RLCS_GENERAL_7 = 0x4e67 # macro
mmRLC_RLCS_GENERAL_7_BASE_IDX = 1 # macro
mmRLC_RLCS_CGCG_REQUEST = 0x4e68 # macro
mmRLC_RLCS_CGCG_REQUEST_BASE_IDX = 1 # macro
mmRLC_RLCS_CGCG_STATUS = 0x4e69 # macro
mmRLC_RLCS_CGCG_STATUS_BASE_IDX = 1 # macro
mmRLC_RLCS_SMU_GFXCLK_STATUS = 0x4e6a # macro
mmRLC_RLCS_SMU_GFXCLK_STATUS_BASE_IDX = 1 # macro
mmRLC_RLCS_SMU_GFXCLK_CONTROL = 0x4e6b # macro
mmRLC_RLCS_SMU_GFXCLK_CONTROL_BASE_IDX = 1 # macro
mmRLC_RLCS_SOC_DS_CNTL = 0x4e6c # macro
mmRLC_RLCS_SOC_DS_CNTL_BASE_IDX = 1 # macro
mmRLC_RLCS_GFX_DS_CNTL = 0x4e6d # macro
mmRLC_RLCS_GFX_DS_CNTL_BASE_IDX = 1 # macro
mmRLC_GPM_STAT = 0x4e6e # macro
mmRLC_GPM_STAT_BASE_IDX = 1 # macro
mmRLC_RLCS_GPM_STAT = 0x4e6e # macro
mmRLC_RLCS_GPM_STAT_BASE_IDX = 1 # macro
mmRLC_RLCS_ABORTED_PD_SEQUENCE = 0x4e6f # macro
mmRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX = 1 # macro
mmRLC_RLCS_DIDT_FORCE_STALL = 0x4e70 # macro
mmRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX = 1 # macro
mmRLC_RLCS_IOV_CMD_STATUS = 0x4e71 # macro
mmRLC_RLCS_IOV_CMD_STATUS_BASE_IDX = 1 # macro
mmRLC_RLCS_IOV_CNTX_LOC_SIZE = 0x4e72 # macro
mmRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX = 1 # macro
mmRLC_RLCS_IOV_SCH_BLOCK = 0x4e73 # macro
mmRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX = 1 # macro
mmRLC_RLCS_IOV_VM_BUSY_STATUS = 0x4e74 # macro
mmRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro
mmRLC_RLCS_GPM_STAT_2 = 0x4e75 # macro
mmRLC_RLCS_GPM_STAT_2_BASE_IDX = 1 # macro
mmRLC_RLCS_GRBM_SOFT_RESET = 0x4e76 # macro
mmRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX = 1 # macro
mmRLC_RLCS_PG_CHANGE_STATUS = 0x4e77 # macro
mmRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX = 1 # macro
mmRLC_RLCS_PG_CHANGE_READ = 0x4e78 # macro
mmRLC_RLCS_PG_CHANGE_READ_BASE_IDX = 1 # macro
mmRLC_RLCS_LB_STATUS = 0x4e79 # macro
mmRLC_RLCS_LB_STATUS_BASE_IDX = 1 # macro
mmRLC_RLCS_LB_READ = 0x4e7a # macro
mmRLC_RLCS_LB_READ_BASE_IDX = 1 # macro
mmRLC_RLCS_LB_CONTROL = 0x4e7b # macro
mmRLC_RLCS_LB_CONTROL_BASE_IDX = 1 # macro
mmRLC_RLCS_IH_SEMAPHORE = 0x4e7c # macro
mmRLC_RLCS_IH_SEMAPHORE_BASE_IDX = 1 # macro
mmRLC_RLCS_IH_COOKIE_SEMAPHORE = 0x4e7d # macro
mmRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX = 1 # macro
mmRLC_RLCS_IH_CTRL_1 = 0x4e7e # macro
mmRLC_RLCS_IH_CTRL_1_BASE_IDX = 1 # macro
mmRLC_RLCS_IH_CTRL_2 = 0x4e7f # macro
mmRLC_RLCS_IH_CTRL_2_BASE_IDX = 1 # macro
mmRLC_RLCS_IH_CTRL_3 = 0x4e80 # macro
mmRLC_RLCS_IH_CTRL_3_BASE_IDX = 1 # macro
mmRLC_RLCS_IH_STATUS = 0x4e81 # macro
mmRLC_RLCS_IH_STATUS_BASE_IDX = 1 # macro
mmRLC_RLCS_WGP_STATUS = 0x4e82 # macro
mmRLC_RLCS_WGP_STATUS_BASE_IDX = 1 # macro
mmRLC_RLCS_WGP_READ = 0x4e83 # macro
mmRLC_RLCS_WGP_READ_BASE_IDX = 1 # macro
mmRLC_RLCS_CP_INT_CTRL_1 = 0x4e84 # macro
mmRLC_RLCS_CP_INT_CTRL_1_BASE_IDX = 1 # macro
mmRLC_RLCS_CP_INT_CTRL_2 = 0x4e85 # macro
mmRLC_RLCS_CP_INT_CTRL_2_BASE_IDX = 1 # macro
mmRLC_RLCS_CP_INT_INFO_1 = 0x4e86 # macro
mmRLC_RLCS_CP_INT_INFO_1_BASE_IDX = 1 # macro
mmRLC_RLCS_CP_INT_INFO_2 = 0x4e87 # macro
mmRLC_RLCS_CP_INT_INFO_2_BASE_IDX = 1 # macro
mmRLC_RLCS_SPM_INT_CTRL = 0x4e88 # macro
mmRLC_RLCS_SPM_INT_CTRL_BASE_IDX = 1 # macro
mmRLC_RLCS_SPM_INT_INFO_1 = 0x4e89 # macro
mmRLC_RLCS_SPM_INT_INFO_1_BASE_IDX = 1 # macro
mmRLC_RLCS_SPM_INT_INFO_2 = 0x4e8a # macro
mmRLC_RLCS_SPM_INT_INFO_2_BASE_IDX = 1 # macro
mmRLC_RLCS_DSM_TRIG = 0x4e8b # macro
mmRLC_RLCS_DSM_TRIG_BASE_IDX = 1 # macro
mmRLC_RLCS_BOOTLOAD_STATUS = 0x4e8d # macro
mmRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX = 1 # macro
mmRLC_RLCS_POWER_BRAKE_CNTL = 0x4e8e # macro
mmRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX = 1 # macro
mmRLC_RLCS_GENERAL_0 = 0x4e8f # macro
mmRLC_RLCS_GENERAL_0_BASE_IDX = 1 # macro
mmRLC_RLCS_GENERAL_1 = 0x4e90 # macro
mmRLC_RLCS_GENERAL_1_BASE_IDX = 1 # macro
mmRLC_RLCS_GENERAL_2 = 0x4e91 # macro
mmRLC_RLCS_GENERAL_2_BASE_IDX = 1 # macro
mmRLC_RLCS_GENERAL_3 = 0x4e92 # macro
mmRLC_RLCS_GENERAL_3_BASE_IDX = 1 # macro
mmRLC_RLCS_GENERAL_4 = 0x4e93 # macro
mmRLC_RLCS_GENERAL_4_BASE_IDX = 1 # macro
mmRLC_RLCS_GENERAL_5 = 0x4e94 # macro
mmRLC_RLCS_GENERAL_5_BASE_IDX = 1 # macro
mmRLC_RLCS_GRBM_IDLE_BUSY_STAT = 0x4ec1 # macro
mmRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX = 1 # macro
mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL = 0x4ec2 # macro
mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX = 1 # macro
mmRLC_RLCS_CMP_IDLE_CNTL = 0x4ec3 # macro
mmRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX = 1 # macro
mmRLC_RLCS_POWER_BRAKE_CNTL_TH1 = 0x4ec4 # macro
mmRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX = 1 # macro
mmRLC_RLCS_AUXILIARY_REG_1 = 0x4ec5 # macro
mmRLC_RLCS_AUXILIARY_REG_1_BASE_IDX = 1 # macro
mmRLC_RLCS_AUXILIARY_REG_2 = 0x4ec6 # macro
mmRLC_RLCS_AUXILIARY_REG_2_BASE_IDX = 1 # macro
mmRLC_RLCS_AUXILIARY_REG_3 = 0x4ec7 # macro
mmRLC_RLCS_AUXILIARY_REG_3_BASE_IDX = 1 # macro
mmRLC_RLCS_AUXILIARY_REG_4 = 0x4ec8 # macro
mmRLC_RLCS_AUXILIARY_REG_4_BASE_IDX = 1 # macro
mmRLC_RLCS_SPM_SQTT_MODE = 0x4ee0 # macro
mmRLC_RLCS_SPM_SQTT_MODE_BASE_IDX = 1 # macro
mmRLC_RLCS_CP_DMA_SRCID_OVER = 0x4ee4 # macro
mmRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX = 1 # macro
mmRLC_RLCS_UTCL2_CNTL = 0x4ee6 # macro
mmRLC_RLCS_UTCL2_CNTL_BASE_IDX = 1 # macro
mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL = 0x4ee8 # macro
mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL_BASE_IDX = 1 # macro
mmRLC_RLCS_BOOTLOAD_ID_STATUS1 = 0x4eec # macro
mmRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX = 1 # macro
mmRLC_RLCS_BOOTLOAD_ID_STATUS2 = 0x4eed # macro
mmRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX = 1 # macro
mmRLC_RLCS_SMUIO_VIDCHG_CTRL = 0x4eee # macro
mmRLC_RLCS_SMUIO_VIDCHG_CTRL_BASE_IDX = 1 # macro
mmRLC_RLCS_EDC_INT_CNTL = 0x4eef # macro
mmRLC_RLCS_EDC_INT_CNTL_BASE_IDX = 1 # macro
mmRLC_RLCS_KMD_LOG_CNTL1 = 0x4ef1 # macro
mmRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX = 1 # macro
mmRLC_RLCS_KMD_LOG_CNTL2 = 0x4ef2 # macro
mmRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX = 1 # macro
mmRLC_RLCS_GPM_LEGACY_INT_STAT = 0x4ef3 # macro
mmRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro
mmRLC_RLCS_GPM_LEGACY_INT_DISABLE = 0x4ef4 # macro
mmRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro
mmRLC_RLCS_SRM_SRCID_CNTL = 0x4efd # macro
mmRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX = 1 # macro
mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE = 0x4f03 # macro
mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX = 1 # macro
mmRLC_RLCS_DEC_END = 0x4fff # macro
mmRLC_RLCS_DEC_END_BASE_IDX = 1 # macro
mmCGTS_RD_CTRL_REG = 0x5004 # macro
mmCGTS_RD_CTRL_REG_BASE_IDX = 1 # macro
mmCGTS_RD_REG = 0x5005 # macro
mmCGTS_RD_REG_BASE_IDX = 1 # macro
mmCGTS_TCC_DISABLE = 0x5006 # macro
mmCGTS_TCC_DISABLE_BASE_IDX = 1 # macro
mmCGTS_USER_TCC_DISABLE = 0x5007 # macro
mmCGTS_USER_TCC_DISABLE_BASE_IDX = 1 # macro
mmCGTS_STATUS_REG = 0x5008 # macro
mmCGTS_STATUS_REG_BASE_IDX = 1 # macro
mmCGTT_SPI_CGTSSM_CLK_CTRL = 0x5009 # macro
mmCGTT_SPI_CGTSSM_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_SPI_PS_CLK_CTRL = 0x507d # macro
mmCGTT_SPI_PS_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_SPIS_CLK_CTRL = 0x507e # macro
mmCGTT_SPIS_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_SPI_CLK_CTRL = 0x5080 # macro
mmCGTT_SPI_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_PC_CLK_CTRL = 0x5081 # macro
mmCGTT_PC_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_BCI_CLK_CTRL = 0x5082 # macro
mmCGTT_BCI_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_VGT_CLK_CTRL = 0x5084 # macro
mmCGTT_VGT_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_IA_CLK_CTRL = 0x5085 # macro
mmCGTT_IA_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_WD_CLK_CTRL = 0x5086 # macro
mmCGTT_WD_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_GS_NGG_CLK_CTRL = 0x5087 # macro
mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_PA_CLK_CTRL = 0x5088 # macro
mmCGTT_PA_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_SC_CLK_CTRL0 = 0x5089 # macro
mmCGTT_SC_CLK_CTRL0_BASE_IDX = 1 # macro
mmCGTT_SC_CLK_CTRL1 = 0x508a # macro
mmCGTT_SC_CLK_CTRL1_BASE_IDX = 1 # macro
mmCGTT_SC_CLK_CTRL2 = 0x508b # macro
mmCGTT_SC_CLK_CTRL2_BASE_IDX = 1 # macro
mmCGTT_SQ_CLK_CTRL = 0x508c # macro
mmCGTT_SQ_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_SQG_CLK_CTRL = 0x508d # macro
mmCGTT_SQG_CLK_CTRL_BASE_IDX = 1 # macro
mmSQ_ALU_CLK_CTRL = 0x508e # macro
mmSQ_ALU_CLK_CTRL_BASE_IDX = 1 # macro
mmSQ_TEX_CLK_CTRL = 0x508f # macro
mmSQ_TEX_CLK_CTRL_BASE_IDX = 1 # macro
mmSQ_LDS_CLK_CTRL = 0x5090 # macro
mmSQ_LDS_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_SX_CLK_CTRL0 = 0x5094 # macro
mmCGTT_SX_CLK_CTRL0_BASE_IDX = 1 # macro
mmCGTT_SX_CLK_CTRL1 = 0x5095 # macro
mmCGTT_SX_CLK_CTRL1_BASE_IDX = 1 # macro
mmCGTT_SX_CLK_CTRL2 = 0x5096 # macro
mmCGTT_SX_CLK_CTRL2_BASE_IDX = 1 # macro
mmCGTT_SX_CLK_CTRL3 = 0x5097 # macro
mmCGTT_SX_CLK_CTRL3_BASE_IDX = 1 # macro
mmCGTT_SX_CLK_CTRL4 = 0x5098 # macro
mmCGTT_SX_CLK_CTRL4_BASE_IDX = 1 # macro
mmTD_CGTT_CTRL = 0x509c # macro
mmTD_CGTT_CTRL_BASE_IDX = 1 # macro
mmTA_CGTT_CTRL = 0x509d # macro
mmTA_CGTT_CTRL_BASE_IDX = 1 # macro
mmCGTT_TCPI_CLK_CTRL = 0x5109 # macro
mmCGTT_TCPI_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_GDS_CLK_CTRL = 0x50a0 # macro
mmCGTT_GDS_CLK_CTRL_BASE_IDX = 1 # macro
mmDB_CGTT_CLK_CTRL_0 = 0x50a4 # macro
mmDB_CGTT_CLK_CTRL_0_BASE_IDX = 1 # macro
mmCB_CGTT_SCLK_CTRL = 0x50a8 # macro
mmCB_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro
mmGL2C_CGTT_SCLK_CTRL = 0x50fc # macro
mmGL2C_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro
mmGL2A_CGTT_SCLK_CTRL = 0x50ac # macro
mmGL2A_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro
mmGL2A_CGTT_SCLK_CTRL_1 = 0x50ad # macro
mmGL2A_CGTT_SCLK_CTRL_1_BASE_IDX = 1 # macro
mmCGTT_CP_CLK_CTRL = 0x50b0 # macro
mmCGTT_CP_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_CPF_CLK_CTRL = 0x50b1 # macro
mmCGTT_CPF_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_CPC_CLK_CTRL = 0x50b2 # macro
mmCGTT_CPC_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_RLC_CLK_CTRL = 0x50b5 # macro
mmCGTT_RLC_CLK_CTRL_BASE_IDX = 1 # macro
mmRLC_GFX_RM_CNTL = 0x50b6 # macro
mmRLC_GFX_RM_CNTL_BASE_IDX = 1 # macro
mmRMI_CGTT_SCLK_CTRL = 0x50c0 # macro
mmRMI_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_TCPF_CLK_CTRL = 0x5111 # macro
mmCGTT_TCPF_CLK_CTRL_BASE_IDX = 1 # macro
mmGCR_CGTT_SCLK_CTRL = 0x50c2 # macro
mmGCR_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro
mmUTCL1_CGTT_CLK_CTRL = 0x50c3 # macro
mmUTCL1_CGTT_CLK_CTRL_BASE_IDX = 1 # macro
mmGCEA_CGTT_CLK_CTRL = 0x50c4 # macro
mmGCEA_CGTT_CLK_CTRL_BASE_IDX = 1 # macro
mmSE_CAC_CGTT_CLK_CTRL = 0x50d0 # macro
mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX = 1 # macro
mmGC_CAC_CGTT_CLK_CTRL = 0x50d8 # macro
mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX = 1 # macro
mmGRBM_CGTT_CLK_CNTL = 0x50e0 # macro
mmGRBM_CGTT_CLK_CNTL_BASE_IDX = 1 # macro
mmGUS_CGTT_CLK_CTRL = 0x50f4 # macro
mmGUS_CGTT_CLK_CTRL_BASE_IDX = 1 # macro
mmCGTT_PH_CLK_CTRL0 = 0x50f8 # macro
mmCGTT_PH_CLK_CTRL0_BASE_IDX = 1 # macro
mmCGTT_PH_CLK_CTRL1 = 0x50f9 # macro
mmCGTT_PH_CLK_CTRL1_BASE_IDX = 1 # macro
mmCGTT_PH_CLK_CTRL2 = 0x50fa # macro
mmCGTT_PH_CLK_CTRL2_BASE_IDX = 1 # macro
mmCGTT_PH_CLK_CTRL3 = 0x50fb # macro
mmCGTT_PH_CLK_CTRL3_BASE_IDX = 1 # macro
mmCP_HYP_PFP_UCODE_ADDR = 0x5814 # macro
mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro
mmCP_PFP_UCODE_ADDR = 0x5814 # macro
mmCP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro
mmCP_HYP_PFP_UCODE_DATA = 0x5815 # macro
mmCP_HYP_PFP_UCODE_DATA_BASE_IDX = 1 # macro
mmCP_PFP_UCODE_DATA = 0x5815 # macro
mmCP_PFP_UCODE_DATA_BASE_IDX = 1 # macro
mmCP_HYP_ME_UCODE_ADDR = 0x5816 # macro
mmCP_HYP_ME_UCODE_ADDR_BASE_IDX = 1 # macro
mmCP_ME_RAM_RADDR = 0x5816 # macro
mmCP_ME_RAM_RADDR_BASE_IDX = 1 # macro
mmCP_ME_RAM_WADDR = 0x5816 # macro
mmCP_ME_RAM_WADDR_BASE_IDX = 1 # macro
mmCP_HYP_ME_UCODE_DATA = 0x5817 # macro
mmCP_HYP_ME_UCODE_DATA_BASE_IDX = 1 # macro
mmCP_ME_RAM_DATA = 0x5817 # macro
mmCP_ME_RAM_DATA_BASE_IDX = 1 # macro
mmCP_CE_UCODE_ADDR = 0x5818 # macro
mmCP_CE_UCODE_ADDR_BASE_IDX = 1 # macro
mmCP_HYP_CE_UCODE_ADDR = 0x5818 # macro
mmCP_HYP_CE_UCODE_ADDR_BASE_IDX = 1 # macro
mmCP_CE_UCODE_DATA = 0x5819 # macro
mmCP_CE_UCODE_DATA_BASE_IDX = 1 # macro
mmCP_HYP_CE_UCODE_DATA = 0x5819 # macro
mmCP_HYP_CE_UCODE_DATA_BASE_IDX = 1 # macro
mmCP_HYP_MEC1_UCODE_ADDR = 0x581a # macro
mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX = 1 # macro
mmCP_MEC_ME1_UCODE_ADDR = 0x581a # macro
mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX = 1 # macro
mmCP_HYP_MEC1_UCODE_DATA = 0x581b # macro
mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX = 1 # macro
mmCP_MEC_ME1_UCODE_DATA = 0x581b # macro
mmCP_MEC_ME1_UCODE_DATA_BASE_IDX = 1 # macro
mmCP_HYP_MEC2_UCODE_ADDR = 0x581c # macro
mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX = 1 # macro
mmCP_MEC_ME2_UCODE_ADDR = 0x581c # macro
mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX = 1 # macro
mmCP_HYP_MEC2_UCODE_DATA = 0x581d # macro
mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX = 1 # macro
mmCP_MEC_ME2_UCODE_DATA = 0x581d # macro
mmCP_MEC_ME2_UCODE_DATA_BASE_IDX = 1 # macro
mmCP_PFP_IC_BASE_LO = 0x5840 # macro
mmCP_PFP_IC_BASE_LO_BASE_IDX = 1 # macro
mmCP_PFP_IC_BASE_HI = 0x5841 # macro
mmCP_PFP_IC_BASE_HI_BASE_IDX = 1 # macro
mmCP_PFP_IC_BASE_CNTL = 0x5842 # macro
mmCP_PFP_IC_BASE_CNTL_BASE_IDX = 1 # macro
mmCP_PFP_IC_OP_CNTL = 0x5843 # macro
mmCP_PFP_IC_OP_CNTL_BASE_IDX = 1 # macro
mmCP_ME_IC_BASE_LO = 0x5844 # macro
mmCP_ME_IC_BASE_LO_BASE_IDX = 1 # macro
mmCP_ME_IC_BASE_HI = 0x5845 # macro
mmCP_ME_IC_BASE_HI_BASE_IDX = 1 # macro
mmCP_ME_IC_BASE_CNTL = 0x5846 # macro
mmCP_ME_IC_BASE_CNTL_BASE_IDX = 1 # macro
mmCP_ME_IC_OP_CNTL = 0x5847 # macro
mmCP_ME_IC_OP_CNTL_BASE_IDX = 1 # macro
mmCP_CE_IC_BASE_LO = 0x5848 # macro
mmCP_CE_IC_BASE_LO_BASE_IDX = 1 # macro
mmCP_CE_IC_BASE_HI = 0x5849 # macro
mmCP_CE_IC_BASE_HI_BASE_IDX = 1 # macro
mmCP_CE_IC_BASE_CNTL = 0x584a # macro
mmCP_CE_IC_BASE_CNTL_BASE_IDX = 1 # macro
mmCP_CE_IC_OP_CNTL = 0x584b # macro
mmCP_CE_IC_OP_CNTL_BASE_IDX = 1 # macro
mmCP_CPC_IC_BASE_LO = 0x584c # macro
mmCP_CPC_IC_BASE_LO_BASE_IDX = 1 # macro
mmCP_CPC_IC_BASE_HI = 0x584d # macro
mmCP_CPC_IC_BASE_HI_BASE_IDX = 1 # macro
mmCP_CPC_IC_BASE_CNTL = 0x584e # macro
mmCP_CPC_IC_BASE_CNTL_BASE_IDX = 1 # macro
mmCP_CPC_IC_OP_CNTL = 0x584f # macro
mmCP_CPC_IC_OP_CNTL_BASE_IDX = 1 # macro
mmCP_MES_IC_BASE_LO = 0x5850 # macro
mmCP_MES_IC_BASE_LO_BASE_IDX = 1 # macro
mmCP_MES_MIBASE_LO = 0x5850 # macro
mmCP_MES_MIBASE_LO_BASE_IDX = 1 # macro
mmCP_MES_IC_BASE_HI = 0x5851 # macro
mmCP_MES_IC_BASE_HI_BASE_IDX = 1 # macro
mmCP_MES_MIBASE_HI = 0x5851 # macro
mmCP_MES_MIBASE_HI_BASE_IDX = 1 # macro
mmCP_MES_IC_BASE_CNTL = 0x5852 # macro
mmCP_MES_IC_BASE_CNTL_BASE_IDX = 1 # macro
mmCP_MES_DC_BASE_LO = 0x5854 # macro
mmCP_MES_DC_BASE_LO_BASE_IDX = 1 # macro
mmCP_MES_MDBASE_LO = 0x5854 # macro
mmCP_MES_MDBASE_LO_BASE_IDX = 1 # macro
mmCP_MES_DC_BASE_HI = 0x5855 # macro
mmCP_MES_DC_BASE_HI_BASE_IDX = 1 # macro
mmCP_MES_MDBASE_HI = 0x5855 # macro
mmCP_MES_MDBASE_HI_BASE_IDX = 1 # macro
mmCP_MES_LOCAL_BASE0_LO = 0x5856 # macro
mmCP_MES_LOCAL_BASE0_LO_BASE_IDX = 1 # macro
mmCP_MES_LOCAL_BASE0_HI = 0x5857 # macro
mmCP_MES_LOCAL_BASE0_HI_BASE_IDX = 1 # macro
mmCP_MES_LOCAL_MASK0_LO = 0x5858 # macro
mmCP_MES_LOCAL_MASK0_LO_BASE_IDX = 1 # macro
mmCP_MES_LOCAL_MASK0_HI = 0x5859 # macro
mmCP_MES_LOCAL_MASK0_HI_BASE_IDX = 1 # macro
mmCP_MES_LOCAL_APERTURE = 0x585a # macro
mmCP_MES_LOCAL_APERTURE_BASE_IDX = 1 # macro
mmCP_MES_MIBOUND_LO = 0x585b # macro
mmCP_MES_MIBOUND_LO_BASE_IDX = 1 # macro
mmCP_MES_MIBOUND_HI = 0x585c # macro
mmCP_MES_MIBOUND_HI_BASE_IDX = 1 # macro
mmCP_MES_MDBOUND_LO = 0x585d # macro
mmCP_MES_MDBOUND_LO_BASE_IDX = 1 # macro
mmCP_MES_MDBOUND_HI = 0x585e # macro
mmCP_MES_MDBOUND_HI_BASE_IDX = 1 # macro
mmGFX_PIPE_PRIORITY = 0x587f # macro
mmGFX_PIPE_PRIORITY_BASE_IDX = 1 # macro
mmGRBM_GFX_INDEX_SR_SELECT = 0x5a00 # macro
mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX = 1 # macro
mmGRBM_GFX_INDEX_SR_DATA = 0x5a01 # macro
mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX = 1 # macro
mmGRBM_GFX_CNTL_SR_SELECT = 0x5a02 # macro
mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX = 1 # macro
mmGRBM_GFX_CNTL_SR_DATA = 0x5a03 # macro
mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX = 1 # macro
mmGRBM_CAM_INDEX = 0x5a04 # macro
mmGRBM_CAM_INDEX_BASE_IDX = 1 # macro
mmGRBM_HYP_CAM_INDEX = 0x5a04 # macro
mmGRBM_HYP_CAM_INDEX_BASE_IDX = 1 # macro
mmGRBM_CAM_DATA = 0x5a05 # macro
mmGRBM_CAM_DATA_BASE_IDX = 1 # macro
mmGRBM_HYP_CAM_DATA = 0x5a05 # macro
mmGRBM_HYP_CAM_DATA_BASE_IDX = 1 # macro
mmGRBM_CAM_DATA_UPPER = 0x5a06 # macro
mmGRBM_CAM_DATA_UPPER_BASE_IDX = 1 # macro
mmGRBM_HYP_CAM_DATA_UPPER = 0x5a06 # macro
mmGRBM_HYP_CAM_DATA_UPPER_BASE_IDX = 1 # macro
mmGC_IH_COOKIE_0_PTR = 0x5a07 # macro
mmGC_IH_COOKIE_0_PTR_BASE_IDX = 1 # macro
mmGRBM_SE_REMAP_CNTL = 0x5a08 # macro
mmGRBM_SE_REMAP_CNTL_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_VF_ENABLE = 0x5b00 # macro
mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_CFG_REG6 = 0x5b06 # macro
mmRLC_GPU_IOV_CFG_REG6_BASE_IDX = 1 # macro
mmRLC_SDMA0_STATUS = 0x5b12 # macro
mmRLC_SDMA0_STATUS_BASE_IDX = 1 # macro
mmRLC_SDMA1_STATUS = 0x5b13 # macro
mmRLC_SDMA1_STATUS_BASE_IDX = 1 # macro
mmRLC_SDMA2_STATUS = 0x5b14 # macro
mmRLC_SDMA2_STATUS_BASE_IDX = 1 # macro
mmRLC_SDMA3_STATUS = 0x5b15 # macro
mmRLC_SDMA3_STATUS_BASE_IDX = 1 # macro
mmRLC_SDMA0_BUSY_STATUS = 0x5b16 # macro
mmRLC_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro
mmRLC_SDMA1_BUSY_STATUS = 0x5b17 # macro
mmRLC_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro
mmRLC_SDMA2_BUSY_STATUS = 0x5b18 # macro
mmRLC_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro
mmRLC_SDMA3_BUSY_STATUS = 0x5b19 # macro
mmRLC_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_CFG_REG8 = 0x5b20 # macro
mmRLC_GPU_IOV_CFG_REG8_BASE_IDX = 1 # macro
mmRLC_RLCV_TIMER_INT_0 = 0x5b25 # macro
mmRLC_RLCV_TIMER_INT_0_BASE_IDX = 1 # macro
mmRLC_RLCV_TIMER_CTRL = 0x5b26 # macro
mmRLC_RLCV_TIMER_CTRL_BASE_IDX = 1 # macro
mmRLC_RLCV_TIMER_STAT = 0x5b27 # macro
mmRLC_RLCV_TIMER_STAT_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_VF_DOORBELL_STATUS = 0x5b2a # macro
mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET = 0x5b2b # macro
mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR = 0x5b2c # macro
mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_VF_MASK = 0x5b2d # macro
mmRLC_GPU_IOV_VF_MASK_BASE_IDX = 1 # macro
mmRLC_HYP_SEMAPHORE_0 = 0x5b2e # macro
mmRLC_HYP_SEMAPHORE_0_BASE_IDX = 1 # macro
mmRLC_HYP_SEMAPHORE_1 = 0x5b2f # macro
mmRLC_HYP_SEMAPHORE_1_BASE_IDX = 1 # macro
mmRLC_BUSY_CLK_CNTL = 0x5b30 # macro
mmRLC_BUSY_CLK_CNTL_BASE_IDX = 1 # macro
mmRLC_CLK_CNTL = 0x5b31 # macro
mmRLC_CLK_CNTL_BASE_IDX = 1 # macro
mmRLC_PACE_TIMER_STAT = 0x5b33 # macro
mmRLC_PACE_TIMER_STAT_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SCH_BLOCK = 0x5b34 # macro
mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_CFG_REG1 = 0x5b35 # macro
mmRLC_GPU_IOV_CFG_REG1_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_CFG_REG2 = 0x5b36 # macro
mmRLC_GPU_IOV_CFG_REG2_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_VM_BUSY_STATUS = 0x5b37 # macro
mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SCH_0 = 0x5b38 # macro
mmRLC_GPU_IOV_SCH_0_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_ACTIVE_FCN_ID = 0x5b39 # macro
mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SCH_3 = 0x5b3a # macro
mmRLC_GPU_IOV_SCH_3_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SCH_1 = 0x5b3b # macro
mmRLC_GPU_IOV_SCH_1_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SCH_2 = 0x5b3c # macro
mmRLC_GPU_IOV_SCH_2_BASE_IDX = 1 # macro
mmRLC_PACE_INT_FORCE = 0x5b3d # macro
mmRLC_PACE_INT_FORCE_BASE_IDX = 1 # macro
mmRLC_PACE_INT_CLEAR = 0x5b3e # macro
mmRLC_PACE_INT_CLEAR_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_INT_STAT = 0x5b3f # macro
mmRLC_GPU_IOV_INT_STAT_BASE_IDX = 1 # macro
mmRLC_RLCV_TIMER_INT_1 = 0x5b40 # macro
mmRLC_RLCV_TIMER_INT_1_BASE_IDX = 1 # macro
mmRLC_IH_COOKIE = 0x5b41 # macro
mmRLC_IH_COOKIE_BASE_IDX = 1 # macro
mmRLC_IH_COOKIE_CNTL = 0x5b42 # macro
mmRLC_IH_COOKIE_CNTL_BASE_IDX = 1 # macro
mmRLC_HYP_RLCG_UCODE_CHKSUM = 0x5b43 # macro
mmRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX = 1 # macro
mmRLC_HYP_RLCP_UCODE_CHKSUM = 0x5b44 # macro
mmRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX = 1 # macro
mmRLC_HYP_RLCV_UCODE_CHKSUM = 0x5b45 # macro
mmRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_F32_CNTL = 0x5b46 # macro
mmRLC_GPU_IOV_F32_CNTL_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_F32_RESET = 0x5b47 # macro
mmRLC_GPU_IOV_F32_RESET_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SMU_RESPONSE = 0x5b4a # macro
mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_VIRT_RESET_REQ = 0x5b4c # macro
mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_RLC_RESPONSE = 0x5b4d # macro
mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_INT_DISABLE = 0x5b4e # macro
mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_INT_FORCE = 0x5b4f # macro
mmRLC_GPU_IOV_INT_FORCE_BASE_IDX = 1 # macro
mmRLC_HYP_SEMAPHORE_2 = 0x5b52 # macro
mmRLC_HYP_SEMAPHORE_2_BASE_IDX = 1 # macro
mmRLC_HYP_SEMAPHORE_3 = 0x5b53 # macro
mmRLC_HYP_SEMAPHORE_3_BASE_IDX = 1 # macro
mmRLC_HYP_RESET_VECTOR = 0x5b54 # macro
mmRLC_HYP_RESET_VECTOR_BASE_IDX = 1 # macro
mmRLC_HYP_BOOTLOAD_SIZE = 0x5b5c # macro
mmRLC_HYP_BOOTLOAD_SIZE_BASE_IDX = 1 # macro
mmRLC_HYP_BOOTLOAD_ADDR_LO = 0x5b5d # macro
mmRLC_HYP_BOOTLOAD_ADDR_LO_BASE_IDX = 1 # macro
mmRLC_HYP_BOOTLOAD_ADDR_HI = 0x5b5e # macro
mmRLC_HYP_BOOTLOAD_ADDR_HI_BASE_IDX = 1 # macro
mmRLC_GPM_IRAM_ADDR = 0x5b5f # macro
mmRLC_GPM_IRAM_ADDR_BASE_IDX = 1 # macro
mmRLC_GPM_IRAM_DATA = 0x5b60 # macro
mmRLC_GPM_IRAM_DATA_BASE_IDX = 1 # macro
mmRLC_GPM_UCODE_ADDR = 0x5b61 # macro
mmRLC_GPM_UCODE_ADDR_BASE_IDX = 1 # macro
mmRLC_GPM_UCODE_DATA = 0x5b62 # macro
mmRLC_GPM_UCODE_DATA_BASE_IDX = 1 # macro
mmRLC_PACE_UCODE_ADDR = 0x5b63 # macro
mmRLC_PACE_UCODE_ADDR_BASE_IDX = 1 # macro
mmRLC_PACE_UCODE_DATA = 0x5b64 # macro
mmRLC_PACE_UCODE_DATA_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_UCODE_ADDR = 0x5b65 # macro
mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_UCODE_DATA = 0x5b66 # macro
mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SCRATCH_ADDR = 0x5b67 # macro
mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SCRATCH_DATA = 0x5b68 # macro
mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX = 1 # macro
mmRLC_RLCV_IRAM_ADDR = 0x5b69 # macro
mmRLC_RLCV_IRAM_ADDR_BASE_IDX = 1 # macro
mmRLC_RLCV_IRAM_DATA = 0x5b6a # macro
mmRLC_RLCV_IRAM_DATA_BASE_IDX = 1 # macro
mmRLC_RLCP_IRAM_ADDR = 0x5b6b # macro
mmRLC_RLCP_IRAM_ADDR_BASE_IDX = 1 # macro
mmRLC_RLCP_IRAM_DATA = 0x5b6c # macro
mmRLC_RLCP_IRAM_DATA_BASE_IDX = 1 # macro
mmRLC_SRM_DRAM_ADDR = 0x5b71 # macro
mmRLC_SRM_DRAM_ADDR_BASE_IDX = 1 # macro
mmRLC_SRM_DRAM_DATA = 0x5b72 # macro
mmRLC_SRM_DRAM_DATA_BASE_IDX = 1 # macro
mmRLC_SRM_ARAM_ADDR = 0x5b73 # macro
mmRLC_SRM_ARAM_ADDR_BASE_IDX = 1 # macro
mmRLC_SRM_ARAM_DATA = 0x5b74 # macro
mmRLC_SRM_ARAM_DATA_BASE_IDX = 1 # macro
mmRLC_GPM_SCRATCH_ADDR = 0x5b75 # macro
mmRLC_GPM_SCRATCH_ADDR_BASE_IDX = 1 # macro
mmRLC_GPM_SCRATCH_DATA = 0x5b76 # macro
mmRLC_GPM_SCRATCH_DATA_BASE_IDX = 1 # macro
mmRLC_GTS_OFFSET_LSB = 0x5b79 # macro
mmRLC_GTS_OFFSET_LSB_BASE_IDX = 1 # macro
mmRLC_GTS_OFFSET_MSB = 0x5b7a # macro
mmRLC_GTS_OFFSET_MSB_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA0_STATUS = 0x5bc0 # macro
mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA1_STATUS = 0x5bc1 # macro
mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA2_STATUS = 0x5bc2 # macro
mmRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA3_STATUS = 0x5bc3 # macro
mmRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA4_STATUS = 0x5bc4 # macro
mmRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA5_STATUS = 0x5bc5 # macro
mmRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA6_STATUS = 0x5bc6 # macro
mmRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA7_STATUS = 0x5bc7 # macro
mmRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA0_BUSY_STATUS = 0x5bc8 # macro
mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA1_BUSY_STATUS = 0x5bc9 # macro
mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA2_BUSY_STATUS = 0x5bca # macro
mmRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA3_BUSY_STATUS = 0x5bcb # macro
mmRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA4_BUSY_STATUS = 0x5bcc # macro
mmRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA5_BUSY_STATUS = 0x5bcd # macro
mmRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA6_BUSY_STATUS = 0x5bce # macro
mmRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX = 1 # macro
mmRLC_GPU_IOV_SDMA7_BUSY_STATUS = 0x5bcf # macro
mmRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX = 1 # macro
mmSDMA0_UCODE_ADDR = 0x5880 # macro
mmSDMA0_UCODE_ADDR_BASE_IDX = 1 # macro
mmSDMA0_UCODE_DATA = 0x5881 # macro
mmSDMA0_UCODE_DATA_BASE_IDX = 1 # macro
mmSDMA0_VM_CTX_LO = 0x5882 # macro
mmSDMA0_VM_CTX_LO_BASE_IDX = 1 # macro
mmSDMA0_VM_CTX_HI = 0x5883 # macro
mmSDMA0_VM_CTX_HI_BASE_IDX = 1 # macro
mmSDMA0_ACTIVE_FCN_ID = 0x5884 # macro
mmSDMA0_ACTIVE_FCN_ID_BASE_IDX = 1 # macro
mmSDMA0_VM_CTX_CNTL = 0x5885 # macro
mmSDMA0_VM_CTX_CNTL_BASE_IDX = 1 # macro
mmSDMA0_VIRT_RESET_REQ = 0x5886 # macro
mmSDMA0_VIRT_RESET_REQ_BASE_IDX = 1 # macro
mmSDMA0_VF_ENABLE = 0x5887 # macro
mmSDMA0_VF_ENABLE_BASE_IDX = 1 # macro
mmSDMA0_CONTEXT_REG_TYPE0 = 0x5888 # macro
mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX = 1 # macro
mmSDMA0_CONTEXT_REG_TYPE1 = 0x5889 # macro
mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX = 1 # macro
mmSDMA0_CONTEXT_REG_TYPE2 = 0x588a # macro
mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX = 1 # macro
mmSDMA0_CONTEXT_REG_TYPE3 = 0x588b # macro
mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX = 1 # macro
mmSDMA0_PUB_REG_TYPE0 = 0x588c # macro
mmSDMA0_PUB_REG_TYPE0_BASE_IDX = 1 # macro
mmSDMA0_PUB_REG_TYPE1 = 0x588d # macro
mmSDMA0_PUB_REG_TYPE1_BASE_IDX = 1 # macro
mmSDMA0_PUB_REG_TYPE2 = 0x588e # macro
mmSDMA0_PUB_REG_TYPE2_BASE_IDX = 1 # macro
mmSDMA0_PUB_REG_TYPE3 = 0x588f # macro
mmSDMA0_PUB_REG_TYPE3_BASE_IDX = 1 # macro
mmSDMA0_VM_CNTL = 0x5893 # macro
mmSDMA0_VM_CNTL_BASE_IDX = 1 # macro
mmSDMA0_BROADCAST_UCODE_ADDR = 0x589c # macro
mmSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX = 1 # macro
mmSDMA0_BROADCAST_UCODE_DATA = 0x589d # macro
mmSDMA0_BROADCAST_UCODE_DATA_BASE_IDX = 1 # macro
mmSDMA1_UCODE_ADDR = 0x58a0 # macro
mmSDMA1_UCODE_ADDR_BASE_IDX = 1 # macro
mmSDMA1_UCODE_DATA = 0x58a1 # macro
mmSDMA1_UCODE_DATA_BASE_IDX = 1 # macro
mmSDMA1_VM_CTX_LO = 0x58a2 # macro
mmSDMA1_VM_CTX_LO_BASE_IDX = 1 # macro
mmSDMA1_VM_CTX_HI = 0x58a3 # macro
mmSDMA1_VM_CTX_HI_BASE_IDX = 1 # macro
mmSDMA1_ACTIVE_FCN_ID = 0x58a4 # macro
mmSDMA1_ACTIVE_FCN_ID_BASE_IDX = 1 # macro
mmSDMA1_VM_CTX_CNTL = 0x58a5 # macro
mmSDMA1_VM_CTX_CNTL_BASE_IDX = 1 # macro
mmSDMA1_VIRT_RESET_REQ = 0x58a6 # macro
mmSDMA1_VIRT_RESET_REQ_BASE_IDX = 1 # macro
mmSDMA1_VF_ENABLE = 0x58a7 # macro
mmSDMA1_VF_ENABLE_BASE_IDX = 1 # macro
mmSDMA1_CONTEXT_REG_TYPE0 = 0x58a8 # macro
mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX = 1 # macro
mmSDMA1_CONTEXT_REG_TYPE1 = 0x58a9 # macro
mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX = 1 # macro
mmSDMA1_CONTEXT_REG_TYPE2 = 0x58aa # macro
mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX = 1 # macro
mmSDMA1_CONTEXT_REG_TYPE3 = 0x58ab # macro
mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX = 1 # macro
mmSDMA1_PUB_REG_TYPE0 = 0x58ac # macro
mmSDMA1_PUB_REG_TYPE0_BASE_IDX = 1 # macro
mmSDMA1_PUB_REG_TYPE1 = 0x58ad # macro
mmSDMA1_PUB_REG_TYPE1_BASE_IDX = 1 # macro
mmSDMA1_PUB_REG_TYPE2 = 0x58ae # macro
mmSDMA1_PUB_REG_TYPE2_BASE_IDX = 1 # macro
mmSDMA1_PUB_REG_TYPE3 = 0x58af # macro
mmSDMA1_PUB_REG_TYPE3_BASE_IDX = 1 # macro
mmSDMA1_VM_CNTL = 0x58b3 # macro
mmSDMA1_VM_CNTL_BASE_IDX = 1 # macro
mmSDMA2_UCODE_ADDR = 0x58c0 # macro
mmSDMA2_UCODE_ADDR_BASE_IDX = 1 # macro
mmSDMA2_UCODE_DATA = 0x58c1 # macro
mmSDMA2_UCODE_DATA_BASE_IDX = 1 # macro
mmSDMA2_VM_CTX_LO = 0x58c2 # macro
mmSDMA2_VM_CTX_LO_BASE_IDX = 1 # macro
mmSDMA2_VM_CTX_HI = 0x58c3 # macro
mmSDMA2_VM_CTX_HI_BASE_IDX = 1 # macro
mmSDMA2_ACTIVE_FCN_ID = 0x58c4 # macro
mmSDMA2_ACTIVE_FCN_ID_BASE_IDX = 1 # macro
mmSDMA2_VM_CTX_CNTL = 0x58c5 # macro
mmSDMA2_VM_CTX_CNTL_BASE_IDX = 1 # macro
mmSDMA2_VIRT_RESET_REQ = 0x58c6 # macro
mmSDMA2_VIRT_RESET_REQ_BASE_IDX = 1 # macro
mmSDMA2_VF_ENABLE = 0x58c7 # macro
mmSDMA2_VF_ENABLE_BASE_IDX = 1 # macro
mmSDMA2_CONTEXT_REG_TYPE0 = 0x58c8 # macro
mmSDMA2_CONTEXT_REG_TYPE0_BASE_IDX = 1 # macro
mmSDMA2_CONTEXT_REG_TYPE1 = 0x58c9 # macro
mmSDMA2_CONTEXT_REG_TYPE1_BASE_IDX = 1 # macro
mmSDMA2_CONTEXT_REG_TYPE2 = 0x58ca # macro
mmSDMA2_CONTEXT_REG_TYPE2_BASE_IDX = 1 # macro
mmSDMA2_CONTEXT_REG_TYPE3 = 0x58cb # macro
mmSDMA2_CONTEXT_REG_TYPE3_BASE_IDX = 1 # macro
mmSDMA2_PUB_REG_TYPE0 = 0x58cc # macro
mmSDMA2_PUB_REG_TYPE0_BASE_IDX = 1 # macro
mmSDMA2_PUB_REG_TYPE1 = 0x58cd # macro
mmSDMA2_PUB_REG_TYPE1_BASE_IDX = 1 # macro
mmSDMA2_PUB_REG_TYPE2 = 0x58ce # macro
mmSDMA2_PUB_REG_TYPE2_BASE_IDX = 1 # macro
mmSDMA2_PUB_REG_TYPE3 = 0x58cf # macro
mmSDMA2_PUB_REG_TYPE3_BASE_IDX = 1 # macro
mmSDMA2_VM_CNTL = 0x58d3 # macro
mmSDMA2_VM_CNTL_BASE_IDX = 1 # macro
mmSDMA3_UCODE_ADDR = 0x58e0 # macro
mmSDMA3_UCODE_ADDR_BASE_IDX = 1 # macro
mmSDMA3_UCODE_DATA = 0x58e1 # macro
mmSDMA3_UCODE_DATA_BASE_IDX = 1 # macro
mmSDMA3_VM_CTX_LO = 0x58e2 # macro
mmSDMA3_VM_CTX_LO_BASE_IDX = 1 # macro
mmSDMA3_VM_CTX_HI = 0x58e3 # macro
mmSDMA3_VM_CTX_HI_BASE_IDX = 1 # macro
mmSDMA3_ACTIVE_FCN_ID = 0x58e4 # macro
mmSDMA3_ACTIVE_FCN_ID_BASE_IDX = 1 # macro
mmSDMA3_VM_CTX_CNTL = 0x58e5 # macro
mmSDMA3_VM_CTX_CNTL_BASE_IDX = 1 # macro
mmSDMA3_VIRT_RESET_REQ = 0x58e6 # macro
mmSDMA3_VIRT_RESET_REQ_BASE_IDX = 1 # macro
mmSDMA3_VF_ENABLE = 0x58e7 # macro
mmSDMA3_VF_ENABLE_BASE_IDX = 1 # macro
mmSDMA3_CONTEXT_REG_TYPE0 = 0x58e8 # macro
mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX = 1 # macro
mmSDMA3_CONTEXT_REG_TYPE1 = 0x58e9 # macro
mmSDMA3_CONTEXT_REG_TYPE1_BASE_IDX = 1 # macro
mmSDMA3_CONTEXT_REG_TYPE2 = 0x58ea # macro
mmSDMA3_CONTEXT_REG_TYPE2_BASE_IDX = 1 # macro
mmSDMA3_CONTEXT_REG_TYPE3 = 0x58eb # macro
mmSDMA3_CONTEXT_REG_TYPE3_BASE_IDX = 1 # macro
mmSDMA3_PUB_REG_TYPE0 = 0x58ec # macro
mmSDMA3_PUB_REG_TYPE0_BASE_IDX = 1 # macro
mmSDMA3_PUB_REG_TYPE1 = 0x58ed # macro
mmSDMA3_PUB_REG_TYPE1_BASE_IDX = 1 # macro
mmSDMA3_PUB_REG_TYPE2 = 0x58ee # macro
mmSDMA3_PUB_REG_TYPE2_BASE_IDX = 1 # macro
mmSDMA3_PUB_REG_TYPE3 = 0x58ef # macro
mmSDMA3_PUB_REG_TYPE3_BASE_IDX = 1 # macro
mmSDMA3_VM_CNTL = 0x58f3 # macro
mmSDMA3_VM_CNTL_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF0 = 0x5a80 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF1 = 0x5a81 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF2 = 0x5a82 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF3 = 0x5a83 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF4 = 0x5a84 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF5 = 0x5a85 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF6 = 0x5a86 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF7 = 0x5a87 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF8 = 0x5a88 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF9 = 0x5a89 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF10 = 0x5a8a # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF11 = 0x5a8b # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF12 = 0x5a8c # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF13 = 0x5a8d # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF14 = 0x5a8e # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF15 = 0x5a8f # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF16 = 0x5a90 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF17 = 0x5a91 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF18 = 0x5a92 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF19 = 0x5a93 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF20 = 0x5a94 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF21 = 0x5a95 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF22 = 0x5a96 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF23 = 0x5a97 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF24 = 0x5a98 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF25 = 0x5a99 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF26 = 0x5a9a # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF27 = 0x5a9b # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF28 = 0x5a9c # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF29 = 0x5a9d # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF30 = 0x5a9e # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX = 1 # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF31 = 0x5a9f # macro
mmGCMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX = 1 # macro
mmGCVM_IOMMU_MMIO_CNTRL_1 = 0x5aa0 # macro
mmGCVM_IOMMU_MMIO_CNTRL_1_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_BASE_LO_0 = 0x5aa1 # macro
mmGCMC_VM_MARC_BASE_LO_0_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_BASE_LO_1 = 0x5aa2 # macro
mmGCMC_VM_MARC_BASE_LO_1_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_BASE_LO_2 = 0x5aa3 # macro
mmGCMC_VM_MARC_BASE_LO_2_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_BASE_LO_3 = 0x5aa4 # macro
mmGCMC_VM_MARC_BASE_LO_3_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_BASE_HI_0 = 0x5aa5 # macro
mmGCMC_VM_MARC_BASE_HI_0_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_BASE_HI_1 = 0x5aa6 # macro
mmGCMC_VM_MARC_BASE_HI_1_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_BASE_HI_2 = 0x5aa7 # macro
mmGCMC_VM_MARC_BASE_HI_2_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_BASE_HI_3 = 0x5aa8 # macro
mmGCMC_VM_MARC_BASE_HI_3_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_RELOC_LO_0 = 0x5aa9 # macro
mmGCMC_VM_MARC_RELOC_LO_0_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_RELOC_LO_1 = 0x5aaa # macro
mmGCMC_VM_MARC_RELOC_LO_1_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_RELOC_LO_2 = 0x5aab # macro
mmGCMC_VM_MARC_RELOC_LO_2_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_RELOC_LO_3 = 0x5aac # macro
mmGCMC_VM_MARC_RELOC_LO_3_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_RELOC_HI_0 = 0x5aad # macro
mmGCMC_VM_MARC_RELOC_HI_0_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_RELOC_HI_1 = 0x5aae # macro
mmGCMC_VM_MARC_RELOC_HI_1_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_RELOC_HI_2 = 0x5aaf # macro
mmGCMC_VM_MARC_RELOC_HI_2_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_RELOC_HI_3 = 0x5ab0 # macro
mmGCMC_VM_MARC_RELOC_HI_3_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_LEN_LO_0 = 0x5ab1 # macro
mmGCMC_VM_MARC_LEN_LO_0_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_LEN_LO_1 = 0x5ab2 # macro
mmGCMC_VM_MARC_LEN_LO_1_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_LEN_LO_2 = 0x5ab3 # macro
mmGCMC_VM_MARC_LEN_LO_2_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_LEN_LO_3 = 0x5ab4 # macro
mmGCMC_VM_MARC_LEN_LO_3_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_LEN_HI_0 = 0x5ab5 # macro
mmGCMC_VM_MARC_LEN_HI_0_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_LEN_HI_1 = 0x5ab6 # macro
mmGCMC_VM_MARC_LEN_HI_1_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_LEN_HI_2 = 0x5ab7 # macro
mmGCMC_VM_MARC_LEN_HI_2_BASE_IDX = 1 # macro
mmGCMC_VM_MARC_LEN_HI_3 = 0x5ab8 # macro
mmGCMC_VM_MARC_LEN_HI_3_BASE_IDX = 1 # macro
mmGCVM_IOMMU_CONTROL_REGISTER = 0x5ab9 # macro
mmGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX = 1 # macro
mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER = 0x5aba # macro
mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX = 1 # macro
mmGCMC_VM_XGMI_GPUIOV_ENABLE = 0x5abb # macro
mmGCMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX = 1 # macro
mmCPG_PSP_DEBUG = 0x5c10 # macro
mmCPG_PSP_DEBUG_BASE_IDX = 1 # macro
mmCPC_PSP_DEBUG = 0x5c11 # macro
mmCPC_PSP_DEBUG_BASE_IDX = 1 # macro
mmGRBM_SEC_CNTL = 0x5e0d # macro
mmGRBM_SEC_CNTL_BASE_IDX = 1 # macro
mmRLC_FWL_FIRST_VIOL_ADDR = 0x5f12 # macro
mmRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX = 1 # macro
mmRLC_SRM_FWL_FIRST_VIOL_ADDR = 0x5f3d # macro
mmRLC_SRM_FWL_FIRST_VIOL_ADDR_BASE_IDX = 1 # macro
mmGCVM_L2_ID_CTRL0 = 0x5dc0 # macro
mmGCVM_L2_ID_CTRL0_BASE_IDX = 1 # macro
mmGCVM_L2_ID_CTRL1 = 0x5dc1 # macro
mmGCVM_L2_ID_CTRL1_BASE_IDX = 1 # macro
mmGCVM_L2_ID_CTRL2 = 0x5dc2 # macro
mmGCVM_L2_ID_CTRL2_BASE_IDX = 1 # macro
mmGCVM_L2_ID_CTRL3 = 0x5dc3 # macro
mmGCVM_L2_ID_CTRL3_BASE_IDX = 1 # macro
mmGCVM_L2_ID_CTRL4 = 0x5dc4 # macro
mmGCVM_L2_ID_CTRL4_BASE_IDX = 1 # macro
mmGCVM_L2_ID_CTRL5 = 0x5dc5 # macro
mmGCVM_L2_ID_CTRL5_BASE_IDX = 1 # macro
mmGCVM_L2_ID_CTRL6 = 0x5dc6 # macro
mmGCVM_L2_ID_CTRL6_BASE_IDX = 1 # macro
mmGCVM_L2_ID_CTRL7 = 0x5dc7 # macro
mmGCVM_L2_ID_CTRL7_BASE_IDX = 1 # macro
mmGCVM_L2_ID_CTRL_HI = 0x5dc8 # macro
mmGCVM_L2_ID_CTRL_HI_BASE_IDX = 1 # macro
mmGCVM_L2_ID_STATUS = 0x5dc9 # macro
mmGCVM_L2_ID_STATUS_BASE_IDX = 1 # macro
mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID = 0x5dcb # macro
mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX = 1 # macro
mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE = 0x5dcd # macro
mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX = 1 # macro
mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO = 0x5dce # macro
mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX = 1 # macro
mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI = 0x5dcf # macro
mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX = 1 # macro
mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO = 0x5dd0 # macro
mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX = 1 # macro
mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI = 0x5dd1 # macro
mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX = 1 # macro
mmSDMA2_DEC_START = 0x0000 # macro
mmSDMA2_DEC_START_BASE_IDX = 2 # macro
mmSDMA2_GLOBAL_TIMESTAMP_LO = 0x000f # macro
mmSDMA2_GLOBAL_TIMESTAMP_LO_BASE_IDX = 2 # macro
mmSDMA2_GLOBAL_TIMESTAMP_HI = 0x0010 # macro
mmSDMA2_GLOBAL_TIMESTAMP_HI_BASE_IDX = 2 # macro
mmSDMA2_PG_CNTL = 0x0016 # macro
mmSDMA2_PG_CNTL_BASE_IDX = 2 # macro
mmSDMA2_PG_CTX_LO = 0x0017 # macro
mmSDMA2_PG_CTX_LO_BASE_IDX = 2 # macro
mmSDMA2_PG_CTX_HI = 0x0018 # macro
mmSDMA2_PG_CTX_HI_BASE_IDX = 2 # macro
mmSDMA2_PG_CTX_CNTL = 0x0019 # macro
mmSDMA2_PG_CTX_CNTL_BASE_IDX = 2 # macro
mmSDMA2_POWER_CNTL = 0x001a # macro
mmSDMA2_POWER_CNTL_BASE_IDX = 2 # macro
mmSDMA2_CLK_CTRL = 0x001b # macro
mmSDMA2_CLK_CTRL_BASE_IDX = 2 # macro
mmSDMA2_CNTL = 0x001c # macro
mmSDMA2_CNTL_BASE_IDX = 2 # macro
mmSDMA2_CHICKEN_BITS = 0x001d # macro
mmSDMA2_CHICKEN_BITS_BASE_IDX = 2 # macro
mmSDMA2_GB_ADDR_CONFIG = 0x001e # macro
mmSDMA2_GB_ADDR_CONFIG_BASE_IDX = 2 # macro
mmSDMA2_GB_ADDR_CONFIG_READ = 0x001f # macro
mmSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX = 2 # macro
mmSDMA2_RB_RPTR_FETCH_HI = 0x0020 # macro
mmSDMA2_RB_RPTR_FETCH_HI_BASE_IDX = 2 # macro
mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL = 0x0021 # macro
mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RB_RPTR_FETCH = 0x0022 # macro
mmSDMA2_RB_RPTR_FETCH_BASE_IDX = 2 # macro
mmSDMA2_IB_OFFSET_FETCH = 0x0023 # macro
mmSDMA2_IB_OFFSET_FETCH_BASE_IDX = 2 # macro
mmSDMA2_PROGRAM = 0x0024 # macro
mmSDMA2_PROGRAM_BASE_IDX = 2 # macro
mmSDMA2_STATUS_REG = 0x0025 # macro
mmSDMA2_STATUS_REG_BASE_IDX = 2 # macro
mmSDMA2_STATUS1_REG = 0x0026 # macro
mmSDMA2_STATUS1_REG_BASE_IDX = 2 # macro
mmSDMA2_RD_BURST_CNTL = 0x0027 # macro
mmSDMA2_RD_BURST_CNTL_BASE_IDX = 2 # macro
mmSDMA2_HBM_PAGE_CONFIG = 0x0028 # macro
mmSDMA2_HBM_PAGE_CONFIG_BASE_IDX = 2 # macro
mmSDMA2_UCODE_CHECKSUM = 0x0029 # macro
mmSDMA2_UCODE_CHECKSUM_BASE_IDX = 2 # macro
mmSDMA2_F32_CNTL = 0x002a # macro
mmSDMA2_F32_CNTL_BASE_IDX = 2 # macro
mmSDMA2_FREEZE = 0x002b # macro
mmSDMA2_FREEZE_BASE_IDX = 2 # macro
mmSDMA2_PHASE0_QUANTUM = 0x002c # macro
mmSDMA2_PHASE0_QUANTUM_BASE_IDX = 2 # macro
mmSDMA2_PHASE1_QUANTUM = 0x002d # macro
mmSDMA2_PHASE1_QUANTUM_BASE_IDX = 2 # macro
mmSDMA2_EDC_CONFIG = 0x0032 # macro
mmSDMA2_EDC_CONFIG_BASE_IDX = 2 # macro
mmSDMA2_BA_THRESHOLD = 0x0033 # macro
mmSDMA2_BA_THRESHOLD_BASE_IDX = 2 # macro
mmSDMA2_ID = 0x0034 # macro
mmSDMA2_ID_BASE_IDX = 2 # macro
mmSDMA2_VERSION = 0x0035 # macro
mmSDMA2_VERSION_BASE_IDX = 2 # macro
mmSDMA2_EDC_COUNTER = 0x0036 # macro
mmSDMA2_EDC_COUNTER_BASE_IDX = 2 # macro
mmSDMA2_EDC_COUNTER_CLEAR = 0x0037 # macro
mmSDMA2_EDC_COUNTER_CLEAR_BASE_IDX = 2 # macro
mmSDMA2_STATUS2_REG = 0x0038 # macro
mmSDMA2_STATUS2_REG_BASE_IDX = 2 # macro
mmSDMA2_ATOMIC_CNTL = 0x0039 # macro
mmSDMA2_ATOMIC_CNTL_BASE_IDX = 2 # macro
mmSDMA2_ATOMIC_PREOP_LO = 0x003a # macro
mmSDMA2_ATOMIC_PREOP_LO_BASE_IDX = 2 # macro
mmSDMA2_ATOMIC_PREOP_HI = 0x003b # macro
mmSDMA2_ATOMIC_PREOP_HI_BASE_IDX = 2 # macro
mmSDMA2_UTCL1_CNTL = 0x003c # macro
mmSDMA2_UTCL1_CNTL_BASE_IDX = 2 # macro
mmSDMA2_UTCL1_WATERMK = 0x003d # macro
mmSDMA2_UTCL1_WATERMK_BASE_IDX = 2 # macro
mmSDMA2_UTCL1_RD_STATUS = 0x003e # macro
mmSDMA2_UTCL1_RD_STATUS_BASE_IDX = 2 # macro
mmSDMA2_UTCL1_WR_STATUS = 0x003f # macro
mmSDMA2_UTCL1_WR_STATUS_BASE_IDX = 2 # macro
mmSDMA2_UTCL1_INV0 = 0x0040 # macro
mmSDMA2_UTCL1_INV0_BASE_IDX = 2 # macro
mmSDMA2_UTCL1_INV1 = 0x0041 # macro
mmSDMA2_UTCL1_INV1_BASE_IDX = 2 # macro
mmSDMA2_UTCL1_INV2 = 0x0042 # macro
mmSDMA2_UTCL1_INV2_BASE_IDX = 2 # macro
mmSDMA2_UTCL1_RD_XNACK0 = 0x0043 # macro
mmSDMA2_UTCL1_RD_XNACK0_BASE_IDX = 2 # macro
mmSDMA2_UTCL1_RD_XNACK1 = 0x0044 # macro
mmSDMA2_UTCL1_RD_XNACK1_BASE_IDX = 2 # macro
mmSDMA2_UTCL1_WR_XNACK0 = 0x0045 # macro
mmSDMA2_UTCL1_WR_XNACK0_BASE_IDX = 2 # macro
mmSDMA2_UTCL1_WR_XNACK1 = 0x0046 # macro
mmSDMA2_UTCL1_WR_XNACK1_BASE_IDX = 2 # macro
mmSDMA2_UTCL1_TIMEOUT = 0x0047 # macro
mmSDMA2_UTCL1_TIMEOUT_BASE_IDX = 2 # macro
mmSDMA2_UTCL1_PAGE = 0x0048 # macro
mmSDMA2_UTCL1_PAGE_BASE_IDX = 2 # macro
mmSDMA2_RELAX_ORDERING_LUT = 0x004a # macro
mmSDMA2_RELAX_ORDERING_LUT_BASE_IDX = 2 # macro
mmSDMA2_CHICKEN_BITS_2 = 0x004b # macro
mmSDMA2_CHICKEN_BITS_2_BASE_IDX = 2 # macro
mmSDMA2_STATUS3_REG = 0x004c # macro
mmSDMA2_STATUS3_REG_BASE_IDX = 2 # macro
mmSDMA2_PHYSICAL_ADDR_LO = 0x004d # macro
mmSDMA2_PHYSICAL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_PHYSICAL_ADDR_HI = 0x004e # macro
mmSDMA2_PHYSICAL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_PHASE2_QUANTUM = 0x004f # macro
mmSDMA2_PHASE2_QUANTUM_BASE_IDX = 2 # macro
mmSDMA2_ERROR_LOG = 0x0050 # macro
mmSDMA2_ERROR_LOG_BASE_IDX = 2 # macro
mmSDMA2_PUB_DUMMY_REG0 = 0x0051 # macro
mmSDMA2_PUB_DUMMY_REG0_BASE_IDX = 2 # macro
mmSDMA2_PUB_DUMMY_REG1 = 0x0052 # macro
mmSDMA2_PUB_DUMMY_REG1_BASE_IDX = 2 # macro
mmSDMA2_PUB_DUMMY_REG2 = 0x0053 # macro
mmSDMA2_PUB_DUMMY_REG2_BASE_IDX = 2 # macro
mmSDMA2_PUB_DUMMY_REG3 = 0x0054 # macro
mmSDMA2_PUB_DUMMY_REG3_BASE_IDX = 2 # macro
mmSDMA2_F32_COUNTER = 0x0055 # macro
mmSDMA2_F32_COUNTER_BASE_IDX = 2 # macro
mmSDMA2_CRD_CNTL = 0x005b # macro
mmSDMA2_CRD_CNTL_BASE_IDX = 2 # macro
mmSDMA2_AQL_STATUS = 0x005f # macro
mmSDMA2_AQL_STATUS_BASE_IDX = 2 # macro
mmSDMA2_EA_DBIT_ADDR_DATA = 0x0060 # macro
mmSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX = 2 # macro
mmSDMA2_EA_DBIT_ADDR_INDEX = 0x0061 # macro
mmSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX = 2 # macro
mmSDMA2_TLBI_GCR_CNTL = 0x0062 # macro
mmSDMA2_TLBI_GCR_CNTL_BASE_IDX = 2 # macro
mmSDMA2_TILING_CONFIG = 0x0063 # macro
mmSDMA2_TILING_CONFIG_BASE_IDX = 2 # macro
mmSDMA2_INT_STATUS = 0x0070 # macro
mmSDMA2_INT_STATUS_BASE_IDX = 2 # macro
mmSDMA2_HOLE_ADDR_LO = 0x0072 # macro
mmSDMA2_HOLE_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_HOLE_ADDR_HI = 0x0073 # macro
mmSDMA2_HOLE_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_CLOCK_GATING_REG = 0x0075 # macro
mmSDMA2_CLOCK_GATING_REG_BASE_IDX = 2 # macro
mmSDMA2_STATUS4_REG = 0x0076 # macro
mmSDMA2_STATUS4_REG_BASE_IDX = 2 # macro
mmSDMA2_SCRATCH_RAM_DATA = 0x0077 # macro
mmSDMA2_SCRATCH_RAM_DATA_BASE_IDX = 2 # macro
mmSDMA2_SCRATCH_RAM_ADDR = 0x0078 # macro
mmSDMA2_SCRATCH_RAM_ADDR_BASE_IDX = 2 # macro
mmSDMA2_TIMESTAMP_CNTL = 0x0079 # macro
mmSDMA2_TIMESTAMP_CNTL_BASE_IDX = 2 # macro
mmSDMA2_STATUS5_REG = 0x007a # macro
mmSDMA2_STATUS5_REG_BASE_IDX = 2 # macro
mmSDMA2_QUEUE_RESET_REQ = 0x007b # macro
mmSDMA2_QUEUE_RESET_REQ_BASE_IDX = 2 # macro
mmSDMA2_GFX_RB_CNTL = 0x0080 # macro
mmSDMA2_GFX_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_GFX_RB_BASE = 0x0081 # macro
mmSDMA2_GFX_RB_BASE_BASE_IDX = 2 # macro
mmSDMA2_GFX_RB_BASE_HI = 0x0082 # macro
mmSDMA2_GFX_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_GFX_RB_RPTR = 0x0083 # macro
mmSDMA2_GFX_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_GFX_RB_RPTR_HI = 0x0084 # macro
mmSDMA2_GFX_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_GFX_RB_WPTR = 0x0085 # macro
mmSDMA2_GFX_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA2_GFX_RB_WPTR_HI = 0x0086 # macro
mmSDMA2_GFX_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_GFX_RB_WPTR_POLL_CNTL = 0x0087 # macro
mmSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_GFX_RB_RPTR_ADDR_HI = 0x0088 # macro
mmSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_GFX_RB_RPTR_ADDR_LO = 0x0089 # macro
mmSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_GFX_IB_CNTL = 0x008a # macro
mmSDMA2_GFX_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_GFX_IB_RPTR = 0x008b # macro
mmSDMA2_GFX_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_GFX_IB_OFFSET = 0x008c # macro
mmSDMA2_GFX_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_GFX_IB_BASE_LO = 0x008d # macro
mmSDMA2_GFX_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA2_GFX_IB_BASE_HI = 0x008e # macro
mmSDMA2_GFX_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_GFX_IB_SIZE = 0x008f # macro
mmSDMA2_GFX_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA2_GFX_SKIP_CNTL = 0x0090 # macro
mmSDMA2_GFX_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA2_GFX_CONTEXT_STATUS = 0x0091 # macro
mmSDMA2_GFX_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA2_GFX_DOORBELL = 0x0092 # macro
mmSDMA2_GFX_DOORBELL_BASE_IDX = 2 # macro
mmSDMA2_GFX_CONTEXT_CNTL = 0x0093 # macro
mmSDMA2_GFX_CONTEXT_CNTL_BASE_IDX = 2 # macro
mmSDMA2_GFX_STATUS = 0x00a8 # macro
mmSDMA2_GFX_STATUS_BASE_IDX = 2 # macro
mmSDMA2_GFX_DOORBELL_LOG = 0x00a9 # macro
mmSDMA2_GFX_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA2_GFX_WATERMARK = 0x00aa # macro
mmSDMA2_GFX_WATERMARK_BASE_IDX = 2 # macro
mmSDMA2_GFX_DOORBELL_OFFSET = 0x00ab # macro
mmSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_GFX_CSA_ADDR_LO = 0x00ac # macro
mmSDMA2_GFX_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_GFX_CSA_ADDR_HI = 0x00ad # macro
mmSDMA2_GFX_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_GFX_IB_SUB_REMAIN = 0x00af # macro
mmSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA2_GFX_PREEMPT = 0x00b0 # macro
mmSDMA2_GFX_PREEMPT_BASE_IDX = 2 # macro
mmSDMA2_GFX_DUMMY_REG = 0x00b1 # macro
mmSDMA2_GFX_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI = 0x00b2 # macro
mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO = 0x00b3 # macro
mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_GFX_RB_AQL_CNTL = 0x00b4 # macro
mmSDMA2_GFX_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_GFX_MINOR_PTR_UPDATE = 0x00b5 # macro
mmSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA2_GFX_MIDCMD_DATA0 = 0x00c0 # macro
mmSDMA2_GFX_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA2_GFX_MIDCMD_DATA1 = 0x00c1 # macro
mmSDMA2_GFX_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA2_GFX_MIDCMD_DATA2 = 0x00c2 # macro
mmSDMA2_GFX_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA2_GFX_MIDCMD_DATA3 = 0x00c3 # macro
mmSDMA2_GFX_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA2_GFX_MIDCMD_DATA4 = 0x00c4 # macro
mmSDMA2_GFX_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA2_GFX_MIDCMD_DATA5 = 0x00c5 # macro
mmSDMA2_GFX_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA2_GFX_MIDCMD_DATA6 = 0x00c6 # macro
mmSDMA2_GFX_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA2_GFX_MIDCMD_DATA7 = 0x00c7 # macro
mmSDMA2_GFX_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA2_GFX_MIDCMD_DATA8 = 0x00c8 # macro
mmSDMA2_GFX_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA2_GFX_MIDCMD_DATA9 = 0x00c9 # macro
mmSDMA2_GFX_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA2_GFX_MIDCMD_DATA10 = 0x00ca # macro
mmSDMA2_GFX_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA2_GFX_MIDCMD_CNTL = 0x00cb # macro
mmSDMA2_GFX_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA2_PAGE_RB_CNTL = 0x00d8 # macro
mmSDMA2_PAGE_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_PAGE_RB_BASE = 0x00d9 # macro
mmSDMA2_PAGE_RB_BASE_BASE_IDX = 2 # macro
mmSDMA2_PAGE_RB_BASE_HI = 0x00da # macro
mmSDMA2_PAGE_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_PAGE_RB_RPTR = 0x00db # macro
mmSDMA2_PAGE_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_PAGE_RB_RPTR_HI = 0x00dc # macro
mmSDMA2_PAGE_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_PAGE_RB_WPTR = 0x00dd # macro
mmSDMA2_PAGE_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA2_PAGE_RB_WPTR_HI = 0x00de # macro
mmSDMA2_PAGE_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_PAGE_RB_WPTR_POLL_CNTL = 0x00df # macro
mmSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_PAGE_RB_RPTR_ADDR_HI = 0x00e0 # macro
mmSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_PAGE_RB_RPTR_ADDR_LO = 0x00e1 # macro
mmSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_PAGE_IB_CNTL = 0x00e2 # macro
mmSDMA2_PAGE_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_PAGE_IB_RPTR = 0x00e3 # macro
mmSDMA2_PAGE_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_PAGE_IB_OFFSET = 0x00e4 # macro
mmSDMA2_PAGE_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_PAGE_IB_BASE_LO = 0x00e5 # macro
mmSDMA2_PAGE_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA2_PAGE_IB_BASE_HI = 0x00e6 # macro
mmSDMA2_PAGE_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_PAGE_IB_SIZE = 0x00e7 # macro
mmSDMA2_PAGE_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA2_PAGE_SKIP_CNTL = 0x00e8 # macro
mmSDMA2_PAGE_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA2_PAGE_CONTEXT_STATUS = 0x00e9 # macro
mmSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA2_PAGE_DOORBELL = 0x00ea # macro
mmSDMA2_PAGE_DOORBELL_BASE_IDX = 2 # macro
mmSDMA2_PAGE_STATUS = 0x0100 # macro
mmSDMA2_PAGE_STATUS_BASE_IDX = 2 # macro
mmSDMA2_PAGE_DOORBELL_LOG = 0x0101 # macro
mmSDMA2_PAGE_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA2_PAGE_WATERMARK = 0x0102 # macro
mmSDMA2_PAGE_WATERMARK_BASE_IDX = 2 # macro
mmSDMA2_PAGE_DOORBELL_OFFSET = 0x0103 # macro
mmSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_PAGE_CSA_ADDR_LO = 0x0104 # macro
mmSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_PAGE_CSA_ADDR_HI = 0x0105 # macro
mmSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_PAGE_IB_SUB_REMAIN = 0x0107 # macro
mmSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA2_PAGE_PREEMPT = 0x0108 # macro
mmSDMA2_PAGE_PREEMPT_BASE_IDX = 2 # macro
mmSDMA2_PAGE_DUMMY_REG = 0x0109 # macro
mmSDMA2_PAGE_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI = 0x010a # macro
mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO = 0x010b # macro
mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_PAGE_RB_AQL_CNTL = 0x010c # macro
mmSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_PAGE_MINOR_PTR_UPDATE = 0x010d # macro
mmSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA2_PAGE_MIDCMD_DATA0 = 0x0118 # macro
mmSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA2_PAGE_MIDCMD_DATA1 = 0x0119 # macro
mmSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA2_PAGE_MIDCMD_DATA2 = 0x011a # macro
mmSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA2_PAGE_MIDCMD_DATA3 = 0x011b # macro
mmSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA2_PAGE_MIDCMD_DATA4 = 0x011c # macro
mmSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA2_PAGE_MIDCMD_DATA5 = 0x011d # macro
mmSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA2_PAGE_MIDCMD_DATA6 = 0x011e # macro
mmSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA2_PAGE_MIDCMD_DATA7 = 0x011f # macro
mmSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA2_PAGE_MIDCMD_DATA8 = 0x0120 # macro
mmSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA2_PAGE_MIDCMD_DATA9 = 0x0121 # macro
mmSDMA2_PAGE_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA2_PAGE_MIDCMD_DATA10 = 0x0122 # macro
mmSDMA2_PAGE_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA2_PAGE_MIDCMD_CNTL = 0x0123 # macro
mmSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC0_RB_CNTL = 0x0130 # macro
mmSDMA2_RLC0_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC0_RB_BASE = 0x0131 # macro
mmSDMA2_RLC0_RB_BASE_BASE_IDX = 2 # macro
mmSDMA2_RLC0_RB_BASE_HI = 0x0132 # macro
mmSDMA2_RLC0_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC0_RB_RPTR = 0x0133 # macro
mmSDMA2_RLC0_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC0_RB_RPTR_HI = 0x0134 # macro
mmSDMA2_RLC0_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC0_RB_WPTR = 0x0135 # macro
mmSDMA2_RLC0_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC0_RB_WPTR_HI = 0x0136 # macro
mmSDMA2_RLC0_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC0_RB_WPTR_POLL_CNTL = 0x0137 # macro
mmSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC0_RB_RPTR_ADDR_HI = 0x0138 # macro
mmSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC0_RB_RPTR_ADDR_LO = 0x0139 # macro
mmSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC0_IB_CNTL = 0x013a # macro
mmSDMA2_RLC0_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC0_IB_RPTR = 0x013b # macro
mmSDMA2_RLC0_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC0_IB_OFFSET = 0x013c # macro
mmSDMA2_RLC0_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC0_IB_BASE_LO = 0x013d # macro
mmSDMA2_RLC0_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC0_IB_BASE_HI = 0x013e # macro
mmSDMA2_RLC0_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC0_IB_SIZE = 0x013f # macro
mmSDMA2_RLC0_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA2_RLC0_SKIP_CNTL = 0x0140 # macro
mmSDMA2_RLC0_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC0_CONTEXT_STATUS = 0x0141 # macro
mmSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC0_DOORBELL = 0x0142 # macro
mmSDMA2_RLC0_DOORBELL_BASE_IDX = 2 # macro
mmSDMA2_RLC0_STATUS = 0x0158 # macro
mmSDMA2_RLC0_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC0_DOORBELL_LOG = 0x0159 # macro
mmSDMA2_RLC0_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA2_RLC0_WATERMARK = 0x015a # macro
mmSDMA2_RLC0_WATERMARK_BASE_IDX = 2 # macro
mmSDMA2_RLC0_DOORBELL_OFFSET = 0x015b # macro
mmSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC0_CSA_ADDR_LO = 0x015c # macro
mmSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC0_CSA_ADDR_HI = 0x015d # macro
mmSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC0_IB_SUB_REMAIN = 0x015f # macro
mmSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA2_RLC0_PREEMPT = 0x0160 # macro
mmSDMA2_RLC0_PREEMPT_BASE_IDX = 2 # macro
mmSDMA2_RLC0_DUMMY_REG = 0x0161 # macro
mmSDMA2_RLC0_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI = 0x0162 # macro
mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO = 0x0163 # macro
mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC0_RB_AQL_CNTL = 0x0164 # macro
mmSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC0_MINOR_PTR_UPDATE = 0x0165 # macro
mmSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA2_RLC0_MIDCMD_DATA0 = 0x0170 # macro
mmSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA2_RLC0_MIDCMD_DATA1 = 0x0171 # macro
mmSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA2_RLC0_MIDCMD_DATA2 = 0x0172 # macro
mmSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA2_RLC0_MIDCMD_DATA3 = 0x0173 # macro
mmSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA2_RLC0_MIDCMD_DATA4 = 0x0174 # macro
mmSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA2_RLC0_MIDCMD_DATA5 = 0x0175 # macro
mmSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA2_RLC0_MIDCMD_DATA6 = 0x0176 # macro
mmSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA2_RLC0_MIDCMD_DATA7 = 0x0177 # macro
mmSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA2_RLC0_MIDCMD_DATA8 = 0x0178 # macro
mmSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA2_RLC0_MIDCMD_DATA9 = 0x0179 # macro
mmSDMA2_RLC0_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA2_RLC0_MIDCMD_DATA10 = 0x017a # macro
mmSDMA2_RLC0_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA2_RLC0_MIDCMD_CNTL = 0x017b # macro
mmSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC1_RB_CNTL = 0x0188 # macro
mmSDMA2_RLC1_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC1_RB_BASE = 0x0189 # macro
mmSDMA2_RLC1_RB_BASE_BASE_IDX = 2 # macro
mmSDMA2_RLC1_RB_BASE_HI = 0x018a # macro
mmSDMA2_RLC1_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC1_RB_RPTR = 0x018b # macro
mmSDMA2_RLC1_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC1_RB_RPTR_HI = 0x018c # macro
mmSDMA2_RLC1_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC1_RB_WPTR = 0x018d # macro
mmSDMA2_RLC1_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC1_RB_WPTR_HI = 0x018e # macro
mmSDMA2_RLC1_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC1_RB_WPTR_POLL_CNTL = 0x018f # macro
mmSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC1_RB_RPTR_ADDR_HI = 0x0190 # macro
mmSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC1_RB_RPTR_ADDR_LO = 0x0191 # macro
mmSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC1_IB_CNTL = 0x0192 # macro
mmSDMA2_RLC1_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC1_IB_RPTR = 0x0193 # macro
mmSDMA2_RLC1_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC1_IB_OFFSET = 0x0194 # macro
mmSDMA2_RLC1_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC1_IB_BASE_LO = 0x0195 # macro
mmSDMA2_RLC1_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC1_IB_BASE_HI = 0x0196 # macro
mmSDMA2_RLC1_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC1_IB_SIZE = 0x0197 # macro
mmSDMA2_RLC1_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA2_RLC1_SKIP_CNTL = 0x0198 # macro
mmSDMA2_RLC1_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC1_CONTEXT_STATUS = 0x0199 # macro
mmSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC1_DOORBELL = 0x019a # macro
mmSDMA2_RLC1_DOORBELL_BASE_IDX = 2 # macro
mmSDMA2_RLC1_STATUS = 0x01b0 # macro
mmSDMA2_RLC1_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC1_DOORBELL_LOG = 0x01b1 # macro
mmSDMA2_RLC1_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA2_RLC1_WATERMARK = 0x01b2 # macro
mmSDMA2_RLC1_WATERMARK_BASE_IDX = 2 # macro
mmSDMA2_RLC1_DOORBELL_OFFSET = 0x01b3 # macro
mmSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC1_CSA_ADDR_LO = 0x01b4 # macro
mmSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC1_CSA_ADDR_HI = 0x01b5 # macro
mmSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC1_IB_SUB_REMAIN = 0x01b7 # macro
mmSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA2_RLC1_PREEMPT = 0x01b8 # macro
mmSDMA2_RLC1_PREEMPT_BASE_IDX = 2 # macro
mmSDMA2_RLC1_DUMMY_REG = 0x01b9 # macro
mmSDMA2_RLC1_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI = 0x01ba # macro
mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO = 0x01bb # macro
mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC1_RB_AQL_CNTL = 0x01bc # macro
mmSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC1_MINOR_PTR_UPDATE = 0x01bd # macro
mmSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA2_RLC1_MIDCMD_DATA0 = 0x01c8 # macro
mmSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA2_RLC1_MIDCMD_DATA1 = 0x01c9 # macro
mmSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA2_RLC1_MIDCMD_DATA2 = 0x01ca # macro
mmSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA2_RLC1_MIDCMD_DATA3 = 0x01cb # macro
mmSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA2_RLC1_MIDCMD_DATA4 = 0x01cc # macro
mmSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA2_RLC1_MIDCMD_DATA5 = 0x01cd # macro
mmSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA2_RLC1_MIDCMD_DATA6 = 0x01ce # macro
mmSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA2_RLC1_MIDCMD_DATA7 = 0x01cf # macro
mmSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA2_RLC1_MIDCMD_DATA8 = 0x01d0 # macro
mmSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA2_RLC1_MIDCMD_DATA9 = 0x01d1 # macro
mmSDMA2_RLC1_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA2_RLC1_MIDCMD_DATA10 = 0x01d2 # macro
mmSDMA2_RLC1_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA2_RLC1_MIDCMD_CNTL = 0x01d3 # macro
mmSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC2_RB_CNTL = 0x01e0 # macro
mmSDMA2_RLC2_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC2_RB_BASE = 0x01e1 # macro
mmSDMA2_RLC2_RB_BASE_BASE_IDX = 2 # macro
mmSDMA2_RLC2_RB_BASE_HI = 0x01e2 # macro
mmSDMA2_RLC2_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC2_RB_RPTR = 0x01e3 # macro
mmSDMA2_RLC2_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC2_RB_RPTR_HI = 0x01e4 # macro
mmSDMA2_RLC2_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC2_RB_WPTR = 0x01e5 # macro
mmSDMA2_RLC2_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC2_RB_WPTR_HI = 0x01e6 # macro
mmSDMA2_RLC2_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC2_RB_WPTR_POLL_CNTL = 0x01e7 # macro
mmSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC2_RB_RPTR_ADDR_HI = 0x01e8 # macro
mmSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC2_RB_RPTR_ADDR_LO = 0x01e9 # macro
mmSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC2_IB_CNTL = 0x01ea # macro
mmSDMA2_RLC2_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC2_IB_RPTR = 0x01eb # macro
mmSDMA2_RLC2_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC2_IB_OFFSET = 0x01ec # macro
mmSDMA2_RLC2_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC2_IB_BASE_LO = 0x01ed # macro
mmSDMA2_RLC2_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC2_IB_BASE_HI = 0x01ee # macro
mmSDMA2_RLC2_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC2_IB_SIZE = 0x01ef # macro
mmSDMA2_RLC2_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA2_RLC2_SKIP_CNTL = 0x01f0 # macro
mmSDMA2_RLC2_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC2_CONTEXT_STATUS = 0x01f1 # macro
mmSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC2_DOORBELL = 0x01f2 # macro
mmSDMA2_RLC2_DOORBELL_BASE_IDX = 2 # macro
mmSDMA2_RLC2_STATUS = 0x0208 # macro
mmSDMA2_RLC2_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC2_DOORBELL_LOG = 0x0209 # macro
mmSDMA2_RLC2_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA2_RLC2_WATERMARK = 0x020a # macro
mmSDMA2_RLC2_WATERMARK_BASE_IDX = 2 # macro
mmSDMA2_RLC2_DOORBELL_OFFSET = 0x020b # macro
mmSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC2_CSA_ADDR_LO = 0x020c # macro
mmSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC2_CSA_ADDR_HI = 0x020d # macro
mmSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC2_IB_SUB_REMAIN = 0x020f # macro
mmSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA2_RLC2_PREEMPT = 0x0210 # macro
mmSDMA2_RLC2_PREEMPT_BASE_IDX = 2 # macro
mmSDMA2_RLC2_DUMMY_REG = 0x0211 # macro
mmSDMA2_RLC2_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI = 0x0212 # macro
mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO = 0x0213 # macro
mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC2_RB_AQL_CNTL = 0x0214 # macro
mmSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC2_MINOR_PTR_UPDATE = 0x0215 # macro
mmSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA2_RLC2_MIDCMD_DATA0 = 0x0220 # macro
mmSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA2_RLC2_MIDCMD_DATA1 = 0x0221 # macro
mmSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA2_RLC2_MIDCMD_DATA2 = 0x0222 # macro
mmSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA2_RLC2_MIDCMD_DATA3 = 0x0223 # macro
mmSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA2_RLC2_MIDCMD_DATA4 = 0x0224 # macro
mmSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA2_RLC2_MIDCMD_DATA5 = 0x0225 # macro
mmSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA2_RLC2_MIDCMD_DATA6 = 0x0226 # macro
mmSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA2_RLC2_MIDCMD_DATA7 = 0x0227 # macro
mmSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA2_RLC2_MIDCMD_DATA8 = 0x0228 # macro
mmSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA2_RLC2_MIDCMD_DATA9 = 0x0229 # macro
mmSDMA2_RLC2_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA2_RLC2_MIDCMD_DATA10 = 0x022a # macro
mmSDMA2_RLC2_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA2_RLC2_MIDCMD_CNTL = 0x022b # macro
mmSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC3_RB_CNTL = 0x0238 # macro
mmSDMA2_RLC3_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC3_RB_BASE = 0x0239 # macro
mmSDMA2_RLC3_RB_BASE_BASE_IDX = 2 # macro
mmSDMA2_RLC3_RB_BASE_HI = 0x023a # macro
mmSDMA2_RLC3_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC3_RB_RPTR = 0x023b # macro
mmSDMA2_RLC3_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC3_RB_RPTR_HI = 0x023c # macro
mmSDMA2_RLC3_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC3_RB_WPTR = 0x023d # macro
mmSDMA2_RLC3_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC3_RB_WPTR_HI = 0x023e # macro
mmSDMA2_RLC3_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC3_RB_WPTR_POLL_CNTL = 0x023f # macro
mmSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC3_RB_RPTR_ADDR_HI = 0x0240 # macro
mmSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC3_RB_RPTR_ADDR_LO = 0x0241 # macro
mmSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC3_IB_CNTL = 0x0242 # macro
mmSDMA2_RLC3_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC3_IB_RPTR = 0x0243 # macro
mmSDMA2_RLC3_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC3_IB_OFFSET = 0x0244 # macro
mmSDMA2_RLC3_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC3_IB_BASE_LO = 0x0245 # macro
mmSDMA2_RLC3_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC3_IB_BASE_HI = 0x0246 # macro
mmSDMA2_RLC3_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC3_IB_SIZE = 0x0247 # macro
mmSDMA2_RLC3_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA2_RLC3_SKIP_CNTL = 0x0248 # macro
mmSDMA2_RLC3_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC3_CONTEXT_STATUS = 0x0249 # macro
mmSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC3_DOORBELL = 0x024a # macro
mmSDMA2_RLC3_DOORBELL_BASE_IDX = 2 # macro
mmSDMA2_RLC3_STATUS = 0x0260 # macro
mmSDMA2_RLC3_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC3_DOORBELL_LOG = 0x0261 # macro
mmSDMA2_RLC3_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA2_RLC3_WATERMARK = 0x0262 # macro
mmSDMA2_RLC3_WATERMARK_BASE_IDX = 2 # macro
mmSDMA2_RLC3_DOORBELL_OFFSET = 0x0263 # macro
mmSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC3_CSA_ADDR_LO = 0x0264 # macro
mmSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC3_CSA_ADDR_HI = 0x0265 # macro
mmSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC3_IB_SUB_REMAIN = 0x0267 # macro
mmSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA2_RLC3_PREEMPT = 0x0268 # macro
mmSDMA2_RLC3_PREEMPT_BASE_IDX = 2 # macro
mmSDMA2_RLC3_DUMMY_REG = 0x0269 # macro
mmSDMA2_RLC3_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI = 0x026a # macro
mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO = 0x026b # macro
mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC3_RB_AQL_CNTL = 0x026c # macro
mmSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC3_MINOR_PTR_UPDATE = 0x026d # macro
mmSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA2_RLC3_MIDCMD_DATA0 = 0x0278 # macro
mmSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA2_RLC3_MIDCMD_DATA1 = 0x0279 # macro
mmSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA2_RLC3_MIDCMD_DATA2 = 0x027a # macro
mmSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA2_RLC3_MIDCMD_DATA3 = 0x027b # macro
mmSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA2_RLC3_MIDCMD_DATA4 = 0x027c # macro
mmSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA2_RLC3_MIDCMD_DATA5 = 0x027d # macro
mmSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA2_RLC3_MIDCMD_DATA6 = 0x027e # macro
mmSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA2_RLC3_MIDCMD_DATA7 = 0x027f # macro
mmSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA2_RLC3_MIDCMD_DATA8 = 0x0280 # macro
mmSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA2_RLC3_MIDCMD_DATA9 = 0x0281 # macro
mmSDMA2_RLC3_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA2_RLC3_MIDCMD_DATA10 = 0x0282 # macro
mmSDMA2_RLC3_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA2_RLC3_MIDCMD_CNTL = 0x0283 # macro
mmSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC4_RB_CNTL = 0x0290 # macro
mmSDMA2_RLC4_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC4_RB_BASE = 0x0291 # macro
mmSDMA2_RLC4_RB_BASE_BASE_IDX = 2 # macro
mmSDMA2_RLC4_RB_BASE_HI = 0x0292 # macro
mmSDMA2_RLC4_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC4_RB_RPTR = 0x0293 # macro
mmSDMA2_RLC4_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC4_RB_RPTR_HI = 0x0294 # macro
mmSDMA2_RLC4_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC4_RB_WPTR = 0x0295 # macro
mmSDMA2_RLC4_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC4_RB_WPTR_HI = 0x0296 # macro
mmSDMA2_RLC4_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC4_RB_WPTR_POLL_CNTL = 0x0297 # macro
mmSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC4_RB_RPTR_ADDR_HI = 0x0298 # macro
mmSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC4_RB_RPTR_ADDR_LO = 0x0299 # macro
mmSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC4_IB_CNTL = 0x029a # macro
mmSDMA2_RLC4_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC4_IB_RPTR = 0x029b # macro
mmSDMA2_RLC4_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC4_IB_OFFSET = 0x029c # macro
mmSDMA2_RLC4_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC4_IB_BASE_LO = 0x029d # macro
mmSDMA2_RLC4_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC4_IB_BASE_HI = 0x029e # macro
mmSDMA2_RLC4_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC4_IB_SIZE = 0x029f # macro
mmSDMA2_RLC4_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA2_RLC4_SKIP_CNTL = 0x02a0 # macro
mmSDMA2_RLC4_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC4_CONTEXT_STATUS = 0x02a1 # macro
mmSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC4_DOORBELL = 0x02a2 # macro
mmSDMA2_RLC4_DOORBELL_BASE_IDX = 2 # macro
mmSDMA2_RLC4_STATUS = 0x02b8 # macro
mmSDMA2_RLC4_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC4_DOORBELL_LOG = 0x02b9 # macro
mmSDMA2_RLC4_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA2_RLC4_WATERMARK = 0x02ba # macro
mmSDMA2_RLC4_WATERMARK_BASE_IDX = 2 # macro
mmSDMA2_RLC4_DOORBELL_OFFSET = 0x02bb # macro
mmSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC4_CSA_ADDR_LO = 0x02bc # macro
mmSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC4_CSA_ADDR_HI = 0x02bd # macro
mmSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC4_IB_SUB_REMAIN = 0x02bf # macro
mmSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA2_RLC4_PREEMPT = 0x02c0 # macro
mmSDMA2_RLC4_PREEMPT_BASE_IDX = 2 # macro
mmSDMA2_RLC4_DUMMY_REG = 0x02c1 # macro
mmSDMA2_RLC4_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI = 0x02c2 # macro
mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO = 0x02c3 # macro
mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC4_RB_AQL_CNTL = 0x02c4 # macro
mmSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC4_MINOR_PTR_UPDATE = 0x02c5 # macro
mmSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA2_RLC4_MIDCMD_DATA0 = 0x02d0 # macro
mmSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA2_RLC4_MIDCMD_DATA1 = 0x02d1 # macro
mmSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA2_RLC4_MIDCMD_DATA2 = 0x02d2 # macro
mmSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA2_RLC4_MIDCMD_DATA3 = 0x02d3 # macro
mmSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA2_RLC4_MIDCMD_DATA4 = 0x02d4 # macro
mmSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA2_RLC4_MIDCMD_DATA5 = 0x02d5 # macro
mmSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA2_RLC4_MIDCMD_DATA6 = 0x02d6 # macro
mmSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA2_RLC4_MIDCMD_DATA7 = 0x02d7 # macro
mmSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA2_RLC4_MIDCMD_DATA8 = 0x02d8 # macro
mmSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA2_RLC4_MIDCMD_DATA9 = 0x02d9 # macro
mmSDMA2_RLC4_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA2_RLC4_MIDCMD_DATA10 = 0x02da # macro
mmSDMA2_RLC4_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA2_RLC4_MIDCMD_CNTL = 0x02db # macro
mmSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC5_RB_CNTL = 0x02e8 # macro
mmSDMA2_RLC5_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC5_RB_BASE = 0x02e9 # macro
mmSDMA2_RLC5_RB_BASE_BASE_IDX = 2 # macro
mmSDMA2_RLC5_RB_BASE_HI = 0x02ea # macro
mmSDMA2_RLC5_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC5_RB_RPTR = 0x02eb # macro
mmSDMA2_RLC5_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC5_RB_RPTR_HI = 0x02ec # macro
mmSDMA2_RLC5_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC5_RB_WPTR = 0x02ed # macro
mmSDMA2_RLC5_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC5_RB_WPTR_HI = 0x02ee # macro
mmSDMA2_RLC5_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC5_RB_WPTR_POLL_CNTL = 0x02ef # macro
mmSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC5_RB_RPTR_ADDR_HI = 0x02f0 # macro
mmSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC5_RB_RPTR_ADDR_LO = 0x02f1 # macro
mmSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC5_IB_CNTL = 0x02f2 # macro
mmSDMA2_RLC5_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC5_IB_RPTR = 0x02f3 # macro
mmSDMA2_RLC5_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC5_IB_OFFSET = 0x02f4 # macro
mmSDMA2_RLC5_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC5_IB_BASE_LO = 0x02f5 # macro
mmSDMA2_RLC5_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC5_IB_BASE_HI = 0x02f6 # macro
mmSDMA2_RLC5_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC5_IB_SIZE = 0x02f7 # macro
mmSDMA2_RLC5_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA2_RLC5_SKIP_CNTL = 0x02f8 # macro
mmSDMA2_RLC5_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC5_CONTEXT_STATUS = 0x02f9 # macro
mmSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC5_DOORBELL = 0x02fa # macro
mmSDMA2_RLC5_DOORBELL_BASE_IDX = 2 # macro
mmSDMA2_RLC5_STATUS = 0x0310 # macro
mmSDMA2_RLC5_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC5_DOORBELL_LOG = 0x0311 # macro
mmSDMA2_RLC5_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA2_RLC5_WATERMARK = 0x0312 # macro
mmSDMA2_RLC5_WATERMARK_BASE_IDX = 2 # macro
mmSDMA2_RLC5_DOORBELL_OFFSET = 0x0313 # macro
mmSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC5_CSA_ADDR_LO = 0x0314 # macro
mmSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC5_CSA_ADDR_HI = 0x0315 # macro
mmSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC5_IB_SUB_REMAIN = 0x0317 # macro
mmSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA2_RLC5_PREEMPT = 0x0318 # macro
mmSDMA2_RLC5_PREEMPT_BASE_IDX = 2 # macro
mmSDMA2_RLC5_DUMMY_REG = 0x0319 # macro
mmSDMA2_RLC5_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI = 0x031a # macro
mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO = 0x031b # macro
mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC5_RB_AQL_CNTL = 0x031c # macro
mmSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC5_MINOR_PTR_UPDATE = 0x031d # macro
mmSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA2_RLC5_MIDCMD_DATA0 = 0x0328 # macro
mmSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA2_RLC5_MIDCMD_DATA1 = 0x0329 # macro
mmSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA2_RLC5_MIDCMD_DATA2 = 0x032a # macro
mmSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA2_RLC5_MIDCMD_DATA3 = 0x032b # macro
mmSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA2_RLC5_MIDCMD_DATA4 = 0x032c # macro
mmSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA2_RLC5_MIDCMD_DATA5 = 0x032d # macro
mmSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA2_RLC5_MIDCMD_DATA6 = 0x032e # macro
mmSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA2_RLC5_MIDCMD_DATA7 = 0x032f # macro
mmSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA2_RLC5_MIDCMD_DATA8 = 0x0330 # macro
mmSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA2_RLC5_MIDCMD_DATA9 = 0x0331 # macro
mmSDMA2_RLC5_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA2_RLC5_MIDCMD_DATA10 = 0x0332 # macro
mmSDMA2_RLC5_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA2_RLC5_MIDCMD_CNTL = 0x0333 # macro
mmSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC6_RB_CNTL = 0x0340 # macro
mmSDMA2_RLC6_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC6_RB_BASE = 0x0341 # macro
mmSDMA2_RLC6_RB_BASE_BASE_IDX = 2 # macro
mmSDMA2_RLC6_RB_BASE_HI = 0x0342 # macro
mmSDMA2_RLC6_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC6_RB_RPTR = 0x0343 # macro
mmSDMA2_RLC6_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC6_RB_RPTR_HI = 0x0344 # macro
mmSDMA2_RLC6_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC6_RB_WPTR = 0x0345 # macro
mmSDMA2_RLC6_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC6_RB_WPTR_HI = 0x0346 # macro
mmSDMA2_RLC6_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC6_RB_WPTR_POLL_CNTL = 0x0347 # macro
mmSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC6_RB_RPTR_ADDR_HI = 0x0348 # macro
mmSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC6_RB_RPTR_ADDR_LO = 0x0349 # macro
mmSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC6_IB_CNTL = 0x034a # macro
mmSDMA2_RLC6_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC6_IB_RPTR = 0x034b # macro
mmSDMA2_RLC6_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC6_IB_OFFSET = 0x034c # macro
mmSDMA2_RLC6_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC6_IB_BASE_LO = 0x034d # macro
mmSDMA2_RLC6_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC6_IB_BASE_HI = 0x034e # macro
mmSDMA2_RLC6_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC6_IB_SIZE = 0x034f # macro
mmSDMA2_RLC6_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA2_RLC6_SKIP_CNTL = 0x0350 # macro
mmSDMA2_RLC6_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC6_CONTEXT_STATUS = 0x0351 # macro
mmSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC6_DOORBELL = 0x0352 # macro
mmSDMA2_RLC6_DOORBELL_BASE_IDX = 2 # macro
mmSDMA2_RLC6_STATUS = 0x0368 # macro
mmSDMA2_RLC6_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC6_DOORBELL_LOG = 0x0369 # macro
mmSDMA2_RLC6_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA2_RLC6_WATERMARK = 0x036a # macro
mmSDMA2_RLC6_WATERMARK_BASE_IDX = 2 # macro
mmSDMA2_RLC6_DOORBELL_OFFSET = 0x036b # macro
mmSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC6_CSA_ADDR_LO = 0x036c # macro
mmSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC6_CSA_ADDR_HI = 0x036d # macro
mmSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC6_IB_SUB_REMAIN = 0x036f # macro
mmSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA2_RLC6_PREEMPT = 0x0370 # macro
mmSDMA2_RLC6_PREEMPT_BASE_IDX = 2 # macro
mmSDMA2_RLC6_DUMMY_REG = 0x0371 # macro
mmSDMA2_RLC6_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI = 0x0372 # macro
mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO = 0x0373 # macro
mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC6_RB_AQL_CNTL = 0x0374 # macro
mmSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC6_MINOR_PTR_UPDATE = 0x0375 # macro
mmSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA2_RLC6_MIDCMD_DATA0 = 0x0380 # macro
mmSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA2_RLC6_MIDCMD_DATA1 = 0x0381 # macro
mmSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA2_RLC6_MIDCMD_DATA2 = 0x0382 # macro
mmSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA2_RLC6_MIDCMD_DATA3 = 0x0383 # macro
mmSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA2_RLC6_MIDCMD_DATA4 = 0x0384 # macro
mmSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA2_RLC6_MIDCMD_DATA5 = 0x0385 # macro
mmSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA2_RLC6_MIDCMD_DATA6 = 0x0386 # macro
mmSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA2_RLC6_MIDCMD_DATA7 = 0x0387 # macro
mmSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA2_RLC6_MIDCMD_DATA8 = 0x0388 # macro
mmSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA2_RLC6_MIDCMD_DATA9 = 0x0389 # macro
mmSDMA2_RLC6_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA2_RLC6_MIDCMD_DATA10 = 0x038a # macro
mmSDMA2_RLC6_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA2_RLC6_MIDCMD_CNTL = 0x038b # macro
mmSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC7_RB_CNTL = 0x0398 # macro
mmSDMA2_RLC7_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC7_RB_BASE = 0x0399 # macro
mmSDMA2_RLC7_RB_BASE_BASE_IDX = 2 # macro
mmSDMA2_RLC7_RB_BASE_HI = 0x039a # macro
mmSDMA2_RLC7_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC7_RB_RPTR = 0x039b # macro
mmSDMA2_RLC7_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC7_RB_RPTR_HI = 0x039c # macro
mmSDMA2_RLC7_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC7_RB_WPTR = 0x039d # macro
mmSDMA2_RLC7_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC7_RB_WPTR_HI = 0x039e # macro
mmSDMA2_RLC7_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC7_RB_WPTR_POLL_CNTL = 0x039f # macro
mmSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC7_RB_RPTR_ADDR_HI = 0x03a0 # macro
mmSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC7_RB_RPTR_ADDR_LO = 0x03a1 # macro
mmSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC7_IB_CNTL = 0x03a2 # macro
mmSDMA2_RLC7_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC7_IB_RPTR = 0x03a3 # macro
mmSDMA2_RLC7_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA2_RLC7_IB_OFFSET = 0x03a4 # macro
mmSDMA2_RLC7_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC7_IB_BASE_LO = 0x03a5 # macro
mmSDMA2_RLC7_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC7_IB_BASE_HI = 0x03a6 # macro
mmSDMA2_RLC7_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC7_IB_SIZE = 0x03a7 # macro
mmSDMA2_RLC7_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA2_RLC7_SKIP_CNTL = 0x03a8 # macro
mmSDMA2_RLC7_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC7_CONTEXT_STATUS = 0x03a9 # macro
mmSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC7_DOORBELL = 0x03aa # macro
mmSDMA2_RLC7_DOORBELL_BASE_IDX = 2 # macro
mmSDMA2_RLC7_STATUS = 0x03c0 # macro
mmSDMA2_RLC7_STATUS_BASE_IDX = 2 # macro
mmSDMA2_RLC7_DOORBELL_LOG = 0x03c1 # macro
mmSDMA2_RLC7_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA2_RLC7_WATERMARK = 0x03c2 # macro
mmSDMA2_RLC7_WATERMARK_BASE_IDX = 2 # macro
mmSDMA2_RLC7_DOORBELL_OFFSET = 0x03c3 # macro
mmSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA2_RLC7_CSA_ADDR_LO = 0x03c4 # macro
mmSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC7_CSA_ADDR_HI = 0x03c5 # macro
mmSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC7_IB_SUB_REMAIN = 0x03c7 # macro
mmSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA2_RLC7_PREEMPT = 0x03c8 # macro
mmSDMA2_RLC7_PREEMPT_BASE_IDX = 2 # macro
mmSDMA2_RLC7_DUMMY_REG = 0x03c9 # macro
mmSDMA2_RLC7_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI = 0x03ca # macro
mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO = 0x03cb # macro
mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA2_RLC7_RB_AQL_CNTL = 0x03cc # macro
mmSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA2_RLC7_MINOR_PTR_UPDATE = 0x03cd # macro
mmSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA2_RLC7_MIDCMD_DATA0 = 0x03d8 # macro
mmSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA2_RLC7_MIDCMD_DATA1 = 0x03d9 # macro
mmSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA2_RLC7_MIDCMD_DATA2 = 0x03da # macro
mmSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA2_RLC7_MIDCMD_DATA3 = 0x03db # macro
mmSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA2_RLC7_MIDCMD_DATA4 = 0x03dc # macro
mmSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA2_RLC7_MIDCMD_DATA5 = 0x03dd # macro
mmSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA2_RLC7_MIDCMD_DATA6 = 0x03de # macro
mmSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA2_RLC7_MIDCMD_DATA7 = 0x03df # macro
mmSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA2_RLC7_MIDCMD_DATA8 = 0x03e0 # macro
mmSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA2_RLC7_MIDCMD_DATA9 = 0x03e1 # macro
mmSDMA2_RLC7_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA2_RLC7_MIDCMD_DATA10 = 0x03e2 # macro
mmSDMA2_RLC7_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA2_RLC7_MIDCMD_CNTL = 0x03e3 # macro
mmSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA3_DEC_START = 0x0400 # macro
mmSDMA3_DEC_START_BASE_IDX = 2 # macro
mmSDMA3_GLOBAL_TIMESTAMP_LO = 0x040f # macro
mmSDMA3_GLOBAL_TIMESTAMP_LO_BASE_IDX = 2 # macro
mmSDMA3_GLOBAL_TIMESTAMP_HI = 0x0410 # macro
mmSDMA3_GLOBAL_TIMESTAMP_HI_BASE_IDX = 2 # macro
mmSDMA3_PG_CNTL = 0x0416 # macro
mmSDMA3_PG_CNTL_BASE_IDX = 2 # macro
mmSDMA3_PG_CTX_LO = 0x0417 # macro
mmSDMA3_PG_CTX_LO_BASE_IDX = 2 # macro
mmSDMA3_PG_CTX_HI = 0x0418 # macro
mmSDMA3_PG_CTX_HI_BASE_IDX = 2 # macro
mmSDMA3_PG_CTX_CNTL = 0x0419 # macro
mmSDMA3_PG_CTX_CNTL_BASE_IDX = 2 # macro
mmSDMA3_POWER_CNTL = 0x041a # macro
mmSDMA3_POWER_CNTL_BASE_IDX = 2 # macro
mmSDMA3_CLK_CTRL = 0x041b # macro
mmSDMA3_CLK_CTRL_BASE_IDX = 2 # macro
mmSDMA3_CNTL = 0x041c # macro
mmSDMA3_CNTL_BASE_IDX = 2 # macro
mmSDMA3_CHICKEN_BITS = 0x041d # macro
mmSDMA3_CHICKEN_BITS_BASE_IDX = 2 # macro
mmSDMA3_GB_ADDR_CONFIG = 0x041e # macro
mmSDMA3_GB_ADDR_CONFIG_BASE_IDX = 2 # macro
mmSDMA3_GB_ADDR_CONFIG_READ = 0x041f # macro
mmSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX = 2 # macro
mmSDMA3_RB_RPTR_FETCH_HI = 0x0420 # macro
mmSDMA3_RB_RPTR_FETCH_HI_BASE_IDX = 2 # macro
mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL = 0x0421 # macro
mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RB_RPTR_FETCH = 0x0422 # macro
mmSDMA3_RB_RPTR_FETCH_BASE_IDX = 2 # macro
mmSDMA3_IB_OFFSET_FETCH = 0x0423 # macro
mmSDMA3_IB_OFFSET_FETCH_BASE_IDX = 2 # macro
mmSDMA3_PROGRAM = 0x0424 # macro
mmSDMA3_PROGRAM_BASE_IDX = 2 # macro
mmSDMA3_STATUS_REG = 0x0425 # macro
mmSDMA3_STATUS_REG_BASE_IDX = 2 # macro
mmSDMA3_STATUS1_REG = 0x0426 # macro
mmSDMA3_STATUS1_REG_BASE_IDX = 2 # macro
mmSDMA3_RD_BURST_CNTL = 0x0427 # macro
mmSDMA3_RD_BURST_CNTL_BASE_IDX = 2 # macro
mmSDMA3_HBM_PAGE_CONFIG = 0x0428 # macro
mmSDMA3_HBM_PAGE_CONFIG_BASE_IDX = 2 # macro
mmSDMA3_UCODE_CHECKSUM = 0x0429 # macro
mmSDMA3_UCODE_CHECKSUM_BASE_IDX = 2 # macro
mmSDMA3_F32_CNTL = 0x042a # macro
mmSDMA3_F32_CNTL_BASE_IDX = 2 # macro
mmSDMA3_FREEZE = 0x042b # macro
mmSDMA3_FREEZE_BASE_IDX = 2 # macro
mmSDMA3_PHASE0_QUANTUM = 0x042c # macro
mmSDMA3_PHASE0_QUANTUM_BASE_IDX = 2 # macro
mmSDMA3_PHASE1_QUANTUM = 0x042d # macro
mmSDMA3_PHASE1_QUANTUM_BASE_IDX = 2 # macro
mmSDMA3_EDC_CONFIG = 0x0432 # macro
mmSDMA3_EDC_CONFIG_BASE_IDX = 2 # macro
mmSDMA3_BA_THRESHOLD = 0x0433 # macro
mmSDMA3_BA_THRESHOLD_BASE_IDX = 2 # macro
mmSDMA3_ID = 0x0434 # macro
mmSDMA3_ID_BASE_IDX = 2 # macro
mmSDMA3_VERSION = 0x0435 # macro
mmSDMA3_VERSION_BASE_IDX = 2 # macro
mmSDMA3_EDC_COUNTER = 0x0436 # macro
mmSDMA3_EDC_COUNTER_BASE_IDX = 2 # macro
mmSDMA3_EDC_COUNTER_CLEAR = 0x0437 # macro
mmSDMA3_EDC_COUNTER_CLEAR_BASE_IDX = 2 # macro
mmSDMA3_STATUS2_REG = 0x0438 # macro
mmSDMA3_STATUS2_REG_BASE_IDX = 2 # macro
mmSDMA3_ATOMIC_CNTL = 0x0439 # macro
mmSDMA3_ATOMIC_CNTL_BASE_IDX = 2 # macro
mmSDMA3_ATOMIC_PREOP_LO = 0x043a # macro
mmSDMA3_ATOMIC_PREOP_LO_BASE_IDX = 2 # macro
mmSDMA3_ATOMIC_PREOP_HI = 0x043b # macro
mmSDMA3_ATOMIC_PREOP_HI_BASE_IDX = 2 # macro
mmSDMA3_UTCL1_CNTL = 0x043c # macro
mmSDMA3_UTCL1_CNTL_BASE_IDX = 2 # macro
mmSDMA3_UTCL1_WATERMK = 0x043d # macro
mmSDMA3_UTCL1_WATERMK_BASE_IDX = 2 # macro
mmSDMA3_UTCL1_RD_STATUS = 0x043e # macro
mmSDMA3_UTCL1_RD_STATUS_BASE_IDX = 2 # macro
mmSDMA3_UTCL1_WR_STATUS = 0x043f # macro
mmSDMA3_UTCL1_WR_STATUS_BASE_IDX = 2 # macro
mmSDMA3_UTCL1_INV0 = 0x0440 # macro
mmSDMA3_UTCL1_INV0_BASE_IDX = 2 # macro
mmSDMA3_UTCL1_INV1 = 0x0441 # macro
mmSDMA3_UTCL1_INV1_BASE_IDX = 2 # macro
mmSDMA3_UTCL1_INV2 = 0x0442 # macro
mmSDMA3_UTCL1_INV2_BASE_IDX = 2 # macro
mmSDMA3_UTCL1_RD_XNACK0 = 0x0443 # macro
mmSDMA3_UTCL1_RD_XNACK0_BASE_IDX = 2 # macro
mmSDMA3_UTCL1_RD_XNACK1 = 0x0444 # macro
mmSDMA3_UTCL1_RD_XNACK1_BASE_IDX = 2 # macro
mmSDMA3_UTCL1_WR_XNACK0 = 0x0445 # macro
mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX = 2 # macro
mmSDMA3_UTCL1_WR_XNACK1 = 0x0446 # macro
mmSDMA3_UTCL1_WR_XNACK1_BASE_IDX = 2 # macro
mmSDMA3_UTCL1_TIMEOUT = 0x0447 # macro
mmSDMA3_UTCL1_TIMEOUT_BASE_IDX = 2 # macro
mmSDMA3_UTCL1_PAGE = 0x0448 # macro
mmSDMA3_UTCL1_PAGE_BASE_IDX = 2 # macro
mmSDMA3_RELAX_ORDERING_LUT = 0x044a # macro
mmSDMA3_RELAX_ORDERING_LUT_BASE_IDX = 2 # macro
mmSDMA3_CHICKEN_BITS_2 = 0x044b # macro
mmSDMA3_CHICKEN_BITS_2_BASE_IDX = 2 # macro
mmSDMA3_STATUS3_REG = 0x044c # macro
mmSDMA3_STATUS3_REG_BASE_IDX = 2 # macro
mmSDMA3_PHYSICAL_ADDR_LO = 0x044d # macro
mmSDMA3_PHYSICAL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_PHYSICAL_ADDR_HI = 0x044e # macro
mmSDMA3_PHYSICAL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_PHASE2_QUANTUM = 0x044f # macro
mmSDMA3_PHASE2_QUANTUM_BASE_IDX = 2 # macro
mmSDMA3_ERROR_LOG = 0x0450 # macro
mmSDMA3_ERROR_LOG_BASE_IDX = 2 # macro
mmSDMA3_PUB_DUMMY_REG0 = 0x0451 # macro
mmSDMA3_PUB_DUMMY_REG0_BASE_IDX = 2 # macro
mmSDMA3_PUB_DUMMY_REG1 = 0x0452 # macro
mmSDMA3_PUB_DUMMY_REG1_BASE_IDX = 2 # macro
mmSDMA3_PUB_DUMMY_REG2 = 0x0453 # macro
mmSDMA3_PUB_DUMMY_REG2_BASE_IDX = 2 # macro
mmSDMA3_PUB_DUMMY_REG3 = 0x0454 # macro
mmSDMA3_PUB_DUMMY_REG3_BASE_IDX = 2 # macro
mmSDMA3_F32_COUNTER = 0x0455 # macro
mmSDMA3_F32_COUNTER_BASE_IDX = 2 # macro
mmSDMA3_CRD_CNTL = 0x045b # macro
mmSDMA3_CRD_CNTL_BASE_IDX = 2 # macro
mmSDMA3_AQL_STATUS = 0x045f # macro
mmSDMA3_AQL_STATUS_BASE_IDX = 2 # macro
mmSDMA3_EA_DBIT_ADDR_DATA = 0x0460 # macro
mmSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX = 2 # macro
mmSDMA3_EA_DBIT_ADDR_INDEX = 0x0461 # macro
mmSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX = 2 # macro
mmSDMA3_TLBI_GCR_CNTL = 0x0462 # macro
mmSDMA3_TLBI_GCR_CNTL_BASE_IDX = 2 # macro
mmSDMA3_TILING_CONFIG = 0x0463 # macro
mmSDMA3_TILING_CONFIG_BASE_IDX = 2 # macro
mmSDMA3_INT_STATUS = 0x0470 # macro
mmSDMA3_INT_STATUS_BASE_IDX = 2 # macro
mmSDMA3_HOLE_ADDR_LO = 0x0472 # macro
mmSDMA3_HOLE_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_HOLE_ADDR_HI = 0x0473 # macro
mmSDMA3_HOLE_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_CLOCK_GATING_REG = 0x0475 # macro
mmSDMA3_CLOCK_GATING_REG_BASE_IDX = 2 # macro
mmSDMA3_STATUS4_REG = 0x0476 # macro
mmSDMA3_STATUS4_REG_BASE_IDX = 2 # macro
mmSDMA3_SCRATCH_RAM_DATA = 0x0477 # macro
mmSDMA3_SCRATCH_RAM_DATA_BASE_IDX = 2 # macro
mmSDMA3_SCRATCH_RAM_ADDR = 0x0478 # macro
mmSDMA3_SCRATCH_RAM_ADDR_BASE_IDX = 2 # macro
mmSDMA3_TIMESTAMP_CNTL = 0x0479 # macro
mmSDMA3_TIMESTAMP_CNTL_BASE_IDX = 2 # macro
mmSDMA3_STATUS5_REG = 0x047a # macro
mmSDMA3_STATUS5_REG_BASE_IDX = 2 # macro
mmSDMA3_QUEUE_RESET_REQ = 0x047b # macro
mmSDMA3_QUEUE_RESET_REQ_BASE_IDX = 2 # macro
mmSDMA3_GFX_RB_CNTL = 0x0480 # macro
mmSDMA3_GFX_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_GFX_RB_BASE = 0x0481 # macro
mmSDMA3_GFX_RB_BASE_BASE_IDX = 2 # macro
mmSDMA3_GFX_RB_BASE_HI = 0x0482 # macro
mmSDMA3_GFX_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_GFX_RB_RPTR = 0x0483 # macro
mmSDMA3_GFX_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_GFX_RB_RPTR_HI = 0x0484 # macro
mmSDMA3_GFX_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_GFX_RB_WPTR = 0x0485 # macro
mmSDMA3_GFX_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA3_GFX_RB_WPTR_HI = 0x0486 # macro
mmSDMA3_GFX_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_GFX_RB_WPTR_POLL_CNTL = 0x0487 # macro
mmSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_GFX_RB_RPTR_ADDR_HI = 0x0488 # macro
mmSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_GFX_RB_RPTR_ADDR_LO = 0x0489 # macro
mmSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_GFX_IB_CNTL = 0x048a # macro
mmSDMA3_GFX_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_GFX_IB_RPTR = 0x048b # macro
mmSDMA3_GFX_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_GFX_IB_OFFSET = 0x048c # macro
mmSDMA3_GFX_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_GFX_IB_BASE_LO = 0x048d # macro
mmSDMA3_GFX_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA3_GFX_IB_BASE_HI = 0x048e # macro
mmSDMA3_GFX_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_GFX_IB_SIZE = 0x048f # macro
mmSDMA3_GFX_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA3_GFX_SKIP_CNTL = 0x0490 # macro
mmSDMA3_GFX_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA3_GFX_CONTEXT_STATUS = 0x0491 # macro
mmSDMA3_GFX_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA3_GFX_DOORBELL = 0x0492 # macro
mmSDMA3_GFX_DOORBELL_BASE_IDX = 2 # macro
mmSDMA3_GFX_CONTEXT_CNTL = 0x0493 # macro
mmSDMA3_GFX_CONTEXT_CNTL_BASE_IDX = 2 # macro
mmSDMA3_GFX_STATUS = 0x04a8 # macro
mmSDMA3_GFX_STATUS_BASE_IDX = 2 # macro
mmSDMA3_GFX_DOORBELL_LOG = 0x04a9 # macro
mmSDMA3_GFX_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA3_GFX_WATERMARK = 0x04aa # macro
mmSDMA3_GFX_WATERMARK_BASE_IDX = 2 # macro
mmSDMA3_GFX_DOORBELL_OFFSET = 0x04ab # macro
mmSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_GFX_CSA_ADDR_LO = 0x04ac # macro
mmSDMA3_GFX_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_GFX_CSA_ADDR_HI = 0x04ad # macro
mmSDMA3_GFX_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_GFX_IB_SUB_REMAIN = 0x04af # macro
mmSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA3_GFX_PREEMPT = 0x04b0 # macro
mmSDMA3_GFX_PREEMPT_BASE_IDX = 2 # macro
mmSDMA3_GFX_DUMMY_REG = 0x04b1 # macro
mmSDMA3_GFX_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI = 0x04b2 # macro
mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO = 0x04b3 # macro
mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_GFX_RB_AQL_CNTL = 0x04b4 # macro
mmSDMA3_GFX_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_GFX_MINOR_PTR_UPDATE = 0x04b5 # macro
mmSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA3_GFX_MIDCMD_DATA0 = 0x04c0 # macro
mmSDMA3_GFX_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA3_GFX_MIDCMD_DATA1 = 0x04c1 # macro
mmSDMA3_GFX_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA3_GFX_MIDCMD_DATA2 = 0x04c2 # macro
mmSDMA3_GFX_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA3_GFX_MIDCMD_DATA3 = 0x04c3 # macro
mmSDMA3_GFX_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA3_GFX_MIDCMD_DATA4 = 0x04c4 # macro
mmSDMA3_GFX_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA3_GFX_MIDCMD_DATA5 = 0x04c5 # macro
mmSDMA3_GFX_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA3_GFX_MIDCMD_DATA6 = 0x04c6 # macro
mmSDMA3_GFX_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA3_GFX_MIDCMD_DATA7 = 0x04c7 # macro
mmSDMA3_GFX_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA3_GFX_MIDCMD_DATA8 = 0x04c8 # macro
mmSDMA3_GFX_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA3_GFX_MIDCMD_DATA9 = 0x04c9 # macro
mmSDMA3_GFX_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA3_GFX_MIDCMD_DATA10 = 0x04ca # macro
mmSDMA3_GFX_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA3_GFX_MIDCMD_CNTL = 0x04cb # macro
mmSDMA3_GFX_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA3_PAGE_RB_CNTL = 0x04d8 # macro
mmSDMA3_PAGE_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_PAGE_RB_BASE = 0x04d9 # macro
mmSDMA3_PAGE_RB_BASE_BASE_IDX = 2 # macro
mmSDMA3_PAGE_RB_BASE_HI = 0x04da # macro
mmSDMA3_PAGE_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_PAGE_RB_RPTR = 0x04db # macro
mmSDMA3_PAGE_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_PAGE_RB_RPTR_HI = 0x04dc # macro
mmSDMA3_PAGE_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_PAGE_RB_WPTR = 0x04dd # macro
mmSDMA3_PAGE_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA3_PAGE_RB_WPTR_HI = 0x04de # macro
mmSDMA3_PAGE_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_PAGE_RB_WPTR_POLL_CNTL = 0x04df # macro
mmSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_PAGE_RB_RPTR_ADDR_HI = 0x04e0 # macro
mmSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_PAGE_RB_RPTR_ADDR_LO = 0x04e1 # macro
mmSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_PAGE_IB_CNTL = 0x04e2 # macro
mmSDMA3_PAGE_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_PAGE_IB_RPTR = 0x04e3 # macro
mmSDMA3_PAGE_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_PAGE_IB_OFFSET = 0x04e4 # macro
mmSDMA3_PAGE_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_PAGE_IB_BASE_LO = 0x04e5 # macro
mmSDMA3_PAGE_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA3_PAGE_IB_BASE_HI = 0x04e6 # macro
mmSDMA3_PAGE_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_PAGE_IB_SIZE = 0x04e7 # macro
mmSDMA3_PAGE_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA3_PAGE_SKIP_CNTL = 0x04e8 # macro
mmSDMA3_PAGE_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA3_PAGE_CONTEXT_STATUS = 0x04e9 # macro
mmSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA3_PAGE_DOORBELL = 0x04ea # macro
mmSDMA3_PAGE_DOORBELL_BASE_IDX = 2 # macro
mmSDMA3_PAGE_STATUS = 0x0500 # macro
mmSDMA3_PAGE_STATUS_BASE_IDX = 2 # macro
mmSDMA3_PAGE_DOORBELL_LOG = 0x0501 # macro
mmSDMA3_PAGE_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA3_PAGE_WATERMARK = 0x0502 # macro
mmSDMA3_PAGE_WATERMARK_BASE_IDX = 2 # macro
mmSDMA3_PAGE_DOORBELL_OFFSET = 0x0503 # macro
mmSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_PAGE_CSA_ADDR_LO = 0x0504 # macro
mmSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_PAGE_CSA_ADDR_HI = 0x0505 # macro
mmSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_PAGE_IB_SUB_REMAIN = 0x0507 # macro
mmSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA3_PAGE_PREEMPT = 0x0508 # macro
mmSDMA3_PAGE_PREEMPT_BASE_IDX = 2 # macro
mmSDMA3_PAGE_DUMMY_REG = 0x0509 # macro
mmSDMA3_PAGE_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI = 0x050a # macro
mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO = 0x050b # macro
mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_PAGE_RB_AQL_CNTL = 0x050c # macro
mmSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_PAGE_MINOR_PTR_UPDATE = 0x050d # macro
mmSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA3_PAGE_MIDCMD_DATA0 = 0x0518 # macro
mmSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA3_PAGE_MIDCMD_DATA1 = 0x0519 # macro
mmSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA3_PAGE_MIDCMD_DATA2 = 0x051a # macro
mmSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA3_PAGE_MIDCMD_DATA3 = 0x051b # macro
mmSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA3_PAGE_MIDCMD_DATA4 = 0x051c # macro
mmSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA3_PAGE_MIDCMD_DATA5 = 0x051d # macro
mmSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA3_PAGE_MIDCMD_DATA6 = 0x051e # macro
mmSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA3_PAGE_MIDCMD_DATA7 = 0x051f # macro
mmSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA3_PAGE_MIDCMD_DATA8 = 0x0520 # macro
mmSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA3_PAGE_MIDCMD_DATA9 = 0x0521 # macro
mmSDMA3_PAGE_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA3_PAGE_MIDCMD_DATA10 = 0x0522 # macro
mmSDMA3_PAGE_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA3_PAGE_MIDCMD_CNTL = 0x0523 # macro
mmSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC0_RB_CNTL = 0x0530 # macro
mmSDMA3_RLC0_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC0_RB_BASE = 0x0531 # macro
mmSDMA3_RLC0_RB_BASE_BASE_IDX = 2 # macro
mmSDMA3_RLC0_RB_BASE_HI = 0x0532 # macro
mmSDMA3_RLC0_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC0_RB_RPTR = 0x0533 # macro
mmSDMA3_RLC0_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC0_RB_RPTR_HI = 0x0534 # macro
mmSDMA3_RLC0_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC0_RB_WPTR = 0x0535 # macro
mmSDMA3_RLC0_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC0_RB_WPTR_HI = 0x0536 # macro
mmSDMA3_RLC0_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC0_RB_WPTR_POLL_CNTL = 0x0537 # macro
mmSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC0_RB_RPTR_ADDR_HI = 0x0538 # macro
mmSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC0_RB_RPTR_ADDR_LO = 0x0539 # macro
mmSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC0_IB_CNTL = 0x053a # macro
mmSDMA3_RLC0_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC0_IB_RPTR = 0x053b # macro
mmSDMA3_RLC0_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC0_IB_OFFSET = 0x053c # macro
mmSDMA3_RLC0_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC0_IB_BASE_LO = 0x053d # macro
mmSDMA3_RLC0_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC0_IB_BASE_HI = 0x053e # macro
mmSDMA3_RLC0_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC0_IB_SIZE = 0x053f # macro
mmSDMA3_RLC0_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA3_RLC0_SKIP_CNTL = 0x0540 # macro
mmSDMA3_RLC0_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC0_CONTEXT_STATUS = 0x0541 # macro
mmSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC0_DOORBELL = 0x0542 # macro
mmSDMA3_RLC0_DOORBELL_BASE_IDX = 2 # macro
mmSDMA3_RLC0_STATUS = 0x0558 # macro
mmSDMA3_RLC0_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC0_DOORBELL_LOG = 0x0559 # macro
mmSDMA3_RLC0_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA3_RLC0_WATERMARK = 0x055a # macro
mmSDMA3_RLC0_WATERMARK_BASE_IDX = 2 # macro
mmSDMA3_RLC0_DOORBELL_OFFSET = 0x055b # macro
mmSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC0_CSA_ADDR_LO = 0x055c # macro
mmSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC0_CSA_ADDR_HI = 0x055d # macro
mmSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC0_IB_SUB_REMAIN = 0x055f # macro
mmSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA3_RLC0_PREEMPT = 0x0560 # macro
mmSDMA3_RLC0_PREEMPT_BASE_IDX = 2 # macro
mmSDMA3_RLC0_DUMMY_REG = 0x0561 # macro
mmSDMA3_RLC0_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI = 0x0562 # macro
mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO = 0x0563 # macro
mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC0_RB_AQL_CNTL = 0x0564 # macro
mmSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC0_MINOR_PTR_UPDATE = 0x0565 # macro
mmSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA3_RLC0_MIDCMD_DATA0 = 0x0570 # macro
mmSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA3_RLC0_MIDCMD_DATA1 = 0x0571 # macro
mmSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA3_RLC0_MIDCMD_DATA2 = 0x0572 # macro
mmSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA3_RLC0_MIDCMD_DATA3 = 0x0573 # macro
mmSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA3_RLC0_MIDCMD_DATA4 = 0x0574 # macro
mmSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA3_RLC0_MIDCMD_DATA5 = 0x0575 # macro
mmSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA3_RLC0_MIDCMD_DATA6 = 0x0576 # macro
mmSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA3_RLC0_MIDCMD_DATA7 = 0x0577 # macro
mmSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA3_RLC0_MIDCMD_DATA8 = 0x0578 # macro
mmSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA3_RLC0_MIDCMD_DATA9 = 0x0579 # macro
mmSDMA3_RLC0_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA3_RLC0_MIDCMD_DATA10 = 0x057a # macro
mmSDMA3_RLC0_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA3_RLC0_MIDCMD_CNTL = 0x057b # macro
mmSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC1_RB_CNTL = 0x0588 # macro
mmSDMA3_RLC1_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC1_RB_BASE = 0x0589 # macro
mmSDMA3_RLC1_RB_BASE_BASE_IDX = 2 # macro
mmSDMA3_RLC1_RB_BASE_HI = 0x058a # macro
mmSDMA3_RLC1_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC1_RB_RPTR = 0x058b # macro
mmSDMA3_RLC1_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC1_RB_RPTR_HI = 0x058c # macro
mmSDMA3_RLC1_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC1_RB_WPTR = 0x058d # macro
mmSDMA3_RLC1_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC1_RB_WPTR_HI = 0x058e # macro
mmSDMA3_RLC1_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC1_RB_WPTR_POLL_CNTL = 0x058f # macro
mmSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC1_RB_RPTR_ADDR_HI = 0x0590 # macro
mmSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC1_RB_RPTR_ADDR_LO = 0x0591 # macro
mmSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC1_IB_CNTL = 0x0592 # macro
mmSDMA3_RLC1_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC1_IB_RPTR = 0x0593 # macro
mmSDMA3_RLC1_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC1_IB_OFFSET = 0x0594 # macro
mmSDMA3_RLC1_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC1_IB_BASE_LO = 0x0595 # macro
mmSDMA3_RLC1_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC1_IB_BASE_HI = 0x0596 # macro
mmSDMA3_RLC1_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC1_IB_SIZE = 0x0597 # macro
mmSDMA3_RLC1_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA3_RLC1_SKIP_CNTL = 0x0598 # macro
mmSDMA3_RLC1_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC1_CONTEXT_STATUS = 0x0599 # macro
mmSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC1_DOORBELL = 0x059a # macro
mmSDMA3_RLC1_DOORBELL_BASE_IDX = 2 # macro
mmSDMA3_RLC1_STATUS = 0x05b0 # macro
mmSDMA3_RLC1_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC1_DOORBELL_LOG = 0x05b1 # macro
mmSDMA3_RLC1_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA3_RLC1_WATERMARK = 0x05b2 # macro
mmSDMA3_RLC1_WATERMARK_BASE_IDX = 2 # macro
mmSDMA3_RLC1_DOORBELL_OFFSET = 0x05b3 # macro
mmSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC1_CSA_ADDR_LO = 0x05b4 # macro
mmSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC1_CSA_ADDR_HI = 0x05b5 # macro
mmSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC1_IB_SUB_REMAIN = 0x05b7 # macro
mmSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA3_RLC1_PREEMPT = 0x05b8 # macro
mmSDMA3_RLC1_PREEMPT_BASE_IDX = 2 # macro
mmSDMA3_RLC1_DUMMY_REG = 0x05b9 # macro
mmSDMA3_RLC1_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI = 0x05ba # macro
mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO = 0x05bb # macro
mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC1_RB_AQL_CNTL = 0x05bc # macro
mmSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC1_MINOR_PTR_UPDATE = 0x05bd # macro
mmSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA3_RLC1_MIDCMD_DATA0 = 0x05c8 # macro
mmSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA3_RLC1_MIDCMD_DATA1 = 0x05c9 # macro
mmSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA3_RLC1_MIDCMD_DATA2 = 0x05ca # macro
mmSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA3_RLC1_MIDCMD_DATA3 = 0x05cb # macro
mmSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA3_RLC1_MIDCMD_DATA4 = 0x05cc # macro
mmSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA3_RLC1_MIDCMD_DATA5 = 0x05cd # macro
mmSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA3_RLC1_MIDCMD_DATA6 = 0x05ce # macro
mmSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA3_RLC1_MIDCMD_DATA7 = 0x05cf # macro
mmSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA3_RLC1_MIDCMD_DATA8 = 0x05d0 # macro
mmSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA3_RLC1_MIDCMD_DATA9 = 0x05d1 # macro
mmSDMA3_RLC1_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA3_RLC1_MIDCMD_DATA10 = 0x05d2 # macro
mmSDMA3_RLC1_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA3_RLC1_MIDCMD_CNTL = 0x05d3 # macro
mmSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC2_RB_CNTL = 0x05e0 # macro
mmSDMA3_RLC2_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC2_RB_BASE = 0x05e1 # macro
mmSDMA3_RLC2_RB_BASE_BASE_IDX = 2 # macro
mmSDMA3_RLC2_RB_BASE_HI = 0x05e2 # macro
mmSDMA3_RLC2_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC2_RB_RPTR = 0x05e3 # macro
mmSDMA3_RLC2_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC2_RB_RPTR_HI = 0x05e4 # macro
mmSDMA3_RLC2_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC2_RB_WPTR = 0x05e5 # macro
mmSDMA3_RLC2_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC2_RB_WPTR_HI = 0x05e6 # macro
mmSDMA3_RLC2_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC2_RB_WPTR_POLL_CNTL = 0x05e7 # macro
mmSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC2_RB_RPTR_ADDR_HI = 0x05e8 # macro
mmSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC2_RB_RPTR_ADDR_LO = 0x05e9 # macro
mmSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC2_IB_CNTL = 0x05ea # macro
mmSDMA3_RLC2_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC2_IB_RPTR = 0x05eb # macro
mmSDMA3_RLC2_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC2_IB_OFFSET = 0x05ec # macro
mmSDMA3_RLC2_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC2_IB_BASE_LO = 0x05ed # macro
mmSDMA3_RLC2_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC2_IB_BASE_HI = 0x05ee # macro
mmSDMA3_RLC2_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC2_IB_SIZE = 0x05ef # macro
mmSDMA3_RLC2_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA3_RLC2_SKIP_CNTL = 0x05f0 # macro
mmSDMA3_RLC2_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC2_CONTEXT_STATUS = 0x05f1 # macro
mmSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC2_DOORBELL = 0x05f2 # macro
mmSDMA3_RLC2_DOORBELL_BASE_IDX = 2 # macro
mmSDMA3_RLC2_STATUS = 0x0608 # macro
mmSDMA3_RLC2_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC2_DOORBELL_LOG = 0x0609 # macro
mmSDMA3_RLC2_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA3_RLC2_WATERMARK = 0x060a # macro
mmSDMA3_RLC2_WATERMARK_BASE_IDX = 2 # macro
mmSDMA3_RLC2_DOORBELL_OFFSET = 0x060b # macro
mmSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC2_CSA_ADDR_LO = 0x060c # macro
mmSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC2_CSA_ADDR_HI = 0x060d # macro
mmSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC2_IB_SUB_REMAIN = 0x060f # macro
mmSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA3_RLC2_PREEMPT = 0x0610 # macro
mmSDMA3_RLC2_PREEMPT_BASE_IDX = 2 # macro
mmSDMA3_RLC2_DUMMY_REG = 0x0611 # macro
mmSDMA3_RLC2_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI = 0x0612 # macro
mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO = 0x0613 # macro
mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC2_RB_AQL_CNTL = 0x0614 # macro
mmSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC2_MINOR_PTR_UPDATE = 0x0615 # macro
mmSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA3_RLC2_MIDCMD_DATA0 = 0x0620 # macro
mmSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA3_RLC2_MIDCMD_DATA1 = 0x0621 # macro
mmSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA3_RLC2_MIDCMD_DATA2 = 0x0622 # macro
mmSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA3_RLC2_MIDCMD_DATA3 = 0x0623 # macro
mmSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA3_RLC2_MIDCMD_DATA4 = 0x0624 # macro
mmSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA3_RLC2_MIDCMD_DATA5 = 0x0625 # macro
mmSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA3_RLC2_MIDCMD_DATA6 = 0x0626 # macro
mmSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA3_RLC2_MIDCMD_DATA7 = 0x0627 # macro
mmSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA3_RLC2_MIDCMD_DATA8 = 0x0628 # macro
mmSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA3_RLC2_MIDCMD_DATA9 = 0x0629 # macro
mmSDMA3_RLC2_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA3_RLC2_MIDCMD_DATA10 = 0x062a # macro
mmSDMA3_RLC2_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA3_RLC2_MIDCMD_CNTL = 0x062b # macro
mmSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC3_RB_CNTL = 0x0638 # macro
mmSDMA3_RLC3_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC3_RB_BASE = 0x0639 # macro
mmSDMA3_RLC3_RB_BASE_BASE_IDX = 2 # macro
mmSDMA3_RLC3_RB_BASE_HI = 0x063a # macro
mmSDMA3_RLC3_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC3_RB_RPTR = 0x063b # macro
mmSDMA3_RLC3_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC3_RB_RPTR_HI = 0x063c # macro
mmSDMA3_RLC3_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC3_RB_WPTR = 0x063d # macro
mmSDMA3_RLC3_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC3_RB_WPTR_HI = 0x063e # macro
mmSDMA3_RLC3_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC3_RB_WPTR_POLL_CNTL = 0x063f # macro
mmSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC3_RB_RPTR_ADDR_HI = 0x0640 # macro
mmSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC3_RB_RPTR_ADDR_LO = 0x0641 # macro
mmSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC3_IB_CNTL = 0x0642 # macro
mmSDMA3_RLC3_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC3_IB_RPTR = 0x0643 # macro
mmSDMA3_RLC3_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC3_IB_OFFSET = 0x0644 # macro
mmSDMA3_RLC3_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC3_IB_BASE_LO = 0x0645 # macro
mmSDMA3_RLC3_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC3_IB_BASE_HI = 0x0646 # macro
mmSDMA3_RLC3_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC3_IB_SIZE = 0x0647 # macro
mmSDMA3_RLC3_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA3_RLC3_SKIP_CNTL = 0x0648 # macro
mmSDMA3_RLC3_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC3_CONTEXT_STATUS = 0x0649 # macro
mmSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC3_DOORBELL = 0x064a # macro
mmSDMA3_RLC3_DOORBELL_BASE_IDX = 2 # macro
mmSDMA3_RLC3_STATUS = 0x0660 # macro
mmSDMA3_RLC3_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC3_DOORBELL_LOG = 0x0661 # macro
mmSDMA3_RLC3_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA3_RLC3_WATERMARK = 0x0662 # macro
mmSDMA3_RLC3_WATERMARK_BASE_IDX = 2 # macro
mmSDMA3_RLC3_DOORBELL_OFFSET = 0x0663 # macro
mmSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC3_CSA_ADDR_LO = 0x0664 # macro
mmSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC3_CSA_ADDR_HI = 0x0665 # macro
mmSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC3_IB_SUB_REMAIN = 0x0667 # macro
mmSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA3_RLC3_PREEMPT = 0x0668 # macro
mmSDMA3_RLC3_PREEMPT_BASE_IDX = 2 # macro
mmSDMA3_RLC3_DUMMY_REG = 0x0669 # macro
mmSDMA3_RLC3_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI = 0x066a # macro
mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO = 0x066b # macro
mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC3_RB_AQL_CNTL = 0x066c # macro
mmSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC3_MINOR_PTR_UPDATE = 0x066d # macro
mmSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA3_RLC3_MIDCMD_DATA0 = 0x0678 # macro
mmSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA3_RLC3_MIDCMD_DATA1 = 0x0679 # macro
mmSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA3_RLC3_MIDCMD_DATA2 = 0x067a # macro
mmSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA3_RLC3_MIDCMD_DATA3 = 0x067b # macro
mmSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA3_RLC3_MIDCMD_DATA4 = 0x067c # macro
mmSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA3_RLC3_MIDCMD_DATA5 = 0x067d # macro
mmSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA3_RLC3_MIDCMD_DATA6 = 0x067e # macro
mmSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA3_RLC3_MIDCMD_DATA7 = 0x067f # macro
mmSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA3_RLC3_MIDCMD_DATA8 = 0x0680 # macro
mmSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA3_RLC3_MIDCMD_DATA9 = 0x0681 # macro
mmSDMA3_RLC3_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA3_RLC3_MIDCMD_DATA10 = 0x0682 # macro
mmSDMA3_RLC3_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA3_RLC3_MIDCMD_CNTL = 0x0683 # macro
mmSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC4_RB_CNTL = 0x0690 # macro
mmSDMA3_RLC4_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC4_RB_BASE = 0x0691 # macro
mmSDMA3_RLC4_RB_BASE_BASE_IDX = 2 # macro
mmSDMA3_RLC4_RB_BASE_HI = 0x0692 # macro
mmSDMA3_RLC4_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC4_RB_RPTR = 0x0693 # macro
mmSDMA3_RLC4_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC4_RB_RPTR_HI = 0x0694 # macro
mmSDMA3_RLC4_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC4_RB_WPTR = 0x0695 # macro
mmSDMA3_RLC4_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC4_RB_WPTR_HI = 0x0696 # macro
mmSDMA3_RLC4_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC4_RB_WPTR_POLL_CNTL = 0x0697 # macro
mmSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC4_RB_RPTR_ADDR_HI = 0x0698 # macro
mmSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC4_RB_RPTR_ADDR_LO = 0x0699 # macro
mmSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC4_IB_CNTL = 0x069a # macro
mmSDMA3_RLC4_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC4_IB_RPTR = 0x069b # macro
mmSDMA3_RLC4_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC4_IB_OFFSET = 0x069c # macro
mmSDMA3_RLC4_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC4_IB_BASE_LO = 0x069d # macro
mmSDMA3_RLC4_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC4_IB_BASE_HI = 0x069e # macro
mmSDMA3_RLC4_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC4_IB_SIZE = 0x069f # macro
mmSDMA3_RLC4_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA3_RLC4_SKIP_CNTL = 0x06a0 # macro
mmSDMA3_RLC4_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC4_CONTEXT_STATUS = 0x06a1 # macro
mmSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC4_DOORBELL = 0x06a2 # macro
mmSDMA3_RLC4_DOORBELL_BASE_IDX = 2 # macro
mmSDMA3_RLC4_STATUS = 0x06b8 # macro
mmSDMA3_RLC4_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC4_DOORBELL_LOG = 0x06b9 # macro
mmSDMA3_RLC4_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA3_RLC4_WATERMARK = 0x06ba # macro
mmSDMA3_RLC4_WATERMARK_BASE_IDX = 2 # macro
mmSDMA3_RLC4_DOORBELL_OFFSET = 0x06bb # macro
mmSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC4_CSA_ADDR_LO = 0x06bc # macro
mmSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC4_CSA_ADDR_HI = 0x06bd # macro
mmSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC4_IB_SUB_REMAIN = 0x06bf # macro
mmSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA3_RLC4_PREEMPT = 0x06c0 # macro
mmSDMA3_RLC4_PREEMPT_BASE_IDX = 2 # macro
mmSDMA3_RLC4_DUMMY_REG = 0x06c1 # macro
mmSDMA3_RLC4_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI = 0x06c2 # macro
mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO = 0x06c3 # macro
mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC4_RB_AQL_CNTL = 0x06c4 # macro
mmSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC4_MINOR_PTR_UPDATE = 0x06c5 # macro
mmSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA3_RLC4_MIDCMD_DATA0 = 0x06d0 # macro
mmSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA3_RLC4_MIDCMD_DATA1 = 0x06d1 # macro
mmSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA3_RLC4_MIDCMD_DATA2 = 0x06d2 # macro
mmSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA3_RLC4_MIDCMD_DATA3 = 0x06d3 # macro
mmSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA3_RLC4_MIDCMD_DATA4 = 0x06d4 # macro
mmSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA3_RLC4_MIDCMD_DATA5 = 0x06d5 # macro
mmSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA3_RLC4_MIDCMD_DATA6 = 0x06d6 # macro
mmSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA3_RLC4_MIDCMD_DATA7 = 0x06d7 # macro
mmSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA3_RLC4_MIDCMD_DATA8 = 0x06d8 # macro
mmSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA3_RLC4_MIDCMD_DATA9 = 0x06d9 # macro
mmSDMA3_RLC4_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA3_RLC4_MIDCMD_DATA10 = 0x06da # macro
mmSDMA3_RLC4_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA3_RLC4_MIDCMD_CNTL = 0x06db # macro
mmSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC5_RB_CNTL = 0x06e8 # macro
mmSDMA3_RLC5_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC5_RB_BASE = 0x06e9 # macro
mmSDMA3_RLC5_RB_BASE_BASE_IDX = 2 # macro
mmSDMA3_RLC5_RB_BASE_HI = 0x06ea # macro
mmSDMA3_RLC5_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC5_RB_RPTR = 0x06eb # macro
mmSDMA3_RLC5_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC5_RB_RPTR_HI = 0x06ec # macro
mmSDMA3_RLC5_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC5_RB_WPTR = 0x06ed # macro
mmSDMA3_RLC5_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC5_RB_WPTR_HI = 0x06ee # macro
mmSDMA3_RLC5_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC5_RB_WPTR_POLL_CNTL = 0x06ef # macro
mmSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC5_RB_RPTR_ADDR_HI = 0x06f0 # macro
mmSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC5_RB_RPTR_ADDR_LO = 0x06f1 # macro
mmSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC5_IB_CNTL = 0x06f2 # macro
mmSDMA3_RLC5_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC5_IB_RPTR = 0x06f3 # macro
mmSDMA3_RLC5_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC5_IB_OFFSET = 0x06f4 # macro
mmSDMA3_RLC5_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC5_IB_BASE_LO = 0x06f5 # macro
mmSDMA3_RLC5_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC5_IB_BASE_HI = 0x06f6 # macro
mmSDMA3_RLC5_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC5_IB_SIZE = 0x06f7 # macro
mmSDMA3_RLC5_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA3_RLC5_SKIP_CNTL = 0x06f8 # macro
mmSDMA3_RLC5_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC5_CONTEXT_STATUS = 0x06f9 # macro
mmSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC5_DOORBELL = 0x06fa # macro
mmSDMA3_RLC5_DOORBELL_BASE_IDX = 2 # macro
mmSDMA3_RLC5_STATUS = 0x0710 # macro
mmSDMA3_RLC5_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC5_DOORBELL_LOG = 0x0711 # macro
mmSDMA3_RLC5_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA3_RLC5_WATERMARK = 0x0712 # macro
mmSDMA3_RLC5_WATERMARK_BASE_IDX = 2 # macro
mmSDMA3_RLC5_DOORBELL_OFFSET = 0x0713 # macro
mmSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC5_CSA_ADDR_LO = 0x0714 # macro
mmSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC5_CSA_ADDR_HI = 0x0715 # macro
mmSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC5_IB_SUB_REMAIN = 0x0717 # macro
mmSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA3_RLC5_PREEMPT = 0x0718 # macro
mmSDMA3_RLC5_PREEMPT_BASE_IDX = 2 # macro
mmSDMA3_RLC5_DUMMY_REG = 0x0719 # macro
mmSDMA3_RLC5_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI = 0x071a # macro
mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO = 0x071b # macro
mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC5_RB_AQL_CNTL = 0x071c # macro
mmSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC5_MINOR_PTR_UPDATE = 0x071d # macro
mmSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA3_RLC5_MIDCMD_DATA0 = 0x0728 # macro
mmSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA3_RLC5_MIDCMD_DATA1 = 0x0729 # macro
mmSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA3_RLC5_MIDCMD_DATA2 = 0x072a # macro
mmSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA3_RLC5_MIDCMD_DATA3 = 0x072b # macro
mmSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA3_RLC5_MIDCMD_DATA4 = 0x072c # macro
mmSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA3_RLC5_MIDCMD_DATA5 = 0x072d # macro
mmSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA3_RLC5_MIDCMD_DATA6 = 0x072e # macro
mmSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA3_RLC5_MIDCMD_DATA7 = 0x072f # macro
mmSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA3_RLC5_MIDCMD_DATA8 = 0x0730 # macro
mmSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA3_RLC5_MIDCMD_DATA9 = 0x0731 # macro
mmSDMA3_RLC5_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA3_RLC5_MIDCMD_DATA10 = 0x0732 # macro
mmSDMA3_RLC5_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA3_RLC5_MIDCMD_CNTL = 0x0733 # macro
mmSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC6_RB_CNTL = 0x0740 # macro
mmSDMA3_RLC6_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC6_RB_BASE = 0x0741 # macro
mmSDMA3_RLC6_RB_BASE_BASE_IDX = 2 # macro
mmSDMA3_RLC6_RB_BASE_HI = 0x0742 # macro
mmSDMA3_RLC6_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC6_RB_RPTR = 0x0743 # macro
mmSDMA3_RLC6_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC6_RB_RPTR_HI = 0x0744 # macro
mmSDMA3_RLC6_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC6_RB_WPTR = 0x0745 # macro
mmSDMA3_RLC6_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC6_RB_WPTR_HI = 0x0746 # macro
mmSDMA3_RLC6_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC6_RB_WPTR_POLL_CNTL = 0x0747 # macro
mmSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC6_RB_RPTR_ADDR_HI = 0x0748 # macro
mmSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC6_RB_RPTR_ADDR_LO = 0x0749 # macro
mmSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC6_IB_CNTL = 0x074a # macro
mmSDMA3_RLC6_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC6_IB_RPTR = 0x074b # macro
mmSDMA3_RLC6_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC6_IB_OFFSET = 0x074c # macro
mmSDMA3_RLC6_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC6_IB_BASE_LO = 0x074d # macro
mmSDMA3_RLC6_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC6_IB_BASE_HI = 0x074e # macro
mmSDMA3_RLC6_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC6_IB_SIZE = 0x074f # macro
mmSDMA3_RLC6_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA3_RLC6_SKIP_CNTL = 0x0750 # macro
mmSDMA3_RLC6_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC6_CONTEXT_STATUS = 0x0751 # macro
mmSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC6_DOORBELL = 0x0752 # macro
mmSDMA3_RLC6_DOORBELL_BASE_IDX = 2 # macro
mmSDMA3_RLC6_STATUS = 0x0768 # macro
mmSDMA3_RLC6_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC6_DOORBELL_LOG = 0x0769 # macro
mmSDMA3_RLC6_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA3_RLC6_WATERMARK = 0x076a # macro
mmSDMA3_RLC6_WATERMARK_BASE_IDX = 2 # macro
mmSDMA3_RLC6_DOORBELL_OFFSET = 0x076b # macro
mmSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC6_CSA_ADDR_LO = 0x076c # macro
mmSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC6_CSA_ADDR_HI = 0x076d # macro
mmSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC6_IB_SUB_REMAIN = 0x076f # macro
mmSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA3_RLC6_PREEMPT = 0x0770 # macro
mmSDMA3_RLC6_PREEMPT_BASE_IDX = 2 # macro
mmSDMA3_RLC6_DUMMY_REG = 0x0771 # macro
mmSDMA3_RLC6_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI = 0x0772 # macro
mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO = 0x0773 # macro
mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC6_RB_AQL_CNTL = 0x0774 # macro
mmSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC6_MINOR_PTR_UPDATE = 0x0775 # macro
mmSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA3_RLC6_MIDCMD_DATA0 = 0x0780 # macro
mmSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA3_RLC6_MIDCMD_DATA1 = 0x0781 # macro
mmSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA3_RLC6_MIDCMD_DATA2 = 0x0782 # macro
mmSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA3_RLC6_MIDCMD_DATA3 = 0x0783 # macro
mmSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA3_RLC6_MIDCMD_DATA4 = 0x0784 # macro
mmSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA3_RLC6_MIDCMD_DATA5 = 0x0785 # macro
mmSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA3_RLC6_MIDCMD_DATA6 = 0x0786 # macro
mmSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA3_RLC6_MIDCMD_DATA7 = 0x0787 # macro
mmSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA3_RLC6_MIDCMD_DATA8 = 0x0788 # macro
mmSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA3_RLC6_MIDCMD_DATA9 = 0x0789 # macro
mmSDMA3_RLC6_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA3_RLC6_MIDCMD_DATA10 = 0x078a # macro
mmSDMA3_RLC6_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA3_RLC6_MIDCMD_CNTL = 0x078b # macro
mmSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC7_RB_CNTL = 0x0798 # macro
mmSDMA3_RLC7_RB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC7_RB_BASE = 0x0799 # macro
mmSDMA3_RLC7_RB_BASE_BASE_IDX = 2 # macro
mmSDMA3_RLC7_RB_BASE_HI = 0x079a # macro
mmSDMA3_RLC7_RB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC7_RB_RPTR = 0x079b # macro
mmSDMA3_RLC7_RB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC7_RB_RPTR_HI = 0x079c # macro
mmSDMA3_RLC7_RB_RPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC7_RB_WPTR = 0x079d # macro
mmSDMA3_RLC7_RB_WPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC7_RB_WPTR_HI = 0x079e # macro
mmSDMA3_RLC7_RB_WPTR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC7_RB_WPTR_POLL_CNTL = 0x079f # macro
mmSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC7_RB_RPTR_ADDR_HI = 0x07a0 # macro
mmSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC7_RB_RPTR_ADDR_LO = 0x07a1 # macro
mmSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC7_IB_CNTL = 0x07a2 # macro
mmSDMA3_RLC7_IB_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC7_IB_RPTR = 0x07a3 # macro
mmSDMA3_RLC7_IB_RPTR_BASE_IDX = 2 # macro
mmSDMA3_RLC7_IB_OFFSET = 0x07a4 # macro
mmSDMA3_RLC7_IB_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC7_IB_BASE_LO = 0x07a5 # macro
mmSDMA3_RLC7_IB_BASE_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC7_IB_BASE_HI = 0x07a6 # macro
mmSDMA3_RLC7_IB_BASE_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC7_IB_SIZE = 0x07a7 # macro
mmSDMA3_RLC7_IB_SIZE_BASE_IDX = 2 # macro
mmSDMA3_RLC7_SKIP_CNTL = 0x07a8 # macro
mmSDMA3_RLC7_SKIP_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC7_CONTEXT_STATUS = 0x07a9 # macro
mmSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC7_DOORBELL = 0x07aa # macro
mmSDMA3_RLC7_DOORBELL_BASE_IDX = 2 # macro
mmSDMA3_RLC7_STATUS = 0x07c0 # macro
mmSDMA3_RLC7_STATUS_BASE_IDX = 2 # macro
mmSDMA3_RLC7_DOORBELL_LOG = 0x07c1 # macro
mmSDMA3_RLC7_DOORBELL_LOG_BASE_IDX = 2 # macro
mmSDMA3_RLC7_WATERMARK = 0x07c2 # macro
mmSDMA3_RLC7_WATERMARK_BASE_IDX = 2 # macro
mmSDMA3_RLC7_DOORBELL_OFFSET = 0x07c3 # macro
mmSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX = 2 # macro
mmSDMA3_RLC7_CSA_ADDR_LO = 0x07c4 # macro
mmSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC7_CSA_ADDR_HI = 0x07c5 # macro
mmSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC7_IB_SUB_REMAIN = 0x07c7 # macro
mmSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX = 2 # macro
mmSDMA3_RLC7_PREEMPT = 0x07c8 # macro
mmSDMA3_RLC7_PREEMPT_BASE_IDX = 2 # macro
mmSDMA3_RLC7_DUMMY_REG = 0x07c9 # macro
mmSDMA3_RLC7_DUMMY_REG_BASE_IDX = 2 # macro
mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI = 0x07ca # macro
mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro
mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO = 0x07cb # macro
mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro
mmSDMA3_RLC7_RB_AQL_CNTL = 0x07cc # macro
mmSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX = 2 # macro
mmSDMA3_RLC7_MINOR_PTR_UPDATE = 0x07cd # macro
mmSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro
mmSDMA3_RLC7_MIDCMD_DATA0 = 0x07d8 # macro
mmSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX = 2 # macro
mmSDMA3_RLC7_MIDCMD_DATA1 = 0x07d9 # macro
mmSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX = 2 # macro
mmSDMA3_RLC7_MIDCMD_DATA2 = 0x07da # macro
mmSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX = 2 # macro
mmSDMA3_RLC7_MIDCMD_DATA3 = 0x07db # macro
mmSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX = 2 # macro
mmSDMA3_RLC7_MIDCMD_DATA4 = 0x07dc # macro
mmSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX = 2 # macro
mmSDMA3_RLC7_MIDCMD_DATA5 = 0x07dd # macro
mmSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX = 2 # macro
mmSDMA3_RLC7_MIDCMD_DATA6 = 0x07de # macro
mmSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX = 2 # macro
mmSDMA3_RLC7_MIDCMD_DATA7 = 0x07df # macro
mmSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX = 2 # macro
mmSDMA3_RLC7_MIDCMD_DATA8 = 0x07e0 # macro
mmSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX = 2 # macro
mmSDMA3_RLC7_MIDCMD_DATA9 = 0x07e1 # macro
mmSDMA3_RLC7_MIDCMD_DATA9_BASE_IDX = 2 # macro
mmSDMA3_RLC7_MIDCMD_DATA10 = 0x07e2 # macro
mmSDMA3_RLC7_MIDCMD_DATA10_BASE_IDX = 2 # macro
mmSDMA3_RLC7_MIDCMD_CNTL = 0x07e3 # macro
mmSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX = 2 # macro
ixPCC_STALL_PATTERN_CTRL = 0x0000 # macro
ixPWRBRK_STALL_PATTERN_CTRL = 0x0001 # macro
ixPCC_STALL_PATTERN_1_2 = 0x0006 # macro
ixPCC_STALL_PATTERN_3_4 = 0x0007 # macro
ixPCC_STALL_PATTERN_5_6 = 0x0008 # macro
ixPCC_STALL_PATTERN_7 = 0x0009 # macro
ixPWRBRK_STALL_PATTERN_1_2 = 0x000a # macro
ixPWRBRK_STALL_PATTERN_3_4 = 0x000b # macro
ixPWRBRK_STALL_PATTERN_5_6 = 0x000c # macro
ixPWRBRK_STALL_PATTERN_7 = 0x000d # macro
ixPCC_PWRBRK_HYSTERESIS_CTRL = 0x000e # macro
ixEDC_STRETCH_PERF_COUNTER = 0x000f # macro
ixEDC_UNSTRETCH_PERF_COUNTER = 0x0010 # macro
ixEDC_STRETCH_NUM_PERF_COUNTER = 0x0011 # macro
ixGC_CAC_OVR_SEL = 0x0022 # macro
ixGC_CAC_OVR_VAL = 0x0023 # macro
ixGC_CAC_WEIGHT_BCI_0 = 0x0024 # macro
ixGC_CAC_WEIGHT_CB_0 = 0x0025 # macro
ixGC_CAC_WEIGHT_CB_1 = 0x0026 # macro
ixGC_CAC_WEIGHT_CB_2 = 0x0027 # macro
ixGC_CAC_WEIGHT_CB_3 = 0x0028 # macro
ixGC_CAC_WEIGHT_CB_4 = 0x0029 # macro
ixGC_CAC_WEIGHT_CP_0 = 0x002a # macro
ixGC_CAC_WEIGHT_CP_1 = 0x002b # macro
ixGC_CAC_WEIGHT_DB_0 = 0x002c # macro
ixGC_CAC_WEIGHT_DB_1 = 0x002d # macro
ixGC_CAC_WEIGHT_DB_2 = 0x002e # macro
ixGC_CAC_WEIGHT_DB_3 = 0x002f # macro
ixGC_CAC_WEIGHT_DB_4 = 0x0030 # macro
ixGC_CAC_WEIGHT_GDS_0 = 0x0031 # macro
ixGC_CAC_WEIGHT_GDS_1 = 0x0032 # macro
ixGC_CAC_WEIGHT_GDS_2 = 0x0033 # macro
ixGC_CAC_WEIGHT_LDS_0 = 0x0034 # macro
ixGC_CAC_WEIGHT_LDS_1 = 0x0035 # macro
ixGC_CAC_WEIGHT_LDS_2 = 0x0036 # macro
ixGC_CAC_WEIGHT_LDS_3 = 0x0037 # macro
ixGC_CAC_WEIGHT_LDS_4 = 0x0038 # macro
ixGC_CAC_WEIGHT_PA_0 = 0x0039 # macro
ixGC_CAC_WEIGHT_PA_1 = 0x003a # macro
ixGC_CAC_WEIGHT_PA_2 = 0x003b # macro
ixGC_CAC_WEIGHT_PA_3 = 0x003c # macro
ixGC_CAC_WEIGHT_PC_0 = 0x003d # macro
ixGC_CAC_WEIGHT_SC_0 = 0x003e # macro
ixGC_CAC_WEIGHT_SC_1 = 0x003f # macro
ixGC_CAC_WEIGHT_SC_2 = 0x0040 # macro
ixGC_CAC_WEIGHT_SC_3 = 0x0041 # macro
ixGC_CAC_WEIGHT_SPI_0 = 0x0042 # macro
ixGC_CAC_WEIGHT_SPI_1 = 0x0043 # macro
ixGC_CAC_WEIGHT_SPI_2 = 0x0044 # macro
ixGC_CAC_WEIGHT_SQ_0 = 0x0045 # macro
ixGC_CAC_WEIGHT_SQ_1 = 0x0046 # macro
ixGC_CAC_WEIGHT_SQ_2 = 0x0047 # macro
ixGC_CAC_WEIGHT_SQ_3 = 0x0048 # macro
ixGC_CAC_WEIGHT_SX_0 = 0x0049 # macro
ixGC_CAC_WEIGHT_SXRB_0 = 0x004a # macro
ixGC_CAC_WEIGHT_TA_0 = 0x004b # macro
ixGC_CAC_WEIGHT_TCP_0 = 0x004c # macro
ixGC_CAC_WEIGHT_TCP_1 = 0x004d # macro
ixGC_CAC_WEIGHT_TCP_2 = 0x004e # macro
ixGC_CAC_WEIGHT_TCP_3 = 0x004f # macro
ixGC_CAC_WEIGHT_TD_0 = 0x0050 # macro
ixGC_CAC_WEIGHT_TD_1 = 0x0051 # macro
ixGC_CAC_WEIGHT_TD_2 = 0x0052 # macro
ixGC_CAC_WEIGHT_TD_3 = 0x0053 # macro
ixGC_CAC_WEIGHT_TD_4 = 0x0054 # macro
ixGC_CAC_WEIGHT_TD_5 = 0x0055 # macro
ixGC_CAC_WEIGHT_RMI_0 = 0x0056 # macro
ixGC_CAC_WEIGHT_RMI_1 = 0x0057 # macro
ixGC_CAC_WEIGHT_EA_0 = 0x0058 # macro
ixGC_CAC_WEIGHT_EA_1 = 0x0059 # macro
ixGC_CAC_WEIGHT_EA_2 = 0x005a # macro
ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 = 0x005b # macro
ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 = 0x005c # macro
ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 = 0x005d # macro
ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 = 0x005e # macro
ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 = 0x005f # macro
ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 = 0x0060 # macro
ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 = 0x0061 # macro
ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 = 0x0062 # macro
ixGC_CAC_WEIGHT_UTCL2_VML2_0 = 0x0063 # macro
ixGC_CAC_WEIGHT_UTCL2_VML2_1 = 0x0064 # macro
ixGC_CAC_WEIGHT_UTCL2_VML2_2 = 0x0065 # macro
ixGC_CAC_WEIGHT_UTCL2_WALKER_0 = 0x0066 # macro
ixGC_CAC_WEIGHT_UTCL2_WALKER_1 = 0x0067 # macro
ixGC_CAC_WEIGHT_UTCL2_WALKER_2 = 0x0068 # macro
ixGC_CAC_WEIGHT_CU_0 = 0x0069 # macro
ixGC_CAC_WEIGHT_UTCL1_0 = 0x006a # macro
ixGC_CAC_WEIGHT_GE_0 = 0x006b # macro
ixGC_CAC_WEIGHT_GE_1 = 0x006c # macro
ixGC_CAC_WEIGHT_GE_2 = 0x006d # macro
ixGC_CAC_WEIGHT_GE_3 = 0x006e # macro
ixGC_CAC_WEIGHT_GE_4 = 0x006f # macro
ixGC_CAC_WEIGHT_GE_5 = 0x0070 # macro
ixGC_CAC_WEIGHT_GE_6 = 0x0071 # macro
ixGC_CAC_WEIGHT_GE_7 = 0x0072 # macro
ixGC_CAC_WEIGHT_GE_8 = 0x0073 # macro
ixGC_CAC_WEIGHT_GE_9 = 0x0074 # macro
ixGC_CAC_WEIGHT_GE_10 = 0x0075 # macro
ixGC_CAC_WEIGHT_PMM_0 = 0x0076 # macro
ixGC_CAC_WEIGHT_GL2C_0 = 0x0077 # macro
ixGC_CAC_WEIGHT_GL2C_1 = 0x0078 # macro
ixGC_CAC_WEIGHT_GL2C_2 = 0x0079 # macro
ixGC_CAC_WEIGHT_GUS_0 = 0x007a # macro
ixGC_CAC_WEIGHT_GUS_1 = 0x007b # macro
ixGC_CAC_WEIGHT_PH_0 = 0x007c # macro
ixGC_CAC_WEIGHT_PH_1 = 0x007d # macro
ixGC_CAC_WEIGHT_PH_2 = 0x007e # macro
ixGC_CAC_WEIGHT_PH_3 = 0x007f # macro
ixGC_CAC_WEIGHT_SDMA_0 = 0x0080 # macro
ixGC_CAC_WEIGHT_SDMA_1 = 0x0081 # macro
ixGC_CAC_WEIGHT_SDMA_2 = 0x0082 # macro
ixGC_CAC_WEIGHT_SDMA_3 = 0x0083 # macro
ixGC_CAC_WEIGHT_SDMA_4 = 0x0084 # macro
ixGC_CAC_WEIGHT_SDMA_5 = 0x0085 # macro
ixGC_CAC_WEIGHT_SP_0 = 0x0086 # macro
ixGC_CAC_WEIGHT_SP_1 = 0x0087 # macro
ixGC_CAC_WEIGHT_GL1C_0 = 0x0088 # macro
ixGC_CAC_WEIGHT_GL1C_1 = 0x0089 # macro
ixGC_CAC_WEIGHT_GL1C_2 = 0x008a # macro
ixGC_CAC_WEIGHT_CHC_0 = 0x008b # macro
ixGC_CAC_WEIGHT_CHC_1 = 0x008c # macro
ixGC_CAC_WEIGHT_SQC_0 = 0x008d # macro
ixGC_CAC_WEIGHT_SQC_1 = 0x008e # macro
ixGC_CAC_WEIGHT_RLC_0 = 0x008f # macro
ixGC_CAC_ACC_LDS0 = 0x0100 # macro
ixGC_CAC_ACC_LDS1 = 0x0101 # macro
ixGC_CAC_ACC_LDS2 = 0x0102 # macro
ixGC_CAC_ACC_LDS3 = 0x0103 # macro
ixGC_CAC_ACC_LDS4 = 0x0104 # macro
ixGC_CAC_ACC_LDS5 = 0x0105 # macro
ixGC_CAC_ACC_LDS6 = 0x0106 # macro
ixGC_CAC_ACC_LDS7 = 0x0107 # macro
ixGC_CAC_ACC_LDS8 = 0x0108 # macro
ixGC_CAC_ACC_BCI0 = 0x0109 # macro
ixGC_CAC_ACC_BCI1 = 0x010a # macro
ixGC_CAC_ACC_CB0 = 0x010b # macro
ixGC_CAC_ACC_CB1 = 0x010c # macro
ixGC_CAC_ACC_CB2 = 0x010d # macro
ixGC_CAC_ACC_CB3 = 0x010e # macro
ixGC_CAC_ACC_CB4 = 0x010f # macro
ixGC_CAC_ACC_CB5 = 0x0110 # macro
ixGC_CAC_ACC_CB6 = 0x0111 # macro
ixGC_CAC_ACC_CB7 = 0x0112 # macro
ixGC_CAC_ACC_CB8 = 0x0113 # macro
ixGC_CAC_ACC_CB9 = 0x0114 # macro
ixGC_CAC_ACC_DB0 = 0x0118 # macro
ixGC_CAC_ACC_DB1 = 0x0119 # macro
ixGC_CAC_ACC_DB2 = 0x011a # macro
ixGC_CAC_ACC_DB3 = 0x011b # macro
ixGC_CAC_ACC_DB4 = 0x011c # macro
ixGC_CAC_ACC_DB5 = 0x011d # macro
ixGC_CAC_ACC_DB6 = 0x011e # macro
ixGC_CAC_ACC_DB7 = 0x011f # macro
ixGC_CAC_ACC_DB8 = 0x0120 # macro
ixGC_CAC_ACC_DB9 = 0x0121 # macro
ixGC_CAC_ACC_GDS5 = 0x0127 # macro
ixGC_CAC_ACC_GDS6 = 0x0128 # macro
ixGC_CAC_ACC_PA0 = 0x0129 # macro
ixGC_CAC_ACC_PA1 = 0x012a # macro
ixGC_CAC_ACC_PA2 = 0x012b # macro
ixGC_CAC_ACC_PA3 = 0x012c # macro
ixGC_CAC_ACC_PA4 = 0x012d # macro
ixGC_CAC_ACC_PA5 = 0x012e # macro
ixGC_CAC_ACC_PA6 = 0x012f # macro
ixGC_CAC_ACC_PA7 = 0x0130 # macro
ixGC_CAC_ACC_PC0 = 0x0131 # macro
ixGC_CAC_ACC_SC0 = 0x0132 # macro
ixGC_CAC_ACC_SC1 = 0x0133 # macro
ixGC_CAC_ACC_SC2 = 0x0134 # macro
ixGC_CAC_ACC_SC3 = 0x0135 # macro
ixGC_CAC_ACC_SC4 = 0x0136 # macro
ixGC_CAC_ACC_SC5 = 0x0137 # macro
ixGC_CAC_ACC_SC6 = 0x0138 # macro
ixGC_CAC_ACC_SC7 = 0x0139 # macro
ixGC_CAC_ACC_SPI0 = 0x013a # macro
ixGC_CAC_ACC_SPI1 = 0x013b # macro
ixGC_CAC_ACC_SPI2 = 0x013c # macro
ixGC_CAC_ACC_SPI3 = 0x013d # macro
ixGC_CAC_ACC_SPI4 = 0x013e # macro
ixGC_CAC_ACC_SPI5 = 0x013f # macro
ixGC_CAC_ACC_SQ0_LOWER = 0x0140 # macro
ixGC_CAC_ACC_SQ0_UPPER = 0x0141 # macro
ixGC_CAC_ACC_SQ1_LOWER = 0x0142 # macro
ixGC_CAC_ACC_SQ1_UPPER = 0x0143 # macro
ixGC_CAC_ACC_SQ2_LOWER = 0x0144 # macro
ixGC_CAC_ACC_SQ2_UPPER = 0x0145 # macro
ixGC_CAC_ACC_SQ3_LOWER = 0x0146 # macro
ixGC_CAC_ACC_SQ3_UPPER = 0x0147 # macro
ixGC_CAC_ACC_SQ4_LOWER = 0x0148 # macro
ixGC_CAC_ACC_SQ4_UPPER = 0x0149 # macro
ixGC_CAC_ACC_SQ5_LOWER = 0x014a # macro
ixGC_CAC_ACC_SQ5_UPPER = 0x014b # macro
ixGC_CAC_ACC_SQ6_LOWER = 0x014c # macro
ixGC_CAC_ACC_SQ6_UPPER = 0x014d # macro
ixGC_CAC_ACC_SQ7_LOWER = 0x014e # macro
ixGC_CAC_ACC_SQ7_UPPER = 0x014f # macro
ixGC_CAC_ACC_SQ8_LOWER = 0x0150 # macro
ixGC_CAC_ACC_SQ8_UPPER = 0x0151 # macro
ixGC_CAC_ACC_SX0 = 0x0152 # macro
ixGC_CAC_ACC_SXRB0 = 0x0153 # macro
ixGC_CAC_ACC_TA0 = 0x0154 # macro
ixGC_CAC_ACC_TCP0 = 0x0155 # macro
ixGC_CAC_ACC_TCP1 = 0x0156 # macro
ixGC_CAC_ACC_TCP2 = 0x0157 # macro
ixGC_CAC_ACC_TCP3 = 0x0158 # macro
ixGC_CAC_ACC_TCP4 = 0x0159 # macro
ixGC_CAC_ACC_TCP5 = 0x015a # macro
ixGC_CAC_ACC_TCP6 = 0x015b # macro
ixGC_CAC_ACC_TCP7 = 0x015c # macro
ixGC_CAC_ACC_TD0 = 0x015d # macro
ixGC_CAC_ACC_TD1 = 0x015e # macro
ixGC_CAC_ACC_TD2 = 0x015f # macro
ixGC_CAC_ACC_TD3 = 0x0160 # macro
ixGC_CAC_ACC_TD4 = 0x0161 # macro
ixGC_CAC_ACC_TD5 = 0x0162 # macro
ixGC_CAC_ACC_TD6 = 0x0163 # macro
ixGC_CAC_ACC_TD7 = 0x0164 # macro
ixGC_CAC_ACC_TD8 = 0x0165 # macro
ixGC_CAC_ACC_TD9 = 0x0166 # macro
ixGC_CAC_ACC_TD10 = 0x0167 # macro
ixGC_CAC_ACC_RMI0 = 0x0168 # macro
ixGC_CAC_ACC_RMI1 = 0x0169 # macro
ixGC_CAC_ACC_RMI2 = 0x016a # macro
ixGC_CAC_ACC_RMI3 = 0x016b # macro
ixGC_CAC_ACC_UTCL2_ATCL20 = 0x0172 # macro
ixGC_CAC_ACC_UTCL2_ATCL21 = 0x0173 # macro
ixGC_CAC_ACC_UTCL2_ATCL22 = 0x0174 # macro
ixGC_CAC_ACC_UTCL2_ATCL23 = 0x0175 # macro
ixGC_CAC_ACC_UTCL2_ATCL24 = 0x0176 # macro
ixGC_CAC_ACC_CU0 = 0x018b # macro
ixGC_CAC_ACC_UTCL10 = 0x018c # macro
ixGC_CAC_ACC_SP0_LOWER = 0x01c2 # macro
ixGC_CAC_ACC_SP0_UPPER = 0x01c3 # macro
ixGC_CAC_ACC_SP1_LOWER = 0x01c4 # macro
ixGC_CAC_ACC_SP1_UPPER = 0x01c5 # macro
ixGC_CAC_ACC_SP2_LOWER = 0x01c6 # macro
ixGC_CAC_ACC_SP2_UPPER = 0x01c7 # macro
ixGC_CAC_ACC_GL1C0 = 0x01c8 # macro
ixGC_CAC_ACC_GL1C1 = 0x01c9 # macro
ixGC_CAC_ACC_GL1C2 = 0x01ca # macro
ixGC_CAC_ACC_GL1C3 = 0x01cb # macro
ixGC_CAC_ACC_GL1C4 = 0x01cc # macro
ixGC_CAC_ACC_SQC0 = 0x01cd # macro
ixGC_CAC_ACC_SQC1 = 0x01ce # macro
ixGC_CAC_ACC_SQC2 = 0x01cf # macro
ixGC_CAC_OVRD_BCI = 0x0200 # macro
ixGC_CAC_OVRD_CB = 0x0201 # macro
ixGC_CAC_OVRD_CP = 0x0203 # macro
ixGC_CAC_OVRD_DB = 0x0204 # macro
ixGC_CAC_OVRD_GDS = 0x0206 # macro
ixGC_CAC_OVRD_LDS = 0x0207 # macro
ixGC_CAC_OVRD_PA = 0x0208 # macro
ixGC_CAC_OVRD_PC = 0x0209 # macro
ixGC_CAC_OVRD_SC = 0x020a # macro
ixGC_CAC_OVRD_SPI = 0x020b # macro
ixGC_CAC_OVRD_CU = 0x020c # macro
ixGC_CAC_OVRD_SQ = 0x020d # macro
ixGC_CAC_OVRD_SX = 0x020e # macro
ixGC_CAC_OVRD_SXRB = 0x020f # macro
ixGC_CAC_OVRD_TA = 0x0210 # macro
ixGC_CAC_OVRD_TCP = 0x0211 # macro
ixGC_CAC_OVRD_TD = 0x0212 # macro
ixGC_CAC_OVRD_RMI = 0x0213 # macro
ixGC_CAC_OVRD_EA = 0x0214 # macro
ixGC_CAC_OVRD_UTCL2_ATCL2 = 0x0215 # macro
ixGC_CAC_OVRD_UTCL2_ROUTER = 0x0216 # macro
ixGC_CAC_OVRD_UTCL2_VML2 = 0x0217 # macro
ixGC_CAC_OVRD_UTCL2_WALKER = 0x0218 # macro
ixGC_CAC_OVRD_SP = 0x0219 # macro
ixGC_CAC_OVRD_UTCL1 = 0x021a # macro
ixGC_CAC_OVRD_CHC = 0x021b # macro
ixGC_CAC_OVRD_GE = 0x021c # macro
ixGC_CAC_OVRD_PMM = 0x021d # macro
ixGC_CAC_OVRD_GL2C = 0x021e # macro
ixGC_CAC_OVRD_GUS = 0x021f # macro
ixGC_CAC_OVRD_PH = 0x0220 # macro
ixGC_CAC_OVRD_SDMA = 0x0221 # macro
ixGC_CAC_OVRD_GL1C = 0x0222 # macro
ixGC_CAC_OVRD_SQC = 0x0223 # macro
ixGC_CAC_OVRD_RLC = 0x0224 # macro
ixGC_CAC_OVRD_GE_HI = 0x0225 # macro
ixSE_CAC_OVR_SEL = 0x0002 # macro
ixSE_CAC_OVR_VAL = 0x0003 # macro
ixGLB_CPG_SAMPLEDELAY = 0x0000 # macro
ixGLB_CPC_SAMPLEDELAY = 0x0001 # macro
ixGLB_CPF_SAMPLEDELAY = 0x0002 # macro
ixGLB_GDS_SAMPLEDELAY = 0x0003 # macro
ixGLB_GCR_SAMPLEDELAY = 0x0004 # macro
ixGLB_PH_SAMPLEDELAY = 0x0005 # macro
ixGLB_GE1_SAMPLEDELAY = 0x0006 # macro
ixGLB_GE2DIST_SAMPLEDELAY = 0x0007 # macro
ixGLB_GUS_SAMPLEDELAY = 0x0008 # macro
ixGLB_CHA_SAMPLEDELAY = 0x0009 # macro
ixGLB_CHCG_SAMPLEDELAY = 0x000a # macro
ixGLB_ATCL2_SAMPLEDELAY = 0x000b # macro
ixGLB_VML2_SAMPLEDELAY = 0x000c # macro
ixGLB_SDMA0_SAMPLEDELAY = 0x000d # macro
ixGLB_SDMA1_SAMPLEDELAY = 0x000e # macro
ixGLB_SDMA2_SAMPLEDELAY = 0x000f # macro
ixGLB_SDMA3_SAMPLEDELAY = 0x0010 # macro
ixGLB_GL2A0_SAMPLEDELAY = 0x0011 # macro
ixGLB_GL2A1_SAMPLEDELAY = 0x0012 # macro
ixGLB_GL2A2_SAMPLEDELAY = 0x0013 # macro
ixGLB_GL2A3_SAMPLEDELAY = 0x0014 # macro
ixGLB_GL2C0_SAMPLEDELAY = 0x0015 # macro
ixGLB_GL2C1_SAMPLEDELAY = 0x0016 # macro
ixGLB_GL2C2_SAMPLEDELAY = 0x0017 # macro
ixGLB_GL2C3_SAMPLEDELAY = 0x0018 # macro
ixGLB_GL2C4_SAMPLEDELAY = 0x0019 # macro
ixGLB_GL2C5_SAMPLEDELAY = 0x001a # macro
ixGLB_GL2C6_SAMPLEDELAY = 0x001b # macro
ixGLB_GL2C7_SAMPLEDELAY = 0x001c # macro
ixGLB_GL2C8_SAMPLEDELAY = 0x001d # macro
ixGLB_GL2C9_SAMPLEDELAY = 0x001e # macro
ixGLB_GL2C10_SAMPLEDELAY = 0x001f # macro
ixGLB_GL2C11_SAMPLEDELAY = 0x0020 # macro
ixGLB_GL2C12_SAMPLEDELAY = 0x0021 # macro
ixGLB_GL2C13_SAMPLEDELAY = 0x0022 # macro
ixGLB_GL2C14_SAMPLEDELAY = 0x0023 # macro
ixGLB_GL2C15_SAMPLEDELAY = 0x0024 # macro
ixGLB_EA0_SAMPLEDELAY = 0x0025 # macro
ixGLB_EA1_SAMPLEDELAY = 0x0026 # macro
ixGLB_EA2_SAMPLEDELAY = 0x0027 # macro
ixGLB_EA3_SAMPLEDELAY = 0x0028 # macro
ixGLB_EA4_SAMPLEDELAY = 0x0029 # macro
ixGLB_EA5_SAMPLEDELAY = 0x002a # macro
ixGLB_EA6_SAMPLEDELAY = 0x002b # macro
ixGLB_EA7_SAMPLEDELAY = 0x002c # macro
ixGLB_EA8_SAMPLEDELAY = 0x002d # macro
ixGLB_EA9_SAMPLEDELAY = 0x002e # macro
ixGLB_EA10_SAMPLEDELAY = 0x002f # macro
ixGLB_EA11_SAMPLEDELAY = 0x0030 # macro
ixGLB_EA12_SAMPLEDELAY = 0x0031 # macro
ixGLB_EA13_SAMPLEDELAY = 0x0032 # macro
ixGLB_EA14_SAMPLEDELAY = 0x0033 # macro
ixGLB_EA15_SAMPLEDELAY = 0x0034 # macro
ixGLB_CHC0_SAMPLEDELAY = 0x0035 # macro
ixGLB_CHC1_SAMPLEDELAY = 0x0036 # macro
ixGLB_CHC2_SAMPLEDELAY = 0x0037 # macro
ixGLB_CHC3_SAMPLEDELAY = 0x0038 # macro
ixGLB_GE2SE0_SAMPLEDELAY = 0x0039 # macro
ixGLB_GE2SE1_SAMPLEDELAY = 0x003a # macro
ixGLB_GE2SE2_SAMPLEDELAY = 0x003b # macro
ixGLB_GE2SE3_SAMPLEDELAY = 0x003c # macro
ixSE_SPI_SAMPLEDELAY = 0x0000 # macro
ixSE_SQG_SAMPLEDELAY = 0x0001 # macro
ixSE_CBR_SAMPLEDELAY = 0x0002 # macro
ixSE_DBR_SAMPLEDELAY = 0x0003 # macro
ixSE_PA_SAMPLEDELAY = 0x0004 # macro
ixSE_SA0SX_SAMPLEDELAY = 0x0005 # macro
ixSE_SA0GL1A_SAMPLEDELAY = 0x0006 # macro
ixSE_SA0GL1CG_SAMPLEDELAY = 0x0007 # macro
ixSE_SA0CB0_SAMPLEDELAY = 0x0008 # macro
ixSE_SA0CB1_SAMPLEDELAY = 0x0009 # macro
ixSE_SA0DB0_SAMPLEDELAY = 0x000a # macro
ixSE_SA0DB1_SAMPLEDELAY = 0x000b # macro
ixSE_SA0SC0_SAMPLEDELAY = 0x000c # macro
ixSE_SA0SC1_SAMPLEDELAY = 0x000d # macro
ixSE_SA0RMI0_SAMPLEDELAY = 0x000e # macro
ixSE_SA0RMI1_SAMPLEDELAY = 0x000f # macro
ixSE_SA0GL1C0_SAMPLEDELAY = 0x0010 # macro
ixSE_SA0GL1C1_SAMPLEDELAY = 0x0011 # macro
ixSE_SA0GL1C2_SAMPLEDELAY = 0x0012 # macro
ixSE_SA0GL1C3_SAMPLEDELAY = 0x0013 # macro
ixSE_SA0WGP00TA0_SAMPLEDELAY = 0x0014 # macro
ixSE_SA0WGP00TA1_SAMPLEDELAY = 0x0015 # macro
ixSE_SA0WGP00TD0_SAMPLEDELAY = 0x0016 # macro
ixSE_SA0WGP00TD1_SAMPLEDELAY = 0x0017 # macro
ixSE_SA0WGP00TCP0_SAMPLEDELAY = 0x0018 # macro
ixSE_SA0WGP00TCP1_SAMPLEDELAY = 0x0019 # macro
ixSE_SA0WGP01TA0_SAMPLEDELAY = 0x001a # macro
ixSE_SA0WGP01TA1_SAMPLEDELAY = 0x001b # macro
ixSE_SA0WGP01TD0_SAMPLEDELAY = 0x001c # macro
ixSE_SA0WGP01TD1_SAMPLEDELAY = 0x001d # macro
ixSE_SA0WGP01TCP0_SAMPLEDELAY = 0x001e # macro
ixSE_SA0WGP01TCP1_SAMPLEDELAY = 0x001f # macro
ixSE_SA0WGP02TA0_SAMPLEDELAY = 0x0020 # macro
ixSE_SA0WGP02TA1_SAMPLEDELAY = 0x0021 # macro
ixSE_SA0WGP02TD0_SAMPLEDELAY = 0x0022 # macro
ixSE_SA0WGP02TD1_SAMPLEDELAY = 0x0023 # macro
ixSE_SA0WGP02TCP0_SAMPLEDELAY = 0x0024 # macro
ixSE_SA0WGP02TCP1_SAMPLEDELAY = 0x0025 # macro
ixSE_SA0WGP03TA0_SAMPLEDELAY = 0x0026 # macro
ixSE_SA0WGP03TA1_SAMPLEDELAY = 0x0027 # macro
ixSE_SA0WGP03TD0_SAMPLEDELAY = 0x0028 # macro
ixSE_SA0WGP03TD1_SAMPLEDELAY = 0x0029 # macro
ixSE_SA0WGP03TCP0_SAMPLEDELAY = 0x002a # macro
ixSE_SA0WGP03TCP1_SAMPLEDELAY = 0x002b # macro
ixSE_SA0WGP04TA0_SAMPLEDELAY = 0x002c # macro
ixSE_SA0WGP04TA1_SAMPLEDELAY = 0x002d # macro
ixSE_SA0WGP04TD0_SAMPLEDELAY = 0x002e # macro
ixSE_SA0WGP04TD1_SAMPLEDELAY = 0x002f # macro
ixSE_SA0WGP04TCP0_SAMPLEDELAY = 0x0030 # macro
ixSE_SA0WGP04TCP1_SAMPLEDELAY = 0x0031 # macro
ixSE_SA1SX_SAMPLEDELAY = 0x0032 # macro
ixSE_SA1GL1A_SAMPLEDELAY = 0x0033 # macro
ixSE_SA1GL1CG_SAMPLEDELAY = 0x0034 # macro
ixSE_SA1CB0_SAMPLEDELAY = 0x0035 # macro
ixSE_SA1CB1_SAMPLEDELAY = 0x0036 # macro
ixSE_SA1DB0_SAMPLEDELAY = 0x0037 # macro
ixSE_SA1DB1_SAMPLEDELAY = 0x0038 # macro
ixSE_SA1SC0_SAMPLEDELAY = 0x0039 # macro
ixSE_SA1SC1_SAMPLEDELAY = 0x003a # macro
ixSE_SA1RMI0_SAMPLEDELAY = 0x003b # macro
ixSE_SA1RMI1_SAMPLEDELAY = 0x003c # macro
ixSE_SA1GL1C0_SAMPLEDELAY = 0x003d # macro
ixSE_SA1GL1C1_SAMPLEDELAY = 0x003e # macro
ixSE_SA1GL1C2_SAMPLEDELAY = 0x003f # macro
ixSE_SA1GL1C3_SAMPLEDELAY = 0x0040 # macro
ixSE_SA1WGP00TA0_SAMPLEDELAY = 0x0041 # macro
ixSE_SA1WGP00TA1_SAMPLEDELAY = 0x0042 # macro
ixSE_SA1WGP00TD0_SAMPLEDELAY = 0x0043 # macro
ixSE_SA1WGP00TD1_SAMPLEDELAY = 0x0044 # macro
ixSE_SA1WGP00TCP0_SAMPLEDELAY = 0x0045 # macro
ixSE_SA1WGP00TCP1_SAMPLEDELAY = 0x0046 # macro
ixSE_SA1WGP01TA0_SAMPLEDELAY = 0x0047 # macro
ixSE_SA1WGP01TA1_SAMPLEDELAY = 0x0048 # macro
ixSE_SA1WGP01TD0_SAMPLEDELAY = 0x0049 # macro
ixSE_SA1WGP01TD1_SAMPLEDELAY = 0x004a # macro
ixSE_SA1WGP01TCP0_SAMPLEDELAY = 0x004b # macro
ixSE_SA1WGP01TCP1_SAMPLEDELAY = 0x004c # macro
ixSE_SA1WGP02TA0_SAMPLEDELAY = 0x004d # macro
ixSE_SA1WGP02TA1_SAMPLEDELAY = 0x004e # macro
ixSE_SA1WGP02TD0_SAMPLEDELAY = 0x004f # macro
ixSE_SA1WGP02TD1_SAMPLEDELAY = 0x0050 # macro
ixSE_SA1WGP02TCP0_SAMPLEDELAY = 0x0051 # macro
ixSE_SA1WGP02TCP1_SAMPLEDELAY = 0x0052 # macro
ixSE_SA1WGP03TA0_SAMPLEDELAY = 0x0053 # macro
ixSE_SA1WGP03TA1_SAMPLEDELAY = 0x0054 # macro
ixSE_SA1WGP03TD0_SAMPLEDELAY = 0x0055 # macro
ixSE_SA1WGP03TD1_SAMPLEDELAY = 0x0056 # macro
ixSE_SA1WGP03TCP0_SAMPLEDELAY = 0x0057 # macro
ixSE_SA1WGP03TCP1_SAMPLEDELAY = 0x0058 # macro
ixSE_SA1WGP04TA0_SAMPLEDELAY = 0x0059 # macro
ixSE_SA1WGP04TA1_SAMPLEDELAY = 0x005a # macro
ixSE_SA1WGP04TD0_SAMPLEDELAY = 0x005b # macro
ixSE_SA1WGP04TD1_SAMPLEDELAY = 0x005c # macro
ixSE_SA1WGP04TCP0_SAMPLEDELAY = 0x005d # macro
ixSE_SA1WGP04TCP1_SAMPLEDELAY = 0x005e # macro
ixSA_WGP_BLK_ID = 0x0000 # macro
ixSQ_WAVE_HW_ID_LEGACY = 0x0104 # macro
ixSQ_WAVE_INST_DW0 = 0x010a # macro
ixSQ_WAVE_VGPR_OFFSET = 0x011b # macro
ixSQ_WAVE_TTMP2 = 0x026e # macro
ixSQ_INTERRUPT_WORD_AUTO = 0x20c0 # macro
ixSQ_INTERRUPT_WORD_ERROR = 0x20c0 # macro
ixSQ_INTERRUPT_WORD_WAVE = 0x20c0 # macro
ixDIDT_SQ_CTRL0 = 0x0000 # macro
ixDIDT_SQ_CTRL1 = 0x0001 # macro
ixDIDT_SQ_CTRL2 = 0x0002 # macro
ixDIDT_SQ_CTRL_OCP = 0x0003 # macro
ixDIDT_SQ_STALL_CTRL = 0x0004 # macro
ixDIDT_SQ_TUNING_CTRL = 0x0005 # macro
ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL = 0x0006 # macro
ixDIDT_SQ_CTRL3 = 0x0007 # macro
ixDIDT_SQ_STALL_PATTERN_1_2 = 0x0008 # macro
ixDIDT_SQ_STALL_PATTERN_3_4 = 0x0009 # macro
ixDIDT_SQ_STALL_PATTERN_5_6 = 0x000a # macro
ixDIDT_SQ_STALL_PATTERN_7 = 0x000b # macro
ixDIDT_SQ_MPD_SCALE_FACTOR = 0x000c # macro
ixDIDT_SQ_STALL_RELEASE_CNTL0 = 0x000d # macro
ixDIDT_SQ_STALL_RELEASE_CNTL1 = 0x000e # macro
ixDIDT_SQ_STALL_RELEASE_CNTL_STATUS = 0x000f # macro
ixDIDT_SQ_WEIGHT0_3 = 0x0010 # macro
ixDIDT_SQ_WEIGHT4_7 = 0x0011 # macro
ixDIDT_SQ_WEIGHT8_11 = 0x0012 # macro
ixDIDT_SQ_EDC_CTRL = 0x0013 # macro
ixDIDT_SQ_EDC_THRESHOLD = 0x0014 # macro
ixDIDT_SQ_EDC_STALL_PATTERN_1_2 = 0x0015 # macro
ixDIDT_SQ_EDC_STALL_PATTERN_3_4 = 0x0016 # macro
ixDIDT_SQ_EDC_STALL_PATTERN_5_6 = 0x0017 # macro
ixDIDT_SQ_EDC_STALL_PATTERN_7 = 0x0018 # macro
ixDIDT_SQ_EDC_TIMER_PERIOD = 0x0019 # macro
ixDIDT_SQ_THROTTLE_CTRL = 0x001a # macro
ixDIDT_SQ_EDC_STALL_DELAY_1 = 0x001b # macro
ixDIDT_SQ_EDC_STALL_DELAY_2 = 0x001c # macro
ixDIDT_SQ_EDC_STALL_DELAY_3 = 0x001d # macro
ixDIDT_SQ_EDC_STATUS = 0x001f # macro
ixDIDT_SQ_EDC_OVERFLOW = 0x0020 # macro
ixDIDT_SQ_EDC_ROLLING_POWER_DELTA = 0x0021 # macro
ixDIDT_SQ_EDC_PCC_PERF_COUNTER = 0x0022 # macro
ixDIDT_DB_CTRL0 = 0x0030 # macro
ixDIDT_DB_CTRL1 = 0x0031 # macro
ixDIDT_DB_CTRL2 = 0x0032 # macro
ixDIDT_DB_CTRL_OCP = 0x0033 # macro
ixDIDT_DB_STALL_CTRL = 0x0034 # macro
ixDIDT_DB_TUNING_CTRL = 0x0035 # macro
ixDIDT_DB_STALL_AUTO_RELEASE_CTRL = 0x0036 # macro
ixDIDT_DB_CTRL3 = 0x0037 # macro
ixDIDT_DB_STALL_PATTERN_1_2 = 0x0038 # macro
ixDIDT_DB_STALL_PATTERN_3_4 = 0x0039 # macro
ixDIDT_DB_STALL_PATTERN_5_6 = 0x003a # macro
ixDIDT_DB_STALL_PATTERN_7 = 0x003b # macro
ixDIDT_DB_MPD_SCALE_FACTOR = 0x003c # macro
ixDIDT_DB_STALL_RELEASE_CNTL0 = 0x003d # macro
ixDIDT_DB_STALL_RELEASE_CNTL1 = 0x003e # macro
ixDIDT_DB_STALL_RELEASE_CNTL_STATUS = 0x003f # macro
ixDIDT_DB_WEIGHT0_3 = 0x0040 # macro
ixDIDT_DB_WEIGHT4_7 = 0x0041 # macro
ixDIDT_DB_WEIGHT8_11 = 0x0042 # macro
ixDIDT_DB_EDC_CTRL = 0x0043 # macro
ixDIDT_DB_EDC_THRESHOLD = 0x0044 # macro
ixDIDT_DB_EDC_STALL_PATTERN_1_2 = 0x0045 # macro
ixDIDT_DB_EDC_STALL_PATTERN_3_4 = 0x0046 # macro
ixDIDT_DB_EDC_STALL_PATTERN_5_6 = 0x0047 # macro
ixDIDT_DB_EDC_STALL_PATTERN_7 = 0x0048 # macro
ixDIDT_DB_EDC_TIMER_PERIOD = 0x0049 # macro
ixDIDT_DB_THROTTLE_CTRL = 0x004a # macro
ixDIDT_DB_EDC_STALL_DELAY_1 = 0x004b # macro
ixDIDT_DB_EDC_STATUS = 0x004f # macro
ixDIDT_DB_EDC_OVERFLOW = 0x0050 # macro
ixDIDT_DB_EDC_ROLLING_POWER_DELTA = 0x0051 # macro
ixDIDT_DB_EDC_PCC_PERF_COUNTER = 0x0052 # macro
ixDIDT_TD_CTRL0 = 0x0060 # macro
ixDIDT_TD_CTRL1 = 0x0061 # macro
ixDIDT_TD_CTRL2 = 0x0062 # macro
ixDIDT_TD_CTRL_OCP = 0x0063 # macro
ixDIDT_TD_STALL_CTRL = 0x0064 # macro
ixDIDT_TD_TUNING_CTRL = 0x0065 # macro
ixDIDT_TD_STALL_AUTO_RELEASE_CTRL = 0x0066 # macro
ixDIDT_TD_CTRL3 = 0x0067 # macro
ixDIDT_TD_STALL_PATTERN_1_2 = 0x0068 # macro
ixDIDT_TD_STALL_PATTERN_3_4 = 0x0069 # macro
ixDIDT_TD_STALL_PATTERN_5_6 = 0x006a # macro
ixDIDT_TD_STALL_PATTERN_7 = 0x006b # macro
ixDIDT_TD_MPD_SCALE_FACTOR = 0x006c # macro
ixDIDT_TD_STALL_RELEASE_CNTL0 = 0x006d # macro
ixDIDT_TD_STALL_RELEASE_CNTL1 = 0x006e # macro
ixDIDT_TD_STALL_RELEASE_CNTL_STATUS = 0x006f # macro
ixDIDT_TD_WEIGHT0_3 = 0x0070 # macro
ixDIDT_TD_WEIGHT4_7 = 0x0071 # macro
ixDIDT_TD_WEIGHT8_11 = 0x0072 # macro
ixDIDT_TD_EDC_CTRL = 0x0073 # macro
ixDIDT_TD_EDC_THRESHOLD = 0x0074 # macro
ixDIDT_TD_EDC_STALL_PATTERN_1_2 = 0x0075 # macro
ixDIDT_TD_EDC_STALL_PATTERN_3_4 = 0x0076 # macro
ixDIDT_TD_EDC_STALL_PATTERN_5_6 = 0x0077 # macro
ixDIDT_TD_EDC_STALL_PATTERN_7 = 0x0078 # macro
ixDIDT_TD_EDC_TIMER_PERIOD = 0x0079 # macro
ixDIDT_TD_THROTTLE_CTRL = 0x007a # macro
ixDIDT_TD_EDC_STALL_DELAY_1 = 0x007b # macro
ixDIDT_TD_EDC_STALL_DELAY_2 = 0x007c # macro
ixDIDT_TD_EDC_STALL_DELAY_3 = 0x007d # macro
ixDIDT_TD_EDC_STATUS = 0x007f # macro
ixDIDT_TD_EDC_OVERFLOW = 0x0080 # macro
ixDIDT_TD_EDC_ROLLING_POWER_DELTA = 0x0081 # macro
ixDIDT_TD_EDC_PCC_PERF_COUNTER = 0x0082 # macro
ixDIDT_TCP_CTRL0 = 0x0090 # macro
ixDIDT_TCP_CTRL1 = 0x0091 # macro
ixDIDT_TCP_CTRL2 = 0x0092 # macro
ixDIDT_TCP_CTRL_OCP = 0x0093 # macro
ixDIDT_TCP_STALL_CTRL = 0x0094 # macro
ixDIDT_TCP_TUNING_CTRL = 0x0095 # macro
ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL = 0x0096 # macro
ixDIDT_TCP_CTRL3 = 0x0097 # macro
ixDIDT_TCP_STALL_PATTERN_1_2 = 0x0098 # macro
ixDIDT_TCP_STALL_PATTERN_3_4 = 0x0099 # macro
ixDIDT_TCP_STALL_PATTERN_5_6 = 0x009a # macro
ixDIDT_TCP_STALL_PATTERN_7 = 0x009b # macro
ixDIDT_TCP_MPD_SCALE_FACTOR = 0x009c # macro
ixDIDT_TCP_STALL_RELEASE_CNTL0 = 0x009d # macro
ixDIDT_TCP_STALL_RELEASE_CNTL1 = 0x009e # macro
ixDIDT_TCP_STALL_RELEASE_CNTL_STATUS = 0x009f # macro
ixDIDT_TCP_WEIGHT0_3 = 0x00a0 # macro
ixDIDT_TCP_WEIGHT4_7 = 0x00a1 # macro
ixDIDT_TCP_WEIGHT8_11 = 0x00a2 # macro
ixDIDT_TCP_EDC_CTRL = 0x00a3 # macro
ixDIDT_TCP_EDC_THRESHOLD = 0x00a4 # macro
ixDIDT_TCP_EDC_STALL_PATTERN_1_2 = 0x00a5 # macro
ixDIDT_TCP_EDC_STALL_PATTERN_3_4 = 0x00a6 # macro
ixDIDT_TCP_EDC_STALL_PATTERN_5_6 = 0x00a7 # macro
ixDIDT_TCP_EDC_STALL_PATTERN_7 = 0x00a8 # macro
ixDIDT_TCP_EDC_TIMER_PERIOD = 0x00a9 # macro
ixDIDT_TCP_THROTTLE_CTRL = 0x00aa # macro
ixDIDT_TCP_EDC_STALL_DELAY_1 = 0x00ab # macro
ixDIDT_TCP_EDC_STALL_DELAY_2 = 0x00ac # macro
ixDIDT_TCP_EDC_STALL_DELAY_3 = 0x00ad # macro
ixDIDT_TCP_EDC_STATUS = 0x00af # macro
ixDIDT_TCP_EDC_OVERFLOW = 0x00b0 # macro
ixDIDT_TCP_EDC_ROLLING_POWER_DELTA = 0x00b1 # macro
ixDIDT_TCP_EDC_PCC_PERF_COUNTER = 0x00b2 # macro
ixDIDT_SQ_STALL_EVENT_COUNTER = 0x00c0 # macro
ixDIDT_DB_STALL_EVENT_COUNTER = 0x00c1 # macro
ixDIDT_TD_STALL_EVENT_COUNTER = 0x00c2 # macro
ixDIDT_TCP_STALL_EVENT_COUNTER = 0x00c3 # macro
_sienna_cichlid_ip_offset_HEADER = True # macro
MAX_INSTANCE = 7 # macro
MAX_SEGMENT = 5 # macro
ATHUB_BASE__INST0_SEG0 = 0x00000C00 # macro
ATHUB_BASE__INST0_SEG1 = 0x02408C00 # macro
ATHUB_BASE__INST0_SEG2 = 0 # macro
ATHUB_BASE__INST0_SEG3 = 0 # macro
ATHUB_BASE__INST0_SEG4 = 0 # macro
ATHUB_BASE__INST1_SEG0 = 0 # macro
ATHUB_BASE__INST1_SEG1 = 0 # macro
ATHUB_BASE__INST1_SEG2 = 0 # macro
ATHUB_BASE__INST1_SEG3 = 0 # macro
ATHUB_BASE__INST1_SEG4 = 0 # macro
ATHUB_BASE__INST2_SEG0 = 0 # macro
ATHUB_BASE__INST2_SEG1 = 0 # macro
ATHUB_BASE__INST2_SEG2 = 0 # macro
ATHUB_BASE__INST2_SEG3 = 0 # macro
ATHUB_BASE__INST2_SEG4 = 0 # macro
ATHUB_BASE__INST3_SEG0 = 0 # macro
ATHUB_BASE__INST3_SEG1 = 0 # macro
ATHUB_BASE__INST3_SEG2 = 0 # macro
ATHUB_BASE__INST3_SEG3 = 0 # macro
ATHUB_BASE__INST3_SEG4 = 0 # macro
ATHUB_BASE__INST4_SEG0 = 0 # macro
ATHUB_BASE__INST4_SEG1 = 0 # macro
ATHUB_BASE__INST4_SEG2 = 0 # macro
ATHUB_BASE__INST4_SEG3 = 0 # macro
ATHUB_BASE__INST4_SEG4 = 0 # macro
ATHUB_BASE__INST5_SEG0 = 0 # macro
ATHUB_BASE__INST5_SEG1 = 0 # macro
ATHUB_BASE__INST5_SEG2 = 0 # macro
ATHUB_BASE__INST5_SEG3 = 0 # macro
ATHUB_BASE__INST5_SEG4 = 0 # macro
ATHUB_BASE__INST6_SEG0 = 0 # macro
ATHUB_BASE__INST6_SEG1 = 0 # macro
ATHUB_BASE__INST6_SEG2 = 0 # macro
ATHUB_BASE__INST6_SEG3 = 0 # macro
ATHUB_BASE__INST6_SEG4 = 0 # macro
CLK_BASE__INST0_SEG0 = 0x00016C00 # macro
CLK_BASE__INST0_SEG1 = 0x02401800 # macro
CLK_BASE__INST0_SEG2 = 0 # macro
CLK_BASE__INST0_SEG3 = 0 # macro
CLK_BASE__INST0_SEG4 = 0 # macro
CLK_BASE__INST1_SEG0 = 0x00016E00 # macro
CLK_BASE__INST1_SEG1 = 0x02401C00 # macro
CLK_BASE__INST1_SEG2 = 0 # macro
CLK_BASE__INST1_SEG3 = 0 # macro
CLK_BASE__INST1_SEG4 = 0 # macro
CLK_BASE__INST2_SEG0 = 0x00017000 # macro
CLK_BASE__INST2_SEG1 = 0x02402000 # macro
CLK_BASE__INST2_SEG2 = 0 # macro
CLK_BASE__INST2_SEG3 = 0 # macro
CLK_BASE__INST2_SEG4 = 0 # macro
CLK_BASE__INST3_SEG0 = 0x00017200 # macro
CLK_BASE__INST3_SEG1 = 0x02402400 # macro
CLK_BASE__INST3_SEG2 = 0 # macro
CLK_BASE__INST3_SEG3 = 0 # macro
CLK_BASE__INST3_SEG4 = 0 # macro
CLK_BASE__INST4_SEG0 = 0x0001B000 # macro
CLK_BASE__INST4_SEG1 = 0x0242D800 # macro
CLK_BASE__INST4_SEG2 = 0 # macro
CLK_BASE__INST4_SEG3 = 0 # macro
CLK_BASE__INST4_SEG4 = 0 # macro
CLK_BASE__INST5_SEG0 = 0x0001B200 # macro
CLK_BASE__INST5_SEG1 = 0x0242DC00 # macro
CLK_BASE__INST5_SEG2 = 0 # macro
CLK_BASE__INST5_SEG3 = 0 # macro
CLK_BASE__INST5_SEG4 = 0 # macro
CLK_BASE__INST6_SEG0 = 0x0001B400 # macro
CLK_BASE__INST6_SEG1 = 0x0242E000 # macro
CLK_BASE__INST6_SEG2 = 0 # macro
CLK_BASE__INST6_SEG3 = 0 # macro
CLK_BASE__INST6_SEG4 = 0 # macro
DF_BASE__INST0_SEG0 = 0x00007000 # macro
DF_BASE__INST0_SEG1 = 0x0240B800 # macro
DF_BASE__INST0_SEG2 = 0 # macro
DF_BASE__INST0_SEG3 = 0 # macro
DF_BASE__INST0_SEG4 = 0 # macro
DF_BASE__INST1_SEG0 = 0 # macro
DF_BASE__INST1_SEG1 = 0 # macro
DF_BASE__INST1_SEG2 = 0 # macro
DF_BASE__INST1_SEG3 = 0 # macro
DF_BASE__INST1_SEG4 = 0 # macro
DF_BASE__INST2_SEG0 = 0 # macro
DF_BASE__INST2_SEG1 = 0 # macro
DF_BASE__INST2_SEG2 = 0 # macro
DF_BASE__INST2_SEG3 = 0 # macro
DF_BASE__INST2_SEG4 = 0 # macro
DF_BASE__INST3_SEG0 = 0 # macro
DF_BASE__INST3_SEG1 = 0 # macro
DF_BASE__INST3_SEG2 = 0 # macro
DF_BASE__INST3_SEG3 = 0 # macro
DF_BASE__INST3_SEG4 = 0 # macro
DF_BASE__INST4_SEG0 = 0 # macro
DF_BASE__INST4_SEG1 = 0 # macro
DF_BASE__INST4_SEG2 = 0 # macro
DF_BASE__INST4_SEG3 = 0 # macro
DF_BASE__INST4_SEG4 = 0 # macro
DF_BASE__INST5_SEG0 = 0 # macro
DF_BASE__INST5_SEG1 = 0 # macro
DF_BASE__INST5_SEG2 = 0 # macro
DF_BASE__INST5_SEG3 = 0 # macro
DF_BASE__INST5_SEG4 = 0 # macro
DF_BASE__INST6_SEG0 = 0 # macro
DF_BASE__INST6_SEG1 = 0 # macro
DF_BASE__INST6_SEG2 = 0 # macro
DF_BASE__INST6_SEG3 = 0 # macro
DF_BASE__INST6_SEG4 = 0 # macro
DIO_BASE__INST0_SEG0 = 0x02404000 # macro
DIO_BASE__INST0_SEG1 = 0 # macro
DIO_BASE__INST0_SEG2 = 0 # macro
DIO_BASE__INST0_SEG3 = 0 # macro
DIO_BASE__INST0_SEG4 = 0 # macro
DIO_BASE__INST1_SEG0 = 0 # macro
DIO_BASE__INST1_SEG1 = 0 # macro
DIO_BASE__INST1_SEG2 = 0 # macro
DIO_BASE__INST1_SEG3 = 0 # macro
DIO_BASE__INST1_SEG4 = 0 # macro
DIO_BASE__INST2_SEG0 = 0 # macro
DIO_BASE__INST2_SEG1 = 0 # macro
DIO_BASE__INST2_SEG2 = 0 # macro
DIO_BASE__INST2_SEG3 = 0 # macro
DIO_BASE__INST2_SEG4 = 0 # macro
DIO_BASE__INST3_SEG0 = 0 # macro
DIO_BASE__INST3_SEG1 = 0 # macro
DIO_BASE__INST3_SEG2 = 0 # macro
DIO_BASE__INST3_SEG3 = 0 # macro
DIO_BASE__INST3_SEG4 = 0 # macro
DIO_BASE__INST4_SEG0 = 0 # macro
DIO_BASE__INST4_SEG1 = 0 # macro
DIO_BASE__INST4_SEG2 = 0 # macro
DIO_BASE__INST4_SEG3 = 0 # macro
DIO_BASE__INST4_SEG4 = 0 # macro
DIO_BASE__INST5_SEG0 = 0 # macro
DIO_BASE__INST5_SEG1 = 0 # macro
DIO_BASE__INST5_SEG2 = 0 # macro
DIO_BASE__INST5_SEG3 = 0 # macro
DIO_BASE__INST5_SEG4 = 0 # macro
DIO_BASE__INST6_SEG0 = 0 # macro
DIO_BASE__INST6_SEG1 = 0 # macro
DIO_BASE__INST6_SEG2 = 0 # macro
DIO_BASE__INST6_SEG3 = 0 # macro
DIO_BASE__INST6_SEG4 = 0 # macro
DCN_BASE__INST0_SEG0 = 0x00000012 # macro
DCN_BASE__INST0_SEG1 = 0x000000C0 # macro
DCN_BASE__INST0_SEG2 = 0x000034C0 # macro
DCN_BASE__INST0_SEG3 = 0x00009000 # macro
DCN_BASE__INST0_SEG4 = 0x02403C00 # macro
DCN_BASE__INST1_SEG0 = 0 # macro
DCN_BASE__INST1_SEG1 = 0 # macro
DCN_BASE__INST1_SEG2 = 0 # macro
DCN_BASE__INST1_SEG3 = 0 # macro
DCN_BASE__INST1_SEG4 = 0 # macro
DCN_BASE__INST2_SEG0 = 0 # macro
DCN_BASE__INST2_SEG1 = 0 # macro
DCN_BASE__INST2_SEG2 = 0 # macro
DCN_BASE__INST2_SEG3 = 0 # macro
DCN_BASE__INST2_SEG4 = 0 # macro
DCN_BASE__INST3_SEG0 = 0 # macro
DCN_BASE__INST3_SEG1 = 0 # macro
DCN_BASE__INST3_SEG2 = 0 # macro
DCN_BASE__INST3_SEG3 = 0 # macro
DCN_BASE__INST3_SEG4 = 0 # macro
DCN_BASE__INST4_SEG0 = 0 # macro
DCN_BASE__INST4_SEG1 = 0 # macro
DCN_BASE__INST4_SEG2 = 0 # macro
DCN_BASE__INST4_SEG3 = 0 # macro
DCN_BASE__INST4_SEG4 = 0 # macro
DCN_BASE__INST5_SEG0 = 0 # macro
DCN_BASE__INST5_SEG1 = 0 # macro
DCN_BASE__INST5_SEG2 = 0 # macro
DCN_BASE__INST5_SEG3 = 0 # macro
DCN_BASE__INST5_SEG4 = 0 # macro
DCN_BASE__INST6_SEG0 = 0 # macro
DCN_BASE__INST6_SEG1 = 0 # macro
DCN_BASE__INST6_SEG2 = 0 # macro
DCN_BASE__INST6_SEG3 = 0 # macro
DCN_BASE__INST6_SEG4 = 0 # macro
DPCS_BASE__INST0_SEG0 = 0x00000012 # macro
DPCS_BASE__INST0_SEG1 = 0x000000C0 # macro
DPCS_BASE__INST0_SEG2 = 0x000034C0 # macro
DPCS_BASE__INST0_SEG3 = 0x00009000 # macro
DPCS_BASE__INST0_SEG4 = 0x02403C00 # macro
DPCS_BASE__INST1_SEG0 = 0 # macro
DPCS_BASE__INST1_SEG1 = 0 # macro
DPCS_BASE__INST1_SEG2 = 0 # macro
DPCS_BASE__INST1_SEG3 = 0 # macro
DPCS_BASE__INST1_SEG4 = 0 # macro
DPCS_BASE__INST2_SEG0 = 0 # macro
DPCS_BASE__INST2_SEG1 = 0 # macro
DPCS_BASE__INST2_SEG2 = 0 # macro
DPCS_BASE__INST2_SEG3 = 0 # macro
DPCS_BASE__INST2_SEG4 = 0 # macro
DPCS_BASE__INST3_SEG0 = 0 # macro
DPCS_BASE__INST3_SEG1 = 0 # macro
DPCS_BASE__INST3_SEG2 = 0 # macro
DPCS_BASE__INST3_SEG3 = 0 # macro
DPCS_BASE__INST3_SEG4 = 0 # macro
DPCS_BASE__INST4_SEG0 = 0 # macro
DPCS_BASE__INST4_SEG1 = 0 # macro
DPCS_BASE__INST4_SEG2 = 0 # macro
DPCS_BASE__INST4_SEG3 = 0 # macro
DPCS_BASE__INST4_SEG4 = 0 # macro
DPCS_BASE__INST5_SEG0 = 0 # macro
DPCS_BASE__INST5_SEG1 = 0 # macro
DPCS_BASE__INST5_SEG2 = 0 # macro
DPCS_BASE__INST5_SEG3 = 0 # macro
DPCS_BASE__INST5_SEG4 = 0 # macro
DPCS_BASE__INST6_SEG0 = 0 # macro
DPCS_BASE__INST6_SEG1 = 0 # macro
DPCS_BASE__INST6_SEG2 = 0 # macro
DPCS_BASE__INST6_SEG3 = 0 # macro
DPCS_BASE__INST6_SEG4 = 0 # macro
FUSE_BASE__INST0_SEG0 = 0x00017400 # macro
FUSE_BASE__INST0_SEG1 = 0x02401400 # macro
FUSE_BASE__INST0_SEG2 = 0 # macro
FUSE_BASE__INST0_SEG3 = 0 # macro
FUSE_BASE__INST0_SEG4 = 0 # macro
FUSE_BASE__INST1_SEG0 = 0 # macro
FUSE_BASE__INST1_SEG1 = 0 # macro
FUSE_BASE__INST1_SEG2 = 0 # macro
FUSE_BASE__INST1_SEG3 = 0 # macro
FUSE_BASE__INST1_SEG4 = 0 # macro
FUSE_BASE__INST2_SEG0 = 0 # macro
FUSE_BASE__INST2_SEG1 = 0 # macro
FUSE_BASE__INST2_SEG2 = 0 # macro
FUSE_BASE__INST2_SEG3 = 0 # macro
FUSE_BASE__INST2_SEG4 = 0 # macro
FUSE_BASE__INST3_SEG0 = 0 # macro
FUSE_BASE__INST3_SEG1 = 0 # macro
FUSE_BASE__INST3_SEG2 = 0 # macro
FUSE_BASE__INST3_SEG3 = 0 # macro
FUSE_BASE__INST3_SEG4 = 0 # macro
FUSE_BASE__INST4_SEG0 = 0 # macro
FUSE_BASE__INST4_SEG1 = 0 # macro
FUSE_BASE__INST4_SEG2 = 0 # macro
FUSE_BASE__INST4_SEG3 = 0 # macro
FUSE_BASE__INST4_SEG4 = 0 # macro
FUSE_BASE__INST5_SEG0 = 0 # macro
FUSE_BASE__INST5_SEG1 = 0 # macro
FUSE_BASE__INST5_SEG2 = 0 # macro
FUSE_BASE__INST5_SEG3 = 0 # macro
FUSE_BASE__INST5_SEG4 = 0 # macro
FUSE_BASE__INST6_SEG0 = 0 # macro
FUSE_BASE__INST6_SEG1 = 0 # macro
FUSE_BASE__INST6_SEG2 = 0 # macro
FUSE_BASE__INST6_SEG3 = 0 # macro
FUSE_BASE__INST6_SEG4 = 0 # macro
GC_BASE__INST0_SEG0 = 0x00001260 # macro
GC_BASE__INST0_SEG1 = 0x0000A000 # macro
GC_BASE__INST0_SEG2 = 0x0001C000 # macro
GC_BASE__INST0_SEG3 = 0x02402C00 # macro
GC_BASE__INST0_SEG4 = 0 # macro
GC_BASE__INST1_SEG0 = 0 # macro
GC_BASE__INST1_SEG1 = 0 # macro
GC_BASE__INST1_SEG2 = 0 # macro
GC_BASE__INST1_SEG3 = 0 # macro
GC_BASE__INST1_SEG4 = 0 # macro
GC_BASE__INST2_SEG0 = 0 # macro
GC_BASE__INST2_SEG1 = 0 # macro
GC_BASE__INST2_SEG2 = 0 # macro
GC_BASE__INST2_SEG3 = 0 # macro
GC_BASE__INST2_SEG4 = 0 # macro
GC_BASE__INST3_SEG0 = 0 # macro
GC_BASE__INST3_SEG1 = 0 # macro
GC_BASE__INST3_SEG2 = 0 # macro
GC_BASE__INST3_SEG3 = 0 # macro
GC_BASE__INST3_SEG4 = 0 # macro
GC_BASE__INST4_SEG0 = 0 # macro
GC_BASE__INST4_SEG1 = 0 # macro
GC_BASE__INST4_SEG2 = 0 # macro
GC_BASE__INST4_SEG3 = 0 # macro
GC_BASE__INST4_SEG4 = 0 # macro
GC_BASE__INST5_SEG0 = 0 # macro
GC_BASE__INST5_SEG1 = 0 # macro
GC_BASE__INST5_SEG2 = 0 # macro
GC_BASE__INST5_SEG3 = 0 # macro
GC_BASE__INST5_SEG4 = 0 # macro
GC_BASE__INST6_SEG0 = 0 # macro
GC_BASE__INST6_SEG1 = 0 # macro
GC_BASE__INST6_SEG2 = 0 # macro
GC_BASE__INST6_SEG3 = 0 # macro
GC_BASE__INST6_SEG4 = 0 # macro
HDA_BASE__INST0_SEG0 = 0x004C0000 # macro
HDA_BASE__INST0_SEG1 = 0x02404800 # macro
HDA_BASE__INST0_SEG2 = 0 # macro
HDA_BASE__INST0_SEG3 = 0 # macro
HDA_BASE__INST0_SEG4 = 0 # macro
HDA_BASE__INST1_SEG0 = 0 # macro
HDA_BASE__INST1_SEG1 = 0 # macro
HDA_BASE__INST1_SEG2 = 0 # macro
HDA_BASE__INST1_SEG3 = 0 # macro
HDA_BASE__INST1_SEG4 = 0 # macro
HDA_BASE__INST2_SEG0 = 0 # macro
HDA_BASE__INST2_SEG1 = 0 # macro
HDA_BASE__INST2_SEG2 = 0 # macro
HDA_BASE__INST2_SEG3 = 0 # macro
HDA_BASE__INST2_SEG4 = 0 # macro
HDA_BASE__INST3_SEG0 = 0 # macro
HDA_BASE__INST3_SEG1 = 0 # macro
HDA_BASE__INST3_SEG2 = 0 # macro
HDA_BASE__INST3_SEG3 = 0 # macro
HDA_BASE__INST3_SEG4 = 0 # macro
HDA_BASE__INST4_SEG0 = 0 # macro
HDA_BASE__INST4_SEG1 = 0 # macro
HDA_BASE__INST4_SEG2 = 0 # macro
HDA_BASE__INST4_SEG3 = 0 # macro
HDA_BASE__INST4_SEG4 = 0 # macro
HDA_BASE__INST5_SEG0 = 0 # macro
HDA_BASE__INST5_SEG1 = 0 # macro
HDA_BASE__INST5_SEG2 = 0 # macro
HDA_BASE__INST5_SEG3 = 0 # macro
HDA_BASE__INST5_SEG4 = 0 # macro
HDA_BASE__INST6_SEG0 = 0 # macro
HDA_BASE__INST6_SEG1 = 0 # macro
HDA_BASE__INST6_SEG2 = 0 # macro
HDA_BASE__INST6_SEG3 = 0 # macro
HDA_BASE__INST6_SEG4 = 0 # macro
HDP_BASE__INST0_SEG0 = 0x00000F20 # macro
HDP_BASE__INST0_SEG1 = 0x0240A400 # macro
HDP_BASE__INST0_SEG2 = 0 # macro
HDP_BASE__INST0_SEG3 = 0 # macro
HDP_BASE__INST0_SEG4 = 0 # macro
HDP_BASE__INST1_SEG0 = 0 # macro
HDP_BASE__INST1_SEG1 = 0 # macro
HDP_BASE__INST1_SEG2 = 0 # macro
HDP_BASE__INST1_SEG3 = 0 # macro
HDP_BASE__INST1_SEG4 = 0 # macro
HDP_BASE__INST2_SEG0 = 0 # macro
HDP_BASE__INST2_SEG1 = 0 # macro
HDP_BASE__INST2_SEG2 = 0 # macro
HDP_BASE__INST2_SEG3 = 0 # macro
HDP_BASE__INST2_SEG4 = 0 # macro
HDP_BASE__INST3_SEG0 = 0 # macro
HDP_BASE__INST3_SEG1 = 0 # macro
HDP_BASE__INST3_SEG2 = 0 # macro
HDP_BASE__INST3_SEG3 = 0 # macro
HDP_BASE__INST3_SEG4 = 0 # macro
HDP_BASE__INST4_SEG0 = 0 # macro
HDP_BASE__INST4_SEG1 = 0 # macro
HDP_BASE__INST4_SEG2 = 0 # macro
HDP_BASE__INST4_SEG3 = 0 # macro
HDP_BASE__INST4_SEG4 = 0 # macro
HDP_BASE__INST5_SEG0 = 0 # macro
HDP_BASE__INST5_SEG1 = 0 # macro
HDP_BASE__INST5_SEG2 = 0 # macro
HDP_BASE__INST5_SEG3 = 0 # macro
HDP_BASE__INST5_SEG4 = 0 # macro
HDP_BASE__INST6_SEG0 = 0 # macro
HDP_BASE__INST6_SEG1 = 0 # macro
HDP_BASE__INST6_SEG2 = 0 # macro
HDP_BASE__INST6_SEG3 = 0 # macro
HDP_BASE__INST6_SEG4 = 0 # macro
MMHUB_BASE__INST0_SEG0 = 0x0001A000 # macro
MMHUB_BASE__INST0_SEG1 = 0x02408800 # macro
MMHUB_BASE__INST0_SEG2 = 0 # macro
MMHUB_BASE__INST0_SEG3 = 0 # macro
MMHUB_BASE__INST0_SEG4 = 0 # macro
MMHUB_BASE__INST1_SEG0 = 0 # macro
MMHUB_BASE__INST1_SEG1 = 0 # macro
MMHUB_BASE__INST1_SEG2 = 0 # macro
MMHUB_BASE__INST1_SEG3 = 0 # macro
MMHUB_BASE__INST1_SEG4 = 0 # macro
MMHUB_BASE__INST2_SEG0 = 0 # macro
MMHUB_BASE__INST2_SEG1 = 0 # macro
MMHUB_BASE__INST2_SEG2 = 0 # macro
MMHUB_BASE__INST2_SEG3 = 0 # macro
MMHUB_BASE__INST2_SEG4 = 0 # macro
MMHUB_BASE__INST3_SEG0 = 0 # macro
MMHUB_BASE__INST3_SEG1 = 0 # macro
MMHUB_BASE__INST3_SEG2 = 0 # macro
MMHUB_BASE__INST3_SEG3 = 0 # macro
MMHUB_BASE__INST3_SEG4 = 0 # macro
MMHUB_BASE__INST4_SEG0 = 0 # macro
MMHUB_BASE__INST4_SEG1 = 0 # macro
MMHUB_BASE__INST4_SEG2 = 0 # macro
MMHUB_BASE__INST4_SEG3 = 0 # macro
MMHUB_BASE__INST4_SEG4 = 0 # macro
MMHUB_BASE__INST5_SEG0 = 0 # macro
MMHUB_BASE__INST5_SEG1 = 0 # macro
MMHUB_BASE__INST5_SEG2 = 0 # macro
MMHUB_BASE__INST5_SEG3 = 0 # macro
MMHUB_BASE__INST5_SEG4 = 0 # macro
MMHUB_BASE__INST6_SEG0 = 0 # macro
MMHUB_BASE__INST6_SEG1 = 0 # macro
MMHUB_BASE__INST6_SEG2 = 0 # macro
MMHUB_BASE__INST6_SEG3 = 0 # macro
MMHUB_BASE__INST6_SEG4 = 0 # macro
MP0_BASE__INST0_SEG0 = 0x00016000 # macro
MP0_BASE__INST0_SEG1 = 0x00DC0000 # macro
MP0_BASE__INST0_SEG2 = 0x00E00000 # macro
MP0_BASE__INST0_SEG3 = 0x00E40000 # macro
MP0_BASE__INST0_SEG4 = 0x0243FC00 # macro
MP0_BASE__INST1_SEG0 = 0 # macro
MP0_BASE__INST1_SEG1 = 0 # macro
MP0_BASE__INST1_SEG2 = 0 # macro
MP0_BASE__INST1_SEG3 = 0 # macro
MP0_BASE__INST1_SEG4 = 0 # macro
MP0_BASE__INST2_SEG0 = 0 # macro
MP0_BASE__INST2_SEG1 = 0 # macro
MP0_BASE__INST2_SEG2 = 0 # macro
MP0_BASE__INST2_SEG3 = 0 # macro
MP0_BASE__INST2_SEG4 = 0 # macro
MP0_BASE__INST3_SEG0 = 0 # macro
MP0_BASE__INST3_SEG1 = 0 # macro
MP0_BASE__INST3_SEG2 = 0 # macro
MP0_BASE__INST3_SEG3 = 0 # macro
MP0_BASE__INST3_SEG4 = 0 # macro
MP0_BASE__INST4_SEG0 = 0 # macro
MP0_BASE__INST4_SEG1 = 0 # macro
MP0_BASE__INST4_SEG2 = 0 # macro
MP0_BASE__INST4_SEG3 = 0 # macro
MP0_BASE__INST4_SEG4 = 0 # macro
MP0_BASE__INST5_SEG0 = 0 # macro
MP0_BASE__INST5_SEG1 = 0 # macro
MP0_BASE__INST5_SEG2 = 0 # macro
MP0_BASE__INST5_SEG3 = 0 # macro
MP0_BASE__INST5_SEG4 = 0 # macro
MP0_BASE__INST6_SEG0 = 0 # macro
MP0_BASE__INST6_SEG1 = 0 # macro
MP0_BASE__INST6_SEG2 = 0 # macro
MP0_BASE__INST6_SEG3 = 0 # macro
MP0_BASE__INST6_SEG4 = 0 # macro
MP1_BASE__INST0_SEG0 = 0x00016000 # macro
MP1_BASE__INST0_SEG1 = 0x00DC0000 # macro
MP1_BASE__INST0_SEG2 = 0x00E00000 # macro
MP1_BASE__INST0_SEG3 = 0x00E40000 # macro
MP1_BASE__INST0_SEG4 = 0x0243FC00 # macro
MP1_BASE__INST1_SEG0 = 0 # macro
MP1_BASE__INST1_SEG1 = 0 # macro
MP1_BASE__INST1_SEG2 = 0 # macro
MP1_BASE__INST1_SEG3 = 0 # macro
MP1_BASE__INST1_SEG4 = 0 # macro
MP1_BASE__INST2_SEG0 = 0 # macro
MP1_BASE__INST2_SEG1 = 0 # macro
MP1_BASE__INST2_SEG2 = 0 # macro
MP1_BASE__INST2_SEG3 = 0 # macro
MP1_BASE__INST2_SEG4 = 0 # macro
MP1_BASE__INST3_SEG0 = 0 # macro
MP1_BASE__INST3_SEG1 = 0 # macro
MP1_BASE__INST3_SEG2 = 0 # macro
MP1_BASE__INST3_SEG3 = 0 # macro
MP1_BASE__INST3_SEG4 = 0 # macro
MP1_BASE__INST4_SEG0 = 0 # macro
MP1_BASE__INST4_SEG1 = 0 # macro
MP1_BASE__INST4_SEG2 = 0 # macro
MP1_BASE__INST4_SEG3 = 0 # macro
MP1_BASE__INST4_SEG4 = 0 # macro
MP1_BASE__INST5_SEG0 = 0 # macro
MP1_BASE__INST5_SEG1 = 0 # macro
MP1_BASE__INST5_SEG2 = 0 # macro
MP1_BASE__INST5_SEG3 = 0 # macro
MP1_BASE__INST5_SEG4 = 0 # macro
MP1_BASE__INST6_SEG0 = 0 # macro
MP1_BASE__INST6_SEG1 = 0 # macro
MP1_BASE__INST6_SEG2 = 0 # macro
MP1_BASE__INST6_SEG3 = 0 # macro
MP1_BASE__INST6_SEG4 = 0 # macro
NBIO_BASE__INST0_SEG0 = 0x00000000 # macro
NBIO_BASE__INST0_SEG1 = 0x00000014 # macro
NBIO_BASE__INST0_SEG2 = 0x00000D20 # macro
NBIO_BASE__INST0_SEG3 = 0x00010400 # macro
NBIO_BASE__INST0_SEG4 = 0x0241B000 # macro
NBIO_BASE__INST1_SEG0 = 0 # macro
NBIO_BASE__INST1_SEG1 = 0 # macro
NBIO_BASE__INST1_SEG2 = 0 # macro
NBIO_BASE__INST1_SEG3 = 0 # macro
NBIO_BASE__INST1_SEG4 = 0 # macro
NBIO_BASE__INST2_SEG0 = 0 # macro
NBIO_BASE__INST2_SEG1 = 0 # macro
NBIO_BASE__INST2_SEG2 = 0 # macro
NBIO_BASE__INST2_SEG3 = 0 # macro
NBIO_BASE__INST2_SEG4 = 0 # macro
NBIO_BASE__INST3_SEG0 = 0 # macro
NBIO_BASE__INST3_SEG1 = 0 # macro
NBIO_BASE__INST3_SEG2 = 0 # macro
NBIO_BASE__INST3_SEG3 = 0 # macro
NBIO_BASE__INST3_SEG4 = 0 # macro
NBIO_BASE__INST4_SEG0 = 0 # macro
NBIO_BASE__INST4_SEG1 = 0 # macro
NBIO_BASE__INST4_SEG2 = 0 # macro
NBIO_BASE__INST4_SEG3 = 0 # macro
NBIO_BASE__INST4_SEG4 = 0 # macro
NBIO_BASE__INST5_SEG0 = 0 # macro
NBIO_BASE__INST5_SEG1 = 0 # macro
NBIO_BASE__INST5_SEG2 = 0 # macro
NBIO_BASE__INST5_SEG3 = 0 # macro
NBIO_BASE__INST5_SEG4 = 0 # macro
NBIO_BASE__INST6_SEG0 = 0 # macro
NBIO_BASE__INST6_SEG1 = 0 # macro
NBIO_BASE__INST6_SEG2 = 0 # macro
NBIO_BASE__INST6_SEG3 = 0 # macro
NBIO_BASE__INST6_SEG4 = 0 # macro
OSSSYS_BASE__INST0_SEG0 = 0x000010A0 # macro
OSSSYS_BASE__INST0_SEG1 = 0x0240A000 # macro
OSSSYS_BASE__INST0_SEG2 = 0 # macro
OSSSYS_BASE__INST0_SEG3 = 0 # macro
OSSSYS_BASE__INST0_SEG4 = 0 # macro
OSSSYS_BASE__INST1_SEG0 = 0 # macro
OSSSYS_BASE__INST1_SEG1 = 0 # macro
OSSSYS_BASE__INST1_SEG2 = 0 # macro
OSSSYS_BASE__INST1_SEG3 = 0 # macro
OSSSYS_BASE__INST1_SEG4 = 0 # macro
OSSSYS_BASE__INST2_SEG0 = 0 # macro
OSSSYS_BASE__INST2_SEG1 = 0 # macro
OSSSYS_BASE__INST2_SEG2 = 0 # macro
OSSSYS_BASE__INST2_SEG3 = 0 # macro
OSSSYS_BASE__INST2_SEG4 = 0 # macro
OSSSYS_BASE__INST3_SEG0 = 0 # macro
OSSSYS_BASE__INST3_SEG1 = 0 # macro
OSSSYS_BASE__INST3_SEG2 = 0 # macro
OSSSYS_BASE__INST3_SEG3 = 0 # macro
OSSSYS_BASE__INST3_SEG4 = 0 # macro
OSSSYS_BASE__INST4_SEG0 = 0 # macro
OSSSYS_BASE__INST4_SEG1 = 0 # macro
OSSSYS_BASE__INST4_SEG2 = 0 # macro
OSSSYS_BASE__INST4_SEG3 = 0 # macro
OSSSYS_BASE__INST4_SEG4 = 0 # macro
OSSSYS_BASE__INST5_SEG0 = 0 # macro
OSSSYS_BASE__INST5_SEG1 = 0 # macro
OSSSYS_BASE__INST5_SEG2 = 0 # macro
OSSSYS_BASE__INST5_SEG3 = 0 # macro
OSSSYS_BASE__INST5_SEG4 = 0 # macro
OSSSYS_BASE__INST6_SEG0 = 0 # macro
OSSSYS_BASE__INST6_SEG1 = 0 # macro
OSSSYS_BASE__INST6_SEG2 = 0 # macro
OSSSYS_BASE__INST6_SEG3 = 0 # macro
OSSSYS_BASE__INST6_SEG4 = 0 # macro
PCIE0_BASE__INST0_SEG0 = 0x00000000 # macro
PCIE0_BASE__INST0_SEG1 = 0x00000014 # macro
PCIE0_BASE__INST0_SEG2 = 0x00000D20 # macro
PCIE0_BASE__INST0_SEG3 = 0x00010400 # macro
PCIE0_BASE__INST0_SEG4 = 0x0241B000 # macro
PCIE0_BASE__INST1_SEG0 = 0 # macro
PCIE0_BASE__INST1_SEG1 = 0 # macro
PCIE0_BASE__INST1_SEG2 = 0 # macro
PCIE0_BASE__INST1_SEG3 = 0 # macro
PCIE0_BASE__INST1_SEG4 = 0 # macro
PCIE0_BASE__INST2_SEG0 = 0 # macro
PCIE0_BASE__INST2_SEG1 = 0 # macro
PCIE0_BASE__INST2_SEG2 = 0 # macro
PCIE0_BASE__INST2_SEG3 = 0 # macro
PCIE0_BASE__INST2_SEG4 = 0 # macro
PCIE0_BASE__INST3_SEG0 = 0 # macro
PCIE0_BASE__INST3_SEG1 = 0 # macro
PCIE0_BASE__INST3_SEG2 = 0 # macro
PCIE0_BASE__INST3_SEG3 = 0 # macro
PCIE0_BASE__INST3_SEG4 = 0 # macro
PCIE0_BASE__INST4_SEG0 = 0 # macro
PCIE0_BASE__INST4_SEG1 = 0 # macro
PCIE0_BASE__INST4_SEG2 = 0 # macro
PCIE0_BASE__INST4_SEG3 = 0 # macro
PCIE0_BASE__INST4_SEG4 = 0 # macro
PCIE0_BASE__INST5_SEG0 = 0 # macro
PCIE0_BASE__INST5_SEG1 = 0 # macro
PCIE0_BASE__INST5_SEG2 = 0 # macro
PCIE0_BASE__INST5_SEG3 = 0 # macro
PCIE0_BASE__INST5_SEG4 = 0 # macro
PCIE0_BASE__INST6_SEG0 = 0 # macro
PCIE0_BASE__INST6_SEG1 = 0 # macro
PCIE0_BASE__INST6_SEG2 = 0 # macro
PCIE0_BASE__INST6_SEG3 = 0 # macro
PCIE0_BASE__INST6_SEG4 = 0 # macro
SDMA0_BASE__INST0_SEG0 = 0x00001260 # macro
SDMA0_BASE__INST0_SEG1 = 0x0000A000 # macro
SDMA0_BASE__INST0_SEG2 = 0x0001C000 # macro
SDMA0_BASE__INST0_SEG3 = 0x02402C00 # macro
SDMA0_BASE__INST0_SEG4 = 0 # macro
SDMA0_BASE__INST1_SEG0 = 0 # macro
SDMA0_BASE__INST1_SEG1 = 0 # macro
SDMA0_BASE__INST1_SEG2 = 0 # macro
SDMA0_BASE__INST1_SEG3 = 0 # macro
SDMA0_BASE__INST1_SEG4 = 0 # macro
SDMA0_BASE__INST2_SEG0 = 0 # macro
SDMA0_BASE__INST2_SEG1 = 0 # macro
SDMA0_BASE__INST2_SEG2 = 0 # macro
SDMA0_BASE__INST2_SEG3 = 0 # macro
SDMA0_BASE__INST2_SEG4 = 0 # macro
SDMA0_BASE__INST3_SEG0 = 0 # macro
SDMA0_BASE__INST3_SEG1 = 0 # macro
SDMA0_BASE__INST3_SEG2 = 0 # macro
SDMA0_BASE__INST3_SEG3 = 0 # macro
SDMA0_BASE__INST3_SEG4 = 0 # macro
SDMA0_BASE__INST4_SEG0 = 0 # macro
SDMA0_BASE__INST4_SEG1 = 0 # macro
SDMA0_BASE__INST4_SEG2 = 0 # macro
SDMA0_BASE__INST4_SEG3 = 0 # macro
SDMA0_BASE__INST4_SEG4 = 0 # macro
SDMA0_BASE__INST5_SEG0 = 0 # macro
SDMA0_BASE__INST5_SEG1 = 0 # macro
SDMA0_BASE__INST5_SEG2 = 0 # macro
SDMA0_BASE__INST5_SEG3 = 0 # macro
SDMA0_BASE__INST5_SEG4 = 0 # macro
SDMA0_BASE__INST6_SEG0 = 0 # macro
SDMA0_BASE__INST6_SEG1 = 0 # macro
SDMA0_BASE__INST6_SEG2 = 0 # macro
SDMA0_BASE__INST6_SEG3 = 0 # macro
SDMA0_BASE__INST6_SEG4 = 0 # macro
SDMA1_BASE__INST0_SEG0 = 0x00001260 # macro
SDMA1_BASE__INST0_SEG1 = 0x0000A000 # macro
SDMA1_BASE__INST0_SEG2 = 0x0001C000 # macro
SDMA1_BASE__INST0_SEG3 = 0x02402C00 # macro
SDMA1_BASE__INST0_SEG4 = 0 # macro
SDMA1_BASE__INST1_SEG0 = 0 # macro
SDMA1_BASE__INST1_SEG1 = 0 # macro
SDMA1_BASE__INST1_SEG2 = 0 # macro
SDMA1_BASE__INST1_SEG3 = 0 # macro
SDMA1_BASE__INST1_SEG4 = 0 # macro
SDMA1_BASE__INST2_SEG0 = 0 # macro
SDMA1_BASE__INST2_SEG1 = 0 # macro
SDMA1_BASE__INST2_SEG2 = 0 # macro
SDMA1_BASE__INST2_SEG3 = 0 # macro
SDMA1_BASE__INST2_SEG4 = 0 # macro
SDMA1_BASE__INST3_SEG0 = 0 # macro
SDMA1_BASE__INST3_SEG1 = 0 # macro
SDMA1_BASE__INST3_SEG2 = 0 # macro
SDMA1_BASE__INST3_SEG3 = 0 # macro
SDMA1_BASE__INST3_SEG4 = 0 # macro
SDMA1_BASE__INST4_SEG0 = 0 # macro
SDMA1_BASE__INST4_SEG1 = 0 # macro
SDMA1_BASE__INST4_SEG2 = 0 # macro
SDMA1_BASE__INST4_SEG3 = 0 # macro
SDMA1_BASE__INST4_SEG4 = 0 # macro
SDMA1_BASE__INST5_SEG0 = 0 # macro
SDMA1_BASE__INST5_SEG1 = 0 # macro
SDMA1_BASE__INST5_SEG2 = 0 # macro
SDMA1_BASE__INST5_SEG3 = 0 # macro
SDMA1_BASE__INST5_SEG4 = 0 # macro
SDMA1_BASE__INST6_SEG0 = 0 # macro
SDMA1_BASE__INST6_SEG1 = 0 # macro
SDMA1_BASE__INST6_SEG2 = 0 # macro
SDMA1_BASE__INST6_SEG3 = 0 # macro
SDMA1_BASE__INST6_SEG4 = 0 # macro
SMUIO_BASE__INST0_SEG0 = 0x00016800 # macro
SMUIO_BASE__INST0_SEG1 = 0x00016A00 # macro
SMUIO_BASE__INST0_SEG2 = 0x00440000 # macro
SMUIO_BASE__INST0_SEG3 = 0x02401000 # macro
SMUIO_BASE__INST0_SEG4 = 0 # macro
SMUIO_BASE__INST1_SEG0 = 0 # macro
SMUIO_BASE__INST1_SEG1 = 0 # macro
SMUIO_BASE__INST1_SEG2 = 0 # macro
SMUIO_BASE__INST1_SEG3 = 0 # macro
SMUIO_BASE__INST1_SEG4 = 0 # macro
SMUIO_BASE__INST2_SEG0 = 0 # macro
SMUIO_BASE__INST2_SEG1 = 0 # macro
SMUIO_BASE__INST2_SEG2 = 0 # macro
SMUIO_BASE__INST2_SEG3 = 0 # macro
SMUIO_BASE__INST2_SEG4 = 0 # macro
SMUIO_BASE__INST3_SEG0 = 0 # macro
SMUIO_BASE__INST3_SEG1 = 0 # macro
SMUIO_BASE__INST3_SEG2 = 0 # macro
SMUIO_BASE__INST3_SEG3 = 0 # macro
SMUIO_BASE__INST3_SEG4 = 0 # macro
SMUIO_BASE__INST4_SEG0 = 0 # macro
SMUIO_BASE__INST4_SEG1 = 0 # macro
SMUIO_BASE__INST4_SEG2 = 0 # macro
SMUIO_BASE__INST4_SEG3 = 0 # macro
SMUIO_BASE__INST4_SEG4 = 0 # macro
SMUIO_BASE__INST5_SEG0 = 0 # macro
SMUIO_BASE__INST5_SEG1 = 0 # macro
SMUIO_BASE__INST5_SEG2 = 0 # macro
SMUIO_BASE__INST5_SEG3 = 0 # macro
SMUIO_BASE__INST5_SEG4 = 0 # macro
SMUIO_BASE__INST6_SEG0 = 0 # macro
SMUIO_BASE__INST6_SEG1 = 0 # macro
SMUIO_BASE__INST6_SEG2 = 0 # macro
SMUIO_BASE__INST6_SEG3 = 0 # macro
SMUIO_BASE__INST6_SEG4 = 0 # macro
THM_BASE__INST0_SEG0 = 0x00016600 # macro
THM_BASE__INST0_SEG1 = 0x02400C00 # macro
THM_BASE__INST0_SEG2 = 0 # macro
THM_BASE__INST0_SEG3 = 0 # macro
THM_BASE__INST0_SEG4 = 0 # macro
THM_BASE__INST1_SEG0 = 0 # macro
THM_BASE__INST1_SEG1 = 0 # macro
THM_BASE__INST1_SEG2 = 0 # macro
THM_BASE__INST1_SEG3 = 0 # macro
THM_BASE__INST1_SEG4 = 0 # macro
THM_BASE__INST2_SEG0 = 0 # macro
THM_BASE__INST2_SEG1 = 0 # macro
THM_BASE__INST2_SEG2 = 0 # macro
THM_BASE__INST2_SEG3 = 0 # macro
THM_BASE__INST2_SEG4 = 0 # macro
THM_BASE__INST3_SEG0 = 0 # macro
THM_BASE__INST3_SEG1 = 0 # macro
THM_BASE__INST3_SEG2 = 0 # macro
THM_BASE__INST3_SEG3 = 0 # macro
THM_BASE__INST3_SEG4 = 0 # macro
THM_BASE__INST4_SEG0 = 0 # macro
THM_BASE__INST4_SEG1 = 0 # macro
THM_BASE__INST4_SEG2 = 0 # macro
THM_BASE__INST4_SEG3 = 0 # macro
THM_BASE__INST4_SEG4 = 0 # macro
THM_BASE__INST5_SEG0 = 0 # macro
THM_BASE__INST5_SEG1 = 0 # macro
THM_BASE__INST5_SEG2 = 0 # macro
THM_BASE__INST5_SEG3 = 0 # macro
THM_BASE__INST5_SEG4 = 0 # macro
THM_BASE__INST6_SEG0 = 0 # macro
THM_BASE__INST6_SEG1 = 0 # macro
THM_BASE__INST6_SEG2 = 0 # macro
THM_BASE__INST6_SEG3 = 0 # macro
THM_BASE__INST6_SEG4 = 0 # macro
UMC_BASE__INST0_SEG0 = 0x00014000 # macro
UMC_BASE__INST0_SEG1 = 0x02425800 # macro
UMC_BASE__INST0_SEG2 = 0 # macro
UMC_BASE__INST0_SEG3 = 0 # macro
UMC_BASE__INST0_SEG4 = 0 # macro
UMC_BASE__INST1_SEG0 = 0x00054000 # macro
UMC_BASE__INST1_SEG1 = 0x02425C00 # macro
UMC_BASE__INST1_SEG2 = 0 # macro
UMC_BASE__INST1_SEG3 = 0 # macro
UMC_BASE__INST1_SEG4 = 0 # macro
UMC_BASE__INST2_SEG0 = 0x00094000 # macro
UMC_BASE__INST2_SEG1 = 0x02426000 # macro
UMC_BASE__INST2_SEG2 = 0 # macro
UMC_BASE__INST2_SEG3 = 0 # macro
UMC_BASE__INST2_SEG4 = 0 # macro
UMC_BASE__INST3_SEG0 = 0x000D4000 # macro
UMC_BASE__INST3_SEG1 = 0x02426400 # macro
UMC_BASE__INST3_SEG2 = 0 # macro
UMC_BASE__INST3_SEG3 = 0 # macro
UMC_BASE__INST3_SEG4 = 0 # macro
UMC_BASE__INST4_SEG0 = 0x00114000 # macro
UMC_BASE__INST4_SEG1 = 0x02426800 # macro
UMC_BASE__INST4_SEG2 = 0 # macro
UMC_BASE__INST4_SEG3 = 0 # macro
UMC_BASE__INST4_SEG4 = 0 # macro
UMC_BASE__INST5_SEG0 = 0x00154000 # macro
UMC_BASE__INST5_SEG1 = 0x02426C00 # macro
UMC_BASE__INST5_SEG2 = 0 # macro
UMC_BASE__INST5_SEG3 = 0 # macro
UMC_BASE__INST5_SEG4 = 0 # macro
UMC_BASE__INST6_SEG0 = 0x00194000 # macro
UMC_BASE__INST6_SEG1 = 0x02427000 # macro
UMC_BASE__INST6_SEG2 = 0 # macro
UMC_BASE__INST6_SEG3 = 0 # macro
UMC_BASE__INST6_SEG4 = 0 # macro
USB0_BASE__INST0_SEG0 = 0x0242A800 # macro
USB0_BASE__INST0_SEG1 = 0x05B00000 # macro
USB0_BASE__INST0_SEG2 = 0 # macro
USB0_BASE__INST0_SEG3 = 0 # macro
USB0_BASE__INST0_SEG4 = 0 # macro
USB0_BASE__INST1_SEG0 = 0 # macro
USB0_BASE__INST1_SEG1 = 0 # macro
USB0_BASE__INST1_SEG2 = 0 # macro
USB0_BASE__INST1_SEG3 = 0 # macro
USB0_BASE__INST1_SEG4 = 0 # macro
USB0_BASE__INST2_SEG0 = 0 # macro
USB0_BASE__INST2_SEG1 = 0 # macro
USB0_BASE__INST2_SEG2 = 0 # macro
USB0_BASE__INST2_SEG3 = 0 # macro
USB0_BASE__INST2_SEG4 = 0 # macro
USB0_BASE__INST3_SEG0 = 0 # macro
USB0_BASE__INST3_SEG1 = 0 # macro
USB0_BASE__INST3_SEG2 = 0 # macro
USB0_BASE__INST3_SEG3 = 0 # macro
USB0_BASE__INST3_SEG4 = 0 # macro
USB0_BASE__INST4_SEG0 = 0 # macro
USB0_BASE__INST4_SEG1 = 0 # macro
USB0_BASE__INST4_SEG2 = 0 # macro
USB0_BASE__INST4_SEG3 = 0 # macro
USB0_BASE__INST4_SEG4 = 0 # macro
USB0_BASE__INST5_SEG0 = 0 # macro
USB0_BASE__INST5_SEG1 = 0 # macro
USB0_BASE__INST5_SEG2 = 0 # macro
USB0_BASE__INST5_SEG3 = 0 # macro
USB0_BASE__INST5_SEG4 = 0 # macro
USB0_BASE__INST6_SEG0 = 0 # macro
USB0_BASE__INST6_SEG1 = 0 # macro
USB0_BASE__INST6_SEG2 = 0 # macro
USB0_BASE__INST6_SEG3 = 0 # macro
USB0_BASE__INST6_SEG4 = 0 # macro
VCN_BASE__INST0_SEG0 = 0x00007800 # macro
VCN_BASE__INST0_SEG1 = 0x00007E00 # macro
VCN_BASE__INST0_SEG2 = 0x02403000 # macro
VCN_BASE__INST0_SEG3 = 0 # macro
VCN_BASE__INST0_SEG4 = 0 # macro
VCN_BASE__INST1_SEG0 = 0x00007B00 # macro
VCN_BASE__INST1_SEG1 = 0x00012000 # macro
VCN_BASE__INST1_SEG2 = 0x02445000 # macro
VCN_BASE__INST1_SEG3 = 0 # macro
VCN_BASE__INST1_SEG4 = 0 # macro
VCN_BASE__INST2_SEG0 = 0 # macro
VCN_BASE__INST2_SEG1 = 0 # macro
VCN_BASE__INST2_SEG2 = 0 # macro
VCN_BASE__INST2_SEG3 = 0 # macro
VCN_BASE__INST2_SEG4 = 0 # macro
VCN_BASE__INST3_SEG0 = 0 # macro
VCN_BASE__INST3_SEG1 = 0 # macro
VCN_BASE__INST3_SEG2 = 0 # macro
VCN_BASE__INST3_SEG3 = 0 # macro
VCN_BASE__INST3_SEG4 = 0 # macro
VCN_BASE__INST4_SEG0 = 0 # macro
VCN_BASE__INST4_SEG1 = 0 # macro
VCN_BASE__INST4_SEG2 = 0 # macro
VCN_BASE__INST4_SEG3 = 0 # macro
VCN_BASE__INST4_SEG4 = 0 # macro
VCN_BASE__INST5_SEG0 = 0 # macro
VCN_BASE__INST5_SEG1 = 0 # macro
VCN_BASE__INST5_SEG2 = 0 # macro
VCN_BASE__INST5_SEG3 = 0 # macro
VCN_BASE__INST5_SEG4 = 0 # macro
VCN_BASE__INST6_SEG0 = 0 # macro
VCN_BASE__INST6_SEG1 = 0 # macro
VCN_BASE__INST6_SEG2 = 0 # macro
VCN_BASE__INST6_SEG3 = 0 # macro
VCN_BASE__INST6_SEG4 = 0 # macro
class struct_IP_BASE_INSTANCE(Structure):
pass
struct_IP_BASE_INSTANCE._pack_ = 1 # source:False
struct_IP_BASE_INSTANCE._fields_ = [
('segment', ctypes.c_uint32 * 5),
]
class struct_IP_BASE(Structure):
_pack_ = 1 # source:False
_fields_ = [
('instance', struct_IP_BASE_INSTANCE * 7),
]
__maybe_unused = struct_IP_BASE # Variable struct_IP_BASE
ATHUB_BASE = struct_IP_BASE # Variable struct_IP_BASE
CLK_BASE = struct_IP_BASE # Variable struct_IP_BASE
DF_BASE = struct_IP_BASE # Variable struct_IP_BASE
DIO_BASE = struct_IP_BASE # Variable struct_IP_BASE
DCN_BASE = struct_IP_BASE # Variable struct_IP_BASE
DPCS_BASE = struct_IP_BASE # Variable struct_IP_BASE
FUSE_BASE = struct_IP_BASE # Variable struct_IP_BASE
GC_BASE = struct_IP_BASE # Variable struct_IP_BASE
HDA_BASE = struct_IP_BASE # Variable struct_IP_BASE
HDP_BASE = struct_IP_BASE # Variable struct_IP_BASE
MMHUB_BASE = struct_IP_BASE # Variable struct_IP_BASE
MP0_BASE = struct_IP_BASE # Variable struct_IP_BASE
MP1_BASE = struct_IP_BASE # Variable struct_IP_BASE
NBIO_BASE = struct_IP_BASE # Variable struct_IP_BASE
OSSSYS_BASE = struct_IP_BASE # Variable struct_IP_BASE
PCIE0_BASE = struct_IP_BASE # Variable struct_IP_BASE
SDMA0_BASE = struct_IP_BASE # Variable struct_IP_BASE
SDMA1_BASE = struct_IP_BASE # Variable struct_IP_BASE
SMUIO_BASE = struct_IP_BASE # Variable struct_IP_BASE
THM_BASE = struct_IP_BASE # Variable struct_IP_BASE
UMC_BASE = struct_IP_BASE # Variable struct_IP_BASE
USB0_BASE = struct_IP_BASE # Variable struct_IP_BASE
VCN_BASE = struct_IP_BASE # Variable struct_IP_BASE
__all__ = \
['ACCEPT_UNSOLICITED_RESPONSE_ENABLE',
'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ACP_TYPE_DVD_AUDIO',
'ACP_TYPE_GENERIC_AUDIO', 'ACP_TYPE_ICE60958_AUDIO',
'ACP_TYPE_SUPER_AUDIO_CD', 'ACrYCb16161616_10LSB',
'ACrYCb16161616_10MSB', 'ACrYCb16161616_12LSB',
'ACrYCb16161616_12MSB', 'ACrYCb2101010', 'ACrYCb8888',
'ADDR_GEN_ONE', 'ADDR_GEN_TWO', 'ADDR_GEN_ZERO', 'ADDR_RESERVED',
'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS',
'AFMT_ACP_SOURCE_FROM_AZALIA', 'AFMT_ACP_TYPE',
'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT',
'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG',
'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG',
'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG',
'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG',
'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL',
'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE',
'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10',
'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12',
'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14',
'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9',
'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT',
'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT',
'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS',
'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER',
'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD',
'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND',
'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS',
'AFMT_AUDIO_PACKET_SENT_DISABLED',
'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM0',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM1',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM2',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM3',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM4',
'AFMT_AUDIO_SRC_FROM_AZ_STREAM5',
'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS',
'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE',
'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS',
'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK',
'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE',
'AFMT_INTERRUPT_STATUS_CHG_MASK', 'AFMT_MEM_DISABLE_MEM_PWR_CTRL',
'AFMT_MEM_ENABLE_MEM_PWR_CTRL',
'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST',
'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST',
'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', 'AFMT_MEM_NO_FORCE_REQUEST',
'AFMT_MEM_PWR_DIS_CTRL', 'AFMT_MEM_PWR_FORCE_CTRL',
'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED',
'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED',
'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED',
'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE', 'ALLOW_SR_ON_TRANS_REQ',
'ALLOW_SR_ON_TRANS_REQ_DISABLE', 'ALLOW_SR_ON_TRANS_REQ_ENABLE',
'ALL_USE_R', 'ALPHA_DATA_ONTO_ALPHA_PORT',
'ALPHA_DATA_ONTO_CB_B_PORT', 'ALPHA_DATA_ONTO_CR_R_PORT',
'ALPHA_DATA_ONTO_Y_G_PORT',
'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK',
'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 'AMCLOCK_ENABLE',
'APG_ACP_OVERRIDE', 'APG_ACP_SOURCE_NO_OVERRIDE',
'APG_ACP_TYPE_DVD_AUDIO', 'APG_ACP_TYPE_GENERIC_AUDIO',
'APG_ACP_TYPE_ICE60958_AUDIO', 'APG_ACP_TYPE_SUPER_AUDIO_CD',
'APG_AUDIO_CRC_CH0_SIG', 'APG_AUDIO_CRC_CH1_SIG',
'APG_AUDIO_CRC_CH2_SIG', 'APG_AUDIO_CRC_CH3_SIG',
'APG_AUDIO_CRC_CH4_SIG', 'APG_AUDIO_CRC_CH5_SIG',
'APG_AUDIO_CRC_CH6_SIG', 'APG_AUDIO_CRC_CH7_SIG',
'APG_AUDIO_CRC_CONTINUOUS', 'APG_AUDIO_CRC_CONTROL_CH_SEL',
'APG_AUDIO_CRC_CONTROL_CONT', 'APG_AUDIO_CRC_ONESHOT',
'APG_AUDIO_CRC_RESERVED_10', 'APG_AUDIO_CRC_RESERVED_11',
'APG_AUDIO_CRC_RESERVED_12', 'APG_AUDIO_CRC_RESERVED_13',
'APG_AUDIO_CRC_RESERVED_14', 'APG_AUDIO_CRC_RESERVED_15',
'APG_AUDIO_CRC_RESERVED_8', 'APG_AUDIO_CRC_RESERVED_9',
'APG_DBG_ACP_TYPE', 'APG_DBG_AUDIO_DTO_BASE',
'APG_DBG_AUDIO_DTO_DIV', 'APG_DBG_AUDIO_DTO_MULTI',
'APG_DBG_MUX_SEL', 'APG_DEBUG_AUDIO_MODE',
'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ',
'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE',
'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED',
'APG_FUNCTIONAL_MODE', 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS',
'APG_INFOFRAME_SOURCE_NO_OVERRIDE',
'APG_MEM_DISABLE_MEM_PWR_CTRL', 'APG_MEM_ENABLE_MEM_PWR_CTRL',
'APG_MEM_FORCE_DEEP_SLEEP_REQUEST',
'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST',
'APG_MEM_FORCE_SHUT_DOWN_REQUEST', 'APG_MEM_NO_FORCE_REQUEST',
'APG_MEM_POWER_STATE', 'APG_MEM_POWER_STATE_DS',
'APG_MEM_POWER_STATE_LS', 'APG_MEM_POWER_STATE_ON',
'APG_MEM_POWER_STATE_SD', 'APG_MEM_PWR_DIS_CTRL',
'APG_MEM_PWR_FORCE_CTRL', 'APG_PACKET_CONTROL_ACP_SOURCE',
'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE', 'APG_RAMP_CONTROL_SIGN',
'APG_RAMP_SIGNED', 'APG_RAMP_UNSIGNED', 'ARGB1555',
'ARGB16161616_10LSB', 'ARGB16161616_10MSB', 'ARGB16161616_12LSB',
'ARGB16161616_12MSB', 'ARGB16161616_FLOAT', 'ARGB16161616_SNORM',
'ARGB16161616_UNORM', 'ARGB2101010', 'ARGB4444', 'ARGB8888',
'ATHUB_BASE', 'ATHUB_BASE__INST0_SEG0', 'ATHUB_BASE__INST0_SEG1',
'ATHUB_BASE__INST0_SEG2', 'ATHUB_BASE__INST0_SEG3',
'ATHUB_BASE__INST0_SEG4', 'ATHUB_BASE__INST1_SEG0',
'ATHUB_BASE__INST1_SEG1', 'ATHUB_BASE__INST1_SEG2',
'ATHUB_BASE__INST1_SEG3', 'ATHUB_BASE__INST1_SEG4',
'ATHUB_BASE__INST2_SEG0', 'ATHUB_BASE__INST2_SEG1',
'ATHUB_BASE__INST2_SEG2', 'ATHUB_BASE__INST2_SEG3',
'ATHUB_BASE__INST2_SEG4', 'ATHUB_BASE__INST3_SEG0',
'ATHUB_BASE__INST3_SEG1', 'ATHUB_BASE__INST3_SEG2',
'ATHUB_BASE__INST3_SEG3', 'ATHUB_BASE__INST3_SEG4',
'ATHUB_BASE__INST4_SEG0', 'ATHUB_BASE__INST4_SEG1',
'ATHUB_BASE__INST4_SEG2', 'ATHUB_BASE__INST4_SEG3',
'ATHUB_BASE__INST4_SEG4', 'ATHUB_BASE__INST5_SEG0',
'ATHUB_BASE__INST5_SEG1', 'ATHUB_BASE__INST5_SEG2',
'ATHUB_BASE__INST5_SEG3', 'ATHUB_BASE__INST5_SEG4',
'ATHUB_BASE__INST6_SEG0', 'ATHUB_BASE__INST6_SEG1',
'ATHUB_BASE__INST6_SEG2', 'ATHUB_BASE__INST6_SEG3',
'ATHUB_BASE__INST6_SEG4', 'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1',
'AUDIO_LAYOUT_SELECT', 'AUTOCAL_MODE_AUTOCENTER',
'AUTOCAL_MODE_AUTOREPLICATE', 'AUTOCAL_MODE_AUTOSCALE',
'AUTOCAL_MODE_OFF', 'AYCrCb16161616_10LSB',
'AYCrCb16161616_10MSB', 'AYCrCb16161616_12LSB',
'AYCrCb16161616_12MSB', 'AYCrCb8888',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED',
'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE',
'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE',
'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE',
'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY',
'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE',
'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED',
'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED',
'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE',
'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO',
'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET',
'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET',
'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED',
'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN',
'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8',
'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9',
'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN',
'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT',
'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE',
'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE',
'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED',
'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE',
'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED',
'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE',
'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN',
'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF',
'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET',
'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET',
'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC',
'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED',
'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED',
'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES',
'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED',
'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED',
'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET',
'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE',
'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES',
'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED',
'AZ_RIRB_WRITE_POINTER_DO_RESET',
'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET',
'AZ_STATE_CHANGE_STATUS',
'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT',
'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'BASE_RATE_44P1KHZ',
'BASE_RATE_48KHZ', 'BGR101111_FIX', 'BGR101111_FLOAT', 'BGR565',
'BIGK_FRAGMENT_SIZE', 'BINNER_BREAK_BATCH', 'BINNER_DROP',
'BINNER_PIPELINE', 'BINNER_PIPELINE_BREAK', 'BINNING_ALLOWED',
'BIN_CONF_OVERRIDE_CHECK', 'BIN_MAP_MODE_NONE',
'BIN_MAP_MODE_POPS', 'BIN_MAP_MODE_RTA_INDEX',
'BIN_SIZE_128_PIXELS', 'BIN_SIZE_256_PIXELS',
'BIN_SIZE_32_PIXELS', 'BIN_SIZE_512_PIXELS', 'BIN_SIZE_64_PIXELS',
'BITS_31_0', 'BITS_32_1', 'BITS_33_2', 'BITS_34_3', 'BITS_35_4',
'BITS_36_5', 'BITS_37_6', 'BITS_38_7', 'BLEND_CONSTANT_ALPHA',
'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR',
'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE',
'BLEND_ONE_MINUS_CONSTANT_ALPHA',
'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA',
'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA',
'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1',
'BLEND_OPT_PRESERVE_A1_IGNORE_A0',
'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE',
'BLEND_OPT_PRESERVE_C0_IGNORE_C1',
'BLEND_OPT_PRESERVE_C1_IGNORE_C0',
'BLEND_OPT_PRESERVE_NONE_IGNORE_A0',
'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL',
'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA',
'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE',
'BLEND_SRC_COLOR', 'BLEND_ZERO', 'BLOCK_CONTEXT_DONE', 'BLUE_LUT',
'BORROWBUFFER_MEM_POWER_STATE_ENUM',
'BORROWBUFFER_MEM_POWER_STATE_ENUM_DS',
'BORROWBUFFER_MEM_POWER_STATE_ENUM_LS',
'BORROWBUFFER_MEM_POWER_STATE_ENUM_ON',
'BORROWBUFFER_MEM_POWER_STATE_ENUM_SD', 'BOTTOM_OF_PIPE_TS',
'BREAK_BATCH', 'BYPASS', 'BYPASS_EN', 'BYPASS_GAMUT',
'BYPASS_POST_CSC', 'BinEventCntl', 'BinMapMode', 'BinSizeExtend',
'BinningMode', 'BlendOp', 'BlendOpt', 'CACHE_BYPASS',
'CACHE_FLUSH', 'CACHE_FLUSH_AND_INV_EVENT',
'CACHE_FLUSH_AND_INV_TS_EVENT', 'CACHE_FLUSH_AND_INV_TS_EVENT',
'CACHE_FLUSH_TS', 'CACHE_LRU_RD', 'CACHE_LRU_WR', 'CACHE_NOA',
'CACHE_NOA_WR', 'CACHE_STREAM', 'CACHE_STREAM_RD', 'CBMode',
'CBPerfClearFilterSel', 'CBPerfOpFilterSel', 'CBPerfSel',
'CBRamList', 'CB_B_DATA_ONTO_ALPHA_PORT',
'CB_B_DATA_ONTO_CB_B_PORT', 'CB_B_DATA_ONTO_CR_R_PORT',
'CB_B_DATA_ONTO_Y_G_PORT', 'CB_DCC_DECOMPRESS',
'CB_DCG_BACKEND_RDLAT_FIFO', 'CB_DCG_CCC_CAS_COLOR_PTR',
'CB_DCG_CCC_CAS_FRAG_PTR', 'CB_DCG_CCC_CAS_KEYID',
'CB_DCG_CCC_CAS_SURF_PARAM', 'CB_DCG_CCC_CAS_TAG_ARRAY',
'CB_DCG_COLOR_STORE', 'CB_DCG_COLOR_STORE_DIRTY_BYTE',
'CB_DCG_DCC_CACHE', 'CB_DCG_DCC_DIRTY_BITS',
'CB_DCG_FMASK_CACHE_STORE', 'CB_DCG_FRONTEND_RDLAT_FIFO',
'CB_DCG_OUTPUT_FIFO', 'CB_DCG_QBLOCK_ALLOC',
'CB_DCG_QUAD_PTR_FIFO', 'CB_DCG_READ_SKID_FIFO',
'CB_DCG_SRC_FIFO', 'CB_DISABLE', 'CB_ELIMINATE_FAST_CLEAR',
'CB_NORMAL', 'CB_PERF_CLEAR_FILTER_SEL_CLEAR',
'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR',
'CB_PERF_OP_FILTER_SEL_DECOMPRESS',
'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR',
'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS',
'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION',
'CB_PERF_OP_FILTER_SEL_RESOLVE',
'CB_PERF_OP_FILTER_SEL_WRITE_ONLY',
'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN',
'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN',
'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN',
'CB_PERF_SEL_BACKEND_READ_CLOCK_EN',
'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN',
'CB_PERF_SEL_BLEND_CLOCK_EN',
'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST',
'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED',
'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED',
'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED',
'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT',
'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY',
'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB',
'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY',
'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB',
'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY',
'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB',
'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY',
'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB',
'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL',
'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED',
'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL',
'CB_PERF_SEL_CC_CACHE_FLUSH',
'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL',
'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC',
'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL',
'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL',
'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL',
'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED',
'CB_PERF_SEL_CC_CACHE_SECTOR_HIT',
'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL',
'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED',
'CB_PERF_SEL_CC_CACHE_TAG_MISS',
'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION',
'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL',
'CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN',
'CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT',
'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN',
'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT',
'CB_PERF_SEL_CC_MC_READ_REQUEST',
'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_CC_MC_WRITE_REQUEST',
'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT',
'CB_PERF_SEL_CC_SURFACE_SYNC', 'CB_PERF_SEL_CC_TAG_HIT',
'CB_PERF_SEL_COLOR_STORE_CLOCK_EN',
'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY',
'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB',
'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY',
'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB',
'CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL',
'CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED',
'CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL',
'CB_PERF_SEL_DCC_CACHE_FLUSH',
'CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL',
'CB_PERF_SEL_DCC_CACHE_PERF_HIT',
'CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL',
'CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL',
'CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL',
'CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED',
'CB_PERF_SEL_DCC_CACHE_SECTOR_MISS',
'CB_PERF_SEL_DCC_CACHE_STALL',
'CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED',
'CB_PERF_SEL_DCC_CACHE_TAG_MISS',
'CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL',
'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD',
'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_DRAWN_TILE',
'CB_PERF_SEL_EVENT', 'CB_PERF_SEL_EVENT_CACHE_FLUSH',
'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT',
'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT',
'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS',
'CB_PERF_SEL_EVENT_CONTEXT_DONE',
'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS',
'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META',
'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT',
'CB_PERF_SEL_FILTER_DRAWN_PIXEL', 'CB_PERF_SEL_FILTER_DRAWN_QUAD',
'CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT',
'CB_PERF_SEL_FILTER_DRAWN_TILE',
'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN',
'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN',
'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN',
'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN',
'CB_PERF_SEL_GRBM_CLOCK_EN', 'CB_PERF_SEL_MEMARB_CLOCK_EN',
'CB_PERF_SEL_NACK_CC_READ', 'CB_PERF_SEL_NACK_CC_WRITE',
'CB_PERF_SEL_NONE', 'CB_PERF_SEL_PERFMON_CLOCK_EN',
'CB_PERF_SEL_RESERVED_118', 'CB_PERF_SEL_RESERVED_119',
'CB_PERF_SEL_RESERVED_120', 'CB_PERF_SEL_RESERVED_121',
'CB_PERF_SEL_RESERVED_122', 'CB_PERF_SEL_RESERVED_123',
'CB_PERF_SEL_RESERVED_124', 'CB_PERF_SEL_RESERVED_125',
'CB_PERF_SEL_RESERVED_126', 'CB_PERF_SEL_RESERVED_127',
'CB_PERF_SEL_RESERVED_128', 'CB_PERF_SEL_RESERVED_129',
'CB_PERF_SEL_RESERVED_130', 'CB_PERF_SEL_RESERVED_131',
'CB_PERF_SEL_RESERVED_132', 'CB_PERF_SEL_RESERVED_133',
'CB_PERF_SEL_RESERVED_134', 'CB_PERF_SEL_RESERVED_135',
'CB_PERF_SEL_RESERVED_136', 'CB_PERF_SEL_RESERVED_137',
'CB_PERF_SEL_RESERVED_138', 'CB_PERF_SEL_RESERVED_139',
'CB_PERF_SEL_RESERVED_140', 'CB_PERF_SEL_RESERVED_141',
'CB_PERF_SEL_RESERVED_142', 'CB_PERF_SEL_RESERVED_143',
'CB_PERF_SEL_RESERVED_144', 'CB_PERF_SEL_RESERVED_145',
'CB_PERF_SEL_RESERVED_146', 'CB_PERF_SEL_RESERVED_147',
'CB_PERF_SEL_RESERVED_148', 'CB_PERF_SEL_RESERVED_149',
'CB_PERF_SEL_RESERVED_165', 'CB_PERF_SEL_RESERVED_166',
'CB_PERF_SEL_RESERVED_167', 'CB_PERF_SEL_RESERVED_168',
'CB_PERF_SEL_RESERVED_169', 'CB_PERF_SEL_RESERVED_170',
'CB_PERF_SEL_RESERVED_171', 'CB_PERF_SEL_RESERVED_172',
'CB_PERF_SEL_RESERVED_173', 'CB_PERF_SEL_RESERVED_174',
'CB_PERF_SEL_RESERVED_175', 'CB_PERF_SEL_RESERVED_176',
'CB_PERF_SEL_RESERVED_177', 'CB_PERF_SEL_RESERVED_178',
'CB_PERF_SEL_RESERVED_179', 'CB_PERF_SEL_RESERVED_180',
'CB_PERF_SEL_RESERVED_181', 'CB_PERF_SEL_RESERVED_182',
'CB_PERF_SEL_RESERVED_183', 'CB_PERF_SEL_RESERVED_184',
'CB_PERF_SEL_RESERVED_185', 'CB_PERF_SEL_RESERVED_186',
'CB_PERF_SEL_RESERVED_187', 'CB_PERF_SEL_RESERVED_188',
'CB_PERF_SEL_RESERVED_189', 'CB_PERF_SEL_RESERVED_190',
'CB_PERF_SEL_RESERVED_191', 'CB_PERF_SEL_RESERVED_192',
'CB_PERF_SEL_RESERVED_193', 'CB_PERF_SEL_RESERVED_194',
'CB_PERF_SEL_RESERVED_195', 'CB_PERF_SEL_RESERVED_196',
'CB_PERF_SEL_RESERVED_197', 'CB_PERF_SEL_RESERVED_198',
'CB_PERF_SEL_RESERVED_199', 'CB_PERF_SEL_RESERVED_205',
'CB_PERF_SEL_RESERVED_206', 'CB_PERF_SEL_RESERVED_207',
'CB_PERF_SEL_RESERVED_208', 'CB_PERF_SEL_RESERVED_209',
'CB_PERF_SEL_RESERVED_21', 'CB_PERF_SEL_RESERVED_210',
'CB_PERF_SEL_RESERVED_211', 'CB_PERF_SEL_RESERVED_212',
'CB_PERF_SEL_RESERVED_213', 'CB_PERF_SEL_RESERVED_214',
'CB_PERF_SEL_RESERVED_215', 'CB_PERF_SEL_RESERVED_216',
'CB_PERF_SEL_RESERVED_217', 'CB_PERF_SEL_RESERVED_218',
'CB_PERF_SEL_RESERVED_219', 'CB_PERF_SEL_RESERVED_22',
'CB_PERF_SEL_RESERVED_220', 'CB_PERF_SEL_RESERVED_221',
'CB_PERF_SEL_RESERVED_222', 'CB_PERF_SEL_RESERVED_223',
'CB_PERF_SEL_RESERVED_224', 'CB_PERF_SEL_RESERVED_225',
'CB_PERF_SEL_RESERVED_226', 'CB_PERF_SEL_RESERVED_227',
'CB_PERF_SEL_RESERVED_228', 'CB_PERF_SEL_RESERVED_229',
'CB_PERF_SEL_RESERVED_23', 'CB_PERF_SEL_RESERVED_230',
'CB_PERF_SEL_RESERVED_231', 'CB_PERF_SEL_RESERVED_232',
'CB_PERF_SEL_RESERVED_233', 'CB_PERF_SEL_RESERVED_234',
'CB_PERF_SEL_RESERVED_235', 'CB_PERF_SEL_RESERVED_236',
'CB_PERF_SEL_RESERVED_237', 'CB_PERF_SEL_RESERVED_238',
'CB_PERF_SEL_RESERVED_239', 'CB_PERF_SEL_RESERVED_24',
'CB_PERF_SEL_RESERVED_240', 'CB_PERF_SEL_RESERVED_241',
'CB_PERF_SEL_RESERVED_242', 'CB_PERF_SEL_RESERVED_243',
'CB_PERF_SEL_RESERVED_244', 'CB_PERF_SEL_RESERVED_245',
'CB_PERF_SEL_RESERVED_246', 'CB_PERF_SEL_RESERVED_247',
'CB_PERF_SEL_RESERVED_248', 'CB_PERF_SEL_RESERVED_249',
'CB_PERF_SEL_RESERVED_25', 'CB_PERF_SEL_RESERVED_259',
'CB_PERF_SEL_RESERVED_26', 'CB_PERF_SEL_RESERVED_260',
'CB_PERF_SEL_RESERVED_261', 'CB_PERF_SEL_RESERVED_262',
'CB_PERF_SEL_RESERVED_263', 'CB_PERF_SEL_RESERVED_264',
'CB_PERF_SEL_RESERVED_265', 'CB_PERF_SEL_RESERVED_266',
'CB_PERF_SEL_RESERVED_267', 'CB_PERF_SEL_RESERVED_268',
'CB_PERF_SEL_RESERVED_269', 'CB_PERF_SEL_RESERVED_27',
'CB_PERF_SEL_RESERVED_270', 'CB_PERF_SEL_RESERVED_271',
'CB_PERF_SEL_RESERVED_272', 'CB_PERF_SEL_RESERVED_273',
'CB_PERF_SEL_RESERVED_274', 'CB_PERF_SEL_RESERVED_275',
'CB_PERF_SEL_RESERVED_276', 'CB_PERF_SEL_RESERVED_277',
'CB_PERF_SEL_RESERVED_278', 'CB_PERF_SEL_RESERVED_279',
'CB_PERF_SEL_RESERVED_28', 'CB_PERF_SEL_RESERVED_280',
'CB_PERF_SEL_RESERVED_281', 'CB_PERF_SEL_RESERVED_282',
'CB_PERF_SEL_RESERVED_283', 'CB_PERF_SEL_RESERVED_284',
'CB_PERF_SEL_RESERVED_285', 'CB_PERF_SEL_RESERVED_286',
'CB_PERF_SEL_RESERVED_287', 'CB_PERF_SEL_RESERVED_288',
'CB_PERF_SEL_RESERVED_289', 'CB_PERF_SEL_RESERVED_29',
'CB_PERF_SEL_RESERVED_290', 'CB_PERF_SEL_RESERVED_291',
'CB_PERF_SEL_RESERVED_292', 'CB_PERF_SEL_RESERVED_293',
'CB_PERF_SEL_RESERVED_294', 'CB_PERF_SEL_RESERVED_295',
'CB_PERF_SEL_RESERVED_296', 'CB_PERF_SEL_RESERVED_297',
'CB_PERF_SEL_RESERVED_298', 'CB_PERF_SEL_RESERVED_299',
'CB_PERF_SEL_RESERVED_303', 'CB_PERF_SEL_RESERVED_304',
'CB_PERF_SEL_RESERVED_305', 'CB_PERF_SEL_RESERVED_306',
'CB_PERF_SEL_RESERVED_307', 'CB_PERF_SEL_RESERVED_308',
'CB_PERF_SEL_RESERVED_309', 'CB_PERF_SEL_RESERVED_310',
'CB_PERF_SEL_RESERVED_311', 'CB_PERF_SEL_RESERVED_312',
'CB_PERF_SEL_RESERVED_313', 'CB_PERF_SEL_RESERVED_314',
'CB_PERF_SEL_RESERVED_315', 'CB_PERF_SEL_RESERVED_316',
'CB_PERF_SEL_RESERVED_317', 'CB_PERF_SEL_RESERVED_318',
'CB_PERF_SEL_RESERVED_319', 'CB_PERF_SEL_RESERVED_320',
'CB_PERF_SEL_RESERVED_321', 'CB_PERF_SEL_RESERVED_322',
'CB_PERF_SEL_RESERVED_323', 'CB_PERF_SEL_RESERVED_324',
'CB_PERF_SEL_RESERVED_325', 'CB_PERF_SEL_RESERVED_326',
'CB_PERF_SEL_RESERVED_327', 'CB_PERF_SEL_RESERVED_328',
'CB_PERF_SEL_RESERVED_329', 'CB_PERF_SEL_RESERVED_330',
'CB_PERF_SEL_RESERVED_331', 'CB_PERF_SEL_RESERVED_332',
'CB_PERF_SEL_RESERVED_333', 'CB_PERF_SEL_RESERVED_334',
'CB_PERF_SEL_RESERVED_335', 'CB_PERF_SEL_RESERVED_336',
'CB_PERF_SEL_RESERVED_337', 'CB_PERF_SEL_RESERVED_338',
'CB_PERF_SEL_RESERVED_339', 'CB_PERF_SEL_RESERVED_340',
'CB_PERF_SEL_RESERVED_341', 'CB_PERF_SEL_RESERVED_342',
'CB_PERF_SEL_RESERVED_343', 'CB_PERF_SEL_RESERVED_344',
'CB_PERF_SEL_RESERVED_345', 'CB_PERF_SEL_RESERVED_346',
'CB_PERF_SEL_RESERVED_347', 'CB_PERF_SEL_RESERVED_348',
'CB_PERF_SEL_RESERVED_349', 'CB_PERF_SEL_RESERVED_350',
'CB_PERF_SEL_RESERVED_351', 'CB_PERF_SEL_RESERVED_352',
'CB_PERF_SEL_RESERVED_353', 'CB_PERF_SEL_RESERVED_354',
'CB_PERF_SEL_RESERVED_355', 'CB_PERF_SEL_RESERVED_356',
'CB_PERF_SEL_RESERVED_357', 'CB_PERF_SEL_RESERVED_358',
'CB_PERF_SEL_RESERVED_359', 'CB_PERF_SEL_RESERVED_360',
'CB_PERF_SEL_RESERVED_361', 'CB_PERF_SEL_RESERVED_362',
'CB_PERF_SEL_RESERVED_363', 'CB_PERF_SEL_RESERVED_364',
'CB_PERF_SEL_RESERVED_365', 'CB_PERF_SEL_RESERVED_366',
'CB_PERF_SEL_RESERVED_367', 'CB_PERF_SEL_RESERVED_368',
'CB_PERF_SEL_RESERVED_369', 'CB_PERF_SEL_RESERVED_370',
'CB_PERF_SEL_RESERVED_371', 'CB_PERF_SEL_RESERVED_372',
'CB_PERF_SEL_RESERVED_373', 'CB_PERF_SEL_RESERVED_374',
'CB_PERF_SEL_RESERVED_375', 'CB_PERF_SEL_RESERVED_376',
'CB_PERF_SEL_RESERVED_377', 'CB_PERF_SEL_RESERVED_378',
'CB_PERF_SEL_RESERVED_379', 'CB_PERF_SEL_RESERVED_38',
'CB_PERF_SEL_RESERVED_380', 'CB_PERF_SEL_RESERVED_381',
'CB_PERF_SEL_RESERVED_382', 'CB_PERF_SEL_RESERVED_383',
'CB_PERF_SEL_RESERVED_384', 'CB_PERF_SEL_RESERVED_385',
'CB_PERF_SEL_RESERVED_386', 'CB_PERF_SEL_RESERVED_387',
'CB_PERF_SEL_RESERVED_388', 'CB_PERF_SEL_RESERVED_389',
'CB_PERF_SEL_RESERVED_39', 'CB_PERF_SEL_RESERVED_390',
'CB_PERF_SEL_RESERVED_391', 'CB_PERF_SEL_RESERVED_392',
'CB_PERF_SEL_RESERVED_393', 'CB_PERF_SEL_RESERVED_394',
'CB_PERF_SEL_RESERVED_395', 'CB_PERF_SEL_RESERVED_396',
'CB_PERF_SEL_RESERVED_397', 'CB_PERF_SEL_RESERVED_398',
'CB_PERF_SEL_RESERVED_399', 'CB_PERF_SEL_RESERVED_40',
'CB_PERF_SEL_RESERVED_400', 'CB_PERF_SEL_RESERVED_401',
'CB_PERF_SEL_RESERVED_402', 'CB_PERF_SEL_RESERVED_403',
'CB_PERF_SEL_RESERVED_404', 'CB_PERF_SEL_RESERVED_405',
'CB_PERF_SEL_RESERVED_406', 'CB_PERF_SEL_RESERVED_407',
'CB_PERF_SEL_RESERVED_408', 'CB_PERF_SEL_RESERVED_409',
'CB_PERF_SEL_RESERVED_41', 'CB_PERF_SEL_RESERVED_410',
'CB_PERF_SEL_RESERVED_411', 'CB_PERF_SEL_RESERVED_412',
'CB_PERF_SEL_RESERVED_413', 'CB_PERF_SEL_RESERVED_414',
'CB_PERF_SEL_RESERVED_415', 'CB_PERF_SEL_RESERVED_416',
'CB_PERF_SEL_RESERVED_417', 'CB_PERF_SEL_RESERVED_418',
'CB_PERF_SEL_RESERVED_419', 'CB_PERF_SEL_RESERVED_42',
'CB_PERF_SEL_RESERVED_420', 'CB_PERF_SEL_RESERVED_421',
'CB_PERF_SEL_RESERVED_422', 'CB_PERF_SEL_RESERVED_423',
'CB_PERF_SEL_RESERVED_424', 'CB_PERF_SEL_RESERVED_425',
'CB_PERF_SEL_RESERVED_426', 'CB_PERF_SEL_RESERVED_427',
'CB_PERF_SEL_RESERVED_428', 'CB_PERF_SEL_RESERVED_429',
'CB_PERF_SEL_RESERVED_43', 'CB_PERF_SEL_RESERVED_430',
'CB_PERF_SEL_RESERVED_431', 'CB_PERF_SEL_RESERVED_432',
'CB_PERF_SEL_RESERVED_433', 'CB_PERF_SEL_RESERVED_434',
'CB_PERF_SEL_RESERVED_435', 'CB_PERF_SEL_RESERVED_436',
'CB_PERF_SEL_RESERVED_437', 'CB_PERF_SEL_RESERVED_438',
'CB_PERF_SEL_RESERVED_439', 'CB_PERF_SEL_RESERVED_44',
'CB_PERF_SEL_RESERVED_440', 'CB_PERF_SEL_RESERVED_441',
'CB_PERF_SEL_RESERVED_442', 'CB_PERF_SEL_RESERVED_443',
'CB_PERF_SEL_RESERVED_444', 'CB_PERF_SEL_RESERVED_445',
'CB_PERF_SEL_RESERVED_446', 'CB_PERF_SEL_RESERVED_447',
'CB_PERF_SEL_RESERVED_448', 'CB_PERF_SEL_RESERVED_449',
'CB_PERF_SEL_RESERVED_45', 'CB_PERF_SEL_RESERVED_450',
'CB_PERF_SEL_RESERVED_451', 'CB_PERF_SEL_RESERVED_452',
'CB_PERF_SEL_RESERVED_453', 'CB_PERF_SEL_RESERVED_454',
'CB_PERF_SEL_RESERVED_455', 'CB_PERF_SEL_RESERVED_456',
'CB_PERF_SEL_RESERVED_457', 'CB_PERF_SEL_RESERVED_458',
'CB_PERF_SEL_RESERVED_459', 'CB_PERF_SEL_RESERVED_46',
'CB_PERF_SEL_RESERVED_460', 'CB_PERF_SEL_RESERVED_461',
'CB_PERF_SEL_RESERVED_462', 'CB_PERF_SEL_RESERVED_463',
'CB_PERF_SEL_RESERVED_464', 'CB_PERF_SEL_RESERVED_465',
'CB_PERF_SEL_RESERVED_47', 'CB_PERF_SEL_RESERVED_48',
'CB_PERF_SEL_RESERVED_49', 'CB_PERF_SEL_RESERVED_65',
'CB_PERF_SEL_RESERVED_66', 'CB_PERF_SEL_RESERVED_67',
'CB_PERF_SEL_RESERVED_68', 'CB_PERF_SEL_RESERVED_69',
'CB_PERF_SEL_RESERVED_70', 'CB_PERF_SEL_RESERVED_71',
'CB_PERF_SEL_RESERVED_72', 'CB_PERF_SEL_RESERVED_73',
'CB_PERF_SEL_RESERVED_74', 'CB_PERF_SEL_RESERVED_75',
'CB_PERF_SEL_RESERVED_76', 'CB_PERF_SEL_RESERVED_77',
'CB_PERF_SEL_RESERVED_78', 'CB_PERF_SEL_RESERVED_79',
'CB_PERF_SEL_RESERVED_80', 'CB_PERF_SEL_RESERVED_81',
'CB_PERF_SEL_RESERVED_82', 'CB_PERF_SEL_RESERVED_83',
'CB_PERF_SEL_RESERVED_84', 'CB_PERF_SEL_RESERVED_85',
'CB_PERF_SEL_RESERVED_86', 'CB_PERF_SEL_RESERVED_87',
'CB_PERF_SEL_RESERVED_88', 'CB_PERF_SEL_RESERVED_89',
'CB_PERF_SEL_RESERVED_90', 'CB_PERF_SEL_RESERVED_91',
'CB_PERF_SEL_RESERVED_92', 'CB_PERF_SEL_RESERVED_93',
'CB_PERF_SEL_RESERVED_94', 'CB_PERF_SEL_RESERVED_95',
'CB_PERF_SEL_RESERVED_96', 'CB_PERF_SEL_RESERVED_97',
'CB_PERF_SEL_RESERVED_98', 'CB_PERF_SEL_RESERVED_99',
'CB_PERF_SEL_STATIC_CLOCK_EN', 'CB_RESERVED',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6',
'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6',
'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL',
'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY',
'CE_PARTITION_BASE', 'CHA_PERF_SEL', 'CHA_PERF_SEL_ARB_REQUESTS',
'CHA_PERF_SEL_BUSY', 'CHA_PERF_SEL_CYCLE',
'CHA_PERF_SEL_IO_32B_WDS_CHC0', 'CHA_PERF_SEL_IO_32B_WDS_CHC1',
'CHA_PERF_SEL_IO_32B_WDS_CHC2', 'CHA_PERF_SEL_IO_32B_WDS_CHC3',
'CHA_PERF_SEL_IO_32B_WDS_CHC4',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC0',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC1',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC2',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC3',
'CHA_PERF_SEL_IO_BURST_COUNT_CHC4',
'CHA_PERF_SEL_MEM_32B_WDS_CHC0', 'CHA_PERF_SEL_MEM_32B_WDS_CHC1',
'CHA_PERF_SEL_MEM_32B_WDS_CHC2', 'CHA_PERF_SEL_MEM_32B_WDS_CHC3',
'CHA_PERF_SEL_MEM_32B_WDS_CHC4',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3',
'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', 'CHA_PERF_SEL_REQUEST_CHC0',
'CHA_PERF_SEL_REQUEST_CHC1', 'CHA_PERF_SEL_REQUEST_CHC2',
'CHA_PERF_SEL_REQUEST_CHC3', 'CHA_PERF_SEL_REQUEST_CHC4',
'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', 'CHA_PERF_SEL_STALL_CHC0',
'CHA_PERF_SEL_STALL_CHC1', 'CHA_PERF_SEL_STALL_CHC2',
'CHA_PERF_SEL_STALL_CHC3', 'CHA_PERF_SEL_STALL_CHC4',
'CHA_PERF_SEL_STALL_CHC5', 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0',
'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1',
'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2',
'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3',
'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', 'CHCG_PERF_SEL',
'CHCG_PERF_SEL_ARB_RET_LEVEL', 'CHCG_PERF_SEL_BUSY',
'CHCG_PERF_SEL_CYCLE', 'CHCG_PERF_SEL_GL2_REQ_READ_LATENCY',
'CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHCG_PERF_SEL_REQ',
'CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET',
'CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHCG_PERF_SEL_REQ_CLIENT0',
'CHCG_PERF_SEL_REQ_CLIENT1', 'CHCG_PERF_SEL_REQ_CLIENT10',
'CHCG_PERF_SEL_REQ_CLIENT11', 'CHCG_PERF_SEL_REQ_CLIENT12',
'CHCG_PERF_SEL_REQ_CLIENT13', 'CHCG_PERF_SEL_REQ_CLIENT14',
'CHCG_PERF_SEL_REQ_CLIENT15', 'CHCG_PERF_SEL_REQ_CLIENT16',
'CHCG_PERF_SEL_REQ_CLIENT17', 'CHCG_PERF_SEL_REQ_CLIENT18',
'CHCG_PERF_SEL_REQ_CLIENT19', 'CHCG_PERF_SEL_REQ_CLIENT2',
'CHCG_PERF_SEL_REQ_CLIENT20', 'CHCG_PERF_SEL_REQ_CLIENT21',
'CHCG_PERF_SEL_REQ_CLIENT22', 'CHCG_PERF_SEL_REQ_CLIENT23',
'CHCG_PERF_SEL_REQ_CLIENT3', 'CHCG_PERF_SEL_REQ_CLIENT4',
'CHCG_PERF_SEL_REQ_CLIENT5', 'CHCG_PERF_SEL_REQ_CLIENT6',
'CHCG_PERF_SEL_REQ_CLIENT7', 'CHCG_PERF_SEL_REQ_CLIENT8',
'CHCG_PERF_SEL_REQ_CLIENT9', 'CHCG_PERF_SEL_REQ_NOP_ACK',
'CHCG_PERF_SEL_REQ_NOP_RTN0', 'CHCG_PERF_SEL_REQ_READ',
'CHCG_PERF_SEL_REQ_READ_128B', 'CHCG_PERF_SEL_REQ_READ_32B',
'CHCG_PERF_SEL_REQ_READ_64B', 'CHCG_PERF_SEL_REQ_WRITE',
'CHCG_PERF_SEL_REQ_WRITE_32B', 'CHCG_PERF_SEL_REQ_WRITE_64B',
'CHCG_PERF_SEL_STALL_BUFFER_FULL', 'CHCG_PERF_SEL_STALL_GUS_GL1',
'CHCG_PERF_SEL_STARVE', 'CHC_PERF_SEL',
'CHC_PERF_SEL_ARB_RET_LEVEL', 'CHC_PERF_SEL_BUSY',
'CHC_PERF_SEL_CYCLE', 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY',
'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHC_PERF_SEL_REQ',
'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET',
'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHC_PERF_SEL_REQ_CLIENT0',
'CHC_PERF_SEL_REQ_CLIENT1', 'CHC_PERF_SEL_REQ_CLIENT10',
'CHC_PERF_SEL_REQ_CLIENT11', 'CHC_PERF_SEL_REQ_CLIENT12',
'CHC_PERF_SEL_REQ_CLIENT13', 'CHC_PERF_SEL_REQ_CLIENT14',
'CHC_PERF_SEL_REQ_CLIENT15', 'CHC_PERF_SEL_REQ_CLIENT16',
'CHC_PERF_SEL_REQ_CLIENT17', 'CHC_PERF_SEL_REQ_CLIENT18',
'CHC_PERF_SEL_REQ_CLIENT19', 'CHC_PERF_SEL_REQ_CLIENT2',
'CHC_PERF_SEL_REQ_CLIENT20', 'CHC_PERF_SEL_REQ_CLIENT21',
'CHC_PERF_SEL_REQ_CLIENT22', 'CHC_PERF_SEL_REQ_CLIENT23',
'CHC_PERF_SEL_REQ_CLIENT3', 'CHC_PERF_SEL_REQ_CLIENT4',
'CHC_PERF_SEL_REQ_CLIENT5', 'CHC_PERF_SEL_REQ_CLIENT6',
'CHC_PERF_SEL_REQ_CLIENT7', 'CHC_PERF_SEL_REQ_CLIENT8',
'CHC_PERF_SEL_REQ_CLIENT9', 'CHC_PERF_SEL_REQ_NOP_ACK',
'CHC_PERF_SEL_REQ_NOP_RTN0', 'CHC_PERF_SEL_REQ_READ',
'CHC_PERF_SEL_REQ_READ_128B', 'CHC_PERF_SEL_REQ_READ_32B',
'CHC_PERF_SEL_REQ_READ_64B', 'CHC_PERF_SEL_REQ_WRITE',
'CHC_PERF_SEL_REQ_WRITE_32B', 'CHC_PERF_SEL_REQ_WRITE_64B',
'CHC_PERF_SEL_STALL_BUFFER_FULL', 'CHC_PERF_SEL_STALL_GL2_GL1',
'CHC_PERF_SEL_STARVE', 'CHUNK_SIZE', 'CHUNK_SIZE_16KB',
'CHUNK_SIZE_1KB', 'CHUNK_SIZE_2KB', 'CHUNK_SIZE_32KB',
'CHUNK_SIZE_4KB', 'CHUNK_SIZE_64KB', 'CHUNK_SIZE_8KB',
'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', 'CLKGATE_SM_MODE',
'CLK_BASE', 'CLK_BASE__INST0_SEG0', 'CLK_BASE__INST0_SEG1',
'CLK_BASE__INST0_SEG2', 'CLK_BASE__INST0_SEG3',
'CLK_BASE__INST0_SEG4', 'CLK_BASE__INST1_SEG0',
'CLK_BASE__INST1_SEG1', 'CLK_BASE__INST1_SEG2',
'CLK_BASE__INST1_SEG3', 'CLK_BASE__INST1_SEG4',
'CLK_BASE__INST2_SEG0', 'CLK_BASE__INST2_SEG1',
'CLK_BASE__INST2_SEG2', 'CLK_BASE__INST2_SEG3',
'CLK_BASE__INST2_SEG4', 'CLK_BASE__INST3_SEG0',
'CLK_BASE__INST3_SEG1', 'CLK_BASE__INST3_SEG2',
'CLK_BASE__INST3_SEG3', 'CLK_BASE__INST3_SEG4',
'CLK_BASE__INST4_SEG0', 'CLK_BASE__INST4_SEG1',
'CLK_BASE__INST4_SEG2', 'CLK_BASE__INST4_SEG3',
'CLK_BASE__INST4_SEG4', 'CLK_BASE__INST5_SEG0',
'CLK_BASE__INST5_SEG1', 'CLK_BASE__INST5_SEG2',
'CLK_BASE__INST5_SEG3', 'CLK_BASE__INST5_SEG4',
'CLK_BASE__INST6_SEG0', 'CLK_BASE__INST6_SEG1',
'CLK_BASE__INST6_SEG2', 'CLK_BASE__INST6_SEG3',
'CLK_BASE__INST6_SEG4', 'CLOCK_BRANCH_SOFT_RESET',
'CLOCK_BRANCH_SOFT_RESET_FORCE', 'CLOCK_BRANCH_SOFT_RESET_NOOP',
'CLOCK_GATING_DISABLE', 'CLOCK_GATING_DISABLED',
'CLOCK_GATING_DISABLED_IN_DCO', 'CLOCK_GATING_DISABLE_ENUM',
'CLOCK_GATING_DISABLE_ENUM_DISABLED',
'CLOCK_GATING_DISABLE_ENUM_ENABLED', 'CLOCK_GATING_EN',
'CLOCK_GATING_ENABLE', 'CLOCK_GATING_ENABLED',
'CLOCK_GATING_ENABLED_IN_DCO', 'CMASK_CLR00_F0', 'CMASK_CLR00_F1',
'CMASK_CLR00_F2', 'CMASK_CLR00_FX', 'CMASK_CLR01_F0',
'CMASK_CLR01_F1', 'CMASK_CLR01_F2', 'CMASK_CLR01_FX',
'CMASK_CLR10_F0', 'CMASK_CLR10_F1', 'CMASK_CLR10_F2',
'CMASK_CLR10_FX', 'CMASK_CLR11_F0', 'CMASK_CLR11_F1',
'CMASK_CLR11_F2', 'CMASK_CLR11_FX', 'CMC_3DLUT_17CUBE',
'CMC_3DLUT_30BIT', 'CMC_3DLUT_30BIT_ENUM', 'CMC_3DLUT_36BIT',
'CMC_3DLUT_9CUBE', 'CMC_3DLUT_RAM_SEL', 'CMC_3DLUT_SIZE_ENUM',
'CMC_LUT_2CFG_MEMORY_A', 'CMC_LUT_2CFG_MEMORY_B',
'CMC_LUT_2CFG_NO_MEMORY', 'CMC_LUT_2_CONFIG_ENUM',
'CMC_LUT_2_MODE_BYPASS', 'CMC_LUT_2_MODE_ENUM',
'CMC_LUT_2_MODE_RAMA_LUT', 'CMC_LUT_2_MODE_RAMB_LUT',
'CMC_LUT_NUM_SEG', 'CMC_LUT_RAM_SEL', 'CMC_RAM0_ACCESS',
'CMC_RAM1_ACCESS', 'CMC_RAM2_ACCESS', 'CMC_RAM3_ACCESS',
'CMC_RAMA_ACCESS', 'CMC_RAMB_ACCESS', 'CMC_SEGMENTS_1',
'CMC_SEGMENTS_128', 'CMC_SEGMENTS_16', 'CMC_SEGMENTS_2',
'CMC_SEGMENTS_32', 'CMC_SEGMENTS_4', 'CMC_SEGMENTS_64',
'CMC_SEGMENTS_8', 'CMPTO', 'CM_BYPASS', 'CM_COEF_FORMAT_ENUM',
'CM_DATA_SIGNED', 'CM_DISABLE', 'CM_EN', 'CM_ENABLE',
'CM_GAMMA_LUT_MODE_ENUM', 'CM_GAMMA_LUT_PWL_DISABLE_ENUM',
'CM_GAMMA_LUT_SEL_ENUM', 'CM_GAMUT_REMAP_MODE_ENUM',
'CM_LUT_2_CONFIG_ENUM', 'CM_LUT_2_MODE_ENUM',
'CM_LUT_4_CONFIG_ENUM', 'CM_LUT_4_MODE_ENUM',
'CM_LUT_CONFIG_MODE', 'CM_LUT_NUM_SEG', 'CM_LUT_RAM_SEL',
'CM_LUT_READ_COLOR_SEL', 'CM_LUT_READ_DBG', 'CM_NOT_PENDING',
'CM_PENDING', 'CM_POST_CSC_MODE_ENUM', 'CM_WRITE_BASE_ONLY',
'CM_YES_PENDING', 'CNVC_BYPASS', 'CNVC_BYPASS_DISABLE',
'CNVC_BYPASS_EN', 'CNVC_COEF_FORMAT_ENUM', 'CNVC_DIS', 'CNVC_EN',
'CNVC_ENABLE', 'CNVC_FIX_S2_13', 'CNVC_FIX_S3_12',
'CNVC_NOT_PENDING', 'CNVC_PENDING', 'CNVC_ROUND', 'CNVC_TRUNCATE',
'CNVC_YES_PENDING', 'COEF_POST_CSC', 'COEF_POST_CSC_B',
'COEF_RAM_SELECT_BACK', 'COEF_RAM_SELECT_CURRENT',
'COEF_RAM_SELECT_RD', 'COLOR_24BIT_1BIT_AND',
'COLOR_24BIT_8BIT_ALPHA_PREMULT',
'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', 'COLOR_64BIT_FP_PREMULT',
'COLOR_64BIT_FP_UNPREMULT', 'COLOR_KEYER_MODE',
'COMB_DST_MINUS_SRC', 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC',
'COMB_MIN_DST_SRC', 'COMB_SRC_MINUS_DST', 'COMPAT_LEVEL',
'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', 'CONFIG_SPACE2_END',
'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', 'CONFIG_SPACE_START',
'CONTEXT_DONE', 'CONTEXT_SPACE_END', 'CONTEXT_SPACE_START',
'CONTEXT_SUSPEND', 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET',
'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET',
'CORB_READ_POINTER_RESET',
'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET',
'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0',
'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_LATENCY_STATS_SEL',
'CPC_LATENCY_STATS_SEL_INVAL_LAST',
'CPC_LATENCY_STATS_SEL_INVAL_MAX',
'CPC_LATENCY_STATS_SEL_INVAL_MIN',
'CPC_LATENCY_STATS_SEL_XACK_LAST',
'CPC_LATENCY_STATS_SEL_XACK_MAX',
'CPC_LATENCY_STATS_SEL_XACK_MIN',
'CPC_LATENCY_STATS_SEL_XNACK_LAST',
'CPC_LATENCY_STATS_SEL_XNACK_MAX',
'CPC_LATENCY_STATS_SEL_XNACK_MIN', 'CPC_PERFCOUNT_SEL',
'CPC_PERF_SEL_ALWAYS_COUNT', 'CPC_PERF_SEL_CPC_GCRIU_BUSY',
'CPC_PERF_SEL_CPC_GCRIU_IDLE', 'CPC_PERF_SEL_CPC_GCRIU_STALL',
'CPC_PERF_SEL_CPC_STAT_BUSY', 'CPC_PERF_SEL_CPC_STAT_IDLE',
'CPC_PERF_SEL_CPC_STAT_STALL', 'CPC_PERF_SEL_CPC_TCIU_BUSY',
'CPC_PERF_SEL_CPC_TCIU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY',
'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_STALL',
'CPC_PERF_SEL_CPC_UTCL2IU_XACK', 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK',
'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE',
'CPC_PERF_SEL_ME1_DC0_SPI_BUSY',
'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ',
'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF',
'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ',
'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE',
'CPC_PERF_SEL_ME2_DC1_SPI_BUSY',
'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ',
'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF',
'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ',
'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT',
'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', 'CPC_PERF_SEL_MES_THREAD0',
'CPC_PERF_SEL_MES_THREAD1',
'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION',
'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE',
'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE',
'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION',
'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM',
'CPF_LATENCY_STATS_SEL', 'CPF_LATENCY_STATS_SEL_INVAL_LAST',
'CPF_LATENCY_STATS_SEL_INVAL_MAX',
'CPF_LATENCY_STATS_SEL_INVAL_MIN',
'CPF_LATENCY_STATS_SEL_READ_LAST',
'CPF_LATENCY_STATS_SEL_READ_MAX',
'CPF_LATENCY_STATS_SEL_READ_MIN',
'CPF_LATENCY_STATS_SEL_XACK_LAST',
'CPF_LATENCY_STATS_SEL_XACK_MAX',
'CPF_LATENCY_STATS_SEL_XACK_MIN',
'CPF_LATENCY_STATS_SEL_XNACK_LAST',
'CPF_LATENCY_STATS_SEL_XNACK_MAX',
'CPF_LATENCY_STATS_SEL_XNACK_MIN', 'CPF_PERFCOUNTWINDOW_SEL',
'CPF_PERFCOUNT_SEL', 'CPF_PERFWINDOW_SEL_CSF',
'CPF_PERFWINDOW_SEL_HQD1', 'CPF_PERFWINDOW_SEL_HQD2',
'CPF_PERFWINDOW_SEL_RDMA', 'CPF_PERFWINDOW_SEL_RWPP',
'CPF_PERF_SEL_ALWAYS_COUNT',
'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION',
'CPF_PERF_SEL_CPF_GCRIU_BUSY', 'CPF_PERF_SEL_CPF_GCRIU_IDLE',
'CPF_PERF_SEL_CPF_GCRIU_STALL', 'CPF_PERF_SEL_CPF_STAT_BUSY',
'CPF_PERF_SEL_CPF_STAT_IDLE', 'CPF_PERF_SEL_CPF_STAT_STALL',
'CPF_PERF_SEL_CPF_TCIU_BUSY', 'CPF_PERF_SEL_CPF_TCIU_IDLE',
'CPF_PERF_SEL_CPF_TCIU_STALL', 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY',
'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', 'CPF_PERF_SEL_CPF_UTCL2IU_STALL',
'CPF_PERF_SEL_CPF_UTCL2IU_XACK', 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK',
'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE',
'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ',
'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY',
'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING',
'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE',
'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS',
'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR',
'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID',
'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION',
'CPF_PERF_SEL_GRBM_DWORDS_SENT',
'CPF_PERF_SEL_GUS_READ_REQUEST_SENT',
'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT',
'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE',
'CPF_PERF_SEL_REGISTER_CLOCK_VALID',
'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT',
'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE',
'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS',
'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS',
'CPF_SCRATCH_REG_ATOMIC_ADD', 'CPF_SCRATCH_REG_ATOMIC_AND',
'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', 'CPF_SCRATCH_REG_ATOMIC_MAX',
'CPF_SCRATCH_REG_ATOMIC_MIN', 'CPF_SCRATCH_REG_ATOMIC_NOT',
'CPF_SCRATCH_REG_ATOMIC_OP', 'CPF_SCRATCH_REG_ATOMIC_OR',
'CPF_SCRATCH_REG_ATOMIC_SUB', 'CPF_TAG_RAM',
'CPG_LATENCY_STATS_SEL', 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST',
'CPG_LATENCY_STATS_SEL_ATOMIC_MAX',
'CPG_LATENCY_STATS_SEL_ATOMIC_MIN',
'CPG_LATENCY_STATS_SEL_INVAL_LAST',
'CPG_LATENCY_STATS_SEL_INVAL_MAX',
'CPG_LATENCY_STATS_SEL_INVAL_MIN',
'CPG_LATENCY_STATS_SEL_READ_LAST',
'CPG_LATENCY_STATS_SEL_READ_MAX',
'CPG_LATENCY_STATS_SEL_READ_MIN',
'CPG_LATENCY_STATS_SEL_WRITE_LAST',
'CPG_LATENCY_STATS_SEL_WRITE_MAX',
'CPG_LATENCY_STATS_SEL_WRITE_MIN',
'CPG_LATENCY_STATS_SEL_XACK_LAST',
'CPG_LATENCY_STATS_SEL_XACK_MAX',
'CPG_LATENCY_STATS_SEL_XACK_MIN',
'CPG_LATENCY_STATS_SEL_XNACK_LAST',
'CPG_LATENCY_STATS_SEL_XNACK_MAX',
'CPG_LATENCY_STATS_SEL_XNACK_MIN', 'CPG_PERFCOUNTWINDOW_SEL',
'CPG_PERFCOUNT_SEL', 'CPG_PERFWINDOW_SEL_APPEND',
'CPG_PERFWINDOW_SEL_CE', 'CPG_PERFWINDOW_SEL_CEDMA',
'CPG_PERFWINDOW_SEL_CPC_IC', 'CPG_PERFWINDOW_SEL_CPG_IC',
'CPG_PERFWINDOW_SEL_DDID', 'CPG_PERFWINDOW_SEL_DFY',
'CPG_PERFWINDOW_SEL_DMA', 'CPG_PERFWINDOW_SEL_ME',
'CPG_PERFWINDOW_SEL_MEC1', 'CPG_PERFWINDOW_SEL_MEC2',
'CPG_PERFWINDOW_SEL_MEMRD', 'CPG_PERFWINDOW_SEL_MEMWR',
'CPG_PERFWINDOW_SEL_MES', 'CPG_PERFWINDOW_SEL_PFP',
'CPG_PERFWINDOW_SEL_PQ1', 'CPG_PERFWINDOW_SEL_PQ2',
'CPG_PERFWINDOW_SEL_PQ3', 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR',
'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', 'CPG_PERFWINDOW_SEL_QURD',
'CPG_PERFWINDOW_SEL_QU_EOP', 'CPG_PERFWINDOW_SEL_QU_PIPE',
'CPG_PERFWINDOW_SEL_QU_STRM', 'CPG_PERFWINDOW_SEL_RB',
'CPG_PERFWINDOW_SEL_RESERVED1', 'CPG_PERFWINDOW_SEL_RESERVED2',
'CPG_PERFWINDOW_SEL_SHADOW', 'CPG_PERFWINDOW_SEL_SR',
'CPG_PERFWINDOW_SEL_VGT0', 'CPG_PERFWINDOW_SEL_VGT1',
'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', 'CPG_PERF_SEL_ALWAYS_COUNT',
'CPG_PERF_SEL_CE_INSTR_CACHE_HIT',
'CPG_PERF_SEL_CE_INSTR_CACHE_MISS',
'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG',
'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ',
'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER',
'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO',
'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO',
'CPG_PERF_SEL_CE_STALL_RAM_DUMP',
'CPG_PERF_SEL_CE_STALL_RAM_WRITE',
'CPG_PERF_SEL_COUNT_TYPE0_PACKETS',
'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 'CPG_PERF_SEL_CPG_GCRIU_BUSY',
'CPG_PERF_SEL_CPG_GCRIU_IDLE', 'CPG_PERF_SEL_CPG_GCRIU_STALL',
'CPG_PERF_SEL_CPG_STAT_BUSY', 'CPG_PERF_SEL_CPG_STAT_IDLE',
'CPG_PERF_SEL_CPG_STAT_STALL', 'CPG_PERF_SEL_CPG_TCIU_BUSY',
'CPG_PERF_SEL_CPG_TCIU_IDLE', 'CPG_PERF_SEL_CPG_TCIU_STALL',
'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE',
'CPG_PERF_SEL_CPG_UTCL2IU_STALL', 'CPG_PERF_SEL_CPG_UTCL2IU_XACK',
'CPG_PERF_SEL_CPG_UTCL2IU_XNACK',
'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS',
'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT',
'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS',
'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS',
'CPG_PERF_SEL_DMA_BUSY',
'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL',
'CPG_PERF_SEL_DMA_STALLED', 'CPG_PERF_SEL_DMA_STARVED',
'CPG_PERF_SEL_DYNAMIC_CLK_VALID',
'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE',
'CPG_PERF_SEL_GUS_READ_REQUEST_SENT',
'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT',
'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY',
'CPG_PERF_SEL_ME_INSTR_CACHE_HIT',
'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', 'CPG_PERF_SEL_ME_PARSER_BUSY',
'CPG_PERF_SEL_ME_PWS_STALLED0', 'CPG_PERF_SEL_ME_PWS_STALLED1',
'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP',
'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ',
'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX',
'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH',
'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS',
'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU',
'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER',
'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER',
'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT',
'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS',
'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1',
'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2',
'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1',
'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2',
'CPG_PERF_SEL_PFP_PWS_STALLED0', 'CPG_PERF_SEL_PFP_PWS_STALLED1',
'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ',
'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY',
'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY',
'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY',
'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY',
'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE',
'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM',
'CPG_PERF_SEL_RBIU_FIFO_FULL',
'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ',
'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ',
'CPG_PERF_SEL_REGISTER_CLK_VALID',
'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX',
'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS',
'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT',
'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE',
'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS',
'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT',
'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION',
'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE',
'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM',
'CP_ALPHA_TAG_RAM_SEL', 'CP_DDID_CNTL_MODE', 'CP_DDID_CNTL_SIZE',
'CP_DDID_CNTL_VMID_SEL', 'CP_ME_ID', 'CP_PACKET2',
'CP_PERFMON_ENABLE_MODE', 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT',
'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE',
'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE',
'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE',
'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM',
'CP_PERFMON_STATE_DISABLE_AND_RESET',
'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM',
'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING',
'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID',
'CRC_CUR_0', 'CRC_CUR_1', 'CRC_CUR_SEL', 'CRC_INTERLACE_0',
'CRC_INTERLACE_1', 'CRC_INTERLACE_2', 'CRC_INTERLACE_3',
'CRC_INTERLACE_SEL', 'CRC_IN_CUR_0', 'CRC_IN_CUR_1',
'CRC_IN_CUR_2', 'CRC_IN_CUR_3', 'CRC_IN_CUR_SEL', 'CRC_IN_PIX_0',
'CRC_IN_PIX_1', 'CRC_IN_PIX_2', 'CRC_IN_PIX_3', 'CRC_IN_PIX_4',
'CRC_IN_PIX_5', 'CRC_IN_PIX_6', 'CRC_IN_PIX_7', 'CRC_IN_PIX_SEL',
'CRC_SRC_0', 'CRC_SRC_1', 'CRC_SRC_2', 'CRC_SRC_3', 'CRC_SRC_SEL',
'CRC_STEREO_0', 'CRC_STEREO_1', 'CRC_STEREO_2', 'CRC_STEREO_3',
'CRC_STEREO_SEL', 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1',
'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2',
'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
'CROB_MEM_PWR_LIGHT_SLEEP_MODE', 'CROSSBAR_FOR_ALPHA',
'CROSSBAR_FOR_CB_B', 'CROSSBAR_FOR_CR_R', 'CROSSBAR_FOR_Y_G',
'CRS', 'CR_R_DATA_ONTO_ALPHA_PORT', 'CR_R_DATA_ONTO_CB_B_PORT',
'CR_R_DATA_ONTO_CR_R_PORT', 'CR_R_DATA_ONTO_Y_G_PORT',
'CSCNTL_ADDR_WIDTH', 'CSCNTL_DATA_WIDTH', 'CSCNTL_TYPE',
'CSCNTL_TYPE_EVENT', 'CSCNTL_TYPE_PRIVATE', 'CSCNTL_TYPE_STATE',
'CSCNTL_TYPE_TG', 'CSCNTL_TYPE_WIDTH', 'CSDATA_ADDR_WIDTH',
'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', 'CSDATA_TYPE_EVENT',
'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', 'CSDATA_TYPE_TG',
'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', 'CS_DONE', 'CS_NA',
'CS_PARTIAL_FLUSH', 'CS_STAGE_ON', 'CURSOR_2X_MAGNIFY',
'CURSOR_2X_MAGNIFY_IS_DISABLE', 'CURSOR_2X_MAGNIFY_IS_ENABLE',
'CURSOR_COLOR_24BIT_1BIT_AND',
'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT',
'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT',
'CURSOR_COLOR_64BIT_FP_PREMULT',
'CURSOR_COLOR_64BIT_FP_UNPREMULT', 'CURSOR_ENABLE',
'CURSOR_IN_GUEST_PHYSICAL_ADDRESS',
'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', 'CURSOR_IS_DISABLE',
'CURSOR_IS_ENABLE', 'CURSOR_IS_NOT_SNOOP', 'CURSOR_IS_SNOOP',
'CURSOR_LINES_PER_CHUNK', 'CURSOR_LINE_PER_CHUNK_1',
'CURSOR_LINE_PER_CHUNK_16', 'CURSOR_LINE_PER_CHUNK_2',
'CURSOR_LINE_PER_CHUNK_4', 'CURSOR_LINE_PER_CHUNK_8',
'CURSOR_MODE', 'CURSOR_MONO_2BIT',
'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY',
'CURSOR_PERFMON_LATENCY_MEASURE_EN',
'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED',
'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED',
'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY',
'CURSOR_PERFMON_LATENCY_MEASURE_SEL', 'CURSOR_PITCH',
'CURSOR_PITCH_128_PIXELS', 'CURSOR_PITCH_256_PIXELS',
'CURSOR_PITCH_64_PIXELS', 'CURSOR_REQUEST_EARLY',
'CURSOR_REQUEST_NORMALLY', 'CURSOR_REQ_MODE', 'CURSOR_SNOOP',
'CURSOR_STEREO_EN', 'CURSOR_STEREO_IS_DISABLED',
'CURSOR_STEREO_IS_ENABLED', 'CURSOR_SURFACE_IS_NOT_TMZ',
'CURSOR_SURFACE_IS_TMZ', 'CURSOR_SURFACE_TMZ', 'CURSOR_SYSTEM',
'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS',
'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0',
'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1',
'CUR_CLAMP_DIS', 'CUR_CLAMP_EN', 'CUR_DIS',
'CUR_DYNAMIC_EXPANSION', 'CUR_EN', 'CUR_ENABLE',
'CUR_EXPAND_MODE', 'CUR_FP_NO_ROM', 'CUR_FP_USE_ROM',
'CUR_INV_CLAMP', 'CUR_MODE', 'CUR_NOT_PENDING', 'CUR_PENDING',
'CUR_ROM_EN', 'CUR_YES_PENDING', 'CUR_ZERO_EXPANSION',
'CbYCrY10101010_422_PACKED', 'CbYCrY12121212_422_PACKED',
'CbYCrY8888_422_PACKED', 'CmaskCode', 'CombFunc', 'CompareFrag',
'ConservativeZExport', 'CovToShaderSel', 'CrYCbA1010102',
'CrYCbA16161616_10LSB', 'CrYCbA16161616_10MSB',
'CrYCbA16161616_12LSB', 'CrYCbA16161616_12MSB', 'CrYCbA8888',
'CrYCbY10101010_422_PACKED', 'CrYCbY12121212_422_PACKED',
'CrYCbY8888_422_PACKED', 'DAC_MUX_SELECT', 'DAC_MUX_SELECT_DACA',
'DAC_MUX_SELECT_DACB', 'DB_BREAK_BATCH_EVENT', 'DB_CACHE_FLUSH',
'DB_CACHE_FLUSH_AND_INV', 'DB_CACHE_FLUSH_AND_INV_EVENT',
'DB_CACHE_FLUSH_AND_INV_TS_EVENT', 'DB_CACHE_FLUSH_TS',
'DB_CONTEXT_DONE_EVENT', 'DB_CONTEXT_SUSPEND_EVENT',
'DB_FLUSH_AND_INV_DB_DATA_TS', 'DB_FLUSH_AND_INV_DB_META',
'DB_INVOKE_CHANGE_EVENT', 'DB_PERF_SEL_CB_DB_rdreq_prt_sends',
'DB_PERF_SEL_CB_DB_rdreq_sends',
'DB_PERF_SEL_CB_DB_wrreq_prt_sends',
'DB_PERF_SEL_CB_DB_wrreq_sends',
'DB_PERF_SEL_DB_CB_context_dones', 'DB_PERF_SEL_DB_CB_eop_dones',
'DB_PERF_SEL_DB_CB_lquad_busy',
'DB_PERF_SEL_DB_CB_lquad_double_format',
'DB_PERF_SEL_DB_CB_lquad_export_quads',
'DB_PERF_SEL_DB_CB_lquad_fast_format',
'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix',
'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix',
'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix',
'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix',
'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending',
'DB_PERF_SEL_DB_CB_lquad_quads',
'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1',
'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2',
'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1',
'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2',
'DB_PERF_SEL_DB_CB_lquad_sends',
'DB_PERF_SEL_DB_CB_lquad_slow_format',
'DB_PERF_SEL_DB_CB_lquad_stalls', 'DB_PERF_SEL_DB_CB_rdret_ack',
'DB_PERF_SEL_DB_CB_rdret_nack', 'DB_PERF_SEL_DB_CB_tile_busy',
'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS',
'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA',
'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS',
'DB_PERF_SEL_DB_CB_tile_sends', 'DB_PERF_SEL_DB_CB_tile_stalls',
'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event',
'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack',
'DB_PERF_SEL_DB_SC_c_tile_rate', 'DB_PERF_SEL_DB_SC_quad_busy',
'DB_PERF_SEL_DB_SC_quad_double_quad',
'DB_PERF_SEL_DB_SC_quad_lit_noz_quad',
'DB_PERF_SEL_DB_SC_quad_lit_quad',
'DB_PERF_SEL_DB_SC_quad_noz_tiles',
'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels',
'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels',
'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels',
'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel',
'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels',
'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels',
'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels',
'DB_PERF_SEL_DB_SC_quad_sends', 'DB_PERF_SEL_DB_SC_quad_stalls',
'DB_PERF_SEL_DB_SC_quad_tiles', 'DB_PERF_SEL_DB_SC_s_tile_rate',
'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled',
'DB_PERF_SEL_DB_SC_tile_df_stalls',
'DB_PERF_SEL_DB_SC_tile_fast_ops',
'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops',
'DB_PERF_SEL_DB_SC_tile_fast_z_ops',
'DB_PERF_SEL_DB_SC_tile_hier_kill',
'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends',
'DB_PERF_SEL_DB_SC_tile_ssaa_kill',
'DB_PERF_SEL_DB_SC_tile_stalls',
'DB_PERF_SEL_DB_SC_tile_tile_rate',
'DB_PERF_SEL_DB_SC_tile_tiles', 'DB_PERF_SEL_DB_SC_z_tile_rate',
'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall',
'DB_PERF_SEL_Depth_Tile_Cache_busy',
'DB_PERF_SEL_Depth_Tile_Cache_data_frees',
'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop',
'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked',
'DB_PERF_SEL_Depth_Tile_Cache_event',
'DB_PERF_SEL_Depth_Tile_Cache_flushes',
'DB_PERF_SEL_Depth_Tile_Cache_hits',
'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve',
'DB_PERF_SEL_Depth_Tile_Cache_misses',
'DB_PERF_SEL_Depth_Tile_Cache_noop_tile',
'DB_PERF_SEL_Depth_Tile_Cache_sends',
'DB_PERF_SEL_Depth_Tile_Cache_starves',
'DB_PERF_SEL_Depth_Tile_Cache_tile_frees',
'DB_PERF_SEL_MI_psd_req_wrack_counter_stall',
'DB_PERF_SEL_MI_quad_req_wrack_counter_stall',
'DB_PERF_SEL_MI_tile_req_wrack_counter_stall',
'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall',
'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall',
'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy',
'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits',
'DB_PERF_SEL_Plane_Cache_flushes',
'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits',
'DB_PERF_SEL_Plane_Cache_misses',
'DB_PERF_SEL_Plane_Cache_starves',
'DB_PERF_SEL_PostZ_Samples_failing_DB',
'DB_PERF_SEL_PostZ_Samples_failing_S',
'DB_PERF_SEL_PostZ_Samples_failing_Z',
'DB_PERF_SEL_PostZ_Samples_passing_Z',
'DB_PERF_SEL_PreZ_Samples_failing_DB',
'DB_PERF_SEL_PreZ_Samples_failing_S',
'DB_PERF_SEL_PreZ_Samples_failing_Z',
'DB_PERF_SEL_PreZ_Samples_passing_Z',
'DB_PERF_SEL_RMI_rd_s_32byte_req',
'DB_PERF_SEL_RMI_rd_s_32byte_ret',
'DB_PERF_SEL_RMI_rd_tile_32byte_req',
'DB_PERF_SEL_RMI_rd_tile_32byte_ret',
'DB_PERF_SEL_RMI_rd_z_32byte_req',
'DB_PERF_SEL_RMI_rd_z_32byte_ret',
'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack',
'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req',
'DB_PERF_SEL_RMI_wr_s_32byte_ack',
'DB_PERF_SEL_RMI_wr_s_32byte_req',
'DB_PERF_SEL_RMI_wr_tile_32byte_ack',
'DB_PERF_SEL_RMI_wr_tile_32byte_req',
'DB_PERF_SEL_RMI_wr_z_32byte_ack',
'DB_PERF_SEL_RMI_wr_z_32byte_req', 'DB_PERF_SEL_SC_DB_quad_busy',
'DB_PERF_SEL_SC_DB_quad_killed_tiles',
'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_quads',
'DB_PERF_SEL_SC_DB_quad_quads_pipe0',
'DB_PERF_SEL_SC_DB_quad_quads_pipe1',
'DB_PERF_SEL_SC_DB_quad_sends', 'DB_PERF_SEL_SC_DB_quad_squads',
'DB_PERF_SEL_SC_DB_quad_tiles', 'DB_PERF_SEL_SC_DB_tile_backface',
'DB_PERF_SEL_SC_DB_tile_busy', 'DB_PERF_SEL_SC_DB_tile_covered',
'DB_PERF_SEL_SC_DB_tile_events', 'DB_PERF_SEL_SC_DB_tile_sends',
'DB_PERF_SEL_SC_DB_tile_stalls', 'DB_PERF_SEL_SC_DB_tile_tiles',
'DB_PERF_SEL_SC_DB_tile_tiles_pipe0',
'DB_PERF_SEL_SC_DB_tile_tiles_pipe1',
'DB_PERF_SEL_SH_quads_outstanding_sum',
'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled',
'DB_PERF_SEL_SX_DB_quad_all_pixels_killed',
'DB_PERF_SEL_SX_DB_quad_busy',
'DB_PERF_SEL_SX_DB_quad_double_format',
'DB_PERF_SEL_SX_DB_quad_export_quads',
'DB_PERF_SEL_SX_DB_quad_exports',
'DB_PERF_SEL_SX_DB_quad_fast_format',
'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read',
'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads',
'DB_PERF_SEL_SX_DB_quad_sends',
'DB_PERF_SEL_SX_DB_quad_slow_format',
'DB_PERF_SEL_SX_DB_quad_stalls',
'DB_PERF_SEL_Stencil_Cache_flushes',
'DB_PERF_SEL_Stencil_Cache_frees',
'DB_PERF_SEL_Stencil_Cache_hits',
'DB_PERF_SEL_Stencil_Cache_misses',
'DB_PERF_SEL_Stencil_Cache_starves',
'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits',
'DB_PERF_SEL_Tile_Cache_mem_return_starve',
'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves',
'DB_PERF_SEL_Tile_Cache_surface_stall',
'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes',
'DB_PERF_SEL_Z_Cache_pmask_hits',
'DB_PERF_SEL_Z_Cache_pmask_misses',
'DB_PERF_SEL_Z_Cache_pmask_starves',
'DB_PERF_SEL_Z_Cache_separate_Z_flushes',
'DB_PERF_SEL_Z_Cache_separate_Z_hits',
'DB_PERF_SEL_Z_Cache_separate_Z_misses',
'DB_PERF_SEL_Z_Cache_separate_Z_starves',
'DB_PERF_SEL_clock_main_active',
'DB_PERF_SEL_clock_mem_export_active',
'DB_PERF_SEL_clock_reg_active',
'DB_PERF_SEL_cs_events_pws_enable',
'DB_PERF_SEL_depth_bounds_tile_culled', 'DB_PERF_SEL_di_dt_stall',
'DB_PERF_SEL_dk_squad_busy', 'DB_PERF_SEL_dk_squad_sends',
'DB_PERF_SEL_dk_squad_stalls', 'DB_PERF_SEL_dk_tile_busy',
'DB_PERF_SEL_dk_tile_quad_starves', 'DB_PERF_SEL_dk_tile_sends',
'DB_PERF_SEL_dk_tile_stalls', 'DB_PERF_SEL_dkg_tile_rate_tile',
'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall',
'DB_PERF_SEL_dtt_sm_slot_stall',
'DB_PERF_SEL_earlyZ_waiting_for_postZ_done',
'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward',
'DB_PERF_SEL_esr_eot_fwd_holding_squad',
'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall',
'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_src_in_sends',
'DB_PERF_SEL_esr_ps_src_in_squads',
'DB_PERF_SEL_esr_ps_src_in_squads_unrolled',
'DB_PERF_SEL_esr_ps_src_in_stall',
'DB_PERF_SEL_esr_ps_src_in_tile_rate',
'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled',
'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate',
'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_ps_vic_busy',
'DB_PERF_SEL_esr_ps_vic_stall',
'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut',
'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut',
'DB_PERF_SEL_esr_psi_vic_tile_rate',
'DB_PERF_SEL_esr_sqq_zi_busy', 'DB_PERF_SEL_esr_sqq_zi_stall',
'DB_PERF_SEL_esr_vic_footprint_match_1x2',
'DB_PERF_SEL_esr_vic_footprint_match_2x1',
'DB_PERF_SEL_esr_vic_footprint_match_2x2',
'DB_PERF_SEL_esr_vic_sqq_busy', 'DB_PERF_SEL_esr_vic_sqq_stall',
'DB_PERF_SEL_etr_out_busy', 'DB_PERF_SEL_etr_out_cb_tile_stall',
'DB_PERF_SEL_etr_out_esr_stall',
'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall',
'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane',
'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane',
'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane',
'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane',
'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane',
'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane',
'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane',
'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane',
'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed',
'DB_PERF_SEL_flush_compressed_stencil',
'DB_PERF_SEL_flush_expanded_stencil',
'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4',
'DB_PERF_SEL_flush_single_stencil',
'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1',
'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1',
'DB_PERF_SEL_his_tile_culled', 'DB_PERF_SEL_hiz_tc_read_starved',
'DB_PERF_SEL_hiz_tc_write_stall', 'DB_PERF_SEL_hiz_tile_culled',
'DB_PERF_SEL_mi_quad_rd_outstanding_sum',
'DB_PERF_SEL_mi_quad_wr_outstanding_sum',
'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall',
'DB_PERF_SEL_mi_tile_rd_outstanding_sum',
'DB_PERF_SEL_mi_tile_wr_outstanding_sum',
'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall',
'DB_PERF_SEL_noz_waiting_for_postz_done',
'DB_PERF_SEL_planes_flushed',
'DB_PERF_SEL_postz_ps_invoked_pixel_cnt',
'DB_PERF_SEL_postzl_full_launch',
'DB_PERF_SEL_postzl_partial_launch',
'DB_PERF_SEL_postzl_partial_waiting',
'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall',
'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall',
'DB_PERF_SEL_postzl_src_in_sends',
'DB_PERF_SEL_postzl_src_in_squads',
'DB_PERF_SEL_postzl_src_in_squads_unrolled',
'DB_PERF_SEL_postzl_src_in_stall',
'DB_PERF_SEL_postzl_src_in_tile_rate',
'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled',
'DB_PERF_SEL_postzl_src_out_stall',
'DB_PERF_SEL_postzl_tile_init_stall',
'DB_PERF_SEL_postzl_tile_mem_stall',
'DB_PERF_SEL_prez_ps_invoked_pixel_cnt',
'DB_PERF_SEL_prezl_src_in_sends',
'DB_PERF_SEL_prezl_src_in_squads',
'DB_PERF_SEL_prezl_src_in_squads_unrolled',
'DB_PERF_SEL_prezl_src_in_stall',
'DB_PERF_SEL_prezl_src_in_tile_rate',
'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled',
'DB_PERF_SEL_prezl_src_out_stall',
'DB_PERF_SEL_prezl_tile_init_stall',
'DB_PERF_SEL_prezl_tile_mem_stall',
'DB_PERF_SEL_ps_events_pws_enable', 'DB_PERF_SEL_qc_busy',
'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall',
'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ',
'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc',
'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy',
'DB_PERF_SEL_quad_rd_mi_stall',
'DB_PERF_SEL_quad_rd_mi_stall_unc', 'DB_PERF_SEL_quad_rd_panic',
'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends',
'DB_PERF_SEL_quad_rd_sends_unc', 'DB_PERF_SEL_quad_rd_tag_stall',
'DB_PERF_SEL_quad_rdret_busy', 'DB_PERF_SEL_quad_rdret_sends',
'DB_PERF_SEL_quad_wr_acks', 'DB_PERF_SEL_quad_wr_busy',
'DB_PERF_SEL_quad_wr_coherency_stall',
'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends',
'DB_PERF_SEL_reZ_waiting_for_postZ_done',
'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop',
'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start',
'DB_PERF_SEL_tcp_dispatcher_flushes',
'DB_PERF_SEL_tcp_dispatcher_reads',
'DB_PERF_SEL_tcp_prefetcher_flushes',
'DB_PERF_SEL_tcp_prefetcher_reads',
'DB_PERF_SEL_tcp_preloader_flushes',
'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends',
'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends',
'DB_PERF_SEL_tiles_compressed_to_decompressed',
'DB_PERF_SEL_tiles_decomp_on_expclear',
'DB_PERF_SEL_tiles_s_clear_on_expclear',
'DB_PERF_SEL_tiles_stencil_fully_summarized',
'DB_PERF_SEL_tiles_z_clear_on_expclear',
'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy',
'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events',
'DB_PERF_SEL_tl_expand_squads',
'DB_PERF_SEL_tl_flush_expand_squads',
'DB_PERF_SEL_tl_in_fast_z_stall',
'DB_PERF_SEL_tl_in_single_stencil_expand_stall',
'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads',
'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads',
'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads',
'DB_PERF_SEL_tl_preZ_squads',
'DB_PERF_SEL_tl_stencil_locked_stall',
'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads',
'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall',
'DB_PERF_SEL_tl_z_fetch_stall',
'DB_PERF_SEL_ts_events_pws_enable',
'DB_PERF_SEL_ts_tc_update_stall',
'DB_PERF_SEL_tsc_insert_summarize_stall',
'DB_PERF_SEL_unmapped_z_tile_culled',
'DB_PERF_SEL_zf_plane_multicycle', 'DB_VPORT_CHANGED_EVENT',
'DCCG_AUDIO_DTO0_SOURCE_SEL', 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0',
'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1',
'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2',
'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3',
'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED',
'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0',
'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', 'DCCG_AUDIO_DTO_SEL',
'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1',
'DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK',
'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO',
'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP',
'DCCG_AUDIO_DTO_USE_512FBR_DTO',
'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DBG_BLOCK_SEL',
'DCCG_DBG_BLOCK_SEL_DCCG', 'DCCG_DBG_BLOCK_SEL_PMON',
'DCCG_DBG_BLOCK_SEL_PMON2', 'DCCG_DBG_EN', 'DCCG_DBG_EN_DISABLE',
'DCCG_DBG_EN_ENABLE', 'DCCG_DEEP_COLOR_CNTL',
'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO',
'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE',
'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN',
'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET',
'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP',
'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION',
'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_MODE_HSYNC',
'DCCG_PERF_MODE_HSYNC_NOOP', 'DCCG_PERF_MODE_HSYNC_START',
'DCCG_PERF_MODE_VSYNC', 'DCCG_PERF_MODE_VSYNC_NOOP',
'DCCG_PERF_MODE_VSYNC_START', 'DCCG_PERF_OTG_SELECT',
'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START',
'DCCG_PERF_SEL_OTG0', 'DCCG_PERF_SEL_OTG1', 'DCCG_PERF_SEL_OTG2',
'DCCG_PERF_SEL_OTG3', 'DCCG_PERF_SEL_RESERVED',
'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1',
'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2',
'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE',
'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE',
'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE',
'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP',
'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP',
'DCHUBBUB_MEM_POWER_MODE_OFF',
'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', 'DCHUBBUB_MEM_PWR_DIS_MODE',
'DCHUBBUB_MEM_PWR_MODE', 'DCIOCHIP_AUX_ALL_PWR_OK',
'DCIOCHIP_AUX_ALL_PWR_OK_0', 'DCIOCHIP_AUX_ALL_PWR_OK_1',
'DCIOCHIP_AUX_CSEL0P9', 'DCIOCHIP_AUX_CSEL1P1',
'DCIOCHIP_AUX_CSEL_DEC0P9', 'DCIOCHIP_AUX_CSEL_DEC1P0',
'DCIOCHIP_AUX_CSEL_INC1P0', 'DCIOCHIP_AUX_CSEL_INC1P1',
'DCIOCHIP_AUX_FALLSLEWSEL', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0',
'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW',
'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_HYS_TUNE',
'DCIOCHIP_AUX_HYS_TUNE_0', 'DCIOCHIP_AUX_HYS_TUNE_1',
'DCIOCHIP_AUX_HYS_TUNE_2', 'DCIOCHIP_AUX_HYS_TUNE_3',
'DCIOCHIP_AUX_RECEIVER_SEL', 'DCIOCHIP_AUX_RECEIVER_SEL_0',
'DCIOCHIP_AUX_RECEIVER_SEL_1', 'DCIOCHIP_AUX_RECEIVER_SEL_2',
'DCIOCHIP_AUX_RECEIVER_SEL_3', 'DCIOCHIP_AUX_RSEL0P9',
'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9',
'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0',
'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL',
'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS',
'DCIOCHIP_AUX_VOD_TUNE', 'DCIOCHIP_AUX_VOD_TUNE_0',
'DCIOCHIP_AUX_VOD_TUNE_1', 'DCIOCHIP_AUX_VOD_TUNE_2',
'DCIOCHIP_AUX_VOD_TUNE_3', 'DCIOCHIP_GPIO_MASK_EN',
'DCIOCHIP_GPIO_MASK_EN_HARDWARE',
'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL',
'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED',
'DCIOCHIP_I2C_COMPSEL', 'DCIOCHIP_I2C_FALLSLEWSEL',
'DCIOCHIP_I2C_FALLSLEWSEL_00', 'DCIOCHIP_I2C_FALLSLEWSEL_01',
'DCIOCHIP_I2C_FALLSLEWSEL_10', 'DCIOCHIP_I2C_FALLSLEWSEL_11',
'DCIOCHIP_I2C_RECEIVER_SEL', 'DCIOCHIP_I2C_RECEIVER_SEL_0',
'DCIOCHIP_I2C_RECEIVER_SEL_1', 'DCIOCHIP_I2C_RECEIVER_SEL_2',
'DCIOCHIP_I2C_RECEIVER_SEL_3', 'DCIOCHIP_I2C_REC_COMPARATOR',
'DCIOCHIP_I2C_REC_SCHMIT', 'DCIOCHIP_I2C_VPH_1V2_EN',
'DCIOCHIP_I2C_VPH_1V2_EN_0', 'DCIOCHIP_I2C_VPH_1V2_EN_1',
'DCIOCHIP_INVERT', 'DCIOCHIP_MASK', 'DCIOCHIP_MASK_DISABLE',
'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE',
'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN',
'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW',
'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT',
'DCIOCHIP_REF_27_SRC_SEL',
'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS',
'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER',
'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS',
'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5',
'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6',
'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL',
'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS',
'DCIO_DBG_ASYNC_4BIT_SEL', 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8',
'DCIO_DBG_ASYNC_4BIT_SEL_15TO12',
'DCIO_DBG_ASYNC_4BIT_SEL_19TO16',
'DCIO_DBG_ASYNC_4BIT_SEL_23TO20',
'DCIO_DBG_ASYNC_4BIT_SEL_27TO24',
'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0',
'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 'DCIO_DBG_ASYNC_BLOCK_SEL',
'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO',
'DCIO_DBG_ASYNC_BLOCK_SEL_DIO',
'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', 'DCIO_DCRXPHY_SOFT_RESET',
'DCIO_DCRXPHY_SOFT_RESET_ASSERT',
'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', 'DCIO_DC_GENERICA_SEL',
'DCIO_DC_GENERICB_SEL',
'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL',
'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL',
'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL',
'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL',
'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE',
'DCIO_DC_GPU_TIMER_READ_SELECT',
'DCIO_DC_GPU_TIMER_START_POSITION',
'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL',
'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL',
'DCIO_DIO_EXT_VSYNC_MASK', 'DCIO_DIO_OTG_EXT_VSYNC_MUX',
'DCIO_DISPCLK_R_DCIO_GATE_DISABLE',
'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE',
'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK',
'DCIO_DPCS_INTERRUPT_TYPE',
'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED',
'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED',
'DCIO_DPRX_LOOPBACK_ENABLE_LOOP',
'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 'DCIO_DSYNC_SOFT_RESET',
'DCIO_DSYNC_SOFT_RESET_ASSERT', 'DCIO_DSYNC_SOFT_RESET_DEASSERT',
'DCIO_EXT_VSYNC_MASK_NONE', 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE',
'DCIO_EXT_VSYNC_MASK_PIPE0', 'DCIO_EXT_VSYNC_MASK_PIPE1',
'DCIO_EXT_VSYNC_MASK_PIPE2', 'DCIO_EXT_VSYNC_MASK_PIPE3',
'DCIO_EXT_VSYNC_MASK_PIPE4', 'DCIO_EXT_VSYNC_MASK_PIPE5',
'DCIO_EXT_VSYNC_MUX_GENERICB', 'DCIO_EXT_VSYNC_MUX_OTG0',
'DCIO_EXT_VSYNC_MUX_OTG1', 'DCIO_EXT_VSYNC_MUX_OTG2',
'DCIO_EXT_VSYNC_MUX_OTG3', 'DCIO_EXT_VSYNC_MUX_OTG4',
'DCIO_EXT_VSYNC_MUX_OTG5', 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB',
'DCIO_GENERICA_SEL_GENERICA_DCCG', 'DCIO_GENERICA_SEL_STEREOSYNC',
'DCIO_GENERICA_SEL_SYNCEN', 'DCIO_GENERICB_SEL_GENERICB_DCCG',
'DCIO_GENERICB_SEL_STEREOSYNC', 'DCIO_GENERICB_SEL_SYNCEN',
'DCIO_GENLK_CLK_GSL_MASK', 'DCIO_GENLK_CLK_GSL_MASK_NO',
'DCIO_GENLK_CLK_GSL_MASK_STEREO',
'DCIO_GENLK_CLK_GSL_MASK_TIMING',
'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE',
'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1',
'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2',
'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3',
'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO',
'DCIO_GENLK_VSYNC_GSL_MASK_STEREO',
'DCIO_GENLK_VSYNC_GSL_MASK_TIMING',
'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP',
'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM',
'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE',
'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP',
'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM',
'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE',
'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37',
'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29',
'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31',
'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35',
'DCIO_GSL_SEL', 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1',
'DCIO_GSL_SEL_GROUP_2', 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE',
'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2',
'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', 'DCIO_PHY_HPO_ENC_SRC_SEL',
'DCIO_SWAPLOCK_A_GSL_MASK', 'DCIO_SWAPLOCK_A_GSL_MASK_NO',
'DCIO_SWAPLOCK_A_GSL_MASK_STEREO',
'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK',
'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO',
'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK',
'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SOCCLK',
'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK',
'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK',
'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK',
'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK',
'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK',
'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK',
'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK',
'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2',
'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED',
'DCIO_UNIPHY_CHANNEL_NO_INVERSION',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2',
'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL',
'DCIO_UNIPHY_IMPCAL_SEL_BINARY',
'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE',
'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT',
'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK',
'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW',
'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED',
'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED',
'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', 'DCN_BASE',
'DCN_BASE__INST0_SEG0', 'DCN_BASE__INST0_SEG1',
'DCN_BASE__INST0_SEG2', 'DCN_BASE__INST0_SEG3',
'DCN_BASE__INST0_SEG4', 'DCN_BASE__INST1_SEG0',
'DCN_BASE__INST1_SEG1', 'DCN_BASE__INST1_SEG2',
'DCN_BASE__INST1_SEG3', 'DCN_BASE__INST1_SEG4',
'DCN_BASE__INST2_SEG0', 'DCN_BASE__INST2_SEG1',
'DCN_BASE__INST2_SEG2', 'DCN_BASE__INST2_SEG3',
'DCN_BASE__INST2_SEG4', 'DCN_BASE__INST3_SEG0',
'DCN_BASE__INST3_SEG1', 'DCN_BASE__INST3_SEG2',
'DCN_BASE__INST3_SEG3', 'DCN_BASE__INST3_SEG4',
'DCN_BASE__INST4_SEG0', 'DCN_BASE__INST4_SEG1',
'DCN_BASE__INST4_SEG2', 'DCN_BASE__INST4_SEG3',
'DCN_BASE__INST4_SEG4', 'DCN_BASE__INST5_SEG0',
'DCN_BASE__INST5_SEG1', 'DCN_BASE__INST5_SEG2',
'DCN_BASE__INST5_SEG3', 'DCN_BASE__INST5_SEG4',
'DCN_BASE__INST6_SEG0', 'DCN_BASE__INST6_SEG1',
'DCN_BASE__INST6_SEG2', 'DCN_BASE__INST6_SEG3',
'DCN_BASE__INST6_SEG4', 'DC_DMCUB_INT_TYPE',
'DC_DMCUB_TIMER_WINDOW', 'DC_MEM_GLOBAL_PWR_REQ_DIS',
'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE',
'DC_SMU_INTERRUPT_ENABLE', 'DDID_VMID_CNTL', 'DDID_VMID_PIPE',
'DEBUG_BUS_SELECT_ABM0', 'DEBUG_BUS_SELECT_ABM1',
'DEBUG_BUS_SELECT_ABM2', 'DEBUG_BUS_SELECT_ABM3',
'DEBUG_BUS_SELECT_ABM_RESERVED0',
'DEBUG_BUS_SELECT_ABM_RESERVED1', 'DEBUG_BUS_SELECT_DPG0',
'DEBUG_BUS_SELECT_DPG1', 'DEBUG_BUS_SELECT_DPG2',
'DEBUG_BUS_SELECT_DPG3', 'DEBUG_BUS_SELECT_DPG_RESERVED0',
'DEBUG_BUS_SELECT_DPG_RESERVED1', 'DEBUG_BUS_SELECT_FMT0',
'DEBUG_BUS_SELECT_FMT1', 'DEBUG_BUS_SELECT_FMT2',
'DEBUG_BUS_SELECT_FMT3', 'DEBUG_BUS_SELECT_FMT_RESERVED0',
'DEBUG_BUS_SELECT_FMT_RESERVED1', 'DEBUG_BUS_SELECT_OPPBUF0',
'DEBUG_BUS_SELECT_OPPBUF1', 'DEBUG_BUS_SELECT_OPPBUF2',
'DEBUG_BUS_SELECT_OPPBUF3', 'DEBUG_BUS_SELECT_OPPBUF_RESERVED0',
'DEBUG_BUS_SELECT_OPPBUF_RESERVED1', 'DEBUG_BUS_SELECT_OPP_PIPE0',
'DEBUG_BUS_SELECT_OPP_PIPE1', 'DEBUG_BUS_SELECT_OPP_PIPE2',
'DEBUG_BUS_SELECT_OPP_PIPE3',
'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0',
'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1', 'DECERR',
'DENORM_TRUNCATE', 'DETILE_BUFFER_PACKER_ENABLE',
'DETILE_BUFFER_PACKER_IS_DISABLE',
'DETILE_BUFFER_PACKER_IS_ENABLE', 'DFQ_MIN_FREE_ENTRIES',
'DFQ_MIN_FREE_ENTRIES_0', 'DFQ_MIN_FREE_ENTRIES_1',
'DFQ_MIN_FREE_ENTRIES_2', 'DFQ_MIN_FREE_ENTRIES_3',
'DFQ_MIN_FREE_ENTRIES_4', 'DFQ_MIN_FREE_ENTRIES_5',
'DFQ_MIN_FREE_ENTRIES_6', 'DFQ_MIN_FREE_ENTRIES_7',
'DFQ_NUM_ENTRIES', 'DFQ_NUM_ENTRIES_0', 'DFQ_NUM_ENTRIES_1',
'DFQ_NUM_ENTRIES_2', 'DFQ_NUM_ENTRIES_3', 'DFQ_NUM_ENTRIES_4',
'DFQ_NUM_ENTRIES_5', 'DFQ_NUM_ENTRIES_6', 'DFQ_NUM_ENTRIES_7',
'DFQ_NUM_ENTRIES_8', 'DFQ_SIZE', 'DFQ_SIZE_0', 'DFQ_SIZE_1',
'DFQ_SIZE_2', 'DFQ_SIZE_3', 'DFQ_SIZE_4', 'DFQ_SIZE_5',
'DFQ_SIZE_6', 'DFQ_SIZE_7', 'DFSMFlushEvents', 'DF_BASE',
'DF_BASE__INST0_SEG0', 'DF_BASE__INST0_SEG1',
'DF_BASE__INST0_SEG2', 'DF_BASE__INST0_SEG3',
'DF_BASE__INST0_SEG4', 'DF_BASE__INST1_SEG0',
'DF_BASE__INST1_SEG1', 'DF_BASE__INST1_SEG2',
'DF_BASE__INST1_SEG3', 'DF_BASE__INST1_SEG4',
'DF_BASE__INST2_SEG0', 'DF_BASE__INST2_SEG1',
'DF_BASE__INST2_SEG2', 'DF_BASE__INST2_SEG3',
'DF_BASE__INST2_SEG4', 'DF_BASE__INST3_SEG0',
'DF_BASE__INST3_SEG1', 'DF_BASE__INST3_SEG2',
'DF_BASE__INST3_SEG3', 'DF_BASE__INST3_SEG4',
'DF_BASE__INST4_SEG0', 'DF_BASE__INST4_SEG1',
'DF_BASE__INST4_SEG2', 'DF_BASE__INST4_SEG3',
'DF_BASE__INST4_SEG4', 'DF_BASE__INST5_SEG0',
'DF_BASE__INST5_SEG1', 'DF_BASE__INST5_SEG2',
'DF_BASE__INST5_SEG3', 'DF_BASE__INST5_SEG4',
'DF_BASE__INST6_SEG0', 'DF_BASE__INST6_SEG1',
'DF_BASE__INST6_SEG2', 'DF_BASE__INST6_SEG3',
'DF_BASE__INST6_SEG4', 'DIFFERENT_RGB', 'DIG_10BIT_TEST_PATTERN',
'DIG_ALL_PIXEL', 'DIG_ALTERNATING_TEST_PATTERN',
'DIG_BE_CNTL_HPD1', 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3',
'DIG_BE_CNTL_HPD4', 'DIG_BE_CNTL_HPD5', 'DIG_BE_CNTL_HPD_SELECT',
'DIG_BE_CNTL_MODE', 'DIG_BE_CNTL_NO_HPD', 'DIG_BE_DP_MST_MODE',
'DIG_BE_DP_SST_MODE', 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2',
'DIG_BE_RESERVED3', 'DIG_BE_RESERVED4', 'DIG_BE_TMDS_DVI_MODE',
'DIG_BE_TMDS_HDMI_MODE', 'DIG_DIGITAL_BYPASS_ENABLE',
'DIG_DIGITAL_BYPASS_OFF', 'DIG_DIGITAL_BYPASS_ON',
'DIG_DIGITAL_BYPASS_SEL', 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB',
'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB',
'DIG_DIGITAL_BYPASS_SEL_36BPP',
'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB',
'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB',
'DIG_DIGITAL_BYPASS_SEL_ALPHA', 'DIG_DIGITAL_BYPASS_SEL_BYPASS',
'DIG_EVEN_PIXEL_ONLY', 'DIG_FE_CNTL_SOURCE_SELECT',
'DIG_FE_CNTL_STEREOSYNC_SELECT', 'DIG_FE_SOURCE_FROM_OTG0',
'DIG_FE_SOURCE_FROM_OTG1', 'DIG_FE_SOURCE_FROM_OTG2',
'DIG_FE_SOURCE_FROM_OTG3', 'DIG_FE_SOURCE_RESERVED',
'DIG_FE_STEREOSYNC_FROM_OTG0', 'DIG_FE_STEREOSYNC_FROM_OTG1',
'DIG_FE_STEREOSYNC_FROM_OTG2', 'DIG_FE_STEREOSYNC_FROM_OTG3',
'DIG_FE_STEREOSYNC_RESERVED', 'DIG_FIFO_1_PIX_PER_CYCLE',
'DIG_FIFO_2_PIX_PER_CYCLE', 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX',
'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL',
'DIG_FIFO_FORCE_RECAL_AVERAGE',
'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL',
'DIG_FIFO_FORCE_RECOMP_MINMAX',
'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE',
'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_NO_ERROR_OCCURRED',
'DIG_FIFO_OUTPUT_PROCESSING_MODE', 'DIG_FIFO_OVERFLOW_OCCURRED',
'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR', 'DIG_FIFO_READ_CLOCK_SRC',
'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG',
'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE',
'DIG_FIFO_UNDERFLOW_OCCURRED', 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL',
'DIG_FIFO_USE_OVERWRITE_LEVEL', 'DIG_INPUT_PIXEL_SEL',
'DIG_IN_DEBUG_MODE', 'DIG_IN_NORMAL_OPERATION',
'DIG_ODD_PIXEL_ONLY', 'DIG_OUTPUT_CRC_CNTL_LINK_SEL',
'DIG_OUTPUT_CRC_DATA_SEL', 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY',
'DIG_OUTPUT_CRC_FOR_AUDIO', 'DIG_OUTPUT_CRC_FOR_FULLFRAME',
'DIG_OUTPUT_CRC_FOR_VBI', 'DIG_OUTPUT_CRC_ON_LINK0',
'DIG_OUTPUT_CRC_ON_LINK1', 'DIG_PAIR_PIXELS',
'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED',
'DIG_RANDOM_PATTERN_SEED_RAN_PAT',
'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS',
'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', 'DIG_SINGLETON_PIXELS',
'DIG_SL_PIXEL_GROUPING',
'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG',
'DIG_TEST_PATTERN_EXTERNAL_RESET_EN',
'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE',
'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL',
'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM',
'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN',
'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET',
'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', 'DIG_UPDATE_EYE_SEL_BOTH',
'DIG_UPDATE_EYE_SEL_LEFT', 'DIG_UPDATE_EYE_SEL_RIGHT',
'DIG_UPDATE_FIELD_SEL_BOTH', 'DIG_UPDATE_FIELD_SEL_BOTTOM',
'DIG_UPDATE_FIELD_SEL_RESERVED', 'DIG_UPDATE_FIELD_SEL_TOP',
'DIOMEM_DISABLE_MEM_PWR_CTRL', 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN',
'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE',
'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN',
'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE',
'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', 'DIOMEM_ENABLE_MEM_PWR_CTRL',
'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', 'DIOMEM_FORCE_LIGHT_SLEEP_REQ',
'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST',
'DIOMEM_FORCE_SHUT_DOWN_REQUEST', 'DIOMEM_NO_FORCE_REQ',
'DIOMEM_NO_FORCE_REQUEST', 'DIOMEM_PWR_DIS_CTRL',
'DIOMEM_PWR_FORCE_CTRL', 'DIOMEM_PWR_FORCE_CTRL2',
'DIOMEM_PWR_SEL_CTRL', 'DIOMEM_PWR_SEL_CTRL2', 'DIO_BASE',
'DIO_BASE__INST0_SEG0', 'DIO_BASE__INST0_SEG1',
'DIO_BASE__INST0_SEG2', 'DIO_BASE__INST0_SEG3',
'DIO_BASE__INST0_SEG4', 'DIO_BASE__INST1_SEG0',
'DIO_BASE__INST1_SEG1', 'DIO_BASE__INST1_SEG2',
'DIO_BASE__INST1_SEG3', 'DIO_BASE__INST1_SEG4',
'DIO_BASE__INST2_SEG0', 'DIO_BASE__INST2_SEG1',
'DIO_BASE__INST2_SEG2', 'DIO_BASE__INST2_SEG3',
'DIO_BASE__INST2_SEG4', 'DIO_BASE__INST3_SEG0',
'DIO_BASE__INST3_SEG1', 'DIO_BASE__INST3_SEG2',
'DIO_BASE__INST3_SEG3', 'DIO_BASE__INST3_SEG4',
'DIO_BASE__INST4_SEG0', 'DIO_BASE__INST4_SEG1',
'DIO_BASE__INST4_SEG2', 'DIO_BASE__INST4_SEG3',
'DIO_BASE__INST4_SEG4', 'DIO_BASE__INST5_SEG0',
'DIO_BASE__INST5_SEG1', 'DIO_BASE__INST5_SEG2',
'DIO_BASE__INST5_SEG3', 'DIO_BASE__INST5_SEG4',
'DIO_BASE__INST6_SEG0', 'DIO_BASE__INST6_SEG1',
'DIO_BASE__INST6_SEG2', 'DIO_BASE__INST6_SEG3',
'DIO_BASE__INST6_SEG4', 'DIO_DBG_BLOCK_SEL',
'DIO_DBG_BLOCK_SEL_AUX0', 'DIO_DBG_BLOCK_SEL_AUX1',
'DIO_DBG_BLOCK_SEL_AUX2', 'DIO_DBG_BLOCK_SEL_AUX3',
'DIO_DBG_BLOCK_SEL_AUX4', 'DIO_DBG_BLOCK_SEL_DIGA',
'DIO_DBG_BLOCK_SEL_DIGB', 'DIO_DBG_BLOCK_SEL_DIGC',
'DIO_DBG_BLOCK_SEL_DIGD', 'DIO_DBG_BLOCK_SEL_DIGE',
'DIO_DBG_BLOCK_SEL_DIGFE_A', 'DIO_DBG_BLOCK_SEL_DIGFE_B',
'DIO_DBG_BLOCK_SEL_DIGFE_C', 'DIO_DBG_BLOCK_SEL_DIGFE_D',
'DIO_DBG_BLOCK_SEL_DIGFE_E', 'DIO_DBG_BLOCK_SEL_DIO',
'DIO_DBG_BLOCK_SEL_DPA', 'DIO_DBG_BLOCK_SEL_DPB',
'DIO_DBG_BLOCK_SEL_DPC', 'DIO_DBG_BLOCK_SEL_DPD',
'DIO_DBG_BLOCK_SEL_DPE', 'DIO_DBG_BLOCK_SEL_DPFE_A',
'DIO_DBG_BLOCK_SEL_DPFE_B', 'DIO_DBG_BLOCK_SEL_DPFE_C',
'DIO_DBG_BLOCK_SEL_DPFE_D', 'DIO_DBG_BLOCK_SEL_DPFE_E',
'DIO_DBG_BLOCK_SEL_PERFMON_DIO', 'DIO_DBG_BLOCK_SEL_RESERVED',
'DIO_FIFO_ERROR', 'DIO_FIFO_ERROR_00', 'DIO_FIFO_ERROR_01',
'DIO_FIFO_ERROR_10', 'DIO_FIFO_ERROR_11',
'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE',
'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL',
'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE',
'DISABLE_BINNING_USE_LEGACY_SC', 'DISABLE_BINNING_USE_NEW_SC',
'DISABLE_CLOCK_GATING', 'DISABLE_CLOCK_GATING_IN_DCO',
'DISABLE_DEBUG', 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL',
'DISABLE_PWL', 'DISABLE_TF0_OPT', 'DISABLE_TF1_OPT',
'DISABLE_THE_FEATURE', 'DISABLE_THE_INTERRUPT',
'DISPCLK_CHG_FWD_CORR_DISABLE',
'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING',
'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING',
'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE',
'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DIVISOR_BY1',
'DIVISOR_BY2_RESERVED', 'DIVISOR_BY3', 'DIVISOR_BY4_RESERVED',
'DIVISOR_BY5_RESERVED', 'DIVISOR_BY6_RESERVED',
'DIVISOR_BY7_RESERVED', 'DIVISOR_BY8_RESERVED', 'DIV_2', 'DIV_4',
'DIV_8', 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT',
'DI_INDEX_SIZE_8_BIT', 'DI_MAJOR_MODE_0', 'DI_MAJOR_MODE_1',
'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', 'DI_PT_LINELIST_ADJ',
'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ',
'DI_PT_NONE', 'DI_PT_PATCH', 'DI_PT_POINTLIST', 'DI_PT_POLYGON',
'DI_PT_QUADLIST', 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST',
'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ',
'DI_PT_TRISTRIP', 'DI_PT_TRISTRIP_ADJ', 'DI_PT_UNUSED_1',
'DI_PT_UNUSED_3', 'DI_PT_UNUSED_4', 'DI_PT_UNUSED_5',
'DI_SRC_SEL_AUTO_INDEX', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE',
'DI_SRC_SEL_RESERVED',
'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE',
'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE',
'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE',
'DMDATA_CLEAR_UNDERFLOW_STATUS', 'DMDATA_DONE',
'DMDATA_DONT_CLEAR', 'DMDATA_HARDWARE_UPDATE_MODE', 'DMDATA_MODE',
'DMDATA_NOT_SENT_TO_DIG', 'DMDATA_NOT_UNDERFLOW',
'DMDATA_NOT_UPDATED', 'DMDATA_QOS_LEVEL_FROM_SOFTWARE',
'DMDATA_QOS_LEVEL_FROM_TTU', 'DMDATA_QOS_MODE', 'DMDATA_REPEAT',
'DMDATA_SENT_TO_DIG', 'DMDATA_SOFTWARE_UPDATE_MODE',
'DMDATA_UNDERFLOW', 'DMDATA_UNDERFLOWED',
'DMDATA_UNDERFLOW_CLEAR', 'DMDATA_UPDATED',
'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES',
'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', 'DMDATA_VM_DONE',
'DMDATA_VM_IS_DONE', 'DMDATA_VM_IS_NOT_DONE',
'DMDATA_WAS_UPDATED', 'DME_MEM_DISABLE_MEM_PWR_CTRL',
'DME_MEM_ENABLE_MEM_PWR_CTRL', 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST',
'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST',
'DME_MEM_FORCE_SHUT_DOWN_REQUEST', 'DME_MEM_NO_FORCE_REQUEST',
'DME_MEM_POWER_STATE_ENUM', 'DME_MEM_POWER_STATE_ENUM_DS',
'DME_MEM_POWER_STATE_ENUM_LS', 'DME_MEM_POWER_STATE_ENUM_ON',
'DME_MEM_POWER_STATE_ENUM_SD', 'DME_MEM_PWR_DIS_CTRL',
'DME_MEM_PWR_FORCE_CTRL', 'DMU_CLOCK_ON', 'DMU_CLOCK_STATUS_OFF',
'DMU_CLOCK_STATUS_ON', 'DMU_DC_GPU_TIMER_READ_SELECT',
'DMU_DC_GPU_TIMER_START_POSITION',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6',
'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7',
'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71',
'DMU_GPU_TIMER_START_0_END_27', 'DMU_GPU_TIMER_START_10_END_37',
'DMU_GPU_TIMER_START_1_END_28', 'DMU_GPU_TIMER_START_2_END_29',
'DMU_GPU_TIMER_START_3_END_30', 'DMU_GPU_TIMER_START_4_END_31',
'DMU_GPU_TIMER_START_6_END_33', 'DMU_GPU_TIMER_START_8_END_35',
'DOLBY_VISION_DISABLED', 'DOLBY_VISION_ENABLE',
'DOLBY_VISION_ENABLED', 'DONUTS', 'DOUT_I2C_ACK',
'DOUT_I2C_ACK_TO_CLEAN',
'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER',
'DOUT_I2C_ARBITRATION_ABORT_XFER',
'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG',
'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG',
'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG',
'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER',
'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO',
'DOUT_I2C_ARBITRATION_SW_PRIORITY',
'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED',
'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED',
'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH',
'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL',
'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED',
'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED',
'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ',
'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ',
'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ',
'DOUT_I2C_CONTROL_DBG_REF_SEL', 'DOUT_I2C_CONTROL_DDC_SELECT',
'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', 'DOUT_I2C_CONTROL_GO',
'DOUT_I2C_CONTROL_NORMAL_DEBUG',
'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER',
'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS',
'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER',
'DOUT_I2C_CONTROL_RESET_SW_STATUS',
'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2',
'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4',
'DOUT_I2C_CONTROL_SELECT_DDC5', 'DOUT_I2C_CONTROL_SELECT_DDCVGA',
'DOUT_I2C_CONTROL_SEND_RESET',
'DOUT_I2C_CONTROL_SEND_RESET_LENGTH',
'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER',
'DOUT_I2C_CONTROL_STOP_TRANSFER',
'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0',
'DOUT_I2C_CONTROL_TRANS0_TRANS1',
'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2',
'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3',
'DOUT_I2C_CONTROL_TRANSACTION_COUNT',
'DOUT_I2C_CONTROL__NOT_SEND_RESET',
'DOUT_I2C_CONTROL__SEND_RESET',
'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10',
'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9',
'DOUT_I2C_DATA_INDEX_WRITE', 'DOUT_I2C_DATA__INDEX_WRITE',
'DOUT_I2C_DATA__NOT_INDEX_WRITE',
'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR',
'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS',
'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL',
'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT',
'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT',
'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE',
'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL',
'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA',
'DOUT_I2C_DDC_SPEED_THRESHOLD',
'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO',
'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE',
'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE',
'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE',
'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET',
'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION',
'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION',
'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE',
'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL',
'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE',
'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS',
'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS',
'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DPCS_BASE',
'DPCS_BASE__INST0_SEG0', 'DPCS_BASE__INST0_SEG1',
'DPCS_BASE__INST0_SEG2', 'DPCS_BASE__INST0_SEG3',
'DPCS_BASE__INST0_SEG4', 'DPCS_BASE__INST1_SEG0',
'DPCS_BASE__INST1_SEG1', 'DPCS_BASE__INST1_SEG2',
'DPCS_BASE__INST1_SEG3', 'DPCS_BASE__INST1_SEG4',
'DPCS_BASE__INST2_SEG0', 'DPCS_BASE__INST2_SEG1',
'DPCS_BASE__INST2_SEG2', 'DPCS_BASE__INST2_SEG3',
'DPCS_BASE__INST2_SEG4', 'DPCS_BASE__INST3_SEG0',
'DPCS_BASE__INST3_SEG1', 'DPCS_BASE__INST3_SEG2',
'DPCS_BASE__INST3_SEG3', 'DPCS_BASE__INST3_SEG4',
'DPCS_BASE__INST4_SEG0', 'DPCS_BASE__INST4_SEG1',
'DPCS_BASE__INST4_SEG2', 'DPCS_BASE__INST4_SEG3',
'DPCS_BASE__INST4_SEG4', 'DPCS_BASE__INST5_SEG0',
'DPCS_BASE__INST5_SEG1', 'DPCS_BASE__INST5_SEG2',
'DPCS_BASE__INST5_SEG3', 'DPCS_BASE__INST5_SEG4',
'DPCS_BASE__INST6_SEG0', 'DPCS_BASE__INST6_SEG1',
'DPCS_BASE__INST6_SEG2', 'DPCS_BASE__INST6_SEG3',
'DPCS_BASE__INST6_SEG4', 'DPHY_8B10B_CUR_DISP',
'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO',
'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET',
'DPHY_8B10B_RESETET',
'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION',
'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE',
'DPHY_ALT_SCRAMBLER_RESET_EN', 'DPHY_ALT_SCRAMBLER_RESET_SEL',
'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE',
'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE',
'DPHY_ATEST_LANE0_PRBS_PATTERN', 'DPHY_ATEST_LANE0_REG_PATTERN',
'DPHY_ATEST_LANE1_PRBS_PATTERN', 'DPHY_ATEST_LANE1_REG_PATTERN',
'DPHY_ATEST_LANE2_PRBS_PATTERN', 'DPHY_ATEST_LANE2_REG_PATTERN',
'DPHY_ATEST_LANE3_PRBS_PATTERN', 'DPHY_ATEST_LANE3_REG_PATTERN',
'DPHY_ATEST_SEL_LANE0', 'DPHY_ATEST_SEL_LANE1',
'DPHY_ATEST_SEL_LANE2', 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS',
'DPHY_CRC_CONTINUOUS', 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED',
'DPHY_CRC_EN', 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD',
'DPHY_CRC_LANE0_SELECTED', 'DPHY_CRC_LANE1_SELECTED',
'DPHY_CRC_LANE2_SELECTED', 'DPHY_CRC_LANE3_SELECTED',
'DPHY_CRC_MST_PHASE_ERROR_ACK', 'DPHY_CRC_MST_PHASE_ERROR_ACKED',
'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT',
'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD',
'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT',
'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY',
'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0',
'DPHY_FEC_ACTIVE', 'DPHY_FEC_DISABLED', 'DPHY_FEC_ENABLE',
'DPHY_FEC_ENABLED', 'DPHY_FEC_NOT_ACTIVE', 'DPHY_FEC_READY',
'DPHY_FEC_READY_DIS', 'DPHY_FEC_READY_EN',
'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START',
'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW',
'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED',
'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN',
'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL',
'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SCRAMBLER_ADVANCE',
'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL',
'DPHY_SCRAMBLER_DIS', 'DPHY_SCRAMBLER_KCODE',
'DPHY_SCRAMBLER_KCODE_DISABLED', 'DPHY_SCRAMBLER_KCODE_ENABLED',
'DPHY_SCRAMBLER_SEL', 'DPHY_SCRAMBLER_SEL_DBG_DATA',
'DPHY_SCRAMBLER_SEL_LANE_DATA', 'DPHY_SCR_DISABLED',
'DPHY_SCR_ENABLED', 'DPHY_SKEW_BYPASS',
'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM',
'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET',
'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET',
'DPHY_SW_FAST_TRAINING_NOT_STARTED',
'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED',
'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2',
'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4',
'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL',
'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL',
'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL',
'DPTE_GROUP_SIZE', 'DPTE_GROUP_SIZE_1024B',
'DPTE_GROUP_SIZE_128B', 'DPTE_GROUP_SIZE_2048B',
'DPTE_GROUP_SIZE_256B', 'DPTE_GROUP_SIZE_512B',
'DPTE_GROUP_SIZE_64B', 'DP_128B132B',
'DP_AUX_ARB_CONTROL_ARB_PRIORITY',
'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW',
'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW',
'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS',
'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC',
'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG',
'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ',
'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG',
'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG',
'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ',
'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', 'DP_AUX_ARB_STATUS',
'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED',
'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED',
'DP_AUX_CONTROL_HPD5_SELECTED', 'DP_AUX_CONTROL_HPD_SEL',
'DP_AUX_CONTROL_NO_HPD_SELECTED', 'DP_AUX_CONTROL_TEST_MODE',
'DP_AUX_CONTROL_TEST_MODE_DISABLE',
'DP_AUX_CONTROL_TEST_MODE_ENABLE',
'DP_AUX_DEFINITE_ERR_REACHED_ACK',
'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START',
'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES',
'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS',
'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD',
'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD',
'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START',
'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP',
'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT',
'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START',
'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64',
'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US',
'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK',
'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF',
'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK',
'DP_AUX_ERR_OCCURRED__NOT_ACK',
'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX',
'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ',
'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US',
'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS',
'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256',
'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64',
'DP_AUX_IDLE', 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK',
'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK',
'DP_AUX_INT__NOT_ACK', 'DP_AUX_IN_USE_GTC', 'DP_AUX_IN_USE_LS',
'DP_AUX_IN_USE_PHYWAKE', 'DP_AUX_IN_USE_SW',
'DP_AUX_LS_UPDATE_ACK', 'DP_AUX_PHY_WAKE_HIGH_PRIORITY',
'DP_AUX_PHY_WAKE_LOW_PRIORITY', 'DP_AUX_PHY_WAKE_PRIORITY',
'DP_AUX_POTENTIAL_ERR_REACHED_ACK',
'DP_AUX_POTENTIAL_ERR_REACHED__ACK',
'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET',
'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED',
'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE',
'DP_AUX_RESET_SEQUENCE_NOT_DONE', 'DP_AUX_RX_TIMEOUT_LEN_MUL',
'DP_AUX_RX_TIMEOUT_LEN_MUL_2', 'DP_AUX_RX_TIMEOUT_LEN_MUL_4',
'DP_AUX_RX_TIMEOUT_LEN_MUL_8', 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL',
'DP_AUX_SW_CONTROL_LS_READ_TRIG',
'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG',
'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO',
'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO',
'DP_AUX_TX_PRECHARGE_LEN_MUL', 'DP_AUX_TX_PRECHARGE_LEN_MUL_2',
'DP_AUX_TX_PRECHARGE_LEN_MUL_4', 'DP_AUX_TX_PRECHARGE_LEN_MUL_8',
'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', 'DP_COMPONENT_DEPTH',
'DP_COMPONENT_DEPTH_10BPC', 'DP_COMPONENT_DEPTH_12BPC',
'DP_COMPONENT_DEPTH_16BPC', 'DP_COMPONENT_DEPTH_6BPC',
'DP_COMPONENT_DEPTH_8BPC', 'DP_CP_ENCRYPTION_TYPE',
'DP_CP_ENCRYPTION_TYPE_0', 'DP_CP_ENCRYPTION_TYPE_1',
'DP_DPHY_8B10B_EXT_DISP', 'DP_DPHY_8B10B_EXT_DISP_ONE',
'DP_DPHY_8B10B_EXT_DISP_ZERO',
'DP_DPHY_FAST_TRAINING_COMPLETE_ACK',
'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED',
'DP_DPHY_FAST_TRAINING_COMPLETE_MASK',
'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED',
'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED',
'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED',
'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED',
'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN',
'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED',
'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1',
'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS',
'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE',
'DP_DPHY_SYM32_1LANE', 'DP_DPHY_SYM32_2LANE',
'DP_DPHY_SYM32_4LANE', 'DP_DPHY_SYM32_ACTIVE',
'DP_DPHY_SYM32_CRC_END_LLCP', 'DP_DPHY_SYM32_CRC_END_PS_ANY',
'DP_DPHY_SYM32_CRC_END_PS_LT_SR', 'DP_DPHY_SYM32_CRC_END_PS_ONLY',
'DP_DPHY_SYM32_CRC_START_LLCP',
'DP_DPHY_SYM32_CRC_START_PS_LT_SR',
'DP_DPHY_SYM32_CRC_START_PS_ONLY',
'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR',
'DP_DPHY_SYM32_CRC_START_TP_START',
'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER',
'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER',
'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX',
'DP_DPHY_SYM32_CRC_USE_END_EVENT',
'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', 'DP_DPHY_SYM32_DISABLE',
'DP_DPHY_SYM32_ENABLE', 'DP_DPHY_SYM32_ENCRYPT_TYPE0',
'DP_DPHY_SYM32_ENCRYPT_TYPE1', 'DP_DPHY_SYM32_LT_TPS1',
'DP_DPHY_SYM32_LT_TPS2', 'DP_DPHY_SYM32_NOT_RESET',
'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING',
'DP_DPHY_SYM32_RATE_UPDATE_PENDING', 'DP_DPHY_SYM32_RESERVED',
'DP_DPHY_SYM32_RESET', 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED',
'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED',
'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE',
'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING',
'DP_DPHY_SYM32_SAT_NO_UPDATE',
'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING',
'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE',
'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING',
'DP_DPHY_SYM32_STATUS_ENABLED', 'DP_DPHY_SYM32_STATUS_IDLE',
'DP_DPHY_SYM32_STREAM_OVR_ALWAYS',
'DP_DPHY_SYM32_STREAM_OVR_NONE',
'DP_DPHY_SYM32_STREAM_OVR_REPLACE',
'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL',
'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', 'DP_DPHY_SYM32_TEST',
'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11',
'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15',
'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23',
'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31',
'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7',
'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9',
'DP_DPHY_SYM32_TP_SELECT_CUSTOM', 'DP_DPHY_SYM32_TP_SELECT_PRBS',
'DP_DPHY_SYM32_TP_SELECT_SQUARE', 'DP_DPHY_SYM32_TP_SELECT_TPS1',
'DP_DPHY_SYM32_TP_SELECT_TPS2', 'DP_DSC_444_SIMPLE_422',
'DP_DSC_DISABLE', 'DP_DSC_MODE', 'DP_DSC_NATIVE_422_420',
'DP_DTO_DESPREAD_DISABLE', 'DP_DTO_DESPREAD_ENABLE',
'DP_DTO_DS_DISABLE', 'DP_EMBEDDED_PANEL',
'DP_EMBEDDED_PANEL_MODE', 'DP_EXTERNAL_PANEL',
'DP_LINK_TRAINING_ALREADY_COMPLETE', 'DP_LINK_TRAINING_COMPLETE',
'DP_LINK_TRAINING_NOT_COMPLETE', 'DP_LINK_TRAINING_SWITCH_MODE',
'DP_LINK_TRAINING_SWITCH_TO_IDLE',
'DP_LINK_TRAINING_SWITCH_TO_VIDEO', 'DP_ML_PHY_SEQ_IMMEDIATE',
'DP_ML_PHY_SEQ_LINE_NUM', 'DP_ML_PHY_SEQ_MODE',
'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE',
'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED',
'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG',
'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG',
'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER',
'DP_MSE_SAT_ENCRYPT0', 'DP_MSE_SAT_ENCRYPT0_DISABLED',
'DP_MSE_SAT_ENCRYPT0_ENABLED', 'DP_MSE_SAT_ENCRYPT1',
'DP_MSE_SAT_ENCRYPT1_DISABLED', 'DP_MSE_SAT_ENCRYPT1_ENABLED',
'DP_MSE_SAT_ENCRYPT2', 'DP_MSE_SAT_ENCRYPT2_DISABLED',
'DP_MSE_SAT_ENCRYPT2_ENABLED', 'DP_MSE_SAT_ENCRYPT3',
'DP_MSE_SAT_ENCRYPT3_DISABLED', 'DP_MSE_SAT_ENCRYPT3_ENABLED',
'DP_MSE_SAT_ENCRYPT4', 'DP_MSE_SAT_ENCRYPT4_DISABLED',
'DP_MSE_SAT_ENCRYPT4_ENABLED', 'DP_MSE_SAT_ENCRYPT5',
'DP_MSE_SAT_ENCRYPT5_DISABLED', 'DP_MSE_SAT_ENCRYPT5_ENABLED',
'DP_MSE_SAT_UPDATE_ACT', 'DP_MSE_SAT_UPDATE_NO_ACTION',
'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER',
'DP_MSE_SAT_UPDATE_WITH_TRIGGER',
'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE',
'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE',
'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER',
'DP_MSO_FOUR_SSTLINK', 'DP_MSO_NUM_OF_SST_LINKS',
'DP_MSO_ONE_SSTLINK', 'DP_MSO_TWO_SSTLINK',
'DP_ONE_PIXEL_PER_CYCLE', 'DP_PIXEL_ENCODING',
'DP_PIXEL_ENCODING_RGB444', 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT',
'DP_PIXEL_ENCODING_YCBCR420', 'DP_PIXEL_ENCODING_YCBCR422',
'DP_PIXEL_ENCODING_YCBCR444', 'DP_PIXEL_ENCODING_Y_ONLY',
'DP_PIXEL_PER_CYCLE_PROCESSING_NUM',
'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ',
'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE',
'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED',
'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY',
'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE',
'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL',
'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG',
'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY',
'DP_SEC_GSP_SEND', 'DP_SEC_GSP_SEND_ANY_LINE',
'DP_SEC_GSP_SEND_PPS', 'DP_SEC_LINE_REFERENCE',
'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', 'DP_SEC_TIMESTAMP_MODE',
'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 'DP_STEER_OVERFLOW_ACK',
'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT',
'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK',
'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK',
'DP_STREAM_ENC_DCCG', 'DP_STREAM_ENC_DISPLAY_PIPE',
'DP_STREAM_ENC_HARDWARE', 'DP_STREAM_ENC_NOT_RESET',
'DP_STREAM_ENC_NO_ERROR_OCCURRED',
'DP_STREAM_ENC_OVERFLOW_OCCURRED',
'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR',
'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT',
'DP_STREAM_ENC_PROGRAMMABLE', 'DP_STREAM_ENC_READ_CLOCK_CONTROL',
'DP_STREAM_ENC_RESET', 'DP_STREAM_ENC_RESET_CONTROL',
'DP_STREAM_ENC_STREAM_ACTIVE', 'DP_STREAM_ENC_UNDERFLOW_OCCURRED',
'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE',
'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE',
'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET',
'DP_STREAM_MAPPER_LINK0', 'DP_STREAM_MAPPER_LINK1',
'DP_STREAM_MAPPER_RESERVED', 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC',
'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC',
'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC',
'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC',
'DP_SYM32_ENC_COMPRESSED_FORMAT', 'DP_SYM32_ENC_CONTINUOUS_MODE',
'DP_SYM32_ENC_CRC_NOT_VALID', 'DP_SYM32_ENC_CRC_VALID',
'DP_SYM32_ENC_DISABLE', 'DP_SYM32_ENC_DP_SOF',
'DP_SYM32_ENC_ENABLE', 'DP_SYM32_ENC_GSP_DEADLINE_MISSED',
'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED',
'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128',
'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32',
'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0',
'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1',
'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME',
'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER',
'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING',
'DP_SYM32_ENC_GSP_TRIGGER_PENDING',
'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST',
'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST',
'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST',
'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST',
'DP_SYM32_ENC_NOT_PENDING', 'DP_SYM32_ENC_NOT_RESET',
'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', 'DP_SYM32_ENC_ONE_SHOT_MODE',
'DP_SYM32_ENC_OTG_SOF', 'DP_SYM32_ENC_OVERFLOW_OCCURRED',
'DP_SYM32_ENC_PENDING',
'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444',
'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420',
'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422',
'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY',
'DP_SYM32_ENC_POWER_STATE_ENUM_DS',
'DP_SYM32_ENC_POWER_STATE_ENUM_LS',
'DP_SYM32_ENC_POWER_STATE_ENUM_ON',
'DP_SYM32_ENC_POWER_STATE_ENUM_SD', 'DP_SYM32_ENC_RESET',
'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED',
'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED',
'DP_SYM32_ENC_SDP_HIGH_PRIORITY', 'DP_SYM32_ENC_SDP_LOW_PRIORITY',
'DP_SYM32_ENC_UNCOMPRESSED_FORMAT',
'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK',
'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK',
'DP_SYM32_ENC_VID_STREAM_NO_DEFER', 'DP_SYNC_POLARITY',
'DP_SYNC_POLARITY_ACTIVE_HIGH', 'DP_SYNC_POLARITY_ACTIVE_LOW',
'DP_TU_OVERFLOW_ACK', 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT',
'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_TWO_PIXEL_PER_CYCLE',
'DP_UDI_1_LANE', 'DP_UDI_2_LANES', 'DP_UDI_4_LANES',
'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED',
'DP_VID_ENHANCED_FRAME_MODE', 'DP_VID_M_1X_INPUT_PIXEL_RATE',
'DP_VID_M_2X_INPUT_PIXEL_RATE', 'DP_VID_M_4X_INPUT_PIXEL_RATE',
'DP_VID_M_8X_INPUT_PIXEL_RATE', 'DP_VID_M_N_CALC_AUTO',
'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE',
'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START',
'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN',
'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_N_MUL',
'DP_VID_STREAM_DISABLE_ACK', 'DP_VID_STREAM_DISABLE_MASK',
'DP_VID_STREAM_DIS_DEFER', 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK',
'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER',
'DP_VID_VBID_FIELD_POL', 'DP_VID_VBID_FIELD_POL_INV',
'DP_VID_VBID_FIELD_POL_NORMAL', 'DRAW_DONE',
'DSCCIF_BITS_PER_COMPONENT_ENUM',
'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT',
'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT',
'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT',
'DSCCIF_ENABLE_ENUM', 'DSCCIF_ENABLE_ENUM_DISABLED',
'DSCCIF_ENABLE_ENUM_ENABLED', 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422',
'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444',
'DSCC_BITS_PER_COMPONENT_ENUM',
'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT',
'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT',
'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT',
'DSCC_DSC_VERSION_MAJOR_ENUM',
'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION',
'DSCC_DSC_VERSION_MINOR_ENUM',
'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION',
'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION',
'DSCC_ENABLE_ENUM', 'DSCC_ENABLE_ENUM_DISABLED',
'DSCC_ENABLE_ENUM_ENABLED', 'DSCC_ICH_RESET_ENUM',
'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET',
'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET',
'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET',
'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', 'DSCC_LINEBUF_DEPTH_ENUM',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT',
'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT',
'DSCC_MEM_PWR_DIS_ENUM', 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS',
'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', 'DSCC_MEM_PWR_FORCE_ENUM',
'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST',
'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST',
'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST',
'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST',
'DSCL_MODE_CHROMA_SCALING_BYPASS', 'DSCL_MODE_DSCL_BYPASS',
'DSCL_MODE_LUMA_SCALING_BYPASS', 'DSCL_MODE_SCALING_444_BYPASS',
'DSCL_MODE_SCALING_444_RGB_ENABLE',
'DSCL_MODE_SCALING_444_YCBCR_ENABLE',
'DSCL_MODE_SCALING_YCBCR_ENABLE', 'DSCL_MODE_SEL', 'DSM_DATA_SEL',
'DSM_DATA_SEL_0', 'DSM_DATA_SEL_1', 'DSM_DATA_SEL_BOTH',
'DSM_DATA_SEL_DISABLE', 'DSM_ENABLE_ERROR_INJECT',
'DSM_ENABLE_ERROR_INJECT_FED_IN',
'DSM_ENABLE_ERROR_INJECT_SINGLE',
'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE',
'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED',
'DSM_SELECT_INJECT_DELAY', 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR',
'DSM_SELECT_INJECT_DELAY_NO_DELAY', 'DSM_SINGLE_WRITE',
'DSM_SINGLE_WRITE_DIS', 'DSM_SINGLE_WRITE_EN', 'DS_HW_CAL_DIS',
'DS_HW_CAL_EN', 'DS_HW_CAL_ENABLE', 'DS_JITTER_COUNT_SRC_SEL',
'DS_JITTER_COUNT_SRC_SEL0', 'DS_JITTER_COUNT_SRC_SEL1',
'DS_REF_IS_EXT_GENLOCK', 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN',
'DS_REF_SRC', 'DTO_FORCE_BYPASS', 'DTO_FORCE_NO_BYPASS',
'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKC_IN_PHASE',
'DVOACLKC_IN_PHASE_WITH_PCLK_DVO',
'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO',
'DVOACLKC_MVP_IN_PHASE', 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO',
'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE',
'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE',
'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE',
'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKD_IN_PHASE',
'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', 'DVOACLK_COARSE_SKEW_CNTL',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS',
'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT',
'DVOACLK_FINE_SKEW_CNTL', 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP',
'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS',
'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS',
'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP',
'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS',
'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS',
'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS',
'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 'DVO_ENABLE_RST',
'DVO_ENABLE_RST_DISABLE', 'DVO_ENABLE_RST_ENABLE',
'DWB_CRC_CONT_EN_CONT', 'DWB_CRC_CONT_EN_ENUM',
'DWB_CRC_CONT_EN_ONE_SHOT', 'DWB_CRC_SRC_SEL_DWB_IN',
'DWB_CRC_SRC_SEL_DWB_OUT', 'DWB_CRC_SRC_SEL_ENUM',
'DWB_CRC_SRC_SEL_OGAM_OUT', 'DWB_DATA_OVERFLOW_INT_TYPE_0',
'DWB_DATA_OVERFLOW_INT_TYPE_1', 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM',
'DWB_DATA_OVERFLOW_TYPE_BUFFER', 'DWB_DATA_OVERFLOW_TYPE_ENUM',
'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW',
'DWB_DATA_OVERFLOW_TYPE_VREADY', 'DWB_DATA_OVERFLOW_TYPE_VUPDATE',
'DWB_DEBUG_SEL_DWBCP', 'DWB_DEBUG_SEL_ENUM', 'DWB_DEBUG_SEL_FC',
'DWB_DEBUG_SEL_PERFMON', 'DWB_DEBUG_SEL_RESERVED',
'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM',
'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13',
'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12',
'DWB_GAMUT_REMAP_MODE_BYPASS', 'DWB_GAMUT_REMAP_MODE_COEF_A',
'DWB_GAMUT_REMAP_MODE_COEF_B', 'DWB_GAMUT_REMAP_MODE_ENUM',
'DWB_GAMUT_REMAP_MODE_RESERVED', 'DWB_LUT_NUM_SEG',
'DWB_MEM_PWR_FORCE_DIS', 'DWB_MEM_PWR_FORCE_DS',
'DWB_MEM_PWR_FORCE_ENUM', 'DWB_MEM_PWR_FORCE_LS',
'DWB_MEM_PWR_FORCE_SD', 'DWB_MEM_PWR_STATE_DS',
'DWB_MEM_PWR_STATE_ENUM', 'DWB_MEM_PWR_STATE_LS',
'DWB_MEM_PWR_STATE_ON', 'DWB_MEM_PWR_STATE_SD',
'DWB_OGAM_LUT_CONFIG_MODE_DIFF', 'DWB_OGAM_LUT_CONFIG_MODE_ENUM',
'DWB_OGAM_LUT_CONFIG_MODE_SAME', 'DWB_OGAM_LUT_HOST_SEL_ENUM',
'DWB_OGAM_LUT_HOST_SEL_RAMA', 'DWB_OGAM_LUT_HOST_SEL_RAMB',
'DWB_OGAM_LUT_READ_COLOR_SEL_B',
'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM',
'DWB_OGAM_LUT_READ_COLOR_SEL_G', 'DWB_OGAM_LUT_READ_COLOR_SEL_R',
'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED',
'DWB_OGAM_LUT_READ_DBG_DISABLE', 'DWB_OGAM_LUT_READ_DBG_ENABLE',
'DWB_OGAM_LUT_READ_DBG_ENUM', 'DWB_OGAM_MODE_BYPASS',
'DWB_OGAM_MODE_ENUM', 'DWB_OGAM_MODE_RAM_LUT_ENABLED',
'DWB_OGAM_MODE_RESERVED', 'DWB_OGAM_PWL_DISABLE_ENUM',
'DWB_OGAM_PWL_DISABLE_FALSE', 'DWB_OGAM_PWL_DISABLE_TRUE',
'DWB_OGAM_SELECT_A', 'DWB_OGAM_SELECT_B', 'DWB_OGAM_SELECT_ENUM',
'DWB_SEGMENTS_1', 'DWB_SEGMENTS_128', 'DWB_SEGMENTS_16',
'DWB_SEGMENTS_2', 'DWB_SEGMENTS_32', 'DWB_SEGMENTS_4',
'DWB_SEGMENTS_64', 'DWB_SEGMENTS_8', 'DWB_TEST_CLK_SEL_ENUM',
'DWB_TEST_CLK_SEL_G', 'DWB_TEST_CLK_SEL_P', 'DWB_TEST_CLK_SEL_R',
'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE',
'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0',
'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1',
'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE',
'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE',
'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks',
'DbPRTFaultBehavior', 'DbPSLControl', 'EARLY',
'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z',
'EFC_ACrYCb16161616_10LSB', 'EFC_ACrYCb16161616_10MSB',
'EFC_ACrYCb16161616_12LSB', 'EFC_ACrYCb16161616_12MSB',
'EFC_ACrYCb2101010', 'EFC_ACrYCb8888', 'EFC_ARGB1555',
'EFC_ARGB16161616_10LSB', 'EFC_ARGB16161616_10MSB',
'EFC_ARGB16161616_12LSB', 'EFC_ARGB16161616_12MSB',
'EFC_ARGB16161616_FLOAT', 'EFC_ARGB16161616_SNORM',
'EFC_ARGB16161616_UNORM', 'EFC_ARGB2101010', 'EFC_ARGB4444',
'EFC_ARGB8888', 'EFC_AYCrCb16161616_10LSB',
'EFC_AYCrCb16161616_10MSB', 'EFC_AYCrCb16161616_12LSB',
'EFC_AYCrCb16161616_12MSB', 'EFC_AYCrCb8888', 'EFC_BGR101111_FIX',
'EFC_BGR101111_FLOAT', 'EFC_BGR565',
'EFC_CbYCrY10101010_422_PACKED', 'EFC_CbYCrY12121212_422_PACKED',
'EFC_CbYCrY8888_422_PACKED', 'EFC_CrYCbA1010102',
'EFC_CrYCbA16161616_10LSB', 'EFC_CrYCbA16161616_10MSB',
'EFC_CrYCbA16161616_12LSB', 'EFC_CrYCbA16161616_12MSB',
'EFC_CrYCbA8888', 'EFC_CrYCbY10101010_422_PACKED',
'EFC_CrYCbY12121212_422_PACKED', 'EFC_CrYCbY8888_422_PACKED',
'EFC_MONO_10LSB', 'EFC_MONO_10MSB', 'EFC_MONO_12LSB',
'EFC_MONO_12MSB', 'EFC_MONO_16', 'EFC_MONO_8',
'EFC_RGB111110_FIX', 'EFC_RGB111110_FLOAT', 'EFC_RGB565',
'EFC_RGBA1010102', 'EFC_RGBA16161616_10LSB',
'EFC_RGBA16161616_10MSB', 'EFC_RGBA16161616_12LSB',
'EFC_RGBA16161616_12MSB', 'EFC_RGBA16161616_FLOAT',
'EFC_RGBA16161616_SNORM', 'EFC_RGBA16161616_UNORM',
'EFC_RGBA4444', 'EFC_RGBA5551', 'EFC_RGBA8888',
'EFC_SURFACE_PIXEL_FORMAT', 'EFC_Y10_CbCr1010_420_PLANAR',
'EFC_Y10_CrCb1010_420_PLANAR', 'EFC_Y12_CbCr1212_420_PLANAR',
'EFC_Y12_CrCb1212_420_PLANAR', 'EFC_Y8_CbCr88_420_PLANAR',
'EFC_Y8_CrCb88_420_PLANAR', 'EFC_YCbYCr10101010_422_PACKED',
'EFC_YCbYCr12121212_422_PACKED', 'EFC_YCbYCr8888_422_PACKED',
'EFC_YCrCbA16161616_10LSB', 'EFC_YCrCbA16161616_10MSB',
'EFC_YCrCbA16161616_12LSB', 'EFC_YCrCbA16161616_12MSB',
'EFC_YCrCbA8888', 'EFC_YCrYCb10101010_422_PACKED',
'EFC_YCrYCb12121212_422_PACKED', 'EFC_YCrYCb8888_422_PACKED',
'ENABLE', 'ENABLE_AMCLK0', 'ENABLE_AMCLK1', 'ENABLE_CLOCK',
'ENABLE_DEBUG', 'ENABLE_ENUM', 'ENABLE_ENUM_DISABLED',
'ENABLE_ENUM_ENABLED', 'ENABLE_JITTER_REMOVAL',
'ENABLE_LEGACY_PIPELINE', 'ENABLE_MEM_PWR_CTRL',
'ENABLE_NGG_PIPELINE', 'ENABLE_PWL', 'ENABLE_TF0_OPT',
'ENABLE_TF1_OPT', 'ENABLE_THE_FEATURE', 'ENABLE_THE_FUNC_CLOCK',
'ENABLE_THE_INTERRUPT', 'ENABLE_THE_REFCLK', 'END_OF_PIPE_IB_END',
'END_OF_PIPE_INCR_DE', 'END_OF_ROW_MODE', 'ENUM_DCN_ACTIVE',
'ENUM_DCN_NOT_ACTIVE', 'ENUM_DIO_DCN_ACTIVE_STATUS',
'ENUM_DPG_BIT_DEPTH', 'ENUM_DPG_BIT_DEPTH_10BPC',
'ENUM_DPG_BIT_DEPTH_12BPC', 'ENUM_DPG_BIT_DEPTH_6BPC',
'ENUM_DPG_BIT_DEPTH_8BPC', 'ENUM_DPG_DISABLE',
'ENUM_DPG_DYNAMIC_RANGE', 'ENUM_DPG_DYNAMIC_RANGE_CEA',
'ENUM_DPG_DYNAMIC_RANGE_VESA', 'ENUM_DPG_EN', 'ENUM_DPG_ENABLE',
'ENUM_DPG_FIELD_POLARITY',
'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD',
'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', 'ENUM_DPG_MODE',
'ENUM_DPG_MODE_HORIZONTAL_BAR', 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK',
'ENUM_DPG_MODE_RGB_DUAL_RAMP', 'ENUM_DPG_MODE_RGB_SINGLE_RAMP',
'ENUM_DPG_MODE_RGB_XR_BIAS', 'ENUM_DPG_MODE_VERTICAL_BAR',
'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK',
'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK',
'ENUM_DP_DPHY_SYM32_CRC_END_EVENT',
'ENUM_DP_DPHY_SYM32_CRC_START_EVENT',
'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE',
'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS',
'ENUM_DP_DPHY_SYM32_ENABLE', 'ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE',
'ENUM_DP_DPHY_SYM32_MODE', 'ENUM_DP_DPHY_SYM32_NUM_LANES',
'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING',
'ENUM_DP_DPHY_SYM32_RESET', 'ENUM_DP_DPHY_SYM32_RESET_STATUS',
'ENUM_DP_DPHY_SYM32_SAT_UPDATE',
'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING',
'ENUM_DP_DPHY_SYM32_STATUS',
'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE',
'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE',
'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL', 'ENUM_DP_DPHY_SYM32_TP_SELECT',
'ENUM_DP_SYM32_ENC_AUDIO_MUTE',
'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE',
'ENUM_DP_SYM32_ENC_CRC_VALID',
'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH',
'ENUM_DP_SYM32_ENC_ENABLE',
'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED',
'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION',
'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE',
'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING',
'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM',
'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS', 'ENUM_DP_SYM32_ENC_PENDING',
'ENUM_DP_SYM32_ENC_PIXEL_ENCODING',
'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE',
'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM', 'ENUM_DP_SYM32_ENC_RESET',
'ENUM_DP_SYM32_ENC_SDP_PRIORITY',
'ENUM_DP_SYM32_ENC_SOF_REFERENCE',
'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER', 'ENUM_DSCRM_DISABLE',
'ENUM_DSCRM_EN', 'ENUM_DSCRM_ENABLE', 'ENUM_NUM_SIMD_PER_CU',
'ES_STAGE_DS', 'ES_STAGE_OFF', 'ES_STAGE_REAL', 'EXOKAY',
'EXPANSION_MODE', 'EXPANSION_MODE_CONSERVATIVE',
'EXPANSION_MODE_OPTIMAL', 'EXPANSION_MODE_ZERO',
'EXPORT_2C_32BPC_AR', 'EXPORT_2C_32BPC_GR', 'EXPORT_4C_16BPC',
'EXPORT_4C_32BPC', 'EXPORT_ANY_Z', 'EXPORT_GREATER_THAN_Z',
'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'F32_MES_PM4_PACKETS_H',
'FAULT_FAIL', 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO',
'FC_EYE_SELECTION_ENUM', 'FC_EYE_SELECTION_LEFT_EYE',
'FC_EYE_SELECTION_RIGHT_EYE', 'FC_EYE_SELECTION_STEREO_DIS',
'FC_FRAME_CAPTURE_RATE_ENUM', 'FC_FRAME_CAPTURE_RATE_FULL',
'FC_FRAME_CAPTURE_RATE_HALF', 'FC_FRAME_CAPTURE_RATE_QUARTER',
'FC_FRAME_CAPTURE_RATE_THIRD', 'FC_STEREO_EYE_POLARITY_ENUM',
'FC_STEREO_EYE_POLARITY_LEFT', 'FC_STEREO_EYE_POLARITY_RIGHT',
'FEC_ACTIVE_STATUS', 'FIX_S2_13', 'FIX_S3_12', 'FLIP_ANY_FRAME',
'FLIP_LEFT_EYE', 'FLIP_RATE', 'FLIP_RATE_0', 'FLIP_RATE_1',
'FLIP_RATE_2', 'FLIP_RATE_3', 'FLIP_RATE_4', 'FLIP_RATE_5',
'FLIP_RATE_6', 'FLIP_RATE_7', 'FLIP_RIGHT_EYE',
'FLUSH_AND_INV_CB_DATA_TS', 'FLUSH_AND_INV_CB_META',
'FLUSH_AND_INV_CB_PIXEL_DATA', 'FLUSH_AND_INV_DB_DATA_TS',
'FLUSH_AND_INV_DB_META', 'FLUSH_CONTROL_FLUSH_NOT_STARTED',
'FLUSH_CONTROL_FLUSH_STARTED', 'FLUSH_DFSM', 'FLUSH_ES_OUTPUT',
'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', 'FMTMEM_DISABLE_MEM_PWR_CTRL',
'FMTMEM_ENABLE_MEM_PWR_CTRL', 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST',
'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST',
'FMTMEM_FORCE_SHUT_DOWN_REQUEST', 'FMTMEM_NO_FORCE_REQUEST',
'FMTMEM_PWR_DIS_CTRL', 'FMTMEM_PWR_FORCE_CTRL',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi',
'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C',
'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G',
'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED',
'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH',
'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP',
'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP',
'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2',
'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING',
'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION',
'FMT_CLAMP_CNTL_COLOR_FORMAT',
'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC',
'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC',
'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC',
'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC',
'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE',
'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1',
'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2',
'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3',
'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS',
'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE',
'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE',
'FMT_CONTROL_PIXEL_ENCODING',
'FMT_CONTROL_PIXEL_ENCODING_RESERVED',
'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444',
'FMT_CONTROL_PIXEL_ENCODING_YCBCR420',
'FMT_CONTROL_PIXEL_ENCODING_YCBCR422',
'FMT_CONTROL_SUBSAMPLING_MODE',
'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE',
'FMT_CONTROL_SUBSAMPLING_MODE_DROP',
'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP',
'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED',
'FMT_CONTROL_SUBSAMPLING_ORDER',
'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR',
'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB',
'FMT_DEBUG_CNTL_COLOR_SELECT', 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE',
'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN',
'FMT_DEBUG_CNTL_COLOR_SELECT_RED1',
'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', 'FMT_DYNAMIC_EXP_MODE',
'FMT_DYNAMIC_EXP_MODE_10to12', 'FMT_DYNAMIC_EXP_MODE_8to12',
'FMT_FRAME_RANDOM_ENABLE_CONTROL',
'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME',
'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', 'FMT_POWER_STATE_ENUM',
'FMT_POWER_STATE_ENUM_DS', 'FMT_POWER_STATE_ENUM_LS',
'FMT_POWER_STATE_ENUM_ON', 'FMT_POWER_STATE_ENUM_SD',
'FMT_RGB_RANDOM_ENABLE_CONTROL',
'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE',
'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP',
'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED',
'FMT_SPATIAL_DITHER_MODE', 'FMT_SPATIAL_DITHER_MODE_0',
'FMT_SPATIAL_DITHER_MODE_1', 'FMT_SPATIAL_DITHER_MODE_2',
'FMT_SPATIAL_DITHER_MODE_3', 'FMT_STEREOSYNC_OVERRIDE_CONTROL',
'FMT_STEREOSYNC_OVERRIDE_CONTROL_0',
'FMT_STEREOSYNC_OVERRIDE_CONTROL_1',
'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0',
'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR',
'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', 'FORCE_00',
'FORCE_BINNING_ON', 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE',
'FORCE_DISABLE_CLOCK', 'FORCE_EARLY_Z', 'FORCE_ENABLE',
'FORCE_FF', 'FORCE_LATE_Z', 'FORCE_LIGHT_SLEEP_REQ',
'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF',
'FORCE_ONE_ROW_FOR_FRAME', 'FORCE_ONE_ROW_FOR_FRAME_0',
'FORCE_ONE_ROW_FOR_FRAME_1', 'FORCE_OPT_AUTO',
'FORCE_OPT_DISABLE', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0',
'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0',
'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0',
'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z',
'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH',
'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF',
'FORCE_THE_CLOCK_DISABLED', 'FORMAT_CROSSBAR',
'FORMAT_CROSSBAR_B', 'FORMAT_CROSSBAR_G', 'FORMAT_CROSSBAR_R',
'FRAG_ALWAYS', 'FRAG_EQUAL', 'FRAG_GEQUAL', 'FRAG_GREATER',
'FRAG_LEQUAL', 'FRAG_LESS', 'FRAG_NEVER', 'FRAG_NOTEQUAL',
'FRAME_TMZ', 'FUSE_BASE', 'FUSE_BASE__INST0_SEG0',
'FUSE_BASE__INST0_SEG1', 'FUSE_BASE__INST0_SEG2',
'FUSE_BASE__INST0_SEG3', 'FUSE_BASE__INST0_SEG4',
'FUSE_BASE__INST1_SEG0', 'FUSE_BASE__INST1_SEG1',
'FUSE_BASE__INST1_SEG2', 'FUSE_BASE__INST1_SEG3',
'FUSE_BASE__INST1_SEG4', 'FUSE_BASE__INST2_SEG0',
'FUSE_BASE__INST2_SEG1', 'FUSE_BASE__INST2_SEG2',
'FUSE_BASE__INST2_SEG3', 'FUSE_BASE__INST2_SEG4',
'FUSE_BASE__INST3_SEG0', 'FUSE_BASE__INST3_SEG1',
'FUSE_BASE__INST3_SEG2', 'FUSE_BASE__INST3_SEG3',
'FUSE_BASE__INST3_SEG4', 'FUSE_BASE__INST4_SEG0',
'FUSE_BASE__INST4_SEG1', 'FUSE_BASE__INST4_SEG2',
'FUSE_BASE__INST4_SEG3', 'FUSE_BASE__INST4_SEG4',
'FUSE_BASE__INST5_SEG0', 'FUSE_BASE__INST5_SEG1',
'FUSE_BASE__INST5_SEG2', 'FUSE_BASE__INST5_SEG3',
'FUSE_BASE__INST5_SEG4', 'FUSE_BASE__INST6_SEG0',
'FUSE_BASE__INST6_SEG1', 'FUSE_BASE__INST6_SEG2',
'FUSE_BASE__INST6_SEG3', 'FUSE_BASE__INST6_SEG4', 'ForceControl',
'GAMUT_COEF', 'GAMUT_COEF_B', 'GATCL1RequestType',
'GATCL1_TYPE_BYPASS', 'GATCL1_TYPE_NORMAL',
'GATCL1_TYPE_SHOOTDOWN', 'GB_EDC_DED_MODE',
'GB_EDC_DED_MODE_HALT', 'GB_EDC_DED_MODE_INT_HALT',
'GB_EDC_DED_MODE_LOG', 'GB_TILING_CONFIG_MACROTABLE_SIZE',
'GB_TILING_CONFIG_TABLE_SIZE', 'GCRPerfSel',
'GCR_PERF_SEL_ALL_REQ',
'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ',
'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ',
'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ',
'GCR_PERF_SEL_CPC_ALL_REQ', 'GCR_PERF_SEL_CPC_GL1_ALL_REQ',
'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPC_GL2_ALL_REQ',
'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPC_METADATA_REQ',
'GCR_PERF_SEL_CPC_SQC_DATA_REQ', 'GCR_PERF_SEL_CPC_SQC_INST_REQ',
'GCR_PERF_SEL_CPC_TCP_REQ',
'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_CPF_ALL_REQ', 'GCR_PERF_SEL_CPF_GL1_ALL_REQ',
'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPF_GL2_ALL_REQ',
'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPF_METADATA_REQ',
'GCR_PERF_SEL_CPF_SQC_DATA_REQ', 'GCR_PERF_SEL_CPF_SQC_INST_REQ',
'GCR_PERF_SEL_CPF_TCP_REQ',
'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_CPG_ALL_REQ', 'GCR_PERF_SEL_CPG_GL1_ALL_REQ',
'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPG_GL2_ALL_REQ',
'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPG_METADATA_REQ',
'GCR_PERF_SEL_CPG_SQC_DATA_REQ', 'GCR_PERF_SEL_CPG_SQC_INST_REQ',
'GCR_PERF_SEL_CPG_TCP_REQ',
'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', 'GCR_PERF_SEL_NONE',
'GCR_PERF_SEL_PHY_REQ', 'GCR_PERF_SEL_PIO_ALL_REQ',
'GCR_PERF_SEL_PIO_GL1_ALL_REQ',
'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', 'GCR_PERF_SEL_PIO_GL2_ALL_REQ',
'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', 'GCR_PERF_SEL_PIO_METADATA_REQ',
'GCR_PERF_SEL_PIO_SQC_DATA_REQ', 'GCR_PERF_SEL_PIO_SQC_INST_REQ',
'GCR_PERF_SEL_PIO_TCP_REQ',
'GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_PM_ALL_REQ', 'GCR_PERF_SEL_PM_GL1_ALL_REQ',
'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_PM_GL1_RANGE_REQ', 'GCR_PERF_SEL_PM_GL2_ALL_REQ',
'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_PM_GL2_RANGE_REQ', 'GCR_PERF_SEL_PM_METADATA_REQ',
'GCR_PERF_SEL_PM_SQC_DATA_REQ', 'GCR_PERF_SEL_PM_SQC_INST_REQ',
'GCR_PERF_SEL_PM_TCP_REQ',
'GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_RLC_ALL_REQ', 'GCR_PERF_SEL_RLC_GL1_ALL_REQ',
'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', 'GCR_PERF_SEL_RLC_GL2_ALL_REQ',
'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', 'GCR_PERF_SEL_RLC_METADATA_REQ',
'GCR_PERF_SEL_RLC_SQC_DATA_REQ', 'GCR_PERF_SEL_RLC_SQC_INST_REQ',
'GCR_PERF_SEL_RLC_TCP_REQ',
'GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_SDMA0_ALL_REQ', 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ',
'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ',
'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ',
'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ',
'GCR_PERF_SEL_SDMA0_METADATA_REQ',
'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ',
'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA0_TCP_REQ',
'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_SDMA1_ALL_REQ', 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ',
'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ',
'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ',
'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ',
'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ',
'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ',
'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ',
'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ',
'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ',
'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ',
'GCR_PERF_SEL_SDMA1_METADATA_REQ',
'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ',
'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA1_TCP_REQ',
'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ',
'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ',
'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ',
'GCR_PERF_SEL_UTCL2_FILTERED_RET',
'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ',
'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT',
'GCR_PERF_SEL_UTCL2_REQ', 'GCR_PERF_SEL_UTCL2_RET',
'GCR_PERF_SEL_VIRT_REQ', 'GC_BASE', 'GC_BASE__INST0_SEG0',
'GC_BASE__INST0_SEG1', 'GC_BASE__INST0_SEG2',
'GC_BASE__INST0_SEG3', 'GC_BASE__INST0_SEG4',
'GC_BASE__INST1_SEG0', 'GC_BASE__INST1_SEG1',
'GC_BASE__INST1_SEG2', 'GC_BASE__INST1_SEG3',
'GC_BASE__INST1_SEG4', 'GC_BASE__INST2_SEG0',
'GC_BASE__INST2_SEG1', 'GC_BASE__INST2_SEG2',
'GC_BASE__INST2_SEG3', 'GC_BASE__INST2_SEG4',
'GC_BASE__INST3_SEG0', 'GC_BASE__INST3_SEG1',
'GC_BASE__INST3_SEG2', 'GC_BASE__INST3_SEG3',
'GC_BASE__INST3_SEG4', 'GC_BASE__INST4_SEG0',
'GC_BASE__INST4_SEG1', 'GC_BASE__INST4_SEG2',
'GC_BASE__INST4_SEG3', 'GC_BASE__INST4_SEG4',
'GC_BASE__INST5_SEG0', 'GC_BASE__INST5_SEG1',
'GC_BASE__INST5_SEG2', 'GC_BASE__INST5_SEG3',
'GC_BASE__INST5_SEG4', 'GC_BASE__INST6_SEG0',
'GC_BASE__INST6_SEG1', 'GC_BASE__INST6_SEG2',
'GC_BASE__INST6_SEG3', 'GC_BASE__INST6_SEG4',
'GDS_PERFCOUNT_SELECT', 'GDS_PERF_SEL_GWS_BYPASS',
'GDS_PERF_SEL_GWS_RELEASED', 'GDS_PERF_SEL_SE0_2COMP_REQ',
'GDS_PERF_SEL_SE0_GDS_ATOM_OP', 'GDS_PERF_SEL_SE0_GDS_BYTE_OP',
'GDS_PERF_SEL_SE0_GDS_CMPXCH_OP', 'GDS_PERF_SEL_SE0_GDS_RD_OP',
'GDS_PERF_SEL_SE0_GDS_REL_OP', 'GDS_PERF_SEL_SE0_GDS_SHORT_OP',
'GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE0_GDS_WR_OP',
'GDS_PERF_SEL_SE0_NORET', 'GDS_PERF_SEL_SE0_ORD_CNT',
'GDS_PERF_SEL_SE0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_RET',
'GDS_PERF_SEL_SE1_2COMP_REQ', 'GDS_PERF_SEL_SE1_GDS_ATOM_OP',
'GDS_PERF_SEL_SE1_GDS_BYTE_OP', 'GDS_PERF_SEL_SE1_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE1_GDS_RD_OP', 'GDS_PERF_SEL_SE1_GDS_REL_OP',
'GDS_PERF_SEL_SE1_GDS_SHORT_OP',
'GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE1_GDS_WR_OP',
'GDS_PERF_SEL_SE1_NORET', 'GDS_PERF_SEL_SE1_ORD_CNT',
'GDS_PERF_SEL_SE1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_RET',
'GDS_PERF_SEL_SE2_2COMP_REQ', 'GDS_PERF_SEL_SE2_GDS_ATOM_OP',
'GDS_PERF_SEL_SE2_GDS_BYTE_OP', 'GDS_PERF_SEL_SE2_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE2_GDS_RD_OP', 'GDS_PERF_SEL_SE2_GDS_REL_OP',
'GDS_PERF_SEL_SE2_GDS_SHORT_OP',
'GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE2_GDS_WR_OP',
'GDS_PERF_SEL_SE2_NORET', 'GDS_PERF_SEL_SE2_ORD_CNT',
'GDS_PERF_SEL_SE2_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_RET',
'GDS_PERF_SEL_SE3_2COMP_REQ', 'GDS_PERF_SEL_SE3_GDS_ATOM_OP',
'GDS_PERF_SEL_SE3_GDS_BYTE_OP', 'GDS_PERF_SEL_SE3_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE3_GDS_RD_OP', 'GDS_PERF_SEL_SE3_GDS_REL_OP',
'GDS_PERF_SEL_SE3_GDS_SHORT_OP',
'GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE3_GDS_WR_OP',
'GDS_PERF_SEL_SE3_NORET', 'GDS_PERF_SEL_SE3_ORD_CNT',
'GDS_PERF_SEL_SE3_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_RET',
'GDS_PERF_SEL_SE4_2COMP_REQ', 'GDS_PERF_SEL_SE4_GDS_ATOM_OP',
'GDS_PERF_SEL_SE4_GDS_BYTE_OP', 'GDS_PERF_SEL_SE4_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE4_GDS_RD_OP', 'GDS_PERF_SEL_SE4_GDS_REL_OP',
'GDS_PERF_SEL_SE4_GDS_SHORT_OP',
'GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE4_GDS_WR_OP',
'GDS_PERF_SEL_SE4_NORET', 'GDS_PERF_SEL_SE4_ORD_CNT',
'GDS_PERF_SEL_SE4_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE4_RET',
'GDS_PERF_SEL_SE5_2COMP_REQ', 'GDS_PERF_SEL_SE5_GDS_ATOM_OP',
'GDS_PERF_SEL_SE5_GDS_BYTE_OP', 'GDS_PERF_SEL_SE5_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE5_GDS_RD_OP', 'GDS_PERF_SEL_SE5_GDS_REL_OP',
'GDS_PERF_SEL_SE5_GDS_SHORT_OP',
'GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE5_GDS_WR_OP',
'GDS_PERF_SEL_SE5_NORET', 'GDS_PERF_SEL_SE5_ORD_CNT',
'GDS_PERF_SEL_SE5_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE5_RET',
'GDS_PERF_SEL_SE6_2COMP_REQ', 'GDS_PERF_SEL_SE6_GDS_ATOM_OP',
'GDS_PERF_SEL_SE6_GDS_BYTE_OP', 'GDS_PERF_SEL_SE6_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE6_GDS_RD_OP', 'GDS_PERF_SEL_SE6_GDS_REL_OP',
'GDS_PERF_SEL_SE6_GDS_SHORT_OP',
'GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE6_GDS_WR_OP',
'GDS_PERF_SEL_SE6_NORET', 'GDS_PERF_SEL_SE6_ORD_CNT',
'GDS_PERF_SEL_SE6_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE6_RET',
'GDS_PERF_SEL_SE7_2COMP_REQ', 'GDS_PERF_SEL_SE7_GDS_ATOM_OP',
'GDS_PERF_SEL_SE7_GDS_BYTE_OP', 'GDS_PERF_SEL_SE7_GDS_CMPXCH_OP',
'GDS_PERF_SEL_SE7_GDS_RD_OP', 'GDS_PERF_SEL_SE7_GDS_REL_OP',
'GDS_PERF_SEL_SE7_GDS_SHORT_OP',
'GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE7_GDS_WR_OP',
'GDS_PERF_SEL_SE7_NORET', 'GDS_PERF_SEL_SE7_ORD_CNT',
'GDS_PERF_SEL_SE7_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE7_RET',
'GDS_PERF_SEL_WBUF_WR', 'GDS_PERF_SEL_WR_COMP',
'GE1_PERFCOUNT_SELECT', 'GE2_DIST_PERFCOUNT_SELECT',
'GE2_SE_PERFCOUNT_SELECT',
'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE',
'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE',
'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL',
'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET',
'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED',
'GENERIC_STEREOSYNC_SEL', 'GENERIC_STEREOSYNC_SEL_D1',
'GENERIC_STEREOSYNC_SEL_D2', 'GENERIC_STEREOSYNC_SEL_D3',
'GENERIC_STEREOSYNC_SEL_D4', 'GENERIC_STEREOSYNC_SEL_RESERVED',
'GEN_ONE', 'GEN_RESERVED', 'GEN_TWO', 'GEN_ZERO',
'GL0V_CACHE_POLICIES', 'GL0V_CACHE_POLICY_HIT_EVICT',
'GL0V_CACHE_POLICY_HIT_LRU', 'GL0V_CACHE_POLICY_MISS_EVICT',
'GL0V_CACHE_POLICY_MISS_LRU', 'GL1A_PERF_SEL',
'GL1A_PERF_SEL_ARB_REQUESTS', 'GL1A_PERF_SEL_BURST_COUNT_GL1C0',
'GL1A_PERF_SEL_BURST_COUNT_GL1C1',
'GL1A_PERF_SEL_BURST_COUNT_GL1C2',
'GL1A_PERF_SEL_BURST_COUNT_GL1C3', 'GL1A_PERF_SEL_BUSY',
'GL1A_PERF_SEL_CYCLE', 'GL1A_PERF_SEL_REQUEST_GL1C0',
'GL1A_PERF_SEL_REQUEST_GL1C1', 'GL1A_PERF_SEL_REQUEST_GL1C2',
'GL1A_PERF_SEL_REQUEST_GL1C3', 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL',
'GL1A_PERF_SEL_STALL_GL1C0', 'GL1A_PERF_SEL_STALL_GL1C1',
'GL1A_PERF_SEL_STALL_GL1C2', 'GL1A_PERF_SEL_STALL_GL1C3',
'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0',
'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1',
'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2',
'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3',
'GL1A_PERF_SEL_WDS_32B_GL1C0', 'GL1A_PERF_SEL_WDS_32B_GL1C1',
'GL1A_PERF_SEL_WDS_32B_GL1C2', 'GL1A_PERF_SEL_WDS_32B_GL1C3',
'GL1C_PERF_SEL', 'GL1C_PERF_SEL_ARB_RET_LEVEL',
'GL1C_PERF_SEL_BUSY', 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT',
'GL1C_PERF_SEL_CYCLE', 'GL1C_PERF_SEL_GL2_REQ_PREFETCH',
'GL1C_PERF_SEL_GL2_REQ_READ', 'GL1C_PERF_SEL_GL2_REQ_READ_128B',
'GL1C_PERF_SEL_GL2_REQ_READ_32B',
'GL1C_PERF_SEL_GL2_REQ_READ_64B',
'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY',
'GL1C_PERF_SEL_GL2_REQ_WRITE', 'GL1C_PERF_SEL_GL2_REQ_WRITE_32B',
'GL1C_PERF_SEL_GL2_REQ_WRITE_64B',
'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'GL1C_PERF_SEL_REQ',
'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET',
'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', 'GL1C_PERF_SEL_REQ_CLIENT0',
'GL1C_PERF_SEL_REQ_CLIENT1', 'GL1C_PERF_SEL_REQ_CLIENT10',
'GL1C_PERF_SEL_REQ_CLIENT11', 'GL1C_PERF_SEL_REQ_CLIENT12',
'GL1C_PERF_SEL_REQ_CLIENT13', 'GL1C_PERF_SEL_REQ_CLIENT14',
'GL1C_PERF_SEL_REQ_CLIENT15', 'GL1C_PERF_SEL_REQ_CLIENT16',
'GL1C_PERF_SEL_REQ_CLIENT17', 'GL1C_PERF_SEL_REQ_CLIENT18',
'GL1C_PERF_SEL_REQ_CLIENT19', 'GL1C_PERF_SEL_REQ_CLIENT2',
'GL1C_PERF_SEL_REQ_CLIENT20', 'GL1C_PERF_SEL_REQ_CLIENT21',
'GL1C_PERF_SEL_REQ_CLIENT22', 'GL1C_PERF_SEL_REQ_CLIENT23',
'GL1C_PERF_SEL_REQ_CLIENT24', 'GL1C_PERF_SEL_REQ_CLIENT25',
'GL1C_PERF_SEL_REQ_CLIENT26', 'GL1C_PERF_SEL_REQ_CLIENT27',
'GL1C_PERF_SEL_REQ_CLIENT3', 'GL1C_PERF_SEL_REQ_CLIENT4',
'GL1C_PERF_SEL_REQ_CLIENT5', 'GL1C_PERF_SEL_REQ_CLIENT6',
'GL1C_PERF_SEL_REQ_CLIENT7', 'GL1C_PERF_SEL_REQ_CLIENT8',
'GL1C_PERF_SEL_REQ_CLIENT9', 'GL1C_PERF_SEL_REQ_MISS',
'GL1C_PERF_SEL_REQ_NOP_ACK', 'GL1C_PERF_SEL_REQ_NOP_RTN0',
'GL1C_PERF_SEL_REQ_READ', 'GL1C_PERF_SEL_REQ_READ_128B',
'GL1C_PERF_SEL_REQ_READ_32B', 'GL1C_PERF_SEL_REQ_READ_64B',
'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT',
'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU',
'GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT',
'GL1C_PERF_SEL_REQ_SHADER_INV', 'GL1C_PERF_SEL_REQ_WRITE',
'GL1C_PERF_SEL_REQ_WRITE_32B', 'GL1C_PERF_SEL_REQ_WRITE_64B',
'GL1C_PERF_SEL_STALL_GCR_INV', 'GL1C_PERF_SEL_STALL_GL2_GL1',
'GL1C_PERF_SEL_STALL_LFIFO_FULL',
'GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE',
'GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC',
'GL1C_PERF_SEL_STALL_VM', 'GL1C_PERF_SEL_STARVE',
'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ',
'GL1C_PERF_SEL_UTCL0_LFIFO_FULL',
'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS',
'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS',
'GL1C_PERF_SEL_UTCL0_REQUEST',
'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX',
'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES',
'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT',
'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL',
'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS',
'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS',
'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT',
'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS',
'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT',
'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT',
'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT',
'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT',
'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT',
'GL1H_REQ_PERF_SEL', 'GL1H_REQ_PERF_SEL_ARB_REQUESTS',
'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0',
'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1', 'GL1H_REQ_PERF_SEL_BUSY',
'GL1H_REQ_PERF_SEL_CYCLE', 'GL1H_REQ_PERF_SEL_REQUEST_GL1_0',
'GL1H_REQ_PERF_SEL_REQUEST_GL1_1',
'GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL',
'GL1H_REQ_PERF_SEL_STALL_GL1_0', 'GL1H_REQ_PERF_SEL_STALL_GL1_1',
'GL1H_REQ_PERF_SEL_WDS_32B_GL1_0',
'GL1H_REQ_PERF_SEL_WDS_32B_GL1_1', 'GL1_CACHE_POLICIES',
'GL1_CACHE_POLICY_HIT_EVICT', 'GL1_CACHE_POLICY_HIT_LRU',
'GL1_CACHE_POLICY_MISS_EVICT', 'GL1_CACHE_POLICY_MISS_LRU',
'GL1_CACHE_STORE_POLICIES', 'GL1_CACHE_STORE_POLICY_BYPASS',
'GL2A_PERF_SEL', 'GL2A_PERF_SEL_BUSY', 'GL2A_PERF_SEL_CYCLE',
'GL2A_PERF_SEL_NONE', 'GL2A_PERF_SEL_REQ_BURST_CLIENT0',
'GL2A_PERF_SEL_REQ_BURST_CLIENT1',
'GL2A_PERF_SEL_REQ_BURST_CLIENT10',
'GL2A_PERF_SEL_REQ_BURST_CLIENT11',
'GL2A_PERF_SEL_REQ_BURST_CLIENT12',
'GL2A_PERF_SEL_REQ_BURST_CLIENT13',
'GL2A_PERF_SEL_REQ_BURST_CLIENT14',
'GL2A_PERF_SEL_REQ_BURST_CLIENT15',
'GL2A_PERF_SEL_REQ_BURST_CLIENT2',
'GL2A_PERF_SEL_REQ_BURST_CLIENT3',
'GL2A_PERF_SEL_REQ_BURST_CLIENT4',
'GL2A_PERF_SEL_REQ_BURST_CLIENT5',
'GL2A_PERF_SEL_REQ_BURST_CLIENT6',
'GL2A_PERF_SEL_REQ_BURST_CLIENT7',
'GL2A_PERF_SEL_REQ_BURST_CLIENT8',
'GL2A_PERF_SEL_REQ_BURST_CLIENT9',
'GL2A_PERF_SEL_REQ_BURST_GL2C0', 'GL2A_PERF_SEL_REQ_BURST_GL2C1',
'GL2A_PERF_SEL_REQ_BURST_GL2C2', 'GL2A_PERF_SEL_REQ_BURST_GL2C3',
'GL2A_PERF_SEL_REQ_BURST_GL2C4', 'GL2A_PERF_SEL_REQ_BURST_GL2C5',
'GL2A_PERF_SEL_REQ_BURST_GL2C6', 'GL2A_PERF_SEL_REQ_BURST_GL2C7',
'GL2A_PERF_SEL_REQ_GL2C0', 'GL2A_PERF_SEL_REQ_GL2C1',
'GL2A_PERF_SEL_REQ_GL2C2', 'GL2A_PERF_SEL_REQ_GL2C3',
'GL2A_PERF_SEL_REQ_GL2C4', 'GL2A_PERF_SEL_REQ_GL2C5',
'GL2A_PERF_SEL_REQ_GL2C6', 'GL2A_PERF_SEL_REQ_GL2C7',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6',
'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7',
'GL2A_PERF_SEL_REQ_STALL_GL2C0', 'GL2A_PERF_SEL_REQ_STALL_GL2C1',
'GL2A_PERF_SEL_REQ_STALL_GL2C2', 'GL2A_PERF_SEL_REQ_STALL_GL2C3',
'GL2A_PERF_SEL_REQ_STALL_GL2C4', 'GL2A_PERF_SEL_REQ_STALL_GL2C5',
'GL2A_PERF_SEL_REQ_STALL_GL2C6', 'GL2A_PERF_SEL_REQ_STALL_GL2C7',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8',
'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9',
'GL2A_PERF_SEL_RTN_CLIENT0', 'GL2A_PERF_SEL_RTN_CLIENT1',
'GL2A_PERF_SEL_RTN_CLIENT10', 'GL2A_PERF_SEL_RTN_CLIENT11',
'GL2A_PERF_SEL_RTN_CLIENT12', 'GL2A_PERF_SEL_RTN_CLIENT13',
'GL2A_PERF_SEL_RTN_CLIENT14', 'GL2A_PERF_SEL_RTN_CLIENT15',
'GL2A_PERF_SEL_RTN_CLIENT2', 'GL2A_PERF_SEL_RTN_CLIENT3',
'GL2A_PERF_SEL_RTN_CLIENT4', 'GL2A_PERF_SEL_RTN_CLIENT5',
'GL2A_PERF_SEL_RTN_CLIENT6', 'GL2A_PERF_SEL_RTN_CLIENT7',
'GL2A_PERF_SEL_RTN_CLIENT8', 'GL2A_PERF_SEL_RTN_CLIENT9',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8',
'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9',
'GL2A_PERF_SEL_RTN_STALL_GL2C0', 'GL2A_PERF_SEL_RTN_STALL_GL2C1',
'GL2A_PERF_SEL_RTN_STALL_GL2C2', 'GL2A_PERF_SEL_RTN_STALL_GL2C3',
'GL2A_PERF_SEL_RTN_STALL_GL2C4', 'GL2A_PERF_SEL_RTN_STALL_GL2C5',
'GL2A_PERF_SEL_RTN_STALL_GL2C6', 'GL2A_PERF_SEL_RTN_STALL_GL2C7',
'GL2C_PERF_SEL', 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT',
'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT',
'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE',
'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE',
'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK',
'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START',
'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START',
'GL2C_PERF_SEL_ATOMIC', 'GL2C_PERF_SEL_BUBBLE',
'GL2C_PERF_SEL_BUSY', 'GL2C_PERF_SEL_BYPASS_REQ',
'GL2C_PERF_SEL_CLIENT0_REQ', 'GL2C_PERF_SEL_CLIENT10_REQ',
'GL2C_PERF_SEL_CLIENT11_REQ', 'GL2C_PERF_SEL_CLIENT12_REQ',
'GL2C_PERF_SEL_CLIENT13_REQ', 'GL2C_PERF_SEL_CLIENT14_REQ',
'GL2C_PERF_SEL_CLIENT15_REQ', 'GL2C_PERF_SEL_CLIENT1_REQ',
'GL2C_PERF_SEL_CLIENT2_REQ', 'GL2C_PERF_SEL_CLIENT3_REQ',
'GL2C_PERF_SEL_CLIENT4_REQ', 'GL2C_PERF_SEL_CLIENT5_REQ',
'GL2C_PERF_SEL_CLIENT6_REQ', 'GL2C_PERF_SEL_CLIENT7_REQ',
'GL2C_PERF_SEL_CLIENT8_REQ', 'GL2C_PERF_SEL_CLIENT9_REQ',
'GL2C_PERF_SEL_CM_CHANNEL0_REQ', 'GL2C_PERF_SEL_CM_CHANNEL10_REQ',
'GL2C_PERF_SEL_CM_CHANNEL11_REQ',
'GL2C_PERF_SEL_CM_CHANNEL12_REQ',
'GL2C_PERF_SEL_CM_CHANNEL13_REQ',
'GL2C_PERF_SEL_CM_CHANNEL14_REQ',
'GL2C_PERF_SEL_CM_CHANNEL15_REQ',
'GL2C_PERF_SEL_CM_CHANNEL16_REQ',
'GL2C_PERF_SEL_CM_CHANNEL17_REQ',
'GL2C_PERF_SEL_CM_CHANNEL18_REQ',
'GL2C_PERF_SEL_CM_CHANNEL19_REQ', 'GL2C_PERF_SEL_CM_CHANNEL1_REQ',
'GL2C_PERF_SEL_CM_CHANNEL20_REQ',
'GL2C_PERF_SEL_CM_CHANNEL21_REQ',
'GL2C_PERF_SEL_CM_CHANNEL22_REQ',
'GL2C_PERF_SEL_CM_CHANNEL23_REQ',
'GL2C_PERF_SEL_CM_CHANNEL24_REQ',
'GL2C_PERF_SEL_CM_CHANNEL25_REQ',
'GL2C_PERF_SEL_CM_CHANNEL26_REQ',
'GL2C_PERF_SEL_CM_CHANNEL27_REQ',
'GL2C_PERF_SEL_CM_CHANNEL28_REQ',
'GL2C_PERF_SEL_CM_CHANNEL29_REQ', 'GL2C_PERF_SEL_CM_CHANNEL2_REQ',
'GL2C_PERF_SEL_CM_CHANNEL30_REQ',
'GL2C_PERF_SEL_CM_CHANNEL31_REQ', 'GL2C_PERF_SEL_CM_CHANNEL3_REQ',
'GL2C_PERF_SEL_CM_CHANNEL4_REQ', 'GL2C_PERF_SEL_CM_CHANNEL5_REQ',
'GL2C_PERF_SEL_CM_CHANNEL6_REQ', 'GL2C_PERF_SEL_CM_CHANNEL7_REQ',
'GL2C_PERF_SEL_CM_CHANNEL8_REQ', 'GL2C_PERF_SEL_CM_CHANNEL9_REQ',
'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ',
'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ',
'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ',
'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ',
'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ',
'GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ',
'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ',
'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ',
'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ',
'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ',
'GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ',
'GL2C_PERF_SEL_CM_COMP_READ_REQ',
'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ',
'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ',
'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ',
'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ',
'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ',
'GL2C_PERF_SEL_CM_DCC_IN_XFC', 'GL2C_PERF_SEL_CM_DCC_OUT_1x1',
'GL2C_PERF_SEL_CM_DCC_OUT_1x2', 'GL2C_PERF_SEL_CM_DCC_OUT_2x1',
'GL2C_PERF_SEL_CM_DCC_OUT_2x2', 'GL2C_PERF_SEL_CM_DCC_OUT_CONST',
'GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP', 'GL2C_PERF_SEL_CM_DCC_OUT_XFC',
'GL2C_PERF_SEL_CM_DCC_STALL', 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ',
'GL2C_PERF_SEL_CM_MERGE_BUF_FULL',
'GL2C_PERF_SEL_CM_METADATA_WR_REQ', 'GL2C_PERF_SEL_CM_NOOP_REQ',
'GL2C_PERF_SEL_CM_NO_ACK_REQ', 'GL2C_PERF_SEL_CM_READ_BACK_REQ',
'GL2C_PERF_SEL_CM_RVF_FULL', 'GL2C_PERF_SEL_CM_SDR_FULL',
'GL2C_PERF_SEL_CM_WR_ACK_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ',
'GL2C_PERF_SEL_COMPRESSED_READ_REQ', 'GL2C_PERF_SEL_CYCLE',
'GL2C_PERF_SEL_C_RO_S_REQ', 'GL2C_PERF_SEL_C_RO_US_REQ',
'GL2C_PERF_SEL_C_RW_S_REQ', 'GL2C_PERF_SEL_C_RW_US_REQ',
'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'GL2C_PERF_SEL_EA_ATOMIC',
'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', 'GL2C_PERF_SEL_EA_OUTSTANDING',
'GL2C_PERF_SEL_EA_RDREQ_128B', 'GL2C_PERF_SEL_EA_RDREQ_32B',
'GL2C_PERF_SEL_EA_RDREQ_64B', 'GL2C_PERF_SEL_EA_RDREQ_96B',
'GL2C_PERF_SEL_EA_RDREQ_DRAM', 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B',
'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL',
'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL',
'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL',
'GL2C_PERF_SEL_EA_RDREQ_SNOOP', 'GL2C_PERF_SEL_EA_RDREQ_SPLIT',
'GL2C_PERF_SEL_EA_RDRET_NACK',
'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B',
'GL2C_PERF_SEL_EA_RD_MDC_32B', 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B',
'GL2C_PERF_SEL_EA_WRREQ_64B', 'GL2C_PERF_SEL_EA_WRREQ_DRAM',
'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B',
'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL',
'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL',
'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL',
'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND',
'GL2C_PERF_SEL_EA_WRREQ_SNOOP', 'GL2C_PERF_SEL_EA_WRRET_NACK',
'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', 'GL2C_PERF_SEL_EVICT',
'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', 'GL2C_PERF_SEL_FULL_HIT',
'GL2C_PERF_SEL_GARLIC_READ', 'GL2C_PERF_SEL_GARLIC_WRITE',
'GL2C_PERF_SEL_GCR_ALL', 'GL2C_PERF_SEL_GCR_DISCARD',
'GL2C_PERF_SEL_GCR_GL2_INV_ALL',
'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', 'GL2C_PERF_SEL_GCR_GL2_WB_ALL',
'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE',
'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', 'GL2C_PERF_SEL_GCR_INV',
'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE',
'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT',
'GL2C_PERF_SEL_GCR_INVL2_VOL_START', 'GL2C_PERF_SEL_GCR_MDC_INV',
'GL2C_PERF_SEL_GCR_MDC_INV_ALL',
'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', 'GL2C_PERF_SEL_GCR_RANGE',
'GL2C_PERF_SEL_GCR_UNSHARED', 'GL2C_PERF_SEL_GCR_VOL',
'GL2C_PERF_SEL_GCR_WB', 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE',
'GL2C_PERF_SEL_GCR_WBINVL2_EVICT',
'GL2C_PERF_SEL_GCR_WBINVL2_START',
'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE',
'GL2C_PERF_SEL_GCR_WBL2_VOL_START', 'GL2C_PERF_SEL_GL2A_LEVEL',
'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', 'GL2C_PERF_SEL_HIT',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8',
'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9',
'GL2C_PERF_SEL_IB_CM_STALL', 'GL2C_PERF_SEL_IB_REQ',
'GL2C_PERF_SEL_IB_STALL', 'GL2C_PERF_SEL_IB_TAG_STALL',
'GL2C_PERF_SEL_INTERNAL_PROBE', 'GL2C_PERF_SEL_IO_READ',
'GL2C_PERF_SEL_IO_WRITE', 'GL2C_PERF_SEL_LATENCY_FIFO_FULL',
'GL2C_PERF_SEL_LRU_REQ', 'GL2C_PERF_SEL_MC_RDREQ',
'GL2C_PERF_SEL_MC_RDREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ',
'GL2C_PERF_SEL_MC_WRREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ_STALL',
'GL2C_PERF_SEL_MDC_INV_METADATA', 'GL2C_PERF_SEL_MDC_LEVEL',
'GL2C_PERF_SEL_MDC_REQ', 'GL2C_PERF_SEL_MDC_SECTOR_HIT',
'GL2C_PERF_SEL_MDC_SECTOR_MISS',
'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL',
'GL2C_PERF_SEL_MDC_TAG_HIT',
'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL',
'GL2C_PERF_SEL_MDC_TAG_STALL',
'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL',
'GL2C_PERF_SEL_METADATA_READ_REQ', 'GL2C_PERF_SEL_MISS',
'GL2C_PERF_SEL_NOA_REQ', 'GL2C_PERF_SEL_NONE',
'GL2C_PERF_SEL_NOP_ACK', 'GL2C_PERF_SEL_NOP_RTN0',
'GL2C_PERF_SEL_NORMAL_EVICT', 'GL2C_PERF_SEL_NORMAL_WRITEBACK',
'GL2C_PERF_SEL_ONION_READ', 'GL2C_PERF_SEL_ONION_WRITE',
'GL2C_PERF_SEL_PARTIAL_32B_HIT', 'GL2C_PERF_SEL_PARTIAL_64B_HIT',
'GL2C_PERF_SEL_PARTIAL_96B_HIT', 'GL2C_PERF_SEL_PROBE',
'GL2C_PERF_SEL_PROBE_ALL', 'GL2C_PERF_SEL_PROBE_EVICT',
'GL2C_PERF_SEL_PROBE_FILTER_DISABLED',
'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION',
'GL2C_PERF_SEL_READ', 'GL2C_PERF_SEL_READ_128_REQ',
'GL2C_PERF_SEL_READ_32_REQ', 'GL2C_PERF_SEL_READ_64_REQ',
'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE',
'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', 'GL2C_PERF_SEL_REQ',
'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', 'GL2C_PERF_SEL_RETURN_ACK',
'GL2C_PERF_SEL_RETURN_DATA', 'GL2C_PERF_SEL_SHARED_REQ',
'GL2C_PERF_SEL_SRC_FIFO_FULL', 'GL2C_PERF_SEL_STREAM_REQ',
'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL',
'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL',
'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL',
'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL',
'GL2C_PERF_SEL_TAG_PROBE_STALL',
'GL2C_PERF_SEL_TAG_READ_DST_STALL', 'GL2C_PERF_SEL_TAG_STALL',
'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL',
'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL',
'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 'GL2C_PERF_SEL_UC_REQ',
'GL2C_PERF_SEL_UNCACHED_WRITE', 'GL2C_PERF_SEL_VOL_REQ',
'GL2C_PERF_SEL_WRITE', 'GL2C_PERF_SEL_WRITEBACK',
'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT',
'GL2C_PERF_SEL_WRITE_32_REQ', 'GL2C_PERF_SEL_WRITE_64_REQ',
'GL2_CACHE_POLICIES', 'GL2_CACHE_POLICY_BYPASS',
'GL2_CACHE_POLICY_LRU', 'GL2_CACHE_POLICY_NOA',
'GL2_CACHE_POLICY_STREAM', 'GL2_EA_CID', 'GL2_EA_CID_CLIENT',
'GL2_EA_CID_CP', 'GL2_EA_CID_CPDMA', 'GL2_EA_CID_DCC',
'GL2_EA_CID_FMASK', 'GL2_EA_CID_HTILE', 'GL2_EA_CID_MES',
'GL2_EA_CID_RLC', 'GL2_EA_CID_RT', 'GL2_EA_CID_SDMA',
'GL2_EA_CID_SQC', 'GL2_EA_CID_TCPMETA', 'GL2_EA_CID_UTCL2',
'GL2_EA_CID_ZPCPSD', 'GL2_EA_CID_Z_STENCIL', 'GL2_NACKS',
'GL2_NACK_DATA_ERROR', 'GL2_NACK_NO_FAULT', 'GL2_NACK_PAGE_FAULT',
'GL2_NACK_PROTECTION_FAULT', 'GL2_OP', 'GL2_OP_ATOMIC_ADD_32',
'GL2_OP_ATOMIC_ADD_64', 'GL2_OP_ATOMIC_ADD_RTN_32',
'GL2_OP_ATOMIC_ADD_RTN_64', 'GL2_OP_ATOMIC_AND_32',
'GL2_OP_ATOMIC_AND_64', 'GL2_OP_ATOMIC_AND_RTN_32',
'GL2_OP_ATOMIC_AND_RTN_64', 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32',
'GL2_OP_ATOMIC_CMPSWAP_32', 'GL2_OP_ATOMIC_CMPSWAP_64',
'GL2_OP_ATOMIC_CMPSWAP_RTN_32', 'GL2_OP_ATOMIC_CMPSWAP_RTN_64',
'GL2_OP_ATOMIC_DEC_32', 'GL2_OP_ATOMIC_DEC_64',
'GL2_OP_ATOMIC_DEC_RTN_32', 'GL2_OP_ATOMIC_DEC_RTN_64',
'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32',
'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32',
'GL2_OP_ATOMIC_FCMPSWAP_32', 'GL2_OP_ATOMIC_FCMPSWAP_64',
'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32',
'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64',
'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32',
'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64',
'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64',
'GL2_OP_ATOMIC_FMAX_32', 'GL2_OP_ATOMIC_FMAX_64',
'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32',
'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64',
'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32',
'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64',
'GL2_OP_ATOMIC_FMAX_RTN_32', 'GL2_OP_ATOMIC_FMAX_RTN_64',
'GL2_OP_ATOMIC_FMIN_32', 'GL2_OP_ATOMIC_FMIN_64',
'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32',
'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64',
'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32',
'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64',
'GL2_OP_ATOMIC_FMIN_RTN_32', 'GL2_OP_ATOMIC_FMIN_RTN_64',
'GL2_OP_ATOMIC_INC_32', 'GL2_OP_ATOMIC_INC_64',
'GL2_OP_ATOMIC_INC_RTN_32', 'GL2_OP_ATOMIC_INC_RTN_64',
'GL2_OP_ATOMIC_OR_32', 'GL2_OP_ATOMIC_OR_64',
'GL2_OP_ATOMIC_OR_RTN_32', 'GL2_OP_ATOMIC_OR_RTN_64',
'GL2_OP_ATOMIC_SMAX_32', 'GL2_OP_ATOMIC_SMAX_64',
'GL2_OP_ATOMIC_SMAX_RTN_32', 'GL2_OP_ATOMIC_SMAX_RTN_64',
'GL2_OP_ATOMIC_SMIN_32', 'GL2_OP_ATOMIC_SMIN_64',
'GL2_OP_ATOMIC_SMIN_RTN_32', 'GL2_OP_ATOMIC_SMIN_RTN_64',
'GL2_OP_ATOMIC_SUB_32', 'GL2_OP_ATOMIC_SUB_64',
'GL2_OP_ATOMIC_SUB_RTN_32', 'GL2_OP_ATOMIC_SUB_RTN_64',
'GL2_OP_ATOMIC_SWAP_32', 'GL2_OP_ATOMIC_SWAP_64',
'GL2_OP_ATOMIC_SWAP_RTN_32', 'GL2_OP_ATOMIC_SWAP_RTN_64',
'GL2_OP_ATOMIC_UMAX_32', 'GL2_OP_ATOMIC_UMAX_64',
'GL2_OP_ATOMIC_UMAX_8', 'GL2_OP_ATOMIC_UMAX_RTN_32',
'GL2_OP_ATOMIC_UMAX_RTN_64', 'GL2_OP_ATOMIC_UMIN_32',
'GL2_OP_ATOMIC_UMIN_64', 'GL2_OP_ATOMIC_UMIN_8',
'GL2_OP_ATOMIC_UMIN_RTN_32', 'GL2_OP_ATOMIC_UMIN_RTN_64',
'GL2_OP_ATOMIC_XOR_32', 'GL2_OP_ATOMIC_XOR_64',
'GL2_OP_ATOMIC_XOR_RTN_32', 'GL2_OP_ATOMIC_XOR_RTN_64',
'GL2_OP_GL1_INV', 'GL2_OP_MASKS', 'GL2_OP_MASK_64',
'GL2_OP_MASK_FLUSH_DENROM', 'GL2_OP_MASK_NO_RTN',
'GL2_OP_NOP_ACK', 'GL2_OP_NOP_RTN0', 'GL2_OP_PROBE_FILTER',
'GL2_OP_READ', 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2',
'GL2_OP_WRITE', 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE',
'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL',
'GLOBAL_STATUS_FLUSH_STATUS',
'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED',
'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED',
'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA',
'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA',
'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA',
'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA',
'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA',
'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO',
'GRBM_PERF_SEL', 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY',
'GRBM_PERF_SEL_BCI_BUSY', 'GRBM_PERF_SEL_CB_BUSY',
'GRBM_PERF_SEL_CB_CLEAN', 'GRBM_PERF_SEL_CH_BUSY',
'GRBM_PERF_SEL_COUNT', 'GRBM_PERF_SEL_CPAXI_BUSY',
'GRBM_PERF_SEL_CPC_BUSY', 'GRBM_PERF_SEL_CPF_BUSY',
'GRBM_PERF_SEL_CPG_BUSY', 'GRBM_PERF_SEL_CP_BUSY',
'GRBM_PERF_SEL_CP_COHER_BUSY', 'GRBM_PERF_SEL_CP_DMA_BUSY',
'GRBM_PERF_SEL_DB_BUSY', 'GRBM_PERF_SEL_DB_CLEAN',
'GRBM_PERF_SEL_EA_BUSY', 'GRBM_PERF_SEL_GDS_BUSY',
'GRBM_PERF_SEL_GE_BUSY', 'GRBM_PERF_SEL_GE_NO_DMA_BUSY',
'GRBM_PERF_SEL_GL1CC_BUSY', 'GRBM_PERF_SEL_GL1H_BUSY',
'GRBM_PERF_SEL_GL2CC_BUSY', 'GRBM_PERF_SEL_GUI_ACTIVE',
'GRBM_PERF_SEL_GUS_BUSY', 'GRBM_PERF_SEL_PA_BUSY',
'GRBM_PERF_SEL_PC_BUSY', 'GRBM_PERF_SEL_PH_BUSY',
'GRBM_PERF_SEL_PMM_BUSY', 'GRBM_PERF_SEL_RLC_BUSY',
'GRBM_PERF_SEL_RMI_BUSY', 'GRBM_PERF_SEL_SC_BUSY',
'GRBM_PERF_SEL_SDMA_BUSY', 'GRBM_PERF_SEL_SPI_BUSY',
'GRBM_PERF_SEL_SX_BUSY', 'GRBM_PERF_SEL_TA_BUSY',
'GRBM_PERF_SEL_TCP_BUSY', 'GRBM_PERF_SEL_USER_DEFINED',
'GRBM_PERF_SEL_UTCL1_BUSY', 'GRBM_PERF_SEL_UTCL2_BUSY',
'GRBM_SE0_PERF_SEL', 'GRBM_SE0_PERF_SEL_BCI_BUSY',
'GRBM_SE0_PERF_SEL_CB_BUSY', 'GRBM_SE0_PERF_SEL_CB_CLEAN',
'GRBM_SE0_PERF_SEL_COUNT', 'GRBM_SE0_PERF_SEL_DB_BUSY',
'GRBM_SE0_PERF_SEL_DB_CLEAN', 'GRBM_SE0_PERF_SEL_GL1CC_BUSY',
'GRBM_SE0_PERF_SEL_GL1H_BUSY', 'GRBM_SE0_PERF_SEL_PA_BUSY',
'GRBM_SE0_PERF_SEL_PC_BUSY', 'GRBM_SE0_PERF_SEL_RMI_BUSY',
'GRBM_SE0_PERF_SEL_SC_BUSY', 'GRBM_SE0_PERF_SEL_SPI_BUSY',
'GRBM_SE0_PERF_SEL_SX_BUSY', 'GRBM_SE0_PERF_SEL_TA_BUSY',
'GRBM_SE0_PERF_SEL_TCP_BUSY', 'GRBM_SE0_PERF_SEL_USER_DEFINED',
'GRBM_SE0_PERF_SEL_UTCL1_BUSY', 'GRBM_SE1_PERF_SEL',
'GRBM_SE1_PERF_SEL_BCI_BUSY', 'GRBM_SE1_PERF_SEL_CB_BUSY',
'GRBM_SE1_PERF_SEL_CB_CLEAN', 'GRBM_SE1_PERF_SEL_COUNT',
'GRBM_SE1_PERF_SEL_DB_BUSY', 'GRBM_SE1_PERF_SEL_DB_CLEAN',
'GRBM_SE1_PERF_SEL_GL1CC_BUSY', 'GRBM_SE1_PERF_SEL_GL1H_BUSY',
'GRBM_SE1_PERF_SEL_PA_BUSY', 'GRBM_SE1_PERF_SEL_PC_BUSY',
'GRBM_SE1_PERF_SEL_RMI_BUSY', 'GRBM_SE1_PERF_SEL_SC_BUSY',
'GRBM_SE1_PERF_SEL_SPI_BUSY', 'GRBM_SE1_PERF_SEL_SX_BUSY',
'GRBM_SE1_PERF_SEL_TA_BUSY', 'GRBM_SE1_PERF_SEL_TCP_BUSY',
'GRBM_SE1_PERF_SEL_USER_DEFINED', 'GRBM_SE1_PERF_SEL_UTCL1_BUSY',
'GRBM_SE2_PERF_SEL', 'GRBM_SE2_PERF_SEL_BCI_BUSY',
'GRBM_SE2_PERF_SEL_CB_BUSY', 'GRBM_SE2_PERF_SEL_CB_CLEAN',
'GRBM_SE2_PERF_SEL_COUNT', 'GRBM_SE2_PERF_SEL_DB_BUSY',
'GRBM_SE2_PERF_SEL_DB_CLEAN', 'GRBM_SE2_PERF_SEL_GL1CC_BUSY',
'GRBM_SE2_PERF_SEL_GL1H_BUSY', 'GRBM_SE2_PERF_SEL_PA_BUSY',
'GRBM_SE2_PERF_SEL_PC_BUSY', 'GRBM_SE2_PERF_SEL_RMI_BUSY',
'GRBM_SE2_PERF_SEL_SC_BUSY', 'GRBM_SE2_PERF_SEL_SPI_BUSY',
'GRBM_SE2_PERF_SEL_SX_BUSY', 'GRBM_SE2_PERF_SEL_TA_BUSY',
'GRBM_SE2_PERF_SEL_TCP_BUSY', 'GRBM_SE2_PERF_SEL_USER_DEFINED',
'GRBM_SE2_PERF_SEL_UTCL1_BUSY', 'GRBM_SE3_PERF_SEL',
'GRBM_SE3_PERF_SEL_BCI_BUSY', 'GRBM_SE3_PERF_SEL_CB_BUSY',
'GRBM_SE3_PERF_SEL_CB_CLEAN', 'GRBM_SE3_PERF_SEL_COUNT',
'GRBM_SE3_PERF_SEL_DB_BUSY', 'GRBM_SE3_PERF_SEL_DB_CLEAN',
'GRBM_SE3_PERF_SEL_GL1CC_BUSY', 'GRBM_SE3_PERF_SEL_GL1H_BUSY',
'GRBM_SE3_PERF_SEL_PA_BUSY', 'GRBM_SE3_PERF_SEL_PC_BUSY',
'GRBM_SE3_PERF_SEL_RMI_BUSY', 'GRBM_SE3_PERF_SEL_SC_BUSY',
'GRBM_SE3_PERF_SEL_SPI_BUSY', 'GRBM_SE3_PERF_SEL_SX_BUSY',
'GRBM_SE3_PERF_SEL_TA_BUSY', 'GRBM_SE3_PERF_SEL_TCP_BUSY',
'GRBM_SE3_PERF_SEL_USER_DEFINED', 'GRBM_SE3_PERF_SEL_UTCL1_BUSY',
'GRBM_SE4_PERF_SEL', 'GRBM_SE4_PERF_SEL_BCI_BUSY',
'GRBM_SE4_PERF_SEL_CB_BUSY', 'GRBM_SE4_PERF_SEL_CB_CLEAN',
'GRBM_SE4_PERF_SEL_COUNT', 'GRBM_SE4_PERF_SEL_DB_BUSY',
'GRBM_SE4_PERF_SEL_DB_CLEAN', 'GRBM_SE4_PERF_SEL_GL1CC_BUSY',
'GRBM_SE4_PERF_SEL_GL1H_BUSY', 'GRBM_SE4_PERF_SEL_PA_BUSY',
'GRBM_SE4_PERF_SEL_PC_BUSY', 'GRBM_SE4_PERF_SEL_RMI_BUSY',
'GRBM_SE4_PERF_SEL_SC_BUSY', 'GRBM_SE4_PERF_SEL_SPI_BUSY',
'GRBM_SE4_PERF_SEL_SX_BUSY', 'GRBM_SE4_PERF_SEL_TA_BUSY',
'GRBM_SE4_PERF_SEL_TCP_BUSY', 'GRBM_SE4_PERF_SEL_USER_DEFINED',
'GRBM_SE4_PERF_SEL_UTCL1_BUSY', 'GRBM_SE5_PERF_SEL',
'GRBM_SE5_PERF_SEL_BCI_BUSY', 'GRBM_SE5_PERF_SEL_CB_BUSY',
'GRBM_SE5_PERF_SEL_CB_CLEAN', 'GRBM_SE5_PERF_SEL_COUNT',
'GRBM_SE5_PERF_SEL_DB_BUSY', 'GRBM_SE5_PERF_SEL_DB_CLEAN',
'GRBM_SE5_PERF_SEL_GL1CC_BUSY', 'GRBM_SE5_PERF_SEL_GL1H_BUSY',
'GRBM_SE5_PERF_SEL_PA_BUSY', 'GRBM_SE5_PERF_SEL_PC_BUSY',
'GRBM_SE5_PERF_SEL_RMI_BUSY', 'GRBM_SE5_PERF_SEL_SC_BUSY',
'GRBM_SE5_PERF_SEL_SPI_BUSY', 'GRBM_SE5_PERF_SEL_SX_BUSY',
'GRBM_SE5_PERF_SEL_TA_BUSY', 'GRBM_SE5_PERF_SEL_TCP_BUSY',
'GRBM_SE5_PERF_SEL_USER_DEFINED', 'GRBM_SE5_PERF_SEL_UTCL1_BUSY',
'GRBM_SE6_PERF_SEL', 'GRBM_SE6_PERF_SEL_BCI_BUSY',
'GRBM_SE6_PERF_SEL_CB_BUSY', 'GRBM_SE6_PERF_SEL_CB_CLEAN',
'GRBM_SE6_PERF_SEL_COUNT', 'GRBM_SE6_PERF_SEL_DB_BUSY',
'GRBM_SE6_PERF_SEL_DB_CLEAN', 'GRBM_SE6_PERF_SEL_GL1CC_BUSY',
'GRBM_SE6_PERF_SEL_GL1H_BUSY', 'GRBM_SE6_PERF_SEL_PA_BUSY',
'GRBM_SE6_PERF_SEL_PC_BUSY', 'GRBM_SE6_PERF_SEL_RMI_BUSY',
'GRBM_SE6_PERF_SEL_SC_BUSY', 'GRBM_SE6_PERF_SEL_SPI_BUSY',
'GRBM_SE6_PERF_SEL_SX_BUSY', 'GRBM_SE6_PERF_SEL_TA_BUSY',
'GRBM_SE6_PERF_SEL_TCP_BUSY', 'GRBM_SE6_PERF_SEL_USER_DEFINED',
'GRBM_SE6_PERF_SEL_UTCL1_BUSY', 'GRBM_SE7_PERF_SEL',
'GRBM_SE7_PERF_SEL_BCI_BUSY', 'GRBM_SE7_PERF_SEL_CB_BUSY',
'GRBM_SE7_PERF_SEL_CB_CLEAN', 'GRBM_SE7_PERF_SEL_COUNT',
'GRBM_SE7_PERF_SEL_DB_BUSY', 'GRBM_SE7_PERF_SEL_DB_CLEAN',
'GRBM_SE7_PERF_SEL_GL1CC_BUSY', 'GRBM_SE7_PERF_SEL_GL1H_BUSY',
'GRBM_SE7_PERF_SEL_PA_BUSY', 'GRBM_SE7_PERF_SEL_PC_BUSY',
'GRBM_SE7_PERF_SEL_RMI_BUSY', 'GRBM_SE7_PERF_SEL_SC_BUSY',
'GRBM_SE7_PERF_SEL_SPI_BUSY', 'GRBM_SE7_PERF_SEL_SX_BUSY',
'GRBM_SE7_PERF_SEL_TA_BUSY', 'GRBM_SE7_PERF_SEL_TCP_BUSY',
'GRBM_SE7_PERF_SEL_USER_DEFINED', 'GRBM_SE7_PERF_SEL_UTCL1_BUSY',
'GREEN_LUT', 'GSTHREADID_SIZE', 'GS_OFF', 'GS_SCENARIO_A',
'GS_SCENARIO_B', 'GS_SCENARIO_C', 'GS_SCENARIO_G', 'GS_STAGE_OFF',
'GS_STAGE_ON', 'HDA_BASE', 'HDA_BASE__INST0_SEG0',
'HDA_BASE__INST0_SEG1', 'HDA_BASE__INST0_SEG2',
'HDA_BASE__INST0_SEG3', 'HDA_BASE__INST0_SEG4',
'HDA_BASE__INST1_SEG0', 'HDA_BASE__INST1_SEG1',
'HDA_BASE__INST1_SEG2', 'HDA_BASE__INST1_SEG3',
'HDA_BASE__INST1_SEG4', 'HDA_BASE__INST2_SEG0',
'HDA_BASE__INST2_SEG1', 'HDA_BASE__INST2_SEG2',
'HDA_BASE__INST2_SEG3', 'HDA_BASE__INST2_SEG4',
'HDA_BASE__INST3_SEG0', 'HDA_BASE__INST3_SEG1',
'HDA_BASE__INST3_SEG2', 'HDA_BASE__INST3_SEG3',
'HDA_BASE__INST3_SEG4', 'HDA_BASE__INST4_SEG0',
'HDA_BASE__INST4_SEG1', 'HDA_BASE__INST4_SEG2',
'HDA_BASE__INST4_SEG3', 'HDA_BASE__INST4_SEG4',
'HDA_BASE__INST5_SEG0', 'HDA_BASE__INST5_SEG1',
'HDA_BASE__INST5_SEG2', 'HDA_BASE__INST5_SEG3',
'HDA_BASE__INST5_SEG4', 'HDA_BASE__INST6_SEG0',
'HDA_BASE__INST6_SEG1', 'HDA_BASE__INST6_SEG2',
'HDA_BASE__INST6_SEG3', 'HDA_BASE__INST6_SEG4',
'HDMICHARCLK_SRC_SEL', 'HDMICHARCLK_SRC_SEL_SRC_RESERVED',
'HDMICHARCLK_SRC_SEL_UNIPHYA', 'HDMICHARCLK_SRC_SEL_UNIPHYB',
'HDMICHARCLK_SRC_SEL_UNIPHYC', 'HDMICHARCLK_SRC_SEL_UNIPHYD',
'HDMICHARCLK_SRC_SEL_UNIPHYE', 'HDMISTREAMCLK_DTO_FORCE_DIS',
'HDMISTREAMCLK_SRC_SEL', 'HDMI_ACP_NOT_SEND', 'HDMI_ACP_PKT_SEND',
'HDMI_ACP_SEND', 'HDMI_ACR_0_MULTIPLE_RESERVED',
'HDMI_ACR_1_MULTIPLE', 'HDMI_ACR_2_MULTIPLE',
'HDMI_ACR_3_MULTIPLE_RESERVED', 'HDMI_ACR_4_MULTIPLE',
'HDMI_ACR_5_MULTIPLE_RESERVED', 'HDMI_ACR_6_MULTIPLE_RESERVED',
'HDMI_ACR_7_MULTIPLE_RESERVED', 'HDMI_ACR_AUDIO_PRIORITY',
'HDMI_ACR_CONT', 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE',
'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE',
'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE',
'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K',
'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K',
'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE',
'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW',
'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK',
'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN',
'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT',
'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE',
'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND',
'HDMI_AUDIO_INFO_SEND',
'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT',
'HDMI_BORROW_MODE', 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE',
'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE',
'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DATA_SCRAMBLE_DISABLE',
'HDMI_DATA_SCRAMBLE_EN', 'HDMI_DATA_SCRAMBLE_ENABLE',
'HDMI_DEEP_COLOR_DEPTH', 'HDMI_DEEP_COLOR_DEPTH_24BPP',
'HDMI_DEEP_COLOR_DEPTH_30BPP', 'HDMI_DEEP_COLOR_DEPTH_36BPP',
'HDMI_DEEP_COLOR_DEPTH_48BPP', 'HDMI_DEFAULT_PAHSE',
'HDMI_DEFAULT_PHASE_IS_0', 'HDMI_DEFAULT_PHASE_IS_1',
'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', 'HDMI_ERROR_MASK',
'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK',
'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE',
'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_FRL',
'HDMI_GC_AVMUTE', 'HDMI_GC_AVMUTE_CONT',
'HDMI_GC_AVMUTE_CONT_DISABLE', 'HDMI_GC_AVMUTE_CONT_ENABLE',
'HDMI_GC_AVMUTE_SET', 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT',
'HDMI_GC_CONT_DISABLE', 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND',
'HDMI_GC_PKT_SEND', 'HDMI_GC_SEND', 'HDMI_GENERIC_CONT',
'HDMI_GENERIC_CONT_DISABLE', 'HDMI_GENERIC_CONT_ENABLE',
'HDMI_GENERIC_NOT_SEND', 'HDMI_GENERIC_PKT_SEND',
'HDMI_GENERIC_SEND', 'HDMI_ISRC_CONT', 'HDMI_ISRC_CONT_DISABLE',
'HDMI_ISRC_CONT_ENABLE', 'HDMI_ISRC_NOT_SEND',
'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND',
'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC',
'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE',
'HDMI_METADATA_ENABLE', 'HDMI_METADATA_NOT_SEND',
'HDMI_METADATA_PKT_SEND', 'HDMI_MPEG_INFO_CONT',
'HDMI_MPEG_INFO_CONT_DISABLE', 'HDMI_MPEG_INFO_CONT_ENABLE',
'HDMI_MPEG_INFO_NOT_SEND', 'HDMI_MPEG_INFO_PKT_SEND',
'HDMI_MPEG_INFO_SEND', 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS',
'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND',
'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION',
'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD',
'HDMI_PACKET_LINE_REFERENCE', 'HDMI_PACKING_PHASE_OVERRIDE',
'HDMI_PACKING_PHASE_SET_BY_HW', 'HDMI_PACKING_PHASE_SET_BY_SW',
'HDMI_PKT_LINE_REF_OTGSOF', 'HDMI_PKT_LINE_REF_VSYNC',
'HDMI_SEND_MAX_AUDIO_PACKETS', 'HDMI_STREAM_ENC_DB_DISABLE',
'HDMI_STREAM_ENC_DB_DISABLE_CONTROL', 'HDMI_STREAM_ENC_DB_ENABLE',
'HDMI_STREAM_ENC_DCCG', 'HDMI_STREAM_ENC_DISABLE',
'HDMI_STREAM_ENC_DISPLAY_PIPE', 'HDMI_STREAM_ENC_DSC_MODE',
'HDMI_STREAM_ENC_ENABLE', 'HDMI_STREAM_ENC_ENABLE_CONTROL',
'HDMI_STREAM_ENC_HARDWARE', 'HDMI_STREAM_ENC_NOT_RESET',
'HDMI_STREAM_ENC_NO_ERROR_OCCURRED',
'HDMI_STREAM_ENC_ODM_COMBINE_MODE',
'HDMI_STREAM_ENC_OVERFLOW_OCCURRED',
'HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR',
'HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT',
'HDMI_STREAM_ENC_PIXEL_ENCODING', 'HDMI_STREAM_ENC_PROGRAMMABLE',
'HDMI_STREAM_ENC_READ_CLOCK_CONTROL', 'HDMI_STREAM_ENC_RESET',
'HDMI_STREAM_ENC_RESET_CONTROL', 'HDMI_STREAM_ENC_STREAM_ACTIVE',
'HDMI_STREAM_ENC_UNDERFLOW_OCCURRED',
'HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE',
'HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', 'HDMI_TB_ENC_ACP_SEND',
'HDMI_TB_ENC_ACR_AUDIO_PRIORITY', 'HDMI_TB_ENC_ACR_CONT',
'HDMI_TB_ENC_ACR_N_MULTIPLE', 'HDMI_TB_ENC_ACR_SELECT',
'HDMI_TB_ENC_ACR_SEND', 'HDMI_TB_ENC_ACR_SOURCE',
'HDMI_TB_ENC_AUDIO_INFO_CONT', 'HDMI_TB_ENC_AUDIO_INFO_SEND',
'HDMI_TB_ENC_CRC_SRC_SEL', 'HDMI_TB_ENC_CRC_TYPE',
'HDMI_TB_ENC_DEEP_COLOR_DEPTH', 'HDMI_TB_ENC_DEFAULT_PAHSE',
'HDMI_TB_ENC_DSC_MODE', 'HDMI_TB_ENC_ENABLE',
'HDMI_TB_ENC_GC_AVMUTE', 'HDMI_TB_ENC_GC_AVMUTE_CONT',
'HDMI_TB_ENC_GC_CONT', 'HDMI_TB_ENC_GC_SEND',
'HDMI_TB_ENC_GENERIC_CONT', 'HDMI_TB_ENC_GENERIC_LOCK_DISABLE',
'HDMI_TB_ENC_GENERIC_LOCK_EN', 'HDMI_TB_ENC_GENERIC_LOCK_ENABLE',
'HDMI_TB_ENC_GENERIC_SEND', 'HDMI_TB_ENC_ISRC_CONT',
'HDMI_TB_ENC_ISRC_SEND', 'HDMI_TB_ENC_METADATA_ENABLE',
'HDMI_TB_ENC_PACKET_LINE_REFERENCE', 'HDMI_TB_ENC_PIXEL_ENCODING',
'HDMI_TB_ENC_RESET', 'HDMI_TB_ENC_SYNC_PHASE',
'HDMI_TMDS_OR_DP_8B10B', 'HDP_BASE', 'HDP_BASE__INST0_SEG0',
'HDP_BASE__INST0_SEG1', 'HDP_BASE__INST0_SEG2',
'HDP_BASE__INST0_SEG3', 'HDP_BASE__INST0_SEG4',
'HDP_BASE__INST1_SEG0', 'HDP_BASE__INST1_SEG1',
'HDP_BASE__INST1_SEG2', 'HDP_BASE__INST1_SEG3',
'HDP_BASE__INST1_SEG4', 'HDP_BASE__INST2_SEG0',
'HDP_BASE__INST2_SEG1', 'HDP_BASE__INST2_SEG2',
'HDP_BASE__INST2_SEG3', 'HDP_BASE__INST2_SEG4',
'HDP_BASE__INST3_SEG0', 'HDP_BASE__INST3_SEG1',
'HDP_BASE__INST3_SEG2', 'HDP_BASE__INST3_SEG3',
'HDP_BASE__INST3_SEG4', 'HDP_BASE__INST4_SEG0',
'HDP_BASE__INST4_SEG1', 'HDP_BASE__INST4_SEG2',
'HDP_BASE__INST4_SEG3', 'HDP_BASE__INST4_SEG4',
'HDP_BASE__INST5_SEG0', 'HDP_BASE__INST5_SEG1',
'HDP_BASE__INST5_SEG2', 'HDP_BASE__INST5_SEG3',
'HDP_BASE__INST5_SEG4', 'HDP_BASE__INST6_SEG0',
'HDP_BASE__INST6_SEG1', 'HDP_BASE__INST6_SEG2',
'HDP_BASE__INST6_SEG3', 'HDP_BASE__INST6_SEG4',
'HDP_ENDIAN_8IN16', 'HDP_ENDIAN_8IN32', 'HDP_ENDIAN_8IN64',
'HDP_ENDIAN_NONE', 'HEADER_AGENT_DISPATCH', 'HEADER_BARRIER',
'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0',
'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON',
'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY',
'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0',
'HPD_INT_CONTROL_RX_INT_ACK_1', 'HPO_SRC0', 'HPO_SRC_RESERVED',
'HPO_TOP_CLOCK_GATING_DIS', 'HPO_TOP_CLOCK_GATING_DISABLE',
'HPO_TOP_CLOCK_GATING_EN',
'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0',
'HPO_TOP_FEATURE_GATED_HDMICHARCLK0',
'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0',
'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0',
'HPO_TOP_PERMANENT_DISPCLK', 'HPO_TOP_PERMANENT_HDMICHARCLK0',
'HPO_TOP_PERMANENT_HDMISTREAMCLK0', 'HPO_TOP_PERMANENT_SOCCLK',
'HPO_TOP_REGISTER_GATED_DISPCLK',
'HPO_TOP_REGISTER_GATED_HDMICHARCLK0',
'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', 'HPO_TOP_TEST_CLK_SEL',
'HPO_TOP_TEST_CLOCK_RESERVED',
'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', 'HS_GS', 'HS_STAGE_OFF',
'HS_STAGE_ON', 'HUBP_BLANK_EN', 'HUBP_BLANK_SW_ASSERT',
'HUBP_BLANK_SW_DEASSERT', 'HUBP_IN_ACTIVE', 'HUBP_IN_BLANK',
'HUBP_IN_VBLANK', 'HUBP_MEASURE_WIN_MODE_DCFCLK',
'HUBP_MEASURE_WIN_MODE_DCFCLK_0',
'HUBP_MEASURE_WIN_MODE_DCFCLK_1',
'HUBP_MEASURE_WIN_MODE_DCFCLK_2',
'HUBP_MEASURE_WIN_MODE_DCFCLK_3', 'HUBP_NO_OUTSTANDING_REQ',
'HUBP_SOFT_RESET', 'HUBP_SOFT_RESET_OFF', 'HUBP_SOFT_RESET_ON',
'HUBP_TTU_DISABLE', 'HUBP_TTU_DISABLED', 'HUBP_TTU_ENABLED',
'HUBP_VREADY_AT_OR_AFTER_VSYNC', 'HUBP_VTG_SEL',
'HW_MIRRORING_DISABLE', 'HW_MIRRORING_ENABLE', 'H_MIRROR_EN',
'Hdp_SurfaceEndian', 'ID_STREAM_DISABLE_ACKED',
'ID_STREAM_DISABLE_NO_ACK', 'IHC_INTERRUPT_DEST',
'IHC_INTERRUPT_LINE_STATUS', 'IH_CLIENT_TYPE',
'IH_CLIENT_TYPE_RESERVED', 'IH_GFX_VMID_CLIENT',
'IH_INTERFACE_TYPE', 'IH_LEGACY_INTERFACE', 'IH_MM_VMID_CLIENT',
'IH_MULTI_VMID_CLIENT', 'IH_PERF_SEL',
'IH_PERF_SEL_BIF_LINE0_FALLING',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF0',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF1',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF10',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF11',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF12',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF13',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF14',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF15',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF2',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF3',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF4',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF5',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF6',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF7',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF8',
'IH_PERF_SEL_BIF_LINE0_FALLING_VF9',
'IH_PERF_SEL_BIF_LINE0_RISING',
'IH_PERF_SEL_BIF_LINE0_RISING_VF0',
'IH_PERF_SEL_BIF_LINE0_RISING_VF1',
'IH_PERF_SEL_BIF_LINE0_RISING_VF10',
'IH_PERF_SEL_BIF_LINE0_RISING_VF11',
'IH_PERF_SEL_BIF_LINE0_RISING_VF12',
'IH_PERF_SEL_BIF_LINE0_RISING_VF13',
'IH_PERF_SEL_BIF_LINE0_RISING_VF14',
'IH_PERF_SEL_BIF_LINE0_RISING_VF15',
'IH_PERF_SEL_BIF_LINE0_RISING_VF2',
'IH_PERF_SEL_BIF_LINE0_RISING_VF3',
'IH_PERF_SEL_BIF_LINE0_RISING_VF4',
'IH_PERF_SEL_BIF_LINE0_RISING_VF5',
'IH_PERF_SEL_BIF_LINE0_RISING_VF6',
'IH_PERF_SEL_BIF_LINE0_RISING_VF7',
'IH_PERF_SEL_BIF_LINE0_RISING_VF8',
'IH_PERF_SEL_BIF_LINE0_RISING_VF9',
'IH_PERF_SEL_BUFFER_FIFO_FULL', 'IH_PERF_SEL_BUFFER_IDLE',
'IH_PERF_SEL_CLIENT0_INT', 'IH_PERF_SEL_CLIENT10_INT',
'IH_PERF_SEL_CLIENT11_INT', 'IH_PERF_SEL_CLIENT12_INT',
'IH_PERF_SEL_CLIENT13_INT', 'IH_PERF_SEL_CLIENT14_INT',
'IH_PERF_SEL_CLIENT15_INT', 'IH_PERF_SEL_CLIENT16_INT',
'IH_PERF_SEL_CLIENT17_INT', 'IH_PERF_SEL_CLIENT18_INT',
'IH_PERF_SEL_CLIENT19_INT', 'IH_PERF_SEL_CLIENT1_INT',
'IH_PERF_SEL_CLIENT20_INT', 'IH_PERF_SEL_CLIENT21_INT',
'IH_PERF_SEL_CLIENT22_INT', 'IH_PERF_SEL_CLIENT23_INT',
'IH_PERF_SEL_CLIENT24_INT', 'IH_PERF_SEL_CLIENT25_INT',
'IH_PERF_SEL_CLIENT26_INT', 'IH_PERF_SEL_CLIENT27_INT',
'IH_PERF_SEL_CLIENT28_INT', 'IH_PERF_SEL_CLIENT29_INT',
'IH_PERF_SEL_CLIENT2_INT', 'IH_PERF_SEL_CLIENT30_INT',
'IH_PERF_SEL_CLIENT31_INT', 'IH_PERF_SEL_CLIENT3_INT',
'IH_PERF_SEL_CLIENT4_INT', 'IH_PERF_SEL_CLIENT5_INT',
'IH_PERF_SEL_CLIENT6_INT', 'IH_PERF_SEL_CLIENT7_INT',
'IH_PERF_SEL_CLIENT8_INT', 'IH_PERF_SEL_CLIENT9_INT',
'IH_PERF_SEL_CLIENT_CREDIT_ERROR', 'IH_PERF_SEL_COOKIE_REC_ERROR',
'IH_PERF_SEL_CYCLE', 'IH_PERF_SEL_IDLE', 'IH_PERF_SEL_INPUT_IDLE',
'IH_PERF_SEL_MC_WR_CLEAN_PENDING',
'IH_PERF_SEL_MC_WR_CLEAN_STALL', 'IH_PERF_SEL_MC_WR_COUNT',
'IH_PERF_SEL_MC_WR_IDLE', 'IH_PERF_SEL_MC_WR_STALL',
'IH_PERF_SEL_RB0_FULL', 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8',
'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB0_FULL_VF0',
'IH_PERF_SEL_RB0_FULL_VF1', 'IH_PERF_SEL_RB0_FULL_VF10',
'IH_PERF_SEL_RB0_FULL_VF11', 'IH_PERF_SEL_RB0_FULL_VF12',
'IH_PERF_SEL_RB0_FULL_VF13', 'IH_PERF_SEL_RB0_FULL_VF14',
'IH_PERF_SEL_RB0_FULL_VF15', 'IH_PERF_SEL_RB0_FULL_VF2',
'IH_PERF_SEL_RB0_FULL_VF3', 'IH_PERF_SEL_RB0_FULL_VF4',
'IH_PERF_SEL_RB0_FULL_VF5', 'IH_PERF_SEL_RB0_FULL_VF6',
'IH_PERF_SEL_RB0_FULL_VF7', 'IH_PERF_SEL_RB0_FULL_VF8',
'IH_PERF_SEL_RB0_FULL_VF9', 'IH_PERF_SEL_RB0_LOAD_RPTR',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF10',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF11',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF12',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF13',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF14',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8',
'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB0_OVERFLOW',
'IH_PERF_SEL_RB0_OVERFLOW_VF0', 'IH_PERF_SEL_RB0_OVERFLOW_VF1',
'IH_PERF_SEL_RB0_OVERFLOW_VF10', 'IH_PERF_SEL_RB0_OVERFLOW_VF11',
'IH_PERF_SEL_RB0_OVERFLOW_VF12', 'IH_PERF_SEL_RB0_OVERFLOW_VF13',
'IH_PERF_SEL_RB0_OVERFLOW_VF14', 'IH_PERF_SEL_RB0_OVERFLOW_VF15',
'IH_PERF_SEL_RB0_OVERFLOW_VF2', 'IH_PERF_SEL_RB0_OVERFLOW_VF3',
'IH_PERF_SEL_RB0_OVERFLOW_VF4', 'IH_PERF_SEL_RB0_OVERFLOW_VF5',
'IH_PERF_SEL_RB0_OVERFLOW_VF6', 'IH_PERF_SEL_RB0_OVERFLOW_VF7',
'IH_PERF_SEL_RB0_OVERFLOW_VF8', 'IH_PERF_SEL_RB0_OVERFLOW_VF9',
'IH_PERF_SEL_RB0_RPTR_WRAP', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF11',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF12',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF13',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF14',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8',
'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRAP',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF10',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF11',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF12',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF13',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF14',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8',
'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8',
'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 'IH_PERF_SEL_RB1_FULL',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8',
'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB1_FULL_VF0',
'IH_PERF_SEL_RB1_FULL_VF1', 'IH_PERF_SEL_RB1_FULL_VF10',
'IH_PERF_SEL_RB1_FULL_VF11', 'IH_PERF_SEL_RB1_FULL_VF12',
'IH_PERF_SEL_RB1_FULL_VF13', 'IH_PERF_SEL_RB1_FULL_VF14',
'IH_PERF_SEL_RB1_FULL_VF15', 'IH_PERF_SEL_RB1_FULL_VF2',
'IH_PERF_SEL_RB1_FULL_VF3', 'IH_PERF_SEL_RB1_FULL_VF4',
'IH_PERF_SEL_RB1_FULL_VF5', 'IH_PERF_SEL_RB1_FULL_VF6',
'IH_PERF_SEL_RB1_FULL_VF7', 'IH_PERF_SEL_RB1_FULL_VF8',
'IH_PERF_SEL_RB1_FULL_VF9', 'IH_PERF_SEL_RB1_LOAD_RPTR',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF10',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF11',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF12',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF13',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF14',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8',
'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB1_OVERFLOW',
'IH_PERF_SEL_RB1_OVERFLOW_VF0', 'IH_PERF_SEL_RB1_OVERFLOW_VF1',
'IH_PERF_SEL_RB1_OVERFLOW_VF10', 'IH_PERF_SEL_RB1_OVERFLOW_VF11',
'IH_PERF_SEL_RB1_OVERFLOW_VF12', 'IH_PERF_SEL_RB1_OVERFLOW_VF13',
'IH_PERF_SEL_RB1_OVERFLOW_VF14', 'IH_PERF_SEL_RB1_OVERFLOW_VF15',
'IH_PERF_SEL_RB1_OVERFLOW_VF2', 'IH_PERF_SEL_RB1_OVERFLOW_VF3',
'IH_PERF_SEL_RB1_OVERFLOW_VF4', 'IH_PERF_SEL_RB1_OVERFLOW_VF5',
'IH_PERF_SEL_RB1_OVERFLOW_VF6', 'IH_PERF_SEL_RB1_OVERFLOW_VF7',
'IH_PERF_SEL_RB1_OVERFLOW_VF8', 'IH_PERF_SEL_RB1_OVERFLOW_VF9',
'IH_PERF_SEL_RB1_RPTR_WRAP', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF11',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF12',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF13',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF14',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8',
'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB1_WPTR_WRAP',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF10',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF11',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF12',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF13',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF14',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8',
'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_FULL',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8',
'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB2_FULL_VF0',
'IH_PERF_SEL_RB2_FULL_VF1', 'IH_PERF_SEL_RB2_FULL_VF10',
'IH_PERF_SEL_RB2_FULL_VF11', 'IH_PERF_SEL_RB2_FULL_VF12',
'IH_PERF_SEL_RB2_FULL_VF13', 'IH_PERF_SEL_RB2_FULL_VF14',
'IH_PERF_SEL_RB2_FULL_VF15', 'IH_PERF_SEL_RB2_FULL_VF2',
'IH_PERF_SEL_RB2_FULL_VF3', 'IH_PERF_SEL_RB2_FULL_VF4',
'IH_PERF_SEL_RB2_FULL_VF5', 'IH_PERF_SEL_RB2_FULL_VF6',
'IH_PERF_SEL_RB2_FULL_VF7', 'IH_PERF_SEL_RB2_FULL_VF8',
'IH_PERF_SEL_RB2_FULL_VF9', 'IH_PERF_SEL_RB2_LOAD_RPTR',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF10',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF11',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF12',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF13',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF14',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8',
'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB2_OVERFLOW',
'IH_PERF_SEL_RB2_OVERFLOW_VF0', 'IH_PERF_SEL_RB2_OVERFLOW_VF1',
'IH_PERF_SEL_RB2_OVERFLOW_VF10', 'IH_PERF_SEL_RB2_OVERFLOW_VF11',
'IH_PERF_SEL_RB2_OVERFLOW_VF12', 'IH_PERF_SEL_RB2_OVERFLOW_VF13',
'IH_PERF_SEL_RB2_OVERFLOW_VF14', 'IH_PERF_SEL_RB2_OVERFLOW_VF15',
'IH_PERF_SEL_RB2_OVERFLOW_VF2', 'IH_PERF_SEL_RB2_OVERFLOW_VF3',
'IH_PERF_SEL_RB2_OVERFLOW_VF4', 'IH_PERF_SEL_RB2_OVERFLOW_VF5',
'IH_PERF_SEL_RB2_OVERFLOW_VF6', 'IH_PERF_SEL_RB2_OVERFLOW_VF7',
'IH_PERF_SEL_RB2_OVERFLOW_VF8', 'IH_PERF_SEL_RB2_OVERFLOW_VF9',
'IH_PERF_SEL_RB2_RPTR_WRAP', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF11',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF12',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF13',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF14',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8',
'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_WPTR_WRAP',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF10',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF11',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF12',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF13',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF14',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8',
'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 'IH_PERF_SEL_SELF_IV_VALID',
'IH_PERF_SEL_STORM_CLIENT_INT_DROP',
'IH_REGISTER_WRITE_INTERFACE', 'IH_RING_ID',
'IH_RING_ID_INTERRUPT', 'IH_RING_ID_REQUEST',
'IH_RING_ID_RESERVED', 'IH_RING_ID_TRANSLATION',
'IH_VF_RB_SELECT', 'IH_VF_RB_SELECT_CLIENT_FCN_ID',
'IH_VF_RB_SELECT_IH_FCN_ID', 'IH_VF_RB_SELECT_PF',
'IH_VF_RB_SELECT_RESERVED',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID',
'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID',
'INDIRECT_BUFFER_VALID', 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE',
'INPUT_FIFO_ERROR_TYPE', 'INPUT_INNER_COVERAGE',
'INST_ID_ECC_INTERRUPT_MSG', 'INST_ID_HOST_REG_TRAP_MSG',
'INST_ID_HW_TRAP', 'INST_ID_HW_TRAP_GET_TBA', 'INST_ID_KILL_SEQ',
'INST_ID_PRIV_START', 'INST_ID_SPI_WREXEC',
'INST_ID_TTRACE_NEW_PC_MSG', 'INTERRUPT_LINE_ASSERTED',
'INTERRUPT_LINE_NOT_ASSERTED', 'INTERRUPT_SENT_TO_DMCUB',
'INTERRUPT_SENT_TO_IH', 'INT_DISABLED', 'INT_ENABLED',
'INT_LEVEL', 'INT_MASK', 'INT_PULSE', 'INVALID_REG_ACCESS_TYPE',
'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD',
'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP',
'IQ_SCH_WAVE_MSG', 'IQ_SEM_REARM', 'JITTER_REMOVE_DISABLE',
'LATE_Z', 'LB_ALPHA_DISABLE', 'LB_ALPHA_EN', 'LB_ALPHA_ENABLE',
'LB_INTERLEAVE_DISABLE', 'LB_INTERLEAVE_EN',
'LB_INTERLEAVE_ENABLE', 'LB_MEMORY_CONFIG', 'LB_MEMORY_CONFIG_0',
'LB_MEMORY_CONFIG_1', 'LB_MEMORY_CONFIG_2', 'LB_MEMORY_CONFIG_3',
'LEGACY_PIPE_INTERLEAVE', 'LEGACY_PIPE_INTERLEAVE_256B',
'LEGACY_PIPE_INTERLEAVE_512B', 'LINESTRIP', 'LOOSE_PACK',
'LSDMA_PERF_SEL', 'LSDMA_PERF_SEL_ATCL2_FREE',
'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH',
'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH',
'LSDMA_PERF_SEL_ATCL2_RET_ACK', 'LSDMA_PERF_SEL_ATCL2_RET_XNACK',
'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ',
'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET',
'LSDMA_PERF_SEL_CE_AFIFO_FULL', 'LSDMA_PERF_SEL_CE_BUSY',
'LSDMA_PERF_SEL_CE_BUSY_END', 'LSDMA_PERF_SEL_CE_BUSY_START',
'LSDMA_PERF_SEL_CE_DST_IDLE', 'LSDMA_PERF_SEL_CE_INFO1_FULL',
'LSDMA_PERF_SEL_CE_INFO_FULL', 'LSDMA_PERF_SEL_CE_IN_IDLE',
'LSDMA_PERF_SEL_CE_L1_STALL', 'LSDMA_PERF_SEL_CE_L1_WR_VLD',
'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND',
'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND',
'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ',
'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET',
'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ',
'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET',
'LSDMA_PERF_SEL_CE_OUT_IDLE', 'LSDMA_PERF_SEL_CE_RD_STALL',
'LSDMA_PERF_SEL_CE_RREQ_IDLE', 'LSDMA_PERF_SEL_CE_SPLIT_IDLE',
'LSDMA_PERF_SEL_CE_WREQ_IDLE', 'LSDMA_PERF_SEL_CE_WR_IDLE',
'LSDMA_PERF_SEL_CE_WR_STALL', 'LSDMA_PERF_SEL_CMD_OP_END',
'LSDMA_PERF_SEL_CMD_OP_MATCH', 'LSDMA_PERF_SEL_CMD_OP_START',
'LSDMA_PERF_SEL_CTX_CHANGE',
'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION',
'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'LSDMA_PERF_SEL_CYCLE',
'LSDMA_PERF_SEL_DMA_L1_RD_SEND', 'LSDMA_PERF_SEL_DMA_L1_WR_SEND',
'LSDMA_PERF_SEL_DMA_MC_RD_SEND', 'LSDMA_PERF_SEL_DMA_MC_WR_SEND',
'LSDMA_PERF_SEL_DOORBELL', 'LSDMA_PERF_SEL_DRAM_ECC',
'LSDMA_PERF_SEL_EX_IDLE',
'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
'LSDMA_PERF_SEL_F32_L1_WR_VLD',
'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER',
'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END',
'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START',
'LSDMA_PERF_SEL_GFX_SELECT', 'LSDMA_PERF_SEL_IB_CMD_FULL',
'LSDMA_PERF_SEL_IB_CMD_IDLE', 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ',
'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_IDLE',
'LSDMA_PERF_SEL_INT_IDLE', 'LSDMA_PERF_SEL_INT_REQ_COUNT',
'LSDMA_PERF_SEL_INT_REQ_STALL',
'LSDMA_PERF_SEL_INT_RESP_ACCEPTED',
'LSDMA_PERF_SEL_INT_RESP_RETRY',
'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD',
'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR',
'LSDMA_PERF_SEL_L1_INV_MIDDLE', 'LSDMA_PERF_SEL_L1_RDL2_IDLE',
'LSDMA_PERF_SEL_L1_RDMC_IDLE', 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE',
'LSDMA_PERF_SEL_L1_RD_INV_EN', 'LSDMA_PERF_SEL_L1_RD_INV_IDLE',
'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR',
'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT',
'LSDMA_PERF_SEL_L1_WRL2_IDLE', 'LSDMA_PERF_SEL_L1_WRMC_IDLE',
'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', 'LSDMA_PERF_SEL_L1_WR_INV_EN',
'LSDMA_PERF_SEL_L1_WR_INV_IDLE',
'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR',
'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT',
'LSDMA_PERF_SEL_MC_RD_COUNT', 'LSDMA_PERF_SEL_MC_RD_IDLE',
'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE',
'LSDMA_PERF_SEL_MC_RD_RET_STALL', 'LSDMA_PERF_SEL_MC_WR_COUNT',
'LSDMA_PERF_SEL_MC_WR_IDLE',
'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID',
'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID',
'LSDMA_PERF_SEL_NACK_GEN_ERR', 'LSDMA_PERF_SEL_NUM_PACKET',
'LSDMA_PERF_SEL_PAGE_SELECT', 'LSDMA_PERF_SEL_RB_CMD_FULL',
'LSDMA_PERF_SEL_RB_CMD_IDLE', 'LSDMA_PERF_SEL_RB_EMPTY',
'LSDMA_PERF_SEL_RB_FULL', 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ',
'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_RB_RPTR_WB',
'LSDMA_PERF_SEL_RB_RPTR_WRAP', 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ',
'LSDMA_PERF_SEL_RB_WPTR_WRAP', 'LSDMA_PERF_SEL_RD_BA_RTR',
'LSDMA_PERF_SEL_REG_IDLE', 'LSDMA_PERF_SEL_RLC0_SELECT',
'LSDMA_PERF_SEL_RLC1_SELECT', 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND',
'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH',
'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 'LSDMA_PERF_SEL_SEM_IDLE',
'LSDMA_PERF_SEL_SEM_REQ_COUNT', 'LSDMA_PERF_SEL_SEM_REQ_STALL',
'LSDMA_PERF_SEL_SEM_RESP_FAIL',
'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE',
'LSDMA_PERF_SEL_SEM_RESP_PASS', 'LSDMA_PERF_SEL_SRBM_REG_SEND',
'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ',
'LSDMA_PERF_SEL_UTCL1_UTCL2_RET',
'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ',
'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', 'LSDMA_PERF_SEL_WR_BA_RTR',
'LS_STAGE_OFF', 'LS_STAGE_ON', 'LUT_2CFG_MEMORY_A',
'LUT_2CFG_MEMORY_B', 'LUT_2CFG_NO_MEMORY', 'LUT_2_MODE_BYPASS',
'LUT_2_MODE_RAMA_LUT', 'LUT_2_MODE_RAMB_LUT', 'LUT_4CFG_MEMORY_A',
'LUT_4CFG_MEMORY_B', 'LUT_4CFG_NO_MEMORY', 'LUT_4CFG_ROM_A',
'LUT_4CFG_ROM_B', 'LUT_4_MODE_BYPASS', 'LUT_4_MODE_RAMA_LUT',
'LUT_4_MODE_RAMB_LUT', 'LUT_4_MODE_ROMA_LUT',
'LUT_4_MODE_ROMB_LUT', 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS',
'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH',
'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT',
'MASTER_UPDATE_LOCK_DB_FIELD_BOTH',
'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM',
'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED',
'MASTER_UPDATE_LOCK_DB_FIELD_TOP',
'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH',
'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT',
'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED',
'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT',
'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK',
'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE',
'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE',
'MASTER_UPDATE_LOCK_SEL', 'MASTER_UPDATE_LOCK_SEL_0',
'MASTER_UPDATE_LOCK_SEL_1', 'MASTER_UPDATE_LOCK_SEL_2',
'MASTER_UPDATE_LOCK_SEL_3', 'MASTER_UPDATE_LOCK_SEL_RESERVED4',
'MASTER_UPDATE_LOCK_SEL_RESERVED5',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED',
'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP',
'MAX_INSTANCE', 'MAX_SEGMENT', 'MEM_ARB_MODE_AGE',
'MEM_ARB_MODE_BOTH', 'MEM_ARB_MODE_FIXED', 'MEM_ARB_MODE_WEIGHT',
'MEM_POWER_DIS_MODE_DISABLE', 'MEM_POWER_DIS_MODE_ENABLE',
'MEM_POWER_FORCE_MODE_DEEP_SLEEP',
'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', 'MEM_POWER_FORCE_MODE_OFF',
'MEM_POWER_FORCE_MODE_SHUT_DOWN', 'MEM_POWER_STATUS_DEEP_SLEEP',
'MEM_POWER_STATUS_LIGHT_SLEEP', 'MEM_POWER_STATUS_ON',
'MEM_POWER_STATUS_SHUT_DOWN', 'MEM_PWR_DIS_CTRL',
'MEM_PWR_DIS_MODE', 'MEM_PWR_FORCE_CTRL', 'MEM_PWR_FORCE_CTRL2',
'MEM_PWR_FORCE_MODE', 'MEM_PWR_SEL_CTRL', 'MEM_PWR_SEL_CTRL2',
'MEM_PWR_STATUS', 'METADATA_HUBP_SEL', 'METADATA_HUBP_SEL_0',
'METADATA_HUBP_SEL_1', 'METADATA_HUBP_SEL_2',
'METADATA_HUBP_SEL_3', 'METADATA_HUBP_SEL_RESERVED',
'METADATA_STREAM_DP', 'METADATA_STREAM_DVE',
'METADATA_STREAM_TYPE_SEL', 'META_CHUNK_SIZE',
'META_CHUNK_SIZE_1KB', 'META_CHUNK_SIZE_2KB',
'META_CHUNK_SIZE_4KB', 'META_CHUNK_SIZE_8KB', 'META_LINEAR',
'META_SURF_LINEAR', 'META_SURF_TILED', 'ME_ID0', 'ME_ID1',
'ME_ID2', 'ME_ID3', 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK',
'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN',
'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL',
'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK',
'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN',
'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MIN_CHUNK_SIZE',
'MIN_CHUNK_SIZE_1024B', 'MIN_CHUNK_SIZE_256B',
'MIN_CHUNK_SIZE_512B', 'MIN_META_CHUNK_SIZE',
'MIN_META_CHUNK_SIZE_128B', 'MIN_META_CHUNK_SIZE_256B',
'MIN_META_CHUNK_SIZE_64B', 'MMHUB_BASE', 'MMHUB_BASE__INST0_SEG0',
'MMHUB_BASE__INST0_SEG1', 'MMHUB_BASE__INST0_SEG2',
'MMHUB_BASE__INST0_SEG3', 'MMHUB_BASE__INST0_SEG4',
'MMHUB_BASE__INST1_SEG0', 'MMHUB_BASE__INST1_SEG1',
'MMHUB_BASE__INST1_SEG2', 'MMHUB_BASE__INST1_SEG3',
'MMHUB_BASE__INST1_SEG4', 'MMHUB_BASE__INST2_SEG0',
'MMHUB_BASE__INST2_SEG1', 'MMHUB_BASE__INST2_SEG2',
'MMHUB_BASE__INST2_SEG3', 'MMHUB_BASE__INST2_SEG4',
'MMHUB_BASE__INST3_SEG0', 'MMHUB_BASE__INST3_SEG1',
'MMHUB_BASE__INST3_SEG2', 'MMHUB_BASE__INST3_SEG3',
'MMHUB_BASE__INST3_SEG4', 'MMHUB_BASE__INST4_SEG0',
'MMHUB_BASE__INST4_SEG1', 'MMHUB_BASE__INST4_SEG2',
'MMHUB_BASE__INST4_SEG3', 'MMHUB_BASE__INST4_SEG4',
'MMHUB_BASE__INST5_SEG0', 'MMHUB_BASE__INST5_SEG1',
'MMHUB_BASE__INST5_SEG2', 'MMHUB_BASE__INST5_SEG3',
'MMHUB_BASE__INST5_SEG4', 'MMHUB_BASE__INST6_SEG0',
'MMHUB_BASE__INST6_SEG1', 'MMHUB_BASE__INST6_SEG2',
'MMHUB_BASE__INST6_SEG3', 'MMHUB_BASE__INST6_SEG4', 'MONO_10LSB',
'MONO_10MSB', 'MONO_12LSB', 'MONO_12MSB', 'MONO_16', 'MONO_2BIT',
'MONO_8', 'MP0_BASE', 'MP0_BASE__INST0_SEG0',
'MP0_BASE__INST0_SEG1', 'MP0_BASE__INST0_SEG2',
'MP0_BASE__INST0_SEG3', 'MP0_BASE__INST0_SEG4',
'MP0_BASE__INST1_SEG0', 'MP0_BASE__INST1_SEG1',
'MP0_BASE__INST1_SEG2', 'MP0_BASE__INST1_SEG3',
'MP0_BASE__INST1_SEG4', 'MP0_BASE__INST2_SEG0',
'MP0_BASE__INST2_SEG1', 'MP0_BASE__INST2_SEG2',
'MP0_BASE__INST2_SEG3', 'MP0_BASE__INST2_SEG4',
'MP0_BASE__INST3_SEG0', 'MP0_BASE__INST3_SEG1',
'MP0_BASE__INST3_SEG2', 'MP0_BASE__INST3_SEG3',
'MP0_BASE__INST3_SEG4', 'MP0_BASE__INST4_SEG0',
'MP0_BASE__INST4_SEG1', 'MP0_BASE__INST4_SEG2',
'MP0_BASE__INST4_SEG3', 'MP0_BASE__INST4_SEG4',
'MP0_BASE__INST5_SEG0', 'MP0_BASE__INST5_SEG1',
'MP0_BASE__INST5_SEG2', 'MP0_BASE__INST5_SEG3',
'MP0_BASE__INST5_SEG4', 'MP0_BASE__INST6_SEG0',
'MP0_BASE__INST6_SEG1', 'MP0_BASE__INST6_SEG2',
'MP0_BASE__INST6_SEG3', 'MP0_BASE__INST6_SEG4', 'MP1_BASE',
'MP1_BASE__INST0_SEG0', 'MP1_BASE__INST0_SEG1',
'MP1_BASE__INST0_SEG2', 'MP1_BASE__INST0_SEG3',
'MP1_BASE__INST0_SEG4', 'MP1_BASE__INST1_SEG0',
'MP1_BASE__INST1_SEG1', 'MP1_BASE__INST1_SEG2',
'MP1_BASE__INST1_SEG3', 'MP1_BASE__INST1_SEG4',
'MP1_BASE__INST2_SEG0', 'MP1_BASE__INST2_SEG1',
'MP1_BASE__INST2_SEG2', 'MP1_BASE__INST2_SEG3',
'MP1_BASE__INST2_SEG4', 'MP1_BASE__INST3_SEG0',
'MP1_BASE__INST3_SEG1', 'MP1_BASE__INST3_SEG2',
'MP1_BASE__INST3_SEG3', 'MP1_BASE__INST3_SEG4',
'MP1_BASE__INST4_SEG0', 'MP1_BASE__INST4_SEG1',
'MP1_BASE__INST4_SEG2', 'MP1_BASE__INST4_SEG3',
'MP1_BASE__INST4_SEG4', 'MP1_BASE__INST5_SEG0',
'MP1_BASE__INST5_SEG1', 'MP1_BASE__INST5_SEG2',
'MP1_BASE__INST5_SEG3', 'MP1_BASE__INST5_SEG4',
'MP1_BASE__INST6_SEG0', 'MP1_BASE__INST6_SEG1',
'MP1_BASE__INST6_SEG2', 'MP1_BASE__INST6_SEG3',
'MP1_BASE__INST6_SEG4', 'MPCC_BG_COLOR_BPC',
'MPCC_BG_COLOR_BPC_10bit', 'MPCC_BG_COLOR_BPC_11bit',
'MPCC_BG_COLOR_BPC_12bit', 'MPCC_BG_COLOR_BPC_8bit',
'MPCC_BG_COLOR_BPC_9bit', 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY',
'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE',
'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN',
'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED',
'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE',
'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE',
'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE',
'MPCC_CONTROL_MPCC_BOT_GAIN_MODE',
'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0',
'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', 'MPCC_CONTROL_MPCC_MODE',
'MPCC_CONTROL_MPCC_MODE_BYPASS',
'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING',
'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY',
'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH',
'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM',
'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13',
'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', 'MPCC_GAMUT_REMAP_MODE_0',
'MPCC_GAMUT_REMAP_MODE_1', 'MPCC_GAMUT_REMAP_MODE_2',
'MPCC_GAMUT_REMAP_MODE_ENUM', 'MPCC_GAMUT_REMAP_MODE_RSV',
'MPCC_MCM_3DLUT_17CUBE', 'MPCC_MCM_3DLUT_30BIT',
'MPCC_MCM_3DLUT_30BIT_ENUM', 'MPCC_MCM_3DLUT_36BIT',
'MPCC_MCM_3DLUT_9CUBE', 'MPCC_MCM_3DLUT_RAM_SEL',
'MPCC_MCM_3DLUT_SIZE_ENUM', 'MPCC_MCM_GAMMA_LUT_BYPASS',
'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL',
'MPCC_MCM_GAMMA_LUT_MODE_ENUM',
'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM', 'MPCC_MCM_GAMMA_LUT_RAMA',
'MPCC_MCM_GAMMA_LUT_RAMB', 'MPCC_MCM_GAMMA_LUT_RAM_LUT',
'MPCC_MCM_GAMMA_LUT_RESERVED_1', 'MPCC_MCM_GAMMA_LUT_RESERVED_3',
'MPCC_MCM_GAMMA_LUT_SEL_ENUM', 'MPCC_MCM_LUT_2_MODE_BYPASS',
'MPCC_MCM_LUT_2_MODE_ENUM', 'MPCC_MCM_LUT_2_MODE_RAMA_LUT',
'MPCC_MCM_LUT_2_MODE_RAMB_LUT', 'MPCC_MCM_LUT_ALL_USE_R',
'MPCC_MCM_LUT_BLUE_LUT', 'MPCC_MCM_LUT_CONFIG_MODE',
'MPCC_MCM_LUT_DIFFERENT_RGB', 'MPCC_MCM_LUT_DISABLE_DEBUG',
'MPCC_MCM_LUT_ENABLE_DEBUG', 'MPCC_MCM_LUT_GREEN_LUT',
'MPCC_MCM_LUT_NUM_SEG', 'MPCC_MCM_LUT_RAMA_ACCESS',
'MPCC_MCM_LUT_RAMB_ACCESS', 'MPCC_MCM_LUT_RAM_SEL',
'MPCC_MCM_LUT_READ_COLOR_SEL', 'MPCC_MCM_LUT_READ_DBG',
'MPCC_MCM_LUT_RED_LUT', 'MPCC_MCM_LUT_SEGMENTS_1',
'MPCC_MCM_LUT_SEGMENTS_128', 'MPCC_MCM_LUT_SEGMENTS_16',
'MPCC_MCM_LUT_SEGMENTS_2', 'MPCC_MCM_LUT_SEGMENTS_32',
'MPCC_MCM_LUT_SEGMENTS_4', 'MPCC_MCM_LUT_SEGMENTS_64',
'MPCC_MCM_LUT_SEGMENTS_8', 'MPCC_MCM_MEM_PWR_FORCE_DIS',
'MPCC_MCM_MEM_PWR_FORCE_DS', 'MPCC_MCM_MEM_PWR_FORCE_ENUM',
'MPCC_MCM_MEM_PWR_FORCE_LS', 'MPCC_MCM_MEM_PWR_FORCE_SD',
'MPCC_MCM_MEM_PWR_STATE_DS', 'MPCC_MCM_MEM_PWR_STATE_ENUM',
'MPCC_MCM_MEM_PWR_STATE_LS', 'MPCC_MCM_MEM_PWR_STATE_ON',
'MPCC_MCM_MEM_PWR_STATE_SD', 'MPCC_MCM_RAM0_ACCESS',
'MPCC_MCM_RAM1_ACCESS', 'MPCC_MCM_RAM2_ACCESS',
'MPCC_MCM_RAM3_ACCESS', 'MPCC_OGAM_ALL_USE_R',
'MPCC_OGAM_BLUE_LUT', 'MPCC_OGAM_DIFFERENT_RGB',
'MPCC_OGAM_DISABLE_DEBUG', 'MPCC_OGAM_DISABLE_PWL',
'MPCC_OGAM_ENABLE_DEBUG', 'MPCC_OGAM_ENABLE_PWL',
'MPCC_OGAM_GREEN_LUT', 'MPCC_OGAM_LUT_2CFG_MEMORY_A',
'MPCC_OGAM_LUT_2CFG_MEMORY_B', 'MPCC_OGAM_LUT_2CFG_NO_MEMORY',
'MPCC_OGAM_LUT_2_CONFIG_ENUM', 'MPCC_OGAM_LUT_CONFIG_MODE',
'MPCC_OGAM_LUT_PWL_DISABLE_ENUM',
'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL',
'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA',
'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB',
'MPCC_OGAM_LUT_RAM_SEL', 'MPCC_OGAM_LUT_READ_COLOR_SEL',
'MPCC_OGAM_LUT_READ_DBG', 'MPCC_OGAM_LUT_SEL_ENUM',
'MPCC_OGAM_MODE_0', 'MPCC_OGAM_MODE_2',
'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM', 'MPCC_OGAM_MODE_RSV',
'MPCC_OGAM_MODE_RSV1', 'MPCC_OGAM_NUM_SEG', 'MPCC_OGAM_RAMA',
'MPCC_OGAM_RAMA_ACCESS', 'MPCC_OGAM_RAMB',
'MPCC_OGAM_RAMB_ACCESS', 'MPCC_OGAM_RED_LUT',
'MPCC_OGAM_SEGMENTS_1', 'MPCC_OGAM_SEGMENTS_128',
'MPCC_OGAM_SEGMENTS_16', 'MPCC_OGAM_SEGMENTS_2',
'MPCC_OGAM_SEGMENTS_32', 'MPCC_OGAM_SEGMENTS_4',
'MPCC_OGAM_SEGMENTS_64', 'MPCC_OGAM_SEGMENTS_8',
'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN',
'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE',
'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE',
'MPCC_SM_CONTROL_MPCC_SM_EN', 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE',
'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE',
'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT',
'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE',
'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE',
'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED',
'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT',
'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE',
'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE',
'MPCC_SM_CONTROL_MPCC_SM_MODE',
'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING',
'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING',
'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING',
'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE',
'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN',
'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE',
'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE',
'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET',
'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE',
'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET',
'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE',
'MPC_CFG_ADR_VUPDATE_LOCK_SET',
'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE',
'MPC_CFG_CFG_VUPDATE_LOCK_SET',
'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE',
'MPC_CFG_CUR_VUPDATE_LOCK_SET',
'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE',
'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', 'MPC_CFG_MPC_TEST_CLK_SEL',
'MPC_CFG_MPC_TEST_CLK_SEL_0', 'MPC_CFG_MPC_TEST_CLK_SEL_1',
'MPC_CFG_MPC_TEST_CLK_SEL_2', 'MPC_CFG_MPC_TEST_CLK_SEL_3',
'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN',
'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE',
'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE',
'MPC_CRC_CALC_INTERLACE_MODE', 'MPC_CRC_CALC_MODE',
'MPC_CRC_CALC_STEREO_MODE', 'MPC_CRC_CONTINUOUS_MODE',
'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM',
'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH',
'MPC_CRC_INTERLACE_MODE_BOTTOM', 'MPC_CRC_INTERLACE_MODE_TOP',
'MPC_CRC_ONE_SHOT_MODE', 'MPC_CRC_SOURCE_SELECT',
'MPC_CRC_SOURCE_SEL_DPP', 'MPC_CRC_SOURCE_SEL_DWB',
'MPC_CRC_SOURCE_SEL_OPP', 'MPC_CRC_SOURCE_SEL_OTHER',
'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH',
'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT',
'MPC_CRC_STEREO_MODE_LEFT', 'MPC_CRC_STEREO_MODE_RIGHT',
'MPC_DEBUG_BUS1_DATA_SELECT',
'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG',
'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT',
'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV',
'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1',
'MPC_DEBUG_BUS2_DATA_SELECT', 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC',
'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT',
'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM',
'MPC_DEBUG_BUS2_DATA_SELECT_RES',
'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT',
'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID',
'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID',
'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID',
'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID',
'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID',
'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1',
'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA',
'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA',
'MPC_DEBUG_BUS_MPCC_BYTE0', 'MPC_DEBUG_BUS_MPCC_BYTE1',
'MPC_DEBUG_BUS_MPCC_BYTE2', 'MPC_DEBUG_BUS_MPCC_BYTE3',
'MPC_DEBUG_BUS_MPCC_BYTE_SELECT', 'MPC_OCSC_COEF_FORMAT',
'MPC_OCSC_COEF_FORMAT_S2_13', 'MPC_OCSC_COEF_FORMAT_S3_12',
'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN',
'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE',
'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE',
'MPC_OUT_CSC_MODE', 'MPC_OUT_CSC_MODE_0', 'MPC_OUT_CSC_MODE_1',
'MPC_OUT_CSC_MODE_2', 'MPC_OUT_CSC_MODE_RSV',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE',
'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH',
'MPC_OUT_RATE_CONTROL_DISABLE_SET',
'MPC_OUT_RATE_CONTROL_SET_DISABLE',
'MPC_OUT_RATE_CONTROL_SET_ENABLE',
'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED',
'MTYPE', 'MTYPE_CC', 'MTYPE_C_RO_S', 'MTYPE_C_RO_US',
'MTYPE_C_RW_S', 'MTYPE_C_RW_US', 'MTYPE_NC', 'MTYPE_RESERVED_1',
'MTYPE_RESERVED_5', 'MTYPE_RESERVED_7', 'MTYPE_UC', 'MTYPE_WC',
'MULTIPLE_BY1', 'MULTIPLE_BY2', 'MULTIPLE_BY3_RESERVED',
'MULTIPLE_BY4', 'MULTIPLE_RESERVED', 'MULT_16', 'MULT_8',
'MemArbMode', 'NBIO_BASE', 'NBIO_BASE__INST0_SEG0',
'NBIO_BASE__INST0_SEG1', 'NBIO_BASE__INST0_SEG2',
'NBIO_BASE__INST0_SEG3', 'NBIO_BASE__INST0_SEG4',
'NBIO_BASE__INST1_SEG0', 'NBIO_BASE__INST1_SEG1',
'NBIO_BASE__INST1_SEG2', 'NBIO_BASE__INST1_SEG3',
'NBIO_BASE__INST1_SEG4', 'NBIO_BASE__INST2_SEG0',
'NBIO_BASE__INST2_SEG1', 'NBIO_BASE__INST2_SEG2',
'NBIO_BASE__INST2_SEG3', 'NBIO_BASE__INST2_SEG4',
'NBIO_BASE__INST3_SEG0', 'NBIO_BASE__INST3_SEG1',
'NBIO_BASE__INST3_SEG2', 'NBIO_BASE__INST3_SEG3',
'NBIO_BASE__INST3_SEG4', 'NBIO_BASE__INST4_SEG0',
'NBIO_BASE__INST4_SEG1', 'NBIO_BASE__INST4_SEG2',
'NBIO_BASE__INST4_SEG3', 'NBIO_BASE__INST4_SEG4',
'NBIO_BASE__INST5_SEG0', 'NBIO_BASE__INST5_SEG1',
'NBIO_BASE__INST5_SEG2', 'NBIO_BASE__INST5_SEG3',
'NBIO_BASE__INST5_SEG4', 'NBIO_BASE__INST6_SEG0',
'NBIO_BASE__INST6_SEG1', 'NBIO_BASE__INST6_SEG2',
'NBIO_BASE__INST6_SEG3', 'NBIO_BASE__INST6_SEG4', 'NON_BYPASS',
'NOT_FORCE_THE_CLOCK_DISABLED', 'NOT_SENT', 'NO_DIST', 'NO_DIV',
'NO_FORCE', 'NO_FORCE_REQ', 'NO_FORCE_REQUEST',
'NO_MIN_CHUNK_SIZE', 'NO_MIN_META_CHUNK_SIZE',
'NO_OUTSTANDING_REQ', 'NUM_SIMD_PER_CU', 'NVD_H',
'OBUF_BYPASS_DIS', 'OBUF_BYPASS_EN', 'OBUF_BYPASS_SEL',
'OBUF_FULL', 'OBUF_FULL_RECOUT', 'OBUF_HALF_RECOUT',
'OBUF_IS_HALF_RECOUT_WIDTH_SEL', 'OBUF_RECOUT',
'OBUF_USE_FULL_BUFFER_SEL', 'OFFCHIP_HS_DEALLOC', 'OFF_SEQ',
'OKAY', 'OKAY_NODATA', 'OMODE_BLEND', 'OMODE_O_THEN_B',
'OMODE_P_THEN_O_THEN_B', 'OMODE_RESERVED_3', 'ON_SEQ',
'OPPBUF_DISPLAY_SEGMENTATION',
'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT',
'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT',
'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT',
'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT',
'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT',
'OPP_ABM_DEBUG_BUS_SELECT_CONTROL',
'OPP_DPG_DEBUG_BUS_SELECT_CONTROL',
'OPP_FMT_DEBUG_BUS_SELECT_CONTROL',
'OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL',
'OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL', 'OPP_PIPE_CLOCK_DISABLE',
'OPP_PIPE_CLOCK_ENABLE', 'OPP_PIPE_CLOCK_ENABLE_CONTROL',
'OPP_PIPE_CRC_CONT_EN', 'OPP_PIPE_CRC_DISABLE', 'OPP_PIPE_CRC_EN',
'OPP_PIPE_CRC_ENABLE', 'OPP_PIPE_CRC_INTERLACE_EN',
'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED',
'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE',
'OPP_PIPE_CRC_INTERLACE_MODE',
'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD',
'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD',
'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM',
'OPP_PIPE_CRC_INTERLACE_MODE_TOP', 'OPP_PIPE_CRC_MODE_CONTINUOUS',
'OPP_PIPE_CRC_MODE_ONE_SHOT', 'OPP_PIPE_CRC_ONE_SHOT_PENDING',
'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING',
'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING',
'OPP_PIPE_CRC_PIXEL_SELECT',
'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS',
'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS',
'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS',
'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED',
'OPP_PIPE_CRC_SOURCE_SELECT', 'OPP_PIPE_CRC_SOURCE_SELECT_FMT',
'OPP_PIPE_CRC_SOURCE_SELECT_SFT', 'OPP_PIPE_CRC_STEREO_EN',
'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO',
'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO',
'OPP_PIPE_CRC_STEREO_MODE',
'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE',
'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE',
'OPP_PIPE_CRC_STEREO_MODE_LEFT', 'OPP_PIPE_CRC_STEREO_MODE_RIGHT',
'OPP_PIPE_DIGTIAL_BYPASS_CONTROL',
'OPP_PIPE_DIGTIAL_BYPASS_DISABLE',
'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', 'OPP_TEST_CLK_SEL_CONTROL',
'OPP_TEST_CLK_SEL_DISPCLK_ABM0', 'OPP_TEST_CLK_SEL_DISPCLK_ABM1',
'OPP_TEST_CLK_SEL_DISPCLK_ABM2', 'OPP_TEST_CLK_SEL_DISPCLK_ABM3',
'OPP_TEST_CLK_SEL_DISPCLK_OPP0', 'OPP_TEST_CLK_SEL_DISPCLK_OPP1',
'OPP_TEST_CLK_SEL_DISPCLK_OPP2', 'OPP_TEST_CLK_SEL_DISPCLK_OPP3',
'OPP_TEST_CLK_SEL_DISPCLK_P', 'OPP_TEST_CLK_SEL_DISPCLK_R',
'OPP_TEST_CLK_SEL_RESERVED0', 'OPP_TEST_CLK_SEL_RESERVED1',
'OPP_TEST_CLK_SEL_RESERVED2', 'OPP_TEST_CLK_SEL_RESERVED3',
'OPP_TOP_CLOCK_DISABLED_STATUS', 'OPP_TOP_CLOCK_ENABLED_STATUS',
'OPP_TOP_CLOCK_ENABLE_STATUS', 'OPP_TOP_CLOCK_GATING_CONTROL',
'OPP_TOP_CLOCK_GATING_DISABLED', 'OPP_TOP_CLOCK_GATING_ENABLED',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4',
'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5',
'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', 'OPT_COMB_MAX',
'OPT_COMB_MIN', 'OPT_COMB_NONE', 'OPT_COMB_REVSUBTRACT',
'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', 'OSSSYS_BASE',
'OSSSYS_BASE__INST0_SEG0', 'OSSSYS_BASE__INST0_SEG1',
'OSSSYS_BASE__INST0_SEG2', 'OSSSYS_BASE__INST0_SEG3',
'OSSSYS_BASE__INST0_SEG4', 'OSSSYS_BASE__INST1_SEG0',
'OSSSYS_BASE__INST1_SEG1', 'OSSSYS_BASE__INST1_SEG2',
'OSSSYS_BASE__INST1_SEG3', 'OSSSYS_BASE__INST1_SEG4',
'OSSSYS_BASE__INST2_SEG0', 'OSSSYS_BASE__INST2_SEG1',
'OSSSYS_BASE__INST2_SEG2', 'OSSSYS_BASE__INST2_SEG3',
'OSSSYS_BASE__INST2_SEG4', 'OSSSYS_BASE__INST3_SEG0',
'OSSSYS_BASE__INST3_SEG1', 'OSSSYS_BASE__INST3_SEG2',
'OSSSYS_BASE__INST3_SEG3', 'OSSSYS_BASE__INST3_SEG4',
'OSSSYS_BASE__INST4_SEG0', 'OSSSYS_BASE__INST4_SEG1',
'OSSSYS_BASE__INST4_SEG2', 'OSSSYS_BASE__INST4_SEG3',
'OSSSYS_BASE__INST4_SEG4', 'OSSSYS_BASE__INST5_SEG0',
'OSSSYS_BASE__INST5_SEG1', 'OSSSYS_BASE__INST5_SEG2',
'OSSSYS_BASE__INST5_SEG3', 'OSSSYS_BASE__INST5_SEG4',
'OSSSYS_BASE__INST6_SEG0', 'OSSSYS_BASE__INST6_SEG1',
'OSSSYS_BASE__INST6_SEG2', 'OSSSYS_BASE__INST6_SEG3',
'OSSSYS_BASE__INST6_SEG4',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE',
'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED',
'OTG_ADD_PIXEL', 'OTG_ADD_PIXEL_FORCE', 'OTG_ADD_PIXEL_NOOP',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST',
'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE',
'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL',
'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP',
'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL',
'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY',
'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE',
'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE',
'OTG_CONTROL_OTG_MASTER_EN', 'OTG_CONTROL_OTG_MASTER_EN_FALSE',
'OTG_CONTROL_OTG_MASTER_EN_TRUE', 'OTG_CONTROL_OTG_OUT_MUX',
'OTG_CONTROL_OTG_OUT_MUX_0', 'OTG_CONTROL_OTG_OUT_MUX_1',
'OTG_CONTROL_OTG_OUT_MUX_2', 'OTG_CONTROL_OTG_START_POINT_CNTL',
'OTG_CONTROL_OTG_START_POINT_CNTL_DP',
'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL',
'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN',
'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE',
'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE',
'OTG_CRC_CNTL_OTG_CRC1_EN', 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE',
'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', 'OTG_CRC_CNTL_OTG_CRC_CONT_EN',
'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE',
'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE',
'OTG_CRC_CNTL_OTG_CRC_CONT_MODE',
'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET',
'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', 'OTG_CRC_CNTL_OTG_CRC_EN',
'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM',
'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT',
'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT',
'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS',
'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE',
'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB',
'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB',
'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B',
'OTG_DIG_UPDATE_VCOUNT_0', 'OTG_DIG_UPDATE_VCOUNT_1',
'OTG_DIG_UPDATE_VCOUNT_MODE',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE',
'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE',
'OTG_DROP_PIXEL', 'OTG_DROP_PIXEL_FORCE', 'OTG_DROP_PIXEL_NOOP',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME',
'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME',
'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN',
'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE',
'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA',
'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE',
'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4',
'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5',
'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL',
'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL',
'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD',
'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL',
'OTG_GLOBAL_UPDATE_LOCK_DISABLE', 'OTG_GLOBAL_UPDATE_LOCK_EN',
'OTG_GLOBAL_UPDATE_LOCK_ENABLE', 'OTG_GSL_MASTER_MODE',
'OTG_GSL_MASTER_MODE_0', 'OTG_GSL_MASTER_MODE_1',
'OTG_GSL_MASTER_MODE_2', 'OTG_GSL_MASTER_MODE_3',
'OTG_HORZ_REPETITION_COUNT', 'OTG_HORZ_REPETITION_COUNT_0',
'OTG_HORZ_REPETITION_COUNT_1', 'OTG_HORZ_REPETITION_COUNT_10',
'OTG_HORZ_REPETITION_COUNT_11', 'OTG_HORZ_REPETITION_COUNT_12',
'OTG_HORZ_REPETITION_COUNT_13', 'OTG_HORZ_REPETITION_COUNT_14',
'OTG_HORZ_REPETITION_COUNT_15', 'OTG_HORZ_REPETITION_COUNT_2',
'OTG_HORZ_REPETITION_COUNT_3', 'OTG_HORZ_REPETITION_COUNT_4',
'OTG_HORZ_REPETITION_COUNT_5', 'OTG_HORZ_REPETITION_COUNT_6',
'OTG_HORZ_REPETITION_COUNT_7', 'OTG_HORZ_REPETITION_COUNT_8',
'OTG_HORZ_REPETITION_COUNT_9', 'OTG_H_SYNC_A_POL',
'OTG_H_SYNC_A_POL_HIGH', 'OTG_H_SYNC_A_POL_LOW',
'OTG_H_TIMING_DIV_MODE', 'OTG_H_TIMING_DIV_MODE_AUTO',
'OTG_H_TIMING_DIV_MODE_DIV_BY2', 'OTG_H_TIMING_DIV_MODE_DIV_BY4',
'OTG_H_TIMING_DIV_MODE_MANUAL', 'OTG_H_TIMING_DIV_MODE_NOAUTO',
'OTG_H_TIMING_DIV_MODE_NO_DIV', 'OTG_H_TIMING_DIV_MODE_RESERVED',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2',
'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE',
'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE',
'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE',
'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE',
'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE',
'OTG_MASTER_UPDATE_LOCK_DB_EN', 'OTG_MASTER_UPDATE_LOCK_DISABLE',
'OTG_MASTER_UPDATE_LOCK_ENABLE', 'OTG_MASTER_UPDATE_LOCK_GSL_EN',
'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE',
'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE',
'OTG_MASTER_UPDATE_LOCK_VCOUNT_0',
'OTG_MASTER_UPDATE_LOCK_VCOUNT_1',
'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA',
'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB',
'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR',
'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE',
'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE',
'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF',
'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON',
'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL',
'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE',
'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE',
'OTG_STEREO_CONTROL_OTG_STEREO_EN',
'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE',
'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE',
'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY',
'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE',
'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE',
'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY',
'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE',
'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED',
'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT',
'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR',
'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE',
'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0',
'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1',
'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN',
'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE',
'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING',
'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2',
'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3',
'OTG_TRIGA_FREQUENCY_SELECT', 'OTG_TRIGA_FREQUENCY_SELECT_0',
'OTG_TRIGA_FREQUENCY_SELECT_1', 'OTG_TRIGA_FREQUENCY_SELECT_2',
'OTG_TRIGA_FREQUENCY_SELECT_3',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2',
'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3',
'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR',
'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE',
'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0',
'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1',
'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN',
'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE',
'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING',
'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2',
'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3',
'OTG_TRIGB_FREQUENCY_SELECT', 'OTG_TRIGB_FREQUENCY_SELECT_0',
'OTG_TRIGB_FREQUENCY_SELECT_1', 'OTG_TRIGB_FREQUENCY_SELECT_2',
'OTG_TRIGB_FREQUENCY_SELECT_3',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2',
'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3',
'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK',
'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE',
'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE',
'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE',
'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE',
'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA',
'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB',
'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR',
'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE',
'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE',
'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR',
'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE',
'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE',
'OTG_VUPDATE_BLOCK_DISABLE', 'OTG_VUPDATE_BLOCK_DISABLE_OFF',
'OTG_VUPDATE_BLOCK_DISABLE_ON', 'OTG_V_SYNC_A_POL',
'OTG_V_SYNC_A_POL_HIGH', 'OTG_V_SYNC_A_POL_LOW',
'OTG_V_SYNC_MODE', 'OTG_V_SYNC_MODE_HBLANK',
'OTG_V_SYNC_MODE_HSYNC',
'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD',
'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0',
'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE',
'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE',
'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE',
'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK',
'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE',
'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE',
'OUTPUT_LINE', 'OUTPUT_POINT',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY',
'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ',
'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ',
'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', 'OUTSTANDING_REQ',
'OVERRUN', 'OreoMode', 'PACKET2_PAD_MASK', 'PACKET2_PAD_SHIFT',
'PACKET3_ACQUIRE_MEM', 'PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA',
'PACKET3_AQL_PACKET', 'PACKET3_ATOMIC_GDS', 'PACKET3_ATOMIC_MEM',
'PACKET3_BLK_CNTX_UPDATE', 'PACKET3_CLEAR_STATE',
'PACKET3_COND_EXEC', 'PACKET3_COND_INDIRECT_BUFFER',
'PACKET3_COND_INDIRECT_BUFFER_CNST', 'PACKET3_COND_PREEMPT',
'PACKET3_COND_WRITE', 'PACKET3_CONTEXT_CONTROL',
'PACKET3_CONTEXT_REG_RMW', 'PACKET3_COPY_DATA',
'PACKET3_COPY_DATA_RB', 'PACKET3_COPY_DW', 'PACKET3_CP_DMA',
'PACKET3_DISPATCH_DIRECT', 'PACKET3_DISPATCH_DRAW',
'PACKET3_DISPATCH_DRAW_ACE', 'PACKET3_DISPATCH_DRAW_PREAMBLE',
'PACKET3_DISPATCH_DRAW_PREAMBLE_ACE', 'PACKET3_DISPATCH_INDIRECT',
'PACKET3_DMA_DATA', 'PACKET3_DMA_DATA_CMD_DAIC',
'PACKET3_DMA_DATA_CMD_DAS', 'PACKET3_DMA_DATA_CMD_RAW_WAIT',
'PACKET3_DMA_DATA_CMD_SAIC', 'PACKET3_DMA_DATA_CMD_SAS',
'PACKET3_DMA_DATA_CP_SYNC', 'PACKET3_DMA_DATA_FILL_MULTI',
'PACKET3_DRAW_INDEX_2', 'PACKET3_DRAW_INDEX_AUTO',
'PACKET3_DRAW_INDEX_INDIRECT',
'PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI',
'PACKET3_DRAW_INDEX_INDIRECT_MULTI',
'PACKET3_DRAW_INDEX_MULTI_AUTO', 'PACKET3_DRAW_INDEX_MULTI_INST',
'PACKET3_DRAW_INDEX_OFFSET_2', 'PACKET3_DRAW_INDIRECT',
'PACKET3_DRAW_INDIRECT_COUNT_MULTI',
'PACKET3_DRAW_INDIRECT_MULTI', 'PACKET3_DRAW_MULTI_PREAMBLE',
'PACKET3_DRAW_PREAMBLE', 'PACKET3_DUMP_CONST_RAM',
'PACKET3_DUMP_CONST_RAM_OFFSET', 'PACKET3_EVENT_WRITE',
'PACKET3_EVENT_WRITE_EOP', 'PACKET3_EVENT_WRITE_EOS',
'PACKET3_FORWARD_HEADER', 'PACKET3_FRAME_CONTROL',
'PACKET3_GEN_PDEPTE', 'PACKET3_GET_LOD_STATS',
'PACKET3_GFX_CNTX_UPDATE', 'PACKET3_GFX_PIPE_LOCK',
'PACKET3_HDP_FLUSH', 'PACKET3_INCREMENT_CE_COUNTER',
'PACKET3_INCREMENT_DE_COUNTER', 'PACKET3_INCR_UPDT_STATE',
'PACKET3_INDEX_ATTRIBUTES_INDIRECT', 'PACKET3_INDEX_BASE',
'PACKET3_INDEX_BUFFER_SIZE', 'PACKET3_INDEX_TYPE',
'PACKET3_INDIRECT_BUFFER', 'PACKET3_INDIRECT_BUFFER_CNST',
'PACKET3_INDIRECT_BUFFER_CNST_END', 'PACKET3_INDIRECT_BUFFER_END',
'PACKET3_INDIRECT_BUFFER_PASID', 'PACKET3_INDIRECT_BUFFER_PRIV',
'PACKET3_INTERRUPT', 'PACKET3_INVALIDATE_TLBS',
'PACKET3_LOAD_COMPUTE_STATE', 'PACKET3_LOAD_CONFIG_REG',
'PACKET3_LOAD_CONST_RAM', 'PACKET3_LOAD_CONTEXT_REG',
'PACKET3_LOAD_CONTEXT_REG_INDEX', 'PACKET3_LOAD_SH_REG',
'PACKET3_LOAD_SH_REG_INDEX', 'PACKET3_LOAD_UCONFIG_REG',
'PACKET3_MAP_PROCESS', 'PACKET3_MAP_PROCESS_VM',
'PACKET3_MAP_QUEUES', 'PACKET3_MEM_SEMAPHORE',
'PACKET3_ME_INITIALIZE', 'PACKET3_NOP', 'PACKET3_NUM_INSTANCES',
'PACKET3_OCCLUSION_QUERY', 'PACKET3_PFP_SYNC_ME',
'PACKET3_PREAMBLE_BEGIN_CLEAR_STATE', 'PACKET3_PREAMBLE_CNTL',
'PACKET3_PREAMBLE_END_CLEAR_STATE', 'PACKET3_PRED_EXEC',
'PACKET3_PRIME_UTCL2', 'PACKET3_QUERY_STATUS', 'PACKET3_REG_RMW',
'PACKET3_RELEASE_MEM', 'PACKET3_RELEASE_MEM_EXECUTE',
'PACKET3_RELEASE_MEM_GCR_GL1_INV',
'PACKET3_RELEASE_MEM_GCR_GL2_DISCARD',
'PACKET3_RELEASE_MEM_GCR_GL2_INV',
'PACKET3_RELEASE_MEM_GCR_GL2_RANGE',
'PACKET3_RELEASE_MEM_GCR_GL2_US',
'PACKET3_RELEASE_MEM_GCR_GL2_WB',
'PACKET3_RELEASE_MEM_GCR_GLM_INV',
'PACKET3_RELEASE_MEM_GCR_GLM_WB',
'PACKET3_RELEASE_MEM_GCR_GLV_INV', 'PACKET3_RELEASE_MEM_GCR_SEQ',
'PACKET3_REWIND', 'PACKET3_RUN_LIST', 'PACKET3_SCRATCH_RAM_READ',
'PACKET3_SCRATCH_RAM_WRITE', 'PACKET3_SEM_SEL_SIGNAL',
'PACKET3_SEM_SEL_SIGNAL_TYPE', 'PACKET3_SEM_SEL_WAIT',
'PACKET3_SEM_USE_MAILBOX', 'PACKET3_SET_BASE',
'PACKET3_SET_CONFIG_REG', 'PACKET3_SET_CONFIG_REG_END',
'PACKET3_SET_CONFIG_REG_START', 'PACKET3_SET_CONTEXT_REG',
'PACKET3_SET_CONTEXT_REG_END', 'PACKET3_SET_CONTEXT_REG_INDEX',
'PACKET3_SET_CONTEXT_REG_INDIRECT',
'PACKET3_SET_CONTEXT_REG_START', 'PACKET3_SET_PREDICATION',
'PACKET3_SET_QUEUE_REG', 'PACKET3_SET_Q_PREEMPTION_MODE',
'PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM',
'PACKET3_SET_RESOURCES', 'PACKET3_SET_SH_REG',
'PACKET3_SET_SH_REG_DI', 'PACKET3_SET_SH_REG_DI_MULTI',
'PACKET3_SET_SH_REG_END', 'PACKET3_SET_SH_REG_INDEX',
'PACKET3_SET_SH_REG_OFFSET', 'PACKET3_SET_SH_REG_START',
'PACKET3_SET_UCONFIG_REG', 'PACKET3_SET_UCONFIG_REG_END',
'PACKET3_SET_UCONFIG_REG_INDEX', 'PACKET3_SET_UCONFIG_REG_START',
'PACKET3_SET_VGPR_REG_DI_MULTI', 'PACKET3_STRMOUT_BUFFER_UPDATE',
'PACKET3_SURFACE_SYNC', 'PACKET3_SWITCH_BUFFER',
'PACKET3_UNMAP_QUEUES', 'PACKET3_WAIT_ON_CE_COUNTER',
'PACKET3_WAIT_ON_DE_COUNTER_DIFF', 'PACKET3_WAIT_REG_MEM',
'PACKET3_WAIT_REG_MEM64', 'PACKET3_WRITE_CONST_RAM',
'PACKET3_WRITE_DATA', 'PACKET_TYPE0', 'PACKET_TYPE1',
'PACKET_TYPE2', 'PACKET_TYPE3', 'PART_FRAC_EVEN', 'PART_FRAC_ODD',
'PART_INTEGER', 'PART_POW2', 'PATCHES', 'PCIE0_BASE',
'PCIE0_BASE__INST0_SEG0', 'PCIE0_BASE__INST0_SEG1',
'PCIE0_BASE__INST0_SEG2', 'PCIE0_BASE__INST0_SEG3',
'PCIE0_BASE__INST0_SEG4', 'PCIE0_BASE__INST1_SEG0',
'PCIE0_BASE__INST1_SEG1', 'PCIE0_BASE__INST1_SEG2',
'PCIE0_BASE__INST1_SEG3', 'PCIE0_BASE__INST1_SEG4',
'PCIE0_BASE__INST2_SEG0', 'PCIE0_BASE__INST2_SEG1',
'PCIE0_BASE__INST2_SEG2', 'PCIE0_BASE__INST2_SEG3',
'PCIE0_BASE__INST2_SEG4', 'PCIE0_BASE__INST3_SEG0',
'PCIE0_BASE__INST3_SEG1', 'PCIE0_BASE__INST3_SEG2',
'PCIE0_BASE__INST3_SEG3', 'PCIE0_BASE__INST3_SEG4',
'PCIE0_BASE__INST4_SEG0', 'PCIE0_BASE__INST4_SEG1',
'PCIE0_BASE__INST4_SEG2', 'PCIE0_BASE__INST4_SEG3',
'PCIE0_BASE__INST4_SEG4', 'PCIE0_BASE__INST5_SEG0',
'PCIE0_BASE__INST5_SEG1', 'PCIE0_BASE__INST5_SEG2',
'PCIE0_BASE__INST5_SEG3', 'PCIE0_BASE__INST5_SEG4',
'PCIE0_BASE__INST6_SEG0', 'PCIE0_BASE__INST6_SEG1',
'PCIE0_BASE__INST6_SEG2', 'PCIE0_BASE__INST6_SEG3',
'PCIE0_BASE__INST6_SEG4', 'PERFCOUNTER_ACTIVE',
'PERFCOUNTER_CNT0_STATE', 'PERFCOUNTER_CNT0_STATE_FREEZE',
'PERFCOUNTER_CNT0_STATE_HW', 'PERFCOUNTER_CNT0_STATE_RESET',
'PERFCOUNTER_CNT0_STATE_START', 'PERFCOUNTER_CNT1_STATE',
'PERFCOUNTER_CNT1_STATE_FREEZE', 'PERFCOUNTER_CNT1_STATE_HW',
'PERFCOUNTER_CNT1_STATE_RESET', 'PERFCOUNTER_CNT1_STATE_START',
'PERFCOUNTER_CNT2_STATE', 'PERFCOUNTER_CNT2_STATE_FREEZE',
'PERFCOUNTER_CNT2_STATE_HW', 'PERFCOUNTER_CNT2_STATE_RESET',
'PERFCOUNTER_CNT2_STATE_START', 'PERFCOUNTER_CNT3_STATE',
'PERFCOUNTER_CNT3_STATE_FREEZE', 'PERFCOUNTER_CNT3_STATE_HW',
'PERFCOUNTER_CNT3_STATE_RESET', 'PERFCOUNTER_CNT3_STATE_START',
'PERFCOUNTER_CNT4_STATE', 'PERFCOUNTER_CNT4_STATE_FREEZE',
'PERFCOUNTER_CNT4_STATE_HW', 'PERFCOUNTER_CNT4_STATE_RESET',
'PERFCOUNTER_CNT4_STATE_START', 'PERFCOUNTER_CNT5_STATE',
'PERFCOUNTER_CNT5_STATE_FREEZE', 'PERFCOUNTER_CNT5_STATE_HW',
'PERFCOUNTER_CNT5_STATE_RESET', 'PERFCOUNTER_CNT5_STATE_START',
'PERFCOUNTER_CNT6_STATE', 'PERFCOUNTER_CNT6_STATE_FREEZE',
'PERFCOUNTER_CNT6_STATE_HW', 'PERFCOUNTER_CNT6_STATE_RESET',
'PERFCOUNTER_CNT6_STATE_START', 'PERFCOUNTER_CNT7_STATE',
'PERFCOUNTER_CNT7_STATE_FREEZE', 'PERFCOUNTER_CNT7_STATE_HW',
'PERFCOUNTER_CNT7_STATE_RESET', 'PERFCOUNTER_CNT7_STATE_START',
'PERFCOUNTER_CNTL_SEL', 'PERFCOUNTER_CNTL_SEL_0',
'PERFCOUNTER_CNTL_SEL_1', 'PERFCOUNTER_CNTL_SEL_2',
'PERFCOUNTER_CNTL_SEL_3', 'PERFCOUNTER_CNTL_SEL_4',
'PERFCOUNTER_CNTL_SEL_5', 'PERFCOUNTER_CNTL_SEL_6',
'PERFCOUNTER_CNTL_SEL_7', 'PERFCOUNTER_CNTOFF_START_DIS',
'PERFCOUNTER_CNTOFF_START_DISABLE',
'PERFCOUNTER_CNTOFF_START_ENABLE',
'PERFCOUNTER_COUNTED_VALUE_TYPE',
'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC',
'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX',
'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL',
'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0',
'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16',
'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0',
'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36',
'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF',
'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_HW_STOP1_0',
'PERFCOUNTER_HW_STOP1_1', 'PERFCOUNTER_HW_STOP1_SEL',
'PERFCOUNTER_HW_STOP2_0', 'PERFCOUNTER_HW_STOP2_1',
'PERFCOUNTER_HW_STOP2_SEL', 'PERFCOUNTER_INC_MODE',
'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB',
'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE',
'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE',
'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE',
'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL',
'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE',
'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK',
'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE',
'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN',
'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE',
'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL',
'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START',
'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL',
'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1',
'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL',
'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL',
'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3',
'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL',
'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL',
'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5',
'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL',
'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL',
'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7',
'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL',
'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR',
'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN',
'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE',
'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE',
'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE',
'PERFMON_COUNTER_MODE_ACCUM',
'PERFMON_COUNTER_MODE_ACTIVE_CYCLES',
'PERFMON_COUNTER_MODE_CYCLES_EQ_HI',
'PERFMON_COUNTER_MODE_CYCLES_GE_HI',
'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT',
'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT',
'PERFMON_COUNTER_MODE_DIRTY',
'PERFMON_COUNTER_MODE_INACTIVE_CYCLES',
'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED',
'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE',
'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP',
'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP',
'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5',
'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7',
'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1',
'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE',
'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET',
'PERFMON_STATE_START', 'PERF_CLIPSM_CULL_PRIMS_CNT',
'PERF_ENGG_BUSY', 'PERF_ENGG_CSB_DELAY_BIN00',
'PERF_ENGG_CSB_DELAY_BIN01', 'PERF_ENGG_CSB_DELAY_BIN02',
'PERF_ENGG_CSB_DELAY_BIN03', 'PERF_ENGG_CSB_DELAY_BIN04',
'PERF_ENGG_CSB_DELAY_BIN05', 'PERF_ENGG_CSB_DELAY_BIN06',
'PERF_ENGG_CSB_DELAY_BIN07', 'PERF_ENGG_CSB_DELAY_BIN08',
'PERF_ENGG_CSB_DELAY_BIN09', 'PERF_ENGG_CSB_DELAY_BIN10',
'PERF_ENGG_CSB_DELAY_BIN11', 'PERF_ENGG_CSB_DELAY_BIN12',
'PERF_ENGG_CSB_DELAY_BIN13', 'PERF_ENGG_CSB_DELAY_BIN14',
'PERF_ENGG_CSB_DELAY_BIN15', 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL',
'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT',
'PERF_ENGG_CSB_GE_MEMORY_EMPTY', 'PERF_ENGG_CSB_GE_MEMORY_FULL',
'PERF_ENGG_CSB_GE_SENDING_SUBGROUP',
'PERF_ENGG_CSB_MACHINE_IS_STARVED',
'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY',
'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI',
'PERF_ENGG_CSB_NULL_SUBGROUP',
'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL',
'PERF_ENGG_CSB_PRIM_COUNT_EQ0', 'PERF_ENGG_CSB_SPI_DELAY_BIN00',
'PERF_ENGG_CSB_SPI_DELAY_BIN01', 'PERF_ENGG_CSB_SPI_DELAY_BIN02',
'PERF_ENGG_CSB_SPI_DELAY_BIN03', 'PERF_ENGG_CSB_SPI_DELAY_BIN04',
'PERF_ENGG_CSB_SPI_DELAY_BIN05', 'PERF_ENGG_CSB_SPI_DELAY_BIN06',
'PERF_ENGG_CSB_SPI_DELAY_BIN07', 'PERF_ENGG_CSB_SPI_DELAY_BIN08',
'PERF_ENGG_CSB_SPI_DELAY_BIN09', 'PERF_ENGG_CSB_SPI_DELAY_BIN10',
'PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL',
'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', 'PERF_ENGG_CSB_SPI_MEMORY_FULL',
'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE',
'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE',
'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO',
'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO',
'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB',
'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM',
'PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM',
'PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM',
'PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM',
'PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM',
'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL',
'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL',
'PERF_ENGG_INDEX_REQ_NULL_REQUEST',
'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS',
'PERF_ENGG_INDEX_REQ_STARVED',
'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY',
'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL',
'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO',
'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT',
'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL',
'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL',
'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0',
'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO',
'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO',
'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB',
'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS',
'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL',
'PERF_ENGG_POS_REQ_STARVED', 'PERF_OUTPUT_PRIM_1_SC',
'PERF_OUTPUT_PRIM_2_SC', 'PERF_OUTPUT_PRIM_3_SC',
'PERF_OUTPUT_PRIM_4_SC', 'PERF_PAPC_CCGSM_BUSY',
'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED',
'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE',
'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP',
'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY',
'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP',
'PERF_PAPC_CLIPSM_WAIT_CLIPGA',
'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM',
'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH',
'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY',
'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY',
'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED',
'PERF_PAPC_CLPRIM_STARVED_CCGSM',
'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8',
'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12',
'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT',
'PERF_PAPC_CLPR_CLIP_PLANE_NEAR',
'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT',
'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM',
'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM',
'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM',
'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE',
'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM',
'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM',
'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM',
'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM',
'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM',
'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM',
'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM',
'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM',
'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2',
'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4',
'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8',
'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13',
'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM',
'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_DISABLE_PIPE',
'PERF_PAPC_PASX_FIRST_DEAD', 'PERF_PAPC_PASX_FIRST_VECTOR',
'PERF_PAPC_PASX_REC_BUSY', 'PERF_PAPC_PASX_REC_IDLE',
'PERF_PAPC_PASX_REC_STALLED',
'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN',
'PERF_PAPC_PASX_REC_STALLED_POS_MEM',
'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ',
'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE',
'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_SE0_FIRST_VECTOR',
'PERF_PAPC_PASX_SE0_REQ', 'PERF_PAPC_PASX_SE0_SECOND_VECTOR',
'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 'PERF_PAPC_PASX_SE1_REQ',
'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 'PERF_PAPC_PASX_SECOND_DEAD',
'PERF_PAPC_PASX_SECOND_VECTOR', 'PERF_PAPC_PASX_VTX_KILL_DISCARD',
'PERF_PAPC_PASX_VTX_NAN_DISCARD',
'PERF_PAPC_PA_INPUT_END_OF_PACKET',
'PERF_PAPC_PA_INPUT_EVENT_FLAG',
'PERF_PAPC_PA_INPUT_EXTENDED_EVENT',
'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT',
'PERF_PAPC_PA_INPUT_NULL_PRIM', 'PERF_PAPC_PA_INPUT_PRIM',
'PERF_PAPC_PA_REG_SCLK_VLD', 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM',
'PERF_PAPC_SU_BUSY', 'PERF_PAPC_SU_CULLED_PRIM',
'PERF_PAPC_SU_DYN_SCLK_VLD', 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM',
'PERF_PAPC_SU_IDLE', 'PERF_PAPC_SU_INPUT_CLIP_PRIM',
'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL',
'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM',
'PERF_PAPC_SU_INPUT_PRIM_DUAL',
'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL',
'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL',
'PERF_PAPC_SU_OUTPUT_CLIP_PRIM',
'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL',
'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG',
'PERF_PAPC_SU_OUTPUT_EVENT_FLAG',
'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT',
'PERF_PAPC_SU_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK',
'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL',
'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE',
'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM',
'PERF_PAPC_SU_OUTPUT_PRIM_DUAL',
'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK',
'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE',
'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT',
'PERF_PAPC_SU_POLYMODE_BACK_CULL',
'PERF_PAPC_SU_POLYMODE_FACE_CULL',
'PERF_PAPC_SU_POLYMODE_FRONT_CULL',
'PERF_PAPC_SU_POLYMODE_INVALID_FILL',
'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE01_OUTPUT_PRIM',
'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE01_STALLED_SC',
'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET',
'PERF_PAPC_SU_SE0_OUTPUT_EOPG',
'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT',
'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE0_OUTPUT_PRIM',
'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE0_STALLED_SC',
'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET',
'PERF_PAPC_SU_SE1_OUTPUT_EOPG',
'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT',
'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE1_OUTPUT_PRIM',
'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE1_STALLED_SC',
'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET',
'PERF_PAPC_SU_SE2_OUTPUT_EOPG',
'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE2_OUTPUT_PRIM',
'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE2_STALLED_SC',
'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET',
'PERF_PAPC_SU_SE3_OUTPUT_EOPG',
'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM',
'PERF_PAPC_SU_SE3_OUTPUT_PRIM',
'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL',
'PERF_PAPC_SU_SE3_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC',
'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM',
'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL',
'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', 'PERF_PA_PIPE0_SWITCHED_GEN',
'PERF_PA_PIPE1_SWITCHED_GEN',
'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', 'PERF_PA_VERTEX_FIFO_FULL',
'PERF_PH_SEND_1_SC', 'PERF_PH_SEND_2_SC', 'PERF_PH_SEND_3_SC',
'PERF_PH_SEND_4_SC', 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT',
'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT',
'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT',
'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT',
'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT',
'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT',
'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT',
'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT',
'PERF_SMALL_PRIM_CULL_PRIM_1X1', 'PERF_SMALL_PRIM_CULL_PRIM_1X2',
'PERF_SMALL_PRIM_CULL_PRIM_1X3', 'PERF_SMALL_PRIM_CULL_PRIM_1XN',
'PERF_SMALL_PRIM_CULL_PRIM_2X1', 'PERF_SMALL_PRIM_CULL_PRIM_2X2',
'PERF_SMALL_PRIM_CULL_PRIM_2X3', 'PERF_SMALL_PRIM_CULL_PRIM_2XN',
'PERF_SMALL_PRIM_CULL_PRIM_3X1', 'PERF_SMALL_PRIM_CULL_PRIM_3X2',
'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT',
'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT',
'PERF_SMALL_PRIM_CULL_PRIM_NX1', 'PERF_SMALL_PRIM_CULL_PRIM_NX2',
'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT',
'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', 'PERSISTENT_SPACE_END',
'PERSISTENT_SPACE_START', 'PHYSYMCLK_FORCE_EN',
'PHYSYMCLK_FORCE_EN_DISABLE', 'PHYSYMCLK_FORCE_EN_ENABLE',
'PHYSYMCLK_FORCE_SRC_PHYD18CLK', 'PHYSYMCLK_FORCE_SRC_PHYD32CLK',
'PHYSYMCLK_FORCE_SRC_SEL', 'PHYSYMCLK_FORCE_SRC_SYMCLK',
'PHY_CUSTOM_RATE', 'PHY_DP_RATE_10P', 'PHY_DP_RATE_13P5',
'PHY_DP_RATE_1P62', 'PHY_DP_RATE_20P', 'PHY_DP_RATE_2P16',
'PHY_DP_RATE_2P43', 'PHY_DP_RATE_2P7', 'PHY_DP_RATE_3P24',
'PHY_DP_RATE_4P32', 'PHY_DP_RATE_5P4', 'PHY_DP_RATE_8P1',
'PHY_IF_WIDTH_10BIT', 'PHY_IF_WIDTH_20BIT', 'PHY_IF_WIDTH_40BIT',
'PHY_IF_WIDTH_80BIT', 'PH_PERFCNT_SEL',
'PH_PERF_SC0_FIFO_STATUS_0', 'PH_PERF_SC0_FIFO_STATUS_1',
'PH_PERF_SC0_FIFO_STATUS_2', 'PH_PERF_SC0_FIFO_STATUS_3',
'PH_PERF_SC1_FIFO_STATUS_0', 'PH_PERF_SC1_FIFO_STATUS_1',
'PH_PERF_SC1_FIFO_STATUS_2', 'PH_PERF_SC1_FIFO_STATUS_3',
'PH_PERF_SC2_FIFO_STATUS_0', 'PH_PERF_SC2_FIFO_STATUS_1',
'PH_PERF_SC2_FIFO_STATUS_2', 'PH_PERF_SC2_FIFO_STATUS_3',
'PH_PERF_SC3_FIFO_STATUS_0', 'PH_PERF_SC3_FIFO_STATUS_1',
'PH_PERF_SC3_FIFO_STATUS_2', 'PH_PERF_SC3_FIFO_STATUS_3',
'PH_PERF_SC4_FIFO_STATUS_0', 'PH_PERF_SC4_FIFO_STATUS_1',
'PH_PERF_SC4_FIFO_STATUS_2', 'PH_PERF_SC4_FIFO_STATUS_3',
'PH_PERF_SC5_FIFO_STATUS_0', 'PH_PERF_SC5_FIFO_STATUS_1',
'PH_PERF_SC5_FIFO_STATUS_2', 'PH_PERF_SC5_FIFO_STATUS_3',
'PH_PERF_SC6_FIFO_STATUS_0', 'PH_PERF_SC6_FIFO_STATUS_1',
'PH_PERF_SC6_FIFO_STATUS_2', 'PH_PERF_SC6_FIFO_STATUS_3',
'PH_PERF_SC7_FIFO_STATUS_0', 'PH_PERF_SC7_FIFO_STATUS_1',
'PH_PERF_SC7_FIFO_STATUS_2', 'PH_PERF_SC7_FIFO_STATUS_3',
'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC0_ARB_BUSY',
'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC0_CREDIT_AT_MAX',
'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC0_PA0_EOPG_WE', 'PH_PERF_SEL_SC0_PA0_EOP_WE',
'PH_PERF_SEL_SC0_PA0_EVENT_WE', 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY',
'PH_PERF_SEL_SC0_PA0_FIFO_FULL', 'PH_PERF_SEL_SC0_PA0_FPOV_WE',
'PH_PERF_SEL_SC0_PA0_LPOV_WE', 'PH_PERF_SEL_SC0_PA0_NULL_WE',
'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC0_PA1_EOPG_WE', 'PH_PERF_SEL_SC0_PA1_EOP_WE',
'PH_PERF_SEL_SC0_PA1_EVENT_WE', 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY',
'PH_PERF_SEL_SC0_PA1_FIFO_FULL', 'PH_PERF_SEL_SC0_PA1_FPOV_WE',
'PH_PERF_SEL_SC0_PA1_LPOV_WE', 'PH_PERF_SEL_SC0_PA1_NULL_WE',
'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC0_PA2_EOPG_WE', 'PH_PERF_SEL_SC0_PA2_EOP_WE',
'PH_PERF_SEL_SC0_PA2_EVENT_WE', 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY',
'PH_PERF_SEL_SC0_PA2_FIFO_FULL', 'PH_PERF_SEL_SC0_PA2_FPOV_WE',
'PH_PERF_SEL_SC0_PA2_LPOV_WE', 'PH_PERF_SEL_SC0_PA2_NULL_WE',
'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC0_PA3_EOPG_WE', 'PH_PERF_SEL_SC0_PA3_EOP_WE',
'PH_PERF_SEL_SC0_PA3_EVENT_WE', 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY',
'PH_PERF_SEL_SC0_PA3_FIFO_FULL', 'PH_PERF_SEL_SC0_PA3_FPOV_WE',
'PH_PERF_SEL_SC0_PA3_LPOV_WE', 'PH_PERF_SEL_SC0_PA3_NULL_WE',
'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC0_PA4_EOPG_WE', 'PH_PERF_SEL_SC0_PA4_EOP_WE',
'PH_PERF_SEL_SC0_PA4_EVENT_WE', 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY',
'PH_PERF_SEL_SC0_PA4_FIFO_FULL', 'PH_PERF_SEL_SC0_PA4_FPOV_WE',
'PH_PERF_SEL_SC0_PA4_LPOV_WE', 'PH_PERF_SEL_SC0_PA4_NULL_WE',
'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC0_PA5_EOPG_WE', 'PH_PERF_SEL_SC0_PA5_EOP_WE',
'PH_PERF_SEL_SC0_PA5_EVENT_WE', 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY',
'PH_PERF_SEL_SC0_PA5_FIFO_FULL', 'PH_PERF_SEL_SC0_PA5_FPOV_WE',
'PH_PERF_SEL_SC0_PA5_LPOV_WE', 'PH_PERF_SEL_SC0_PA5_NULL_WE',
'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC0_PA6_EOPG_WE', 'PH_PERF_SEL_SC0_PA6_EOP_WE',
'PH_PERF_SEL_SC0_PA6_EVENT_WE', 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY',
'PH_PERF_SEL_SC0_PA6_FIFO_FULL', 'PH_PERF_SEL_SC0_PA6_FPOV_WE',
'PH_PERF_SEL_SC0_PA6_LPOV_WE', 'PH_PERF_SEL_SC0_PA6_NULL_WE',
'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC0_PA7_EOPG_WE', 'PH_PERF_SEL_SC0_PA7_EOP_WE',
'PH_PERF_SEL_SC0_PA7_EVENT_WE', 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY',
'PH_PERF_SEL_SC0_PA7_FIFO_FULL', 'PH_PERF_SEL_SC0_PA7_FPOV_WE',
'PH_PERF_SEL_SC0_PA7_LPOV_WE', 'PH_PERF_SEL_SC0_PA7_NULL_WE',
'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC0_SEND', 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC1_ARB_BUSY',
'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC1_CREDIT_AT_MAX',
'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC1_PA0_EOPG_WE', 'PH_PERF_SEL_SC1_PA0_EOP_WE',
'PH_PERF_SEL_SC1_PA0_EVENT_WE', 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY',
'PH_PERF_SEL_SC1_PA0_FIFO_FULL', 'PH_PERF_SEL_SC1_PA0_FPOV_WE',
'PH_PERF_SEL_SC1_PA0_LPOV_WE', 'PH_PERF_SEL_SC1_PA0_NULL_WE',
'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC1_PA1_EOPG_WE', 'PH_PERF_SEL_SC1_PA1_EOP_WE',
'PH_PERF_SEL_SC1_PA1_EVENT_WE', 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY',
'PH_PERF_SEL_SC1_PA1_FIFO_FULL', 'PH_PERF_SEL_SC1_PA1_FPOV_WE',
'PH_PERF_SEL_SC1_PA1_LPOV_WE', 'PH_PERF_SEL_SC1_PA1_NULL_WE',
'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC1_PA2_EOPG_WE', 'PH_PERF_SEL_SC1_PA2_EOP_WE',
'PH_PERF_SEL_SC1_PA2_EVENT_WE', 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY',
'PH_PERF_SEL_SC1_PA2_FIFO_FULL', 'PH_PERF_SEL_SC1_PA2_FPOV_WE',
'PH_PERF_SEL_SC1_PA2_LPOV_WE', 'PH_PERF_SEL_SC1_PA2_NULL_WE',
'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC1_PA3_EOPG_WE', 'PH_PERF_SEL_SC1_PA3_EOP_WE',
'PH_PERF_SEL_SC1_PA3_EVENT_WE', 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY',
'PH_PERF_SEL_SC1_PA3_FIFO_FULL', 'PH_PERF_SEL_SC1_PA3_FPOV_WE',
'PH_PERF_SEL_SC1_PA3_LPOV_WE', 'PH_PERF_SEL_SC1_PA3_NULL_WE',
'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC1_PA4_EOPG_WE', 'PH_PERF_SEL_SC1_PA4_EOP_WE',
'PH_PERF_SEL_SC1_PA4_EVENT_WE', 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY',
'PH_PERF_SEL_SC1_PA4_FIFO_FULL', 'PH_PERF_SEL_SC1_PA4_FPOV_WE',
'PH_PERF_SEL_SC1_PA4_LPOV_WE', 'PH_PERF_SEL_SC1_PA4_NULL_WE',
'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC1_PA5_EOPG_WE', 'PH_PERF_SEL_SC1_PA5_EOP_WE',
'PH_PERF_SEL_SC1_PA5_EVENT_WE', 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY',
'PH_PERF_SEL_SC1_PA5_FIFO_FULL', 'PH_PERF_SEL_SC1_PA5_FPOV_WE',
'PH_PERF_SEL_SC1_PA5_LPOV_WE', 'PH_PERF_SEL_SC1_PA5_NULL_WE',
'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC1_PA6_EOPG_WE', 'PH_PERF_SEL_SC1_PA6_EOP_WE',
'PH_PERF_SEL_SC1_PA6_EVENT_WE', 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY',
'PH_PERF_SEL_SC1_PA6_FIFO_FULL', 'PH_PERF_SEL_SC1_PA6_FPOV_WE',
'PH_PERF_SEL_SC1_PA6_LPOV_WE', 'PH_PERF_SEL_SC1_PA6_NULL_WE',
'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC1_PA7_EOPG_WE', 'PH_PERF_SEL_SC1_PA7_EOP_WE',
'PH_PERF_SEL_SC1_PA7_EVENT_WE', 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY',
'PH_PERF_SEL_SC1_PA7_FIFO_FULL', 'PH_PERF_SEL_SC1_PA7_FPOV_WE',
'PH_PERF_SEL_SC1_PA7_LPOV_WE', 'PH_PERF_SEL_SC1_PA7_NULL_WE',
'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC1_SEND', 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC2_ARB_BUSY',
'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC2_CREDIT_AT_MAX',
'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC2_PA0_EOPG_WE', 'PH_PERF_SEL_SC2_PA0_EOP_WE',
'PH_PERF_SEL_SC2_PA0_EVENT_WE', 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY',
'PH_PERF_SEL_SC2_PA0_FIFO_FULL', 'PH_PERF_SEL_SC2_PA0_FPOV_WE',
'PH_PERF_SEL_SC2_PA0_LPOV_WE', 'PH_PERF_SEL_SC2_PA0_NULL_WE',
'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC2_PA1_EOPG_WE', 'PH_PERF_SEL_SC2_PA1_EOP_WE',
'PH_PERF_SEL_SC2_PA1_EVENT_WE', 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY',
'PH_PERF_SEL_SC2_PA1_FIFO_FULL', 'PH_PERF_SEL_SC2_PA1_FPOV_WE',
'PH_PERF_SEL_SC2_PA1_LPOV_WE', 'PH_PERF_SEL_SC2_PA1_NULL_WE',
'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC2_PA2_EOPG_WE', 'PH_PERF_SEL_SC2_PA2_EOP_WE',
'PH_PERF_SEL_SC2_PA2_EVENT_WE', 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY',
'PH_PERF_SEL_SC2_PA2_FIFO_FULL', 'PH_PERF_SEL_SC2_PA2_FPOV_WE',
'PH_PERF_SEL_SC2_PA2_LPOV_WE', 'PH_PERF_SEL_SC2_PA2_NULL_WE',
'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC2_PA3_EOPG_WE', 'PH_PERF_SEL_SC2_PA3_EOP_WE',
'PH_PERF_SEL_SC2_PA3_EVENT_WE', 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY',
'PH_PERF_SEL_SC2_PA3_FIFO_FULL', 'PH_PERF_SEL_SC2_PA3_FPOV_WE',
'PH_PERF_SEL_SC2_PA3_LPOV_WE', 'PH_PERF_SEL_SC2_PA3_NULL_WE',
'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC2_PA4_EOPG_WE', 'PH_PERF_SEL_SC2_PA4_EOP_WE',
'PH_PERF_SEL_SC2_PA4_EVENT_WE', 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY',
'PH_PERF_SEL_SC2_PA4_FIFO_FULL', 'PH_PERF_SEL_SC2_PA4_FPOV_WE',
'PH_PERF_SEL_SC2_PA4_LPOV_WE', 'PH_PERF_SEL_SC2_PA4_NULL_WE',
'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC2_PA5_EOPG_WE', 'PH_PERF_SEL_SC2_PA5_EOP_WE',
'PH_PERF_SEL_SC2_PA5_EVENT_WE', 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY',
'PH_PERF_SEL_SC2_PA5_FIFO_FULL', 'PH_PERF_SEL_SC2_PA5_FPOV_WE',
'PH_PERF_SEL_SC2_PA5_LPOV_WE', 'PH_PERF_SEL_SC2_PA5_NULL_WE',
'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC2_PA6_EOPG_WE', 'PH_PERF_SEL_SC2_PA6_EOP_WE',
'PH_PERF_SEL_SC2_PA6_EVENT_WE', 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY',
'PH_PERF_SEL_SC2_PA6_FIFO_FULL', 'PH_PERF_SEL_SC2_PA6_FPOV_WE',
'PH_PERF_SEL_SC2_PA6_LPOV_WE', 'PH_PERF_SEL_SC2_PA6_NULL_WE',
'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC2_PA7_EOPG_WE', 'PH_PERF_SEL_SC2_PA7_EOP_WE',
'PH_PERF_SEL_SC2_PA7_EVENT_WE', 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY',
'PH_PERF_SEL_SC2_PA7_FIFO_FULL', 'PH_PERF_SEL_SC2_PA7_FPOV_WE',
'PH_PERF_SEL_SC2_PA7_LPOV_WE', 'PH_PERF_SEL_SC2_PA7_NULL_WE',
'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC2_SEND', 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC3_ARB_BUSY',
'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC3_CREDIT_AT_MAX',
'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC3_PA0_EOPG_WE', 'PH_PERF_SEL_SC3_PA0_EOP_WE',
'PH_PERF_SEL_SC3_PA0_EVENT_WE', 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY',
'PH_PERF_SEL_SC3_PA0_FIFO_FULL', 'PH_PERF_SEL_SC3_PA0_FPOV_WE',
'PH_PERF_SEL_SC3_PA0_LPOV_WE', 'PH_PERF_SEL_SC3_PA0_NULL_WE',
'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC3_PA1_EOPG_WE', 'PH_PERF_SEL_SC3_PA1_EOP_WE',
'PH_PERF_SEL_SC3_PA1_EVENT_WE', 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY',
'PH_PERF_SEL_SC3_PA1_FIFO_FULL', 'PH_PERF_SEL_SC3_PA1_FPOV_WE',
'PH_PERF_SEL_SC3_PA1_LPOV_WE', 'PH_PERF_SEL_SC3_PA1_NULL_WE',
'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC3_PA2_EOPG_WE', 'PH_PERF_SEL_SC3_PA2_EOP_WE',
'PH_PERF_SEL_SC3_PA2_EVENT_WE', 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY',
'PH_PERF_SEL_SC3_PA2_FIFO_FULL', 'PH_PERF_SEL_SC3_PA2_FPOV_WE',
'PH_PERF_SEL_SC3_PA2_LPOV_WE', 'PH_PERF_SEL_SC3_PA2_NULL_WE',
'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC3_PA3_EOPG_WE', 'PH_PERF_SEL_SC3_PA3_EOP_WE',
'PH_PERF_SEL_SC3_PA3_EVENT_WE', 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY',
'PH_PERF_SEL_SC3_PA3_FIFO_FULL', 'PH_PERF_SEL_SC3_PA3_FPOV_WE',
'PH_PERF_SEL_SC3_PA3_LPOV_WE', 'PH_PERF_SEL_SC3_PA3_NULL_WE',
'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC3_PA4_EOPG_WE', 'PH_PERF_SEL_SC3_PA4_EOP_WE',
'PH_PERF_SEL_SC3_PA4_EVENT_WE', 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY',
'PH_PERF_SEL_SC3_PA4_FIFO_FULL', 'PH_PERF_SEL_SC3_PA4_FPOV_WE',
'PH_PERF_SEL_SC3_PA4_LPOV_WE', 'PH_PERF_SEL_SC3_PA4_NULL_WE',
'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC3_PA5_EOPG_WE', 'PH_PERF_SEL_SC3_PA5_EOP_WE',
'PH_PERF_SEL_SC3_PA5_EVENT_WE', 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY',
'PH_PERF_SEL_SC3_PA5_FIFO_FULL', 'PH_PERF_SEL_SC3_PA5_FPOV_WE',
'PH_PERF_SEL_SC3_PA5_LPOV_WE', 'PH_PERF_SEL_SC3_PA5_NULL_WE',
'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC3_PA6_EOPG_WE', 'PH_PERF_SEL_SC3_PA6_EOP_WE',
'PH_PERF_SEL_SC3_PA6_EVENT_WE', 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY',
'PH_PERF_SEL_SC3_PA6_FIFO_FULL', 'PH_PERF_SEL_SC3_PA6_FPOV_WE',
'PH_PERF_SEL_SC3_PA6_LPOV_WE', 'PH_PERF_SEL_SC3_PA6_NULL_WE',
'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC3_PA7_EOPG_WE', 'PH_PERF_SEL_SC3_PA7_EOP_WE',
'PH_PERF_SEL_SC3_PA7_EVENT_WE', 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY',
'PH_PERF_SEL_SC3_PA7_FIFO_FULL', 'PH_PERF_SEL_SC3_PA7_FPOV_WE',
'PH_PERF_SEL_SC3_PA7_LPOV_WE', 'PH_PERF_SEL_SC3_PA7_NULL_WE',
'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC3_SEND', 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC4_ARB_BUSY',
'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC4_CREDIT_AT_MAX',
'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC4_PA0_EOPG_WE', 'PH_PERF_SEL_SC4_PA0_EOP_WE',
'PH_PERF_SEL_SC4_PA0_EVENT_WE', 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY',
'PH_PERF_SEL_SC4_PA0_FIFO_FULL', 'PH_PERF_SEL_SC4_PA0_FPOV_WE',
'PH_PERF_SEL_SC4_PA0_LPOV_WE', 'PH_PERF_SEL_SC4_PA0_NULL_WE',
'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC4_PA1_EOPG_WE', 'PH_PERF_SEL_SC4_PA1_EOP_WE',
'PH_PERF_SEL_SC4_PA1_EVENT_WE', 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY',
'PH_PERF_SEL_SC4_PA1_FIFO_FULL', 'PH_PERF_SEL_SC4_PA1_FPOV_WE',
'PH_PERF_SEL_SC4_PA1_LPOV_WE', 'PH_PERF_SEL_SC4_PA1_NULL_WE',
'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC4_PA2_EOPG_WE', 'PH_PERF_SEL_SC4_PA2_EOP_WE',
'PH_PERF_SEL_SC4_PA2_EVENT_WE', 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY',
'PH_PERF_SEL_SC4_PA2_FIFO_FULL', 'PH_PERF_SEL_SC4_PA2_FPOV_WE',
'PH_PERF_SEL_SC4_PA2_LPOV_WE', 'PH_PERF_SEL_SC4_PA2_NULL_WE',
'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC4_PA3_EOPG_WE', 'PH_PERF_SEL_SC4_PA3_EOP_WE',
'PH_PERF_SEL_SC4_PA3_EVENT_WE', 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY',
'PH_PERF_SEL_SC4_PA3_FIFO_FULL', 'PH_PERF_SEL_SC4_PA3_FPOV_WE',
'PH_PERF_SEL_SC4_PA3_LPOV_WE', 'PH_PERF_SEL_SC4_PA3_NULL_WE',
'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC4_PA4_EOPG_WE', 'PH_PERF_SEL_SC4_PA4_EOP_WE',
'PH_PERF_SEL_SC4_PA4_EVENT_WE', 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY',
'PH_PERF_SEL_SC4_PA4_FIFO_FULL', 'PH_PERF_SEL_SC4_PA4_FPOV_WE',
'PH_PERF_SEL_SC4_PA4_LPOV_WE', 'PH_PERF_SEL_SC4_PA4_NULL_WE',
'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC4_PA5_EOPG_WE', 'PH_PERF_SEL_SC4_PA5_EOP_WE',
'PH_PERF_SEL_SC4_PA5_EVENT_WE', 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY',
'PH_PERF_SEL_SC4_PA5_FIFO_FULL', 'PH_PERF_SEL_SC4_PA5_FPOV_WE',
'PH_PERF_SEL_SC4_PA5_LPOV_WE', 'PH_PERF_SEL_SC4_PA5_NULL_WE',
'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC4_PA6_EOPG_WE', 'PH_PERF_SEL_SC4_PA6_EOP_WE',
'PH_PERF_SEL_SC4_PA6_EVENT_WE', 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY',
'PH_PERF_SEL_SC4_PA6_FIFO_FULL', 'PH_PERF_SEL_SC4_PA6_FPOV_WE',
'PH_PERF_SEL_SC4_PA6_LPOV_WE', 'PH_PERF_SEL_SC4_PA6_NULL_WE',
'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC4_PA7_EOPG_WE', 'PH_PERF_SEL_SC4_PA7_EOP_WE',
'PH_PERF_SEL_SC4_PA7_EVENT_WE', 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY',
'PH_PERF_SEL_SC4_PA7_FIFO_FULL', 'PH_PERF_SEL_SC4_PA7_FPOV_WE',
'PH_PERF_SEL_SC4_PA7_LPOV_WE', 'PH_PERF_SEL_SC4_PA7_NULL_WE',
'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC4_SEND', 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC5_ARB_BUSY',
'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC5_CREDIT_AT_MAX',
'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC5_PA0_EOPG_WE', 'PH_PERF_SEL_SC5_PA0_EOP_WE',
'PH_PERF_SEL_SC5_PA0_EVENT_WE', 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY',
'PH_PERF_SEL_SC5_PA0_FIFO_FULL', 'PH_PERF_SEL_SC5_PA0_FPOV_WE',
'PH_PERF_SEL_SC5_PA0_LPOV_WE', 'PH_PERF_SEL_SC5_PA0_NULL_WE',
'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC5_PA1_EOPG_WE', 'PH_PERF_SEL_SC5_PA1_EOP_WE',
'PH_PERF_SEL_SC5_PA1_EVENT_WE', 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY',
'PH_PERF_SEL_SC5_PA1_FIFO_FULL', 'PH_PERF_SEL_SC5_PA1_FPOV_WE',
'PH_PERF_SEL_SC5_PA1_LPOV_WE', 'PH_PERF_SEL_SC5_PA1_NULL_WE',
'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC5_PA2_EOPG_WE', 'PH_PERF_SEL_SC5_PA2_EOP_WE',
'PH_PERF_SEL_SC5_PA2_EVENT_WE', 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY',
'PH_PERF_SEL_SC5_PA2_FIFO_FULL', 'PH_PERF_SEL_SC5_PA2_FPOV_WE',
'PH_PERF_SEL_SC5_PA2_LPOV_WE', 'PH_PERF_SEL_SC5_PA2_NULL_WE',
'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC5_PA3_EOPG_WE', 'PH_PERF_SEL_SC5_PA3_EOP_WE',
'PH_PERF_SEL_SC5_PA3_EVENT_WE', 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY',
'PH_PERF_SEL_SC5_PA3_FIFO_FULL', 'PH_PERF_SEL_SC5_PA3_FPOV_WE',
'PH_PERF_SEL_SC5_PA3_LPOV_WE', 'PH_PERF_SEL_SC5_PA3_NULL_WE',
'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC5_PA4_EOPG_WE', 'PH_PERF_SEL_SC5_PA4_EOP_WE',
'PH_PERF_SEL_SC5_PA4_EVENT_WE', 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY',
'PH_PERF_SEL_SC5_PA4_FIFO_FULL', 'PH_PERF_SEL_SC5_PA4_FPOV_WE',
'PH_PERF_SEL_SC5_PA4_LPOV_WE', 'PH_PERF_SEL_SC5_PA4_NULL_WE',
'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC5_PA5_EOPG_WE', 'PH_PERF_SEL_SC5_PA5_EOP_WE',
'PH_PERF_SEL_SC5_PA5_EVENT_WE', 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY',
'PH_PERF_SEL_SC5_PA5_FIFO_FULL', 'PH_PERF_SEL_SC5_PA5_FPOV_WE',
'PH_PERF_SEL_SC5_PA5_LPOV_WE', 'PH_PERF_SEL_SC5_PA5_NULL_WE',
'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC5_PA6_EOPG_WE', 'PH_PERF_SEL_SC5_PA6_EOP_WE',
'PH_PERF_SEL_SC5_PA6_EVENT_WE', 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY',
'PH_PERF_SEL_SC5_PA6_FIFO_FULL', 'PH_PERF_SEL_SC5_PA6_FPOV_WE',
'PH_PERF_SEL_SC5_PA6_LPOV_WE', 'PH_PERF_SEL_SC5_PA6_NULL_WE',
'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC5_PA7_EOPG_WE', 'PH_PERF_SEL_SC5_PA7_EOP_WE',
'PH_PERF_SEL_SC5_PA7_EVENT_WE', 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY',
'PH_PERF_SEL_SC5_PA7_FIFO_FULL', 'PH_PERF_SEL_SC5_PA7_FPOV_WE',
'PH_PERF_SEL_SC5_PA7_LPOV_WE', 'PH_PERF_SEL_SC5_PA7_NULL_WE',
'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC5_SEND', 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC6_ARB_BUSY',
'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC6_CREDIT_AT_MAX',
'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC6_PA0_EOPG_WE', 'PH_PERF_SEL_SC6_PA0_EOP_WE',
'PH_PERF_SEL_SC6_PA0_EVENT_WE', 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY',
'PH_PERF_SEL_SC6_PA0_FIFO_FULL', 'PH_PERF_SEL_SC6_PA0_FPOV_WE',
'PH_PERF_SEL_SC6_PA0_LPOV_WE', 'PH_PERF_SEL_SC6_PA0_NULL_WE',
'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC6_PA1_EOPG_WE', 'PH_PERF_SEL_SC6_PA1_EOP_WE',
'PH_PERF_SEL_SC6_PA1_EVENT_WE', 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY',
'PH_PERF_SEL_SC6_PA1_FIFO_FULL', 'PH_PERF_SEL_SC6_PA1_FPOV_WE',
'PH_PERF_SEL_SC6_PA1_LPOV_WE', 'PH_PERF_SEL_SC6_PA1_NULL_WE',
'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC6_PA2_EOPG_WE', 'PH_PERF_SEL_SC6_PA2_EOP_WE',
'PH_PERF_SEL_SC6_PA2_EVENT_WE', 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY',
'PH_PERF_SEL_SC6_PA2_FIFO_FULL', 'PH_PERF_SEL_SC6_PA2_FPOV_WE',
'PH_PERF_SEL_SC6_PA2_LPOV_WE', 'PH_PERF_SEL_SC6_PA2_NULL_WE',
'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC6_PA3_EOPG_WE', 'PH_PERF_SEL_SC6_PA3_EOP_WE',
'PH_PERF_SEL_SC6_PA3_EVENT_WE', 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY',
'PH_PERF_SEL_SC6_PA3_FIFO_FULL', 'PH_PERF_SEL_SC6_PA3_FPOV_WE',
'PH_PERF_SEL_SC6_PA3_LPOV_WE', 'PH_PERF_SEL_SC6_PA3_NULL_WE',
'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC6_PA4_EOPG_WE', 'PH_PERF_SEL_SC6_PA4_EOP_WE',
'PH_PERF_SEL_SC6_PA4_EVENT_WE', 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY',
'PH_PERF_SEL_SC6_PA4_FIFO_FULL', 'PH_PERF_SEL_SC6_PA4_FPOV_WE',
'PH_PERF_SEL_SC6_PA4_LPOV_WE', 'PH_PERF_SEL_SC6_PA4_NULL_WE',
'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC6_PA5_EOPG_WE', 'PH_PERF_SEL_SC6_PA5_EOP_WE',
'PH_PERF_SEL_SC6_PA5_EVENT_WE', 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY',
'PH_PERF_SEL_SC6_PA5_FIFO_FULL', 'PH_PERF_SEL_SC6_PA5_FPOV_WE',
'PH_PERF_SEL_SC6_PA5_LPOV_WE', 'PH_PERF_SEL_SC6_PA5_NULL_WE',
'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC6_PA6_EOPG_WE', 'PH_PERF_SEL_SC6_PA6_EOP_WE',
'PH_PERF_SEL_SC6_PA6_EVENT_WE', 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY',
'PH_PERF_SEL_SC6_PA6_FIFO_FULL', 'PH_PERF_SEL_SC6_PA6_FPOV_WE',
'PH_PERF_SEL_SC6_PA6_LPOV_WE', 'PH_PERF_SEL_SC6_PA6_NULL_WE',
'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC6_PA7_EOPG_WE', 'PH_PERF_SEL_SC6_PA7_EOP_WE',
'PH_PERF_SEL_SC6_PA7_EVENT_WE', 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY',
'PH_PERF_SEL_SC6_PA7_FIFO_FULL', 'PH_PERF_SEL_SC6_PA7_FPOV_WE',
'PH_PERF_SEL_SC6_PA7_LPOV_WE', 'PH_PERF_SEL_SC6_PA7_NULL_WE',
'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC6_SEND', 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID',
'PH_PERF_SEL_SC7_ARB_BUSY',
'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP',
'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP',
'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP',
'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW',
'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE',
'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL',
'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY',
'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES',
'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO',
'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM',
'PH_PERF_SEL_SC7_CREDIT_AT_MAX',
'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND',
'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW',
'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION',
'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION',
'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION',
'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC7_PA0_EOPG_WE', 'PH_PERF_SEL_SC7_PA0_EOP_WE',
'PH_PERF_SEL_SC7_PA0_EVENT_WE', 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY',
'PH_PERF_SEL_SC7_PA0_FIFO_FULL', 'PH_PERF_SEL_SC7_PA0_FPOV_WE',
'PH_PERF_SEL_SC7_PA0_LPOV_WE', 'PH_PERF_SEL_SC7_PA0_NULL_WE',
'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC7_PA1_EOPG_WE', 'PH_PERF_SEL_SC7_PA1_EOP_WE',
'PH_PERF_SEL_SC7_PA1_EVENT_WE', 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY',
'PH_PERF_SEL_SC7_PA1_FIFO_FULL', 'PH_PERF_SEL_SC7_PA1_FPOV_WE',
'PH_PERF_SEL_SC7_PA1_LPOV_WE', 'PH_PERF_SEL_SC7_PA1_NULL_WE',
'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC7_PA2_EOPG_WE', 'PH_PERF_SEL_SC7_PA2_EOP_WE',
'PH_PERF_SEL_SC7_PA2_EVENT_WE', 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY',
'PH_PERF_SEL_SC7_PA2_FIFO_FULL', 'PH_PERF_SEL_SC7_PA2_FPOV_WE',
'PH_PERF_SEL_SC7_PA2_LPOV_WE', 'PH_PERF_SEL_SC7_PA2_NULL_WE',
'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC7_PA3_EOPG_WE', 'PH_PERF_SEL_SC7_PA3_EOP_WE',
'PH_PERF_SEL_SC7_PA3_EVENT_WE', 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY',
'PH_PERF_SEL_SC7_PA3_FIFO_FULL', 'PH_PERF_SEL_SC7_PA3_FPOV_WE',
'PH_PERF_SEL_SC7_PA3_LPOV_WE', 'PH_PERF_SEL_SC7_PA3_NULL_WE',
'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC7_PA4_EOPG_WE', 'PH_PERF_SEL_SC7_PA4_EOP_WE',
'PH_PERF_SEL_SC7_PA4_EVENT_WE', 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY',
'PH_PERF_SEL_SC7_PA4_FIFO_FULL', 'PH_PERF_SEL_SC7_PA4_FPOV_WE',
'PH_PERF_SEL_SC7_PA4_LPOV_WE', 'PH_PERF_SEL_SC7_PA4_NULL_WE',
'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC7_PA5_EOPG_WE', 'PH_PERF_SEL_SC7_PA5_EOP_WE',
'PH_PERF_SEL_SC7_PA5_EVENT_WE', 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY',
'PH_PERF_SEL_SC7_PA5_FIFO_FULL', 'PH_PERF_SEL_SC7_PA5_FPOV_WE',
'PH_PERF_SEL_SC7_PA5_LPOV_WE', 'PH_PERF_SEL_SC7_PA5_NULL_WE',
'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC7_PA6_EOPG_WE', 'PH_PERF_SEL_SC7_PA6_EOP_WE',
'PH_PERF_SEL_SC7_PA6_EVENT_WE', 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY',
'PH_PERF_SEL_SC7_PA6_FIFO_FULL', 'PH_PERF_SEL_SC7_PA6_FPOV_WE',
'PH_PERF_SEL_SC7_PA6_LPOV_WE', 'PH_PERF_SEL_SC7_PA6_NULL_WE',
'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD',
'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD',
'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE',
'PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD',
'PH_PERF_SEL_SC7_PA7_EOPG_WE', 'PH_PERF_SEL_SC7_PA7_EOP_WE',
'PH_PERF_SEL_SC7_PA7_EVENT_WE', 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY',
'PH_PERF_SEL_SC7_PA7_FIFO_FULL', 'PH_PERF_SEL_SC7_PA7_FPOV_WE',
'PH_PERF_SEL_SC7_PA7_LPOV_WE', 'PH_PERF_SEL_SC7_PA7_NULL_WE',
'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE',
'PH_PERF_SEL_SC7_SEND', 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID',
'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT',
'PH_SPI_MODE_DISABLED', 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT',
'PIPELINESTAT_START', 'PIPELINESTAT_STOP', 'PIPE_ALIGNED',
'PIPE_ALIGNED_SURF', 'PIPE_COMPAT_LEVEL', 'PIPE_ID0', 'PIPE_ID1',
'PIPE_ID2', 'PIPE_ID3', 'PIPE_INT_MASK_MODE',
'PIPE_INT_MASK_MODE_DISABLE', 'PIPE_INT_MASK_MODE_ENABLE',
'PIPE_INT_TYPE_MODE', 'PIPE_INT_TYPE_MODE_DISABLE',
'PIPE_INT_TYPE_MODE_ENABLE', 'PIPE_IN_FLUSH_URGENT',
'PIPE_IN_FLUSH_URGENT_DISABLE', 'PIPE_IN_FLUSH_URGENT_ENABLE',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC',
'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD',
'PIPE_PIXEL_RATE_PLL_SOURCE',
'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL',
'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE',
'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL',
'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIPE_UNALIGNED_SURF',
'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1',
'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF',
'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE', 'PIXEL_PIPE_OCCLUSION_COUNT_0',
'PIXEL_PIPE_OCCLUSION_COUNT_1', 'PIXEL_PIPE_OCCLUSION_COUNT_2',
'PIXEL_PIPE_OCCLUSION_COUNT_3', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0',
'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1',
'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0',
'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL',
'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET',
'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS',
'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS',
'PIX_DYNAMIC_EXPANSION', 'PIX_EXPAND_MODE', 'PIX_ZERO_EXPANSION',
'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE',
'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM4_MEC_RELEASE_MEM_DEFINED',
'PM4_MEC_WRITE_DATA_DEFINED', 'PM4_MES_HEADER_DEFINED',
'PM_ASSERT_RESET', 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1',
'POINTLIST', 'POWER_STATE_ENUM', 'POWER_STATE_ENUM_DS',
'POWER_STATE_ENUM_LS', 'POWER_STATE_ENUM_ON',
'POWER_STATE_ENUM_SD', 'PRE_CSC_BYPASS', 'PRE_CSC_MODE_ENUM',
'PRE_CSC_SET_A', 'PRE_CSC_SET_B', 'PRE_DEGAM_BT2020',
'PRE_DEGAM_BT2100HLG', 'PRE_DEGAM_BT2100PQ', 'PRE_DEGAM_BYPASS',
'PRE_DEGAM_ENABLE', 'PRE_DEGAM_GAMMA_22', 'PRE_DEGAM_GAMMA_24',
'PRE_DEGAM_GAMMA_26', 'PRE_DEGAM_MODE', 'PRE_DEGAM_SELECT',
'PRE_DEGAM_SRGB', 'PROG_SEQ', 'PROTVIOL', 'PRQ_MRQ_FLUSH_URGENT',
'PRQ_MRQ_FLUSH_URGENT_DISABLE', 'PRQ_MRQ_FLUSH_URGENT_ENABLE',
'PS', 'PSLC_ASAP', 'PSLC_AUTO', 'PSLC_COUNTDOWN',
'PSLC_ON_HANG_ONLY', 'PS_DONE', 'PS_PARTIAL_FLUSH',
'PTE_BUFFER_MODE', 'PTE_BUFFER_MODE_0', 'PTE_BUFFER_MODE_1',
'PTE_ROW_HEIGHT_LINEAR', 'PTE_ROW_HEIGHT_LINEAR_1024L',
'PTE_ROW_HEIGHT_LINEAR_128L', 'PTE_ROW_HEIGHT_LINEAR_16L',
'PTE_ROW_HEIGHT_LINEAR_256L', 'PTE_ROW_HEIGHT_LINEAR_32L',
'PTE_ROW_HEIGHT_LINEAR_512L', 'PTE_ROW_HEIGHT_LINEAR_64L',
'PTE_ROW_HEIGHT_LINEAR_8L',
'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE',
'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN',
'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT',
'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN',
'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN',
'PWRSEQ_BL_PWM_DISABLE', 'PWRSEQ_BL_PWM_ENABLE',
'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE',
'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE',
'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE',
'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN',
'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE',
'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN',
'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM',
'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM',
'PWRSEQ_BL_PWM_GRP1_REG_LOCK',
'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE',
'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE',
'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START',
'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE',
'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE',
'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE',
'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE',
'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL',
'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM',
'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1',
'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2',
'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3',
'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL',
'PWRSEQ_GPIO_MASK_EN', 'PWRSEQ_GPIO_MASK_EN_HARDWARE',
'PWRSEQ_GPIO_MASK_EN_SOFTWARE', 'PWRSEQ_PANEL_BLON_OFF',
'PWRSEQ_PANEL_BLON_ON', 'PWRSEQ_PANEL_BLON_POL_INVERT',
'PWRSEQ_PANEL_BLON_POL_NON_INVERT', 'PWRSEQ_PANEL_DIGON_OFF',
'PWRSEQ_PANEL_DIGON_ON', 'PWRSEQ_PANEL_DIGON_POL_INVERT',
'PWRSEQ_PANEL_DIGON_POL_NON_INVERT',
'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON',
'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL',
'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON',
'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL',
'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL',
'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE',
'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN',
'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF',
'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON',
'PWRSEQ_PANEL_SYNCEN_POL_INVERT',
'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT',
'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON',
'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', 'PerfCounter_Vals',
'PhSPIstatusMode', 'PixelPipeCounterId', 'PixelPipeStride',
'PkrMap', 'PkrXsel', 'PkrXsel2', 'PkrYsel', 'RAMA', 'RAMA_ACCESS',
'RAMB', 'RAMB_ACCESS', 'RAM_LUT', 'RANGE_00', 'RANGE_FF',
'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1',
'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3',
'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1',
'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3',
'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1',
'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3',
'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1',
'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3',
'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1',
'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3',
'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1',
'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3',
'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1',
'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1',
'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1',
'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3',
'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE',
'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE',
'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE',
'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE',
'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE',
'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE',
'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE',
'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0',
'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2',
'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0',
'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2',
'RASTER_CONFIG_SE_PAIR_MAP_3',
'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE',
'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE',
'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE',
'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE',
'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE',
'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE',
'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE',
'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE',
'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE',
'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW',
'RDPCSPIPE_APBCLK_DISABLE', 'RDPCSPIPE_APBCLK_ENABLE',
'RDPCSPIPE_APB_PSLVERR_MASK_DISABLE',
'RDPCSPIPE_APB_PSLVERR_MASK_ENABLE',
'RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN',
'RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN',
'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON',
'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN',
'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS',
'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON',
'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON',
'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN',
'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS',
'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS',
'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN',
'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN',
'RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET',
'RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET',
'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK',
'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE',
'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE',
'RDPCSPIPE_DBG_OCLA_SEL', 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8',
'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16',
'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24',
'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32',
'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40',
'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48',
'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56',
'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0',
'RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE',
'RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE',
'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE',
'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE',
'RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE',
'RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE',
'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE',
'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE',
'RDPCSPIPE_ENC_TYPE', 'RDPCSPIPE_EXT_PCLK_EN_DISABLE',
'RDPCSPIPE_EXT_PCLK_EN_ENABLE', 'RDPCSPIPE_FIFO_EMPTY',
'RDPCSPIPE_FIFO_FULL', 'RDPCSPIPE_FIFO_IS_EMPTY',
'RDPCSPIPE_FIFO_IS_FULL', 'RDPCSPIPE_FIFO_NOT_EMPTY',
'RDPCSPIPE_FIFO_NOT_FULL',
'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK',
'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE',
'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK',
'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE',
'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK',
'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK',
'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK',
'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE',
'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE',
'RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE',
'RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE',
'RDPCSPIPE_MEM_PWR_DEEP_SLEEP', 'RDPCSPIPE_MEM_PWR_LIGHT_SLEEP',
'RDPCSPIPE_MEM_PWR_NO_FORCE',
'RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP',
'RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP',
'RDPCSPIPE_MEM_PWR_PWR_STATE_ON',
'RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN',
'RDPCSPIPE_MEM_PWR_SHUT_DOWN',
'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK',
'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE',
'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE',
'RDPCSPIPE_PACK_MODE', 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL',
'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL',
'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE',
'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE',
'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE',
'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV',
'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV',
'RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV',
'RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL',
'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT',
'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE',
'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH',
'RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE',
'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC',
'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB',
'RDPCSPIPE_PHY_CR_PARA_SEL_CR', 'RDPCSPIPE_PHY_CR_PARA_SEL_JTAG',
'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV',
'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10',
'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2',
'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3',
'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4',
'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5',
'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6',
'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8',
'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1',
'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16',
'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2',
'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3',
'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8',
'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT',
'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT',
'RDPCSPIPE_PHY_DP_TX_RATE', 'RDPCSPIPE_PHY_DP_TX_RATE_DIV2',
'RDPCSPIPE_PHY_DP_TX_RATE_DIV4',
'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40',
'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42',
'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44',
'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46',
'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48',
'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50',
'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52',
'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54',
'RDPCSPIPE_PHY_DP_TX_WIDTH_10', 'RDPCSPIPE_PHY_DP_TX_WIDTH_16',
'RDPCSPIPE_PHY_DP_TX_WIDTH_20', 'RDPCSPIPE_PHY_DP_TX_WIDTH_8',
'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0',
'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1',
'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2',
'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3',
'RDPCSPIPE_PHY_IF_WIDTH', 'RDPCSPIPE_PHY_RATE',
'RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE',
'RDPCSPIPE_PHY_REF_ALT_CLK_EN',
'RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE', 'RDPCSPIPE_PHY_REF_RANGE_0',
'RDPCSPIPE_PHY_REF_RANGE_1', 'RDPCSPIPE_PHY_REF_RANGE_2',
'RDPCSPIPE_PHY_REF_RANGE_3', 'RDPCSPIPE_PHY_REF_RANGE_4',
'RDPCSPIPE_PHY_REF_RANGE_5', 'RDPCSPIPE_PHY_REF_RANGE_6',
'RDPCSPIPE_PHY_REF_RANGE_7',
'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE',
'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE',
'RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE',
'RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE',
'RDPCSPIPE_SRAMCLK_DISABLE', 'RDPCSPIPE_SRAMCLK_ENABLE',
'RDPCSPIPE_SRAMCLK_GATE_DISABLE', 'RDPCSPIPE_SRAMCLK_GATE_ENABLE',
'RDPCSPIPE_SRAMCLK_NOT_PASS', 'RDPCSPIPE_SRAMCLK_PASS',
'RDPCSPIPE_SRAM_EXT_LD_DONE', 'RDPCSPIPE_SRAM_EXT_LD_NOT_DONE',
'RDPCSPIPE_SRAM_INIT_DONE', 'RDPCSPIPE_SRAM_INIT_NOT_DONE',
'RDPCSPIPE_SRAM_SRAM_RESET_DISABLE',
'RDPCSPIPE_SRAM_SRAM_RESET_ENABLE',
'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF',
'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON', 'RDPCSPIPE_TEST_CLK_SEL',
'RDPCSPIPE_TEST_CLK_SEL_CFGCLK',
'RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK',
'RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK',
'RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK',
'RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK',
'RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK',
'RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK',
'RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK',
'RDPCSPIPE_TEST_CLK_SEL_NONE',
'RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK',
'RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk',
'RDPCSPIPE_TEST_CLK_SEL_SRAMCLK',
'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS',
'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4',
'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS',
'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4',
'RDPCSPIPE_TEST_CLK_SEL_dtb_out0',
'RDPCSPIPE_TEST_CLK_SEL_dtb_out1', 'RDPCS_PIPE_CLK_CLOCK_OFF',
'RDPCS_PIPE_CLK_CLOCK_ON', 'RDPCS_PIPE_CLK_DISABLE',
'RDPCS_PIPE_CLK_ENABLE', 'RDPCS_PIPE_CLK_GATE_DISABLE',
'RDPCS_PIPE_CLK_GATE_ENABLE',
'RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB',
'RDPCS_PIPE_FIFO_DISABLE', 'RDPCS_PIPE_FIFO_ENABLE',
'RDPCS_PIPE_FIFO_LANE_DISABLE', 'RDPCS_PIPE_FIFO_LANE_ENABLE',
'RDPCS_PIPE_PHYD32CLK_CLOCK_OFF', 'RDPCS_PIPE_PHYD32CLK_CLOCK_ON',
'RDPCS_PIPE_SOFT_RESET_DISABLE', 'RDPCS_PIPE_SOFT_RESET_ENABLE',
'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE',
'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE', 'READ_SEQ',
'RECTLIST', 'RECT_2D', 'RED_LUT', 'REFER_TO_DP_SOF',
'REFER_TO_OTG_SOF', 'REG_SECURE_VIOLATE_READ',
'REG_SECURE_VIOLATE_WRITE', 'REG_UNALLOCATED_ADDR_READ',
'REG_UNALLOCATED_ADDR_WRITE', 'REG_VIRTUAL_READ',
'REG_VIRTUAL_WRITE', 'RESERVED_1', 'RESERVED_10', 'RESERVED_11',
'RESERVED_20', 'RESERVED_21', 'RESERVED_22', 'RESERVED_23',
'RESERVED_3', 'RESERVED_32', 'RESERVED_33', 'RESERVED_34',
'RESERVED_35', 'RESERVED_44', 'RESERVED_45', 'RESERVED_46',
'RESERVED_47', 'RESERVED_56', 'RESERVED_57', 'RESERVED_58',
'RESERVED_59', 'RESERVED_60', 'RESERVED_61', 'RESERVED_62',
'RESERVED_63', 'RESERVED_72', 'RESERVED_73', 'RESERVED_74',
'RESERVED_75', 'RESERVED_8', 'RESERVED_84', 'RESERVED_85',
'RESERVED_86', 'RESERVED_87', 'RESERVED_88', 'RESERVED_89',
'RESERVED_9', 'RESERVED_90', 'RESERVED_91', 'RESERVED_ES',
'RESERVED_LS', 'RESERVED_RDPOLICY', 'RESERVED_VS',
'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', 'RESPONSE_STATUS', 'RE_Z',
'RGB111110_FIX', 'RGB111110_FLOAT', 'RGB565', 'RGBA1010102',
'RGBA16161616_10LSB', 'RGBA16161616_10MSB', 'RGBA16161616_12LSB',
'RGBA16161616_12MSB', 'RGBA16161616_FLOAT', 'RGBA16161616_SNORM',
'RGBA16161616_UNORM', 'RGBA4444', 'RGBA5551', 'RGBA8888', 'RGBE',
'RINGID0', 'RINGID1', 'RINGID2', 'RINGID3',
'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL',
'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED',
'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED',
'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL',
'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED',
'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED',
'RLC_DOORBELL_MODE', 'RLC_DOORBELL_MODE_DISABLE',
'RLC_DOORBELL_MODE_ENABLE', 'RLC_DOORBELL_MODE_ENABLE_PF',
'RLC_DOORBELL_MODE_ENABLE_PF_VF', 'RLC_PERFCOUNTER_SEL',
'RLC_PERFMON_STATE', 'RLC_PERFMON_STATE_DISABLE',
'RLC_PERFMON_STATE_ENABLE', 'RLC_PERFMON_STATE_RESERVED_3',
'RLC_PERFMON_STATE_RESERVED_4', 'RLC_PERFMON_STATE_RESERVED_5',
'RLC_PERFMON_STATE_RESERVED_6', 'RLC_PERFMON_STATE_RESET',
'RLC_PERFMON_STATE_ROLLOVER', 'RLC_PERF_SEL_CP_INTERRUPT',
'RLC_PERF_SEL_GRBM_INTERRUPT', 'RLC_PERF_SEL_IH_INTERRUPT',
'RLC_PERF_SEL_POWER_FEATURE_0', 'RLC_PERF_SEL_POWER_FEATURE_1',
'RLC_PERF_SEL_SERDES_COMMAND_WRITE', 'RLC_PERF_SEL_SPM_INTERRUPT',
'RMIPerfSel', 'RMI_CID', 'RMI_CID_CC', 'RMI_CID_CM', 'RMI_CID_DC',
'RMI_CID_FC', 'RMI_CID_S', 'RMI_CID_TILE', 'RMI_CID_Z',
'RMI_CID_ZPCPSD', 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID',
'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', 'ROM_SIGNATURE',
'ROTATE_0_DEGREES', 'ROTATE_180_DEGREES', 'ROTATE_270_DEGREES',
'ROTATE_90_DEGREES', 'ROTATION_ANGLE', 'ROW_TTU_MODE',
'RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK',
'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD',
'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF',
'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN',
'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP', 'RSPM_CMD',
'RSPM_CMD_CALIBRATE', 'RSPM_CMD_FORCE_SAMPLE', 'RSPM_CMD_IDLE',
'RSPM_CMD_INVALID', 'RSPM_CMD_PERF_RESET', 'RSPM_CMD_PERF_SAMPLE',
'RSPM_CMD_PROF_START', 'RSPM_CMD_PROF_STOP', 'RSPM_CMD_SPM_RESET',
'RSPM_CMD_SPM_START', 'RSPM_CMD_SPM_STOP', 'RST_PIX_CNT',
'RSV_TAG_RAM', 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel',
'ReadPolicy', 'Reserved_0x00', 'Reserved_0x09',
'RingCounterControl', 'SAMPLE_PIPELINESTAT',
'SAMPLE_STREAMOUTSTATS', 'SAMPLE_STREAMOUTSTATS1',
'SAMPLE_STREAMOUTSTATS2', 'SAMPLE_STREAMOUTSTATS3',
'SCL_2TAP_HARDCODE', 'SCL_ALPHA_COEF', 'SCL_ALPHA_COEF_FIRST',
'SCL_ALPHA_COEF_SECOND', 'SCL_AUTOCAL_MODE', 'SCL_BOUNDARY',
'SCL_BOUNDARY_BLACK', 'SCL_BOUNDARY_EDGE', 'SCL_CHROMA_COEF',
'SCL_CHROMA_COEF_FIRST', 'SCL_CHROMA_COEF_SECOND',
'SCL_COEF_2TAP_HARDCODE_OFF', 'SCL_COEF_2TAP_HARDCODE_ON',
'SCL_COEF_CHROMA_HORZ_FILTER', 'SCL_COEF_CHROMA_VERT_FILTER',
'SCL_COEF_FILTER_TYPE_SEL', 'SCL_COEF_LUMA_HORZ_FILTER',
'SCL_COEF_LUMA_VERT_FILTER', 'SCL_COEF_RAM_SEL',
'SCL_COEF_RAM_SEL_0', 'SCL_COEF_RAM_SEL_1', 'SCL_SHARP_DISABLE',
'SCL_SHARP_EN', 'SCL_SHARP_ENABLE', 'SC_BACKEND_BUSY',
'SC_BACKEND_PRIM_FIFO_FULL', 'SC_BB_DISCARD',
'SC_BCI_CREDIT_AT_MAX', 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND',
'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_BCI_SEND',
'SC_BM_BE0_STALLED', 'SC_BM_BE1_STALLED', 'SC_BM_BE2_STALLED',
'SC_BM_BE3_STALLED', 'SC_BM_BUSY',
'SC_BM_MULTI_ACCUM_1_BE_STALLED',
'SC_BM_MULTI_ACCUM_2_BE_STALLED',
'SC_BM_MULTI_ACCUM_3_BE_STALLED',
'SC_BM_MULTI_ACCUM_4_BE_STALLED', 'SC_BUSY_CNT_NOT_ZERO',
'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', 'SC_DB0_QUAD_INTF_BUSY',
'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', 'SC_DB0_QUAD_INTF_IDLE',
'SC_DB0_QUAD_INTF_SEND', 'SC_DB0_QUAD_INTF_STALLED_BY_DB',
'SC_DB0_TILE_INTERFACE_BUSY',
'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX',
'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND',
'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'SC_DB0_TILE_INTERFACE_SEND', 'SC_DB0_TILE_INTERFACE_SEND_EVENT',
'SC_DB0_TILE_INTERFACE_SEND_SOP',
'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT',
'SC_DB0_TILE_MASK_FIFO_FULL',
'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL',
'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL',
'SC_DB1_QUAD_INTF_BUSY', 'SC_DB1_QUAD_INTF_CREDIT_AT_MAX',
'SC_DB1_QUAD_INTF_IDLE', 'SC_DB1_QUAD_INTF_SEND',
'SC_DB1_QUAD_INTF_STALLED_BY_DB', 'SC_DB1_TILE_INTERFACE_BUSY',
'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX',
'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND',
'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND',
'SC_DB1_TILE_INTERFACE_SEND', 'SC_DB1_TILE_INTERFACE_SEND_EVENT',
'SC_DB1_TILE_INTERFACE_SEND_SOP',
'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT',
'SC_DB1_TILE_MASK_FIFO_FULL',
'SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL',
'SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL',
'SC_EARLYZ_QUAD_COUNT', 'SC_EARLYZ_QUAD_WITH_1_PIX',
'SC_EARLYZ_QUAD_WITH_2_PIX', 'SC_EARLYZ_QUAD_WITH_3_PIX',
'SC_EARLYZ_QUAD_WITH_4_PIX', 'SC_EOP_SYNC_WINDOW',
'SC_FSR_WALKED', 'SC_FULL_FULL_QUAD', 'SC_FULL_HALF_QUAD',
'SC_FULL_QTR_QUAD', 'SC_GRP0_DYN_SCLK_BUSY',
'SC_GRP1_DYN_SCLK_BUSY', 'SC_GRP2_DYN_SCLK_BUSY',
'SC_GRP3_DYN_SCLK_BUSY', 'SC_GRP4_DYN_SCLK_BUSY',
'SC_GRP5_DYN_SCLK_BUSY', 'SC_GRP6_DYN_SCLK_BUSY',
'SC_GRP7_DYN_SCLK_BUSY', 'SC_GRP8_DYN_SCLK_BUSY',
'SC_GRP9_DYN_SCLK_BUSY', 'SC_HALF_FULL_QUAD', 'SC_HALF_HALF_QUAD',
'SC_HALF_LSB', 'SC_HALF_QTR_QUAD', 'SC_LSB_ONE_SIDED',
'SC_LSB_TWO_SIDED', 'SC_MULTICYCLE_BUBBLE_FREEZE',
'SC_P0_DETAIL_QUAD_COUNT', 'SC_P0_DETAIL_QUAD_WITH_1_PIX',
'SC_P0_DETAIL_QUAD_WITH_2_PIX', 'SC_P0_DETAIL_QUAD_WITH_3_PIX',
'SC_P0_DETAIL_QUAD_WITH_4_PIX', 'SC_P0_HIZ_QUAD_COUNT',
'SC_P0_HIZ_QUAD_PER_TILE_H0', 'SC_P0_HIZ_QUAD_PER_TILE_H1',
'SC_P0_HIZ_QUAD_PER_TILE_H10', 'SC_P0_HIZ_QUAD_PER_TILE_H11',
'SC_P0_HIZ_QUAD_PER_TILE_H12', 'SC_P0_HIZ_QUAD_PER_TILE_H13',
'SC_P0_HIZ_QUAD_PER_TILE_H14', 'SC_P0_HIZ_QUAD_PER_TILE_H15',
'SC_P0_HIZ_QUAD_PER_TILE_H16', 'SC_P0_HIZ_QUAD_PER_TILE_H2',
'SC_P0_HIZ_QUAD_PER_TILE_H3', 'SC_P0_HIZ_QUAD_PER_TILE_H4',
'SC_P0_HIZ_QUAD_PER_TILE_H5', 'SC_P0_HIZ_QUAD_PER_TILE_H6',
'SC_P0_HIZ_QUAD_PER_TILE_H7', 'SC_P0_HIZ_QUAD_PER_TILE_H8',
'SC_P0_HIZ_QUAD_PER_TILE_H9', 'SC_P0_HIZ_TILE_COUNT',
'SC_P1_DETAIL_QUAD_COUNT', 'SC_P1_DETAIL_QUAD_WITH_1_PIX',
'SC_P1_DETAIL_QUAD_WITH_2_PIX', 'SC_P1_DETAIL_QUAD_WITH_3_PIX',
'SC_P1_DETAIL_QUAD_WITH_4_PIX', 'SC_P1_HIZ_QUAD_COUNT',
'SC_P1_HIZ_QUAD_PER_TILE_H0', 'SC_P1_HIZ_QUAD_PER_TILE_H1',
'SC_P1_HIZ_QUAD_PER_TILE_H10', 'SC_P1_HIZ_QUAD_PER_TILE_H11',
'SC_P1_HIZ_QUAD_PER_TILE_H12', 'SC_P1_HIZ_QUAD_PER_TILE_H13',
'SC_P1_HIZ_QUAD_PER_TILE_H14', 'SC_P1_HIZ_QUAD_PER_TILE_H15',
'SC_P1_HIZ_QUAD_PER_TILE_H16', 'SC_P1_HIZ_QUAD_PER_TILE_H2',
'SC_P1_HIZ_QUAD_PER_TILE_H3', 'SC_P1_HIZ_QUAD_PER_TILE_H4',
'SC_P1_HIZ_QUAD_PER_TILE_H5', 'SC_P1_HIZ_QUAD_PER_TILE_H6',
'SC_P1_HIZ_QUAD_PER_TILE_H7', 'SC_P1_HIZ_QUAD_PER_TILE_H8',
'SC_P1_HIZ_QUAD_PER_TILE_H9', 'SC_P1_HIZ_TILE_COUNT',
'SC_P2_DETAIL_QUAD_COUNT', 'SC_P2_DETAIL_QUAD_WITH_1_PIX',
'SC_P2_DETAIL_QUAD_WITH_2_PIX', 'SC_P2_DETAIL_QUAD_WITH_3_PIX',
'SC_P2_DETAIL_QUAD_WITH_4_PIX', 'SC_P2_HIZ_QUAD_COUNT',
'SC_P2_HIZ_QUAD_PER_TILE_H0', 'SC_P2_HIZ_QUAD_PER_TILE_H1',
'SC_P2_HIZ_QUAD_PER_TILE_H10', 'SC_P2_HIZ_QUAD_PER_TILE_H11',
'SC_P2_HIZ_QUAD_PER_TILE_H12', 'SC_P2_HIZ_QUAD_PER_TILE_H13',
'SC_P2_HIZ_QUAD_PER_TILE_H14', 'SC_P2_HIZ_QUAD_PER_TILE_H15',
'SC_P2_HIZ_QUAD_PER_TILE_H16', 'SC_P2_HIZ_QUAD_PER_TILE_H2',
'SC_P2_HIZ_QUAD_PER_TILE_H3', 'SC_P2_HIZ_QUAD_PER_TILE_H4',
'SC_P2_HIZ_QUAD_PER_TILE_H5', 'SC_P2_HIZ_QUAD_PER_TILE_H6',
'SC_P2_HIZ_QUAD_PER_TILE_H7', 'SC_P2_HIZ_QUAD_PER_TILE_H8',
'SC_P2_HIZ_QUAD_PER_TILE_H9', 'SC_P2_HIZ_TILE_COUNT',
'SC_P3_DETAIL_QUAD_COUNT', 'SC_P3_DETAIL_QUAD_WITH_1_PIX',
'SC_P3_DETAIL_QUAD_WITH_2_PIX', 'SC_P3_DETAIL_QUAD_WITH_3_PIX',
'SC_P3_DETAIL_QUAD_WITH_4_PIX', 'SC_P3_HIZ_QUAD_COUNT',
'SC_P3_HIZ_QUAD_PER_TILE_H0', 'SC_P3_HIZ_QUAD_PER_TILE_H1',
'SC_P3_HIZ_QUAD_PER_TILE_H10', 'SC_P3_HIZ_QUAD_PER_TILE_H11',
'SC_P3_HIZ_QUAD_PER_TILE_H12', 'SC_P3_HIZ_QUAD_PER_TILE_H13',
'SC_P3_HIZ_QUAD_PER_TILE_H14', 'SC_P3_HIZ_QUAD_PER_TILE_H15',
'SC_P3_HIZ_QUAD_PER_TILE_H16', 'SC_P3_HIZ_QUAD_PER_TILE_H2',
'SC_P3_HIZ_QUAD_PER_TILE_H3', 'SC_P3_HIZ_QUAD_PER_TILE_H4',
'SC_P3_HIZ_QUAD_PER_TILE_H5', 'SC_P3_HIZ_QUAD_PER_TILE_H6',
'SC_P3_HIZ_QUAD_PER_TILE_H7', 'SC_P3_HIZ_QUAD_PER_TILE_H8',
'SC_P3_HIZ_QUAD_PER_TILE_H9', 'SC_P3_HIZ_TILE_COUNT',
'SC_PA0_SC_DATA_FIFO_EOPG_RD', 'SC_PA0_SC_DATA_FIFO_EOP_RD',
'SC_PA0_SC_DATA_FIFO_RD', 'SC_PA0_SC_DATA_FIFO_WE',
'SC_PA0_SC_DEALLOC_0_RD', 'SC_PA0_SC_DEALLOC_1_RD',
'SC_PA0_SC_EOPG_WE', 'SC_PA0_SC_EOP_WE', 'SC_PA0_SC_EVENT_WE',
'SC_PA0_SC_FPOV_WE', 'SC_PA0_SC_LPOV_WE',
'SC_PA0_SC_NULL_DEALLOC_WE', 'SC_PA0_SC_NULL_WE',
'SC_PA1_SC_DATA_FIFO_EOPG_RD', 'SC_PA1_SC_DATA_FIFO_EOP_RD',
'SC_PA1_SC_DATA_FIFO_RD', 'SC_PA1_SC_DATA_FIFO_WE',
'SC_PA1_SC_DEALLOC_0_RD', 'SC_PA1_SC_DEALLOC_1_RD',
'SC_PA1_SC_EOPG_WE', 'SC_PA1_SC_EOP_WE', 'SC_PA1_SC_EVENT_WE',
'SC_PA1_SC_FPOV_WE', 'SC_PA1_SC_LPOV_WE',
'SC_PA1_SC_NULL_DEALLOC_WE', 'SC_PA1_SC_NULL_WE',
'SC_PA2_SC_DATA_FIFO_EOPG_RD', 'SC_PA2_SC_DATA_FIFO_EOP_RD',
'SC_PA2_SC_DATA_FIFO_RD', 'SC_PA2_SC_DATA_FIFO_WE',
'SC_PA2_SC_DEALLOC_0_RD', 'SC_PA2_SC_DEALLOC_1_RD',
'SC_PA2_SC_EOPG_WE', 'SC_PA2_SC_EOP_WE', 'SC_PA2_SC_EVENT_WE',
'SC_PA2_SC_FPOV_WE', 'SC_PA2_SC_LPOV_WE',
'SC_PA2_SC_NULL_DEALLOC_WE', 'SC_PA2_SC_NULL_WE',
'SC_PA3_SC_DATA_FIFO_EOPG_RD', 'SC_PA3_SC_DATA_FIFO_EOP_RD',
'SC_PA3_SC_DATA_FIFO_RD', 'SC_PA3_SC_DATA_FIFO_WE',
'SC_PA3_SC_DEALLOC_0_RD', 'SC_PA3_SC_DEALLOC_1_RD',
'SC_PA3_SC_EOPG_WE', 'SC_PA3_SC_EOP_WE', 'SC_PA3_SC_EVENT_WE',
'SC_PA3_SC_FPOV_WE', 'SC_PA3_SC_LPOV_WE',
'SC_PA3_SC_NULL_DEALLOC_WE', 'SC_PA3_SC_NULL_WE',
'SC_PA_SC_DEALLOC_0_0_WE', 'SC_PA_SC_DEALLOC_0_1_WE',
'SC_PA_SC_DEALLOC_1_0_WE', 'SC_PA_SC_DEALLOC_1_1_WE',
'SC_PA_SC_DEALLOC_2_0_WE', 'SC_PA_SC_DEALLOC_2_1_WE',
'SC_PA_SC_DEALLOC_3_0_WE', 'SC_PA_SC_DEALLOC_3_1_WE',
'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL',
'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE',
'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE',
'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH',
'SC_PBB_BATCH_BREAK_DUE_TO_EVENT',
'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT',
'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE',
'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE',
'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH',
'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT',
'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT',
'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV',
'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT',
'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE',
'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE',
'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT',
'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE',
'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET',
'SC_PBB_BATCH_BREAK_DUE_TO_PRIM',
'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER',
'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW',
'SC_PBB_BATCH_HIST_NUM_CONTEXTS',
'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES',
'SC_PBB_BATCH_HIST_NUM_PRIMS',
'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS',
'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM',
'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS',
'SC_PBB_BIN_HIST_NUM_CONTEXTS',
'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES',
'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY',
'SC_PBB_BUSY_AND_NO_SENDS',
'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', 'SC_PBB_END_OF_BATCH',
'SC_PBB_END_OF_BIN',
'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN',
'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW',
'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION',
'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS',
'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH',
'SC_PBB_RESERVED', 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES',
'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB',
'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL',
'SC_PKR_4X2_FILL_QUAD', 'SC_PKR_4X2_QUAD_SPLIT',
'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV',
'SC_PKR_END_OF_VECTOR', 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE',
'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP',
'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX',
'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2',
'SC_PKR_WAVE_BREAK_FULL_TILE', 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION',
'SC_PK_BUSY', 'SC_PK_DEALLOC_WAVE_BREAK',
'SC_PK_MAX_DEALLOC_FORCE_EOV', 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H',
'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H',
'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H',
'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H',
'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H',
'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H',
'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H',
'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H',
'SC_PK_PM_FULL_TILE_WAVE_BRK_1H',
'SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H',
'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H',
'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H',
'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H',
'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H',
'SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H',
'SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H',
'SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H',
'SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H',
'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H',
'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD',
'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD',
'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD',
'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD',
'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD',
'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD',
'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD',
'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD',
'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD',
'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD',
'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD',
'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD',
'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD',
'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD',
'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD',
'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD',
'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H',
'SC_POPS_FORCE_EOV', 'SC_POPS_INTRA_WAVE_OVERLAPS',
'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY',
'SC_PS_ARB_EOP_POP_SYNC_POP', 'SC_PS_ARB_EVENT_SYNC_POP',
'SC_PS_ARB_NULL_PRIM_BUBBLE_POP',
'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH',
'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO',
'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY',
'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE',
'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES',
'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM',
'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP',
'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_ENG_MULTICYCLE_BUBBLE',
'SC_PS_PA0_SC_FIFO_EMPTY', 'SC_PS_PA0_SC_FIFO_FULL',
'SC_PS_PA1_SC_FIFO_EMPTY', 'SC_PS_PA1_SC_FIFO_FULL',
'SC_PS_PA2_SC_FIFO_EMPTY', 'SC_PS_PA2_SC_FIFO_FULL',
'SC_PS_PA3_SC_FIFO_EMPTY', 'SC_PS_PA3_SC_FIFO_FULL',
'SC_PS_PM_PBB_TO_PSE_FIFO_FULL',
'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL',
'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL',
'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL',
'SC_PS_PM_PFF_PW_FULL', 'SC_PS_PM_ZFF_PW_FULL',
'SC_PS_TO_BE_SCLK_GATE_STALL', 'SC_PS_TS_EVENT_FIFO_POP',
'SC_PS_TS_EVENT_FIFO_PUSH', 'SC_PW_BM_PASS_EMPTY_PRIM',
'SC_QTR_FULL_QUAD', 'SC_QTR_HALF_QUAD', 'SC_QTR_QTR_QUAD',
'SC_QZ0_QUAD_COUNT', 'SC_QZ0_QUAD_PER_TILE_H0',
'SC_QZ0_QUAD_PER_TILE_H1', 'SC_QZ0_QUAD_PER_TILE_H10',
'SC_QZ0_QUAD_PER_TILE_H11', 'SC_QZ0_QUAD_PER_TILE_H12',
'SC_QZ0_QUAD_PER_TILE_H13', 'SC_QZ0_QUAD_PER_TILE_H14',
'SC_QZ0_QUAD_PER_TILE_H15', 'SC_QZ0_QUAD_PER_TILE_H16',
'SC_QZ0_QUAD_PER_TILE_H2', 'SC_QZ0_QUAD_PER_TILE_H3',
'SC_QZ0_QUAD_PER_TILE_H4', 'SC_QZ0_QUAD_PER_TILE_H5',
'SC_QZ0_QUAD_PER_TILE_H6', 'SC_QZ0_QUAD_PER_TILE_H7',
'SC_QZ0_QUAD_PER_TILE_H8', 'SC_QZ0_QUAD_PER_TILE_H9',
'SC_QZ0_TILE_COUNT', 'SC_QZ0_TILE_COVERED_COUNT',
'SC_QZ0_TILE_NOT_COVERED_COUNT', 'SC_QZ1_QUAD_COUNT',
'SC_QZ1_QUAD_PER_TILE_H0', 'SC_QZ1_QUAD_PER_TILE_H1',
'SC_QZ1_QUAD_PER_TILE_H10', 'SC_QZ1_QUAD_PER_TILE_H11',
'SC_QZ1_QUAD_PER_TILE_H12', 'SC_QZ1_QUAD_PER_TILE_H13',
'SC_QZ1_QUAD_PER_TILE_H14', 'SC_QZ1_QUAD_PER_TILE_H15',
'SC_QZ1_QUAD_PER_TILE_H16', 'SC_QZ1_QUAD_PER_TILE_H2',
'SC_QZ1_QUAD_PER_TILE_H3', 'SC_QZ1_QUAD_PER_TILE_H4',
'SC_QZ1_QUAD_PER_TILE_H5', 'SC_QZ1_QUAD_PER_TILE_H6',
'SC_QZ1_QUAD_PER_TILE_H7', 'SC_QZ1_QUAD_PER_TILE_H8',
'SC_QZ1_QUAD_PER_TILE_H9', 'SC_QZ1_TILE_COUNT',
'SC_QZ1_TILE_COVERED_COUNT', 'SC_QZ1_TILE_NOT_COVERED_COUNT',
'SC_QZ2_QUAD_COUNT', 'SC_QZ2_QUAD_PER_TILE_H0',
'SC_QZ2_QUAD_PER_TILE_H1', 'SC_QZ2_QUAD_PER_TILE_H10',
'SC_QZ2_QUAD_PER_TILE_H11', 'SC_QZ2_QUAD_PER_TILE_H12',
'SC_QZ2_QUAD_PER_TILE_H13', 'SC_QZ2_QUAD_PER_TILE_H14',
'SC_QZ2_QUAD_PER_TILE_H15', 'SC_QZ2_QUAD_PER_TILE_H16',
'SC_QZ2_QUAD_PER_TILE_H2', 'SC_QZ2_QUAD_PER_TILE_H3',
'SC_QZ2_QUAD_PER_TILE_H4', 'SC_QZ2_QUAD_PER_TILE_H5',
'SC_QZ2_QUAD_PER_TILE_H6', 'SC_QZ2_QUAD_PER_TILE_H7',
'SC_QZ2_QUAD_PER_TILE_H8', 'SC_QZ2_QUAD_PER_TILE_H9',
'SC_QZ2_TILE_COUNT', 'SC_QZ2_TILE_COVERED_COUNT',
'SC_QZ2_TILE_NOT_COVERED_COUNT', 'SC_QZ3_QUAD_COUNT',
'SC_QZ3_QUAD_PER_TILE_H0', 'SC_QZ3_QUAD_PER_TILE_H1',
'SC_QZ3_QUAD_PER_TILE_H10', 'SC_QZ3_QUAD_PER_TILE_H11',
'SC_QZ3_QUAD_PER_TILE_H12', 'SC_QZ3_QUAD_PER_TILE_H13',
'SC_QZ3_QUAD_PER_TILE_H14', 'SC_QZ3_QUAD_PER_TILE_H15',
'SC_QZ3_QUAD_PER_TILE_H16', 'SC_QZ3_QUAD_PER_TILE_H2',
'SC_QZ3_QUAD_PER_TILE_H3', 'SC_QZ3_QUAD_PER_TILE_H4',
'SC_QZ3_QUAD_PER_TILE_H5', 'SC_QZ3_QUAD_PER_TILE_H6',
'SC_QZ3_QUAD_PER_TILE_H7', 'SC_QZ3_QUAD_PER_TILE_H8',
'SC_QZ3_QUAD_PER_TILE_H9', 'SC_QZ3_TILE_COUNT',
'SC_QZ3_TILE_COVERED_COUNT', 'SC_QZ3_TILE_NOT_COVERED_COUNT',
'SC_QZQP_WINDOW_VALID', 'SC_QZQP_WINDOW_VALID_BUSY',
'SC_REG_SCLK_BUSY', 'SC_RESERVED_0', 'SC_RESERVED_1',
'SC_RESERVED_2', 'SC_RESERVED_3', 'SC_SCB_BUSY',
'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD',
'SC_SEND_DB_VPZ', 'SC_SPIBC_FULL_FREEZE', 'SC_SPI_CREDIT_AT_MAX',
'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND',
'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_SPI_DEALLOC_0_0',
'SC_SPI_DEALLOC_0_1', 'SC_SPI_DEALLOC_0_2', 'SC_SPI_DEALLOC_1_0',
'SC_SPI_DEALLOC_1_1', 'SC_SPI_DEALLOC_1_2', 'SC_SPI_DEALLOC_2_0',
'SC_SPI_DEALLOC_2_1', 'SC_SPI_DEALLOC_2_2', 'SC_SPI_DEALLOC_3_0',
'SC_SPI_DEALLOC_3_1', 'SC_SPI_DEALLOC_3_2', 'SC_SPI_EVENT',
'SC_SPI_FPOV_0', 'SC_SPI_FPOV_1', 'SC_SPI_FPOV_2',
'SC_SPI_FPOV_3', 'SC_SPI_SEND', 'SC_SRPS_WINDOW_VALID',
'SC_SRPS_WINDOW_VALID_BUSY', 'SC_STALLED_BY_BCI',
'SC_STALLED_BY_DB0_TILEFIFO', 'SC_STALLED_BY_DB1_TILEFIFO',
'SC_STALLED_BY_DB_QUAD', 'SC_STALLED_BY_DB_TILE',
'SC_STALLED_BY_PRIMFIFO', 'SC_STALLED_BY_QUADFIFO',
'SC_STALLED_BY_SPI', 'SC_STALLED_BY_TILEFIFO',
'SC_STALLED_BY_TILEORDERFIFO', 'SC_STARVED_BY_DB_QUAD',
'SC_STARVED_BY_DB_TILE', 'SC_STARVED_BY_PA',
'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL',
'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY',
'SC_SUPERTILE_COUNT',
'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8',
'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9',
'SC_SUPERTILE_PER_PRIM_H0', 'SC_SUPERTILE_PER_PRIM_H1',
'SC_SUPERTILE_PER_PRIM_H10', 'SC_SUPERTILE_PER_PRIM_H11',
'SC_SUPERTILE_PER_PRIM_H12', 'SC_SUPERTILE_PER_PRIM_H13',
'SC_SUPERTILE_PER_PRIM_H14', 'SC_SUPERTILE_PER_PRIM_H15',
'SC_SUPERTILE_PER_PRIM_H16', 'SC_SUPERTILE_PER_PRIM_H2',
'SC_SUPERTILE_PER_PRIM_H3', 'SC_SUPERTILE_PER_PRIM_H4',
'SC_SUPERTILE_PER_PRIM_H5', 'SC_SUPERTILE_PER_PRIM_H6',
'SC_SUPERTILE_PER_PRIM_H7', 'SC_SUPERTILE_PER_PRIM_H8',
'SC_SUPERTILE_PER_PRIM_H9', 'SC_TILE_PER_PRIM_H0',
'SC_TILE_PER_PRIM_H1', 'SC_TILE_PER_PRIM_H10',
'SC_TILE_PER_PRIM_H11', 'SC_TILE_PER_PRIM_H12',
'SC_TILE_PER_PRIM_H13', 'SC_TILE_PER_PRIM_H14',
'SC_TILE_PER_PRIM_H15', 'SC_TILE_PER_PRIM_H16',
'SC_TILE_PER_PRIM_H2', 'SC_TILE_PER_PRIM_H3',
'SC_TILE_PER_PRIM_H4', 'SC_TILE_PER_PRIM_H5',
'SC_TILE_PER_PRIM_H6', 'SC_TILE_PER_PRIM_H7',
'SC_TILE_PER_PRIM_H8', 'SC_TILE_PER_PRIM_H9',
'SC_TILE_PER_SUPERTILE_H0', 'SC_TILE_PER_SUPERTILE_H1',
'SC_TILE_PER_SUPERTILE_H10', 'SC_TILE_PER_SUPERTILE_H11',
'SC_TILE_PER_SUPERTILE_H12', 'SC_TILE_PER_SUPERTILE_H13',
'SC_TILE_PER_SUPERTILE_H14', 'SC_TILE_PER_SUPERTILE_H15',
'SC_TILE_PER_SUPERTILE_H16', 'SC_TILE_PER_SUPERTILE_H2',
'SC_TILE_PER_SUPERTILE_H3', 'SC_TILE_PER_SUPERTILE_H4',
'SC_TILE_PER_SUPERTILE_H5', 'SC_TILE_PER_SUPERTILE_H6',
'SC_TILE_PER_SUPERTILE_H7', 'SC_TILE_PER_SUPERTILE_H8',
'SC_TILE_PER_SUPERTILE_H9', 'SC_TILE_PICKED_H1',
'SC_TILE_PICKED_H2', 'SC_TILE_PICKED_H3', 'SC_TILE_PICKED_H4',
'SC_TPQZ_WINDOW_VALID', 'SC_TPQZ_WINDOW_VALID_BUSY',
'SC_TRPK_WINDOW_VALID', 'SC_TRPK_WINDOW_VALID_BUSY', 'SC_UR_1X',
'SC_UR_2X', 'SC_UR_4X', 'SC_UR_8X', 'SC_VRS_COMB_MODE_MAX',
'SC_VRS_COMB_MODE_MIN', 'SC_VRS_COMB_MODE_OVERRIDE',
'SC_VRS_COMB_MODE_PASSTHRU', 'SC_VRS_COMB_MODE_SATURATE',
'SDMA0_BASE', 'SDMA0_BASE__INST0_SEG0', 'SDMA0_BASE__INST0_SEG1',
'SDMA0_BASE__INST0_SEG2', 'SDMA0_BASE__INST0_SEG3',
'SDMA0_BASE__INST0_SEG4', 'SDMA0_BASE__INST1_SEG0',
'SDMA0_BASE__INST1_SEG1', 'SDMA0_BASE__INST1_SEG2',
'SDMA0_BASE__INST1_SEG3', 'SDMA0_BASE__INST1_SEG4',
'SDMA0_BASE__INST2_SEG0', 'SDMA0_BASE__INST2_SEG1',
'SDMA0_BASE__INST2_SEG2', 'SDMA0_BASE__INST2_SEG3',
'SDMA0_BASE__INST2_SEG4', 'SDMA0_BASE__INST3_SEG0',
'SDMA0_BASE__INST3_SEG1', 'SDMA0_BASE__INST3_SEG2',
'SDMA0_BASE__INST3_SEG3', 'SDMA0_BASE__INST3_SEG4',
'SDMA0_BASE__INST4_SEG0', 'SDMA0_BASE__INST4_SEG1',
'SDMA0_BASE__INST4_SEG2', 'SDMA0_BASE__INST4_SEG3',
'SDMA0_BASE__INST4_SEG4', 'SDMA0_BASE__INST5_SEG0',
'SDMA0_BASE__INST5_SEG1', 'SDMA0_BASE__INST5_SEG2',
'SDMA0_BASE__INST5_SEG3', 'SDMA0_BASE__INST5_SEG4',
'SDMA0_BASE__INST6_SEG0', 'SDMA0_BASE__INST6_SEG1',
'SDMA0_BASE__INST6_SEG2', 'SDMA0_BASE__INST6_SEG3',
'SDMA0_BASE__INST6_SEG4', 'SDMA1_BASE', 'SDMA1_BASE__INST0_SEG0',
'SDMA1_BASE__INST0_SEG1', 'SDMA1_BASE__INST0_SEG2',
'SDMA1_BASE__INST0_SEG3', 'SDMA1_BASE__INST0_SEG4',
'SDMA1_BASE__INST1_SEG0', 'SDMA1_BASE__INST1_SEG1',
'SDMA1_BASE__INST1_SEG2', 'SDMA1_BASE__INST1_SEG3',
'SDMA1_BASE__INST1_SEG4', 'SDMA1_BASE__INST2_SEG0',
'SDMA1_BASE__INST2_SEG1', 'SDMA1_BASE__INST2_SEG2',
'SDMA1_BASE__INST2_SEG3', 'SDMA1_BASE__INST2_SEG4',
'SDMA1_BASE__INST3_SEG0', 'SDMA1_BASE__INST3_SEG1',
'SDMA1_BASE__INST3_SEG2', 'SDMA1_BASE__INST3_SEG3',
'SDMA1_BASE__INST3_SEG4', 'SDMA1_BASE__INST4_SEG0',
'SDMA1_BASE__INST4_SEG1', 'SDMA1_BASE__INST4_SEG2',
'SDMA1_BASE__INST4_SEG3', 'SDMA1_BASE__INST4_SEG4',
'SDMA1_BASE__INST5_SEG0', 'SDMA1_BASE__INST5_SEG1',
'SDMA1_BASE__INST5_SEG2', 'SDMA1_BASE__INST5_SEG3',
'SDMA1_BASE__INST5_SEG4', 'SDMA1_BASE__INST6_SEG0',
'SDMA1_BASE__INST6_SEG1', 'SDMA1_BASE__INST6_SEG2',
'SDMA1_BASE__INST6_SEG3', 'SDMA1_BASE__INST6_SEG4',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset',
'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift',
'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask',
'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset',
'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift',
'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask',
'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset',
'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset',
'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset',
'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift',
'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask',
'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset',
'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift',
'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask',
'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset',
'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift',
'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask',
'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset',
'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift',
'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask',
'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset',
'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift',
'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask',
'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset',
'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift',
'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset',
'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift',
'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask',
'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset',
'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift',
'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask',
'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset',
'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift',
'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask',
'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset',
'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift',
'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask',
'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset',
'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset',
'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift',
'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask',
'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset',
'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift',
'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask',
'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset',
'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift',
'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask',
'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset',
'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift',
'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask',
'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset',
'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift',
'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask',
'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset',
'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift',
'SDMA_AQL_PKT_HEADER_HEADER_barrier_mask',
'SDMA_AQL_PKT_HEADER_HEADER_barrier_offset',
'SDMA_AQL_PKT_HEADER_HEADER_barrier_shift',
'SDMA_AQL_PKT_HEADER_HEADER_cpv_mask',
'SDMA_AQL_PKT_HEADER_HEADER_cpv_offset',
'SDMA_AQL_PKT_HEADER_HEADER_cpv_shift',
'SDMA_AQL_PKT_HEADER_HEADER_format_mask',
'SDMA_AQL_PKT_HEADER_HEADER_format_offset',
'SDMA_AQL_PKT_HEADER_HEADER_format_shift',
'SDMA_AQL_PKT_HEADER_HEADER_op_mask',
'SDMA_AQL_PKT_HEADER_HEADER_op_offset',
'SDMA_AQL_PKT_HEADER_HEADER_op_shift',
'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask',
'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset',
'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift',
'SDMA_AQL_PKT_HEADER_HEADER_reserved_mask',
'SDMA_AQL_PKT_HEADER_HEADER_reserved_offset',
'SDMA_AQL_PKT_HEADER_HEADER_reserved_shift',
'SDMA_AQL_PKT_HEADER_HEADER_subop_mask',
'SDMA_AQL_PKT_HEADER_HEADER_subop_offset',
'SDMA_AQL_PKT_HEADER_HEADER_subop_shift', 'SDMA_ATOMIC_ADD64',
'SDMA_GCR_GL1_INV', 'SDMA_GCR_GL2_DISCARD', 'SDMA_GCR_GL2_INV',
'SDMA_GCR_GL2_US', 'SDMA_GCR_GL2_WB', 'SDMA_GCR_GLK_INV',
'SDMA_GCR_GLK_WB', 'SDMA_GCR_GLM_INV', 'SDMA_GCR_GLM_WB',
'SDMA_GCR_GLV_INV', 'SDMA_GCR_RANGE_IS_PA',
'SDMA_OP_AQL_BARRIER_OR', 'SDMA_OP_AQL_COPY', 'SDMA_OP_ATOMIC',
'SDMA_OP_COND_EXE', 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY',
'SDMA_OP_DUMMY_TRAP', 'SDMA_OP_FENCE', 'SDMA_OP_GCR',
'SDMA_OP_GCR_REQ', 'SDMA_OP_GPUVM_INV', 'SDMA_OP_INDIRECT',
'SDMA_OP_NOP', 'SDMA_OP_POLL_REGMEM', 'SDMA_OP_PRE_EXE',
'SDMA_OP_PTEPDE', 'SDMA_OP_SEM', 'SDMA_OP_SRBM_WRITE',
'SDMA_OP_TIMESTAMP', 'SDMA_OP_TRAP', 'SDMA_OP_WRITE',
'SDMA_PERFMON_SEL', 'SDMA_PERFMON_SEL_CE_AFIFO_FULL',
'SDMA_PERFMON_SEL_CE_DST_IDLE', 'SDMA_PERFMON_SEL_CE_INFO1_FULL',
'SDMA_PERFMON_SEL_CE_INFO_FULL', 'SDMA_PERFMON_SEL_CE_IN_IDLE',
'SDMA_PERFMON_SEL_CE_L1_WR_VLD', 'SDMA_PERFMON_SEL_CE_OUT_IDLE',
'SDMA_PERFMON_SEL_CE_RD_STALL', 'SDMA_PERFMON_SEL_CE_RREQ_IDLE',
'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', 'SDMA_PERFMON_SEL_CE_WREQ_IDLE',
'SDMA_PERFMON_SEL_CE_WR_IDLE', 'SDMA_PERFMON_SEL_CE_WR_STALL',
'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', 'SDMA_PERFMON_SEL_CTX_CHANGE',
'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION',
'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERFMON_SEL_CYCLE',
'SDMA_PERFMON_SEL_DMA_L1_RD_SEND',
'SDMA_PERFMON_SEL_DMA_L1_WR_SEND',
'SDMA_PERFMON_SEL_DMA_MC_RD_SEND',
'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', 'SDMA_PERFMON_SEL_DOORBELL',
'SDMA_PERFMON_SEL_EX_IDLE',
'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
'SDMA_PERFMON_SEL_F32_L1_WR_VLD', 'SDMA_PERFMON_SEL_GCR_RTN',
'SDMA_PERFMON_SEL_GCR_SEND', 'SDMA_PERFMON_SEL_GFX_SELECT',
'SDMA_PERFMON_SEL_GPUVM_INV_HIGH',
'SDMA_PERFMON_SEL_GPUVM_INV_LOW', 'SDMA_PERFMON_SEL_IB_CMD_FULL',
'SDMA_PERFMON_SEL_IB_CMD_IDLE', 'SDMA_PERFMON_SEL_IDLE',
'SDMA_PERFMON_SEL_INT_IDLE', 'SDMA_PERFMON_SEL_INT_REQ_COUNT',
'SDMA_PERFMON_SEL_INT_REQ_STALL',
'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED',
'SDMA_PERFMON_SEL_INT_RESP_RETRY',
'SDMA_PERFMON_SEL_L1_RDL2_IDLE', 'SDMA_PERFMON_SEL_L1_RDMC_IDLE',
'SDMA_PERFMON_SEL_L1_RD_INV_IDLE',
'SDMA_PERFMON_SEL_L1_WRL2_IDLE', 'SDMA_PERFMON_SEL_L1_WRMC_IDLE',
'SDMA_PERFMON_SEL_L1_WR_INV_IDLE',
'SDMA_PERFMON_SEL_L2_META_RET_VLD',
'SDMA_PERFMON_SEL_MC_RD_COUNT', 'SDMA_PERFMON_SEL_MC_RD_IDLE',
'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE',
'SDMA_PERFMON_SEL_MC_RD_RET_STALL',
'SDMA_PERFMON_SEL_MC_WR_COUNT', 'SDMA_PERFMON_SEL_MC_WR_IDLE',
'SDMA_PERFMON_SEL_META_L2_REQ_SEND',
'SDMA_PERFMON_SEL_META_REQ_SEND', 'SDMA_PERFMON_SEL_META_RTN_VLD',
'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER',
'SDMA_PERFMON_SEL_NUM_PACKET', 'SDMA_PERFMON_SEL_PAGE_SELECT',
'SDMA_PERFMON_SEL_RB_CMD_FULL', 'SDMA_PERFMON_SEL_RB_CMD_IDLE',
'SDMA_PERFMON_SEL_RB_EMPTY', 'SDMA_PERFMON_SEL_RB_FULL',
'SDMA_PERFMON_SEL_RB_RPTR_WB', 'SDMA_PERFMON_SEL_RB_RPTR_WRAP',
'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ',
'SDMA_PERFMON_SEL_RB_WPTR_WRAP', 'SDMA_PERFMON_SEL_RD_BA_RTR',
'SDMA_PERFMON_SEL_REG_IDLE', 'SDMA_PERFMON_SEL_RLC0_SELECT',
'SDMA_PERFMON_SEL_RLC1_SELECT',
'SDMA_PERFMON_SEL_SDMA_CPF_INVACK',
'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK',
'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL',
'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND',
'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND',
'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND',
'SDMA_PERFMON_SEL_SEM_IDLE', 'SDMA_PERFMON_SEL_SEM_REQ_COUNT',
'SDMA_PERFMON_SEL_SEM_REQ_STALL',
'SDMA_PERFMON_SEL_SEM_RESP_FAIL',
'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE',
'SDMA_PERFMON_SEL_SEM_RESP_PASS',
'SDMA_PERFMON_SEL_SRBM_REG_SEND', 'SDMA_PERFMON_SEL_TLBI_RTN',
'SDMA_PERFMON_SEL_TLBI_SEND',
'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER',
'SDMA_PERFMON_SEL_UTCL2_FREE', 'SDMA_PERFMON_SEL_UTCL2_RET_ACK',
'SDMA_PERFMON_SEL_UTCL2_RET_XNACK',
'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ',
'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL',
'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN',
'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN',
'SDMA_PERFMON_SEL_WR_BA_RTR', 'SDMA_PERF_SEL',
'SDMA_PERF_SEL_CE_AFIFO_FULL', 'SDMA_PERF_SEL_CE_BUSY',
'SDMA_PERF_SEL_CE_BUSY_END', 'SDMA_PERF_SEL_CE_BUSY_START',
'SDMA_PERF_SEL_CE_CH_RDREQ_SEND',
'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', 'SDMA_PERF_SEL_CE_CH_WR_REQ',
'SDMA_PERF_SEL_CE_CH_WR_RET', 'SDMA_PERF_SEL_CE_DST_IDLE',
'SDMA_PERF_SEL_CE_INFO1_FULL', 'SDMA_PERF_SEL_CE_INFO_FULL',
'SDMA_PERF_SEL_CE_IN_IDLE', 'SDMA_PERF_SEL_CE_L1_WR_VLD',
'SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ',
'SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET', 'SDMA_PERF_SEL_CE_OUT_IDLE',
'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE',
'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE',
'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL',
'SDMA_PERF_SEL_CGCG_FENCE', 'SDMA_PERF_SEL_CH_CE_RDRET_VALID',
'SDMA_PERF_SEL_CH_CE_WRRET_VALID', 'SDMA_PERF_SEL_CMD_OP_END',
'SDMA_PERF_SEL_CMD_OP_MATCH', 'SDMA_PERF_SEL_CMD_OP_START',
'SDMA_PERF_SEL_CPF_SDMA_INVREQ', 'SDMA_PERF_SEL_CTX_CHANGE',
'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION',
'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE',
'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND',
'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND',
'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_EX_IDLE',
'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE',
'SDMA_PERF_SEL_F32_CH_WR_REQ', 'SDMA_PERF_SEL_F32_CH_WR_RET',
'SDMA_PERF_SEL_F32_L1_WR_VLD',
'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER',
'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END',
'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START',
'SDMA_PERF_SEL_GCR_RTN', 'SDMA_PERF_SEL_GCR_SEND',
'SDMA_PERF_SEL_GFX_SELECT', 'SDMA_PERF_SEL_GPUVM_INV_HIGH',
'SDMA_PERF_SEL_GPUVM_INV_LOW', 'SDMA_PERF_SEL_IB_CH_RD_REQ',
'SDMA_PERF_SEL_IB_CH_RD_RET', 'SDMA_PERF_SEL_IB_CMD_FULL',
'SDMA_PERF_SEL_IB_CMD_IDLE', 'SDMA_PERF_SEL_IDLE',
'SDMA_PERF_SEL_INT_IDLE', 'SDMA_PERF_SEL_INT_REQ_COUNT',
'SDMA_PERF_SEL_INT_REQ_STALL', 'SDMA_PERF_SEL_INT_RESP_ACCEPTED',
'SDMA_PERF_SEL_INT_RESP_RETRY', 'SDMA_PERF_SEL_L1_RDL2_IDLE',
'SDMA_PERF_SEL_L1_RDMC_IDLE', 'SDMA_PERF_SEL_L1_RD_INV_IDLE',
'SDMA_PERF_SEL_L1_WRL2_IDLE', 'SDMA_PERF_SEL_L1_WRMC_IDLE',
'SDMA_PERF_SEL_L1_WR_INV_IDLE', 'SDMA_PERF_SEL_L2_META_RET_VLD',
'SDMA_PERF_SEL_MC_RD_COUNT', 'SDMA_PERF_SEL_MC_RD_IDLE',
'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE',
'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT',
'SDMA_PERF_SEL_MC_WR_IDLE', 'SDMA_PERF_SEL_META_L2_REQ_SEND',
'SDMA_PERF_SEL_META_REQ_SEND', 'SDMA_PERF_SEL_META_RTN_VLD',
'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_PAGE_SELECT',
'SDMA_PERF_SEL_RB_CH_RD_REQ', 'SDMA_PERF_SEL_RB_CH_RD_RET',
'SDMA_PERF_SEL_RB_CMD_FULL', 'SDMA_PERF_SEL_RB_CMD_IDLE',
'SDMA_PERF_SEL_RB_EMPTY', 'SDMA_PERF_SEL_RB_FULL',
'SDMA_PERF_SEL_RB_RPTR_WB', 'SDMA_PERF_SEL_RB_RPTR_WRAP',
'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 'SDMA_PERF_SEL_RB_WPTR_WRAP',
'SDMA_PERF_SEL_RD_BA_RTR', 'SDMA_PERF_SEL_REG_IDLE',
'SDMA_PERF_SEL_RLC0_SELECT', 'SDMA_PERF_SEL_RLC1_SELECT',
'SDMA_PERF_SEL_SDMA_CPF_INVACK',
'SDMA_PERF_SEL_SDMA_UTCL2_INVACK',
'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL',
'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND',
'SDMA_PERF_SEL_SDMA_UTCL2_SEND',
'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', 'SDMA_PERF_SEL_SEM_IDLE',
'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL',
'SDMA_PERF_SEL_SEM_RESP_FAIL',
'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE',
'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND',
'SDMA_PERF_SEL_TLBI_RTN', 'SDMA_PERF_SEL_TLBI_SEND',
'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', 'SDMA_PERF_SEL_UTCL1_UTCL2_RET',
'SDMA_PERF_SEL_UTCL2_FREE', 'SDMA_PERF_SEL_UTCL2_RET_ACK',
'SDMA_PERF_SEL_UTCL2_RET_XNACK',
'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ',
'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL',
'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN',
'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', 'SDMA_PERF_SEL_WPTR_CH_RD_REQ',
'SDMA_PERF_SEL_WPTR_CH_RD_RET', 'SDMA_PERF_SEL_WR_BA_RTR',
'SDMA_PKT_ATOMIC', 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask',
'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset',
'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift',
'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask',
'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset',
'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift',
'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask',
'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset',
'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift',
'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask',
'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset',
'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift',
'SDMA_PKT_ATOMIC_HEADER_atomic_op_mask',
'SDMA_PKT_ATOMIC_HEADER_atomic_op_offset',
'SDMA_PKT_ATOMIC_HEADER_atomic_op_shift',
'SDMA_PKT_ATOMIC_HEADER_cache_policy_mask',
'SDMA_PKT_ATOMIC_HEADER_cache_policy_offset',
'SDMA_PKT_ATOMIC_HEADER_cache_policy_shift',
'SDMA_PKT_ATOMIC_HEADER_cpv_mask',
'SDMA_PKT_ATOMIC_HEADER_cpv_offset',
'SDMA_PKT_ATOMIC_HEADER_cpv_shift',
'SDMA_PKT_ATOMIC_HEADER_loop_mask',
'SDMA_PKT_ATOMIC_HEADER_loop_offset',
'SDMA_PKT_ATOMIC_HEADER_loop_shift',
'SDMA_PKT_ATOMIC_HEADER_op_mask',
'SDMA_PKT_ATOMIC_HEADER_op_offset',
'SDMA_PKT_ATOMIC_HEADER_op_shift',
'SDMA_PKT_ATOMIC_HEADER_tmz_mask',
'SDMA_PKT_ATOMIC_HEADER_tmz_offset',
'SDMA_PKT_ATOMIC_HEADER_tmz_shift',
'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask',
'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset',
'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift',
'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask',
'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset',
'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift',
'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask',
'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset',
'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift',
'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask',
'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset',
'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift',
'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask',
'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset',
'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift',
'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask',
'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset',
'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift',
'SDMA_PKT_COND_EXE_HEADER_cache_policy_mask',
'SDMA_PKT_COND_EXE_HEADER_cache_policy_offset',
'SDMA_PKT_COND_EXE_HEADER_cache_policy_shift',
'SDMA_PKT_COND_EXE_HEADER_cpv_mask',
'SDMA_PKT_COND_EXE_HEADER_cpv_offset',
'SDMA_PKT_COND_EXE_HEADER_cpv_shift',
'SDMA_PKT_COND_EXE_HEADER_op_mask',
'SDMA_PKT_COND_EXE_HEADER_op_offset',
'SDMA_PKT_COND_EXE_HEADER_op_shift',
'SDMA_PKT_COND_EXE_HEADER_sub_op_mask',
'SDMA_PKT_COND_EXE_HEADER_sub_op_offset',
'SDMA_PKT_COND_EXE_HEADER_sub_op_shift',
'SDMA_PKT_COND_EXE_REFERENCE_reference_mask',
'SDMA_PKT_COND_EXE_REFERENCE_reference_offset',
'SDMA_PKT_COND_EXE_REFERENCE_reference_shift',
'SDMA_PKT_CONSTANT_FILL',
'SDMA_PKT_CONSTANT_FILL_COUNT_count_mask',
'SDMA_PKT_CONSTANT_FILL_COUNT_count_offset',
'SDMA_PKT_CONSTANT_FILL_COUNT_count_shift',
'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask',
'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset',
'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift',
'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask',
'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset',
'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift',
'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask',
'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset',
'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift',
'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask',
'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset',
'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift',
'SDMA_PKT_CONSTANT_FILL_HEADER_op_mask',
'SDMA_PKT_CONSTANT_FILL_HEADER_op_offset',
'SDMA_PKT_CONSTANT_FILL_HEADER_op_shift',
'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask',
'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset',
'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift',
'SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask',
'SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset',
'SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift',
'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask',
'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset',
'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift',
'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask',
'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset',
'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift',
'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask',
'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset',
'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift',
'SDMA_PKT_COPY_LINEAR',
'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask',
'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset',
'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift',
'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask',
'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset',
'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift',
'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask',
'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset',
'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift',
'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask',
'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset',
'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift',
'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask',
'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset',
'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift',
'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask',
'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset',
'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift',
'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask',
'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset',
'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift',
'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask',
'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset',
'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift',
'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask',
'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset',
'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift',
'SDMA_PKT_COPY_LINEAR_COUNT_count_mask',
'SDMA_PKT_COPY_LINEAR_COUNT_count_offset',
'SDMA_PKT_COPY_LINEAR_COUNT_count_shift',
'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask',
'SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset',
'SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift',
'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask',
'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset',
'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift',
'SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask',
'SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset',
'SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift',
'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask',
'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset',
'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift',
'SDMA_PKT_COPY_LINEAR_HEADER_op_mask',
'SDMA_PKT_COPY_LINEAR_HEADER_op_offset',
'SDMA_PKT_COPY_LINEAR_HEADER_op_shift',
'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask',
'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset',
'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift',
'SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask',
'SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset',
'SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift',
'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask',
'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset',
'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift',
'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask',
'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset',
'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift',
'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask',
'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset',
'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift',
'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask',
'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset',
'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift',
'SDMA_PKT_COPY_LINEAR_RECT',
'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask',
'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset',
'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift',
'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask',
'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset',
'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift',
'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask',
'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset',
'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset',
'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift',
'SDMA_PKT_COPY_STRUCT_COUNT_count_mask',
'SDMA_PKT_COPY_STRUCT_COUNT_count_offset',
'SDMA_PKT_COPY_STRUCT_COUNT_count_shift',
'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask',
'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset',
'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift',
'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask',
'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset',
'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift',
'SDMA_PKT_COPY_STRUCT_DW_5_stride_mask',
'SDMA_PKT_COPY_STRUCT_DW_5_stride_offset',
'SDMA_PKT_COPY_STRUCT_DW_5_stride_shift',
'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask',
'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset',
'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift',
'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask',
'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset',
'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift',
'SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask',
'SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset',
'SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift',
'SDMA_PKT_COPY_STRUCT_HEADER_detile_mask',
'SDMA_PKT_COPY_STRUCT_HEADER_detile_offset',
'SDMA_PKT_COPY_STRUCT_HEADER_detile_shift',
'SDMA_PKT_COPY_STRUCT_HEADER_op_mask',
'SDMA_PKT_COPY_STRUCT_HEADER_op_offset',
'SDMA_PKT_COPY_STRUCT_HEADER_op_shift',
'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask',
'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset',
'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift',
'SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask',
'SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset',
'SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift',
'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask',
'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset',
'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift',
'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask',
'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset',
'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift',
'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask',
'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset',
'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift',
'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask',
'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset',
'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift',
'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask',
'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset',
'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift',
'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask',
'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset',
'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift',
'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask',
'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset',
'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift',
'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask',
'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset',
'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift',
'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask',
'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset',
'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset',
'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift',
'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask',
'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset',
'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift',
'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask',
'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset',
'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift',
'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask',
'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset',
'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift',
'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask',
'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset',
'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift',
'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask',
'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset',
'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift',
'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask',
'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset',
'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift',
'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask',
'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset',
'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift',
'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask',
'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset',
'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift',
'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask',
'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset',
'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift',
'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask',
'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset',
'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift',
'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask',
'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset',
'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset',
'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift',
'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask',
'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset',
'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift',
'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask',
'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset',
'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift',
'SDMA_PKT_COPY_T2T_BC_HEADER_op_mask',
'SDMA_PKT_COPY_T2T_BC_HEADER_op_offset',
'SDMA_PKT_COPY_T2T_BC_HEADER_op_shift',
'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask',
'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset',
'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift',
'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask',
'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset',
'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift',
'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask',
'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset',
'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift',
'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_COPY_T2T_DW_10_dst_width_mask',
'SDMA_PKT_COPY_T2T_DW_10_dst_width_offset',
'SDMA_PKT_COPY_T2T_DW_10_dst_width_shift',
'SDMA_PKT_COPY_T2T_DW_10_dst_z_mask',
'SDMA_PKT_COPY_T2T_DW_10_dst_z_offset',
'SDMA_PKT_COPY_T2T_DW_10_dst_z_shift',
'SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask',
'SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset',
'SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift',
'SDMA_PKT_COPY_T2T_DW_11_dst_height_mask',
'SDMA_PKT_COPY_T2T_DW_11_dst_height_offset',
'SDMA_PKT_COPY_T2T_DW_11_dst_height_shift',
'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask',
'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset',
'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift',
'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask',
'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset',
'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift',
'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask',
'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset',
'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift',
'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask',
'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset',
'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift',
'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask',
'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset',
'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift',
'SDMA_PKT_COPY_T2T_DW_13_rect_x_mask',
'SDMA_PKT_COPY_T2T_DW_13_rect_x_offset',
'SDMA_PKT_COPY_T2T_DW_13_rect_x_shift',
'SDMA_PKT_COPY_T2T_DW_13_rect_y_mask',
'SDMA_PKT_COPY_T2T_DW_13_rect_y_offset',
'SDMA_PKT_COPY_T2T_DW_13_rect_y_shift',
'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask',
'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset',
'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift',
'SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask',
'SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset',
'SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift',
'SDMA_PKT_COPY_T2T_DW_14_rect_z_mask',
'SDMA_PKT_COPY_T2T_DW_14_rect_z_offset',
'SDMA_PKT_COPY_T2T_DW_14_rect_z_shift',
'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask',
'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset',
'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift',
'SDMA_PKT_COPY_T2T_DW_14_src_sw_mask',
'SDMA_PKT_COPY_T2T_DW_14_src_sw_offset',
'SDMA_PKT_COPY_T2T_DW_14_src_sw_shift',
'SDMA_PKT_COPY_T2T_DW_3_src_x_mask',
'SDMA_PKT_COPY_T2T_DW_3_src_x_offset',
'SDMA_PKT_COPY_T2T_DW_3_src_x_shift',
'SDMA_PKT_COPY_T2T_DW_3_src_y_mask',
'SDMA_PKT_COPY_T2T_DW_3_src_y_offset',
'SDMA_PKT_COPY_T2T_DW_3_src_y_shift',
'SDMA_PKT_COPY_T2T_DW_4_src_width_mask',
'SDMA_PKT_COPY_T2T_DW_4_src_width_offset',
'SDMA_PKT_COPY_T2T_DW_4_src_width_shift',
'SDMA_PKT_COPY_T2T_DW_4_src_z_mask',
'SDMA_PKT_COPY_T2T_DW_4_src_z_offset',
'SDMA_PKT_COPY_T2T_DW_4_src_z_shift',
'SDMA_PKT_COPY_T2T_DW_5_src_depth_mask',
'SDMA_PKT_COPY_T2T_DW_5_src_depth_offset',
'SDMA_PKT_COPY_T2T_DW_5_src_depth_shift',
'SDMA_PKT_COPY_T2T_DW_5_src_height_mask',
'SDMA_PKT_COPY_T2T_DW_5_src_height_offset',
'SDMA_PKT_COPY_T2T_DW_5_src_height_shift',
'SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask',
'SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset',
'SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift',
'SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask',
'SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset',
'SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift',
'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask',
'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset',
'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift',
'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask',
'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset',
'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift',
'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask',
'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset',
'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift',
'SDMA_PKT_COPY_T2T_DW_9_dst_x_mask',
'SDMA_PKT_COPY_T2T_DW_9_dst_x_offset',
'SDMA_PKT_COPY_T2T_DW_9_dst_x_shift',
'SDMA_PKT_COPY_T2T_DW_9_dst_y_mask',
'SDMA_PKT_COPY_T2T_DW_9_dst_y_offset',
'SDMA_PKT_COPY_T2T_DW_9_dst_y_shift',
'SDMA_PKT_COPY_T2T_HEADER_cpv_mask',
'SDMA_PKT_COPY_T2T_HEADER_cpv_offset',
'SDMA_PKT_COPY_T2T_HEADER_cpv_shift',
'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask',
'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset',
'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift',
'SDMA_PKT_COPY_T2T_HEADER_dcc_mask',
'SDMA_PKT_COPY_T2T_HEADER_dcc_offset',
'SDMA_PKT_COPY_T2T_HEADER_dcc_shift',
'SDMA_PKT_COPY_T2T_HEADER_op_mask',
'SDMA_PKT_COPY_T2T_HEADER_op_offset',
'SDMA_PKT_COPY_T2T_HEADER_op_shift',
'SDMA_PKT_COPY_T2T_HEADER_sub_op_mask',
'SDMA_PKT_COPY_T2T_HEADER_sub_op_offset',
'SDMA_PKT_COPY_T2T_HEADER_sub_op_shift',
'SDMA_PKT_COPY_T2T_HEADER_tmz_mask',
'SDMA_PKT_COPY_T2T_HEADER_tmz_offset',
'SDMA_PKT_COPY_T2T_HEADER_tmz_shift',
'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask',
'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset',
'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift',
'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask',
'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset',
'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift',
'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask',
'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset',
'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift',
'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask',
'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset',
'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift',
'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask',
'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset',
'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift',
'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask',
'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset',
'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift',
'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask',
'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset',
'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift',
'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask',
'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset',
'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift',
'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask',
'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset',
'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift',
'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask',
'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset',
'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift',
'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask',
'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset',
'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift',
'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask',
'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset',
'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift',
'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask',
'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset',
'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift',
'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask',
'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset',
'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift',
'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask',
'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset',
'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift',
'SDMA_PKT_COPY_TILED_BC_COUNT_count_mask',
'SDMA_PKT_COPY_TILED_BC_COUNT_count_offset',
'SDMA_PKT_COPY_TILED_BC_COUNT_count_shift',
'SDMA_PKT_COPY_TILED_BC_DW_3_width_mask',
'SDMA_PKT_COPY_TILED_BC_DW_3_width_offset',
'SDMA_PKT_COPY_TILED_BC_DW_3_width_shift',
'SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask',
'SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset',
'SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift',
'SDMA_PKT_COPY_TILED_BC_DW_4_height_mask',
'SDMA_PKT_COPY_TILED_BC_DW_4_height_offset',
'SDMA_PKT_COPY_TILED_BC_DW_4_height_shift',
'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask',
'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset',
'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift',
'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask',
'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset',
'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift',
'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask',
'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset',
'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift',
'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask',
'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset',
'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift',
'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask',
'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset',
'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift',
'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask',
'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset',
'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift',
'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask',
'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset',
'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift',
'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask',
'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset',
'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift',
'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask',
'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset',
'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift',
'SDMA_PKT_COPY_TILED_BC_DW_6_x_mask',
'SDMA_PKT_COPY_TILED_BC_DW_6_x_offset',
'SDMA_PKT_COPY_TILED_BC_DW_6_x_shift',
'SDMA_PKT_COPY_TILED_BC_DW_6_y_mask',
'SDMA_PKT_COPY_TILED_BC_DW_6_y_offset',
'SDMA_PKT_COPY_TILED_BC_DW_6_y_shift',
'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask',
'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset',
'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift',
'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask',
'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset',
'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift',
'SDMA_PKT_COPY_TILED_BC_DW_7_z_mask',
'SDMA_PKT_COPY_TILED_BC_DW_7_z_offset',
'SDMA_PKT_COPY_TILED_BC_DW_7_z_shift',
'SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask',
'SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset',
'SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift',
'SDMA_PKT_COPY_TILED_BC_HEADER_op_mask',
'SDMA_PKT_COPY_TILED_BC_HEADER_op_offset',
'SDMA_PKT_COPY_TILED_BC_HEADER_op_shift',
'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask',
'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset',
'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift',
'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask',
'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset',
'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift',
'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask',
'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset',
'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift',
'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask',
'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset',
'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift',
'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask',
'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset',
'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift',
'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask',
'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset',
'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift',
'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask',
'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset',
'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift',
'SDMA_PKT_COPY_TILED_COUNT_count_mask',
'SDMA_PKT_COPY_TILED_COUNT_count_offset',
'SDMA_PKT_COPY_TILED_COUNT_count_shift',
'SDMA_PKT_COPY_TILED_DW_3_width_mask',
'SDMA_PKT_COPY_TILED_DW_3_width_offset',
'SDMA_PKT_COPY_TILED_DW_3_width_shift',
'SDMA_PKT_COPY_TILED_DW_4_depth_mask',
'SDMA_PKT_COPY_TILED_DW_4_depth_offset',
'SDMA_PKT_COPY_TILED_DW_4_depth_shift',
'SDMA_PKT_COPY_TILED_DW_4_height_mask',
'SDMA_PKT_COPY_TILED_DW_4_height_offset',
'SDMA_PKT_COPY_TILED_DW_4_height_shift',
'SDMA_PKT_COPY_TILED_DW_5_dimension_mask',
'SDMA_PKT_COPY_TILED_DW_5_dimension_offset',
'SDMA_PKT_COPY_TILED_DW_5_dimension_shift',
'SDMA_PKT_COPY_TILED_DW_5_element_size_mask',
'SDMA_PKT_COPY_TILED_DW_5_element_size_offset',
'SDMA_PKT_COPY_TILED_DW_5_element_size_shift',
'SDMA_PKT_COPY_TILED_DW_5_mip_max_mask',
'SDMA_PKT_COPY_TILED_DW_5_mip_max_offset',
'SDMA_PKT_COPY_TILED_DW_5_mip_max_shift',
'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask',
'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset',
'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift',
'SDMA_PKT_COPY_TILED_DW_6_x_mask',
'SDMA_PKT_COPY_TILED_DW_6_x_offset',
'SDMA_PKT_COPY_TILED_DW_6_x_shift',
'SDMA_PKT_COPY_TILED_DW_6_y_mask',
'SDMA_PKT_COPY_TILED_DW_6_y_offset',
'SDMA_PKT_COPY_TILED_DW_6_y_shift',
'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask',
'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset',
'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift',
'SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask',
'SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset',
'SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift',
'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask',
'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset',
'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift',
'SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask',
'SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset',
'SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift',
'SDMA_PKT_COPY_TILED_DW_7_z_mask',
'SDMA_PKT_COPY_TILED_DW_7_z_offset',
'SDMA_PKT_COPY_TILED_DW_7_z_shift',
'SDMA_PKT_COPY_TILED_HEADER_cpv_mask',
'SDMA_PKT_COPY_TILED_HEADER_cpv_offset',
'SDMA_PKT_COPY_TILED_HEADER_cpv_shift',
'SDMA_PKT_COPY_TILED_HEADER_detile_mask',
'SDMA_PKT_COPY_TILED_HEADER_detile_offset',
'SDMA_PKT_COPY_TILED_HEADER_detile_shift',
'SDMA_PKT_COPY_TILED_HEADER_encrypt_mask',
'SDMA_PKT_COPY_TILED_HEADER_encrypt_offset',
'SDMA_PKT_COPY_TILED_HEADER_encrypt_shift',
'SDMA_PKT_COPY_TILED_HEADER_op_mask',
'SDMA_PKT_COPY_TILED_HEADER_op_offset',
'SDMA_PKT_COPY_TILED_HEADER_op_shift',
'SDMA_PKT_COPY_TILED_HEADER_sub_op_mask',
'SDMA_PKT_COPY_TILED_HEADER_sub_op_offset',
'SDMA_PKT_COPY_TILED_HEADER_sub_op_shift',
'SDMA_PKT_COPY_TILED_HEADER_tmz_mask',
'SDMA_PKT_COPY_TILED_HEADER_tmz_offset',
'SDMA_PKT_COPY_TILED_HEADER_tmz_shift',
'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask',
'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset',
'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift',
'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask',
'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset',
'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift',
'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask',
'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset',
'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift',
'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask',
'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset',
'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift',
'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask',
'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset',
'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift',
'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask',
'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset',
'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift',
'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask',
'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset',
'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift',
'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask',
'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset',
'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift',
'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask',
'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset',
'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift',
'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask',
'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset',
'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift',
'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset',
'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift',
'SDMA_PKT_DUMMY_TRAP_HEADER_op_mask',
'SDMA_PKT_DUMMY_TRAP_HEADER_op_offset',
'SDMA_PKT_DUMMY_TRAP_HEADER_op_shift',
'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask',
'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset',
'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift',
'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask',
'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset',
'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift',
'SDMA_PKT_FENCE', 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask',
'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset',
'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift',
'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask',
'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset',
'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift',
'SDMA_PKT_FENCE_DATA_data_mask',
'SDMA_PKT_FENCE_DATA_data_offset',
'SDMA_PKT_FENCE_DATA_data_shift',
'SDMA_PKT_FENCE_HEADER_cpv_mask',
'SDMA_PKT_FENCE_HEADER_cpv_offset',
'SDMA_PKT_FENCE_HEADER_cpv_shift',
'SDMA_PKT_FENCE_HEADER_gcc_mask',
'SDMA_PKT_FENCE_HEADER_gcc_offset',
'SDMA_PKT_FENCE_HEADER_gcc_shift',
'SDMA_PKT_FENCE_HEADER_gpa_mask',
'SDMA_PKT_FENCE_HEADER_gpa_offset',
'SDMA_PKT_FENCE_HEADER_gpa_shift',
'SDMA_PKT_FENCE_HEADER_l2_policy_mask',
'SDMA_PKT_FENCE_HEADER_l2_policy_offset',
'SDMA_PKT_FENCE_HEADER_l2_policy_shift',
'SDMA_PKT_FENCE_HEADER_llc_policy_mask',
'SDMA_PKT_FENCE_HEADER_llc_policy_offset',
'SDMA_PKT_FENCE_HEADER_llc_policy_shift',
'SDMA_PKT_FENCE_HEADER_mtype_mask',
'SDMA_PKT_FENCE_HEADER_mtype_offset',
'SDMA_PKT_FENCE_HEADER_mtype_shift',
'SDMA_PKT_FENCE_HEADER_op_mask',
'SDMA_PKT_FENCE_HEADER_op_offset',
'SDMA_PKT_FENCE_HEADER_op_shift',
'SDMA_PKT_FENCE_HEADER_snp_mask',
'SDMA_PKT_FENCE_HEADER_snp_offset',
'SDMA_PKT_FENCE_HEADER_snp_shift',
'SDMA_PKT_FENCE_HEADER_sub_op_mask',
'SDMA_PKT_FENCE_HEADER_sub_op_offset',
'SDMA_PKT_FENCE_HEADER_sub_op_shift',
'SDMA_PKT_FENCE_HEADER_sys_mask',
'SDMA_PKT_FENCE_HEADER_sys_offset',
'SDMA_PKT_FENCE_HEADER_sys_shift', 'SDMA_PKT_GCR',
'SDMA_PKT_GCR_REQ_HEADER_op_mask',
'SDMA_PKT_GCR_REQ_HEADER_op_offset',
'SDMA_PKT_GCR_REQ_HEADER_op_shift',
'SDMA_PKT_GCR_REQ_HEADER_sub_op_mask',
'SDMA_PKT_GCR_REQ_HEADER_sub_op_offset',
'SDMA_PKT_GCR_REQ_HEADER_sub_op_shift',
'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask',
'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset',
'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift',
'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask',
'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset',
'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift',
'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask',
'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset',
'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift',
'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask',
'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset',
'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift',
'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask',
'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset',
'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift',
'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask',
'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset',
'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift',
'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask',
'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset',
'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift',
'SDMA_PKT_GPUVM_INV_HEADER_op_mask',
'SDMA_PKT_GPUVM_INV_HEADER_op_offset',
'SDMA_PKT_GPUVM_INV_HEADER_op_shift',
'SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask',
'SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset',
'SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset',
'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift',
'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask',
'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset',
'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift',
'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask',
'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset',
'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift',
'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask',
'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset',
'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift',
'SDMA_PKT_HDP_FLUSH',
'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask',
'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset',
'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift',
'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask',
'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset',
'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift',
'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask',
'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset',
'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift',
'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask',
'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset',
'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift',
'SDMA_PKT_INDIRECT_HEADER_op_mask',
'SDMA_PKT_INDIRECT_HEADER_op_offset',
'SDMA_PKT_INDIRECT_HEADER_op_shift',
'SDMA_PKT_INDIRECT_HEADER_priv_mask',
'SDMA_PKT_INDIRECT_HEADER_priv_offset',
'SDMA_PKT_INDIRECT_HEADER_priv_shift',
'SDMA_PKT_INDIRECT_HEADER_sub_op_mask',
'SDMA_PKT_INDIRECT_HEADER_sub_op_offset',
'SDMA_PKT_INDIRECT_HEADER_sub_op_shift',
'SDMA_PKT_INDIRECT_HEADER_vmid_mask',
'SDMA_PKT_INDIRECT_HEADER_vmid_offset',
'SDMA_PKT_INDIRECT_HEADER_vmid_shift',
'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask',
'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset',
'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift',
'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask',
'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset',
'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift',
'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask',
'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset',
'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift',
'SDMA_PKT_MEM_INCR_HEADER_cpv_mask',
'SDMA_PKT_MEM_INCR_HEADER_cpv_offset',
'SDMA_PKT_MEM_INCR_HEADER_cpv_shift',
'SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask',
'SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset',
'SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift',
'SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask',
'SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset',
'SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift',
'SDMA_PKT_MEM_INCR_HEADER_op_mask',
'SDMA_PKT_MEM_INCR_HEADER_op_offset',
'SDMA_PKT_MEM_INCR_HEADER_op_shift',
'SDMA_PKT_MEM_INCR_HEADER_sub_op_mask',
'SDMA_PKT_MEM_INCR_HEADER_sub_op_offset',
'SDMA_PKT_MEM_INCR_HEADER_sub_op_shift',
'SDMA_PKT_NOP_DATA0_data0_mask',
'SDMA_PKT_NOP_DATA0_data0_offset',
'SDMA_PKT_NOP_DATA0_data0_shift',
'SDMA_PKT_NOP_HEADER_count_mask',
'SDMA_PKT_NOP_HEADER_count_offset',
'SDMA_PKT_NOP_HEADER_count_shift', 'SDMA_PKT_NOP_HEADER_op_mask',
'SDMA_PKT_NOP_HEADER_op_offset', 'SDMA_PKT_NOP_HEADER_op_shift',
'SDMA_PKT_NOP_HEADER_sub_op_mask',
'SDMA_PKT_NOP_HEADER_sub_op_offset',
'SDMA_PKT_NOP_HEADER_sub_op_shift',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset',
'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift',
'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask',
'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset',
'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift',
'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask',
'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset',
'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift',
'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask',
'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset',
'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift',
'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask',
'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset',
'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift',
'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask',
'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset',
'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift',
'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask',
'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset',
'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift',
'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask',
'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset',
'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift',
'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask',
'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset',
'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset',
'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift',
'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask',
'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset',
'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift',
'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask',
'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset',
'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift',
'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask',
'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset',
'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift',
'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask',
'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset',
'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift',
'SDMA_PKT_POLL_REGMEM',
'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask',
'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset',
'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift',
'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask',
'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset',
'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift',
'SDMA_PKT_POLL_REGMEM_DW5_interval_mask',
'SDMA_PKT_POLL_REGMEM_DW5_interval_offset',
'SDMA_PKT_POLL_REGMEM_DW5_interval_shift',
'SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask',
'SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset',
'SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift',
'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask',
'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset',
'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift',
'SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask',
'SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset',
'SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift',
'SDMA_PKT_POLL_REGMEM_HEADER_func_mask',
'SDMA_PKT_POLL_REGMEM_HEADER_func_offset',
'SDMA_PKT_POLL_REGMEM_HEADER_func_shift',
'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask',
'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset',
'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift',
'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask',
'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset',
'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift',
'SDMA_PKT_POLL_REGMEM_HEADER_op_mask',
'SDMA_PKT_POLL_REGMEM_HEADER_op_offset',
'SDMA_PKT_POLL_REGMEM_HEADER_op_shift',
'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask',
'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset',
'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift',
'SDMA_PKT_POLL_REGMEM_MASK_mask_mask',
'SDMA_PKT_POLL_REGMEM_MASK_mask_offset',
'SDMA_PKT_POLL_REGMEM_MASK_mask_shift',
'SDMA_PKT_POLL_REGMEM_VALUE_value_mask',
'SDMA_PKT_POLL_REGMEM_VALUE_value_offset',
'SDMA_PKT_POLL_REGMEM_VALUE_value_shift',
'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask',
'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset',
'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift',
'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask',
'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset',
'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift',
'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask',
'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset',
'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift',
'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask',
'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset',
'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift',
'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask',
'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset',
'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift',
'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask',
'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset',
'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift',
'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask',
'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset',
'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift',
'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask',
'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset',
'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift',
'SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask',
'SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset',
'SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift',
'SDMA_PKT_PRE_EXE_HEADER_op_mask',
'SDMA_PKT_PRE_EXE_HEADER_op_offset',
'SDMA_PKT_PRE_EXE_HEADER_op_shift',
'SDMA_PKT_PRE_EXE_HEADER_sub_op_mask',
'SDMA_PKT_PRE_EXE_HEADER_sub_op_offset',
'SDMA_PKT_PRE_EXE_HEADER_sub_op_shift',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset',
'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift',
'SDMA_PKT_PTEPDE_COPY_COUNT_count_mask',
'SDMA_PKT_PTEPDE_COPY_COUNT_count_offset',
'SDMA_PKT_PTEPDE_COPY_COUNT_count_shift',
'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask',
'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset',
'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift',
'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask',
'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset',
'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift',
'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask',
'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset',
'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift',
'SDMA_PKT_PTEPDE_COPY_HEADER_op_mask',
'SDMA_PKT_PTEPDE_COPY_HEADER_op_offset',
'SDMA_PKT_PTEPDE_COPY_HEADER_op_shift',
'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask',
'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset',
'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift',
'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask',
'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset',
'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift',
'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask',
'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset',
'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift',
'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask',
'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset',
'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift',
'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask',
'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset',
'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift',
'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask',
'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset',
'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift',
'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask',
'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset',
'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift',
'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask',
'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset',
'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift',
'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask',
'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset',
'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift',
'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask',
'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset',
'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift',
'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask',
'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset',
'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift',
'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask',
'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset',
'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift',
'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask',
'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset',
'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift',
'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask',
'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset',
'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift',
'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask',
'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset',
'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift',
'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask',
'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset',
'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift',
'SDMA_PKT_PTEPDE_RMW_HEADER_op_mask',
'SDMA_PKT_PTEPDE_RMW_HEADER_op_offset',
'SDMA_PKT_PTEPDE_RMW_HEADER_op_shift',
'SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask',
'SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset',
'SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift',
'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask',
'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset',
'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift',
'SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask',
'SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset',
'SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift',
'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask',
'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset',
'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift',
'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask',
'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset',
'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift',
'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask',
'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset',
'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift',
'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask',
'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset',
'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift',
'SDMA_PKT_REGISTER_RMW_ADDR_addr_mask',
'SDMA_PKT_REGISTER_RMW_ADDR_addr_offset',
'SDMA_PKT_REGISTER_RMW_ADDR_addr_shift',
'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask',
'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset',
'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift',
'SDMA_PKT_REGISTER_RMW_HEADER_op_mask',
'SDMA_PKT_REGISTER_RMW_HEADER_op_offset',
'SDMA_PKT_REGISTER_RMW_HEADER_op_shift',
'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask',
'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset',
'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift',
'SDMA_PKT_REGISTER_RMW_MASK_mask_mask',
'SDMA_PKT_REGISTER_RMW_MASK_mask_offset',
'SDMA_PKT_REGISTER_RMW_MASK_mask_shift',
'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask',
'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset',
'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift',
'SDMA_PKT_REGISTER_RMW_MISC_stride_mask',
'SDMA_PKT_REGISTER_RMW_MISC_stride_offset',
'SDMA_PKT_REGISTER_RMW_MISC_stride_shift',
'SDMA_PKT_REGISTER_RMW_VALUE_value_mask',
'SDMA_PKT_REGISTER_RMW_VALUE_value_offset',
'SDMA_PKT_REGISTER_RMW_VALUE_value_shift',
'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask',
'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset',
'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift',
'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask',
'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset',
'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift',
'SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask',
'SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset',
'SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift',
'SDMA_PKT_SEMAPHORE_HEADER_op_mask',
'SDMA_PKT_SEMAPHORE_HEADER_op_offset',
'SDMA_PKT_SEMAPHORE_HEADER_op_shift',
'SDMA_PKT_SEMAPHORE_HEADER_signal_mask',
'SDMA_PKT_SEMAPHORE_HEADER_signal_offset',
'SDMA_PKT_SEMAPHORE_HEADER_signal_shift',
'SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask',
'SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset',
'SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift',
'SDMA_PKT_SEMAPHORE_HEADER_write_one_mask',
'SDMA_PKT_SEMAPHORE_HEADER_write_one_offset',
'SDMA_PKT_SEMAPHORE_HEADER_write_one_shift',
'SDMA_PKT_SRBM_WRITE_ADDR_addr_mask',
'SDMA_PKT_SRBM_WRITE_ADDR_addr_offset',
'SDMA_PKT_SRBM_WRITE_ADDR_addr_shift',
'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask',
'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset',
'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift',
'SDMA_PKT_SRBM_WRITE_DATA_data_mask',
'SDMA_PKT_SRBM_WRITE_DATA_data_offset',
'SDMA_PKT_SRBM_WRITE_DATA_data_shift',
'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask',
'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset',
'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift',
'SDMA_PKT_SRBM_WRITE_HEADER_op_mask',
'SDMA_PKT_SRBM_WRITE_HEADER_op_offset',
'SDMA_PKT_SRBM_WRITE_HEADER_op_shift',
'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask',
'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset',
'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift', 'SDMA_PKT_TIMESTAMP',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset',
'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift',
'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask',
'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset',
'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift',
'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask',
'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset',
'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift',
'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask',
'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset',
'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift',
'SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask',
'SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset',
'SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift',
'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask',
'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset',
'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift',
'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask',
'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset',
'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift',
'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask',
'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset',
'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift',
'SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask',
'SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset',
'SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift',
'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask',
'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset',
'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift',
'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask',
'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset',
'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift',
'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask',
'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset',
'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift',
'SDMA_PKT_TRAP', 'SDMA_PKT_TRAP_HEADER_op_mask',
'SDMA_PKT_TRAP_HEADER_op_offset', 'SDMA_PKT_TRAP_HEADER_op_shift',
'SDMA_PKT_TRAP_HEADER_sub_op_mask',
'SDMA_PKT_TRAP_HEADER_sub_op_offset',
'SDMA_PKT_TRAP_HEADER_sub_op_shift',
'SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask',
'SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset',
'SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift',
'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask',
'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset',
'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift',
'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask',
'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset',
'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift',
'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask',
'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset',
'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift',
'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask',
'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset',
'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift',
'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask',
'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset',
'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift',
'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask',
'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset',
'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift',
'SDMA_PKT_VM_INVALIDATION_HEADER_op_mask',
'SDMA_PKT_VM_INVALIDATION_HEADER_op_offset',
'SDMA_PKT_VM_INVALIDATION_HEADER_op_shift',
'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask',
'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset',
'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift',
'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask',
'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset',
'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift',
'SDMA_PKT_WRITE_INCR_COUNT_count_mask',
'SDMA_PKT_WRITE_INCR_COUNT_count_offset',
'SDMA_PKT_WRITE_INCR_COUNT_count_shift',
'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask',
'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset',
'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift',
'SDMA_PKT_WRITE_INCR_HEADER_cpv_mask',
'SDMA_PKT_WRITE_INCR_HEADER_cpv_offset',
'SDMA_PKT_WRITE_INCR_HEADER_cpv_shift',
'SDMA_PKT_WRITE_INCR_HEADER_op_mask',
'SDMA_PKT_WRITE_INCR_HEADER_op_offset',
'SDMA_PKT_WRITE_INCR_HEADER_op_shift',
'SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask',
'SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset',
'SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift',
'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask',
'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset',
'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift',
'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask',
'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset',
'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift',
'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask',
'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset',
'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift',
'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask',
'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset',
'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift',
'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask',
'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset',
'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift',
'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask',
'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset',
'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift',
'SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask',
'SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset',
'SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift',
'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask',
'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset',
'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift',
'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift',
'SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask',
'SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset',
'SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift',
'SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask',
'SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset',
'SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift',
'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask',
'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset',
'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift',
'SDMA_PKT_WRITE_TILED_COUNT_count_mask',
'SDMA_PKT_WRITE_TILED_COUNT_count_offset',
'SDMA_PKT_WRITE_TILED_COUNT_count_shift',
'SDMA_PKT_WRITE_TILED_DATA0_data0_mask',
'SDMA_PKT_WRITE_TILED_DATA0_data0_offset',
'SDMA_PKT_WRITE_TILED_DATA0_data0_shift',
'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_WRITE_TILED_DW_3_width_mask',
'SDMA_PKT_WRITE_TILED_DW_3_width_offset',
'SDMA_PKT_WRITE_TILED_DW_3_width_shift',
'SDMA_PKT_WRITE_TILED_DW_4_depth_mask',
'SDMA_PKT_WRITE_TILED_DW_4_depth_offset',
'SDMA_PKT_WRITE_TILED_DW_4_depth_shift',
'SDMA_PKT_WRITE_TILED_DW_4_height_mask',
'SDMA_PKT_WRITE_TILED_DW_4_height_offset',
'SDMA_PKT_WRITE_TILED_DW_4_height_shift',
'SDMA_PKT_WRITE_TILED_DW_5_dimension_mask',
'SDMA_PKT_WRITE_TILED_DW_5_dimension_offset',
'SDMA_PKT_WRITE_TILED_DW_5_dimension_shift',
'SDMA_PKT_WRITE_TILED_DW_5_element_size_mask',
'SDMA_PKT_WRITE_TILED_DW_5_element_size_offset',
'SDMA_PKT_WRITE_TILED_DW_5_element_size_shift',
'SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask',
'SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset',
'SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift',
'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask',
'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset',
'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift',
'SDMA_PKT_WRITE_TILED_DW_6_x_mask',
'SDMA_PKT_WRITE_TILED_DW_6_x_offset',
'SDMA_PKT_WRITE_TILED_DW_6_x_shift',
'SDMA_PKT_WRITE_TILED_DW_6_y_mask',
'SDMA_PKT_WRITE_TILED_DW_6_y_offset',
'SDMA_PKT_WRITE_TILED_DW_6_y_shift',
'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask',
'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset',
'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift',
'SDMA_PKT_WRITE_TILED_DW_7_sw_mask',
'SDMA_PKT_WRITE_TILED_DW_7_sw_offset',
'SDMA_PKT_WRITE_TILED_DW_7_sw_shift',
'SDMA_PKT_WRITE_TILED_DW_7_z_mask',
'SDMA_PKT_WRITE_TILED_DW_7_z_offset',
'SDMA_PKT_WRITE_TILED_DW_7_z_shift',
'SDMA_PKT_WRITE_TILED_HEADER_cpv_mask',
'SDMA_PKT_WRITE_TILED_HEADER_cpv_offset',
'SDMA_PKT_WRITE_TILED_HEADER_cpv_shift',
'SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask',
'SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset',
'SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift',
'SDMA_PKT_WRITE_TILED_HEADER_op_mask',
'SDMA_PKT_WRITE_TILED_HEADER_op_offset',
'SDMA_PKT_WRITE_TILED_HEADER_op_shift',
'SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask',
'SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset',
'SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift',
'SDMA_PKT_WRITE_TILED_HEADER_tmz_mask',
'SDMA_PKT_WRITE_TILED_HEADER_tmz_offset',
'SDMA_PKT_WRITE_TILED_HEADER_tmz_shift',
'SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask',
'SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset',
'SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift',
'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask',
'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset',
'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift',
'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask',
'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset',
'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift',
'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask',
'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset',
'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift',
'SDMA_PKT_WRITE_UNTILED_DW_3_count_mask',
'SDMA_PKT_WRITE_UNTILED_DW_3_count_offset',
'SDMA_PKT_WRITE_UNTILED_DW_3_count_shift',
'SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask',
'SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset',
'SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift',
'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask',
'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset',
'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift',
'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask',
'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset',
'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift',
'SDMA_PKT_WRITE_UNTILED_HEADER_op_mask',
'SDMA_PKT_WRITE_UNTILED_HEADER_op_offset',
'SDMA_PKT_WRITE_UNTILED_HEADER_op_shift',
'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask',
'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset',
'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift',
'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask',
'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset',
'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift',
'SDMA_SUBOP_COPY_DIRTY_PAGE', 'SDMA_SUBOP_COPY_LINEAR',
'SDMA_SUBOP_COPY_LINEAR_BC', 'SDMA_SUBOP_COPY_LINEAR_PHY',
'SDMA_SUBOP_COPY_LINEAR_RECT', 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND',
'SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC',
'SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE', 'SDMA_SUBOP_COPY_SOA',
'SDMA_SUBOP_COPY_T2T_SUB_WIND', 'SDMA_SUBOP_COPY_T2T_SUB_WIND_BC',
'SDMA_SUBOP_COPY_TILED', 'SDMA_SUBOP_COPY_TILED_BC',
'SDMA_SUBOP_COPY_TILED_SUB_WIND',
'SDMA_SUBOP_COPY_TILED_SUB_WIND_BC', 'SDMA_SUBOP_DATA_FILL_MULTI',
'SDMA_SUBOP_MEM_INCR', 'SDMA_SUBOP_POLL_DBIT_WRITE_MEM',
'SDMA_SUBOP_POLL_MEM_VERIFY', 'SDMA_SUBOP_POLL_REG_WRITE_MEM',
'SDMA_SUBOP_PTEPDE_COPY', 'SDMA_SUBOP_PTEPDE_COPY_BACKWARDS',
'SDMA_SUBOP_PTEPDE_GEN', 'SDMA_SUBOP_PTEPDE_RMW',
'SDMA_SUBOP_TIMESTAMP_GET', 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL',
'SDMA_SUBOP_TIMESTAMP_SET', 'SDMA_SUBOP_USER_GCR',
'SDMA_SUBOP_VM_INVALIDATION', 'SDMA_SUBOP_WRITE_LINEAR',
'SDMA_SUBOP_WRITE_TILED', 'SDMA_SUBOP_WRITE_TILED_BC',
'SEC_GSP0_PRIORITY_HIGH', 'SEC_GSP0_PRIORITY_LOW', 'SEGMENTS_1',
'SEGMENTS_128', 'SEGMENTS_16', 'SEGMENTS_2', 'SEGMENTS_32',
'SEGMENTS_4', 'SEGMENTS_64', 'SEGMENTS_8', 'SEL_DTBCLK0',
'SEL_DTBCLK1', 'SEL_REFCLK0', 'SEM_ECC_ERROR', 'SEM_PERF_SEL',
'SEM_PERF_SEL_ACP_REQ_SIGNAL', 'SEM_PERF_SEL_ACP_REQ_WAIT',
'SEM_PERF_SEL_ATC_INVALIDATION', 'SEM_PERF_SEL_ATC_REQ',
'SEM_PERF_SEL_ATC_RET', 'SEM_PERF_SEL_ATC_VM_INVALIDATION',
'SEM_PERF_SEL_ATC_XNACK', 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL',
'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT',
'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL',
'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT',
'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL',
'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT',
'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL',
'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT',
'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT',
'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL',
'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT',
'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL',
'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT',
'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL',
'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT',
'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL',
'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT',
'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT',
'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E0_REQ_WAIT',
'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E1_REQ_WAIT',
'SEM_PERF_SEL_CYCLE', 'SEM_PERF_SEL_IDLE',
'SEM_PERF_SEL_ISP_REQ_SIGNAL', 'SEM_PERF_SEL_ISP_REQ_WAIT',
'SEM_PERF_SEL_MC_RD_REQ', 'SEM_PERF_SEL_MC_RD_RET',
'SEM_PERF_SEL_MC_WR_REQ', 'SEM_PERF_SEL_MC_WR_RET',
'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA0_REQ_WAIT',
'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA1_REQ_WAIT',
'SEM_PERF_SEL_SDMA2_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA2_REQ_WAIT',
'SEM_PERF_SEL_SDMA3_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA3_REQ_WAIT',
'SEM_PERF_SEL_UVD1_REQ_SIGNAL', 'SEM_PERF_SEL_UVD1_REQ_WAIT',
'SEM_PERF_SEL_UVD_REQ_SIGNAL', 'SEM_PERF_SEL_UVD_REQ_WAIT',
'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 'SEM_PERF_SEL_VCE0_REQ_WAIT',
'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 'SEM_PERF_SEL_VCE1_REQ_WAIT',
'SEM_PERF_SEL_VP8_REQ_SIGNAL', 'SEM_PERF_SEL_VP8_REQ_WAIT',
'SEM_RESP_FAILED', 'SEM_RESP_PASSED', 'SEM_TRANS_ERROR',
'SEND_AT_EARLIEST_TIME', 'SEND_AT_LINK_NUMBER',
'SEND_NORMAL_PACKET', 'SEND_PPS_PACKET', 'SET_SMU_MSG_INTR',
'SH_MEM_ADDRESS_MODE', 'SH_MEM_ADDRESS_MODE_32',
'SH_MEM_ADDRESS_MODE_64', 'SH_MEM_ALIGNMENT_MODE',
'SH_MEM_ALIGNMENT_MODE_DWORD',
'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT',
'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED',
'SIGNED', 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE',
'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START',
'SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE',
'SIMM16_WAITCNT_DEPCTR_SA_SDST_START',
'SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE',
'SIMM16_WAITCNT_DEPCTR_VA_SDST_START',
'SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE',
'SIMM16_WAITCNT_DEPCTR_VA_SSRC_START',
'SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE',
'SIMM16_WAITCNT_DEPCTR_VA_VCC_START',
'SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE',
'SIMM16_WAITCNT_DEPCTR_VA_VDST_START',
'SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE',
'SIMM16_WAITCNT_DEPCTR_VM_VSRC_START',
'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START',
'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START',
'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START',
'SIMM16_WAIT_EVENT_EXP_RDY_SIZE',
'SIMM16_WAIT_EVENT_EXP_RDY_START', 'SIZE_16K', 'SIZE_8K',
'SLVERR', 'SMUIO_BASE', 'SMUIO_BASE__INST0_SEG0',
'SMUIO_BASE__INST0_SEG1', 'SMUIO_BASE__INST0_SEG2',
'SMUIO_BASE__INST0_SEG3', 'SMUIO_BASE__INST0_SEG4',
'SMUIO_BASE__INST1_SEG0', 'SMUIO_BASE__INST1_SEG1',
'SMUIO_BASE__INST1_SEG2', 'SMUIO_BASE__INST1_SEG3',
'SMUIO_BASE__INST1_SEG4', 'SMUIO_BASE__INST2_SEG0',
'SMUIO_BASE__INST2_SEG1', 'SMUIO_BASE__INST2_SEG2',
'SMUIO_BASE__INST2_SEG3', 'SMUIO_BASE__INST2_SEG4',
'SMUIO_BASE__INST3_SEG0', 'SMUIO_BASE__INST3_SEG1',
'SMUIO_BASE__INST3_SEG2', 'SMUIO_BASE__INST3_SEG3',
'SMUIO_BASE__INST3_SEG4', 'SMUIO_BASE__INST4_SEG0',
'SMUIO_BASE__INST4_SEG1', 'SMUIO_BASE__INST4_SEG2',
'SMUIO_BASE__INST4_SEG3', 'SMUIO_BASE__INST4_SEG4',
'SMUIO_BASE__INST5_SEG0', 'SMUIO_BASE__INST5_SEG1',
'SMUIO_BASE__INST5_SEG2', 'SMUIO_BASE__INST5_SEG3',
'SMUIO_BASE__INST5_SEG4', 'SMUIO_BASE__INST6_SEG0',
'SMUIO_BASE__INST6_SEG1', 'SMUIO_BASE__INST6_SEG2',
'SMUIO_BASE__INST6_SEG3', 'SMUIO_BASE__INST6_SEG4', 'SMU_INTR',
'SMU_INTR_STATUS_CLEAR', 'SMU_INTR_STATUS_NOOP',
'SMU_MSG_INTR_NOOP', 'SM_MODE_RESERVED', 'SOFT_RESET',
'SOFT_RESET_0', 'SOFT_RESET_1', 'SO_VGTSTREAMOUT_FLUSH',
'SPI_FOG_EXP', 'SPI_FOG_EXP2', 'SPI_FOG_LINEAR', 'SPI_FOG_MODE',
'SPI_FOG_NONE', 'SPI_LB_WAVES_RSVD', 'SPI_LB_WAVES_SELECT',
'SPI_PERFCNT_SEL', 'SPI_PERF_BUSY', 'SPI_PERF_CSGN_BUSY',
'SPI_PERF_CSGN_CRAWLER_STALL', 'SPI_PERF_CSGN_EVENT_WAVE',
'SPI_PERF_CSGN_NUM_THREADGROUPS', 'SPI_PERF_CSGN_PWS_STALL',
'SPI_PERF_CSGN_WAVE', 'SPI_PERF_CSGN_WINDOW_VALID',
'SPI_PERF_CSN_BUSY', 'SPI_PERF_CSN_CRAWLER_STALL',
'SPI_PERF_CSN_EVENT_WAVE', 'SPI_PERF_CSN_NUM_THREADGROUPS',
'SPI_PERF_CSN_WAVE', 'SPI_PERF_CSN_WINDOW_VALID',
'SPI_PERF_EXPORT_DB0_STALL', 'SPI_PERF_EXPORT_DB1_STALL',
'SPI_PERF_EXPORT_DB2_STALL', 'SPI_PERF_EXPORT_DB3_STALL',
'SPI_PERF_EXPORT_DB4_STALL', 'SPI_PERF_EXPORT_DB5_STALL',
'SPI_PERF_EXPORT_DB6_STALL', 'SPI_PERF_EXPORT_DB7_STALL',
'SPI_PERF_EXPORT_SCB0_STALL', 'SPI_PERF_EXPORT_SCB1_STALL',
'SPI_PERF_EXPORT_SCB2_STALL', 'SPI_PERF_EXPORT_SCB3_STALL',
'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT',
'SPI_PERF_EXP_ARB_IDX_CNT', 'SPI_PERF_EXP_ARB_POS_CNT',
'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED',
'SPI_PERF_EXP_THROT_DOWNSTEP', 'SPI_PERF_EXP_THROT_UPSTEP',
'SPI_PERF_EXP_WITH_CONFLICT', 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR',
'SPI_PERF_GS_BUSY', 'SPI_PERF_GS_CRAWLER_STALL',
'SPI_PERF_GS_EVENT_WAVE', 'SPI_PERF_GS_EXP_DONE',
'SPI_PERF_GS_FIRST_SUBGRP', 'SPI_PERF_GS_HS_DEALLOC',
'SPI_PERF_GS_INDX0_STALL', 'SPI_PERF_GS_INDX1_STALL',
'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT',
'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC',
'SPI_PERF_GS_NGG_STALL_MSG_VAL', 'SPI_PERF_GS_PERS_UPD_FULL0',
'SPI_PERF_GS_PERS_UPD_FULL1', 'SPI_PERF_GS_POS0_STALL',
'SPI_PERF_GS_POS1_STALL', 'SPI_PERF_GS_PWS_STALL',
'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WINDOW_VALID',
'SPI_PERF_HS_BUSY', 'SPI_PERF_HS_CRAWLER_STALL',
'SPI_PERF_HS_EVENT_WAVE', 'SPI_PERF_HS_FIRST_WAVE',
'SPI_PERF_HS_OFFCHIP_LDS_STALL', 'SPI_PERF_HS_PERS_UPD_FULL0',
'SPI_PERF_HS_PERS_UPD_FULL1', 'SPI_PERF_HS_PWS_STALL',
'SPI_PERF_HS_WAVE', 'SPI_PERF_HS_WINDOW_VALID',
'SPI_PERF_NUM_EXPGRANT_EXPORTS',
'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS',
'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS',
'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS',
'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS',
'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS',
'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS',
'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS',
'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS',
'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS',
'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS',
'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS',
'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS',
'SPI_PERF_PIX_ALLOC_PEND_CNT', 'SPI_PERF_PS0_2_WAVE_GROUPS',
'SPI_PERF_PS0_ACTIVE', 'SPI_PERF_PS0_BUSY',
'SPI_PERF_PS0_CRAWLER_STALL', 'SPI_PERF_PS0_DEALLOC',
'SPI_PERF_PS0_EVENT_WAVE', 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT',
'SPI_PERF_PS0_OPT_WAVE', 'SPI_PERF_PS0_PRIM_BIN0',
'SPI_PERF_PS0_PRIM_BIN1', 'SPI_PERF_PS0_WAVE',
'SPI_PERF_PS0_WAVEID_STARVED',
'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY',
'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS0_WINDOW_VALID',
'SPI_PERF_PS1_2_WAVE_GROUPS', 'SPI_PERF_PS1_ACTIVE',
'SPI_PERF_PS1_BUSY', 'SPI_PERF_PS1_CRAWLER_STALL',
'SPI_PERF_PS1_DEALLOC', 'SPI_PERF_PS1_EVENT_WAVE',
'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS1_OPT_WAVE',
'SPI_PERF_PS1_PRIM_BIN0', 'SPI_PERF_PS1_PRIM_BIN1',
'SPI_PERF_PS1_WAVE', 'SPI_PERF_PS1_WAVEID_STARVED',
'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY',
'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS1_WINDOW_VALID',
'SPI_PERF_PS2_2_WAVE_GROUPS', 'SPI_PERF_PS2_ACTIVE',
'SPI_PERF_PS2_BUSY', 'SPI_PERF_PS2_CRAWLER_STALL',
'SPI_PERF_PS2_DEALLOC', 'SPI_PERF_PS2_EVENT_WAVE',
'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS2_OPT_WAVE',
'SPI_PERF_PS2_PRIM_BIN0', 'SPI_PERF_PS2_PRIM_BIN1',
'SPI_PERF_PS2_WAVE', 'SPI_PERF_PS2_WAVEID_STARVED',
'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY',
'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS2_WINDOW_VALID',
'SPI_PERF_PS3_2_WAVE_GROUPS', 'SPI_PERF_PS3_ACTIVE',
'SPI_PERF_PS3_BUSY', 'SPI_PERF_PS3_CRAWLER_STALL',
'SPI_PERF_PS3_DEALLOC', 'SPI_PERF_PS3_EVENT_WAVE',
'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS3_OPT_WAVE',
'SPI_PERF_PS3_PRIM_BIN0', 'SPI_PERF_PS3_PRIM_BIN1',
'SPI_PERF_PS3_WAVE', 'SPI_PERF_PS3_WAVEID_STARVED',
'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY',
'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS3_WINDOW_VALID',
'SPI_PERF_PS_EXP_ALLOC', 'SPI_PERF_PS_EXP_ARB_CONFLICT',
'SPI_PERF_PS_EXP_DONE', 'SPI_PERF_PS_PERS_UPD_FULL0',
'SPI_PERF_PS_PERS_UPD_FULL1', 'SPI_PERF_PS_PWS_STALL',
'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG',
'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN',
'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS',
'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS',
'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS',
'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG',
'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN',
'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS',
'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS',
'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS',
'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG',
'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN',
'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS',
'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS',
'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS',
'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG',
'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN',
'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS',
'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS',
'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', 'SPI_PERF_RA_BAR_CU_FULL_CSG',
'SPI_PERF_RA_BAR_CU_FULL_CSN', 'SPI_PERF_RA_BAR_CU_FULL_HS',
'SPI_PERF_RA_BULKY_CU_FULL_CSG', 'SPI_PERF_RA_BULKY_CU_FULL_CSN',
'SPI_PERF_RA_CSC_UNDER_TUNNEL', 'SPI_PERF_RA_CSG_LOCK',
'SPI_PERF_RA_CSN_LOCK', 'SPI_PERF_RA_GFX_UNDER_TUNNEL',
'SPI_PERF_RA_GS_LOCK', 'SPI_PERF_RA_HS_LOCK',
'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN',
'SPI_PERF_RA_LDS_CU_FULL_GS', 'SPI_PERF_RA_LDS_CU_FULL_HS',
'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_PIPE_REQ_BIN2',
'SPI_PERF_RA_PRE_ALLOC_STALL', 'SPI_PERF_RA_REQ_NO_ALLOC',
'SPI_PERF_RA_REQ_NO_ALLOC_CSG', 'SPI_PERF_RA_REQ_NO_ALLOC_CSN',
'SPI_PERF_RA_REQ_NO_ALLOC_GS', 'SPI_PERF_RA_REQ_NO_ALLOC_HS',
'SPI_PERF_RA_REQ_NO_ALLOC_PS', 'SPI_PERF_RA_RES_STALL_CSG',
'SPI_PERF_RA_RES_STALL_CSN', 'SPI_PERF_RA_RES_STALL_GS',
'SPI_PERF_RA_RES_STALL_HS', 'SPI_PERF_RA_RES_STALL_PS',
'SPI_PERF_RA_RSV_UPD', 'SPI_PERF_RA_TASK_REQ_BIN3',
'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN',
'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN',
'SPI_PERF_RA_TMP_STALL_GS', 'SPI_PERF_RA_TMP_STALL_HS',
'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG',
'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_GS',
'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS',
'SPI_PERF_RA_WAVE_SIMD_FULL_CSG',
'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_GS',
'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS',
'SPI_PERF_RA_WR_CTL_FULL', 'SPI_PERF_RA_WVALLOC_STALL',
'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN',
'SPI_PERF_RA_WVLIM_STALL_GS', 'SPI_PERF_RA_WVLIM_STALL_HS',
'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_SWC_CSGN_WR',
'SPI_PERF_SWC_CSN_WR', 'SPI_PERF_SWC_GS_WR', 'SPI_PERF_SWC_HS_WR',
'SPI_PERF_SWC_PS_WR', 'SPI_PERF_VWC_CSGN_WR',
'SPI_PERF_VWC_CSN_WR', 'SPI_PERF_VWC_ES_WR', 'SPI_PERF_VWC_GS_WR',
'SPI_PERF_VWC_HS_WR', 'SPI_PERF_VWC_LS_WR', 'SPI_PERF_VWC_PS_WR',
'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0',
'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE',
'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T',
'SPI_PS_LDS_GROUP_1', 'SPI_PS_LDS_GROUP_2', 'SPI_PS_LDS_GROUP_4',
'SPI_PS_LDS_GROUP_SIZE', 'SPI_SAMPLE_CNTL', 'SPI_SHADER_1COMP',
'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', 'SPI_SHADER_32_AR',
'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', 'SPI_SHADER_4COMP',
'SPI_SHADER_4COMPRESS', 'SPI_SHADER_EX_FORMAT',
'SPI_SHADER_FORMAT', 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE',
'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR',
'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR',
'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN',
'SP_PERF_SEL_DST_BUF_ALLOC_STALL',
'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', 'SP_PERF_SEL_DST_BUF_ODD_DIRTY',
'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI',
'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', 'SP_PERF_SEL_DUMMY_LAST',
'SP_PERF_SEL_SRC_CACHE_HIT_B0', 'SP_PERF_SEL_SRC_CACHE_HIT_B1',
'SP_PERF_SEL_SRC_CACHE_HIT_B2', 'SP_PERF_SEL_SRC_CACHE_HIT_B3',
'SP_PERF_SEL_SRC_CACHE_PROBE_B0',
'SP_PERF_SEL_SRC_CACHE_PROBE_B1',
'SP_PERF_SEL_SRC_CACHE_PROBE_B2',
'SP_PERF_SEL_SRC_CACHE_PROBE_B3',
'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0',
'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1',
'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2',
'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3',
'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0',
'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1',
'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2',
'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3',
'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0',
'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1',
'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2',
'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3',
'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS',
'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE',
'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY',
'SP_PERF_SEL_VALU_OPERAND',
'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF',
'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL',
'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', 'SP_PERF_SEL_VALU_STALL',
'SP_PERF_SEL_VALU_STALL_DST_STALL',
'SP_PERF_SEL_VALU_STALL_SDST_FWD',
'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY',
'SP_PERF_SEL_VALU_STALL_VDST_FWD',
'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY',
'SP_PERF_SEL_VALU_VGPR_OPERAND', 'SP_PERF_SEL_VGPR_EXP_RD',
'SP_PERF_SEL_VGPR_RD', 'SP_PERF_SEL_VGPR_SPI_WR',
'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', 'SP_PERF_SEL_VGPR_VMEM_RD',
'SP_PERF_SEL_VGPR_WR', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES',
'SQC_PERF_SEL_DCACHE_CACHE_STALLED',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX',
'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT',
'SQC_PERF_SEL_DCACHE_FLAT_REQ', 'SQC_PERF_SEL_DCACHE_GCR',
'SQC_PERF_SEL_DCACHE_GCR_HITS',
'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_DCACHE_HITS',
'SQC_PERF_SEL_DCACHE_HIT_LRU_READ',
'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL',
'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT',
'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB',
'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB',
'SQC_PERF_SEL_DCACHE_INVAL_ASYNC',
'SQC_PERF_SEL_DCACHE_INVAL_INST', 'SQC_PERF_SEL_DCACHE_MISSES',
'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_DCACHE_REQ',
'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE',
'SQC_PERF_SEL_DCACHE_REQ_READ_1',
'SQC_PERF_SEL_DCACHE_REQ_READ_16',
'SQC_PERF_SEL_DCACHE_REQ_READ_2',
'SQC_PERF_SEL_DCACHE_REQ_READ_4',
'SQC_PERF_SEL_DCACHE_REQ_READ_8',
'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL',
'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT',
'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL',
'SQC_PERF_SEL_DUMMY_LAST', 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES',
'SQC_PERF_SEL_ICACHE_CACHE_STALLED',
'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX',
'SQC_PERF_SEL_ICACHE_GCR', 'SQC_PERF_SEL_ICACHE_GCR_HITS',
'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_ICACHE_HITS',
'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL',
'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT',
'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB',
'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB',
'SQC_PERF_SEL_ICACHE_INVAL_ASYNC',
'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES',
'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_ICACHE_REQ',
'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT',
'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL',
'SQC_PERF_SEL_LDS_ADDR_ACTIVE', 'SQC_PERF_SEL_LDS_ADDR_CONFLICT',
'SQC_PERF_SEL_LDS_ADDR_STALL', 'SQC_PERF_SEL_LDS_ATOMIC_RETURN',
'SQC_PERF_SEL_LDS_BANK_CONFLICT',
'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', 'SQC_PERF_SEL_LDS_IDX_ACTIVE',
'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL',
'SQC_PERF_SEL_LDS_MEM_VIOLATIONS',
'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD',
'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD',
'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL',
'SQC_PERF_SEL_LDS_UNALIGNED_STALL', 'SQC_PERF_SEL_LDS_VGPR_BUSY',
'SQC_PERF_SEL_SQ_DCACHE_REQS', 'SQC_PERF_SEL_TC_DATA_READ_REQ',
'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ',
'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL',
'SQC_PERF_SEL_TC_STARVE', 'SQC_PERF_SEL_TD_VGPR_BUSY',
'SQDEC_BEGIN', 'SQDEC_END', 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END',
'SQG_PERF_SEL', 'SQG_PERF_SEL_ACCUM_PREV',
'SQG_PERF_SEL_BUSY_CYCLES', 'SQG_PERF_SEL_CYCLES',
'SQG_PERF_SEL_DUMMY_LAST', 'SQG_PERF_SEL_EVENTS',
'SQG_PERF_SEL_EXP_BUS0_BUSY', 'SQG_PERF_SEL_EXP_BUS1_BUSY',
'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY',
'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', 'SQG_PERF_SEL_ITEMS',
'SQG_PERF_SEL_LEVEL_WAVES', 'SQG_PERF_SEL_MSG',
'SQG_PERF_SEL_MSG_BUS_BUSY', 'SQG_PERF_SEL_MSG_INTERRUPT',
'SQG_PERF_SEL_NONE', 'SQG_PERF_SEL_PS_QUADS',
'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS',
'SQG_PERF_SEL_TTRACE_LOST_PACKETS', 'SQG_PERF_SEL_TTRACE_REQS',
'SQG_PERF_SEL_TTRACE_STALL', 'SQG_PERF_SEL_WAVE32_ITEMS',
'SQG_PERF_SEL_WAVE64_ITEMS', 'SQG_PERF_SEL_WAVES',
'SQG_PERF_SEL_WAVES_32', 'SQG_PERF_SEL_WAVES_64',
'SQG_PERF_SEL_WAVES_EQ_32', 'SQG_PERF_SEL_WAVES_EQ_64',
'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', 'SQG_PERF_SEL_WAVES_LT_16',
'SQG_PERF_SEL_WAVES_LT_32', 'SQG_PERF_SEL_WAVES_LT_48',
'SQG_PERF_SEL_WAVES_LT_64', 'SQG_PERF_SEL_WAVES_RESTORED',
'SQG_PERF_SEL_WAVES_SAVED', 'SQG_PERF_SEL_WAVE_CYCLES',
'SQIND_GLOBAL_REGS_OFFSET', 'SQIND_GLOBAL_REGS_SIZE',
'SQIND_LOCAL_REGS_OFFSET', 'SQIND_LOCAL_REGS_SIZE',
'SQIND_WAVE_HWREGS_OFFSET', 'SQIND_WAVE_HWREGS_SIZE',
'SQIND_WAVE_SGPRS_OFFSET', 'SQIND_WAVE_SGPRS_SIZE',
'SQIND_WAVE_VGPRS_OFFSET', 'SQIND_WAVE_VGPRS_SIZE',
'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', 'SQPERFSDEC_BEGIN',
'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', 'SQPWRDEC_END',
'SQ_CAC_POWER_ALU_BUSY', 'SQ_CAC_POWER_GPR_RD',
'SQ_CAC_POWER_GPR_WR', 'SQ_CAC_POWER_LDS_BUSY',
'SQ_CAC_POWER_SEL', 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU',
'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2',
'SQ_DISPATCHER_GFX_CNT_PER_RING', 'SQ_DISPATCHER_GFX_MIN',
'SQ_EDC_FUE_CNTL_LDS', 'SQ_EDC_FUE_CNTL_SIMD0',
'SQ_EDC_FUE_CNTL_SIMD1', 'SQ_EDC_FUE_CNTL_SIMD2',
'SQ_EDC_FUE_CNTL_SIMD3', 'SQ_EDC_FUE_CNTL_SQ',
'SQ_EDC_FUE_CNTL_TA', 'SQ_EDC_FUE_CNTL_TCP', 'SQ_EDC_FUE_CNTL_TD',
'SQ_EDC_INFO_SOURCE', 'SQ_EDC_INFO_SOURCE_GDS',
'SQ_EDC_INFO_SOURCE_INST', 'SQ_EDC_INFO_SOURCE_INVALID',
'SQ_EDC_INFO_SOURCE_LDS', 'SQ_EDC_INFO_SOURCE_SGPR',
'SQ_EDC_INFO_SOURCE_TA', 'SQ_EDC_INFO_SOURCE_VGPR',
'SQ_EX_MODE_EXCP_ADDR_WATCH0', 'SQ_EX_MODE_EXCP_DIV0',
'SQ_EX_MODE_EXCP_HI_ADDR_WATCH1',
'SQ_EX_MODE_EXCP_HI_ADDR_WATCH2',
'SQ_EX_MODE_EXCP_HI_ADDR_WATCH3', 'SQ_EX_MODE_EXCP_INEXACT',
'SQ_EX_MODE_EXCP_INPUT_DENORM', 'SQ_EX_MODE_EXCP_INT_DIV0',
'SQ_EX_MODE_EXCP_INVALID', 'SQ_EX_MODE_EXCP_MEM_VIOL',
'SQ_EX_MODE_EXCP_OVERFLOW', 'SQ_EX_MODE_EXCP_UNDERFLOW',
'SQ_EX_MODE_EXCP_VALU_BASE', 'SQ_EX_MODE_EXCP_VALU_SIZE',
'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT',
'SQ_IBUF_IB_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_DRET',
'SQ_IBUF_IB_EMPTY_WAIT_GNT', 'SQ_IBUF_IB_IDLE',
'SQ_IBUF_IB_INI_WAIT_DRET', 'SQ_IBUF_IB_INI_WAIT_GNT',
'SQ_IBUF_IB_LE_4DW', 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST',
'SQ_IMG_FILTER_MODE_BLEND', 'SQ_IMG_FILTER_MODE_MAX',
'SQ_IMG_FILTER_MODE_MIN', 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD',
'SQ_IND_CMD_CMD_KILL', 'SQ_IND_CMD_CMD_NULL',
'SQ_IND_CMD_CMD_SAVECTX', 'SQ_IND_CMD_CMD_SETFATALHALT',
'SQ_IND_CMD_CMD_SETHALT', 'SQ_IND_CMD_CMD_SET_SPI_PRIO',
'SQ_IND_CMD_CMD_SINGLE_STEP', 'SQ_IND_CMD_CMD_TRAP',
'SQ_IND_CMD_CMD_TRAP_AFTER_INST', 'SQ_IND_CMD_MODE',
'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME',
'SQ_IND_CMD_MODE_BROADCAST_PIPE',
'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE',
'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV',
'SQ_INST_STR_IB_WAVE_INST_SKIP_AV',
'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV',
'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML',
'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', 'SQ_INST_STR_ST',
'SQ_INST_TYPE', 'SQ_INST_TYPE_BARRIER',
'SQ_INST_TYPE_BRANCH_NOT_TAKEN', 'SQ_INST_TYPE_BRANCH_TAKEN',
'SQ_INST_TYPE_EXP', 'SQ_INST_TYPE_JUMP', 'SQ_INST_TYPE_LDS',
'SQ_INST_TYPE_LDS_DIRECT', 'SQ_INST_TYPE_MSG',
'SQ_INST_TYPE_NONE', 'SQ_INST_TYPE_OTHER', 'SQ_INST_TYPE_SCALAR',
'SQ_INST_TYPE_TEX', 'SQ_INST_TYPE_VALU', 'SQ_LLC_0', 'SQ_LLC_1',
'SQ_LLC_BYPASS', 'SQ_LLC_CTL', 'SQ_LLC_RSVD_2',
'SQ_MAX_PGM_SGPRS', 'SQ_MAX_PGM_VGPRS', 'SQ_NON_EVENT',
'SQ_NO_INST_ISSUE', 'SQ_NO_INST_ISSUE_ALU_DEP',
'SQ_NO_INST_ISSUE_BARRIER_WAIT', 'SQ_NO_INST_ISSUE_NO_ARB_WIN',
'SQ_NO_INST_ISSUE_NO_INSTS', 'SQ_NO_INST_ISSUE_OTHER',
'SQ_NO_INST_ISSUE_SLEEP_WAIT', 'SQ_NO_INST_ISSUE_S_WAITCNT',
'SQ_OOB_COMPLETE', 'SQ_OOB_INDEX_AND_OFFSET', 'SQ_OOB_INDEX_ONLY',
'SQ_OOB_NUM_RECORDS_0', 'SQ_OOB_SELECT', 'SQ_PERF_SEL',
'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_BUSY_CYCLES',
'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END',
'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS',
'SQ_PERF_SEL_EXP_BUS0_BUSY', 'SQ_PERF_SEL_EXP_BUS1_BUSY',
'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY',
'SQ_PERF_SEL_EXP_REQ_BUS_STALL', 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL',
'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_REQS',
'SQ_PERF_SEL_INSTS_ALL', 'SQ_PERF_SEL_INSTS_BRANCH',
'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN',
'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN',
'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS',
'SQ_PERF_SEL_INSTS_DELAY_ALU',
'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', 'SQ_PERF_SEL_INSTS_EXP',
'SQ_PERF_SEL_INSTS_EXP_GDS', 'SQ_PERF_SEL_INSTS_FLAT',
'SQ_PERF_SEL_INSTS_GDS', 'SQ_PERF_SEL_INSTS_INTERNAL',
'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD',
'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', 'SQ_PERF_SEL_INSTS_SALU',
'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM',
'SQ_PERF_SEL_INSTS_SMEM_NORM', 'SQ_PERF_SEL_INSTS_TEX',
'SQ_PERF_SEL_INSTS_TEX_LOAD', 'SQ_PERF_SEL_INSTS_TEX_STORE',
'SQ_PERF_SEL_INSTS_VALU', 'SQ_PERF_SEL_INSTS_VALU_1_PASS',
'SQ_PERF_SEL_INSTS_VALU_2_PASS', 'SQ_PERF_SEL_INSTS_VALU_4_PASS',
'SQ_PERF_SEL_INSTS_VALU_DP',
'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED',
'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC',
'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64',
'SQ_PERF_SEL_INSTS_VALU_TRANS', 'SQ_PERF_SEL_INSTS_VALU_TRANS32',
'SQ_PERF_SEL_INSTS_VALU_VINTERP',
'SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP',
'SQ_PERF_SEL_INSTS_WAVE32', 'SQ_PERF_SEL_INSTS_WAVE32_FLAT',
'SQ_PERF_SEL_INSTS_WAVE32_LDS',
'SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD',
'SQ_PERF_SEL_INSTS_WAVE32_TEX',
'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD',
'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE',
'SQ_PERF_SEL_INSTS_WAVE32_VALU',
'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC',
'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32',
'SQ_PERF_SEL_INST_CACHE_REQ_STALL', 'SQ_PERF_SEL_INST_CYCLES_EXP',
'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', 'SQ_PERF_SEL_INST_CYCLES_FLAT',
'SQ_PERF_SEL_INST_CYCLES_GDS', 'SQ_PERF_SEL_INST_CYCLES_LDS',
'SQ_PERF_SEL_INST_CYCLES_TEX', 'SQ_PERF_SEL_INST_CYCLES_VALU',
'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC',
'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32',
'SQ_PERF_SEL_INST_CYCLES_VMEM',
'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD',
'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE',
'SQ_PERF_SEL_INST_LEVEL_EXP', 'SQ_PERF_SEL_INST_LEVEL_GDS',
'SQ_PERF_SEL_INST_LEVEL_LDS', 'SQ_PERF_SEL_INST_LEVEL_SMEM',
'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD',
'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', 'SQ_PERF_SEL_ITEMS',
'SQ_PERF_SEL_ITEMS_MAX_VALU', 'SQ_PERF_SEL_ITEMS_VALU',
'SQ_PERF_SEL_ITEM_CYCLES_VALU', 'SQ_PERF_SEL_ITEM_CYCLES_VMEM',
'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL',
'SQ_PERF_SEL_LEVEL_WAVES', 'SQ_PERF_SEL_MSG',
'SQ_PERF_SEL_MSG_BUS_BUSY', 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL',
'SQ_PERF_SEL_MSG_INTERRUPT', 'SQ_PERF_SEL_NONE',
'SQ_PERF_SEL_NONE2', 'SQ_PERF_SEL_OVERFLOW_PREV',
'SQ_PERF_SEL_PS_QUADS', 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL',
'SQ_PERF_SEL_SALU_PIPE_STALL', 'SQ_PERF_SEL_SALU_SGATHER_STALL',
'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL',
'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL',
'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES',
'SQ_PERF_SEL_SP_CONST_CYCLES',
'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', 'SQ_PERF_SEL_USER0',
'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11',
'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14',
'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3',
'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6',
'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9',
'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1',
'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11',
'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13',
'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15',
'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3',
'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5',
'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7',
'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9',
'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL',
'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES',
'SQ_PERF_SEL_VALU_RETURN_SDST',
'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL',
'SQ_PERF_SEL_VALU_SGATHER_STALL',
'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL',
'SQ_PERF_SEL_VALU_STARVE', 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL',
'SQ_PERF_SEL_VMEM_BUS_ACTIVE', 'SQ_PERF_SEL_VMEM_BUS_STALL',
'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL',
'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL',
'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL',
'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL',
'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY',
'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY',
'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT',
'SQ_PERF_SEL_WAIT_ANY', 'SQ_PERF_SEL_WAIT_BARRIER',
'SQ_PERF_SEL_WAIT_CNT_ANY', 'SQ_PERF_SEL_WAIT_CNT_EXP',
'SQ_PERF_SEL_WAIT_CNT_LGKM', 'SQ_PERF_SEL_WAIT_CNT_VMVS',
'SQ_PERF_SEL_WAIT_DELAY_ALU', 'SQ_PERF_SEL_WAIT_DEPCTR',
'SQ_PERF_SEL_WAIT_EXP_ALLOC', 'SQ_PERF_SEL_WAIT_IFETCH',
'SQ_PERF_SEL_WAIT_INST_ANY', 'SQ_PERF_SEL_WAIT_INST_BR_MSG',
'SQ_PERF_SEL_WAIT_INST_EXP_GDS', 'SQ_PERF_SEL_WAIT_INST_FLAT',
'SQ_PERF_SEL_WAIT_INST_LDS', 'SQ_PERF_SEL_WAIT_INST_SCA',
'SQ_PERF_SEL_WAIT_INST_TEX', 'SQ_PERF_SEL_WAIT_INST_VALU',
'SQ_PERF_SEL_WAIT_INST_VMEM', 'SQ_PERF_SEL_WAIT_OTHER',
'SQ_PERF_SEL_WAIT_SLEEP', 'SQ_PERF_SEL_WAIT_TTRACE',
'SQ_PERF_SEL_WAVE32_INSTS', 'SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS',
'SQ_PERF_SEL_WAVE32_ITEMS', 'SQ_PERF_SEL_WAVE64_HALF_SKIP',
'SQ_PERF_SEL_WAVE64_INSTS', 'SQ_PERF_SEL_WAVE64_ITEMS',
'SQ_PERF_SEL_WAVES', 'SQ_PERF_SEL_WAVES_32',
'SQ_PERF_SEL_WAVES_64', 'SQ_PERF_SEL_WAVES_EQ_32',
'SQ_PERF_SEL_WAVES_EQ_64', 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH',
'SQ_PERF_SEL_WAVES_LT_16', 'SQ_PERF_SEL_WAVES_LT_32',
'SQ_PERF_SEL_WAVES_LT_48', 'SQ_PERF_SEL_WAVES_LT_64',
'SQ_PERF_SEL_WAVES_RESTORED', 'SQ_PERF_SEL_WAVES_SAVED',
'SQ_PERF_SEL_WAVE_CYCLES', 'SQ_PERF_SEL_WAVE_READY',
'SQ_ROUND_MINUS_INFINITY', 'SQ_ROUND_MODE',
'SQ_ROUND_NEAREST_EVEN', 'SQ_ROUND_PLUS_INFINITY',
'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', 'SQ_RSRC_BUF_RSVD_1',
'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', 'SQ_RSRC_BUF_TYPE',
'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', 'SQ_RSRC_FLAT_RSVD_2',
'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', 'SQ_RSRC_IMG_1D',
'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', 'SQ_RSRC_IMG_2D_ARRAY',
'SQ_RSRC_IMG_2D_MSAA', 'SQ_RSRC_IMG_2D_MSAA_ARRAY',
'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', 'SQ_RSRC_IMG_RSVD_0',
'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', 'SQ_RSRC_IMG_RSVD_3',
'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', 'SQ_RSRC_IMG_RSVD_6',
'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', 'SQ_SEL_0', 'SQ_SEL_1',
'SQ_SEL_N_BC_1', 'SQ_SEL_RESERVED_1', 'SQ_SEL_W', 'SQ_SEL_X',
'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', 'SQ_TEX_ANISO_RATIO',
'SQ_TEX_ANISO_RATIO_1', 'SQ_TEX_ANISO_RATIO_16',
'SQ_TEX_ANISO_RATIO_2', 'SQ_TEX_ANISO_RATIO_4',
'SQ_TEX_ANISO_RATIO_8', 'SQ_TEX_BORDER_COLOR',
'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK',
'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE',
'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK',
'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER',
'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE',
'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL',
'SQ_TEX_DEPTH_COMPARE_GREATER',
'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS',
'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER',
'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER',
'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE',
'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ',
'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER',
'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL',
'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER',
'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT',
'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT',
'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR',
'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT',
'SQ_TT_INST_EXCLUDE_EXPGNT234_BIT',
'SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT',
'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT',
'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT', 'SQ_TT_MODE',
'SQ_TT_MODE_DETAIL', 'SQ_TT_MODE_GLOBAL', 'SQ_TT_MODE_OFF',
'SQ_TT_MODE_ON', 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT',
'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT',
'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT',
'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT',
'SQ_TT_REG_EXCLUDE_USER_DATA_BIT',
'SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT', 'SQ_TT_RT_FREQ',
'SQ_TT_RT_FREQ_1024_CLK', 'SQ_TT_RT_FREQ_4096_CLK',
'SQ_TT_RT_FREQ_NEVER', 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT',
'SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT',
'SQ_TT_TOKEN_MASK_ALL_BIT', 'SQ_TT_TOKEN_MASK_ALL_SHIFT',
'SQ_TT_TOKEN_MASK_COMP_BIT', 'SQ_TT_TOKEN_MASK_COMP_SHIFT',
'SQ_TT_TOKEN_MASK_CONFIG_BIT', 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT',
'SQ_TT_TOKEN_MASK_CONTEXT_BIT', 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT',
'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT',
'SQ_TT_TOKEN_MASK_INST_EXCLUDE',
'SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT',
'SQ_TT_TOKEN_MASK_REG_EXCLUDE',
'SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT',
'SQ_TT_TOKEN_MASK_REG_INCLUDE',
'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT', 'SQ_TT_TOKEN_MASK_RSVD_BIT',
'SQ_TT_TOKEN_MASK_RSVD_SHIFT', 'SQ_TT_TOKEN_MASK_SHDEC_BIT',
'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', 'SQ_TT_TOKEN_MASK_SQDEC_BIT',
'SQ_TT_TOKEN_MASK_SQDEC_SHIFT',
'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT', 'SQ_TT_UTIL_TIMER',
'SQ_TT_UTIL_TIMER_100_CLK', 'SQ_TT_UTIL_TIMER_250_CLK',
'SQ_TT_WAVESTART_MODE', 'SQ_TT_WAVESTART_MODE_ALLOC',
'SQ_TT_WAVESTART_MODE_PBB_ID', 'SQ_TT_WAVESTART_MODE_SHORT',
'SQ_TT_WTYPE_INCLUDE', 'SQ_TT_WTYPE_INCLUDE_CS_BIT',
'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_GS_BIT',
'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_HS_BIT',
'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_PS_BIT',
'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_RSVD0_BIT',
'SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT',
'SQ_TT_WTYPE_INCLUDE_RSVD1_BIT',
'SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT',
'SQ_TT_WTYPE_INCLUDE_RSVD2_BIT',
'SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT', 'SQ_TT_WTYPE_INCLUDE_SHIFT',
'SQ_WATCH_MODES', 'SQ_WATCH_MODE_ALL', 'SQ_WATCH_MODE_ATOMIC',
'SQ_WATCH_MODE_NONREAD', 'SQ_WATCH_MODE_READ',
'SQ_WAVE_FWD_PROG_INTERVAL', 'SQ_WAVE_FWD_PROG_INTERVAL_1024',
'SQ_WAVE_FWD_PROG_INTERVAL_256', 'SQ_WAVE_FWD_PROG_INTERVAL_4096',
'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', 'SQ_WAVE_IB_DEP_HOLD_CNT_SIZE',
'SQ_WAVE_IB_DEP_LDS_DIR_SIZE', 'SQ_WAVE_IB_DEP_SA_EXEC_SIZE',
'SQ_WAVE_IB_DEP_SA_M0_SIZE', 'SQ_WAVE_IB_DEP_SA_SDST_SIZE',
'SQ_WAVE_IB_DEP_VA_EXEC_SIZE', 'SQ_WAVE_IB_DEP_VA_SDST_SIZE',
'SQ_WAVE_IB_DEP_VA_SSRC_SIZE', 'SQ_WAVE_IB_DEP_VA_VCC_SIZE',
'SQ_WAVE_IB_DEP_VA_VDST_SIZE', 'SQ_WAVE_IB_DEP_VM_VSRC_SIZE',
'SQ_WAVE_IB_ECC_CLEAN', 'SQ_WAVE_IB_ECC_ERR_CONTINUE',
'SQ_WAVE_IB_ECC_ERR_HALT', 'SQ_WAVE_IB_ECC_ST',
'SQ_WAVE_IB_ECC_WITH_ERR_MSG', 'SQ_WAVE_SCHED_MODES',
'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', 'SQ_WAVE_SCHED_MODE_EXPERT',
'SQ_WAVE_SCHED_MODE_NORMAL', 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS',
'SQ_WAVE_TYPE_GS', 'SQ_WAVE_TYPE_HS', 'SQ_WAVE_TYPE_PS',
'SQ_WAVE_TYPE_PS0', 'SQ_WAVE_TYPE_PS1', 'SQ_WAVE_TYPE_PS2',
'SQ_WAVE_TYPE_PS3', 'SQ_WAVE_TYPE_RSVD0', 'SQ_WAVE_TYPE_RSVD1',
'SQ_WAVE_TYPE_RSVD2', 'SRCID_NONSECURE_CP',
'SRCID_NONSECURE_CP_RCIU', 'SRCID_RLC', 'SRCID_RLCV',
'SRCID_SECURE_CP', 'SRCID_SECURE_CP_RCIU', 'STALL',
'STENCIL_ADD_CLAMP', 'STENCIL_ADD_WRAP', 'STENCIL_AND',
'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR',
'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP',
'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP',
'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO',
'STREAM_0_SYNCHRONIZATION',
'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_10_SYNCHRONIZATION',
'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_11_SYNCHRONIZATION',
'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_12_SYNCHRONIZATION',
'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_13_SYNCHRONIZATION',
'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_14_SYNCHRONIZATION',
'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_15_SYNCHRONIZATION',
'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_1_SYNCHRONIZATION',
'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_2_SYNCHRONIZATION',
'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_3_SYNCHRONIZATION',
'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED',
'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED',
'STREAM_4_SYNCHRONIZATION',
'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_5_SYNCHRONIZATION',
'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_6_SYNCHRONIZATION',
'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_7_SYNCHRONIZATION',
'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_8_SYNCHRONIZATION',
'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_9_SYNCHRONIZATION',
'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED',
'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED',
'STREAM_DSC_444_RGB', 'STREAM_DSC_DISABLE',
'STREAM_DSC_NATIVE_422_420', 'STREAM_ODM_COMBINE_1_SEGMENT',
'STREAM_ODM_COMBINE_2_SEGMENT', 'STREAM_ODM_COMBINE_4_SEGMENT',
'STREAM_ODM_COMBINE_RESERVED', 'STREAM_PIXEL_ENCODING_420',
'STREAM_PIXEL_ENCODING_422', 'STREAM_PIXEL_ENCODING_444_RGB',
'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM',
'STRM_PERFMON_STATE_DISABLE_AND_RESET',
'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM',
'STRM_PERFMON_STATE_RESERVED_3',
'STRM_PERFMON_STATE_START_COUNTING',
'STRM_PERFMON_STATE_STOP_COUNTING', 'SURFACE_DCC',
'SURFACE_DCC_BLOCK_IS_IND_128B', 'SURFACE_DCC_BLOCK_IS_IND_64B',
'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL',
'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', 'SURFACE_DCC_IND_128B',
'SURFACE_DCC_IND_64B', 'SURFACE_DCC_IND_BLK',
'SURFACE_DCC_IS_IND_128B', 'SURFACE_DCC_IS_IND_64B',
'SURFACE_DCC_IS_NOT_IND_128B', 'SURFACE_DCC_IS_NOT_IND_64B',
'SURFACE_FLIP_AWAY_INT_LEVEL', 'SURFACE_FLIP_AWAY_INT_PULSE',
'SURFACE_FLIP_AWAY_INT_TYPE', 'SURFACE_FLIP_EXEC_DEBUG_MODE',
'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE',
'SURFACE_FLIP_EXEC_NORMAL_MODE', 'SURFACE_FLIP_INT_LEVEL',
'SURFACE_FLIP_INT_PULSE', 'SURFACE_FLIP_INT_TYPE',
'SURFACE_FLIP_IN_STEREOSYNC', 'SURFACE_FLIP_IN_STEREOSYNC_MODE',
'SURFACE_FLIP_MODE_FOR_STEREOSYNC',
'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED',
'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE',
'SURFACE_FLIP_STEREO_SELECT_DISABLE',
'SURFACE_FLIP_STEREO_SELECT_DISABLED',
'SURFACE_FLIP_STEREO_SELECT_ENABLED',
'SURFACE_FLIP_STEREO_SELECT_POLARITY',
'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT',
'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT',
'SURFACE_FLIP_TYPE', 'SURFACE_FLIP_VUPDATE_SKIP_NUM',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_0',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_1',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_10',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_11',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_12',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_13',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_14',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_15',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_2',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_3',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_4',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_5',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_6',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_7',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_8',
'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', 'SURFACE_INUSE_IS_LATCHED',
'SURFACE_INUSE_IS_NOT_LATCHED', 'SURFACE_INUSE_RAED_NO_LATCH',
'SURFACE_IS_DCC', 'SURFACE_IS_NOT_DCC', 'SURFACE_IS_NOT_TMZ',
'SURFACE_IS_TMZ', 'SURFACE_I_FLIP', 'SURFACE_PIXEL_FORMAT',
'SURFACE_TMZ', 'SURFACE_UPDATE_IS_LOCKED',
'SURFACE_UPDATE_IS_UNLOCKED', 'SURFACE_UPDATE_LOCK',
'SURFACE_V_FLIP', 'SU_PERFCNT_SEL', 'SWATH_HEIGHT',
'SWATH_HEIGHT_16L', 'SWATH_HEIGHT_1L', 'SWATH_HEIGHT_2L',
'SWATH_HEIGHT_4L', 'SWATH_HEIGHT_8L', 'SX_BLEND_OPT',
'SX_CB_RAT_ACK_REQUEST', 'SX_DOWNCONVERT_FORMAT',
'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', 'SX_PERF_SEL_CLOCK',
'SX_PERF_SEL_CLOCK_DROP_STALL', 'SX_PERF_SEL_COL_BUSY',
'SX_PERF_SEL_DB0_4X2_DISCARD', 'SX_PERF_SEL_DB0_END_OF_WAVE',
'SX_PERF_SEL_DB0_HALF_QUADS', 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS',
'SX_PERF_SEL_DB0_MRT_DISCARD_SRC',
'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST',
'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS',
'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS',
'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL',
'SX_PERF_SEL_DB0_PRED_PIXELS', 'SX_PERF_SEL_DB0_SIZE',
'SX_PERF_SEL_DB1_4X2_DISCARD', 'SX_PERF_SEL_DB1_END_OF_WAVE',
'SX_PERF_SEL_DB1_HALF_QUADS', 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS',
'SX_PERF_SEL_DB1_MRT_DISCARD_SRC',
'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST',
'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS',
'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS',
'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL',
'SX_PERF_SEL_DB1_PRED_PIXELS', 'SX_PERF_SEL_DB1_SIZE',
'SX_PERF_SEL_DB2_4X2_DISCARD', 'SX_PERF_SEL_DB2_END_OF_WAVE',
'SX_PERF_SEL_DB2_HALF_QUADS', 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS',
'SX_PERF_SEL_DB2_MRT_DISCARD_SRC',
'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST',
'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS',
'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS',
'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL',
'SX_PERF_SEL_DB2_PRED_PIXELS', 'SX_PERF_SEL_DB2_SIZE',
'SX_PERF_SEL_DB3_4X2_DISCARD', 'SX_PERF_SEL_DB3_END_OF_WAVE',
'SX_PERF_SEL_DB3_HALF_QUADS', 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS',
'SX_PERF_SEL_DB3_MRT_DISCARD_SRC',
'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST',
'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS',
'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS',
'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL',
'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_DB3_SIZE',
'SX_PERF_SEL_GATE_EN1', 'SX_PERF_SEL_GATE_EN2',
'SX_PERF_SEL_GATE_EN3', 'SX_PERF_SEL_GATE_EN4',
'SX_PERF_SEL_GATE_EN5', 'SX_PERF_SEL_GATE_EN6',
'SX_PERF_SEL_GATE_EN7', 'SX_PERF_SEL_GATE_EN8',
'SX_PERF_SEL_IDX_BUSY', 'SX_PERF_SEL_IDX_IDLE_CYCLES',
'SX_PERF_SEL_IDX_REQ', 'SX_PERF_SEL_IDX_REQ_LATENCY',
'SX_PERF_SEL_IDX_RET', 'SX_PERF_SEL_IDX_SCBD_STALL',
'SX_PERF_SEL_IDX_STALL_CYCLES', 'SX_PERF_SEL_PA_IDLE_CYCLES',
'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_POS_BANK_CONF',
'SX_PERF_SEL_PA_REQ', 'SX_PERF_SEL_PA_REQ_LATENCY',
'SX_PERF_SEL_POS_BUSY', 'SX_PERF_SEL_POS_SCBD_STALL',
'SX_PERF_SEL_SH_COLOR_STALL', 'SX_PERF_SEL_SH_COLOR_STARVE',
'SX_PERF_SEL_SH_IDX_STARVE', 'SX_PERF_SEL_SH_POS_STALL',
'SX_PERF_SEL_SH_POS_STARVE', 'SX_RT_EXPORT_10_11_11',
'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR',
'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10',
'SX_RT_EXPORT_2_10_10_10_6E4', 'SX_RT_EXPORT_2_10_10_10_7E3',
'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4',
'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8',
'SX_RT_EXPORT_9_9_9_E5', 'SX_RT_EXPORT_NO_CONVERSION',
'SYMCLK_FE_FORCE_EN', 'SYMCLK_FE_FORCE_EN_DISABLE',
'SYMCLK_FE_FORCE_EN_ENABLE', 'SYMCLK_FE_FORCE_SRC',
'SYMCLK_FE_FORCE_SRC_RESERVED', 'SYMCLK_FE_FORCE_SRC_UNIPHYA',
'SYMCLK_FE_FORCE_SRC_UNIPHYB', 'SYMCLK_FE_FORCE_SRC_UNIPHYC',
'SYMCLK_FE_FORCE_SRC_UNIPHYD', 'ScMap', 'ScUncertaintyRegionMode',
'ScUncertaintyRegionMult', 'ScXsel', 'ScYsel', 'SeMap',
'SePairMap', 'SePairXsel', 'SePairYsel', 'SeXsel', 'SeYsel',
'SourceFormat', 'Spare_257', 'StencilOp', 'TA_PERFCOUNT_SEL',
'TA_PERF_SEL_NULL', 'TA_PERF_SEL_addr_stalled_by_tc_cycles',
'TA_PERF_SEL_addr_stalled_by_td_cycles',
'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy',
'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles',
'TA_PERF_SEL_addresser_stalled_cycles',
'TA_PERF_SEL_aligner_busy',
'TA_PERF_SEL_aligner_clk_valid_cycles',
'TA_PERF_SEL_aligner_cycles', 'TA_PERF_SEL_aniso_10_cycle_quads',
'TA_PERF_SEL_aniso_12_cycle_quads',
'TA_PERF_SEL_aniso_14_cycle_quads',
'TA_PERF_SEL_aniso_16_cycle_quads',
'TA_PERF_SEL_aniso_1_cycle_quads',
'TA_PERF_SEL_aniso_2_cycle_quads',
'TA_PERF_SEL_aniso_4_cycle_quads',
'TA_PERF_SEL_aniso_6_cycle_quads',
'TA_PERF_SEL_aniso_8_cycle_quads',
'TA_PERF_SEL_aniso_gt1_cycle_quads',
'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles',
'TA_PERF_SEL_aniso_stalled_cycles',
'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions',
'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions',
'TA_PERF_SEL_atomic_write_data_input_cycles',
'TA_PERF_SEL_atomic_write_data_output_cycles',
'TA_PERF_SEL_bf_busy',
'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles',
'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles',
'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions',
'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions',
'TA_PERF_SEL_buffer_atomic_wavefronts',
'TA_PERF_SEL_buffer_flat_1_op_burst',
'TA_PERF_SEL_buffer_flat_2to3_op_burst',
'TA_PERF_SEL_buffer_flat_4to31_op_burst',
'TA_PERF_SEL_buffer_flat_clk_valid_cycles',
'TA_PERF_SEL_buffer_flat_ge32_op_burst',
'TA_PERF_SEL_buffer_has_index_instructions',
'TA_PERF_SEL_buffer_has_offset_instructions',
'TA_PERF_SEL_buffer_load_wavefronts',
'TA_PERF_SEL_buffer_store_wavefronts',
'TA_PERF_SEL_buffer_total_cycles',
'TA_PERF_SEL_buffer_wavefronts', 'TA_PERF_SEL_bvh_total_cycles',
'TA_PERF_SEL_color_1_cycle_quads',
'TA_PERF_SEL_color_2_cycle_quads',
'TA_PERF_SEL_color_3_cycle_quads',
'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles',
'TA_PERF_SEL_deriv_stalled_cycles',
'TA_PERF_SEL_flat_1_address_input_vgpr_instructions',
'TA_PERF_SEL_flat_atomic_wavefronts',
'TA_PERF_SEL_flat_load_wavefronts',
'TA_PERF_SEL_flat_store_wavefronts',
'TA_PERF_SEL_flat_total_cycles', 'TA_PERF_SEL_flat_wavefronts',
'TA_PERF_SEL_gradient_busy',
'TA_PERF_SEL_gradient_clk_valid_cycles',
'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy',
'TA_PERF_SEL_harvestable_clk_enabled_cycles',
'TA_PERF_SEL_harvestable_register_clk_enabled_cycles',
'TA_PERF_SEL_ibubble_16to31_cycle_burst',
'TA_PERF_SEL_ibubble_1_cycle_burst',
'TA_PERF_SEL_ibubble_2to3_cycle_burst',
'TA_PERF_SEL_ibubble_32to63_cycle_burst',
'TA_PERF_SEL_ibubble_4to15_cycle_burst',
'TA_PERF_SEL_ibubble_ge64_cycle_burst',
'TA_PERF_SEL_image_atomic_wavefronts',
'TA_PERF_SEL_image_bvh_11_input_vgpr_instructions',
'TA_PERF_SEL_image_bvh_12_input_vgpr_instructions',
'TA_PERF_SEL_image_bvh_1_op_burst',
'TA_PERF_SEL_image_bvh_2to3_op_burst',
'TA_PERF_SEL_image_bvh_4to7_op_burst',
'TA_PERF_SEL_image_bvh_8_input_vgpr_instructions',
'TA_PERF_SEL_image_bvh_9_input_vgpr_instructions',
'TA_PERF_SEL_image_bvh_ge8_op_burst',
'TA_PERF_SEL_image_linked_1_op_burst',
'TA_PERF_SEL_image_linked_2to3_op_burst',
'TA_PERF_SEL_image_linked_4to7_op_burst',
'TA_PERF_SEL_image_linked_ge8_op_burst',
'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions',
'TA_PERF_SEL_image_nosampler_1_op_burst',
'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions',
'TA_PERF_SEL_image_nosampler_2to3_op_burst',
'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions',
'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions',
'TA_PERF_SEL_image_nosampler_4to31_op_burst',
'TA_PERF_SEL_image_nosampler_ge32_op_burst',
'TA_PERF_SEL_image_nosampler_has_q_instructions',
'TA_PERF_SEL_image_nosampler_has_r_instructions',
'TA_PERF_SEL_image_nosampler_has_t_instructions',
'TA_PERF_SEL_image_nosampler_total_cycles',
'TA_PERF_SEL_image_read_wavefronts',
'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_1_op_burst',
'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_2to3_op_burst',
'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_4to7_op_burst',
'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions',
'TA_PERF_SEL_image_sampler_ge8_op_burst',
'TA_PERF_SEL_image_sampler_has_bias_instructions',
'TA_PERF_SEL_image_sampler_has_dr_instructions',
'TA_PERF_SEL_image_sampler_has_ds_instructions',
'TA_PERF_SEL_image_sampler_has_dt_instructions',
'TA_PERF_SEL_image_sampler_has_offset_instructions',
'TA_PERF_SEL_image_sampler_has_q_instructions',
'TA_PERF_SEL_image_sampler_has_r_instructions',
'TA_PERF_SEL_image_sampler_has_reference_instructions',
'TA_PERF_SEL_image_sampler_has_t_instructions',
'TA_PERF_SEL_image_sampler_total_cycles',
'TA_PERF_SEL_image_sampler_wavefronts',
'TA_PERF_SEL_image_store_wavefronts',
'TA_PERF_SEL_image_wavefronts', 'TA_PERF_SEL_in_addr_cycles',
'TA_PERF_SEL_in_busy', 'TA_PERF_SEL_in_cfifo_busy',
'TA_PERF_SEL_in_data_cycles', 'TA_PERF_SEL_in_fifos_busy',
'TA_PERF_SEL_in_qfifo_busy', 'TA_PERF_SEL_in_rfifo_busy',
'TA_PERF_SEL_in_waiting_on_req_cycles',
'TA_PERF_SEL_in_wfifo_busy',
'TA_PERF_SEL_latency_ram_ref_required_instructions',
'TA_PERF_SEL_latency_ram_weights_written_cycles',
'TA_PERF_SEL_latency_ram_whv_required_instructions',
'TA_PERF_SEL_latency_ram_whv_required_quads',
'TA_PERF_SEL_latency_ram_ws_required_instructions',
'TA_PERF_SEL_latency_ram_ws_required_quads',
'TA_PERF_SEL_lod_aniso_clk_valid_cycles', 'TA_PERF_SEL_lod_busy',
'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_quads',
'TA_PERF_SEL_mip_2_cycle_quads',
'TA_PERF_SEL_mipmap_invalid_samples',
'TA_PERF_SEL_mipmap_lod_0_samples',
'TA_PERF_SEL_mipmap_lod_10_samples',
'TA_PERF_SEL_mipmap_lod_11_samples',
'TA_PERF_SEL_mipmap_lod_12_samples',
'TA_PERF_SEL_mipmap_lod_13_samples',
'TA_PERF_SEL_mipmap_lod_14_samples',
'TA_PERF_SEL_mipmap_lod_1_samples',
'TA_PERF_SEL_mipmap_lod_2_samples',
'TA_PERF_SEL_mipmap_lod_3_samples',
'TA_PERF_SEL_mipmap_lod_4_samples',
'TA_PERF_SEL_mipmap_lod_5_samples',
'TA_PERF_SEL_mipmap_lod_6_samples',
'TA_PERF_SEL_mipmap_lod_7_samples',
'TA_PERF_SEL_mipmap_lod_8_samples',
'TA_PERF_SEL_mipmap_lod_9_samples',
'TA_PERF_SEL_non_harvestable_clk_enabled_cycles',
'TA_PERF_SEL_nonsampler_clk_valid_cycles', 'TA_PERF_SEL_ns_busy',
'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input',
'TA_PERF_SEL_num_nodes_invalidated_due_to_oob',
'TA_PERF_SEL_num_of_bvh_invalidated_first_tri',
'TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri',
'TA_PERF_SEL_num_of_bvh_invalidated_fp16_box',
'TA_PERF_SEL_num_of_bvh_invalidated_fp32_box',
'TA_PERF_SEL_num_of_bvh_invalidated_second_tri',
'TA_PERF_SEL_num_of_bvh_invalidated_third_tri',
'TA_PERF_SEL_num_of_bvh_valid_first_tri',
'TA_PERF_SEL_num_of_bvh_valid_fourth_tri',
'TA_PERF_SEL_num_of_bvh_valid_fp16_box',
'TA_PERF_SEL_num_of_bvh_valid_fp32_box',
'TA_PERF_SEL_num_of_bvh_valid_second_tri',
'TA_PERF_SEL_num_of_bvh_valid_third_tri',
'TA_PERF_SEL_num_unlit_nodes_ta_opt',
'TA_PERF_SEL_point_sampled_quads',
'TA_PERF_SEL_register_clk_valid_cycles',
'TA_PERF_SEL_sampler_addressing_clk_valid_cycles',
'TA_PERF_SEL_sampler_clk_valid_cycles',
'TA_PERF_SEL_sampler_op_quads', 'TA_PERF_SEL_smp_busy_ns_idle',
'TA_PERF_SEL_smp_idle_ns_busy',
'TA_PERF_SEL_store_2_write_data_vgpr_instructions',
'TA_PERF_SEL_store_3_write_data_vgpr_instructions',
'TA_PERF_SEL_store_4_write_data_vgpr_instructions',
'TA_PERF_SEL_store_has_w_instructions',
'TA_PERF_SEL_store_has_x_instructions',
'TA_PERF_SEL_store_has_y_instructions',
'TA_PERF_SEL_store_has_z_instructions',
'TA_PERF_SEL_store_write_data_input_cycles',
'TA_PERF_SEL_store_write_data_output_cycles',
'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles',
'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles',
'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles',
'TA_PERF_SEL_ta_busy', 'TA_PERF_SEL_tcreq_clk_valid_cycles',
'TA_PERF_SEL_total_wavefronts', 'TA_PERF_SEL_vmemcmd_cycles',
'TA_PERF_SEL_vmemreq_cycles', 'TA_PERF_SEL_vol_1_cycle_quads',
'TA_PERF_SEL_vol_2_cycle_quads', 'TA_PERF_SEL_walker_cycles',
'TA_PERF_SEL_write_1_op_burst', 'TA_PERF_SEL_write_2to3_op_burst',
'TA_PERF_SEL_write_4to31_op_burst',
'TA_PERF_SEL_write_data_clk_valid_cycles',
'TA_PERF_SEL_write_ge32_op_burst', 'TA_PERF_SEL_write_path_busy',
'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR',
'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1',
'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3',
'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED',
'TA_TC_REQ_MODES', 'TA_TC_REQ_MODE_BORDER', 'TA_TC_REQ_MODE_BYTE',
'TA_TC_REQ_MODE_BYTE_NV', 'TA_TC_REQ_MODE_DWORD',
'TA_TC_REQ_MODE_NORMAL', 'TA_TC_REQ_MODE_TEX0',
'TA_TC_REQ_MODE_TEX1', 'TA_TC_REQ_MODE_TEX2', 'TB_ACP_NOT_SEND',
'TB_ACP_PKT_SEND', 'TB_ACR_0_MULTIPLE_RESERVED',
'TB_ACR_1_MULTIPLE', 'TB_ACR_2_MULTIPLE',
'TB_ACR_3_MULTIPLE_RESERVED', 'TB_ACR_4_MULTIPLE',
'TB_ACR_5_MULTIPLE_RESERVED', 'TB_ACR_6_MULTIPLE_RESERVED',
'TB_ACR_7_MULTIPLE_RESERVED', 'TB_ACR_CONT_DISABLE',
'TB_ACR_CONT_ENABLE', 'TB_ACR_NOT_SEND',
'TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', 'TB_ACR_PKT_SEND',
'TB_ACR_SELECT_32K', 'TB_ACR_SELECT_44K', 'TB_ACR_SELECT_48K',
'TB_ACR_SELECT_HW', 'TB_ACR_SOURCE_HW', 'TB_ACR_SOURCE_SW',
'TB_AUDIO_INFO_CONT_DISABLE', 'TB_AUDIO_INFO_CONT_ENABLE',
'TB_AUDIO_INFO_NOT_SEND', 'TB_AUDIO_INFO_PKT_SEND',
'TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT',
'TB_BORROW_MODE_ACTIVE', 'TB_BORROW_MODE_BLANK',
'TB_BORROW_MODE_NONE', 'TB_BORROW_MODE_RESERVED',
'TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES', 'TB_CRC_ACTIVE_TRIBYTES',
'TB_CRC_ALL_TRIBYTES', 'TB_CRC_DATAISLAND_TRIBYTES',
'TB_CRC_DEEP_COLOR_PACKER', 'TB_CRC_DSC_PACKER',
'TB_CRC_ENCRYPTOR_INPUT', 'TB_CRC_TB_ENC_INPUT',
'TB_DEEP_COLOR_DEPTH_24BPP', 'TB_DEEP_COLOR_DEPTH_30BPP',
'TB_DEEP_COLOR_DEPTH_36BPP', 'TB_DEEP_COLOR_DEPTH_RESERVED',
'TB_DEFAULT_PHASE_IS_0', 'TB_DEFAULT_PHASE_IS_1', 'TB_DISABLE',
'TB_DSC_444_RGB', 'TB_DSC_DISABLE', 'TB_DSC_NATIVE_422_420',
'TB_ENABLE', 'TB_GC_AVMUTE_CONT_DISABLE',
'TB_GC_AVMUTE_CONT_ENABLE', 'TB_GC_AVMUTE_SET',
'TB_GC_AVMUTE_UNSET', 'TB_GC_CONT_DISABLE', 'TB_GC_CONT_ENABLE',
'TB_GC_NOT_SEND', 'TB_GC_PKT_SEND', 'TB_GENERIC_CONT_DISABLE',
'TB_GENERIC_CONT_ENABLE', 'TB_GENERIC_NOT_SEND',
'TB_GENERIC_PKT_SEND', 'TB_ISRC_CONT_DISABLE',
'TB_ISRC_CONT_ENABLE', 'TB_ISRC_NOT_SEND', 'TB_ISRC_PKT_SEND',
'TB_METADATA_NOT_SEND', 'TB_METADATA_PKT_SEND', 'TB_NOT_RESET',
'TB_NOT_SYNC_PHASE_ON_FRAME_START', 'TB_NO_ERROR_OCCURRED',
'TB_OVERFLOW_OCCURRED', 'TB_PIXEL_ENCODING_420',
'TB_PIXEL_ENCODING_422', 'TB_PIXEL_ENCODING_444_RGB',
'TB_PKT_LINE_REF_END_OF_ACTIVE', 'TB_PKT_LINE_REF_OTGSOF',
'TB_RESET', 'TB_SYNC_PHASE_ON_FRAME_START', 'TCC_CACHE_POLICIES',
'TCC_CACHE_POLICY_LRU', 'TCC_CACHE_POLICY_STREAM', 'TCC_MTYPE',
'TCP_CACHE_POLICIES', 'TCP_CACHE_POLICY_HIT_EVICT',
'TCP_CACHE_POLICY_HIT_LRU', 'TCP_CACHE_POLICY_MISS_EVICT',
'TCP_CACHE_POLICY_MISS_LRU', 'TCP_CACHE_STORE_POLICIES',
'TCP_CACHE_STORE_POLICY_WT_EVICT',
'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_DSM_DATA_SEL',
'TCP_DSM_DISABLE', 'TCP_DSM_INJECT_SEL', 'TCP_DSM_INJECT_SEL0',
'TCP_DSM_INJECT_SEL1', 'TCP_DSM_INJECT_SEL2',
'TCP_DSM_INJECT_SEL3', 'TCP_DSM_SEL0', 'TCP_DSM_SEL1',
'TCP_DSM_SEL_BOTH', 'TCP_DSM_SINGLE_WRITE',
'TCP_DSM_SINGLE_WRITE_DIS', 'TCP_DSM_SINGLE_WRITE_EN',
'TCP_OPCODE_ATOMIC', 'TCP_OPCODE_ATOMIC_CMPSWAP',
'TCP_OPCODE_GATHERH', 'TCP_OPCODE_INV', 'TCP_OPCODE_LOAD',
'TCP_OPCODE_READ', 'TCP_OPCODE_SAMPLER', 'TCP_OPCODE_TYPE',
'TCP_OPCODE_WRITE', 'TCP_PERFCOUNT_SELECT',
'TCP_PERF_SEL_ALLOC_STALL',
'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL',
'TCP_PERF_SEL_COMP_TEX_LOAD_STALL',
'TCP_PERF_SEL_DATA_FIFO_STALL', 'TCP_PERF_SEL_GATE_EN1',
'TCP_PERF_SEL_GATE_EN2', 'TCP_PERF_SEL_GL1_GRANT_READ_STALL',
'TCP_PERF_SEL_GL1_PENDING_STALL', 'TCP_PERF_SEL_GL1_READ_LATENCY',
'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET',
'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET',
'TCP_PERF_SEL_GL1_REQ_READ', 'TCP_PERF_SEL_GL1_REQ_READ_128B',
'TCP_PERF_SEL_GL1_REQ_READ_64B', 'TCP_PERF_SEL_GL1_REQ_WRITE',
'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE',
'TCP_PERF_SEL_GL1_TCP_RDRET_STALL',
'TCP_PERF_SEL_GL1_WRITE_LATENCY', 'TCP_PERF_SEL_LFIFO_STALL',
'TCP_PERF_SEL_LOD_STALL', 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL',
'TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL',
'TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL', 'TCP_PERF_SEL_POWER_STALL',
'TCP_PERF_SEL_READ_DATACONFLICT_STALL',
'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', 'TCP_PERF_SEL_REQ',
'TCP_PERF_SEL_REQ_MISS', 'TCP_PERF_SEL_REQ_MISS_TAGBANK0',
'TCP_PERF_SEL_REQ_MISS_TAGBANK1',
'TCP_PERF_SEL_REQ_MISS_TAGBANK2',
'TCP_PERF_SEL_REQ_MISS_TAGBANK3', 'TCP_PERF_SEL_REQ_NON_READ',
'TCP_PERF_SEL_REQ_READ', 'TCP_PERF_SEL_REQ_READ_HIT_EVICT',
'TCP_PERF_SEL_REQ_READ_HIT_LRU',
'TCP_PERF_SEL_REQ_READ_MISS_EVICT',
'TCP_PERF_SEL_REQ_TAGBANK0_SET0',
'TCP_PERF_SEL_REQ_TAGBANK0_SET1',
'TCP_PERF_SEL_REQ_TAGBANK1_SET0',
'TCP_PERF_SEL_REQ_TAGBANK1_SET1',
'TCP_PERF_SEL_REQ_TAGBANK2_SET0',
'TCP_PERF_SEL_REQ_TAGBANK2_SET1',
'TCP_PERF_SEL_REQ_TAGBANK3_SET0',
'TCP_PERF_SEL_REQ_TAGBANK3_SET1', 'TCP_PERF_SEL_REQ_WRITE',
'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT',
'TCP_PERF_SEL_REQ_WRITE_MISS_LRU', 'TCP_PERF_SEL_TA_REQ',
'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET',
'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET',
'TCP_PERF_SEL_TA_REQ_GL0_INV', 'TCP_PERF_SEL_TA_REQ_READ',
'TCP_PERF_SEL_TA_REQ_STATE_READ', 'TCP_PERF_SEL_TA_REQ_WRITE',
'TCP_PERF_SEL_TA_TCP_REQ_STARVE', 'TCP_PERF_SEL_TCP_LATENCY',
'TCP_PERF_SEL_TCP_TA_REQ_STALL',
'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', 'TCP_PERF_SEL_TD_TCP_STALL',
'TCP_PERF_SEL_UNORDERED_MTYPE_STALL',
'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL',
'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', 'TCP_WATCH_MODES',
'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC',
'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', 'TC_EA_CID',
'TC_EA_CID_CPF', 'TC_EA_CID_CPG', 'TC_EA_CID_DCC',
'TC_EA_CID_FMASK', 'TC_EA_CID_HTILE', 'TC_EA_CID_IA',
'TC_EA_CID_MISC', 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC',
'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA',
'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', 'TC_NACKS',
'TC_NACK_DATA_ERROR', 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT',
'TC_NACK_PROTECTION_FAULT', 'TC_OP', 'TC_OP_ATOMIC_ADD_32',
'TC_OP_ATOMIC_ADD_64', 'TC_OP_ATOMIC_ADD_RTN_32',
'TC_OP_ATOMIC_ADD_RTN_64', 'TC_OP_ATOMIC_AND_32',
'TC_OP_ATOMIC_AND_64', 'TC_OP_ATOMIC_AND_RTN_32',
'TC_OP_ATOMIC_AND_RTN_64', 'TC_OP_ATOMIC_CMPSWAP_32',
'TC_OP_ATOMIC_CMPSWAP_64', 'TC_OP_ATOMIC_CMPSWAP_RTN_32',
'TC_OP_ATOMIC_CMPSWAP_RTN_64', 'TC_OP_ATOMIC_DEC_32',
'TC_OP_ATOMIC_DEC_64', 'TC_OP_ATOMIC_DEC_RTN_32',
'TC_OP_ATOMIC_DEC_RTN_64', 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32',
'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32',
'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64',
'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32',
'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64',
'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32',
'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64',
'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64',
'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64',
'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32',
'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64',
'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32',
'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64',
'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64',
'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64',
'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32',
'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64',
'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32',
'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64',
'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64',
'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64',
'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64',
'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64',
'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64',
'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64',
'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64',
'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64',
'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64',
'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64',
'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64',
'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64',
'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64',
'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64',
'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64',
'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64',
'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64',
'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64',
'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64',
'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS',
'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN',
'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER',
'TC_OP_READ', 'TC_OP_RESERVED_FADD_32',
'TC_OP_RESERVED_FADD_RTN_32', 'TC_OP_RESERVED_FOP_32_0',
'TC_OP_RESERVED_FOP_32_2', 'TC_OP_RESERVED_FOP_64_0',
'TC_OP_RESERVED_FOP_64_1', 'TC_OP_RESERVED_FOP_64_2',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0',
'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1',
'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_2',
'TC_OP_RESERVED_FOP_RTN_64_0', 'TC_OP_RESERVED_FOP_RTN_64_1',
'TC_OP_RESERVED_FOP_RTN_64_2', 'TC_OP_RESERVED_NON_FLOAT_32_1',
'TC_OP_RESERVED_NON_FLOAT_32_2', 'TC_OP_RESERVED_NON_FLOAT_32_3',
'TC_OP_RESERVED_NON_FLOAT_32_4', 'TC_OP_RESERVED_NON_FLOAT_64_1',
'TC_OP_RESERVED_NON_FLOAT_64_2', 'TC_OP_RESERVED_NON_FLOAT_64_3',
'TC_OP_RESERVED_NON_FLOAT_64_4',
'TC_OP_RESERVED_NON_FLOAT_RTN_32_0',
'TC_OP_RESERVED_NON_FLOAT_RTN_32_1',
'TC_OP_RESERVED_NON_FLOAT_RTN_32_2',
'TC_OP_RESERVED_NON_FLOAT_RTN_32_3',
'TC_OP_RESERVED_NON_FLOAT_RTN_64_1',
'TC_OP_RESERVED_NON_FLOAT_RTN_64_2',
'TC_OP_RESERVED_NON_FLOAT_RTN_64_3',
'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1',
'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2',
'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC',
'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL',
'TD_PERF_SEL_address_cmd_poison',
'TD_PERF_SEL_all_pipes_sclk_on_at_same_time',
'TD_PERF_SEL_blend_prt_with_prt_default_0',
'TD_PERF_SEL_blend_prt_with_prt_default_1',
'TD_PERF_SEL_bubble_bin_lds_stall_1to3',
'TD_PERF_SEL_bubble_bin_lds_stall_4to7',
'TD_PERF_SEL_bubble_bin_lds_stall_8to15',
'TD_PERF_SEL_bubble_bin_lds_stall_gt15',
'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0',
'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1',
'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511',
'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31',
'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127',
'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511',
'TD_PERF_SEL_burst_bin_bvh4_1', 'TD_PERF_SEL_burst_bin_bvh4_2to8',
'TD_PERF_SEL_burst_bin_bvh4_9to16',
'TD_PERF_SEL_burst_bin_bvh4_box_nodes_1',
'TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4',
'TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7',
'TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16',
'TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16',
'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1',
'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8',
'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16',
'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16',
'TD_PERF_SEL_burst_bin_bvh4_gt16',
'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1',
'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8',
'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16',
'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16',
'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1',
'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8',
'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16',
'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16',
'TD_PERF_SEL_burst_bin_gather_1',
'TD_PERF_SEL_burst_bin_gather_2to8',
'TD_PERF_SEL_burst_bin_gather_9to16',
'TD_PERF_SEL_burst_bin_gather_gt16',
'TD_PERF_SEL_burst_bin_nofilter_1',
'TD_PERF_SEL_burst_bin_nofilter_2to4',
'TD_PERF_SEL_burst_bin_nofilter_5to7',
'TD_PERF_SEL_burst_bin_nofilter_8to16',
'TD_PERF_SEL_burst_bin_nofilter_gt16',
'TD_PERF_SEL_burst_bin_preempting_nofilter_1',
'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4',
'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7',
'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16',
'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16',
'TD_PERF_SEL_burst_bin_sampler_1',
'TD_PERF_SEL_burst_bin_sampler_2to8',
'TD_PERF_SEL_burst_bin_sampler_9to16',
'TD_PERF_SEL_burst_bin_sampler_gt16',
'TD_PERF_SEL_bypassLerp_instr',
'TD_PERF_SEL_core_state_ram_max_cnt',
'TD_PERF_SEL_core_state_rams_read', 'TD_PERF_SEL_d16_en_instr',
'TD_PERF_SEL_data_poison',
'TD_PERF_SEL_done_scoreboard_bp_due_to_lds',
'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo',
'TD_PERF_SEL_done_scoreboard_is_full',
'TD_PERF_SEL_done_scoreboard_max_stored_cnt',
'TD_PERF_SEL_done_scoreboard_max_waiting_cnt',
'TD_PERF_SEL_done_scoreboard_not_empty',
'TD_PERF_SEL_four_comp_return_instr', 'TD_PERF_SEL_gather4_instr',
'TD_PERF_SEL_gather4h_instr',
'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full',
'TD_PERF_SEL_input_busy', 'TD_PERF_SEL_input_state_fifo_full',
'TD_PERF_SEL_instruction_dest_is_lds', 'TD_PERF_SEL_ldfptr_instr',
'TD_PERF_SEL_lds_stall', 'TD_PERF_SEL_load_instr',
'TD_PERF_SEL_lod_warn_from_ta',
'TD_PERF_SEL_min_max_filter_instr', 'TD_PERF_SEL_mixmode_instr',
'TD_PERF_SEL_mixmode_resource', 'TD_PERF_SEL_msaa_load_instr',
'TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off',
'TD_PERF_SEL_nofilter_busy',
'TD_PERF_SEL_nofilter_byte_cycling_16cycles',
'TD_PERF_SEL_nofilter_byte_cycling_4cycles',
'TD_PERF_SEL_nofilter_byte_cycling_8cycles',
'TD_PERF_SEL_nofilter_d16_sclk_en',
'TD_PERF_SEL_nofilter_d32_sclk_en',
'TD_PERF_SEL_nofilter_dword_cycling_2cycles',
'TD_PERF_SEL_nofilter_dword_cycling_4cycles',
'TD_PERF_SEL_nofilter_formatters_turned_on',
'TD_PERF_SEL_nofilter_insert_extra_comps',
'TD_PERF_SEL_nofilter_pkr_full',
'TD_PERF_SEL_nofilter_pkr_full_due_to_arb',
'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt',
'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt',
'TD_PERF_SEL_nofilter_sclk_en',
'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off',
'TD_PERF_SEL_nofilter_total_num_comps_to_lds', 'TD_PERF_SEL_none',
'TD_PERF_SEL_one_comp_return_instr',
'TD_PERF_SEL_opaque_black_border',
'TD_PERF_SEL_out_of_order_instr',
'TD_PERF_SEL_preempting_nofilter_max_cnt',
'TD_PERF_SEL_prt_ack_instr',
'TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero',
'TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en',
'TD_PERF_SEL_ray_tracing_bvh4_box_sort_en',
'TD_PERF_SEL_ray_tracing_bvh4_busy',
'TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node',
'TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node',
'TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node',
'TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node',
'TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt',
'TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node',
'TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node',
'TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en',
'TD_PERF_SEL_ray_tracing_bvh4_num_box_misses',
'TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan',
'TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx',
'TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses',
'TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers',
'TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx',
'TD_PERF_SEL_ray_tracing_bvh4_pkr_full',
'TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb',
'TD_PERF_SEL_ray_tracing_bvh4_sclk_en',
'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0',
'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1',
'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31',
'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2',
'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32',
'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4',
'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8',
'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16',
'TD_PERF_SEL_ray_tracing_bvh4_tri_node',
'TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en',
'TD_PERF_SEL_reference_data_rams_read',
'TD_PERF_SEL_resmap_instr',
'TD_PERF_SEL_resmap_with_aniso_filtering',
'TD_PERF_SEL_resmap_with_cubemap_corner',
'TD_PERF_SEL_resmap_with_no_more_filtering',
'TD_PERF_SEL_resmap_with_volume_filtering',
'TD_PERF_SEL_sample_c_instr', 'TD_PERF_SEL_sample_instr',
'TD_PERF_SEL_sampler_accum_sclk_en',
'TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off',
'TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off',
'TD_PERF_SEL_sampler_bilerp_sclk_en',
'TD_PERF_SEL_sampler_bypass_sclk_en',
'TD_PERF_SEL_sampler_core_sclk_en',
'TD_PERF_SEL_sampler_format_flt_sclk_en',
'TD_PERF_SEL_sampler_format_fxdpt_sclk_en',
'TD_PERF_SEL_sampler_lerp0_active',
'TD_PERF_SEL_sampler_lerp1_active',
'TD_PERF_SEL_sampler_lerp2_active',
'TD_PERF_SEL_sampler_lerp3_active',
'TD_PERF_SEL_sampler_lerp_busy',
'TD_PERF_SEL_sampler_minmax_sclk_en',
'TD_PERF_SEL_sampler_out_busy', 'TD_PERF_SEL_sampler_out_sclk_en',
'TD_PERF_SEL_sampler_pkr_full',
'TD_PERF_SEL_sampler_pkr_full_due_to_arb',
'TD_PERF_SEL_sampler_preformatter_sclk_en',
'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off',
'TD_PERF_SEL_status_packet', 'TD_PERF_SEL_ta_data_stall',
'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles',
'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles',
'TD_PERF_SEL_tc_data_stall', 'TD_PERF_SEL_tc_ram_stall',
'TD_PERF_SEL_tc_td_data_fifo_full',
'TD_PERF_SEL_tc_td_ram_fifo_full',
'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', 'TD_PERF_SEL_td_busy',
'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles',
'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles',
'TD_PERF_SEL_three_comp_return_instr',
'TD_PERF_SEL_total_num_instr',
'TD_PERF_SEL_total_num_instr_with_perf_wdw',
'TD_PERF_SEL_total_num_nofilter_instr',
'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw',
'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr',
'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw',
'TD_PERF_SEL_total_num_sampler_instr',
'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw',
'TD_PERF_SEL_two_comp_return_instr',
'TD_PERF_SEL_user_defined_border',
'TD_PERF_SEL_weight_data_rams_read', 'TD_PERF_SEL_white_border',
'TD_PERF_SEL_write_ack_instr', 'TESS_ISOLINE', 'TESS_QUAD',
'TESS_TRIANGLE', 'TEST_CLK_DIV_SEL', 'TEST_CLK_SEL',
'TEST_CLK_SEL_0', 'TEST_CLK_SEL_1', 'TEST_CLK_SEL_2',
'TEST_CLK_SEL_3', 'TEST_CLK_SEL_4', 'TEST_CLK_SEL_5',
'TEST_CLK_SEL_6', 'TEST_CLK_SEL_7',
'TEST_CLOCK_MUX_SELECT_DISPCLK_G',
'TEST_CLOCK_MUX_SELECT_DISPCLK_P',
'TEST_CLOCK_MUX_SELECT_DISPCLK_R',
'TEST_CLOCK_MUX_SELECT_DSCCLK_G',
'TEST_CLOCK_MUX_SELECT_DSCCLK_P',
'TEST_CLOCK_MUX_SELECT_DSCCLK_R', 'TEST_CLOCK_MUX_SELECT_ENUM',
'TEX_BC_SWIZZLE', 'TEX_BC_Swizzle_WXYZ', 'TEX_BC_Swizzle_WZYX',
'TEX_BC_Swizzle_XWYZ', 'TEX_BC_Swizzle_XYZW',
'TEX_BC_Swizzle_YXWZ', 'TEX_BC_Swizzle_ZYXW',
'TEX_BORDER_COLOR_TYPE', 'TEX_BorderColor_OpaqueBlack',
'TEX_BorderColor_OpaqueWhite', 'TEX_BorderColor_Register',
'TEX_BorderColor_TransparentBlack', 'TEX_CHROMA_KEY', 'TEX_CLAMP',
'TEX_COORD_TYPE', 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled',
'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3',
'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder',
'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror',
'TEX_Clamp_MirrorOnceHalfToBorder',
'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast',
'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized',
'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION',
'TEX_DepthCompareFunction_Always',
'TEX_DepthCompareFunction_Equal',
'TEX_DepthCompareFunction_Greater',
'TEX_DepthCompareFunction_GreaterEqual',
'TEX_DepthCompareFunction_Less',
'TEX_DepthCompareFunction_LessEqual',
'TEX_DepthCompareFunction_Never',
'TEX_DepthCompareFunction_NotEqual', 'TEX_FORMAT_COMP',
'TEX_FormatComp_RESERVED_3', 'TEX_FormatComp_Signed',
'TEX_FormatComp_Unsigned', 'TEX_FormatComp_UnsignedBiased',
'TEX_MAX_ANISO_RATIO', 'TEX_MIP_FILTER',
'TEX_MaxAnisoRatio_16to1', 'TEX_MaxAnisoRatio_1to1',
'TEX_MaxAnisoRatio_2to1', 'TEX_MaxAnisoRatio_4to1',
'TEX_MaxAnisoRatio_8to1', 'TEX_MaxAnisoRatio_RESERVED_5',
'TEX_MaxAnisoRatio_RESERVED_6', 'TEX_MaxAnisoRatio_RESERVED_7',
'TEX_MipFilter_Linear', 'TEX_MipFilter_None',
'TEX_MipFilter_Point', 'TEX_MipFilter_Point_Aniso_Adj',
'TEX_REQUEST_SIZE', 'TEX_RequestSize_128B',
'TEX_RequestSize_2X64B', 'TEX_RequestSize_32B',
'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE',
'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid',
'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint',
'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER',
'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point',
'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER',
'THM_BASE', 'THM_BASE__INST0_SEG0', 'THM_BASE__INST0_SEG1',
'THM_BASE__INST0_SEG2', 'THM_BASE__INST0_SEG3',
'THM_BASE__INST0_SEG4', 'THM_BASE__INST1_SEG0',
'THM_BASE__INST1_SEG1', 'THM_BASE__INST1_SEG2',
'THM_BASE__INST1_SEG3', 'THM_BASE__INST1_SEG4',
'THM_BASE__INST2_SEG0', 'THM_BASE__INST2_SEG1',
'THM_BASE__INST2_SEG2', 'THM_BASE__INST2_SEG3',
'THM_BASE__INST2_SEG4', 'THM_BASE__INST3_SEG0',
'THM_BASE__INST3_SEG1', 'THM_BASE__INST3_SEG2',
'THM_BASE__INST3_SEG3', 'THM_BASE__INST3_SEG4',
'THM_BASE__INST4_SEG0', 'THM_BASE__INST4_SEG1',
'THM_BASE__INST4_SEG2', 'THM_BASE__INST4_SEG3',
'THM_BASE__INST4_SEG4', 'THM_BASE__INST5_SEG0',
'THM_BASE__INST5_SEG1', 'THM_BASE__INST5_SEG2',
'THM_BASE__INST5_SEG3', 'THM_BASE__INST5_SEG4',
'THM_BASE__INST6_SEG0', 'THM_BASE__INST6_SEG1',
'THM_BASE__INST6_SEG2', 'THM_BASE__INST6_SEG3',
'THM_BASE__INST6_SEG4', 'THREAD_TRACE_DRAW',
'THREAD_TRACE_FINISH', 'THREAD_TRACE_MARKER',
'THREAD_TRACE_START', 'THREAD_TRACE_STOP', 'TIGHT_PACK',
'TMDS_COLOR_FORMAT', 'TMDS_COLOR_FORMAT_DUAL30BPP',
'TMDS_COLOR_FORMAT_RESERVED', 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB',
'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP',
'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN',
'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0',
'TMDS_CTL0_DATA_MODULATION_BIT1',
'TMDS_CTL0_DATA_MODULATION_BIT2',
'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL',
'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED',
'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC',
'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC',
'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED',
'TMDS_CTL0_DATA_SEL8_RANDOM_DATA',
'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA',
'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN',
'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT',
'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION',
'TMDS_CTL1_DATA_MODULATION_BIT0',
'TMDS_CTL1_DATA_MODULATION_BIT1',
'TMDS_CTL1_DATA_MODULATION_BIT2',
'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL',
'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED',
'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC',
'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC',
'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED',
'TMDS_CTL1_DATA_SEL8_BLANK_TIME',
'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED',
'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN',
'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT',
'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION',
'TMDS_CTL2_DATA_MODULATION_BIT0',
'TMDS_CTL2_DATA_MODULATION_BIT1',
'TMDS_CTL2_DATA_MODULATION_BIT2',
'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL',
'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED',
'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC',
'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC',
'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED',
'TMDS_CTL2_DATA_SEL8_BLANK_TIME',
'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED',
'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN',
'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT',
'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION',
'TMDS_CTL3_DATA_MODULATION_BIT0',
'TMDS_CTL3_DATA_MODULATION_BIT1',
'TMDS_CTL3_DATA_MODULATION_BIT2',
'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL',
'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED',
'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC',
'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC',
'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED',
'TMDS_CTL3_DATA_SEL8_BLANK_TIME',
'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED',
'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN',
'TMDS_CTL3_PATTERN_OUT_ENABLE',
'TMDS_DATA_SYNCHRONIZATION_DSINTSEL',
'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS',
'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', 'TMDS_MUX_SELECT',
'TMDS_MUX_SELECT_B', 'TMDS_MUX_SELECT_G', 'TMDS_MUX_SELECT_R',
'TMDS_MUX_SELECT_RESERVED', 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START',
'TMDS_PIXEL_ENCODING', 'TMDS_PIXEL_ENCODING_422',
'TMDS_PIXEL_ENCODING_444_OR_420', 'TMDS_REG_TEST_OUTPUTA_CNTLA',
'TMDS_REG_TEST_OUTPUTA_CNTLA_NA',
'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0',
'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1',
'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2',
'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA',
'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0',
'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1',
'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0',
'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2',
'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG',
'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START',
'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT',
'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT',
'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT',
'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT',
'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA',
'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB',
'TMDS_TRANSMITTER_CONTROL_IDSCKSELA',
'TMDS_TRANSMITTER_CONTROL_IDSCKSELB',
'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN',
'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK',
'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN',
'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK',
'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS',
'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS',
'TMDS_TRANSMITTER_ENABLE_HPD_MASK',
'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK',
'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK',
'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE',
'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE',
'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE',
'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE',
'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON',
'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON',
'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK',
'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK',
'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK',
'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK',
'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE',
'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE',
'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE',
'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE',
'TMDS_TRANSMITTER_PLLSEL_BY_HW',
'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW',
'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD',
'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE',
'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE',
'TMDS_TRANSMITTER_PLL_RST_ON_HPD',
'TMDS_TRANSMITTER_TDCLK_FROM_PADS',
'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK',
'TMDS_TRANSMITTER_TMCLK_FROM_PADS',
'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', 'TRANSERR',
'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES',
'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES',
'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES',
'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS',
'TRISTRIP', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource',
'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource',
'TVX_Type_ValidVertexBuffer', 'UCONFIG_SPACE_END',
'UCONFIG_SPACE_START', 'UMC_BASE', 'UMC_BASE__INST0_SEG0',
'UMC_BASE__INST0_SEG1', 'UMC_BASE__INST0_SEG2',
'UMC_BASE__INST0_SEG3', 'UMC_BASE__INST0_SEG4',
'UMC_BASE__INST1_SEG0', 'UMC_BASE__INST1_SEG1',
'UMC_BASE__INST1_SEG2', 'UMC_BASE__INST1_SEG3',
'UMC_BASE__INST1_SEG4', 'UMC_BASE__INST2_SEG0',
'UMC_BASE__INST2_SEG1', 'UMC_BASE__INST2_SEG2',
'UMC_BASE__INST2_SEG3', 'UMC_BASE__INST2_SEG4',
'UMC_BASE__INST3_SEG0', 'UMC_BASE__INST3_SEG1',
'UMC_BASE__INST3_SEG2', 'UMC_BASE__INST3_SEG3',
'UMC_BASE__INST3_SEG4', 'UMC_BASE__INST4_SEG0',
'UMC_BASE__INST4_SEG1', 'UMC_BASE__INST4_SEG2',
'UMC_BASE__INST4_SEG3', 'UMC_BASE__INST4_SEG4',
'UMC_BASE__INST5_SEG0', 'UMC_BASE__INST5_SEG1',
'UMC_BASE__INST5_SEG2', 'UMC_BASE__INST5_SEG3',
'UMC_BASE__INST5_SEG4', 'UMC_BASE__INST6_SEG0',
'UMC_BASE__INST6_SEG1', 'UMC_BASE__INST6_SEG2',
'UMC_BASE__INST6_SEG3', 'UMC_BASE__INST6_SEG4', 'UNDEF',
'UNSIGNED', 'USB0_BASE', 'USB0_BASE__INST0_SEG0',
'USB0_BASE__INST0_SEG1', 'USB0_BASE__INST0_SEG2',
'USB0_BASE__INST0_SEG3', 'USB0_BASE__INST0_SEG4',
'USB0_BASE__INST1_SEG0', 'USB0_BASE__INST1_SEG1',
'USB0_BASE__INST1_SEG2', 'USB0_BASE__INST1_SEG3',
'USB0_BASE__INST1_SEG4', 'USB0_BASE__INST2_SEG0',
'USB0_BASE__INST2_SEG1', 'USB0_BASE__INST2_SEG2',
'USB0_BASE__INST2_SEG3', 'USB0_BASE__INST2_SEG4',
'USB0_BASE__INST3_SEG0', 'USB0_BASE__INST3_SEG1',
'USB0_BASE__INST3_SEG2', 'USB0_BASE__INST3_SEG3',
'USB0_BASE__INST3_SEG4', 'USB0_BASE__INST4_SEG0',
'USB0_BASE__INST4_SEG1', 'USB0_BASE__INST4_SEG2',
'USB0_BASE__INST4_SEG3', 'USB0_BASE__INST4_SEG4',
'USB0_BASE__INST5_SEG0', 'USB0_BASE__INST5_SEG1',
'USB0_BASE__INST5_SEG2', 'USB0_BASE__INST5_SEG3',
'USB0_BASE__INST5_SEG4', 'USB0_BASE__INST6_SEG0',
'USB0_BASE__INST6_SEG1', 'USB0_BASE__INST6_SEG2',
'USB0_BASE__INST6_SEG3', 'USB0_BASE__INST6_SEG4',
'USE_MALL_FOR_CURSOR', 'USE_MALL_FOR_CURSOR_0',
'USE_MALL_FOR_CURSOR_1', 'USE_MALL_FOR_PSTATE_CHANGE',
'USE_MALL_FOR_PSTATE_CHANGE_0', 'USE_MALL_FOR_PSTATE_CHANGE_1',
'USE_MALL_FOR_STATIC_SCREEN', 'USE_MALL_FOR_STATIC_SCREEN_0',
'USE_MALL_FOR_STATIC_SCREEN_1', 'UTCL0FaultType',
'UTCL0RequestType', 'UTCL0_TYPE_BYPASS', 'UTCL0_TYPE_NORMAL',
'UTCL0_TYPE_SHOOTDOWN', 'UTCL0_XNACK_NO_RETRY', 'UTCL0_XNACK_PRT',
'UTCL0_XNACK_RETRY', 'UTCL0_XNACK_SUCCESS', 'UTCL1FaultType',
'UTCL1PerfSel', 'UTCL1RequestType', 'UTCL1_PERF_SEL_BYPASS_REQS',
'UTCL1_PERF_SEL_CP_INVREQS', 'UTCL1_PERF_SEL_HITS',
'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS',
'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS',
'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT',
'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', 'UTCL1_PERF_SEL_MISSES',
'UTCL1_PERF_SEL_NONE', 'UTCL1_PERF_SEL_RANGE_INVREQS',
'UTCL1_PERF_SEL_REQS', 'UTCL1_PERF_SEL_RTNS',
'UTCL1_PERF_SEL_STALL_MH_FULL',
'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', 'UTCL1_PERF_SEL_UTCL2_REQS',
'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM',
'UTCL1_PERF_SEL_UTCL2_RET_CNT', 'UTCL1_PERF_SEL_UTCL2_RET_FAULT',
'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT',
'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT',
'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY',
'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS',
'UTCL1_PERF_SEL_XLAT_REQ_BUSY', 'UTCL1_TYPE_BYPASS',
'UTCL1_TYPE_NORMAL', 'UTCL1_TYPE_SHOOTDOWN',
'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', 'UTCL1_XNACK_RETRY',
'UTCL1_XNACK_SUCCESS', 'VCN_BASE', 'VCN_BASE__INST0_SEG0',
'VCN_BASE__INST0_SEG1', 'VCN_BASE__INST0_SEG2',
'VCN_BASE__INST0_SEG3', 'VCN_BASE__INST0_SEG4',
'VCN_BASE__INST1_SEG0', 'VCN_BASE__INST1_SEG1',
'VCN_BASE__INST1_SEG2', 'VCN_BASE__INST1_SEG3',
'VCN_BASE__INST1_SEG4', 'VCN_BASE__INST2_SEG0',
'VCN_BASE__INST2_SEG1', 'VCN_BASE__INST2_SEG2',
'VCN_BASE__INST2_SEG3', 'VCN_BASE__INST2_SEG4',
'VCN_BASE__INST3_SEG0', 'VCN_BASE__INST3_SEG1',
'VCN_BASE__INST3_SEG2', 'VCN_BASE__INST3_SEG3',
'VCN_BASE__INST3_SEG4', 'VCN_BASE__INST4_SEG0',
'VCN_BASE__INST4_SEG1', 'VCN_BASE__INST4_SEG2',
'VCN_BASE__INST4_SEG3', 'VCN_BASE__INST4_SEG4',
'VCN_BASE__INST5_SEG0', 'VCN_BASE__INST5_SEG1',
'VCN_BASE__INST5_SEG2', 'VCN_BASE__INST5_SEG3',
'VCN_BASE__INST5_SEG4', 'VCN_BASE__INST6_SEG0',
'VCN_BASE__INST6_SEG1', 'VCN_BASE__INST6_SEG2',
'VCN_BASE__INST6_SEG3', 'VCN_BASE__INST6_SEG4', 'VGT_DETECT_ONE',
'VGT_DETECT_ZERO', 'VGT_DIST_MODE', 'VGT_DI_INDEX_SIZE',
'VGT_DI_MAJOR_MODE_SELECT', 'VGT_DI_PRIM_TYPE',
'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', 'VGT_DMA_BUF_RING',
'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', 'VGT_DMA_PTR_UPDATE',
'VGT_DMA_SWAP_16_BIT', 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE',
'VGT_DMA_SWAP_NONE', 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE',
'VGT_FLUSH', 'VGT_GROUP_CONV_SEL', 'VGT_GRP_AUTO_PRIM',
'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32',
'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_SINT_16',
'VGT_GRP_SINT_32', 'VGT_GRP_UINT_16', 'VGT_GRP_UINT_32',
'VGT_GS_MODE_TYPE', 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16',
'VGT_INDEX_32', 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE',
'VGT_OUTPATH_GS_BLOCK', 'VGT_OUTPATH_HS_BLOCK',
'VGT_OUTPATH_PRIM_GEN', 'VGT_OUTPATH_SELECT',
'VGT_OUTPATH_TE_GS_BLOCK', 'VGT_OUTPATH_TE_OUTPUT',
'VGT_OUTPATH_TE_PRIM_GEN', 'VGT_OUTPATH_VTX_REUSE',
'VGT_OUT_2D_RECT', 'VGT_OUT_LINE', 'VGT_OUT_LINE_ADJ',
'VGT_OUT_PATCH', 'VGT_OUT_POINT', 'VGT_OUT_PRIM_TYPE',
'VGT_OUT_RECT_V0', 'VGT_OUT_RECT_V1', 'VGT_OUT_RECT_V2',
'VGT_OUT_RECT_V3', 'VGT_OUT_TRI', 'VGT_OUT_TRI_ADJ',
'VGT_POLICY_BYPASS', 'VGT_POLICY_LRU', 'VGT_POLICY_STREAM',
'VGT_RDREQ_POLICY', 'VGT_STAGES_ES_EN', 'VGT_STAGES_GS_EN',
'VGT_STAGES_HS_EN', 'VGT_STAGES_LS_EN', 'VGT_STAGES_VS_EN',
'VGT_STREAMOUT_RESET', 'VGT_STREAMOUT_SYNC', 'VGT_TESS_PARTITION',
'VGT_TESS_TOPOLOGY', 'VGT_TESS_TYPE', 'VGT_TE_PRIM_INDEX_LINE',
'VGT_TE_PRIM_INDEX_QUAD', 'VGT_TE_PRIM_INDEX_TRI', 'VGT_TE_QUAD',
'VID_ENHANCED_MODE', 'VID_NORMAL_FRAME_MODE',
'VID_STREAM_DISABLE_MASKED', 'VID_STREAM_DISABLE_UNMASK',
'VMEMCMD_RETURN_IN_ORDER', 'VMEMCMD_RETURN_IN_ORDER_READ',
'VMEMCMD_RETURN_ORDER', 'VMEMCMD_RETURN_OUT_OF_ORDER', 'VMID_SZ',
'VMPG_SIZE', 'VMPG_SIZE_4KB', 'VMPG_SIZE_64KB', 'VM_GROUP_SIZE',
'VM_GROUP_SIZE_1024B', 'VM_GROUP_SIZE_128B',
'VM_GROUP_SIZE_2048B', 'VM_GROUP_SIZE_256B', 'VM_GROUP_SIZE_512B',
'VM_GROUP_SIZE_64B', 'VM_PG_SIZE_1024KB', 'VM_PG_SIZE_128KB',
'VM_PG_SIZE_16KB', 'VM_PG_SIZE_2048KB', 'VM_PG_SIZE_256KB',
'VM_PG_SIZE_32KB', 'VM_PG_SIZE_4KB', 'VM_PG_SIZE_512KB',
'VM_PG_SIZE_64KB', 'VM_PG_SIZE_8KB',
'VPG_MEM_DISABLE_MEM_PWR_CTRL', 'VPG_MEM_ENABLE_MEM_PWR_CTRL',
'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', 'VPG_MEM_NO_FORCE_REQ',
'VPG_MEM_PWR_DIS_CTRL', 'VPG_MEM_PWR_FORCE_CTRL',
'VREADY_AT_OR_AFTER_VSYNC', 'VREADY_BEFORE_VSYNC',
'VRSCombinerModeSC', 'VRS_SHADING_RATE_16X_SSAA',
'VRS_SHADING_RATE_1X1', 'VRS_SHADING_RATE_1X2',
'VRS_SHADING_RATE_2X1', 'VRS_SHADING_RATE_2X2',
'VRS_SHADING_RATE_2X4', 'VRS_SHADING_RATE_2X_SSAA',
'VRS_SHADING_RATE_4X2', 'VRS_SHADING_RATE_4X4',
'VRS_SHADING_RATE_4X_SSAA', 'VRS_SHADING_RATE_8X_SSAA',
'VRS_SHADING_RATE_UNDEFINED0', 'VRS_SHADING_RATE_UNDEFINED1',
'VRS_SHADING_RATE_UNDEFINED2', 'VRS_SHADING_RATE_UNDEFINED3',
'VRS_SHADING_RATE_UNDEFINED4', 'VRSrate', 'VSYNC_CNT_LATCH_MASK',
'VSYNC_CNT_LATCH_MASK_0', 'VSYNC_CNT_LATCH_MASK_1',
'VSYNC_CNT_RESET_SEL', 'VSYNC_CNT_RESET_SEL_0',
'VSYNC_CNT_RESET_SEL_1', 'VS_PARTIAL_FLUSH',
'VS_STAGE_COPY_SHADER', 'VS_STAGE_DS', 'VS_STAGE_REAL',
'VTG_SEL_0', 'VTG_SEL_1', 'VTG_SEL_2', 'VTG_SEL_3', 'VTG_SEL_4',
'VTG_SEL_5', 'WAIT_SYNC', 'WATERMARK_MODE', 'WD_IA_DRAW_REG_XFER',
'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC',
'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE',
'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM',
'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1',
'WD_IA_DRAW_REG_XFER_GE_CNTL',
'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN',
'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM',
'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID',
'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN',
'WD_IA_DRAW_SOURCE', 'WD_IA_DRAW_SOURCE_AUTO',
'WD_IA_DRAW_SOURCE_DMA', 'WD_IA_DRAW_SOURCE_IMMD',
'WD_IA_DRAW_SOURCE_OPAQ', 'WD_IA_DRAW_TYPE',
'WD_IA_DRAW_TYPE_DI_MM0', 'WD_IA_DRAW_TYPE_EVENT_ADDR',
'WD_IA_DRAW_TYPE_EVENT_INIT', 'WD_IA_DRAW_TYPE_IMM_DATA',
'WD_IA_DRAW_TYPE_INDX_OFF', 'WD_IA_DRAW_TYPE_MAX_INDX',
'WD_IA_DRAW_TYPE_MIN_INDX', 'WD_IA_DRAW_TYPE_REG_XFER',
'WRITE_BASE_ONLY', 'WRITE_BOTH', 'WRITE_DATA_addr_incr_enum',
'WRITE_DATA_cache_policy_enum', 'WRITE_DATA_dst_sel_enum',
'WRITE_DATA_wr_confirm_enum', 'WR_CONFIRM', 'WR_ONE_ADDR',
'WritePolicy', 'XNORM', 'XNORM_A', 'XNORM_B',
'XTAL_REF_CLOCK_SOURCE_SEL',
'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK',
'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL',
'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'Y10_CbCr1010_420_PLANAR',
'Y10_CrCb1010_420_PLANAR', 'Y12_CbCr1212_420_PLANAR',
'Y12_CrCb1212_420_PLANAR', 'Y8_CbCr88_420_PLANAR',
'Y8_CrCb88_420_PLANAR', 'YCbYCr10101010_422_PACKED',
'YCbYCr12121212_422_PACKED', 'YCbYCr8888_422_PACKED',
'YCrCbA16161616_10LSB', 'YCrCbA16161616_10MSB',
'YCrCbA16161616_12LSB', 'YCrCbA16161616_12MSB', 'YCrCbA8888',
'YCrYCb10101010_422_PACKED', 'YCrYCb12121212_422_PACKED',
'YCrYCb8888_422_PACKED', 'Y_G_DATA_ONTO_ALPHA_PORT',
'Y_G_DATA_ONTO_CB_B_PORT', 'Y_G_DATA_ONTO_CR_R_PORT',
'Y_G_DATA_ONTO_Y_G_PORT', 'ZLimitSumm', 'ZModeForce', 'ZOrder',
'ZPASS_DISABLE', 'ZPASS_PIXELS', 'ZPASS_SAMPLES',
'ZSamplePosition', 'Z_SAMPLE_CENTER', 'Z_SAMPLE_CENTROID',
'ZpassControl', '__SDMA_V6_0_0_PKT_OPEN_H_', '__maybe_unused',
'_gc_10_3_0_OFFSET_HEADER', '_gc_11_0_0_OFFSET_HEADER',
'_sienna_cichlid_ip_offset_HEADER', '_soc21_ENUM_HEADER',
'addr_incr___write_data__do_not_increment_address',
'addr_incr___write_data__increment_address',
'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT', 'c_uint32', 'c_uint32',
'c_uint32', 'c_uint32', 'c_uint32', 'c_uint32',
'cache_policy___write_data__lru',
'cache_policy___write_data__stream',
'cache_policy__mec_release_mem__lru',
'cache_policy__mec_release_mem__stream',
'data_sel__mec_release_mem__none',
'data_sel__mec_release_mem__send_32_bit_low',
'data_sel__mec_release_mem__send_64_bit_data',
'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo',
'data_sel__mec_release_mem__send_gpu_clock_counter',
'data_sel__mec_release_mem__store_gds_data_to_memory',
'dst_sel___write_data__gds',
'dst_sel___write_data__mem_mapped_register',
'dst_sel___write_data__memory',
'dst_sel___write_data__memory_mapped_adc_persistent_state',
'dst_sel___write_data__tc_l2',
'dst_sel__mec_release_mem__memory_controller',
'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit',
'dst_sel__mec_release_mem__queue_write_pointer_register',
'dst_sel__mec_release_mem__tc_l2',
'event_index__mec_release_mem__end_of_pipe',
'event_index__mec_release_mem__shader_done', 'ge1_assembler_busy',
'ge1_assembler_dma_starved', 'ge1_assembler_stalled',
'ge1_dma_busy', 'ge1_dma_lat_bin_0', 'ge1_dma_lat_bin_1',
'ge1_dma_lat_bin_2', 'ge1_dma_lat_bin_3', 'ge1_dma_lat_bin_4',
'ge1_dma_lat_bin_5', 'ge1_dma_lat_bin_6', 'ge1_dma_lat_bin_7',
'ge1_dma_return_cl0', 'ge1_dma_return_cl1',
'ge1_dma_return_size_cl0', 'ge1_dma_return_size_cl1',
'ge1_dma_utcl1_consecutive_retry_event',
'ge1_dma_utcl1_request_event', 'ge1_dma_utcl1_retry_event',
'ge1_dma_utcl1_stall_event', 'ge1_dma_utcl1_stall_utcl2_event',
'ge1_dma_utcl1_translation_hit_event',
'ge1_dma_utcl1_translation_miss_event', 'ge1_pipe0_to_pipe1',
'ge1_pipe1_to_pipe0', 'ge1_prim_group_limit_hit',
'ge1_rbiu_di_fifo_stalled_p0', 'ge1_rbiu_di_fifo_stalled_p1',
'ge1_rbiu_di_fifo_starved_p0', 'ge1_rbiu_di_fifo_starved_p1',
'ge1_rbiu_dr_fifo_stalled_p0', 'ge1_rbiu_dr_fifo_stalled_p1',
'ge1_rbiu_dr_fifo_starved_p0', 'ge1_rbiu_dr_fifo_starved_p1',
'ge1_sclk_input_vld', 'ge1_sclk_reg_vld',
'ge1_small_draws_one_instance', 'ge1_stat_busy',
'ge1_stat_no_dma_busy', 'ge1_unopt_multi_instance_draws',
'ge_agm_gcr_crd_stall', 'ge_agm_gcr_latency', 'ge_agm_gcr_req',
'ge_agm_gcr_stall', 'ge_agm_gcr_tag_stall', 'ge_all_tf2',
'ge_all_tf3', 'ge_all_tf4', 'ge_all_tf5', 'ge_all_tf6',
'ge_all_tf_eq', 'ge_csb_spi_bp', 'ge_dist_distributer_busy',
'ge_dist_hs_done', 'ge_dist_hs_done_latency',
'ge_dist_hs_done_latency_se0', 'ge_dist_hs_done_latency_se1',
'ge_dist_hs_done_latency_se2', 'ge_dist_hs_done_latency_se3',
'ge_dist_hs_done_latency_se4', 'ge_dist_hs_done_latency_se5',
'ge_dist_hs_done_latency_se6', 'ge_dist_hs_done_latency_se7',
'ge_dist_hs_done_se0', 'ge_dist_hs_done_se1',
'ge_dist_hs_done_se2', 'ge_dist_hs_done_se3',
'ge_dist_hs_done_se4', 'ge_dist_hs_done_se5',
'ge_dist_hs_done_se6', 'ge_dist_hs_done_se7',
'ge_dist_inside_tf_bin_0', 'ge_dist_inside_tf_bin_1',
'ge_dist_inside_tf_bin_2', 'ge_dist_inside_tf_bin_3',
'ge_dist_inside_tf_bin_4', 'ge_dist_inside_tf_bin_5',
'ge_dist_inside_tf_bin_6', 'ge_dist_inside_tf_bin_7',
'ge_dist_inside_tf_bin_8', 'ge_dist_null_patch',
'ge_dist_op_fifo_full_starve', 'ge_dist_pc_feorder_fifo_full',
'ge_dist_pc_ge_manager_busy', 'ge_dist_pc_req_stall_se0',
'ge_dist_pc_req_stall_se1', 'ge_dist_pc_req_stall_se2',
'ge_dist_pc_req_stall_se3', 'ge_dist_pc_req_stall_se4',
'ge_dist_pc_req_stall_se5', 'ge_dist_pc_req_stall_se6',
'ge_dist_pc_req_stall_se7', 'ge_dist_pc_space_zero',
'ge_dist_reserved', 'ge_dist_sclk_core_vld',
'ge_dist_sclk_input_vld', 'ge_dist_sclk_wd_te11_vld',
'ge_dist_switch_mode_stall', 'ge_dist_te11_starved',
'ge_dist_tfreq_lat_bin_0', 'ge_dist_tfreq_lat_bin_1',
'ge_dist_tfreq_lat_bin_2', 'ge_dist_tfreq_lat_bin_3',
'ge_dist_tfreq_lat_bin_4', 'ge_dist_tfreq_lat_bin_5',
'ge_dist_tfreq_lat_bin_6', 'ge_dist_tfreq_lat_bin_7',
'ge_dist_tfreq_utcl1_consecutive_retry_event',
'ge_dist_tfreq_utcl1_request_event',
'ge_dist_tfreq_utcl1_retry_event',
'ge_dist_tfreq_utcl1_stall_event',
'ge_dist_tfreq_utcl1_stall_utcl2_event',
'ge_dist_tfreq_utcl1_translation_hit_event',
'ge_dist_tfreq_utcl1_translation_miss_event',
'ge_dist_vs_pc_stall', 'ge_dist_wd_te11_busy', 'ge_distclk_vld',
'ge_esvert_send', 'ge_gs_issue_rtr_stalled', 'ge_gsprim_send',
'ge_gsprim_stalled_esvert', 'ge_gsthread_stalled',
'ge_hs_stall_tfmm_fifo_full', 'ge_hs_tif_stall',
'ge_ngg_agm_req_stall', 'ge_ngg_attr_discard_alloc',
'ge_ngg_attr_grp_alloc', 'ge_ngg_attr_grp_latency',
'ge_ngg_indx_bus_stall', 'ge_ngg_ord_id_req_stall',
'ge_ngg_pc_space_not_avail', 'ge_ngg_reuse_prim_limit_hit',
'ge_ngg_reuse_vert_limit_hit', 'ge_ngg_spi_esvert_partial_eov',
'ge_ngg_spi_gsprim_partial_eov', 'ge_ngg_stall_tess_off_tess_on',
'ge_ngg_stall_tess_on_tess_off', 'ge_ngg_starved_after_work',
'ge_ngg_starved_idle', 'ge_ngg_starving_for_pc_grant',
'ge_ngg_subgrp_fifo_stall', 'ge_num_of_donut_dist_patches',
'ge_num_of_hs_alloc_events', 'ge_num_of_no_dist_patches',
'ge_num_of_patch_dist_patches',
'ge_num_of_se_switches_due_to_donut',
'ge_num_of_se_switches_due_to_patch_accum',
'ge_num_of_se_switches_due_to_trap', 'ge_pa0_csb_eop',
'ge_pa1_csb_eop', 'ge_se0_te11_starved_on_hs_done',
'ge_se1_te11_starved_on_hs_done',
'ge_se2_te11_starved_on_hs_done',
'ge_se3_te11_starved_on_hs_done',
'ge_se4_te11_starved_on_hs_done',
'ge_se5_te11_starved_on_hs_done',
'ge_se6_te11_starved_on_hs_done',
'ge_se7_te11_starved_on_hs_done', 'ge_se_ds_prims',
'ge_se_es_thread_groups', 'ge_se_esvert_stalled_gsprim',
'ge_se_hs_input_stall', 'ge_se_hs_tfm_stall',
'ge_se_hs_tgs_active_high_water_mark', 'ge_se_hs_thread_groups',
'ge_se_reused_es_indices', 'ge_se_sclk_input_vld',
'ge_se_sclk_ngg_vld', 'ge_se_sclk_te11_vld',
'ge_se_sending_vert_or_prim', 'ge_se_spi_esvert_eov',
'ge_se_spi_esvert_stalled', 'ge_se_spi_esvert_starved_busy',
'ge_se_spi_esvert_valid', 'ge_se_spi_gsprim_cont',
'ge_se_spi_gsprim_eov', 'ge_se_spi_gsprim_stalled',
'ge_se_spi_gsprim_starved_busy', 'ge_se_spi_gsprim_valid',
'ge_se_spi_gssubgrp_event_window_active',
'ge_se_spi_gssubgrp_is_event', 'ge_se_spi_gssubgrp_send',
'ge_se_spi_hsvert_eov', 'ge_se_spi_hsvert_fifo_full_stall',
'ge_se_spi_hsvert_stalled', 'ge_se_spi_hsvert_starved_busy',
'ge_se_spi_hsvert_valid', 'ge_se_spi_hswave_is_event',
'ge_se_spi_hswave_send', 'ge_se_spi_lsvert_eov',
'ge_se_spi_lsvert_stalled', 'ge_se_spi_lsvert_starved_busy',
'ge_se_spi_lsvert_valid', 'ge_se_spi_tgrp_fifo_stall',
'ge_spi_gsgrp_valid', 'ge_spi_hsgrp_spi_stall',
'ge_spi_hswave_fifo_full_stall', 'ge_spi_lswave_fifo_full_stall',
'ge_te11_compactor_starved', 'ge_te11_con_stall',
'ge_te11_stall_prim_funnel', 'ge_te11_stall_vert_funnel',
'ge_tf_ret_data_stalling_hs_done', 'hdp_flush_cmd', 'int32_t',
'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare',
'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare',
'int_sel__mec_release_mem__none',
'int_sel__mec_release_mem__send_data_after_write_confirm',
'int_sel__mec_release_mem__send_interrupt_after_write_confirm',
'int_sel__mec_release_mem__send_interrupt_only',
'int_sel__mec_release_mem__unconditionally_send_int_ctxid',
'ixDIDT_DB_CTRL0', 'ixDIDT_DB_CTRL1', 'ixDIDT_DB_CTRL2',
'ixDIDT_DB_CTRL3', 'ixDIDT_DB_CTRL_OCP', 'ixDIDT_DB_EDC_CTRL',
'ixDIDT_DB_EDC_OVERFLOW', 'ixDIDT_DB_EDC_PCC_PERF_COUNTER',
'ixDIDT_DB_EDC_ROLLING_POWER_DELTA',
'ixDIDT_DB_EDC_STALL_DELAY_1', 'ixDIDT_DB_EDC_STALL_PATTERN_1_2',
'ixDIDT_DB_EDC_STALL_PATTERN_3_4',
'ixDIDT_DB_EDC_STALL_PATTERN_5_6',
'ixDIDT_DB_EDC_STALL_PATTERN_7', 'ixDIDT_DB_EDC_STATUS',
'ixDIDT_DB_EDC_THRESHOLD', 'ixDIDT_DB_EDC_TIMER_PERIOD',
'ixDIDT_DB_MPD_SCALE_FACTOR', 'ixDIDT_DB_STALL_AUTO_RELEASE_CTRL',
'ixDIDT_DB_STALL_CTRL', 'ixDIDT_DB_STALL_EVENT_COUNTER',
'ixDIDT_DB_STALL_PATTERN_1_2', 'ixDIDT_DB_STALL_PATTERN_3_4',
'ixDIDT_DB_STALL_PATTERN_5_6', 'ixDIDT_DB_STALL_PATTERN_7',
'ixDIDT_DB_STALL_RELEASE_CNTL0', 'ixDIDT_DB_STALL_RELEASE_CNTL1',
'ixDIDT_DB_STALL_RELEASE_CNTL_STATUS', 'ixDIDT_DB_THROTTLE_CTRL',
'ixDIDT_DB_TUNING_CTRL', 'ixDIDT_DB_WEIGHT0_3',
'ixDIDT_DB_WEIGHT4_7', 'ixDIDT_DB_WEIGHT8_11', 'ixDIDT_SQ_CTRL0',
'ixDIDT_SQ_CTRL1', 'ixDIDT_SQ_CTRL2', 'ixDIDT_SQ_CTRL3',
'ixDIDT_SQ_CTRL_OCP', 'ixDIDT_SQ_EDC_CTRL',
'ixDIDT_SQ_EDC_OVERFLOW', 'ixDIDT_SQ_EDC_PCC_PERF_COUNTER',
'ixDIDT_SQ_EDC_ROLLING_POWER_DELTA',
'ixDIDT_SQ_EDC_STALL_DELAY_1', 'ixDIDT_SQ_EDC_STALL_DELAY_2',
'ixDIDT_SQ_EDC_STALL_DELAY_3', 'ixDIDT_SQ_EDC_STALL_PATTERN_1_2',
'ixDIDT_SQ_EDC_STALL_PATTERN_3_4',
'ixDIDT_SQ_EDC_STALL_PATTERN_5_6',
'ixDIDT_SQ_EDC_STALL_PATTERN_7', 'ixDIDT_SQ_EDC_STATUS',
'ixDIDT_SQ_EDC_THRESHOLD', 'ixDIDT_SQ_EDC_TIMER_PERIOD',
'ixDIDT_SQ_MPD_SCALE_FACTOR', 'ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL',
'ixDIDT_SQ_STALL_CTRL', 'ixDIDT_SQ_STALL_EVENT_COUNTER',
'ixDIDT_SQ_STALL_PATTERN_1_2', 'ixDIDT_SQ_STALL_PATTERN_3_4',
'ixDIDT_SQ_STALL_PATTERN_5_6', 'ixDIDT_SQ_STALL_PATTERN_7',
'ixDIDT_SQ_STALL_RELEASE_CNTL0', 'ixDIDT_SQ_STALL_RELEASE_CNTL1',
'ixDIDT_SQ_STALL_RELEASE_CNTL_STATUS', 'ixDIDT_SQ_THROTTLE_CTRL',
'ixDIDT_SQ_TUNING_CTRL', 'ixDIDT_SQ_WEIGHT0_3',
'ixDIDT_SQ_WEIGHT4_7', 'ixDIDT_SQ_WEIGHT8_11', 'ixDIDT_TCP_CTRL0',
'ixDIDT_TCP_CTRL1', 'ixDIDT_TCP_CTRL2', 'ixDIDT_TCP_CTRL3',
'ixDIDT_TCP_CTRL_OCP', 'ixDIDT_TCP_EDC_CTRL',
'ixDIDT_TCP_EDC_OVERFLOW', 'ixDIDT_TCP_EDC_PCC_PERF_COUNTER',
'ixDIDT_TCP_EDC_ROLLING_POWER_DELTA',
'ixDIDT_TCP_EDC_STALL_DELAY_1', 'ixDIDT_TCP_EDC_STALL_DELAY_2',
'ixDIDT_TCP_EDC_STALL_DELAY_3',
'ixDIDT_TCP_EDC_STALL_PATTERN_1_2',
'ixDIDT_TCP_EDC_STALL_PATTERN_3_4',
'ixDIDT_TCP_EDC_STALL_PATTERN_5_6',
'ixDIDT_TCP_EDC_STALL_PATTERN_7', 'ixDIDT_TCP_EDC_STATUS',
'ixDIDT_TCP_EDC_THRESHOLD', 'ixDIDT_TCP_EDC_TIMER_PERIOD',
'ixDIDT_TCP_MPD_SCALE_FACTOR',
'ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL', 'ixDIDT_TCP_STALL_CTRL',
'ixDIDT_TCP_STALL_EVENT_COUNTER', 'ixDIDT_TCP_STALL_PATTERN_1_2',
'ixDIDT_TCP_STALL_PATTERN_3_4', 'ixDIDT_TCP_STALL_PATTERN_5_6',
'ixDIDT_TCP_STALL_PATTERN_7', 'ixDIDT_TCP_STALL_RELEASE_CNTL0',
'ixDIDT_TCP_STALL_RELEASE_CNTL1',
'ixDIDT_TCP_STALL_RELEASE_CNTL_STATUS',
'ixDIDT_TCP_THROTTLE_CTRL', 'ixDIDT_TCP_TUNING_CTRL',
'ixDIDT_TCP_WEIGHT0_3', 'ixDIDT_TCP_WEIGHT4_7',
'ixDIDT_TCP_WEIGHT8_11', 'ixDIDT_TD_CTRL0', 'ixDIDT_TD_CTRL1',
'ixDIDT_TD_CTRL2', 'ixDIDT_TD_CTRL3', 'ixDIDT_TD_CTRL_OCP',
'ixDIDT_TD_EDC_CTRL', 'ixDIDT_TD_EDC_OVERFLOW',
'ixDIDT_TD_EDC_PCC_PERF_COUNTER',
'ixDIDT_TD_EDC_ROLLING_POWER_DELTA',
'ixDIDT_TD_EDC_STALL_DELAY_1', 'ixDIDT_TD_EDC_STALL_DELAY_2',
'ixDIDT_TD_EDC_STALL_DELAY_3', 'ixDIDT_TD_EDC_STALL_PATTERN_1_2',
'ixDIDT_TD_EDC_STALL_PATTERN_3_4',
'ixDIDT_TD_EDC_STALL_PATTERN_5_6',
'ixDIDT_TD_EDC_STALL_PATTERN_7', 'ixDIDT_TD_EDC_STATUS',
'ixDIDT_TD_EDC_THRESHOLD', 'ixDIDT_TD_EDC_TIMER_PERIOD',
'ixDIDT_TD_MPD_SCALE_FACTOR', 'ixDIDT_TD_STALL_AUTO_RELEASE_CTRL',
'ixDIDT_TD_STALL_CTRL', 'ixDIDT_TD_STALL_EVENT_COUNTER',
'ixDIDT_TD_STALL_PATTERN_1_2', 'ixDIDT_TD_STALL_PATTERN_3_4',
'ixDIDT_TD_STALL_PATTERN_5_6', 'ixDIDT_TD_STALL_PATTERN_7',
'ixDIDT_TD_STALL_RELEASE_CNTL0', 'ixDIDT_TD_STALL_RELEASE_CNTL1',
'ixDIDT_TD_STALL_RELEASE_CNTL_STATUS', 'ixDIDT_TD_THROTTLE_CTRL',
'ixDIDT_TD_TUNING_CTRL', 'ixDIDT_TD_WEIGHT0_3',
'ixDIDT_TD_WEIGHT4_7', 'ixDIDT_TD_WEIGHT8_11',
'ixEDC_STRETCH_NUM_PERF_COUNTER', 'ixEDC_STRETCH_PERF_COUNTER',
'ixEDC_UNSTRETCH_PERF_COUNTER', 'ixFIXED_PATTERN_PERF_COUNTER_1',
'ixFIXED_PATTERN_PERF_COUNTER_10',
'ixFIXED_PATTERN_PERF_COUNTER_2',
'ixFIXED_PATTERN_PERF_COUNTER_3',
'ixFIXED_PATTERN_PERF_COUNTER_4',
'ixFIXED_PATTERN_PERF_COUNTER_5',
'ixFIXED_PATTERN_PERF_COUNTER_6',
'ixFIXED_PATTERN_PERF_COUNTER_7',
'ixFIXED_PATTERN_PERF_COUNTER_8',
'ixFIXED_PATTERN_PERF_COUNTER_9', 'ixGC_CAC_ACC_BCI0',
'ixGC_CAC_ACC_BCI1', 'ixGC_CAC_ACC_CB0', 'ixGC_CAC_ACC_CB1',
'ixGC_CAC_ACC_CB2', 'ixGC_CAC_ACC_CB3', 'ixGC_CAC_ACC_CB4',
'ixGC_CAC_ACC_CB5', 'ixGC_CAC_ACC_CB6', 'ixGC_CAC_ACC_CB7',
'ixGC_CAC_ACC_CB8', 'ixGC_CAC_ACC_CB9', 'ixGC_CAC_ACC_CHC0',
'ixGC_CAC_ACC_CHC1', 'ixGC_CAC_ACC_CHC2', 'ixGC_CAC_ACC_CP0',
'ixGC_CAC_ACC_CP1', 'ixGC_CAC_ACC_CP2', 'ixGC_CAC_ACC_CU0',
'ixGC_CAC_ACC_DB0', 'ixGC_CAC_ACC_DB1', 'ixGC_CAC_ACC_DB2',
'ixGC_CAC_ACC_DB3', 'ixGC_CAC_ACC_DB4', 'ixGC_CAC_ACC_DB5',
'ixGC_CAC_ACC_DB6', 'ixGC_CAC_ACC_DB7', 'ixGC_CAC_ACC_DB8',
'ixGC_CAC_ACC_DB9', 'ixGC_CAC_ACC_EA0', 'ixGC_CAC_ACC_EA1',
'ixGC_CAC_ACC_EA2', 'ixGC_CAC_ACC_EA3', 'ixGC_CAC_ACC_EA4',
'ixGC_CAC_ACC_EA5', 'ixGC_CAC_ACC_GDS0', 'ixGC_CAC_ACC_GDS1',
'ixGC_CAC_ACC_GDS2', 'ixGC_CAC_ACC_GDS3', 'ixGC_CAC_ACC_GDS4',
'ixGC_CAC_ACC_GDS5', 'ixGC_CAC_ACC_GDS6', 'ixGC_CAC_ACC_GE0',
'ixGC_CAC_ACC_GE1', 'ixGC_CAC_ACC_GE10', 'ixGC_CAC_ACC_GE11',
'ixGC_CAC_ACC_GE12', 'ixGC_CAC_ACC_GE13', 'ixGC_CAC_ACC_GE14',
'ixGC_CAC_ACC_GE15', 'ixGC_CAC_ACC_GE16', 'ixGC_CAC_ACC_GE17',
'ixGC_CAC_ACC_GE18', 'ixGC_CAC_ACC_GE19', 'ixGC_CAC_ACC_GE2',
'ixGC_CAC_ACC_GE20', 'ixGC_CAC_ACC_GE3', 'ixGC_CAC_ACC_GE4',
'ixGC_CAC_ACC_GE5', 'ixGC_CAC_ACC_GE6', 'ixGC_CAC_ACC_GE7',
'ixGC_CAC_ACC_GE8', 'ixGC_CAC_ACC_GE9', 'ixGC_CAC_ACC_GL1C0',
'ixGC_CAC_ACC_GL1C1', 'ixGC_CAC_ACC_GL1C2', 'ixGC_CAC_ACC_GL1C3',
'ixGC_CAC_ACC_GL1C4', 'ixGC_CAC_ACC_GL2C0', 'ixGC_CAC_ACC_GL2C1',
'ixGC_CAC_ACC_GL2C2', 'ixGC_CAC_ACC_GL2C3', 'ixGC_CAC_ACC_GL2C4',
'ixGC_CAC_ACC_GUS0', 'ixGC_CAC_ACC_GUS1', 'ixGC_CAC_ACC_GUS2',
'ixGC_CAC_ACC_LDS0', 'ixGC_CAC_ACC_LDS1', 'ixGC_CAC_ACC_LDS2',
'ixGC_CAC_ACC_LDS3', 'ixGC_CAC_ACC_LDS4', 'ixGC_CAC_ACC_LDS5',
'ixGC_CAC_ACC_LDS6', 'ixGC_CAC_ACC_LDS7', 'ixGC_CAC_ACC_LDS8',
'ixGC_CAC_ACC_PA0', 'ixGC_CAC_ACC_PA1', 'ixGC_CAC_ACC_PA2',
'ixGC_CAC_ACC_PA3', 'ixGC_CAC_ACC_PA4', 'ixGC_CAC_ACC_PA5',
'ixGC_CAC_ACC_PA6', 'ixGC_CAC_ACC_PA7', 'ixGC_CAC_ACC_PC0',
'ixGC_CAC_ACC_PH0', 'ixGC_CAC_ACC_PH1', 'ixGC_CAC_ACC_PH2',
'ixGC_CAC_ACC_PH3', 'ixGC_CAC_ACC_PH4', 'ixGC_CAC_ACC_PH5',
'ixGC_CAC_ACC_PH6', 'ixGC_CAC_ACC_PH7', 'ixGC_CAC_ACC_PMM0',
'ixGC_CAC_ACC_RLC0', 'ixGC_CAC_ACC_RMI0', 'ixGC_CAC_ACC_RMI1',
'ixGC_CAC_ACC_RMI2', 'ixGC_CAC_ACC_RMI3', 'ixGC_CAC_ACC_SC0',
'ixGC_CAC_ACC_SC1', 'ixGC_CAC_ACC_SC2', 'ixGC_CAC_ACC_SC3',
'ixGC_CAC_ACC_SC4', 'ixGC_CAC_ACC_SC5', 'ixGC_CAC_ACC_SC6',
'ixGC_CAC_ACC_SC7', 'ixGC_CAC_ACC_SDMA0', 'ixGC_CAC_ACC_SDMA1',
'ixGC_CAC_ACC_SDMA10', 'ixGC_CAC_ACC_SDMA11',
'ixGC_CAC_ACC_SDMA2', 'ixGC_CAC_ACC_SDMA3', 'ixGC_CAC_ACC_SDMA4',
'ixGC_CAC_ACC_SDMA5', 'ixGC_CAC_ACC_SDMA6', 'ixGC_CAC_ACC_SDMA7',
'ixGC_CAC_ACC_SDMA8', 'ixGC_CAC_ACC_SDMA9',
'ixGC_CAC_ACC_SP0_LOWER', 'ixGC_CAC_ACC_SP0_UPPER',
'ixGC_CAC_ACC_SP1_LOWER', 'ixGC_CAC_ACC_SP1_UPPER',
'ixGC_CAC_ACC_SP2_LOWER', 'ixGC_CAC_ACC_SP2_UPPER',
'ixGC_CAC_ACC_SPI0', 'ixGC_CAC_ACC_SPI1', 'ixGC_CAC_ACC_SPI2',
'ixGC_CAC_ACC_SPI3', 'ixGC_CAC_ACC_SPI4', 'ixGC_CAC_ACC_SPI5',
'ixGC_CAC_ACC_SQ0_LOWER', 'ixGC_CAC_ACC_SQ0_UPPER',
'ixGC_CAC_ACC_SQ1_LOWER', 'ixGC_CAC_ACC_SQ1_UPPER',
'ixGC_CAC_ACC_SQ2_LOWER', 'ixGC_CAC_ACC_SQ2_UPPER',
'ixGC_CAC_ACC_SQ3_LOWER', 'ixGC_CAC_ACC_SQ3_UPPER',
'ixGC_CAC_ACC_SQ4_LOWER', 'ixGC_CAC_ACC_SQ4_UPPER',
'ixGC_CAC_ACC_SQ5_LOWER', 'ixGC_CAC_ACC_SQ5_UPPER',
'ixGC_CAC_ACC_SQ6_LOWER', 'ixGC_CAC_ACC_SQ6_UPPER',
'ixGC_CAC_ACC_SQ7_LOWER', 'ixGC_CAC_ACC_SQ7_UPPER',
'ixGC_CAC_ACC_SQ8_LOWER', 'ixGC_CAC_ACC_SQ8_UPPER',
'ixGC_CAC_ACC_SQC0', 'ixGC_CAC_ACC_SQC1', 'ixGC_CAC_ACC_SQC2',
'ixGC_CAC_ACC_SX0', 'ixGC_CAC_ACC_SXRB0', 'ixGC_CAC_ACC_TA0',
'ixGC_CAC_ACC_TCP0', 'ixGC_CAC_ACC_TCP1', 'ixGC_CAC_ACC_TCP2',
'ixGC_CAC_ACC_TCP3', 'ixGC_CAC_ACC_TCP4', 'ixGC_CAC_ACC_TCP5',
'ixGC_CAC_ACC_TCP6', 'ixGC_CAC_ACC_TCP7', 'ixGC_CAC_ACC_TD0',
'ixGC_CAC_ACC_TD1', 'ixGC_CAC_ACC_TD10', 'ixGC_CAC_ACC_TD2',
'ixGC_CAC_ACC_TD3', 'ixGC_CAC_ACC_TD4', 'ixGC_CAC_ACC_TD5',
'ixGC_CAC_ACC_TD6', 'ixGC_CAC_ACC_TD7', 'ixGC_CAC_ACC_TD8',
'ixGC_CAC_ACC_TD9', 'ixGC_CAC_ACC_UTCL10',
'ixGC_CAC_ACC_UTCL2_ATCL20', 'ixGC_CAC_ACC_UTCL2_ATCL21',
'ixGC_CAC_ACC_UTCL2_ATCL22', 'ixGC_CAC_ACC_UTCL2_ATCL23',
'ixGC_CAC_ACC_UTCL2_ATCL24', 'ixGC_CAC_ACC_UTCL2_ROUTER0',
'ixGC_CAC_ACC_UTCL2_ROUTER1', 'ixGC_CAC_ACC_UTCL2_ROUTER2',
'ixGC_CAC_ACC_UTCL2_ROUTER3', 'ixGC_CAC_ACC_UTCL2_ROUTER4',
'ixGC_CAC_ACC_UTCL2_ROUTER5', 'ixGC_CAC_ACC_UTCL2_ROUTER6',
'ixGC_CAC_ACC_UTCL2_ROUTER7', 'ixGC_CAC_ACC_UTCL2_ROUTER8',
'ixGC_CAC_ACC_UTCL2_ROUTER9', 'ixGC_CAC_ACC_UTCL2_VML20',
'ixGC_CAC_ACC_UTCL2_VML21', 'ixGC_CAC_ACC_UTCL2_VML22',
'ixGC_CAC_ACC_UTCL2_VML23', 'ixGC_CAC_ACC_UTCL2_VML24',
'ixGC_CAC_ACC_UTCL2_WALKER0', 'ixGC_CAC_ACC_UTCL2_WALKER1',
'ixGC_CAC_ACC_UTCL2_WALKER2', 'ixGC_CAC_ACC_UTCL2_WALKER3',
'ixGC_CAC_ACC_UTCL2_WALKER4', 'ixGC_CAC_CNTL', 'ixGC_CAC_ID',
'ixGC_CAC_OVRD_BCI', 'ixGC_CAC_OVRD_CB', 'ixGC_CAC_OVRD_CHC',
'ixGC_CAC_OVRD_CP', 'ixGC_CAC_OVRD_CU', 'ixGC_CAC_OVRD_DB',
'ixGC_CAC_OVRD_EA', 'ixGC_CAC_OVRD_GDS', 'ixGC_CAC_OVRD_GE',
'ixGC_CAC_OVRD_GE_HI', 'ixGC_CAC_OVRD_GL1C', 'ixGC_CAC_OVRD_GL2C',
'ixGC_CAC_OVRD_GUS', 'ixGC_CAC_OVRD_LDS', 'ixGC_CAC_OVRD_PA',
'ixGC_CAC_OVRD_PC', 'ixGC_CAC_OVRD_PH', 'ixGC_CAC_OVRD_PMM',
'ixGC_CAC_OVRD_RLC', 'ixGC_CAC_OVRD_RMI', 'ixGC_CAC_OVRD_SC',
'ixGC_CAC_OVRD_SDMA', 'ixGC_CAC_OVRD_SP', 'ixGC_CAC_OVRD_SPI',
'ixGC_CAC_OVRD_SQ', 'ixGC_CAC_OVRD_SQC', 'ixGC_CAC_OVRD_SX',
'ixGC_CAC_OVRD_SXRB', 'ixGC_CAC_OVRD_TA', 'ixGC_CAC_OVRD_TCP',
'ixGC_CAC_OVRD_TD', 'ixGC_CAC_OVRD_UTCL1',
'ixGC_CAC_OVRD_UTCL2_ATCL2', 'ixGC_CAC_OVRD_UTCL2_ROUTER',
'ixGC_CAC_OVRD_UTCL2_VML2', 'ixGC_CAC_OVRD_UTCL2_WALKER',
'ixGC_CAC_OVR_SEL', 'ixGC_CAC_OVR_VAL', 'ixGC_CAC_WEIGHT_BCI_0',
'ixGC_CAC_WEIGHT_CB_0', 'ixGC_CAC_WEIGHT_CB_1',
'ixGC_CAC_WEIGHT_CB_2', 'ixGC_CAC_WEIGHT_CB_3',
'ixGC_CAC_WEIGHT_CB_4', 'ixGC_CAC_WEIGHT_CHC_0',
'ixGC_CAC_WEIGHT_CHC_1', 'ixGC_CAC_WEIGHT_CP_0',
'ixGC_CAC_WEIGHT_CP_1', 'ixGC_CAC_WEIGHT_CU_0',
'ixGC_CAC_WEIGHT_DB_0', 'ixGC_CAC_WEIGHT_DB_1',
'ixGC_CAC_WEIGHT_DB_2', 'ixGC_CAC_WEIGHT_DB_3',
'ixGC_CAC_WEIGHT_DB_4', 'ixGC_CAC_WEIGHT_EA_0',
'ixGC_CAC_WEIGHT_EA_1', 'ixGC_CAC_WEIGHT_EA_2',
'ixGC_CAC_WEIGHT_GDS_0', 'ixGC_CAC_WEIGHT_GDS_1',
'ixGC_CAC_WEIGHT_GDS_2', 'ixGC_CAC_WEIGHT_GE_0',
'ixGC_CAC_WEIGHT_GE_1', 'ixGC_CAC_WEIGHT_GE_10',
'ixGC_CAC_WEIGHT_GE_2', 'ixGC_CAC_WEIGHT_GE_3',
'ixGC_CAC_WEIGHT_GE_4', 'ixGC_CAC_WEIGHT_GE_5',
'ixGC_CAC_WEIGHT_GE_6', 'ixGC_CAC_WEIGHT_GE_7',
'ixGC_CAC_WEIGHT_GE_8', 'ixGC_CAC_WEIGHT_GE_9',
'ixGC_CAC_WEIGHT_GL1C_0', 'ixGC_CAC_WEIGHT_GL1C_1',
'ixGC_CAC_WEIGHT_GL1C_2', 'ixGC_CAC_WEIGHT_GL2C_0',
'ixGC_CAC_WEIGHT_GL2C_1', 'ixGC_CAC_WEIGHT_GL2C_2',
'ixGC_CAC_WEIGHT_GUS_0', 'ixGC_CAC_WEIGHT_GUS_1',
'ixGC_CAC_WEIGHT_LDS_0', 'ixGC_CAC_WEIGHT_LDS_1',
'ixGC_CAC_WEIGHT_LDS_2', 'ixGC_CAC_WEIGHT_LDS_3',
'ixGC_CAC_WEIGHT_LDS_4', 'ixGC_CAC_WEIGHT_PA_0',
'ixGC_CAC_WEIGHT_PA_1', 'ixGC_CAC_WEIGHT_PA_2',
'ixGC_CAC_WEIGHT_PA_3', 'ixGC_CAC_WEIGHT_PC_0',
'ixGC_CAC_WEIGHT_PH_0', 'ixGC_CAC_WEIGHT_PH_1',
'ixGC_CAC_WEIGHT_PH_2', 'ixGC_CAC_WEIGHT_PH_3',
'ixGC_CAC_WEIGHT_PMM_0', 'ixGC_CAC_WEIGHT_RLC_0',
'ixGC_CAC_WEIGHT_RMI_0', 'ixGC_CAC_WEIGHT_RMI_1',
'ixGC_CAC_WEIGHT_SC_0', 'ixGC_CAC_WEIGHT_SC_1',
'ixGC_CAC_WEIGHT_SC_2', 'ixGC_CAC_WEIGHT_SC_3',
'ixGC_CAC_WEIGHT_SDMA_0', 'ixGC_CAC_WEIGHT_SDMA_1',
'ixGC_CAC_WEIGHT_SDMA_2', 'ixGC_CAC_WEIGHT_SDMA_3',
'ixGC_CAC_WEIGHT_SDMA_4', 'ixGC_CAC_WEIGHT_SDMA_5',
'ixGC_CAC_WEIGHT_SPI_0', 'ixGC_CAC_WEIGHT_SPI_1',
'ixGC_CAC_WEIGHT_SPI_2', 'ixGC_CAC_WEIGHT_SP_0',
'ixGC_CAC_WEIGHT_SP_1', 'ixGC_CAC_WEIGHT_SQC_0',
'ixGC_CAC_WEIGHT_SQC_1', 'ixGC_CAC_WEIGHT_SQ_0',
'ixGC_CAC_WEIGHT_SQ_1', 'ixGC_CAC_WEIGHT_SQ_2',
'ixGC_CAC_WEIGHT_SQ_3', 'ixGC_CAC_WEIGHT_SXRB_0',
'ixGC_CAC_WEIGHT_SX_0', 'ixGC_CAC_WEIGHT_TA_0',
'ixGC_CAC_WEIGHT_TCP_0', 'ixGC_CAC_WEIGHT_TCP_1',
'ixGC_CAC_WEIGHT_TCP_2', 'ixGC_CAC_WEIGHT_TCP_3',
'ixGC_CAC_WEIGHT_TD_0', 'ixGC_CAC_WEIGHT_TD_1',
'ixGC_CAC_WEIGHT_TD_2', 'ixGC_CAC_WEIGHT_TD_3',
'ixGC_CAC_WEIGHT_TD_4', 'ixGC_CAC_WEIGHT_TD_5',
'ixGC_CAC_WEIGHT_UTCL1_0', 'ixGC_CAC_WEIGHT_UTCL2_ATCL2_0',
'ixGC_CAC_WEIGHT_UTCL2_ATCL2_1', 'ixGC_CAC_WEIGHT_UTCL2_ATCL2_2',
'ixGC_CAC_WEIGHT_UTCL2_ROUTER_0',
'ixGC_CAC_WEIGHT_UTCL2_ROUTER_1',
'ixGC_CAC_WEIGHT_UTCL2_ROUTER_2',
'ixGC_CAC_WEIGHT_UTCL2_ROUTER_3',
'ixGC_CAC_WEIGHT_UTCL2_ROUTER_4', 'ixGC_CAC_WEIGHT_UTCL2_VML2_0',
'ixGC_CAC_WEIGHT_UTCL2_VML2_1', 'ixGC_CAC_WEIGHT_UTCL2_VML2_2',
'ixGC_CAC_WEIGHT_UTCL2_WALKER_0',
'ixGC_CAC_WEIGHT_UTCL2_WALKER_1',
'ixGC_CAC_WEIGHT_UTCL2_WALKER_2', 'ixGLB_ATCL2_SAMPLEDELAY',
'ixGLB_CHA_SAMPLEDELAY', 'ixGLB_CHC0_SAMPLEDELAY',
'ixGLB_CHC1_SAMPLEDELAY', 'ixGLB_CHC2_SAMPLEDELAY',
'ixGLB_CHC3_SAMPLEDELAY', 'ixGLB_CHCG_SAMPLEDELAY',
'ixGLB_CPC_SAMPLEDELAY', 'ixGLB_CPF_SAMPLEDELAY',
'ixGLB_CPG_SAMPLEDELAY', 'ixGLB_EA0_SAMPLEDELAY',
'ixGLB_EA10_SAMPLEDELAY', 'ixGLB_EA11_SAMPLEDELAY',
'ixGLB_EA12_SAMPLEDELAY', 'ixGLB_EA13_SAMPLEDELAY',
'ixGLB_EA14_SAMPLEDELAY', 'ixGLB_EA15_SAMPLEDELAY',
'ixGLB_EA1_SAMPLEDELAY', 'ixGLB_EA2_SAMPLEDELAY',
'ixGLB_EA3_SAMPLEDELAY', 'ixGLB_EA4_SAMPLEDELAY',
'ixGLB_EA5_SAMPLEDELAY', 'ixGLB_EA6_SAMPLEDELAY',
'ixGLB_EA7_SAMPLEDELAY', 'ixGLB_EA8_SAMPLEDELAY',
'ixGLB_EA9_SAMPLEDELAY', 'ixGLB_GCR_SAMPLEDELAY',
'ixGLB_GDS_SAMPLEDELAY', 'ixGLB_GE1_SAMPLEDELAY',
'ixGLB_GE2DIST_SAMPLEDELAY', 'ixGLB_GE2SE0_SAMPLEDELAY',
'ixGLB_GE2SE1_SAMPLEDELAY', 'ixGLB_GE2SE2_SAMPLEDELAY',
'ixGLB_GE2SE3_SAMPLEDELAY', 'ixGLB_GL2A0_SAMPLEDELAY',
'ixGLB_GL2A1_SAMPLEDELAY', 'ixGLB_GL2A2_SAMPLEDELAY',
'ixGLB_GL2A3_SAMPLEDELAY', 'ixGLB_GL2C0_SAMPLEDELAY',
'ixGLB_GL2C10_SAMPLEDELAY', 'ixGLB_GL2C11_SAMPLEDELAY',
'ixGLB_GL2C12_SAMPLEDELAY', 'ixGLB_GL2C13_SAMPLEDELAY',
'ixGLB_GL2C14_SAMPLEDELAY', 'ixGLB_GL2C15_SAMPLEDELAY',
'ixGLB_GL2C1_SAMPLEDELAY', 'ixGLB_GL2C2_SAMPLEDELAY',
'ixGLB_GL2C3_SAMPLEDELAY', 'ixGLB_GL2C4_SAMPLEDELAY',
'ixGLB_GL2C5_SAMPLEDELAY', 'ixGLB_GL2C6_SAMPLEDELAY',
'ixGLB_GL2C7_SAMPLEDELAY', 'ixGLB_GL2C8_SAMPLEDELAY',
'ixGLB_GL2C9_SAMPLEDELAY', 'ixGLB_GUS_SAMPLEDELAY',
'ixGLB_PH_SAMPLEDELAY', 'ixGLB_SDMA0_SAMPLEDELAY',
'ixGLB_SDMA1_SAMPLEDELAY', 'ixGLB_SDMA2_SAMPLEDELAY',
'ixGLB_SDMA3_SAMPLEDELAY', 'ixGLB_VML2_SAMPLEDELAY',
'ixHW_LUT_UPDATE_STATUS', 'ixPCC_PWRBRK_HYSTERESIS_CTRL',
'ixPCC_STALL_PATTERN_1_2', 'ixPCC_STALL_PATTERN_3_4',
'ixPCC_STALL_PATTERN_5_6', 'ixPCC_STALL_PATTERN_7',
'ixPCC_STALL_PATTERN_CTRL', 'ixPWRBRK_RELEASE_TO_STALL_LUT_17_20',
'ixPWRBRK_RELEASE_TO_STALL_LUT_1_8',
'ixPWRBRK_RELEASE_TO_STALL_LUT_9_16',
'ixPWRBRK_STALL_PATTERN_1_2', 'ixPWRBRK_STALL_PATTERN_3_4',
'ixPWRBRK_STALL_PATTERN_5_6', 'ixPWRBRK_STALL_PATTERN_7',
'ixPWRBRK_STALL_PATTERN_CTRL',
'ixPWRBRK_STALL_TO_RELEASE_LUT_1_4',
'ixPWRBRK_STALL_TO_RELEASE_LUT_5_7',
'ixRELEASE_TO_STALL_LUT_17_20', 'ixRELEASE_TO_STALL_LUT_1_8',
'ixRELEASE_TO_STALL_LUT_9_16', 'ixRTAVFS_REG0', 'ixRTAVFS_REG1',
'ixRTAVFS_REG10', 'ixRTAVFS_REG100', 'ixRTAVFS_REG101',
'ixRTAVFS_REG102', 'ixRTAVFS_REG103', 'ixRTAVFS_REG104',
'ixRTAVFS_REG105', 'ixRTAVFS_REG106', 'ixRTAVFS_REG107',
'ixRTAVFS_REG108', 'ixRTAVFS_REG109', 'ixRTAVFS_REG11',
'ixRTAVFS_REG110', 'ixRTAVFS_REG111', 'ixRTAVFS_REG112',
'ixRTAVFS_REG113', 'ixRTAVFS_REG114', 'ixRTAVFS_REG115',
'ixRTAVFS_REG116', 'ixRTAVFS_REG117', 'ixRTAVFS_REG118',
'ixRTAVFS_REG119', 'ixRTAVFS_REG12', 'ixRTAVFS_REG120',
'ixRTAVFS_REG121', 'ixRTAVFS_REG122', 'ixRTAVFS_REG123',
'ixRTAVFS_REG124', 'ixRTAVFS_REG125', 'ixRTAVFS_REG126',
'ixRTAVFS_REG127', 'ixRTAVFS_REG128', 'ixRTAVFS_REG129',
'ixRTAVFS_REG13', 'ixRTAVFS_REG130', 'ixRTAVFS_REG131',
'ixRTAVFS_REG132', 'ixRTAVFS_REG133', 'ixRTAVFS_REG134',
'ixRTAVFS_REG135', 'ixRTAVFS_REG136', 'ixRTAVFS_REG137',
'ixRTAVFS_REG138', 'ixRTAVFS_REG139', 'ixRTAVFS_REG14',
'ixRTAVFS_REG140', 'ixRTAVFS_REG141', 'ixRTAVFS_REG142',
'ixRTAVFS_REG143', 'ixRTAVFS_REG144', 'ixRTAVFS_REG145',
'ixRTAVFS_REG146', 'ixRTAVFS_REG147', 'ixRTAVFS_REG148',
'ixRTAVFS_REG149', 'ixRTAVFS_REG15', 'ixRTAVFS_REG150',
'ixRTAVFS_REG151', 'ixRTAVFS_REG152', 'ixRTAVFS_REG153',
'ixRTAVFS_REG154', 'ixRTAVFS_REG155', 'ixRTAVFS_REG156',
'ixRTAVFS_REG157', 'ixRTAVFS_REG158', 'ixRTAVFS_REG159',
'ixRTAVFS_REG16', 'ixRTAVFS_REG160', 'ixRTAVFS_REG161',
'ixRTAVFS_REG162', 'ixRTAVFS_REG163', 'ixRTAVFS_REG164',
'ixRTAVFS_REG165', 'ixRTAVFS_REG166', 'ixRTAVFS_REG167',
'ixRTAVFS_REG168', 'ixRTAVFS_REG169', 'ixRTAVFS_REG17',
'ixRTAVFS_REG170', 'ixRTAVFS_REG171', 'ixRTAVFS_REG172',
'ixRTAVFS_REG173', 'ixRTAVFS_REG174', 'ixRTAVFS_REG175',
'ixRTAVFS_REG176', 'ixRTAVFS_REG177', 'ixRTAVFS_REG178',
'ixRTAVFS_REG179', 'ixRTAVFS_REG18', 'ixRTAVFS_REG180',
'ixRTAVFS_REG181', 'ixRTAVFS_REG182', 'ixRTAVFS_REG183',
'ixRTAVFS_REG184', 'ixRTAVFS_REG185', 'ixRTAVFS_REG186',
'ixRTAVFS_REG187', 'ixRTAVFS_REG188', 'ixRTAVFS_REG189',
'ixRTAVFS_REG19', 'ixRTAVFS_REG190', 'ixRTAVFS_REG191',
'ixRTAVFS_REG192', 'ixRTAVFS_REG193', 'ixRTAVFS_REG194',
'ixRTAVFS_REG2', 'ixRTAVFS_REG20', 'ixRTAVFS_REG21',
'ixRTAVFS_REG22', 'ixRTAVFS_REG23', 'ixRTAVFS_REG24',
'ixRTAVFS_REG25', 'ixRTAVFS_REG26', 'ixRTAVFS_REG27',
'ixRTAVFS_REG28', 'ixRTAVFS_REG29', 'ixRTAVFS_REG3',
'ixRTAVFS_REG30', 'ixRTAVFS_REG31', 'ixRTAVFS_REG32',
'ixRTAVFS_REG33', 'ixRTAVFS_REG34', 'ixRTAVFS_REG35',
'ixRTAVFS_REG36', 'ixRTAVFS_REG37', 'ixRTAVFS_REG38',
'ixRTAVFS_REG39', 'ixRTAVFS_REG4', 'ixRTAVFS_REG40',
'ixRTAVFS_REG41', 'ixRTAVFS_REG42', 'ixRTAVFS_REG43',
'ixRTAVFS_REG44', 'ixRTAVFS_REG45', 'ixRTAVFS_REG46',
'ixRTAVFS_REG47', 'ixRTAVFS_REG48', 'ixRTAVFS_REG49',
'ixRTAVFS_REG5', 'ixRTAVFS_REG50', 'ixRTAVFS_REG51',
'ixRTAVFS_REG52', 'ixRTAVFS_REG53', 'ixRTAVFS_REG54',
'ixRTAVFS_REG55', 'ixRTAVFS_REG56', 'ixRTAVFS_REG57',
'ixRTAVFS_REG58', 'ixRTAVFS_REG59', 'ixRTAVFS_REG6',
'ixRTAVFS_REG60', 'ixRTAVFS_REG61', 'ixRTAVFS_REG62',
'ixRTAVFS_REG63', 'ixRTAVFS_REG64', 'ixRTAVFS_REG65',
'ixRTAVFS_REG66', 'ixRTAVFS_REG67', 'ixRTAVFS_REG68',
'ixRTAVFS_REG69', 'ixRTAVFS_REG7', 'ixRTAVFS_REG70',
'ixRTAVFS_REG71', 'ixRTAVFS_REG72', 'ixRTAVFS_REG73',
'ixRTAVFS_REG74', 'ixRTAVFS_REG75', 'ixRTAVFS_REG76',
'ixRTAVFS_REG77', 'ixRTAVFS_REG78', 'ixRTAVFS_REG79',
'ixRTAVFS_REG8', 'ixRTAVFS_REG80', 'ixRTAVFS_REG81',
'ixRTAVFS_REG82', 'ixRTAVFS_REG83', 'ixRTAVFS_REG84',
'ixRTAVFS_REG85', 'ixRTAVFS_REG86', 'ixRTAVFS_REG87',
'ixRTAVFS_REG88', 'ixRTAVFS_REG89', 'ixRTAVFS_REG9',
'ixRTAVFS_REG90', 'ixRTAVFS_REG91', 'ixRTAVFS_REG92',
'ixRTAVFS_REG93', 'ixRTAVFS_REG94', 'ixRTAVFS_REG95',
'ixRTAVFS_REG96', 'ixRTAVFS_REG97', 'ixRTAVFS_REG98',
'ixRTAVFS_REG99', 'ixSA_WGP_BLK_ID', 'ixSE_CAC_CNTL',
'ixSE_CAC_ID', 'ixSE_CAC_OVR_SEL', 'ixSE_CAC_OVR_VAL',
'ixSE_CBR_SAMPLEDELAY', 'ixSE_DBR_SAMPLEDELAY',
'ixSE_PA_SAMPLEDELAY', 'ixSE_SA0CB0_SAMPLEDELAY',
'ixSE_SA0CB1_SAMPLEDELAY', 'ixSE_SA0DB0_SAMPLEDELAY',
'ixSE_SA0DB1_SAMPLEDELAY', 'ixSE_SA0GL1A_SAMPLEDELAY',
'ixSE_SA0GL1C0_SAMPLEDELAY', 'ixSE_SA0GL1C1_SAMPLEDELAY',
'ixSE_SA0GL1C2_SAMPLEDELAY', 'ixSE_SA0GL1C3_SAMPLEDELAY',
'ixSE_SA0GL1CG_SAMPLEDELAY', 'ixSE_SA0RMI0_SAMPLEDELAY',
'ixSE_SA0RMI1_SAMPLEDELAY', 'ixSE_SA0SC0_SAMPLEDELAY',
'ixSE_SA0SC1_SAMPLEDELAY', 'ixSE_SA0SX_SAMPLEDELAY',
'ixSE_SA0WGP00TA0_SAMPLEDELAY', 'ixSE_SA0WGP00TA1_SAMPLEDELAY',
'ixSE_SA0WGP00TCP0_SAMPLEDELAY', 'ixSE_SA0WGP00TCP1_SAMPLEDELAY',
'ixSE_SA0WGP00TD0_SAMPLEDELAY', 'ixSE_SA0WGP00TD1_SAMPLEDELAY',
'ixSE_SA0WGP01TA0_SAMPLEDELAY', 'ixSE_SA0WGP01TA1_SAMPLEDELAY',
'ixSE_SA0WGP01TCP0_SAMPLEDELAY', 'ixSE_SA0WGP01TCP1_SAMPLEDELAY',
'ixSE_SA0WGP01TD0_SAMPLEDELAY', 'ixSE_SA0WGP01TD1_SAMPLEDELAY',
'ixSE_SA0WGP02TA0_SAMPLEDELAY', 'ixSE_SA0WGP02TA1_SAMPLEDELAY',
'ixSE_SA0WGP02TCP0_SAMPLEDELAY', 'ixSE_SA0WGP02TCP1_SAMPLEDELAY',
'ixSE_SA0WGP02TD0_SAMPLEDELAY', 'ixSE_SA0WGP02TD1_SAMPLEDELAY',
'ixSE_SA0WGP03TA0_SAMPLEDELAY', 'ixSE_SA0WGP03TA1_SAMPLEDELAY',
'ixSE_SA0WGP03TCP0_SAMPLEDELAY', 'ixSE_SA0WGP03TCP1_SAMPLEDELAY',
'ixSE_SA0WGP03TD0_SAMPLEDELAY', 'ixSE_SA0WGP03TD1_SAMPLEDELAY',
'ixSE_SA0WGP04TA0_SAMPLEDELAY', 'ixSE_SA0WGP04TA1_SAMPLEDELAY',
'ixSE_SA0WGP04TCP0_SAMPLEDELAY', 'ixSE_SA0WGP04TCP1_SAMPLEDELAY',
'ixSE_SA0WGP04TD0_SAMPLEDELAY', 'ixSE_SA0WGP04TD1_SAMPLEDELAY',
'ixSE_SA1CB0_SAMPLEDELAY', 'ixSE_SA1CB1_SAMPLEDELAY',
'ixSE_SA1DB0_SAMPLEDELAY', 'ixSE_SA1DB1_SAMPLEDELAY',
'ixSE_SA1GL1A_SAMPLEDELAY', 'ixSE_SA1GL1C0_SAMPLEDELAY',
'ixSE_SA1GL1C1_SAMPLEDELAY', 'ixSE_SA1GL1C2_SAMPLEDELAY',
'ixSE_SA1GL1C3_SAMPLEDELAY', 'ixSE_SA1GL1CG_SAMPLEDELAY',
'ixSE_SA1RMI0_SAMPLEDELAY', 'ixSE_SA1RMI1_SAMPLEDELAY',
'ixSE_SA1SC0_SAMPLEDELAY', 'ixSE_SA1SC1_SAMPLEDELAY',
'ixSE_SA1SX_SAMPLEDELAY', 'ixSE_SA1WGP00TA0_SAMPLEDELAY',
'ixSE_SA1WGP00TA1_SAMPLEDELAY', 'ixSE_SA1WGP00TCP0_SAMPLEDELAY',
'ixSE_SA1WGP00TCP1_SAMPLEDELAY', 'ixSE_SA1WGP00TD0_SAMPLEDELAY',
'ixSE_SA1WGP00TD1_SAMPLEDELAY', 'ixSE_SA1WGP01TA0_SAMPLEDELAY',
'ixSE_SA1WGP01TA1_SAMPLEDELAY', 'ixSE_SA1WGP01TCP0_SAMPLEDELAY',
'ixSE_SA1WGP01TCP1_SAMPLEDELAY', 'ixSE_SA1WGP01TD0_SAMPLEDELAY',
'ixSE_SA1WGP01TD1_SAMPLEDELAY', 'ixSE_SA1WGP02TA0_SAMPLEDELAY',
'ixSE_SA1WGP02TA1_SAMPLEDELAY', 'ixSE_SA1WGP02TCP0_SAMPLEDELAY',
'ixSE_SA1WGP02TCP1_SAMPLEDELAY', 'ixSE_SA1WGP02TD0_SAMPLEDELAY',
'ixSE_SA1WGP02TD1_SAMPLEDELAY', 'ixSE_SA1WGP03TA0_SAMPLEDELAY',
'ixSE_SA1WGP03TA1_SAMPLEDELAY', 'ixSE_SA1WGP03TCP0_SAMPLEDELAY',
'ixSE_SA1WGP03TCP1_SAMPLEDELAY', 'ixSE_SA1WGP03TD0_SAMPLEDELAY',
'ixSE_SA1WGP03TD1_SAMPLEDELAY', 'ixSE_SA1WGP04TA0_SAMPLEDELAY',
'ixSE_SA1WGP04TA1_SAMPLEDELAY', 'ixSE_SA1WGP04TCP0_SAMPLEDELAY',
'ixSE_SA1WGP04TCP1_SAMPLEDELAY', 'ixSE_SA1WGP04TD0_SAMPLEDELAY',
'ixSE_SA1WGP04TD1_SAMPLEDELAY', 'ixSE_SPI_SAMPLEDELAY',
'ixSE_SQG_SAMPLEDELAY', 'ixSQ_DEBUG_CTRL_LOCAL',
'ixSQ_DEBUG_STS_LOCAL', 'ixSQ_INTERRUPT_WORD_AUTO',
'ixSQ_INTERRUPT_WORD_ERROR', 'ixSQ_INTERRUPT_WORD_WAVE',
'ixSQ_WAVE_ACTIVE', 'ixSQ_WAVE_EXEC_HI', 'ixSQ_WAVE_EXEC_LO',
'ixSQ_WAVE_FLAT_SCRATCH_HI', 'ixSQ_WAVE_FLAT_SCRATCH_LO',
'ixSQ_WAVE_FLUSH_IB', 'ixSQ_WAVE_GPR_ALLOC', 'ixSQ_WAVE_HW_ID1',
'ixSQ_WAVE_HW_ID2', 'ixSQ_WAVE_HW_ID_LEGACY', 'ixSQ_WAVE_IB_DBG1',
'ixSQ_WAVE_IB_STS', 'ixSQ_WAVE_IB_STS2', 'ixSQ_WAVE_INST_DW0',
'ixSQ_WAVE_LDS_ALLOC', 'ixSQ_WAVE_M0', 'ixSQ_WAVE_MODE',
'ixSQ_WAVE_PC_HI', 'ixSQ_WAVE_PC_LO', 'ixSQ_WAVE_POPS_PACKER',
'ixSQ_WAVE_SCHED_MODE', 'ixSQ_WAVE_SHADER_CYCLES',
'ixSQ_WAVE_STATUS', 'ixSQ_WAVE_TRAPSTS', 'ixSQ_WAVE_TTMP0',
'ixSQ_WAVE_TTMP1', 'ixSQ_WAVE_TTMP10', 'ixSQ_WAVE_TTMP11',
'ixSQ_WAVE_TTMP12', 'ixSQ_WAVE_TTMP13', 'ixSQ_WAVE_TTMP14',
'ixSQ_WAVE_TTMP15', 'ixSQ_WAVE_TTMP2', 'ixSQ_WAVE_TTMP3',
'ixSQ_WAVE_TTMP4', 'ixSQ_WAVE_TTMP5', 'ixSQ_WAVE_TTMP6',
'ixSQ_WAVE_TTMP7', 'ixSQ_WAVE_TTMP8', 'ixSQ_WAVE_TTMP9',
'ixSQ_WAVE_VALID_AND_IDLE', 'ixSQ_WAVE_VGPR_OFFSET',
'ixSTALL_TO_PWRBRK_LUT_1_4', 'ixSTALL_TO_PWRBRK_LUT_5_7',
'ixSTALL_TO_RELEASE_LUT_1_4', 'ixSTALL_TO_RELEASE_LUT_5_7',
'mmCB_BLEND0_CONTROL', 'mmCB_BLEND0_CONTROL_BASE_IDX',
'mmCB_BLEND1_CONTROL', 'mmCB_BLEND1_CONTROL_BASE_IDX',
'mmCB_BLEND2_CONTROL', 'mmCB_BLEND2_CONTROL_BASE_IDX',
'mmCB_BLEND3_CONTROL', 'mmCB_BLEND3_CONTROL_BASE_IDX',
'mmCB_BLEND4_CONTROL', 'mmCB_BLEND4_CONTROL_BASE_IDX',
'mmCB_BLEND5_CONTROL', 'mmCB_BLEND5_CONTROL_BASE_IDX',
'mmCB_BLEND6_CONTROL', 'mmCB_BLEND6_CONTROL_BASE_IDX',
'mmCB_BLEND7_CONTROL', 'mmCB_BLEND7_CONTROL_BASE_IDX',
'mmCB_BLEND_ALPHA', 'mmCB_BLEND_ALPHA_BASE_IDX',
'mmCB_BLEND_BLUE', 'mmCB_BLEND_BLUE_BASE_IDX', 'mmCB_BLEND_GREEN',
'mmCB_BLEND_GREEN_BASE_IDX', 'mmCB_BLEND_RED',
'mmCB_BLEND_RED_BASE_IDX', 'mmCB_CACHE_EVICT_POINTS',
'mmCB_CACHE_EVICT_POINTS_BASE_IDX', 'mmCB_CGTT_SCLK_CTRL',
'mmCB_CGTT_SCLK_CTRL_BASE_IDX', 'mmCB_COLOR0_ATTRIB',
'mmCB_COLOR0_ATTRIB2', 'mmCB_COLOR0_ATTRIB2_BASE_IDX',
'mmCB_COLOR0_ATTRIB3', 'mmCB_COLOR0_ATTRIB3_BASE_IDX',
'mmCB_COLOR0_ATTRIB_BASE_IDX', 'mmCB_COLOR0_BASE',
'mmCB_COLOR0_BASE_BASE_IDX', 'mmCB_COLOR0_BASE_EXT',
'mmCB_COLOR0_BASE_EXT_BASE_IDX', 'mmCB_COLOR0_CLEAR_WORD0',
'mmCB_COLOR0_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR0_CLEAR_WORD1',
'mmCB_COLOR0_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR0_CMASK',
'mmCB_COLOR0_CMASK_BASE_EXT',
'mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR0_CMASK_BASE_IDX', 'mmCB_COLOR0_CMASK_SLICE',
'mmCB_COLOR0_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR0_DCC_BASE',
'mmCB_COLOR0_DCC_BASE_BASE_IDX', 'mmCB_COLOR0_DCC_BASE_EXT',
'mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR0_DCC_CONTROL',
'mmCB_COLOR0_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR0_FMASK',
'mmCB_COLOR0_FMASK_BASE_EXT',
'mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR0_FMASK_BASE_IDX', 'mmCB_COLOR0_FMASK_SLICE',
'mmCB_COLOR0_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR0_INFO',
'mmCB_COLOR0_INFO_BASE_IDX', 'mmCB_COLOR0_PITCH',
'mmCB_COLOR0_PITCH_BASE_IDX', 'mmCB_COLOR0_SLICE',
'mmCB_COLOR0_SLICE_BASE_IDX', 'mmCB_COLOR0_VIEW',
'mmCB_COLOR0_VIEW_BASE_IDX', 'mmCB_COLOR1_ATTRIB',
'mmCB_COLOR1_ATTRIB2', 'mmCB_COLOR1_ATTRIB2_BASE_IDX',
'mmCB_COLOR1_ATTRIB3', 'mmCB_COLOR1_ATTRIB3_BASE_IDX',
'mmCB_COLOR1_ATTRIB_BASE_IDX', 'mmCB_COLOR1_BASE',
'mmCB_COLOR1_BASE_BASE_IDX', 'mmCB_COLOR1_BASE_EXT',
'mmCB_COLOR1_BASE_EXT_BASE_IDX', 'mmCB_COLOR1_CLEAR_WORD0',
'mmCB_COLOR1_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR1_CLEAR_WORD1',
'mmCB_COLOR1_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR1_CMASK',
'mmCB_COLOR1_CMASK_BASE_EXT',
'mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR1_CMASK_BASE_IDX', 'mmCB_COLOR1_CMASK_SLICE',
'mmCB_COLOR1_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR1_DCC_BASE',
'mmCB_COLOR1_DCC_BASE_BASE_IDX', 'mmCB_COLOR1_DCC_BASE_EXT',
'mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR1_DCC_CONTROL',
'mmCB_COLOR1_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR1_FMASK',
'mmCB_COLOR1_FMASK_BASE_EXT',
'mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR1_FMASK_BASE_IDX', 'mmCB_COLOR1_FMASK_SLICE',
'mmCB_COLOR1_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR1_INFO',
'mmCB_COLOR1_INFO_BASE_IDX', 'mmCB_COLOR1_PITCH',
'mmCB_COLOR1_PITCH_BASE_IDX', 'mmCB_COLOR1_SLICE',
'mmCB_COLOR1_SLICE_BASE_IDX', 'mmCB_COLOR1_VIEW',
'mmCB_COLOR1_VIEW_BASE_IDX', 'mmCB_COLOR2_ATTRIB',
'mmCB_COLOR2_ATTRIB2', 'mmCB_COLOR2_ATTRIB2_BASE_IDX',
'mmCB_COLOR2_ATTRIB3', 'mmCB_COLOR2_ATTRIB3_BASE_IDX',
'mmCB_COLOR2_ATTRIB_BASE_IDX', 'mmCB_COLOR2_BASE',
'mmCB_COLOR2_BASE_BASE_IDX', 'mmCB_COLOR2_BASE_EXT',
'mmCB_COLOR2_BASE_EXT_BASE_IDX', 'mmCB_COLOR2_CLEAR_WORD0',
'mmCB_COLOR2_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR2_CLEAR_WORD1',
'mmCB_COLOR2_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR2_CMASK',
'mmCB_COLOR2_CMASK_BASE_EXT',
'mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR2_CMASK_BASE_IDX', 'mmCB_COLOR2_CMASK_SLICE',
'mmCB_COLOR2_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR2_DCC_BASE',
'mmCB_COLOR2_DCC_BASE_BASE_IDX', 'mmCB_COLOR2_DCC_BASE_EXT',
'mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR2_DCC_CONTROL',
'mmCB_COLOR2_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR2_FMASK',
'mmCB_COLOR2_FMASK_BASE_EXT',
'mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR2_FMASK_BASE_IDX', 'mmCB_COLOR2_FMASK_SLICE',
'mmCB_COLOR2_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR2_INFO',
'mmCB_COLOR2_INFO_BASE_IDX', 'mmCB_COLOR2_PITCH',
'mmCB_COLOR2_PITCH_BASE_IDX', 'mmCB_COLOR2_SLICE',
'mmCB_COLOR2_SLICE_BASE_IDX', 'mmCB_COLOR2_VIEW',
'mmCB_COLOR2_VIEW_BASE_IDX', 'mmCB_COLOR3_ATTRIB',
'mmCB_COLOR3_ATTRIB2', 'mmCB_COLOR3_ATTRIB2_BASE_IDX',
'mmCB_COLOR3_ATTRIB3', 'mmCB_COLOR3_ATTRIB3_BASE_IDX',
'mmCB_COLOR3_ATTRIB_BASE_IDX', 'mmCB_COLOR3_BASE',
'mmCB_COLOR3_BASE_BASE_IDX', 'mmCB_COLOR3_BASE_EXT',
'mmCB_COLOR3_BASE_EXT_BASE_IDX', 'mmCB_COLOR3_CLEAR_WORD0',
'mmCB_COLOR3_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR3_CLEAR_WORD1',
'mmCB_COLOR3_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR3_CMASK',
'mmCB_COLOR3_CMASK_BASE_EXT',
'mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR3_CMASK_BASE_IDX', 'mmCB_COLOR3_CMASK_SLICE',
'mmCB_COLOR3_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR3_DCC_BASE',
'mmCB_COLOR3_DCC_BASE_BASE_IDX', 'mmCB_COLOR3_DCC_BASE_EXT',
'mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR3_DCC_CONTROL',
'mmCB_COLOR3_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR3_FMASK',
'mmCB_COLOR3_FMASK_BASE_EXT',
'mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR3_FMASK_BASE_IDX', 'mmCB_COLOR3_FMASK_SLICE',
'mmCB_COLOR3_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR3_INFO',
'mmCB_COLOR3_INFO_BASE_IDX', 'mmCB_COLOR3_PITCH',
'mmCB_COLOR3_PITCH_BASE_IDX', 'mmCB_COLOR3_SLICE',
'mmCB_COLOR3_SLICE_BASE_IDX', 'mmCB_COLOR3_VIEW',
'mmCB_COLOR3_VIEW_BASE_IDX', 'mmCB_COLOR4_ATTRIB',
'mmCB_COLOR4_ATTRIB2', 'mmCB_COLOR4_ATTRIB2_BASE_IDX',
'mmCB_COLOR4_ATTRIB3', 'mmCB_COLOR4_ATTRIB3_BASE_IDX',
'mmCB_COLOR4_ATTRIB_BASE_IDX', 'mmCB_COLOR4_BASE',
'mmCB_COLOR4_BASE_BASE_IDX', 'mmCB_COLOR4_BASE_EXT',
'mmCB_COLOR4_BASE_EXT_BASE_IDX', 'mmCB_COLOR4_CLEAR_WORD0',
'mmCB_COLOR4_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR4_CLEAR_WORD1',
'mmCB_COLOR4_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR4_CMASK',
'mmCB_COLOR4_CMASK_BASE_EXT',
'mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR4_CMASK_BASE_IDX', 'mmCB_COLOR4_CMASK_SLICE',
'mmCB_COLOR4_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR4_DCC_BASE',
'mmCB_COLOR4_DCC_BASE_BASE_IDX', 'mmCB_COLOR4_DCC_BASE_EXT',
'mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR4_DCC_CONTROL',
'mmCB_COLOR4_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR4_FMASK',
'mmCB_COLOR4_FMASK_BASE_EXT',
'mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR4_FMASK_BASE_IDX', 'mmCB_COLOR4_FMASK_SLICE',
'mmCB_COLOR4_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR4_INFO',
'mmCB_COLOR4_INFO_BASE_IDX', 'mmCB_COLOR4_PITCH',
'mmCB_COLOR4_PITCH_BASE_IDX', 'mmCB_COLOR4_SLICE',
'mmCB_COLOR4_SLICE_BASE_IDX', 'mmCB_COLOR4_VIEW',
'mmCB_COLOR4_VIEW_BASE_IDX', 'mmCB_COLOR5_ATTRIB',
'mmCB_COLOR5_ATTRIB2', 'mmCB_COLOR5_ATTRIB2_BASE_IDX',
'mmCB_COLOR5_ATTRIB3', 'mmCB_COLOR5_ATTRIB3_BASE_IDX',
'mmCB_COLOR5_ATTRIB_BASE_IDX', 'mmCB_COLOR5_BASE',
'mmCB_COLOR5_BASE_BASE_IDX', 'mmCB_COLOR5_BASE_EXT',
'mmCB_COLOR5_BASE_EXT_BASE_IDX', 'mmCB_COLOR5_CLEAR_WORD0',
'mmCB_COLOR5_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR5_CLEAR_WORD1',
'mmCB_COLOR5_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR5_CMASK',
'mmCB_COLOR5_CMASK_BASE_EXT',
'mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR5_CMASK_BASE_IDX', 'mmCB_COLOR5_CMASK_SLICE',
'mmCB_COLOR5_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR5_DCC_BASE',
'mmCB_COLOR5_DCC_BASE_BASE_IDX', 'mmCB_COLOR5_DCC_BASE_EXT',
'mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR5_DCC_CONTROL',
'mmCB_COLOR5_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR5_FMASK',
'mmCB_COLOR5_FMASK_BASE_EXT',
'mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR5_FMASK_BASE_IDX', 'mmCB_COLOR5_FMASK_SLICE',
'mmCB_COLOR5_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR5_INFO',
'mmCB_COLOR5_INFO_BASE_IDX', 'mmCB_COLOR5_PITCH',
'mmCB_COLOR5_PITCH_BASE_IDX', 'mmCB_COLOR5_SLICE',
'mmCB_COLOR5_SLICE_BASE_IDX', 'mmCB_COLOR5_VIEW',
'mmCB_COLOR5_VIEW_BASE_IDX', 'mmCB_COLOR6_ATTRIB',
'mmCB_COLOR6_ATTRIB2', 'mmCB_COLOR6_ATTRIB2_BASE_IDX',
'mmCB_COLOR6_ATTRIB3', 'mmCB_COLOR6_ATTRIB3_BASE_IDX',
'mmCB_COLOR6_ATTRIB_BASE_IDX', 'mmCB_COLOR6_BASE',
'mmCB_COLOR6_BASE_BASE_IDX', 'mmCB_COLOR6_BASE_EXT',
'mmCB_COLOR6_BASE_EXT_BASE_IDX', 'mmCB_COLOR6_CLEAR_WORD0',
'mmCB_COLOR6_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR6_CLEAR_WORD1',
'mmCB_COLOR6_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR6_CMASK',
'mmCB_COLOR6_CMASK_BASE_EXT',
'mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR6_CMASK_BASE_IDX', 'mmCB_COLOR6_CMASK_SLICE',
'mmCB_COLOR6_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR6_DCC_BASE',
'mmCB_COLOR6_DCC_BASE_BASE_IDX', 'mmCB_COLOR6_DCC_BASE_EXT',
'mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR6_DCC_CONTROL',
'mmCB_COLOR6_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR6_FMASK',
'mmCB_COLOR6_FMASK_BASE_EXT',
'mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR6_FMASK_BASE_IDX', 'mmCB_COLOR6_FMASK_SLICE',
'mmCB_COLOR6_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR6_INFO',
'mmCB_COLOR6_INFO_BASE_IDX', 'mmCB_COLOR6_PITCH',
'mmCB_COLOR6_PITCH_BASE_IDX', 'mmCB_COLOR6_SLICE',
'mmCB_COLOR6_SLICE_BASE_IDX', 'mmCB_COLOR6_VIEW',
'mmCB_COLOR6_VIEW_BASE_IDX', 'mmCB_COLOR7_ATTRIB',
'mmCB_COLOR7_ATTRIB2', 'mmCB_COLOR7_ATTRIB2_BASE_IDX',
'mmCB_COLOR7_ATTRIB3', 'mmCB_COLOR7_ATTRIB3_BASE_IDX',
'mmCB_COLOR7_ATTRIB_BASE_IDX', 'mmCB_COLOR7_BASE',
'mmCB_COLOR7_BASE_BASE_IDX', 'mmCB_COLOR7_BASE_EXT',
'mmCB_COLOR7_BASE_EXT_BASE_IDX', 'mmCB_COLOR7_CLEAR_WORD0',
'mmCB_COLOR7_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR7_CLEAR_WORD1',
'mmCB_COLOR7_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR7_CMASK',
'mmCB_COLOR7_CMASK_BASE_EXT',
'mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR7_CMASK_BASE_IDX', 'mmCB_COLOR7_CMASK_SLICE',
'mmCB_COLOR7_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR7_DCC_BASE',
'mmCB_COLOR7_DCC_BASE_BASE_IDX', 'mmCB_COLOR7_DCC_BASE_EXT',
'mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR7_DCC_CONTROL',
'mmCB_COLOR7_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR7_FMASK',
'mmCB_COLOR7_FMASK_BASE_EXT',
'mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX',
'mmCB_COLOR7_FMASK_BASE_IDX', 'mmCB_COLOR7_FMASK_SLICE',
'mmCB_COLOR7_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR7_INFO',
'mmCB_COLOR7_INFO_BASE_IDX', 'mmCB_COLOR7_PITCH',
'mmCB_COLOR7_PITCH_BASE_IDX', 'mmCB_COLOR7_SLICE',
'mmCB_COLOR7_SLICE_BASE_IDX', 'mmCB_COLOR7_VIEW',
'mmCB_COLOR7_VIEW_BASE_IDX', 'mmCB_COLOR_CONTROL',
'mmCB_COLOR_CONTROL_BASE_IDX', 'mmCB_COVERAGE_OUT_CONTROL',
'mmCB_COVERAGE_OUT_CONTROL_BASE_IDX', 'mmCB_DCC_CONFIG',
'mmCB_DCC_CONFIG_BASE_IDX', 'mmCB_DCC_CONTROL',
'mmCB_DCC_CONTROL_BASE_IDX', 'mmCB_HW_CONTROL',
'mmCB_HW_CONTROL_1', 'mmCB_HW_CONTROL_1_BASE_IDX',
'mmCB_HW_CONTROL_2', 'mmCB_HW_CONTROL_2_BASE_IDX',
'mmCB_HW_CONTROL_3', 'mmCB_HW_CONTROL_3_BASE_IDX',
'mmCB_HW_CONTROL_4', 'mmCB_HW_CONTROL_4_BASE_IDX',
'mmCB_HW_CONTROL_BASE_IDX', 'mmCB_HW_MEM_ARBITER_RD',
'mmCB_HW_MEM_ARBITER_RD_BASE_IDX', 'mmCB_HW_MEM_ARBITER_WR',
'mmCB_HW_MEM_ARBITER_WR_BASE_IDX', 'mmCB_PERFCOUNTER0_HI',
'mmCB_PERFCOUNTER0_HI_BASE_IDX', 'mmCB_PERFCOUNTER0_LO',
'mmCB_PERFCOUNTER0_LO_BASE_IDX', 'mmCB_PERFCOUNTER0_SELECT',
'mmCB_PERFCOUNTER0_SELECT1', 'mmCB_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmCB_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCB_PERFCOUNTER1_HI',
'mmCB_PERFCOUNTER1_HI_BASE_IDX', 'mmCB_PERFCOUNTER1_LO',
'mmCB_PERFCOUNTER1_LO_BASE_IDX', 'mmCB_PERFCOUNTER1_SELECT',
'mmCB_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCB_PERFCOUNTER2_HI',
'mmCB_PERFCOUNTER2_HI_BASE_IDX', 'mmCB_PERFCOUNTER2_LO',
'mmCB_PERFCOUNTER2_LO_BASE_IDX', 'mmCB_PERFCOUNTER2_SELECT',
'mmCB_PERFCOUNTER2_SELECT_BASE_IDX', 'mmCB_PERFCOUNTER3_HI',
'mmCB_PERFCOUNTER3_HI_BASE_IDX', 'mmCB_PERFCOUNTER3_LO',
'mmCB_PERFCOUNTER3_LO_BASE_IDX', 'mmCB_PERFCOUNTER3_SELECT',
'mmCB_PERFCOUNTER3_SELECT_BASE_IDX', 'mmCB_PERFCOUNTER_FILTER',
'mmCB_PERFCOUNTER_FILTER_BASE_IDX',
'mmCB_RMI_BC_GL2_CACHE_CONTROL',
'mmCB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX',
'mmCB_RMI_GL2_CACHE_CONTROL',
'mmCB_RMI_GL2_CACHE_CONTROL_BASE_IDX', 'mmCB_SHADER_MASK',
'mmCB_SHADER_MASK_BASE_IDX', 'mmCB_STUTTER_CONTROL_CMASK_RDLAT',
'mmCB_STUTTER_CONTROL_CMASK_RDLAT_BASE_IDX',
'mmCB_STUTTER_CONTROL_COLOR_RDLAT',
'mmCB_STUTTER_CONTROL_COLOR_RDLAT_BASE_IDX',
'mmCB_STUTTER_CONTROL_FMASK_RDLAT',
'mmCB_STUTTER_CONTROL_FMASK_RDLAT_BASE_IDX', 'mmCB_TARGET_MASK',
'mmCB_TARGET_MASK_BASE_IDX', 'mmCC_GC_EDC_CONFIG',
'mmCC_GC_EDC_CONFIG_BASE_IDX', 'mmCC_GC_PRIM_CONFIG',
'mmCC_GC_PRIM_CONFIG_BASE_IDX', 'mmCC_GC_SA_UNIT_DISABLE',
'mmCC_GC_SA_UNIT_DISABLE_BASE_IDX', 'mmCC_GC_SHADER_ARRAY_CONFIG',
'mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX',
'mmCC_GC_SHADER_ARRAY_CONFIG_GEN0',
'mmCC_GC_SHADER_ARRAY_CONFIG_GEN0_BASE_IDX',
'mmCC_GC_SHADER_ARRAY_CONFIG_GEN1',
'mmCC_GC_SHADER_ARRAY_CONFIG_GEN1_BASE_IDX',
'mmCC_GC_SHADER_RATE_CONFIG',
'mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX', 'mmCC_RB_BACKEND_DISABLE',
'mmCC_RB_BACKEND_DISABLE_BASE_IDX', 'mmCC_RB_DAISY_CHAIN',
'mmCC_RB_DAISY_CHAIN_BASE_IDX', 'mmCC_RB_REDUNDANCY',
'mmCC_RB_REDUNDANCY_BASE_IDX', 'mmCC_RMI_REDUNDANCY',
'mmCC_RMI_REDUNDANCY_BASE_IDX', 'mmCGTS_RD_CTRL_REG',
'mmCGTS_RD_CTRL_REG_BASE_IDX', 'mmCGTS_RD_REG',
'mmCGTS_RD_REG_BASE_IDX', 'mmCGTS_STATUS_REG',
'mmCGTS_STATUS_REG_BASE_IDX', 'mmCGTS_TCC_DISABLE',
'mmCGTS_TCC_DISABLE_BASE_IDX', 'mmCGTS_USER_TCC_DISABLE',
'mmCGTS_USER_TCC_DISABLE_BASE_IDX', 'mmCGTT_BCI_CLK_CTRL',
'mmCGTT_BCI_CLK_CTRL_BASE_IDX', 'mmCGTT_CPC_CLK_CTRL',
'mmCGTT_CPC_CLK_CTRL_BASE_IDX', 'mmCGTT_CPF_CLK_CTRL',
'mmCGTT_CPF_CLK_CTRL_BASE_IDX', 'mmCGTT_CP_CLK_CTRL',
'mmCGTT_CP_CLK_CTRL_BASE_IDX', 'mmCGTT_GDS_CLK_CTRL',
'mmCGTT_GDS_CLK_CTRL_BASE_IDX', 'mmCGTT_GS_NGG_CLK_CTRL',
'mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX', 'mmCGTT_IA_CLK_CTRL',
'mmCGTT_IA_CLK_CTRL_BASE_IDX', 'mmCGTT_PA_CLK_CTRL',
'mmCGTT_PA_CLK_CTRL_BASE_IDX', 'mmCGTT_PC_CLK_CTRL',
'mmCGTT_PC_CLK_CTRL_BASE_IDX', 'mmCGTT_PH_CLK_CTRL0',
'mmCGTT_PH_CLK_CTRL0_BASE_IDX', 'mmCGTT_PH_CLK_CTRL1',
'mmCGTT_PH_CLK_CTRL1_BASE_IDX', 'mmCGTT_PH_CLK_CTRL2',
'mmCGTT_PH_CLK_CTRL2_BASE_IDX', 'mmCGTT_PH_CLK_CTRL3',
'mmCGTT_PH_CLK_CTRL3_BASE_IDX', 'mmCGTT_RLC_CLK_CTRL',
'mmCGTT_RLC_CLK_CTRL_BASE_IDX', 'mmCGTT_SC_CLK_CTRL0',
'mmCGTT_SC_CLK_CTRL0_BASE_IDX', 'mmCGTT_SC_CLK_CTRL1',
'mmCGTT_SC_CLK_CTRL1_BASE_IDX', 'mmCGTT_SC_CLK_CTRL2',
'mmCGTT_SC_CLK_CTRL2_BASE_IDX', 'mmCGTT_SPIS_CLK_CTRL',
'mmCGTT_SPIS_CLK_CTRL_BASE_IDX', 'mmCGTT_SPI_CGTSSM_CLK_CTRL',
'mmCGTT_SPI_CGTSSM_CLK_CTRL_BASE_IDX', 'mmCGTT_SPI_CLK_CTRL',
'mmCGTT_SPI_CLK_CTRL_BASE_IDX', 'mmCGTT_SPI_PS_CLK_CTRL',
'mmCGTT_SPI_PS_CLK_CTRL_BASE_IDX', 'mmCGTT_SQG_CLK_CTRL',
'mmCGTT_SQG_CLK_CTRL_BASE_IDX', 'mmCGTT_SQ_CLK_CTRL',
'mmCGTT_SQ_CLK_CTRL_BASE_IDX', 'mmCGTT_SX_CLK_CTRL0',
'mmCGTT_SX_CLK_CTRL0_BASE_IDX', 'mmCGTT_SX_CLK_CTRL1',
'mmCGTT_SX_CLK_CTRL1_BASE_IDX', 'mmCGTT_SX_CLK_CTRL2',
'mmCGTT_SX_CLK_CTRL2_BASE_IDX', 'mmCGTT_SX_CLK_CTRL3',
'mmCGTT_SX_CLK_CTRL3_BASE_IDX', 'mmCGTT_SX_CLK_CTRL4',
'mmCGTT_SX_CLK_CTRL4_BASE_IDX', 'mmCGTT_TCPF_CLK_CTRL',
'mmCGTT_TCPF_CLK_CTRL_BASE_IDX', 'mmCGTT_TCPI_CLK_CTRL',
'mmCGTT_TCPI_CLK_CTRL_BASE_IDX', 'mmCGTT_VGT_CLK_CTRL',
'mmCGTT_VGT_CLK_CTRL_BASE_IDX', 'mmCGTT_WD_CLK_CTRL',
'mmCGTT_WD_CLK_CTRL_BASE_IDX', 'mmCHA_CHC_CREDITS',
'mmCHA_CHC_CREDITS_BASE_IDX', 'mmCHA_CLIENT_FREE_DELAY',
'mmCHA_CLIENT_FREE_DELAY_BASE_IDX', 'mmCHA_PERFCOUNTER0_HI',
'mmCHA_PERFCOUNTER0_HI_BASE_IDX', 'mmCHA_PERFCOUNTER0_LO',
'mmCHA_PERFCOUNTER0_LO_BASE_IDX', 'mmCHA_PERFCOUNTER0_SELECT',
'mmCHA_PERFCOUNTER0_SELECT1',
'mmCHA_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmCHA_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCHA_PERFCOUNTER1_HI',
'mmCHA_PERFCOUNTER1_HI_BASE_IDX', 'mmCHA_PERFCOUNTER1_LO',
'mmCHA_PERFCOUNTER1_LO_BASE_IDX', 'mmCHA_PERFCOUNTER1_SELECT',
'mmCHA_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCHA_PERFCOUNTER2_HI',
'mmCHA_PERFCOUNTER2_HI_BASE_IDX', 'mmCHA_PERFCOUNTER2_LO',
'mmCHA_PERFCOUNTER2_LO_BASE_IDX', 'mmCHA_PERFCOUNTER2_SELECT',
'mmCHA_PERFCOUNTER2_SELECT_BASE_IDX', 'mmCHA_PERFCOUNTER3_HI',
'mmCHA_PERFCOUNTER3_HI_BASE_IDX', 'mmCHA_PERFCOUNTER3_LO',
'mmCHA_PERFCOUNTER3_LO_BASE_IDX', 'mmCHA_PERFCOUNTER3_SELECT',
'mmCHA_PERFCOUNTER3_SELECT_BASE_IDX', 'mmCHCG_CTRL',
'mmCHCG_CTRL_BASE_IDX', 'mmCHCG_PERFCOUNTER0_HI',
'mmCHCG_PERFCOUNTER0_HI_BASE_IDX', 'mmCHCG_PERFCOUNTER0_LO',
'mmCHCG_PERFCOUNTER0_LO_BASE_IDX', 'mmCHCG_PERFCOUNTER0_SELECT',
'mmCHCG_PERFCOUNTER0_SELECT1',
'mmCHCG_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmCHCG_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCHCG_PERFCOUNTER1_HI',
'mmCHCG_PERFCOUNTER1_HI_BASE_IDX', 'mmCHCG_PERFCOUNTER1_LO',
'mmCHCG_PERFCOUNTER1_LO_BASE_IDX', 'mmCHCG_PERFCOUNTER1_SELECT',
'mmCHCG_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCHCG_PERFCOUNTER2_HI',
'mmCHCG_PERFCOUNTER2_HI_BASE_IDX', 'mmCHCG_PERFCOUNTER2_LO',
'mmCHCG_PERFCOUNTER2_LO_BASE_IDX', 'mmCHCG_PERFCOUNTER2_SELECT',
'mmCHCG_PERFCOUNTER2_SELECT_BASE_IDX', 'mmCHCG_PERFCOUNTER3_HI',
'mmCHCG_PERFCOUNTER3_HI_BASE_IDX', 'mmCHCG_PERFCOUNTER3_LO',
'mmCHCG_PERFCOUNTER3_LO_BASE_IDX', 'mmCHCG_PERFCOUNTER3_SELECT',
'mmCHCG_PERFCOUNTER3_SELECT_BASE_IDX', 'mmCHCG_STATUS',
'mmCHCG_STATUS_BASE_IDX', 'mmCHC_CTRL', 'mmCHC_CTRL_BASE_IDX',
'mmCHC_PERFCOUNTER0_HI', 'mmCHC_PERFCOUNTER0_HI_BASE_IDX',
'mmCHC_PERFCOUNTER0_LO', 'mmCHC_PERFCOUNTER0_LO_BASE_IDX',
'mmCHC_PERFCOUNTER0_SELECT', 'mmCHC_PERFCOUNTER0_SELECT1',
'mmCHC_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmCHC_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCHC_PERFCOUNTER1_HI',
'mmCHC_PERFCOUNTER1_HI_BASE_IDX', 'mmCHC_PERFCOUNTER1_LO',
'mmCHC_PERFCOUNTER1_LO_BASE_IDX', 'mmCHC_PERFCOUNTER1_SELECT',
'mmCHC_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCHC_PERFCOUNTER2_HI',
'mmCHC_PERFCOUNTER2_HI_BASE_IDX', 'mmCHC_PERFCOUNTER2_LO',
'mmCHC_PERFCOUNTER2_LO_BASE_IDX', 'mmCHC_PERFCOUNTER2_SELECT',
'mmCHC_PERFCOUNTER2_SELECT_BASE_IDX', 'mmCHC_PERFCOUNTER3_HI',
'mmCHC_PERFCOUNTER3_HI_BASE_IDX', 'mmCHC_PERFCOUNTER3_LO',
'mmCHC_PERFCOUNTER3_LO_BASE_IDX', 'mmCHC_PERFCOUNTER3_SELECT',
'mmCHC_PERFCOUNTER3_SELECT_BASE_IDX', 'mmCHC_STATUS',
'mmCHC_STATUS_BASE_IDX', 'mmCH_ARB_CTRL',
'mmCH_ARB_CTRL_BASE_IDX', 'mmCH_ARB_STATUS',
'mmCH_ARB_STATUS_BASE_IDX', 'mmCH_DRAM_BURST_CTRL',
'mmCH_DRAM_BURST_CTRL_BASE_IDX', 'mmCH_DRAM_BURST_MASK',
'mmCH_DRAM_BURST_MASK_BASE_IDX', 'mmCH_PIPE_STEER',
'mmCH_PIPE_STEER_BASE_IDX', 'mmCH_VC5_ENABLE',
'mmCH_VC5_ENABLE_BASE_IDX', 'mmCOHER_DEST_BASE_0',
'mmCOHER_DEST_BASE_0_BASE_IDX', 'mmCOHER_DEST_BASE_1',
'mmCOHER_DEST_BASE_1_BASE_IDX', 'mmCOHER_DEST_BASE_2',
'mmCOHER_DEST_BASE_2_BASE_IDX', 'mmCOHER_DEST_BASE_3',
'mmCOHER_DEST_BASE_3_BASE_IDX', 'mmCOHER_DEST_BASE_HI_0',
'mmCOHER_DEST_BASE_HI_0_BASE_IDX', 'mmCOHER_DEST_BASE_HI_1',
'mmCOHER_DEST_BASE_HI_1_BASE_IDX', 'mmCOHER_DEST_BASE_HI_2',
'mmCOHER_DEST_BASE_HI_2_BASE_IDX', 'mmCOHER_DEST_BASE_HI_3',
'mmCOHER_DEST_BASE_HI_3_BASE_IDX', 'mmCOMPUTE_DDID_INDEX',
'mmCOMPUTE_DDID_INDEX_BASE_IDX', 'mmCOMPUTE_DESTINATION_EN_SE0',
'mmCOMPUTE_DESTINATION_EN_SE0_BASE_IDX',
'mmCOMPUTE_DESTINATION_EN_SE1',
'mmCOMPUTE_DESTINATION_EN_SE1_BASE_IDX',
'mmCOMPUTE_DESTINATION_EN_SE2',
'mmCOMPUTE_DESTINATION_EN_SE2_BASE_IDX',
'mmCOMPUTE_DESTINATION_EN_SE3',
'mmCOMPUTE_DESTINATION_EN_SE3_BASE_IDX', 'mmCOMPUTE_DIM_X',
'mmCOMPUTE_DIM_X_BASE_IDX', 'mmCOMPUTE_DIM_Y',
'mmCOMPUTE_DIM_Y_BASE_IDX', 'mmCOMPUTE_DIM_Z',
'mmCOMPUTE_DIM_Z_BASE_IDX', 'mmCOMPUTE_DISPATCH_END',
'mmCOMPUTE_DISPATCH_END_BASE_IDX', 'mmCOMPUTE_DISPATCH_ID',
'mmCOMPUTE_DISPATCH_ID_BASE_IDX', 'mmCOMPUTE_DISPATCH_INITIATOR',
'mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX',
'mmCOMPUTE_DISPATCH_PKT_ADDR_HI',
'mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX',
'mmCOMPUTE_DISPATCH_PKT_ADDR_LO',
'mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX',
'mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI',
'mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX',
'mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO',
'mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX',
'mmCOMPUTE_DISPATCH_TUNNEL', 'mmCOMPUTE_DISPATCH_TUNNEL_BASE_IDX',
'mmCOMPUTE_MISC_RESERVED', 'mmCOMPUTE_MISC_RESERVED_BASE_IDX',
'mmCOMPUTE_NOWHERE', 'mmCOMPUTE_NOWHERE_BASE_IDX',
'mmCOMPUTE_NUM_THREAD_X', 'mmCOMPUTE_NUM_THREAD_X_BASE_IDX',
'mmCOMPUTE_NUM_THREAD_Y', 'mmCOMPUTE_NUM_THREAD_Y_BASE_IDX',
'mmCOMPUTE_NUM_THREAD_Z', 'mmCOMPUTE_NUM_THREAD_Z_BASE_IDX',
'mmCOMPUTE_PERFCOUNT_ENABLE',
'mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX', 'mmCOMPUTE_PGM_HI',
'mmCOMPUTE_PGM_HI_BASE_IDX', 'mmCOMPUTE_PGM_LO',
'mmCOMPUTE_PGM_LO_BASE_IDX', 'mmCOMPUTE_PGM_RSRC1',
'mmCOMPUTE_PGM_RSRC1_BASE_IDX', 'mmCOMPUTE_PGM_RSRC2',
'mmCOMPUTE_PGM_RSRC2_BASE_IDX', 'mmCOMPUTE_PGM_RSRC3',
'mmCOMPUTE_PGM_RSRC3_BASE_IDX', 'mmCOMPUTE_PIPELINESTAT_ENABLE',
'mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX', 'mmCOMPUTE_RELAUNCH',
'mmCOMPUTE_RELAUNCH2', 'mmCOMPUTE_RELAUNCH2_BASE_IDX',
'mmCOMPUTE_RELAUNCH_BASE_IDX', 'mmCOMPUTE_REQ_CTRL',
'mmCOMPUTE_REQ_CTRL_BASE_IDX', 'mmCOMPUTE_RESOURCE_LIMITS',
'mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX', 'mmCOMPUTE_RESTART_X',
'mmCOMPUTE_RESTART_X_BASE_IDX', 'mmCOMPUTE_RESTART_Y',
'mmCOMPUTE_RESTART_Y_BASE_IDX', 'mmCOMPUTE_RESTART_Z',
'mmCOMPUTE_RESTART_Z_BASE_IDX', 'mmCOMPUTE_SHADER_CHKSUM',
'mmCOMPUTE_SHADER_CHKSUM_BASE_IDX', 'mmCOMPUTE_START_X',
'mmCOMPUTE_START_X_BASE_IDX', 'mmCOMPUTE_START_Y',
'mmCOMPUTE_START_Y_BASE_IDX', 'mmCOMPUTE_START_Z',
'mmCOMPUTE_START_Z_BASE_IDX', 'mmCOMPUTE_STATIC_THREAD_MGMT_SE0',
'mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX',
'mmCOMPUTE_STATIC_THREAD_MGMT_SE1',
'mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX',
'mmCOMPUTE_STATIC_THREAD_MGMT_SE2',
'mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX',
'mmCOMPUTE_STATIC_THREAD_MGMT_SE3',
'mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX',
'mmCOMPUTE_THREADGROUP_ID', 'mmCOMPUTE_THREADGROUP_ID_BASE_IDX',
'mmCOMPUTE_THREAD_TRACE_ENABLE',
'mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX',
'mmCOMPUTE_TMPRING_SIZE', 'mmCOMPUTE_TMPRING_SIZE_BASE_IDX',
'mmCOMPUTE_USER_ACCUM_0', 'mmCOMPUTE_USER_ACCUM_0_BASE_IDX',
'mmCOMPUTE_USER_ACCUM_1', 'mmCOMPUTE_USER_ACCUM_1_BASE_IDX',
'mmCOMPUTE_USER_ACCUM_2', 'mmCOMPUTE_USER_ACCUM_2_BASE_IDX',
'mmCOMPUTE_USER_ACCUM_3', 'mmCOMPUTE_USER_ACCUM_3_BASE_IDX',
'mmCOMPUTE_USER_DATA_0', 'mmCOMPUTE_USER_DATA_0_BASE_IDX',
'mmCOMPUTE_USER_DATA_1', 'mmCOMPUTE_USER_DATA_10',
'mmCOMPUTE_USER_DATA_10_BASE_IDX', 'mmCOMPUTE_USER_DATA_11',
'mmCOMPUTE_USER_DATA_11_BASE_IDX', 'mmCOMPUTE_USER_DATA_12',
'mmCOMPUTE_USER_DATA_12_BASE_IDX', 'mmCOMPUTE_USER_DATA_13',
'mmCOMPUTE_USER_DATA_13_BASE_IDX', 'mmCOMPUTE_USER_DATA_14',
'mmCOMPUTE_USER_DATA_14_BASE_IDX', 'mmCOMPUTE_USER_DATA_15',
'mmCOMPUTE_USER_DATA_15_BASE_IDX',
'mmCOMPUTE_USER_DATA_1_BASE_IDX', 'mmCOMPUTE_USER_DATA_2',
'mmCOMPUTE_USER_DATA_2_BASE_IDX', 'mmCOMPUTE_USER_DATA_3',
'mmCOMPUTE_USER_DATA_3_BASE_IDX', 'mmCOMPUTE_USER_DATA_4',
'mmCOMPUTE_USER_DATA_4_BASE_IDX', 'mmCOMPUTE_USER_DATA_5',
'mmCOMPUTE_USER_DATA_5_BASE_IDX', 'mmCOMPUTE_USER_DATA_6',
'mmCOMPUTE_USER_DATA_6_BASE_IDX', 'mmCOMPUTE_USER_DATA_7',
'mmCOMPUTE_USER_DATA_7_BASE_IDX', 'mmCOMPUTE_USER_DATA_8',
'mmCOMPUTE_USER_DATA_8_BASE_IDX', 'mmCOMPUTE_USER_DATA_9',
'mmCOMPUTE_USER_DATA_9_BASE_IDX', 'mmCOMPUTE_VMID',
'mmCOMPUTE_VMID_BASE_IDX', 'mmCOMPUTE_WAVE_RESTORE_ADDR_HI',
'mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX',
'mmCOMPUTE_WAVE_RESTORE_ADDR_LO',
'mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX',
'mmCONFIG_RESERVED_REG0', 'mmCONFIG_RESERVED_REG0_BASE_IDX',
'mmCONFIG_RESERVED_REG1', 'mmCONFIG_RESERVED_REG1_BASE_IDX',
'mmCONTEXT_RESERVED_REG0', 'mmCONTEXT_RESERVED_REG0_BASE_IDX',
'mmCONTEXT_RESERVED_REG1', 'mmCONTEXT_RESERVED_REG1_BASE_IDX',
'mmCPC_DDID_BASE_ADDR_HI', 'mmCPC_DDID_BASE_ADDR_HI_BASE_IDX',
'mmCPC_DDID_BASE_ADDR_LO', 'mmCPC_DDID_BASE_ADDR_LO_BASE_IDX',
'mmCPC_DDID_CNTL', 'mmCPC_DDID_CNTL_BASE_IDX', 'mmCPC_INT_ADDR',
'mmCPC_INT_ADDR_BASE_IDX', 'mmCPC_INT_CNTL',
'mmCPC_INT_CNTL_BASE_IDX', 'mmCPC_INT_CNTX_ID',
'mmCPC_INT_CNTX_ID_BASE_IDX', 'mmCPC_INT_INFO',
'mmCPC_INT_INFO_BASE_IDX', 'mmCPC_INT_PASID',
'mmCPC_INT_PASID_BASE_IDX', 'mmCPC_INT_STATUS',
'mmCPC_INT_STATUS_BASE_IDX', 'mmCPC_LATENCY_STATS_DATA',
'mmCPC_LATENCY_STATS_DATA_BASE_IDX', 'mmCPC_LATENCY_STATS_SELECT',
'mmCPC_LATENCY_STATS_SELECT_BASE_IDX', 'mmCPC_OS_PIPES',
'mmCPC_OS_PIPES_BASE_IDX', 'mmCPC_PERFCOUNTER0_HI',
'mmCPC_PERFCOUNTER0_HI_BASE_IDX', 'mmCPC_PERFCOUNTER0_LO',
'mmCPC_PERFCOUNTER0_LO_BASE_IDX', 'mmCPC_PERFCOUNTER0_SELECT',
'mmCPC_PERFCOUNTER0_SELECT1',
'mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmCPC_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCPC_PERFCOUNTER1_HI',
'mmCPC_PERFCOUNTER1_HI_BASE_IDX', 'mmCPC_PERFCOUNTER1_LO',
'mmCPC_PERFCOUNTER1_LO_BASE_IDX', 'mmCPC_PERFCOUNTER1_SELECT',
'mmCPC_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCPC_PSP_DEBUG',
'mmCPC_PSP_DEBUG_BASE_IDX', 'mmCPC_SUSPEND_CNTL_STACK_OFFSET',
'mmCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX',
'mmCPC_SUSPEND_CNTL_STACK_SIZE',
'mmCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX',
'mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI',
'mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX',
'mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO',
'mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX',
'mmCPC_SUSPEND_CTX_SAVE_CONTROL',
'mmCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX',
'mmCPC_SUSPEND_CTX_SAVE_SIZE',
'mmCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX',
'mmCPC_SUSPEND_WG_STATE_OFFSET',
'mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX', 'mmCPC_UTCL1_CNTL',
'mmCPC_UTCL1_CNTL_BASE_IDX', 'mmCPC_UTCL1_ERROR',
'mmCPC_UTCL1_ERROR_BASE_IDX', 'mmCPC_UTCL1_STATUS',
'mmCPC_UTCL1_STATUS_BASE_IDX', 'mmCPF_GCR_CNTL',
'mmCPF_GCR_CNTL_BASE_IDX', 'mmCPF_LATENCY_STATS_DATA',
'mmCPF_LATENCY_STATS_DATA_BASE_IDX', 'mmCPF_LATENCY_STATS_SELECT',
'mmCPF_LATENCY_STATS_SELECT_BASE_IDX', 'mmCPF_PERFCOUNTER0_HI',
'mmCPF_PERFCOUNTER0_HI_BASE_IDX', 'mmCPF_PERFCOUNTER0_LO',
'mmCPF_PERFCOUNTER0_LO_BASE_IDX', 'mmCPF_PERFCOUNTER0_SELECT',
'mmCPF_PERFCOUNTER0_SELECT1',
'mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmCPF_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCPF_PERFCOUNTER1_HI',
'mmCPF_PERFCOUNTER1_HI_BASE_IDX', 'mmCPF_PERFCOUNTER1_LO',
'mmCPF_PERFCOUNTER1_LO_BASE_IDX', 'mmCPF_PERFCOUNTER1_SELECT',
'mmCPF_PERFCOUNTER1_SELECT_BASE_IDX',
'mmCPF_TC_PERF_COUNTER_WINDOW_SELECT',
'mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX',
'mmCPF_UTCL1_CNTL', 'mmCPF_UTCL1_CNTL_BASE_IDX',
'mmCPF_UTCL1_STATUS', 'mmCPF_UTCL1_STATUS_BASE_IDX',
'mmCPG_LATENCY_STATS_DATA', 'mmCPG_LATENCY_STATS_DATA_BASE_IDX',
'mmCPG_LATENCY_STATS_SELECT',
'mmCPG_LATENCY_STATS_SELECT_BASE_IDX', 'mmCPG_PERFCOUNTER0_HI',
'mmCPG_PERFCOUNTER0_HI_BASE_IDX', 'mmCPG_PERFCOUNTER0_LO',
'mmCPG_PERFCOUNTER0_LO_BASE_IDX', 'mmCPG_PERFCOUNTER0_SELECT',
'mmCPG_PERFCOUNTER0_SELECT1',
'mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmCPG_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCPG_PERFCOUNTER1_HI',
'mmCPG_PERFCOUNTER1_HI_BASE_IDX', 'mmCPG_PERFCOUNTER1_LO',
'mmCPG_PERFCOUNTER1_LO_BASE_IDX', 'mmCPG_PERFCOUNTER1_SELECT',
'mmCPG_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCPG_PSP_DEBUG',
'mmCPG_PSP_DEBUG_BASE_IDX', 'mmCPG_RCIU_CAM_DATA',
'mmCPG_RCIU_CAM_DATA_BASE_IDX', 'mmCPG_RCIU_CAM_DATA_PHASE0',
'mmCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX',
'mmCPG_RCIU_CAM_DATA_PHASE1',
'mmCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX',
'mmCPG_RCIU_CAM_DATA_PHASE2',
'mmCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX', 'mmCPG_RCIU_CAM_INDEX',
'mmCPG_RCIU_CAM_INDEX_BASE_IDX',
'mmCPG_TC_PERF_COUNTER_WINDOW_SELECT',
'mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX',
'mmCPG_UTCL1_CNTL', 'mmCPG_UTCL1_CNTL_BASE_IDX',
'mmCPG_UTCL1_ERROR', 'mmCPG_UTCL1_ERROR_BASE_IDX',
'mmCPG_UTCL1_STATUS', 'mmCPG_UTCL1_STATUS_BASE_IDX',
'mmCP_APPEND_ADDR_HI', 'mmCP_APPEND_ADDR_HI_BASE_IDX',
'mmCP_APPEND_ADDR_LO', 'mmCP_APPEND_ADDR_LO_BASE_IDX',
'mmCP_APPEND_CMD_ADDR_HI', 'mmCP_APPEND_CMD_ADDR_HI_BASE_IDX',
'mmCP_APPEND_CMD_ADDR_LO', 'mmCP_APPEND_CMD_ADDR_LO_BASE_IDX',
'mmCP_APPEND_DATA', 'mmCP_APPEND_DATA_BASE_IDX',
'mmCP_APPEND_DATA_HI', 'mmCP_APPEND_DATA_HI_BASE_IDX',
'mmCP_APPEND_DATA_LO', 'mmCP_APPEND_DATA_LO_BASE_IDX',
'mmCP_APPEND_DDID_CNT', 'mmCP_APPEND_DDID_CNT_BASE_IDX',
'mmCP_APPEND_LAST_CS_FENCE', 'mmCP_APPEND_LAST_CS_FENCE_BASE_IDX',
'mmCP_APPEND_LAST_CS_FENCE_HI',
'mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX',
'mmCP_APPEND_LAST_CS_FENCE_LO',
'mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX',
'mmCP_APPEND_LAST_PS_FENCE', 'mmCP_APPEND_LAST_PS_FENCE_BASE_IDX',
'mmCP_APPEND_LAST_PS_FENCE_HI',
'mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX',
'mmCP_APPEND_LAST_PS_FENCE_LO',
'mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX', 'mmCP_AQL_SMM_STATUS',
'mmCP_AQL_SMM_STATUS_BASE_IDX', 'mmCP_ATOMIC_PREOP_HI',
'mmCP_ATOMIC_PREOP_HI_BASE_IDX', 'mmCP_ATOMIC_PREOP_LO',
'mmCP_ATOMIC_PREOP_LO_BASE_IDX', 'mmCP_BUSY_STAT',
'mmCP_BUSY_STAT_BASE_IDX', 'mmCP_CEQ1_AVAIL',
'mmCP_CEQ1_AVAIL_BASE_IDX', 'mmCP_CEQ2_AVAIL',
'mmCP_CEQ2_AVAIL_BASE_IDX', 'mmCP_CE_ATOMIC_PREOP_HI',
'mmCP_CE_ATOMIC_PREOP_HI_BASE_IDX', 'mmCP_CE_ATOMIC_PREOP_LO',
'mmCP_CE_ATOMIC_PREOP_LO_BASE_IDX', 'mmCP_CE_COMPARE_COUNT',
'mmCP_CE_COMPARE_COUNT_BASE_IDX', 'mmCP_CE_COMPLETION_STATUS',
'mmCP_CE_COMPLETION_STATUS_BASE_IDX', 'mmCP_CE_COUNTER',
'mmCP_CE_COUNTER_BASE_IDX', 'mmCP_CE_CS_PARTITION_INDEX',
'mmCP_CE_CS_PARTITION_INDEX_BASE_IDX', 'mmCP_CE_DB_BASE_HI',
'mmCP_CE_DB_BASE_HI_BASE_IDX', 'mmCP_CE_DB_BASE_LO',
'mmCP_CE_DB_BASE_LO_BASE_IDX', 'mmCP_CE_DB_BUFSZ',
'mmCP_CE_DB_BUFSZ_BASE_IDX', 'mmCP_CE_DB_CMD_BUFSZ',
'mmCP_CE_DB_CMD_BUFSZ_BASE_IDX', 'mmCP_CE_DE_COUNT',
'mmCP_CE_DE_COUNT_BASE_IDX', 'mmCP_CE_DOORBELL_CONTROL',
'mmCP_CE_DOORBELL_CONTROL_BASE_IDX', 'mmCP_CE_F32_INTERRUPT',
'mmCP_CE_F32_INTERRUPT_BASE_IDX', 'mmCP_CE_GDS_ATOMIC0_PREOP_HI',
'mmCP_CE_GDS_ATOMIC0_PREOP_HI_BASE_IDX',
'mmCP_CE_GDS_ATOMIC0_PREOP_LO',
'mmCP_CE_GDS_ATOMIC0_PREOP_LO_BASE_IDX',
'mmCP_CE_GDS_ATOMIC1_PREOP_HI',
'mmCP_CE_GDS_ATOMIC1_PREOP_HI_BASE_IDX',
'mmCP_CE_GDS_ATOMIC1_PREOP_LO',
'mmCP_CE_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'mmCP_CE_HEADER_DUMP',
'mmCP_CE_HEADER_DUMP_BASE_IDX', 'mmCP_CE_IB1_BASE_HI',
'mmCP_CE_IB1_BASE_HI_BASE_IDX', 'mmCP_CE_IB1_BASE_LO',
'mmCP_CE_IB1_BASE_LO_BASE_IDX', 'mmCP_CE_IB1_BUFSZ',
'mmCP_CE_IB1_BUFSZ_BASE_IDX', 'mmCP_CE_IB1_CMD_BUFSZ',
'mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX', 'mmCP_CE_IB1_OFFSET',
'mmCP_CE_IB1_OFFSET_BASE_IDX', 'mmCP_CE_IB2_BASE_HI',
'mmCP_CE_IB2_BASE_HI_BASE_IDX', 'mmCP_CE_IB2_BASE_LO',
'mmCP_CE_IB2_BASE_LO_BASE_IDX', 'mmCP_CE_IB2_BUFSZ',
'mmCP_CE_IB2_BUFSZ_BASE_IDX', 'mmCP_CE_IB2_CMD_BUFSZ',
'mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX', 'mmCP_CE_IB2_OFFSET',
'mmCP_CE_IB2_OFFSET_BASE_IDX', 'mmCP_CE_IC_BASE_CNTL',
'mmCP_CE_IC_BASE_CNTL_BASE_IDX', 'mmCP_CE_IC_BASE_HI',
'mmCP_CE_IC_BASE_HI_BASE_IDX', 'mmCP_CE_IC_BASE_LO',
'mmCP_CE_IC_BASE_LO_BASE_IDX', 'mmCP_CE_IC_OP_CNTL',
'mmCP_CE_IC_OP_CNTL_BASE_IDX', 'mmCP_CE_INIT_BASE_HI',
'mmCP_CE_INIT_BASE_HI_BASE_IDX', 'mmCP_CE_INIT_BASE_LO',
'mmCP_CE_INIT_BASE_LO_BASE_IDX', 'mmCP_CE_INIT_BUFSZ',
'mmCP_CE_INIT_BUFSZ_BASE_IDX', 'mmCP_CE_INIT_CMD_BUFSZ',
'mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX', 'mmCP_CE_INSTR_PNTR',
'mmCP_CE_INSTR_PNTR_BASE_IDX', 'mmCP_CE_INTR_ROUTINE_START',
'mmCP_CE_INTR_ROUTINE_START_BASE_IDX', 'mmCP_CE_JT_STAT',
'mmCP_CE_JT_STAT_BASE_IDX', 'mmCP_CE_METADATA_BASE_ADDR',
'mmCP_CE_METADATA_BASE_ADDR_BASE_IDX',
'mmCP_CE_METADATA_BASE_ADDR_HI',
'mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX',
'mmCP_CE_PRGRM_CNTR_START', 'mmCP_CE_PRGRM_CNTR_START_BASE_IDX',
'mmCP_CE_ROQ_DB_STAT', 'mmCP_CE_ROQ_DB_STAT_BASE_IDX',
'mmCP_CE_ROQ_IB1_STAT', 'mmCP_CE_ROQ_IB1_STAT_BASE_IDX',
'mmCP_CE_ROQ_IB2_STAT', 'mmCP_CE_ROQ_IB2_STAT_BASE_IDX',
'mmCP_CE_ROQ_RB_STAT', 'mmCP_CE_ROQ_RB_STAT_BASE_IDX',
'mmCP_CE_UCODE_ADDR', 'mmCP_CE_UCODE_ADDR_BASE_IDX',
'mmCP_CE_UCODE_DATA', 'mmCP_CE_UCODE_DATA_BASE_IDX',
'mmCP_CMD_DATA', 'mmCP_CMD_DATA_BASE_IDX', 'mmCP_CMD_INDEX',
'mmCP_CMD_INDEX_BASE_IDX', 'mmCP_CNTX_STAT',
'mmCP_CNTX_STAT_BASE_IDX', 'mmCP_COHER_BASE',
'mmCP_COHER_BASE_BASE_IDX', 'mmCP_COHER_BASE_HI',
'mmCP_COHER_BASE_HI_BASE_IDX', 'mmCP_COHER_CNTL',
'mmCP_COHER_CNTL_BASE_IDX', 'mmCP_COHER_SIZE',
'mmCP_COHER_SIZE_BASE_IDX', 'mmCP_COHER_SIZE_HI',
'mmCP_COHER_SIZE_HI_BASE_IDX', 'mmCP_COHER_START_DELAY',
'mmCP_COHER_START_DELAY_BASE_IDX', 'mmCP_COHER_STATUS',
'mmCP_COHER_STATUS_BASE_IDX', 'mmCP_CONTEXT_CNTL',
'mmCP_CONTEXT_CNTL_BASE_IDX', 'mmCP_CPC_BUSY_STAT',
'mmCP_CPC_BUSY_STAT2', 'mmCP_CPC_BUSY_STAT2_BASE_IDX',
'mmCP_CPC_BUSY_STAT_BASE_IDX', 'mmCP_CPC_GFX_CNTL',
'mmCP_CPC_GFX_CNTL_BASE_IDX', 'mmCP_CPC_GRBM_FREE_COUNT',
'mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX', 'mmCP_CPC_HALT_HYST_COUNT',
'mmCP_CPC_HALT_HYST_COUNT_BASE_IDX', 'mmCP_CPC_IC_BASE_CNTL',
'mmCP_CPC_IC_BASE_CNTL_BASE_IDX', 'mmCP_CPC_IC_BASE_HI',
'mmCP_CPC_IC_BASE_HI_BASE_IDX', 'mmCP_CPC_IC_BASE_LO',
'mmCP_CPC_IC_BASE_LO_BASE_IDX', 'mmCP_CPC_IC_OP_CNTL',
'mmCP_CPC_IC_OP_CNTL_BASE_IDX', 'mmCP_CPC_MGCG_SYNC_CNTL',
'mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX',
'mmCP_CPC_PRIV_VIOLATION_ADDR',
'mmCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX', 'mmCP_CPC_SCRATCH_DATA',
'mmCP_CPC_SCRATCH_DATA_BASE_IDX', 'mmCP_CPC_SCRATCH_INDEX',
'mmCP_CPC_SCRATCH_INDEX_BASE_IDX', 'mmCP_CPC_STALLED_STAT1',
'mmCP_CPC_STALLED_STAT1_BASE_IDX', 'mmCP_CPC_STATUS',
'mmCP_CPC_STATUS_BASE_IDX', 'mmCP_CPF_BUSY_STAT',
'mmCP_CPF_BUSY_STAT2', 'mmCP_CPF_BUSY_STAT2_BASE_IDX',
'mmCP_CPF_BUSY_STAT_BASE_IDX', 'mmCP_CPF_GRBM_FREE_COUNT',
'mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX', 'mmCP_CPF_STALLED_STAT1',
'mmCP_CPF_STALLED_STAT1_BASE_IDX', 'mmCP_CPF_STATUS',
'mmCP_CPF_STATUS_BASE_IDX', 'mmCP_CSF_STAT',
'mmCP_CSF_STAT_BASE_IDX', 'mmCP_DB_BASE_HI',
'mmCP_DB_BASE_HI_BASE_IDX', 'mmCP_DB_BASE_LO',
'mmCP_DB_BASE_LO_BASE_IDX', 'mmCP_DB_BUFSZ',
'mmCP_DB_BUFSZ_BASE_IDX', 'mmCP_DB_CMD_BUFSZ',
'mmCP_DB_CMD_BUFSZ_BASE_IDX', 'mmCP_DDID_BASE_ADDR_HI',
'mmCP_DDID_BASE_ADDR_HI_BASE_IDX', 'mmCP_DDID_BASE_ADDR_LO',
'mmCP_DDID_BASE_ADDR_LO_BASE_IDX', 'mmCP_DDID_CNTL',
'mmCP_DDID_CNTL_BASE_IDX', 'mmCP_DEVICE_ID',
'mmCP_DEVICE_ID_BASE_IDX', 'mmCP_DE_CE_COUNT',
'mmCP_DE_CE_COUNT_BASE_IDX', 'mmCP_DE_DE_COUNT',
'mmCP_DE_DE_COUNT_BASE_IDX', 'mmCP_DE_LAST_INVAL_COUNT',
'mmCP_DE_LAST_INVAL_COUNT_BASE_IDX', 'mmCP_DISPATCH_INDR_ADDR',
'mmCP_DISPATCH_INDR_ADDR_BASE_IDX', 'mmCP_DISPATCH_INDR_ADDR_HI',
'mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX', 'mmCP_DMA_CNTL',
'mmCP_DMA_CNTL_BASE_IDX', 'mmCP_DMA_ME_CMD_ADDR_HI',
'mmCP_DMA_ME_CMD_ADDR_HI_BASE_IDX', 'mmCP_DMA_ME_CMD_ADDR_LO',
'mmCP_DMA_ME_CMD_ADDR_LO_BASE_IDX', 'mmCP_DMA_ME_COMMAND',
'mmCP_DMA_ME_COMMAND_BASE_IDX', 'mmCP_DMA_ME_CONTROL',
'mmCP_DMA_ME_CONTROL_BASE_IDX', 'mmCP_DMA_ME_DST_ADDR',
'mmCP_DMA_ME_DST_ADDR_BASE_IDX', 'mmCP_DMA_ME_DST_ADDR_HI',
'mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX', 'mmCP_DMA_ME_SRC_ADDR',
'mmCP_DMA_ME_SRC_ADDR_BASE_IDX', 'mmCP_DMA_ME_SRC_ADDR_HI',
'mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX', 'mmCP_DMA_PFP_CMD_ADDR_HI',
'mmCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX', 'mmCP_DMA_PFP_CMD_ADDR_LO',
'mmCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX', 'mmCP_DMA_PFP_COMMAND',
'mmCP_DMA_PFP_COMMAND_BASE_IDX', 'mmCP_DMA_PFP_CONTROL',
'mmCP_DMA_PFP_CONTROL_BASE_IDX', 'mmCP_DMA_PFP_DST_ADDR',
'mmCP_DMA_PFP_DST_ADDR_BASE_IDX', 'mmCP_DMA_PFP_DST_ADDR_HI',
'mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX', 'mmCP_DMA_PFP_SRC_ADDR',
'mmCP_DMA_PFP_SRC_ADDR_BASE_IDX', 'mmCP_DMA_PFP_SRC_ADDR_HI',
'mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX', 'mmCP_DMA_READ_TAGS',
'mmCP_DMA_READ_TAGS_BASE_IDX', 'mmCP_DMA_WATCH0_ADDR_HI',
'mmCP_DMA_WATCH0_ADDR_HI_BASE_IDX', 'mmCP_DMA_WATCH0_ADDR_LO',
'mmCP_DMA_WATCH0_ADDR_LO_BASE_IDX', 'mmCP_DMA_WATCH0_CNTL',
'mmCP_DMA_WATCH0_CNTL_BASE_IDX', 'mmCP_DMA_WATCH0_MASK',
'mmCP_DMA_WATCH0_MASK_BASE_IDX', 'mmCP_DMA_WATCH1_ADDR_HI',
'mmCP_DMA_WATCH1_ADDR_HI_BASE_IDX', 'mmCP_DMA_WATCH1_ADDR_LO',
'mmCP_DMA_WATCH1_ADDR_LO_BASE_IDX', 'mmCP_DMA_WATCH1_CNTL',
'mmCP_DMA_WATCH1_CNTL_BASE_IDX', 'mmCP_DMA_WATCH1_MASK',
'mmCP_DMA_WATCH1_MASK_BASE_IDX', 'mmCP_DMA_WATCH2_ADDR_HI',
'mmCP_DMA_WATCH2_ADDR_HI_BASE_IDX', 'mmCP_DMA_WATCH2_ADDR_LO',
'mmCP_DMA_WATCH2_ADDR_LO_BASE_IDX', 'mmCP_DMA_WATCH2_CNTL',
'mmCP_DMA_WATCH2_CNTL_BASE_IDX', 'mmCP_DMA_WATCH2_MASK',
'mmCP_DMA_WATCH2_MASK_BASE_IDX', 'mmCP_DMA_WATCH3_ADDR_HI',
'mmCP_DMA_WATCH3_ADDR_HI_BASE_IDX', 'mmCP_DMA_WATCH3_ADDR_LO',
'mmCP_DMA_WATCH3_ADDR_LO_BASE_IDX', 'mmCP_DMA_WATCH3_CNTL',
'mmCP_DMA_WATCH3_CNTL_BASE_IDX', 'mmCP_DMA_WATCH3_MASK',
'mmCP_DMA_WATCH3_MASK_BASE_IDX', 'mmCP_DMA_WATCH_STAT',
'mmCP_DMA_WATCH_STAT_ADDR_HI',
'mmCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX',
'mmCP_DMA_WATCH_STAT_ADDR_LO',
'mmCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX',
'mmCP_DMA_WATCH_STAT_BASE_IDX', 'mmCP_DRAW_INDX_INDR_ADDR',
'mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX',
'mmCP_DRAW_INDX_INDR_ADDR_HI',
'mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX', 'mmCP_DRAW_OBJECT',
'mmCP_DRAW_OBJECT_BASE_IDX', 'mmCP_DRAW_OBJECT_COUNTER',
'mmCP_DRAW_OBJECT_COUNTER_BASE_IDX', 'mmCP_DRAW_WINDOW_CNTL',
'mmCP_DRAW_WINDOW_CNTL_BASE_IDX', 'mmCP_DRAW_WINDOW_HI',
'mmCP_DRAW_WINDOW_HI_BASE_IDX', 'mmCP_DRAW_WINDOW_LO',
'mmCP_DRAW_WINDOW_LO_BASE_IDX', 'mmCP_DRAW_WINDOW_MASK_HI',
'mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX', 'mmCP_ECC_FIRSTOCCURRENCE',
'mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX',
'mmCP_ECC_FIRSTOCCURRENCE_RING0',
'mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX',
'mmCP_ECC_FIRSTOCCURRENCE_RING1',
'mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX',
'mmCP_ECC_FIRSTOCCURRENCE_RING2',
'mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX', 'mmCP_EOPQ_WAIT_TIME',
'mmCP_EOPQ_WAIT_TIME_BASE_IDX', 'mmCP_EOP_DONE_ADDR_HI',
'mmCP_EOP_DONE_ADDR_HI_BASE_IDX', 'mmCP_EOP_DONE_ADDR_LO',
'mmCP_EOP_DONE_ADDR_LO_BASE_IDX', 'mmCP_EOP_DONE_CNTX_ID',
'mmCP_EOP_DONE_CNTX_ID_BASE_IDX', 'mmCP_EOP_DONE_DATA_CNTL',
'mmCP_EOP_DONE_DATA_CNTL_BASE_IDX', 'mmCP_EOP_DONE_DATA_HI',
'mmCP_EOP_DONE_DATA_HI_BASE_IDX', 'mmCP_EOP_DONE_DATA_LO',
'mmCP_EOP_DONE_DATA_LO_BASE_IDX', 'mmCP_EOP_DONE_EVENT_CNTL',
'mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX', 'mmCP_EOP_LAST_FENCE_HI',
'mmCP_EOP_LAST_FENCE_HI_BASE_IDX', 'mmCP_EOP_LAST_FENCE_LO',
'mmCP_EOP_LAST_FENCE_LO_BASE_IDX', 'mmCP_FATAL_ERROR',
'mmCP_FATAL_ERROR_BASE_IDX', 'mmCP_FETCHER_SOURCE',
'mmCP_FETCHER_SOURCE_BASE_IDX', 'mmCP_GDS_ATOMIC0_PREOP_HI',
'mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX', 'mmCP_GDS_ATOMIC0_PREOP_LO',
'mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX', 'mmCP_GDS_ATOMIC1_PREOP_HI',
'mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX', 'mmCP_GDS_ATOMIC1_PREOP_LO',
'mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'mmCP_GDS_BKUP_ADDR',
'mmCP_GDS_BKUP_ADDR_BASE_IDX', 'mmCP_GDS_BKUP_ADDR_HI',
'mmCP_GDS_BKUP_ADDR_HI_BASE_IDX', 'mmCP_GFX_DDID_DELTA_RPT_COUNT',
'mmCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX',
'mmCP_GFX_DDID_INFLIGHT_COUNT',
'mmCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX', 'mmCP_GFX_DDID_RPTR',
'mmCP_GFX_DDID_RPTR_BASE_IDX', 'mmCP_GFX_DDID_WPTR',
'mmCP_GFX_DDID_WPTR_BASE_IDX', 'mmCP_GFX_ERROR',
'mmCP_GFX_ERROR_BASE_IDX', 'mmCP_GFX_HPD_CONTROL0',
'mmCP_GFX_HPD_CONTROL0_BASE_IDX',
'mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI',
'mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX',
'mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO',
'mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX',
'mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI',
'mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX',
'mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO',
'mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX',
'mmCP_GFX_HPD_STATUS0', 'mmCP_GFX_HPD_STATUS0_BASE_IDX',
'mmCP_GFX_HQD_ACTIVE', 'mmCP_GFX_HQD_ACTIVE_BASE_IDX',
'mmCP_GFX_HQD_BASE', 'mmCP_GFX_HQD_BASE_BASE_IDX',
'mmCP_GFX_HQD_BASE_HI', 'mmCP_GFX_HQD_BASE_HI_BASE_IDX',
'mmCP_GFX_HQD_CE_BASE', 'mmCP_GFX_HQD_CE_BASE_BASE_IDX',
'mmCP_GFX_HQD_CE_BASE_HI', 'mmCP_GFX_HQD_CE_BASE_HI_BASE_IDX',
'mmCP_GFX_HQD_CE_CNTL', 'mmCP_GFX_HQD_CE_CNTL_BASE_IDX',
'mmCP_GFX_HQD_CE_CSMD_RPTR', 'mmCP_GFX_HQD_CE_CSMD_RPTR_BASE_IDX',
'mmCP_GFX_HQD_CE_OFFSET', 'mmCP_GFX_HQD_CE_OFFSET_BASE_IDX',
'mmCP_GFX_HQD_CE_RPTR', 'mmCP_GFX_HQD_CE_RPTR_ADDR',
'mmCP_GFX_HQD_CE_RPTR_ADDR_BASE_IDX',
'mmCP_GFX_HQD_CE_RPTR_ADDR_HI',
'mmCP_GFX_HQD_CE_RPTR_ADDR_HI_BASE_IDX',
'mmCP_GFX_HQD_CE_RPTR_BASE_IDX', 'mmCP_GFX_HQD_CE_RPTR_WR',
'mmCP_GFX_HQD_CE_RPTR_WR_BASE_IDX', 'mmCP_GFX_HQD_CE_WPTR',
'mmCP_GFX_HQD_CE_WPTR_BASE_IDX', 'mmCP_GFX_HQD_CE_WPTR_HI',
'mmCP_GFX_HQD_CE_WPTR_HI_BASE_IDX',
'mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI',
'mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO',
'mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO_BASE_IDX', 'mmCP_GFX_HQD_CNTL',
'mmCP_GFX_HQD_CNTL_BASE_IDX', 'mmCP_GFX_HQD_CSMD_RPTR',
'mmCP_GFX_HQD_CSMD_RPTR_BASE_IDX', 'mmCP_GFX_HQD_DEQUEUE_REQUEST',
'mmCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX',
'mmCP_GFX_HQD_HQ_CONTROL0', 'mmCP_GFX_HQD_HQ_CONTROL0_BASE_IDX',
'mmCP_GFX_HQD_HQ_STATUS0', 'mmCP_GFX_HQD_HQ_STATUS0_BASE_IDX',
'mmCP_GFX_HQD_MAPPED', 'mmCP_GFX_HQD_MAPPED_BASE_IDX',
'mmCP_GFX_HQD_OFFSET', 'mmCP_GFX_HQD_OFFSET_BASE_IDX',
'mmCP_GFX_HQD_QUANTUM', 'mmCP_GFX_HQD_QUANTUM_BASE_IDX',
'mmCP_GFX_HQD_QUEUE_PRIORITY',
'mmCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX',
'mmCP_GFX_HQD_QUE_MGR_CONTROL',
'mmCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX', 'mmCP_GFX_HQD_RPTR',
'mmCP_GFX_HQD_RPTR_ADDR', 'mmCP_GFX_HQD_RPTR_ADDR_BASE_IDX',
'mmCP_GFX_HQD_RPTR_ADDR_HI', 'mmCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX',
'mmCP_GFX_HQD_RPTR_BASE_IDX', 'mmCP_GFX_HQD_VMID',
'mmCP_GFX_HQD_VMID_BASE_IDX', 'mmCP_GFX_HQD_WPTR',
'mmCP_GFX_HQD_WPTR_BASE_IDX', 'mmCP_GFX_HQD_WPTR_HI',
'mmCP_GFX_HQD_WPTR_HI_BASE_IDX', 'mmCP_GFX_INDEX_MUTEX',
'mmCP_GFX_INDEX_MUTEX_BASE_IDX', 'mmCP_GFX_MQD_BASE_ADDR',
'mmCP_GFX_MQD_BASE_ADDR_BASE_IDX', 'mmCP_GFX_MQD_BASE_ADDR_HI',
'mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX', 'mmCP_GFX_MQD_CONTROL',
'mmCP_GFX_MQD_CONTROL_BASE_IDX', 'mmCP_GFX_QUEUE_INDEX',
'mmCP_GFX_QUEUE_INDEX_BASE_IDX', 'mmCP_GPU_TIMESTAMP_OFFSET_HI',
'mmCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX',
'mmCP_GPU_TIMESTAMP_OFFSET_LO',
'mmCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX', 'mmCP_GRBM_FREE_COUNT',
'mmCP_GRBM_FREE_COUNT_BASE_IDX', 'mmCP_HPD_MES_ROQ_OFFSETS',
'mmCP_HPD_MES_ROQ_OFFSETS_BASE_IDX', 'mmCP_HPD_ROQ_OFFSETS',
'mmCP_HPD_ROQ_OFFSETS_BASE_IDX', 'mmCP_HPD_STATUS0',
'mmCP_HPD_STATUS0_BASE_IDX', 'mmCP_HPD_UTCL1_CNTL',
'mmCP_HPD_UTCL1_CNTL_BASE_IDX', 'mmCP_HPD_UTCL1_ERROR',
'mmCP_HPD_UTCL1_ERROR_ADDR', 'mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX',
'mmCP_HPD_UTCL1_ERROR_BASE_IDX', 'mmCP_HQD_ACTIVE',
'mmCP_HQD_ACTIVE_BASE_IDX', 'mmCP_HQD_AQL_CONTROL',
'mmCP_HQD_AQL_CONTROL_BASE_IDX', 'mmCP_HQD_ATOMIC0_PREOP_HI',
'mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX', 'mmCP_HQD_ATOMIC0_PREOP_LO',
'mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX', 'mmCP_HQD_ATOMIC1_PREOP_HI',
'mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX', 'mmCP_HQD_ATOMIC1_PREOP_LO',
'mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX',
'mmCP_HQD_CNTL_STACK_OFFSET',
'mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX', 'mmCP_HQD_CNTL_STACK_SIZE',
'mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX',
'mmCP_HQD_CTX_SAVE_BASE_ADDR_HI',
'mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX',
'mmCP_HQD_CTX_SAVE_BASE_ADDR_LO',
'mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX',
'mmCP_HQD_CTX_SAVE_CONTROL', 'mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX',
'mmCP_HQD_CTX_SAVE_SIZE', 'mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX',
'mmCP_HQD_DDID_DELTA_RPT_COUNT',
'mmCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX',
'mmCP_HQD_DDID_INFLIGHT_COUNT',
'mmCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX', 'mmCP_HQD_DDID_RPTR',
'mmCP_HQD_DDID_RPTR_BASE_IDX', 'mmCP_HQD_DDID_WPTR',
'mmCP_HQD_DDID_WPTR_BASE_IDX', 'mmCP_HQD_DEQUEUE_REQUEST',
'mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX', 'mmCP_HQD_DEQUEUE_STATUS',
'mmCP_HQD_DEQUEUE_STATUS_BASE_IDX', 'mmCP_HQD_DMA_OFFLOAD',
'mmCP_HQD_DMA_OFFLOAD_BASE_IDX', 'mmCP_HQD_EOP_BASE_ADDR',
'mmCP_HQD_EOP_BASE_ADDR_BASE_IDX', 'mmCP_HQD_EOP_BASE_ADDR_HI',
'mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX', 'mmCP_HQD_EOP_CONTROL',
'mmCP_HQD_EOP_CONTROL_BASE_IDX', 'mmCP_HQD_EOP_EVENTS',
'mmCP_HQD_EOP_EVENTS_BASE_IDX', 'mmCP_HQD_EOP_RPTR',
'mmCP_HQD_EOP_RPTR_BASE_IDX', 'mmCP_HQD_EOP_WPTR',
'mmCP_HQD_EOP_WPTR_BASE_IDX', 'mmCP_HQD_EOP_WPTR_MEM',
'mmCP_HQD_EOP_WPTR_MEM_BASE_IDX', 'mmCP_HQD_ERROR',
'mmCP_HQD_ERROR_BASE_IDX', 'mmCP_HQD_GDS_RESOURCE_STATE',
'mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX', 'mmCP_HQD_GFX_CONTROL',
'mmCP_HQD_GFX_CONTROL_BASE_IDX', 'mmCP_HQD_GFX_STATUS',
'mmCP_HQD_GFX_STATUS_BASE_IDX', 'mmCP_HQD_HQ_CONTROL0',
'mmCP_HQD_HQ_CONTROL0_BASE_IDX', 'mmCP_HQD_HQ_CONTROL1',
'mmCP_HQD_HQ_CONTROL1_BASE_IDX', 'mmCP_HQD_HQ_SCHEDULER0',
'mmCP_HQD_HQ_SCHEDULER0_BASE_IDX', 'mmCP_HQD_HQ_SCHEDULER1',
'mmCP_HQD_HQ_SCHEDULER1_BASE_IDX', 'mmCP_HQD_HQ_STATUS0',
'mmCP_HQD_HQ_STATUS0_BASE_IDX', 'mmCP_HQD_HQ_STATUS1',
'mmCP_HQD_HQ_STATUS1_BASE_IDX', 'mmCP_HQD_IB_BASE_ADDR',
'mmCP_HQD_IB_BASE_ADDR_BASE_IDX', 'mmCP_HQD_IB_BASE_ADDR_HI',
'mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX', 'mmCP_HQD_IB_CONTROL',
'mmCP_HQD_IB_CONTROL_BASE_IDX', 'mmCP_HQD_IB_RPTR',
'mmCP_HQD_IB_RPTR_BASE_IDX', 'mmCP_HQD_IQ_RPTR',
'mmCP_HQD_IQ_RPTR_BASE_IDX', 'mmCP_HQD_IQ_TIMER',
'mmCP_HQD_IQ_TIMER_BASE_IDX', 'mmCP_HQD_MSG_TYPE',
'mmCP_HQD_MSG_TYPE_BASE_IDX', 'mmCP_HQD_OFFLOAD',
'mmCP_HQD_OFFLOAD_BASE_IDX', 'mmCP_HQD_PERSISTENT_STATE',
'mmCP_HQD_PERSISTENT_STATE_BASE_IDX', 'mmCP_HQD_PIPE_PRIORITY',
'mmCP_HQD_PIPE_PRIORITY_BASE_IDX', 'mmCP_HQD_PQ_BASE',
'mmCP_HQD_PQ_BASE_BASE_IDX', 'mmCP_HQD_PQ_BASE_HI',
'mmCP_HQD_PQ_BASE_HI_BASE_IDX', 'mmCP_HQD_PQ_CONTROL',
'mmCP_HQD_PQ_CONTROL_BASE_IDX', 'mmCP_HQD_PQ_DOORBELL_CONTROL',
'mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX', 'mmCP_HQD_PQ_RPTR',
'mmCP_HQD_PQ_RPTR_BASE_IDX', 'mmCP_HQD_PQ_RPTR_REPORT_ADDR',
'mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX',
'mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI',
'mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX', 'mmCP_HQD_PQ_WPTR_HI',
'mmCP_HQD_PQ_WPTR_HI_BASE_IDX', 'mmCP_HQD_PQ_WPTR_LO',
'mmCP_HQD_PQ_WPTR_LO_BASE_IDX', 'mmCP_HQD_PQ_WPTR_POLL_ADDR',
'mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX',
'mmCP_HQD_PQ_WPTR_POLL_ADDR_HI',
'mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX', 'mmCP_HQD_QUANTUM',
'mmCP_HQD_QUANTUM_BASE_IDX', 'mmCP_HQD_QUEUE_PRIORITY',
'mmCP_HQD_QUEUE_PRIORITY_BASE_IDX', 'mmCP_HQD_SEMA_CMD',
'mmCP_HQD_SEMA_CMD_BASE_IDX',
'mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT',
'mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX',
'mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET',
'mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX',
'mmCP_HQD_SUSPEND_WG_STATE_OFFSET',
'mmCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX', 'mmCP_HQD_VMID',
'mmCP_HQD_VMID_BASE_IDX', 'mmCP_HQD_WG_STATE_OFFSET',
'mmCP_HQD_WG_STATE_OFFSET_BASE_IDX', 'mmCP_HYP_CE_UCODE_ADDR',
'mmCP_HYP_CE_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_CE_UCODE_DATA',
'mmCP_HYP_CE_UCODE_DATA_BASE_IDX', 'mmCP_HYP_MEC1_UCODE_ADDR',
'mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_MEC1_UCODE_DATA',
'mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX', 'mmCP_HYP_MEC2_UCODE_ADDR',
'mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_MEC2_UCODE_DATA',
'mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX', 'mmCP_HYP_ME_UCODE_ADDR',
'mmCP_HYP_ME_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_ME_UCODE_DATA',
'mmCP_HYP_ME_UCODE_DATA_BASE_IDX', 'mmCP_HYP_PFP_UCODE_ADDR',
'mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_PFP_UCODE_DATA',
'mmCP_HYP_PFP_UCODE_DATA_BASE_IDX', 'mmCP_IB1_BASE_HI',
'mmCP_IB1_BASE_HI_BASE_IDX', 'mmCP_IB1_BASE_LO',
'mmCP_IB1_BASE_LO_BASE_IDX', 'mmCP_IB1_BUFSZ',
'mmCP_IB1_BUFSZ_BASE_IDX', 'mmCP_IB2_BASE_HI',
'mmCP_IB2_BASE_HI_BASE_IDX', 'mmCP_IB2_BASE_LO',
'mmCP_IB2_BASE_LO_BASE_IDX', 'mmCP_IB2_BUFSZ',
'mmCP_IB2_BUFSZ_BASE_IDX', 'mmCP_IB2_CMD_BUFSZ',
'mmCP_IB2_CMD_BUFSZ_BASE_IDX', 'mmCP_IB2_OFFSET',
'mmCP_IB2_OFFSET_BASE_IDX', 'mmCP_IB2_PREAMBLE_BEGIN',
'mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX', 'mmCP_IB2_PREAMBLE_END',
'mmCP_IB2_PREAMBLE_END_BASE_IDX', 'mmCP_INDEX_BASE_ADDR',
'mmCP_INDEX_BASE_ADDR_BASE_IDX', 'mmCP_INDEX_BASE_ADDR_HI',
'mmCP_INDEX_BASE_ADDR_HI_BASE_IDX', 'mmCP_INDEX_TYPE',
'mmCP_INDEX_TYPE_BASE_IDX', 'mmCP_INT_CNTL',
'mmCP_INT_CNTL_BASE_IDX', 'mmCP_INT_CNTL_RING0',
'mmCP_INT_CNTL_RING0_BASE_IDX', 'mmCP_INT_CNTL_RING1',
'mmCP_INT_CNTL_RING1_BASE_IDX', 'mmCP_INT_CNTL_RING2',
'mmCP_INT_CNTL_RING2_BASE_IDX', 'mmCP_INT_STATUS',
'mmCP_INT_STATUS_BASE_IDX', 'mmCP_INT_STATUS_RING0',
'mmCP_INT_STATUS_RING0_BASE_IDX', 'mmCP_INT_STATUS_RING1',
'mmCP_INT_STATUS_RING1_BASE_IDX', 'mmCP_INT_STATUS_RING2',
'mmCP_INT_STATUS_RING2_BASE_IDX', 'mmCP_IQ_WAIT_TIME1',
'mmCP_IQ_WAIT_TIME1_BASE_IDX', 'mmCP_IQ_WAIT_TIME2',
'mmCP_IQ_WAIT_TIME2_BASE_IDX', 'mmCP_IQ_WAIT_TIME3',
'mmCP_IQ_WAIT_TIME3_BASE_IDX', 'mmCP_MAX_CONTEXT',
'mmCP_MAX_CONTEXT_BASE_IDX', 'mmCP_ME0_PIPE0_PRIORITY',
'mmCP_ME0_PIPE0_PRIORITY_BASE_IDX', 'mmCP_ME0_PIPE0_VMID',
'mmCP_ME0_PIPE0_VMID_BASE_IDX', 'mmCP_ME0_PIPE1_PRIORITY',
'mmCP_ME0_PIPE1_PRIORITY_BASE_IDX', 'mmCP_ME0_PIPE1_VMID',
'mmCP_ME0_PIPE1_VMID_BASE_IDX', 'mmCP_ME0_PIPE2_PRIORITY',
'mmCP_ME0_PIPE2_PRIORITY_BASE_IDX', 'mmCP_ME0_PIPE_PRIORITY_CNTS',
'mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX', 'mmCP_ME1_INT_STAT_DEBUG',
'mmCP_ME1_INT_STAT_DEBUG_BASE_IDX', 'mmCP_ME1_PIPE0_INT_CNTL',
'mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX', 'mmCP_ME1_PIPE0_INT_STATUS',
'mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX', 'mmCP_ME1_PIPE0_PRIORITY',
'mmCP_ME1_PIPE0_PRIORITY_BASE_IDX', 'mmCP_ME1_PIPE1_INT_CNTL',
'mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX', 'mmCP_ME1_PIPE1_INT_STATUS',
'mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX', 'mmCP_ME1_PIPE1_PRIORITY',
'mmCP_ME1_PIPE1_PRIORITY_BASE_IDX', 'mmCP_ME1_PIPE2_INT_CNTL',
'mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX', 'mmCP_ME1_PIPE2_INT_STATUS',
'mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX', 'mmCP_ME1_PIPE2_PRIORITY',
'mmCP_ME1_PIPE2_PRIORITY_BASE_IDX', 'mmCP_ME1_PIPE3_INT_CNTL',
'mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX', 'mmCP_ME1_PIPE3_INT_STATUS',
'mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX', 'mmCP_ME1_PIPE3_PRIORITY',
'mmCP_ME1_PIPE3_PRIORITY_BASE_IDX', 'mmCP_ME1_PIPE_PRIORITY_CNTS',
'mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX', 'mmCP_ME2_INT_STAT_DEBUG',
'mmCP_ME2_INT_STAT_DEBUG_BASE_IDX', 'mmCP_ME2_PIPE0_INT_CNTL',
'mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX', 'mmCP_ME2_PIPE0_INT_STATUS',
'mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX', 'mmCP_ME2_PIPE0_PRIORITY',
'mmCP_ME2_PIPE0_PRIORITY_BASE_IDX', 'mmCP_ME2_PIPE1_INT_CNTL',
'mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX', 'mmCP_ME2_PIPE1_INT_STATUS',
'mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX', 'mmCP_ME2_PIPE1_PRIORITY',
'mmCP_ME2_PIPE1_PRIORITY_BASE_IDX', 'mmCP_ME2_PIPE2_INT_CNTL',
'mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX', 'mmCP_ME2_PIPE2_INT_STATUS',
'mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX', 'mmCP_ME2_PIPE2_PRIORITY',
'mmCP_ME2_PIPE2_PRIORITY_BASE_IDX', 'mmCP_ME2_PIPE3_INT_CNTL',
'mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX', 'mmCP_ME2_PIPE3_INT_STATUS',
'mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX', 'mmCP_ME2_PIPE3_PRIORITY',
'mmCP_ME2_PIPE3_PRIORITY_BASE_IDX', 'mmCP_ME2_PIPE_PRIORITY_CNTS',
'mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX', 'mmCP_MEC1_F32_INTERRUPT',
'mmCP_MEC1_F32_INTERRUPT_BASE_IDX', 'mmCP_MEC1_F32_INT_DIS',
'mmCP_MEC1_F32_INT_DIS_BASE_IDX', 'mmCP_MEC1_INSTR_PNTR',
'mmCP_MEC1_INSTR_PNTR_BASE_IDX', 'mmCP_MEC1_INTR_ROUTINE_START',
'mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX',
'mmCP_MEC1_PRGRM_CNTR_START',
'mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX', 'mmCP_MEC2_F32_INTERRUPT',
'mmCP_MEC2_F32_INTERRUPT_BASE_IDX', 'mmCP_MEC2_F32_INT_DIS',
'mmCP_MEC2_F32_INT_DIS_BASE_IDX', 'mmCP_MEC2_INSTR_PNTR',
'mmCP_MEC2_INSTR_PNTR_BASE_IDX', 'mmCP_MEC2_INTR_ROUTINE_START',
'mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX',
'mmCP_MEC2_PRGRM_CNTR_START',
'mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX', 'mmCP_MEC_CNTL',
'mmCP_MEC_CNTL_BASE_IDX', 'mmCP_MEC_DOORBELL_RANGE_LOWER',
'mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX',
'mmCP_MEC_DOORBELL_RANGE_UPPER',
'mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX', 'mmCP_MEC_JT_STAT',
'mmCP_MEC_JT_STAT_BASE_IDX', 'mmCP_MEC_ME1_HEADER_DUMP',
'mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX', 'mmCP_MEC_ME1_UCODE_ADDR',
'mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX', 'mmCP_MEC_ME1_UCODE_DATA',
'mmCP_MEC_ME1_UCODE_DATA_BASE_IDX', 'mmCP_MEC_ME2_HEADER_DUMP',
'mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX', 'mmCP_MEC_ME2_UCODE_ADDR',
'mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX', 'mmCP_MEC_ME2_UCODE_DATA',
'mmCP_MEC_ME2_UCODE_DATA_BASE_IDX', 'mmCP_MEM_SLP_CNTL',
'mmCP_MEM_SLP_CNTL_BASE_IDX', 'mmCP_MEQ_AVAIL',
'mmCP_MEQ_AVAIL_BASE_IDX', 'mmCP_MEQ_STAT',
'mmCP_MEQ_STAT_BASE_IDX', 'mmCP_MEQ_STQ_THRESHOLD',
'mmCP_MEQ_STQ_THRESHOLD_BASE_IDX', 'mmCP_MEQ_THRESHOLDS',
'mmCP_MEQ_THRESHOLDS_BASE_IDX', 'mmCP_MES_CNTL',
'mmCP_MES_CNTL_BASE_IDX', 'mmCP_MES_DC_BASE_CNTL',
'mmCP_MES_DC_BASE_CNTL_BASE_IDX', 'mmCP_MES_DC_BASE_HI',
'mmCP_MES_DC_BASE_HI_BASE_IDX', 'mmCP_MES_DC_BASE_LO',
'mmCP_MES_DC_BASE_LO_BASE_IDX', 'mmCP_MES_DC_OP_CNTL',
'mmCP_MES_DC_OP_CNTL_BASE_IDX', 'mmCP_MES_DM_INDEX_ADDR',
'mmCP_MES_DM_INDEX_ADDR_BASE_IDX', 'mmCP_MES_DM_INDEX_DATA',
'mmCP_MES_DM_INDEX_DATA_BASE_IDX', 'mmCP_MES_DOORBELL_CONTROL1',
'mmCP_MES_DOORBELL_CONTROL1_BASE_IDX',
'mmCP_MES_DOORBELL_CONTROL2',
'mmCP_MES_DOORBELL_CONTROL2_BASE_IDX',
'mmCP_MES_DOORBELL_CONTROL3',
'mmCP_MES_DOORBELL_CONTROL3_BASE_IDX',
'mmCP_MES_DOORBELL_CONTROL4',
'mmCP_MES_DOORBELL_CONTROL4_BASE_IDX',
'mmCP_MES_DOORBELL_CONTROL5',
'mmCP_MES_DOORBELL_CONTROL5_BASE_IDX',
'mmCP_MES_DOORBELL_CONTROL6',
'mmCP_MES_DOORBELL_CONTROL6_BASE_IDX', 'mmCP_MES_GP0_HI',
'mmCP_MES_GP0_HI_BASE_IDX', 'mmCP_MES_GP0_LO',
'mmCP_MES_GP0_LO_BASE_IDX', 'mmCP_MES_GP1_HI',
'mmCP_MES_GP1_HI_BASE_IDX', 'mmCP_MES_GP1_LO',
'mmCP_MES_GP1_LO_BASE_IDX', 'mmCP_MES_GP2_HI',
'mmCP_MES_GP2_HI_BASE_IDX', 'mmCP_MES_GP2_LO',
'mmCP_MES_GP2_LO_BASE_IDX', 'mmCP_MES_GP3_HI',
'mmCP_MES_GP3_HI_BASE_IDX', 'mmCP_MES_GP3_LO',
'mmCP_MES_GP3_LO_BASE_IDX', 'mmCP_MES_GP4_HI',
'mmCP_MES_GP4_HI_BASE_IDX', 'mmCP_MES_GP4_LO',
'mmCP_MES_GP4_LO_BASE_IDX', 'mmCP_MES_GP5_HI',
'mmCP_MES_GP5_HI_BASE_IDX', 'mmCP_MES_GP5_LO',
'mmCP_MES_GP5_LO_BASE_IDX', 'mmCP_MES_GP6_HI',
'mmCP_MES_GP6_HI_BASE_IDX', 'mmCP_MES_GP6_LO',
'mmCP_MES_GP6_LO_BASE_IDX', 'mmCP_MES_GP7_HI',
'mmCP_MES_GP7_HI_BASE_IDX', 'mmCP_MES_GP7_LO',
'mmCP_MES_GP7_LO_BASE_IDX', 'mmCP_MES_GP8_HI',
'mmCP_MES_GP8_HI_BASE_IDX', 'mmCP_MES_GP8_LO',
'mmCP_MES_GP8_LO_BASE_IDX', 'mmCP_MES_GP9_HI',
'mmCP_MES_GP9_HI_BASE_IDX', 'mmCP_MES_GP9_LO',
'mmCP_MES_GP9_LO_BASE_IDX', 'mmCP_MES_HEADER_DUMP',
'mmCP_MES_HEADER_DUMP_BASE_IDX', 'mmCP_MES_IC_BASE_CNTL',
'mmCP_MES_IC_BASE_CNTL_BASE_IDX', 'mmCP_MES_IC_BASE_HI',
'mmCP_MES_IC_BASE_HI_BASE_IDX', 'mmCP_MES_IC_BASE_LO',
'mmCP_MES_IC_BASE_LO_BASE_IDX', 'mmCP_MES_IC_OP_CNTL',
'mmCP_MES_IC_OP_CNTL_BASE_IDX', 'mmCP_MES_INSTR_PNTR',
'mmCP_MES_INSTR_PNTR_BASE_IDX', 'mmCP_MES_INTERRUPT',
'mmCP_MES_INTERRUPT_BASE_IDX', 'mmCP_MES_INTR_ROUTINE_START',
'mmCP_MES_INTR_ROUTINE_START_BASE_IDX', 'mmCP_MES_LOCAL_APERTURE',
'mmCP_MES_LOCAL_APERTURE_BASE_IDX', 'mmCP_MES_LOCAL_BASE0_HI',
'mmCP_MES_LOCAL_BASE0_HI_BASE_IDX', 'mmCP_MES_LOCAL_BASE0_LO',
'mmCP_MES_LOCAL_BASE0_LO_BASE_IDX', 'mmCP_MES_LOCAL_MASK0_HI',
'mmCP_MES_LOCAL_MASK0_HI_BASE_IDX', 'mmCP_MES_LOCAL_MASK0_LO',
'mmCP_MES_LOCAL_MASK0_LO_BASE_IDX', 'mmCP_MES_MARCHID_HI',
'mmCP_MES_MARCHID_HI_BASE_IDX', 'mmCP_MES_MARCHID_LO',
'mmCP_MES_MARCHID_LO_BASE_IDX', 'mmCP_MES_MBADADDR_HI',
'mmCP_MES_MBADADDR_HI_BASE_IDX', 'mmCP_MES_MBADADDR_LO',
'mmCP_MES_MBADADDR_LO_BASE_IDX', 'mmCP_MES_MCAUSE_HI',
'mmCP_MES_MCAUSE_HI_BASE_IDX', 'mmCP_MES_MCAUSE_LO',
'mmCP_MES_MCAUSE_LO_BASE_IDX', 'mmCP_MES_MCYCLE_HI',
'mmCP_MES_MCYCLE_HI_BASE_IDX', 'mmCP_MES_MCYCLE_LO',
'mmCP_MES_MCYCLE_LO_BASE_IDX', 'mmCP_MES_MDBASE_HI',
'mmCP_MES_MDBASE_HI_BASE_IDX', 'mmCP_MES_MDBASE_LO',
'mmCP_MES_MDBASE_LO_BASE_IDX', 'mmCP_MES_MDBOUND_HI',
'mmCP_MES_MDBOUND_HI_BASE_IDX', 'mmCP_MES_MDBOUND_LO',
'mmCP_MES_MDBOUND_LO_BASE_IDX', 'mmCP_MES_MEPC_HI',
'mmCP_MES_MEPC_HI_BASE_IDX', 'mmCP_MES_MEPC_LO',
'mmCP_MES_MEPC_LO_BASE_IDX', 'mmCP_MES_MHARTID_HI',
'mmCP_MES_MHARTID_HI_BASE_IDX', 'mmCP_MES_MHARTID_LO',
'mmCP_MES_MHARTID_LO_BASE_IDX', 'mmCP_MES_MIBASE_HI',
'mmCP_MES_MIBASE_HI_BASE_IDX', 'mmCP_MES_MIBASE_LO',
'mmCP_MES_MIBASE_LO_BASE_IDX', 'mmCP_MES_MIBOUND_HI',
'mmCP_MES_MIBOUND_HI_BASE_IDX', 'mmCP_MES_MIBOUND_LO',
'mmCP_MES_MIBOUND_LO_BASE_IDX', 'mmCP_MES_MIE_HI',
'mmCP_MES_MIE_HI_BASE_IDX', 'mmCP_MES_MIE_LO',
'mmCP_MES_MIE_LO_BASE_IDX', 'mmCP_MES_MIMPID_HI',
'mmCP_MES_MIMPID_HI_BASE_IDX', 'mmCP_MES_MIMPID_LO',
'mmCP_MES_MIMPID_LO_BASE_IDX', 'mmCP_MES_MINSTRET_HI',
'mmCP_MES_MINSTRET_HI_BASE_IDX', 'mmCP_MES_MINSTRET_LO',
'mmCP_MES_MINSTRET_LO_BASE_IDX', 'mmCP_MES_MIP_HI',
'mmCP_MES_MIP_HI_BASE_IDX', 'mmCP_MES_MIP_LO',
'mmCP_MES_MIP_LO_BASE_IDX', 'mmCP_MES_MISA_HI',
'mmCP_MES_MISA_HI_BASE_IDX', 'mmCP_MES_MISA_LO',
'mmCP_MES_MISA_LO_BASE_IDX', 'mmCP_MES_MSCRATCH_HI',
'mmCP_MES_MSCRATCH_HI_BASE_IDX', 'mmCP_MES_MSCRATCH_LO',
'mmCP_MES_MSCRATCH_LO_BASE_IDX', 'mmCP_MES_MSTATUS_HI',
'mmCP_MES_MSTATUS_HI_BASE_IDX', 'mmCP_MES_MSTATUS_LO',
'mmCP_MES_MSTATUS_LO_BASE_IDX', 'mmCP_MES_MTIMECMP_HI',
'mmCP_MES_MTIMECMP_HI_BASE_IDX', 'mmCP_MES_MTIMECMP_LO',
'mmCP_MES_MTIMECMP_LO_BASE_IDX', 'mmCP_MES_MTIME_HI',
'mmCP_MES_MTIME_HI_BASE_IDX', 'mmCP_MES_MTIME_LO',
'mmCP_MES_MTIME_LO_BASE_IDX', 'mmCP_MES_MTVEC_HI',
'mmCP_MES_MTVEC_HI_BASE_IDX', 'mmCP_MES_MTVEC_LO',
'mmCP_MES_MTVEC_LO_BASE_IDX', 'mmCP_MES_MVENDORID_HI',
'mmCP_MES_MVENDORID_HI_BASE_IDX', 'mmCP_MES_MVENDORID_LO',
'mmCP_MES_MVENDORID_LO_BASE_IDX', 'mmCP_MES_PENDING_INTERRUPT',
'mmCP_MES_PENDING_INTERRUPT_BASE_IDX', 'mmCP_MES_PERFCOUNT_CNTL',
'mmCP_MES_PERFCOUNT_CNTL_BASE_IDX', 'mmCP_MES_PIPE0_PRIORITY',
'mmCP_MES_PIPE0_PRIORITY_BASE_IDX', 'mmCP_MES_PIPE1_PRIORITY',
'mmCP_MES_PIPE1_PRIORITY_BASE_IDX', 'mmCP_MES_PIPE2_PRIORITY',
'mmCP_MES_PIPE2_PRIORITY_BASE_IDX', 'mmCP_MES_PIPE3_PRIORITY',
'mmCP_MES_PIPE3_PRIORITY_BASE_IDX', 'mmCP_MES_PIPE_PRIORITY_CNTS',
'mmCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX',
'mmCP_MES_PRGRM_CNTR_START', 'mmCP_MES_PRGRM_CNTR_START_BASE_IDX',
'mmCP_MES_PROCESS_QUANTUM_PIPE0',
'mmCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX',
'mmCP_MES_PROCESS_QUANTUM_PIPE1',
'mmCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX',
'mmCP_MES_SCRATCH_DATA', 'mmCP_MES_SCRATCH_DATA_BASE_IDX',
'mmCP_MES_SCRATCH_INDEX', 'mmCP_MES_SCRATCH_INDEX_BASE_IDX',
'mmCP_ME_ATOMIC_PREOP_HI', 'mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX',
'mmCP_ME_ATOMIC_PREOP_LO', 'mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX',
'mmCP_ME_CNTL', 'mmCP_ME_CNTL_BASE_IDX', 'mmCP_ME_COHER_BASE',
'mmCP_ME_COHER_BASE_BASE_IDX', 'mmCP_ME_COHER_BASE_HI',
'mmCP_ME_COHER_BASE_HI_BASE_IDX', 'mmCP_ME_COHER_CNTL',
'mmCP_ME_COHER_CNTL_BASE_IDX', 'mmCP_ME_COHER_SIZE',
'mmCP_ME_COHER_SIZE_BASE_IDX', 'mmCP_ME_COHER_SIZE_HI',
'mmCP_ME_COHER_SIZE_HI_BASE_IDX', 'mmCP_ME_COHER_STATUS',
'mmCP_ME_COHER_STATUS_BASE_IDX', 'mmCP_ME_F32_INTERRUPT',
'mmCP_ME_F32_INTERRUPT_BASE_IDX', 'mmCP_ME_GDS_ATOMIC0_PREOP_HI',
'mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX',
'mmCP_ME_GDS_ATOMIC0_PREOP_LO',
'mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX',
'mmCP_ME_GDS_ATOMIC1_PREOP_HI',
'mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX',
'mmCP_ME_GDS_ATOMIC1_PREOP_LO',
'mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'mmCP_ME_HEADER_DUMP',
'mmCP_ME_HEADER_DUMP_BASE_IDX', 'mmCP_ME_IC_BASE_CNTL',
'mmCP_ME_IC_BASE_CNTL_BASE_IDX', 'mmCP_ME_IC_BASE_HI',
'mmCP_ME_IC_BASE_HI_BASE_IDX', 'mmCP_ME_IC_BASE_LO',
'mmCP_ME_IC_BASE_LO_BASE_IDX', 'mmCP_ME_IC_OP_CNTL',
'mmCP_ME_IC_OP_CNTL_BASE_IDX', 'mmCP_ME_INSTR_PNTR',
'mmCP_ME_INSTR_PNTR_BASE_IDX', 'mmCP_ME_INTR_ROUTINE_START',
'mmCP_ME_INTR_ROUTINE_START_BASE_IDX', 'mmCP_ME_MC_RADDR_HI',
'mmCP_ME_MC_RADDR_HI_BASE_IDX', 'mmCP_ME_MC_RADDR_LO',
'mmCP_ME_MC_RADDR_LO_BASE_IDX', 'mmCP_ME_MC_WADDR_HI',
'mmCP_ME_MC_WADDR_HI_BASE_IDX', 'mmCP_ME_MC_WADDR_LO',
'mmCP_ME_MC_WADDR_LO_BASE_IDX', 'mmCP_ME_MC_WDATA_HI',
'mmCP_ME_MC_WDATA_HI_BASE_IDX', 'mmCP_ME_MC_WDATA_LO',
'mmCP_ME_MC_WDATA_LO_BASE_IDX', 'mmCP_ME_PREEMPTION',
'mmCP_ME_PREEMPTION_BASE_IDX', 'mmCP_ME_PRGRM_CNTR_START',
'mmCP_ME_PRGRM_CNTR_START_BASE_IDX', 'mmCP_ME_RAM_DATA',
'mmCP_ME_RAM_DATA_BASE_IDX', 'mmCP_ME_RAM_RADDR',
'mmCP_ME_RAM_RADDR_BASE_IDX', 'mmCP_ME_RAM_WADDR',
'mmCP_ME_RAM_WADDR_BASE_IDX', 'mmCP_MQD_BASE_ADDR',
'mmCP_MQD_BASE_ADDR_BASE_IDX', 'mmCP_MQD_BASE_ADDR_HI',
'mmCP_MQD_BASE_ADDR_HI_BASE_IDX', 'mmCP_MQD_CONTROL',
'mmCP_MQD_CONTROL_BASE_IDX', 'mmCP_NUM_PRIM_NEEDED_COUNT0_HI',
'mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX',
'mmCP_NUM_PRIM_NEEDED_COUNT0_LO',
'mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX',
'mmCP_NUM_PRIM_NEEDED_COUNT1_HI',
'mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX',
'mmCP_NUM_PRIM_NEEDED_COUNT1_LO',
'mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX',
'mmCP_NUM_PRIM_NEEDED_COUNT2_HI',
'mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX',
'mmCP_NUM_PRIM_NEEDED_COUNT2_LO',
'mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX',
'mmCP_NUM_PRIM_NEEDED_COUNT3_HI',
'mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX',
'mmCP_NUM_PRIM_NEEDED_COUNT3_LO',
'mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX',
'mmCP_NUM_PRIM_WRITTEN_COUNT0_HI',
'mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX',
'mmCP_NUM_PRIM_WRITTEN_COUNT0_LO',
'mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX',
'mmCP_NUM_PRIM_WRITTEN_COUNT1_HI',
'mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX',
'mmCP_NUM_PRIM_WRITTEN_COUNT1_LO',
'mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX',
'mmCP_NUM_PRIM_WRITTEN_COUNT2_HI',
'mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX',
'mmCP_NUM_PRIM_WRITTEN_COUNT2_LO',
'mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX',
'mmCP_NUM_PRIM_WRITTEN_COUNT3_HI',
'mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX',
'mmCP_NUM_PRIM_WRITTEN_COUNT3_LO',
'mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX',
'mmCP_PA_CINVOC_COUNT_HI', 'mmCP_PA_CINVOC_COUNT_HI_BASE_IDX',
'mmCP_PA_CINVOC_COUNT_LO', 'mmCP_PA_CINVOC_COUNT_LO_BASE_IDX',
'mmCP_PA_CPRIM_COUNT_HI', 'mmCP_PA_CPRIM_COUNT_HI_BASE_IDX',
'mmCP_PA_CPRIM_COUNT_LO', 'mmCP_PA_CPRIM_COUNT_LO_BASE_IDX',
'mmCP_PERFMON_CNTL', 'mmCP_PERFMON_CNTL_BASE_IDX',
'mmCP_PERFMON_CNTX_CNTL', 'mmCP_PERFMON_CNTX_CNTL_BASE_IDX',
'mmCP_PFP_ATOMIC_PREOP_HI', 'mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX',
'mmCP_PFP_ATOMIC_PREOP_LO', 'mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX',
'mmCP_PFP_COMPLETION_STATUS',
'mmCP_PFP_COMPLETION_STATUS_BASE_IDX', 'mmCP_PFP_F32_INTERRUPT',
'mmCP_PFP_F32_INTERRUPT_BASE_IDX',
'mmCP_PFP_GDS_ATOMIC0_PREOP_HI',
'mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX',
'mmCP_PFP_GDS_ATOMIC0_PREOP_LO',
'mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX',
'mmCP_PFP_GDS_ATOMIC1_PREOP_HI',
'mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX',
'mmCP_PFP_GDS_ATOMIC1_PREOP_LO',
'mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'mmCP_PFP_HEADER_DUMP',
'mmCP_PFP_HEADER_DUMP_BASE_IDX', 'mmCP_PFP_IB_CONTROL',
'mmCP_PFP_IB_CONTROL_BASE_IDX', 'mmCP_PFP_IC_BASE_CNTL',
'mmCP_PFP_IC_BASE_CNTL_BASE_IDX', 'mmCP_PFP_IC_BASE_HI',
'mmCP_PFP_IC_BASE_HI_BASE_IDX', 'mmCP_PFP_IC_BASE_LO',
'mmCP_PFP_IC_BASE_LO_BASE_IDX', 'mmCP_PFP_IC_OP_CNTL',
'mmCP_PFP_IC_OP_CNTL_BASE_IDX', 'mmCP_PFP_INSTR_PNTR',
'mmCP_PFP_INSTR_PNTR_BASE_IDX', 'mmCP_PFP_INTR_ROUTINE_START',
'mmCP_PFP_INTR_ROUTINE_START_BASE_IDX', 'mmCP_PFP_JT_STAT',
'mmCP_PFP_JT_STAT_BASE_IDX', 'mmCP_PFP_LOAD_CONTROL',
'mmCP_PFP_LOAD_CONTROL_BASE_IDX', 'mmCP_PFP_METADATA_BASE_ADDR',
'mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX',
'mmCP_PFP_METADATA_BASE_ADDR_HI',
'mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX',
'mmCP_PFP_PRGRM_CNTR_START', 'mmCP_PFP_PRGRM_CNTR_START_BASE_IDX',
'mmCP_PFP_UCODE_ADDR', 'mmCP_PFP_UCODE_ADDR_BASE_IDX',
'mmCP_PFP_UCODE_DATA', 'mmCP_PFP_UCODE_DATA_BASE_IDX',
'mmCP_PIPEID', 'mmCP_PIPEID_BASE_IDX', 'mmCP_PIPE_STATS_ADDR_HI',
'mmCP_PIPE_STATS_ADDR_HI_BASE_IDX', 'mmCP_PIPE_STATS_ADDR_LO',
'mmCP_PIPE_STATS_ADDR_LO_BASE_IDX', 'mmCP_PIPE_STATS_CONTROL',
'mmCP_PIPE_STATS_CONTROL_BASE_IDX', 'mmCP_PQ_STATUS',
'mmCP_PQ_STATUS_BASE_IDX', 'mmCP_PQ_WPTR_POLL_CNTL',
'mmCP_PQ_WPTR_POLL_CNTL1', 'mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX',
'mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX', 'mmCP_PRED_NOT_VISIBLE',
'mmCP_PRED_NOT_VISIBLE_BASE_IDX', 'mmCP_PRIV_VIOLATION_ADDR',
'mmCP_PRIV_VIOLATION_ADDR_BASE_IDX', 'mmCP_PROCESS_QUANTUM',
'mmCP_PROCESS_QUANTUM_BASE_IDX', 'mmCP_PWR_CNTL',
'mmCP_PWR_CNTL_BASE_IDX', 'mmCP_QUEUE_THRESHOLDS',
'mmCP_QUEUE_THRESHOLDS_BASE_IDX', 'mmCP_RB0_ACTIVE',
'mmCP_RB0_ACTIVE_BASE_IDX', 'mmCP_RB0_BASE',
'mmCP_RB0_BASE_BASE_IDX', 'mmCP_RB0_BASE_HI',
'mmCP_RB0_BASE_HI_BASE_IDX', 'mmCP_RB0_BUFSZ_MASK',
'mmCP_RB0_BUFSZ_MASK_BASE_IDX', 'mmCP_RB0_CNTL',
'mmCP_RB0_CNTL_BASE_IDX', 'mmCP_RB0_RPTR', 'mmCP_RB0_RPTR_ADDR',
'mmCP_RB0_RPTR_ADDR_BASE_IDX', 'mmCP_RB0_RPTR_ADDR_HI',
'mmCP_RB0_RPTR_ADDR_HI_BASE_IDX', 'mmCP_RB0_RPTR_BASE_IDX',
'mmCP_RB0_WPTR', 'mmCP_RB0_WPTR_BASE_IDX', 'mmCP_RB0_WPTR_HI',
'mmCP_RB0_WPTR_HI_BASE_IDX', 'mmCP_RB1_ACTIVE',
'mmCP_RB1_ACTIVE_BASE_IDX', 'mmCP_RB1_BASE',
'mmCP_RB1_BASE_BASE_IDX', 'mmCP_RB1_BASE_HI',
'mmCP_RB1_BASE_HI_BASE_IDX', 'mmCP_RB1_BUFSZ_MASK',
'mmCP_RB1_BUFSZ_MASK_BASE_IDX', 'mmCP_RB1_CNTL',
'mmCP_RB1_CNTL_BASE_IDX', 'mmCP_RB1_RPTR', 'mmCP_RB1_RPTR_ADDR',
'mmCP_RB1_RPTR_ADDR_BASE_IDX', 'mmCP_RB1_RPTR_ADDR_HI',
'mmCP_RB1_RPTR_ADDR_HI_BASE_IDX', 'mmCP_RB1_RPTR_BASE_IDX',
'mmCP_RB1_WPTR', 'mmCP_RB1_WPTR_BASE_IDX', 'mmCP_RB1_WPTR_HI',
'mmCP_RB1_WPTR_HI_BASE_IDX', 'mmCP_RB2_BASE',
'mmCP_RB2_BASE_BASE_IDX', 'mmCP_RB2_CNTL',
'mmCP_RB2_CNTL_BASE_IDX', 'mmCP_RB2_RPTR', 'mmCP_RB2_RPTR_ADDR',
'mmCP_RB2_RPTR_ADDR_BASE_IDX', 'mmCP_RB2_RPTR_ADDR_HI',
'mmCP_RB2_RPTR_ADDR_HI_BASE_IDX', 'mmCP_RB2_RPTR_BASE_IDX',
'mmCP_RB2_WPTR', 'mmCP_RB2_WPTR_BASE_IDX', 'mmCP_RB_ACTIVE',
'mmCP_RB_ACTIVE_BASE_IDX', 'mmCP_RB_BASE',
'mmCP_RB_BASE_BASE_IDX', 'mmCP_RB_BUFSZ_MASK',
'mmCP_RB_BUFSZ_MASK_BASE_IDX', 'mmCP_RB_CNTL',
'mmCP_RB_CNTL_BASE_IDX', 'mmCP_RB_DOORBELL_CLEAR',
'mmCP_RB_DOORBELL_CLEAR_BASE_IDX', 'mmCP_RB_DOORBELL_CONTROL',
'mmCP_RB_DOORBELL_CONTROL_BASE_IDX',
'mmCP_RB_DOORBELL_RANGE_LOWER',
'mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX',
'mmCP_RB_DOORBELL_RANGE_UPPER',
'mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX', 'mmCP_RB_OFFSET',
'mmCP_RB_OFFSET_BASE_IDX', 'mmCP_RB_RPTR', 'mmCP_RB_RPTR_ADDR',
'mmCP_RB_RPTR_ADDR_BASE_IDX', 'mmCP_RB_RPTR_ADDR_HI',
'mmCP_RB_RPTR_ADDR_HI_BASE_IDX', 'mmCP_RB_RPTR_BASE_IDX',
'mmCP_RB_RPTR_WR', 'mmCP_RB_RPTR_WR_BASE_IDX', 'mmCP_RB_STATUS',
'mmCP_RB_STATUS_BASE_IDX', 'mmCP_RB_VMID',
'mmCP_RB_VMID_BASE_IDX', 'mmCP_RB_WPTR', 'mmCP_RB_WPTR_BASE_IDX',
'mmCP_RB_WPTR_DELAY', 'mmCP_RB_WPTR_DELAY_BASE_IDX',
'mmCP_RB_WPTR_HI', 'mmCP_RB_WPTR_HI_BASE_IDX',
'mmCP_RB_WPTR_POLL_ADDR_HI', 'mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmCP_RB_WPTR_POLL_ADDR_LO', 'mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmCP_RB_WPTR_POLL_CNTL', 'mmCP_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmCP_RING0_PRIORITY', 'mmCP_RING0_PRIORITY_BASE_IDX',
'mmCP_RING1_PRIORITY', 'mmCP_RING1_PRIORITY_BASE_IDX',
'mmCP_RING2_PRIORITY', 'mmCP_RING2_PRIORITY_BASE_IDX',
'mmCP_RINGID', 'mmCP_RINGID_BASE_IDX', 'mmCP_RING_PRIORITY_CNTS',
'mmCP_RING_PRIORITY_CNTS_BASE_IDX', 'mmCP_ROQ1_THRESHOLDS',
'mmCP_ROQ1_THRESHOLDS_BASE_IDX', 'mmCP_ROQ2_AVAIL',
'mmCP_ROQ2_AVAIL_BASE_IDX', 'mmCP_ROQ2_THRESHOLDS',
'mmCP_ROQ2_THRESHOLDS_BASE_IDX', 'mmCP_ROQ3_THRESHOLDS',
'mmCP_ROQ3_THRESHOLDS_BASE_IDX', 'mmCP_ROQ_AVAIL',
'mmCP_ROQ_AVAIL_BASE_IDX', 'mmCP_ROQ_DB_STAT',
'mmCP_ROQ_DB_STAT_BASE_IDX', 'mmCP_ROQ_IB1_STAT',
'mmCP_ROQ_IB1_STAT_BASE_IDX', 'mmCP_ROQ_IB2_STAT',
'mmCP_ROQ_IB2_STAT_BASE_IDX', 'mmCP_ROQ_RB_STAT',
'mmCP_ROQ_RB_STAT_BASE_IDX', 'mmCP_ROQ_THRESHOLDS',
'mmCP_ROQ_THRESHOLDS_BASE_IDX', 'mmCP_SAMPLE_STATUS',
'mmCP_SAMPLE_STATUS_BASE_IDX', 'mmCP_SCRATCH_DATA',
'mmCP_SCRATCH_DATA_BASE_IDX', 'mmCP_SCRATCH_INDEX',
'mmCP_SCRATCH_INDEX_BASE_IDX', 'mmCP_SC_PSINVOC_COUNT0_HI',
'mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX', 'mmCP_SC_PSINVOC_COUNT0_LO',
'mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX', 'mmCP_SC_PSINVOC_COUNT1_HI',
'mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX', 'mmCP_SC_PSINVOC_COUNT1_LO',
'mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX', 'mmCP_SD_CNTL',
'mmCP_SD_CNTL_BASE_IDX', 'mmCP_SEM_WAIT_TIMER',
'mmCP_SEM_WAIT_TIMER_BASE_IDX', 'mmCP_SIG_SEM_ADDR_HI',
'mmCP_SIG_SEM_ADDR_HI_BASE_IDX', 'mmCP_SIG_SEM_ADDR_LO',
'mmCP_SIG_SEM_ADDR_LO_BASE_IDX', 'mmCP_SOFT_RESET_CNTL',
'mmCP_SOFT_RESET_CNTL_BASE_IDX', 'mmCP_STALLED_STAT1',
'mmCP_STALLED_STAT1_BASE_IDX', 'mmCP_STALLED_STAT2',
'mmCP_STALLED_STAT2_BASE_IDX', 'mmCP_STALLED_STAT3',
'mmCP_STALLED_STAT3_BASE_IDX', 'mmCP_STAT', 'mmCP_STAT_BASE_IDX',
'mmCP_STQ_AVAIL', 'mmCP_STQ_AVAIL_BASE_IDX', 'mmCP_STQ_STAT',
'mmCP_STQ_STAT_BASE_IDX', 'mmCP_STQ_THRESHOLDS',
'mmCP_STQ_THRESHOLDS_BASE_IDX', 'mmCP_STQ_WR_STAT',
'mmCP_STQ_WR_STAT_BASE_IDX', 'mmCP_STREAM_OUT_ADDR_HI',
'mmCP_STREAM_OUT_ADDR_HI_BASE_IDX', 'mmCP_STREAM_OUT_ADDR_LO',
'mmCP_STREAM_OUT_ADDR_LO_BASE_IDX', 'mmCP_STREAM_OUT_CONTROL',
'mmCP_STREAM_OUT_CONTROL_BASE_IDX', 'mmCP_STRMOUT_CNTL',
'mmCP_STRMOUT_CNTL_BASE_IDX', 'mmCP_ST_BASE_HI',
'mmCP_ST_BASE_HI_BASE_IDX', 'mmCP_ST_BASE_LO',
'mmCP_ST_BASE_LO_BASE_IDX', 'mmCP_ST_BUFSZ',
'mmCP_ST_BUFSZ_BASE_IDX', 'mmCP_ST_CMD_BUFSZ',
'mmCP_ST_CMD_BUFSZ_BASE_IDX', 'mmCP_SUSPEND_CNTL',
'mmCP_SUSPEND_CNTL_BASE_IDX', 'mmCP_SUSPEND_RESUME_REQ',
'mmCP_SUSPEND_RESUME_REQ_BASE_IDX', 'mmCP_VGT_CSINVOC_COUNT_HI',
'mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_CSINVOC_COUNT_LO',
'mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VGT_DSINVOC_COUNT_HI',
'mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_DSINVOC_COUNT_LO',
'mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VGT_GSINVOC_COUNT_HI',
'mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_GSINVOC_COUNT_LO',
'mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VGT_GSPRIM_COUNT_HI',
'mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX', 'mmCP_VGT_GSPRIM_COUNT_LO',
'mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX', 'mmCP_VGT_HSINVOC_COUNT_HI',
'mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_HSINVOC_COUNT_LO',
'mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VGT_IAPRIM_COUNT_HI',
'mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX', 'mmCP_VGT_IAPRIM_COUNT_LO',
'mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX', 'mmCP_VGT_IAVERT_COUNT_HI',
'mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX', 'mmCP_VGT_IAVERT_COUNT_LO',
'mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX', 'mmCP_VGT_VSINVOC_COUNT_HI',
'mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_VSINVOC_COUNT_LO',
'mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VIRT_STATUS',
'mmCP_VIRT_STATUS_BASE_IDX', 'mmCP_VMID', 'mmCP_VMID_BASE_IDX',
'mmCP_VMID_PREEMPT', 'mmCP_VMID_PREEMPT_BASE_IDX',
'mmCP_VMID_RESET', 'mmCP_VMID_RESET_BASE_IDX', 'mmCP_VMID_STATUS',
'mmCP_VMID_STATUS_BASE_IDX', 'mmCP_WAIT_REG_MEM_TIMEOUT',
'mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX', 'mmCP_WAIT_SEM_ADDR_HI',
'mmCP_WAIT_SEM_ADDR_HI_BASE_IDX', 'mmCP_WAIT_SEM_ADDR_LO',
'mmCP_WAIT_SEM_ADDR_LO_BASE_IDX', 'mmCS_COPY_STATE',
'mmCS_COPY_STATE_BASE_IDX', 'mmDB_ALPHA_TO_MASK',
'mmDB_ALPHA_TO_MASK_BASE_IDX', 'mmDB_CGTT_CLK_CTRL_0',
'mmDB_CGTT_CLK_CTRL_0_BASE_IDX', 'mmDB_COUNT_CONTROL',
'mmDB_COUNT_CONTROL_BASE_IDX', 'mmDB_CREDIT_LIMIT',
'mmDB_CREDIT_LIMIT_BASE_IDX', 'mmDB_DEBUG', 'mmDB_DEBUG2',
'mmDB_DEBUG2_BASE_IDX', 'mmDB_DEBUG3', 'mmDB_DEBUG3_BASE_IDX',
'mmDB_DEBUG4', 'mmDB_DEBUG4_BASE_IDX', 'mmDB_DEBUG5',
'mmDB_DEBUG5_BASE_IDX', 'mmDB_DEBUG_BASE_IDX',
'mmDB_DEPTH_BOUNDS_MAX', 'mmDB_DEPTH_BOUNDS_MAX_BASE_IDX',
'mmDB_DEPTH_BOUNDS_MIN', 'mmDB_DEPTH_BOUNDS_MIN_BASE_IDX',
'mmDB_DEPTH_CLEAR', 'mmDB_DEPTH_CLEAR_BASE_IDX',
'mmDB_DEPTH_CONTROL', 'mmDB_DEPTH_CONTROL_BASE_IDX',
'mmDB_DEPTH_SIZE_XY', 'mmDB_DEPTH_SIZE_XY_BASE_IDX',
'mmDB_DEPTH_VIEW', 'mmDB_DEPTH_VIEW_BASE_IDX', 'mmDB_DFSM_CONFIG',
'mmDB_DFSM_CONFIG_BASE_IDX', 'mmDB_DFSM_CONTROL',
'mmDB_DFSM_CONTROL_BASE_IDX', 'mmDB_DFSM_FLUSH_AUX_EVENT',
'mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX', 'mmDB_DFSM_FLUSH_ENABLE',
'mmDB_DFSM_FLUSH_ENABLE_BASE_IDX', 'mmDB_DFSM_PRIMS_IN_FLIGHT',
'mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX', 'mmDB_DFSM_TILES_IN_FLIGHT',
'mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX', 'mmDB_DFSM_WATCHDOG',
'mmDB_DFSM_WATCHDOG_BASE_IDX', 'mmDB_EQAA', 'mmDB_EQAA_BASE_IDX',
'mmDB_EQUAD_STUTTER_CONTROL',
'mmDB_EQUAD_STUTTER_CONTROL_BASE_IDX',
'mmDB_ETILE_STUTTER_CONTROL',
'mmDB_ETILE_STUTTER_CONTROL_BASE_IDX', 'mmDB_EXCEPTION_CONTROL',
'mmDB_EXCEPTION_CONTROL_BASE_IDX',
'mmDB_FGCG_INTERFACES_CLK_CTRL',
'mmDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX',
'mmDB_FGCG_SRAMS_CLK_CTRL', 'mmDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX',
'mmDB_FIFO_DEPTH1', 'mmDB_FIFO_DEPTH1_BASE_IDX',
'mmDB_FIFO_DEPTH2', 'mmDB_FIFO_DEPTH2_BASE_IDX',
'mmDB_FIFO_DEPTH3', 'mmDB_FIFO_DEPTH3_BASE_IDX',
'mmDB_FREE_CACHELINES', 'mmDB_FREE_CACHELINES_BASE_IDX',
'mmDB_HTILE_DATA_BASE', 'mmDB_HTILE_DATA_BASE_BASE_IDX',
'mmDB_HTILE_DATA_BASE_HI', 'mmDB_HTILE_DATA_BASE_HI_BASE_IDX',
'mmDB_HTILE_SURFACE', 'mmDB_HTILE_SURFACE_BASE_IDX',
'mmDB_LAST_OF_BURST_CONFIG', 'mmDB_LAST_OF_BURST_CONFIG_BASE_IDX',
'mmDB_LQUAD_STUTTER_CONTROL',
'mmDB_LQUAD_STUTTER_CONTROL_BASE_IDX',
'mmDB_LTILE_STUTTER_CONTROL',
'mmDB_LTILE_STUTTER_CONTROL_BASE_IDX', 'mmDB_MEM_ARB_WATERMARKS',
'mmDB_MEM_ARB_WATERMARKS_BASE_IDX', 'mmDB_OCCLUSION_COUNT0_HI',
'mmDB_OCCLUSION_COUNT0_HI_BASE_IDX', 'mmDB_OCCLUSION_COUNT0_LOW',
'mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX', 'mmDB_OCCLUSION_COUNT1_HI',
'mmDB_OCCLUSION_COUNT1_HI_BASE_IDX', 'mmDB_OCCLUSION_COUNT1_LOW',
'mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX', 'mmDB_OCCLUSION_COUNT2_HI',
'mmDB_OCCLUSION_COUNT2_HI_BASE_IDX', 'mmDB_OCCLUSION_COUNT2_LOW',
'mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX', 'mmDB_OCCLUSION_COUNT3_HI',
'mmDB_OCCLUSION_COUNT3_HI_BASE_IDX', 'mmDB_OCCLUSION_COUNT3_LOW',
'mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX', 'mmDB_PERFCOUNTER0_HI',
'mmDB_PERFCOUNTER0_HI_BASE_IDX', 'mmDB_PERFCOUNTER0_LO',
'mmDB_PERFCOUNTER0_LO_BASE_IDX', 'mmDB_PERFCOUNTER0_SELECT',
'mmDB_PERFCOUNTER0_SELECT1', 'mmDB_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmDB_PERFCOUNTER0_SELECT_BASE_IDX', 'mmDB_PERFCOUNTER1_HI',
'mmDB_PERFCOUNTER1_HI_BASE_IDX', 'mmDB_PERFCOUNTER1_LO',
'mmDB_PERFCOUNTER1_LO_BASE_IDX', 'mmDB_PERFCOUNTER1_SELECT',
'mmDB_PERFCOUNTER1_SELECT1', 'mmDB_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmDB_PERFCOUNTER1_SELECT_BASE_IDX', 'mmDB_PERFCOUNTER2_HI',
'mmDB_PERFCOUNTER2_HI_BASE_IDX', 'mmDB_PERFCOUNTER2_LO',
'mmDB_PERFCOUNTER2_LO_BASE_IDX', 'mmDB_PERFCOUNTER2_SELECT',
'mmDB_PERFCOUNTER2_SELECT_BASE_IDX', 'mmDB_PERFCOUNTER3_HI',
'mmDB_PERFCOUNTER3_HI_BASE_IDX', 'mmDB_PERFCOUNTER3_LO',
'mmDB_PERFCOUNTER3_LO_BASE_IDX', 'mmDB_PERFCOUNTER3_SELECT',
'mmDB_PERFCOUNTER3_SELECT_BASE_IDX', 'mmDB_PRELOAD_CONTROL',
'mmDB_PRELOAD_CONTROL_BASE_IDX', 'mmDB_RENDER_CONTROL',
'mmDB_RENDER_CONTROL_BASE_IDX', 'mmDB_RENDER_OVERRIDE',
'mmDB_RENDER_OVERRIDE2', 'mmDB_RENDER_OVERRIDE2_BASE_IDX',
'mmDB_RENDER_OVERRIDE_BASE_IDX', 'mmDB_RESERVED_REG_1',
'mmDB_RESERVED_REG_1_BASE_IDX', 'mmDB_RESERVED_REG_2',
'mmDB_RESERVED_REG_2_BASE_IDX', 'mmDB_RESERVED_REG_3',
'mmDB_RESERVED_REG_3_BASE_IDX', 'mmDB_RING_CONTROL',
'mmDB_RING_CONTROL_BASE_IDX', 'mmDB_RMI_BC_GL2_CACHE_CONTROL',
'mmDB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX',
'mmDB_RMI_L2_CACHE_CONTROL', 'mmDB_RMI_L2_CACHE_CONTROL_BASE_IDX',
'mmDB_SHADER_CONTROL', 'mmDB_SHADER_CONTROL_BASE_IDX',
'mmDB_SRESULTS_COMPARE_STATE0',
'mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX',
'mmDB_SRESULTS_COMPARE_STATE1',
'mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX', 'mmDB_STENCILREFMASK',
'mmDB_STENCILREFMASK_BASE_IDX', 'mmDB_STENCILREFMASK_BF',
'mmDB_STENCILREFMASK_BF_BASE_IDX', 'mmDB_STENCIL_CLEAR',
'mmDB_STENCIL_CLEAR_BASE_IDX', 'mmDB_STENCIL_CONTROL',
'mmDB_STENCIL_CONTROL_BASE_IDX', 'mmDB_STENCIL_INFO',
'mmDB_STENCIL_INFO_BASE_IDX', 'mmDB_STENCIL_READ_BASE',
'mmDB_STENCIL_READ_BASE_BASE_IDX', 'mmDB_STENCIL_READ_BASE_HI',
'mmDB_STENCIL_READ_BASE_HI_BASE_IDX', 'mmDB_STENCIL_WRITE_BASE',
'mmDB_STENCIL_WRITE_BASE_BASE_IDX', 'mmDB_STENCIL_WRITE_BASE_HI',
'mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX', 'mmDB_SUBTILE_CONTROL',
'mmDB_SUBTILE_CONTROL_BASE_IDX', 'mmDB_VRS_OVERRIDE_CNTL',
'mmDB_VRS_OVERRIDE_CNTL_BASE_IDX', 'mmDB_WATERMARKS',
'mmDB_WATERMARKS_BASE_IDX', 'mmDB_ZPASS_COUNT_HI',
'mmDB_ZPASS_COUNT_HI_BASE_IDX', 'mmDB_ZPASS_COUNT_LOW',
'mmDB_ZPASS_COUNT_LOW_BASE_IDX', 'mmDB_Z_INFO',
'mmDB_Z_INFO_BASE_IDX', 'mmDB_Z_READ_BASE',
'mmDB_Z_READ_BASE_BASE_IDX', 'mmDB_Z_READ_BASE_HI',
'mmDB_Z_READ_BASE_HI_BASE_IDX', 'mmDB_Z_WRITE_BASE',
'mmDB_Z_WRITE_BASE_BASE_IDX', 'mmDB_Z_WRITE_BASE_HI',
'mmDB_Z_WRITE_BASE_HI_BASE_IDX', 'mmDIDT_INDEX_AUTO_INCR_EN',
'mmDIDT_INDEX_AUTO_INCR_EN_BASE_IDX', 'mmDIDT_IND_DATA',
'mmDIDT_IND_DATA_BASE_IDX', 'mmDIDT_IND_INDEX',
'mmDIDT_IND_INDEX_BASE_IDX', 'mmEDC_HYSTERESIS_CNTL',
'mmEDC_HYSTERESIS_CNTL_BASE_IDX', 'mmEDC_HYSTERESIS_STAT',
'mmEDC_HYSTERESIS_STAT_BASE_IDX', 'mmEDC_PERF_COUNTER',
'mmEDC_PERF_COUNTER_BASE_IDX', 'mmGB_ADDR_CONFIG',
'mmGB_ADDR_CONFIG_BASE_IDX', 'mmGB_ADDR_CONFIG_READ',
'mmGB_ADDR_CONFIG_READ_BASE_IDX', 'mmGB_BACKEND_MAP',
'mmGB_BACKEND_MAP_BASE_IDX', 'mmGB_EDC_MODE',
'mmGB_EDC_MODE_BASE_IDX', 'mmGB_GPU_ID', 'mmGB_GPU_ID_BASE_IDX',
'mmGCEA_CGTT_CLK_CTRL', 'mmGCEA_CGTT_CLK_CTRL_BASE_IDX',
'mmGCEA_DRAM_PAGE_BURST', 'mmGCEA_DRAM_PAGE_BURST_BASE_IDX',
'mmGCEA_DRAM_RD_CAM_CNTL', 'mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX',
'mmGCEA_DRAM_RD_CLI2GRP_MAP0',
'mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX',
'mmGCEA_DRAM_RD_CLI2GRP_MAP1',
'mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX',
'mmGCEA_DRAM_RD_GRP2VC_MAP', 'mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX',
'mmGCEA_DRAM_RD_LAZY', 'mmGCEA_DRAM_RD_LAZY_BASE_IDX',
'mmGCEA_DRAM_RD_PRI_AGE', 'mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX',
'mmGCEA_DRAM_RD_PRI_FIXED', 'mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX',
'mmGCEA_DRAM_RD_PRI_QUANT_PRI1',
'mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX',
'mmGCEA_DRAM_RD_PRI_QUANT_PRI2',
'mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX',
'mmGCEA_DRAM_RD_PRI_QUANT_PRI3',
'mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX',
'mmGCEA_DRAM_RD_PRI_QUEUING',
'mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX',
'mmGCEA_DRAM_RD_PRI_URGENCY',
'mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX', 'mmGCEA_DRAM_WR_CAM_CNTL',
'mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX', 'mmGCEA_DRAM_WR_CLI2GRP_MAP0',
'mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX',
'mmGCEA_DRAM_WR_CLI2GRP_MAP1',
'mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX',
'mmGCEA_DRAM_WR_GRP2VC_MAP', 'mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX',
'mmGCEA_DRAM_WR_LAZY', 'mmGCEA_DRAM_WR_LAZY_BASE_IDX',
'mmGCEA_DRAM_WR_PRI_AGE', 'mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX',
'mmGCEA_DRAM_WR_PRI_FIXED', 'mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX',
'mmGCEA_DRAM_WR_PRI_QUANT_PRI1',
'mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX',
'mmGCEA_DRAM_WR_PRI_QUANT_PRI2',
'mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX',
'mmGCEA_DRAM_WR_PRI_QUANT_PRI3',
'mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX',
'mmGCEA_DRAM_WR_PRI_QUEUING',
'mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX',
'mmGCEA_DRAM_WR_PRI_URGENCY',
'mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX', 'mmGCEA_DSM_CNTL',
'mmGCEA_DSM_CNTL2', 'mmGCEA_DSM_CNTL2A',
'mmGCEA_DSM_CNTL2A_BASE_IDX', 'mmGCEA_DSM_CNTL2B',
'mmGCEA_DSM_CNTL2B_BASE_IDX', 'mmGCEA_DSM_CNTL2_BASE_IDX',
'mmGCEA_DSM_CNTLA', 'mmGCEA_DSM_CNTLA_BASE_IDX',
'mmGCEA_DSM_CNTLB', 'mmGCEA_DSM_CNTLB_BASE_IDX',
'mmGCEA_DSM_CNTL_BASE_IDX', 'mmGCEA_ERR_STATUS',
'mmGCEA_ERR_STATUS_BASE_IDX', 'mmGCEA_GL2C_XBR_CREDITS',
'mmGCEA_GL2C_XBR_CREDITS_BASE_IDX', 'mmGCEA_GL2C_XBR_MAXBURST',
'mmGCEA_GL2C_XBR_MAXBURST_BASE_IDX', 'mmGCEA_IO_GROUP_BURST',
'mmGCEA_IO_GROUP_BURST_BASE_IDX', 'mmGCEA_IO_RD_CLI2GRP_MAP0',
'mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX', 'mmGCEA_IO_RD_CLI2GRP_MAP1',
'mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX',
'mmGCEA_IO_RD_COMBINE_FLUSH',
'mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX', 'mmGCEA_IO_RD_PRI_AGE',
'mmGCEA_IO_RD_PRI_AGE_BASE_IDX', 'mmGCEA_IO_RD_PRI_FIXED',
'mmGCEA_IO_RD_PRI_FIXED_BASE_IDX', 'mmGCEA_IO_RD_PRI_QUANT_PRI1',
'mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX',
'mmGCEA_IO_RD_PRI_QUANT_PRI2',
'mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX',
'mmGCEA_IO_RD_PRI_QUANT_PRI3',
'mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX',
'mmGCEA_IO_RD_PRI_QUEUING', 'mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX',
'mmGCEA_IO_RD_PRI_URGENCY', 'mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX',
'mmGCEA_IO_RD_PRI_URGENCY_MASKING',
'mmGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX',
'mmGCEA_IO_WR_CLI2GRP_MAP0', 'mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX',
'mmGCEA_IO_WR_CLI2GRP_MAP1', 'mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX',
'mmGCEA_IO_WR_COMBINE_FLUSH',
'mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX', 'mmGCEA_IO_WR_PRI_AGE',
'mmGCEA_IO_WR_PRI_AGE_BASE_IDX', 'mmGCEA_IO_WR_PRI_FIXED',
'mmGCEA_IO_WR_PRI_FIXED_BASE_IDX', 'mmGCEA_IO_WR_PRI_QUANT_PRI1',
'mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX',
'mmGCEA_IO_WR_PRI_QUANT_PRI2',
'mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX',
'mmGCEA_IO_WR_PRI_QUANT_PRI3',
'mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX',
'mmGCEA_IO_WR_PRI_QUEUING', 'mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX',
'mmGCEA_IO_WR_PRI_URGENCY', 'mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX',
'mmGCEA_IO_WR_PRI_URGENCY_MASKING',
'mmGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX',
'mmGCEA_LATENCY_SAMPLING', 'mmGCEA_LATENCY_SAMPLING_BASE_IDX',
'mmGCEA_MISC', 'mmGCEA_MISC2', 'mmGCEA_MISC2_BASE_IDX',
'mmGCEA_MISC_BASE_IDX', 'mmGCEA_PERFCOUNTER0_CFG',
'mmGCEA_PERFCOUNTER0_CFG_BASE_IDX', 'mmGCEA_PERFCOUNTER1_CFG',
'mmGCEA_PERFCOUNTER1_CFG_BASE_IDX', 'mmGCEA_PERFCOUNTER2_HI',
'mmGCEA_PERFCOUNTER2_HI_BASE_IDX', 'mmGCEA_PERFCOUNTER2_LO',
'mmGCEA_PERFCOUNTER2_LO_BASE_IDX', 'mmGCEA_PERFCOUNTER2_MODE',
'mmGCEA_PERFCOUNTER2_MODE_BASE_IDX', 'mmGCEA_PERFCOUNTER2_SELECT',
'mmGCEA_PERFCOUNTER2_SELECT1',
'mmGCEA_PERFCOUNTER2_SELECT1_BASE_IDX',
'mmGCEA_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGCEA_PERFCOUNTER_HI',
'mmGCEA_PERFCOUNTER_HI_BASE_IDX', 'mmGCEA_PERFCOUNTER_LO',
'mmGCEA_PERFCOUNTER_LO_BASE_IDX', 'mmGCEA_PERFCOUNTER_RSLT_CNTL',
'mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'mmGCEA_PROBE_CNTL',
'mmGCEA_PROBE_CNTL_BASE_IDX', 'mmGCEA_PROBE_MAP',
'mmGCEA_PROBE_MAP_BASE_IDX', 'mmGCEA_RRET_MEM_RESERVE',
'mmGCEA_RRET_MEM_RESERVE_BASE_IDX', 'mmGCMC_MEM_POWER_LS',
'mmGCMC_MEM_POWER_LS_BASE_IDX', 'mmGCMC_SHARED_ACTIVE_FCN_ID',
'mmGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX',
'mmGCMC_SHARED_VIRT_RESET_REQ', 'mmGCMC_SHARED_VIRT_RESET_REQ2',
'mmGCMC_SHARED_VIRT_RESET_REQ2_BASE_IDX',
'mmGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX', 'mmGCMC_VM_AGP_BASE',
'mmGCMC_VM_AGP_BASE_BASE_IDX', 'mmGCMC_VM_AGP_BOT',
'mmGCMC_VM_AGP_BOT_BASE_IDX', 'mmGCMC_VM_AGP_TOP',
'mmGCMC_VM_AGP_TOP_BASE_IDX', 'mmGCMC_VM_APT_CNTL',
'mmGCMC_VM_APT_CNTL_BASE_IDX',
'mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END',
'mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX',
'mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START',
'mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX',
'mmGCMC_VM_FB_LOCATION_BASE',
'mmGCMC_VM_FB_LOCATION_BASE_BASE_IDX',
'mmGCMC_VM_FB_LOCATION_TOP', 'mmGCMC_VM_FB_LOCATION_TOP_BASE_IDX',
'mmGCMC_VM_FB_NOALLOC_CNTL', 'mmGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX',
'mmGCMC_VM_FB_OFFSET', 'mmGCMC_VM_FB_OFFSET_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF0',
'mmGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF1', 'mmGCMC_VM_FB_SIZE_OFFSET_VF10',
'mmGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF11',
'mmGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF12',
'mmGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF13',
'mmGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF14',
'mmGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF15',
'mmGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF16',
'mmGCMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF17',
'mmGCMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF18',
'mmGCMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF19',
'mmGCMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF2', 'mmGCMC_VM_FB_SIZE_OFFSET_VF20',
'mmGCMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF21',
'mmGCMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF22',
'mmGCMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF23',
'mmGCMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF24',
'mmGCMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF25',
'mmGCMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF26',
'mmGCMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF27',
'mmGCMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF28',
'mmGCMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF29',
'mmGCMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF3', 'mmGCMC_VM_FB_SIZE_OFFSET_VF30',
'mmGCMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF31',
'mmGCMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF4',
'mmGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF5',
'mmGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF6',
'mmGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF7',
'mmGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF8',
'mmGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX',
'mmGCMC_VM_FB_SIZE_OFFSET_VF9',
'mmGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX',
'mmGCMC_VM_L2_PERFCOUNTER0_CFG',
'mmGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX',
'mmGCMC_VM_L2_PERFCOUNTER1_CFG',
'mmGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX',
'mmGCMC_VM_L2_PERFCOUNTER2_CFG',
'mmGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX',
'mmGCMC_VM_L2_PERFCOUNTER3_CFG',
'mmGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX',
'mmGCMC_VM_L2_PERFCOUNTER4_CFG',
'mmGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX',
'mmGCMC_VM_L2_PERFCOUNTER5_CFG',
'mmGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX',
'mmGCMC_VM_L2_PERFCOUNTER6_CFG',
'mmGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX',
'mmGCMC_VM_L2_PERFCOUNTER7_CFG',
'mmGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX',
'mmGCMC_VM_L2_PERFCOUNTER_HI',
'mmGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX',
'mmGCMC_VM_L2_PERFCOUNTER_LO',
'mmGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX',
'mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL',
'mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
'mmGCMC_VM_LOCAL_HBM_ADDRESS_END',
'mmGCMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX',
'mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL',
'mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX',
'mmGCMC_VM_LOCAL_HBM_ADDRESS_START',
'mmGCMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX',
'mmGCMC_VM_MARC_BASE_HI_0', 'mmGCMC_VM_MARC_BASE_HI_0_BASE_IDX',
'mmGCMC_VM_MARC_BASE_HI_1', 'mmGCMC_VM_MARC_BASE_HI_1_BASE_IDX',
'mmGCMC_VM_MARC_BASE_HI_2', 'mmGCMC_VM_MARC_BASE_HI_2_BASE_IDX',
'mmGCMC_VM_MARC_BASE_HI_3', 'mmGCMC_VM_MARC_BASE_HI_3_BASE_IDX',
'mmGCMC_VM_MARC_BASE_LO_0', 'mmGCMC_VM_MARC_BASE_LO_0_BASE_IDX',
'mmGCMC_VM_MARC_BASE_LO_1', 'mmGCMC_VM_MARC_BASE_LO_1_BASE_IDX',
'mmGCMC_VM_MARC_BASE_LO_2', 'mmGCMC_VM_MARC_BASE_LO_2_BASE_IDX',
'mmGCMC_VM_MARC_BASE_LO_3', 'mmGCMC_VM_MARC_BASE_LO_3_BASE_IDX',
'mmGCMC_VM_MARC_LEN_HI_0', 'mmGCMC_VM_MARC_LEN_HI_0_BASE_IDX',
'mmGCMC_VM_MARC_LEN_HI_1', 'mmGCMC_VM_MARC_LEN_HI_1_BASE_IDX',
'mmGCMC_VM_MARC_LEN_HI_2', 'mmGCMC_VM_MARC_LEN_HI_2_BASE_IDX',
'mmGCMC_VM_MARC_LEN_HI_3', 'mmGCMC_VM_MARC_LEN_HI_3_BASE_IDX',
'mmGCMC_VM_MARC_LEN_LO_0', 'mmGCMC_VM_MARC_LEN_LO_0_BASE_IDX',
'mmGCMC_VM_MARC_LEN_LO_1', 'mmGCMC_VM_MARC_LEN_LO_1_BASE_IDX',
'mmGCMC_VM_MARC_LEN_LO_2', 'mmGCMC_VM_MARC_LEN_LO_2_BASE_IDX',
'mmGCMC_VM_MARC_LEN_LO_3', 'mmGCMC_VM_MARC_LEN_LO_3_BASE_IDX',
'mmGCMC_VM_MARC_RELOC_HI_0', 'mmGCMC_VM_MARC_RELOC_HI_0_BASE_IDX',
'mmGCMC_VM_MARC_RELOC_HI_1', 'mmGCMC_VM_MARC_RELOC_HI_1_BASE_IDX',
'mmGCMC_VM_MARC_RELOC_HI_2', 'mmGCMC_VM_MARC_RELOC_HI_2_BASE_IDX',
'mmGCMC_VM_MARC_RELOC_HI_3', 'mmGCMC_VM_MARC_RELOC_HI_3_BASE_IDX',
'mmGCMC_VM_MARC_RELOC_LO_0', 'mmGCMC_VM_MARC_RELOC_LO_0_BASE_IDX',
'mmGCMC_VM_MARC_RELOC_LO_1', 'mmGCMC_VM_MARC_RELOC_LO_1_BASE_IDX',
'mmGCMC_VM_MARC_RELOC_LO_2', 'mmGCMC_VM_MARC_RELOC_LO_2_BASE_IDX',
'mmGCMC_VM_MARC_RELOC_LO_3', 'mmGCMC_VM_MARC_RELOC_LO_3_BASE_IDX',
'mmGCMC_VM_MX_L1_TLB_CNTL', 'mmGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX',
'mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2',
'mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX',
'mmGCMC_VM_NB_MMIOBASE', 'mmGCMC_VM_NB_MMIOBASE_BASE_IDX',
'mmGCMC_VM_NB_MMIOLIMIT', 'mmGCMC_VM_NB_MMIOLIMIT_BASE_IDX',
'mmGCMC_VM_NB_PCI_ARB', 'mmGCMC_VM_NB_PCI_ARB_BASE_IDX',
'mmGCMC_VM_NB_PCI_CTRL', 'mmGCMC_VM_NB_PCI_CTRL_BASE_IDX',
'mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1',
'mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX',
'mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2',
'mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX', 'mmGCMC_VM_STEERING',
'mmGCMC_VM_STEERING_BASE_IDX',
'mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB',
'mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX',
'mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB',
'mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX',
'mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR',
'mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX',
'mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR',
'mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX',
'mmGCMC_VM_XGMI_GPUIOV_ENABLE',
'mmGCMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX',
'mmGCMC_VM_XGMI_LFB_CNTL', 'mmGCMC_VM_XGMI_LFB_CNTL_BASE_IDX',
'mmGCMC_VM_XGMI_LFB_SIZE', 'mmGCMC_VM_XGMI_LFB_SIZE_BASE_IDX',
'mmGCRD_SA_TARGETS_DISABLE', 'mmGCRD_SA_TARGETS_DISABLE_BASE_IDX',
'mmGCR_CGTT_SCLK_CTRL', 'mmGCR_CGTT_SCLK_CTRL_BASE_IDX',
'mmGCR_CMD_STATUS', 'mmGCR_CMD_STATUS_BASE_IDX',
'mmGCR_GENERAL_CNTL', 'mmGCR_GENERAL_CNTL_BASE_IDX',
'mmGCR_PERFCOUNTER0_HI', 'mmGCR_PERFCOUNTER0_HI_BASE_IDX',
'mmGCR_PERFCOUNTER0_LO', 'mmGCR_PERFCOUNTER0_LO_BASE_IDX',
'mmGCR_PERFCOUNTER0_SELECT', 'mmGCR_PERFCOUNTER0_SELECT1',
'mmGCR_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmGCR_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGCR_PERFCOUNTER1_HI',
'mmGCR_PERFCOUNTER1_HI_BASE_IDX', 'mmGCR_PERFCOUNTER1_LO',
'mmGCR_PERFCOUNTER1_LO_BASE_IDX', 'mmGCR_PERFCOUNTER1_SELECT',
'mmGCR_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGCR_PIO_CNTL',
'mmGCR_PIO_CNTL_BASE_IDX', 'mmGCR_PIO_DATA',
'mmGCR_PIO_DATA_BASE_IDX', 'mmGCR_SPARE', 'mmGCR_SPARE_BASE_IDX',
'mmGCUTCL2_HARVEST_BYPASS_GROUPS',
'mmGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX',
'mmGCUTCL2_PERFCOUNTER0_CFG',
'mmGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX',
'mmGCUTCL2_PERFCOUNTER1_CFG',
'mmGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX',
'mmGCUTCL2_PERFCOUNTER2_CFG',
'mmGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX',
'mmGCUTCL2_PERFCOUNTER3_CFG',
'mmGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX', 'mmGCUTCL2_PERFCOUNTER_HI',
'mmGCUTCL2_PERFCOUNTER_HI_BASE_IDX', 'mmGCUTCL2_PERFCOUNTER_LO',
'mmGCUTCL2_PERFCOUNTER_LO_BASE_IDX',
'mmGCUTCL2_PERFCOUNTER_RSLT_CNTL',
'mmGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
'mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID',
'mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX',
'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI',
'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX',
'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO',
'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX',
'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI',
'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX',
'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO',
'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX',
'mmGCVML2_PERFCOUNTER2_0_HI',
'mmGCVML2_PERFCOUNTER2_0_HI_BASE_IDX',
'mmGCVML2_PERFCOUNTER2_0_LO',
'mmGCVML2_PERFCOUNTER2_0_LO_BASE_IDX',
'mmGCVML2_PERFCOUNTER2_0_MODE',
'mmGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX',
'mmGCVML2_PERFCOUNTER2_0_SELECT',
'mmGCVML2_PERFCOUNTER2_0_SELECT1',
'mmGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX',
'mmGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX',
'mmGCVML2_PERFCOUNTER2_1_HI',
'mmGCVML2_PERFCOUNTER2_1_HI_BASE_IDX',
'mmGCVML2_PERFCOUNTER2_1_LO',
'mmGCVML2_PERFCOUNTER2_1_LO_BASE_IDX',
'mmGCVML2_PERFCOUNTER2_1_MODE',
'mmGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX',
'mmGCVML2_PERFCOUNTER2_1_SELECT',
'mmGCVML2_PERFCOUNTER2_1_SELECT1',
'mmGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX',
'mmGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX',
'mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT',
'mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX',
'mmGCVML2_WALKER_MACRO_THROTTLE_TIME',
'mmGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX',
'mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT',
'mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX',
'mmGCVML2_WALKER_MICRO_THROTTLE_TIME',
'mmGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX',
'mmGCVM_CONTEXT0_CNTL', 'mmGCVM_CONTEXT0_CNTL_BASE_IDX',
'mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT10_CNTL', 'mmGCVM_CONTEXT10_CNTL_BASE_IDX',
'mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT11_CNTL', 'mmGCVM_CONTEXT11_CNTL_BASE_IDX',
'mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT12_CNTL', 'mmGCVM_CONTEXT12_CNTL_BASE_IDX',
'mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT13_CNTL', 'mmGCVM_CONTEXT13_CNTL_BASE_IDX',
'mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT14_CNTL', 'mmGCVM_CONTEXT14_CNTL_BASE_IDX',
'mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT15_CNTL', 'mmGCVM_CONTEXT15_CNTL_BASE_IDX',
'mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT1_CNTL', 'mmGCVM_CONTEXT1_CNTL_BASE_IDX',
'mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT2_CNTL', 'mmGCVM_CONTEXT2_CNTL_BASE_IDX',
'mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT3_CNTL', 'mmGCVM_CONTEXT3_CNTL_BASE_IDX',
'mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT4_CNTL', 'mmGCVM_CONTEXT4_CNTL_BASE_IDX',
'mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT5_CNTL', 'mmGCVM_CONTEXT5_CNTL_BASE_IDX',
'mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT6_CNTL', 'mmGCVM_CONTEXT6_CNTL_BASE_IDX',
'mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT7_CNTL', 'mmGCVM_CONTEXT7_CNTL_BASE_IDX',
'mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT8_CNTL', 'mmGCVM_CONTEXT8_CNTL_BASE_IDX',
'mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT9_CNTL', 'mmGCVM_CONTEXT9_CNTL_BASE_IDX',
'mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32',
'mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32',
'mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32',
'mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32',
'mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32',
'mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32',
'mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'mmGCVM_CONTEXTS_DISABLE', 'mmGCVM_CONTEXTS_DISABLE_BASE_IDX',
'mmGCVM_DEBUG', 'mmGCVM_DEBUG_BASE_IDX',
'mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32',
'mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX',
'mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32',
'mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX',
'mmGCVM_DUMMY_PAGE_FAULT_CNTL',
'mmGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX', 'mmGCVM_INVALIDATE_CNTL',
'mmGCVM_INVALIDATE_CNTL_BASE_IDX', 'mmGCVM_INVALIDATE_ENG0_ACK',
'mmGCVM_INVALIDATE_ENG0_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG0_REQ',
'mmGCVM_INVALIDATE_ENG0_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG0_SEM',
'mmGCVM_INVALIDATE_ENG0_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG10_ACK',
'mmGCVM_INVALIDATE_ENG10_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG10_REQ',
'mmGCVM_INVALIDATE_ENG10_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG10_SEM',
'mmGCVM_INVALIDATE_ENG10_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG11_ACK',
'mmGCVM_INVALIDATE_ENG11_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG11_REQ',
'mmGCVM_INVALIDATE_ENG11_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG11_SEM',
'mmGCVM_INVALIDATE_ENG11_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG12_ACK',
'mmGCVM_INVALIDATE_ENG12_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG12_REQ',
'mmGCVM_INVALIDATE_ENG12_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG12_SEM',
'mmGCVM_INVALIDATE_ENG12_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG13_ACK',
'mmGCVM_INVALIDATE_ENG13_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG13_REQ',
'mmGCVM_INVALIDATE_ENG13_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG13_SEM',
'mmGCVM_INVALIDATE_ENG13_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG14_ACK',
'mmGCVM_INVALIDATE_ENG14_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG14_REQ',
'mmGCVM_INVALIDATE_ENG14_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG14_SEM',
'mmGCVM_INVALIDATE_ENG14_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG15_ACK',
'mmGCVM_INVALIDATE_ENG15_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG15_REQ',
'mmGCVM_INVALIDATE_ENG15_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG15_SEM',
'mmGCVM_INVALIDATE_ENG15_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG16_ACK',
'mmGCVM_INVALIDATE_ENG16_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG16_REQ',
'mmGCVM_INVALIDATE_ENG16_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG16_SEM',
'mmGCVM_INVALIDATE_ENG16_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG17_ACK',
'mmGCVM_INVALIDATE_ENG17_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG17_REQ',
'mmGCVM_INVALIDATE_ENG17_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG17_SEM',
'mmGCVM_INVALIDATE_ENG17_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG1_ACK',
'mmGCVM_INVALIDATE_ENG1_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG1_REQ',
'mmGCVM_INVALIDATE_ENG1_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG1_SEM',
'mmGCVM_INVALIDATE_ENG1_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG2_ACK',
'mmGCVM_INVALIDATE_ENG2_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG2_REQ',
'mmGCVM_INVALIDATE_ENG2_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG2_SEM',
'mmGCVM_INVALIDATE_ENG2_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG3_ACK',
'mmGCVM_INVALIDATE_ENG3_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG3_REQ',
'mmGCVM_INVALIDATE_ENG3_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG3_SEM',
'mmGCVM_INVALIDATE_ENG3_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG4_ACK',
'mmGCVM_INVALIDATE_ENG4_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG4_REQ',
'mmGCVM_INVALIDATE_ENG4_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG4_SEM',
'mmGCVM_INVALIDATE_ENG4_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG5_ACK',
'mmGCVM_INVALIDATE_ENG5_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG5_REQ',
'mmGCVM_INVALIDATE_ENG5_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG5_SEM',
'mmGCVM_INVALIDATE_ENG5_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG6_ACK',
'mmGCVM_INVALIDATE_ENG6_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG6_REQ',
'mmGCVM_INVALIDATE_ENG6_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG6_SEM',
'mmGCVM_INVALIDATE_ENG6_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG7_ACK',
'mmGCVM_INVALIDATE_ENG7_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG7_REQ',
'mmGCVM_INVALIDATE_ENG7_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG7_SEM',
'mmGCVM_INVALIDATE_ENG7_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG8_ACK',
'mmGCVM_INVALIDATE_ENG8_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG8_REQ',
'mmGCVM_INVALIDATE_ENG8_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG8_SEM',
'mmGCVM_INVALIDATE_ENG8_SEM_BASE_IDX',
'mmGCVM_INVALIDATE_ENG9_ACK',
'mmGCVM_INVALIDATE_ENG9_ACK_BASE_IDX',
'mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32',
'mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32',
'mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX',
'mmGCVM_INVALIDATE_ENG9_REQ',
'mmGCVM_INVALIDATE_ENG9_REQ_BASE_IDX',
'mmGCVM_INVALIDATE_ENG9_SEM',
'mmGCVM_INVALIDATE_ENG9_SEM_BASE_IDX',
'mmGCVM_IOMMU_CONTROL_REGISTER',
'mmGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX',
'mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE',
'mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX',
'mmGCVM_IOMMU_MMIO_CNTRL_1', 'mmGCVM_IOMMU_MMIO_CNTRL_1_BASE_IDX',
'mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER',
'mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX',
'mmGCVM_L2_BANK_SELECT_RESERVED_CID',
'mmGCVM_L2_BANK_SELECT_RESERVED_CID2',
'mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX',
'mmGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX',
'mmGCVM_L2_CACHE_PARITY_CNTL',
'mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX', 'mmGCVM_L2_CNTL',
'mmGCVM_L2_CNTL2', 'mmGCVM_L2_CNTL2_BASE_IDX', 'mmGCVM_L2_CNTL3',
'mmGCVM_L2_CNTL3_BASE_IDX', 'mmGCVM_L2_CNTL4',
'mmGCVM_L2_CNTL4_BASE_IDX', 'mmGCVM_L2_CNTL5',
'mmGCVM_L2_CNTL5_BASE_IDX', 'mmGCVM_L2_CNTL_BASE_IDX',
'mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32',
'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX',
'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32',
'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX',
'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32',
'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX',
'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32',
'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX',
'mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32',
'mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX',
'mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32',
'mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX',
'mmGCVM_L2_GCR_CNTL', 'mmGCVM_L2_GCR_CNTL_BASE_IDX',
'mmGCVM_L2_ID_CTRL0', 'mmGCVM_L2_ID_CTRL0_BASE_IDX',
'mmGCVM_L2_ID_CTRL1', 'mmGCVM_L2_ID_CTRL1_BASE_IDX',
'mmGCVM_L2_ID_CTRL2', 'mmGCVM_L2_ID_CTRL2_BASE_IDX',
'mmGCVM_L2_ID_CTRL3', 'mmGCVM_L2_ID_CTRL3_BASE_IDX',
'mmGCVM_L2_ID_CTRL4', 'mmGCVM_L2_ID_CTRL4_BASE_IDX',
'mmGCVM_L2_ID_CTRL5', 'mmGCVM_L2_ID_CTRL5_BASE_IDX',
'mmGCVM_L2_ID_CTRL6', 'mmGCVM_L2_ID_CTRL6_BASE_IDX',
'mmGCVM_L2_ID_CTRL7', 'mmGCVM_L2_ID_CTRL7_BASE_IDX',
'mmGCVM_L2_ID_CTRL_HI', 'mmGCVM_L2_ID_CTRL_HI_BASE_IDX',
'mmGCVM_L2_ID_STATUS', 'mmGCVM_L2_ID_STATUS_BASE_IDX',
'mmGCVM_L2_IH_LOG_CNTL', 'mmGCVM_L2_IH_LOG_CNTL_BASE_IDX',
'mmGCVM_L2_MM_GROUP_RT_CLASSES',
'mmGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX',
'mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32',
'mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX',
'mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32',
'mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX',
'mmGCVM_L2_PROTECTION_FAULT_CNTL',
'mmGCVM_L2_PROTECTION_FAULT_CNTL2',
'mmGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX',
'mmGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX',
'mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32',
'mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX',
'mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32',
'mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX',
'mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3',
'mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX',
'mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4',
'mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX',
'mmGCVM_L2_PROTECTION_FAULT_STATUS',
'mmGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX',
'mmGCVM_L2_PTE_CACHE_DUMP_CNTL',
'mmGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX',
'mmGCVM_L2_PTE_CACHE_DUMP_READ',
'mmGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX', 'mmGCVM_L2_STATUS',
'mmGCVM_L2_STATUS_BASE_IDX', 'mmGC_CAC_AGGR_LOWER',
'mmGC_CAC_AGGR_LOWER_BASE_IDX', 'mmGC_CAC_AGGR_UPPER',
'mmGC_CAC_AGGR_UPPER_BASE_IDX', 'mmGC_CAC_CGTT_CLK_CTRL',
'mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX', 'mmGC_CAC_CTRL_1',
'mmGC_CAC_CTRL_1_BASE_IDX', 'mmGC_CAC_CTRL_2',
'mmGC_CAC_CTRL_2_BASE_IDX', 'mmGC_CAC_IND_DATA',
'mmGC_CAC_IND_DATA_BASE_IDX', 'mmGC_CAC_IND_INDEX',
'mmGC_CAC_IND_INDEX_BASE_IDX', 'mmGC_CAC_SOFT_CTRL',
'mmGC_CAC_SOFT_CTRL_BASE_IDX', 'mmGC_EDC_CTRL',
'mmGC_EDC_CTRL_BASE_IDX', 'mmGC_EDC_OVERFLOW',
'mmGC_EDC_OVERFLOW_BASE_IDX', 'mmGC_EDC_ROLLING_POWER_DELTA',
'mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX', 'mmGC_EDC_STATUS',
'mmGC_EDC_STATUS_BASE_IDX', 'mmGC_EDC_STRETCH_CTRL',
'mmGC_EDC_STRETCH_CTRL_BASE_IDX', 'mmGC_EDC_STRETCH_THRESHOLD',
'mmGC_EDC_STRETCH_THRESHOLD_BASE_IDX', 'mmGC_EDC_THRESHOLD',
'mmGC_EDC_THRESHOLD_BASE_IDX', 'mmGC_IH_COOKIE_0_PTR',
'mmGC_IH_COOKIE_0_PTR_BASE_IDX', 'mmGC_THROTTLE_CTRL',
'mmGC_THROTTLE_CTRL1', 'mmGC_THROTTLE_CTRL1_BASE_IDX',
'mmGC_THROTTLE_CTRL_BASE_IDX', 'mmGC_THROTTLE_STATUS',
'mmGC_THROTTLE_STATUS_BASE_IDX', 'mmGC_USER_PRIM_CONFIG',
'mmGC_USER_PRIM_CONFIG_BASE_IDX', 'mmGC_USER_RB_BACKEND_DISABLE',
'mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX',
'mmGC_USER_RB_REDUNDANCY', 'mmGC_USER_RB_REDUNDANCY_BASE_IDX',
'mmGC_USER_RMI_REDUNDANCY', 'mmGC_USER_RMI_REDUNDANCY_BASE_IDX',
'mmGC_USER_SA_UNIT_DISABLE', 'mmGC_USER_SA_UNIT_DISABLE_BASE_IDX',
'mmGC_USER_SHADER_ARRAY_CONFIG',
'mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX',
'mmGC_USER_SHADER_RATE_CONFIG',
'mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX', 'mmGDS_ATOM_BASE',
'mmGDS_ATOM_BASE_BASE_IDX', 'mmGDS_ATOM_CNTL',
'mmGDS_ATOM_CNTL_BASE_IDX', 'mmGDS_ATOM_COMPLETE',
'mmGDS_ATOM_COMPLETE_BASE_IDX', 'mmGDS_ATOM_DST',
'mmGDS_ATOM_DST_BASE_IDX', 'mmGDS_ATOM_OFFSET0',
'mmGDS_ATOM_OFFSET0_BASE_IDX', 'mmGDS_ATOM_OFFSET1',
'mmGDS_ATOM_OFFSET1_BASE_IDX', 'mmGDS_ATOM_OP',
'mmGDS_ATOM_OP_BASE_IDX', 'mmGDS_ATOM_READ0',
'mmGDS_ATOM_READ0_BASE_IDX', 'mmGDS_ATOM_READ0_U',
'mmGDS_ATOM_READ0_U_BASE_IDX', 'mmGDS_ATOM_READ1',
'mmGDS_ATOM_READ1_BASE_IDX', 'mmGDS_ATOM_READ1_U',
'mmGDS_ATOM_READ1_U_BASE_IDX', 'mmGDS_ATOM_SIZE',
'mmGDS_ATOM_SIZE_BASE_IDX', 'mmGDS_ATOM_SRC0',
'mmGDS_ATOM_SRC0_BASE_IDX', 'mmGDS_ATOM_SRC0_U',
'mmGDS_ATOM_SRC0_U_BASE_IDX', 'mmGDS_ATOM_SRC1',
'mmGDS_ATOM_SRC1_BASE_IDX', 'mmGDS_ATOM_SRC1_U',
'mmGDS_ATOM_SRC1_U_BASE_IDX', 'mmGDS_CNTL_STATUS',
'mmGDS_CNTL_STATUS_BASE_IDX', 'mmGDS_COMPUTE_MAX_WAVE_ID',
'mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX', 'mmGDS_CONFIG',
'mmGDS_CONFIG_BASE_IDX', 'mmGDS_CS_CTXSW_CNT0',
'mmGDS_CS_CTXSW_CNT0_BASE_IDX', 'mmGDS_CS_CTXSW_CNT1',
'mmGDS_CS_CTXSW_CNT1_BASE_IDX', 'mmGDS_CS_CTXSW_CNT2',
'mmGDS_CS_CTXSW_CNT2_BASE_IDX', 'mmGDS_CS_CTXSW_CNT3',
'mmGDS_CS_CTXSW_CNT3_BASE_IDX', 'mmGDS_CS_CTXSW_STATUS',
'mmGDS_CS_CTXSW_STATUS_BASE_IDX', 'mmGDS_DSM_CNTL',
'mmGDS_DSM_CNTL2', 'mmGDS_DSM_CNTL2_BASE_IDX',
'mmGDS_DSM_CNTL_BASE_IDX', 'mmGDS_EDC_CNT',
'mmGDS_EDC_CNT_BASE_IDX', 'mmGDS_EDC_GRBM_CNT',
'mmGDS_EDC_GRBM_CNT_BASE_IDX', 'mmGDS_EDC_OA_DED',
'mmGDS_EDC_OA_DED_BASE_IDX', 'mmGDS_EDC_OA_PHY_CNT',
'mmGDS_EDC_OA_PHY_CNT_BASE_IDX', 'mmGDS_EDC_OA_PIPE_CNT',
'mmGDS_EDC_OA_PIPE_CNT_BASE_IDX', 'mmGDS_ENHANCE',
'mmGDS_ENHANCE2', 'mmGDS_ENHANCE2_BASE_IDX',
'mmGDS_ENHANCE_BASE_IDX', 'mmGDS_GFX_CTXSW_STATUS',
'mmGDS_GFX_CTXSW_STATUS_BASE_IDX', 'mmGDS_GS_CTXSW_CNT0',
'mmGDS_GS_CTXSW_CNT0_BASE_IDX', 'mmGDS_GS_CTXSW_CNT1',
'mmGDS_GS_CTXSW_CNT1_BASE_IDX', 'mmGDS_GS_CTXSW_CNT2',
'mmGDS_GS_CTXSW_CNT2_BASE_IDX', 'mmGDS_GS_CTXSW_CNT3',
'mmGDS_GS_CTXSW_CNT3_BASE_IDX', 'mmGDS_GWS_RESET0',
'mmGDS_GWS_RESET0_BASE_IDX', 'mmGDS_GWS_RESET1',
'mmGDS_GWS_RESET1_BASE_IDX', 'mmGDS_GWS_RESOURCE',
'mmGDS_GWS_RESOURCE_BASE_IDX', 'mmGDS_GWS_RESOURCE_CNT',
'mmGDS_GWS_RESOURCE_CNTL', 'mmGDS_GWS_RESOURCE_CNTL_BASE_IDX',
'mmGDS_GWS_RESOURCE_CNT_BASE_IDX', 'mmGDS_GWS_RESOURCE_RESET',
'mmGDS_GWS_RESOURCE_RESET_BASE_IDX', 'mmGDS_GWS_VMID0',
'mmGDS_GWS_VMID0_BASE_IDX', 'mmGDS_GWS_VMID1', 'mmGDS_GWS_VMID10',
'mmGDS_GWS_VMID10_BASE_IDX', 'mmGDS_GWS_VMID11',
'mmGDS_GWS_VMID11_BASE_IDX', 'mmGDS_GWS_VMID12',
'mmGDS_GWS_VMID12_BASE_IDX', 'mmGDS_GWS_VMID13',
'mmGDS_GWS_VMID13_BASE_IDX', 'mmGDS_GWS_VMID14',
'mmGDS_GWS_VMID14_BASE_IDX', 'mmGDS_GWS_VMID15',
'mmGDS_GWS_VMID15_BASE_IDX', 'mmGDS_GWS_VMID1_BASE_IDX',
'mmGDS_GWS_VMID2', 'mmGDS_GWS_VMID2_BASE_IDX', 'mmGDS_GWS_VMID3',
'mmGDS_GWS_VMID3_BASE_IDX', 'mmGDS_GWS_VMID4',
'mmGDS_GWS_VMID4_BASE_IDX', 'mmGDS_GWS_VMID5',
'mmGDS_GWS_VMID5_BASE_IDX', 'mmGDS_GWS_VMID6',
'mmGDS_GWS_VMID6_BASE_IDX', 'mmGDS_GWS_VMID7',
'mmGDS_GWS_VMID7_BASE_IDX', 'mmGDS_GWS_VMID8',
'mmGDS_GWS_VMID8_BASE_IDX', 'mmGDS_GWS_VMID9',
'mmGDS_GWS_VMID9_BASE_IDX', 'mmGDS_MEMORY_CLEAN',
'mmGDS_MEMORY_CLEAN_BASE_IDX', 'mmGDS_OA_ADDRESS',
'mmGDS_OA_ADDRESS_BASE_IDX', 'mmGDS_OA_CGPG_RESTORE',
'mmGDS_OA_CGPG_RESTORE_BASE_IDX', 'mmGDS_OA_CNTL',
'mmGDS_OA_CNTL_BASE_IDX', 'mmGDS_OA_COUNTER',
'mmGDS_OA_COUNTER_BASE_IDX', 'mmGDS_OA_INCDEC',
'mmGDS_OA_INCDEC_BASE_IDX', 'mmGDS_OA_RESET',
'mmGDS_OA_RESET_BASE_IDX', 'mmGDS_OA_RESET_MASK',
'mmGDS_OA_RESET_MASK_BASE_IDX', 'mmGDS_OA_RING_SIZE',
'mmGDS_OA_RING_SIZE_BASE_IDX', 'mmGDS_OA_VMID0',
'mmGDS_OA_VMID0_BASE_IDX', 'mmGDS_OA_VMID1', 'mmGDS_OA_VMID10',
'mmGDS_OA_VMID10_BASE_IDX', 'mmGDS_OA_VMID11',
'mmGDS_OA_VMID11_BASE_IDX', 'mmGDS_OA_VMID12',
'mmGDS_OA_VMID12_BASE_IDX', 'mmGDS_OA_VMID13',
'mmGDS_OA_VMID13_BASE_IDX', 'mmGDS_OA_VMID14',
'mmGDS_OA_VMID14_BASE_IDX', 'mmGDS_OA_VMID15',
'mmGDS_OA_VMID15_BASE_IDX', 'mmGDS_OA_VMID1_BASE_IDX',
'mmGDS_OA_VMID2', 'mmGDS_OA_VMID2_BASE_IDX', 'mmGDS_OA_VMID3',
'mmGDS_OA_VMID3_BASE_IDX', 'mmGDS_OA_VMID4',
'mmGDS_OA_VMID4_BASE_IDX', 'mmGDS_OA_VMID5',
'mmGDS_OA_VMID5_BASE_IDX', 'mmGDS_OA_VMID6',
'mmGDS_OA_VMID6_BASE_IDX', 'mmGDS_OA_VMID7',
'mmGDS_OA_VMID7_BASE_IDX', 'mmGDS_OA_VMID8',
'mmGDS_OA_VMID8_BASE_IDX', 'mmGDS_OA_VMID9',
'mmGDS_OA_VMID9_BASE_IDX', 'mmGDS_PERFCOUNTER0_HI',
'mmGDS_PERFCOUNTER0_HI_BASE_IDX', 'mmGDS_PERFCOUNTER0_LO',
'mmGDS_PERFCOUNTER0_LO_BASE_IDX', 'mmGDS_PERFCOUNTER0_SELECT',
'mmGDS_PERFCOUNTER0_SELECT1',
'mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmGDS_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGDS_PERFCOUNTER1_HI',
'mmGDS_PERFCOUNTER1_HI_BASE_IDX', 'mmGDS_PERFCOUNTER1_LO',
'mmGDS_PERFCOUNTER1_LO_BASE_IDX', 'mmGDS_PERFCOUNTER1_SELECT',
'mmGDS_PERFCOUNTER1_SELECT1',
'mmGDS_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmGDS_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGDS_PERFCOUNTER2_HI',
'mmGDS_PERFCOUNTER2_HI_BASE_IDX', 'mmGDS_PERFCOUNTER2_LO',
'mmGDS_PERFCOUNTER2_LO_BASE_IDX', 'mmGDS_PERFCOUNTER2_SELECT',
'mmGDS_PERFCOUNTER2_SELECT1',
'mmGDS_PERFCOUNTER2_SELECT1_BASE_IDX',
'mmGDS_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGDS_PERFCOUNTER3_HI',
'mmGDS_PERFCOUNTER3_HI_BASE_IDX', 'mmGDS_PERFCOUNTER3_LO',
'mmGDS_PERFCOUNTER3_LO_BASE_IDX', 'mmGDS_PERFCOUNTER3_SELECT',
'mmGDS_PERFCOUNTER3_SELECT1',
'mmGDS_PERFCOUNTER3_SELECT1_BASE_IDX',
'mmGDS_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGDS_PROTECTION_FAULT',
'mmGDS_PROTECTION_FAULT_BASE_IDX', 'mmGDS_PS_CTXSW_CNT0',
'mmGDS_PS_CTXSW_CNT0_BASE_IDX', 'mmGDS_PS_CTXSW_CNT1',
'mmGDS_PS_CTXSW_CNT1_BASE_IDX', 'mmGDS_PS_CTXSW_CNT2',
'mmGDS_PS_CTXSW_CNT2_BASE_IDX', 'mmGDS_PS_CTXSW_CNT3',
'mmGDS_PS_CTXSW_CNT3_BASE_IDX', 'mmGDS_PS_CTXSW_IDX',
'mmGDS_PS_CTXSW_IDX_BASE_IDX', 'mmGDS_RD_ADDR',
'mmGDS_RD_ADDR_BASE_IDX', 'mmGDS_RD_BURST_ADDR',
'mmGDS_RD_BURST_ADDR_BASE_IDX', 'mmGDS_RD_BURST_COUNT',
'mmGDS_RD_BURST_COUNT_BASE_IDX', 'mmGDS_RD_BURST_DATA',
'mmGDS_RD_BURST_DATA_BASE_IDX', 'mmGDS_RD_DATA',
'mmGDS_RD_DATA_BASE_IDX', 'mmGDS_VMID0_BASE',
'mmGDS_VMID0_BASE_BASE_IDX', 'mmGDS_VMID0_SIZE',
'mmGDS_VMID0_SIZE_BASE_IDX', 'mmGDS_VMID10_BASE',
'mmGDS_VMID10_BASE_BASE_IDX', 'mmGDS_VMID10_SIZE',
'mmGDS_VMID10_SIZE_BASE_IDX', 'mmGDS_VMID11_BASE',
'mmGDS_VMID11_BASE_BASE_IDX', 'mmGDS_VMID11_SIZE',
'mmGDS_VMID11_SIZE_BASE_IDX', 'mmGDS_VMID12_BASE',
'mmGDS_VMID12_BASE_BASE_IDX', 'mmGDS_VMID12_SIZE',
'mmGDS_VMID12_SIZE_BASE_IDX', 'mmGDS_VMID13_BASE',
'mmGDS_VMID13_BASE_BASE_IDX', 'mmGDS_VMID13_SIZE',
'mmGDS_VMID13_SIZE_BASE_IDX', 'mmGDS_VMID14_BASE',
'mmGDS_VMID14_BASE_BASE_IDX', 'mmGDS_VMID14_SIZE',
'mmGDS_VMID14_SIZE_BASE_IDX', 'mmGDS_VMID15_BASE',
'mmGDS_VMID15_BASE_BASE_IDX', 'mmGDS_VMID15_SIZE',
'mmGDS_VMID15_SIZE_BASE_IDX', 'mmGDS_VMID1_BASE',
'mmGDS_VMID1_BASE_BASE_IDX', 'mmGDS_VMID1_SIZE',
'mmGDS_VMID1_SIZE_BASE_IDX', 'mmGDS_VMID2_BASE',
'mmGDS_VMID2_BASE_BASE_IDX', 'mmGDS_VMID2_SIZE',
'mmGDS_VMID2_SIZE_BASE_IDX', 'mmGDS_VMID3_BASE',
'mmGDS_VMID3_BASE_BASE_IDX', 'mmGDS_VMID3_SIZE',
'mmGDS_VMID3_SIZE_BASE_IDX', 'mmGDS_VMID4_BASE',
'mmGDS_VMID4_BASE_BASE_IDX', 'mmGDS_VMID4_SIZE',
'mmGDS_VMID4_SIZE_BASE_IDX', 'mmGDS_VMID5_BASE',
'mmGDS_VMID5_BASE_BASE_IDX', 'mmGDS_VMID5_SIZE',
'mmGDS_VMID5_SIZE_BASE_IDX', 'mmGDS_VMID6_BASE',
'mmGDS_VMID6_BASE_BASE_IDX', 'mmGDS_VMID6_SIZE',
'mmGDS_VMID6_SIZE_BASE_IDX', 'mmGDS_VMID7_BASE',
'mmGDS_VMID7_BASE_BASE_IDX', 'mmGDS_VMID7_SIZE',
'mmGDS_VMID7_SIZE_BASE_IDX', 'mmGDS_VMID8_BASE',
'mmGDS_VMID8_BASE_BASE_IDX', 'mmGDS_VMID8_SIZE',
'mmGDS_VMID8_SIZE_BASE_IDX', 'mmGDS_VMID9_BASE',
'mmGDS_VMID9_BASE_BASE_IDX', 'mmGDS_VMID9_SIZE',
'mmGDS_VMID9_SIZE_BASE_IDX', 'mmGDS_VM_PROTECTION_FAULT',
'mmGDS_VM_PROTECTION_FAULT_BASE_IDX', 'mmGDS_VS_CTXSW_CNT0',
'mmGDS_VS_CTXSW_CNT0_BASE_IDX', 'mmGDS_VS_CTXSW_CNT1',
'mmGDS_VS_CTXSW_CNT1_BASE_IDX', 'mmGDS_VS_CTXSW_CNT2',
'mmGDS_VS_CTXSW_CNT2_BASE_IDX', 'mmGDS_VS_CTXSW_CNT3',
'mmGDS_VS_CTXSW_CNT3_BASE_IDX', 'mmGDS_WD_GDS_CSB',
'mmGDS_WD_GDS_CSB_BASE_IDX', 'mmGDS_WRITE_COMPLETE',
'mmGDS_WRITE_COMPLETE_BASE_IDX', 'mmGDS_WR_ADDR',
'mmGDS_WR_ADDR_BASE_IDX', 'mmGDS_WR_BURST_ADDR',
'mmGDS_WR_BURST_ADDR_BASE_IDX', 'mmGDS_WR_BURST_DATA',
'mmGDS_WR_BURST_DATA_BASE_IDX', 'mmGDS_WR_DATA',
'mmGDS_WR_DATA_BASE_IDX', 'mmGE1_PERFCOUNTER0_HI',
'mmGE1_PERFCOUNTER0_HI_BASE_IDX', 'mmGE1_PERFCOUNTER0_LO',
'mmGE1_PERFCOUNTER0_LO_BASE_IDX', 'mmGE1_PERFCOUNTER0_SELECT',
'mmGE1_PERFCOUNTER0_SELECT1',
'mmGE1_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmGE1_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGE1_PERFCOUNTER1_HI',
'mmGE1_PERFCOUNTER1_HI_BASE_IDX', 'mmGE1_PERFCOUNTER1_LO',
'mmGE1_PERFCOUNTER1_LO_BASE_IDX', 'mmGE1_PERFCOUNTER1_SELECT',
'mmGE1_PERFCOUNTER1_SELECT1',
'mmGE1_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmGE1_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGE1_PERFCOUNTER2_HI',
'mmGE1_PERFCOUNTER2_HI_BASE_IDX', 'mmGE1_PERFCOUNTER2_LO',
'mmGE1_PERFCOUNTER2_LO_BASE_IDX', 'mmGE1_PERFCOUNTER2_SELECT',
'mmGE1_PERFCOUNTER2_SELECT1',
'mmGE1_PERFCOUNTER2_SELECT1_BASE_IDX',
'mmGE1_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGE1_PERFCOUNTER3_HI',
'mmGE1_PERFCOUNTER3_HI_BASE_IDX', 'mmGE1_PERFCOUNTER3_LO',
'mmGE1_PERFCOUNTER3_LO_BASE_IDX', 'mmGE1_PERFCOUNTER3_SELECT',
'mmGE1_PERFCOUNTER3_SELECT1',
'mmGE1_PERFCOUNTER3_SELECT1_BASE_IDX',
'mmGE1_PERFCOUNTER3_SELECT_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER0_HI',
'mmGE2_DIST_PERFCOUNTER0_HI_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER0_LO',
'mmGE2_DIST_PERFCOUNTER0_LO_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER0_SELECT',
'mmGE2_DIST_PERFCOUNTER0_SELECT1',
'mmGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER1_HI',
'mmGE2_DIST_PERFCOUNTER1_HI_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER1_LO',
'mmGE2_DIST_PERFCOUNTER1_LO_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER1_SELECT',
'mmGE2_DIST_PERFCOUNTER1_SELECT1',
'mmGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER2_HI',
'mmGE2_DIST_PERFCOUNTER2_HI_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER2_LO',
'mmGE2_DIST_PERFCOUNTER2_LO_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER2_SELECT',
'mmGE2_DIST_PERFCOUNTER2_SELECT1',
'mmGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER3_HI',
'mmGE2_DIST_PERFCOUNTER3_HI_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER3_LO',
'mmGE2_DIST_PERFCOUNTER3_LO_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER3_SELECT',
'mmGE2_DIST_PERFCOUNTER3_SELECT1',
'mmGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX',
'mmGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX',
'mmGE2_SE_PERFCOUNTER0_HI', 'mmGE2_SE_PERFCOUNTER0_HI_BASE_IDX',
'mmGE2_SE_PERFCOUNTER0_LO', 'mmGE2_SE_PERFCOUNTER0_LO_BASE_IDX',
'mmGE2_SE_PERFCOUNTER0_SELECT', 'mmGE2_SE_PERFCOUNTER0_SELECT1',
'mmGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX',
'mmGE2_SE_PERFCOUNTER1_HI', 'mmGE2_SE_PERFCOUNTER1_HI_BASE_IDX',
'mmGE2_SE_PERFCOUNTER1_LO', 'mmGE2_SE_PERFCOUNTER1_LO_BASE_IDX',
'mmGE2_SE_PERFCOUNTER1_SELECT', 'mmGE2_SE_PERFCOUNTER1_SELECT1',
'mmGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX',
'mmGE2_SE_PERFCOUNTER2_HI', 'mmGE2_SE_PERFCOUNTER2_HI_BASE_IDX',
'mmGE2_SE_PERFCOUNTER2_LO', 'mmGE2_SE_PERFCOUNTER2_LO_BASE_IDX',
'mmGE2_SE_PERFCOUNTER2_SELECT', 'mmGE2_SE_PERFCOUNTER2_SELECT1',
'mmGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX',
'mmGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX',
'mmGE2_SE_PERFCOUNTER3_HI', 'mmGE2_SE_PERFCOUNTER3_HI_BASE_IDX',
'mmGE2_SE_PERFCOUNTER3_LO', 'mmGE2_SE_PERFCOUNTER3_LO_BASE_IDX',
'mmGE2_SE_PERFCOUNTER3_SELECT', 'mmGE2_SE_PERFCOUNTER3_SELECT1',
'mmGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX',
'mmGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGE_CNTL',
'mmGE_CNTL_BASE_IDX', 'mmGE_DMA_FIRST_INDEX',
'mmGE_DMA_FIRST_INDEX_BASE_IDX', 'mmGE_INDX_OFFSET',
'mmGE_INDX_OFFSET_BASE_IDX', 'mmGE_MAX_OUTPUT_PER_SUBGROUP',
'mmGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX', 'mmGE_MAX_VTX_INDX',
'mmGE_MAX_VTX_INDX_BASE_IDX', 'mmGE_MIN_VTX_INDX',
'mmGE_MIN_VTX_INDX_BASE_IDX', 'mmGE_MULTI_PRIM_IB_RESET_EN',
'mmGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX', 'mmGE_NGG_SUBGRP_CNTL',
'mmGE_NGG_SUBGRP_CNTL_BASE_IDX', 'mmGE_PC_ALLOC',
'mmGE_PC_ALLOC_BASE_IDX', 'mmGE_PC_CNTL', 'mmGE_PC_CNTL_BASE_IDX',
'mmGE_PRIV_CONTROL', 'mmGE_PRIV_CONTROL_BASE_IDX', 'mmGE_STATUS',
'mmGE_STATUS_BASE_IDX', 'mmGE_STEREO_CNTL',
'mmGE_STEREO_CNTL_BASE_IDX', 'mmGE_USER_VGPR1',
'mmGE_USER_VGPR1_BASE_IDX', 'mmGE_USER_VGPR2',
'mmGE_USER_VGPR2_BASE_IDX', 'mmGE_USER_VGPR3',
'mmGE_USER_VGPR3_BASE_IDX', 'mmGE_USER_VGPR_EN',
'mmGE_USER_VGPR_EN_BASE_IDX', 'mmGFX_COPY_STATE',
'mmGFX_COPY_STATE_BASE_IDX', 'mmGFX_PIPE_CONTROL',
'mmGFX_PIPE_CONTROL_BASE_IDX', 'mmGFX_PIPE_PRIORITY',
'mmGFX_PIPE_PRIORITY_BASE_IDX', 'mmGL1A_PERFCOUNTER0_HI',
'mmGL1A_PERFCOUNTER0_HI_BASE_IDX', 'mmGL1A_PERFCOUNTER0_LO',
'mmGL1A_PERFCOUNTER0_LO_BASE_IDX', 'mmGL1A_PERFCOUNTER0_SELECT',
'mmGL1A_PERFCOUNTER0_SELECT1',
'mmGL1A_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmGL1A_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGL1A_PERFCOUNTER1_HI',
'mmGL1A_PERFCOUNTER1_HI_BASE_IDX', 'mmGL1A_PERFCOUNTER1_LO',
'mmGL1A_PERFCOUNTER1_LO_BASE_IDX', 'mmGL1A_PERFCOUNTER1_SELECT',
'mmGL1A_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGL1A_PERFCOUNTER2_HI',
'mmGL1A_PERFCOUNTER2_HI_BASE_IDX', 'mmGL1A_PERFCOUNTER2_LO',
'mmGL1A_PERFCOUNTER2_LO_BASE_IDX', 'mmGL1A_PERFCOUNTER2_SELECT',
'mmGL1A_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGL1A_PERFCOUNTER3_HI',
'mmGL1A_PERFCOUNTER3_HI_BASE_IDX', 'mmGL1A_PERFCOUNTER3_LO',
'mmGL1A_PERFCOUNTER3_LO_BASE_IDX', 'mmGL1A_PERFCOUNTER3_SELECT',
'mmGL1A_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGL1C_PERFCOUNTER0_HI',
'mmGL1C_PERFCOUNTER0_HI_BASE_IDX', 'mmGL1C_PERFCOUNTER0_LO',
'mmGL1C_PERFCOUNTER0_LO_BASE_IDX', 'mmGL1C_PERFCOUNTER0_SELECT',
'mmGL1C_PERFCOUNTER0_SELECT1',
'mmGL1C_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmGL1C_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGL1C_PERFCOUNTER1_HI',
'mmGL1C_PERFCOUNTER1_HI_BASE_IDX', 'mmGL1C_PERFCOUNTER1_LO',
'mmGL1C_PERFCOUNTER1_LO_BASE_IDX', 'mmGL1C_PERFCOUNTER1_SELECT',
'mmGL1C_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGL1C_PERFCOUNTER2_HI',
'mmGL1C_PERFCOUNTER2_HI_BASE_IDX', 'mmGL1C_PERFCOUNTER2_LO',
'mmGL1C_PERFCOUNTER2_LO_BASE_IDX', 'mmGL1C_PERFCOUNTER2_SELECT',
'mmGL1C_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGL1C_PERFCOUNTER3_HI',
'mmGL1C_PERFCOUNTER3_HI_BASE_IDX', 'mmGL1C_PERFCOUNTER3_LO',
'mmGL1C_PERFCOUNTER3_LO_BASE_IDX', 'mmGL1C_PERFCOUNTER3_SELECT',
'mmGL1C_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGL1C_STATUS',
'mmGL1C_STATUS_BASE_IDX', 'mmGL1C_UTCL0_CNTL2',
'mmGL1C_UTCL0_CNTL2_BASE_IDX', 'mmGL1C_UTCL0_RETRY',
'mmGL1C_UTCL0_RETRY_BASE_IDX', 'mmGL1C_UTCL0_STATUS',
'mmGL1C_UTCL0_STATUS_BASE_IDX', 'mmGL1_ARB_STATUS',
'mmGL1_ARB_STATUS_BASE_IDX', 'mmGL1_DRAM_BURST_MASK',
'mmGL1_DRAM_BURST_MASK_BASE_IDX', 'mmGL1_PIPE_STEER',
'mmGL1_PIPE_STEER_BASE_IDX', 'mmGL2A_ADDR_MATCH_CTRL',
'mmGL2A_ADDR_MATCH_CTRL_BASE_IDX', 'mmGL2A_ADDR_MATCH_MASK',
'mmGL2A_ADDR_MATCH_MASK_BASE_IDX', 'mmGL2A_ADDR_MATCH_SIZE',
'mmGL2A_ADDR_MATCH_SIZE_BASE_IDX', 'mmGL2A_CGTT_SCLK_CTRL',
'mmGL2A_CGTT_SCLK_CTRL_1', 'mmGL2A_CGTT_SCLK_CTRL_1_BASE_IDX',
'mmGL2A_CGTT_SCLK_CTRL_BASE_IDX', 'mmGL2A_PERFCOUNTER0_HI',
'mmGL2A_PERFCOUNTER0_HI_BASE_IDX', 'mmGL2A_PERFCOUNTER0_LO',
'mmGL2A_PERFCOUNTER0_LO_BASE_IDX', 'mmGL2A_PERFCOUNTER0_SELECT',
'mmGL2A_PERFCOUNTER0_SELECT1',
'mmGL2A_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmGL2A_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGL2A_PERFCOUNTER1_HI',
'mmGL2A_PERFCOUNTER1_HI_BASE_IDX', 'mmGL2A_PERFCOUNTER1_LO',
'mmGL2A_PERFCOUNTER1_LO_BASE_IDX', 'mmGL2A_PERFCOUNTER1_SELECT',
'mmGL2A_PERFCOUNTER1_SELECT1',
'mmGL2A_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmGL2A_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGL2A_PERFCOUNTER2_HI',
'mmGL2A_PERFCOUNTER2_HI_BASE_IDX', 'mmGL2A_PERFCOUNTER2_LO',
'mmGL2A_PERFCOUNTER2_LO_BASE_IDX', 'mmGL2A_PERFCOUNTER2_SELECT',
'mmGL2A_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGL2A_PERFCOUNTER3_HI',
'mmGL2A_PERFCOUNTER3_HI_BASE_IDX', 'mmGL2A_PERFCOUNTER3_LO',
'mmGL2A_PERFCOUNTER3_LO_BASE_IDX', 'mmGL2A_PERFCOUNTER3_SELECT',
'mmGL2A_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGL2A_PRIORITY_CTRL',
'mmGL2A_PRIORITY_CTRL_BASE_IDX', 'mmGL2C_ADDR_MATCH_MASK',
'mmGL2C_ADDR_MATCH_MASK_BASE_IDX', 'mmGL2C_ADDR_MATCH_SIZE',
'mmGL2C_ADDR_MATCH_SIZE_BASE_IDX', 'mmGL2C_CGTT_SCLK_CTRL',
'mmGL2C_CGTT_SCLK_CTRL_BASE_IDX', 'mmGL2C_CM_CTRL0',
'mmGL2C_CM_CTRL0_BASE_IDX', 'mmGL2C_CM_CTRL1',
'mmGL2C_CM_CTRL1_BASE_IDX', 'mmGL2C_CM_STALL',
'mmGL2C_CM_STALL_BASE_IDX', 'mmGL2C_CTRL', 'mmGL2C_CTRL2',
'mmGL2C_CTRL2_BASE_IDX', 'mmGL2C_CTRL_BASE_IDX',
'mmGL2C_LB_CTR_CTRL', 'mmGL2C_LB_CTR_CTRL_BASE_IDX',
'mmGL2C_LB_CTR_SEL0', 'mmGL2C_LB_CTR_SEL0_BASE_IDX',
'mmGL2C_LB_CTR_SEL1', 'mmGL2C_LB_CTR_SEL1_BASE_IDX',
'mmGL2C_LB_DATA0', 'mmGL2C_LB_DATA0_BASE_IDX', 'mmGL2C_LB_DATA1',
'mmGL2C_LB_DATA1_BASE_IDX', 'mmGL2C_LB_DATA2',
'mmGL2C_LB_DATA2_BASE_IDX', 'mmGL2C_LB_DATA3',
'mmGL2C_LB_DATA3_BASE_IDX', 'mmGL2C_MDC_PF_FLAG_CTRL',
'mmGL2C_MDC_PF_FLAG_CTRL_BASE_IDX', 'mmGL2C_PERFCOUNTER0_HI',
'mmGL2C_PERFCOUNTER0_HI_BASE_IDX', 'mmGL2C_PERFCOUNTER0_LO',
'mmGL2C_PERFCOUNTER0_LO_BASE_IDX', 'mmGL2C_PERFCOUNTER0_SELECT',
'mmGL2C_PERFCOUNTER0_SELECT1',
'mmGL2C_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmGL2C_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGL2C_PERFCOUNTER1_HI',
'mmGL2C_PERFCOUNTER1_HI_BASE_IDX', 'mmGL2C_PERFCOUNTER1_LO',
'mmGL2C_PERFCOUNTER1_LO_BASE_IDX', 'mmGL2C_PERFCOUNTER1_SELECT',
'mmGL2C_PERFCOUNTER1_SELECT1',
'mmGL2C_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmGL2C_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGL2C_PERFCOUNTER2_HI',
'mmGL2C_PERFCOUNTER2_HI_BASE_IDX', 'mmGL2C_PERFCOUNTER2_LO',
'mmGL2C_PERFCOUNTER2_LO_BASE_IDX', 'mmGL2C_PERFCOUNTER2_SELECT',
'mmGL2C_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGL2C_PERFCOUNTER3_HI',
'mmGL2C_PERFCOUNTER3_HI_BASE_IDX', 'mmGL2C_PERFCOUNTER3_LO',
'mmGL2C_PERFCOUNTER3_LO_BASE_IDX', 'mmGL2C_PERFCOUNTER3_SELECT',
'mmGL2C_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGL2C_SOFT_RESET',
'mmGL2C_SOFT_RESET_BASE_IDX', 'mmGL2C_WBINVL2',
'mmGL2C_WBINVL2_BASE_IDX', 'mmGL2_PIPE_STEER_0',
'mmGL2_PIPE_STEER_0_BASE_IDX', 'mmGL2_PIPE_STEER_1',
'mmGL2_PIPE_STEER_1_BASE_IDX', 'mmGRBM_CAM_DATA',
'mmGRBM_CAM_DATA_BASE_IDX', 'mmGRBM_CAM_DATA_UPPER',
'mmGRBM_CAM_DATA_UPPER_BASE_IDX', 'mmGRBM_CAM_INDEX',
'mmGRBM_CAM_INDEX_BASE_IDX', 'mmGRBM_CGTT_CLK_CNTL',
'mmGRBM_CGTT_CLK_CNTL_BASE_IDX', 'mmGRBM_CHIP_REVISION',
'mmGRBM_CHIP_REVISION_BASE_IDX', 'mmGRBM_CNTL',
'mmGRBM_CNTL_BASE_IDX', 'mmGRBM_DSM_BYPASS',
'mmGRBM_DSM_BYPASS_BASE_IDX', 'mmGRBM_FENCE_RANGE0',
'mmGRBM_FENCE_RANGE0_BASE_IDX', 'mmGRBM_FENCE_RANGE1',
'mmGRBM_FENCE_RANGE1_BASE_IDX', 'mmGRBM_GFX_CLKEN_CNTL',
'mmGRBM_GFX_CLKEN_CNTL_BASE_IDX', 'mmGRBM_GFX_CNTL',
'mmGRBM_GFX_CNTL_BASE_IDX', 'mmGRBM_GFX_CNTL_SR_DATA',
'mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX', 'mmGRBM_GFX_CNTL_SR_SELECT',
'mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX', 'mmGRBM_GFX_INDEX',
'mmGRBM_GFX_INDEX_BASE_IDX', 'mmGRBM_GFX_INDEX_SR_DATA',
'mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX', 'mmGRBM_GFX_INDEX_SR_SELECT',
'mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX', 'mmGRBM_HYP_CAM_DATA',
'mmGRBM_HYP_CAM_DATA_BASE_IDX', 'mmGRBM_HYP_CAM_DATA_UPPER',
'mmGRBM_HYP_CAM_DATA_UPPER_BASE_IDX', 'mmGRBM_HYP_CAM_INDEX',
'mmGRBM_HYP_CAM_INDEX_BASE_IDX', 'mmGRBM_IH_CREDIT',
'mmGRBM_IH_CREDIT_BASE_IDX', 'mmGRBM_INT_CNTL',
'mmGRBM_INT_CNTL_BASE_IDX', 'mmGRBM_NOWHERE',
'mmGRBM_NOWHERE_BASE_IDX', 'mmGRBM_PERFCOUNTER0_HI',
'mmGRBM_PERFCOUNTER0_HI_BASE_IDX', 'mmGRBM_PERFCOUNTER0_LO',
'mmGRBM_PERFCOUNTER0_LO_BASE_IDX', 'mmGRBM_PERFCOUNTER0_SELECT',
'mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX',
'mmGRBM_PERFCOUNTER0_SELECT_HI',
'mmGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX',
'mmGRBM_PERFCOUNTER1_HI', 'mmGRBM_PERFCOUNTER1_HI_BASE_IDX',
'mmGRBM_PERFCOUNTER1_LO', 'mmGRBM_PERFCOUNTER1_LO_BASE_IDX',
'mmGRBM_PERFCOUNTER1_SELECT',
'mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX',
'mmGRBM_PERFCOUNTER1_SELECT_HI',
'mmGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX', 'mmGRBM_PWR_CNTL',
'mmGRBM_PWR_CNTL2', 'mmGRBM_PWR_CNTL2_BASE_IDX',
'mmGRBM_PWR_CNTL_BASE_IDX', 'mmGRBM_READ_ERROR',
'mmGRBM_READ_ERROR2', 'mmGRBM_READ_ERROR2_BASE_IDX',
'mmGRBM_READ_ERROR_BASE_IDX', 'mmGRBM_SCRATCH_REG0',
'mmGRBM_SCRATCH_REG0_BASE_IDX', 'mmGRBM_SCRATCH_REG1',
'mmGRBM_SCRATCH_REG1_BASE_IDX', 'mmGRBM_SCRATCH_REG2',
'mmGRBM_SCRATCH_REG2_BASE_IDX', 'mmGRBM_SCRATCH_REG3',
'mmGRBM_SCRATCH_REG3_BASE_IDX', 'mmGRBM_SCRATCH_REG4',
'mmGRBM_SCRATCH_REG4_BASE_IDX', 'mmGRBM_SCRATCH_REG5',
'mmGRBM_SCRATCH_REG5_BASE_IDX', 'mmGRBM_SCRATCH_REG6',
'mmGRBM_SCRATCH_REG6_BASE_IDX', 'mmGRBM_SCRATCH_REG7',
'mmGRBM_SCRATCH_REG7_BASE_IDX', 'mmGRBM_SE0_PERFCOUNTER_HI',
'mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX', 'mmGRBM_SE0_PERFCOUNTER_LO',
'mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX',
'mmGRBM_SE0_PERFCOUNTER_SELECT',
'mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX',
'mmGRBM_SE1_PERFCOUNTER_HI', 'mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX',
'mmGRBM_SE1_PERFCOUNTER_LO', 'mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX',
'mmGRBM_SE1_PERFCOUNTER_SELECT',
'mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX',
'mmGRBM_SE2_PERFCOUNTER_HI', 'mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX',
'mmGRBM_SE2_PERFCOUNTER_LO', 'mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX',
'mmGRBM_SE2_PERFCOUNTER_SELECT',
'mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX',
'mmGRBM_SE3_PERFCOUNTER_HI', 'mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX',
'mmGRBM_SE3_PERFCOUNTER_LO', 'mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX',
'mmGRBM_SE3_PERFCOUNTER_SELECT',
'mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX', 'mmGRBM_SEC_CNTL',
'mmGRBM_SEC_CNTL_BASE_IDX', 'mmGRBM_SE_REMAP_CNTL',
'mmGRBM_SE_REMAP_CNTL_BASE_IDX', 'mmGRBM_SKEW_CNTL',
'mmGRBM_SKEW_CNTL_BASE_IDX', 'mmGRBM_SOFT_RESET',
'mmGRBM_SOFT_RESET_BASE_IDX', 'mmGRBM_STATUS', 'mmGRBM_STATUS2',
'mmGRBM_STATUS2_BASE_IDX', 'mmGRBM_STATUS3',
'mmGRBM_STATUS3_BASE_IDX', 'mmGRBM_STATUS_BASE_IDX',
'mmGRBM_STATUS_SE0', 'mmGRBM_STATUS_SE0_BASE_IDX',
'mmGRBM_STATUS_SE1', 'mmGRBM_STATUS_SE1_BASE_IDX',
'mmGRBM_STATUS_SE2', 'mmGRBM_STATUS_SE2_BASE_IDX',
'mmGRBM_STATUS_SE3', 'mmGRBM_STATUS_SE3_BASE_IDX',
'mmGRBM_TRAP_ADDR', 'mmGRBM_TRAP_ADDR_BASE_IDX',
'mmGRBM_TRAP_ADDR_MSK', 'mmGRBM_TRAP_ADDR_MSK_BASE_IDX',
'mmGRBM_TRAP_OP', 'mmGRBM_TRAP_OP_BASE_IDX', 'mmGRBM_TRAP_WD',
'mmGRBM_TRAP_WD_BASE_IDX', 'mmGRBM_TRAP_WD_MSK',
'mmGRBM_TRAP_WD_MSK_BASE_IDX', 'mmGRBM_UTCL2_INVAL_RANGE_END',
'mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX',
'mmGRBM_UTCL2_INVAL_RANGE_START',
'mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX',
'mmGRBM_WAIT_IDLE_CLOCKS', 'mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX',
'mmGRBM_WRITE_ERROR', 'mmGRBM_WRITE_ERROR_BASE_IDX',
'mmGRTAVFS_CLK_CNTL', 'mmGRTAVFS_CLK_CNTL_BASE_IDX',
'mmGRTAVFS_GENERAL_0', 'mmGRTAVFS_GENERAL_0_BASE_IDX',
'mmGRTAVFS_PSM_CNTL', 'mmGRTAVFS_PSM_CNTL_BASE_IDX',
'mmGRTAVFS_RTAVFS_RD_DATA', 'mmGRTAVFS_RTAVFS_RD_DATA_BASE_IDX',
'mmGRTAVFS_RTAVFS_REG_ADDR', 'mmGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX',
'mmGRTAVFS_RTAVFS_REG_CTRL', 'mmGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX',
'mmGRTAVFS_RTAVFS_REG_STATUS',
'mmGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX',
'mmGRTAVFS_RTAVFS_WR_DATA', 'mmGRTAVFS_RTAVFS_WR_DATA_BASE_IDX',
'mmGRTAVFS_SOFT_RESET', 'mmGRTAVFS_SOFT_RESET_BASE_IDX',
'mmGRTAVFS_TARG_FREQ', 'mmGRTAVFS_TARG_FREQ_BASE_IDX',
'mmGRTAVFS_TARG_VOLT', 'mmGRTAVFS_TARG_VOLT_BASE_IDX',
'mmGUS_CGTT_CLK_CTRL', 'mmGUS_CGTT_CLK_CTRL_BASE_IDX',
'mmGUS_DRAM_COMBINE_FLUSH', 'mmGUS_DRAM_COMBINE_FLUSH_BASE_IDX',
'mmGUS_DRAM_COMBINE_RD_WR_EN',
'mmGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX', 'mmGUS_DRAM_GROUP_BURST',
'mmGUS_DRAM_GROUP_BURST_BASE_IDX', 'mmGUS_DRAM_PRI_AGE_COEFF',
'mmGUS_DRAM_PRI_AGE_COEFF_BASE_IDX', 'mmGUS_DRAM_PRI_AGE_RATE',
'mmGUS_DRAM_PRI_AGE_RATE_BASE_IDX', 'mmGUS_DRAM_PRI_FIXED',
'mmGUS_DRAM_PRI_FIXED_BASE_IDX', 'mmGUS_DRAM_PRI_QUANT1_PRI1',
'mmGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX',
'mmGUS_DRAM_PRI_QUANT1_PRI2',
'mmGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX',
'mmGUS_DRAM_PRI_QUANT1_PRI3',
'mmGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX',
'mmGUS_DRAM_PRI_QUANT1_PRI4',
'mmGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX',
'mmGUS_DRAM_PRI_QUANT1_PRI5',
'mmGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX',
'mmGUS_DRAM_PRI_QUANT_PRI1', 'mmGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX',
'mmGUS_DRAM_PRI_QUANT_PRI2', 'mmGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX',
'mmGUS_DRAM_PRI_QUANT_PRI3', 'mmGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX',
'mmGUS_DRAM_PRI_QUANT_PRI4', 'mmGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX',
'mmGUS_DRAM_PRI_QUANT_PRI5', 'mmGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX',
'mmGUS_DRAM_PRI_QUEUING', 'mmGUS_DRAM_PRI_QUEUING_BASE_IDX',
'mmGUS_DRAM_PRI_URGENCY_COEFF',
'mmGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX',
'mmGUS_DRAM_PRI_URGENCY_MODE',
'mmGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX', 'mmGUS_ERR_STATUS',
'mmGUS_ERR_STATUS_BASE_IDX', 'mmGUS_IO_GROUP_BURST',
'mmGUS_IO_GROUP_BURST_BASE_IDX', 'mmGUS_IO_RD_COMBINE_FLUSH',
'mmGUS_IO_RD_COMBINE_FLUSH_BASE_IDX', 'mmGUS_IO_RD_PRI_AGE_COEFF',
'mmGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX', 'mmGUS_IO_RD_PRI_AGE_RATE',
'mmGUS_IO_RD_PRI_AGE_RATE_BASE_IDX', 'mmGUS_IO_RD_PRI_FIXED',
'mmGUS_IO_RD_PRI_FIXED_BASE_IDX', 'mmGUS_IO_RD_PRI_QUANT1_PRI1',
'mmGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX',
'mmGUS_IO_RD_PRI_QUANT1_PRI2',
'mmGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX',
'mmGUS_IO_RD_PRI_QUANT1_PRI3',
'mmGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX',
'mmGUS_IO_RD_PRI_QUANT1_PRI4',
'mmGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX',
'mmGUS_IO_RD_PRI_QUANT_PRI1',
'mmGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX',
'mmGUS_IO_RD_PRI_QUANT_PRI2',
'mmGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX',
'mmGUS_IO_RD_PRI_QUANT_PRI3',
'mmGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX',
'mmGUS_IO_RD_PRI_QUANT_PRI4',
'mmGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX', 'mmGUS_IO_RD_PRI_QUEUING',
'mmGUS_IO_RD_PRI_QUEUING_BASE_IDX',
'mmGUS_IO_RD_PRI_URGENCY_COEFF',
'mmGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX',
'mmGUS_IO_RD_PRI_URGENCY_MODE',
'mmGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX',
'mmGUS_IO_WR_COMBINE_FLUSH', 'mmGUS_IO_WR_COMBINE_FLUSH_BASE_IDX',
'mmGUS_IO_WR_PRI_AGE_COEFF', 'mmGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX',
'mmGUS_IO_WR_PRI_AGE_RATE', 'mmGUS_IO_WR_PRI_AGE_RATE_BASE_IDX',
'mmGUS_IO_WR_PRI_FIXED', 'mmGUS_IO_WR_PRI_FIXED_BASE_IDX',
'mmGUS_IO_WR_PRI_QUANT1_PRI1',
'mmGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX',
'mmGUS_IO_WR_PRI_QUANT1_PRI2',
'mmGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX',
'mmGUS_IO_WR_PRI_QUANT1_PRI3',
'mmGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX',
'mmGUS_IO_WR_PRI_QUANT1_PRI4',
'mmGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX',
'mmGUS_IO_WR_PRI_QUANT_PRI1',
'mmGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX',
'mmGUS_IO_WR_PRI_QUANT_PRI2',
'mmGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX',
'mmGUS_IO_WR_PRI_QUANT_PRI3',
'mmGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX',
'mmGUS_IO_WR_PRI_QUANT_PRI4',
'mmGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX', 'mmGUS_IO_WR_PRI_QUEUING',
'mmGUS_IO_WR_PRI_QUEUING_BASE_IDX',
'mmGUS_IO_WR_PRI_URGENCY_COEFF',
'mmGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX',
'mmGUS_IO_WR_PRI_URGENCY_MODE',
'mmGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX', 'mmGUS_L1_CH0_CMD_IN',
'mmGUS_L1_CH0_CMD_IN_BASE_IDX', 'mmGUS_L1_CH0_CMD_OUT',
'mmGUS_L1_CH0_CMD_OUT_BASE_IDX', 'mmGUS_L1_CH0_DATA_IN',
'mmGUS_L1_CH0_DATA_IN_BASE_IDX', 'mmGUS_L1_CH0_DATA_OUT',
'mmGUS_L1_CH0_DATA_OUT_BASE_IDX', 'mmGUS_L1_CH0_DATA_U_IN',
'mmGUS_L1_CH0_DATA_U_IN_BASE_IDX', 'mmGUS_L1_CH0_DATA_U_OUT',
'mmGUS_L1_CH0_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_CH1_CMD_IN',
'mmGUS_L1_CH1_CMD_IN_BASE_IDX', 'mmGUS_L1_CH1_CMD_OUT',
'mmGUS_L1_CH1_CMD_OUT_BASE_IDX', 'mmGUS_L1_CH1_DATA_IN',
'mmGUS_L1_CH1_DATA_IN_BASE_IDX', 'mmGUS_L1_CH1_DATA_OUT',
'mmGUS_L1_CH1_DATA_OUT_BASE_IDX', 'mmGUS_L1_CH1_DATA_U_IN',
'mmGUS_L1_CH1_DATA_U_IN_BASE_IDX', 'mmGUS_L1_CH1_DATA_U_OUT',
'mmGUS_L1_CH1_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_SA0_CMD_IN',
'mmGUS_L1_SA0_CMD_IN_BASE_IDX', 'mmGUS_L1_SA0_CMD_OUT',
'mmGUS_L1_SA0_CMD_OUT_BASE_IDX', 'mmGUS_L1_SA0_DATA_IN',
'mmGUS_L1_SA0_DATA_IN_BASE_IDX', 'mmGUS_L1_SA0_DATA_OUT',
'mmGUS_L1_SA0_DATA_OUT_BASE_IDX', 'mmGUS_L1_SA0_DATA_U_IN',
'mmGUS_L1_SA0_DATA_U_IN_BASE_IDX', 'mmGUS_L1_SA0_DATA_U_OUT',
'mmGUS_L1_SA0_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_SA1_CMD_IN',
'mmGUS_L1_SA1_CMD_IN_BASE_IDX', 'mmGUS_L1_SA1_CMD_OUT',
'mmGUS_L1_SA1_CMD_OUT_BASE_IDX', 'mmGUS_L1_SA1_DATA_IN',
'mmGUS_L1_SA1_DATA_IN_BASE_IDX', 'mmGUS_L1_SA1_DATA_OUT',
'mmGUS_L1_SA1_DATA_OUT_BASE_IDX', 'mmGUS_L1_SA1_DATA_U_IN',
'mmGUS_L1_SA1_DATA_U_IN_BASE_IDX', 'mmGUS_L1_SA1_DATA_U_OUT',
'mmGUS_L1_SA1_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_SA2_CMD_IN',
'mmGUS_L1_SA2_CMD_IN_BASE_IDX', 'mmGUS_L1_SA2_CMD_OUT',
'mmGUS_L1_SA2_CMD_OUT_BASE_IDX', 'mmGUS_L1_SA2_DATA_IN',
'mmGUS_L1_SA2_DATA_IN_BASE_IDX', 'mmGUS_L1_SA2_DATA_OUT',
'mmGUS_L1_SA2_DATA_OUT_BASE_IDX', 'mmGUS_L1_SA2_DATA_U_IN',
'mmGUS_L1_SA2_DATA_U_IN_BASE_IDX', 'mmGUS_L1_SA2_DATA_U_OUT',
'mmGUS_L1_SA2_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_SA3_CMD_IN',
'mmGUS_L1_SA3_CMD_IN_BASE_IDX', 'mmGUS_L1_SA3_CMD_OUT',
'mmGUS_L1_SA3_CMD_OUT_BASE_IDX', 'mmGUS_L1_SA3_DATA_IN',
'mmGUS_L1_SA3_DATA_IN_BASE_IDX', 'mmGUS_L1_SA3_DATA_OUT',
'mmGUS_L1_SA3_DATA_OUT_BASE_IDX', 'mmGUS_L1_SA3_DATA_U_IN',
'mmGUS_L1_SA3_DATA_U_IN_BASE_IDX', 'mmGUS_L1_SA3_DATA_U_OUT',
'mmGUS_L1_SA3_DATA_U_OUT_BASE_IDX', 'mmGUS_LATENCY_SAMPLING',
'mmGUS_LATENCY_SAMPLING_BASE_IDX', 'mmGUS_MISC', 'mmGUS_MISC2',
'mmGUS_MISC2_BASE_IDX', 'mmGUS_MISC3', 'mmGUS_MISC3_BASE_IDX',
'mmGUS_MISC_BASE_IDX', 'mmGUS_PERFCOUNTER0_CFG',
'mmGUS_PERFCOUNTER0_CFG_BASE_IDX', 'mmGUS_PERFCOUNTER1_CFG',
'mmGUS_PERFCOUNTER1_CFG_BASE_IDX', 'mmGUS_PERFCOUNTER2_HI',
'mmGUS_PERFCOUNTER2_HI_BASE_IDX', 'mmGUS_PERFCOUNTER2_LO',
'mmGUS_PERFCOUNTER2_LO_BASE_IDX', 'mmGUS_PERFCOUNTER2_MODE',
'mmGUS_PERFCOUNTER2_MODE_BASE_IDX', 'mmGUS_PERFCOUNTER2_SELECT',
'mmGUS_PERFCOUNTER2_SELECT1',
'mmGUS_PERFCOUNTER2_SELECT1_BASE_IDX',
'mmGUS_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGUS_PERFCOUNTER_HI',
'mmGUS_PERFCOUNTER_HI_BASE_IDX', 'mmGUS_PERFCOUNTER_LO',
'mmGUS_PERFCOUNTER_LO_BASE_IDX', 'mmGUS_PERFCOUNTER_RSLT_CNTL',
'mmGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'mmGUS_SDP_ARB_FINAL',
'mmGUS_SDP_ARB_FINAL_BASE_IDX', 'mmGUS_SDP_CREDITS',
'mmGUS_SDP_CREDITS_BASE_IDX', 'mmGUS_SDP_ENABLE',
'mmGUS_SDP_ENABLE_BASE_IDX', 'mmGUS_SDP_QOS_VC_PRIORITY',
'mmGUS_SDP_QOS_VC_PRIORITY_BASE_IDX', 'mmGUS_SDP_REQ_CNTL',
'mmGUS_SDP_REQ_CNTL_BASE_IDX', 'mmGUS_SDP_TAG_RESERVE0',
'mmGUS_SDP_TAG_RESERVE0_BASE_IDX', 'mmGUS_SDP_TAG_RESERVE1',
'mmGUS_SDP_TAG_RESERVE1_BASE_IDX', 'mmGUS_SDP_VCC_RESERVE0',
'mmGUS_SDP_VCC_RESERVE0_BASE_IDX', 'mmGUS_SDP_VCC_RESERVE1',
'mmGUS_SDP_VCC_RESERVE1_BASE_IDX', 'mmGUS_SDP_VCD_RESERVE0',
'mmGUS_SDP_VCD_RESERVE0_BASE_IDX', 'mmGUS_SDP_VCD_RESERVE1',
'mmGUS_SDP_VCD_RESERVE1_BASE_IDX', 'mmGUS_WRRSP_FIFO_CNTL',
'mmGUS_WRRSP_FIFO_CNTL_BASE_IDX', 'mmIA_ENHANCE',
'mmIA_ENHANCE_BASE_IDX', 'mmIA_MULTI_VGT_PARAM',
'mmIA_MULTI_VGT_PARAM_BASE_IDX', 'mmIA_MULTI_VGT_PARAM_PIPED',
'mmIA_MULTI_VGT_PARAM_PIPED_BASE_IDX', 'mmIA_UTCL1_CNTL',
'mmIA_UTCL1_CNTL_BASE_IDX', 'mmIA_UTCL1_STATUS',
'mmIA_UTCL1_STATUS_2', 'mmIA_UTCL1_STATUS_2_BASE_IDX',
'mmIA_UTCL1_STATUS_BASE_IDX', 'mmLDS_CONFIG',
'mmLDS_CONFIG_BASE_IDX', 'mmPA_CL_CLIP_CNTL',
'mmPA_CL_CLIP_CNTL_BASE_IDX', 'mmPA_CL_CNTL_STATUS',
'mmPA_CL_CNTL_STATUS_BASE_IDX', 'mmPA_CL_ENHANCE',
'mmPA_CL_ENHANCE_BASE_IDX', 'mmPA_CL_GB_HORZ_CLIP_ADJ',
'mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX', 'mmPA_CL_GB_HORZ_DISC_ADJ',
'mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX', 'mmPA_CL_GB_VERT_CLIP_ADJ',
'mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX', 'mmPA_CL_GB_VERT_DISC_ADJ',
'mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX', 'mmPA_CL_NANINF_CNTL',
'mmPA_CL_NANINF_CNTL_BASE_IDX', 'mmPA_CL_NGG_CNTL',
'mmPA_CL_NGG_CNTL_BASE_IDX', 'mmPA_CL_POINT_CULL_RAD',
'mmPA_CL_POINT_CULL_RAD_BASE_IDX', 'mmPA_CL_POINT_SIZE',
'mmPA_CL_POINT_SIZE_BASE_IDX', 'mmPA_CL_POINT_X_RAD',
'mmPA_CL_POINT_X_RAD_BASE_IDX', 'mmPA_CL_POINT_Y_RAD',
'mmPA_CL_POINT_Y_RAD_BASE_IDX', 'mmPA_CL_PROG_NEAR_CLIP_Z',
'mmPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX', 'mmPA_CL_UCP_0_W',
'mmPA_CL_UCP_0_W_BASE_IDX', 'mmPA_CL_UCP_0_X',
'mmPA_CL_UCP_0_X_BASE_IDX', 'mmPA_CL_UCP_0_Y',
'mmPA_CL_UCP_0_Y_BASE_IDX', 'mmPA_CL_UCP_0_Z',
'mmPA_CL_UCP_0_Z_BASE_IDX', 'mmPA_CL_UCP_1_W',
'mmPA_CL_UCP_1_W_BASE_IDX', 'mmPA_CL_UCP_1_X',
'mmPA_CL_UCP_1_X_BASE_IDX', 'mmPA_CL_UCP_1_Y',
'mmPA_CL_UCP_1_Y_BASE_IDX', 'mmPA_CL_UCP_1_Z',
'mmPA_CL_UCP_1_Z_BASE_IDX', 'mmPA_CL_UCP_2_W',
'mmPA_CL_UCP_2_W_BASE_IDX', 'mmPA_CL_UCP_2_X',
'mmPA_CL_UCP_2_X_BASE_IDX', 'mmPA_CL_UCP_2_Y',
'mmPA_CL_UCP_2_Y_BASE_IDX', 'mmPA_CL_UCP_2_Z',
'mmPA_CL_UCP_2_Z_BASE_IDX', 'mmPA_CL_UCP_3_W',
'mmPA_CL_UCP_3_W_BASE_IDX', 'mmPA_CL_UCP_3_X',
'mmPA_CL_UCP_3_X_BASE_IDX', 'mmPA_CL_UCP_3_Y',
'mmPA_CL_UCP_3_Y_BASE_IDX', 'mmPA_CL_UCP_3_Z',
'mmPA_CL_UCP_3_Z_BASE_IDX', 'mmPA_CL_UCP_4_W',
'mmPA_CL_UCP_4_W_BASE_IDX', 'mmPA_CL_UCP_4_X',
'mmPA_CL_UCP_4_X_BASE_IDX', 'mmPA_CL_UCP_4_Y',
'mmPA_CL_UCP_4_Y_BASE_IDX', 'mmPA_CL_UCP_4_Z',
'mmPA_CL_UCP_4_Z_BASE_IDX', 'mmPA_CL_UCP_5_W',
'mmPA_CL_UCP_5_W_BASE_IDX', 'mmPA_CL_UCP_5_X',
'mmPA_CL_UCP_5_X_BASE_IDX', 'mmPA_CL_UCP_5_Y',
'mmPA_CL_UCP_5_Y_BASE_IDX', 'mmPA_CL_UCP_5_Z',
'mmPA_CL_UCP_5_Z_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET',
'mmPA_CL_VPORT_XOFFSET_1', 'mmPA_CL_VPORT_XOFFSET_10',
'mmPA_CL_VPORT_XOFFSET_10_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_11',
'mmPA_CL_VPORT_XOFFSET_11_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_12',
'mmPA_CL_VPORT_XOFFSET_12_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_13',
'mmPA_CL_VPORT_XOFFSET_13_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_14',
'mmPA_CL_VPORT_XOFFSET_14_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_15',
'mmPA_CL_VPORT_XOFFSET_15_BASE_IDX',
'mmPA_CL_VPORT_XOFFSET_1_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_2',
'mmPA_CL_VPORT_XOFFSET_2_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_3',
'mmPA_CL_VPORT_XOFFSET_3_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_4',
'mmPA_CL_VPORT_XOFFSET_4_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_5',
'mmPA_CL_VPORT_XOFFSET_5_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_6',
'mmPA_CL_VPORT_XOFFSET_6_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_7',
'mmPA_CL_VPORT_XOFFSET_7_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_8',
'mmPA_CL_VPORT_XOFFSET_8_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_9',
'mmPA_CL_VPORT_XOFFSET_9_BASE_IDX',
'mmPA_CL_VPORT_XOFFSET_BASE_IDX', 'mmPA_CL_VPORT_XSCALE',
'mmPA_CL_VPORT_XSCALE_1', 'mmPA_CL_VPORT_XSCALE_10',
'mmPA_CL_VPORT_XSCALE_10_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_11',
'mmPA_CL_VPORT_XSCALE_11_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_12',
'mmPA_CL_VPORT_XSCALE_12_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_13',
'mmPA_CL_VPORT_XSCALE_13_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_14',
'mmPA_CL_VPORT_XSCALE_14_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_15',
'mmPA_CL_VPORT_XSCALE_15_BASE_IDX',
'mmPA_CL_VPORT_XSCALE_1_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_2',
'mmPA_CL_VPORT_XSCALE_2_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_3',
'mmPA_CL_VPORT_XSCALE_3_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_4',
'mmPA_CL_VPORT_XSCALE_4_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_5',
'mmPA_CL_VPORT_XSCALE_5_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_6',
'mmPA_CL_VPORT_XSCALE_6_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_7',
'mmPA_CL_VPORT_XSCALE_7_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_8',
'mmPA_CL_VPORT_XSCALE_8_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_9',
'mmPA_CL_VPORT_XSCALE_9_BASE_IDX',
'mmPA_CL_VPORT_XSCALE_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET',
'mmPA_CL_VPORT_YOFFSET_1', 'mmPA_CL_VPORT_YOFFSET_10',
'mmPA_CL_VPORT_YOFFSET_10_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_11',
'mmPA_CL_VPORT_YOFFSET_11_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_12',
'mmPA_CL_VPORT_YOFFSET_12_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_13',
'mmPA_CL_VPORT_YOFFSET_13_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_14',
'mmPA_CL_VPORT_YOFFSET_14_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_15',
'mmPA_CL_VPORT_YOFFSET_15_BASE_IDX',
'mmPA_CL_VPORT_YOFFSET_1_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_2',
'mmPA_CL_VPORT_YOFFSET_2_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_3',
'mmPA_CL_VPORT_YOFFSET_3_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_4',
'mmPA_CL_VPORT_YOFFSET_4_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_5',
'mmPA_CL_VPORT_YOFFSET_5_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_6',
'mmPA_CL_VPORT_YOFFSET_6_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_7',
'mmPA_CL_VPORT_YOFFSET_7_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_8',
'mmPA_CL_VPORT_YOFFSET_8_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_9',
'mmPA_CL_VPORT_YOFFSET_9_BASE_IDX',
'mmPA_CL_VPORT_YOFFSET_BASE_IDX', 'mmPA_CL_VPORT_YSCALE',
'mmPA_CL_VPORT_YSCALE_1', 'mmPA_CL_VPORT_YSCALE_10',
'mmPA_CL_VPORT_YSCALE_10_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_11',
'mmPA_CL_VPORT_YSCALE_11_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_12',
'mmPA_CL_VPORT_YSCALE_12_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_13',
'mmPA_CL_VPORT_YSCALE_13_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_14',
'mmPA_CL_VPORT_YSCALE_14_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_15',
'mmPA_CL_VPORT_YSCALE_15_BASE_IDX',
'mmPA_CL_VPORT_YSCALE_1_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_2',
'mmPA_CL_VPORT_YSCALE_2_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_3',
'mmPA_CL_VPORT_YSCALE_3_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_4',
'mmPA_CL_VPORT_YSCALE_4_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_5',
'mmPA_CL_VPORT_YSCALE_5_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_6',
'mmPA_CL_VPORT_YSCALE_6_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_7',
'mmPA_CL_VPORT_YSCALE_7_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_8',
'mmPA_CL_VPORT_YSCALE_8_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_9',
'mmPA_CL_VPORT_YSCALE_9_BASE_IDX',
'mmPA_CL_VPORT_YSCALE_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET',
'mmPA_CL_VPORT_ZOFFSET_1', 'mmPA_CL_VPORT_ZOFFSET_10',
'mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_11',
'mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_12',
'mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_13',
'mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_14',
'mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_15',
'mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX',
'mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_2',
'mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_3',
'mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_4',
'mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_5',
'mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_6',
'mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_7',
'mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_8',
'mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_9',
'mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX',
'mmPA_CL_VPORT_ZOFFSET_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE',
'mmPA_CL_VPORT_ZSCALE_1', 'mmPA_CL_VPORT_ZSCALE_10',
'mmPA_CL_VPORT_ZSCALE_10_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_11',
'mmPA_CL_VPORT_ZSCALE_11_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_12',
'mmPA_CL_VPORT_ZSCALE_12_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_13',
'mmPA_CL_VPORT_ZSCALE_13_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_14',
'mmPA_CL_VPORT_ZSCALE_14_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_15',
'mmPA_CL_VPORT_ZSCALE_15_BASE_IDX',
'mmPA_CL_VPORT_ZSCALE_1_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_2',
'mmPA_CL_VPORT_ZSCALE_2_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_3',
'mmPA_CL_VPORT_ZSCALE_3_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_4',
'mmPA_CL_VPORT_ZSCALE_4_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_5',
'mmPA_CL_VPORT_ZSCALE_5_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_6',
'mmPA_CL_VPORT_ZSCALE_6_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_7',
'mmPA_CL_VPORT_ZSCALE_7_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_8',
'mmPA_CL_VPORT_ZSCALE_8_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_9',
'mmPA_CL_VPORT_ZSCALE_9_BASE_IDX',
'mmPA_CL_VPORT_ZSCALE_BASE_IDX', 'mmPA_CL_VRS_CNTL',
'mmPA_CL_VRS_CNTL_BASE_IDX', 'mmPA_CL_VS_OUT_CNTL',
'mmPA_CL_VS_OUT_CNTL_BASE_IDX', 'mmPA_CL_VTE_CNTL',
'mmPA_CL_VTE_CNTL_BASE_IDX', 'mmPA_PH_ENHANCE',
'mmPA_PH_ENHANCE_BASE_IDX', 'mmPA_PH_INTERFACE_FIFO_SIZE',
'mmPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX', 'mmPA_PH_PERFCOUNTER0_HI',
'mmPA_PH_PERFCOUNTER0_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER0_LO',
'mmPA_PH_PERFCOUNTER0_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER0_SELECT',
'mmPA_PH_PERFCOUNTER0_SELECT1',
'mmPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmPA_PH_PERFCOUNTER0_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER1_HI',
'mmPA_PH_PERFCOUNTER1_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER1_LO',
'mmPA_PH_PERFCOUNTER1_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER1_SELECT',
'mmPA_PH_PERFCOUNTER1_SELECT1',
'mmPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmPA_PH_PERFCOUNTER1_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER2_HI',
'mmPA_PH_PERFCOUNTER2_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER2_LO',
'mmPA_PH_PERFCOUNTER2_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER2_SELECT',
'mmPA_PH_PERFCOUNTER2_SELECT1',
'mmPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX',
'mmPA_PH_PERFCOUNTER2_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER3_HI',
'mmPA_PH_PERFCOUNTER3_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER3_LO',
'mmPA_PH_PERFCOUNTER3_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER3_SELECT',
'mmPA_PH_PERFCOUNTER3_SELECT1',
'mmPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX',
'mmPA_PH_PERFCOUNTER3_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER4_HI',
'mmPA_PH_PERFCOUNTER4_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER4_LO',
'mmPA_PH_PERFCOUNTER4_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER4_SELECT',
'mmPA_PH_PERFCOUNTER4_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER5_HI',
'mmPA_PH_PERFCOUNTER5_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER5_LO',
'mmPA_PH_PERFCOUNTER5_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER5_SELECT',
'mmPA_PH_PERFCOUNTER5_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER6_HI',
'mmPA_PH_PERFCOUNTER6_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER6_LO',
'mmPA_PH_PERFCOUNTER6_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER6_SELECT',
'mmPA_PH_PERFCOUNTER6_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER7_HI',
'mmPA_PH_PERFCOUNTER7_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER7_LO',
'mmPA_PH_PERFCOUNTER7_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER7_SELECT',
'mmPA_PH_PERFCOUNTER7_SELECT_BASE_IDX', 'mmPA_SC_AA_CONFIG',
'mmPA_SC_AA_CONFIG_BASE_IDX', 'mmPA_SC_AA_MASK_X0Y0_X1Y0',
'mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX', 'mmPA_SC_AA_MASK_X0Y1_X1Y1',
'mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3',
'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX',
'mmPA_SC_BC_WAVE_BREAK', 'mmPA_SC_BC_WAVE_BREAK_BASE_IDX',
'mmPA_SC_BINNER_CNTL_0', 'mmPA_SC_BINNER_CNTL_0_BASE_IDX',
'mmPA_SC_BINNER_CNTL_1', 'mmPA_SC_BINNER_CNTL_1_BASE_IDX',
'mmPA_SC_BINNER_CNTL_OVERRIDE',
'mmPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX',
'mmPA_SC_BINNER_EVENT_CNTL_0',
'mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX',
'mmPA_SC_BINNER_EVENT_CNTL_1',
'mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX',
'mmPA_SC_BINNER_EVENT_CNTL_2',
'mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX',
'mmPA_SC_BINNER_EVENT_CNTL_3',
'mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX',
'mmPA_SC_BINNER_PERF_CNTL_0',
'mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX',
'mmPA_SC_BINNER_PERF_CNTL_1',
'mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX',
'mmPA_SC_BINNER_PERF_CNTL_2',
'mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX',
'mmPA_SC_BINNER_PERF_CNTL_3',
'mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX',
'mmPA_SC_BINNER_TIMEOUT_COUNTER',
'mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX',
'mmPA_SC_CENTROID_PRIORITY_0',
'mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX',
'mmPA_SC_CENTROID_PRIORITY_1',
'mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX', 'mmPA_SC_CLIPRECT_0_BR',
'mmPA_SC_CLIPRECT_0_BR_BASE_IDX', 'mmPA_SC_CLIPRECT_0_TL',
'mmPA_SC_CLIPRECT_0_TL_BASE_IDX', 'mmPA_SC_CLIPRECT_1_BR',
'mmPA_SC_CLIPRECT_1_BR_BASE_IDX', 'mmPA_SC_CLIPRECT_1_TL',
'mmPA_SC_CLIPRECT_1_TL_BASE_IDX', 'mmPA_SC_CLIPRECT_2_BR',
'mmPA_SC_CLIPRECT_2_BR_BASE_IDX', 'mmPA_SC_CLIPRECT_2_TL',
'mmPA_SC_CLIPRECT_2_TL_BASE_IDX', 'mmPA_SC_CLIPRECT_3_BR',
'mmPA_SC_CLIPRECT_3_BR_BASE_IDX', 'mmPA_SC_CLIPRECT_3_TL',
'mmPA_SC_CLIPRECT_3_TL_BASE_IDX', 'mmPA_SC_CLIPRECT_RULE',
'mmPA_SC_CLIPRECT_RULE_BASE_IDX',
'mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL',
'mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX',
'mmPA_SC_DSM_CNTL', 'mmPA_SC_DSM_CNTL_BASE_IDX',
'mmPA_SC_EDGERULE', 'mmPA_SC_EDGERULE_BASE_IDX',
'mmPA_SC_ENHANCE', 'mmPA_SC_ENHANCE_1',
'mmPA_SC_ENHANCE_1_BASE_IDX', 'mmPA_SC_ENHANCE_2',
'mmPA_SC_ENHANCE_2_BASE_IDX', 'mmPA_SC_ENHANCE_3',
'mmPA_SC_ENHANCE_3_BASE_IDX', 'mmPA_SC_ENHANCE_BASE_IDX',
'mmPA_SC_ENHANCE_INTERNAL', 'mmPA_SC_ENHANCE_INTERNAL_BASE_IDX',
'mmPA_SC_FIFO_DEPTH_CNTL', 'mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX',
'mmPA_SC_FIFO_SIZE', 'mmPA_SC_FIFO_SIZE_BASE_IDX',
'mmPA_SC_FORCE_EOV_MAX_CNTS',
'mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX',
'mmPA_SC_GENERIC_SCISSOR_BR',
'mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX',
'mmPA_SC_GENERIC_SCISSOR_TL',
'mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX',
'mmPA_SC_HP3D_TRAP_SCREEN_COUNT',
'mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX',
'mmPA_SC_HP3D_TRAP_SCREEN_H', 'mmPA_SC_HP3D_TRAP_SCREEN_HV_EN',
'mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX',
'mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK',
'mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX',
'mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX',
'mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE',
'mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX',
'mmPA_SC_HP3D_TRAP_SCREEN_V',
'mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX', 'mmPA_SC_IF_FIFO_SIZE',
'mmPA_SC_IF_FIFO_SIZE_BASE_IDX', 'mmPA_SC_LINE_CNTL',
'mmPA_SC_LINE_CNTL_BASE_IDX', 'mmPA_SC_LINE_STIPPLE',
'mmPA_SC_LINE_STIPPLE_BASE_IDX', 'mmPA_SC_LINE_STIPPLE_STATE',
'mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX', 'mmPA_SC_MODE_CNTL_0',
'mmPA_SC_MODE_CNTL_0_BASE_IDX', 'mmPA_SC_MODE_CNTL_1',
'mmPA_SC_MODE_CNTL_1_BASE_IDX', 'mmPA_SC_NGG_MODE_CNTL',
'mmPA_SC_NGG_MODE_CNTL_BASE_IDX', 'mmPA_SC_P3D_TRAP_SCREEN_COUNT',
'mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX',
'mmPA_SC_P3D_TRAP_SCREEN_H', 'mmPA_SC_P3D_TRAP_SCREEN_HV_EN',
'mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX',
'mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK',
'mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX',
'mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX',
'mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE',
'mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX',
'mmPA_SC_P3D_TRAP_SCREEN_V', 'mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX',
'mmPA_SC_PBB_OVERRIDE_FLAG', 'mmPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX',
'mmPA_SC_PERFCOUNTER0_HI', 'mmPA_SC_PERFCOUNTER0_HI_BASE_IDX',
'mmPA_SC_PERFCOUNTER0_LO', 'mmPA_SC_PERFCOUNTER0_LO_BASE_IDX',
'mmPA_SC_PERFCOUNTER0_SELECT', 'mmPA_SC_PERFCOUNTER0_SELECT1',
'mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER1_HI',
'mmPA_SC_PERFCOUNTER1_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER1_LO',
'mmPA_SC_PERFCOUNTER1_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER1_SELECT',
'mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER2_HI',
'mmPA_SC_PERFCOUNTER2_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER2_LO',
'mmPA_SC_PERFCOUNTER2_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER2_SELECT',
'mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER3_HI',
'mmPA_SC_PERFCOUNTER3_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER3_LO',
'mmPA_SC_PERFCOUNTER3_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER3_SELECT',
'mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER4_HI',
'mmPA_SC_PERFCOUNTER4_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER4_LO',
'mmPA_SC_PERFCOUNTER4_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER4_SELECT',
'mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER5_HI',
'mmPA_SC_PERFCOUNTER5_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER5_LO',
'mmPA_SC_PERFCOUNTER5_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER5_SELECT',
'mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER6_HI',
'mmPA_SC_PERFCOUNTER6_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER6_LO',
'mmPA_SC_PERFCOUNTER6_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER6_SELECT',
'mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER7_HI',
'mmPA_SC_PERFCOUNTER7_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER7_LO',
'mmPA_SC_PERFCOUNTER7_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER7_SELECT',
'mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX',
'mmPA_SC_PKR_WAVE_TABLE_CNTL',
'mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX', 'mmPA_SC_RASTER_CONFIG',
'mmPA_SC_RASTER_CONFIG_1', 'mmPA_SC_RASTER_CONFIG_1_BASE_IDX',
'mmPA_SC_RASTER_CONFIG_BASE_IDX', 'mmPA_SC_SCREEN_EXTENT_CONTROL',
'mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX',
'mmPA_SC_SCREEN_EXTENT_MAX_0',
'mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX',
'mmPA_SC_SCREEN_EXTENT_MAX_1',
'mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX',
'mmPA_SC_SCREEN_EXTENT_MIN_0',
'mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX',
'mmPA_SC_SCREEN_EXTENT_MIN_1',
'mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX',
'mmPA_SC_SCREEN_SCISSOR_BR', 'mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX',
'mmPA_SC_SCREEN_SCISSOR_TL', 'mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX',
'mmPA_SC_SHADER_CONTROL', 'mmPA_SC_SHADER_CONTROL_BASE_IDX',
'mmPA_SC_TILE_STEERING_CREST_OVERRIDE',
'mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX',
'mmPA_SC_TILE_STEERING_OVERRIDE',
'mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX',
'mmPA_SC_TRAP_SCREEN_COUNT', 'mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX',
'mmPA_SC_TRAP_SCREEN_H', 'mmPA_SC_TRAP_SCREEN_HV_EN',
'mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX',
'mmPA_SC_TRAP_SCREEN_HV_LOCK',
'mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX',
'mmPA_SC_TRAP_SCREEN_H_BASE_IDX',
'mmPA_SC_TRAP_SCREEN_OCCURRENCE',
'mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX',
'mmPA_SC_TRAP_SCREEN_V', 'mmPA_SC_TRAP_SCREEN_V_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_0_BR',
'mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_0_TL',
'mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_10_BR',
'mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_10_TL',
'mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_11_BR',
'mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_11_TL',
'mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_12_BR',
'mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_12_TL',
'mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_13_BR',
'mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_13_TL',
'mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_14_BR',
'mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_14_TL',
'mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_15_BR',
'mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_15_TL',
'mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_1_BR',
'mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_1_TL',
'mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_2_BR',
'mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_2_TL',
'mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_3_BR',
'mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_3_TL',
'mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_4_BR',
'mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_4_TL',
'mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_5_BR',
'mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_5_TL',
'mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_6_BR',
'mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_6_TL',
'mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_7_BR',
'mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_7_TL',
'mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_8_BR',
'mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_8_TL',
'mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_9_BR',
'mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX',
'mmPA_SC_VPORT_SCISSOR_9_TL',
'mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_0',
'mmPA_SC_VPORT_ZMAX_0_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_1',
'mmPA_SC_VPORT_ZMAX_10', 'mmPA_SC_VPORT_ZMAX_10_BASE_IDX',
'mmPA_SC_VPORT_ZMAX_11', 'mmPA_SC_VPORT_ZMAX_11_BASE_IDX',
'mmPA_SC_VPORT_ZMAX_12', 'mmPA_SC_VPORT_ZMAX_12_BASE_IDX',
'mmPA_SC_VPORT_ZMAX_13', 'mmPA_SC_VPORT_ZMAX_13_BASE_IDX',
'mmPA_SC_VPORT_ZMAX_14', 'mmPA_SC_VPORT_ZMAX_14_BASE_IDX',
'mmPA_SC_VPORT_ZMAX_15', 'mmPA_SC_VPORT_ZMAX_15_BASE_IDX',
'mmPA_SC_VPORT_ZMAX_1_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_2',
'mmPA_SC_VPORT_ZMAX_2_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_3',
'mmPA_SC_VPORT_ZMAX_3_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_4',
'mmPA_SC_VPORT_ZMAX_4_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_5',
'mmPA_SC_VPORT_ZMAX_5_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_6',
'mmPA_SC_VPORT_ZMAX_6_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_7',
'mmPA_SC_VPORT_ZMAX_7_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_8',
'mmPA_SC_VPORT_ZMAX_8_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_9',
'mmPA_SC_VPORT_ZMAX_9_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_0',
'mmPA_SC_VPORT_ZMIN_0_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_1',
'mmPA_SC_VPORT_ZMIN_10', 'mmPA_SC_VPORT_ZMIN_10_BASE_IDX',
'mmPA_SC_VPORT_ZMIN_11', 'mmPA_SC_VPORT_ZMIN_11_BASE_IDX',
'mmPA_SC_VPORT_ZMIN_12', 'mmPA_SC_VPORT_ZMIN_12_BASE_IDX',
'mmPA_SC_VPORT_ZMIN_13', 'mmPA_SC_VPORT_ZMIN_13_BASE_IDX',
'mmPA_SC_VPORT_ZMIN_14', 'mmPA_SC_VPORT_ZMIN_14_BASE_IDX',
'mmPA_SC_VPORT_ZMIN_15', 'mmPA_SC_VPORT_ZMIN_15_BASE_IDX',
'mmPA_SC_VPORT_ZMIN_1_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_2',
'mmPA_SC_VPORT_ZMIN_2_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_3',
'mmPA_SC_VPORT_ZMIN_3_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_4',
'mmPA_SC_VPORT_ZMIN_4_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_5',
'mmPA_SC_VPORT_ZMIN_5_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_6',
'mmPA_SC_VPORT_ZMIN_6_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_7',
'mmPA_SC_VPORT_ZMIN_7_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_8',
'mmPA_SC_VPORT_ZMIN_8_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_9',
'mmPA_SC_VPORT_ZMIN_9_BASE_IDX', 'mmPA_SC_WINDOW_OFFSET',
'mmPA_SC_WINDOW_OFFSET_BASE_IDX', 'mmPA_SC_WINDOW_SCISSOR_BR',
'mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX', 'mmPA_SC_WINDOW_SCISSOR_TL',
'mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX',
'mmPA_SIDEBAND_REQUEST_DELAYS',
'mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX', 'mmPA_STATE_STEREO_X',
'mmPA_STATE_STEREO_X_BASE_IDX', 'mmPA_STEREO_CNTL',
'mmPA_STEREO_CNTL_BASE_IDX', 'mmPA_SU_CNTL_STATUS',
'mmPA_SU_CNTL_STATUS_BASE_IDX', 'mmPA_SU_HARDWARE_SCREEN_OFFSET',
'mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX', 'mmPA_SU_LINE_CNTL',
'mmPA_SU_LINE_CNTL_BASE_IDX', 'mmPA_SU_LINE_STIPPLE_CNTL',
'mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX',
'mmPA_SU_LINE_STIPPLE_SCALE',
'mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX',
'mmPA_SU_LINE_STIPPLE_VALUE',
'mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX',
'mmPA_SU_OVER_RASTERIZATION_CNTL',
'mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX',
'mmPA_SU_PERFCOUNTER0_HI', 'mmPA_SU_PERFCOUNTER0_HI_BASE_IDX',
'mmPA_SU_PERFCOUNTER0_LO', 'mmPA_SU_PERFCOUNTER0_LO_BASE_IDX',
'mmPA_SU_PERFCOUNTER0_SELECT', 'mmPA_SU_PERFCOUNTER0_SELECT1',
'mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX', 'mmPA_SU_PERFCOUNTER1_HI',
'mmPA_SU_PERFCOUNTER1_HI_BASE_IDX', 'mmPA_SU_PERFCOUNTER1_LO',
'mmPA_SU_PERFCOUNTER1_LO_BASE_IDX', 'mmPA_SU_PERFCOUNTER1_SELECT',
'mmPA_SU_PERFCOUNTER1_SELECT1',
'mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX', 'mmPA_SU_PERFCOUNTER2_HI',
'mmPA_SU_PERFCOUNTER2_HI_BASE_IDX', 'mmPA_SU_PERFCOUNTER2_LO',
'mmPA_SU_PERFCOUNTER2_LO_BASE_IDX', 'mmPA_SU_PERFCOUNTER2_SELECT',
'mmPA_SU_PERFCOUNTER2_SELECT1',
'mmPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX',
'mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX', 'mmPA_SU_PERFCOUNTER3_HI',
'mmPA_SU_PERFCOUNTER3_HI_BASE_IDX', 'mmPA_SU_PERFCOUNTER3_LO',
'mmPA_SU_PERFCOUNTER3_LO_BASE_IDX', 'mmPA_SU_PERFCOUNTER3_SELECT',
'mmPA_SU_PERFCOUNTER3_SELECT1',
'mmPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX',
'mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX', 'mmPA_SU_POINT_MINMAX',
'mmPA_SU_POINT_MINMAX_BASE_IDX', 'mmPA_SU_POINT_SIZE',
'mmPA_SU_POINT_SIZE_BASE_IDX', 'mmPA_SU_POLY_OFFSET_BACK_OFFSET',
'mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX',
'mmPA_SU_POLY_OFFSET_BACK_SCALE',
'mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX',
'mmPA_SU_POLY_OFFSET_CLAMP', 'mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX',
'mmPA_SU_POLY_OFFSET_DB_FMT_CNTL',
'mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX',
'mmPA_SU_POLY_OFFSET_FRONT_OFFSET',
'mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX',
'mmPA_SU_POLY_OFFSET_FRONT_SCALE',
'mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX',
'mmPA_SU_PRIM_FILTER_CNTL', 'mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX',
'mmPA_SU_SC_MODE_CNTL', 'mmPA_SU_SC_MODE_CNTL_BASE_IDX',
'mmPA_SU_SMALL_PRIM_FILTER_CNTL',
'mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX', 'mmPA_SU_VTX_CNTL',
'mmPA_SU_VTX_CNTL_BASE_IDX', 'mmPCC_PERF_COUNTER',
'mmPCC_PERF_COUNTER_BASE_IDX', 'mmPMM_GENERAL_CNTL',
'mmPMM_GENERAL_CNTL_BASE_IDX', 'mmPWRBRK_PERF_COUNTER',
'mmPWRBRK_PERF_COUNTER_BASE_IDX', 'mmRLC_AUTO_PG_CTRL',
'mmRLC_AUTO_PG_CTRL_BASE_IDX', 'mmRLC_BUSY_CLK_CNTL',
'mmRLC_BUSY_CLK_CNTL_BASE_IDX', 'mmRLC_CAC_MASK_CNTL',
'mmRLC_CAC_MASK_CNTL_BASE_IDX', 'mmRLC_CAPTURE_GPU_CLOCK_COUNT',
'mmRLC_CAPTURE_GPU_CLOCK_COUNT_1',
'mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX',
'mmRLC_CAPTURE_GPU_CLOCK_COUNT_2',
'mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX',
'mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX', 'mmRLC_CGCG_CGLS_CTRL',
'mmRLC_CGCG_CGLS_CTRL_3D', 'mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX',
'mmRLC_CGCG_CGLS_CTRL_BASE_IDX', 'mmRLC_CGCG_RAMP_CTRL',
'mmRLC_CGCG_RAMP_CTRL_3D', 'mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX',
'mmRLC_CGCG_RAMP_CTRL_BASE_IDX', 'mmRLC_CGTT_MGCG_OVERRIDE',
'mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX', 'mmRLC_CLK_CNTL',
'mmRLC_CLK_CNTL_BASE_IDX', 'mmRLC_CLK_COUNT_CTRL',
'mmRLC_CLK_COUNT_CTRL_BASE_IDX', 'mmRLC_CLK_COUNT_GFXCLK_LSB',
'mmRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX',
'mmRLC_CLK_COUNT_GFXCLK_MSB',
'mmRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX',
'mmRLC_CLK_COUNT_REFCLK_LSB',
'mmRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX',
'mmRLC_CLK_COUNT_REFCLK_MSB',
'mmRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX', 'mmRLC_CLK_COUNT_STAT',
'mmRLC_CLK_COUNT_STAT_BASE_IDX', 'mmRLC_CLK_STATUS',
'mmRLC_CLK_STATUS_BASE_IDX', 'mmRLC_CNTL', 'mmRLC_CNTL_BASE_IDX',
'mmRLC_CPAXI_DOORBELL_MON_CTRL',
'mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX',
'mmRLC_CPAXI_DOORBELL_MON_DATA_LSB',
'mmRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX',
'mmRLC_CPAXI_DOORBELL_MON_DATA_MSB',
'mmRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX',
'mmRLC_CPAXI_DOORBELL_MON_STAT',
'mmRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX', 'mmRLC_CP_EOF_INT',
'mmRLC_CP_EOF_INT_BASE_IDX', 'mmRLC_CP_EOF_INT_CNT',
'mmRLC_CP_EOF_INT_CNT_BASE_IDX', 'mmRLC_CP_SCHEDULERS',
'mmRLC_CP_SCHEDULERS_BASE_IDX', 'mmRLC_CP_STAT_INVAL_CTRL',
'mmRLC_CP_STAT_INVAL_CTRL_BASE_IDX', 'mmRLC_CP_STAT_INVAL_STAT',
'mmRLC_CP_STAT_INVAL_STAT_BASE_IDX', 'mmRLC_CSIB_ADDR_HI',
'mmRLC_CSIB_ADDR_HI_BASE_IDX', 'mmRLC_CSIB_ADDR_LO',
'mmRLC_CSIB_ADDR_LO_BASE_IDX', 'mmRLC_CSIB_LENGTH',
'mmRLC_CSIB_LENGTH_BASE_IDX', 'mmRLC_DYN_PG_REQUEST',
'mmRLC_DYN_PG_REQUEST_BASE_IDX', 'mmRLC_DYN_PG_STATUS',
'mmRLC_DYN_PG_STATUS_BASE_IDX', 'mmRLC_F32_UCODE_VERSION',
'mmRLC_F32_UCODE_VERSION_BASE_IDX', 'mmRLC_FWL_FIRST_VIOL_ADDR',
'mmRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX', 'mmRLC_GFX_RM_CNTL',
'mmRLC_GFX_RM_CNTL_BASE_IDX', 'mmRLC_GPM_CP_DMA_COMPLETE_T0',
'mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX',
'mmRLC_GPM_CP_DMA_COMPLETE_T1',
'mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX', 'mmRLC_GPM_GENERAL_0',
'mmRLC_GPM_GENERAL_0_BASE_IDX', 'mmRLC_GPM_GENERAL_1',
'mmRLC_GPM_GENERAL_10', 'mmRLC_GPM_GENERAL_10_BASE_IDX',
'mmRLC_GPM_GENERAL_11', 'mmRLC_GPM_GENERAL_11_BASE_IDX',
'mmRLC_GPM_GENERAL_12', 'mmRLC_GPM_GENERAL_12_BASE_IDX',
'mmRLC_GPM_GENERAL_13', 'mmRLC_GPM_GENERAL_13_BASE_IDX',
'mmRLC_GPM_GENERAL_14', 'mmRLC_GPM_GENERAL_14_BASE_IDX',
'mmRLC_GPM_GENERAL_15', 'mmRLC_GPM_GENERAL_15_BASE_IDX',
'mmRLC_GPM_GENERAL_16', 'mmRLC_GPM_GENERAL_16_BASE_IDX',
'mmRLC_GPM_GENERAL_1_BASE_IDX', 'mmRLC_GPM_GENERAL_2',
'mmRLC_GPM_GENERAL_2_BASE_IDX', 'mmRLC_GPM_GENERAL_3',
'mmRLC_GPM_GENERAL_3_BASE_IDX', 'mmRLC_GPM_GENERAL_4',
'mmRLC_GPM_GENERAL_4_BASE_IDX', 'mmRLC_GPM_GENERAL_5',
'mmRLC_GPM_GENERAL_5_BASE_IDX', 'mmRLC_GPM_GENERAL_6',
'mmRLC_GPM_GENERAL_6_BASE_IDX', 'mmRLC_GPM_GENERAL_7',
'mmRLC_GPM_GENERAL_7_BASE_IDX', 'mmRLC_GPM_GENERAL_8',
'mmRLC_GPM_GENERAL_8_BASE_IDX', 'mmRLC_GPM_GENERAL_9',
'mmRLC_GPM_GENERAL_9_BASE_IDX', 'mmRLC_GPM_INT_DISABLE_TH0',
'mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX', 'mmRLC_GPM_INT_FORCE_TH0',
'mmRLC_GPM_INT_FORCE_TH0_BASE_IDX', 'mmRLC_GPM_INT_STAT_TH0',
'mmRLC_GPM_INT_STAT_TH0_BASE_IDX', 'mmRLC_GPM_IRAM_ADDR',
'mmRLC_GPM_IRAM_ADDR_BASE_IDX', 'mmRLC_GPM_IRAM_DATA',
'mmRLC_GPM_IRAM_DATA_BASE_IDX', 'mmRLC_GPM_LEGACY_INT_CLEAR',
'mmRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX',
'mmRLC_GPM_LEGACY_INT_DISABLE',
'mmRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX',
'mmRLC_GPM_LEGACY_INT_STAT', 'mmRLC_GPM_LEGACY_INT_STAT_BASE_IDX',
'mmRLC_GPM_LOG_CONT', 'mmRLC_GPM_LOG_CONT_BASE_IDX',
'mmRLC_GPM_LOG_SIZE', 'mmRLC_GPM_LOG_SIZE_BASE_IDX',
'mmRLC_GPM_PERF_COUNT_0', 'mmRLC_GPM_PERF_COUNT_0_BASE_IDX',
'mmRLC_GPM_PERF_COUNT_1', 'mmRLC_GPM_PERF_COUNT_1_BASE_IDX',
'mmRLC_GPM_SCRATCH_ADDR', 'mmRLC_GPM_SCRATCH_ADDR_BASE_IDX',
'mmRLC_GPM_SCRATCH_DATA', 'mmRLC_GPM_SCRATCH_DATA_BASE_IDX',
'mmRLC_GPM_STAT', 'mmRLC_GPM_STAT_BASE_IDX',
'mmRLC_GPM_THREAD_ENABLE', 'mmRLC_GPM_THREAD_ENABLE_BASE_IDX',
'mmRLC_GPM_THREAD_PRIORITY', 'mmRLC_GPM_THREAD_PRIORITY_BASE_IDX',
'mmRLC_GPM_THREAD_RESET', 'mmRLC_GPM_THREAD_RESET_BASE_IDX',
'mmRLC_GPM_TIMER_CTRL', 'mmRLC_GPM_TIMER_CTRL_BASE_IDX',
'mmRLC_GPM_TIMER_INT_0', 'mmRLC_GPM_TIMER_INT_0_BASE_IDX',
'mmRLC_GPM_TIMER_INT_1', 'mmRLC_GPM_TIMER_INT_1_BASE_IDX',
'mmRLC_GPM_TIMER_INT_2', 'mmRLC_GPM_TIMER_INT_2_BASE_IDX',
'mmRLC_GPM_TIMER_INT_3', 'mmRLC_GPM_TIMER_INT_3_BASE_IDX',
'mmRLC_GPM_TIMER_INT_4', 'mmRLC_GPM_TIMER_INT_4_BASE_IDX',
'mmRLC_GPM_TIMER_STAT', 'mmRLC_GPM_TIMER_STAT_BASE_IDX',
'mmRLC_GPM_UCODE_ADDR', 'mmRLC_GPM_UCODE_ADDR_BASE_IDX',
'mmRLC_GPM_UCODE_DATA', 'mmRLC_GPM_UCODE_DATA_BASE_IDX',
'mmRLC_GPM_UTCL1_CNTL_0', 'mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX',
'mmRLC_GPM_UTCL1_CNTL_1', 'mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX',
'mmRLC_GPM_UTCL1_CNTL_2', 'mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX',
'mmRLC_GPM_UTCL1_TH0_ERROR_1',
'mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX',
'mmRLC_GPM_UTCL1_TH0_ERROR_2',
'mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX',
'mmRLC_GPM_UTCL1_TH1_ERROR_1',
'mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX',
'mmRLC_GPM_UTCL1_TH1_ERROR_2',
'mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX',
'mmRLC_GPM_UTCL1_TH2_ERROR_1',
'mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX',
'mmRLC_GPM_UTCL1_TH2_ERROR_2',
'mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX', 'mmRLC_GPR_REG1',
'mmRLC_GPR_REG1_BASE_IDX', 'mmRLC_GPR_REG2',
'mmRLC_GPR_REG2_BASE_IDX', 'mmRLC_GPU_CLOCK_32',
'mmRLC_GPU_CLOCK_32_BASE_IDX', 'mmRLC_GPU_CLOCK_32_RES_SEL',
'mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX',
'mmRLC_GPU_CLOCK_COUNT_LSB', 'mmRLC_GPU_CLOCK_COUNT_LSB_1',
'mmRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX',
'mmRLC_GPU_CLOCK_COUNT_LSB_2',
'mmRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX',
'mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX', 'mmRLC_GPU_CLOCK_COUNT_MSB',
'mmRLC_GPU_CLOCK_COUNT_MSB_1',
'mmRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX',
'mmRLC_GPU_CLOCK_COUNT_MSB_2',
'mmRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX',
'mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX',
'mmRLC_GPU_CLOCK_COUNT_SPM_LSB',
'mmRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX',
'mmRLC_GPU_CLOCK_COUNT_SPM_MSB',
'mmRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX',
'mmRLC_GPU_IOV_ACTIVE_FCN_ID',
'mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX', 'mmRLC_GPU_IOV_CFG_REG1',
'mmRLC_GPU_IOV_CFG_REG1_BASE_IDX', 'mmRLC_GPU_IOV_CFG_REG2',
'mmRLC_GPU_IOV_CFG_REG2_BASE_IDX', 'mmRLC_GPU_IOV_CFG_REG6',
'mmRLC_GPU_IOV_CFG_REG6_BASE_IDX', 'mmRLC_GPU_IOV_CFG_REG8',
'mmRLC_GPU_IOV_CFG_REG8_BASE_IDX', 'mmRLC_GPU_IOV_F32_CNTL',
'mmRLC_GPU_IOV_F32_CNTL_BASE_IDX', 'mmRLC_GPU_IOV_F32_RESET',
'mmRLC_GPU_IOV_F32_RESET_BASE_IDX', 'mmRLC_GPU_IOV_INT_DISABLE',
'mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX', 'mmRLC_GPU_IOV_INT_FORCE',
'mmRLC_GPU_IOV_INT_FORCE_BASE_IDX', 'mmRLC_GPU_IOV_INT_STAT',
'mmRLC_GPU_IOV_INT_STAT_BASE_IDX', 'mmRLC_GPU_IOV_PERF_CNT_CNTL',
'mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX',
'mmRLC_GPU_IOV_PERF_CNT_RD_ADDR',
'mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX',
'mmRLC_GPU_IOV_PERF_CNT_RD_DATA',
'mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX',
'mmRLC_GPU_IOV_PERF_CNT_WR_ADDR',
'mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX',
'mmRLC_GPU_IOV_PERF_CNT_WR_DATA',
'mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX',
'mmRLC_GPU_IOV_RLC_RESPONSE',
'mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX', 'mmRLC_GPU_IOV_SCH_0',
'mmRLC_GPU_IOV_SCH_0_BASE_IDX', 'mmRLC_GPU_IOV_SCH_1',
'mmRLC_GPU_IOV_SCH_1_BASE_IDX', 'mmRLC_GPU_IOV_SCH_2',
'mmRLC_GPU_IOV_SCH_2_BASE_IDX', 'mmRLC_GPU_IOV_SCH_3',
'mmRLC_GPU_IOV_SCH_3_BASE_IDX', 'mmRLC_GPU_IOV_SCH_BLOCK',
'mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX', 'mmRLC_GPU_IOV_SCRATCH_ADDR',
'mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX',
'mmRLC_GPU_IOV_SCRATCH_DATA',
'mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX',
'mmRLC_GPU_IOV_SDMA0_BUSY_STATUS',
'mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA0_STATUS',
'mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA1_BUSY_STATUS',
'mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA1_STATUS',
'mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA2_BUSY_STATUS',
'mmRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA2_STATUS',
'mmRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA3_BUSY_STATUS',
'mmRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA3_STATUS',
'mmRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA4_BUSY_STATUS',
'mmRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA4_STATUS',
'mmRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA5_BUSY_STATUS',
'mmRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA5_STATUS',
'mmRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA6_BUSY_STATUS',
'mmRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA6_STATUS',
'mmRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA7_BUSY_STATUS',
'mmRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SDMA7_STATUS',
'mmRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_SMU_RESPONSE',
'mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX', 'mmRLC_GPU_IOV_UCODE_ADDR',
'mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX', 'mmRLC_GPU_IOV_UCODE_DATA',
'mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX',
'mmRLC_GPU_IOV_VF_DOORBELL_STATUS',
'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX',
'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR',
'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX',
'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET',
'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX',
'mmRLC_GPU_IOV_VF_ENABLE', 'mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX',
'mmRLC_GPU_IOV_VF_MASK', 'mmRLC_GPU_IOV_VF_MASK_BASE_IDX',
'mmRLC_GPU_IOV_VIRT_RESET_REQ',
'mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX',
'mmRLC_GPU_IOV_VM_BUSY_STATUS',
'mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX', 'mmRLC_GTS_OFFSET_LSB',
'mmRLC_GTS_OFFSET_LSB_BASE_IDX', 'mmRLC_GTS_OFFSET_MSB',
'mmRLC_GTS_OFFSET_MSB_BASE_IDX', 'mmRLC_HYP_BOOTLOAD_ADDR_HI',
'mmRLC_HYP_BOOTLOAD_ADDR_HI_BASE_IDX',
'mmRLC_HYP_BOOTLOAD_ADDR_LO',
'mmRLC_HYP_BOOTLOAD_ADDR_LO_BASE_IDX', 'mmRLC_HYP_BOOTLOAD_SIZE',
'mmRLC_HYP_BOOTLOAD_SIZE_BASE_IDX', 'mmRLC_HYP_RESET_VECTOR',
'mmRLC_HYP_RESET_VECTOR_BASE_IDX', 'mmRLC_HYP_RLCG_UCODE_CHKSUM',
'mmRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX',
'mmRLC_HYP_RLCP_UCODE_CHKSUM',
'mmRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX',
'mmRLC_HYP_RLCV_UCODE_CHKSUM',
'mmRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX', 'mmRLC_HYP_SEMAPHORE_0',
'mmRLC_HYP_SEMAPHORE_0_BASE_IDX', 'mmRLC_HYP_SEMAPHORE_1',
'mmRLC_HYP_SEMAPHORE_1_BASE_IDX', 'mmRLC_HYP_SEMAPHORE_2',
'mmRLC_HYP_SEMAPHORE_2_BASE_IDX', 'mmRLC_HYP_SEMAPHORE_3',
'mmRLC_HYP_SEMAPHORE_3_BASE_IDX', 'mmRLC_IH_COOKIE',
'mmRLC_IH_COOKIE_BASE_IDX', 'mmRLC_IH_COOKIE_CNTL',
'mmRLC_IH_COOKIE_CNTL_BASE_IDX', 'mmRLC_INT_STAT',
'mmRLC_INT_STAT_BASE_IDX', 'mmRLC_JUMP_TABLE_RESTORE',
'mmRLC_JUMP_TABLE_RESTORE_BASE_IDX',
'mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK',
'mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK_BASE_IDX', 'mmRLC_LB_CNTL',
'mmRLC_LB_CNTL_BASE_IDX', 'mmRLC_LB_CNTR_1',
'mmRLC_LB_CNTR_1_BASE_IDX', 'mmRLC_LB_CNTR_2',
'mmRLC_LB_CNTR_2_BASE_IDX', 'mmRLC_LB_CNTR_INIT_1',
'mmRLC_LB_CNTR_INIT_1_BASE_IDX', 'mmRLC_LB_CNTR_INIT_2',
'mmRLC_LB_CNTR_INIT_2_BASE_IDX', 'mmRLC_LB_CNTR_MAX_1',
'mmRLC_LB_CNTR_MAX_1_BASE_IDX', 'mmRLC_LB_CNTR_MAX_2',
'mmRLC_LB_CNTR_MAX_2_BASE_IDX', 'mmRLC_LB_CONFIG_1',
'mmRLC_LB_CONFIG_1_BASE_IDX', 'mmRLC_LB_CONFIG_2',
'mmRLC_LB_CONFIG_2_BASE_IDX', 'mmRLC_LB_CONFIG_3',
'mmRLC_LB_CONFIG_3_BASE_IDX', 'mmRLC_LB_CONFIG_4',
'mmRLC_LB_CONFIG_4_BASE_IDX', 'mmRLC_LB_CONFIG_5',
'mmRLC_LB_CONFIG_5_BASE_IDX', 'mmRLC_LB_DELAY',
'mmRLC_LB_DELAY_BASE_IDX', 'mmRLC_LB_INIT_WGP_MASK',
'mmRLC_LB_INIT_WGP_MASK_BASE_IDX', 'mmRLC_LB_PARAMS',
'mmRLC_LB_PARAMS_BASE_IDX', 'mmRLC_LB_WGP_STAT',
'mmRLC_LB_WGP_STAT_BASE_IDX', 'mmRLC_MAX_PG_WGP',
'mmRLC_MAX_PG_WGP_BASE_IDX', 'mmRLC_MEM_SLP_CNTL',
'mmRLC_MEM_SLP_CNTL_BASE_IDX', 'mmRLC_MGCG_CTRL',
'mmRLC_MGCG_CTRL_BASE_IDX', 'mmRLC_PACE_INT_CLEAR',
'mmRLC_PACE_INT_CLEAR_BASE_IDX', 'mmRLC_PACE_INT_DISABLE',
'mmRLC_PACE_INT_DISABLE_BASE_IDX', 'mmRLC_PACE_INT_FORCE',
'mmRLC_PACE_INT_FORCE_BASE_IDX', 'mmRLC_PACE_INT_STAT',
'mmRLC_PACE_INT_STAT_BASE_IDX', 'mmRLC_PACE_SCRATCH_ADDR',
'mmRLC_PACE_SCRATCH_ADDR_BASE_IDX', 'mmRLC_PACE_SCRATCH_DATA',
'mmRLC_PACE_SCRATCH_DATA_BASE_IDX', 'mmRLC_PACE_SPARE_INT',
'mmRLC_PACE_SPARE_INT_1', 'mmRLC_PACE_SPARE_INT_1_BASE_IDX',
'mmRLC_PACE_SPARE_INT_BASE_IDX', 'mmRLC_PACE_TIMER_CTRL',
'mmRLC_PACE_TIMER_CTRL_BASE_IDX', 'mmRLC_PACE_TIMER_INT_0',
'mmRLC_PACE_TIMER_INT_0_BASE_IDX', 'mmRLC_PACE_TIMER_INT_1',
'mmRLC_PACE_TIMER_INT_1_BASE_IDX', 'mmRLC_PACE_TIMER_STAT',
'mmRLC_PACE_TIMER_STAT_BASE_IDX', 'mmRLC_PACE_UCODE_ADDR',
'mmRLC_PACE_UCODE_ADDR_BASE_IDX', 'mmRLC_PACE_UCODE_DATA',
'mmRLC_PACE_UCODE_DATA_BASE_IDX',
'mmRLC_PCC_STRETCH_HYSTERESIS_CNTL',
'mmRLC_PCC_STRETCH_HYSTERESIS_CNTL_BASE_IDX',
'mmRLC_PERFCOUNTER0_HI', 'mmRLC_PERFCOUNTER0_HI_BASE_IDX',
'mmRLC_PERFCOUNTER0_LO', 'mmRLC_PERFCOUNTER0_LO_BASE_IDX',
'mmRLC_PERFCOUNTER0_SELECT', 'mmRLC_PERFCOUNTER0_SELECT_BASE_IDX',
'mmRLC_PERFCOUNTER1_HI', 'mmRLC_PERFCOUNTER1_HI_BASE_IDX',
'mmRLC_PERFCOUNTER1_LO', 'mmRLC_PERFCOUNTER1_LO_BASE_IDX',
'mmRLC_PERFCOUNTER1_SELECT', 'mmRLC_PERFCOUNTER1_SELECT_BASE_IDX',
'mmRLC_PERFMON_CLK_CNTL', 'mmRLC_PERFMON_CLK_CNTL_BASE_IDX',
'mmRLC_PERFMON_CNTL', 'mmRLC_PERFMON_CNTL_BASE_IDX',
'mmRLC_PG_ALWAYS_ON_WGP_MASK',
'mmRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX', 'mmRLC_PG_CNTL',
'mmRLC_PG_CNTL_BASE_IDX', 'mmRLC_PG_DELAY', 'mmRLC_PG_DELAY_2',
'mmRLC_PG_DELAY_2_BASE_IDX', 'mmRLC_PG_DELAY_3',
'mmRLC_PG_DELAY_3_BASE_IDX', 'mmRLC_PG_DELAY_BASE_IDX',
'mmRLC_PREWALKER_UTCL1_ADDR_LSB',
'mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX',
'mmRLC_PREWALKER_UTCL1_ADDR_MSB',
'mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX',
'mmRLC_PREWALKER_UTCL1_CNTL',
'mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX',
'mmRLC_PREWALKER_UTCL1_SIZE_LSB',
'mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX',
'mmRLC_PREWALKER_UTCL1_SIZE_MSB',
'mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX',
'mmRLC_PREWALKER_UTCL1_TRIG',
'mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX', 'mmRLC_R2I_CNTL_0',
'mmRLC_R2I_CNTL_0_BASE_IDX', 'mmRLC_R2I_CNTL_1',
'mmRLC_R2I_CNTL_1_BASE_IDX', 'mmRLC_R2I_CNTL_2',
'mmRLC_R2I_CNTL_2_BASE_IDX', 'mmRLC_R2I_CNTL_3',
'mmRLC_R2I_CNTL_3_BASE_IDX', 'mmRLC_REFCLOCK_TIMESTAMP_LSB',
'mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX',
'mmRLC_REFCLOCK_TIMESTAMP_MSB',
'mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX',
'mmRLC_RLCG_DOORBELL_0_DATA_HI',
'mmRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX',
'mmRLC_RLCG_DOORBELL_0_DATA_LO',
'mmRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX',
'mmRLC_RLCG_DOORBELL_1_DATA_HI',
'mmRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX',
'mmRLC_RLCG_DOORBELL_1_DATA_LO',
'mmRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX',
'mmRLC_RLCG_DOORBELL_2_DATA_HI',
'mmRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX',
'mmRLC_RLCG_DOORBELL_2_DATA_LO',
'mmRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX',
'mmRLC_RLCG_DOORBELL_3_DATA_HI',
'mmRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX',
'mmRLC_RLCG_DOORBELL_3_DATA_LO',
'mmRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX',
'mmRLC_RLCG_DOORBELL_CNTL', 'mmRLC_RLCG_DOORBELL_CNTL_BASE_IDX',
'mmRLC_RLCG_DOORBELL_RANGE', 'mmRLC_RLCG_DOORBELL_RANGE_BASE_IDX',
'mmRLC_RLCG_DOORBELL_STAT', 'mmRLC_RLCG_DOORBELL_STAT_BASE_IDX',
'mmRLC_RLCP_DOORBELL_0_DATA_HI',
'mmRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX',
'mmRLC_RLCP_DOORBELL_0_DATA_LO',
'mmRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX',
'mmRLC_RLCP_DOORBELL_1_DATA_HI',
'mmRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX',
'mmRLC_RLCP_DOORBELL_1_DATA_LO',
'mmRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX',
'mmRLC_RLCP_DOORBELL_2_DATA_HI',
'mmRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX',
'mmRLC_RLCP_DOORBELL_2_DATA_LO',
'mmRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX',
'mmRLC_RLCP_DOORBELL_3_DATA_HI',
'mmRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX',
'mmRLC_RLCP_DOORBELL_3_DATA_LO',
'mmRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX',
'mmRLC_RLCP_DOORBELL_CNTL', 'mmRLC_RLCP_DOORBELL_CNTL_BASE_IDX',
'mmRLC_RLCP_DOORBELL_RANGE', 'mmRLC_RLCP_DOORBELL_RANGE_BASE_IDX',
'mmRLC_RLCP_DOORBELL_STAT', 'mmRLC_RLCP_DOORBELL_STAT_BASE_IDX',
'mmRLC_RLCP_IRAM_ADDR', 'mmRLC_RLCP_IRAM_ADDR_BASE_IDX',
'mmRLC_RLCP_IRAM_DATA', 'mmRLC_RLCP_IRAM_DATA_BASE_IDX',
'mmRLC_RLCS_ABORTED_PD_SEQUENCE',
'mmRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX',
'mmRLC_RLCS_AUXILIARY_REG_1',
'mmRLC_RLCS_AUXILIARY_REG_1_BASE_IDX',
'mmRLC_RLCS_AUXILIARY_REG_2',
'mmRLC_RLCS_AUXILIARY_REG_2_BASE_IDX',
'mmRLC_RLCS_AUXILIARY_REG_3',
'mmRLC_RLCS_AUXILIARY_REG_3_BASE_IDX',
'mmRLC_RLCS_AUXILIARY_REG_4',
'mmRLC_RLCS_AUXILIARY_REG_4_BASE_IDX',
'mmRLC_RLCS_BOOTLOAD_ID_STATUS1',
'mmRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX',
'mmRLC_RLCS_BOOTLOAD_ID_STATUS2',
'mmRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX',
'mmRLC_RLCS_BOOTLOAD_STATUS',
'mmRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX', 'mmRLC_RLCS_CGCG_REQUEST',
'mmRLC_RLCS_CGCG_REQUEST_BASE_IDX', 'mmRLC_RLCS_CGCG_STATUS',
'mmRLC_RLCS_CGCG_STATUS_BASE_IDX', 'mmRLC_RLCS_CMP_IDLE_CNTL',
'mmRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX',
'mmRLC_RLCS_CP_DMA_SRCID_OVER',
'mmRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX',
'mmRLC_RLCS_CP_INT_CTRL_1', 'mmRLC_RLCS_CP_INT_CTRL_1_BASE_IDX',
'mmRLC_RLCS_CP_INT_CTRL_2', 'mmRLC_RLCS_CP_INT_CTRL_2_BASE_IDX',
'mmRLC_RLCS_CP_INT_INFO_1', 'mmRLC_RLCS_CP_INT_INFO_1_BASE_IDX',
'mmRLC_RLCS_CP_INT_INFO_2', 'mmRLC_RLCS_CP_INT_INFO_2_BASE_IDX',
'mmRLC_RLCS_DEC_DUMP_ADDR', 'mmRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX',
'mmRLC_RLCS_DEC_END', 'mmRLC_RLCS_DEC_END_BASE_IDX',
'mmRLC_RLCS_DEC_START', 'mmRLC_RLCS_DEC_START_BASE_IDX',
'mmRLC_RLCS_DIDT_FORCE_STALL',
'mmRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX', 'mmRLC_RLCS_DSM_TRIG',
'mmRLC_RLCS_DSM_TRIG_BASE_IDX', 'mmRLC_RLCS_EDC_INT_CNTL',
'mmRLC_RLCS_EDC_INT_CNTL_BASE_IDX', 'mmRLC_RLCS_EXCEPTION_REG_1',
'mmRLC_RLCS_EXCEPTION_REG_1_BASE_IDX',
'mmRLC_RLCS_EXCEPTION_REG_2',
'mmRLC_RLCS_EXCEPTION_REG_2_BASE_IDX',
'mmRLC_RLCS_EXCEPTION_REG_3',
'mmRLC_RLCS_EXCEPTION_REG_3_BASE_IDX',
'mmRLC_RLCS_EXCEPTION_REG_4',
'mmRLC_RLCS_EXCEPTION_REG_4_BASE_IDX', 'mmRLC_RLCS_GENERAL_0',
'mmRLC_RLCS_GENERAL_0_BASE_IDX', 'mmRLC_RLCS_GENERAL_1',
'mmRLC_RLCS_GENERAL_1_BASE_IDX', 'mmRLC_RLCS_GENERAL_2',
'mmRLC_RLCS_GENERAL_2_BASE_IDX', 'mmRLC_RLCS_GENERAL_3',
'mmRLC_RLCS_GENERAL_3_BASE_IDX', 'mmRLC_RLCS_GENERAL_4',
'mmRLC_RLCS_GENERAL_4_BASE_IDX', 'mmRLC_RLCS_GENERAL_5',
'mmRLC_RLCS_GENERAL_5_BASE_IDX', 'mmRLC_RLCS_GENERAL_6',
'mmRLC_RLCS_GENERAL_6_BASE_IDX', 'mmRLC_RLCS_GENERAL_7',
'mmRLC_RLCS_GENERAL_7_BASE_IDX', 'mmRLC_RLCS_GFX_DS_CNTL',
'mmRLC_RLCS_GFX_DS_CNTL_BASE_IDX',
'mmRLC_RLCS_GPM_LEGACY_INT_DISABLE',
'mmRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX',
'mmRLC_RLCS_GPM_LEGACY_INT_STAT',
'mmRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX', 'mmRLC_RLCS_GPM_STAT',
'mmRLC_RLCS_GPM_STAT_2', 'mmRLC_RLCS_GPM_STAT_2_BASE_IDX',
'mmRLC_RLCS_GPM_STAT_BASE_IDX',
'mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL',
'mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX',
'mmRLC_RLCS_GRBM_IDLE_BUSY_STAT',
'mmRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX',
'mmRLC_RLCS_GRBM_SOFT_RESET',
'mmRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX',
'mmRLC_RLCS_IH_COOKIE_SEMAPHORE',
'mmRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX', 'mmRLC_RLCS_IH_CTRL_1',
'mmRLC_RLCS_IH_CTRL_1_BASE_IDX', 'mmRLC_RLCS_IH_CTRL_2',
'mmRLC_RLCS_IH_CTRL_2_BASE_IDX', 'mmRLC_RLCS_IH_CTRL_3',
'mmRLC_RLCS_IH_CTRL_3_BASE_IDX', 'mmRLC_RLCS_IH_SEMAPHORE',
'mmRLC_RLCS_IH_SEMAPHORE_BASE_IDX', 'mmRLC_RLCS_IH_STATUS',
'mmRLC_RLCS_IH_STATUS_BASE_IDX', 'mmRLC_RLCS_IOV_CMD_STATUS',
'mmRLC_RLCS_IOV_CMD_STATUS_BASE_IDX',
'mmRLC_RLCS_IOV_CNTX_LOC_SIZE',
'mmRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX',
'mmRLC_RLCS_IOV_SCH_BLOCK', 'mmRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX',
'mmRLC_RLCS_IOV_VM_BUSY_STATUS',
'mmRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX',
'mmRLC_RLCS_KMD_LOG_CNTL1', 'mmRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX',
'mmRLC_RLCS_KMD_LOG_CNTL2', 'mmRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX',
'mmRLC_RLCS_LB_CONTROL', 'mmRLC_RLCS_LB_CONTROL_BASE_IDX',
'mmRLC_RLCS_LB_READ', 'mmRLC_RLCS_LB_READ_BASE_IDX',
'mmRLC_RLCS_LB_STATUS', 'mmRLC_RLCS_LB_STATUS_BASE_IDX',
'mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL',
'mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL_BASE_IDX',
'mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE',
'mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX',
'mmRLC_RLCS_PG_CHANGE_READ', 'mmRLC_RLCS_PG_CHANGE_READ_BASE_IDX',
'mmRLC_RLCS_PG_CHANGE_STATUS',
'mmRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX',
'mmRLC_RLCS_POWER_BRAKE_CNTL',
'mmRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX',
'mmRLC_RLCS_POWER_BRAKE_CNTL_TH1',
'mmRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX',
'mmRLC_RLCS_SMUIO_VIDCHG_CTRL',
'mmRLC_RLCS_SMUIO_VIDCHG_CTRL_BASE_IDX',
'mmRLC_RLCS_SMU_GFXCLK_CONTROL',
'mmRLC_RLCS_SMU_GFXCLK_CONTROL_BASE_IDX',
'mmRLC_RLCS_SMU_GFXCLK_STATUS',
'mmRLC_RLCS_SMU_GFXCLK_STATUS_BASE_IDX', 'mmRLC_RLCS_SOC_DS_CNTL',
'mmRLC_RLCS_SOC_DS_CNTL_BASE_IDX', 'mmRLC_RLCS_SPM_INT_CTRL',
'mmRLC_RLCS_SPM_INT_CTRL_BASE_IDX', 'mmRLC_RLCS_SPM_INT_INFO_1',
'mmRLC_RLCS_SPM_INT_INFO_1_BASE_IDX', 'mmRLC_RLCS_SPM_INT_INFO_2',
'mmRLC_RLCS_SPM_INT_INFO_2_BASE_IDX', 'mmRLC_RLCS_SPM_SQTT_MODE',
'mmRLC_RLCS_SPM_SQTT_MODE_BASE_IDX', 'mmRLC_RLCS_SRM_SRCID_CNTL',
'mmRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX', 'mmRLC_RLCS_UTCL2_CNTL',
'mmRLC_RLCS_UTCL2_CNTL_BASE_IDX', 'mmRLC_RLCS_WGP_READ',
'mmRLC_RLCS_WGP_READ_BASE_IDX', 'mmRLC_RLCS_WGP_STATUS',
'mmRLC_RLCS_WGP_STATUS_BASE_IDX', 'mmRLC_RLCV_COMMAND',
'mmRLC_RLCV_COMMAND_BASE_IDX', 'mmRLC_RLCV_DOORBELL_0_DATA_HI',
'mmRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX',
'mmRLC_RLCV_DOORBELL_0_DATA_LO',
'mmRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX',
'mmRLC_RLCV_DOORBELL_1_DATA_HI',
'mmRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX',
'mmRLC_RLCV_DOORBELL_1_DATA_LO',
'mmRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX',
'mmRLC_RLCV_DOORBELL_2_DATA_HI',
'mmRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX',
'mmRLC_RLCV_DOORBELL_2_DATA_LO',
'mmRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX',
'mmRLC_RLCV_DOORBELL_3_DATA_HI',
'mmRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX',
'mmRLC_RLCV_DOORBELL_3_DATA_LO',
'mmRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX',
'mmRLC_RLCV_DOORBELL_CNTL', 'mmRLC_RLCV_DOORBELL_CNTL_BASE_IDX',
'mmRLC_RLCV_DOORBELL_RANGE', 'mmRLC_RLCV_DOORBELL_RANGE_BASE_IDX',
'mmRLC_RLCV_DOORBELL_STAT', 'mmRLC_RLCV_DOORBELL_STAT_BASE_IDX',
'mmRLC_RLCV_IRAM_ADDR', 'mmRLC_RLCV_IRAM_ADDR_BASE_IDX',
'mmRLC_RLCV_IRAM_DATA', 'mmRLC_RLCV_IRAM_DATA_BASE_IDX',
'mmRLC_RLCV_SAFE_MODE', 'mmRLC_RLCV_SAFE_MODE_BASE_IDX',
'mmRLC_RLCV_SPARE_INT', 'mmRLC_RLCV_SPARE_INT_1',
'mmRLC_RLCV_SPARE_INT_1_BASE_IDX',
'mmRLC_RLCV_SPARE_INT_BASE_IDX', 'mmRLC_RLCV_TIMER_CTRL',
'mmRLC_RLCV_TIMER_CTRL_BASE_IDX', 'mmRLC_RLCV_TIMER_INT_0',
'mmRLC_RLCV_TIMER_INT_0_BASE_IDX', 'mmRLC_RLCV_TIMER_INT_1',
'mmRLC_RLCV_TIMER_INT_1_BASE_IDX', 'mmRLC_RLCV_TIMER_STAT',
'mmRLC_RLCV_TIMER_STAT_BASE_IDX', 'mmRLC_SAFE_MODE',
'mmRLC_SAFE_MODE_BASE_IDX', 'mmRLC_SDMA0_BUSY_STATUS',
'mmRLC_SDMA0_BUSY_STATUS_BASE_IDX', 'mmRLC_SDMA0_STATUS',
'mmRLC_SDMA0_STATUS_BASE_IDX', 'mmRLC_SDMA1_BUSY_STATUS',
'mmRLC_SDMA1_BUSY_STATUS_BASE_IDX', 'mmRLC_SDMA1_STATUS',
'mmRLC_SDMA1_STATUS_BASE_IDX', 'mmRLC_SDMA2_BUSY_STATUS',
'mmRLC_SDMA2_BUSY_STATUS_BASE_IDX', 'mmRLC_SDMA2_STATUS',
'mmRLC_SDMA2_STATUS_BASE_IDX', 'mmRLC_SDMA3_BUSY_STATUS',
'mmRLC_SDMA3_BUSY_STATUS_BASE_IDX', 'mmRLC_SDMA3_STATUS',
'mmRLC_SDMA3_STATUS_BASE_IDX', 'mmRLC_SEMAPHORE_0',
'mmRLC_SEMAPHORE_0_BASE_IDX', 'mmRLC_SEMAPHORE_1',
'mmRLC_SEMAPHORE_1_BASE_IDX', 'mmRLC_SEMAPHORE_2',
'mmRLC_SEMAPHORE_2_BASE_IDX', 'mmRLC_SEMAPHORE_3',
'mmRLC_SEMAPHORE_3_BASE_IDX', 'mmRLC_SERDES_BUSY',
'mmRLC_SERDES_BUSY_BASE_IDX', 'mmRLC_SERDES_CTRL',
'mmRLC_SERDES_CTRL_BASE_IDX', 'mmRLC_SERDES_DATA',
'mmRLC_SERDES_DATA_BASE_IDX', 'mmRLC_SERDES_MASK',
'mmRLC_SERDES_MASK_BASE_IDX', 'mmRLC_SERDES_RD_DATA_0',
'mmRLC_SERDES_RD_DATA_0_BASE_IDX', 'mmRLC_SERDES_RD_DATA_1',
'mmRLC_SERDES_RD_DATA_1_BASE_IDX', 'mmRLC_SERDES_RD_DATA_2',
'mmRLC_SERDES_RD_DATA_2_BASE_IDX', 'mmRLC_SERDES_RD_DATA_3',
'mmRLC_SERDES_RD_DATA_3_BASE_IDX', 'mmRLC_SERDES_RD_INDEX',
'mmRLC_SERDES_RD_INDEX_BASE_IDX', 'mmRLC_SMU_ARGUMENT_1',
'mmRLC_SMU_ARGUMENT_1_BASE_IDX', 'mmRLC_SMU_ARGUMENT_2',
'mmRLC_SMU_ARGUMENT_2_BASE_IDX', 'mmRLC_SMU_ARGUMENT_3',
'mmRLC_SMU_ARGUMENT_3_BASE_IDX', 'mmRLC_SMU_ARGUMENT_4',
'mmRLC_SMU_ARGUMENT_4_BASE_IDX', 'mmRLC_SMU_CLK_REQ',
'mmRLC_SMU_CLK_REQ_BASE_IDX', 'mmRLC_SMU_COMMAND',
'mmRLC_SMU_COMMAND_BASE_IDX', 'mmRLC_SMU_GRBM_REG_SAVE_CTRL',
'mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX', 'mmRLC_SMU_MESSAGE',
'mmRLC_SMU_MESSAGE_BASE_IDX', 'mmRLC_SMU_SAFE_MODE',
'mmRLC_SMU_SAFE_MODE_BASE_IDX', 'mmRLC_SPARE_INT_0',
'mmRLC_SPARE_INT_0_BASE_IDX', 'mmRLC_SPARE_INT_1',
'mmRLC_SPARE_INT_1_BASE_IDX', 'mmRLC_SPARE_INT_2',
'mmRLC_SPARE_INT_2_BASE_IDX', 'mmRLC_SPM_ACCUM_CTRL',
'mmRLC_SPM_ACCUM_CTRLRAM_ADDR',
'mmRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX',
'mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET',
'mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX',
'mmRLC_SPM_ACCUM_CTRLRAM_DATA',
'mmRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX',
'mmRLC_SPM_ACCUM_CTRL_BASE_IDX',
'mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS',
'mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX',
'mmRLC_SPM_ACCUM_DATARAM_ADDR',
'mmRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX',
'mmRLC_SPM_ACCUM_DATARAM_DATA',
'mmRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX',
'mmRLC_SPM_ACCUM_DATARAM_WRCOUNT',
'mmRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX',
'mmRLC_SPM_ACCUM_MODE', 'mmRLC_SPM_ACCUM_MODE_BASE_IDX',
'mmRLC_SPM_ACCUM_SAMPLES_REQUESTED',
'mmRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX',
'mmRLC_SPM_ACCUM_STATUS', 'mmRLC_SPM_ACCUM_STATUS_BASE_IDX',
'mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR',
'mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX',
'mmRLC_SPM_ACCUM_SWA_DATARAM_DATA',
'mmRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX',
'mmRLC_SPM_ACCUM_THRESHOLD', 'mmRLC_SPM_ACCUM_THRESHOLD_BASE_IDX',
'mmRLC_SPM_DESER_START_SKEW',
'mmRLC_SPM_DESER_START_SKEW_BASE_IDX',
'mmRLC_SPM_GFXCLOCK_HIGHCOUNT',
'mmRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX',
'mmRLC_SPM_GFXCLOCK_LOWCOUNT',
'mmRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX',
'mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR',
'mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR_BASE_IDX',
'mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA',
'mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA_BASE_IDX',
'mmRLC_SPM_GLOBALS_MUXSEL_SKEW',
'mmRLC_SPM_GLOBALS_MUXSEL_SKEW_BASE_IDX',
'mmRLC_SPM_GLOBALS_SAMPLE_SKEW',
'mmRLC_SPM_GLOBALS_SAMPLE_SKEW_BASE_IDX',
'mmRLC_SPM_GLOBAL_MUXSEL_ADDR',
'mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX',
'mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET',
'mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET_BASE_IDX',
'mmRLC_SPM_GLOBAL_MUXSEL_DATA',
'mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX', 'mmRLC_SPM_INT_CNTL',
'mmRLC_SPM_INT_CNTL_BASE_IDX', 'mmRLC_SPM_INT_INFO_1',
'mmRLC_SPM_INT_INFO_1_BASE_IDX', 'mmRLC_SPM_INT_INFO_2',
'mmRLC_SPM_INT_INFO_2_BASE_IDX', 'mmRLC_SPM_INT_STATUS',
'mmRLC_SPM_INT_STATUS_BASE_IDX', 'mmRLC_SPM_MC_CNTL',
'mmRLC_SPM_MC_CNTL_BASE_IDX', 'mmRLC_SPM_PERFMON_CNTL',
'mmRLC_SPM_PERFMON_CNTL_BASE_IDX',
'mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE',
'mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE_BASE_IDX',
'mmRLC_SPM_PERFMON_RING_BASE_HI',
'mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX',
'mmRLC_SPM_PERFMON_RING_BASE_LO',
'mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX',
'mmRLC_SPM_PERFMON_RING_SIZE',
'mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX',
'mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE',
'mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE_BASE_IDX',
'mmRLC_SPM_PERFMON_SEGMENT_SIZE',
'mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX',
'mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE',
'mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE_BASE_IDX',
'mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE',
'mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE_BASE_IDX',
'mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE',
'mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE_BASE_IDX',
'mmRLC_SPM_RING_RDPTR', 'mmRLC_SPM_RING_RDPTR_BASE_IDX',
'mmRLC_SPM_RING_WRPTR', 'mmRLC_SPM_RING_WRPTR_BASE_IDX',
'mmRLC_SPM_SAMPLE_CNT', 'mmRLC_SPM_SAMPLE_CNT_BASE_IDX',
'mmRLC_SPM_SEGMENT_THRESHOLD',
'mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX',
'mmRLC_SPM_SE_MUXSEL_ADDR', 'mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX',
'mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET',
'mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET_BASE_IDX',
'mmRLC_SPM_SE_MUXSEL_DATA', 'mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX',
'mmRLC_SPM_SE_MUXSEL_SKEW', 'mmRLC_SPM_SE_MUXSEL_SKEW_BASE_IDX',
'mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR',
'mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR_BASE_IDX',
'mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA',
'mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA_BASE_IDX',
'mmRLC_SPM_SE_SAMPLE_SKEW', 'mmRLC_SPM_SE_SAMPLE_SKEW_BASE_IDX',
'mmRLC_SPM_THREAD_TRACE_CTRL',
'mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX', 'mmRLC_SPM_UTCL1_CNTL',
'mmRLC_SPM_UTCL1_CNTL_BASE_IDX', 'mmRLC_SPM_UTCL1_ERROR_1',
'mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX', 'mmRLC_SPM_UTCL1_ERROR_2',
'mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX', 'mmRLC_SPM_VIRT_CTRL',
'mmRLC_SPM_VIRT_CTRL_BASE_IDX', 'mmRLC_SPM_VIRT_STATUS',
'mmRLC_SPM_VIRT_STATUS_BASE_IDX', 'mmRLC_SPP_CAM_ADDR',
'mmRLC_SPP_CAM_ADDR_BASE_IDX', 'mmRLC_SPP_CAM_DATA',
'mmRLC_SPP_CAM_DATA_BASE_IDX', 'mmRLC_SPP_CAM_EXT_ADDR',
'mmRLC_SPP_CAM_EXT_ADDR_BASE_IDX', 'mmRLC_SPP_CAM_EXT_DATA',
'mmRLC_SPP_CAM_EXT_DATA_BASE_IDX', 'mmRLC_SPP_CTRL',
'mmRLC_SPP_CTRL_BASE_IDX', 'mmRLC_SPP_GLOBAL_SH_ID',
'mmRLC_SPP_GLOBAL_SH_ID_BASE_IDX', 'mmRLC_SPP_GLOBAL_SH_ID_VALID',
'mmRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX',
'mmRLC_SPP_INFLIGHT_RD_ADDR',
'mmRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX',
'mmRLC_SPP_INFLIGHT_RD_DATA',
'mmRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX', 'mmRLC_SPP_PBB_INFO',
'mmRLC_SPP_PBB_INFO_BASE_IDX', 'mmRLC_SPP_PROF_INFO_1',
'mmRLC_SPP_PROF_INFO_1_BASE_IDX', 'mmRLC_SPP_PROF_INFO_2',
'mmRLC_SPP_PROF_INFO_2_BASE_IDX', 'mmRLC_SPP_PVT_LEVEL_MAX',
'mmRLC_SPP_PVT_LEVEL_MAX_BASE_IDX', 'mmRLC_SPP_PVT_STAT_0',
'mmRLC_SPP_PVT_STAT_0_BASE_IDX', 'mmRLC_SPP_PVT_STAT_1',
'mmRLC_SPP_PVT_STAT_1_BASE_IDX', 'mmRLC_SPP_PVT_STAT_2',
'mmRLC_SPP_PVT_STAT_2_BASE_IDX', 'mmRLC_SPP_PVT_STAT_3',
'mmRLC_SPP_PVT_STAT_3_BASE_IDX', 'mmRLC_SPP_RESET',
'mmRLC_SPP_RESET_BASE_IDX', 'mmRLC_SPP_SHADER_PROFILE_EN',
'mmRLC_SPP_SHADER_PROFILE_EN_BASE_IDX',
'mmRLC_SPP_SSF_CAPTURE_EN', 'mmRLC_SPP_SSF_CAPTURE_EN_BASE_IDX',
'mmRLC_SPP_SSF_THRESHOLD_0', 'mmRLC_SPP_SSF_THRESHOLD_0_BASE_IDX',
'mmRLC_SPP_SSF_THRESHOLD_1', 'mmRLC_SPP_SSF_THRESHOLD_1_BASE_IDX',
'mmRLC_SPP_SSF_THRESHOLD_2', 'mmRLC_SPP_SSF_THRESHOLD_2_BASE_IDX',
'mmRLC_SPP_STALL_STATE_UPDATE',
'mmRLC_SPP_STALL_STATE_UPDATE_BASE_IDX', 'mmRLC_SPP_STATUS',
'mmRLC_SPP_STATUS_BASE_IDX', 'mmRLC_SRM_ARAM_ADDR',
'mmRLC_SRM_ARAM_ADDR_BASE_IDX', 'mmRLC_SRM_ARAM_DATA',
'mmRLC_SRM_ARAM_DATA_BASE_IDX', 'mmRLC_SRM_CNTL',
'mmRLC_SRM_CNTL_BASE_IDX', 'mmRLC_SRM_DRAM_ADDR',
'mmRLC_SRM_DRAM_ADDR_BASE_IDX', 'mmRLC_SRM_DRAM_DATA',
'mmRLC_SRM_DRAM_DATA_BASE_IDX', 'mmRLC_SRM_FWL_FIRST_VIOL_ADDR',
'mmRLC_SRM_FWL_FIRST_VIOL_ADDR_BASE_IDX', 'mmRLC_SRM_GPM_ABORT',
'mmRLC_SRM_GPM_ABORT_BASE_IDX', 'mmRLC_SRM_GPM_COMMAND',
'mmRLC_SRM_GPM_COMMAND_BASE_IDX', 'mmRLC_SRM_GPM_COMMAND_STATUS',
'mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_ADDR_0',
'mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_ADDR_1',
'mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_ADDR_2',
'mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_ADDR_3',
'mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_ADDR_4',
'mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_ADDR_5',
'mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_ADDR_6',
'mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_ADDR_7',
'mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_DATA_0',
'mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_DATA_1',
'mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_DATA_2',
'mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_DATA_3',
'mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_DATA_4',
'mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_DATA_5',
'mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_DATA_6',
'mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX',
'mmRLC_SRM_INDEX_CNTL_DATA_7',
'mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX', 'mmRLC_SRM_RLCV_COMMAND',
'mmRLC_SRM_RLCV_COMMAND_BASE_IDX',
'mmRLC_SRM_RLCV_COMMAND_STATUS',
'mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX', 'mmRLC_SRM_STAT',
'mmRLC_SRM_STAT_BASE_IDX', 'mmRLC_STAT', 'mmRLC_STATIC_PG_STATUS',
'mmRLC_STATIC_PG_STATUS_BASE_IDX', 'mmRLC_STAT_BASE_IDX',
'mmRLC_UCODE_CNTL', 'mmRLC_UCODE_CNTL_BASE_IDX',
'mmRLC_UTCL1_STATUS', 'mmRLC_UTCL1_STATUS_2',
'mmRLC_UTCL1_STATUS_2_BASE_IDX', 'mmRLC_UTCL1_STATUS_BASE_IDX',
'mmRLC_WGP_STATUS', 'mmRLC_WGP_STATUS_BASE_IDX',
'mmRLC_XT_DOORBELL_0_DATA_HI',
'mmRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX',
'mmRLC_XT_DOORBELL_0_DATA_LO',
'mmRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX',
'mmRLC_XT_DOORBELL_1_DATA_HI',
'mmRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX',
'mmRLC_XT_DOORBELL_1_DATA_LO',
'mmRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX',
'mmRLC_XT_DOORBELL_2_DATA_HI',
'mmRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX',
'mmRLC_XT_DOORBELL_2_DATA_LO',
'mmRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX',
'mmRLC_XT_DOORBELL_3_DATA_HI',
'mmRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX',
'mmRLC_XT_DOORBELL_3_DATA_LO',
'mmRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX', 'mmRLC_XT_DOORBELL_CNTL',
'mmRLC_XT_DOORBELL_CNTL_BASE_IDX', 'mmRLC_XT_DOORBELL_RANGE',
'mmRLC_XT_DOORBELL_RANGE_BASE_IDX', 'mmRLC_XT_DOORBELL_STAT',
'mmRLC_XT_DOORBELL_STAT_BASE_IDX', 'mmRMI_CGTT_SCLK_CTRL',
'mmRMI_CGTT_SCLK_CTRL_BASE_IDX', 'mmRMI_CLOCK_CNTRL',
'mmRMI_CLOCK_CNTRL_BASE_IDX', 'mmRMI_DEMUX_CNTL',
'mmRMI_DEMUX_CNTL_BASE_IDX', 'mmRMI_GENERAL_CNTL',
'mmRMI_GENERAL_CNTL1', 'mmRMI_GENERAL_CNTL1_BASE_IDX',
'mmRMI_GENERAL_CNTL_BASE_IDX', 'mmRMI_GENERAL_STATUS',
'mmRMI_GENERAL_STATUS_BASE_IDX', 'mmRMI_PERFCOUNTER0_HI',
'mmRMI_PERFCOUNTER0_HI_BASE_IDX', 'mmRMI_PERFCOUNTER0_LO',
'mmRMI_PERFCOUNTER0_LO_BASE_IDX', 'mmRMI_PERFCOUNTER0_SELECT',
'mmRMI_PERFCOUNTER0_SELECT1',
'mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmRMI_PERFCOUNTER0_SELECT_BASE_IDX', 'mmRMI_PERFCOUNTER1_HI',
'mmRMI_PERFCOUNTER1_HI_BASE_IDX', 'mmRMI_PERFCOUNTER1_LO',
'mmRMI_PERFCOUNTER1_LO_BASE_IDX', 'mmRMI_PERFCOUNTER1_SELECT',
'mmRMI_PERFCOUNTER1_SELECT_BASE_IDX', 'mmRMI_PERFCOUNTER2_HI',
'mmRMI_PERFCOUNTER2_HI_BASE_IDX', 'mmRMI_PERFCOUNTER2_LO',
'mmRMI_PERFCOUNTER2_LO_BASE_IDX', 'mmRMI_PERFCOUNTER2_SELECT',
'mmRMI_PERFCOUNTER2_SELECT1',
'mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX',
'mmRMI_PERFCOUNTER2_SELECT_BASE_IDX', 'mmRMI_PERFCOUNTER3_HI',
'mmRMI_PERFCOUNTER3_HI_BASE_IDX', 'mmRMI_PERFCOUNTER3_LO',
'mmRMI_PERFCOUNTER3_LO_BASE_IDX', 'mmRMI_PERFCOUNTER3_SELECT',
'mmRMI_PERFCOUNTER3_SELECT_BASE_IDX', 'mmRMI_PERF_COUNTER_CNTL',
'mmRMI_PERF_COUNTER_CNTL_BASE_IDX', 'mmRMI_PROBE_POP_LOGIC_CNTL',
'mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX', 'mmRMI_RB_GLX_CID_MAP',
'mmRMI_RB_GLX_CID_MAP_BASE_IDX', 'mmRMI_SCOREBOARD_CNTL',
'mmRMI_SCOREBOARD_CNTL_BASE_IDX', 'mmRMI_SCOREBOARD_STATUS0',
'mmRMI_SCOREBOARD_STATUS0_BASE_IDX', 'mmRMI_SCOREBOARD_STATUS1',
'mmRMI_SCOREBOARD_STATUS1_BASE_IDX', 'mmRMI_SCOREBOARD_STATUS2',
'mmRMI_SCOREBOARD_STATUS2_BASE_IDX', 'mmRMI_SPARE',
'mmRMI_SPARE_1', 'mmRMI_SPARE_1_BASE_IDX', 'mmRMI_SPARE_2',
'mmRMI_SPARE_2_BASE_IDX', 'mmRMI_SPARE_BASE_IDX',
'mmRMI_SUBBLOCK_STATUS0', 'mmRMI_SUBBLOCK_STATUS0_BASE_IDX',
'mmRMI_SUBBLOCK_STATUS1', 'mmRMI_SUBBLOCK_STATUS1_BASE_IDX',
'mmRMI_SUBBLOCK_STATUS2', 'mmRMI_SUBBLOCK_STATUS2_BASE_IDX',
'mmRMI_SUBBLOCK_STATUS3', 'mmRMI_SUBBLOCK_STATUS3_BASE_IDX',
'mmRMI_TCIW_FORMATTER0_CNTL',
'mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX',
'mmRMI_TCIW_FORMATTER1_CNTL',
'mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX', 'mmRMI_UTCL1_CNTL1',
'mmRMI_UTCL1_CNTL1_BASE_IDX', 'mmRMI_UTCL1_CNTL2',
'mmRMI_UTCL1_CNTL2_BASE_IDX', 'mmRMI_UTCL1_STATUS',
'mmRMI_UTCL1_STATUS_BASE_IDX', 'mmRMI_UTC_UNIT_CONFIG',
'mmRMI_UTC_UNIT_CONFIG_BASE_IDX', 'mmRMI_UTC_XNACK_N_MISC_CNTL',
'mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX',
'mmRMI_XBAR_ARBITER_CONFIG', 'mmRMI_XBAR_ARBITER_CONFIG_1',
'mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX',
'mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX', 'mmRMI_XBAR_CONFIG',
'mmRMI_XBAR_CONFIG_BASE_IDX', 'mmRTAVFS_RTAVFS_REG_ADDR',
'mmRTAVFS_RTAVFS_REG_ADDR_BASE_IDX', 'mmRTAVFS_RTAVFS_WR_DATA',
'mmRTAVFS_RTAVFS_WR_DATA_BASE_IDX', 'mmSCRATCH_ADDR',
'mmSCRATCH_ADDR_BASE_IDX', 'mmSCRATCH_REG0',
'mmSCRATCH_REG0_BASE_IDX', 'mmSCRATCH_REG1',
'mmSCRATCH_REG1_BASE_IDX', 'mmSCRATCH_REG2',
'mmSCRATCH_REG2_BASE_IDX', 'mmSCRATCH_REG3',
'mmSCRATCH_REG3_BASE_IDX', 'mmSCRATCH_REG4',
'mmSCRATCH_REG4_BASE_IDX', 'mmSCRATCH_REG5',
'mmSCRATCH_REG5_BASE_IDX', 'mmSCRATCH_REG6',
'mmSCRATCH_REG6_BASE_IDX', 'mmSCRATCH_REG7',
'mmSCRATCH_REG7_BASE_IDX', 'mmSCRATCH_REG_ATOMIC',
'mmSCRATCH_REG_ATOMIC_BASE_IDX', 'mmSCRATCH_REG_CMPSWAP_ATOMIC',
'mmSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX', 'mmSCRATCH_UMSK',
'mmSCRATCH_UMSK_BASE_IDX', 'mmSDMA0_ACTIVE_FCN_ID',
'mmSDMA0_ACTIVE_FCN_ID_BASE_IDX', 'mmSDMA0_AQL_STATUS',
'mmSDMA0_AQL_STATUS_BASE_IDX', 'mmSDMA0_ATOMIC_CNTL',
'mmSDMA0_ATOMIC_CNTL_BASE_IDX', 'mmSDMA0_ATOMIC_PREOP_HI',
'mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX', 'mmSDMA0_ATOMIC_PREOP_LO',
'mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX', 'mmSDMA0_BA_THRESHOLD',
'mmSDMA0_BA_THRESHOLD_BASE_IDX', 'mmSDMA0_BROADCAST_UCODE_ADDR',
'mmSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX',
'mmSDMA0_BROADCAST_UCODE_DATA',
'mmSDMA0_BROADCAST_UCODE_DATA_BASE_IDX', 'mmSDMA0_CHICKEN_BITS',
'mmSDMA0_CHICKEN_BITS_2', 'mmSDMA0_CHICKEN_BITS_2_BASE_IDX',
'mmSDMA0_CHICKEN_BITS_BASE_IDX', 'mmSDMA0_CLK_CTRL',
'mmSDMA0_CLK_CTRL_BASE_IDX', 'mmSDMA0_CLOCK_GATING_REG',
'mmSDMA0_CLOCK_GATING_REG_BASE_IDX', 'mmSDMA0_CNTL',
'mmSDMA0_CNTL_BASE_IDX', 'mmSDMA0_CONTEXT_REG_TYPE0',
'mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX', 'mmSDMA0_CONTEXT_REG_TYPE1',
'mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX', 'mmSDMA0_CONTEXT_REG_TYPE2',
'mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX', 'mmSDMA0_CONTEXT_REG_TYPE3',
'mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX', 'mmSDMA0_CRD_CNTL',
'mmSDMA0_CRD_CNTL_BASE_IDX', 'mmSDMA0_DEC_START',
'mmSDMA0_DEC_START_BASE_IDX', 'mmSDMA0_EA_DBIT_ADDR_DATA',
'mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX',
'mmSDMA0_EA_DBIT_ADDR_INDEX',
'mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX', 'mmSDMA0_EDC_CONFIG',
'mmSDMA0_EDC_CONFIG_BASE_IDX', 'mmSDMA0_EDC_COUNTER',
'mmSDMA0_EDC_COUNTER_BASE_IDX', 'mmSDMA0_EDC_COUNTER_CLEAR',
'mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX', 'mmSDMA0_ERROR_LOG',
'mmSDMA0_ERROR_LOG_BASE_IDX', 'mmSDMA0_F32_CNTL',
'mmSDMA0_F32_CNTL_BASE_IDX', 'mmSDMA0_F32_COUNTER',
'mmSDMA0_F32_COUNTER_BASE_IDX', 'mmSDMA0_FREEZE',
'mmSDMA0_FREEZE_BASE_IDX', 'mmSDMA0_GB_ADDR_CONFIG',
'mmSDMA0_GB_ADDR_CONFIG_BASE_IDX', 'mmSDMA0_GB_ADDR_CONFIG_READ',
'mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX',
'mmSDMA0_GFX_CONTEXT_CNTL', 'mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX',
'mmSDMA0_GFX_CONTEXT_STATUS',
'mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX', 'mmSDMA0_GFX_CSA_ADDR_HI',
'mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX', 'mmSDMA0_GFX_CSA_ADDR_LO',
'mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX', 'mmSDMA0_GFX_DOORBELL',
'mmSDMA0_GFX_DOORBELL_BASE_IDX', 'mmSDMA0_GFX_DOORBELL_LOG',
'mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX',
'mmSDMA0_GFX_DOORBELL_OFFSET',
'mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_GFX_DUMMY_REG',
'mmSDMA0_GFX_DUMMY_REG_BASE_IDX', 'mmSDMA0_GFX_IB_BASE_HI',
'mmSDMA0_GFX_IB_BASE_HI_BASE_IDX', 'mmSDMA0_GFX_IB_BASE_LO',
'mmSDMA0_GFX_IB_BASE_LO_BASE_IDX', 'mmSDMA0_GFX_IB_CNTL',
'mmSDMA0_GFX_IB_CNTL_BASE_IDX', 'mmSDMA0_GFX_IB_OFFSET',
'mmSDMA0_GFX_IB_OFFSET_BASE_IDX', 'mmSDMA0_GFX_IB_RPTR',
'mmSDMA0_GFX_IB_RPTR_BASE_IDX', 'mmSDMA0_GFX_IB_SIZE',
'mmSDMA0_GFX_IB_SIZE_BASE_IDX', 'mmSDMA0_GFX_IB_SUB_REMAIN',
'mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_CNTL',
'mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA0',
'mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA1',
'mmSDMA0_GFX_MIDCMD_DATA10', 'mmSDMA0_GFX_MIDCMD_DATA10_BASE_IDX',
'mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA2',
'mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA3',
'mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA4',
'mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA5',
'mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA6',
'mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA7',
'mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA8',
'mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA9',
'mmSDMA0_GFX_MIDCMD_DATA9_BASE_IDX',
'mmSDMA0_GFX_MINOR_PTR_UPDATE',
'mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_GFX_PREEMPT',
'mmSDMA0_GFX_PREEMPT_BASE_IDX', 'mmSDMA0_GFX_RB_AQL_CNTL',
'mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_GFX_RB_BASE',
'mmSDMA0_GFX_RB_BASE_BASE_IDX', 'mmSDMA0_GFX_RB_BASE_HI',
'mmSDMA0_GFX_RB_BASE_HI_BASE_IDX', 'mmSDMA0_GFX_RB_CNTL',
'mmSDMA0_GFX_RB_CNTL_BASE_IDX', 'mmSDMA0_GFX_RB_RPTR',
'mmSDMA0_GFX_RB_RPTR_ADDR_HI',
'mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA0_GFX_RB_RPTR_ADDR_LO',
'mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA0_GFX_RB_RPTR_BASE_IDX', 'mmSDMA0_GFX_RB_RPTR_HI',
'mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_GFX_RB_WPTR',
'mmSDMA0_GFX_RB_WPTR_BASE_IDX', 'mmSDMA0_GFX_RB_WPTR_HI',
'mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX',
'mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI',
'mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO',
'mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA0_GFX_RB_WPTR_POLL_CNTL',
'mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX', 'mmSDMA0_GFX_SKIP_CNTL',
'mmSDMA0_GFX_SKIP_CNTL_BASE_IDX', 'mmSDMA0_GFX_STATUS',
'mmSDMA0_GFX_STATUS_BASE_IDX', 'mmSDMA0_GFX_WATERMARK',
'mmSDMA0_GFX_WATERMARK_BASE_IDX', 'mmSDMA0_GLOBAL_TIMESTAMP_HI',
'mmSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX',
'mmSDMA0_GLOBAL_TIMESTAMP_LO',
'mmSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX', 'mmSDMA0_HBM_PAGE_CONFIG',
'mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX', 'mmSDMA0_HOLE_ADDR_HI',
'mmSDMA0_HOLE_ADDR_HI_BASE_IDX', 'mmSDMA0_HOLE_ADDR_LO',
'mmSDMA0_HOLE_ADDR_LO_BASE_IDX', 'mmSDMA0_IB_OFFSET_FETCH',
'mmSDMA0_IB_OFFSET_FETCH_BASE_IDX', 'mmSDMA0_ID',
'mmSDMA0_ID_BASE_IDX', 'mmSDMA0_INT_STATUS',
'mmSDMA0_INT_STATUS_BASE_IDX', 'mmSDMA0_PAGE_CONTEXT_STATUS',
'mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX',
'mmSDMA0_PAGE_CSA_ADDR_HI', 'mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX',
'mmSDMA0_PAGE_CSA_ADDR_LO', 'mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX',
'mmSDMA0_PAGE_DOORBELL', 'mmSDMA0_PAGE_DOORBELL_BASE_IDX',
'mmSDMA0_PAGE_DOORBELL_LOG', 'mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX',
'mmSDMA0_PAGE_DOORBELL_OFFSET',
'mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_PAGE_DUMMY_REG',
'mmSDMA0_PAGE_DUMMY_REG_BASE_IDX', 'mmSDMA0_PAGE_IB_BASE_HI',
'mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX', 'mmSDMA0_PAGE_IB_BASE_LO',
'mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX', 'mmSDMA0_PAGE_IB_CNTL',
'mmSDMA0_PAGE_IB_CNTL_BASE_IDX', 'mmSDMA0_PAGE_IB_OFFSET',
'mmSDMA0_PAGE_IB_OFFSET_BASE_IDX', 'mmSDMA0_PAGE_IB_RPTR',
'mmSDMA0_PAGE_IB_RPTR_BASE_IDX', 'mmSDMA0_PAGE_IB_SIZE',
'mmSDMA0_PAGE_IB_SIZE_BASE_IDX', 'mmSDMA0_PAGE_IB_SUB_REMAIN',
'mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_CNTL',
'mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA0',
'mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA1',
'mmSDMA0_PAGE_MIDCMD_DATA10',
'mmSDMA0_PAGE_MIDCMD_DATA10_BASE_IDX',
'mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA2',
'mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA3',
'mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA4',
'mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA5',
'mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA6',
'mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA7',
'mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA8',
'mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA9',
'mmSDMA0_PAGE_MIDCMD_DATA9_BASE_IDX',
'mmSDMA0_PAGE_MINOR_PTR_UPDATE',
'mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_PAGE_PREEMPT',
'mmSDMA0_PAGE_PREEMPT_BASE_IDX', 'mmSDMA0_PAGE_RB_AQL_CNTL',
'mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_PAGE_RB_BASE',
'mmSDMA0_PAGE_RB_BASE_BASE_IDX', 'mmSDMA0_PAGE_RB_BASE_HI',
'mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX', 'mmSDMA0_PAGE_RB_CNTL',
'mmSDMA0_PAGE_RB_CNTL_BASE_IDX', 'mmSDMA0_PAGE_RB_RPTR',
'mmSDMA0_PAGE_RB_RPTR_ADDR_HI',
'mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA0_PAGE_RB_RPTR_ADDR_LO',
'mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA0_PAGE_RB_RPTR_BASE_IDX', 'mmSDMA0_PAGE_RB_RPTR_HI',
'mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_PAGE_RB_WPTR',
'mmSDMA0_PAGE_RB_WPTR_BASE_IDX', 'mmSDMA0_PAGE_RB_WPTR_HI',
'mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX',
'mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI',
'mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO',
'mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA0_PAGE_RB_WPTR_POLL_CNTL',
'mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA0_PAGE_SKIP_CNTL', 'mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX',
'mmSDMA0_PAGE_STATUS', 'mmSDMA0_PAGE_STATUS_BASE_IDX',
'mmSDMA0_PAGE_WATERMARK', 'mmSDMA0_PAGE_WATERMARK_BASE_IDX',
'mmSDMA0_PERFCNT_MISC_CNTL', 'mmSDMA0_PERFCNT_MISC_CNTL_BASE_IDX',
'mmSDMA0_PERFCNT_PERFCOUNTER0_CFG',
'mmSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX',
'mmSDMA0_PERFCNT_PERFCOUNTER1_CFG',
'mmSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX',
'mmSDMA0_PERFCNT_PERFCOUNTER_HI',
'mmSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX',
'mmSDMA0_PERFCNT_PERFCOUNTER_LO',
'mmSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX',
'mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL',
'mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
'mmSDMA0_PERFCOUNTER0_HI', 'mmSDMA0_PERFCOUNTER0_HI_BASE_IDX',
'mmSDMA0_PERFCOUNTER0_LO', 'mmSDMA0_PERFCOUNTER0_LO_BASE_IDX',
'mmSDMA0_PERFCOUNTER0_SELECT', 'mmSDMA0_PERFCOUNTER0_SELECT1',
'mmSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmSDMA0_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSDMA0_PERFCOUNTER1_HI',
'mmSDMA0_PERFCOUNTER1_HI_BASE_IDX', 'mmSDMA0_PERFCOUNTER1_LO',
'mmSDMA0_PERFCOUNTER1_LO_BASE_IDX', 'mmSDMA0_PERFCOUNTER1_SELECT',
'mmSDMA0_PERFCOUNTER1_SELECT1',
'mmSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmSDMA0_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSDMA0_PG_CNTL',
'mmSDMA0_PG_CNTL_BASE_IDX', 'mmSDMA0_PG_CTX_CNTL',
'mmSDMA0_PG_CTX_CNTL_BASE_IDX', 'mmSDMA0_PG_CTX_HI',
'mmSDMA0_PG_CTX_HI_BASE_IDX', 'mmSDMA0_PG_CTX_LO',
'mmSDMA0_PG_CTX_LO_BASE_IDX', 'mmSDMA0_PHASE0_QUANTUM',
'mmSDMA0_PHASE0_QUANTUM_BASE_IDX', 'mmSDMA0_PHASE1_QUANTUM',
'mmSDMA0_PHASE1_QUANTUM_BASE_IDX', 'mmSDMA0_PHASE2_QUANTUM',
'mmSDMA0_PHASE2_QUANTUM_BASE_IDX', 'mmSDMA0_PHYSICAL_ADDR_HI',
'mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX', 'mmSDMA0_PHYSICAL_ADDR_LO',
'mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX', 'mmSDMA0_POWER_CNTL',
'mmSDMA0_POWER_CNTL_BASE_IDX', 'mmSDMA0_PROGRAM',
'mmSDMA0_PROGRAM_BASE_IDX', 'mmSDMA0_PUB_DUMMY_REG0',
'mmSDMA0_PUB_DUMMY_REG0_BASE_IDX', 'mmSDMA0_PUB_DUMMY_REG1',
'mmSDMA0_PUB_DUMMY_REG1_BASE_IDX', 'mmSDMA0_PUB_DUMMY_REG2',
'mmSDMA0_PUB_DUMMY_REG2_BASE_IDX', 'mmSDMA0_PUB_DUMMY_REG3',
'mmSDMA0_PUB_DUMMY_REG3_BASE_IDX', 'mmSDMA0_PUB_REG_TYPE0',
'mmSDMA0_PUB_REG_TYPE0_BASE_IDX', 'mmSDMA0_PUB_REG_TYPE1',
'mmSDMA0_PUB_REG_TYPE1_BASE_IDX', 'mmSDMA0_PUB_REG_TYPE2',
'mmSDMA0_PUB_REG_TYPE2_BASE_IDX', 'mmSDMA0_PUB_REG_TYPE3',
'mmSDMA0_PUB_REG_TYPE3_BASE_IDX', 'mmSDMA0_QUEUE_RESET_REQ',
'mmSDMA0_QUEUE_RESET_REQ_BASE_IDX', 'mmSDMA0_RB_RPTR_FETCH',
'mmSDMA0_RB_RPTR_FETCH_BASE_IDX', 'mmSDMA0_RB_RPTR_FETCH_HI',
'mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX', 'mmSDMA0_RD_BURST_CNTL',
'mmSDMA0_RD_BURST_CNTL_BASE_IDX', 'mmSDMA0_RELAX_ORDERING_LUT',
'mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX',
'mmSDMA0_RLC0_CONTEXT_STATUS',
'mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX',
'mmSDMA0_RLC0_CSA_ADDR_HI', 'mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC0_CSA_ADDR_LO', 'mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC0_DOORBELL', 'mmSDMA0_RLC0_DOORBELL_BASE_IDX',
'mmSDMA0_RLC0_DOORBELL_LOG', 'mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX',
'mmSDMA0_RLC0_DOORBELL_OFFSET',
'mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC0_DUMMY_REG',
'mmSDMA0_RLC0_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC0_IB_BASE_HI',
'mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC0_IB_BASE_LO',
'mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC0_IB_CNTL',
'mmSDMA0_RLC0_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC0_IB_OFFSET',
'mmSDMA0_RLC0_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC0_IB_RPTR',
'mmSDMA0_RLC0_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC0_IB_SIZE',
'mmSDMA0_RLC0_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC0_IB_SUB_REMAIN',
'mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_CNTL',
'mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA0',
'mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA1',
'mmSDMA0_RLC0_MIDCMD_DATA10',
'mmSDMA0_RLC0_MIDCMD_DATA10_BASE_IDX',
'mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA2',
'mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA3',
'mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA4',
'mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA5',
'mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA6',
'mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA7',
'mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA8',
'mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA9',
'mmSDMA0_RLC0_MIDCMD_DATA9_BASE_IDX',
'mmSDMA0_RLC0_MINOR_PTR_UPDATE',
'mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC0_PREEMPT',
'mmSDMA0_RLC0_PREEMPT_BASE_IDX', 'mmSDMA0_RLC0_RB_AQL_CNTL',
'mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC0_RB_BASE',
'mmSDMA0_RLC0_RB_BASE_BASE_IDX', 'mmSDMA0_RLC0_RB_BASE_HI',
'mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC0_RB_CNTL',
'mmSDMA0_RLC0_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC0_RB_RPTR',
'mmSDMA0_RLC0_RB_RPTR_ADDR_HI',
'mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC0_RB_RPTR_ADDR_LO',
'mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC0_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC0_RB_RPTR_HI',
'mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC0_RB_WPTR',
'mmSDMA0_RLC0_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC0_RB_WPTR_HI',
'mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX',
'mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI',
'mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO',
'mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC0_RB_WPTR_POLL_CNTL',
'mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA0_RLC0_SKIP_CNTL', 'mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX',
'mmSDMA0_RLC0_STATUS', 'mmSDMA0_RLC0_STATUS_BASE_IDX',
'mmSDMA0_RLC0_WATERMARK', 'mmSDMA0_RLC0_WATERMARK_BASE_IDX',
'mmSDMA0_RLC1_CONTEXT_STATUS',
'mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX',
'mmSDMA0_RLC1_CSA_ADDR_HI', 'mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC1_CSA_ADDR_LO', 'mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC1_DOORBELL', 'mmSDMA0_RLC1_DOORBELL_BASE_IDX',
'mmSDMA0_RLC1_DOORBELL_LOG', 'mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX',
'mmSDMA0_RLC1_DOORBELL_OFFSET',
'mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC1_DUMMY_REG',
'mmSDMA0_RLC1_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC1_IB_BASE_HI',
'mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC1_IB_BASE_LO',
'mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC1_IB_CNTL',
'mmSDMA0_RLC1_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC1_IB_OFFSET',
'mmSDMA0_RLC1_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC1_IB_RPTR',
'mmSDMA0_RLC1_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC1_IB_SIZE',
'mmSDMA0_RLC1_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC1_IB_SUB_REMAIN',
'mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_CNTL',
'mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA0',
'mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA1',
'mmSDMA0_RLC1_MIDCMD_DATA10',
'mmSDMA0_RLC1_MIDCMD_DATA10_BASE_IDX',
'mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA2',
'mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA3',
'mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA4',
'mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA5',
'mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA6',
'mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA7',
'mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA8',
'mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA9',
'mmSDMA0_RLC1_MIDCMD_DATA9_BASE_IDX',
'mmSDMA0_RLC1_MINOR_PTR_UPDATE',
'mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC1_PREEMPT',
'mmSDMA0_RLC1_PREEMPT_BASE_IDX', 'mmSDMA0_RLC1_RB_AQL_CNTL',
'mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC1_RB_BASE',
'mmSDMA0_RLC1_RB_BASE_BASE_IDX', 'mmSDMA0_RLC1_RB_BASE_HI',
'mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC1_RB_CNTL',
'mmSDMA0_RLC1_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC1_RB_RPTR',
'mmSDMA0_RLC1_RB_RPTR_ADDR_HI',
'mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC1_RB_RPTR_ADDR_LO',
'mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC1_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC1_RB_RPTR_HI',
'mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC1_RB_WPTR',
'mmSDMA0_RLC1_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC1_RB_WPTR_HI',
'mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX',
'mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI',
'mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO',
'mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC1_RB_WPTR_POLL_CNTL',
'mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA0_RLC1_SKIP_CNTL', 'mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX',
'mmSDMA0_RLC1_STATUS', 'mmSDMA0_RLC1_STATUS_BASE_IDX',
'mmSDMA0_RLC1_WATERMARK', 'mmSDMA0_RLC1_WATERMARK_BASE_IDX',
'mmSDMA0_RLC2_CONTEXT_STATUS',
'mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX',
'mmSDMA0_RLC2_CSA_ADDR_HI', 'mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC2_CSA_ADDR_LO', 'mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC2_DOORBELL', 'mmSDMA0_RLC2_DOORBELL_BASE_IDX',
'mmSDMA0_RLC2_DOORBELL_LOG', 'mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX',
'mmSDMA0_RLC2_DOORBELL_OFFSET',
'mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC2_DUMMY_REG',
'mmSDMA0_RLC2_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC2_IB_BASE_HI',
'mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC2_IB_BASE_LO',
'mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC2_IB_CNTL',
'mmSDMA0_RLC2_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC2_IB_OFFSET',
'mmSDMA0_RLC2_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC2_IB_RPTR',
'mmSDMA0_RLC2_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC2_IB_SIZE',
'mmSDMA0_RLC2_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC2_IB_SUB_REMAIN',
'mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_CNTL',
'mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA0',
'mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA1',
'mmSDMA0_RLC2_MIDCMD_DATA10',
'mmSDMA0_RLC2_MIDCMD_DATA10_BASE_IDX',
'mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA2',
'mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA3',
'mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA4',
'mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA5',
'mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA6',
'mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA7',
'mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA8',
'mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA9',
'mmSDMA0_RLC2_MIDCMD_DATA9_BASE_IDX',
'mmSDMA0_RLC2_MINOR_PTR_UPDATE',
'mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC2_PREEMPT',
'mmSDMA0_RLC2_PREEMPT_BASE_IDX', 'mmSDMA0_RLC2_RB_AQL_CNTL',
'mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC2_RB_BASE',
'mmSDMA0_RLC2_RB_BASE_BASE_IDX', 'mmSDMA0_RLC2_RB_BASE_HI',
'mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC2_RB_CNTL',
'mmSDMA0_RLC2_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC2_RB_RPTR',
'mmSDMA0_RLC2_RB_RPTR_ADDR_HI',
'mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC2_RB_RPTR_ADDR_LO',
'mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC2_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC2_RB_RPTR_HI',
'mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC2_RB_WPTR',
'mmSDMA0_RLC2_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC2_RB_WPTR_HI',
'mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX',
'mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI',
'mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO',
'mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC2_RB_WPTR_POLL_CNTL',
'mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA0_RLC2_SKIP_CNTL', 'mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX',
'mmSDMA0_RLC2_STATUS', 'mmSDMA0_RLC2_STATUS_BASE_IDX',
'mmSDMA0_RLC2_WATERMARK', 'mmSDMA0_RLC2_WATERMARK_BASE_IDX',
'mmSDMA0_RLC3_CONTEXT_STATUS',
'mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX',
'mmSDMA0_RLC3_CSA_ADDR_HI', 'mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC3_CSA_ADDR_LO', 'mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC3_DOORBELL', 'mmSDMA0_RLC3_DOORBELL_BASE_IDX',
'mmSDMA0_RLC3_DOORBELL_LOG', 'mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX',
'mmSDMA0_RLC3_DOORBELL_OFFSET',
'mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC3_DUMMY_REG',
'mmSDMA0_RLC3_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC3_IB_BASE_HI',
'mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC3_IB_BASE_LO',
'mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC3_IB_CNTL',
'mmSDMA0_RLC3_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC3_IB_OFFSET',
'mmSDMA0_RLC3_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC3_IB_RPTR',
'mmSDMA0_RLC3_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC3_IB_SIZE',
'mmSDMA0_RLC3_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC3_IB_SUB_REMAIN',
'mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_CNTL',
'mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA0',
'mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA1',
'mmSDMA0_RLC3_MIDCMD_DATA10',
'mmSDMA0_RLC3_MIDCMD_DATA10_BASE_IDX',
'mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA2',
'mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA3',
'mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA4',
'mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA5',
'mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA6',
'mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA7',
'mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA8',
'mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA9',
'mmSDMA0_RLC3_MIDCMD_DATA9_BASE_IDX',
'mmSDMA0_RLC3_MINOR_PTR_UPDATE',
'mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC3_PREEMPT',
'mmSDMA0_RLC3_PREEMPT_BASE_IDX', 'mmSDMA0_RLC3_RB_AQL_CNTL',
'mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC3_RB_BASE',
'mmSDMA0_RLC3_RB_BASE_BASE_IDX', 'mmSDMA0_RLC3_RB_BASE_HI',
'mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC3_RB_CNTL',
'mmSDMA0_RLC3_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC3_RB_RPTR',
'mmSDMA0_RLC3_RB_RPTR_ADDR_HI',
'mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC3_RB_RPTR_ADDR_LO',
'mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC3_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC3_RB_RPTR_HI',
'mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC3_RB_WPTR',
'mmSDMA0_RLC3_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC3_RB_WPTR_HI',
'mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX',
'mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI',
'mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO',
'mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC3_RB_WPTR_POLL_CNTL',
'mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA0_RLC3_SKIP_CNTL', 'mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX',
'mmSDMA0_RLC3_STATUS', 'mmSDMA0_RLC3_STATUS_BASE_IDX',
'mmSDMA0_RLC3_WATERMARK', 'mmSDMA0_RLC3_WATERMARK_BASE_IDX',
'mmSDMA0_RLC4_CONTEXT_STATUS',
'mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX',
'mmSDMA0_RLC4_CSA_ADDR_HI', 'mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC4_CSA_ADDR_LO', 'mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC4_DOORBELL', 'mmSDMA0_RLC4_DOORBELL_BASE_IDX',
'mmSDMA0_RLC4_DOORBELL_LOG', 'mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX',
'mmSDMA0_RLC4_DOORBELL_OFFSET',
'mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC4_DUMMY_REG',
'mmSDMA0_RLC4_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC4_IB_BASE_HI',
'mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC4_IB_BASE_LO',
'mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC4_IB_CNTL',
'mmSDMA0_RLC4_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC4_IB_OFFSET',
'mmSDMA0_RLC4_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC4_IB_RPTR',
'mmSDMA0_RLC4_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC4_IB_SIZE',
'mmSDMA0_RLC4_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC4_IB_SUB_REMAIN',
'mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_CNTL',
'mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA0',
'mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA1',
'mmSDMA0_RLC4_MIDCMD_DATA10',
'mmSDMA0_RLC4_MIDCMD_DATA10_BASE_IDX',
'mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA2',
'mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA3',
'mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA4',
'mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA5',
'mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA6',
'mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA7',
'mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA8',
'mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA9',
'mmSDMA0_RLC4_MIDCMD_DATA9_BASE_IDX',
'mmSDMA0_RLC4_MINOR_PTR_UPDATE',
'mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC4_PREEMPT',
'mmSDMA0_RLC4_PREEMPT_BASE_IDX', 'mmSDMA0_RLC4_RB_AQL_CNTL',
'mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC4_RB_BASE',
'mmSDMA0_RLC4_RB_BASE_BASE_IDX', 'mmSDMA0_RLC4_RB_BASE_HI',
'mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC4_RB_CNTL',
'mmSDMA0_RLC4_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC4_RB_RPTR',
'mmSDMA0_RLC4_RB_RPTR_ADDR_HI',
'mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC4_RB_RPTR_ADDR_LO',
'mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC4_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC4_RB_RPTR_HI',
'mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC4_RB_WPTR',
'mmSDMA0_RLC4_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC4_RB_WPTR_HI',
'mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX',
'mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI',
'mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO',
'mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC4_RB_WPTR_POLL_CNTL',
'mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA0_RLC4_SKIP_CNTL', 'mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX',
'mmSDMA0_RLC4_STATUS', 'mmSDMA0_RLC4_STATUS_BASE_IDX',
'mmSDMA0_RLC4_WATERMARK', 'mmSDMA0_RLC4_WATERMARK_BASE_IDX',
'mmSDMA0_RLC5_CONTEXT_STATUS',
'mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX',
'mmSDMA0_RLC5_CSA_ADDR_HI', 'mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC5_CSA_ADDR_LO', 'mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC5_DOORBELL', 'mmSDMA0_RLC5_DOORBELL_BASE_IDX',
'mmSDMA0_RLC5_DOORBELL_LOG', 'mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX',
'mmSDMA0_RLC5_DOORBELL_OFFSET',
'mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC5_DUMMY_REG',
'mmSDMA0_RLC5_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC5_IB_BASE_HI',
'mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC5_IB_BASE_LO',
'mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC5_IB_CNTL',
'mmSDMA0_RLC5_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC5_IB_OFFSET',
'mmSDMA0_RLC5_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC5_IB_RPTR',
'mmSDMA0_RLC5_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC5_IB_SIZE',
'mmSDMA0_RLC5_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC5_IB_SUB_REMAIN',
'mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_CNTL',
'mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA0',
'mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA1',
'mmSDMA0_RLC5_MIDCMD_DATA10',
'mmSDMA0_RLC5_MIDCMD_DATA10_BASE_IDX',
'mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA2',
'mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA3',
'mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA4',
'mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA5',
'mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA6',
'mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA7',
'mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA8',
'mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA9',
'mmSDMA0_RLC5_MIDCMD_DATA9_BASE_IDX',
'mmSDMA0_RLC5_MINOR_PTR_UPDATE',
'mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC5_PREEMPT',
'mmSDMA0_RLC5_PREEMPT_BASE_IDX', 'mmSDMA0_RLC5_RB_AQL_CNTL',
'mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC5_RB_BASE',
'mmSDMA0_RLC5_RB_BASE_BASE_IDX', 'mmSDMA0_RLC5_RB_BASE_HI',
'mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC5_RB_CNTL',
'mmSDMA0_RLC5_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC5_RB_RPTR',
'mmSDMA0_RLC5_RB_RPTR_ADDR_HI',
'mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC5_RB_RPTR_ADDR_LO',
'mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC5_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC5_RB_RPTR_HI',
'mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC5_RB_WPTR',
'mmSDMA0_RLC5_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC5_RB_WPTR_HI',
'mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX',
'mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI',
'mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO',
'mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC5_RB_WPTR_POLL_CNTL',
'mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA0_RLC5_SKIP_CNTL', 'mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX',
'mmSDMA0_RLC5_STATUS', 'mmSDMA0_RLC5_STATUS_BASE_IDX',
'mmSDMA0_RLC5_WATERMARK', 'mmSDMA0_RLC5_WATERMARK_BASE_IDX',
'mmSDMA0_RLC6_CONTEXT_STATUS',
'mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX',
'mmSDMA0_RLC6_CSA_ADDR_HI', 'mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC6_CSA_ADDR_LO', 'mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC6_DOORBELL', 'mmSDMA0_RLC6_DOORBELL_BASE_IDX',
'mmSDMA0_RLC6_DOORBELL_LOG', 'mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX',
'mmSDMA0_RLC6_DOORBELL_OFFSET',
'mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC6_DUMMY_REG',
'mmSDMA0_RLC6_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC6_IB_BASE_HI',
'mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC6_IB_BASE_LO',
'mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC6_IB_CNTL',
'mmSDMA0_RLC6_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC6_IB_OFFSET',
'mmSDMA0_RLC6_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC6_IB_RPTR',
'mmSDMA0_RLC6_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC6_IB_SIZE',
'mmSDMA0_RLC6_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC6_IB_SUB_REMAIN',
'mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_CNTL',
'mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA0',
'mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA1',
'mmSDMA0_RLC6_MIDCMD_DATA10',
'mmSDMA0_RLC6_MIDCMD_DATA10_BASE_IDX',
'mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA2',
'mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA3',
'mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA4',
'mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA5',
'mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA6',
'mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA7',
'mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA8',
'mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA9',
'mmSDMA0_RLC6_MIDCMD_DATA9_BASE_IDX',
'mmSDMA0_RLC6_MINOR_PTR_UPDATE',
'mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC6_PREEMPT',
'mmSDMA0_RLC6_PREEMPT_BASE_IDX', 'mmSDMA0_RLC6_RB_AQL_CNTL',
'mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC6_RB_BASE',
'mmSDMA0_RLC6_RB_BASE_BASE_IDX', 'mmSDMA0_RLC6_RB_BASE_HI',
'mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC6_RB_CNTL',
'mmSDMA0_RLC6_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC6_RB_RPTR',
'mmSDMA0_RLC6_RB_RPTR_ADDR_HI',
'mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC6_RB_RPTR_ADDR_LO',
'mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC6_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC6_RB_RPTR_HI',
'mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC6_RB_WPTR',
'mmSDMA0_RLC6_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC6_RB_WPTR_HI',
'mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX',
'mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI',
'mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO',
'mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC6_RB_WPTR_POLL_CNTL',
'mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA0_RLC6_SKIP_CNTL', 'mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX',
'mmSDMA0_RLC6_STATUS', 'mmSDMA0_RLC6_STATUS_BASE_IDX',
'mmSDMA0_RLC6_WATERMARK', 'mmSDMA0_RLC6_WATERMARK_BASE_IDX',
'mmSDMA0_RLC7_CONTEXT_STATUS',
'mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX',
'mmSDMA0_RLC7_CSA_ADDR_HI', 'mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC7_CSA_ADDR_LO', 'mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC7_DOORBELL', 'mmSDMA0_RLC7_DOORBELL_BASE_IDX',
'mmSDMA0_RLC7_DOORBELL_LOG', 'mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX',
'mmSDMA0_RLC7_DOORBELL_OFFSET',
'mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC7_DUMMY_REG',
'mmSDMA0_RLC7_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC7_IB_BASE_HI',
'mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC7_IB_BASE_LO',
'mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC7_IB_CNTL',
'mmSDMA0_RLC7_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC7_IB_OFFSET',
'mmSDMA0_RLC7_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC7_IB_RPTR',
'mmSDMA0_RLC7_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC7_IB_SIZE',
'mmSDMA0_RLC7_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC7_IB_SUB_REMAIN',
'mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_CNTL',
'mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA0',
'mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA1',
'mmSDMA0_RLC7_MIDCMD_DATA10',
'mmSDMA0_RLC7_MIDCMD_DATA10_BASE_IDX',
'mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA2',
'mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA3',
'mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA4',
'mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA5',
'mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA6',
'mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA7',
'mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA8',
'mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA9',
'mmSDMA0_RLC7_MIDCMD_DATA9_BASE_IDX',
'mmSDMA0_RLC7_MINOR_PTR_UPDATE',
'mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC7_PREEMPT',
'mmSDMA0_RLC7_PREEMPT_BASE_IDX', 'mmSDMA0_RLC7_RB_AQL_CNTL',
'mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC7_RB_BASE',
'mmSDMA0_RLC7_RB_BASE_BASE_IDX', 'mmSDMA0_RLC7_RB_BASE_HI',
'mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC7_RB_CNTL',
'mmSDMA0_RLC7_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC7_RB_RPTR',
'mmSDMA0_RLC7_RB_RPTR_ADDR_HI',
'mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC7_RB_RPTR_ADDR_LO',
'mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC7_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC7_RB_RPTR_HI',
'mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC7_RB_WPTR',
'mmSDMA0_RLC7_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC7_RB_WPTR_HI',
'mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX',
'mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI',
'mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO',
'mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA0_RLC7_RB_WPTR_POLL_CNTL',
'mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA0_RLC7_SKIP_CNTL', 'mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX',
'mmSDMA0_RLC7_STATUS', 'mmSDMA0_RLC7_STATUS_BASE_IDX',
'mmSDMA0_RLC7_WATERMARK', 'mmSDMA0_RLC7_WATERMARK_BASE_IDX',
'mmSDMA0_SCRATCH_RAM_ADDR', 'mmSDMA0_SCRATCH_RAM_ADDR_BASE_IDX',
'mmSDMA0_SCRATCH_RAM_DATA', 'mmSDMA0_SCRATCH_RAM_DATA_BASE_IDX',
'mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL',
'mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX',
'mmSDMA0_STATUS1_REG', 'mmSDMA0_STATUS1_REG_BASE_IDX',
'mmSDMA0_STATUS2_REG', 'mmSDMA0_STATUS2_REG_BASE_IDX',
'mmSDMA0_STATUS3_REG', 'mmSDMA0_STATUS3_REG_BASE_IDX',
'mmSDMA0_STATUS4_REG', 'mmSDMA0_STATUS4_REG_BASE_IDX',
'mmSDMA0_STATUS5_REG', 'mmSDMA0_STATUS5_REG_BASE_IDX',
'mmSDMA0_STATUS_REG', 'mmSDMA0_STATUS_REG_BASE_IDX',
'mmSDMA0_TILING_CONFIG', 'mmSDMA0_TILING_CONFIG_BASE_IDX',
'mmSDMA0_TIMESTAMP_CNTL', 'mmSDMA0_TIMESTAMP_CNTL_BASE_IDX',
'mmSDMA0_TLBI_GCR_CNTL', 'mmSDMA0_TLBI_GCR_CNTL_BASE_IDX',
'mmSDMA0_UCODE_ADDR', 'mmSDMA0_UCODE_ADDR_BASE_IDX',
'mmSDMA0_UCODE_CHECKSUM', 'mmSDMA0_UCODE_CHECKSUM_BASE_IDX',
'mmSDMA0_UCODE_DATA', 'mmSDMA0_UCODE_DATA_BASE_IDX',
'mmSDMA0_UTCL1_CNTL', 'mmSDMA0_UTCL1_CNTL_BASE_IDX',
'mmSDMA0_UTCL1_INV0', 'mmSDMA0_UTCL1_INV0_BASE_IDX',
'mmSDMA0_UTCL1_INV1', 'mmSDMA0_UTCL1_INV1_BASE_IDX',
'mmSDMA0_UTCL1_INV2', 'mmSDMA0_UTCL1_INV2_BASE_IDX',
'mmSDMA0_UTCL1_PAGE', 'mmSDMA0_UTCL1_PAGE_BASE_IDX',
'mmSDMA0_UTCL1_RD_STATUS', 'mmSDMA0_UTCL1_RD_STATUS_BASE_IDX',
'mmSDMA0_UTCL1_RD_XNACK0', 'mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX',
'mmSDMA0_UTCL1_RD_XNACK1', 'mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX',
'mmSDMA0_UTCL1_TIMEOUT', 'mmSDMA0_UTCL1_TIMEOUT_BASE_IDX',
'mmSDMA0_UTCL1_WATERMK', 'mmSDMA0_UTCL1_WATERMK_BASE_IDX',
'mmSDMA0_UTCL1_WR_STATUS', 'mmSDMA0_UTCL1_WR_STATUS_BASE_IDX',
'mmSDMA0_UTCL1_WR_XNACK0', 'mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX',
'mmSDMA0_UTCL1_WR_XNACK1', 'mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX',
'mmSDMA0_VERSION', 'mmSDMA0_VERSION_BASE_IDX',
'mmSDMA0_VF_ENABLE', 'mmSDMA0_VF_ENABLE_BASE_IDX',
'mmSDMA0_VIRT_RESET_REQ', 'mmSDMA0_VIRT_RESET_REQ_BASE_IDX',
'mmSDMA0_VM_CNTL', 'mmSDMA0_VM_CNTL_BASE_IDX',
'mmSDMA0_VM_CTX_CNTL', 'mmSDMA0_VM_CTX_CNTL_BASE_IDX',
'mmSDMA0_VM_CTX_HI', 'mmSDMA0_VM_CTX_HI_BASE_IDX',
'mmSDMA0_VM_CTX_LO', 'mmSDMA0_VM_CTX_LO_BASE_IDX',
'mmSDMA1_ACTIVE_FCN_ID', 'mmSDMA1_ACTIVE_FCN_ID_BASE_IDX',
'mmSDMA1_AQL_STATUS', 'mmSDMA1_AQL_STATUS_BASE_IDX',
'mmSDMA1_ATOMIC_CNTL', 'mmSDMA1_ATOMIC_CNTL_BASE_IDX',
'mmSDMA1_ATOMIC_PREOP_HI', 'mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX',
'mmSDMA1_ATOMIC_PREOP_LO', 'mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX',
'mmSDMA1_BA_THRESHOLD', 'mmSDMA1_BA_THRESHOLD_BASE_IDX',
'mmSDMA1_CHICKEN_BITS', 'mmSDMA1_CHICKEN_BITS_2',
'mmSDMA1_CHICKEN_BITS_2_BASE_IDX',
'mmSDMA1_CHICKEN_BITS_BASE_IDX', 'mmSDMA1_CLK_CTRL',
'mmSDMA1_CLK_CTRL_BASE_IDX', 'mmSDMA1_CLOCK_GATING_REG',
'mmSDMA1_CLOCK_GATING_REG_BASE_IDX', 'mmSDMA1_CNTL',
'mmSDMA1_CNTL_BASE_IDX', 'mmSDMA1_CONTEXT_REG_TYPE0',
'mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX', 'mmSDMA1_CONTEXT_REG_TYPE1',
'mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX', 'mmSDMA1_CONTEXT_REG_TYPE2',
'mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX', 'mmSDMA1_CONTEXT_REG_TYPE3',
'mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX', 'mmSDMA1_CRD_CNTL',
'mmSDMA1_CRD_CNTL_BASE_IDX', 'mmSDMA1_DEC_START',
'mmSDMA1_DEC_START_BASE_IDX', 'mmSDMA1_EA_DBIT_ADDR_DATA',
'mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX',
'mmSDMA1_EA_DBIT_ADDR_INDEX',
'mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX', 'mmSDMA1_EDC_CONFIG',
'mmSDMA1_EDC_CONFIG_BASE_IDX', 'mmSDMA1_EDC_COUNTER',
'mmSDMA1_EDC_COUNTER_BASE_IDX', 'mmSDMA1_EDC_COUNTER_CLEAR',
'mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX', 'mmSDMA1_ERROR_LOG',
'mmSDMA1_ERROR_LOG_BASE_IDX', 'mmSDMA1_F32_CNTL',
'mmSDMA1_F32_CNTL_BASE_IDX', 'mmSDMA1_F32_COUNTER',
'mmSDMA1_F32_COUNTER_BASE_IDX', 'mmSDMA1_FREEZE',
'mmSDMA1_FREEZE_BASE_IDX', 'mmSDMA1_GB_ADDR_CONFIG',
'mmSDMA1_GB_ADDR_CONFIG_BASE_IDX', 'mmSDMA1_GB_ADDR_CONFIG_READ',
'mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX',
'mmSDMA1_GFX_CONTEXT_CNTL', 'mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX',
'mmSDMA1_GFX_CONTEXT_STATUS',
'mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX', 'mmSDMA1_GFX_CSA_ADDR_HI',
'mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX', 'mmSDMA1_GFX_CSA_ADDR_LO',
'mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX', 'mmSDMA1_GFX_DOORBELL',
'mmSDMA1_GFX_DOORBELL_BASE_IDX', 'mmSDMA1_GFX_DOORBELL_LOG',
'mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX',
'mmSDMA1_GFX_DOORBELL_OFFSET',
'mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_GFX_DUMMY_REG',
'mmSDMA1_GFX_DUMMY_REG_BASE_IDX', 'mmSDMA1_GFX_IB_BASE_HI',
'mmSDMA1_GFX_IB_BASE_HI_BASE_IDX', 'mmSDMA1_GFX_IB_BASE_LO',
'mmSDMA1_GFX_IB_BASE_LO_BASE_IDX', 'mmSDMA1_GFX_IB_CNTL',
'mmSDMA1_GFX_IB_CNTL_BASE_IDX', 'mmSDMA1_GFX_IB_OFFSET',
'mmSDMA1_GFX_IB_OFFSET_BASE_IDX', 'mmSDMA1_GFX_IB_RPTR',
'mmSDMA1_GFX_IB_RPTR_BASE_IDX', 'mmSDMA1_GFX_IB_SIZE',
'mmSDMA1_GFX_IB_SIZE_BASE_IDX', 'mmSDMA1_GFX_IB_SUB_REMAIN',
'mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_CNTL',
'mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA0',
'mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA1',
'mmSDMA1_GFX_MIDCMD_DATA10', 'mmSDMA1_GFX_MIDCMD_DATA10_BASE_IDX',
'mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA2',
'mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA3',
'mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA4',
'mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA5',
'mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA6',
'mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA7',
'mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA8',
'mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA9',
'mmSDMA1_GFX_MIDCMD_DATA9_BASE_IDX',
'mmSDMA1_GFX_MINOR_PTR_UPDATE',
'mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_GFX_PREEMPT',
'mmSDMA1_GFX_PREEMPT_BASE_IDX', 'mmSDMA1_GFX_RB_AQL_CNTL',
'mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_GFX_RB_BASE',
'mmSDMA1_GFX_RB_BASE_BASE_IDX', 'mmSDMA1_GFX_RB_BASE_HI',
'mmSDMA1_GFX_RB_BASE_HI_BASE_IDX', 'mmSDMA1_GFX_RB_CNTL',
'mmSDMA1_GFX_RB_CNTL_BASE_IDX', 'mmSDMA1_GFX_RB_RPTR',
'mmSDMA1_GFX_RB_RPTR_ADDR_HI',
'mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA1_GFX_RB_RPTR_ADDR_LO',
'mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA1_GFX_RB_RPTR_BASE_IDX', 'mmSDMA1_GFX_RB_RPTR_HI',
'mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_GFX_RB_WPTR',
'mmSDMA1_GFX_RB_WPTR_BASE_IDX', 'mmSDMA1_GFX_RB_WPTR_HI',
'mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX',
'mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI',
'mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO',
'mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA1_GFX_RB_WPTR_POLL_CNTL',
'mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX', 'mmSDMA1_GFX_SKIP_CNTL',
'mmSDMA1_GFX_SKIP_CNTL_BASE_IDX', 'mmSDMA1_GFX_STATUS',
'mmSDMA1_GFX_STATUS_BASE_IDX', 'mmSDMA1_GFX_WATERMARK',
'mmSDMA1_GFX_WATERMARK_BASE_IDX', 'mmSDMA1_GLOBAL_TIMESTAMP_HI',
'mmSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX',
'mmSDMA1_GLOBAL_TIMESTAMP_LO',
'mmSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX', 'mmSDMA1_HBM_PAGE_CONFIG',
'mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX', 'mmSDMA1_HOLE_ADDR_HI',
'mmSDMA1_HOLE_ADDR_HI_BASE_IDX', 'mmSDMA1_HOLE_ADDR_LO',
'mmSDMA1_HOLE_ADDR_LO_BASE_IDX', 'mmSDMA1_IB_OFFSET_FETCH',
'mmSDMA1_IB_OFFSET_FETCH_BASE_IDX', 'mmSDMA1_ID',
'mmSDMA1_ID_BASE_IDX', 'mmSDMA1_INT_STATUS',
'mmSDMA1_INT_STATUS_BASE_IDX', 'mmSDMA1_PAGE_CONTEXT_STATUS',
'mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX',
'mmSDMA1_PAGE_CSA_ADDR_HI', 'mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX',
'mmSDMA1_PAGE_CSA_ADDR_LO', 'mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX',
'mmSDMA1_PAGE_DOORBELL', 'mmSDMA1_PAGE_DOORBELL_BASE_IDX',
'mmSDMA1_PAGE_DOORBELL_LOG', 'mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX',
'mmSDMA1_PAGE_DOORBELL_OFFSET',
'mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_PAGE_DUMMY_REG',
'mmSDMA1_PAGE_DUMMY_REG_BASE_IDX', 'mmSDMA1_PAGE_IB_BASE_HI',
'mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX', 'mmSDMA1_PAGE_IB_BASE_LO',
'mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX', 'mmSDMA1_PAGE_IB_CNTL',
'mmSDMA1_PAGE_IB_CNTL_BASE_IDX', 'mmSDMA1_PAGE_IB_OFFSET',
'mmSDMA1_PAGE_IB_OFFSET_BASE_IDX', 'mmSDMA1_PAGE_IB_RPTR',
'mmSDMA1_PAGE_IB_RPTR_BASE_IDX', 'mmSDMA1_PAGE_IB_SIZE',
'mmSDMA1_PAGE_IB_SIZE_BASE_IDX', 'mmSDMA1_PAGE_IB_SUB_REMAIN',
'mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_CNTL',
'mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA0',
'mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA1',
'mmSDMA1_PAGE_MIDCMD_DATA10',
'mmSDMA1_PAGE_MIDCMD_DATA10_BASE_IDX',
'mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA2',
'mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA3',
'mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA4',
'mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA5',
'mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA6',
'mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA7',
'mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA8',
'mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA9',
'mmSDMA1_PAGE_MIDCMD_DATA9_BASE_IDX',
'mmSDMA1_PAGE_MINOR_PTR_UPDATE',
'mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_PAGE_PREEMPT',
'mmSDMA1_PAGE_PREEMPT_BASE_IDX', 'mmSDMA1_PAGE_RB_AQL_CNTL',
'mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_PAGE_RB_BASE',
'mmSDMA1_PAGE_RB_BASE_BASE_IDX', 'mmSDMA1_PAGE_RB_BASE_HI',
'mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX', 'mmSDMA1_PAGE_RB_CNTL',
'mmSDMA1_PAGE_RB_CNTL_BASE_IDX', 'mmSDMA1_PAGE_RB_RPTR',
'mmSDMA1_PAGE_RB_RPTR_ADDR_HI',
'mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA1_PAGE_RB_RPTR_ADDR_LO',
'mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA1_PAGE_RB_RPTR_BASE_IDX', 'mmSDMA1_PAGE_RB_RPTR_HI',
'mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_PAGE_RB_WPTR',
'mmSDMA1_PAGE_RB_WPTR_BASE_IDX', 'mmSDMA1_PAGE_RB_WPTR_HI',
'mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX',
'mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI',
'mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO',
'mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA1_PAGE_RB_WPTR_POLL_CNTL',
'mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA1_PAGE_SKIP_CNTL', 'mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX',
'mmSDMA1_PAGE_STATUS', 'mmSDMA1_PAGE_STATUS_BASE_IDX',
'mmSDMA1_PAGE_WATERMARK', 'mmSDMA1_PAGE_WATERMARK_BASE_IDX',
'mmSDMA1_PERFCNT_MISC_CNTL', 'mmSDMA1_PERFCNT_MISC_CNTL_BASE_IDX',
'mmSDMA1_PERFCNT_PERFCOUNTER0_CFG',
'mmSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX',
'mmSDMA1_PERFCNT_PERFCOUNTER1_CFG',
'mmSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX',
'mmSDMA1_PERFCNT_PERFCOUNTER_HI',
'mmSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX',
'mmSDMA1_PERFCNT_PERFCOUNTER_LO',
'mmSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX',
'mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL',
'mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
'mmSDMA1_PERFCOUNTER0_HI', 'mmSDMA1_PERFCOUNTER0_HI_BASE_IDX',
'mmSDMA1_PERFCOUNTER0_LO', 'mmSDMA1_PERFCOUNTER0_LO_BASE_IDX',
'mmSDMA1_PERFCOUNTER0_SELECT', 'mmSDMA1_PERFCOUNTER0_SELECT1',
'mmSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmSDMA1_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSDMA1_PERFCOUNTER1_HI',
'mmSDMA1_PERFCOUNTER1_HI_BASE_IDX', 'mmSDMA1_PERFCOUNTER1_LO',
'mmSDMA1_PERFCOUNTER1_LO_BASE_IDX', 'mmSDMA1_PERFCOUNTER1_SELECT',
'mmSDMA1_PERFCOUNTER1_SELECT1',
'mmSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmSDMA1_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSDMA1_PG_CNTL',
'mmSDMA1_PG_CNTL_BASE_IDX', 'mmSDMA1_PG_CTX_CNTL',
'mmSDMA1_PG_CTX_CNTL_BASE_IDX', 'mmSDMA1_PG_CTX_HI',
'mmSDMA1_PG_CTX_HI_BASE_IDX', 'mmSDMA1_PG_CTX_LO',
'mmSDMA1_PG_CTX_LO_BASE_IDX', 'mmSDMA1_PHASE0_QUANTUM',
'mmSDMA1_PHASE0_QUANTUM_BASE_IDX', 'mmSDMA1_PHASE1_QUANTUM',
'mmSDMA1_PHASE1_QUANTUM_BASE_IDX', 'mmSDMA1_PHASE2_QUANTUM',
'mmSDMA1_PHASE2_QUANTUM_BASE_IDX', 'mmSDMA1_PHYSICAL_ADDR_HI',
'mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX', 'mmSDMA1_PHYSICAL_ADDR_LO',
'mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX', 'mmSDMA1_POWER_CNTL',
'mmSDMA1_POWER_CNTL_BASE_IDX', 'mmSDMA1_PROGRAM',
'mmSDMA1_PROGRAM_BASE_IDX', 'mmSDMA1_PUB_DUMMY_REG0',
'mmSDMA1_PUB_DUMMY_REG0_BASE_IDX', 'mmSDMA1_PUB_DUMMY_REG1',
'mmSDMA1_PUB_DUMMY_REG1_BASE_IDX', 'mmSDMA1_PUB_DUMMY_REG2',
'mmSDMA1_PUB_DUMMY_REG2_BASE_IDX', 'mmSDMA1_PUB_DUMMY_REG3',
'mmSDMA1_PUB_DUMMY_REG3_BASE_IDX', 'mmSDMA1_PUB_REG_TYPE0',
'mmSDMA1_PUB_REG_TYPE0_BASE_IDX', 'mmSDMA1_PUB_REG_TYPE1',
'mmSDMA1_PUB_REG_TYPE1_BASE_IDX', 'mmSDMA1_PUB_REG_TYPE2',
'mmSDMA1_PUB_REG_TYPE2_BASE_IDX', 'mmSDMA1_PUB_REG_TYPE3',
'mmSDMA1_PUB_REG_TYPE3_BASE_IDX', 'mmSDMA1_QUEUE_RESET_REQ',
'mmSDMA1_QUEUE_RESET_REQ_BASE_IDX', 'mmSDMA1_RB_RPTR_FETCH',
'mmSDMA1_RB_RPTR_FETCH_BASE_IDX', 'mmSDMA1_RB_RPTR_FETCH_HI',
'mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX', 'mmSDMA1_RD_BURST_CNTL',
'mmSDMA1_RD_BURST_CNTL_BASE_IDX', 'mmSDMA1_RELAX_ORDERING_LUT',
'mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX',
'mmSDMA1_RLC0_CONTEXT_STATUS',
'mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX',
'mmSDMA1_RLC0_CSA_ADDR_HI', 'mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC0_CSA_ADDR_LO', 'mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC0_DOORBELL', 'mmSDMA1_RLC0_DOORBELL_BASE_IDX',
'mmSDMA1_RLC0_DOORBELL_LOG', 'mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX',
'mmSDMA1_RLC0_DOORBELL_OFFSET',
'mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC0_DUMMY_REG',
'mmSDMA1_RLC0_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC0_IB_BASE_HI',
'mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC0_IB_BASE_LO',
'mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC0_IB_CNTL',
'mmSDMA1_RLC0_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC0_IB_OFFSET',
'mmSDMA1_RLC0_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC0_IB_RPTR',
'mmSDMA1_RLC0_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC0_IB_SIZE',
'mmSDMA1_RLC0_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC0_IB_SUB_REMAIN',
'mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_CNTL',
'mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA0',
'mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA1',
'mmSDMA1_RLC0_MIDCMD_DATA10',
'mmSDMA1_RLC0_MIDCMD_DATA10_BASE_IDX',
'mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA2',
'mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA3',
'mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA4',
'mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA5',
'mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA6',
'mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA7',
'mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA8',
'mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA9',
'mmSDMA1_RLC0_MIDCMD_DATA9_BASE_IDX',
'mmSDMA1_RLC0_MINOR_PTR_UPDATE',
'mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC0_PREEMPT',
'mmSDMA1_RLC0_PREEMPT_BASE_IDX', 'mmSDMA1_RLC0_RB_AQL_CNTL',
'mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC0_RB_BASE',
'mmSDMA1_RLC0_RB_BASE_BASE_IDX', 'mmSDMA1_RLC0_RB_BASE_HI',
'mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC0_RB_CNTL',
'mmSDMA1_RLC0_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC0_RB_RPTR',
'mmSDMA1_RLC0_RB_RPTR_ADDR_HI',
'mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC0_RB_RPTR_ADDR_LO',
'mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC0_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC0_RB_RPTR_HI',
'mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC0_RB_WPTR',
'mmSDMA1_RLC0_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC0_RB_WPTR_HI',
'mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX',
'mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI',
'mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO',
'mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC0_RB_WPTR_POLL_CNTL',
'mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA1_RLC0_SKIP_CNTL', 'mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX',
'mmSDMA1_RLC0_STATUS', 'mmSDMA1_RLC0_STATUS_BASE_IDX',
'mmSDMA1_RLC0_WATERMARK', 'mmSDMA1_RLC0_WATERMARK_BASE_IDX',
'mmSDMA1_RLC1_CONTEXT_STATUS',
'mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX',
'mmSDMA1_RLC1_CSA_ADDR_HI', 'mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC1_CSA_ADDR_LO', 'mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC1_DOORBELL', 'mmSDMA1_RLC1_DOORBELL_BASE_IDX',
'mmSDMA1_RLC1_DOORBELL_LOG', 'mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX',
'mmSDMA1_RLC1_DOORBELL_OFFSET',
'mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC1_DUMMY_REG',
'mmSDMA1_RLC1_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC1_IB_BASE_HI',
'mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC1_IB_BASE_LO',
'mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC1_IB_CNTL',
'mmSDMA1_RLC1_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC1_IB_OFFSET',
'mmSDMA1_RLC1_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC1_IB_RPTR',
'mmSDMA1_RLC1_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC1_IB_SIZE',
'mmSDMA1_RLC1_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC1_IB_SUB_REMAIN',
'mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_CNTL',
'mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA0',
'mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA1',
'mmSDMA1_RLC1_MIDCMD_DATA10',
'mmSDMA1_RLC1_MIDCMD_DATA10_BASE_IDX',
'mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA2',
'mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA3',
'mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA4',
'mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA5',
'mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA6',
'mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA7',
'mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA8',
'mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA9',
'mmSDMA1_RLC1_MIDCMD_DATA9_BASE_IDX',
'mmSDMA1_RLC1_MINOR_PTR_UPDATE',
'mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC1_PREEMPT',
'mmSDMA1_RLC1_PREEMPT_BASE_IDX', 'mmSDMA1_RLC1_RB_AQL_CNTL',
'mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC1_RB_BASE',
'mmSDMA1_RLC1_RB_BASE_BASE_IDX', 'mmSDMA1_RLC1_RB_BASE_HI',
'mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC1_RB_CNTL',
'mmSDMA1_RLC1_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC1_RB_RPTR',
'mmSDMA1_RLC1_RB_RPTR_ADDR_HI',
'mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC1_RB_RPTR_ADDR_LO',
'mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC1_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC1_RB_RPTR_HI',
'mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC1_RB_WPTR',
'mmSDMA1_RLC1_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC1_RB_WPTR_HI',
'mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX',
'mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI',
'mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO',
'mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC1_RB_WPTR_POLL_CNTL',
'mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA1_RLC1_SKIP_CNTL', 'mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX',
'mmSDMA1_RLC1_STATUS', 'mmSDMA1_RLC1_STATUS_BASE_IDX',
'mmSDMA1_RLC1_WATERMARK', 'mmSDMA1_RLC1_WATERMARK_BASE_IDX',
'mmSDMA1_RLC2_CONTEXT_STATUS',
'mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX',
'mmSDMA1_RLC2_CSA_ADDR_HI', 'mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC2_CSA_ADDR_LO', 'mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC2_DOORBELL', 'mmSDMA1_RLC2_DOORBELL_BASE_IDX',
'mmSDMA1_RLC2_DOORBELL_LOG', 'mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX',
'mmSDMA1_RLC2_DOORBELL_OFFSET',
'mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC2_DUMMY_REG',
'mmSDMA1_RLC2_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC2_IB_BASE_HI',
'mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC2_IB_BASE_LO',
'mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC2_IB_CNTL',
'mmSDMA1_RLC2_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC2_IB_OFFSET',
'mmSDMA1_RLC2_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC2_IB_RPTR',
'mmSDMA1_RLC2_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC2_IB_SIZE',
'mmSDMA1_RLC2_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC2_IB_SUB_REMAIN',
'mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_CNTL',
'mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA0',
'mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA1',
'mmSDMA1_RLC2_MIDCMD_DATA10',
'mmSDMA1_RLC2_MIDCMD_DATA10_BASE_IDX',
'mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA2',
'mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA3',
'mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA4',
'mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA5',
'mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA6',
'mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA7',
'mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA8',
'mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA9',
'mmSDMA1_RLC2_MIDCMD_DATA9_BASE_IDX',
'mmSDMA1_RLC2_MINOR_PTR_UPDATE',
'mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC2_PREEMPT',
'mmSDMA1_RLC2_PREEMPT_BASE_IDX', 'mmSDMA1_RLC2_RB_AQL_CNTL',
'mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC2_RB_BASE',
'mmSDMA1_RLC2_RB_BASE_BASE_IDX', 'mmSDMA1_RLC2_RB_BASE_HI',
'mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC2_RB_CNTL',
'mmSDMA1_RLC2_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC2_RB_RPTR',
'mmSDMA1_RLC2_RB_RPTR_ADDR_HI',
'mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC2_RB_RPTR_ADDR_LO',
'mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC2_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC2_RB_RPTR_HI',
'mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC2_RB_WPTR',
'mmSDMA1_RLC2_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC2_RB_WPTR_HI',
'mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX',
'mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI',
'mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO',
'mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC2_RB_WPTR_POLL_CNTL',
'mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA1_RLC2_SKIP_CNTL', 'mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX',
'mmSDMA1_RLC2_STATUS', 'mmSDMA1_RLC2_STATUS_BASE_IDX',
'mmSDMA1_RLC2_WATERMARK', 'mmSDMA1_RLC2_WATERMARK_BASE_IDX',
'mmSDMA1_RLC3_CONTEXT_STATUS',
'mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX',
'mmSDMA1_RLC3_CSA_ADDR_HI', 'mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC3_CSA_ADDR_LO', 'mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC3_DOORBELL', 'mmSDMA1_RLC3_DOORBELL_BASE_IDX',
'mmSDMA1_RLC3_DOORBELL_LOG', 'mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX',
'mmSDMA1_RLC3_DOORBELL_OFFSET',
'mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC3_DUMMY_REG',
'mmSDMA1_RLC3_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC3_IB_BASE_HI',
'mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC3_IB_BASE_LO',
'mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC3_IB_CNTL',
'mmSDMA1_RLC3_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC3_IB_OFFSET',
'mmSDMA1_RLC3_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC3_IB_RPTR',
'mmSDMA1_RLC3_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC3_IB_SIZE',
'mmSDMA1_RLC3_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC3_IB_SUB_REMAIN',
'mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_CNTL',
'mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA0',
'mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA1',
'mmSDMA1_RLC3_MIDCMD_DATA10',
'mmSDMA1_RLC3_MIDCMD_DATA10_BASE_IDX',
'mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA2',
'mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA3',
'mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA4',
'mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA5',
'mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA6',
'mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA7',
'mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA8',
'mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA9',
'mmSDMA1_RLC3_MIDCMD_DATA9_BASE_IDX',
'mmSDMA1_RLC3_MINOR_PTR_UPDATE',
'mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC3_PREEMPT',
'mmSDMA1_RLC3_PREEMPT_BASE_IDX', 'mmSDMA1_RLC3_RB_AQL_CNTL',
'mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC3_RB_BASE',
'mmSDMA1_RLC3_RB_BASE_BASE_IDX', 'mmSDMA1_RLC3_RB_BASE_HI',
'mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC3_RB_CNTL',
'mmSDMA1_RLC3_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC3_RB_RPTR',
'mmSDMA1_RLC3_RB_RPTR_ADDR_HI',
'mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC3_RB_RPTR_ADDR_LO',
'mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC3_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC3_RB_RPTR_HI',
'mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC3_RB_WPTR',
'mmSDMA1_RLC3_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC3_RB_WPTR_HI',
'mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX',
'mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI',
'mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO',
'mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC3_RB_WPTR_POLL_CNTL',
'mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA1_RLC3_SKIP_CNTL', 'mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX',
'mmSDMA1_RLC3_STATUS', 'mmSDMA1_RLC3_STATUS_BASE_IDX',
'mmSDMA1_RLC3_WATERMARK', 'mmSDMA1_RLC3_WATERMARK_BASE_IDX',
'mmSDMA1_RLC4_CONTEXT_STATUS',
'mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX',
'mmSDMA1_RLC4_CSA_ADDR_HI', 'mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC4_CSA_ADDR_LO', 'mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC4_DOORBELL', 'mmSDMA1_RLC4_DOORBELL_BASE_IDX',
'mmSDMA1_RLC4_DOORBELL_LOG', 'mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX',
'mmSDMA1_RLC4_DOORBELL_OFFSET',
'mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC4_DUMMY_REG',
'mmSDMA1_RLC4_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC4_IB_BASE_HI',
'mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC4_IB_BASE_LO',
'mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC4_IB_CNTL',
'mmSDMA1_RLC4_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC4_IB_OFFSET',
'mmSDMA1_RLC4_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC4_IB_RPTR',
'mmSDMA1_RLC4_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC4_IB_SIZE',
'mmSDMA1_RLC4_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC4_IB_SUB_REMAIN',
'mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_CNTL',
'mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA0',
'mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA1',
'mmSDMA1_RLC4_MIDCMD_DATA10',
'mmSDMA1_RLC4_MIDCMD_DATA10_BASE_IDX',
'mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA2',
'mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA3',
'mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA4',
'mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA5',
'mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA6',
'mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA7',
'mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA8',
'mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA9',
'mmSDMA1_RLC4_MIDCMD_DATA9_BASE_IDX',
'mmSDMA1_RLC4_MINOR_PTR_UPDATE',
'mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC4_PREEMPT',
'mmSDMA1_RLC4_PREEMPT_BASE_IDX', 'mmSDMA1_RLC4_RB_AQL_CNTL',
'mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC4_RB_BASE',
'mmSDMA1_RLC4_RB_BASE_BASE_IDX', 'mmSDMA1_RLC4_RB_BASE_HI',
'mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC4_RB_CNTL',
'mmSDMA1_RLC4_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC4_RB_RPTR',
'mmSDMA1_RLC4_RB_RPTR_ADDR_HI',
'mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC4_RB_RPTR_ADDR_LO',
'mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC4_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC4_RB_RPTR_HI',
'mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC4_RB_WPTR',
'mmSDMA1_RLC4_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC4_RB_WPTR_HI',
'mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX',
'mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI',
'mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO',
'mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC4_RB_WPTR_POLL_CNTL',
'mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA1_RLC4_SKIP_CNTL', 'mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX',
'mmSDMA1_RLC4_STATUS', 'mmSDMA1_RLC4_STATUS_BASE_IDX',
'mmSDMA1_RLC4_WATERMARK', 'mmSDMA1_RLC4_WATERMARK_BASE_IDX',
'mmSDMA1_RLC5_CONTEXT_STATUS',
'mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX',
'mmSDMA1_RLC5_CSA_ADDR_HI', 'mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC5_CSA_ADDR_LO', 'mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC5_DOORBELL', 'mmSDMA1_RLC5_DOORBELL_BASE_IDX',
'mmSDMA1_RLC5_DOORBELL_LOG', 'mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX',
'mmSDMA1_RLC5_DOORBELL_OFFSET',
'mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC5_DUMMY_REG',
'mmSDMA1_RLC5_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC5_IB_BASE_HI',
'mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC5_IB_BASE_LO',
'mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC5_IB_CNTL',
'mmSDMA1_RLC5_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC5_IB_OFFSET',
'mmSDMA1_RLC5_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC5_IB_RPTR',
'mmSDMA1_RLC5_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC5_IB_SIZE',
'mmSDMA1_RLC5_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC5_IB_SUB_REMAIN',
'mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_CNTL',
'mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA0',
'mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA1',
'mmSDMA1_RLC5_MIDCMD_DATA10',
'mmSDMA1_RLC5_MIDCMD_DATA10_BASE_IDX',
'mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA2',
'mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA3',
'mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA4',
'mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA5',
'mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA6',
'mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA7',
'mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA8',
'mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA9',
'mmSDMA1_RLC5_MIDCMD_DATA9_BASE_IDX',
'mmSDMA1_RLC5_MINOR_PTR_UPDATE',
'mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC5_PREEMPT',
'mmSDMA1_RLC5_PREEMPT_BASE_IDX', 'mmSDMA1_RLC5_RB_AQL_CNTL',
'mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC5_RB_BASE',
'mmSDMA1_RLC5_RB_BASE_BASE_IDX', 'mmSDMA1_RLC5_RB_BASE_HI',
'mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC5_RB_CNTL',
'mmSDMA1_RLC5_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC5_RB_RPTR',
'mmSDMA1_RLC5_RB_RPTR_ADDR_HI',
'mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC5_RB_RPTR_ADDR_LO',
'mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC5_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC5_RB_RPTR_HI',
'mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC5_RB_WPTR',
'mmSDMA1_RLC5_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC5_RB_WPTR_HI',
'mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX',
'mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI',
'mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO',
'mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC5_RB_WPTR_POLL_CNTL',
'mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA1_RLC5_SKIP_CNTL', 'mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX',
'mmSDMA1_RLC5_STATUS', 'mmSDMA1_RLC5_STATUS_BASE_IDX',
'mmSDMA1_RLC5_WATERMARK', 'mmSDMA1_RLC5_WATERMARK_BASE_IDX',
'mmSDMA1_RLC6_CONTEXT_STATUS',
'mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX',
'mmSDMA1_RLC6_CSA_ADDR_HI', 'mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC6_CSA_ADDR_LO', 'mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC6_DOORBELL', 'mmSDMA1_RLC6_DOORBELL_BASE_IDX',
'mmSDMA1_RLC6_DOORBELL_LOG', 'mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX',
'mmSDMA1_RLC6_DOORBELL_OFFSET',
'mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC6_DUMMY_REG',
'mmSDMA1_RLC6_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC6_IB_BASE_HI',
'mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC6_IB_BASE_LO',
'mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC6_IB_CNTL',
'mmSDMA1_RLC6_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC6_IB_OFFSET',
'mmSDMA1_RLC6_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC6_IB_RPTR',
'mmSDMA1_RLC6_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC6_IB_SIZE',
'mmSDMA1_RLC6_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC6_IB_SUB_REMAIN',
'mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_CNTL',
'mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA0',
'mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA1',
'mmSDMA1_RLC6_MIDCMD_DATA10',
'mmSDMA1_RLC6_MIDCMD_DATA10_BASE_IDX',
'mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA2',
'mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA3',
'mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA4',
'mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA5',
'mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA6',
'mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA7',
'mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA8',
'mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA9',
'mmSDMA1_RLC6_MIDCMD_DATA9_BASE_IDX',
'mmSDMA1_RLC6_MINOR_PTR_UPDATE',
'mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC6_PREEMPT',
'mmSDMA1_RLC6_PREEMPT_BASE_IDX', 'mmSDMA1_RLC6_RB_AQL_CNTL',
'mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC6_RB_BASE',
'mmSDMA1_RLC6_RB_BASE_BASE_IDX', 'mmSDMA1_RLC6_RB_BASE_HI',
'mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC6_RB_CNTL',
'mmSDMA1_RLC6_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC6_RB_RPTR',
'mmSDMA1_RLC6_RB_RPTR_ADDR_HI',
'mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC6_RB_RPTR_ADDR_LO',
'mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC6_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC6_RB_RPTR_HI',
'mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC6_RB_WPTR',
'mmSDMA1_RLC6_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC6_RB_WPTR_HI',
'mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX',
'mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI',
'mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO',
'mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC6_RB_WPTR_POLL_CNTL',
'mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA1_RLC6_SKIP_CNTL', 'mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX',
'mmSDMA1_RLC6_STATUS', 'mmSDMA1_RLC6_STATUS_BASE_IDX',
'mmSDMA1_RLC6_WATERMARK', 'mmSDMA1_RLC6_WATERMARK_BASE_IDX',
'mmSDMA1_RLC7_CONTEXT_STATUS',
'mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX',
'mmSDMA1_RLC7_CSA_ADDR_HI', 'mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC7_CSA_ADDR_LO', 'mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC7_DOORBELL', 'mmSDMA1_RLC7_DOORBELL_BASE_IDX',
'mmSDMA1_RLC7_DOORBELL_LOG', 'mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX',
'mmSDMA1_RLC7_DOORBELL_OFFSET',
'mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC7_DUMMY_REG',
'mmSDMA1_RLC7_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC7_IB_BASE_HI',
'mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC7_IB_BASE_LO',
'mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC7_IB_CNTL',
'mmSDMA1_RLC7_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC7_IB_OFFSET',
'mmSDMA1_RLC7_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC7_IB_RPTR',
'mmSDMA1_RLC7_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC7_IB_SIZE',
'mmSDMA1_RLC7_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC7_IB_SUB_REMAIN',
'mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_CNTL',
'mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA0',
'mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA1',
'mmSDMA1_RLC7_MIDCMD_DATA10',
'mmSDMA1_RLC7_MIDCMD_DATA10_BASE_IDX',
'mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA2',
'mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA3',
'mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA4',
'mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA5',
'mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA6',
'mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA7',
'mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA8',
'mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA9',
'mmSDMA1_RLC7_MIDCMD_DATA9_BASE_IDX',
'mmSDMA1_RLC7_MINOR_PTR_UPDATE',
'mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC7_PREEMPT',
'mmSDMA1_RLC7_PREEMPT_BASE_IDX', 'mmSDMA1_RLC7_RB_AQL_CNTL',
'mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC7_RB_BASE',
'mmSDMA1_RLC7_RB_BASE_BASE_IDX', 'mmSDMA1_RLC7_RB_BASE_HI',
'mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC7_RB_CNTL',
'mmSDMA1_RLC7_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC7_RB_RPTR',
'mmSDMA1_RLC7_RB_RPTR_ADDR_HI',
'mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC7_RB_RPTR_ADDR_LO',
'mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC7_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC7_RB_RPTR_HI',
'mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC7_RB_WPTR',
'mmSDMA1_RLC7_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC7_RB_WPTR_HI',
'mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX',
'mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI',
'mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO',
'mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA1_RLC7_RB_WPTR_POLL_CNTL',
'mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA1_RLC7_SKIP_CNTL', 'mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX',
'mmSDMA1_RLC7_STATUS', 'mmSDMA1_RLC7_STATUS_BASE_IDX',
'mmSDMA1_RLC7_WATERMARK', 'mmSDMA1_RLC7_WATERMARK_BASE_IDX',
'mmSDMA1_SCRATCH_RAM_ADDR', 'mmSDMA1_SCRATCH_RAM_ADDR_BASE_IDX',
'mmSDMA1_SCRATCH_RAM_DATA', 'mmSDMA1_SCRATCH_RAM_DATA_BASE_IDX',
'mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL',
'mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX',
'mmSDMA1_STATUS1_REG', 'mmSDMA1_STATUS1_REG_BASE_IDX',
'mmSDMA1_STATUS2_REG', 'mmSDMA1_STATUS2_REG_BASE_IDX',
'mmSDMA1_STATUS3_REG', 'mmSDMA1_STATUS3_REG_BASE_IDX',
'mmSDMA1_STATUS4_REG', 'mmSDMA1_STATUS4_REG_BASE_IDX',
'mmSDMA1_STATUS5_REG', 'mmSDMA1_STATUS5_REG_BASE_IDX',
'mmSDMA1_STATUS_REG', 'mmSDMA1_STATUS_REG_BASE_IDX',
'mmSDMA1_TILING_CONFIG', 'mmSDMA1_TILING_CONFIG_BASE_IDX',
'mmSDMA1_TIMESTAMP_CNTL', 'mmSDMA1_TIMESTAMP_CNTL_BASE_IDX',
'mmSDMA1_TLBI_GCR_CNTL', 'mmSDMA1_TLBI_GCR_CNTL_BASE_IDX',
'mmSDMA1_UCODE_ADDR', 'mmSDMA1_UCODE_ADDR_BASE_IDX',
'mmSDMA1_UCODE_CHECKSUM', 'mmSDMA1_UCODE_CHECKSUM_BASE_IDX',
'mmSDMA1_UCODE_DATA', 'mmSDMA1_UCODE_DATA_BASE_IDX',
'mmSDMA1_UTCL1_CNTL', 'mmSDMA1_UTCL1_CNTL_BASE_IDX',
'mmSDMA1_UTCL1_INV0', 'mmSDMA1_UTCL1_INV0_BASE_IDX',
'mmSDMA1_UTCL1_INV1', 'mmSDMA1_UTCL1_INV1_BASE_IDX',
'mmSDMA1_UTCL1_INV2', 'mmSDMA1_UTCL1_INV2_BASE_IDX',
'mmSDMA1_UTCL1_PAGE', 'mmSDMA1_UTCL1_PAGE_BASE_IDX',
'mmSDMA1_UTCL1_RD_STATUS', 'mmSDMA1_UTCL1_RD_STATUS_BASE_IDX',
'mmSDMA1_UTCL1_RD_XNACK0', 'mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX',
'mmSDMA1_UTCL1_RD_XNACK1', 'mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX',
'mmSDMA1_UTCL1_TIMEOUT', 'mmSDMA1_UTCL1_TIMEOUT_BASE_IDX',
'mmSDMA1_UTCL1_WATERMK', 'mmSDMA1_UTCL1_WATERMK_BASE_IDX',
'mmSDMA1_UTCL1_WR_STATUS', 'mmSDMA1_UTCL1_WR_STATUS_BASE_IDX',
'mmSDMA1_UTCL1_WR_XNACK0', 'mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX',
'mmSDMA1_UTCL1_WR_XNACK1', 'mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX',
'mmSDMA1_VERSION', 'mmSDMA1_VERSION_BASE_IDX',
'mmSDMA1_VF_ENABLE', 'mmSDMA1_VF_ENABLE_BASE_IDX',
'mmSDMA1_VIRT_RESET_REQ', 'mmSDMA1_VIRT_RESET_REQ_BASE_IDX',
'mmSDMA1_VM_CNTL', 'mmSDMA1_VM_CNTL_BASE_IDX',
'mmSDMA1_VM_CTX_CNTL', 'mmSDMA1_VM_CTX_CNTL_BASE_IDX',
'mmSDMA1_VM_CTX_HI', 'mmSDMA1_VM_CTX_HI_BASE_IDX',
'mmSDMA1_VM_CTX_LO', 'mmSDMA1_VM_CTX_LO_BASE_IDX',
'mmSDMA2_ACTIVE_FCN_ID', 'mmSDMA2_ACTIVE_FCN_ID_BASE_IDX',
'mmSDMA2_AQL_STATUS', 'mmSDMA2_AQL_STATUS_BASE_IDX',
'mmSDMA2_ATOMIC_CNTL', 'mmSDMA2_ATOMIC_CNTL_BASE_IDX',
'mmSDMA2_ATOMIC_PREOP_HI', 'mmSDMA2_ATOMIC_PREOP_HI_BASE_IDX',
'mmSDMA2_ATOMIC_PREOP_LO', 'mmSDMA2_ATOMIC_PREOP_LO_BASE_IDX',
'mmSDMA2_BA_THRESHOLD', 'mmSDMA2_BA_THRESHOLD_BASE_IDX',
'mmSDMA2_CHICKEN_BITS', 'mmSDMA2_CHICKEN_BITS_2',
'mmSDMA2_CHICKEN_BITS_2_BASE_IDX',
'mmSDMA2_CHICKEN_BITS_BASE_IDX', 'mmSDMA2_CLK_CTRL',
'mmSDMA2_CLK_CTRL_BASE_IDX', 'mmSDMA2_CLOCK_GATING_REG',
'mmSDMA2_CLOCK_GATING_REG_BASE_IDX', 'mmSDMA2_CNTL',
'mmSDMA2_CNTL_BASE_IDX', 'mmSDMA2_CONTEXT_REG_TYPE0',
'mmSDMA2_CONTEXT_REG_TYPE0_BASE_IDX', 'mmSDMA2_CONTEXT_REG_TYPE1',
'mmSDMA2_CONTEXT_REG_TYPE1_BASE_IDX', 'mmSDMA2_CONTEXT_REG_TYPE2',
'mmSDMA2_CONTEXT_REG_TYPE2_BASE_IDX', 'mmSDMA2_CONTEXT_REG_TYPE3',
'mmSDMA2_CONTEXT_REG_TYPE3_BASE_IDX', 'mmSDMA2_CRD_CNTL',
'mmSDMA2_CRD_CNTL_BASE_IDX', 'mmSDMA2_DEC_START',
'mmSDMA2_DEC_START_BASE_IDX', 'mmSDMA2_EA_DBIT_ADDR_DATA',
'mmSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX',
'mmSDMA2_EA_DBIT_ADDR_INDEX',
'mmSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX', 'mmSDMA2_EDC_CONFIG',
'mmSDMA2_EDC_CONFIG_BASE_IDX', 'mmSDMA2_EDC_COUNTER',
'mmSDMA2_EDC_COUNTER_BASE_IDX', 'mmSDMA2_EDC_COUNTER_CLEAR',
'mmSDMA2_EDC_COUNTER_CLEAR_BASE_IDX', 'mmSDMA2_ERROR_LOG',
'mmSDMA2_ERROR_LOG_BASE_IDX', 'mmSDMA2_F32_CNTL',
'mmSDMA2_F32_CNTL_BASE_IDX', 'mmSDMA2_F32_COUNTER',
'mmSDMA2_F32_COUNTER_BASE_IDX', 'mmSDMA2_FREEZE',
'mmSDMA2_FREEZE_BASE_IDX', 'mmSDMA2_GB_ADDR_CONFIG',
'mmSDMA2_GB_ADDR_CONFIG_BASE_IDX', 'mmSDMA2_GB_ADDR_CONFIG_READ',
'mmSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX',
'mmSDMA2_GFX_CONTEXT_CNTL', 'mmSDMA2_GFX_CONTEXT_CNTL_BASE_IDX',
'mmSDMA2_GFX_CONTEXT_STATUS',
'mmSDMA2_GFX_CONTEXT_STATUS_BASE_IDX', 'mmSDMA2_GFX_CSA_ADDR_HI',
'mmSDMA2_GFX_CSA_ADDR_HI_BASE_IDX', 'mmSDMA2_GFX_CSA_ADDR_LO',
'mmSDMA2_GFX_CSA_ADDR_LO_BASE_IDX', 'mmSDMA2_GFX_DOORBELL',
'mmSDMA2_GFX_DOORBELL_BASE_IDX', 'mmSDMA2_GFX_DOORBELL_LOG',
'mmSDMA2_GFX_DOORBELL_LOG_BASE_IDX',
'mmSDMA2_GFX_DOORBELL_OFFSET',
'mmSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_GFX_DUMMY_REG',
'mmSDMA2_GFX_DUMMY_REG_BASE_IDX', 'mmSDMA2_GFX_IB_BASE_HI',
'mmSDMA2_GFX_IB_BASE_HI_BASE_IDX', 'mmSDMA2_GFX_IB_BASE_LO',
'mmSDMA2_GFX_IB_BASE_LO_BASE_IDX', 'mmSDMA2_GFX_IB_CNTL',
'mmSDMA2_GFX_IB_CNTL_BASE_IDX', 'mmSDMA2_GFX_IB_OFFSET',
'mmSDMA2_GFX_IB_OFFSET_BASE_IDX', 'mmSDMA2_GFX_IB_RPTR',
'mmSDMA2_GFX_IB_RPTR_BASE_IDX', 'mmSDMA2_GFX_IB_SIZE',
'mmSDMA2_GFX_IB_SIZE_BASE_IDX', 'mmSDMA2_GFX_IB_SUB_REMAIN',
'mmSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_CNTL',
'mmSDMA2_GFX_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA0',
'mmSDMA2_GFX_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA1',
'mmSDMA2_GFX_MIDCMD_DATA10', 'mmSDMA2_GFX_MIDCMD_DATA10_BASE_IDX',
'mmSDMA2_GFX_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA2',
'mmSDMA2_GFX_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA3',
'mmSDMA2_GFX_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA4',
'mmSDMA2_GFX_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA5',
'mmSDMA2_GFX_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA6',
'mmSDMA2_GFX_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA7',
'mmSDMA2_GFX_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA8',
'mmSDMA2_GFX_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA9',
'mmSDMA2_GFX_MIDCMD_DATA9_BASE_IDX',
'mmSDMA2_GFX_MINOR_PTR_UPDATE',
'mmSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_GFX_PREEMPT',
'mmSDMA2_GFX_PREEMPT_BASE_IDX', 'mmSDMA2_GFX_RB_AQL_CNTL',
'mmSDMA2_GFX_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_GFX_RB_BASE',
'mmSDMA2_GFX_RB_BASE_BASE_IDX', 'mmSDMA2_GFX_RB_BASE_HI',
'mmSDMA2_GFX_RB_BASE_HI_BASE_IDX', 'mmSDMA2_GFX_RB_CNTL',
'mmSDMA2_GFX_RB_CNTL_BASE_IDX', 'mmSDMA2_GFX_RB_RPTR',
'mmSDMA2_GFX_RB_RPTR_ADDR_HI',
'mmSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA2_GFX_RB_RPTR_ADDR_LO',
'mmSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA2_GFX_RB_RPTR_BASE_IDX', 'mmSDMA2_GFX_RB_RPTR_HI',
'mmSDMA2_GFX_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_GFX_RB_WPTR',
'mmSDMA2_GFX_RB_WPTR_BASE_IDX', 'mmSDMA2_GFX_RB_WPTR_HI',
'mmSDMA2_GFX_RB_WPTR_HI_BASE_IDX',
'mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI',
'mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO',
'mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA2_GFX_RB_WPTR_POLL_CNTL',
'mmSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX', 'mmSDMA2_GFX_SKIP_CNTL',
'mmSDMA2_GFX_SKIP_CNTL_BASE_IDX', 'mmSDMA2_GFX_STATUS',
'mmSDMA2_GFX_STATUS_BASE_IDX', 'mmSDMA2_GFX_WATERMARK',
'mmSDMA2_GFX_WATERMARK_BASE_IDX', 'mmSDMA2_GLOBAL_TIMESTAMP_HI',
'mmSDMA2_GLOBAL_TIMESTAMP_HI_BASE_IDX',
'mmSDMA2_GLOBAL_TIMESTAMP_LO',
'mmSDMA2_GLOBAL_TIMESTAMP_LO_BASE_IDX', 'mmSDMA2_HBM_PAGE_CONFIG',
'mmSDMA2_HBM_PAGE_CONFIG_BASE_IDX', 'mmSDMA2_HOLE_ADDR_HI',
'mmSDMA2_HOLE_ADDR_HI_BASE_IDX', 'mmSDMA2_HOLE_ADDR_LO',
'mmSDMA2_HOLE_ADDR_LO_BASE_IDX', 'mmSDMA2_IB_OFFSET_FETCH',
'mmSDMA2_IB_OFFSET_FETCH_BASE_IDX', 'mmSDMA2_ID',
'mmSDMA2_ID_BASE_IDX', 'mmSDMA2_INT_STATUS',
'mmSDMA2_INT_STATUS_BASE_IDX', 'mmSDMA2_PAGE_CONTEXT_STATUS',
'mmSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX',
'mmSDMA2_PAGE_CSA_ADDR_HI', 'mmSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX',
'mmSDMA2_PAGE_CSA_ADDR_LO', 'mmSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX',
'mmSDMA2_PAGE_DOORBELL', 'mmSDMA2_PAGE_DOORBELL_BASE_IDX',
'mmSDMA2_PAGE_DOORBELL_LOG', 'mmSDMA2_PAGE_DOORBELL_LOG_BASE_IDX',
'mmSDMA2_PAGE_DOORBELL_OFFSET',
'mmSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_PAGE_DUMMY_REG',
'mmSDMA2_PAGE_DUMMY_REG_BASE_IDX', 'mmSDMA2_PAGE_IB_BASE_HI',
'mmSDMA2_PAGE_IB_BASE_HI_BASE_IDX', 'mmSDMA2_PAGE_IB_BASE_LO',
'mmSDMA2_PAGE_IB_BASE_LO_BASE_IDX', 'mmSDMA2_PAGE_IB_CNTL',
'mmSDMA2_PAGE_IB_CNTL_BASE_IDX', 'mmSDMA2_PAGE_IB_OFFSET',
'mmSDMA2_PAGE_IB_OFFSET_BASE_IDX', 'mmSDMA2_PAGE_IB_RPTR',
'mmSDMA2_PAGE_IB_RPTR_BASE_IDX', 'mmSDMA2_PAGE_IB_SIZE',
'mmSDMA2_PAGE_IB_SIZE_BASE_IDX', 'mmSDMA2_PAGE_IB_SUB_REMAIN',
'mmSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_CNTL',
'mmSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA0',
'mmSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA1',
'mmSDMA2_PAGE_MIDCMD_DATA10',
'mmSDMA2_PAGE_MIDCMD_DATA10_BASE_IDX',
'mmSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA2',
'mmSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA3',
'mmSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA4',
'mmSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA5',
'mmSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA6',
'mmSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA7',
'mmSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA8',
'mmSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA9',
'mmSDMA2_PAGE_MIDCMD_DATA9_BASE_IDX',
'mmSDMA2_PAGE_MINOR_PTR_UPDATE',
'mmSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_PAGE_PREEMPT',
'mmSDMA2_PAGE_PREEMPT_BASE_IDX', 'mmSDMA2_PAGE_RB_AQL_CNTL',
'mmSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_PAGE_RB_BASE',
'mmSDMA2_PAGE_RB_BASE_BASE_IDX', 'mmSDMA2_PAGE_RB_BASE_HI',
'mmSDMA2_PAGE_RB_BASE_HI_BASE_IDX', 'mmSDMA2_PAGE_RB_CNTL',
'mmSDMA2_PAGE_RB_CNTL_BASE_IDX', 'mmSDMA2_PAGE_RB_RPTR',
'mmSDMA2_PAGE_RB_RPTR_ADDR_HI',
'mmSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA2_PAGE_RB_RPTR_ADDR_LO',
'mmSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA2_PAGE_RB_RPTR_BASE_IDX', 'mmSDMA2_PAGE_RB_RPTR_HI',
'mmSDMA2_PAGE_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_PAGE_RB_WPTR',
'mmSDMA2_PAGE_RB_WPTR_BASE_IDX', 'mmSDMA2_PAGE_RB_WPTR_HI',
'mmSDMA2_PAGE_RB_WPTR_HI_BASE_IDX',
'mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI',
'mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO',
'mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA2_PAGE_RB_WPTR_POLL_CNTL',
'mmSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA2_PAGE_SKIP_CNTL', 'mmSDMA2_PAGE_SKIP_CNTL_BASE_IDX',
'mmSDMA2_PAGE_STATUS', 'mmSDMA2_PAGE_STATUS_BASE_IDX',
'mmSDMA2_PAGE_WATERMARK', 'mmSDMA2_PAGE_WATERMARK_BASE_IDX',
'mmSDMA2_PERFCNT_MISC_CNTL', 'mmSDMA2_PERFCNT_MISC_CNTL_BASE_IDX',
'mmSDMA2_PERFCNT_PERFCOUNTER0_CFG',
'mmSDMA2_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX',
'mmSDMA2_PERFCNT_PERFCOUNTER1_CFG',
'mmSDMA2_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX',
'mmSDMA2_PERFCNT_PERFCOUNTER_HI',
'mmSDMA2_PERFCNT_PERFCOUNTER_HI_BASE_IDX',
'mmSDMA2_PERFCNT_PERFCOUNTER_LO',
'mmSDMA2_PERFCNT_PERFCOUNTER_LO_BASE_IDX',
'mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL',
'mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
'mmSDMA2_PERFCOUNTER0_HI', 'mmSDMA2_PERFCOUNTER0_HI_BASE_IDX',
'mmSDMA2_PERFCOUNTER0_LO', 'mmSDMA2_PERFCOUNTER0_LO_BASE_IDX',
'mmSDMA2_PERFCOUNTER0_SELECT', 'mmSDMA2_PERFCOUNTER0_SELECT1',
'mmSDMA2_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmSDMA2_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSDMA2_PERFCOUNTER1_HI',
'mmSDMA2_PERFCOUNTER1_HI_BASE_IDX', 'mmSDMA2_PERFCOUNTER1_LO',
'mmSDMA2_PERFCOUNTER1_LO_BASE_IDX', 'mmSDMA2_PERFCOUNTER1_SELECT',
'mmSDMA2_PERFCOUNTER1_SELECT1',
'mmSDMA2_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmSDMA2_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSDMA2_PG_CNTL',
'mmSDMA2_PG_CNTL_BASE_IDX', 'mmSDMA2_PG_CTX_CNTL',
'mmSDMA2_PG_CTX_CNTL_BASE_IDX', 'mmSDMA2_PG_CTX_HI',
'mmSDMA2_PG_CTX_HI_BASE_IDX', 'mmSDMA2_PG_CTX_LO',
'mmSDMA2_PG_CTX_LO_BASE_IDX', 'mmSDMA2_PHASE0_QUANTUM',
'mmSDMA2_PHASE0_QUANTUM_BASE_IDX', 'mmSDMA2_PHASE1_QUANTUM',
'mmSDMA2_PHASE1_QUANTUM_BASE_IDX', 'mmSDMA2_PHASE2_QUANTUM',
'mmSDMA2_PHASE2_QUANTUM_BASE_IDX', 'mmSDMA2_PHYSICAL_ADDR_HI',
'mmSDMA2_PHYSICAL_ADDR_HI_BASE_IDX', 'mmSDMA2_PHYSICAL_ADDR_LO',
'mmSDMA2_PHYSICAL_ADDR_LO_BASE_IDX', 'mmSDMA2_POWER_CNTL',
'mmSDMA2_POWER_CNTL_BASE_IDX', 'mmSDMA2_PROGRAM',
'mmSDMA2_PROGRAM_BASE_IDX', 'mmSDMA2_PUB_DUMMY_REG0',
'mmSDMA2_PUB_DUMMY_REG0_BASE_IDX', 'mmSDMA2_PUB_DUMMY_REG1',
'mmSDMA2_PUB_DUMMY_REG1_BASE_IDX', 'mmSDMA2_PUB_DUMMY_REG2',
'mmSDMA2_PUB_DUMMY_REG2_BASE_IDX', 'mmSDMA2_PUB_DUMMY_REG3',
'mmSDMA2_PUB_DUMMY_REG3_BASE_IDX', 'mmSDMA2_PUB_REG_TYPE0',
'mmSDMA2_PUB_REG_TYPE0_BASE_IDX', 'mmSDMA2_PUB_REG_TYPE1',
'mmSDMA2_PUB_REG_TYPE1_BASE_IDX', 'mmSDMA2_PUB_REG_TYPE2',
'mmSDMA2_PUB_REG_TYPE2_BASE_IDX', 'mmSDMA2_PUB_REG_TYPE3',
'mmSDMA2_PUB_REG_TYPE3_BASE_IDX', 'mmSDMA2_QUEUE_RESET_REQ',
'mmSDMA2_QUEUE_RESET_REQ_BASE_IDX', 'mmSDMA2_RB_RPTR_FETCH',
'mmSDMA2_RB_RPTR_FETCH_BASE_IDX', 'mmSDMA2_RB_RPTR_FETCH_HI',
'mmSDMA2_RB_RPTR_FETCH_HI_BASE_IDX', 'mmSDMA2_RD_BURST_CNTL',
'mmSDMA2_RD_BURST_CNTL_BASE_IDX', 'mmSDMA2_RELAX_ORDERING_LUT',
'mmSDMA2_RELAX_ORDERING_LUT_BASE_IDX',
'mmSDMA2_RLC0_CONTEXT_STATUS',
'mmSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX',
'mmSDMA2_RLC0_CSA_ADDR_HI', 'mmSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC0_CSA_ADDR_LO', 'mmSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC0_DOORBELL', 'mmSDMA2_RLC0_DOORBELL_BASE_IDX',
'mmSDMA2_RLC0_DOORBELL_LOG', 'mmSDMA2_RLC0_DOORBELL_LOG_BASE_IDX',
'mmSDMA2_RLC0_DOORBELL_OFFSET',
'mmSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC0_DUMMY_REG',
'mmSDMA2_RLC0_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC0_IB_BASE_HI',
'mmSDMA2_RLC0_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC0_IB_BASE_LO',
'mmSDMA2_RLC0_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC0_IB_CNTL',
'mmSDMA2_RLC0_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC0_IB_OFFSET',
'mmSDMA2_RLC0_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC0_IB_RPTR',
'mmSDMA2_RLC0_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC0_IB_SIZE',
'mmSDMA2_RLC0_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC0_IB_SUB_REMAIN',
'mmSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_CNTL',
'mmSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA0',
'mmSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA1',
'mmSDMA2_RLC0_MIDCMD_DATA10',
'mmSDMA2_RLC0_MIDCMD_DATA10_BASE_IDX',
'mmSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA2',
'mmSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA3',
'mmSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA4',
'mmSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA5',
'mmSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA6',
'mmSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA7',
'mmSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA8',
'mmSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA9',
'mmSDMA2_RLC0_MIDCMD_DATA9_BASE_IDX',
'mmSDMA2_RLC0_MINOR_PTR_UPDATE',
'mmSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC0_PREEMPT',
'mmSDMA2_RLC0_PREEMPT_BASE_IDX', 'mmSDMA2_RLC0_RB_AQL_CNTL',
'mmSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC0_RB_BASE',
'mmSDMA2_RLC0_RB_BASE_BASE_IDX', 'mmSDMA2_RLC0_RB_BASE_HI',
'mmSDMA2_RLC0_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC0_RB_CNTL',
'mmSDMA2_RLC0_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC0_RB_RPTR',
'mmSDMA2_RLC0_RB_RPTR_ADDR_HI',
'mmSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC0_RB_RPTR_ADDR_LO',
'mmSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC0_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC0_RB_RPTR_HI',
'mmSDMA2_RLC0_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC0_RB_WPTR',
'mmSDMA2_RLC0_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC0_RB_WPTR_HI',
'mmSDMA2_RLC0_RB_WPTR_HI_BASE_IDX',
'mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI',
'mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO',
'mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC0_RB_WPTR_POLL_CNTL',
'mmSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA2_RLC0_SKIP_CNTL', 'mmSDMA2_RLC0_SKIP_CNTL_BASE_IDX',
'mmSDMA2_RLC0_STATUS', 'mmSDMA2_RLC0_STATUS_BASE_IDX',
'mmSDMA2_RLC0_WATERMARK', 'mmSDMA2_RLC0_WATERMARK_BASE_IDX',
'mmSDMA2_RLC1_CONTEXT_STATUS',
'mmSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX',
'mmSDMA2_RLC1_CSA_ADDR_HI', 'mmSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC1_CSA_ADDR_LO', 'mmSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC1_DOORBELL', 'mmSDMA2_RLC1_DOORBELL_BASE_IDX',
'mmSDMA2_RLC1_DOORBELL_LOG', 'mmSDMA2_RLC1_DOORBELL_LOG_BASE_IDX',
'mmSDMA2_RLC1_DOORBELL_OFFSET',
'mmSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC1_DUMMY_REG',
'mmSDMA2_RLC1_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC1_IB_BASE_HI',
'mmSDMA2_RLC1_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC1_IB_BASE_LO',
'mmSDMA2_RLC1_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC1_IB_CNTL',
'mmSDMA2_RLC1_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC1_IB_OFFSET',
'mmSDMA2_RLC1_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC1_IB_RPTR',
'mmSDMA2_RLC1_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC1_IB_SIZE',
'mmSDMA2_RLC1_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC1_IB_SUB_REMAIN',
'mmSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_CNTL',
'mmSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA0',
'mmSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA1',
'mmSDMA2_RLC1_MIDCMD_DATA10',
'mmSDMA2_RLC1_MIDCMD_DATA10_BASE_IDX',
'mmSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA2',
'mmSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA3',
'mmSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA4',
'mmSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA5',
'mmSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA6',
'mmSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA7',
'mmSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA8',
'mmSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA9',
'mmSDMA2_RLC1_MIDCMD_DATA9_BASE_IDX',
'mmSDMA2_RLC1_MINOR_PTR_UPDATE',
'mmSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC1_PREEMPT',
'mmSDMA2_RLC1_PREEMPT_BASE_IDX', 'mmSDMA2_RLC1_RB_AQL_CNTL',
'mmSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC1_RB_BASE',
'mmSDMA2_RLC1_RB_BASE_BASE_IDX', 'mmSDMA2_RLC1_RB_BASE_HI',
'mmSDMA2_RLC1_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC1_RB_CNTL',
'mmSDMA2_RLC1_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC1_RB_RPTR',
'mmSDMA2_RLC1_RB_RPTR_ADDR_HI',
'mmSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC1_RB_RPTR_ADDR_LO',
'mmSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC1_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC1_RB_RPTR_HI',
'mmSDMA2_RLC1_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC1_RB_WPTR',
'mmSDMA2_RLC1_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC1_RB_WPTR_HI',
'mmSDMA2_RLC1_RB_WPTR_HI_BASE_IDX',
'mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI',
'mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO',
'mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC1_RB_WPTR_POLL_CNTL',
'mmSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA2_RLC1_SKIP_CNTL', 'mmSDMA2_RLC1_SKIP_CNTL_BASE_IDX',
'mmSDMA2_RLC1_STATUS', 'mmSDMA2_RLC1_STATUS_BASE_IDX',
'mmSDMA2_RLC1_WATERMARK', 'mmSDMA2_RLC1_WATERMARK_BASE_IDX',
'mmSDMA2_RLC2_CONTEXT_STATUS',
'mmSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX',
'mmSDMA2_RLC2_CSA_ADDR_HI', 'mmSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC2_CSA_ADDR_LO', 'mmSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC2_DOORBELL', 'mmSDMA2_RLC2_DOORBELL_BASE_IDX',
'mmSDMA2_RLC2_DOORBELL_LOG', 'mmSDMA2_RLC2_DOORBELL_LOG_BASE_IDX',
'mmSDMA2_RLC2_DOORBELL_OFFSET',
'mmSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC2_DUMMY_REG',
'mmSDMA2_RLC2_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC2_IB_BASE_HI',
'mmSDMA2_RLC2_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC2_IB_BASE_LO',
'mmSDMA2_RLC2_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC2_IB_CNTL',
'mmSDMA2_RLC2_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC2_IB_OFFSET',
'mmSDMA2_RLC2_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC2_IB_RPTR',
'mmSDMA2_RLC2_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC2_IB_SIZE',
'mmSDMA2_RLC2_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC2_IB_SUB_REMAIN',
'mmSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_CNTL',
'mmSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA0',
'mmSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA1',
'mmSDMA2_RLC2_MIDCMD_DATA10',
'mmSDMA2_RLC2_MIDCMD_DATA10_BASE_IDX',
'mmSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA2',
'mmSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA3',
'mmSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA4',
'mmSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA5',
'mmSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA6',
'mmSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA7',
'mmSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA8',
'mmSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA9',
'mmSDMA2_RLC2_MIDCMD_DATA9_BASE_IDX',
'mmSDMA2_RLC2_MINOR_PTR_UPDATE',
'mmSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC2_PREEMPT',
'mmSDMA2_RLC2_PREEMPT_BASE_IDX', 'mmSDMA2_RLC2_RB_AQL_CNTL',
'mmSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC2_RB_BASE',
'mmSDMA2_RLC2_RB_BASE_BASE_IDX', 'mmSDMA2_RLC2_RB_BASE_HI',
'mmSDMA2_RLC2_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC2_RB_CNTL',
'mmSDMA2_RLC2_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC2_RB_RPTR',
'mmSDMA2_RLC2_RB_RPTR_ADDR_HI',
'mmSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC2_RB_RPTR_ADDR_LO',
'mmSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC2_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC2_RB_RPTR_HI',
'mmSDMA2_RLC2_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC2_RB_WPTR',
'mmSDMA2_RLC2_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC2_RB_WPTR_HI',
'mmSDMA2_RLC2_RB_WPTR_HI_BASE_IDX',
'mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI',
'mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO',
'mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC2_RB_WPTR_POLL_CNTL',
'mmSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA2_RLC2_SKIP_CNTL', 'mmSDMA2_RLC2_SKIP_CNTL_BASE_IDX',
'mmSDMA2_RLC2_STATUS', 'mmSDMA2_RLC2_STATUS_BASE_IDX',
'mmSDMA2_RLC2_WATERMARK', 'mmSDMA2_RLC2_WATERMARK_BASE_IDX',
'mmSDMA2_RLC3_CONTEXT_STATUS',
'mmSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX',
'mmSDMA2_RLC3_CSA_ADDR_HI', 'mmSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC3_CSA_ADDR_LO', 'mmSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC3_DOORBELL', 'mmSDMA2_RLC3_DOORBELL_BASE_IDX',
'mmSDMA2_RLC3_DOORBELL_LOG', 'mmSDMA2_RLC3_DOORBELL_LOG_BASE_IDX',
'mmSDMA2_RLC3_DOORBELL_OFFSET',
'mmSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC3_DUMMY_REG',
'mmSDMA2_RLC3_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC3_IB_BASE_HI',
'mmSDMA2_RLC3_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC3_IB_BASE_LO',
'mmSDMA2_RLC3_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC3_IB_CNTL',
'mmSDMA2_RLC3_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC3_IB_OFFSET',
'mmSDMA2_RLC3_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC3_IB_RPTR',
'mmSDMA2_RLC3_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC3_IB_SIZE',
'mmSDMA2_RLC3_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC3_IB_SUB_REMAIN',
'mmSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_CNTL',
'mmSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA0',
'mmSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA1',
'mmSDMA2_RLC3_MIDCMD_DATA10',
'mmSDMA2_RLC3_MIDCMD_DATA10_BASE_IDX',
'mmSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA2',
'mmSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA3',
'mmSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA4',
'mmSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA5',
'mmSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA6',
'mmSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA7',
'mmSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA8',
'mmSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA9',
'mmSDMA2_RLC3_MIDCMD_DATA9_BASE_IDX',
'mmSDMA2_RLC3_MINOR_PTR_UPDATE',
'mmSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC3_PREEMPT',
'mmSDMA2_RLC3_PREEMPT_BASE_IDX', 'mmSDMA2_RLC3_RB_AQL_CNTL',
'mmSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC3_RB_BASE',
'mmSDMA2_RLC3_RB_BASE_BASE_IDX', 'mmSDMA2_RLC3_RB_BASE_HI',
'mmSDMA2_RLC3_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC3_RB_CNTL',
'mmSDMA2_RLC3_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC3_RB_RPTR',
'mmSDMA2_RLC3_RB_RPTR_ADDR_HI',
'mmSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC3_RB_RPTR_ADDR_LO',
'mmSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC3_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC3_RB_RPTR_HI',
'mmSDMA2_RLC3_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC3_RB_WPTR',
'mmSDMA2_RLC3_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC3_RB_WPTR_HI',
'mmSDMA2_RLC3_RB_WPTR_HI_BASE_IDX',
'mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI',
'mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO',
'mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC3_RB_WPTR_POLL_CNTL',
'mmSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA2_RLC3_SKIP_CNTL', 'mmSDMA2_RLC3_SKIP_CNTL_BASE_IDX',
'mmSDMA2_RLC3_STATUS', 'mmSDMA2_RLC3_STATUS_BASE_IDX',
'mmSDMA2_RLC3_WATERMARK', 'mmSDMA2_RLC3_WATERMARK_BASE_IDX',
'mmSDMA2_RLC4_CONTEXT_STATUS',
'mmSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX',
'mmSDMA2_RLC4_CSA_ADDR_HI', 'mmSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC4_CSA_ADDR_LO', 'mmSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC4_DOORBELL', 'mmSDMA2_RLC4_DOORBELL_BASE_IDX',
'mmSDMA2_RLC4_DOORBELL_LOG', 'mmSDMA2_RLC4_DOORBELL_LOG_BASE_IDX',
'mmSDMA2_RLC4_DOORBELL_OFFSET',
'mmSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC4_DUMMY_REG',
'mmSDMA2_RLC4_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC4_IB_BASE_HI',
'mmSDMA2_RLC4_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC4_IB_BASE_LO',
'mmSDMA2_RLC4_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC4_IB_CNTL',
'mmSDMA2_RLC4_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC4_IB_OFFSET',
'mmSDMA2_RLC4_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC4_IB_RPTR',
'mmSDMA2_RLC4_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC4_IB_SIZE',
'mmSDMA2_RLC4_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC4_IB_SUB_REMAIN',
'mmSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_CNTL',
'mmSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA0',
'mmSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA1',
'mmSDMA2_RLC4_MIDCMD_DATA10',
'mmSDMA2_RLC4_MIDCMD_DATA10_BASE_IDX',
'mmSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA2',
'mmSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA3',
'mmSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA4',
'mmSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA5',
'mmSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA6',
'mmSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA7',
'mmSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA8',
'mmSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA9',
'mmSDMA2_RLC4_MIDCMD_DATA9_BASE_IDX',
'mmSDMA2_RLC4_MINOR_PTR_UPDATE',
'mmSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC4_PREEMPT',
'mmSDMA2_RLC4_PREEMPT_BASE_IDX', 'mmSDMA2_RLC4_RB_AQL_CNTL',
'mmSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC4_RB_BASE',
'mmSDMA2_RLC4_RB_BASE_BASE_IDX', 'mmSDMA2_RLC4_RB_BASE_HI',
'mmSDMA2_RLC4_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC4_RB_CNTL',
'mmSDMA2_RLC4_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC4_RB_RPTR',
'mmSDMA2_RLC4_RB_RPTR_ADDR_HI',
'mmSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC4_RB_RPTR_ADDR_LO',
'mmSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC4_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC4_RB_RPTR_HI',
'mmSDMA2_RLC4_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC4_RB_WPTR',
'mmSDMA2_RLC4_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC4_RB_WPTR_HI',
'mmSDMA2_RLC4_RB_WPTR_HI_BASE_IDX',
'mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI',
'mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO',
'mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC4_RB_WPTR_POLL_CNTL',
'mmSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA2_RLC4_SKIP_CNTL', 'mmSDMA2_RLC4_SKIP_CNTL_BASE_IDX',
'mmSDMA2_RLC4_STATUS', 'mmSDMA2_RLC4_STATUS_BASE_IDX',
'mmSDMA2_RLC4_WATERMARK', 'mmSDMA2_RLC4_WATERMARK_BASE_IDX',
'mmSDMA2_RLC5_CONTEXT_STATUS',
'mmSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX',
'mmSDMA2_RLC5_CSA_ADDR_HI', 'mmSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC5_CSA_ADDR_LO', 'mmSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC5_DOORBELL', 'mmSDMA2_RLC5_DOORBELL_BASE_IDX',
'mmSDMA2_RLC5_DOORBELL_LOG', 'mmSDMA2_RLC5_DOORBELL_LOG_BASE_IDX',
'mmSDMA2_RLC5_DOORBELL_OFFSET',
'mmSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC5_DUMMY_REG',
'mmSDMA2_RLC5_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC5_IB_BASE_HI',
'mmSDMA2_RLC5_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC5_IB_BASE_LO',
'mmSDMA2_RLC5_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC5_IB_CNTL',
'mmSDMA2_RLC5_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC5_IB_OFFSET',
'mmSDMA2_RLC5_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC5_IB_RPTR',
'mmSDMA2_RLC5_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC5_IB_SIZE',
'mmSDMA2_RLC5_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC5_IB_SUB_REMAIN',
'mmSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_CNTL',
'mmSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA0',
'mmSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA1',
'mmSDMA2_RLC5_MIDCMD_DATA10',
'mmSDMA2_RLC5_MIDCMD_DATA10_BASE_IDX',
'mmSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA2',
'mmSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA3',
'mmSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA4',
'mmSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA5',
'mmSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA6',
'mmSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA7',
'mmSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA8',
'mmSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA9',
'mmSDMA2_RLC5_MIDCMD_DATA9_BASE_IDX',
'mmSDMA2_RLC5_MINOR_PTR_UPDATE',
'mmSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC5_PREEMPT',
'mmSDMA2_RLC5_PREEMPT_BASE_IDX', 'mmSDMA2_RLC5_RB_AQL_CNTL',
'mmSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC5_RB_BASE',
'mmSDMA2_RLC5_RB_BASE_BASE_IDX', 'mmSDMA2_RLC5_RB_BASE_HI',
'mmSDMA2_RLC5_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC5_RB_CNTL',
'mmSDMA2_RLC5_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC5_RB_RPTR',
'mmSDMA2_RLC5_RB_RPTR_ADDR_HI',
'mmSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC5_RB_RPTR_ADDR_LO',
'mmSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC5_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC5_RB_RPTR_HI',
'mmSDMA2_RLC5_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC5_RB_WPTR',
'mmSDMA2_RLC5_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC5_RB_WPTR_HI',
'mmSDMA2_RLC5_RB_WPTR_HI_BASE_IDX',
'mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI',
'mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO',
'mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC5_RB_WPTR_POLL_CNTL',
'mmSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA2_RLC5_SKIP_CNTL', 'mmSDMA2_RLC5_SKIP_CNTL_BASE_IDX',
'mmSDMA2_RLC5_STATUS', 'mmSDMA2_RLC5_STATUS_BASE_IDX',
'mmSDMA2_RLC5_WATERMARK', 'mmSDMA2_RLC5_WATERMARK_BASE_IDX',
'mmSDMA2_RLC6_CONTEXT_STATUS',
'mmSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX',
'mmSDMA2_RLC6_CSA_ADDR_HI', 'mmSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC6_CSA_ADDR_LO', 'mmSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC6_DOORBELL', 'mmSDMA2_RLC6_DOORBELL_BASE_IDX',
'mmSDMA2_RLC6_DOORBELL_LOG', 'mmSDMA2_RLC6_DOORBELL_LOG_BASE_IDX',
'mmSDMA2_RLC6_DOORBELL_OFFSET',
'mmSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC6_DUMMY_REG',
'mmSDMA2_RLC6_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC6_IB_BASE_HI',
'mmSDMA2_RLC6_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC6_IB_BASE_LO',
'mmSDMA2_RLC6_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC6_IB_CNTL',
'mmSDMA2_RLC6_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC6_IB_OFFSET',
'mmSDMA2_RLC6_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC6_IB_RPTR',
'mmSDMA2_RLC6_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC6_IB_SIZE',
'mmSDMA2_RLC6_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC6_IB_SUB_REMAIN',
'mmSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_CNTL',
'mmSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA0',
'mmSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA1',
'mmSDMA2_RLC6_MIDCMD_DATA10',
'mmSDMA2_RLC6_MIDCMD_DATA10_BASE_IDX',
'mmSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA2',
'mmSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA3',
'mmSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA4',
'mmSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA5',
'mmSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA6',
'mmSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA7',
'mmSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA8',
'mmSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA9',
'mmSDMA2_RLC6_MIDCMD_DATA9_BASE_IDX',
'mmSDMA2_RLC6_MINOR_PTR_UPDATE',
'mmSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC6_PREEMPT',
'mmSDMA2_RLC6_PREEMPT_BASE_IDX', 'mmSDMA2_RLC6_RB_AQL_CNTL',
'mmSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC6_RB_BASE',
'mmSDMA2_RLC6_RB_BASE_BASE_IDX', 'mmSDMA2_RLC6_RB_BASE_HI',
'mmSDMA2_RLC6_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC6_RB_CNTL',
'mmSDMA2_RLC6_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC6_RB_RPTR',
'mmSDMA2_RLC6_RB_RPTR_ADDR_HI',
'mmSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC6_RB_RPTR_ADDR_LO',
'mmSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC6_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC6_RB_RPTR_HI',
'mmSDMA2_RLC6_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC6_RB_WPTR',
'mmSDMA2_RLC6_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC6_RB_WPTR_HI',
'mmSDMA2_RLC6_RB_WPTR_HI_BASE_IDX',
'mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI',
'mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO',
'mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC6_RB_WPTR_POLL_CNTL',
'mmSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA2_RLC6_SKIP_CNTL', 'mmSDMA2_RLC6_SKIP_CNTL_BASE_IDX',
'mmSDMA2_RLC6_STATUS', 'mmSDMA2_RLC6_STATUS_BASE_IDX',
'mmSDMA2_RLC6_WATERMARK', 'mmSDMA2_RLC6_WATERMARK_BASE_IDX',
'mmSDMA2_RLC7_CONTEXT_STATUS',
'mmSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX',
'mmSDMA2_RLC7_CSA_ADDR_HI', 'mmSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC7_CSA_ADDR_LO', 'mmSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC7_DOORBELL', 'mmSDMA2_RLC7_DOORBELL_BASE_IDX',
'mmSDMA2_RLC7_DOORBELL_LOG', 'mmSDMA2_RLC7_DOORBELL_LOG_BASE_IDX',
'mmSDMA2_RLC7_DOORBELL_OFFSET',
'mmSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC7_DUMMY_REG',
'mmSDMA2_RLC7_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC7_IB_BASE_HI',
'mmSDMA2_RLC7_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC7_IB_BASE_LO',
'mmSDMA2_RLC7_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC7_IB_CNTL',
'mmSDMA2_RLC7_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC7_IB_OFFSET',
'mmSDMA2_RLC7_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC7_IB_RPTR',
'mmSDMA2_RLC7_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC7_IB_SIZE',
'mmSDMA2_RLC7_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC7_IB_SUB_REMAIN',
'mmSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_CNTL',
'mmSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA0',
'mmSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA1',
'mmSDMA2_RLC7_MIDCMD_DATA10',
'mmSDMA2_RLC7_MIDCMD_DATA10_BASE_IDX',
'mmSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA2',
'mmSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA3',
'mmSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA4',
'mmSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA5',
'mmSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA6',
'mmSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA7',
'mmSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA8',
'mmSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA9',
'mmSDMA2_RLC7_MIDCMD_DATA9_BASE_IDX',
'mmSDMA2_RLC7_MINOR_PTR_UPDATE',
'mmSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC7_PREEMPT',
'mmSDMA2_RLC7_PREEMPT_BASE_IDX', 'mmSDMA2_RLC7_RB_AQL_CNTL',
'mmSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC7_RB_BASE',
'mmSDMA2_RLC7_RB_BASE_BASE_IDX', 'mmSDMA2_RLC7_RB_BASE_HI',
'mmSDMA2_RLC7_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC7_RB_CNTL',
'mmSDMA2_RLC7_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC7_RB_RPTR',
'mmSDMA2_RLC7_RB_RPTR_ADDR_HI',
'mmSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC7_RB_RPTR_ADDR_LO',
'mmSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC7_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC7_RB_RPTR_HI',
'mmSDMA2_RLC7_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC7_RB_WPTR',
'mmSDMA2_RLC7_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC7_RB_WPTR_HI',
'mmSDMA2_RLC7_RB_WPTR_HI_BASE_IDX',
'mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI',
'mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO',
'mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA2_RLC7_RB_WPTR_POLL_CNTL',
'mmSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA2_RLC7_SKIP_CNTL', 'mmSDMA2_RLC7_SKIP_CNTL_BASE_IDX',
'mmSDMA2_RLC7_STATUS', 'mmSDMA2_RLC7_STATUS_BASE_IDX',
'mmSDMA2_RLC7_WATERMARK', 'mmSDMA2_RLC7_WATERMARK_BASE_IDX',
'mmSDMA2_SCRATCH_RAM_ADDR', 'mmSDMA2_SCRATCH_RAM_ADDR_BASE_IDX',
'mmSDMA2_SCRATCH_RAM_DATA', 'mmSDMA2_SCRATCH_RAM_DATA_BASE_IDX',
'mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL',
'mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX',
'mmSDMA2_STATUS1_REG', 'mmSDMA2_STATUS1_REG_BASE_IDX',
'mmSDMA2_STATUS2_REG', 'mmSDMA2_STATUS2_REG_BASE_IDX',
'mmSDMA2_STATUS3_REG', 'mmSDMA2_STATUS3_REG_BASE_IDX',
'mmSDMA2_STATUS4_REG', 'mmSDMA2_STATUS4_REG_BASE_IDX',
'mmSDMA2_STATUS5_REG', 'mmSDMA2_STATUS5_REG_BASE_IDX',
'mmSDMA2_STATUS_REG', 'mmSDMA2_STATUS_REG_BASE_IDX',
'mmSDMA2_TILING_CONFIG', 'mmSDMA2_TILING_CONFIG_BASE_IDX',
'mmSDMA2_TIMESTAMP_CNTL', 'mmSDMA2_TIMESTAMP_CNTL_BASE_IDX',
'mmSDMA2_TLBI_GCR_CNTL', 'mmSDMA2_TLBI_GCR_CNTL_BASE_IDX',
'mmSDMA2_UCODE_ADDR', 'mmSDMA2_UCODE_ADDR_BASE_IDX',
'mmSDMA2_UCODE_CHECKSUM', 'mmSDMA2_UCODE_CHECKSUM_BASE_IDX',
'mmSDMA2_UCODE_DATA', 'mmSDMA2_UCODE_DATA_BASE_IDX',
'mmSDMA2_UTCL1_CNTL', 'mmSDMA2_UTCL1_CNTL_BASE_IDX',
'mmSDMA2_UTCL1_INV0', 'mmSDMA2_UTCL1_INV0_BASE_IDX',
'mmSDMA2_UTCL1_INV1', 'mmSDMA2_UTCL1_INV1_BASE_IDX',
'mmSDMA2_UTCL1_INV2', 'mmSDMA2_UTCL1_INV2_BASE_IDX',
'mmSDMA2_UTCL1_PAGE', 'mmSDMA2_UTCL1_PAGE_BASE_IDX',
'mmSDMA2_UTCL1_RD_STATUS', 'mmSDMA2_UTCL1_RD_STATUS_BASE_IDX',
'mmSDMA2_UTCL1_RD_XNACK0', 'mmSDMA2_UTCL1_RD_XNACK0_BASE_IDX',
'mmSDMA2_UTCL1_RD_XNACK1', 'mmSDMA2_UTCL1_RD_XNACK1_BASE_IDX',
'mmSDMA2_UTCL1_TIMEOUT', 'mmSDMA2_UTCL1_TIMEOUT_BASE_IDX',
'mmSDMA2_UTCL1_WATERMK', 'mmSDMA2_UTCL1_WATERMK_BASE_IDX',
'mmSDMA2_UTCL1_WR_STATUS', 'mmSDMA2_UTCL1_WR_STATUS_BASE_IDX',
'mmSDMA2_UTCL1_WR_XNACK0', 'mmSDMA2_UTCL1_WR_XNACK0_BASE_IDX',
'mmSDMA2_UTCL1_WR_XNACK1', 'mmSDMA2_UTCL1_WR_XNACK1_BASE_IDX',
'mmSDMA2_VERSION', 'mmSDMA2_VERSION_BASE_IDX',
'mmSDMA2_VF_ENABLE', 'mmSDMA2_VF_ENABLE_BASE_IDX',
'mmSDMA2_VIRT_RESET_REQ', 'mmSDMA2_VIRT_RESET_REQ_BASE_IDX',
'mmSDMA2_VM_CNTL', 'mmSDMA2_VM_CNTL_BASE_IDX',
'mmSDMA2_VM_CTX_CNTL', 'mmSDMA2_VM_CTX_CNTL_BASE_IDX',
'mmSDMA2_VM_CTX_HI', 'mmSDMA2_VM_CTX_HI_BASE_IDX',
'mmSDMA2_VM_CTX_LO', 'mmSDMA2_VM_CTX_LO_BASE_IDX',
'mmSDMA3_ACTIVE_FCN_ID', 'mmSDMA3_ACTIVE_FCN_ID_BASE_IDX',
'mmSDMA3_AQL_STATUS', 'mmSDMA3_AQL_STATUS_BASE_IDX',
'mmSDMA3_ATOMIC_CNTL', 'mmSDMA3_ATOMIC_CNTL_BASE_IDX',
'mmSDMA3_ATOMIC_PREOP_HI', 'mmSDMA3_ATOMIC_PREOP_HI_BASE_IDX',
'mmSDMA3_ATOMIC_PREOP_LO', 'mmSDMA3_ATOMIC_PREOP_LO_BASE_IDX',
'mmSDMA3_BA_THRESHOLD', 'mmSDMA3_BA_THRESHOLD_BASE_IDX',
'mmSDMA3_CHICKEN_BITS', 'mmSDMA3_CHICKEN_BITS_2',
'mmSDMA3_CHICKEN_BITS_2_BASE_IDX',
'mmSDMA3_CHICKEN_BITS_BASE_IDX', 'mmSDMA3_CLK_CTRL',
'mmSDMA3_CLK_CTRL_BASE_IDX', 'mmSDMA3_CLOCK_GATING_REG',
'mmSDMA3_CLOCK_GATING_REG_BASE_IDX', 'mmSDMA3_CNTL',
'mmSDMA3_CNTL_BASE_IDX', 'mmSDMA3_CONTEXT_REG_TYPE0',
'mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX', 'mmSDMA3_CONTEXT_REG_TYPE1',
'mmSDMA3_CONTEXT_REG_TYPE1_BASE_IDX', 'mmSDMA3_CONTEXT_REG_TYPE2',
'mmSDMA3_CONTEXT_REG_TYPE2_BASE_IDX', 'mmSDMA3_CONTEXT_REG_TYPE3',
'mmSDMA3_CONTEXT_REG_TYPE3_BASE_IDX', 'mmSDMA3_CRD_CNTL',
'mmSDMA3_CRD_CNTL_BASE_IDX', 'mmSDMA3_DEC_START',
'mmSDMA3_DEC_START_BASE_IDX', 'mmSDMA3_EA_DBIT_ADDR_DATA',
'mmSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX',
'mmSDMA3_EA_DBIT_ADDR_INDEX',
'mmSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX', 'mmSDMA3_EDC_CONFIG',
'mmSDMA3_EDC_CONFIG_BASE_IDX', 'mmSDMA3_EDC_COUNTER',
'mmSDMA3_EDC_COUNTER_BASE_IDX', 'mmSDMA3_EDC_COUNTER_CLEAR',
'mmSDMA3_EDC_COUNTER_CLEAR_BASE_IDX', 'mmSDMA3_ERROR_LOG',
'mmSDMA3_ERROR_LOG_BASE_IDX', 'mmSDMA3_F32_CNTL',
'mmSDMA3_F32_CNTL_BASE_IDX', 'mmSDMA3_F32_COUNTER',
'mmSDMA3_F32_COUNTER_BASE_IDX', 'mmSDMA3_FREEZE',
'mmSDMA3_FREEZE_BASE_IDX', 'mmSDMA3_GB_ADDR_CONFIG',
'mmSDMA3_GB_ADDR_CONFIG_BASE_IDX', 'mmSDMA3_GB_ADDR_CONFIG_READ',
'mmSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX',
'mmSDMA3_GFX_CONTEXT_CNTL', 'mmSDMA3_GFX_CONTEXT_CNTL_BASE_IDX',
'mmSDMA3_GFX_CONTEXT_STATUS',
'mmSDMA3_GFX_CONTEXT_STATUS_BASE_IDX', 'mmSDMA3_GFX_CSA_ADDR_HI',
'mmSDMA3_GFX_CSA_ADDR_HI_BASE_IDX', 'mmSDMA3_GFX_CSA_ADDR_LO',
'mmSDMA3_GFX_CSA_ADDR_LO_BASE_IDX', 'mmSDMA3_GFX_DOORBELL',
'mmSDMA3_GFX_DOORBELL_BASE_IDX', 'mmSDMA3_GFX_DOORBELL_LOG',
'mmSDMA3_GFX_DOORBELL_LOG_BASE_IDX',
'mmSDMA3_GFX_DOORBELL_OFFSET',
'mmSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_GFX_DUMMY_REG',
'mmSDMA3_GFX_DUMMY_REG_BASE_IDX', 'mmSDMA3_GFX_IB_BASE_HI',
'mmSDMA3_GFX_IB_BASE_HI_BASE_IDX', 'mmSDMA3_GFX_IB_BASE_LO',
'mmSDMA3_GFX_IB_BASE_LO_BASE_IDX', 'mmSDMA3_GFX_IB_CNTL',
'mmSDMA3_GFX_IB_CNTL_BASE_IDX', 'mmSDMA3_GFX_IB_OFFSET',
'mmSDMA3_GFX_IB_OFFSET_BASE_IDX', 'mmSDMA3_GFX_IB_RPTR',
'mmSDMA3_GFX_IB_RPTR_BASE_IDX', 'mmSDMA3_GFX_IB_SIZE',
'mmSDMA3_GFX_IB_SIZE_BASE_IDX', 'mmSDMA3_GFX_IB_SUB_REMAIN',
'mmSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_CNTL',
'mmSDMA3_GFX_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA0',
'mmSDMA3_GFX_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA1',
'mmSDMA3_GFX_MIDCMD_DATA10', 'mmSDMA3_GFX_MIDCMD_DATA10_BASE_IDX',
'mmSDMA3_GFX_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA2',
'mmSDMA3_GFX_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA3',
'mmSDMA3_GFX_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA4',
'mmSDMA3_GFX_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA5',
'mmSDMA3_GFX_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA6',
'mmSDMA3_GFX_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA7',
'mmSDMA3_GFX_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA8',
'mmSDMA3_GFX_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA9',
'mmSDMA3_GFX_MIDCMD_DATA9_BASE_IDX',
'mmSDMA3_GFX_MINOR_PTR_UPDATE',
'mmSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_GFX_PREEMPT',
'mmSDMA3_GFX_PREEMPT_BASE_IDX', 'mmSDMA3_GFX_RB_AQL_CNTL',
'mmSDMA3_GFX_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_GFX_RB_BASE',
'mmSDMA3_GFX_RB_BASE_BASE_IDX', 'mmSDMA3_GFX_RB_BASE_HI',
'mmSDMA3_GFX_RB_BASE_HI_BASE_IDX', 'mmSDMA3_GFX_RB_CNTL',
'mmSDMA3_GFX_RB_CNTL_BASE_IDX', 'mmSDMA3_GFX_RB_RPTR',
'mmSDMA3_GFX_RB_RPTR_ADDR_HI',
'mmSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA3_GFX_RB_RPTR_ADDR_LO',
'mmSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA3_GFX_RB_RPTR_BASE_IDX', 'mmSDMA3_GFX_RB_RPTR_HI',
'mmSDMA3_GFX_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_GFX_RB_WPTR',
'mmSDMA3_GFX_RB_WPTR_BASE_IDX', 'mmSDMA3_GFX_RB_WPTR_HI',
'mmSDMA3_GFX_RB_WPTR_HI_BASE_IDX',
'mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI',
'mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO',
'mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA3_GFX_RB_WPTR_POLL_CNTL',
'mmSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX', 'mmSDMA3_GFX_SKIP_CNTL',
'mmSDMA3_GFX_SKIP_CNTL_BASE_IDX', 'mmSDMA3_GFX_STATUS',
'mmSDMA3_GFX_STATUS_BASE_IDX', 'mmSDMA3_GFX_WATERMARK',
'mmSDMA3_GFX_WATERMARK_BASE_IDX', 'mmSDMA3_GLOBAL_TIMESTAMP_HI',
'mmSDMA3_GLOBAL_TIMESTAMP_HI_BASE_IDX',
'mmSDMA3_GLOBAL_TIMESTAMP_LO',
'mmSDMA3_GLOBAL_TIMESTAMP_LO_BASE_IDX', 'mmSDMA3_HBM_PAGE_CONFIG',
'mmSDMA3_HBM_PAGE_CONFIG_BASE_IDX', 'mmSDMA3_HOLE_ADDR_HI',
'mmSDMA3_HOLE_ADDR_HI_BASE_IDX', 'mmSDMA3_HOLE_ADDR_LO',
'mmSDMA3_HOLE_ADDR_LO_BASE_IDX', 'mmSDMA3_IB_OFFSET_FETCH',
'mmSDMA3_IB_OFFSET_FETCH_BASE_IDX', 'mmSDMA3_ID',
'mmSDMA3_ID_BASE_IDX', 'mmSDMA3_INT_STATUS',
'mmSDMA3_INT_STATUS_BASE_IDX', 'mmSDMA3_PAGE_CONTEXT_STATUS',
'mmSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX',
'mmSDMA3_PAGE_CSA_ADDR_HI', 'mmSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX',
'mmSDMA3_PAGE_CSA_ADDR_LO', 'mmSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX',
'mmSDMA3_PAGE_DOORBELL', 'mmSDMA3_PAGE_DOORBELL_BASE_IDX',
'mmSDMA3_PAGE_DOORBELL_LOG', 'mmSDMA3_PAGE_DOORBELL_LOG_BASE_IDX',
'mmSDMA3_PAGE_DOORBELL_OFFSET',
'mmSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_PAGE_DUMMY_REG',
'mmSDMA3_PAGE_DUMMY_REG_BASE_IDX', 'mmSDMA3_PAGE_IB_BASE_HI',
'mmSDMA3_PAGE_IB_BASE_HI_BASE_IDX', 'mmSDMA3_PAGE_IB_BASE_LO',
'mmSDMA3_PAGE_IB_BASE_LO_BASE_IDX', 'mmSDMA3_PAGE_IB_CNTL',
'mmSDMA3_PAGE_IB_CNTL_BASE_IDX', 'mmSDMA3_PAGE_IB_OFFSET',
'mmSDMA3_PAGE_IB_OFFSET_BASE_IDX', 'mmSDMA3_PAGE_IB_RPTR',
'mmSDMA3_PAGE_IB_RPTR_BASE_IDX', 'mmSDMA3_PAGE_IB_SIZE',
'mmSDMA3_PAGE_IB_SIZE_BASE_IDX', 'mmSDMA3_PAGE_IB_SUB_REMAIN',
'mmSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_CNTL',
'mmSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA0',
'mmSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA1',
'mmSDMA3_PAGE_MIDCMD_DATA10',
'mmSDMA3_PAGE_MIDCMD_DATA10_BASE_IDX',
'mmSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA2',
'mmSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA3',
'mmSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA4',
'mmSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA5',
'mmSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA6',
'mmSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA7',
'mmSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA8',
'mmSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA9',
'mmSDMA3_PAGE_MIDCMD_DATA9_BASE_IDX',
'mmSDMA3_PAGE_MINOR_PTR_UPDATE',
'mmSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_PAGE_PREEMPT',
'mmSDMA3_PAGE_PREEMPT_BASE_IDX', 'mmSDMA3_PAGE_RB_AQL_CNTL',
'mmSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_PAGE_RB_BASE',
'mmSDMA3_PAGE_RB_BASE_BASE_IDX', 'mmSDMA3_PAGE_RB_BASE_HI',
'mmSDMA3_PAGE_RB_BASE_HI_BASE_IDX', 'mmSDMA3_PAGE_RB_CNTL',
'mmSDMA3_PAGE_RB_CNTL_BASE_IDX', 'mmSDMA3_PAGE_RB_RPTR',
'mmSDMA3_PAGE_RB_RPTR_ADDR_HI',
'mmSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA3_PAGE_RB_RPTR_ADDR_LO',
'mmSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA3_PAGE_RB_RPTR_BASE_IDX', 'mmSDMA3_PAGE_RB_RPTR_HI',
'mmSDMA3_PAGE_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_PAGE_RB_WPTR',
'mmSDMA3_PAGE_RB_WPTR_BASE_IDX', 'mmSDMA3_PAGE_RB_WPTR_HI',
'mmSDMA3_PAGE_RB_WPTR_HI_BASE_IDX',
'mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI',
'mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO',
'mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA3_PAGE_RB_WPTR_POLL_CNTL',
'mmSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA3_PAGE_SKIP_CNTL', 'mmSDMA3_PAGE_SKIP_CNTL_BASE_IDX',
'mmSDMA3_PAGE_STATUS', 'mmSDMA3_PAGE_STATUS_BASE_IDX',
'mmSDMA3_PAGE_WATERMARK', 'mmSDMA3_PAGE_WATERMARK_BASE_IDX',
'mmSDMA3_PERFCNT_MISC_CNTL', 'mmSDMA3_PERFCNT_MISC_CNTL_BASE_IDX',
'mmSDMA3_PERFCNT_PERFCOUNTER0_CFG',
'mmSDMA3_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX',
'mmSDMA3_PERFCNT_PERFCOUNTER1_CFG',
'mmSDMA3_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX',
'mmSDMA3_PERFCNT_PERFCOUNTER_HI',
'mmSDMA3_PERFCNT_PERFCOUNTER_HI_BASE_IDX',
'mmSDMA3_PERFCNT_PERFCOUNTER_LO',
'mmSDMA3_PERFCNT_PERFCOUNTER_LO_BASE_IDX',
'mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL',
'mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
'mmSDMA3_PERFCOUNTER0_HI', 'mmSDMA3_PERFCOUNTER0_HI_BASE_IDX',
'mmSDMA3_PERFCOUNTER0_LO', 'mmSDMA3_PERFCOUNTER0_LO_BASE_IDX',
'mmSDMA3_PERFCOUNTER0_SELECT', 'mmSDMA3_PERFCOUNTER0_SELECT1',
'mmSDMA3_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmSDMA3_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSDMA3_PERFCOUNTER1_HI',
'mmSDMA3_PERFCOUNTER1_HI_BASE_IDX', 'mmSDMA3_PERFCOUNTER1_LO',
'mmSDMA3_PERFCOUNTER1_LO_BASE_IDX', 'mmSDMA3_PERFCOUNTER1_SELECT',
'mmSDMA3_PERFCOUNTER1_SELECT1',
'mmSDMA3_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmSDMA3_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSDMA3_PG_CNTL',
'mmSDMA3_PG_CNTL_BASE_IDX', 'mmSDMA3_PG_CTX_CNTL',
'mmSDMA3_PG_CTX_CNTL_BASE_IDX', 'mmSDMA3_PG_CTX_HI',
'mmSDMA3_PG_CTX_HI_BASE_IDX', 'mmSDMA3_PG_CTX_LO',
'mmSDMA3_PG_CTX_LO_BASE_IDX', 'mmSDMA3_PHASE0_QUANTUM',
'mmSDMA3_PHASE0_QUANTUM_BASE_IDX', 'mmSDMA3_PHASE1_QUANTUM',
'mmSDMA3_PHASE1_QUANTUM_BASE_IDX', 'mmSDMA3_PHASE2_QUANTUM',
'mmSDMA3_PHASE2_QUANTUM_BASE_IDX', 'mmSDMA3_PHYSICAL_ADDR_HI',
'mmSDMA3_PHYSICAL_ADDR_HI_BASE_IDX', 'mmSDMA3_PHYSICAL_ADDR_LO',
'mmSDMA3_PHYSICAL_ADDR_LO_BASE_IDX', 'mmSDMA3_POWER_CNTL',
'mmSDMA3_POWER_CNTL_BASE_IDX', 'mmSDMA3_PROGRAM',
'mmSDMA3_PROGRAM_BASE_IDX', 'mmSDMA3_PUB_DUMMY_REG0',
'mmSDMA3_PUB_DUMMY_REG0_BASE_IDX', 'mmSDMA3_PUB_DUMMY_REG1',
'mmSDMA3_PUB_DUMMY_REG1_BASE_IDX', 'mmSDMA3_PUB_DUMMY_REG2',
'mmSDMA3_PUB_DUMMY_REG2_BASE_IDX', 'mmSDMA3_PUB_DUMMY_REG3',
'mmSDMA3_PUB_DUMMY_REG3_BASE_IDX', 'mmSDMA3_PUB_REG_TYPE0',
'mmSDMA3_PUB_REG_TYPE0_BASE_IDX', 'mmSDMA3_PUB_REG_TYPE1',
'mmSDMA3_PUB_REG_TYPE1_BASE_IDX', 'mmSDMA3_PUB_REG_TYPE2',
'mmSDMA3_PUB_REG_TYPE2_BASE_IDX', 'mmSDMA3_PUB_REG_TYPE3',
'mmSDMA3_PUB_REG_TYPE3_BASE_IDX', 'mmSDMA3_QUEUE_RESET_REQ',
'mmSDMA3_QUEUE_RESET_REQ_BASE_IDX', 'mmSDMA3_RB_RPTR_FETCH',
'mmSDMA3_RB_RPTR_FETCH_BASE_IDX', 'mmSDMA3_RB_RPTR_FETCH_HI',
'mmSDMA3_RB_RPTR_FETCH_HI_BASE_IDX', 'mmSDMA3_RD_BURST_CNTL',
'mmSDMA3_RD_BURST_CNTL_BASE_IDX', 'mmSDMA3_RELAX_ORDERING_LUT',
'mmSDMA3_RELAX_ORDERING_LUT_BASE_IDX',
'mmSDMA3_RLC0_CONTEXT_STATUS',
'mmSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX',
'mmSDMA3_RLC0_CSA_ADDR_HI', 'mmSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC0_CSA_ADDR_LO', 'mmSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC0_DOORBELL', 'mmSDMA3_RLC0_DOORBELL_BASE_IDX',
'mmSDMA3_RLC0_DOORBELL_LOG', 'mmSDMA3_RLC0_DOORBELL_LOG_BASE_IDX',
'mmSDMA3_RLC0_DOORBELL_OFFSET',
'mmSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC0_DUMMY_REG',
'mmSDMA3_RLC0_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC0_IB_BASE_HI',
'mmSDMA3_RLC0_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC0_IB_BASE_LO',
'mmSDMA3_RLC0_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC0_IB_CNTL',
'mmSDMA3_RLC0_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC0_IB_OFFSET',
'mmSDMA3_RLC0_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC0_IB_RPTR',
'mmSDMA3_RLC0_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC0_IB_SIZE',
'mmSDMA3_RLC0_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC0_IB_SUB_REMAIN',
'mmSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_CNTL',
'mmSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA0',
'mmSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA1',
'mmSDMA3_RLC0_MIDCMD_DATA10',
'mmSDMA3_RLC0_MIDCMD_DATA10_BASE_IDX',
'mmSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA2',
'mmSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA3',
'mmSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA4',
'mmSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA5',
'mmSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA6',
'mmSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA7',
'mmSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA8',
'mmSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA9',
'mmSDMA3_RLC0_MIDCMD_DATA9_BASE_IDX',
'mmSDMA3_RLC0_MINOR_PTR_UPDATE',
'mmSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC0_PREEMPT',
'mmSDMA3_RLC0_PREEMPT_BASE_IDX', 'mmSDMA3_RLC0_RB_AQL_CNTL',
'mmSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC0_RB_BASE',
'mmSDMA3_RLC0_RB_BASE_BASE_IDX', 'mmSDMA3_RLC0_RB_BASE_HI',
'mmSDMA3_RLC0_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC0_RB_CNTL',
'mmSDMA3_RLC0_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC0_RB_RPTR',
'mmSDMA3_RLC0_RB_RPTR_ADDR_HI',
'mmSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC0_RB_RPTR_ADDR_LO',
'mmSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC0_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC0_RB_RPTR_HI',
'mmSDMA3_RLC0_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC0_RB_WPTR',
'mmSDMA3_RLC0_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC0_RB_WPTR_HI',
'mmSDMA3_RLC0_RB_WPTR_HI_BASE_IDX',
'mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI',
'mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO',
'mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC0_RB_WPTR_POLL_CNTL',
'mmSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA3_RLC0_SKIP_CNTL', 'mmSDMA3_RLC0_SKIP_CNTL_BASE_IDX',
'mmSDMA3_RLC0_STATUS', 'mmSDMA3_RLC0_STATUS_BASE_IDX',
'mmSDMA3_RLC0_WATERMARK', 'mmSDMA3_RLC0_WATERMARK_BASE_IDX',
'mmSDMA3_RLC1_CONTEXT_STATUS',
'mmSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX',
'mmSDMA3_RLC1_CSA_ADDR_HI', 'mmSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC1_CSA_ADDR_LO', 'mmSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC1_DOORBELL', 'mmSDMA3_RLC1_DOORBELL_BASE_IDX',
'mmSDMA3_RLC1_DOORBELL_LOG', 'mmSDMA3_RLC1_DOORBELL_LOG_BASE_IDX',
'mmSDMA3_RLC1_DOORBELL_OFFSET',
'mmSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC1_DUMMY_REG',
'mmSDMA3_RLC1_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC1_IB_BASE_HI',
'mmSDMA3_RLC1_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC1_IB_BASE_LO',
'mmSDMA3_RLC1_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC1_IB_CNTL',
'mmSDMA3_RLC1_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC1_IB_OFFSET',
'mmSDMA3_RLC1_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC1_IB_RPTR',
'mmSDMA3_RLC1_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC1_IB_SIZE',
'mmSDMA3_RLC1_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC1_IB_SUB_REMAIN',
'mmSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_CNTL',
'mmSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA0',
'mmSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA1',
'mmSDMA3_RLC1_MIDCMD_DATA10',
'mmSDMA3_RLC1_MIDCMD_DATA10_BASE_IDX',
'mmSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA2',
'mmSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA3',
'mmSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA4',
'mmSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA5',
'mmSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA6',
'mmSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA7',
'mmSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA8',
'mmSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA9',
'mmSDMA3_RLC1_MIDCMD_DATA9_BASE_IDX',
'mmSDMA3_RLC1_MINOR_PTR_UPDATE',
'mmSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC1_PREEMPT',
'mmSDMA3_RLC1_PREEMPT_BASE_IDX', 'mmSDMA3_RLC1_RB_AQL_CNTL',
'mmSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC1_RB_BASE',
'mmSDMA3_RLC1_RB_BASE_BASE_IDX', 'mmSDMA3_RLC1_RB_BASE_HI',
'mmSDMA3_RLC1_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC1_RB_CNTL',
'mmSDMA3_RLC1_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC1_RB_RPTR',
'mmSDMA3_RLC1_RB_RPTR_ADDR_HI',
'mmSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC1_RB_RPTR_ADDR_LO',
'mmSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC1_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC1_RB_RPTR_HI',
'mmSDMA3_RLC1_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC1_RB_WPTR',
'mmSDMA3_RLC1_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC1_RB_WPTR_HI',
'mmSDMA3_RLC1_RB_WPTR_HI_BASE_IDX',
'mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI',
'mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO',
'mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC1_RB_WPTR_POLL_CNTL',
'mmSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA3_RLC1_SKIP_CNTL', 'mmSDMA3_RLC1_SKIP_CNTL_BASE_IDX',
'mmSDMA3_RLC1_STATUS', 'mmSDMA3_RLC1_STATUS_BASE_IDX',
'mmSDMA3_RLC1_WATERMARK', 'mmSDMA3_RLC1_WATERMARK_BASE_IDX',
'mmSDMA3_RLC2_CONTEXT_STATUS',
'mmSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX',
'mmSDMA3_RLC2_CSA_ADDR_HI', 'mmSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC2_CSA_ADDR_LO', 'mmSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC2_DOORBELL', 'mmSDMA3_RLC2_DOORBELL_BASE_IDX',
'mmSDMA3_RLC2_DOORBELL_LOG', 'mmSDMA3_RLC2_DOORBELL_LOG_BASE_IDX',
'mmSDMA3_RLC2_DOORBELL_OFFSET',
'mmSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC2_DUMMY_REG',
'mmSDMA3_RLC2_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC2_IB_BASE_HI',
'mmSDMA3_RLC2_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC2_IB_BASE_LO',
'mmSDMA3_RLC2_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC2_IB_CNTL',
'mmSDMA3_RLC2_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC2_IB_OFFSET',
'mmSDMA3_RLC2_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC2_IB_RPTR',
'mmSDMA3_RLC2_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC2_IB_SIZE',
'mmSDMA3_RLC2_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC2_IB_SUB_REMAIN',
'mmSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_CNTL',
'mmSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA0',
'mmSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA1',
'mmSDMA3_RLC2_MIDCMD_DATA10',
'mmSDMA3_RLC2_MIDCMD_DATA10_BASE_IDX',
'mmSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA2',
'mmSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA3',
'mmSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA4',
'mmSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA5',
'mmSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA6',
'mmSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA7',
'mmSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA8',
'mmSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA9',
'mmSDMA3_RLC2_MIDCMD_DATA9_BASE_IDX',
'mmSDMA3_RLC2_MINOR_PTR_UPDATE',
'mmSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC2_PREEMPT',
'mmSDMA3_RLC2_PREEMPT_BASE_IDX', 'mmSDMA3_RLC2_RB_AQL_CNTL',
'mmSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC2_RB_BASE',
'mmSDMA3_RLC2_RB_BASE_BASE_IDX', 'mmSDMA3_RLC2_RB_BASE_HI',
'mmSDMA3_RLC2_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC2_RB_CNTL',
'mmSDMA3_RLC2_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC2_RB_RPTR',
'mmSDMA3_RLC2_RB_RPTR_ADDR_HI',
'mmSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC2_RB_RPTR_ADDR_LO',
'mmSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC2_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC2_RB_RPTR_HI',
'mmSDMA3_RLC2_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC2_RB_WPTR',
'mmSDMA3_RLC2_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC2_RB_WPTR_HI',
'mmSDMA3_RLC2_RB_WPTR_HI_BASE_IDX',
'mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI',
'mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO',
'mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC2_RB_WPTR_POLL_CNTL',
'mmSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA3_RLC2_SKIP_CNTL', 'mmSDMA3_RLC2_SKIP_CNTL_BASE_IDX',
'mmSDMA3_RLC2_STATUS', 'mmSDMA3_RLC2_STATUS_BASE_IDX',
'mmSDMA3_RLC2_WATERMARK', 'mmSDMA3_RLC2_WATERMARK_BASE_IDX',
'mmSDMA3_RLC3_CONTEXT_STATUS',
'mmSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX',
'mmSDMA3_RLC3_CSA_ADDR_HI', 'mmSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC3_CSA_ADDR_LO', 'mmSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC3_DOORBELL', 'mmSDMA3_RLC3_DOORBELL_BASE_IDX',
'mmSDMA3_RLC3_DOORBELL_LOG', 'mmSDMA3_RLC3_DOORBELL_LOG_BASE_IDX',
'mmSDMA3_RLC3_DOORBELL_OFFSET',
'mmSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC3_DUMMY_REG',
'mmSDMA3_RLC3_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC3_IB_BASE_HI',
'mmSDMA3_RLC3_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC3_IB_BASE_LO',
'mmSDMA3_RLC3_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC3_IB_CNTL',
'mmSDMA3_RLC3_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC3_IB_OFFSET',
'mmSDMA3_RLC3_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC3_IB_RPTR',
'mmSDMA3_RLC3_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC3_IB_SIZE',
'mmSDMA3_RLC3_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC3_IB_SUB_REMAIN',
'mmSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_CNTL',
'mmSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA0',
'mmSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA1',
'mmSDMA3_RLC3_MIDCMD_DATA10',
'mmSDMA3_RLC3_MIDCMD_DATA10_BASE_IDX',
'mmSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA2',
'mmSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA3',
'mmSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA4',
'mmSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA5',
'mmSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA6',
'mmSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA7',
'mmSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA8',
'mmSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA9',
'mmSDMA3_RLC3_MIDCMD_DATA9_BASE_IDX',
'mmSDMA3_RLC3_MINOR_PTR_UPDATE',
'mmSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC3_PREEMPT',
'mmSDMA3_RLC3_PREEMPT_BASE_IDX', 'mmSDMA3_RLC3_RB_AQL_CNTL',
'mmSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC3_RB_BASE',
'mmSDMA3_RLC3_RB_BASE_BASE_IDX', 'mmSDMA3_RLC3_RB_BASE_HI',
'mmSDMA3_RLC3_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC3_RB_CNTL',
'mmSDMA3_RLC3_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC3_RB_RPTR',
'mmSDMA3_RLC3_RB_RPTR_ADDR_HI',
'mmSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC3_RB_RPTR_ADDR_LO',
'mmSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC3_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC3_RB_RPTR_HI',
'mmSDMA3_RLC3_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC3_RB_WPTR',
'mmSDMA3_RLC3_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC3_RB_WPTR_HI',
'mmSDMA3_RLC3_RB_WPTR_HI_BASE_IDX',
'mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI',
'mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO',
'mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC3_RB_WPTR_POLL_CNTL',
'mmSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA3_RLC3_SKIP_CNTL', 'mmSDMA3_RLC3_SKIP_CNTL_BASE_IDX',
'mmSDMA3_RLC3_STATUS', 'mmSDMA3_RLC3_STATUS_BASE_IDX',
'mmSDMA3_RLC3_WATERMARK', 'mmSDMA3_RLC3_WATERMARK_BASE_IDX',
'mmSDMA3_RLC4_CONTEXT_STATUS',
'mmSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX',
'mmSDMA3_RLC4_CSA_ADDR_HI', 'mmSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC4_CSA_ADDR_LO', 'mmSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC4_DOORBELL', 'mmSDMA3_RLC4_DOORBELL_BASE_IDX',
'mmSDMA3_RLC4_DOORBELL_LOG', 'mmSDMA3_RLC4_DOORBELL_LOG_BASE_IDX',
'mmSDMA3_RLC4_DOORBELL_OFFSET',
'mmSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC4_DUMMY_REG',
'mmSDMA3_RLC4_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC4_IB_BASE_HI',
'mmSDMA3_RLC4_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC4_IB_BASE_LO',
'mmSDMA3_RLC4_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC4_IB_CNTL',
'mmSDMA3_RLC4_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC4_IB_OFFSET',
'mmSDMA3_RLC4_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC4_IB_RPTR',
'mmSDMA3_RLC4_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC4_IB_SIZE',
'mmSDMA3_RLC4_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC4_IB_SUB_REMAIN',
'mmSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_CNTL',
'mmSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA0',
'mmSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA1',
'mmSDMA3_RLC4_MIDCMD_DATA10',
'mmSDMA3_RLC4_MIDCMD_DATA10_BASE_IDX',
'mmSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA2',
'mmSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA3',
'mmSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA4',
'mmSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA5',
'mmSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA6',
'mmSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA7',
'mmSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA8',
'mmSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA9',
'mmSDMA3_RLC4_MIDCMD_DATA9_BASE_IDX',
'mmSDMA3_RLC4_MINOR_PTR_UPDATE',
'mmSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC4_PREEMPT',
'mmSDMA3_RLC4_PREEMPT_BASE_IDX', 'mmSDMA3_RLC4_RB_AQL_CNTL',
'mmSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC4_RB_BASE',
'mmSDMA3_RLC4_RB_BASE_BASE_IDX', 'mmSDMA3_RLC4_RB_BASE_HI',
'mmSDMA3_RLC4_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC4_RB_CNTL',
'mmSDMA3_RLC4_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC4_RB_RPTR',
'mmSDMA3_RLC4_RB_RPTR_ADDR_HI',
'mmSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC4_RB_RPTR_ADDR_LO',
'mmSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC4_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC4_RB_RPTR_HI',
'mmSDMA3_RLC4_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC4_RB_WPTR',
'mmSDMA3_RLC4_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC4_RB_WPTR_HI',
'mmSDMA3_RLC4_RB_WPTR_HI_BASE_IDX',
'mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI',
'mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO',
'mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC4_RB_WPTR_POLL_CNTL',
'mmSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA3_RLC4_SKIP_CNTL', 'mmSDMA3_RLC4_SKIP_CNTL_BASE_IDX',
'mmSDMA3_RLC4_STATUS', 'mmSDMA3_RLC4_STATUS_BASE_IDX',
'mmSDMA3_RLC4_WATERMARK', 'mmSDMA3_RLC4_WATERMARK_BASE_IDX',
'mmSDMA3_RLC5_CONTEXT_STATUS',
'mmSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX',
'mmSDMA3_RLC5_CSA_ADDR_HI', 'mmSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC5_CSA_ADDR_LO', 'mmSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC5_DOORBELL', 'mmSDMA3_RLC5_DOORBELL_BASE_IDX',
'mmSDMA3_RLC5_DOORBELL_LOG', 'mmSDMA3_RLC5_DOORBELL_LOG_BASE_IDX',
'mmSDMA3_RLC5_DOORBELL_OFFSET',
'mmSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC5_DUMMY_REG',
'mmSDMA3_RLC5_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC5_IB_BASE_HI',
'mmSDMA3_RLC5_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC5_IB_BASE_LO',
'mmSDMA3_RLC5_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC5_IB_CNTL',
'mmSDMA3_RLC5_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC5_IB_OFFSET',
'mmSDMA3_RLC5_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC5_IB_RPTR',
'mmSDMA3_RLC5_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC5_IB_SIZE',
'mmSDMA3_RLC5_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC5_IB_SUB_REMAIN',
'mmSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_CNTL',
'mmSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA0',
'mmSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA1',
'mmSDMA3_RLC5_MIDCMD_DATA10',
'mmSDMA3_RLC5_MIDCMD_DATA10_BASE_IDX',
'mmSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA2',
'mmSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA3',
'mmSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA4',
'mmSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA5',
'mmSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA6',
'mmSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA7',
'mmSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA8',
'mmSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA9',
'mmSDMA3_RLC5_MIDCMD_DATA9_BASE_IDX',
'mmSDMA3_RLC5_MINOR_PTR_UPDATE',
'mmSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC5_PREEMPT',
'mmSDMA3_RLC5_PREEMPT_BASE_IDX', 'mmSDMA3_RLC5_RB_AQL_CNTL',
'mmSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC5_RB_BASE',
'mmSDMA3_RLC5_RB_BASE_BASE_IDX', 'mmSDMA3_RLC5_RB_BASE_HI',
'mmSDMA3_RLC5_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC5_RB_CNTL',
'mmSDMA3_RLC5_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC5_RB_RPTR',
'mmSDMA3_RLC5_RB_RPTR_ADDR_HI',
'mmSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC5_RB_RPTR_ADDR_LO',
'mmSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC5_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC5_RB_RPTR_HI',
'mmSDMA3_RLC5_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC5_RB_WPTR',
'mmSDMA3_RLC5_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC5_RB_WPTR_HI',
'mmSDMA3_RLC5_RB_WPTR_HI_BASE_IDX',
'mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI',
'mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO',
'mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC5_RB_WPTR_POLL_CNTL',
'mmSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA3_RLC5_SKIP_CNTL', 'mmSDMA3_RLC5_SKIP_CNTL_BASE_IDX',
'mmSDMA3_RLC5_STATUS', 'mmSDMA3_RLC5_STATUS_BASE_IDX',
'mmSDMA3_RLC5_WATERMARK', 'mmSDMA3_RLC5_WATERMARK_BASE_IDX',
'mmSDMA3_RLC6_CONTEXT_STATUS',
'mmSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX',
'mmSDMA3_RLC6_CSA_ADDR_HI', 'mmSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC6_CSA_ADDR_LO', 'mmSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC6_DOORBELL', 'mmSDMA3_RLC6_DOORBELL_BASE_IDX',
'mmSDMA3_RLC6_DOORBELL_LOG', 'mmSDMA3_RLC6_DOORBELL_LOG_BASE_IDX',
'mmSDMA3_RLC6_DOORBELL_OFFSET',
'mmSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC6_DUMMY_REG',
'mmSDMA3_RLC6_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC6_IB_BASE_HI',
'mmSDMA3_RLC6_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC6_IB_BASE_LO',
'mmSDMA3_RLC6_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC6_IB_CNTL',
'mmSDMA3_RLC6_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC6_IB_OFFSET',
'mmSDMA3_RLC6_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC6_IB_RPTR',
'mmSDMA3_RLC6_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC6_IB_SIZE',
'mmSDMA3_RLC6_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC6_IB_SUB_REMAIN',
'mmSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_CNTL',
'mmSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA0',
'mmSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA1',
'mmSDMA3_RLC6_MIDCMD_DATA10',
'mmSDMA3_RLC6_MIDCMD_DATA10_BASE_IDX',
'mmSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA2',
'mmSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA3',
'mmSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA4',
'mmSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA5',
'mmSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA6',
'mmSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA7',
'mmSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA8',
'mmSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA9',
'mmSDMA3_RLC6_MIDCMD_DATA9_BASE_IDX',
'mmSDMA3_RLC6_MINOR_PTR_UPDATE',
'mmSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC6_PREEMPT',
'mmSDMA3_RLC6_PREEMPT_BASE_IDX', 'mmSDMA3_RLC6_RB_AQL_CNTL',
'mmSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC6_RB_BASE',
'mmSDMA3_RLC6_RB_BASE_BASE_IDX', 'mmSDMA3_RLC6_RB_BASE_HI',
'mmSDMA3_RLC6_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC6_RB_CNTL',
'mmSDMA3_RLC6_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC6_RB_RPTR',
'mmSDMA3_RLC6_RB_RPTR_ADDR_HI',
'mmSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC6_RB_RPTR_ADDR_LO',
'mmSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC6_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC6_RB_RPTR_HI',
'mmSDMA3_RLC6_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC6_RB_WPTR',
'mmSDMA3_RLC6_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC6_RB_WPTR_HI',
'mmSDMA3_RLC6_RB_WPTR_HI_BASE_IDX',
'mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI',
'mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO',
'mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC6_RB_WPTR_POLL_CNTL',
'mmSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA3_RLC6_SKIP_CNTL', 'mmSDMA3_RLC6_SKIP_CNTL_BASE_IDX',
'mmSDMA3_RLC6_STATUS', 'mmSDMA3_RLC6_STATUS_BASE_IDX',
'mmSDMA3_RLC6_WATERMARK', 'mmSDMA3_RLC6_WATERMARK_BASE_IDX',
'mmSDMA3_RLC7_CONTEXT_STATUS',
'mmSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX',
'mmSDMA3_RLC7_CSA_ADDR_HI', 'mmSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC7_CSA_ADDR_LO', 'mmSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC7_DOORBELL', 'mmSDMA3_RLC7_DOORBELL_BASE_IDX',
'mmSDMA3_RLC7_DOORBELL_LOG', 'mmSDMA3_RLC7_DOORBELL_LOG_BASE_IDX',
'mmSDMA3_RLC7_DOORBELL_OFFSET',
'mmSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC7_DUMMY_REG',
'mmSDMA3_RLC7_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC7_IB_BASE_HI',
'mmSDMA3_RLC7_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC7_IB_BASE_LO',
'mmSDMA3_RLC7_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC7_IB_CNTL',
'mmSDMA3_RLC7_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC7_IB_OFFSET',
'mmSDMA3_RLC7_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC7_IB_RPTR',
'mmSDMA3_RLC7_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC7_IB_SIZE',
'mmSDMA3_RLC7_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC7_IB_SUB_REMAIN',
'mmSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_CNTL',
'mmSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA0',
'mmSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA1',
'mmSDMA3_RLC7_MIDCMD_DATA10',
'mmSDMA3_RLC7_MIDCMD_DATA10_BASE_IDX',
'mmSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA2',
'mmSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA3',
'mmSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA4',
'mmSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA5',
'mmSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA6',
'mmSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA7',
'mmSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA8',
'mmSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA9',
'mmSDMA3_RLC7_MIDCMD_DATA9_BASE_IDX',
'mmSDMA3_RLC7_MINOR_PTR_UPDATE',
'mmSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC7_PREEMPT',
'mmSDMA3_RLC7_PREEMPT_BASE_IDX', 'mmSDMA3_RLC7_RB_AQL_CNTL',
'mmSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC7_RB_BASE',
'mmSDMA3_RLC7_RB_BASE_BASE_IDX', 'mmSDMA3_RLC7_RB_BASE_HI',
'mmSDMA3_RLC7_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC7_RB_CNTL',
'mmSDMA3_RLC7_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC7_RB_RPTR',
'mmSDMA3_RLC7_RB_RPTR_ADDR_HI',
'mmSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC7_RB_RPTR_ADDR_LO',
'mmSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC7_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC7_RB_RPTR_HI',
'mmSDMA3_RLC7_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC7_RB_WPTR',
'mmSDMA3_RLC7_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC7_RB_WPTR_HI',
'mmSDMA3_RLC7_RB_WPTR_HI_BASE_IDX',
'mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI',
'mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO',
'mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'mmSDMA3_RLC7_RB_WPTR_POLL_CNTL',
'mmSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX',
'mmSDMA3_RLC7_SKIP_CNTL', 'mmSDMA3_RLC7_SKIP_CNTL_BASE_IDX',
'mmSDMA3_RLC7_STATUS', 'mmSDMA3_RLC7_STATUS_BASE_IDX',
'mmSDMA3_RLC7_WATERMARK', 'mmSDMA3_RLC7_WATERMARK_BASE_IDX',
'mmSDMA3_SCRATCH_RAM_ADDR', 'mmSDMA3_SCRATCH_RAM_ADDR_BASE_IDX',
'mmSDMA3_SCRATCH_RAM_DATA', 'mmSDMA3_SCRATCH_RAM_DATA_BASE_IDX',
'mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL',
'mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX',
'mmSDMA3_STATUS1_REG', 'mmSDMA3_STATUS1_REG_BASE_IDX',
'mmSDMA3_STATUS2_REG', 'mmSDMA3_STATUS2_REG_BASE_IDX',
'mmSDMA3_STATUS3_REG', 'mmSDMA3_STATUS3_REG_BASE_IDX',
'mmSDMA3_STATUS4_REG', 'mmSDMA3_STATUS4_REG_BASE_IDX',
'mmSDMA3_STATUS5_REG', 'mmSDMA3_STATUS5_REG_BASE_IDX',
'mmSDMA3_STATUS_REG', 'mmSDMA3_STATUS_REG_BASE_IDX',
'mmSDMA3_TILING_CONFIG', 'mmSDMA3_TILING_CONFIG_BASE_IDX',
'mmSDMA3_TIMESTAMP_CNTL', 'mmSDMA3_TIMESTAMP_CNTL_BASE_IDX',
'mmSDMA3_TLBI_GCR_CNTL', 'mmSDMA3_TLBI_GCR_CNTL_BASE_IDX',
'mmSDMA3_UCODE_ADDR', 'mmSDMA3_UCODE_ADDR_BASE_IDX',
'mmSDMA3_UCODE_CHECKSUM', 'mmSDMA3_UCODE_CHECKSUM_BASE_IDX',
'mmSDMA3_UCODE_DATA', 'mmSDMA3_UCODE_DATA_BASE_IDX',
'mmSDMA3_UTCL1_CNTL', 'mmSDMA3_UTCL1_CNTL_BASE_IDX',
'mmSDMA3_UTCL1_INV0', 'mmSDMA3_UTCL1_INV0_BASE_IDX',
'mmSDMA3_UTCL1_INV1', 'mmSDMA3_UTCL1_INV1_BASE_IDX',
'mmSDMA3_UTCL1_INV2', 'mmSDMA3_UTCL1_INV2_BASE_IDX',
'mmSDMA3_UTCL1_PAGE', 'mmSDMA3_UTCL1_PAGE_BASE_IDX',
'mmSDMA3_UTCL1_RD_STATUS', 'mmSDMA3_UTCL1_RD_STATUS_BASE_IDX',
'mmSDMA3_UTCL1_RD_XNACK0', 'mmSDMA3_UTCL1_RD_XNACK0_BASE_IDX',
'mmSDMA3_UTCL1_RD_XNACK1', 'mmSDMA3_UTCL1_RD_XNACK1_BASE_IDX',
'mmSDMA3_UTCL1_TIMEOUT', 'mmSDMA3_UTCL1_TIMEOUT_BASE_IDX',
'mmSDMA3_UTCL1_WATERMK', 'mmSDMA3_UTCL1_WATERMK_BASE_IDX',
'mmSDMA3_UTCL1_WR_STATUS', 'mmSDMA3_UTCL1_WR_STATUS_BASE_IDX',
'mmSDMA3_UTCL1_WR_XNACK0', 'mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX',
'mmSDMA3_UTCL1_WR_XNACK1', 'mmSDMA3_UTCL1_WR_XNACK1_BASE_IDX',
'mmSDMA3_VERSION', 'mmSDMA3_VERSION_BASE_IDX',
'mmSDMA3_VF_ENABLE', 'mmSDMA3_VF_ENABLE_BASE_IDX',
'mmSDMA3_VIRT_RESET_REQ', 'mmSDMA3_VIRT_RESET_REQ_BASE_IDX',
'mmSDMA3_VM_CNTL', 'mmSDMA3_VM_CNTL_BASE_IDX',
'mmSDMA3_VM_CTX_CNTL', 'mmSDMA3_VM_CTX_CNTL_BASE_IDX',
'mmSDMA3_VM_CTX_HI', 'mmSDMA3_VM_CTX_HI_BASE_IDX',
'mmSDMA3_VM_CTX_LO', 'mmSDMA3_VM_CTX_LO_BASE_IDX',
'mmSE_CAC_CGTT_CLK_CTRL', 'mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX',
'mmSE_CAC_IND_DATA', 'mmSE_CAC_IND_DATA_BASE_IDX',
'mmSE_CAC_IND_INDEX', 'mmSE_CAC_IND_INDEX_BASE_IDX',
'mmSH_MEM_BASES', 'mmSH_MEM_BASES_BASE_IDX', 'mmSH_MEM_CONFIG',
'mmSH_MEM_CONFIG_BASE_IDX', 'mmSH_RESERVED_REG0',
'mmSH_RESERVED_REG0_BASE_IDX', 'mmSH_RESERVED_REG1',
'mmSH_RESERVED_REG1_BASE_IDX', 'mmSMU_RLC_RESPONSE',
'mmSMU_RLC_RESPONSE_BASE_IDX', 'mmSPI_ARB_CNTL_0',
'mmSPI_ARB_CNTL_0_BASE_IDX', 'mmSPI_ARB_CYCLES_0',
'mmSPI_ARB_CYCLES_0_BASE_IDX', 'mmSPI_ARB_CYCLES_1',
'mmSPI_ARB_CYCLES_1_BASE_IDX', 'mmSPI_ARB_PRIORITY',
'mmSPI_ARB_PRIORITY_BASE_IDX', 'mmSPI_BARYC_CNTL',
'mmSPI_BARYC_CNTL_BASE_IDX', 'mmSPI_COMPUTE_QUEUE_RESET',
'mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX', 'mmSPI_COMPUTE_WF_CTX_SAVE',
'mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX', 'mmSPI_CONFIG_CNTL',
'mmSPI_CONFIG_CNTL_1', 'mmSPI_CONFIG_CNTL_1_BASE_IDX',
'mmSPI_CONFIG_CNTL_1_REMAP', 'mmSPI_CONFIG_CNTL_1_REMAP_BASE_IDX',
'mmSPI_CONFIG_CNTL_2', 'mmSPI_CONFIG_CNTL_2_BASE_IDX',
'mmSPI_CONFIG_CNTL_2_REMAP', 'mmSPI_CONFIG_CNTL_2_REMAP_BASE_IDX',
'mmSPI_CONFIG_CNTL_BASE_IDX', 'mmSPI_CONFIG_CNTL_REMAP',
'mmSPI_CONFIG_CNTL_REMAP_BASE_IDX', 'mmSPI_CONFIG_PS_CU_EN',
'mmSPI_CONFIG_PS_CU_EN_BASE_IDX', 'mmSPI_CSQ_WF_ACTIVE_COUNT_0',
'mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX',
'mmSPI_CSQ_WF_ACTIVE_COUNT_1',
'mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX',
'mmSPI_CSQ_WF_ACTIVE_COUNT_2',
'mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX',
'mmSPI_CSQ_WF_ACTIVE_COUNT_3',
'mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX',
'mmSPI_CSQ_WF_ACTIVE_STATUS',
'mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX', 'mmSPI_DSM_CNTL',
'mmSPI_DSM_CNTL2', 'mmSPI_DSM_CNTL2_BASE_IDX',
'mmSPI_DSM_CNTL_BASE_IDX', 'mmSPI_EDC_CNT',
'mmSPI_EDC_CNT_BASE_IDX', 'mmSPI_EXP_THROTTLE_CTRL',
'mmSPI_EXP_THROTTLE_CTRL_BASE_IDX', 'mmSPI_FEATURE_CTRL',
'mmSPI_FEATURE_CTRL_BASE_IDX', 'mmSPI_GDBG_TRAP_CONFIG',
'mmSPI_GDBG_TRAP_CONFIG_BASE_IDX', 'mmSPI_GDBG_TRAP_DATA0',
'mmSPI_GDBG_TRAP_DATA0_BASE_IDX', 'mmSPI_GDBG_TRAP_DATA1',
'mmSPI_GDBG_TRAP_DATA1_BASE_IDX', 'mmSPI_GDBG_TRAP_MASK',
'mmSPI_GDBG_TRAP_MASK_BASE_IDX', 'mmSPI_GDBG_WAVE_CNTL',
'mmSPI_GDBG_WAVE_CNTL2', 'mmSPI_GDBG_WAVE_CNTL2_BASE_IDX',
'mmSPI_GDBG_WAVE_CNTL3', 'mmSPI_GDBG_WAVE_CNTL3_BASE_IDX',
'mmSPI_GDBG_WAVE_CNTL_BASE_IDX', 'mmSPI_GDS_CREDITS',
'mmSPI_GDS_CREDITS_BASE_IDX', 'mmSPI_GFX_CNTL',
'mmSPI_GFX_CNTL_BASE_IDX', 'mmSPI_INTERP_CONTROL_0',
'mmSPI_INTERP_CONTROL_0_BASE_IDX', 'mmSPI_LB_CTR_CTRL',
'mmSPI_LB_CTR_CTRL_BASE_IDX', 'mmSPI_LB_DATA_PERWGP_WAVE_CS',
'mmSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX',
'mmSPI_LB_DATA_PERWGP_WAVE_HSGS',
'mmSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX',
'mmSPI_LB_DATA_PERWGP_WAVE_VSPS',
'mmSPI_LB_DATA_PERWGP_WAVE_VSPS_BASE_IDX', 'mmSPI_LB_DATA_REG',
'mmSPI_LB_DATA_REG_BASE_IDX', 'mmSPI_LB_DATA_WAVES',
'mmSPI_LB_DATA_WAVES_BASE_IDX', 'mmSPI_LB_WGP_MASK',
'mmSPI_LB_WGP_MASK_BASE_IDX', 'mmSPI_P0_TRAP_SCREEN_GPR_MIN',
'mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX',
'mmSPI_P0_TRAP_SCREEN_PSBA_HI',
'mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX',
'mmSPI_P0_TRAP_SCREEN_PSBA_LO',
'mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX',
'mmSPI_P0_TRAP_SCREEN_PSMA_HI',
'mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX',
'mmSPI_P0_TRAP_SCREEN_PSMA_LO',
'mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX',
'mmSPI_P1_TRAP_SCREEN_GPR_MIN',
'mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX',
'mmSPI_P1_TRAP_SCREEN_PSBA_HI',
'mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX',
'mmSPI_P1_TRAP_SCREEN_PSBA_LO',
'mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX',
'mmSPI_P1_TRAP_SCREEN_PSMA_HI',
'mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX',
'mmSPI_P1_TRAP_SCREEN_PSMA_LO',
'mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX', 'mmSPI_PERFCOUNTER0_HI',
'mmSPI_PERFCOUNTER0_HI_BASE_IDX', 'mmSPI_PERFCOUNTER0_LO',
'mmSPI_PERFCOUNTER0_LO_BASE_IDX', 'mmSPI_PERFCOUNTER0_SELECT',
'mmSPI_PERFCOUNTER0_SELECT1',
'mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmSPI_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER1_HI',
'mmSPI_PERFCOUNTER1_HI_BASE_IDX', 'mmSPI_PERFCOUNTER1_LO',
'mmSPI_PERFCOUNTER1_LO_BASE_IDX', 'mmSPI_PERFCOUNTER1_SELECT',
'mmSPI_PERFCOUNTER1_SELECT1',
'mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmSPI_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER2_HI',
'mmSPI_PERFCOUNTER2_HI_BASE_IDX', 'mmSPI_PERFCOUNTER2_LO',
'mmSPI_PERFCOUNTER2_LO_BASE_IDX', 'mmSPI_PERFCOUNTER2_SELECT',
'mmSPI_PERFCOUNTER2_SELECT1',
'mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX',
'mmSPI_PERFCOUNTER2_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER3_HI',
'mmSPI_PERFCOUNTER3_HI_BASE_IDX', 'mmSPI_PERFCOUNTER3_LO',
'mmSPI_PERFCOUNTER3_LO_BASE_IDX', 'mmSPI_PERFCOUNTER3_SELECT',
'mmSPI_PERFCOUNTER3_SELECT1',
'mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX',
'mmSPI_PERFCOUNTER3_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER4_HI',
'mmSPI_PERFCOUNTER4_HI_BASE_IDX', 'mmSPI_PERFCOUNTER4_LO',
'mmSPI_PERFCOUNTER4_LO_BASE_IDX', 'mmSPI_PERFCOUNTER4_SELECT',
'mmSPI_PERFCOUNTER4_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER5_HI',
'mmSPI_PERFCOUNTER5_HI_BASE_IDX', 'mmSPI_PERFCOUNTER5_LO',
'mmSPI_PERFCOUNTER5_LO_BASE_IDX', 'mmSPI_PERFCOUNTER5_SELECT',
'mmSPI_PERFCOUNTER5_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER_BINS',
'mmSPI_PERFCOUNTER_BINS_BASE_IDX',
'mmSPI_PG_ENABLE_STATIC_WGP_MASK',
'mmSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX', 'mmSPI_PQEV_CTRL',
'mmSPI_PQEV_CTRL_BASE_IDX', 'mmSPI_PS_INPUT_ADDR',
'mmSPI_PS_INPUT_ADDR_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_0',
'mmSPI_PS_INPUT_CNTL_0_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_1',
'mmSPI_PS_INPUT_CNTL_10', 'mmSPI_PS_INPUT_CNTL_10_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_11', 'mmSPI_PS_INPUT_CNTL_11_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_12', 'mmSPI_PS_INPUT_CNTL_12_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_13', 'mmSPI_PS_INPUT_CNTL_13_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_14', 'mmSPI_PS_INPUT_CNTL_14_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_15', 'mmSPI_PS_INPUT_CNTL_15_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_16', 'mmSPI_PS_INPUT_CNTL_16_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_17', 'mmSPI_PS_INPUT_CNTL_17_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_18', 'mmSPI_PS_INPUT_CNTL_18_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_19', 'mmSPI_PS_INPUT_CNTL_19_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_1_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_2',
'mmSPI_PS_INPUT_CNTL_20', 'mmSPI_PS_INPUT_CNTL_20_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_21', 'mmSPI_PS_INPUT_CNTL_21_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_22', 'mmSPI_PS_INPUT_CNTL_22_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_23', 'mmSPI_PS_INPUT_CNTL_23_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_24', 'mmSPI_PS_INPUT_CNTL_24_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_25', 'mmSPI_PS_INPUT_CNTL_25_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_26', 'mmSPI_PS_INPUT_CNTL_26_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_27', 'mmSPI_PS_INPUT_CNTL_27_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_28', 'mmSPI_PS_INPUT_CNTL_28_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_29', 'mmSPI_PS_INPUT_CNTL_29_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_2_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_3',
'mmSPI_PS_INPUT_CNTL_30', 'mmSPI_PS_INPUT_CNTL_30_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_31', 'mmSPI_PS_INPUT_CNTL_31_BASE_IDX',
'mmSPI_PS_INPUT_CNTL_3_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_4',
'mmSPI_PS_INPUT_CNTL_4_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_5',
'mmSPI_PS_INPUT_CNTL_5_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_6',
'mmSPI_PS_INPUT_CNTL_6_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_7',
'mmSPI_PS_INPUT_CNTL_7_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_8',
'mmSPI_PS_INPUT_CNTL_8_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_9',
'mmSPI_PS_INPUT_CNTL_9_BASE_IDX', 'mmSPI_PS_INPUT_ENA',
'mmSPI_PS_INPUT_ENA_BASE_IDX', 'mmSPI_PS_IN_CONTROL',
'mmSPI_PS_IN_CONTROL_BASE_IDX', 'mmSPI_PS_MAX_WAVE_ID',
'mmSPI_PS_MAX_WAVE_ID_BASE_IDX', 'mmSPI_RESOURCE_RESERVE_CU_0',
'mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_CU_1',
'mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_CU_2',
'mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_CU_3',
'mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_CU_4',
'mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_CU_5',
'mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_CU_6',
'mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_CU_7',
'mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_CU_8',
'mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_CU_9',
'mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_EN_CU_0',
'mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_EN_CU_1',
'mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_EN_CU_2',
'mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_EN_CU_3',
'mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_EN_CU_4',
'mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_EN_CU_5',
'mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_EN_CU_6',
'mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_EN_CU_7',
'mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_EN_CU_8',
'mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX',
'mmSPI_RESOURCE_RESERVE_EN_CU_9',
'mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX',
'mmSPI_SHADER_COL_FORMAT', 'mmSPI_SHADER_COL_FORMAT_BASE_IDX',
'mmSPI_SHADER_IDX_FORMAT', 'mmSPI_SHADER_IDX_FORMAT_BASE_IDX',
'mmSPI_SHADER_LATE_ALLOC_VS',
'mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX',
'mmSPI_SHADER_PGM_CHKSUM_GS',
'mmSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX',
'mmSPI_SHADER_PGM_CHKSUM_HS',
'mmSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX',
'mmSPI_SHADER_PGM_CHKSUM_PS',
'mmSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX',
'mmSPI_SHADER_PGM_CHKSUM_VS',
'mmSPI_SHADER_PGM_CHKSUM_VS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_ES',
'mmSPI_SHADER_PGM_HI_ES_BASE_IDX', 'mmSPI_SHADER_PGM_HI_ES_GS',
'mmSPI_SHADER_PGM_HI_ES_GS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_GS',
'mmSPI_SHADER_PGM_HI_GS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_HS',
'mmSPI_SHADER_PGM_HI_HS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_LS',
'mmSPI_SHADER_PGM_HI_LS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_LS_HS',
'mmSPI_SHADER_PGM_HI_LS_HS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_PS',
'mmSPI_SHADER_PGM_HI_PS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_VS',
'mmSPI_SHADER_PGM_HI_VS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_ES',
'mmSPI_SHADER_PGM_LO_ES_BASE_IDX', 'mmSPI_SHADER_PGM_LO_ES_GS',
'mmSPI_SHADER_PGM_LO_ES_GS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_GS',
'mmSPI_SHADER_PGM_LO_GS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_HS',
'mmSPI_SHADER_PGM_LO_HS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_LS',
'mmSPI_SHADER_PGM_LO_LS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_LS_HS',
'mmSPI_SHADER_PGM_LO_LS_HS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_PS',
'mmSPI_SHADER_PGM_LO_PS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_VS',
'mmSPI_SHADER_PGM_LO_VS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC1_GS',
'mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC1_HS',
'mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC1_PS',
'mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC1_VS',
'mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC2_GS',
'mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX',
'mmSPI_SHADER_PGM_RSRC2_GS_VS',
'mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX',
'mmSPI_SHADER_PGM_RSRC2_HS', 'mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX',
'mmSPI_SHADER_PGM_RSRC2_PS', 'mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX',
'mmSPI_SHADER_PGM_RSRC2_VS', 'mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX',
'mmSPI_SHADER_PGM_RSRC3_GS', 'mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX',
'mmSPI_SHADER_PGM_RSRC3_HS', 'mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX',
'mmSPI_SHADER_PGM_RSRC3_PS', 'mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX',
'mmSPI_SHADER_PGM_RSRC3_VS', 'mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX',
'mmSPI_SHADER_PGM_RSRC4_GS', 'mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX',
'mmSPI_SHADER_PGM_RSRC4_HS', 'mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX',
'mmSPI_SHADER_PGM_RSRC4_PS', 'mmSPI_SHADER_PGM_RSRC4_PS_BASE_IDX',
'mmSPI_SHADER_PGM_RSRC4_VS', 'mmSPI_SHADER_PGM_RSRC4_VS_BASE_IDX',
'mmSPI_SHADER_POS_FORMAT', 'mmSPI_SHADER_POS_FORMAT_BASE_IDX',
'mmSPI_SHADER_REQ_CTRL_ESGS',
'mmSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX',
'mmSPI_SHADER_REQ_CTRL_LSHS',
'mmSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX', 'mmSPI_SHADER_REQ_CTRL_PS',
'mmSPI_SHADER_REQ_CTRL_PS_BASE_IDX', 'mmSPI_SHADER_REQ_CTRL_VS',
'mmSPI_SHADER_REQ_CTRL_VS_BASE_IDX',
'mmSPI_SHADER_RSRC_LIMIT_CTRL',
'mmSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_ESGS_0',
'mmSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_ESGS_1',
'mmSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_ESGS_2',
'mmSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_ESGS_3',
'mmSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_LSHS_0',
'mmSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_LSHS_1',
'mmSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_LSHS_2',
'mmSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_LSHS_3',
'mmSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_PS_0',
'mmSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_PS_1',
'mmSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_PS_2',
'mmSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_PS_3',
'mmSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_VS_0',
'mmSPI_SHADER_USER_ACCUM_VS_0_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_VS_1',
'mmSPI_SHADER_USER_ACCUM_VS_1_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_VS_2',
'mmSPI_SHADER_USER_ACCUM_VS_2_BASE_IDX',
'mmSPI_SHADER_USER_ACCUM_VS_3',
'mmSPI_SHADER_USER_ACCUM_VS_3_BASE_IDX',
'mmSPI_SHADER_USER_DATA_ADDR_HI_GS',
'mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX',
'mmSPI_SHADER_USER_DATA_ADDR_HI_HS',
'mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX',
'mmSPI_SHADER_USER_DATA_ADDR_LO_GS',
'mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX',
'mmSPI_SHADER_USER_DATA_ADDR_LO_HS',
'mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_0',
'mmSPI_SHADER_USER_DATA_GS_0_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_1', 'mmSPI_SHADER_USER_DATA_GS_10',
'mmSPI_SHADER_USER_DATA_GS_10_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_11',
'mmSPI_SHADER_USER_DATA_GS_11_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_12',
'mmSPI_SHADER_USER_DATA_GS_12_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_13',
'mmSPI_SHADER_USER_DATA_GS_13_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_14',
'mmSPI_SHADER_USER_DATA_GS_14_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_15',
'mmSPI_SHADER_USER_DATA_GS_15_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_16',
'mmSPI_SHADER_USER_DATA_GS_16_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_17',
'mmSPI_SHADER_USER_DATA_GS_17_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_18',
'mmSPI_SHADER_USER_DATA_GS_18_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_19',
'mmSPI_SHADER_USER_DATA_GS_19_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_1_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_2', 'mmSPI_SHADER_USER_DATA_GS_20',
'mmSPI_SHADER_USER_DATA_GS_20_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_21',
'mmSPI_SHADER_USER_DATA_GS_21_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_22',
'mmSPI_SHADER_USER_DATA_GS_22_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_23',
'mmSPI_SHADER_USER_DATA_GS_23_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_24',
'mmSPI_SHADER_USER_DATA_GS_24_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_25',
'mmSPI_SHADER_USER_DATA_GS_25_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_26',
'mmSPI_SHADER_USER_DATA_GS_26_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_27',
'mmSPI_SHADER_USER_DATA_GS_27_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_28',
'mmSPI_SHADER_USER_DATA_GS_28_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_29',
'mmSPI_SHADER_USER_DATA_GS_29_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_2_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_3', 'mmSPI_SHADER_USER_DATA_GS_30',
'mmSPI_SHADER_USER_DATA_GS_30_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_31',
'mmSPI_SHADER_USER_DATA_GS_31_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_3_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_4',
'mmSPI_SHADER_USER_DATA_GS_4_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_5',
'mmSPI_SHADER_USER_DATA_GS_5_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_6',
'mmSPI_SHADER_USER_DATA_GS_6_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_7',
'mmSPI_SHADER_USER_DATA_GS_7_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_8',
'mmSPI_SHADER_USER_DATA_GS_8_BASE_IDX',
'mmSPI_SHADER_USER_DATA_GS_9',
'mmSPI_SHADER_USER_DATA_GS_9_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_0',
'mmSPI_SHADER_USER_DATA_HS_0_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_1', 'mmSPI_SHADER_USER_DATA_HS_10',
'mmSPI_SHADER_USER_DATA_HS_10_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_11',
'mmSPI_SHADER_USER_DATA_HS_11_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_12',
'mmSPI_SHADER_USER_DATA_HS_12_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_13',
'mmSPI_SHADER_USER_DATA_HS_13_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_14',
'mmSPI_SHADER_USER_DATA_HS_14_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_15',
'mmSPI_SHADER_USER_DATA_HS_15_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_16',
'mmSPI_SHADER_USER_DATA_HS_16_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_17',
'mmSPI_SHADER_USER_DATA_HS_17_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_18',
'mmSPI_SHADER_USER_DATA_HS_18_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_19',
'mmSPI_SHADER_USER_DATA_HS_19_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_1_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_2', 'mmSPI_SHADER_USER_DATA_HS_20',
'mmSPI_SHADER_USER_DATA_HS_20_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_21',
'mmSPI_SHADER_USER_DATA_HS_21_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_22',
'mmSPI_SHADER_USER_DATA_HS_22_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_23',
'mmSPI_SHADER_USER_DATA_HS_23_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_24',
'mmSPI_SHADER_USER_DATA_HS_24_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_25',
'mmSPI_SHADER_USER_DATA_HS_25_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_26',
'mmSPI_SHADER_USER_DATA_HS_26_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_27',
'mmSPI_SHADER_USER_DATA_HS_27_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_28',
'mmSPI_SHADER_USER_DATA_HS_28_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_29',
'mmSPI_SHADER_USER_DATA_HS_29_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_2_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_3', 'mmSPI_SHADER_USER_DATA_HS_30',
'mmSPI_SHADER_USER_DATA_HS_30_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_31',
'mmSPI_SHADER_USER_DATA_HS_31_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_3_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_4',
'mmSPI_SHADER_USER_DATA_HS_4_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_5',
'mmSPI_SHADER_USER_DATA_HS_5_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_6',
'mmSPI_SHADER_USER_DATA_HS_6_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_7',
'mmSPI_SHADER_USER_DATA_HS_7_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_8',
'mmSPI_SHADER_USER_DATA_HS_8_BASE_IDX',
'mmSPI_SHADER_USER_DATA_HS_9',
'mmSPI_SHADER_USER_DATA_HS_9_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_0',
'mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_1', 'mmSPI_SHADER_USER_DATA_PS_10',
'mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_11',
'mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_12',
'mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_13',
'mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_14',
'mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_15',
'mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_16',
'mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_17',
'mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_18',
'mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_19',
'mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_2', 'mmSPI_SHADER_USER_DATA_PS_20',
'mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_21',
'mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_22',
'mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_23',
'mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_24',
'mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_25',
'mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_26',
'mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_27',
'mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_28',
'mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_29',
'mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_3', 'mmSPI_SHADER_USER_DATA_PS_30',
'mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_31',
'mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_4',
'mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_5',
'mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_6',
'mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_7',
'mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_8',
'mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX',
'mmSPI_SHADER_USER_DATA_PS_9',
'mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_0',
'mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_1', 'mmSPI_SHADER_USER_DATA_VS_10',
'mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_11',
'mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_12',
'mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_13',
'mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_14',
'mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_15',
'mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_16',
'mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_17',
'mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_18',
'mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_19',
'mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_2', 'mmSPI_SHADER_USER_DATA_VS_20',
'mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_21',
'mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_22',
'mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_23',
'mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_24',
'mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_25',
'mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_26',
'mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_27',
'mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_28',
'mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_29',
'mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_3', 'mmSPI_SHADER_USER_DATA_VS_30',
'mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_31',
'mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_4',
'mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_5',
'mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_6',
'mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_7',
'mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_8',
'mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX',
'mmSPI_SHADER_USER_DATA_VS_9',
'mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX', 'mmSPI_SHADER_Z_FORMAT',
'mmSPI_SHADER_Z_FORMAT_BASE_IDX', 'mmSPI_START_PHASE',
'mmSPI_START_PHASE_BASE_IDX', 'mmSPI_SX_EXPORT_BUFFER_SIZES',
'mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX',
'mmSPI_SX_SCOREBOARD_BUFFER_SIZES',
'mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX', 'mmSPI_TMPRING_SIZE',
'mmSPI_TMPRING_SIZE_BASE_IDX', 'mmSPI_USER_ACCUM_VMID_CNTL',
'mmSPI_USER_ACCUM_VMID_CNTL_BASE_IDX', 'mmSPI_VS_OUT_CONFIG',
'mmSPI_VS_OUT_CONFIG_BASE_IDX', 'mmSPI_WAVE_LIMIT_CNTL',
'mmSPI_WAVE_LIMIT_CNTL_BASE_IDX', 'mmSPI_WAVE_LIMIT_CNTL_REMAP',
'mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX',
'mmSPI_WCL_PIPE_PERCENT_CS0',
'mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX',
'mmSPI_WCL_PIPE_PERCENT_CS1',
'mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX',
'mmSPI_WCL_PIPE_PERCENT_CS2',
'mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX',
'mmSPI_WCL_PIPE_PERCENT_CS3',
'mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX',
'mmSPI_WCL_PIPE_PERCENT_GFX',
'mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX',
'mmSPI_WCL_PIPE_PERCENT_HP3D',
'mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX', 'mmSPI_WF_LIFETIME_CNTL',
'mmSPI_WF_LIFETIME_CNTL_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_0',
'mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_1',
'mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_2',
'mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_3',
'mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_4',
'mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_5',
'mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_0',
'mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_1', 'mmSPI_WF_LIFETIME_STATUS_11',
'mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_13',
'mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_14',
'mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_15',
'mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_16',
'mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_17',
'mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_18',
'mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_19',
'mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_2', 'mmSPI_WF_LIFETIME_STATUS_20',
'mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_21',
'mmSPI_WF_LIFETIME_STATUS_21_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_4',
'mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_6',
'mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_7',
'mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_8',
'mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX',
'mmSPI_WF_LIFETIME_STATUS_9',
'mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX', 'mmSP_CONFIG',
'mmSP_CONFIG_BASE_IDX', 'mmSQC_CACHES', 'mmSQC_CACHES_BASE_IDX',
'mmSQC_CONFIG', 'mmSQC_CONFIG_BASE_IDX',
'mmSQC_DCACHE_UTCL0_CNTL1', 'mmSQC_DCACHE_UTCL0_CNTL1_BASE_IDX',
'mmSQC_DCACHE_UTCL0_CNTL2', 'mmSQC_DCACHE_UTCL0_CNTL2_BASE_IDX',
'mmSQC_DCACHE_UTCL0_STATUS', 'mmSQC_DCACHE_UTCL0_STATUS_BASE_IDX',
'mmSQC_ICACHE_UTCL0_CNTL1', 'mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX',
'mmSQC_ICACHE_UTCL0_CNTL2', 'mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX',
'mmSQC_ICACHE_UTCL0_STATUS', 'mmSQC_ICACHE_UTCL0_STATUS_BASE_IDX',
'mmSQG_CONFIG', 'mmSQG_CONFIG_BASE_IDX', 'mmSQG_STATUS',
'mmSQG_STATUS_BASE_IDX', 'mmSQG_UTCL0_CNTL1',
'mmSQG_UTCL0_CNTL1_BASE_IDX', 'mmSQG_UTCL0_CNTL2',
'mmSQG_UTCL0_CNTL2_BASE_IDX', 'mmSQG_UTCL0_STATUS',
'mmSQG_UTCL0_STATUS_BASE_IDX', 'mmSQ_ALU_CLK_CTRL',
'mmSQ_ALU_CLK_CTRL_BASE_IDX', 'mmSQ_ARB_CONFIG',
'mmSQ_ARB_CONFIG_BASE_IDX', 'mmSQ_CMD', 'mmSQ_CMD_BASE_IDX',
'mmSQ_CONFIG', 'mmSQ_CONFIG_BASE_IDX', 'mmSQ_DEBUG',
'mmSQ_DEBUG_BASE_IDX', 'mmSQ_DEBUG_STS_GLOBAL',
'mmSQ_DEBUG_STS_GLOBAL2', 'mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX',
'mmSQ_DEBUG_STS_GLOBAL_BASE_IDX', 'mmSQ_DSM_CNTL',
'mmSQ_DSM_CNTL2', 'mmSQ_DSM_CNTL2_BASE_IDX',
'mmSQ_DSM_CNTL_BASE_IDX', 'mmSQ_EDC_CNT', 'mmSQ_EDC_CNT_BASE_IDX',
'mmSQ_EDC_FUE_CNTL', 'mmSQ_EDC_FUE_CNTL_BASE_IDX',
'mmSQ_FIFO_SIZES', 'mmSQ_FIFO_SIZES_BASE_IDX', 'mmSQ_IND_DATA',
'mmSQ_IND_DATA_BASE_IDX', 'mmSQ_IND_INDEX',
'mmSQ_IND_INDEX_BASE_IDX', 'mmSQ_INTERRUPT_AUTO_MASK',
'mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX', 'mmSQ_INTERRUPT_MSG_CTRL',
'mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX', 'mmSQ_LB_CTR_CTRL',
'mmSQ_LB_CTR_CTRL_BASE_IDX', 'mmSQ_LB_CTR_SEL0',
'mmSQ_LB_CTR_SEL0_BASE_IDX', 'mmSQ_LB_CTR_SEL1',
'mmSQ_LB_CTR_SEL1_BASE_IDX', 'mmSQ_LB_DATA0',
'mmSQ_LB_DATA0_BASE_IDX', 'mmSQ_LB_DATA1',
'mmSQ_LB_DATA1_BASE_IDX', 'mmSQ_LB_DATA2',
'mmSQ_LB_DATA2_BASE_IDX', 'mmSQ_LB_DATA3',
'mmSQ_LB_DATA3_BASE_IDX', 'mmSQ_LDS_CLK_CTRL',
'mmSQ_LDS_CLK_CTRL_BASE_IDX', 'mmSQ_PERFCOUNTER0_HI',
'mmSQ_PERFCOUNTER0_HI_BASE_IDX', 'mmSQ_PERFCOUNTER0_LO',
'mmSQ_PERFCOUNTER0_LO_BASE_IDX', 'mmSQ_PERFCOUNTER0_SELECT',
'mmSQ_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER10_HI',
'mmSQ_PERFCOUNTER10_HI_BASE_IDX', 'mmSQ_PERFCOUNTER10_LO',
'mmSQ_PERFCOUNTER10_LO_BASE_IDX', 'mmSQ_PERFCOUNTER10_SELECT',
'mmSQ_PERFCOUNTER10_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER11_HI',
'mmSQ_PERFCOUNTER11_HI_BASE_IDX', 'mmSQ_PERFCOUNTER11_LO',
'mmSQ_PERFCOUNTER11_LO_BASE_IDX', 'mmSQ_PERFCOUNTER11_SELECT',
'mmSQ_PERFCOUNTER11_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER12_HI',
'mmSQ_PERFCOUNTER12_HI_BASE_IDX', 'mmSQ_PERFCOUNTER12_LO',
'mmSQ_PERFCOUNTER12_LO_BASE_IDX', 'mmSQ_PERFCOUNTER12_SELECT',
'mmSQ_PERFCOUNTER12_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER13_HI',
'mmSQ_PERFCOUNTER13_HI_BASE_IDX', 'mmSQ_PERFCOUNTER13_LO',
'mmSQ_PERFCOUNTER13_LO_BASE_IDX', 'mmSQ_PERFCOUNTER13_SELECT',
'mmSQ_PERFCOUNTER13_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER14_HI',
'mmSQ_PERFCOUNTER14_HI_BASE_IDX', 'mmSQ_PERFCOUNTER14_LO',
'mmSQ_PERFCOUNTER14_LO_BASE_IDX', 'mmSQ_PERFCOUNTER14_SELECT',
'mmSQ_PERFCOUNTER14_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER15_HI',
'mmSQ_PERFCOUNTER15_HI_BASE_IDX', 'mmSQ_PERFCOUNTER15_LO',
'mmSQ_PERFCOUNTER15_LO_BASE_IDX', 'mmSQ_PERFCOUNTER15_SELECT',
'mmSQ_PERFCOUNTER15_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER1_HI',
'mmSQ_PERFCOUNTER1_HI_BASE_IDX', 'mmSQ_PERFCOUNTER1_LO',
'mmSQ_PERFCOUNTER1_LO_BASE_IDX', 'mmSQ_PERFCOUNTER1_SELECT',
'mmSQ_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER2_HI',
'mmSQ_PERFCOUNTER2_HI_BASE_IDX', 'mmSQ_PERFCOUNTER2_LO',
'mmSQ_PERFCOUNTER2_LO_BASE_IDX', 'mmSQ_PERFCOUNTER2_SELECT',
'mmSQ_PERFCOUNTER2_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER3_HI',
'mmSQ_PERFCOUNTER3_HI_BASE_IDX', 'mmSQ_PERFCOUNTER3_LO',
'mmSQ_PERFCOUNTER3_LO_BASE_IDX', 'mmSQ_PERFCOUNTER3_SELECT',
'mmSQ_PERFCOUNTER3_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER4_HI',
'mmSQ_PERFCOUNTER4_HI_BASE_IDX', 'mmSQ_PERFCOUNTER4_LO',
'mmSQ_PERFCOUNTER4_LO_BASE_IDX', 'mmSQ_PERFCOUNTER4_SELECT',
'mmSQ_PERFCOUNTER4_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER5_HI',
'mmSQ_PERFCOUNTER5_HI_BASE_IDX', 'mmSQ_PERFCOUNTER5_LO',
'mmSQ_PERFCOUNTER5_LO_BASE_IDX', 'mmSQ_PERFCOUNTER5_SELECT',
'mmSQ_PERFCOUNTER5_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER6_HI',
'mmSQ_PERFCOUNTER6_HI_BASE_IDX', 'mmSQ_PERFCOUNTER6_LO',
'mmSQ_PERFCOUNTER6_LO_BASE_IDX', 'mmSQ_PERFCOUNTER6_SELECT',
'mmSQ_PERFCOUNTER6_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER7_HI',
'mmSQ_PERFCOUNTER7_HI_BASE_IDX', 'mmSQ_PERFCOUNTER7_LO',
'mmSQ_PERFCOUNTER7_LO_BASE_IDX', 'mmSQ_PERFCOUNTER7_SELECT',
'mmSQ_PERFCOUNTER7_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER8_HI',
'mmSQ_PERFCOUNTER8_HI_BASE_IDX', 'mmSQ_PERFCOUNTER8_LO',
'mmSQ_PERFCOUNTER8_LO_BASE_IDX', 'mmSQ_PERFCOUNTER8_SELECT',
'mmSQ_PERFCOUNTER8_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER9_HI',
'mmSQ_PERFCOUNTER9_HI_BASE_IDX', 'mmSQ_PERFCOUNTER9_LO',
'mmSQ_PERFCOUNTER9_LO_BASE_IDX', 'mmSQ_PERFCOUNTER9_SELECT',
'mmSQ_PERFCOUNTER9_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER_CTRL',
'mmSQ_PERFCOUNTER_CTRL2', 'mmSQ_PERFCOUNTER_CTRL2_BASE_IDX',
'mmSQ_PERFCOUNTER_CTRL_BASE_IDX', 'mmSQ_RANDOM_WAVE_PRI',
'mmSQ_RANDOM_WAVE_PRI_BASE_IDX', 'mmSQ_RUNTIME_CONFIG',
'mmSQ_RUNTIME_CONFIG_BASE_IDX', 'mmSQ_SHADER_TBA_HI',
'mmSQ_SHADER_TBA_HI_BASE_IDX', 'mmSQ_SHADER_TBA_LO',
'mmSQ_SHADER_TBA_LO_BASE_IDX', 'mmSQ_SHADER_TMA_HI',
'mmSQ_SHADER_TMA_HI_BASE_IDX', 'mmSQ_SHADER_TMA_LO',
'mmSQ_SHADER_TMA_LO_BASE_IDX', 'mmSQ_TEX_CLK_CTRL',
'mmSQ_TEX_CLK_CTRL_BASE_IDX', 'mmSQ_THREAD_TRACE_BUF0_BASE',
'mmSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX',
'mmSQ_THREAD_TRACE_BUF0_SIZE',
'mmSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX',
'mmSQ_THREAD_TRACE_BUF1_BASE',
'mmSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX',
'mmSQ_THREAD_TRACE_BUF1_SIZE',
'mmSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX', 'mmSQ_THREAD_TRACE_CTRL',
'mmSQ_THREAD_TRACE_CTRL_BASE_IDX',
'mmSQ_THREAD_TRACE_DROPPED_CNTR',
'mmSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX',
'mmSQ_THREAD_TRACE_GFX_DRAW_CNTR',
'mmSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX',
'mmSQ_THREAD_TRACE_GFX_MARKER_CNTR',
'mmSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX',
'mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR',
'mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX',
'mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR',
'mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX',
'mmSQ_THREAD_TRACE_MASK', 'mmSQ_THREAD_TRACE_MASK_BASE_IDX',
'mmSQ_THREAD_TRACE_STATUS', 'mmSQ_THREAD_TRACE_STATUS2',
'mmSQ_THREAD_TRACE_STATUS2_BASE_IDX',
'mmSQ_THREAD_TRACE_STATUS_BASE_IDX',
'mmSQ_THREAD_TRACE_TOKEN_MASK',
'mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX',
'mmSQ_THREAD_TRACE_USERDATA_0',
'mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX',
'mmSQ_THREAD_TRACE_USERDATA_1',
'mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX',
'mmSQ_THREAD_TRACE_USERDATA_2',
'mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX',
'mmSQ_THREAD_TRACE_USERDATA_3',
'mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX',
'mmSQ_THREAD_TRACE_USERDATA_4',
'mmSQ_THREAD_TRACE_USERDATA_4_BASE_IDX',
'mmSQ_THREAD_TRACE_USERDATA_5',
'mmSQ_THREAD_TRACE_USERDATA_5_BASE_IDX',
'mmSQ_THREAD_TRACE_USERDATA_6',
'mmSQ_THREAD_TRACE_USERDATA_6_BASE_IDX',
'mmSQ_THREAD_TRACE_USERDATA_7',
'mmSQ_THREAD_TRACE_USERDATA_7_BASE_IDX', 'mmSQ_THREAD_TRACE_WPTR',
'mmSQ_THREAD_TRACE_WPTR_BASE_IDX', 'mmSQ_TIME_HI',
'mmSQ_TIME_HI_BASE_IDX', 'mmSQ_TIME_LO', 'mmSQ_TIME_LO_BASE_IDX',
'mmSQ_WATCH0_ADDR_H', 'mmSQ_WATCH0_ADDR_H_BASE_IDX',
'mmSQ_WATCH0_ADDR_L', 'mmSQ_WATCH0_ADDR_L_BASE_IDX',
'mmSQ_WATCH0_CNTL', 'mmSQ_WATCH0_CNTL_BASE_IDX',
'mmSQ_WATCH1_ADDR_H', 'mmSQ_WATCH1_ADDR_H_BASE_IDX',
'mmSQ_WATCH1_ADDR_L', 'mmSQ_WATCH1_ADDR_L_BASE_IDX',
'mmSQ_WATCH1_CNTL', 'mmSQ_WATCH1_CNTL_BASE_IDX',
'mmSQ_WATCH2_ADDR_H', 'mmSQ_WATCH2_ADDR_H_BASE_IDX',
'mmSQ_WATCH2_ADDR_L', 'mmSQ_WATCH2_ADDR_L_BASE_IDX',
'mmSQ_WATCH2_CNTL', 'mmSQ_WATCH2_CNTL_BASE_IDX',
'mmSQ_WATCH3_ADDR_H', 'mmSQ_WATCH3_ADDR_H_BASE_IDX',
'mmSQ_WATCH3_ADDR_L', 'mmSQ_WATCH3_ADDR_L_BASE_IDX',
'mmSQ_WATCH3_CNTL', 'mmSQ_WATCH3_CNTL_BASE_IDX',
'mmSQ_WREXEC_EXEC_HI', 'mmSQ_WREXEC_EXEC_HI_BASE_IDX',
'mmSQ_WREXEC_EXEC_LO', 'mmSQ_WREXEC_EXEC_LO_BASE_IDX',
'mmSX_BLEND_OPT_CONTROL', 'mmSX_BLEND_OPT_CONTROL_BASE_IDX',
'mmSX_BLEND_OPT_EPSILON', 'mmSX_BLEND_OPT_EPSILON_BASE_IDX',
'mmSX_DEBUG_1', 'mmSX_DEBUG_1_BASE_IDX', 'mmSX_MRT0_BLEND_OPT',
'mmSX_MRT0_BLEND_OPT_BASE_IDX', 'mmSX_MRT1_BLEND_OPT',
'mmSX_MRT1_BLEND_OPT_BASE_IDX', 'mmSX_MRT2_BLEND_OPT',
'mmSX_MRT2_BLEND_OPT_BASE_IDX', 'mmSX_MRT3_BLEND_OPT',
'mmSX_MRT3_BLEND_OPT_BASE_IDX', 'mmSX_MRT4_BLEND_OPT',
'mmSX_MRT4_BLEND_OPT_BASE_IDX', 'mmSX_MRT5_BLEND_OPT',
'mmSX_MRT5_BLEND_OPT_BASE_IDX', 'mmSX_MRT6_BLEND_OPT',
'mmSX_MRT6_BLEND_OPT_BASE_IDX', 'mmSX_MRT7_BLEND_OPT',
'mmSX_MRT7_BLEND_OPT_BASE_IDX', 'mmSX_PERFCOUNTER0_HI',
'mmSX_PERFCOUNTER0_HI_BASE_IDX', 'mmSX_PERFCOUNTER0_LO',
'mmSX_PERFCOUNTER0_LO_BASE_IDX', 'mmSX_PERFCOUNTER0_SELECT',
'mmSX_PERFCOUNTER0_SELECT1', 'mmSX_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmSX_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSX_PERFCOUNTER1_HI',
'mmSX_PERFCOUNTER1_HI_BASE_IDX', 'mmSX_PERFCOUNTER1_LO',
'mmSX_PERFCOUNTER1_LO_BASE_IDX', 'mmSX_PERFCOUNTER1_SELECT',
'mmSX_PERFCOUNTER1_SELECT1', 'mmSX_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmSX_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSX_PERFCOUNTER2_HI',
'mmSX_PERFCOUNTER2_HI_BASE_IDX', 'mmSX_PERFCOUNTER2_LO',
'mmSX_PERFCOUNTER2_LO_BASE_IDX', 'mmSX_PERFCOUNTER2_SELECT',
'mmSX_PERFCOUNTER2_SELECT_BASE_IDX', 'mmSX_PERFCOUNTER3_HI',
'mmSX_PERFCOUNTER3_HI_BASE_IDX', 'mmSX_PERFCOUNTER3_LO',
'mmSX_PERFCOUNTER3_LO_BASE_IDX', 'mmSX_PERFCOUNTER3_SELECT',
'mmSX_PERFCOUNTER3_SELECT_BASE_IDX', 'mmSX_PS_DOWNCONVERT',
'mmSX_PS_DOWNCONVERT_BASE_IDX', 'mmSX_PS_DOWNCONVERT_CONTROL',
'mmSX_PS_DOWNCONVERT_CONTROL_BASE_IDX', 'mmTA_BC_BASE_ADDR',
'mmTA_BC_BASE_ADDR_BASE_IDX', 'mmTA_BC_BASE_ADDR_HI',
'mmTA_BC_BASE_ADDR_HI_BASE_IDX', 'mmTA_CGTT_CTRL',
'mmTA_CGTT_CTRL_BASE_IDX', 'mmTA_CNTL', 'mmTA_CNTL_BASE_IDX',
'mmTA_CS_BC_BASE_ADDR', 'mmTA_CS_BC_BASE_ADDR_BASE_IDX',
'mmTA_CS_BC_BASE_ADDR_HI', 'mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX',
'mmTA_PERFCOUNTER0_HI', 'mmTA_PERFCOUNTER0_HI_BASE_IDX',
'mmTA_PERFCOUNTER0_LO', 'mmTA_PERFCOUNTER0_LO_BASE_IDX',
'mmTA_PERFCOUNTER0_SELECT', 'mmTA_PERFCOUNTER0_SELECT1',
'mmTA_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmTA_PERFCOUNTER0_SELECT_BASE_IDX', 'mmTA_PERFCOUNTER1_HI',
'mmTA_PERFCOUNTER1_HI_BASE_IDX', 'mmTA_PERFCOUNTER1_LO',
'mmTA_PERFCOUNTER1_LO_BASE_IDX', 'mmTA_PERFCOUNTER1_SELECT',
'mmTA_PERFCOUNTER1_SELECT_BASE_IDX', 'mmTA_RESERVED_010C',
'mmTA_RESERVED_010C_BASE_IDX', 'mmTA_SCRATCH',
'mmTA_SCRATCH_BASE_IDX', 'mmTA_STATUS', 'mmTA_STATUS_BASE_IDX',
'mmTCI_CNTL_1', 'mmTCI_CNTL_1_BASE_IDX', 'mmTCI_CNTL_2',
'mmTCI_CNTL_2_BASE_IDX', 'mmTCI_STATUS', 'mmTCI_STATUS_BASE_IDX',
'mmTCP_EDC_CNT', 'mmTCP_EDC_CNT_BASE_IDX', 'mmTCP_INVALIDATE',
'mmTCP_INVALIDATE_BASE_IDX', 'mmTCP_PERFCOUNTER0_HI',
'mmTCP_PERFCOUNTER0_HI_BASE_IDX', 'mmTCP_PERFCOUNTER0_LO',
'mmTCP_PERFCOUNTER0_LO_BASE_IDX', 'mmTCP_PERFCOUNTER0_SELECT',
'mmTCP_PERFCOUNTER0_SELECT1',
'mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmTCP_PERFCOUNTER0_SELECT_BASE_IDX', 'mmTCP_PERFCOUNTER1_HI',
'mmTCP_PERFCOUNTER1_HI_BASE_IDX', 'mmTCP_PERFCOUNTER1_LO',
'mmTCP_PERFCOUNTER1_LO_BASE_IDX', 'mmTCP_PERFCOUNTER1_SELECT',
'mmTCP_PERFCOUNTER1_SELECT1',
'mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX',
'mmTCP_PERFCOUNTER1_SELECT_BASE_IDX', 'mmTCP_PERFCOUNTER2_HI',
'mmTCP_PERFCOUNTER2_HI_BASE_IDX', 'mmTCP_PERFCOUNTER2_LO',
'mmTCP_PERFCOUNTER2_LO_BASE_IDX', 'mmTCP_PERFCOUNTER2_SELECT',
'mmTCP_PERFCOUNTER2_SELECT_BASE_IDX', 'mmTCP_PERFCOUNTER3_HI',
'mmTCP_PERFCOUNTER3_HI_BASE_IDX', 'mmTCP_PERFCOUNTER3_LO',
'mmTCP_PERFCOUNTER3_LO_BASE_IDX', 'mmTCP_PERFCOUNTER3_SELECT',
'mmTCP_PERFCOUNTER3_SELECT_BASE_IDX', 'mmTCP_PERFCOUNTER_FILTER',
'mmTCP_PERFCOUNTER_FILTER2', 'mmTCP_PERFCOUNTER_FILTER2_BASE_IDX',
'mmTCP_PERFCOUNTER_FILTER_BASE_IDX',
'mmTCP_PERFCOUNTER_FILTER_EN',
'mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX', 'mmTCP_STATUS',
'mmTCP_STATUS_BASE_IDX', 'mmTCP_WATCH0_ADDR_H',
'mmTCP_WATCH0_ADDR_H_BASE_IDX', 'mmTCP_WATCH0_ADDR_L',
'mmTCP_WATCH0_ADDR_L_BASE_IDX', 'mmTCP_WATCH0_CNTL',
'mmTCP_WATCH0_CNTL_BASE_IDX', 'mmTCP_WATCH1_ADDR_H',
'mmTCP_WATCH1_ADDR_H_BASE_IDX', 'mmTCP_WATCH1_ADDR_L',
'mmTCP_WATCH1_ADDR_L_BASE_IDX', 'mmTCP_WATCH1_CNTL',
'mmTCP_WATCH1_CNTL_BASE_IDX', 'mmTCP_WATCH2_ADDR_H',
'mmTCP_WATCH2_ADDR_H_BASE_IDX', 'mmTCP_WATCH2_ADDR_L',
'mmTCP_WATCH2_ADDR_L_BASE_IDX', 'mmTCP_WATCH2_CNTL',
'mmTCP_WATCH2_CNTL_BASE_IDX', 'mmTCP_WATCH3_ADDR_H',
'mmTCP_WATCH3_ADDR_H_BASE_IDX', 'mmTCP_WATCH3_ADDR_L',
'mmTCP_WATCH3_ADDR_L_BASE_IDX', 'mmTCP_WATCH3_CNTL',
'mmTCP_WATCH3_CNTL_BASE_IDX', 'mmTD_CGTT_CTRL',
'mmTD_CGTT_CTRL_BASE_IDX', 'mmTD_DSM_CNTL', 'mmTD_DSM_CNTL2',
'mmTD_DSM_CNTL2_BASE_IDX', 'mmTD_DSM_CNTL_BASE_IDX',
'mmTD_PERFCOUNTER0_HI', 'mmTD_PERFCOUNTER0_HI_BASE_IDX',
'mmTD_PERFCOUNTER0_LO', 'mmTD_PERFCOUNTER0_LO_BASE_IDX',
'mmTD_PERFCOUNTER0_SELECT', 'mmTD_PERFCOUNTER0_SELECT1',
'mmTD_PERFCOUNTER0_SELECT1_BASE_IDX',
'mmTD_PERFCOUNTER0_SELECT_BASE_IDX', 'mmTD_PERFCOUNTER1_HI',
'mmTD_PERFCOUNTER1_HI_BASE_IDX', 'mmTD_PERFCOUNTER1_LO',
'mmTD_PERFCOUNTER1_LO_BASE_IDX', 'mmTD_PERFCOUNTER1_SELECT',
'mmTD_PERFCOUNTER1_SELECT_BASE_IDX', 'mmTD_SCRATCH',
'mmTD_SCRATCH_BASE_IDX', 'mmTD_STATUS', 'mmTD_STATUS_BASE_IDX',
'mmUCONFIG_RESERVED_REG0', 'mmUCONFIG_RESERVED_REG0_BASE_IDX',
'mmUCONFIG_RESERVED_REG1', 'mmUCONFIG_RESERVED_REG1_BASE_IDX',
'mmUTCL1_ALOG', 'mmUTCL1_ALOG_BASE_IDX', 'mmUTCL1_CGTT_CLK_CTRL',
'mmUTCL1_CGTT_CLK_CTRL_BASE_IDX', 'mmUTCL1_CTRL',
'mmUTCL1_CTRL_BASE_IDX', 'mmUTCL1_PERFCOUNTER0_HI',
'mmUTCL1_PERFCOUNTER0_HI_BASE_IDX', 'mmUTCL1_PERFCOUNTER0_LO',
'mmUTCL1_PERFCOUNTER0_LO_BASE_IDX', 'mmUTCL1_PERFCOUNTER0_SELECT',
'mmUTCL1_PERFCOUNTER0_SELECT_BASE_IDX', 'mmUTCL1_PERFCOUNTER1_HI',
'mmUTCL1_PERFCOUNTER1_HI_BASE_IDX', 'mmUTCL1_PERFCOUNTER1_LO',
'mmUTCL1_PERFCOUNTER1_LO_BASE_IDX', 'mmUTCL1_PERFCOUNTER1_SELECT',
'mmUTCL1_PERFCOUNTER1_SELECT_BASE_IDX', 'mmUTCL1_STATUS',
'mmUTCL1_STATUS_BASE_IDX', 'mmUTCL1_UTCL0_INVREQ_DISABLE',
'mmUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX',
'mmVGT_CACHE_INVALIDATION', 'mmVGT_CACHE_INVALIDATION_BASE_IDX',
'mmVGT_DISPATCH_DRAW_INDEX', 'mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX',
'mmVGT_DMA_BASE', 'mmVGT_DMA_BASE_BASE_IDX', 'mmVGT_DMA_BASE_HI',
'mmVGT_DMA_BASE_HI_BASE_IDX', 'mmVGT_DMA_CONTROL',
'mmVGT_DMA_CONTROL_BASE_IDX', 'mmVGT_DMA_DATA_FIFO_DEPTH',
'mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX', 'mmVGT_DMA_EVENT_INITIATOR',
'mmVGT_DMA_EVENT_INITIATOR_BASE_IDX', 'mmVGT_DMA_INDEX_TYPE',
'mmVGT_DMA_INDEX_TYPE_BASE_IDX', 'mmVGT_DMA_LS_HS_CONFIG',
'mmVGT_DMA_LS_HS_CONFIG_BASE_IDX', 'mmVGT_DMA_MAX_SIZE',
'mmVGT_DMA_MAX_SIZE_BASE_IDX', 'mmVGT_DMA_NUM_INSTANCES',
'mmVGT_DMA_NUM_INSTANCES_BASE_IDX', 'mmVGT_DMA_PRIMITIVE_TYPE',
'mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX', 'mmVGT_DMA_REQ_FIFO_DEPTH',
'mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX', 'mmVGT_DMA_SIZE',
'mmVGT_DMA_SIZE_BASE_IDX', 'mmVGT_DRAW_INITIATOR',
'mmVGT_DRAW_INITIATOR_BASE_IDX', 'mmVGT_DRAW_INIT_FIFO_DEPTH',
'mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX', 'mmVGT_DRAW_PAYLOAD_CNTL',
'mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX', 'mmVGT_ENHANCE',
'mmVGT_ENHANCE_BASE_IDX', 'mmVGT_ESGS_RING_ITEMSIZE',
'mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX', 'mmVGT_ESGS_RING_SIZE',
'mmVGT_ESGS_RING_SIZE_BASE_IDX', 'mmVGT_ESGS_RING_SIZE_UMD',
'mmVGT_ESGS_RING_SIZE_UMD_BASE_IDX', 'mmVGT_ES_PER_GS',
'mmVGT_ES_PER_GS_BASE_IDX', 'mmVGT_EVENT_ADDRESS_REG',
'mmVGT_EVENT_ADDRESS_REG_BASE_IDX', 'mmVGT_EVENT_INITIATOR',
'mmVGT_EVENT_INITIATOR_BASE_IDX', 'mmVGT_FIFO_DEPTHS',
'mmVGT_FIFO_DEPTHS_BASE_IDX', 'mmVGT_GROUP_DECR',
'mmVGT_GROUP_DECR_BASE_IDX', 'mmVGT_GROUP_FIRST_DECR',
'mmVGT_GROUP_FIRST_DECR_BASE_IDX', 'mmVGT_GROUP_PRIM_TYPE',
'mmVGT_GROUP_PRIM_TYPE_BASE_IDX', 'mmVGT_GROUP_VECT_0_CNTL',
'mmVGT_GROUP_VECT_0_CNTL_BASE_IDX', 'mmVGT_GROUP_VECT_0_FMT_CNTL',
'mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX', 'mmVGT_GROUP_VECT_1_CNTL',
'mmVGT_GROUP_VECT_1_CNTL_BASE_IDX', 'mmVGT_GROUP_VECT_1_FMT_CNTL',
'mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX',
'mmVGT_GSVS_RING_ITEMSIZE', 'mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX',
'mmVGT_GSVS_RING_OFFSET_1', 'mmVGT_GSVS_RING_OFFSET_1_BASE_IDX',
'mmVGT_GSVS_RING_OFFSET_2', 'mmVGT_GSVS_RING_OFFSET_2_BASE_IDX',
'mmVGT_GSVS_RING_OFFSET_3', 'mmVGT_GSVS_RING_OFFSET_3_BASE_IDX',
'mmVGT_GSVS_RING_SIZE', 'mmVGT_GSVS_RING_SIZE_BASE_IDX',
'mmVGT_GSVS_RING_SIZE_UMD', 'mmVGT_GSVS_RING_SIZE_UMD_BASE_IDX',
'mmVGT_GS_INSTANCE_CNT', 'mmVGT_GS_INSTANCE_CNT_BASE_IDX',
'mmVGT_GS_MAX_VERT_OUT', 'mmVGT_GS_MAX_VERT_OUT_BASE_IDX',
'mmVGT_GS_MAX_WAVE_ID', 'mmVGT_GS_MAX_WAVE_ID_BASE_IDX',
'mmVGT_GS_MODE', 'mmVGT_GS_MODE_BASE_IDX', 'mmVGT_GS_ONCHIP_CNTL',
'mmVGT_GS_ONCHIP_CNTL_BASE_IDX', 'mmVGT_GS_OUT_PRIM_TYPE',
'mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX', 'mmVGT_GS_PER_ES',
'mmVGT_GS_PER_ES_BASE_IDX', 'mmVGT_GS_PER_VS',
'mmVGT_GS_PER_VS_BASE_IDX', 'mmVGT_GS_VERTEX_REUSE',
'mmVGT_GS_VERTEX_REUSE_BASE_IDX', 'mmVGT_GS_VERT_ITEMSIZE',
'mmVGT_GS_VERT_ITEMSIZE_1', 'mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX',
'mmVGT_GS_VERT_ITEMSIZE_2', 'mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX',
'mmVGT_GS_VERT_ITEMSIZE_3', 'mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX',
'mmVGT_GS_VERT_ITEMSIZE_BASE_IDX', 'mmVGT_HOS_CNTL',
'mmVGT_HOS_CNTL_BASE_IDX', 'mmVGT_HOS_MAX_TESS_LEVEL',
'mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX', 'mmVGT_HOS_MIN_TESS_LEVEL',
'mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX', 'mmVGT_HOS_REUSE_DEPTH',
'mmVGT_HOS_REUSE_DEPTH_BASE_IDX', 'mmVGT_HS_OFFCHIP_PARAM',
'mmVGT_HS_OFFCHIP_PARAM_BASE_IDX', 'mmVGT_HS_OFFCHIP_PARAM_UMD',
'mmVGT_HS_OFFCHIP_PARAM_UMD_BASE_IDX', 'mmVGT_IMMED_DATA',
'mmVGT_IMMED_DATA_BASE_IDX', 'mmVGT_INDEX_TYPE',
'mmVGT_INDEX_TYPE_BASE_IDX', 'mmVGT_INDX_OFFSET',
'mmVGT_INDX_OFFSET_BASE_IDX', 'mmVGT_INSTANCE_BASE_ID',
'mmVGT_INSTANCE_BASE_ID_BASE_IDX', 'mmVGT_INSTANCE_STEP_RATE_0',
'mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX',
'mmVGT_INSTANCE_STEP_RATE_1',
'mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX', 'mmVGT_LAST_COPY_STATE',
'mmVGT_LAST_COPY_STATE_BASE_IDX', 'mmVGT_LS_HS_CONFIG',
'mmVGT_LS_HS_CONFIG_BASE_IDX', 'mmVGT_MAX_VTX_INDX',
'mmVGT_MAX_VTX_INDX_BASE_IDX', 'mmVGT_MC_LAT_CNTL',
'mmVGT_MC_LAT_CNTL_BASE_IDX', 'mmVGT_MIN_VTX_INDX',
'mmVGT_MIN_VTX_INDX_BASE_IDX', 'mmVGT_MULTI_PRIM_IB_RESET_EN',
'mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX',
'mmVGT_MULTI_PRIM_IB_RESET_INDX',
'mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX', 'mmVGT_NUM_INDICES',
'mmVGT_NUM_INDICES_BASE_IDX', 'mmVGT_NUM_INSTANCES',
'mmVGT_NUM_INSTANCES_BASE_IDX', 'mmVGT_OUTPUT_PATH_CNTL',
'mmVGT_OUTPUT_PATH_CNTL_BASE_IDX', 'mmVGT_OUT_DEALLOC_CNTL',
'mmVGT_OUT_DEALLOC_CNTL_BASE_IDX', 'mmVGT_PRIMITIVEID_EN',
'mmVGT_PRIMITIVEID_EN_BASE_IDX', 'mmVGT_PRIMITIVEID_RESET',
'mmVGT_PRIMITIVEID_RESET_BASE_IDX', 'mmVGT_PRIMITIVE_TYPE',
'mmVGT_PRIMITIVE_TYPE_BASE_IDX', 'mmVGT_REUSE_OFF',
'mmVGT_REUSE_OFF_BASE_IDX', 'mmVGT_SHADER_STAGES_EN',
'mmVGT_SHADER_STAGES_EN_BASE_IDX', 'mmVGT_STRMOUT_BUFFER_CONFIG',
'mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX',
'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0',
'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX',
'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1',
'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX',
'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2',
'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX',
'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3',
'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX',
'mmVGT_STRMOUT_BUFFER_OFFSET_0',
'mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX',
'mmVGT_STRMOUT_BUFFER_OFFSET_1',
'mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX',
'mmVGT_STRMOUT_BUFFER_OFFSET_2',
'mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX',
'mmVGT_STRMOUT_BUFFER_OFFSET_3',
'mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX',
'mmVGT_STRMOUT_BUFFER_SIZE_0',
'mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX',
'mmVGT_STRMOUT_BUFFER_SIZE_1',
'mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX',
'mmVGT_STRMOUT_BUFFER_SIZE_2',
'mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX',
'mmVGT_STRMOUT_BUFFER_SIZE_3',
'mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX', 'mmVGT_STRMOUT_CONFIG',
'mmVGT_STRMOUT_CONFIG_BASE_IDX', 'mmVGT_STRMOUT_DELAY',
'mmVGT_STRMOUT_DELAY_BASE_IDX',
'mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE',
'mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX',
'mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET',
'mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX',
'mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE',
'mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX',
'mmVGT_STRMOUT_VTX_STRIDE_0',
'mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX',
'mmVGT_STRMOUT_VTX_STRIDE_1',
'mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX',
'mmVGT_STRMOUT_VTX_STRIDE_2',
'mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX',
'mmVGT_STRMOUT_VTX_STRIDE_3',
'mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX', 'mmVGT_SYS_CONFIG',
'mmVGT_SYS_CONFIG_BASE_IDX', 'mmVGT_TESS_DISTRIBUTION',
'mmVGT_TESS_DISTRIBUTION_BASE_IDX', 'mmVGT_TF_MEMORY_BASE',
'mmVGT_TF_MEMORY_BASE_BASE_IDX', 'mmVGT_TF_MEMORY_BASE_HI',
'mmVGT_TF_MEMORY_BASE_HI_BASE_IDX', 'mmVGT_TF_MEMORY_BASE_HI_UMD',
'mmVGT_TF_MEMORY_BASE_HI_UMD_BASE_IDX',
'mmVGT_TF_MEMORY_BASE_UMD', 'mmVGT_TF_MEMORY_BASE_UMD_BASE_IDX',
'mmVGT_TF_PARAM', 'mmVGT_TF_PARAM_BASE_IDX', 'mmVGT_TF_RING_SIZE',
'mmVGT_TF_RING_SIZE_BASE_IDX', 'mmVGT_TF_RING_SIZE_UMD',
'mmVGT_TF_RING_SIZE_UMD_BASE_IDX',
'mmVGT_VERTEX_REUSE_BLOCK_CNTL',
'mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX', 'mmVGT_VS_MAX_WAVE_ID',
'mmVGT_VS_MAX_WAVE_ID_BASE_IDX', 'mmVGT_VTX_CNT_EN',
'mmVGT_VTX_CNT_EN_BASE_IDX', 'mmVGT_VTX_VECT_EJECT_REG',
'mmVGT_VTX_VECT_EJECT_REG_BASE_IDX',
'mmVIOLATION_DATA_ASYNC_VF_PROG',
'mmVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX', 'mmWD_BUF_RESOURCE_1',
'mmWD_BUF_RESOURCE_1_BASE_IDX', 'mmWD_BUF_RESOURCE_2',
'mmWD_BUF_RESOURCE_2_BASE_IDX', 'mmWD_CNTL_SB_BUF_BASE',
'mmWD_CNTL_SB_BUF_BASE_BASE_IDX', 'mmWD_CNTL_SB_BUF_BASE_HI',
'mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX', 'mmWD_CNTL_STATUS',
'mmWD_CNTL_STATUS_BASE_IDX', 'mmWD_ENHANCE',
'mmWD_ENHANCE_BASE_IDX', 'mmWD_INDEX_BUF_BASE',
'mmWD_INDEX_BUF_BASE_BASE_IDX', 'mmWD_INDEX_BUF_BASE_HI',
'mmWD_INDEX_BUF_BASE_HI_BASE_IDX', 'mmWD_POS_BUF_BASE',
'mmWD_POS_BUF_BASE_BASE_IDX', 'mmWD_POS_BUF_BASE_HI',
'mmWD_POS_BUF_BASE_HI_BASE_IDX', 'mmWD_QOS', 'mmWD_QOS_BASE_IDX',
'mmWD_UTCL1_CNTL', 'mmWD_UTCL1_CNTL_BASE_IDX',
'mmWD_UTCL1_STATUS', 'mmWD_UTCL1_STATUS_BASE_IDX',
'pq_exe_status__mec_release_mem__default',
'pq_exe_status__mec_release_mem__phase_update',
'regCB_BLEND0_CONTROL', 'regCB_BLEND0_CONTROL_BASE_IDX',
'regCB_BLEND1_CONTROL', 'regCB_BLEND1_CONTROL_BASE_IDX',
'regCB_BLEND2_CONTROL', 'regCB_BLEND2_CONTROL_BASE_IDX',
'regCB_BLEND3_CONTROL', 'regCB_BLEND3_CONTROL_BASE_IDX',
'regCB_BLEND4_CONTROL', 'regCB_BLEND4_CONTROL_BASE_IDX',
'regCB_BLEND5_CONTROL', 'regCB_BLEND5_CONTROL_BASE_IDX',
'regCB_BLEND6_CONTROL', 'regCB_BLEND6_CONTROL_BASE_IDX',
'regCB_BLEND7_CONTROL', 'regCB_BLEND7_CONTROL_BASE_IDX',
'regCB_BLEND_ALPHA', 'regCB_BLEND_ALPHA_BASE_IDX',
'regCB_BLEND_BLUE', 'regCB_BLEND_BLUE_BASE_IDX',
'regCB_BLEND_GREEN', 'regCB_BLEND_GREEN_BASE_IDX',
'regCB_BLEND_RED', 'regCB_BLEND_RED_BASE_IDX',
'regCB_CACHE_EVICT_POINTS', 'regCB_CACHE_EVICT_POINTS_BASE_IDX',
'regCB_CGTT_SCLK_CTRL', 'regCB_CGTT_SCLK_CTRL_BASE_IDX',
'regCB_COLOR0_ATTRIB', 'regCB_COLOR0_ATTRIB2',
'regCB_COLOR0_ATTRIB2_BASE_IDX', 'regCB_COLOR0_ATTRIB3',
'regCB_COLOR0_ATTRIB3_BASE_IDX', 'regCB_COLOR0_ATTRIB_BASE_IDX',
'regCB_COLOR0_BASE', 'regCB_COLOR0_BASE_BASE_IDX',
'regCB_COLOR0_BASE_EXT', 'regCB_COLOR0_BASE_EXT_BASE_IDX',
'regCB_COLOR0_DCC_BASE', 'regCB_COLOR0_DCC_BASE_BASE_IDX',
'regCB_COLOR0_DCC_BASE_EXT', 'regCB_COLOR0_DCC_BASE_EXT_BASE_IDX',
'regCB_COLOR0_FDCC_CONTROL', 'regCB_COLOR0_FDCC_CONTROL_BASE_IDX',
'regCB_COLOR0_INFO', 'regCB_COLOR0_INFO_BASE_IDX',
'regCB_COLOR0_VIEW', 'regCB_COLOR0_VIEW_BASE_IDX',
'regCB_COLOR1_ATTRIB', 'regCB_COLOR1_ATTRIB2',
'regCB_COLOR1_ATTRIB2_BASE_IDX', 'regCB_COLOR1_ATTRIB3',
'regCB_COLOR1_ATTRIB3_BASE_IDX', 'regCB_COLOR1_ATTRIB_BASE_IDX',
'regCB_COLOR1_BASE', 'regCB_COLOR1_BASE_BASE_IDX',
'regCB_COLOR1_BASE_EXT', 'regCB_COLOR1_BASE_EXT_BASE_IDX',
'regCB_COLOR1_DCC_BASE', 'regCB_COLOR1_DCC_BASE_BASE_IDX',
'regCB_COLOR1_DCC_BASE_EXT', 'regCB_COLOR1_DCC_BASE_EXT_BASE_IDX',
'regCB_COLOR1_FDCC_CONTROL', 'regCB_COLOR1_FDCC_CONTROL_BASE_IDX',
'regCB_COLOR1_INFO', 'regCB_COLOR1_INFO_BASE_IDX',
'regCB_COLOR1_VIEW', 'regCB_COLOR1_VIEW_BASE_IDX',
'regCB_COLOR2_ATTRIB', 'regCB_COLOR2_ATTRIB2',
'regCB_COLOR2_ATTRIB2_BASE_IDX', 'regCB_COLOR2_ATTRIB3',
'regCB_COLOR2_ATTRIB3_BASE_IDX', 'regCB_COLOR2_ATTRIB_BASE_IDX',
'regCB_COLOR2_BASE', 'regCB_COLOR2_BASE_BASE_IDX',
'regCB_COLOR2_BASE_EXT', 'regCB_COLOR2_BASE_EXT_BASE_IDX',
'regCB_COLOR2_DCC_BASE', 'regCB_COLOR2_DCC_BASE_BASE_IDX',
'regCB_COLOR2_DCC_BASE_EXT', 'regCB_COLOR2_DCC_BASE_EXT_BASE_IDX',
'regCB_COLOR2_FDCC_CONTROL', 'regCB_COLOR2_FDCC_CONTROL_BASE_IDX',
'regCB_COLOR2_INFO', 'regCB_COLOR2_INFO_BASE_IDX',
'regCB_COLOR2_VIEW', 'regCB_COLOR2_VIEW_BASE_IDX',
'regCB_COLOR3_ATTRIB', 'regCB_COLOR3_ATTRIB2',
'regCB_COLOR3_ATTRIB2_BASE_IDX', 'regCB_COLOR3_ATTRIB3',
'regCB_COLOR3_ATTRIB3_BASE_IDX', 'regCB_COLOR3_ATTRIB_BASE_IDX',
'regCB_COLOR3_BASE', 'regCB_COLOR3_BASE_BASE_IDX',
'regCB_COLOR3_BASE_EXT', 'regCB_COLOR3_BASE_EXT_BASE_IDX',
'regCB_COLOR3_DCC_BASE', 'regCB_COLOR3_DCC_BASE_BASE_IDX',
'regCB_COLOR3_DCC_BASE_EXT', 'regCB_COLOR3_DCC_BASE_EXT_BASE_IDX',
'regCB_COLOR3_FDCC_CONTROL', 'regCB_COLOR3_FDCC_CONTROL_BASE_IDX',
'regCB_COLOR3_INFO', 'regCB_COLOR3_INFO_BASE_IDX',
'regCB_COLOR3_VIEW', 'regCB_COLOR3_VIEW_BASE_IDX',
'regCB_COLOR4_ATTRIB', 'regCB_COLOR4_ATTRIB2',
'regCB_COLOR4_ATTRIB2_BASE_IDX', 'regCB_COLOR4_ATTRIB3',
'regCB_COLOR4_ATTRIB3_BASE_IDX', 'regCB_COLOR4_ATTRIB_BASE_IDX',
'regCB_COLOR4_BASE', 'regCB_COLOR4_BASE_BASE_IDX',
'regCB_COLOR4_BASE_EXT', 'regCB_COLOR4_BASE_EXT_BASE_IDX',
'regCB_COLOR4_DCC_BASE', 'regCB_COLOR4_DCC_BASE_BASE_IDX',
'regCB_COLOR4_DCC_BASE_EXT', 'regCB_COLOR4_DCC_BASE_EXT_BASE_IDX',
'regCB_COLOR4_FDCC_CONTROL', 'regCB_COLOR4_FDCC_CONTROL_BASE_IDX',
'regCB_COLOR4_INFO', 'regCB_COLOR4_INFO_BASE_IDX',
'regCB_COLOR4_VIEW', 'regCB_COLOR4_VIEW_BASE_IDX',
'regCB_COLOR5_ATTRIB', 'regCB_COLOR5_ATTRIB2',
'regCB_COLOR5_ATTRIB2_BASE_IDX', 'regCB_COLOR5_ATTRIB3',
'regCB_COLOR5_ATTRIB3_BASE_IDX', 'regCB_COLOR5_ATTRIB_BASE_IDX',
'regCB_COLOR5_BASE', 'regCB_COLOR5_BASE_BASE_IDX',
'regCB_COLOR5_BASE_EXT', 'regCB_COLOR5_BASE_EXT_BASE_IDX',
'regCB_COLOR5_DCC_BASE', 'regCB_COLOR5_DCC_BASE_BASE_IDX',
'regCB_COLOR5_DCC_BASE_EXT', 'regCB_COLOR5_DCC_BASE_EXT_BASE_IDX',
'regCB_COLOR5_FDCC_CONTROL', 'regCB_COLOR5_FDCC_CONTROL_BASE_IDX',
'regCB_COLOR5_INFO', 'regCB_COLOR5_INFO_BASE_IDX',
'regCB_COLOR5_VIEW', 'regCB_COLOR5_VIEW_BASE_IDX',
'regCB_COLOR6_ATTRIB', 'regCB_COLOR6_ATTRIB2',
'regCB_COLOR6_ATTRIB2_BASE_IDX', 'regCB_COLOR6_ATTRIB3',
'regCB_COLOR6_ATTRIB3_BASE_IDX', 'regCB_COLOR6_ATTRIB_BASE_IDX',
'regCB_COLOR6_BASE', 'regCB_COLOR6_BASE_BASE_IDX',
'regCB_COLOR6_BASE_EXT', 'regCB_COLOR6_BASE_EXT_BASE_IDX',
'regCB_COLOR6_DCC_BASE', 'regCB_COLOR6_DCC_BASE_BASE_IDX',
'regCB_COLOR6_DCC_BASE_EXT', 'regCB_COLOR6_DCC_BASE_EXT_BASE_IDX',
'regCB_COLOR6_FDCC_CONTROL', 'regCB_COLOR6_FDCC_CONTROL_BASE_IDX',
'regCB_COLOR6_INFO', 'regCB_COLOR6_INFO_BASE_IDX',
'regCB_COLOR6_VIEW', 'regCB_COLOR6_VIEW_BASE_IDX',
'regCB_COLOR7_ATTRIB', 'regCB_COLOR7_ATTRIB2',
'regCB_COLOR7_ATTRIB2_BASE_IDX', 'regCB_COLOR7_ATTRIB3',
'regCB_COLOR7_ATTRIB3_BASE_IDX', 'regCB_COLOR7_ATTRIB_BASE_IDX',
'regCB_COLOR7_BASE', 'regCB_COLOR7_BASE_BASE_IDX',
'regCB_COLOR7_BASE_EXT', 'regCB_COLOR7_BASE_EXT_BASE_IDX',
'regCB_COLOR7_DCC_BASE', 'regCB_COLOR7_DCC_BASE_BASE_IDX',
'regCB_COLOR7_DCC_BASE_EXT', 'regCB_COLOR7_DCC_BASE_EXT_BASE_IDX',
'regCB_COLOR7_FDCC_CONTROL', 'regCB_COLOR7_FDCC_CONTROL_BASE_IDX',
'regCB_COLOR7_INFO', 'regCB_COLOR7_INFO_BASE_IDX',
'regCB_COLOR7_VIEW', 'regCB_COLOR7_VIEW_BASE_IDX',
'regCB_COLOR_CONTROL', 'regCB_COLOR_CONTROL_BASE_IDX',
'regCB_COVERAGE_OUT_CONTROL',
'regCB_COVERAGE_OUT_CONTROL_BASE_IDX', 'regCB_DCC_CONFIG',
'regCB_DCC_CONFIG2', 'regCB_DCC_CONFIG2_BASE_IDX',
'regCB_DCC_CONFIG_BASE_IDX', 'regCB_FDCC_CONTROL',
'regCB_FDCC_CONTROL_BASE_IDX', 'regCB_FGCG_SRAM_OVERRIDE',
'regCB_FGCG_SRAM_OVERRIDE_BASE_IDX', 'regCB_HW_CONTROL',
'regCB_HW_CONTROL_1', 'regCB_HW_CONTROL_1_BASE_IDX',
'regCB_HW_CONTROL_2', 'regCB_HW_CONTROL_2_BASE_IDX',
'regCB_HW_CONTROL_3', 'regCB_HW_CONTROL_3_BASE_IDX',
'regCB_HW_CONTROL_4', 'regCB_HW_CONTROL_4_BASE_IDX',
'regCB_HW_CONTROL_BASE_IDX', 'regCB_HW_MEM_ARBITER_RD',
'regCB_HW_MEM_ARBITER_RD_BASE_IDX', 'regCB_HW_MEM_ARBITER_WR',
'regCB_HW_MEM_ARBITER_WR_BASE_IDX', 'regCB_PERFCOUNTER0_HI',
'regCB_PERFCOUNTER0_HI_BASE_IDX', 'regCB_PERFCOUNTER0_LO',
'regCB_PERFCOUNTER0_LO_BASE_IDX', 'regCB_PERFCOUNTER0_SELECT',
'regCB_PERFCOUNTER0_SELECT1',
'regCB_PERFCOUNTER0_SELECT1_BASE_IDX',
'regCB_PERFCOUNTER0_SELECT_BASE_IDX', 'regCB_PERFCOUNTER1_HI',
'regCB_PERFCOUNTER1_HI_BASE_IDX', 'regCB_PERFCOUNTER1_LO',
'regCB_PERFCOUNTER1_LO_BASE_IDX', 'regCB_PERFCOUNTER1_SELECT',
'regCB_PERFCOUNTER1_SELECT_BASE_IDX', 'regCB_PERFCOUNTER2_HI',
'regCB_PERFCOUNTER2_HI_BASE_IDX', 'regCB_PERFCOUNTER2_LO',
'regCB_PERFCOUNTER2_LO_BASE_IDX', 'regCB_PERFCOUNTER2_SELECT',
'regCB_PERFCOUNTER2_SELECT_BASE_IDX', 'regCB_PERFCOUNTER3_HI',
'regCB_PERFCOUNTER3_HI_BASE_IDX', 'regCB_PERFCOUNTER3_LO',
'regCB_PERFCOUNTER3_LO_BASE_IDX', 'regCB_PERFCOUNTER3_SELECT',
'regCB_PERFCOUNTER3_SELECT_BASE_IDX', 'regCB_PERFCOUNTER_FILTER',
'regCB_PERFCOUNTER_FILTER_BASE_IDX',
'regCB_RMI_GL2_CACHE_CONTROL',
'regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX', 'regCB_SHADER_MASK',
'regCB_SHADER_MASK_BASE_IDX', 'regCB_TARGET_MASK',
'regCB_TARGET_MASK_BASE_IDX', 'regCC_GC_EDC_CONFIG',
'regCC_GC_EDC_CONFIG_BASE_IDX', 'regCC_GC_PRIM_CONFIG',
'regCC_GC_PRIM_CONFIG_BASE_IDX', 'regCC_GC_SA_UNIT_DISABLE',
'regCC_GC_SA_UNIT_DISABLE_BASE_IDX',
'regCC_GC_SHADER_ARRAY_CONFIG',
'regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX',
'regCC_GC_SHADER_RATE_CONFIG',
'regCC_GC_SHADER_RATE_CONFIG_BASE_IDX',
'regCC_RB_BACKEND_DISABLE', 'regCC_RB_BACKEND_DISABLE_BASE_IDX',
'regCC_RB_DAISY_CHAIN', 'regCC_RB_DAISY_CHAIN_BASE_IDX',
'regCC_RB_REDUNDANCY', 'regCC_RB_REDUNDANCY_BASE_IDX',
'regCC_RMI_REDUNDANCY', 'regCC_RMI_REDUNDANCY_BASE_IDX',
'regCGTS_TCC_DISABLE', 'regCGTS_TCC_DISABLE_BASE_IDX',
'regCGTS_USER_TCC_DISABLE', 'regCGTS_USER_TCC_DISABLE_BASE_IDX',
'regCGTT_CPC_CLK_CTRL', 'regCGTT_CPC_CLK_CTRL_BASE_IDX',
'regCGTT_CPF_CLK_CTRL', 'regCGTT_CPF_CLK_CTRL_BASE_IDX',
'regCGTT_CP_CLK_CTRL', 'regCGTT_CP_CLK_CTRL_BASE_IDX',
'regCGTT_GS_NGG_CLK_CTRL', 'regCGTT_GS_NGG_CLK_CTRL_BASE_IDX',
'regCGTT_PA_CLK_CTRL', 'regCGTT_PA_CLK_CTRL_BASE_IDX',
'regCGTT_PH_CLK_CTRL0', 'regCGTT_PH_CLK_CTRL0_BASE_IDX',
'regCGTT_PH_CLK_CTRL1', 'regCGTT_PH_CLK_CTRL1_BASE_IDX',
'regCGTT_PH_CLK_CTRL2', 'regCGTT_PH_CLK_CTRL2_BASE_IDX',
'regCGTT_PH_CLK_CTRL3', 'regCGTT_PH_CLK_CTRL3_BASE_IDX',
'regCGTT_RLC_CLK_CTRL', 'regCGTT_RLC_CLK_CTRL_BASE_IDX',
'regCGTT_SC_CLK_CTRL0', 'regCGTT_SC_CLK_CTRL0_BASE_IDX',
'regCGTT_SC_CLK_CTRL1', 'regCGTT_SC_CLK_CTRL1_BASE_IDX',
'regCGTT_SC_CLK_CTRL2', 'regCGTT_SC_CLK_CTRL2_BASE_IDX',
'regCGTT_SC_CLK_CTRL3', 'regCGTT_SC_CLK_CTRL3_BASE_IDX',
'regCGTT_SC_CLK_CTRL4', 'regCGTT_SC_CLK_CTRL4_BASE_IDX',
'regCGTT_SQG_CLK_CTRL', 'regCGTT_SQG_CLK_CTRL_BASE_IDX',
'regCHA_CHC_CREDITS', 'regCHA_CHC_CREDITS_BASE_IDX',
'regCHA_CLIENT_FREE_DELAY', 'regCHA_CLIENT_FREE_DELAY_BASE_IDX',
'regCHA_PERFCOUNTER0_HI', 'regCHA_PERFCOUNTER0_HI_BASE_IDX',
'regCHA_PERFCOUNTER0_LO', 'regCHA_PERFCOUNTER0_LO_BASE_IDX',
'regCHA_PERFCOUNTER0_SELECT', 'regCHA_PERFCOUNTER0_SELECT1',
'regCHA_PERFCOUNTER0_SELECT1_BASE_IDX',
'regCHA_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER1_HI',
'regCHA_PERFCOUNTER1_HI_BASE_IDX', 'regCHA_PERFCOUNTER1_LO',
'regCHA_PERFCOUNTER1_LO_BASE_IDX', 'regCHA_PERFCOUNTER1_SELECT',
'regCHA_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER2_HI',
'regCHA_PERFCOUNTER2_HI_BASE_IDX', 'regCHA_PERFCOUNTER2_LO',
'regCHA_PERFCOUNTER2_LO_BASE_IDX', 'regCHA_PERFCOUNTER2_SELECT',
'regCHA_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER3_HI',
'regCHA_PERFCOUNTER3_HI_BASE_IDX', 'regCHA_PERFCOUNTER3_LO',
'regCHA_PERFCOUNTER3_LO_BASE_IDX', 'regCHA_PERFCOUNTER3_SELECT',
'regCHA_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHCG_CTRL',
'regCHCG_CTRL_BASE_IDX', 'regCHCG_PERFCOUNTER0_HI',
'regCHCG_PERFCOUNTER0_HI_BASE_IDX', 'regCHCG_PERFCOUNTER0_LO',
'regCHCG_PERFCOUNTER0_LO_BASE_IDX', 'regCHCG_PERFCOUNTER0_SELECT',
'regCHCG_PERFCOUNTER0_SELECT1',
'regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX',
'regCHCG_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER1_HI',
'regCHCG_PERFCOUNTER1_HI_BASE_IDX', 'regCHCG_PERFCOUNTER1_LO',
'regCHCG_PERFCOUNTER1_LO_BASE_IDX', 'regCHCG_PERFCOUNTER1_SELECT',
'regCHCG_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER2_HI',
'regCHCG_PERFCOUNTER2_HI_BASE_IDX', 'regCHCG_PERFCOUNTER2_LO',
'regCHCG_PERFCOUNTER2_LO_BASE_IDX', 'regCHCG_PERFCOUNTER2_SELECT',
'regCHCG_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER3_HI',
'regCHCG_PERFCOUNTER3_HI_BASE_IDX', 'regCHCG_PERFCOUNTER3_LO',
'regCHCG_PERFCOUNTER3_LO_BASE_IDX', 'regCHCG_PERFCOUNTER3_SELECT',
'regCHCG_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHCG_STATUS',
'regCHCG_STATUS_BASE_IDX', 'regCHC_CTRL', 'regCHC_CTRL_BASE_IDX',
'regCHC_PERFCOUNTER0_HI', 'regCHC_PERFCOUNTER0_HI_BASE_IDX',
'regCHC_PERFCOUNTER0_LO', 'regCHC_PERFCOUNTER0_LO_BASE_IDX',
'regCHC_PERFCOUNTER0_SELECT', 'regCHC_PERFCOUNTER0_SELECT1',
'regCHC_PERFCOUNTER0_SELECT1_BASE_IDX',
'regCHC_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER1_HI',
'regCHC_PERFCOUNTER1_HI_BASE_IDX', 'regCHC_PERFCOUNTER1_LO',
'regCHC_PERFCOUNTER1_LO_BASE_IDX', 'regCHC_PERFCOUNTER1_SELECT',
'regCHC_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER2_HI',
'regCHC_PERFCOUNTER2_HI_BASE_IDX', 'regCHC_PERFCOUNTER2_LO',
'regCHC_PERFCOUNTER2_LO_BASE_IDX', 'regCHC_PERFCOUNTER2_SELECT',
'regCHC_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER3_HI',
'regCHC_PERFCOUNTER3_HI_BASE_IDX', 'regCHC_PERFCOUNTER3_LO',
'regCHC_PERFCOUNTER3_LO_BASE_IDX', 'regCHC_PERFCOUNTER3_SELECT',
'regCHC_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHC_STATUS',
'regCHC_STATUS_BASE_IDX', 'regCHICKEN_BITS',
'regCHICKEN_BITS_BASE_IDX', 'regCHI_CHR_MGCG_OVERRIDE',
'regCHI_CHR_MGCG_OVERRIDE_BASE_IDX',
'regCHI_CHR_REP_FGCG_OVERRIDE',
'regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX', 'regCH_ARB_CTRL',
'regCH_ARB_CTRL_BASE_IDX', 'regCH_ARB_STATUS',
'regCH_ARB_STATUS_BASE_IDX', 'regCH_DRAM_BURST_CTRL',
'regCH_DRAM_BURST_CTRL_BASE_IDX', 'regCH_DRAM_BURST_MASK',
'regCH_DRAM_BURST_MASK_BASE_IDX', 'regCH_PIPE_STEER',
'regCH_PIPE_STEER_BASE_IDX', 'regCH_VC5_ENABLE',
'regCH_VC5_ENABLE_BASE_IDX', 'regCOHER_DEST_BASE_0',
'regCOHER_DEST_BASE_0_BASE_IDX', 'regCOHER_DEST_BASE_1',
'regCOHER_DEST_BASE_1_BASE_IDX', 'regCOHER_DEST_BASE_2',
'regCOHER_DEST_BASE_2_BASE_IDX', 'regCOHER_DEST_BASE_3',
'regCOHER_DEST_BASE_3_BASE_IDX', 'regCOHER_DEST_BASE_HI_0',
'regCOHER_DEST_BASE_HI_0_BASE_IDX', 'regCOHER_DEST_BASE_HI_1',
'regCOHER_DEST_BASE_HI_1_BASE_IDX', 'regCOHER_DEST_BASE_HI_2',
'regCOHER_DEST_BASE_HI_2_BASE_IDX', 'regCOHER_DEST_BASE_HI_3',
'regCOHER_DEST_BASE_HI_3_BASE_IDX', 'regCOMPUTE_DDID_INDEX',
'regCOMPUTE_DDID_INDEX_BASE_IDX', 'regCOMPUTE_DESTINATION_EN_SE0',
'regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX',
'regCOMPUTE_DESTINATION_EN_SE1',
'regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX',
'regCOMPUTE_DESTINATION_EN_SE2',
'regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX',
'regCOMPUTE_DESTINATION_EN_SE3',
'regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX', 'regCOMPUTE_DIM_X',
'regCOMPUTE_DIM_X_BASE_IDX', 'regCOMPUTE_DIM_Y',
'regCOMPUTE_DIM_Y_BASE_IDX', 'regCOMPUTE_DIM_Z',
'regCOMPUTE_DIM_Z_BASE_IDX', 'regCOMPUTE_DISPATCH_END',
'regCOMPUTE_DISPATCH_END_BASE_IDX', 'regCOMPUTE_DISPATCH_ID',
'regCOMPUTE_DISPATCH_ID_BASE_IDX',
'regCOMPUTE_DISPATCH_INITIATOR',
'regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX',
'regCOMPUTE_DISPATCH_INTERLEAVE',
'regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX',
'regCOMPUTE_DISPATCH_PKT_ADDR_HI',
'regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX',
'regCOMPUTE_DISPATCH_PKT_ADDR_LO',
'regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX',
'regCOMPUTE_DISPATCH_SCRATCH_BASE_HI',
'regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX',
'regCOMPUTE_DISPATCH_SCRATCH_BASE_LO',
'regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX',
'regCOMPUTE_DISPATCH_TUNNEL',
'regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX', 'regCOMPUTE_MISC_RESERVED',
'regCOMPUTE_MISC_RESERVED_BASE_IDX', 'regCOMPUTE_NOWHERE',
'regCOMPUTE_NOWHERE_BASE_IDX', 'regCOMPUTE_NUM_THREAD_X',
'regCOMPUTE_NUM_THREAD_X_BASE_IDX', 'regCOMPUTE_NUM_THREAD_Y',
'regCOMPUTE_NUM_THREAD_Y_BASE_IDX', 'regCOMPUTE_NUM_THREAD_Z',
'regCOMPUTE_NUM_THREAD_Z_BASE_IDX', 'regCOMPUTE_PERFCOUNT_ENABLE',
'regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX', 'regCOMPUTE_PGM_HI',
'regCOMPUTE_PGM_HI_BASE_IDX', 'regCOMPUTE_PGM_LO',
'regCOMPUTE_PGM_LO_BASE_IDX', 'regCOMPUTE_PGM_RSRC1',
'regCOMPUTE_PGM_RSRC1_BASE_IDX', 'regCOMPUTE_PGM_RSRC2',
'regCOMPUTE_PGM_RSRC2_BASE_IDX', 'regCOMPUTE_PGM_RSRC3',
'regCOMPUTE_PGM_RSRC3_BASE_IDX', 'regCOMPUTE_PIPELINESTAT_ENABLE',
'regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX', 'regCOMPUTE_RELAUNCH',
'regCOMPUTE_RELAUNCH2', 'regCOMPUTE_RELAUNCH2_BASE_IDX',
'regCOMPUTE_RELAUNCH_BASE_IDX', 'regCOMPUTE_REQ_CTRL',
'regCOMPUTE_REQ_CTRL_BASE_IDX', 'regCOMPUTE_RESOURCE_LIMITS',
'regCOMPUTE_RESOURCE_LIMITS_BASE_IDX', 'regCOMPUTE_RESTART_X',
'regCOMPUTE_RESTART_X_BASE_IDX', 'regCOMPUTE_RESTART_Y',
'regCOMPUTE_RESTART_Y_BASE_IDX', 'regCOMPUTE_RESTART_Z',
'regCOMPUTE_RESTART_Z_BASE_IDX', 'regCOMPUTE_SHADER_CHKSUM',
'regCOMPUTE_SHADER_CHKSUM_BASE_IDX', 'regCOMPUTE_START_X',
'regCOMPUTE_START_X_BASE_IDX', 'regCOMPUTE_START_Y',
'regCOMPUTE_START_Y_BASE_IDX', 'regCOMPUTE_START_Z',
'regCOMPUTE_START_Z_BASE_IDX',
'regCOMPUTE_STATIC_THREAD_MGMT_SE0',
'regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX',
'regCOMPUTE_STATIC_THREAD_MGMT_SE1',
'regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX',
'regCOMPUTE_STATIC_THREAD_MGMT_SE2',
'regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX',
'regCOMPUTE_STATIC_THREAD_MGMT_SE3',
'regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX',
'regCOMPUTE_STATIC_THREAD_MGMT_SE4',
'regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX',
'regCOMPUTE_STATIC_THREAD_MGMT_SE5',
'regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX',
'regCOMPUTE_STATIC_THREAD_MGMT_SE6',
'regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX',
'regCOMPUTE_STATIC_THREAD_MGMT_SE7',
'regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX',
'regCOMPUTE_THREADGROUP_ID', 'regCOMPUTE_THREADGROUP_ID_BASE_IDX',
'regCOMPUTE_THREAD_TRACE_ENABLE',
'regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX',
'regCOMPUTE_TMPRING_SIZE', 'regCOMPUTE_TMPRING_SIZE_BASE_IDX',
'regCOMPUTE_USER_ACCUM_0', 'regCOMPUTE_USER_ACCUM_0_BASE_IDX',
'regCOMPUTE_USER_ACCUM_1', 'regCOMPUTE_USER_ACCUM_1_BASE_IDX',
'regCOMPUTE_USER_ACCUM_2', 'regCOMPUTE_USER_ACCUM_2_BASE_IDX',
'regCOMPUTE_USER_ACCUM_3', 'regCOMPUTE_USER_ACCUM_3_BASE_IDX',
'regCOMPUTE_USER_DATA_0', 'regCOMPUTE_USER_DATA_0_BASE_IDX',
'regCOMPUTE_USER_DATA_1', 'regCOMPUTE_USER_DATA_10',
'regCOMPUTE_USER_DATA_10_BASE_IDX', 'regCOMPUTE_USER_DATA_11',
'regCOMPUTE_USER_DATA_11_BASE_IDX', 'regCOMPUTE_USER_DATA_12',
'regCOMPUTE_USER_DATA_12_BASE_IDX', 'regCOMPUTE_USER_DATA_13',
'regCOMPUTE_USER_DATA_13_BASE_IDX', 'regCOMPUTE_USER_DATA_14',
'regCOMPUTE_USER_DATA_14_BASE_IDX', 'regCOMPUTE_USER_DATA_15',
'regCOMPUTE_USER_DATA_15_BASE_IDX',
'regCOMPUTE_USER_DATA_1_BASE_IDX', 'regCOMPUTE_USER_DATA_2',
'regCOMPUTE_USER_DATA_2_BASE_IDX', 'regCOMPUTE_USER_DATA_3',
'regCOMPUTE_USER_DATA_3_BASE_IDX', 'regCOMPUTE_USER_DATA_4',
'regCOMPUTE_USER_DATA_4_BASE_IDX', 'regCOMPUTE_USER_DATA_5',
'regCOMPUTE_USER_DATA_5_BASE_IDX', 'regCOMPUTE_USER_DATA_6',
'regCOMPUTE_USER_DATA_6_BASE_IDX', 'regCOMPUTE_USER_DATA_7',
'regCOMPUTE_USER_DATA_7_BASE_IDX', 'regCOMPUTE_USER_DATA_8',
'regCOMPUTE_USER_DATA_8_BASE_IDX', 'regCOMPUTE_USER_DATA_9',
'regCOMPUTE_USER_DATA_9_BASE_IDX', 'regCOMPUTE_VMID',
'regCOMPUTE_VMID_BASE_IDX', 'regCOMPUTE_WAVE_RESTORE_ADDR_HI',
'regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX',
'regCOMPUTE_WAVE_RESTORE_ADDR_LO',
'regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX',
'regCONFIG_RESERVED_REG0', 'regCONFIG_RESERVED_REG0_BASE_IDX',
'regCONFIG_RESERVED_REG1', 'regCONFIG_RESERVED_REG1_BASE_IDX',
'regCONTEXT_RESERVED_REG0', 'regCONTEXT_RESERVED_REG0_BASE_IDX',
'regCONTEXT_RESERVED_REG1', 'regCONTEXT_RESERVED_REG1_BASE_IDX',
'regCPC_DDID_BASE_ADDR_HI', 'regCPC_DDID_BASE_ADDR_HI_BASE_IDX',
'regCPC_DDID_BASE_ADDR_LO', 'regCPC_DDID_BASE_ADDR_LO_BASE_IDX',
'regCPC_DDID_CNTL', 'regCPC_DDID_CNTL_BASE_IDX',
'regCPC_INT_ADDR', 'regCPC_INT_ADDR_BASE_IDX', 'regCPC_INT_CNTL',
'regCPC_INT_CNTL_BASE_IDX', 'regCPC_INT_CNTX_ID',
'regCPC_INT_CNTX_ID_BASE_IDX', 'regCPC_INT_INFO',
'regCPC_INT_INFO_BASE_IDX', 'regCPC_INT_PASID',
'regCPC_INT_PASID_BASE_IDX', 'regCPC_INT_STATUS',
'regCPC_INT_STATUS_BASE_IDX', 'regCPC_LATENCY_STATS_DATA',
'regCPC_LATENCY_STATS_DATA_BASE_IDX',
'regCPC_LATENCY_STATS_SELECT',
'regCPC_LATENCY_STATS_SELECT_BASE_IDX', 'regCPC_OS_PIPES',
'regCPC_OS_PIPES_BASE_IDX', 'regCPC_PERFCOUNTER0_HI',
'regCPC_PERFCOUNTER0_HI_BASE_IDX', 'regCPC_PERFCOUNTER0_LO',
'regCPC_PERFCOUNTER0_LO_BASE_IDX', 'regCPC_PERFCOUNTER0_SELECT',
'regCPC_PERFCOUNTER0_SELECT1',
'regCPC_PERFCOUNTER0_SELECT1_BASE_IDX',
'regCPC_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPC_PERFCOUNTER1_HI',
'regCPC_PERFCOUNTER1_HI_BASE_IDX', 'regCPC_PERFCOUNTER1_LO',
'regCPC_PERFCOUNTER1_LO_BASE_IDX', 'regCPC_PERFCOUNTER1_SELECT',
'regCPC_PERFCOUNTER1_SELECT_BASE_IDX', 'regCPC_PSP_DEBUG',
'regCPC_PSP_DEBUG_BASE_IDX', 'regCPC_SUSPEND_CNTL_STACK_OFFSET',
'regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX',
'regCPC_SUSPEND_CNTL_STACK_SIZE',
'regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX',
'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI',
'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX',
'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO',
'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX',
'regCPC_SUSPEND_CTX_SAVE_CONTROL',
'regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX',
'regCPC_SUSPEND_CTX_SAVE_SIZE',
'regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX',
'regCPC_SUSPEND_WG_STATE_OFFSET',
'regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX',
'regCPC_TC_PERF_COUNTER_WINDOW_SELECT',
'regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX',
'regCPC_UTCL1_CNTL', 'regCPC_UTCL1_CNTL_BASE_IDX',
'regCPC_UTCL1_ERROR', 'regCPC_UTCL1_ERROR_BASE_IDX',
'regCPC_UTCL1_STATUS', 'regCPC_UTCL1_STATUS_BASE_IDX',
'regCPF_GCR_CNTL', 'regCPF_GCR_CNTL_BASE_IDX',
'regCPF_LATENCY_STATS_DATA', 'regCPF_LATENCY_STATS_DATA_BASE_IDX',
'regCPF_LATENCY_STATS_SELECT',
'regCPF_LATENCY_STATS_SELECT_BASE_IDX', 'regCPF_PERFCOUNTER0_HI',
'regCPF_PERFCOUNTER0_HI_BASE_IDX', 'regCPF_PERFCOUNTER0_LO',
'regCPF_PERFCOUNTER0_LO_BASE_IDX', 'regCPF_PERFCOUNTER0_SELECT',
'regCPF_PERFCOUNTER0_SELECT1',
'regCPF_PERFCOUNTER0_SELECT1_BASE_IDX',
'regCPF_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPF_PERFCOUNTER1_HI',
'regCPF_PERFCOUNTER1_HI_BASE_IDX', 'regCPF_PERFCOUNTER1_LO',
'regCPF_PERFCOUNTER1_LO_BASE_IDX', 'regCPF_PERFCOUNTER1_SELECT',
'regCPF_PERFCOUNTER1_SELECT_BASE_IDX',
'regCPF_TC_PERF_COUNTER_WINDOW_SELECT',
'regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX',
'regCPF_UTCL1_CNTL', 'regCPF_UTCL1_CNTL_BASE_IDX',
'regCPF_UTCL1_STATUS', 'regCPF_UTCL1_STATUS_BASE_IDX',
'regCPG_LATENCY_STATS_DATA', 'regCPG_LATENCY_STATS_DATA_BASE_IDX',
'regCPG_LATENCY_STATS_SELECT',
'regCPG_LATENCY_STATS_SELECT_BASE_IDX', 'regCPG_PERFCOUNTER0_HI',
'regCPG_PERFCOUNTER0_HI_BASE_IDX', 'regCPG_PERFCOUNTER0_LO',
'regCPG_PERFCOUNTER0_LO_BASE_IDX', 'regCPG_PERFCOUNTER0_SELECT',
'regCPG_PERFCOUNTER0_SELECT1',
'regCPG_PERFCOUNTER0_SELECT1_BASE_IDX',
'regCPG_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPG_PERFCOUNTER1_HI',
'regCPG_PERFCOUNTER1_HI_BASE_IDX', 'regCPG_PERFCOUNTER1_LO',
'regCPG_PERFCOUNTER1_LO_BASE_IDX', 'regCPG_PERFCOUNTER1_SELECT',
'regCPG_PERFCOUNTER1_SELECT_BASE_IDX', 'regCPG_PSP_DEBUG',
'regCPG_PSP_DEBUG_BASE_IDX', 'regCPG_RCIU_CAM_DATA',
'regCPG_RCIU_CAM_DATA_BASE_IDX', 'regCPG_RCIU_CAM_DATA_PHASE0',
'regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX',
'regCPG_RCIU_CAM_DATA_PHASE1',
'regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX',
'regCPG_RCIU_CAM_DATA_PHASE2',
'regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX', 'regCPG_RCIU_CAM_INDEX',
'regCPG_RCIU_CAM_INDEX_BASE_IDX',
'regCPG_TC_PERF_COUNTER_WINDOW_SELECT',
'regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX',
'regCPG_UTCL1_CNTL', 'regCPG_UTCL1_CNTL_BASE_IDX',
'regCPG_UTCL1_ERROR', 'regCPG_UTCL1_ERROR_BASE_IDX',
'regCPG_UTCL1_STATUS', 'regCPG_UTCL1_STATUS_BASE_IDX',
'regCP_APPEND_ADDR_HI', 'regCP_APPEND_ADDR_HI_BASE_IDX',
'regCP_APPEND_ADDR_LO', 'regCP_APPEND_ADDR_LO_BASE_IDX',
'regCP_APPEND_CMD_ADDR_HI', 'regCP_APPEND_CMD_ADDR_HI_BASE_IDX',
'regCP_APPEND_CMD_ADDR_LO', 'regCP_APPEND_CMD_ADDR_LO_BASE_IDX',
'regCP_APPEND_DATA', 'regCP_APPEND_DATA_BASE_IDX',
'regCP_APPEND_DATA_HI', 'regCP_APPEND_DATA_HI_BASE_IDX',
'regCP_APPEND_DATA_LO', 'regCP_APPEND_DATA_LO_BASE_IDX',
'regCP_APPEND_DDID_CNT', 'regCP_APPEND_DDID_CNT_BASE_IDX',
'regCP_APPEND_LAST_CS_FENCE',
'regCP_APPEND_LAST_CS_FENCE_BASE_IDX',
'regCP_APPEND_LAST_CS_FENCE_HI',
'regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX',
'regCP_APPEND_LAST_CS_FENCE_LO',
'regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX',
'regCP_APPEND_LAST_PS_FENCE',
'regCP_APPEND_LAST_PS_FENCE_BASE_IDX',
'regCP_APPEND_LAST_PS_FENCE_HI',
'regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX',
'regCP_APPEND_LAST_PS_FENCE_LO',
'regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX', 'regCP_AQL_SMM_STATUS',
'regCP_AQL_SMM_STATUS_BASE_IDX', 'regCP_ATOMIC_PREOP_HI',
'regCP_ATOMIC_PREOP_HI_BASE_IDX', 'regCP_ATOMIC_PREOP_LO',
'regCP_ATOMIC_PREOP_LO_BASE_IDX', 'regCP_BUSY_STAT',
'regCP_BUSY_STAT_BASE_IDX', 'regCP_CMD_DATA',
'regCP_CMD_DATA_BASE_IDX', 'regCP_CMD_INDEX',
'regCP_CMD_INDEX_BASE_IDX', 'regCP_CNTX_STAT',
'regCP_CNTX_STAT_BASE_IDX', 'regCP_CONTEXT_CNTL',
'regCP_CONTEXT_CNTL_BASE_IDX', 'regCP_CPC_BUSY_HYSTERESIS',
'regCP_CPC_BUSY_HYSTERESIS_BASE_IDX', 'regCP_CPC_BUSY_STAT',
'regCP_CPC_BUSY_STAT2', 'regCP_CPC_BUSY_STAT2_BASE_IDX',
'regCP_CPC_BUSY_STAT_BASE_IDX', 'regCP_CPC_DEBUG',
'regCP_CPC_DEBUG_BASE_IDX', 'regCP_CPC_DEBUG_CNTL',
'regCP_CPC_DEBUG_CNTL_BASE_IDX', 'regCP_CPC_DEBUG_DATA',
'regCP_CPC_DEBUG_DATA_BASE_IDX', 'regCP_CPC_GFX_CNTL',
'regCP_CPC_GFX_CNTL_BASE_IDX', 'regCP_CPC_GRBM_FREE_COUNT',
'regCP_CPC_GRBM_FREE_COUNT_BASE_IDX', 'regCP_CPC_HALT_HYST_COUNT',
'regCP_CPC_HALT_HYST_COUNT_BASE_IDX', 'regCP_CPC_IC_BASE_CNTL',
'regCP_CPC_IC_BASE_CNTL_BASE_IDX', 'regCP_CPC_IC_BASE_HI',
'regCP_CPC_IC_BASE_HI_BASE_IDX', 'regCP_CPC_IC_BASE_LO',
'regCP_CPC_IC_BASE_LO_BASE_IDX', 'regCP_CPC_IC_OP_CNTL',
'regCP_CPC_IC_OP_CNTL_BASE_IDX', 'regCP_CPC_MGCG_SYNC_CNTL',
'regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX',
'regCP_CPC_PRIV_VIOLATION_ADDR',
'regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX',
'regCP_CPC_SCRATCH_DATA', 'regCP_CPC_SCRATCH_DATA_BASE_IDX',
'regCP_CPC_SCRATCH_INDEX', 'regCP_CPC_SCRATCH_INDEX_BASE_IDX',
'regCP_CPC_STALLED_STAT1', 'regCP_CPC_STALLED_STAT1_BASE_IDX',
'regCP_CPC_STATUS', 'regCP_CPC_STATUS_BASE_IDX',
'regCP_CPF_BUSY_HYSTERESIS1',
'regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX',
'regCP_CPF_BUSY_HYSTERESIS2',
'regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX', 'regCP_CPF_BUSY_STAT',
'regCP_CPF_BUSY_STAT2', 'regCP_CPF_BUSY_STAT2_BASE_IDX',
'regCP_CPF_BUSY_STAT_BASE_IDX', 'regCP_CPF_GRBM_FREE_COUNT',
'regCP_CPF_GRBM_FREE_COUNT_BASE_IDX', 'regCP_CPF_STALLED_STAT1',
'regCP_CPF_STALLED_STAT1_BASE_IDX', 'regCP_CPF_STATUS',
'regCP_CPF_STATUS_BASE_IDX', 'regCP_CPG_BUSY_HYSTERESIS1',
'regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX',
'regCP_CPG_BUSY_HYSTERESIS2',
'regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX', 'regCP_CSF_STAT',
'regCP_CSF_STAT_BASE_IDX', 'regCP_CU_MASK_ADDR_HI',
'regCP_CU_MASK_ADDR_HI_BASE_IDX', 'regCP_CU_MASK_ADDR_LO',
'regCP_CU_MASK_ADDR_LO_BASE_IDX', 'regCP_CU_MASK_CNTL',
'regCP_CU_MASK_CNTL_BASE_IDX', 'regCP_DB_BASE_HI',
'regCP_DB_BASE_HI_BASE_IDX', 'regCP_DB_BASE_LO',
'regCP_DB_BASE_LO_BASE_IDX', 'regCP_DB_BUFSZ',
'regCP_DB_BUFSZ_BASE_IDX', 'regCP_DB_CMD_BUFSZ',
'regCP_DB_CMD_BUFSZ_BASE_IDX', 'regCP_DDID_BASE_ADDR_HI',
'regCP_DDID_BASE_ADDR_HI_BASE_IDX', 'regCP_DDID_BASE_ADDR_LO',
'regCP_DDID_BASE_ADDR_LO_BASE_IDX', 'regCP_DDID_CNTL',
'regCP_DDID_CNTL_BASE_IDX', 'regCP_DEBUG', 'regCP_DEBUG_2',
'regCP_DEBUG_2_BASE_IDX', 'regCP_DEBUG_BASE_IDX',
'regCP_DEBUG_CNTL', 'regCP_DEBUG_CNTL_BASE_IDX',
'regCP_DEBUG_DATA', 'regCP_DEBUG_DATA_BASE_IDX',
'regCP_DEVICE_ID', 'regCP_DEVICE_ID_BASE_IDX',
'regCP_DISPATCH_INDR_ADDR', 'regCP_DISPATCH_INDR_ADDR_BASE_IDX',
'regCP_DISPATCH_INDR_ADDR_HI',
'regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX', 'regCP_DMA_CNTL',
'regCP_DMA_CNTL_BASE_IDX', 'regCP_DMA_ME_CMD_ADDR_HI',
'regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX', 'regCP_DMA_ME_CMD_ADDR_LO',
'regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX', 'regCP_DMA_ME_COMMAND',
'regCP_DMA_ME_COMMAND_BASE_IDX', 'regCP_DMA_ME_CONTROL',
'regCP_DMA_ME_CONTROL_BASE_IDX', 'regCP_DMA_ME_DST_ADDR',
'regCP_DMA_ME_DST_ADDR_BASE_IDX', 'regCP_DMA_ME_DST_ADDR_HI',
'regCP_DMA_ME_DST_ADDR_HI_BASE_IDX', 'regCP_DMA_ME_SRC_ADDR',
'regCP_DMA_ME_SRC_ADDR_BASE_IDX', 'regCP_DMA_ME_SRC_ADDR_HI',
'regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_CMD_ADDR_HI',
'regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_CMD_ADDR_LO',
'regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX', 'regCP_DMA_PFP_COMMAND',
'regCP_DMA_PFP_COMMAND_BASE_IDX', 'regCP_DMA_PFP_CONTROL',
'regCP_DMA_PFP_CONTROL_BASE_IDX', 'regCP_DMA_PFP_DST_ADDR',
'regCP_DMA_PFP_DST_ADDR_BASE_IDX', 'regCP_DMA_PFP_DST_ADDR_HI',
'regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_SRC_ADDR',
'regCP_DMA_PFP_SRC_ADDR_BASE_IDX', 'regCP_DMA_PFP_SRC_ADDR_HI',
'regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX', 'regCP_DMA_READ_TAGS',
'regCP_DMA_READ_TAGS_BASE_IDX', 'regCP_DMA_WATCH0_ADDR_HI',
'regCP_DMA_WATCH0_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH0_ADDR_LO',
'regCP_DMA_WATCH0_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH0_CNTL',
'regCP_DMA_WATCH0_CNTL_BASE_IDX', 'regCP_DMA_WATCH0_MASK',
'regCP_DMA_WATCH0_MASK_BASE_IDX', 'regCP_DMA_WATCH1_ADDR_HI',
'regCP_DMA_WATCH1_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH1_ADDR_LO',
'regCP_DMA_WATCH1_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH1_CNTL',
'regCP_DMA_WATCH1_CNTL_BASE_IDX', 'regCP_DMA_WATCH1_MASK',
'regCP_DMA_WATCH1_MASK_BASE_IDX', 'regCP_DMA_WATCH2_ADDR_HI',
'regCP_DMA_WATCH2_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH2_ADDR_LO',
'regCP_DMA_WATCH2_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH2_CNTL',
'regCP_DMA_WATCH2_CNTL_BASE_IDX', 'regCP_DMA_WATCH2_MASK',
'regCP_DMA_WATCH2_MASK_BASE_IDX', 'regCP_DMA_WATCH3_ADDR_HI',
'regCP_DMA_WATCH3_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH3_ADDR_LO',
'regCP_DMA_WATCH3_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH3_CNTL',
'regCP_DMA_WATCH3_CNTL_BASE_IDX', 'regCP_DMA_WATCH3_MASK',
'regCP_DMA_WATCH3_MASK_BASE_IDX', 'regCP_DMA_WATCH_STAT',
'regCP_DMA_WATCH_STAT_ADDR_HI',
'regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX',
'regCP_DMA_WATCH_STAT_ADDR_LO',
'regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX',
'regCP_DMA_WATCH_STAT_BASE_IDX', 'regCP_DRAW_INDX_INDR_ADDR',
'regCP_DRAW_INDX_INDR_ADDR_BASE_IDX',
'regCP_DRAW_INDX_INDR_ADDR_HI',
'regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX', 'regCP_DRAW_OBJECT',
'regCP_DRAW_OBJECT_BASE_IDX', 'regCP_DRAW_OBJECT_COUNTER',
'regCP_DRAW_OBJECT_COUNTER_BASE_IDX', 'regCP_DRAW_WINDOW_CNTL',
'regCP_DRAW_WINDOW_CNTL_BASE_IDX', 'regCP_DRAW_WINDOW_HI',
'regCP_DRAW_WINDOW_HI_BASE_IDX', 'regCP_DRAW_WINDOW_LO',
'regCP_DRAW_WINDOW_LO_BASE_IDX', 'regCP_DRAW_WINDOW_MASK_HI',
'regCP_DRAW_WINDOW_MASK_HI_BASE_IDX', 'regCP_ECC_FIRSTOCCURRENCE',
'regCP_ECC_FIRSTOCCURRENCE_BASE_IDX',
'regCP_ECC_FIRSTOCCURRENCE_RING0',
'regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX',
'regCP_ECC_FIRSTOCCURRENCE_RING1',
'regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX',
'regCP_EOPQ_WAIT_TIME', 'regCP_EOPQ_WAIT_TIME_BASE_IDX',
'regCP_EOP_DONE_ADDR_HI', 'regCP_EOP_DONE_ADDR_HI_BASE_IDX',
'regCP_EOP_DONE_ADDR_LO', 'regCP_EOP_DONE_ADDR_LO_BASE_IDX',
'regCP_EOP_DONE_CNTX_ID', 'regCP_EOP_DONE_CNTX_ID_BASE_IDX',
'regCP_EOP_DONE_DATA_CNTL', 'regCP_EOP_DONE_DATA_CNTL_BASE_IDX',
'regCP_EOP_DONE_DATA_HI', 'regCP_EOP_DONE_DATA_HI_BASE_IDX',
'regCP_EOP_DONE_DATA_LO', 'regCP_EOP_DONE_DATA_LO_BASE_IDX',
'regCP_EOP_DONE_EVENT_CNTL', 'regCP_EOP_DONE_EVENT_CNTL_BASE_IDX',
'regCP_EOP_LAST_FENCE_HI', 'regCP_EOP_LAST_FENCE_HI_BASE_IDX',
'regCP_EOP_LAST_FENCE_LO', 'regCP_EOP_LAST_FENCE_LO_BASE_IDX',
'regCP_FATAL_ERROR', 'regCP_FATAL_ERROR_BASE_IDX',
'regCP_FETCHER_SOURCE', 'regCP_FETCHER_SOURCE_BASE_IDX',
'regCP_GDS_ATOMIC0_PREOP_HI',
'regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX',
'regCP_GDS_ATOMIC0_PREOP_LO',
'regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX',
'regCP_GDS_ATOMIC1_PREOP_HI',
'regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX',
'regCP_GDS_ATOMIC1_PREOP_LO',
'regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'regCP_GDS_BKUP_ADDR',
'regCP_GDS_BKUP_ADDR_BASE_IDX', 'regCP_GDS_BKUP_ADDR_HI',
'regCP_GDS_BKUP_ADDR_HI_BASE_IDX', 'regCP_GE_MSINVOC_COUNT_HI',
'regCP_GE_MSINVOC_COUNT_HI_BASE_IDX', 'regCP_GE_MSINVOC_COUNT_LO',
'regCP_GE_MSINVOC_COUNT_LO_BASE_IDX', 'regCP_GFX_CNTL',
'regCP_GFX_CNTL_BASE_IDX', 'regCP_GFX_DDID_DELTA_RPT_COUNT',
'regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX',
'regCP_GFX_DDID_INFLIGHT_COUNT',
'regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX', 'regCP_GFX_DDID_RPTR',
'regCP_GFX_DDID_RPTR_BASE_IDX', 'regCP_GFX_DDID_WPTR',
'regCP_GFX_DDID_WPTR_BASE_IDX', 'regCP_GFX_ERROR',
'regCP_GFX_ERROR_BASE_IDX', 'regCP_GFX_HPD_CONTROL0',
'regCP_GFX_HPD_CONTROL0_BASE_IDX',
'regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI',
'regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX',
'regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO',
'regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX',
'regCP_GFX_HPD_OSPRE_FENCE_DATA_HI',
'regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX',
'regCP_GFX_HPD_OSPRE_FENCE_DATA_LO',
'regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX',
'regCP_GFX_HPD_STATUS0', 'regCP_GFX_HPD_STATUS0_BASE_IDX',
'regCP_GFX_HQD_ACTIVE', 'regCP_GFX_HQD_ACTIVE_BASE_IDX',
'regCP_GFX_HQD_BASE', 'regCP_GFX_HQD_BASE_BASE_IDX',
'regCP_GFX_HQD_BASE_HI', 'regCP_GFX_HQD_BASE_HI_BASE_IDX',
'regCP_GFX_HQD_CNTL', 'regCP_GFX_HQD_CNTL_BASE_IDX',
'regCP_GFX_HQD_CSMD_RPTR', 'regCP_GFX_HQD_CSMD_RPTR_BASE_IDX',
'regCP_GFX_HQD_DEQUEUE_REQUEST',
'regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX',
'regCP_GFX_HQD_HQ_CONTROL0', 'regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX',
'regCP_GFX_HQD_HQ_STATUS0', 'regCP_GFX_HQD_HQ_STATUS0_BASE_IDX',
'regCP_GFX_HQD_IQ_TIMER', 'regCP_GFX_HQD_IQ_TIMER_BASE_IDX',
'regCP_GFX_HQD_MAPPED', 'regCP_GFX_HQD_MAPPED_BASE_IDX',
'regCP_GFX_HQD_OFFSET', 'regCP_GFX_HQD_OFFSET_BASE_IDX',
'regCP_GFX_HQD_QUANTUM', 'regCP_GFX_HQD_QUANTUM_BASE_IDX',
'regCP_GFX_HQD_QUEUE_PRIORITY',
'regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX',
'regCP_GFX_HQD_QUE_MGR_CONTROL',
'regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX', 'regCP_GFX_HQD_RPTR',
'regCP_GFX_HQD_RPTR_ADDR', 'regCP_GFX_HQD_RPTR_ADDR_BASE_IDX',
'regCP_GFX_HQD_RPTR_ADDR_HI',
'regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX',
'regCP_GFX_HQD_RPTR_BASE_IDX', 'regCP_GFX_HQD_VMID',
'regCP_GFX_HQD_VMID_BASE_IDX', 'regCP_GFX_HQD_WPTR',
'regCP_GFX_HQD_WPTR_BASE_IDX', 'regCP_GFX_HQD_WPTR_HI',
'regCP_GFX_HQD_WPTR_HI_BASE_IDX', 'regCP_GFX_INDEX_MUTEX',
'regCP_GFX_INDEX_MUTEX_BASE_IDX', 'regCP_GFX_MQD_BASE_ADDR',
'regCP_GFX_MQD_BASE_ADDR_BASE_IDX', 'regCP_GFX_MQD_BASE_ADDR_HI',
'regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX', 'regCP_GFX_MQD_CONTROL',
'regCP_GFX_MQD_CONTROL_BASE_IDX', 'regCP_GFX_QUEUE_INDEX',
'regCP_GFX_QUEUE_INDEX_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE0_BASE0',
'regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE0_BASE1',
'regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE0_CNTL0',
'regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE0_CNTL1',
'regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE0_MASK0',
'regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE0_MASK1',
'regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE10_BASE0',
'regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE10_BASE1',
'regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE10_CNTL0',
'regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE10_CNTL1',
'regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE10_MASK0',
'regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE10_MASK1',
'regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE11_BASE0',
'regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE11_BASE1',
'regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE11_CNTL0',
'regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE11_CNTL1',
'regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE11_MASK0',
'regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE11_MASK1',
'regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE12_BASE0',
'regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE12_BASE1',
'regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE12_CNTL0',
'regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE12_CNTL1',
'regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE12_MASK0',
'regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE12_MASK1',
'regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE13_BASE0',
'regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE13_BASE1',
'regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE13_CNTL0',
'regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE13_CNTL1',
'regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE13_MASK0',
'regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE13_MASK1',
'regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE14_BASE0',
'regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE14_BASE1',
'regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE14_CNTL0',
'regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE14_CNTL1',
'regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE14_MASK0',
'regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE14_MASK1',
'regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE15_BASE0',
'regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE15_BASE1',
'regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE15_CNTL0',
'regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE15_CNTL1',
'regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE15_MASK0',
'regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE15_MASK1',
'regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE1_BASE0',
'regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE1_BASE1',
'regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE1_CNTL0',
'regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE1_CNTL1',
'regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE1_MASK0',
'regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE1_MASK1',
'regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE2_BASE0',
'regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE2_BASE1',
'regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE2_CNTL0',
'regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE2_CNTL1',
'regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE2_MASK0',
'regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE2_MASK1',
'regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE3_BASE0',
'regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE3_BASE1',
'regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE3_CNTL0',
'regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE3_CNTL1',
'regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE3_MASK0',
'regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE3_MASK1',
'regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE4_BASE0',
'regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE4_BASE1',
'regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE4_CNTL0',
'regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE4_CNTL1',
'regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE4_MASK0',
'regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE4_MASK1',
'regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE5_BASE0',
'regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE5_BASE1',
'regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE5_CNTL0',
'regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE5_CNTL1',
'regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE5_MASK0',
'regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE5_MASK1',
'regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE6_BASE0',
'regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE6_BASE1',
'regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE6_CNTL0',
'regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE6_CNTL1',
'regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE6_MASK0',
'regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE6_MASK1',
'regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE7_BASE0',
'regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE7_BASE1',
'regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE7_CNTL0',
'regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE7_CNTL1',
'regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE7_MASK0',
'regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE7_MASK1',
'regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE8_BASE0',
'regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE8_BASE1',
'regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE8_CNTL0',
'regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE8_CNTL1',
'regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE8_MASK0',
'regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE8_MASK1',
'regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE9_BASE0',
'regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE9_BASE1',
'regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE9_CNTL0',
'regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE9_CNTL1',
'regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE9_MASK0',
'regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX',
'regCP_GFX_RS64_DC_APERTURE9_MASK1',
'regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX',
'regCP_GFX_RS64_DC_BASE0_HI',
'regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX',
'regCP_GFX_RS64_DC_BASE0_LO',
'regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX',
'regCP_GFX_RS64_DC_BASE1_HI',
'regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX',
'regCP_GFX_RS64_DC_BASE1_LO',
'regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX',
'regCP_GFX_RS64_DC_BASE_CNTL',
'regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX',
'regCP_GFX_RS64_DC_OP_CNTL', 'regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX',
'regCP_GFX_RS64_DM_INDEX_ADDR',
'regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX',
'regCP_GFX_RS64_DM_INDEX_DATA',
'regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX', 'regCP_GFX_RS64_GP0_HI0',
'regCP_GFX_RS64_GP0_HI0_BASE_IDX', 'regCP_GFX_RS64_GP0_HI1',
'regCP_GFX_RS64_GP0_HI1_BASE_IDX', 'regCP_GFX_RS64_GP0_LO0',
'regCP_GFX_RS64_GP0_LO0_BASE_IDX', 'regCP_GFX_RS64_GP0_LO1',
'regCP_GFX_RS64_GP0_LO1_BASE_IDX', 'regCP_GFX_RS64_GP1_HI0',
'regCP_GFX_RS64_GP1_HI0_BASE_IDX', 'regCP_GFX_RS64_GP1_HI1',
'regCP_GFX_RS64_GP1_HI1_BASE_IDX', 'regCP_GFX_RS64_GP1_LO0',
'regCP_GFX_RS64_GP1_LO0_BASE_IDX', 'regCP_GFX_RS64_GP1_LO1',
'regCP_GFX_RS64_GP1_LO1_BASE_IDX', 'regCP_GFX_RS64_GP2_HI0',
'regCP_GFX_RS64_GP2_HI0_BASE_IDX', 'regCP_GFX_RS64_GP2_HI1',
'regCP_GFX_RS64_GP2_HI1_BASE_IDX', 'regCP_GFX_RS64_GP2_LO0',
'regCP_GFX_RS64_GP2_LO0_BASE_IDX', 'regCP_GFX_RS64_GP2_LO1',
'regCP_GFX_RS64_GP2_LO1_BASE_IDX', 'regCP_GFX_RS64_GP3_HI0',
'regCP_GFX_RS64_GP3_HI0_BASE_IDX', 'regCP_GFX_RS64_GP3_HI1',
'regCP_GFX_RS64_GP3_HI1_BASE_IDX', 'regCP_GFX_RS64_GP3_LO0',
'regCP_GFX_RS64_GP3_LO0_BASE_IDX', 'regCP_GFX_RS64_GP3_LO1',
'regCP_GFX_RS64_GP3_LO1_BASE_IDX', 'regCP_GFX_RS64_GP4_HI0',
'regCP_GFX_RS64_GP4_HI0_BASE_IDX', 'regCP_GFX_RS64_GP4_HI1',
'regCP_GFX_RS64_GP4_HI1_BASE_IDX', 'regCP_GFX_RS64_GP4_LO0',
'regCP_GFX_RS64_GP4_LO0_BASE_IDX', 'regCP_GFX_RS64_GP4_LO1',
'regCP_GFX_RS64_GP4_LO1_BASE_IDX', 'regCP_GFX_RS64_GP5_HI0',
'regCP_GFX_RS64_GP5_HI0_BASE_IDX', 'regCP_GFX_RS64_GP5_HI1',
'regCP_GFX_RS64_GP5_HI1_BASE_IDX', 'regCP_GFX_RS64_GP5_LO0',
'regCP_GFX_RS64_GP5_LO0_BASE_IDX', 'regCP_GFX_RS64_GP5_LO1',
'regCP_GFX_RS64_GP5_LO1_BASE_IDX', 'regCP_GFX_RS64_GP6_HI',
'regCP_GFX_RS64_GP6_HI_BASE_IDX', 'regCP_GFX_RS64_GP6_LO',
'regCP_GFX_RS64_GP6_LO_BASE_IDX', 'regCP_GFX_RS64_GP7_HI',
'regCP_GFX_RS64_GP7_HI_BASE_IDX', 'regCP_GFX_RS64_GP7_LO',
'regCP_GFX_RS64_GP7_LO_BASE_IDX', 'regCP_GFX_RS64_GP8_HI',
'regCP_GFX_RS64_GP8_HI_BASE_IDX', 'regCP_GFX_RS64_GP8_LO',
'regCP_GFX_RS64_GP8_LO_BASE_IDX', 'regCP_GFX_RS64_GP9_HI',
'regCP_GFX_RS64_GP9_HI_BASE_IDX', 'regCP_GFX_RS64_GP9_LO',
'regCP_GFX_RS64_GP9_LO_BASE_IDX', 'regCP_GFX_RS64_INSTR_PNTR0',
'regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX',
'regCP_GFX_RS64_INSTR_PNTR1',
'regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX',
'regCP_GFX_RS64_INTERRUPT0', 'regCP_GFX_RS64_INTERRUPT0_BASE_IDX',
'regCP_GFX_RS64_INTERRUPT1', 'regCP_GFX_RS64_INTERRUPT1_BASE_IDX',
'regCP_GFX_RS64_INTR_EN0', 'regCP_GFX_RS64_INTR_EN0_BASE_IDX',
'regCP_GFX_RS64_INTR_EN1', 'regCP_GFX_RS64_INTR_EN1_BASE_IDX',
'regCP_GFX_RS64_LOCAL_APERTURE',
'regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX',
'regCP_GFX_RS64_LOCAL_BASE0_HI',
'regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX',
'regCP_GFX_RS64_LOCAL_BASE0_LO',
'regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX',
'regCP_GFX_RS64_LOCAL_INSTR_APERTURE',
'regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX',
'regCP_GFX_RS64_LOCAL_INSTR_BASE_HI',
'regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX',
'regCP_GFX_RS64_LOCAL_INSTR_BASE_LO',
'regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX',
'regCP_GFX_RS64_LOCAL_INSTR_MASK_HI',
'regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX',
'regCP_GFX_RS64_LOCAL_INSTR_MASK_LO',
'regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX',
'regCP_GFX_RS64_LOCAL_MASK0_HI',
'regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX',
'regCP_GFX_RS64_LOCAL_MASK0_LO',
'regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX',
'regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE',
'regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX',
'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI',
'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX',
'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO',
'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX',
'regCP_GFX_RS64_MIBOUND_HI', 'regCP_GFX_RS64_MIBOUND_HI_BASE_IDX',
'regCP_GFX_RS64_MIBOUND_LO', 'regCP_GFX_RS64_MIBOUND_LO_BASE_IDX',
'regCP_GFX_RS64_MIP_HI0', 'regCP_GFX_RS64_MIP_HI0_BASE_IDX',
'regCP_GFX_RS64_MIP_HI1', 'regCP_GFX_RS64_MIP_HI1_BASE_IDX',
'regCP_GFX_RS64_MIP_LO0', 'regCP_GFX_RS64_MIP_LO0_BASE_IDX',
'regCP_GFX_RS64_MIP_LO1', 'regCP_GFX_RS64_MIP_LO1_BASE_IDX',
'regCP_GFX_RS64_MTIMECMP_HI0',
'regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX',
'regCP_GFX_RS64_MTIMECMP_HI1',
'regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX',
'regCP_GFX_RS64_MTIMECMP_LO0',
'regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX',
'regCP_GFX_RS64_MTIMECMP_LO1',
'regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX',
'regCP_GFX_RS64_PENDING_INTERRUPT0',
'regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX',
'regCP_GFX_RS64_PENDING_INTERRUPT1',
'regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX',
'regCP_GFX_RS64_PERFCOUNT_CNTL0',
'regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX',
'regCP_GFX_RS64_PERFCOUNT_CNTL1',
'regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX',
'regCP_GPU_TIMESTAMP_OFFSET_HI',
'regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX',
'regCP_GPU_TIMESTAMP_OFFSET_LO',
'regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX', 'regCP_GRBM_FREE_COUNT',
'regCP_GRBM_FREE_COUNT_BASE_IDX', 'regCP_HPD_MES_ROQ_OFFSETS',
'regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX', 'regCP_HPD_ROQ_OFFSETS',
'regCP_HPD_ROQ_OFFSETS_BASE_IDX', 'regCP_HPD_STATUS0',
'regCP_HPD_STATUS0_BASE_IDX', 'regCP_HPD_UTCL1_CNTL',
'regCP_HPD_UTCL1_CNTL_BASE_IDX', 'regCP_HPD_UTCL1_ERROR',
'regCP_HPD_UTCL1_ERROR_ADDR',
'regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX',
'regCP_HPD_UTCL1_ERROR_BASE_IDX', 'regCP_HQD_ACTIVE',
'regCP_HQD_ACTIVE_BASE_IDX', 'regCP_HQD_AQL_CONTROL',
'regCP_HQD_AQL_CONTROL_BASE_IDX', 'regCP_HQD_ATOMIC0_PREOP_HI',
'regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX',
'regCP_HQD_ATOMIC0_PREOP_LO',
'regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX',
'regCP_HQD_ATOMIC1_PREOP_HI',
'regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX',
'regCP_HQD_ATOMIC1_PREOP_LO',
'regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX',
'regCP_HQD_CNTL_STACK_OFFSET',
'regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX',
'regCP_HQD_CNTL_STACK_SIZE', 'regCP_HQD_CNTL_STACK_SIZE_BASE_IDX',
'regCP_HQD_CTX_SAVE_BASE_ADDR_HI',
'regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX',
'regCP_HQD_CTX_SAVE_BASE_ADDR_LO',
'regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX',
'regCP_HQD_CTX_SAVE_CONTROL',
'regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX', 'regCP_HQD_CTX_SAVE_SIZE',
'regCP_HQD_CTX_SAVE_SIZE_BASE_IDX',
'regCP_HQD_DDID_DELTA_RPT_COUNT',
'regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX',
'regCP_HQD_DDID_INFLIGHT_COUNT',
'regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX', 'regCP_HQD_DDID_RPTR',
'regCP_HQD_DDID_RPTR_BASE_IDX', 'regCP_HQD_DDID_WPTR',
'regCP_HQD_DDID_WPTR_BASE_IDX', 'regCP_HQD_DEQUEUE_REQUEST',
'regCP_HQD_DEQUEUE_REQUEST_BASE_IDX', 'regCP_HQD_DEQUEUE_STATUS',
'regCP_HQD_DEQUEUE_STATUS_BASE_IDX', 'regCP_HQD_DMA_OFFLOAD',
'regCP_HQD_DMA_OFFLOAD_BASE_IDX', 'regCP_HQD_EOP_BASE_ADDR',
'regCP_HQD_EOP_BASE_ADDR_BASE_IDX', 'regCP_HQD_EOP_BASE_ADDR_HI',
'regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX', 'regCP_HQD_EOP_CONTROL',
'regCP_HQD_EOP_CONTROL_BASE_IDX', 'regCP_HQD_EOP_EVENTS',
'regCP_HQD_EOP_EVENTS_BASE_IDX', 'regCP_HQD_EOP_RPTR',
'regCP_HQD_EOP_RPTR_BASE_IDX', 'regCP_HQD_EOP_WPTR',
'regCP_HQD_EOP_WPTR_BASE_IDX', 'regCP_HQD_EOP_WPTR_MEM',
'regCP_HQD_EOP_WPTR_MEM_BASE_IDX', 'regCP_HQD_ERROR',
'regCP_HQD_ERROR_BASE_IDX', 'regCP_HQD_GDS_RESOURCE_STATE',
'regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX', 'regCP_HQD_GFX_CONTROL',
'regCP_HQD_GFX_CONTROL_BASE_IDX', 'regCP_HQD_GFX_STATUS',
'regCP_HQD_GFX_STATUS_BASE_IDX', 'regCP_HQD_HQ_CONTROL0',
'regCP_HQD_HQ_CONTROL0_BASE_IDX', 'regCP_HQD_HQ_CONTROL1',
'regCP_HQD_HQ_CONTROL1_BASE_IDX', 'regCP_HQD_HQ_SCHEDULER0',
'regCP_HQD_HQ_SCHEDULER0_BASE_IDX', 'regCP_HQD_HQ_SCHEDULER1',
'regCP_HQD_HQ_SCHEDULER1_BASE_IDX', 'regCP_HQD_HQ_STATUS0',
'regCP_HQD_HQ_STATUS0_BASE_IDX', 'regCP_HQD_HQ_STATUS1',
'regCP_HQD_HQ_STATUS1_BASE_IDX', 'regCP_HQD_IB_BASE_ADDR',
'regCP_HQD_IB_BASE_ADDR_BASE_IDX', 'regCP_HQD_IB_BASE_ADDR_HI',
'regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX', 'regCP_HQD_IB_CONTROL',
'regCP_HQD_IB_CONTROL_BASE_IDX', 'regCP_HQD_IB_RPTR',
'regCP_HQD_IB_RPTR_BASE_IDX', 'regCP_HQD_IQ_RPTR',
'regCP_HQD_IQ_RPTR_BASE_IDX', 'regCP_HQD_IQ_TIMER',
'regCP_HQD_IQ_TIMER_BASE_IDX', 'regCP_HQD_MSG_TYPE',
'regCP_HQD_MSG_TYPE_BASE_IDX', 'regCP_HQD_OFFLOAD',
'regCP_HQD_OFFLOAD_BASE_IDX', 'regCP_HQD_PERSISTENT_STATE',
'regCP_HQD_PERSISTENT_STATE_BASE_IDX', 'regCP_HQD_PIPE_PRIORITY',
'regCP_HQD_PIPE_PRIORITY_BASE_IDX', 'regCP_HQD_PQ_BASE',
'regCP_HQD_PQ_BASE_BASE_IDX', 'regCP_HQD_PQ_BASE_HI',
'regCP_HQD_PQ_BASE_HI_BASE_IDX', 'regCP_HQD_PQ_CONTROL',
'regCP_HQD_PQ_CONTROL_BASE_IDX', 'regCP_HQD_PQ_DOORBELL_CONTROL',
'regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX', 'regCP_HQD_PQ_RPTR',
'regCP_HQD_PQ_RPTR_BASE_IDX', 'regCP_HQD_PQ_RPTR_REPORT_ADDR',
'regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX',
'regCP_HQD_PQ_RPTR_REPORT_ADDR_HI',
'regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX',
'regCP_HQD_PQ_WPTR_HI', 'regCP_HQD_PQ_WPTR_HI_BASE_IDX',
'regCP_HQD_PQ_WPTR_LO', 'regCP_HQD_PQ_WPTR_LO_BASE_IDX',
'regCP_HQD_PQ_WPTR_POLL_ADDR',
'regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX',
'regCP_HQD_PQ_WPTR_POLL_ADDR_HI',
'regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX', 'regCP_HQD_QUANTUM',
'regCP_HQD_QUANTUM_BASE_IDX', 'regCP_HQD_QUEUE_PRIORITY',
'regCP_HQD_QUEUE_PRIORITY_BASE_IDX', 'regCP_HQD_SEMA_CMD',
'regCP_HQD_SEMA_CMD_BASE_IDX',
'regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT',
'regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX',
'regCP_HQD_SUSPEND_CNTL_STACK_OFFSET',
'regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX',
'regCP_HQD_SUSPEND_WG_STATE_OFFSET',
'regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX', 'regCP_HQD_VMID',
'regCP_HQD_VMID_BASE_IDX', 'regCP_HQD_WG_STATE_OFFSET',
'regCP_HQD_WG_STATE_OFFSET_BASE_IDX', 'regCP_HYP_MEC1_UCODE_ADDR',
'regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX', 'regCP_HYP_MEC1_UCODE_DATA',
'regCP_HYP_MEC1_UCODE_DATA_BASE_IDX', 'regCP_HYP_MEC2_UCODE_ADDR',
'regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX', 'regCP_HYP_MEC2_UCODE_DATA',
'regCP_HYP_MEC2_UCODE_DATA_BASE_IDX', 'regCP_HYP_ME_UCODE_ADDR',
'regCP_HYP_ME_UCODE_ADDR_BASE_IDX', 'regCP_HYP_ME_UCODE_DATA',
'regCP_HYP_ME_UCODE_DATA_BASE_IDX', 'regCP_HYP_PFP_UCODE_ADDR',
'regCP_HYP_PFP_UCODE_ADDR_BASE_IDX', 'regCP_HYP_PFP_UCODE_DATA',
'regCP_HYP_PFP_UCODE_DATA_BASE_IDX', 'regCP_IB1_BASE_HI',
'regCP_IB1_BASE_HI_BASE_IDX', 'regCP_IB1_BASE_LO',
'regCP_IB1_BASE_LO_BASE_IDX', 'regCP_IB1_BUFSZ',
'regCP_IB1_BUFSZ_BASE_IDX', 'regCP_IB1_CMD_BUFSZ',
'regCP_IB1_CMD_BUFSZ_BASE_IDX', 'regCP_IB2_BASE_HI',
'regCP_IB2_BASE_HI_BASE_IDX', 'regCP_IB2_BASE_LO',
'regCP_IB2_BASE_LO_BASE_IDX', 'regCP_IB2_BUFSZ',
'regCP_IB2_BUFSZ_BASE_IDX', 'regCP_IB2_CMD_BUFSZ',
'regCP_IB2_CMD_BUFSZ_BASE_IDX', 'regCP_IB2_OFFSET',
'regCP_IB2_OFFSET_BASE_IDX', 'regCP_IB2_PREAMBLE_BEGIN',
'regCP_IB2_PREAMBLE_BEGIN_BASE_IDX', 'regCP_IB2_PREAMBLE_END',
'regCP_IB2_PREAMBLE_END_BASE_IDX', 'regCP_INDEX_BASE_ADDR',
'regCP_INDEX_BASE_ADDR_BASE_IDX', 'regCP_INDEX_BASE_ADDR_HI',
'regCP_INDEX_BASE_ADDR_HI_BASE_IDX', 'regCP_INDEX_TYPE',
'regCP_INDEX_TYPE_BASE_IDX', 'regCP_INT_CNTL',
'regCP_INT_CNTL_BASE_IDX', 'regCP_INT_CNTL_RING0',
'regCP_INT_CNTL_RING0_BASE_IDX', 'regCP_INT_CNTL_RING1',
'regCP_INT_CNTL_RING1_BASE_IDX', 'regCP_INT_STATUS',
'regCP_INT_STATUS_BASE_IDX', 'regCP_INT_STATUS_RING0',
'regCP_INT_STATUS_RING0_BASE_IDX', 'regCP_INT_STATUS_RING1',
'regCP_INT_STATUS_RING1_BASE_IDX', 'regCP_IQ_WAIT_TIME1',
'regCP_IQ_WAIT_TIME1_BASE_IDX', 'regCP_IQ_WAIT_TIME2',
'regCP_IQ_WAIT_TIME2_BASE_IDX', 'regCP_IQ_WAIT_TIME3',
'regCP_IQ_WAIT_TIME3_BASE_IDX', 'regCP_MAX_CONTEXT',
'regCP_MAX_CONTEXT_BASE_IDX', 'regCP_MAX_DRAW_COUNT',
'regCP_MAX_DRAW_COUNT_BASE_IDX', 'regCP_ME0_PIPE0_PRIORITY',
'regCP_ME0_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME0_PIPE0_VMID',
'regCP_ME0_PIPE0_VMID_BASE_IDX', 'regCP_ME0_PIPE1_PRIORITY',
'regCP_ME0_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME0_PIPE1_VMID',
'regCP_ME0_PIPE1_VMID_BASE_IDX', 'regCP_ME0_PIPE_PRIORITY_CNTS',
'regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX',
'regCP_ME1_PIPE0_INT_CNTL', 'regCP_ME1_PIPE0_INT_CNTL_BASE_IDX',
'regCP_ME1_PIPE0_INT_STATUS',
'regCP_ME1_PIPE0_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE0_PRIORITY',
'regCP_ME1_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE1_INT_CNTL',
'regCP_ME1_PIPE1_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE1_INT_STATUS',
'regCP_ME1_PIPE1_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE1_PRIORITY',
'regCP_ME1_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE2_INT_CNTL',
'regCP_ME1_PIPE2_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE2_INT_STATUS',
'regCP_ME1_PIPE2_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE2_PRIORITY',
'regCP_ME1_PIPE2_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE3_INT_CNTL',
'regCP_ME1_PIPE3_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE3_INT_STATUS',
'regCP_ME1_PIPE3_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE3_PRIORITY',
'regCP_ME1_PIPE3_PRIORITY_BASE_IDX',
'regCP_ME1_PIPE_PRIORITY_CNTS',
'regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX',
'regCP_ME2_PIPE0_INT_CNTL', 'regCP_ME2_PIPE0_INT_CNTL_BASE_IDX',
'regCP_ME2_PIPE0_INT_STATUS',
'regCP_ME2_PIPE0_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE0_PRIORITY',
'regCP_ME2_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE1_INT_CNTL',
'regCP_ME2_PIPE1_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE1_INT_STATUS',
'regCP_ME2_PIPE1_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE1_PRIORITY',
'regCP_ME2_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE2_INT_CNTL',
'regCP_ME2_PIPE2_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE2_INT_STATUS',
'regCP_ME2_PIPE2_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE2_PRIORITY',
'regCP_ME2_PIPE2_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE3_INT_CNTL',
'regCP_ME2_PIPE3_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE3_INT_STATUS',
'regCP_ME2_PIPE3_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE3_PRIORITY',
'regCP_ME2_PIPE3_PRIORITY_BASE_IDX',
'regCP_ME2_PIPE_PRIORITY_CNTS',
'regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX',
'regCP_MEC1_F32_INTERRUPT', 'regCP_MEC1_F32_INTERRUPT_BASE_IDX',
'regCP_MEC1_F32_INT_DIS', 'regCP_MEC1_F32_INT_DIS_BASE_IDX',
'regCP_MEC1_INSTR_PNTR', 'regCP_MEC1_INSTR_PNTR_BASE_IDX',
'regCP_MEC1_INTR_ROUTINE_START',
'regCP_MEC1_INTR_ROUTINE_START_BASE_IDX',
'regCP_MEC1_PRGRM_CNTR_START',
'regCP_MEC1_PRGRM_CNTR_START_BASE_IDX',
'regCP_MEC2_F32_INTERRUPT', 'regCP_MEC2_F32_INTERRUPT_BASE_IDX',
'regCP_MEC2_F32_INT_DIS', 'regCP_MEC2_F32_INT_DIS_BASE_IDX',
'regCP_MEC2_INSTR_PNTR', 'regCP_MEC2_INSTR_PNTR_BASE_IDX',
'regCP_MEC2_INTR_ROUTINE_START',
'regCP_MEC2_INTR_ROUTINE_START_BASE_IDX',
'regCP_MEC2_PRGRM_CNTR_START',
'regCP_MEC2_PRGRM_CNTR_START_BASE_IDX', 'regCP_MEC_CNTL',
'regCP_MEC_CNTL_BASE_IDX', 'regCP_MEC_DC_APERTURE0_BASE',
'regCP_MEC_DC_APERTURE0_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE0_CNTL',
'regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE0_MASK',
'regCP_MEC_DC_APERTURE0_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE10_BASE',
'regCP_MEC_DC_APERTURE10_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE10_CNTL',
'regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE10_MASK',
'regCP_MEC_DC_APERTURE10_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE11_BASE',
'regCP_MEC_DC_APERTURE11_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE11_CNTL',
'regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE11_MASK',
'regCP_MEC_DC_APERTURE11_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE12_BASE',
'regCP_MEC_DC_APERTURE12_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE12_CNTL',
'regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE12_MASK',
'regCP_MEC_DC_APERTURE12_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE13_BASE',
'regCP_MEC_DC_APERTURE13_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE13_CNTL',
'regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE13_MASK',
'regCP_MEC_DC_APERTURE13_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE14_BASE',
'regCP_MEC_DC_APERTURE14_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE14_CNTL',
'regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE14_MASK',
'regCP_MEC_DC_APERTURE14_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE15_BASE',
'regCP_MEC_DC_APERTURE15_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE15_CNTL',
'regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE15_MASK',
'regCP_MEC_DC_APERTURE15_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE1_BASE',
'regCP_MEC_DC_APERTURE1_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE1_CNTL',
'regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE1_MASK',
'regCP_MEC_DC_APERTURE1_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE2_BASE',
'regCP_MEC_DC_APERTURE2_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE2_CNTL',
'regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE2_MASK',
'regCP_MEC_DC_APERTURE2_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE3_BASE',
'regCP_MEC_DC_APERTURE3_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE3_CNTL',
'regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE3_MASK',
'regCP_MEC_DC_APERTURE3_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE4_BASE',
'regCP_MEC_DC_APERTURE4_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE4_CNTL',
'regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE4_MASK',
'regCP_MEC_DC_APERTURE4_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE5_BASE',
'regCP_MEC_DC_APERTURE5_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE5_CNTL',
'regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE5_MASK',
'regCP_MEC_DC_APERTURE5_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE6_BASE',
'regCP_MEC_DC_APERTURE6_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE6_CNTL',
'regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE6_MASK',
'regCP_MEC_DC_APERTURE6_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE7_BASE',
'regCP_MEC_DC_APERTURE7_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE7_CNTL',
'regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE7_MASK',
'regCP_MEC_DC_APERTURE7_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE8_BASE',
'regCP_MEC_DC_APERTURE8_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE8_CNTL',
'regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE8_MASK',
'regCP_MEC_DC_APERTURE8_MASK_BASE_IDX',
'regCP_MEC_DC_APERTURE9_BASE',
'regCP_MEC_DC_APERTURE9_BASE_BASE_IDX',
'regCP_MEC_DC_APERTURE9_CNTL',
'regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX',
'regCP_MEC_DC_APERTURE9_MASK',
'regCP_MEC_DC_APERTURE9_MASK_BASE_IDX', 'regCP_MEC_DC_BASE_CNTL',
'regCP_MEC_DC_BASE_CNTL_BASE_IDX', 'regCP_MEC_DC_BASE_HI',
'regCP_MEC_DC_BASE_HI_BASE_IDX', 'regCP_MEC_DC_BASE_LO',
'regCP_MEC_DC_BASE_LO_BASE_IDX', 'regCP_MEC_DC_OP_CNTL',
'regCP_MEC_DC_OP_CNTL_BASE_IDX', 'regCP_MEC_DM_INDEX_ADDR',
'regCP_MEC_DM_INDEX_ADDR_BASE_IDX', 'regCP_MEC_DM_INDEX_DATA',
'regCP_MEC_DM_INDEX_DATA_BASE_IDX',
'regCP_MEC_DOORBELL_RANGE_LOWER',
'regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX',
'regCP_MEC_DOORBELL_RANGE_UPPER',
'regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX', 'regCP_MEC_GP0_HI',
'regCP_MEC_GP0_HI_BASE_IDX', 'regCP_MEC_GP0_LO',
'regCP_MEC_GP0_LO_BASE_IDX', 'regCP_MEC_GP1_HI',
'regCP_MEC_GP1_HI_BASE_IDX', 'regCP_MEC_GP1_LO',
'regCP_MEC_GP1_LO_BASE_IDX', 'regCP_MEC_GP2_HI',
'regCP_MEC_GP2_HI_BASE_IDX', 'regCP_MEC_GP2_LO',
'regCP_MEC_GP2_LO_BASE_IDX', 'regCP_MEC_GP3_HI',
'regCP_MEC_GP3_HI_BASE_IDX', 'regCP_MEC_GP3_LO',
'regCP_MEC_GP3_LO_BASE_IDX', 'regCP_MEC_GP4_HI',
'regCP_MEC_GP4_HI_BASE_IDX', 'regCP_MEC_GP4_LO',
'regCP_MEC_GP4_LO_BASE_IDX', 'regCP_MEC_GP5_HI',
'regCP_MEC_GP5_HI_BASE_IDX', 'regCP_MEC_GP5_LO',
'regCP_MEC_GP5_LO_BASE_IDX', 'regCP_MEC_GP6_HI',
'regCP_MEC_GP6_HI_BASE_IDX', 'regCP_MEC_GP6_LO',
'regCP_MEC_GP6_LO_BASE_IDX', 'regCP_MEC_GP7_HI',
'regCP_MEC_GP7_HI_BASE_IDX', 'regCP_MEC_GP7_LO',
'regCP_MEC_GP7_LO_BASE_IDX', 'regCP_MEC_GP8_HI',
'regCP_MEC_GP8_HI_BASE_IDX', 'regCP_MEC_GP8_LO',
'regCP_MEC_GP8_LO_BASE_IDX', 'regCP_MEC_GP9_HI',
'regCP_MEC_GP9_HI_BASE_IDX', 'regCP_MEC_GP9_LO',
'regCP_MEC_GP9_LO_BASE_IDX', 'regCP_MEC_ISA_CNTL',
'regCP_MEC_ISA_CNTL_BASE_IDX', 'regCP_MEC_JT_STAT',
'regCP_MEC_JT_STAT_BASE_IDX', 'regCP_MEC_LOCAL_APERTURE',
'regCP_MEC_LOCAL_APERTURE_BASE_IDX', 'regCP_MEC_LOCAL_BASE0_HI',
'regCP_MEC_LOCAL_BASE0_HI_BASE_IDX', 'regCP_MEC_LOCAL_BASE0_LO',
'regCP_MEC_LOCAL_BASE0_LO_BASE_IDX',
'regCP_MEC_LOCAL_INSTR_APERTURE',
'regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX',
'regCP_MEC_LOCAL_INSTR_BASE_HI',
'regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX',
'regCP_MEC_LOCAL_INSTR_BASE_LO',
'regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX',
'regCP_MEC_LOCAL_INSTR_MASK_HI',
'regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX',
'regCP_MEC_LOCAL_INSTR_MASK_LO',
'regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX',
'regCP_MEC_LOCAL_MASK0_HI', 'regCP_MEC_LOCAL_MASK0_HI_BASE_IDX',
'regCP_MEC_LOCAL_MASK0_LO', 'regCP_MEC_LOCAL_MASK0_LO_BASE_IDX',
'regCP_MEC_LOCAL_SCRATCH_APERTURE',
'regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX',
'regCP_MEC_LOCAL_SCRATCH_BASE_HI',
'regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX',
'regCP_MEC_LOCAL_SCRATCH_BASE_LO',
'regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX', 'regCP_MEC_MDBASE_HI',
'regCP_MEC_MDBASE_HI_BASE_IDX', 'regCP_MEC_MDBASE_LO',
'regCP_MEC_MDBASE_LO_BASE_IDX', 'regCP_MEC_MDBOUND_HI',
'regCP_MEC_MDBOUND_HI_BASE_IDX', 'regCP_MEC_MDBOUND_LO',
'regCP_MEC_MDBOUND_LO_BASE_IDX', 'regCP_MEC_ME1_HEADER_DUMP',
'regCP_MEC_ME1_HEADER_DUMP_BASE_IDX', 'regCP_MEC_ME1_UCODE_ADDR',
'regCP_MEC_ME1_UCODE_ADDR_BASE_IDX', 'regCP_MEC_ME1_UCODE_DATA',
'regCP_MEC_ME1_UCODE_DATA_BASE_IDX', 'regCP_MEC_ME2_HEADER_DUMP',
'regCP_MEC_ME2_HEADER_DUMP_BASE_IDX', 'regCP_MEC_ME2_UCODE_ADDR',
'regCP_MEC_ME2_UCODE_ADDR_BASE_IDX', 'regCP_MEC_ME2_UCODE_DATA',
'regCP_MEC_ME2_UCODE_DATA_BASE_IDX', 'regCP_MEC_MIBOUND_HI',
'regCP_MEC_MIBOUND_HI_BASE_IDX', 'regCP_MEC_MIBOUND_LO',
'regCP_MEC_MIBOUND_LO_BASE_IDX', 'regCP_MEC_MIE_HI',
'regCP_MEC_MIE_HI_BASE_IDX', 'regCP_MEC_MIE_LO',
'regCP_MEC_MIE_LO_BASE_IDX', 'regCP_MEC_MIP_HI',
'regCP_MEC_MIP_HI_BASE_IDX', 'regCP_MEC_MIP_LO',
'regCP_MEC_MIP_LO_BASE_IDX', 'regCP_MEC_MTIMECMP_HI',
'regCP_MEC_MTIMECMP_HI_BASE_IDX', 'regCP_MEC_MTIMECMP_LO',
'regCP_MEC_MTIMECMP_LO_BASE_IDX', 'regCP_MEC_MTVEC_HI',
'regCP_MEC_MTVEC_HI_BASE_IDX', 'regCP_MEC_MTVEC_LO',
'regCP_MEC_MTVEC_LO_BASE_IDX', 'regCP_MEC_RS64_CNTL',
'regCP_MEC_RS64_CNTL_BASE_IDX', 'regCP_MEC_RS64_INSTR_PNTR',
'regCP_MEC_RS64_INSTR_PNTR_BASE_IDX', 'regCP_MEC_RS64_INTERRUPT',
'regCP_MEC_RS64_INTERRUPT_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_16',
'regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_17',
'regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_18',
'regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_19',
'regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_20',
'regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_21',
'regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_22',
'regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_23',
'regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_24',
'regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_25',
'regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_26',
'regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_27',
'regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_28',
'regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_29',
'regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_30',
'regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX',
'regCP_MEC_RS64_INTERRUPT_DATA_31',
'regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX',
'regCP_MEC_RS64_PENDING_INTERRUPT',
'regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX',
'regCP_MEC_RS64_PERFCOUNT_CNTL',
'regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX',
'regCP_MEC_RS64_PRGRM_CNTR_START',
'regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX',
'regCP_MEC_RS64_PRGRM_CNTR_START_HI',
'regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_MEQ_AVAIL',
'regCP_MEQ_AVAIL_BASE_IDX', 'regCP_MEQ_STAT',
'regCP_MEQ_STAT_BASE_IDX', 'regCP_MEQ_THRESHOLDS',
'regCP_MEQ_THRESHOLDS_BASE_IDX', 'regCP_MES_CNTL',
'regCP_MES_CNTL_BASE_IDX', 'regCP_MES_DC_APERTURE0_BASE',
'regCP_MES_DC_APERTURE0_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE0_CNTL',
'regCP_MES_DC_APERTURE0_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE0_MASK',
'regCP_MES_DC_APERTURE0_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE10_BASE',
'regCP_MES_DC_APERTURE10_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE10_CNTL',
'regCP_MES_DC_APERTURE10_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE10_MASK',
'regCP_MES_DC_APERTURE10_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE11_BASE',
'regCP_MES_DC_APERTURE11_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE11_CNTL',
'regCP_MES_DC_APERTURE11_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE11_MASK',
'regCP_MES_DC_APERTURE11_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE12_BASE',
'regCP_MES_DC_APERTURE12_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE12_CNTL',
'regCP_MES_DC_APERTURE12_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE12_MASK',
'regCP_MES_DC_APERTURE12_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE13_BASE',
'regCP_MES_DC_APERTURE13_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE13_CNTL',
'regCP_MES_DC_APERTURE13_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE13_MASK',
'regCP_MES_DC_APERTURE13_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE14_BASE',
'regCP_MES_DC_APERTURE14_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE14_CNTL',
'regCP_MES_DC_APERTURE14_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE14_MASK',
'regCP_MES_DC_APERTURE14_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE15_BASE',
'regCP_MES_DC_APERTURE15_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE15_CNTL',
'regCP_MES_DC_APERTURE15_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE15_MASK',
'regCP_MES_DC_APERTURE15_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE1_BASE',
'regCP_MES_DC_APERTURE1_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE1_CNTL',
'regCP_MES_DC_APERTURE1_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE1_MASK',
'regCP_MES_DC_APERTURE1_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE2_BASE',
'regCP_MES_DC_APERTURE2_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE2_CNTL',
'regCP_MES_DC_APERTURE2_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE2_MASK',
'regCP_MES_DC_APERTURE2_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE3_BASE',
'regCP_MES_DC_APERTURE3_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE3_CNTL',
'regCP_MES_DC_APERTURE3_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE3_MASK',
'regCP_MES_DC_APERTURE3_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE4_BASE',
'regCP_MES_DC_APERTURE4_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE4_CNTL',
'regCP_MES_DC_APERTURE4_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE4_MASK',
'regCP_MES_DC_APERTURE4_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE5_BASE',
'regCP_MES_DC_APERTURE5_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE5_CNTL',
'regCP_MES_DC_APERTURE5_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE5_MASK',
'regCP_MES_DC_APERTURE5_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE6_BASE',
'regCP_MES_DC_APERTURE6_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE6_CNTL',
'regCP_MES_DC_APERTURE6_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE6_MASK',
'regCP_MES_DC_APERTURE6_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE7_BASE',
'regCP_MES_DC_APERTURE7_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE7_CNTL',
'regCP_MES_DC_APERTURE7_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE7_MASK',
'regCP_MES_DC_APERTURE7_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE8_BASE',
'regCP_MES_DC_APERTURE8_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE8_CNTL',
'regCP_MES_DC_APERTURE8_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE8_MASK',
'regCP_MES_DC_APERTURE8_MASK_BASE_IDX',
'regCP_MES_DC_APERTURE9_BASE',
'regCP_MES_DC_APERTURE9_BASE_BASE_IDX',
'regCP_MES_DC_APERTURE9_CNTL',
'regCP_MES_DC_APERTURE9_CNTL_BASE_IDX',
'regCP_MES_DC_APERTURE9_MASK',
'regCP_MES_DC_APERTURE9_MASK_BASE_IDX', 'regCP_MES_DC_BASE_CNTL',
'regCP_MES_DC_BASE_CNTL_BASE_IDX', 'regCP_MES_DC_BASE_HI',
'regCP_MES_DC_BASE_HI_BASE_IDX', 'regCP_MES_DC_BASE_LO',
'regCP_MES_DC_BASE_LO_BASE_IDX', 'regCP_MES_DC_OP_CNTL',
'regCP_MES_DC_OP_CNTL_BASE_IDX',
'regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR',
'regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX',
'regCP_MES_DM_INDEX_ADDR', 'regCP_MES_DM_INDEX_ADDR_BASE_IDX',
'regCP_MES_DM_INDEX_DATA', 'regCP_MES_DM_INDEX_DATA_BASE_IDX',
'regCP_MES_DOORBELL_CONTROL1',
'regCP_MES_DOORBELL_CONTROL1_BASE_IDX',
'regCP_MES_DOORBELL_CONTROL2',
'regCP_MES_DOORBELL_CONTROL2_BASE_IDX',
'regCP_MES_DOORBELL_CONTROL3',
'regCP_MES_DOORBELL_CONTROL3_BASE_IDX',
'regCP_MES_DOORBELL_CONTROL4',
'regCP_MES_DOORBELL_CONTROL4_BASE_IDX',
'regCP_MES_DOORBELL_CONTROL5',
'regCP_MES_DOORBELL_CONTROL5_BASE_IDX',
'regCP_MES_DOORBELL_CONTROL6',
'regCP_MES_DOORBELL_CONTROL6_BASE_IDX', 'regCP_MES_GP0_HI',
'regCP_MES_GP0_HI_BASE_IDX', 'regCP_MES_GP0_LO',
'regCP_MES_GP0_LO_BASE_IDX', 'regCP_MES_GP1_HI',
'regCP_MES_GP1_HI_BASE_IDX', 'regCP_MES_GP1_LO',
'regCP_MES_GP1_LO_BASE_IDX', 'regCP_MES_GP2_HI',
'regCP_MES_GP2_HI_BASE_IDX', 'regCP_MES_GP2_LO',
'regCP_MES_GP2_LO_BASE_IDX', 'regCP_MES_GP3_HI',
'regCP_MES_GP3_HI_BASE_IDX', 'regCP_MES_GP3_LO',
'regCP_MES_GP3_LO_BASE_IDX', 'regCP_MES_GP4_HI',
'regCP_MES_GP4_HI_BASE_IDX', 'regCP_MES_GP4_LO',
'regCP_MES_GP4_LO_BASE_IDX', 'regCP_MES_GP5_HI',
'regCP_MES_GP5_HI_BASE_IDX', 'regCP_MES_GP5_LO',
'regCP_MES_GP5_LO_BASE_IDX', 'regCP_MES_GP6_HI',
'regCP_MES_GP6_HI_BASE_IDX', 'regCP_MES_GP6_LO',
'regCP_MES_GP6_LO_BASE_IDX', 'regCP_MES_GP7_HI',
'regCP_MES_GP7_HI_BASE_IDX', 'regCP_MES_GP7_LO',
'regCP_MES_GP7_LO_BASE_IDX', 'regCP_MES_GP8_HI',
'regCP_MES_GP8_HI_BASE_IDX', 'regCP_MES_GP8_LO',
'regCP_MES_GP8_LO_BASE_IDX', 'regCP_MES_GP9_HI',
'regCP_MES_GP9_HI_BASE_IDX', 'regCP_MES_GP9_LO',
'regCP_MES_GP9_LO_BASE_IDX', 'regCP_MES_HEADER_DUMP',
'regCP_MES_HEADER_DUMP_BASE_IDX', 'regCP_MES_IC_BASE_CNTL',
'regCP_MES_IC_BASE_CNTL_BASE_IDX', 'regCP_MES_IC_BASE_HI',
'regCP_MES_IC_BASE_HI_BASE_IDX', 'regCP_MES_IC_BASE_LO',
'regCP_MES_IC_BASE_LO_BASE_IDX', 'regCP_MES_IC_OP_CNTL',
'regCP_MES_IC_OP_CNTL_BASE_IDX', 'regCP_MES_INSTR_PNTR',
'regCP_MES_INSTR_PNTR_BASE_IDX', 'regCP_MES_INTERRUPT',
'regCP_MES_INTERRUPT_BASE_IDX', 'regCP_MES_INTERRUPT_DATA_16',
'regCP_MES_INTERRUPT_DATA_16_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_17',
'regCP_MES_INTERRUPT_DATA_17_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_18',
'regCP_MES_INTERRUPT_DATA_18_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_19',
'regCP_MES_INTERRUPT_DATA_19_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_20',
'regCP_MES_INTERRUPT_DATA_20_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_21',
'regCP_MES_INTERRUPT_DATA_21_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_22',
'regCP_MES_INTERRUPT_DATA_22_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_23',
'regCP_MES_INTERRUPT_DATA_23_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_24',
'regCP_MES_INTERRUPT_DATA_24_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_25',
'regCP_MES_INTERRUPT_DATA_25_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_26',
'regCP_MES_INTERRUPT_DATA_26_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_27',
'regCP_MES_INTERRUPT_DATA_27_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_28',
'regCP_MES_INTERRUPT_DATA_28_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_29',
'regCP_MES_INTERRUPT_DATA_29_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_30',
'regCP_MES_INTERRUPT_DATA_30_BASE_IDX',
'regCP_MES_INTERRUPT_DATA_31',
'regCP_MES_INTERRUPT_DATA_31_BASE_IDX',
'regCP_MES_INTR_ROUTINE_START',
'regCP_MES_INTR_ROUTINE_START_BASE_IDX',
'regCP_MES_INTR_ROUTINE_START_HI',
'regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX',
'regCP_MES_LOCAL_APERTURE', 'regCP_MES_LOCAL_APERTURE_BASE_IDX',
'regCP_MES_LOCAL_BASE0_HI', 'regCP_MES_LOCAL_BASE0_HI_BASE_IDX',
'regCP_MES_LOCAL_BASE0_LO', 'regCP_MES_LOCAL_BASE0_LO_BASE_IDX',
'regCP_MES_LOCAL_INSTR_APERTURE',
'regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX',
'regCP_MES_LOCAL_INSTR_BASE_HI',
'regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX',
'regCP_MES_LOCAL_INSTR_BASE_LO',
'regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX',
'regCP_MES_LOCAL_INSTR_MASK_HI',
'regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX',
'regCP_MES_LOCAL_INSTR_MASK_LO',
'regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX',
'regCP_MES_LOCAL_MASK0_HI', 'regCP_MES_LOCAL_MASK0_HI_BASE_IDX',
'regCP_MES_LOCAL_MASK0_LO', 'regCP_MES_LOCAL_MASK0_LO_BASE_IDX',
'regCP_MES_LOCAL_SCRATCH_APERTURE',
'regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX',
'regCP_MES_LOCAL_SCRATCH_BASE_HI',
'regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX',
'regCP_MES_LOCAL_SCRATCH_BASE_LO',
'regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX',
'regCP_MES_MARCHID_HI', 'regCP_MES_MARCHID_HI_BASE_IDX',
'regCP_MES_MARCHID_LO', 'regCP_MES_MARCHID_LO_BASE_IDX',
'regCP_MES_MBADADDR_HI', 'regCP_MES_MBADADDR_HI_BASE_IDX',
'regCP_MES_MBADADDR_LO', 'regCP_MES_MBADADDR_LO_BASE_IDX',
'regCP_MES_MCAUSE_HI', 'regCP_MES_MCAUSE_HI_BASE_IDX',
'regCP_MES_MCAUSE_LO', 'regCP_MES_MCAUSE_LO_BASE_IDX',
'regCP_MES_MCYCLE_HI', 'regCP_MES_MCYCLE_HI_BASE_IDX',
'regCP_MES_MCYCLE_LO', 'regCP_MES_MCYCLE_LO_BASE_IDX',
'regCP_MES_MDBASE_HI', 'regCP_MES_MDBASE_HI_BASE_IDX',
'regCP_MES_MDBASE_LO', 'regCP_MES_MDBASE_LO_BASE_IDX',
'regCP_MES_MDBOUND_HI', 'regCP_MES_MDBOUND_HI_BASE_IDX',
'regCP_MES_MDBOUND_LO', 'regCP_MES_MDBOUND_LO_BASE_IDX',
'regCP_MES_MEPC_HI', 'regCP_MES_MEPC_HI_BASE_IDX',
'regCP_MES_MEPC_LO', 'regCP_MES_MEPC_LO_BASE_IDX',
'regCP_MES_MHARTID_HI', 'regCP_MES_MHARTID_HI_BASE_IDX',
'regCP_MES_MHARTID_LO', 'regCP_MES_MHARTID_LO_BASE_IDX',
'regCP_MES_MIBASE_HI', 'regCP_MES_MIBASE_HI_BASE_IDX',
'regCP_MES_MIBASE_LO', 'regCP_MES_MIBASE_LO_BASE_IDX',
'regCP_MES_MIBOUND_HI', 'regCP_MES_MIBOUND_HI_BASE_IDX',
'regCP_MES_MIBOUND_LO', 'regCP_MES_MIBOUND_LO_BASE_IDX',
'regCP_MES_MIE_HI', 'regCP_MES_MIE_HI_BASE_IDX',
'regCP_MES_MIE_LO', 'regCP_MES_MIE_LO_BASE_IDX',
'regCP_MES_MIMPID_HI', 'regCP_MES_MIMPID_HI_BASE_IDX',
'regCP_MES_MIMPID_LO', 'regCP_MES_MIMPID_LO_BASE_IDX',
'regCP_MES_MINSTRET_HI', 'regCP_MES_MINSTRET_HI_BASE_IDX',
'regCP_MES_MINSTRET_LO', 'regCP_MES_MINSTRET_LO_BASE_IDX',
'regCP_MES_MIP_HI', 'regCP_MES_MIP_HI_BASE_IDX',
'regCP_MES_MIP_LO', 'regCP_MES_MIP_LO_BASE_IDX',
'regCP_MES_MISA_HI', 'regCP_MES_MISA_HI_BASE_IDX',
'regCP_MES_MISA_LO', 'regCP_MES_MISA_LO_BASE_IDX',
'regCP_MES_MSCRATCH_HI', 'regCP_MES_MSCRATCH_HI_BASE_IDX',
'regCP_MES_MSCRATCH_LO', 'regCP_MES_MSCRATCH_LO_BASE_IDX',
'regCP_MES_MSTATUS_HI', 'regCP_MES_MSTATUS_HI_BASE_IDX',
'regCP_MES_MSTATUS_LO', 'regCP_MES_MSTATUS_LO_BASE_IDX',
'regCP_MES_MTIMECMP_HI', 'regCP_MES_MTIMECMP_HI_BASE_IDX',
'regCP_MES_MTIMECMP_LO', 'regCP_MES_MTIMECMP_LO_BASE_IDX',
'regCP_MES_MTIME_HI', 'regCP_MES_MTIME_HI_BASE_IDX',
'regCP_MES_MTIME_LO', 'regCP_MES_MTIME_LO_BASE_IDX',
'regCP_MES_MTVEC_HI', 'regCP_MES_MTVEC_HI_BASE_IDX',
'regCP_MES_MTVEC_LO', 'regCP_MES_MTVEC_LO_BASE_IDX',
'regCP_MES_MVENDORID_HI', 'regCP_MES_MVENDORID_HI_BASE_IDX',
'regCP_MES_MVENDORID_LO', 'regCP_MES_MVENDORID_LO_BASE_IDX',
'regCP_MES_PENDING_INTERRUPT',
'regCP_MES_PENDING_INTERRUPT_BASE_IDX',
'regCP_MES_PERFCOUNT_CNTL', 'regCP_MES_PERFCOUNT_CNTL_BASE_IDX',
'regCP_MES_PIPE0_PRIORITY', 'regCP_MES_PIPE0_PRIORITY_BASE_IDX',
'regCP_MES_PIPE1_PRIORITY', 'regCP_MES_PIPE1_PRIORITY_BASE_IDX',
'regCP_MES_PIPE2_PRIORITY', 'regCP_MES_PIPE2_PRIORITY_BASE_IDX',
'regCP_MES_PIPE3_PRIORITY', 'regCP_MES_PIPE3_PRIORITY_BASE_IDX',
'regCP_MES_PIPE_PRIORITY_CNTS',
'regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX',
'regCP_MES_PRGRM_CNTR_START',
'regCP_MES_PRGRM_CNTR_START_BASE_IDX',
'regCP_MES_PRGRM_CNTR_START_HI',
'regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX',
'regCP_MES_PROCESS_QUANTUM_PIPE0',
'regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX',
'regCP_MES_PROCESS_QUANTUM_PIPE1',
'regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX',
'regCP_MES_SCRATCH_DATA', 'regCP_MES_SCRATCH_DATA_BASE_IDX',
'regCP_MES_SCRATCH_INDEX', 'regCP_MES_SCRATCH_INDEX_BASE_IDX',
'regCP_ME_ATOMIC_PREOP_HI', 'regCP_ME_ATOMIC_PREOP_HI_BASE_IDX',
'regCP_ME_ATOMIC_PREOP_LO', 'regCP_ME_ATOMIC_PREOP_LO_BASE_IDX',
'regCP_ME_CNTL', 'regCP_ME_CNTL_BASE_IDX', 'regCP_ME_COHER_BASE',
'regCP_ME_COHER_BASE_BASE_IDX', 'regCP_ME_COHER_BASE_HI',
'regCP_ME_COHER_BASE_HI_BASE_IDX', 'regCP_ME_COHER_CNTL',
'regCP_ME_COHER_CNTL_BASE_IDX', 'regCP_ME_COHER_SIZE',
'regCP_ME_COHER_SIZE_BASE_IDX', 'regCP_ME_COHER_SIZE_HI',
'regCP_ME_COHER_SIZE_HI_BASE_IDX', 'regCP_ME_COHER_STATUS',
'regCP_ME_COHER_STATUS_BASE_IDX', 'regCP_ME_F32_INTERRUPT',
'regCP_ME_F32_INTERRUPT_BASE_IDX',
'regCP_ME_GDS_ATOMIC0_PREOP_HI',
'regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX',
'regCP_ME_GDS_ATOMIC0_PREOP_LO',
'regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX',
'regCP_ME_GDS_ATOMIC1_PREOP_HI',
'regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX',
'regCP_ME_GDS_ATOMIC1_PREOP_LO',
'regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'regCP_ME_HEADER_DUMP',
'regCP_ME_HEADER_DUMP_BASE_IDX', 'regCP_ME_IC_BASE_CNTL',
'regCP_ME_IC_BASE_CNTL_BASE_IDX', 'regCP_ME_IC_BASE_HI',
'regCP_ME_IC_BASE_HI_BASE_IDX', 'regCP_ME_IC_BASE_LO',
'regCP_ME_IC_BASE_LO_BASE_IDX', 'regCP_ME_IC_OP_CNTL',
'regCP_ME_IC_OP_CNTL_BASE_IDX', 'regCP_ME_INSTR_PNTR',
'regCP_ME_INSTR_PNTR_BASE_IDX', 'regCP_ME_INTR_ROUTINE_START',
'regCP_ME_INTR_ROUTINE_START_BASE_IDX',
'regCP_ME_INTR_ROUTINE_START_HI',
'regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX', 'regCP_ME_MC_RADDR_HI',
'regCP_ME_MC_RADDR_HI_BASE_IDX', 'regCP_ME_MC_RADDR_LO',
'regCP_ME_MC_RADDR_LO_BASE_IDX', 'regCP_ME_MC_WADDR_HI',
'regCP_ME_MC_WADDR_HI_BASE_IDX', 'regCP_ME_MC_WADDR_LO',
'regCP_ME_MC_WADDR_LO_BASE_IDX', 'regCP_ME_MC_WDATA_HI',
'regCP_ME_MC_WDATA_HI_BASE_IDX', 'regCP_ME_MC_WDATA_LO',
'regCP_ME_MC_WDATA_LO_BASE_IDX', 'regCP_ME_PREEMPTION',
'regCP_ME_PREEMPTION_BASE_IDX', 'regCP_ME_PRGRM_CNTR_START',
'regCP_ME_PRGRM_CNTR_START_BASE_IDX',
'regCP_ME_PRGRM_CNTR_START_HI',
'regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_ME_RAM_DATA',
'regCP_ME_RAM_DATA_BASE_IDX', 'regCP_ME_RAM_RADDR',
'regCP_ME_RAM_RADDR_BASE_IDX', 'regCP_ME_RAM_WADDR',
'regCP_ME_RAM_WADDR_BASE_IDX', 'regCP_ME_SDMA_CS',
'regCP_ME_SDMA_CS_BASE_IDX', 'regCP_MQD_BASE_ADDR',
'regCP_MQD_BASE_ADDR_BASE_IDX', 'regCP_MQD_BASE_ADDR_HI',
'regCP_MQD_BASE_ADDR_HI_BASE_IDX', 'regCP_MQD_CONTROL',
'regCP_MQD_CONTROL_BASE_IDX', 'regCP_PA_CINVOC_COUNT_HI',
'regCP_PA_CINVOC_COUNT_HI_BASE_IDX', 'regCP_PA_CINVOC_COUNT_LO',
'regCP_PA_CINVOC_COUNT_LO_BASE_IDX', 'regCP_PA_CPRIM_COUNT_HI',
'regCP_PA_CPRIM_COUNT_HI_BASE_IDX', 'regCP_PA_CPRIM_COUNT_LO',
'regCP_PA_CPRIM_COUNT_LO_BASE_IDX', 'regCP_PA_MSPRIM_COUNT_HI',
'regCP_PA_MSPRIM_COUNT_HI_BASE_IDX', 'regCP_PA_MSPRIM_COUNT_LO',
'regCP_PA_MSPRIM_COUNT_LO_BASE_IDX', 'regCP_PERFMON_CNTL',
'regCP_PERFMON_CNTL_BASE_IDX', 'regCP_PERFMON_CNTX_CNTL',
'regCP_PERFMON_CNTX_CNTL_BASE_IDX', 'regCP_PFP_ATOMIC_PREOP_HI',
'regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX', 'regCP_PFP_ATOMIC_PREOP_LO',
'regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX',
'regCP_PFP_COMPLETION_STATUS',
'regCP_PFP_COMPLETION_STATUS_BASE_IDX', 'regCP_PFP_F32_INTERRUPT',
'regCP_PFP_F32_INTERRUPT_BASE_IDX',
'regCP_PFP_GDS_ATOMIC0_PREOP_HI',
'regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX',
'regCP_PFP_GDS_ATOMIC0_PREOP_LO',
'regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX',
'regCP_PFP_GDS_ATOMIC1_PREOP_HI',
'regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX',
'regCP_PFP_GDS_ATOMIC1_PREOP_LO',
'regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX',
'regCP_PFP_HEADER_DUMP', 'regCP_PFP_HEADER_DUMP_BASE_IDX',
'regCP_PFP_IB_CONTROL', 'regCP_PFP_IB_CONTROL_BASE_IDX',
'regCP_PFP_IC_BASE_CNTL', 'regCP_PFP_IC_BASE_CNTL_BASE_IDX',
'regCP_PFP_IC_BASE_HI', 'regCP_PFP_IC_BASE_HI_BASE_IDX',
'regCP_PFP_IC_BASE_LO', 'regCP_PFP_IC_BASE_LO_BASE_IDX',
'regCP_PFP_IC_OP_CNTL', 'regCP_PFP_IC_OP_CNTL_BASE_IDX',
'regCP_PFP_INSTR_PNTR', 'regCP_PFP_INSTR_PNTR_BASE_IDX',
'regCP_PFP_INTR_ROUTINE_START',
'regCP_PFP_INTR_ROUTINE_START_BASE_IDX',
'regCP_PFP_INTR_ROUTINE_START_HI',
'regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX', 'regCP_PFP_JT_STAT',
'regCP_PFP_JT_STAT_BASE_IDX', 'regCP_PFP_LOAD_CONTROL',
'regCP_PFP_LOAD_CONTROL_BASE_IDX', 'regCP_PFP_METADATA_BASE_ADDR',
'regCP_PFP_METADATA_BASE_ADDR_BASE_IDX',
'regCP_PFP_METADATA_BASE_ADDR_HI',
'regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX',
'regCP_PFP_PRGRM_CNTR_START',
'regCP_PFP_PRGRM_CNTR_START_BASE_IDX',
'regCP_PFP_PRGRM_CNTR_START_HI',
'regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_PFP_SDMA_CS',
'regCP_PFP_SDMA_CS_BASE_IDX', 'regCP_PFP_UCODE_ADDR',
'regCP_PFP_UCODE_ADDR_BASE_IDX', 'regCP_PFP_UCODE_DATA',
'regCP_PFP_UCODE_DATA_BASE_IDX', 'regCP_PIPEID',
'regCP_PIPEID_BASE_IDX', 'regCP_PIPE_STATS_ADDR_HI',
'regCP_PIPE_STATS_ADDR_HI_BASE_IDX', 'regCP_PIPE_STATS_ADDR_LO',
'regCP_PIPE_STATS_ADDR_LO_BASE_IDX', 'regCP_PIPE_STATS_CONTROL',
'regCP_PIPE_STATS_CONTROL_BASE_IDX', 'regCP_PQ_STATUS',
'regCP_PQ_STATUS_BASE_IDX', 'regCP_PQ_WPTR_POLL_CNTL',
'regCP_PQ_WPTR_POLL_CNTL1', 'regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX',
'regCP_PQ_WPTR_POLL_CNTL_BASE_IDX', 'regCP_PRED_NOT_VISIBLE',
'regCP_PRED_NOT_VISIBLE_BASE_IDX', 'regCP_PRIV_VIOLATION_ADDR',
'regCP_PRIV_VIOLATION_ADDR_BASE_IDX', 'regCP_PROCESS_QUANTUM',
'regCP_PROCESS_QUANTUM_BASE_IDX', 'regCP_PWR_CNTL',
'regCP_PWR_CNTL_BASE_IDX', 'regCP_RB0_ACTIVE',
'regCP_RB0_ACTIVE_BASE_IDX', 'regCP_RB0_BASE',
'regCP_RB0_BASE_BASE_IDX', 'regCP_RB0_BASE_HI',
'regCP_RB0_BASE_HI_BASE_IDX', 'regCP_RB0_BUFSZ_MASK',
'regCP_RB0_BUFSZ_MASK_BASE_IDX', 'regCP_RB0_CNTL',
'regCP_RB0_CNTL_BASE_IDX', 'regCP_RB0_RPTR',
'regCP_RB0_RPTR_ADDR', 'regCP_RB0_RPTR_ADDR_BASE_IDX',
'regCP_RB0_RPTR_ADDR_HI', 'regCP_RB0_RPTR_ADDR_HI_BASE_IDX',
'regCP_RB0_RPTR_BASE_IDX', 'regCP_RB0_WPTR',
'regCP_RB0_WPTR_BASE_IDX', 'regCP_RB0_WPTR_HI',
'regCP_RB0_WPTR_HI_BASE_IDX', 'regCP_RB1_ACTIVE',
'regCP_RB1_ACTIVE_BASE_IDX', 'regCP_RB1_BASE',
'regCP_RB1_BASE_BASE_IDX', 'regCP_RB1_BASE_HI',
'regCP_RB1_BASE_HI_BASE_IDX', 'regCP_RB1_BUFSZ_MASK',
'regCP_RB1_BUFSZ_MASK_BASE_IDX', 'regCP_RB1_CNTL',
'regCP_RB1_CNTL_BASE_IDX', 'regCP_RB1_RPTR',
'regCP_RB1_RPTR_ADDR', 'regCP_RB1_RPTR_ADDR_BASE_IDX',
'regCP_RB1_RPTR_ADDR_HI', 'regCP_RB1_RPTR_ADDR_HI_BASE_IDX',
'regCP_RB1_RPTR_BASE_IDX', 'regCP_RB1_WPTR',
'regCP_RB1_WPTR_BASE_IDX', 'regCP_RB1_WPTR_HI',
'regCP_RB1_WPTR_HI_BASE_IDX', 'regCP_RB_ACTIVE',
'regCP_RB_ACTIVE_BASE_IDX', 'regCP_RB_BASE',
'regCP_RB_BASE_BASE_IDX', 'regCP_RB_BUFSZ_MASK',
'regCP_RB_BUFSZ_MASK_BASE_IDX', 'regCP_RB_CNTL',
'regCP_RB_CNTL_BASE_IDX', 'regCP_RB_DOORBELL_CLEAR',
'regCP_RB_DOORBELL_CLEAR_BASE_IDX', 'regCP_RB_DOORBELL_CONTROL',
'regCP_RB_DOORBELL_CONTROL_BASE_IDX',
'regCP_RB_DOORBELL_RANGE_LOWER',
'regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX',
'regCP_RB_DOORBELL_RANGE_UPPER',
'regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX', 'regCP_RB_OFFSET',
'regCP_RB_OFFSET_BASE_IDX', 'regCP_RB_RPTR', 'regCP_RB_RPTR_ADDR',
'regCP_RB_RPTR_ADDR_BASE_IDX', 'regCP_RB_RPTR_ADDR_HI',
'regCP_RB_RPTR_ADDR_HI_BASE_IDX', 'regCP_RB_RPTR_BASE_IDX',
'regCP_RB_RPTR_WR', 'regCP_RB_RPTR_WR_BASE_IDX',
'regCP_RB_STATUS', 'regCP_RB_STATUS_BASE_IDX', 'regCP_RB_VMID',
'regCP_RB_VMID_BASE_IDX', 'regCP_RB_WPTR',
'regCP_RB_WPTR_BASE_IDX', 'regCP_RB_WPTR_DELAY',
'regCP_RB_WPTR_DELAY_BASE_IDX', 'regCP_RB_WPTR_HI',
'regCP_RB_WPTR_HI_BASE_IDX', 'regCP_RB_WPTR_POLL_ADDR_HI',
'regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regCP_RB_WPTR_POLL_ADDR_LO',
'regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX', 'regCP_RB_WPTR_POLL_CNTL',
'regCP_RB_WPTR_POLL_CNTL_BASE_IDX', 'regCP_RING0_PRIORITY',
'regCP_RING0_PRIORITY_BASE_IDX', 'regCP_RING1_PRIORITY',
'regCP_RING1_PRIORITY_BASE_IDX', 'regCP_RINGID',
'regCP_RINGID_BASE_IDX', 'regCP_RING_PRIORITY_CNTS',
'regCP_RING_PRIORITY_CNTS_BASE_IDX', 'regCP_ROQ1_THRESHOLDS',
'regCP_ROQ1_THRESHOLDS_BASE_IDX', 'regCP_ROQ2_AVAIL',
'regCP_ROQ2_AVAIL_BASE_IDX', 'regCP_ROQ2_THRESHOLDS',
'regCP_ROQ2_THRESHOLDS_BASE_IDX', 'regCP_ROQ3_THRESHOLDS',
'regCP_ROQ3_THRESHOLDS_BASE_IDX', 'regCP_ROQ_AVAIL',
'regCP_ROQ_AVAIL_BASE_IDX', 'regCP_ROQ_DB_STAT',
'regCP_ROQ_DB_STAT_BASE_IDX', 'regCP_ROQ_IB1_STAT',
'regCP_ROQ_IB1_STAT_BASE_IDX', 'regCP_ROQ_IB2_STAT',
'regCP_ROQ_IB2_STAT_BASE_IDX', 'regCP_ROQ_RB_STAT',
'regCP_ROQ_RB_STAT_BASE_IDX', 'regCP_SAMPLE_STATUS',
'regCP_SAMPLE_STATUS_BASE_IDX', 'regCP_SCRATCH_DATA',
'regCP_SCRATCH_DATA_BASE_IDX', 'regCP_SCRATCH_INDEX',
'regCP_SCRATCH_INDEX_BASE_IDX', 'regCP_SC_PSINVOC_COUNT0_HI',
'regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX',
'regCP_SC_PSINVOC_COUNT0_LO',
'regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX',
'regCP_SC_PSINVOC_COUNT1_HI',
'regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX',
'regCP_SC_PSINVOC_COUNT1_LO',
'regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX', 'regCP_SDMA_DMA_DONE',
'regCP_SDMA_DMA_DONE_BASE_IDX', 'regCP_SD_CNTL',
'regCP_SD_CNTL_BASE_IDX', 'regCP_SEM_WAIT_TIMER',
'regCP_SEM_WAIT_TIMER_BASE_IDX', 'regCP_SIG_SEM_ADDR_HI',
'regCP_SIG_SEM_ADDR_HI_BASE_IDX', 'regCP_SIG_SEM_ADDR_LO',
'regCP_SIG_SEM_ADDR_LO_BASE_IDX', 'regCP_SOFT_RESET_CNTL',
'regCP_SOFT_RESET_CNTL_BASE_IDX', 'regCP_STALLED_STAT1',
'regCP_STALLED_STAT1_BASE_IDX', 'regCP_STALLED_STAT2',
'regCP_STALLED_STAT2_BASE_IDX', 'regCP_STALLED_STAT3',
'regCP_STALLED_STAT3_BASE_IDX', 'regCP_STAT',
'regCP_STAT_BASE_IDX', 'regCP_STQ_AVAIL',
'regCP_STQ_AVAIL_BASE_IDX', 'regCP_STQ_STAT',
'regCP_STQ_STAT_BASE_IDX', 'regCP_STQ_THRESHOLDS',
'regCP_STQ_THRESHOLDS_BASE_IDX', 'regCP_STQ_WR_STAT',
'regCP_STQ_WR_STAT_BASE_IDX', 'regCP_ST_BASE_HI',
'regCP_ST_BASE_HI_BASE_IDX', 'regCP_ST_BASE_LO',
'regCP_ST_BASE_LO_BASE_IDX', 'regCP_ST_BUFSZ',
'regCP_ST_BUFSZ_BASE_IDX', 'regCP_ST_CMD_BUFSZ',
'regCP_ST_CMD_BUFSZ_BASE_IDX', 'regCP_SUSPEND_CNTL',
'regCP_SUSPEND_CNTL_BASE_IDX', 'regCP_SUSPEND_RESUME_REQ',
'regCP_SUSPEND_RESUME_REQ_BASE_IDX', 'regCP_VGT_ASINVOC_COUNT_HI',
'regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX',
'regCP_VGT_ASINVOC_COUNT_LO',
'regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX',
'regCP_VGT_CSINVOC_COUNT_HI',
'regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX',
'regCP_VGT_CSINVOC_COUNT_LO',
'regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX',
'regCP_VGT_DSINVOC_COUNT_HI',
'regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX',
'regCP_VGT_DSINVOC_COUNT_LO',
'regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX',
'regCP_VGT_GSINVOC_COUNT_HI',
'regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX',
'regCP_VGT_GSINVOC_COUNT_LO',
'regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX',
'regCP_VGT_GSPRIM_COUNT_HI', 'regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX',
'regCP_VGT_GSPRIM_COUNT_LO', 'regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX',
'regCP_VGT_HSINVOC_COUNT_HI',
'regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX',
'regCP_VGT_HSINVOC_COUNT_LO',
'regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX',
'regCP_VGT_IAPRIM_COUNT_HI', 'regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX',
'regCP_VGT_IAPRIM_COUNT_LO', 'regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX',
'regCP_VGT_IAVERT_COUNT_HI', 'regCP_VGT_IAVERT_COUNT_HI_BASE_IDX',
'regCP_VGT_IAVERT_COUNT_LO', 'regCP_VGT_IAVERT_COUNT_LO_BASE_IDX',
'regCP_VGT_VSINVOC_COUNT_HI',
'regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX',
'regCP_VGT_VSINVOC_COUNT_LO',
'regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX', 'regCP_VIRT_STATUS',
'regCP_VIRT_STATUS_BASE_IDX', 'regCP_VMID', 'regCP_VMID_BASE_IDX',
'regCP_VMID_PREEMPT', 'regCP_VMID_PREEMPT_BASE_IDX',
'regCP_VMID_RESET', 'regCP_VMID_RESET_BASE_IDX',
'regCP_VMID_STATUS', 'regCP_VMID_STATUS_BASE_IDX',
'regCP_WAIT_REG_MEM_TIMEOUT',
'regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX', 'regCP_WAIT_SEM_ADDR_HI',
'regCP_WAIT_SEM_ADDR_HI_BASE_IDX', 'regCP_WAIT_SEM_ADDR_LO',
'regCP_WAIT_SEM_ADDR_LO_BASE_IDX', 'regDB_ALPHA_TO_MASK',
'regDB_ALPHA_TO_MASK_BASE_IDX', 'regDB_CGTT_CLK_CTRL_0',
'regDB_CGTT_CLK_CTRL_0_BASE_IDX', 'regDB_COUNT_CONTROL',
'regDB_COUNT_CONTROL_BASE_IDX', 'regDB_CREDIT_LIMIT',
'regDB_CREDIT_LIMIT_BASE_IDX', 'regDB_DEBUG', 'regDB_DEBUG2',
'regDB_DEBUG2_BASE_IDX', 'regDB_DEBUG3', 'regDB_DEBUG3_BASE_IDX',
'regDB_DEBUG4', 'regDB_DEBUG4_BASE_IDX', 'regDB_DEBUG5',
'regDB_DEBUG5_BASE_IDX', 'regDB_DEBUG6', 'regDB_DEBUG6_BASE_IDX',
'regDB_DEBUG7', 'regDB_DEBUG7_BASE_IDX', 'regDB_DEBUG_BASE_IDX',
'regDB_DEPTH_BOUNDS_MAX', 'regDB_DEPTH_BOUNDS_MAX_BASE_IDX',
'regDB_DEPTH_BOUNDS_MIN', 'regDB_DEPTH_BOUNDS_MIN_BASE_IDX',
'regDB_DEPTH_CLEAR', 'regDB_DEPTH_CLEAR_BASE_IDX',
'regDB_DEPTH_CONTROL', 'regDB_DEPTH_CONTROL_BASE_IDX',
'regDB_DEPTH_SIZE_XY', 'regDB_DEPTH_SIZE_XY_BASE_IDX',
'regDB_DEPTH_VIEW', 'regDB_DEPTH_VIEW_BASE_IDX', 'regDB_EQAA',
'regDB_EQAA_BASE_IDX', 'regDB_EQUAD_STUTTER_CONTROL',
'regDB_EQUAD_STUTTER_CONTROL_BASE_IDX',
'regDB_ETILE_STUTTER_CONTROL',
'regDB_ETILE_STUTTER_CONTROL_BASE_IDX', 'regDB_EXCEPTION_CONTROL',
'regDB_EXCEPTION_CONTROL_BASE_IDX',
'regDB_FGCG_INTERFACES_CLK_CTRL',
'regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX',
'regDB_FGCG_SRAMS_CLK_CTRL', 'regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX',
'regDB_FIFO_DEPTH1', 'regDB_FIFO_DEPTH1_BASE_IDX',
'regDB_FIFO_DEPTH2', 'regDB_FIFO_DEPTH2_BASE_IDX',
'regDB_FIFO_DEPTH3', 'regDB_FIFO_DEPTH3_BASE_IDX',
'regDB_FIFO_DEPTH4', 'regDB_FIFO_DEPTH4_BASE_IDX',
'regDB_FREE_CACHELINES', 'regDB_FREE_CACHELINES_BASE_IDX',
'regDB_HTILE_DATA_BASE', 'regDB_HTILE_DATA_BASE_BASE_IDX',
'regDB_HTILE_DATA_BASE_HI', 'regDB_HTILE_DATA_BASE_HI_BASE_IDX',
'regDB_HTILE_SURFACE', 'regDB_HTILE_SURFACE_BASE_IDX',
'regDB_LAST_OF_BURST_CONFIG',
'regDB_LAST_OF_BURST_CONFIG_BASE_IDX',
'regDB_LQUAD_STUTTER_CONTROL',
'regDB_LQUAD_STUTTER_CONTROL_BASE_IDX',
'regDB_LTILE_STUTTER_CONTROL',
'regDB_LTILE_STUTTER_CONTROL_BASE_IDX',
'regDB_MEM_ARB_WATERMARKS', 'regDB_MEM_ARB_WATERMARKS_BASE_IDX',
'regDB_OCCLUSION_COUNT0_HI', 'regDB_OCCLUSION_COUNT0_HI_BASE_IDX',
'regDB_OCCLUSION_COUNT0_LOW',
'regDB_OCCLUSION_COUNT0_LOW_BASE_IDX',
'regDB_OCCLUSION_COUNT1_HI', 'regDB_OCCLUSION_COUNT1_HI_BASE_IDX',
'regDB_OCCLUSION_COUNT1_LOW',
'regDB_OCCLUSION_COUNT1_LOW_BASE_IDX',
'regDB_OCCLUSION_COUNT2_HI', 'regDB_OCCLUSION_COUNT2_HI_BASE_IDX',
'regDB_OCCLUSION_COUNT2_LOW',
'regDB_OCCLUSION_COUNT2_LOW_BASE_IDX',
'regDB_OCCLUSION_COUNT3_HI', 'regDB_OCCLUSION_COUNT3_HI_BASE_IDX',
'regDB_OCCLUSION_COUNT3_LOW',
'regDB_OCCLUSION_COUNT3_LOW_BASE_IDX', 'regDB_PERFCOUNTER0_HI',
'regDB_PERFCOUNTER0_HI_BASE_IDX', 'regDB_PERFCOUNTER0_LO',
'regDB_PERFCOUNTER0_LO_BASE_IDX', 'regDB_PERFCOUNTER0_SELECT',
'regDB_PERFCOUNTER0_SELECT1',
'regDB_PERFCOUNTER0_SELECT1_BASE_IDX',
'regDB_PERFCOUNTER0_SELECT_BASE_IDX', 'regDB_PERFCOUNTER1_HI',
'regDB_PERFCOUNTER1_HI_BASE_IDX', 'regDB_PERFCOUNTER1_LO',
'regDB_PERFCOUNTER1_LO_BASE_IDX', 'regDB_PERFCOUNTER1_SELECT',
'regDB_PERFCOUNTER1_SELECT1',
'regDB_PERFCOUNTER1_SELECT1_BASE_IDX',
'regDB_PERFCOUNTER1_SELECT_BASE_IDX', 'regDB_PERFCOUNTER2_HI',
'regDB_PERFCOUNTER2_HI_BASE_IDX', 'regDB_PERFCOUNTER2_LO',
'regDB_PERFCOUNTER2_LO_BASE_IDX', 'regDB_PERFCOUNTER2_SELECT',
'regDB_PERFCOUNTER2_SELECT_BASE_IDX', 'regDB_PERFCOUNTER3_HI',
'regDB_PERFCOUNTER3_HI_BASE_IDX', 'regDB_PERFCOUNTER3_LO',
'regDB_PERFCOUNTER3_LO_BASE_IDX', 'regDB_PERFCOUNTER3_SELECT',
'regDB_PERFCOUNTER3_SELECT_BASE_IDX', 'regDB_PRELOAD_CONTROL',
'regDB_PRELOAD_CONTROL_BASE_IDX', 'regDB_RENDER_CONTROL',
'regDB_RENDER_CONTROL_BASE_IDX', 'regDB_RENDER_OVERRIDE',
'regDB_RENDER_OVERRIDE2', 'regDB_RENDER_OVERRIDE2_BASE_IDX',
'regDB_RENDER_OVERRIDE_BASE_IDX', 'regDB_RESERVED_REG_1',
'regDB_RESERVED_REG_1_BASE_IDX', 'regDB_RESERVED_REG_2',
'regDB_RESERVED_REG_2_BASE_IDX', 'regDB_RESERVED_REG_3',
'regDB_RESERVED_REG_3_BASE_IDX', 'regDB_RING_CONTROL',
'regDB_RING_CONTROL_BASE_IDX', 'regDB_RMI_L2_CACHE_CONTROL',
'regDB_RMI_L2_CACHE_CONTROL_BASE_IDX', 'regDB_SHADER_CONTROL',
'regDB_SHADER_CONTROL_BASE_IDX', 'regDB_SRESULTS_COMPARE_STATE0',
'regDB_SRESULTS_COMPARE_STATE0_BASE_IDX',
'regDB_SRESULTS_COMPARE_STATE1',
'regDB_SRESULTS_COMPARE_STATE1_BASE_IDX', 'regDB_STENCILREFMASK',
'regDB_STENCILREFMASK_BASE_IDX', 'regDB_STENCILREFMASK_BF',
'regDB_STENCILREFMASK_BF_BASE_IDX', 'regDB_STENCIL_CLEAR',
'regDB_STENCIL_CLEAR_BASE_IDX', 'regDB_STENCIL_CONTROL',
'regDB_STENCIL_CONTROL_BASE_IDX', 'regDB_STENCIL_INFO',
'regDB_STENCIL_INFO_BASE_IDX', 'regDB_STENCIL_READ_BASE',
'regDB_STENCIL_READ_BASE_BASE_IDX', 'regDB_STENCIL_READ_BASE_HI',
'regDB_STENCIL_READ_BASE_HI_BASE_IDX', 'regDB_STENCIL_WRITE_BASE',
'regDB_STENCIL_WRITE_BASE_BASE_IDX',
'regDB_STENCIL_WRITE_BASE_HI',
'regDB_STENCIL_WRITE_BASE_HI_BASE_IDX', 'regDB_SUBTILE_CONTROL',
'regDB_SUBTILE_CONTROL_BASE_IDX', 'regDB_WATERMARKS',
'regDB_WATERMARKS_BASE_IDX', 'regDB_Z_INFO',
'regDB_Z_INFO_BASE_IDX', 'regDB_Z_READ_BASE',
'regDB_Z_READ_BASE_BASE_IDX', 'regDB_Z_READ_BASE_HI',
'regDB_Z_READ_BASE_HI_BASE_IDX', 'regDB_Z_WRITE_BASE',
'regDB_Z_WRITE_BASE_BASE_IDX', 'regDB_Z_WRITE_BASE_HI',
'regDB_Z_WRITE_BASE_HI_BASE_IDX', 'regDIDT_EDC_CTRL',
'regDIDT_EDC_CTRL_BASE_IDX', 'regDIDT_EDC_DYNAMIC_THRESHOLD_RO',
'regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX',
'regDIDT_EDC_OVERFLOW', 'regDIDT_EDC_OVERFLOW_BASE_IDX',
'regDIDT_EDC_ROLLING_POWER_DELTA',
'regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX',
'regDIDT_EDC_STALL_PATTERN_1_2',
'regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX',
'regDIDT_EDC_STALL_PATTERN_3_4',
'regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX',
'regDIDT_EDC_STALL_PATTERN_5_6',
'regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX',
'regDIDT_EDC_STALL_PATTERN_7',
'regDIDT_EDC_STALL_PATTERN_7_BASE_IDX', 'regDIDT_EDC_STATUS',
'regDIDT_EDC_STATUS_BASE_IDX', 'regDIDT_EDC_THRESHOLD',
'regDIDT_EDC_THRESHOLD_BASE_IDX', 'regDIDT_EDC_THROTTLE_CTRL',
'regDIDT_EDC_THROTTLE_CTRL_BASE_IDX',
'regDIDT_INDEX_AUTO_INCR_EN',
'regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX', 'regDIDT_IND_DATA',
'regDIDT_IND_DATA_BASE_IDX', 'regDIDT_IND_INDEX',
'regDIDT_IND_INDEX_BASE_IDX', 'regDIDT_STALL_PATTERN_1_2',
'regDIDT_STALL_PATTERN_1_2_BASE_IDX', 'regDIDT_STALL_PATTERN_3_4',
'regDIDT_STALL_PATTERN_3_4_BASE_IDX', 'regDIDT_STALL_PATTERN_5_6',
'regDIDT_STALL_PATTERN_5_6_BASE_IDX', 'regDIDT_STALL_PATTERN_7',
'regDIDT_STALL_PATTERN_7_BASE_IDX', 'regDIDT_STALL_PATTERN_CTRL',
'regDIDT_STALL_PATTERN_CTRL_BASE_IDX', 'regEDC_HYSTERESIS_CNTL',
'regEDC_HYSTERESIS_CNTL_BASE_IDX', 'regEDC_HYSTERESIS_STAT',
'regEDC_HYSTERESIS_STAT_BASE_IDX', 'regEDC_PERF_COUNTER',
'regEDC_PERF_COUNTER_BASE_IDX', 'regEDC_STRETCH_NUM_PERF_COUNTER',
'regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX',
'regEDC_STRETCH_PERF_COUNTER',
'regEDC_STRETCH_PERF_COUNTER_BASE_IDX',
'regEDC_UNSTRETCH_PERF_COUNTER',
'regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX', 'regGB_ADDR_CONFIG',
'regGB_ADDR_CONFIG_BASE_IDX', 'regGB_ADDR_CONFIG_READ',
'regGB_ADDR_CONFIG_READ_BASE_IDX', 'regGB_BACKEND_MAP',
'regGB_BACKEND_MAP_BASE_IDX', 'regGB_EDC_MODE',
'regGB_EDC_MODE_BASE_IDX', 'regGB_GPU_ID',
'regGB_GPU_ID_BASE_IDX', 'regGCEA_DRAM_PAGE_BURST',
'regGCEA_DRAM_PAGE_BURST_BASE_IDX', 'regGCEA_DRAM_RD_CAM_CNTL',
'regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX',
'regGCEA_DRAM_RD_CLI2GRP_MAP0',
'regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX',
'regGCEA_DRAM_RD_CLI2GRP_MAP1',
'regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX',
'regGCEA_DRAM_RD_GRP2VC_MAP',
'regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX', 'regGCEA_DRAM_RD_LAZY',
'regGCEA_DRAM_RD_LAZY_BASE_IDX', 'regGCEA_DRAM_RD_PRI_AGE',
'regGCEA_DRAM_RD_PRI_AGE_BASE_IDX', 'regGCEA_DRAM_RD_PRI_FIXED',
'regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX',
'regGCEA_DRAM_RD_PRI_QUANT_PRI1',
'regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX',
'regGCEA_DRAM_RD_PRI_QUANT_PRI2',
'regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX',
'regGCEA_DRAM_RD_PRI_QUANT_PRI3',
'regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX',
'regGCEA_DRAM_RD_PRI_QUEUING',
'regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX',
'regGCEA_DRAM_RD_PRI_URGENCY',
'regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX',
'regGCEA_DRAM_WR_CAM_CNTL', 'regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX',
'regGCEA_DRAM_WR_CLI2GRP_MAP0',
'regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX',
'regGCEA_DRAM_WR_CLI2GRP_MAP1',
'regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX',
'regGCEA_DRAM_WR_GRP2VC_MAP',
'regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX', 'regGCEA_DRAM_WR_LAZY',
'regGCEA_DRAM_WR_LAZY_BASE_IDX', 'regGCEA_DRAM_WR_PRI_AGE',
'regGCEA_DRAM_WR_PRI_AGE_BASE_IDX', 'regGCEA_DRAM_WR_PRI_FIXED',
'regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX',
'regGCEA_DRAM_WR_PRI_QUANT_PRI1',
'regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX',
'regGCEA_DRAM_WR_PRI_QUANT_PRI2',
'regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX',
'regGCEA_DRAM_WR_PRI_QUANT_PRI3',
'regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX',
'regGCEA_DRAM_WR_PRI_QUEUING',
'regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX',
'regGCEA_DRAM_WR_PRI_URGENCY',
'regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX', 'regGCEA_DSM_CNTL',
'regGCEA_DSM_CNTL2', 'regGCEA_DSM_CNTL2A',
'regGCEA_DSM_CNTL2A_BASE_IDX', 'regGCEA_DSM_CNTL2B',
'regGCEA_DSM_CNTL2B_BASE_IDX', 'regGCEA_DSM_CNTL2_BASE_IDX',
'regGCEA_DSM_CNTLA', 'regGCEA_DSM_CNTLA_BASE_IDX',
'regGCEA_DSM_CNTLB', 'regGCEA_DSM_CNTLB_BASE_IDX',
'regGCEA_DSM_CNTL_BASE_IDX', 'regGCEA_EDC_CNT',
'regGCEA_EDC_CNT2', 'regGCEA_EDC_CNT2_BASE_IDX',
'regGCEA_EDC_CNT3', 'regGCEA_EDC_CNT3_BASE_IDX',
'regGCEA_EDC_CNT_BASE_IDX', 'regGCEA_ERR_STATUS',
'regGCEA_ERR_STATUS_BASE_IDX', 'regGCEA_GL2C_XBR_CREDITS',
'regGCEA_GL2C_XBR_CREDITS_BASE_IDX', 'regGCEA_GL2C_XBR_MAXBURST',
'regGCEA_GL2C_XBR_MAXBURST_BASE_IDX', 'regGCEA_ICG_CTRL',
'regGCEA_ICG_CTRL_BASE_IDX', 'regGCEA_IO_GROUP_BURST',
'regGCEA_IO_GROUP_BURST_BASE_IDX', 'regGCEA_IO_RD_CLI2GRP_MAP0',
'regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX',
'regGCEA_IO_RD_CLI2GRP_MAP1',
'regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX',
'regGCEA_IO_RD_COMBINE_FLUSH',
'regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX', 'regGCEA_IO_RD_PRI_AGE',
'regGCEA_IO_RD_PRI_AGE_BASE_IDX', 'regGCEA_IO_RD_PRI_FIXED',
'regGCEA_IO_RD_PRI_FIXED_BASE_IDX',
'regGCEA_IO_RD_PRI_QUANT_PRI1',
'regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX',
'regGCEA_IO_RD_PRI_QUANT_PRI2',
'regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX',
'regGCEA_IO_RD_PRI_QUANT_PRI3',
'regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX',
'regGCEA_IO_RD_PRI_QUEUING', 'regGCEA_IO_RD_PRI_QUEUING_BASE_IDX',
'regGCEA_IO_RD_PRI_URGENCY', 'regGCEA_IO_RD_PRI_URGENCY_BASE_IDX',
'regGCEA_IO_RD_PRI_URGENCY_MASKING',
'regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX',
'regGCEA_IO_WR_CLI2GRP_MAP0',
'regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX',
'regGCEA_IO_WR_CLI2GRP_MAP1',
'regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX',
'regGCEA_IO_WR_COMBINE_FLUSH',
'regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX', 'regGCEA_IO_WR_PRI_AGE',
'regGCEA_IO_WR_PRI_AGE_BASE_IDX', 'regGCEA_IO_WR_PRI_FIXED',
'regGCEA_IO_WR_PRI_FIXED_BASE_IDX',
'regGCEA_IO_WR_PRI_QUANT_PRI1',
'regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX',
'regGCEA_IO_WR_PRI_QUANT_PRI2',
'regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX',
'regGCEA_IO_WR_PRI_QUANT_PRI3',
'regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX',
'regGCEA_IO_WR_PRI_QUEUING', 'regGCEA_IO_WR_PRI_QUEUING_BASE_IDX',
'regGCEA_IO_WR_PRI_URGENCY', 'regGCEA_IO_WR_PRI_URGENCY_BASE_IDX',
'regGCEA_IO_WR_PRI_URGENCY_MASKING',
'regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX',
'regGCEA_LATENCY_SAMPLING', 'regGCEA_LATENCY_SAMPLING_BASE_IDX',
'regGCEA_MAM_CTRL', 'regGCEA_MAM_CTRL2',
'regGCEA_MAM_CTRL2_BASE_IDX', 'regGCEA_MAM_CTRL_BASE_IDX',
'regGCEA_MISC', 'regGCEA_MISC2', 'regGCEA_MISC2_BASE_IDX',
'regGCEA_MISC_BASE_IDX', 'regGCEA_PERFCOUNTER0_CFG',
'regGCEA_PERFCOUNTER0_CFG_BASE_IDX', 'regGCEA_PERFCOUNTER1_CFG',
'regGCEA_PERFCOUNTER1_CFG_BASE_IDX', 'regGCEA_PERFCOUNTER2_HI',
'regGCEA_PERFCOUNTER2_HI_BASE_IDX', 'regGCEA_PERFCOUNTER2_LO',
'regGCEA_PERFCOUNTER2_LO_BASE_IDX', 'regGCEA_PERFCOUNTER2_MODE',
'regGCEA_PERFCOUNTER2_MODE_BASE_IDX',
'regGCEA_PERFCOUNTER2_SELECT', 'regGCEA_PERFCOUNTER2_SELECT1',
'regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX',
'regGCEA_PERFCOUNTER2_SELECT_BASE_IDX', 'regGCEA_PERFCOUNTER_HI',
'regGCEA_PERFCOUNTER_HI_BASE_IDX', 'regGCEA_PERFCOUNTER_LO',
'regGCEA_PERFCOUNTER_LO_BASE_IDX',
'regGCEA_PERFCOUNTER_RSLT_CNTL',
'regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regGCEA_PROBE_CNTL',
'regGCEA_PROBE_CNTL_BASE_IDX', 'regGCEA_PROBE_MAP',
'regGCEA_PROBE_MAP_BASE_IDX', 'regGCEA_RRET_MEM_RESERVE',
'regGCEA_RRET_MEM_RESERVE_BASE_IDX', 'regGCEA_SDP_ARB_FINAL',
'regGCEA_SDP_ARB_FINAL_BASE_IDX', 'regGCEA_SDP_CREDITS',
'regGCEA_SDP_CREDITS_BASE_IDX', 'regGCEA_SDP_ENABLE',
'regGCEA_SDP_ENABLE_BASE_IDX', 'regGCEA_SDP_IO_PRIORITY',
'regGCEA_SDP_IO_PRIORITY_BASE_IDX', 'regGCEA_SDP_TAG_RESERVE0',
'regGCEA_SDP_TAG_RESERVE0_BASE_IDX', 'regGCEA_SDP_TAG_RESERVE1',
'regGCEA_SDP_TAG_RESERVE1_BASE_IDX', 'regGCEA_SDP_VCC_RESERVE0',
'regGCEA_SDP_VCC_RESERVE0_BASE_IDX', 'regGCEA_SDP_VCC_RESERVE1',
'regGCEA_SDP_VCC_RESERVE1_BASE_IDX', 'regGCMC_MEM_POWER_LS',
'regGCMC_MEM_POWER_LS_BASE_IDX', 'regGCMC_VM_AGP_BASE',
'regGCMC_VM_AGP_BASE_BASE_IDX', 'regGCMC_VM_AGP_BOT',
'regGCMC_VM_AGP_BOT_BASE_IDX', 'regGCMC_VM_AGP_TOP',
'regGCMC_VM_AGP_TOP_BASE_IDX', 'regGCMC_VM_APT_CNTL',
'regGCMC_VM_APT_CNTL_BASE_IDX',
'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END',
'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX',
'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START',
'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX',
'regGCMC_VM_FB_LOCATION_BASE',
'regGCMC_VM_FB_LOCATION_BASE_BASE_IDX',
'regGCMC_VM_FB_LOCATION_TOP',
'regGCMC_VM_FB_LOCATION_TOP_BASE_IDX',
'regGCMC_VM_FB_NOALLOC_CNTL',
'regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX', 'regGCMC_VM_FB_OFFSET',
'regGCMC_VM_FB_OFFSET_BASE_IDX', 'regGCMC_VM_FB_SIZE_OFFSET_VF0',
'regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF1', 'regGCMC_VM_FB_SIZE_OFFSET_VF10',
'regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF11',
'regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF12',
'regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF13',
'regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF14',
'regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF15',
'regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF2',
'regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF3',
'regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF4',
'regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF5',
'regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF6',
'regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF7',
'regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF8',
'regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX',
'regGCMC_VM_FB_SIZE_OFFSET_VF9',
'regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX',
'regGCMC_VM_L2_PERFCOUNTER0_CFG',
'regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX',
'regGCMC_VM_L2_PERFCOUNTER1_CFG',
'regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX',
'regGCMC_VM_L2_PERFCOUNTER2_CFG',
'regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX',
'regGCMC_VM_L2_PERFCOUNTER3_CFG',
'regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX',
'regGCMC_VM_L2_PERFCOUNTER4_CFG',
'regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX',
'regGCMC_VM_L2_PERFCOUNTER5_CFG',
'regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX',
'regGCMC_VM_L2_PERFCOUNTER6_CFG',
'regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX',
'regGCMC_VM_L2_PERFCOUNTER7_CFG',
'regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX',
'regGCMC_VM_L2_PERFCOUNTER_HI',
'regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX',
'regGCMC_VM_L2_PERFCOUNTER_LO',
'regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX',
'regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL',
'regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
'regGCMC_VM_LOCAL_FB_ADDRESS_END',
'regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX',
'regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL',
'regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX',
'regGCMC_VM_LOCAL_FB_ADDRESS_START',
'regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX',
'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END',
'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX',
'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START',
'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX',
'regGCMC_VM_MARC_BASE_HI_0', 'regGCMC_VM_MARC_BASE_HI_0_BASE_IDX',
'regGCMC_VM_MARC_BASE_HI_1', 'regGCMC_VM_MARC_BASE_HI_10',
'regGCMC_VM_MARC_BASE_HI_10_BASE_IDX',
'regGCMC_VM_MARC_BASE_HI_11',
'regGCMC_VM_MARC_BASE_HI_11_BASE_IDX',
'regGCMC_VM_MARC_BASE_HI_12',
'regGCMC_VM_MARC_BASE_HI_12_BASE_IDX',
'regGCMC_VM_MARC_BASE_HI_13',
'regGCMC_VM_MARC_BASE_HI_13_BASE_IDX',
'regGCMC_VM_MARC_BASE_HI_14',
'regGCMC_VM_MARC_BASE_HI_14_BASE_IDX',
'regGCMC_VM_MARC_BASE_HI_15',
'regGCMC_VM_MARC_BASE_HI_15_BASE_IDX',
'regGCMC_VM_MARC_BASE_HI_1_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_2',
'regGCMC_VM_MARC_BASE_HI_2_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_3',
'regGCMC_VM_MARC_BASE_HI_3_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_4',
'regGCMC_VM_MARC_BASE_HI_4_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_5',
'regGCMC_VM_MARC_BASE_HI_5_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_6',
'regGCMC_VM_MARC_BASE_HI_6_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_7',
'regGCMC_VM_MARC_BASE_HI_7_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_8',
'regGCMC_VM_MARC_BASE_HI_8_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_9',
'regGCMC_VM_MARC_BASE_HI_9_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_0',
'regGCMC_VM_MARC_BASE_LO_0_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_1',
'regGCMC_VM_MARC_BASE_LO_10',
'regGCMC_VM_MARC_BASE_LO_10_BASE_IDX',
'regGCMC_VM_MARC_BASE_LO_11',
'regGCMC_VM_MARC_BASE_LO_11_BASE_IDX',
'regGCMC_VM_MARC_BASE_LO_12',
'regGCMC_VM_MARC_BASE_LO_12_BASE_IDX',
'regGCMC_VM_MARC_BASE_LO_13',
'regGCMC_VM_MARC_BASE_LO_13_BASE_IDX',
'regGCMC_VM_MARC_BASE_LO_14',
'regGCMC_VM_MARC_BASE_LO_14_BASE_IDX',
'regGCMC_VM_MARC_BASE_LO_15',
'regGCMC_VM_MARC_BASE_LO_15_BASE_IDX',
'regGCMC_VM_MARC_BASE_LO_1_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_2',
'regGCMC_VM_MARC_BASE_LO_2_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_3',
'regGCMC_VM_MARC_BASE_LO_3_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_4',
'regGCMC_VM_MARC_BASE_LO_4_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_5',
'regGCMC_VM_MARC_BASE_LO_5_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_6',
'regGCMC_VM_MARC_BASE_LO_6_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_7',
'regGCMC_VM_MARC_BASE_LO_7_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_8',
'regGCMC_VM_MARC_BASE_LO_8_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_9',
'regGCMC_VM_MARC_BASE_LO_9_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_0',
'regGCMC_VM_MARC_LEN_HI_0_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_1',
'regGCMC_VM_MARC_LEN_HI_10', 'regGCMC_VM_MARC_LEN_HI_10_BASE_IDX',
'regGCMC_VM_MARC_LEN_HI_11', 'regGCMC_VM_MARC_LEN_HI_11_BASE_IDX',
'regGCMC_VM_MARC_LEN_HI_12', 'regGCMC_VM_MARC_LEN_HI_12_BASE_IDX',
'regGCMC_VM_MARC_LEN_HI_13', 'regGCMC_VM_MARC_LEN_HI_13_BASE_IDX',
'regGCMC_VM_MARC_LEN_HI_14', 'regGCMC_VM_MARC_LEN_HI_14_BASE_IDX',
'regGCMC_VM_MARC_LEN_HI_15', 'regGCMC_VM_MARC_LEN_HI_15_BASE_IDX',
'regGCMC_VM_MARC_LEN_HI_1_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_2',
'regGCMC_VM_MARC_LEN_HI_2_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_3',
'regGCMC_VM_MARC_LEN_HI_3_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_4',
'regGCMC_VM_MARC_LEN_HI_4_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_5',
'regGCMC_VM_MARC_LEN_HI_5_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_6',
'regGCMC_VM_MARC_LEN_HI_6_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_7',
'regGCMC_VM_MARC_LEN_HI_7_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_8',
'regGCMC_VM_MARC_LEN_HI_8_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_9',
'regGCMC_VM_MARC_LEN_HI_9_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_0',
'regGCMC_VM_MARC_LEN_LO_0_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_1',
'regGCMC_VM_MARC_LEN_LO_10', 'regGCMC_VM_MARC_LEN_LO_10_BASE_IDX',
'regGCMC_VM_MARC_LEN_LO_11', 'regGCMC_VM_MARC_LEN_LO_11_BASE_IDX',
'regGCMC_VM_MARC_LEN_LO_12', 'regGCMC_VM_MARC_LEN_LO_12_BASE_IDX',
'regGCMC_VM_MARC_LEN_LO_13', 'regGCMC_VM_MARC_LEN_LO_13_BASE_IDX',
'regGCMC_VM_MARC_LEN_LO_14', 'regGCMC_VM_MARC_LEN_LO_14_BASE_IDX',
'regGCMC_VM_MARC_LEN_LO_15', 'regGCMC_VM_MARC_LEN_LO_15_BASE_IDX',
'regGCMC_VM_MARC_LEN_LO_1_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_2',
'regGCMC_VM_MARC_LEN_LO_2_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_3',
'regGCMC_VM_MARC_LEN_LO_3_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_4',
'regGCMC_VM_MARC_LEN_LO_4_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_5',
'regGCMC_VM_MARC_LEN_LO_5_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_6',
'regGCMC_VM_MARC_LEN_LO_6_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_7',
'regGCMC_VM_MARC_LEN_LO_7_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_8',
'regGCMC_VM_MARC_LEN_LO_8_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_9',
'regGCMC_VM_MARC_LEN_LO_9_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_0',
'regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_1',
'regGCMC_VM_MARC_PFVF_MAPPING_10',
'regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_11',
'regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_12',
'regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_13',
'regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_14',
'regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_15',
'regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_2',
'regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_3',
'regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_4',
'regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_5',
'regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_6',
'regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_7',
'regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_8',
'regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX',
'regGCMC_VM_MARC_PFVF_MAPPING_9',
'regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_0',
'regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_1', 'regGCMC_VM_MARC_RELOC_HI_10',
'regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_11',
'regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_12',
'regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_13',
'regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_14',
'regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_15',
'regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_2',
'regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_3',
'regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_4',
'regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_5',
'regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_6',
'regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_7',
'regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_8',
'regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX',
'regGCMC_VM_MARC_RELOC_HI_9',
'regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_0',
'regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_1', 'regGCMC_VM_MARC_RELOC_LO_10',
'regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_11',
'regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_12',
'regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_13',
'regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_14',
'regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_15',
'regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_2',
'regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_3',
'regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_4',
'regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_5',
'regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_6',
'regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_7',
'regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_8',
'regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX',
'regGCMC_VM_MARC_RELOC_LO_9',
'regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX',
'regGCMC_VM_MX_L1_TLB_CNTL', 'regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX',
'regGCMC_VM_NB_LOWER_TOP_OF_DRAM2',
'regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX',
'regGCMC_VM_NB_TOP_OF_DRAM_SLOT1',
'regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX',
'regGCMC_VM_NB_UPPER_TOP_OF_DRAM2',
'regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX',
'regGCMC_VM_STEERING', 'regGCMC_VM_STEERING_BASE_IDX',
'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB',
'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX',
'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB',
'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX',
'regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR',
'regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX',
'regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR',
'regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX',
'regGCRD_CREDIT_SAFE', 'regGCRD_CREDIT_SAFE_BASE_IDX',
'regGCRD_SA0_TARGETS_DISABLE',
'regGCRD_SA0_TARGETS_DISABLE_BASE_IDX',
'regGCRD_SA1_TARGETS_DISABLE',
'regGCRD_SA1_TARGETS_DISABLE_BASE_IDX', 'regGCR_CMD_STATUS',
'regGCR_CMD_STATUS_BASE_IDX', 'regGCR_GENERAL_CNTL',
'regGCR_GENERAL_CNTL_BASE_IDX', 'regGCR_PERFCOUNTER0_HI',
'regGCR_PERFCOUNTER0_HI_BASE_IDX', 'regGCR_PERFCOUNTER0_LO',
'regGCR_PERFCOUNTER0_LO_BASE_IDX', 'regGCR_PERFCOUNTER0_SELECT',
'regGCR_PERFCOUNTER0_SELECT1',
'regGCR_PERFCOUNTER0_SELECT1_BASE_IDX',
'regGCR_PERFCOUNTER0_SELECT_BASE_IDX', 'regGCR_PERFCOUNTER1_HI',
'regGCR_PERFCOUNTER1_HI_BASE_IDX', 'regGCR_PERFCOUNTER1_LO',
'regGCR_PERFCOUNTER1_LO_BASE_IDX', 'regGCR_PERFCOUNTER1_SELECT',
'regGCR_PERFCOUNTER1_SELECT_BASE_IDX', 'regGCR_PIO_CNTL',
'regGCR_PIO_CNTL_BASE_IDX', 'regGCR_PIO_DATA',
'regGCR_PIO_DATA_BASE_IDX', 'regGCR_SPARE',
'regGCR_SPARE_BASE_IDX', 'regGCUTCL2_CGTT_BUSY_CTRL',
'regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX',
'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC',
'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX',
'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC',
'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX',
'regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC',
'regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX',
'regGCUTCL2_GROUP_RET_FAULT_STATUS',
'regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX',
'regGCUTCL2_HARVEST_BYPASS_GROUPS',
'regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX',
'regGCUTCL2_ICG_CTRL', 'regGCUTCL2_ICG_CTRL_BASE_IDX',
'regGCUTCL2_PERFCOUNTER0_CFG',
'regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX',
'regGCUTCL2_PERFCOUNTER1_CFG',
'regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX',
'regGCUTCL2_PERFCOUNTER2_CFG',
'regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX',
'regGCUTCL2_PERFCOUNTER3_CFG',
'regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX',
'regGCUTCL2_PERFCOUNTER_HI', 'regGCUTCL2_PERFCOUNTER_HI_BASE_IDX',
'regGCUTCL2_PERFCOUNTER_LO', 'regGCUTCL2_PERFCOUNTER_LO_BASE_IDX',
'regGCUTCL2_PERFCOUNTER_RSLT_CNTL',
'regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
'regGCUTCL2_TRANSLATION_BYPASS_BY_VMID',
'regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX',
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL',
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX',
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI',
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX',
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO',
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX',
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI',
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX',
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO',
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX',
'regGCUTC_TRANSLATION_FAULT_CNTL0',
'regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX',
'regGCUTC_TRANSLATION_FAULT_CNTL1',
'regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX',
'regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT',
'regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX',
'regGCVML2_PERFCOUNTER2_0_HI',
'regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX',
'regGCVML2_PERFCOUNTER2_0_LO',
'regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX',
'regGCVML2_PERFCOUNTER2_0_MODE',
'regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX',
'regGCVML2_PERFCOUNTER2_0_SELECT',
'regGCVML2_PERFCOUNTER2_0_SELECT1',
'regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX',
'regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX',
'regGCVML2_PERFCOUNTER2_1_HI',
'regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX',
'regGCVML2_PERFCOUNTER2_1_LO',
'regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX',
'regGCVML2_PERFCOUNTER2_1_MODE',
'regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX',
'regGCVML2_PERFCOUNTER2_1_SELECT',
'regGCVML2_PERFCOUNTER2_1_SELECT1',
'regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX',
'regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX',
'regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ',
'regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX',
'regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT',
'regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX',
'regGCVML2_WALKER_MACRO_THROTTLE_TIME',
'regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX',
'regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT',
'regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX',
'regGCVML2_WALKER_MICRO_THROTTLE_TIME',
'regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX',
'regGCVM_CONTEXT0_CNTL', 'regGCVM_CONTEXT0_CNTL_BASE_IDX',
'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT10_CNTL', 'regGCVM_CONTEXT10_CNTL_BASE_IDX',
'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT11_CNTL', 'regGCVM_CONTEXT11_CNTL_BASE_IDX',
'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT12_CNTL', 'regGCVM_CONTEXT12_CNTL_BASE_IDX',
'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT13_CNTL', 'regGCVM_CONTEXT13_CNTL_BASE_IDX',
'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT14_CNTL', 'regGCVM_CONTEXT14_CNTL_BASE_IDX',
'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT15_CNTL', 'regGCVM_CONTEXT15_CNTL_BASE_IDX',
'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT1_CNTL', 'regGCVM_CONTEXT1_CNTL_BASE_IDX',
'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT2_CNTL', 'regGCVM_CONTEXT2_CNTL_BASE_IDX',
'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT3_CNTL', 'regGCVM_CONTEXT3_CNTL_BASE_IDX',
'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT4_CNTL', 'regGCVM_CONTEXT4_CNTL_BASE_IDX',
'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT5_CNTL', 'regGCVM_CONTEXT5_CNTL_BASE_IDX',
'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT6_CNTL', 'regGCVM_CONTEXT6_CNTL_BASE_IDX',
'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT7_CNTL', 'regGCVM_CONTEXT7_CNTL_BASE_IDX',
'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT8_CNTL', 'regGCVM_CONTEXT8_CNTL_BASE_IDX',
'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT9_CNTL', 'regGCVM_CONTEXT9_CNTL_BASE_IDX',
'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32',
'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32',
'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32',
'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32',
'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32',
'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32',
'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
'regGCVM_CONTEXTS_DISABLE', 'regGCVM_CONTEXTS_DISABLE_BASE_IDX',
'regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32',
'regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX',
'regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32',
'regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX',
'regGCVM_DUMMY_PAGE_FAULT_CNTL',
'regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX',
'regGCVM_INVALIDATE_CNTL', 'regGCVM_INVALIDATE_CNTL_BASE_IDX',
'regGCVM_INVALIDATE_ENG0_ACK',
'regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG0_REQ',
'regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG0_SEM',
'regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG10_ACK',
'regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG10_REQ',
'regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG10_SEM',
'regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG11_ACK',
'regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG11_REQ',
'regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG11_SEM',
'regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG12_ACK',
'regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG12_REQ',
'regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG12_SEM',
'regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG13_ACK',
'regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG13_REQ',
'regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG13_SEM',
'regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG14_ACK',
'regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG14_REQ',
'regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG14_SEM',
'regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG15_ACK',
'regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG15_REQ',
'regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG15_SEM',
'regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG16_ACK',
'regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG16_REQ',
'regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG16_SEM',
'regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG17_ACK',
'regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG17_REQ',
'regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG17_SEM',
'regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG1_ACK',
'regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG1_REQ',
'regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG1_SEM',
'regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG2_ACK',
'regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG2_REQ',
'regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG2_SEM',
'regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG3_ACK',
'regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG3_REQ',
'regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG3_SEM',
'regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG4_ACK',
'regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG4_REQ',
'regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG4_SEM',
'regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG5_ACK',
'regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG5_REQ',
'regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG5_SEM',
'regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG6_ACK',
'regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG6_REQ',
'regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG6_SEM',
'regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG7_ACK',
'regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG7_REQ',
'regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG7_SEM',
'regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG8_ACK',
'regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG8_REQ',
'regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG8_SEM',
'regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX',
'regGCVM_INVALIDATE_ENG9_ACK',
'regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX',
'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32',
'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX',
'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32',
'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX',
'regGCVM_INVALIDATE_ENG9_REQ',
'regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX',
'regGCVM_INVALIDATE_ENG9_SEM',
'regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX',
'regGCVM_L2_BANK_SELECT_MASKS',
'regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX',
'regGCVM_L2_BANK_SELECT_RESERVED_CID',
'regGCVM_L2_BANK_SELECT_RESERVED_CID2',
'regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX',
'regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX',
'regGCVM_L2_CACHE_PARITY_CNTL',
'regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX',
'regGCVM_L2_CGTT_BUSY_CTRL', 'regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX',
'regGCVM_L2_CNTL', 'regGCVM_L2_CNTL2',
'regGCVM_L2_CNTL2_BASE_IDX', 'regGCVM_L2_CNTL3',
'regGCVM_L2_CNTL3_BASE_IDX', 'regGCVM_L2_CNTL4',
'regGCVM_L2_CNTL4_BASE_IDX', 'regGCVM_L2_CNTL5',
'regGCVM_L2_CNTL5_BASE_IDX', 'regGCVM_L2_CNTL_BASE_IDX',
'regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32',
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX',
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32',
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX',
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32',
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX',
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32',
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX',
'regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32',
'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX',
'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32',
'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX',
'regGCVM_L2_GCR_CNTL', 'regGCVM_L2_GCR_CNTL_BASE_IDX',
'regGCVM_L2_ICG_CTRL', 'regGCVM_L2_ICG_CTRL_BASE_IDX',
'regGCVM_L2_MM_GROUP_RT_CLASSES',
'regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX',
'regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
'regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
'regGCVM_L2_PROTECTION_FAULT_ADDR_HI32',
'regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX',
'regGCVM_L2_PROTECTION_FAULT_ADDR_LO32',
'regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX',
'regGCVM_L2_PROTECTION_FAULT_CNTL',
'regGCVM_L2_PROTECTION_FAULT_CNTL2',
'regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX',
'regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX',
'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32',
'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX',
'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32',
'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX',
'regGCVM_L2_PROTECTION_FAULT_MM_CNTL3',
'regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX',
'regGCVM_L2_PROTECTION_FAULT_MM_CNTL4',
'regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX',
'regGCVM_L2_PROTECTION_FAULT_STATUS',
'regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX',
'regGCVM_L2_PTE_CACHE_DUMP_CNTL',
'regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX',
'regGCVM_L2_PTE_CACHE_DUMP_READ',
'regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX', 'regGCVM_L2_STATUS',
'regGCVM_L2_STATUS_BASE_IDX', 'regGC_CAC_AGGR_GFXCLK_CYCLE',
'regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regGC_CAC_AGGR_LOWER',
'regGC_CAC_AGGR_LOWER_BASE_IDX', 'regGC_CAC_AGGR_UPPER',
'regGC_CAC_AGGR_UPPER_BASE_IDX', 'regGC_CAC_CTRL_1',
'regGC_CAC_CTRL_1_BASE_IDX', 'regGC_CAC_CTRL_2',
'regGC_CAC_CTRL_2_BASE_IDX', 'regGC_CAC_IND_DATA',
'regGC_CAC_IND_DATA_BASE_IDX', 'regGC_CAC_IND_INDEX',
'regGC_CAC_IND_INDEX_BASE_IDX', 'regGC_CAC_WEIGHT_CHC_0',
'regGC_CAC_WEIGHT_CHC_0_BASE_IDX', 'regGC_CAC_WEIGHT_CHC_1',
'regGC_CAC_WEIGHT_CHC_1_BASE_IDX', 'regGC_CAC_WEIGHT_CP_0',
'regGC_CAC_WEIGHT_CP_0_BASE_IDX', 'regGC_CAC_WEIGHT_CP_1',
'regGC_CAC_WEIGHT_CP_1_BASE_IDX', 'regGC_CAC_WEIGHT_EA_0',
'regGC_CAC_WEIGHT_EA_0_BASE_IDX', 'regGC_CAC_WEIGHT_EA_1',
'regGC_CAC_WEIGHT_EA_1_BASE_IDX', 'regGC_CAC_WEIGHT_EA_2',
'regGC_CAC_WEIGHT_EA_2_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_0',
'regGC_CAC_WEIGHT_GDS_0_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_1',
'regGC_CAC_WEIGHT_GDS_1_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_2',
'regGC_CAC_WEIGHT_GDS_2_BASE_IDX', 'regGC_CAC_WEIGHT_GE_0',
'regGC_CAC_WEIGHT_GE_0_BASE_IDX', 'regGC_CAC_WEIGHT_GE_1',
'regGC_CAC_WEIGHT_GE_1_BASE_IDX', 'regGC_CAC_WEIGHT_GE_2',
'regGC_CAC_WEIGHT_GE_2_BASE_IDX', 'regGC_CAC_WEIGHT_GE_3',
'regGC_CAC_WEIGHT_GE_3_BASE_IDX', 'regGC_CAC_WEIGHT_GE_4',
'regGC_CAC_WEIGHT_GE_4_BASE_IDX', 'regGC_CAC_WEIGHT_GE_5',
'regGC_CAC_WEIGHT_GE_5_BASE_IDX', 'regGC_CAC_WEIGHT_GE_6',
'regGC_CAC_WEIGHT_GE_6_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_0',
'regGC_CAC_WEIGHT_GL2C_0_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_1',
'regGC_CAC_WEIGHT_GL2C_1_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_2',
'regGC_CAC_WEIGHT_GL2C_2_BASE_IDX', 'regGC_CAC_WEIGHT_GRBM_0',
'regGC_CAC_WEIGHT_GRBM_0_BASE_IDX', 'regGC_CAC_WEIGHT_GUS_0',
'regGC_CAC_WEIGHT_GUS_0_BASE_IDX', 'regGC_CAC_WEIGHT_GUS_1',
'regGC_CAC_WEIGHT_GUS_1_BASE_IDX', 'regGC_CAC_WEIGHT_PH_0',
'regGC_CAC_WEIGHT_PH_0_BASE_IDX', 'regGC_CAC_WEIGHT_PH_1',
'regGC_CAC_WEIGHT_PH_1_BASE_IDX', 'regGC_CAC_WEIGHT_PH_2',
'regGC_CAC_WEIGHT_PH_2_BASE_IDX', 'regGC_CAC_WEIGHT_PH_3',
'regGC_CAC_WEIGHT_PH_3_BASE_IDX', 'regGC_CAC_WEIGHT_PMM_0',
'regGC_CAC_WEIGHT_PMM_0_BASE_IDX', 'regGC_CAC_WEIGHT_RLC_0',
'regGC_CAC_WEIGHT_RLC_0_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_0',
'regGC_CAC_WEIGHT_SDMA_0_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_1',
'regGC_CAC_WEIGHT_SDMA_1_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_2',
'regGC_CAC_WEIGHT_SDMA_2_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_3',
'regGC_CAC_WEIGHT_SDMA_3_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_4',
'regGC_CAC_WEIGHT_SDMA_4_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_5',
'regGC_CAC_WEIGHT_SDMA_5_BASE_IDX',
'regGC_CAC_WEIGHT_UTCL2_ROUTER_0',
'regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX',
'regGC_CAC_WEIGHT_UTCL2_ROUTER_1',
'regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX',
'regGC_CAC_WEIGHT_UTCL2_ROUTER_2',
'regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX',
'regGC_CAC_WEIGHT_UTCL2_ROUTER_3',
'regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX',
'regGC_CAC_WEIGHT_UTCL2_ROUTER_4',
'regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX',
'regGC_CAC_WEIGHT_UTCL2_VML2_0',
'regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX',
'regGC_CAC_WEIGHT_UTCL2_VML2_1',
'regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX',
'regGC_CAC_WEIGHT_UTCL2_VML2_2',
'regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX',
'regGC_CAC_WEIGHT_UTCL2_WALKER_0',
'regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX',
'regGC_CAC_WEIGHT_UTCL2_WALKER_1',
'regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX',
'regGC_CAC_WEIGHT_UTCL2_WALKER_2',
'regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX',
'regGC_EDC_CLK_MONITOR_CTRL',
'regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX', 'regGC_EDC_CTRL',
'regGC_EDC_CTRL_BASE_IDX', 'regGC_EDC_OVERFLOW',
'regGC_EDC_OVERFLOW_BASE_IDX', 'regGC_EDC_ROLLING_POWER_DELTA',
'regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX', 'regGC_EDC_STATUS',
'regGC_EDC_STATUS_BASE_IDX', 'regGC_EDC_STRETCH_CTRL',
'regGC_EDC_STRETCH_CTRL_BASE_IDX', 'regGC_EDC_STRETCH_THRESHOLD',
'regGC_EDC_STRETCH_THRESHOLD_BASE_IDX', 'regGC_EDC_THRESHOLD',
'regGC_EDC_THRESHOLD_BASE_IDX', 'regGC_IH_COOKIE_0_PTR',
'regGC_IH_COOKIE_0_PTR_BASE_IDX', 'regGC_THROTTLE_CTRL',
'regGC_THROTTLE_CTRL1', 'regGC_THROTTLE_CTRL1_BASE_IDX',
'regGC_THROTTLE_CTRL_BASE_IDX', 'regGC_THROTTLE_STATUS',
'regGC_THROTTLE_STATUS_BASE_IDX', 'regGC_USER_PRIM_CONFIG',
'regGC_USER_PRIM_CONFIG_BASE_IDX',
'regGC_USER_RB_BACKEND_DISABLE',
'regGC_USER_RB_BACKEND_DISABLE_BASE_IDX',
'regGC_USER_RB_REDUNDANCY', 'regGC_USER_RB_REDUNDANCY_BASE_IDX',
'regGC_USER_RMI_REDUNDANCY', 'regGC_USER_RMI_REDUNDANCY_BASE_IDX',
'regGC_USER_SA_UNIT_DISABLE',
'regGC_USER_SA_UNIT_DISABLE_BASE_IDX',
'regGC_USER_SHADER_ARRAY_CONFIG',
'regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX',
'regGC_USER_SHADER_RATE_CONFIG',
'regGC_USER_SHADER_RATE_CONFIG_BASE_IDX', 'regGDS_ATOM_BASE',
'regGDS_ATOM_BASE_BASE_IDX', 'regGDS_ATOM_CNTL',
'regGDS_ATOM_CNTL_BASE_IDX', 'regGDS_ATOM_COMPLETE',
'regGDS_ATOM_COMPLETE_BASE_IDX', 'regGDS_ATOM_DST',
'regGDS_ATOM_DST_BASE_IDX', 'regGDS_ATOM_OFFSET0',
'regGDS_ATOM_OFFSET0_BASE_IDX', 'regGDS_ATOM_OFFSET1',
'regGDS_ATOM_OFFSET1_BASE_IDX', 'regGDS_ATOM_OP',
'regGDS_ATOM_OP_BASE_IDX', 'regGDS_ATOM_READ0',
'regGDS_ATOM_READ0_BASE_IDX', 'regGDS_ATOM_READ0_U',
'regGDS_ATOM_READ0_U_BASE_IDX', 'regGDS_ATOM_READ1',
'regGDS_ATOM_READ1_BASE_IDX', 'regGDS_ATOM_READ1_U',
'regGDS_ATOM_READ1_U_BASE_IDX', 'regGDS_ATOM_SIZE',
'regGDS_ATOM_SIZE_BASE_IDX', 'regGDS_ATOM_SRC0',
'regGDS_ATOM_SRC0_BASE_IDX', 'regGDS_ATOM_SRC0_U',
'regGDS_ATOM_SRC0_U_BASE_IDX', 'regGDS_ATOM_SRC1',
'regGDS_ATOM_SRC1_BASE_IDX', 'regGDS_ATOM_SRC1_U',
'regGDS_ATOM_SRC1_U_BASE_IDX', 'regGDS_CNTL_STATUS',
'regGDS_CNTL_STATUS_BASE_IDX', 'regGDS_COMPUTE_MAX_WAVE_ID',
'regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX', 'regGDS_CONFIG',
'regGDS_CONFIG_BASE_IDX', 'regGDS_CS_CTXSW_CNT0',
'regGDS_CS_CTXSW_CNT0_BASE_IDX', 'regGDS_CS_CTXSW_CNT1',
'regGDS_CS_CTXSW_CNT1_BASE_IDX', 'regGDS_CS_CTXSW_CNT2',
'regGDS_CS_CTXSW_CNT2_BASE_IDX', 'regGDS_CS_CTXSW_CNT3',
'regGDS_CS_CTXSW_CNT3_BASE_IDX', 'regGDS_CS_CTXSW_STATUS',
'regGDS_CS_CTXSW_STATUS_BASE_IDX', 'regGDS_DSM_CNTL',
'regGDS_DSM_CNTL2', 'regGDS_DSM_CNTL2_BASE_IDX',
'regGDS_DSM_CNTL_BASE_IDX', 'regGDS_EDC_CNT',
'regGDS_EDC_CNT_BASE_IDX', 'regGDS_EDC_GRBM_CNT',
'regGDS_EDC_GRBM_CNT_BASE_IDX', 'regGDS_EDC_OA_DED',
'regGDS_EDC_OA_DED_BASE_IDX', 'regGDS_EDC_OA_PHY_CNT',
'regGDS_EDC_OA_PHY_CNT_BASE_IDX', 'regGDS_EDC_OA_PIPE_CNT',
'regGDS_EDC_OA_PIPE_CNT_BASE_IDX', 'regGDS_ENHANCE',
'regGDS_ENHANCE2', 'regGDS_ENHANCE2_BASE_IDX',
'regGDS_ENHANCE_BASE_IDX', 'regGDS_GFX_CTXSW_STATUS',
'regGDS_GFX_CTXSW_STATUS_BASE_IDX', 'regGDS_GS_0',
'regGDS_GS_0_BASE_IDX', 'regGDS_GS_1', 'regGDS_GS_1_BASE_IDX',
'regGDS_GS_2', 'regGDS_GS_2_BASE_IDX', 'regGDS_GS_3',
'regGDS_GS_3_BASE_IDX', 'regGDS_GS_CTXSW_CNT0',
'regGDS_GS_CTXSW_CNT0_BASE_IDX', 'regGDS_GS_CTXSW_CNT1',
'regGDS_GS_CTXSW_CNT1_BASE_IDX', 'regGDS_GS_CTXSW_CNT2',
'regGDS_GS_CTXSW_CNT2_BASE_IDX', 'regGDS_GS_CTXSW_CNT3',
'regGDS_GS_CTXSW_CNT3_BASE_IDX', 'regGDS_GWS_RESET0',
'regGDS_GWS_RESET0_BASE_IDX', 'regGDS_GWS_RESET1',
'regGDS_GWS_RESET1_BASE_IDX', 'regGDS_GWS_RESOURCE',
'regGDS_GWS_RESOURCE_BASE_IDX', 'regGDS_GWS_RESOURCE_CNT',
'regGDS_GWS_RESOURCE_CNTL', 'regGDS_GWS_RESOURCE_CNTL_BASE_IDX',
'regGDS_GWS_RESOURCE_CNT_BASE_IDX', 'regGDS_GWS_RESOURCE_RESET',
'regGDS_GWS_RESOURCE_RESET_BASE_IDX', 'regGDS_GWS_VMID0',
'regGDS_GWS_VMID0_BASE_IDX', 'regGDS_GWS_VMID1',
'regGDS_GWS_VMID10', 'regGDS_GWS_VMID10_BASE_IDX',
'regGDS_GWS_VMID11', 'regGDS_GWS_VMID11_BASE_IDX',
'regGDS_GWS_VMID12', 'regGDS_GWS_VMID12_BASE_IDX',
'regGDS_GWS_VMID13', 'regGDS_GWS_VMID13_BASE_IDX',
'regGDS_GWS_VMID14', 'regGDS_GWS_VMID14_BASE_IDX',
'regGDS_GWS_VMID15', 'regGDS_GWS_VMID15_BASE_IDX',
'regGDS_GWS_VMID1_BASE_IDX', 'regGDS_GWS_VMID2',
'regGDS_GWS_VMID2_BASE_IDX', 'regGDS_GWS_VMID3',
'regGDS_GWS_VMID3_BASE_IDX', 'regGDS_GWS_VMID4',
'regGDS_GWS_VMID4_BASE_IDX', 'regGDS_GWS_VMID5',
'regGDS_GWS_VMID5_BASE_IDX', 'regGDS_GWS_VMID6',
'regGDS_GWS_VMID6_BASE_IDX', 'regGDS_GWS_VMID7',
'regGDS_GWS_VMID7_BASE_IDX', 'regGDS_GWS_VMID8',
'regGDS_GWS_VMID8_BASE_IDX', 'regGDS_GWS_VMID9',
'regGDS_GWS_VMID9_BASE_IDX', 'regGDS_MEMORY_CLEAN',
'regGDS_MEMORY_CLEAN_BASE_IDX', 'regGDS_OA_ADDRESS',
'regGDS_OA_ADDRESS_BASE_IDX', 'regGDS_OA_CGPG_RESTORE',
'regGDS_OA_CGPG_RESTORE_BASE_IDX', 'regGDS_OA_CNTL',
'regGDS_OA_CNTL_BASE_IDX', 'regGDS_OA_COUNTER',
'regGDS_OA_COUNTER_BASE_IDX', 'regGDS_OA_INCDEC',
'regGDS_OA_INCDEC_BASE_IDX', 'regGDS_OA_RESET',
'regGDS_OA_RESET_BASE_IDX', 'regGDS_OA_RESET_MASK',
'regGDS_OA_RESET_MASK_BASE_IDX', 'regGDS_OA_RING_SIZE',
'regGDS_OA_RING_SIZE_BASE_IDX', 'regGDS_OA_VMID0',
'regGDS_OA_VMID0_BASE_IDX', 'regGDS_OA_VMID1', 'regGDS_OA_VMID10',
'regGDS_OA_VMID10_BASE_IDX', 'regGDS_OA_VMID11',
'regGDS_OA_VMID11_BASE_IDX', 'regGDS_OA_VMID12',
'regGDS_OA_VMID12_BASE_IDX', 'regGDS_OA_VMID13',
'regGDS_OA_VMID13_BASE_IDX', 'regGDS_OA_VMID14',
'regGDS_OA_VMID14_BASE_IDX', 'regGDS_OA_VMID15',
'regGDS_OA_VMID15_BASE_IDX', 'regGDS_OA_VMID1_BASE_IDX',
'regGDS_OA_VMID2', 'regGDS_OA_VMID2_BASE_IDX', 'regGDS_OA_VMID3',
'regGDS_OA_VMID3_BASE_IDX', 'regGDS_OA_VMID4',
'regGDS_OA_VMID4_BASE_IDX', 'regGDS_OA_VMID5',
'regGDS_OA_VMID5_BASE_IDX', 'regGDS_OA_VMID6',
'regGDS_OA_VMID6_BASE_IDX', 'regGDS_OA_VMID7',
'regGDS_OA_VMID7_BASE_IDX', 'regGDS_OA_VMID8',
'regGDS_OA_VMID8_BASE_IDX', 'regGDS_OA_VMID9',
'regGDS_OA_VMID9_BASE_IDX', 'regGDS_PERFCOUNTER0_HI',
'regGDS_PERFCOUNTER0_HI_BASE_IDX', 'regGDS_PERFCOUNTER0_LO',
'regGDS_PERFCOUNTER0_LO_BASE_IDX', 'regGDS_PERFCOUNTER0_SELECT',
'regGDS_PERFCOUNTER0_SELECT1',
'regGDS_PERFCOUNTER0_SELECT1_BASE_IDX',
'regGDS_PERFCOUNTER0_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER1_HI',
'regGDS_PERFCOUNTER1_HI_BASE_IDX', 'regGDS_PERFCOUNTER1_LO',
'regGDS_PERFCOUNTER1_LO_BASE_IDX', 'regGDS_PERFCOUNTER1_SELECT',
'regGDS_PERFCOUNTER1_SELECT1',
'regGDS_PERFCOUNTER1_SELECT1_BASE_IDX',
'regGDS_PERFCOUNTER1_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER2_HI',
'regGDS_PERFCOUNTER2_HI_BASE_IDX', 'regGDS_PERFCOUNTER2_LO',
'regGDS_PERFCOUNTER2_LO_BASE_IDX', 'regGDS_PERFCOUNTER2_SELECT',
'regGDS_PERFCOUNTER2_SELECT1',
'regGDS_PERFCOUNTER2_SELECT1_BASE_IDX',
'regGDS_PERFCOUNTER2_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER3_HI',
'regGDS_PERFCOUNTER3_HI_BASE_IDX', 'regGDS_PERFCOUNTER3_LO',
'regGDS_PERFCOUNTER3_LO_BASE_IDX', 'regGDS_PERFCOUNTER3_SELECT',
'regGDS_PERFCOUNTER3_SELECT1',
'regGDS_PERFCOUNTER3_SELECT1_BASE_IDX',
'regGDS_PERFCOUNTER3_SELECT_BASE_IDX', 'regGDS_PROTECTION_FAULT',
'regGDS_PROTECTION_FAULT_BASE_IDX', 'regGDS_PS_CTXSW_CNT0',
'regGDS_PS_CTXSW_CNT0_BASE_IDX', 'regGDS_PS_CTXSW_CNT1',
'regGDS_PS_CTXSW_CNT1_BASE_IDX', 'regGDS_PS_CTXSW_CNT2',
'regGDS_PS_CTXSW_CNT2_BASE_IDX', 'regGDS_PS_CTXSW_CNT3',
'regGDS_PS_CTXSW_CNT3_BASE_IDX', 'regGDS_PS_CTXSW_IDX',
'regGDS_PS_CTXSW_IDX_BASE_IDX', 'regGDS_RD_ADDR',
'regGDS_RD_ADDR_BASE_IDX', 'regGDS_RD_BURST_ADDR',
'regGDS_RD_BURST_ADDR_BASE_IDX', 'regGDS_RD_BURST_COUNT',
'regGDS_RD_BURST_COUNT_BASE_IDX', 'regGDS_RD_BURST_DATA',
'regGDS_RD_BURST_DATA_BASE_IDX', 'regGDS_RD_DATA',
'regGDS_RD_DATA_BASE_IDX', 'regGDS_STRMOUT_DWORDS_WRITTEN_0',
'regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX',
'regGDS_STRMOUT_DWORDS_WRITTEN_1',
'regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX',
'regGDS_STRMOUT_DWORDS_WRITTEN_2',
'regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX',
'regGDS_STRMOUT_DWORDS_WRITTEN_3',
'regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX',
'regGDS_STRMOUT_PRIMS_NEEDED_0_HI',
'regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX',
'regGDS_STRMOUT_PRIMS_NEEDED_0_LO',
'regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX',
'regGDS_STRMOUT_PRIMS_NEEDED_1_HI',
'regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX',
'regGDS_STRMOUT_PRIMS_NEEDED_1_LO',
'regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX',
'regGDS_STRMOUT_PRIMS_NEEDED_2_HI',
'regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX',
'regGDS_STRMOUT_PRIMS_NEEDED_2_LO',
'regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX',
'regGDS_STRMOUT_PRIMS_NEEDED_3_HI',
'regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX',
'regGDS_STRMOUT_PRIMS_NEEDED_3_LO',
'regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX',
'regGDS_STRMOUT_PRIMS_WRITTEN_0_HI',
'regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX',
'regGDS_STRMOUT_PRIMS_WRITTEN_0_LO',
'regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX',
'regGDS_STRMOUT_PRIMS_WRITTEN_1_HI',
'regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX',
'regGDS_STRMOUT_PRIMS_WRITTEN_1_LO',
'regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX',
'regGDS_STRMOUT_PRIMS_WRITTEN_2_HI',
'regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX',
'regGDS_STRMOUT_PRIMS_WRITTEN_2_LO',
'regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX',
'regGDS_STRMOUT_PRIMS_WRITTEN_3_HI',
'regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX',
'regGDS_STRMOUT_PRIMS_WRITTEN_3_LO',
'regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX', 'regGDS_VMID0_BASE',
'regGDS_VMID0_BASE_BASE_IDX', 'regGDS_VMID0_SIZE',
'regGDS_VMID0_SIZE_BASE_IDX', 'regGDS_VMID10_BASE',
'regGDS_VMID10_BASE_BASE_IDX', 'regGDS_VMID10_SIZE',
'regGDS_VMID10_SIZE_BASE_IDX', 'regGDS_VMID11_BASE',
'regGDS_VMID11_BASE_BASE_IDX', 'regGDS_VMID11_SIZE',
'regGDS_VMID11_SIZE_BASE_IDX', 'regGDS_VMID12_BASE',
'regGDS_VMID12_BASE_BASE_IDX', 'regGDS_VMID12_SIZE',
'regGDS_VMID12_SIZE_BASE_IDX', 'regGDS_VMID13_BASE',
'regGDS_VMID13_BASE_BASE_IDX', 'regGDS_VMID13_SIZE',
'regGDS_VMID13_SIZE_BASE_IDX', 'regGDS_VMID14_BASE',
'regGDS_VMID14_BASE_BASE_IDX', 'regGDS_VMID14_SIZE',
'regGDS_VMID14_SIZE_BASE_IDX', 'regGDS_VMID15_BASE',
'regGDS_VMID15_BASE_BASE_IDX', 'regGDS_VMID15_SIZE',
'regGDS_VMID15_SIZE_BASE_IDX', 'regGDS_VMID1_BASE',
'regGDS_VMID1_BASE_BASE_IDX', 'regGDS_VMID1_SIZE',
'regGDS_VMID1_SIZE_BASE_IDX', 'regGDS_VMID2_BASE',
'regGDS_VMID2_BASE_BASE_IDX', 'regGDS_VMID2_SIZE',
'regGDS_VMID2_SIZE_BASE_IDX', 'regGDS_VMID3_BASE',
'regGDS_VMID3_BASE_BASE_IDX', 'regGDS_VMID3_SIZE',
'regGDS_VMID3_SIZE_BASE_IDX', 'regGDS_VMID4_BASE',
'regGDS_VMID4_BASE_BASE_IDX', 'regGDS_VMID4_SIZE',
'regGDS_VMID4_SIZE_BASE_IDX', 'regGDS_VMID5_BASE',
'regGDS_VMID5_BASE_BASE_IDX', 'regGDS_VMID5_SIZE',
'regGDS_VMID5_SIZE_BASE_IDX', 'regGDS_VMID6_BASE',
'regGDS_VMID6_BASE_BASE_IDX', 'regGDS_VMID6_SIZE',
'regGDS_VMID6_SIZE_BASE_IDX', 'regGDS_VMID7_BASE',
'regGDS_VMID7_BASE_BASE_IDX', 'regGDS_VMID7_SIZE',
'regGDS_VMID7_SIZE_BASE_IDX', 'regGDS_VMID8_BASE',
'regGDS_VMID8_BASE_BASE_IDX', 'regGDS_VMID8_SIZE',
'regGDS_VMID8_SIZE_BASE_IDX', 'regGDS_VMID9_BASE',
'regGDS_VMID9_BASE_BASE_IDX', 'regGDS_VMID9_SIZE',
'regGDS_VMID9_SIZE_BASE_IDX', 'regGDS_VM_PROTECTION_FAULT',
'regGDS_VM_PROTECTION_FAULT_BASE_IDX', 'regGDS_WRITE_COMPLETE',
'regGDS_WRITE_COMPLETE_BASE_IDX', 'regGDS_WR_ADDR',
'regGDS_WR_ADDR_BASE_IDX', 'regGDS_WR_BURST_ADDR',
'regGDS_WR_BURST_ADDR_BASE_IDX', 'regGDS_WR_BURST_DATA',
'regGDS_WR_BURST_DATA_BASE_IDX', 'regGDS_WR_DATA',
'regGDS_WR_DATA_BASE_IDX', 'regGE1_PERFCOUNTER0_HI',
'regGE1_PERFCOUNTER0_HI_BASE_IDX', 'regGE1_PERFCOUNTER0_LO',
'regGE1_PERFCOUNTER0_LO_BASE_IDX', 'regGE1_PERFCOUNTER0_SELECT',
'regGE1_PERFCOUNTER0_SELECT1',
'regGE1_PERFCOUNTER0_SELECT1_BASE_IDX',
'regGE1_PERFCOUNTER0_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER1_HI',
'regGE1_PERFCOUNTER1_HI_BASE_IDX', 'regGE1_PERFCOUNTER1_LO',
'regGE1_PERFCOUNTER1_LO_BASE_IDX', 'regGE1_PERFCOUNTER1_SELECT',
'regGE1_PERFCOUNTER1_SELECT1',
'regGE1_PERFCOUNTER1_SELECT1_BASE_IDX',
'regGE1_PERFCOUNTER1_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER2_HI',
'regGE1_PERFCOUNTER2_HI_BASE_IDX', 'regGE1_PERFCOUNTER2_LO',
'regGE1_PERFCOUNTER2_LO_BASE_IDX', 'regGE1_PERFCOUNTER2_SELECT',
'regGE1_PERFCOUNTER2_SELECT1',
'regGE1_PERFCOUNTER2_SELECT1_BASE_IDX',
'regGE1_PERFCOUNTER2_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER3_HI',
'regGE1_PERFCOUNTER3_HI_BASE_IDX', 'regGE1_PERFCOUNTER3_LO',
'regGE1_PERFCOUNTER3_LO_BASE_IDX', 'regGE1_PERFCOUNTER3_SELECT',
'regGE1_PERFCOUNTER3_SELECT1',
'regGE1_PERFCOUNTER3_SELECT1_BASE_IDX',
'regGE1_PERFCOUNTER3_SELECT_BASE_IDX',
'regGE2_DIST_PERFCOUNTER0_HI',
'regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX',
'regGE2_DIST_PERFCOUNTER0_LO',
'regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX',
'regGE2_DIST_PERFCOUNTER0_SELECT',
'regGE2_DIST_PERFCOUNTER0_SELECT1',
'regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX',
'regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX',
'regGE2_DIST_PERFCOUNTER1_HI',
'regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX',
'regGE2_DIST_PERFCOUNTER1_LO',
'regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX',
'regGE2_DIST_PERFCOUNTER1_SELECT',
'regGE2_DIST_PERFCOUNTER1_SELECT1',
'regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX',
'regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX',
'regGE2_DIST_PERFCOUNTER2_HI',
'regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX',
'regGE2_DIST_PERFCOUNTER2_LO',
'regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX',
'regGE2_DIST_PERFCOUNTER2_SELECT',
'regGE2_DIST_PERFCOUNTER2_SELECT1',
'regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX',
'regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX',
'regGE2_DIST_PERFCOUNTER3_HI',
'regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX',
'regGE2_DIST_PERFCOUNTER3_LO',
'regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX',
'regGE2_DIST_PERFCOUNTER3_SELECT',
'regGE2_DIST_PERFCOUNTER3_SELECT1',
'regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX',
'regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX',
'regGE2_SE_CNTL_STATUS', 'regGE2_SE_CNTL_STATUS_BASE_IDX',
'regGE2_SE_PERFCOUNTER0_HI', 'regGE2_SE_PERFCOUNTER0_HI_BASE_IDX',
'regGE2_SE_PERFCOUNTER0_LO', 'regGE2_SE_PERFCOUNTER0_LO_BASE_IDX',
'regGE2_SE_PERFCOUNTER0_SELECT', 'regGE2_SE_PERFCOUNTER0_SELECT1',
'regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX',
'regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX',
'regGE2_SE_PERFCOUNTER1_HI', 'regGE2_SE_PERFCOUNTER1_HI_BASE_IDX',
'regGE2_SE_PERFCOUNTER1_LO', 'regGE2_SE_PERFCOUNTER1_LO_BASE_IDX',
'regGE2_SE_PERFCOUNTER1_SELECT', 'regGE2_SE_PERFCOUNTER1_SELECT1',
'regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX',
'regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX',
'regGE2_SE_PERFCOUNTER2_HI', 'regGE2_SE_PERFCOUNTER2_HI_BASE_IDX',
'regGE2_SE_PERFCOUNTER2_LO', 'regGE2_SE_PERFCOUNTER2_LO_BASE_IDX',
'regGE2_SE_PERFCOUNTER2_SELECT', 'regGE2_SE_PERFCOUNTER2_SELECT1',
'regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX',
'regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX',
'regGE2_SE_PERFCOUNTER3_HI', 'regGE2_SE_PERFCOUNTER3_HI_BASE_IDX',
'regGE2_SE_PERFCOUNTER3_LO', 'regGE2_SE_PERFCOUNTER3_LO_BASE_IDX',
'regGE2_SE_PERFCOUNTER3_SELECT', 'regGE2_SE_PERFCOUNTER3_SELECT1',
'regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX',
'regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX', 'regGE_CNTL',
'regGE_CNTL_BASE_IDX', 'regGE_GS_FAST_LAUNCH_WG_DIM',
'regGE_GS_FAST_LAUNCH_WG_DIM_1',
'regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX',
'regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX', 'regGE_INDX_OFFSET',
'regGE_INDX_OFFSET_BASE_IDX', 'regGE_MAX_OUTPUT_PER_SUBGROUP',
'regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX', 'regGE_MAX_VTX_INDX',
'regGE_MAX_VTX_INDX_BASE_IDX', 'regGE_MIN_VTX_INDX',
'regGE_MIN_VTX_INDX_BASE_IDX', 'regGE_MULTI_PRIM_IB_RESET_EN',
'regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX', 'regGE_NGG_SUBGRP_CNTL',
'regGE_NGG_SUBGRP_CNTL_BASE_IDX', 'regGE_PA_IF_SAFE_REG',
'regGE_PA_IF_SAFE_REG_BASE_IDX', 'regGE_PC_ALLOC',
'regGE_PC_ALLOC_BASE_IDX', 'regGE_PRIV_CONTROL',
'regGE_PRIV_CONTROL_BASE_IDX', 'regGE_RATE_CNTL_1',
'regGE_RATE_CNTL_1_BASE_IDX', 'regGE_RATE_CNTL_2',
'regGE_RATE_CNTL_2_BASE_IDX', 'regGE_SPI_IF_SAFE_REG',
'regGE_SPI_IF_SAFE_REG_BASE_IDX', 'regGE_STATUS',
'regGE_STATUS_BASE_IDX', 'regGE_STEREO_CNTL',
'regGE_STEREO_CNTL_BASE_IDX', 'regGE_USER_VGPR1',
'regGE_USER_VGPR1_BASE_IDX', 'regGE_USER_VGPR2',
'regGE_USER_VGPR2_BASE_IDX', 'regGE_USER_VGPR3',
'regGE_USER_VGPR3_BASE_IDX', 'regGE_USER_VGPR_EN',
'regGE_USER_VGPR_EN_BASE_IDX', 'regGFX_COPY_STATE',
'regGFX_COPY_STATE_BASE_IDX', 'regGFX_ICG_GL2C_CTRL',
'regGFX_ICG_GL2C_CTRL1', 'regGFX_ICG_GL2C_CTRL1_BASE_IDX',
'regGFX_ICG_GL2C_CTRL_BASE_IDX', 'regGFX_IMU_AEB_OVERRIDE',
'regGFX_IMU_AEB_OVERRIDE_BASE_IDX', 'regGFX_IMU_C2PMSG_0',
'regGFX_IMU_C2PMSG_0_BASE_IDX', 'regGFX_IMU_C2PMSG_1',
'regGFX_IMU_C2PMSG_10', 'regGFX_IMU_C2PMSG_10_BASE_IDX',
'regGFX_IMU_C2PMSG_11', 'regGFX_IMU_C2PMSG_11_BASE_IDX',
'regGFX_IMU_C2PMSG_12', 'regGFX_IMU_C2PMSG_12_BASE_IDX',
'regGFX_IMU_C2PMSG_13', 'regGFX_IMU_C2PMSG_13_BASE_IDX',
'regGFX_IMU_C2PMSG_14', 'regGFX_IMU_C2PMSG_14_BASE_IDX',
'regGFX_IMU_C2PMSG_15', 'regGFX_IMU_C2PMSG_15_BASE_IDX',
'regGFX_IMU_C2PMSG_16', 'regGFX_IMU_C2PMSG_16_BASE_IDX',
'regGFX_IMU_C2PMSG_17', 'regGFX_IMU_C2PMSG_17_BASE_IDX',
'regGFX_IMU_C2PMSG_18', 'regGFX_IMU_C2PMSG_18_BASE_IDX',
'regGFX_IMU_C2PMSG_19', 'regGFX_IMU_C2PMSG_19_BASE_IDX',
'regGFX_IMU_C2PMSG_1_BASE_IDX', 'regGFX_IMU_C2PMSG_2',
'regGFX_IMU_C2PMSG_20', 'regGFX_IMU_C2PMSG_20_BASE_IDX',
'regGFX_IMU_C2PMSG_21', 'regGFX_IMU_C2PMSG_21_BASE_IDX',
'regGFX_IMU_C2PMSG_22', 'regGFX_IMU_C2PMSG_22_BASE_IDX',
'regGFX_IMU_C2PMSG_23', 'regGFX_IMU_C2PMSG_23_BASE_IDX',
'regGFX_IMU_C2PMSG_24', 'regGFX_IMU_C2PMSG_24_BASE_IDX',
'regGFX_IMU_C2PMSG_25', 'regGFX_IMU_C2PMSG_25_BASE_IDX',
'regGFX_IMU_C2PMSG_26', 'regGFX_IMU_C2PMSG_26_BASE_IDX',
'regGFX_IMU_C2PMSG_27', 'regGFX_IMU_C2PMSG_27_BASE_IDX',
'regGFX_IMU_C2PMSG_28', 'regGFX_IMU_C2PMSG_28_BASE_IDX',
'regGFX_IMU_C2PMSG_29', 'regGFX_IMU_C2PMSG_29_BASE_IDX',
'regGFX_IMU_C2PMSG_2_BASE_IDX', 'regGFX_IMU_C2PMSG_3',
'regGFX_IMU_C2PMSG_30', 'regGFX_IMU_C2PMSG_30_BASE_IDX',
'regGFX_IMU_C2PMSG_31', 'regGFX_IMU_C2PMSG_31_BASE_IDX',
'regGFX_IMU_C2PMSG_32', 'regGFX_IMU_C2PMSG_32_BASE_IDX',
'regGFX_IMU_C2PMSG_33', 'regGFX_IMU_C2PMSG_33_BASE_IDX',
'regGFX_IMU_C2PMSG_34', 'regGFX_IMU_C2PMSG_34_BASE_IDX',
'regGFX_IMU_C2PMSG_35', 'regGFX_IMU_C2PMSG_35_BASE_IDX',
'regGFX_IMU_C2PMSG_36', 'regGFX_IMU_C2PMSG_36_BASE_IDX',
'regGFX_IMU_C2PMSG_37', 'regGFX_IMU_C2PMSG_37_BASE_IDX',
'regGFX_IMU_C2PMSG_38', 'regGFX_IMU_C2PMSG_38_BASE_IDX',
'regGFX_IMU_C2PMSG_39', 'regGFX_IMU_C2PMSG_39_BASE_IDX',
'regGFX_IMU_C2PMSG_3_BASE_IDX', 'regGFX_IMU_C2PMSG_4',
'regGFX_IMU_C2PMSG_40', 'regGFX_IMU_C2PMSG_40_BASE_IDX',
'regGFX_IMU_C2PMSG_41', 'regGFX_IMU_C2PMSG_41_BASE_IDX',
'regGFX_IMU_C2PMSG_42', 'regGFX_IMU_C2PMSG_42_BASE_IDX',
'regGFX_IMU_C2PMSG_43', 'regGFX_IMU_C2PMSG_43_BASE_IDX',
'regGFX_IMU_C2PMSG_44', 'regGFX_IMU_C2PMSG_44_BASE_IDX',
'regGFX_IMU_C2PMSG_45', 'regGFX_IMU_C2PMSG_45_BASE_IDX',
'regGFX_IMU_C2PMSG_46', 'regGFX_IMU_C2PMSG_46_BASE_IDX',
'regGFX_IMU_C2PMSG_47', 'regGFX_IMU_C2PMSG_47_BASE_IDX',
'regGFX_IMU_C2PMSG_4_BASE_IDX', 'regGFX_IMU_C2PMSG_5',
'regGFX_IMU_C2PMSG_5_BASE_IDX', 'regGFX_IMU_C2PMSG_6',
'regGFX_IMU_C2PMSG_6_BASE_IDX', 'regGFX_IMU_C2PMSG_7',
'regGFX_IMU_C2PMSG_7_BASE_IDX', 'regGFX_IMU_C2PMSG_8',
'regGFX_IMU_C2PMSG_8_BASE_IDX', 'regGFX_IMU_C2PMSG_9',
'regGFX_IMU_C2PMSG_9_BASE_IDX', 'regGFX_IMU_C2PMSG_ACCESS_CTRL0',
'regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX',
'regGFX_IMU_C2PMSG_ACCESS_CTRL1',
'regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX', 'regGFX_IMU_CLK_CTRL',
'regGFX_IMU_CLK_CTRL_BASE_IDX', 'regGFX_IMU_CORE_CTRL',
'regGFX_IMU_CORE_CTRL_BASE_IDX', 'regGFX_IMU_CORE_INT_STATUS',
'regGFX_IMU_CORE_INT_STATUS_BASE_IDX', 'regGFX_IMU_CORE_STATUS',
'regGFX_IMU_CORE_STATUS_BASE_IDX', 'regGFX_IMU_DOORBELL_CONTROL',
'regGFX_IMU_DOORBELL_CONTROL_BASE_IDX', 'regGFX_IMU_DPM_ACC',
'regGFX_IMU_DPM_ACC_BASE_IDX', 'regGFX_IMU_DPM_CONTROL',
'regGFX_IMU_DPM_CONTROL_BASE_IDX', 'regGFX_IMU_DPM_REF_COUNTER',
'regGFX_IMU_DPM_REF_COUNTER_BASE_IDX', 'regGFX_IMU_D_RAM_ADDR',
'regGFX_IMU_D_RAM_ADDR_BASE_IDX', 'regGFX_IMU_D_RAM_DATA',
'regGFX_IMU_D_RAM_DATA_BASE_IDX', 'regGFX_IMU_FENCE_CTRL',
'regGFX_IMU_FENCE_CTRL_BASE_IDX', 'regGFX_IMU_FENCE_LOG_ADDR',
'regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX', 'regGFX_IMU_FENCE_LOG_INIT',
'regGFX_IMU_FENCE_LOG_INIT_BASE_IDX', 'regGFX_IMU_FUSESTRAP',
'regGFX_IMU_FUSE_CTRL', 'regGFX_IMU_FUSE_CTRL_BASE_IDX',
'regGFX_IMU_FW_GTS_HI', 'regGFX_IMU_FW_GTS_HI_BASE_IDX',
'regGFX_IMU_FW_GTS_LO', 'regGFX_IMU_FW_GTS_LO_BASE_IDX',
'regGFX_IMU_GAP_PWROK', 'regGFX_IMU_GAP_PWROK_BASE_IDX',
'regGFX_IMU_GFXCLK_BYPASS_CTRL',
'regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX',
'regGFX_IMU_GFX_IH_GASKET_CTRL',
'regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX',
'regGFX_IMU_GFX_ISO_CTRL', 'regGFX_IMU_GFX_ISO_CTRL_BASE_IDX',
'regGFX_IMU_GFX_RESET_CTRL', 'regGFX_IMU_GFX_RESET_CTRL_BASE_IDX',
'regGFX_IMU_GTS_OFFSET_HI', 'regGFX_IMU_GTS_OFFSET_HI_BASE_IDX',
'regGFX_IMU_GTS_OFFSET_LO', 'regGFX_IMU_GTS_OFFSET_LO_BASE_IDX',
'regGFX_IMU_IH_CTRL_1', 'regGFX_IMU_IH_CTRL_1_BASE_IDX',
'regGFX_IMU_IH_CTRL_2', 'regGFX_IMU_IH_CTRL_2_BASE_IDX',
'regGFX_IMU_IH_CTRL_3', 'regGFX_IMU_IH_CTRL_3_BASE_IDX',
'regGFX_IMU_IH_STATUS', 'regGFX_IMU_IH_STATUS_BASE_IDX',
'regGFX_IMU_I_RAM_ADDR', 'regGFX_IMU_I_RAM_ADDR_BASE_IDX',
'regGFX_IMU_I_RAM_DATA', 'regGFX_IMU_I_RAM_DATA_BASE_IDX',
'regGFX_IMU_MP1_MUTEX', 'regGFX_IMU_MP1_MUTEX_BASE_IDX',
'regGFX_IMU_MSG_FLAGS', 'regGFX_IMU_MSG_FLAGS_BASE_IDX',
'regGFX_IMU_PIC_INTR', 'regGFX_IMU_PIC_INTR_BASE_IDX',
'regGFX_IMU_PIC_INTR_ID', 'regGFX_IMU_PIC_INTR_ID_BASE_IDX',
'regGFX_IMU_PIC_INT_EDGE', 'regGFX_IMU_PIC_INT_EDGE_BASE_IDX',
'regGFX_IMU_PIC_INT_LVL', 'regGFX_IMU_PIC_INT_LVL_BASE_IDX',
'regGFX_IMU_PIC_INT_MASK', 'regGFX_IMU_PIC_INT_MASK_BASE_IDX',
'regGFX_IMU_PIC_INT_PRI_0', 'regGFX_IMU_PIC_INT_PRI_0_BASE_IDX',
'regGFX_IMU_PIC_INT_PRI_1', 'regGFX_IMU_PIC_INT_PRI_1_BASE_IDX',
'regGFX_IMU_PIC_INT_PRI_2', 'regGFX_IMU_PIC_INT_PRI_2_BASE_IDX',
'regGFX_IMU_PIC_INT_PRI_3', 'regGFX_IMU_PIC_INT_PRI_3_BASE_IDX',
'regGFX_IMU_PIC_INT_PRI_4', 'regGFX_IMU_PIC_INT_PRI_4_BASE_IDX',
'regGFX_IMU_PIC_INT_PRI_5', 'regGFX_IMU_PIC_INT_PRI_5_BASE_IDX',
'regGFX_IMU_PIC_INT_PRI_6', 'regGFX_IMU_PIC_INT_PRI_6_BASE_IDX',
'regGFX_IMU_PIC_INT_PRI_7', 'regGFX_IMU_PIC_INT_PRI_7_BASE_IDX',
'regGFX_IMU_PIC_INT_STATUS', 'regGFX_IMU_PIC_INT_STATUS_BASE_IDX',
'regGFX_IMU_PROGRAM_CTR', 'regGFX_IMU_PROGRAM_CTR_BASE_IDX',
'regGFX_IMU_PWRMGT_IRQ_CTRL',
'regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX', 'regGFX_IMU_PWROK',
'regGFX_IMU_PWROKRAW', 'regGFX_IMU_PWROKRAW_BASE_IDX',
'regGFX_IMU_PWROK_BASE_IDX', 'regGFX_IMU_RESETn',
'regGFX_IMU_RESETn_BASE_IDX', 'regGFX_IMU_RLC_BOOTLOADER_ADDR_HI',
'regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX',
'regGFX_IMU_RLC_BOOTLOADER_ADDR_LO',
'regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX',
'regGFX_IMU_RLC_BOOTLOADER_SIZE',
'regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX',
'regGFX_IMU_RLC_CG_CTRL', 'regGFX_IMU_RLC_CG_CTRL_BASE_IDX',
'regGFX_IMU_RLC_CMD', 'regGFX_IMU_RLC_CMD_BASE_IDX',
'regGFX_IMU_RLC_DATA_0', 'regGFX_IMU_RLC_DATA_0_BASE_IDX',
'regGFX_IMU_RLC_DATA_1', 'regGFX_IMU_RLC_DATA_1_BASE_IDX',
'regGFX_IMU_RLC_DATA_2', 'regGFX_IMU_RLC_DATA_2_BASE_IDX',
'regGFX_IMU_RLC_DATA_3', 'regGFX_IMU_RLC_DATA_3_BASE_IDX',
'regGFX_IMU_RLC_DATA_4', 'regGFX_IMU_RLC_DATA_4_BASE_IDX',
'regGFX_IMU_RLC_GTS_OFFSET_HI',
'regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX',
'regGFX_IMU_RLC_GTS_OFFSET_LO',
'regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX',
'regGFX_IMU_RLC_MSG_STATUS', 'regGFX_IMU_RLC_MSG_STATUS_BASE_IDX',
'regGFX_IMU_RLC_MUTEX', 'regGFX_IMU_RLC_MUTEX_BASE_IDX',
'regGFX_IMU_RLC_OVERRIDE', 'regGFX_IMU_RLC_OVERRIDE_BASE_IDX',
'regGFX_IMU_RLC_RAM_ADDR_HIGH',
'regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX',
'regGFX_IMU_RLC_RAM_ADDR_LOW',
'regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX', 'regGFX_IMU_RLC_RAM_DATA',
'regGFX_IMU_RLC_RAM_DATA_BASE_IDX', 'regGFX_IMU_RLC_RAM_INDEX',
'regGFX_IMU_RLC_RAM_INDEX_BASE_IDX',
'regGFX_IMU_RLC_RESET_VECTOR',
'regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX', 'regGFX_IMU_RLC_STATUS',
'regGFX_IMU_RLC_STATUS_BASE_IDX', 'regGFX_IMU_RLC_THROTTLE_GFX',
'regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX', 'regGFX_IMU_SCRATCH_0',
'regGFX_IMU_SCRATCH_0_BASE_IDX', 'regGFX_IMU_SCRATCH_1',
'regGFX_IMU_SCRATCH_10', 'regGFX_IMU_SCRATCH_10_BASE_IDX',
'regGFX_IMU_SCRATCH_11', 'regGFX_IMU_SCRATCH_11_BASE_IDX',
'regGFX_IMU_SCRATCH_12', 'regGFX_IMU_SCRATCH_12_BASE_IDX',
'regGFX_IMU_SCRATCH_13', 'regGFX_IMU_SCRATCH_13_BASE_IDX',
'regGFX_IMU_SCRATCH_14', 'regGFX_IMU_SCRATCH_14_BASE_IDX',
'regGFX_IMU_SCRATCH_15', 'regGFX_IMU_SCRATCH_15_BASE_IDX',
'regGFX_IMU_SCRATCH_1_BASE_IDX', 'regGFX_IMU_SCRATCH_2',
'regGFX_IMU_SCRATCH_2_BASE_IDX', 'regGFX_IMU_SCRATCH_3',
'regGFX_IMU_SCRATCH_3_BASE_IDX', 'regGFX_IMU_SCRATCH_4',
'regGFX_IMU_SCRATCH_4_BASE_IDX', 'regGFX_IMU_SCRATCH_5',
'regGFX_IMU_SCRATCH_5_BASE_IDX', 'regGFX_IMU_SCRATCH_6',
'regGFX_IMU_SCRATCH_6_BASE_IDX', 'regGFX_IMU_SCRATCH_7',
'regGFX_IMU_SCRATCH_7_BASE_IDX', 'regGFX_IMU_SCRATCH_8',
'regGFX_IMU_SCRATCH_8_BASE_IDX', 'regGFX_IMU_SCRATCH_9',
'regGFX_IMU_SCRATCH_9_BASE_IDX', 'regGFX_IMU_SMUIO_VIDCHG_CTRL',
'regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX', 'regGFX_IMU_SOC_ADDR',
'regGFX_IMU_SOC_ADDR_BASE_IDX', 'regGFX_IMU_SOC_DATA',
'regGFX_IMU_SOC_DATA_BASE_IDX', 'regGFX_IMU_SOC_REQ',
'regGFX_IMU_SOC_REQ_BASE_IDX', 'regGFX_IMU_STATUS',
'regGFX_IMU_STATUS_BASE_IDX', 'regGFX_IMU_TELEMETRY',
'regGFX_IMU_TELEMETRY_BASE_IDX', 'regGFX_IMU_TELEMETRY_DATA',
'regGFX_IMU_TELEMETRY_DATA_BASE_IDX',
'regGFX_IMU_TELEMETRY_TEMPERATURE',
'regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX',
'regGFX_IMU_TIMER0_CMP0', 'regGFX_IMU_TIMER0_CMP0_BASE_IDX',
'regGFX_IMU_TIMER0_CMP1', 'regGFX_IMU_TIMER0_CMP1_BASE_IDX',
'regGFX_IMU_TIMER0_CMP3', 'regGFX_IMU_TIMER0_CMP3_BASE_IDX',
'regGFX_IMU_TIMER0_CMP_AUTOINC',
'regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX',
'regGFX_IMU_TIMER0_CMP_INTEN',
'regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER0_CTRL0',
'regGFX_IMU_TIMER0_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER0_CTRL1',
'regGFX_IMU_TIMER0_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER0_VALUE',
'regGFX_IMU_TIMER0_VALUE_BASE_IDX', 'regGFX_IMU_TIMER1_CMP0',
'regGFX_IMU_TIMER1_CMP0_BASE_IDX', 'regGFX_IMU_TIMER1_CMP1',
'regGFX_IMU_TIMER1_CMP1_BASE_IDX', 'regGFX_IMU_TIMER1_CMP3',
'regGFX_IMU_TIMER1_CMP3_BASE_IDX',
'regGFX_IMU_TIMER1_CMP_AUTOINC',
'regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX',
'regGFX_IMU_TIMER1_CMP_INTEN',
'regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER1_CTRL0',
'regGFX_IMU_TIMER1_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER1_CTRL1',
'regGFX_IMU_TIMER1_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER1_VALUE',
'regGFX_IMU_TIMER1_VALUE_BASE_IDX', 'regGFX_IMU_TIMER2_CMP0',
'regGFX_IMU_TIMER2_CMP0_BASE_IDX', 'regGFX_IMU_TIMER2_CMP1',
'regGFX_IMU_TIMER2_CMP1_BASE_IDX', 'regGFX_IMU_TIMER2_CMP3',
'regGFX_IMU_TIMER2_CMP3_BASE_IDX',
'regGFX_IMU_TIMER2_CMP_AUTOINC',
'regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX',
'regGFX_IMU_TIMER2_CMP_INTEN',
'regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER2_CTRL0',
'regGFX_IMU_TIMER2_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER2_CTRL1',
'regGFX_IMU_TIMER2_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER2_VALUE',
'regGFX_IMU_TIMER2_VALUE_BASE_IDX', 'regGFX_IMU_VDCI_RESET_CTRL',
'regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX', 'regGFX_IMU_VF_CTRL',
'regGFX_IMU_VF_CTRL_BASE_IDX', 'regGFX_PIPE_CONTROL',
'regGFX_PIPE_CONTROL_BASE_IDX', 'regGFX_PIPE_PRIORITY',
'regGFX_PIPE_PRIORITY_BASE_IDX', 'regGL1A_PERFCOUNTER0_HI',
'regGL1A_PERFCOUNTER0_HI_BASE_IDX', 'regGL1A_PERFCOUNTER0_LO',
'regGL1A_PERFCOUNTER0_LO_BASE_IDX', 'regGL1A_PERFCOUNTER0_SELECT',
'regGL1A_PERFCOUNTER0_SELECT1',
'regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX',
'regGL1A_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER1_HI',
'regGL1A_PERFCOUNTER1_HI_BASE_IDX', 'regGL1A_PERFCOUNTER1_LO',
'regGL1A_PERFCOUNTER1_LO_BASE_IDX', 'regGL1A_PERFCOUNTER1_SELECT',
'regGL1A_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER2_HI',
'regGL1A_PERFCOUNTER2_HI_BASE_IDX', 'regGL1A_PERFCOUNTER2_LO',
'regGL1A_PERFCOUNTER2_LO_BASE_IDX', 'regGL1A_PERFCOUNTER2_SELECT',
'regGL1A_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER3_HI',
'regGL1A_PERFCOUNTER3_HI_BASE_IDX', 'regGL1A_PERFCOUNTER3_LO',
'regGL1A_PERFCOUNTER3_LO_BASE_IDX', 'regGL1A_PERFCOUNTER3_SELECT',
'regGL1A_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER0_HI',
'regGL1C_PERFCOUNTER0_HI_BASE_IDX', 'regGL1C_PERFCOUNTER0_LO',
'regGL1C_PERFCOUNTER0_LO_BASE_IDX', 'regGL1C_PERFCOUNTER0_SELECT',
'regGL1C_PERFCOUNTER0_SELECT1',
'regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX',
'regGL1C_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER1_HI',
'regGL1C_PERFCOUNTER1_HI_BASE_IDX', 'regGL1C_PERFCOUNTER1_LO',
'regGL1C_PERFCOUNTER1_LO_BASE_IDX', 'regGL1C_PERFCOUNTER1_SELECT',
'regGL1C_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER2_HI',
'regGL1C_PERFCOUNTER2_HI_BASE_IDX', 'regGL1C_PERFCOUNTER2_LO',
'regGL1C_PERFCOUNTER2_LO_BASE_IDX', 'regGL1C_PERFCOUNTER2_SELECT',
'regGL1C_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER3_HI',
'regGL1C_PERFCOUNTER3_HI_BASE_IDX', 'regGL1C_PERFCOUNTER3_LO',
'regGL1C_PERFCOUNTER3_LO_BASE_IDX', 'regGL1C_PERFCOUNTER3_SELECT',
'regGL1C_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL1C_STATUS',
'regGL1C_STATUS_BASE_IDX', 'regGL1C_UTCL0_CNTL1',
'regGL1C_UTCL0_CNTL1_BASE_IDX', 'regGL1C_UTCL0_CNTL2',
'regGL1C_UTCL0_CNTL2_BASE_IDX', 'regGL1C_UTCL0_RETRY',
'regGL1C_UTCL0_RETRY_BASE_IDX', 'regGL1C_UTCL0_STATUS',
'regGL1C_UTCL0_STATUS_BASE_IDX', 'regGL1H_ARB_CTRL',
'regGL1H_ARB_CTRL_BASE_IDX', 'regGL1H_ARB_STATUS',
'regGL1H_ARB_STATUS_BASE_IDX', 'regGL1H_BURST_CTRL',
'regGL1H_BURST_CTRL_BASE_IDX', 'regGL1H_BURST_MASK',
'regGL1H_BURST_MASK_BASE_IDX', 'regGL1H_GL1_CREDITS',
'regGL1H_GL1_CREDITS_BASE_IDX', 'regGL1H_ICG_CTRL',
'regGL1H_ICG_CTRL_BASE_IDX', 'regGL1H_PERFCOUNTER0_HI',
'regGL1H_PERFCOUNTER0_HI_BASE_IDX', 'regGL1H_PERFCOUNTER0_LO',
'regGL1H_PERFCOUNTER0_LO_BASE_IDX', 'regGL1H_PERFCOUNTER0_SELECT',
'regGL1H_PERFCOUNTER0_SELECT1',
'regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX',
'regGL1H_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER1_HI',
'regGL1H_PERFCOUNTER1_HI_BASE_IDX', 'regGL1H_PERFCOUNTER1_LO',
'regGL1H_PERFCOUNTER1_LO_BASE_IDX', 'regGL1H_PERFCOUNTER1_SELECT',
'regGL1H_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER2_HI',
'regGL1H_PERFCOUNTER2_HI_BASE_IDX', 'regGL1H_PERFCOUNTER2_LO',
'regGL1H_PERFCOUNTER2_LO_BASE_IDX', 'regGL1H_PERFCOUNTER2_SELECT',
'regGL1H_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER3_HI',
'regGL1H_PERFCOUNTER3_HI_BASE_IDX', 'regGL1H_PERFCOUNTER3_LO',
'regGL1H_PERFCOUNTER3_LO_BASE_IDX', 'regGL1H_PERFCOUNTER3_SELECT',
'regGL1H_PERFCOUNTER3_SELECT_BASE_IDX',
'regGL1I_GL1R_MGCG_OVERRIDE',
'regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX',
'regGL1I_GL1R_REP_FGCG_OVERRIDE',
'regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX', 'regGL1_ARB_STATUS',
'regGL1_ARB_STATUS_BASE_IDX', 'regGL1_DRAM_BURST_MASK',
'regGL1_DRAM_BURST_MASK_BASE_IDX', 'regGL1_PIPE_STEER',
'regGL1_PIPE_STEER_BASE_IDX', 'regGL2A_ADDR_MATCH_CTRL',
'regGL2A_ADDR_MATCH_CTRL_BASE_IDX', 'regGL2A_ADDR_MATCH_MASK',
'regGL2A_ADDR_MATCH_MASK_BASE_IDX', 'regGL2A_ADDR_MATCH_SIZE',
'regGL2A_ADDR_MATCH_SIZE_BASE_IDX', 'regGL2A_PERFCOUNTER0_HI',
'regGL2A_PERFCOUNTER0_HI_BASE_IDX', 'regGL2A_PERFCOUNTER0_LO',
'regGL2A_PERFCOUNTER0_LO_BASE_IDX', 'regGL2A_PERFCOUNTER0_SELECT',
'regGL2A_PERFCOUNTER0_SELECT1',
'regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX',
'regGL2A_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER1_HI',
'regGL2A_PERFCOUNTER1_HI_BASE_IDX', 'regGL2A_PERFCOUNTER1_LO',
'regGL2A_PERFCOUNTER1_LO_BASE_IDX', 'regGL2A_PERFCOUNTER1_SELECT',
'regGL2A_PERFCOUNTER1_SELECT1',
'regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX',
'regGL2A_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER2_HI',
'regGL2A_PERFCOUNTER2_HI_BASE_IDX', 'regGL2A_PERFCOUNTER2_LO',
'regGL2A_PERFCOUNTER2_LO_BASE_IDX', 'regGL2A_PERFCOUNTER2_SELECT',
'regGL2A_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER3_HI',
'regGL2A_PERFCOUNTER3_HI_BASE_IDX', 'regGL2A_PERFCOUNTER3_LO',
'regGL2A_PERFCOUNTER3_LO_BASE_IDX', 'regGL2A_PERFCOUNTER3_SELECT',
'regGL2A_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL2A_PRIORITY_CTRL',
'regGL2A_PRIORITY_CTRL_BASE_IDX', 'regGL2A_RESP_THROTTLE_CTRL',
'regGL2A_RESP_THROTTLE_CTRL_BASE_IDX', 'regGL2C_ADDR_MATCH_MASK',
'regGL2C_ADDR_MATCH_MASK_BASE_IDX', 'regGL2C_ADDR_MATCH_SIZE',
'regGL2C_ADDR_MATCH_SIZE_BASE_IDX', 'regGL2C_CM_CTRL0',
'regGL2C_CM_CTRL0_BASE_IDX', 'regGL2C_CM_CTRL1',
'regGL2C_CM_CTRL1_BASE_IDX', 'regGL2C_CM_STALL',
'regGL2C_CM_STALL_BASE_IDX', 'regGL2C_CTRL', 'regGL2C_CTRL2',
'regGL2C_CTRL2_BASE_IDX', 'regGL2C_CTRL3',
'regGL2C_CTRL3_BASE_IDX', 'regGL2C_CTRL4',
'regGL2C_CTRL4_BASE_IDX', 'regGL2C_CTRL_BASE_IDX',
'regGL2C_DISCARD_STALL_CTRL',
'regGL2C_DISCARD_STALL_CTRL_BASE_IDX', 'regGL2C_LB_CTR_CTRL',
'regGL2C_LB_CTR_CTRL_BASE_IDX', 'regGL2C_LB_CTR_SEL0',
'regGL2C_LB_CTR_SEL0_BASE_IDX', 'regGL2C_LB_CTR_SEL1',
'regGL2C_LB_CTR_SEL1_BASE_IDX', 'regGL2C_LB_DATA0',
'regGL2C_LB_DATA0_BASE_IDX', 'regGL2C_LB_DATA1',
'regGL2C_LB_DATA1_BASE_IDX', 'regGL2C_LB_DATA2',
'regGL2C_LB_DATA2_BASE_IDX', 'regGL2C_LB_DATA3',
'regGL2C_LB_DATA3_BASE_IDX', 'regGL2C_PERFCOUNTER0_HI',
'regGL2C_PERFCOUNTER0_HI_BASE_IDX', 'regGL2C_PERFCOUNTER0_LO',
'regGL2C_PERFCOUNTER0_LO_BASE_IDX', 'regGL2C_PERFCOUNTER0_SELECT',
'regGL2C_PERFCOUNTER0_SELECT1',
'regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX',
'regGL2C_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER1_HI',
'regGL2C_PERFCOUNTER1_HI_BASE_IDX', 'regGL2C_PERFCOUNTER1_LO',
'regGL2C_PERFCOUNTER1_LO_BASE_IDX', 'regGL2C_PERFCOUNTER1_SELECT',
'regGL2C_PERFCOUNTER1_SELECT1',
'regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX',
'regGL2C_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER2_HI',
'regGL2C_PERFCOUNTER2_HI_BASE_IDX', 'regGL2C_PERFCOUNTER2_LO',
'regGL2C_PERFCOUNTER2_LO_BASE_IDX', 'regGL2C_PERFCOUNTER2_SELECT',
'regGL2C_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER3_HI',
'regGL2C_PERFCOUNTER3_HI_BASE_IDX', 'regGL2C_PERFCOUNTER3_LO',
'regGL2C_PERFCOUNTER3_LO_BASE_IDX', 'regGL2C_PERFCOUNTER3_SELECT',
'regGL2C_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL2C_SOFT_RESET',
'regGL2C_SOFT_RESET_BASE_IDX', 'regGL2C_WBINVL2',
'regGL2C_WBINVL2_BASE_IDX', 'regGL2_PIPE_STEER_0',
'regGL2_PIPE_STEER_0_BASE_IDX', 'regGL2_PIPE_STEER_1',
'regGL2_PIPE_STEER_1_BASE_IDX', 'regGL2_PIPE_STEER_2',
'regGL2_PIPE_STEER_2_BASE_IDX', 'regGL2_PIPE_STEER_3',
'regGL2_PIPE_STEER_3_BASE_IDX', 'regGRBM_CAM_DATA',
'regGRBM_CAM_DATA_BASE_IDX', 'regGRBM_CAM_DATA_UPPER',
'regGRBM_CAM_DATA_UPPER_BASE_IDX', 'regGRBM_CAM_INDEX',
'regGRBM_CAM_INDEX_BASE_IDX', 'regGRBM_CHIP_REVISION',
'regGRBM_CHIP_REVISION_BASE_IDX', 'regGRBM_CNTL',
'regGRBM_CNTL_BASE_IDX', 'regGRBM_DSM_BYPASS',
'regGRBM_DSM_BYPASS_BASE_IDX', 'regGRBM_FENCE_RANGE0',
'regGRBM_FENCE_RANGE0_BASE_IDX', 'regGRBM_FENCE_RANGE1',
'regGRBM_FENCE_RANGE1_BASE_IDX', 'regGRBM_GFX_CLKEN_CNTL',
'regGRBM_GFX_CLKEN_CNTL_BASE_IDX', 'regGRBM_GFX_CNTL',
'regGRBM_GFX_CNTL_BASE_IDX', 'regGRBM_GFX_CNTL_SR_DATA',
'regGRBM_GFX_CNTL_SR_DATA_BASE_IDX', 'regGRBM_GFX_CNTL_SR_SELECT',
'regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX', 'regGRBM_GFX_INDEX',
'regGRBM_GFX_INDEX_BASE_IDX', 'regGRBM_GFX_INDEX_SR_DATA',
'regGRBM_GFX_INDEX_SR_DATA_BASE_IDX',
'regGRBM_GFX_INDEX_SR_SELECT',
'regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX', 'regGRBM_HYP_CAM_DATA',
'regGRBM_HYP_CAM_DATA_BASE_IDX', 'regGRBM_HYP_CAM_DATA_UPPER',
'regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX', 'regGRBM_HYP_CAM_INDEX',
'regGRBM_HYP_CAM_INDEX_BASE_IDX', 'regGRBM_IH_CREDIT',
'regGRBM_IH_CREDIT_BASE_IDX', 'regGRBM_INT_CNTL',
'regGRBM_INT_CNTL_BASE_IDX', 'regGRBM_INVALID_PIPE',
'regGRBM_INVALID_PIPE_BASE_IDX', 'regGRBM_NOWHERE',
'regGRBM_NOWHERE_BASE_IDX', 'regGRBM_PERFCOUNTER0_HI',
'regGRBM_PERFCOUNTER0_HI_BASE_IDX', 'regGRBM_PERFCOUNTER0_LO',
'regGRBM_PERFCOUNTER0_LO_BASE_IDX', 'regGRBM_PERFCOUNTER0_SELECT',
'regGRBM_PERFCOUNTER0_SELECT_BASE_IDX',
'regGRBM_PERFCOUNTER0_SELECT_HI',
'regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX',
'regGRBM_PERFCOUNTER1_HI', 'regGRBM_PERFCOUNTER1_HI_BASE_IDX',
'regGRBM_PERFCOUNTER1_LO', 'regGRBM_PERFCOUNTER1_LO_BASE_IDX',
'regGRBM_PERFCOUNTER1_SELECT',
'regGRBM_PERFCOUNTER1_SELECT_BASE_IDX',
'regGRBM_PERFCOUNTER1_SELECT_HI',
'regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX', 'regGRBM_PWR_CNTL',
'regGRBM_PWR_CNTL2', 'regGRBM_PWR_CNTL2_BASE_IDX',
'regGRBM_PWR_CNTL_BASE_IDX', 'regGRBM_READ_ERROR',
'regGRBM_READ_ERROR2', 'regGRBM_READ_ERROR2_BASE_IDX',
'regGRBM_READ_ERROR_BASE_IDX', 'regGRBM_SCRATCH_REG0',
'regGRBM_SCRATCH_REG0_BASE_IDX', 'regGRBM_SCRATCH_REG1',
'regGRBM_SCRATCH_REG1_BASE_IDX', 'regGRBM_SCRATCH_REG2',
'regGRBM_SCRATCH_REG2_BASE_IDX', 'regGRBM_SCRATCH_REG3',
'regGRBM_SCRATCH_REG3_BASE_IDX', 'regGRBM_SCRATCH_REG4',
'regGRBM_SCRATCH_REG4_BASE_IDX', 'regGRBM_SCRATCH_REG5',
'regGRBM_SCRATCH_REG5_BASE_IDX', 'regGRBM_SCRATCH_REG6',
'regGRBM_SCRATCH_REG6_BASE_IDX', 'regGRBM_SCRATCH_REG7',
'regGRBM_SCRATCH_REG7_BASE_IDX', 'regGRBM_SE0_PERFCOUNTER_HI',
'regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX',
'regGRBM_SE0_PERFCOUNTER_LO',
'regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX',
'regGRBM_SE0_PERFCOUNTER_SELECT',
'regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX',
'regGRBM_SE1_PERFCOUNTER_HI',
'regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX',
'regGRBM_SE1_PERFCOUNTER_LO',
'regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX',
'regGRBM_SE1_PERFCOUNTER_SELECT',
'regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX',
'regGRBM_SE2_PERFCOUNTER_HI',
'regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX',
'regGRBM_SE2_PERFCOUNTER_LO',
'regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX',
'regGRBM_SE2_PERFCOUNTER_SELECT',
'regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX',
'regGRBM_SE3_PERFCOUNTER_HI',
'regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX',
'regGRBM_SE3_PERFCOUNTER_LO',
'regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX',
'regGRBM_SE3_PERFCOUNTER_SELECT',
'regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX',
'regGRBM_SE4_PERFCOUNTER_HI',
'regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX',
'regGRBM_SE4_PERFCOUNTER_LO',
'regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX',
'regGRBM_SE4_PERFCOUNTER_SELECT',
'regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX',
'regGRBM_SE5_PERFCOUNTER_HI',
'regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX',
'regGRBM_SE5_PERFCOUNTER_LO',
'regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX',
'regGRBM_SE5_PERFCOUNTER_SELECT',
'regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX',
'regGRBM_SE6_PERFCOUNTER_HI',
'regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX',
'regGRBM_SE6_PERFCOUNTER_LO',
'regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX',
'regGRBM_SE6_PERFCOUNTER_SELECT',
'regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX', 'regGRBM_SEC_CNTL',
'regGRBM_SEC_CNTL_BASE_IDX', 'regGRBM_SE_REMAP_CNTL',
'regGRBM_SE_REMAP_CNTL_BASE_IDX', 'regGRBM_SKEW_CNTL',
'regGRBM_SKEW_CNTL_BASE_IDX', 'regGRBM_SOFT_RESET',
'regGRBM_SOFT_RESET_BASE_IDX', 'regGRBM_STATUS',
'regGRBM_STATUS2', 'regGRBM_STATUS2_BASE_IDX', 'regGRBM_STATUS3',
'regGRBM_STATUS3_BASE_IDX', 'regGRBM_STATUS_BASE_IDX',
'regGRBM_STATUS_SE0', 'regGRBM_STATUS_SE0_BASE_IDX',
'regGRBM_STATUS_SE1', 'regGRBM_STATUS_SE1_BASE_IDX',
'regGRBM_STATUS_SE2', 'regGRBM_STATUS_SE2_BASE_IDX',
'regGRBM_STATUS_SE3', 'regGRBM_STATUS_SE3_BASE_IDX',
'regGRBM_STATUS_SE4', 'regGRBM_STATUS_SE4_BASE_IDX',
'regGRBM_STATUS_SE5', 'regGRBM_STATUS_SE5_BASE_IDX',
'regGRBM_TRAP_ADDR', 'regGRBM_TRAP_ADDR_BASE_IDX',
'regGRBM_TRAP_ADDR_MSK', 'regGRBM_TRAP_ADDR_MSK_BASE_IDX',
'regGRBM_TRAP_OP', 'regGRBM_TRAP_OP_BASE_IDX', 'regGRBM_TRAP_WD',
'regGRBM_TRAP_WD_BASE_IDX', 'regGRBM_TRAP_WD_MSK',
'regGRBM_TRAP_WD_MSK_BASE_IDX', 'regGRBM_UTCL2_INVAL_RANGE_END',
'regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX',
'regGRBM_UTCL2_INVAL_RANGE_START',
'regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX',
'regGRBM_WAIT_IDLE_CLOCKS', 'regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX',
'regGRBM_WRITE_ERROR', 'regGRBM_WRITE_ERROR_BASE_IDX',
'regGRTAVFS_CLK_CNTL', 'regGRTAVFS_CLK_CNTL_BASE_IDX',
'regGRTAVFS_GENERAL_0', 'regGRTAVFS_GENERAL_0_BASE_IDX',
'regGRTAVFS_PSM_CNTL', 'regGRTAVFS_PSM_CNTL_BASE_IDX',
'regGRTAVFS_RTAVFS_RD_DATA', 'regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX',
'regGRTAVFS_RTAVFS_REG_ADDR',
'regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX',
'regGRTAVFS_RTAVFS_REG_CTRL',
'regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX',
'regGRTAVFS_RTAVFS_REG_STATUS',
'regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX',
'regGRTAVFS_RTAVFS_WR_DATA', 'regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX',
'regGRTAVFS_SE_CLK_CNTL', 'regGRTAVFS_SE_CLK_CNTL_BASE_IDX',
'regGRTAVFS_SE_GENERAL_0', 'regGRTAVFS_SE_GENERAL_0_BASE_IDX',
'regGRTAVFS_SE_PSM_CNTL', 'regGRTAVFS_SE_PSM_CNTL_BASE_IDX',
'regGRTAVFS_SE_RTAVFS_RD_DATA',
'regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX',
'regGRTAVFS_SE_RTAVFS_REG_ADDR',
'regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX',
'regGRTAVFS_SE_RTAVFS_REG_CTRL',
'regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX',
'regGRTAVFS_SE_RTAVFS_REG_STATUS',
'regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX',
'regGRTAVFS_SE_RTAVFS_WR_DATA',
'regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX',
'regGRTAVFS_SE_SOFT_RESET', 'regGRTAVFS_SE_SOFT_RESET_BASE_IDX',
'regGRTAVFS_SE_TARG_FREQ', 'regGRTAVFS_SE_TARG_FREQ_BASE_IDX',
'regGRTAVFS_SE_TARG_VOLT', 'regGRTAVFS_SE_TARG_VOLT_BASE_IDX',
'regGRTAVFS_SOFT_RESET', 'regGRTAVFS_SOFT_RESET_BASE_IDX',
'regGRTAVFS_TARG_FREQ', 'regGRTAVFS_TARG_FREQ_BASE_IDX',
'regGRTAVFS_TARG_VOLT', 'regGRTAVFS_TARG_VOLT_BASE_IDX',
'regGUS_DRAM_COMBINE_FLUSH', 'regGUS_DRAM_COMBINE_FLUSH_BASE_IDX',
'regGUS_DRAM_COMBINE_RD_WR_EN',
'regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX',
'regGUS_DRAM_GROUP_BURST', 'regGUS_DRAM_GROUP_BURST_BASE_IDX',
'regGUS_DRAM_PRI_AGE_COEFF', 'regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX',
'regGUS_DRAM_PRI_AGE_RATE', 'regGUS_DRAM_PRI_AGE_RATE_BASE_IDX',
'regGUS_DRAM_PRI_FIXED', 'regGUS_DRAM_PRI_FIXED_BASE_IDX',
'regGUS_DRAM_PRI_QUANT1_PRI1',
'regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX',
'regGUS_DRAM_PRI_QUANT1_PRI2',
'regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX',
'regGUS_DRAM_PRI_QUANT1_PRI3',
'regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX',
'regGUS_DRAM_PRI_QUANT1_PRI4',
'regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX',
'regGUS_DRAM_PRI_QUANT1_PRI5',
'regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX',
'regGUS_DRAM_PRI_QUANT_PRI1',
'regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX',
'regGUS_DRAM_PRI_QUANT_PRI2',
'regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX',
'regGUS_DRAM_PRI_QUANT_PRI3',
'regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX',
'regGUS_DRAM_PRI_QUANT_PRI4',
'regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX',
'regGUS_DRAM_PRI_QUANT_PRI5',
'regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX', 'regGUS_DRAM_PRI_QUEUING',
'regGUS_DRAM_PRI_QUEUING_BASE_IDX',
'regGUS_DRAM_PRI_URGENCY_COEFF',
'regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX',
'regGUS_DRAM_PRI_URGENCY_MODE',
'regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX', 'regGUS_ERR_STATUS',
'regGUS_ERR_STATUS_BASE_IDX', 'regGUS_ICG_CTRL',
'regGUS_ICG_CTRL_BASE_IDX', 'regGUS_IO_GROUP_BURST',
'regGUS_IO_GROUP_BURST_BASE_IDX', 'regGUS_IO_RD_COMBINE_FLUSH',
'regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX',
'regGUS_IO_RD_PRI_AGE_COEFF',
'regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX',
'regGUS_IO_RD_PRI_AGE_RATE', 'regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX',
'regGUS_IO_RD_PRI_FIXED', 'regGUS_IO_RD_PRI_FIXED_BASE_IDX',
'regGUS_IO_RD_PRI_QUANT1_PRI1',
'regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX',
'regGUS_IO_RD_PRI_QUANT1_PRI2',
'regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX',
'regGUS_IO_RD_PRI_QUANT1_PRI3',
'regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX',
'regGUS_IO_RD_PRI_QUANT1_PRI4',
'regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX',
'regGUS_IO_RD_PRI_QUANT_PRI1',
'regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX',
'regGUS_IO_RD_PRI_QUANT_PRI2',
'regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX',
'regGUS_IO_RD_PRI_QUANT_PRI3',
'regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX',
'regGUS_IO_RD_PRI_QUANT_PRI4',
'regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX',
'regGUS_IO_RD_PRI_QUEUING', 'regGUS_IO_RD_PRI_QUEUING_BASE_IDX',
'regGUS_IO_RD_PRI_URGENCY_COEFF',
'regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX',
'regGUS_IO_RD_PRI_URGENCY_MODE',
'regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX',
'regGUS_IO_WR_COMBINE_FLUSH',
'regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX',
'regGUS_IO_WR_PRI_AGE_COEFF',
'regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX',
'regGUS_IO_WR_PRI_AGE_RATE', 'regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX',
'regGUS_IO_WR_PRI_FIXED', 'regGUS_IO_WR_PRI_FIXED_BASE_IDX',
'regGUS_IO_WR_PRI_QUANT1_PRI1',
'regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX',
'regGUS_IO_WR_PRI_QUANT1_PRI2',
'regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX',
'regGUS_IO_WR_PRI_QUANT1_PRI3',
'regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX',
'regGUS_IO_WR_PRI_QUANT1_PRI4',
'regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX',
'regGUS_IO_WR_PRI_QUANT_PRI1',
'regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX',
'regGUS_IO_WR_PRI_QUANT_PRI2',
'regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX',
'regGUS_IO_WR_PRI_QUANT_PRI3',
'regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX',
'regGUS_IO_WR_PRI_QUANT_PRI4',
'regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX',
'regGUS_IO_WR_PRI_QUEUING', 'regGUS_IO_WR_PRI_QUEUING_BASE_IDX',
'regGUS_IO_WR_PRI_URGENCY_COEFF',
'regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX',
'regGUS_IO_WR_PRI_URGENCY_MODE',
'regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX', 'regGUS_L1_CH0_CMD_IN',
'regGUS_L1_CH0_CMD_IN_BASE_IDX', 'regGUS_L1_CH0_CMD_OUT',
'regGUS_L1_CH0_CMD_OUT_BASE_IDX', 'regGUS_L1_CH0_DATA_IN',
'regGUS_L1_CH0_DATA_IN_BASE_IDX', 'regGUS_L1_CH0_DATA_OUT',
'regGUS_L1_CH0_DATA_OUT_BASE_IDX', 'regGUS_L1_CH0_DATA_U_IN',
'regGUS_L1_CH0_DATA_U_IN_BASE_IDX', 'regGUS_L1_CH0_DATA_U_OUT',
'regGUS_L1_CH0_DATA_U_OUT_BASE_IDX', 'regGUS_L1_CH1_CMD_IN',
'regGUS_L1_CH1_CMD_IN_BASE_IDX', 'regGUS_L1_CH1_CMD_OUT',
'regGUS_L1_CH1_CMD_OUT_BASE_IDX', 'regGUS_L1_CH1_DATA_IN',
'regGUS_L1_CH1_DATA_IN_BASE_IDX', 'regGUS_L1_CH1_DATA_OUT',
'regGUS_L1_CH1_DATA_OUT_BASE_IDX', 'regGUS_L1_CH1_DATA_U_IN',
'regGUS_L1_CH1_DATA_U_IN_BASE_IDX', 'regGUS_L1_CH1_DATA_U_OUT',
'regGUS_L1_CH1_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA0_CMD_IN',
'regGUS_L1_SA0_CMD_IN_BASE_IDX', 'regGUS_L1_SA0_CMD_OUT',
'regGUS_L1_SA0_CMD_OUT_BASE_IDX', 'regGUS_L1_SA0_DATA_IN',
'regGUS_L1_SA0_DATA_IN_BASE_IDX', 'regGUS_L1_SA0_DATA_OUT',
'regGUS_L1_SA0_DATA_OUT_BASE_IDX', 'regGUS_L1_SA0_DATA_U_IN',
'regGUS_L1_SA0_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA0_DATA_U_OUT',
'regGUS_L1_SA0_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA1_CMD_IN',
'regGUS_L1_SA1_CMD_IN_BASE_IDX', 'regGUS_L1_SA1_CMD_OUT',
'regGUS_L1_SA1_CMD_OUT_BASE_IDX', 'regGUS_L1_SA1_DATA_IN',
'regGUS_L1_SA1_DATA_IN_BASE_IDX', 'regGUS_L1_SA1_DATA_OUT',
'regGUS_L1_SA1_DATA_OUT_BASE_IDX', 'regGUS_L1_SA1_DATA_U_IN',
'regGUS_L1_SA1_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA1_DATA_U_OUT',
'regGUS_L1_SA1_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA2_CMD_IN',
'regGUS_L1_SA2_CMD_IN_BASE_IDX', 'regGUS_L1_SA2_CMD_OUT',
'regGUS_L1_SA2_CMD_OUT_BASE_IDX', 'regGUS_L1_SA2_DATA_IN',
'regGUS_L1_SA2_DATA_IN_BASE_IDX', 'regGUS_L1_SA2_DATA_OUT',
'regGUS_L1_SA2_DATA_OUT_BASE_IDX', 'regGUS_L1_SA2_DATA_U_IN',
'regGUS_L1_SA2_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA2_DATA_U_OUT',
'regGUS_L1_SA2_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA3_CMD_IN',
'regGUS_L1_SA3_CMD_IN_BASE_IDX', 'regGUS_L1_SA3_CMD_OUT',
'regGUS_L1_SA3_CMD_OUT_BASE_IDX', 'regGUS_L1_SA3_DATA_IN',
'regGUS_L1_SA3_DATA_IN_BASE_IDX', 'regGUS_L1_SA3_DATA_OUT',
'regGUS_L1_SA3_DATA_OUT_BASE_IDX', 'regGUS_L1_SA3_DATA_U_IN',
'regGUS_L1_SA3_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA3_DATA_U_OUT',
'regGUS_L1_SA3_DATA_U_OUT_BASE_IDX', 'regGUS_LATENCY_SAMPLING',
'regGUS_LATENCY_SAMPLING_BASE_IDX', 'regGUS_MISC', 'regGUS_MISC2',
'regGUS_MISC2_BASE_IDX', 'regGUS_MISC3', 'regGUS_MISC3_BASE_IDX',
'regGUS_MISC_BASE_IDX', 'regGUS_PERFCOUNTER0_CFG',
'regGUS_PERFCOUNTER0_CFG_BASE_IDX', 'regGUS_PERFCOUNTER1_CFG',
'regGUS_PERFCOUNTER1_CFG_BASE_IDX', 'regGUS_PERFCOUNTER2_HI',
'regGUS_PERFCOUNTER2_HI_BASE_IDX', 'regGUS_PERFCOUNTER2_LO',
'regGUS_PERFCOUNTER2_LO_BASE_IDX', 'regGUS_PERFCOUNTER2_MODE',
'regGUS_PERFCOUNTER2_MODE_BASE_IDX', 'regGUS_PERFCOUNTER2_SELECT',
'regGUS_PERFCOUNTER2_SELECT1',
'regGUS_PERFCOUNTER2_SELECT1_BASE_IDX',
'regGUS_PERFCOUNTER2_SELECT_BASE_IDX', 'regGUS_PERFCOUNTER_HI',
'regGUS_PERFCOUNTER_HI_BASE_IDX', 'regGUS_PERFCOUNTER_LO',
'regGUS_PERFCOUNTER_LO_BASE_IDX', 'regGUS_PERFCOUNTER_RSLT_CNTL',
'regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regGUS_SDP_ARB_FINAL',
'regGUS_SDP_ARB_FINAL_BASE_IDX', 'regGUS_SDP_CREDITS',
'regGUS_SDP_CREDITS_BASE_IDX', 'regGUS_SDP_ENABLE',
'regGUS_SDP_ENABLE_BASE_IDX', 'regGUS_SDP_QOS_VC_PRIORITY',
'regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX', 'regGUS_SDP_REQ_CNTL',
'regGUS_SDP_REQ_CNTL_BASE_IDX', 'regGUS_SDP_TAG_RESERVE0',
'regGUS_SDP_TAG_RESERVE0_BASE_IDX', 'regGUS_SDP_TAG_RESERVE1',
'regGUS_SDP_TAG_RESERVE1_BASE_IDX', 'regGUS_SDP_VCC_RESERVE0',
'regGUS_SDP_VCC_RESERVE0_BASE_IDX', 'regGUS_SDP_VCC_RESERVE1',
'regGUS_SDP_VCC_RESERVE1_BASE_IDX', 'regGUS_SDP_VCD_RESERVE0',
'regGUS_SDP_VCD_RESERVE0_BASE_IDX', 'regGUS_SDP_VCD_RESERVE1',
'regGUS_SDP_VCD_RESERVE1_BASE_IDX', 'regGUS_WRRSP_FIFO_CNTL',
'regGUS_WRRSP_FIFO_CNTL_BASE_IDX', 'regIA_ENHANCE',
'regIA_ENHANCE_BASE_IDX', 'regIA_UTCL1_CNTL',
'regIA_UTCL1_CNTL_BASE_IDX', 'regIA_UTCL1_STATUS',
'regIA_UTCL1_STATUS_2', 'regIA_UTCL1_STATUS_2_BASE_IDX',
'regIA_UTCL1_STATUS_BASE_IDX', 'regICG_CHA_CTRL',
'regICG_CHA_CTRL_BASE_IDX', 'regICG_CHCG_CLK_CTRL',
'regICG_CHCG_CLK_CTRL_BASE_IDX', 'regICG_CHC_CLK_CTRL',
'regICG_CHC_CLK_CTRL_BASE_IDX', 'regICG_GL1A_CTRL',
'regICG_GL1A_CTRL_BASE_IDX', 'regICG_GL1C_CLK_CTRL',
'regICG_GL1C_CLK_CTRL_BASE_IDX', 'regICG_LDS_CLK_CTRL',
'regICG_LDS_CLK_CTRL_BASE_IDX', 'regICG_SP_CLK_CTRL',
'regICG_SP_CLK_CTRL_BASE_IDX', 'regLDS_CONFIG',
'regLDS_CONFIG_BASE_IDX', 'regPA_CL_CLIP_CNTL',
'regPA_CL_CLIP_CNTL_BASE_IDX', 'regPA_CL_CNTL_STATUS',
'regPA_CL_CNTL_STATUS_BASE_IDX', 'regPA_CL_ENHANCE',
'regPA_CL_ENHANCE_BASE_IDX', 'regPA_CL_GB_HORZ_CLIP_ADJ',
'regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX', 'regPA_CL_GB_HORZ_DISC_ADJ',
'regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX', 'regPA_CL_GB_VERT_CLIP_ADJ',
'regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX', 'regPA_CL_GB_VERT_DISC_ADJ',
'regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX', 'regPA_CL_NANINF_CNTL',
'regPA_CL_NANINF_CNTL_BASE_IDX', 'regPA_CL_NGG_CNTL',
'regPA_CL_NGG_CNTL_BASE_IDX', 'regPA_CL_POINT_CULL_RAD',
'regPA_CL_POINT_CULL_RAD_BASE_IDX', 'regPA_CL_POINT_SIZE',
'regPA_CL_POINT_SIZE_BASE_IDX', 'regPA_CL_POINT_X_RAD',
'regPA_CL_POINT_X_RAD_BASE_IDX', 'regPA_CL_POINT_Y_RAD',
'regPA_CL_POINT_Y_RAD_BASE_IDX', 'regPA_CL_PROG_NEAR_CLIP_Z',
'regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX', 'regPA_CL_UCP_0_W',
'regPA_CL_UCP_0_W_BASE_IDX', 'regPA_CL_UCP_0_X',
'regPA_CL_UCP_0_X_BASE_IDX', 'regPA_CL_UCP_0_Y',
'regPA_CL_UCP_0_Y_BASE_IDX', 'regPA_CL_UCP_0_Z',
'regPA_CL_UCP_0_Z_BASE_IDX', 'regPA_CL_UCP_1_W',
'regPA_CL_UCP_1_W_BASE_IDX', 'regPA_CL_UCP_1_X',
'regPA_CL_UCP_1_X_BASE_IDX', 'regPA_CL_UCP_1_Y',
'regPA_CL_UCP_1_Y_BASE_IDX', 'regPA_CL_UCP_1_Z',
'regPA_CL_UCP_1_Z_BASE_IDX', 'regPA_CL_UCP_2_W',
'regPA_CL_UCP_2_W_BASE_IDX', 'regPA_CL_UCP_2_X',
'regPA_CL_UCP_2_X_BASE_IDX', 'regPA_CL_UCP_2_Y',
'regPA_CL_UCP_2_Y_BASE_IDX', 'regPA_CL_UCP_2_Z',
'regPA_CL_UCP_2_Z_BASE_IDX', 'regPA_CL_UCP_3_W',
'regPA_CL_UCP_3_W_BASE_IDX', 'regPA_CL_UCP_3_X',
'regPA_CL_UCP_3_X_BASE_IDX', 'regPA_CL_UCP_3_Y',
'regPA_CL_UCP_3_Y_BASE_IDX', 'regPA_CL_UCP_3_Z',
'regPA_CL_UCP_3_Z_BASE_IDX', 'regPA_CL_UCP_4_W',
'regPA_CL_UCP_4_W_BASE_IDX', 'regPA_CL_UCP_4_X',
'regPA_CL_UCP_4_X_BASE_IDX', 'regPA_CL_UCP_4_Y',
'regPA_CL_UCP_4_Y_BASE_IDX', 'regPA_CL_UCP_4_Z',
'regPA_CL_UCP_4_Z_BASE_IDX', 'regPA_CL_UCP_5_W',
'regPA_CL_UCP_5_W_BASE_IDX', 'regPA_CL_UCP_5_X',
'regPA_CL_UCP_5_X_BASE_IDX', 'regPA_CL_UCP_5_Y',
'regPA_CL_UCP_5_Y_BASE_IDX', 'regPA_CL_UCP_5_Z',
'regPA_CL_UCP_5_Z_BASE_IDX', 'regPA_CL_VPORT_XOFFSET',
'regPA_CL_VPORT_XOFFSET_1', 'regPA_CL_VPORT_XOFFSET_10',
'regPA_CL_VPORT_XOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_11',
'regPA_CL_VPORT_XOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_12',
'regPA_CL_VPORT_XOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_13',
'regPA_CL_VPORT_XOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_14',
'regPA_CL_VPORT_XOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_15',
'regPA_CL_VPORT_XOFFSET_15_BASE_IDX',
'regPA_CL_VPORT_XOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_2',
'regPA_CL_VPORT_XOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_3',
'regPA_CL_VPORT_XOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_4',
'regPA_CL_VPORT_XOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_5',
'regPA_CL_VPORT_XOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_6',
'regPA_CL_VPORT_XOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_7',
'regPA_CL_VPORT_XOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_8',
'regPA_CL_VPORT_XOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_9',
'regPA_CL_VPORT_XOFFSET_9_BASE_IDX',
'regPA_CL_VPORT_XOFFSET_BASE_IDX', 'regPA_CL_VPORT_XSCALE',
'regPA_CL_VPORT_XSCALE_1', 'regPA_CL_VPORT_XSCALE_10',
'regPA_CL_VPORT_XSCALE_10_BASE_IDX', 'regPA_CL_VPORT_XSCALE_11',
'regPA_CL_VPORT_XSCALE_11_BASE_IDX', 'regPA_CL_VPORT_XSCALE_12',
'regPA_CL_VPORT_XSCALE_12_BASE_IDX', 'regPA_CL_VPORT_XSCALE_13',
'regPA_CL_VPORT_XSCALE_13_BASE_IDX', 'regPA_CL_VPORT_XSCALE_14',
'regPA_CL_VPORT_XSCALE_14_BASE_IDX', 'regPA_CL_VPORT_XSCALE_15',
'regPA_CL_VPORT_XSCALE_15_BASE_IDX',
'regPA_CL_VPORT_XSCALE_1_BASE_IDX', 'regPA_CL_VPORT_XSCALE_2',
'regPA_CL_VPORT_XSCALE_2_BASE_IDX', 'regPA_CL_VPORT_XSCALE_3',
'regPA_CL_VPORT_XSCALE_3_BASE_IDX', 'regPA_CL_VPORT_XSCALE_4',
'regPA_CL_VPORT_XSCALE_4_BASE_IDX', 'regPA_CL_VPORT_XSCALE_5',
'regPA_CL_VPORT_XSCALE_5_BASE_IDX', 'regPA_CL_VPORT_XSCALE_6',
'regPA_CL_VPORT_XSCALE_6_BASE_IDX', 'regPA_CL_VPORT_XSCALE_7',
'regPA_CL_VPORT_XSCALE_7_BASE_IDX', 'regPA_CL_VPORT_XSCALE_8',
'regPA_CL_VPORT_XSCALE_8_BASE_IDX', 'regPA_CL_VPORT_XSCALE_9',
'regPA_CL_VPORT_XSCALE_9_BASE_IDX',
'regPA_CL_VPORT_XSCALE_BASE_IDX', 'regPA_CL_VPORT_YOFFSET',
'regPA_CL_VPORT_YOFFSET_1', 'regPA_CL_VPORT_YOFFSET_10',
'regPA_CL_VPORT_YOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_11',
'regPA_CL_VPORT_YOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_12',
'regPA_CL_VPORT_YOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_13',
'regPA_CL_VPORT_YOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_14',
'regPA_CL_VPORT_YOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_15',
'regPA_CL_VPORT_YOFFSET_15_BASE_IDX',
'regPA_CL_VPORT_YOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_2',
'regPA_CL_VPORT_YOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_3',
'regPA_CL_VPORT_YOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_4',
'regPA_CL_VPORT_YOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_5',
'regPA_CL_VPORT_YOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_6',
'regPA_CL_VPORT_YOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_7',
'regPA_CL_VPORT_YOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_8',
'regPA_CL_VPORT_YOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_9',
'regPA_CL_VPORT_YOFFSET_9_BASE_IDX',
'regPA_CL_VPORT_YOFFSET_BASE_IDX', 'regPA_CL_VPORT_YSCALE',
'regPA_CL_VPORT_YSCALE_1', 'regPA_CL_VPORT_YSCALE_10',
'regPA_CL_VPORT_YSCALE_10_BASE_IDX', 'regPA_CL_VPORT_YSCALE_11',
'regPA_CL_VPORT_YSCALE_11_BASE_IDX', 'regPA_CL_VPORT_YSCALE_12',
'regPA_CL_VPORT_YSCALE_12_BASE_IDX', 'regPA_CL_VPORT_YSCALE_13',
'regPA_CL_VPORT_YSCALE_13_BASE_IDX', 'regPA_CL_VPORT_YSCALE_14',
'regPA_CL_VPORT_YSCALE_14_BASE_IDX', 'regPA_CL_VPORT_YSCALE_15',
'regPA_CL_VPORT_YSCALE_15_BASE_IDX',
'regPA_CL_VPORT_YSCALE_1_BASE_IDX', 'regPA_CL_VPORT_YSCALE_2',
'regPA_CL_VPORT_YSCALE_2_BASE_IDX', 'regPA_CL_VPORT_YSCALE_3',
'regPA_CL_VPORT_YSCALE_3_BASE_IDX', 'regPA_CL_VPORT_YSCALE_4',
'regPA_CL_VPORT_YSCALE_4_BASE_IDX', 'regPA_CL_VPORT_YSCALE_5',
'regPA_CL_VPORT_YSCALE_5_BASE_IDX', 'regPA_CL_VPORT_YSCALE_6',
'regPA_CL_VPORT_YSCALE_6_BASE_IDX', 'regPA_CL_VPORT_YSCALE_7',
'regPA_CL_VPORT_YSCALE_7_BASE_IDX', 'regPA_CL_VPORT_YSCALE_8',
'regPA_CL_VPORT_YSCALE_8_BASE_IDX', 'regPA_CL_VPORT_YSCALE_9',
'regPA_CL_VPORT_YSCALE_9_BASE_IDX',
'regPA_CL_VPORT_YSCALE_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET',
'regPA_CL_VPORT_ZOFFSET_1', 'regPA_CL_VPORT_ZOFFSET_10',
'regPA_CL_VPORT_ZOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_11',
'regPA_CL_VPORT_ZOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_12',
'regPA_CL_VPORT_ZOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_13',
'regPA_CL_VPORT_ZOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_14',
'regPA_CL_VPORT_ZOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_15',
'regPA_CL_VPORT_ZOFFSET_15_BASE_IDX',
'regPA_CL_VPORT_ZOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_2',
'regPA_CL_VPORT_ZOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_3',
'regPA_CL_VPORT_ZOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_4',
'regPA_CL_VPORT_ZOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_5',
'regPA_CL_VPORT_ZOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_6',
'regPA_CL_VPORT_ZOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_7',
'regPA_CL_VPORT_ZOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_8',
'regPA_CL_VPORT_ZOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_9',
'regPA_CL_VPORT_ZOFFSET_9_BASE_IDX',
'regPA_CL_VPORT_ZOFFSET_BASE_IDX', 'regPA_CL_VPORT_ZSCALE',
'regPA_CL_VPORT_ZSCALE_1', 'regPA_CL_VPORT_ZSCALE_10',
'regPA_CL_VPORT_ZSCALE_10_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_11',
'regPA_CL_VPORT_ZSCALE_11_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_12',
'regPA_CL_VPORT_ZSCALE_12_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_13',
'regPA_CL_VPORT_ZSCALE_13_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_14',
'regPA_CL_VPORT_ZSCALE_14_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_15',
'regPA_CL_VPORT_ZSCALE_15_BASE_IDX',
'regPA_CL_VPORT_ZSCALE_1_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_2',
'regPA_CL_VPORT_ZSCALE_2_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_3',
'regPA_CL_VPORT_ZSCALE_3_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_4',
'regPA_CL_VPORT_ZSCALE_4_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_5',
'regPA_CL_VPORT_ZSCALE_5_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_6',
'regPA_CL_VPORT_ZSCALE_6_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_7',
'regPA_CL_VPORT_ZSCALE_7_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_8',
'regPA_CL_VPORT_ZSCALE_8_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_9',
'regPA_CL_VPORT_ZSCALE_9_BASE_IDX',
'regPA_CL_VPORT_ZSCALE_BASE_IDX', 'regPA_CL_VRS_CNTL',
'regPA_CL_VRS_CNTL_BASE_IDX', 'regPA_CL_VS_OUT_CNTL',
'regPA_CL_VS_OUT_CNTL_BASE_IDX', 'regPA_CL_VTE_CNTL',
'regPA_CL_VTE_CNTL_BASE_IDX', 'regPA_PH_ENHANCE',
'regPA_PH_ENHANCE_BASE_IDX', 'regPA_PH_INTERFACE_FIFO_SIZE',
'regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX',
'regPA_PH_PERFCOUNTER0_HI', 'regPA_PH_PERFCOUNTER0_HI_BASE_IDX',
'regPA_PH_PERFCOUNTER0_LO', 'regPA_PH_PERFCOUNTER0_LO_BASE_IDX',
'regPA_PH_PERFCOUNTER0_SELECT', 'regPA_PH_PERFCOUNTER0_SELECT1',
'regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX',
'regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX',
'regPA_PH_PERFCOUNTER1_HI', 'regPA_PH_PERFCOUNTER1_HI_BASE_IDX',
'regPA_PH_PERFCOUNTER1_LO', 'regPA_PH_PERFCOUNTER1_LO_BASE_IDX',
'regPA_PH_PERFCOUNTER1_SELECT', 'regPA_PH_PERFCOUNTER1_SELECT1',
'regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX',
'regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX',
'regPA_PH_PERFCOUNTER2_HI', 'regPA_PH_PERFCOUNTER2_HI_BASE_IDX',
'regPA_PH_PERFCOUNTER2_LO', 'regPA_PH_PERFCOUNTER2_LO_BASE_IDX',
'regPA_PH_PERFCOUNTER2_SELECT', 'regPA_PH_PERFCOUNTER2_SELECT1',
'regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX',
'regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX',
'regPA_PH_PERFCOUNTER3_HI', 'regPA_PH_PERFCOUNTER3_HI_BASE_IDX',
'regPA_PH_PERFCOUNTER3_LO', 'regPA_PH_PERFCOUNTER3_LO_BASE_IDX',
'regPA_PH_PERFCOUNTER3_SELECT', 'regPA_PH_PERFCOUNTER3_SELECT1',
'regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX',
'regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX',
'regPA_PH_PERFCOUNTER4_HI', 'regPA_PH_PERFCOUNTER4_HI_BASE_IDX',
'regPA_PH_PERFCOUNTER4_LO', 'regPA_PH_PERFCOUNTER4_LO_BASE_IDX',
'regPA_PH_PERFCOUNTER4_SELECT',
'regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX',
'regPA_PH_PERFCOUNTER5_HI', 'regPA_PH_PERFCOUNTER5_HI_BASE_IDX',
'regPA_PH_PERFCOUNTER5_LO', 'regPA_PH_PERFCOUNTER5_LO_BASE_IDX',
'regPA_PH_PERFCOUNTER5_SELECT',
'regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX',
'regPA_PH_PERFCOUNTER6_HI', 'regPA_PH_PERFCOUNTER6_HI_BASE_IDX',
'regPA_PH_PERFCOUNTER6_LO', 'regPA_PH_PERFCOUNTER6_LO_BASE_IDX',
'regPA_PH_PERFCOUNTER6_SELECT',
'regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX',
'regPA_PH_PERFCOUNTER7_HI', 'regPA_PH_PERFCOUNTER7_HI_BASE_IDX',
'regPA_PH_PERFCOUNTER7_LO', 'regPA_PH_PERFCOUNTER7_LO_BASE_IDX',
'regPA_PH_PERFCOUNTER7_SELECT',
'regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX', 'regPA_RATE_CNTL',
'regPA_RATE_CNTL_BASE_IDX', 'regPA_SC_AA_CONFIG',
'regPA_SC_AA_CONFIG_BASE_IDX', 'regPA_SC_AA_MASK_X0Y0_X1Y0',
'regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX',
'regPA_SC_AA_MASK_X0Y1_X1Y1',
'regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3',
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX',
'regPA_SC_ATM_CNTL', 'regPA_SC_ATM_CNTL_BASE_IDX',
'regPA_SC_BINNER_CNTL_0', 'regPA_SC_BINNER_CNTL_0_BASE_IDX',
'regPA_SC_BINNER_CNTL_1', 'regPA_SC_BINNER_CNTL_1_BASE_IDX',
'regPA_SC_BINNER_CNTL_2', 'regPA_SC_BINNER_CNTL_2_BASE_IDX',
'regPA_SC_BINNER_CNTL_OVERRIDE',
'regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX',
'regPA_SC_BINNER_EVENT_CNTL_0',
'regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX',
'regPA_SC_BINNER_EVENT_CNTL_1',
'regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX',
'regPA_SC_BINNER_EVENT_CNTL_2',
'regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX',
'regPA_SC_BINNER_EVENT_CNTL_3',
'regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX',
'regPA_SC_BINNER_PERF_CNTL_0',
'regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX',
'regPA_SC_BINNER_PERF_CNTL_1',
'regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX',
'regPA_SC_BINNER_PERF_CNTL_2',
'regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX',
'regPA_SC_BINNER_PERF_CNTL_3',
'regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX',
'regPA_SC_BINNER_TIMEOUT_COUNTER',
'regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX',
'regPA_SC_CENTROID_PRIORITY_0',
'regPA_SC_CENTROID_PRIORITY_0_BASE_IDX',
'regPA_SC_CENTROID_PRIORITY_1',
'regPA_SC_CENTROID_PRIORITY_1_BASE_IDX', 'regPA_SC_CLIPRECT_0_BR',
'regPA_SC_CLIPRECT_0_BR_BASE_IDX', 'regPA_SC_CLIPRECT_0_TL',
'regPA_SC_CLIPRECT_0_TL_BASE_IDX', 'regPA_SC_CLIPRECT_1_BR',
'regPA_SC_CLIPRECT_1_BR_BASE_IDX', 'regPA_SC_CLIPRECT_1_TL',
'regPA_SC_CLIPRECT_1_TL_BASE_IDX', 'regPA_SC_CLIPRECT_2_BR',
'regPA_SC_CLIPRECT_2_BR_BASE_IDX', 'regPA_SC_CLIPRECT_2_TL',
'regPA_SC_CLIPRECT_2_TL_BASE_IDX', 'regPA_SC_CLIPRECT_3_BR',
'regPA_SC_CLIPRECT_3_BR_BASE_IDX', 'regPA_SC_CLIPRECT_3_TL',
'regPA_SC_CLIPRECT_3_TL_BASE_IDX', 'regPA_SC_CLIPRECT_RULE',
'regPA_SC_CLIPRECT_RULE_BASE_IDX',
'regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL',
'regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX',
'regPA_SC_DSM_CNTL', 'regPA_SC_DSM_CNTL_BASE_IDX',
'regPA_SC_EDGERULE', 'regPA_SC_EDGERULE_BASE_IDX',
'regPA_SC_ENHANCE', 'regPA_SC_ENHANCE_1',
'regPA_SC_ENHANCE_1_BASE_IDX', 'regPA_SC_ENHANCE_2',
'regPA_SC_ENHANCE_2_BASE_IDX', 'regPA_SC_ENHANCE_3',
'regPA_SC_ENHANCE_3_BASE_IDX', 'regPA_SC_ENHANCE_BASE_IDX',
'regPA_SC_FIFO_DEPTH_CNTL', 'regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX',
'regPA_SC_FIFO_SIZE', 'regPA_SC_FIFO_SIZE_BASE_IDX',
'regPA_SC_FORCE_EOV_MAX_CNTS',
'regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX',
'regPA_SC_GENERIC_SCISSOR_BR',
'regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX',
'regPA_SC_GENERIC_SCISSOR_TL',
'regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX',
'regPA_SC_HP3D_TRAP_SCREEN_COUNT',
'regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX',
'regPA_SC_HP3D_TRAP_SCREEN_H', 'regPA_SC_HP3D_TRAP_SCREEN_HV_EN',
'regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX',
'regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK',
'regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX',
'regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX',
'regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE',
'regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX',
'regPA_SC_HP3D_TRAP_SCREEN_V',
'regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX', 'regPA_SC_IF_FIFO_SIZE',
'regPA_SC_IF_FIFO_SIZE_BASE_IDX', 'regPA_SC_LINE_CNTL',
'regPA_SC_LINE_CNTL_BASE_IDX', 'regPA_SC_LINE_STIPPLE',
'regPA_SC_LINE_STIPPLE_BASE_IDX', 'regPA_SC_LINE_STIPPLE_STATE',
'regPA_SC_LINE_STIPPLE_STATE_BASE_IDX', 'regPA_SC_MODE_CNTL_0',
'regPA_SC_MODE_CNTL_0_BASE_IDX', 'regPA_SC_MODE_CNTL_1',
'regPA_SC_MODE_CNTL_1_BASE_IDX', 'regPA_SC_NGG_MODE_CNTL',
'regPA_SC_NGG_MODE_CNTL_BASE_IDX',
'regPA_SC_P3D_TRAP_SCREEN_COUNT',
'regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX',
'regPA_SC_P3D_TRAP_SCREEN_H', 'regPA_SC_P3D_TRAP_SCREEN_HV_EN',
'regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX',
'regPA_SC_P3D_TRAP_SCREEN_HV_LOCK',
'regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX',
'regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX',
'regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE',
'regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX',
'regPA_SC_P3D_TRAP_SCREEN_V',
'regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX',
'regPA_SC_PACKER_WAVE_ID_CNTL',
'regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX',
'regPA_SC_PBB_OVERRIDE_FLAG',
'regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX', 'regPA_SC_PERFCOUNTER0_HI',
'regPA_SC_PERFCOUNTER0_HI_BASE_IDX', 'regPA_SC_PERFCOUNTER0_LO',
'regPA_SC_PERFCOUNTER0_LO_BASE_IDX',
'regPA_SC_PERFCOUNTER0_SELECT', 'regPA_SC_PERFCOUNTER0_SELECT1',
'regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX',
'regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX',
'regPA_SC_PERFCOUNTER1_HI', 'regPA_SC_PERFCOUNTER1_HI_BASE_IDX',
'regPA_SC_PERFCOUNTER1_LO', 'regPA_SC_PERFCOUNTER1_LO_BASE_IDX',
'regPA_SC_PERFCOUNTER1_SELECT',
'regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX',
'regPA_SC_PERFCOUNTER2_HI', 'regPA_SC_PERFCOUNTER2_HI_BASE_IDX',
'regPA_SC_PERFCOUNTER2_LO', 'regPA_SC_PERFCOUNTER2_LO_BASE_IDX',
'regPA_SC_PERFCOUNTER2_SELECT',
'regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX',
'regPA_SC_PERFCOUNTER3_HI', 'regPA_SC_PERFCOUNTER3_HI_BASE_IDX',
'regPA_SC_PERFCOUNTER3_LO', 'regPA_SC_PERFCOUNTER3_LO_BASE_IDX',
'regPA_SC_PERFCOUNTER3_SELECT',
'regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX',
'regPA_SC_PERFCOUNTER4_HI', 'regPA_SC_PERFCOUNTER4_HI_BASE_IDX',
'regPA_SC_PERFCOUNTER4_LO', 'regPA_SC_PERFCOUNTER4_LO_BASE_IDX',
'regPA_SC_PERFCOUNTER4_SELECT',
'regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX',
'regPA_SC_PERFCOUNTER5_HI', 'regPA_SC_PERFCOUNTER5_HI_BASE_IDX',
'regPA_SC_PERFCOUNTER5_LO', 'regPA_SC_PERFCOUNTER5_LO_BASE_IDX',
'regPA_SC_PERFCOUNTER5_SELECT',
'regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX',
'regPA_SC_PERFCOUNTER6_HI', 'regPA_SC_PERFCOUNTER6_HI_BASE_IDX',
'regPA_SC_PERFCOUNTER6_LO', 'regPA_SC_PERFCOUNTER6_LO_BASE_IDX',
'regPA_SC_PERFCOUNTER6_SELECT',
'regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX',
'regPA_SC_PERFCOUNTER7_HI', 'regPA_SC_PERFCOUNTER7_HI_BASE_IDX',
'regPA_SC_PERFCOUNTER7_LO', 'regPA_SC_PERFCOUNTER7_LO_BASE_IDX',
'regPA_SC_PERFCOUNTER7_SELECT',
'regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX',
'regPA_SC_PKR_WAVE_TABLE_CNTL',
'regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX', 'regPA_SC_RASTER_CONFIG',
'regPA_SC_RASTER_CONFIG_1', 'regPA_SC_RASTER_CONFIG_1_BASE_IDX',
'regPA_SC_RASTER_CONFIG_BASE_IDX',
'regPA_SC_SCREEN_EXTENT_CONTROL',
'regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX',
'regPA_SC_SCREEN_EXTENT_MAX_0',
'regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX',
'regPA_SC_SCREEN_EXTENT_MAX_1',
'regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX',
'regPA_SC_SCREEN_EXTENT_MIN_0',
'regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX',
'regPA_SC_SCREEN_EXTENT_MIN_1',
'regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX',
'regPA_SC_SCREEN_SCISSOR_BR',
'regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX',
'regPA_SC_SCREEN_SCISSOR_TL',
'regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX', 'regPA_SC_SHADER_CONTROL',
'regPA_SC_SHADER_CONTROL_BASE_IDX',
'regPA_SC_TILE_STEERING_CREST_OVERRIDE',
'regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX',
'regPA_SC_TILE_STEERING_OVERRIDE',
'regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX',
'regPA_SC_TRAP_SCREEN_COUNT',
'regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX', 'regPA_SC_TRAP_SCREEN_H',
'regPA_SC_TRAP_SCREEN_HV_EN',
'regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX',
'regPA_SC_TRAP_SCREEN_HV_LOCK',
'regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX',
'regPA_SC_TRAP_SCREEN_H_BASE_IDX',
'regPA_SC_TRAP_SCREEN_OCCURRENCE',
'regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX',
'regPA_SC_TRAP_SCREEN_V', 'regPA_SC_TRAP_SCREEN_V_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_0_BR',
'regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_0_TL',
'regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_10_BR',
'regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_10_TL',
'regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_11_BR',
'regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_11_TL',
'regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_12_BR',
'regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_12_TL',
'regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_13_BR',
'regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_13_TL',
'regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_14_BR',
'regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_14_TL',
'regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_15_BR',
'regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_15_TL',
'regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_1_BR',
'regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_1_TL',
'regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_2_BR',
'regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_2_TL',
'regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_3_BR',
'regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_3_TL',
'regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_4_BR',
'regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_4_TL',
'regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_5_BR',
'regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_5_TL',
'regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_6_BR',
'regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_6_TL',
'regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_7_BR',
'regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_7_TL',
'regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_8_BR',
'regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_8_TL',
'regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_9_BR',
'regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX',
'regPA_SC_VPORT_SCISSOR_9_TL',
'regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX', 'regPA_SC_VPORT_ZMAX_0',
'regPA_SC_VPORT_ZMAX_0_BASE_IDX', 'regPA_SC_VPORT_ZMAX_1',
'regPA_SC_VPORT_ZMAX_10', 'regPA_SC_VPORT_ZMAX_10_BASE_IDX',
'regPA_SC_VPORT_ZMAX_11', 'regPA_SC_VPORT_ZMAX_11_BASE_IDX',
'regPA_SC_VPORT_ZMAX_12', 'regPA_SC_VPORT_ZMAX_12_BASE_IDX',
'regPA_SC_VPORT_ZMAX_13', 'regPA_SC_VPORT_ZMAX_13_BASE_IDX',
'regPA_SC_VPORT_ZMAX_14', 'regPA_SC_VPORT_ZMAX_14_BASE_IDX',
'regPA_SC_VPORT_ZMAX_15', 'regPA_SC_VPORT_ZMAX_15_BASE_IDX',
'regPA_SC_VPORT_ZMAX_1_BASE_IDX', 'regPA_SC_VPORT_ZMAX_2',
'regPA_SC_VPORT_ZMAX_2_BASE_IDX', 'regPA_SC_VPORT_ZMAX_3',
'regPA_SC_VPORT_ZMAX_3_BASE_IDX', 'regPA_SC_VPORT_ZMAX_4',
'regPA_SC_VPORT_ZMAX_4_BASE_IDX', 'regPA_SC_VPORT_ZMAX_5',
'regPA_SC_VPORT_ZMAX_5_BASE_IDX', 'regPA_SC_VPORT_ZMAX_6',
'regPA_SC_VPORT_ZMAX_6_BASE_IDX', 'regPA_SC_VPORT_ZMAX_7',
'regPA_SC_VPORT_ZMAX_7_BASE_IDX', 'regPA_SC_VPORT_ZMAX_8',
'regPA_SC_VPORT_ZMAX_8_BASE_IDX', 'regPA_SC_VPORT_ZMAX_9',
'regPA_SC_VPORT_ZMAX_9_BASE_IDX', 'regPA_SC_VPORT_ZMIN_0',
'regPA_SC_VPORT_ZMIN_0_BASE_IDX', 'regPA_SC_VPORT_ZMIN_1',
'regPA_SC_VPORT_ZMIN_10', 'regPA_SC_VPORT_ZMIN_10_BASE_IDX',
'regPA_SC_VPORT_ZMIN_11', 'regPA_SC_VPORT_ZMIN_11_BASE_IDX',
'regPA_SC_VPORT_ZMIN_12', 'regPA_SC_VPORT_ZMIN_12_BASE_IDX',
'regPA_SC_VPORT_ZMIN_13', 'regPA_SC_VPORT_ZMIN_13_BASE_IDX',
'regPA_SC_VPORT_ZMIN_14', 'regPA_SC_VPORT_ZMIN_14_BASE_IDX',
'regPA_SC_VPORT_ZMIN_15', 'regPA_SC_VPORT_ZMIN_15_BASE_IDX',
'regPA_SC_VPORT_ZMIN_1_BASE_IDX', 'regPA_SC_VPORT_ZMIN_2',
'regPA_SC_VPORT_ZMIN_2_BASE_IDX', 'regPA_SC_VPORT_ZMIN_3',
'regPA_SC_VPORT_ZMIN_3_BASE_IDX', 'regPA_SC_VPORT_ZMIN_4',
'regPA_SC_VPORT_ZMIN_4_BASE_IDX', 'regPA_SC_VPORT_ZMIN_5',
'regPA_SC_VPORT_ZMIN_5_BASE_IDX', 'regPA_SC_VPORT_ZMIN_6',
'regPA_SC_VPORT_ZMIN_6_BASE_IDX', 'regPA_SC_VPORT_ZMIN_7',
'regPA_SC_VPORT_ZMIN_7_BASE_IDX', 'regPA_SC_VPORT_ZMIN_8',
'regPA_SC_VPORT_ZMIN_8_BASE_IDX', 'regPA_SC_VPORT_ZMIN_9',
'regPA_SC_VPORT_ZMIN_9_BASE_IDX', 'regPA_SC_VRS_OVERRIDE_CNTL',
'regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX', 'regPA_SC_VRS_RATE_BASE',
'regPA_SC_VRS_RATE_BASE_BASE_IDX', 'regPA_SC_VRS_RATE_BASE_EXT',
'regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX',
'regPA_SC_VRS_RATE_CACHE_CNTL',
'regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX',
'regPA_SC_VRS_RATE_FEEDBACK_BASE',
'regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX',
'regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT',
'regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX',
'regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY',
'regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX',
'regPA_SC_VRS_RATE_SIZE_XY', 'regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX',
'regPA_SC_VRS_SURFACE_CNTL', 'regPA_SC_VRS_SURFACE_CNTL_1',
'regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX',
'regPA_SC_VRS_SURFACE_CNTL_BASE_IDX', 'regPA_SC_WINDOW_OFFSET',
'regPA_SC_WINDOW_OFFSET_BASE_IDX', 'regPA_SC_WINDOW_SCISSOR_BR',
'regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX',
'regPA_SC_WINDOW_SCISSOR_TL',
'regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX', 'regPA_STATE_STEREO_X',
'regPA_STATE_STEREO_X_BASE_IDX', 'regPA_STEREO_CNTL',
'regPA_STEREO_CNTL_BASE_IDX', 'regPA_SU_CNTL_STATUS',
'regPA_SU_CNTL_STATUS_BASE_IDX',
'regPA_SU_HARDWARE_SCREEN_OFFSET',
'regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX', 'regPA_SU_LINE_CNTL',
'regPA_SU_LINE_CNTL_BASE_IDX', 'regPA_SU_LINE_STIPPLE_CNTL',
'regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX',
'regPA_SU_LINE_STIPPLE_SCALE',
'regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX',
'regPA_SU_LINE_STIPPLE_VALUE',
'regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX',
'regPA_SU_OVER_RASTERIZATION_CNTL',
'regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX',
'regPA_SU_PERFCOUNTER0_HI', 'regPA_SU_PERFCOUNTER0_HI_BASE_IDX',
'regPA_SU_PERFCOUNTER0_LO', 'regPA_SU_PERFCOUNTER0_LO_BASE_IDX',
'regPA_SU_PERFCOUNTER0_SELECT', 'regPA_SU_PERFCOUNTER0_SELECT1',
'regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX',
'regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX',
'regPA_SU_PERFCOUNTER1_HI', 'regPA_SU_PERFCOUNTER1_HI_BASE_IDX',
'regPA_SU_PERFCOUNTER1_LO', 'regPA_SU_PERFCOUNTER1_LO_BASE_IDX',
'regPA_SU_PERFCOUNTER1_SELECT', 'regPA_SU_PERFCOUNTER1_SELECT1',
'regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX',
'regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX',
'regPA_SU_PERFCOUNTER2_HI', 'regPA_SU_PERFCOUNTER2_HI_BASE_IDX',
'regPA_SU_PERFCOUNTER2_LO', 'regPA_SU_PERFCOUNTER2_LO_BASE_IDX',
'regPA_SU_PERFCOUNTER2_SELECT', 'regPA_SU_PERFCOUNTER2_SELECT1',
'regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX',
'regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX',
'regPA_SU_PERFCOUNTER3_HI', 'regPA_SU_PERFCOUNTER3_HI_BASE_IDX',
'regPA_SU_PERFCOUNTER3_LO', 'regPA_SU_PERFCOUNTER3_LO_BASE_IDX',
'regPA_SU_PERFCOUNTER3_SELECT', 'regPA_SU_PERFCOUNTER3_SELECT1',
'regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX',
'regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX', 'regPA_SU_POINT_MINMAX',
'regPA_SU_POINT_MINMAX_BASE_IDX', 'regPA_SU_POINT_SIZE',
'regPA_SU_POINT_SIZE_BASE_IDX',
'regPA_SU_POLY_OFFSET_BACK_OFFSET',
'regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX',
'regPA_SU_POLY_OFFSET_BACK_SCALE',
'regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX',
'regPA_SU_POLY_OFFSET_CLAMP',
'regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX',
'regPA_SU_POLY_OFFSET_DB_FMT_CNTL',
'regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX',
'regPA_SU_POLY_OFFSET_FRONT_OFFSET',
'regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX',
'regPA_SU_POLY_OFFSET_FRONT_SCALE',
'regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX',
'regPA_SU_PRIM_FILTER_CNTL', 'regPA_SU_PRIM_FILTER_CNTL_BASE_IDX',
'regPA_SU_SC_MODE_CNTL', 'regPA_SU_SC_MODE_CNTL_BASE_IDX',
'regPA_SU_SMALL_PRIM_FILTER_CNTL',
'regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX', 'regPA_SU_VTX_CNTL',
'regPA_SU_VTX_CNTL_BASE_IDX', 'regPCC_PERF_COUNTER',
'regPCC_PERF_COUNTER_BASE_IDX', 'regPCC_PWRBRK_HYSTERESIS_CTRL',
'regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX',
'regPCC_STALL_PATTERN_1_2', 'regPCC_STALL_PATTERN_1_2_BASE_IDX',
'regPCC_STALL_PATTERN_3_4', 'regPCC_STALL_PATTERN_3_4_BASE_IDX',
'regPCC_STALL_PATTERN_5_6', 'regPCC_STALL_PATTERN_5_6_BASE_IDX',
'regPCC_STALL_PATTERN_7', 'regPCC_STALL_PATTERN_7_BASE_IDX',
'regPCC_STALL_PATTERN_CTRL', 'regPCC_STALL_PATTERN_CTRL_BASE_IDX',
'regPC_PERFCOUNTER0_HI', 'regPC_PERFCOUNTER0_HI_BASE_IDX',
'regPC_PERFCOUNTER0_LO', 'regPC_PERFCOUNTER0_LO_BASE_IDX',
'regPC_PERFCOUNTER0_SELECT', 'regPC_PERFCOUNTER0_SELECT1',
'regPC_PERFCOUNTER0_SELECT1_BASE_IDX',
'regPC_PERFCOUNTER0_SELECT_BASE_IDX', 'regPC_PERFCOUNTER1_HI',
'regPC_PERFCOUNTER1_HI_BASE_IDX', 'regPC_PERFCOUNTER1_LO',
'regPC_PERFCOUNTER1_LO_BASE_IDX', 'regPC_PERFCOUNTER1_SELECT',
'regPC_PERFCOUNTER1_SELECT1',
'regPC_PERFCOUNTER1_SELECT1_BASE_IDX',
'regPC_PERFCOUNTER1_SELECT_BASE_IDX', 'regPC_PERFCOUNTER2_HI',
'regPC_PERFCOUNTER2_HI_BASE_IDX', 'regPC_PERFCOUNTER2_LO',
'regPC_PERFCOUNTER2_LO_BASE_IDX', 'regPC_PERFCOUNTER2_SELECT',
'regPC_PERFCOUNTER2_SELECT1',
'regPC_PERFCOUNTER2_SELECT1_BASE_IDX',
'regPC_PERFCOUNTER2_SELECT_BASE_IDX', 'regPC_PERFCOUNTER3_HI',
'regPC_PERFCOUNTER3_HI_BASE_IDX', 'regPC_PERFCOUNTER3_LO',
'regPC_PERFCOUNTER3_LO_BASE_IDX', 'regPC_PERFCOUNTER3_SELECT',
'regPC_PERFCOUNTER3_SELECT1',
'regPC_PERFCOUNTER3_SELECT1_BASE_IDX',
'regPC_PERFCOUNTER3_SELECT_BASE_IDX', 'regPMM_CNTL',
'regPMM_CNTL2', 'regPMM_CNTL2_BASE_IDX', 'regPMM_CNTL_BASE_IDX',
'regPMM_STATUS', 'regPMM_STATUS_BASE_IDX',
'regPWRBRK_PERF_COUNTER', 'regPWRBRK_PERF_COUNTER_BASE_IDX',
'regPWRBRK_STALL_PATTERN_1_2',
'regPWRBRK_STALL_PATTERN_1_2_BASE_IDX',
'regPWRBRK_STALL_PATTERN_3_4',
'regPWRBRK_STALL_PATTERN_3_4_BASE_IDX',
'regPWRBRK_STALL_PATTERN_5_6',
'regPWRBRK_STALL_PATTERN_5_6_BASE_IDX',
'regPWRBRK_STALL_PATTERN_7', 'regPWRBRK_STALL_PATTERN_7_BASE_IDX',
'regPWRBRK_STALL_PATTERN_CTRL',
'regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX', 'regRLC_AUTO_PG_CTRL',
'regRLC_AUTO_PG_CTRL_BASE_IDX', 'regRLC_BUSY_CLK_CNTL',
'regRLC_BUSY_CLK_CNTL_BASE_IDX', 'regRLC_CAC_MASK_CNTL',
'regRLC_CAC_MASK_CNTL_BASE_IDX', 'regRLC_CAPTURE_GPU_CLOCK_COUNT',
'regRLC_CAPTURE_GPU_CLOCK_COUNT_1',
'regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX',
'regRLC_CAPTURE_GPU_CLOCK_COUNT_2',
'regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX',
'regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX',
'regRLC_CGCG_CGLS_CTRL', 'regRLC_CGCG_CGLS_CTRL_3D',
'regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX',
'regRLC_CGCG_CGLS_CTRL_BASE_IDX', 'regRLC_CGCG_RAMP_CTRL',
'regRLC_CGCG_RAMP_CTRL_3D', 'regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX',
'regRLC_CGCG_RAMP_CTRL_BASE_IDX', 'regRLC_CGTT_MGCG_OVERRIDE',
'regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX', 'regRLC_CLK_CNTL',
'regRLC_CLK_CNTL_BASE_IDX', 'regRLC_CLK_COUNT_CTRL',
'regRLC_CLK_COUNT_CTRL_BASE_IDX', 'regRLC_CLK_COUNT_GFXCLK_LSB',
'regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX',
'regRLC_CLK_COUNT_GFXCLK_MSB',
'regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX',
'regRLC_CLK_COUNT_REFCLK_LSB',
'regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX',
'regRLC_CLK_COUNT_REFCLK_MSB',
'regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX', 'regRLC_CLK_COUNT_STAT',
'regRLC_CLK_COUNT_STAT_BASE_IDX',
'regRLC_CLK_RESIDENCY_CNTR_CTRL',
'regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX',
'regRLC_CLK_RESIDENCY_EVENT_CNTR',
'regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX',
'regRLC_CLK_RESIDENCY_REF_CNTR',
'regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_CNTL',
'regRLC_CNTL_BASE_IDX', 'regRLC_CP_EOF_INT',
'regRLC_CP_EOF_INT_BASE_IDX', 'regRLC_CP_EOF_INT_CNT',
'regRLC_CP_EOF_INT_CNT_BASE_IDX', 'regRLC_CP_SCHEDULERS',
'regRLC_CP_SCHEDULERS_BASE_IDX', 'regRLC_CP_STAT_INVAL_CTRL',
'regRLC_CP_STAT_INVAL_CTRL_BASE_IDX', 'regRLC_CP_STAT_INVAL_STAT',
'regRLC_CP_STAT_INVAL_STAT_BASE_IDX', 'regRLC_CSIB_ADDR_HI',
'regRLC_CSIB_ADDR_HI_BASE_IDX', 'regRLC_CSIB_ADDR_LO',
'regRLC_CSIB_ADDR_LO_BASE_IDX', 'regRLC_CSIB_LENGTH',
'regRLC_CSIB_LENGTH_BASE_IDX', 'regRLC_DS_RESIDENCY_CNTR_CTRL',
'regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX',
'regRLC_DS_RESIDENCY_EVENT_CNTR',
'regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX',
'regRLC_DS_RESIDENCY_REF_CNTR',
'regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_DYN_PG_REQUEST',
'regRLC_DYN_PG_REQUEST_BASE_IDX', 'regRLC_DYN_PG_STATUS',
'regRLC_DYN_PG_STATUS_BASE_IDX', 'regRLC_F32_UCODE_VERSION',
'regRLC_F32_UCODE_VERSION_BASE_IDX', 'regRLC_FWL_FIRST_VIOL_ADDR',
'regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX',
'regRLC_GENERAL_RESIDENCY_CNTR_CTRL',
'regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX',
'regRLC_GENERAL_RESIDENCY_EVENT_CNTR',
'regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX',
'regRLC_GENERAL_RESIDENCY_REF_CNTR',
'regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX',
'regRLC_GFX_IH_ARBITER_STAT',
'regRLC_GFX_IH_ARBITER_STAT_BASE_IDX',
'regRLC_GFX_IH_CLIENT_CTRL', 'regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX',
'regRLC_GFX_IH_CLIENT_OTHER_STAT',
'regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX',
'regRLC_GFX_IH_CLIENT_SDMA_STAT',
'regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX',
'regRLC_GFX_IH_CLIENT_SE_STAT_H',
'regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX',
'regRLC_GFX_IH_CLIENT_SE_STAT_L',
'regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX', 'regRLC_GFX_IMU_CMD',
'regRLC_GFX_IMU_CMD_BASE_IDX', 'regRLC_GFX_IMU_DATA_0',
'regRLC_GFX_IMU_DATA_0_BASE_IDX', 'regRLC_GPM_CP_DMA_COMPLETE_T0',
'regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX',
'regRLC_GPM_CP_DMA_COMPLETE_T1',
'regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX', 'regRLC_GPM_GENERAL_0',
'regRLC_GPM_GENERAL_0_BASE_IDX', 'regRLC_GPM_GENERAL_1',
'regRLC_GPM_GENERAL_10', 'regRLC_GPM_GENERAL_10_BASE_IDX',
'regRLC_GPM_GENERAL_11', 'regRLC_GPM_GENERAL_11_BASE_IDX',
'regRLC_GPM_GENERAL_12', 'regRLC_GPM_GENERAL_12_BASE_IDX',
'regRLC_GPM_GENERAL_13', 'regRLC_GPM_GENERAL_13_BASE_IDX',
'regRLC_GPM_GENERAL_14', 'regRLC_GPM_GENERAL_14_BASE_IDX',
'regRLC_GPM_GENERAL_15', 'regRLC_GPM_GENERAL_15_BASE_IDX',
'regRLC_GPM_GENERAL_16', 'regRLC_GPM_GENERAL_16_BASE_IDX',
'regRLC_GPM_GENERAL_1_BASE_IDX', 'regRLC_GPM_GENERAL_2',
'regRLC_GPM_GENERAL_2_BASE_IDX', 'regRLC_GPM_GENERAL_3',
'regRLC_GPM_GENERAL_3_BASE_IDX', 'regRLC_GPM_GENERAL_4',
'regRLC_GPM_GENERAL_4_BASE_IDX', 'regRLC_GPM_GENERAL_5',
'regRLC_GPM_GENERAL_5_BASE_IDX', 'regRLC_GPM_GENERAL_6',
'regRLC_GPM_GENERAL_6_BASE_IDX', 'regRLC_GPM_GENERAL_7',
'regRLC_GPM_GENERAL_7_BASE_IDX', 'regRLC_GPM_GENERAL_8',
'regRLC_GPM_GENERAL_8_BASE_IDX', 'regRLC_GPM_GENERAL_9',
'regRLC_GPM_GENERAL_9_BASE_IDX', 'regRLC_GPM_INT_DISABLE_TH0',
'regRLC_GPM_INT_DISABLE_TH0_BASE_IDX', 'regRLC_GPM_INT_FORCE_TH0',
'regRLC_GPM_INT_FORCE_TH0_BASE_IDX', 'regRLC_GPM_INT_STAT_TH0',
'regRLC_GPM_INT_STAT_TH0_BASE_IDX', 'regRLC_GPM_IRAM_ADDR',
'regRLC_GPM_IRAM_ADDR_BASE_IDX', 'regRLC_GPM_IRAM_DATA',
'regRLC_GPM_IRAM_DATA_BASE_IDX', 'regRLC_GPM_LEGACY_INT_CLEAR',
'regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX',
'regRLC_GPM_LEGACY_INT_DISABLE',
'regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX',
'regRLC_GPM_LEGACY_INT_STAT',
'regRLC_GPM_LEGACY_INT_STAT_BASE_IDX', 'regRLC_GPM_PERF_COUNT_0',
'regRLC_GPM_PERF_COUNT_0_BASE_IDX', 'regRLC_GPM_PERF_COUNT_1',
'regRLC_GPM_PERF_COUNT_1_BASE_IDX', 'regRLC_GPM_SCRATCH_ADDR',
'regRLC_GPM_SCRATCH_ADDR_BASE_IDX', 'regRLC_GPM_SCRATCH_DATA',
'regRLC_GPM_SCRATCH_DATA_BASE_IDX', 'regRLC_GPM_STAT',
'regRLC_GPM_STAT_BASE_IDX', 'regRLC_GPM_THREAD_ENABLE',
'regRLC_GPM_THREAD_ENABLE_BASE_IDX',
'regRLC_GPM_THREAD_INVALIDATE_CACHE',
'regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX',
'regRLC_GPM_THREAD_PRIORITY',
'regRLC_GPM_THREAD_PRIORITY_BASE_IDX', 'regRLC_GPM_THREAD_RESET',
'regRLC_GPM_THREAD_RESET_BASE_IDX', 'regRLC_GPM_TIMER_CTRL',
'regRLC_GPM_TIMER_CTRL_BASE_IDX', 'regRLC_GPM_TIMER_INT_0',
'regRLC_GPM_TIMER_INT_0_BASE_IDX', 'regRLC_GPM_TIMER_INT_1',
'regRLC_GPM_TIMER_INT_1_BASE_IDX', 'regRLC_GPM_TIMER_INT_2',
'regRLC_GPM_TIMER_INT_2_BASE_IDX', 'regRLC_GPM_TIMER_INT_3',
'regRLC_GPM_TIMER_INT_3_BASE_IDX', 'regRLC_GPM_TIMER_INT_4',
'regRLC_GPM_TIMER_INT_4_BASE_IDX', 'regRLC_GPM_TIMER_STAT',
'regRLC_GPM_TIMER_STAT_BASE_IDX', 'regRLC_GPM_UCODE_ADDR',
'regRLC_GPM_UCODE_ADDR_BASE_IDX', 'regRLC_GPM_UCODE_DATA',
'regRLC_GPM_UCODE_DATA_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_0',
'regRLC_GPM_UTCL1_CNTL_0_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_1',
'regRLC_GPM_UTCL1_CNTL_1_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_2',
'regRLC_GPM_UTCL1_CNTL_2_BASE_IDX',
'regRLC_GPM_UTCL1_TH0_ERROR_1',
'regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX',
'regRLC_GPM_UTCL1_TH0_ERROR_2',
'regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX',
'regRLC_GPM_UTCL1_TH1_ERROR_1',
'regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX',
'regRLC_GPM_UTCL1_TH1_ERROR_2',
'regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX',
'regRLC_GPM_UTCL1_TH2_ERROR_1',
'regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX',
'regRLC_GPM_UTCL1_TH2_ERROR_2',
'regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX', 'regRLC_GPR_REG1',
'regRLC_GPR_REG1_BASE_IDX', 'regRLC_GPR_REG2',
'regRLC_GPR_REG2_BASE_IDX', 'regRLC_GPU_CLOCK_32',
'regRLC_GPU_CLOCK_32_BASE_IDX', 'regRLC_GPU_CLOCK_32_RES_SEL',
'regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX',
'regRLC_GPU_CLOCK_COUNT_LSB', 'regRLC_GPU_CLOCK_COUNT_LSB_1',
'regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX',
'regRLC_GPU_CLOCK_COUNT_LSB_2',
'regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX',
'regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX',
'regRLC_GPU_CLOCK_COUNT_MSB', 'regRLC_GPU_CLOCK_COUNT_MSB_1',
'regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX',
'regRLC_GPU_CLOCK_COUNT_MSB_2',
'regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX',
'regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX',
'regRLC_GPU_CLOCK_COUNT_SPM_LSB',
'regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX',
'regRLC_GPU_CLOCK_COUNT_SPM_MSB',
'regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX',
'regRLC_GPU_IOV_CFG_REG1', 'regRLC_GPU_IOV_CFG_REG1_BASE_IDX',
'regRLC_GPU_IOV_CFG_REG2', 'regRLC_GPU_IOV_CFG_REG2_BASE_IDX',
'regRLC_GPU_IOV_CFG_REG6', 'regRLC_GPU_IOV_CFG_REG6_BASE_IDX',
'regRLC_GPU_IOV_CFG_REG8', 'regRLC_GPU_IOV_CFG_REG8_BASE_IDX',
'regRLC_GPU_IOV_F32_CNTL', 'regRLC_GPU_IOV_F32_CNTL_BASE_IDX',
'regRLC_GPU_IOV_F32_INVALIDATE_CACHE',
'regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX',
'regRLC_GPU_IOV_F32_RESET', 'regRLC_GPU_IOV_F32_RESET_BASE_IDX',
'regRLC_GPU_IOV_INT_DISABLE',
'regRLC_GPU_IOV_INT_DISABLE_BASE_IDX', 'regRLC_GPU_IOV_INT_FORCE',
'regRLC_GPU_IOV_INT_FORCE_BASE_IDX', 'regRLC_GPU_IOV_INT_STAT',
'regRLC_GPU_IOV_INT_STAT_BASE_IDX',
'regRLC_GPU_IOV_PERF_CNT_CNTL',
'regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX',
'regRLC_GPU_IOV_PERF_CNT_RD_ADDR',
'regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX',
'regRLC_GPU_IOV_PERF_CNT_RD_DATA',
'regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX',
'regRLC_GPU_IOV_PERF_CNT_WR_ADDR',
'regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX',
'regRLC_GPU_IOV_PERF_CNT_WR_DATA',
'regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX',
'regRLC_GPU_IOV_RLC_RESPONSE',
'regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX', 'regRLC_GPU_IOV_SCH_0',
'regRLC_GPU_IOV_SCH_0_BASE_IDX', 'regRLC_GPU_IOV_SCH_1',
'regRLC_GPU_IOV_SCH_1_BASE_IDX', 'regRLC_GPU_IOV_SCH_2',
'regRLC_GPU_IOV_SCH_2_BASE_IDX', 'regRLC_GPU_IOV_SCH_3',
'regRLC_GPU_IOV_SCH_3_BASE_IDX', 'regRLC_GPU_IOV_SCH_BLOCK',
'regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX',
'regRLC_GPU_IOV_SCRATCH_ADDR',
'regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX',
'regRLC_GPU_IOV_SCRATCH_DATA',
'regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX',
'regRLC_GPU_IOV_SDMA0_BUSY_STATUS',
'regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA0_STATUS',
'regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA1_BUSY_STATUS',
'regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA1_STATUS',
'regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA2_BUSY_STATUS',
'regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA2_STATUS',
'regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA3_BUSY_STATUS',
'regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA3_STATUS',
'regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA4_BUSY_STATUS',
'regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA4_STATUS',
'regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA5_BUSY_STATUS',
'regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA5_STATUS',
'regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA6_BUSY_STATUS',
'regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA6_STATUS',
'regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA7_BUSY_STATUS',
'regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SDMA7_STATUS',
'regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX',
'regRLC_GPU_IOV_SMU_RESPONSE',
'regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX',
'regRLC_GPU_IOV_UCODE_ADDR', 'regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX',
'regRLC_GPU_IOV_UCODE_DATA', 'regRLC_GPU_IOV_UCODE_DATA_BASE_IDX',
'regRLC_GPU_IOV_VF_DOORBELL_STATUS',
'regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX',
'regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR',
'regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX',
'regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET',
'regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX',
'regRLC_GPU_IOV_VF_ENABLE', 'regRLC_GPU_IOV_VF_ENABLE_BASE_IDX',
'regRLC_GPU_IOV_VF_MASK', 'regRLC_GPU_IOV_VF_MASK_BASE_IDX',
'regRLC_GPU_IOV_VM_BUSY_STATUS',
'regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX', 'regRLC_GTS_OFFSET_LSB',
'regRLC_GTS_OFFSET_LSB_BASE_IDX', 'regRLC_GTS_OFFSET_MSB',
'regRLC_GTS_OFFSET_MSB_BASE_IDX', 'regRLC_HYP_RLCG_UCODE_CHKSUM',
'regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX',
'regRLC_HYP_RLCP_UCODE_CHKSUM',
'regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX',
'regRLC_HYP_RLCV_UCODE_CHKSUM',
'regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX', 'regRLC_HYP_SEMAPHORE_0',
'regRLC_HYP_SEMAPHORE_0_BASE_IDX', 'regRLC_HYP_SEMAPHORE_1',
'regRLC_HYP_SEMAPHORE_1_BASE_IDX', 'regRLC_HYP_SEMAPHORE_2',
'regRLC_HYP_SEMAPHORE_2_BASE_IDX', 'regRLC_HYP_SEMAPHORE_3',
'regRLC_HYP_SEMAPHORE_3_BASE_IDX', 'regRLC_IH_COOKIE',
'regRLC_IH_COOKIE_BASE_IDX', 'regRLC_IH_COOKIE_CNTL',
'regRLC_IH_COOKIE_CNTL_BASE_IDX', 'regRLC_IMU_BOOTLOAD_ADDR_HI',
'regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX',
'regRLC_IMU_BOOTLOAD_ADDR_LO',
'regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX',
'regRLC_IMU_BOOTLOAD_SIZE', 'regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX',
'regRLC_IMU_MISC', 'regRLC_IMU_MISC_BASE_IDX',
'regRLC_IMU_RESET_VECTOR', 'regRLC_IMU_RESET_VECTOR_BASE_IDX',
'regRLC_INT_STAT', 'regRLC_INT_STAT_BASE_IDX',
'regRLC_JUMP_TABLE_RESTORE', 'regRLC_JUMP_TABLE_RESTORE_BASE_IDX',
'regRLC_LX6_CNTL', 'regRLC_LX6_CNTL_BASE_IDX',
'regRLC_LX6_DRAM_ADDR', 'regRLC_LX6_DRAM_ADDR_BASE_IDX',
'regRLC_LX6_DRAM_DATA', 'regRLC_LX6_DRAM_DATA_BASE_IDX',
'regRLC_LX6_IRAM_ADDR', 'regRLC_LX6_IRAM_ADDR_BASE_IDX',
'regRLC_LX6_IRAM_DATA', 'regRLC_LX6_IRAM_DATA_BASE_IDX',
'regRLC_MAX_PG_WGP', 'regRLC_MAX_PG_WGP_BASE_IDX',
'regRLC_MEM_SLP_CNTL', 'regRLC_MEM_SLP_CNTL_BASE_IDX',
'regRLC_MGCG_CTRL', 'regRLC_MGCG_CTRL_BASE_IDX',
'regRLC_PACE_INT_CLEAR', 'regRLC_PACE_INT_CLEAR_BASE_IDX',
'regRLC_PACE_INT_DISABLE', 'regRLC_PACE_INT_DISABLE_BASE_IDX',
'regRLC_PACE_INT_FORCE', 'regRLC_PACE_INT_FORCE_BASE_IDX',
'regRLC_PACE_INT_STAT', 'regRLC_PACE_INT_STAT_BASE_IDX',
'regRLC_PACE_SCRATCH_ADDR', 'regRLC_PACE_SCRATCH_ADDR_BASE_IDX',
'regRLC_PACE_SCRATCH_DATA', 'regRLC_PACE_SCRATCH_DATA_BASE_IDX',
'regRLC_PACE_SPARE_INT', 'regRLC_PACE_SPARE_INT_1',
'regRLC_PACE_SPARE_INT_1_BASE_IDX',
'regRLC_PACE_SPARE_INT_BASE_IDX', 'regRLC_PACE_TIMER_CTRL',
'regRLC_PACE_TIMER_CTRL_BASE_IDX', 'regRLC_PACE_TIMER_INT_0',
'regRLC_PACE_TIMER_INT_0_BASE_IDX', 'regRLC_PACE_TIMER_INT_1',
'regRLC_PACE_TIMER_INT_1_BASE_IDX', 'regRLC_PACE_TIMER_STAT',
'regRLC_PACE_TIMER_STAT_BASE_IDX', 'regRLC_PACE_UCODE_ADDR',
'regRLC_PACE_UCODE_ADDR_BASE_IDX', 'regRLC_PACE_UCODE_DATA',
'regRLC_PACE_UCODE_DATA_BASE_IDX',
'regRLC_PCC_RESIDENCY_CNTR_CTRL',
'regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX',
'regRLC_PCC_RESIDENCY_EVENT_CNTR',
'regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX',
'regRLC_PCC_RESIDENCY_REF_CNTR',
'regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX',
'regRLC_PERFCOUNTER0_HI', 'regRLC_PERFCOUNTER0_HI_BASE_IDX',
'regRLC_PERFCOUNTER0_LO', 'regRLC_PERFCOUNTER0_LO_BASE_IDX',
'regRLC_PERFCOUNTER0_SELECT',
'regRLC_PERFCOUNTER0_SELECT_BASE_IDX', 'regRLC_PERFCOUNTER1_HI',
'regRLC_PERFCOUNTER1_HI_BASE_IDX', 'regRLC_PERFCOUNTER1_LO',
'regRLC_PERFCOUNTER1_LO_BASE_IDX', 'regRLC_PERFCOUNTER1_SELECT',
'regRLC_PERFCOUNTER1_SELECT_BASE_IDX', 'regRLC_PERFMON_CNTL',
'regRLC_PERFMON_CNTL_BASE_IDX', 'regRLC_PG_ALWAYS_ON_WGP_MASK',
'regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX', 'regRLC_PG_CNTL',
'regRLC_PG_CNTL_BASE_IDX', 'regRLC_PG_DELAY', 'regRLC_PG_DELAY_2',
'regRLC_PG_DELAY_2_BASE_IDX', 'regRLC_PG_DELAY_3',
'regRLC_PG_DELAY_3_BASE_IDX', 'regRLC_PG_DELAY_BASE_IDX',
'regRLC_POWER_RESIDENCY_CNTR_CTRL',
'regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX',
'regRLC_POWER_RESIDENCY_EVENT_CNTR',
'regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX',
'regRLC_POWER_RESIDENCY_REF_CNTR',
'regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_R2I_CNTL_0',
'regRLC_R2I_CNTL_0_BASE_IDX', 'regRLC_R2I_CNTL_1',
'regRLC_R2I_CNTL_1_BASE_IDX', 'regRLC_R2I_CNTL_2',
'regRLC_R2I_CNTL_2_BASE_IDX', 'regRLC_R2I_CNTL_3',
'regRLC_R2I_CNTL_3_BASE_IDX', 'regRLC_REFCLOCK_TIMESTAMP_LSB',
'regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX',
'regRLC_REFCLOCK_TIMESTAMP_MSB',
'regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX',
'regRLC_RLCG_DOORBELL_0_DATA_HI',
'regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX',
'regRLC_RLCG_DOORBELL_0_DATA_LO',
'regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX',
'regRLC_RLCG_DOORBELL_1_DATA_HI',
'regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX',
'regRLC_RLCG_DOORBELL_1_DATA_LO',
'regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX',
'regRLC_RLCG_DOORBELL_2_DATA_HI',
'regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX',
'regRLC_RLCG_DOORBELL_2_DATA_LO',
'regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX',
'regRLC_RLCG_DOORBELL_3_DATA_HI',
'regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX',
'regRLC_RLCG_DOORBELL_3_DATA_LO',
'regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX',
'regRLC_RLCG_DOORBELL_CNTL', 'regRLC_RLCG_DOORBELL_CNTL_BASE_IDX',
'regRLC_RLCG_DOORBELL_RANGE',
'regRLC_RLCG_DOORBELL_RANGE_BASE_IDX',
'regRLC_RLCG_DOORBELL_STAT', 'regRLC_RLCG_DOORBELL_STAT_BASE_IDX',
'regRLC_RLCP_DOORBELL_0_DATA_HI',
'regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX',
'regRLC_RLCP_DOORBELL_0_DATA_LO',
'regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX',
'regRLC_RLCP_DOORBELL_1_DATA_HI',
'regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX',
'regRLC_RLCP_DOORBELL_1_DATA_LO',
'regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX',
'regRLC_RLCP_DOORBELL_2_DATA_HI',
'regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX',
'regRLC_RLCP_DOORBELL_2_DATA_LO',
'regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX',
'regRLC_RLCP_DOORBELL_3_DATA_HI',
'regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX',
'regRLC_RLCP_DOORBELL_3_DATA_LO',
'regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX',
'regRLC_RLCP_DOORBELL_CNTL', 'regRLC_RLCP_DOORBELL_CNTL_BASE_IDX',
'regRLC_RLCP_DOORBELL_RANGE',
'regRLC_RLCP_DOORBELL_RANGE_BASE_IDX',
'regRLC_RLCP_DOORBELL_STAT', 'regRLC_RLCP_DOORBELL_STAT_BASE_IDX',
'regRLC_RLCP_IRAM_ADDR', 'regRLC_RLCP_IRAM_ADDR_BASE_IDX',
'regRLC_RLCP_IRAM_DATA', 'regRLC_RLCP_IRAM_DATA_BASE_IDX',
'regRLC_RLCS_ABORTED_PD_SEQUENCE',
'regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX',
'regRLC_RLCS_AUXILIARY_REG_1',
'regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX',
'regRLC_RLCS_AUXILIARY_REG_2',
'regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX',
'regRLC_RLCS_AUXILIARY_REG_3',
'regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX',
'regRLC_RLCS_AUXILIARY_REG_4',
'regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX',
'regRLC_RLCS_BOOTLOAD_ID_STATUS1',
'regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX',
'regRLC_RLCS_BOOTLOAD_ID_STATUS2',
'regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX',
'regRLC_RLCS_BOOTLOAD_STATUS',
'regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX',
'regRLC_RLCS_CGCG_REQUEST', 'regRLC_RLCS_CGCG_REQUEST_BASE_IDX',
'regRLC_RLCS_CGCG_STATUS', 'regRLC_RLCS_CGCG_STATUS_BASE_IDX',
'regRLC_RLCS_CMP_IDLE_CNTL', 'regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX',
'regRLC_RLCS_CP_DMA_SRCID_OVER',
'regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX',
'regRLC_RLCS_CP_INT_CTRL_1', 'regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX',
'regRLC_RLCS_CP_INT_CTRL_2', 'regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX',
'regRLC_RLCS_CP_INT_INFO_1', 'regRLC_RLCS_CP_INT_INFO_1_BASE_IDX',
'regRLC_RLCS_CP_INT_INFO_2', 'regRLC_RLCS_CP_INT_INFO_2_BASE_IDX',
'regRLC_RLCS_DEC_DUMP_ADDR', 'regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX',
'regRLC_RLCS_DEC_END', 'regRLC_RLCS_DEC_END_BASE_IDX',
'regRLC_RLCS_DEC_START', 'regRLC_RLCS_DEC_START_BASE_IDX',
'regRLC_RLCS_DIDT_FORCE_STALL',
'regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX', 'regRLC_RLCS_DSM_TRIG',
'regRLC_RLCS_DSM_TRIG_BASE_IDX', 'regRLC_RLCS_EDC_INT_CNTL',
'regRLC_RLCS_EDC_INT_CNTL_BASE_IDX',
'regRLC_RLCS_EXCEPTION_REG_1',
'regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX',
'regRLC_RLCS_EXCEPTION_REG_2',
'regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX',
'regRLC_RLCS_EXCEPTION_REG_3',
'regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX',
'regRLC_RLCS_EXCEPTION_REG_4',
'regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX', 'regRLC_RLCS_GCR_DATA_0',
'regRLC_RLCS_GCR_DATA_0_BASE_IDX', 'regRLC_RLCS_GCR_DATA_1',
'regRLC_RLCS_GCR_DATA_1_BASE_IDX', 'regRLC_RLCS_GCR_DATA_2',
'regRLC_RLCS_GCR_DATA_2_BASE_IDX', 'regRLC_RLCS_GCR_DATA_3',
'regRLC_RLCS_GCR_DATA_3_BASE_IDX', 'regRLC_RLCS_GCR_STATUS',
'regRLC_RLCS_GCR_STATUS_BASE_IDX', 'regRLC_RLCS_GENERAL_0',
'regRLC_RLCS_GENERAL_0_BASE_IDX', 'regRLC_RLCS_GENERAL_1',
'regRLC_RLCS_GENERAL_10', 'regRLC_RLCS_GENERAL_10_BASE_IDX',
'regRLC_RLCS_GENERAL_11', 'regRLC_RLCS_GENERAL_11_BASE_IDX',
'regRLC_RLCS_GENERAL_12', 'regRLC_RLCS_GENERAL_12_BASE_IDX',
'regRLC_RLCS_GENERAL_13', 'regRLC_RLCS_GENERAL_13_BASE_IDX',
'regRLC_RLCS_GENERAL_14', 'regRLC_RLCS_GENERAL_14_BASE_IDX',
'regRLC_RLCS_GENERAL_15', 'regRLC_RLCS_GENERAL_15_BASE_IDX',
'regRLC_RLCS_GENERAL_16', 'regRLC_RLCS_GENERAL_16_BASE_IDX',
'regRLC_RLCS_GENERAL_1_BASE_IDX', 'regRLC_RLCS_GENERAL_2',
'regRLC_RLCS_GENERAL_2_BASE_IDX', 'regRLC_RLCS_GENERAL_3',
'regRLC_RLCS_GENERAL_3_BASE_IDX', 'regRLC_RLCS_GENERAL_4',
'regRLC_RLCS_GENERAL_4_BASE_IDX', 'regRLC_RLCS_GENERAL_5',
'regRLC_RLCS_GENERAL_5_BASE_IDX', 'regRLC_RLCS_GENERAL_6',
'regRLC_RLCS_GENERAL_6_BASE_IDX', 'regRLC_RLCS_GENERAL_7',
'regRLC_RLCS_GENERAL_7_BASE_IDX', 'regRLC_RLCS_GENERAL_8',
'regRLC_RLCS_GENERAL_8_BASE_IDX', 'regRLC_RLCS_GENERAL_9',
'regRLC_RLCS_GENERAL_9_BASE_IDX',
'regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL',
'regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX',
'regRLC_RLCS_GFX_DS_CNTL', 'regRLC_RLCS_GFX_DS_CNTL_BASE_IDX',
'regRLC_RLCS_GFX_MEM_POWER_CTRL_LO',
'regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX',
'regRLC_RLCS_GFX_RM_CNTL', 'regRLC_RLCS_GFX_RM_CNTL_BASE_IDX',
'regRLC_RLCS_GPM_LEGACY_INT_DISABLE',
'regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX',
'regRLC_RLCS_GPM_LEGACY_INT_STAT',
'regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX',
'regRLC_RLCS_GPM_STAT', 'regRLC_RLCS_GPM_STAT_2',
'regRLC_RLCS_GPM_STAT_2_BASE_IDX',
'regRLC_RLCS_GPM_STAT_BASE_IDX',
'regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL',
'regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX',
'regRLC_RLCS_GRBM_IDLE_BUSY_STAT',
'regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX',
'regRLC_RLCS_GRBM_SOFT_RESET',
'regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX',
'regRLC_RLCS_IH_COOKIE_SEMAPHORE',
'regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX',
'regRLC_RLCS_IH_SEMAPHORE', 'regRLC_RLCS_IH_SEMAPHORE_BASE_IDX',
'regRLC_RLCS_IMU_GFX_DOORBELL_FENCE',
'regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX',
'regRLC_RLCS_IMU_RAM_ADDR_0_LSB',
'regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX',
'regRLC_RLCS_IMU_RAM_ADDR_0_MSB',
'regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX',
'regRLC_RLCS_IMU_RAM_ADDR_1_LSB',
'regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX',
'regRLC_RLCS_IMU_RAM_ADDR_1_MSB',
'regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX',
'regRLC_RLCS_IMU_RAM_CNTL', 'regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX',
'regRLC_RLCS_IMU_RAM_DATA_0',
'regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX',
'regRLC_RLCS_IMU_RAM_DATA_1',
'regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX',
'regRLC_RLCS_IMU_RLC_MSG_CNTL',
'regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX',
'regRLC_RLCS_IMU_RLC_MSG_CONTROL',
'regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX',
'regRLC_RLCS_IMU_RLC_MSG_DATA0',
'regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX',
'regRLC_RLCS_IMU_RLC_MSG_DATA1',
'regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX',
'regRLC_RLCS_IMU_RLC_MSG_DATA2',
'regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX',
'regRLC_RLCS_IMU_RLC_MSG_DATA3',
'regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX',
'regRLC_RLCS_IMU_RLC_MSG_DATA4',
'regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX',
'regRLC_RLCS_IMU_RLC_MUTEX_CNTL',
'regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX',
'regRLC_RLCS_IMU_RLC_STATUS',
'regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX',
'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0',
'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX',
'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1',
'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX',
'regRLC_RLCS_IMU_VIDCHG_CNTL',
'regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX',
'regRLC_RLCS_IOV_CMD_STATUS',
'regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX',
'regRLC_RLCS_IOV_CNTX_LOC_SIZE',
'regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX',
'regRLC_RLCS_IOV_SCH_BLOCK', 'regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX',
'regRLC_RLCS_IOV_VM_BUSY_STATUS',
'regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX',
'regRLC_RLCS_KMD_LOG_CNTL1', 'regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX',
'regRLC_RLCS_KMD_LOG_CNTL2', 'regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX',
'regRLC_RLCS_PERFMON_CLK_CNTL_UCODE',
'regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX',
'regRLC_RLCS_PG_CHANGE_READ',
'regRLC_RLCS_PG_CHANGE_READ_BASE_IDX',
'regRLC_RLCS_PG_CHANGE_STATUS',
'regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX',
'regRLC_RLCS_PMM_CGCG_CNTL', 'regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX',
'regRLC_RLCS_POWER_BRAKE_CNTL',
'regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX',
'regRLC_RLCS_POWER_BRAKE_CNTL_TH1',
'regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX',
'regRLC_RLCS_RLC_IMU_MSG_CNTL',
'regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX',
'regRLC_RLCS_RLC_IMU_MSG_CONTROL',
'regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX',
'regRLC_RLCS_RLC_IMU_MSG_DATA0',
'regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX',
'regRLC_RLCS_RLC_IMU_STATUS',
'regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX',
'regRLC_RLCS_SDMA_INT_CNTL_1',
'regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX',
'regRLC_RLCS_SDMA_INT_CNTL_2',
'regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX',
'regRLC_RLCS_SDMA_INT_INFO', 'regRLC_RLCS_SDMA_INT_INFO_BASE_IDX',
'regRLC_RLCS_SDMA_INT_STAT', 'regRLC_RLCS_SDMA_INT_STAT_BASE_IDX',
'regRLC_RLCS_SOC_DS_CNTL', 'regRLC_RLCS_SOC_DS_CNTL_BASE_IDX',
'regRLC_RLCS_SPM_INT_CTRL', 'regRLC_RLCS_SPM_INT_CTRL_BASE_IDX',
'regRLC_RLCS_SPM_INT_INFO_1',
'regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX',
'regRLC_RLCS_SPM_INT_INFO_2',
'regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX',
'regRLC_RLCS_SPM_SQTT_MODE', 'regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX',
'regRLC_RLCS_SRM_SRCID_CNTL',
'regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX', 'regRLC_RLCS_UTCL2_CNTL',
'regRLC_RLCS_UTCL2_CNTL_BASE_IDX', 'regRLC_RLCS_WGP_READ',
'regRLC_RLCS_WGP_READ_BASE_IDX', 'regRLC_RLCS_WGP_STATUS',
'regRLC_RLCS_WGP_STATUS_BASE_IDX', 'regRLC_RLCV_COMMAND',
'regRLC_RLCV_COMMAND_BASE_IDX', 'regRLC_RLCV_DOORBELL_0_DATA_HI',
'regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX',
'regRLC_RLCV_DOORBELL_0_DATA_LO',
'regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX',
'regRLC_RLCV_DOORBELL_1_DATA_HI',
'regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX',
'regRLC_RLCV_DOORBELL_1_DATA_LO',
'regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX',
'regRLC_RLCV_DOORBELL_2_DATA_HI',
'regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX',
'regRLC_RLCV_DOORBELL_2_DATA_LO',
'regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX',
'regRLC_RLCV_DOORBELL_3_DATA_HI',
'regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX',
'regRLC_RLCV_DOORBELL_3_DATA_LO',
'regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX',
'regRLC_RLCV_DOORBELL_CNTL', 'regRLC_RLCV_DOORBELL_CNTL_BASE_IDX',
'regRLC_RLCV_DOORBELL_RANGE',
'regRLC_RLCV_DOORBELL_RANGE_BASE_IDX',
'regRLC_RLCV_DOORBELL_STAT', 'regRLC_RLCV_DOORBELL_STAT_BASE_IDX',
'regRLC_RLCV_IRAM_ADDR', 'regRLC_RLCV_IRAM_ADDR_BASE_IDX',
'regRLC_RLCV_IRAM_DATA', 'regRLC_RLCV_IRAM_DATA_BASE_IDX',
'regRLC_RLCV_SAFE_MODE', 'regRLC_RLCV_SAFE_MODE_BASE_IDX',
'regRLC_RLCV_SPARE_INT', 'regRLC_RLCV_SPARE_INT_1',
'regRLC_RLCV_SPARE_INT_1_BASE_IDX',
'regRLC_RLCV_SPARE_INT_BASE_IDX', 'regRLC_RLCV_TIMER_CTRL',
'regRLC_RLCV_TIMER_CTRL_BASE_IDX', 'regRLC_RLCV_TIMER_INT_0',
'regRLC_RLCV_TIMER_INT_0_BASE_IDX', 'regRLC_RLCV_TIMER_INT_1',
'regRLC_RLCV_TIMER_INT_1_BASE_IDX', 'regRLC_RLCV_TIMER_STAT',
'regRLC_RLCV_TIMER_STAT_BASE_IDX', 'regRLC_SAFE_MODE',
'regRLC_SAFE_MODE_BASE_IDX', 'regRLC_SDMA0_BUSY_STATUS',
'regRLC_SDMA0_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA0_STATUS',
'regRLC_SDMA0_STATUS_BASE_IDX', 'regRLC_SDMA1_BUSY_STATUS',
'regRLC_SDMA1_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA1_STATUS',
'regRLC_SDMA1_STATUS_BASE_IDX', 'regRLC_SDMA2_BUSY_STATUS',
'regRLC_SDMA2_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA2_STATUS',
'regRLC_SDMA2_STATUS_BASE_IDX', 'regRLC_SDMA3_BUSY_STATUS',
'regRLC_SDMA3_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA3_STATUS',
'regRLC_SDMA3_STATUS_BASE_IDX', 'regRLC_SEMAPHORE_0',
'regRLC_SEMAPHORE_0_BASE_IDX', 'regRLC_SEMAPHORE_1',
'regRLC_SEMAPHORE_1_BASE_IDX', 'regRLC_SEMAPHORE_2',
'regRLC_SEMAPHORE_2_BASE_IDX', 'regRLC_SEMAPHORE_3',
'regRLC_SEMAPHORE_3_BASE_IDX', 'regRLC_SERDES_BUSY',
'regRLC_SERDES_BUSY_BASE_IDX', 'regRLC_SERDES_CTRL',
'regRLC_SERDES_CTRL_BASE_IDX', 'regRLC_SERDES_DATA',
'regRLC_SERDES_DATA_BASE_IDX', 'regRLC_SERDES_MASK',
'regRLC_SERDES_MASK_BASE_IDX', 'regRLC_SERDES_RD_DATA_0',
'regRLC_SERDES_RD_DATA_0_BASE_IDX', 'regRLC_SERDES_RD_DATA_1',
'regRLC_SERDES_RD_DATA_1_BASE_IDX', 'regRLC_SERDES_RD_DATA_2',
'regRLC_SERDES_RD_DATA_2_BASE_IDX', 'regRLC_SERDES_RD_DATA_3',
'regRLC_SERDES_RD_DATA_3_BASE_IDX', 'regRLC_SERDES_RD_INDEX',
'regRLC_SERDES_RD_INDEX_BASE_IDX', 'regRLC_SMU_ARGUMENT_1',
'regRLC_SMU_ARGUMENT_1_BASE_IDX', 'regRLC_SMU_ARGUMENT_2',
'regRLC_SMU_ARGUMENT_2_BASE_IDX', 'regRLC_SMU_ARGUMENT_3',
'regRLC_SMU_ARGUMENT_3_BASE_IDX', 'regRLC_SMU_ARGUMENT_4',
'regRLC_SMU_ARGUMENT_4_BASE_IDX', 'regRLC_SMU_ARGUMENT_5',
'regRLC_SMU_ARGUMENT_5_BASE_IDX', 'regRLC_SMU_CLK_REQ',
'regRLC_SMU_CLK_REQ_BASE_IDX', 'regRLC_SMU_COMMAND',
'regRLC_SMU_COMMAND_BASE_IDX', 'regRLC_SMU_MESSAGE',
'regRLC_SMU_MESSAGE_1', 'regRLC_SMU_MESSAGE_1_BASE_IDX',
'regRLC_SMU_MESSAGE_2', 'regRLC_SMU_MESSAGE_2_BASE_IDX',
'regRLC_SMU_MESSAGE_BASE_IDX', 'regRLC_SMU_SAFE_MODE',
'regRLC_SMU_SAFE_MODE_BASE_IDX', 'regRLC_SPARE',
'regRLC_SPARE_BASE_IDX', 'regRLC_SPARE_INT_0',
'regRLC_SPARE_INT_0_BASE_IDX', 'regRLC_SPARE_INT_1',
'regRLC_SPARE_INT_1_BASE_IDX', 'regRLC_SPARE_INT_2',
'regRLC_SPARE_INT_2_BASE_IDX', 'regRLC_SPM_ACCUM_CTRL',
'regRLC_SPM_ACCUM_CTRLRAM_ADDR',
'regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX',
'regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET',
'regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX',
'regRLC_SPM_ACCUM_CTRLRAM_DATA',
'regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX',
'regRLC_SPM_ACCUM_CTRL_BASE_IDX',
'regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS',
'regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX',
'regRLC_SPM_ACCUM_DATARAM_ADDR',
'regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX',
'regRLC_SPM_ACCUM_DATARAM_DATA',
'regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX',
'regRLC_SPM_ACCUM_DATARAM_WRCOUNT',
'regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX',
'regRLC_SPM_ACCUM_MODE', 'regRLC_SPM_ACCUM_MODE_BASE_IDX',
'regRLC_SPM_ACCUM_SAMPLES_REQUESTED',
'regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX',
'regRLC_SPM_ACCUM_STATUS', 'regRLC_SPM_ACCUM_STATUS_BASE_IDX',
'regRLC_SPM_ACCUM_SWA_DATARAM_ADDR',
'regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX',
'regRLC_SPM_ACCUM_SWA_DATARAM_DATA',
'regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX',
'regRLC_SPM_ACCUM_THRESHOLD',
'regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX',
'regRLC_SPM_GFXCLOCK_HIGHCOUNT',
'regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX',
'regRLC_SPM_GFXCLOCK_LOWCOUNT',
'regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX',
'regRLC_SPM_GLOBAL_DELAY_IND_ADDR',
'regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX',
'regRLC_SPM_GLOBAL_DELAY_IND_DATA',
'regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX',
'regRLC_SPM_GLOBAL_MUXSEL_ADDR',
'regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX',
'regRLC_SPM_GLOBAL_MUXSEL_DATA',
'regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX', 'regRLC_SPM_INT_CNTL',
'regRLC_SPM_INT_CNTL_BASE_IDX', 'regRLC_SPM_INT_INFO_1',
'regRLC_SPM_INT_INFO_1_BASE_IDX', 'regRLC_SPM_INT_INFO_2',
'regRLC_SPM_INT_INFO_2_BASE_IDX', 'regRLC_SPM_INT_STATUS',
'regRLC_SPM_INT_STATUS_BASE_IDX', 'regRLC_SPM_MC_CNTL',
'regRLC_SPM_MC_CNTL_BASE_IDX', 'regRLC_SPM_MODE',
'regRLC_SPM_MODE_BASE_IDX', 'regRLC_SPM_PAUSE',
'regRLC_SPM_PAUSE_BASE_IDX', 'regRLC_SPM_PERFMON_CNTL',
'regRLC_SPM_PERFMON_CNTL_BASE_IDX',
'regRLC_SPM_PERFMON_RING_BASE_HI',
'regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX',
'regRLC_SPM_PERFMON_RING_BASE_LO',
'regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX',
'regRLC_SPM_PERFMON_RING_SIZE',
'regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX',
'regRLC_SPM_PERFMON_SEGMENT_SIZE',
'regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX',
'regRLC_SPM_RING_RDPTR', 'regRLC_SPM_RING_RDPTR_BASE_IDX',
'regRLC_SPM_RING_WRPTR', 'regRLC_SPM_RING_WRPTR_BASE_IDX',
'regRLC_SPM_RSPM_CMD', 'regRLC_SPM_RSPM_CMD_ACK',
'regRLC_SPM_RSPM_CMD_ACK_BASE_IDX',
'regRLC_SPM_RSPM_CMD_BASE_IDX', 'regRLC_SPM_RSPM_REQ_DATA_HI',
'regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX',
'regRLC_SPM_RSPM_REQ_DATA_LO',
'regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX', 'regRLC_SPM_RSPM_REQ_OP',
'regRLC_SPM_RSPM_REQ_OP_BASE_IDX', 'regRLC_SPM_RSPM_RET_DATA',
'regRLC_SPM_RSPM_RET_DATA_BASE_IDX', 'regRLC_SPM_RSPM_RET_OP',
'regRLC_SPM_RSPM_RET_OP_BASE_IDX', 'regRLC_SPM_SAMPLE_CNT',
'regRLC_SPM_SAMPLE_CNT_BASE_IDX', 'regRLC_SPM_SEGMENT_THRESHOLD',
'regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX',
'regRLC_SPM_SE_DELAY_IND_ADDR',
'regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX',
'regRLC_SPM_SE_DELAY_IND_DATA',
'regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX',
'regRLC_SPM_SE_MUXSEL_ADDR', 'regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX',
'regRLC_SPM_SE_MUXSEL_DATA', 'regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX',
'regRLC_SPM_SE_RSPM_REQ_DATA_HI',
'regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX',
'regRLC_SPM_SE_RSPM_REQ_DATA_LO',
'regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX',
'regRLC_SPM_SE_RSPM_REQ_OP', 'regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX',
'regRLC_SPM_SE_RSPM_RET_DATA',
'regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX',
'regRLC_SPM_SE_RSPM_RET_OP', 'regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX',
'regRLC_SPM_SPARE', 'regRLC_SPM_SPARE_BASE_IDX',
'regRLC_SPM_STATUS', 'regRLC_SPM_STATUS_BASE_IDX',
'regRLC_SPM_THREAD_TRACE_CTRL',
'regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX', 'regRLC_SPM_UTCL1_CNTL',
'regRLC_SPM_UTCL1_CNTL_BASE_IDX', 'regRLC_SPM_UTCL1_ERROR_1',
'regRLC_SPM_UTCL1_ERROR_1_BASE_IDX', 'regRLC_SPM_UTCL1_ERROR_2',
'regRLC_SPM_UTCL1_ERROR_2_BASE_IDX', 'regRLC_SPP_CAM_ADDR',
'regRLC_SPP_CAM_ADDR_BASE_IDX', 'regRLC_SPP_CAM_DATA',
'regRLC_SPP_CAM_DATA_BASE_IDX', 'regRLC_SPP_CAM_EXT_ADDR',
'regRLC_SPP_CAM_EXT_ADDR_BASE_IDX', 'regRLC_SPP_CAM_EXT_DATA',
'regRLC_SPP_CAM_EXT_DATA_BASE_IDX', 'regRLC_SPP_CTRL',
'regRLC_SPP_CTRL_BASE_IDX', 'regRLC_SPP_GLOBAL_SH_ID',
'regRLC_SPP_GLOBAL_SH_ID_BASE_IDX',
'regRLC_SPP_GLOBAL_SH_ID_VALID',
'regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX',
'regRLC_SPP_INFLIGHT_RD_ADDR',
'regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX',
'regRLC_SPP_INFLIGHT_RD_DATA',
'regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX', 'regRLC_SPP_PBB_INFO',
'regRLC_SPP_PBB_INFO_BASE_IDX', 'regRLC_SPP_PROF_INFO_1',
'regRLC_SPP_PROF_INFO_1_BASE_IDX', 'regRLC_SPP_PROF_INFO_2',
'regRLC_SPP_PROF_INFO_2_BASE_IDX', 'regRLC_SPP_PVT_LEVEL_MAX',
'regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX', 'regRLC_SPP_PVT_STAT_0',
'regRLC_SPP_PVT_STAT_0_BASE_IDX', 'regRLC_SPP_PVT_STAT_1',
'regRLC_SPP_PVT_STAT_1_BASE_IDX', 'regRLC_SPP_PVT_STAT_2',
'regRLC_SPP_PVT_STAT_2_BASE_IDX', 'regRLC_SPP_PVT_STAT_3',
'regRLC_SPP_PVT_STAT_3_BASE_IDX', 'regRLC_SPP_RESET',
'regRLC_SPP_RESET_BASE_IDX', 'regRLC_SPP_SHADER_PROFILE_EN',
'regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX',
'regRLC_SPP_SSF_CAPTURE_EN', 'regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX',
'regRLC_SPP_SSF_THRESHOLD_0',
'regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX',
'regRLC_SPP_SSF_THRESHOLD_1',
'regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX',
'regRLC_SPP_SSF_THRESHOLD_2',
'regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX',
'regRLC_SPP_STALL_STATE_UPDATE',
'regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX', 'regRLC_SPP_STATUS',
'regRLC_SPP_STATUS_BASE_IDX', 'regRLC_SRM_ARAM_ADDR',
'regRLC_SRM_ARAM_ADDR_BASE_IDX', 'regRLC_SRM_ARAM_DATA',
'regRLC_SRM_ARAM_DATA_BASE_IDX', 'regRLC_SRM_CNTL',
'regRLC_SRM_CNTL_BASE_IDX', 'regRLC_SRM_DRAM_ADDR',
'regRLC_SRM_DRAM_ADDR_BASE_IDX', 'regRLC_SRM_DRAM_DATA',
'regRLC_SRM_DRAM_DATA_BASE_IDX', 'regRLC_SRM_GPM_ABORT',
'regRLC_SRM_GPM_ABORT_BASE_IDX', 'regRLC_SRM_GPM_COMMAND',
'regRLC_SRM_GPM_COMMAND_BASE_IDX',
'regRLC_SRM_GPM_COMMAND_STATUS',
'regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_ADDR_0',
'regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_ADDR_1',
'regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_ADDR_2',
'regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_ADDR_3',
'regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_ADDR_4',
'regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_ADDR_5',
'regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_ADDR_6',
'regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_ADDR_7',
'regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_DATA_0',
'regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_DATA_1',
'regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_DATA_2',
'regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_DATA_3',
'regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_DATA_4',
'regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_DATA_5',
'regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_DATA_6',
'regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX',
'regRLC_SRM_INDEX_CNTL_DATA_7',
'regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX', 'regRLC_SRM_STAT',
'regRLC_SRM_STAT_BASE_IDX', 'regRLC_STAT',
'regRLC_STATIC_PG_STATUS', 'regRLC_STATIC_PG_STATUS_BASE_IDX',
'regRLC_STAT_BASE_IDX', 'regRLC_UCODE_CNTL',
'regRLC_UCODE_CNTL_BASE_IDX', 'regRLC_ULV_RESIDENCY_CNTR_CTRL',
'regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX',
'regRLC_ULV_RESIDENCY_EVENT_CNTR',
'regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX',
'regRLC_ULV_RESIDENCY_REF_CNTR',
'regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_UTCL1_STATUS',
'regRLC_UTCL1_STATUS_2', 'regRLC_UTCL1_STATUS_2_BASE_IDX',
'regRLC_UTCL1_STATUS_BASE_IDX', 'regRLC_WGP_STATUS',
'regRLC_WGP_STATUS_BASE_IDX', 'regRLC_XT_CORE_ALT_RESET_VEC',
'regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX',
'regRLC_XT_CORE_FAULT_INFO', 'regRLC_XT_CORE_FAULT_INFO_BASE_IDX',
'regRLC_XT_CORE_INTERRUPT', 'regRLC_XT_CORE_INTERRUPT_BASE_IDX',
'regRLC_XT_CORE_RESERVED', 'regRLC_XT_CORE_RESERVED_BASE_IDX',
'regRLC_XT_CORE_STATUS', 'regRLC_XT_CORE_STATUS_BASE_IDX',
'regRLC_XT_DOORBELL_0_DATA_HI',
'regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX',
'regRLC_XT_DOORBELL_0_DATA_LO',
'regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX',
'regRLC_XT_DOORBELL_1_DATA_HI',
'regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX',
'regRLC_XT_DOORBELL_1_DATA_LO',
'regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX',
'regRLC_XT_DOORBELL_2_DATA_HI',
'regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX',
'regRLC_XT_DOORBELL_2_DATA_LO',
'regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX',
'regRLC_XT_DOORBELL_3_DATA_HI',
'regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX',
'regRLC_XT_DOORBELL_3_DATA_LO',
'regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX',
'regRLC_XT_DOORBELL_CNTL', 'regRLC_XT_DOORBELL_CNTL_BASE_IDX',
'regRLC_XT_DOORBELL_RANGE', 'regRLC_XT_DOORBELL_RANGE_BASE_IDX',
'regRLC_XT_DOORBELL_STAT', 'regRLC_XT_DOORBELL_STAT_BASE_IDX',
'regRLC_XT_INT_VEC_CLEAR', 'regRLC_XT_INT_VEC_CLEAR_BASE_IDX',
'regRLC_XT_INT_VEC_FORCE', 'regRLC_XT_INT_VEC_FORCE_BASE_IDX',
'regRLC_XT_INT_VEC_MUX_INT_SEL',
'regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX',
'regRLC_XT_INT_VEC_MUX_SEL', 'regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX',
'regRMI_CLOCK_CNTRL', 'regRMI_CLOCK_CNTRL_BASE_IDX',
'regRMI_DEMUX_CNTL', 'regRMI_DEMUX_CNTL_BASE_IDX',
'regRMI_GENERAL_CNTL', 'regRMI_GENERAL_CNTL1',
'regRMI_GENERAL_CNTL1_BASE_IDX', 'regRMI_GENERAL_CNTL_BASE_IDX',
'regRMI_GENERAL_STATUS', 'regRMI_GENERAL_STATUS_BASE_IDX',
'regRMI_PERFCOUNTER0_HI', 'regRMI_PERFCOUNTER0_HI_BASE_IDX',
'regRMI_PERFCOUNTER0_LO', 'regRMI_PERFCOUNTER0_LO_BASE_IDX',
'regRMI_PERFCOUNTER0_SELECT', 'regRMI_PERFCOUNTER0_SELECT1',
'regRMI_PERFCOUNTER0_SELECT1_BASE_IDX',
'regRMI_PERFCOUNTER0_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER1_HI',
'regRMI_PERFCOUNTER1_HI_BASE_IDX', 'regRMI_PERFCOUNTER1_LO',
'regRMI_PERFCOUNTER1_LO_BASE_IDX', 'regRMI_PERFCOUNTER1_SELECT',
'regRMI_PERFCOUNTER1_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER2_HI',
'regRMI_PERFCOUNTER2_HI_BASE_IDX', 'regRMI_PERFCOUNTER2_LO',
'regRMI_PERFCOUNTER2_LO_BASE_IDX', 'regRMI_PERFCOUNTER2_SELECT',
'regRMI_PERFCOUNTER2_SELECT1',
'regRMI_PERFCOUNTER2_SELECT1_BASE_IDX',
'regRMI_PERFCOUNTER2_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER3_HI',
'regRMI_PERFCOUNTER3_HI_BASE_IDX', 'regRMI_PERFCOUNTER3_LO',
'regRMI_PERFCOUNTER3_LO_BASE_IDX', 'regRMI_PERFCOUNTER3_SELECT',
'regRMI_PERFCOUNTER3_SELECT_BASE_IDX', 'regRMI_PERF_COUNTER_CNTL',
'regRMI_PERF_COUNTER_CNTL_BASE_IDX',
'regRMI_PROBE_POP_LOGIC_CNTL',
'regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX', 'regRMI_RB_GLX_CID_MAP',
'regRMI_RB_GLX_CID_MAP_BASE_IDX', 'regRMI_SCOREBOARD_CNTL',
'regRMI_SCOREBOARD_CNTL_BASE_IDX', 'regRMI_SCOREBOARD_STATUS0',
'regRMI_SCOREBOARD_STATUS0_BASE_IDX', 'regRMI_SCOREBOARD_STATUS1',
'regRMI_SCOREBOARD_STATUS1_BASE_IDX', 'regRMI_SCOREBOARD_STATUS2',
'regRMI_SCOREBOARD_STATUS2_BASE_IDX', 'regRMI_SPARE',
'regRMI_SPARE_1', 'regRMI_SPARE_1_BASE_IDX', 'regRMI_SPARE_2',
'regRMI_SPARE_2_BASE_IDX', 'regRMI_SPARE_BASE_IDX',
'regRMI_SUBBLOCK_STATUS0', 'regRMI_SUBBLOCK_STATUS0_BASE_IDX',
'regRMI_SUBBLOCK_STATUS1', 'regRMI_SUBBLOCK_STATUS1_BASE_IDX',
'regRMI_SUBBLOCK_STATUS2', 'regRMI_SUBBLOCK_STATUS2_BASE_IDX',
'regRMI_SUBBLOCK_STATUS3', 'regRMI_SUBBLOCK_STATUS3_BASE_IDX',
'regRMI_TCIW_FORMATTER0_CNTL',
'regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX',
'regRMI_TCIW_FORMATTER1_CNTL',
'regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX', 'regRMI_UTCL1_CNTL1',
'regRMI_UTCL1_CNTL1_BASE_IDX', 'regRMI_UTCL1_CNTL2',
'regRMI_UTCL1_CNTL2_BASE_IDX', 'regRMI_UTCL1_STATUS',
'regRMI_UTCL1_STATUS_BASE_IDX', 'regRMI_UTC_UNIT_CONFIG',
'regRMI_UTC_UNIT_CONFIG_BASE_IDX', 'regRMI_UTC_XNACK_N_MISC_CNTL',
'regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX',
'regRMI_XBAR_ARBITER_CONFIG', 'regRMI_XBAR_ARBITER_CONFIG_1',
'regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX',
'regRMI_XBAR_ARBITER_CONFIG_BASE_IDX', 'regRMI_XBAR_CONFIG',
'regRMI_XBAR_CONFIG_BASE_IDX', 'regRTAVFS_RTAVFS_REG_ADDR',
'regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX', 'regRTAVFS_RTAVFS_WR_DATA',
'regRTAVFS_RTAVFS_WR_DATA_BASE_IDX', 'regSCRATCH_REG0',
'regSCRATCH_REG0_BASE_IDX', 'regSCRATCH_REG1',
'regSCRATCH_REG1_BASE_IDX', 'regSCRATCH_REG2',
'regSCRATCH_REG2_BASE_IDX', 'regSCRATCH_REG3',
'regSCRATCH_REG3_BASE_IDX', 'regSCRATCH_REG4',
'regSCRATCH_REG4_BASE_IDX', 'regSCRATCH_REG5',
'regSCRATCH_REG5_BASE_IDX', 'regSCRATCH_REG6',
'regSCRATCH_REG6_BASE_IDX', 'regSCRATCH_REG7',
'regSCRATCH_REG7_BASE_IDX', 'regSCRATCH_REG_ATOMIC',
'regSCRATCH_REG_ATOMIC_BASE_IDX', 'regSCRATCH_REG_CMPSWAP_ATOMIC',
'regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX', 'regSDMA0_AQL_STATUS',
'regSDMA0_AQL_STATUS_BASE_IDX', 'regSDMA0_ATOMIC_CNTL',
'regSDMA0_ATOMIC_CNTL_BASE_IDX', 'regSDMA0_ATOMIC_PREOP_HI',
'regSDMA0_ATOMIC_PREOP_HI_BASE_IDX', 'regSDMA0_ATOMIC_PREOP_LO',
'regSDMA0_ATOMIC_PREOP_LO_BASE_IDX', 'regSDMA0_BA_THRESHOLD',
'regSDMA0_BA_THRESHOLD_BASE_IDX', 'regSDMA0_BROADCAST_UCODE_ADDR',
'regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX',
'regSDMA0_BROADCAST_UCODE_DATA',
'regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX', 'regSDMA0_CE_CTRL',
'regSDMA0_CE_CTRL_BASE_IDX', 'regSDMA0_CHICKEN_BITS',
'regSDMA0_CHICKEN_BITS_2', 'regSDMA0_CHICKEN_BITS_2_BASE_IDX',
'regSDMA0_CHICKEN_BITS_BASE_IDX', 'regSDMA0_CLOCK_GATING_STATUS',
'regSDMA0_CLOCK_GATING_STATUS_BASE_IDX', 'regSDMA0_CNTL',
'regSDMA0_CNTL1', 'regSDMA0_CNTL1_BASE_IDX',
'regSDMA0_CNTL_BASE_IDX', 'regSDMA0_CRD_CNTL',
'regSDMA0_CRD_CNTL_BASE_IDX', 'regSDMA0_DEC_START',
'regSDMA0_DEC_START_BASE_IDX', 'regSDMA0_EA_DBIT_ADDR_DATA',
'regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX',
'regSDMA0_EA_DBIT_ADDR_INDEX',
'regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX', 'regSDMA0_EDC_CONFIG',
'regSDMA0_EDC_CONFIG_BASE_IDX', 'regSDMA0_EDC_COUNTER',
'regSDMA0_EDC_COUNTER_BASE_IDX', 'regSDMA0_EDC_COUNTER_CLEAR',
'regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX', 'regSDMA0_ERROR_LOG',
'regSDMA0_ERROR_LOG_BASE_IDX', 'regSDMA0_F32_CNTL',
'regSDMA0_F32_CNTL_BASE_IDX', 'regSDMA0_F32_COUNTER',
'regSDMA0_F32_COUNTER_BASE_IDX', 'regSDMA0_F32_MISC_CNTL',
'regSDMA0_F32_MISC_CNTL_BASE_IDX', 'regSDMA0_FED_STATUS',
'regSDMA0_FED_STATUS_BASE_IDX', 'regSDMA0_FREEZE',
'regSDMA0_FREEZE_BASE_IDX', 'regSDMA0_GB_ADDR_CONFIG',
'regSDMA0_GB_ADDR_CONFIG_BASE_IDX',
'regSDMA0_GB_ADDR_CONFIG_READ',
'regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX',
'regSDMA0_GLOBAL_QUANTUM', 'regSDMA0_GLOBAL_QUANTUM_BASE_IDX',
'regSDMA0_GLOBAL_TIMESTAMP_HI',
'regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX',
'regSDMA0_GLOBAL_TIMESTAMP_LO',
'regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX',
'regSDMA0_HBM_PAGE_CONFIG', 'regSDMA0_HBM_PAGE_CONFIG_BASE_IDX',
'regSDMA0_HOLE_ADDR_HI', 'regSDMA0_HOLE_ADDR_HI_BASE_IDX',
'regSDMA0_HOLE_ADDR_LO', 'regSDMA0_HOLE_ADDR_LO_BASE_IDX',
'regSDMA0_IB_OFFSET_FETCH', 'regSDMA0_IB_OFFSET_FETCH_BASE_IDX',
'regSDMA0_ID', 'regSDMA0_ID_BASE_IDX', 'regSDMA0_INT_STATUS',
'regSDMA0_INT_STATUS_BASE_IDX', 'regSDMA0_PERFCNT_MISC_CNTL',
'regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX',
'regSDMA0_PERFCNT_PERFCOUNTER0_CFG',
'regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX',
'regSDMA0_PERFCNT_PERFCOUNTER1_CFG',
'regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX',
'regSDMA0_PERFCNT_PERFCOUNTER_HI',
'regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX',
'regSDMA0_PERFCNT_PERFCOUNTER_LO',
'regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX',
'regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL',
'regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
'regSDMA0_PERFCOUNTER0_HI', 'regSDMA0_PERFCOUNTER0_HI_BASE_IDX',
'regSDMA0_PERFCOUNTER0_LO', 'regSDMA0_PERFCOUNTER0_LO_BASE_IDX',
'regSDMA0_PERFCOUNTER0_SELECT', 'regSDMA0_PERFCOUNTER0_SELECT1',
'regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX',
'regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX',
'regSDMA0_PERFCOUNTER1_HI', 'regSDMA0_PERFCOUNTER1_HI_BASE_IDX',
'regSDMA0_PERFCOUNTER1_LO', 'regSDMA0_PERFCOUNTER1_LO_BASE_IDX',
'regSDMA0_PERFCOUNTER1_SELECT', 'regSDMA0_PERFCOUNTER1_SELECT1',
'regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX',
'regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX',
'regSDMA0_PHYSICAL_ADDR_HI', 'regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX',
'regSDMA0_PHYSICAL_ADDR_LO', 'regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX',
'regSDMA0_POWER_CNTL', 'regSDMA0_POWER_CNTL_BASE_IDX',
'regSDMA0_PROCESS_QUANTUM0', 'regSDMA0_PROCESS_QUANTUM0_BASE_IDX',
'regSDMA0_PROCESS_QUANTUM1', 'regSDMA0_PROCESS_QUANTUM1_BASE_IDX',
'regSDMA0_PROGRAM', 'regSDMA0_PROGRAM_BASE_IDX',
'regSDMA0_PUB_DUMMY_REG0', 'regSDMA0_PUB_DUMMY_REG0_BASE_IDX',
'regSDMA0_PUB_DUMMY_REG1', 'regSDMA0_PUB_DUMMY_REG1_BASE_IDX',
'regSDMA0_PUB_DUMMY_REG2', 'regSDMA0_PUB_DUMMY_REG2_BASE_IDX',
'regSDMA0_PUB_DUMMY_REG3', 'regSDMA0_PUB_DUMMY_REG3_BASE_IDX',
'regSDMA0_QUEUE0_CONTEXT_STATUS',
'regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX',
'regSDMA0_QUEUE0_CSA_ADDR_HI',
'regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE0_CSA_ADDR_LO',
'regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE0_DOORBELL', 'regSDMA0_QUEUE0_DOORBELL_BASE_IDX',
'regSDMA0_QUEUE0_DOORBELL_LOG',
'regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX',
'regSDMA0_QUEUE0_DOORBELL_OFFSET',
'regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX',
'regSDMA0_QUEUE0_DUMMY_REG', 'regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX',
'regSDMA0_QUEUE0_IB_BASE_HI',
'regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX',
'regSDMA0_QUEUE0_IB_BASE_LO',
'regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE0_IB_CNTL',
'regSDMA0_QUEUE0_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_IB_OFFSET',
'regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE0_IB_RPTR',
'regSDMA0_QUEUE0_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE0_IB_SIZE',
'regSDMA0_QUEUE0_IB_SIZE_BASE_IDX',
'regSDMA0_QUEUE0_IB_SUB_REMAIN',
'regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX',
'regSDMA0_QUEUE0_MIDCMD_CNTL',
'regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX',
'regSDMA0_QUEUE0_MIDCMD_DATA0',
'regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX',
'regSDMA0_QUEUE0_MIDCMD_DATA1', 'regSDMA0_QUEUE0_MIDCMD_DATA10',
'regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX',
'regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX',
'regSDMA0_QUEUE0_MIDCMD_DATA2',
'regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX',
'regSDMA0_QUEUE0_MIDCMD_DATA3',
'regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX',
'regSDMA0_QUEUE0_MIDCMD_DATA4',
'regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX',
'regSDMA0_QUEUE0_MIDCMD_DATA5',
'regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX',
'regSDMA0_QUEUE0_MIDCMD_DATA6',
'regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX',
'regSDMA0_QUEUE0_MIDCMD_DATA7',
'regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX',
'regSDMA0_QUEUE0_MIDCMD_DATA8',
'regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX',
'regSDMA0_QUEUE0_MIDCMD_DATA9',
'regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX',
'regSDMA0_QUEUE0_MINOR_PTR_UPDATE',
'regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA0_QUEUE0_PREEMPT', 'regSDMA0_QUEUE0_PREEMPT_BASE_IDX',
'regSDMA0_QUEUE0_RB_AQL_CNTL',
'regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_RB_BASE',
'regSDMA0_QUEUE0_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE0_RB_BASE_HI',
'regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE0_RB_CNTL',
'regSDMA0_QUEUE0_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_RB_PREEMPT',
'regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE0_RB_RPTR',
'regSDMA0_QUEUE0_RB_RPTR_ADDR_HI',
'regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE0_RB_RPTR_ADDR_LO',
'regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE0_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE0_RB_RPTR_HI',
'regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE0_RB_WPTR',
'regSDMA0_QUEUE0_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE0_RB_WPTR_HI',
'regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX',
'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI',
'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO',
'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE0_SCHEDULE_CNTL',
'regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX',
'regSDMA0_QUEUE0_SKIP_CNTL', 'regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX',
'regSDMA0_QUEUE1_CONTEXT_STATUS',
'regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX',
'regSDMA0_QUEUE1_CSA_ADDR_HI',
'regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE1_CSA_ADDR_LO',
'regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE1_DOORBELL', 'regSDMA0_QUEUE1_DOORBELL_BASE_IDX',
'regSDMA0_QUEUE1_DOORBELL_LOG',
'regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX',
'regSDMA0_QUEUE1_DOORBELL_OFFSET',
'regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX',
'regSDMA0_QUEUE1_DUMMY_REG', 'regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX',
'regSDMA0_QUEUE1_IB_BASE_HI',
'regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX',
'regSDMA0_QUEUE1_IB_BASE_LO',
'regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE1_IB_CNTL',
'regSDMA0_QUEUE1_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_IB_OFFSET',
'regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE1_IB_RPTR',
'regSDMA0_QUEUE1_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE1_IB_SIZE',
'regSDMA0_QUEUE1_IB_SIZE_BASE_IDX',
'regSDMA0_QUEUE1_IB_SUB_REMAIN',
'regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX',
'regSDMA0_QUEUE1_MIDCMD_CNTL',
'regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX',
'regSDMA0_QUEUE1_MIDCMD_DATA0',
'regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX',
'regSDMA0_QUEUE1_MIDCMD_DATA1', 'regSDMA0_QUEUE1_MIDCMD_DATA10',
'regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX',
'regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX',
'regSDMA0_QUEUE1_MIDCMD_DATA2',
'regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX',
'regSDMA0_QUEUE1_MIDCMD_DATA3',
'regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX',
'regSDMA0_QUEUE1_MIDCMD_DATA4',
'regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX',
'regSDMA0_QUEUE1_MIDCMD_DATA5',
'regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX',
'regSDMA0_QUEUE1_MIDCMD_DATA6',
'regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX',
'regSDMA0_QUEUE1_MIDCMD_DATA7',
'regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX',
'regSDMA0_QUEUE1_MIDCMD_DATA8',
'regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX',
'regSDMA0_QUEUE1_MIDCMD_DATA9',
'regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX',
'regSDMA0_QUEUE1_MINOR_PTR_UPDATE',
'regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA0_QUEUE1_PREEMPT', 'regSDMA0_QUEUE1_PREEMPT_BASE_IDX',
'regSDMA0_QUEUE1_RB_AQL_CNTL',
'regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_RB_BASE',
'regSDMA0_QUEUE1_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE1_RB_BASE_HI',
'regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE1_RB_CNTL',
'regSDMA0_QUEUE1_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_RB_PREEMPT',
'regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE1_RB_RPTR',
'regSDMA0_QUEUE1_RB_RPTR_ADDR_HI',
'regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE1_RB_RPTR_ADDR_LO',
'regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE1_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE1_RB_RPTR_HI',
'regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE1_RB_WPTR',
'regSDMA0_QUEUE1_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE1_RB_WPTR_HI',
'regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX',
'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI',
'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO',
'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE1_SCHEDULE_CNTL',
'regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX',
'regSDMA0_QUEUE1_SKIP_CNTL', 'regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX',
'regSDMA0_QUEUE2_CONTEXT_STATUS',
'regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX',
'regSDMA0_QUEUE2_CSA_ADDR_HI',
'regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE2_CSA_ADDR_LO',
'regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE2_DOORBELL', 'regSDMA0_QUEUE2_DOORBELL_BASE_IDX',
'regSDMA0_QUEUE2_DOORBELL_LOG',
'regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX',
'regSDMA0_QUEUE2_DOORBELL_OFFSET',
'regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX',
'regSDMA0_QUEUE2_DUMMY_REG', 'regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX',
'regSDMA0_QUEUE2_IB_BASE_HI',
'regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX',
'regSDMA0_QUEUE2_IB_BASE_LO',
'regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE2_IB_CNTL',
'regSDMA0_QUEUE2_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_IB_OFFSET',
'regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE2_IB_RPTR',
'regSDMA0_QUEUE2_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE2_IB_SIZE',
'regSDMA0_QUEUE2_IB_SIZE_BASE_IDX',
'regSDMA0_QUEUE2_IB_SUB_REMAIN',
'regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX',
'regSDMA0_QUEUE2_MIDCMD_CNTL',
'regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX',
'regSDMA0_QUEUE2_MIDCMD_DATA0',
'regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX',
'regSDMA0_QUEUE2_MIDCMD_DATA1', 'regSDMA0_QUEUE2_MIDCMD_DATA10',
'regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX',
'regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX',
'regSDMA0_QUEUE2_MIDCMD_DATA2',
'regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX',
'regSDMA0_QUEUE2_MIDCMD_DATA3',
'regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX',
'regSDMA0_QUEUE2_MIDCMD_DATA4',
'regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX',
'regSDMA0_QUEUE2_MIDCMD_DATA5',
'regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX',
'regSDMA0_QUEUE2_MIDCMD_DATA6',
'regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX',
'regSDMA0_QUEUE2_MIDCMD_DATA7',
'regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX',
'regSDMA0_QUEUE2_MIDCMD_DATA8',
'regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX',
'regSDMA0_QUEUE2_MIDCMD_DATA9',
'regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX',
'regSDMA0_QUEUE2_MINOR_PTR_UPDATE',
'regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA0_QUEUE2_PREEMPT', 'regSDMA0_QUEUE2_PREEMPT_BASE_IDX',
'regSDMA0_QUEUE2_RB_AQL_CNTL',
'regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_RB_BASE',
'regSDMA0_QUEUE2_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE2_RB_BASE_HI',
'regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE2_RB_CNTL',
'regSDMA0_QUEUE2_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_RB_PREEMPT',
'regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE2_RB_RPTR',
'regSDMA0_QUEUE2_RB_RPTR_ADDR_HI',
'regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE2_RB_RPTR_ADDR_LO',
'regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE2_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE2_RB_RPTR_HI',
'regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE2_RB_WPTR',
'regSDMA0_QUEUE2_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE2_RB_WPTR_HI',
'regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX',
'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI',
'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO',
'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE2_SCHEDULE_CNTL',
'regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX',
'regSDMA0_QUEUE2_SKIP_CNTL', 'regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX',
'regSDMA0_QUEUE3_CONTEXT_STATUS',
'regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX',
'regSDMA0_QUEUE3_CSA_ADDR_HI',
'regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE3_CSA_ADDR_LO',
'regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE3_DOORBELL', 'regSDMA0_QUEUE3_DOORBELL_BASE_IDX',
'regSDMA0_QUEUE3_DOORBELL_LOG',
'regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX',
'regSDMA0_QUEUE3_DOORBELL_OFFSET',
'regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX',
'regSDMA0_QUEUE3_DUMMY_REG', 'regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX',
'regSDMA0_QUEUE3_IB_BASE_HI',
'regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX',
'regSDMA0_QUEUE3_IB_BASE_LO',
'regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE3_IB_CNTL',
'regSDMA0_QUEUE3_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_IB_OFFSET',
'regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE3_IB_RPTR',
'regSDMA0_QUEUE3_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE3_IB_SIZE',
'regSDMA0_QUEUE3_IB_SIZE_BASE_IDX',
'regSDMA0_QUEUE3_IB_SUB_REMAIN',
'regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX',
'regSDMA0_QUEUE3_MIDCMD_CNTL',
'regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX',
'regSDMA0_QUEUE3_MIDCMD_DATA0',
'regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX',
'regSDMA0_QUEUE3_MIDCMD_DATA1', 'regSDMA0_QUEUE3_MIDCMD_DATA10',
'regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX',
'regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX',
'regSDMA0_QUEUE3_MIDCMD_DATA2',
'regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX',
'regSDMA0_QUEUE3_MIDCMD_DATA3',
'regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX',
'regSDMA0_QUEUE3_MIDCMD_DATA4',
'regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX',
'regSDMA0_QUEUE3_MIDCMD_DATA5',
'regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX',
'regSDMA0_QUEUE3_MIDCMD_DATA6',
'regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX',
'regSDMA0_QUEUE3_MIDCMD_DATA7',
'regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX',
'regSDMA0_QUEUE3_MIDCMD_DATA8',
'regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX',
'regSDMA0_QUEUE3_MIDCMD_DATA9',
'regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX',
'regSDMA0_QUEUE3_MINOR_PTR_UPDATE',
'regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA0_QUEUE3_PREEMPT', 'regSDMA0_QUEUE3_PREEMPT_BASE_IDX',
'regSDMA0_QUEUE3_RB_AQL_CNTL',
'regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_RB_BASE',
'regSDMA0_QUEUE3_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE3_RB_BASE_HI',
'regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE3_RB_CNTL',
'regSDMA0_QUEUE3_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_RB_PREEMPT',
'regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE3_RB_RPTR',
'regSDMA0_QUEUE3_RB_RPTR_ADDR_HI',
'regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE3_RB_RPTR_ADDR_LO',
'regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE3_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE3_RB_RPTR_HI',
'regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE3_RB_WPTR',
'regSDMA0_QUEUE3_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE3_RB_WPTR_HI',
'regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX',
'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI',
'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO',
'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE3_SCHEDULE_CNTL',
'regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX',
'regSDMA0_QUEUE3_SKIP_CNTL', 'regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX',
'regSDMA0_QUEUE4_CONTEXT_STATUS',
'regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX',
'regSDMA0_QUEUE4_CSA_ADDR_HI',
'regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE4_CSA_ADDR_LO',
'regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE4_DOORBELL', 'regSDMA0_QUEUE4_DOORBELL_BASE_IDX',
'regSDMA0_QUEUE4_DOORBELL_LOG',
'regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX',
'regSDMA0_QUEUE4_DOORBELL_OFFSET',
'regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX',
'regSDMA0_QUEUE4_DUMMY_REG', 'regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX',
'regSDMA0_QUEUE4_IB_BASE_HI',
'regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX',
'regSDMA0_QUEUE4_IB_BASE_LO',
'regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE4_IB_CNTL',
'regSDMA0_QUEUE4_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_IB_OFFSET',
'regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE4_IB_RPTR',
'regSDMA0_QUEUE4_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE4_IB_SIZE',
'regSDMA0_QUEUE4_IB_SIZE_BASE_IDX',
'regSDMA0_QUEUE4_IB_SUB_REMAIN',
'regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX',
'regSDMA0_QUEUE4_MIDCMD_CNTL',
'regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX',
'regSDMA0_QUEUE4_MIDCMD_DATA0',
'regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX',
'regSDMA0_QUEUE4_MIDCMD_DATA1', 'regSDMA0_QUEUE4_MIDCMD_DATA10',
'regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX',
'regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX',
'regSDMA0_QUEUE4_MIDCMD_DATA2',
'regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX',
'regSDMA0_QUEUE4_MIDCMD_DATA3',
'regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX',
'regSDMA0_QUEUE4_MIDCMD_DATA4',
'regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX',
'regSDMA0_QUEUE4_MIDCMD_DATA5',
'regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX',
'regSDMA0_QUEUE4_MIDCMD_DATA6',
'regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX',
'regSDMA0_QUEUE4_MIDCMD_DATA7',
'regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX',
'regSDMA0_QUEUE4_MIDCMD_DATA8',
'regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX',
'regSDMA0_QUEUE4_MIDCMD_DATA9',
'regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX',
'regSDMA0_QUEUE4_MINOR_PTR_UPDATE',
'regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA0_QUEUE4_PREEMPT', 'regSDMA0_QUEUE4_PREEMPT_BASE_IDX',
'regSDMA0_QUEUE4_RB_AQL_CNTL',
'regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_RB_BASE',
'regSDMA0_QUEUE4_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE4_RB_BASE_HI',
'regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE4_RB_CNTL',
'regSDMA0_QUEUE4_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_RB_PREEMPT',
'regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE4_RB_RPTR',
'regSDMA0_QUEUE4_RB_RPTR_ADDR_HI',
'regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE4_RB_RPTR_ADDR_LO',
'regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE4_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE4_RB_RPTR_HI',
'regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE4_RB_WPTR',
'regSDMA0_QUEUE4_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE4_RB_WPTR_HI',
'regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX',
'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI',
'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO',
'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE4_SCHEDULE_CNTL',
'regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX',
'regSDMA0_QUEUE4_SKIP_CNTL', 'regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX',
'regSDMA0_QUEUE5_CONTEXT_STATUS',
'regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX',
'regSDMA0_QUEUE5_CSA_ADDR_HI',
'regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE5_CSA_ADDR_LO',
'regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE5_DOORBELL', 'regSDMA0_QUEUE5_DOORBELL_BASE_IDX',
'regSDMA0_QUEUE5_DOORBELL_LOG',
'regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX',
'regSDMA0_QUEUE5_DOORBELL_OFFSET',
'regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX',
'regSDMA0_QUEUE5_DUMMY_REG', 'regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX',
'regSDMA0_QUEUE5_IB_BASE_HI',
'regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX',
'regSDMA0_QUEUE5_IB_BASE_LO',
'regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE5_IB_CNTL',
'regSDMA0_QUEUE5_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_IB_OFFSET',
'regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE5_IB_RPTR',
'regSDMA0_QUEUE5_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE5_IB_SIZE',
'regSDMA0_QUEUE5_IB_SIZE_BASE_IDX',
'regSDMA0_QUEUE5_IB_SUB_REMAIN',
'regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX',
'regSDMA0_QUEUE5_MIDCMD_CNTL',
'regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX',
'regSDMA0_QUEUE5_MIDCMD_DATA0',
'regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX',
'regSDMA0_QUEUE5_MIDCMD_DATA1', 'regSDMA0_QUEUE5_MIDCMD_DATA10',
'regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX',
'regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX',
'regSDMA0_QUEUE5_MIDCMD_DATA2',
'regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX',
'regSDMA0_QUEUE5_MIDCMD_DATA3',
'regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX',
'regSDMA0_QUEUE5_MIDCMD_DATA4',
'regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX',
'regSDMA0_QUEUE5_MIDCMD_DATA5',
'regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX',
'regSDMA0_QUEUE5_MIDCMD_DATA6',
'regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX',
'regSDMA0_QUEUE5_MIDCMD_DATA7',
'regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX',
'regSDMA0_QUEUE5_MIDCMD_DATA8',
'regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX',
'regSDMA0_QUEUE5_MIDCMD_DATA9',
'regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX',
'regSDMA0_QUEUE5_MINOR_PTR_UPDATE',
'regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA0_QUEUE5_PREEMPT', 'regSDMA0_QUEUE5_PREEMPT_BASE_IDX',
'regSDMA0_QUEUE5_RB_AQL_CNTL',
'regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_RB_BASE',
'regSDMA0_QUEUE5_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE5_RB_BASE_HI',
'regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE5_RB_CNTL',
'regSDMA0_QUEUE5_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_RB_PREEMPT',
'regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE5_RB_RPTR',
'regSDMA0_QUEUE5_RB_RPTR_ADDR_HI',
'regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE5_RB_RPTR_ADDR_LO',
'regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE5_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE5_RB_RPTR_HI',
'regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE5_RB_WPTR',
'regSDMA0_QUEUE5_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE5_RB_WPTR_HI',
'regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX',
'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI',
'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO',
'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE5_SCHEDULE_CNTL',
'regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX',
'regSDMA0_QUEUE5_SKIP_CNTL', 'regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX',
'regSDMA0_QUEUE6_CONTEXT_STATUS',
'regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX',
'regSDMA0_QUEUE6_CSA_ADDR_HI',
'regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE6_CSA_ADDR_LO',
'regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE6_DOORBELL', 'regSDMA0_QUEUE6_DOORBELL_BASE_IDX',
'regSDMA0_QUEUE6_DOORBELL_LOG',
'regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX',
'regSDMA0_QUEUE6_DOORBELL_OFFSET',
'regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX',
'regSDMA0_QUEUE6_DUMMY_REG', 'regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX',
'regSDMA0_QUEUE6_IB_BASE_HI',
'regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX',
'regSDMA0_QUEUE6_IB_BASE_LO',
'regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE6_IB_CNTL',
'regSDMA0_QUEUE6_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_IB_OFFSET',
'regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE6_IB_RPTR',
'regSDMA0_QUEUE6_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE6_IB_SIZE',
'regSDMA0_QUEUE6_IB_SIZE_BASE_IDX',
'regSDMA0_QUEUE6_IB_SUB_REMAIN',
'regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX',
'regSDMA0_QUEUE6_MIDCMD_CNTL',
'regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX',
'regSDMA0_QUEUE6_MIDCMD_DATA0',
'regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX',
'regSDMA0_QUEUE6_MIDCMD_DATA1', 'regSDMA0_QUEUE6_MIDCMD_DATA10',
'regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX',
'regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX',
'regSDMA0_QUEUE6_MIDCMD_DATA2',
'regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX',
'regSDMA0_QUEUE6_MIDCMD_DATA3',
'regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX',
'regSDMA0_QUEUE6_MIDCMD_DATA4',
'regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX',
'regSDMA0_QUEUE6_MIDCMD_DATA5',
'regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX',
'regSDMA0_QUEUE6_MIDCMD_DATA6',
'regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX',
'regSDMA0_QUEUE6_MIDCMD_DATA7',
'regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX',
'regSDMA0_QUEUE6_MIDCMD_DATA8',
'regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX',
'regSDMA0_QUEUE6_MIDCMD_DATA9',
'regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX',
'regSDMA0_QUEUE6_MINOR_PTR_UPDATE',
'regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA0_QUEUE6_PREEMPT', 'regSDMA0_QUEUE6_PREEMPT_BASE_IDX',
'regSDMA0_QUEUE6_RB_AQL_CNTL',
'regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_RB_BASE',
'regSDMA0_QUEUE6_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE6_RB_BASE_HI',
'regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE6_RB_CNTL',
'regSDMA0_QUEUE6_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_RB_PREEMPT',
'regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE6_RB_RPTR',
'regSDMA0_QUEUE6_RB_RPTR_ADDR_HI',
'regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE6_RB_RPTR_ADDR_LO',
'regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE6_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE6_RB_RPTR_HI',
'regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE6_RB_WPTR',
'regSDMA0_QUEUE6_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE6_RB_WPTR_HI',
'regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX',
'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI',
'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO',
'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE6_SCHEDULE_CNTL',
'regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX',
'regSDMA0_QUEUE6_SKIP_CNTL', 'regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX',
'regSDMA0_QUEUE7_CONTEXT_STATUS',
'regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX',
'regSDMA0_QUEUE7_CSA_ADDR_HI',
'regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE7_CSA_ADDR_LO',
'regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE7_DOORBELL', 'regSDMA0_QUEUE7_DOORBELL_BASE_IDX',
'regSDMA0_QUEUE7_DOORBELL_LOG',
'regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX',
'regSDMA0_QUEUE7_DOORBELL_OFFSET',
'regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX',
'regSDMA0_QUEUE7_DUMMY_REG', 'regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX',
'regSDMA0_QUEUE7_IB_BASE_HI',
'regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX',
'regSDMA0_QUEUE7_IB_BASE_LO',
'regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE7_IB_CNTL',
'regSDMA0_QUEUE7_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_IB_OFFSET',
'regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE7_IB_RPTR',
'regSDMA0_QUEUE7_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE7_IB_SIZE',
'regSDMA0_QUEUE7_IB_SIZE_BASE_IDX',
'regSDMA0_QUEUE7_IB_SUB_REMAIN',
'regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX',
'regSDMA0_QUEUE7_MIDCMD_CNTL',
'regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX',
'regSDMA0_QUEUE7_MIDCMD_DATA0',
'regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX',
'regSDMA0_QUEUE7_MIDCMD_DATA1', 'regSDMA0_QUEUE7_MIDCMD_DATA10',
'regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX',
'regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX',
'regSDMA0_QUEUE7_MIDCMD_DATA2',
'regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX',
'regSDMA0_QUEUE7_MIDCMD_DATA3',
'regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX',
'regSDMA0_QUEUE7_MIDCMD_DATA4',
'regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX',
'regSDMA0_QUEUE7_MIDCMD_DATA5',
'regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX',
'regSDMA0_QUEUE7_MIDCMD_DATA6',
'regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX',
'regSDMA0_QUEUE7_MIDCMD_DATA7',
'regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX',
'regSDMA0_QUEUE7_MIDCMD_DATA8',
'regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX',
'regSDMA0_QUEUE7_MIDCMD_DATA9',
'regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX',
'regSDMA0_QUEUE7_MINOR_PTR_UPDATE',
'regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA0_QUEUE7_PREEMPT', 'regSDMA0_QUEUE7_PREEMPT_BASE_IDX',
'regSDMA0_QUEUE7_RB_AQL_CNTL',
'regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_RB_BASE',
'regSDMA0_QUEUE7_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE7_RB_BASE_HI',
'regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE7_RB_CNTL',
'regSDMA0_QUEUE7_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_RB_PREEMPT',
'regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE7_RB_RPTR',
'regSDMA0_QUEUE7_RB_RPTR_ADDR_HI',
'regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE7_RB_RPTR_ADDR_LO',
'regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE7_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE7_RB_RPTR_HI',
'regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE7_RB_WPTR',
'regSDMA0_QUEUE7_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE7_RB_WPTR_HI',
'regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX',
'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI',
'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO',
'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA0_QUEUE7_SCHEDULE_CNTL',
'regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX',
'regSDMA0_QUEUE7_SKIP_CNTL', 'regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX',
'regSDMA0_QUEUE_RESET_REQ', 'regSDMA0_QUEUE_RESET_REQ_BASE_IDX',
'regSDMA0_QUEUE_STATUS0', 'regSDMA0_QUEUE_STATUS0_BASE_IDX',
'regSDMA0_RB_RPTR_FETCH', 'regSDMA0_RB_RPTR_FETCH_BASE_IDX',
'regSDMA0_RB_RPTR_FETCH_HI', 'regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX',
'regSDMA0_RELAX_ORDERING_LUT',
'regSDMA0_RELAX_ORDERING_LUT_BASE_IDX', 'regSDMA0_RLC_CGCG_CTRL',
'regSDMA0_RLC_CGCG_CTRL_BASE_IDX', 'regSDMA0_SCRATCH_RAM_ADDR',
'regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX', 'regSDMA0_SCRATCH_RAM_DATA',
'regSDMA0_SCRATCH_RAM_DATA_BASE_IDX',
'regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL',
'regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX',
'regSDMA0_STATUS1_REG', 'regSDMA0_STATUS1_REG_BASE_IDX',
'regSDMA0_STATUS2_REG', 'regSDMA0_STATUS2_REG_BASE_IDX',
'regSDMA0_STATUS3_REG', 'regSDMA0_STATUS3_REG_BASE_IDX',
'regSDMA0_STATUS4_REG', 'regSDMA0_STATUS4_REG_BASE_IDX',
'regSDMA0_STATUS5_REG', 'regSDMA0_STATUS5_REG_BASE_IDX',
'regSDMA0_STATUS6_REG', 'regSDMA0_STATUS6_REG_BASE_IDX',
'regSDMA0_STATUS_REG', 'regSDMA0_STATUS_REG_BASE_IDX',
'regSDMA0_TILING_CONFIG', 'regSDMA0_TILING_CONFIG_BASE_IDX',
'regSDMA0_TIMESTAMP_CNTL', 'regSDMA0_TIMESTAMP_CNTL_BASE_IDX',
'regSDMA0_TLBI_GCR_CNTL', 'regSDMA0_TLBI_GCR_CNTL_BASE_IDX',
'regSDMA0_UCODE1_CHECKSUM', 'regSDMA0_UCODE1_CHECKSUM_BASE_IDX',
'regSDMA0_UCODE_ADDR', 'regSDMA0_UCODE_ADDR_BASE_IDX',
'regSDMA0_UCODE_CHECKSUM', 'regSDMA0_UCODE_CHECKSUM_BASE_IDX',
'regSDMA0_UCODE_DATA', 'regSDMA0_UCODE_DATA_BASE_IDX',
'regSDMA0_UCODE_SELFLOAD_CONTROL',
'regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX', 'regSDMA0_UTCL1_CNTL',
'regSDMA0_UTCL1_CNTL_BASE_IDX', 'regSDMA0_UTCL1_INV0',
'regSDMA0_UTCL1_INV0_BASE_IDX', 'regSDMA0_UTCL1_INV1',
'regSDMA0_UTCL1_INV1_BASE_IDX', 'regSDMA0_UTCL1_INV2',
'regSDMA0_UTCL1_INV2_BASE_IDX', 'regSDMA0_UTCL1_PAGE',
'regSDMA0_UTCL1_PAGE_BASE_IDX', 'regSDMA0_UTCL1_RD_STATUS',
'regSDMA0_UTCL1_RD_STATUS_BASE_IDX', 'regSDMA0_UTCL1_RD_XNACK0',
'regSDMA0_UTCL1_RD_XNACK0_BASE_IDX', 'regSDMA0_UTCL1_RD_XNACK1',
'regSDMA0_UTCL1_RD_XNACK1_BASE_IDX', 'regSDMA0_UTCL1_TIMEOUT',
'regSDMA0_UTCL1_TIMEOUT_BASE_IDX', 'regSDMA0_UTCL1_WATERMK',
'regSDMA0_UTCL1_WATERMK_BASE_IDX', 'regSDMA0_UTCL1_WR_STATUS',
'regSDMA0_UTCL1_WR_STATUS_BASE_IDX', 'regSDMA0_UTCL1_WR_XNACK0',
'regSDMA0_UTCL1_WR_XNACK0_BASE_IDX', 'regSDMA0_UTCL1_WR_XNACK1',
'regSDMA0_UTCL1_WR_XNACK1_BASE_IDX', 'regSDMA0_VERSION',
'regSDMA0_VERSION_BASE_IDX', 'regSDMA0_WATCHDOG_CNTL',
'regSDMA0_WATCHDOG_CNTL_BASE_IDX', 'regSDMA1_AQL_STATUS',
'regSDMA1_AQL_STATUS_BASE_IDX', 'regSDMA1_ATOMIC_CNTL',
'regSDMA1_ATOMIC_CNTL_BASE_IDX', 'regSDMA1_ATOMIC_PREOP_HI',
'regSDMA1_ATOMIC_PREOP_HI_BASE_IDX', 'regSDMA1_ATOMIC_PREOP_LO',
'regSDMA1_ATOMIC_PREOP_LO_BASE_IDX', 'regSDMA1_BA_THRESHOLD',
'regSDMA1_BA_THRESHOLD_BASE_IDX', 'regSDMA1_BROADCAST_UCODE_ADDR',
'regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX',
'regSDMA1_BROADCAST_UCODE_DATA',
'regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX', 'regSDMA1_CE_CTRL',
'regSDMA1_CE_CTRL_BASE_IDX', 'regSDMA1_CHICKEN_BITS',
'regSDMA1_CHICKEN_BITS_2', 'regSDMA1_CHICKEN_BITS_2_BASE_IDX',
'regSDMA1_CHICKEN_BITS_BASE_IDX', 'regSDMA1_CLOCK_GATING_STATUS',
'regSDMA1_CLOCK_GATING_STATUS_BASE_IDX', 'regSDMA1_CNTL',
'regSDMA1_CNTL1', 'regSDMA1_CNTL1_BASE_IDX',
'regSDMA1_CNTL_BASE_IDX', 'regSDMA1_CRD_CNTL',
'regSDMA1_CRD_CNTL_BASE_IDX', 'regSDMA1_DEC_START',
'regSDMA1_DEC_START_BASE_IDX', 'regSDMA1_EA_DBIT_ADDR_DATA',
'regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX',
'regSDMA1_EA_DBIT_ADDR_INDEX',
'regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX', 'regSDMA1_EDC_CONFIG',
'regSDMA1_EDC_CONFIG_BASE_IDX', 'regSDMA1_EDC_COUNTER',
'regSDMA1_EDC_COUNTER_BASE_IDX', 'regSDMA1_EDC_COUNTER_CLEAR',
'regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX', 'regSDMA1_ERROR_LOG',
'regSDMA1_ERROR_LOG_BASE_IDX', 'regSDMA1_F32_CNTL',
'regSDMA1_F32_CNTL_BASE_IDX', 'regSDMA1_F32_COUNTER',
'regSDMA1_F32_COUNTER_BASE_IDX', 'regSDMA1_F32_MISC_CNTL',
'regSDMA1_F32_MISC_CNTL_BASE_IDX', 'regSDMA1_FED_STATUS',
'regSDMA1_FED_STATUS_BASE_IDX', 'regSDMA1_FREEZE',
'regSDMA1_FREEZE_BASE_IDX', 'regSDMA1_GB_ADDR_CONFIG',
'regSDMA1_GB_ADDR_CONFIG_BASE_IDX',
'regSDMA1_GB_ADDR_CONFIG_READ',
'regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX',
'regSDMA1_GLOBAL_QUANTUM', 'regSDMA1_GLOBAL_QUANTUM_BASE_IDX',
'regSDMA1_GLOBAL_TIMESTAMP_HI',
'regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX',
'regSDMA1_GLOBAL_TIMESTAMP_LO',
'regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX',
'regSDMA1_HBM_PAGE_CONFIG', 'regSDMA1_HBM_PAGE_CONFIG_BASE_IDX',
'regSDMA1_HOLE_ADDR_HI', 'regSDMA1_HOLE_ADDR_HI_BASE_IDX',
'regSDMA1_HOLE_ADDR_LO', 'regSDMA1_HOLE_ADDR_LO_BASE_IDX',
'regSDMA1_IB_OFFSET_FETCH', 'regSDMA1_IB_OFFSET_FETCH_BASE_IDX',
'regSDMA1_ID', 'regSDMA1_ID_BASE_IDX', 'regSDMA1_INT_STATUS',
'regSDMA1_INT_STATUS_BASE_IDX', 'regSDMA1_PERFCNT_MISC_CNTL',
'regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX',
'regSDMA1_PERFCNT_PERFCOUNTER0_CFG',
'regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX',
'regSDMA1_PERFCNT_PERFCOUNTER1_CFG',
'regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX',
'regSDMA1_PERFCNT_PERFCOUNTER_HI',
'regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX',
'regSDMA1_PERFCNT_PERFCOUNTER_LO',
'regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX',
'regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL',
'regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
'regSDMA1_PERFCOUNTER0_HI', 'regSDMA1_PERFCOUNTER0_HI_BASE_IDX',
'regSDMA1_PERFCOUNTER0_LO', 'regSDMA1_PERFCOUNTER0_LO_BASE_IDX',
'regSDMA1_PERFCOUNTER0_SELECT', 'regSDMA1_PERFCOUNTER0_SELECT1',
'regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX',
'regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX',
'regSDMA1_PERFCOUNTER1_HI', 'regSDMA1_PERFCOUNTER1_HI_BASE_IDX',
'regSDMA1_PERFCOUNTER1_LO', 'regSDMA1_PERFCOUNTER1_LO_BASE_IDX',
'regSDMA1_PERFCOUNTER1_SELECT', 'regSDMA1_PERFCOUNTER1_SELECT1',
'regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX',
'regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX',
'regSDMA1_PHYSICAL_ADDR_HI', 'regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX',
'regSDMA1_PHYSICAL_ADDR_LO', 'regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX',
'regSDMA1_POWER_CNTL', 'regSDMA1_POWER_CNTL_BASE_IDX',
'regSDMA1_PROCESS_QUANTUM0', 'regSDMA1_PROCESS_QUANTUM0_BASE_IDX',
'regSDMA1_PROCESS_QUANTUM1', 'regSDMA1_PROCESS_QUANTUM1_BASE_IDX',
'regSDMA1_PROGRAM', 'regSDMA1_PROGRAM_BASE_IDX',
'regSDMA1_PUB_DUMMY_REG0', 'regSDMA1_PUB_DUMMY_REG0_BASE_IDX',
'regSDMA1_PUB_DUMMY_REG1', 'regSDMA1_PUB_DUMMY_REG1_BASE_IDX',
'regSDMA1_PUB_DUMMY_REG2', 'regSDMA1_PUB_DUMMY_REG2_BASE_IDX',
'regSDMA1_PUB_DUMMY_REG3', 'regSDMA1_PUB_DUMMY_REG3_BASE_IDX',
'regSDMA1_QUEUE0_CONTEXT_STATUS',
'regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX',
'regSDMA1_QUEUE0_CSA_ADDR_HI',
'regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE0_CSA_ADDR_LO',
'regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE0_DOORBELL', 'regSDMA1_QUEUE0_DOORBELL_BASE_IDX',
'regSDMA1_QUEUE0_DOORBELL_LOG',
'regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX',
'regSDMA1_QUEUE0_DOORBELL_OFFSET',
'regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX',
'regSDMA1_QUEUE0_DUMMY_REG', 'regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX',
'regSDMA1_QUEUE0_IB_BASE_HI',
'regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX',
'regSDMA1_QUEUE0_IB_BASE_LO',
'regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE0_IB_CNTL',
'regSDMA1_QUEUE0_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_IB_OFFSET',
'regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE0_IB_RPTR',
'regSDMA1_QUEUE0_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE0_IB_SIZE',
'regSDMA1_QUEUE0_IB_SIZE_BASE_IDX',
'regSDMA1_QUEUE0_IB_SUB_REMAIN',
'regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX',
'regSDMA1_QUEUE0_MIDCMD_CNTL',
'regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX',
'regSDMA1_QUEUE0_MIDCMD_DATA0',
'regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX',
'regSDMA1_QUEUE0_MIDCMD_DATA1', 'regSDMA1_QUEUE0_MIDCMD_DATA10',
'regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX',
'regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX',
'regSDMA1_QUEUE0_MIDCMD_DATA2',
'regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX',
'regSDMA1_QUEUE0_MIDCMD_DATA3',
'regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX',
'regSDMA1_QUEUE0_MIDCMD_DATA4',
'regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX',
'regSDMA1_QUEUE0_MIDCMD_DATA5',
'regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX',
'regSDMA1_QUEUE0_MIDCMD_DATA6',
'regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX',
'regSDMA1_QUEUE0_MIDCMD_DATA7',
'regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX',
'regSDMA1_QUEUE0_MIDCMD_DATA8',
'regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX',
'regSDMA1_QUEUE0_MIDCMD_DATA9',
'regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX',
'regSDMA1_QUEUE0_MINOR_PTR_UPDATE',
'regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA1_QUEUE0_PREEMPT', 'regSDMA1_QUEUE0_PREEMPT_BASE_IDX',
'regSDMA1_QUEUE0_RB_AQL_CNTL',
'regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_RB_BASE',
'regSDMA1_QUEUE0_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE0_RB_BASE_HI',
'regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE0_RB_CNTL',
'regSDMA1_QUEUE0_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_RB_PREEMPT',
'regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE0_RB_RPTR',
'regSDMA1_QUEUE0_RB_RPTR_ADDR_HI',
'regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE0_RB_RPTR_ADDR_LO',
'regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE0_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE0_RB_RPTR_HI',
'regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE0_RB_WPTR',
'regSDMA1_QUEUE0_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE0_RB_WPTR_HI',
'regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX',
'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI',
'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO',
'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE0_SCHEDULE_CNTL',
'regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX',
'regSDMA1_QUEUE0_SKIP_CNTL', 'regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX',
'regSDMA1_QUEUE1_CONTEXT_STATUS',
'regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX',
'regSDMA1_QUEUE1_CSA_ADDR_HI',
'regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE1_CSA_ADDR_LO',
'regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE1_DOORBELL', 'regSDMA1_QUEUE1_DOORBELL_BASE_IDX',
'regSDMA1_QUEUE1_DOORBELL_LOG',
'regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX',
'regSDMA1_QUEUE1_DOORBELL_OFFSET',
'regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX',
'regSDMA1_QUEUE1_DUMMY_REG', 'regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX',
'regSDMA1_QUEUE1_IB_BASE_HI',
'regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX',
'regSDMA1_QUEUE1_IB_BASE_LO',
'regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE1_IB_CNTL',
'regSDMA1_QUEUE1_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_IB_OFFSET',
'regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE1_IB_RPTR',
'regSDMA1_QUEUE1_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE1_IB_SIZE',
'regSDMA1_QUEUE1_IB_SIZE_BASE_IDX',
'regSDMA1_QUEUE1_IB_SUB_REMAIN',
'regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX',
'regSDMA1_QUEUE1_MIDCMD_CNTL',
'regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX',
'regSDMA1_QUEUE1_MIDCMD_DATA0',
'regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX',
'regSDMA1_QUEUE1_MIDCMD_DATA1', 'regSDMA1_QUEUE1_MIDCMD_DATA10',
'regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX',
'regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX',
'regSDMA1_QUEUE1_MIDCMD_DATA2',
'regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX',
'regSDMA1_QUEUE1_MIDCMD_DATA3',
'regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX',
'regSDMA1_QUEUE1_MIDCMD_DATA4',
'regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX',
'regSDMA1_QUEUE1_MIDCMD_DATA5',
'regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX',
'regSDMA1_QUEUE1_MIDCMD_DATA6',
'regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX',
'regSDMA1_QUEUE1_MIDCMD_DATA7',
'regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX',
'regSDMA1_QUEUE1_MIDCMD_DATA8',
'regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX',
'regSDMA1_QUEUE1_MIDCMD_DATA9',
'regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX',
'regSDMA1_QUEUE1_MINOR_PTR_UPDATE',
'regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA1_QUEUE1_PREEMPT', 'regSDMA1_QUEUE1_PREEMPT_BASE_IDX',
'regSDMA1_QUEUE1_RB_AQL_CNTL',
'regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_RB_BASE',
'regSDMA1_QUEUE1_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE1_RB_BASE_HI',
'regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE1_RB_CNTL',
'regSDMA1_QUEUE1_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_RB_PREEMPT',
'regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE1_RB_RPTR',
'regSDMA1_QUEUE1_RB_RPTR_ADDR_HI',
'regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE1_RB_RPTR_ADDR_LO',
'regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE1_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE1_RB_RPTR_HI',
'regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE1_RB_WPTR',
'regSDMA1_QUEUE1_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE1_RB_WPTR_HI',
'regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX',
'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI',
'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO',
'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE1_SCHEDULE_CNTL',
'regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX',
'regSDMA1_QUEUE1_SKIP_CNTL', 'regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX',
'regSDMA1_QUEUE2_CONTEXT_STATUS',
'regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX',
'regSDMA1_QUEUE2_CSA_ADDR_HI',
'regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE2_CSA_ADDR_LO',
'regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE2_DOORBELL', 'regSDMA1_QUEUE2_DOORBELL_BASE_IDX',
'regSDMA1_QUEUE2_DOORBELL_LOG',
'regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX',
'regSDMA1_QUEUE2_DOORBELL_OFFSET',
'regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX',
'regSDMA1_QUEUE2_DUMMY_REG', 'regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX',
'regSDMA1_QUEUE2_IB_BASE_HI',
'regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX',
'regSDMA1_QUEUE2_IB_BASE_LO',
'regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE2_IB_CNTL',
'regSDMA1_QUEUE2_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_IB_OFFSET',
'regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE2_IB_RPTR',
'regSDMA1_QUEUE2_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE2_IB_SIZE',
'regSDMA1_QUEUE2_IB_SIZE_BASE_IDX',
'regSDMA1_QUEUE2_IB_SUB_REMAIN',
'regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX',
'regSDMA1_QUEUE2_MIDCMD_CNTL',
'regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX',
'regSDMA1_QUEUE2_MIDCMD_DATA0',
'regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX',
'regSDMA1_QUEUE2_MIDCMD_DATA1', 'regSDMA1_QUEUE2_MIDCMD_DATA10',
'regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX',
'regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX',
'regSDMA1_QUEUE2_MIDCMD_DATA2',
'regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX',
'regSDMA1_QUEUE2_MIDCMD_DATA3',
'regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX',
'regSDMA1_QUEUE2_MIDCMD_DATA4',
'regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX',
'regSDMA1_QUEUE2_MIDCMD_DATA5',
'regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX',
'regSDMA1_QUEUE2_MIDCMD_DATA6',
'regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX',
'regSDMA1_QUEUE2_MIDCMD_DATA7',
'regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX',
'regSDMA1_QUEUE2_MIDCMD_DATA8',
'regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX',
'regSDMA1_QUEUE2_MIDCMD_DATA9',
'regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX',
'regSDMA1_QUEUE2_MINOR_PTR_UPDATE',
'regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA1_QUEUE2_PREEMPT', 'regSDMA1_QUEUE2_PREEMPT_BASE_IDX',
'regSDMA1_QUEUE2_RB_AQL_CNTL',
'regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_RB_BASE',
'regSDMA1_QUEUE2_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE2_RB_BASE_HI',
'regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE2_RB_CNTL',
'regSDMA1_QUEUE2_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_RB_PREEMPT',
'regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE2_RB_RPTR',
'regSDMA1_QUEUE2_RB_RPTR_ADDR_HI',
'regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE2_RB_RPTR_ADDR_LO',
'regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE2_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE2_RB_RPTR_HI',
'regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE2_RB_WPTR',
'regSDMA1_QUEUE2_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE2_RB_WPTR_HI',
'regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX',
'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI',
'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO',
'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE2_SCHEDULE_CNTL',
'regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX',
'regSDMA1_QUEUE2_SKIP_CNTL', 'regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX',
'regSDMA1_QUEUE3_CONTEXT_STATUS',
'regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX',
'regSDMA1_QUEUE3_CSA_ADDR_HI',
'regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE3_CSA_ADDR_LO',
'regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE3_DOORBELL', 'regSDMA1_QUEUE3_DOORBELL_BASE_IDX',
'regSDMA1_QUEUE3_DOORBELL_LOG',
'regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX',
'regSDMA1_QUEUE3_DOORBELL_OFFSET',
'regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX',
'regSDMA1_QUEUE3_DUMMY_REG', 'regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX',
'regSDMA1_QUEUE3_IB_BASE_HI',
'regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX',
'regSDMA1_QUEUE3_IB_BASE_LO',
'regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE3_IB_CNTL',
'regSDMA1_QUEUE3_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_IB_OFFSET',
'regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE3_IB_RPTR',
'regSDMA1_QUEUE3_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE3_IB_SIZE',
'regSDMA1_QUEUE3_IB_SIZE_BASE_IDX',
'regSDMA1_QUEUE3_IB_SUB_REMAIN',
'regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX',
'regSDMA1_QUEUE3_MIDCMD_CNTL',
'regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX',
'regSDMA1_QUEUE3_MIDCMD_DATA0',
'regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX',
'regSDMA1_QUEUE3_MIDCMD_DATA1', 'regSDMA1_QUEUE3_MIDCMD_DATA10',
'regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX',
'regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX',
'regSDMA1_QUEUE3_MIDCMD_DATA2',
'regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX',
'regSDMA1_QUEUE3_MIDCMD_DATA3',
'regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX',
'regSDMA1_QUEUE3_MIDCMD_DATA4',
'regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX',
'regSDMA1_QUEUE3_MIDCMD_DATA5',
'regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX',
'regSDMA1_QUEUE3_MIDCMD_DATA6',
'regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX',
'regSDMA1_QUEUE3_MIDCMD_DATA7',
'regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX',
'regSDMA1_QUEUE3_MIDCMD_DATA8',
'regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX',
'regSDMA1_QUEUE3_MIDCMD_DATA9',
'regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX',
'regSDMA1_QUEUE3_MINOR_PTR_UPDATE',
'regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA1_QUEUE3_PREEMPT', 'regSDMA1_QUEUE3_PREEMPT_BASE_IDX',
'regSDMA1_QUEUE3_RB_AQL_CNTL',
'regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_RB_BASE',
'regSDMA1_QUEUE3_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE3_RB_BASE_HI',
'regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE3_RB_CNTL',
'regSDMA1_QUEUE3_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_RB_PREEMPT',
'regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE3_RB_RPTR',
'regSDMA1_QUEUE3_RB_RPTR_ADDR_HI',
'regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE3_RB_RPTR_ADDR_LO',
'regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE3_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE3_RB_RPTR_HI',
'regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE3_RB_WPTR',
'regSDMA1_QUEUE3_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE3_RB_WPTR_HI',
'regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX',
'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI',
'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO',
'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE3_SCHEDULE_CNTL',
'regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX',
'regSDMA1_QUEUE3_SKIP_CNTL', 'regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX',
'regSDMA1_QUEUE4_CONTEXT_STATUS',
'regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX',
'regSDMA1_QUEUE4_CSA_ADDR_HI',
'regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE4_CSA_ADDR_LO',
'regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE4_DOORBELL', 'regSDMA1_QUEUE4_DOORBELL_BASE_IDX',
'regSDMA1_QUEUE4_DOORBELL_LOG',
'regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX',
'regSDMA1_QUEUE4_DOORBELL_OFFSET',
'regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX',
'regSDMA1_QUEUE4_DUMMY_REG', 'regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX',
'regSDMA1_QUEUE4_IB_BASE_HI',
'regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX',
'regSDMA1_QUEUE4_IB_BASE_LO',
'regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE4_IB_CNTL',
'regSDMA1_QUEUE4_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_IB_OFFSET',
'regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE4_IB_RPTR',
'regSDMA1_QUEUE4_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE4_IB_SIZE',
'regSDMA1_QUEUE4_IB_SIZE_BASE_IDX',
'regSDMA1_QUEUE4_IB_SUB_REMAIN',
'regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX',
'regSDMA1_QUEUE4_MIDCMD_CNTL',
'regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX',
'regSDMA1_QUEUE4_MIDCMD_DATA0',
'regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX',
'regSDMA1_QUEUE4_MIDCMD_DATA1', 'regSDMA1_QUEUE4_MIDCMD_DATA10',
'regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX',
'regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX',
'regSDMA1_QUEUE4_MIDCMD_DATA2',
'regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX',
'regSDMA1_QUEUE4_MIDCMD_DATA3',
'regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX',
'regSDMA1_QUEUE4_MIDCMD_DATA4',
'regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX',
'regSDMA1_QUEUE4_MIDCMD_DATA5',
'regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX',
'regSDMA1_QUEUE4_MIDCMD_DATA6',
'regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX',
'regSDMA1_QUEUE4_MIDCMD_DATA7',
'regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX',
'regSDMA1_QUEUE4_MIDCMD_DATA8',
'regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX',
'regSDMA1_QUEUE4_MIDCMD_DATA9',
'regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX',
'regSDMA1_QUEUE4_MINOR_PTR_UPDATE',
'regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA1_QUEUE4_PREEMPT', 'regSDMA1_QUEUE4_PREEMPT_BASE_IDX',
'regSDMA1_QUEUE4_RB_AQL_CNTL',
'regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_RB_BASE',
'regSDMA1_QUEUE4_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE4_RB_BASE_HI',
'regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE4_RB_CNTL',
'regSDMA1_QUEUE4_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_RB_PREEMPT',
'regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE4_RB_RPTR',
'regSDMA1_QUEUE4_RB_RPTR_ADDR_HI',
'regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE4_RB_RPTR_ADDR_LO',
'regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE4_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE4_RB_RPTR_HI',
'regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE4_RB_WPTR',
'regSDMA1_QUEUE4_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE4_RB_WPTR_HI',
'regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX',
'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI',
'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO',
'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE4_SCHEDULE_CNTL',
'regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX',
'regSDMA1_QUEUE4_SKIP_CNTL', 'regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX',
'regSDMA1_QUEUE5_CONTEXT_STATUS',
'regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX',
'regSDMA1_QUEUE5_CSA_ADDR_HI',
'regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE5_CSA_ADDR_LO',
'regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE5_DOORBELL', 'regSDMA1_QUEUE5_DOORBELL_BASE_IDX',
'regSDMA1_QUEUE5_DOORBELL_LOG',
'regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX',
'regSDMA1_QUEUE5_DOORBELL_OFFSET',
'regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX',
'regSDMA1_QUEUE5_DUMMY_REG', 'regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX',
'regSDMA1_QUEUE5_IB_BASE_HI',
'regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX',
'regSDMA1_QUEUE5_IB_BASE_LO',
'regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE5_IB_CNTL',
'regSDMA1_QUEUE5_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_IB_OFFSET',
'regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE5_IB_RPTR',
'regSDMA1_QUEUE5_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE5_IB_SIZE',
'regSDMA1_QUEUE5_IB_SIZE_BASE_IDX',
'regSDMA1_QUEUE5_IB_SUB_REMAIN',
'regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX',
'regSDMA1_QUEUE5_MIDCMD_CNTL',
'regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX',
'regSDMA1_QUEUE5_MIDCMD_DATA0',
'regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX',
'regSDMA1_QUEUE5_MIDCMD_DATA1', 'regSDMA1_QUEUE5_MIDCMD_DATA10',
'regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX',
'regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX',
'regSDMA1_QUEUE5_MIDCMD_DATA2',
'regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX',
'regSDMA1_QUEUE5_MIDCMD_DATA3',
'regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX',
'regSDMA1_QUEUE5_MIDCMD_DATA4',
'regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX',
'regSDMA1_QUEUE5_MIDCMD_DATA5',
'regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX',
'regSDMA1_QUEUE5_MIDCMD_DATA6',
'regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX',
'regSDMA1_QUEUE5_MIDCMD_DATA7',
'regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX',
'regSDMA1_QUEUE5_MIDCMD_DATA8',
'regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX',
'regSDMA1_QUEUE5_MIDCMD_DATA9',
'regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX',
'regSDMA1_QUEUE5_MINOR_PTR_UPDATE',
'regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA1_QUEUE5_PREEMPT', 'regSDMA1_QUEUE5_PREEMPT_BASE_IDX',
'regSDMA1_QUEUE5_RB_AQL_CNTL',
'regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_RB_BASE',
'regSDMA1_QUEUE5_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE5_RB_BASE_HI',
'regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE5_RB_CNTL',
'regSDMA1_QUEUE5_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_RB_PREEMPT',
'regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE5_RB_RPTR',
'regSDMA1_QUEUE5_RB_RPTR_ADDR_HI',
'regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE5_RB_RPTR_ADDR_LO',
'regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE5_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE5_RB_RPTR_HI',
'regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE5_RB_WPTR',
'regSDMA1_QUEUE5_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE5_RB_WPTR_HI',
'regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX',
'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI',
'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO',
'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE5_SCHEDULE_CNTL',
'regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX',
'regSDMA1_QUEUE5_SKIP_CNTL', 'regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX',
'regSDMA1_QUEUE6_CONTEXT_STATUS',
'regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX',
'regSDMA1_QUEUE6_CSA_ADDR_HI',
'regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE6_CSA_ADDR_LO',
'regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE6_DOORBELL', 'regSDMA1_QUEUE6_DOORBELL_BASE_IDX',
'regSDMA1_QUEUE6_DOORBELL_LOG',
'regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX',
'regSDMA1_QUEUE6_DOORBELL_OFFSET',
'regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX',
'regSDMA1_QUEUE6_DUMMY_REG', 'regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX',
'regSDMA1_QUEUE6_IB_BASE_HI',
'regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX',
'regSDMA1_QUEUE6_IB_BASE_LO',
'regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE6_IB_CNTL',
'regSDMA1_QUEUE6_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_IB_OFFSET',
'regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE6_IB_RPTR',
'regSDMA1_QUEUE6_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE6_IB_SIZE',
'regSDMA1_QUEUE6_IB_SIZE_BASE_IDX',
'regSDMA1_QUEUE6_IB_SUB_REMAIN',
'regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX',
'regSDMA1_QUEUE6_MIDCMD_CNTL',
'regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX',
'regSDMA1_QUEUE6_MIDCMD_DATA0',
'regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX',
'regSDMA1_QUEUE6_MIDCMD_DATA1', 'regSDMA1_QUEUE6_MIDCMD_DATA10',
'regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX',
'regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX',
'regSDMA1_QUEUE6_MIDCMD_DATA2',
'regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX',
'regSDMA1_QUEUE6_MIDCMD_DATA3',
'regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX',
'regSDMA1_QUEUE6_MIDCMD_DATA4',
'regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX',
'regSDMA1_QUEUE6_MIDCMD_DATA5',
'regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX',
'regSDMA1_QUEUE6_MIDCMD_DATA6',
'regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX',
'regSDMA1_QUEUE6_MIDCMD_DATA7',
'regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX',
'regSDMA1_QUEUE6_MIDCMD_DATA8',
'regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX',
'regSDMA1_QUEUE6_MIDCMD_DATA9',
'regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX',
'regSDMA1_QUEUE6_MINOR_PTR_UPDATE',
'regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA1_QUEUE6_PREEMPT', 'regSDMA1_QUEUE6_PREEMPT_BASE_IDX',
'regSDMA1_QUEUE6_RB_AQL_CNTL',
'regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_RB_BASE',
'regSDMA1_QUEUE6_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE6_RB_BASE_HI',
'regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE6_RB_CNTL',
'regSDMA1_QUEUE6_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_RB_PREEMPT',
'regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE6_RB_RPTR',
'regSDMA1_QUEUE6_RB_RPTR_ADDR_HI',
'regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE6_RB_RPTR_ADDR_LO',
'regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE6_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE6_RB_RPTR_HI',
'regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE6_RB_WPTR',
'regSDMA1_QUEUE6_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE6_RB_WPTR_HI',
'regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX',
'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI',
'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO',
'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE6_SCHEDULE_CNTL',
'regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX',
'regSDMA1_QUEUE6_SKIP_CNTL', 'regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX',
'regSDMA1_QUEUE7_CONTEXT_STATUS',
'regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX',
'regSDMA1_QUEUE7_CSA_ADDR_HI',
'regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE7_CSA_ADDR_LO',
'regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE7_DOORBELL', 'regSDMA1_QUEUE7_DOORBELL_BASE_IDX',
'regSDMA1_QUEUE7_DOORBELL_LOG',
'regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX',
'regSDMA1_QUEUE7_DOORBELL_OFFSET',
'regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX',
'regSDMA1_QUEUE7_DUMMY_REG', 'regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX',
'regSDMA1_QUEUE7_IB_BASE_HI',
'regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX',
'regSDMA1_QUEUE7_IB_BASE_LO',
'regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE7_IB_CNTL',
'regSDMA1_QUEUE7_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_IB_OFFSET',
'regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE7_IB_RPTR',
'regSDMA1_QUEUE7_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE7_IB_SIZE',
'regSDMA1_QUEUE7_IB_SIZE_BASE_IDX',
'regSDMA1_QUEUE7_IB_SUB_REMAIN',
'regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX',
'regSDMA1_QUEUE7_MIDCMD_CNTL',
'regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX',
'regSDMA1_QUEUE7_MIDCMD_DATA0',
'regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX',
'regSDMA1_QUEUE7_MIDCMD_DATA1', 'regSDMA1_QUEUE7_MIDCMD_DATA10',
'regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX',
'regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX',
'regSDMA1_QUEUE7_MIDCMD_DATA2',
'regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX',
'regSDMA1_QUEUE7_MIDCMD_DATA3',
'regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX',
'regSDMA1_QUEUE7_MIDCMD_DATA4',
'regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX',
'regSDMA1_QUEUE7_MIDCMD_DATA5',
'regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX',
'regSDMA1_QUEUE7_MIDCMD_DATA6',
'regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX',
'regSDMA1_QUEUE7_MIDCMD_DATA7',
'regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX',
'regSDMA1_QUEUE7_MIDCMD_DATA8',
'regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX',
'regSDMA1_QUEUE7_MIDCMD_DATA9',
'regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX',
'regSDMA1_QUEUE7_MINOR_PTR_UPDATE',
'regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX',
'regSDMA1_QUEUE7_PREEMPT', 'regSDMA1_QUEUE7_PREEMPT_BASE_IDX',
'regSDMA1_QUEUE7_RB_AQL_CNTL',
'regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_RB_BASE',
'regSDMA1_QUEUE7_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE7_RB_BASE_HI',
'regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE7_RB_CNTL',
'regSDMA1_QUEUE7_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_RB_PREEMPT',
'regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE7_RB_RPTR',
'regSDMA1_QUEUE7_RB_RPTR_ADDR_HI',
'regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE7_RB_RPTR_ADDR_LO',
'regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE7_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE7_RB_RPTR_HI',
'regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE7_RB_WPTR',
'regSDMA1_QUEUE7_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE7_RB_WPTR_HI',
'regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX',
'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI',
'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO',
'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
'regSDMA1_QUEUE7_SCHEDULE_CNTL',
'regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX',
'regSDMA1_QUEUE7_SKIP_CNTL', 'regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX',
'regSDMA1_QUEUE_RESET_REQ', 'regSDMA1_QUEUE_RESET_REQ_BASE_IDX',
'regSDMA1_QUEUE_STATUS0', 'regSDMA1_QUEUE_STATUS0_BASE_IDX',
'regSDMA1_RB_RPTR_FETCH', 'regSDMA1_RB_RPTR_FETCH_BASE_IDX',
'regSDMA1_RB_RPTR_FETCH_HI', 'regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX',
'regSDMA1_RELAX_ORDERING_LUT',
'regSDMA1_RELAX_ORDERING_LUT_BASE_IDX', 'regSDMA1_RLC_CGCG_CTRL',
'regSDMA1_RLC_CGCG_CTRL_BASE_IDX', 'regSDMA1_SCRATCH_RAM_ADDR',
'regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX', 'regSDMA1_SCRATCH_RAM_DATA',
'regSDMA1_SCRATCH_RAM_DATA_BASE_IDX',
'regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL',
'regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX',
'regSDMA1_STATUS1_REG', 'regSDMA1_STATUS1_REG_BASE_IDX',
'regSDMA1_STATUS2_REG', 'regSDMA1_STATUS2_REG_BASE_IDX',
'regSDMA1_STATUS3_REG', 'regSDMA1_STATUS3_REG_BASE_IDX',
'regSDMA1_STATUS4_REG', 'regSDMA1_STATUS4_REG_BASE_IDX',
'regSDMA1_STATUS5_REG', 'regSDMA1_STATUS5_REG_BASE_IDX',
'regSDMA1_STATUS6_REG', 'regSDMA1_STATUS6_REG_BASE_IDX',
'regSDMA1_STATUS_REG', 'regSDMA1_STATUS_REG_BASE_IDX',
'regSDMA1_TILING_CONFIG', 'regSDMA1_TILING_CONFIG_BASE_IDX',
'regSDMA1_TIMESTAMP_CNTL', 'regSDMA1_TIMESTAMP_CNTL_BASE_IDX',
'regSDMA1_TLBI_GCR_CNTL', 'regSDMA1_TLBI_GCR_CNTL_BASE_IDX',
'regSDMA1_UCODE1_CHECKSUM', 'regSDMA1_UCODE1_CHECKSUM_BASE_IDX',
'regSDMA1_UCODE_ADDR', 'regSDMA1_UCODE_ADDR_BASE_IDX',
'regSDMA1_UCODE_CHECKSUM', 'regSDMA1_UCODE_CHECKSUM_BASE_IDX',
'regSDMA1_UCODE_DATA', 'regSDMA1_UCODE_DATA_BASE_IDX',
'regSDMA1_UCODE_SELFLOAD_CONTROL',
'regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX', 'regSDMA1_UTCL1_CNTL',
'regSDMA1_UTCL1_CNTL_BASE_IDX', 'regSDMA1_UTCL1_INV0',
'regSDMA1_UTCL1_INV0_BASE_IDX', 'regSDMA1_UTCL1_INV1',
'regSDMA1_UTCL1_INV1_BASE_IDX', 'regSDMA1_UTCL1_INV2',
'regSDMA1_UTCL1_INV2_BASE_IDX', 'regSDMA1_UTCL1_PAGE',
'regSDMA1_UTCL1_PAGE_BASE_IDX', 'regSDMA1_UTCL1_RD_STATUS',
'regSDMA1_UTCL1_RD_STATUS_BASE_IDX', 'regSDMA1_UTCL1_RD_XNACK0',
'regSDMA1_UTCL1_RD_XNACK0_BASE_IDX', 'regSDMA1_UTCL1_RD_XNACK1',
'regSDMA1_UTCL1_RD_XNACK1_BASE_IDX', 'regSDMA1_UTCL1_TIMEOUT',
'regSDMA1_UTCL1_TIMEOUT_BASE_IDX', 'regSDMA1_UTCL1_WATERMK',
'regSDMA1_UTCL1_WATERMK_BASE_IDX', 'regSDMA1_UTCL1_WR_STATUS',
'regSDMA1_UTCL1_WR_STATUS_BASE_IDX', 'regSDMA1_UTCL1_WR_XNACK0',
'regSDMA1_UTCL1_WR_XNACK0_BASE_IDX', 'regSDMA1_UTCL1_WR_XNACK1',
'regSDMA1_UTCL1_WR_XNACK1_BASE_IDX', 'regSDMA1_VERSION',
'regSDMA1_VERSION_BASE_IDX', 'regSDMA1_WATCHDOG_CNTL',
'regSDMA1_WATCHDOG_CNTL_BASE_IDX', 'regSE0_CAC_AGGR_GFXCLK_CYCLE',
'regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE0_CAC_AGGR_LOWER',
'regSE0_CAC_AGGR_LOWER_BASE_IDX', 'regSE0_CAC_AGGR_UPPER',
'regSE0_CAC_AGGR_UPPER_BASE_IDX', 'regSE1_CAC_AGGR_GFXCLK_CYCLE',
'regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE1_CAC_AGGR_LOWER',
'regSE1_CAC_AGGR_LOWER_BASE_IDX', 'regSE1_CAC_AGGR_UPPER',
'regSE1_CAC_AGGR_UPPER_BASE_IDX', 'regSE2_CAC_AGGR_GFXCLK_CYCLE',
'regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE2_CAC_AGGR_LOWER',
'regSE2_CAC_AGGR_LOWER_BASE_IDX', 'regSE2_CAC_AGGR_UPPER',
'regSE2_CAC_AGGR_UPPER_BASE_IDX', 'regSE3_CAC_AGGR_GFXCLK_CYCLE',
'regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE3_CAC_AGGR_LOWER',
'regSE3_CAC_AGGR_LOWER_BASE_IDX', 'regSE3_CAC_AGGR_UPPER',
'regSE3_CAC_AGGR_UPPER_BASE_IDX', 'regSE4_CAC_AGGR_GFXCLK_CYCLE',
'regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE4_CAC_AGGR_LOWER',
'regSE4_CAC_AGGR_LOWER_BASE_IDX', 'regSE4_CAC_AGGR_UPPER',
'regSE4_CAC_AGGR_UPPER_BASE_IDX', 'regSE5_CAC_AGGR_GFXCLK_CYCLE',
'regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE5_CAC_AGGR_LOWER',
'regSE5_CAC_AGGR_LOWER_BASE_IDX', 'regSE5_CAC_AGGR_UPPER',
'regSE5_CAC_AGGR_UPPER_BASE_IDX', 'regSEDC_GL1_GL2_OVERRIDES',
'regSEDC_GL1_GL2_OVERRIDES_BASE_IDX', 'regSE_CAC_CTRL_1',
'regSE_CAC_CTRL_1_BASE_IDX', 'regSE_CAC_CTRL_2',
'regSE_CAC_CTRL_2_BASE_IDX', 'regSE_CAC_IND_DATA',
'regSE_CAC_IND_DATA_BASE_IDX', 'regSE_CAC_IND_INDEX',
'regSE_CAC_IND_INDEX_BASE_IDX', 'regSE_CAC_WEIGHT_BCI_0',
'regSE_CAC_WEIGHT_BCI_0_BASE_IDX', 'regSE_CAC_WEIGHT_CB_0',
'regSE_CAC_WEIGHT_CB_0_BASE_IDX', 'regSE_CAC_WEIGHT_CB_1',
'regSE_CAC_WEIGHT_CB_10', 'regSE_CAC_WEIGHT_CB_10_BASE_IDX',
'regSE_CAC_WEIGHT_CB_11', 'regSE_CAC_WEIGHT_CB_11_BASE_IDX',
'regSE_CAC_WEIGHT_CB_1_BASE_IDX', 'regSE_CAC_WEIGHT_CB_2',
'regSE_CAC_WEIGHT_CB_2_BASE_IDX', 'regSE_CAC_WEIGHT_CB_3',
'regSE_CAC_WEIGHT_CB_3_BASE_IDX', 'regSE_CAC_WEIGHT_CB_4',
'regSE_CAC_WEIGHT_CB_4_BASE_IDX', 'regSE_CAC_WEIGHT_CB_5',
'regSE_CAC_WEIGHT_CB_5_BASE_IDX', 'regSE_CAC_WEIGHT_CB_6',
'regSE_CAC_WEIGHT_CB_6_BASE_IDX', 'regSE_CAC_WEIGHT_CB_7',
'regSE_CAC_WEIGHT_CB_7_BASE_IDX', 'regSE_CAC_WEIGHT_CB_8',
'regSE_CAC_WEIGHT_CB_8_BASE_IDX', 'regSE_CAC_WEIGHT_CB_9',
'regSE_CAC_WEIGHT_CB_9_BASE_IDX', 'regSE_CAC_WEIGHT_CU_0',
'regSE_CAC_WEIGHT_CU_0_BASE_IDX', 'regSE_CAC_WEIGHT_DB_0',
'regSE_CAC_WEIGHT_DB_0_BASE_IDX', 'regSE_CAC_WEIGHT_DB_1',
'regSE_CAC_WEIGHT_DB_1_BASE_IDX', 'regSE_CAC_WEIGHT_DB_2',
'regSE_CAC_WEIGHT_DB_2_BASE_IDX', 'regSE_CAC_WEIGHT_DB_3',
'regSE_CAC_WEIGHT_DB_3_BASE_IDX', 'regSE_CAC_WEIGHT_DB_4',
'regSE_CAC_WEIGHT_DB_4_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_0',
'regSE_CAC_WEIGHT_GL1C_0_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_1',
'regSE_CAC_WEIGHT_GL1C_1_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_2',
'regSE_CAC_WEIGHT_GL1C_2_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_0',
'regSE_CAC_WEIGHT_LDS_0_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_1',
'regSE_CAC_WEIGHT_LDS_1_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_2',
'regSE_CAC_WEIGHT_LDS_2_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_3',
'regSE_CAC_WEIGHT_LDS_3_BASE_IDX', 'regSE_CAC_WEIGHT_PA_0',
'regSE_CAC_WEIGHT_PA_0_BASE_IDX', 'regSE_CAC_WEIGHT_PA_1',
'regSE_CAC_WEIGHT_PA_1_BASE_IDX', 'regSE_CAC_WEIGHT_PA_2',
'regSE_CAC_WEIGHT_PA_2_BASE_IDX', 'regSE_CAC_WEIGHT_PA_3',
'regSE_CAC_WEIGHT_PA_3_BASE_IDX', 'regSE_CAC_WEIGHT_PC_0',
'regSE_CAC_WEIGHT_PC_0_BASE_IDX', 'regSE_CAC_WEIGHT_RMI_0',
'regSE_CAC_WEIGHT_RMI_0_BASE_IDX', 'regSE_CAC_WEIGHT_RMI_1',
'regSE_CAC_WEIGHT_RMI_1_BASE_IDX', 'regSE_CAC_WEIGHT_SC_0',
'regSE_CAC_WEIGHT_SC_0_BASE_IDX', 'regSE_CAC_WEIGHT_SC_1',
'regSE_CAC_WEIGHT_SC_1_BASE_IDX', 'regSE_CAC_WEIGHT_SC_2',
'regSE_CAC_WEIGHT_SC_2_BASE_IDX', 'regSE_CAC_WEIGHT_SC_3',
'regSE_CAC_WEIGHT_SC_3_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_0',
'regSE_CAC_WEIGHT_SPI_0_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_1',
'regSE_CAC_WEIGHT_SPI_1_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_2',
'regSE_CAC_WEIGHT_SPI_2_BASE_IDX', 'regSE_CAC_WEIGHT_SP_0',
'regSE_CAC_WEIGHT_SP_0_BASE_IDX', 'regSE_CAC_WEIGHT_SP_1',
'regSE_CAC_WEIGHT_SP_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQC_0',
'regSE_CAC_WEIGHT_SQC_0_BASE_IDX', 'regSE_CAC_WEIGHT_SQC_1',
'regSE_CAC_WEIGHT_SQC_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_0',
'regSE_CAC_WEIGHT_SQ_0_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_1',
'regSE_CAC_WEIGHT_SQ_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_2',
'regSE_CAC_WEIGHT_SQ_2_BASE_IDX', 'regSE_CAC_WEIGHT_SXRB_0',
'regSE_CAC_WEIGHT_SXRB_0_BASE_IDX', 'regSE_CAC_WEIGHT_SX_0',
'regSE_CAC_WEIGHT_SX_0_BASE_IDX', 'regSE_CAC_WEIGHT_TA_0',
'regSE_CAC_WEIGHT_TA_0_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_0',
'regSE_CAC_WEIGHT_TCP_0_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_1',
'regSE_CAC_WEIGHT_TCP_1_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_2',
'regSE_CAC_WEIGHT_TCP_2_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_3',
'regSE_CAC_WEIGHT_TCP_3_BASE_IDX', 'regSE_CAC_WEIGHT_TD_0',
'regSE_CAC_WEIGHT_TD_0_BASE_IDX', 'regSE_CAC_WEIGHT_TD_1',
'regSE_CAC_WEIGHT_TD_1_BASE_IDX', 'regSE_CAC_WEIGHT_TD_2',
'regSE_CAC_WEIGHT_TD_2_BASE_IDX', 'regSE_CAC_WEIGHT_TD_3',
'regSE_CAC_WEIGHT_TD_3_BASE_IDX', 'regSE_CAC_WEIGHT_TD_4',
'regSE_CAC_WEIGHT_TD_4_BASE_IDX', 'regSE_CAC_WEIGHT_TD_5',
'regSE_CAC_WEIGHT_TD_5_BASE_IDX', 'regSE_CAC_WEIGHT_UTCL1_0',
'regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX',
'regSE_CAC_WINDOW_AGGR_VALUE',
'regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX',
'regSE_CAC_WINDOW_GFXCLK_CYCLE',
'regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX', 'regSH_MEM_BASES',
'regSH_MEM_BASES_BASE_IDX', 'regSH_MEM_CONFIG',
'regSH_MEM_CONFIG_BASE_IDX', 'regSH_RESERVED_REG0',
'regSH_RESERVED_REG0_BASE_IDX', 'regSH_RESERVED_REG1',
'regSH_RESERVED_REG1_BASE_IDX', 'regSMU_RLC_RESPONSE',
'regSMU_RLC_RESPONSE_BASE_IDX', 'regSPI_ARB_CNTL_0',
'regSPI_ARB_CNTL_0_BASE_IDX', 'regSPI_ARB_CYCLES_0',
'regSPI_ARB_CYCLES_0_BASE_IDX', 'regSPI_ARB_CYCLES_1',
'regSPI_ARB_CYCLES_1_BASE_IDX', 'regSPI_ARB_PRIORITY',
'regSPI_ARB_PRIORITY_BASE_IDX', 'regSPI_ATTRIBUTE_RING_BASE',
'regSPI_ATTRIBUTE_RING_BASE_BASE_IDX',
'regSPI_ATTRIBUTE_RING_SIZE',
'regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX', 'regSPI_BARYC_CNTL',
'regSPI_BARYC_CNTL_BASE_IDX', 'regSPI_COMPUTE_QUEUE_RESET',
'regSPI_COMPUTE_QUEUE_RESET_BASE_IDX',
'regSPI_COMPUTE_WF_CTX_SAVE',
'regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX',
'regSPI_COMPUTE_WF_CTX_SAVE_STATUS',
'regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX',
'regSPI_CONFIG_CNTL', 'regSPI_CONFIG_CNTL_1',
'regSPI_CONFIG_CNTL_1_BASE_IDX', 'regSPI_CONFIG_CNTL_2',
'regSPI_CONFIG_CNTL_2_BASE_IDX', 'regSPI_CONFIG_CNTL_BASE_IDX',
'regSPI_CONFIG_PS_CU_EN', 'regSPI_CONFIG_PS_CU_EN_BASE_IDX',
'regSPI_CSQ_WF_ACTIVE_COUNT_0',
'regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX',
'regSPI_CSQ_WF_ACTIVE_COUNT_1',
'regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX',
'regSPI_CSQ_WF_ACTIVE_COUNT_2',
'regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX',
'regSPI_CSQ_WF_ACTIVE_COUNT_3',
'regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX',
'regSPI_CSQ_WF_ACTIVE_STATUS',
'regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX', 'regSPI_DSM_CNTL',
'regSPI_DSM_CNTL2', 'regSPI_DSM_CNTL2_BASE_IDX',
'regSPI_DSM_CNTL_BASE_IDX', 'regSPI_EDC_CNT',
'regSPI_EDC_CNT_BASE_IDX', 'regSPI_EXP_THROTTLE_CTRL',
'regSPI_EXP_THROTTLE_CTRL_BASE_IDX', 'regSPI_FEATURE_CTRL',
'regSPI_FEATURE_CTRL_BASE_IDX', 'regSPI_GDBG_PER_VMID_CNTL',
'regSPI_GDBG_PER_VMID_CNTL_BASE_IDX', 'regSPI_GDBG_TRAP_CONFIG',
'regSPI_GDBG_TRAP_CONFIG_BASE_IDX', 'regSPI_GDBG_WAVE_CNTL',
'regSPI_GDBG_WAVE_CNTL3', 'regSPI_GDBG_WAVE_CNTL3_BASE_IDX',
'regSPI_GDBG_WAVE_CNTL_BASE_IDX', 'regSPI_GDS_CREDITS',
'regSPI_GDS_CREDITS_BASE_IDX', 'regSPI_GFX_CNTL',
'regSPI_GFX_CNTL_BASE_IDX', 'regSPI_GFX_SCRATCH_BASE_HI',
'regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX',
'regSPI_GFX_SCRATCH_BASE_LO',
'regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX', 'regSPI_GS_THROTTLE_CNTL1',
'regSPI_GS_THROTTLE_CNTL1_BASE_IDX', 'regSPI_GS_THROTTLE_CNTL2',
'regSPI_GS_THROTTLE_CNTL2_BASE_IDX', 'regSPI_INTERP_CONTROL_0',
'regSPI_INTERP_CONTROL_0_BASE_IDX', 'regSPI_LB_CTR_CTRL',
'regSPI_LB_CTR_CTRL_BASE_IDX', 'regSPI_LB_DATA_REG',
'regSPI_LB_DATA_REG_BASE_IDX', 'regSPI_LB_DATA_WAVES',
'regSPI_LB_DATA_WAVES_BASE_IDX', 'regSPI_LB_WGP_MASK',
'regSPI_LB_WGP_MASK_BASE_IDX', 'regSPI_P0_TRAP_SCREEN_GPR_MIN',
'regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX',
'regSPI_P0_TRAP_SCREEN_PSBA_HI',
'regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX',
'regSPI_P0_TRAP_SCREEN_PSBA_LO',
'regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX',
'regSPI_P0_TRAP_SCREEN_PSMA_HI',
'regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX',
'regSPI_P0_TRAP_SCREEN_PSMA_LO',
'regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX',
'regSPI_P1_TRAP_SCREEN_GPR_MIN',
'regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX',
'regSPI_P1_TRAP_SCREEN_PSBA_HI',
'regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX',
'regSPI_P1_TRAP_SCREEN_PSBA_LO',
'regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX',
'regSPI_P1_TRAP_SCREEN_PSMA_HI',
'regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX',
'regSPI_P1_TRAP_SCREEN_PSMA_LO',
'regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX',
'regSPI_PERFCOUNTER0_HI', 'regSPI_PERFCOUNTER0_HI_BASE_IDX',
'regSPI_PERFCOUNTER0_LO', 'regSPI_PERFCOUNTER0_LO_BASE_IDX',
'regSPI_PERFCOUNTER0_SELECT', 'regSPI_PERFCOUNTER0_SELECT1',
'regSPI_PERFCOUNTER0_SELECT1_BASE_IDX',
'regSPI_PERFCOUNTER0_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER1_HI',
'regSPI_PERFCOUNTER1_HI_BASE_IDX', 'regSPI_PERFCOUNTER1_LO',
'regSPI_PERFCOUNTER1_LO_BASE_IDX', 'regSPI_PERFCOUNTER1_SELECT',
'regSPI_PERFCOUNTER1_SELECT1',
'regSPI_PERFCOUNTER1_SELECT1_BASE_IDX',
'regSPI_PERFCOUNTER1_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER2_HI',
'regSPI_PERFCOUNTER2_HI_BASE_IDX', 'regSPI_PERFCOUNTER2_LO',
'regSPI_PERFCOUNTER2_LO_BASE_IDX', 'regSPI_PERFCOUNTER2_SELECT',
'regSPI_PERFCOUNTER2_SELECT1',
'regSPI_PERFCOUNTER2_SELECT1_BASE_IDX',
'regSPI_PERFCOUNTER2_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER3_HI',
'regSPI_PERFCOUNTER3_HI_BASE_IDX', 'regSPI_PERFCOUNTER3_LO',
'regSPI_PERFCOUNTER3_LO_BASE_IDX', 'regSPI_PERFCOUNTER3_SELECT',
'regSPI_PERFCOUNTER3_SELECT1',
'regSPI_PERFCOUNTER3_SELECT1_BASE_IDX',
'regSPI_PERFCOUNTER3_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER4_HI',
'regSPI_PERFCOUNTER4_HI_BASE_IDX', 'regSPI_PERFCOUNTER4_LO',
'regSPI_PERFCOUNTER4_LO_BASE_IDX', 'regSPI_PERFCOUNTER4_SELECT',
'regSPI_PERFCOUNTER4_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER5_HI',
'regSPI_PERFCOUNTER5_HI_BASE_IDX', 'regSPI_PERFCOUNTER5_LO',
'regSPI_PERFCOUNTER5_LO_BASE_IDX', 'regSPI_PERFCOUNTER5_SELECT',
'regSPI_PERFCOUNTER5_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER_BINS',
'regSPI_PERFCOUNTER_BINS_BASE_IDX',
'regSPI_PG_ENABLE_STATIC_WGP_MASK',
'regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX', 'regSPI_PQEV_CTRL',
'regSPI_PQEV_CTRL_BASE_IDX', 'regSPI_PS_INPUT_ADDR',
'regSPI_PS_INPUT_ADDR_BASE_IDX', 'regSPI_PS_INPUT_CNTL_0',
'regSPI_PS_INPUT_CNTL_0_BASE_IDX', 'regSPI_PS_INPUT_CNTL_1',
'regSPI_PS_INPUT_CNTL_10', 'regSPI_PS_INPUT_CNTL_10_BASE_IDX',
'regSPI_PS_INPUT_CNTL_11', 'regSPI_PS_INPUT_CNTL_11_BASE_IDX',
'regSPI_PS_INPUT_CNTL_12', 'regSPI_PS_INPUT_CNTL_12_BASE_IDX',
'regSPI_PS_INPUT_CNTL_13', 'regSPI_PS_INPUT_CNTL_13_BASE_IDX',
'regSPI_PS_INPUT_CNTL_14', 'regSPI_PS_INPUT_CNTL_14_BASE_IDX',
'regSPI_PS_INPUT_CNTL_15', 'regSPI_PS_INPUT_CNTL_15_BASE_IDX',
'regSPI_PS_INPUT_CNTL_16', 'regSPI_PS_INPUT_CNTL_16_BASE_IDX',
'regSPI_PS_INPUT_CNTL_17', 'regSPI_PS_INPUT_CNTL_17_BASE_IDX',
'regSPI_PS_INPUT_CNTL_18', 'regSPI_PS_INPUT_CNTL_18_BASE_IDX',
'regSPI_PS_INPUT_CNTL_19', 'regSPI_PS_INPUT_CNTL_19_BASE_IDX',
'regSPI_PS_INPUT_CNTL_1_BASE_IDX', 'regSPI_PS_INPUT_CNTL_2',
'regSPI_PS_INPUT_CNTL_20', 'regSPI_PS_INPUT_CNTL_20_BASE_IDX',
'regSPI_PS_INPUT_CNTL_21', 'regSPI_PS_INPUT_CNTL_21_BASE_IDX',
'regSPI_PS_INPUT_CNTL_22', 'regSPI_PS_INPUT_CNTL_22_BASE_IDX',
'regSPI_PS_INPUT_CNTL_23', 'regSPI_PS_INPUT_CNTL_23_BASE_IDX',
'regSPI_PS_INPUT_CNTL_24', 'regSPI_PS_INPUT_CNTL_24_BASE_IDX',
'regSPI_PS_INPUT_CNTL_25', 'regSPI_PS_INPUT_CNTL_25_BASE_IDX',
'regSPI_PS_INPUT_CNTL_26', 'regSPI_PS_INPUT_CNTL_26_BASE_IDX',
'regSPI_PS_INPUT_CNTL_27', 'regSPI_PS_INPUT_CNTL_27_BASE_IDX',
'regSPI_PS_INPUT_CNTL_28', 'regSPI_PS_INPUT_CNTL_28_BASE_IDX',
'regSPI_PS_INPUT_CNTL_29', 'regSPI_PS_INPUT_CNTL_29_BASE_IDX',
'regSPI_PS_INPUT_CNTL_2_BASE_IDX', 'regSPI_PS_INPUT_CNTL_3',
'regSPI_PS_INPUT_CNTL_30', 'regSPI_PS_INPUT_CNTL_30_BASE_IDX',
'regSPI_PS_INPUT_CNTL_31', 'regSPI_PS_INPUT_CNTL_31_BASE_IDX',
'regSPI_PS_INPUT_CNTL_3_BASE_IDX', 'regSPI_PS_INPUT_CNTL_4',
'regSPI_PS_INPUT_CNTL_4_BASE_IDX', 'regSPI_PS_INPUT_CNTL_5',
'regSPI_PS_INPUT_CNTL_5_BASE_IDX', 'regSPI_PS_INPUT_CNTL_6',
'regSPI_PS_INPUT_CNTL_6_BASE_IDX', 'regSPI_PS_INPUT_CNTL_7',
'regSPI_PS_INPUT_CNTL_7_BASE_IDX', 'regSPI_PS_INPUT_CNTL_8',
'regSPI_PS_INPUT_CNTL_8_BASE_IDX', 'regSPI_PS_INPUT_CNTL_9',
'regSPI_PS_INPUT_CNTL_9_BASE_IDX', 'regSPI_PS_INPUT_ENA',
'regSPI_PS_INPUT_ENA_BASE_IDX', 'regSPI_PS_IN_CONTROL',
'regSPI_PS_IN_CONTROL_BASE_IDX', 'regSPI_PS_MAX_WAVE_ID',
'regSPI_PS_MAX_WAVE_ID_BASE_IDX', 'regSPI_RESOURCE_RESERVE_CU_0',
'regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_1', 'regSPI_RESOURCE_RESERVE_CU_10',
'regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_11',
'regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_12',
'regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_13',
'regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_14',
'regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_15',
'regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_2',
'regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_3',
'regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_4',
'regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_5',
'regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_6',
'regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_7',
'regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_8',
'regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX',
'regSPI_RESOURCE_RESERVE_CU_9',
'regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_0',
'regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_1',
'regSPI_RESOURCE_RESERVE_EN_CU_10',
'regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_11',
'regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_12',
'regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_13',
'regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_14',
'regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_15',
'regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_2',
'regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_3',
'regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_4',
'regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_5',
'regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_6',
'regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_7',
'regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_8',
'regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX',
'regSPI_RESOURCE_RESERVE_EN_CU_9',
'regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX',
'regSPI_SHADER_COL_FORMAT', 'regSPI_SHADER_COL_FORMAT_BASE_IDX',
'regSPI_SHADER_GS_MESHLET_DIM',
'regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX',
'regSPI_SHADER_GS_MESHLET_EXP_ALLOC',
'regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX',
'regSPI_SHADER_IDX_FORMAT', 'regSPI_SHADER_IDX_FORMAT_BASE_IDX',
'regSPI_SHADER_PGM_CHKSUM_GS',
'regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX',
'regSPI_SHADER_PGM_CHKSUM_HS',
'regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX',
'regSPI_SHADER_PGM_CHKSUM_PS',
'regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX', 'regSPI_SHADER_PGM_HI_ES',
'regSPI_SHADER_PGM_HI_ES_BASE_IDX', 'regSPI_SHADER_PGM_HI_ES_GS',
'regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX', 'regSPI_SHADER_PGM_HI_GS',
'regSPI_SHADER_PGM_HI_GS_BASE_IDX', 'regSPI_SHADER_PGM_HI_HS',
'regSPI_SHADER_PGM_HI_HS_BASE_IDX', 'regSPI_SHADER_PGM_HI_LS',
'regSPI_SHADER_PGM_HI_LS_BASE_IDX', 'regSPI_SHADER_PGM_HI_LS_HS',
'regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX', 'regSPI_SHADER_PGM_HI_PS',
'regSPI_SHADER_PGM_HI_PS_BASE_IDX', 'regSPI_SHADER_PGM_LO_ES',
'regSPI_SHADER_PGM_LO_ES_BASE_IDX', 'regSPI_SHADER_PGM_LO_ES_GS',
'regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX', 'regSPI_SHADER_PGM_LO_GS',
'regSPI_SHADER_PGM_LO_GS_BASE_IDX', 'regSPI_SHADER_PGM_LO_HS',
'regSPI_SHADER_PGM_LO_HS_BASE_IDX', 'regSPI_SHADER_PGM_LO_LS',
'regSPI_SHADER_PGM_LO_LS_BASE_IDX', 'regSPI_SHADER_PGM_LO_LS_HS',
'regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX', 'regSPI_SHADER_PGM_LO_PS',
'regSPI_SHADER_PGM_LO_PS_BASE_IDX', 'regSPI_SHADER_PGM_RSRC1_GS',
'regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX',
'regSPI_SHADER_PGM_RSRC1_HS',
'regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX',
'regSPI_SHADER_PGM_RSRC1_PS',
'regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX',
'regSPI_SHADER_PGM_RSRC2_GS',
'regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX',
'regSPI_SHADER_PGM_RSRC2_HS',
'regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX',
'regSPI_SHADER_PGM_RSRC2_PS',
'regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX',
'regSPI_SHADER_PGM_RSRC3_GS',
'regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX',
'regSPI_SHADER_PGM_RSRC3_HS',
'regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX',
'regSPI_SHADER_PGM_RSRC3_PS',
'regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX',
'regSPI_SHADER_PGM_RSRC4_GS',
'regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX',
'regSPI_SHADER_PGM_RSRC4_HS',
'regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX',
'regSPI_SHADER_PGM_RSRC4_PS',
'regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX', 'regSPI_SHADER_POS_FORMAT',
'regSPI_SHADER_POS_FORMAT_BASE_IDX',
'regSPI_SHADER_REQ_CTRL_ESGS',
'regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX',
'regSPI_SHADER_REQ_CTRL_LSHS',
'regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX',
'regSPI_SHADER_REQ_CTRL_PS', 'regSPI_SHADER_REQ_CTRL_PS_BASE_IDX',
'regSPI_SHADER_RSRC_LIMIT_CTRL',
'regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX',
'regSPI_SHADER_USER_ACCUM_ESGS_0',
'regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX',
'regSPI_SHADER_USER_ACCUM_ESGS_1',
'regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX',
'regSPI_SHADER_USER_ACCUM_ESGS_2',
'regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX',
'regSPI_SHADER_USER_ACCUM_ESGS_3',
'regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX',
'regSPI_SHADER_USER_ACCUM_LSHS_0',
'regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX',
'regSPI_SHADER_USER_ACCUM_LSHS_1',
'regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX',
'regSPI_SHADER_USER_ACCUM_LSHS_2',
'regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX',
'regSPI_SHADER_USER_ACCUM_LSHS_3',
'regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX',
'regSPI_SHADER_USER_ACCUM_PS_0',
'regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX',
'regSPI_SHADER_USER_ACCUM_PS_1',
'regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX',
'regSPI_SHADER_USER_ACCUM_PS_2',
'regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX',
'regSPI_SHADER_USER_ACCUM_PS_3',
'regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX',
'regSPI_SHADER_USER_DATA_ADDR_HI_GS',
'regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX',
'regSPI_SHADER_USER_DATA_ADDR_HI_HS',
'regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX',
'regSPI_SHADER_USER_DATA_ADDR_LO_GS',
'regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX',
'regSPI_SHADER_USER_DATA_ADDR_LO_HS',
'regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_0',
'regSPI_SHADER_USER_DATA_GS_0_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_1', 'regSPI_SHADER_USER_DATA_GS_10',
'regSPI_SHADER_USER_DATA_GS_10_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_11',
'regSPI_SHADER_USER_DATA_GS_11_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_12',
'regSPI_SHADER_USER_DATA_GS_12_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_13',
'regSPI_SHADER_USER_DATA_GS_13_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_14',
'regSPI_SHADER_USER_DATA_GS_14_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_15',
'regSPI_SHADER_USER_DATA_GS_15_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_16',
'regSPI_SHADER_USER_DATA_GS_16_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_17',
'regSPI_SHADER_USER_DATA_GS_17_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_18',
'regSPI_SHADER_USER_DATA_GS_18_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_19',
'regSPI_SHADER_USER_DATA_GS_19_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_1_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_2', 'regSPI_SHADER_USER_DATA_GS_20',
'regSPI_SHADER_USER_DATA_GS_20_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_21',
'regSPI_SHADER_USER_DATA_GS_21_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_22',
'regSPI_SHADER_USER_DATA_GS_22_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_23',
'regSPI_SHADER_USER_DATA_GS_23_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_24',
'regSPI_SHADER_USER_DATA_GS_24_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_25',
'regSPI_SHADER_USER_DATA_GS_25_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_26',
'regSPI_SHADER_USER_DATA_GS_26_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_27',
'regSPI_SHADER_USER_DATA_GS_27_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_28',
'regSPI_SHADER_USER_DATA_GS_28_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_29',
'regSPI_SHADER_USER_DATA_GS_29_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_2_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_3', 'regSPI_SHADER_USER_DATA_GS_30',
'regSPI_SHADER_USER_DATA_GS_30_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_31',
'regSPI_SHADER_USER_DATA_GS_31_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_3_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_4',
'regSPI_SHADER_USER_DATA_GS_4_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_5',
'regSPI_SHADER_USER_DATA_GS_5_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_6',
'regSPI_SHADER_USER_DATA_GS_6_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_7',
'regSPI_SHADER_USER_DATA_GS_7_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_8',
'regSPI_SHADER_USER_DATA_GS_8_BASE_IDX',
'regSPI_SHADER_USER_DATA_GS_9',
'regSPI_SHADER_USER_DATA_GS_9_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_0',
'regSPI_SHADER_USER_DATA_HS_0_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_1', 'regSPI_SHADER_USER_DATA_HS_10',
'regSPI_SHADER_USER_DATA_HS_10_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_11',
'regSPI_SHADER_USER_DATA_HS_11_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_12',
'regSPI_SHADER_USER_DATA_HS_12_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_13',
'regSPI_SHADER_USER_DATA_HS_13_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_14',
'regSPI_SHADER_USER_DATA_HS_14_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_15',
'regSPI_SHADER_USER_DATA_HS_15_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_16',
'regSPI_SHADER_USER_DATA_HS_16_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_17',
'regSPI_SHADER_USER_DATA_HS_17_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_18',
'regSPI_SHADER_USER_DATA_HS_18_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_19',
'regSPI_SHADER_USER_DATA_HS_19_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_1_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_2', 'regSPI_SHADER_USER_DATA_HS_20',
'regSPI_SHADER_USER_DATA_HS_20_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_21',
'regSPI_SHADER_USER_DATA_HS_21_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_22',
'regSPI_SHADER_USER_DATA_HS_22_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_23',
'regSPI_SHADER_USER_DATA_HS_23_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_24',
'regSPI_SHADER_USER_DATA_HS_24_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_25',
'regSPI_SHADER_USER_DATA_HS_25_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_26',
'regSPI_SHADER_USER_DATA_HS_26_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_27',
'regSPI_SHADER_USER_DATA_HS_27_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_28',
'regSPI_SHADER_USER_DATA_HS_28_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_29',
'regSPI_SHADER_USER_DATA_HS_29_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_2_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_3', 'regSPI_SHADER_USER_DATA_HS_30',
'regSPI_SHADER_USER_DATA_HS_30_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_31',
'regSPI_SHADER_USER_DATA_HS_31_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_3_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_4',
'regSPI_SHADER_USER_DATA_HS_4_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_5',
'regSPI_SHADER_USER_DATA_HS_5_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_6',
'regSPI_SHADER_USER_DATA_HS_6_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_7',
'regSPI_SHADER_USER_DATA_HS_7_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_8',
'regSPI_SHADER_USER_DATA_HS_8_BASE_IDX',
'regSPI_SHADER_USER_DATA_HS_9',
'regSPI_SHADER_USER_DATA_HS_9_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_0',
'regSPI_SHADER_USER_DATA_PS_0_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_1', 'regSPI_SHADER_USER_DATA_PS_10',
'regSPI_SHADER_USER_DATA_PS_10_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_11',
'regSPI_SHADER_USER_DATA_PS_11_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_12',
'regSPI_SHADER_USER_DATA_PS_12_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_13',
'regSPI_SHADER_USER_DATA_PS_13_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_14',
'regSPI_SHADER_USER_DATA_PS_14_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_15',
'regSPI_SHADER_USER_DATA_PS_15_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_16',
'regSPI_SHADER_USER_DATA_PS_16_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_17',
'regSPI_SHADER_USER_DATA_PS_17_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_18',
'regSPI_SHADER_USER_DATA_PS_18_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_19',
'regSPI_SHADER_USER_DATA_PS_19_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_1_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_2', 'regSPI_SHADER_USER_DATA_PS_20',
'regSPI_SHADER_USER_DATA_PS_20_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_21',
'regSPI_SHADER_USER_DATA_PS_21_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_22',
'regSPI_SHADER_USER_DATA_PS_22_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_23',
'regSPI_SHADER_USER_DATA_PS_23_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_24',
'regSPI_SHADER_USER_DATA_PS_24_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_25',
'regSPI_SHADER_USER_DATA_PS_25_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_26',
'regSPI_SHADER_USER_DATA_PS_26_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_27',
'regSPI_SHADER_USER_DATA_PS_27_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_28',
'regSPI_SHADER_USER_DATA_PS_28_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_29',
'regSPI_SHADER_USER_DATA_PS_29_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_2_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_3', 'regSPI_SHADER_USER_DATA_PS_30',
'regSPI_SHADER_USER_DATA_PS_30_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_31',
'regSPI_SHADER_USER_DATA_PS_31_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_3_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_4',
'regSPI_SHADER_USER_DATA_PS_4_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_5',
'regSPI_SHADER_USER_DATA_PS_5_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_6',
'regSPI_SHADER_USER_DATA_PS_6_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_7',
'regSPI_SHADER_USER_DATA_PS_7_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_8',
'regSPI_SHADER_USER_DATA_PS_8_BASE_IDX',
'regSPI_SHADER_USER_DATA_PS_9',
'regSPI_SHADER_USER_DATA_PS_9_BASE_IDX', 'regSPI_SHADER_Z_FORMAT',
'regSPI_SHADER_Z_FORMAT_BASE_IDX',
'regSPI_SX_EXPORT_BUFFER_SIZES',
'regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX',
'regSPI_SX_SCOREBOARD_BUFFER_SIZES',
'regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX',
'regSPI_TMPRING_SIZE', 'regSPI_TMPRING_SIZE_BASE_IDX',
'regSPI_USER_ACCUM_VMID_CNTL',
'regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX', 'regSPI_VS_OUT_CONFIG',
'regSPI_VS_OUT_CONFIG_BASE_IDX', 'regSPI_WAVE_LIMIT_CNTL',
'regSPI_WAVE_LIMIT_CNTL_BASE_IDX', 'regSPI_WCL_PIPE_PERCENT_CS0',
'regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX',
'regSPI_WCL_PIPE_PERCENT_CS1',
'regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX',
'regSPI_WCL_PIPE_PERCENT_CS2',
'regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX',
'regSPI_WCL_PIPE_PERCENT_CS3',
'regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX',
'regSPI_WCL_PIPE_PERCENT_CS4',
'regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX',
'regSPI_WCL_PIPE_PERCENT_CS5',
'regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX',
'regSPI_WCL_PIPE_PERCENT_CS6',
'regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX',
'regSPI_WCL_PIPE_PERCENT_CS7',
'regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX',
'regSPI_WCL_PIPE_PERCENT_GFX',
'regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX',
'regSPI_WCL_PIPE_PERCENT_HP3D',
'regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX',
'regSPI_WF_LIFETIME_CNTL', 'regSPI_WF_LIFETIME_CNTL_BASE_IDX',
'regSPI_WF_LIFETIME_LIMIT_0',
'regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX',
'regSPI_WF_LIFETIME_LIMIT_1',
'regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX',
'regSPI_WF_LIFETIME_LIMIT_2',
'regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX',
'regSPI_WF_LIFETIME_LIMIT_3',
'regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX',
'regSPI_WF_LIFETIME_LIMIT_4',
'regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX',
'regSPI_WF_LIFETIME_LIMIT_5',
'regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_0',
'regSPI_WF_LIFETIME_STATUS_0_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_11',
'regSPI_WF_LIFETIME_STATUS_11_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_13',
'regSPI_WF_LIFETIME_STATUS_13_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_14',
'regSPI_WF_LIFETIME_STATUS_14_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_15',
'regSPI_WF_LIFETIME_STATUS_15_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_16',
'regSPI_WF_LIFETIME_STATUS_16_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_17',
'regSPI_WF_LIFETIME_STATUS_17_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_18',
'regSPI_WF_LIFETIME_STATUS_18_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_19',
'regSPI_WF_LIFETIME_STATUS_19_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_2', 'regSPI_WF_LIFETIME_STATUS_20',
'regSPI_WF_LIFETIME_STATUS_20_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_21',
'regSPI_WF_LIFETIME_STATUS_21_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_2_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_4',
'regSPI_WF_LIFETIME_STATUS_4_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_6',
'regSPI_WF_LIFETIME_STATUS_6_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_7',
'regSPI_WF_LIFETIME_STATUS_7_BASE_IDX',
'regSPI_WF_LIFETIME_STATUS_9',
'regSPI_WF_LIFETIME_STATUS_9_BASE_IDX', 'regSP_CONFIG',
'regSP_CONFIG_BASE_IDX', 'regSQC_CACHES',
'regSQC_CACHES_BASE_IDX', 'regSQC_CONFIG',
'regSQC_CONFIG_BASE_IDX', 'regSQG_CONFIG',
'regSQG_CONFIG_BASE_IDX', 'regSQG_GL1H_STATUS',
'regSQG_GL1H_STATUS_BASE_IDX', 'regSQG_PERFCOUNTER0_HI',
'regSQG_PERFCOUNTER0_HI_BASE_IDX', 'regSQG_PERFCOUNTER0_LO',
'regSQG_PERFCOUNTER0_LO_BASE_IDX', 'regSQG_PERFCOUNTER0_SELECT',
'regSQG_PERFCOUNTER0_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER1_HI',
'regSQG_PERFCOUNTER1_HI_BASE_IDX', 'regSQG_PERFCOUNTER1_LO',
'regSQG_PERFCOUNTER1_LO_BASE_IDX', 'regSQG_PERFCOUNTER1_SELECT',
'regSQG_PERFCOUNTER1_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER2_HI',
'regSQG_PERFCOUNTER2_HI_BASE_IDX', 'regSQG_PERFCOUNTER2_LO',
'regSQG_PERFCOUNTER2_LO_BASE_IDX', 'regSQG_PERFCOUNTER2_SELECT',
'regSQG_PERFCOUNTER2_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER3_HI',
'regSQG_PERFCOUNTER3_HI_BASE_IDX', 'regSQG_PERFCOUNTER3_LO',
'regSQG_PERFCOUNTER3_LO_BASE_IDX', 'regSQG_PERFCOUNTER3_SELECT',
'regSQG_PERFCOUNTER3_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER4_HI',
'regSQG_PERFCOUNTER4_HI_BASE_IDX', 'regSQG_PERFCOUNTER4_LO',
'regSQG_PERFCOUNTER4_LO_BASE_IDX', 'regSQG_PERFCOUNTER4_SELECT',
'regSQG_PERFCOUNTER4_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER5_HI',
'regSQG_PERFCOUNTER5_HI_BASE_IDX', 'regSQG_PERFCOUNTER5_LO',
'regSQG_PERFCOUNTER5_LO_BASE_IDX', 'regSQG_PERFCOUNTER5_SELECT',
'regSQG_PERFCOUNTER5_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER6_HI',
'regSQG_PERFCOUNTER6_HI_BASE_IDX', 'regSQG_PERFCOUNTER6_LO',
'regSQG_PERFCOUNTER6_LO_BASE_IDX', 'regSQG_PERFCOUNTER6_SELECT',
'regSQG_PERFCOUNTER6_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER7_HI',
'regSQG_PERFCOUNTER7_HI_BASE_IDX', 'regSQG_PERFCOUNTER7_LO',
'regSQG_PERFCOUNTER7_LO_BASE_IDX', 'regSQG_PERFCOUNTER7_SELECT',
'regSQG_PERFCOUNTER7_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER_CTRL',
'regSQG_PERFCOUNTER_CTRL2', 'regSQG_PERFCOUNTER_CTRL2_BASE_IDX',
'regSQG_PERFCOUNTER_CTRL_BASE_IDX', 'regSQG_PERF_SAMPLE_FINISH',
'regSQG_PERF_SAMPLE_FINISH_BASE_IDX', 'regSQG_STATUS',
'regSQG_STATUS_BASE_IDX', 'regSQ_ALU_CLK_CTRL',
'regSQ_ALU_CLK_CTRL_BASE_IDX', 'regSQ_ARB_CONFIG',
'regSQ_ARB_CONFIG_BASE_IDX', 'regSQ_CMD', 'regSQ_CMD_BASE_IDX',
'regSQ_CONFIG', 'regSQ_CONFIG_BASE_IDX', 'regSQ_DEBUG',
'regSQ_DEBUG_BASE_IDX', 'regSQ_DEBUG_HOST_TRAP_STATUS',
'regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX', 'regSQ_DEBUG_STS_GLOBAL',
'regSQ_DEBUG_STS_GLOBAL2', 'regSQ_DEBUG_STS_GLOBAL2_BASE_IDX',
'regSQ_DEBUG_STS_GLOBAL_BASE_IDX', 'regSQ_DSM_CNTL',
'regSQ_DSM_CNTL2', 'regSQ_DSM_CNTL2_BASE_IDX',
'regSQ_DSM_CNTL_BASE_IDX', 'regSQ_FIFO_SIZES',
'regSQ_FIFO_SIZES_BASE_IDX', 'regSQ_IND_DATA',
'regSQ_IND_DATA_BASE_IDX', 'regSQ_IND_INDEX',
'regSQ_IND_INDEX_BASE_IDX', 'regSQ_INTERRUPT_AUTO_MASK',
'regSQ_INTERRUPT_AUTO_MASK_BASE_IDX', 'regSQ_INTERRUPT_MSG_CTRL',
'regSQ_INTERRUPT_MSG_CTRL_BASE_IDX', 'regSQ_LDS_CLK_CTRL',
'regSQ_LDS_CLK_CTRL_BASE_IDX', 'regSQ_PERFCOUNTER0_LO',
'regSQ_PERFCOUNTER0_LO_BASE_IDX', 'regSQ_PERFCOUNTER0_SELECT',
'regSQ_PERFCOUNTER0_SELECT_BASE_IDX',
'regSQ_PERFCOUNTER10_SELECT',
'regSQ_PERFCOUNTER10_SELECT_BASE_IDX',
'regSQ_PERFCOUNTER11_SELECT',
'regSQ_PERFCOUNTER11_SELECT_BASE_IDX',
'regSQ_PERFCOUNTER12_SELECT',
'regSQ_PERFCOUNTER12_SELECT_BASE_IDX',
'regSQ_PERFCOUNTER13_SELECT',
'regSQ_PERFCOUNTER13_SELECT_BASE_IDX',
'regSQ_PERFCOUNTER14_SELECT',
'regSQ_PERFCOUNTER14_SELECT_BASE_IDX',
'regSQ_PERFCOUNTER15_SELECT',
'regSQ_PERFCOUNTER15_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER1_LO',
'regSQ_PERFCOUNTER1_LO_BASE_IDX', 'regSQ_PERFCOUNTER1_SELECT',
'regSQ_PERFCOUNTER1_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER2_LO',
'regSQ_PERFCOUNTER2_LO_BASE_IDX', 'regSQ_PERFCOUNTER2_SELECT',
'regSQ_PERFCOUNTER2_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER3_LO',
'regSQ_PERFCOUNTER3_LO_BASE_IDX', 'regSQ_PERFCOUNTER3_SELECT',
'regSQ_PERFCOUNTER3_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER4_LO',
'regSQ_PERFCOUNTER4_LO_BASE_IDX', 'regSQ_PERFCOUNTER4_SELECT',
'regSQ_PERFCOUNTER4_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER5_LO',
'regSQ_PERFCOUNTER5_LO_BASE_IDX', 'regSQ_PERFCOUNTER5_SELECT',
'regSQ_PERFCOUNTER5_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER6_LO',
'regSQ_PERFCOUNTER6_LO_BASE_IDX', 'regSQ_PERFCOUNTER6_SELECT',
'regSQ_PERFCOUNTER6_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER7_LO',
'regSQ_PERFCOUNTER7_LO_BASE_IDX', 'regSQ_PERFCOUNTER7_SELECT',
'regSQ_PERFCOUNTER7_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER8_SELECT',
'regSQ_PERFCOUNTER8_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER9_SELECT',
'regSQ_PERFCOUNTER9_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER_CTRL',
'regSQ_PERFCOUNTER_CTRL2', 'regSQ_PERFCOUNTER_CTRL2_BASE_IDX',
'regSQ_PERFCOUNTER_CTRL_BASE_IDX', 'regSQ_PERF_SNAPSHOT_CTRL',
'regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX', 'regSQ_RANDOM_WAVE_PRI',
'regSQ_RANDOM_WAVE_PRI_BASE_IDX', 'regSQ_RUNTIME_CONFIG',
'regSQ_RUNTIME_CONFIG_BASE_IDX', 'regSQ_SHADER_TBA_HI',
'regSQ_SHADER_TBA_HI_BASE_IDX', 'regSQ_SHADER_TBA_LO',
'regSQ_SHADER_TBA_LO_BASE_IDX', 'regSQ_SHADER_TMA_HI',
'regSQ_SHADER_TMA_HI_BASE_IDX', 'regSQ_SHADER_TMA_LO',
'regSQ_SHADER_TMA_LO_BASE_IDX', 'regSQ_TEX_CLK_CTRL',
'regSQ_TEX_CLK_CTRL_BASE_IDX', 'regSQ_THREAD_TRACE_BUF0_BASE',
'regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX',
'regSQ_THREAD_TRACE_BUF0_SIZE',
'regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX',
'regSQ_THREAD_TRACE_BUF1_BASE',
'regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX',
'regSQ_THREAD_TRACE_BUF1_SIZE',
'regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX',
'regSQ_THREAD_TRACE_CTRL', 'regSQ_THREAD_TRACE_CTRL_BASE_IDX',
'regSQ_THREAD_TRACE_DROPPED_CNTR',
'regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX',
'regSQ_THREAD_TRACE_GFX_DRAW_CNTR',
'regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX',
'regSQ_THREAD_TRACE_GFX_MARKER_CNTR',
'regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX',
'regSQ_THREAD_TRACE_HP3D_DRAW_CNTR',
'regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX',
'regSQ_THREAD_TRACE_HP3D_MARKER_CNTR',
'regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX',
'regSQ_THREAD_TRACE_MASK', 'regSQ_THREAD_TRACE_MASK_BASE_IDX',
'regSQ_THREAD_TRACE_STATUS', 'regSQ_THREAD_TRACE_STATUS2',
'regSQ_THREAD_TRACE_STATUS2_BASE_IDX',
'regSQ_THREAD_TRACE_STATUS_BASE_IDX',
'regSQ_THREAD_TRACE_TOKEN_MASK',
'regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX',
'regSQ_THREAD_TRACE_USERDATA_0',
'regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX',
'regSQ_THREAD_TRACE_USERDATA_1',
'regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX',
'regSQ_THREAD_TRACE_USERDATA_2',
'regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX',
'regSQ_THREAD_TRACE_USERDATA_3',
'regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX',
'regSQ_THREAD_TRACE_USERDATA_4',
'regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX',
'regSQ_THREAD_TRACE_USERDATA_5',
'regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX',
'regSQ_THREAD_TRACE_USERDATA_6',
'regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX',
'regSQ_THREAD_TRACE_USERDATA_7',
'regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX',
'regSQ_THREAD_TRACE_WPTR', 'regSQ_THREAD_TRACE_WPTR_BASE_IDX',
'regSQ_WATCH0_ADDR_H', 'regSQ_WATCH0_ADDR_H_BASE_IDX',
'regSQ_WATCH0_ADDR_L', 'regSQ_WATCH0_ADDR_L_BASE_IDX',
'regSQ_WATCH0_CNTL', 'regSQ_WATCH0_CNTL_BASE_IDX',
'regSQ_WATCH1_ADDR_H', 'regSQ_WATCH1_ADDR_H_BASE_IDX',
'regSQ_WATCH1_ADDR_L', 'regSQ_WATCH1_ADDR_L_BASE_IDX',
'regSQ_WATCH1_CNTL', 'regSQ_WATCH1_CNTL_BASE_IDX',
'regSQ_WATCH2_ADDR_H', 'regSQ_WATCH2_ADDR_H_BASE_IDX',
'regSQ_WATCH2_ADDR_L', 'regSQ_WATCH2_ADDR_L_BASE_IDX',
'regSQ_WATCH2_CNTL', 'regSQ_WATCH2_CNTL_BASE_IDX',
'regSQ_WATCH3_ADDR_H', 'regSQ_WATCH3_ADDR_H_BASE_IDX',
'regSQ_WATCH3_ADDR_L', 'regSQ_WATCH3_ADDR_L_BASE_IDX',
'regSQ_WATCH3_CNTL', 'regSQ_WATCH3_CNTL_BASE_IDX',
'regSX_BLEND_OPT_CONTROL', 'regSX_BLEND_OPT_CONTROL_BASE_IDX',
'regSX_BLEND_OPT_EPSILON', 'regSX_BLEND_OPT_EPSILON_BASE_IDX',
'regSX_DEBUG_1', 'regSX_DEBUG_1_BASE_IDX', 'regSX_MRT0_BLEND_OPT',
'regSX_MRT0_BLEND_OPT_BASE_IDX', 'regSX_MRT1_BLEND_OPT',
'regSX_MRT1_BLEND_OPT_BASE_IDX', 'regSX_MRT2_BLEND_OPT',
'regSX_MRT2_BLEND_OPT_BASE_IDX', 'regSX_MRT3_BLEND_OPT',
'regSX_MRT3_BLEND_OPT_BASE_IDX', 'regSX_MRT4_BLEND_OPT',
'regSX_MRT4_BLEND_OPT_BASE_IDX', 'regSX_MRT5_BLEND_OPT',
'regSX_MRT5_BLEND_OPT_BASE_IDX', 'regSX_MRT6_BLEND_OPT',
'regSX_MRT6_BLEND_OPT_BASE_IDX', 'regSX_MRT7_BLEND_OPT',
'regSX_MRT7_BLEND_OPT_BASE_IDX', 'regSX_PERFCOUNTER0_HI',
'regSX_PERFCOUNTER0_HI_BASE_IDX', 'regSX_PERFCOUNTER0_LO',
'regSX_PERFCOUNTER0_LO_BASE_IDX', 'regSX_PERFCOUNTER0_SELECT',
'regSX_PERFCOUNTER0_SELECT1',
'regSX_PERFCOUNTER0_SELECT1_BASE_IDX',
'regSX_PERFCOUNTER0_SELECT_BASE_IDX', 'regSX_PERFCOUNTER1_HI',
'regSX_PERFCOUNTER1_HI_BASE_IDX', 'regSX_PERFCOUNTER1_LO',
'regSX_PERFCOUNTER1_LO_BASE_IDX', 'regSX_PERFCOUNTER1_SELECT',
'regSX_PERFCOUNTER1_SELECT1',
'regSX_PERFCOUNTER1_SELECT1_BASE_IDX',
'regSX_PERFCOUNTER1_SELECT_BASE_IDX', 'regSX_PERFCOUNTER2_HI',
'regSX_PERFCOUNTER2_HI_BASE_IDX', 'regSX_PERFCOUNTER2_LO',
'regSX_PERFCOUNTER2_LO_BASE_IDX', 'regSX_PERFCOUNTER2_SELECT',
'regSX_PERFCOUNTER2_SELECT_BASE_IDX', 'regSX_PERFCOUNTER3_HI',
'regSX_PERFCOUNTER3_HI_BASE_IDX', 'regSX_PERFCOUNTER3_LO',
'regSX_PERFCOUNTER3_LO_BASE_IDX', 'regSX_PERFCOUNTER3_SELECT',
'regSX_PERFCOUNTER3_SELECT_BASE_IDX', 'regSX_PS_DOWNCONVERT',
'regSX_PS_DOWNCONVERT_BASE_IDX', 'regSX_PS_DOWNCONVERT_CONTROL',
'regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX', 'regTA_BC_BASE_ADDR',
'regTA_BC_BASE_ADDR_BASE_IDX', 'regTA_BC_BASE_ADDR_HI',
'regTA_BC_BASE_ADDR_HI_BASE_IDX', 'regTA_CGTT_CTRL',
'regTA_CGTT_CTRL_BASE_IDX', 'regTA_CNTL', 'regTA_CNTL2',
'regTA_CNTL2_BASE_IDX', 'regTA_CNTL_AUX',
'regTA_CNTL_AUX_BASE_IDX', 'regTA_CNTL_BASE_IDX',
'regTA_CS_BC_BASE_ADDR', 'regTA_CS_BC_BASE_ADDR_BASE_IDX',
'regTA_CS_BC_BASE_ADDR_HI', 'regTA_CS_BC_BASE_ADDR_HI_BASE_IDX',
'regTA_PERFCOUNTER0_HI', 'regTA_PERFCOUNTER0_HI_BASE_IDX',
'regTA_PERFCOUNTER0_LO', 'regTA_PERFCOUNTER0_LO_BASE_IDX',
'regTA_PERFCOUNTER0_SELECT', 'regTA_PERFCOUNTER0_SELECT1',
'regTA_PERFCOUNTER0_SELECT1_BASE_IDX',
'regTA_PERFCOUNTER0_SELECT_BASE_IDX', 'regTA_PERFCOUNTER1_HI',
'regTA_PERFCOUNTER1_HI_BASE_IDX', 'regTA_PERFCOUNTER1_LO',
'regTA_PERFCOUNTER1_LO_BASE_IDX', 'regTA_PERFCOUNTER1_SELECT',
'regTA_PERFCOUNTER1_SELECT_BASE_IDX', 'regTA_SCRATCH',
'regTA_SCRATCH_BASE_IDX', 'regTA_STATUS', 'regTA_STATUS_BASE_IDX',
'regTCP_CNTL', 'regTCP_CNTL2', 'regTCP_CNTL2_BASE_IDX',
'regTCP_CNTL_BASE_IDX', 'regTCP_DEBUG_DATA',
'regTCP_DEBUG_DATA_BASE_IDX', 'regTCP_DEBUG_INDEX',
'regTCP_DEBUG_INDEX_BASE_IDX', 'regTCP_INVALIDATE',
'regTCP_INVALIDATE_BASE_IDX', 'regTCP_PERFCOUNTER0_HI',
'regTCP_PERFCOUNTER0_HI_BASE_IDX', 'regTCP_PERFCOUNTER0_LO',
'regTCP_PERFCOUNTER0_LO_BASE_IDX', 'regTCP_PERFCOUNTER0_SELECT',
'regTCP_PERFCOUNTER0_SELECT1',
'regTCP_PERFCOUNTER0_SELECT1_BASE_IDX',
'regTCP_PERFCOUNTER0_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER1_HI',
'regTCP_PERFCOUNTER1_HI_BASE_IDX', 'regTCP_PERFCOUNTER1_LO',
'regTCP_PERFCOUNTER1_LO_BASE_IDX', 'regTCP_PERFCOUNTER1_SELECT',
'regTCP_PERFCOUNTER1_SELECT1',
'regTCP_PERFCOUNTER1_SELECT1_BASE_IDX',
'regTCP_PERFCOUNTER1_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER2_HI',
'regTCP_PERFCOUNTER2_HI_BASE_IDX', 'regTCP_PERFCOUNTER2_LO',
'regTCP_PERFCOUNTER2_LO_BASE_IDX', 'regTCP_PERFCOUNTER2_SELECT',
'regTCP_PERFCOUNTER2_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER3_HI',
'regTCP_PERFCOUNTER3_HI_BASE_IDX', 'regTCP_PERFCOUNTER3_LO',
'regTCP_PERFCOUNTER3_LO_BASE_IDX', 'regTCP_PERFCOUNTER3_SELECT',
'regTCP_PERFCOUNTER3_SELECT_BASE_IDX',
'regTCP_PERFCOUNTER_FILTER', 'regTCP_PERFCOUNTER_FILTER2',
'regTCP_PERFCOUNTER_FILTER2_BASE_IDX',
'regTCP_PERFCOUNTER_FILTER_BASE_IDX',
'regTCP_PERFCOUNTER_FILTER_EN',
'regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX', 'regTCP_STATUS',
'regTCP_STATUS_BASE_IDX', 'regTCP_WATCH0_ADDR_H',
'regTCP_WATCH0_ADDR_H_BASE_IDX', 'regTCP_WATCH0_ADDR_L',
'regTCP_WATCH0_ADDR_L_BASE_IDX', 'regTCP_WATCH0_CNTL',
'regTCP_WATCH0_CNTL_BASE_IDX', 'regTCP_WATCH1_ADDR_H',
'regTCP_WATCH1_ADDR_H_BASE_IDX', 'regTCP_WATCH1_ADDR_L',
'regTCP_WATCH1_ADDR_L_BASE_IDX', 'regTCP_WATCH1_CNTL',
'regTCP_WATCH1_CNTL_BASE_IDX', 'regTCP_WATCH2_ADDR_H',
'regTCP_WATCH2_ADDR_H_BASE_IDX', 'regTCP_WATCH2_ADDR_L',
'regTCP_WATCH2_ADDR_L_BASE_IDX', 'regTCP_WATCH2_CNTL',
'regTCP_WATCH2_CNTL_BASE_IDX', 'regTCP_WATCH3_ADDR_H',
'regTCP_WATCH3_ADDR_H_BASE_IDX', 'regTCP_WATCH3_ADDR_L',
'regTCP_WATCH3_ADDR_L_BASE_IDX', 'regTCP_WATCH3_CNTL',
'regTCP_WATCH3_CNTL_BASE_IDX', 'regTD_DSM_CNTL',
'regTD_DSM_CNTL2', 'regTD_DSM_CNTL2_BASE_IDX',
'regTD_DSM_CNTL_BASE_IDX', 'regTD_PERFCOUNTER0_HI',
'regTD_PERFCOUNTER0_HI_BASE_IDX', 'regTD_PERFCOUNTER0_LO',
'regTD_PERFCOUNTER0_LO_BASE_IDX', 'regTD_PERFCOUNTER0_SELECT',
'regTD_PERFCOUNTER0_SELECT1',
'regTD_PERFCOUNTER0_SELECT1_BASE_IDX',
'regTD_PERFCOUNTER0_SELECT_BASE_IDX', 'regTD_PERFCOUNTER1_HI',
'regTD_PERFCOUNTER1_HI_BASE_IDX', 'regTD_PERFCOUNTER1_LO',
'regTD_PERFCOUNTER1_LO_BASE_IDX', 'regTD_PERFCOUNTER1_SELECT',
'regTD_PERFCOUNTER1_SELECT_BASE_IDX', 'regTD_SCRATCH',
'regTD_SCRATCH_BASE_IDX', 'regTD_STATUS', 'regTD_STATUS_BASE_IDX',
'regUCONFIG_RESERVED_REG0', 'regUCONFIG_RESERVED_REG0_BASE_IDX',
'regUCONFIG_RESERVED_REG1', 'regUCONFIG_RESERVED_REG1_BASE_IDX',
'regUTCL1_ALOG', 'regUTCL1_ALOG_BASE_IDX', 'regUTCL1_CTRL_0',
'regUTCL1_CTRL_0_BASE_IDX', 'regUTCL1_CTRL_1',
'regUTCL1_CTRL_1_BASE_IDX', 'regUTCL1_CTRL_2',
'regUTCL1_CTRL_2_BASE_IDX', 'regUTCL1_FIFO_SIZING',
'regUTCL1_FIFO_SIZING_BASE_IDX', 'regUTCL1_PERFCOUNTER0_HI',
'regUTCL1_PERFCOUNTER0_HI_BASE_IDX', 'regUTCL1_PERFCOUNTER0_LO',
'regUTCL1_PERFCOUNTER0_LO_BASE_IDX',
'regUTCL1_PERFCOUNTER0_SELECT',
'regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX',
'regUTCL1_PERFCOUNTER1_HI', 'regUTCL1_PERFCOUNTER1_HI_BASE_IDX',
'regUTCL1_PERFCOUNTER1_LO', 'regUTCL1_PERFCOUNTER1_LO_BASE_IDX',
'regUTCL1_PERFCOUNTER1_SELECT',
'regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX',
'regUTCL1_PERFCOUNTER2_HI', 'regUTCL1_PERFCOUNTER2_HI_BASE_IDX',
'regUTCL1_PERFCOUNTER2_LO', 'regUTCL1_PERFCOUNTER2_LO_BASE_IDX',
'regUTCL1_PERFCOUNTER2_SELECT',
'regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX',
'regUTCL1_PERFCOUNTER3_HI', 'regUTCL1_PERFCOUNTER3_HI_BASE_IDX',
'regUTCL1_PERFCOUNTER3_LO', 'regUTCL1_PERFCOUNTER3_LO_BASE_IDX',
'regUTCL1_PERFCOUNTER3_SELECT',
'regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX', 'regUTCL1_STATUS',
'regUTCL1_STATUS_BASE_IDX', 'regUTCL1_UTCL0_INVREQ_DISABLE',
'regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX', 'regVGT_DMA_BASE',
'regVGT_DMA_BASE_BASE_IDX', 'regVGT_DMA_BASE_HI',
'regVGT_DMA_BASE_HI_BASE_IDX', 'regVGT_DMA_DATA_FIFO_DEPTH',
'regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX', 'regVGT_DMA_INDEX_TYPE',
'regVGT_DMA_INDEX_TYPE_BASE_IDX', 'regVGT_DMA_MAX_SIZE',
'regVGT_DMA_MAX_SIZE_BASE_IDX', 'regVGT_DMA_NUM_INSTANCES',
'regVGT_DMA_NUM_INSTANCES_BASE_IDX', 'regVGT_DMA_REQ_FIFO_DEPTH',
'regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX', 'regVGT_DMA_SIZE',
'regVGT_DMA_SIZE_BASE_IDX', 'regVGT_DRAW_INITIATOR',
'regVGT_DRAW_INITIATOR_BASE_IDX', 'regVGT_DRAW_INIT_FIFO_DEPTH',
'regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX',
'regVGT_DRAW_PAYLOAD_CNTL', 'regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX',
'regVGT_ENHANCE', 'regVGT_ENHANCE_BASE_IDX',
'regVGT_ESGS_RING_ITEMSIZE', 'regVGT_ESGS_RING_ITEMSIZE_BASE_IDX',
'regVGT_EVENT_ADDRESS_REG', 'regVGT_EVENT_ADDRESS_REG_BASE_IDX',
'regVGT_EVENT_INITIATOR', 'regVGT_EVENT_INITIATOR_BASE_IDX',
'regVGT_GS_INSTANCE_CNT', 'regVGT_GS_INSTANCE_CNT_BASE_IDX',
'regVGT_GS_MAX_VERT_OUT', 'regVGT_GS_MAX_VERT_OUT_BASE_IDX',
'regVGT_GS_MAX_WAVE_ID', 'regVGT_GS_MAX_WAVE_ID_BASE_IDX',
'regVGT_GS_OUT_PRIM_TYPE', 'regVGT_GS_OUT_PRIM_TYPE_BASE_IDX',
'regVGT_HOS_MAX_TESS_LEVEL', 'regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX',
'regVGT_HOS_MIN_TESS_LEVEL', 'regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX',
'regVGT_HS_OFFCHIP_PARAM', 'regVGT_HS_OFFCHIP_PARAM_BASE_IDX',
'regVGT_INDEX_TYPE', 'regVGT_INDEX_TYPE_BASE_IDX',
'regVGT_INSTANCE_BASE_ID', 'regVGT_INSTANCE_BASE_ID_BASE_IDX',
'regVGT_LS_HS_CONFIG', 'regVGT_LS_HS_CONFIG_BASE_IDX',
'regVGT_MC_LAT_CNTL', 'regVGT_MC_LAT_CNTL_BASE_IDX',
'regVGT_MULTI_PRIM_IB_RESET_INDX',
'regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX', 'regVGT_NUM_INDICES',
'regVGT_NUM_INDICES_BASE_IDX', 'regVGT_NUM_INSTANCES',
'regVGT_NUM_INSTANCES_BASE_IDX', 'regVGT_PRIMITIVEID_EN',
'regVGT_PRIMITIVEID_EN_BASE_IDX', 'regVGT_PRIMITIVEID_RESET',
'regVGT_PRIMITIVEID_RESET_BASE_IDX', 'regVGT_PRIMITIVE_TYPE',
'regVGT_PRIMITIVE_TYPE_BASE_IDX', 'regVGT_REUSE_OFF',
'regVGT_REUSE_OFF_BASE_IDX', 'regVGT_SHADER_STAGES_EN',
'regVGT_SHADER_STAGES_EN_BASE_IDX',
'regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE',
'regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX',
'regVGT_STRMOUT_DRAW_OPAQUE_OFFSET',
'regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX',
'regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE',
'regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX',
'regVGT_SYS_CONFIG', 'regVGT_SYS_CONFIG_BASE_IDX',
'regVGT_TESS_DISTRIBUTION', 'regVGT_TESS_DISTRIBUTION_BASE_IDX',
'regVGT_TF_MEMORY_BASE', 'regVGT_TF_MEMORY_BASE_BASE_IDX',
'regVGT_TF_MEMORY_BASE_HI', 'regVGT_TF_MEMORY_BASE_HI_BASE_IDX',
'regVGT_TF_PARAM', 'regVGT_TF_PARAM_BASE_IDX',
'regVGT_TF_RING_SIZE', 'regVGT_TF_RING_SIZE_BASE_IDX',
'regVIOLATION_DATA_ASYNC_VF_PROG',
'regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX', 'regWD_CNTL_STATUS',
'regWD_CNTL_STATUS_BASE_IDX', 'regWD_ENHANCE',
'regWD_ENHANCE_BASE_IDX', 'regWD_QOS', 'regWD_QOS_BASE_IDX',
'regWD_UTCL1_CNTL', 'regWD_UTCL1_CNTL_BASE_IDX',
'regWD_UTCL1_STATUS', 'regWD_UTCL1_STATUS_BASE_IDX',
'struct_IP_BASE', 'struct_IP_BASE_INSTANCE',
'struct_PM4_MES_TYPE_3_HEADER_0', 'struct_SDMA_PKT_ATOMIC_TAG',
'struct_SDMA_PKT_ATOMIC_TAG_0_0',
'struct_SDMA_PKT_ATOMIC_TAG_1_0',
'struct_SDMA_PKT_ATOMIC_TAG_2_0',
'struct_SDMA_PKT_ATOMIC_TAG_3_0',
'struct_SDMA_PKT_ATOMIC_TAG_4_0',
'struct_SDMA_PKT_ATOMIC_TAG_5_0',
'struct_SDMA_PKT_ATOMIC_TAG_6_0',
'struct_SDMA_PKT_ATOMIC_TAG_7_0',
'struct_SDMA_PKT_CONSTANT_FILL_TAG',
'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0',
'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0',
'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0',
'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0',
'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0',
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0',
'struct_SDMA_PKT_COPY_LINEAR_TAG',
'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0',
'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0',
'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0',
'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0',
'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0',
'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0',
'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0',
'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0',
'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0',
'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG',
'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0',
'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0',
'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG',
'struct_SDMA_PKT_POLL_REGMEM_TAG',
'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0',
'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0',
'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0',
'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0',
'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0',
'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0',
'struct_SDMA_PKT_TIMESTAMP_TAG',
'struct_SDMA_PKT_TIMESTAMP_TAG_0_0',
'struct_SDMA_PKT_TIMESTAMP_TAG_1_0',
'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG',
'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0',
'struct_pm4_mec_release_mem',
'struct_pm4_mec_release_mem_1_bitfields2',
'struct_pm4_mec_release_mem_2_bitfields3',
'struct_pm4_mec_release_mem_3_bitfields4',
'struct_pm4_mec_release_mem_3_bitfields4b',
'struct_pm4_mec_release_mem_5_bitfields6c',
'struct_pm4_mec_write_data_mmio',
'struct_pm4_mec_write_data_mmio_1_bitfields2',
'struct_pm4_mec_write_data_mmio_2_bitfields3', 'uint32_t',
'union_PM4_MES_TYPE_3_HEADER',
'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION',
'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION',
'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION',
'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION',
'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION',
'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION',
'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION',
'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION',
'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION',
'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION',
'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION',
'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION',
'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION',
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION',
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION',
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION',
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION',
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION',
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION',
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION',
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION',
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION',
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION',
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION',
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION',
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION',
'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION',
'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION',
'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION',
'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION',
'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION',
'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION',
'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION',
'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION',
'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION',
'union_SDMA_PKT_FENCE_TAG_DATA_UNION',
'union_SDMA_PKT_FENCE_TAG_HEADER_UNION',
'union_SDMA_PKT_GCR_TAG_HEADER_UNION',
'union_SDMA_PKT_GCR_TAG_WORD1_UNION',
'union_SDMA_PKT_GCR_TAG_WORD2_UNION',
'union_SDMA_PKT_GCR_TAG_WORD3_UNION',
'union_SDMA_PKT_GCR_TAG_WORD4_UNION',
'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION',
'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION',
'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION',
'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION',
'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION',
'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION',
'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION',
'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION',
'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION',
'union_SDMA_PKT_TRAP_TAG_HEADER_UNION',
'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION',
'union_pm4_mec_release_mem_0', 'union_pm4_mec_release_mem_1',
'union_pm4_mec_release_mem_2', 'union_pm4_mec_release_mem_3',
'union_pm4_mec_release_mem_4', 'union_pm4_mec_release_mem_5',
'union_pm4_mec_release_mem_6', 'union_pm4_mec_write_data_mmio_0',
'union_pm4_mec_write_data_mmio_1',
'union_pm4_mec_write_data_mmio_2',
'wr_confirm___write_data__do_not_wait_for_write_confirmation',
'wr_confirm___write_data__wait_for_write_confirmation']