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109 lines
3.3 KiB
109 lines
3.3 KiB
#if defined(ENABLE_SPI) || defined(BOOTSTUB)
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// master -> panda DMA start
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void llspi_mosi_dma(uint8_t *addr, int len) {
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// disable DMA + SPI
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register_clear_bits(&(SPI4->CFG1), SPI_CFG1_RXDMAEN);
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DMA2_Stream2->CR &= ~DMA_SxCR_EN;
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register_clear_bits(&(SPI4->CR1), SPI_CR1_SPE);
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// drain the bus
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while ((SPI4->SR & SPI_SR_RXP) != 0U) {
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volatile uint8_t dat = SPI4->RXDR;
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(void)dat;
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}
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// clear all pending
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SPI4->IFCR |= (0x1FFU << 3U);
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register_set(&(SPI4->IER), 0, 0x3FFU);
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// setup destination and length
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register_set(&(DMA2_Stream2->M0AR), (uint32_t)addr, 0xFFFFFFFFU);
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DMA2_Stream2->NDTR = len;
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// enable DMA + SPI
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DMA2_Stream2->CR |= DMA_SxCR_EN;
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register_set_bits(&(SPI4->CFG1), SPI_CFG1_RXDMAEN);
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register_set_bits(&(SPI4->CR1), SPI_CR1_SPE);
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}
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// panda -> master DMA start
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void llspi_miso_dma(uint8_t *addr, int len) {
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// disable DMA + SPI
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DMA2_Stream3->CR &= ~DMA_SxCR_EN;
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register_clear_bits(&(SPI4->CFG1), SPI_CFG1_TXDMAEN);
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register_clear_bits(&(SPI4->CR1), SPI_CR1_SPE);
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// setup source and length
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register_set(&(DMA2_Stream3->M0AR), (uint32_t)addr, 0xFFFFFFFFU);
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DMA2_Stream3->NDTR = len;
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// clear under-run while we were reading
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SPI4->IFCR |= (0x1FFU << 3U);
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// setup interrupt on TXC
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register_set(&(SPI4->IER), (1U << SPI_IER_EOTIE_Pos), 0x3FFU);
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// enable DMA + SPI
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register_set_bits(&(SPI4->CFG1), SPI_CFG1_TXDMAEN);
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DMA2_Stream3->CR |= DMA_SxCR_EN;
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register_set_bits(&(SPI4->CR1), SPI_CR1_SPE);
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}
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static bool spi_tx_dma_done = false;
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// master -> panda DMA finished
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static void DMA2_Stream2_IRQ_Handler(void) {
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// Clear interrupt flag
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DMA2->LIFCR = DMA_LIFCR_CTCIF2;
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spi_rx_done();
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}
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// panda -> master DMA finished
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static void DMA2_Stream3_IRQ_Handler(void) {
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ENTER_CRITICAL();
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DMA2->LIFCR = DMA_LIFCR_CTCIF3;
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spi_tx_dma_done = true;
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EXIT_CRITICAL();
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}
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// panda TX finished
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static void SPI4_IRQ_Handler(void) {
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// clear flag
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SPI4->IFCR |= (0x1FFU << 3U);
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if (spi_tx_dma_done && ((SPI4->SR & SPI_SR_TXC) != 0U)) {
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spi_tx_dma_done = false;
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spi_tx_done(false);
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}
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}
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void llspi_init(void) {
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REGISTER_INTERRUPT(SPI4_IRQn, SPI4_IRQ_Handler, (SPI_IRQ_RATE * 2U), FAULT_INTERRUPT_RATE_SPI)
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REGISTER_INTERRUPT(DMA2_Stream2_IRQn, DMA2_Stream2_IRQ_Handler, SPI_IRQ_RATE, FAULT_INTERRUPT_RATE_SPI_DMA)
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REGISTER_INTERRUPT(DMA2_Stream3_IRQn, DMA2_Stream3_IRQ_Handler, SPI_IRQ_RATE, FAULT_INTERRUPT_RATE_SPI_DMA)
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// Setup MOSI DMA
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register_set(&(DMAMUX1_Channel10->CCR), 83U, 0xFFFFFFFFU);
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register_set(&(DMA2_Stream2->CR), (DMA_SxCR_MINC | DMA_SxCR_TCIE), 0x1E077EFEU);
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register_set(&(DMA2_Stream2->PAR), (uint32_t)&(SPI4->RXDR), 0xFFFFFFFFU);
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// Setup MISO DMA, memory -> peripheral
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register_set(&(DMAMUX1_Channel11->CCR), 84U, 0xFFFFFFFFU);
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register_set(&(DMA2_Stream3->CR), (DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_TCIE), 0x1E077EFEU);
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register_set(&(DMA2_Stream3->PAR), (uint32_t)&(SPI4->TXDR), 0xFFFFFFFFU);
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// Enable SPI
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register_set(&(SPI4->IER), 0, 0x3FFU);
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register_set(&(SPI4->CFG1), (7U << SPI_CFG1_DSIZE_Pos), SPI_CFG1_DSIZE_Msk);
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register_set(&(SPI4->UDRDR), 0xcd, 0xFFFFU); // set under-run value for debugging
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register_set(&(SPI4->CR1), SPI_CR1_SPE, 0xFFFFU);
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register_set(&(SPI4->CR2), 0, 0xFFFFU);
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NVIC_EnableIRQ(DMA2_Stream2_IRQn);
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NVIC_EnableIRQ(DMA2_Stream3_IRQn);
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NVIC_EnableIRQ(SPI4_IRQn);
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}
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#endif
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