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22115 lines
1001 KiB
22115 lines
1001 KiB
# mypy: ignore-errors
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# -*- coding: utf-8 -*-
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#
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# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++']
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# WORD_SIZE is: 8
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# POINTER_SIZE is: 8
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# LONGDOUBLE_SIZE is: 16
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#
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import ctypes, os
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class AsDictMixin:
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@classmethod
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def as_dict(cls, self):
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result = {}
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if not isinstance(self, AsDictMixin):
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# not a structure, assume it's already a python object
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return self
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if not hasattr(cls, "_fields_"):
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return result
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# sys.version_info >= (3, 5)
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# for (field, *_) in cls._fields_: # noqa
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for field_tuple in cls._fields_: # noqa
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field = field_tuple[0]
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if field.startswith('PADDING_'):
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continue
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value = getattr(self, field)
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type_ = type(value)
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if hasattr(value, "_length_") and hasattr(value, "_type_"):
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# array
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if not hasattr(type_, "as_dict"):
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value = [v for v in value]
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else:
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type_ = type_._type_
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value = [type_.as_dict(v) for v in value]
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elif hasattr(value, "contents") and hasattr(value, "_type_"):
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# pointer
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try:
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if not hasattr(type_, "as_dict"):
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value = value.contents
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else:
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type_ = type_._type_
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value = type_.as_dict(value.contents)
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except ValueError:
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# nullptr
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value = None
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elif isinstance(value, AsDictMixin):
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# other structure
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value = type_.as_dict(value)
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result[field] = value
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return result
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class Structure(ctypes.Structure, AsDictMixin):
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def __init__(self, *args, **kwds):
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# We don't want to use positional arguments fill PADDING_* fields
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args = dict(zip(self.__class__._field_names_(), args))
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args.update(kwds)
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super(Structure, self).__init__(**args)
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@classmethod
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def _field_names_(cls):
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if hasattr(cls, '_fields_'):
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return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING'))
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else:
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return ()
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@classmethod
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def get_type(cls, field):
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for f in cls._fields_:
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if f[0] == field:
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return f[1]
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return None
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@classmethod
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def bind(cls, bound_fields):
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fields = {}
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for name, type_ in cls._fields_:
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if hasattr(type_, "restype"):
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if name in bound_fields:
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if bound_fields[name] is None:
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fields[name] = type_()
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else:
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# use a closure to capture the callback from the loop scope
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fields[name] = (
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type_((lambda callback: lambda *args: callback(*args))(
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bound_fields[name]))
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)
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del bound_fields[name]
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else:
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# default callback implementation (does nothing)
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try:
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default_ = type_(0).restype().value
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except TypeError:
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default_ = None
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fields[name] = type_((
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lambda default_: lambda *args: default_)(default_))
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else:
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# not a callback function, use default initialization
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if name in bound_fields:
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fields[name] = bound_fields[name]
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del bound_fields[name]
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else:
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fields[name] = type_()
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if len(bound_fields) != 0:
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raise ValueError(
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"Cannot bind the following unknown callback(s) {}.{}".format(
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cls.__name__, bound_fields.keys()
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))
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return cls(**fields)
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class Union(ctypes.Union, AsDictMixin):
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pass
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HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro
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SDMA_OP_COPY = 1 # Variable ctypes.c_uint32
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SDMA_OP_FENCE = 5 # Variable ctypes.c_uint32
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SDMA_OP_TRAP = 6 # Variable ctypes.c_uint32
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SDMA_OP_POLL_REGMEM = 8 # Variable ctypes.c_uint32
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SDMA_OP_ATOMIC = 10 # Variable ctypes.c_uint32
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SDMA_OP_CONST_FILL = 11 # Variable ctypes.c_uint32
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SDMA_OP_TIMESTAMP = 13 # Variable ctypes.c_uint32
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SDMA_OP_GCR = 17 # Variable ctypes.c_uint32
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SDMA_SUBOP_COPY_LINEAR = 0 # Variable ctypes.c_uint32
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SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32
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SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # Variable ctypes.c_uint32
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SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32
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SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32
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class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure):
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pass
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class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union):
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pass
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class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure):
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pass
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struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False
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struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [
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('op', ctypes.c_uint32, 8),
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('sub_op', ctypes.c_uint32, 8),
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('extra_info', ctypes.c_uint32, 16),
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]
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union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False
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union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',)
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union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [
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('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0),
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('DW_0_DATA', ctypes.c_uint32),
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]
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class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union):
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pass
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class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure):
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pass
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struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False
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struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [
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('count', ctypes.c_uint32, 22),
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('reserved_0', ctypes.c_uint32, 10),
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]
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union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False
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union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',)
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union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [
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('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0),
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('DW_1_DATA', ctypes.c_uint32),
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]
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class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union):
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pass
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class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure):
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pass
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struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False
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struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [
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('reserved_0', ctypes.c_uint32, 16),
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('dst_swap', ctypes.c_uint32, 2),
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('reserved_1', ctypes.c_uint32, 6),
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('src_swap', ctypes.c_uint32, 2),
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('reserved_2', ctypes.c_uint32, 6),
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]
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union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False
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union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',)
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union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [
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('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0),
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('DW_2_DATA', ctypes.c_uint32),
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]
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class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union):
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pass
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class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure):
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pass
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struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False
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struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [
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('src_addr_31_0', ctypes.c_uint32, 32),
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]
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union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False
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union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',)
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union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [
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('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0),
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('DW_3_DATA', ctypes.c_uint32),
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]
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class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union):
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pass
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class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure):
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pass
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struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False
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struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [
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('src_addr_63_32', ctypes.c_uint32, 32),
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]
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union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False
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union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',)
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union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [
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('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0),
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('DW_4_DATA', ctypes.c_uint32),
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]
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class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union):
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pass
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class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure):
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pass
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struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False
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struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [
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('dst_addr_31_0', ctypes.c_uint32, 32),
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]
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union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False
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union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',)
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union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [
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('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0),
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('DW_5_DATA', ctypes.c_uint32),
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]
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class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union):
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pass
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class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure):
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pass
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struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False
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struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [
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('dst_addr_63_32', ctypes.c_uint32, 32),
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]
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union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False
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union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',)
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union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [
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('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0),
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('DW_6_DATA', ctypes.c_uint32),
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]
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struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False
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struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [
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('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION),
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('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION),
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('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION),
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('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION),
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('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION),
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('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION),
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('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION),
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]
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SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG
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class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure):
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pass
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class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union):
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pass
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class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure):
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pass
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struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False
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struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [
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('op', ctypes.c_uint32, 8),
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('sub_op', ctypes.c_uint32, 8),
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('reserved', ctypes.c_uint32, 13),
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('element', ctypes.c_uint32, 3),
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]
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union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False
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union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',)
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union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [
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('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0),
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('DW_0_DATA', ctypes.c_uint32),
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]
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class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union):
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pass
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class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure):
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pass
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struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False
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struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [
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('src_addr_31_0', ctypes.c_uint32, 32),
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]
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union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False
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union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',)
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union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [
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('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0),
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('DW_1_DATA', ctypes.c_uint32),
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]
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class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union):
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pass
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class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure):
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pass
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struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False
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struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [
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('src_addr_63_32', ctypes.c_uint32, 32),
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]
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union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False
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union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',)
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union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [
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('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0),
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('DW_2_DATA', ctypes.c_uint32),
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]
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class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union):
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pass
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class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure):
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pass
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|
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struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False
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struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [
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('src_offset_x', ctypes.c_uint32, 14),
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('reserved_1', ctypes.c_uint32, 2),
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('src_offset_y', ctypes.c_uint32, 14),
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|
('reserved_2', ctypes.c_uint32, 2),
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]
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|
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union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False
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|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',)
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|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [
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('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0),
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('DW_3_DATA', ctypes.c_uint32),
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]
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|
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class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union):
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pass
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|
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class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure):
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pass
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|
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|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False
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struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [
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('src_offset_z', ctypes.c_uint32, 11),
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('reserved_1', ctypes.c_uint32, 2),
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|
('src_pitch', ctypes.c_uint32, 19),
|
|
]
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|
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|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False
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union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',)
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|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [
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|
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0),
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('DW_4_DATA', ctypes.c_uint32),
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]
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class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union):
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pass
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class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure):
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pass
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|
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|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False
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|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [
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|
('src_slice_pitch', ctypes.c_uint32, 28),
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('reserved_1', ctypes.c_uint32, 4),
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|
]
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|
|
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union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False
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|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',)
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|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [
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|
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0),
|
|
('DW_5_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [
|
|
('dst_addr_31_0', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0),
|
|
('DW_6_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [
|
|
('dst_addr_63_32', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0),
|
|
('DW_7_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [
|
|
('dst_offset_x', ctypes.c_uint32, 14),
|
|
('reserved_1', ctypes.c_uint32, 2),
|
|
('dst_offset_y', ctypes.c_uint32, 14),
|
|
('reserved_2', ctypes.c_uint32, 2),
|
|
]
|
|
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0),
|
|
('DW_8_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [
|
|
('dst_offset_z', ctypes.c_uint32, 11),
|
|
('reserved_1', ctypes.c_uint32, 2),
|
|
('dst_pitch', ctypes.c_uint32, 19),
|
|
]
|
|
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0),
|
|
('DW_9_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [
|
|
('dst_slice_pitch', ctypes.c_uint32, 28),
|
|
('reserved_1', ctypes.c_uint32, 4),
|
|
]
|
|
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0),
|
|
('DW_10_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [
|
|
('rect_x', ctypes.c_uint32, 14),
|
|
('reserved_1', ctypes.c_uint32, 2),
|
|
('rect_y', ctypes.c_uint32, 14),
|
|
('reserved_2', ctypes.c_uint32, 2),
|
|
]
|
|
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0),
|
|
('DW_11_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [
|
|
('rect_z', ctypes.c_uint32, 11),
|
|
('reserved_1', ctypes.c_uint32, 5),
|
|
('dst_swap', ctypes.c_uint32, 2),
|
|
('reserved_2', ctypes.c_uint32, 6),
|
|
('src_swap', ctypes.c_uint32, 2),
|
|
('reserved_3', ctypes.c_uint32, 6),
|
|
]
|
|
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0),
|
|
('DW_12_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [
|
|
('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION),
|
|
('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION),
|
|
('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION),
|
|
('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION),
|
|
('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION),
|
|
('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION),
|
|
('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION),
|
|
('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION),
|
|
('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION),
|
|
('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION),
|
|
('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION),
|
|
('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION),
|
|
('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION),
|
|
]
|
|
|
|
SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG
|
|
class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure):
|
|
pass
|
|
|
|
class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [
|
|
('op', ctypes.c_uint32, 8),
|
|
('sub_op', ctypes.c_uint32, 8),
|
|
('sw', ctypes.c_uint32, 2),
|
|
('reserved_0', ctypes.c_uint32, 12),
|
|
('fillsize', ctypes.c_uint32, 2),
|
|
]
|
|
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0),
|
|
('DW_0_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [
|
|
('dst_addr_31_0', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0),
|
|
('DW_1_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [
|
|
('dst_addr_63_32', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0),
|
|
('DW_2_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [
|
|
('src_data_31_0', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0),
|
|
('DW_3_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [
|
|
('count', ctypes.c_uint32, 22),
|
|
('reserved_0', ctypes.c_uint32, 10),
|
|
]
|
|
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0),
|
|
('DW_4_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [
|
|
('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION),
|
|
('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION),
|
|
('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION),
|
|
('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION),
|
|
('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION),
|
|
]
|
|
|
|
SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG
|
|
class struct_SDMA_PKT_FENCE_TAG(Structure):
|
|
pass
|
|
|
|
class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_FENCE_TAG_0_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [
|
|
('op', ctypes.c_uint32, 8),
|
|
('sub_op', ctypes.c_uint32, 8),
|
|
('mtype', ctypes.c_uint32, 3),
|
|
('gcc', ctypes.c_uint32, 1),
|
|
('sys', ctypes.c_uint32, 1),
|
|
('pad1', ctypes.c_uint32, 1),
|
|
('snp', ctypes.c_uint32, 1),
|
|
('gpa', ctypes.c_uint32, 1),
|
|
('l2_policy', ctypes.c_uint32, 2),
|
|
('reserved_0', ctypes.c_uint32, 6),
|
|
]
|
|
|
|
union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_FENCE_TAG_0_0),
|
|
('DW_0_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_FENCE_TAG_1_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [
|
|
('addr_31_0', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_FENCE_TAG_1_0),
|
|
('DW_1_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_FENCE_TAG_2_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [
|
|
('addr_63_32', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_FENCE_TAG_2_0),
|
|
('DW_2_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_FENCE_TAG_3_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [
|
|
('data', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_FENCE_TAG_3_0),
|
|
('DW_3_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_FENCE_TAG._fields_ = [
|
|
('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION),
|
|
('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION),
|
|
('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION),
|
|
('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION),
|
|
]
|
|
|
|
SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG
|
|
class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure):
|
|
pass
|
|
|
|
class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [
|
|
('op', ctypes.c_uint32, 8),
|
|
('sub_op', ctypes.c_uint32, 8),
|
|
('reserved_0', ctypes.c_uint32, 10),
|
|
('hdp_flush', ctypes.c_uint32, 1),
|
|
('reserved_1', ctypes.c_uint32, 1),
|
|
('func', ctypes.c_uint32, 3),
|
|
('mem_poll', ctypes.c_uint32, 1),
|
|
]
|
|
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0),
|
|
('DW_0_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [
|
|
('addr_31_0', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0),
|
|
('DW_1_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [
|
|
('addr_63_32', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0),
|
|
('DW_2_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [
|
|
('value', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0),
|
|
('DW_3_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [
|
|
('mask', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0),
|
|
('DW_4_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [
|
|
('interval', ctypes.c_uint32, 16),
|
|
('retry_count', ctypes.c_uint32, 12),
|
|
('reserved_0', ctypes.c_uint32, 4),
|
|
]
|
|
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0),
|
|
('DW_5_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [
|
|
('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION),
|
|
('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION),
|
|
('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION),
|
|
('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION),
|
|
('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION),
|
|
('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION),
|
|
]
|
|
|
|
SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG
|
|
class struct_SDMA_PKT_ATOMIC_TAG(Structure):
|
|
pass
|
|
|
|
class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [
|
|
('op', ctypes.c_uint32, 8),
|
|
('sub_op', ctypes.c_uint32, 8),
|
|
('l', ctypes.c_uint32, 1),
|
|
('reserved_0', ctypes.c_uint32, 8),
|
|
('operation', ctypes.c_uint32, 7),
|
|
]
|
|
|
|
union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0),
|
|
('DW_0_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [
|
|
('addr_31_0', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0),
|
|
('DW_1_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [
|
|
('addr_63_32', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0),
|
|
('DW_2_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [
|
|
('src_data_31_0', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0),
|
|
('DW_3_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [
|
|
('src_data_63_32', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0),
|
|
('DW_4_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [
|
|
('cmp_data_31_0', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0),
|
|
('DW_5_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [
|
|
('cmp_data_63_32', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0),
|
|
('DW_6_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [
|
|
('loop_interval', ctypes.c_uint32, 13),
|
|
('reserved_0', ctypes.c_uint32, 19),
|
|
]
|
|
|
|
union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0),
|
|
('DW_7_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_ATOMIC_TAG._fields_ = [
|
|
('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION),
|
|
('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION),
|
|
('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION),
|
|
('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION),
|
|
('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION),
|
|
('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION),
|
|
('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION),
|
|
('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION),
|
|
]
|
|
|
|
SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG
|
|
class struct_SDMA_PKT_TIMESTAMP_TAG(Structure):
|
|
pass
|
|
|
|
class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [
|
|
('op', ctypes.c_uint32, 8),
|
|
('sub_op', ctypes.c_uint32, 8),
|
|
('reserved_0', ctypes.c_uint32, 16),
|
|
]
|
|
|
|
union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0),
|
|
('DW_0_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [
|
|
('addr_31_0', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0),
|
|
('DW_1_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [
|
|
('addr_63_32', ctypes.c_uint32, 32),
|
|
]
|
|
|
|
union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0),
|
|
('DW_2_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [
|
|
('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION),
|
|
('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION),
|
|
('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION),
|
|
]
|
|
|
|
SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG
|
|
class struct_SDMA_PKT_TRAP_TAG(Structure):
|
|
pass
|
|
|
|
class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_TRAP_TAG_0_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [
|
|
('op', ctypes.c_uint32, 8),
|
|
('sub_op', ctypes.c_uint32, 8),
|
|
('reserved_0', ctypes.c_uint32, 16),
|
|
]
|
|
|
|
union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_TRAP_TAG_0_0),
|
|
('DW_0_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_TRAP_TAG_1_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [
|
|
('int_ctx', ctypes.c_uint32, 28),
|
|
('reserved_1', ctypes.c_uint32, 4),
|
|
]
|
|
|
|
union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_TRAP_TAG_1_0),
|
|
('DW_1_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_TRAP_TAG._fields_ = [
|
|
('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION),
|
|
('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION),
|
|
]
|
|
|
|
SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG
|
|
class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [
|
|
('DW_0_DATA', ctypes.c_uint32),
|
|
('DW_1_DATA', ctypes.c_uint32),
|
|
('DW_2_DATA', ctypes.c_uint32),
|
|
('DW_3_DATA', ctypes.c_uint32),
|
|
('DW_4_DATA', ctypes.c_uint32),
|
|
('DW_5_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG
|
|
hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG
|
|
class struct_SDMA_PKT_GCR_TAG(Structure):
|
|
pass
|
|
|
|
class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_GCR_TAG_0_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [
|
|
('op', ctypes.c_uint32, 8),
|
|
('sub_op', ctypes.c_uint32, 8),
|
|
('_2', ctypes.c_uint32, 16),
|
|
]
|
|
|
|
union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_GCR_TAG_0_0),
|
|
('DW_0_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_GCR_TAG_1_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [
|
|
('_0', ctypes.c_uint32, 7),
|
|
('BaseVA_LO', ctypes.c_uint32, 25),
|
|
]
|
|
|
|
union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_GCR_TAG_1_0),
|
|
('DW_1_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_GCR_TAG_2_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [
|
|
('BaseVA_HI', ctypes.c_uint32, 16),
|
|
('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2),
|
|
('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2),
|
|
('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1),
|
|
('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1),
|
|
('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1),
|
|
('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1),
|
|
('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1),
|
|
('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1),
|
|
('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1),
|
|
('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2),
|
|
('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1),
|
|
('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1),
|
|
('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1),
|
|
]
|
|
|
|
union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_GCR_TAG_2_0),
|
|
('DW_2_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_GCR_TAG_3_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [
|
|
('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1),
|
|
('GCR_CONTROL_SEQ', ctypes.c_uint32, 2),
|
|
('_2', ctypes.c_uint32, 4),
|
|
('LimitVA_LO', ctypes.c_uint32, 25),
|
|
]
|
|
|
|
union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_GCR_TAG_3_0),
|
|
('DW_3_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union):
|
|
pass
|
|
|
|
class struct_SDMA_PKT_GCR_TAG_4_0(Structure):
|
|
pass
|
|
|
|
struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [
|
|
('LimitVA_HI', ctypes.c_uint32, 16),
|
|
('_1', ctypes.c_uint32, 8),
|
|
('VMID', ctypes.c_uint32, 4),
|
|
('_3', ctypes.c_uint32, 4),
|
|
]
|
|
|
|
union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False
|
|
union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',)
|
|
union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [
|
|
('_0', struct_SDMA_PKT_GCR_TAG_4_0),
|
|
('DW_4_DATA', ctypes.c_uint32),
|
|
]
|
|
|
|
struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False
|
|
struct_SDMA_PKT_GCR_TAG._fields_ = [
|
|
('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION),
|
|
('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION),
|
|
('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION),
|
|
('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION),
|
|
('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION),
|
|
]
|
|
|
|
SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG
|
|
NVD_H = True # macro
|
|
PACKET_TYPE0 = 0 # macro
|
|
PACKET_TYPE1 = 1 # macro
|
|
PACKET_TYPE2 = 2 # macro
|
|
PACKET_TYPE3 = 3 # macro
|
|
def CP_PACKET_GET_TYPE(h): # macro
|
|
return (((h)>>30)&3)
|
|
def CP_PACKET_GET_COUNT(h): # macro
|
|
return (((h)>>16)&0x3FFF)
|
|
def CP_PACKET0_GET_REG(h): # macro
|
|
return ((h)&0xFFFF)
|
|
def CP_PACKET3_GET_OPCODE(h): # macro
|
|
return (((h)>>8)&0xFF)
|
|
def PACKET0(reg, n): # macro
|
|
return ((0<<30)|((reg)&0xFFFF)|((n)&0x3FFF)<<16)
|
|
CP_PACKET2 = 0x80000000 # macro
|
|
PACKET2_PAD_SHIFT = 0 # macro
|
|
PACKET2_PAD_MASK = (0x3fffffff<<0) # macro
|
|
# def PACKET2(v): # macro
|
|
# return (0x80000000|REG_SET(PACKET2_PAD,(v)))
|
|
def PACKET3(op, n): # macro
|
|
return ((3<<30)|(((op)&0xFF)<<8)|((n)&0x3FFF)<<16)
|
|
def PACKET3_COMPUTE(op, n): # macro
|
|
return (PACKET3(op,n)|1<<1)
|
|
PACKET3_NOP = 0x10 # macro
|
|
PACKET3_SET_BASE = 0x11 # macro
|
|
def PACKET3_BASE_INDEX(x): # macro
|
|
return ((x)<<0)
|
|
CE_PARTITION_BASE = 3 # macro
|
|
PACKET3_CLEAR_STATE = 0x12 # macro
|
|
PACKET3_INDEX_BUFFER_SIZE = 0x13 # macro
|
|
PACKET3_DISPATCH_DIRECT = 0x15 # macro
|
|
PACKET3_DISPATCH_INDIRECT = 0x16 # macro
|
|
PACKET3_INDIRECT_BUFFER_END = 0x17 # macro
|
|
PACKET3_INDIRECT_BUFFER_CNST_END = 0x19 # macro
|
|
PACKET3_ATOMIC_GDS = 0x1D # macro
|
|
PACKET3_ATOMIC_MEM = 0x1E # macro
|
|
PACKET3_OCCLUSION_QUERY = 0x1F # macro
|
|
PACKET3_SET_PREDICATION = 0x20 # macro
|
|
PACKET3_REG_RMW = 0x21 # macro
|
|
PACKET3_COND_EXEC = 0x22 # macro
|
|
PACKET3_PRED_EXEC = 0x23 # macro
|
|
PACKET3_DRAW_INDIRECT = 0x24 # macro
|
|
PACKET3_DRAW_INDEX_INDIRECT = 0x25 # macro
|
|
PACKET3_INDEX_BASE = 0x26 # macro
|
|
PACKET3_DRAW_INDEX_2 = 0x27 # macro
|
|
PACKET3_CONTEXT_CONTROL = 0x28 # macro
|
|
PACKET3_INDEX_TYPE = 0x2A # macro
|
|
PACKET3_DRAW_INDIRECT_MULTI = 0x2C # macro
|
|
PACKET3_DRAW_INDEX_AUTO = 0x2D # macro
|
|
PACKET3_NUM_INSTANCES = 0x2F # macro
|
|
PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30 # macro
|
|
PACKET3_INDIRECT_BUFFER_PRIV = 0x32 # macro
|
|
PACKET3_INDIRECT_BUFFER_CNST = 0x33 # macro
|
|
PACKET3_COND_INDIRECT_BUFFER_CNST = 0x33 # macro
|
|
PACKET3_STRMOUT_BUFFER_UPDATE = 0x34 # macro
|
|
PACKET3_DRAW_INDEX_OFFSET_2 = 0x35 # macro
|
|
PACKET3_DRAW_PREAMBLE = 0x36 # macro
|
|
PACKET3_WRITE_DATA = 0x37 # macro
|
|
def WRITE_DATA_DST_SEL(x): # macro
|
|
return ((x)<<8)
|
|
WR_ONE_ADDR = (1<<16) # macro
|
|
WR_CONFIRM = (1<<20) # macro
|
|
def WRITE_DATA_CACHE_POLICY(x): # macro
|
|
return ((x)<<25)
|
|
def WRITE_DATA_ENGINE_SEL(x): # macro
|
|
return ((x)<<30)
|
|
PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38 # macro
|
|
PACKET3_MEM_SEMAPHORE = 0x39 # macro
|
|
PACKET3_SEM_USE_MAILBOX = (0x1<<16) # macro
|
|
PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1<<20) # macro
|
|
PACKET3_SEM_SEL_SIGNAL = (0x6<<29) # macro
|
|
PACKET3_SEM_SEL_WAIT = (0x7<<29) # macro
|
|
PACKET3_DRAW_INDEX_MULTI_INST = 0x3A # macro
|
|
PACKET3_COPY_DW = 0x3B # macro
|
|
PACKET3_WAIT_REG_MEM = 0x3C # macro
|
|
def WAIT_REG_MEM_FUNCTION(x): # macro
|
|
return ((x)<<0)
|
|
def WAIT_REG_MEM_MEM_SPACE(x): # macro
|
|
return ((x)<<4)
|
|
def WAIT_REG_MEM_OPERATION(x): # macro
|
|
return ((x)<<6)
|
|
def WAIT_REG_MEM_ENGINE(x): # macro
|
|
return ((x)<<8)
|
|
PACKET3_INDIRECT_BUFFER = 0x3F # macro
|
|
INDIRECT_BUFFER_VALID = (1<<23) # macro
|
|
def INDIRECT_BUFFER_CACHE_POLICY(x): # macro
|
|
return ((x)<<28)
|
|
def INDIRECT_BUFFER_PRE_ENB(x): # macro
|
|
return ((x)<<21)
|
|
def INDIRECT_BUFFER_PRE_RESUME(x): # macro
|
|
return ((x)<<30)
|
|
PACKET3_COND_INDIRECT_BUFFER = 0x3F # macro
|
|
PACKET3_COPY_DATA = 0x40 # macro
|
|
PACKET3_CP_DMA = 0x41 # macro
|
|
PACKET3_PFP_SYNC_ME = 0x42 # macro
|
|
PACKET3_SURFACE_SYNC = 0x43 # macro
|
|
PACKET3_ME_INITIALIZE = 0x44 # macro
|
|
PACKET3_COND_WRITE = 0x45 # macro
|
|
PACKET3_EVENT_WRITE = 0x46 # macro
|
|
def EVENT_TYPE(x): # macro
|
|
return ((x)<<0)
|
|
def EVENT_INDEX(x): # macro
|
|
return ((x)<<8)
|
|
PACKET3_EVENT_WRITE_EOP = 0x47 # macro
|
|
PACKET3_EVENT_WRITE_EOS = 0x48 # macro
|
|
PACKET3_RELEASE_MEM = 0x49 # macro
|
|
def PACKET3_RELEASE_MEM_EVENT_TYPE(x): # macro
|
|
return ((x)<<0)
|
|
def PACKET3_RELEASE_MEM_EVENT_INDEX(x): # macro
|
|
return ((x)<<8)
|
|
PACKET3_RELEASE_MEM_GCR_GLM_WB = (1<<12) # macro
|
|
PACKET3_RELEASE_MEM_GCR_GLM_INV = (1<<13) # macro
|
|
PACKET3_RELEASE_MEM_GCR_GLV_INV = (1<<14) # macro
|
|
PACKET3_RELEASE_MEM_GCR_GL1_INV = (1<<15) # macro
|
|
PACKET3_RELEASE_MEM_GCR_GL2_US = (1<<16) # macro
|
|
PACKET3_RELEASE_MEM_GCR_GL2_RANGE = (1<<17) # macro
|
|
PACKET3_RELEASE_MEM_GCR_GL2_DISCARD = (1<<19) # macro
|
|
PACKET3_RELEASE_MEM_GCR_GL2_INV = (1<<20) # macro
|
|
PACKET3_RELEASE_MEM_GCR_GL2_WB = (1<<21) # macro
|
|
PACKET3_RELEASE_MEM_GCR_SEQ = (1<<22) # macro
|
|
def PACKET3_RELEASE_MEM_CACHE_POLICY(x): # macro
|
|
return ((x)<<25)
|
|
PACKET3_RELEASE_MEM_EXECUTE = (1<<28) # macro
|
|
def PACKET3_RELEASE_MEM_DATA_SEL(x): # macro
|
|
return ((x)<<29)
|
|
def PACKET3_RELEASE_MEM_INT_SEL(x): # macro
|
|
return ((x)<<24)
|
|
def PACKET3_RELEASE_MEM_DST_SEL(x): # macro
|
|
return ((x)<<16)
|
|
PACKET3_PREAMBLE_CNTL = 0x4A # macro
|
|
PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2<<28) # macro
|
|
PACKET3_PREAMBLE_END_CLEAR_STATE = (3<<28) # macro
|
|
PACKET3_DMA_DATA = 0x50 # macro
|
|
def PACKET3_DMA_DATA_ENGINE(x): # macro
|
|
return ((x)<<0)
|
|
def PACKET3_DMA_DATA_SRC_CACHE_POLICY(x): # macro
|
|
return ((x)<<13)
|
|
def PACKET3_DMA_DATA_DST_SEL(x): # macro
|
|
return ((x)<<20)
|
|
def PACKET3_DMA_DATA_DST_CACHE_POLICY(x): # macro
|
|
return ((x)<<25)
|
|
def PACKET3_DMA_DATA_SRC_SEL(x): # macro
|
|
return ((x)<<29)
|
|
PACKET3_DMA_DATA_CP_SYNC = (1<<31) # macro
|
|
PACKET3_DMA_DATA_CMD_SAS = (1<<26) # macro
|
|
PACKET3_DMA_DATA_CMD_DAS = (1<<27) # macro
|
|
PACKET3_DMA_DATA_CMD_SAIC = (1<<28) # macro
|
|
PACKET3_DMA_DATA_CMD_DAIC = (1<<29) # macro
|
|
PACKET3_DMA_DATA_CMD_RAW_WAIT = (1<<30) # macro
|
|
PACKET3_CONTEXT_REG_RMW = 0x51 # macro
|
|
PACKET3_GFX_CNTX_UPDATE = 0x52 # macro
|
|
PACKET3_BLK_CNTX_UPDATE = 0x53 # macro
|
|
PACKET3_INCR_UPDT_STATE = 0x55 # macro
|
|
PACKET3_ACQUIRE_MEM = 0x58 # macro
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x): # macro
|
|
return ((x)<<0)
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x): # macro
|
|
return ((x)<<2)
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x): # macro
|
|
return ((x)<<4)
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x): # macro
|
|
return ((x)<<5)
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x): # macro
|
|
return ((x)<<6)
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x): # macro
|
|
return ((x)<<7)
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x): # macro
|
|
return ((x)<<8)
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x): # macro
|
|
return ((x)<<9)
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x): # macro
|
|
return ((x)<<10)
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x): # macro
|
|
return ((x)<<11)
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x): # macro
|
|
return ((x)<<13)
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x): # macro
|
|
return ((x)<<14)
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x): # macro
|
|
return ((x)<<15)
|
|
def PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x): # macro
|
|
return ((x)<<16)
|
|
PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA = (1<<18) # macro
|
|
PACKET3_REWIND = 0x59 # macro
|
|
PACKET3_INTERRUPT = 0x5A # macro
|
|
PACKET3_GEN_PDEPTE = 0x5B # macro
|
|
PACKET3_INDIRECT_BUFFER_PASID = 0x5C # macro
|
|
PACKET3_PRIME_UTCL2 = 0x5D # macro
|
|
PACKET3_LOAD_UCONFIG_REG = 0x5E # macro
|
|
PACKET3_LOAD_SH_REG = 0x5F # macro
|
|
PACKET3_LOAD_CONFIG_REG = 0x60 # macro
|
|
PACKET3_LOAD_CONTEXT_REG = 0x61 # macro
|
|
PACKET3_LOAD_COMPUTE_STATE = 0x62 # macro
|
|
PACKET3_LOAD_SH_REG_INDEX = 0x63 # macro
|
|
PACKET3_SET_CONFIG_REG = 0x68 # macro
|
|
PACKET3_SET_CONFIG_REG_START = 0x00002000 # macro
|
|
PACKET3_SET_CONFIG_REG_END = 0x00002c00 # macro
|
|
PACKET3_SET_CONTEXT_REG = 0x69 # macro
|
|
PACKET3_SET_CONTEXT_REG_START = 0x0000a000 # macro
|
|
PACKET3_SET_CONTEXT_REG_END = 0x0000a400 # macro
|
|
PACKET3_SET_CONTEXT_REG_INDEX = 0x6A # macro
|
|
PACKET3_SET_VGPR_REG_DI_MULTI = 0x71 # macro
|
|
PACKET3_SET_SH_REG_DI = 0x72 # macro
|
|
PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73 # macro
|
|
PACKET3_SET_SH_REG_DI_MULTI = 0x74 # macro
|
|
PACKET3_GFX_PIPE_LOCK = 0x75 # macro
|
|
PACKET3_SET_SH_REG = 0x76 # macro
|
|
PACKET3_SET_SH_REG_START = 0x00002c00 # macro
|
|
PACKET3_SET_SH_REG_END = 0x00003000 # macro
|
|
PACKET3_SET_SH_REG_OFFSET = 0x77 # macro
|
|
PACKET3_SET_QUEUE_REG = 0x78 # macro
|
|
PACKET3_SET_UCONFIG_REG = 0x79 # macro
|
|
PACKET3_SET_UCONFIG_REG_START = 0x0000c000 # macro
|
|
PACKET3_SET_UCONFIG_REG_END = 0x0000c400 # macro
|
|
PACKET3_SET_UCONFIG_REG_INDEX = 0x7A # macro
|
|
PACKET3_FORWARD_HEADER = 0x7C # macro
|
|
PACKET3_SCRATCH_RAM_WRITE = 0x7D # macro
|
|
PACKET3_SCRATCH_RAM_READ = 0x7E # macro
|
|
PACKET3_LOAD_CONST_RAM = 0x80 # macro
|
|
PACKET3_WRITE_CONST_RAM = 0x81 # macro
|
|
PACKET3_DUMP_CONST_RAM = 0x83 # macro
|
|
PACKET3_INCREMENT_CE_COUNTER = 0x84 # macro
|
|
PACKET3_INCREMENT_DE_COUNTER = 0x85 # macro
|
|
PACKET3_WAIT_ON_CE_COUNTER = 0x86 # macro
|
|
PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88 # macro
|
|
PACKET3_SWITCH_BUFFER = 0x8B # macro
|
|
PACKET3_DISPATCH_DRAW_PREAMBLE = 0x8C # macro
|
|
PACKET3_DISPATCH_DRAW_PREAMBLE_ACE = 0x8C # macro
|
|
PACKET3_DISPATCH_DRAW = 0x8D # macro
|
|
PACKET3_DISPATCH_DRAW_ACE = 0x8D # macro
|
|
PACKET3_GET_LOD_STATS = 0x8E # macro
|
|
PACKET3_DRAW_MULTI_PREAMBLE = 0x8F # macro
|
|
PACKET3_FRAME_CONTROL = 0x90 # macro
|
|
FRAME_TMZ = (1<<0) # macro
|
|
def FRAME_CMD(x): # macro
|
|
return ((x)<<28)
|
|
PACKET3_INDEX_ATTRIBUTES_INDIRECT = 0x91 # macro
|
|
PACKET3_WAIT_REG_MEM64 = 0x93 # macro
|
|
PACKET3_COND_PREEMPT = 0x94 # macro
|
|
PACKET3_HDP_FLUSH = 0x95 # macro
|
|
PACKET3_COPY_DATA_RB = 0x96 # macro
|
|
PACKET3_INVALIDATE_TLBS = 0x98 # macro
|
|
def PACKET3_INVALIDATE_TLBS_DST_SEL(x): # macro
|
|
return ((x)<<0)
|
|
def PACKET3_INVALIDATE_TLBS_ALL_HUB(x): # macro
|
|
return ((x)<<4)
|
|
def PACKET3_INVALIDATE_TLBS_PASID(x): # macro
|
|
return ((x)<<5)
|
|
PACKET3_AQL_PACKET = 0x99 # macro
|
|
PACKET3_DMA_DATA_FILL_MULTI = 0x9A # macro
|
|
PACKET3_SET_SH_REG_INDEX = 0x9B # macro
|
|
PACKET3_DRAW_INDIRECT_COUNT_MULTI = 0x9C # macro
|
|
PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI = 0x9D # macro
|
|
PACKET3_DUMP_CONST_RAM_OFFSET = 0x9E # macro
|
|
PACKET3_LOAD_CONTEXT_REG_INDEX = 0x9F # macro
|
|
PACKET3_SET_RESOURCES = 0xA0 # macro
|
|
def PACKET3_SET_RESOURCES_VMID_MASK(x): # macro
|
|
return ((x)<<0)
|
|
def PACKET3_SET_RESOURCES_UNMAP_LATENTY(x): # macro
|
|
return ((x)<<16)
|
|
def PACKET3_SET_RESOURCES_QUEUE_TYPE(x): # macro
|
|
return ((x)<<29)
|
|
PACKET3_MAP_PROCESS = 0xA1 # macro
|
|
PACKET3_MAP_QUEUES = 0xA2 # macro
|
|
def PACKET3_MAP_QUEUES_QUEUE_SEL(x): # macro
|
|
return ((x)<<4)
|
|
def PACKET3_MAP_QUEUES_VMID(x): # macro
|
|
return ((x)<<8)
|
|
def PACKET3_MAP_QUEUES_QUEUE(x): # macro
|
|
return ((x)<<13)
|
|
def PACKET3_MAP_QUEUES_PIPE(x): # macro
|
|
return ((x)<<16)
|
|
def PACKET3_MAP_QUEUES_ME(x): # macro
|
|
return ((x)<<18)
|
|
def PACKET3_MAP_QUEUES_QUEUE_TYPE(x): # macro
|
|
return ((x)<<21)
|
|
def PACKET3_MAP_QUEUES_ALLOC_FORMAT(x): # macro
|
|
return ((x)<<24)
|
|
def PACKET3_MAP_QUEUES_ENGINE_SEL(x): # macro
|
|
return ((x)<<26)
|
|
def PACKET3_MAP_QUEUES_NUM_QUEUES(x): # macro
|
|
return ((x)<<29)
|
|
def PACKET3_MAP_QUEUES_CHECK_DISABLE(x): # macro
|
|
return ((x)<<1)
|
|
def PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x): # macro
|
|
return ((x)<<2)
|
|
PACKET3_UNMAP_QUEUES = 0xA3 # macro
|
|
def PACKET3_UNMAP_QUEUES_ACTION(x): # macro
|
|
return ((x)<<0)
|
|
def PACKET3_UNMAP_QUEUES_QUEUE_SEL(x): # macro
|
|
return ((x)<<4)
|
|
def PACKET3_UNMAP_QUEUES_ENGINE_SEL(x): # macro
|
|
return ((x)<<26)
|
|
def PACKET3_UNMAP_QUEUES_NUM_QUEUES(x): # macro
|
|
return ((x)<<29)
|
|
def PACKET3_UNMAP_QUEUES_PASID(x): # macro
|
|
return ((x)<<0)
|
|
def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x): # macro
|
|
return ((x)<<2)
|
|
def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x): # macro
|
|
return ((x)<<2)
|
|
def PACKET3_UNMAP_QUEUES_RB_WPTR(x): # macro
|
|
return ((x)<<0)
|
|
def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x): # macro
|
|
return ((x)<<2)
|
|
def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x): # macro
|
|
return ((x)<<2)
|
|
PACKET3_QUERY_STATUS = 0xA4 # macro
|
|
def PACKET3_QUERY_STATUS_CONTEXT_ID(x): # macro
|
|
return ((x)<<0)
|
|
def PACKET3_QUERY_STATUS_INTERRUPT_SEL(x): # macro
|
|
return ((x)<<28)
|
|
def PACKET3_QUERY_STATUS_COMMAND(x): # macro
|
|
return ((x)<<30)
|
|
def PACKET3_QUERY_STATUS_PASID(x): # macro
|
|
return ((x)<<0)
|
|
def PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x): # macro
|
|
return ((x)<<2)
|
|
def PACKET3_QUERY_STATUS_ENG_SEL(x): # macro
|
|
return ((x)<<25)
|
|
PACKET3_RUN_LIST = 0xA5 # macro
|
|
PACKET3_MAP_PROCESS_VM = 0xA6 # macro
|
|
PACKET3_SET_Q_PREEMPTION_MODE = 0xF0 # macro
|
|
def PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x): # macro
|
|
return ((x)<<0)
|
|
PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM = (1<<0) # macro
|
|
_gc_11_0_0_OFFSET_HEADER = True # macro
|
|
regSDMA0_DEC_START = 0x0000 # macro
|
|
regSDMA0_DEC_START_BASE_IDX = 0 # macro
|
|
regSDMA0_F32_MISC_CNTL = 0x000b # macro
|
|
regSDMA0_F32_MISC_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_GLOBAL_TIMESTAMP_LO = 0x000f # macro
|
|
regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_GLOBAL_TIMESTAMP_HI = 0x0010 # macro
|
|
regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_POWER_CNTL = 0x001a # macro
|
|
regSDMA0_POWER_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_CNTL = 0x001c # macro
|
|
regSDMA0_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_CHICKEN_BITS = 0x001d # macro
|
|
regSDMA0_CHICKEN_BITS_BASE_IDX = 0 # macro
|
|
regSDMA0_GB_ADDR_CONFIG = 0x001e # macro
|
|
regSDMA0_GB_ADDR_CONFIG_BASE_IDX = 0 # macro
|
|
regSDMA0_GB_ADDR_CONFIG_READ = 0x001f # macro
|
|
regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro
|
|
regSDMA0_RB_RPTR_FETCH = 0x0020 # macro
|
|
regSDMA0_RB_RPTR_FETCH_BASE_IDX = 0 # macro
|
|
regSDMA0_RB_RPTR_FETCH_HI = 0x0021 # macro
|
|
regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL = 0x0022 # macro
|
|
regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_IB_OFFSET_FETCH = 0x0023 # macro
|
|
regSDMA0_IB_OFFSET_FETCH_BASE_IDX = 0 # macro
|
|
regSDMA0_PROGRAM = 0x0024 # macro
|
|
regSDMA0_PROGRAM_BASE_IDX = 0 # macro
|
|
regSDMA0_STATUS_REG = 0x0025 # macro
|
|
regSDMA0_STATUS_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_STATUS1_REG = 0x0026 # macro
|
|
regSDMA0_STATUS1_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_CNTL1 = 0x0027 # macro
|
|
regSDMA0_CNTL1_BASE_IDX = 0 # macro
|
|
regSDMA0_HBM_PAGE_CONFIG = 0x0028 # macro
|
|
regSDMA0_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro
|
|
regSDMA0_UCODE_CHECKSUM = 0x0029 # macro
|
|
regSDMA0_UCODE_CHECKSUM_BASE_IDX = 0 # macro
|
|
regSDMA0_FREEZE = 0x002b # macro
|
|
regSDMA0_FREEZE_BASE_IDX = 0 # macro
|
|
regSDMA0_PROCESS_QUANTUM0 = 0x002c # macro
|
|
regSDMA0_PROCESS_QUANTUM0_BASE_IDX = 0 # macro
|
|
regSDMA0_PROCESS_QUANTUM1 = 0x002d # macro
|
|
regSDMA0_PROCESS_QUANTUM1_BASE_IDX = 0 # macro
|
|
regSDMA0_WATCHDOG_CNTL = 0x002e # macro
|
|
regSDMA0_WATCHDOG_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE_STATUS0 = 0x002f # macro
|
|
regSDMA0_QUEUE_STATUS0_BASE_IDX = 0 # macro
|
|
regSDMA0_EDC_CONFIG = 0x0032 # macro
|
|
regSDMA0_EDC_CONFIG_BASE_IDX = 0 # macro
|
|
regSDMA0_BA_THRESHOLD = 0x0033 # macro
|
|
regSDMA0_BA_THRESHOLD_BASE_IDX = 0 # macro
|
|
regSDMA0_ID = 0x0034 # macro
|
|
regSDMA0_ID_BASE_IDX = 0 # macro
|
|
regSDMA0_VERSION = 0x0035 # macro
|
|
regSDMA0_VERSION_BASE_IDX = 0 # macro
|
|
regSDMA0_EDC_COUNTER = 0x0036 # macro
|
|
regSDMA0_EDC_COUNTER_BASE_IDX = 0 # macro
|
|
regSDMA0_EDC_COUNTER_CLEAR = 0x0037 # macro
|
|
regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro
|
|
regSDMA0_STATUS2_REG = 0x0038 # macro
|
|
regSDMA0_STATUS2_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_ATOMIC_CNTL = 0x0039 # macro
|
|
regSDMA0_ATOMIC_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_ATOMIC_PREOP_LO = 0x003a # macro
|
|
regSDMA0_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_ATOMIC_PREOP_HI = 0x003b # macro
|
|
regSDMA0_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_UTCL1_CNTL = 0x003c # macro
|
|
regSDMA0_UTCL1_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_UTCL1_WATERMK = 0x003d # macro
|
|
regSDMA0_UTCL1_WATERMK_BASE_IDX = 0 # macro
|
|
regSDMA0_UTCL1_TIMEOUT = 0x003e # macro
|
|
regSDMA0_UTCL1_TIMEOUT_BASE_IDX = 0 # macro
|
|
regSDMA0_UTCL1_PAGE = 0x003f # macro
|
|
regSDMA0_UTCL1_PAGE_BASE_IDX = 0 # macro
|
|
regSDMA0_UTCL1_RD_STATUS = 0x0040 # macro
|
|
regSDMA0_UTCL1_RD_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_UTCL1_WR_STATUS = 0x0041 # macro
|
|
regSDMA0_UTCL1_WR_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_UTCL1_INV0 = 0x0042 # macro
|
|
regSDMA0_UTCL1_INV0_BASE_IDX = 0 # macro
|
|
regSDMA0_UTCL1_INV1 = 0x0043 # macro
|
|
regSDMA0_UTCL1_INV1_BASE_IDX = 0 # macro
|
|
regSDMA0_UTCL1_INV2 = 0x0044 # macro
|
|
regSDMA0_UTCL1_INV2_BASE_IDX = 0 # macro
|
|
regSDMA0_UTCL1_RD_XNACK0 = 0x0045 # macro
|
|
regSDMA0_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro
|
|
regSDMA0_UTCL1_RD_XNACK1 = 0x0046 # macro
|
|
regSDMA0_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro
|
|
regSDMA0_UTCL1_WR_XNACK0 = 0x0047 # macro
|
|
regSDMA0_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro
|
|
regSDMA0_UTCL1_WR_XNACK1 = 0x0048 # macro
|
|
regSDMA0_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro
|
|
regSDMA0_RELAX_ORDERING_LUT = 0x004a # macro
|
|
regSDMA0_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro
|
|
regSDMA0_CHICKEN_BITS_2 = 0x004b # macro
|
|
regSDMA0_CHICKEN_BITS_2_BASE_IDX = 0 # macro
|
|
regSDMA0_STATUS3_REG = 0x004c # macro
|
|
regSDMA0_STATUS3_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_PHYSICAL_ADDR_LO = 0x004d # macro
|
|
regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_PHYSICAL_ADDR_HI = 0x004e # macro
|
|
regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_GLOBAL_QUANTUM = 0x004f # macro
|
|
regSDMA0_GLOBAL_QUANTUM_BASE_IDX = 0 # macro
|
|
regSDMA0_ERROR_LOG = 0x0050 # macro
|
|
regSDMA0_ERROR_LOG_BASE_IDX = 0 # macro
|
|
regSDMA0_PUB_DUMMY_REG0 = 0x0051 # macro
|
|
regSDMA0_PUB_DUMMY_REG0_BASE_IDX = 0 # macro
|
|
regSDMA0_PUB_DUMMY_REG1 = 0x0052 # macro
|
|
regSDMA0_PUB_DUMMY_REG1_BASE_IDX = 0 # macro
|
|
regSDMA0_PUB_DUMMY_REG2 = 0x0053 # macro
|
|
regSDMA0_PUB_DUMMY_REG2_BASE_IDX = 0 # macro
|
|
regSDMA0_PUB_DUMMY_REG3 = 0x0054 # macro
|
|
regSDMA0_PUB_DUMMY_REG3_BASE_IDX = 0 # macro
|
|
regSDMA0_F32_COUNTER = 0x0055 # macro
|
|
regSDMA0_F32_COUNTER_BASE_IDX = 0 # macro
|
|
regSDMA0_CRD_CNTL = 0x005b # macro
|
|
regSDMA0_CRD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_RLC_CGCG_CTRL = 0x005c # macro
|
|
regSDMA0_RLC_CGCG_CTRL_BASE_IDX = 0 # macro
|
|
regSDMA0_AQL_STATUS = 0x005f # macro
|
|
regSDMA0_AQL_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_EA_DBIT_ADDR_DATA = 0x0060 # macro
|
|
regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro
|
|
regSDMA0_EA_DBIT_ADDR_INDEX = 0x0061 # macro
|
|
regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro
|
|
regSDMA0_TLBI_GCR_CNTL = 0x0062 # macro
|
|
regSDMA0_TLBI_GCR_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_TILING_CONFIG = 0x0063 # macro
|
|
regSDMA0_TILING_CONFIG_BASE_IDX = 0 # macro
|
|
regSDMA0_INT_STATUS = 0x0070 # macro
|
|
regSDMA0_INT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_HOLE_ADDR_LO = 0x0072 # macro
|
|
regSDMA0_HOLE_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_HOLE_ADDR_HI = 0x0073 # macro
|
|
regSDMA0_HOLE_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_CLOCK_GATING_STATUS = 0x0075 # macro
|
|
regSDMA0_CLOCK_GATING_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_STATUS4_REG = 0x0076 # macro
|
|
regSDMA0_STATUS4_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_SCRATCH_RAM_DATA = 0x0077 # macro
|
|
regSDMA0_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro
|
|
regSDMA0_SCRATCH_RAM_ADDR = 0x0078 # macro
|
|
regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro
|
|
regSDMA0_TIMESTAMP_CNTL = 0x0079 # macro
|
|
regSDMA0_TIMESTAMP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_STATUS5_REG = 0x007a # macro
|
|
regSDMA0_STATUS5_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE_RESET_REQ = 0x007b # macro
|
|
regSDMA0_QUEUE_RESET_REQ_BASE_IDX = 0 # macro
|
|
regSDMA0_STATUS6_REG = 0x007c # macro
|
|
regSDMA0_STATUS6_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_UCODE1_CHECKSUM = 0x007d # macro
|
|
regSDMA0_UCODE1_CHECKSUM_BASE_IDX = 0 # macro
|
|
regSDMA0_CE_CTRL = 0x007e # macro
|
|
regSDMA0_CE_CTRL_BASE_IDX = 0 # macro
|
|
regSDMA0_FED_STATUS = 0x007f # macro
|
|
regSDMA0_FED_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_RB_CNTL = 0x0080 # macro
|
|
regSDMA0_QUEUE0_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_RB_BASE = 0x0081 # macro
|
|
regSDMA0_QUEUE0_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_RB_BASE_HI = 0x0082 # macro
|
|
regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_RB_RPTR = 0x0083 # macro
|
|
regSDMA0_QUEUE0_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_RB_RPTR_HI = 0x0084 # macro
|
|
regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_RB_WPTR = 0x0085 # macro
|
|
regSDMA0_QUEUE0_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_RB_WPTR_HI = 0x0086 # macro
|
|
regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_RB_RPTR_ADDR_HI = 0x0088 # macro
|
|
regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_RB_RPTR_ADDR_LO = 0x0089 # macro
|
|
regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_IB_CNTL = 0x008a # macro
|
|
regSDMA0_QUEUE0_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_IB_RPTR = 0x008b # macro
|
|
regSDMA0_QUEUE0_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_IB_OFFSET = 0x008c # macro
|
|
regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_IB_BASE_LO = 0x008d # macro
|
|
regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_IB_BASE_HI = 0x008e # macro
|
|
regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_IB_SIZE = 0x008f # macro
|
|
regSDMA0_QUEUE0_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_SKIP_CNTL = 0x0090 # macro
|
|
regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_CONTEXT_STATUS = 0x0091 # macro
|
|
regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_DOORBELL = 0x0092 # macro
|
|
regSDMA0_QUEUE0_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_DOORBELL_LOG = 0x00a9 # macro
|
|
regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_DOORBELL_OFFSET = 0x00ab # macro
|
|
regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_CSA_ADDR_LO = 0x00ac # macro
|
|
regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_CSA_ADDR_HI = 0x00ad # macro
|
|
regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_SCHEDULE_CNTL = 0x00ae # macro
|
|
regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_IB_SUB_REMAIN = 0x00af # macro
|
|
regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_PREEMPT = 0x00b0 # macro
|
|
regSDMA0_QUEUE0_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_DUMMY_REG = 0x00b1 # macro
|
|
regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI = 0x00b2 # macro
|
|
regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO = 0x00b3 # macro
|
|
regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_RB_AQL_CNTL = 0x00b4 # macro
|
|
regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_MINOR_PTR_UPDATE = 0x00b5 # macro
|
|
regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_RB_PREEMPT = 0x00b6 # macro
|
|
regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA0 = 0x00c0 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA1 = 0x00c1 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA2 = 0x00c2 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA3 = 0x00c3 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA4 = 0x00c4 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA5 = 0x00c5 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA6 = 0x00c6 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA7 = 0x00c7 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA8 = 0x00c8 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA9 = 0x00c9 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA10 = 0x00ca # macro
|
|
regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE0_MIDCMD_CNTL = 0x00cb # macro
|
|
regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_RB_CNTL = 0x00d8 # macro
|
|
regSDMA0_QUEUE1_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_RB_BASE = 0x00d9 # macro
|
|
regSDMA0_QUEUE1_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_RB_BASE_HI = 0x00da # macro
|
|
regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_RB_RPTR = 0x00db # macro
|
|
regSDMA0_QUEUE1_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_RB_RPTR_HI = 0x00dc # macro
|
|
regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_RB_WPTR = 0x00dd # macro
|
|
regSDMA0_QUEUE1_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_RB_WPTR_HI = 0x00de # macro
|
|
regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_RB_RPTR_ADDR_HI = 0x00e0 # macro
|
|
regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_RB_RPTR_ADDR_LO = 0x00e1 # macro
|
|
regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_IB_CNTL = 0x00e2 # macro
|
|
regSDMA0_QUEUE1_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_IB_RPTR = 0x00e3 # macro
|
|
regSDMA0_QUEUE1_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_IB_OFFSET = 0x00e4 # macro
|
|
regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_IB_BASE_LO = 0x00e5 # macro
|
|
regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_IB_BASE_HI = 0x00e6 # macro
|
|
regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_IB_SIZE = 0x00e7 # macro
|
|
regSDMA0_QUEUE1_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_SKIP_CNTL = 0x00e8 # macro
|
|
regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_CONTEXT_STATUS = 0x00e9 # macro
|
|
regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_DOORBELL = 0x00ea # macro
|
|
regSDMA0_QUEUE1_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_DOORBELL_LOG = 0x0101 # macro
|
|
regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_DOORBELL_OFFSET = 0x0103 # macro
|
|
regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_CSA_ADDR_LO = 0x0104 # macro
|
|
regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_CSA_ADDR_HI = 0x0105 # macro
|
|
regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_SCHEDULE_CNTL = 0x0106 # macro
|
|
regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_IB_SUB_REMAIN = 0x0107 # macro
|
|
regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_PREEMPT = 0x0108 # macro
|
|
regSDMA0_QUEUE1_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_DUMMY_REG = 0x0109 # macro
|
|
regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI = 0x010a # macro
|
|
regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO = 0x010b # macro
|
|
regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_RB_AQL_CNTL = 0x010c # macro
|
|
regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_MINOR_PTR_UPDATE = 0x010d # macro
|
|
regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_RB_PREEMPT = 0x010e # macro
|
|
regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA0 = 0x0118 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA1 = 0x0119 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA2 = 0x011a # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA3 = 0x011b # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA4 = 0x011c # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA5 = 0x011d # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA6 = 0x011e # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA7 = 0x011f # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA8 = 0x0120 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA9 = 0x0121 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA10 = 0x0122 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_CNTL = 0x0123 # macro
|
|
regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_RB_CNTL = 0x0130 # macro
|
|
regSDMA0_QUEUE2_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_RB_BASE = 0x0131 # macro
|
|
regSDMA0_QUEUE2_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_RB_BASE_HI = 0x0132 # macro
|
|
regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_RB_RPTR = 0x0133 # macro
|
|
regSDMA0_QUEUE2_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_RB_RPTR_HI = 0x0134 # macro
|
|
regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_RB_WPTR = 0x0135 # macro
|
|
regSDMA0_QUEUE2_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_RB_WPTR_HI = 0x0136 # macro
|
|
regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_RB_RPTR_ADDR_HI = 0x0138 # macro
|
|
regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_RB_RPTR_ADDR_LO = 0x0139 # macro
|
|
regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_IB_CNTL = 0x013a # macro
|
|
regSDMA0_QUEUE2_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_IB_RPTR = 0x013b # macro
|
|
regSDMA0_QUEUE2_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_IB_OFFSET = 0x013c # macro
|
|
regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_IB_BASE_LO = 0x013d # macro
|
|
regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_IB_BASE_HI = 0x013e # macro
|
|
regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_IB_SIZE = 0x013f # macro
|
|
regSDMA0_QUEUE2_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_SKIP_CNTL = 0x0140 # macro
|
|
regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_CONTEXT_STATUS = 0x0141 # macro
|
|
regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_DOORBELL = 0x0142 # macro
|
|
regSDMA0_QUEUE2_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_DOORBELL_LOG = 0x0159 # macro
|
|
regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_DOORBELL_OFFSET = 0x015b # macro
|
|
regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_CSA_ADDR_LO = 0x015c # macro
|
|
regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_CSA_ADDR_HI = 0x015d # macro
|
|
regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_SCHEDULE_CNTL = 0x015e # macro
|
|
regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_IB_SUB_REMAIN = 0x015f # macro
|
|
regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_PREEMPT = 0x0160 # macro
|
|
regSDMA0_QUEUE2_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_DUMMY_REG = 0x0161 # macro
|
|
regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI = 0x0162 # macro
|
|
regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO = 0x0163 # macro
|
|
regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_RB_AQL_CNTL = 0x0164 # macro
|
|
regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_MINOR_PTR_UPDATE = 0x0165 # macro
|
|
regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_RB_PREEMPT = 0x0166 # macro
|
|
regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA0 = 0x0170 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA1 = 0x0171 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA2 = 0x0172 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA3 = 0x0173 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA4 = 0x0174 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA5 = 0x0175 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA6 = 0x0176 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA7 = 0x0177 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA8 = 0x0178 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA9 = 0x0179 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA10 = 0x017a # macro
|
|
regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE2_MIDCMD_CNTL = 0x017b # macro
|
|
regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_RB_CNTL = 0x0188 # macro
|
|
regSDMA0_QUEUE3_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_RB_BASE = 0x0189 # macro
|
|
regSDMA0_QUEUE3_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_RB_BASE_HI = 0x018a # macro
|
|
regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_RB_RPTR = 0x018b # macro
|
|
regSDMA0_QUEUE3_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_RB_RPTR_HI = 0x018c # macro
|
|
regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_RB_WPTR = 0x018d # macro
|
|
regSDMA0_QUEUE3_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_RB_WPTR_HI = 0x018e # macro
|
|
regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_RB_RPTR_ADDR_HI = 0x0190 # macro
|
|
regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_RB_RPTR_ADDR_LO = 0x0191 # macro
|
|
regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_IB_CNTL = 0x0192 # macro
|
|
regSDMA0_QUEUE3_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_IB_RPTR = 0x0193 # macro
|
|
regSDMA0_QUEUE3_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_IB_OFFSET = 0x0194 # macro
|
|
regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_IB_BASE_LO = 0x0195 # macro
|
|
regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_IB_BASE_HI = 0x0196 # macro
|
|
regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_IB_SIZE = 0x0197 # macro
|
|
regSDMA0_QUEUE3_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_SKIP_CNTL = 0x0198 # macro
|
|
regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_CONTEXT_STATUS = 0x0199 # macro
|
|
regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_DOORBELL = 0x019a # macro
|
|
regSDMA0_QUEUE3_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_DOORBELL_LOG = 0x01b1 # macro
|
|
regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_DOORBELL_OFFSET = 0x01b3 # macro
|
|
regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_CSA_ADDR_LO = 0x01b4 # macro
|
|
regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_CSA_ADDR_HI = 0x01b5 # macro
|
|
regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_SCHEDULE_CNTL = 0x01b6 # macro
|
|
regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_IB_SUB_REMAIN = 0x01b7 # macro
|
|
regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_PREEMPT = 0x01b8 # macro
|
|
regSDMA0_QUEUE3_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_DUMMY_REG = 0x01b9 # macro
|
|
regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI = 0x01ba # macro
|
|
regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO = 0x01bb # macro
|
|
regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_RB_AQL_CNTL = 0x01bc # macro
|
|
regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_MINOR_PTR_UPDATE = 0x01bd # macro
|
|
regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_RB_PREEMPT = 0x01be # macro
|
|
regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA0 = 0x01c8 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA1 = 0x01c9 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA2 = 0x01ca # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA3 = 0x01cb # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA4 = 0x01cc # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA5 = 0x01cd # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA6 = 0x01ce # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA7 = 0x01cf # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA8 = 0x01d0 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA9 = 0x01d1 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA10 = 0x01d2 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_CNTL = 0x01d3 # macro
|
|
regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_RB_CNTL = 0x01e0 # macro
|
|
regSDMA0_QUEUE4_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_RB_BASE = 0x01e1 # macro
|
|
regSDMA0_QUEUE4_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_RB_BASE_HI = 0x01e2 # macro
|
|
regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_RB_RPTR = 0x01e3 # macro
|
|
regSDMA0_QUEUE4_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_RB_RPTR_HI = 0x01e4 # macro
|
|
regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_RB_WPTR = 0x01e5 # macro
|
|
regSDMA0_QUEUE4_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_RB_WPTR_HI = 0x01e6 # macro
|
|
regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_RB_RPTR_ADDR_HI = 0x01e8 # macro
|
|
regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_RB_RPTR_ADDR_LO = 0x01e9 # macro
|
|
regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_IB_CNTL = 0x01ea # macro
|
|
regSDMA0_QUEUE4_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_IB_RPTR = 0x01eb # macro
|
|
regSDMA0_QUEUE4_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_IB_OFFSET = 0x01ec # macro
|
|
regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_IB_BASE_LO = 0x01ed # macro
|
|
regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_IB_BASE_HI = 0x01ee # macro
|
|
regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_IB_SIZE = 0x01ef # macro
|
|
regSDMA0_QUEUE4_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_SKIP_CNTL = 0x01f0 # macro
|
|
regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_CONTEXT_STATUS = 0x01f1 # macro
|
|
regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_DOORBELL = 0x01f2 # macro
|
|
regSDMA0_QUEUE4_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_DOORBELL_LOG = 0x0209 # macro
|
|
regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_DOORBELL_OFFSET = 0x020b # macro
|
|
regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_CSA_ADDR_LO = 0x020c # macro
|
|
regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_CSA_ADDR_HI = 0x020d # macro
|
|
regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_SCHEDULE_CNTL = 0x020e # macro
|
|
regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_IB_SUB_REMAIN = 0x020f # macro
|
|
regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_PREEMPT = 0x0210 # macro
|
|
regSDMA0_QUEUE4_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_DUMMY_REG = 0x0211 # macro
|
|
regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI = 0x0212 # macro
|
|
regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO = 0x0213 # macro
|
|
regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_RB_AQL_CNTL = 0x0214 # macro
|
|
regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_MINOR_PTR_UPDATE = 0x0215 # macro
|
|
regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_RB_PREEMPT = 0x0216 # macro
|
|
regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA0 = 0x0220 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA1 = 0x0221 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA2 = 0x0222 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA3 = 0x0223 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA4 = 0x0224 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA5 = 0x0225 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA6 = 0x0226 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA7 = 0x0227 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA8 = 0x0228 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA9 = 0x0229 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA10 = 0x022a # macro
|
|
regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE4_MIDCMD_CNTL = 0x022b # macro
|
|
regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_RB_CNTL = 0x0238 # macro
|
|
regSDMA0_QUEUE5_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_RB_BASE = 0x0239 # macro
|
|
regSDMA0_QUEUE5_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_RB_BASE_HI = 0x023a # macro
|
|
regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_RB_RPTR = 0x023b # macro
|
|
regSDMA0_QUEUE5_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_RB_RPTR_HI = 0x023c # macro
|
|
regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_RB_WPTR = 0x023d # macro
|
|
regSDMA0_QUEUE5_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_RB_WPTR_HI = 0x023e # macro
|
|
regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_RB_RPTR_ADDR_HI = 0x0240 # macro
|
|
regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_RB_RPTR_ADDR_LO = 0x0241 # macro
|
|
regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_IB_CNTL = 0x0242 # macro
|
|
regSDMA0_QUEUE5_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_IB_RPTR = 0x0243 # macro
|
|
regSDMA0_QUEUE5_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_IB_OFFSET = 0x0244 # macro
|
|
regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_IB_BASE_LO = 0x0245 # macro
|
|
regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_IB_BASE_HI = 0x0246 # macro
|
|
regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_IB_SIZE = 0x0247 # macro
|
|
regSDMA0_QUEUE5_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_SKIP_CNTL = 0x0248 # macro
|
|
regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_CONTEXT_STATUS = 0x0249 # macro
|
|
regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_DOORBELL = 0x024a # macro
|
|
regSDMA0_QUEUE5_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_DOORBELL_LOG = 0x0261 # macro
|
|
regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_DOORBELL_OFFSET = 0x0263 # macro
|
|
regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_CSA_ADDR_LO = 0x0264 # macro
|
|
regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_CSA_ADDR_HI = 0x0265 # macro
|
|
regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_SCHEDULE_CNTL = 0x0266 # macro
|
|
regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_IB_SUB_REMAIN = 0x0267 # macro
|
|
regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_PREEMPT = 0x0268 # macro
|
|
regSDMA0_QUEUE5_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_DUMMY_REG = 0x0269 # macro
|
|
regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI = 0x026a # macro
|
|
regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO = 0x026b # macro
|
|
regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_RB_AQL_CNTL = 0x026c # macro
|
|
regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_MINOR_PTR_UPDATE = 0x026d # macro
|
|
regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_RB_PREEMPT = 0x026e # macro
|
|
regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA0 = 0x0278 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA1 = 0x0279 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA2 = 0x027a # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA3 = 0x027b # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA4 = 0x027c # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA5 = 0x027d # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA6 = 0x027e # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA7 = 0x027f # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA8 = 0x0280 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA9 = 0x0281 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA10 = 0x0282 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_CNTL = 0x0283 # macro
|
|
regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_RB_CNTL = 0x0290 # macro
|
|
regSDMA0_QUEUE6_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_RB_BASE = 0x0291 # macro
|
|
regSDMA0_QUEUE6_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_RB_BASE_HI = 0x0292 # macro
|
|
regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_RB_RPTR = 0x0293 # macro
|
|
regSDMA0_QUEUE6_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_RB_RPTR_HI = 0x0294 # macro
|
|
regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_RB_WPTR = 0x0295 # macro
|
|
regSDMA0_QUEUE6_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_RB_WPTR_HI = 0x0296 # macro
|
|
regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_RB_RPTR_ADDR_HI = 0x0298 # macro
|
|
regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_RB_RPTR_ADDR_LO = 0x0299 # macro
|
|
regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_IB_CNTL = 0x029a # macro
|
|
regSDMA0_QUEUE6_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_IB_RPTR = 0x029b # macro
|
|
regSDMA0_QUEUE6_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_IB_OFFSET = 0x029c # macro
|
|
regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_IB_BASE_LO = 0x029d # macro
|
|
regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_IB_BASE_HI = 0x029e # macro
|
|
regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_IB_SIZE = 0x029f # macro
|
|
regSDMA0_QUEUE6_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_SKIP_CNTL = 0x02a0 # macro
|
|
regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_CONTEXT_STATUS = 0x02a1 # macro
|
|
regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_DOORBELL = 0x02a2 # macro
|
|
regSDMA0_QUEUE6_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_DOORBELL_LOG = 0x02b9 # macro
|
|
regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_DOORBELL_OFFSET = 0x02bb # macro
|
|
regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_CSA_ADDR_LO = 0x02bc # macro
|
|
regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_CSA_ADDR_HI = 0x02bd # macro
|
|
regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_SCHEDULE_CNTL = 0x02be # macro
|
|
regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_IB_SUB_REMAIN = 0x02bf # macro
|
|
regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_PREEMPT = 0x02c0 # macro
|
|
regSDMA0_QUEUE6_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_DUMMY_REG = 0x02c1 # macro
|
|
regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI = 0x02c2 # macro
|
|
regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO = 0x02c3 # macro
|
|
regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_RB_AQL_CNTL = 0x02c4 # macro
|
|
regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_MINOR_PTR_UPDATE = 0x02c5 # macro
|
|
regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_RB_PREEMPT = 0x02c6 # macro
|
|
regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA0 = 0x02d0 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA1 = 0x02d1 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA2 = 0x02d2 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA3 = 0x02d3 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA4 = 0x02d4 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA5 = 0x02d5 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA6 = 0x02d6 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA7 = 0x02d7 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA8 = 0x02d8 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA9 = 0x02d9 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA10 = 0x02da # macro
|
|
regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE6_MIDCMD_CNTL = 0x02db # macro
|
|
regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_RB_CNTL = 0x02e8 # macro
|
|
regSDMA0_QUEUE7_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_RB_BASE = 0x02e9 # macro
|
|
regSDMA0_QUEUE7_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_RB_BASE_HI = 0x02ea # macro
|
|
regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_RB_RPTR = 0x02eb # macro
|
|
regSDMA0_QUEUE7_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_RB_RPTR_HI = 0x02ec # macro
|
|
regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_RB_WPTR = 0x02ed # macro
|
|
regSDMA0_QUEUE7_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_RB_WPTR_HI = 0x02ee # macro
|
|
regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_RB_RPTR_ADDR_HI = 0x02f0 # macro
|
|
regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_RB_RPTR_ADDR_LO = 0x02f1 # macro
|
|
regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_IB_CNTL = 0x02f2 # macro
|
|
regSDMA0_QUEUE7_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_IB_RPTR = 0x02f3 # macro
|
|
regSDMA0_QUEUE7_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_IB_OFFSET = 0x02f4 # macro
|
|
regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_IB_BASE_LO = 0x02f5 # macro
|
|
regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_IB_BASE_HI = 0x02f6 # macro
|
|
regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_IB_SIZE = 0x02f7 # macro
|
|
regSDMA0_QUEUE7_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_SKIP_CNTL = 0x02f8 # macro
|
|
regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_CONTEXT_STATUS = 0x02f9 # macro
|
|
regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_DOORBELL = 0x02fa # macro
|
|
regSDMA0_QUEUE7_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_DOORBELL_LOG = 0x0311 # macro
|
|
regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_DOORBELL_OFFSET = 0x0313 # macro
|
|
regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_CSA_ADDR_LO = 0x0314 # macro
|
|
regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_CSA_ADDR_HI = 0x0315 # macro
|
|
regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_SCHEDULE_CNTL = 0x0316 # macro
|
|
regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_IB_SUB_REMAIN = 0x0317 # macro
|
|
regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_PREEMPT = 0x0318 # macro
|
|
regSDMA0_QUEUE7_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_DUMMY_REG = 0x0319 # macro
|
|
regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI = 0x031a # macro
|
|
regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO = 0x031b # macro
|
|
regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_RB_AQL_CNTL = 0x031c # macro
|
|
regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_MINOR_PTR_UPDATE = 0x031d # macro
|
|
regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_RB_PREEMPT = 0x031e # macro
|
|
regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA0 = 0x0328 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA1 = 0x0329 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA2 = 0x032a # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA3 = 0x032b # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA4 = 0x032c # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA5 = 0x032d # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA6 = 0x032e # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA7 = 0x032f # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA8 = 0x0330 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA9 = 0x0331 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA10 = 0x0332 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_CNTL = 0x0333 # macro
|
|
regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_DEC_START = 0x0600 # macro
|
|
regSDMA1_DEC_START_BASE_IDX = 0 # macro
|
|
regSDMA1_F32_MISC_CNTL = 0x060b # macro
|
|
regSDMA1_F32_MISC_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_GLOBAL_TIMESTAMP_LO = 0x060f # macro
|
|
regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_GLOBAL_TIMESTAMP_HI = 0x0610 # macro
|
|
regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_POWER_CNTL = 0x061a # macro
|
|
regSDMA1_POWER_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_CNTL = 0x061c # macro
|
|
regSDMA1_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_CHICKEN_BITS = 0x061d # macro
|
|
regSDMA1_CHICKEN_BITS_BASE_IDX = 0 # macro
|
|
regSDMA1_GB_ADDR_CONFIG = 0x061e # macro
|
|
regSDMA1_GB_ADDR_CONFIG_BASE_IDX = 0 # macro
|
|
regSDMA1_GB_ADDR_CONFIG_READ = 0x061f # macro
|
|
regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro
|
|
regSDMA1_RB_RPTR_FETCH = 0x0620 # macro
|
|
regSDMA1_RB_RPTR_FETCH_BASE_IDX = 0 # macro
|
|
regSDMA1_RB_RPTR_FETCH_HI = 0x0621 # macro
|
|
regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL = 0x0622 # macro
|
|
regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_IB_OFFSET_FETCH = 0x0623 # macro
|
|
regSDMA1_IB_OFFSET_FETCH_BASE_IDX = 0 # macro
|
|
regSDMA1_PROGRAM = 0x0624 # macro
|
|
regSDMA1_PROGRAM_BASE_IDX = 0 # macro
|
|
regSDMA1_STATUS_REG = 0x0625 # macro
|
|
regSDMA1_STATUS_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_STATUS1_REG = 0x0626 # macro
|
|
regSDMA1_STATUS1_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_CNTL1 = 0x0627 # macro
|
|
regSDMA1_CNTL1_BASE_IDX = 0 # macro
|
|
regSDMA1_HBM_PAGE_CONFIG = 0x0628 # macro
|
|
regSDMA1_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro
|
|
regSDMA1_UCODE_CHECKSUM = 0x0629 # macro
|
|
regSDMA1_UCODE_CHECKSUM_BASE_IDX = 0 # macro
|
|
regSDMA1_FREEZE = 0x062b # macro
|
|
regSDMA1_FREEZE_BASE_IDX = 0 # macro
|
|
regSDMA1_PROCESS_QUANTUM0 = 0x062c # macro
|
|
regSDMA1_PROCESS_QUANTUM0_BASE_IDX = 0 # macro
|
|
regSDMA1_PROCESS_QUANTUM1 = 0x062d # macro
|
|
regSDMA1_PROCESS_QUANTUM1_BASE_IDX = 0 # macro
|
|
regSDMA1_WATCHDOG_CNTL = 0x062e # macro
|
|
regSDMA1_WATCHDOG_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE_STATUS0 = 0x062f # macro
|
|
regSDMA1_QUEUE_STATUS0_BASE_IDX = 0 # macro
|
|
regSDMA1_EDC_CONFIG = 0x0632 # macro
|
|
regSDMA1_EDC_CONFIG_BASE_IDX = 0 # macro
|
|
regSDMA1_BA_THRESHOLD = 0x0633 # macro
|
|
regSDMA1_BA_THRESHOLD_BASE_IDX = 0 # macro
|
|
regSDMA1_ID = 0x0634 # macro
|
|
regSDMA1_ID_BASE_IDX = 0 # macro
|
|
regSDMA1_VERSION = 0x0635 # macro
|
|
regSDMA1_VERSION_BASE_IDX = 0 # macro
|
|
regSDMA1_EDC_COUNTER = 0x0636 # macro
|
|
regSDMA1_EDC_COUNTER_BASE_IDX = 0 # macro
|
|
regSDMA1_EDC_COUNTER_CLEAR = 0x0637 # macro
|
|
regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro
|
|
regSDMA1_STATUS2_REG = 0x0638 # macro
|
|
regSDMA1_STATUS2_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_ATOMIC_CNTL = 0x0639 # macro
|
|
regSDMA1_ATOMIC_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_ATOMIC_PREOP_LO = 0x063a # macro
|
|
regSDMA1_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_ATOMIC_PREOP_HI = 0x063b # macro
|
|
regSDMA1_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_UTCL1_CNTL = 0x063c # macro
|
|
regSDMA1_UTCL1_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_UTCL1_WATERMK = 0x063d # macro
|
|
regSDMA1_UTCL1_WATERMK_BASE_IDX = 0 # macro
|
|
regSDMA1_UTCL1_TIMEOUT = 0x063e # macro
|
|
regSDMA1_UTCL1_TIMEOUT_BASE_IDX = 0 # macro
|
|
regSDMA1_UTCL1_PAGE = 0x063f # macro
|
|
regSDMA1_UTCL1_PAGE_BASE_IDX = 0 # macro
|
|
regSDMA1_UTCL1_RD_STATUS = 0x0640 # macro
|
|
regSDMA1_UTCL1_RD_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_UTCL1_WR_STATUS = 0x0641 # macro
|
|
regSDMA1_UTCL1_WR_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_UTCL1_INV0 = 0x0642 # macro
|
|
regSDMA1_UTCL1_INV0_BASE_IDX = 0 # macro
|
|
regSDMA1_UTCL1_INV1 = 0x0643 # macro
|
|
regSDMA1_UTCL1_INV1_BASE_IDX = 0 # macro
|
|
regSDMA1_UTCL1_INV2 = 0x0644 # macro
|
|
regSDMA1_UTCL1_INV2_BASE_IDX = 0 # macro
|
|
regSDMA1_UTCL1_RD_XNACK0 = 0x0645 # macro
|
|
regSDMA1_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro
|
|
regSDMA1_UTCL1_RD_XNACK1 = 0x0646 # macro
|
|
regSDMA1_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro
|
|
regSDMA1_UTCL1_WR_XNACK0 = 0x0647 # macro
|
|
regSDMA1_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro
|
|
regSDMA1_UTCL1_WR_XNACK1 = 0x0648 # macro
|
|
regSDMA1_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro
|
|
regSDMA1_RELAX_ORDERING_LUT = 0x064a # macro
|
|
regSDMA1_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro
|
|
regSDMA1_CHICKEN_BITS_2 = 0x064b # macro
|
|
regSDMA1_CHICKEN_BITS_2_BASE_IDX = 0 # macro
|
|
regSDMA1_STATUS3_REG = 0x064c # macro
|
|
regSDMA1_STATUS3_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_PHYSICAL_ADDR_LO = 0x064d # macro
|
|
regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_PHYSICAL_ADDR_HI = 0x064e # macro
|
|
regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_GLOBAL_QUANTUM = 0x064f # macro
|
|
regSDMA1_GLOBAL_QUANTUM_BASE_IDX = 0 # macro
|
|
regSDMA1_ERROR_LOG = 0x0650 # macro
|
|
regSDMA1_ERROR_LOG_BASE_IDX = 0 # macro
|
|
regSDMA1_PUB_DUMMY_REG0 = 0x0651 # macro
|
|
regSDMA1_PUB_DUMMY_REG0_BASE_IDX = 0 # macro
|
|
regSDMA1_PUB_DUMMY_REG1 = 0x0652 # macro
|
|
regSDMA1_PUB_DUMMY_REG1_BASE_IDX = 0 # macro
|
|
regSDMA1_PUB_DUMMY_REG2 = 0x0653 # macro
|
|
regSDMA1_PUB_DUMMY_REG2_BASE_IDX = 0 # macro
|
|
regSDMA1_PUB_DUMMY_REG3 = 0x0654 # macro
|
|
regSDMA1_PUB_DUMMY_REG3_BASE_IDX = 0 # macro
|
|
regSDMA1_F32_COUNTER = 0x0655 # macro
|
|
regSDMA1_F32_COUNTER_BASE_IDX = 0 # macro
|
|
regSDMA1_CRD_CNTL = 0x065b # macro
|
|
regSDMA1_CRD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_RLC_CGCG_CTRL = 0x065c # macro
|
|
regSDMA1_RLC_CGCG_CTRL_BASE_IDX = 0 # macro
|
|
regSDMA1_AQL_STATUS = 0x065f # macro
|
|
regSDMA1_AQL_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_EA_DBIT_ADDR_DATA = 0x0660 # macro
|
|
regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro
|
|
regSDMA1_EA_DBIT_ADDR_INDEX = 0x0661 # macro
|
|
regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro
|
|
regSDMA1_TLBI_GCR_CNTL = 0x0662 # macro
|
|
regSDMA1_TLBI_GCR_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_TILING_CONFIG = 0x0663 # macro
|
|
regSDMA1_TILING_CONFIG_BASE_IDX = 0 # macro
|
|
regSDMA1_INT_STATUS = 0x0670 # macro
|
|
regSDMA1_INT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_HOLE_ADDR_LO = 0x0672 # macro
|
|
regSDMA1_HOLE_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_HOLE_ADDR_HI = 0x0673 # macro
|
|
regSDMA1_HOLE_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_CLOCK_GATING_STATUS = 0x0675 # macro
|
|
regSDMA1_CLOCK_GATING_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_STATUS4_REG = 0x0676 # macro
|
|
regSDMA1_STATUS4_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_SCRATCH_RAM_DATA = 0x0677 # macro
|
|
regSDMA1_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro
|
|
regSDMA1_SCRATCH_RAM_ADDR = 0x0678 # macro
|
|
regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro
|
|
regSDMA1_TIMESTAMP_CNTL = 0x0679 # macro
|
|
regSDMA1_TIMESTAMP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_STATUS5_REG = 0x067a # macro
|
|
regSDMA1_STATUS5_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE_RESET_REQ = 0x067b # macro
|
|
regSDMA1_QUEUE_RESET_REQ_BASE_IDX = 0 # macro
|
|
regSDMA1_STATUS6_REG = 0x067c # macro
|
|
regSDMA1_STATUS6_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_UCODE1_CHECKSUM = 0x067d # macro
|
|
regSDMA1_UCODE1_CHECKSUM_BASE_IDX = 0 # macro
|
|
regSDMA1_CE_CTRL = 0x067e # macro
|
|
regSDMA1_CE_CTRL_BASE_IDX = 0 # macro
|
|
regSDMA1_FED_STATUS = 0x067f # macro
|
|
regSDMA1_FED_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_RB_CNTL = 0x0680 # macro
|
|
regSDMA1_QUEUE0_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_RB_BASE = 0x0681 # macro
|
|
regSDMA1_QUEUE0_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_RB_BASE_HI = 0x0682 # macro
|
|
regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_RB_RPTR = 0x0683 # macro
|
|
regSDMA1_QUEUE0_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_RB_RPTR_HI = 0x0684 # macro
|
|
regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_RB_WPTR = 0x0685 # macro
|
|
regSDMA1_QUEUE0_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_RB_WPTR_HI = 0x0686 # macro
|
|
regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_RB_RPTR_ADDR_HI = 0x0688 # macro
|
|
regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_RB_RPTR_ADDR_LO = 0x0689 # macro
|
|
regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_IB_CNTL = 0x068a # macro
|
|
regSDMA1_QUEUE0_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_IB_RPTR = 0x068b # macro
|
|
regSDMA1_QUEUE0_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_IB_OFFSET = 0x068c # macro
|
|
regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_IB_BASE_LO = 0x068d # macro
|
|
regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_IB_BASE_HI = 0x068e # macro
|
|
regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_IB_SIZE = 0x068f # macro
|
|
regSDMA1_QUEUE0_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_SKIP_CNTL = 0x0690 # macro
|
|
regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_CONTEXT_STATUS = 0x0691 # macro
|
|
regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_DOORBELL = 0x0692 # macro
|
|
regSDMA1_QUEUE0_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_DOORBELL_LOG = 0x06a9 # macro
|
|
regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_DOORBELL_OFFSET = 0x06ab # macro
|
|
regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_CSA_ADDR_LO = 0x06ac # macro
|
|
regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_CSA_ADDR_HI = 0x06ad # macro
|
|
regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_SCHEDULE_CNTL = 0x06ae # macro
|
|
regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_IB_SUB_REMAIN = 0x06af # macro
|
|
regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_PREEMPT = 0x06b0 # macro
|
|
regSDMA1_QUEUE0_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_DUMMY_REG = 0x06b1 # macro
|
|
regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI = 0x06b2 # macro
|
|
regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO = 0x06b3 # macro
|
|
regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_RB_AQL_CNTL = 0x06b4 # macro
|
|
regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_MINOR_PTR_UPDATE = 0x06b5 # macro
|
|
regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_RB_PREEMPT = 0x06b6 # macro
|
|
regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA0 = 0x06c0 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA1 = 0x06c1 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA2 = 0x06c2 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA3 = 0x06c3 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA4 = 0x06c4 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA5 = 0x06c5 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA6 = 0x06c6 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA7 = 0x06c7 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA8 = 0x06c8 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA9 = 0x06c9 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA10 = 0x06ca # macro
|
|
regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE0_MIDCMD_CNTL = 0x06cb # macro
|
|
regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_RB_CNTL = 0x06d8 # macro
|
|
regSDMA1_QUEUE1_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_RB_BASE = 0x06d9 # macro
|
|
regSDMA1_QUEUE1_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_RB_BASE_HI = 0x06da # macro
|
|
regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_RB_RPTR = 0x06db # macro
|
|
regSDMA1_QUEUE1_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_RB_RPTR_HI = 0x06dc # macro
|
|
regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_RB_WPTR = 0x06dd # macro
|
|
regSDMA1_QUEUE1_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_RB_WPTR_HI = 0x06de # macro
|
|
regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_RB_RPTR_ADDR_HI = 0x06e0 # macro
|
|
regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_RB_RPTR_ADDR_LO = 0x06e1 # macro
|
|
regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_IB_CNTL = 0x06e2 # macro
|
|
regSDMA1_QUEUE1_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_IB_RPTR = 0x06e3 # macro
|
|
regSDMA1_QUEUE1_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_IB_OFFSET = 0x06e4 # macro
|
|
regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_IB_BASE_LO = 0x06e5 # macro
|
|
regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_IB_BASE_HI = 0x06e6 # macro
|
|
regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_IB_SIZE = 0x06e7 # macro
|
|
regSDMA1_QUEUE1_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_SKIP_CNTL = 0x06e8 # macro
|
|
regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_CONTEXT_STATUS = 0x06e9 # macro
|
|
regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_DOORBELL = 0x06ea # macro
|
|
regSDMA1_QUEUE1_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_DOORBELL_LOG = 0x0701 # macro
|
|
regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_DOORBELL_OFFSET = 0x0703 # macro
|
|
regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_CSA_ADDR_LO = 0x0704 # macro
|
|
regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_CSA_ADDR_HI = 0x0705 # macro
|
|
regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_SCHEDULE_CNTL = 0x0706 # macro
|
|
regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_IB_SUB_REMAIN = 0x0707 # macro
|
|
regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_PREEMPT = 0x0708 # macro
|
|
regSDMA1_QUEUE1_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_DUMMY_REG = 0x0709 # macro
|
|
regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI = 0x070a # macro
|
|
regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO = 0x070b # macro
|
|
regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_RB_AQL_CNTL = 0x070c # macro
|
|
regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_MINOR_PTR_UPDATE = 0x070d # macro
|
|
regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_RB_PREEMPT = 0x070e # macro
|
|
regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA0 = 0x0718 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA1 = 0x0719 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA2 = 0x071a # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA3 = 0x071b # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA4 = 0x071c # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA5 = 0x071d # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA6 = 0x071e # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA7 = 0x071f # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA8 = 0x0720 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA9 = 0x0721 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA10 = 0x0722 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_CNTL = 0x0723 # macro
|
|
regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_RB_CNTL = 0x0730 # macro
|
|
regSDMA1_QUEUE2_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_RB_BASE = 0x0731 # macro
|
|
regSDMA1_QUEUE2_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_RB_BASE_HI = 0x0732 # macro
|
|
regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_RB_RPTR = 0x0733 # macro
|
|
regSDMA1_QUEUE2_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_RB_RPTR_HI = 0x0734 # macro
|
|
regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_RB_WPTR = 0x0735 # macro
|
|
regSDMA1_QUEUE2_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_RB_WPTR_HI = 0x0736 # macro
|
|
regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_RB_RPTR_ADDR_HI = 0x0738 # macro
|
|
regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_RB_RPTR_ADDR_LO = 0x0739 # macro
|
|
regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_IB_CNTL = 0x073a # macro
|
|
regSDMA1_QUEUE2_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_IB_RPTR = 0x073b # macro
|
|
regSDMA1_QUEUE2_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_IB_OFFSET = 0x073c # macro
|
|
regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_IB_BASE_LO = 0x073d # macro
|
|
regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_IB_BASE_HI = 0x073e # macro
|
|
regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_IB_SIZE = 0x073f # macro
|
|
regSDMA1_QUEUE2_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_SKIP_CNTL = 0x0740 # macro
|
|
regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_CONTEXT_STATUS = 0x0741 # macro
|
|
regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_DOORBELL = 0x0742 # macro
|
|
regSDMA1_QUEUE2_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_DOORBELL_LOG = 0x0759 # macro
|
|
regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_DOORBELL_OFFSET = 0x075b # macro
|
|
regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_CSA_ADDR_LO = 0x075c # macro
|
|
regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_CSA_ADDR_HI = 0x075d # macro
|
|
regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_SCHEDULE_CNTL = 0x075e # macro
|
|
regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_IB_SUB_REMAIN = 0x075f # macro
|
|
regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_PREEMPT = 0x0760 # macro
|
|
regSDMA1_QUEUE2_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_DUMMY_REG = 0x0761 # macro
|
|
regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI = 0x0762 # macro
|
|
regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO = 0x0763 # macro
|
|
regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_RB_AQL_CNTL = 0x0764 # macro
|
|
regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_MINOR_PTR_UPDATE = 0x0765 # macro
|
|
regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_RB_PREEMPT = 0x0766 # macro
|
|
regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA0 = 0x0770 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA1 = 0x0771 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA2 = 0x0772 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA3 = 0x0773 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA4 = 0x0774 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA5 = 0x0775 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA6 = 0x0776 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA7 = 0x0777 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA8 = 0x0778 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA9 = 0x0779 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA10 = 0x077a # macro
|
|
regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE2_MIDCMD_CNTL = 0x077b # macro
|
|
regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_RB_CNTL = 0x0788 # macro
|
|
regSDMA1_QUEUE3_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_RB_BASE = 0x0789 # macro
|
|
regSDMA1_QUEUE3_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_RB_BASE_HI = 0x078a # macro
|
|
regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_RB_RPTR = 0x078b # macro
|
|
regSDMA1_QUEUE3_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_RB_RPTR_HI = 0x078c # macro
|
|
regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_RB_WPTR = 0x078d # macro
|
|
regSDMA1_QUEUE3_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_RB_WPTR_HI = 0x078e # macro
|
|
regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_RB_RPTR_ADDR_HI = 0x0790 # macro
|
|
regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_RB_RPTR_ADDR_LO = 0x0791 # macro
|
|
regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_IB_CNTL = 0x0792 # macro
|
|
regSDMA1_QUEUE3_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_IB_RPTR = 0x0793 # macro
|
|
regSDMA1_QUEUE3_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_IB_OFFSET = 0x0794 # macro
|
|
regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_IB_BASE_LO = 0x0795 # macro
|
|
regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_IB_BASE_HI = 0x0796 # macro
|
|
regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_IB_SIZE = 0x0797 # macro
|
|
regSDMA1_QUEUE3_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_SKIP_CNTL = 0x0798 # macro
|
|
regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_CONTEXT_STATUS = 0x0799 # macro
|
|
regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_DOORBELL = 0x079a # macro
|
|
regSDMA1_QUEUE3_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_DOORBELL_LOG = 0x07b1 # macro
|
|
regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_DOORBELL_OFFSET = 0x07b3 # macro
|
|
regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_CSA_ADDR_LO = 0x07b4 # macro
|
|
regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_CSA_ADDR_HI = 0x07b5 # macro
|
|
regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_SCHEDULE_CNTL = 0x07b6 # macro
|
|
regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_IB_SUB_REMAIN = 0x07b7 # macro
|
|
regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_PREEMPT = 0x07b8 # macro
|
|
regSDMA1_QUEUE3_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_DUMMY_REG = 0x07b9 # macro
|
|
regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI = 0x07ba # macro
|
|
regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO = 0x07bb # macro
|
|
regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_RB_AQL_CNTL = 0x07bc # macro
|
|
regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_MINOR_PTR_UPDATE = 0x07bd # macro
|
|
regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_RB_PREEMPT = 0x07be # macro
|
|
regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA0 = 0x07c8 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA1 = 0x07c9 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA2 = 0x07ca # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA3 = 0x07cb # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA4 = 0x07cc # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA5 = 0x07cd # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA6 = 0x07ce # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA7 = 0x07cf # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA8 = 0x07d0 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA9 = 0x07d1 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA10 = 0x07d2 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_CNTL = 0x07d3 # macro
|
|
regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_RB_CNTL = 0x07e0 # macro
|
|
regSDMA1_QUEUE4_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_RB_BASE = 0x07e1 # macro
|
|
regSDMA1_QUEUE4_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_RB_BASE_HI = 0x07e2 # macro
|
|
regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_RB_RPTR = 0x07e3 # macro
|
|
regSDMA1_QUEUE4_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_RB_RPTR_HI = 0x07e4 # macro
|
|
regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_RB_WPTR = 0x07e5 # macro
|
|
regSDMA1_QUEUE4_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_RB_WPTR_HI = 0x07e6 # macro
|
|
regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_RB_RPTR_ADDR_HI = 0x07e8 # macro
|
|
regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_RB_RPTR_ADDR_LO = 0x07e9 # macro
|
|
regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_IB_CNTL = 0x07ea # macro
|
|
regSDMA1_QUEUE4_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_IB_RPTR = 0x07eb # macro
|
|
regSDMA1_QUEUE4_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_IB_OFFSET = 0x07ec # macro
|
|
regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_IB_BASE_LO = 0x07ed # macro
|
|
regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_IB_BASE_HI = 0x07ee # macro
|
|
regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_IB_SIZE = 0x07ef # macro
|
|
regSDMA1_QUEUE4_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_SKIP_CNTL = 0x07f0 # macro
|
|
regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_CONTEXT_STATUS = 0x07f1 # macro
|
|
regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_DOORBELL = 0x07f2 # macro
|
|
regSDMA1_QUEUE4_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_DOORBELL_LOG = 0x0809 # macro
|
|
regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_DOORBELL_OFFSET = 0x080b # macro
|
|
regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_CSA_ADDR_LO = 0x080c # macro
|
|
regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_CSA_ADDR_HI = 0x080d # macro
|
|
regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_SCHEDULE_CNTL = 0x080e # macro
|
|
regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_IB_SUB_REMAIN = 0x080f # macro
|
|
regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_PREEMPT = 0x0810 # macro
|
|
regSDMA1_QUEUE4_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_DUMMY_REG = 0x0811 # macro
|
|
regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI = 0x0812 # macro
|
|
regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO = 0x0813 # macro
|
|
regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_RB_AQL_CNTL = 0x0814 # macro
|
|
regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_MINOR_PTR_UPDATE = 0x0815 # macro
|
|
regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_RB_PREEMPT = 0x0816 # macro
|
|
regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA0 = 0x0820 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA1 = 0x0821 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA2 = 0x0822 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA3 = 0x0823 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA4 = 0x0824 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA5 = 0x0825 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA6 = 0x0826 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA7 = 0x0827 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA8 = 0x0828 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA9 = 0x0829 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA10 = 0x082a # macro
|
|
regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE4_MIDCMD_CNTL = 0x082b # macro
|
|
regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_RB_CNTL = 0x0838 # macro
|
|
regSDMA1_QUEUE5_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_RB_BASE = 0x0839 # macro
|
|
regSDMA1_QUEUE5_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_RB_BASE_HI = 0x083a # macro
|
|
regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_RB_RPTR = 0x083b # macro
|
|
regSDMA1_QUEUE5_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_RB_RPTR_HI = 0x083c # macro
|
|
regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_RB_WPTR = 0x083d # macro
|
|
regSDMA1_QUEUE5_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_RB_WPTR_HI = 0x083e # macro
|
|
regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_RB_RPTR_ADDR_HI = 0x0840 # macro
|
|
regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_RB_RPTR_ADDR_LO = 0x0841 # macro
|
|
regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_IB_CNTL = 0x0842 # macro
|
|
regSDMA1_QUEUE5_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_IB_RPTR = 0x0843 # macro
|
|
regSDMA1_QUEUE5_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_IB_OFFSET = 0x0844 # macro
|
|
regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_IB_BASE_LO = 0x0845 # macro
|
|
regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_IB_BASE_HI = 0x0846 # macro
|
|
regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_IB_SIZE = 0x0847 # macro
|
|
regSDMA1_QUEUE5_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_SKIP_CNTL = 0x0848 # macro
|
|
regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_CONTEXT_STATUS = 0x0849 # macro
|
|
regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_DOORBELL = 0x084a # macro
|
|
regSDMA1_QUEUE5_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_DOORBELL_LOG = 0x0861 # macro
|
|
regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_DOORBELL_OFFSET = 0x0863 # macro
|
|
regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_CSA_ADDR_LO = 0x0864 # macro
|
|
regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_CSA_ADDR_HI = 0x0865 # macro
|
|
regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_SCHEDULE_CNTL = 0x0866 # macro
|
|
regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_IB_SUB_REMAIN = 0x0867 # macro
|
|
regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_PREEMPT = 0x0868 # macro
|
|
regSDMA1_QUEUE5_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_DUMMY_REG = 0x0869 # macro
|
|
regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI = 0x086a # macro
|
|
regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO = 0x086b # macro
|
|
regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_RB_AQL_CNTL = 0x086c # macro
|
|
regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_MINOR_PTR_UPDATE = 0x086d # macro
|
|
regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_RB_PREEMPT = 0x086e # macro
|
|
regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA0 = 0x0878 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA1 = 0x0879 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA2 = 0x087a # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA3 = 0x087b # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA4 = 0x087c # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA5 = 0x087d # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA6 = 0x087e # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA7 = 0x087f # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA8 = 0x0880 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA9 = 0x0881 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA10 = 0x0882 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_CNTL = 0x0883 # macro
|
|
regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_RB_CNTL = 0x0890 # macro
|
|
regSDMA1_QUEUE6_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_RB_BASE = 0x0891 # macro
|
|
regSDMA1_QUEUE6_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_RB_BASE_HI = 0x0892 # macro
|
|
regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_RB_RPTR = 0x0893 # macro
|
|
regSDMA1_QUEUE6_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_RB_RPTR_HI = 0x0894 # macro
|
|
regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_RB_WPTR = 0x0895 # macro
|
|
regSDMA1_QUEUE6_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_RB_WPTR_HI = 0x0896 # macro
|
|
regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_RB_RPTR_ADDR_HI = 0x0898 # macro
|
|
regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_RB_RPTR_ADDR_LO = 0x0899 # macro
|
|
regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_IB_CNTL = 0x089a # macro
|
|
regSDMA1_QUEUE6_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_IB_RPTR = 0x089b # macro
|
|
regSDMA1_QUEUE6_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_IB_OFFSET = 0x089c # macro
|
|
regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_IB_BASE_LO = 0x089d # macro
|
|
regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_IB_BASE_HI = 0x089e # macro
|
|
regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_IB_SIZE = 0x089f # macro
|
|
regSDMA1_QUEUE6_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_SKIP_CNTL = 0x08a0 # macro
|
|
regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_CONTEXT_STATUS = 0x08a1 # macro
|
|
regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_DOORBELL = 0x08a2 # macro
|
|
regSDMA1_QUEUE6_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_DOORBELL_LOG = 0x08b9 # macro
|
|
regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_DOORBELL_OFFSET = 0x08bb # macro
|
|
regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_CSA_ADDR_LO = 0x08bc # macro
|
|
regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_CSA_ADDR_HI = 0x08bd # macro
|
|
regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_SCHEDULE_CNTL = 0x08be # macro
|
|
regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_IB_SUB_REMAIN = 0x08bf # macro
|
|
regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_PREEMPT = 0x08c0 # macro
|
|
regSDMA1_QUEUE6_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_DUMMY_REG = 0x08c1 # macro
|
|
regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI = 0x08c2 # macro
|
|
regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO = 0x08c3 # macro
|
|
regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_RB_AQL_CNTL = 0x08c4 # macro
|
|
regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_MINOR_PTR_UPDATE = 0x08c5 # macro
|
|
regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_RB_PREEMPT = 0x08c6 # macro
|
|
regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA0 = 0x08d0 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA1 = 0x08d1 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA2 = 0x08d2 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA3 = 0x08d3 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA4 = 0x08d4 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA5 = 0x08d5 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA6 = 0x08d6 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA7 = 0x08d7 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA8 = 0x08d8 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA9 = 0x08d9 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA10 = 0x08da # macro
|
|
regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE6_MIDCMD_CNTL = 0x08db # macro
|
|
regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_RB_CNTL = 0x08e8 # macro
|
|
regSDMA1_QUEUE7_RB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_RB_BASE = 0x08e9 # macro
|
|
regSDMA1_QUEUE7_RB_BASE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_RB_BASE_HI = 0x08ea # macro
|
|
regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_RB_RPTR = 0x08eb # macro
|
|
regSDMA1_QUEUE7_RB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_RB_RPTR_HI = 0x08ec # macro
|
|
regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_RB_WPTR = 0x08ed # macro
|
|
regSDMA1_QUEUE7_RB_WPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_RB_WPTR_HI = 0x08ee # macro
|
|
regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_RB_RPTR_ADDR_HI = 0x08f0 # macro
|
|
regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_RB_RPTR_ADDR_LO = 0x08f1 # macro
|
|
regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_IB_CNTL = 0x08f2 # macro
|
|
regSDMA1_QUEUE7_IB_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_IB_RPTR = 0x08f3 # macro
|
|
regSDMA1_QUEUE7_IB_RPTR_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_IB_OFFSET = 0x08f4 # macro
|
|
regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_IB_BASE_LO = 0x08f5 # macro
|
|
regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_IB_BASE_HI = 0x08f6 # macro
|
|
regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_IB_SIZE = 0x08f7 # macro
|
|
regSDMA1_QUEUE7_IB_SIZE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_SKIP_CNTL = 0x08f8 # macro
|
|
regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_CONTEXT_STATUS = 0x08f9 # macro
|
|
regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_DOORBELL = 0x08fa # macro
|
|
regSDMA1_QUEUE7_DOORBELL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_DOORBELL_LOG = 0x0911 # macro
|
|
regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_DOORBELL_OFFSET = 0x0913 # macro
|
|
regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_CSA_ADDR_LO = 0x0914 # macro
|
|
regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_CSA_ADDR_HI = 0x0915 # macro
|
|
regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_SCHEDULE_CNTL = 0x0916 # macro
|
|
regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_IB_SUB_REMAIN = 0x0917 # macro
|
|
regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_PREEMPT = 0x0918 # macro
|
|
regSDMA1_QUEUE7_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_DUMMY_REG = 0x0919 # macro
|
|
regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI = 0x091a # macro
|
|
regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO = 0x091b # macro
|
|
regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_RB_AQL_CNTL = 0x091c # macro
|
|
regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_MINOR_PTR_UPDATE = 0x091d # macro
|
|
regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_RB_PREEMPT = 0x091e # macro
|
|
regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA0 = 0x0928 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA1 = 0x0929 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA2 = 0x092a # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA3 = 0x092b # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA4 = 0x092c # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA5 = 0x092d # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA6 = 0x092e # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA7 = 0x092f # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA8 = 0x0930 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA9 = 0x0931 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA10 = 0x0932 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX = 0 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_CNTL = 0x0933 # macro
|
|
regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX = 0 # macro
|
|
regSDMA0_UCODE_ADDR = 0x5880 # macro
|
|
regSDMA0_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regSDMA0_UCODE_DATA = 0x5881 # macro
|
|
regSDMA0_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regSDMA0_UCODE_SELFLOAD_CONTROL = 0x5882 # macro
|
|
regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX = 1 # macro
|
|
regSDMA0_BROADCAST_UCODE_ADDR = 0x5886 # macro
|
|
regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regSDMA0_BROADCAST_UCODE_DATA = 0x5887 # macro
|
|
regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regSDMA0_F32_CNTL = 0x589a # macro
|
|
regSDMA0_F32_CNTL_BASE_IDX = 1 # macro
|
|
regSDMA1_UCODE_ADDR = 0x58a0 # macro
|
|
regSDMA1_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regSDMA1_UCODE_DATA = 0x58a1 # macro
|
|
regSDMA1_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regSDMA1_UCODE_SELFLOAD_CONTROL = 0x58a2 # macro
|
|
regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX = 1 # macro
|
|
regSDMA1_BROADCAST_UCODE_ADDR = 0x58a6 # macro
|
|
regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regSDMA1_BROADCAST_UCODE_DATA = 0x58a7 # macro
|
|
regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regSDMA1_F32_CNTL = 0x58ba # macro
|
|
regSDMA1_F32_CNTL_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCNT_PERFCOUNTER0_CFG = 0x3e20 # macro
|
|
regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCNT_PERFCOUNTER1_CFG = 0x3e21 # macro
|
|
regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e22 # macro
|
|
regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCNT_MISC_CNTL = 0x3e23 # macro
|
|
regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCOUNTER0_SELECT = 0x3e24 # macro
|
|
regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCOUNTER0_SELECT1 = 0x3e25 # macro
|
|
regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCOUNTER1_SELECT = 0x3e26 # macro
|
|
regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCOUNTER1_SELECT1 = 0x3e27 # macro
|
|
regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCNT_PERFCOUNTER0_CFG = 0x3e2c # macro
|
|
regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCNT_PERFCOUNTER1_CFG = 0x3e2d # macro
|
|
regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e2e # macro
|
|
regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCNT_MISC_CNTL = 0x3e2f # macro
|
|
regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCOUNTER0_SELECT = 0x3e30 # macro
|
|
regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCOUNTER0_SELECT1 = 0x3e31 # macro
|
|
regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCOUNTER1_SELECT = 0x3e32 # macro
|
|
regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCOUNTER1_SELECT1 = 0x3e33 # macro
|
|
regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCNT_PERFCOUNTER_LO = 0x3660 # macro
|
|
regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCNT_PERFCOUNTER_HI = 0x3661 # macro
|
|
regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCOUNTER0_LO = 0x3662 # macro
|
|
regSDMA0_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCOUNTER0_HI = 0x3663 # macro
|
|
regSDMA0_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCOUNTER1_LO = 0x3664 # macro
|
|
regSDMA0_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regSDMA0_PERFCOUNTER1_HI = 0x3665 # macro
|
|
regSDMA0_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCNT_PERFCOUNTER_LO = 0x366c # macro
|
|
regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCNT_PERFCOUNTER_HI = 0x366d # macro
|
|
regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCOUNTER0_LO = 0x366e # macro
|
|
regSDMA1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCOUNTER0_HI = 0x366f # macro
|
|
regSDMA1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCOUNTER1_LO = 0x3670 # macro
|
|
regSDMA1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regSDMA1_PERFCOUNTER1_HI = 0x3671 # macro
|
|
regSDMA1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regGRBM_CNTL = 0x0da0 # macro
|
|
regGRBM_CNTL_BASE_IDX = 0 # macro
|
|
regGRBM_SKEW_CNTL = 0x0da1 # macro
|
|
regGRBM_SKEW_CNTL_BASE_IDX = 0 # macro
|
|
regGRBM_STATUS2 = 0x0da2 # macro
|
|
regGRBM_STATUS2_BASE_IDX = 0 # macro
|
|
regGRBM_PWR_CNTL = 0x0da3 # macro
|
|
regGRBM_PWR_CNTL_BASE_IDX = 0 # macro
|
|
regGRBM_STATUS = 0x0da4 # macro
|
|
regGRBM_STATUS_BASE_IDX = 0 # macro
|
|
regGRBM_STATUS_SE0 = 0x0da5 # macro
|
|
regGRBM_STATUS_SE0_BASE_IDX = 0 # macro
|
|
regGRBM_STATUS_SE1 = 0x0da6 # macro
|
|
regGRBM_STATUS_SE1_BASE_IDX = 0 # macro
|
|
regGRBM_STATUS3 = 0x0da7 # macro
|
|
regGRBM_STATUS3_BASE_IDX = 0 # macro
|
|
regGRBM_SOFT_RESET = 0x0da8 # macro
|
|
regGRBM_SOFT_RESET_BASE_IDX = 0 # macro
|
|
regGRBM_GFX_CLKEN_CNTL = 0x0dac # macro
|
|
regGRBM_GFX_CLKEN_CNTL_BASE_IDX = 0 # macro
|
|
regGRBM_WAIT_IDLE_CLOCKS = 0x0dad # macro
|
|
regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX = 0 # macro
|
|
regGRBM_STATUS_SE2 = 0x0dae # macro
|
|
regGRBM_STATUS_SE2_BASE_IDX = 0 # macro
|
|
regGRBM_STATUS_SE3 = 0x0daf # macro
|
|
regGRBM_STATUS_SE3_BASE_IDX = 0 # macro
|
|
regGRBM_STATUS_SE4 = 0x0db0 # macro
|
|
regGRBM_STATUS_SE4_BASE_IDX = 0 # macro
|
|
regGRBM_STATUS_SE5 = 0x0db1 # macro
|
|
regGRBM_STATUS_SE5_BASE_IDX = 0 # macro
|
|
regGRBM_READ_ERROR = 0x0db6 # macro
|
|
regGRBM_READ_ERROR_BASE_IDX = 0 # macro
|
|
regGRBM_READ_ERROR2 = 0x0db7 # macro
|
|
regGRBM_READ_ERROR2_BASE_IDX = 0 # macro
|
|
regGRBM_INT_CNTL = 0x0db8 # macro
|
|
regGRBM_INT_CNTL_BASE_IDX = 0 # macro
|
|
regGRBM_TRAP_OP = 0x0db9 # macro
|
|
regGRBM_TRAP_OP_BASE_IDX = 0 # macro
|
|
regGRBM_TRAP_ADDR = 0x0dba # macro
|
|
regGRBM_TRAP_ADDR_BASE_IDX = 0 # macro
|
|
regGRBM_TRAP_ADDR_MSK = 0x0dbb # macro
|
|
regGRBM_TRAP_ADDR_MSK_BASE_IDX = 0 # macro
|
|
regGRBM_TRAP_WD = 0x0dbc # macro
|
|
regGRBM_TRAP_WD_BASE_IDX = 0 # macro
|
|
regGRBM_TRAP_WD_MSK = 0x0dbd # macro
|
|
regGRBM_TRAP_WD_MSK_BASE_IDX = 0 # macro
|
|
regGRBM_DSM_BYPASS = 0x0dbe # macro
|
|
regGRBM_DSM_BYPASS_BASE_IDX = 0 # macro
|
|
regGRBM_WRITE_ERROR = 0x0dbf # macro
|
|
regGRBM_WRITE_ERROR_BASE_IDX = 0 # macro
|
|
regGRBM_CHIP_REVISION = 0x0dc1 # macro
|
|
regGRBM_CHIP_REVISION_BASE_IDX = 0 # macro
|
|
regGRBM_IH_CREDIT = 0x0dc4 # macro
|
|
regGRBM_IH_CREDIT_BASE_IDX = 0 # macro
|
|
regGRBM_PWR_CNTL2 = 0x0dc5 # macro
|
|
regGRBM_PWR_CNTL2_BASE_IDX = 0 # macro
|
|
regGRBM_UTCL2_INVAL_RANGE_START = 0x0dc6 # macro
|
|
regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX = 0 # macro
|
|
regGRBM_UTCL2_INVAL_RANGE_END = 0x0dc7 # macro
|
|
regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX = 0 # macro
|
|
regGRBM_INVALID_PIPE = 0x0dc9 # macro
|
|
regGRBM_INVALID_PIPE_BASE_IDX = 0 # macro
|
|
regGRBM_FENCE_RANGE0 = 0x0dca # macro
|
|
regGRBM_FENCE_RANGE0_BASE_IDX = 0 # macro
|
|
regGRBM_FENCE_RANGE1 = 0x0dcb # macro
|
|
regGRBM_FENCE_RANGE1_BASE_IDX = 0 # macro
|
|
regGRBM_SCRATCH_REG0 = 0x0de0 # macro
|
|
regGRBM_SCRATCH_REG0_BASE_IDX = 0 # macro
|
|
regGRBM_SCRATCH_REG1 = 0x0de1 # macro
|
|
regGRBM_SCRATCH_REG1_BASE_IDX = 0 # macro
|
|
regGRBM_SCRATCH_REG2 = 0x0de2 # macro
|
|
regGRBM_SCRATCH_REG2_BASE_IDX = 0 # macro
|
|
regGRBM_SCRATCH_REG3 = 0x0de3 # macro
|
|
regGRBM_SCRATCH_REG3_BASE_IDX = 0 # macro
|
|
regGRBM_SCRATCH_REG4 = 0x0de4 # macro
|
|
regGRBM_SCRATCH_REG4_BASE_IDX = 0 # macro
|
|
regGRBM_SCRATCH_REG5 = 0x0de5 # macro
|
|
regGRBM_SCRATCH_REG5_BASE_IDX = 0 # macro
|
|
regGRBM_SCRATCH_REG6 = 0x0de6 # macro
|
|
regGRBM_SCRATCH_REG6_BASE_IDX = 0 # macro
|
|
regGRBM_SCRATCH_REG7 = 0x0de7 # macro
|
|
regGRBM_SCRATCH_REG7_BASE_IDX = 0 # macro
|
|
regVIOLATION_DATA_ASYNC_VF_PROG = 0x0df1 # macro
|
|
regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX = 0 # macro
|
|
regCP_CPC_DEBUG_CNTL = 0x0e20 # macro
|
|
regCP_CPC_DEBUG_CNTL_BASE_IDX = 0 # macro
|
|
regCP_CPC_DEBUG_DATA = 0x0e21 # macro
|
|
regCP_CPC_DEBUG_DATA_BASE_IDX = 0 # macro
|
|
regCP_CPC_STATUS = 0x0e24 # macro
|
|
regCP_CPC_STATUS_BASE_IDX = 0 # macro
|
|
regCP_CPC_BUSY_STAT = 0x0e25 # macro
|
|
regCP_CPC_BUSY_STAT_BASE_IDX = 0 # macro
|
|
regCP_CPC_STALLED_STAT1 = 0x0e26 # macro
|
|
regCP_CPC_STALLED_STAT1_BASE_IDX = 0 # macro
|
|
regCP_CPF_STATUS = 0x0e27 # macro
|
|
regCP_CPF_STATUS_BASE_IDX = 0 # macro
|
|
regCP_CPF_BUSY_STAT = 0x0e28 # macro
|
|
regCP_CPF_BUSY_STAT_BASE_IDX = 0 # macro
|
|
regCP_CPF_STALLED_STAT1 = 0x0e29 # macro
|
|
regCP_CPF_STALLED_STAT1_BASE_IDX = 0 # macro
|
|
regCP_CPC_BUSY_STAT2 = 0x0e2a # macro
|
|
regCP_CPC_BUSY_STAT2_BASE_IDX = 0 # macro
|
|
regCP_CPC_GRBM_FREE_COUNT = 0x0e2b # macro
|
|
regCP_CPC_GRBM_FREE_COUNT_BASE_IDX = 0 # macro
|
|
regCP_CPC_PRIV_VIOLATION_ADDR = 0x0e2c # macro
|
|
regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro
|
|
regCP_MEC_ME1_HEADER_DUMP = 0x0e2e # macro
|
|
regCP_MEC_ME1_HEADER_DUMP_BASE_IDX = 0 # macro
|
|
regCP_MEC_ME2_HEADER_DUMP = 0x0e2f # macro
|
|
regCP_MEC_ME2_HEADER_DUMP_BASE_IDX = 0 # macro
|
|
regCP_CPC_SCRATCH_INDEX = 0x0e30 # macro
|
|
regCP_CPC_SCRATCH_INDEX_BASE_IDX = 0 # macro
|
|
regCP_CPC_SCRATCH_DATA = 0x0e31 # macro
|
|
regCP_CPC_SCRATCH_DATA_BASE_IDX = 0 # macro
|
|
regCP_CPF_GRBM_FREE_COUNT = 0x0e32 # macro
|
|
regCP_CPF_GRBM_FREE_COUNT_BASE_IDX = 0 # macro
|
|
regCP_CPF_BUSY_STAT2 = 0x0e33 # macro
|
|
regCP_CPF_BUSY_STAT2_BASE_IDX = 0 # macro
|
|
regCP_CPC_HALT_HYST_COUNT = 0x0e47 # macro
|
|
regCP_CPC_HALT_HYST_COUNT_BASE_IDX = 0 # macro
|
|
regCP_STALLED_STAT3 = 0x0f3c # macro
|
|
regCP_STALLED_STAT3_BASE_IDX = 0 # macro
|
|
regCP_STALLED_STAT1 = 0x0f3d # macro
|
|
regCP_STALLED_STAT1_BASE_IDX = 0 # macro
|
|
regCP_STALLED_STAT2 = 0x0f3e # macro
|
|
regCP_STALLED_STAT2_BASE_IDX = 0 # macro
|
|
regCP_BUSY_STAT = 0x0f3f # macro
|
|
regCP_BUSY_STAT_BASE_IDX = 0 # macro
|
|
regCP_STAT = 0x0f40 # macro
|
|
regCP_STAT_BASE_IDX = 0 # macro
|
|
regCP_ME_HEADER_DUMP = 0x0f41 # macro
|
|
regCP_ME_HEADER_DUMP_BASE_IDX = 0 # macro
|
|
regCP_PFP_HEADER_DUMP = 0x0f42 # macro
|
|
regCP_PFP_HEADER_DUMP_BASE_IDX = 0 # macro
|
|
regCP_GRBM_FREE_COUNT = 0x0f43 # macro
|
|
regCP_GRBM_FREE_COUNT_BASE_IDX = 0 # macro
|
|
regCP_PFP_INSTR_PNTR = 0x0f45 # macro
|
|
regCP_PFP_INSTR_PNTR_BASE_IDX = 0 # macro
|
|
regCP_ME_INSTR_PNTR = 0x0f46 # macro
|
|
regCP_ME_INSTR_PNTR_BASE_IDX = 0 # macro
|
|
regCP_MEC1_INSTR_PNTR = 0x0f48 # macro
|
|
regCP_MEC1_INSTR_PNTR_BASE_IDX = 0 # macro
|
|
regCP_MEC2_INSTR_PNTR = 0x0f49 # macro
|
|
regCP_MEC2_INSTR_PNTR_BASE_IDX = 0 # macro
|
|
regCP_CSF_STAT = 0x0f54 # macro
|
|
regCP_CSF_STAT_BASE_IDX = 0 # macro
|
|
regCP_CNTX_STAT = 0x0f58 # macro
|
|
regCP_CNTX_STAT_BASE_IDX = 0 # macro
|
|
regCP_ME_PREEMPTION = 0x0f59 # macro
|
|
regCP_ME_PREEMPTION_BASE_IDX = 0 # macro
|
|
regCP_RB1_RPTR = 0x0f5f # macro
|
|
regCP_RB1_RPTR_BASE_IDX = 0 # macro
|
|
regCP_RB0_RPTR = 0x0f60 # macro
|
|
regCP_RB0_RPTR_BASE_IDX = 0 # macro
|
|
regCP_RB_RPTR = 0x0f60 # macro
|
|
regCP_RB_RPTR_BASE_IDX = 0 # macro
|
|
regCP_RB_WPTR_DELAY = 0x0f61 # macro
|
|
regCP_RB_WPTR_DELAY_BASE_IDX = 0 # macro
|
|
regCP_RB_WPTR_POLL_CNTL = 0x0f62 # macro
|
|
regCP_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
|
|
regCP_ROQ1_THRESHOLDS = 0x0f75 # macro
|
|
regCP_ROQ1_THRESHOLDS_BASE_IDX = 0 # macro
|
|
regCP_ROQ2_THRESHOLDS = 0x0f76 # macro
|
|
regCP_ROQ2_THRESHOLDS_BASE_IDX = 0 # macro
|
|
regCP_STQ_THRESHOLDS = 0x0f77 # macro
|
|
regCP_STQ_THRESHOLDS_BASE_IDX = 0 # macro
|
|
regCP_MEQ_THRESHOLDS = 0x0f79 # macro
|
|
regCP_MEQ_THRESHOLDS_BASE_IDX = 0 # macro
|
|
regCP_ROQ_AVAIL = 0x0f7a # macro
|
|
regCP_ROQ_AVAIL_BASE_IDX = 0 # macro
|
|
regCP_STQ_AVAIL = 0x0f7b # macro
|
|
regCP_STQ_AVAIL_BASE_IDX = 0 # macro
|
|
regCP_ROQ2_AVAIL = 0x0f7c # macro
|
|
regCP_ROQ2_AVAIL_BASE_IDX = 0 # macro
|
|
regCP_MEQ_AVAIL = 0x0f7d # macro
|
|
regCP_MEQ_AVAIL_BASE_IDX = 0 # macro
|
|
regCP_CMD_INDEX = 0x0f7e # macro
|
|
regCP_CMD_INDEX_BASE_IDX = 0 # macro
|
|
regCP_CMD_DATA = 0x0f7f # macro
|
|
regCP_CMD_DATA_BASE_IDX = 0 # macro
|
|
regCP_ROQ_RB_STAT = 0x0f80 # macro
|
|
regCP_ROQ_RB_STAT_BASE_IDX = 0 # macro
|
|
regCP_ROQ_IB1_STAT = 0x0f81 # macro
|
|
regCP_ROQ_IB1_STAT_BASE_IDX = 0 # macro
|
|
regCP_ROQ_IB2_STAT = 0x0f82 # macro
|
|
regCP_ROQ_IB2_STAT_BASE_IDX = 0 # macro
|
|
regCP_STQ_STAT = 0x0f83 # macro
|
|
regCP_STQ_STAT_BASE_IDX = 0 # macro
|
|
regCP_STQ_WR_STAT = 0x0f84 # macro
|
|
regCP_STQ_WR_STAT_BASE_IDX = 0 # macro
|
|
regCP_MEQ_STAT = 0x0f85 # macro
|
|
regCP_MEQ_STAT_BASE_IDX = 0 # macro
|
|
regCP_ROQ3_THRESHOLDS = 0x0f8c # macro
|
|
regCP_ROQ3_THRESHOLDS_BASE_IDX = 0 # macro
|
|
regCP_ROQ_DB_STAT = 0x0f8d # macro
|
|
regCP_ROQ_DB_STAT_BASE_IDX = 0 # macro
|
|
regCP_DEBUG_CNTL = 0x0f98 # macro
|
|
regCP_DEBUG_CNTL_BASE_IDX = 0 # macro
|
|
regCP_DEBUG_DATA = 0x0f99 # macro
|
|
regCP_DEBUG_DATA_BASE_IDX = 0 # macro
|
|
regCP_PRIV_VIOLATION_ADDR = 0x0f9a # macro
|
|
regCP_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro
|
|
regVGT_DMA_DATA_FIFO_DEPTH = 0x0fcd # macro
|
|
regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX = 0 # macro
|
|
regVGT_DMA_REQ_FIFO_DEPTH = 0x0fce # macro
|
|
regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX = 0 # macro
|
|
regVGT_DRAW_INIT_FIFO_DEPTH = 0x0fcf # macro
|
|
regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX = 0 # macro
|
|
regVGT_MC_LAT_CNTL = 0x0fd6 # macro
|
|
regVGT_MC_LAT_CNTL_BASE_IDX = 0 # macro
|
|
regIA_UTCL1_STATUS_2 = 0x0fd7 # macro
|
|
regIA_UTCL1_STATUS_2_BASE_IDX = 0 # macro
|
|
regWD_CNTL_STATUS = 0x0fdf # macro
|
|
regWD_CNTL_STATUS_BASE_IDX = 0 # macro
|
|
regCC_GC_PRIM_CONFIG = 0x0fe0 # macro
|
|
regCC_GC_PRIM_CONFIG_BASE_IDX = 0 # macro
|
|
regWD_QOS = 0x0fe2 # macro
|
|
regWD_QOS_BASE_IDX = 0 # macro
|
|
regWD_UTCL1_CNTL = 0x0fe3 # macro
|
|
regWD_UTCL1_CNTL_BASE_IDX = 0 # macro
|
|
regWD_UTCL1_STATUS = 0x0fe4 # macro
|
|
regWD_UTCL1_STATUS_BASE_IDX = 0 # macro
|
|
regIA_UTCL1_CNTL = 0x0fe6 # macro
|
|
regIA_UTCL1_CNTL_BASE_IDX = 0 # macro
|
|
regIA_UTCL1_STATUS = 0x0fe7 # macro
|
|
regIA_UTCL1_STATUS_BASE_IDX = 0 # macro
|
|
regCC_GC_SA_UNIT_DISABLE = 0x0fe9 # macro
|
|
regCC_GC_SA_UNIT_DISABLE_BASE_IDX = 0 # macro
|
|
regGE_RATE_CNTL_1 = 0x0ff4 # macro
|
|
regGE_RATE_CNTL_1_BASE_IDX = 0 # macro
|
|
regGE_RATE_CNTL_2 = 0x0ff5 # macro
|
|
regGE_RATE_CNTL_2_BASE_IDX = 0 # macro
|
|
regVGT_SYS_CONFIG = 0x1003 # macro
|
|
regVGT_SYS_CONFIG_BASE_IDX = 0 # macro
|
|
regGE_PRIV_CONTROL = 0x1004 # macro
|
|
regGE_PRIV_CONTROL_BASE_IDX = 0 # macro
|
|
regGE_STATUS = 0x1005 # macro
|
|
regGE_STATUS_BASE_IDX = 0 # macro
|
|
regVGT_GS_MAX_WAVE_ID = 0x1009 # macro
|
|
regVGT_GS_MAX_WAVE_ID_BASE_IDX = 0 # macro
|
|
regGFX_PIPE_CONTROL = 0x100d # macro
|
|
regGFX_PIPE_CONTROL_BASE_IDX = 0 # macro
|
|
regCC_GC_SHADER_ARRAY_CONFIG = 0x100f # macro
|
|
regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX = 0 # macro
|
|
regGE2_SE_CNTL_STATUS = 0x1011 # macro
|
|
regGE2_SE_CNTL_STATUS_BASE_IDX = 0 # macro
|
|
regGE_SPI_IF_SAFE_REG = 0x1018 # macro
|
|
regGE_SPI_IF_SAFE_REG_BASE_IDX = 0 # macro
|
|
regGE_PA_IF_SAFE_REG = 0x1019 # macro
|
|
regGE_PA_IF_SAFE_REG_BASE_IDX = 0 # macro
|
|
regPA_CL_CNTL_STATUS = 0x1024 # macro
|
|
regPA_CL_CNTL_STATUS_BASE_IDX = 0 # macro
|
|
regPA_CL_ENHANCE = 0x1025 # macro
|
|
regPA_CL_ENHANCE_BASE_IDX = 0 # macro
|
|
regPA_SU_CNTL_STATUS = 0x1034 # macro
|
|
regPA_SU_CNTL_STATUS_BASE_IDX = 0 # macro
|
|
regPA_SC_FIFO_DEPTH_CNTL = 0x1035 # macro
|
|
regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX = 0 # macro
|
|
regSQ_CONFIG = 0x10a0 # macro
|
|
regSQ_CONFIG_BASE_IDX = 0 # macro
|
|
regSQC_CONFIG = 0x10a1 # macro
|
|
regSQC_CONFIG_BASE_IDX = 0 # macro
|
|
regLDS_CONFIG = 0x10a2 # macro
|
|
regLDS_CONFIG_BASE_IDX = 0 # macro
|
|
regSQ_RANDOM_WAVE_PRI = 0x10a3 # macro
|
|
regSQ_RANDOM_WAVE_PRI_BASE_IDX = 0 # macro
|
|
regSQG_STATUS = 0x10a4 # macro
|
|
regSQG_STATUS_BASE_IDX = 0 # macro
|
|
regSQ_FIFO_SIZES = 0x10a5 # macro
|
|
regSQ_FIFO_SIZES_BASE_IDX = 0 # macro
|
|
regSQ_DSM_CNTL = 0x10a6 # macro
|
|
regSQ_DSM_CNTL_BASE_IDX = 0 # macro
|
|
regSQ_DSM_CNTL2 = 0x10a7 # macro
|
|
regSQ_DSM_CNTL2_BASE_IDX = 0 # macro
|
|
regSP_CONFIG = 0x10ab # macro
|
|
regSP_CONFIG_BASE_IDX = 0 # macro
|
|
regSQ_ARB_CONFIG = 0x10ac # macro
|
|
regSQ_ARB_CONFIG_BASE_IDX = 0 # macro
|
|
regSQ_DEBUG_HOST_TRAP_STATUS = 0x10b6 # macro
|
|
regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX = 0 # macro
|
|
regSQG_GL1H_STATUS = 0x10b9 # macro
|
|
regSQG_GL1H_STATUS_BASE_IDX = 0 # macro
|
|
regSQG_CONFIG = 0x10ba # macro
|
|
regSQG_CONFIG_BASE_IDX = 0 # macro
|
|
regSQ_PERF_SNAPSHOT_CTRL = 0x10bb # macro
|
|
regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX = 0 # macro
|
|
regCC_GC_SHADER_RATE_CONFIG = 0x10bc # macro
|
|
regCC_GC_SHADER_RATE_CONFIG_BASE_IDX = 0 # macro
|
|
regSQ_INTERRUPT_AUTO_MASK = 0x10be # macro
|
|
regSQ_INTERRUPT_AUTO_MASK_BASE_IDX = 0 # macro
|
|
regSQ_INTERRUPT_MSG_CTRL = 0x10bf # macro
|
|
regSQ_INTERRUPT_MSG_CTRL_BASE_IDX = 0 # macro
|
|
regSQ_WATCH0_ADDR_H = 0x10d0 # macro
|
|
regSQ_WATCH0_ADDR_H_BASE_IDX = 0 # macro
|
|
regSQ_WATCH0_ADDR_L = 0x10d1 # macro
|
|
regSQ_WATCH0_ADDR_L_BASE_IDX = 0 # macro
|
|
regSQ_WATCH0_CNTL = 0x10d2 # macro
|
|
regSQ_WATCH0_CNTL_BASE_IDX = 0 # macro
|
|
regSQ_WATCH1_ADDR_H = 0x10d3 # macro
|
|
regSQ_WATCH1_ADDR_H_BASE_IDX = 0 # macro
|
|
regSQ_WATCH1_ADDR_L = 0x10d4 # macro
|
|
regSQ_WATCH1_ADDR_L_BASE_IDX = 0 # macro
|
|
regSQ_WATCH1_CNTL = 0x10d5 # macro
|
|
regSQ_WATCH1_CNTL_BASE_IDX = 0 # macro
|
|
regSQ_WATCH2_ADDR_H = 0x10d6 # macro
|
|
regSQ_WATCH2_ADDR_H_BASE_IDX = 0 # macro
|
|
regSQ_WATCH2_ADDR_L = 0x10d7 # macro
|
|
regSQ_WATCH2_ADDR_L_BASE_IDX = 0 # macro
|
|
regSQ_WATCH2_CNTL = 0x10d8 # macro
|
|
regSQ_WATCH2_CNTL_BASE_IDX = 0 # macro
|
|
regSQ_WATCH3_ADDR_H = 0x10d9 # macro
|
|
regSQ_WATCH3_ADDR_H_BASE_IDX = 0 # macro
|
|
regSQ_WATCH3_ADDR_L = 0x10da # macro
|
|
regSQ_WATCH3_ADDR_L_BASE_IDX = 0 # macro
|
|
regSQ_WATCH3_CNTL = 0x10db # macro
|
|
regSQ_WATCH3_CNTL_BASE_IDX = 0 # macro
|
|
regSQ_IND_INDEX = 0x1118 # macro
|
|
regSQ_IND_INDEX_BASE_IDX = 0 # macro
|
|
regSQ_IND_DATA = 0x1119 # macro
|
|
regSQ_IND_DATA_BASE_IDX = 0 # macro
|
|
regSQ_CMD = 0x111b # macro
|
|
regSQ_CMD_BASE_IDX = 0 # macro
|
|
regSX_DEBUG_1 = 0x11b8 # macro
|
|
regSX_DEBUG_1_BASE_IDX = 0 # macro
|
|
regSPI_PS_MAX_WAVE_ID = 0x11da # macro
|
|
regSPI_PS_MAX_WAVE_ID_BASE_IDX = 0 # macro
|
|
regSPI_GFX_CNTL = 0x11dc # macro
|
|
regSPI_GFX_CNTL_BASE_IDX = 0 # macro
|
|
regSPI_DSM_CNTL = 0x11e3 # macro
|
|
regSPI_DSM_CNTL_BASE_IDX = 0 # macro
|
|
regSPI_DSM_CNTL2 = 0x11e4 # macro
|
|
regSPI_DSM_CNTL2_BASE_IDX = 0 # macro
|
|
regSPI_EDC_CNT = 0x11e5 # macro
|
|
regSPI_EDC_CNT_BASE_IDX = 0 # macro
|
|
regSPI_CONFIG_PS_CU_EN = 0x11f2 # macro
|
|
regSPI_CONFIG_PS_CU_EN_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_CNTL = 0x124a # macro
|
|
regSPI_WF_LIFETIME_CNTL_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_LIMIT_0 = 0x124b # macro
|
|
regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_LIMIT_1 = 0x124c # macro
|
|
regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_LIMIT_2 = 0x124d # macro
|
|
regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_LIMIT_3 = 0x124e # macro
|
|
regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_LIMIT_4 = 0x124f # macro
|
|
regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_LIMIT_5 = 0x1250 # macro
|
|
regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_0 = 0x1255 # macro
|
|
regSPI_WF_LIFETIME_STATUS_0_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_2 = 0x1257 # macro
|
|
regSPI_WF_LIFETIME_STATUS_2_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_4 = 0x1259 # macro
|
|
regSPI_WF_LIFETIME_STATUS_4_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_6 = 0x125b # macro
|
|
regSPI_WF_LIFETIME_STATUS_6_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_7 = 0x125c # macro
|
|
regSPI_WF_LIFETIME_STATUS_7_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_9 = 0x125e # macro
|
|
regSPI_WF_LIFETIME_STATUS_9_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_11 = 0x1260 # macro
|
|
regSPI_WF_LIFETIME_STATUS_11_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_13 = 0x1262 # macro
|
|
regSPI_WF_LIFETIME_STATUS_13_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_14 = 0x1263 # macro
|
|
regSPI_WF_LIFETIME_STATUS_14_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_15 = 0x1264 # macro
|
|
regSPI_WF_LIFETIME_STATUS_15_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_16 = 0x1265 # macro
|
|
regSPI_WF_LIFETIME_STATUS_16_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_17 = 0x1266 # macro
|
|
regSPI_WF_LIFETIME_STATUS_17_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_18 = 0x1267 # macro
|
|
regSPI_WF_LIFETIME_STATUS_18_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_19 = 0x1268 # macro
|
|
regSPI_WF_LIFETIME_STATUS_19_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_20 = 0x1269 # macro
|
|
regSPI_WF_LIFETIME_STATUS_20_BASE_IDX = 0 # macro
|
|
regSPI_WF_LIFETIME_STATUS_21 = 0x126b # macro
|
|
regSPI_WF_LIFETIME_STATUS_21_BASE_IDX = 0 # macro
|
|
regSPI_LB_CTR_CTRL = 0x1274 # macro
|
|
regSPI_LB_CTR_CTRL_BASE_IDX = 0 # macro
|
|
regSPI_LB_WGP_MASK = 0x1275 # macro
|
|
regSPI_LB_WGP_MASK_BASE_IDX = 0 # macro
|
|
regSPI_LB_DATA_REG = 0x1276 # macro
|
|
regSPI_LB_DATA_REG_BASE_IDX = 0 # macro
|
|
regSPI_PG_ENABLE_STATIC_WGP_MASK = 0x1277 # macro
|
|
regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX = 0 # macro
|
|
regSPI_GDS_CREDITS = 0x1278 # macro
|
|
regSPI_GDS_CREDITS_BASE_IDX = 0 # macro
|
|
regSPI_SX_EXPORT_BUFFER_SIZES = 0x1279 # macro
|
|
regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX = 0 # macro
|
|
regSPI_SX_SCOREBOARD_BUFFER_SIZES = 0x127a # macro
|
|
regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX = 0 # macro
|
|
regSPI_CSQ_WF_ACTIVE_STATUS = 0x127b # macro
|
|
regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX = 0 # macro
|
|
regSPI_CSQ_WF_ACTIVE_COUNT_0 = 0x127c # macro
|
|
regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX = 0 # macro
|
|
regSPI_CSQ_WF_ACTIVE_COUNT_1 = 0x127d # macro
|
|
regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX = 0 # macro
|
|
regSPI_CSQ_WF_ACTIVE_COUNT_2 = 0x127e # macro
|
|
regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX = 0 # macro
|
|
regSPI_CSQ_WF_ACTIVE_COUNT_3 = 0x127f # macro
|
|
regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX = 0 # macro
|
|
regSPI_LB_DATA_WAVES = 0x1284 # macro
|
|
regSPI_LB_DATA_WAVES_BASE_IDX = 0 # macro
|
|
regSPI_P0_TRAP_SCREEN_PSBA_LO = 0x128c # macro
|
|
regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro
|
|
regSPI_P0_TRAP_SCREEN_PSBA_HI = 0x128d # macro
|
|
regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro
|
|
regSPI_P0_TRAP_SCREEN_PSMA_LO = 0x128e # macro
|
|
regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro
|
|
regSPI_P0_TRAP_SCREEN_PSMA_HI = 0x128f # macro
|
|
regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro
|
|
regSPI_P0_TRAP_SCREEN_GPR_MIN = 0x1290 # macro
|
|
regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro
|
|
regSPI_P1_TRAP_SCREEN_PSBA_LO = 0x1291 # macro
|
|
regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro
|
|
regSPI_P1_TRAP_SCREEN_PSBA_HI = 0x1292 # macro
|
|
regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro
|
|
regSPI_P1_TRAP_SCREEN_PSMA_LO = 0x1293 # macro
|
|
regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro
|
|
regSPI_P1_TRAP_SCREEN_PSMA_HI = 0x1294 # macro
|
|
regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro
|
|
regSPI_P1_TRAP_SCREEN_GPR_MIN = 0x1295 # macro
|
|
regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro
|
|
regTD_STATUS = 0x12c6 # macro
|
|
regTD_STATUS_BASE_IDX = 0 # macro
|
|
regTD_DSM_CNTL = 0x12cf # macro
|
|
regTD_DSM_CNTL_BASE_IDX = 0 # macro
|
|
regTD_DSM_CNTL2 = 0x12d0 # macro
|
|
regTD_DSM_CNTL2_BASE_IDX = 0 # macro
|
|
regTD_SCRATCH = 0x12d3 # macro
|
|
regTD_SCRATCH_BASE_IDX = 0 # macro
|
|
regTA_CNTL = 0x12e1 # macro
|
|
regTA_CNTL_BASE_IDX = 0 # macro
|
|
regTA_CNTL_AUX = 0x12e2 # macro
|
|
regTA_CNTL_AUX_BASE_IDX = 0 # macro
|
|
regTA_CNTL2 = 0x12e5 # macro
|
|
regTA_CNTL2_BASE_IDX = 0 # macro
|
|
regTA_STATUS = 0x12e8 # macro
|
|
regTA_STATUS_BASE_IDX = 0 # macro
|
|
regTA_SCRATCH = 0x1304 # macro
|
|
regTA_SCRATCH_BASE_IDX = 0 # macro
|
|
regGDS_CONFIG = 0x1360 # macro
|
|
regGDS_CONFIG_BASE_IDX = 0 # macro
|
|
regGDS_CNTL_STATUS = 0x1361 # macro
|
|
regGDS_CNTL_STATUS_BASE_IDX = 0 # macro
|
|
regGDS_ENHANCE = 0x1362 # macro
|
|
regGDS_ENHANCE_BASE_IDX = 0 # macro
|
|
regGDS_PROTECTION_FAULT = 0x1363 # macro
|
|
regGDS_PROTECTION_FAULT_BASE_IDX = 0 # macro
|
|
regGDS_VM_PROTECTION_FAULT = 0x1364 # macro
|
|
regGDS_VM_PROTECTION_FAULT_BASE_IDX = 0 # macro
|
|
regGDS_EDC_CNT = 0x1365 # macro
|
|
regGDS_EDC_CNT_BASE_IDX = 0 # macro
|
|
regGDS_EDC_GRBM_CNT = 0x1366 # macro
|
|
regGDS_EDC_GRBM_CNT_BASE_IDX = 0 # macro
|
|
regGDS_EDC_OA_DED = 0x1367 # macro
|
|
regGDS_EDC_OA_DED_BASE_IDX = 0 # macro
|
|
regGDS_DSM_CNTL = 0x136a # macro
|
|
regGDS_DSM_CNTL_BASE_IDX = 0 # macro
|
|
regGDS_EDC_OA_PHY_CNT = 0x136b # macro
|
|
regGDS_EDC_OA_PHY_CNT_BASE_IDX = 0 # macro
|
|
regGDS_EDC_OA_PIPE_CNT = 0x136c # macro
|
|
regGDS_EDC_OA_PIPE_CNT_BASE_IDX = 0 # macro
|
|
regGDS_DSM_CNTL2 = 0x136d # macro
|
|
regGDS_DSM_CNTL2_BASE_IDX = 0 # macro
|
|
regDB_DEBUG = 0x13ac # macro
|
|
regDB_DEBUG_BASE_IDX = 0 # macro
|
|
regDB_DEBUG2 = 0x13ad # macro
|
|
regDB_DEBUG2_BASE_IDX = 0 # macro
|
|
regDB_DEBUG3 = 0x13ae # macro
|
|
regDB_DEBUG3_BASE_IDX = 0 # macro
|
|
regDB_DEBUG4 = 0x13af # macro
|
|
regDB_DEBUG4_BASE_IDX = 0 # macro
|
|
regDB_ETILE_STUTTER_CONTROL = 0x13b0 # macro
|
|
regDB_ETILE_STUTTER_CONTROL_BASE_IDX = 0 # macro
|
|
regDB_LTILE_STUTTER_CONTROL = 0x13b1 # macro
|
|
regDB_LTILE_STUTTER_CONTROL_BASE_IDX = 0 # macro
|
|
regDB_EQUAD_STUTTER_CONTROL = 0x13b2 # macro
|
|
regDB_EQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro
|
|
regDB_LQUAD_STUTTER_CONTROL = 0x13b3 # macro
|
|
regDB_LQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro
|
|
regDB_CREDIT_LIMIT = 0x13b4 # macro
|
|
regDB_CREDIT_LIMIT_BASE_IDX = 0 # macro
|
|
regDB_WATERMARKS = 0x13b5 # macro
|
|
regDB_WATERMARKS_BASE_IDX = 0 # macro
|
|
regDB_SUBTILE_CONTROL = 0x13b6 # macro
|
|
regDB_SUBTILE_CONTROL_BASE_IDX = 0 # macro
|
|
regDB_FREE_CACHELINES = 0x13b7 # macro
|
|
regDB_FREE_CACHELINES_BASE_IDX = 0 # macro
|
|
regDB_FIFO_DEPTH1 = 0x13b8 # macro
|
|
regDB_FIFO_DEPTH1_BASE_IDX = 0 # macro
|
|
regDB_FIFO_DEPTH2 = 0x13b9 # macro
|
|
regDB_FIFO_DEPTH2_BASE_IDX = 0 # macro
|
|
regDB_LAST_OF_BURST_CONFIG = 0x13ba # macro
|
|
regDB_LAST_OF_BURST_CONFIG_BASE_IDX = 0 # macro
|
|
regDB_RING_CONTROL = 0x13bb # macro
|
|
regDB_RING_CONTROL_BASE_IDX = 0 # macro
|
|
regDB_MEM_ARB_WATERMARKS = 0x13bc # macro
|
|
regDB_MEM_ARB_WATERMARKS_BASE_IDX = 0 # macro
|
|
regDB_FIFO_DEPTH3 = 0x13bd # macro
|
|
regDB_FIFO_DEPTH3_BASE_IDX = 0 # macro
|
|
regDB_DEBUG6 = 0x13be # macro
|
|
regDB_DEBUG6_BASE_IDX = 0 # macro
|
|
regDB_EXCEPTION_CONTROL = 0x13bf # macro
|
|
regDB_EXCEPTION_CONTROL_BASE_IDX = 0 # macro
|
|
regDB_DEBUG7 = 0x13d0 # macro
|
|
regDB_DEBUG7_BASE_IDX = 0 # macro
|
|
regDB_DEBUG5 = 0x13d1 # macro
|
|
regDB_DEBUG5_BASE_IDX = 0 # macro
|
|
regDB_FGCG_SRAMS_CLK_CTRL = 0x13d7 # macro
|
|
regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX = 0 # macro
|
|
regDB_FGCG_INTERFACES_CLK_CTRL = 0x13d8 # macro
|
|
regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX = 0 # macro
|
|
regDB_FIFO_DEPTH4 = 0x13d9 # macro
|
|
regDB_FIFO_DEPTH4_BASE_IDX = 0 # macro
|
|
regCC_RB_REDUNDANCY = 0x13dc # macro
|
|
regCC_RB_REDUNDANCY_BASE_IDX = 0 # macro
|
|
regCC_RB_BACKEND_DISABLE = 0x13dd # macro
|
|
regCC_RB_BACKEND_DISABLE_BASE_IDX = 0 # macro
|
|
regGB_ADDR_CONFIG = 0x13de # macro
|
|
regGB_ADDR_CONFIG_BASE_IDX = 0 # macro
|
|
regGB_BACKEND_MAP = 0x13df # macro
|
|
regGB_BACKEND_MAP_BASE_IDX = 0 # macro
|
|
regGB_GPU_ID = 0x13e0 # macro
|
|
regGB_GPU_ID_BASE_IDX = 0 # macro
|
|
regCC_RB_DAISY_CHAIN = 0x13e1 # macro
|
|
regCC_RB_DAISY_CHAIN_BASE_IDX = 0 # macro
|
|
regGB_ADDR_CONFIG_READ = 0x13e2 # macro
|
|
regGB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro
|
|
regCB_HW_CONTROL_4 = 0x1422 # macro
|
|
regCB_HW_CONTROL_4_BASE_IDX = 0 # macro
|
|
regCB_HW_CONTROL_3 = 0x1423 # macro
|
|
regCB_HW_CONTROL_3_BASE_IDX = 0 # macro
|
|
regCB_HW_CONTROL = 0x1424 # macro
|
|
regCB_HW_CONTROL_BASE_IDX = 0 # macro
|
|
regCB_HW_CONTROL_1 = 0x1425 # macro
|
|
regCB_HW_CONTROL_1_BASE_IDX = 0 # macro
|
|
regCB_HW_CONTROL_2 = 0x1426 # macro
|
|
regCB_HW_CONTROL_2_BASE_IDX = 0 # macro
|
|
regCB_DCC_CONFIG = 0x1427 # macro
|
|
regCB_DCC_CONFIG_BASE_IDX = 0 # macro
|
|
regCB_HW_MEM_ARBITER_RD = 0x1428 # macro
|
|
regCB_HW_MEM_ARBITER_RD_BASE_IDX = 0 # macro
|
|
regCB_HW_MEM_ARBITER_WR = 0x1429 # macro
|
|
regCB_HW_MEM_ARBITER_WR_BASE_IDX = 0 # macro
|
|
regCB_FGCG_SRAM_OVERRIDE = 0x142a # macro
|
|
regCB_FGCG_SRAM_OVERRIDE_BASE_IDX = 0 # macro
|
|
regCB_DCC_CONFIG2 = 0x142b # macro
|
|
regCB_DCC_CONFIG2_BASE_IDX = 0 # macro
|
|
regCHICKEN_BITS = 0x142d # macro
|
|
regCHICKEN_BITS_BASE_IDX = 0 # macro
|
|
regCB_CACHE_EVICT_POINTS = 0x142e # macro
|
|
regCB_CACHE_EVICT_POINTS_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_RD_CLI2GRP_MAP0 = 0x17a0 # macro
|
|
regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_RD_CLI2GRP_MAP1 = 0x17a1 # macro
|
|
regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_WR_CLI2GRP_MAP0 = 0x17a2 # macro
|
|
regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_WR_CLI2GRP_MAP1 = 0x17a3 # macro
|
|
regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_RD_GRP2VC_MAP = 0x17a4 # macro
|
|
regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_WR_GRP2VC_MAP = 0x17a5 # macro
|
|
regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_RD_LAZY = 0x17a6 # macro
|
|
regGCEA_DRAM_RD_LAZY_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_WR_LAZY = 0x17a7 # macro
|
|
regGCEA_DRAM_WR_LAZY_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_RD_CAM_CNTL = 0x17a8 # macro
|
|
regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_WR_CAM_CNTL = 0x17a9 # macro
|
|
regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_PAGE_BURST = 0x17aa # macro
|
|
regGCEA_DRAM_PAGE_BURST_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_RD_PRI_AGE = 0x17ab # macro
|
|
regGCEA_DRAM_RD_PRI_AGE_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_WR_PRI_AGE = 0x17ac # macro
|
|
regGCEA_DRAM_WR_PRI_AGE_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_RD_PRI_QUEUING = 0x17ad # macro
|
|
regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_WR_PRI_QUEUING = 0x17ae # macro
|
|
regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_RD_PRI_FIXED = 0x17af # macro
|
|
regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_WR_PRI_FIXED = 0x17b0 # macro
|
|
regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_RD_PRI_URGENCY = 0x17b1 # macro
|
|
regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_WR_PRI_URGENCY = 0x17b2 # macro
|
|
regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_RD_PRI_QUANT_PRI1 = 0x17b3 # macro
|
|
regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_RD_PRI_QUANT_PRI2 = 0x17b4 # macro
|
|
regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_RD_PRI_QUANT_PRI3 = 0x17b5 # macro
|
|
regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_WR_PRI_QUANT_PRI1 = 0x17b6 # macro
|
|
regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_WR_PRI_QUANT_PRI2 = 0x17b7 # macro
|
|
regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro
|
|
regGCEA_DRAM_WR_PRI_QUANT_PRI3 = 0x17b8 # macro
|
|
regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro
|
|
regGCEA_IO_RD_CLI2GRP_MAP0 = 0x187d # macro
|
|
regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro
|
|
regGCEA_IO_RD_CLI2GRP_MAP1 = 0x187e # macro
|
|
regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro
|
|
regGCEA_IO_WR_CLI2GRP_MAP0 = 0x187f # macro
|
|
regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro
|
|
regGCEA_IO_WR_CLI2GRP_MAP1 = 0x1880 # macro
|
|
regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro
|
|
regGCEA_IO_RD_COMBINE_FLUSH = 0x1881 # macro
|
|
regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX = 0 # macro
|
|
regGCEA_IO_WR_COMBINE_FLUSH = 0x1882 # macro
|
|
regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX = 0 # macro
|
|
regGCEA_IO_GROUP_BURST = 0x1883 # macro
|
|
regGCEA_IO_GROUP_BURST_BASE_IDX = 0 # macro
|
|
regGCEA_IO_RD_PRI_AGE = 0x1884 # macro
|
|
regGCEA_IO_RD_PRI_AGE_BASE_IDX = 0 # macro
|
|
regGCEA_IO_WR_PRI_AGE = 0x1885 # macro
|
|
regGCEA_IO_WR_PRI_AGE_BASE_IDX = 0 # macro
|
|
regGCEA_IO_RD_PRI_QUEUING = 0x1886 # macro
|
|
regGCEA_IO_RD_PRI_QUEUING_BASE_IDX = 0 # macro
|
|
regGCEA_IO_WR_PRI_QUEUING = 0x1887 # macro
|
|
regGCEA_IO_WR_PRI_QUEUING_BASE_IDX = 0 # macro
|
|
regGCEA_IO_RD_PRI_FIXED = 0x1888 # macro
|
|
regGCEA_IO_RD_PRI_FIXED_BASE_IDX = 0 # macro
|
|
regGCEA_IO_WR_PRI_FIXED = 0x1889 # macro
|
|
regGCEA_IO_WR_PRI_FIXED_BASE_IDX = 0 # macro
|
|
regGCEA_IO_RD_PRI_URGENCY = 0x188a # macro
|
|
regGCEA_IO_RD_PRI_URGENCY_BASE_IDX = 0 # macro
|
|
regGCEA_IO_WR_PRI_URGENCY = 0x188b # macro
|
|
regGCEA_IO_WR_PRI_URGENCY_BASE_IDX = 0 # macro
|
|
regGCEA_IO_RD_PRI_URGENCY_MASKING = 0x188c # macro
|
|
regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro
|
|
regGCEA_IO_WR_PRI_URGENCY_MASKING = 0x188d # macro
|
|
regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro
|
|
regGCEA_IO_RD_PRI_QUANT_PRI1 = 0x188e # macro
|
|
regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro
|
|
regGCEA_IO_RD_PRI_QUANT_PRI2 = 0x188f # macro
|
|
regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro
|
|
regGCEA_IO_RD_PRI_QUANT_PRI3 = 0x1890 # macro
|
|
regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro
|
|
regGCEA_IO_WR_PRI_QUANT_PRI1 = 0x1891 # macro
|
|
regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro
|
|
regGCEA_IO_WR_PRI_QUANT_PRI2 = 0x1892 # macro
|
|
regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro
|
|
regGCEA_IO_WR_PRI_QUANT_PRI3 = 0x1893 # macro
|
|
regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro
|
|
regGCEA_SDP_ARB_FINAL = 0x1896 # macro
|
|
regGCEA_SDP_ARB_FINAL_BASE_IDX = 0 # macro
|
|
regGCEA_SDP_IO_PRIORITY = 0x1899 # macro
|
|
regGCEA_SDP_IO_PRIORITY_BASE_IDX = 0 # macro
|
|
regGCEA_SDP_CREDITS = 0x189a # macro
|
|
regGCEA_SDP_CREDITS_BASE_IDX = 0 # macro
|
|
regGCEA_SDP_TAG_RESERVE0 = 0x189b # macro
|
|
regGCEA_SDP_TAG_RESERVE0_BASE_IDX = 0 # macro
|
|
regGCEA_SDP_TAG_RESERVE1 = 0x189c # macro
|
|
regGCEA_SDP_TAG_RESERVE1_BASE_IDX = 0 # macro
|
|
regGCEA_SDP_VCC_RESERVE0 = 0x189d # macro
|
|
regGCEA_SDP_VCC_RESERVE0_BASE_IDX = 0 # macro
|
|
regGCEA_SDP_VCC_RESERVE1 = 0x189e # macro
|
|
regGCEA_SDP_VCC_RESERVE1_BASE_IDX = 0 # macro
|
|
regGCEA_MISC = 0x14a2 # macro
|
|
regGCEA_MISC_BASE_IDX = 0 # macro
|
|
regGCEA_LATENCY_SAMPLING = 0x14a3 # macro
|
|
regGCEA_LATENCY_SAMPLING_BASE_IDX = 0 # macro
|
|
regGCEA_MAM_CTRL2 = 0x14a9 # macro
|
|
regGCEA_MAM_CTRL2_BASE_IDX = 0 # macro
|
|
regGCEA_MAM_CTRL = 0x14ab # macro
|
|
regGCEA_MAM_CTRL_BASE_IDX = 0 # macro
|
|
regGCEA_EDC_CNT = 0x14b2 # macro
|
|
regGCEA_EDC_CNT_BASE_IDX = 0 # macro
|
|
regGCEA_EDC_CNT2 = 0x14b3 # macro
|
|
regGCEA_EDC_CNT2_BASE_IDX = 0 # macro
|
|
regGCEA_DSM_CNTL = 0x14b4 # macro
|
|
regGCEA_DSM_CNTL_BASE_IDX = 0 # macro
|
|
regGCEA_DSM_CNTLA = 0x14b5 # macro
|
|
regGCEA_DSM_CNTLA_BASE_IDX = 0 # macro
|
|
regGCEA_DSM_CNTLB = 0x14b6 # macro
|
|
regGCEA_DSM_CNTLB_BASE_IDX = 0 # macro
|
|
regGCEA_DSM_CNTL2 = 0x14b7 # macro
|
|
regGCEA_DSM_CNTL2_BASE_IDX = 0 # macro
|
|
regGCEA_DSM_CNTL2A = 0x14b8 # macro
|
|
regGCEA_DSM_CNTL2A_BASE_IDX = 0 # macro
|
|
regGCEA_DSM_CNTL2B = 0x14b9 # macro
|
|
regGCEA_DSM_CNTL2B_BASE_IDX = 0 # macro
|
|
regGCEA_GL2C_XBR_CREDITS = 0x14ba # macro
|
|
regGCEA_GL2C_XBR_CREDITS_BASE_IDX = 0 # macro
|
|
regGCEA_GL2C_XBR_MAXBURST = 0x14bb # macro
|
|
regGCEA_GL2C_XBR_MAXBURST_BASE_IDX = 0 # macro
|
|
regGCEA_PROBE_CNTL = 0x14bc # macro
|
|
regGCEA_PROBE_CNTL_BASE_IDX = 0 # macro
|
|
regGCEA_PROBE_MAP = 0x14bd # macro
|
|
regGCEA_PROBE_MAP_BASE_IDX = 0 # macro
|
|
regGCEA_ERR_STATUS = 0x14be # macro
|
|
regGCEA_ERR_STATUS_BASE_IDX = 0 # macro
|
|
regGCEA_MISC2 = 0x14bf # macro
|
|
regGCEA_MISC2_BASE_IDX = 0 # macro
|
|
regGCEA_RRET_MEM_RESERVE = 0x1518 # macro
|
|
regGCEA_RRET_MEM_RESERVE_BASE_IDX = 0 # macro
|
|
regGCEA_EDC_CNT3 = 0x151a # macro
|
|
regGCEA_EDC_CNT3_BASE_IDX = 0 # macro
|
|
regGCEA_SDP_ENABLE = 0x151e # macro
|
|
regGCEA_SDP_ENABLE_BASE_IDX = 0 # macro
|
|
regSPI_PQEV_CTRL = 0x14c0 # macro
|
|
regSPI_PQEV_CTRL_BASE_IDX = 0 # macro
|
|
regSPI_EXP_THROTTLE_CTRL = 0x14c3 # macro
|
|
regSPI_EXP_THROTTLE_CTRL_BASE_IDX = 0 # macro
|
|
regRMI_GENERAL_CNTL = 0x1880 # macro
|
|
regRMI_GENERAL_CNTL_BASE_IDX = 1 # macro
|
|
regRMI_GENERAL_CNTL1 = 0x1881 # macro
|
|
regRMI_GENERAL_CNTL1_BASE_IDX = 1 # macro
|
|
regRMI_GENERAL_STATUS = 0x1882 # macro
|
|
regRMI_GENERAL_STATUS_BASE_IDX = 1 # macro
|
|
regRMI_SUBBLOCK_STATUS0 = 0x1883 # macro
|
|
regRMI_SUBBLOCK_STATUS0_BASE_IDX = 1 # macro
|
|
regRMI_SUBBLOCK_STATUS1 = 0x1884 # macro
|
|
regRMI_SUBBLOCK_STATUS1_BASE_IDX = 1 # macro
|
|
regRMI_SUBBLOCK_STATUS2 = 0x1885 # macro
|
|
regRMI_SUBBLOCK_STATUS2_BASE_IDX = 1 # macro
|
|
regRMI_SUBBLOCK_STATUS3 = 0x1886 # macro
|
|
regRMI_SUBBLOCK_STATUS3_BASE_IDX = 1 # macro
|
|
regRMI_XBAR_CONFIG = 0x1887 # macro
|
|
regRMI_XBAR_CONFIG_BASE_IDX = 1 # macro
|
|
regRMI_PROBE_POP_LOGIC_CNTL = 0x1888 # macro
|
|
regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX = 1 # macro
|
|
regRMI_UTC_XNACK_N_MISC_CNTL = 0x1889 # macro
|
|
regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX = 1 # macro
|
|
regRMI_DEMUX_CNTL = 0x188a # macro
|
|
regRMI_DEMUX_CNTL_BASE_IDX = 1 # macro
|
|
regRMI_UTCL1_CNTL1 = 0x188b # macro
|
|
regRMI_UTCL1_CNTL1_BASE_IDX = 1 # macro
|
|
regRMI_UTCL1_CNTL2 = 0x188c # macro
|
|
regRMI_UTCL1_CNTL2_BASE_IDX = 1 # macro
|
|
regRMI_UTC_UNIT_CONFIG = 0x188d # macro
|
|
regRMI_UTC_UNIT_CONFIG_BASE_IDX = 1 # macro
|
|
regRMI_TCIW_FORMATTER0_CNTL = 0x188e # macro
|
|
regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX = 1 # macro
|
|
regRMI_TCIW_FORMATTER1_CNTL = 0x188f # macro
|
|
regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX = 1 # macro
|
|
regRMI_SCOREBOARD_CNTL = 0x1890 # macro
|
|
regRMI_SCOREBOARD_CNTL_BASE_IDX = 1 # macro
|
|
regRMI_SCOREBOARD_STATUS0 = 0x1891 # macro
|
|
regRMI_SCOREBOARD_STATUS0_BASE_IDX = 1 # macro
|
|
regRMI_SCOREBOARD_STATUS1 = 0x1892 # macro
|
|
regRMI_SCOREBOARD_STATUS1_BASE_IDX = 1 # macro
|
|
regRMI_SCOREBOARD_STATUS2 = 0x1893 # macro
|
|
regRMI_SCOREBOARD_STATUS2_BASE_IDX = 1 # macro
|
|
regRMI_XBAR_ARBITER_CONFIG = 0x1894 # macro
|
|
regRMI_XBAR_ARBITER_CONFIG_BASE_IDX = 1 # macro
|
|
regRMI_XBAR_ARBITER_CONFIG_1 = 0x1895 # macro
|
|
regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX = 1 # macro
|
|
regRMI_CLOCK_CNTRL = 0x1896 # macro
|
|
regRMI_CLOCK_CNTRL_BASE_IDX = 1 # macro
|
|
regRMI_UTCL1_STATUS = 0x1897 # macro
|
|
regRMI_UTCL1_STATUS_BASE_IDX = 1 # macro
|
|
regRMI_RB_GLX_CID_MAP = 0x1898 # macro
|
|
regRMI_RB_GLX_CID_MAP_BASE_IDX = 1 # macro
|
|
regRMI_SPARE = 0x189f # macro
|
|
regRMI_SPARE_BASE_IDX = 1 # macro
|
|
regRMI_SPARE_1 = 0x18a0 # macro
|
|
regRMI_SPARE_1_BASE_IDX = 1 # macro
|
|
regRMI_SPARE_2 = 0x18a1 # macro
|
|
regRMI_SPARE_2_BASE_IDX = 1 # macro
|
|
regCC_RMI_REDUNDANCY = 0x18a2 # macro
|
|
regCC_RMI_REDUNDANCY_BASE_IDX = 1 # macro
|
|
regGCR_PIO_CNTL = 0x1580 # macro
|
|
regGCR_PIO_CNTL_BASE_IDX = 0 # macro
|
|
regGCR_PIO_DATA = 0x1581 # macro
|
|
regGCR_PIO_DATA_BASE_IDX = 0 # macro
|
|
regPMM_CNTL = 0x1582 # macro
|
|
regPMM_CNTL_BASE_IDX = 0 # macro
|
|
regPMM_STATUS = 0x1583 # macro
|
|
regPMM_STATUS_BASE_IDX = 0 # macro
|
|
regUTCL1_CTRL_1 = 0x158c # macro
|
|
regUTCL1_CTRL_1_BASE_IDX = 0 # macro
|
|
regUTCL1_ALOG = 0x158f # macro
|
|
regUTCL1_ALOG_BASE_IDX = 0 # macro
|
|
regUTCL1_STATUS = 0x1594 # macro
|
|
regUTCL1_STATUS_BASE_IDX = 0 # macro
|
|
regGCMC_VM_NB_TOP_OF_DRAM_SLOT1 = 0x15a4 # macro
|
|
regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX = 0 # macro
|
|
regGCMC_VM_NB_LOWER_TOP_OF_DRAM2 = 0x15a5 # macro
|
|
regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX = 0 # macro
|
|
regGCMC_VM_NB_UPPER_TOP_OF_DRAM2 = 0x15a6 # macro
|
|
regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX = 0 # macro
|
|
regGCMC_VM_FB_OFFSET = 0x15a7 # macro
|
|
regGCMC_VM_FB_OFFSET_BASE_IDX = 0 # macro
|
|
regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x15a8 # macro
|
|
regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX = 0 # macro
|
|
regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x15a9 # macro
|
|
regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX = 0 # macro
|
|
regGCMC_VM_STEERING = 0x15aa # macro
|
|
regGCMC_VM_STEERING_BASE_IDX = 0 # macro
|
|
regGCMC_MEM_POWER_LS = 0x15ac # macro
|
|
regGCMC_MEM_POWER_LS_BASE_IDX = 0 # macro
|
|
regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START = 0x15ad # macro
|
|
regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX = 0 # macro
|
|
regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END = 0x15ae # macro
|
|
regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX = 0 # macro
|
|
regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START = 0x15af # macro
|
|
regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX = 0 # macro
|
|
regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END = 0x15b0 # macro
|
|
regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX = 0 # macro
|
|
regGCMC_VM_APT_CNTL = 0x15b1 # macro
|
|
regGCMC_VM_APT_CNTL_BASE_IDX = 0 # macro
|
|
regGCMC_VM_LOCAL_FB_ADDRESS_START = 0x15b2 # macro
|
|
regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX = 0 # macro
|
|
regGCMC_VM_LOCAL_FB_ADDRESS_END = 0x15b3 # macro
|
|
regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX = 0 # macro
|
|
regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL = 0x15b4 # macro
|
|
regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX = 0 # macro
|
|
regGCUTCL2_ICG_CTRL = 0x15b5 # macro
|
|
regGCUTCL2_ICG_CTRL_BASE_IDX = 0 # macro
|
|
regGCUTCL2_CGTT_BUSY_CTRL = 0x15b7 # macro
|
|
regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro
|
|
regGCMC_VM_FB_NOALLOC_CNTL = 0x15b8 # macro
|
|
regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX = 0 # macro
|
|
regGCUTCL2_HARVEST_BYPASS_GROUPS = 0x15b9 # macro
|
|
regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX = 0 # macro
|
|
regGCUTCL2_GROUP_RET_FAULT_STATUS = 0x15bb # macro
|
|
regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CNTL = 0x15bc # macro
|
|
regGCVM_L2_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CNTL2 = 0x15bd # macro
|
|
regGCVM_L2_CNTL2_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CNTL3 = 0x15be # macro
|
|
regGCVM_L2_CNTL3_BASE_IDX = 0 # macro
|
|
regGCVM_L2_STATUS = 0x15bf # macro
|
|
regGCVM_L2_STATUS_BASE_IDX = 0 # macro
|
|
regGCVM_DUMMY_PAGE_FAULT_CNTL = 0x15c0 # macro
|
|
regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 = 0x15c1 # macro
|
|
regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 = 0x15c2 # macro
|
|
regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_CNTL = 0x15c3 # macro
|
|
regGCVM_INVALIDATE_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_CNTL = 0x15c4 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_CNTL2 = 0x15c5 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX = 0 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_MM_CNTL3 = 0x15c6 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX = 0 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_MM_CNTL4 = 0x15c7 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX = 0 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_STATUS = 0x15c8 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX = 0 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_ADDR_LO32 = 0x15c9 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_ADDR_HI32 = 0x15ca # macro
|
|
regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 = 0x15cb # macro
|
|
regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 = 0x15cc # macro
|
|
regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 = 0x15ce # macro
|
|
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 = 0x15cf # macro
|
|
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 = 0x15d0 # macro
|
|
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 = 0x15d1 # macro
|
|
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 = 0x15d2 # macro
|
|
regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 = 0x15d3 # macro
|
|
regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CNTL4 = 0x15d4 # macro
|
|
regGCVM_L2_CNTL4_BASE_IDX = 0 # macro
|
|
regGCVM_L2_MM_GROUP_RT_CLASSES = 0x15d5 # macro
|
|
regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_BANK_SELECT_RESERVED_CID = 0x15d6 # macro
|
|
regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX = 0 # macro
|
|
regGCVM_L2_BANK_SELECT_RESERVED_CID2 = 0x15d7 # macro
|
|
regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CACHE_PARITY_CNTL = 0x15d8 # macro
|
|
regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_L2_ICG_CTRL = 0x15d9 # macro
|
|
regGCVM_L2_ICG_CTRL_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CNTL5 = 0x15da # macro
|
|
regGCVM_L2_CNTL5_BASE_IDX = 0 # macro
|
|
regGCVM_L2_GCR_CNTL = 0x15db # macro
|
|
regGCVM_L2_GCR_CNTL_BASE_IDX = 0 # macro
|
|
regGCVML2_WALKER_MACRO_THROTTLE_TIME = 0x15dc # macro
|
|
regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX = 0 # macro
|
|
regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT = 0x15dd # macro
|
|
regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro
|
|
regGCVML2_WALKER_MICRO_THROTTLE_TIME = 0x15de # macro
|
|
regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX = 0 # macro
|
|
regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT = 0x15df # macro
|
|
regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CGTT_BUSY_CTRL = 0x15e0 # macro
|
|
regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro
|
|
regGCVM_L2_PTE_CACHE_DUMP_CNTL = 0x15e1 # macro
|
|
regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_L2_PTE_CACHE_DUMP_READ = 0x15e2 # macro
|
|
regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX = 0 # macro
|
|
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO = 0x15e5 # macro
|
|
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX = 0 # macro
|
|
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI = 0x15e6 # macro
|
|
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX = 0 # macro
|
|
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO = 0x15e7 # macro
|
|
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX = 0 # macro
|
|
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI = 0x15e8 # macro
|
|
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX = 0 # macro
|
|
regGCVM_L2_BANK_SELECT_MASKS = 0x15e9 # macro
|
|
regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX = 0 # macro
|
|
regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC = 0x15ea # macro
|
|
regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX = 0 # macro
|
|
regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC = 0x15eb # macro
|
|
regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX = 0 # macro
|
|
regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC = 0x15ec # macro
|
|
regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX = 0 # macro
|
|
regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT = 0x15ed # macro
|
|
regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX = 0 # macro
|
|
regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ = 0x15ee # macro
|
|
regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX = 0 # macro
|
|
regGCMC_VM_FB_LOCATION_BASE = 0x1678 # macro
|
|
regGCMC_VM_FB_LOCATION_BASE_BASE_IDX = 0 # macro
|
|
regGCMC_VM_FB_LOCATION_TOP = 0x1679 # macro
|
|
regGCMC_VM_FB_LOCATION_TOP_BASE_IDX = 0 # macro
|
|
regGCMC_VM_AGP_TOP = 0x167a # macro
|
|
regGCMC_VM_AGP_TOP_BASE_IDX = 0 # macro
|
|
regGCMC_VM_AGP_BOT = 0x167b # macro
|
|
regGCMC_VM_AGP_BOT_BASE_IDX = 0 # macro
|
|
regGCMC_VM_AGP_BASE = 0x167c # macro
|
|
regGCMC_VM_AGP_BASE_BASE_IDX = 0 # macro
|
|
regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x167d # macro
|
|
regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX = 0 # macro
|
|
regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x167e # macro
|
|
regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX = 0 # macro
|
|
regGCMC_VM_MX_L1_TLB_CNTL = 0x167f # macro
|
|
regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT0_CNTL = 0x1688 # macro
|
|
regGCVM_CONTEXT0_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT1_CNTL = 0x1689 # macro
|
|
regGCVM_CONTEXT1_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT2_CNTL = 0x168a # macro
|
|
regGCVM_CONTEXT2_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT3_CNTL = 0x168b # macro
|
|
regGCVM_CONTEXT3_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT4_CNTL = 0x168c # macro
|
|
regGCVM_CONTEXT4_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT5_CNTL = 0x168d # macro
|
|
regGCVM_CONTEXT5_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT6_CNTL = 0x168e # macro
|
|
regGCVM_CONTEXT6_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT7_CNTL = 0x168f # macro
|
|
regGCVM_CONTEXT7_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT8_CNTL = 0x1690 # macro
|
|
regGCVM_CONTEXT8_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT9_CNTL = 0x1691 # macro
|
|
regGCVM_CONTEXT9_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT10_CNTL = 0x1692 # macro
|
|
regGCVM_CONTEXT10_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT11_CNTL = 0x1693 # macro
|
|
regGCVM_CONTEXT11_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT12_CNTL = 0x1694 # macro
|
|
regGCVM_CONTEXT12_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT13_CNTL = 0x1695 # macro
|
|
regGCVM_CONTEXT13_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT14_CNTL = 0x1696 # macro
|
|
regGCVM_CONTEXT14_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT15_CNTL = 0x1697 # macro
|
|
regGCVM_CONTEXT15_CNTL_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXTS_DISABLE = 0x1698 # macro
|
|
regGCVM_CONTEXTS_DISABLE_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG0_SEM = 0x1699 # macro
|
|
regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG1_SEM = 0x169a # macro
|
|
regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG2_SEM = 0x169b # macro
|
|
regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG3_SEM = 0x169c # macro
|
|
regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG4_SEM = 0x169d # macro
|
|
regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG5_SEM = 0x169e # macro
|
|
regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG6_SEM = 0x169f # macro
|
|
regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG7_SEM = 0x16a0 # macro
|
|
regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG8_SEM = 0x16a1 # macro
|
|
regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG9_SEM = 0x16a2 # macro
|
|
regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG10_SEM = 0x16a3 # macro
|
|
regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG11_SEM = 0x16a4 # macro
|
|
regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG12_SEM = 0x16a5 # macro
|
|
regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG13_SEM = 0x16a6 # macro
|
|
regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG14_SEM = 0x16a7 # macro
|
|
regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG15_SEM = 0x16a8 # macro
|
|
regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG16_SEM = 0x16a9 # macro
|
|
regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG17_SEM = 0x16aa # macro
|
|
regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG0_REQ = 0x16ab # macro
|
|
regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG1_REQ = 0x16ac # macro
|
|
regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG2_REQ = 0x16ad # macro
|
|
regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG3_REQ = 0x16ae # macro
|
|
regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG4_REQ = 0x16af # macro
|
|
regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG5_REQ = 0x16b0 # macro
|
|
regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG6_REQ = 0x16b1 # macro
|
|
regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG7_REQ = 0x16b2 # macro
|
|
regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG8_REQ = 0x16b3 # macro
|
|
regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG9_REQ = 0x16b4 # macro
|
|
regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG10_REQ = 0x16b5 # macro
|
|
regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG11_REQ = 0x16b6 # macro
|
|
regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG12_REQ = 0x16b7 # macro
|
|
regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG13_REQ = 0x16b8 # macro
|
|
regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG14_REQ = 0x16b9 # macro
|
|
regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG15_REQ = 0x16ba # macro
|
|
regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG16_REQ = 0x16bb # macro
|
|
regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG17_REQ = 0x16bc # macro
|
|
regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG0_ACK = 0x16bd # macro
|
|
regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG1_ACK = 0x16be # macro
|
|
regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG2_ACK = 0x16bf # macro
|
|
regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG3_ACK = 0x16c0 # macro
|
|
regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG4_ACK = 0x16c1 # macro
|
|
regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG5_ACK = 0x16c2 # macro
|
|
regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG6_ACK = 0x16c3 # macro
|
|
regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG7_ACK = 0x16c4 # macro
|
|
regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG8_ACK = 0x16c5 # macro
|
|
regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG9_ACK = 0x16c6 # macro
|
|
regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG10_ACK = 0x16c7 # macro
|
|
regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG11_ACK = 0x16c8 # macro
|
|
regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG12_ACK = 0x16c9 # macro
|
|
regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG13_ACK = 0x16ca # macro
|
|
regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG14_ACK = 0x16cb # macro
|
|
regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG15_ACK = 0x16cc # macro
|
|
regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG16_ACK = 0x16cd # macro
|
|
regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG17_ACK = 0x16ce # macro
|
|
regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 = 0x16cf # macro
|
|
regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 = 0x16d0 # macro
|
|
regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 = 0x16d1 # macro
|
|
regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 = 0x16d2 # macro
|
|
regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 = 0x16d3 # macro
|
|
regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 = 0x16d4 # macro
|
|
regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 = 0x16d5 # macro
|
|
regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 = 0x16d6 # macro
|
|
regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 = 0x16d7 # macro
|
|
regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 = 0x16d8 # macro
|
|
regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 = 0x16d9 # macro
|
|
regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 = 0x16da # macro
|
|
regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 = 0x16db # macro
|
|
regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 = 0x16dc # macro
|
|
regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 = 0x16dd # macro
|
|
regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 = 0x16de # macro
|
|
regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 = 0x16df # macro
|
|
regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 = 0x16e0 # macro
|
|
regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 = 0x16e1 # macro
|
|
regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 = 0x16e2 # macro
|
|
regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 = 0x16e3 # macro
|
|
regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 = 0x16e4 # macro
|
|
regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 = 0x16e5 # macro
|
|
regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 = 0x16e6 # macro
|
|
regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 = 0x16e7 # macro
|
|
regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 = 0x16e8 # macro
|
|
regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 = 0x16e9 # macro
|
|
regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 = 0x16ea # macro
|
|
regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 = 0x16eb # macro
|
|
regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 = 0x16ec # macro
|
|
regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 = 0x16ed # macro
|
|
regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 = 0x16ee # macro
|
|
regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 = 0x16ef # macro
|
|
regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 = 0x16f0 # macro
|
|
regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 = 0x16f1 # macro
|
|
regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 = 0x16f2 # macro
|
|
regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f3 # macro
|
|
regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f4 # macro
|
|
regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f5 # macro
|
|
regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f6 # macro
|
|
regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f7 # macro
|
|
regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f8 # macro
|
|
regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f9 # macro
|
|
regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fa # macro
|
|
regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 = 0x16fb # macro
|
|
regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fc # macro
|
|
regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 = 0x16fd # macro
|
|
regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fe # macro
|
|
regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 = 0x16ff # macro
|
|
regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 = 0x1700 # macro
|
|
regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 = 0x1701 # macro
|
|
regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 = 0x1702 # macro
|
|
regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 = 0x1703 # macro
|
|
regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 = 0x1704 # macro
|
|
regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 = 0x1705 # macro
|
|
regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 = 0x1706 # macro
|
|
regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 = 0x1707 # macro
|
|
regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 = 0x1708 # macro
|
|
regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 = 0x1709 # macro
|
|
regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 = 0x170a # macro
|
|
regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 = 0x170b # macro
|
|
regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 = 0x170c # macro
|
|
regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 = 0x170d # macro
|
|
regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 = 0x170e # macro
|
|
regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 = 0x170f # macro
|
|
regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 = 0x1710 # macro
|
|
regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 = 0x1711 # macro
|
|
regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 = 0x1712 # macro
|
|
regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 = 0x1713 # macro
|
|
regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 = 0x1714 # macro
|
|
regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 = 0x1715 # macro
|
|
regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 = 0x1716 # macro
|
|
regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 = 0x1717 # macro
|
|
regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 = 0x1718 # macro
|
|
regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 = 0x1719 # macro
|
|
regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 = 0x171a # macro
|
|
regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 = 0x171b # macro
|
|
regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 = 0x171c # macro
|
|
regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 = 0x171d # macro
|
|
regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 = 0x171e # macro
|
|
regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 = 0x171f # macro
|
|
regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 = 0x1720 # macro
|
|
regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 = 0x1721 # macro
|
|
regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 = 0x1722 # macro
|
|
regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 = 0x1723 # macro
|
|
regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 = 0x1724 # macro
|
|
regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 = 0x1725 # macro
|
|
regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 = 0x1726 # macro
|
|
regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 = 0x1727 # macro
|
|
regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 = 0x1728 # macro
|
|
regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 = 0x1729 # macro
|
|
regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 = 0x172a # macro
|
|
regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 = 0x172b # macro
|
|
regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 = 0x172c # macro
|
|
regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 = 0x172d # macro
|
|
regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 = 0x172e # macro
|
|
regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 = 0x172f # macro
|
|
regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 = 0x1730 # macro
|
|
regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 = 0x1731 # macro
|
|
regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 = 0x1732 # macro
|
|
regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 = 0x1733 # macro
|
|
regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 = 0x1734 # macro
|
|
regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 = 0x1735 # macro
|
|
regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 = 0x1736 # macro
|
|
regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 = 0x1737 # macro
|
|
regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 = 0x1738 # macro
|
|
regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 = 0x1739 # macro
|
|
regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 = 0x173a # macro
|
|
regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 = 0x173b # macro
|
|
regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 = 0x173c # macro
|
|
regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 = 0x173d # macro
|
|
regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 = 0x173e # macro
|
|
regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 = 0x173f # macro
|
|
regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 = 0x1740 # macro
|
|
regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 = 0x1741 # macro
|
|
regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 = 0x1742 # macro
|
|
regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 = 0x1743 # macro
|
|
regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 = 0x1744 # macro
|
|
regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 = 0x1745 # macro
|
|
regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 = 0x1746 # macro
|
|
regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 = 0x1747 # macro
|
|
regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 = 0x1748 # macro
|
|
regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 = 0x1749 # macro
|
|
regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 = 0x174a # macro
|
|
regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 = 0x174b # macro
|
|
regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 = 0x174c # macro
|
|
regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 = 0x174d # macro
|
|
regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 = 0x174e # macro
|
|
regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 = 0x174f # macro
|
|
regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 = 0x1750 # macro
|
|
regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 = 0x1751 # macro
|
|
regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro
|
|
regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 = 0x1752 # macro
|
|
regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro
|
|
regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1753 # macro
|
|
regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1754 # macro
|
|
regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1755 # macro
|
|
regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1756 # macro
|
|
regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1757 # macro
|
|
regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1758 # macro
|
|
regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1759 # macro
|
|
regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175a # macro
|
|
regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175b # macro
|
|
regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175c # macro
|
|
regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175d # macro
|
|
regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175e # macro
|
|
regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175f # macro
|
|
regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1760 # macro
|
|
regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1761 # macro
|
|
regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1762 # macro
|
|
regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1763 # macro
|
|
regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro
|
|
regGCVML2_PERFCOUNTER2_0_LO = 0x34e0 # macro
|
|
regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX = 1 # macro
|
|
regGCVML2_PERFCOUNTER2_1_LO = 0x34e1 # macro
|
|
regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX = 1 # macro
|
|
regGCVML2_PERFCOUNTER2_0_HI = 0x34e2 # macro
|
|
regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX = 1 # macro
|
|
regGCVML2_PERFCOUNTER2_1_HI = 0x34e3 # macro
|
|
regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX = 1 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER_LO = 0x34e4 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX = 1 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER_HI = 0x34e5 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX = 1 # macro
|
|
regGCUTCL2_PERFCOUNTER_LO = 0x34e6 # macro
|
|
regGCUTCL2_PERFCOUNTER_LO_BASE_IDX = 1 # macro
|
|
regGCUTCL2_PERFCOUNTER_HI = 0x34e7 # macro
|
|
regGCUTCL2_PERFCOUNTER_HI_BASE_IDX = 1 # macro
|
|
regGCVML2_PERFCOUNTER2_0_SELECT = 0x3d20 # macro
|
|
regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX = 1 # macro
|
|
regGCVML2_PERFCOUNTER2_1_SELECT = 0x3d21 # macro
|
|
regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX = 1 # macro
|
|
regGCVML2_PERFCOUNTER2_0_SELECT1 = 0x3d22 # macro
|
|
regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX = 1 # macro
|
|
regGCVML2_PERFCOUNTER2_1_SELECT1 = 0x3d23 # macro
|
|
regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX = 1 # macro
|
|
regGCVML2_PERFCOUNTER2_0_MODE = 0x3d24 # macro
|
|
regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX = 1 # macro
|
|
regGCVML2_PERFCOUNTER2_1_MODE = 0x3d25 # macro
|
|
regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX = 1 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER0_CFG = 0x3d30 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER1_CFG = 0x3d31 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER2_CFG = 0x3d32 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER3_CFG = 0x3d33 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER4_CFG = 0x3d34 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX = 1 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER5_CFG = 0x3d35 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX = 1 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER6_CFG = 0x3d36 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX = 1 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER7_CFG = 0x3d37 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX = 1 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL = 0x3d38 # macro
|
|
regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
|
|
regGCUTCL2_PERFCOUNTER0_CFG = 0x3d39 # macro
|
|
regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
|
|
regGCUTCL2_PERFCOUNTER1_CFG = 0x3d3a # macro
|
|
regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
|
|
regGCUTCL2_PERFCOUNTER2_CFG = 0x3d3b # macro
|
|
regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro
|
|
regGCUTCL2_PERFCOUNTER3_CFG = 0x3d3c # macro
|
|
regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro
|
|
regGCUTCL2_PERFCOUNTER_RSLT_CNTL = 0x3d3d # macro
|
|
regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF0 = 0x5a80 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF1 = 0x5a81 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF2 = 0x5a82 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF3 = 0x5a83 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF4 = 0x5a84 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF5 = 0x5a85 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF6 = 0x5a86 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF7 = 0x5a87 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF8 = 0x5a88 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF9 = 0x5a89 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF10 = 0x5a8a # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF11 = 0x5a8b # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF12 = 0x5a8c # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF13 = 0x5a8d # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF14 = 0x5a8e # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX = 1 # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF15 = 0x5a8f # macro
|
|
regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX = 1 # macro
|
|
regGCUTCL2_TRANSLATION_BYPASS_BY_VMID = 0x5e41 # macro
|
|
regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX = 1 # macro
|
|
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL = 0x5e44 # macro
|
|
regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_0 = 0x5e48 # macro
|
|
regGCMC_VM_MARC_BASE_LO_0_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_1 = 0x5e49 # macro
|
|
regGCMC_VM_MARC_BASE_LO_1_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_2 = 0x5e4a # macro
|
|
regGCMC_VM_MARC_BASE_LO_2_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_3 = 0x5e4b # macro
|
|
regGCMC_VM_MARC_BASE_LO_3_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_4 = 0x5e4c # macro
|
|
regGCMC_VM_MARC_BASE_LO_4_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_5 = 0x5e4d # macro
|
|
regGCMC_VM_MARC_BASE_LO_5_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_6 = 0x5e4e # macro
|
|
regGCMC_VM_MARC_BASE_LO_6_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_7 = 0x5e4f # macro
|
|
regGCMC_VM_MARC_BASE_LO_7_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_8 = 0x5e50 # macro
|
|
regGCMC_VM_MARC_BASE_LO_8_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_9 = 0x5e51 # macro
|
|
regGCMC_VM_MARC_BASE_LO_9_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_10 = 0x5e52 # macro
|
|
regGCMC_VM_MARC_BASE_LO_10_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_11 = 0x5e53 # macro
|
|
regGCMC_VM_MARC_BASE_LO_11_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_12 = 0x5e54 # macro
|
|
regGCMC_VM_MARC_BASE_LO_12_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_13 = 0x5e55 # macro
|
|
regGCMC_VM_MARC_BASE_LO_13_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_14 = 0x5e56 # macro
|
|
regGCMC_VM_MARC_BASE_LO_14_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_LO_15 = 0x5e57 # macro
|
|
regGCMC_VM_MARC_BASE_LO_15_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_0 = 0x5e58 # macro
|
|
regGCMC_VM_MARC_BASE_HI_0_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_1 = 0x5e59 # macro
|
|
regGCMC_VM_MARC_BASE_HI_1_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_2 = 0x5e5a # macro
|
|
regGCMC_VM_MARC_BASE_HI_2_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_3 = 0x5e5b # macro
|
|
regGCMC_VM_MARC_BASE_HI_3_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_4 = 0x5e5c # macro
|
|
regGCMC_VM_MARC_BASE_HI_4_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_5 = 0x5e5d # macro
|
|
regGCMC_VM_MARC_BASE_HI_5_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_6 = 0x5e5e # macro
|
|
regGCMC_VM_MARC_BASE_HI_6_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_7 = 0x5e5f # macro
|
|
regGCMC_VM_MARC_BASE_HI_7_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_8 = 0x5e60 # macro
|
|
regGCMC_VM_MARC_BASE_HI_8_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_9 = 0x5e61 # macro
|
|
regGCMC_VM_MARC_BASE_HI_9_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_10 = 0x5e62 # macro
|
|
regGCMC_VM_MARC_BASE_HI_10_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_11 = 0x5e63 # macro
|
|
regGCMC_VM_MARC_BASE_HI_11_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_12 = 0x5e64 # macro
|
|
regGCMC_VM_MARC_BASE_HI_12_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_13 = 0x5e65 # macro
|
|
regGCMC_VM_MARC_BASE_HI_13_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_14 = 0x5e66 # macro
|
|
regGCMC_VM_MARC_BASE_HI_14_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_BASE_HI_15 = 0x5e67 # macro
|
|
regGCMC_VM_MARC_BASE_HI_15_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_0 = 0x5e68 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_1 = 0x5e69 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_2 = 0x5e6a # macro
|
|
regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_3 = 0x5e6b # macro
|
|
regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_4 = 0x5e6c # macro
|
|
regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_5 = 0x5e6d # macro
|
|
regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_6 = 0x5e6e # macro
|
|
regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_7 = 0x5e6f # macro
|
|
regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_8 = 0x5e70 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_9 = 0x5e71 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_10 = 0x5e72 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_11 = 0x5e73 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_12 = 0x5e74 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_13 = 0x5e75 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_14 = 0x5e76 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_15 = 0x5e77 # macro
|
|
regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_0 = 0x5e78 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_1 = 0x5e79 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_2 = 0x5e7a # macro
|
|
regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_3 = 0x5e7b # macro
|
|
regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_4 = 0x5e7c # macro
|
|
regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_5 = 0x5e7d # macro
|
|
regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_6 = 0x5e7e # macro
|
|
regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_7 = 0x5e7f # macro
|
|
regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_8 = 0x5e80 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_9 = 0x5e81 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_10 = 0x5e82 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_11 = 0x5e83 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_12 = 0x5e84 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_13 = 0x5e85 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_14 = 0x5e86 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_15 = 0x5e87 # macro
|
|
regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_0 = 0x5e88 # macro
|
|
regGCMC_VM_MARC_LEN_LO_0_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_1 = 0x5e89 # macro
|
|
regGCMC_VM_MARC_LEN_LO_1_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_2 = 0x5e8a # macro
|
|
regGCMC_VM_MARC_LEN_LO_2_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_3 = 0x5e8b # macro
|
|
regGCMC_VM_MARC_LEN_LO_3_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_4 = 0x5e8c # macro
|
|
regGCMC_VM_MARC_LEN_LO_4_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_5 = 0x5e8d # macro
|
|
regGCMC_VM_MARC_LEN_LO_5_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_6 = 0x5e8e # macro
|
|
regGCMC_VM_MARC_LEN_LO_6_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_7 = 0x5e8f # macro
|
|
regGCMC_VM_MARC_LEN_LO_7_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_8 = 0x5e90 # macro
|
|
regGCMC_VM_MARC_LEN_LO_8_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_9 = 0x5e91 # macro
|
|
regGCMC_VM_MARC_LEN_LO_9_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_10 = 0x5e92 # macro
|
|
regGCMC_VM_MARC_LEN_LO_10_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_11 = 0x5e93 # macro
|
|
regGCMC_VM_MARC_LEN_LO_11_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_12 = 0x5e94 # macro
|
|
regGCMC_VM_MARC_LEN_LO_12_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_13 = 0x5e95 # macro
|
|
regGCMC_VM_MARC_LEN_LO_13_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_14 = 0x5e96 # macro
|
|
regGCMC_VM_MARC_LEN_LO_14_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_LO_15 = 0x5e97 # macro
|
|
regGCMC_VM_MARC_LEN_LO_15_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_0 = 0x5e98 # macro
|
|
regGCMC_VM_MARC_LEN_HI_0_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_1 = 0x5e99 # macro
|
|
regGCMC_VM_MARC_LEN_HI_1_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_2 = 0x5e9a # macro
|
|
regGCMC_VM_MARC_LEN_HI_2_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_3 = 0x5e9b # macro
|
|
regGCMC_VM_MARC_LEN_HI_3_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_4 = 0x5e9c # macro
|
|
regGCMC_VM_MARC_LEN_HI_4_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_5 = 0x5e9d # macro
|
|
regGCMC_VM_MARC_LEN_HI_5_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_6 = 0x5e9e # macro
|
|
regGCMC_VM_MARC_LEN_HI_6_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_7 = 0x5e9f # macro
|
|
regGCMC_VM_MARC_LEN_HI_7_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_8 = 0x5ea0 # macro
|
|
regGCMC_VM_MARC_LEN_HI_8_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_9 = 0x5ea1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_9_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_10 = 0x5ea2 # macro
|
|
regGCMC_VM_MARC_LEN_HI_10_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_11 = 0x5ea3 # macro
|
|
regGCMC_VM_MARC_LEN_HI_11_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_12 = 0x5ea4 # macro
|
|
regGCMC_VM_MARC_LEN_HI_12_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_13 = 0x5ea5 # macro
|
|
regGCMC_VM_MARC_LEN_HI_13_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_14 = 0x5ea6 # macro
|
|
regGCMC_VM_MARC_LEN_HI_14_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_LEN_HI_15 = 0x5ea7 # macro
|
|
regGCMC_VM_MARC_LEN_HI_15_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_0 = 0x5ea8 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_1 = 0x5ea9 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_2 = 0x5eaa # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_3 = 0x5eab # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_4 = 0x5eac # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_5 = 0x5ead # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_6 = 0x5eae # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_7 = 0x5eaf # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_8 = 0x5eb0 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_9 = 0x5eb1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_10 = 0x5eb2 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_11 = 0x5eb3 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_12 = 0x5eb4 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_13 = 0x5eb5 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_14 = 0x5eb6 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX = 1 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_15 = 0x5eb7 # macro
|
|
regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX = 1 # macro
|
|
regGCUTC_TRANSLATION_FAULT_CNTL0 = 0x5eb8 # macro
|
|
regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX = 1 # macro
|
|
regGCUTC_TRANSLATION_FAULT_CNTL1 = 0x5eb9 # macro
|
|
regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX = 1 # macro
|
|
regSPI_SHADER_PGM_RSRC4_PS = 0x19a1 # macro
|
|
regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_CHKSUM_PS = 0x19a6 # macro
|
|
regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_RSRC3_PS = 0x19a7 # macro
|
|
regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_LO_PS = 0x19a8 # macro
|
|
regSPI_SHADER_PGM_LO_PS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_HI_PS = 0x19a9 # macro
|
|
regSPI_SHADER_PGM_HI_PS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_RSRC1_PS = 0x19aa # macro
|
|
regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_RSRC2_PS = 0x19ab # macro
|
|
regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_0 = 0x19ac # macro
|
|
regSPI_SHADER_USER_DATA_PS_0_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_1 = 0x19ad # macro
|
|
regSPI_SHADER_USER_DATA_PS_1_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_2 = 0x19ae # macro
|
|
regSPI_SHADER_USER_DATA_PS_2_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_3 = 0x19af # macro
|
|
regSPI_SHADER_USER_DATA_PS_3_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_4 = 0x19b0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_4_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_5 = 0x19b1 # macro
|
|
regSPI_SHADER_USER_DATA_PS_5_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_6 = 0x19b2 # macro
|
|
regSPI_SHADER_USER_DATA_PS_6_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_7 = 0x19b3 # macro
|
|
regSPI_SHADER_USER_DATA_PS_7_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_8 = 0x19b4 # macro
|
|
regSPI_SHADER_USER_DATA_PS_8_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_9 = 0x19b5 # macro
|
|
regSPI_SHADER_USER_DATA_PS_9_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_10 = 0x19b6 # macro
|
|
regSPI_SHADER_USER_DATA_PS_10_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_11 = 0x19b7 # macro
|
|
regSPI_SHADER_USER_DATA_PS_11_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_12 = 0x19b8 # macro
|
|
regSPI_SHADER_USER_DATA_PS_12_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_13 = 0x19b9 # macro
|
|
regSPI_SHADER_USER_DATA_PS_13_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_14 = 0x19ba # macro
|
|
regSPI_SHADER_USER_DATA_PS_14_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_15 = 0x19bb # macro
|
|
regSPI_SHADER_USER_DATA_PS_15_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_16 = 0x19bc # macro
|
|
regSPI_SHADER_USER_DATA_PS_16_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_17 = 0x19bd # macro
|
|
regSPI_SHADER_USER_DATA_PS_17_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_18 = 0x19be # macro
|
|
regSPI_SHADER_USER_DATA_PS_18_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_19 = 0x19bf # macro
|
|
regSPI_SHADER_USER_DATA_PS_19_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_20 = 0x19c0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_20_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_21 = 0x19c1 # macro
|
|
regSPI_SHADER_USER_DATA_PS_21_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_22 = 0x19c2 # macro
|
|
regSPI_SHADER_USER_DATA_PS_22_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_23 = 0x19c3 # macro
|
|
regSPI_SHADER_USER_DATA_PS_23_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_24 = 0x19c4 # macro
|
|
regSPI_SHADER_USER_DATA_PS_24_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_25 = 0x19c5 # macro
|
|
regSPI_SHADER_USER_DATA_PS_25_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_26 = 0x19c6 # macro
|
|
regSPI_SHADER_USER_DATA_PS_26_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_27 = 0x19c7 # macro
|
|
regSPI_SHADER_USER_DATA_PS_27_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_28 = 0x19c8 # macro
|
|
regSPI_SHADER_USER_DATA_PS_28_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_29 = 0x19c9 # macro
|
|
regSPI_SHADER_USER_DATA_PS_29_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_30 = 0x19ca # macro
|
|
regSPI_SHADER_USER_DATA_PS_30_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_PS_31 = 0x19cb # macro
|
|
regSPI_SHADER_USER_DATA_PS_31_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_REQ_CTRL_PS = 0x19d0 # macro
|
|
regSPI_SHADER_REQ_CTRL_PS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_ACCUM_PS_0 = 0x19d2 # macro
|
|
regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_ACCUM_PS_1 = 0x19d3 # macro
|
|
regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_ACCUM_PS_2 = 0x19d4 # macro
|
|
regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_ACCUM_PS_3 = 0x19d5 # macro
|
|
regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_CHKSUM_GS = 0x1a20 # macro
|
|
regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_RSRC4_GS = 0x1a21 # macro
|
|
regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_ADDR_LO_GS = 0x1a22 # macro
|
|
regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_ADDR_HI_GS = 0x1a23 # macro
|
|
regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_LO_ES_GS = 0x1a24 # macro
|
|
regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_HI_ES_GS = 0x1a25 # macro
|
|
regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_RSRC3_GS = 0x1a27 # macro
|
|
regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_LO_GS = 0x1a28 # macro
|
|
regSPI_SHADER_PGM_LO_GS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_HI_GS = 0x1a29 # macro
|
|
regSPI_SHADER_PGM_HI_GS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_RSRC1_GS = 0x1a2a # macro
|
|
regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_RSRC2_GS = 0x1a2b # macro
|
|
regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_0 = 0x1a2c # macro
|
|
regSPI_SHADER_USER_DATA_GS_0_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_1 = 0x1a2d # macro
|
|
regSPI_SHADER_USER_DATA_GS_1_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_2 = 0x1a2e # macro
|
|
regSPI_SHADER_USER_DATA_GS_2_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_3 = 0x1a2f # macro
|
|
regSPI_SHADER_USER_DATA_GS_3_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_4 = 0x1a30 # macro
|
|
regSPI_SHADER_USER_DATA_GS_4_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_5 = 0x1a31 # macro
|
|
regSPI_SHADER_USER_DATA_GS_5_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_6 = 0x1a32 # macro
|
|
regSPI_SHADER_USER_DATA_GS_6_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_7 = 0x1a33 # macro
|
|
regSPI_SHADER_USER_DATA_GS_7_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_8 = 0x1a34 # macro
|
|
regSPI_SHADER_USER_DATA_GS_8_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_9 = 0x1a35 # macro
|
|
regSPI_SHADER_USER_DATA_GS_9_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_10 = 0x1a36 # macro
|
|
regSPI_SHADER_USER_DATA_GS_10_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_11 = 0x1a37 # macro
|
|
regSPI_SHADER_USER_DATA_GS_11_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_12 = 0x1a38 # macro
|
|
regSPI_SHADER_USER_DATA_GS_12_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_13 = 0x1a39 # macro
|
|
regSPI_SHADER_USER_DATA_GS_13_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_14 = 0x1a3a # macro
|
|
regSPI_SHADER_USER_DATA_GS_14_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_15 = 0x1a3b # macro
|
|
regSPI_SHADER_USER_DATA_GS_15_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_16 = 0x1a3c # macro
|
|
regSPI_SHADER_USER_DATA_GS_16_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_17 = 0x1a3d # macro
|
|
regSPI_SHADER_USER_DATA_GS_17_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_18 = 0x1a3e # macro
|
|
regSPI_SHADER_USER_DATA_GS_18_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_19 = 0x1a3f # macro
|
|
regSPI_SHADER_USER_DATA_GS_19_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_20 = 0x1a40 # macro
|
|
regSPI_SHADER_USER_DATA_GS_20_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_21 = 0x1a41 # macro
|
|
regSPI_SHADER_USER_DATA_GS_21_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_22 = 0x1a42 # macro
|
|
regSPI_SHADER_USER_DATA_GS_22_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_23 = 0x1a43 # macro
|
|
regSPI_SHADER_USER_DATA_GS_23_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_24 = 0x1a44 # macro
|
|
regSPI_SHADER_USER_DATA_GS_24_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_25 = 0x1a45 # macro
|
|
regSPI_SHADER_USER_DATA_GS_25_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_26 = 0x1a46 # macro
|
|
regSPI_SHADER_USER_DATA_GS_26_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_27 = 0x1a47 # macro
|
|
regSPI_SHADER_USER_DATA_GS_27_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_28 = 0x1a48 # macro
|
|
regSPI_SHADER_USER_DATA_GS_28_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_29 = 0x1a49 # macro
|
|
regSPI_SHADER_USER_DATA_GS_29_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_30 = 0x1a4a # macro
|
|
regSPI_SHADER_USER_DATA_GS_30_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_GS_31 = 0x1a4b # macro
|
|
regSPI_SHADER_USER_DATA_GS_31_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_GS_MESHLET_DIM = 0x1a4c # macro
|
|
regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_GS_MESHLET_EXP_ALLOC = 0x1a4d # macro
|
|
regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_REQ_CTRL_ESGS = 0x1a50 # macro
|
|
regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_ACCUM_ESGS_0 = 0x1a52 # macro
|
|
regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_ACCUM_ESGS_1 = 0x1a53 # macro
|
|
regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_ACCUM_ESGS_2 = 0x1a54 # macro
|
|
regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_ACCUM_ESGS_3 = 0x1a55 # macro
|
|
regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_LO_ES = 0x1a68 # macro
|
|
regSPI_SHADER_PGM_LO_ES_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_HI_ES = 0x1a69 # macro
|
|
regSPI_SHADER_PGM_HI_ES_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_CHKSUM_HS = 0x1aa0 # macro
|
|
regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_RSRC4_HS = 0x1aa1 # macro
|
|
regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_ADDR_LO_HS = 0x1aa2 # macro
|
|
regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_ADDR_HI_HS = 0x1aa3 # macro
|
|
regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_LO_LS_HS = 0x1aa4 # macro
|
|
regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_HI_LS_HS = 0x1aa5 # macro
|
|
regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_RSRC3_HS = 0x1aa7 # macro
|
|
regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_LO_HS = 0x1aa8 # macro
|
|
regSPI_SHADER_PGM_LO_HS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_HI_HS = 0x1aa9 # macro
|
|
regSPI_SHADER_PGM_HI_HS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_RSRC1_HS = 0x1aaa # macro
|
|
regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_RSRC2_HS = 0x1aab # macro
|
|
regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_0 = 0x1aac # macro
|
|
regSPI_SHADER_USER_DATA_HS_0_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_1 = 0x1aad # macro
|
|
regSPI_SHADER_USER_DATA_HS_1_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_2 = 0x1aae # macro
|
|
regSPI_SHADER_USER_DATA_HS_2_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_3 = 0x1aaf # macro
|
|
regSPI_SHADER_USER_DATA_HS_3_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_4 = 0x1ab0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_4_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_5 = 0x1ab1 # macro
|
|
regSPI_SHADER_USER_DATA_HS_5_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_6 = 0x1ab2 # macro
|
|
regSPI_SHADER_USER_DATA_HS_6_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_7 = 0x1ab3 # macro
|
|
regSPI_SHADER_USER_DATA_HS_7_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_8 = 0x1ab4 # macro
|
|
regSPI_SHADER_USER_DATA_HS_8_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_9 = 0x1ab5 # macro
|
|
regSPI_SHADER_USER_DATA_HS_9_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_10 = 0x1ab6 # macro
|
|
regSPI_SHADER_USER_DATA_HS_10_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_11 = 0x1ab7 # macro
|
|
regSPI_SHADER_USER_DATA_HS_11_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_12 = 0x1ab8 # macro
|
|
regSPI_SHADER_USER_DATA_HS_12_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_13 = 0x1ab9 # macro
|
|
regSPI_SHADER_USER_DATA_HS_13_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_14 = 0x1aba # macro
|
|
regSPI_SHADER_USER_DATA_HS_14_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_15 = 0x1abb # macro
|
|
regSPI_SHADER_USER_DATA_HS_15_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_16 = 0x1abc # macro
|
|
regSPI_SHADER_USER_DATA_HS_16_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_17 = 0x1abd # macro
|
|
regSPI_SHADER_USER_DATA_HS_17_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_18 = 0x1abe # macro
|
|
regSPI_SHADER_USER_DATA_HS_18_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_19 = 0x1abf # macro
|
|
regSPI_SHADER_USER_DATA_HS_19_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_20 = 0x1ac0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_20_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_21 = 0x1ac1 # macro
|
|
regSPI_SHADER_USER_DATA_HS_21_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_22 = 0x1ac2 # macro
|
|
regSPI_SHADER_USER_DATA_HS_22_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_23 = 0x1ac3 # macro
|
|
regSPI_SHADER_USER_DATA_HS_23_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_24 = 0x1ac4 # macro
|
|
regSPI_SHADER_USER_DATA_HS_24_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_25 = 0x1ac5 # macro
|
|
regSPI_SHADER_USER_DATA_HS_25_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_26 = 0x1ac6 # macro
|
|
regSPI_SHADER_USER_DATA_HS_26_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_27 = 0x1ac7 # macro
|
|
regSPI_SHADER_USER_DATA_HS_27_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_28 = 0x1ac8 # macro
|
|
regSPI_SHADER_USER_DATA_HS_28_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_29 = 0x1ac9 # macro
|
|
regSPI_SHADER_USER_DATA_HS_29_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_30 = 0x1aca # macro
|
|
regSPI_SHADER_USER_DATA_HS_30_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_DATA_HS_31 = 0x1acb # macro
|
|
regSPI_SHADER_USER_DATA_HS_31_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_REQ_CTRL_LSHS = 0x1ad0 # macro
|
|
regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_ACCUM_LSHS_0 = 0x1ad2 # macro
|
|
regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_ACCUM_LSHS_1 = 0x1ad3 # macro
|
|
regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_ACCUM_LSHS_2 = 0x1ad4 # macro
|
|
regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_USER_ACCUM_LSHS_3 = 0x1ad5 # macro
|
|
regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_LO_LS = 0x1ae8 # macro
|
|
regSPI_SHADER_PGM_LO_LS_BASE_IDX = 0 # macro
|
|
regSPI_SHADER_PGM_HI_LS = 0x1ae9 # macro
|
|
regSPI_SHADER_PGM_HI_LS_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DISPATCH_INITIATOR = 0x1ba0 # macro
|
|
regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DIM_X = 0x1ba1 # macro
|
|
regCOMPUTE_DIM_X_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DIM_Y = 0x1ba2 # macro
|
|
regCOMPUTE_DIM_Y_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DIM_Z = 0x1ba3 # macro
|
|
regCOMPUTE_DIM_Z_BASE_IDX = 0 # macro
|
|
regCOMPUTE_START_X = 0x1ba4 # macro
|
|
regCOMPUTE_START_X_BASE_IDX = 0 # macro
|
|
regCOMPUTE_START_Y = 0x1ba5 # macro
|
|
regCOMPUTE_START_Y_BASE_IDX = 0 # macro
|
|
regCOMPUTE_START_Z = 0x1ba6 # macro
|
|
regCOMPUTE_START_Z_BASE_IDX = 0 # macro
|
|
regCOMPUTE_NUM_THREAD_X = 0x1ba7 # macro
|
|
regCOMPUTE_NUM_THREAD_X_BASE_IDX = 0 # macro
|
|
regCOMPUTE_NUM_THREAD_Y = 0x1ba8 # macro
|
|
regCOMPUTE_NUM_THREAD_Y_BASE_IDX = 0 # macro
|
|
regCOMPUTE_NUM_THREAD_Z = 0x1ba9 # macro
|
|
regCOMPUTE_NUM_THREAD_Z_BASE_IDX = 0 # macro
|
|
regCOMPUTE_PIPELINESTAT_ENABLE = 0x1baa # macro
|
|
regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX = 0 # macro
|
|
regCOMPUTE_PERFCOUNT_ENABLE = 0x1bab # macro
|
|
regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX = 0 # macro
|
|
regCOMPUTE_PGM_LO = 0x1bac # macro
|
|
regCOMPUTE_PGM_LO_BASE_IDX = 0 # macro
|
|
regCOMPUTE_PGM_HI = 0x1bad # macro
|
|
regCOMPUTE_PGM_HI_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DISPATCH_PKT_ADDR_LO = 0x1bae # macro
|
|
regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DISPATCH_PKT_ADDR_HI = 0x1baf # macro
|
|
regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DISPATCH_SCRATCH_BASE_LO = 0x1bb0 # macro
|
|
regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DISPATCH_SCRATCH_BASE_HI = 0x1bb1 # macro
|
|
regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX = 0 # macro
|
|
regCOMPUTE_PGM_RSRC1 = 0x1bb2 # macro
|
|
regCOMPUTE_PGM_RSRC1_BASE_IDX = 0 # macro
|
|
regCOMPUTE_PGM_RSRC2 = 0x1bb3 # macro
|
|
regCOMPUTE_PGM_RSRC2_BASE_IDX = 0 # macro
|
|
regCOMPUTE_VMID = 0x1bb4 # macro
|
|
regCOMPUTE_VMID_BASE_IDX = 0 # macro
|
|
regCOMPUTE_RESOURCE_LIMITS = 0x1bb5 # macro
|
|
regCOMPUTE_RESOURCE_LIMITS_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DESTINATION_EN_SE0 = 0x1bb6 # macro
|
|
regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX = 0 # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE0 = 0x1bb6 # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DESTINATION_EN_SE1 = 0x1bb7 # macro
|
|
regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX = 0 # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE1 = 0x1bb7 # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX = 0 # macro
|
|
regCOMPUTE_TMPRING_SIZE = 0x1bb8 # macro
|
|
regCOMPUTE_TMPRING_SIZE_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DESTINATION_EN_SE2 = 0x1bb9 # macro
|
|
regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX = 0 # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE2 = 0x1bb9 # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DESTINATION_EN_SE3 = 0x1bba # macro
|
|
regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX = 0 # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE3 = 0x1bba # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX = 0 # macro
|
|
regCOMPUTE_RESTART_X = 0x1bbb # macro
|
|
regCOMPUTE_RESTART_X_BASE_IDX = 0 # macro
|
|
regCOMPUTE_RESTART_Y = 0x1bbc # macro
|
|
regCOMPUTE_RESTART_Y_BASE_IDX = 0 # macro
|
|
regCOMPUTE_RESTART_Z = 0x1bbd # macro
|
|
regCOMPUTE_RESTART_Z_BASE_IDX = 0 # macro
|
|
regCOMPUTE_THREAD_TRACE_ENABLE = 0x1bbe # macro
|
|
regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX = 0 # macro
|
|
regCOMPUTE_MISC_RESERVED = 0x1bbf # macro
|
|
regCOMPUTE_MISC_RESERVED_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DISPATCH_ID = 0x1bc0 # macro
|
|
regCOMPUTE_DISPATCH_ID_BASE_IDX = 0 # macro
|
|
regCOMPUTE_THREADGROUP_ID = 0x1bc1 # macro
|
|
regCOMPUTE_THREADGROUP_ID_BASE_IDX = 0 # macro
|
|
regCOMPUTE_REQ_CTRL = 0x1bc2 # macro
|
|
regCOMPUTE_REQ_CTRL_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_ACCUM_0 = 0x1bc4 # macro
|
|
regCOMPUTE_USER_ACCUM_0_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_ACCUM_1 = 0x1bc5 # macro
|
|
regCOMPUTE_USER_ACCUM_1_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_ACCUM_2 = 0x1bc6 # macro
|
|
regCOMPUTE_USER_ACCUM_2_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_ACCUM_3 = 0x1bc7 # macro
|
|
regCOMPUTE_USER_ACCUM_3_BASE_IDX = 0 # macro
|
|
regCOMPUTE_PGM_RSRC3 = 0x1bc8 # macro
|
|
regCOMPUTE_PGM_RSRC3_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DDID_INDEX = 0x1bc9 # macro
|
|
regCOMPUTE_DDID_INDEX_BASE_IDX = 0 # macro
|
|
regCOMPUTE_SHADER_CHKSUM = 0x1bca # macro
|
|
regCOMPUTE_SHADER_CHKSUM_BASE_IDX = 0 # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE4 = 0x1bcb # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX = 0 # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE5 = 0x1bcc # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX = 0 # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE6 = 0x1bcd # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX = 0 # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE7 = 0x1bce # macro
|
|
regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DISPATCH_INTERLEAVE = 0x1bcf # macro
|
|
regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX = 0 # macro
|
|
regCOMPUTE_RELAUNCH = 0x1bd0 # macro
|
|
regCOMPUTE_RELAUNCH_BASE_IDX = 0 # macro
|
|
regCOMPUTE_WAVE_RESTORE_ADDR_LO = 0x1bd1 # macro
|
|
regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCOMPUTE_WAVE_RESTORE_ADDR_HI = 0x1bd2 # macro
|
|
regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCOMPUTE_RELAUNCH2 = 0x1bd3 # macro
|
|
regCOMPUTE_RELAUNCH2_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_0 = 0x1be0 # macro
|
|
regCOMPUTE_USER_DATA_0_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_1 = 0x1be1 # macro
|
|
regCOMPUTE_USER_DATA_1_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_2 = 0x1be2 # macro
|
|
regCOMPUTE_USER_DATA_2_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_3 = 0x1be3 # macro
|
|
regCOMPUTE_USER_DATA_3_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_4 = 0x1be4 # macro
|
|
regCOMPUTE_USER_DATA_4_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_5 = 0x1be5 # macro
|
|
regCOMPUTE_USER_DATA_5_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_6 = 0x1be6 # macro
|
|
regCOMPUTE_USER_DATA_6_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_7 = 0x1be7 # macro
|
|
regCOMPUTE_USER_DATA_7_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_8 = 0x1be8 # macro
|
|
regCOMPUTE_USER_DATA_8_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_9 = 0x1be9 # macro
|
|
regCOMPUTE_USER_DATA_9_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_10 = 0x1bea # macro
|
|
regCOMPUTE_USER_DATA_10_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_11 = 0x1beb # macro
|
|
regCOMPUTE_USER_DATA_11_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_12 = 0x1bec # macro
|
|
regCOMPUTE_USER_DATA_12_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_13 = 0x1bed # macro
|
|
regCOMPUTE_USER_DATA_13_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_14 = 0x1bee # macro
|
|
regCOMPUTE_USER_DATA_14_BASE_IDX = 0 # macro
|
|
regCOMPUTE_USER_DATA_15 = 0x1bef # macro
|
|
regCOMPUTE_USER_DATA_15_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DISPATCH_TUNNEL = 0x1c1d # macro
|
|
regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX = 0 # macro
|
|
regCOMPUTE_DISPATCH_END = 0x1c1e # macro
|
|
regCOMPUTE_DISPATCH_END_BASE_IDX = 0 # macro
|
|
regCOMPUTE_NOWHERE = 0x1c1f # macro
|
|
regCOMPUTE_NOWHERE_BASE_IDX = 0 # macro
|
|
regSH_RESERVED_REG0 = 0x1c20 # macro
|
|
regSH_RESERVED_REG0_BASE_IDX = 0 # macro
|
|
regSH_RESERVED_REG1 = 0x1c21 # macro
|
|
regSH_RESERVED_REG1_BASE_IDX = 0 # macro
|
|
regCP_CU_MASK_ADDR_LO = 0x1dd2 # macro
|
|
regCP_CU_MASK_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCP_CU_MASK_ADDR_HI = 0x1dd3 # macro
|
|
regCP_CU_MASK_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_CU_MASK_CNTL = 0x1dd4 # macro
|
|
regCP_CU_MASK_CNTL_BASE_IDX = 0 # macro
|
|
regCP_EOPQ_WAIT_TIME = 0x1dd5 # macro
|
|
regCP_EOPQ_WAIT_TIME_BASE_IDX = 0 # macro
|
|
regCP_CPC_MGCG_SYNC_CNTL = 0x1dd6 # macro
|
|
regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX = 0 # macro
|
|
regCPC_INT_INFO = 0x1dd7 # macro
|
|
regCPC_INT_INFO_BASE_IDX = 0 # macro
|
|
regCP_VIRT_STATUS = 0x1dd8 # macro
|
|
regCP_VIRT_STATUS_BASE_IDX = 0 # macro
|
|
regCPC_INT_ADDR = 0x1dd9 # macro
|
|
regCPC_INT_ADDR_BASE_IDX = 0 # macro
|
|
regCPC_INT_PASID = 0x1dda # macro
|
|
regCPC_INT_PASID_BASE_IDX = 0 # macro
|
|
regCP_GFX_ERROR = 0x1ddb # macro
|
|
regCP_GFX_ERROR_BASE_IDX = 0 # macro
|
|
regCPG_UTCL1_CNTL = 0x1ddc # macro
|
|
regCPG_UTCL1_CNTL_BASE_IDX = 0 # macro
|
|
regCPC_UTCL1_CNTL = 0x1ddd # macro
|
|
regCPC_UTCL1_CNTL_BASE_IDX = 0 # macro
|
|
regCPF_UTCL1_CNTL = 0x1dde # macro
|
|
regCPF_UTCL1_CNTL_BASE_IDX = 0 # macro
|
|
regCP_AQL_SMM_STATUS = 0x1ddf # macro
|
|
regCP_AQL_SMM_STATUS_BASE_IDX = 0 # macro
|
|
regCP_RB0_BASE = 0x1de0 # macro
|
|
regCP_RB0_BASE_BASE_IDX = 0 # macro
|
|
regCP_RB_BASE = 0x1de0 # macro
|
|
regCP_RB_BASE_BASE_IDX = 0 # macro
|
|
regCP_RB0_CNTL = 0x1de1 # macro
|
|
regCP_RB0_CNTL_BASE_IDX = 0 # macro
|
|
regCP_RB_CNTL = 0x1de1 # macro
|
|
regCP_RB_CNTL_BASE_IDX = 0 # macro
|
|
regCP_RB_RPTR_WR = 0x1de2 # macro
|
|
regCP_RB_RPTR_WR_BASE_IDX = 0 # macro
|
|
regCP_RB0_RPTR_ADDR = 0x1de3 # macro
|
|
regCP_RB0_RPTR_ADDR_BASE_IDX = 0 # macro
|
|
regCP_RB_RPTR_ADDR = 0x1de3 # macro
|
|
regCP_RB_RPTR_ADDR_BASE_IDX = 0 # macro
|
|
regCP_RB0_RPTR_ADDR_HI = 0x1de4 # macro
|
|
regCP_RB0_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_RB_RPTR_ADDR_HI = 0x1de4 # macro
|
|
regCP_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_RB0_BUFSZ_MASK = 0x1de5 # macro
|
|
regCP_RB0_BUFSZ_MASK_BASE_IDX = 0 # macro
|
|
regCP_RB_BUFSZ_MASK = 0x1de5 # macro
|
|
regCP_RB_BUFSZ_MASK_BASE_IDX = 0 # macro
|
|
regCP_INT_CNTL = 0x1de9 # macro
|
|
regCP_INT_CNTL_BASE_IDX = 0 # macro
|
|
regCP_INT_STATUS = 0x1dea # macro
|
|
regCP_INT_STATUS_BASE_IDX = 0 # macro
|
|
regCP_DEVICE_ID = 0x1deb # macro
|
|
regCP_DEVICE_ID_BASE_IDX = 0 # macro
|
|
regCP_ME0_PIPE_PRIORITY_CNTS = 0x1dec # macro
|
|
regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro
|
|
regCP_RING_PRIORITY_CNTS = 0x1dec # macro
|
|
regCP_RING_PRIORITY_CNTS_BASE_IDX = 0 # macro
|
|
regCP_ME0_PIPE0_PRIORITY = 0x1ded # macro
|
|
regCP_ME0_PIPE0_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_RING0_PRIORITY = 0x1ded # macro
|
|
regCP_RING0_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_ME0_PIPE1_PRIORITY = 0x1dee # macro
|
|
regCP_ME0_PIPE1_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_RING1_PRIORITY = 0x1dee # macro
|
|
regCP_RING1_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_FATAL_ERROR = 0x1df0 # macro
|
|
regCP_FATAL_ERROR_BASE_IDX = 0 # macro
|
|
regCP_RB_VMID = 0x1df1 # macro
|
|
regCP_RB_VMID_BASE_IDX = 0 # macro
|
|
regCP_ME0_PIPE0_VMID = 0x1df2 # macro
|
|
regCP_ME0_PIPE0_VMID_BASE_IDX = 0 # macro
|
|
regCP_ME0_PIPE1_VMID = 0x1df3 # macro
|
|
regCP_ME0_PIPE1_VMID_BASE_IDX = 0 # macro
|
|
regCP_RB0_WPTR = 0x1df4 # macro
|
|
regCP_RB0_WPTR_BASE_IDX = 0 # macro
|
|
regCP_RB_WPTR = 0x1df4 # macro
|
|
regCP_RB_WPTR_BASE_IDX = 0 # macro
|
|
regCP_RB0_WPTR_HI = 0x1df5 # macro
|
|
regCP_RB0_WPTR_HI_BASE_IDX = 0 # macro
|
|
regCP_RB_WPTR_HI = 0x1df5 # macro
|
|
regCP_RB_WPTR_HI_BASE_IDX = 0 # macro
|
|
regCP_RB1_WPTR = 0x1df6 # macro
|
|
regCP_RB1_WPTR_BASE_IDX = 0 # macro
|
|
regCP_RB1_WPTR_HI = 0x1df7 # macro
|
|
regCP_RB1_WPTR_HI_BASE_IDX = 0 # macro
|
|
regCP_PROCESS_QUANTUM = 0x1df9 # macro
|
|
regCP_PROCESS_QUANTUM_BASE_IDX = 0 # macro
|
|
regCP_RB_DOORBELL_RANGE_LOWER = 0x1dfa # macro
|
|
regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro
|
|
regCP_RB_DOORBELL_RANGE_UPPER = 0x1dfb # macro
|
|
regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro
|
|
regCP_MEC_DOORBELL_RANGE_LOWER = 0x1dfc # macro
|
|
regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro
|
|
regCP_MEC_DOORBELL_RANGE_UPPER = 0x1dfd # macro
|
|
regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro
|
|
regCPG_UTCL1_ERROR = 0x1dfe # macro
|
|
regCPG_UTCL1_ERROR_BASE_IDX = 0 # macro
|
|
regCPC_UTCL1_ERROR = 0x1dff # macro
|
|
regCPC_UTCL1_ERROR_BASE_IDX = 0 # macro
|
|
regCP_RB1_BASE = 0x1e00 # macro
|
|
regCP_RB1_BASE_BASE_IDX = 0 # macro
|
|
regCP_RB1_CNTL = 0x1e01 # macro
|
|
regCP_RB1_CNTL_BASE_IDX = 0 # macro
|
|
regCP_RB1_RPTR_ADDR = 0x1e02 # macro
|
|
regCP_RB1_RPTR_ADDR_BASE_IDX = 0 # macro
|
|
regCP_RB1_RPTR_ADDR_HI = 0x1e03 # macro
|
|
regCP_RB1_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_RB1_BUFSZ_MASK = 0x1e04 # macro
|
|
regCP_RB1_BUFSZ_MASK_BASE_IDX = 0 # macro
|
|
regCP_INT_CNTL_RING0 = 0x1e0a # macro
|
|
regCP_INT_CNTL_RING0_BASE_IDX = 0 # macro
|
|
regCP_INT_CNTL_RING1 = 0x1e0b # macro
|
|
regCP_INT_CNTL_RING1_BASE_IDX = 0 # macro
|
|
regCP_INT_STATUS_RING0 = 0x1e0d # macro
|
|
regCP_INT_STATUS_RING0_BASE_IDX = 0 # macro
|
|
regCP_INT_STATUS_RING1 = 0x1e0e # macro
|
|
regCP_INT_STATUS_RING1_BASE_IDX = 0 # macro
|
|
regCP_ME_F32_INTERRUPT = 0x1e13 # macro
|
|
regCP_ME_F32_INTERRUPT_BASE_IDX = 0 # macro
|
|
regCP_PFP_F32_INTERRUPT = 0x1e14 # macro
|
|
regCP_PFP_F32_INTERRUPT_BASE_IDX = 0 # macro
|
|
regCP_MEC1_F32_INTERRUPT = 0x1e16 # macro
|
|
regCP_MEC1_F32_INTERRUPT_BASE_IDX = 0 # macro
|
|
regCP_MEC2_F32_INTERRUPT = 0x1e17 # macro
|
|
regCP_MEC2_F32_INTERRUPT_BASE_IDX = 0 # macro
|
|
regCP_PWR_CNTL = 0x1e18 # macro
|
|
regCP_PWR_CNTL_BASE_IDX = 0 # macro
|
|
regCP_ECC_FIRSTOCCURRENCE = 0x1e1a # macro
|
|
regCP_ECC_FIRSTOCCURRENCE_BASE_IDX = 0 # macro
|
|
regCP_ECC_FIRSTOCCURRENCE_RING0 = 0x1e1b # macro
|
|
regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX = 0 # macro
|
|
regCP_ECC_FIRSTOCCURRENCE_RING1 = 0x1e1c # macro
|
|
regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX = 0 # macro
|
|
regGB_EDC_MODE = 0x1e1e # macro
|
|
regGB_EDC_MODE_BASE_IDX = 0 # macro
|
|
regCP_DEBUG = 0x1e1f # macro
|
|
regCP_DEBUG_BASE_IDX = 0 # macro
|
|
regCP_CPC_DEBUG = 0x1e21 # macro
|
|
regCP_CPC_DEBUG_BASE_IDX = 0 # macro
|
|
regCP_PQ_WPTR_POLL_CNTL = 0x1e23 # macro
|
|
regCP_PQ_WPTR_POLL_CNTL_BASE_IDX = 0 # macro
|
|
regCP_PQ_WPTR_POLL_CNTL1 = 0x1e24 # macro
|
|
regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX = 0 # macro
|
|
regCP_ME1_PIPE0_INT_CNTL = 0x1e25 # macro
|
|
regCP_ME1_PIPE0_INT_CNTL_BASE_IDX = 0 # macro
|
|
regCP_ME1_PIPE1_INT_CNTL = 0x1e26 # macro
|
|
regCP_ME1_PIPE1_INT_CNTL_BASE_IDX = 0 # macro
|
|
regCP_ME1_PIPE2_INT_CNTL = 0x1e27 # macro
|
|
regCP_ME1_PIPE2_INT_CNTL_BASE_IDX = 0 # macro
|
|
regCP_ME1_PIPE3_INT_CNTL = 0x1e28 # macro
|
|
regCP_ME1_PIPE3_INT_CNTL_BASE_IDX = 0 # macro
|
|
regCP_ME2_PIPE0_INT_CNTL = 0x1e29 # macro
|
|
regCP_ME2_PIPE0_INT_CNTL_BASE_IDX = 0 # macro
|
|
regCP_ME2_PIPE1_INT_CNTL = 0x1e2a # macro
|
|
regCP_ME2_PIPE1_INT_CNTL_BASE_IDX = 0 # macro
|
|
regCP_ME2_PIPE2_INT_CNTL = 0x1e2b # macro
|
|
regCP_ME2_PIPE2_INT_CNTL_BASE_IDX = 0 # macro
|
|
regCP_ME2_PIPE3_INT_CNTL = 0x1e2c # macro
|
|
regCP_ME2_PIPE3_INT_CNTL_BASE_IDX = 0 # macro
|
|
regCP_ME1_PIPE0_INT_STATUS = 0x1e2d # macro
|
|
regCP_ME1_PIPE0_INT_STATUS_BASE_IDX = 0 # macro
|
|
regCP_ME1_PIPE1_INT_STATUS = 0x1e2e # macro
|
|
regCP_ME1_PIPE1_INT_STATUS_BASE_IDX = 0 # macro
|
|
regCP_ME1_PIPE2_INT_STATUS = 0x1e2f # macro
|
|
regCP_ME1_PIPE2_INT_STATUS_BASE_IDX = 0 # macro
|
|
regCP_ME1_PIPE3_INT_STATUS = 0x1e30 # macro
|
|
regCP_ME1_PIPE3_INT_STATUS_BASE_IDX = 0 # macro
|
|
regCP_ME2_PIPE0_INT_STATUS = 0x1e31 # macro
|
|
regCP_ME2_PIPE0_INT_STATUS_BASE_IDX = 0 # macro
|
|
regCP_ME2_PIPE1_INT_STATUS = 0x1e32 # macro
|
|
regCP_ME2_PIPE1_INT_STATUS_BASE_IDX = 0 # macro
|
|
regCP_ME2_PIPE2_INT_STATUS = 0x1e33 # macro
|
|
regCP_ME2_PIPE2_INT_STATUS_BASE_IDX = 0 # macro
|
|
regCP_ME2_PIPE3_INT_STATUS = 0x1e34 # macro
|
|
regCP_ME2_PIPE3_INT_STATUS_BASE_IDX = 0 # macro
|
|
regCP_GFX_QUEUE_INDEX = 0x1e37 # macro
|
|
regCP_GFX_QUEUE_INDEX_BASE_IDX = 0 # macro
|
|
regCC_GC_EDC_CONFIG = 0x1e38 # macro
|
|
regCC_GC_EDC_CONFIG_BASE_IDX = 0 # macro
|
|
regCP_ME1_PIPE_PRIORITY_CNTS = 0x1e39 # macro
|
|
regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro
|
|
regCP_ME1_PIPE0_PRIORITY = 0x1e3a # macro
|
|
regCP_ME1_PIPE0_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_ME1_PIPE1_PRIORITY = 0x1e3b # macro
|
|
regCP_ME1_PIPE1_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_ME1_PIPE2_PRIORITY = 0x1e3c # macro
|
|
regCP_ME1_PIPE2_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_ME1_PIPE3_PRIORITY = 0x1e3d # macro
|
|
regCP_ME1_PIPE3_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_ME2_PIPE_PRIORITY_CNTS = 0x1e3e # macro
|
|
regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro
|
|
regCP_ME2_PIPE0_PRIORITY = 0x1e3f # macro
|
|
regCP_ME2_PIPE0_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_ME2_PIPE1_PRIORITY = 0x1e40 # macro
|
|
regCP_ME2_PIPE1_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_ME2_PIPE2_PRIORITY = 0x1e41 # macro
|
|
regCP_ME2_PIPE2_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_ME2_PIPE3_PRIORITY = 0x1e42 # macro
|
|
regCP_ME2_PIPE3_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_PFP_PRGRM_CNTR_START = 0x1e44 # macro
|
|
regCP_PFP_PRGRM_CNTR_START_BASE_IDX = 0 # macro
|
|
regCP_ME_PRGRM_CNTR_START = 0x1e45 # macro
|
|
regCP_ME_PRGRM_CNTR_START_BASE_IDX = 0 # macro
|
|
regCP_MEC1_PRGRM_CNTR_START = 0x1e46 # macro
|
|
regCP_MEC1_PRGRM_CNTR_START_BASE_IDX = 0 # macro
|
|
regCP_MEC2_PRGRM_CNTR_START = 0x1e47 # macro
|
|
regCP_MEC2_PRGRM_CNTR_START_BASE_IDX = 0 # macro
|
|
regCP_PFP_INTR_ROUTINE_START = 0x1e49 # macro
|
|
regCP_PFP_INTR_ROUTINE_START_BASE_IDX = 0 # macro
|
|
regCP_ME_INTR_ROUTINE_START = 0x1e4a # macro
|
|
regCP_ME_INTR_ROUTINE_START_BASE_IDX = 0 # macro
|
|
regCP_MEC1_INTR_ROUTINE_START = 0x1e4b # macro
|
|
regCP_MEC1_INTR_ROUTINE_START_BASE_IDX = 0 # macro
|
|
regCP_MEC2_INTR_ROUTINE_START = 0x1e4c # macro
|
|
regCP_MEC2_INTR_ROUTINE_START_BASE_IDX = 0 # macro
|
|
regCP_CONTEXT_CNTL = 0x1e4d # macro
|
|
regCP_CONTEXT_CNTL_BASE_IDX = 0 # macro
|
|
regCP_MAX_CONTEXT = 0x1e4e # macro
|
|
regCP_MAX_CONTEXT_BASE_IDX = 0 # macro
|
|
regCP_IQ_WAIT_TIME1 = 0x1e4f # macro
|
|
regCP_IQ_WAIT_TIME1_BASE_IDX = 0 # macro
|
|
regCP_IQ_WAIT_TIME2 = 0x1e50 # macro
|
|
regCP_IQ_WAIT_TIME2_BASE_IDX = 0 # macro
|
|
regCP_RB0_BASE_HI = 0x1e51 # macro
|
|
regCP_RB0_BASE_HI_BASE_IDX = 0 # macro
|
|
regCP_RB1_BASE_HI = 0x1e52 # macro
|
|
regCP_RB1_BASE_HI_BASE_IDX = 0 # macro
|
|
regCP_VMID_RESET = 0x1e53 # macro
|
|
regCP_VMID_RESET_BASE_IDX = 0 # macro
|
|
regCPC_INT_CNTL = 0x1e54 # macro
|
|
regCPC_INT_CNTL_BASE_IDX = 0 # macro
|
|
regCPC_INT_STATUS = 0x1e55 # macro
|
|
regCPC_INT_STATUS_BASE_IDX = 0 # macro
|
|
regCP_VMID_PREEMPT = 0x1e56 # macro
|
|
regCP_VMID_PREEMPT_BASE_IDX = 0 # macro
|
|
regCPC_INT_CNTX_ID = 0x1e57 # macro
|
|
regCPC_INT_CNTX_ID_BASE_IDX = 0 # macro
|
|
regCP_PQ_STATUS = 0x1e58 # macro
|
|
regCP_PQ_STATUS_BASE_IDX = 0 # macro
|
|
regCP_PFP_PRGRM_CNTR_START_HI = 0x1e59 # macro
|
|
regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX = 0 # macro
|
|
regCP_MAX_DRAW_COUNT = 0x1e5c # macro
|
|
regCP_MAX_DRAW_COUNT_BASE_IDX = 0 # macro
|
|
regCP_MEC1_F32_INT_DIS = 0x1e5d # macro
|
|
regCP_MEC1_F32_INT_DIS_BASE_IDX = 0 # macro
|
|
regCP_MEC2_F32_INT_DIS = 0x1e5e # macro
|
|
regCP_MEC2_F32_INT_DIS_BASE_IDX = 0 # macro
|
|
regCP_VMID_STATUS = 0x1e5f # macro
|
|
regCP_VMID_STATUS_BASE_IDX = 0 # macro
|
|
regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO = 0x1e60 # macro
|
|
regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI = 0x1e61 # macro
|
|
regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCPC_SUSPEND_CTX_SAVE_CONTROL = 0x1e62 # macro
|
|
regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro
|
|
regCPC_SUSPEND_CNTL_STACK_OFFSET = 0x1e63 # macro
|
|
regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro
|
|
regCPC_SUSPEND_CNTL_STACK_SIZE = 0x1e64 # macro
|
|
regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX = 0 # macro
|
|
regCPC_SUSPEND_WG_STATE_OFFSET = 0x1e65 # macro
|
|
regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro
|
|
regCPC_SUSPEND_CTX_SAVE_SIZE = 0x1e66 # macro
|
|
regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX = 0 # macro
|
|
regCPC_OS_PIPES = 0x1e67 # macro
|
|
regCPC_OS_PIPES_BASE_IDX = 0 # macro
|
|
regCP_SUSPEND_RESUME_REQ = 0x1e68 # macro
|
|
regCP_SUSPEND_RESUME_REQ_BASE_IDX = 0 # macro
|
|
regCP_SUSPEND_CNTL = 0x1e69 # macro
|
|
regCP_SUSPEND_CNTL_BASE_IDX = 0 # macro
|
|
regCP_IQ_WAIT_TIME3 = 0x1e6a # macro
|
|
regCP_IQ_WAIT_TIME3_BASE_IDX = 0 # macro
|
|
regCPC_DDID_BASE_ADDR_LO = 0x1e6b # macro
|
|
regCPC_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCP_DDID_BASE_ADDR_LO = 0x1e6b # macro
|
|
regCP_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCPC_DDID_BASE_ADDR_HI = 0x1e6c # macro
|
|
regCPC_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_DDID_BASE_ADDR_HI = 0x1e6c # macro
|
|
regCP_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCPC_DDID_CNTL = 0x1e6d # macro
|
|
regCPC_DDID_CNTL_BASE_IDX = 0 # macro
|
|
regCP_DDID_CNTL = 0x1e6d # macro
|
|
regCP_DDID_CNTL_BASE_IDX = 0 # macro
|
|
regCP_GFX_DDID_INFLIGHT_COUNT = 0x1e6e # macro
|
|
regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro
|
|
regCP_GFX_DDID_WPTR = 0x1e6f # macro
|
|
regCP_GFX_DDID_WPTR_BASE_IDX = 0 # macro
|
|
regCP_GFX_DDID_RPTR = 0x1e70 # macro
|
|
regCP_GFX_DDID_RPTR_BASE_IDX = 0 # macro
|
|
regCP_GFX_DDID_DELTA_RPT_COUNT = 0x1e71 # macro
|
|
regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro
|
|
regCP_GFX_HPD_STATUS0 = 0x1e72 # macro
|
|
regCP_GFX_HPD_STATUS0_BASE_IDX = 0 # macro
|
|
regCP_GFX_HPD_CONTROL0 = 0x1e73 # macro
|
|
regCP_GFX_HPD_CONTROL0_BASE_IDX = 0 # macro
|
|
regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO = 0x1e74 # macro
|
|
regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI = 0x1e75 # macro
|
|
regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_GFX_HPD_OSPRE_FENCE_DATA_LO = 0x1e76 # macro
|
|
regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX = 0 # macro
|
|
regCP_GFX_HPD_OSPRE_FENCE_DATA_HI = 0x1e77 # macro
|
|
regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX = 0 # macro
|
|
regCP_GFX_INDEX_MUTEX = 0x1e78 # macro
|
|
regCP_GFX_INDEX_MUTEX_BASE_IDX = 0 # macro
|
|
regCP_ME_PRGRM_CNTR_START_HI = 0x1e79 # macro
|
|
regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX = 0 # macro
|
|
regCP_PFP_INTR_ROUTINE_START_HI = 0x1e7a # macro
|
|
regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX = 0 # macro
|
|
regCP_ME_INTR_ROUTINE_START_HI = 0x1e7b # macro
|
|
regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX = 0 # macro
|
|
regCP_GFX_MQD_BASE_ADDR = 0x1e7e # macro
|
|
regCP_GFX_MQD_BASE_ADDR_BASE_IDX = 0 # macro
|
|
regCP_GFX_MQD_BASE_ADDR_HI = 0x1e7f # macro
|
|
regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_ACTIVE = 0x1e80 # macro
|
|
regCP_GFX_HQD_ACTIVE_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_VMID = 0x1e81 # macro
|
|
regCP_GFX_HQD_VMID_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_QUEUE_PRIORITY = 0x1e84 # macro
|
|
regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_QUANTUM = 0x1e85 # macro
|
|
regCP_GFX_HQD_QUANTUM_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_BASE = 0x1e86 # macro
|
|
regCP_GFX_HQD_BASE_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_BASE_HI = 0x1e87 # macro
|
|
regCP_GFX_HQD_BASE_HI_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_RPTR = 0x1e88 # macro
|
|
regCP_GFX_HQD_RPTR_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_RPTR_ADDR = 0x1e89 # macro
|
|
regCP_GFX_HQD_RPTR_ADDR_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_RPTR_ADDR_HI = 0x1e8a # macro
|
|
regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_RB_WPTR_POLL_ADDR_LO = 0x1e8b # macro
|
|
regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCP_RB_WPTR_POLL_ADDR_HI = 0x1e8c # macro
|
|
regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_RB_DOORBELL_CONTROL = 0x1e8d # macro
|
|
regCP_RB_DOORBELL_CONTROL_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_OFFSET = 0x1e8e # macro
|
|
regCP_GFX_HQD_OFFSET_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_CNTL = 0x1e8f # macro
|
|
regCP_GFX_HQD_CNTL_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_CSMD_RPTR = 0x1e90 # macro
|
|
regCP_GFX_HQD_CSMD_RPTR_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_WPTR = 0x1e91 # macro
|
|
regCP_GFX_HQD_WPTR_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_WPTR_HI = 0x1e92 # macro
|
|
regCP_GFX_HQD_WPTR_HI_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_DEQUEUE_REQUEST = 0x1e93 # macro
|
|
regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_MAPPED = 0x1e94 # macro
|
|
regCP_GFX_HQD_MAPPED_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_QUE_MGR_CONTROL = 0x1e95 # macro
|
|
regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_IQ_TIMER = 0x1e96 # macro
|
|
regCP_GFX_HQD_IQ_TIMER_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_HQ_STATUS0 = 0x1e98 # macro
|
|
regCP_GFX_HQD_HQ_STATUS0_BASE_IDX = 0 # macro
|
|
regCP_GFX_HQD_HQ_CONTROL0 = 0x1e99 # macro
|
|
regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro
|
|
regCP_GFX_MQD_CONTROL = 0x1e9a # macro
|
|
regCP_GFX_MQD_CONTROL_BASE_IDX = 0 # macro
|
|
regCP_HQD_GFX_CONTROL = 0x1e9f # macro
|
|
regCP_HQD_GFX_CONTROL_BASE_IDX = 0 # macro
|
|
regCP_HQD_GFX_STATUS = 0x1ea0 # macro
|
|
regCP_HQD_GFX_STATUS_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH0_ADDR_LO = 0x1ec0 # macro
|
|
regCP_DMA_WATCH0_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH0_ADDR_HI = 0x1ec1 # macro
|
|
regCP_DMA_WATCH0_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH0_MASK = 0x1ec2 # macro
|
|
regCP_DMA_WATCH0_MASK_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH0_CNTL = 0x1ec3 # macro
|
|
regCP_DMA_WATCH0_CNTL_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH1_ADDR_LO = 0x1ec4 # macro
|
|
regCP_DMA_WATCH1_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH1_ADDR_HI = 0x1ec5 # macro
|
|
regCP_DMA_WATCH1_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH1_MASK = 0x1ec6 # macro
|
|
regCP_DMA_WATCH1_MASK_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH1_CNTL = 0x1ec7 # macro
|
|
regCP_DMA_WATCH1_CNTL_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH2_ADDR_LO = 0x1ec8 # macro
|
|
regCP_DMA_WATCH2_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH2_ADDR_HI = 0x1ec9 # macro
|
|
regCP_DMA_WATCH2_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH2_MASK = 0x1eca # macro
|
|
regCP_DMA_WATCH2_MASK_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH2_CNTL = 0x1ecb # macro
|
|
regCP_DMA_WATCH2_CNTL_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH3_ADDR_LO = 0x1ecc # macro
|
|
regCP_DMA_WATCH3_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH3_ADDR_HI = 0x1ecd # macro
|
|
regCP_DMA_WATCH3_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH3_MASK = 0x1ece # macro
|
|
regCP_DMA_WATCH3_MASK_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH3_CNTL = 0x1ecf # macro
|
|
regCP_DMA_WATCH3_CNTL_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH_STAT_ADDR_LO = 0x1ed0 # macro
|
|
regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH_STAT_ADDR_HI = 0x1ed1 # macro
|
|
regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_DMA_WATCH_STAT = 0x1ed2 # macro
|
|
regCP_DMA_WATCH_STAT_BASE_IDX = 0 # macro
|
|
regCP_PFP_JT_STAT = 0x1ed3 # macro
|
|
regCP_PFP_JT_STAT_BASE_IDX = 0 # macro
|
|
regCP_MEC_JT_STAT = 0x1ed5 # macro
|
|
regCP_MEC_JT_STAT_BASE_IDX = 0 # macro
|
|
regCP_CPC_BUSY_HYSTERESIS = 0x1edb # macro
|
|
regCP_CPC_BUSY_HYSTERESIS_BASE_IDX = 0 # macro
|
|
regCP_CPF_BUSY_HYSTERESIS1 = 0x1edc # macro
|
|
regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX = 0 # macro
|
|
regCP_CPF_BUSY_HYSTERESIS2 = 0x1edd # macro
|
|
regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX = 0 # macro
|
|
regCP_CPG_BUSY_HYSTERESIS1 = 0x1ede # macro
|
|
regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX = 0 # macro
|
|
regCP_CPG_BUSY_HYSTERESIS2 = 0x1edf # macro
|
|
regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX = 0 # macro
|
|
regCP_RB_DOORBELL_CLEAR = 0x1f28 # macro
|
|
regCP_RB_DOORBELL_CLEAR_BASE_IDX = 0 # macro
|
|
regCP_RB0_ACTIVE = 0x1f40 # macro
|
|
regCP_RB0_ACTIVE_BASE_IDX = 0 # macro
|
|
regCP_RB_ACTIVE = 0x1f40 # macro
|
|
regCP_RB_ACTIVE_BASE_IDX = 0 # macro
|
|
regCP_RB1_ACTIVE = 0x1f41 # macro
|
|
regCP_RB1_ACTIVE_BASE_IDX = 0 # macro
|
|
regCP_RB_STATUS = 0x1f43 # macro
|
|
regCP_RB_STATUS_BASE_IDX = 0 # macro
|
|
regCPG_RCIU_CAM_INDEX = 0x1f44 # macro
|
|
regCPG_RCIU_CAM_INDEX_BASE_IDX = 0 # macro
|
|
regCPG_RCIU_CAM_DATA = 0x1f45 # macro
|
|
regCPG_RCIU_CAM_DATA_BASE_IDX = 0 # macro
|
|
regCPG_RCIU_CAM_DATA_PHASE0 = 0x1f45 # macro
|
|
regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX = 0 # macro
|
|
regCPG_RCIU_CAM_DATA_PHASE1 = 0x1f45 # macro
|
|
regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX = 0 # macro
|
|
regCPG_RCIU_CAM_DATA_PHASE2 = 0x1f45 # macro
|
|
regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX = 0 # macro
|
|
regCP_GPU_TIMESTAMP_OFFSET_LO = 0x1f4c # macro
|
|
regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX = 0 # macro
|
|
regCP_GPU_TIMESTAMP_OFFSET_HI = 0x1f4d # macro
|
|
regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX = 0 # macro
|
|
regCP_SDMA_DMA_DONE = 0x1f4e # macro
|
|
regCP_SDMA_DMA_DONE_BASE_IDX = 0 # macro
|
|
regCP_PFP_SDMA_CS = 0x1f4f # macro
|
|
regCP_PFP_SDMA_CS_BASE_IDX = 0 # macro
|
|
regCP_ME_SDMA_CS = 0x1f50 # macro
|
|
regCP_ME_SDMA_CS_BASE_IDX = 0 # macro
|
|
regCPF_GCR_CNTL = 0x1f53 # macro
|
|
regCPF_GCR_CNTL_BASE_IDX = 0 # macro
|
|
regCPG_UTCL1_STATUS = 0x1f54 # macro
|
|
regCPG_UTCL1_STATUS_BASE_IDX = 0 # macro
|
|
regCPC_UTCL1_STATUS = 0x1f55 # macro
|
|
regCPC_UTCL1_STATUS_BASE_IDX = 0 # macro
|
|
regCPF_UTCL1_STATUS = 0x1f56 # macro
|
|
regCPF_UTCL1_STATUS_BASE_IDX = 0 # macro
|
|
regCP_SD_CNTL = 0x1f57 # macro
|
|
regCP_SD_CNTL_BASE_IDX = 0 # macro
|
|
regCP_SOFT_RESET_CNTL = 0x1f59 # macro
|
|
regCP_SOFT_RESET_CNTL_BASE_IDX = 0 # macro
|
|
regCP_CPC_GFX_CNTL = 0x1f5a # macro
|
|
regCP_CPC_GFX_CNTL_BASE_IDX = 0 # macro
|
|
regSPI_ARB_PRIORITY = 0x1f60 # macro
|
|
regSPI_ARB_PRIORITY_BASE_IDX = 0 # macro
|
|
regSPI_ARB_CYCLES_0 = 0x1f61 # macro
|
|
regSPI_ARB_CYCLES_0_BASE_IDX = 0 # macro
|
|
regSPI_ARB_CYCLES_1 = 0x1f62 # macro
|
|
regSPI_ARB_CYCLES_1_BASE_IDX = 0 # macro
|
|
regSPI_WCL_PIPE_PERCENT_GFX = 0x1f67 # macro
|
|
regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX = 0 # macro
|
|
regSPI_WCL_PIPE_PERCENT_HP3D = 0x1f68 # macro
|
|
regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX = 0 # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS0 = 0x1f69 # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX = 0 # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS1 = 0x1f6a # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX = 0 # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS2 = 0x1f6b # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX = 0 # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS3 = 0x1f6c # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX = 0 # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS4 = 0x1f6d # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX = 0 # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS5 = 0x1f6e # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX = 0 # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS6 = 0x1f6f # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX = 0 # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS7 = 0x1f70 # macro
|
|
regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX = 0 # macro
|
|
regSPI_USER_ACCUM_VMID_CNTL = 0x1f71 # macro
|
|
regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX = 0 # macro
|
|
regSPI_GDBG_PER_VMID_CNTL = 0x1f72 # macro
|
|
regSPI_GDBG_PER_VMID_CNTL_BASE_IDX = 0 # macro
|
|
regSPI_COMPUTE_QUEUE_RESET = 0x1f73 # macro
|
|
regSPI_COMPUTE_QUEUE_RESET_BASE_IDX = 0 # macro
|
|
regSPI_COMPUTE_WF_CTX_SAVE = 0x1f74 # macro
|
|
regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX = 0 # macro
|
|
regCP_HPD_UTCL1_CNTL = 0x1fa3 # macro
|
|
regCP_HPD_UTCL1_CNTL_BASE_IDX = 0 # macro
|
|
regCP_HPD_UTCL1_ERROR = 0x1fa7 # macro
|
|
regCP_HPD_UTCL1_ERROR_BASE_IDX = 0 # macro
|
|
regCP_HPD_UTCL1_ERROR_ADDR = 0x1fa8 # macro
|
|
regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX = 0 # macro
|
|
regCP_MQD_BASE_ADDR = 0x1fa9 # macro
|
|
regCP_MQD_BASE_ADDR_BASE_IDX = 0 # macro
|
|
regCP_MQD_BASE_ADDR_HI = 0x1faa # macro
|
|
regCP_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_HQD_ACTIVE = 0x1fab # macro
|
|
regCP_HQD_ACTIVE_BASE_IDX = 0 # macro
|
|
regCP_HQD_VMID = 0x1fac # macro
|
|
regCP_HQD_VMID_BASE_IDX = 0 # macro
|
|
regCP_HQD_PERSISTENT_STATE = 0x1fad # macro
|
|
regCP_HQD_PERSISTENT_STATE_BASE_IDX = 0 # macro
|
|
regCP_HQD_PIPE_PRIORITY = 0x1fae # macro
|
|
regCP_HQD_PIPE_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_HQD_QUEUE_PRIORITY = 0x1faf # macro
|
|
regCP_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro
|
|
regCP_HQD_QUANTUM = 0x1fb0 # macro
|
|
regCP_HQD_QUANTUM_BASE_IDX = 0 # macro
|
|
regCP_HQD_PQ_BASE = 0x1fb1 # macro
|
|
regCP_HQD_PQ_BASE_BASE_IDX = 0 # macro
|
|
regCP_HQD_PQ_BASE_HI = 0x1fb2 # macro
|
|
regCP_HQD_PQ_BASE_HI_BASE_IDX = 0 # macro
|
|
regCP_HQD_PQ_RPTR = 0x1fb3 # macro
|
|
regCP_HQD_PQ_RPTR_BASE_IDX = 0 # macro
|
|
regCP_HQD_PQ_RPTR_REPORT_ADDR = 0x1fb4 # macro
|
|
regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX = 0 # macro
|
|
regCP_HQD_PQ_RPTR_REPORT_ADDR_HI = 0x1fb5 # macro
|
|
regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_HQD_PQ_WPTR_POLL_ADDR = 0x1fb6 # macro
|
|
regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX = 0 # macro
|
|
regCP_HQD_PQ_WPTR_POLL_ADDR_HI = 0x1fb7 # macro
|
|
regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_HQD_PQ_DOORBELL_CONTROL = 0x1fb8 # macro
|
|
regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX = 0 # macro
|
|
regCP_HQD_PQ_CONTROL = 0x1fba # macro
|
|
regCP_HQD_PQ_CONTROL_BASE_IDX = 0 # macro
|
|
regCP_HQD_IB_BASE_ADDR = 0x1fbb # macro
|
|
regCP_HQD_IB_BASE_ADDR_BASE_IDX = 0 # macro
|
|
regCP_HQD_IB_BASE_ADDR_HI = 0x1fbc # macro
|
|
regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_HQD_IB_RPTR = 0x1fbd # macro
|
|
regCP_HQD_IB_RPTR_BASE_IDX = 0 # macro
|
|
regCP_HQD_IB_CONTROL = 0x1fbe # macro
|
|
regCP_HQD_IB_CONTROL_BASE_IDX = 0 # macro
|
|
regCP_HQD_IQ_TIMER = 0x1fbf # macro
|
|
regCP_HQD_IQ_TIMER_BASE_IDX = 0 # macro
|
|
regCP_HQD_IQ_RPTR = 0x1fc0 # macro
|
|
regCP_HQD_IQ_RPTR_BASE_IDX = 0 # macro
|
|
regCP_HQD_DEQUEUE_REQUEST = 0x1fc1 # macro
|
|
regCP_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro
|
|
regCP_HQD_DMA_OFFLOAD = 0x1fc2 # macro
|
|
regCP_HQD_DMA_OFFLOAD_BASE_IDX = 0 # macro
|
|
regCP_HQD_OFFLOAD = 0x1fc2 # macro
|
|
regCP_HQD_OFFLOAD_BASE_IDX = 0 # macro
|
|
regCP_HQD_SEMA_CMD = 0x1fc3 # macro
|
|
regCP_HQD_SEMA_CMD_BASE_IDX = 0 # macro
|
|
regCP_HQD_MSG_TYPE = 0x1fc4 # macro
|
|
regCP_HQD_MSG_TYPE_BASE_IDX = 0 # macro
|
|
regCP_HQD_ATOMIC0_PREOP_LO = 0x1fc5 # macro
|
|
regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX = 0 # macro
|
|
regCP_HQD_ATOMIC0_PREOP_HI = 0x1fc6 # macro
|
|
regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX = 0 # macro
|
|
regCP_HQD_ATOMIC1_PREOP_LO = 0x1fc7 # macro
|
|
regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX = 0 # macro
|
|
regCP_HQD_ATOMIC1_PREOP_HI = 0x1fc8 # macro
|
|
regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX = 0 # macro
|
|
regCP_HQD_HQ_SCHEDULER0 = 0x1fc9 # macro
|
|
regCP_HQD_HQ_SCHEDULER0_BASE_IDX = 0 # macro
|
|
regCP_HQD_HQ_STATUS0 = 0x1fc9 # macro
|
|
regCP_HQD_HQ_STATUS0_BASE_IDX = 0 # macro
|
|
regCP_HQD_HQ_CONTROL0 = 0x1fca # macro
|
|
regCP_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro
|
|
regCP_HQD_HQ_SCHEDULER1 = 0x1fca # macro
|
|
regCP_HQD_HQ_SCHEDULER1_BASE_IDX = 0 # macro
|
|
regCP_MQD_CONTROL = 0x1fcb # macro
|
|
regCP_MQD_CONTROL_BASE_IDX = 0 # macro
|
|
regCP_HQD_HQ_STATUS1 = 0x1fcc # macro
|
|
regCP_HQD_HQ_STATUS1_BASE_IDX = 0 # macro
|
|
regCP_HQD_HQ_CONTROL1 = 0x1fcd # macro
|
|
regCP_HQD_HQ_CONTROL1_BASE_IDX = 0 # macro
|
|
regCP_HQD_EOP_BASE_ADDR = 0x1fce # macro
|
|
regCP_HQD_EOP_BASE_ADDR_BASE_IDX = 0 # macro
|
|
regCP_HQD_EOP_BASE_ADDR_HI = 0x1fcf # macro
|
|
regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_HQD_EOP_CONTROL = 0x1fd0 # macro
|
|
regCP_HQD_EOP_CONTROL_BASE_IDX = 0 # macro
|
|
regCP_HQD_EOP_RPTR = 0x1fd1 # macro
|
|
regCP_HQD_EOP_RPTR_BASE_IDX = 0 # macro
|
|
regCP_HQD_EOP_WPTR = 0x1fd2 # macro
|
|
regCP_HQD_EOP_WPTR_BASE_IDX = 0 # macro
|
|
regCP_HQD_EOP_EVENTS = 0x1fd3 # macro
|
|
regCP_HQD_EOP_EVENTS_BASE_IDX = 0 # macro
|
|
regCP_HQD_CTX_SAVE_BASE_ADDR_LO = 0x1fd4 # macro
|
|
regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro
|
|
regCP_HQD_CTX_SAVE_BASE_ADDR_HI = 0x1fd5 # macro
|
|
regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro
|
|
regCP_HQD_CTX_SAVE_CONTROL = 0x1fd6 # macro
|
|
regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro
|
|
regCP_HQD_CNTL_STACK_OFFSET = 0x1fd7 # macro
|
|
regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro
|
|
regCP_HQD_CNTL_STACK_SIZE = 0x1fd8 # macro
|
|
regCP_HQD_CNTL_STACK_SIZE_BASE_IDX = 0 # macro
|
|
regCP_HQD_WG_STATE_OFFSET = 0x1fd9 # macro
|
|
regCP_HQD_WG_STATE_OFFSET_BASE_IDX = 0 # macro
|
|
regCP_HQD_CTX_SAVE_SIZE = 0x1fda # macro
|
|
regCP_HQD_CTX_SAVE_SIZE_BASE_IDX = 0 # macro
|
|
regCP_HQD_GDS_RESOURCE_STATE = 0x1fdb # macro
|
|
regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX = 0 # macro
|
|
regCP_HQD_ERROR = 0x1fdc # macro
|
|
regCP_HQD_ERROR_BASE_IDX = 0 # macro
|
|
regCP_HQD_EOP_WPTR_MEM = 0x1fdd # macro
|
|
regCP_HQD_EOP_WPTR_MEM_BASE_IDX = 0 # macro
|
|
regCP_HQD_AQL_CONTROL = 0x1fde # macro
|
|
regCP_HQD_AQL_CONTROL_BASE_IDX = 0 # macro
|
|
regCP_HQD_PQ_WPTR_LO = 0x1fdf # macro
|
|
regCP_HQD_PQ_WPTR_LO_BASE_IDX = 0 # macro
|
|
regCP_HQD_PQ_WPTR_HI = 0x1fe0 # macro
|
|
regCP_HQD_PQ_WPTR_HI_BASE_IDX = 0 # macro
|
|
regCP_HQD_SUSPEND_CNTL_STACK_OFFSET = 0x1fe1 # macro
|
|
regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro
|
|
regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT = 0x1fe2 # macro
|
|
regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX = 0 # macro
|
|
regCP_HQD_SUSPEND_WG_STATE_OFFSET = 0x1fe3 # macro
|
|
regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro
|
|
regCP_HQD_DDID_RPTR = 0x1fe4 # macro
|
|
regCP_HQD_DDID_RPTR_BASE_IDX = 0 # macro
|
|
regCP_HQD_DDID_WPTR = 0x1fe5 # macro
|
|
regCP_HQD_DDID_WPTR_BASE_IDX = 0 # macro
|
|
regCP_HQD_DDID_INFLIGHT_COUNT = 0x1fe6 # macro
|
|
regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro
|
|
regCP_HQD_DDID_DELTA_RPT_COUNT = 0x1fe7 # macro
|
|
regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro
|
|
regCP_HQD_DEQUEUE_STATUS = 0x1fe8 # macro
|
|
regCP_HQD_DEQUEUE_STATUS_BASE_IDX = 0 # macro
|
|
regTCP_WATCH0_ADDR_H = 0x2048 # macro
|
|
regTCP_WATCH0_ADDR_H_BASE_IDX = 0 # macro
|
|
regTCP_WATCH0_ADDR_L = 0x2049 # macro
|
|
regTCP_WATCH0_ADDR_L_BASE_IDX = 0 # macro
|
|
regTCP_WATCH0_CNTL = 0x204a # macro
|
|
regTCP_WATCH0_CNTL_BASE_IDX = 0 # macro
|
|
regTCP_WATCH1_ADDR_H = 0x204b # macro
|
|
regTCP_WATCH1_ADDR_H_BASE_IDX = 0 # macro
|
|
regTCP_WATCH1_ADDR_L = 0x204c # macro
|
|
regTCP_WATCH1_ADDR_L_BASE_IDX = 0 # macro
|
|
regTCP_WATCH1_CNTL = 0x204d # macro
|
|
regTCP_WATCH1_CNTL_BASE_IDX = 0 # macro
|
|
regTCP_WATCH2_ADDR_H = 0x204e # macro
|
|
regTCP_WATCH2_ADDR_H_BASE_IDX = 0 # macro
|
|
regTCP_WATCH2_ADDR_L = 0x204f # macro
|
|
regTCP_WATCH2_ADDR_L_BASE_IDX = 0 # macro
|
|
regTCP_WATCH2_CNTL = 0x2050 # macro
|
|
regTCP_WATCH2_CNTL_BASE_IDX = 0 # macro
|
|
regTCP_WATCH3_ADDR_H = 0x2051 # macro
|
|
regTCP_WATCH3_ADDR_H_BASE_IDX = 0 # macro
|
|
regTCP_WATCH3_ADDR_L = 0x2052 # macro
|
|
regTCP_WATCH3_ADDR_L_BASE_IDX = 0 # macro
|
|
regTCP_WATCH3_CNTL = 0x2053 # macro
|
|
regTCP_WATCH3_CNTL_BASE_IDX = 0 # macro
|
|
regGDS_VMID0_BASE = 0x20a0 # macro
|
|
regGDS_VMID0_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID0_SIZE = 0x20a1 # macro
|
|
regGDS_VMID0_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID1_BASE = 0x20a2 # macro
|
|
regGDS_VMID1_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID1_SIZE = 0x20a3 # macro
|
|
regGDS_VMID1_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID2_BASE = 0x20a4 # macro
|
|
regGDS_VMID2_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID2_SIZE = 0x20a5 # macro
|
|
regGDS_VMID2_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID3_BASE = 0x20a6 # macro
|
|
regGDS_VMID3_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID3_SIZE = 0x20a7 # macro
|
|
regGDS_VMID3_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID4_BASE = 0x20a8 # macro
|
|
regGDS_VMID4_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID4_SIZE = 0x20a9 # macro
|
|
regGDS_VMID4_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID5_BASE = 0x20aa # macro
|
|
regGDS_VMID5_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID5_SIZE = 0x20ab # macro
|
|
regGDS_VMID5_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID6_BASE = 0x20ac # macro
|
|
regGDS_VMID6_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID6_SIZE = 0x20ad # macro
|
|
regGDS_VMID6_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID7_BASE = 0x20ae # macro
|
|
regGDS_VMID7_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID7_SIZE = 0x20af # macro
|
|
regGDS_VMID7_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID8_BASE = 0x20b0 # macro
|
|
regGDS_VMID8_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID8_SIZE = 0x20b1 # macro
|
|
regGDS_VMID8_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID9_BASE = 0x20b2 # macro
|
|
regGDS_VMID9_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID9_SIZE = 0x20b3 # macro
|
|
regGDS_VMID9_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID10_BASE = 0x20b4 # macro
|
|
regGDS_VMID10_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID10_SIZE = 0x20b5 # macro
|
|
regGDS_VMID10_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID11_BASE = 0x20b6 # macro
|
|
regGDS_VMID11_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID11_SIZE = 0x20b7 # macro
|
|
regGDS_VMID11_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID12_BASE = 0x20b8 # macro
|
|
regGDS_VMID12_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID12_SIZE = 0x20b9 # macro
|
|
regGDS_VMID12_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID13_BASE = 0x20ba # macro
|
|
regGDS_VMID13_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID13_SIZE = 0x20bb # macro
|
|
regGDS_VMID13_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID14_BASE = 0x20bc # macro
|
|
regGDS_VMID14_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID14_SIZE = 0x20bd # macro
|
|
regGDS_VMID14_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_VMID15_BASE = 0x20be # macro
|
|
regGDS_VMID15_BASE_BASE_IDX = 0 # macro
|
|
regGDS_VMID15_SIZE = 0x20bf # macro
|
|
regGDS_VMID15_SIZE_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID0 = 0x20c0 # macro
|
|
regGDS_GWS_VMID0_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID1 = 0x20c1 # macro
|
|
regGDS_GWS_VMID1_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID2 = 0x20c2 # macro
|
|
regGDS_GWS_VMID2_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID3 = 0x20c3 # macro
|
|
regGDS_GWS_VMID3_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID4 = 0x20c4 # macro
|
|
regGDS_GWS_VMID4_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID5 = 0x20c5 # macro
|
|
regGDS_GWS_VMID5_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID6 = 0x20c6 # macro
|
|
regGDS_GWS_VMID6_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID7 = 0x20c7 # macro
|
|
regGDS_GWS_VMID7_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID8 = 0x20c8 # macro
|
|
regGDS_GWS_VMID8_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID9 = 0x20c9 # macro
|
|
regGDS_GWS_VMID9_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID10 = 0x20ca # macro
|
|
regGDS_GWS_VMID10_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID11 = 0x20cb # macro
|
|
regGDS_GWS_VMID11_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID12 = 0x20cc # macro
|
|
regGDS_GWS_VMID12_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID13 = 0x20cd # macro
|
|
regGDS_GWS_VMID13_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID14 = 0x20ce # macro
|
|
regGDS_GWS_VMID14_BASE_IDX = 0 # macro
|
|
regGDS_GWS_VMID15 = 0x20cf # macro
|
|
regGDS_GWS_VMID15_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID0 = 0x20d0 # macro
|
|
regGDS_OA_VMID0_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID1 = 0x20d1 # macro
|
|
regGDS_OA_VMID1_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID2 = 0x20d2 # macro
|
|
regGDS_OA_VMID2_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID3 = 0x20d3 # macro
|
|
regGDS_OA_VMID3_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID4 = 0x20d4 # macro
|
|
regGDS_OA_VMID4_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID5 = 0x20d5 # macro
|
|
regGDS_OA_VMID5_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID6 = 0x20d6 # macro
|
|
regGDS_OA_VMID6_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID7 = 0x20d7 # macro
|
|
regGDS_OA_VMID7_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID8 = 0x20d8 # macro
|
|
regGDS_OA_VMID8_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID9 = 0x20d9 # macro
|
|
regGDS_OA_VMID9_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID10 = 0x20da # macro
|
|
regGDS_OA_VMID10_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID11 = 0x20db # macro
|
|
regGDS_OA_VMID11_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID12 = 0x20dc # macro
|
|
regGDS_OA_VMID12_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID13 = 0x20dd # macro
|
|
regGDS_OA_VMID13_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID14 = 0x20de # macro
|
|
regGDS_OA_VMID14_BASE_IDX = 0 # macro
|
|
regGDS_OA_VMID15 = 0x20df # macro
|
|
regGDS_OA_VMID15_BASE_IDX = 0 # macro
|
|
regGDS_GWS_RESET0 = 0x20e4 # macro
|
|
regGDS_GWS_RESET0_BASE_IDX = 0 # macro
|
|
regGDS_GWS_RESET1 = 0x20e5 # macro
|
|
regGDS_GWS_RESET1_BASE_IDX = 0 # macro
|
|
regGDS_GWS_RESOURCE_RESET = 0x20e6 # macro
|
|
regGDS_GWS_RESOURCE_RESET_BASE_IDX = 0 # macro
|
|
regGDS_COMPUTE_MAX_WAVE_ID = 0x20e8 # macro
|
|
regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX = 0 # macro
|
|
regGDS_OA_RESET_MASK = 0x20e9 # macro
|
|
regGDS_OA_RESET_MASK_BASE_IDX = 0 # macro
|
|
regGDS_OA_RESET = 0x20ea # macro
|
|
regGDS_OA_RESET_BASE_IDX = 0 # macro
|
|
regGDS_CS_CTXSW_STATUS = 0x20ed # macro
|
|
regGDS_CS_CTXSW_STATUS_BASE_IDX = 0 # macro
|
|
regGDS_CS_CTXSW_CNT0 = 0x20ee # macro
|
|
regGDS_CS_CTXSW_CNT0_BASE_IDX = 0 # macro
|
|
regGDS_CS_CTXSW_CNT1 = 0x20ef # macro
|
|
regGDS_CS_CTXSW_CNT1_BASE_IDX = 0 # macro
|
|
regGDS_CS_CTXSW_CNT2 = 0x20f0 # macro
|
|
regGDS_CS_CTXSW_CNT2_BASE_IDX = 0 # macro
|
|
regGDS_CS_CTXSW_CNT3 = 0x20f1 # macro
|
|
regGDS_CS_CTXSW_CNT3_BASE_IDX = 0 # macro
|
|
regGDS_GFX_CTXSW_STATUS = 0x20f2 # macro
|
|
regGDS_GFX_CTXSW_STATUS_BASE_IDX = 0 # macro
|
|
regGDS_PS_CTXSW_CNT0 = 0x20f7 # macro
|
|
regGDS_PS_CTXSW_CNT0_BASE_IDX = 0 # macro
|
|
regGDS_PS_CTXSW_CNT1 = 0x20f8 # macro
|
|
regGDS_PS_CTXSW_CNT1_BASE_IDX = 0 # macro
|
|
regGDS_PS_CTXSW_CNT2 = 0x20f9 # macro
|
|
regGDS_PS_CTXSW_CNT2_BASE_IDX = 0 # macro
|
|
regGDS_PS_CTXSW_CNT3 = 0x20fa # macro
|
|
regGDS_PS_CTXSW_CNT3_BASE_IDX = 0 # macro
|
|
regGDS_PS_CTXSW_IDX = 0x20fb # macro
|
|
regGDS_PS_CTXSW_IDX_BASE_IDX = 0 # macro
|
|
regGDS_GS_CTXSW_CNT0 = 0x2117 # macro
|
|
regGDS_GS_CTXSW_CNT0_BASE_IDX = 0 # macro
|
|
regGDS_GS_CTXSW_CNT1 = 0x2118 # macro
|
|
regGDS_GS_CTXSW_CNT1_BASE_IDX = 0 # macro
|
|
regGDS_GS_CTXSW_CNT2 = 0x2119 # macro
|
|
regGDS_GS_CTXSW_CNT2_BASE_IDX = 0 # macro
|
|
regGDS_GS_CTXSW_CNT3 = 0x211a # macro
|
|
regGDS_GS_CTXSW_CNT3_BASE_IDX = 0 # macro
|
|
regGDS_MEMORY_CLEAN = 0x211f # macro
|
|
regGDS_MEMORY_CLEAN_BASE_IDX = 0 # macro
|
|
regGUS_IO_RD_COMBINE_FLUSH = 0x2c00 # macro
|
|
regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_COMBINE_FLUSH = 0x2c01 # macro
|
|
regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_AGE_RATE = 0x2c02 # macro
|
|
regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_AGE_RATE = 0x2c03 # macro
|
|
regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_AGE_COEFF = 0x2c04 # macro
|
|
regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_AGE_COEFF = 0x2c05 # macro
|
|
regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_QUEUING = 0x2c06 # macro
|
|
regGUS_IO_RD_PRI_QUEUING_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_QUEUING = 0x2c07 # macro
|
|
regGUS_IO_WR_PRI_QUEUING_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_FIXED = 0x2c08 # macro
|
|
regGUS_IO_RD_PRI_FIXED_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_FIXED = 0x2c09 # macro
|
|
regGUS_IO_WR_PRI_FIXED_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_URGENCY_COEFF = 0x2c0a # macro
|
|
regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_URGENCY_COEFF = 0x2c0b # macro
|
|
regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_URGENCY_MODE = 0x2c0c # macro
|
|
regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_URGENCY_MODE = 0x2c0d # macro
|
|
regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_QUANT_PRI1 = 0x2c0e # macro
|
|
regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_QUANT_PRI2 = 0x2c0f # macro
|
|
regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_QUANT_PRI3 = 0x2c10 # macro
|
|
regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_QUANT_PRI4 = 0x2c11 # macro
|
|
regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_QUANT_PRI1 = 0x2c12 # macro
|
|
regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_QUANT_PRI2 = 0x2c13 # macro
|
|
regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_QUANT_PRI3 = 0x2c14 # macro
|
|
regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_QUANT_PRI4 = 0x2c15 # macro
|
|
regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_QUANT1_PRI1 = 0x2c16 # macro
|
|
regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_QUANT1_PRI2 = 0x2c17 # macro
|
|
regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_QUANT1_PRI3 = 0x2c18 # macro
|
|
regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro
|
|
regGUS_IO_RD_PRI_QUANT1_PRI4 = 0x2c19 # macro
|
|
regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_QUANT1_PRI1 = 0x2c1a # macro
|
|
regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_QUANT1_PRI2 = 0x2c1b # macro
|
|
regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_QUANT1_PRI3 = 0x2c1c # macro
|
|
regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro
|
|
regGUS_IO_WR_PRI_QUANT1_PRI4 = 0x2c1d # macro
|
|
regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_COMBINE_FLUSH = 0x2c1e # macro
|
|
regGUS_DRAM_COMBINE_FLUSH_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_COMBINE_RD_WR_EN = 0x2c1f # macro
|
|
regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_AGE_RATE = 0x2c20 # macro
|
|
regGUS_DRAM_PRI_AGE_RATE_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_AGE_COEFF = 0x2c21 # macro
|
|
regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_QUEUING = 0x2c22 # macro
|
|
regGUS_DRAM_PRI_QUEUING_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_FIXED = 0x2c23 # macro
|
|
regGUS_DRAM_PRI_FIXED_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_URGENCY_COEFF = 0x2c24 # macro
|
|
regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_URGENCY_MODE = 0x2c25 # macro
|
|
regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_QUANT_PRI1 = 0x2c26 # macro
|
|
regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_QUANT_PRI2 = 0x2c27 # macro
|
|
regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_QUANT_PRI3 = 0x2c28 # macro
|
|
regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_QUANT_PRI4 = 0x2c29 # macro
|
|
regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_QUANT_PRI5 = 0x2c2a # macro
|
|
regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_QUANT1_PRI1 = 0x2c2b # macro
|
|
regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_QUANT1_PRI2 = 0x2c2c # macro
|
|
regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_QUANT1_PRI3 = 0x2c2d # macro
|
|
regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_QUANT1_PRI4 = 0x2c2e # macro
|
|
regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_PRI_QUANT1_PRI5 = 0x2c2f # macro
|
|
regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX = 1 # macro
|
|
regGUS_IO_GROUP_BURST = 0x2c30 # macro
|
|
regGUS_IO_GROUP_BURST_BASE_IDX = 1 # macro
|
|
regGUS_DRAM_GROUP_BURST = 0x2c31 # macro
|
|
regGUS_DRAM_GROUP_BURST_BASE_IDX = 1 # macro
|
|
regGUS_SDP_ARB_FINAL = 0x2c32 # macro
|
|
regGUS_SDP_ARB_FINAL_BASE_IDX = 1 # macro
|
|
regGUS_SDP_QOS_VC_PRIORITY = 0x2c33 # macro
|
|
regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX = 1 # macro
|
|
regGUS_SDP_CREDITS = 0x2c34 # macro
|
|
regGUS_SDP_CREDITS_BASE_IDX = 1 # macro
|
|
regGUS_SDP_TAG_RESERVE0 = 0x2c35 # macro
|
|
regGUS_SDP_TAG_RESERVE0_BASE_IDX = 1 # macro
|
|
regGUS_SDP_TAG_RESERVE1 = 0x2c36 # macro
|
|
regGUS_SDP_TAG_RESERVE1_BASE_IDX = 1 # macro
|
|
regGUS_SDP_VCC_RESERVE0 = 0x2c37 # macro
|
|
regGUS_SDP_VCC_RESERVE0_BASE_IDX = 1 # macro
|
|
regGUS_SDP_VCC_RESERVE1 = 0x2c38 # macro
|
|
regGUS_SDP_VCC_RESERVE1_BASE_IDX = 1 # macro
|
|
regGUS_SDP_VCD_RESERVE0 = 0x2c39 # macro
|
|
regGUS_SDP_VCD_RESERVE0_BASE_IDX = 1 # macro
|
|
regGUS_SDP_VCD_RESERVE1 = 0x2c3a # macro
|
|
regGUS_SDP_VCD_RESERVE1_BASE_IDX = 1 # macro
|
|
regGUS_SDP_REQ_CNTL = 0x2c3b # macro
|
|
regGUS_SDP_REQ_CNTL_BASE_IDX = 1 # macro
|
|
regGUS_MISC = 0x2c3c # macro
|
|
regGUS_MISC_BASE_IDX = 1 # macro
|
|
regGUS_LATENCY_SAMPLING = 0x2c3d # macro
|
|
regGUS_LATENCY_SAMPLING_BASE_IDX = 1 # macro
|
|
regGUS_ERR_STATUS = 0x2c3e # macro
|
|
regGUS_ERR_STATUS_BASE_IDX = 1 # macro
|
|
regGUS_MISC2 = 0x2c3f # macro
|
|
regGUS_MISC2_BASE_IDX = 1 # macro
|
|
regGUS_SDP_ENABLE = 0x2c45 # macro
|
|
regGUS_SDP_ENABLE_BASE_IDX = 1 # macro
|
|
regGUS_L1_CH0_CMD_IN = 0x2c46 # macro
|
|
regGUS_L1_CH0_CMD_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_CH0_CMD_OUT = 0x2c47 # macro
|
|
regGUS_L1_CH0_CMD_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_CH0_DATA_IN = 0x2c48 # macro
|
|
regGUS_L1_CH0_DATA_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_CH0_DATA_OUT = 0x2c49 # macro
|
|
regGUS_L1_CH0_DATA_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_CH0_DATA_U_IN = 0x2c4a # macro
|
|
regGUS_L1_CH0_DATA_U_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_CH0_DATA_U_OUT = 0x2c4b # macro
|
|
regGUS_L1_CH0_DATA_U_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_CH1_CMD_IN = 0x2c4c # macro
|
|
regGUS_L1_CH1_CMD_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_CH1_CMD_OUT = 0x2c4d # macro
|
|
regGUS_L1_CH1_CMD_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_CH1_DATA_IN = 0x2c4e # macro
|
|
regGUS_L1_CH1_DATA_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_CH1_DATA_OUT = 0x2c4f # macro
|
|
regGUS_L1_CH1_DATA_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_CH1_DATA_U_IN = 0x2c50 # macro
|
|
regGUS_L1_CH1_DATA_U_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_CH1_DATA_U_OUT = 0x2c51 # macro
|
|
regGUS_L1_CH1_DATA_U_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA0_CMD_IN = 0x2c52 # macro
|
|
regGUS_L1_SA0_CMD_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA0_CMD_OUT = 0x2c53 # macro
|
|
regGUS_L1_SA0_CMD_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA0_DATA_IN = 0x2c54 # macro
|
|
regGUS_L1_SA0_DATA_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA0_DATA_OUT = 0x2c55 # macro
|
|
regGUS_L1_SA0_DATA_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA0_DATA_U_IN = 0x2c56 # macro
|
|
regGUS_L1_SA0_DATA_U_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA0_DATA_U_OUT = 0x2c57 # macro
|
|
regGUS_L1_SA0_DATA_U_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA1_CMD_IN = 0x2c58 # macro
|
|
regGUS_L1_SA1_CMD_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA1_CMD_OUT = 0x2c59 # macro
|
|
regGUS_L1_SA1_CMD_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA1_DATA_IN = 0x2c5a # macro
|
|
regGUS_L1_SA1_DATA_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA1_DATA_OUT = 0x2c5b # macro
|
|
regGUS_L1_SA1_DATA_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA1_DATA_U_IN = 0x2c5c # macro
|
|
regGUS_L1_SA1_DATA_U_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA1_DATA_U_OUT = 0x2c5d # macro
|
|
regGUS_L1_SA1_DATA_U_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA2_CMD_IN = 0x2c5e # macro
|
|
regGUS_L1_SA2_CMD_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA2_CMD_OUT = 0x2c5f # macro
|
|
regGUS_L1_SA2_CMD_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA2_DATA_IN = 0x2c60 # macro
|
|
regGUS_L1_SA2_DATA_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA2_DATA_OUT = 0x2c61 # macro
|
|
regGUS_L1_SA2_DATA_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA2_DATA_U_IN = 0x2c62 # macro
|
|
regGUS_L1_SA2_DATA_U_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA2_DATA_U_OUT = 0x2c63 # macro
|
|
regGUS_L1_SA2_DATA_U_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA3_CMD_IN = 0x2c64 # macro
|
|
regGUS_L1_SA3_CMD_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA3_CMD_OUT = 0x2c65 # macro
|
|
regGUS_L1_SA3_CMD_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA3_DATA_IN = 0x2c66 # macro
|
|
regGUS_L1_SA3_DATA_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA3_DATA_OUT = 0x2c67 # macro
|
|
regGUS_L1_SA3_DATA_OUT_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA3_DATA_U_IN = 0x2c68 # macro
|
|
regGUS_L1_SA3_DATA_U_IN_BASE_IDX = 1 # macro
|
|
regGUS_L1_SA3_DATA_U_OUT = 0x2c69 # macro
|
|
regGUS_L1_SA3_DATA_U_OUT_BASE_IDX = 1 # macro
|
|
regGUS_MISC3 = 0x2c6a # macro
|
|
regGUS_MISC3_BASE_IDX = 1 # macro
|
|
regGUS_WRRSP_FIFO_CNTL = 0x2c6b # macro
|
|
regGUS_WRRSP_FIFO_CNTL_BASE_IDX = 1 # macro
|
|
regDB_RENDER_CONTROL = 0x0000 # macro
|
|
regDB_RENDER_CONTROL_BASE_IDX = 1 # macro
|
|
regDB_COUNT_CONTROL = 0x0001 # macro
|
|
regDB_COUNT_CONTROL_BASE_IDX = 1 # macro
|
|
regDB_DEPTH_VIEW = 0x0002 # macro
|
|
regDB_DEPTH_VIEW_BASE_IDX = 1 # macro
|
|
regDB_RENDER_OVERRIDE = 0x0003 # macro
|
|
regDB_RENDER_OVERRIDE_BASE_IDX = 1 # macro
|
|
regDB_RENDER_OVERRIDE2 = 0x0004 # macro
|
|
regDB_RENDER_OVERRIDE2_BASE_IDX = 1 # macro
|
|
regDB_HTILE_DATA_BASE = 0x0005 # macro
|
|
regDB_HTILE_DATA_BASE_BASE_IDX = 1 # macro
|
|
regDB_DEPTH_SIZE_XY = 0x0007 # macro
|
|
regDB_DEPTH_SIZE_XY_BASE_IDX = 1 # macro
|
|
regDB_DEPTH_BOUNDS_MIN = 0x0008 # macro
|
|
regDB_DEPTH_BOUNDS_MIN_BASE_IDX = 1 # macro
|
|
regDB_DEPTH_BOUNDS_MAX = 0x0009 # macro
|
|
regDB_DEPTH_BOUNDS_MAX_BASE_IDX = 1 # macro
|
|
regDB_STENCIL_CLEAR = 0x000a # macro
|
|
regDB_STENCIL_CLEAR_BASE_IDX = 1 # macro
|
|
regDB_DEPTH_CLEAR = 0x000b # macro
|
|
regDB_DEPTH_CLEAR_BASE_IDX = 1 # macro
|
|
regPA_SC_SCREEN_SCISSOR_TL = 0x000c # macro
|
|
regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_SCREEN_SCISSOR_BR = 0x000d # macro
|
|
regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX = 1 # macro
|
|
regDB_RESERVED_REG_2 = 0x000f # macro
|
|
regDB_RESERVED_REG_2_BASE_IDX = 1 # macro
|
|
regDB_Z_INFO = 0x0010 # macro
|
|
regDB_Z_INFO_BASE_IDX = 1 # macro
|
|
regDB_STENCIL_INFO = 0x0011 # macro
|
|
regDB_STENCIL_INFO_BASE_IDX = 1 # macro
|
|
regDB_Z_READ_BASE = 0x0012 # macro
|
|
regDB_Z_READ_BASE_BASE_IDX = 1 # macro
|
|
regDB_STENCIL_READ_BASE = 0x0013 # macro
|
|
regDB_STENCIL_READ_BASE_BASE_IDX = 1 # macro
|
|
regDB_Z_WRITE_BASE = 0x0014 # macro
|
|
regDB_Z_WRITE_BASE_BASE_IDX = 1 # macro
|
|
regDB_STENCIL_WRITE_BASE = 0x0015 # macro
|
|
regDB_STENCIL_WRITE_BASE_BASE_IDX = 1 # macro
|
|
regDB_RESERVED_REG_1 = 0x0016 # macro
|
|
regDB_RESERVED_REG_1_BASE_IDX = 1 # macro
|
|
regDB_RESERVED_REG_3 = 0x0017 # macro
|
|
regDB_RESERVED_REG_3_BASE_IDX = 1 # macro
|
|
regDB_Z_READ_BASE_HI = 0x001a # macro
|
|
regDB_Z_READ_BASE_HI_BASE_IDX = 1 # macro
|
|
regDB_STENCIL_READ_BASE_HI = 0x001b # macro
|
|
regDB_STENCIL_READ_BASE_HI_BASE_IDX = 1 # macro
|
|
regDB_Z_WRITE_BASE_HI = 0x001c # macro
|
|
regDB_Z_WRITE_BASE_HI_BASE_IDX = 1 # macro
|
|
regDB_STENCIL_WRITE_BASE_HI = 0x001d # macro
|
|
regDB_STENCIL_WRITE_BASE_HI_BASE_IDX = 1 # macro
|
|
regDB_HTILE_DATA_BASE_HI = 0x001e # macro
|
|
regDB_HTILE_DATA_BASE_HI_BASE_IDX = 1 # macro
|
|
regDB_RMI_L2_CACHE_CONTROL = 0x001f # macro
|
|
regDB_RMI_L2_CACHE_CONTROL_BASE_IDX = 1 # macro
|
|
regTA_BC_BASE_ADDR = 0x0020 # macro
|
|
regTA_BC_BASE_ADDR_BASE_IDX = 1 # macro
|
|
regTA_BC_BASE_ADDR_HI = 0x0021 # macro
|
|
regTA_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCOHER_DEST_BASE_HI_0 = 0x007a # macro
|
|
regCOHER_DEST_BASE_HI_0_BASE_IDX = 1 # macro
|
|
regCOHER_DEST_BASE_HI_1 = 0x007b # macro
|
|
regCOHER_DEST_BASE_HI_1_BASE_IDX = 1 # macro
|
|
regCOHER_DEST_BASE_HI_2 = 0x007c # macro
|
|
regCOHER_DEST_BASE_HI_2_BASE_IDX = 1 # macro
|
|
regCOHER_DEST_BASE_HI_3 = 0x007d # macro
|
|
regCOHER_DEST_BASE_HI_3_BASE_IDX = 1 # macro
|
|
regCOHER_DEST_BASE_2 = 0x007e # macro
|
|
regCOHER_DEST_BASE_2_BASE_IDX = 1 # macro
|
|
regCOHER_DEST_BASE_3 = 0x007f # macro
|
|
regCOHER_DEST_BASE_3_BASE_IDX = 1 # macro
|
|
regPA_SC_WINDOW_OFFSET = 0x0080 # macro
|
|
regPA_SC_WINDOW_OFFSET_BASE_IDX = 1 # macro
|
|
regPA_SC_WINDOW_SCISSOR_TL = 0x0081 # macro
|
|
regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_WINDOW_SCISSOR_BR = 0x0082 # macro
|
|
regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_CLIPRECT_RULE = 0x0083 # macro
|
|
regPA_SC_CLIPRECT_RULE_BASE_IDX = 1 # macro
|
|
regPA_SC_CLIPRECT_0_TL = 0x0084 # macro
|
|
regPA_SC_CLIPRECT_0_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_CLIPRECT_0_BR = 0x0085 # macro
|
|
regPA_SC_CLIPRECT_0_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_CLIPRECT_1_TL = 0x0086 # macro
|
|
regPA_SC_CLIPRECT_1_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_CLIPRECT_1_BR = 0x0087 # macro
|
|
regPA_SC_CLIPRECT_1_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_CLIPRECT_2_TL = 0x0088 # macro
|
|
regPA_SC_CLIPRECT_2_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_CLIPRECT_2_BR = 0x0089 # macro
|
|
regPA_SC_CLIPRECT_2_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_CLIPRECT_3_TL = 0x008a # macro
|
|
regPA_SC_CLIPRECT_3_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_CLIPRECT_3_BR = 0x008b # macro
|
|
regPA_SC_CLIPRECT_3_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_EDGERULE = 0x008c # macro
|
|
regPA_SC_EDGERULE_BASE_IDX = 1 # macro
|
|
regPA_SU_HARDWARE_SCREEN_OFFSET = 0x008d # macro
|
|
regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX = 1 # macro
|
|
regCB_TARGET_MASK = 0x008e # macro
|
|
regCB_TARGET_MASK_BASE_IDX = 1 # macro
|
|
regCB_SHADER_MASK = 0x008f # macro
|
|
regCB_SHADER_MASK_BASE_IDX = 1 # macro
|
|
regPA_SC_GENERIC_SCISSOR_TL = 0x0090 # macro
|
|
regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_GENERIC_SCISSOR_BR = 0x0091 # macro
|
|
regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX = 1 # macro
|
|
regCOHER_DEST_BASE_0 = 0x0092 # macro
|
|
regCOHER_DEST_BASE_0_BASE_IDX = 1 # macro
|
|
regCOHER_DEST_BASE_1 = 0x0093 # macro
|
|
regCOHER_DEST_BASE_1_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_0_TL = 0x0094 # macro
|
|
regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_0_BR = 0x0095 # macro
|
|
regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_1_TL = 0x0096 # macro
|
|
regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_1_BR = 0x0097 # macro
|
|
regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_2_TL = 0x0098 # macro
|
|
regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_2_BR = 0x0099 # macro
|
|
regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_3_TL = 0x009a # macro
|
|
regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_3_BR = 0x009b # macro
|
|
regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_4_TL = 0x009c # macro
|
|
regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_4_BR = 0x009d # macro
|
|
regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_5_TL = 0x009e # macro
|
|
regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_5_BR = 0x009f # macro
|
|
regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_6_TL = 0x00a0 # macro
|
|
regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_6_BR = 0x00a1 # macro
|
|
regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_7_TL = 0x00a2 # macro
|
|
regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_7_BR = 0x00a3 # macro
|
|
regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_8_TL = 0x00a4 # macro
|
|
regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_8_BR = 0x00a5 # macro
|
|
regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_9_TL = 0x00a6 # macro
|
|
regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_9_BR = 0x00a7 # macro
|
|
regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_10_TL = 0x00a8 # macro
|
|
regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_10_BR = 0x00a9 # macro
|
|
regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_11_TL = 0x00aa # macro
|
|
regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_11_BR = 0x00ab # macro
|
|
regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_12_TL = 0x00ac # macro
|
|
regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_12_BR = 0x00ad # macro
|
|
regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_13_TL = 0x00ae # macro
|
|
regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_13_BR = 0x00af # macro
|
|
regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_14_TL = 0x00b0 # macro
|
|
regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_14_BR = 0x00b1 # macro
|
|
regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_15_TL = 0x00b2 # macro
|
|
regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_SCISSOR_15_BR = 0x00b3 # macro
|
|
regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_0 = 0x00b4 # macro
|
|
regPA_SC_VPORT_ZMIN_0_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_0 = 0x00b5 # macro
|
|
regPA_SC_VPORT_ZMAX_0_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_1 = 0x00b6 # macro
|
|
regPA_SC_VPORT_ZMIN_1_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_1 = 0x00b7 # macro
|
|
regPA_SC_VPORT_ZMAX_1_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_2 = 0x00b8 # macro
|
|
regPA_SC_VPORT_ZMIN_2_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_2 = 0x00b9 # macro
|
|
regPA_SC_VPORT_ZMAX_2_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_3 = 0x00ba # macro
|
|
regPA_SC_VPORT_ZMIN_3_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_3 = 0x00bb # macro
|
|
regPA_SC_VPORT_ZMAX_3_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_4 = 0x00bc # macro
|
|
regPA_SC_VPORT_ZMIN_4_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_4 = 0x00bd # macro
|
|
regPA_SC_VPORT_ZMAX_4_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_5 = 0x00be # macro
|
|
regPA_SC_VPORT_ZMIN_5_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_5 = 0x00bf # macro
|
|
regPA_SC_VPORT_ZMAX_5_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_6 = 0x00c0 # macro
|
|
regPA_SC_VPORT_ZMIN_6_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_6 = 0x00c1 # macro
|
|
regPA_SC_VPORT_ZMAX_6_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_7 = 0x00c2 # macro
|
|
regPA_SC_VPORT_ZMIN_7_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_7 = 0x00c3 # macro
|
|
regPA_SC_VPORT_ZMAX_7_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_8 = 0x00c4 # macro
|
|
regPA_SC_VPORT_ZMIN_8_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_8 = 0x00c5 # macro
|
|
regPA_SC_VPORT_ZMAX_8_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_9 = 0x00c6 # macro
|
|
regPA_SC_VPORT_ZMIN_9_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_9 = 0x00c7 # macro
|
|
regPA_SC_VPORT_ZMAX_9_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_10 = 0x00c8 # macro
|
|
regPA_SC_VPORT_ZMIN_10_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_10 = 0x00c9 # macro
|
|
regPA_SC_VPORT_ZMAX_10_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_11 = 0x00ca # macro
|
|
regPA_SC_VPORT_ZMIN_11_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_11 = 0x00cb # macro
|
|
regPA_SC_VPORT_ZMAX_11_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_12 = 0x00cc # macro
|
|
regPA_SC_VPORT_ZMIN_12_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_12 = 0x00cd # macro
|
|
regPA_SC_VPORT_ZMAX_12_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_13 = 0x00ce # macro
|
|
regPA_SC_VPORT_ZMIN_13_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_13 = 0x00cf # macro
|
|
regPA_SC_VPORT_ZMAX_13_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_14 = 0x00d0 # macro
|
|
regPA_SC_VPORT_ZMIN_14_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_14 = 0x00d1 # macro
|
|
regPA_SC_VPORT_ZMAX_14_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMIN_15 = 0x00d2 # macro
|
|
regPA_SC_VPORT_ZMIN_15_BASE_IDX = 1 # macro
|
|
regPA_SC_VPORT_ZMAX_15 = 0x00d3 # macro
|
|
regPA_SC_VPORT_ZMAX_15_BASE_IDX = 1 # macro
|
|
regPA_SC_RASTER_CONFIG = 0x00d4 # macro
|
|
regPA_SC_RASTER_CONFIG_BASE_IDX = 1 # macro
|
|
regPA_SC_RASTER_CONFIG_1 = 0x00d5 # macro
|
|
regPA_SC_RASTER_CONFIG_1_BASE_IDX = 1 # macro
|
|
regPA_SC_SCREEN_EXTENT_CONTROL = 0x00d6 # macro
|
|
regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX = 1 # macro
|
|
regPA_SC_TILE_STEERING_OVERRIDE = 0x00d7 # macro
|
|
regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX = 1 # macro
|
|
regCP_PERFMON_CNTX_CNTL = 0x00d8 # macro
|
|
regCP_PERFMON_CNTX_CNTL_BASE_IDX = 1 # macro
|
|
regCP_PIPEID = 0x00d9 # macro
|
|
regCP_PIPEID_BASE_IDX = 1 # macro
|
|
regCP_RINGID = 0x00d9 # macro
|
|
regCP_RINGID_BASE_IDX = 1 # macro
|
|
regCP_VMID = 0x00da # macro
|
|
regCP_VMID_BASE_IDX = 1 # macro
|
|
regCONTEXT_RESERVED_REG0 = 0x00db # macro
|
|
regCONTEXT_RESERVED_REG0_BASE_IDX = 1 # macro
|
|
regCONTEXT_RESERVED_REG1 = 0x00dc # macro
|
|
regCONTEXT_RESERVED_REG1_BASE_IDX = 1 # macro
|
|
regPA_SC_VRS_OVERRIDE_CNTL = 0x00f4 # macro
|
|
regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SC_VRS_RATE_FEEDBACK_BASE = 0x00f5 # macro
|
|
regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX = 1 # macro
|
|
regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT = 0x00f6 # macro
|
|
regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX = 1 # macro
|
|
regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY = 0x00f7 # macro
|
|
regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX = 1 # macro
|
|
regPA_SC_VRS_RATE_CACHE_CNTL = 0x00f9 # macro
|
|
regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SC_VRS_RATE_BASE = 0x00fc # macro
|
|
regPA_SC_VRS_RATE_BASE_BASE_IDX = 1 # macro
|
|
regPA_SC_VRS_RATE_BASE_EXT = 0x00fd # macro
|
|
regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX = 1 # macro
|
|
regPA_SC_VRS_RATE_SIZE_XY = 0x00fe # macro
|
|
regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX = 1 # macro
|
|
regVGT_MULTI_PRIM_IB_RESET_INDX = 0x0103 # macro
|
|
regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX = 1 # macro
|
|
regCB_RMI_GL2_CACHE_CONTROL = 0x0104 # macro
|
|
regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_BLEND_RED = 0x0105 # macro
|
|
regCB_BLEND_RED_BASE_IDX = 1 # macro
|
|
regCB_BLEND_GREEN = 0x0106 # macro
|
|
regCB_BLEND_GREEN_BASE_IDX = 1 # macro
|
|
regCB_BLEND_BLUE = 0x0107 # macro
|
|
regCB_BLEND_BLUE_BASE_IDX = 1 # macro
|
|
regCB_BLEND_ALPHA = 0x0108 # macro
|
|
regCB_BLEND_ALPHA_BASE_IDX = 1 # macro
|
|
regCB_FDCC_CONTROL = 0x0109 # macro
|
|
regCB_FDCC_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_COVERAGE_OUT_CONTROL = 0x010a # macro
|
|
regCB_COVERAGE_OUT_CONTROL_BASE_IDX = 1 # macro
|
|
regDB_STENCIL_CONTROL = 0x010b # macro
|
|
regDB_STENCIL_CONTROL_BASE_IDX = 1 # macro
|
|
regDB_STENCILREFMASK = 0x010c # macro
|
|
regDB_STENCILREFMASK_BASE_IDX = 1 # macro
|
|
regDB_STENCILREFMASK_BF = 0x010d # macro
|
|
regDB_STENCILREFMASK_BF_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE = 0x010f # macro
|
|
regPA_CL_VPORT_XSCALE_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET = 0x0110 # macro
|
|
regPA_CL_VPORT_XOFFSET_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE = 0x0111 # macro
|
|
regPA_CL_VPORT_YSCALE_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET = 0x0112 # macro
|
|
regPA_CL_VPORT_YOFFSET_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE = 0x0113 # macro
|
|
regPA_CL_VPORT_ZSCALE_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET = 0x0114 # macro
|
|
regPA_CL_VPORT_ZOFFSET_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_1 = 0x0115 # macro
|
|
regPA_CL_VPORT_XSCALE_1_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_1 = 0x0116 # macro
|
|
regPA_CL_VPORT_XOFFSET_1_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_1 = 0x0117 # macro
|
|
regPA_CL_VPORT_YSCALE_1_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_1 = 0x0118 # macro
|
|
regPA_CL_VPORT_YOFFSET_1_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_1 = 0x0119 # macro
|
|
regPA_CL_VPORT_ZSCALE_1_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_1 = 0x011a # macro
|
|
regPA_CL_VPORT_ZOFFSET_1_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_2 = 0x011b # macro
|
|
regPA_CL_VPORT_XSCALE_2_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_2 = 0x011c # macro
|
|
regPA_CL_VPORT_XOFFSET_2_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_2 = 0x011d # macro
|
|
regPA_CL_VPORT_YSCALE_2_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_2 = 0x011e # macro
|
|
regPA_CL_VPORT_YOFFSET_2_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_2 = 0x011f # macro
|
|
regPA_CL_VPORT_ZSCALE_2_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_2 = 0x0120 # macro
|
|
regPA_CL_VPORT_ZOFFSET_2_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_3 = 0x0121 # macro
|
|
regPA_CL_VPORT_XSCALE_3_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_3 = 0x0122 # macro
|
|
regPA_CL_VPORT_XOFFSET_3_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_3 = 0x0123 # macro
|
|
regPA_CL_VPORT_YSCALE_3_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_3 = 0x0124 # macro
|
|
regPA_CL_VPORT_YOFFSET_3_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_3 = 0x0125 # macro
|
|
regPA_CL_VPORT_ZSCALE_3_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_3 = 0x0126 # macro
|
|
regPA_CL_VPORT_ZOFFSET_3_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_4 = 0x0127 # macro
|
|
regPA_CL_VPORT_XSCALE_4_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_4 = 0x0128 # macro
|
|
regPA_CL_VPORT_XOFFSET_4_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_4 = 0x0129 # macro
|
|
regPA_CL_VPORT_YSCALE_4_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_4 = 0x012a # macro
|
|
regPA_CL_VPORT_YOFFSET_4_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_4 = 0x012b # macro
|
|
regPA_CL_VPORT_ZSCALE_4_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_4 = 0x012c # macro
|
|
regPA_CL_VPORT_ZOFFSET_4_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_5 = 0x012d # macro
|
|
regPA_CL_VPORT_XSCALE_5_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_5 = 0x012e # macro
|
|
regPA_CL_VPORT_XOFFSET_5_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_5 = 0x012f # macro
|
|
regPA_CL_VPORT_YSCALE_5_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_5 = 0x0130 # macro
|
|
regPA_CL_VPORT_YOFFSET_5_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_5 = 0x0131 # macro
|
|
regPA_CL_VPORT_ZSCALE_5_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_5 = 0x0132 # macro
|
|
regPA_CL_VPORT_ZOFFSET_5_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_6 = 0x0133 # macro
|
|
regPA_CL_VPORT_XSCALE_6_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_6 = 0x0134 # macro
|
|
regPA_CL_VPORT_XOFFSET_6_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_6 = 0x0135 # macro
|
|
regPA_CL_VPORT_YSCALE_6_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_6 = 0x0136 # macro
|
|
regPA_CL_VPORT_YOFFSET_6_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_6 = 0x0137 # macro
|
|
regPA_CL_VPORT_ZSCALE_6_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_6 = 0x0138 # macro
|
|
regPA_CL_VPORT_ZOFFSET_6_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_7 = 0x0139 # macro
|
|
regPA_CL_VPORT_XSCALE_7_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_7 = 0x013a # macro
|
|
regPA_CL_VPORT_XOFFSET_7_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_7 = 0x013b # macro
|
|
regPA_CL_VPORT_YSCALE_7_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_7 = 0x013c # macro
|
|
regPA_CL_VPORT_YOFFSET_7_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_7 = 0x013d # macro
|
|
regPA_CL_VPORT_ZSCALE_7_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_7 = 0x013e # macro
|
|
regPA_CL_VPORT_ZOFFSET_7_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_8 = 0x013f # macro
|
|
regPA_CL_VPORT_XSCALE_8_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_8 = 0x0140 # macro
|
|
regPA_CL_VPORT_XOFFSET_8_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_8 = 0x0141 # macro
|
|
regPA_CL_VPORT_YSCALE_8_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_8 = 0x0142 # macro
|
|
regPA_CL_VPORT_YOFFSET_8_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_8 = 0x0143 # macro
|
|
regPA_CL_VPORT_ZSCALE_8_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_8 = 0x0144 # macro
|
|
regPA_CL_VPORT_ZOFFSET_8_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_9 = 0x0145 # macro
|
|
regPA_CL_VPORT_XSCALE_9_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_9 = 0x0146 # macro
|
|
regPA_CL_VPORT_XOFFSET_9_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_9 = 0x0147 # macro
|
|
regPA_CL_VPORT_YSCALE_9_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_9 = 0x0148 # macro
|
|
regPA_CL_VPORT_YOFFSET_9_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_9 = 0x0149 # macro
|
|
regPA_CL_VPORT_ZSCALE_9_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_9 = 0x014a # macro
|
|
regPA_CL_VPORT_ZOFFSET_9_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_10 = 0x014b # macro
|
|
regPA_CL_VPORT_XSCALE_10_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_10 = 0x014c # macro
|
|
regPA_CL_VPORT_XOFFSET_10_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_10 = 0x014d # macro
|
|
regPA_CL_VPORT_YSCALE_10_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_10 = 0x014e # macro
|
|
regPA_CL_VPORT_YOFFSET_10_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_10 = 0x014f # macro
|
|
regPA_CL_VPORT_ZSCALE_10_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_10 = 0x0150 # macro
|
|
regPA_CL_VPORT_ZOFFSET_10_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_11 = 0x0151 # macro
|
|
regPA_CL_VPORT_XSCALE_11_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_11 = 0x0152 # macro
|
|
regPA_CL_VPORT_XOFFSET_11_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_11 = 0x0153 # macro
|
|
regPA_CL_VPORT_YSCALE_11_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_11 = 0x0154 # macro
|
|
regPA_CL_VPORT_YOFFSET_11_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_11 = 0x0155 # macro
|
|
regPA_CL_VPORT_ZSCALE_11_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_11 = 0x0156 # macro
|
|
regPA_CL_VPORT_ZOFFSET_11_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_12 = 0x0157 # macro
|
|
regPA_CL_VPORT_XSCALE_12_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_12 = 0x0158 # macro
|
|
regPA_CL_VPORT_XOFFSET_12_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_12 = 0x0159 # macro
|
|
regPA_CL_VPORT_YSCALE_12_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_12 = 0x015a # macro
|
|
regPA_CL_VPORT_YOFFSET_12_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_12 = 0x015b # macro
|
|
regPA_CL_VPORT_ZSCALE_12_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_12 = 0x015c # macro
|
|
regPA_CL_VPORT_ZOFFSET_12_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_13 = 0x015d # macro
|
|
regPA_CL_VPORT_XSCALE_13_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_13 = 0x015e # macro
|
|
regPA_CL_VPORT_XOFFSET_13_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_13 = 0x015f # macro
|
|
regPA_CL_VPORT_YSCALE_13_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_13 = 0x0160 # macro
|
|
regPA_CL_VPORT_YOFFSET_13_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_13 = 0x0161 # macro
|
|
regPA_CL_VPORT_ZSCALE_13_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_13 = 0x0162 # macro
|
|
regPA_CL_VPORT_ZOFFSET_13_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_14 = 0x0163 # macro
|
|
regPA_CL_VPORT_XSCALE_14_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_14 = 0x0164 # macro
|
|
regPA_CL_VPORT_XOFFSET_14_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_14 = 0x0165 # macro
|
|
regPA_CL_VPORT_YSCALE_14_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_14 = 0x0166 # macro
|
|
regPA_CL_VPORT_YOFFSET_14_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_14 = 0x0167 # macro
|
|
regPA_CL_VPORT_ZSCALE_14_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_14 = 0x0168 # macro
|
|
regPA_CL_VPORT_ZOFFSET_14_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XSCALE_15 = 0x0169 # macro
|
|
regPA_CL_VPORT_XSCALE_15_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_XOFFSET_15 = 0x016a # macro
|
|
regPA_CL_VPORT_XOFFSET_15_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YSCALE_15 = 0x016b # macro
|
|
regPA_CL_VPORT_YSCALE_15_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_YOFFSET_15 = 0x016c # macro
|
|
regPA_CL_VPORT_YOFFSET_15_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZSCALE_15 = 0x016d # macro
|
|
regPA_CL_VPORT_ZSCALE_15_BASE_IDX = 1 # macro
|
|
regPA_CL_VPORT_ZOFFSET_15 = 0x016e # macro
|
|
regPA_CL_VPORT_ZOFFSET_15_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_0_X = 0x016f # macro
|
|
regPA_CL_UCP_0_X_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_0_Y = 0x0170 # macro
|
|
regPA_CL_UCP_0_Y_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_0_Z = 0x0171 # macro
|
|
regPA_CL_UCP_0_Z_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_0_W = 0x0172 # macro
|
|
regPA_CL_UCP_0_W_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_1_X = 0x0173 # macro
|
|
regPA_CL_UCP_1_X_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_1_Y = 0x0174 # macro
|
|
regPA_CL_UCP_1_Y_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_1_Z = 0x0175 # macro
|
|
regPA_CL_UCP_1_Z_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_1_W = 0x0176 # macro
|
|
regPA_CL_UCP_1_W_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_2_X = 0x0177 # macro
|
|
regPA_CL_UCP_2_X_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_2_Y = 0x0178 # macro
|
|
regPA_CL_UCP_2_Y_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_2_Z = 0x0179 # macro
|
|
regPA_CL_UCP_2_Z_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_2_W = 0x017a # macro
|
|
regPA_CL_UCP_2_W_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_3_X = 0x017b # macro
|
|
regPA_CL_UCP_3_X_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_3_Y = 0x017c # macro
|
|
regPA_CL_UCP_3_Y_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_3_Z = 0x017d # macro
|
|
regPA_CL_UCP_3_Z_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_3_W = 0x017e # macro
|
|
regPA_CL_UCP_3_W_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_4_X = 0x017f # macro
|
|
regPA_CL_UCP_4_X_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_4_Y = 0x0180 # macro
|
|
regPA_CL_UCP_4_Y_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_4_Z = 0x0181 # macro
|
|
regPA_CL_UCP_4_Z_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_4_W = 0x0182 # macro
|
|
regPA_CL_UCP_4_W_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_5_X = 0x0183 # macro
|
|
regPA_CL_UCP_5_X_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_5_Y = 0x0184 # macro
|
|
regPA_CL_UCP_5_Y_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_5_Z = 0x0185 # macro
|
|
regPA_CL_UCP_5_Z_BASE_IDX = 1 # macro
|
|
regPA_CL_UCP_5_W = 0x0186 # macro
|
|
regPA_CL_UCP_5_W_BASE_IDX = 1 # macro
|
|
regPA_CL_PROG_NEAR_CLIP_Z = 0x0187 # macro
|
|
regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX = 1 # macro
|
|
regPA_RATE_CNTL = 0x0188 # macro
|
|
regPA_RATE_CNTL_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_0 = 0x0191 # macro
|
|
regSPI_PS_INPUT_CNTL_0_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_1 = 0x0192 # macro
|
|
regSPI_PS_INPUT_CNTL_1_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_2 = 0x0193 # macro
|
|
regSPI_PS_INPUT_CNTL_2_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_3 = 0x0194 # macro
|
|
regSPI_PS_INPUT_CNTL_3_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_4 = 0x0195 # macro
|
|
regSPI_PS_INPUT_CNTL_4_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_5 = 0x0196 # macro
|
|
regSPI_PS_INPUT_CNTL_5_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_6 = 0x0197 # macro
|
|
regSPI_PS_INPUT_CNTL_6_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_7 = 0x0198 # macro
|
|
regSPI_PS_INPUT_CNTL_7_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_8 = 0x0199 # macro
|
|
regSPI_PS_INPUT_CNTL_8_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_9 = 0x019a # macro
|
|
regSPI_PS_INPUT_CNTL_9_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_10 = 0x019b # macro
|
|
regSPI_PS_INPUT_CNTL_10_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_11 = 0x019c # macro
|
|
regSPI_PS_INPUT_CNTL_11_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_12 = 0x019d # macro
|
|
regSPI_PS_INPUT_CNTL_12_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_13 = 0x019e # macro
|
|
regSPI_PS_INPUT_CNTL_13_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_14 = 0x019f # macro
|
|
regSPI_PS_INPUT_CNTL_14_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_15 = 0x01a0 # macro
|
|
regSPI_PS_INPUT_CNTL_15_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_16 = 0x01a1 # macro
|
|
regSPI_PS_INPUT_CNTL_16_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_17 = 0x01a2 # macro
|
|
regSPI_PS_INPUT_CNTL_17_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_18 = 0x01a3 # macro
|
|
regSPI_PS_INPUT_CNTL_18_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_19 = 0x01a4 # macro
|
|
regSPI_PS_INPUT_CNTL_19_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_20 = 0x01a5 # macro
|
|
regSPI_PS_INPUT_CNTL_20_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_21 = 0x01a6 # macro
|
|
regSPI_PS_INPUT_CNTL_21_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_22 = 0x01a7 # macro
|
|
regSPI_PS_INPUT_CNTL_22_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_23 = 0x01a8 # macro
|
|
regSPI_PS_INPUT_CNTL_23_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_24 = 0x01a9 # macro
|
|
regSPI_PS_INPUT_CNTL_24_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_25 = 0x01aa # macro
|
|
regSPI_PS_INPUT_CNTL_25_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_26 = 0x01ab # macro
|
|
regSPI_PS_INPUT_CNTL_26_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_27 = 0x01ac # macro
|
|
regSPI_PS_INPUT_CNTL_27_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_28 = 0x01ad # macro
|
|
regSPI_PS_INPUT_CNTL_28_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_29 = 0x01ae # macro
|
|
regSPI_PS_INPUT_CNTL_29_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_30 = 0x01af # macro
|
|
regSPI_PS_INPUT_CNTL_30_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_CNTL_31 = 0x01b0 # macro
|
|
regSPI_PS_INPUT_CNTL_31_BASE_IDX = 1 # macro
|
|
regSPI_VS_OUT_CONFIG = 0x01b1 # macro
|
|
regSPI_VS_OUT_CONFIG_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_ENA = 0x01b3 # macro
|
|
regSPI_PS_INPUT_ENA_BASE_IDX = 1 # macro
|
|
regSPI_PS_INPUT_ADDR = 0x01b4 # macro
|
|
regSPI_PS_INPUT_ADDR_BASE_IDX = 1 # macro
|
|
regSPI_INTERP_CONTROL_0 = 0x01b5 # macro
|
|
regSPI_INTERP_CONTROL_0_BASE_IDX = 1 # macro
|
|
regSPI_PS_IN_CONTROL = 0x01b6 # macro
|
|
regSPI_PS_IN_CONTROL_BASE_IDX = 1 # macro
|
|
regSPI_BARYC_CNTL = 0x01b8 # macro
|
|
regSPI_BARYC_CNTL_BASE_IDX = 1 # macro
|
|
regSPI_TMPRING_SIZE = 0x01ba # macro
|
|
regSPI_TMPRING_SIZE_BASE_IDX = 1 # macro
|
|
regSPI_GFX_SCRATCH_BASE_LO = 0x01bb # macro
|
|
regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX = 1 # macro
|
|
regSPI_GFX_SCRATCH_BASE_HI = 0x01bc # macro
|
|
regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX = 1 # macro
|
|
regSPI_SHADER_IDX_FORMAT = 0x01c2 # macro
|
|
regSPI_SHADER_IDX_FORMAT_BASE_IDX = 1 # macro
|
|
regSPI_SHADER_POS_FORMAT = 0x01c3 # macro
|
|
regSPI_SHADER_POS_FORMAT_BASE_IDX = 1 # macro
|
|
regSPI_SHADER_Z_FORMAT = 0x01c4 # macro
|
|
regSPI_SHADER_Z_FORMAT_BASE_IDX = 1 # macro
|
|
regSPI_SHADER_COL_FORMAT = 0x01c5 # macro
|
|
regSPI_SHADER_COL_FORMAT_BASE_IDX = 1 # macro
|
|
regSX_PS_DOWNCONVERT_CONTROL = 0x01d4 # macro
|
|
regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX = 1 # macro
|
|
regSX_PS_DOWNCONVERT = 0x01d5 # macro
|
|
regSX_PS_DOWNCONVERT_BASE_IDX = 1 # macro
|
|
regSX_BLEND_OPT_EPSILON = 0x01d6 # macro
|
|
regSX_BLEND_OPT_EPSILON_BASE_IDX = 1 # macro
|
|
regSX_BLEND_OPT_CONTROL = 0x01d7 # macro
|
|
regSX_BLEND_OPT_CONTROL_BASE_IDX = 1 # macro
|
|
regSX_MRT0_BLEND_OPT = 0x01d8 # macro
|
|
regSX_MRT0_BLEND_OPT_BASE_IDX = 1 # macro
|
|
regSX_MRT1_BLEND_OPT = 0x01d9 # macro
|
|
regSX_MRT1_BLEND_OPT_BASE_IDX = 1 # macro
|
|
regSX_MRT2_BLEND_OPT = 0x01da # macro
|
|
regSX_MRT2_BLEND_OPT_BASE_IDX = 1 # macro
|
|
regSX_MRT3_BLEND_OPT = 0x01db # macro
|
|
regSX_MRT3_BLEND_OPT_BASE_IDX = 1 # macro
|
|
regSX_MRT4_BLEND_OPT = 0x01dc # macro
|
|
regSX_MRT4_BLEND_OPT_BASE_IDX = 1 # macro
|
|
regSX_MRT5_BLEND_OPT = 0x01dd # macro
|
|
regSX_MRT5_BLEND_OPT_BASE_IDX = 1 # macro
|
|
regSX_MRT6_BLEND_OPT = 0x01de # macro
|
|
regSX_MRT6_BLEND_OPT_BASE_IDX = 1 # macro
|
|
regSX_MRT7_BLEND_OPT = 0x01df # macro
|
|
regSX_MRT7_BLEND_OPT_BASE_IDX = 1 # macro
|
|
regCB_BLEND0_CONTROL = 0x01e0 # macro
|
|
regCB_BLEND0_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_BLEND1_CONTROL = 0x01e1 # macro
|
|
regCB_BLEND1_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_BLEND2_CONTROL = 0x01e2 # macro
|
|
regCB_BLEND2_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_BLEND3_CONTROL = 0x01e3 # macro
|
|
regCB_BLEND3_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_BLEND4_CONTROL = 0x01e4 # macro
|
|
regCB_BLEND4_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_BLEND5_CONTROL = 0x01e5 # macro
|
|
regCB_BLEND5_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_BLEND6_CONTROL = 0x01e6 # macro
|
|
regCB_BLEND6_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_BLEND7_CONTROL = 0x01e7 # macro
|
|
regCB_BLEND7_CONTROL_BASE_IDX = 1 # macro
|
|
regGFX_COPY_STATE = 0x01f4 # macro
|
|
regGFX_COPY_STATE_BASE_IDX = 1 # macro
|
|
regPA_CL_POINT_X_RAD = 0x01f5 # macro
|
|
regPA_CL_POINT_X_RAD_BASE_IDX = 1 # macro
|
|
regPA_CL_POINT_Y_RAD = 0x01f6 # macro
|
|
regPA_CL_POINT_Y_RAD_BASE_IDX = 1 # macro
|
|
regPA_CL_POINT_SIZE = 0x01f7 # macro
|
|
regPA_CL_POINT_SIZE_BASE_IDX = 1 # macro
|
|
regPA_CL_POINT_CULL_RAD = 0x01f8 # macro
|
|
regPA_CL_POINT_CULL_RAD_BASE_IDX = 1 # macro
|
|
regVGT_DMA_BASE_HI = 0x01f9 # macro
|
|
regVGT_DMA_BASE_HI_BASE_IDX = 1 # macro
|
|
regVGT_DMA_BASE = 0x01fa # macro
|
|
regVGT_DMA_BASE_BASE_IDX = 1 # macro
|
|
regVGT_DRAW_INITIATOR = 0x01fc # macro
|
|
regVGT_DRAW_INITIATOR_BASE_IDX = 1 # macro
|
|
regVGT_EVENT_ADDRESS_REG = 0x01fe # macro
|
|
regVGT_EVENT_ADDRESS_REG_BASE_IDX = 1 # macro
|
|
regGE_MAX_OUTPUT_PER_SUBGROUP = 0x01ff # macro
|
|
regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX = 1 # macro
|
|
regDB_DEPTH_CONTROL = 0x0200 # macro
|
|
regDB_DEPTH_CONTROL_BASE_IDX = 1 # macro
|
|
regDB_EQAA = 0x0201 # macro
|
|
regDB_EQAA_BASE_IDX = 1 # macro
|
|
regCB_COLOR_CONTROL = 0x0202 # macro
|
|
regCB_COLOR_CONTROL_BASE_IDX = 1 # macro
|
|
regDB_SHADER_CONTROL = 0x0203 # macro
|
|
regDB_SHADER_CONTROL_BASE_IDX = 1 # macro
|
|
regPA_CL_CLIP_CNTL = 0x0204 # macro
|
|
regPA_CL_CLIP_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SU_SC_MODE_CNTL = 0x0205 # macro
|
|
regPA_SU_SC_MODE_CNTL_BASE_IDX = 1 # macro
|
|
regPA_CL_VTE_CNTL = 0x0206 # macro
|
|
regPA_CL_VTE_CNTL_BASE_IDX = 1 # macro
|
|
regPA_CL_VS_OUT_CNTL = 0x0207 # macro
|
|
regPA_CL_VS_OUT_CNTL_BASE_IDX = 1 # macro
|
|
regPA_CL_NANINF_CNTL = 0x0208 # macro
|
|
regPA_CL_NANINF_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SU_LINE_STIPPLE_CNTL = 0x0209 # macro
|
|
regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SU_LINE_STIPPLE_SCALE = 0x020a # macro
|
|
regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX = 1 # macro
|
|
regPA_SU_PRIM_FILTER_CNTL = 0x020b # macro
|
|
regPA_SU_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SU_SMALL_PRIM_FILTER_CNTL = 0x020c # macro
|
|
regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro
|
|
regPA_CL_NGG_CNTL = 0x020e # macro
|
|
regPA_CL_NGG_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SU_OVER_RASTERIZATION_CNTL = 0x020f # macro
|
|
regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX = 1 # macro
|
|
regPA_STEREO_CNTL = 0x0210 # macro
|
|
regPA_STEREO_CNTL_BASE_IDX = 1 # macro
|
|
regPA_STATE_STEREO_X = 0x0211 # macro
|
|
regPA_STATE_STEREO_X_BASE_IDX = 1 # macro
|
|
regPA_CL_VRS_CNTL = 0x0212 # macro
|
|
regPA_CL_VRS_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SU_POINT_SIZE = 0x0280 # macro
|
|
regPA_SU_POINT_SIZE_BASE_IDX = 1 # macro
|
|
regPA_SU_POINT_MINMAX = 0x0281 # macro
|
|
regPA_SU_POINT_MINMAX_BASE_IDX = 1 # macro
|
|
regPA_SU_LINE_CNTL = 0x0282 # macro
|
|
regPA_SU_LINE_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SC_LINE_STIPPLE = 0x0283 # macro
|
|
regPA_SC_LINE_STIPPLE_BASE_IDX = 1 # macro
|
|
regVGT_HOS_MAX_TESS_LEVEL = 0x0286 # macro
|
|
regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX = 1 # macro
|
|
regVGT_HOS_MIN_TESS_LEVEL = 0x0287 # macro
|
|
regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX = 1 # macro
|
|
regPA_SC_MODE_CNTL_0 = 0x0292 # macro
|
|
regPA_SC_MODE_CNTL_0_BASE_IDX = 1 # macro
|
|
regPA_SC_MODE_CNTL_1 = 0x0293 # macro
|
|
regPA_SC_MODE_CNTL_1_BASE_IDX = 1 # macro
|
|
regVGT_ENHANCE = 0x0294 # macro
|
|
regVGT_ENHANCE_BASE_IDX = 1 # macro
|
|
regIA_ENHANCE = 0x029c # macro
|
|
regIA_ENHANCE_BASE_IDX = 1 # macro
|
|
regVGT_DMA_SIZE = 0x029d # macro
|
|
regVGT_DMA_SIZE_BASE_IDX = 1 # macro
|
|
regVGT_DMA_MAX_SIZE = 0x029e # macro
|
|
regVGT_DMA_MAX_SIZE_BASE_IDX = 1 # macro
|
|
regVGT_DMA_INDEX_TYPE = 0x029f # macro
|
|
regVGT_DMA_INDEX_TYPE_BASE_IDX = 1 # macro
|
|
regWD_ENHANCE = 0x02a0 # macro
|
|
regWD_ENHANCE_BASE_IDX = 1 # macro
|
|
regVGT_PRIMITIVEID_EN = 0x02a1 # macro
|
|
regVGT_PRIMITIVEID_EN_BASE_IDX = 1 # macro
|
|
regVGT_DMA_NUM_INSTANCES = 0x02a2 # macro
|
|
regVGT_DMA_NUM_INSTANCES_BASE_IDX = 1 # macro
|
|
regVGT_PRIMITIVEID_RESET = 0x02a3 # macro
|
|
regVGT_PRIMITIVEID_RESET_BASE_IDX = 1 # macro
|
|
regVGT_EVENT_INITIATOR = 0x02a4 # macro
|
|
regVGT_EVENT_INITIATOR_BASE_IDX = 1 # macro
|
|
regVGT_DRAW_PAYLOAD_CNTL = 0x02a6 # macro
|
|
regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX = 1 # macro
|
|
regVGT_ESGS_RING_ITEMSIZE = 0x02ab # macro
|
|
regVGT_ESGS_RING_ITEMSIZE_BASE_IDX = 1 # macro
|
|
regVGT_REUSE_OFF = 0x02ad # macro
|
|
regVGT_REUSE_OFF_BASE_IDX = 1 # macro
|
|
regDB_HTILE_SURFACE = 0x02af # macro
|
|
regDB_HTILE_SURFACE_BASE_IDX = 1 # macro
|
|
regDB_SRESULTS_COMPARE_STATE0 = 0x02b0 # macro
|
|
regDB_SRESULTS_COMPARE_STATE0_BASE_IDX = 1 # macro
|
|
regDB_SRESULTS_COMPARE_STATE1 = 0x02b1 # macro
|
|
regDB_SRESULTS_COMPARE_STATE1_BASE_IDX = 1 # macro
|
|
regDB_PRELOAD_CONTROL = 0x02b2 # macro
|
|
regDB_PRELOAD_CONTROL_BASE_IDX = 1 # macro
|
|
regVGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x02ca # macro
|
|
regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX = 1 # macro
|
|
regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x02cb # macro
|
|
regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX = 1 # macro
|
|
regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x02cc # macro
|
|
regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX = 1 # macro
|
|
regVGT_GS_MAX_VERT_OUT = 0x02ce # macro
|
|
regVGT_GS_MAX_VERT_OUT_BASE_IDX = 1 # macro
|
|
regGE_NGG_SUBGRP_CNTL = 0x02d3 # macro
|
|
regGE_NGG_SUBGRP_CNTL_BASE_IDX = 1 # macro
|
|
regVGT_TESS_DISTRIBUTION = 0x02d4 # macro
|
|
regVGT_TESS_DISTRIBUTION_BASE_IDX = 1 # macro
|
|
regVGT_SHADER_STAGES_EN = 0x02d5 # macro
|
|
regVGT_SHADER_STAGES_EN_BASE_IDX = 1 # macro
|
|
regVGT_LS_HS_CONFIG = 0x02d6 # macro
|
|
regVGT_LS_HS_CONFIG_BASE_IDX = 1 # macro
|
|
regVGT_TF_PARAM = 0x02db # macro
|
|
regVGT_TF_PARAM_BASE_IDX = 1 # macro
|
|
regDB_ALPHA_TO_MASK = 0x02dc # macro
|
|
regDB_ALPHA_TO_MASK_BASE_IDX = 1 # macro
|
|
regPA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x02de # macro
|
|
regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SU_POLY_OFFSET_CLAMP = 0x02df # macro
|
|
regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX = 1 # macro
|
|
regPA_SU_POLY_OFFSET_FRONT_SCALE = 0x02e0 # macro
|
|
regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX = 1 # macro
|
|
regPA_SU_POLY_OFFSET_FRONT_OFFSET = 0x02e1 # macro
|
|
regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX = 1 # macro
|
|
regPA_SU_POLY_OFFSET_BACK_SCALE = 0x02e2 # macro
|
|
regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX = 1 # macro
|
|
regPA_SU_POLY_OFFSET_BACK_OFFSET = 0x02e3 # macro
|
|
regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX = 1 # macro
|
|
regVGT_GS_INSTANCE_CNT = 0x02e4 # macro
|
|
regVGT_GS_INSTANCE_CNT_BASE_IDX = 1 # macro
|
|
regPA_SC_CENTROID_PRIORITY_0 = 0x02f5 # macro
|
|
regPA_SC_CENTROID_PRIORITY_0_BASE_IDX = 1 # macro
|
|
regPA_SC_CENTROID_PRIORITY_1 = 0x02f6 # macro
|
|
regPA_SC_CENTROID_PRIORITY_1_BASE_IDX = 1 # macro
|
|
regPA_SC_LINE_CNTL = 0x02f7 # macro
|
|
regPA_SC_LINE_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_CONFIG = 0x02f8 # macro
|
|
regPA_SC_AA_CONFIG_BASE_IDX = 1 # macro
|
|
regPA_SU_VTX_CNTL = 0x02f9 # macro
|
|
regPA_SU_VTX_CNTL_BASE_IDX = 1 # macro
|
|
regPA_CL_GB_VERT_CLIP_ADJ = 0x02fa # macro
|
|
regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX = 1 # macro
|
|
regPA_CL_GB_VERT_DISC_ADJ = 0x02fb # macro
|
|
regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX = 1 # macro
|
|
regPA_CL_GB_HORZ_CLIP_ADJ = 0x02fc # macro
|
|
regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX = 1 # macro
|
|
regPA_CL_GB_HORZ_DISC_ADJ = 0x02fd # macro
|
|
regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x02fe # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 = 0x02ff # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 = 0x0300 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 = 0x0301 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 = 0x0302 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 = 0x0303 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 = 0x0304 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 = 0x0305 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 = 0x0306 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 = 0x0307 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 = 0x0308 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 = 0x0309 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 = 0x030a # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 = 0x030b # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 = 0x030c # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 = 0x030d # macro
|
|
regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_MASK_X0Y0_X1Y0 = 0x030e # macro
|
|
regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX = 1 # macro
|
|
regPA_SC_AA_MASK_X0Y1_X1Y1 = 0x030f # macro
|
|
regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX = 1 # macro
|
|
regPA_SC_SHADER_CONTROL = 0x0310 # macro
|
|
regPA_SC_SHADER_CONTROL_BASE_IDX = 1 # macro
|
|
regPA_SC_BINNER_CNTL_0 = 0x0311 # macro
|
|
regPA_SC_BINNER_CNTL_0_BASE_IDX = 1 # macro
|
|
regPA_SC_BINNER_CNTL_1 = 0x0312 # macro
|
|
regPA_SC_BINNER_CNTL_1_BASE_IDX = 1 # macro
|
|
regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x0313 # macro
|
|
regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SC_NGG_MODE_CNTL = 0x0314 # macro
|
|
regPA_SC_NGG_MODE_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SC_BINNER_CNTL_2 = 0x0315 # macro
|
|
regPA_SC_BINNER_CNTL_2_BASE_IDX = 1 # macro
|
|
regCB_COLOR0_BASE = 0x0318 # macro
|
|
regCB_COLOR0_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR0_VIEW = 0x031b # macro
|
|
regCB_COLOR0_VIEW_BASE_IDX = 1 # macro
|
|
regCB_COLOR0_INFO = 0x031c # macro
|
|
regCB_COLOR0_INFO_BASE_IDX = 1 # macro
|
|
regCB_COLOR0_ATTRIB = 0x031d # macro
|
|
regCB_COLOR0_ATTRIB_BASE_IDX = 1 # macro
|
|
regCB_COLOR0_FDCC_CONTROL = 0x031e # macro
|
|
regCB_COLOR0_FDCC_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_COLOR0_DCC_BASE = 0x0325 # macro
|
|
regCB_COLOR0_DCC_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR1_BASE = 0x0327 # macro
|
|
regCB_COLOR1_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR1_VIEW = 0x032a # macro
|
|
regCB_COLOR1_VIEW_BASE_IDX = 1 # macro
|
|
regCB_COLOR1_INFO = 0x032b # macro
|
|
regCB_COLOR1_INFO_BASE_IDX = 1 # macro
|
|
regCB_COLOR1_ATTRIB = 0x032c # macro
|
|
regCB_COLOR1_ATTRIB_BASE_IDX = 1 # macro
|
|
regCB_COLOR1_FDCC_CONTROL = 0x032d # macro
|
|
regCB_COLOR1_FDCC_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_COLOR1_DCC_BASE = 0x0334 # macro
|
|
regCB_COLOR1_DCC_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR2_BASE = 0x0336 # macro
|
|
regCB_COLOR2_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR2_VIEW = 0x0339 # macro
|
|
regCB_COLOR2_VIEW_BASE_IDX = 1 # macro
|
|
regCB_COLOR2_INFO = 0x033a # macro
|
|
regCB_COLOR2_INFO_BASE_IDX = 1 # macro
|
|
regCB_COLOR2_ATTRIB = 0x033b # macro
|
|
regCB_COLOR2_ATTRIB_BASE_IDX = 1 # macro
|
|
regCB_COLOR2_FDCC_CONTROL = 0x033c # macro
|
|
regCB_COLOR2_FDCC_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_COLOR2_DCC_BASE = 0x0343 # macro
|
|
regCB_COLOR2_DCC_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR3_BASE = 0x0345 # macro
|
|
regCB_COLOR3_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR3_VIEW = 0x0348 # macro
|
|
regCB_COLOR3_VIEW_BASE_IDX = 1 # macro
|
|
regCB_COLOR3_INFO = 0x0349 # macro
|
|
regCB_COLOR3_INFO_BASE_IDX = 1 # macro
|
|
regCB_COLOR3_ATTRIB = 0x034a # macro
|
|
regCB_COLOR3_ATTRIB_BASE_IDX = 1 # macro
|
|
regCB_COLOR3_FDCC_CONTROL = 0x034b # macro
|
|
regCB_COLOR3_FDCC_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_COLOR3_DCC_BASE = 0x0352 # macro
|
|
regCB_COLOR3_DCC_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR4_BASE = 0x0354 # macro
|
|
regCB_COLOR4_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR4_VIEW = 0x0357 # macro
|
|
regCB_COLOR4_VIEW_BASE_IDX = 1 # macro
|
|
regCB_COLOR4_INFO = 0x0358 # macro
|
|
regCB_COLOR4_INFO_BASE_IDX = 1 # macro
|
|
regCB_COLOR4_ATTRIB = 0x0359 # macro
|
|
regCB_COLOR4_ATTRIB_BASE_IDX = 1 # macro
|
|
regCB_COLOR4_FDCC_CONTROL = 0x035a # macro
|
|
regCB_COLOR4_FDCC_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_COLOR4_DCC_BASE = 0x0361 # macro
|
|
regCB_COLOR4_DCC_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR5_BASE = 0x0363 # macro
|
|
regCB_COLOR5_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR5_VIEW = 0x0366 # macro
|
|
regCB_COLOR5_VIEW_BASE_IDX = 1 # macro
|
|
regCB_COLOR5_INFO = 0x0367 # macro
|
|
regCB_COLOR5_INFO_BASE_IDX = 1 # macro
|
|
regCB_COLOR5_ATTRIB = 0x0368 # macro
|
|
regCB_COLOR5_ATTRIB_BASE_IDX = 1 # macro
|
|
regCB_COLOR5_FDCC_CONTROL = 0x0369 # macro
|
|
regCB_COLOR5_FDCC_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_COLOR5_DCC_BASE = 0x0370 # macro
|
|
regCB_COLOR5_DCC_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR6_BASE = 0x0372 # macro
|
|
regCB_COLOR6_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR6_VIEW = 0x0375 # macro
|
|
regCB_COLOR6_VIEW_BASE_IDX = 1 # macro
|
|
regCB_COLOR6_INFO = 0x0376 # macro
|
|
regCB_COLOR6_INFO_BASE_IDX = 1 # macro
|
|
regCB_COLOR6_ATTRIB = 0x0377 # macro
|
|
regCB_COLOR6_ATTRIB_BASE_IDX = 1 # macro
|
|
regCB_COLOR6_FDCC_CONTROL = 0x0378 # macro
|
|
regCB_COLOR6_FDCC_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_COLOR6_DCC_BASE = 0x037f # macro
|
|
regCB_COLOR6_DCC_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR7_BASE = 0x0381 # macro
|
|
regCB_COLOR7_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR7_VIEW = 0x0384 # macro
|
|
regCB_COLOR7_VIEW_BASE_IDX = 1 # macro
|
|
regCB_COLOR7_INFO = 0x0385 # macro
|
|
regCB_COLOR7_INFO_BASE_IDX = 1 # macro
|
|
regCB_COLOR7_ATTRIB = 0x0386 # macro
|
|
regCB_COLOR7_ATTRIB_BASE_IDX = 1 # macro
|
|
regCB_COLOR7_FDCC_CONTROL = 0x0387 # macro
|
|
regCB_COLOR7_FDCC_CONTROL_BASE_IDX = 1 # macro
|
|
regCB_COLOR7_DCC_BASE = 0x038e # macro
|
|
regCB_COLOR7_DCC_BASE_BASE_IDX = 1 # macro
|
|
regCB_COLOR0_BASE_EXT = 0x0390 # macro
|
|
regCB_COLOR0_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR1_BASE_EXT = 0x0391 # macro
|
|
regCB_COLOR1_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR2_BASE_EXT = 0x0392 # macro
|
|
regCB_COLOR2_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR3_BASE_EXT = 0x0393 # macro
|
|
regCB_COLOR3_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR4_BASE_EXT = 0x0394 # macro
|
|
regCB_COLOR4_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR5_BASE_EXT = 0x0395 # macro
|
|
regCB_COLOR5_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR6_BASE_EXT = 0x0396 # macro
|
|
regCB_COLOR6_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR7_BASE_EXT = 0x0397 # macro
|
|
regCB_COLOR7_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR0_DCC_BASE_EXT = 0x03a8 # macro
|
|
regCB_COLOR0_DCC_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR1_DCC_BASE_EXT = 0x03a9 # macro
|
|
regCB_COLOR1_DCC_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR2_DCC_BASE_EXT = 0x03aa # macro
|
|
regCB_COLOR2_DCC_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR3_DCC_BASE_EXT = 0x03ab # macro
|
|
regCB_COLOR3_DCC_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR4_DCC_BASE_EXT = 0x03ac # macro
|
|
regCB_COLOR4_DCC_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR5_DCC_BASE_EXT = 0x03ad # macro
|
|
regCB_COLOR5_DCC_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR6_DCC_BASE_EXT = 0x03ae # macro
|
|
regCB_COLOR6_DCC_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR7_DCC_BASE_EXT = 0x03af # macro
|
|
regCB_COLOR7_DCC_BASE_EXT_BASE_IDX = 1 # macro
|
|
regCB_COLOR0_ATTRIB2 = 0x03b0 # macro
|
|
regCB_COLOR0_ATTRIB2_BASE_IDX = 1 # macro
|
|
regCB_COLOR1_ATTRIB2 = 0x03b1 # macro
|
|
regCB_COLOR1_ATTRIB2_BASE_IDX = 1 # macro
|
|
regCB_COLOR2_ATTRIB2 = 0x03b2 # macro
|
|
regCB_COLOR2_ATTRIB2_BASE_IDX = 1 # macro
|
|
regCB_COLOR3_ATTRIB2 = 0x03b3 # macro
|
|
regCB_COLOR3_ATTRIB2_BASE_IDX = 1 # macro
|
|
regCB_COLOR4_ATTRIB2 = 0x03b4 # macro
|
|
regCB_COLOR4_ATTRIB2_BASE_IDX = 1 # macro
|
|
regCB_COLOR5_ATTRIB2 = 0x03b5 # macro
|
|
regCB_COLOR5_ATTRIB2_BASE_IDX = 1 # macro
|
|
regCB_COLOR6_ATTRIB2 = 0x03b6 # macro
|
|
regCB_COLOR6_ATTRIB2_BASE_IDX = 1 # macro
|
|
regCB_COLOR7_ATTRIB2 = 0x03b7 # macro
|
|
regCB_COLOR7_ATTRIB2_BASE_IDX = 1 # macro
|
|
regCB_COLOR0_ATTRIB3 = 0x03b8 # macro
|
|
regCB_COLOR0_ATTRIB3_BASE_IDX = 1 # macro
|
|
regCB_COLOR1_ATTRIB3 = 0x03b9 # macro
|
|
regCB_COLOR1_ATTRIB3_BASE_IDX = 1 # macro
|
|
regCB_COLOR2_ATTRIB3 = 0x03ba # macro
|
|
regCB_COLOR2_ATTRIB3_BASE_IDX = 1 # macro
|
|
regCB_COLOR3_ATTRIB3 = 0x03bb # macro
|
|
regCB_COLOR3_ATTRIB3_BASE_IDX = 1 # macro
|
|
regCB_COLOR4_ATTRIB3 = 0x03bc # macro
|
|
regCB_COLOR4_ATTRIB3_BASE_IDX = 1 # macro
|
|
regCB_COLOR5_ATTRIB3 = 0x03bd # macro
|
|
regCB_COLOR5_ATTRIB3_BASE_IDX = 1 # macro
|
|
regCB_COLOR6_ATTRIB3 = 0x03be # macro
|
|
regCB_COLOR6_ATTRIB3_BASE_IDX = 1 # macro
|
|
regCB_COLOR7_ATTRIB3 = 0x03bf # macro
|
|
regCB_COLOR7_ATTRIB3_BASE_IDX = 1 # macro
|
|
regCONFIG_RESERVED_REG0 = 0x0800 # macro
|
|
regCONFIG_RESERVED_REG0_BASE_IDX = 1 # macro
|
|
regCONFIG_RESERVED_REG1 = 0x0801 # macro
|
|
regCONFIG_RESERVED_REG1_BASE_IDX = 1 # macro
|
|
regCP_MEC_CNTL = 0x0802 # macro
|
|
regCP_MEC_CNTL_BASE_IDX = 1 # macro
|
|
regCP_ME_CNTL = 0x0803 # macro
|
|
regCP_ME_CNTL_BASE_IDX = 1 # macro
|
|
regGRBM_GFX_CNTL = 0x0900 # macro
|
|
regGRBM_GFX_CNTL_BASE_IDX = 1 # macro
|
|
regGRBM_NOWHERE = 0x0901 # macro
|
|
regGRBM_NOWHERE_BASE_IDX = 1 # macro
|
|
regPA_SC_VRS_SURFACE_CNTL = 0x0940 # macro
|
|
regPA_SC_VRS_SURFACE_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SC_ENHANCE = 0x0941 # macro
|
|
regPA_SC_ENHANCE_BASE_IDX = 1 # macro
|
|
regPA_SC_ENHANCE_1 = 0x0942 # macro
|
|
regPA_SC_ENHANCE_1_BASE_IDX = 1 # macro
|
|
regPA_SC_ENHANCE_2 = 0x0943 # macro
|
|
regPA_SC_ENHANCE_2_BASE_IDX = 1 # macro
|
|
regPA_SC_ENHANCE_3 = 0x0944 # macro
|
|
regPA_SC_ENHANCE_3_BASE_IDX = 1 # macro
|
|
regPA_SC_BINNER_CNTL_OVERRIDE = 0x0946 # macro
|
|
regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX = 1 # macro
|
|
regPA_SC_PBB_OVERRIDE_FLAG = 0x0947 # macro
|
|
regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX = 1 # macro
|
|
regPA_SC_DSM_CNTL = 0x0948 # macro
|
|
regPA_SC_DSM_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SC_TILE_STEERING_CREST_OVERRIDE = 0x0949 # macro
|
|
regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX = 1 # macro
|
|
regPA_SC_FIFO_SIZE = 0x094a # macro
|
|
regPA_SC_FIFO_SIZE_BASE_IDX = 1 # macro
|
|
regPA_SC_IF_FIFO_SIZE = 0x094b # macro
|
|
regPA_SC_IF_FIFO_SIZE_BASE_IDX = 1 # macro
|
|
regPA_SC_PACKER_WAVE_ID_CNTL = 0x094c # macro
|
|
regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SC_ATM_CNTL = 0x094d # macro
|
|
regPA_SC_ATM_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SC_PKR_WAVE_TABLE_CNTL = 0x094e # macro
|
|
regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX = 1 # macro
|
|
regPA_SC_FORCE_EOV_MAX_CNTS = 0x094f # macro
|
|
regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX = 1 # macro
|
|
regPA_SC_BINNER_EVENT_CNTL_0 = 0x0950 # macro
|
|
regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX = 1 # macro
|
|
regPA_SC_BINNER_EVENT_CNTL_1 = 0x0951 # macro
|
|
regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX = 1 # macro
|
|
regPA_SC_BINNER_EVENT_CNTL_2 = 0x0952 # macro
|
|
regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX = 1 # macro
|
|
regPA_SC_BINNER_EVENT_CNTL_3 = 0x0953 # macro
|
|
regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX = 1 # macro
|
|
regPA_SC_BINNER_TIMEOUT_COUNTER = 0x0954 # macro
|
|
regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX = 1 # macro
|
|
regPA_SC_BINNER_PERF_CNTL_0 = 0x0955 # macro
|
|
regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX = 1 # macro
|
|
regPA_SC_BINNER_PERF_CNTL_1 = 0x0956 # macro
|
|
regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX = 1 # macro
|
|
regPA_SC_BINNER_PERF_CNTL_2 = 0x0957 # macro
|
|
regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX = 1 # macro
|
|
regPA_SC_BINNER_PERF_CNTL_3 = 0x0958 # macro
|
|
regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX = 1 # macro
|
|
regPA_SC_P3D_TRAP_SCREEN_HV_LOCK = 0x095b # macro
|
|
regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro
|
|
regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK = 0x095c # macro
|
|
regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro
|
|
regPA_SC_TRAP_SCREEN_HV_LOCK = 0x095d # macro
|
|
regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro
|
|
regPA_PH_INTERFACE_FIFO_SIZE = 0x095e # macro
|
|
regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX = 1 # macro
|
|
regPA_PH_ENHANCE = 0x095f # macro
|
|
regPA_PH_ENHANCE_BASE_IDX = 1 # macro
|
|
regPA_SC_VRS_SURFACE_CNTL_1 = 0x0960 # macro
|
|
regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX = 1 # macro
|
|
regSQ_RUNTIME_CONFIG = 0x09e0 # macro
|
|
regSQ_RUNTIME_CONFIG_BASE_IDX = 1 # macro
|
|
regSQ_DEBUG_STS_GLOBAL = 0x09e1 # macro
|
|
regSQ_DEBUG_STS_GLOBAL_BASE_IDX = 1 # macro
|
|
regSQ_DEBUG_STS_GLOBAL2 = 0x09e2 # macro
|
|
regSQ_DEBUG_STS_GLOBAL2_BASE_IDX = 1 # macro
|
|
regSH_MEM_BASES = 0x09e3 # macro
|
|
regSH_MEM_BASES_BASE_IDX = 1 # macro
|
|
regSH_MEM_CONFIG = 0x09e4 # macro
|
|
regSH_MEM_CONFIG_BASE_IDX = 1 # macro
|
|
regSQ_DEBUG = 0x09e5 # macro
|
|
regSQ_DEBUG_BASE_IDX = 1 # macro
|
|
regSQ_SHADER_TBA_LO = 0x09e6 # macro
|
|
regSQ_SHADER_TBA_LO_BASE_IDX = 1 # macro
|
|
regSQ_SHADER_TBA_HI = 0x09e7 # macro
|
|
regSQ_SHADER_TBA_HI_BASE_IDX = 1 # macro
|
|
regSQ_SHADER_TMA_LO = 0x09e8 # macro
|
|
regSQ_SHADER_TMA_LO_BASE_IDX = 1 # macro
|
|
regSQ_SHADER_TMA_HI = 0x09e9 # macro
|
|
regSQ_SHADER_TMA_HI_BASE_IDX = 1 # macro
|
|
regCP_DEBUG_2 = 0x1800 # macro
|
|
regCP_DEBUG_2_BASE_IDX = 1 # macro
|
|
regCP_FETCHER_SOURCE = 0x1801 # macro
|
|
regCP_FETCHER_SOURCE_BASE_IDX = 1 # macro
|
|
regCP_HPD_MES_ROQ_OFFSETS = 0x1821 # macro
|
|
regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX = 1 # macro
|
|
regCP_HPD_ROQ_OFFSETS = 0x1821 # macro
|
|
regCP_HPD_ROQ_OFFSETS_BASE_IDX = 1 # macro
|
|
regCP_HPD_STATUS0 = 0x1822 # macro
|
|
regCP_HPD_STATUS0_BASE_IDX = 1 # macro
|
|
regDIDT_INDEX_AUTO_INCR_EN = 0x1900 # macro
|
|
regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX = 1 # macro
|
|
regDIDT_EDC_CTRL = 0x1901 # macro
|
|
regDIDT_EDC_CTRL_BASE_IDX = 1 # macro
|
|
regDIDT_EDC_THROTTLE_CTRL = 0x1902 # macro
|
|
regDIDT_EDC_THROTTLE_CTRL_BASE_IDX = 1 # macro
|
|
regDIDT_EDC_THRESHOLD = 0x1903 # macro
|
|
regDIDT_EDC_THRESHOLD_BASE_IDX = 1 # macro
|
|
regDIDT_EDC_STALL_PATTERN_1_2 = 0x1904 # macro
|
|
regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX = 1 # macro
|
|
regDIDT_EDC_STALL_PATTERN_3_4 = 0x1905 # macro
|
|
regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX = 1 # macro
|
|
regDIDT_EDC_STALL_PATTERN_5_6 = 0x1906 # macro
|
|
regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX = 1 # macro
|
|
regDIDT_EDC_STALL_PATTERN_7 = 0x1907 # macro
|
|
regDIDT_EDC_STALL_PATTERN_7_BASE_IDX = 1 # macro
|
|
regDIDT_EDC_STATUS = 0x1908 # macro
|
|
regDIDT_EDC_STATUS_BASE_IDX = 1 # macro
|
|
regDIDT_EDC_DYNAMIC_THRESHOLD_RO = 0x1909 # macro
|
|
regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX = 1 # macro
|
|
regDIDT_EDC_OVERFLOW = 0x190a # macro
|
|
regDIDT_EDC_OVERFLOW_BASE_IDX = 1 # macro
|
|
regDIDT_EDC_ROLLING_POWER_DELTA = 0x190b # macro
|
|
regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX = 1 # macro
|
|
regDIDT_IND_INDEX = 0x190c # macro
|
|
regDIDT_IND_INDEX_BASE_IDX = 1 # macro
|
|
regDIDT_IND_DATA = 0x190d # macro
|
|
regDIDT_IND_DATA_BASE_IDX = 1 # macro
|
|
regSPI_GDBG_WAVE_CNTL = 0x1943 # macro
|
|
regSPI_GDBG_WAVE_CNTL_BASE_IDX = 1 # macro
|
|
regSPI_GDBG_TRAP_CONFIG = 0x1944 # macro
|
|
regSPI_GDBG_TRAP_CONFIG_BASE_IDX = 1 # macro
|
|
regSPI_GDBG_WAVE_CNTL3 = 0x1945 # macro
|
|
regSPI_GDBG_WAVE_CNTL3_BASE_IDX = 1 # macro
|
|
regSPI_ARB_CNTL_0 = 0x1949 # macro
|
|
regSPI_ARB_CNTL_0_BASE_IDX = 1 # macro
|
|
regSPI_FEATURE_CTRL = 0x194a # macro
|
|
regSPI_FEATURE_CTRL_BASE_IDX = 1 # macro
|
|
regSPI_SHADER_RSRC_LIMIT_CTRL = 0x194b # macro
|
|
regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX = 1 # macro
|
|
regSPI_COMPUTE_WF_CTX_SAVE_STATUS = 0x194e # macro
|
|
regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX = 1 # macro
|
|
regTCP_INVALIDATE = 0x19a0 # macro
|
|
regTCP_INVALIDATE_BASE_IDX = 1 # macro
|
|
regTCP_STATUS = 0x19a1 # macro
|
|
regTCP_STATUS_BASE_IDX = 1 # macro
|
|
regTCP_CNTL = 0x19a2 # macro
|
|
regTCP_CNTL_BASE_IDX = 1 # macro
|
|
regTCP_CNTL2 = 0x19a3 # macro
|
|
regTCP_CNTL2_BASE_IDX = 1 # macro
|
|
regTCP_DEBUG_INDEX = 0x19a5 # macro
|
|
regTCP_DEBUG_INDEX_BASE_IDX = 1 # macro
|
|
regTCP_DEBUG_DATA = 0x19a6 # macro
|
|
regTCP_DEBUG_DATA_BASE_IDX = 1 # macro
|
|
regGDS_ENHANCE2 = 0x19b0 # macro
|
|
regGDS_ENHANCE2_BASE_IDX = 1 # macro
|
|
regGDS_OA_CGPG_RESTORE = 0x19b1 # macro
|
|
regGDS_OA_CGPG_RESTORE_BASE_IDX = 1 # macro
|
|
regUTCL1_CTRL_0 = 0x1980 # macro
|
|
regUTCL1_CTRL_0_BASE_IDX = 1 # macro
|
|
regUTCL1_UTCL0_INVREQ_DISABLE = 0x1984 # macro
|
|
regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX = 1 # macro
|
|
regUTCL1_CTRL_2 = 0x1985 # macro
|
|
regUTCL1_CTRL_2_BASE_IDX = 1 # macro
|
|
regUTCL1_FIFO_SIZING = 0x1986 # macro
|
|
regUTCL1_FIFO_SIZING_BASE_IDX = 1 # macro
|
|
regGCRD_SA0_TARGETS_DISABLE = 0x1987 # macro
|
|
regGCRD_SA0_TARGETS_DISABLE_BASE_IDX = 1 # macro
|
|
regGCRD_SA1_TARGETS_DISABLE = 0x1989 # macro
|
|
regGCRD_SA1_TARGETS_DISABLE_BASE_IDX = 1 # macro
|
|
regGCRD_CREDIT_SAFE = 0x198a # macro
|
|
regGCRD_CREDIT_SAFE_BASE_IDX = 1 # macro
|
|
regGCR_GENERAL_CNTL = 0x1990 # macro
|
|
regGCR_GENERAL_CNTL_BASE_IDX = 1 # macro
|
|
regGCR_CMD_STATUS = 0x1992 # macro
|
|
regGCR_CMD_STATUS_BASE_IDX = 1 # macro
|
|
regGCR_SPARE = 0x1993 # macro
|
|
regGCR_SPARE_BASE_IDX = 1 # macro
|
|
regPMM_CNTL2 = 0x1999 # macro
|
|
regPMM_CNTL2_BASE_IDX = 1 # macro
|
|
regSEDC_GL1_GL2_OVERRIDES = 0x1ac0 # macro
|
|
regSEDC_GL1_GL2_OVERRIDES_BASE_IDX = 1 # macro
|
|
regGC_CAC_CTRL_1 = 0x1ad0 # macro
|
|
regGC_CAC_CTRL_1_BASE_IDX = 1 # macro
|
|
regGC_CAC_CTRL_2 = 0x1ad1 # macro
|
|
regGC_CAC_CTRL_2_BASE_IDX = 1 # macro
|
|
regGC_CAC_AGGR_LOWER = 0x1ad2 # macro
|
|
regGC_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
|
|
regGC_CAC_AGGR_UPPER = 0x1ad3 # macro
|
|
regGC_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
|
|
regSE0_CAC_AGGR_LOWER = 0x1ad4 # macro
|
|
regSE0_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
|
|
regSE0_CAC_AGGR_UPPER = 0x1ad5 # macro
|
|
regSE0_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
|
|
regSE1_CAC_AGGR_LOWER = 0x1ad6 # macro
|
|
regSE1_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
|
|
regSE1_CAC_AGGR_UPPER = 0x1ad7 # macro
|
|
regSE1_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
|
|
regSE2_CAC_AGGR_LOWER = 0x1ad8 # macro
|
|
regSE2_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
|
|
regSE2_CAC_AGGR_UPPER = 0x1ad9 # macro
|
|
regSE2_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
|
|
regSE3_CAC_AGGR_LOWER = 0x1ada # macro
|
|
regSE3_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
|
|
regSE3_CAC_AGGR_UPPER = 0x1adb # macro
|
|
regSE3_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
|
|
regSE4_CAC_AGGR_LOWER = 0x1adc # macro
|
|
regSE4_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
|
|
regSE4_CAC_AGGR_UPPER = 0x1add # macro
|
|
regSE4_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
|
|
regSE5_CAC_AGGR_LOWER = 0x1ade # macro
|
|
regSE5_CAC_AGGR_LOWER_BASE_IDX = 1 # macro
|
|
regSE5_CAC_AGGR_UPPER = 0x1adf # macro
|
|
regSE5_CAC_AGGR_UPPER_BASE_IDX = 1 # macro
|
|
regGC_CAC_AGGR_GFXCLK_CYCLE = 0x1ae4 # macro
|
|
regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
|
|
regSE0_CAC_AGGR_GFXCLK_CYCLE = 0x1ae5 # macro
|
|
regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
|
|
regSE1_CAC_AGGR_GFXCLK_CYCLE = 0x1ae6 # macro
|
|
regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
|
|
regSE2_CAC_AGGR_GFXCLK_CYCLE = 0x1ae7 # macro
|
|
regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
|
|
regSE3_CAC_AGGR_GFXCLK_CYCLE = 0x1ae8 # macro
|
|
regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
|
|
regSE4_CAC_AGGR_GFXCLK_CYCLE = 0x1ae9 # macro
|
|
regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
|
|
regSE5_CAC_AGGR_GFXCLK_CYCLE = 0x1aea # macro
|
|
regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro
|
|
regGC_EDC_CTRL = 0x1aed # macro
|
|
regGC_EDC_CTRL_BASE_IDX = 1 # macro
|
|
regGC_EDC_THRESHOLD = 0x1aee # macro
|
|
regGC_EDC_THRESHOLD_BASE_IDX = 1 # macro
|
|
regGC_EDC_STRETCH_CTRL = 0x1aef # macro
|
|
regGC_EDC_STRETCH_CTRL_BASE_IDX = 1 # macro
|
|
regGC_EDC_STRETCH_THRESHOLD = 0x1af0 # macro
|
|
regGC_EDC_STRETCH_THRESHOLD_BASE_IDX = 1 # macro
|
|
regEDC_HYSTERESIS_CNTL = 0x1af1 # macro
|
|
regEDC_HYSTERESIS_CNTL_BASE_IDX = 1 # macro
|
|
regGC_THROTTLE_CTRL = 0x1af2 # macro
|
|
regGC_THROTTLE_CTRL_BASE_IDX = 1 # macro
|
|
regGC_THROTTLE_CTRL1 = 0x1af3 # macro
|
|
regGC_THROTTLE_CTRL1_BASE_IDX = 1 # macro
|
|
regPCC_STALL_PATTERN_CTRL = 0x1af4 # macro
|
|
regPCC_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro
|
|
regPWRBRK_STALL_PATTERN_CTRL = 0x1af5 # macro
|
|
regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro
|
|
regPCC_STALL_PATTERN_1_2 = 0x1af6 # macro
|
|
regPCC_STALL_PATTERN_1_2_BASE_IDX = 1 # macro
|
|
regPCC_STALL_PATTERN_3_4 = 0x1af7 # macro
|
|
regPCC_STALL_PATTERN_3_4_BASE_IDX = 1 # macro
|
|
regPCC_STALL_PATTERN_5_6 = 0x1af8 # macro
|
|
regPCC_STALL_PATTERN_5_6_BASE_IDX = 1 # macro
|
|
regPCC_STALL_PATTERN_7 = 0x1af9 # macro
|
|
regPCC_STALL_PATTERN_7_BASE_IDX = 1 # macro
|
|
regPWRBRK_STALL_PATTERN_1_2 = 0x1afa # macro
|
|
regPWRBRK_STALL_PATTERN_1_2_BASE_IDX = 1 # macro
|
|
regPWRBRK_STALL_PATTERN_3_4 = 0x1afb # macro
|
|
regPWRBRK_STALL_PATTERN_3_4_BASE_IDX = 1 # macro
|
|
regPWRBRK_STALL_PATTERN_5_6 = 0x1afc # macro
|
|
regPWRBRK_STALL_PATTERN_5_6_BASE_IDX = 1 # macro
|
|
regPWRBRK_STALL_PATTERN_7 = 0x1afd # macro
|
|
regPWRBRK_STALL_PATTERN_7_BASE_IDX = 1 # macro
|
|
regDIDT_STALL_PATTERN_CTRL = 0x1afe # macro
|
|
regDIDT_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro
|
|
regDIDT_STALL_PATTERN_1_2 = 0x1aff # macro
|
|
regDIDT_STALL_PATTERN_1_2_BASE_IDX = 1 # macro
|
|
regDIDT_STALL_PATTERN_3_4 = 0x1b00 # macro
|
|
regDIDT_STALL_PATTERN_3_4_BASE_IDX = 1 # macro
|
|
regDIDT_STALL_PATTERN_5_6 = 0x1b01 # macro
|
|
regDIDT_STALL_PATTERN_5_6_BASE_IDX = 1 # macro
|
|
regDIDT_STALL_PATTERN_7 = 0x1b02 # macro
|
|
regDIDT_STALL_PATTERN_7_BASE_IDX = 1 # macro
|
|
regPCC_PWRBRK_HYSTERESIS_CTRL = 0x1b03 # macro
|
|
regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX = 1 # macro
|
|
regEDC_STRETCH_PERF_COUNTER = 0x1b04 # macro
|
|
regEDC_STRETCH_PERF_COUNTER_BASE_IDX = 1 # macro
|
|
regEDC_UNSTRETCH_PERF_COUNTER = 0x1b05 # macro
|
|
regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX = 1 # macro
|
|
regEDC_STRETCH_NUM_PERF_COUNTER = 0x1b06 # macro
|
|
regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX = 1 # macro
|
|
regGC_EDC_STATUS = 0x1b07 # macro
|
|
regGC_EDC_STATUS_BASE_IDX = 1 # macro
|
|
regGC_EDC_OVERFLOW = 0x1b08 # macro
|
|
regGC_EDC_OVERFLOW_BASE_IDX = 1 # macro
|
|
regGC_EDC_ROLLING_POWER_DELTA = 0x1b09 # macro
|
|
regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX = 1 # macro
|
|
regGC_THROTTLE_STATUS = 0x1b0a # macro
|
|
regGC_THROTTLE_STATUS_BASE_IDX = 1 # macro
|
|
regEDC_PERF_COUNTER = 0x1b0b # macro
|
|
regEDC_PERF_COUNTER_BASE_IDX = 1 # macro
|
|
regPCC_PERF_COUNTER = 0x1b0c # macro
|
|
regPCC_PERF_COUNTER_BASE_IDX = 1 # macro
|
|
regPWRBRK_PERF_COUNTER = 0x1b0d # macro
|
|
regPWRBRK_PERF_COUNTER_BASE_IDX = 1 # macro
|
|
regEDC_HYSTERESIS_STAT = 0x1b0e # macro
|
|
regEDC_HYSTERESIS_STAT_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_CP_0 = 0x1b10 # macro
|
|
regGC_CAC_WEIGHT_CP_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_CP_1 = 0x1b11 # macro
|
|
regGC_CAC_WEIGHT_CP_1_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_EA_0 = 0x1b12 # macro
|
|
regGC_CAC_WEIGHT_EA_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_EA_1 = 0x1b13 # macro
|
|
regGC_CAC_WEIGHT_EA_1_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_EA_2 = 0x1b14 # macro
|
|
regGC_CAC_WEIGHT_EA_2_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_ROUTER_0 = 0x1b15 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_ROUTER_1 = 0x1b16 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_ROUTER_2 = 0x1b17 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_ROUTER_3 = 0x1b18 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_ROUTER_4 = 0x1b19 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_VML2_0 = 0x1b1a # macro
|
|
regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_VML2_1 = 0x1b1b # macro
|
|
regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_VML2_2 = 0x1b1c # macro
|
|
regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_WALKER_0 = 0x1b1d # macro
|
|
regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_WALKER_1 = 0x1b1e # macro
|
|
regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_UTCL2_WALKER_2 = 0x1b1f # macro
|
|
regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GDS_0 = 0x1b20 # macro
|
|
regGC_CAC_WEIGHT_GDS_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GDS_1 = 0x1b21 # macro
|
|
regGC_CAC_WEIGHT_GDS_1_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GDS_2 = 0x1b22 # macro
|
|
regGC_CAC_WEIGHT_GDS_2_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GE_0 = 0x1b23 # macro
|
|
regGC_CAC_WEIGHT_GE_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GE_1 = 0x1b24 # macro
|
|
regGC_CAC_WEIGHT_GE_1_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GE_2 = 0x1b25 # macro
|
|
regGC_CAC_WEIGHT_GE_2_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GE_3 = 0x1b26 # macro
|
|
regGC_CAC_WEIGHT_GE_3_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GE_4 = 0x1b27 # macro
|
|
regGC_CAC_WEIGHT_GE_4_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GE_5 = 0x1b28 # macro
|
|
regGC_CAC_WEIGHT_GE_5_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GE_6 = 0x1b29 # macro
|
|
regGC_CAC_WEIGHT_GE_6_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_PMM_0 = 0x1b2e # macro
|
|
regGC_CAC_WEIGHT_PMM_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GL2C_0 = 0x1b2f # macro
|
|
regGC_CAC_WEIGHT_GL2C_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GL2C_1 = 0x1b30 # macro
|
|
regGC_CAC_WEIGHT_GL2C_1_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GL2C_2 = 0x1b31 # macro
|
|
regGC_CAC_WEIGHT_GL2C_2_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_PH_0 = 0x1b32 # macro
|
|
regGC_CAC_WEIGHT_PH_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_PH_1 = 0x1b33 # macro
|
|
regGC_CAC_WEIGHT_PH_1_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_PH_2 = 0x1b34 # macro
|
|
regGC_CAC_WEIGHT_PH_2_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_PH_3 = 0x1b35 # macro
|
|
regGC_CAC_WEIGHT_PH_3_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_SDMA_0 = 0x1b36 # macro
|
|
regGC_CAC_WEIGHT_SDMA_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_SDMA_1 = 0x1b37 # macro
|
|
regGC_CAC_WEIGHT_SDMA_1_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_SDMA_2 = 0x1b38 # macro
|
|
regGC_CAC_WEIGHT_SDMA_2_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_SDMA_3 = 0x1b39 # macro
|
|
regGC_CAC_WEIGHT_SDMA_3_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_SDMA_4 = 0x1b3a # macro
|
|
regGC_CAC_WEIGHT_SDMA_4_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_SDMA_5 = 0x1b3b # macro
|
|
regGC_CAC_WEIGHT_SDMA_5_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_CHC_0 = 0x1b3c # macro
|
|
regGC_CAC_WEIGHT_CHC_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_CHC_1 = 0x1b3d # macro
|
|
regGC_CAC_WEIGHT_CHC_1_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GUS_0 = 0x1b3e # macro
|
|
regGC_CAC_WEIGHT_GUS_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GUS_1 = 0x1b3f # macro
|
|
regGC_CAC_WEIGHT_GUS_1_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_RLC_0 = 0x1b40 # macro
|
|
regGC_CAC_WEIGHT_RLC_0_BASE_IDX = 1 # macro
|
|
regGC_CAC_WEIGHT_GRBM_0 = 0x1b44 # macro
|
|
regGC_CAC_WEIGHT_GRBM_0_BASE_IDX = 1 # macro
|
|
regGC_EDC_CLK_MONITOR_CTRL = 0x1b56 # macro
|
|
regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX = 1 # macro
|
|
regGC_CAC_IND_INDEX = 0x1b58 # macro
|
|
regGC_CAC_IND_INDEX_BASE_IDX = 1 # macro
|
|
regGC_CAC_IND_DATA = 0x1b59 # macro
|
|
regGC_CAC_IND_DATA_BASE_IDX = 1 # macro
|
|
regSE_CAC_CTRL_1 = 0x1b70 # macro
|
|
regSE_CAC_CTRL_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_CTRL_2 = 0x1b71 # macro
|
|
regSE_CAC_CTRL_2_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_TA_0 = 0x1b72 # macro
|
|
regSE_CAC_WEIGHT_TA_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_TD_0 = 0x1b73 # macro
|
|
regSE_CAC_WEIGHT_TD_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_TD_1 = 0x1b74 # macro
|
|
regSE_CAC_WEIGHT_TD_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_TD_2 = 0x1b75 # macro
|
|
regSE_CAC_WEIGHT_TD_2_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_TD_3 = 0x1b76 # macro
|
|
regSE_CAC_WEIGHT_TD_3_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_TD_4 = 0x1b77 # macro
|
|
regSE_CAC_WEIGHT_TD_4_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_TD_5 = 0x1b78 # macro
|
|
regSE_CAC_WEIGHT_TD_5_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_TCP_0 = 0x1b79 # macro
|
|
regSE_CAC_WEIGHT_TCP_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_TCP_1 = 0x1b7a # macro
|
|
regSE_CAC_WEIGHT_TCP_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_TCP_2 = 0x1b7b # macro
|
|
regSE_CAC_WEIGHT_TCP_2_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_TCP_3 = 0x1b7c # macro
|
|
regSE_CAC_WEIGHT_TCP_3_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SQ_0 = 0x1b7d # macro
|
|
regSE_CAC_WEIGHT_SQ_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SQ_1 = 0x1b7e # macro
|
|
regSE_CAC_WEIGHT_SQ_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SQ_2 = 0x1b7f # macro
|
|
regSE_CAC_WEIGHT_SQ_2_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SP_0 = 0x1b80 # macro
|
|
regSE_CAC_WEIGHT_SP_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SP_1 = 0x1b81 # macro
|
|
regSE_CAC_WEIGHT_SP_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_LDS_0 = 0x1b82 # macro
|
|
regSE_CAC_WEIGHT_LDS_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_LDS_1 = 0x1b83 # macro
|
|
regSE_CAC_WEIGHT_LDS_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_LDS_2 = 0x1b84 # macro
|
|
regSE_CAC_WEIGHT_LDS_2_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_LDS_3 = 0x1b85 # macro
|
|
regSE_CAC_WEIGHT_LDS_3_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SQC_0 = 0x1b87 # macro
|
|
regSE_CAC_WEIGHT_SQC_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SQC_1 = 0x1b88 # macro
|
|
regSE_CAC_WEIGHT_SQC_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_CU_0 = 0x1b89 # macro
|
|
regSE_CAC_WEIGHT_CU_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_BCI_0 = 0x1b8a # macro
|
|
regSE_CAC_WEIGHT_BCI_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_CB_0 = 0x1b8b # macro
|
|
regSE_CAC_WEIGHT_CB_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_CB_1 = 0x1b8c # macro
|
|
regSE_CAC_WEIGHT_CB_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_CB_2 = 0x1b8d # macro
|
|
regSE_CAC_WEIGHT_CB_2_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_CB_3 = 0x1b8e # macro
|
|
regSE_CAC_WEIGHT_CB_3_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_CB_4 = 0x1b8f # macro
|
|
regSE_CAC_WEIGHT_CB_4_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_CB_5 = 0x1b90 # macro
|
|
regSE_CAC_WEIGHT_CB_5_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_CB_6 = 0x1b91 # macro
|
|
regSE_CAC_WEIGHT_CB_6_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_CB_7 = 0x1b92 # macro
|
|
regSE_CAC_WEIGHT_CB_7_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_CB_8 = 0x1b93 # macro
|
|
regSE_CAC_WEIGHT_CB_8_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_CB_9 = 0x1b94 # macro
|
|
regSE_CAC_WEIGHT_CB_9_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_CB_10 = 0x1b95 # macro
|
|
regSE_CAC_WEIGHT_CB_10_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_CB_11 = 0x1b96 # macro
|
|
regSE_CAC_WEIGHT_CB_11_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_DB_0 = 0x1b97 # macro
|
|
regSE_CAC_WEIGHT_DB_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_DB_1 = 0x1b98 # macro
|
|
regSE_CAC_WEIGHT_DB_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_DB_2 = 0x1b99 # macro
|
|
regSE_CAC_WEIGHT_DB_2_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_DB_3 = 0x1b9a # macro
|
|
regSE_CAC_WEIGHT_DB_3_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_DB_4 = 0x1b9b # macro
|
|
regSE_CAC_WEIGHT_DB_4_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_RMI_0 = 0x1b9c # macro
|
|
regSE_CAC_WEIGHT_RMI_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_RMI_1 = 0x1b9d # macro
|
|
regSE_CAC_WEIGHT_RMI_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SX_0 = 0x1b9e # macro
|
|
regSE_CAC_WEIGHT_SX_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SXRB_0 = 0x1b9f # macro
|
|
regSE_CAC_WEIGHT_SXRB_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_UTCL1_0 = 0x1ba0 # macro
|
|
regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_GL1C_0 = 0x1ba1 # macro
|
|
regSE_CAC_WEIGHT_GL1C_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_GL1C_1 = 0x1ba2 # macro
|
|
regSE_CAC_WEIGHT_GL1C_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_GL1C_2 = 0x1ba3 # macro
|
|
regSE_CAC_WEIGHT_GL1C_2_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SPI_0 = 0x1ba4 # macro
|
|
regSE_CAC_WEIGHT_SPI_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SPI_1 = 0x1ba5 # macro
|
|
regSE_CAC_WEIGHT_SPI_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SPI_2 = 0x1ba6 # macro
|
|
regSE_CAC_WEIGHT_SPI_2_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_PC_0 = 0x1ba7 # macro
|
|
regSE_CAC_WEIGHT_PC_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_PA_0 = 0x1ba8 # macro
|
|
regSE_CAC_WEIGHT_PA_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_PA_1 = 0x1ba9 # macro
|
|
regSE_CAC_WEIGHT_PA_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_PA_2 = 0x1baa # macro
|
|
regSE_CAC_WEIGHT_PA_2_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_PA_3 = 0x1bab # macro
|
|
regSE_CAC_WEIGHT_PA_3_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SC_0 = 0x1bac # macro
|
|
regSE_CAC_WEIGHT_SC_0_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SC_1 = 0x1bad # macro
|
|
regSE_CAC_WEIGHT_SC_1_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SC_2 = 0x1bae # macro
|
|
regSE_CAC_WEIGHT_SC_2_BASE_IDX = 1 # macro
|
|
regSE_CAC_WEIGHT_SC_3 = 0x1baf # macro
|
|
regSE_CAC_WEIGHT_SC_3_BASE_IDX = 1 # macro
|
|
regSE_CAC_WINDOW_AGGR_VALUE = 0x1bb0 # macro
|
|
regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX = 1 # macro
|
|
regSE_CAC_WINDOW_GFXCLK_CYCLE = 0x1bb1 # macro
|
|
regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX = 1 # macro
|
|
regSE_CAC_IND_INDEX = 0x1bce # macro
|
|
regSE_CAC_IND_INDEX_BASE_IDX = 1 # macro
|
|
regSE_CAC_IND_DATA = 0x1bcf # macro
|
|
regSE_CAC_IND_DATA_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_0 = 0x1c00 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_1 = 0x1c01 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_2 = 0x1c02 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_3 = 0x1c03 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_4 = 0x1c04 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_5 = 0x1c05 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_6 = 0x1c06 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_7 = 0x1c07 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_8 = 0x1c08 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_9 = 0x1c09 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_10 = 0x1c0a # macro
|
|
regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_11 = 0x1c0b # macro
|
|
regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_12 = 0x1c0c # macro
|
|
regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_13 = 0x1c0d # macro
|
|
regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_14 = 0x1c0e # macro
|
|
regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_CU_15 = 0x1c0f # macro
|
|
regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_0 = 0x1c10 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_1 = 0x1c11 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_2 = 0x1c12 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_3 = 0x1c13 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_4 = 0x1c14 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_5 = 0x1c15 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_6 = 0x1c16 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_7 = 0x1c17 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_8 = 0x1c18 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_9 = 0x1c19 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_10 = 0x1c1a # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_11 = 0x1c1b # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_12 = 0x1c1c # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_13 = 0x1c1d # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_14 = 0x1c1e # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX = 1 # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_15 = 0x1c1f # macro
|
|
regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX = 1 # macro
|
|
regCP_EOP_DONE_ADDR_LO = 0x2000 # macro
|
|
regCP_EOP_DONE_ADDR_LO_BASE_IDX = 1 # macro
|
|
regCP_EOP_DONE_ADDR_HI = 0x2001 # macro
|
|
regCP_EOP_DONE_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_EOP_DONE_DATA_LO = 0x2002 # macro
|
|
regCP_EOP_DONE_DATA_LO_BASE_IDX = 1 # macro
|
|
regCP_EOP_DONE_DATA_HI = 0x2003 # macro
|
|
regCP_EOP_DONE_DATA_HI_BASE_IDX = 1 # macro
|
|
regCP_EOP_LAST_FENCE_LO = 0x2004 # macro
|
|
regCP_EOP_LAST_FENCE_LO_BASE_IDX = 1 # macro
|
|
regCP_EOP_LAST_FENCE_HI = 0x2005 # macro
|
|
regCP_EOP_LAST_FENCE_HI_BASE_IDX = 1 # macro
|
|
regCP_PIPE_STATS_ADDR_LO = 0x2018 # macro
|
|
regCP_PIPE_STATS_ADDR_LO_BASE_IDX = 1 # macro
|
|
regCP_PIPE_STATS_ADDR_HI = 0x2019 # macro
|
|
regCP_PIPE_STATS_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_VGT_IAVERT_COUNT_LO = 0x201a # macro
|
|
regCP_VGT_IAVERT_COUNT_LO_BASE_IDX = 1 # macro
|
|
regCP_VGT_IAVERT_COUNT_HI = 0x201b # macro
|
|
regCP_VGT_IAVERT_COUNT_HI_BASE_IDX = 1 # macro
|
|
regCP_VGT_IAPRIM_COUNT_LO = 0x201c # macro
|
|
regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX = 1 # macro
|
|
regCP_VGT_IAPRIM_COUNT_HI = 0x201d # macro
|
|
regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX = 1 # macro
|
|
regCP_VGT_GSPRIM_COUNT_LO = 0x201e # macro
|
|
regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX = 1 # macro
|
|
regCP_VGT_GSPRIM_COUNT_HI = 0x201f # macro
|
|
regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX = 1 # macro
|
|
regCP_VGT_VSINVOC_COUNT_LO = 0x2020 # macro
|
|
regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX = 1 # macro
|
|
regCP_VGT_VSINVOC_COUNT_HI = 0x2021 # macro
|
|
regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX = 1 # macro
|
|
regCP_VGT_GSINVOC_COUNT_LO = 0x2022 # macro
|
|
regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX = 1 # macro
|
|
regCP_VGT_GSINVOC_COUNT_HI = 0x2023 # macro
|
|
regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX = 1 # macro
|
|
regCP_VGT_HSINVOC_COUNT_LO = 0x2024 # macro
|
|
regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX = 1 # macro
|
|
regCP_VGT_HSINVOC_COUNT_HI = 0x2025 # macro
|
|
regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX = 1 # macro
|
|
regCP_VGT_DSINVOC_COUNT_LO = 0x2026 # macro
|
|
regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX = 1 # macro
|
|
regCP_VGT_DSINVOC_COUNT_HI = 0x2027 # macro
|
|
regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX = 1 # macro
|
|
regCP_PA_CINVOC_COUNT_LO = 0x2028 # macro
|
|
regCP_PA_CINVOC_COUNT_LO_BASE_IDX = 1 # macro
|
|
regCP_PA_CINVOC_COUNT_HI = 0x2029 # macro
|
|
regCP_PA_CINVOC_COUNT_HI_BASE_IDX = 1 # macro
|
|
regCP_PA_CPRIM_COUNT_LO = 0x202a # macro
|
|
regCP_PA_CPRIM_COUNT_LO_BASE_IDX = 1 # macro
|
|
regCP_PA_CPRIM_COUNT_HI = 0x202b # macro
|
|
regCP_PA_CPRIM_COUNT_HI_BASE_IDX = 1 # macro
|
|
regCP_SC_PSINVOC_COUNT0_LO = 0x202c # macro
|
|
regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX = 1 # macro
|
|
regCP_SC_PSINVOC_COUNT0_HI = 0x202d # macro
|
|
regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX = 1 # macro
|
|
regCP_SC_PSINVOC_COUNT1_LO = 0x202e # macro
|
|
regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX = 1 # macro
|
|
regCP_SC_PSINVOC_COUNT1_HI = 0x202f # macro
|
|
regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX = 1 # macro
|
|
regCP_VGT_CSINVOC_COUNT_LO = 0x2030 # macro
|
|
regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX = 1 # macro
|
|
regCP_VGT_CSINVOC_COUNT_HI = 0x2031 # macro
|
|
regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX = 1 # macro
|
|
regCP_VGT_ASINVOC_COUNT_LO = 0x2032 # macro
|
|
regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX = 1 # macro
|
|
regCP_VGT_ASINVOC_COUNT_HI = 0x2033 # macro
|
|
regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX = 1 # macro
|
|
regCP_PIPE_STATS_CONTROL = 0x203d # macro
|
|
regCP_PIPE_STATS_CONTROL_BASE_IDX = 1 # macro
|
|
regSCRATCH_REG0 = 0x2040 # macro
|
|
regSCRATCH_REG0_BASE_IDX = 1 # macro
|
|
regSCRATCH_REG1 = 0x2041 # macro
|
|
regSCRATCH_REG1_BASE_IDX = 1 # macro
|
|
regSCRATCH_REG2 = 0x2042 # macro
|
|
regSCRATCH_REG2_BASE_IDX = 1 # macro
|
|
regSCRATCH_REG3 = 0x2043 # macro
|
|
regSCRATCH_REG3_BASE_IDX = 1 # macro
|
|
regSCRATCH_REG4 = 0x2044 # macro
|
|
regSCRATCH_REG4_BASE_IDX = 1 # macro
|
|
regSCRATCH_REG5 = 0x2045 # macro
|
|
regSCRATCH_REG5_BASE_IDX = 1 # macro
|
|
regSCRATCH_REG6 = 0x2046 # macro
|
|
regSCRATCH_REG6_BASE_IDX = 1 # macro
|
|
regSCRATCH_REG7 = 0x2047 # macro
|
|
regSCRATCH_REG7_BASE_IDX = 1 # macro
|
|
regSCRATCH_REG_ATOMIC = 0x2048 # macro
|
|
regSCRATCH_REG_ATOMIC_BASE_IDX = 1 # macro
|
|
regSCRATCH_REG_CMPSWAP_ATOMIC = 0x2048 # macro
|
|
regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX = 1 # macro
|
|
regCP_APPEND_DDID_CNT = 0x204b # macro
|
|
regCP_APPEND_DDID_CNT_BASE_IDX = 1 # macro
|
|
regCP_APPEND_DATA_HI = 0x204c # macro
|
|
regCP_APPEND_DATA_HI_BASE_IDX = 1 # macro
|
|
regCP_APPEND_LAST_CS_FENCE_HI = 0x204d # macro
|
|
regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX = 1 # macro
|
|
regCP_APPEND_LAST_PS_FENCE_HI = 0x204e # macro
|
|
regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX = 1 # macro
|
|
regCP_PFP_ATOMIC_PREOP_LO = 0x2052 # macro
|
|
regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro
|
|
regCP_PFP_ATOMIC_PREOP_HI = 0x2053 # macro
|
|
regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro
|
|
regCP_PFP_GDS_ATOMIC0_PREOP_LO = 0x2054 # macro
|
|
regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro
|
|
regCP_PFP_GDS_ATOMIC0_PREOP_HI = 0x2055 # macro
|
|
regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro
|
|
regCP_PFP_GDS_ATOMIC1_PREOP_LO = 0x2056 # macro
|
|
regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro
|
|
regCP_PFP_GDS_ATOMIC1_PREOP_HI = 0x2057 # macro
|
|
regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro
|
|
regCP_APPEND_ADDR_LO = 0x2058 # macro
|
|
regCP_APPEND_ADDR_LO_BASE_IDX = 1 # macro
|
|
regCP_APPEND_ADDR_HI = 0x2059 # macro
|
|
regCP_APPEND_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_APPEND_DATA = 0x205a # macro
|
|
regCP_APPEND_DATA_BASE_IDX = 1 # macro
|
|
regCP_APPEND_DATA_LO = 0x205a # macro
|
|
regCP_APPEND_DATA_LO_BASE_IDX = 1 # macro
|
|
regCP_APPEND_LAST_CS_FENCE = 0x205b # macro
|
|
regCP_APPEND_LAST_CS_FENCE_BASE_IDX = 1 # macro
|
|
regCP_APPEND_LAST_CS_FENCE_LO = 0x205b # macro
|
|
regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX = 1 # macro
|
|
regCP_APPEND_LAST_PS_FENCE = 0x205c # macro
|
|
regCP_APPEND_LAST_PS_FENCE_BASE_IDX = 1 # macro
|
|
regCP_APPEND_LAST_PS_FENCE_LO = 0x205c # macro
|
|
regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX = 1 # macro
|
|
regCP_ATOMIC_PREOP_LO = 0x205d # macro
|
|
regCP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro
|
|
regCP_ME_ATOMIC_PREOP_LO = 0x205d # macro
|
|
regCP_ME_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro
|
|
regCP_ATOMIC_PREOP_HI = 0x205e # macro
|
|
regCP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro
|
|
regCP_ME_ATOMIC_PREOP_HI = 0x205e # macro
|
|
regCP_ME_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro
|
|
regCP_GDS_ATOMIC0_PREOP_LO = 0x205f # macro
|
|
regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro
|
|
regCP_ME_GDS_ATOMIC0_PREOP_LO = 0x205f # macro
|
|
regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro
|
|
regCP_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro
|
|
regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro
|
|
regCP_ME_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro
|
|
regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro
|
|
regCP_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro
|
|
regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro
|
|
regCP_ME_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro
|
|
regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro
|
|
regCP_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro
|
|
regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro
|
|
regCP_ME_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro
|
|
regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro
|
|
regCP_ME_MC_WADDR_LO = 0x2069 # macro
|
|
regCP_ME_MC_WADDR_LO_BASE_IDX = 1 # macro
|
|
regCP_ME_MC_WADDR_HI = 0x206a # macro
|
|
regCP_ME_MC_WADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_ME_MC_WDATA_LO = 0x206b # macro
|
|
regCP_ME_MC_WDATA_LO_BASE_IDX = 1 # macro
|
|
regCP_ME_MC_WDATA_HI = 0x206c # macro
|
|
regCP_ME_MC_WDATA_HI_BASE_IDX = 1 # macro
|
|
regCP_ME_MC_RADDR_LO = 0x206d # macro
|
|
regCP_ME_MC_RADDR_LO_BASE_IDX = 1 # macro
|
|
regCP_ME_MC_RADDR_HI = 0x206e # macro
|
|
regCP_ME_MC_RADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_SEM_WAIT_TIMER = 0x206f # macro
|
|
regCP_SEM_WAIT_TIMER_BASE_IDX = 1 # macro
|
|
regCP_SIG_SEM_ADDR_LO = 0x2070 # macro
|
|
regCP_SIG_SEM_ADDR_LO_BASE_IDX = 1 # macro
|
|
regCP_SIG_SEM_ADDR_HI = 0x2071 # macro
|
|
regCP_SIG_SEM_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_WAIT_REG_MEM_TIMEOUT = 0x2074 # macro
|
|
regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX = 1 # macro
|
|
regCP_WAIT_SEM_ADDR_LO = 0x2075 # macro
|
|
regCP_WAIT_SEM_ADDR_LO_BASE_IDX = 1 # macro
|
|
regCP_WAIT_SEM_ADDR_HI = 0x2076 # macro
|
|
regCP_WAIT_SEM_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_DMA_PFP_CONTROL = 0x2077 # macro
|
|
regCP_DMA_PFP_CONTROL_BASE_IDX = 1 # macro
|
|
regCP_DMA_ME_CONTROL = 0x2078 # macro
|
|
regCP_DMA_ME_CONTROL_BASE_IDX = 1 # macro
|
|
regCP_DMA_ME_SRC_ADDR = 0x2080 # macro
|
|
regCP_DMA_ME_SRC_ADDR_BASE_IDX = 1 # macro
|
|
regCP_DMA_ME_SRC_ADDR_HI = 0x2081 # macro
|
|
regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_DMA_ME_DST_ADDR = 0x2082 # macro
|
|
regCP_DMA_ME_DST_ADDR_BASE_IDX = 1 # macro
|
|
regCP_DMA_ME_DST_ADDR_HI = 0x2083 # macro
|
|
regCP_DMA_ME_DST_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_DMA_ME_COMMAND = 0x2084 # macro
|
|
regCP_DMA_ME_COMMAND_BASE_IDX = 1 # macro
|
|
regCP_DMA_PFP_SRC_ADDR = 0x2085 # macro
|
|
regCP_DMA_PFP_SRC_ADDR_BASE_IDX = 1 # macro
|
|
regCP_DMA_PFP_SRC_ADDR_HI = 0x2086 # macro
|
|
regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_DMA_PFP_DST_ADDR = 0x2087 # macro
|
|
regCP_DMA_PFP_DST_ADDR_BASE_IDX = 1 # macro
|
|
regCP_DMA_PFP_DST_ADDR_HI = 0x2088 # macro
|
|
regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_DMA_PFP_COMMAND = 0x2089 # macro
|
|
regCP_DMA_PFP_COMMAND_BASE_IDX = 1 # macro
|
|
regCP_DMA_CNTL = 0x208a # macro
|
|
regCP_DMA_CNTL_BASE_IDX = 1 # macro
|
|
regCP_DMA_READ_TAGS = 0x208b # macro
|
|
regCP_DMA_READ_TAGS_BASE_IDX = 1 # macro
|
|
regCP_PFP_IB_CONTROL = 0x208d # macro
|
|
regCP_PFP_IB_CONTROL_BASE_IDX = 1 # macro
|
|
regCP_PFP_LOAD_CONTROL = 0x208e # macro
|
|
regCP_PFP_LOAD_CONTROL_BASE_IDX = 1 # macro
|
|
regCP_SCRATCH_INDEX = 0x208f # macro
|
|
regCP_SCRATCH_INDEX_BASE_IDX = 1 # macro
|
|
regCP_SCRATCH_DATA = 0x2090 # macro
|
|
regCP_SCRATCH_DATA_BASE_IDX = 1 # macro
|
|
regCP_RB_OFFSET = 0x2091 # macro
|
|
regCP_RB_OFFSET_BASE_IDX = 1 # macro
|
|
regCP_IB2_OFFSET = 0x2093 # macro
|
|
regCP_IB2_OFFSET_BASE_IDX = 1 # macro
|
|
regCP_IB2_PREAMBLE_BEGIN = 0x2096 # macro
|
|
regCP_IB2_PREAMBLE_BEGIN_BASE_IDX = 1 # macro
|
|
regCP_IB2_PREAMBLE_END = 0x2097 # macro
|
|
regCP_IB2_PREAMBLE_END_BASE_IDX = 1 # macro
|
|
regCP_DMA_ME_CMD_ADDR_LO = 0x209c # macro
|
|
regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX = 1 # macro
|
|
regCP_DMA_ME_CMD_ADDR_HI = 0x209d # macro
|
|
regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_DMA_PFP_CMD_ADDR_LO = 0x209e # macro
|
|
regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX = 1 # macro
|
|
regCP_DMA_PFP_CMD_ADDR_HI = 0x209f # macro
|
|
regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_APPEND_CMD_ADDR_LO = 0x20a0 # macro
|
|
regCP_APPEND_CMD_ADDR_LO_BASE_IDX = 1 # macro
|
|
regCP_APPEND_CMD_ADDR_HI = 0x20a1 # macro
|
|
regCP_APPEND_CMD_ADDR_HI_BASE_IDX = 1 # macro
|
|
regUCONFIG_RESERVED_REG0 = 0x20a2 # macro
|
|
regUCONFIG_RESERVED_REG0_BASE_IDX = 1 # macro
|
|
regUCONFIG_RESERVED_REG1 = 0x20a3 # macro
|
|
regUCONFIG_RESERVED_REG1_BASE_IDX = 1 # macro
|
|
regCP_PA_MSPRIM_COUNT_LO = 0x20a4 # macro
|
|
regCP_PA_MSPRIM_COUNT_LO_BASE_IDX = 1 # macro
|
|
regCP_PA_MSPRIM_COUNT_HI = 0x20a5 # macro
|
|
regCP_PA_MSPRIM_COUNT_HI_BASE_IDX = 1 # macro
|
|
regCP_GE_MSINVOC_COUNT_LO = 0x20a6 # macro
|
|
regCP_GE_MSINVOC_COUNT_LO_BASE_IDX = 1 # macro
|
|
regCP_GE_MSINVOC_COUNT_HI = 0x20a7 # macro
|
|
regCP_GE_MSINVOC_COUNT_HI_BASE_IDX = 1 # macro
|
|
regCP_IB1_CMD_BUFSZ = 0x20c0 # macro
|
|
regCP_IB1_CMD_BUFSZ_BASE_IDX = 1 # macro
|
|
regCP_IB2_CMD_BUFSZ = 0x20c1 # macro
|
|
regCP_IB2_CMD_BUFSZ_BASE_IDX = 1 # macro
|
|
regCP_ST_CMD_BUFSZ = 0x20c2 # macro
|
|
regCP_ST_CMD_BUFSZ_BASE_IDX = 1 # macro
|
|
regCP_IB1_BASE_LO = 0x20cc # macro
|
|
regCP_IB1_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_IB1_BASE_HI = 0x20cd # macro
|
|
regCP_IB1_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_IB1_BUFSZ = 0x20ce # macro
|
|
regCP_IB1_BUFSZ_BASE_IDX = 1 # macro
|
|
regCP_IB2_BASE_LO = 0x20cf # macro
|
|
regCP_IB2_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_IB2_BASE_HI = 0x20d0 # macro
|
|
regCP_IB2_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_IB2_BUFSZ = 0x20d1 # macro
|
|
regCP_IB2_BUFSZ_BASE_IDX = 1 # macro
|
|
regCP_ST_BASE_LO = 0x20d2 # macro
|
|
regCP_ST_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_ST_BASE_HI = 0x20d3 # macro
|
|
regCP_ST_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_ST_BUFSZ = 0x20d4 # macro
|
|
regCP_ST_BUFSZ_BASE_IDX = 1 # macro
|
|
regCP_EOP_DONE_EVENT_CNTL = 0x20d5 # macro
|
|
regCP_EOP_DONE_EVENT_CNTL_BASE_IDX = 1 # macro
|
|
regCP_EOP_DONE_DATA_CNTL = 0x20d6 # macro
|
|
regCP_EOP_DONE_DATA_CNTL_BASE_IDX = 1 # macro
|
|
regCP_EOP_DONE_CNTX_ID = 0x20d7 # macro
|
|
regCP_EOP_DONE_CNTX_ID_BASE_IDX = 1 # macro
|
|
regCP_DB_BASE_LO = 0x20d8 # macro
|
|
regCP_DB_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_DB_BASE_HI = 0x20d9 # macro
|
|
regCP_DB_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_DB_BUFSZ = 0x20da # macro
|
|
regCP_DB_BUFSZ_BASE_IDX = 1 # macro
|
|
regCP_DB_CMD_BUFSZ = 0x20db # macro
|
|
regCP_DB_CMD_BUFSZ_BASE_IDX = 1 # macro
|
|
regCP_PFP_COMPLETION_STATUS = 0x20ec # macro
|
|
regCP_PFP_COMPLETION_STATUS_BASE_IDX = 1 # macro
|
|
regCP_PRED_NOT_VISIBLE = 0x20ee # macro
|
|
regCP_PRED_NOT_VISIBLE_BASE_IDX = 1 # macro
|
|
regCP_PFP_METADATA_BASE_ADDR = 0x20f0 # macro
|
|
regCP_PFP_METADATA_BASE_ADDR_BASE_IDX = 1 # macro
|
|
regCP_PFP_METADATA_BASE_ADDR_HI = 0x20f1 # macro
|
|
regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_DRAW_INDX_INDR_ADDR = 0x20f4 # macro
|
|
regCP_DRAW_INDX_INDR_ADDR_BASE_IDX = 1 # macro
|
|
regCP_DRAW_INDX_INDR_ADDR_HI = 0x20f5 # macro
|
|
regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_DISPATCH_INDR_ADDR = 0x20f6 # macro
|
|
regCP_DISPATCH_INDR_ADDR_BASE_IDX = 1 # macro
|
|
regCP_DISPATCH_INDR_ADDR_HI = 0x20f7 # macro
|
|
regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_INDEX_BASE_ADDR = 0x20f8 # macro
|
|
regCP_INDEX_BASE_ADDR_BASE_IDX = 1 # macro
|
|
regCP_INDEX_BASE_ADDR_HI = 0x20f9 # macro
|
|
regCP_INDEX_BASE_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_INDEX_TYPE = 0x20fa # macro
|
|
regCP_INDEX_TYPE_BASE_IDX = 1 # macro
|
|
regCP_GDS_BKUP_ADDR = 0x20fb # macro
|
|
regCP_GDS_BKUP_ADDR_BASE_IDX = 1 # macro
|
|
regCP_GDS_BKUP_ADDR_HI = 0x20fc # macro
|
|
regCP_GDS_BKUP_ADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_SAMPLE_STATUS = 0x20fd # macro
|
|
regCP_SAMPLE_STATUS_BASE_IDX = 1 # macro
|
|
regCP_ME_COHER_CNTL = 0x20fe # macro
|
|
regCP_ME_COHER_CNTL_BASE_IDX = 1 # macro
|
|
regCP_ME_COHER_SIZE = 0x20ff # macro
|
|
regCP_ME_COHER_SIZE_BASE_IDX = 1 # macro
|
|
regCP_ME_COHER_SIZE_HI = 0x2100 # macro
|
|
regCP_ME_COHER_SIZE_HI_BASE_IDX = 1 # macro
|
|
regCP_ME_COHER_BASE = 0x2101 # macro
|
|
regCP_ME_COHER_BASE_BASE_IDX = 1 # macro
|
|
regCP_ME_COHER_BASE_HI = 0x2102 # macro
|
|
regCP_ME_COHER_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_ME_COHER_STATUS = 0x2103 # macro
|
|
regCP_ME_COHER_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPM_PERF_COUNT_0 = 0x2140 # macro
|
|
regRLC_GPM_PERF_COUNT_0_BASE_IDX = 1 # macro
|
|
regRLC_GPM_PERF_COUNT_1 = 0x2141 # macro
|
|
regRLC_GPM_PERF_COUNT_1_BASE_IDX = 1 # macro
|
|
regGRBM_GFX_INDEX = 0x2200 # macro
|
|
regGRBM_GFX_INDEX_BASE_IDX = 1 # macro
|
|
regVGT_PRIMITIVE_TYPE = 0x2242 # macro
|
|
regVGT_PRIMITIVE_TYPE_BASE_IDX = 1 # macro
|
|
regVGT_INDEX_TYPE = 0x2243 # macro
|
|
regVGT_INDEX_TYPE_BASE_IDX = 1 # macro
|
|
regGE_MIN_VTX_INDX = 0x2249 # macro
|
|
regGE_MIN_VTX_INDX_BASE_IDX = 1 # macro
|
|
regGE_INDX_OFFSET = 0x224a # macro
|
|
regGE_INDX_OFFSET_BASE_IDX = 1 # macro
|
|
regGE_MULTI_PRIM_IB_RESET_EN = 0x224b # macro
|
|
regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX = 1 # macro
|
|
regVGT_NUM_INDICES = 0x224c # macro
|
|
regVGT_NUM_INDICES_BASE_IDX = 1 # macro
|
|
regVGT_NUM_INSTANCES = 0x224d # macro
|
|
regVGT_NUM_INSTANCES_BASE_IDX = 1 # macro
|
|
regVGT_TF_RING_SIZE = 0x224e # macro
|
|
regVGT_TF_RING_SIZE_BASE_IDX = 1 # macro
|
|
regVGT_HS_OFFCHIP_PARAM = 0x224f # macro
|
|
regVGT_HS_OFFCHIP_PARAM_BASE_IDX = 1 # macro
|
|
regVGT_TF_MEMORY_BASE = 0x2250 # macro
|
|
regVGT_TF_MEMORY_BASE_BASE_IDX = 1 # macro
|
|
regGE_MAX_VTX_INDX = 0x2259 # macro
|
|
regGE_MAX_VTX_INDX_BASE_IDX = 1 # macro
|
|
regVGT_INSTANCE_BASE_ID = 0x225a # macro
|
|
regVGT_INSTANCE_BASE_ID_BASE_IDX = 1 # macro
|
|
regGE_CNTL = 0x225b # macro
|
|
regGE_CNTL_BASE_IDX = 1 # macro
|
|
regGE_USER_VGPR1 = 0x225c # macro
|
|
regGE_USER_VGPR1_BASE_IDX = 1 # macro
|
|
regGE_USER_VGPR2 = 0x225d # macro
|
|
regGE_USER_VGPR2_BASE_IDX = 1 # macro
|
|
regGE_USER_VGPR3 = 0x225e # macro
|
|
regGE_USER_VGPR3_BASE_IDX = 1 # macro
|
|
regGE_STEREO_CNTL = 0x225f # macro
|
|
regGE_STEREO_CNTL_BASE_IDX = 1 # macro
|
|
regGE_PC_ALLOC = 0x2260 # macro
|
|
regGE_PC_ALLOC_BASE_IDX = 1 # macro
|
|
regVGT_TF_MEMORY_BASE_HI = 0x2261 # macro
|
|
regVGT_TF_MEMORY_BASE_HI_BASE_IDX = 1 # macro
|
|
regGE_USER_VGPR_EN = 0x2262 # macro
|
|
regGE_USER_VGPR_EN_BASE_IDX = 1 # macro
|
|
regGE_GS_FAST_LAUNCH_WG_DIM = 0x2264 # macro
|
|
regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX = 1 # macro
|
|
regGE_GS_FAST_LAUNCH_WG_DIM_1 = 0x2265 # macro
|
|
regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX = 1 # macro
|
|
regVGT_GS_OUT_PRIM_TYPE = 0x2266 # macro
|
|
regVGT_GS_OUT_PRIM_TYPE_BASE_IDX = 1 # macro
|
|
regPA_SU_LINE_STIPPLE_VALUE = 0x2280 # macro
|
|
regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX = 1 # macro
|
|
regPA_SC_LINE_STIPPLE_STATE = 0x2281 # macro
|
|
regPA_SC_LINE_STIPPLE_STATE_BASE_IDX = 1 # macro
|
|
regPA_SC_SCREEN_EXTENT_MIN_0 = 0x2284 # macro
|
|
regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX = 1 # macro
|
|
regPA_SC_SCREEN_EXTENT_MAX_0 = 0x2285 # macro
|
|
regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX = 1 # macro
|
|
regPA_SC_SCREEN_EXTENT_MIN_1 = 0x2286 # macro
|
|
regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX = 1 # macro
|
|
regPA_SC_SCREEN_EXTENT_MAX_1 = 0x228b # macro
|
|
regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX = 1 # macro
|
|
regPA_SC_P3D_TRAP_SCREEN_HV_EN = 0x22a0 # macro
|
|
regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro
|
|
regPA_SC_P3D_TRAP_SCREEN_H = 0x22a1 # macro
|
|
regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro
|
|
regPA_SC_P3D_TRAP_SCREEN_V = 0x22a2 # macro
|
|
regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro
|
|
regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE = 0x22a3 # macro
|
|
regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro
|
|
regPA_SC_P3D_TRAP_SCREEN_COUNT = 0x22a4 # macro
|
|
regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro
|
|
regPA_SC_HP3D_TRAP_SCREEN_HV_EN = 0x22a8 # macro
|
|
regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro
|
|
regPA_SC_HP3D_TRAP_SCREEN_H = 0x22a9 # macro
|
|
regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro
|
|
regPA_SC_HP3D_TRAP_SCREEN_V = 0x22aa # macro
|
|
regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro
|
|
regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE = 0x22ab # macro
|
|
regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro
|
|
regPA_SC_HP3D_TRAP_SCREEN_COUNT = 0x22ac # macro
|
|
regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro
|
|
regPA_SC_TRAP_SCREEN_HV_EN = 0x22b0 # macro
|
|
regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro
|
|
regPA_SC_TRAP_SCREEN_H = 0x22b1 # macro
|
|
regPA_SC_TRAP_SCREEN_H_BASE_IDX = 1 # macro
|
|
regPA_SC_TRAP_SCREEN_V = 0x22b2 # macro
|
|
regPA_SC_TRAP_SCREEN_V_BASE_IDX = 1 # macro
|
|
regPA_SC_TRAP_SCREEN_OCCURRENCE = 0x22b3 # macro
|
|
regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro
|
|
regPA_SC_TRAP_SCREEN_COUNT = 0x22b4 # macro
|
|
regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_0 = 0x2340 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_1 = 0x2341 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_2 = 0x2342 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_3 = 0x2343 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_4 = 0x2344 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_5 = 0x2345 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_6 = 0x2346 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_7 = 0x2347 # macro
|
|
regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX = 1 # macro
|
|
regSQC_CACHES = 0x2348 # macro
|
|
regSQC_CACHES_BASE_IDX = 1 # macro
|
|
regTA_CS_BC_BASE_ADDR = 0x2380 # macro
|
|
regTA_CS_BC_BASE_ADDR_BASE_IDX = 1 # macro
|
|
regTA_CS_BC_BASE_ADDR_HI = 0x2381 # macro
|
|
regTA_CS_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro
|
|
regDB_OCCLUSION_COUNT0_LOW = 0x23c0 # macro
|
|
regDB_OCCLUSION_COUNT0_LOW_BASE_IDX = 1 # macro
|
|
regDB_OCCLUSION_COUNT0_HI = 0x23c1 # macro
|
|
regDB_OCCLUSION_COUNT0_HI_BASE_IDX = 1 # macro
|
|
regDB_OCCLUSION_COUNT1_LOW = 0x23c2 # macro
|
|
regDB_OCCLUSION_COUNT1_LOW_BASE_IDX = 1 # macro
|
|
regDB_OCCLUSION_COUNT1_HI = 0x23c3 # macro
|
|
regDB_OCCLUSION_COUNT1_HI_BASE_IDX = 1 # macro
|
|
regDB_OCCLUSION_COUNT2_LOW = 0x23c4 # macro
|
|
regDB_OCCLUSION_COUNT2_LOW_BASE_IDX = 1 # macro
|
|
regDB_OCCLUSION_COUNT2_HI = 0x23c5 # macro
|
|
regDB_OCCLUSION_COUNT2_HI_BASE_IDX = 1 # macro
|
|
regDB_OCCLUSION_COUNT3_LOW = 0x23c6 # macro
|
|
regDB_OCCLUSION_COUNT3_LOW_BASE_IDX = 1 # macro
|
|
regDB_OCCLUSION_COUNT3_HI = 0x23c7 # macro
|
|
regDB_OCCLUSION_COUNT3_HI_BASE_IDX = 1 # macro
|
|
regGDS_RD_ADDR = 0x2400 # macro
|
|
regGDS_RD_ADDR_BASE_IDX = 1 # macro
|
|
regGDS_RD_DATA = 0x2401 # macro
|
|
regGDS_RD_DATA_BASE_IDX = 1 # macro
|
|
regGDS_RD_BURST_ADDR = 0x2402 # macro
|
|
regGDS_RD_BURST_ADDR_BASE_IDX = 1 # macro
|
|
regGDS_RD_BURST_COUNT = 0x2403 # macro
|
|
regGDS_RD_BURST_COUNT_BASE_IDX = 1 # macro
|
|
regGDS_RD_BURST_DATA = 0x2404 # macro
|
|
regGDS_RD_BURST_DATA_BASE_IDX = 1 # macro
|
|
regGDS_WR_ADDR = 0x2405 # macro
|
|
regGDS_WR_ADDR_BASE_IDX = 1 # macro
|
|
regGDS_WR_DATA = 0x2406 # macro
|
|
regGDS_WR_DATA_BASE_IDX = 1 # macro
|
|
regGDS_WR_BURST_ADDR = 0x2407 # macro
|
|
regGDS_WR_BURST_ADDR_BASE_IDX = 1 # macro
|
|
regGDS_WR_BURST_DATA = 0x2408 # macro
|
|
regGDS_WR_BURST_DATA_BASE_IDX = 1 # macro
|
|
regGDS_WRITE_COMPLETE = 0x2409 # macro
|
|
regGDS_WRITE_COMPLETE_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_CNTL = 0x240a # macro
|
|
regGDS_ATOM_CNTL_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_COMPLETE = 0x240b # macro
|
|
regGDS_ATOM_COMPLETE_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_BASE = 0x240c # macro
|
|
regGDS_ATOM_BASE_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_SIZE = 0x240d # macro
|
|
regGDS_ATOM_SIZE_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_OFFSET0 = 0x240e # macro
|
|
regGDS_ATOM_OFFSET0_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_OFFSET1 = 0x240f # macro
|
|
regGDS_ATOM_OFFSET1_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_DST = 0x2410 # macro
|
|
regGDS_ATOM_DST_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_OP = 0x2411 # macro
|
|
regGDS_ATOM_OP_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_SRC0 = 0x2412 # macro
|
|
regGDS_ATOM_SRC0_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_SRC0_U = 0x2413 # macro
|
|
regGDS_ATOM_SRC0_U_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_SRC1 = 0x2414 # macro
|
|
regGDS_ATOM_SRC1_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_SRC1_U = 0x2415 # macro
|
|
regGDS_ATOM_SRC1_U_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_READ0 = 0x2416 # macro
|
|
regGDS_ATOM_READ0_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_READ0_U = 0x2417 # macro
|
|
regGDS_ATOM_READ0_U_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_READ1 = 0x2418 # macro
|
|
regGDS_ATOM_READ1_BASE_IDX = 1 # macro
|
|
regGDS_ATOM_READ1_U = 0x2419 # macro
|
|
regGDS_ATOM_READ1_U_BASE_IDX = 1 # macro
|
|
regGDS_GWS_RESOURCE_CNTL = 0x241a # macro
|
|
regGDS_GWS_RESOURCE_CNTL_BASE_IDX = 1 # macro
|
|
regGDS_GWS_RESOURCE = 0x241b # macro
|
|
regGDS_GWS_RESOURCE_BASE_IDX = 1 # macro
|
|
regGDS_GWS_RESOURCE_CNT = 0x241c # macro
|
|
regGDS_GWS_RESOURCE_CNT_BASE_IDX = 1 # macro
|
|
regGDS_OA_CNTL = 0x241d # macro
|
|
regGDS_OA_CNTL_BASE_IDX = 1 # macro
|
|
regGDS_OA_COUNTER = 0x241e # macro
|
|
regGDS_OA_COUNTER_BASE_IDX = 1 # macro
|
|
regGDS_OA_ADDRESS = 0x241f # macro
|
|
regGDS_OA_ADDRESS_BASE_IDX = 1 # macro
|
|
regGDS_OA_INCDEC = 0x2420 # macro
|
|
regGDS_OA_INCDEC_BASE_IDX = 1 # macro
|
|
regGDS_OA_RING_SIZE = 0x2421 # macro
|
|
regGDS_OA_RING_SIZE_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_DWORDS_WRITTEN_0 = 0x2422 # macro
|
|
regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_DWORDS_WRITTEN_1 = 0x2423 # macro
|
|
regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_DWORDS_WRITTEN_2 = 0x2424 # macro
|
|
regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_DWORDS_WRITTEN_3 = 0x2425 # macro
|
|
regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX = 1 # macro
|
|
regGDS_GS_0 = 0x2426 # macro
|
|
regGDS_GS_0_BASE_IDX = 1 # macro
|
|
regGDS_GS_1 = 0x2427 # macro
|
|
regGDS_GS_1_BASE_IDX = 1 # macro
|
|
regGDS_GS_2 = 0x2428 # macro
|
|
regGDS_GS_2_BASE_IDX = 1 # macro
|
|
regGDS_GS_3 = 0x2429 # macro
|
|
regGDS_GS_3_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_0_LO = 0x242a # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_0_HI = 0x242b # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_0_LO = 0x242c # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_0_HI = 0x242d # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_1_LO = 0x242e # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_1_HI = 0x242f # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_1_LO = 0x2430 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_1_HI = 0x2431 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_2_LO = 0x2432 # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_2_HI = 0x2433 # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_2_LO = 0x2434 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_2_HI = 0x2435 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_3_LO = 0x2436 # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_3_HI = 0x2437 # macro
|
|
regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_3_LO = 0x2438 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX = 1 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_3_HI = 0x2439 # macro
|
|
regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX = 1 # macro
|
|
regSPI_CONFIG_CNTL = 0x2440 # macro
|
|
regSPI_CONFIG_CNTL_BASE_IDX = 1 # macro
|
|
regSPI_CONFIG_CNTL_1 = 0x2441 # macro
|
|
regSPI_CONFIG_CNTL_1_BASE_IDX = 1 # macro
|
|
regSPI_CONFIG_CNTL_2 = 0x2442 # macro
|
|
regSPI_CONFIG_CNTL_2_BASE_IDX = 1 # macro
|
|
regSPI_WAVE_LIMIT_CNTL = 0x2443 # macro
|
|
regSPI_WAVE_LIMIT_CNTL_BASE_IDX = 1 # macro
|
|
regSPI_GS_THROTTLE_CNTL1 = 0x2444 # macro
|
|
regSPI_GS_THROTTLE_CNTL1_BASE_IDX = 1 # macro
|
|
regSPI_GS_THROTTLE_CNTL2 = 0x2445 # macro
|
|
regSPI_GS_THROTTLE_CNTL2_BASE_IDX = 1 # macro
|
|
regSPI_ATTRIBUTE_RING_BASE = 0x2446 # macro
|
|
regSPI_ATTRIBUTE_RING_BASE_BASE_IDX = 1 # macro
|
|
regSPI_ATTRIBUTE_RING_SIZE = 0x2447 # macro
|
|
regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX = 1 # macro
|
|
regCP_MES_PRGRM_CNTR_START = 0x2800 # macro
|
|
regCP_MES_PRGRM_CNTR_START_BASE_IDX = 1 # macro
|
|
regCP_MES_INTR_ROUTINE_START = 0x2801 # macro
|
|
regCP_MES_INTR_ROUTINE_START_BASE_IDX = 1 # macro
|
|
regCP_MES_MTVEC_LO = 0x2801 # macro
|
|
regCP_MES_MTVEC_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_INTR_ROUTINE_START_HI = 0x2802 # macro
|
|
regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MTVEC_HI = 0x2802 # macro
|
|
regCP_MES_MTVEC_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_CNTL = 0x2807 # macro
|
|
regCP_MES_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_PIPE_PRIORITY_CNTS = 0x2808 # macro
|
|
regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX = 1 # macro
|
|
regCP_MES_PIPE0_PRIORITY = 0x2809 # macro
|
|
regCP_MES_PIPE0_PRIORITY_BASE_IDX = 1 # macro
|
|
regCP_MES_PIPE1_PRIORITY = 0x280a # macro
|
|
regCP_MES_PIPE1_PRIORITY_BASE_IDX = 1 # macro
|
|
regCP_MES_PIPE2_PRIORITY = 0x280b # macro
|
|
regCP_MES_PIPE2_PRIORITY_BASE_IDX = 1 # macro
|
|
regCP_MES_PIPE3_PRIORITY = 0x280c # macro
|
|
regCP_MES_PIPE3_PRIORITY_BASE_IDX = 1 # macro
|
|
regCP_MES_HEADER_DUMP = 0x280d # macro
|
|
regCP_MES_HEADER_DUMP_BASE_IDX = 1 # macro
|
|
regCP_MES_MIE_LO = 0x280e # macro
|
|
regCP_MES_MIE_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MIE_HI = 0x280f # macro
|
|
regCP_MES_MIE_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT = 0x2810 # macro
|
|
regCP_MES_INTERRUPT_BASE_IDX = 1 # macro
|
|
regCP_MES_SCRATCH_INDEX = 0x2811 # macro
|
|
regCP_MES_SCRATCH_INDEX_BASE_IDX = 1 # macro
|
|
regCP_MES_SCRATCH_DATA = 0x2812 # macro
|
|
regCP_MES_SCRATCH_DATA_BASE_IDX = 1 # macro
|
|
regCP_MES_INSTR_PNTR = 0x2813 # macro
|
|
regCP_MES_INSTR_PNTR_BASE_IDX = 1 # macro
|
|
regCP_MES_MSCRATCH_HI = 0x2814 # macro
|
|
regCP_MES_MSCRATCH_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MSCRATCH_LO = 0x2815 # macro
|
|
regCP_MES_MSCRATCH_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MSTATUS_LO = 0x2816 # macro
|
|
regCP_MES_MSTATUS_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MSTATUS_HI = 0x2817 # macro
|
|
regCP_MES_MSTATUS_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MEPC_LO = 0x2818 # macro
|
|
regCP_MES_MEPC_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MEPC_HI = 0x2819 # macro
|
|
regCP_MES_MEPC_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MCAUSE_LO = 0x281a # macro
|
|
regCP_MES_MCAUSE_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MCAUSE_HI = 0x281b # macro
|
|
regCP_MES_MCAUSE_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MBADADDR_LO = 0x281c # macro
|
|
regCP_MES_MBADADDR_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MBADADDR_HI = 0x281d # macro
|
|
regCP_MES_MBADADDR_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MIP_LO = 0x281e # macro
|
|
regCP_MES_MIP_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MIP_HI = 0x281f # macro
|
|
regCP_MES_MIP_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_IC_OP_CNTL = 0x2820 # macro
|
|
regCP_MES_IC_OP_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_MCYCLE_LO = 0x2826 # macro
|
|
regCP_MES_MCYCLE_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MCYCLE_HI = 0x2827 # macro
|
|
regCP_MES_MCYCLE_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MTIME_LO = 0x2828 # macro
|
|
regCP_MES_MTIME_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MTIME_HI = 0x2829 # macro
|
|
regCP_MES_MTIME_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MINSTRET_LO = 0x282a # macro
|
|
regCP_MES_MINSTRET_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MINSTRET_HI = 0x282b # macro
|
|
regCP_MES_MINSTRET_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MISA_LO = 0x282c # macro
|
|
regCP_MES_MISA_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MISA_HI = 0x282d # macro
|
|
regCP_MES_MISA_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MVENDORID_LO = 0x282e # macro
|
|
regCP_MES_MVENDORID_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MVENDORID_HI = 0x282f # macro
|
|
regCP_MES_MVENDORID_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MARCHID_LO = 0x2830 # macro
|
|
regCP_MES_MARCHID_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MARCHID_HI = 0x2831 # macro
|
|
regCP_MES_MARCHID_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MIMPID_LO = 0x2832 # macro
|
|
regCP_MES_MIMPID_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MIMPID_HI = 0x2833 # macro
|
|
regCP_MES_MIMPID_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MHARTID_LO = 0x2834 # macro
|
|
regCP_MES_MHARTID_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MHARTID_HI = 0x2835 # macro
|
|
regCP_MES_MHARTID_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_BASE_CNTL = 0x2836 # macro
|
|
regCP_MES_DC_BASE_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_OP_CNTL = 0x2837 # macro
|
|
regCP_MES_DC_OP_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_MTIMECMP_LO = 0x2838 # macro
|
|
regCP_MES_MTIMECMP_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MTIMECMP_HI = 0x2839 # macro
|
|
regCP_MES_MTIMECMP_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_PROCESS_QUANTUM_PIPE0 = 0x283a # macro
|
|
regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX = 1 # macro
|
|
regCP_MES_PROCESS_QUANTUM_PIPE1 = 0x283b # macro
|
|
regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX = 1 # macro
|
|
regCP_MES_DOORBELL_CONTROL1 = 0x283c # macro
|
|
regCP_MES_DOORBELL_CONTROL1_BASE_IDX = 1 # macro
|
|
regCP_MES_DOORBELL_CONTROL2 = 0x283d # macro
|
|
regCP_MES_DOORBELL_CONTROL2_BASE_IDX = 1 # macro
|
|
regCP_MES_DOORBELL_CONTROL3 = 0x283e # macro
|
|
regCP_MES_DOORBELL_CONTROL3_BASE_IDX = 1 # macro
|
|
regCP_MES_DOORBELL_CONTROL4 = 0x283f # macro
|
|
regCP_MES_DOORBELL_CONTROL4_BASE_IDX = 1 # macro
|
|
regCP_MES_DOORBELL_CONTROL5 = 0x2840 # macro
|
|
regCP_MES_DOORBELL_CONTROL5_BASE_IDX = 1 # macro
|
|
regCP_MES_DOORBELL_CONTROL6 = 0x2841 # macro
|
|
regCP_MES_DOORBELL_CONTROL6_BASE_IDX = 1 # macro
|
|
regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR = 0x2842 # macro
|
|
regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX = 1 # macro
|
|
regCP_MES_GP0_LO = 0x2843 # macro
|
|
regCP_MES_GP0_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_GP0_HI = 0x2844 # macro
|
|
regCP_MES_GP0_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_GP1_LO = 0x2845 # macro
|
|
regCP_MES_GP1_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_GP1_HI = 0x2846 # macro
|
|
regCP_MES_GP1_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_GP2_LO = 0x2847 # macro
|
|
regCP_MES_GP2_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_GP2_HI = 0x2848 # macro
|
|
regCP_MES_GP2_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_GP3_LO = 0x2849 # macro
|
|
regCP_MES_GP3_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_GP3_HI = 0x284a # macro
|
|
regCP_MES_GP3_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_GP4_LO = 0x284b # macro
|
|
regCP_MES_GP4_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_GP4_HI = 0x284c # macro
|
|
regCP_MES_GP4_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_GP5_LO = 0x284d # macro
|
|
regCP_MES_GP5_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_GP5_HI = 0x284e # macro
|
|
regCP_MES_GP5_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_GP6_LO = 0x284f # macro
|
|
regCP_MES_GP6_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_GP6_HI = 0x2850 # macro
|
|
regCP_MES_GP6_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_GP7_LO = 0x2851 # macro
|
|
regCP_MES_GP7_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_GP7_HI = 0x2852 # macro
|
|
regCP_MES_GP7_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_GP8_LO = 0x2853 # macro
|
|
regCP_MES_GP8_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_GP8_HI = 0x2854 # macro
|
|
regCP_MES_GP8_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_GP9_LO = 0x2855 # macro
|
|
regCP_MES_GP9_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_GP9_HI = 0x2856 # macro
|
|
regCP_MES_GP9_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_LOCAL_BASE0_LO = 0x2883 # macro
|
|
regCP_MES_LOCAL_BASE0_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_LOCAL_BASE0_HI = 0x2884 # macro
|
|
regCP_MES_LOCAL_BASE0_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_LOCAL_MASK0_LO = 0x2885 # macro
|
|
regCP_MES_LOCAL_MASK0_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_LOCAL_MASK0_HI = 0x2886 # macro
|
|
regCP_MES_LOCAL_MASK0_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_LOCAL_APERTURE = 0x2887 # macro
|
|
regCP_MES_LOCAL_APERTURE_BASE_IDX = 1 # macro
|
|
regCP_MES_LOCAL_INSTR_BASE_LO = 0x2888 # macro
|
|
regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_LOCAL_INSTR_BASE_HI = 0x2889 # macro
|
|
regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_LOCAL_INSTR_MASK_LO = 0x288a # macro
|
|
regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_LOCAL_INSTR_MASK_HI = 0x288b # macro
|
|
regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_LOCAL_INSTR_APERTURE = 0x288c # macro
|
|
regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro
|
|
regCP_MES_LOCAL_SCRATCH_APERTURE = 0x288d # macro
|
|
regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro
|
|
regCP_MES_LOCAL_SCRATCH_BASE_LO = 0x288e # macro
|
|
regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_LOCAL_SCRATCH_BASE_HI = 0x288f # macro
|
|
regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_PERFCOUNT_CNTL = 0x2899 # macro
|
|
regCP_MES_PERFCOUNT_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_PENDING_INTERRUPT = 0x289a # macro
|
|
regCP_MES_PENDING_INTERRUPT_BASE_IDX = 1 # macro
|
|
regCP_MES_PRGRM_CNTR_START_HI = 0x289d # macro
|
|
regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_16 = 0x289f # macro
|
|
regCP_MES_INTERRUPT_DATA_16_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_17 = 0x28a0 # macro
|
|
regCP_MES_INTERRUPT_DATA_17_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_18 = 0x28a1 # macro
|
|
regCP_MES_INTERRUPT_DATA_18_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_19 = 0x28a2 # macro
|
|
regCP_MES_INTERRUPT_DATA_19_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_20 = 0x28a3 # macro
|
|
regCP_MES_INTERRUPT_DATA_20_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_21 = 0x28a4 # macro
|
|
regCP_MES_INTERRUPT_DATA_21_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_22 = 0x28a5 # macro
|
|
regCP_MES_INTERRUPT_DATA_22_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_23 = 0x28a6 # macro
|
|
regCP_MES_INTERRUPT_DATA_23_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_24 = 0x28a7 # macro
|
|
regCP_MES_INTERRUPT_DATA_24_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_25 = 0x28a8 # macro
|
|
regCP_MES_INTERRUPT_DATA_25_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_26 = 0x28a9 # macro
|
|
regCP_MES_INTERRUPT_DATA_26_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_27 = 0x28aa # macro
|
|
regCP_MES_INTERRUPT_DATA_27_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_28 = 0x28ab # macro
|
|
regCP_MES_INTERRUPT_DATA_28_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_29 = 0x28ac # macro
|
|
regCP_MES_INTERRUPT_DATA_29_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_30 = 0x28ad # macro
|
|
regCP_MES_INTERRUPT_DATA_30_BASE_IDX = 1 # macro
|
|
regCP_MES_INTERRUPT_DATA_31 = 0x28ae # macro
|
|
regCP_MES_INTERRUPT_DATA_31_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE0_BASE = 0x28af # macro
|
|
regCP_MES_DC_APERTURE0_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE0_MASK = 0x28b0 # macro
|
|
regCP_MES_DC_APERTURE0_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE0_CNTL = 0x28b1 # macro
|
|
regCP_MES_DC_APERTURE0_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE1_BASE = 0x28b2 # macro
|
|
regCP_MES_DC_APERTURE1_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE1_MASK = 0x28b3 # macro
|
|
regCP_MES_DC_APERTURE1_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE1_CNTL = 0x28b4 # macro
|
|
regCP_MES_DC_APERTURE1_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE2_BASE = 0x28b5 # macro
|
|
regCP_MES_DC_APERTURE2_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE2_MASK = 0x28b6 # macro
|
|
regCP_MES_DC_APERTURE2_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE2_CNTL = 0x28b7 # macro
|
|
regCP_MES_DC_APERTURE2_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE3_BASE = 0x28b8 # macro
|
|
regCP_MES_DC_APERTURE3_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE3_MASK = 0x28b9 # macro
|
|
regCP_MES_DC_APERTURE3_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE3_CNTL = 0x28ba # macro
|
|
regCP_MES_DC_APERTURE3_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE4_BASE = 0x28bb # macro
|
|
regCP_MES_DC_APERTURE4_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE4_MASK = 0x28bc # macro
|
|
regCP_MES_DC_APERTURE4_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE4_CNTL = 0x28bd # macro
|
|
regCP_MES_DC_APERTURE4_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE5_BASE = 0x28be # macro
|
|
regCP_MES_DC_APERTURE5_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE5_MASK = 0x28bf # macro
|
|
regCP_MES_DC_APERTURE5_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE5_CNTL = 0x28c0 # macro
|
|
regCP_MES_DC_APERTURE5_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE6_BASE = 0x28c1 # macro
|
|
regCP_MES_DC_APERTURE6_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE6_MASK = 0x28c2 # macro
|
|
regCP_MES_DC_APERTURE6_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE6_CNTL = 0x28c3 # macro
|
|
regCP_MES_DC_APERTURE6_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE7_BASE = 0x28c4 # macro
|
|
regCP_MES_DC_APERTURE7_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE7_MASK = 0x28c5 # macro
|
|
regCP_MES_DC_APERTURE7_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE7_CNTL = 0x28c6 # macro
|
|
regCP_MES_DC_APERTURE7_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE8_BASE = 0x28c7 # macro
|
|
regCP_MES_DC_APERTURE8_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE8_MASK = 0x28c8 # macro
|
|
regCP_MES_DC_APERTURE8_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE8_CNTL = 0x28c9 # macro
|
|
regCP_MES_DC_APERTURE8_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE9_BASE = 0x28ca # macro
|
|
regCP_MES_DC_APERTURE9_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE9_MASK = 0x28cb # macro
|
|
regCP_MES_DC_APERTURE9_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE9_CNTL = 0x28cc # macro
|
|
regCP_MES_DC_APERTURE9_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE10_BASE = 0x28cd # macro
|
|
regCP_MES_DC_APERTURE10_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE10_MASK = 0x28ce # macro
|
|
regCP_MES_DC_APERTURE10_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE10_CNTL = 0x28cf # macro
|
|
regCP_MES_DC_APERTURE10_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE11_BASE = 0x28d0 # macro
|
|
regCP_MES_DC_APERTURE11_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE11_MASK = 0x28d1 # macro
|
|
regCP_MES_DC_APERTURE11_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE11_CNTL = 0x28d2 # macro
|
|
regCP_MES_DC_APERTURE11_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE12_BASE = 0x28d3 # macro
|
|
regCP_MES_DC_APERTURE12_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE12_MASK = 0x28d4 # macro
|
|
regCP_MES_DC_APERTURE12_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE12_CNTL = 0x28d5 # macro
|
|
regCP_MES_DC_APERTURE12_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE13_BASE = 0x28d6 # macro
|
|
regCP_MES_DC_APERTURE13_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE13_MASK = 0x28d7 # macro
|
|
regCP_MES_DC_APERTURE13_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE13_CNTL = 0x28d8 # macro
|
|
regCP_MES_DC_APERTURE13_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE14_BASE = 0x28d9 # macro
|
|
regCP_MES_DC_APERTURE14_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE14_MASK = 0x28da # macro
|
|
regCP_MES_DC_APERTURE14_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE14_CNTL = 0x28db # macro
|
|
regCP_MES_DC_APERTURE14_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE15_BASE = 0x28dc # macro
|
|
regCP_MES_DC_APERTURE15_BASE_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE15_MASK = 0x28dd # macro
|
|
regCP_MES_DC_APERTURE15_MASK_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_APERTURE15_CNTL = 0x28de # macro
|
|
regCP_MES_DC_APERTURE15_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_PRGRM_CNTR_START = 0x2900 # macro
|
|
regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX = 1 # macro
|
|
regCP_MEC_MTVEC_LO = 0x2901 # macro
|
|
regCP_MEC_MTVEC_LO_BASE_IDX = 1 # macro
|
|
regCP_MEC_MTVEC_HI = 0x2902 # macro
|
|
regCP_MEC_MTVEC_HI_BASE_IDX = 1 # macro
|
|
regCP_MEC_ISA_CNTL = 0x2903 # macro
|
|
regCP_MEC_ISA_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_CNTL = 0x2904 # macro
|
|
regCP_MEC_RS64_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_MIE_LO = 0x2905 # macro
|
|
regCP_MEC_MIE_LO_BASE_IDX = 1 # macro
|
|
regCP_MEC_MIE_HI = 0x2906 # macro
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regCP_MEC_MIE_HI_BASE_IDX = 1 # macro
|
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regCP_MEC_RS64_INTERRUPT = 0x2907 # macro
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|
regCP_MEC_RS64_INTERRUPT_BASE_IDX = 1 # macro
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regCP_MEC_RS64_INSTR_PNTR = 0x2908 # macro
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|
regCP_MEC_RS64_INSTR_PNTR_BASE_IDX = 1 # macro
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regCP_MEC_MIP_LO = 0x2909 # macro
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regCP_MEC_MIP_LO_BASE_IDX = 1 # macro
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regCP_MEC_MIP_HI = 0x290a # macro
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regCP_MEC_MIP_HI_BASE_IDX = 1 # macro
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regCP_MEC_DC_BASE_CNTL = 0x290b # macro
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regCP_MEC_DC_BASE_CNTL_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_OP_CNTL = 0x290c # macro
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regCP_MEC_DC_OP_CNTL_BASE_IDX = 1 # macro
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|
regCP_MEC_MTIMECMP_LO = 0x290d # macro
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|
regCP_MEC_MTIMECMP_LO_BASE_IDX = 1 # macro
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|
regCP_MEC_MTIMECMP_HI = 0x290e # macro
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regCP_MEC_MTIMECMP_HI_BASE_IDX = 1 # macro
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|
regCP_MEC_GP0_LO = 0x2910 # macro
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|
regCP_MEC_GP0_LO_BASE_IDX = 1 # macro
|
|
regCP_MEC_GP0_HI = 0x2911 # macro
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|
regCP_MEC_GP0_HI_BASE_IDX = 1 # macro
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|
regCP_MEC_GP1_LO = 0x2912 # macro
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|
regCP_MEC_GP1_LO_BASE_IDX = 1 # macro
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|
regCP_MEC_GP1_HI = 0x2913 # macro
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|
regCP_MEC_GP1_HI_BASE_IDX = 1 # macro
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|
regCP_MEC_GP2_LO = 0x2914 # macro
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regCP_MEC_GP2_LO_BASE_IDX = 1 # macro
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|
regCP_MEC_GP2_HI = 0x2915 # macro
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|
regCP_MEC_GP2_HI_BASE_IDX = 1 # macro
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regCP_MEC_GP3_LO = 0x2916 # macro
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regCP_MEC_GP3_LO_BASE_IDX = 1 # macro
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|
regCP_MEC_GP3_HI = 0x2917 # macro
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regCP_MEC_GP3_HI_BASE_IDX = 1 # macro
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|
regCP_MEC_GP4_LO = 0x2918 # macro
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|
regCP_MEC_GP4_LO_BASE_IDX = 1 # macro
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|
regCP_MEC_GP4_HI = 0x2919 # macro
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|
regCP_MEC_GP4_HI_BASE_IDX = 1 # macro
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|
regCP_MEC_GP5_LO = 0x291a # macro
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|
regCP_MEC_GP5_LO_BASE_IDX = 1 # macro
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|
regCP_MEC_GP5_HI = 0x291b # macro
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|
regCP_MEC_GP5_HI_BASE_IDX = 1 # macro
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|
regCP_MEC_GP6_LO = 0x291c # macro
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|
regCP_MEC_GP6_LO_BASE_IDX = 1 # macro
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|
regCP_MEC_GP6_HI = 0x291d # macro
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|
regCP_MEC_GP6_HI_BASE_IDX = 1 # macro
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|
regCP_MEC_GP7_LO = 0x291e # macro
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|
regCP_MEC_GP7_LO_BASE_IDX = 1 # macro
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|
regCP_MEC_GP7_HI = 0x291f # macro
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|
regCP_MEC_GP7_HI_BASE_IDX = 1 # macro
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|
regCP_MEC_GP8_LO = 0x2920 # macro
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|
regCP_MEC_GP8_LO_BASE_IDX = 1 # macro
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|
regCP_MEC_GP8_HI = 0x2921 # macro
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|
regCP_MEC_GP8_HI_BASE_IDX = 1 # macro
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|
regCP_MEC_GP9_LO = 0x2922 # macro
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|
regCP_MEC_GP9_LO_BASE_IDX = 1 # macro
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|
regCP_MEC_GP9_HI = 0x2923 # macro
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|
regCP_MEC_GP9_HI_BASE_IDX = 1 # macro
|
|
regCP_MEC_LOCAL_BASE0_LO = 0x2927 # macro
|
|
regCP_MEC_LOCAL_BASE0_LO_BASE_IDX = 1 # macro
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|
regCP_MEC_LOCAL_BASE0_HI = 0x2928 # macro
|
|
regCP_MEC_LOCAL_BASE0_HI_BASE_IDX = 1 # macro
|
|
regCP_MEC_LOCAL_MASK0_LO = 0x2929 # macro
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|
regCP_MEC_LOCAL_MASK0_LO_BASE_IDX = 1 # macro
|
|
regCP_MEC_LOCAL_MASK0_HI = 0x292a # macro
|
|
regCP_MEC_LOCAL_MASK0_HI_BASE_IDX = 1 # macro
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|
regCP_MEC_LOCAL_APERTURE = 0x292b # macro
|
|
regCP_MEC_LOCAL_APERTURE_BASE_IDX = 1 # macro
|
|
regCP_MEC_LOCAL_INSTR_BASE_LO = 0x292c # macro
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|
regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro
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|
regCP_MEC_LOCAL_INSTR_BASE_HI = 0x292d # macro
|
|
regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_MEC_LOCAL_INSTR_MASK_LO = 0x292e # macro
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|
regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro
|
|
regCP_MEC_LOCAL_INSTR_MASK_HI = 0x292f # macro
|
|
regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro
|
|
regCP_MEC_LOCAL_INSTR_APERTURE = 0x2930 # macro
|
|
regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro
|
|
regCP_MEC_LOCAL_SCRATCH_APERTURE = 0x2931 # macro
|
|
regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro
|
|
regCP_MEC_LOCAL_SCRATCH_BASE_LO = 0x2932 # macro
|
|
regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_MEC_LOCAL_SCRATCH_BASE_HI = 0x2933 # macro
|
|
regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_PERFCOUNT_CNTL = 0x2934 # macro
|
|
regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_PENDING_INTERRUPT = 0x2935 # macro
|
|
regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_PRGRM_CNTR_START_HI = 0x2938 # macro
|
|
regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_16 = 0x293a # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_17 = 0x293b # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX = 1 # macro
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|
regCP_MEC_RS64_INTERRUPT_DATA_18 = 0x293c # macro
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|
regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_19 = 0x293d # macro
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|
regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX = 1 # macro
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|
regCP_MEC_RS64_INTERRUPT_DATA_20 = 0x293e # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_21 = 0x293f # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX = 1 # macro
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|
regCP_MEC_RS64_INTERRUPT_DATA_22 = 0x2940 # macro
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|
regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_23 = 0x2941 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX = 1 # macro
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|
regCP_MEC_RS64_INTERRUPT_DATA_24 = 0x2942 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_25 = 0x2943 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_26 = 0x2944 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_27 = 0x2945 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX = 1 # macro
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|
regCP_MEC_RS64_INTERRUPT_DATA_28 = 0x2946 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_29 = 0x2947 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_30 = 0x2948 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX = 1 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_31 = 0x2949 # macro
|
|
regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE0_BASE = 0x294a # macro
|
|
regCP_MEC_DC_APERTURE0_BASE_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE0_MASK = 0x294b # macro
|
|
regCP_MEC_DC_APERTURE0_MASK_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE0_CNTL = 0x294c # macro
|
|
regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE1_BASE = 0x294d # macro
|
|
regCP_MEC_DC_APERTURE1_BASE_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE1_MASK = 0x294e # macro
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|
regCP_MEC_DC_APERTURE1_MASK_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE1_CNTL = 0x294f # macro
|
|
regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE2_BASE = 0x2950 # macro
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|
regCP_MEC_DC_APERTURE2_BASE_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE2_MASK = 0x2951 # macro
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|
regCP_MEC_DC_APERTURE2_MASK_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE2_CNTL = 0x2952 # macro
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|
regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE3_BASE = 0x2953 # macro
|
|
regCP_MEC_DC_APERTURE3_BASE_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE3_MASK = 0x2954 # macro
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|
regCP_MEC_DC_APERTURE3_MASK_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE3_CNTL = 0x2955 # macro
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|
regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE4_BASE = 0x2956 # macro
|
|
regCP_MEC_DC_APERTURE4_BASE_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE4_MASK = 0x2957 # macro
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|
regCP_MEC_DC_APERTURE4_MASK_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE4_CNTL = 0x2958 # macro
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|
regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE5_BASE = 0x2959 # macro
|
|
regCP_MEC_DC_APERTURE5_BASE_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE5_MASK = 0x295a # macro
|
|
regCP_MEC_DC_APERTURE5_MASK_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE5_CNTL = 0x295b # macro
|
|
regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE6_BASE = 0x295c # macro
|
|
regCP_MEC_DC_APERTURE6_BASE_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE6_MASK = 0x295d # macro
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|
regCP_MEC_DC_APERTURE6_MASK_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE6_CNTL = 0x295e # macro
|
|
regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE7_BASE = 0x295f # macro
|
|
regCP_MEC_DC_APERTURE7_BASE_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE7_MASK = 0x2960 # macro
|
|
regCP_MEC_DC_APERTURE7_MASK_BASE_IDX = 1 # macro
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|
regCP_MEC_DC_APERTURE7_CNTL = 0x2961 # macro
|
|
regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE8_BASE = 0x2962 # macro
|
|
regCP_MEC_DC_APERTURE8_BASE_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE8_MASK = 0x2963 # macro
|
|
regCP_MEC_DC_APERTURE8_MASK_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE8_CNTL = 0x2964 # macro
|
|
regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE9_BASE = 0x2965 # macro
|
|
regCP_MEC_DC_APERTURE9_BASE_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE9_MASK = 0x2966 # macro
|
|
regCP_MEC_DC_APERTURE9_MASK_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE9_CNTL = 0x2967 # macro
|
|
regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE10_BASE = 0x2968 # macro
|
|
regCP_MEC_DC_APERTURE10_BASE_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE10_MASK = 0x2969 # macro
|
|
regCP_MEC_DC_APERTURE10_MASK_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE10_CNTL = 0x296a # macro
|
|
regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE11_BASE = 0x296b # macro
|
|
regCP_MEC_DC_APERTURE11_BASE_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE11_MASK = 0x296c # macro
|
|
regCP_MEC_DC_APERTURE11_MASK_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE11_CNTL = 0x296d # macro
|
|
regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE12_BASE = 0x296e # macro
|
|
regCP_MEC_DC_APERTURE12_BASE_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE12_MASK = 0x296f # macro
|
|
regCP_MEC_DC_APERTURE12_MASK_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE12_CNTL = 0x2970 # macro
|
|
regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE13_BASE = 0x2971 # macro
|
|
regCP_MEC_DC_APERTURE13_BASE_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE13_MASK = 0x2972 # macro
|
|
regCP_MEC_DC_APERTURE13_MASK_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE13_CNTL = 0x2973 # macro
|
|
regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE14_BASE = 0x2974 # macro
|
|
regCP_MEC_DC_APERTURE14_BASE_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE14_MASK = 0x2975 # macro
|
|
regCP_MEC_DC_APERTURE14_MASK_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE14_CNTL = 0x2976 # macro
|
|
regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE15_BASE = 0x2977 # macro
|
|
regCP_MEC_DC_APERTURE15_BASE_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE15_MASK = 0x2978 # macro
|
|
regCP_MEC_DC_APERTURE15_MASK_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_APERTURE15_CNTL = 0x2979 # macro
|
|
regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX = 1 # macro
|
|
regCP_CPC_IC_OP_CNTL = 0x297a # macro
|
|
regCP_CPC_IC_OP_CNTL_BASE_IDX = 1 # macro
|
|
regCP_GFX_CNTL = 0x2a00 # macro
|
|
regCP_GFX_CNTL_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_INTERRUPT0 = 0x2a01 # macro
|
|
regCP_GFX_RS64_INTERRUPT0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_INTR_EN0 = 0x2a02 # macro
|
|
regCP_GFX_RS64_INTR_EN0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_INTR_EN1 = 0x2a03 # macro
|
|
regCP_GFX_RS64_INTR_EN1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_BASE_CNTL = 0x2a08 # macro
|
|
regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_OP_CNTL = 0x2a09 # macro
|
|
regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_LOCAL_BASE0_LO = 0x2a0a # macro
|
|
regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_LOCAL_BASE0_HI = 0x2a0b # macro
|
|
regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_LOCAL_MASK0_LO = 0x2a0c # macro
|
|
regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_LOCAL_MASK0_HI = 0x2a0d # macro
|
|
regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_LOCAL_APERTURE = 0x2a0e # macro
|
|
regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_LOCAL_INSTR_BASE_LO = 0x2a0f # macro
|
|
regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_LOCAL_INSTR_BASE_HI = 0x2a10 # macro
|
|
regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_LOCAL_INSTR_MASK_LO = 0x2a11 # macro
|
|
regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_LOCAL_INSTR_MASK_HI = 0x2a12 # macro
|
|
regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_LOCAL_INSTR_APERTURE = 0x2a13 # macro
|
|
regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE = 0x2a14 # macro
|
|
regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO = 0x2a15 # macro
|
|
regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI = 0x2a16 # macro
|
|
regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_PERFCOUNT_CNTL0 = 0x2a1a # macro
|
|
regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_PERFCOUNT_CNTL1 = 0x2a1b # macro
|
|
regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_MIP_LO0 = 0x2a1c # macro
|
|
regCP_GFX_RS64_MIP_LO0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_MIP_LO1 = 0x2a1d # macro
|
|
regCP_GFX_RS64_MIP_LO1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_MIP_HI0 = 0x2a1e # macro
|
|
regCP_GFX_RS64_MIP_HI0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_MIP_HI1 = 0x2a1f # macro
|
|
regCP_GFX_RS64_MIP_HI1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_MTIMECMP_LO0 = 0x2a20 # macro
|
|
regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_MTIMECMP_LO1 = 0x2a21 # macro
|
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regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX = 1 # macro
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regCP_GFX_RS64_MTIMECMP_HI0 = 0x2a22 # macro
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regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX = 1 # macro
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regCP_GFX_RS64_MTIMECMP_HI1 = 0x2a23 # macro
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regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX = 1 # macro
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regCP_GFX_RS64_GP0_LO0 = 0x2a24 # macro
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regCP_GFX_RS64_GP0_LO0_BASE_IDX = 1 # macro
|
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regCP_GFX_RS64_GP0_LO1 = 0x2a25 # macro
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regCP_GFX_RS64_GP0_LO1_BASE_IDX = 1 # macro
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regCP_GFX_RS64_GP0_HI0 = 0x2a26 # macro
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regCP_GFX_RS64_GP0_HI0_BASE_IDX = 1 # macro
|
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regCP_GFX_RS64_GP0_HI1 = 0x2a27 # macro
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regCP_GFX_RS64_GP0_HI1_BASE_IDX = 1 # macro
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regCP_GFX_RS64_GP1_LO0 = 0x2a28 # macro
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regCP_GFX_RS64_GP1_LO0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP1_LO1 = 0x2a29 # macro
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regCP_GFX_RS64_GP1_LO1_BASE_IDX = 1 # macro
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|
regCP_GFX_RS64_GP1_HI0 = 0x2a2a # macro
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regCP_GFX_RS64_GP1_HI0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP1_HI1 = 0x2a2b # macro
|
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regCP_GFX_RS64_GP1_HI1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP2_LO0 = 0x2a2c # macro
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regCP_GFX_RS64_GP2_LO0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP2_LO1 = 0x2a2d # macro
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regCP_GFX_RS64_GP2_LO1_BASE_IDX = 1 # macro
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regCP_GFX_RS64_GP2_HI0 = 0x2a2e # macro
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regCP_GFX_RS64_GP2_HI0_BASE_IDX = 1 # macro
|
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regCP_GFX_RS64_GP2_HI1 = 0x2a2f # macro
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regCP_GFX_RS64_GP2_HI1_BASE_IDX = 1 # macro
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regCP_GFX_RS64_GP3_LO0 = 0x2a30 # macro
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regCP_GFX_RS64_GP3_LO0_BASE_IDX = 1 # macro
|
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regCP_GFX_RS64_GP3_LO1 = 0x2a31 # macro
|
|
regCP_GFX_RS64_GP3_LO1_BASE_IDX = 1 # macro
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regCP_GFX_RS64_GP3_HI0 = 0x2a32 # macro
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regCP_GFX_RS64_GP3_HI0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP3_HI1 = 0x2a33 # macro
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regCP_GFX_RS64_GP3_HI1_BASE_IDX = 1 # macro
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regCP_GFX_RS64_GP4_LO0 = 0x2a34 # macro
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|
regCP_GFX_RS64_GP4_LO0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP4_LO1 = 0x2a35 # macro
|
|
regCP_GFX_RS64_GP4_LO1_BASE_IDX = 1 # macro
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regCP_GFX_RS64_GP4_HI0 = 0x2a36 # macro
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regCP_GFX_RS64_GP4_HI0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP4_HI1 = 0x2a37 # macro
|
|
regCP_GFX_RS64_GP4_HI1_BASE_IDX = 1 # macro
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regCP_GFX_RS64_GP5_LO0 = 0x2a38 # macro
|
|
regCP_GFX_RS64_GP5_LO0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP5_LO1 = 0x2a39 # macro
|
|
regCP_GFX_RS64_GP5_LO1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP5_HI0 = 0x2a3a # macro
|
|
regCP_GFX_RS64_GP5_HI0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP5_HI1 = 0x2a3b # macro
|
|
regCP_GFX_RS64_GP5_HI1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP6_LO = 0x2a3c # macro
|
|
regCP_GFX_RS64_GP6_LO_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP6_HI = 0x2a3d # macro
|
|
regCP_GFX_RS64_GP6_HI_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP7_LO = 0x2a3e # macro
|
|
regCP_GFX_RS64_GP7_LO_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP7_HI = 0x2a3f # macro
|
|
regCP_GFX_RS64_GP7_HI_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP8_LO = 0x2a40 # macro
|
|
regCP_GFX_RS64_GP8_LO_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP8_HI = 0x2a41 # macro
|
|
regCP_GFX_RS64_GP8_HI_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP9_LO = 0x2a42 # macro
|
|
regCP_GFX_RS64_GP9_LO_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_GP9_HI = 0x2a43 # macro
|
|
regCP_GFX_RS64_GP9_HI_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_INSTR_PNTR0 = 0x2a44 # macro
|
|
regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_INSTR_PNTR1 = 0x2a45 # macro
|
|
regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_PENDING_INTERRUPT0 = 0x2a46 # macro
|
|
regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_PENDING_INTERRUPT1 = 0x2a47 # macro
|
|
regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE0_BASE0 = 0x2a49 # macro
|
|
regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE0_MASK0 = 0x2a4a # macro
|
|
regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE0_CNTL0 = 0x2a4b # macro
|
|
regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE1_BASE0 = 0x2a4c # macro
|
|
regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE1_MASK0 = 0x2a4d # macro
|
|
regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE1_CNTL0 = 0x2a4e # macro
|
|
regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE2_BASE0 = 0x2a4f # macro
|
|
regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE2_MASK0 = 0x2a50 # macro
|
|
regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE2_CNTL0 = 0x2a51 # macro
|
|
regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE3_BASE0 = 0x2a52 # macro
|
|
regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE3_MASK0 = 0x2a53 # macro
|
|
regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE3_CNTL0 = 0x2a54 # macro
|
|
regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE4_BASE0 = 0x2a55 # macro
|
|
regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE4_MASK0 = 0x2a56 # macro
|
|
regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE4_CNTL0 = 0x2a57 # macro
|
|
regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE5_BASE0 = 0x2a58 # macro
|
|
regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE5_MASK0 = 0x2a59 # macro
|
|
regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE5_CNTL0 = 0x2a5a # macro
|
|
regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE6_BASE0 = 0x2a5b # macro
|
|
regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE6_MASK0 = 0x2a5c # macro
|
|
regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE6_CNTL0 = 0x2a5d # macro
|
|
regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE7_BASE0 = 0x2a5e # macro
|
|
regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE7_MASK0 = 0x2a5f # macro
|
|
regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE7_CNTL0 = 0x2a60 # macro
|
|
regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE8_BASE0 = 0x2a61 # macro
|
|
regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE8_MASK0 = 0x2a62 # macro
|
|
regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE8_CNTL0 = 0x2a63 # macro
|
|
regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE9_BASE0 = 0x2a64 # macro
|
|
regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE9_MASK0 = 0x2a65 # macro
|
|
regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE9_CNTL0 = 0x2a66 # macro
|
|
regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE10_BASE0 = 0x2a67 # macro
|
|
regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE10_MASK0 = 0x2a68 # macro
|
|
regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE10_CNTL0 = 0x2a69 # macro
|
|
regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE11_BASE0 = 0x2a6a # macro
|
|
regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE11_MASK0 = 0x2a6b # macro
|
|
regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE11_CNTL0 = 0x2a6c # macro
|
|
regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE12_BASE0 = 0x2a6d # macro
|
|
regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE12_MASK0 = 0x2a6e # macro
|
|
regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE12_CNTL0 = 0x2a6f # macro
|
|
regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE13_BASE0 = 0x2a70 # macro
|
|
regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE13_MASK0 = 0x2a71 # macro
|
|
regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE13_CNTL0 = 0x2a72 # macro
|
|
regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE14_BASE0 = 0x2a73 # macro
|
|
regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE14_MASK0 = 0x2a74 # macro
|
|
regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE14_CNTL0 = 0x2a75 # macro
|
|
regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE15_BASE0 = 0x2a76 # macro
|
|
regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE15_MASK0 = 0x2a77 # macro
|
|
regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE15_CNTL0 = 0x2a78 # macro
|
|
regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE0_BASE1 = 0x2a79 # macro
|
|
regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE0_MASK1 = 0x2a7a # macro
|
|
regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE0_CNTL1 = 0x2a7b # macro
|
|
regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE1_BASE1 = 0x2a7c # macro
|
|
regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE1_MASK1 = 0x2a7d # macro
|
|
regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE1_CNTL1 = 0x2a7e # macro
|
|
regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE2_BASE1 = 0x2a7f # macro
|
|
regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE2_MASK1 = 0x2a80 # macro
|
|
regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE2_CNTL1 = 0x2a81 # macro
|
|
regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE3_BASE1 = 0x2a82 # macro
|
|
regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE3_MASK1 = 0x2a83 # macro
|
|
regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE3_CNTL1 = 0x2a84 # macro
|
|
regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE4_BASE1 = 0x2a85 # macro
|
|
regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE4_MASK1 = 0x2a86 # macro
|
|
regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE4_CNTL1 = 0x2a87 # macro
|
|
regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE5_BASE1 = 0x2a88 # macro
|
|
regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE5_MASK1 = 0x2a89 # macro
|
|
regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE5_CNTL1 = 0x2a8a # macro
|
|
regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE6_BASE1 = 0x2a8b # macro
|
|
regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE6_MASK1 = 0x2a8c # macro
|
|
regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE6_CNTL1 = 0x2a8d # macro
|
|
regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE7_BASE1 = 0x2a8e # macro
|
|
regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE7_MASK1 = 0x2a8f # macro
|
|
regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE7_CNTL1 = 0x2a90 # macro
|
|
regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE8_BASE1 = 0x2a91 # macro
|
|
regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE8_MASK1 = 0x2a92 # macro
|
|
regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE8_CNTL1 = 0x2a93 # macro
|
|
regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE9_BASE1 = 0x2a94 # macro
|
|
regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE9_MASK1 = 0x2a95 # macro
|
|
regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE9_CNTL1 = 0x2a96 # macro
|
|
regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE10_BASE1 = 0x2a97 # macro
|
|
regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE10_MASK1 = 0x2a98 # macro
|
|
regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE10_CNTL1 = 0x2a99 # macro
|
|
regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE11_BASE1 = 0x2a9a # macro
|
|
regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE11_MASK1 = 0x2a9b # macro
|
|
regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE11_CNTL1 = 0x2a9c # macro
|
|
regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE12_BASE1 = 0x2a9d # macro
|
|
regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE12_MASK1 = 0x2a9e # macro
|
|
regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE12_CNTL1 = 0x2a9f # macro
|
|
regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE13_BASE1 = 0x2aa0 # macro
|
|
regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE13_MASK1 = 0x2aa1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE13_CNTL1 = 0x2aa2 # macro
|
|
regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE14_BASE1 = 0x2aa3 # macro
|
|
regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE14_MASK1 = 0x2aa4 # macro
|
|
regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE14_CNTL1 = 0x2aa5 # macro
|
|
regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE15_BASE1 = 0x2aa6 # macro
|
|
regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE15_MASK1 = 0x2aa7 # macro
|
|
regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_APERTURE15_CNTL1 = 0x2aa8 # macro
|
|
regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_INTERRUPT1 = 0x2aac # macro
|
|
regCP_GFX_RS64_INTERRUPT1_BASE_IDX = 1 # macro
|
|
regGL1_DRAM_BURST_MASK = 0x2d02 # macro
|
|
regGL1_DRAM_BURST_MASK_BASE_IDX = 1 # macro
|
|
regGL1_ARB_STATUS = 0x2d03 # macro
|
|
regGL1_ARB_STATUS_BASE_IDX = 1 # macro
|
|
regGL1I_GL1R_REP_FGCG_OVERRIDE = 0x2d05 # macro
|
|
regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX = 1 # macro
|
|
regGL1C_STATUS = 0x2d41 # macro
|
|
regGL1C_STATUS_BASE_IDX = 1 # macro
|
|
regGL1C_UTCL0_CNTL1 = 0x2d42 # macro
|
|
regGL1C_UTCL0_CNTL1_BASE_IDX = 1 # macro
|
|
regGL1C_UTCL0_CNTL2 = 0x2d43 # macro
|
|
regGL1C_UTCL0_CNTL2_BASE_IDX = 1 # macro
|
|
regGL1C_UTCL0_STATUS = 0x2d44 # macro
|
|
regGL1C_UTCL0_STATUS_BASE_IDX = 1 # macro
|
|
regGL1C_UTCL0_RETRY = 0x2d45 # macro
|
|
regGL1C_UTCL0_RETRY_BASE_IDX = 1 # macro
|
|
regCH_ARB_CTRL = 0x2d80 # macro
|
|
regCH_ARB_CTRL_BASE_IDX = 1 # macro
|
|
regCH_DRAM_BURST_MASK = 0x2d82 # macro
|
|
regCH_DRAM_BURST_MASK_BASE_IDX = 1 # macro
|
|
regCH_ARB_STATUS = 0x2d83 # macro
|
|
regCH_ARB_STATUS_BASE_IDX = 1 # macro
|
|
regCH_DRAM_BURST_CTRL = 0x2d84 # macro
|
|
regCH_DRAM_BURST_CTRL_BASE_IDX = 1 # macro
|
|
regCHA_CHC_CREDITS = 0x2d88 # macro
|
|
regCHA_CHC_CREDITS_BASE_IDX = 1 # macro
|
|
regCHA_CLIENT_FREE_DELAY = 0x2d89 # macro
|
|
regCHA_CLIENT_FREE_DELAY_BASE_IDX = 1 # macro
|
|
regCHI_CHR_REP_FGCG_OVERRIDE = 0x2d8c # macro
|
|
regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX = 1 # macro
|
|
regCH_VC5_ENABLE = 0x2d94 # macro
|
|
regCH_VC5_ENABLE_BASE_IDX = 1 # macro
|
|
regCHC_CTRL = 0x2dc0 # macro
|
|
regCHC_CTRL_BASE_IDX = 1 # macro
|
|
regCHC_STATUS = 0x2dc1 # macro
|
|
regCHC_STATUS_BASE_IDX = 1 # macro
|
|
regCHCG_CTRL = 0x2dc2 # macro
|
|
regCHCG_CTRL_BASE_IDX = 1 # macro
|
|
regCHCG_STATUS = 0x2dc3 # macro
|
|
regCHCG_STATUS_BASE_IDX = 1 # macro
|
|
regGL2C_CTRL = 0x2e00 # macro
|
|
regGL2C_CTRL_BASE_IDX = 1 # macro
|
|
regGL2C_CTRL2 = 0x2e01 # macro
|
|
regGL2C_CTRL2_BASE_IDX = 1 # macro
|
|
regGL2C_ADDR_MATCH_MASK = 0x2e03 # macro
|
|
regGL2C_ADDR_MATCH_MASK_BASE_IDX = 1 # macro
|
|
regGL2C_ADDR_MATCH_SIZE = 0x2e04 # macro
|
|
regGL2C_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro
|
|
regGL2C_WBINVL2 = 0x2e05 # macro
|
|
regGL2C_WBINVL2_BASE_IDX = 1 # macro
|
|
regGL2C_SOFT_RESET = 0x2e06 # macro
|
|
regGL2C_SOFT_RESET_BASE_IDX = 1 # macro
|
|
regGL2C_CM_CTRL0 = 0x2e07 # macro
|
|
regGL2C_CM_CTRL0_BASE_IDX = 1 # macro
|
|
regGL2C_CM_CTRL1 = 0x2e08 # macro
|
|
regGL2C_CM_CTRL1_BASE_IDX = 1 # macro
|
|
regGL2C_CM_STALL = 0x2e09 # macro
|
|
regGL2C_CM_STALL_BASE_IDX = 1 # macro
|
|
regGL2C_CTRL3 = 0x2e0c # macro
|
|
regGL2C_CTRL3_BASE_IDX = 1 # macro
|
|
regGL2C_LB_CTR_CTRL = 0x2e0d # macro
|
|
regGL2C_LB_CTR_CTRL_BASE_IDX = 1 # macro
|
|
regGL2C_LB_DATA0 = 0x2e0e # macro
|
|
regGL2C_LB_DATA0_BASE_IDX = 1 # macro
|
|
regGL2C_LB_DATA1 = 0x2e0f # macro
|
|
regGL2C_LB_DATA1_BASE_IDX = 1 # macro
|
|
regGL2C_LB_DATA2 = 0x2e10 # macro
|
|
regGL2C_LB_DATA2_BASE_IDX = 1 # macro
|
|
regGL2C_LB_DATA3 = 0x2e11 # macro
|
|
regGL2C_LB_DATA3_BASE_IDX = 1 # macro
|
|
regGL2C_LB_CTR_SEL0 = 0x2e12 # macro
|
|
regGL2C_LB_CTR_SEL0_BASE_IDX = 1 # macro
|
|
regGL2C_LB_CTR_SEL1 = 0x2e13 # macro
|
|
regGL2C_LB_CTR_SEL1_BASE_IDX = 1 # macro
|
|
regGL2C_CTRL4 = 0x2e17 # macro
|
|
regGL2C_CTRL4_BASE_IDX = 1 # macro
|
|
regGL2C_DISCARD_STALL_CTRL = 0x2e18 # macro
|
|
regGL2C_DISCARD_STALL_CTRL_BASE_IDX = 1 # macro
|
|
regGL2A_ADDR_MATCH_CTRL = 0x2e20 # macro
|
|
regGL2A_ADDR_MATCH_CTRL_BASE_IDX = 1 # macro
|
|
regGL2A_ADDR_MATCH_MASK = 0x2e21 # macro
|
|
regGL2A_ADDR_MATCH_MASK_BASE_IDX = 1 # macro
|
|
regGL2A_ADDR_MATCH_SIZE = 0x2e22 # macro
|
|
regGL2A_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro
|
|
regGL2A_PRIORITY_CTRL = 0x2e23 # macro
|
|
regGL2A_PRIORITY_CTRL_BASE_IDX = 1 # macro
|
|
regGL2A_RESP_THROTTLE_CTRL = 0x2e2a # macro
|
|
regGL2A_RESP_THROTTLE_CTRL_BASE_IDX = 1 # macro
|
|
regGL1H_ARB_CTRL = 0x2e40 # macro
|
|
regGL1H_ARB_CTRL_BASE_IDX = 1 # macro
|
|
regGL1H_GL1_CREDITS = 0x2e41 # macro
|
|
regGL1H_GL1_CREDITS_BASE_IDX = 1 # macro
|
|
regGL1H_BURST_MASK = 0x2e42 # macro
|
|
regGL1H_BURST_MASK_BASE_IDX = 1 # macro
|
|
regGL1H_BURST_CTRL = 0x2e43 # macro
|
|
regGL1H_BURST_CTRL_BASE_IDX = 1 # macro
|
|
regGL1H_ARB_STATUS = 0x2e44 # macro
|
|
regGL1H_ARB_STATUS_BASE_IDX = 1 # macro
|
|
regCPG_PERFCOUNTER1_LO = 0x3000 # macro
|
|
regCPG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regCPG_PERFCOUNTER1_HI = 0x3001 # macro
|
|
regCPG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regCPG_PERFCOUNTER0_LO = 0x3002 # macro
|
|
regCPG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regCPG_PERFCOUNTER0_HI = 0x3003 # macro
|
|
regCPG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regCPC_PERFCOUNTER1_LO = 0x3004 # macro
|
|
regCPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regCPC_PERFCOUNTER1_HI = 0x3005 # macro
|
|
regCPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regCPC_PERFCOUNTER0_LO = 0x3006 # macro
|
|
regCPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regCPC_PERFCOUNTER0_HI = 0x3007 # macro
|
|
regCPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regCPF_PERFCOUNTER1_LO = 0x3008 # macro
|
|
regCPF_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regCPF_PERFCOUNTER1_HI = 0x3009 # macro
|
|
regCPF_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regCPF_PERFCOUNTER0_LO = 0x300a # macro
|
|
regCPF_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regCPF_PERFCOUNTER0_HI = 0x300b # macro
|
|
regCPF_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regCPF_LATENCY_STATS_DATA = 0x300c # macro
|
|
regCPF_LATENCY_STATS_DATA_BASE_IDX = 1 # macro
|
|
regCPG_LATENCY_STATS_DATA = 0x300d # macro
|
|
regCPG_LATENCY_STATS_DATA_BASE_IDX = 1 # macro
|
|
regCPC_LATENCY_STATS_DATA = 0x300e # macro
|
|
regCPC_LATENCY_STATS_DATA_BASE_IDX = 1 # macro
|
|
regGRBM_PERFCOUNTER0_LO = 0x3040 # macro
|
|
regGRBM_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regGRBM_PERFCOUNTER0_HI = 0x3041 # macro
|
|
regGRBM_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regGRBM_PERFCOUNTER1_LO = 0x3043 # macro
|
|
regGRBM_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regGRBM_PERFCOUNTER1_HI = 0x3044 # macro
|
|
regGRBM_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regGRBM_SE0_PERFCOUNTER_LO = 0x3045 # macro
|
|
regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX = 1 # macro
|
|
regGRBM_SE0_PERFCOUNTER_HI = 0x3046 # macro
|
|
regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX = 1 # macro
|
|
regGRBM_SE1_PERFCOUNTER_LO = 0x3047 # macro
|
|
regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX = 1 # macro
|
|
regGRBM_SE1_PERFCOUNTER_HI = 0x3048 # macro
|
|
regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX = 1 # macro
|
|
regGRBM_SE2_PERFCOUNTER_LO = 0x3049 # macro
|
|
regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX = 1 # macro
|
|
regGRBM_SE2_PERFCOUNTER_HI = 0x304a # macro
|
|
regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX = 1 # macro
|
|
regGRBM_SE3_PERFCOUNTER_LO = 0x304b # macro
|
|
regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX = 1 # macro
|
|
regGRBM_SE3_PERFCOUNTER_HI = 0x304c # macro
|
|
regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX = 1 # macro
|
|
regGRBM_SE4_PERFCOUNTER_LO = 0x304d # macro
|
|
regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX = 1 # macro
|
|
regGRBM_SE4_PERFCOUNTER_HI = 0x304e # macro
|
|
regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX = 1 # macro
|
|
regGRBM_SE5_PERFCOUNTER_LO = 0x304f # macro
|
|
regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX = 1 # macro
|
|
regGRBM_SE5_PERFCOUNTER_HI = 0x3050 # macro
|
|
regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX = 1 # macro
|
|
regGRBM_SE6_PERFCOUNTER_LO = 0x3051 # macro
|
|
regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX = 1 # macro
|
|
regGRBM_SE6_PERFCOUNTER_HI = 0x3052 # macro
|
|
regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER0_LO = 0x30a4 # macro
|
|
regGE1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER0_HI = 0x30a5 # macro
|
|
regGE1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER1_LO = 0x30a6 # macro
|
|
regGE1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER1_HI = 0x30a7 # macro
|
|
regGE1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER2_LO = 0x30a8 # macro
|
|
regGE1_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER2_HI = 0x30a9 # macro
|
|
regGE1_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER3_LO = 0x30aa # macro
|
|
regGE1_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER3_HI = 0x30ab # macro
|
|
regGE1_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER0_LO = 0x30ac # macro
|
|
regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER0_HI = 0x30ad # macro
|
|
regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER1_LO = 0x30ae # macro
|
|
regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER1_HI = 0x30af # macro
|
|
regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER2_LO = 0x30b0 # macro
|
|
regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER2_HI = 0x30b1 # macro
|
|
regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER3_LO = 0x30b2 # macro
|
|
regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER3_HI = 0x30b3 # macro
|
|
regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER0_LO = 0x30b4 # macro
|
|
regGE2_SE_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER0_HI = 0x30b5 # macro
|
|
regGE2_SE_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER1_LO = 0x30b6 # macro
|
|
regGE2_SE_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER1_HI = 0x30b7 # macro
|
|
regGE2_SE_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER2_LO = 0x30b8 # macro
|
|
regGE2_SE_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER2_HI = 0x30b9 # macro
|
|
regGE2_SE_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER3_LO = 0x30ba # macro
|
|
regGE2_SE_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER3_HI = 0x30bb # macro
|
|
regGE2_SE_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER0_LO = 0x3100 # macro
|
|
regPA_SU_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER0_HI = 0x3101 # macro
|
|
regPA_SU_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER1_LO = 0x3102 # macro
|
|
regPA_SU_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER1_HI = 0x3103 # macro
|
|
regPA_SU_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER2_LO = 0x3104 # macro
|
|
regPA_SU_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER2_HI = 0x3105 # macro
|
|
regPA_SU_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER3_LO = 0x3106 # macro
|
|
regPA_SU_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER3_HI = 0x3107 # macro
|
|
regPA_SU_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER0_LO = 0x3140 # macro
|
|
regPA_SC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER0_HI = 0x3141 # macro
|
|
regPA_SC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER1_LO = 0x3142 # macro
|
|
regPA_SC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER1_HI = 0x3143 # macro
|
|
regPA_SC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER2_LO = 0x3144 # macro
|
|
regPA_SC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER2_HI = 0x3145 # macro
|
|
regPA_SC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER3_LO = 0x3146 # macro
|
|
regPA_SC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER3_HI = 0x3147 # macro
|
|
regPA_SC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER4_LO = 0x3148 # macro
|
|
regPA_SC_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER4_HI = 0x3149 # macro
|
|
regPA_SC_PERFCOUNTER4_HI_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER5_LO = 0x314a # macro
|
|
regPA_SC_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER5_HI = 0x314b # macro
|
|
regPA_SC_PERFCOUNTER5_HI_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER6_LO = 0x314c # macro
|
|
regPA_SC_PERFCOUNTER6_LO_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER6_HI = 0x314d # macro
|
|
regPA_SC_PERFCOUNTER6_HI_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER7_LO = 0x314e # macro
|
|
regPA_SC_PERFCOUNTER7_LO_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER7_HI = 0x314f # macro
|
|
regPA_SC_PERFCOUNTER7_HI_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER0_HI = 0x3180 # macro
|
|
regSPI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER0_LO = 0x3181 # macro
|
|
regSPI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER1_HI = 0x3182 # macro
|
|
regSPI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER1_LO = 0x3183 # macro
|
|
regSPI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER2_HI = 0x3184 # macro
|
|
regSPI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER2_LO = 0x3185 # macro
|
|
regSPI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER3_HI = 0x3186 # macro
|
|
regSPI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER3_LO = 0x3187 # macro
|
|
regSPI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER4_HI = 0x3188 # macro
|
|
regSPI_PERFCOUNTER4_HI_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER4_LO = 0x3189 # macro
|
|
regSPI_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER5_HI = 0x318a # macro
|
|
regSPI_PERFCOUNTER5_HI_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER5_LO = 0x318b # macro
|
|
regSPI_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER0_HI = 0x318c # macro
|
|
regPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER0_LO = 0x318d # macro
|
|
regPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER1_HI = 0x318e # macro
|
|
regPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER1_LO = 0x318f # macro
|
|
regPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER2_HI = 0x3190 # macro
|
|
regPC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER2_LO = 0x3191 # macro
|
|
regPC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER3_HI = 0x3192 # macro
|
|
regPC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER3_LO = 0x3193 # macro
|
|
regPC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER0_LO = 0x31c0 # macro
|
|
regSQ_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER1_LO = 0x31c2 # macro
|
|
regSQ_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER2_LO = 0x31c4 # macro
|
|
regSQ_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER3_LO = 0x31c6 # macro
|
|
regSQ_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER4_LO = 0x31c8 # macro
|
|
regSQ_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER5_LO = 0x31ca # macro
|
|
regSQ_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER6_LO = 0x31cc # macro
|
|
regSQ_PERFCOUNTER6_LO_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER7_LO = 0x31ce # macro
|
|
regSQ_PERFCOUNTER7_LO_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER0_LO = 0x31e4 # macro
|
|
regSQG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER0_HI = 0x31e5 # macro
|
|
regSQG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER1_LO = 0x31e6 # macro
|
|
regSQG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER1_HI = 0x31e7 # macro
|
|
regSQG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER2_LO = 0x31e8 # macro
|
|
regSQG_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER2_HI = 0x31e9 # macro
|
|
regSQG_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER3_LO = 0x31ea # macro
|
|
regSQG_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER3_HI = 0x31eb # macro
|
|
regSQG_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER4_LO = 0x31ec # macro
|
|
regSQG_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER4_HI = 0x31ed # macro
|
|
regSQG_PERFCOUNTER4_HI_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER5_LO = 0x31ee # macro
|
|
regSQG_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER5_HI = 0x31ef # macro
|
|
regSQG_PERFCOUNTER5_HI_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER6_LO = 0x31f0 # macro
|
|
regSQG_PERFCOUNTER6_LO_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER6_HI = 0x31f1 # macro
|
|
regSQG_PERFCOUNTER6_HI_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER7_LO = 0x31f2 # macro
|
|
regSQG_PERFCOUNTER7_LO_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER7_HI = 0x31f3 # macro
|
|
regSQG_PERFCOUNTER7_HI_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER0_LO = 0x3240 # macro
|
|
regSX_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER0_HI = 0x3241 # macro
|
|
regSX_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER1_LO = 0x3242 # macro
|
|
regSX_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER1_HI = 0x3243 # macro
|
|
regSX_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER2_LO = 0x3244 # macro
|
|
regSX_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER2_HI = 0x3245 # macro
|
|
regSX_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER3_LO = 0x3246 # macro
|
|
regSX_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER3_HI = 0x3247 # macro
|
|
regSX_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regGCEA_PERFCOUNTER2_LO = 0x3260 # macro
|
|
regGCEA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regGCEA_PERFCOUNTER2_HI = 0x3261 # macro
|
|
regGCEA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regGCEA_PERFCOUNTER_LO = 0x3262 # macro
|
|
regGCEA_PERFCOUNTER_LO_BASE_IDX = 1 # macro
|
|
regGCEA_PERFCOUNTER_HI = 0x3263 # macro
|
|
regGCEA_PERFCOUNTER_HI_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER0_LO = 0x3280 # macro
|
|
regGDS_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER0_HI = 0x3281 # macro
|
|
regGDS_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER1_LO = 0x3282 # macro
|
|
regGDS_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER1_HI = 0x3283 # macro
|
|
regGDS_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER2_LO = 0x3284 # macro
|
|
regGDS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER2_HI = 0x3285 # macro
|
|
regGDS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER3_LO = 0x3286 # macro
|
|
regGDS_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER3_HI = 0x3287 # macro
|
|
regGDS_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regTA_PERFCOUNTER0_LO = 0x32c0 # macro
|
|
regTA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regTA_PERFCOUNTER0_HI = 0x32c1 # macro
|
|
regTA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regTA_PERFCOUNTER1_LO = 0x32c2 # macro
|
|
regTA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regTA_PERFCOUNTER1_HI = 0x32c3 # macro
|
|
regTA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regTD_PERFCOUNTER0_LO = 0x3300 # macro
|
|
regTD_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regTD_PERFCOUNTER0_HI = 0x3301 # macro
|
|
regTD_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regTD_PERFCOUNTER1_LO = 0x3302 # macro
|
|
regTD_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regTD_PERFCOUNTER1_HI = 0x3303 # macro
|
|
regTD_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER0_LO = 0x3340 # macro
|
|
regTCP_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER0_HI = 0x3341 # macro
|
|
regTCP_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER1_LO = 0x3342 # macro
|
|
regTCP_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER1_HI = 0x3343 # macro
|
|
regTCP_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER2_LO = 0x3344 # macro
|
|
regTCP_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER2_HI = 0x3345 # macro
|
|
regTCP_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER3_LO = 0x3346 # macro
|
|
regTCP_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER3_HI = 0x3347 # macro
|
|
regTCP_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER_FILTER = 0x3348 # macro
|
|
regTCP_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER_FILTER2 = 0x3349 # macro
|
|
regTCP_PERFCOUNTER_FILTER2_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER_FILTER_EN = 0x334a # macro
|
|
regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER0_LO = 0x3380 # macro
|
|
regGL2C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER0_HI = 0x3381 # macro
|
|
regGL2C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER1_LO = 0x3382 # macro
|
|
regGL2C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER1_HI = 0x3383 # macro
|
|
regGL2C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER2_LO = 0x3384 # macro
|
|
regGL2C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER2_HI = 0x3385 # macro
|
|
regGL2C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER3_LO = 0x3386 # macro
|
|
regGL2C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER3_HI = 0x3387 # macro
|
|
regGL2C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER0_LO = 0x3390 # macro
|
|
regGL2A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER0_HI = 0x3391 # macro
|
|
regGL2A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER1_LO = 0x3392 # macro
|
|
regGL2A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER1_HI = 0x3393 # macro
|
|
regGL2A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER2_LO = 0x3394 # macro
|
|
regGL2A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER2_HI = 0x3395 # macro
|
|
regGL2A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER3_LO = 0x3396 # macro
|
|
regGL2A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER3_HI = 0x3397 # macro
|
|
regGL2A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regGL1C_PERFCOUNTER0_LO = 0x33a0 # macro
|
|
regGL1C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regGL1C_PERFCOUNTER0_HI = 0x33a1 # macro
|
|
regGL1C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regGL1C_PERFCOUNTER1_LO = 0x33a2 # macro
|
|
regGL1C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regGL1C_PERFCOUNTER1_HI = 0x33a3 # macro
|
|
regGL1C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regGL1C_PERFCOUNTER2_LO = 0x33a4 # macro
|
|
regGL1C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regGL1C_PERFCOUNTER2_HI = 0x33a5 # macro
|
|
regGL1C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regGL1C_PERFCOUNTER3_LO = 0x33a6 # macro
|
|
regGL1C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regGL1C_PERFCOUNTER3_HI = 0x33a7 # macro
|
|
regGL1C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regCHC_PERFCOUNTER0_LO = 0x33c0 # macro
|
|
regCHC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regCHC_PERFCOUNTER0_HI = 0x33c1 # macro
|
|
regCHC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regCHC_PERFCOUNTER1_LO = 0x33c2 # macro
|
|
regCHC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regCHC_PERFCOUNTER1_HI = 0x33c3 # macro
|
|
regCHC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regCHC_PERFCOUNTER2_LO = 0x33c4 # macro
|
|
regCHC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regCHC_PERFCOUNTER2_HI = 0x33c5 # macro
|
|
regCHC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regCHC_PERFCOUNTER3_LO = 0x33c6 # macro
|
|
regCHC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regCHC_PERFCOUNTER3_HI = 0x33c7 # macro
|
|
regCHC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regCHCG_PERFCOUNTER0_LO = 0x33c8 # macro
|
|
regCHCG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regCHCG_PERFCOUNTER0_HI = 0x33c9 # macro
|
|
regCHCG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regCHCG_PERFCOUNTER1_LO = 0x33ca # macro
|
|
regCHCG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regCHCG_PERFCOUNTER1_HI = 0x33cb # macro
|
|
regCHCG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regCHCG_PERFCOUNTER2_LO = 0x33cc # macro
|
|
regCHCG_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regCHCG_PERFCOUNTER2_HI = 0x33cd # macro
|
|
regCHCG_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regCHCG_PERFCOUNTER3_LO = 0x33ce # macro
|
|
regCHCG_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regCHCG_PERFCOUNTER3_HI = 0x33cf # macro
|
|
regCHCG_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER0_LO = 0x3406 # macro
|
|
regCB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER0_HI = 0x3407 # macro
|
|
regCB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER1_LO = 0x3408 # macro
|
|
regCB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER1_HI = 0x3409 # macro
|
|
regCB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER2_LO = 0x340a # macro
|
|
regCB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER2_HI = 0x340b # macro
|
|
regCB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER3_LO = 0x340c # macro
|
|
regCB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER3_HI = 0x340d # macro
|
|
regCB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER0_LO = 0x3440 # macro
|
|
regDB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER0_HI = 0x3441 # macro
|
|
regDB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER1_LO = 0x3442 # macro
|
|
regDB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER1_HI = 0x3443 # macro
|
|
regDB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER2_LO = 0x3444 # macro
|
|
regDB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER2_HI = 0x3445 # macro
|
|
regDB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER3_LO = 0x3446 # macro
|
|
regDB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER3_HI = 0x3447 # macro
|
|
regDB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regRLC_PERFCOUNTER0_LO = 0x3480 # macro
|
|
regRLC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regRLC_PERFCOUNTER0_HI = 0x3481 # macro
|
|
regRLC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regRLC_PERFCOUNTER1_LO = 0x3482 # macro
|
|
regRLC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regRLC_PERFCOUNTER1_HI = 0x3483 # macro
|
|
regRLC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER0_LO = 0x34c0 # macro
|
|
regRMI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER0_HI = 0x34c1 # macro
|
|
regRMI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER1_LO = 0x34c2 # macro
|
|
regRMI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER1_HI = 0x34c3 # macro
|
|
regRMI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER2_LO = 0x34c4 # macro
|
|
regRMI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER2_HI = 0x34c5 # macro
|
|
regRMI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER3_LO = 0x34c6 # macro
|
|
regRMI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER3_HI = 0x34c7 # macro
|
|
regRMI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regGCR_PERFCOUNTER0_LO = 0x3520 # macro
|
|
regGCR_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regGCR_PERFCOUNTER0_HI = 0x3521 # macro
|
|
regGCR_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regGCR_PERFCOUNTER1_LO = 0x3522 # macro
|
|
regGCR_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regGCR_PERFCOUNTER1_HI = 0x3523 # macro
|
|
regGCR_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER0_LO = 0x3580 # macro
|
|
regPA_PH_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER0_HI = 0x3581 # macro
|
|
regPA_PH_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER1_LO = 0x3582 # macro
|
|
regPA_PH_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER1_HI = 0x3583 # macro
|
|
regPA_PH_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER2_LO = 0x3584 # macro
|
|
regPA_PH_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER2_HI = 0x3585 # macro
|
|
regPA_PH_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER3_LO = 0x3586 # macro
|
|
regPA_PH_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER3_HI = 0x3587 # macro
|
|
regPA_PH_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER4_LO = 0x3588 # macro
|
|
regPA_PH_PERFCOUNTER4_LO_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER4_HI = 0x3589 # macro
|
|
regPA_PH_PERFCOUNTER4_HI_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER5_LO = 0x358a # macro
|
|
regPA_PH_PERFCOUNTER5_LO_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER5_HI = 0x358b # macro
|
|
regPA_PH_PERFCOUNTER5_HI_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER6_LO = 0x358c # macro
|
|
regPA_PH_PERFCOUNTER6_LO_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER6_HI = 0x358d # macro
|
|
regPA_PH_PERFCOUNTER6_HI_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER7_LO = 0x358e # macro
|
|
regPA_PH_PERFCOUNTER7_LO_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER7_HI = 0x358f # macro
|
|
regPA_PH_PERFCOUNTER7_HI_BASE_IDX = 1 # macro
|
|
regUTCL1_PERFCOUNTER0_LO = 0x35a0 # macro
|
|
regUTCL1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regUTCL1_PERFCOUNTER0_HI = 0x35a1 # macro
|
|
regUTCL1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regUTCL1_PERFCOUNTER1_LO = 0x35a2 # macro
|
|
regUTCL1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regUTCL1_PERFCOUNTER1_HI = 0x35a3 # macro
|
|
regUTCL1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regUTCL1_PERFCOUNTER2_LO = 0x35a4 # macro
|
|
regUTCL1_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regUTCL1_PERFCOUNTER2_HI = 0x35a5 # macro
|
|
regUTCL1_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regUTCL1_PERFCOUNTER3_LO = 0x35a6 # macro
|
|
regUTCL1_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regUTCL1_PERFCOUNTER3_HI = 0x35a7 # macro
|
|
regUTCL1_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regGL1A_PERFCOUNTER0_LO = 0x35c0 # macro
|
|
regGL1A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regGL1A_PERFCOUNTER0_HI = 0x35c1 # macro
|
|
regGL1A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regGL1A_PERFCOUNTER1_LO = 0x35c2 # macro
|
|
regGL1A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regGL1A_PERFCOUNTER1_HI = 0x35c3 # macro
|
|
regGL1A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regGL1A_PERFCOUNTER2_LO = 0x35c4 # macro
|
|
regGL1A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regGL1A_PERFCOUNTER2_HI = 0x35c5 # macro
|
|
regGL1A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regGL1A_PERFCOUNTER3_LO = 0x35c6 # macro
|
|
regGL1A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regGL1A_PERFCOUNTER3_HI = 0x35c7 # macro
|
|
regGL1A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regGL1H_PERFCOUNTER0_LO = 0x35d0 # macro
|
|
regGL1H_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regGL1H_PERFCOUNTER0_HI = 0x35d1 # macro
|
|
regGL1H_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regGL1H_PERFCOUNTER1_LO = 0x35d2 # macro
|
|
regGL1H_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regGL1H_PERFCOUNTER1_HI = 0x35d3 # macro
|
|
regGL1H_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regGL1H_PERFCOUNTER2_LO = 0x35d4 # macro
|
|
regGL1H_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regGL1H_PERFCOUNTER2_HI = 0x35d5 # macro
|
|
regGL1H_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regGL1H_PERFCOUNTER3_LO = 0x35d6 # macro
|
|
regGL1H_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regGL1H_PERFCOUNTER3_HI = 0x35d7 # macro
|
|
regGL1H_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regCHA_PERFCOUNTER0_LO = 0x3600 # macro
|
|
regCHA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro
|
|
regCHA_PERFCOUNTER0_HI = 0x3601 # macro
|
|
regCHA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro
|
|
regCHA_PERFCOUNTER1_LO = 0x3602 # macro
|
|
regCHA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro
|
|
regCHA_PERFCOUNTER1_HI = 0x3603 # macro
|
|
regCHA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro
|
|
regCHA_PERFCOUNTER2_LO = 0x3604 # macro
|
|
regCHA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regCHA_PERFCOUNTER2_HI = 0x3605 # macro
|
|
regCHA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regCHA_PERFCOUNTER3_LO = 0x3606 # macro
|
|
regCHA_PERFCOUNTER3_LO_BASE_IDX = 1 # macro
|
|
regCHA_PERFCOUNTER3_HI = 0x3607 # macro
|
|
regCHA_PERFCOUNTER3_HI_BASE_IDX = 1 # macro
|
|
regGUS_PERFCOUNTER2_LO = 0x3640 # macro
|
|
regGUS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro
|
|
regGUS_PERFCOUNTER2_HI = 0x3641 # macro
|
|
regGUS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro
|
|
regGUS_PERFCOUNTER_LO = 0x3642 # macro
|
|
regGUS_PERFCOUNTER_LO_BASE_IDX = 1 # macro
|
|
regGUS_PERFCOUNTER_HI = 0x3643 # macro
|
|
regGUS_PERFCOUNTER_HI_BASE_IDX = 1 # macro
|
|
regCPG_PERFCOUNTER1_SELECT = 0x3800 # macro
|
|
regCPG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regCPG_PERFCOUNTER0_SELECT1 = 0x3801 # macro
|
|
regCPG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regCPG_PERFCOUNTER0_SELECT = 0x3802 # macro
|
|
regCPG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regCPC_PERFCOUNTER1_SELECT = 0x3803 # macro
|
|
regCPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regCPC_PERFCOUNTER0_SELECT1 = 0x3804 # macro
|
|
regCPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regCPF_PERFCOUNTER1_SELECT = 0x3805 # macro
|
|
regCPF_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regCPF_PERFCOUNTER0_SELECT1 = 0x3806 # macro
|
|
regCPF_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regCPF_PERFCOUNTER0_SELECT = 0x3807 # macro
|
|
regCPF_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regCP_PERFMON_CNTL = 0x3808 # macro
|
|
regCP_PERFMON_CNTL_BASE_IDX = 1 # macro
|
|
regCPC_PERFCOUNTER0_SELECT = 0x3809 # macro
|
|
regCPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regCPF_TC_PERF_COUNTER_WINDOW_SELECT = 0x380a # macro
|
|
regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro
|
|
regCPG_TC_PERF_COUNTER_WINDOW_SELECT = 0x380b # macro
|
|
regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro
|
|
regCPF_LATENCY_STATS_SELECT = 0x380c # macro
|
|
regCPF_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro
|
|
regCPG_LATENCY_STATS_SELECT = 0x380d # macro
|
|
regCPG_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro
|
|
regCPC_LATENCY_STATS_SELECT = 0x380e # macro
|
|
regCPC_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro
|
|
regCPC_TC_PERF_COUNTER_WINDOW_SELECT = 0x380f # macro
|
|
regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro
|
|
regCP_DRAW_OBJECT = 0x3810 # macro
|
|
regCP_DRAW_OBJECT_BASE_IDX = 1 # macro
|
|
regCP_DRAW_OBJECT_COUNTER = 0x3811 # macro
|
|
regCP_DRAW_OBJECT_COUNTER_BASE_IDX = 1 # macro
|
|
regCP_DRAW_WINDOW_MASK_HI = 0x3812 # macro
|
|
regCP_DRAW_WINDOW_MASK_HI_BASE_IDX = 1 # macro
|
|
regCP_DRAW_WINDOW_HI = 0x3813 # macro
|
|
regCP_DRAW_WINDOW_HI_BASE_IDX = 1 # macro
|
|
regCP_DRAW_WINDOW_LO = 0x3814 # macro
|
|
regCP_DRAW_WINDOW_LO_BASE_IDX = 1 # macro
|
|
regCP_DRAW_WINDOW_CNTL = 0x3815 # macro
|
|
regCP_DRAW_WINDOW_CNTL_BASE_IDX = 1 # macro
|
|
regGRBM_PERFCOUNTER0_SELECT = 0x3840 # macro
|
|
regGRBM_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regGRBM_PERFCOUNTER1_SELECT = 0x3841 # macro
|
|
regGRBM_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regGRBM_SE0_PERFCOUNTER_SELECT = 0x3842 # macro
|
|
regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
|
|
regGRBM_SE1_PERFCOUNTER_SELECT = 0x3843 # macro
|
|
regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
|
|
regGRBM_SE2_PERFCOUNTER_SELECT = 0x3844 # macro
|
|
regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
|
|
regGRBM_SE3_PERFCOUNTER_SELECT = 0x3845 # macro
|
|
regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
|
|
regGRBM_SE4_PERFCOUNTER_SELECT = 0x3846 # macro
|
|
regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
|
|
regGRBM_SE5_PERFCOUNTER_SELECT = 0x3847 # macro
|
|
regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
|
|
regGRBM_SE6_PERFCOUNTER_SELECT = 0x3848 # macro
|
|
regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro
|
|
regGRBM_PERFCOUNTER0_SELECT_HI = 0x384d # macro
|
|
regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX = 1 # macro
|
|
regGRBM_PERFCOUNTER1_SELECT_HI = 0x384e # macro
|
|
regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER0_SELECT = 0x38a4 # macro
|
|
regGE1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER0_SELECT1 = 0x38a5 # macro
|
|
regGE1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER1_SELECT = 0x38a6 # macro
|
|
regGE1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER1_SELECT1 = 0x38a7 # macro
|
|
regGE1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER2_SELECT = 0x38a8 # macro
|
|
regGE1_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER2_SELECT1 = 0x38a9 # macro
|
|
regGE1_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER3_SELECT = 0x38aa # macro
|
|
regGE1_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regGE1_PERFCOUNTER3_SELECT1 = 0x38ab # macro
|
|
regGE1_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER0_SELECT = 0x38ac # macro
|
|
regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER0_SELECT1 = 0x38ad # macro
|
|
regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER1_SELECT = 0x38ae # macro
|
|
regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER1_SELECT1 = 0x38af # macro
|
|
regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER2_SELECT = 0x38b0 # macro
|
|
regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER2_SELECT1 = 0x38b1 # macro
|
|
regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER3_SELECT = 0x38b2 # macro
|
|
regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regGE2_DIST_PERFCOUNTER3_SELECT1 = 0x38b3 # macro
|
|
regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER0_SELECT = 0x38b4 # macro
|
|
regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER0_SELECT1 = 0x38b5 # macro
|
|
regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER1_SELECT = 0x38b6 # macro
|
|
regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER1_SELECT1 = 0x38b7 # macro
|
|
regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER2_SELECT = 0x38b8 # macro
|
|
regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER2_SELECT1 = 0x38b9 # macro
|
|
regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER3_SELECT = 0x38ba # macro
|
|
regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regGE2_SE_PERFCOUNTER3_SELECT1 = 0x38bb # macro
|
|
regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER0_SELECT = 0x3900 # macro
|
|
regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER0_SELECT1 = 0x3901 # macro
|
|
regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER1_SELECT = 0x3902 # macro
|
|
regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER1_SELECT1 = 0x3903 # macro
|
|
regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER2_SELECT = 0x3904 # macro
|
|
regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER2_SELECT1 = 0x3905 # macro
|
|
regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER3_SELECT = 0x3906 # macro
|
|
regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regPA_SU_PERFCOUNTER3_SELECT1 = 0x3907 # macro
|
|
regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER0_SELECT = 0x3940 # macro
|
|
regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER0_SELECT1 = 0x3941 # macro
|
|
regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER1_SELECT = 0x3942 # macro
|
|
regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER2_SELECT = 0x3943 # macro
|
|
regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER3_SELECT = 0x3944 # macro
|
|
regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER4_SELECT = 0x3945 # macro
|
|
regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER5_SELECT = 0x3946 # macro
|
|
regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER6_SELECT = 0x3947 # macro
|
|
regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro
|
|
regPA_SC_PERFCOUNTER7_SELECT = 0x3948 # macro
|
|
regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER0_SELECT = 0x3980 # macro
|
|
regSPI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER1_SELECT = 0x3981 # macro
|
|
regSPI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER2_SELECT = 0x3982 # macro
|
|
regSPI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER3_SELECT = 0x3983 # macro
|
|
regSPI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER0_SELECT1 = 0x3984 # macro
|
|
regSPI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER1_SELECT1 = 0x3985 # macro
|
|
regSPI_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER2_SELECT1 = 0x3986 # macro
|
|
regSPI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER3_SELECT1 = 0x3987 # macro
|
|
regSPI_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER4_SELECT = 0x3988 # macro
|
|
regSPI_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER5_SELECT = 0x3989 # macro
|
|
regSPI_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
|
|
regSPI_PERFCOUNTER_BINS = 0x398a # macro
|
|
regSPI_PERFCOUNTER_BINS_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER0_SELECT = 0x398c # macro
|
|
regPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER1_SELECT = 0x398d # macro
|
|
regPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER2_SELECT = 0x398e # macro
|
|
regPC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER3_SELECT = 0x398f # macro
|
|
regPC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER0_SELECT1 = 0x3990 # macro
|
|
regPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER1_SELECT1 = 0x3991 # macro
|
|
regPC_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER2_SELECT1 = 0x3992 # macro
|
|
regPC_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
|
|
regPC_PERFCOUNTER3_SELECT1 = 0x3993 # macro
|
|
regPC_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER0_SELECT = 0x39c0 # macro
|
|
regSQ_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER1_SELECT = 0x39c1 # macro
|
|
regSQ_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER2_SELECT = 0x39c2 # macro
|
|
regSQ_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER3_SELECT = 0x39c3 # macro
|
|
regSQ_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER4_SELECT = 0x39c4 # macro
|
|
regSQ_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER5_SELECT = 0x39c5 # macro
|
|
regSQ_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER6_SELECT = 0x39c6 # macro
|
|
regSQ_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER7_SELECT = 0x39c7 # macro
|
|
regSQ_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER8_SELECT = 0x39c8 # macro
|
|
regSQ_PERFCOUNTER8_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER9_SELECT = 0x39c9 # macro
|
|
regSQ_PERFCOUNTER9_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER10_SELECT = 0x39ca # macro
|
|
regSQ_PERFCOUNTER10_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER11_SELECT = 0x39cb # macro
|
|
regSQ_PERFCOUNTER11_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER12_SELECT = 0x39cc # macro
|
|
regSQ_PERFCOUNTER12_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER13_SELECT = 0x39cd # macro
|
|
regSQ_PERFCOUNTER13_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER14_SELECT = 0x39ce # macro
|
|
regSQ_PERFCOUNTER14_SELECT_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER15_SELECT = 0x39cf # macro
|
|
regSQ_PERFCOUNTER15_SELECT_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER0_SELECT = 0x39d0 # macro
|
|
regSQG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER1_SELECT = 0x39d1 # macro
|
|
regSQG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER2_SELECT = 0x39d2 # macro
|
|
regSQG_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER3_SELECT = 0x39d3 # macro
|
|
regSQG_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER4_SELECT = 0x39d4 # macro
|
|
regSQG_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER5_SELECT = 0x39d5 # macro
|
|
regSQG_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER6_SELECT = 0x39d6 # macro
|
|
regSQG_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER7_SELECT = 0x39d7 # macro
|
|
regSQG_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER_CTRL = 0x39d8 # macro
|
|
regSQG_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro
|
|
regSQG_PERFCOUNTER_CTRL2 = 0x39da # macro
|
|
regSQG_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro
|
|
regSQG_PERF_SAMPLE_FINISH = 0x39db # macro
|
|
regSQG_PERF_SAMPLE_FINISH_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER_CTRL = 0x39e0 # macro
|
|
regSQ_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro
|
|
regSQ_PERFCOUNTER_CTRL2 = 0x39e2 # macro
|
|
regSQ_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_BUF0_BASE = 0x39e8 # macro
|
|
regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_BUF0_SIZE = 0x39e9 # macro
|
|
regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_BUF1_BASE = 0x39ea # macro
|
|
regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_BUF1_SIZE = 0x39eb # macro
|
|
regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_CTRL = 0x39ec # macro
|
|
regSQ_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_MASK = 0x39ed # macro
|
|
regSQ_THREAD_TRACE_MASK_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_TOKEN_MASK = 0x39ee # macro
|
|
regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_WPTR = 0x39ef # macro
|
|
regSQ_THREAD_TRACE_WPTR_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_STATUS = 0x39f4 # macro
|
|
regSQ_THREAD_TRACE_STATUS_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_STATUS2 = 0x39f5 # macro
|
|
regSQ_THREAD_TRACE_STATUS2_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_GFX_DRAW_CNTR = 0x39f6 # macro
|
|
regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_GFX_MARKER_CNTR = 0x39f7 # macro
|
|
regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_HP3D_DRAW_CNTR = 0x39f8 # macro
|
|
regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_HP3D_MARKER_CNTR = 0x39f9 # macro
|
|
regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX = 1 # macro
|
|
regSQ_THREAD_TRACE_DROPPED_CNTR = 0x39fa # macro
|
|
regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX = 1 # macro
|
|
regGCEA_PERFCOUNTER2_SELECT = 0x3a00 # macro
|
|
regGCEA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regGCEA_PERFCOUNTER2_SELECT1 = 0x3a01 # macro
|
|
regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
|
|
regGCEA_PERFCOUNTER2_MODE = 0x3a02 # macro
|
|
regGCEA_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro
|
|
regGCEA_PERFCOUNTER0_CFG = 0x3a03 # macro
|
|
regGCEA_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
|
|
regGCEA_PERFCOUNTER1_CFG = 0x3a04 # macro
|
|
regGCEA_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
|
|
regGCEA_PERFCOUNTER_RSLT_CNTL = 0x3a05 # macro
|
|
regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER0_SELECT = 0x3a40 # macro
|
|
regSX_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER1_SELECT = 0x3a41 # macro
|
|
regSX_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER2_SELECT = 0x3a42 # macro
|
|
regSX_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER3_SELECT = 0x3a43 # macro
|
|
regSX_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER0_SELECT1 = 0x3a44 # macro
|
|
regSX_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regSX_PERFCOUNTER1_SELECT1 = 0x3a45 # macro
|
|
regSX_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER0_SELECT = 0x3a80 # macro
|
|
regGDS_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER1_SELECT = 0x3a81 # macro
|
|
regGDS_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER2_SELECT = 0x3a82 # macro
|
|
regGDS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER3_SELECT = 0x3a83 # macro
|
|
regGDS_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER0_SELECT1 = 0x3a84 # macro
|
|
regGDS_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER1_SELECT1 = 0x3a85 # macro
|
|
regGDS_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER2_SELECT1 = 0x3a86 # macro
|
|
regGDS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
|
|
regGDS_PERFCOUNTER3_SELECT1 = 0x3a87 # macro
|
|
regGDS_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
|
|
regTA_PERFCOUNTER0_SELECT = 0x3ac0 # macro
|
|
regTA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regTA_PERFCOUNTER0_SELECT1 = 0x3ac1 # macro
|
|
regTA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regTA_PERFCOUNTER1_SELECT = 0x3ac2 # macro
|
|
regTA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regTD_PERFCOUNTER0_SELECT = 0x3b00 # macro
|
|
regTD_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regTD_PERFCOUNTER0_SELECT1 = 0x3b01 # macro
|
|
regTD_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regTD_PERFCOUNTER1_SELECT = 0x3b02 # macro
|
|
regTD_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER0_SELECT = 0x3b40 # macro
|
|
regTCP_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER0_SELECT1 = 0x3b41 # macro
|
|
regTCP_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER1_SELECT = 0x3b42 # macro
|
|
regTCP_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER1_SELECT1 = 0x3b43 # macro
|
|
regTCP_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER2_SELECT = 0x3b44 # macro
|
|
regTCP_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regTCP_PERFCOUNTER3_SELECT = 0x3b45 # macro
|
|
regTCP_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER0_SELECT = 0x3b80 # macro
|
|
regGL2C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER0_SELECT1 = 0x3b81 # macro
|
|
regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER1_SELECT = 0x3b82 # macro
|
|
regGL2C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER1_SELECT1 = 0x3b83 # macro
|
|
regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER2_SELECT = 0x3b84 # macro
|
|
regGL2C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regGL2C_PERFCOUNTER3_SELECT = 0x3b85 # macro
|
|
regGL2C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER0_SELECT = 0x3b90 # macro
|
|
regGL2A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER0_SELECT1 = 0x3b91 # macro
|
|
regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER1_SELECT = 0x3b92 # macro
|
|
regGL2A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER1_SELECT1 = 0x3b93 # macro
|
|
regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER2_SELECT = 0x3b94 # macro
|
|
regGL2A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regGL2A_PERFCOUNTER3_SELECT = 0x3b95 # macro
|
|
regGL2A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regGL1C_PERFCOUNTER0_SELECT = 0x3ba0 # macro
|
|
regGL1C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regGL1C_PERFCOUNTER0_SELECT1 = 0x3ba1 # macro
|
|
regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regGL1C_PERFCOUNTER1_SELECT = 0x3ba2 # macro
|
|
regGL1C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regGL1C_PERFCOUNTER2_SELECT = 0x3ba3 # macro
|
|
regGL1C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regGL1C_PERFCOUNTER3_SELECT = 0x3ba4 # macro
|
|
regGL1C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regCHC_PERFCOUNTER0_SELECT = 0x3bc0 # macro
|
|
regCHC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regCHC_PERFCOUNTER0_SELECT1 = 0x3bc1 # macro
|
|
regCHC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regCHC_PERFCOUNTER1_SELECT = 0x3bc2 # macro
|
|
regCHC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regCHC_PERFCOUNTER2_SELECT = 0x3bc3 # macro
|
|
regCHC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regCHC_PERFCOUNTER3_SELECT = 0x3bc4 # macro
|
|
regCHC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regCHCG_PERFCOUNTER0_SELECT = 0x3bc6 # macro
|
|
regCHCG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regCHCG_PERFCOUNTER0_SELECT1 = 0x3bc7 # macro
|
|
regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regCHCG_PERFCOUNTER1_SELECT = 0x3bc8 # macro
|
|
regCHCG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regCHCG_PERFCOUNTER2_SELECT = 0x3bc9 # macro
|
|
regCHCG_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regCHCG_PERFCOUNTER3_SELECT = 0x3bca # macro
|
|
regCHCG_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER_FILTER = 0x3c00 # macro
|
|
regCB_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER0_SELECT = 0x3c01 # macro
|
|
regCB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER0_SELECT1 = 0x3c02 # macro
|
|
regCB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER1_SELECT = 0x3c03 # macro
|
|
regCB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER2_SELECT = 0x3c04 # macro
|
|
regCB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regCB_PERFCOUNTER3_SELECT = 0x3c05 # macro
|
|
regCB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER0_SELECT = 0x3c40 # macro
|
|
regDB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER0_SELECT1 = 0x3c41 # macro
|
|
regDB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER1_SELECT = 0x3c42 # macro
|
|
regDB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER1_SELECT1 = 0x3c43 # macro
|
|
regDB_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER2_SELECT = 0x3c44 # macro
|
|
regDB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regDB_PERFCOUNTER3_SELECT = 0x3c46 # macro
|
|
regDB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regRLC_SPM_PERFMON_CNTL = 0x3c80 # macro
|
|
regRLC_SPM_PERFMON_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_SPM_PERFMON_RING_BASE_LO = 0x3c81 # macro
|
|
regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX = 1 # macro
|
|
regRLC_SPM_PERFMON_RING_BASE_HI = 0x3c82 # macro
|
|
regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX = 1 # macro
|
|
regRLC_SPM_PERFMON_RING_SIZE = 0x3c83 # macro
|
|
regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX = 1 # macro
|
|
regRLC_SPM_RING_WRPTR = 0x3c84 # macro
|
|
regRLC_SPM_RING_WRPTR_BASE_IDX = 1 # macro
|
|
regRLC_SPM_RING_RDPTR = 0x3c85 # macro
|
|
regRLC_SPM_RING_RDPTR_BASE_IDX = 1 # macro
|
|
regRLC_SPM_SEGMENT_THRESHOLD = 0x3c86 # macro
|
|
regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX = 1 # macro
|
|
regRLC_SPM_PERFMON_SEGMENT_SIZE = 0x3c87 # macro
|
|
regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX = 1 # macro
|
|
regRLC_SPM_GLOBAL_MUXSEL_ADDR = 0x3c88 # macro
|
|
regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_SPM_GLOBAL_MUXSEL_DATA = 0x3c89 # macro
|
|
regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX = 1 # macro
|
|
regRLC_SPM_SE_MUXSEL_ADDR = 0x3c8a # macro
|
|
regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_SPM_SE_MUXSEL_DATA = 0x3c8b # macro
|
|
regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_DATARAM_ADDR = 0x3c92 # macro
|
|
regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_DATARAM_DATA = 0x3c93 # macro
|
|
regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_SWA_DATARAM_ADDR = 0x3c94 # macro
|
|
regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_SWA_DATARAM_DATA = 0x3c95 # macro
|
|
regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_CTRLRAM_ADDR = 0x3c96 # macro
|
|
regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_CTRLRAM_DATA = 0x3c97 # macro
|
|
regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET = 0x3c98 # macro
|
|
regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_STATUS = 0x3c99 # macro
|
|
regRLC_SPM_ACCUM_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_CTRL = 0x3c9a # macro
|
|
regRLC_SPM_ACCUM_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_MODE = 0x3c9b # macro
|
|
regRLC_SPM_ACCUM_MODE_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_THRESHOLD = 0x3c9c # macro
|
|
regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_SAMPLES_REQUESTED = 0x3c9d # macro
|
|
regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_DATARAM_WRCOUNT = 0x3c9e # macro
|
|
regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX = 1 # macro
|
|
regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS = 0x3c9f # macro
|
|
regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX = 1 # macro
|
|
regRLC_SPM_PAUSE = 0x3ca2 # macro
|
|
regRLC_SPM_PAUSE_BASE_IDX = 1 # macro
|
|
regRLC_SPM_STATUS = 0x3ca3 # macro
|
|
regRLC_SPM_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_SPM_GFXCLOCK_LOWCOUNT = 0x3ca4 # macro
|
|
regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX = 1 # macro
|
|
regRLC_SPM_GFXCLOCK_HIGHCOUNT = 0x3ca5 # macro
|
|
regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX = 1 # macro
|
|
regRLC_SPM_MODE = 0x3cad # macro
|
|
regRLC_SPM_MODE_BASE_IDX = 1 # macro
|
|
regRLC_SPM_RSPM_REQ_DATA_LO = 0x3cae # macro
|
|
regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_SPM_RSPM_REQ_DATA_HI = 0x3caf # macro
|
|
regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_SPM_RSPM_REQ_OP = 0x3cb0 # macro
|
|
regRLC_SPM_RSPM_REQ_OP_BASE_IDX = 1 # macro
|
|
regRLC_SPM_RSPM_RET_DATA = 0x3cb1 # macro
|
|
regRLC_SPM_RSPM_RET_DATA_BASE_IDX = 1 # macro
|
|
regRLC_SPM_RSPM_RET_OP = 0x3cb2 # macro
|
|
regRLC_SPM_RSPM_RET_OP_BASE_IDX = 1 # macro
|
|
regRLC_SPM_SE_RSPM_REQ_DATA_LO = 0x3cb3 # macro
|
|
regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_SPM_SE_RSPM_REQ_DATA_HI = 0x3cb4 # macro
|
|
regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_SPM_SE_RSPM_REQ_OP = 0x3cb5 # macro
|
|
regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX = 1 # macro
|
|
regRLC_SPM_SE_RSPM_RET_DATA = 0x3cb6 # macro
|
|
regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX = 1 # macro
|
|
regRLC_SPM_SE_RSPM_RET_OP = 0x3cb7 # macro
|
|
regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX = 1 # macro
|
|
regRLC_SPM_RSPM_CMD = 0x3cb8 # macro
|
|
regRLC_SPM_RSPM_CMD_BASE_IDX = 1 # macro
|
|
regRLC_SPM_RSPM_CMD_ACK = 0x3cb9 # macro
|
|
regRLC_SPM_RSPM_CMD_ACK_BASE_IDX = 1 # macro
|
|
regRLC_SPM_SPARE = 0x3cbf # macro
|
|
regRLC_SPM_SPARE_BASE_IDX = 1 # macro
|
|
regRLC_PERFMON_CNTL = 0x3cc0 # macro
|
|
regRLC_PERFMON_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_PERFCOUNTER0_SELECT = 0x3cc1 # macro
|
|
regRLC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regRLC_PERFCOUNTER1_SELECT = 0x3cc2 # macro
|
|
regRLC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_PERF_CNT_CNTL = 0x3cc3 # macro
|
|
regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_PERF_CNT_WR_ADDR = 0x3cc4 # macro
|
|
regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_PERF_CNT_WR_DATA = 0x3cc5 # macro
|
|
regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_PERF_CNT_RD_ADDR = 0x3cc6 # macro
|
|
regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_PERF_CNT_RD_DATA = 0x3cc7 # macro
|
|
regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER0_SELECT = 0x3d00 # macro
|
|
regRMI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER0_SELECT1 = 0x3d01 # macro
|
|
regRMI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER1_SELECT = 0x3d02 # macro
|
|
regRMI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER2_SELECT = 0x3d03 # macro
|
|
regRMI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER2_SELECT1 = 0x3d04 # macro
|
|
regRMI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
|
|
regRMI_PERFCOUNTER3_SELECT = 0x3d05 # macro
|
|
regRMI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regRMI_PERF_COUNTER_CNTL = 0x3d06 # macro
|
|
regRMI_PERF_COUNTER_CNTL_BASE_IDX = 1 # macro
|
|
regGCR_PERFCOUNTER0_SELECT = 0x3d60 # macro
|
|
regGCR_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regGCR_PERFCOUNTER0_SELECT1 = 0x3d61 # macro
|
|
regGCR_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regGCR_PERFCOUNTER1_SELECT = 0x3d62 # macro
|
|
regGCR_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER0_SELECT = 0x3d80 # macro
|
|
regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER0_SELECT1 = 0x3d81 # macro
|
|
regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER1_SELECT = 0x3d82 # macro
|
|
regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER2_SELECT = 0x3d83 # macro
|
|
regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER3_SELECT = 0x3d84 # macro
|
|
regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER4_SELECT = 0x3d85 # macro
|
|
regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER5_SELECT = 0x3d86 # macro
|
|
regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER6_SELECT = 0x3d87 # macro
|
|
regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER7_SELECT = 0x3d88 # macro
|
|
regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER1_SELECT1 = 0x3d90 # macro
|
|
regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER2_SELECT1 = 0x3d91 # macro
|
|
regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
|
|
regPA_PH_PERFCOUNTER3_SELECT1 = 0x3d92 # macro
|
|
regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro
|
|
regUTCL1_PERFCOUNTER0_SELECT = 0x3da0 # macro
|
|
regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regUTCL1_PERFCOUNTER1_SELECT = 0x3da1 # macro
|
|
regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regUTCL1_PERFCOUNTER2_SELECT = 0x3da2 # macro
|
|
regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regUTCL1_PERFCOUNTER3_SELECT = 0x3da3 # macro
|
|
regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regGL1A_PERFCOUNTER0_SELECT = 0x3dc0 # macro
|
|
regGL1A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regGL1A_PERFCOUNTER0_SELECT1 = 0x3dc1 # macro
|
|
regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regGL1A_PERFCOUNTER1_SELECT = 0x3dc2 # macro
|
|
regGL1A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regGL1A_PERFCOUNTER2_SELECT = 0x3dc3 # macro
|
|
regGL1A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regGL1A_PERFCOUNTER3_SELECT = 0x3dc4 # macro
|
|
regGL1A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regGL1H_PERFCOUNTER0_SELECT = 0x3dd0 # macro
|
|
regGL1H_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regGL1H_PERFCOUNTER0_SELECT1 = 0x3dd1 # macro
|
|
regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regGL1H_PERFCOUNTER1_SELECT = 0x3dd2 # macro
|
|
regGL1H_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regGL1H_PERFCOUNTER2_SELECT = 0x3dd3 # macro
|
|
regGL1H_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regGL1H_PERFCOUNTER3_SELECT = 0x3dd4 # macro
|
|
regGL1H_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regCHA_PERFCOUNTER0_SELECT = 0x3de0 # macro
|
|
regCHA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro
|
|
regCHA_PERFCOUNTER0_SELECT1 = 0x3de1 # macro
|
|
regCHA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro
|
|
regCHA_PERFCOUNTER1_SELECT = 0x3de2 # macro
|
|
regCHA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro
|
|
regCHA_PERFCOUNTER2_SELECT = 0x3de3 # macro
|
|
regCHA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regCHA_PERFCOUNTER3_SELECT = 0x3de4 # macro
|
|
regCHA_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro
|
|
regGUS_PERFCOUNTER2_SELECT = 0x3e00 # macro
|
|
regGUS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro
|
|
regGUS_PERFCOUNTER2_SELECT1 = 0x3e01 # macro
|
|
regGUS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro
|
|
regGUS_PERFCOUNTER2_MODE = 0x3e02 # macro
|
|
regGUS_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro
|
|
regGUS_PERFCOUNTER0_CFG = 0x3e03 # macro
|
|
regGUS_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro
|
|
regGUS_PERFCOUNTER1_CFG = 0x3e04 # macro
|
|
regGUS_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro
|
|
regGUS_PERFCOUNTER_RSLT_CNTL = 0x3e05 # macro
|
|
regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro
|
|
regGRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro
|
|
regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro
|
|
regGRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro
|
|
regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro
|
|
regGRTAVFS_GENERAL_0 = 0x4b02 # macro
|
|
regGRTAVFS_GENERAL_0_BASE_IDX = 1 # macro
|
|
regGRTAVFS_RTAVFS_RD_DATA = 0x4b03 # macro
|
|
regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX = 1 # macro
|
|
regGRTAVFS_RTAVFS_REG_CTRL = 0x4b04 # macro
|
|
regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX = 1 # macro
|
|
regGRTAVFS_RTAVFS_REG_STATUS = 0x4b05 # macro
|
|
regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX = 1 # macro
|
|
regGRTAVFS_TARG_FREQ = 0x4b06 # macro
|
|
regGRTAVFS_TARG_FREQ_BASE_IDX = 1 # macro
|
|
regGRTAVFS_TARG_VOLT = 0x4b07 # macro
|
|
regGRTAVFS_TARG_VOLT_BASE_IDX = 1 # macro
|
|
regGRTAVFS_SOFT_RESET = 0x4b0c # macro
|
|
regGRTAVFS_SOFT_RESET_BASE_IDX = 1 # macro
|
|
regGRTAVFS_PSM_CNTL = 0x4b0d # macro
|
|
regGRTAVFS_PSM_CNTL_BASE_IDX = 1 # macro
|
|
regGRTAVFS_CLK_CNTL = 0x4b0e # macro
|
|
regGRTAVFS_CLK_CNTL_BASE_IDX = 1 # macro
|
|
regGRTAVFS_SE_RTAVFS_REG_ADDR = 0x4b40 # macro
|
|
regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro
|
|
regGRTAVFS_SE_RTAVFS_WR_DATA = 0x4b41 # macro
|
|
regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX = 1 # macro
|
|
regGRTAVFS_SE_GENERAL_0 = 0x4b42 # macro
|
|
regGRTAVFS_SE_GENERAL_0_BASE_IDX = 1 # macro
|
|
regGRTAVFS_SE_RTAVFS_RD_DATA = 0x4b43 # macro
|
|
regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX = 1 # macro
|
|
regGRTAVFS_SE_RTAVFS_REG_CTRL = 0x4b44 # macro
|
|
regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX = 1 # macro
|
|
regGRTAVFS_SE_RTAVFS_REG_STATUS = 0x4b45 # macro
|
|
regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX = 1 # macro
|
|
regGRTAVFS_SE_TARG_FREQ = 0x4b46 # macro
|
|
regGRTAVFS_SE_TARG_FREQ_BASE_IDX = 1 # macro
|
|
regGRTAVFS_SE_TARG_VOLT = 0x4b47 # macro
|
|
regGRTAVFS_SE_TARG_VOLT_BASE_IDX = 1 # macro
|
|
regGRTAVFS_SE_SOFT_RESET = 0x4b4c # macro
|
|
regGRTAVFS_SE_SOFT_RESET_BASE_IDX = 1 # macro
|
|
regGRTAVFS_SE_PSM_CNTL = 0x4b4d # macro
|
|
regGRTAVFS_SE_PSM_CNTL_BASE_IDX = 1 # macro
|
|
regGRTAVFS_SE_CLK_CNTL = 0x4b4e # macro
|
|
regGRTAVFS_SE_CLK_CNTL_BASE_IDX = 1 # macro
|
|
regRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro
|
|
regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro
|
|
regRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro
|
|
regRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro
|
|
regCP_HYP_PFP_UCODE_ADDR = 0x5814 # macro
|
|
regCP_HYP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regCP_PFP_UCODE_ADDR = 0x5814 # macro
|
|
regCP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regCP_HYP_PFP_UCODE_DATA = 0x5815 # macro
|
|
regCP_HYP_PFP_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regCP_PFP_UCODE_DATA = 0x5815 # macro
|
|
regCP_PFP_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regCP_HYP_ME_UCODE_ADDR = 0x5816 # macro
|
|
regCP_HYP_ME_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regCP_ME_RAM_RADDR = 0x5816 # macro
|
|
regCP_ME_RAM_RADDR_BASE_IDX = 1 # macro
|
|
regCP_ME_RAM_WADDR = 0x5816 # macro
|
|
regCP_ME_RAM_WADDR_BASE_IDX = 1 # macro
|
|
regCP_HYP_ME_UCODE_DATA = 0x5817 # macro
|
|
regCP_HYP_ME_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regCP_ME_RAM_DATA = 0x5817 # macro
|
|
regCP_ME_RAM_DATA_BASE_IDX = 1 # macro
|
|
regCP_HYP_MEC1_UCODE_ADDR = 0x581a # macro
|
|
regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regCP_MEC_ME1_UCODE_ADDR = 0x581a # macro
|
|
regCP_MEC_ME1_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regCP_HYP_MEC1_UCODE_DATA = 0x581b # macro
|
|
regCP_HYP_MEC1_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regCP_MEC_ME1_UCODE_DATA = 0x581b # macro
|
|
regCP_MEC_ME1_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regCP_HYP_MEC2_UCODE_ADDR = 0x581c # macro
|
|
regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regCP_MEC_ME2_UCODE_ADDR = 0x581c # macro
|
|
regCP_MEC_ME2_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regCP_HYP_MEC2_UCODE_DATA = 0x581d # macro
|
|
regCP_HYP_MEC2_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regCP_MEC_ME2_UCODE_DATA = 0x581d # macro
|
|
regCP_MEC_ME2_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regCP_PFP_IC_BASE_LO = 0x5840 # macro
|
|
regCP_PFP_IC_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_PFP_IC_BASE_HI = 0x5841 # macro
|
|
regCP_PFP_IC_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_PFP_IC_BASE_CNTL = 0x5842 # macro
|
|
regCP_PFP_IC_BASE_CNTL_BASE_IDX = 1 # macro
|
|
regCP_PFP_IC_OP_CNTL = 0x5843 # macro
|
|
regCP_PFP_IC_OP_CNTL_BASE_IDX = 1 # macro
|
|
regCP_ME_IC_BASE_LO = 0x5844 # macro
|
|
regCP_ME_IC_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_ME_IC_BASE_HI = 0x5845 # macro
|
|
regCP_ME_IC_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_ME_IC_BASE_CNTL = 0x5846 # macro
|
|
regCP_ME_IC_BASE_CNTL_BASE_IDX = 1 # macro
|
|
regCP_ME_IC_OP_CNTL = 0x5847 # macro
|
|
regCP_ME_IC_OP_CNTL_BASE_IDX = 1 # macro
|
|
regCP_CPC_IC_BASE_LO = 0x584c # macro
|
|
regCP_CPC_IC_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_CPC_IC_BASE_HI = 0x584d # macro
|
|
regCP_CPC_IC_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_CPC_IC_BASE_CNTL = 0x584e # macro
|
|
regCP_CPC_IC_BASE_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_IC_BASE_LO = 0x5850 # macro
|
|
regCP_MES_IC_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MIBASE_LO = 0x5850 # macro
|
|
regCP_MES_MIBASE_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_IC_BASE_HI = 0x5851 # macro
|
|
regCP_MES_IC_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MIBASE_HI = 0x5851 # macro
|
|
regCP_MES_MIBASE_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_IC_BASE_CNTL = 0x5852 # macro
|
|
regCP_MES_IC_BASE_CNTL_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_BASE_LO = 0x5854 # macro
|
|
regCP_MES_DC_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MDBASE_LO = 0x5854 # macro
|
|
regCP_MES_MDBASE_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_DC_BASE_HI = 0x5855 # macro
|
|
regCP_MES_DC_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MDBASE_HI = 0x5855 # macro
|
|
regCP_MES_MDBASE_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MIBOUND_LO = 0x585b # macro
|
|
regCP_MES_MIBOUND_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MIBOUND_HI = 0x585c # macro
|
|
regCP_MES_MIBOUND_HI_BASE_IDX = 1 # macro
|
|
regCP_MES_MDBOUND_LO = 0x585d # macro
|
|
regCP_MES_MDBOUND_LO_BASE_IDX = 1 # macro
|
|
regCP_MES_MDBOUND_HI = 0x585e # macro
|
|
regCP_MES_MDBOUND_HI_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_BASE0_LO = 0x5863 # macro
|
|
regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_BASE1_LO = 0x5864 # macro
|
|
regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_BASE0_HI = 0x5865 # macro
|
|
regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DC_BASE1_HI = 0x5866 # macro
|
|
regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_MIBOUND_LO = 0x586c # macro
|
|
regCP_GFX_RS64_MIBOUND_LO_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_MIBOUND_HI = 0x586d # macro
|
|
regCP_GFX_RS64_MIBOUND_HI_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_BASE_LO = 0x5870 # macro
|
|
regCP_MEC_DC_BASE_LO_BASE_IDX = 1 # macro
|
|
regCP_MEC_MDBASE_LO = 0x5870 # macro
|
|
regCP_MEC_MDBASE_LO_BASE_IDX = 1 # macro
|
|
regCP_MEC_DC_BASE_HI = 0x5871 # macro
|
|
regCP_MEC_DC_BASE_HI_BASE_IDX = 1 # macro
|
|
regCP_MEC_MDBASE_HI = 0x5871 # macro
|
|
regCP_MEC_MDBASE_HI_BASE_IDX = 1 # macro
|
|
regCP_MEC_MIBOUND_LO = 0x5872 # macro
|
|
regCP_MEC_MIBOUND_LO_BASE_IDX = 1 # macro
|
|
regCP_MEC_MIBOUND_HI = 0x5873 # macro
|
|
regCP_MEC_MIBOUND_HI_BASE_IDX = 1 # macro
|
|
regCP_MEC_MDBOUND_LO = 0x5874 # macro
|
|
regCP_MEC_MDBOUND_LO_BASE_IDX = 1 # macro
|
|
regCP_MEC_MDBOUND_HI = 0x5875 # macro
|
|
regCP_MEC_MDBOUND_HI_BASE_IDX = 1 # macro
|
|
regRLC_CNTL = 0x4c00 # macro
|
|
regRLC_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_F32_UCODE_VERSION = 0x4c03 # macro
|
|
regRLC_F32_UCODE_VERSION_BASE_IDX = 1 # macro
|
|
regRLC_STAT = 0x4c04 # macro
|
|
regRLC_STAT_BASE_IDX = 1 # macro
|
|
regRLC_REFCLOCK_TIMESTAMP_LSB = 0x4c0c # macro
|
|
regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX = 1 # macro
|
|
regRLC_REFCLOCK_TIMESTAMP_MSB = 0x4c0d # macro
|
|
regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX = 1 # macro
|
|
regRLC_GPM_TIMER_INT_0 = 0x4c0e # macro
|
|
regRLC_GPM_TIMER_INT_0_BASE_IDX = 1 # macro
|
|
regRLC_GPM_TIMER_INT_1 = 0x4c0f # macro
|
|
regRLC_GPM_TIMER_INT_1_BASE_IDX = 1 # macro
|
|
regRLC_GPM_TIMER_INT_2 = 0x4c10 # macro
|
|
regRLC_GPM_TIMER_INT_2_BASE_IDX = 1 # macro
|
|
regRLC_GPM_TIMER_INT_3 = 0x4c11 # macro
|
|
regRLC_GPM_TIMER_INT_3_BASE_IDX = 1 # macro
|
|
regRLC_GPM_TIMER_INT_4 = 0x4c12 # macro
|
|
regRLC_GPM_TIMER_INT_4_BASE_IDX = 1 # macro
|
|
regRLC_GPM_TIMER_CTRL = 0x4c13 # macro
|
|
regRLC_GPM_TIMER_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_GPM_TIMER_STAT = 0x4c14 # macro
|
|
regRLC_GPM_TIMER_STAT_BASE_IDX = 1 # macro
|
|
regRLC_GPM_LEGACY_INT_STAT = 0x4c16 # macro
|
|
regRLC_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro
|
|
regRLC_GPM_LEGACY_INT_CLEAR = 0x4c17 # macro
|
|
regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX = 1 # macro
|
|
regRLC_INT_STAT = 0x4c18 # macro
|
|
regRLC_INT_STAT_BASE_IDX = 1 # macro
|
|
regRLC_MGCG_CTRL = 0x4c1a # macro
|
|
regRLC_MGCG_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_JUMP_TABLE_RESTORE = 0x4c1e # macro
|
|
regRLC_JUMP_TABLE_RESTORE_BASE_IDX = 1 # macro
|
|
regRLC_PG_DELAY_2 = 0x4c1f # macro
|
|
regRLC_PG_DELAY_2_BASE_IDX = 1 # macro
|
|
regRLC_GPU_CLOCK_COUNT_LSB = 0x4c24 # macro
|
|
regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX = 1 # macro
|
|
regRLC_GPU_CLOCK_COUNT_MSB = 0x4c25 # macro
|
|
regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX = 1 # macro
|
|
regRLC_CAPTURE_GPU_CLOCK_COUNT = 0x4c26 # macro
|
|
regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX = 1 # macro
|
|
regRLC_UCODE_CNTL = 0x4c27 # macro
|
|
regRLC_UCODE_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_GPM_THREAD_RESET = 0x4c28 # macro
|
|
regRLC_GPM_THREAD_RESET_BASE_IDX = 1 # macro
|
|
regRLC_GPM_CP_DMA_COMPLETE_T0 = 0x4c29 # macro
|
|
regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX = 1 # macro
|
|
regRLC_GPM_CP_DMA_COMPLETE_T1 = 0x4c2a # macro
|
|
regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX = 1 # macro
|
|
regRLC_GPM_THREAD_INVALIDATE_CACHE = 0x4c2b # macro
|
|
regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX = 1 # macro
|
|
regRLC_CLK_COUNT_GFXCLK_LSB = 0x4c30 # macro
|
|
regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX = 1 # macro
|
|
regRLC_CLK_COUNT_GFXCLK_MSB = 0x4c31 # macro
|
|
regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX = 1 # macro
|
|
regRLC_CLK_COUNT_REFCLK_LSB = 0x4c32 # macro
|
|
regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX = 1 # macro
|
|
regRLC_CLK_COUNT_REFCLK_MSB = 0x4c33 # macro
|
|
regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX = 1 # macro
|
|
regRLC_CLK_COUNT_CTRL = 0x4c34 # macro
|
|
regRLC_CLK_COUNT_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_CLK_COUNT_STAT = 0x4c35 # macro
|
|
regRLC_CLK_COUNT_STAT_BASE_IDX = 1 # macro
|
|
regRLC_RLCG_DOORBELL_CNTL = 0x4c36 # macro
|
|
regRLC_RLCG_DOORBELL_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_RLCG_DOORBELL_STAT = 0x4c37 # macro
|
|
regRLC_RLCG_DOORBELL_STAT_BASE_IDX = 1 # macro
|
|
regRLC_RLCG_DOORBELL_0_DATA_LO = 0x4c38 # macro
|
|
regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_RLCG_DOORBELL_0_DATA_HI = 0x4c39 # macro
|
|
regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_RLCG_DOORBELL_1_DATA_LO = 0x4c3a # macro
|
|
regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_RLCG_DOORBELL_1_DATA_HI = 0x4c3b # macro
|
|
regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_RLCG_DOORBELL_2_DATA_LO = 0x4c3c # macro
|
|
regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_RLCG_DOORBELL_2_DATA_HI = 0x4c3d # macro
|
|
regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_RLCG_DOORBELL_3_DATA_LO = 0x4c3e # macro
|
|
regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_RLCG_DOORBELL_3_DATA_HI = 0x4c3f # macro
|
|
regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_GPU_CLOCK_32_RES_SEL = 0x4c41 # macro
|
|
regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX = 1 # macro
|
|
regRLC_GPU_CLOCK_32 = 0x4c42 # macro
|
|
regRLC_GPU_CLOCK_32_BASE_IDX = 1 # macro
|
|
regRLC_PG_CNTL = 0x4c43 # macro
|
|
regRLC_PG_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_GPM_THREAD_PRIORITY = 0x4c44 # macro
|
|
regRLC_GPM_THREAD_PRIORITY_BASE_IDX = 1 # macro
|
|
regRLC_GPM_THREAD_ENABLE = 0x4c45 # macro
|
|
regRLC_GPM_THREAD_ENABLE_BASE_IDX = 1 # macro
|
|
regRLC_RLCG_DOORBELL_RANGE = 0x4c47 # macro
|
|
regRLC_RLCG_DOORBELL_RANGE_BASE_IDX = 1 # macro
|
|
regRLC_CGTT_MGCG_OVERRIDE = 0x4c48 # macro
|
|
regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX = 1 # macro
|
|
regRLC_CGCG_CGLS_CTRL = 0x4c49 # macro
|
|
regRLC_CGCG_CGLS_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_CGCG_RAMP_CTRL = 0x4c4a # macro
|
|
regRLC_CGCG_RAMP_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_DYN_PG_STATUS = 0x4c4b # macro
|
|
regRLC_DYN_PG_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_DYN_PG_REQUEST = 0x4c4c # macro
|
|
regRLC_DYN_PG_REQUEST_BASE_IDX = 1 # macro
|
|
regRLC_PG_DELAY = 0x4c4d # macro
|
|
regRLC_PG_DELAY_BASE_IDX = 1 # macro
|
|
regRLC_WGP_STATUS = 0x4c4e # macro
|
|
regRLC_WGP_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_PG_ALWAYS_ON_WGP_MASK = 0x4c53 # macro
|
|
regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX = 1 # macro
|
|
regRLC_MAX_PG_WGP = 0x4c54 # macro
|
|
regRLC_MAX_PG_WGP_BASE_IDX = 1 # macro
|
|
regRLC_AUTO_PG_CTRL = 0x4c55 # macro
|
|
regRLC_AUTO_PG_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_SERDES_RD_INDEX = 0x4c59 # macro
|
|
regRLC_SERDES_RD_INDEX_BASE_IDX = 1 # macro
|
|
regRLC_SERDES_RD_DATA_0 = 0x4c5a # macro
|
|
regRLC_SERDES_RD_DATA_0_BASE_IDX = 1 # macro
|
|
regRLC_SERDES_RD_DATA_1 = 0x4c5b # macro
|
|
regRLC_SERDES_RD_DATA_1_BASE_IDX = 1 # macro
|
|
regRLC_SERDES_RD_DATA_2 = 0x4c5c # macro
|
|
regRLC_SERDES_RD_DATA_2_BASE_IDX = 1 # macro
|
|
regRLC_SERDES_RD_DATA_3 = 0x4c5d # macro
|
|
regRLC_SERDES_RD_DATA_3_BASE_IDX = 1 # macro
|
|
regRLC_SERDES_MASK = 0x4c5e # macro
|
|
regRLC_SERDES_MASK_BASE_IDX = 1 # macro
|
|
regRLC_SERDES_CTRL = 0x4c5f # macro
|
|
regRLC_SERDES_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_SERDES_DATA = 0x4c60 # macro
|
|
regRLC_SERDES_DATA_BASE_IDX = 1 # macro
|
|
regRLC_SERDES_BUSY = 0x4c61 # macro
|
|
regRLC_SERDES_BUSY_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_0 = 0x4c63 # macro
|
|
regRLC_GPM_GENERAL_0_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_1 = 0x4c64 # macro
|
|
regRLC_GPM_GENERAL_1_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_2 = 0x4c65 # macro
|
|
regRLC_GPM_GENERAL_2_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_3 = 0x4c66 # macro
|
|
regRLC_GPM_GENERAL_3_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_4 = 0x4c67 # macro
|
|
regRLC_GPM_GENERAL_4_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_5 = 0x4c68 # macro
|
|
regRLC_GPM_GENERAL_5_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_6 = 0x4c69 # macro
|
|
regRLC_GPM_GENERAL_6_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_7 = 0x4c6a # macro
|
|
regRLC_GPM_GENERAL_7_BASE_IDX = 1 # macro
|
|
regRLC_STATIC_PG_STATUS = 0x4c6e # macro
|
|
regRLC_STATIC_PG_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_16 = 0x4c76 # macro
|
|
regRLC_GPM_GENERAL_16_BASE_IDX = 1 # macro
|
|
regRLC_PG_DELAY_3 = 0x4c78 # macro
|
|
regRLC_PG_DELAY_3_BASE_IDX = 1 # macro
|
|
regRLC_GPR_REG1 = 0x4c79 # macro
|
|
regRLC_GPR_REG1_BASE_IDX = 1 # macro
|
|
regRLC_GPR_REG2 = 0x4c7a # macro
|
|
regRLC_GPR_REG2_BASE_IDX = 1 # macro
|
|
regRLC_GPM_INT_DISABLE_TH0 = 0x4c7c # macro
|
|
regRLC_GPM_INT_DISABLE_TH0_BASE_IDX = 1 # macro
|
|
regRLC_GPM_LEGACY_INT_DISABLE = 0x4c7d # macro
|
|
regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro
|
|
regRLC_GPM_INT_FORCE_TH0 = 0x4c7e # macro
|
|
regRLC_GPM_INT_FORCE_TH0_BASE_IDX = 1 # macro
|
|
regRLC_SRM_CNTL = 0x4c80 # macro
|
|
regRLC_SRM_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_SRM_GPM_COMMAND_STATUS = 0x4c88 # macro
|
|
regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_0 = 0x4c8b # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_1 = 0x4c8c # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_2 = 0x4c8d # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_3 = 0x4c8e # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_4 = 0x4c8f # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_5 = 0x4c90 # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_6 = 0x4c91 # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_7 = 0x4c92 # macro
|
|
regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_0 = 0x4c93 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_1 = 0x4c94 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_2 = 0x4c95 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_3 = 0x4c96 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_4 = 0x4c97 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_5 = 0x4c98 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_6 = 0x4c99 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX = 1 # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_7 = 0x4c9a # macro
|
|
regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX = 1 # macro
|
|
regRLC_SRM_STAT = 0x4c9b # macro
|
|
regRLC_SRM_STAT_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_8 = 0x4cad # macro
|
|
regRLC_GPM_GENERAL_8_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_9 = 0x4cae # macro
|
|
regRLC_GPM_GENERAL_9_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_10 = 0x4caf # macro
|
|
regRLC_GPM_GENERAL_10_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_11 = 0x4cb0 # macro
|
|
regRLC_GPM_GENERAL_11_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_12 = 0x4cb1 # macro
|
|
regRLC_GPM_GENERAL_12_BASE_IDX = 1 # macro
|
|
regRLC_GPM_UTCL1_CNTL_0 = 0x4cb2 # macro
|
|
regRLC_GPM_UTCL1_CNTL_0_BASE_IDX = 1 # macro
|
|
regRLC_GPM_UTCL1_CNTL_1 = 0x4cb3 # macro
|
|
regRLC_GPM_UTCL1_CNTL_1_BASE_IDX = 1 # macro
|
|
regRLC_GPM_UTCL1_CNTL_2 = 0x4cb4 # macro
|
|
regRLC_GPM_UTCL1_CNTL_2_BASE_IDX = 1 # macro
|
|
regRLC_SPM_UTCL1_CNTL = 0x4cb5 # macro
|
|
regRLC_SPM_UTCL1_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_UTCL1_STATUS_2 = 0x4cb6 # macro
|
|
regRLC_UTCL1_STATUS_2_BASE_IDX = 1 # macro
|
|
regRLC_SPM_UTCL1_ERROR_1 = 0x4cbc # macro
|
|
regRLC_SPM_UTCL1_ERROR_1_BASE_IDX = 1 # macro
|
|
regRLC_SPM_UTCL1_ERROR_2 = 0x4cbd # macro
|
|
regRLC_SPM_UTCL1_ERROR_2_BASE_IDX = 1 # macro
|
|
regRLC_GPM_UTCL1_TH0_ERROR_1 = 0x4cbe # macro
|
|
regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX = 1 # macro
|
|
regRLC_GPM_UTCL1_TH0_ERROR_2 = 0x4cc0 # macro
|
|
regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX = 1 # macro
|
|
regRLC_GPM_UTCL1_TH1_ERROR_1 = 0x4cc1 # macro
|
|
regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX = 1 # macro
|
|
regRLC_GPM_UTCL1_TH1_ERROR_2 = 0x4cc2 # macro
|
|
regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX = 1 # macro
|
|
regRLC_GPM_UTCL1_TH2_ERROR_1 = 0x4cc3 # macro
|
|
regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX = 1 # macro
|
|
regRLC_GPM_UTCL1_TH2_ERROR_2 = 0x4cc4 # macro
|
|
regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX = 1 # macro
|
|
regRLC_CGCG_CGLS_CTRL_3D = 0x4cc5 # macro
|
|
regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX = 1 # macro
|
|
regRLC_CGCG_RAMP_CTRL_3D = 0x4cc6 # macro
|
|
regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX = 1 # macro
|
|
regRLC_SEMAPHORE_0 = 0x4cc7 # macro
|
|
regRLC_SEMAPHORE_0_BASE_IDX = 1 # macro
|
|
regRLC_SEMAPHORE_1 = 0x4cc8 # macro
|
|
regRLC_SEMAPHORE_1_BASE_IDX = 1 # macro
|
|
regRLC_SEMAPHORE_2 = 0x4cc9 # macro
|
|
regRLC_SEMAPHORE_2_BASE_IDX = 1 # macro
|
|
regRLC_SEMAPHORE_3 = 0x4cca # macro
|
|
regRLC_SEMAPHORE_3_BASE_IDX = 1 # macro
|
|
regRLC_PACE_INT_STAT = 0x4ccc # macro
|
|
regRLC_PACE_INT_STAT_BASE_IDX = 1 # macro
|
|
regRLC_UTCL1_STATUS = 0x4cd4 # macro
|
|
regRLC_UTCL1_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_R2I_CNTL_0 = 0x4cd5 # macro
|
|
regRLC_R2I_CNTL_0_BASE_IDX = 1 # macro
|
|
regRLC_R2I_CNTL_1 = 0x4cd6 # macro
|
|
regRLC_R2I_CNTL_1_BASE_IDX = 1 # macro
|
|
regRLC_R2I_CNTL_2 = 0x4cd7 # macro
|
|
regRLC_R2I_CNTL_2_BASE_IDX = 1 # macro
|
|
regRLC_R2I_CNTL_3 = 0x4cd8 # macro
|
|
regRLC_R2I_CNTL_3_BASE_IDX = 1 # macro
|
|
regRLC_GPM_INT_STAT_TH0 = 0x4cdc # macro
|
|
regRLC_GPM_INT_STAT_TH0_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_13 = 0x4cdd # macro
|
|
regRLC_GPM_GENERAL_13_BASE_IDX = 1 # macro
|
|
regRLC_GPM_GENERAL_14 = 0x4cde # macro
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regRLC_GPM_GENERAL_14_BASE_IDX = 1 # macro
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regRLC_GPM_GENERAL_15 = 0x4cdf # macro
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|
regRLC_GPM_GENERAL_15_BASE_IDX = 1 # macro
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regRLC_CAPTURE_GPU_CLOCK_COUNT_1 = 0x4cea # macro
|
|
regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX = 1 # macro
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|
regRLC_GPU_CLOCK_COUNT_LSB_2 = 0x4ceb # macro
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regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX = 1 # macro
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regRLC_GPU_CLOCK_COUNT_MSB_2 = 0x4cec # macro
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regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX = 1 # macro
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regRLC_PACE_INT_DISABLE = 0x4ced # macro
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|
regRLC_PACE_INT_DISABLE_BASE_IDX = 1 # macro
|
|
regRLC_CAPTURE_GPU_CLOCK_COUNT_2 = 0x4cef # macro
|
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regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX = 1 # macro
|
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regRLC_RLCV_DOORBELL_RANGE = 0x4cf0 # macro
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|
regRLC_RLCV_DOORBELL_RANGE_BASE_IDX = 1 # macro
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|
regRLC_RLCV_DOORBELL_CNTL = 0x4cf1 # macro
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|
regRLC_RLCV_DOORBELL_CNTL_BASE_IDX = 1 # macro
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|
regRLC_RLCV_DOORBELL_STAT = 0x4cf2 # macro
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|
regRLC_RLCV_DOORBELL_STAT_BASE_IDX = 1 # macro
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|
regRLC_RLCV_DOORBELL_0_DATA_LO = 0x4cf3 # macro
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|
regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro
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regRLC_RLCV_DOORBELL_0_DATA_HI = 0x4cf4 # macro
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regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro
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regRLC_RLCV_DOORBELL_1_DATA_LO = 0x4cf5 # macro
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|
regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro
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regRLC_RLCV_DOORBELL_1_DATA_HI = 0x4cf6 # macro
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|
regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro
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|
regRLC_RLCV_DOORBELL_2_DATA_LO = 0x4cf7 # macro
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|
regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro
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regRLC_RLCV_DOORBELL_2_DATA_HI = 0x4cf8 # macro
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|
regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro
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regRLC_RLCV_DOORBELL_3_DATA_LO = 0x4cf9 # macro
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|
regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro
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regRLC_RLCV_DOORBELL_3_DATA_HI = 0x4cfa # macro
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|
regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro
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|
regRLC_GPU_CLOCK_COUNT_LSB_1 = 0x4cfb # macro
|
|
regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX = 1 # macro
|
|
regRLC_GPU_CLOCK_COUNT_MSB_1 = 0x4cfc # macro
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|
regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX = 1 # macro
|
|
regRLC_RLCV_SPARE_INT = 0x4d00 # macro
|
|
regRLC_RLCV_SPARE_INT_BASE_IDX = 1 # macro
|
|
regRLC_PACE_TIMER_INT_0 = 0x4d04 # macro
|
|
regRLC_PACE_TIMER_INT_0_BASE_IDX = 1 # macro
|
|
regRLC_PACE_TIMER_INT_1 = 0x4d05 # macro
|
|
regRLC_PACE_TIMER_INT_1_BASE_IDX = 1 # macro
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|
regRLC_PACE_TIMER_CTRL = 0x4d06 # macro
|
|
regRLC_PACE_TIMER_CTRL_BASE_IDX = 1 # macro
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|
regRLC_SMU_CLK_REQ = 0x4d08 # macro
|
|
regRLC_SMU_CLK_REQ_BASE_IDX = 1 # macro
|
|
regRLC_CP_STAT_INVAL_STAT = 0x4d09 # macro
|
|
regRLC_CP_STAT_INVAL_STAT_BASE_IDX = 1 # macro
|
|
regRLC_CP_STAT_INVAL_CTRL = 0x4d0a # macro
|
|
regRLC_CP_STAT_INVAL_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_SPARE = 0x4d0b # macro
|
|
regRLC_SPARE_BASE_IDX = 1 # macro
|
|
regRLC_SPP_CTRL = 0x4d0c # macro
|
|
regRLC_SPP_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_SPP_SHADER_PROFILE_EN = 0x4d0d # macro
|
|
regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX = 1 # macro
|
|
regRLC_SPP_SSF_CAPTURE_EN = 0x4d0e # macro
|
|
regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX = 1 # macro
|
|
regRLC_SPP_SSF_THRESHOLD_0 = 0x4d0f # macro
|
|
regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX = 1 # macro
|
|
regRLC_SPP_SSF_THRESHOLD_1 = 0x4d10 # macro
|
|
regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX = 1 # macro
|
|
regRLC_SPP_SSF_THRESHOLD_2 = 0x4d11 # macro
|
|
regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX = 1 # macro
|
|
regRLC_SPP_INFLIGHT_RD_ADDR = 0x4d12 # macro
|
|
regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_SPP_INFLIGHT_RD_DATA = 0x4d13 # macro
|
|
regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX = 1 # macro
|
|
regRLC_SPP_PROF_INFO_1 = 0x4d18 # macro
|
|
regRLC_SPP_PROF_INFO_1_BASE_IDX = 1 # macro
|
|
regRLC_SPP_PROF_INFO_2 = 0x4d19 # macro
|
|
regRLC_SPP_PROF_INFO_2_BASE_IDX = 1 # macro
|
|
regRLC_SPP_GLOBAL_SH_ID = 0x4d1a # macro
|
|
regRLC_SPP_GLOBAL_SH_ID_BASE_IDX = 1 # macro
|
|
regRLC_SPP_GLOBAL_SH_ID_VALID = 0x4d1b # macro
|
|
regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX = 1 # macro
|
|
regRLC_SPP_STATUS = 0x4d1c # macro
|
|
regRLC_SPP_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_SPP_PVT_STAT_0 = 0x4d1d # macro
|
|
regRLC_SPP_PVT_STAT_0_BASE_IDX = 1 # macro
|
|
regRLC_SPP_PVT_STAT_1 = 0x4d1e # macro
|
|
regRLC_SPP_PVT_STAT_1_BASE_IDX = 1 # macro
|
|
regRLC_SPP_PVT_STAT_2 = 0x4d1f # macro
|
|
regRLC_SPP_PVT_STAT_2_BASE_IDX = 1 # macro
|
|
regRLC_SPP_PVT_STAT_3 = 0x4d20 # macro
|
|
regRLC_SPP_PVT_STAT_3_BASE_IDX = 1 # macro
|
|
regRLC_SPP_PVT_LEVEL_MAX = 0x4d21 # macro
|
|
regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX = 1 # macro
|
|
regRLC_SPP_STALL_STATE_UPDATE = 0x4d22 # macro
|
|
regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX = 1 # macro
|
|
regRLC_SPP_PBB_INFO = 0x4d23 # macro
|
|
regRLC_SPP_PBB_INFO_BASE_IDX = 1 # macro
|
|
regRLC_SPP_RESET = 0x4d24 # macro
|
|
regRLC_SPP_RESET_BASE_IDX = 1 # macro
|
|
regRLC_RLCP_DOORBELL_RANGE = 0x4d26 # macro
|
|
regRLC_RLCP_DOORBELL_RANGE_BASE_IDX = 1 # macro
|
|
regRLC_RLCP_DOORBELL_CNTL = 0x4d27 # macro
|
|
regRLC_RLCP_DOORBELL_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_RLCP_DOORBELL_STAT = 0x4d28 # macro
|
|
regRLC_RLCP_DOORBELL_STAT_BASE_IDX = 1 # macro
|
|
regRLC_RLCP_DOORBELL_0_DATA_LO = 0x4d29 # macro
|
|
regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_RLCP_DOORBELL_0_DATA_HI = 0x4d2a # macro
|
|
regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_RLCP_DOORBELL_1_DATA_LO = 0x4d2b # macro
|
|
regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_RLCP_DOORBELL_1_DATA_HI = 0x4d2c # macro
|
|
regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_RLCP_DOORBELL_2_DATA_LO = 0x4d2d # macro
|
|
regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_RLCP_DOORBELL_2_DATA_HI = 0x4d2e # macro
|
|
regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_RLCP_DOORBELL_3_DATA_LO = 0x4d2f # macro
|
|
regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_RLCP_DOORBELL_3_DATA_HI = 0x4d30 # macro
|
|
regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_CAC_MASK_CNTL = 0x4d45 # macro
|
|
regRLC_CAC_MASK_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_POWER_RESIDENCY_CNTR_CTRL = 0x4d48 # macro
|
|
regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_CLK_RESIDENCY_CNTR_CTRL = 0x4d49 # macro
|
|
regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_DS_RESIDENCY_CNTR_CTRL = 0x4d4a # macro
|
|
regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_ULV_RESIDENCY_CNTR_CTRL = 0x4d4b # macro
|
|
regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_PCC_RESIDENCY_CNTR_CTRL = 0x4d4c # macro
|
|
regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_GENERAL_RESIDENCY_CNTR_CTRL = 0x4d4d # macro
|
|
regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_POWER_RESIDENCY_EVENT_CNTR = 0x4d50 # macro
|
|
regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro
|
|
regRLC_CLK_RESIDENCY_EVENT_CNTR = 0x4d51 # macro
|
|
regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro
|
|
regRLC_DS_RESIDENCY_EVENT_CNTR = 0x4d52 # macro
|
|
regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro
|
|
regRLC_ULV_RESIDENCY_EVENT_CNTR = 0x4d53 # macro
|
|
regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro
|
|
regRLC_PCC_RESIDENCY_EVENT_CNTR = 0x4d54 # macro
|
|
regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro
|
|
regRLC_GENERAL_RESIDENCY_EVENT_CNTR = 0x4d55 # macro
|
|
regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro
|
|
regRLC_POWER_RESIDENCY_REF_CNTR = 0x4d58 # macro
|
|
regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro
|
|
regRLC_CLK_RESIDENCY_REF_CNTR = 0x4d59 # macro
|
|
regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro
|
|
regRLC_DS_RESIDENCY_REF_CNTR = 0x4d5a # macro
|
|
regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro
|
|
regRLC_ULV_RESIDENCY_REF_CNTR = 0x4d5b # macro
|
|
regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro
|
|
regRLC_PCC_RESIDENCY_REF_CNTR = 0x4d5c # macro
|
|
regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro
|
|
regRLC_GENERAL_RESIDENCY_REF_CNTR = 0x4d5d # macro
|
|
regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro
|
|
regRLC_GFX_IH_CLIENT_CTRL = 0x4d5e # macro
|
|
regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_GFX_IH_ARBITER_STAT = 0x4d5f # macro
|
|
regRLC_GFX_IH_ARBITER_STAT_BASE_IDX = 1 # macro
|
|
regRLC_GFX_IH_CLIENT_SE_STAT_L = 0x4d60 # macro
|
|
regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX = 1 # macro
|
|
regRLC_GFX_IH_CLIENT_SE_STAT_H = 0x4d61 # macro
|
|
regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX = 1 # macro
|
|
regRLC_GFX_IH_CLIENT_SDMA_STAT = 0x4d62 # macro
|
|
regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX = 1 # macro
|
|
regRLC_GFX_IH_CLIENT_OTHER_STAT = 0x4d63 # macro
|
|
regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX = 1 # macro
|
|
regRLC_SPM_GLOBAL_DELAY_IND_ADDR = 0x4d64 # macro
|
|
regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_SPM_GLOBAL_DELAY_IND_DATA = 0x4d65 # macro
|
|
regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX = 1 # macro
|
|
regRLC_SPM_SE_DELAY_IND_ADDR = 0x4d66 # macro
|
|
regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_SPM_SE_DELAY_IND_DATA = 0x4d67 # macro
|
|
regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX = 1 # macro
|
|
regRLC_LX6_CNTL = 0x4d80 # macro
|
|
regRLC_LX6_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_XT_CORE_STATUS = 0x4dd4 # macro
|
|
regRLC_XT_CORE_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_XT_CORE_INTERRUPT = 0x4dd5 # macro
|
|
regRLC_XT_CORE_INTERRUPT_BASE_IDX = 1 # macro
|
|
regRLC_XT_CORE_FAULT_INFO = 0x4dd6 # macro
|
|
regRLC_XT_CORE_FAULT_INFO_BASE_IDX = 1 # macro
|
|
regRLC_XT_CORE_ALT_RESET_VEC = 0x4dd7 # macro
|
|
regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX = 1 # macro
|
|
regRLC_XT_CORE_RESERVED = 0x4dd8 # macro
|
|
regRLC_XT_CORE_RESERVED_BASE_IDX = 1 # macro
|
|
regRLC_XT_INT_VEC_FORCE = 0x4dd9 # macro
|
|
regRLC_XT_INT_VEC_FORCE_BASE_IDX = 1 # macro
|
|
regRLC_XT_INT_VEC_CLEAR = 0x4dda # macro
|
|
regRLC_XT_INT_VEC_CLEAR_BASE_IDX = 1 # macro
|
|
regRLC_XT_INT_VEC_MUX_SEL = 0x4ddb # macro
|
|
regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX = 1 # macro
|
|
regRLC_XT_INT_VEC_MUX_INT_SEL = 0x4ddc # macro
|
|
regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX = 1 # macro
|
|
regRLC_GPU_CLOCK_COUNT_SPM_LSB = 0x4de4 # macro
|
|
regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX = 1 # macro
|
|
regRLC_GPU_CLOCK_COUNT_SPM_MSB = 0x4de5 # macro
|
|
regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX = 1 # macro
|
|
regRLC_SPM_THREAD_TRACE_CTRL = 0x4de6 # macro
|
|
regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_SPP_CAM_ADDR = 0x4de8 # macro
|
|
regRLC_SPP_CAM_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_SPP_CAM_DATA = 0x4de9 # macro
|
|
regRLC_SPP_CAM_DATA_BASE_IDX = 1 # macro
|
|
regRLC_SPP_CAM_EXT_ADDR = 0x4dea # macro
|
|
regRLC_SPP_CAM_EXT_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_SPP_CAM_EXT_DATA = 0x4deb # macro
|
|
regRLC_SPP_CAM_EXT_DATA_BASE_IDX = 1 # macro
|
|
regRLC_XT_DOORBELL_RANGE = 0x4df5 # macro
|
|
regRLC_XT_DOORBELL_RANGE_BASE_IDX = 1 # macro
|
|
regRLC_XT_DOORBELL_CNTL = 0x4df6 # macro
|
|
regRLC_XT_DOORBELL_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_XT_DOORBELL_STAT = 0x4df7 # macro
|
|
regRLC_XT_DOORBELL_STAT_BASE_IDX = 1 # macro
|
|
regRLC_XT_DOORBELL_0_DATA_LO = 0x4df8 # macro
|
|
regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_XT_DOORBELL_0_DATA_HI = 0x4df9 # macro
|
|
regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_XT_DOORBELL_1_DATA_LO = 0x4dfa # macro
|
|
regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_XT_DOORBELL_1_DATA_HI = 0x4dfb # macro
|
|
regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_XT_DOORBELL_2_DATA_LO = 0x4dfc # macro
|
|
regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_XT_DOORBELL_2_DATA_HI = 0x4dfd # macro
|
|
regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_XT_DOORBELL_3_DATA_LO = 0x4dfe # macro
|
|
regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro
|
|
regRLC_XT_DOORBELL_3_DATA_HI = 0x4dff # macro
|
|
regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro
|
|
regRLC_MEM_SLP_CNTL = 0x4e00 # macro
|
|
regRLC_MEM_SLP_CNTL_BASE_IDX = 1 # macro
|
|
regSMU_RLC_RESPONSE = 0x4e01 # macro
|
|
regSMU_RLC_RESPONSE_BASE_IDX = 1 # macro
|
|
regRLC_RLCV_SAFE_MODE = 0x4e02 # macro
|
|
regRLC_RLCV_SAFE_MODE_BASE_IDX = 1 # macro
|
|
regRLC_SMU_SAFE_MODE = 0x4e03 # macro
|
|
regRLC_SMU_SAFE_MODE_BASE_IDX = 1 # macro
|
|
regRLC_RLCV_COMMAND = 0x4e04 # macro
|
|
regRLC_RLCV_COMMAND_BASE_IDX = 1 # macro
|
|
regRLC_SMU_MESSAGE = 0x4e05 # macro
|
|
regRLC_SMU_MESSAGE_BASE_IDX = 1 # macro
|
|
regRLC_SMU_MESSAGE_1 = 0x4e06 # macro
|
|
regRLC_SMU_MESSAGE_1_BASE_IDX = 1 # macro
|
|
regRLC_SMU_MESSAGE_2 = 0x4e07 # macro
|
|
regRLC_SMU_MESSAGE_2_BASE_IDX = 1 # macro
|
|
regRLC_SRM_GPM_COMMAND = 0x4e08 # macro
|
|
regRLC_SRM_GPM_COMMAND_BASE_IDX = 1 # macro
|
|
regRLC_SRM_GPM_ABORT = 0x4e09 # macro
|
|
regRLC_SRM_GPM_ABORT_BASE_IDX = 1 # macro
|
|
regRLC_SMU_COMMAND = 0x4e0a # macro
|
|
regRLC_SMU_COMMAND_BASE_IDX = 1 # macro
|
|
regRLC_SMU_ARGUMENT_1 = 0x4e0b # macro
|
|
regRLC_SMU_ARGUMENT_1_BASE_IDX = 1 # macro
|
|
regRLC_SMU_ARGUMENT_2 = 0x4e0c # macro
|
|
regRLC_SMU_ARGUMENT_2_BASE_IDX = 1 # macro
|
|
regRLC_SMU_ARGUMENT_3 = 0x4e0d # macro
|
|
regRLC_SMU_ARGUMENT_3_BASE_IDX = 1 # macro
|
|
regRLC_SMU_ARGUMENT_4 = 0x4e0e # macro
|
|
regRLC_SMU_ARGUMENT_4_BASE_IDX = 1 # macro
|
|
regRLC_SMU_ARGUMENT_5 = 0x4e0f # macro
|
|
regRLC_SMU_ARGUMENT_5_BASE_IDX = 1 # macro
|
|
regRLC_IMU_BOOTLOAD_ADDR_HI = 0x4e10 # macro
|
|
regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX = 1 # macro
|
|
regRLC_IMU_BOOTLOAD_ADDR_LO = 0x4e11 # macro
|
|
regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX = 1 # macro
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regRLC_IMU_BOOTLOAD_SIZE = 0x4e12 # macro
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regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX = 1 # macro
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regRLC_IMU_MISC = 0x4e16 # macro
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regRLC_IMU_MISC_BASE_IDX = 1 # macro
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regRLC_IMU_RESET_VECTOR = 0x4e17 # macro
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regRLC_IMU_RESET_VECTOR_BASE_IDX = 1 # macro
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regRLC_RLCS_DEC_START = 0x4e60 # macro
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regRLC_RLCS_DEC_START_BASE_IDX = 1 # macro
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regRLC_RLCS_DEC_DUMP_ADDR = 0x4e61 # macro
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regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX = 1 # macro
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regRLC_RLCS_EXCEPTION_REG_1 = 0x4e62 # macro
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regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX = 1 # macro
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regRLC_RLCS_EXCEPTION_REG_2 = 0x4e63 # macro
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regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX = 1 # macro
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regRLC_RLCS_EXCEPTION_REG_3 = 0x4e64 # macro
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regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX = 1 # macro
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regRLC_RLCS_EXCEPTION_REG_4 = 0x4e65 # macro
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regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX = 1 # macro
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regRLC_RLCS_CGCG_REQUEST = 0x4e66 # macro
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regRLC_RLCS_CGCG_REQUEST_BASE_IDX = 1 # macro
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regRLC_RLCS_CGCG_STATUS = 0x4e67 # macro
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regRLC_RLCS_CGCG_STATUS_BASE_IDX = 1 # macro
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regRLC_RLCS_SOC_DS_CNTL = 0x4e68 # macro
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regRLC_RLCS_SOC_DS_CNTL_BASE_IDX = 1 # macro
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regRLC_RLCS_GFX_DS_CNTL = 0x4e69 # macro
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regRLC_RLCS_GFX_DS_CNTL_BASE_IDX = 1 # macro
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regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL = 0x4e6a # macro
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regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX = 1 # macro
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regRLC_GPM_STAT = 0x4e6b # macro
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regRLC_GPM_STAT_BASE_IDX = 1 # macro
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regRLC_RLCS_GPM_STAT = 0x4e6b # macro
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regRLC_RLCS_GPM_STAT_BASE_IDX = 1 # macro
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regRLC_RLCS_ABORTED_PD_SEQUENCE = 0x4e6c # macro
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regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX = 1 # macro
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regRLC_RLCS_DIDT_FORCE_STALL = 0x4e6d # macro
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regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX = 1 # macro
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regRLC_RLCS_IOV_CMD_STATUS = 0x4e6e # macro
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regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX = 1 # macro
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regRLC_RLCS_IOV_CNTX_LOC_SIZE = 0x4e6f # macro
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regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX = 1 # macro
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regRLC_RLCS_IOV_SCH_BLOCK = 0x4e70 # macro
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regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX = 1 # macro
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regRLC_RLCS_IOV_VM_BUSY_STATUS = 0x4e71 # macro
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regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro
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regRLC_RLCS_GPM_STAT_2 = 0x4e72 # macro
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regRLC_RLCS_GPM_STAT_2_BASE_IDX = 1 # macro
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regRLC_RLCS_GRBM_SOFT_RESET = 0x4e73 # macro
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regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX = 1 # macro
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regRLC_RLCS_PG_CHANGE_STATUS = 0x4e74 # macro
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regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX = 1 # macro
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regRLC_RLCS_PG_CHANGE_READ = 0x4e75 # macro
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regRLC_RLCS_PG_CHANGE_READ_BASE_IDX = 1 # macro
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regRLC_RLCS_IH_SEMAPHORE = 0x4e76 # macro
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regRLC_RLCS_IH_SEMAPHORE_BASE_IDX = 1 # macro
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regRLC_RLCS_IH_COOKIE_SEMAPHORE = 0x4e77 # macro
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regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX = 1 # macro
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regRLC_RLCS_WGP_STATUS = 0x4e78 # macro
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regRLC_RLCS_WGP_STATUS_BASE_IDX = 1 # macro
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regRLC_RLCS_WGP_READ = 0x4e79 # macro
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regRLC_RLCS_WGP_READ_BASE_IDX = 1 # macro
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regRLC_RLCS_CP_INT_CTRL_1 = 0x4e7a # macro
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regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX = 1 # macro
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regRLC_RLCS_CP_INT_CTRL_2 = 0x4e7b # macro
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regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX = 1 # macro
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regRLC_RLCS_CP_INT_INFO_1 = 0x4e7c # macro
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regRLC_RLCS_CP_INT_INFO_1_BASE_IDX = 1 # macro
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regRLC_RLCS_CP_INT_INFO_2 = 0x4e7d # macro
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regRLC_RLCS_CP_INT_INFO_2_BASE_IDX = 1 # macro
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regRLC_RLCS_SPM_INT_CTRL = 0x4e7e # macro
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regRLC_RLCS_SPM_INT_CTRL_BASE_IDX = 1 # macro
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regRLC_RLCS_SPM_INT_INFO_1 = 0x4e7f # macro
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regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX = 1 # macro
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regRLC_RLCS_SPM_INT_INFO_2 = 0x4e80 # macro
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regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX = 1 # macro
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regRLC_RLCS_DSM_TRIG = 0x4e81 # macro
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regRLC_RLCS_DSM_TRIG_BASE_IDX = 1 # macro
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regRLC_RLCS_BOOTLOAD_STATUS = 0x4e82 # macro
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regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX = 1 # macro
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regRLC_RLCS_POWER_BRAKE_CNTL = 0x4e83 # macro
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regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX = 1 # macro
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regRLC_RLCS_POWER_BRAKE_CNTL_TH1 = 0x4e84 # macro
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regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX = 1 # macro
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regRLC_RLCS_GRBM_IDLE_BUSY_STAT = 0x4e85 # macro
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regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX = 1 # macro
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regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL = 0x4e86 # macro
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regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX = 1 # macro
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regRLC_RLCS_CMP_IDLE_CNTL = 0x4e87 # macro
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regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_0 = 0x4e88 # macro
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regRLC_RLCS_GENERAL_0_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_1 = 0x4e89 # macro
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regRLC_RLCS_GENERAL_1_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_2 = 0x4e8a # macro
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regRLC_RLCS_GENERAL_2_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_3 = 0x4e8b # macro
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regRLC_RLCS_GENERAL_3_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_4 = 0x4e8c # macro
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regRLC_RLCS_GENERAL_4_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_5 = 0x4e8d # macro
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regRLC_RLCS_GENERAL_5_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_6 = 0x4e8e # macro
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regRLC_RLCS_GENERAL_6_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_7 = 0x4e8f # macro
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regRLC_RLCS_GENERAL_7_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_8 = 0x4e90 # macro
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regRLC_RLCS_GENERAL_8_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_9 = 0x4e91 # macro
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regRLC_RLCS_GENERAL_9_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_10 = 0x4e92 # macro
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regRLC_RLCS_GENERAL_10_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_11 = 0x4e93 # macro
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regRLC_RLCS_GENERAL_11_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_12 = 0x4e94 # macro
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regRLC_RLCS_GENERAL_12_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_13 = 0x4e95 # macro
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regRLC_RLCS_GENERAL_13_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_14 = 0x4e96 # macro
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regRLC_RLCS_GENERAL_14_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_15 = 0x4e97 # macro
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regRLC_RLCS_GENERAL_15_BASE_IDX = 1 # macro
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regRLC_RLCS_GENERAL_16 = 0x4e98 # macro
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regRLC_RLCS_GENERAL_16_BASE_IDX = 1 # macro
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regRLC_RLCS_AUXILIARY_REG_1 = 0x4ec5 # macro
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regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX = 1 # macro
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regRLC_RLCS_AUXILIARY_REG_2 = 0x4ec6 # macro
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regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX = 1 # macro
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regRLC_RLCS_AUXILIARY_REG_3 = 0x4ec7 # macro
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regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX = 1 # macro
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regRLC_RLCS_AUXILIARY_REG_4 = 0x4ec8 # macro
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regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX = 1 # macro
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regRLC_RLCS_SPM_SQTT_MODE = 0x4ec9 # macro
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regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX = 1 # macro
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regRLC_RLCS_CP_DMA_SRCID_OVER = 0x4eca # macro
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regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX = 1 # macro
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regRLC_RLCS_BOOTLOAD_ID_STATUS1 = 0x4ecb # macro
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regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX = 1 # macro
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regRLC_RLCS_BOOTLOAD_ID_STATUS2 = 0x4ecc # macro
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regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_VIDCHG_CNTL = 0x4ecd # macro
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regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX = 1 # macro
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regRLC_RLCS_EDC_INT_CNTL = 0x4ece # macro
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regRLC_RLCS_EDC_INT_CNTL_BASE_IDX = 1 # macro
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regRLC_RLCS_KMD_LOG_CNTL1 = 0x4ecf # macro
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regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX = 1 # macro
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regRLC_RLCS_KMD_LOG_CNTL2 = 0x4ed0 # macro
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regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX = 1 # macro
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regRLC_RLCS_GPM_LEGACY_INT_STAT = 0x4ed1 # macro
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regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro
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regRLC_RLCS_GPM_LEGACY_INT_DISABLE = 0x4ed2 # macro
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regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro
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regRLC_RLCS_SRM_SRCID_CNTL = 0x4ed3 # macro
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regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX = 1 # macro
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regRLC_RLCS_GCR_DATA_0 = 0x4ed4 # macro
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regRLC_RLCS_GCR_DATA_0_BASE_IDX = 1 # macro
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regRLC_RLCS_GCR_DATA_1 = 0x4ed5 # macro
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regRLC_RLCS_GCR_DATA_1_BASE_IDX = 1 # macro
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regRLC_RLCS_GCR_DATA_2 = 0x4ed6 # macro
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regRLC_RLCS_GCR_DATA_2_BASE_IDX = 1 # macro
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regRLC_RLCS_GCR_DATA_3 = 0x4ed7 # macro
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regRLC_RLCS_GCR_DATA_3_BASE_IDX = 1 # macro
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regRLC_RLCS_GCR_STATUS = 0x4ed8 # macro
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regRLC_RLCS_GCR_STATUS_BASE_IDX = 1 # macro
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regRLC_RLCS_PERFMON_CLK_CNTL_UCODE = 0x4ed9 # macro
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regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX = 1 # macro
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regRLC_RLCS_UTCL2_CNTL = 0x4eda # macro
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regRLC_RLCS_UTCL2_CNTL_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RLC_MSG_DATA0 = 0x4edb # macro
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regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RLC_MSG_DATA1 = 0x4edc # macro
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regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RLC_MSG_DATA2 = 0x4edd # macro
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regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RLC_MSG_DATA3 = 0x4ede # macro
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regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RLC_MSG_DATA4 = 0x4edf # macro
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regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RLC_MSG_CONTROL = 0x4ee0 # macro
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regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RLC_MSG_CNTL = 0x4ee1 # macro
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regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX = 1 # macro
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regRLC_RLCS_RLC_IMU_MSG_DATA0 = 0x4ee2 # macro
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regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX = 1 # macro
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regRLC_RLCS_RLC_IMU_MSG_CONTROL = 0x4ee3 # macro
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regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX = 1 # macro
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regRLC_RLCS_RLC_IMU_MSG_CNTL = 0x4ee4 # macro
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regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0 = 0x4ee5 # macro
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regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1 = 0x4ee6 # macro
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regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RLC_MUTEX_CNTL = 0x4ee7 # macro
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regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RLC_STATUS = 0x4ee8 # macro
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regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX = 1 # macro
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regRLC_RLCS_RLC_IMU_STATUS = 0x4ee9 # macro
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regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RAM_DATA_1 = 0x4eea # macro
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regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RAM_ADDR_1_LSB = 0x4eeb # macro
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regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RAM_ADDR_1_MSB = 0x4eec # macro
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regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RAM_DATA_0 = 0x4eed # macro
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regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RAM_ADDR_0_LSB = 0x4eee # macro
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regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RAM_ADDR_0_MSB = 0x4eef # macro
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regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_RAM_CNTL = 0x4ef0 # macro
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regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX = 1 # macro
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regRLC_RLCS_IMU_GFX_DOORBELL_FENCE = 0x4ef1 # macro
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regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX = 1 # macro
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regRLC_RLCS_SDMA_INT_CNTL_1 = 0x4ef3 # macro
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regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX = 1 # macro
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regRLC_RLCS_SDMA_INT_CNTL_2 = 0x4ef4 # macro
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|
regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX = 1 # macro
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regRLC_RLCS_SDMA_INT_STAT = 0x4ef5 # macro
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regRLC_RLCS_SDMA_INT_STAT_BASE_IDX = 1 # macro
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|
regRLC_RLCS_SDMA_INT_INFO = 0x4ef6 # macro
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regRLC_RLCS_SDMA_INT_INFO_BASE_IDX = 1 # macro
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|
regRLC_RLCS_PMM_CGCG_CNTL = 0x4ef7 # macro
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|
regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX = 1 # macro
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|
regRLC_RLCS_GFX_MEM_POWER_CTRL_LO = 0x4ef8 # macro
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regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX = 1 # macro
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|
regRLC_RLCS_GFX_RM_CNTL = 0x4efa # macro
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|
regRLC_RLCS_GFX_RM_CNTL_BASE_IDX = 1 # macro
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|
regRLC_RLCS_DEC_END = 0x4fff # macro
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regRLC_RLCS_DEC_END_BASE_IDX = 1 # macro
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|
regRLC_SAFE_MODE = 0x0980 # macro
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|
regRLC_SAFE_MODE_BASE_IDX = 1 # macro
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|
regRLC_SPM_SAMPLE_CNT = 0x0981 # macro
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|
regRLC_SPM_SAMPLE_CNT_BASE_IDX = 1 # macro
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|
regRLC_SPM_MC_CNTL = 0x0982 # macro
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|
regRLC_SPM_MC_CNTL_BASE_IDX = 1 # macro
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|
regRLC_SPM_INT_CNTL = 0x0983 # macro
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|
regRLC_SPM_INT_CNTL_BASE_IDX = 1 # macro
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|
regRLC_SPM_INT_STATUS = 0x0984 # macro
|
|
regRLC_SPM_INT_STATUS_BASE_IDX = 1 # macro
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|
regRLC_SPM_INT_INFO_1 = 0x0985 # macro
|
|
regRLC_SPM_INT_INFO_1_BASE_IDX = 1 # macro
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|
regRLC_SPM_INT_INFO_2 = 0x0986 # macro
|
|
regRLC_SPM_INT_INFO_2_BASE_IDX = 1 # macro
|
|
regRLC_CSIB_ADDR_LO = 0x0987 # macro
|
|
regRLC_CSIB_ADDR_LO_BASE_IDX = 1 # macro
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|
regRLC_CSIB_ADDR_HI = 0x0988 # macro
|
|
regRLC_CSIB_ADDR_HI_BASE_IDX = 1 # macro
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|
regRLC_CSIB_LENGTH = 0x0989 # macro
|
|
regRLC_CSIB_LENGTH_BASE_IDX = 1 # macro
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|
regRLC_CP_SCHEDULERS = 0x098a # macro
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|
regRLC_CP_SCHEDULERS_BASE_IDX = 1 # macro
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|
regRLC_CP_EOF_INT = 0x098b # macro
|
|
regRLC_CP_EOF_INT_BASE_IDX = 1 # macro
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|
regRLC_CP_EOF_INT_CNT = 0x098c # macro
|
|
regRLC_CP_EOF_INT_CNT_BASE_IDX = 1 # macro
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|
regRLC_SPARE_INT_0 = 0x098d # macro
|
|
regRLC_SPARE_INT_0_BASE_IDX = 1 # macro
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|
regRLC_SPARE_INT_1 = 0x098e # macro
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|
regRLC_SPARE_INT_1_BASE_IDX = 1 # macro
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|
regRLC_SPARE_INT_2 = 0x098f # macro
|
|
regRLC_SPARE_INT_2_BASE_IDX = 1 # macro
|
|
regRLC_PACE_SPARE_INT = 0x0990 # macro
|
|
regRLC_PACE_SPARE_INT_BASE_IDX = 1 # macro
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|
regRLC_PACE_SPARE_INT_1 = 0x0991 # macro
|
|
regRLC_PACE_SPARE_INT_1_BASE_IDX = 1 # macro
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|
regRLC_RLCV_SPARE_INT_1 = 0x0992 # macro
|
|
regRLC_RLCV_SPARE_INT_1_BASE_IDX = 1 # macro
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|
regCGTS_TCC_DISABLE = 0x5006 # macro
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|
regCGTS_TCC_DISABLE_BASE_IDX = 1 # macro
|
|
regCGTT_GS_NGG_CLK_CTRL = 0x5087 # macro
|
|
regCGTT_GS_NGG_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regCGTT_PA_CLK_CTRL = 0x5088 # macro
|
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regCGTT_PA_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regCGTT_SC_CLK_CTRL0 = 0x5089 # macro
|
|
regCGTT_SC_CLK_CTRL0_BASE_IDX = 1 # macro
|
|
regCGTT_SC_CLK_CTRL1 = 0x508a # macro
|
|
regCGTT_SC_CLK_CTRL1_BASE_IDX = 1 # macro
|
|
regCGTT_SC_CLK_CTRL2 = 0x508b # macro
|
|
regCGTT_SC_CLK_CTRL2_BASE_IDX = 1 # macro
|
|
regCGTT_SQG_CLK_CTRL = 0x508d # macro
|
|
regCGTT_SQG_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regSQ_ALU_CLK_CTRL = 0x508e # macro
|
|
regSQ_ALU_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regSQ_TEX_CLK_CTRL = 0x508f # macro
|
|
regSQ_TEX_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regSQ_LDS_CLK_CTRL = 0x5090 # macro
|
|
regSQ_LDS_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regICG_SP_CLK_CTRL = 0x5093 # macro
|
|
regICG_SP_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regTA_CGTT_CTRL = 0x509d # macro
|
|
regTA_CGTT_CTRL_BASE_IDX = 1 # macro
|
|
regDB_CGTT_CLK_CTRL_0 = 0x50a4 # macro
|
|
regDB_CGTT_CLK_CTRL_0_BASE_IDX = 1 # macro
|
|
regCB_CGTT_SCLK_CTRL = 0x50a8 # macro
|
|
regCB_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro
|
|
regCGTT_CP_CLK_CTRL = 0x50b0 # macro
|
|
regCGTT_CP_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regCGTT_CPF_CLK_CTRL = 0x50b1 # macro
|
|
regCGTT_CPF_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regCGTT_CPC_CLK_CTRL = 0x50b2 # macro
|
|
regCGTT_CPC_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regCGTT_RLC_CLK_CTRL = 0x50b5 # macro
|
|
regCGTT_RLC_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regCGTT_SC_CLK_CTRL3 = 0x50bc # macro
|
|
regCGTT_SC_CLK_CTRL3_BASE_IDX = 1 # macro
|
|
regCGTT_SC_CLK_CTRL4 = 0x50bd # macro
|
|
regCGTT_SC_CLK_CTRL4_BASE_IDX = 1 # macro
|
|
regGCEA_ICG_CTRL = 0x50c4 # macro
|
|
regGCEA_ICG_CTRL_BASE_IDX = 1 # macro
|
|
regGL1I_GL1R_MGCG_OVERRIDE = 0x50e4 # macro
|
|
regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX = 1 # macro
|
|
regGL1H_ICG_CTRL = 0x50e8 # macro
|
|
regGL1H_ICG_CTRL_BASE_IDX = 1 # macro
|
|
regCHI_CHR_MGCG_OVERRIDE = 0x50e9 # macro
|
|
regCHI_CHR_MGCG_OVERRIDE_BASE_IDX = 1 # macro
|
|
regICG_GL1C_CLK_CTRL = 0x50ec # macro
|
|
regICG_GL1C_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regICG_GL1A_CTRL = 0x50f0 # macro
|
|
regICG_GL1A_CTRL_BASE_IDX = 1 # macro
|
|
regICG_CHA_CTRL = 0x50f1 # macro
|
|
regICG_CHA_CTRL_BASE_IDX = 1 # macro
|
|
regGUS_ICG_CTRL = 0x50f4 # macro
|
|
regGUS_ICG_CTRL_BASE_IDX = 1 # macro
|
|
regCGTT_PH_CLK_CTRL0 = 0x50f8 # macro
|
|
regCGTT_PH_CLK_CTRL0_BASE_IDX = 1 # macro
|
|
regCGTT_PH_CLK_CTRL1 = 0x50f9 # macro
|
|
regCGTT_PH_CLK_CTRL1_BASE_IDX = 1 # macro
|
|
regCGTT_PH_CLK_CTRL2 = 0x50fa # macro
|
|
regCGTT_PH_CLK_CTRL2_BASE_IDX = 1 # macro
|
|
regCGTT_PH_CLK_CTRL3 = 0x50fb # macro
|
|
regCGTT_PH_CLK_CTRL3_BASE_IDX = 1 # macro
|
|
regGFX_ICG_GL2C_CTRL = 0x50fc # macro
|
|
regGFX_ICG_GL2C_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_ICG_GL2C_CTRL1 = 0x50fd # macro
|
|
regGFX_ICG_GL2C_CTRL1_BASE_IDX = 1 # macro
|
|
regICG_LDS_CLK_CTRL = 0x5114 # macro
|
|
regICG_LDS_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regICG_CHC_CLK_CTRL = 0x5140 # macro
|
|
regICG_CHC_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regICG_CHCG_CLK_CTRL = 0x5144 # macro
|
|
regICG_CHCG_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_PIPE_PRIORITY = 0x587f # macro
|
|
regGFX_PIPE_PRIORITY_BASE_IDX = 1 # macro
|
|
regGRBM_GFX_INDEX_SR_SELECT = 0x5a00 # macro
|
|
regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX = 1 # macro
|
|
regGRBM_GFX_INDEX_SR_DATA = 0x5a01 # macro
|
|
regGRBM_GFX_INDEX_SR_DATA_BASE_IDX = 1 # macro
|
|
regGRBM_GFX_CNTL_SR_SELECT = 0x5a02 # macro
|
|
regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX = 1 # macro
|
|
regGRBM_GFX_CNTL_SR_DATA = 0x5a03 # macro
|
|
regGRBM_GFX_CNTL_SR_DATA_BASE_IDX = 1 # macro
|
|
regGC_IH_COOKIE_0_PTR = 0x5a07 # macro
|
|
regGC_IH_COOKIE_0_PTR_BASE_IDX = 1 # macro
|
|
regGRBM_SE_REMAP_CNTL = 0x5a08 # macro
|
|
regGRBM_SE_REMAP_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_VF_ENABLE = 0x5b00 # macro
|
|
regRLC_GPU_IOV_VF_ENABLE_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_CFG_REG6 = 0x5b06 # macro
|
|
regRLC_GPU_IOV_CFG_REG6_BASE_IDX = 1 # macro
|
|
regRLC_SDMA0_STATUS = 0x5b18 # macro
|
|
regRLC_SDMA0_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_SDMA1_STATUS = 0x5b19 # macro
|
|
regRLC_SDMA1_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_SDMA2_STATUS = 0x5b1a # macro
|
|
regRLC_SDMA2_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_SDMA3_STATUS = 0x5b1b # macro
|
|
regRLC_SDMA3_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_SDMA0_BUSY_STATUS = 0x5b1c # macro
|
|
regRLC_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_SDMA1_BUSY_STATUS = 0x5b1d # macro
|
|
regRLC_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_SDMA2_BUSY_STATUS = 0x5b1e # macro
|
|
regRLC_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_SDMA3_BUSY_STATUS = 0x5b1f # macro
|
|
regRLC_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_CFG_REG8 = 0x5b20 # macro
|
|
regRLC_GPU_IOV_CFG_REG8_BASE_IDX = 1 # macro
|
|
regRLC_RLCV_TIMER_INT_0 = 0x5b25 # macro
|
|
regRLC_RLCV_TIMER_INT_0_BASE_IDX = 1 # macro
|
|
regRLC_RLCV_TIMER_INT_1 = 0x5b26 # macro
|
|
regRLC_RLCV_TIMER_INT_1_BASE_IDX = 1 # macro
|
|
regRLC_RLCV_TIMER_CTRL = 0x5b27 # macro
|
|
regRLC_RLCV_TIMER_CTRL_BASE_IDX = 1 # macro
|
|
regRLC_RLCV_TIMER_STAT = 0x5b28 # macro
|
|
regRLC_RLCV_TIMER_STAT_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_VF_DOORBELL_STATUS = 0x5b2a # macro
|
|
regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET = 0x5b2b # macro
|
|
regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR = 0x5b2c # macro
|
|
regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_VF_MASK = 0x5b2d # macro
|
|
regRLC_GPU_IOV_VF_MASK_BASE_IDX = 1 # macro
|
|
regRLC_HYP_SEMAPHORE_0 = 0x5b2e # macro
|
|
regRLC_HYP_SEMAPHORE_0_BASE_IDX = 1 # macro
|
|
regRLC_HYP_SEMAPHORE_1 = 0x5b2f # macro
|
|
regRLC_HYP_SEMAPHORE_1_BASE_IDX = 1 # macro
|
|
regRLC_BUSY_CLK_CNTL = 0x5b30 # macro
|
|
regRLC_BUSY_CLK_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_CLK_CNTL = 0x5b31 # macro
|
|
regRLC_CLK_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_PACE_TIMER_STAT = 0x5b33 # macro
|
|
regRLC_PACE_TIMER_STAT_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SCH_BLOCK = 0x5b34 # macro
|
|
regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_CFG_REG1 = 0x5b35 # macro
|
|
regRLC_GPU_IOV_CFG_REG1_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_CFG_REG2 = 0x5b36 # macro
|
|
regRLC_GPU_IOV_CFG_REG2_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_VM_BUSY_STATUS = 0x5b37 # macro
|
|
regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SCH_0 = 0x5b38 # macro
|
|
regRLC_GPU_IOV_SCH_0_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SCH_3 = 0x5b3a # macro
|
|
regRLC_GPU_IOV_SCH_3_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SCH_1 = 0x5b3b # macro
|
|
regRLC_GPU_IOV_SCH_1_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SCH_2 = 0x5b3c # macro
|
|
regRLC_GPU_IOV_SCH_2_BASE_IDX = 1 # macro
|
|
regRLC_PACE_INT_FORCE = 0x5b3d # macro
|
|
regRLC_PACE_INT_FORCE_BASE_IDX = 1 # macro
|
|
regRLC_PACE_INT_CLEAR = 0x5b3e # macro
|
|
regRLC_PACE_INT_CLEAR_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_INT_STAT = 0x5b3f # macro
|
|
regRLC_GPU_IOV_INT_STAT_BASE_IDX = 1 # macro
|
|
regRLC_IH_COOKIE = 0x5b41 # macro
|
|
regRLC_IH_COOKIE_BASE_IDX = 1 # macro
|
|
regRLC_IH_COOKIE_CNTL = 0x5b42 # macro
|
|
regRLC_IH_COOKIE_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_HYP_RLCG_UCODE_CHKSUM = 0x5b43 # macro
|
|
regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX = 1 # macro
|
|
regRLC_HYP_RLCP_UCODE_CHKSUM = 0x5b44 # macro
|
|
regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX = 1 # macro
|
|
regRLC_HYP_RLCV_UCODE_CHKSUM = 0x5b45 # macro
|
|
regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_F32_CNTL = 0x5b46 # macro
|
|
regRLC_GPU_IOV_F32_CNTL_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_F32_RESET = 0x5b47 # macro
|
|
regRLC_GPU_IOV_F32_RESET_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_UCODE_ADDR = 0x5b48 # macro
|
|
regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_UCODE_DATA = 0x5b49 # macro
|
|
regRLC_GPU_IOV_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SMU_RESPONSE = 0x5b4a # macro
|
|
regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_F32_INVALIDATE_CACHE = 0x5b4b # macro
|
|
regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_RLC_RESPONSE = 0x5b4d # macro
|
|
regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_INT_DISABLE = 0x5b4e # macro
|
|
regRLC_GPU_IOV_INT_DISABLE_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_INT_FORCE = 0x5b4f # macro
|
|
regRLC_GPU_IOV_INT_FORCE_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SCRATCH_ADDR = 0x5b50 # macro
|
|
regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SCRATCH_DATA = 0x5b51 # macro
|
|
regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX = 1 # macro
|
|
regRLC_HYP_SEMAPHORE_2 = 0x5b52 # macro
|
|
regRLC_HYP_SEMAPHORE_2_BASE_IDX = 1 # macro
|
|
regRLC_HYP_SEMAPHORE_3 = 0x5b53 # macro
|
|
regRLC_HYP_SEMAPHORE_3_BASE_IDX = 1 # macro
|
|
regRLC_GPM_UCODE_ADDR = 0x5b60 # macro
|
|
regRLC_GPM_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_GPM_UCODE_DATA = 0x5b61 # macro
|
|
regRLC_GPM_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regRLC_GPM_IRAM_ADDR = 0x5b62 # macro
|
|
regRLC_GPM_IRAM_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_GPM_IRAM_DATA = 0x5b63 # macro
|
|
regRLC_GPM_IRAM_DATA_BASE_IDX = 1 # macro
|
|
regRLC_RLCP_IRAM_ADDR = 0x5b64 # macro
|
|
regRLC_RLCP_IRAM_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_RLCP_IRAM_DATA = 0x5b65 # macro
|
|
regRLC_RLCP_IRAM_DATA_BASE_IDX = 1 # macro
|
|
regRLC_RLCV_IRAM_ADDR = 0x5b66 # macro
|
|
regRLC_RLCV_IRAM_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_RLCV_IRAM_DATA = 0x5b67 # macro
|
|
regRLC_RLCV_IRAM_DATA_BASE_IDX = 1 # macro
|
|
regRLC_LX6_DRAM_ADDR = 0x5b68 # macro
|
|
regRLC_LX6_DRAM_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_LX6_DRAM_DATA = 0x5b69 # macro
|
|
regRLC_LX6_DRAM_DATA_BASE_IDX = 1 # macro
|
|
regRLC_LX6_IRAM_ADDR = 0x5b6a # macro
|
|
regRLC_LX6_IRAM_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_LX6_IRAM_DATA = 0x5b6b # macro
|
|
regRLC_LX6_IRAM_DATA_BASE_IDX = 1 # macro
|
|
regRLC_PACE_UCODE_ADDR = 0x5b6c # macro
|
|
regRLC_PACE_UCODE_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_PACE_UCODE_DATA = 0x5b6d # macro
|
|
regRLC_PACE_UCODE_DATA_BASE_IDX = 1 # macro
|
|
regRLC_GPM_SCRATCH_ADDR = 0x5b6e # macro
|
|
regRLC_GPM_SCRATCH_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_GPM_SCRATCH_DATA = 0x5b6f # macro
|
|
regRLC_GPM_SCRATCH_DATA_BASE_IDX = 1 # macro
|
|
regRLC_SRM_DRAM_ADDR = 0x5b71 # macro
|
|
regRLC_SRM_DRAM_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_SRM_DRAM_DATA = 0x5b72 # macro
|
|
regRLC_SRM_DRAM_DATA_BASE_IDX = 1 # macro
|
|
regRLC_SRM_ARAM_ADDR = 0x5b73 # macro
|
|
regRLC_SRM_ARAM_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_SRM_ARAM_DATA = 0x5b74 # macro
|
|
regRLC_SRM_ARAM_DATA_BASE_IDX = 1 # macro
|
|
regRLC_PACE_SCRATCH_ADDR = 0x5b77 # macro
|
|
regRLC_PACE_SCRATCH_ADDR_BASE_IDX = 1 # macro
|
|
regRLC_PACE_SCRATCH_DATA = 0x5b78 # macro
|
|
regRLC_PACE_SCRATCH_DATA_BASE_IDX = 1 # macro
|
|
regRLC_GTS_OFFSET_LSB = 0x5b79 # macro
|
|
regRLC_GTS_OFFSET_LSB_BASE_IDX = 1 # macro
|
|
regRLC_GTS_OFFSET_MSB = 0x5b7a # macro
|
|
regRLC_GTS_OFFSET_MSB_BASE_IDX = 1 # macro
|
|
regGL2_PIPE_STEER_0 = 0x5b80 # macro
|
|
regGL2_PIPE_STEER_0_BASE_IDX = 1 # macro
|
|
regGL2_PIPE_STEER_1 = 0x5b81 # macro
|
|
regGL2_PIPE_STEER_1_BASE_IDX = 1 # macro
|
|
regGL2_PIPE_STEER_2 = 0x5b82 # macro
|
|
regGL2_PIPE_STEER_2_BASE_IDX = 1 # macro
|
|
regGL2_PIPE_STEER_3 = 0x5b83 # macro
|
|
regGL2_PIPE_STEER_3_BASE_IDX = 1 # macro
|
|
regGL1_PIPE_STEER = 0x5b84 # macro
|
|
regGL1_PIPE_STEER_BASE_IDX = 1 # macro
|
|
regCH_PIPE_STEER = 0x5b88 # macro
|
|
regCH_PIPE_STEER_BASE_IDX = 1 # macro
|
|
regGC_USER_SHADER_ARRAY_CONFIG = 0x5b90 # macro
|
|
regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX = 1 # macro
|
|
regGC_USER_PRIM_CONFIG = 0x5b91 # macro
|
|
regGC_USER_PRIM_CONFIG_BASE_IDX = 1 # macro
|
|
regGC_USER_SA_UNIT_DISABLE = 0x5b92 # macro
|
|
regGC_USER_SA_UNIT_DISABLE_BASE_IDX = 1 # macro
|
|
regGC_USER_RB_REDUNDANCY = 0x5b93 # macro
|
|
regGC_USER_RB_REDUNDANCY_BASE_IDX = 1 # macro
|
|
regGC_USER_RB_BACKEND_DISABLE = 0x5b94 # macro
|
|
regGC_USER_RB_BACKEND_DISABLE_BASE_IDX = 1 # macro
|
|
regGC_USER_RMI_REDUNDANCY = 0x5b95 # macro
|
|
regGC_USER_RMI_REDUNDANCY_BASE_IDX = 1 # macro
|
|
regCGTS_USER_TCC_DISABLE = 0x5b96 # macro
|
|
regCGTS_USER_TCC_DISABLE_BASE_IDX = 1 # macro
|
|
regGC_USER_SHADER_RATE_CONFIG = 0x5b97 # macro
|
|
regGC_USER_SHADER_RATE_CONFIG_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA0_STATUS = 0x5bc0 # macro
|
|
regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA1_STATUS = 0x5bc1 # macro
|
|
regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA2_STATUS = 0x5bc2 # macro
|
|
regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA3_STATUS = 0x5bc3 # macro
|
|
regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA4_STATUS = 0x5bc4 # macro
|
|
regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA5_STATUS = 0x5bc5 # macro
|
|
regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA6_STATUS = 0x5bc6 # macro
|
|
regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA7_STATUS = 0x5bc7 # macro
|
|
regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA0_BUSY_STATUS = 0x5bc8 # macro
|
|
regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA1_BUSY_STATUS = 0x5bc9 # macro
|
|
regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA2_BUSY_STATUS = 0x5bca # macro
|
|
regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA3_BUSY_STATUS = 0x5bcb # macro
|
|
regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA4_BUSY_STATUS = 0x5bcc # macro
|
|
regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA5_BUSY_STATUS = 0x5bcd # macro
|
|
regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA6_BUSY_STATUS = 0x5bce # macro
|
|
regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GPU_IOV_SDMA7_BUSY_STATUS = 0x5bcf # macro
|
|
regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX = 1 # macro
|
|
regCP_MES_DM_INDEX_ADDR = 0x5c00 # macro
|
|
regCP_MES_DM_INDEX_ADDR_BASE_IDX = 1 # macro
|
|
regCP_MES_DM_INDEX_DATA = 0x5c01 # macro
|
|
regCP_MES_DM_INDEX_DATA_BASE_IDX = 1 # macro
|
|
regCP_MEC_DM_INDEX_ADDR = 0x5c02 # macro
|
|
regCP_MEC_DM_INDEX_ADDR_BASE_IDX = 1 # macro
|
|
regCP_MEC_DM_INDEX_DATA = 0x5c03 # macro
|
|
regCP_MEC_DM_INDEX_DATA_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DM_INDEX_ADDR = 0x5c04 # macro
|
|
regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX = 1 # macro
|
|
regCP_GFX_RS64_DM_INDEX_DATA = 0x5c05 # macro
|
|
regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX = 1 # macro
|
|
regCPG_PSP_DEBUG = 0x5c10 # macro
|
|
regCPG_PSP_DEBUG_BASE_IDX = 1 # macro
|
|
regCPC_PSP_DEBUG = 0x5c11 # macro
|
|
regCPC_PSP_DEBUG_BASE_IDX = 1 # macro
|
|
regGRBM_SEC_CNTL = 0x5e0d # macro
|
|
regGRBM_SEC_CNTL_BASE_IDX = 1 # macro
|
|
regGRBM_CAM_INDEX = 0x5e10 # macro
|
|
regGRBM_CAM_INDEX_BASE_IDX = 1 # macro
|
|
regGRBM_HYP_CAM_INDEX = 0x5e10 # macro
|
|
regGRBM_HYP_CAM_INDEX_BASE_IDX = 1 # macro
|
|
regGRBM_CAM_DATA = 0x5e11 # macro
|
|
regGRBM_CAM_DATA_BASE_IDX = 1 # macro
|
|
regGRBM_HYP_CAM_DATA = 0x5e11 # macro
|
|
regGRBM_HYP_CAM_DATA_BASE_IDX = 1 # macro
|
|
regGRBM_CAM_DATA_UPPER = 0x5e12 # macro
|
|
regGRBM_CAM_DATA_UPPER_BASE_IDX = 1 # macro
|
|
regGRBM_HYP_CAM_DATA_UPPER = 0x5e12 # macro
|
|
regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX = 1 # macro
|
|
regRLC_FWL_FIRST_VIOL_ADDR = 0x5f26 # macro
|
|
regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_0 = 0x4000 # macro
|
|
regGFX_IMU_C2PMSG_0_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_1 = 0x4001 # macro
|
|
regGFX_IMU_C2PMSG_1_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_2 = 0x4002 # macro
|
|
regGFX_IMU_C2PMSG_2_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_3 = 0x4003 # macro
|
|
regGFX_IMU_C2PMSG_3_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_4 = 0x4004 # macro
|
|
regGFX_IMU_C2PMSG_4_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_5 = 0x4005 # macro
|
|
regGFX_IMU_C2PMSG_5_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_6 = 0x4006 # macro
|
|
regGFX_IMU_C2PMSG_6_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_7 = 0x4007 # macro
|
|
regGFX_IMU_C2PMSG_7_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_8 = 0x4008 # macro
|
|
regGFX_IMU_C2PMSG_8_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_9 = 0x4009 # macro
|
|
regGFX_IMU_C2PMSG_9_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_10 = 0x400a # macro
|
|
regGFX_IMU_C2PMSG_10_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_11 = 0x400b # macro
|
|
regGFX_IMU_C2PMSG_11_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_12 = 0x400c # macro
|
|
regGFX_IMU_C2PMSG_12_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_13 = 0x400d # macro
|
|
regGFX_IMU_C2PMSG_13_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_14 = 0x400e # macro
|
|
regGFX_IMU_C2PMSG_14_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_15 = 0x400f # macro
|
|
regGFX_IMU_C2PMSG_15_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_16 = 0x4010 # macro
|
|
regGFX_IMU_C2PMSG_16_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_17 = 0x4011 # macro
|
|
regGFX_IMU_C2PMSG_17_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_18 = 0x4012 # macro
|
|
regGFX_IMU_C2PMSG_18_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_19 = 0x4013 # macro
|
|
regGFX_IMU_C2PMSG_19_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_20 = 0x4014 # macro
|
|
regGFX_IMU_C2PMSG_20_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_21 = 0x4015 # macro
|
|
regGFX_IMU_C2PMSG_21_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_22 = 0x4016 # macro
|
|
regGFX_IMU_C2PMSG_22_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_23 = 0x4017 # macro
|
|
regGFX_IMU_C2PMSG_23_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_24 = 0x4018 # macro
|
|
regGFX_IMU_C2PMSG_24_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_25 = 0x4019 # macro
|
|
regGFX_IMU_C2PMSG_25_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_26 = 0x401a # macro
|
|
regGFX_IMU_C2PMSG_26_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_27 = 0x401b # macro
|
|
regGFX_IMU_C2PMSG_27_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_28 = 0x401c # macro
|
|
regGFX_IMU_C2PMSG_28_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_29 = 0x401d # macro
|
|
regGFX_IMU_C2PMSG_29_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_30 = 0x401e # macro
|
|
regGFX_IMU_C2PMSG_30_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_31 = 0x401f # macro
|
|
regGFX_IMU_C2PMSG_31_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_32 = 0x4020 # macro
|
|
regGFX_IMU_C2PMSG_32_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_33 = 0x4021 # macro
|
|
regGFX_IMU_C2PMSG_33_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_34 = 0x4022 # macro
|
|
regGFX_IMU_C2PMSG_34_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_35 = 0x4023 # macro
|
|
regGFX_IMU_C2PMSG_35_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_36 = 0x4024 # macro
|
|
regGFX_IMU_C2PMSG_36_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_37 = 0x4025 # macro
|
|
regGFX_IMU_C2PMSG_37_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_38 = 0x4026 # macro
|
|
regGFX_IMU_C2PMSG_38_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_39 = 0x4027 # macro
|
|
regGFX_IMU_C2PMSG_39_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_40 = 0x4028 # macro
|
|
regGFX_IMU_C2PMSG_40_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_41 = 0x4029 # macro
|
|
regGFX_IMU_C2PMSG_41_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_42 = 0x402a # macro
|
|
regGFX_IMU_C2PMSG_42_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_43 = 0x402b # macro
|
|
regGFX_IMU_C2PMSG_43_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_44 = 0x402c # macro
|
|
regGFX_IMU_C2PMSG_44_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_45 = 0x402d # macro
|
|
regGFX_IMU_C2PMSG_45_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_46 = 0x402e # macro
|
|
regGFX_IMU_C2PMSG_46_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_47 = 0x402f # macro
|
|
regGFX_IMU_C2PMSG_47_BASE_IDX = 1 # macro
|
|
regGFX_IMU_MSG_FLAGS = 0x403f # macro
|
|
regGFX_IMU_MSG_FLAGS_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_ACCESS_CTRL0 = 0x4040 # macro
|
|
regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX = 1 # macro
|
|
regGFX_IMU_C2PMSG_ACCESS_CTRL1 = 0x4041 # macro
|
|
regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PWRMGT_IRQ_CTRL = 0x4042 # macro
|
|
regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_MP1_MUTEX = 0x4043 # macro
|
|
regGFX_IMU_MP1_MUTEX_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_DATA_4 = 0x4046 # macro
|
|
regGFX_IMU_RLC_DATA_4_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_DATA_3 = 0x4047 # macro
|
|
regGFX_IMU_RLC_DATA_3_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_DATA_2 = 0x4048 # macro
|
|
regGFX_IMU_RLC_DATA_2_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_DATA_1 = 0x4049 # macro
|
|
regGFX_IMU_RLC_DATA_1_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_DATA_0 = 0x404a # macro
|
|
regGFX_IMU_RLC_DATA_0_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_CMD = 0x404b # macro
|
|
regGFX_IMU_RLC_CMD_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_MUTEX = 0x404c # macro
|
|
regGFX_IMU_RLC_MUTEX_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_MSG_STATUS = 0x404f # macro
|
|
regGFX_IMU_RLC_MSG_STATUS_BASE_IDX = 1 # macro
|
|
regRLC_GFX_IMU_DATA_0 = 0x4052 # macro
|
|
regRLC_GFX_IMU_DATA_0_BASE_IDX = 1 # macro
|
|
regRLC_GFX_IMU_CMD = 0x4053 # macro
|
|
regRLC_GFX_IMU_CMD_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_STATUS = 0x4054 # macro
|
|
regGFX_IMU_RLC_STATUS_BASE_IDX = 1 # macro
|
|
regGFX_IMU_STATUS = 0x4055 # macro
|
|
regGFX_IMU_STATUS_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SOC_DATA = 0x4059 # macro
|
|
regGFX_IMU_SOC_DATA_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SOC_ADDR = 0x405a # macro
|
|
regGFX_IMU_SOC_ADDR_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SOC_REQ = 0x405b # macro
|
|
regGFX_IMU_SOC_REQ_BASE_IDX = 1 # macro
|
|
regGFX_IMU_VF_CTRL = 0x405c # macro
|
|
regGFX_IMU_VF_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TELEMETRY = 0x4060 # macro
|
|
regGFX_IMU_TELEMETRY_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TELEMETRY_DATA = 0x4061 # macro
|
|
regGFX_IMU_TELEMETRY_DATA_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TELEMETRY_TEMPERATURE = 0x4062 # macro
|
|
regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_0 = 0x4068 # macro
|
|
regGFX_IMU_SCRATCH_0_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_1 = 0x4069 # macro
|
|
regGFX_IMU_SCRATCH_1_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_2 = 0x406a # macro
|
|
regGFX_IMU_SCRATCH_2_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_3 = 0x406b # macro
|
|
regGFX_IMU_SCRATCH_3_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_4 = 0x406c # macro
|
|
regGFX_IMU_SCRATCH_4_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_5 = 0x406d # macro
|
|
regGFX_IMU_SCRATCH_5_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_6 = 0x406e # macro
|
|
regGFX_IMU_SCRATCH_6_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_7 = 0x406f # macro
|
|
regGFX_IMU_SCRATCH_7_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_8 = 0x4070 # macro
|
|
regGFX_IMU_SCRATCH_8_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_9 = 0x4071 # macro
|
|
regGFX_IMU_SCRATCH_9_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_10 = 0x4072 # macro
|
|
regGFX_IMU_SCRATCH_10_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_11 = 0x4073 # macro
|
|
regGFX_IMU_SCRATCH_11_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_12 = 0x4074 # macro
|
|
regGFX_IMU_SCRATCH_12_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_13 = 0x4075 # macro
|
|
regGFX_IMU_SCRATCH_13_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_14 = 0x4076 # macro
|
|
regGFX_IMU_SCRATCH_14_BASE_IDX = 1 # macro
|
|
regGFX_IMU_SCRATCH_15 = 0x4077 # macro
|
|
regGFX_IMU_SCRATCH_15_BASE_IDX = 1 # macro
|
|
regGFX_IMU_FW_GTS_LO = 0x4078 # macro
|
|
regGFX_IMU_FW_GTS_LO_BASE_IDX = 1 # macro
|
|
regGFX_IMU_FW_GTS_HI = 0x4079 # macro
|
|
regGFX_IMU_FW_GTS_HI_BASE_IDX = 1 # macro
|
|
regGFX_IMU_GTS_OFFSET_LO = 0x407a # macro
|
|
regGFX_IMU_GTS_OFFSET_LO_BASE_IDX = 1 # macro
|
|
regGFX_IMU_GTS_OFFSET_HI = 0x407b # macro
|
|
regGFX_IMU_GTS_OFFSET_HI_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_GTS_OFFSET_LO = 0x407c # macro
|
|
regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_GTS_OFFSET_HI = 0x407d # macro
|
|
regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX = 1 # macro
|
|
regGFX_IMU_CORE_INT_STATUS = 0x407f # macro
|
|
regGFX_IMU_CORE_INT_STATUS_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INT_MASK = 0x4080 # macro
|
|
regGFX_IMU_PIC_INT_MASK_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INT_LVL = 0x4081 # macro
|
|
regGFX_IMU_PIC_INT_LVL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INT_EDGE = 0x4082 # macro
|
|
regGFX_IMU_PIC_INT_EDGE_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INT_PRI_0 = 0x4083 # macro
|
|
regGFX_IMU_PIC_INT_PRI_0_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INT_PRI_1 = 0x4084 # macro
|
|
regGFX_IMU_PIC_INT_PRI_1_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INT_PRI_2 = 0x4085 # macro
|
|
regGFX_IMU_PIC_INT_PRI_2_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INT_PRI_3 = 0x4086 # macro
|
|
regGFX_IMU_PIC_INT_PRI_3_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INT_PRI_4 = 0x4087 # macro
|
|
regGFX_IMU_PIC_INT_PRI_4_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INT_PRI_5 = 0x4088 # macro
|
|
regGFX_IMU_PIC_INT_PRI_5_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INT_PRI_6 = 0x4089 # macro
|
|
regGFX_IMU_PIC_INT_PRI_6_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INT_PRI_7 = 0x408a # macro
|
|
regGFX_IMU_PIC_INT_PRI_7_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INT_STATUS = 0x408b # macro
|
|
regGFX_IMU_PIC_INT_STATUS_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INTR = 0x408c # macro
|
|
regGFX_IMU_PIC_INTR_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PIC_INTR_ID = 0x408d # macro
|
|
regGFX_IMU_PIC_INTR_ID_BASE_IDX = 1 # macro
|
|
regGFX_IMU_IH_CTRL_1 = 0x4090 # macro
|
|
regGFX_IMU_IH_CTRL_1_BASE_IDX = 1 # macro
|
|
regGFX_IMU_IH_CTRL_2 = 0x4091 # macro
|
|
regGFX_IMU_IH_CTRL_2_BASE_IDX = 1 # macro
|
|
regGFX_IMU_IH_CTRL_3 = 0x4092 # macro
|
|
regGFX_IMU_IH_CTRL_3_BASE_IDX = 1 # macro
|
|
regGFX_IMU_IH_STATUS = 0x4093 # macro
|
|
regGFX_IMU_IH_STATUS_BASE_IDX = 1 # macro
|
|
regGFX_IMU_FUSESTRAP = 0x4094 # macro
|
|
regGFX_IMU_SMUIO_VIDCHG_CTRL = 0x4098 # macro
|
|
regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_GFXCLK_BYPASS_CTRL = 0x409c # macro
|
|
regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_CLK_CTRL = 0x409d # macro
|
|
regGFX_IMU_CLK_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_DOORBELL_CONTROL = 0x409e # macro
|
|
regGFX_IMU_DOORBELL_CONTROL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_CG_CTRL = 0x40a0 # macro
|
|
regGFX_IMU_RLC_CG_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_THROTTLE_GFX = 0x40a1 # macro
|
|
regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_RESET_VECTOR = 0x40a2 # macro
|
|
regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_OVERRIDE = 0x40a3 # macro
|
|
regGFX_IMU_RLC_OVERRIDE_BASE_IDX = 1 # macro
|
|
regGFX_IMU_DPM_CONTROL = 0x40a8 # macro
|
|
regGFX_IMU_DPM_CONTROL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_DPM_ACC = 0x40a9 # macro
|
|
regGFX_IMU_DPM_ACC_BASE_IDX = 1 # macro
|
|
regGFX_IMU_DPM_REF_COUNTER = 0x40aa # macro
|
|
regGFX_IMU_DPM_REF_COUNTER_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_RAM_INDEX = 0x40ac # macro
|
|
regGFX_IMU_RLC_RAM_INDEX_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_RAM_ADDR_HIGH = 0x40ad # macro
|
|
regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_RAM_ADDR_LOW = 0x40ae # macro
|
|
regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_RAM_DATA = 0x40af # macro
|
|
regGFX_IMU_RLC_RAM_DATA_BASE_IDX = 1 # macro
|
|
regGFX_IMU_FENCE_CTRL = 0x40b0 # macro
|
|
regGFX_IMU_FENCE_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_FENCE_LOG_INIT = 0x40b1 # macro
|
|
regGFX_IMU_FENCE_LOG_INIT_BASE_IDX = 1 # macro
|
|
regGFX_IMU_FENCE_LOG_ADDR = 0x40b2 # macro
|
|
regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PROGRAM_CTR = 0x40b5 # macro
|
|
regGFX_IMU_PROGRAM_CTR_BASE_IDX = 1 # macro
|
|
regGFX_IMU_CORE_CTRL = 0x40b6 # macro
|
|
regGFX_IMU_CORE_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_CORE_STATUS = 0x40b7 # macro
|
|
regGFX_IMU_CORE_STATUS_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PWROKRAW = 0x40b8 # macro
|
|
regGFX_IMU_PWROKRAW_BASE_IDX = 1 # macro
|
|
regGFX_IMU_PWROK = 0x40b9 # macro
|
|
regGFX_IMU_PWROK_BASE_IDX = 1 # macro
|
|
regGFX_IMU_GAP_PWROK = 0x40ba # macro
|
|
regGFX_IMU_GAP_PWROK_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RESETn = 0x40bb # macro
|
|
regGFX_IMU_RESETn_BASE_IDX = 1 # macro
|
|
regGFX_IMU_GFX_RESET_CTRL = 0x40bc # macro
|
|
regGFX_IMU_GFX_RESET_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_AEB_OVERRIDE = 0x40bd # macro
|
|
regGFX_IMU_AEB_OVERRIDE_BASE_IDX = 1 # macro
|
|
regGFX_IMU_VDCI_RESET_CTRL = 0x40be # macro
|
|
regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_GFX_ISO_CTRL = 0x40bf # macro
|
|
regGFX_IMU_GFX_ISO_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER0_CTRL0 = 0x40c0 # macro
|
|
regGFX_IMU_TIMER0_CTRL0_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER0_CTRL1 = 0x40c1 # macro
|
|
regGFX_IMU_TIMER0_CTRL1_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER0_CMP_AUTOINC = 0x40c2 # macro
|
|
regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER0_CMP_INTEN = 0x40c3 # macro
|
|
regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER0_CMP0 = 0x40c4 # macro
|
|
regGFX_IMU_TIMER0_CMP0_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER0_CMP1 = 0x40c5 # macro
|
|
regGFX_IMU_TIMER0_CMP1_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER0_CMP3 = 0x40c7 # macro
|
|
regGFX_IMU_TIMER0_CMP3_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER0_VALUE = 0x40c8 # macro
|
|
regGFX_IMU_TIMER0_VALUE_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER1_CTRL0 = 0x40c9 # macro
|
|
regGFX_IMU_TIMER1_CTRL0_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER1_CTRL1 = 0x40ca # macro
|
|
regGFX_IMU_TIMER1_CTRL1_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER1_CMP_AUTOINC = 0x40cb # macro
|
|
regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER1_CMP_INTEN = 0x40cc # macro
|
|
regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER1_CMP0 = 0x40cd # macro
|
|
regGFX_IMU_TIMER1_CMP0_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER1_CMP1 = 0x40ce # macro
|
|
regGFX_IMU_TIMER1_CMP1_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER1_CMP3 = 0x40d0 # macro
|
|
regGFX_IMU_TIMER1_CMP3_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER1_VALUE = 0x40d1 # macro
|
|
regGFX_IMU_TIMER1_VALUE_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER2_CTRL0 = 0x40d2 # macro
|
|
regGFX_IMU_TIMER2_CTRL0_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER2_CTRL1 = 0x40d3 # macro
|
|
regGFX_IMU_TIMER2_CTRL1_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER2_CMP_AUTOINC = 0x40d4 # macro
|
|
regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER2_CMP_INTEN = 0x40d5 # macro
|
|
regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER2_CMP0 = 0x40d6 # macro
|
|
regGFX_IMU_TIMER2_CMP0_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER2_CMP1 = 0x40d7 # macro
|
|
regGFX_IMU_TIMER2_CMP1_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER2_CMP3 = 0x40d9 # macro
|
|
regGFX_IMU_TIMER2_CMP3_BASE_IDX = 1 # macro
|
|
regGFX_IMU_TIMER2_VALUE = 0x40da # macro
|
|
regGFX_IMU_TIMER2_VALUE_BASE_IDX = 1 # macro
|
|
regGFX_IMU_FUSE_CTRL = 0x40e0 # macro
|
|
regGFX_IMU_FUSE_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_D_RAM_ADDR = 0x40fc # macro
|
|
regGFX_IMU_D_RAM_ADDR_BASE_IDX = 1 # macro
|
|
regGFX_IMU_D_RAM_DATA = 0x40fd # macro
|
|
regGFX_IMU_D_RAM_DATA_BASE_IDX = 1 # macro
|
|
regGFX_IMU_GFX_IH_GASKET_CTRL = 0x40ff # macro
|
|
regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_BOOTLOADER_ADDR_HI = 0x5f81 # macro
|
|
regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_BOOTLOADER_ADDR_LO = 0x5f82 # macro
|
|
regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX = 1 # macro
|
|
regGFX_IMU_RLC_BOOTLOADER_SIZE = 0x5f83 # macro
|
|
regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX = 1 # macro
|
|
regGFX_IMU_I_RAM_ADDR = 0x5f90 # macro
|
|
regGFX_IMU_I_RAM_ADDR_BASE_IDX = 1 # macro
|
|
regGFX_IMU_I_RAM_DATA = 0x5f91 # macro
|
|
regGFX_IMU_I_RAM_DATA_BASE_IDX = 1 # macro
|
|
ixGC_CAC_ID = 0x0000 # macro
|
|
ixGC_CAC_CNTL = 0x0001 # macro
|
|
ixGC_CAC_ACC_CP0 = 0x0010 # macro
|
|
ixGC_CAC_ACC_CP1 = 0x0011 # macro
|
|
ixGC_CAC_ACC_CP2 = 0x0012 # macro
|
|
ixGC_CAC_ACC_EA0 = 0x0013 # macro
|
|
ixGC_CAC_ACC_EA1 = 0x0014 # macro
|
|
ixGC_CAC_ACC_EA2 = 0x0015 # macro
|
|
ixGC_CAC_ACC_EA3 = 0x0016 # macro
|
|
ixGC_CAC_ACC_EA4 = 0x0017 # macro
|
|
ixGC_CAC_ACC_EA5 = 0x0018 # macro
|
|
ixGC_CAC_ACC_UTCL2_ROUTER0 = 0x0019 # macro
|
|
ixGC_CAC_ACC_UTCL2_ROUTER1 = 0x001a # macro
|
|
ixGC_CAC_ACC_UTCL2_ROUTER2 = 0x001b # macro
|
|
ixGC_CAC_ACC_UTCL2_ROUTER3 = 0x001c # macro
|
|
ixGC_CAC_ACC_UTCL2_ROUTER4 = 0x001d # macro
|
|
ixGC_CAC_ACC_UTCL2_ROUTER5 = 0x001e # macro
|
|
ixGC_CAC_ACC_UTCL2_ROUTER6 = 0x001f # macro
|
|
ixGC_CAC_ACC_UTCL2_ROUTER7 = 0x0020 # macro
|
|
ixGC_CAC_ACC_UTCL2_ROUTER8 = 0x0021 # macro
|
|
ixGC_CAC_ACC_UTCL2_ROUTER9 = 0x0022 # macro
|
|
ixGC_CAC_ACC_UTCL2_VML20 = 0x0023 # macro
|
|
ixGC_CAC_ACC_UTCL2_VML21 = 0x0024 # macro
|
|
ixGC_CAC_ACC_UTCL2_VML22 = 0x0025 # macro
|
|
ixGC_CAC_ACC_UTCL2_VML23 = 0x0026 # macro
|
|
ixGC_CAC_ACC_UTCL2_VML24 = 0x0027 # macro
|
|
ixGC_CAC_ACC_UTCL2_WALKER0 = 0x0028 # macro
|
|
ixGC_CAC_ACC_UTCL2_WALKER1 = 0x0029 # macro
|
|
ixGC_CAC_ACC_UTCL2_WALKER2 = 0x002a # macro
|
|
ixGC_CAC_ACC_UTCL2_WALKER3 = 0x002b # macro
|
|
ixGC_CAC_ACC_UTCL2_WALKER4 = 0x002c # macro
|
|
ixGC_CAC_ACC_GDS0 = 0x002d # macro
|
|
ixGC_CAC_ACC_GDS1 = 0x002e # macro
|
|
ixGC_CAC_ACC_GDS2 = 0x002f # macro
|
|
ixGC_CAC_ACC_GDS3 = 0x0030 # macro
|
|
ixGC_CAC_ACC_GDS4 = 0x0031 # macro
|
|
ixGC_CAC_ACC_GE0 = 0x0032 # macro
|
|
ixGC_CAC_ACC_GE1 = 0x0033 # macro
|
|
ixGC_CAC_ACC_GE2 = 0x0034 # macro
|
|
ixGC_CAC_ACC_GE3 = 0x0035 # macro
|
|
ixGC_CAC_ACC_GE4 = 0x0036 # macro
|
|
ixGC_CAC_ACC_GE5 = 0x0037 # macro
|
|
ixGC_CAC_ACC_GE6 = 0x0038 # macro
|
|
ixGC_CAC_ACC_GE7 = 0x0039 # macro
|
|
ixGC_CAC_ACC_GE8 = 0x003a # macro
|
|
ixGC_CAC_ACC_GE9 = 0x003b # macro
|
|
ixGC_CAC_ACC_GE10 = 0x003c # macro
|
|
ixGC_CAC_ACC_GE11 = 0x003d # macro
|
|
ixGC_CAC_ACC_GE12 = 0x003e # macro
|
|
ixGC_CAC_ACC_GE13 = 0x003f # macro
|
|
ixGC_CAC_ACC_GE14 = 0x0040 # macro
|
|
ixGC_CAC_ACC_GE15 = 0x0041 # macro
|
|
ixGC_CAC_ACC_GE16 = 0x0042 # macro
|
|
ixGC_CAC_ACC_GE17 = 0x0043 # macro
|
|
ixGC_CAC_ACC_GE18 = 0x0044 # macro
|
|
ixGC_CAC_ACC_GE19 = 0x0045 # macro
|
|
ixGC_CAC_ACC_GE20 = 0x0046 # macro
|
|
ixGC_CAC_ACC_PMM0 = 0x0047 # macro
|
|
ixGC_CAC_ACC_GL2C0 = 0x0048 # macro
|
|
ixGC_CAC_ACC_GL2C1 = 0x0049 # macro
|
|
ixGC_CAC_ACC_GL2C2 = 0x004a # macro
|
|
ixGC_CAC_ACC_GL2C3 = 0x004b # macro
|
|
ixGC_CAC_ACC_GL2C4 = 0x004c # macro
|
|
ixGC_CAC_ACC_PH0 = 0x004d # macro
|
|
ixGC_CAC_ACC_PH1 = 0x004e # macro
|
|
ixGC_CAC_ACC_PH2 = 0x004f # macro
|
|
ixGC_CAC_ACC_PH3 = 0x0050 # macro
|
|
ixGC_CAC_ACC_PH4 = 0x0051 # macro
|
|
ixGC_CAC_ACC_PH5 = 0x0052 # macro
|
|
ixGC_CAC_ACC_PH6 = 0x0053 # macro
|
|
ixGC_CAC_ACC_PH7 = 0x0054 # macro
|
|
ixGC_CAC_ACC_SDMA0 = 0x0055 # macro
|
|
ixGC_CAC_ACC_SDMA1 = 0x0056 # macro
|
|
ixGC_CAC_ACC_SDMA2 = 0x0057 # macro
|
|
ixGC_CAC_ACC_SDMA3 = 0x0058 # macro
|
|
ixGC_CAC_ACC_SDMA4 = 0x0059 # macro
|
|
ixGC_CAC_ACC_SDMA5 = 0x005a # macro
|
|
ixGC_CAC_ACC_SDMA6 = 0x005b # macro
|
|
ixGC_CAC_ACC_SDMA7 = 0x005c # macro
|
|
ixGC_CAC_ACC_SDMA8 = 0x005d # macro
|
|
ixGC_CAC_ACC_SDMA9 = 0x005e # macro
|
|
ixGC_CAC_ACC_SDMA10 = 0x005f # macro
|
|
ixGC_CAC_ACC_SDMA11 = 0x0060 # macro
|
|
ixGC_CAC_ACC_CHC0 = 0x0061 # macro
|
|
ixGC_CAC_ACC_CHC1 = 0x0062 # macro
|
|
ixGC_CAC_ACC_CHC2 = 0x0063 # macro
|
|
ixGC_CAC_ACC_GUS0 = 0x0064 # macro
|
|
ixGC_CAC_ACC_GUS1 = 0x0065 # macro
|
|
ixGC_CAC_ACC_GUS2 = 0x0066 # macro
|
|
ixGC_CAC_ACC_RLC0 = 0x0067 # macro
|
|
ixRELEASE_TO_STALL_LUT_1_8 = 0x0100 # macro
|
|
ixRELEASE_TO_STALL_LUT_9_16 = 0x0101 # macro
|
|
ixRELEASE_TO_STALL_LUT_17_20 = 0x0102 # macro
|
|
ixSTALL_TO_RELEASE_LUT_1_4 = 0x0103 # macro
|
|
ixSTALL_TO_RELEASE_LUT_5_7 = 0x0104 # macro
|
|
ixSTALL_TO_PWRBRK_LUT_1_4 = 0x0105 # macro
|
|
ixSTALL_TO_PWRBRK_LUT_5_7 = 0x0106 # macro
|
|
ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 = 0x0107 # macro
|
|
ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 = 0x0108 # macro
|
|
ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 = 0x0109 # macro
|
|
ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 = 0x010a # macro
|
|
ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 = 0x010b # macro
|
|
ixFIXED_PATTERN_PERF_COUNTER_1 = 0x010c # macro
|
|
ixFIXED_PATTERN_PERF_COUNTER_2 = 0x010d # macro
|
|
ixFIXED_PATTERN_PERF_COUNTER_3 = 0x010e # macro
|
|
ixFIXED_PATTERN_PERF_COUNTER_4 = 0x010f # macro
|
|
ixFIXED_PATTERN_PERF_COUNTER_5 = 0x0110 # macro
|
|
ixFIXED_PATTERN_PERF_COUNTER_6 = 0x0111 # macro
|
|
ixFIXED_PATTERN_PERF_COUNTER_7 = 0x0112 # macro
|
|
ixFIXED_PATTERN_PERF_COUNTER_8 = 0x0113 # macro
|
|
ixFIXED_PATTERN_PERF_COUNTER_9 = 0x0114 # macro
|
|
ixFIXED_PATTERN_PERF_COUNTER_10 = 0x0115 # macro
|
|
ixHW_LUT_UPDATE_STATUS = 0x0116 # macro
|
|
ixSE_CAC_ID = 0x0000 # macro
|
|
ixSE_CAC_CNTL = 0x0001 # macro
|
|
ixRTAVFS_REG0 = 0x0000 # macro
|
|
ixRTAVFS_REG1 = 0x0001 # macro
|
|
ixRTAVFS_REG2 = 0x0002 # macro
|
|
ixRTAVFS_REG3 = 0x0003 # macro
|
|
ixRTAVFS_REG4 = 0x0004 # macro
|
|
ixRTAVFS_REG5 = 0x0005 # macro
|
|
ixRTAVFS_REG6 = 0x0006 # macro
|
|
ixRTAVFS_REG7 = 0x0007 # macro
|
|
ixRTAVFS_REG8 = 0x0008 # macro
|
|
ixRTAVFS_REG9 = 0x0009 # macro
|
|
ixRTAVFS_REG10 = 0x000a # macro
|
|
ixRTAVFS_REG11 = 0x000b # macro
|
|
ixRTAVFS_REG12 = 0x000c # macro
|
|
ixRTAVFS_REG13 = 0x000d # macro
|
|
ixRTAVFS_REG14 = 0x000e # macro
|
|
ixRTAVFS_REG15 = 0x000f # macro
|
|
ixRTAVFS_REG16 = 0x0010 # macro
|
|
ixRTAVFS_REG17 = 0x0011 # macro
|
|
ixRTAVFS_REG18 = 0x0012 # macro
|
|
ixRTAVFS_REG19 = 0x0013 # macro
|
|
ixRTAVFS_REG20 = 0x0014 # macro
|
|
ixRTAVFS_REG21 = 0x0015 # macro
|
|
ixRTAVFS_REG22 = 0x0016 # macro
|
|
ixRTAVFS_REG23 = 0x0017 # macro
|
|
ixRTAVFS_REG24 = 0x0018 # macro
|
|
ixRTAVFS_REG25 = 0x0019 # macro
|
|
ixRTAVFS_REG26 = 0x001a # macro
|
|
ixRTAVFS_REG27 = 0x001b # macro
|
|
ixRTAVFS_REG28 = 0x001c # macro
|
|
ixRTAVFS_REG29 = 0x001d # macro
|
|
ixRTAVFS_REG30 = 0x001e # macro
|
|
ixRTAVFS_REG31 = 0x001f # macro
|
|
ixRTAVFS_REG32 = 0x0020 # macro
|
|
ixRTAVFS_REG33 = 0x0021 # macro
|
|
ixRTAVFS_REG34 = 0x0022 # macro
|
|
ixRTAVFS_REG35 = 0x0023 # macro
|
|
ixRTAVFS_REG36 = 0x0024 # macro
|
|
ixRTAVFS_REG37 = 0x0025 # macro
|
|
ixRTAVFS_REG38 = 0x0026 # macro
|
|
ixRTAVFS_REG39 = 0x0027 # macro
|
|
ixRTAVFS_REG40 = 0x0028 # macro
|
|
ixRTAVFS_REG41 = 0x0029 # macro
|
|
ixRTAVFS_REG42 = 0x002a # macro
|
|
ixRTAVFS_REG43 = 0x002b # macro
|
|
ixRTAVFS_REG44 = 0x002c # macro
|
|
ixRTAVFS_REG45 = 0x002d # macro
|
|
ixRTAVFS_REG46 = 0x002e # macro
|
|
ixRTAVFS_REG47 = 0x002f # macro
|
|
ixRTAVFS_REG48 = 0x0030 # macro
|
|
ixRTAVFS_REG49 = 0x0031 # macro
|
|
ixRTAVFS_REG50 = 0x0032 # macro
|
|
ixRTAVFS_REG51 = 0x0033 # macro
|
|
ixRTAVFS_REG52 = 0x0034 # macro
|
|
ixRTAVFS_REG53 = 0x0035 # macro
|
|
ixRTAVFS_REG54 = 0x0036 # macro
|
|
ixRTAVFS_REG55 = 0x0037 # macro
|
|
ixRTAVFS_REG56 = 0x0038 # macro
|
|
ixRTAVFS_REG57 = 0x0039 # macro
|
|
ixRTAVFS_REG58 = 0x003a # macro
|
|
ixRTAVFS_REG59 = 0x003b # macro
|
|
ixRTAVFS_REG60 = 0x003c # macro
|
|
ixRTAVFS_REG61 = 0x003d # macro
|
|
ixRTAVFS_REG62 = 0x003e # macro
|
|
ixRTAVFS_REG63 = 0x003f # macro
|
|
ixRTAVFS_REG64 = 0x0040 # macro
|
|
ixRTAVFS_REG65 = 0x0041 # macro
|
|
ixRTAVFS_REG66 = 0x0042 # macro
|
|
ixRTAVFS_REG67 = 0x0043 # macro
|
|
ixRTAVFS_REG68 = 0x0044 # macro
|
|
ixRTAVFS_REG69 = 0x0045 # macro
|
|
ixRTAVFS_REG70 = 0x0046 # macro
|
|
ixRTAVFS_REG71 = 0x0047 # macro
|
|
ixRTAVFS_REG72 = 0x0048 # macro
|
|
ixRTAVFS_REG73 = 0x0049 # macro
|
|
ixRTAVFS_REG74 = 0x004a # macro
|
|
ixRTAVFS_REG75 = 0x004b # macro
|
|
ixRTAVFS_REG76 = 0x004c # macro
|
|
ixRTAVFS_REG77 = 0x004d # macro
|
|
ixRTAVFS_REG78 = 0x004e # macro
|
|
ixRTAVFS_REG79 = 0x004f # macro
|
|
ixRTAVFS_REG80 = 0x0050 # macro
|
|
ixRTAVFS_REG81 = 0x0051 # macro
|
|
ixRTAVFS_REG82 = 0x0052 # macro
|
|
ixRTAVFS_REG83 = 0x0053 # macro
|
|
ixRTAVFS_REG84 = 0x0054 # macro
|
|
ixRTAVFS_REG85 = 0x0055 # macro
|
|
ixRTAVFS_REG86 = 0x0056 # macro
|
|
ixRTAVFS_REG87 = 0x0057 # macro
|
|
ixRTAVFS_REG88 = 0x0058 # macro
|
|
ixRTAVFS_REG89 = 0x0059 # macro
|
|
ixRTAVFS_REG90 = 0x005a # macro
|
|
ixRTAVFS_REG91 = 0x005b # macro
|
|
ixRTAVFS_REG92 = 0x005c # macro
|
|
ixRTAVFS_REG93 = 0x005d # macro
|
|
ixRTAVFS_REG94 = 0x005e # macro
|
|
ixRTAVFS_REG95 = 0x005f # macro
|
|
ixRTAVFS_REG96 = 0x0060 # macro
|
|
ixRTAVFS_REG97 = 0x0061 # macro
|
|
ixRTAVFS_REG98 = 0x0062 # macro
|
|
ixRTAVFS_REG99 = 0x0063 # macro
|
|
ixRTAVFS_REG100 = 0x0064 # macro
|
|
ixRTAVFS_REG101 = 0x0065 # macro
|
|
ixRTAVFS_REG102 = 0x0066 # macro
|
|
ixRTAVFS_REG103 = 0x0067 # macro
|
|
ixRTAVFS_REG104 = 0x0068 # macro
|
|
ixRTAVFS_REG105 = 0x0069 # macro
|
|
ixRTAVFS_REG106 = 0x006a # macro
|
|
ixRTAVFS_REG107 = 0x006b # macro
|
|
ixRTAVFS_REG108 = 0x006c # macro
|
|
ixRTAVFS_REG109 = 0x006d # macro
|
|
ixRTAVFS_REG110 = 0x006e # macro
|
|
ixRTAVFS_REG111 = 0x006f # macro
|
|
ixRTAVFS_REG112 = 0x0070 # macro
|
|
ixRTAVFS_REG113 = 0x0071 # macro
|
|
ixRTAVFS_REG114 = 0x0072 # macro
|
|
ixRTAVFS_REG115 = 0x0073 # macro
|
|
ixRTAVFS_REG116 = 0x0074 # macro
|
|
ixRTAVFS_REG117 = 0x0075 # macro
|
|
ixRTAVFS_REG118 = 0x0076 # macro
|
|
ixRTAVFS_REG119 = 0x0077 # macro
|
|
ixRTAVFS_REG120 = 0x0078 # macro
|
|
ixRTAVFS_REG121 = 0x0079 # macro
|
|
ixRTAVFS_REG122 = 0x007a # macro
|
|
ixRTAVFS_REG123 = 0x007b # macro
|
|
ixRTAVFS_REG124 = 0x007c # macro
|
|
ixRTAVFS_REG125 = 0x007d # macro
|
|
ixRTAVFS_REG126 = 0x007e # macro
|
|
ixRTAVFS_REG127 = 0x007f # macro
|
|
ixRTAVFS_REG128 = 0x0080 # macro
|
|
ixRTAVFS_REG129 = 0x0081 # macro
|
|
ixRTAVFS_REG130 = 0x0082 # macro
|
|
ixRTAVFS_REG131 = 0x0083 # macro
|
|
ixRTAVFS_REG132 = 0x0084 # macro
|
|
ixRTAVFS_REG133 = 0x0085 # macro
|
|
ixRTAVFS_REG134 = 0x0086 # macro
|
|
ixRTAVFS_REG135 = 0x0087 # macro
|
|
ixRTAVFS_REG136 = 0x0088 # macro
|
|
ixRTAVFS_REG137 = 0x0089 # macro
|
|
ixRTAVFS_REG138 = 0x008a # macro
|
|
ixRTAVFS_REG139 = 0x008b # macro
|
|
ixRTAVFS_REG140 = 0x008c # macro
|
|
ixRTAVFS_REG141 = 0x008d # macro
|
|
ixRTAVFS_REG142 = 0x008e # macro
|
|
ixRTAVFS_REG143 = 0x008f # macro
|
|
ixRTAVFS_REG144 = 0x0090 # macro
|
|
ixRTAVFS_REG145 = 0x0091 # macro
|
|
ixRTAVFS_REG146 = 0x0092 # macro
|
|
ixRTAVFS_REG147 = 0x0093 # macro
|
|
ixRTAVFS_REG148 = 0x0094 # macro
|
|
ixRTAVFS_REG149 = 0x0095 # macro
|
|
ixRTAVFS_REG150 = 0x0096 # macro
|
|
ixRTAVFS_REG151 = 0x0097 # macro
|
|
ixRTAVFS_REG152 = 0x0098 # macro
|
|
ixRTAVFS_REG153 = 0x0099 # macro
|
|
ixRTAVFS_REG154 = 0x009a # macro
|
|
ixRTAVFS_REG155 = 0x009b # macro
|
|
ixRTAVFS_REG156 = 0x009c # macro
|
|
ixRTAVFS_REG157 = 0x009d # macro
|
|
ixRTAVFS_REG158 = 0x009e # macro
|
|
ixRTAVFS_REG159 = 0x009f # macro
|
|
ixRTAVFS_REG160 = 0x00a0 # macro
|
|
ixRTAVFS_REG161 = 0x00a1 # macro
|
|
ixRTAVFS_REG162 = 0x00a2 # macro
|
|
ixRTAVFS_REG163 = 0x00a3 # macro
|
|
ixRTAVFS_REG164 = 0x00a4 # macro
|
|
ixRTAVFS_REG165 = 0x00a5 # macro
|
|
ixRTAVFS_REG166 = 0x00a6 # macro
|
|
ixRTAVFS_REG167 = 0x00a7 # macro
|
|
ixRTAVFS_REG168 = 0x00a8 # macro
|
|
ixRTAVFS_REG169 = 0x00a9 # macro
|
|
ixRTAVFS_REG170 = 0x00aa # macro
|
|
ixRTAVFS_REG171 = 0x00ab # macro
|
|
ixRTAVFS_REG172 = 0x00ac # macro
|
|
ixRTAVFS_REG173 = 0x00ad # macro
|
|
ixRTAVFS_REG174 = 0x00ae # macro
|
|
ixRTAVFS_REG175 = 0x00af # macro
|
|
ixRTAVFS_REG176 = 0x00b0 # macro
|
|
ixRTAVFS_REG177 = 0x00b1 # macro
|
|
ixRTAVFS_REG178 = 0x00b2 # macro
|
|
ixRTAVFS_REG179 = 0x00b3 # macro
|
|
ixRTAVFS_REG180 = 0x00b4 # macro
|
|
ixRTAVFS_REG181 = 0x00b5 # macro
|
|
ixRTAVFS_REG182 = 0x00b6 # macro
|
|
ixRTAVFS_REG183 = 0x00b7 # macro
|
|
ixRTAVFS_REG184 = 0x00b8 # macro
|
|
ixRTAVFS_REG185 = 0x00b9 # macro
|
|
ixRTAVFS_REG186 = 0x00ba # macro
|
|
ixRTAVFS_REG187 = 0x00bb # macro
|
|
ixRTAVFS_REG188 = 0x00bc # macro
|
|
ixRTAVFS_REG189 = 0x00bd # macro
|
|
ixRTAVFS_REG190 = 0x00be # macro
|
|
ixRTAVFS_REG191 = 0x00bf # macro
|
|
ixRTAVFS_REG192 = 0x00c0 # macro
|
|
ixRTAVFS_REG193 = 0x00c1 # macro
|
|
ixRTAVFS_REG194 = 0x00c2 # macro
|
|
ixSQ_DEBUG_STS_LOCAL = 0x0008 # macro
|
|
ixSQ_DEBUG_CTRL_LOCAL = 0x0009 # macro
|
|
ixSQ_WAVE_ACTIVE = 0x000a # macro
|
|
ixSQ_WAVE_VALID_AND_IDLE = 0x000b # macro
|
|
ixSQ_WAVE_MODE = 0x0101 # macro
|
|
ixSQ_WAVE_STATUS = 0x0102 # macro
|
|
ixSQ_WAVE_TRAPSTS = 0x0103 # macro
|
|
ixSQ_WAVE_GPR_ALLOC = 0x0105 # macro
|
|
ixSQ_WAVE_LDS_ALLOC = 0x0106 # macro
|
|
ixSQ_WAVE_IB_STS = 0x0107 # macro
|
|
ixSQ_WAVE_PC_LO = 0x0108 # macro
|
|
ixSQ_WAVE_PC_HI = 0x0109 # macro
|
|
ixSQ_WAVE_IB_DBG1 = 0x010d # macro
|
|
ixSQ_WAVE_FLUSH_IB = 0x010e # macro
|
|
ixSQ_WAVE_FLAT_SCRATCH_LO = 0x0114 # macro
|
|
ixSQ_WAVE_FLAT_SCRATCH_HI = 0x0115 # macro
|
|
ixSQ_WAVE_HW_ID1 = 0x0117 # macro
|
|
ixSQ_WAVE_HW_ID2 = 0x0118 # macro
|
|
ixSQ_WAVE_POPS_PACKER = 0x0119 # macro
|
|
ixSQ_WAVE_SCHED_MODE = 0x011a # macro
|
|
ixSQ_WAVE_IB_STS2 = 0x011c # macro
|
|
ixSQ_WAVE_SHADER_CYCLES = 0x011d # macro
|
|
ixSQ_WAVE_TTMP0 = 0x026c # macro
|
|
ixSQ_WAVE_TTMP1 = 0x026d # macro
|
|
ixSQ_WAVE_TTMP3 = 0x026f # macro
|
|
ixSQ_WAVE_TTMP4 = 0x0270 # macro
|
|
ixSQ_WAVE_TTMP5 = 0x0271 # macro
|
|
ixSQ_WAVE_TTMP6 = 0x0272 # macro
|
|
ixSQ_WAVE_TTMP7 = 0x0273 # macro
|
|
ixSQ_WAVE_TTMP8 = 0x0274 # macro
|
|
ixSQ_WAVE_TTMP9 = 0x0275 # macro
|
|
ixSQ_WAVE_TTMP10 = 0x0276 # macro
|
|
ixSQ_WAVE_TTMP11 = 0x0277 # macro
|
|
ixSQ_WAVE_TTMP12 = 0x0278 # macro
|
|
ixSQ_WAVE_TTMP13 = 0x0279 # macro
|
|
ixSQ_WAVE_TTMP14 = 0x027a # macro
|
|
ixSQ_WAVE_TTMP15 = 0x027b # macro
|
|
ixSQ_WAVE_M0 = 0x027d # macro
|
|
ixSQ_WAVE_EXEC_LO = 0x027e # macro
|
|
ixSQ_WAVE_EXEC_HI = 0x027f # macro
|
|
_sienna_cichlid_ip_offset_HEADER = True # macro
|
|
MAX_INSTANCE = 7 # macro
|
|
MAX_SEGMENT = 5 # macro
|
|
ATHUB_BASE__INST0_SEG0 = 0x00000C00 # macro
|
|
ATHUB_BASE__INST0_SEG1 = 0x02408C00 # macro
|
|
ATHUB_BASE__INST0_SEG2 = 0 # macro
|
|
ATHUB_BASE__INST0_SEG3 = 0 # macro
|
|
ATHUB_BASE__INST0_SEG4 = 0 # macro
|
|
ATHUB_BASE__INST1_SEG0 = 0 # macro
|
|
ATHUB_BASE__INST1_SEG1 = 0 # macro
|
|
ATHUB_BASE__INST1_SEG2 = 0 # macro
|
|
ATHUB_BASE__INST1_SEG3 = 0 # macro
|
|
ATHUB_BASE__INST1_SEG4 = 0 # macro
|
|
ATHUB_BASE__INST2_SEG0 = 0 # macro
|
|
ATHUB_BASE__INST2_SEG1 = 0 # macro
|
|
ATHUB_BASE__INST2_SEG2 = 0 # macro
|
|
ATHUB_BASE__INST2_SEG3 = 0 # macro
|
|
ATHUB_BASE__INST2_SEG4 = 0 # macro
|
|
ATHUB_BASE__INST3_SEG0 = 0 # macro
|
|
ATHUB_BASE__INST3_SEG1 = 0 # macro
|
|
ATHUB_BASE__INST3_SEG2 = 0 # macro
|
|
ATHUB_BASE__INST3_SEG3 = 0 # macro
|
|
ATHUB_BASE__INST3_SEG4 = 0 # macro
|
|
ATHUB_BASE__INST4_SEG0 = 0 # macro
|
|
ATHUB_BASE__INST4_SEG1 = 0 # macro
|
|
ATHUB_BASE__INST4_SEG2 = 0 # macro
|
|
ATHUB_BASE__INST4_SEG3 = 0 # macro
|
|
ATHUB_BASE__INST4_SEG4 = 0 # macro
|
|
ATHUB_BASE__INST5_SEG0 = 0 # macro
|
|
ATHUB_BASE__INST5_SEG1 = 0 # macro
|
|
ATHUB_BASE__INST5_SEG2 = 0 # macro
|
|
ATHUB_BASE__INST5_SEG3 = 0 # macro
|
|
ATHUB_BASE__INST5_SEG4 = 0 # macro
|
|
ATHUB_BASE__INST6_SEG0 = 0 # macro
|
|
ATHUB_BASE__INST6_SEG1 = 0 # macro
|
|
ATHUB_BASE__INST6_SEG2 = 0 # macro
|
|
ATHUB_BASE__INST6_SEG3 = 0 # macro
|
|
ATHUB_BASE__INST6_SEG4 = 0 # macro
|
|
CLK_BASE__INST0_SEG0 = 0x00016C00 # macro
|
|
CLK_BASE__INST0_SEG1 = 0x02401800 # macro
|
|
CLK_BASE__INST0_SEG2 = 0 # macro
|
|
CLK_BASE__INST0_SEG3 = 0 # macro
|
|
CLK_BASE__INST0_SEG4 = 0 # macro
|
|
CLK_BASE__INST1_SEG0 = 0x00016E00 # macro
|
|
CLK_BASE__INST1_SEG1 = 0x02401C00 # macro
|
|
CLK_BASE__INST1_SEG2 = 0 # macro
|
|
CLK_BASE__INST1_SEG3 = 0 # macro
|
|
CLK_BASE__INST1_SEG4 = 0 # macro
|
|
CLK_BASE__INST2_SEG0 = 0x00017000 # macro
|
|
CLK_BASE__INST2_SEG1 = 0x02402000 # macro
|
|
CLK_BASE__INST2_SEG2 = 0 # macro
|
|
CLK_BASE__INST2_SEG3 = 0 # macro
|
|
CLK_BASE__INST2_SEG4 = 0 # macro
|
|
CLK_BASE__INST3_SEG0 = 0x00017200 # macro
|
|
CLK_BASE__INST3_SEG1 = 0x02402400 # macro
|
|
CLK_BASE__INST3_SEG2 = 0 # macro
|
|
CLK_BASE__INST3_SEG3 = 0 # macro
|
|
CLK_BASE__INST3_SEG4 = 0 # macro
|
|
CLK_BASE__INST4_SEG0 = 0x0001B000 # macro
|
|
CLK_BASE__INST4_SEG1 = 0x0242D800 # macro
|
|
CLK_BASE__INST4_SEG2 = 0 # macro
|
|
CLK_BASE__INST4_SEG3 = 0 # macro
|
|
CLK_BASE__INST4_SEG4 = 0 # macro
|
|
CLK_BASE__INST5_SEG0 = 0x0001B200 # macro
|
|
CLK_BASE__INST5_SEG1 = 0x0242DC00 # macro
|
|
CLK_BASE__INST5_SEG2 = 0 # macro
|
|
CLK_BASE__INST5_SEG3 = 0 # macro
|
|
CLK_BASE__INST5_SEG4 = 0 # macro
|
|
CLK_BASE__INST6_SEG0 = 0x0001B400 # macro
|
|
CLK_BASE__INST6_SEG1 = 0x0242E000 # macro
|
|
CLK_BASE__INST6_SEG2 = 0 # macro
|
|
CLK_BASE__INST6_SEG3 = 0 # macro
|
|
CLK_BASE__INST6_SEG4 = 0 # macro
|
|
DF_BASE__INST0_SEG0 = 0x00007000 # macro
|
|
DF_BASE__INST0_SEG1 = 0x0240B800 # macro
|
|
DF_BASE__INST0_SEG2 = 0 # macro
|
|
DF_BASE__INST0_SEG3 = 0 # macro
|
|
DF_BASE__INST0_SEG4 = 0 # macro
|
|
DF_BASE__INST1_SEG0 = 0 # macro
|
|
DF_BASE__INST1_SEG1 = 0 # macro
|
|
DF_BASE__INST1_SEG2 = 0 # macro
|
|
DF_BASE__INST1_SEG3 = 0 # macro
|
|
DF_BASE__INST1_SEG4 = 0 # macro
|
|
DF_BASE__INST2_SEG0 = 0 # macro
|
|
DF_BASE__INST2_SEG1 = 0 # macro
|
|
DF_BASE__INST2_SEG2 = 0 # macro
|
|
DF_BASE__INST2_SEG3 = 0 # macro
|
|
DF_BASE__INST2_SEG4 = 0 # macro
|
|
DF_BASE__INST3_SEG0 = 0 # macro
|
|
DF_BASE__INST3_SEG1 = 0 # macro
|
|
DF_BASE__INST3_SEG2 = 0 # macro
|
|
DF_BASE__INST3_SEG3 = 0 # macro
|
|
DF_BASE__INST3_SEG4 = 0 # macro
|
|
DF_BASE__INST4_SEG0 = 0 # macro
|
|
DF_BASE__INST4_SEG1 = 0 # macro
|
|
DF_BASE__INST4_SEG2 = 0 # macro
|
|
DF_BASE__INST4_SEG3 = 0 # macro
|
|
DF_BASE__INST4_SEG4 = 0 # macro
|
|
DF_BASE__INST5_SEG0 = 0 # macro
|
|
DF_BASE__INST5_SEG1 = 0 # macro
|
|
DF_BASE__INST5_SEG2 = 0 # macro
|
|
DF_BASE__INST5_SEG3 = 0 # macro
|
|
DF_BASE__INST5_SEG4 = 0 # macro
|
|
DF_BASE__INST6_SEG0 = 0 # macro
|
|
DF_BASE__INST6_SEG1 = 0 # macro
|
|
DF_BASE__INST6_SEG2 = 0 # macro
|
|
DF_BASE__INST6_SEG3 = 0 # macro
|
|
DF_BASE__INST6_SEG4 = 0 # macro
|
|
DIO_BASE__INST0_SEG0 = 0x02404000 # macro
|
|
DIO_BASE__INST0_SEG1 = 0 # macro
|
|
DIO_BASE__INST0_SEG2 = 0 # macro
|
|
DIO_BASE__INST0_SEG3 = 0 # macro
|
|
DIO_BASE__INST0_SEG4 = 0 # macro
|
|
DIO_BASE__INST1_SEG0 = 0 # macro
|
|
DIO_BASE__INST1_SEG1 = 0 # macro
|
|
DIO_BASE__INST1_SEG2 = 0 # macro
|
|
DIO_BASE__INST1_SEG3 = 0 # macro
|
|
DIO_BASE__INST1_SEG4 = 0 # macro
|
|
DIO_BASE__INST2_SEG0 = 0 # macro
|
|
DIO_BASE__INST2_SEG1 = 0 # macro
|
|
DIO_BASE__INST2_SEG2 = 0 # macro
|
|
DIO_BASE__INST2_SEG3 = 0 # macro
|
|
DIO_BASE__INST2_SEG4 = 0 # macro
|
|
DIO_BASE__INST3_SEG0 = 0 # macro
|
|
DIO_BASE__INST3_SEG1 = 0 # macro
|
|
DIO_BASE__INST3_SEG2 = 0 # macro
|
|
DIO_BASE__INST3_SEG3 = 0 # macro
|
|
DIO_BASE__INST3_SEG4 = 0 # macro
|
|
DIO_BASE__INST4_SEG0 = 0 # macro
|
|
DIO_BASE__INST4_SEG1 = 0 # macro
|
|
DIO_BASE__INST4_SEG2 = 0 # macro
|
|
DIO_BASE__INST4_SEG3 = 0 # macro
|
|
DIO_BASE__INST4_SEG4 = 0 # macro
|
|
DIO_BASE__INST5_SEG0 = 0 # macro
|
|
DIO_BASE__INST5_SEG1 = 0 # macro
|
|
DIO_BASE__INST5_SEG2 = 0 # macro
|
|
DIO_BASE__INST5_SEG3 = 0 # macro
|
|
DIO_BASE__INST5_SEG4 = 0 # macro
|
|
DIO_BASE__INST6_SEG0 = 0 # macro
|
|
DIO_BASE__INST6_SEG1 = 0 # macro
|
|
DIO_BASE__INST6_SEG2 = 0 # macro
|
|
DIO_BASE__INST6_SEG3 = 0 # macro
|
|
DIO_BASE__INST6_SEG4 = 0 # macro
|
|
DCN_BASE__INST0_SEG0 = 0x00000012 # macro
|
|
DCN_BASE__INST0_SEG1 = 0x000000C0 # macro
|
|
DCN_BASE__INST0_SEG2 = 0x000034C0 # macro
|
|
DCN_BASE__INST0_SEG3 = 0x00009000 # macro
|
|
DCN_BASE__INST0_SEG4 = 0x02403C00 # macro
|
|
DCN_BASE__INST1_SEG0 = 0 # macro
|
|
DCN_BASE__INST1_SEG1 = 0 # macro
|
|
DCN_BASE__INST1_SEG2 = 0 # macro
|
|
DCN_BASE__INST1_SEG3 = 0 # macro
|
|
DCN_BASE__INST1_SEG4 = 0 # macro
|
|
DCN_BASE__INST2_SEG0 = 0 # macro
|
|
DCN_BASE__INST2_SEG1 = 0 # macro
|
|
DCN_BASE__INST2_SEG2 = 0 # macro
|
|
DCN_BASE__INST2_SEG3 = 0 # macro
|
|
DCN_BASE__INST2_SEG4 = 0 # macro
|
|
DCN_BASE__INST3_SEG0 = 0 # macro
|
|
DCN_BASE__INST3_SEG1 = 0 # macro
|
|
DCN_BASE__INST3_SEG2 = 0 # macro
|
|
DCN_BASE__INST3_SEG3 = 0 # macro
|
|
DCN_BASE__INST3_SEG4 = 0 # macro
|
|
DCN_BASE__INST4_SEG0 = 0 # macro
|
|
DCN_BASE__INST4_SEG1 = 0 # macro
|
|
DCN_BASE__INST4_SEG2 = 0 # macro
|
|
DCN_BASE__INST4_SEG3 = 0 # macro
|
|
DCN_BASE__INST4_SEG4 = 0 # macro
|
|
DCN_BASE__INST5_SEG0 = 0 # macro
|
|
DCN_BASE__INST5_SEG1 = 0 # macro
|
|
DCN_BASE__INST5_SEG2 = 0 # macro
|
|
DCN_BASE__INST5_SEG3 = 0 # macro
|
|
DCN_BASE__INST5_SEG4 = 0 # macro
|
|
DCN_BASE__INST6_SEG0 = 0 # macro
|
|
DCN_BASE__INST6_SEG1 = 0 # macro
|
|
DCN_BASE__INST6_SEG2 = 0 # macro
|
|
DCN_BASE__INST6_SEG3 = 0 # macro
|
|
DCN_BASE__INST6_SEG4 = 0 # macro
|
|
DPCS_BASE__INST0_SEG0 = 0x00000012 # macro
|
|
DPCS_BASE__INST0_SEG1 = 0x000000C0 # macro
|
|
DPCS_BASE__INST0_SEG2 = 0x000034C0 # macro
|
|
DPCS_BASE__INST0_SEG3 = 0x00009000 # macro
|
|
DPCS_BASE__INST0_SEG4 = 0x02403C00 # macro
|
|
DPCS_BASE__INST1_SEG0 = 0 # macro
|
|
DPCS_BASE__INST1_SEG1 = 0 # macro
|
|
DPCS_BASE__INST1_SEG2 = 0 # macro
|
|
DPCS_BASE__INST1_SEG3 = 0 # macro
|
|
DPCS_BASE__INST1_SEG4 = 0 # macro
|
|
DPCS_BASE__INST2_SEG0 = 0 # macro
|
|
DPCS_BASE__INST2_SEG1 = 0 # macro
|
|
DPCS_BASE__INST2_SEG2 = 0 # macro
|
|
DPCS_BASE__INST2_SEG3 = 0 # macro
|
|
DPCS_BASE__INST2_SEG4 = 0 # macro
|
|
DPCS_BASE__INST3_SEG0 = 0 # macro
|
|
DPCS_BASE__INST3_SEG1 = 0 # macro
|
|
DPCS_BASE__INST3_SEG2 = 0 # macro
|
|
DPCS_BASE__INST3_SEG3 = 0 # macro
|
|
DPCS_BASE__INST3_SEG4 = 0 # macro
|
|
DPCS_BASE__INST4_SEG0 = 0 # macro
|
|
DPCS_BASE__INST4_SEG1 = 0 # macro
|
|
DPCS_BASE__INST4_SEG2 = 0 # macro
|
|
DPCS_BASE__INST4_SEG3 = 0 # macro
|
|
DPCS_BASE__INST4_SEG4 = 0 # macro
|
|
DPCS_BASE__INST5_SEG0 = 0 # macro
|
|
DPCS_BASE__INST5_SEG1 = 0 # macro
|
|
DPCS_BASE__INST5_SEG2 = 0 # macro
|
|
DPCS_BASE__INST5_SEG3 = 0 # macro
|
|
DPCS_BASE__INST5_SEG4 = 0 # macro
|
|
DPCS_BASE__INST6_SEG0 = 0 # macro
|
|
DPCS_BASE__INST6_SEG1 = 0 # macro
|
|
DPCS_BASE__INST6_SEG2 = 0 # macro
|
|
DPCS_BASE__INST6_SEG3 = 0 # macro
|
|
DPCS_BASE__INST6_SEG4 = 0 # macro
|
|
FUSE_BASE__INST0_SEG0 = 0x00017400 # macro
|
|
FUSE_BASE__INST0_SEG1 = 0x02401400 # macro
|
|
FUSE_BASE__INST0_SEG2 = 0 # macro
|
|
FUSE_BASE__INST0_SEG3 = 0 # macro
|
|
FUSE_BASE__INST0_SEG4 = 0 # macro
|
|
FUSE_BASE__INST1_SEG0 = 0 # macro
|
|
FUSE_BASE__INST1_SEG1 = 0 # macro
|
|
FUSE_BASE__INST1_SEG2 = 0 # macro
|
|
FUSE_BASE__INST1_SEG3 = 0 # macro
|
|
FUSE_BASE__INST1_SEG4 = 0 # macro
|
|
FUSE_BASE__INST2_SEG0 = 0 # macro
|
|
FUSE_BASE__INST2_SEG1 = 0 # macro
|
|
FUSE_BASE__INST2_SEG2 = 0 # macro
|
|
FUSE_BASE__INST2_SEG3 = 0 # macro
|
|
FUSE_BASE__INST2_SEG4 = 0 # macro
|
|
FUSE_BASE__INST3_SEG0 = 0 # macro
|
|
FUSE_BASE__INST3_SEG1 = 0 # macro
|
|
FUSE_BASE__INST3_SEG2 = 0 # macro
|
|
FUSE_BASE__INST3_SEG3 = 0 # macro
|
|
FUSE_BASE__INST3_SEG4 = 0 # macro
|
|
FUSE_BASE__INST4_SEG0 = 0 # macro
|
|
FUSE_BASE__INST4_SEG1 = 0 # macro
|
|
FUSE_BASE__INST4_SEG2 = 0 # macro
|
|
FUSE_BASE__INST4_SEG3 = 0 # macro
|
|
FUSE_BASE__INST4_SEG4 = 0 # macro
|
|
FUSE_BASE__INST5_SEG0 = 0 # macro
|
|
FUSE_BASE__INST5_SEG1 = 0 # macro
|
|
FUSE_BASE__INST5_SEG2 = 0 # macro
|
|
FUSE_BASE__INST5_SEG3 = 0 # macro
|
|
FUSE_BASE__INST5_SEG4 = 0 # macro
|
|
FUSE_BASE__INST6_SEG0 = 0 # macro
|
|
FUSE_BASE__INST6_SEG1 = 0 # macro
|
|
FUSE_BASE__INST6_SEG2 = 0 # macro
|
|
FUSE_BASE__INST6_SEG3 = 0 # macro
|
|
FUSE_BASE__INST6_SEG4 = 0 # macro
|
|
GC_BASE__INST0_SEG0 = 0x00001260 # macro
|
|
GC_BASE__INST0_SEG1 = 0x0000A000 # macro
|
|
GC_BASE__INST0_SEG2 = 0x0001C000 # macro
|
|
GC_BASE__INST0_SEG3 = 0x02402C00 # macro
|
|
GC_BASE__INST0_SEG4 = 0 # macro
|
|
GC_BASE__INST1_SEG0 = 0 # macro
|
|
GC_BASE__INST1_SEG1 = 0 # macro
|
|
GC_BASE__INST1_SEG2 = 0 # macro
|
|
GC_BASE__INST1_SEG3 = 0 # macro
|
|
GC_BASE__INST1_SEG4 = 0 # macro
|
|
GC_BASE__INST2_SEG0 = 0 # macro
|
|
GC_BASE__INST2_SEG1 = 0 # macro
|
|
GC_BASE__INST2_SEG2 = 0 # macro
|
|
GC_BASE__INST2_SEG3 = 0 # macro
|
|
GC_BASE__INST2_SEG4 = 0 # macro
|
|
GC_BASE__INST3_SEG0 = 0 # macro
|
|
GC_BASE__INST3_SEG1 = 0 # macro
|
|
GC_BASE__INST3_SEG2 = 0 # macro
|
|
GC_BASE__INST3_SEG3 = 0 # macro
|
|
GC_BASE__INST3_SEG4 = 0 # macro
|
|
GC_BASE__INST4_SEG0 = 0 # macro
|
|
GC_BASE__INST4_SEG1 = 0 # macro
|
|
GC_BASE__INST4_SEG2 = 0 # macro
|
|
GC_BASE__INST4_SEG3 = 0 # macro
|
|
GC_BASE__INST4_SEG4 = 0 # macro
|
|
GC_BASE__INST5_SEG0 = 0 # macro
|
|
GC_BASE__INST5_SEG1 = 0 # macro
|
|
GC_BASE__INST5_SEG2 = 0 # macro
|
|
GC_BASE__INST5_SEG3 = 0 # macro
|
|
GC_BASE__INST5_SEG4 = 0 # macro
|
|
GC_BASE__INST6_SEG0 = 0 # macro
|
|
GC_BASE__INST6_SEG1 = 0 # macro
|
|
GC_BASE__INST6_SEG2 = 0 # macro
|
|
GC_BASE__INST6_SEG3 = 0 # macro
|
|
GC_BASE__INST6_SEG4 = 0 # macro
|
|
HDA_BASE__INST0_SEG0 = 0x004C0000 # macro
|
|
HDA_BASE__INST0_SEG1 = 0x02404800 # macro
|
|
HDA_BASE__INST0_SEG2 = 0 # macro
|
|
HDA_BASE__INST0_SEG3 = 0 # macro
|
|
HDA_BASE__INST0_SEG4 = 0 # macro
|
|
HDA_BASE__INST1_SEG0 = 0 # macro
|
|
HDA_BASE__INST1_SEG1 = 0 # macro
|
|
HDA_BASE__INST1_SEG2 = 0 # macro
|
|
HDA_BASE__INST1_SEG3 = 0 # macro
|
|
HDA_BASE__INST1_SEG4 = 0 # macro
|
|
HDA_BASE__INST2_SEG0 = 0 # macro
|
|
HDA_BASE__INST2_SEG1 = 0 # macro
|
|
HDA_BASE__INST2_SEG2 = 0 # macro
|
|
HDA_BASE__INST2_SEG3 = 0 # macro
|
|
HDA_BASE__INST2_SEG4 = 0 # macro
|
|
HDA_BASE__INST3_SEG0 = 0 # macro
|
|
HDA_BASE__INST3_SEG1 = 0 # macro
|
|
HDA_BASE__INST3_SEG2 = 0 # macro
|
|
HDA_BASE__INST3_SEG3 = 0 # macro
|
|
HDA_BASE__INST3_SEG4 = 0 # macro
|
|
HDA_BASE__INST4_SEG0 = 0 # macro
|
|
HDA_BASE__INST4_SEG1 = 0 # macro
|
|
HDA_BASE__INST4_SEG2 = 0 # macro
|
|
HDA_BASE__INST4_SEG3 = 0 # macro
|
|
HDA_BASE__INST4_SEG4 = 0 # macro
|
|
HDA_BASE__INST5_SEG0 = 0 # macro
|
|
HDA_BASE__INST5_SEG1 = 0 # macro
|
|
HDA_BASE__INST5_SEG2 = 0 # macro
|
|
HDA_BASE__INST5_SEG3 = 0 # macro
|
|
HDA_BASE__INST5_SEG4 = 0 # macro
|
|
HDA_BASE__INST6_SEG0 = 0 # macro
|
|
HDA_BASE__INST6_SEG1 = 0 # macro
|
|
HDA_BASE__INST6_SEG2 = 0 # macro
|
|
HDA_BASE__INST6_SEG3 = 0 # macro
|
|
HDA_BASE__INST6_SEG4 = 0 # macro
|
|
HDP_BASE__INST0_SEG0 = 0x00000F20 # macro
|
|
HDP_BASE__INST0_SEG1 = 0x0240A400 # macro
|
|
HDP_BASE__INST0_SEG2 = 0 # macro
|
|
HDP_BASE__INST0_SEG3 = 0 # macro
|
|
HDP_BASE__INST0_SEG4 = 0 # macro
|
|
HDP_BASE__INST1_SEG0 = 0 # macro
|
|
HDP_BASE__INST1_SEG1 = 0 # macro
|
|
HDP_BASE__INST1_SEG2 = 0 # macro
|
|
HDP_BASE__INST1_SEG3 = 0 # macro
|
|
HDP_BASE__INST1_SEG4 = 0 # macro
|
|
HDP_BASE__INST2_SEG0 = 0 # macro
|
|
HDP_BASE__INST2_SEG1 = 0 # macro
|
|
HDP_BASE__INST2_SEG2 = 0 # macro
|
|
HDP_BASE__INST2_SEG3 = 0 # macro
|
|
HDP_BASE__INST2_SEG4 = 0 # macro
|
|
HDP_BASE__INST3_SEG0 = 0 # macro
|
|
HDP_BASE__INST3_SEG1 = 0 # macro
|
|
HDP_BASE__INST3_SEG2 = 0 # macro
|
|
HDP_BASE__INST3_SEG3 = 0 # macro
|
|
HDP_BASE__INST3_SEG4 = 0 # macro
|
|
HDP_BASE__INST4_SEG0 = 0 # macro
|
|
HDP_BASE__INST4_SEG1 = 0 # macro
|
|
HDP_BASE__INST4_SEG2 = 0 # macro
|
|
HDP_BASE__INST4_SEG3 = 0 # macro
|
|
HDP_BASE__INST4_SEG4 = 0 # macro
|
|
HDP_BASE__INST5_SEG0 = 0 # macro
|
|
HDP_BASE__INST5_SEG1 = 0 # macro
|
|
HDP_BASE__INST5_SEG2 = 0 # macro
|
|
HDP_BASE__INST5_SEG3 = 0 # macro
|
|
HDP_BASE__INST5_SEG4 = 0 # macro
|
|
HDP_BASE__INST6_SEG0 = 0 # macro
|
|
HDP_BASE__INST6_SEG1 = 0 # macro
|
|
HDP_BASE__INST6_SEG2 = 0 # macro
|
|
HDP_BASE__INST6_SEG3 = 0 # macro
|
|
HDP_BASE__INST6_SEG4 = 0 # macro
|
|
MMHUB_BASE__INST0_SEG0 = 0x0001A000 # macro
|
|
MMHUB_BASE__INST0_SEG1 = 0x02408800 # macro
|
|
MMHUB_BASE__INST0_SEG2 = 0 # macro
|
|
MMHUB_BASE__INST0_SEG3 = 0 # macro
|
|
MMHUB_BASE__INST0_SEG4 = 0 # macro
|
|
MMHUB_BASE__INST1_SEG0 = 0 # macro
|
|
MMHUB_BASE__INST1_SEG1 = 0 # macro
|
|
MMHUB_BASE__INST1_SEG2 = 0 # macro
|
|
MMHUB_BASE__INST1_SEG3 = 0 # macro
|
|
MMHUB_BASE__INST1_SEG4 = 0 # macro
|
|
MMHUB_BASE__INST2_SEG0 = 0 # macro
|
|
MMHUB_BASE__INST2_SEG1 = 0 # macro
|
|
MMHUB_BASE__INST2_SEG2 = 0 # macro
|
|
MMHUB_BASE__INST2_SEG3 = 0 # macro
|
|
MMHUB_BASE__INST2_SEG4 = 0 # macro
|
|
MMHUB_BASE__INST3_SEG0 = 0 # macro
|
|
MMHUB_BASE__INST3_SEG1 = 0 # macro
|
|
MMHUB_BASE__INST3_SEG2 = 0 # macro
|
|
MMHUB_BASE__INST3_SEG3 = 0 # macro
|
|
MMHUB_BASE__INST3_SEG4 = 0 # macro
|
|
MMHUB_BASE__INST4_SEG0 = 0 # macro
|
|
MMHUB_BASE__INST4_SEG1 = 0 # macro
|
|
MMHUB_BASE__INST4_SEG2 = 0 # macro
|
|
MMHUB_BASE__INST4_SEG3 = 0 # macro
|
|
MMHUB_BASE__INST4_SEG4 = 0 # macro
|
|
MMHUB_BASE__INST5_SEG0 = 0 # macro
|
|
MMHUB_BASE__INST5_SEG1 = 0 # macro
|
|
MMHUB_BASE__INST5_SEG2 = 0 # macro
|
|
MMHUB_BASE__INST5_SEG3 = 0 # macro
|
|
MMHUB_BASE__INST5_SEG4 = 0 # macro
|
|
MMHUB_BASE__INST6_SEG0 = 0 # macro
|
|
MMHUB_BASE__INST6_SEG1 = 0 # macro
|
|
MMHUB_BASE__INST6_SEG2 = 0 # macro
|
|
MMHUB_BASE__INST6_SEG3 = 0 # macro
|
|
MMHUB_BASE__INST6_SEG4 = 0 # macro
|
|
MP0_BASE__INST0_SEG0 = 0x00016000 # macro
|
|
MP0_BASE__INST0_SEG1 = 0x00DC0000 # macro
|
|
MP0_BASE__INST0_SEG2 = 0x00E00000 # macro
|
|
MP0_BASE__INST0_SEG3 = 0x00E40000 # macro
|
|
MP0_BASE__INST0_SEG4 = 0x0243FC00 # macro
|
|
MP0_BASE__INST1_SEG0 = 0 # macro
|
|
MP0_BASE__INST1_SEG1 = 0 # macro
|
|
MP0_BASE__INST1_SEG2 = 0 # macro
|
|
MP0_BASE__INST1_SEG3 = 0 # macro
|
|
MP0_BASE__INST1_SEG4 = 0 # macro
|
|
MP0_BASE__INST2_SEG0 = 0 # macro
|
|
MP0_BASE__INST2_SEG1 = 0 # macro
|
|
MP0_BASE__INST2_SEG2 = 0 # macro
|
|
MP0_BASE__INST2_SEG3 = 0 # macro
|
|
MP0_BASE__INST2_SEG4 = 0 # macro
|
|
MP0_BASE__INST3_SEG0 = 0 # macro
|
|
MP0_BASE__INST3_SEG1 = 0 # macro
|
|
MP0_BASE__INST3_SEG2 = 0 # macro
|
|
MP0_BASE__INST3_SEG3 = 0 # macro
|
|
MP0_BASE__INST3_SEG4 = 0 # macro
|
|
MP0_BASE__INST4_SEG0 = 0 # macro
|
|
MP0_BASE__INST4_SEG1 = 0 # macro
|
|
MP0_BASE__INST4_SEG2 = 0 # macro
|
|
MP0_BASE__INST4_SEG3 = 0 # macro
|
|
MP0_BASE__INST4_SEG4 = 0 # macro
|
|
MP0_BASE__INST5_SEG0 = 0 # macro
|
|
MP0_BASE__INST5_SEG1 = 0 # macro
|
|
MP0_BASE__INST5_SEG2 = 0 # macro
|
|
MP0_BASE__INST5_SEG3 = 0 # macro
|
|
MP0_BASE__INST5_SEG4 = 0 # macro
|
|
MP0_BASE__INST6_SEG0 = 0 # macro
|
|
MP0_BASE__INST6_SEG1 = 0 # macro
|
|
MP0_BASE__INST6_SEG2 = 0 # macro
|
|
MP0_BASE__INST6_SEG3 = 0 # macro
|
|
MP0_BASE__INST6_SEG4 = 0 # macro
|
|
MP1_BASE__INST0_SEG0 = 0x00016000 # macro
|
|
MP1_BASE__INST0_SEG1 = 0x00DC0000 # macro
|
|
MP1_BASE__INST0_SEG2 = 0x00E00000 # macro
|
|
MP1_BASE__INST0_SEG3 = 0x00E40000 # macro
|
|
MP1_BASE__INST0_SEG4 = 0x0243FC00 # macro
|
|
MP1_BASE__INST1_SEG0 = 0 # macro
|
|
MP1_BASE__INST1_SEG1 = 0 # macro
|
|
MP1_BASE__INST1_SEG2 = 0 # macro
|
|
MP1_BASE__INST1_SEG3 = 0 # macro
|
|
MP1_BASE__INST1_SEG4 = 0 # macro
|
|
MP1_BASE__INST2_SEG0 = 0 # macro
|
|
MP1_BASE__INST2_SEG1 = 0 # macro
|
|
MP1_BASE__INST2_SEG2 = 0 # macro
|
|
MP1_BASE__INST2_SEG3 = 0 # macro
|
|
MP1_BASE__INST2_SEG4 = 0 # macro
|
|
MP1_BASE__INST3_SEG0 = 0 # macro
|
|
MP1_BASE__INST3_SEG1 = 0 # macro
|
|
MP1_BASE__INST3_SEG2 = 0 # macro
|
|
MP1_BASE__INST3_SEG3 = 0 # macro
|
|
MP1_BASE__INST3_SEG4 = 0 # macro
|
|
MP1_BASE__INST4_SEG0 = 0 # macro
|
|
MP1_BASE__INST4_SEG1 = 0 # macro
|
|
MP1_BASE__INST4_SEG2 = 0 # macro
|
|
MP1_BASE__INST4_SEG3 = 0 # macro
|
|
MP1_BASE__INST4_SEG4 = 0 # macro
|
|
MP1_BASE__INST5_SEG0 = 0 # macro
|
|
MP1_BASE__INST5_SEG1 = 0 # macro
|
|
MP1_BASE__INST5_SEG2 = 0 # macro
|
|
MP1_BASE__INST5_SEG3 = 0 # macro
|
|
MP1_BASE__INST5_SEG4 = 0 # macro
|
|
MP1_BASE__INST6_SEG0 = 0 # macro
|
|
MP1_BASE__INST6_SEG1 = 0 # macro
|
|
MP1_BASE__INST6_SEG2 = 0 # macro
|
|
MP1_BASE__INST6_SEG3 = 0 # macro
|
|
MP1_BASE__INST6_SEG4 = 0 # macro
|
|
NBIO_BASE__INST0_SEG0 = 0x00000000 # macro
|
|
NBIO_BASE__INST0_SEG1 = 0x00000014 # macro
|
|
NBIO_BASE__INST0_SEG2 = 0x00000D20 # macro
|
|
NBIO_BASE__INST0_SEG3 = 0x00010400 # macro
|
|
NBIO_BASE__INST0_SEG4 = 0x0241B000 # macro
|
|
NBIO_BASE__INST1_SEG0 = 0 # macro
|
|
NBIO_BASE__INST1_SEG1 = 0 # macro
|
|
NBIO_BASE__INST1_SEG2 = 0 # macro
|
|
NBIO_BASE__INST1_SEG3 = 0 # macro
|
|
NBIO_BASE__INST1_SEG4 = 0 # macro
|
|
NBIO_BASE__INST2_SEG0 = 0 # macro
|
|
NBIO_BASE__INST2_SEG1 = 0 # macro
|
|
NBIO_BASE__INST2_SEG2 = 0 # macro
|
|
NBIO_BASE__INST2_SEG3 = 0 # macro
|
|
NBIO_BASE__INST2_SEG4 = 0 # macro
|
|
NBIO_BASE__INST3_SEG0 = 0 # macro
|
|
NBIO_BASE__INST3_SEG1 = 0 # macro
|
|
NBIO_BASE__INST3_SEG2 = 0 # macro
|
|
NBIO_BASE__INST3_SEG3 = 0 # macro
|
|
NBIO_BASE__INST3_SEG4 = 0 # macro
|
|
NBIO_BASE__INST4_SEG0 = 0 # macro
|
|
NBIO_BASE__INST4_SEG1 = 0 # macro
|
|
NBIO_BASE__INST4_SEG2 = 0 # macro
|
|
NBIO_BASE__INST4_SEG3 = 0 # macro
|
|
NBIO_BASE__INST4_SEG4 = 0 # macro
|
|
NBIO_BASE__INST5_SEG0 = 0 # macro
|
|
NBIO_BASE__INST5_SEG1 = 0 # macro
|
|
NBIO_BASE__INST5_SEG2 = 0 # macro
|
|
NBIO_BASE__INST5_SEG3 = 0 # macro
|
|
NBIO_BASE__INST5_SEG4 = 0 # macro
|
|
NBIO_BASE__INST6_SEG0 = 0 # macro
|
|
NBIO_BASE__INST6_SEG1 = 0 # macro
|
|
NBIO_BASE__INST6_SEG2 = 0 # macro
|
|
NBIO_BASE__INST6_SEG3 = 0 # macro
|
|
NBIO_BASE__INST6_SEG4 = 0 # macro
|
|
OSSSYS_BASE__INST0_SEG0 = 0x000010A0 # macro
|
|
OSSSYS_BASE__INST0_SEG1 = 0x0240A000 # macro
|
|
OSSSYS_BASE__INST0_SEG2 = 0 # macro
|
|
OSSSYS_BASE__INST0_SEG3 = 0 # macro
|
|
OSSSYS_BASE__INST0_SEG4 = 0 # macro
|
|
OSSSYS_BASE__INST1_SEG0 = 0 # macro
|
|
OSSSYS_BASE__INST1_SEG1 = 0 # macro
|
|
OSSSYS_BASE__INST1_SEG2 = 0 # macro
|
|
OSSSYS_BASE__INST1_SEG3 = 0 # macro
|
|
OSSSYS_BASE__INST1_SEG4 = 0 # macro
|
|
OSSSYS_BASE__INST2_SEG0 = 0 # macro
|
|
OSSSYS_BASE__INST2_SEG1 = 0 # macro
|
|
OSSSYS_BASE__INST2_SEG2 = 0 # macro
|
|
OSSSYS_BASE__INST2_SEG3 = 0 # macro
|
|
OSSSYS_BASE__INST2_SEG4 = 0 # macro
|
|
OSSSYS_BASE__INST3_SEG0 = 0 # macro
|
|
OSSSYS_BASE__INST3_SEG1 = 0 # macro
|
|
OSSSYS_BASE__INST3_SEG2 = 0 # macro
|
|
OSSSYS_BASE__INST3_SEG3 = 0 # macro
|
|
OSSSYS_BASE__INST3_SEG4 = 0 # macro
|
|
OSSSYS_BASE__INST4_SEG0 = 0 # macro
|
|
OSSSYS_BASE__INST4_SEG1 = 0 # macro
|
|
OSSSYS_BASE__INST4_SEG2 = 0 # macro
|
|
OSSSYS_BASE__INST4_SEG3 = 0 # macro
|
|
OSSSYS_BASE__INST4_SEG4 = 0 # macro
|
|
OSSSYS_BASE__INST5_SEG0 = 0 # macro
|
|
OSSSYS_BASE__INST5_SEG1 = 0 # macro
|
|
OSSSYS_BASE__INST5_SEG2 = 0 # macro
|
|
OSSSYS_BASE__INST5_SEG3 = 0 # macro
|
|
OSSSYS_BASE__INST5_SEG4 = 0 # macro
|
|
OSSSYS_BASE__INST6_SEG0 = 0 # macro
|
|
OSSSYS_BASE__INST6_SEG1 = 0 # macro
|
|
OSSSYS_BASE__INST6_SEG2 = 0 # macro
|
|
OSSSYS_BASE__INST6_SEG3 = 0 # macro
|
|
OSSSYS_BASE__INST6_SEG4 = 0 # macro
|
|
PCIE0_BASE__INST0_SEG0 = 0x00000000 # macro
|
|
PCIE0_BASE__INST0_SEG1 = 0x00000014 # macro
|
|
PCIE0_BASE__INST0_SEG2 = 0x00000D20 # macro
|
|
PCIE0_BASE__INST0_SEG3 = 0x00010400 # macro
|
|
PCIE0_BASE__INST0_SEG4 = 0x0241B000 # macro
|
|
PCIE0_BASE__INST1_SEG0 = 0 # macro
|
|
PCIE0_BASE__INST1_SEG1 = 0 # macro
|
|
PCIE0_BASE__INST1_SEG2 = 0 # macro
|
|
PCIE0_BASE__INST1_SEG3 = 0 # macro
|
|
PCIE0_BASE__INST1_SEG4 = 0 # macro
|
|
PCIE0_BASE__INST2_SEG0 = 0 # macro
|
|
PCIE0_BASE__INST2_SEG1 = 0 # macro
|
|
PCIE0_BASE__INST2_SEG2 = 0 # macro
|
|
PCIE0_BASE__INST2_SEG3 = 0 # macro
|
|
PCIE0_BASE__INST2_SEG4 = 0 # macro
|
|
PCIE0_BASE__INST3_SEG0 = 0 # macro
|
|
PCIE0_BASE__INST3_SEG1 = 0 # macro
|
|
PCIE0_BASE__INST3_SEG2 = 0 # macro
|
|
PCIE0_BASE__INST3_SEG3 = 0 # macro
|
|
PCIE0_BASE__INST3_SEG4 = 0 # macro
|
|
PCIE0_BASE__INST4_SEG0 = 0 # macro
|
|
PCIE0_BASE__INST4_SEG1 = 0 # macro
|
|
PCIE0_BASE__INST4_SEG2 = 0 # macro
|
|
PCIE0_BASE__INST4_SEG3 = 0 # macro
|
|
PCIE0_BASE__INST4_SEG4 = 0 # macro
|
|
PCIE0_BASE__INST5_SEG0 = 0 # macro
|
|
PCIE0_BASE__INST5_SEG1 = 0 # macro
|
|
PCIE0_BASE__INST5_SEG2 = 0 # macro
|
|
PCIE0_BASE__INST5_SEG3 = 0 # macro
|
|
PCIE0_BASE__INST5_SEG4 = 0 # macro
|
|
PCIE0_BASE__INST6_SEG0 = 0 # macro
|
|
PCIE0_BASE__INST6_SEG1 = 0 # macro
|
|
PCIE0_BASE__INST6_SEG2 = 0 # macro
|
|
PCIE0_BASE__INST6_SEG3 = 0 # macro
|
|
PCIE0_BASE__INST6_SEG4 = 0 # macro
|
|
SDMA0_BASE__INST0_SEG0 = 0x00001260 # macro
|
|
SDMA0_BASE__INST0_SEG1 = 0x0000A000 # macro
|
|
SDMA0_BASE__INST0_SEG2 = 0x0001C000 # macro
|
|
SDMA0_BASE__INST0_SEG3 = 0x02402C00 # macro
|
|
SDMA0_BASE__INST0_SEG4 = 0 # macro
|
|
SDMA0_BASE__INST1_SEG0 = 0 # macro
|
|
SDMA0_BASE__INST1_SEG1 = 0 # macro
|
|
SDMA0_BASE__INST1_SEG2 = 0 # macro
|
|
SDMA0_BASE__INST1_SEG3 = 0 # macro
|
|
SDMA0_BASE__INST1_SEG4 = 0 # macro
|
|
SDMA0_BASE__INST2_SEG0 = 0 # macro
|
|
SDMA0_BASE__INST2_SEG1 = 0 # macro
|
|
SDMA0_BASE__INST2_SEG2 = 0 # macro
|
|
SDMA0_BASE__INST2_SEG3 = 0 # macro
|
|
SDMA0_BASE__INST2_SEG4 = 0 # macro
|
|
SDMA0_BASE__INST3_SEG0 = 0 # macro
|
|
SDMA0_BASE__INST3_SEG1 = 0 # macro
|
|
SDMA0_BASE__INST3_SEG2 = 0 # macro
|
|
SDMA0_BASE__INST3_SEG3 = 0 # macro
|
|
SDMA0_BASE__INST3_SEG4 = 0 # macro
|
|
SDMA0_BASE__INST4_SEG0 = 0 # macro
|
|
SDMA0_BASE__INST4_SEG1 = 0 # macro
|
|
SDMA0_BASE__INST4_SEG2 = 0 # macro
|
|
SDMA0_BASE__INST4_SEG3 = 0 # macro
|
|
SDMA0_BASE__INST4_SEG4 = 0 # macro
|
|
SDMA0_BASE__INST5_SEG0 = 0 # macro
|
|
SDMA0_BASE__INST5_SEG1 = 0 # macro
|
|
SDMA0_BASE__INST5_SEG2 = 0 # macro
|
|
SDMA0_BASE__INST5_SEG3 = 0 # macro
|
|
SDMA0_BASE__INST5_SEG4 = 0 # macro
|
|
SDMA0_BASE__INST6_SEG0 = 0 # macro
|
|
SDMA0_BASE__INST6_SEG1 = 0 # macro
|
|
SDMA0_BASE__INST6_SEG2 = 0 # macro
|
|
SDMA0_BASE__INST6_SEG3 = 0 # macro
|
|
SDMA0_BASE__INST6_SEG4 = 0 # macro
|
|
SDMA1_BASE__INST0_SEG0 = 0x00001260 # macro
|
|
SDMA1_BASE__INST0_SEG1 = 0x0000A000 # macro
|
|
SDMA1_BASE__INST0_SEG2 = 0x0001C000 # macro
|
|
SDMA1_BASE__INST0_SEG3 = 0x02402C00 # macro
|
|
SDMA1_BASE__INST0_SEG4 = 0 # macro
|
|
SDMA1_BASE__INST1_SEG0 = 0 # macro
|
|
SDMA1_BASE__INST1_SEG1 = 0 # macro
|
|
SDMA1_BASE__INST1_SEG2 = 0 # macro
|
|
SDMA1_BASE__INST1_SEG3 = 0 # macro
|
|
SDMA1_BASE__INST1_SEG4 = 0 # macro
|
|
SDMA1_BASE__INST2_SEG0 = 0 # macro
|
|
SDMA1_BASE__INST2_SEG1 = 0 # macro
|
|
SDMA1_BASE__INST2_SEG2 = 0 # macro
|
|
SDMA1_BASE__INST2_SEG3 = 0 # macro
|
|
SDMA1_BASE__INST2_SEG4 = 0 # macro
|
|
SDMA1_BASE__INST3_SEG0 = 0 # macro
|
|
SDMA1_BASE__INST3_SEG1 = 0 # macro
|
|
SDMA1_BASE__INST3_SEG2 = 0 # macro
|
|
SDMA1_BASE__INST3_SEG3 = 0 # macro
|
|
SDMA1_BASE__INST3_SEG4 = 0 # macro
|
|
SDMA1_BASE__INST4_SEG0 = 0 # macro
|
|
SDMA1_BASE__INST4_SEG1 = 0 # macro
|
|
SDMA1_BASE__INST4_SEG2 = 0 # macro
|
|
SDMA1_BASE__INST4_SEG3 = 0 # macro
|
|
SDMA1_BASE__INST4_SEG4 = 0 # macro
|
|
SDMA1_BASE__INST5_SEG0 = 0 # macro
|
|
SDMA1_BASE__INST5_SEG1 = 0 # macro
|
|
SDMA1_BASE__INST5_SEG2 = 0 # macro
|
|
SDMA1_BASE__INST5_SEG3 = 0 # macro
|
|
SDMA1_BASE__INST5_SEG4 = 0 # macro
|
|
SDMA1_BASE__INST6_SEG0 = 0 # macro
|
|
SDMA1_BASE__INST6_SEG1 = 0 # macro
|
|
SDMA1_BASE__INST6_SEG2 = 0 # macro
|
|
SDMA1_BASE__INST6_SEG3 = 0 # macro
|
|
SDMA1_BASE__INST6_SEG4 = 0 # macro
|
|
SMUIO_BASE__INST0_SEG0 = 0x00016800 # macro
|
|
SMUIO_BASE__INST0_SEG1 = 0x00016A00 # macro
|
|
SMUIO_BASE__INST0_SEG2 = 0x00440000 # macro
|
|
SMUIO_BASE__INST0_SEG3 = 0x02401000 # macro
|
|
SMUIO_BASE__INST0_SEG4 = 0 # macro
|
|
SMUIO_BASE__INST1_SEG0 = 0 # macro
|
|
SMUIO_BASE__INST1_SEG1 = 0 # macro
|
|
SMUIO_BASE__INST1_SEG2 = 0 # macro
|
|
SMUIO_BASE__INST1_SEG3 = 0 # macro
|
|
SMUIO_BASE__INST1_SEG4 = 0 # macro
|
|
SMUIO_BASE__INST2_SEG0 = 0 # macro
|
|
SMUIO_BASE__INST2_SEG1 = 0 # macro
|
|
SMUIO_BASE__INST2_SEG2 = 0 # macro
|
|
SMUIO_BASE__INST2_SEG3 = 0 # macro
|
|
SMUIO_BASE__INST2_SEG4 = 0 # macro
|
|
SMUIO_BASE__INST3_SEG0 = 0 # macro
|
|
SMUIO_BASE__INST3_SEG1 = 0 # macro
|
|
SMUIO_BASE__INST3_SEG2 = 0 # macro
|
|
SMUIO_BASE__INST3_SEG3 = 0 # macro
|
|
SMUIO_BASE__INST3_SEG4 = 0 # macro
|
|
SMUIO_BASE__INST4_SEG0 = 0 # macro
|
|
SMUIO_BASE__INST4_SEG1 = 0 # macro
|
|
SMUIO_BASE__INST4_SEG2 = 0 # macro
|
|
SMUIO_BASE__INST4_SEG3 = 0 # macro
|
|
SMUIO_BASE__INST4_SEG4 = 0 # macro
|
|
SMUIO_BASE__INST5_SEG0 = 0 # macro
|
|
SMUIO_BASE__INST5_SEG1 = 0 # macro
|
|
SMUIO_BASE__INST5_SEG2 = 0 # macro
|
|
SMUIO_BASE__INST5_SEG3 = 0 # macro
|
|
SMUIO_BASE__INST5_SEG4 = 0 # macro
|
|
SMUIO_BASE__INST6_SEG0 = 0 # macro
|
|
SMUIO_BASE__INST6_SEG1 = 0 # macro
|
|
SMUIO_BASE__INST6_SEG2 = 0 # macro
|
|
SMUIO_BASE__INST6_SEG3 = 0 # macro
|
|
SMUIO_BASE__INST6_SEG4 = 0 # macro
|
|
THM_BASE__INST0_SEG0 = 0x00016600 # macro
|
|
THM_BASE__INST0_SEG1 = 0x02400C00 # macro
|
|
THM_BASE__INST0_SEG2 = 0 # macro
|
|
THM_BASE__INST0_SEG3 = 0 # macro
|
|
THM_BASE__INST0_SEG4 = 0 # macro
|
|
THM_BASE__INST1_SEG0 = 0 # macro
|
|
THM_BASE__INST1_SEG1 = 0 # macro
|
|
THM_BASE__INST1_SEG2 = 0 # macro
|
|
THM_BASE__INST1_SEG3 = 0 # macro
|
|
THM_BASE__INST1_SEG4 = 0 # macro
|
|
THM_BASE__INST2_SEG0 = 0 # macro
|
|
THM_BASE__INST2_SEG1 = 0 # macro
|
|
THM_BASE__INST2_SEG2 = 0 # macro
|
|
THM_BASE__INST2_SEG3 = 0 # macro
|
|
THM_BASE__INST2_SEG4 = 0 # macro
|
|
THM_BASE__INST3_SEG0 = 0 # macro
|
|
THM_BASE__INST3_SEG1 = 0 # macro
|
|
THM_BASE__INST3_SEG2 = 0 # macro
|
|
THM_BASE__INST3_SEG3 = 0 # macro
|
|
THM_BASE__INST3_SEG4 = 0 # macro
|
|
THM_BASE__INST4_SEG0 = 0 # macro
|
|
THM_BASE__INST4_SEG1 = 0 # macro
|
|
THM_BASE__INST4_SEG2 = 0 # macro
|
|
THM_BASE__INST4_SEG3 = 0 # macro
|
|
THM_BASE__INST4_SEG4 = 0 # macro
|
|
THM_BASE__INST5_SEG0 = 0 # macro
|
|
THM_BASE__INST5_SEG1 = 0 # macro
|
|
THM_BASE__INST5_SEG2 = 0 # macro
|
|
THM_BASE__INST5_SEG3 = 0 # macro
|
|
THM_BASE__INST5_SEG4 = 0 # macro
|
|
THM_BASE__INST6_SEG0 = 0 # macro
|
|
THM_BASE__INST6_SEG1 = 0 # macro
|
|
THM_BASE__INST6_SEG2 = 0 # macro
|
|
THM_BASE__INST6_SEG3 = 0 # macro
|
|
THM_BASE__INST6_SEG4 = 0 # macro
|
|
UMC_BASE__INST0_SEG0 = 0x00014000 # macro
|
|
UMC_BASE__INST0_SEG1 = 0x02425800 # macro
|
|
UMC_BASE__INST0_SEG2 = 0 # macro
|
|
UMC_BASE__INST0_SEG3 = 0 # macro
|
|
UMC_BASE__INST0_SEG4 = 0 # macro
|
|
UMC_BASE__INST1_SEG0 = 0x00054000 # macro
|
|
UMC_BASE__INST1_SEG1 = 0x02425C00 # macro
|
|
UMC_BASE__INST1_SEG2 = 0 # macro
|
|
UMC_BASE__INST1_SEG3 = 0 # macro
|
|
UMC_BASE__INST1_SEG4 = 0 # macro
|
|
UMC_BASE__INST2_SEG0 = 0x00094000 # macro
|
|
UMC_BASE__INST2_SEG1 = 0x02426000 # macro
|
|
UMC_BASE__INST2_SEG2 = 0 # macro
|
|
UMC_BASE__INST2_SEG3 = 0 # macro
|
|
UMC_BASE__INST2_SEG4 = 0 # macro
|
|
UMC_BASE__INST3_SEG0 = 0x000D4000 # macro
|
|
UMC_BASE__INST3_SEG1 = 0x02426400 # macro
|
|
UMC_BASE__INST3_SEG2 = 0 # macro
|
|
UMC_BASE__INST3_SEG3 = 0 # macro
|
|
UMC_BASE__INST3_SEG4 = 0 # macro
|
|
UMC_BASE__INST4_SEG0 = 0x00114000 # macro
|
|
UMC_BASE__INST4_SEG1 = 0x02426800 # macro
|
|
UMC_BASE__INST4_SEG2 = 0 # macro
|
|
UMC_BASE__INST4_SEG3 = 0 # macro
|
|
UMC_BASE__INST4_SEG4 = 0 # macro
|
|
UMC_BASE__INST5_SEG0 = 0x00154000 # macro
|
|
UMC_BASE__INST5_SEG1 = 0x02426C00 # macro
|
|
UMC_BASE__INST5_SEG2 = 0 # macro
|
|
UMC_BASE__INST5_SEG3 = 0 # macro
|
|
UMC_BASE__INST5_SEG4 = 0 # macro
|
|
UMC_BASE__INST6_SEG0 = 0x00194000 # macro
|
|
UMC_BASE__INST6_SEG1 = 0x02427000 # macro
|
|
UMC_BASE__INST6_SEG2 = 0 # macro
|
|
UMC_BASE__INST6_SEG3 = 0 # macro
|
|
UMC_BASE__INST6_SEG4 = 0 # macro
|
|
USB0_BASE__INST0_SEG0 = 0x0242A800 # macro
|
|
USB0_BASE__INST0_SEG1 = 0x05B00000 # macro
|
|
USB0_BASE__INST0_SEG2 = 0 # macro
|
|
USB0_BASE__INST0_SEG3 = 0 # macro
|
|
USB0_BASE__INST0_SEG4 = 0 # macro
|
|
USB0_BASE__INST1_SEG0 = 0 # macro
|
|
USB0_BASE__INST1_SEG1 = 0 # macro
|
|
USB0_BASE__INST1_SEG2 = 0 # macro
|
|
USB0_BASE__INST1_SEG3 = 0 # macro
|
|
USB0_BASE__INST1_SEG4 = 0 # macro
|
|
USB0_BASE__INST2_SEG0 = 0 # macro
|
|
USB0_BASE__INST2_SEG1 = 0 # macro
|
|
USB0_BASE__INST2_SEG2 = 0 # macro
|
|
USB0_BASE__INST2_SEG3 = 0 # macro
|
|
USB0_BASE__INST2_SEG4 = 0 # macro
|
|
USB0_BASE__INST3_SEG0 = 0 # macro
|
|
USB0_BASE__INST3_SEG1 = 0 # macro
|
|
USB0_BASE__INST3_SEG2 = 0 # macro
|
|
USB0_BASE__INST3_SEG3 = 0 # macro
|
|
USB0_BASE__INST3_SEG4 = 0 # macro
|
|
USB0_BASE__INST4_SEG0 = 0 # macro
|
|
USB0_BASE__INST4_SEG1 = 0 # macro
|
|
USB0_BASE__INST4_SEG2 = 0 # macro
|
|
USB0_BASE__INST4_SEG3 = 0 # macro
|
|
USB0_BASE__INST4_SEG4 = 0 # macro
|
|
USB0_BASE__INST5_SEG0 = 0 # macro
|
|
USB0_BASE__INST5_SEG1 = 0 # macro
|
|
USB0_BASE__INST5_SEG2 = 0 # macro
|
|
USB0_BASE__INST5_SEG3 = 0 # macro
|
|
USB0_BASE__INST5_SEG4 = 0 # macro
|
|
USB0_BASE__INST6_SEG0 = 0 # macro
|
|
USB0_BASE__INST6_SEG1 = 0 # macro
|
|
USB0_BASE__INST6_SEG2 = 0 # macro
|
|
USB0_BASE__INST6_SEG3 = 0 # macro
|
|
USB0_BASE__INST6_SEG4 = 0 # macro
|
|
VCN_BASE__INST0_SEG0 = 0x00007800 # macro
|
|
VCN_BASE__INST0_SEG1 = 0x00007E00 # macro
|
|
VCN_BASE__INST0_SEG2 = 0x02403000 # macro
|
|
VCN_BASE__INST0_SEG3 = 0 # macro
|
|
VCN_BASE__INST0_SEG4 = 0 # macro
|
|
VCN_BASE__INST1_SEG0 = 0x00007B00 # macro
|
|
VCN_BASE__INST1_SEG1 = 0x00012000 # macro
|
|
VCN_BASE__INST1_SEG2 = 0x02445000 # macro
|
|
VCN_BASE__INST1_SEG3 = 0 # macro
|
|
VCN_BASE__INST1_SEG4 = 0 # macro
|
|
VCN_BASE__INST2_SEG0 = 0 # macro
|
|
VCN_BASE__INST2_SEG1 = 0 # macro
|
|
VCN_BASE__INST2_SEG2 = 0 # macro
|
|
VCN_BASE__INST2_SEG3 = 0 # macro
|
|
VCN_BASE__INST2_SEG4 = 0 # macro
|
|
VCN_BASE__INST3_SEG0 = 0 # macro
|
|
VCN_BASE__INST3_SEG1 = 0 # macro
|
|
VCN_BASE__INST3_SEG2 = 0 # macro
|
|
VCN_BASE__INST3_SEG3 = 0 # macro
|
|
VCN_BASE__INST3_SEG4 = 0 # macro
|
|
VCN_BASE__INST4_SEG0 = 0 # macro
|
|
VCN_BASE__INST4_SEG1 = 0 # macro
|
|
VCN_BASE__INST4_SEG2 = 0 # macro
|
|
VCN_BASE__INST4_SEG3 = 0 # macro
|
|
VCN_BASE__INST4_SEG4 = 0 # macro
|
|
VCN_BASE__INST5_SEG0 = 0 # macro
|
|
VCN_BASE__INST5_SEG1 = 0 # macro
|
|
VCN_BASE__INST5_SEG2 = 0 # macro
|
|
VCN_BASE__INST5_SEG3 = 0 # macro
|
|
VCN_BASE__INST5_SEG4 = 0 # macro
|
|
VCN_BASE__INST6_SEG0 = 0 # macro
|
|
VCN_BASE__INST6_SEG1 = 0 # macro
|
|
VCN_BASE__INST6_SEG2 = 0 # macro
|
|
VCN_BASE__INST6_SEG3 = 0 # macro
|
|
VCN_BASE__INST6_SEG4 = 0 # macro
|
|
class struct_IP_BASE_INSTANCE(Structure):
|
|
pass
|
|
|
|
struct_IP_BASE_INSTANCE._pack_ = 1 # source:False
|
|
struct_IP_BASE_INSTANCE._fields_ = [
|
|
('segment', ctypes.c_uint32 * 5),
|
|
]
|
|
|
|
class struct_IP_BASE(Structure):
|
|
_pack_ = 1 # source:False
|
|
_fields_ = [
|
|
('instance', struct_IP_BASE_INSTANCE * 7),
|
|
]
|
|
|
|
__maybe_unused = struct_IP_BASE # Variable struct_IP_BASE
|
|
ATHUB_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
CLK_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
DF_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
DIO_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
DCN_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
DPCS_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
FUSE_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
GC_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
HDA_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
HDP_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
MMHUB_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
MP0_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
MP1_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
NBIO_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
OSSSYS_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
PCIE0_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
SDMA0_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
SDMA1_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
SMUIO_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
THM_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
UMC_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
USB0_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
VCN_BASE = struct_IP_BASE # Variable struct_IP_BASE
|
|
__all__ = \
|
|
['ATHUB_BASE', 'ATHUB_BASE__INST0_SEG0', 'ATHUB_BASE__INST0_SEG1',
|
|
'ATHUB_BASE__INST0_SEG2', 'ATHUB_BASE__INST0_SEG3',
|
|
'ATHUB_BASE__INST0_SEG4', 'ATHUB_BASE__INST1_SEG0',
|
|
'ATHUB_BASE__INST1_SEG1', 'ATHUB_BASE__INST1_SEG2',
|
|
'ATHUB_BASE__INST1_SEG3', 'ATHUB_BASE__INST1_SEG4',
|
|
'ATHUB_BASE__INST2_SEG0', 'ATHUB_BASE__INST2_SEG1',
|
|
'ATHUB_BASE__INST2_SEG2', 'ATHUB_BASE__INST2_SEG3',
|
|
'ATHUB_BASE__INST2_SEG4', 'ATHUB_BASE__INST3_SEG0',
|
|
'ATHUB_BASE__INST3_SEG1', 'ATHUB_BASE__INST3_SEG2',
|
|
'ATHUB_BASE__INST3_SEG3', 'ATHUB_BASE__INST3_SEG4',
|
|
'ATHUB_BASE__INST4_SEG0', 'ATHUB_BASE__INST4_SEG1',
|
|
'ATHUB_BASE__INST4_SEG2', 'ATHUB_BASE__INST4_SEG3',
|
|
'ATHUB_BASE__INST4_SEG4', 'ATHUB_BASE__INST5_SEG0',
|
|
'ATHUB_BASE__INST5_SEG1', 'ATHUB_BASE__INST5_SEG2',
|
|
'ATHUB_BASE__INST5_SEG3', 'ATHUB_BASE__INST5_SEG4',
|
|
'ATHUB_BASE__INST6_SEG0', 'ATHUB_BASE__INST6_SEG1',
|
|
'ATHUB_BASE__INST6_SEG2', 'ATHUB_BASE__INST6_SEG3',
|
|
'ATHUB_BASE__INST6_SEG4', 'CE_PARTITION_BASE', 'CLK_BASE',
|
|
'CLK_BASE__INST0_SEG0', 'CLK_BASE__INST0_SEG1',
|
|
'CLK_BASE__INST0_SEG2', 'CLK_BASE__INST0_SEG3',
|
|
'CLK_BASE__INST0_SEG4', 'CLK_BASE__INST1_SEG0',
|
|
'CLK_BASE__INST1_SEG1', 'CLK_BASE__INST1_SEG2',
|
|
'CLK_BASE__INST1_SEG3', 'CLK_BASE__INST1_SEG4',
|
|
'CLK_BASE__INST2_SEG0', 'CLK_BASE__INST2_SEG1',
|
|
'CLK_BASE__INST2_SEG2', 'CLK_BASE__INST2_SEG3',
|
|
'CLK_BASE__INST2_SEG4', 'CLK_BASE__INST3_SEG0',
|
|
'CLK_BASE__INST3_SEG1', 'CLK_BASE__INST3_SEG2',
|
|
'CLK_BASE__INST3_SEG3', 'CLK_BASE__INST3_SEG4',
|
|
'CLK_BASE__INST4_SEG0', 'CLK_BASE__INST4_SEG1',
|
|
'CLK_BASE__INST4_SEG2', 'CLK_BASE__INST4_SEG3',
|
|
'CLK_BASE__INST4_SEG4', 'CLK_BASE__INST5_SEG0',
|
|
'CLK_BASE__INST5_SEG1', 'CLK_BASE__INST5_SEG2',
|
|
'CLK_BASE__INST5_SEG3', 'CLK_BASE__INST5_SEG4',
|
|
'CLK_BASE__INST6_SEG0', 'CLK_BASE__INST6_SEG1',
|
|
'CLK_BASE__INST6_SEG2', 'CLK_BASE__INST6_SEG3',
|
|
'CLK_BASE__INST6_SEG4', 'CP_PACKET2', 'DCN_BASE',
|
|
'DCN_BASE__INST0_SEG0', 'DCN_BASE__INST0_SEG1',
|
|
'DCN_BASE__INST0_SEG2', 'DCN_BASE__INST0_SEG3',
|
|
'DCN_BASE__INST0_SEG4', 'DCN_BASE__INST1_SEG0',
|
|
'DCN_BASE__INST1_SEG1', 'DCN_BASE__INST1_SEG2',
|
|
'DCN_BASE__INST1_SEG3', 'DCN_BASE__INST1_SEG4',
|
|
'DCN_BASE__INST2_SEG0', 'DCN_BASE__INST2_SEG1',
|
|
'DCN_BASE__INST2_SEG2', 'DCN_BASE__INST2_SEG3',
|
|
'DCN_BASE__INST2_SEG4', 'DCN_BASE__INST3_SEG0',
|
|
'DCN_BASE__INST3_SEG1', 'DCN_BASE__INST3_SEG2',
|
|
'DCN_BASE__INST3_SEG3', 'DCN_BASE__INST3_SEG4',
|
|
'DCN_BASE__INST4_SEG0', 'DCN_BASE__INST4_SEG1',
|
|
'DCN_BASE__INST4_SEG2', 'DCN_BASE__INST4_SEG3',
|
|
'DCN_BASE__INST4_SEG4', 'DCN_BASE__INST5_SEG0',
|
|
'DCN_BASE__INST5_SEG1', 'DCN_BASE__INST5_SEG2',
|
|
'DCN_BASE__INST5_SEG3', 'DCN_BASE__INST5_SEG4',
|
|
'DCN_BASE__INST6_SEG0', 'DCN_BASE__INST6_SEG1',
|
|
'DCN_BASE__INST6_SEG2', 'DCN_BASE__INST6_SEG3',
|
|
'DCN_BASE__INST6_SEG4', 'DF_BASE', 'DF_BASE__INST0_SEG0',
|
|
'DF_BASE__INST0_SEG1', 'DF_BASE__INST0_SEG2',
|
|
'DF_BASE__INST0_SEG3', 'DF_BASE__INST0_SEG4',
|
|
'DF_BASE__INST1_SEG0', 'DF_BASE__INST1_SEG1',
|
|
'DF_BASE__INST1_SEG2', 'DF_BASE__INST1_SEG3',
|
|
'DF_BASE__INST1_SEG4', 'DF_BASE__INST2_SEG0',
|
|
'DF_BASE__INST2_SEG1', 'DF_BASE__INST2_SEG2',
|
|
'DF_BASE__INST2_SEG3', 'DF_BASE__INST2_SEG4',
|
|
'DF_BASE__INST3_SEG0', 'DF_BASE__INST3_SEG1',
|
|
'DF_BASE__INST3_SEG2', 'DF_BASE__INST3_SEG3',
|
|
'DF_BASE__INST3_SEG4', 'DF_BASE__INST4_SEG0',
|
|
'DF_BASE__INST4_SEG1', 'DF_BASE__INST4_SEG2',
|
|
'DF_BASE__INST4_SEG3', 'DF_BASE__INST4_SEG4',
|
|
'DF_BASE__INST5_SEG0', 'DF_BASE__INST5_SEG1',
|
|
'DF_BASE__INST5_SEG2', 'DF_BASE__INST5_SEG3',
|
|
'DF_BASE__INST5_SEG4', 'DF_BASE__INST6_SEG0',
|
|
'DF_BASE__INST6_SEG1', 'DF_BASE__INST6_SEG2',
|
|
'DF_BASE__INST6_SEG3', 'DF_BASE__INST6_SEG4', 'DIO_BASE',
|
|
'DIO_BASE__INST0_SEG0', 'DIO_BASE__INST0_SEG1',
|
|
'DIO_BASE__INST0_SEG2', 'DIO_BASE__INST0_SEG3',
|
|
'DIO_BASE__INST0_SEG4', 'DIO_BASE__INST1_SEG0',
|
|
'DIO_BASE__INST1_SEG1', 'DIO_BASE__INST1_SEG2',
|
|
'DIO_BASE__INST1_SEG3', 'DIO_BASE__INST1_SEG4',
|
|
'DIO_BASE__INST2_SEG0', 'DIO_BASE__INST2_SEG1',
|
|
'DIO_BASE__INST2_SEG2', 'DIO_BASE__INST2_SEG3',
|
|
'DIO_BASE__INST2_SEG4', 'DIO_BASE__INST3_SEG0',
|
|
'DIO_BASE__INST3_SEG1', 'DIO_BASE__INST3_SEG2',
|
|
'DIO_BASE__INST3_SEG3', 'DIO_BASE__INST3_SEG4',
|
|
'DIO_BASE__INST4_SEG0', 'DIO_BASE__INST4_SEG1',
|
|
'DIO_BASE__INST4_SEG2', 'DIO_BASE__INST4_SEG3',
|
|
'DIO_BASE__INST4_SEG4', 'DIO_BASE__INST5_SEG0',
|
|
'DIO_BASE__INST5_SEG1', 'DIO_BASE__INST5_SEG2',
|
|
'DIO_BASE__INST5_SEG3', 'DIO_BASE__INST5_SEG4',
|
|
'DIO_BASE__INST6_SEG0', 'DIO_BASE__INST6_SEG1',
|
|
'DIO_BASE__INST6_SEG2', 'DIO_BASE__INST6_SEG3',
|
|
'DIO_BASE__INST6_SEG4', 'DPCS_BASE', 'DPCS_BASE__INST0_SEG0',
|
|
'DPCS_BASE__INST0_SEG1', 'DPCS_BASE__INST0_SEG2',
|
|
'DPCS_BASE__INST0_SEG3', 'DPCS_BASE__INST0_SEG4',
|
|
'DPCS_BASE__INST1_SEG0', 'DPCS_BASE__INST1_SEG1',
|
|
'DPCS_BASE__INST1_SEG2', 'DPCS_BASE__INST1_SEG3',
|
|
'DPCS_BASE__INST1_SEG4', 'DPCS_BASE__INST2_SEG0',
|
|
'DPCS_BASE__INST2_SEG1', 'DPCS_BASE__INST2_SEG2',
|
|
'DPCS_BASE__INST2_SEG3', 'DPCS_BASE__INST2_SEG4',
|
|
'DPCS_BASE__INST3_SEG0', 'DPCS_BASE__INST3_SEG1',
|
|
'DPCS_BASE__INST3_SEG2', 'DPCS_BASE__INST3_SEG3',
|
|
'DPCS_BASE__INST3_SEG4', 'DPCS_BASE__INST4_SEG0',
|
|
'DPCS_BASE__INST4_SEG1', 'DPCS_BASE__INST4_SEG2',
|
|
'DPCS_BASE__INST4_SEG3', 'DPCS_BASE__INST4_SEG4',
|
|
'DPCS_BASE__INST5_SEG0', 'DPCS_BASE__INST5_SEG1',
|
|
'DPCS_BASE__INST5_SEG2', 'DPCS_BASE__INST5_SEG3',
|
|
'DPCS_BASE__INST5_SEG4', 'DPCS_BASE__INST6_SEG0',
|
|
'DPCS_BASE__INST6_SEG1', 'DPCS_BASE__INST6_SEG2',
|
|
'DPCS_BASE__INST6_SEG3', 'DPCS_BASE__INST6_SEG4', 'FRAME_TMZ',
|
|
'FUSE_BASE', 'FUSE_BASE__INST0_SEG0', 'FUSE_BASE__INST0_SEG1',
|
|
'FUSE_BASE__INST0_SEG2', 'FUSE_BASE__INST0_SEG3',
|
|
'FUSE_BASE__INST0_SEG4', 'FUSE_BASE__INST1_SEG0',
|
|
'FUSE_BASE__INST1_SEG1', 'FUSE_BASE__INST1_SEG2',
|
|
'FUSE_BASE__INST1_SEG3', 'FUSE_BASE__INST1_SEG4',
|
|
'FUSE_BASE__INST2_SEG0', 'FUSE_BASE__INST2_SEG1',
|
|
'FUSE_BASE__INST2_SEG2', 'FUSE_BASE__INST2_SEG3',
|
|
'FUSE_BASE__INST2_SEG4', 'FUSE_BASE__INST3_SEG0',
|
|
'FUSE_BASE__INST3_SEG1', 'FUSE_BASE__INST3_SEG2',
|
|
'FUSE_BASE__INST3_SEG3', 'FUSE_BASE__INST3_SEG4',
|
|
'FUSE_BASE__INST4_SEG0', 'FUSE_BASE__INST4_SEG1',
|
|
'FUSE_BASE__INST4_SEG2', 'FUSE_BASE__INST4_SEG3',
|
|
'FUSE_BASE__INST4_SEG4', 'FUSE_BASE__INST5_SEG0',
|
|
'FUSE_BASE__INST5_SEG1', 'FUSE_BASE__INST5_SEG2',
|
|
'FUSE_BASE__INST5_SEG3', 'FUSE_BASE__INST5_SEG4',
|
|
'FUSE_BASE__INST6_SEG0', 'FUSE_BASE__INST6_SEG1',
|
|
'FUSE_BASE__INST6_SEG2', 'FUSE_BASE__INST6_SEG3',
|
|
'FUSE_BASE__INST6_SEG4', 'GC_BASE', 'GC_BASE__INST0_SEG0',
|
|
'GC_BASE__INST0_SEG1', 'GC_BASE__INST0_SEG2',
|
|
'GC_BASE__INST0_SEG3', 'GC_BASE__INST0_SEG4',
|
|
'GC_BASE__INST1_SEG0', 'GC_BASE__INST1_SEG1',
|
|
'GC_BASE__INST1_SEG2', 'GC_BASE__INST1_SEG3',
|
|
'GC_BASE__INST1_SEG4', 'GC_BASE__INST2_SEG0',
|
|
'GC_BASE__INST2_SEG1', 'GC_BASE__INST2_SEG2',
|
|
'GC_BASE__INST2_SEG3', 'GC_BASE__INST2_SEG4',
|
|
'GC_BASE__INST3_SEG0', 'GC_BASE__INST3_SEG1',
|
|
'GC_BASE__INST3_SEG2', 'GC_BASE__INST3_SEG3',
|
|
'GC_BASE__INST3_SEG4', 'GC_BASE__INST4_SEG0',
|
|
'GC_BASE__INST4_SEG1', 'GC_BASE__INST4_SEG2',
|
|
'GC_BASE__INST4_SEG3', 'GC_BASE__INST4_SEG4',
|
|
'GC_BASE__INST5_SEG0', 'GC_BASE__INST5_SEG1',
|
|
'GC_BASE__INST5_SEG2', 'GC_BASE__INST5_SEG3',
|
|
'GC_BASE__INST5_SEG4', 'GC_BASE__INST6_SEG0',
|
|
'GC_BASE__INST6_SEG1', 'GC_BASE__INST6_SEG2',
|
|
'GC_BASE__INST6_SEG3', 'GC_BASE__INST6_SEG4', 'HDA_BASE',
|
|
'HDA_BASE__INST0_SEG0', 'HDA_BASE__INST0_SEG1',
|
|
'HDA_BASE__INST0_SEG2', 'HDA_BASE__INST0_SEG3',
|
|
'HDA_BASE__INST0_SEG4', 'HDA_BASE__INST1_SEG0',
|
|
'HDA_BASE__INST1_SEG1', 'HDA_BASE__INST1_SEG2',
|
|
'HDA_BASE__INST1_SEG3', 'HDA_BASE__INST1_SEG4',
|
|
'HDA_BASE__INST2_SEG0', 'HDA_BASE__INST2_SEG1',
|
|
'HDA_BASE__INST2_SEG2', 'HDA_BASE__INST2_SEG3',
|
|
'HDA_BASE__INST2_SEG4', 'HDA_BASE__INST3_SEG0',
|
|
'HDA_BASE__INST3_SEG1', 'HDA_BASE__INST3_SEG2',
|
|
'HDA_BASE__INST3_SEG3', 'HDA_BASE__INST3_SEG4',
|
|
'HDA_BASE__INST4_SEG0', 'HDA_BASE__INST4_SEG1',
|
|
'HDA_BASE__INST4_SEG2', 'HDA_BASE__INST4_SEG3',
|
|
'HDA_BASE__INST4_SEG4', 'HDA_BASE__INST5_SEG0',
|
|
'HDA_BASE__INST5_SEG1', 'HDA_BASE__INST5_SEG2',
|
|
'HDA_BASE__INST5_SEG3', 'HDA_BASE__INST5_SEG4',
|
|
'HDA_BASE__INST6_SEG0', 'HDA_BASE__INST6_SEG1',
|
|
'HDA_BASE__INST6_SEG2', 'HDA_BASE__INST6_SEG3',
|
|
'HDA_BASE__INST6_SEG4', 'HDP_BASE', 'HDP_BASE__INST0_SEG0',
|
|
'HDP_BASE__INST0_SEG1', 'HDP_BASE__INST0_SEG2',
|
|
'HDP_BASE__INST0_SEG3', 'HDP_BASE__INST0_SEG4',
|
|
'HDP_BASE__INST1_SEG0', 'HDP_BASE__INST1_SEG1',
|
|
'HDP_BASE__INST1_SEG2', 'HDP_BASE__INST1_SEG3',
|
|
'HDP_BASE__INST1_SEG4', 'HDP_BASE__INST2_SEG0',
|
|
'HDP_BASE__INST2_SEG1', 'HDP_BASE__INST2_SEG2',
|
|
'HDP_BASE__INST2_SEG3', 'HDP_BASE__INST2_SEG4',
|
|
'HDP_BASE__INST3_SEG0', 'HDP_BASE__INST3_SEG1',
|
|
'HDP_BASE__INST3_SEG2', 'HDP_BASE__INST3_SEG3',
|
|
'HDP_BASE__INST3_SEG4', 'HDP_BASE__INST4_SEG0',
|
|
'HDP_BASE__INST4_SEG1', 'HDP_BASE__INST4_SEG2',
|
|
'HDP_BASE__INST4_SEG3', 'HDP_BASE__INST4_SEG4',
|
|
'HDP_BASE__INST5_SEG0', 'HDP_BASE__INST5_SEG1',
|
|
'HDP_BASE__INST5_SEG2', 'HDP_BASE__INST5_SEG3',
|
|
'HDP_BASE__INST5_SEG4', 'HDP_BASE__INST6_SEG0',
|
|
'HDP_BASE__INST6_SEG1', 'HDP_BASE__INST6_SEG2',
|
|
'HDP_BASE__INST6_SEG3', 'HDP_BASE__INST6_SEG4',
|
|
'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', 'INDIRECT_BUFFER_VALID',
|
|
'MAX_INSTANCE', 'MAX_SEGMENT', 'MMHUB_BASE',
|
|
'MMHUB_BASE__INST0_SEG0', 'MMHUB_BASE__INST0_SEG1',
|
|
'MMHUB_BASE__INST0_SEG2', 'MMHUB_BASE__INST0_SEG3',
|
|
'MMHUB_BASE__INST0_SEG4', 'MMHUB_BASE__INST1_SEG0',
|
|
'MMHUB_BASE__INST1_SEG1', 'MMHUB_BASE__INST1_SEG2',
|
|
'MMHUB_BASE__INST1_SEG3', 'MMHUB_BASE__INST1_SEG4',
|
|
'MMHUB_BASE__INST2_SEG0', 'MMHUB_BASE__INST2_SEG1',
|
|
'MMHUB_BASE__INST2_SEG2', 'MMHUB_BASE__INST2_SEG3',
|
|
'MMHUB_BASE__INST2_SEG4', 'MMHUB_BASE__INST3_SEG0',
|
|
'MMHUB_BASE__INST3_SEG1', 'MMHUB_BASE__INST3_SEG2',
|
|
'MMHUB_BASE__INST3_SEG3', 'MMHUB_BASE__INST3_SEG4',
|
|
'MMHUB_BASE__INST4_SEG0', 'MMHUB_BASE__INST4_SEG1',
|
|
'MMHUB_BASE__INST4_SEG2', 'MMHUB_BASE__INST4_SEG3',
|
|
'MMHUB_BASE__INST4_SEG4', 'MMHUB_BASE__INST5_SEG0',
|
|
'MMHUB_BASE__INST5_SEG1', 'MMHUB_BASE__INST5_SEG2',
|
|
'MMHUB_BASE__INST5_SEG3', 'MMHUB_BASE__INST5_SEG4',
|
|
'MMHUB_BASE__INST6_SEG0', 'MMHUB_BASE__INST6_SEG1',
|
|
'MMHUB_BASE__INST6_SEG2', 'MMHUB_BASE__INST6_SEG3',
|
|
'MMHUB_BASE__INST6_SEG4', 'MP0_BASE', 'MP0_BASE__INST0_SEG0',
|
|
'MP0_BASE__INST0_SEG1', 'MP0_BASE__INST0_SEG2',
|
|
'MP0_BASE__INST0_SEG3', 'MP0_BASE__INST0_SEG4',
|
|
'MP0_BASE__INST1_SEG0', 'MP0_BASE__INST1_SEG1',
|
|
'MP0_BASE__INST1_SEG2', 'MP0_BASE__INST1_SEG3',
|
|
'MP0_BASE__INST1_SEG4', 'MP0_BASE__INST2_SEG0',
|
|
'MP0_BASE__INST2_SEG1', 'MP0_BASE__INST2_SEG2',
|
|
'MP0_BASE__INST2_SEG3', 'MP0_BASE__INST2_SEG4',
|
|
'MP0_BASE__INST3_SEG0', 'MP0_BASE__INST3_SEG1',
|
|
'MP0_BASE__INST3_SEG2', 'MP0_BASE__INST3_SEG3',
|
|
'MP0_BASE__INST3_SEG4', 'MP0_BASE__INST4_SEG0',
|
|
'MP0_BASE__INST4_SEG1', 'MP0_BASE__INST4_SEG2',
|
|
'MP0_BASE__INST4_SEG3', 'MP0_BASE__INST4_SEG4',
|
|
'MP0_BASE__INST5_SEG0', 'MP0_BASE__INST5_SEG1',
|
|
'MP0_BASE__INST5_SEG2', 'MP0_BASE__INST5_SEG3',
|
|
'MP0_BASE__INST5_SEG4', 'MP0_BASE__INST6_SEG0',
|
|
'MP0_BASE__INST6_SEG1', 'MP0_BASE__INST6_SEG2',
|
|
'MP0_BASE__INST6_SEG3', 'MP0_BASE__INST6_SEG4', 'MP1_BASE',
|
|
'MP1_BASE__INST0_SEG0', 'MP1_BASE__INST0_SEG1',
|
|
'MP1_BASE__INST0_SEG2', 'MP1_BASE__INST0_SEG3',
|
|
'MP1_BASE__INST0_SEG4', 'MP1_BASE__INST1_SEG0',
|
|
'MP1_BASE__INST1_SEG1', 'MP1_BASE__INST1_SEG2',
|
|
'MP1_BASE__INST1_SEG3', 'MP1_BASE__INST1_SEG4',
|
|
'MP1_BASE__INST2_SEG0', 'MP1_BASE__INST2_SEG1',
|
|
'MP1_BASE__INST2_SEG2', 'MP1_BASE__INST2_SEG3',
|
|
'MP1_BASE__INST2_SEG4', 'MP1_BASE__INST3_SEG0',
|
|
'MP1_BASE__INST3_SEG1', 'MP1_BASE__INST3_SEG2',
|
|
'MP1_BASE__INST3_SEG3', 'MP1_BASE__INST3_SEG4',
|
|
'MP1_BASE__INST4_SEG0', 'MP1_BASE__INST4_SEG1',
|
|
'MP1_BASE__INST4_SEG2', 'MP1_BASE__INST4_SEG3',
|
|
'MP1_BASE__INST4_SEG4', 'MP1_BASE__INST5_SEG0',
|
|
'MP1_BASE__INST5_SEG1', 'MP1_BASE__INST5_SEG2',
|
|
'MP1_BASE__INST5_SEG3', 'MP1_BASE__INST5_SEG4',
|
|
'MP1_BASE__INST6_SEG0', 'MP1_BASE__INST6_SEG1',
|
|
'MP1_BASE__INST6_SEG2', 'MP1_BASE__INST6_SEG3',
|
|
'MP1_BASE__INST6_SEG4', 'NBIO_BASE', 'NBIO_BASE__INST0_SEG0',
|
|
'NBIO_BASE__INST0_SEG1', 'NBIO_BASE__INST0_SEG2',
|
|
'NBIO_BASE__INST0_SEG3', 'NBIO_BASE__INST0_SEG4',
|
|
'NBIO_BASE__INST1_SEG0', 'NBIO_BASE__INST1_SEG1',
|
|
'NBIO_BASE__INST1_SEG2', 'NBIO_BASE__INST1_SEG3',
|
|
'NBIO_BASE__INST1_SEG4', 'NBIO_BASE__INST2_SEG0',
|
|
'NBIO_BASE__INST2_SEG1', 'NBIO_BASE__INST2_SEG2',
|
|
'NBIO_BASE__INST2_SEG3', 'NBIO_BASE__INST2_SEG4',
|
|
'NBIO_BASE__INST3_SEG0', 'NBIO_BASE__INST3_SEG1',
|
|
'NBIO_BASE__INST3_SEG2', 'NBIO_BASE__INST3_SEG3',
|
|
'NBIO_BASE__INST3_SEG4', 'NBIO_BASE__INST4_SEG0',
|
|
'NBIO_BASE__INST4_SEG1', 'NBIO_BASE__INST4_SEG2',
|
|
'NBIO_BASE__INST4_SEG3', 'NBIO_BASE__INST4_SEG4',
|
|
'NBIO_BASE__INST5_SEG0', 'NBIO_BASE__INST5_SEG1',
|
|
'NBIO_BASE__INST5_SEG2', 'NBIO_BASE__INST5_SEG3',
|
|
'NBIO_BASE__INST5_SEG4', 'NBIO_BASE__INST6_SEG0',
|
|
'NBIO_BASE__INST6_SEG1', 'NBIO_BASE__INST6_SEG2',
|
|
'NBIO_BASE__INST6_SEG3', 'NBIO_BASE__INST6_SEG4', 'NVD_H',
|
|
'OSSSYS_BASE', 'OSSSYS_BASE__INST0_SEG0',
|
|
'OSSSYS_BASE__INST0_SEG1', 'OSSSYS_BASE__INST0_SEG2',
|
|
'OSSSYS_BASE__INST0_SEG3', 'OSSSYS_BASE__INST0_SEG4',
|
|
'OSSSYS_BASE__INST1_SEG0', 'OSSSYS_BASE__INST1_SEG1',
|
|
'OSSSYS_BASE__INST1_SEG2', 'OSSSYS_BASE__INST1_SEG3',
|
|
'OSSSYS_BASE__INST1_SEG4', 'OSSSYS_BASE__INST2_SEG0',
|
|
'OSSSYS_BASE__INST2_SEG1', 'OSSSYS_BASE__INST2_SEG2',
|
|
'OSSSYS_BASE__INST2_SEG3', 'OSSSYS_BASE__INST2_SEG4',
|
|
'OSSSYS_BASE__INST3_SEG0', 'OSSSYS_BASE__INST3_SEG1',
|
|
'OSSSYS_BASE__INST3_SEG2', 'OSSSYS_BASE__INST3_SEG3',
|
|
'OSSSYS_BASE__INST3_SEG4', 'OSSSYS_BASE__INST4_SEG0',
|
|
'OSSSYS_BASE__INST4_SEG1', 'OSSSYS_BASE__INST4_SEG2',
|
|
'OSSSYS_BASE__INST4_SEG3', 'OSSSYS_BASE__INST4_SEG4',
|
|
'OSSSYS_BASE__INST5_SEG0', 'OSSSYS_BASE__INST5_SEG1',
|
|
'OSSSYS_BASE__INST5_SEG2', 'OSSSYS_BASE__INST5_SEG3',
|
|
'OSSSYS_BASE__INST5_SEG4', 'OSSSYS_BASE__INST6_SEG0',
|
|
'OSSSYS_BASE__INST6_SEG1', 'OSSSYS_BASE__INST6_SEG2',
|
|
'OSSSYS_BASE__INST6_SEG3', 'OSSSYS_BASE__INST6_SEG4',
|
|
'PACKET2_PAD_MASK', 'PACKET2_PAD_SHIFT', 'PACKET3_ACQUIRE_MEM',
|
|
'PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA', 'PACKET3_AQL_PACKET',
|
|
'PACKET3_ATOMIC_GDS', 'PACKET3_ATOMIC_MEM',
|
|
'PACKET3_BLK_CNTX_UPDATE', 'PACKET3_CLEAR_STATE',
|
|
'PACKET3_COND_EXEC', 'PACKET3_COND_INDIRECT_BUFFER',
|
|
'PACKET3_COND_INDIRECT_BUFFER_CNST', 'PACKET3_COND_PREEMPT',
|
|
'PACKET3_COND_WRITE', 'PACKET3_CONTEXT_CONTROL',
|
|
'PACKET3_CONTEXT_REG_RMW', 'PACKET3_COPY_DATA',
|
|
'PACKET3_COPY_DATA_RB', 'PACKET3_COPY_DW', 'PACKET3_CP_DMA',
|
|
'PACKET3_DISPATCH_DIRECT', 'PACKET3_DISPATCH_DRAW',
|
|
'PACKET3_DISPATCH_DRAW_ACE', 'PACKET3_DISPATCH_DRAW_PREAMBLE',
|
|
'PACKET3_DISPATCH_DRAW_PREAMBLE_ACE', 'PACKET3_DISPATCH_INDIRECT',
|
|
'PACKET3_DMA_DATA', 'PACKET3_DMA_DATA_CMD_DAIC',
|
|
'PACKET3_DMA_DATA_CMD_DAS', 'PACKET3_DMA_DATA_CMD_RAW_WAIT',
|
|
'PACKET3_DMA_DATA_CMD_SAIC', 'PACKET3_DMA_DATA_CMD_SAS',
|
|
'PACKET3_DMA_DATA_CP_SYNC', 'PACKET3_DMA_DATA_FILL_MULTI',
|
|
'PACKET3_DRAW_INDEX_2', 'PACKET3_DRAW_INDEX_AUTO',
|
|
'PACKET3_DRAW_INDEX_INDIRECT',
|
|
'PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI',
|
|
'PACKET3_DRAW_INDEX_INDIRECT_MULTI',
|
|
'PACKET3_DRAW_INDEX_MULTI_AUTO', 'PACKET3_DRAW_INDEX_MULTI_INST',
|
|
'PACKET3_DRAW_INDEX_OFFSET_2', 'PACKET3_DRAW_INDIRECT',
|
|
'PACKET3_DRAW_INDIRECT_COUNT_MULTI',
|
|
'PACKET3_DRAW_INDIRECT_MULTI', 'PACKET3_DRAW_MULTI_PREAMBLE',
|
|
'PACKET3_DRAW_PREAMBLE', 'PACKET3_DUMP_CONST_RAM',
|
|
'PACKET3_DUMP_CONST_RAM_OFFSET', 'PACKET3_EVENT_WRITE',
|
|
'PACKET3_EVENT_WRITE_EOP', 'PACKET3_EVENT_WRITE_EOS',
|
|
'PACKET3_FORWARD_HEADER', 'PACKET3_FRAME_CONTROL',
|
|
'PACKET3_GEN_PDEPTE', 'PACKET3_GET_LOD_STATS',
|
|
'PACKET3_GFX_CNTX_UPDATE', 'PACKET3_GFX_PIPE_LOCK',
|
|
'PACKET3_HDP_FLUSH', 'PACKET3_INCREMENT_CE_COUNTER',
|
|
'PACKET3_INCREMENT_DE_COUNTER', 'PACKET3_INCR_UPDT_STATE',
|
|
'PACKET3_INDEX_ATTRIBUTES_INDIRECT', 'PACKET3_INDEX_BASE',
|
|
'PACKET3_INDEX_BUFFER_SIZE', 'PACKET3_INDEX_TYPE',
|
|
'PACKET3_INDIRECT_BUFFER', 'PACKET3_INDIRECT_BUFFER_CNST',
|
|
'PACKET3_INDIRECT_BUFFER_CNST_END', 'PACKET3_INDIRECT_BUFFER_END',
|
|
'PACKET3_INDIRECT_BUFFER_PASID', 'PACKET3_INDIRECT_BUFFER_PRIV',
|
|
'PACKET3_INTERRUPT', 'PACKET3_INVALIDATE_TLBS',
|
|
'PACKET3_LOAD_COMPUTE_STATE', 'PACKET3_LOAD_CONFIG_REG',
|
|
'PACKET3_LOAD_CONST_RAM', 'PACKET3_LOAD_CONTEXT_REG',
|
|
'PACKET3_LOAD_CONTEXT_REG_INDEX', 'PACKET3_LOAD_SH_REG',
|
|
'PACKET3_LOAD_SH_REG_INDEX', 'PACKET3_LOAD_UCONFIG_REG',
|
|
'PACKET3_MAP_PROCESS', 'PACKET3_MAP_PROCESS_VM',
|
|
'PACKET3_MAP_QUEUES', 'PACKET3_MEM_SEMAPHORE',
|
|
'PACKET3_ME_INITIALIZE', 'PACKET3_NOP', 'PACKET3_NUM_INSTANCES',
|
|
'PACKET3_OCCLUSION_QUERY', 'PACKET3_PFP_SYNC_ME',
|
|
'PACKET3_PREAMBLE_BEGIN_CLEAR_STATE', 'PACKET3_PREAMBLE_CNTL',
|
|
'PACKET3_PREAMBLE_END_CLEAR_STATE', 'PACKET3_PRED_EXEC',
|
|
'PACKET3_PRIME_UTCL2', 'PACKET3_QUERY_STATUS', 'PACKET3_REG_RMW',
|
|
'PACKET3_RELEASE_MEM', 'PACKET3_RELEASE_MEM_EXECUTE',
|
|
'PACKET3_RELEASE_MEM_GCR_GL1_INV',
|
|
'PACKET3_RELEASE_MEM_GCR_GL2_DISCARD',
|
|
'PACKET3_RELEASE_MEM_GCR_GL2_INV',
|
|
'PACKET3_RELEASE_MEM_GCR_GL2_RANGE',
|
|
'PACKET3_RELEASE_MEM_GCR_GL2_US',
|
|
'PACKET3_RELEASE_MEM_GCR_GL2_WB',
|
|
'PACKET3_RELEASE_MEM_GCR_GLM_INV',
|
|
'PACKET3_RELEASE_MEM_GCR_GLM_WB',
|
|
'PACKET3_RELEASE_MEM_GCR_GLV_INV', 'PACKET3_RELEASE_MEM_GCR_SEQ',
|
|
'PACKET3_REWIND', 'PACKET3_RUN_LIST', 'PACKET3_SCRATCH_RAM_READ',
|
|
'PACKET3_SCRATCH_RAM_WRITE', 'PACKET3_SEM_SEL_SIGNAL',
|
|
'PACKET3_SEM_SEL_SIGNAL_TYPE', 'PACKET3_SEM_SEL_WAIT',
|
|
'PACKET3_SEM_USE_MAILBOX', 'PACKET3_SET_BASE',
|
|
'PACKET3_SET_CONFIG_REG', 'PACKET3_SET_CONFIG_REG_END',
|
|
'PACKET3_SET_CONFIG_REG_START', 'PACKET3_SET_CONTEXT_REG',
|
|
'PACKET3_SET_CONTEXT_REG_END', 'PACKET3_SET_CONTEXT_REG_INDEX',
|
|
'PACKET3_SET_CONTEXT_REG_INDIRECT',
|
|
'PACKET3_SET_CONTEXT_REG_START', 'PACKET3_SET_PREDICATION',
|
|
'PACKET3_SET_QUEUE_REG', 'PACKET3_SET_Q_PREEMPTION_MODE',
|
|
'PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM',
|
|
'PACKET3_SET_RESOURCES', 'PACKET3_SET_SH_REG',
|
|
'PACKET3_SET_SH_REG_DI', 'PACKET3_SET_SH_REG_DI_MULTI',
|
|
'PACKET3_SET_SH_REG_END', 'PACKET3_SET_SH_REG_INDEX',
|
|
'PACKET3_SET_SH_REG_OFFSET', 'PACKET3_SET_SH_REG_START',
|
|
'PACKET3_SET_UCONFIG_REG', 'PACKET3_SET_UCONFIG_REG_END',
|
|
'PACKET3_SET_UCONFIG_REG_INDEX', 'PACKET3_SET_UCONFIG_REG_START',
|
|
'PACKET3_SET_VGPR_REG_DI_MULTI', 'PACKET3_STRMOUT_BUFFER_UPDATE',
|
|
'PACKET3_SURFACE_SYNC', 'PACKET3_SWITCH_BUFFER',
|
|
'PACKET3_UNMAP_QUEUES', 'PACKET3_WAIT_ON_CE_COUNTER',
|
|
'PACKET3_WAIT_ON_DE_COUNTER_DIFF', 'PACKET3_WAIT_REG_MEM',
|
|
'PACKET3_WAIT_REG_MEM64', 'PACKET3_WRITE_CONST_RAM',
|
|
'PACKET3_WRITE_DATA', 'PACKET_TYPE0', 'PACKET_TYPE1',
|
|
'PACKET_TYPE2', 'PACKET_TYPE3', 'PCIE0_BASE',
|
|
'PCIE0_BASE__INST0_SEG0', 'PCIE0_BASE__INST0_SEG1',
|
|
'PCIE0_BASE__INST0_SEG2', 'PCIE0_BASE__INST0_SEG3',
|
|
'PCIE0_BASE__INST0_SEG4', 'PCIE0_BASE__INST1_SEG0',
|
|
'PCIE0_BASE__INST1_SEG1', 'PCIE0_BASE__INST1_SEG2',
|
|
'PCIE0_BASE__INST1_SEG3', 'PCIE0_BASE__INST1_SEG4',
|
|
'PCIE0_BASE__INST2_SEG0', 'PCIE0_BASE__INST2_SEG1',
|
|
'PCIE0_BASE__INST2_SEG2', 'PCIE0_BASE__INST2_SEG3',
|
|
'PCIE0_BASE__INST2_SEG4', 'PCIE0_BASE__INST3_SEG0',
|
|
'PCIE0_BASE__INST3_SEG1', 'PCIE0_BASE__INST3_SEG2',
|
|
'PCIE0_BASE__INST3_SEG3', 'PCIE0_BASE__INST3_SEG4',
|
|
'PCIE0_BASE__INST4_SEG0', 'PCIE0_BASE__INST4_SEG1',
|
|
'PCIE0_BASE__INST4_SEG2', 'PCIE0_BASE__INST4_SEG3',
|
|
'PCIE0_BASE__INST4_SEG4', 'PCIE0_BASE__INST5_SEG0',
|
|
'PCIE0_BASE__INST5_SEG1', 'PCIE0_BASE__INST5_SEG2',
|
|
'PCIE0_BASE__INST5_SEG3', 'PCIE0_BASE__INST5_SEG4',
|
|
'PCIE0_BASE__INST6_SEG0', 'PCIE0_BASE__INST6_SEG1',
|
|
'PCIE0_BASE__INST6_SEG2', 'PCIE0_BASE__INST6_SEG3',
|
|
'PCIE0_BASE__INST6_SEG4', 'SDMA0_BASE', 'SDMA0_BASE__INST0_SEG0',
|
|
'SDMA0_BASE__INST0_SEG1', 'SDMA0_BASE__INST0_SEG2',
|
|
'SDMA0_BASE__INST0_SEG3', 'SDMA0_BASE__INST0_SEG4',
|
|
'SDMA0_BASE__INST1_SEG0', 'SDMA0_BASE__INST1_SEG1',
|
|
'SDMA0_BASE__INST1_SEG2', 'SDMA0_BASE__INST1_SEG3',
|
|
'SDMA0_BASE__INST1_SEG4', 'SDMA0_BASE__INST2_SEG0',
|
|
'SDMA0_BASE__INST2_SEG1', 'SDMA0_BASE__INST2_SEG2',
|
|
'SDMA0_BASE__INST2_SEG3', 'SDMA0_BASE__INST2_SEG4',
|
|
'SDMA0_BASE__INST3_SEG0', 'SDMA0_BASE__INST3_SEG1',
|
|
'SDMA0_BASE__INST3_SEG2', 'SDMA0_BASE__INST3_SEG3',
|
|
'SDMA0_BASE__INST3_SEG4', 'SDMA0_BASE__INST4_SEG0',
|
|
'SDMA0_BASE__INST4_SEG1', 'SDMA0_BASE__INST4_SEG2',
|
|
'SDMA0_BASE__INST4_SEG3', 'SDMA0_BASE__INST4_SEG4',
|
|
'SDMA0_BASE__INST5_SEG0', 'SDMA0_BASE__INST5_SEG1',
|
|
'SDMA0_BASE__INST5_SEG2', 'SDMA0_BASE__INST5_SEG3',
|
|
'SDMA0_BASE__INST5_SEG4', 'SDMA0_BASE__INST6_SEG0',
|
|
'SDMA0_BASE__INST6_SEG1', 'SDMA0_BASE__INST6_SEG2',
|
|
'SDMA0_BASE__INST6_SEG3', 'SDMA0_BASE__INST6_SEG4', 'SDMA1_BASE',
|
|
'SDMA1_BASE__INST0_SEG0', 'SDMA1_BASE__INST0_SEG1',
|
|
'SDMA1_BASE__INST0_SEG2', 'SDMA1_BASE__INST0_SEG3',
|
|
'SDMA1_BASE__INST0_SEG4', 'SDMA1_BASE__INST1_SEG0',
|
|
'SDMA1_BASE__INST1_SEG1', 'SDMA1_BASE__INST1_SEG2',
|
|
'SDMA1_BASE__INST1_SEG3', 'SDMA1_BASE__INST1_SEG4',
|
|
'SDMA1_BASE__INST2_SEG0', 'SDMA1_BASE__INST2_SEG1',
|
|
'SDMA1_BASE__INST2_SEG2', 'SDMA1_BASE__INST2_SEG3',
|
|
'SDMA1_BASE__INST2_SEG4', 'SDMA1_BASE__INST3_SEG0',
|
|
'SDMA1_BASE__INST3_SEG1', 'SDMA1_BASE__INST3_SEG2',
|
|
'SDMA1_BASE__INST3_SEG3', 'SDMA1_BASE__INST3_SEG4',
|
|
'SDMA1_BASE__INST4_SEG0', 'SDMA1_BASE__INST4_SEG1',
|
|
'SDMA1_BASE__INST4_SEG2', 'SDMA1_BASE__INST4_SEG3',
|
|
'SDMA1_BASE__INST4_SEG4', 'SDMA1_BASE__INST5_SEG0',
|
|
'SDMA1_BASE__INST5_SEG1', 'SDMA1_BASE__INST5_SEG2',
|
|
'SDMA1_BASE__INST5_SEG3', 'SDMA1_BASE__INST5_SEG4',
|
|
'SDMA1_BASE__INST6_SEG0', 'SDMA1_BASE__INST6_SEG1',
|
|
'SDMA1_BASE__INST6_SEG2', 'SDMA1_BASE__INST6_SEG3',
|
|
'SDMA1_BASE__INST6_SEG4', 'SDMA_ATOMIC_ADD64', 'SDMA_OP_ATOMIC',
|
|
'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', 'SDMA_OP_FENCE',
|
|
'SDMA_OP_GCR', 'SDMA_OP_POLL_REGMEM', 'SDMA_OP_TIMESTAMP',
|
|
'SDMA_OP_TRAP', 'SDMA_PKT_ATOMIC', 'SDMA_PKT_CONSTANT_FILL',
|
|
'SDMA_PKT_COPY_LINEAR', 'SDMA_PKT_COPY_LINEAR_RECT',
|
|
'SDMA_PKT_FENCE', 'SDMA_PKT_GCR', 'SDMA_PKT_HDP_FLUSH',
|
|
'SDMA_PKT_POLL_REGMEM', 'SDMA_PKT_TIMESTAMP', 'SDMA_PKT_TRAP',
|
|
'SDMA_SUBOP_COPY_LINEAR', 'SDMA_SUBOP_COPY_LINEAR_RECT',
|
|
'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', 'SDMA_SUBOP_USER_GCR',
|
|
'SMUIO_BASE', 'SMUIO_BASE__INST0_SEG0', 'SMUIO_BASE__INST0_SEG1',
|
|
'SMUIO_BASE__INST0_SEG2', 'SMUIO_BASE__INST0_SEG3',
|
|
'SMUIO_BASE__INST0_SEG4', 'SMUIO_BASE__INST1_SEG0',
|
|
'SMUIO_BASE__INST1_SEG1', 'SMUIO_BASE__INST1_SEG2',
|
|
'SMUIO_BASE__INST1_SEG3', 'SMUIO_BASE__INST1_SEG4',
|
|
'SMUIO_BASE__INST2_SEG0', 'SMUIO_BASE__INST2_SEG1',
|
|
'SMUIO_BASE__INST2_SEG2', 'SMUIO_BASE__INST2_SEG3',
|
|
'SMUIO_BASE__INST2_SEG4', 'SMUIO_BASE__INST3_SEG0',
|
|
'SMUIO_BASE__INST3_SEG1', 'SMUIO_BASE__INST3_SEG2',
|
|
'SMUIO_BASE__INST3_SEG3', 'SMUIO_BASE__INST3_SEG4',
|
|
'SMUIO_BASE__INST4_SEG0', 'SMUIO_BASE__INST4_SEG1',
|
|
'SMUIO_BASE__INST4_SEG2', 'SMUIO_BASE__INST4_SEG3',
|
|
'SMUIO_BASE__INST4_SEG4', 'SMUIO_BASE__INST5_SEG0',
|
|
'SMUIO_BASE__INST5_SEG1', 'SMUIO_BASE__INST5_SEG2',
|
|
'SMUIO_BASE__INST5_SEG3', 'SMUIO_BASE__INST5_SEG4',
|
|
'SMUIO_BASE__INST6_SEG0', 'SMUIO_BASE__INST6_SEG1',
|
|
'SMUIO_BASE__INST6_SEG2', 'SMUIO_BASE__INST6_SEG3',
|
|
'SMUIO_BASE__INST6_SEG4', 'THM_BASE', 'THM_BASE__INST0_SEG0',
|
|
'THM_BASE__INST0_SEG1', 'THM_BASE__INST0_SEG2',
|
|
'THM_BASE__INST0_SEG3', 'THM_BASE__INST0_SEG4',
|
|
'THM_BASE__INST1_SEG0', 'THM_BASE__INST1_SEG1',
|
|
'THM_BASE__INST1_SEG2', 'THM_BASE__INST1_SEG3',
|
|
'THM_BASE__INST1_SEG4', 'THM_BASE__INST2_SEG0',
|
|
'THM_BASE__INST2_SEG1', 'THM_BASE__INST2_SEG2',
|
|
'THM_BASE__INST2_SEG3', 'THM_BASE__INST2_SEG4',
|
|
'THM_BASE__INST3_SEG0', 'THM_BASE__INST3_SEG1',
|
|
'THM_BASE__INST3_SEG2', 'THM_BASE__INST3_SEG3',
|
|
'THM_BASE__INST3_SEG4', 'THM_BASE__INST4_SEG0',
|
|
'THM_BASE__INST4_SEG1', 'THM_BASE__INST4_SEG2',
|
|
'THM_BASE__INST4_SEG3', 'THM_BASE__INST4_SEG4',
|
|
'THM_BASE__INST5_SEG0', 'THM_BASE__INST5_SEG1',
|
|
'THM_BASE__INST5_SEG2', 'THM_BASE__INST5_SEG3',
|
|
'THM_BASE__INST5_SEG4', 'THM_BASE__INST6_SEG0',
|
|
'THM_BASE__INST6_SEG1', 'THM_BASE__INST6_SEG2',
|
|
'THM_BASE__INST6_SEG3', 'THM_BASE__INST6_SEG4', 'UMC_BASE',
|
|
'UMC_BASE__INST0_SEG0', 'UMC_BASE__INST0_SEG1',
|
|
'UMC_BASE__INST0_SEG2', 'UMC_BASE__INST0_SEG3',
|
|
'UMC_BASE__INST0_SEG4', 'UMC_BASE__INST1_SEG0',
|
|
'UMC_BASE__INST1_SEG1', 'UMC_BASE__INST1_SEG2',
|
|
'UMC_BASE__INST1_SEG3', 'UMC_BASE__INST1_SEG4',
|
|
'UMC_BASE__INST2_SEG0', 'UMC_BASE__INST2_SEG1',
|
|
'UMC_BASE__INST2_SEG2', 'UMC_BASE__INST2_SEG3',
|
|
'UMC_BASE__INST2_SEG4', 'UMC_BASE__INST3_SEG0',
|
|
'UMC_BASE__INST3_SEG1', 'UMC_BASE__INST3_SEG2',
|
|
'UMC_BASE__INST3_SEG3', 'UMC_BASE__INST3_SEG4',
|
|
'UMC_BASE__INST4_SEG0', 'UMC_BASE__INST4_SEG1',
|
|
'UMC_BASE__INST4_SEG2', 'UMC_BASE__INST4_SEG3',
|
|
'UMC_BASE__INST4_SEG4', 'UMC_BASE__INST5_SEG0',
|
|
'UMC_BASE__INST5_SEG1', 'UMC_BASE__INST5_SEG2',
|
|
'UMC_BASE__INST5_SEG3', 'UMC_BASE__INST5_SEG4',
|
|
'UMC_BASE__INST6_SEG0', 'UMC_BASE__INST6_SEG1',
|
|
'UMC_BASE__INST6_SEG2', 'UMC_BASE__INST6_SEG3',
|
|
'UMC_BASE__INST6_SEG4', 'USB0_BASE', 'USB0_BASE__INST0_SEG0',
|
|
'USB0_BASE__INST0_SEG1', 'USB0_BASE__INST0_SEG2',
|
|
'USB0_BASE__INST0_SEG3', 'USB0_BASE__INST0_SEG4',
|
|
'USB0_BASE__INST1_SEG0', 'USB0_BASE__INST1_SEG1',
|
|
'USB0_BASE__INST1_SEG2', 'USB0_BASE__INST1_SEG3',
|
|
'USB0_BASE__INST1_SEG4', 'USB0_BASE__INST2_SEG0',
|
|
'USB0_BASE__INST2_SEG1', 'USB0_BASE__INST2_SEG2',
|
|
'USB0_BASE__INST2_SEG3', 'USB0_BASE__INST2_SEG4',
|
|
'USB0_BASE__INST3_SEG0', 'USB0_BASE__INST3_SEG1',
|
|
'USB0_BASE__INST3_SEG2', 'USB0_BASE__INST3_SEG3',
|
|
'USB0_BASE__INST3_SEG4', 'USB0_BASE__INST4_SEG0',
|
|
'USB0_BASE__INST4_SEG1', 'USB0_BASE__INST4_SEG2',
|
|
'USB0_BASE__INST4_SEG3', 'USB0_BASE__INST4_SEG4',
|
|
'USB0_BASE__INST5_SEG0', 'USB0_BASE__INST5_SEG1',
|
|
'USB0_BASE__INST5_SEG2', 'USB0_BASE__INST5_SEG3',
|
|
'USB0_BASE__INST5_SEG4', 'USB0_BASE__INST6_SEG0',
|
|
'USB0_BASE__INST6_SEG1', 'USB0_BASE__INST6_SEG2',
|
|
'USB0_BASE__INST6_SEG3', 'USB0_BASE__INST6_SEG4', 'VCN_BASE',
|
|
'VCN_BASE__INST0_SEG0', 'VCN_BASE__INST0_SEG1',
|
|
'VCN_BASE__INST0_SEG2', 'VCN_BASE__INST0_SEG3',
|
|
'VCN_BASE__INST0_SEG4', 'VCN_BASE__INST1_SEG0',
|
|
'VCN_BASE__INST1_SEG1', 'VCN_BASE__INST1_SEG2',
|
|
'VCN_BASE__INST1_SEG3', 'VCN_BASE__INST1_SEG4',
|
|
'VCN_BASE__INST2_SEG0', 'VCN_BASE__INST2_SEG1',
|
|
'VCN_BASE__INST2_SEG2', 'VCN_BASE__INST2_SEG3',
|
|
'VCN_BASE__INST2_SEG4', 'VCN_BASE__INST3_SEG0',
|
|
'VCN_BASE__INST3_SEG1', 'VCN_BASE__INST3_SEG2',
|
|
'VCN_BASE__INST3_SEG3', 'VCN_BASE__INST3_SEG4',
|
|
'VCN_BASE__INST4_SEG0', 'VCN_BASE__INST4_SEG1',
|
|
'VCN_BASE__INST4_SEG2', 'VCN_BASE__INST4_SEG3',
|
|
'VCN_BASE__INST4_SEG4', 'VCN_BASE__INST5_SEG0',
|
|
'VCN_BASE__INST5_SEG1', 'VCN_BASE__INST5_SEG2',
|
|
'VCN_BASE__INST5_SEG3', 'VCN_BASE__INST5_SEG4',
|
|
'VCN_BASE__INST6_SEG0', 'VCN_BASE__INST6_SEG1',
|
|
'VCN_BASE__INST6_SEG2', 'VCN_BASE__INST6_SEG3',
|
|
'VCN_BASE__INST6_SEG4', 'WR_CONFIRM', 'WR_ONE_ADDR',
|
|
'__maybe_unused', '_gc_11_0_0_OFFSET_HEADER',
|
|
'_sienna_cichlid_ip_offset_HEADER', 'hdp_flush_cmd',
|
|
'ixFIXED_PATTERN_PERF_COUNTER_1',
|
|
'ixFIXED_PATTERN_PERF_COUNTER_10',
|
|
'ixFIXED_PATTERN_PERF_COUNTER_2',
|
|
'ixFIXED_PATTERN_PERF_COUNTER_3',
|
|
'ixFIXED_PATTERN_PERF_COUNTER_4',
|
|
'ixFIXED_PATTERN_PERF_COUNTER_5',
|
|
'ixFIXED_PATTERN_PERF_COUNTER_6',
|
|
'ixFIXED_PATTERN_PERF_COUNTER_7',
|
|
'ixFIXED_PATTERN_PERF_COUNTER_8',
|
|
'ixFIXED_PATTERN_PERF_COUNTER_9', 'ixGC_CAC_ACC_CHC0',
|
|
'ixGC_CAC_ACC_CHC1', 'ixGC_CAC_ACC_CHC2', 'ixGC_CAC_ACC_CP0',
|
|
'ixGC_CAC_ACC_CP1', 'ixGC_CAC_ACC_CP2', 'ixGC_CAC_ACC_EA0',
|
|
'ixGC_CAC_ACC_EA1', 'ixGC_CAC_ACC_EA2', 'ixGC_CAC_ACC_EA3',
|
|
'ixGC_CAC_ACC_EA4', 'ixGC_CAC_ACC_EA5', 'ixGC_CAC_ACC_GDS0',
|
|
'ixGC_CAC_ACC_GDS1', 'ixGC_CAC_ACC_GDS2', 'ixGC_CAC_ACC_GDS3',
|
|
'ixGC_CAC_ACC_GDS4', 'ixGC_CAC_ACC_GE0', 'ixGC_CAC_ACC_GE1',
|
|
'ixGC_CAC_ACC_GE10', 'ixGC_CAC_ACC_GE11', 'ixGC_CAC_ACC_GE12',
|
|
'ixGC_CAC_ACC_GE13', 'ixGC_CAC_ACC_GE14', 'ixGC_CAC_ACC_GE15',
|
|
'ixGC_CAC_ACC_GE16', 'ixGC_CAC_ACC_GE17', 'ixGC_CAC_ACC_GE18',
|
|
'ixGC_CAC_ACC_GE19', 'ixGC_CAC_ACC_GE2', 'ixGC_CAC_ACC_GE20',
|
|
'ixGC_CAC_ACC_GE3', 'ixGC_CAC_ACC_GE4', 'ixGC_CAC_ACC_GE5',
|
|
'ixGC_CAC_ACC_GE6', 'ixGC_CAC_ACC_GE7', 'ixGC_CAC_ACC_GE8',
|
|
'ixGC_CAC_ACC_GE9', 'ixGC_CAC_ACC_GL2C0', 'ixGC_CAC_ACC_GL2C1',
|
|
'ixGC_CAC_ACC_GL2C2', 'ixGC_CAC_ACC_GL2C3', 'ixGC_CAC_ACC_GL2C4',
|
|
'ixGC_CAC_ACC_GUS0', 'ixGC_CAC_ACC_GUS1', 'ixGC_CAC_ACC_GUS2',
|
|
'ixGC_CAC_ACC_PH0', 'ixGC_CAC_ACC_PH1', 'ixGC_CAC_ACC_PH2',
|
|
'ixGC_CAC_ACC_PH3', 'ixGC_CAC_ACC_PH4', 'ixGC_CAC_ACC_PH5',
|
|
'ixGC_CAC_ACC_PH6', 'ixGC_CAC_ACC_PH7', 'ixGC_CAC_ACC_PMM0',
|
|
'ixGC_CAC_ACC_RLC0', 'ixGC_CAC_ACC_SDMA0', 'ixGC_CAC_ACC_SDMA1',
|
|
'ixGC_CAC_ACC_SDMA10', 'ixGC_CAC_ACC_SDMA11',
|
|
'ixGC_CAC_ACC_SDMA2', 'ixGC_CAC_ACC_SDMA3', 'ixGC_CAC_ACC_SDMA4',
|
|
'ixGC_CAC_ACC_SDMA5', 'ixGC_CAC_ACC_SDMA6', 'ixGC_CAC_ACC_SDMA7',
|
|
'ixGC_CAC_ACC_SDMA8', 'ixGC_CAC_ACC_SDMA9',
|
|
'ixGC_CAC_ACC_UTCL2_ROUTER0', 'ixGC_CAC_ACC_UTCL2_ROUTER1',
|
|
'ixGC_CAC_ACC_UTCL2_ROUTER2', 'ixGC_CAC_ACC_UTCL2_ROUTER3',
|
|
'ixGC_CAC_ACC_UTCL2_ROUTER4', 'ixGC_CAC_ACC_UTCL2_ROUTER5',
|
|
'ixGC_CAC_ACC_UTCL2_ROUTER6', 'ixGC_CAC_ACC_UTCL2_ROUTER7',
|
|
'ixGC_CAC_ACC_UTCL2_ROUTER8', 'ixGC_CAC_ACC_UTCL2_ROUTER9',
|
|
'ixGC_CAC_ACC_UTCL2_VML20', 'ixGC_CAC_ACC_UTCL2_VML21',
|
|
'ixGC_CAC_ACC_UTCL2_VML22', 'ixGC_CAC_ACC_UTCL2_VML23',
|
|
'ixGC_CAC_ACC_UTCL2_VML24', 'ixGC_CAC_ACC_UTCL2_WALKER0',
|
|
'ixGC_CAC_ACC_UTCL2_WALKER1', 'ixGC_CAC_ACC_UTCL2_WALKER2',
|
|
'ixGC_CAC_ACC_UTCL2_WALKER3', 'ixGC_CAC_ACC_UTCL2_WALKER4',
|
|
'ixGC_CAC_CNTL', 'ixGC_CAC_ID', 'ixHW_LUT_UPDATE_STATUS',
|
|
'ixPWRBRK_RELEASE_TO_STALL_LUT_17_20',
|
|
'ixPWRBRK_RELEASE_TO_STALL_LUT_1_8',
|
|
'ixPWRBRK_RELEASE_TO_STALL_LUT_9_16',
|
|
'ixPWRBRK_STALL_TO_RELEASE_LUT_1_4',
|
|
'ixPWRBRK_STALL_TO_RELEASE_LUT_5_7',
|
|
'ixRELEASE_TO_STALL_LUT_17_20', 'ixRELEASE_TO_STALL_LUT_1_8',
|
|
'ixRELEASE_TO_STALL_LUT_9_16', 'ixRTAVFS_REG0', 'ixRTAVFS_REG1',
|
|
'ixRTAVFS_REG10', 'ixRTAVFS_REG100', 'ixRTAVFS_REG101',
|
|
'ixRTAVFS_REG102', 'ixRTAVFS_REG103', 'ixRTAVFS_REG104',
|
|
'ixRTAVFS_REG105', 'ixRTAVFS_REG106', 'ixRTAVFS_REG107',
|
|
'ixRTAVFS_REG108', 'ixRTAVFS_REG109', 'ixRTAVFS_REG11',
|
|
'ixRTAVFS_REG110', 'ixRTAVFS_REG111', 'ixRTAVFS_REG112',
|
|
'ixRTAVFS_REG113', 'ixRTAVFS_REG114', 'ixRTAVFS_REG115',
|
|
'ixRTAVFS_REG116', 'ixRTAVFS_REG117', 'ixRTAVFS_REG118',
|
|
'ixRTAVFS_REG119', 'ixRTAVFS_REG12', 'ixRTAVFS_REG120',
|
|
'ixRTAVFS_REG121', 'ixRTAVFS_REG122', 'ixRTAVFS_REG123',
|
|
'ixRTAVFS_REG124', 'ixRTAVFS_REG125', 'ixRTAVFS_REG126',
|
|
'ixRTAVFS_REG127', 'ixRTAVFS_REG128', 'ixRTAVFS_REG129',
|
|
'ixRTAVFS_REG13', 'ixRTAVFS_REG130', 'ixRTAVFS_REG131',
|
|
'ixRTAVFS_REG132', 'ixRTAVFS_REG133', 'ixRTAVFS_REG134',
|
|
'ixRTAVFS_REG135', 'ixRTAVFS_REG136', 'ixRTAVFS_REG137',
|
|
'ixRTAVFS_REG138', 'ixRTAVFS_REG139', 'ixRTAVFS_REG14',
|
|
'ixRTAVFS_REG140', 'ixRTAVFS_REG141', 'ixRTAVFS_REG142',
|
|
'ixRTAVFS_REG143', 'ixRTAVFS_REG144', 'ixRTAVFS_REG145',
|
|
'ixRTAVFS_REG146', 'ixRTAVFS_REG147', 'ixRTAVFS_REG148',
|
|
'ixRTAVFS_REG149', 'ixRTAVFS_REG15', 'ixRTAVFS_REG150',
|
|
'ixRTAVFS_REG151', 'ixRTAVFS_REG152', 'ixRTAVFS_REG153',
|
|
'ixRTAVFS_REG154', 'ixRTAVFS_REG155', 'ixRTAVFS_REG156',
|
|
'ixRTAVFS_REG157', 'ixRTAVFS_REG158', 'ixRTAVFS_REG159',
|
|
'ixRTAVFS_REG16', 'ixRTAVFS_REG160', 'ixRTAVFS_REG161',
|
|
'ixRTAVFS_REG162', 'ixRTAVFS_REG163', 'ixRTAVFS_REG164',
|
|
'ixRTAVFS_REG165', 'ixRTAVFS_REG166', 'ixRTAVFS_REG167',
|
|
'ixRTAVFS_REG168', 'ixRTAVFS_REG169', 'ixRTAVFS_REG17',
|
|
'ixRTAVFS_REG170', 'ixRTAVFS_REG171', 'ixRTAVFS_REG172',
|
|
'ixRTAVFS_REG173', 'ixRTAVFS_REG174', 'ixRTAVFS_REG175',
|
|
'ixRTAVFS_REG176', 'ixRTAVFS_REG177', 'ixRTAVFS_REG178',
|
|
'ixRTAVFS_REG179', 'ixRTAVFS_REG18', 'ixRTAVFS_REG180',
|
|
'ixRTAVFS_REG181', 'ixRTAVFS_REG182', 'ixRTAVFS_REG183',
|
|
'ixRTAVFS_REG184', 'ixRTAVFS_REG185', 'ixRTAVFS_REG186',
|
|
'ixRTAVFS_REG187', 'ixRTAVFS_REG188', 'ixRTAVFS_REG189',
|
|
'ixRTAVFS_REG19', 'ixRTAVFS_REG190', 'ixRTAVFS_REG191',
|
|
'ixRTAVFS_REG192', 'ixRTAVFS_REG193', 'ixRTAVFS_REG194',
|
|
'ixRTAVFS_REG2', 'ixRTAVFS_REG20', 'ixRTAVFS_REG21',
|
|
'ixRTAVFS_REG22', 'ixRTAVFS_REG23', 'ixRTAVFS_REG24',
|
|
'ixRTAVFS_REG25', 'ixRTAVFS_REG26', 'ixRTAVFS_REG27',
|
|
'ixRTAVFS_REG28', 'ixRTAVFS_REG29', 'ixRTAVFS_REG3',
|
|
'ixRTAVFS_REG30', 'ixRTAVFS_REG31', 'ixRTAVFS_REG32',
|
|
'ixRTAVFS_REG33', 'ixRTAVFS_REG34', 'ixRTAVFS_REG35',
|
|
'ixRTAVFS_REG36', 'ixRTAVFS_REG37', 'ixRTAVFS_REG38',
|
|
'ixRTAVFS_REG39', 'ixRTAVFS_REG4', 'ixRTAVFS_REG40',
|
|
'ixRTAVFS_REG41', 'ixRTAVFS_REG42', 'ixRTAVFS_REG43',
|
|
'ixRTAVFS_REG44', 'ixRTAVFS_REG45', 'ixRTAVFS_REG46',
|
|
'ixRTAVFS_REG47', 'ixRTAVFS_REG48', 'ixRTAVFS_REG49',
|
|
'ixRTAVFS_REG5', 'ixRTAVFS_REG50', 'ixRTAVFS_REG51',
|
|
'ixRTAVFS_REG52', 'ixRTAVFS_REG53', 'ixRTAVFS_REG54',
|
|
'ixRTAVFS_REG55', 'ixRTAVFS_REG56', 'ixRTAVFS_REG57',
|
|
'ixRTAVFS_REG58', 'ixRTAVFS_REG59', 'ixRTAVFS_REG6',
|
|
'ixRTAVFS_REG60', 'ixRTAVFS_REG61', 'ixRTAVFS_REG62',
|
|
'ixRTAVFS_REG63', 'ixRTAVFS_REG64', 'ixRTAVFS_REG65',
|
|
'ixRTAVFS_REG66', 'ixRTAVFS_REG67', 'ixRTAVFS_REG68',
|
|
'ixRTAVFS_REG69', 'ixRTAVFS_REG7', 'ixRTAVFS_REG70',
|
|
'ixRTAVFS_REG71', 'ixRTAVFS_REG72', 'ixRTAVFS_REG73',
|
|
'ixRTAVFS_REG74', 'ixRTAVFS_REG75', 'ixRTAVFS_REG76',
|
|
'ixRTAVFS_REG77', 'ixRTAVFS_REG78', 'ixRTAVFS_REG79',
|
|
'ixRTAVFS_REG8', 'ixRTAVFS_REG80', 'ixRTAVFS_REG81',
|
|
'ixRTAVFS_REG82', 'ixRTAVFS_REG83', 'ixRTAVFS_REG84',
|
|
'ixRTAVFS_REG85', 'ixRTAVFS_REG86', 'ixRTAVFS_REG87',
|
|
'ixRTAVFS_REG88', 'ixRTAVFS_REG89', 'ixRTAVFS_REG9',
|
|
'ixRTAVFS_REG90', 'ixRTAVFS_REG91', 'ixRTAVFS_REG92',
|
|
'ixRTAVFS_REG93', 'ixRTAVFS_REG94', 'ixRTAVFS_REG95',
|
|
'ixRTAVFS_REG96', 'ixRTAVFS_REG97', 'ixRTAVFS_REG98',
|
|
'ixRTAVFS_REG99', 'ixSE_CAC_CNTL', 'ixSE_CAC_ID',
|
|
'ixSQ_DEBUG_CTRL_LOCAL', 'ixSQ_DEBUG_STS_LOCAL',
|
|
'ixSQ_WAVE_ACTIVE', 'ixSQ_WAVE_EXEC_HI', 'ixSQ_WAVE_EXEC_LO',
|
|
'ixSQ_WAVE_FLAT_SCRATCH_HI', 'ixSQ_WAVE_FLAT_SCRATCH_LO',
|
|
'ixSQ_WAVE_FLUSH_IB', 'ixSQ_WAVE_GPR_ALLOC', 'ixSQ_WAVE_HW_ID1',
|
|
'ixSQ_WAVE_HW_ID2', 'ixSQ_WAVE_IB_DBG1', 'ixSQ_WAVE_IB_STS',
|
|
'ixSQ_WAVE_IB_STS2', 'ixSQ_WAVE_LDS_ALLOC', 'ixSQ_WAVE_M0',
|
|
'ixSQ_WAVE_MODE', 'ixSQ_WAVE_PC_HI', 'ixSQ_WAVE_PC_LO',
|
|
'ixSQ_WAVE_POPS_PACKER', 'ixSQ_WAVE_SCHED_MODE',
|
|
'ixSQ_WAVE_SHADER_CYCLES', 'ixSQ_WAVE_STATUS',
|
|
'ixSQ_WAVE_TRAPSTS', 'ixSQ_WAVE_TTMP0', 'ixSQ_WAVE_TTMP1',
|
|
'ixSQ_WAVE_TTMP10', 'ixSQ_WAVE_TTMP11', 'ixSQ_WAVE_TTMP12',
|
|
'ixSQ_WAVE_TTMP13', 'ixSQ_WAVE_TTMP14', 'ixSQ_WAVE_TTMP15',
|
|
'ixSQ_WAVE_TTMP3', 'ixSQ_WAVE_TTMP4', 'ixSQ_WAVE_TTMP5',
|
|
'ixSQ_WAVE_TTMP6', 'ixSQ_WAVE_TTMP7', 'ixSQ_WAVE_TTMP8',
|
|
'ixSQ_WAVE_TTMP9', 'ixSQ_WAVE_VALID_AND_IDLE',
|
|
'ixSTALL_TO_PWRBRK_LUT_1_4', 'ixSTALL_TO_PWRBRK_LUT_5_7',
|
|
'ixSTALL_TO_RELEASE_LUT_1_4', 'ixSTALL_TO_RELEASE_LUT_5_7',
|
|
'regCB_BLEND0_CONTROL', 'regCB_BLEND0_CONTROL_BASE_IDX',
|
|
'regCB_BLEND1_CONTROL', 'regCB_BLEND1_CONTROL_BASE_IDX',
|
|
'regCB_BLEND2_CONTROL', 'regCB_BLEND2_CONTROL_BASE_IDX',
|
|
'regCB_BLEND3_CONTROL', 'regCB_BLEND3_CONTROL_BASE_IDX',
|
|
'regCB_BLEND4_CONTROL', 'regCB_BLEND4_CONTROL_BASE_IDX',
|
|
'regCB_BLEND5_CONTROL', 'regCB_BLEND5_CONTROL_BASE_IDX',
|
|
'regCB_BLEND6_CONTROL', 'regCB_BLEND6_CONTROL_BASE_IDX',
|
|
'regCB_BLEND7_CONTROL', 'regCB_BLEND7_CONTROL_BASE_IDX',
|
|
'regCB_BLEND_ALPHA', 'regCB_BLEND_ALPHA_BASE_IDX',
|
|
'regCB_BLEND_BLUE', 'regCB_BLEND_BLUE_BASE_IDX',
|
|
'regCB_BLEND_GREEN', 'regCB_BLEND_GREEN_BASE_IDX',
|
|
'regCB_BLEND_RED', 'regCB_BLEND_RED_BASE_IDX',
|
|
'regCB_CACHE_EVICT_POINTS', 'regCB_CACHE_EVICT_POINTS_BASE_IDX',
|
|
'regCB_CGTT_SCLK_CTRL', 'regCB_CGTT_SCLK_CTRL_BASE_IDX',
|
|
'regCB_COLOR0_ATTRIB', 'regCB_COLOR0_ATTRIB2',
|
|
'regCB_COLOR0_ATTRIB2_BASE_IDX', 'regCB_COLOR0_ATTRIB3',
|
|
'regCB_COLOR0_ATTRIB3_BASE_IDX', 'regCB_COLOR0_ATTRIB_BASE_IDX',
|
|
'regCB_COLOR0_BASE', 'regCB_COLOR0_BASE_BASE_IDX',
|
|
'regCB_COLOR0_BASE_EXT', 'regCB_COLOR0_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR0_DCC_BASE', 'regCB_COLOR0_DCC_BASE_BASE_IDX',
|
|
'regCB_COLOR0_DCC_BASE_EXT', 'regCB_COLOR0_DCC_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR0_FDCC_CONTROL', 'regCB_COLOR0_FDCC_CONTROL_BASE_IDX',
|
|
'regCB_COLOR0_INFO', 'regCB_COLOR0_INFO_BASE_IDX',
|
|
'regCB_COLOR0_VIEW', 'regCB_COLOR0_VIEW_BASE_IDX',
|
|
'regCB_COLOR1_ATTRIB', 'regCB_COLOR1_ATTRIB2',
|
|
'regCB_COLOR1_ATTRIB2_BASE_IDX', 'regCB_COLOR1_ATTRIB3',
|
|
'regCB_COLOR1_ATTRIB3_BASE_IDX', 'regCB_COLOR1_ATTRIB_BASE_IDX',
|
|
'regCB_COLOR1_BASE', 'regCB_COLOR1_BASE_BASE_IDX',
|
|
'regCB_COLOR1_BASE_EXT', 'regCB_COLOR1_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR1_DCC_BASE', 'regCB_COLOR1_DCC_BASE_BASE_IDX',
|
|
'regCB_COLOR1_DCC_BASE_EXT', 'regCB_COLOR1_DCC_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR1_FDCC_CONTROL', 'regCB_COLOR1_FDCC_CONTROL_BASE_IDX',
|
|
'regCB_COLOR1_INFO', 'regCB_COLOR1_INFO_BASE_IDX',
|
|
'regCB_COLOR1_VIEW', 'regCB_COLOR1_VIEW_BASE_IDX',
|
|
'regCB_COLOR2_ATTRIB', 'regCB_COLOR2_ATTRIB2',
|
|
'regCB_COLOR2_ATTRIB2_BASE_IDX', 'regCB_COLOR2_ATTRIB3',
|
|
'regCB_COLOR2_ATTRIB3_BASE_IDX', 'regCB_COLOR2_ATTRIB_BASE_IDX',
|
|
'regCB_COLOR2_BASE', 'regCB_COLOR2_BASE_BASE_IDX',
|
|
'regCB_COLOR2_BASE_EXT', 'regCB_COLOR2_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR2_DCC_BASE', 'regCB_COLOR2_DCC_BASE_BASE_IDX',
|
|
'regCB_COLOR2_DCC_BASE_EXT', 'regCB_COLOR2_DCC_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR2_FDCC_CONTROL', 'regCB_COLOR2_FDCC_CONTROL_BASE_IDX',
|
|
'regCB_COLOR2_INFO', 'regCB_COLOR2_INFO_BASE_IDX',
|
|
'regCB_COLOR2_VIEW', 'regCB_COLOR2_VIEW_BASE_IDX',
|
|
'regCB_COLOR3_ATTRIB', 'regCB_COLOR3_ATTRIB2',
|
|
'regCB_COLOR3_ATTRIB2_BASE_IDX', 'regCB_COLOR3_ATTRIB3',
|
|
'regCB_COLOR3_ATTRIB3_BASE_IDX', 'regCB_COLOR3_ATTRIB_BASE_IDX',
|
|
'regCB_COLOR3_BASE', 'regCB_COLOR3_BASE_BASE_IDX',
|
|
'regCB_COLOR3_BASE_EXT', 'regCB_COLOR3_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR3_DCC_BASE', 'regCB_COLOR3_DCC_BASE_BASE_IDX',
|
|
'regCB_COLOR3_DCC_BASE_EXT', 'regCB_COLOR3_DCC_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR3_FDCC_CONTROL', 'regCB_COLOR3_FDCC_CONTROL_BASE_IDX',
|
|
'regCB_COLOR3_INFO', 'regCB_COLOR3_INFO_BASE_IDX',
|
|
'regCB_COLOR3_VIEW', 'regCB_COLOR3_VIEW_BASE_IDX',
|
|
'regCB_COLOR4_ATTRIB', 'regCB_COLOR4_ATTRIB2',
|
|
'regCB_COLOR4_ATTRIB2_BASE_IDX', 'regCB_COLOR4_ATTRIB3',
|
|
'regCB_COLOR4_ATTRIB3_BASE_IDX', 'regCB_COLOR4_ATTRIB_BASE_IDX',
|
|
'regCB_COLOR4_BASE', 'regCB_COLOR4_BASE_BASE_IDX',
|
|
'regCB_COLOR4_BASE_EXT', 'regCB_COLOR4_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR4_DCC_BASE', 'regCB_COLOR4_DCC_BASE_BASE_IDX',
|
|
'regCB_COLOR4_DCC_BASE_EXT', 'regCB_COLOR4_DCC_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR4_FDCC_CONTROL', 'regCB_COLOR4_FDCC_CONTROL_BASE_IDX',
|
|
'regCB_COLOR4_INFO', 'regCB_COLOR4_INFO_BASE_IDX',
|
|
'regCB_COLOR4_VIEW', 'regCB_COLOR4_VIEW_BASE_IDX',
|
|
'regCB_COLOR5_ATTRIB', 'regCB_COLOR5_ATTRIB2',
|
|
'regCB_COLOR5_ATTRIB2_BASE_IDX', 'regCB_COLOR5_ATTRIB3',
|
|
'regCB_COLOR5_ATTRIB3_BASE_IDX', 'regCB_COLOR5_ATTRIB_BASE_IDX',
|
|
'regCB_COLOR5_BASE', 'regCB_COLOR5_BASE_BASE_IDX',
|
|
'regCB_COLOR5_BASE_EXT', 'regCB_COLOR5_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR5_DCC_BASE', 'regCB_COLOR5_DCC_BASE_BASE_IDX',
|
|
'regCB_COLOR5_DCC_BASE_EXT', 'regCB_COLOR5_DCC_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR5_FDCC_CONTROL', 'regCB_COLOR5_FDCC_CONTROL_BASE_IDX',
|
|
'regCB_COLOR5_INFO', 'regCB_COLOR5_INFO_BASE_IDX',
|
|
'regCB_COLOR5_VIEW', 'regCB_COLOR5_VIEW_BASE_IDX',
|
|
'regCB_COLOR6_ATTRIB', 'regCB_COLOR6_ATTRIB2',
|
|
'regCB_COLOR6_ATTRIB2_BASE_IDX', 'regCB_COLOR6_ATTRIB3',
|
|
'regCB_COLOR6_ATTRIB3_BASE_IDX', 'regCB_COLOR6_ATTRIB_BASE_IDX',
|
|
'regCB_COLOR6_BASE', 'regCB_COLOR6_BASE_BASE_IDX',
|
|
'regCB_COLOR6_BASE_EXT', 'regCB_COLOR6_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR6_DCC_BASE', 'regCB_COLOR6_DCC_BASE_BASE_IDX',
|
|
'regCB_COLOR6_DCC_BASE_EXT', 'regCB_COLOR6_DCC_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR6_FDCC_CONTROL', 'regCB_COLOR6_FDCC_CONTROL_BASE_IDX',
|
|
'regCB_COLOR6_INFO', 'regCB_COLOR6_INFO_BASE_IDX',
|
|
'regCB_COLOR6_VIEW', 'regCB_COLOR6_VIEW_BASE_IDX',
|
|
'regCB_COLOR7_ATTRIB', 'regCB_COLOR7_ATTRIB2',
|
|
'regCB_COLOR7_ATTRIB2_BASE_IDX', 'regCB_COLOR7_ATTRIB3',
|
|
'regCB_COLOR7_ATTRIB3_BASE_IDX', 'regCB_COLOR7_ATTRIB_BASE_IDX',
|
|
'regCB_COLOR7_BASE', 'regCB_COLOR7_BASE_BASE_IDX',
|
|
'regCB_COLOR7_BASE_EXT', 'regCB_COLOR7_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR7_DCC_BASE', 'regCB_COLOR7_DCC_BASE_BASE_IDX',
|
|
'regCB_COLOR7_DCC_BASE_EXT', 'regCB_COLOR7_DCC_BASE_EXT_BASE_IDX',
|
|
'regCB_COLOR7_FDCC_CONTROL', 'regCB_COLOR7_FDCC_CONTROL_BASE_IDX',
|
|
'regCB_COLOR7_INFO', 'regCB_COLOR7_INFO_BASE_IDX',
|
|
'regCB_COLOR7_VIEW', 'regCB_COLOR7_VIEW_BASE_IDX',
|
|
'regCB_COLOR_CONTROL', 'regCB_COLOR_CONTROL_BASE_IDX',
|
|
'regCB_COVERAGE_OUT_CONTROL',
|
|
'regCB_COVERAGE_OUT_CONTROL_BASE_IDX', 'regCB_DCC_CONFIG',
|
|
'regCB_DCC_CONFIG2', 'regCB_DCC_CONFIG2_BASE_IDX',
|
|
'regCB_DCC_CONFIG_BASE_IDX', 'regCB_FDCC_CONTROL',
|
|
'regCB_FDCC_CONTROL_BASE_IDX', 'regCB_FGCG_SRAM_OVERRIDE',
|
|
'regCB_FGCG_SRAM_OVERRIDE_BASE_IDX', 'regCB_HW_CONTROL',
|
|
'regCB_HW_CONTROL_1', 'regCB_HW_CONTROL_1_BASE_IDX',
|
|
'regCB_HW_CONTROL_2', 'regCB_HW_CONTROL_2_BASE_IDX',
|
|
'regCB_HW_CONTROL_3', 'regCB_HW_CONTROL_3_BASE_IDX',
|
|
'regCB_HW_CONTROL_4', 'regCB_HW_CONTROL_4_BASE_IDX',
|
|
'regCB_HW_CONTROL_BASE_IDX', 'regCB_HW_MEM_ARBITER_RD',
|
|
'regCB_HW_MEM_ARBITER_RD_BASE_IDX', 'regCB_HW_MEM_ARBITER_WR',
|
|
'regCB_HW_MEM_ARBITER_WR_BASE_IDX', 'regCB_PERFCOUNTER0_HI',
|
|
'regCB_PERFCOUNTER0_HI_BASE_IDX', 'regCB_PERFCOUNTER0_LO',
|
|
'regCB_PERFCOUNTER0_LO_BASE_IDX', 'regCB_PERFCOUNTER0_SELECT',
|
|
'regCB_PERFCOUNTER0_SELECT1',
|
|
'regCB_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regCB_PERFCOUNTER0_SELECT_BASE_IDX', 'regCB_PERFCOUNTER1_HI',
|
|
'regCB_PERFCOUNTER1_HI_BASE_IDX', 'regCB_PERFCOUNTER1_LO',
|
|
'regCB_PERFCOUNTER1_LO_BASE_IDX', 'regCB_PERFCOUNTER1_SELECT',
|
|
'regCB_PERFCOUNTER1_SELECT_BASE_IDX', 'regCB_PERFCOUNTER2_HI',
|
|
'regCB_PERFCOUNTER2_HI_BASE_IDX', 'regCB_PERFCOUNTER2_LO',
|
|
'regCB_PERFCOUNTER2_LO_BASE_IDX', 'regCB_PERFCOUNTER2_SELECT',
|
|
'regCB_PERFCOUNTER2_SELECT_BASE_IDX', 'regCB_PERFCOUNTER3_HI',
|
|
'regCB_PERFCOUNTER3_HI_BASE_IDX', 'regCB_PERFCOUNTER3_LO',
|
|
'regCB_PERFCOUNTER3_LO_BASE_IDX', 'regCB_PERFCOUNTER3_SELECT',
|
|
'regCB_PERFCOUNTER3_SELECT_BASE_IDX', 'regCB_PERFCOUNTER_FILTER',
|
|
'regCB_PERFCOUNTER_FILTER_BASE_IDX',
|
|
'regCB_RMI_GL2_CACHE_CONTROL',
|
|
'regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX', 'regCB_SHADER_MASK',
|
|
'regCB_SHADER_MASK_BASE_IDX', 'regCB_TARGET_MASK',
|
|
'regCB_TARGET_MASK_BASE_IDX', 'regCC_GC_EDC_CONFIG',
|
|
'regCC_GC_EDC_CONFIG_BASE_IDX', 'regCC_GC_PRIM_CONFIG',
|
|
'regCC_GC_PRIM_CONFIG_BASE_IDX', 'regCC_GC_SA_UNIT_DISABLE',
|
|
'regCC_GC_SA_UNIT_DISABLE_BASE_IDX',
|
|
'regCC_GC_SHADER_ARRAY_CONFIG',
|
|
'regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX',
|
|
'regCC_GC_SHADER_RATE_CONFIG',
|
|
'regCC_GC_SHADER_RATE_CONFIG_BASE_IDX',
|
|
'regCC_RB_BACKEND_DISABLE', 'regCC_RB_BACKEND_DISABLE_BASE_IDX',
|
|
'regCC_RB_DAISY_CHAIN', 'regCC_RB_DAISY_CHAIN_BASE_IDX',
|
|
'regCC_RB_REDUNDANCY', 'regCC_RB_REDUNDANCY_BASE_IDX',
|
|
'regCC_RMI_REDUNDANCY', 'regCC_RMI_REDUNDANCY_BASE_IDX',
|
|
'regCGTS_TCC_DISABLE', 'regCGTS_TCC_DISABLE_BASE_IDX',
|
|
'regCGTS_USER_TCC_DISABLE', 'regCGTS_USER_TCC_DISABLE_BASE_IDX',
|
|
'regCGTT_CPC_CLK_CTRL', 'regCGTT_CPC_CLK_CTRL_BASE_IDX',
|
|
'regCGTT_CPF_CLK_CTRL', 'regCGTT_CPF_CLK_CTRL_BASE_IDX',
|
|
'regCGTT_CP_CLK_CTRL', 'regCGTT_CP_CLK_CTRL_BASE_IDX',
|
|
'regCGTT_GS_NGG_CLK_CTRL', 'regCGTT_GS_NGG_CLK_CTRL_BASE_IDX',
|
|
'regCGTT_PA_CLK_CTRL', 'regCGTT_PA_CLK_CTRL_BASE_IDX',
|
|
'regCGTT_PH_CLK_CTRL0', 'regCGTT_PH_CLK_CTRL0_BASE_IDX',
|
|
'regCGTT_PH_CLK_CTRL1', 'regCGTT_PH_CLK_CTRL1_BASE_IDX',
|
|
'regCGTT_PH_CLK_CTRL2', 'regCGTT_PH_CLK_CTRL2_BASE_IDX',
|
|
'regCGTT_PH_CLK_CTRL3', 'regCGTT_PH_CLK_CTRL3_BASE_IDX',
|
|
'regCGTT_RLC_CLK_CTRL', 'regCGTT_RLC_CLK_CTRL_BASE_IDX',
|
|
'regCGTT_SC_CLK_CTRL0', 'regCGTT_SC_CLK_CTRL0_BASE_IDX',
|
|
'regCGTT_SC_CLK_CTRL1', 'regCGTT_SC_CLK_CTRL1_BASE_IDX',
|
|
'regCGTT_SC_CLK_CTRL2', 'regCGTT_SC_CLK_CTRL2_BASE_IDX',
|
|
'regCGTT_SC_CLK_CTRL3', 'regCGTT_SC_CLK_CTRL3_BASE_IDX',
|
|
'regCGTT_SC_CLK_CTRL4', 'regCGTT_SC_CLK_CTRL4_BASE_IDX',
|
|
'regCGTT_SQG_CLK_CTRL', 'regCGTT_SQG_CLK_CTRL_BASE_IDX',
|
|
'regCHA_CHC_CREDITS', 'regCHA_CHC_CREDITS_BASE_IDX',
|
|
'regCHA_CLIENT_FREE_DELAY', 'regCHA_CLIENT_FREE_DELAY_BASE_IDX',
|
|
'regCHA_PERFCOUNTER0_HI', 'regCHA_PERFCOUNTER0_HI_BASE_IDX',
|
|
'regCHA_PERFCOUNTER0_LO', 'regCHA_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regCHA_PERFCOUNTER0_SELECT', 'regCHA_PERFCOUNTER0_SELECT1',
|
|
'regCHA_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regCHA_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER1_HI',
|
|
'regCHA_PERFCOUNTER1_HI_BASE_IDX', 'regCHA_PERFCOUNTER1_LO',
|
|
'regCHA_PERFCOUNTER1_LO_BASE_IDX', 'regCHA_PERFCOUNTER1_SELECT',
|
|
'regCHA_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER2_HI',
|
|
'regCHA_PERFCOUNTER2_HI_BASE_IDX', 'regCHA_PERFCOUNTER2_LO',
|
|
'regCHA_PERFCOUNTER2_LO_BASE_IDX', 'regCHA_PERFCOUNTER2_SELECT',
|
|
'regCHA_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER3_HI',
|
|
'regCHA_PERFCOUNTER3_HI_BASE_IDX', 'regCHA_PERFCOUNTER3_LO',
|
|
'regCHA_PERFCOUNTER3_LO_BASE_IDX', 'regCHA_PERFCOUNTER3_SELECT',
|
|
'regCHA_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHCG_CTRL',
|
|
'regCHCG_CTRL_BASE_IDX', 'regCHCG_PERFCOUNTER0_HI',
|
|
'regCHCG_PERFCOUNTER0_HI_BASE_IDX', 'regCHCG_PERFCOUNTER0_LO',
|
|
'regCHCG_PERFCOUNTER0_LO_BASE_IDX', 'regCHCG_PERFCOUNTER0_SELECT',
|
|
'regCHCG_PERFCOUNTER0_SELECT1',
|
|
'regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regCHCG_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER1_HI',
|
|
'regCHCG_PERFCOUNTER1_HI_BASE_IDX', 'regCHCG_PERFCOUNTER1_LO',
|
|
'regCHCG_PERFCOUNTER1_LO_BASE_IDX', 'regCHCG_PERFCOUNTER1_SELECT',
|
|
'regCHCG_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER2_HI',
|
|
'regCHCG_PERFCOUNTER2_HI_BASE_IDX', 'regCHCG_PERFCOUNTER2_LO',
|
|
'regCHCG_PERFCOUNTER2_LO_BASE_IDX', 'regCHCG_PERFCOUNTER2_SELECT',
|
|
'regCHCG_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER3_HI',
|
|
'regCHCG_PERFCOUNTER3_HI_BASE_IDX', 'regCHCG_PERFCOUNTER3_LO',
|
|
'regCHCG_PERFCOUNTER3_LO_BASE_IDX', 'regCHCG_PERFCOUNTER3_SELECT',
|
|
'regCHCG_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHCG_STATUS',
|
|
'regCHCG_STATUS_BASE_IDX', 'regCHC_CTRL', 'regCHC_CTRL_BASE_IDX',
|
|
'regCHC_PERFCOUNTER0_HI', 'regCHC_PERFCOUNTER0_HI_BASE_IDX',
|
|
'regCHC_PERFCOUNTER0_LO', 'regCHC_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regCHC_PERFCOUNTER0_SELECT', 'regCHC_PERFCOUNTER0_SELECT1',
|
|
'regCHC_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regCHC_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER1_HI',
|
|
'regCHC_PERFCOUNTER1_HI_BASE_IDX', 'regCHC_PERFCOUNTER1_LO',
|
|
'regCHC_PERFCOUNTER1_LO_BASE_IDX', 'regCHC_PERFCOUNTER1_SELECT',
|
|
'regCHC_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER2_HI',
|
|
'regCHC_PERFCOUNTER2_HI_BASE_IDX', 'regCHC_PERFCOUNTER2_LO',
|
|
'regCHC_PERFCOUNTER2_LO_BASE_IDX', 'regCHC_PERFCOUNTER2_SELECT',
|
|
'regCHC_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER3_HI',
|
|
'regCHC_PERFCOUNTER3_HI_BASE_IDX', 'regCHC_PERFCOUNTER3_LO',
|
|
'regCHC_PERFCOUNTER3_LO_BASE_IDX', 'regCHC_PERFCOUNTER3_SELECT',
|
|
'regCHC_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHC_STATUS',
|
|
'regCHC_STATUS_BASE_IDX', 'regCHICKEN_BITS',
|
|
'regCHICKEN_BITS_BASE_IDX', 'regCHI_CHR_MGCG_OVERRIDE',
|
|
'regCHI_CHR_MGCG_OVERRIDE_BASE_IDX',
|
|
'regCHI_CHR_REP_FGCG_OVERRIDE',
|
|
'regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX', 'regCH_ARB_CTRL',
|
|
'regCH_ARB_CTRL_BASE_IDX', 'regCH_ARB_STATUS',
|
|
'regCH_ARB_STATUS_BASE_IDX', 'regCH_DRAM_BURST_CTRL',
|
|
'regCH_DRAM_BURST_CTRL_BASE_IDX', 'regCH_DRAM_BURST_MASK',
|
|
'regCH_DRAM_BURST_MASK_BASE_IDX', 'regCH_PIPE_STEER',
|
|
'regCH_PIPE_STEER_BASE_IDX', 'regCH_VC5_ENABLE',
|
|
'regCH_VC5_ENABLE_BASE_IDX', 'regCOHER_DEST_BASE_0',
|
|
'regCOHER_DEST_BASE_0_BASE_IDX', 'regCOHER_DEST_BASE_1',
|
|
'regCOHER_DEST_BASE_1_BASE_IDX', 'regCOHER_DEST_BASE_2',
|
|
'regCOHER_DEST_BASE_2_BASE_IDX', 'regCOHER_DEST_BASE_3',
|
|
'regCOHER_DEST_BASE_3_BASE_IDX', 'regCOHER_DEST_BASE_HI_0',
|
|
'regCOHER_DEST_BASE_HI_0_BASE_IDX', 'regCOHER_DEST_BASE_HI_1',
|
|
'regCOHER_DEST_BASE_HI_1_BASE_IDX', 'regCOHER_DEST_BASE_HI_2',
|
|
'regCOHER_DEST_BASE_HI_2_BASE_IDX', 'regCOHER_DEST_BASE_HI_3',
|
|
'regCOHER_DEST_BASE_HI_3_BASE_IDX', 'regCOMPUTE_DDID_INDEX',
|
|
'regCOMPUTE_DDID_INDEX_BASE_IDX', 'regCOMPUTE_DESTINATION_EN_SE0',
|
|
'regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX',
|
|
'regCOMPUTE_DESTINATION_EN_SE1',
|
|
'regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX',
|
|
'regCOMPUTE_DESTINATION_EN_SE2',
|
|
'regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX',
|
|
'regCOMPUTE_DESTINATION_EN_SE3',
|
|
'regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX', 'regCOMPUTE_DIM_X',
|
|
'regCOMPUTE_DIM_X_BASE_IDX', 'regCOMPUTE_DIM_Y',
|
|
'regCOMPUTE_DIM_Y_BASE_IDX', 'regCOMPUTE_DIM_Z',
|
|
'regCOMPUTE_DIM_Z_BASE_IDX', 'regCOMPUTE_DISPATCH_END',
|
|
'regCOMPUTE_DISPATCH_END_BASE_IDX', 'regCOMPUTE_DISPATCH_ID',
|
|
'regCOMPUTE_DISPATCH_ID_BASE_IDX',
|
|
'regCOMPUTE_DISPATCH_INITIATOR',
|
|
'regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX',
|
|
'regCOMPUTE_DISPATCH_INTERLEAVE',
|
|
'regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX',
|
|
'regCOMPUTE_DISPATCH_PKT_ADDR_HI',
|
|
'regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX',
|
|
'regCOMPUTE_DISPATCH_PKT_ADDR_LO',
|
|
'regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX',
|
|
'regCOMPUTE_DISPATCH_SCRATCH_BASE_HI',
|
|
'regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX',
|
|
'regCOMPUTE_DISPATCH_SCRATCH_BASE_LO',
|
|
'regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX',
|
|
'regCOMPUTE_DISPATCH_TUNNEL',
|
|
'regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX', 'regCOMPUTE_MISC_RESERVED',
|
|
'regCOMPUTE_MISC_RESERVED_BASE_IDX', 'regCOMPUTE_NOWHERE',
|
|
'regCOMPUTE_NOWHERE_BASE_IDX', 'regCOMPUTE_NUM_THREAD_X',
|
|
'regCOMPUTE_NUM_THREAD_X_BASE_IDX', 'regCOMPUTE_NUM_THREAD_Y',
|
|
'regCOMPUTE_NUM_THREAD_Y_BASE_IDX', 'regCOMPUTE_NUM_THREAD_Z',
|
|
'regCOMPUTE_NUM_THREAD_Z_BASE_IDX', 'regCOMPUTE_PERFCOUNT_ENABLE',
|
|
'regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX', 'regCOMPUTE_PGM_HI',
|
|
'regCOMPUTE_PGM_HI_BASE_IDX', 'regCOMPUTE_PGM_LO',
|
|
'regCOMPUTE_PGM_LO_BASE_IDX', 'regCOMPUTE_PGM_RSRC1',
|
|
'regCOMPUTE_PGM_RSRC1_BASE_IDX', 'regCOMPUTE_PGM_RSRC2',
|
|
'regCOMPUTE_PGM_RSRC2_BASE_IDX', 'regCOMPUTE_PGM_RSRC3',
|
|
'regCOMPUTE_PGM_RSRC3_BASE_IDX', 'regCOMPUTE_PIPELINESTAT_ENABLE',
|
|
'regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX', 'regCOMPUTE_RELAUNCH',
|
|
'regCOMPUTE_RELAUNCH2', 'regCOMPUTE_RELAUNCH2_BASE_IDX',
|
|
'regCOMPUTE_RELAUNCH_BASE_IDX', 'regCOMPUTE_REQ_CTRL',
|
|
'regCOMPUTE_REQ_CTRL_BASE_IDX', 'regCOMPUTE_RESOURCE_LIMITS',
|
|
'regCOMPUTE_RESOURCE_LIMITS_BASE_IDX', 'regCOMPUTE_RESTART_X',
|
|
'regCOMPUTE_RESTART_X_BASE_IDX', 'regCOMPUTE_RESTART_Y',
|
|
'regCOMPUTE_RESTART_Y_BASE_IDX', 'regCOMPUTE_RESTART_Z',
|
|
'regCOMPUTE_RESTART_Z_BASE_IDX', 'regCOMPUTE_SHADER_CHKSUM',
|
|
'regCOMPUTE_SHADER_CHKSUM_BASE_IDX', 'regCOMPUTE_START_X',
|
|
'regCOMPUTE_START_X_BASE_IDX', 'regCOMPUTE_START_Y',
|
|
'regCOMPUTE_START_Y_BASE_IDX', 'regCOMPUTE_START_Z',
|
|
'regCOMPUTE_START_Z_BASE_IDX',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE0',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE1',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE2',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE3',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE4',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE5',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE6',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE7',
|
|
'regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX',
|
|
'regCOMPUTE_THREADGROUP_ID', 'regCOMPUTE_THREADGROUP_ID_BASE_IDX',
|
|
'regCOMPUTE_THREAD_TRACE_ENABLE',
|
|
'regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX',
|
|
'regCOMPUTE_TMPRING_SIZE', 'regCOMPUTE_TMPRING_SIZE_BASE_IDX',
|
|
'regCOMPUTE_USER_ACCUM_0', 'regCOMPUTE_USER_ACCUM_0_BASE_IDX',
|
|
'regCOMPUTE_USER_ACCUM_1', 'regCOMPUTE_USER_ACCUM_1_BASE_IDX',
|
|
'regCOMPUTE_USER_ACCUM_2', 'regCOMPUTE_USER_ACCUM_2_BASE_IDX',
|
|
'regCOMPUTE_USER_ACCUM_3', 'regCOMPUTE_USER_ACCUM_3_BASE_IDX',
|
|
'regCOMPUTE_USER_DATA_0', 'regCOMPUTE_USER_DATA_0_BASE_IDX',
|
|
'regCOMPUTE_USER_DATA_1', 'regCOMPUTE_USER_DATA_10',
|
|
'regCOMPUTE_USER_DATA_10_BASE_IDX', 'regCOMPUTE_USER_DATA_11',
|
|
'regCOMPUTE_USER_DATA_11_BASE_IDX', 'regCOMPUTE_USER_DATA_12',
|
|
'regCOMPUTE_USER_DATA_12_BASE_IDX', 'regCOMPUTE_USER_DATA_13',
|
|
'regCOMPUTE_USER_DATA_13_BASE_IDX', 'regCOMPUTE_USER_DATA_14',
|
|
'regCOMPUTE_USER_DATA_14_BASE_IDX', 'regCOMPUTE_USER_DATA_15',
|
|
'regCOMPUTE_USER_DATA_15_BASE_IDX',
|
|
'regCOMPUTE_USER_DATA_1_BASE_IDX', 'regCOMPUTE_USER_DATA_2',
|
|
'regCOMPUTE_USER_DATA_2_BASE_IDX', 'regCOMPUTE_USER_DATA_3',
|
|
'regCOMPUTE_USER_DATA_3_BASE_IDX', 'regCOMPUTE_USER_DATA_4',
|
|
'regCOMPUTE_USER_DATA_4_BASE_IDX', 'regCOMPUTE_USER_DATA_5',
|
|
'regCOMPUTE_USER_DATA_5_BASE_IDX', 'regCOMPUTE_USER_DATA_6',
|
|
'regCOMPUTE_USER_DATA_6_BASE_IDX', 'regCOMPUTE_USER_DATA_7',
|
|
'regCOMPUTE_USER_DATA_7_BASE_IDX', 'regCOMPUTE_USER_DATA_8',
|
|
'regCOMPUTE_USER_DATA_8_BASE_IDX', 'regCOMPUTE_USER_DATA_9',
|
|
'regCOMPUTE_USER_DATA_9_BASE_IDX', 'regCOMPUTE_VMID',
|
|
'regCOMPUTE_VMID_BASE_IDX', 'regCOMPUTE_WAVE_RESTORE_ADDR_HI',
|
|
'regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX',
|
|
'regCOMPUTE_WAVE_RESTORE_ADDR_LO',
|
|
'regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX',
|
|
'regCONFIG_RESERVED_REG0', 'regCONFIG_RESERVED_REG0_BASE_IDX',
|
|
'regCONFIG_RESERVED_REG1', 'regCONFIG_RESERVED_REG1_BASE_IDX',
|
|
'regCONTEXT_RESERVED_REG0', 'regCONTEXT_RESERVED_REG0_BASE_IDX',
|
|
'regCONTEXT_RESERVED_REG1', 'regCONTEXT_RESERVED_REG1_BASE_IDX',
|
|
'regCPC_DDID_BASE_ADDR_HI', 'regCPC_DDID_BASE_ADDR_HI_BASE_IDX',
|
|
'regCPC_DDID_BASE_ADDR_LO', 'regCPC_DDID_BASE_ADDR_LO_BASE_IDX',
|
|
'regCPC_DDID_CNTL', 'regCPC_DDID_CNTL_BASE_IDX',
|
|
'regCPC_INT_ADDR', 'regCPC_INT_ADDR_BASE_IDX', 'regCPC_INT_CNTL',
|
|
'regCPC_INT_CNTL_BASE_IDX', 'regCPC_INT_CNTX_ID',
|
|
'regCPC_INT_CNTX_ID_BASE_IDX', 'regCPC_INT_INFO',
|
|
'regCPC_INT_INFO_BASE_IDX', 'regCPC_INT_PASID',
|
|
'regCPC_INT_PASID_BASE_IDX', 'regCPC_INT_STATUS',
|
|
'regCPC_INT_STATUS_BASE_IDX', 'regCPC_LATENCY_STATS_DATA',
|
|
'regCPC_LATENCY_STATS_DATA_BASE_IDX',
|
|
'regCPC_LATENCY_STATS_SELECT',
|
|
'regCPC_LATENCY_STATS_SELECT_BASE_IDX', 'regCPC_OS_PIPES',
|
|
'regCPC_OS_PIPES_BASE_IDX', 'regCPC_PERFCOUNTER0_HI',
|
|
'regCPC_PERFCOUNTER0_HI_BASE_IDX', 'regCPC_PERFCOUNTER0_LO',
|
|
'regCPC_PERFCOUNTER0_LO_BASE_IDX', 'regCPC_PERFCOUNTER0_SELECT',
|
|
'regCPC_PERFCOUNTER0_SELECT1',
|
|
'regCPC_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regCPC_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPC_PERFCOUNTER1_HI',
|
|
'regCPC_PERFCOUNTER1_HI_BASE_IDX', 'regCPC_PERFCOUNTER1_LO',
|
|
'regCPC_PERFCOUNTER1_LO_BASE_IDX', 'regCPC_PERFCOUNTER1_SELECT',
|
|
'regCPC_PERFCOUNTER1_SELECT_BASE_IDX', 'regCPC_PSP_DEBUG',
|
|
'regCPC_PSP_DEBUG_BASE_IDX', 'regCPC_SUSPEND_CNTL_STACK_OFFSET',
|
|
'regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX',
|
|
'regCPC_SUSPEND_CNTL_STACK_SIZE',
|
|
'regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX',
|
|
'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI',
|
|
'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX',
|
|
'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO',
|
|
'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX',
|
|
'regCPC_SUSPEND_CTX_SAVE_CONTROL',
|
|
'regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX',
|
|
'regCPC_SUSPEND_CTX_SAVE_SIZE',
|
|
'regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX',
|
|
'regCPC_SUSPEND_WG_STATE_OFFSET',
|
|
'regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX',
|
|
'regCPC_TC_PERF_COUNTER_WINDOW_SELECT',
|
|
'regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX',
|
|
'regCPC_UTCL1_CNTL', 'regCPC_UTCL1_CNTL_BASE_IDX',
|
|
'regCPC_UTCL1_ERROR', 'regCPC_UTCL1_ERROR_BASE_IDX',
|
|
'regCPC_UTCL1_STATUS', 'regCPC_UTCL1_STATUS_BASE_IDX',
|
|
'regCPF_GCR_CNTL', 'regCPF_GCR_CNTL_BASE_IDX',
|
|
'regCPF_LATENCY_STATS_DATA', 'regCPF_LATENCY_STATS_DATA_BASE_IDX',
|
|
'regCPF_LATENCY_STATS_SELECT',
|
|
'regCPF_LATENCY_STATS_SELECT_BASE_IDX', 'regCPF_PERFCOUNTER0_HI',
|
|
'regCPF_PERFCOUNTER0_HI_BASE_IDX', 'regCPF_PERFCOUNTER0_LO',
|
|
'regCPF_PERFCOUNTER0_LO_BASE_IDX', 'regCPF_PERFCOUNTER0_SELECT',
|
|
'regCPF_PERFCOUNTER0_SELECT1',
|
|
'regCPF_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regCPF_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPF_PERFCOUNTER1_HI',
|
|
'regCPF_PERFCOUNTER1_HI_BASE_IDX', 'regCPF_PERFCOUNTER1_LO',
|
|
'regCPF_PERFCOUNTER1_LO_BASE_IDX', 'regCPF_PERFCOUNTER1_SELECT',
|
|
'regCPF_PERFCOUNTER1_SELECT_BASE_IDX',
|
|
'regCPF_TC_PERF_COUNTER_WINDOW_SELECT',
|
|
'regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX',
|
|
'regCPF_UTCL1_CNTL', 'regCPF_UTCL1_CNTL_BASE_IDX',
|
|
'regCPF_UTCL1_STATUS', 'regCPF_UTCL1_STATUS_BASE_IDX',
|
|
'regCPG_LATENCY_STATS_DATA', 'regCPG_LATENCY_STATS_DATA_BASE_IDX',
|
|
'regCPG_LATENCY_STATS_SELECT',
|
|
'regCPG_LATENCY_STATS_SELECT_BASE_IDX', 'regCPG_PERFCOUNTER0_HI',
|
|
'regCPG_PERFCOUNTER0_HI_BASE_IDX', 'regCPG_PERFCOUNTER0_LO',
|
|
'regCPG_PERFCOUNTER0_LO_BASE_IDX', 'regCPG_PERFCOUNTER0_SELECT',
|
|
'regCPG_PERFCOUNTER0_SELECT1',
|
|
'regCPG_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regCPG_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPG_PERFCOUNTER1_HI',
|
|
'regCPG_PERFCOUNTER1_HI_BASE_IDX', 'regCPG_PERFCOUNTER1_LO',
|
|
'regCPG_PERFCOUNTER1_LO_BASE_IDX', 'regCPG_PERFCOUNTER1_SELECT',
|
|
'regCPG_PERFCOUNTER1_SELECT_BASE_IDX', 'regCPG_PSP_DEBUG',
|
|
'regCPG_PSP_DEBUG_BASE_IDX', 'regCPG_RCIU_CAM_DATA',
|
|
'regCPG_RCIU_CAM_DATA_BASE_IDX', 'regCPG_RCIU_CAM_DATA_PHASE0',
|
|
'regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX',
|
|
'regCPG_RCIU_CAM_DATA_PHASE1',
|
|
'regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX',
|
|
'regCPG_RCIU_CAM_DATA_PHASE2',
|
|
'regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX', 'regCPG_RCIU_CAM_INDEX',
|
|
'regCPG_RCIU_CAM_INDEX_BASE_IDX',
|
|
'regCPG_TC_PERF_COUNTER_WINDOW_SELECT',
|
|
'regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX',
|
|
'regCPG_UTCL1_CNTL', 'regCPG_UTCL1_CNTL_BASE_IDX',
|
|
'regCPG_UTCL1_ERROR', 'regCPG_UTCL1_ERROR_BASE_IDX',
|
|
'regCPG_UTCL1_STATUS', 'regCPG_UTCL1_STATUS_BASE_IDX',
|
|
'regCP_APPEND_ADDR_HI', 'regCP_APPEND_ADDR_HI_BASE_IDX',
|
|
'regCP_APPEND_ADDR_LO', 'regCP_APPEND_ADDR_LO_BASE_IDX',
|
|
'regCP_APPEND_CMD_ADDR_HI', 'regCP_APPEND_CMD_ADDR_HI_BASE_IDX',
|
|
'regCP_APPEND_CMD_ADDR_LO', 'regCP_APPEND_CMD_ADDR_LO_BASE_IDX',
|
|
'regCP_APPEND_DATA', 'regCP_APPEND_DATA_BASE_IDX',
|
|
'regCP_APPEND_DATA_HI', 'regCP_APPEND_DATA_HI_BASE_IDX',
|
|
'regCP_APPEND_DATA_LO', 'regCP_APPEND_DATA_LO_BASE_IDX',
|
|
'regCP_APPEND_DDID_CNT', 'regCP_APPEND_DDID_CNT_BASE_IDX',
|
|
'regCP_APPEND_LAST_CS_FENCE',
|
|
'regCP_APPEND_LAST_CS_FENCE_BASE_IDX',
|
|
'regCP_APPEND_LAST_CS_FENCE_HI',
|
|
'regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX',
|
|
'regCP_APPEND_LAST_CS_FENCE_LO',
|
|
'regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX',
|
|
'regCP_APPEND_LAST_PS_FENCE',
|
|
'regCP_APPEND_LAST_PS_FENCE_BASE_IDX',
|
|
'regCP_APPEND_LAST_PS_FENCE_HI',
|
|
'regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX',
|
|
'regCP_APPEND_LAST_PS_FENCE_LO',
|
|
'regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX', 'regCP_AQL_SMM_STATUS',
|
|
'regCP_AQL_SMM_STATUS_BASE_IDX', 'regCP_ATOMIC_PREOP_HI',
|
|
'regCP_ATOMIC_PREOP_HI_BASE_IDX', 'regCP_ATOMIC_PREOP_LO',
|
|
'regCP_ATOMIC_PREOP_LO_BASE_IDX', 'regCP_BUSY_STAT',
|
|
'regCP_BUSY_STAT_BASE_IDX', 'regCP_CMD_DATA',
|
|
'regCP_CMD_DATA_BASE_IDX', 'regCP_CMD_INDEX',
|
|
'regCP_CMD_INDEX_BASE_IDX', 'regCP_CNTX_STAT',
|
|
'regCP_CNTX_STAT_BASE_IDX', 'regCP_CONTEXT_CNTL',
|
|
'regCP_CONTEXT_CNTL_BASE_IDX', 'regCP_CPC_BUSY_HYSTERESIS',
|
|
'regCP_CPC_BUSY_HYSTERESIS_BASE_IDX', 'regCP_CPC_BUSY_STAT',
|
|
'regCP_CPC_BUSY_STAT2', 'regCP_CPC_BUSY_STAT2_BASE_IDX',
|
|
'regCP_CPC_BUSY_STAT_BASE_IDX', 'regCP_CPC_DEBUG',
|
|
'regCP_CPC_DEBUG_BASE_IDX', 'regCP_CPC_DEBUG_CNTL',
|
|
'regCP_CPC_DEBUG_CNTL_BASE_IDX', 'regCP_CPC_DEBUG_DATA',
|
|
'regCP_CPC_DEBUG_DATA_BASE_IDX', 'regCP_CPC_GFX_CNTL',
|
|
'regCP_CPC_GFX_CNTL_BASE_IDX', 'regCP_CPC_GRBM_FREE_COUNT',
|
|
'regCP_CPC_GRBM_FREE_COUNT_BASE_IDX', 'regCP_CPC_HALT_HYST_COUNT',
|
|
'regCP_CPC_HALT_HYST_COUNT_BASE_IDX', 'regCP_CPC_IC_BASE_CNTL',
|
|
'regCP_CPC_IC_BASE_CNTL_BASE_IDX', 'regCP_CPC_IC_BASE_HI',
|
|
'regCP_CPC_IC_BASE_HI_BASE_IDX', 'regCP_CPC_IC_BASE_LO',
|
|
'regCP_CPC_IC_BASE_LO_BASE_IDX', 'regCP_CPC_IC_OP_CNTL',
|
|
'regCP_CPC_IC_OP_CNTL_BASE_IDX', 'regCP_CPC_MGCG_SYNC_CNTL',
|
|
'regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX',
|
|
'regCP_CPC_PRIV_VIOLATION_ADDR',
|
|
'regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX',
|
|
'regCP_CPC_SCRATCH_DATA', 'regCP_CPC_SCRATCH_DATA_BASE_IDX',
|
|
'regCP_CPC_SCRATCH_INDEX', 'regCP_CPC_SCRATCH_INDEX_BASE_IDX',
|
|
'regCP_CPC_STALLED_STAT1', 'regCP_CPC_STALLED_STAT1_BASE_IDX',
|
|
'regCP_CPC_STATUS', 'regCP_CPC_STATUS_BASE_IDX',
|
|
'regCP_CPF_BUSY_HYSTERESIS1',
|
|
'regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX',
|
|
'regCP_CPF_BUSY_HYSTERESIS2',
|
|
'regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX', 'regCP_CPF_BUSY_STAT',
|
|
'regCP_CPF_BUSY_STAT2', 'regCP_CPF_BUSY_STAT2_BASE_IDX',
|
|
'regCP_CPF_BUSY_STAT_BASE_IDX', 'regCP_CPF_GRBM_FREE_COUNT',
|
|
'regCP_CPF_GRBM_FREE_COUNT_BASE_IDX', 'regCP_CPF_STALLED_STAT1',
|
|
'regCP_CPF_STALLED_STAT1_BASE_IDX', 'regCP_CPF_STATUS',
|
|
'regCP_CPF_STATUS_BASE_IDX', 'regCP_CPG_BUSY_HYSTERESIS1',
|
|
'regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX',
|
|
'regCP_CPG_BUSY_HYSTERESIS2',
|
|
'regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX', 'regCP_CSF_STAT',
|
|
'regCP_CSF_STAT_BASE_IDX', 'regCP_CU_MASK_ADDR_HI',
|
|
'regCP_CU_MASK_ADDR_HI_BASE_IDX', 'regCP_CU_MASK_ADDR_LO',
|
|
'regCP_CU_MASK_ADDR_LO_BASE_IDX', 'regCP_CU_MASK_CNTL',
|
|
'regCP_CU_MASK_CNTL_BASE_IDX', 'regCP_DB_BASE_HI',
|
|
'regCP_DB_BASE_HI_BASE_IDX', 'regCP_DB_BASE_LO',
|
|
'regCP_DB_BASE_LO_BASE_IDX', 'regCP_DB_BUFSZ',
|
|
'regCP_DB_BUFSZ_BASE_IDX', 'regCP_DB_CMD_BUFSZ',
|
|
'regCP_DB_CMD_BUFSZ_BASE_IDX', 'regCP_DDID_BASE_ADDR_HI',
|
|
'regCP_DDID_BASE_ADDR_HI_BASE_IDX', 'regCP_DDID_BASE_ADDR_LO',
|
|
'regCP_DDID_BASE_ADDR_LO_BASE_IDX', 'regCP_DDID_CNTL',
|
|
'regCP_DDID_CNTL_BASE_IDX', 'regCP_DEBUG', 'regCP_DEBUG_2',
|
|
'regCP_DEBUG_2_BASE_IDX', 'regCP_DEBUG_BASE_IDX',
|
|
'regCP_DEBUG_CNTL', 'regCP_DEBUG_CNTL_BASE_IDX',
|
|
'regCP_DEBUG_DATA', 'regCP_DEBUG_DATA_BASE_IDX',
|
|
'regCP_DEVICE_ID', 'regCP_DEVICE_ID_BASE_IDX',
|
|
'regCP_DISPATCH_INDR_ADDR', 'regCP_DISPATCH_INDR_ADDR_BASE_IDX',
|
|
'regCP_DISPATCH_INDR_ADDR_HI',
|
|
'regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX', 'regCP_DMA_CNTL',
|
|
'regCP_DMA_CNTL_BASE_IDX', 'regCP_DMA_ME_CMD_ADDR_HI',
|
|
'regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX', 'regCP_DMA_ME_CMD_ADDR_LO',
|
|
'regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX', 'regCP_DMA_ME_COMMAND',
|
|
'regCP_DMA_ME_COMMAND_BASE_IDX', 'regCP_DMA_ME_CONTROL',
|
|
'regCP_DMA_ME_CONTROL_BASE_IDX', 'regCP_DMA_ME_DST_ADDR',
|
|
'regCP_DMA_ME_DST_ADDR_BASE_IDX', 'regCP_DMA_ME_DST_ADDR_HI',
|
|
'regCP_DMA_ME_DST_ADDR_HI_BASE_IDX', 'regCP_DMA_ME_SRC_ADDR',
|
|
'regCP_DMA_ME_SRC_ADDR_BASE_IDX', 'regCP_DMA_ME_SRC_ADDR_HI',
|
|
'regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_CMD_ADDR_HI',
|
|
'regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_CMD_ADDR_LO',
|
|
'regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX', 'regCP_DMA_PFP_COMMAND',
|
|
'regCP_DMA_PFP_COMMAND_BASE_IDX', 'regCP_DMA_PFP_CONTROL',
|
|
'regCP_DMA_PFP_CONTROL_BASE_IDX', 'regCP_DMA_PFP_DST_ADDR',
|
|
'regCP_DMA_PFP_DST_ADDR_BASE_IDX', 'regCP_DMA_PFP_DST_ADDR_HI',
|
|
'regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_SRC_ADDR',
|
|
'regCP_DMA_PFP_SRC_ADDR_BASE_IDX', 'regCP_DMA_PFP_SRC_ADDR_HI',
|
|
'regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX', 'regCP_DMA_READ_TAGS',
|
|
'regCP_DMA_READ_TAGS_BASE_IDX', 'regCP_DMA_WATCH0_ADDR_HI',
|
|
'regCP_DMA_WATCH0_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH0_ADDR_LO',
|
|
'regCP_DMA_WATCH0_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH0_CNTL',
|
|
'regCP_DMA_WATCH0_CNTL_BASE_IDX', 'regCP_DMA_WATCH0_MASK',
|
|
'regCP_DMA_WATCH0_MASK_BASE_IDX', 'regCP_DMA_WATCH1_ADDR_HI',
|
|
'regCP_DMA_WATCH1_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH1_ADDR_LO',
|
|
'regCP_DMA_WATCH1_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH1_CNTL',
|
|
'regCP_DMA_WATCH1_CNTL_BASE_IDX', 'regCP_DMA_WATCH1_MASK',
|
|
'regCP_DMA_WATCH1_MASK_BASE_IDX', 'regCP_DMA_WATCH2_ADDR_HI',
|
|
'regCP_DMA_WATCH2_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH2_ADDR_LO',
|
|
'regCP_DMA_WATCH2_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH2_CNTL',
|
|
'regCP_DMA_WATCH2_CNTL_BASE_IDX', 'regCP_DMA_WATCH2_MASK',
|
|
'regCP_DMA_WATCH2_MASK_BASE_IDX', 'regCP_DMA_WATCH3_ADDR_HI',
|
|
'regCP_DMA_WATCH3_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH3_ADDR_LO',
|
|
'regCP_DMA_WATCH3_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH3_CNTL',
|
|
'regCP_DMA_WATCH3_CNTL_BASE_IDX', 'regCP_DMA_WATCH3_MASK',
|
|
'regCP_DMA_WATCH3_MASK_BASE_IDX', 'regCP_DMA_WATCH_STAT',
|
|
'regCP_DMA_WATCH_STAT_ADDR_HI',
|
|
'regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX',
|
|
'regCP_DMA_WATCH_STAT_ADDR_LO',
|
|
'regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX',
|
|
'regCP_DMA_WATCH_STAT_BASE_IDX', 'regCP_DRAW_INDX_INDR_ADDR',
|
|
'regCP_DRAW_INDX_INDR_ADDR_BASE_IDX',
|
|
'regCP_DRAW_INDX_INDR_ADDR_HI',
|
|
'regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX', 'regCP_DRAW_OBJECT',
|
|
'regCP_DRAW_OBJECT_BASE_IDX', 'regCP_DRAW_OBJECT_COUNTER',
|
|
'regCP_DRAW_OBJECT_COUNTER_BASE_IDX', 'regCP_DRAW_WINDOW_CNTL',
|
|
'regCP_DRAW_WINDOW_CNTL_BASE_IDX', 'regCP_DRAW_WINDOW_HI',
|
|
'regCP_DRAW_WINDOW_HI_BASE_IDX', 'regCP_DRAW_WINDOW_LO',
|
|
'regCP_DRAW_WINDOW_LO_BASE_IDX', 'regCP_DRAW_WINDOW_MASK_HI',
|
|
'regCP_DRAW_WINDOW_MASK_HI_BASE_IDX', 'regCP_ECC_FIRSTOCCURRENCE',
|
|
'regCP_ECC_FIRSTOCCURRENCE_BASE_IDX',
|
|
'regCP_ECC_FIRSTOCCURRENCE_RING0',
|
|
'regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX',
|
|
'regCP_ECC_FIRSTOCCURRENCE_RING1',
|
|
'regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX',
|
|
'regCP_EOPQ_WAIT_TIME', 'regCP_EOPQ_WAIT_TIME_BASE_IDX',
|
|
'regCP_EOP_DONE_ADDR_HI', 'regCP_EOP_DONE_ADDR_HI_BASE_IDX',
|
|
'regCP_EOP_DONE_ADDR_LO', 'regCP_EOP_DONE_ADDR_LO_BASE_IDX',
|
|
'regCP_EOP_DONE_CNTX_ID', 'regCP_EOP_DONE_CNTX_ID_BASE_IDX',
|
|
'regCP_EOP_DONE_DATA_CNTL', 'regCP_EOP_DONE_DATA_CNTL_BASE_IDX',
|
|
'regCP_EOP_DONE_DATA_HI', 'regCP_EOP_DONE_DATA_HI_BASE_IDX',
|
|
'regCP_EOP_DONE_DATA_LO', 'regCP_EOP_DONE_DATA_LO_BASE_IDX',
|
|
'regCP_EOP_DONE_EVENT_CNTL', 'regCP_EOP_DONE_EVENT_CNTL_BASE_IDX',
|
|
'regCP_EOP_LAST_FENCE_HI', 'regCP_EOP_LAST_FENCE_HI_BASE_IDX',
|
|
'regCP_EOP_LAST_FENCE_LO', 'regCP_EOP_LAST_FENCE_LO_BASE_IDX',
|
|
'regCP_FATAL_ERROR', 'regCP_FATAL_ERROR_BASE_IDX',
|
|
'regCP_FETCHER_SOURCE', 'regCP_FETCHER_SOURCE_BASE_IDX',
|
|
'regCP_GDS_ATOMIC0_PREOP_HI',
|
|
'regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX',
|
|
'regCP_GDS_ATOMIC0_PREOP_LO',
|
|
'regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX',
|
|
'regCP_GDS_ATOMIC1_PREOP_HI',
|
|
'regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX',
|
|
'regCP_GDS_ATOMIC1_PREOP_LO',
|
|
'regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'regCP_GDS_BKUP_ADDR',
|
|
'regCP_GDS_BKUP_ADDR_BASE_IDX', 'regCP_GDS_BKUP_ADDR_HI',
|
|
'regCP_GDS_BKUP_ADDR_HI_BASE_IDX', 'regCP_GE_MSINVOC_COUNT_HI',
|
|
'regCP_GE_MSINVOC_COUNT_HI_BASE_IDX', 'regCP_GE_MSINVOC_COUNT_LO',
|
|
'regCP_GE_MSINVOC_COUNT_LO_BASE_IDX', 'regCP_GFX_CNTL',
|
|
'regCP_GFX_CNTL_BASE_IDX', 'regCP_GFX_DDID_DELTA_RPT_COUNT',
|
|
'regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX',
|
|
'regCP_GFX_DDID_INFLIGHT_COUNT',
|
|
'regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX', 'regCP_GFX_DDID_RPTR',
|
|
'regCP_GFX_DDID_RPTR_BASE_IDX', 'regCP_GFX_DDID_WPTR',
|
|
'regCP_GFX_DDID_WPTR_BASE_IDX', 'regCP_GFX_ERROR',
|
|
'regCP_GFX_ERROR_BASE_IDX', 'regCP_GFX_HPD_CONTROL0',
|
|
'regCP_GFX_HPD_CONTROL0_BASE_IDX',
|
|
'regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI',
|
|
'regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX',
|
|
'regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO',
|
|
'regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX',
|
|
'regCP_GFX_HPD_OSPRE_FENCE_DATA_HI',
|
|
'regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX',
|
|
'regCP_GFX_HPD_OSPRE_FENCE_DATA_LO',
|
|
'regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX',
|
|
'regCP_GFX_HPD_STATUS0', 'regCP_GFX_HPD_STATUS0_BASE_IDX',
|
|
'regCP_GFX_HQD_ACTIVE', 'regCP_GFX_HQD_ACTIVE_BASE_IDX',
|
|
'regCP_GFX_HQD_BASE', 'regCP_GFX_HQD_BASE_BASE_IDX',
|
|
'regCP_GFX_HQD_BASE_HI', 'regCP_GFX_HQD_BASE_HI_BASE_IDX',
|
|
'regCP_GFX_HQD_CNTL', 'regCP_GFX_HQD_CNTL_BASE_IDX',
|
|
'regCP_GFX_HQD_CSMD_RPTR', 'regCP_GFX_HQD_CSMD_RPTR_BASE_IDX',
|
|
'regCP_GFX_HQD_DEQUEUE_REQUEST',
|
|
'regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX',
|
|
'regCP_GFX_HQD_HQ_CONTROL0', 'regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX',
|
|
'regCP_GFX_HQD_HQ_STATUS0', 'regCP_GFX_HQD_HQ_STATUS0_BASE_IDX',
|
|
'regCP_GFX_HQD_IQ_TIMER', 'regCP_GFX_HQD_IQ_TIMER_BASE_IDX',
|
|
'regCP_GFX_HQD_MAPPED', 'regCP_GFX_HQD_MAPPED_BASE_IDX',
|
|
'regCP_GFX_HQD_OFFSET', 'regCP_GFX_HQD_OFFSET_BASE_IDX',
|
|
'regCP_GFX_HQD_QUANTUM', 'regCP_GFX_HQD_QUANTUM_BASE_IDX',
|
|
'regCP_GFX_HQD_QUEUE_PRIORITY',
|
|
'regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX',
|
|
'regCP_GFX_HQD_QUE_MGR_CONTROL',
|
|
'regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX', 'regCP_GFX_HQD_RPTR',
|
|
'regCP_GFX_HQD_RPTR_ADDR', 'regCP_GFX_HQD_RPTR_ADDR_BASE_IDX',
|
|
'regCP_GFX_HQD_RPTR_ADDR_HI',
|
|
'regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX',
|
|
'regCP_GFX_HQD_RPTR_BASE_IDX', 'regCP_GFX_HQD_VMID',
|
|
'regCP_GFX_HQD_VMID_BASE_IDX', 'regCP_GFX_HQD_WPTR',
|
|
'regCP_GFX_HQD_WPTR_BASE_IDX', 'regCP_GFX_HQD_WPTR_HI',
|
|
'regCP_GFX_HQD_WPTR_HI_BASE_IDX', 'regCP_GFX_INDEX_MUTEX',
|
|
'regCP_GFX_INDEX_MUTEX_BASE_IDX', 'regCP_GFX_MQD_BASE_ADDR',
|
|
'regCP_GFX_MQD_BASE_ADDR_BASE_IDX', 'regCP_GFX_MQD_BASE_ADDR_HI',
|
|
'regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX', 'regCP_GFX_MQD_CONTROL',
|
|
'regCP_GFX_MQD_CONTROL_BASE_IDX', 'regCP_GFX_QUEUE_INDEX',
|
|
'regCP_GFX_QUEUE_INDEX_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE0_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE0_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE0_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE0_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE0_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE0_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE10_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE10_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE10_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE10_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE10_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE10_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE11_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE11_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE11_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE11_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE11_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE11_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE12_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE12_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE12_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE12_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE12_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE12_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE13_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE13_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE13_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE13_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE13_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE13_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE14_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE14_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE14_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE14_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE14_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE14_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE15_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE15_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE15_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE15_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE15_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE15_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE1_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE1_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE1_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE1_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE1_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE1_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE2_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE2_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE2_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE2_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE2_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE2_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE3_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE3_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE3_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE3_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE3_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE3_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE4_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE4_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE4_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE4_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE4_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE4_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE5_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE5_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE5_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE5_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE5_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE5_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE6_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE6_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE6_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE6_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE6_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE6_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE7_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE7_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE7_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE7_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE7_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE7_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE8_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE8_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE8_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE8_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE8_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE8_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE9_BASE0',
|
|
'regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE9_BASE1',
|
|
'regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE9_CNTL0',
|
|
'regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE9_CNTL1',
|
|
'regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE9_MASK0',
|
|
'regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_APERTURE9_MASK1',
|
|
'regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_BASE0_HI',
|
|
'regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_BASE0_LO',
|
|
'regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_BASE1_HI',
|
|
'regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_BASE1_LO',
|
|
'regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_BASE_CNTL',
|
|
'regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX',
|
|
'regCP_GFX_RS64_DC_OP_CNTL', 'regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX',
|
|
'regCP_GFX_RS64_DM_INDEX_ADDR',
|
|
'regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX',
|
|
'regCP_GFX_RS64_DM_INDEX_DATA',
|
|
'regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX', 'regCP_GFX_RS64_GP0_HI0',
|
|
'regCP_GFX_RS64_GP0_HI0_BASE_IDX', 'regCP_GFX_RS64_GP0_HI1',
|
|
'regCP_GFX_RS64_GP0_HI1_BASE_IDX', 'regCP_GFX_RS64_GP0_LO0',
|
|
'regCP_GFX_RS64_GP0_LO0_BASE_IDX', 'regCP_GFX_RS64_GP0_LO1',
|
|
'regCP_GFX_RS64_GP0_LO1_BASE_IDX', 'regCP_GFX_RS64_GP1_HI0',
|
|
'regCP_GFX_RS64_GP1_HI0_BASE_IDX', 'regCP_GFX_RS64_GP1_HI1',
|
|
'regCP_GFX_RS64_GP1_HI1_BASE_IDX', 'regCP_GFX_RS64_GP1_LO0',
|
|
'regCP_GFX_RS64_GP1_LO0_BASE_IDX', 'regCP_GFX_RS64_GP1_LO1',
|
|
'regCP_GFX_RS64_GP1_LO1_BASE_IDX', 'regCP_GFX_RS64_GP2_HI0',
|
|
'regCP_GFX_RS64_GP2_HI0_BASE_IDX', 'regCP_GFX_RS64_GP2_HI1',
|
|
'regCP_GFX_RS64_GP2_HI1_BASE_IDX', 'regCP_GFX_RS64_GP2_LO0',
|
|
'regCP_GFX_RS64_GP2_LO0_BASE_IDX', 'regCP_GFX_RS64_GP2_LO1',
|
|
'regCP_GFX_RS64_GP2_LO1_BASE_IDX', 'regCP_GFX_RS64_GP3_HI0',
|
|
'regCP_GFX_RS64_GP3_HI0_BASE_IDX', 'regCP_GFX_RS64_GP3_HI1',
|
|
'regCP_GFX_RS64_GP3_HI1_BASE_IDX', 'regCP_GFX_RS64_GP3_LO0',
|
|
'regCP_GFX_RS64_GP3_LO0_BASE_IDX', 'regCP_GFX_RS64_GP3_LO1',
|
|
'regCP_GFX_RS64_GP3_LO1_BASE_IDX', 'regCP_GFX_RS64_GP4_HI0',
|
|
'regCP_GFX_RS64_GP4_HI0_BASE_IDX', 'regCP_GFX_RS64_GP4_HI1',
|
|
'regCP_GFX_RS64_GP4_HI1_BASE_IDX', 'regCP_GFX_RS64_GP4_LO0',
|
|
'regCP_GFX_RS64_GP4_LO0_BASE_IDX', 'regCP_GFX_RS64_GP4_LO1',
|
|
'regCP_GFX_RS64_GP4_LO1_BASE_IDX', 'regCP_GFX_RS64_GP5_HI0',
|
|
'regCP_GFX_RS64_GP5_HI0_BASE_IDX', 'regCP_GFX_RS64_GP5_HI1',
|
|
'regCP_GFX_RS64_GP5_HI1_BASE_IDX', 'regCP_GFX_RS64_GP5_LO0',
|
|
'regCP_GFX_RS64_GP5_LO0_BASE_IDX', 'regCP_GFX_RS64_GP5_LO1',
|
|
'regCP_GFX_RS64_GP5_LO1_BASE_IDX', 'regCP_GFX_RS64_GP6_HI',
|
|
'regCP_GFX_RS64_GP6_HI_BASE_IDX', 'regCP_GFX_RS64_GP6_LO',
|
|
'regCP_GFX_RS64_GP6_LO_BASE_IDX', 'regCP_GFX_RS64_GP7_HI',
|
|
'regCP_GFX_RS64_GP7_HI_BASE_IDX', 'regCP_GFX_RS64_GP7_LO',
|
|
'regCP_GFX_RS64_GP7_LO_BASE_IDX', 'regCP_GFX_RS64_GP8_HI',
|
|
'regCP_GFX_RS64_GP8_HI_BASE_IDX', 'regCP_GFX_RS64_GP8_LO',
|
|
'regCP_GFX_RS64_GP8_LO_BASE_IDX', 'regCP_GFX_RS64_GP9_HI',
|
|
'regCP_GFX_RS64_GP9_HI_BASE_IDX', 'regCP_GFX_RS64_GP9_LO',
|
|
'regCP_GFX_RS64_GP9_LO_BASE_IDX', 'regCP_GFX_RS64_INSTR_PNTR0',
|
|
'regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX',
|
|
'regCP_GFX_RS64_INSTR_PNTR1',
|
|
'regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX',
|
|
'regCP_GFX_RS64_INTERRUPT0', 'regCP_GFX_RS64_INTERRUPT0_BASE_IDX',
|
|
'regCP_GFX_RS64_INTERRUPT1', 'regCP_GFX_RS64_INTERRUPT1_BASE_IDX',
|
|
'regCP_GFX_RS64_INTR_EN0', 'regCP_GFX_RS64_INTR_EN0_BASE_IDX',
|
|
'regCP_GFX_RS64_INTR_EN1', 'regCP_GFX_RS64_INTR_EN1_BASE_IDX',
|
|
'regCP_GFX_RS64_LOCAL_APERTURE',
|
|
'regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX',
|
|
'regCP_GFX_RS64_LOCAL_BASE0_HI',
|
|
'regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX',
|
|
'regCP_GFX_RS64_LOCAL_BASE0_LO',
|
|
'regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX',
|
|
'regCP_GFX_RS64_LOCAL_INSTR_APERTURE',
|
|
'regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX',
|
|
'regCP_GFX_RS64_LOCAL_INSTR_BASE_HI',
|
|
'regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX',
|
|
'regCP_GFX_RS64_LOCAL_INSTR_BASE_LO',
|
|
'regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX',
|
|
'regCP_GFX_RS64_LOCAL_INSTR_MASK_HI',
|
|
'regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX',
|
|
'regCP_GFX_RS64_LOCAL_INSTR_MASK_LO',
|
|
'regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX',
|
|
'regCP_GFX_RS64_LOCAL_MASK0_HI',
|
|
'regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX',
|
|
'regCP_GFX_RS64_LOCAL_MASK0_LO',
|
|
'regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX',
|
|
'regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE',
|
|
'regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX',
|
|
'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI',
|
|
'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX',
|
|
'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO',
|
|
'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX',
|
|
'regCP_GFX_RS64_MIBOUND_HI', 'regCP_GFX_RS64_MIBOUND_HI_BASE_IDX',
|
|
'regCP_GFX_RS64_MIBOUND_LO', 'regCP_GFX_RS64_MIBOUND_LO_BASE_IDX',
|
|
'regCP_GFX_RS64_MIP_HI0', 'regCP_GFX_RS64_MIP_HI0_BASE_IDX',
|
|
'regCP_GFX_RS64_MIP_HI1', 'regCP_GFX_RS64_MIP_HI1_BASE_IDX',
|
|
'regCP_GFX_RS64_MIP_LO0', 'regCP_GFX_RS64_MIP_LO0_BASE_IDX',
|
|
'regCP_GFX_RS64_MIP_LO1', 'regCP_GFX_RS64_MIP_LO1_BASE_IDX',
|
|
'regCP_GFX_RS64_MTIMECMP_HI0',
|
|
'regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX',
|
|
'regCP_GFX_RS64_MTIMECMP_HI1',
|
|
'regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX',
|
|
'regCP_GFX_RS64_MTIMECMP_LO0',
|
|
'regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX',
|
|
'regCP_GFX_RS64_MTIMECMP_LO1',
|
|
'regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX',
|
|
'regCP_GFX_RS64_PENDING_INTERRUPT0',
|
|
'regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX',
|
|
'regCP_GFX_RS64_PENDING_INTERRUPT1',
|
|
'regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX',
|
|
'regCP_GFX_RS64_PERFCOUNT_CNTL0',
|
|
'regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX',
|
|
'regCP_GFX_RS64_PERFCOUNT_CNTL1',
|
|
'regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX',
|
|
'regCP_GPU_TIMESTAMP_OFFSET_HI',
|
|
'regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX',
|
|
'regCP_GPU_TIMESTAMP_OFFSET_LO',
|
|
'regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX', 'regCP_GRBM_FREE_COUNT',
|
|
'regCP_GRBM_FREE_COUNT_BASE_IDX', 'regCP_HPD_MES_ROQ_OFFSETS',
|
|
'regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX', 'regCP_HPD_ROQ_OFFSETS',
|
|
'regCP_HPD_ROQ_OFFSETS_BASE_IDX', 'regCP_HPD_STATUS0',
|
|
'regCP_HPD_STATUS0_BASE_IDX', 'regCP_HPD_UTCL1_CNTL',
|
|
'regCP_HPD_UTCL1_CNTL_BASE_IDX', 'regCP_HPD_UTCL1_ERROR',
|
|
'regCP_HPD_UTCL1_ERROR_ADDR',
|
|
'regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX',
|
|
'regCP_HPD_UTCL1_ERROR_BASE_IDX', 'regCP_HQD_ACTIVE',
|
|
'regCP_HQD_ACTIVE_BASE_IDX', 'regCP_HQD_AQL_CONTROL',
|
|
'regCP_HQD_AQL_CONTROL_BASE_IDX', 'regCP_HQD_ATOMIC0_PREOP_HI',
|
|
'regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX',
|
|
'regCP_HQD_ATOMIC0_PREOP_LO',
|
|
'regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX',
|
|
'regCP_HQD_ATOMIC1_PREOP_HI',
|
|
'regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX',
|
|
'regCP_HQD_ATOMIC1_PREOP_LO',
|
|
'regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX',
|
|
'regCP_HQD_CNTL_STACK_OFFSET',
|
|
'regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX',
|
|
'regCP_HQD_CNTL_STACK_SIZE', 'regCP_HQD_CNTL_STACK_SIZE_BASE_IDX',
|
|
'regCP_HQD_CTX_SAVE_BASE_ADDR_HI',
|
|
'regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX',
|
|
'regCP_HQD_CTX_SAVE_BASE_ADDR_LO',
|
|
'regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX',
|
|
'regCP_HQD_CTX_SAVE_CONTROL',
|
|
'regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX', 'regCP_HQD_CTX_SAVE_SIZE',
|
|
'regCP_HQD_CTX_SAVE_SIZE_BASE_IDX',
|
|
'regCP_HQD_DDID_DELTA_RPT_COUNT',
|
|
'regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX',
|
|
'regCP_HQD_DDID_INFLIGHT_COUNT',
|
|
'regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX', 'regCP_HQD_DDID_RPTR',
|
|
'regCP_HQD_DDID_RPTR_BASE_IDX', 'regCP_HQD_DDID_WPTR',
|
|
'regCP_HQD_DDID_WPTR_BASE_IDX', 'regCP_HQD_DEQUEUE_REQUEST',
|
|
'regCP_HQD_DEQUEUE_REQUEST_BASE_IDX', 'regCP_HQD_DEQUEUE_STATUS',
|
|
'regCP_HQD_DEQUEUE_STATUS_BASE_IDX', 'regCP_HQD_DMA_OFFLOAD',
|
|
'regCP_HQD_DMA_OFFLOAD_BASE_IDX', 'regCP_HQD_EOP_BASE_ADDR',
|
|
'regCP_HQD_EOP_BASE_ADDR_BASE_IDX', 'regCP_HQD_EOP_BASE_ADDR_HI',
|
|
'regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX', 'regCP_HQD_EOP_CONTROL',
|
|
'regCP_HQD_EOP_CONTROL_BASE_IDX', 'regCP_HQD_EOP_EVENTS',
|
|
'regCP_HQD_EOP_EVENTS_BASE_IDX', 'regCP_HQD_EOP_RPTR',
|
|
'regCP_HQD_EOP_RPTR_BASE_IDX', 'regCP_HQD_EOP_WPTR',
|
|
'regCP_HQD_EOP_WPTR_BASE_IDX', 'regCP_HQD_EOP_WPTR_MEM',
|
|
'regCP_HQD_EOP_WPTR_MEM_BASE_IDX', 'regCP_HQD_ERROR',
|
|
'regCP_HQD_ERROR_BASE_IDX', 'regCP_HQD_GDS_RESOURCE_STATE',
|
|
'regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX', 'regCP_HQD_GFX_CONTROL',
|
|
'regCP_HQD_GFX_CONTROL_BASE_IDX', 'regCP_HQD_GFX_STATUS',
|
|
'regCP_HQD_GFX_STATUS_BASE_IDX', 'regCP_HQD_HQ_CONTROL0',
|
|
'regCP_HQD_HQ_CONTROL0_BASE_IDX', 'regCP_HQD_HQ_CONTROL1',
|
|
'regCP_HQD_HQ_CONTROL1_BASE_IDX', 'regCP_HQD_HQ_SCHEDULER0',
|
|
'regCP_HQD_HQ_SCHEDULER0_BASE_IDX', 'regCP_HQD_HQ_SCHEDULER1',
|
|
'regCP_HQD_HQ_SCHEDULER1_BASE_IDX', 'regCP_HQD_HQ_STATUS0',
|
|
'regCP_HQD_HQ_STATUS0_BASE_IDX', 'regCP_HQD_HQ_STATUS1',
|
|
'regCP_HQD_HQ_STATUS1_BASE_IDX', 'regCP_HQD_IB_BASE_ADDR',
|
|
'regCP_HQD_IB_BASE_ADDR_BASE_IDX', 'regCP_HQD_IB_BASE_ADDR_HI',
|
|
'regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX', 'regCP_HQD_IB_CONTROL',
|
|
'regCP_HQD_IB_CONTROL_BASE_IDX', 'regCP_HQD_IB_RPTR',
|
|
'regCP_HQD_IB_RPTR_BASE_IDX', 'regCP_HQD_IQ_RPTR',
|
|
'regCP_HQD_IQ_RPTR_BASE_IDX', 'regCP_HQD_IQ_TIMER',
|
|
'regCP_HQD_IQ_TIMER_BASE_IDX', 'regCP_HQD_MSG_TYPE',
|
|
'regCP_HQD_MSG_TYPE_BASE_IDX', 'regCP_HQD_OFFLOAD',
|
|
'regCP_HQD_OFFLOAD_BASE_IDX', 'regCP_HQD_PERSISTENT_STATE',
|
|
'regCP_HQD_PERSISTENT_STATE_BASE_IDX', 'regCP_HQD_PIPE_PRIORITY',
|
|
'regCP_HQD_PIPE_PRIORITY_BASE_IDX', 'regCP_HQD_PQ_BASE',
|
|
'regCP_HQD_PQ_BASE_BASE_IDX', 'regCP_HQD_PQ_BASE_HI',
|
|
'regCP_HQD_PQ_BASE_HI_BASE_IDX', 'regCP_HQD_PQ_CONTROL',
|
|
'regCP_HQD_PQ_CONTROL_BASE_IDX', 'regCP_HQD_PQ_DOORBELL_CONTROL',
|
|
'regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX', 'regCP_HQD_PQ_RPTR',
|
|
'regCP_HQD_PQ_RPTR_BASE_IDX', 'regCP_HQD_PQ_RPTR_REPORT_ADDR',
|
|
'regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX',
|
|
'regCP_HQD_PQ_RPTR_REPORT_ADDR_HI',
|
|
'regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX',
|
|
'regCP_HQD_PQ_WPTR_HI', 'regCP_HQD_PQ_WPTR_HI_BASE_IDX',
|
|
'regCP_HQD_PQ_WPTR_LO', 'regCP_HQD_PQ_WPTR_LO_BASE_IDX',
|
|
'regCP_HQD_PQ_WPTR_POLL_ADDR',
|
|
'regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX',
|
|
'regCP_HQD_PQ_WPTR_POLL_ADDR_HI',
|
|
'regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX', 'regCP_HQD_QUANTUM',
|
|
'regCP_HQD_QUANTUM_BASE_IDX', 'regCP_HQD_QUEUE_PRIORITY',
|
|
'regCP_HQD_QUEUE_PRIORITY_BASE_IDX', 'regCP_HQD_SEMA_CMD',
|
|
'regCP_HQD_SEMA_CMD_BASE_IDX',
|
|
'regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT',
|
|
'regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX',
|
|
'regCP_HQD_SUSPEND_CNTL_STACK_OFFSET',
|
|
'regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX',
|
|
'regCP_HQD_SUSPEND_WG_STATE_OFFSET',
|
|
'regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX', 'regCP_HQD_VMID',
|
|
'regCP_HQD_VMID_BASE_IDX', 'regCP_HQD_WG_STATE_OFFSET',
|
|
'regCP_HQD_WG_STATE_OFFSET_BASE_IDX', 'regCP_HYP_MEC1_UCODE_ADDR',
|
|
'regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX', 'regCP_HYP_MEC1_UCODE_DATA',
|
|
'regCP_HYP_MEC1_UCODE_DATA_BASE_IDX', 'regCP_HYP_MEC2_UCODE_ADDR',
|
|
'regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX', 'regCP_HYP_MEC2_UCODE_DATA',
|
|
'regCP_HYP_MEC2_UCODE_DATA_BASE_IDX', 'regCP_HYP_ME_UCODE_ADDR',
|
|
'regCP_HYP_ME_UCODE_ADDR_BASE_IDX', 'regCP_HYP_ME_UCODE_DATA',
|
|
'regCP_HYP_ME_UCODE_DATA_BASE_IDX', 'regCP_HYP_PFP_UCODE_ADDR',
|
|
'regCP_HYP_PFP_UCODE_ADDR_BASE_IDX', 'regCP_HYP_PFP_UCODE_DATA',
|
|
'regCP_HYP_PFP_UCODE_DATA_BASE_IDX', 'regCP_IB1_BASE_HI',
|
|
'regCP_IB1_BASE_HI_BASE_IDX', 'regCP_IB1_BASE_LO',
|
|
'regCP_IB1_BASE_LO_BASE_IDX', 'regCP_IB1_BUFSZ',
|
|
'regCP_IB1_BUFSZ_BASE_IDX', 'regCP_IB1_CMD_BUFSZ',
|
|
'regCP_IB1_CMD_BUFSZ_BASE_IDX', 'regCP_IB2_BASE_HI',
|
|
'regCP_IB2_BASE_HI_BASE_IDX', 'regCP_IB2_BASE_LO',
|
|
'regCP_IB2_BASE_LO_BASE_IDX', 'regCP_IB2_BUFSZ',
|
|
'regCP_IB2_BUFSZ_BASE_IDX', 'regCP_IB2_CMD_BUFSZ',
|
|
'regCP_IB2_CMD_BUFSZ_BASE_IDX', 'regCP_IB2_OFFSET',
|
|
'regCP_IB2_OFFSET_BASE_IDX', 'regCP_IB2_PREAMBLE_BEGIN',
|
|
'regCP_IB2_PREAMBLE_BEGIN_BASE_IDX', 'regCP_IB2_PREAMBLE_END',
|
|
'regCP_IB2_PREAMBLE_END_BASE_IDX', 'regCP_INDEX_BASE_ADDR',
|
|
'regCP_INDEX_BASE_ADDR_BASE_IDX', 'regCP_INDEX_BASE_ADDR_HI',
|
|
'regCP_INDEX_BASE_ADDR_HI_BASE_IDX', 'regCP_INDEX_TYPE',
|
|
'regCP_INDEX_TYPE_BASE_IDX', 'regCP_INT_CNTL',
|
|
'regCP_INT_CNTL_BASE_IDX', 'regCP_INT_CNTL_RING0',
|
|
'regCP_INT_CNTL_RING0_BASE_IDX', 'regCP_INT_CNTL_RING1',
|
|
'regCP_INT_CNTL_RING1_BASE_IDX', 'regCP_INT_STATUS',
|
|
'regCP_INT_STATUS_BASE_IDX', 'regCP_INT_STATUS_RING0',
|
|
'regCP_INT_STATUS_RING0_BASE_IDX', 'regCP_INT_STATUS_RING1',
|
|
'regCP_INT_STATUS_RING1_BASE_IDX', 'regCP_IQ_WAIT_TIME1',
|
|
'regCP_IQ_WAIT_TIME1_BASE_IDX', 'regCP_IQ_WAIT_TIME2',
|
|
'regCP_IQ_WAIT_TIME2_BASE_IDX', 'regCP_IQ_WAIT_TIME3',
|
|
'regCP_IQ_WAIT_TIME3_BASE_IDX', 'regCP_MAX_CONTEXT',
|
|
'regCP_MAX_CONTEXT_BASE_IDX', 'regCP_MAX_DRAW_COUNT',
|
|
'regCP_MAX_DRAW_COUNT_BASE_IDX', 'regCP_ME0_PIPE0_PRIORITY',
|
|
'regCP_ME0_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME0_PIPE0_VMID',
|
|
'regCP_ME0_PIPE0_VMID_BASE_IDX', 'regCP_ME0_PIPE1_PRIORITY',
|
|
'regCP_ME0_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME0_PIPE1_VMID',
|
|
'regCP_ME0_PIPE1_VMID_BASE_IDX', 'regCP_ME0_PIPE_PRIORITY_CNTS',
|
|
'regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX',
|
|
'regCP_ME1_PIPE0_INT_CNTL', 'regCP_ME1_PIPE0_INT_CNTL_BASE_IDX',
|
|
'regCP_ME1_PIPE0_INT_STATUS',
|
|
'regCP_ME1_PIPE0_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE0_PRIORITY',
|
|
'regCP_ME1_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE1_INT_CNTL',
|
|
'regCP_ME1_PIPE1_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE1_INT_STATUS',
|
|
'regCP_ME1_PIPE1_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE1_PRIORITY',
|
|
'regCP_ME1_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE2_INT_CNTL',
|
|
'regCP_ME1_PIPE2_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE2_INT_STATUS',
|
|
'regCP_ME1_PIPE2_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE2_PRIORITY',
|
|
'regCP_ME1_PIPE2_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE3_INT_CNTL',
|
|
'regCP_ME1_PIPE3_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE3_INT_STATUS',
|
|
'regCP_ME1_PIPE3_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE3_PRIORITY',
|
|
'regCP_ME1_PIPE3_PRIORITY_BASE_IDX',
|
|
'regCP_ME1_PIPE_PRIORITY_CNTS',
|
|
'regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX',
|
|
'regCP_ME2_PIPE0_INT_CNTL', 'regCP_ME2_PIPE0_INT_CNTL_BASE_IDX',
|
|
'regCP_ME2_PIPE0_INT_STATUS',
|
|
'regCP_ME2_PIPE0_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE0_PRIORITY',
|
|
'regCP_ME2_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE1_INT_CNTL',
|
|
'regCP_ME2_PIPE1_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE1_INT_STATUS',
|
|
'regCP_ME2_PIPE1_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE1_PRIORITY',
|
|
'regCP_ME2_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE2_INT_CNTL',
|
|
'regCP_ME2_PIPE2_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE2_INT_STATUS',
|
|
'regCP_ME2_PIPE2_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE2_PRIORITY',
|
|
'regCP_ME2_PIPE2_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE3_INT_CNTL',
|
|
'regCP_ME2_PIPE3_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE3_INT_STATUS',
|
|
'regCP_ME2_PIPE3_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE3_PRIORITY',
|
|
'regCP_ME2_PIPE3_PRIORITY_BASE_IDX',
|
|
'regCP_ME2_PIPE_PRIORITY_CNTS',
|
|
'regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX',
|
|
'regCP_MEC1_F32_INTERRUPT', 'regCP_MEC1_F32_INTERRUPT_BASE_IDX',
|
|
'regCP_MEC1_F32_INT_DIS', 'regCP_MEC1_F32_INT_DIS_BASE_IDX',
|
|
'regCP_MEC1_INSTR_PNTR', 'regCP_MEC1_INSTR_PNTR_BASE_IDX',
|
|
'regCP_MEC1_INTR_ROUTINE_START',
|
|
'regCP_MEC1_INTR_ROUTINE_START_BASE_IDX',
|
|
'regCP_MEC1_PRGRM_CNTR_START',
|
|
'regCP_MEC1_PRGRM_CNTR_START_BASE_IDX',
|
|
'regCP_MEC2_F32_INTERRUPT', 'regCP_MEC2_F32_INTERRUPT_BASE_IDX',
|
|
'regCP_MEC2_F32_INT_DIS', 'regCP_MEC2_F32_INT_DIS_BASE_IDX',
|
|
'regCP_MEC2_INSTR_PNTR', 'regCP_MEC2_INSTR_PNTR_BASE_IDX',
|
|
'regCP_MEC2_INTR_ROUTINE_START',
|
|
'regCP_MEC2_INTR_ROUTINE_START_BASE_IDX',
|
|
'regCP_MEC2_PRGRM_CNTR_START',
|
|
'regCP_MEC2_PRGRM_CNTR_START_BASE_IDX', 'regCP_MEC_CNTL',
|
|
'regCP_MEC_CNTL_BASE_IDX', 'regCP_MEC_DC_APERTURE0_BASE',
|
|
'regCP_MEC_DC_APERTURE0_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE0_CNTL',
|
|
'regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE0_MASK',
|
|
'regCP_MEC_DC_APERTURE0_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE10_BASE',
|
|
'regCP_MEC_DC_APERTURE10_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE10_CNTL',
|
|
'regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE10_MASK',
|
|
'regCP_MEC_DC_APERTURE10_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE11_BASE',
|
|
'regCP_MEC_DC_APERTURE11_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE11_CNTL',
|
|
'regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE11_MASK',
|
|
'regCP_MEC_DC_APERTURE11_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE12_BASE',
|
|
'regCP_MEC_DC_APERTURE12_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE12_CNTL',
|
|
'regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE12_MASK',
|
|
'regCP_MEC_DC_APERTURE12_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE13_BASE',
|
|
'regCP_MEC_DC_APERTURE13_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE13_CNTL',
|
|
'regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE13_MASK',
|
|
'regCP_MEC_DC_APERTURE13_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE14_BASE',
|
|
'regCP_MEC_DC_APERTURE14_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE14_CNTL',
|
|
'regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE14_MASK',
|
|
'regCP_MEC_DC_APERTURE14_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE15_BASE',
|
|
'regCP_MEC_DC_APERTURE15_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE15_CNTL',
|
|
'regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE15_MASK',
|
|
'regCP_MEC_DC_APERTURE15_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE1_BASE',
|
|
'regCP_MEC_DC_APERTURE1_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE1_CNTL',
|
|
'regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE1_MASK',
|
|
'regCP_MEC_DC_APERTURE1_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE2_BASE',
|
|
'regCP_MEC_DC_APERTURE2_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE2_CNTL',
|
|
'regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE2_MASK',
|
|
'regCP_MEC_DC_APERTURE2_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE3_BASE',
|
|
'regCP_MEC_DC_APERTURE3_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE3_CNTL',
|
|
'regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE3_MASK',
|
|
'regCP_MEC_DC_APERTURE3_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE4_BASE',
|
|
'regCP_MEC_DC_APERTURE4_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE4_CNTL',
|
|
'regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE4_MASK',
|
|
'regCP_MEC_DC_APERTURE4_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE5_BASE',
|
|
'regCP_MEC_DC_APERTURE5_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE5_CNTL',
|
|
'regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE5_MASK',
|
|
'regCP_MEC_DC_APERTURE5_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE6_BASE',
|
|
'regCP_MEC_DC_APERTURE6_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE6_CNTL',
|
|
'regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE6_MASK',
|
|
'regCP_MEC_DC_APERTURE6_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE7_BASE',
|
|
'regCP_MEC_DC_APERTURE7_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE7_CNTL',
|
|
'regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE7_MASK',
|
|
'regCP_MEC_DC_APERTURE7_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE8_BASE',
|
|
'regCP_MEC_DC_APERTURE8_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE8_CNTL',
|
|
'regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE8_MASK',
|
|
'regCP_MEC_DC_APERTURE8_MASK_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE9_BASE',
|
|
'regCP_MEC_DC_APERTURE9_BASE_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE9_CNTL',
|
|
'regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX',
|
|
'regCP_MEC_DC_APERTURE9_MASK',
|
|
'regCP_MEC_DC_APERTURE9_MASK_BASE_IDX', 'regCP_MEC_DC_BASE_CNTL',
|
|
'regCP_MEC_DC_BASE_CNTL_BASE_IDX', 'regCP_MEC_DC_BASE_HI',
|
|
'regCP_MEC_DC_BASE_HI_BASE_IDX', 'regCP_MEC_DC_BASE_LO',
|
|
'regCP_MEC_DC_BASE_LO_BASE_IDX', 'regCP_MEC_DC_OP_CNTL',
|
|
'regCP_MEC_DC_OP_CNTL_BASE_IDX', 'regCP_MEC_DM_INDEX_ADDR',
|
|
'regCP_MEC_DM_INDEX_ADDR_BASE_IDX', 'regCP_MEC_DM_INDEX_DATA',
|
|
'regCP_MEC_DM_INDEX_DATA_BASE_IDX',
|
|
'regCP_MEC_DOORBELL_RANGE_LOWER',
|
|
'regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX',
|
|
'regCP_MEC_DOORBELL_RANGE_UPPER',
|
|
'regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX', 'regCP_MEC_GP0_HI',
|
|
'regCP_MEC_GP0_HI_BASE_IDX', 'regCP_MEC_GP0_LO',
|
|
'regCP_MEC_GP0_LO_BASE_IDX', 'regCP_MEC_GP1_HI',
|
|
'regCP_MEC_GP1_HI_BASE_IDX', 'regCP_MEC_GP1_LO',
|
|
'regCP_MEC_GP1_LO_BASE_IDX', 'regCP_MEC_GP2_HI',
|
|
'regCP_MEC_GP2_HI_BASE_IDX', 'regCP_MEC_GP2_LO',
|
|
'regCP_MEC_GP2_LO_BASE_IDX', 'regCP_MEC_GP3_HI',
|
|
'regCP_MEC_GP3_HI_BASE_IDX', 'regCP_MEC_GP3_LO',
|
|
'regCP_MEC_GP3_LO_BASE_IDX', 'regCP_MEC_GP4_HI',
|
|
'regCP_MEC_GP4_HI_BASE_IDX', 'regCP_MEC_GP4_LO',
|
|
'regCP_MEC_GP4_LO_BASE_IDX', 'regCP_MEC_GP5_HI',
|
|
'regCP_MEC_GP5_HI_BASE_IDX', 'regCP_MEC_GP5_LO',
|
|
'regCP_MEC_GP5_LO_BASE_IDX', 'regCP_MEC_GP6_HI',
|
|
'regCP_MEC_GP6_HI_BASE_IDX', 'regCP_MEC_GP6_LO',
|
|
'regCP_MEC_GP6_LO_BASE_IDX', 'regCP_MEC_GP7_HI',
|
|
'regCP_MEC_GP7_HI_BASE_IDX', 'regCP_MEC_GP7_LO',
|
|
'regCP_MEC_GP7_LO_BASE_IDX', 'regCP_MEC_GP8_HI',
|
|
'regCP_MEC_GP8_HI_BASE_IDX', 'regCP_MEC_GP8_LO',
|
|
'regCP_MEC_GP8_LO_BASE_IDX', 'regCP_MEC_GP9_HI',
|
|
'regCP_MEC_GP9_HI_BASE_IDX', 'regCP_MEC_GP9_LO',
|
|
'regCP_MEC_GP9_LO_BASE_IDX', 'regCP_MEC_ISA_CNTL',
|
|
'regCP_MEC_ISA_CNTL_BASE_IDX', 'regCP_MEC_JT_STAT',
|
|
'regCP_MEC_JT_STAT_BASE_IDX', 'regCP_MEC_LOCAL_APERTURE',
|
|
'regCP_MEC_LOCAL_APERTURE_BASE_IDX', 'regCP_MEC_LOCAL_BASE0_HI',
|
|
'regCP_MEC_LOCAL_BASE0_HI_BASE_IDX', 'regCP_MEC_LOCAL_BASE0_LO',
|
|
'regCP_MEC_LOCAL_BASE0_LO_BASE_IDX',
|
|
'regCP_MEC_LOCAL_INSTR_APERTURE',
|
|
'regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX',
|
|
'regCP_MEC_LOCAL_INSTR_BASE_HI',
|
|
'regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX',
|
|
'regCP_MEC_LOCAL_INSTR_BASE_LO',
|
|
'regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX',
|
|
'regCP_MEC_LOCAL_INSTR_MASK_HI',
|
|
'regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX',
|
|
'regCP_MEC_LOCAL_INSTR_MASK_LO',
|
|
'regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX',
|
|
'regCP_MEC_LOCAL_MASK0_HI', 'regCP_MEC_LOCAL_MASK0_HI_BASE_IDX',
|
|
'regCP_MEC_LOCAL_MASK0_LO', 'regCP_MEC_LOCAL_MASK0_LO_BASE_IDX',
|
|
'regCP_MEC_LOCAL_SCRATCH_APERTURE',
|
|
'regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX',
|
|
'regCP_MEC_LOCAL_SCRATCH_BASE_HI',
|
|
'regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX',
|
|
'regCP_MEC_LOCAL_SCRATCH_BASE_LO',
|
|
'regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX', 'regCP_MEC_MDBASE_HI',
|
|
'regCP_MEC_MDBASE_HI_BASE_IDX', 'regCP_MEC_MDBASE_LO',
|
|
'regCP_MEC_MDBASE_LO_BASE_IDX', 'regCP_MEC_MDBOUND_HI',
|
|
'regCP_MEC_MDBOUND_HI_BASE_IDX', 'regCP_MEC_MDBOUND_LO',
|
|
'regCP_MEC_MDBOUND_LO_BASE_IDX', 'regCP_MEC_ME1_HEADER_DUMP',
|
|
'regCP_MEC_ME1_HEADER_DUMP_BASE_IDX', 'regCP_MEC_ME1_UCODE_ADDR',
|
|
'regCP_MEC_ME1_UCODE_ADDR_BASE_IDX', 'regCP_MEC_ME1_UCODE_DATA',
|
|
'regCP_MEC_ME1_UCODE_DATA_BASE_IDX', 'regCP_MEC_ME2_HEADER_DUMP',
|
|
'regCP_MEC_ME2_HEADER_DUMP_BASE_IDX', 'regCP_MEC_ME2_UCODE_ADDR',
|
|
'regCP_MEC_ME2_UCODE_ADDR_BASE_IDX', 'regCP_MEC_ME2_UCODE_DATA',
|
|
'regCP_MEC_ME2_UCODE_DATA_BASE_IDX', 'regCP_MEC_MIBOUND_HI',
|
|
'regCP_MEC_MIBOUND_HI_BASE_IDX', 'regCP_MEC_MIBOUND_LO',
|
|
'regCP_MEC_MIBOUND_LO_BASE_IDX', 'regCP_MEC_MIE_HI',
|
|
'regCP_MEC_MIE_HI_BASE_IDX', 'regCP_MEC_MIE_LO',
|
|
'regCP_MEC_MIE_LO_BASE_IDX', 'regCP_MEC_MIP_HI',
|
|
'regCP_MEC_MIP_HI_BASE_IDX', 'regCP_MEC_MIP_LO',
|
|
'regCP_MEC_MIP_LO_BASE_IDX', 'regCP_MEC_MTIMECMP_HI',
|
|
'regCP_MEC_MTIMECMP_HI_BASE_IDX', 'regCP_MEC_MTIMECMP_LO',
|
|
'regCP_MEC_MTIMECMP_LO_BASE_IDX', 'regCP_MEC_MTVEC_HI',
|
|
'regCP_MEC_MTVEC_HI_BASE_IDX', 'regCP_MEC_MTVEC_LO',
|
|
'regCP_MEC_MTVEC_LO_BASE_IDX', 'regCP_MEC_RS64_CNTL',
|
|
'regCP_MEC_RS64_CNTL_BASE_IDX', 'regCP_MEC_RS64_INSTR_PNTR',
|
|
'regCP_MEC_RS64_INSTR_PNTR_BASE_IDX', 'regCP_MEC_RS64_INTERRUPT',
|
|
'regCP_MEC_RS64_INTERRUPT_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_16',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_17',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_18',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_19',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_20',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_21',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_22',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_23',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_24',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_25',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_26',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_27',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_28',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_29',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_30',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_31',
|
|
'regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX',
|
|
'regCP_MEC_RS64_PENDING_INTERRUPT',
|
|
'regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX',
|
|
'regCP_MEC_RS64_PERFCOUNT_CNTL',
|
|
'regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX',
|
|
'regCP_MEC_RS64_PRGRM_CNTR_START',
|
|
'regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX',
|
|
'regCP_MEC_RS64_PRGRM_CNTR_START_HI',
|
|
'regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_MEQ_AVAIL',
|
|
'regCP_MEQ_AVAIL_BASE_IDX', 'regCP_MEQ_STAT',
|
|
'regCP_MEQ_STAT_BASE_IDX', 'regCP_MEQ_THRESHOLDS',
|
|
'regCP_MEQ_THRESHOLDS_BASE_IDX', 'regCP_MES_CNTL',
|
|
'regCP_MES_CNTL_BASE_IDX', 'regCP_MES_DC_APERTURE0_BASE',
|
|
'regCP_MES_DC_APERTURE0_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE0_CNTL',
|
|
'regCP_MES_DC_APERTURE0_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE0_MASK',
|
|
'regCP_MES_DC_APERTURE0_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE10_BASE',
|
|
'regCP_MES_DC_APERTURE10_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE10_CNTL',
|
|
'regCP_MES_DC_APERTURE10_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE10_MASK',
|
|
'regCP_MES_DC_APERTURE10_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE11_BASE',
|
|
'regCP_MES_DC_APERTURE11_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE11_CNTL',
|
|
'regCP_MES_DC_APERTURE11_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE11_MASK',
|
|
'regCP_MES_DC_APERTURE11_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE12_BASE',
|
|
'regCP_MES_DC_APERTURE12_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE12_CNTL',
|
|
'regCP_MES_DC_APERTURE12_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE12_MASK',
|
|
'regCP_MES_DC_APERTURE12_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE13_BASE',
|
|
'regCP_MES_DC_APERTURE13_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE13_CNTL',
|
|
'regCP_MES_DC_APERTURE13_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE13_MASK',
|
|
'regCP_MES_DC_APERTURE13_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE14_BASE',
|
|
'regCP_MES_DC_APERTURE14_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE14_CNTL',
|
|
'regCP_MES_DC_APERTURE14_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE14_MASK',
|
|
'regCP_MES_DC_APERTURE14_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE15_BASE',
|
|
'regCP_MES_DC_APERTURE15_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE15_CNTL',
|
|
'regCP_MES_DC_APERTURE15_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE15_MASK',
|
|
'regCP_MES_DC_APERTURE15_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE1_BASE',
|
|
'regCP_MES_DC_APERTURE1_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE1_CNTL',
|
|
'regCP_MES_DC_APERTURE1_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE1_MASK',
|
|
'regCP_MES_DC_APERTURE1_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE2_BASE',
|
|
'regCP_MES_DC_APERTURE2_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE2_CNTL',
|
|
'regCP_MES_DC_APERTURE2_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE2_MASK',
|
|
'regCP_MES_DC_APERTURE2_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE3_BASE',
|
|
'regCP_MES_DC_APERTURE3_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE3_CNTL',
|
|
'regCP_MES_DC_APERTURE3_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE3_MASK',
|
|
'regCP_MES_DC_APERTURE3_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE4_BASE',
|
|
'regCP_MES_DC_APERTURE4_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE4_CNTL',
|
|
'regCP_MES_DC_APERTURE4_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE4_MASK',
|
|
'regCP_MES_DC_APERTURE4_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE5_BASE',
|
|
'regCP_MES_DC_APERTURE5_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE5_CNTL',
|
|
'regCP_MES_DC_APERTURE5_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE5_MASK',
|
|
'regCP_MES_DC_APERTURE5_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE6_BASE',
|
|
'regCP_MES_DC_APERTURE6_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE6_CNTL',
|
|
'regCP_MES_DC_APERTURE6_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE6_MASK',
|
|
'regCP_MES_DC_APERTURE6_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE7_BASE',
|
|
'regCP_MES_DC_APERTURE7_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE7_CNTL',
|
|
'regCP_MES_DC_APERTURE7_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE7_MASK',
|
|
'regCP_MES_DC_APERTURE7_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE8_BASE',
|
|
'regCP_MES_DC_APERTURE8_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE8_CNTL',
|
|
'regCP_MES_DC_APERTURE8_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE8_MASK',
|
|
'regCP_MES_DC_APERTURE8_MASK_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE9_BASE',
|
|
'regCP_MES_DC_APERTURE9_BASE_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE9_CNTL',
|
|
'regCP_MES_DC_APERTURE9_CNTL_BASE_IDX',
|
|
'regCP_MES_DC_APERTURE9_MASK',
|
|
'regCP_MES_DC_APERTURE9_MASK_BASE_IDX', 'regCP_MES_DC_BASE_CNTL',
|
|
'regCP_MES_DC_BASE_CNTL_BASE_IDX', 'regCP_MES_DC_BASE_HI',
|
|
'regCP_MES_DC_BASE_HI_BASE_IDX', 'regCP_MES_DC_BASE_LO',
|
|
'regCP_MES_DC_BASE_LO_BASE_IDX', 'regCP_MES_DC_OP_CNTL',
|
|
'regCP_MES_DC_OP_CNTL_BASE_IDX',
|
|
'regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR',
|
|
'regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX',
|
|
'regCP_MES_DM_INDEX_ADDR', 'regCP_MES_DM_INDEX_ADDR_BASE_IDX',
|
|
'regCP_MES_DM_INDEX_DATA', 'regCP_MES_DM_INDEX_DATA_BASE_IDX',
|
|
'regCP_MES_DOORBELL_CONTROL1',
|
|
'regCP_MES_DOORBELL_CONTROL1_BASE_IDX',
|
|
'regCP_MES_DOORBELL_CONTROL2',
|
|
'regCP_MES_DOORBELL_CONTROL2_BASE_IDX',
|
|
'regCP_MES_DOORBELL_CONTROL3',
|
|
'regCP_MES_DOORBELL_CONTROL3_BASE_IDX',
|
|
'regCP_MES_DOORBELL_CONTROL4',
|
|
'regCP_MES_DOORBELL_CONTROL4_BASE_IDX',
|
|
'regCP_MES_DOORBELL_CONTROL5',
|
|
'regCP_MES_DOORBELL_CONTROL5_BASE_IDX',
|
|
'regCP_MES_DOORBELL_CONTROL6',
|
|
'regCP_MES_DOORBELL_CONTROL6_BASE_IDX', 'regCP_MES_GP0_HI',
|
|
'regCP_MES_GP0_HI_BASE_IDX', 'regCP_MES_GP0_LO',
|
|
'regCP_MES_GP0_LO_BASE_IDX', 'regCP_MES_GP1_HI',
|
|
'regCP_MES_GP1_HI_BASE_IDX', 'regCP_MES_GP1_LO',
|
|
'regCP_MES_GP1_LO_BASE_IDX', 'regCP_MES_GP2_HI',
|
|
'regCP_MES_GP2_HI_BASE_IDX', 'regCP_MES_GP2_LO',
|
|
'regCP_MES_GP2_LO_BASE_IDX', 'regCP_MES_GP3_HI',
|
|
'regCP_MES_GP3_HI_BASE_IDX', 'regCP_MES_GP3_LO',
|
|
'regCP_MES_GP3_LO_BASE_IDX', 'regCP_MES_GP4_HI',
|
|
'regCP_MES_GP4_HI_BASE_IDX', 'regCP_MES_GP4_LO',
|
|
'regCP_MES_GP4_LO_BASE_IDX', 'regCP_MES_GP5_HI',
|
|
'regCP_MES_GP5_HI_BASE_IDX', 'regCP_MES_GP5_LO',
|
|
'regCP_MES_GP5_LO_BASE_IDX', 'regCP_MES_GP6_HI',
|
|
'regCP_MES_GP6_HI_BASE_IDX', 'regCP_MES_GP6_LO',
|
|
'regCP_MES_GP6_LO_BASE_IDX', 'regCP_MES_GP7_HI',
|
|
'regCP_MES_GP7_HI_BASE_IDX', 'regCP_MES_GP7_LO',
|
|
'regCP_MES_GP7_LO_BASE_IDX', 'regCP_MES_GP8_HI',
|
|
'regCP_MES_GP8_HI_BASE_IDX', 'regCP_MES_GP8_LO',
|
|
'regCP_MES_GP8_LO_BASE_IDX', 'regCP_MES_GP9_HI',
|
|
'regCP_MES_GP9_HI_BASE_IDX', 'regCP_MES_GP9_LO',
|
|
'regCP_MES_GP9_LO_BASE_IDX', 'regCP_MES_HEADER_DUMP',
|
|
'regCP_MES_HEADER_DUMP_BASE_IDX', 'regCP_MES_IC_BASE_CNTL',
|
|
'regCP_MES_IC_BASE_CNTL_BASE_IDX', 'regCP_MES_IC_BASE_HI',
|
|
'regCP_MES_IC_BASE_HI_BASE_IDX', 'regCP_MES_IC_BASE_LO',
|
|
'regCP_MES_IC_BASE_LO_BASE_IDX', 'regCP_MES_IC_OP_CNTL',
|
|
'regCP_MES_IC_OP_CNTL_BASE_IDX', 'regCP_MES_INSTR_PNTR',
|
|
'regCP_MES_INSTR_PNTR_BASE_IDX', 'regCP_MES_INTERRUPT',
|
|
'regCP_MES_INTERRUPT_BASE_IDX', 'regCP_MES_INTERRUPT_DATA_16',
|
|
'regCP_MES_INTERRUPT_DATA_16_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_17',
|
|
'regCP_MES_INTERRUPT_DATA_17_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_18',
|
|
'regCP_MES_INTERRUPT_DATA_18_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_19',
|
|
'regCP_MES_INTERRUPT_DATA_19_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_20',
|
|
'regCP_MES_INTERRUPT_DATA_20_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_21',
|
|
'regCP_MES_INTERRUPT_DATA_21_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_22',
|
|
'regCP_MES_INTERRUPT_DATA_22_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_23',
|
|
'regCP_MES_INTERRUPT_DATA_23_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_24',
|
|
'regCP_MES_INTERRUPT_DATA_24_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_25',
|
|
'regCP_MES_INTERRUPT_DATA_25_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_26',
|
|
'regCP_MES_INTERRUPT_DATA_26_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_27',
|
|
'regCP_MES_INTERRUPT_DATA_27_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_28',
|
|
'regCP_MES_INTERRUPT_DATA_28_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_29',
|
|
'regCP_MES_INTERRUPT_DATA_29_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_30',
|
|
'regCP_MES_INTERRUPT_DATA_30_BASE_IDX',
|
|
'regCP_MES_INTERRUPT_DATA_31',
|
|
'regCP_MES_INTERRUPT_DATA_31_BASE_IDX',
|
|
'regCP_MES_INTR_ROUTINE_START',
|
|
'regCP_MES_INTR_ROUTINE_START_BASE_IDX',
|
|
'regCP_MES_INTR_ROUTINE_START_HI',
|
|
'regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX',
|
|
'regCP_MES_LOCAL_APERTURE', 'regCP_MES_LOCAL_APERTURE_BASE_IDX',
|
|
'regCP_MES_LOCAL_BASE0_HI', 'regCP_MES_LOCAL_BASE0_HI_BASE_IDX',
|
|
'regCP_MES_LOCAL_BASE0_LO', 'regCP_MES_LOCAL_BASE0_LO_BASE_IDX',
|
|
'regCP_MES_LOCAL_INSTR_APERTURE',
|
|
'regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX',
|
|
'regCP_MES_LOCAL_INSTR_BASE_HI',
|
|
'regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX',
|
|
'regCP_MES_LOCAL_INSTR_BASE_LO',
|
|
'regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX',
|
|
'regCP_MES_LOCAL_INSTR_MASK_HI',
|
|
'regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX',
|
|
'regCP_MES_LOCAL_INSTR_MASK_LO',
|
|
'regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX',
|
|
'regCP_MES_LOCAL_MASK0_HI', 'regCP_MES_LOCAL_MASK0_HI_BASE_IDX',
|
|
'regCP_MES_LOCAL_MASK0_LO', 'regCP_MES_LOCAL_MASK0_LO_BASE_IDX',
|
|
'regCP_MES_LOCAL_SCRATCH_APERTURE',
|
|
'regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX',
|
|
'regCP_MES_LOCAL_SCRATCH_BASE_HI',
|
|
'regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX',
|
|
'regCP_MES_LOCAL_SCRATCH_BASE_LO',
|
|
'regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX',
|
|
'regCP_MES_MARCHID_HI', 'regCP_MES_MARCHID_HI_BASE_IDX',
|
|
'regCP_MES_MARCHID_LO', 'regCP_MES_MARCHID_LO_BASE_IDX',
|
|
'regCP_MES_MBADADDR_HI', 'regCP_MES_MBADADDR_HI_BASE_IDX',
|
|
'regCP_MES_MBADADDR_LO', 'regCP_MES_MBADADDR_LO_BASE_IDX',
|
|
'regCP_MES_MCAUSE_HI', 'regCP_MES_MCAUSE_HI_BASE_IDX',
|
|
'regCP_MES_MCAUSE_LO', 'regCP_MES_MCAUSE_LO_BASE_IDX',
|
|
'regCP_MES_MCYCLE_HI', 'regCP_MES_MCYCLE_HI_BASE_IDX',
|
|
'regCP_MES_MCYCLE_LO', 'regCP_MES_MCYCLE_LO_BASE_IDX',
|
|
'regCP_MES_MDBASE_HI', 'regCP_MES_MDBASE_HI_BASE_IDX',
|
|
'regCP_MES_MDBASE_LO', 'regCP_MES_MDBASE_LO_BASE_IDX',
|
|
'regCP_MES_MDBOUND_HI', 'regCP_MES_MDBOUND_HI_BASE_IDX',
|
|
'regCP_MES_MDBOUND_LO', 'regCP_MES_MDBOUND_LO_BASE_IDX',
|
|
'regCP_MES_MEPC_HI', 'regCP_MES_MEPC_HI_BASE_IDX',
|
|
'regCP_MES_MEPC_LO', 'regCP_MES_MEPC_LO_BASE_IDX',
|
|
'regCP_MES_MHARTID_HI', 'regCP_MES_MHARTID_HI_BASE_IDX',
|
|
'regCP_MES_MHARTID_LO', 'regCP_MES_MHARTID_LO_BASE_IDX',
|
|
'regCP_MES_MIBASE_HI', 'regCP_MES_MIBASE_HI_BASE_IDX',
|
|
'regCP_MES_MIBASE_LO', 'regCP_MES_MIBASE_LO_BASE_IDX',
|
|
'regCP_MES_MIBOUND_HI', 'regCP_MES_MIBOUND_HI_BASE_IDX',
|
|
'regCP_MES_MIBOUND_LO', 'regCP_MES_MIBOUND_LO_BASE_IDX',
|
|
'regCP_MES_MIE_HI', 'regCP_MES_MIE_HI_BASE_IDX',
|
|
'regCP_MES_MIE_LO', 'regCP_MES_MIE_LO_BASE_IDX',
|
|
'regCP_MES_MIMPID_HI', 'regCP_MES_MIMPID_HI_BASE_IDX',
|
|
'regCP_MES_MIMPID_LO', 'regCP_MES_MIMPID_LO_BASE_IDX',
|
|
'regCP_MES_MINSTRET_HI', 'regCP_MES_MINSTRET_HI_BASE_IDX',
|
|
'regCP_MES_MINSTRET_LO', 'regCP_MES_MINSTRET_LO_BASE_IDX',
|
|
'regCP_MES_MIP_HI', 'regCP_MES_MIP_HI_BASE_IDX',
|
|
'regCP_MES_MIP_LO', 'regCP_MES_MIP_LO_BASE_IDX',
|
|
'regCP_MES_MISA_HI', 'regCP_MES_MISA_HI_BASE_IDX',
|
|
'regCP_MES_MISA_LO', 'regCP_MES_MISA_LO_BASE_IDX',
|
|
'regCP_MES_MSCRATCH_HI', 'regCP_MES_MSCRATCH_HI_BASE_IDX',
|
|
'regCP_MES_MSCRATCH_LO', 'regCP_MES_MSCRATCH_LO_BASE_IDX',
|
|
'regCP_MES_MSTATUS_HI', 'regCP_MES_MSTATUS_HI_BASE_IDX',
|
|
'regCP_MES_MSTATUS_LO', 'regCP_MES_MSTATUS_LO_BASE_IDX',
|
|
'regCP_MES_MTIMECMP_HI', 'regCP_MES_MTIMECMP_HI_BASE_IDX',
|
|
'regCP_MES_MTIMECMP_LO', 'regCP_MES_MTIMECMP_LO_BASE_IDX',
|
|
'regCP_MES_MTIME_HI', 'regCP_MES_MTIME_HI_BASE_IDX',
|
|
'regCP_MES_MTIME_LO', 'regCP_MES_MTIME_LO_BASE_IDX',
|
|
'regCP_MES_MTVEC_HI', 'regCP_MES_MTVEC_HI_BASE_IDX',
|
|
'regCP_MES_MTVEC_LO', 'regCP_MES_MTVEC_LO_BASE_IDX',
|
|
'regCP_MES_MVENDORID_HI', 'regCP_MES_MVENDORID_HI_BASE_IDX',
|
|
'regCP_MES_MVENDORID_LO', 'regCP_MES_MVENDORID_LO_BASE_IDX',
|
|
'regCP_MES_PENDING_INTERRUPT',
|
|
'regCP_MES_PENDING_INTERRUPT_BASE_IDX',
|
|
'regCP_MES_PERFCOUNT_CNTL', 'regCP_MES_PERFCOUNT_CNTL_BASE_IDX',
|
|
'regCP_MES_PIPE0_PRIORITY', 'regCP_MES_PIPE0_PRIORITY_BASE_IDX',
|
|
'regCP_MES_PIPE1_PRIORITY', 'regCP_MES_PIPE1_PRIORITY_BASE_IDX',
|
|
'regCP_MES_PIPE2_PRIORITY', 'regCP_MES_PIPE2_PRIORITY_BASE_IDX',
|
|
'regCP_MES_PIPE3_PRIORITY', 'regCP_MES_PIPE3_PRIORITY_BASE_IDX',
|
|
'regCP_MES_PIPE_PRIORITY_CNTS',
|
|
'regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX',
|
|
'regCP_MES_PRGRM_CNTR_START',
|
|
'regCP_MES_PRGRM_CNTR_START_BASE_IDX',
|
|
'regCP_MES_PRGRM_CNTR_START_HI',
|
|
'regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX',
|
|
'regCP_MES_PROCESS_QUANTUM_PIPE0',
|
|
'regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX',
|
|
'regCP_MES_PROCESS_QUANTUM_PIPE1',
|
|
'regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX',
|
|
'regCP_MES_SCRATCH_DATA', 'regCP_MES_SCRATCH_DATA_BASE_IDX',
|
|
'regCP_MES_SCRATCH_INDEX', 'regCP_MES_SCRATCH_INDEX_BASE_IDX',
|
|
'regCP_ME_ATOMIC_PREOP_HI', 'regCP_ME_ATOMIC_PREOP_HI_BASE_IDX',
|
|
'regCP_ME_ATOMIC_PREOP_LO', 'regCP_ME_ATOMIC_PREOP_LO_BASE_IDX',
|
|
'regCP_ME_CNTL', 'regCP_ME_CNTL_BASE_IDX', 'regCP_ME_COHER_BASE',
|
|
'regCP_ME_COHER_BASE_BASE_IDX', 'regCP_ME_COHER_BASE_HI',
|
|
'regCP_ME_COHER_BASE_HI_BASE_IDX', 'regCP_ME_COHER_CNTL',
|
|
'regCP_ME_COHER_CNTL_BASE_IDX', 'regCP_ME_COHER_SIZE',
|
|
'regCP_ME_COHER_SIZE_BASE_IDX', 'regCP_ME_COHER_SIZE_HI',
|
|
'regCP_ME_COHER_SIZE_HI_BASE_IDX', 'regCP_ME_COHER_STATUS',
|
|
'regCP_ME_COHER_STATUS_BASE_IDX', 'regCP_ME_F32_INTERRUPT',
|
|
'regCP_ME_F32_INTERRUPT_BASE_IDX',
|
|
'regCP_ME_GDS_ATOMIC0_PREOP_HI',
|
|
'regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX',
|
|
'regCP_ME_GDS_ATOMIC0_PREOP_LO',
|
|
'regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX',
|
|
'regCP_ME_GDS_ATOMIC1_PREOP_HI',
|
|
'regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX',
|
|
'regCP_ME_GDS_ATOMIC1_PREOP_LO',
|
|
'regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'regCP_ME_HEADER_DUMP',
|
|
'regCP_ME_HEADER_DUMP_BASE_IDX', 'regCP_ME_IC_BASE_CNTL',
|
|
'regCP_ME_IC_BASE_CNTL_BASE_IDX', 'regCP_ME_IC_BASE_HI',
|
|
'regCP_ME_IC_BASE_HI_BASE_IDX', 'regCP_ME_IC_BASE_LO',
|
|
'regCP_ME_IC_BASE_LO_BASE_IDX', 'regCP_ME_IC_OP_CNTL',
|
|
'regCP_ME_IC_OP_CNTL_BASE_IDX', 'regCP_ME_INSTR_PNTR',
|
|
'regCP_ME_INSTR_PNTR_BASE_IDX', 'regCP_ME_INTR_ROUTINE_START',
|
|
'regCP_ME_INTR_ROUTINE_START_BASE_IDX',
|
|
'regCP_ME_INTR_ROUTINE_START_HI',
|
|
'regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX', 'regCP_ME_MC_RADDR_HI',
|
|
'regCP_ME_MC_RADDR_HI_BASE_IDX', 'regCP_ME_MC_RADDR_LO',
|
|
'regCP_ME_MC_RADDR_LO_BASE_IDX', 'regCP_ME_MC_WADDR_HI',
|
|
'regCP_ME_MC_WADDR_HI_BASE_IDX', 'regCP_ME_MC_WADDR_LO',
|
|
'regCP_ME_MC_WADDR_LO_BASE_IDX', 'regCP_ME_MC_WDATA_HI',
|
|
'regCP_ME_MC_WDATA_HI_BASE_IDX', 'regCP_ME_MC_WDATA_LO',
|
|
'regCP_ME_MC_WDATA_LO_BASE_IDX', 'regCP_ME_PREEMPTION',
|
|
'regCP_ME_PREEMPTION_BASE_IDX', 'regCP_ME_PRGRM_CNTR_START',
|
|
'regCP_ME_PRGRM_CNTR_START_BASE_IDX',
|
|
'regCP_ME_PRGRM_CNTR_START_HI',
|
|
'regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_ME_RAM_DATA',
|
|
'regCP_ME_RAM_DATA_BASE_IDX', 'regCP_ME_RAM_RADDR',
|
|
'regCP_ME_RAM_RADDR_BASE_IDX', 'regCP_ME_RAM_WADDR',
|
|
'regCP_ME_RAM_WADDR_BASE_IDX', 'regCP_ME_SDMA_CS',
|
|
'regCP_ME_SDMA_CS_BASE_IDX', 'regCP_MQD_BASE_ADDR',
|
|
'regCP_MQD_BASE_ADDR_BASE_IDX', 'regCP_MQD_BASE_ADDR_HI',
|
|
'regCP_MQD_BASE_ADDR_HI_BASE_IDX', 'regCP_MQD_CONTROL',
|
|
'regCP_MQD_CONTROL_BASE_IDX', 'regCP_PA_CINVOC_COUNT_HI',
|
|
'regCP_PA_CINVOC_COUNT_HI_BASE_IDX', 'regCP_PA_CINVOC_COUNT_LO',
|
|
'regCP_PA_CINVOC_COUNT_LO_BASE_IDX', 'regCP_PA_CPRIM_COUNT_HI',
|
|
'regCP_PA_CPRIM_COUNT_HI_BASE_IDX', 'regCP_PA_CPRIM_COUNT_LO',
|
|
'regCP_PA_CPRIM_COUNT_LO_BASE_IDX', 'regCP_PA_MSPRIM_COUNT_HI',
|
|
'regCP_PA_MSPRIM_COUNT_HI_BASE_IDX', 'regCP_PA_MSPRIM_COUNT_LO',
|
|
'regCP_PA_MSPRIM_COUNT_LO_BASE_IDX', 'regCP_PERFMON_CNTL',
|
|
'regCP_PERFMON_CNTL_BASE_IDX', 'regCP_PERFMON_CNTX_CNTL',
|
|
'regCP_PERFMON_CNTX_CNTL_BASE_IDX', 'regCP_PFP_ATOMIC_PREOP_HI',
|
|
'regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX', 'regCP_PFP_ATOMIC_PREOP_LO',
|
|
'regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX',
|
|
'regCP_PFP_COMPLETION_STATUS',
|
|
'regCP_PFP_COMPLETION_STATUS_BASE_IDX', 'regCP_PFP_F32_INTERRUPT',
|
|
'regCP_PFP_F32_INTERRUPT_BASE_IDX',
|
|
'regCP_PFP_GDS_ATOMIC0_PREOP_HI',
|
|
'regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX',
|
|
'regCP_PFP_GDS_ATOMIC0_PREOP_LO',
|
|
'regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX',
|
|
'regCP_PFP_GDS_ATOMIC1_PREOP_HI',
|
|
'regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX',
|
|
'regCP_PFP_GDS_ATOMIC1_PREOP_LO',
|
|
'regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX',
|
|
'regCP_PFP_HEADER_DUMP', 'regCP_PFP_HEADER_DUMP_BASE_IDX',
|
|
'regCP_PFP_IB_CONTROL', 'regCP_PFP_IB_CONTROL_BASE_IDX',
|
|
'regCP_PFP_IC_BASE_CNTL', 'regCP_PFP_IC_BASE_CNTL_BASE_IDX',
|
|
'regCP_PFP_IC_BASE_HI', 'regCP_PFP_IC_BASE_HI_BASE_IDX',
|
|
'regCP_PFP_IC_BASE_LO', 'regCP_PFP_IC_BASE_LO_BASE_IDX',
|
|
'regCP_PFP_IC_OP_CNTL', 'regCP_PFP_IC_OP_CNTL_BASE_IDX',
|
|
'regCP_PFP_INSTR_PNTR', 'regCP_PFP_INSTR_PNTR_BASE_IDX',
|
|
'regCP_PFP_INTR_ROUTINE_START',
|
|
'regCP_PFP_INTR_ROUTINE_START_BASE_IDX',
|
|
'regCP_PFP_INTR_ROUTINE_START_HI',
|
|
'regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX', 'regCP_PFP_JT_STAT',
|
|
'regCP_PFP_JT_STAT_BASE_IDX', 'regCP_PFP_LOAD_CONTROL',
|
|
'regCP_PFP_LOAD_CONTROL_BASE_IDX', 'regCP_PFP_METADATA_BASE_ADDR',
|
|
'regCP_PFP_METADATA_BASE_ADDR_BASE_IDX',
|
|
'regCP_PFP_METADATA_BASE_ADDR_HI',
|
|
'regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX',
|
|
'regCP_PFP_PRGRM_CNTR_START',
|
|
'regCP_PFP_PRGRM_CNTR_START_BASE_IDX',
|
|
'regCP_PFP_PRGRM_CNTR_START_HI',
|
|
'regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_PFP_SDMA_CS',
|
|
'regCP_PFP_SDMA_CS_BASE_IDX', 'regCP_PFP_UCODE_ADDR',
|
|
'regCP_PFP_UCODE_ADDR_BASE_IDX', 'regCP_PFP_UCODE_DATA',
|
|
'regCP_PFP_UCODE_DATA_BASE_IDX', 'regCP_PIPEID',
|
|
'regCP_PIPEID_BASE_IDX', 'regCP_PIPE_STATS_ADDR_HI',
|
|
'regCP_PIPE_STATS_ADDR_HI_BASE_IDX', 'regCP_PIPE_STATS_ADDR_LO',
|
|
'regCP_PIPE_STATS_ADDR_LO_BASE_IDX', 'regCP_PIPE_STATS_CONTROL',
|
|
'regCP_PIPE_STATS_CONTROL_BASE_IDX', 'regCP_PQ_STATUS',
|
|
'regCP_PQ_STATUS_BASE_IDX', 'regCP_PQ_WPTR_POLL_CNTL',
|
|
'regCP_PQ_WPTR_POLL_CNTL1', 'regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX',
|
|
'regCP_PQ_WPTR_POLL_CNTL_BASE_IDX', 'regCP_PRED_NOT_VISIBLE',
|
|
'regCP_PRED_NOT_VISIBLE_BASE_IDX', 'regCP_PRIV_VIOLATION_ADDR',
|
|
'regCP_PRIV_VIOLATION_ADDR_BASE_IDX', 'regCP_PROCESS_QUANTUM',
|
|
'regCP_PROCESS_QUANTUM_BASE_IDX', 'regCP_PWR_CNTL',
|
|
'regCP_PWR_CNTL_BASE_IDX', 'regCP_RB0_ACTIVE',
|
|
'regCP_RB0_ACTIVE_BASE_IDX', 'regCP_RB0_BASE',
|
|
'regCP_RB0_BASE_BASE_IDX', 'regCP_RB0_BASE_HI',
|
|
'regCP_RB0_BASE_HI_BASE_IDX', 'regCP_RB0_BUFSZ_MASK',
|
|
'regCP_RB0_BUFSZ_MASK_BASE_IDX', 'regCP_RB0_CNTL',
|
|
'regCP_RB0_CNTL_BASE_IDX', 'regCP_RB0_RPTR',
|
|
'regCP_RB0_RPTR_ADDR', 'regCP_RB0_RPTR_ADDR_BASE_IDX',
|
|
'regCP_RB0_RPTR_ADDR_HI', 'regCP_RB0_RPTR_ADDR_HI_BASE_IDX',
|
|
'regCP_RB0_RPTR_BASE_IDX', 'regCP_RB0_WPTR',
|
|
'regCP_RB0_WPTR_BASE_IDX', 'regCP_RB0_WPTR_HI',
|
|
'regCP_RB0_WPTR_HI_BASE_IDX', 'regCP_RB1_ACTIVE',
|
|
'regCP_RB1_ACTIVE_BASE_IDX', 'regCP_RB1_BASE',
|
|
'regCP_RB1_BASE_BASE_IDX', 'regCP_RB1_BASE_HI',
|
|
'regCP_RB1_BASE_HI_BASE_IDX', 'regCP_RB1_BUFSZ_MASK',
|
|
'regCP_RB1_BUFSZ_MASK_BASE_IDX', 'regCP_RB1_CNTL',
|
|
'regCP_RB1_CNTL_BASE_IDX', 'regCP_RB1_RPTR',
|
|
'regCP_RB1_RPTR_ADDR', 'regCP_RB1_RPTR_ADDR_BASE_IDX',
|
|
'regCP_RB1_RPTR_ADDR_HI', 'regCP_RB1_RPTR_ADDR_HI_BASE_IDX',
|
|
'regCP_RB1_RPTR_BASE_IDX', 'regCP_RB1_WPTR',
|
|
'regCP_RB1_WPTR_BASE_IDX', 'regCP_RB1_WPTR_HI',
|
|
'regCP_RB1_WPTR_HI_BASE_IDX', 'regCP_RB_ACTIVE',
|
|
'regCP_RB_ACTIVE_BASE_IDX', 'regCP_RB_BASE',
|
|
'regCP_RB_BASE_BASE_IDX', 'regCP_RB_BUFSZ_MASK',
|
|
'regCP_RB_BUFSZ_MASK_BASE_IDX', 'regCP_RB_CNTL',
|
|
'regCP_RB_CNTL_BASE_IDX', 'regCP_RB_DOORBELL_CLEAR',
|
|
'regCP_RB_DOORBELL_CLEAR_BASE_IDX', 'regCP_RB_DOORBELL_CONTROL',
|
|
'regCP_RB_DOORBELL_CONTROL_BASE_IDX',
|
|
'regCP_RB_DOORBELL_RANGE_LOWER',
|
|
'regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX',
|
|
'regCP_RB_DOORBELL_RANGE_UPPER',
|
|
'regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX', 'regCP_RB_OFFSET',
|
|
'regCP_RB_OFFSET_BASE_IDX', 'regCP_RB_RPTR', 'regCP_RB_RPTR_ADDR',
|
|
'regCP_RB_RPTR_ADDR_BASE_IDX', 'regCP_RB_RPTR_ADDR_HI',
|
|
'regCP_RB_RPTR_ADDR_HI_BASE_IDX', 'regCP_RB_RPTR_BASE_IDX',
|
|
'regCP_RB_RPTR_WR', 'regCP_RB_RPTR_WR_BASE_IDX',
|
|
'regCP_RB_STATUS', 'regCP_RB_STATUS_BASE_IDX', 'regCP_RB_VMID',
|
|
'regCP_RB_VMID_BASE_IDX', 'regCP_RB_WPTR',
|
|
'regCP_RB_WPTR_BASE_IDX', 'regCP_RB_WPTR_DELAY',
|
|
'regCP_RB_WPTR_DELAY_BASE_IDX', 'regCP_RB_WPTR_HI',
|
|
'regCP_RB_WPTR_HI_BASE_IDX', 'regCP_RB_WPTR_POLL_ADDR_HI',
|
|
'regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regCP_RB_WPTR_POLL_ADDR_LO',
|
|
'regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX', 'regCP_RB_WPTR_POLL_CNTL',
|
|
'regCP_RB_WPTR_POLL_CNTL_BASE_IDX', 'regCP_RING0_PRIORITY',
|
|
'regCP_RING0_PRIORITY_BASE_IDX', 'regCP_RING1_PRIORITY',
|
|
'regCP_RING1_PRIORITY_BASE_IDX', 'regCP_RINGID',
|
|
'regCP_RINGID_BASE_IDX', 'regCP_RING_PRIORITY_CNTS',
|
|
'regCP_RING_PRIORITY_CNTS_BASE_IDX', 'regCP_ROQ1_THRESHOLDS',
|
|
'regCP_ROQ1_THRESHOLDS_BASE_IDX', 'regCP_ROQ2_AVAIL',
|
|
'regCP_ROQ2_AVAIL_BASE_IDX', 'regCP_ROQ2_THRESHOLDS',
|
|
'regCP_ROQ2_THRESHOLDS_BASE_IDX', 'regCP_ROQ3_THRESHOLDS',
|
|
'regCP_ROQ3_THRESHOLDS_BASE_IDX', 'regCP_ROQ_AVAIL',
|
|
'regCP_ROQ_AVAIL_BASE_IDX', 'regCP_ROQ_DB_STAT',
|
|
'regCP_ROQ_DB_STAT_BASE_IDX', 'regCP_ROQ_IB1_STAT',
|
|
'regCP_ROQ_IB1_STAT_BASE_IDX', 'regCP_ROQ_IB2_STAT',
|
|
'regCP_ROQ_IB2_STAT_BASE_IDX', 'regCP_ROQ_RB_STAT',
|
|
'regCP_ROQ_RB_STAT_BASE_IDX', 'regCP_SAMPLE_STATUS',
|
|
'regCP_SAMPLE_STATUS_BASE_IDX', 'regCP_SCRATCH_DATA',
|
|
'regCP_SCRATCH_DATA_BASE_IDX', 'regCP_SCRATCH_INDEX',
|
|
'regCP_SCRATCH_INDEX_BASE_IDX', 'regCP_SC_PSINVOC_COUNT0_HI',
|
|
'regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX',
|
|
'regCP_SC_PSINVOC_COUNT0_LO',
|
|
'regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX',
|
|
'regCP_SC_PSINVOC_COUNT1_HI',
|
|
'regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX',
|
|
'regCP_SC_PSINVOC_COUNT1_LO',
|
|
'regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX', 'regCP_SDMA_DMA_DONE',
|
|
'regCP_SDMA_DMA_DONE_BASE_IDX', 'regCP_SD_CNTL',
|
|
'regCP_SD_CNTL_BASE_IDX', 'regCP_SEM_WAIT_TIMER',
|
|
'regCP_SEM_WAIT_TIMER_BASE_IDX', 'regCP_SIG_SEM_ADDR_HI',
|
|
'regCP_SIG_SEM_ADDR_HI_BASE_IDX', 'regCP_SIG_SEM_ADDR_LO',
|
|
'regCP_SIG_SEM_ADDR_LO_BASE_IDX', 'regCP_SOFT_RESET_CNTL',
|
|
'regCP_SOFT_RESET_CNTL_BASE_IDX', 'regCP_STALLED_STAT1',
|
|
'regCP_STALLED_STAT1_BASE_IDX', 'regCP_STALLED_STAT2',
|
|
'regCP_STALLED_STAT2_BASE_IDX', 'regCP_STALLED_STAT3',
|
|
'regCP_STALLED_STAT3_BASE_IDX', 'regCP_STAT',
|
|
'regCP_STAT_BASE_IDX', 'regCP_STQ_AVAIL',
|
|
'regCP_STQ_AVAIL_BASE_IDX', 'regCP_STQ_STAT',
|
|
'regCP_STQ_STAT_BASE_IDX', 'regCP_STQ_THRESHOLDS',
|
|
'regCP_STQ_THRESHOLDS_BASE_IDX', 'regCP_STQ_WR_STAT',
|
|
'regCP_STQ_WR_STAT_BASE_IDX', 'regCP_ST_BASE_HI',
|
|
'regCP_ST_BASE_HI_BASE_IDX', 'regCP_ST_BASE_LO',
|
|
'regCP_ST_BASE_LO_BASE_IDX', 'regCP_ST_BUFSZ',
|
|
'regCP_ST_BUFSZ_BASE_IDX', 'regCP_ST_CMD_BUFSZ',
|
|
'regCP_ST_CMD_BUFSZ_BASE_IDX', 'regCP_SUSPEND_CNTL',
|
|
'regCP_SUSPEND_CNTL_BASE_IDX', 'regCP_SUSPEND_RESUME_REQ',
|
|
'regCP_SUSPEND_RESUME_REQ_BASE_IDX', 'regCP_VGT_ASINVOC_COUNT_HI',
|
|
'regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX',
|
|
'regCP_VGT_ASINVOC_COUNT_LO',
|
|
'regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX',
|
|
'regCP_VGT_CSINVOC_COUNT_HI',
|
|
'regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX',
|
|
'regCP_VGT_CSINVOC_COUNT_LO',
|
|
'regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX',
|
|
'regCP_VGT_DSINVOC_COUNT_HI',
|
|
'regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX',
|
|
'regCP_VGT_DSINVOC_COUNT_LO',
|
|
'regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX',
|
|
'regCP_VGT_GSINVOC_COUNT_HI',
|
|
'regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX',
|
|
'regCP_VGT_GSINVOC_COUNT_LO',
|
|
'regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX',
|
|
'regCP_VGT_GSPRIM_COUNT_HI', 'regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX',
|
|
'regCP_VGT_GSPRIM_COUNT_LO', 'regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX',
|
|
'regCP_VGT_HSINVOC_COUNT_HI',
|
|
'regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX',
|
|
'regCP_VGT_HSINVOC_COUNT_LO',
|
|
'regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX',
|
|
'regCP_VGT_IAPRIM_COUNT_HI', 'regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX',
|
|
'regCP_VGT_IAPRIM_COUNT_LO', 'regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX',
|
|
'regCP_VGT_IAVERT_COUNT_HI', 'regCP_VGT_IAVERT_COUNT_HI_BASE_IDX',
|
|
'regCP_VGT_IAVERT_COUNT_LO', 'regCP_VGT_IAVERT_COUNT_LO_BASE_IDX',
|
|
'regCP_VGT_VSINVOC_COUNT_HI',
|
|
'regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX',
|
|
'regCP_VGT_VSINVOC_COUNT_LO',
|
|
'regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX', 'regCP_VIRT_STATUS',
|
|
'regCP_VIRT_STATUS_BASE_IDX', 'regCP_VMID', 'regCP_VMID_BASE_IDX',
|
|
'regCP_VMID_PREEMPT', 'regCP_VMID_PREEMPT_BASE_IDX',
|
|
'regCP_VMID_RESET', 'regCP_VMID_RESET_BASE_IDX',
|
|
'regCP_VMID_STATUS', 'regCP_VMID_STATUS_BASE_IDX',
|
|
'regCP_WAIT_REG_MEM_TIMEOUT',
|
|
'regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX', 'regCP_WAIT_SEM_ADDR_HI',
|
|
'regCP_WAIT_SEM_ADDR_HI_BASE_IDX', 'regCP_WAIT_SEM_ADDR_LO',
|
|
'regCP_WAIT_SEM_ADDR_LO_BASE_IDX', 'regDB_ALPHA_TO_MASK',
|
|
'regDB_ALPHA_TO_MASK_BASE_IDX', 'regDB_CGTT_CLK_CTRL_0',
|
|
'regDB_CGTT_CLK_CTRL_0_BASE_IDX', 'regDB_COUNT_CONTROL',
|
|
'regDB_COUNT_CONTROL_BASE_IDX', 'regDB_CREDIT_LIMIT',
|
|
'regDB_CREDIT_LIMIT_BASE_IDX', 'regDB_DEBUG', 'regDB_DEBUG2',
|
|
'regDB_DEBUG2_BASE_IDX', 'regDB_DEBUG3', 'regDB_DEBUG3_BASE_IDX',
|
|
'regDB_DEBUG4', 'regDB_DEBUG4_BASE_IDX', 'regDB_DEBUG5',
|
|
'regDB_DEBUG5_BASE_IDX', 'regDB_DEBUG6', 'regDB_DEBUG6_BASE_IDX',
|
|
'regDB_DEBUG7', 'regDB_DEBUG7_BASE_IDX', 'regDB_DEBUG_BASE_IDX',
|
|
'regDB_DEPTH_BOUNDS_MAX', 'regDB_DEPTH_BOUNDS_MAX_BASE_IDX',
|
|
'regDB_DEPTH_BOUNDS_MIN', 'regDB_DEPTH_BOUNDS_MIN_BASE_IDX',
|
|
'regDB_DEPTH_CLEAR', 'regDB_DEPTH_CLEAR_BASE_IDX',
|
|
'regDB_DEPTH_CONTROL', 'regDB_DEPTH_CONTROL_BASE_IDX',
|
|
'regDB_DEPTH_SIZE_XY', 'regDB_DEPTH_SIZE_XY_BASE_IDX',
|
|
'regDB_DEPTH_VIEW', 'regDB_DEPTH_VIEW_BASE_IDX', 'regDB_EQAA',
|
|
'regDB_EQAA_BASE_IDX', 'regDB_EQUAD_STUTTER_CONTROL',
|
|
'regDB_EQUAD_STUTTER_CONTROL_BASE_IDX',
|
|
'regDB_ETILE_STUTTER_CONTROL',
|
|
'regDB_ETILE_STUTTER_CONTROL_BASE_IDX', 'regDB_EXCEPTION_CONTROL',
|
|
'regDB_EXCEPTION_CONTROL_BASE_IDX',
|
|
'regDB_FGCG_INTERFACES_CLK_CTRL',
|
|
'regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX',
|
|
'regDB_FGCG_SRAMS_CLK_CTRL', 'regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX',
|
|
'regDB_FIFO_DEPTH1', 'regDB_FIFO_DEPTH1_BASE_IDX',
|
|
'regDB_FIFO_DEPTH2', 'regDB_FIFO_DEPTH2_BASE_IDX',
|
|
'regDB_FIFO_DEPTH3', 'regDB_FIFO_DEPTH3_BASE_IDX',
|
|
'regDB_FIFO_DEPTH4', 'regDB_FIFO_DEPTH4_BASE_IDX',
|
|
'regDB_FREE_CACHELINES', 'regDB_FREE_CACHELINES_BASE_IDX',
|
|
'regDB_HTILE_DATA_BASE', 'regDB_HTILE_DATA_BASE_BASE_IDX',
|
|
'regDB_HTILE_DATA_BASE_HI', 'regDB_HTILE_DATA_BASE_HI_BASE_IDX',
|
|
'regDB_HTILE_SURFACE', 'regDB_HTILE_SURFACE_BASE_IDX',
|
|
'regDB_LAST_OF_BURST_CONFIG',
|
|
'regDB_LAST_OF_BURST_CONFIG_BASE_IDX',
|
|
'regDB_LQUAD_STUTTER_CONTROL',
|
|
'regDB_LQUAD_STUTTER_CONTROL_BASE_IDX',
|
|
'regDB_LTILE_STUTTER_CONTROL',
|
|
'regDB_LTILE_STUTTER_CONTROL_BASE_IDX',
|
|
'regDB_MEM_ARB_WATERMARKS', 'regDB_MEM_ARB_WATERMARKS_BASE_IDX',
|
|
'regDB_OCCLUSION_COUNT0_HI', 'regDB_OCCLUSION_COUNT0_HI_BASE_IDX',
|
|
'regDB_OCCLUSION_COUNT0_LOW',
|
|
'regDB_OCCLUSION_COUNT0_LOW_BASE_IDX',
|
|
'regDB_OCCLUSION_COUNT1_HI', 'regDB_OCCLUSION_COUNT1_HI_BASE_IDX',
|
|
'regDB_OCCLUSION_COUNT1_LOW',
|
|
'regDB_OCCLUSION_COUNT1_LOW_BASE_IDX',
|
|
'regDB_OCCLUSION_COUNT2_HI', 'regDB_OCCLUSION_COUNT2_HI_BASE_IDX',
|
|
'regDB_OCCLUSION_COUNT2_LOW',
|
|
'regDB_OCCLUSION_COUNT2_LOW_BASE_IDX',
|
|
'regDB_OCCLUSION_COUNT3_HI', 'regDB_OCCLUSION_COUNT3_HI_BASE_IDX',
|
|
'regDB_OCCLUSION_COUNT3_LOW',
|
|
'regDB_OCCLUSION_COUNT3_LOW_BASE_IDX', 'regDB_PERFCOUNTER0_HI',
|
|
'regDB_PERFCOUNTER0_HI_BASE_IDX', 'regDB_PERFCOUNTER0_LO',
|
|
'regDB_PERFCOUNTER0_LO_BASE_IDX', 'regDB_PERFCOUNTER0_SELECT',
|
|
'regDB_PERFCOUNTER0_SELECT1',
|
|
'regDB_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regDB_PERFCOUNTER0_SELECT_BASE_IDX', 'regDB_PERFCOUNTER1_HI',
|
|
'regDB_PERFCOUNTER1_HI_BASE_IDX', 'regDB_PERFCOUNTER1_LO',
|
|
'regDB_PERFCOUNTER1_LO_BASE_IDX', 'regDB_PERFCOUNTER1_SELECT',
|
|
'regDB_PERFCOUNTER1_SELECT1',
|
|
'regDB_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regDB_PERFCOUNTER1_SELECT_BASE_IDX', 'regDB_PERFCOUNTER2_HI',
|
|
'regDB_PERFCOUNTER2_HI_BASE_IDX', 'regDB_PERFCOUNTER2_LO',
|
|
'regDB_PERFCOUNTER2_LO_BASE_IDX', 'regDB_PERFCOUNTER2_SELECT',
|
|
'regDB_PERFCOUNTER2_SELECT_BASE_IDX', 'regDB_PERFCOUNTER3_HI',
|
|
'regDB_PERFCOUNTER3_HI_BASE_IDX', 'regDB_PERFCOUNTER3_LO',
|
|
'regDB_PERFCOUNTER3_LO_BASE_IDX', 'regDB_PERFCOUNTER3_SELECT',
|
|
'regDB_PERFCOUNTER3_SELECT_BASE_IDX', 'regDB_PRELOAD_CONTROL',
|
|
'regDB_PRELOAD_CONTROL_BASE_IDX', 'regDB_RENDER_CONTROL',
|
|
'regDB_RENDER_CONTROL_BASE_IDX', 'regDB_RENDER_OVERRIDE',
|
|
'regDB_RENDER_OVERRIDE2', 'regDB_RENDER_OVERRIDE2_BASE_IDX',
|
|
'regDB_RENDER_OVERRIDE_BASE_IDX', 'regDB_RESERVED_REG_1',
|
|
'regDB_RESERVED_REG_1_BASE_IDX', 'regDB_RESERVED_REG_2',
|
|
'regDB_RESERVED_REG_2_BASE_IDX', 'regDB_RESERVED_REG_3',
|
|
'regDB_RESERVED_REG_3_BASE_IDX', 'regDB_RING_CONTROL',
|
|
'regDB_RING_CONTROL_BASE_IDX', 'regDB_RMI_L2_CACHE_CONTROL',
|
|
'regDB_RMI_L2_CACHE_CONTROL_BASE_IDX', 'regDB_SHADER_CONTROL',
|
|
'regDB_SHADER_CONTROL_BASE_IDX', 'regDB_SRESULTS_COMPARE_STATE0',
|
|
'regDB_SRESULTS_COMPARE_STATE0_BASE_IDX',
|
|
'regDB_SRESULTS_COMPARE_STATE1',
|
|
'regDB_SRESULTS_COMPARE_STATE1_BASE_IDX', 'regDB_STENCILREFMASK',
|
|
'regDB_STENCILREFMASK_BASE_IDX', 'regDB_STENCILREFMASK_BF',
|
|
'regDB_STENCILREFMASK_BF_BASE_IDX', 'regDB_STENCIL_CLEAR',
|
|
'regDB_STENCIL_CLEAR_BASE_IDX', 'regDB_STENCIL_CONTROL',
|
|
'regDB_STENCIL_CONTROL_BASE_IDX', 'regDB_STENCIL_INFO',
|
|
'regDB_STENCIL_INFO_BASE_IDX', 'regDB_STENCIL_READ_BASE',
|
|
'regDB_STENCIL_READ_BASE_BASE_IDX', 'regDB_STENCIL_READ_BASE_HI',
|
|
'regDB_STENCIL_READ_BASE_HI_BASE_IDX', 'regDB_STENCIL_WRITE_BASE',
|
|
'regDB_STENCIL_WRITE_BASE_BASE_IDX',
|
|
'regDB_STENCIL_WRITE_BASE_HI',
|
|
'regDB_STENCIL_WRITE_BASE_HI_BASE_IDX', 'regDB_SUBTILE_CONTROL',
|
|
'regDB_SUBTILE_CONTROL_BASE_IDX', 'regDB_WATERMARKS',
|
|
'regDB_WATERMARKS_BASE_IDX', 'regDB_Z_INFO',
|
|
'regDB_Z_INFO_BASE_IDX', 'regDB_Z_READ_BASE',
|
|
'regDB_Z_READ_BASE_BASE_IDX', 'regDB_Z_READ_BASE_HI',
|
|
'regDB_Z_READ_BASE_HI_BASE_IDX', 'regDB_Z_WRITE_BASE',
|
|
'regDB_Z_WRITE_BASE_BASE_IDX', 'regDB_Z_WRITE_BASE_HI',
|
|
'regDB_Z_WRITE_BASE_HI_BASE_IDX', 'regDIDT_EDC_CTRL',
|
|
'regDIDT_EDC_CTRL_BASE_IDX', 'regDIDT_EDC_DYNAMIC_THRESHOLD_RO',
|
|
'regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX',
|
|
'regDIDT_EDC_OVERFLOW', 'regDIDT_EDC_OVERFLOW_BASE_IDX',
|
|
'regDIDT_EDC_ROLLING_POWER_DELTA',
|
|
'regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX',
|
|
'regDIDT_EDC_STALL_PATTERN_1_2',
|
|
'regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX',
|
|
'regDIDT_EDC_STALL_PATTERN_3_4',
|
|
'regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX',
|
|
'regDIDT_EDC_STALL_PATTERN_5_6',
|
|
'regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX',
|
|
'regDIDT_EDC_STALL_PATTERN_7',
|
|
'regDIDT_EDC_STALL_PATTERN_7_BASE_IDX', 'regDIDT_EDC_STATUS',
|
|
'regDIDT_EDC_STATUS_BASE_IDX', 'regDIDT_EDC_THRESHOLD',
|
|
'regDIDT_EDC_THRESHOLD_BASE_IDX', 'regDIDT_EDC_THROTTLE_CTRL',
|
|
'regDIDT_EDC_THROTTLE_CTRL_BASE_IDX',
|
|
'regDIDT_INDEX_AUTO_INCR_EN',
|
|
'regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX', 'regDIDT_IND_DATA',
|
|
'regDIDT_IND_DATA_BASE_IDX', 'regDIDT_IND_INDEX',
|
|
'regDIDT_IND_INDEX_BASE_IDX', 'regDIDT_STALL_PATTERN_1_2',
|
|
'regDIDT_STALL_PATTERN_1_2_BASE_IDX', 'regDIDT_STALL_PATTERN_3_4',
|
|
'regDIDT_STALL_PATTERN_3_4_BASE_IDX', 'regDIDT_STALL_PATTERN_5_6',
|
|
'regDIDT_STALL_PATTERN_5_6_BASE_IDX', 'regDIDT_STALL_PATTERN_7',
|
|
'regDIDT_STALL_PATTERN_7_BASE_IDX', 'regDIDT_STALL_PATTERN_CTRL',
|
|
'regDIDT_STALL_PATTERN_CTRL_BASE_IDX', 'regEDC_HYSTERESIS_CNTL',
|
|
'regEDC_HYSTERESIS_CNTL_BASE_IDX', 'regEDC_HYSTERESIS_STAT',
|
|
'regEDC_HYSTERESIS_STAT_BASE_IDX', 'regEDC_PERF_COUNTER',
|
|
'regEDC_PERF_COUNTER_BASE_IDX', 'regEDC_STRETCH_NUM_PERF_COUNTER',
|
|
'regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX',
|
|
'regEDC_STRETCH_PERF_COUNTER',
|
|
'regEDC_STRETCH_PERF_COUNTER_BASE_IDX',
|
|
'regEDC_UNSTRETCH_PERF_COUNTER',
|
|
'regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX', 'regGB_ADDR_CONFIG',
|
|
'regGB_ADDR_CONFIG_BASE_IDX', 'regGB_ADDR_CONFIG_READ',
|
|
'regGB_ADDR_CONFIG_READ_BASE_IDX', 'regGB_BACKEND_MAP',
|
|
'regGB_BACKEND_MAP_BASE_IDX', 'regGB_EDC_MODE',
|
|
'regGB_EDC_MODE_BASE_IDX', 'regGB_GPU_ID',
|
|
'regGB_GPU_ID_BASE_IDX', 'regGCEA_DRAM_PAGE_BURST',
|
|
'regGCEA_DRAM_PAGE_BURST_BASE_IDX', 'regGCEA_DRAM_RD_CAM_CNTL',
|
|
'regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX',
|
|
'regGCEA_DRAM_RD_CLI2GRP_MAP0',
|
|
'regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX',
|
|
'regGCEA_DRAM_RD_CLI2GRP_MAP1',
|
|
'regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX',
|
|
'regGCEA_DRAM_RD_GRP2VC_MAP',
|
|
'regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX', 'regGCEA_DRAM_RD_LAZY',
|
|
'regGCEA_DRAM_RD_LAZY_BASE_IDX', 'regGCEA_DRAM_RD_PRI_AGE',
|
|
'regGCEA_DRAM_RD_PRI_AGE_BASE_IDX', 'regGCEA_DRAM_RD_PRI_FIXED',
|
|
'regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX',
|
|
'regGCEA_DRAM_RD_PRI_QUANT_PRI1',
|
|
'regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX',
|
|
'regGCEA_DRAM_RD_PRI_QUANT_PRI2',
|
|
'regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX',
|
|
'regGCEA_DRAM_RD_PRI_QUANT_PRI3',
|
|
'regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX',
|
|
'regGCEA_DRAM_RD_PRI_QUEUING',
|
|
'regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX',
|
|
'regGCEA_DRAM_RD_PRI_URGENCY',
|
|
'regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX',
|
|
'regGCEA_DRAM_WR_CAM_CNTL', 'regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX',
|
|
'regGCEA_DRAM_WR_CLI2GRP_MAP0',
|
|
'regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX',
|
|
'regGCEA_DRAM_WR_CLI2GRP_MAP1',
|
|
'regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX',
|
|
'regGCEA_DRAM_WR_GRP2VC_MAP',
|
|
'regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX', 'regGCEA_DRAM_WR_LAZY',
|
|
'regGCEA_DRAM_WR_LAZY_BASE_IDX', 'regGCEA_DRAM_WR_PRI_AGE',
|
|
'regGCEA_DRAM_WR_PRI_AGE_BASE_IDX', 'regGCEA_DRAM_WR_PRI_FIXED',
|
|
'regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX',
|
|
'regGCEA_DRAM_WR_PRI_QUANT_PRI1',
|
|
'regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX',
|
|
'regGCEA_DRAM_WR_PRI_QUANT_PRI2',
|
|
'regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX',
|
|
'regGCEA_DRAM_WR_PRI_QUANT_PRI3',
|
|
'regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX',
|
|
'regGCEA_DRAM_WR_PRI_QUEUING',
|
|
'regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX',
|
|
'regGCEA_DRAM_WR_PRI_URGENCY',
|
|
'regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX', 'regGCEA_DSM_CNTL',
|
|
'regGCEA_DSM_CNTL2', 'regGCEA_DSM_CNTL2A',
|
|
'regGCEA_DSM_CNTL2A_BASE_IDX', 'regGCEA_DSM_CNTL2B',
|
|
'regGCEA_DSM_CNTL2B_BASE_IDX', 'regGCEA_DSM_CNTL2_BASE_IDX',
|
|
'regGCEA_DSM_CNTLA', 'regGCEA_DSM_CNTLA_BASE_IDX',
|
|
'regGCEA_DSM_CNTLB', 'regGCEA_DSM_CNTLB_BASE_IDX',
|
|
'regGCEA_DSM_CNTL_BASE_IDX', 'regGCEA_EDC_CNT',
|
|
'regGCEA_EDC_CNT2', 'regGCEA_EDC_CNT2_BASE_IDX',
|
|
'regGCEA_EDC_CNT3', 'regGCEA_EDC_CNT3_BASE_IDX',
|
|
'regGCEA_EDC_CNT_BASE_IDX', 'regGCEA_ERR_STATUS',
|
|
'regGCEA_ERR_STATUS_BASE_IDX', 'regGCEA_GL2C_XBR_CREDITS',
|
|
'regGCEA_GL2C_XBR_CREDITS_BASE_IDX', 'regGCEA_GL2C_XBR_MAXBURST',
|
|
'regGCEA_GL2C_XBR_MAXBURST_BASE_IDX', 'regGCEA_ICG_CTRL',
|
|
'regGCEA_ICG_CTRL_BASE_IDX', 'regGCEA_IO_GROUP_BURST',
|
|
'regGCEA_IO_GROUP_BURST_BASE_IDX', 'regGCEA_IO_RD_CLI2GRP_MAP0',
|
|
'regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX',
|
|
'regGCEA_IO_RD_CLI2GRP_MAP1',
|
|
'regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX',
|
|
'regGCEA_IO_RD_COMBINE_FLUSH',
|
|
'regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX', 'regGCEA_IO_RD_PRI_AGE',
|
|
'regGCEA_IO_RD_PRI_AGE_BASE_IDX', 'regGCEA_IO_RD_PRI_FIXED',
|
|
'regGCEA_IO_RD_PRI_FIXED_BASE_IDX',
|
|
'regGCEA_IO_RD_PRI_QUANT_PRI1',
|
|
'regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX',
|
|
'regGCEA_IO_RD_PRI_QUANT_PRI2',
|
|
'regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX',
|
|
'regGCEA_IO_RD_PRI_QUANT_PRI3',
|
|
'regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX',
|
|
'regGCEA_IO_RD_PRI_QUEUING', 'regGCEA_IO_RD_PRI_QUEUING_BASE_IDX',
|
|
'regGCEA_IO_RD_PRI_URGENCY', 'regGCEA_IO_RD_PRI_URGENCY_BASE_IDX',
|
|
'regGCEA_IO_RD_PRI_URGENCY_MASKING',
|
|
'regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX',
|
|
'regGCEA_IO_WR_CLI2GRP_MAP0',
|
|
'regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX',
|
|
'regGCEA_IO_WR_CLI2GRP_MAP1',
|
|
'regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX',
|
|
'regGCEA_IO_WR_COMBINE_FLUSH',
|
|
'regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX', 'regGCEA_IO_WR_PRI_AGE',
|
|
'regGCEA_IO_WR_PRI_AGE_BASE_IDX', 'regGCEA_IO_WR_PRI_FIXED',
|
|
'regGCEA_IO_WR_PRI_FIXED_BASE_IDX',
|
|
'regGCEA_IO_WR_PRI_QUANT_PRI1',
|
|
'regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX',
|
|
'regGCEA_IO_WR_PRI_QUANT_PRI2',
|
|
'regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX',
|
|
'regGCEA_IO_WR_PRI_QUANT_PRI3',
|
|
'regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX',
|
|
'regGCEA_IO_WR_PRI_QUEUING', 'regGCEA_IO_WR_PRI_QUEUING_BASE_IDX',
|
|
'regGCEA_IO_WR_PRI_URGENCY', 'regGCEA_IO_WR_PRI_URGENCY_BASE_IDX',
|
|
'regGCEA_IO_WR_PRI_URGENCY_MASKING',
|
|
'regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX',
|
|
'regGCEA_LATENCY_SAMPLING', 'regGCEA_LATENCY_SAMPLING_BASE_IDX',
|
|
'regGCEA_MAM_CTRL', 'regGCEA_MAM_CTRL2',
|
|
'regGCEA_MAM_CTRL2_BASE_IDX', 'regGCEA_MAM_CTRL_BASE_IDX',
|
|
'regGCEA_MISC', 'regGCEA_MISC2', 'regGCEA_MISC2_BASE_IDX',
|
|
'regGCEA_MISC_BASE_IDX', 'regGCEA_PERFCOUNTER0_CFG',
|
|
'regGCEA_PERFCOUNTER0_CFG_BASE_IDX', 'regGCEA_PERFCOUNTER1_CFG',
|
|
'regGCEA_PERFCOUNTER1_CFG_BASE_IDX', 'regGCEA_PERFCOUNTER2_HI',
|
|
'regGCEA_PERFCOUNTER2_HI_BASE_IDX', 'regGCEA_PERFCOUNTER2_LO',
|
|
'regGCEA_PERFCOUNTER2_LO_BASE_IDX', 'regGCEA_PERFCOUNTER2_MODE',
|
|
'regGCEA_PERFCOUNTER2_MODE_BASE_IDX',
|
|
'regGCEA_PERFCOUNTER2_SELECT', 'regGCEA_PERFCOUNTER2_SELECT1',
|
|
'regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX',
|
|
'regGCEA_PERFCOUNTER2_SELECT_BASE_IDX', 'regGCEA_PERFCOUNTER_HI',
|
|
'regGCEA_PERFCOUNTER_HI_BASE_IDX', 'regGCEA_PERFCOUNTER_LO',
|
|
'regGCEA_PERFCOUNTER_LO_BASE_IDX',
|
|
'regGCEA_PERFCOUNTER_RSLT_CNTL',
|
|
'regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regGCEA_PROBE_CNTL',
|
|
'regGCEA_PROBE_CNTL_BASE_IDX', 'regGCEA_PROBE_MAP',
|
|
'regGCEA_PROBE_MAP_BASE_IDX', 'regGCEA_RRET_MEM_RESERVE',
|
|
'regGCEA_RRET_MEM_RESERVE_BASE_IDX', 'regGCEA_SDP_ARB_FINAL',
|
|
'regGCEA_SDP_ARB_FINAL_BASE_IDX', 'regGCEA_SDP_CREDITS',
|
|
'regGCEA_SDP_CREDITS_BASE_IDX', 'regGCEA_SDP_ENABLE',
|
|
'regGCEA_SDP_ENABLE_BASE_IDX', 'regGCEA_SDP_IO_PRIORITY',
|
|
'regGCEA_SDP_IO_PRIORITY_BASE_IDX', 'regGCEA_SDP_TAG_RESERVE0',
|
|
'regGCEA_SDP_TAG_RESERVE0_BASE_IDX', 'regGCEA_SDP_TAG_RESERVE1',
|
|
'regGCEA_SDP_TAG_RESERVE1_BASE_IDX', 'regGCEA_SDP_VCC_RESERVE0',
|
|
'regGCEA_SDP_VCC_RESERVE0_BASE_IDX', 'regGCEA_SDP_VCC_RESERVE1',
|
|
'regGCEA_SDP_VCC_RESERVE1_BASE_IDX', 'regGCMC_MEM_POWER_LS',
|
|
'regGCMC_MEM_POWER_LS_BASE_IDX', 'regGCMC_VM_AGP_BASE',
|
|
'regGCMC_VM_AGP_BASE_BASE_IDX', 'regGCMC_VM_AGP_BOT',
|
|
'regGCMC_VM_AGP_BOT_BASE_IDX', 'regGCMC_VM_AGP_TOP',
|
|
'regGCMC_VM_AGP_TOP_BASE_IDX', 'regGCMC_VM_APT_CNTL',
|
|
'regGCMC_VM_APT_CNTL_BASE_IDX',
|
|
'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END',
|
|
'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX',
|
|
'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START',
|
|
'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX',
|
|
'regGCMC_VM_FB_LOCATION_BASE',
|
|
'regGCMC_VM_FB_LOCATION_BASE_BASE_IDX',
|
|
'regGCMC_VM_FB_LOCATION_TOP',
|
|
'regGCMC_VM_FB_LOCATION_TOP_BASE_IDX',
|
|
'regGCMC_VM_FB_NOALLOC_CNTL',
|
|
'regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX', 'regGCMC_VM_FB_OFFSET',
|
|
'regGCMC_VM_FB_OFFSET_BASE_IDX', 'regGCMC_VM_FB_SIZE_OFFSET_VF0',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF1', 'regGCMC_VM_FB_SIZE_OFFSET_VF10',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF11',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF12',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF13',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF14',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF15',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF2',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF3',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF4',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF5',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF6',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF7',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF8',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF9',
|
|
'regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX',
|
|
'regGCMC_VM_L2_PERFCOUNTER0_CFG',
|
|
'regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX',
|
|
'regGCMC_VM_L2_PERFCOUNTER1_CFG',
|
|
'regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX',
|
|
'regGCMC_VM_L2_PERFCOUNTER2_CFG',
|
|
'regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX',
|
|
'regGCMC_VM_L2_PERFCOUNTER3_CFG',
|
|
'regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX',
|
|
'regGCMC_VM_L2_PERFCOUNTER4_CFG',
|
|
'regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX',
|
|
'regGCMC_VM_L2_PERFCOUNTER5_CFG',
|
|
'regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX',
|
|
'regGCMC_VM_L2_PERFCOUNTER6_CFG',
|
|
'regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX',
|
|
'regGCMC_VM_L2_PERFCOUNTER7_CFG',
|
|
'regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX',
|
|
'regGCMC_VM_L2_PERFCOUNTER_HI',
|
|
'regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX',
|
|
'regGCMC_VM_L2_PERFCOUNTER_LO',
|
|
'regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX',
|
|
'regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL',
|
|
'regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
|
|
'regGCMC_VM_LOCAL_FB_ADDRESS_END',
|
|
'regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX',
|
|
'regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL',
|
|
'regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX',
|
|
'regGCMC_VM_LOCAL_FB_ADDRESS_START',
|
|
'regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX',
|
|
'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END',
|
|
'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX',
|
|
'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START',
|
|
'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_HI_0', 'regGCMC_VM_MARC_BASE_HI_0_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_HI_1', 'regGCMC_VM_MARC_BASE_HI_10',
|
|
'regGCMC_VM_MARC_BASE_HI_10_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_HI_11',
|
|
'regGCMC_VM_MARC_BASE_HI_11_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_HI_12',
|
|
'regGCMC_VM_MARC_BASE_HI_12_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_HI_13',
|
|
'regGCMC_VM_MARC_BASE_HI_13_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_HI_14',
|
|
'regGCMC_VM_MARC_BASE_HI_14_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_HI_15',
|
|
'regGCMC_VM_MARC_BASE_HI_15_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_HI_1_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_2',
|
|
'regGCMC_VM_MARC_BASE_HI_2_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_3',
|
|
'regGCMC_VM_MARC_BASE_HI_3_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_4',
|
|
'regGCMC_VM_MARC_BASE_HI_4_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_5',
|
|
'regGCMC_VM_MARC_BASE_HI_5_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_6',
|
|
'regGCMC_VM_MARC_BASE_HI_6_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_7',
|
|
'regGCMC_VM_MARC_BASE_HI_7_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_8',
|
|
'regGCMC_VM_MARC_BASE_HI_8_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_9',
|
|
'regGCMC_VM_MARC_BASE_HI_9_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_0',
|
|
'regGCMC_VM_MARC_BASE_LO_0_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_1',
|
|
'regGCMC_VM_MARC_BASE_LO_10',
|
|
'regGCMC_VM_MARC_BASE_LO_10_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_LO_11',
|
|
'regGCMC_VM_MARC_BASE_LO_11_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_LO_12',
|
|
'regGCMC_VM_MARC_BASE_LO_12_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_LO_13',
|
|
'regGCMC_VM_MARC_BASE_LO_13_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_LO_14',
|
|
'regGCMC_VM_MARC_BASE_LO_14_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_LO_15',
|
|
'regGCMC_VM_MARC_BASE_LO_15_BASE_IDX',
|
|
'regGCMC_VM_MARC_BASE_LO_1_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_2',
|
|
'regGCMC_VM_MARC_BASE_LO_2_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_3',
|
|
'regGCMC_VM_MARC_BASE_LO_3_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_4',
|
|
'regGCMC_VM_MARC_BASE_LO_4_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_5',
|
|
'regGCMC_VM_MARC_BASE_LO_5_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_6',
|
|
'regGCMC_VM_MARC_BASE_LO_6_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_7',
|
|
'regGCMC_VM_MARC_BASE_LO_7_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_8',
|
|
'regGCMC_VM_MARC_BASE_LO_8_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_9',
|
|
'regGCMC_VM_MARC_BASE_LO_9_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_0',
|
|
'regGCMC_VM_MARC_LEN_HI_0_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_1',
|
|
'regGCMC_VM_MARC_LEN_HI_10', 'regGCMC_VM_MARC_LEN_HI_10_BASE_IDX',
|
|
'regGCMC_VM_MARC_LEN_HI_11', 'regGCMC_VM_MARC_LEN_HI_11_BASE_IDX',
|
|
'regGCMC_VM_MARC_LEN_HI_12', 'regGCMC_VM_MARC_LEN_HI_12_BASE_IDX',
|
|
'regGCMC_VM_MARC_LEN_HI_13', 'regGCMC_VM_MARC_LEN_HI_13_BASE_IDX',
|
|
'regGCMC_VM_MARC_LEN_HI_14', 'regGCMC_VM_MARC_LEN_HI_14_BASE_IDX',
|
|
'regGCMC_VM_MARC_LEN_HI_15', 'regGCMC_VM_MARC_LEN_HI_15_BASE_IDX',
|
|
'regGCMC_VM_MARC_LEN_HI_1_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_2',
|
|
'regGCMC_VM_MARC_LEN_HI_2_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_3',
|
|
'regGCMC_VM_MARC_LEN_HI_3_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_4',
|
|
'regGCMC_VM_MARC_LEN_HI_4_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_5',
|
|
'regGCMC_VM_MARC_LEN_HI_5_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_6',
|
|
'regGCMC_VM_MARC_LEN_HI_6_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_7',
|
|
'regGCMC_VM_MARC_LEN_HI_7_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_8',
|
|
'regGCMC_VM_MARC_LEN_HI_8_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_9',
|
|
'regGCMC_VM_MARC_LEN_HI_9_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_0',
|
|
'regGCMC_VM_MARC_LEN_LO_0_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_1',
|
|
'regGCMC_VM_MARC_LEN_LO_10', 'regGCMC_VM_MARC_LEN_LO_10_BASE_IDX',
|
|
'regGCMC_VM_MARC_LEN_LO_11', 'regGCMC_VM_MARC_LEN_LO_11_BASE_IDX',
|
|
'regGCMC_VM_MARC_LEN_LO_12', 'regGCMC_VM_MARC_LEN_LO_12_BASE_IDX',
|
|
'regGCMC_VM_MARC_LEN_LO_13', 'regGCMC_VM_MARC_LEN_LO_13_BASE_IDX',
|
|
'regGCMC_VM_MARC_LEN_LO_14', 'regGCMC_VM_MARC_LEN_LO_14_BASE_IDX',
|
|
'regGCMC_VM_MARC_LEN_LO_15', 'regGCMC_VM_MARC_LEN_LO_15_BASE_IDX',
|
|
'regGCMC_VM_MARC_LEN_LO_1_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_2',
|
|
'regGCMC_VM_MARC_LEN_LO_2_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_3',
|
|
'regGCMC_VM_MARC_LEN_LO_3_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_4',
|
|
'regGCMC_VM_MARC_LEN_LO_4_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_5',
|
|
'regGCMC_VM_MARC_LEN_LO_5_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_6',
|
|
'regGCMC_VM_MARC_LEN_LO_6_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_7',
|
|
'regGCMC_VM_MARC_LEN_LO_7_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_8',
|
|
'regGCMC_VM_MARC_LEN_LO_8_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_9',
|
|
'regGCMC_VM_MARC_LEN_LO_9_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_0',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_1',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_10',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_11',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_12',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_13',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_14',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_15',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_2',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_3',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_4',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_5',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_6',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_7',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_8',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_9',
|
|
'regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_0',
|
|
'regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_1', 'regGCMC_VM_MARC_RELOC_HI_10',
|
|
'regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_11',
|
|
'regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_12',
|
|
'regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_13',
|
|
'regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_14',
|
|
'regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_15',
|
|
'regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_2',
|
|
'regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_3',
|
|
'regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_4',
|
|
'regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_5',
|
|
'regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_6',
|
|
'regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_7',
|
|
'regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_8',
|
|
'regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_HI_9',
|
|
'regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_0',
|
|
'regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_1', 'regGCMC_VM_MARC_RELOC_LO_10',
|
|
'regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_11',
|
|
'regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_12',
|
|
'regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_13',
|
|
'regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_14',
|
|
'regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_15',
|
|
'regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_2',
|
|
'regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_3',
|
|
'regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_4',
|
|
'regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_5',
|
|
'regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_6',
|
|
'regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_7',
|
|
'regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_8',
|
|
'regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX',
|
|
'regGCMC_VM_MARC_RELOC_LO_9',
|
|
'regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX',
|
|
'regGCMC_VM_MX_L1_TLB_CNTL', 'regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX',
|
|
'regGCMC_VM_NB_LOWER_TOP_OF_DRAM2',
|
|
'regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX',
|
|
'regGCMC_VM_NB_TOP_OF_DRAM_SLOT1',
|
|
'regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX',
|
|
'regGCMC_VM_NB_UPPER_TOP_OF_DRAM2',
|
|
'regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX',
|
|
'regGCMC_VM_STEERING', 'regGCMC_VM_STEERING_BASE_IDX',
|
|
'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB',
|
|
'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX',
|
|
'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB',
|
|
'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX',
|
|
'regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR',
|
|
'regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX',
|
|
'regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR',
|
|
'regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX',
|
|
'regGCRD_CREDIT_SAFE', 'regGCRD_CREDIT_SAFE_BASE_IDX',
|
|
'regGCRD_SA0_TARGETS_DISABLE',
|
|
'regGCRD_SA0_TARGETS_DISABLE_BASE_IDX',
|
|
'regGCRD_SA1_TARGETS_DISABLE',
|
|
'regGCRD_SA1_TARGETS_DISABLE_BASE_IDX', 'regGCR_CMD_STATUS',
|
|
'regGCR_CMD_STATUS_BASE_IDX', 'regGCR_GENERAL_CNTL',
|
|
'regGCR_GENERAL_CNTL_BASE_IDX', 'regGCR_PERFCOUNTER0_HI',
|
|
'regGCR_PERFCOUNTER0_HI_BASE_IDX', 'regGCR_PERFCOUNTER0_LO',
|
|
'regGCR_PERFCOUNTER0_LO_BASE_IDX', 'regGCR_PERFCOUNTER0_SELECT',
|
|
'regGCR_PERFCOUNTER0_SELECT1',
|
|
'regGCR_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regGCR_PERFCOUNTER0_SELECT_BASE_IDX', 'regGCR_PERFCOUNTER1_HI',
|
|
'regGCR_PERFCOUNTER1_HI_BASE_IDX', 'regGCR_PERFCOUNTER1_LO',
|
|
'regGCR_PERFCOUNTER1_LO_BASE_IDX', 'regGCR_PERFCOUNTER1_SELECT',
|
|
'regGCR_PERFCOUNTER1_SELECT_BASE_IDX', 'regGCR_PIO_CNTL',
|
|
'regGCR_PIO_CNTL_BASE_IDX', 'regGCR_PIO_DATA',
|
|
'regGCR_PIO_DATA_BASE_IDX', 'regGCR_SPARE',
|
|
'regGCR_SPARE_BASE_IDX', 'regGCUTCL2_CGTT_BUSY_CTRL',
|
|
'regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX',
|
|
'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC',
|
|
'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX',
|
|
'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC',
|
|
'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX',
|
|
'regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC',
|
|
'regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX',
|
|
'regGCUTCL2_GROUP_RET_FAULT_STATUS',
|
|
'regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX',
|
|
'regGCUTCL2_HARVEST_BYPASS_GROUPS',
|
|
'regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX',
|
|
'regGCUTCL2_ICG_CTRL', 'regGCUTCL2_ICG_CTRL_BASE_IDX',
|
|
'regGCUTCL2_PERFCOUNTER0_CFG',
|
|
'regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX',
|
|
'regGCUTCL2_PERFCOUNTER1_CFG',
|
|
'regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX',
|
|
'regGCUTCL2_PERFCOUNTER2_CFG',
|
|
'regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX',
|
|
'regGCUTCL2_PERFCOUNTER3_CFG',
|
|
'regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX',
|
|
'regGCUTCL2_PERFCOUNTER_HI', 'regGCUTCL2_PERFCOUNTER_HI_BASE_IDX',
|
|
'regGCUTCL2_PERFCOUNTER_LO', 'regGCUTCL2_PERFCOUNTER_LO_BASE_IDX',
|
|
'regGCUTCL2_PERFCOUNTER_RSLT_CNTL',
|
|
'regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
|
|
'regGCUTCL2_TRANSLATION_BYPASS_BY_VMID',
|
|
'regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX',
|
|
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL',
|
|
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX',
|
|
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI',
|
|
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX',
|
|
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO',
|
|
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX',
|
|
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI',
|
|
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX',
|
|
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO',
|
|
'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX',
|
|
'regGCUTC_TRANSLATION_FAULT_CNTL0',
|
|
'regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX',
|
|
'regGCUTC_TRANSLATION_FAULT_CNTL1',
|
|
'regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX',
|
|
'regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT',
|
|
'regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX',
|
|
'regGCVML2_PERFCOUNTER2_0_HI',
|
|
'regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX',
|
|
'regGCVML2_PERFCOUNTER2_0_LO',
|
|
'regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX',
|
|
'regGCVML2_PERFCOUNTER2_0_MODE',
|
|
'regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX',
|
|
'regGCVML2_PERFCOUNTER2_0_SELECT',
|
|
'regGCVML2_PERFCOUNTER2_0_SELECT1',
|
|
'regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX',
|
|
'regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX',
|
|
'regGCVML2_PERFCOUNTER2_1_HI',
|
|
'regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX',
|
|
'regGCVML2_PERFCOUNTER2_1_LO',
|
|
'regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX',
|
|
'regGCVML2_PERFCOUNTER2_1_MODE',
|
|
'regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX',
|
|
'regGCVML2_PERFCOUNTER2_1_SELECT',
|
|
'regGCVML2_PERFCOUNTER2_1_SELECT1',
|
|
'regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX',
|
|
'regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX',
|
|
'regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ',
|
|
'regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX',
|
|
'regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT',
|
|
'regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX',
|
|
'regGCVML2_WALKER_MACRO_THROTTLE_TIME',
|
|
'regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX',
|
|
'regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT',
|
|
'regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX',
|
|
'regGCVML2_WALKER_MICRO_THROTTLE_TIME',
|
|
'regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX',
|
|
'regGCVM_CONTEXT0_CNTL', 'regGCVM_CONTEXT0_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT10_CNTL', 'regGCVM_CONTEXT10_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT11_CNTL', 'regGCVM_CONTEXT11_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT12_CNTL', 'regGCVM_CONTEXT12_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT13_CNTL', 'regGCVM_CONTEXT13_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT14_CNTL', 'regGCVM_CONTEXT14_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT15_CNTL', 'regGCVM_CONTEXT15_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT1_CNTL', 'regGCVM_CONTEXT1_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT2_CNTL', 'regGCVM_CONTEXT2_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT3_CNTL', 'regGCVM_CONTEXT3_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT4_CNTL', 'regGCVM_CONTEXT4_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT5_CNTL', 'regGCVM_CONTEXT5_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT6_CNTL', 'regGCVM_CONTEXT6_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT7_CNTL', 'regGCVM_CONTEXT7_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT8_CNTL', 'regGCVM_CONTEXT8_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT9_CNTL', 'regGCVM_CONTEXT9_CNTL_BASE_IDX',
|
|
'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32',
|
|
'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32',
|
|
'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32',
|
|
'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32',
|
|
'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32',
|
|
'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32',
|
|
'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_CONTEXTS_DISABLE', 'regGCVM_CONTEXTS_DISABLE_BASE_IDX',
|
|
'regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32',
|
|
'regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32',
|
|
'regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_DUMMY_PAGE_FAULT_CNTL',
|
|
'regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX',
|
|
'regGCVM_INVALIDATE_CNTL', 'regGCVM_INVALIDATE_CNTL_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG0_ACK',
|
|
'regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG0_REQ',
|
|
'regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG0_SEM',
|
|
'regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG10_ACK',
|
|
'regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG10_REQ',
|
|
'regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG10_SEM',
|
|
'regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG11_ACK',
|
|
'regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG11_REQ',
|
|
'regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG11_SEM',
|
|
'regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG12_ACK',
|
|
'regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG12_REQ',
|
|
'regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG12_SEM',
|
|
'regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG13_ACK',
|
|
'regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG13_REQ',
|
|
'regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG13_SEM',
|
|
'regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG14_ACK',
|
|
'regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG14_REQ',
|
|
'regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG14_SEM',
|
|
'regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG15_ACK',
|
|
'regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG15_REQ',
|
|
'regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG15_SEM',
|
|
'regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG16_ACK',
|
|
'regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG16_REQ',
|
|
'regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG16_SEM',
|
|
'regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG17_ACK',
|
|
'regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG17_REQ',
|
|
'regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG17_SEM',
|
|
'regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG1_ACK',
|
|
'regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG1_REQ',
|
|
'regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG1_SEM',
|
|
'regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG2_ACK',
|
|
'regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG2_REQ',
|
|
'regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG2_SEM',
|
|
'regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG3_ACK',
|
|
'regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG3_REQ',
|
|
'regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG3_SEM',
|
|
'regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG4_ACK',
|
|
'regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG4_REQ',
|
|
'regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG4_SEM',
|
|
'regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG5_ACK',
|
|
'regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG5_REQ',
|
|
'regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG5_SEM',
|
|
'regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG6_ACK',
|
|
'regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG6_REQ',
|
|
'regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG6_SEM',
|
|
'regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG7_ACK',
|
|
'regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG7_REQ',
|
|
'regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG7_SEM',
|
|
'regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG8_ACK',
|
|
'regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG8_REQ',
|
|
'regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG8_SEM',
|
|
'regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG9_ACK',
|
|
'regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32',
|
|
'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32',
|
|
'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG9_REQ',
|
|
'regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX',
|
|
'regGCVM_INVALIDATE_ENG9_SEM',
|
|
'regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX',
|
|
'regGCVM_L2_BANK_SELECT_MASKS',
|
|
'regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX',
|
|
'regGCVM_L2_BANK_SELECT_RESERVED_CID',
|
|
'regGCVM_L2_BANK_SELECT_RESERVED_CID2',
|
|
'regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX',
|
|
'regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX',
|
|
'regGCVM_L2_CACHE_PARITY_CNTL',
|
|
'regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX',
|
|
'regGCVM_L2_CGTT_BUSY_CTRL', 'regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX',
|
|
'regGCVM_L2_CNTL', 'regGCVM_L2_CNTL2',
|
|
'regGCVM_L2_CNTL2_BASE_IDX', 'regGCVM_L2_CNTL3',
|
|
'regGCVM_L2_CNTL3_BASE_IDX', 'regGCVM_L2_CNTL4',
|
|
'regGCVM_L2_CNTL4_BASE_IDX', 'regGCVM_L2_CNTL5',
|
|
'regGCVM_L2_CNTL5_BASE_IDX', 'regGCVM_L2_CNTL_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32',
|
|
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32',
|
|
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32',
|
|
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32',
|
|
'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32',
|
|
'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX',
|
|
'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32',
|
|
'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX',
|
|
'regGCVM_L2_GCR_CNTL', 'regGCVM_L2_GCR_CNTL_BASE_IDX',
|
|
'regGCVM_L2_ICG_CTRL', 'regGCVM_L2_ICG_CTRL_BASE_IDX',
|
|
'regGCVM_L2_MM_GROUP_RT_CLASSES',
|
|
'regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX',
|
|
'regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES',
|
|
'regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX',
|
|
'regGCVM_L2_PROTECTION_FAULT_ADDR_HI32',
|
|
'regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_L2_PROTECTION_FAULT_ADDR_LO32',
|
|
'regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_L2_PROTECTION_FAULT_CNTL',
|
|
'regGCVM_L2_PROTECTION_FAULT_CNTL2',
|
|
'regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX',
|
|
'regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX',
|
|
'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32',
|
|
'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX',
|
|
'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32',
|
|
'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX',
|
|
'regGCVM_L2_PROTECTION_FAULT_MM_CNTL3',
|
|
'regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX',
|
|
'regGCVM_L2_PROTECTION_FAULT_MM_CNTL4',
|
|
'regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX',
|
|
'regGCVM_L2_PROTECTION_FAULT_STATUS',
|
|
'regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX',
|
|
'regGCVM_L2_PTE_CACHE_DUMP_CNTL',
|
|
'regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX',
|
|
'regGCVM_L2_PTE_CACHE_DUMP_READ',
|
|
'regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX', 'regGCVM_L2_STATUS',
|
|
'regGCVM_L2_STATUS_BASE_IDX', 'regGC_CAC_AGGR_GFXCLK_CYCLE',
|
|
'regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regGC_CAC_AGGR_LOWER',
|
|
'regGC_CAC_AGGR_LOWER_BASE_IDX', 'regGC_CAC_AGGR_UPPER',
|
|
'regGC_CAC_AGGR_UPPER_BASE_IDX', 'regGC_CAC_CTRL_1',
|
|
'regGC_CAC_CTRL_1_BASE_IDX', 'regGC_CAC_CTRL_2',
|
|
'regGC_CAC_CTRL_2_BASE_IDX', 'regGC_CAC_IND_DATA',
|
|
'regGC_CAC_IND_DATA_BASE_IDX', 'regGC_CAC_IND_INDEX',
|
|
'regGC_CAC_IND_INDEX_BASE_IDX', 'regGC_CAC_WEIGHT_CHC_0',
|
|
'regGC_CAC_WEIGHT_CHC_0_BASE_IDX', 'regGC_CAC_WEIGHT_CHC_1',
|
|
'regGC_CAC_WEIGHT_CHC_1_BASE_IDX', 'regGC_CAC_WEIGHT_CP_0',
|
|
'regGC_CAC_WEIGHT_CP_0_BASE_IDX', 'regGC_CAC_WEIGHT_CP_1',
|
|
'regGC_CAC_WEIGHT_CP_1_BASE_IDX', 'regGC_CAC_WEIGHT_EA_0',
|
|
'regGC_CAC_WEIGHT_EA_0_BASE_IDX', 'regGC_CAC_WEIGHT_EA_1',
|
|
'regGC_CAC_WEIGHT_EA_1_BASE_IDX', 'regGC_CAC_WEIGHT_EA_2',
|
|
'regGC_CAC_WEIGHT_EA_2_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_0',
|
|
'regGC_CAC_WEIGHT_GDS_0_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_1',
|
|
'regGC_CAC_WEIGHT_GDS_1_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_2',
|
|
'regGC_CAC_WEIGHT_GDS_2_BASE_IDX', 'regGC_CAC_WEIGHT_GE_0',
|
|
'regGC_CAC_WEIGHT_GE_0_BASE_IDX', 'regGC_CAC_WEIGHT_GE_1',
|
|
'regGC_CAC_WEIGHT_GE_1_BASE_IDX', 'regGC_CAC_WEIGHT_GE_2',
|
|
'regGC_CAC_WEIGHT_GE_2_BASE_IDX', 'regGC_CAC_WEIGHT_GE_3',
|
|
'regGC_CAC_WEIGHT_GE_3_BASE_IDX', 'regGC_CAC_WEIGHT_GE_4',
|
|
'regGC_CAC_WEIGHT_GE_4_BASE_IDX', 'regGC_CAC_WEIGHT_GE_5',
|
|
'regGC_CAC_WEIGHT_GE_5_BASE_IDX', 'regGC_CAC_WEIGHT_GE_6',
|
|
'regGC_CAC_WEIGHT_GE_6_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_0',
|
|
'regGC_CAC_WEIGHT_GL2C_0_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_1',
|
|
'regGC_CAC_WEIGHT_GL2C_1_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_2',
|
|
'regGC_CAC_WEIGHT_GL2C_2_BASE_IDX', 'regGC_CAC_WEIGHT_GRBM_0',
|
|
'regGC_CAC_WEIGHT_GRBM_0_BASE_IDX', 'regGC_CAC_WEIGHT_GUS_0',
|
|
'regGC_CAC_WEIGHT_GUS_0_BASE_IDX', 'regGC_CAC_WEIGHT_GUS_1',
|
|
'regGC_CAC_WEIGHT_GUS_1_BASE_IDX', 'regGC_CAC_WEIGHT_PH_0',
|
|
'regGC_CAC_WEIGHT_PH_0_BASE_IDX', 'regGC_CAC_WEIGHT_PH_1',
|
|
'regGC_CAC_WEIGHT_PH_1_BASE_IDX', 'regGC_CAC_WEIGHT_PH_2',
|
|
'regGC_CAC_WEIGHT_PH_2_BASE_IDX', 'regGC_CAC_WEIGHT_PH_3',
|
|
'regGC_CAC_WEIGHT_PH_3_BASE_IDX', 'regGC_CAC_WEIGHT_PMM_0',
|
|
'regGC_CAC_WEIGHT_PMM_0_BASE_IDX', 'regGC_CAC_WEIGHT_RLC_0',
|
|
'regGC_CAC_WEIGHT_RLC_0_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_0',
|
|
'regGC_CAC_WEIGHT_SDMA_0_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_1',
|
|
'regGC_CAC_WEIGHT_SDMA_1_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_2',
|
|
'regGC_CAC_WEIGHT_SDMA_2_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_3',
|
|
'regGC_CAC_WEIGHT_SDMA_3_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_4',
|
|
'regGC_CAC_WEIGHT_SDMA_4_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_5',
|
|
'regGC_CAC_WEIGHT_SDMA_5_BASE_IDX',
|
|
'regGC_CAC_WEIGHT_UTCL2_ROUTER_0',
|
|
'regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX',
|
|
'regGC_CAC_WEIGHT_UTCL2_ROUTER_1',
|
|
'regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX',
|
|
'regGC_CAC_WEIGHT_UTCL2_ROUTER_2',
|
|
'regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX',
|
|
'regGC_CAC_WEIGHT_UTCL2_ROUTER_3',
|
|
'regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX',
|
|
'regGC_CAC_WEIGHT_UTCL2_ROUTER_4',
|
|
'regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX',
|
|
'regGC_CAC_WEIGHT_UTCL2_VML2_0',
|
|
'regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX',
|
|
'regGC_CAC_WEIGHT_UTCL2_VML2_1',
|
|
'regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX',
|
|
'regGC_CAC_WEIGHT_UTCL2_VML2_2',
|
|
'regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX',
|
|
'regGC_CAC_WEIGHT_UTCL2_WALKER_0',
|
|
'regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX',
|
|
'regGC_CAC_WEIGHT_UTCL2_WALKER_1',
|
|
'regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX',
|
|
'regGC_CAC_WEIGHT_UTCL2_WALKER_2',
|
|
'regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX',
|
|
'regGC_EDC_CLK_MONITOR_CTRL',
|
|
'regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX', 'regGC_EDC_CTRL',
|
|
'regGC_EDC_CTRL_BASE_IDX', 'regGC_EDC_OVERFLOW',
|
|
'regGC_EDC_OVERFLOW_BASE_IDX', 'regGC_EDC_ROLLING_POWER_DELTA',
|
|
'regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX', 'regGC_EDC_STATUS',
|
|
'regGC_EDC_STATUS_BASE_IDX', 'regGC_EDC_STRETCH_CTRL',
|
|
'regGC_EDC_STRETCH_CTRL_BASE_IDX', 'regGC_EDC_STRETCH_THRESHOLD',
|
|
'regGC_EDC_STRETCH_THRESHOLD_BASE_IDX', 'regGC_EDC_THRESHOLD',
|
|
'regGC_EDC_THRESHOLD_BASE_IDX', 'regGC_IH_COOKIE_0_PTR',
|
|
'regGC_IH_COOKIE_0_PTR_BASE_IDX', 'regGC_THROTTLE_CTRL',
|
|
'regGC_THROTTLE_CTRL1', 'regGC_THROTTLE_CTRL1_BASE_IDX',
|
|
'regGC_THROTTLE_CTRL_BASE_IDX', 'regGC_THROTTLE_STATUS',
|
|
'regGC_THROTTLE_STATUS_BASE_IDX', 'regGC_USER_PRIM_CONFIG',
|
|
'regGC_USER_PRIM_CONFIG_BASE_IDX',
|
|
'regGC_USER_RB_BACKEND_DISABLE',
|
|
'regGC_USER_RB_BACKEND_DISABLE_BASE_IDX',
|
|
'regGC_USER_RB_REDUNDANCY', 'regGC_USER_RB_REDUNDANCY_BASE_IDX',
|
|
'regGC_USER_RMI_REDUNDANCY', 'regGC_USER_RMI_REDUNDANCY_BASE_IDX',
|
|
'regGC_USER_SA_UNIT_DISABLE',
|
|
'regGC_USER_SA_UNIT_DISABLE_BASE_IDX',
|
|
'regGC_USER_SHADER_ARRAY_CONFIG',
|
|
'regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX',
|
|
'regGC_USER_SHADER_RATE_CONFIG',
|
|
'regGC_USER_SHADER_RATE_CONFIG_BASE_IDX', 'regGDS_ATOM_BASE',
|
|
'regGDS_ATOM_BASE_BASE_IDX', 'regGDS_ATOM_CNTL',
|
|
'regGDS_ATOM_CNTL_BASE_IDX', 'regGDS_ATOM_COMPLETE',
|
|
'regGDS_ATOM_COMPLETE_BASE_IDX', 'regGDS_ATOM_DST',
|
|
'regGDS_ATOM_DST_BASE_IDX', 'regGDS_ATOM_OFFSET0',
|
|
'regGDS_ATOM_OFFSET0_BASE_IDX', 'regGDS_ATOM_OFFSET1',
|
|
'regGDS_ATOM_OFFSET1_BASE_IDX', 'regGDS_ATOM_OP',
|
|
'regGDS_ATOM_OP_BASE_IDX', 'regGDS_ATOM_READ0',
|
|
'regGDS_ATOM_READ0_BASE_IDX', 'regGDS_ATOM_READ0_U',
|
|
'regGDS_ATOM_READ0_U_BASE_IDX', 'regGDS_ATOM_READ1',
|
|
'regGDS_ATOM_READ1_BASE_IDX', 'regGDS_ATOM_READ1_U',
|
|
'regGDS_ATOM_READ1_U_BASE_IDX', 'regGDS_ATOM_SIZE',
|
|
'regGDS_ATOM_SIZE_BASE_IDX', 'regGDS_ATOM_SRC0',
|
|
'regGDS_ATOM_SRC0_BASE_IDX', 'regGDS_ATOM_SRC0_U',
|
|
'regGDS_ATOM_SRC0_U_BASE_IDX', 'regGDS_ATOM_SRC1',
|
|
'regGDS_ATOM_SRC1_BASE_IDX', 'regGDS_ATOM_SRC1_U',
|
|
'regGDS_ATOM_SRC1_U_BASE_IDX', 'regGDS_CNTL_STATUS',
|
|
'regGDS_CNTL_STATUS_BASE_IDX', 'regGDS_COMPUTE_MAX_WAVE_ID',
|
|
'regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX', 'regGDS_CONFIG',
|
|
'regGDS_CONFIG_BASE_IDX', 'regGDS_CS_CTXSW_CNT0',
|
|
'regGDS_CS_CTXSW_CNT0_BASE_IDX', 'regGDS_CS_CTXSW_CNT1',
|
|
'regGDS_CS_CTXSW_CNT1_BASE_IDX', 'regGDS_CS_CTXSW_CNT2',
|
|
'regGDS_CS_CTXSW_CNT2_BASE_IDX', 'regGDS_CS_CTXSW_CNT3',
|
|
'regGDS_CS_CTXSW_CNT3_BASE_IDX', 'regGDS_CS_CTXSW_STATUS',
|
|
'regGDS_CS_CTXSW_STATUS_BASE_IDX', 'regGDS_DSM_CNTL',
|
|
'regGDS_DSM_CNTL2', 'regGDS_DSM_CNTL2_BASE_IDX',
|
|
'regGDS_DSM_CNTL_BASE_IDX', 'regGDS_EDC_CNT',
|
|
'regGDS_EDC_CNT_BASE_IDX', 'regGDS_EDC_GRBM_CNT',
|
|
'regGDS_EDC_GRBM_CNT_BASE_IDX', 'regGDS_EDC_OA_DED',
|
|
'regGDS_EDC_OA_DED_BASE_IDX', 'regGDS_EDC_OA_PHY_CNT',
|
|
'regGDS_EDC_OA_PHY_CNT_BASE_IDX', 'regGDS_EDC_OA_PIPE_CNT',
|
|
'regGDS_EDC_OA_PIPE_CNT_BASE_IDX', 'regGDS_ENHANCE',
|
|
'regGDS_ENHANCE2', 'regGDS_ENHANCE2_BASE_IDX',
|
|
'regGDS_ENHANCE_BASE_IDX', 'regGDS_GFX_CTXSW_STATUS',
|
|
'regGDS_GFX_CTXSW_STATUS_BASE_IDX', 'regGDS_GS_0',
|
|
'regGDS_GS_0_BASE_IDX', 'regGDS_GS_1', 'regGDS_GS_1_BASE_IDX',
|
|
'regGDS_GS_2', 'regGDS_GS_2_BASE_IDX', 'regGDS_GS_3',
|
|
'regGDS_GS_3_BASE_IDX', 'regGDS_GS_CTXSW_CNT0',
|
|
'regGDS_GS_CTXSW_CNT0_BASE_IDX', 'regGDS_GS_CTXSW_CNT1',
|
|
'regGDS_GS_CTXSW_CNT1_BASE_IDX', 'regGDS_GS_CTXSW_CNT2',
|
|
'regGDS_GS_CTXSW_CNT2_BASE_IDX', 'regGDS_GS_CTXSW_CNT3',
|
|
'regGDS_GS_CTXSW_CNT3_BASE_IDX', 'regGDS_GWS_RESET0',
|
|
'regGDS_GWS_RESET0_BASE_IDX', 'regGDS_GWS_RESET1',
|
|
'regGDS_GWS_RESET1_BASE_IDX', 'regGDS_GWS_RESOURCE',
|
|
'regGDS_GWS_RESOURCE_BASE_IDX', 'regGDS_GWS_RESOURCE_CNT',
|
|
'regGDS_GWS_RESOURCE_CNTL', 'regGDS_GWS_RESOURCE_CNTL_BASE_IDX',
|
|
'regGDS_GWS_RESOURCE_CNT_BASE_IDX', 'regGDS_GWS_RESOURCE_RESET',
|
|
'regGDS_GWS_RESOURCE_RESET_BASE_IDX', 'regGDS_GWS_VMID0',
|
|
'regGDS_GWS_VMID0_BASE_IDX', 'regGDS_GWS_VMID1',
|
|
'regGDS_GWS_VMID10', 'regGDS_GWS_VMID10_BASE_IDX',
|
|
'regGDS_GWS_VMID11', 'regGDS_GWS_VMID11_BASE_IDX',
|
|
'regGDS_GWS_VMID12', 'regGDS_GWS_VMID12_BASE_IDX',
|
|
'regGDS_GWS_VMID13', 'regGDS_GWS_VMID13_BASE_IDX',
|
|
'regGDS_GWS_VMID14', 'regGDS_GWS_VMID14_BASE_IDX',
|
|
'regGDS_GWS_VMID15', 'regGDS_GWS_VMID15_BASE_IDX',
|
|
'regGDS_GWS_VMID1_BASE_IDX', 'regGDS_GWS_VMID2',
|
|
'regGDS_GWS_VMID2_BASE_IDX', 'regGDS_GWS_VMID3',
|
|
'regGDS_GWS_VMID3_BASE_IDX', 'regGDS_GWS_VMID4',
|
|
'regGDS_GWS_VMID4_BASE_IDX', 'regGDS_GWS_VMID5',
|
|
'regGDS_GWS_VMID5_BASE_IDX', 'regGDS_GWS_VMID6',
|
|
'regGDS_GWS_VMID6_BASE_IDX', 'regGDS_GWS_VMID7',
|
|
'regGDS_GWS_VMID7_BASE_IDX', 'regGDS_GWS_VMID8',
|
|
'regGDS_GWS_VMID8_BASE_IDX', 'regGDS_GWS_VMID9',
|
|
'regGDS_GWS_VMID9_BASE_IDX', 'regGDS_MEMORY_CLEAN',
|
|
'regGDS_MEMORY_CLEAN_BASE_IDX', 'regGDS_OA_ADDRESS',
|
|
'regGDS_OA_ADDRESS_BASE_IDX', 'regGDS_OA_CGPG_RESTORE',
|
|
'regGDS_OA_CGPG_RESTORE_BASE_IDX', 'regGDS_OA_CNTL',
|
|
'regGDS_OA_CNTL_BASE_IDX', 'regGDS_OA_COUNTER',
|
|
'regGDS_OA_COUNTER_BASE_IDX', 'regGDS_OA_INCDEC',
|
|
'regGDS_OA_INCDEC_BASE_IDX', 'regGDS_OA_RESET',
|
|
'regGDS_OA_RESET_BASE_IDX', 'regGDS_OA_RESET_MASK',
|
|
'regGDS_OA_RESET_MASK_BASE_IDX', 'regGDS_OA_RING_SIZE',
|
|
'regGDS_OA_RING_SIZE_BASE_IDX', 'regGDS_OA_VMID0',
|
|
'regGDS_OA_VMID0_BASE_IDX', 'regGDS_OA_VMID1', 'regGDS_OA_VMID10',
|
|
'regGDS_OA_VMID10_BASE_IDX', 'regGDS_OA_VMID11',
|
|
'regGDS_OA_VMID11_BASE_IDX', 'regGDS_OA_VMID12',
|
|
'regGDS_OA_VMID12_BASE_IDX', 'regGDS_OA_VMID13',
|
|
'regGDS_OA_VMID13_BASE_IDX', 'regGDS_OA_VMID14',
|
|
'regGDS_OA_VMID14_BASE_IDX', 'regGDS_OA_VMID15',
|
|
'regGDS_OA_VMID15_BASE_IDX', 'regGDS_OA_VMID1_BASE_IDX',
|
|
'regGDS_OA_VMID2', 'regGDS_OA_VMID2_BASE_IDX', 'regGDS_OA_VMID3',
|
|
'regGDS_OA_VMID3_BASE_IDX', 'regGDS_OA_VMID4',
|
|
'regGDS_OA_VMID4_BASE_IDX', 'regGDS_OA_VMID5',
|
|
'regGDS_OA_VMID5_BASE_IDX', 'regGDS_OA_VMID6',
|
|
'regGDS_OA_VMID6_BASE_IDX', 'regGDS_OA_VMID7',
|
|
'regGDS_OA_VMID7_BASE_IDX', 'regGDS_OA_VMID8',
|
|
'regGDS_OA_VMID8_BASE_IDX', 'regGDS_OA_VMID9',
|
|
'regGDS_OA_VMID9_BASE_IDX', 'regGDS_PERFCOUNTER0_HI',
|
|
'regGDS_PERFCOUNTER0_HI_BASE_IDX', 'regGDS_PERFCOUNTER0_LO',
|
|
'regGDS_PERFCOUNTER0_LO_BASE_IDX', 'regGDS_PERFCOUNTER0_SELECT',
|
|
'regGDS_PERFCOUNTER0_SELECT1',
|
|
'regGDS_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regGDS_PERFCOUNTER0_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER1_HI',
|
|
'regGDS_PERFCOUNTER1_HI_BASE_IDX', 'regGDS_PERFCOUNTER1_LO',
|
|
'regGDS_PERFCOUNTER1_LO_BASE_IDX', 'regGDS_PERFCOUNTER1_SELECT',
|
|
'regGDS_PERFCOUNTER1_SELECT1',
|
|
'regGDS_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regGDS_PERFCOUNTER1_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER2_HI',
|
|
'regGDS_PERFCOUNTER2_HI_BASE_IDX', 'regGDS_PERFCOUNTER2_LO',
|
|
'regGDS_PERFCOUNTER2_LO_BASE_IDX', 'regGDS_PERFCOUNTER2_SELECT',
|
|
'regGDS_PERFCOUNTER2_SELECT1',
|
|
'regGDS_PERFCOUNTER2_SELECT1_BASE_IDX',
|
|
'regGDS_PERFCOUNTER2_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER3_HI',
|
|
'regGDS_PERFCOUNTER3_HI_BASE_IDX', 'regGDS_PERFCOUNTER3_LO',
|
|
'regGDS_PERFCOUNTER3_LO_BASE_IDX', 'regGDS_PERFCOUNTER3_SELECT',
|
|
'regGDS_PERFCOUNTER3_SELECT1',
|
|
'regGDS_PERFCOUNTER3_SELECT1_BASE_IDX',
|
|
'regGDS_PERFCOUNTER3_SELECT_BASE_IDX', 'regGDS_PROTECTION_FAULT',
|
|
'regGDS_PROTECTION_FAULT_BASE_IDX', 'regGDS_PS_CTXSW_CNT0',
|
|
'regGDS_PS_CTXSW_CNT0_BASE_IDX', 'regGDS_PS_CTXSW_CNT1',
|
|
'regGDS_PS_CTXSW_CNT1_BASE_IDX', 'regGDS_PS_CTXSW_CNT2',
|
|
'regGDS_PS_CTXSW_CNT2_BASE_IDX', 'regGDS_PS_CTXSW_CNT3',
|
|
'regGDS_PS_CTXSW_CNT3_BASE_IDX', 'regGDS_PS_CTXSW_IDX',
|
|
'regGDS_PS_CTXSW_IDX_BASE_IDX', 'regGDS_RD_ADDR',
|
|
'regGDS_RD_ADDR_BASE_IDX', 'regGDS_RD_BURST_ADDR',
|
|
'regGDS_RD_BURST_ADDR_BASE_IDX', 'regGDS_RD_BURST_COUNT',
|
|
'regGDS_RD_BURST_COUNT_BASE_IDX', 'regGDS_RD_BURST_DATA',
|
|
'regGDS_RD_BURST_DATA_BASE_IDX', 'regGDS_RD_DATA',
|
|
'regGDS_RD_DATA_BASE_IDX', 'regGDS_STRMOUT_DWORDS_WRITTEN_0',
|
|
'regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX',
|
|
'regGDS_STRMOUT_DWORDS_WRITTEN_1',
|
|
'regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX',
|
|
'regGDS_STRMOUT_DWORDS_WRITTEN_2',
|
|
'regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX',
|
|
'regGDS_STRMOUT_DWORDS_WRITTEN_3',
|
|
'regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_0_HI',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_0_LO',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_1_HI',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_1_LO',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_2_HI',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_2_LO',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_3_HI',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_3_LO',
|
|
'regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_0_HI',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_0_LO',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_1_HI',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_1_LO',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_2_HI',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_2_LO',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_3_HI',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_3_LO',
|
|
'regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX', 'regGDS_VMID0_BASE',
|
|
'regGDS_VMID0_BASE_BASE_IDX', 'regGDS_VMID0_SIZE',
|
|
'regGDS_VMID0_SIZE_BASE_IDX', 'regGDS_VMID10_BASE',
|
|
'regGDS_VMID10_BASE_BASE_IDX', 'regGDS_VMID10_SIZE',
|
|
'regGDS_VMID10_SIZE_BASE_IDX', 'regGDS_VMID11_BASE',
|
|
'regGDS_VMID11_BASE_BASE_IDX', 'regGDS_VMID11_SIZE',
|
|
'regGDS_VMID11_SIZE_BASE_IDX', 'regGDS_VMID12_BASE',
|
|
'regGDS_VMID12_BASE_BASE_IDX', 'regGDS_VMID12_SIZE',
|
|
'regGDS_VMID12_SIZE_BASE_IDX', 'regGDS_VMID13_BASE',
|
|
'regGDS_VMID13_BASE_BASE_IDX', 'regGDS_VMID13_SIZE',
|
|
'regGDS_VMID13_SIZE_BASE_IDX', 'regGDS_VMID14_BASE',
|
|
'regGDS_VMID14_BASE_BASE_IDX', 'regGDS_VMID14_SIZE',
|
|
'regGDS_VMID14_SIZE_BASE_IDX', 'regGDS_VMID15_BASE',
|
|
'regGDS_VMID15_BASE_BASE_IDX', 'regGDS_VMID15_SIZE',
|
|
'regGDS_VMID15_SIZE_BASE_IDX', 'regGDS_VMID1_BASE',
|
|
'regGDS_VMID1_BASE_BASE_IDX', 'regGDS_VMID1_SIZE',
|
|
'regGDS_VMID1_SIZE_BASE_IDX', 'regGDS_VMID2_BASE',
|
|
'regGDS_VMID2_BASE_BASE_IDX', 'regGDS_VMID2_SIZE',
|
|
'regGDS_VMID2_SIZE_BASE_IDX', 'regGDS_VMID3_BASE',
|
|
'regGDS_VMID3_BASE_BASE_IDX', 'regGDS_VMID3_SIZE',
|
|
'regGDS_VMID3_SIZE_BASE_IDX', 'regGDS_VMID4_BASE',
|
|
'regGDS_VMID4_BASE_BASE_IDX', 'regGDS_VMID4_SIZE',
|
|
'regGDS_VMID4_SIZE_BASE_IDX', 'regGDS_VMID5_BASE',
|
|
'regGDS_VMID5_BASE_BASE_IDX', 'regGDS_VMID5_SIZE',
|
|
'regGDS_VMID5_SIZE_BASE_IDX', 'regGDS_VMID6_BASE',
|
|
'regGDS_VMID6_BASE_BASE_IDX', 'regGDS_VMID6_SIZE',
|
|
'regGDS_VMID6_SIZE_BASE_IDX', 'regGDS_VMID7_BASE',
|
|
'regGDS_VMID7_BASE_BASE_IDX', 'regGDS_VMID7_SIZE',
|
|
'regGDS_VMID7_SIZE_BASE_IDX', 'regGDS_VMID8_BASE',
|
|
'regGDS_VMID8_BASE_BASE_IDX', 'regGDS_VMID8_SIZE',
|
|
'regGDS_VMID8_SIZE_BASE_IDX', 'regGDS_VMID9_BASE',
|
|
'regGDS_VMID9_BASE_BASE_IDX', 'regGDS_VMID9_SIZE',
|
|
'regGDS_VMID9_SIZE_BASE_IDX', 'regGDS_VM_PROTECTION_FAULT',
|
|
'regGDS_VM_PROTECTION_FAULT_BASE_IDX', 'regGDS_WRITE_COMPLETE',
|
|
'regGDS_WRITE_COMPLETE_BASE_IDX', 'regGDS_WR_ADDR',
|
|
'regGDS_WR_ADDR_BASE_IDX', 'regGDS_WR_BURST_ADDR',
|
|
'regGDS_WR_BURST_ADDR_BASE_IDX', 'regGDS_WR_BURST_DATA',
|
|
'regGDS_WR_BURST_DATA_BASE_IDX', 'regGDS_WR_DATA',
|
|
'regGDS_WR_DATA_BASE_IDX', 'regGE1_PERFCOUNTER0_HI',
|
|
'regGE1_PERFCOUNTER0_HI_BASE_IDX', 'regGE1_PERFCOUNTER0_LO',
|
|
'regGE1_PERFCOUNTER0_LO_BASE_IDX', 'regGE1_PERFCOUNTER0_SELECT',
|
|
'regGE1_PERFCOUNTER0_SELECT1',
|
|
'regGE1_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regGE1_PERFCOUNTER0_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER1_HI',
|
|
'regGE1_PERFCOUNTER1_HI_BASE_IDX', 'regGE1_PERFCOUNTER1_LO',
|
|
'regGE1_PERFCOUNTER1_LO_BASE_IDX', 'regGE1_PERFCOUNTER1_SELECT',
|
|
'regGE1_PERFCOUNTER1_SELECT1',
|
|
'regGE1_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regGE1_PERFCOUNTER1_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER2_HI',
|
|
'regGE1_PERFCOUNTER2_HI_BASE_IDX', 'regGE1_PERFCOUNTER2_LO',
|
|
'regGE1_PERFCOUNTER2_LO_BASE_IDX', 'regGE1_PERFCOUNTER2_SELECT',
|
|
'regGE1_PERFCOUNTER2_SELECT1',
|
|
'regGE1_PERFCOUNTER2_SELECT1_BASE_IDX',
|
|
'regGE1_PERFCOUNTER2_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER3_HI',
|
|
'regGE1_PERFCOUNTER3_HI_BASE_IDX', 'regGE1_PERFCOUNTER3_LO',
|
|
'regGE1_PERFCOUNTER3_LO_BASE_IDX', 'regGE1_PERFCOUNTER3_SELECT',
|
|
'regGE1_PERFCOUNTER3_SELECT1',
|
|
'regGE1_PERFCOUNTER3_SELECT1_BASE_IDX',
|
|
'regGE1_PERFCOUNTER3_SELECT_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER0_HI',
|
|
'regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER0_LO',
|
|
'regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER0_SELECT',
|
|
'regGE2_DIST_PERFCOUNTER0_SELECT1',
|
|
'regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER1_HI',
|
|
'regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER1_LO',
|
|
'regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER1_SELECT',
|
|
'regGE2_DIST_PERFCOUNTER1_SELECT1',
|
|
'regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER2_HI',
|
|
'regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER2_LO',
|
|
'regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER2_SELECT',
|
|
'regGE2_DIST_PERFCOUNTER2_SELECT1',
|
|
'regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER3_HI',
|
|
'regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER3_LO',
|
|
'regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER3_SELECT',
|
|
'regGE2_DIST_PERFCOUNTER3_SELECT1',
|
|
'regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX',
|
|
'regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX',
|
|
'regGE2_SE_CNTL_STATUS', 'regGE2_SE_CNTL_STATUS_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER0_HI', 'regGE2_SE_PERFCOUNTER0_HI_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER0_LO', 'regGE2_SE_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER0_SELECT', 'regGE2_SE_PERFCOUNTER0_SELECT1',
|
|
'regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER1_HI', 'regGE2_SE_PERFCOUNTER1_HI_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER1_LO', 'regGE2_SE_PERFCOUNTER1_LO_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER1_SELECT', 'regGE2_SE_PERFCOUNTER1_SELECT1',
|
|
'regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER2_HI', 'regGE2_SE_PERFCOUNTER2_HI_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER2_LO', 'regGE2_SE_PERFCOUNTER2_LO_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER2_SELECT', 'regGE2_SE_PERFCOUNTER2_SELECT1',
|
|
'regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER3_HI', 'regGE2_SE_PERFCOUNTER3_HI_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER3_LO', 'regGE2_SE_PERFCOUNTER3_LO_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER3_SELECT', 'regGE2_SE_PERFCOUNTER3_SELECT1',
|
|
'regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX',
|
|
'regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX', 'regGE_CNTL',
|
|
'regGE_CNTL_BASE_IDX', 'regGE_GS_FAST_LAUNCH_WG_DIM',
|
|
'regGE_GS_FAST_LAUNCH_WG_DIM_1',
|
|
'regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX',
|
|
'regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX', 'regGE_INDX_OFFSET',
|
|
'regGE_INDX_OFFSET_BASE_IDX', 'regGE_MAX_OUTPUT_PER_SUBGROUP',
|
|
'regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX', 'regGE_MAX_VTX_INDX',
|
|
'regGE_MAX_VTX_INDX_BASE_IDX', 'regGE_MIN_VTX_INDX',
|
|
'regGE_MIN_VTX_INDX_BASE_IDX', 'regGE_MULTI_PRIM_IB_RESET_EN',
|
|
'regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX', 'regGE_NGG_SUBGRP_CNTL',
|
|
'regGE_NGG_SUBGRP_CNTL_BASE_IDX', 'regGE_PA_IF_SAFE_REG',
|
|
'regGE_PA_IF_SAFE_REG_BASE_IDX', 'regGE_PC_ALLOC',
|
|
'regGE_PC_ALLOC_BASE_IDX', 'regGE_PRIV_CONTROL',
|
|
'regGE_PRIV_CONTROL_BASE_IDX', 'regGE_RATE_CNTL_1',
|
|
'regGE_RATE_CNTL_1_BASE_IDX', 'regGE_RATE_CNTL_2',
|
|
'regGE_RATE_CNTL_2_BASE_IDX', 'regGE_SPI_IF_SAFE_REG',
|
|
'regGE_SPI_IF_SAFE_REG_BASE_IDX', 'regGE_STATUS',
|
|
'regGE_STATUS_BASE_IDX', 'regGE_STEREO_CNTL',
|
|
'regGE_STEREO_CNTL_BASE_IDX', 'regGE_USER_VGPR1',
|
|
'regGE_USER_VGPR1_BASE_IDX', 'regGE_USER_VGPR2',
|
|
'regGE_USER_VGPR2_BASE_IDX', 'regGE_USER_VGPR3',
|
|
'regGE_USER_VGPR3_BASE_IDX', 'regGE_USER_VGPR_EN',
|
|
'regGE_USER_VGPR_EN_BASE_IDX', 'regGFX_COPY_STATE',
|
|
'regGFX_COPY_STATE_BASE_IDX', 'regGFX_ICG_GL2C_CTRL',
|
|
'regGFX_ICG_GL2C_CTRL1', 'regGFX_ICG_GL2C_CTRL1_BASE_IDX',
|
|
'regGFX_ICG_GL2C_CTRL_BASE_IDX', 'regGFX_IMU_AEB_OVERRIDE',
|
|
'regGFX_IMU_AEB_OVERRIDE_BASE_IDX', 'regGFX_IMU_C2PMSG_0',
|
|
'regGFX_IMU_C2PMSG_0_BASE_IDX', 'regGFX_IMU_C2PMSG_1',
|
|
'regGFX_IMU_C2PMSG_10', 'regGFX_IMU_C2PMSG_10_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_11', 'regGFX_IMU_C2PMSG_11_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_12', 'regGFX_IMU_C2PMSG_12_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_13', 'regGFX_IMU_C2PMSG_13_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_14', 'regGFX_IMU_C2PMSG_14_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_15', 'regGFX_IMU_C2PMSG_15_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_16', 'regGFX_IMU_C2PMSG_16_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_17', 'regGFX_IMU_C2PMSG_17_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_18', 'regGFX_IMU_C2PMSG_18_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_19', 'regGFX_IMU_C2PMSG_19_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_1_BASE_IDX', 'regGFX_IMU_C2PMSG_2',
|
|
'regGFX_IMU_C2PMSG_20', 'regGFX_IMU_C2PMSG_20_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_21', 'regGFX_IMU_C2PMSG_21_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_22', 'regGFX_IMU_C2PMSG_22_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_23', 'regGFX_IMU_C2PMSG_23_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_24', 'regGFX_IMU_C2PMSG_24_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_25', 'regGFX_IMU_C2PMSG_25_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_26', 'regGFX_IMU_C2PMSG_26_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_27', 'regGFX_IMU_C2PMSG_27_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_28', 'regGFX_IMU_C2PMSG_28_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_29', 'regGFX_IMU_C2PMSG_29_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_2_BASE_IDX', 'regGFX_IMU_C2PMSG_3',
|
|
'regGFX_IMU_C2PMSG_30', 'regGFX_IMU_C2PMSG_30_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_31', 'regGFX_IMU_C2PMSG_31_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_32', 'regGFX_IMU_C2PMSG_32_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_33', 'regGFX_IMU_C2PMSG_33_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_34', 'regGFX_IMU_C2PMSG_34_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_35', 'regGFX_IMU_C2PMSG_35_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_36', 'regGFX_IMU_C2PMSG_36_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_37', 'regGFX_IMU_C2PMSG_37_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_38', 'regGFX_IMU_C2PMSG_38_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_39', 'regGFX_IMU_C2PMSG_39_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_3_BASE_IDX', 'regGFX_IMU_C2PMSG_4',
|
|
'regGFX_IMU_C2PMSG_40', 'regGFX_IMU_C2PMSG_40_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_41', 'regGFX_IMU_C2PMSG_41_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_42', 'regGFX_IMU_C2PMSG_42_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_43', 'regGFX_IMU_C2PMSG_43_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_44', 'regGFX_IMU_C2PMSG_44_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_45', 'regGFX_IMU_C2PMSG_45_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_46', 'regGFX_IMU_C2PMSG_46_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_47', 'regGFX_IMU_C2PMSG_47_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_4_BASE_IDX', 'regGFX_IMU_C2PMSG_5',
|
|
'regGFX_IMU_C2PMSG_5_BASE_IDX', 'regGFX_IMU_C2PMSG_6',
|
|
'regGFX_IMU_C2PMSG_6_BASE_IDX', 'regGFX_IMU_C2PMSG_7',
|
|
'regGFX_IMU_C2PMSG_7_BASE_IDX', 'regGFX_IMU_C2PMSG_8',
|
|
'regGFX_IMU_C2PMSG_8_BASE_IDX', 'regGFX_IMU_C2PMSG_9',
|
|
'regGFX_IMU_C2PMSG_9_BASE_IDX', 'regGFX_IMU_C2PMSG_ACCESS_CTRL0',
|
|
'regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX',
|
|
'regGFX_IMU_C2PMSG_ACCESS_CTRL1',
|
|
'regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX', 'regGFX_IMU_CLK_CTRL',
|
|
'regGFX_IMU_CLK_CTRL_BASE_IDX', 'regGFX_IMU_CORE_CTRL',
|
|
'regGFX_IMU_CORE_CTRL_BASE_IDX', 'regGFX_IMU_CORE_INT_STATUS',
|
|
'regGFX_IMU_CORE_INT_STATUS_BASE_IDX', 'regGFX_IMU_CORE_STATUS',
|
|
'regGFX_IMU_CORE_STATUS_BASE_IDX', 'regGFX_IMU_DOORBELL_CONTROL',
|
|
'regGFX_IMU_DOORBELL_CONTROL_BASE_IDX', 'regGFX_IMU_DPM_ACC',
|
|
'regGFX_IMU_DPM_ACC_BASE_IDX', 'regGFX_IMU_DPM_CONTROL',
|
|
'regGFX_IMU_DPM_CONTROL_BASE_IDX', 'regGFX_IMU_DPM_REF_COUNTER',
|
|
'regGFX_IMU_DPM_REF_COUNTER_BASE_IDX', 'regGFX_IMU_D_RAM_ADDR',
|
|
'regGFX_IMU_D_RAM_ADDR_BASE_IDX', 'regGFX_IMU_D_RAM_DATA',
|
|
'regGFX_IMU_D_RAM_DATA_BASE_IDX', 'regGFX_IMU_FENCE_CTRL',
|
|
'regGFX_IMU_FENCE_CTRL_BASE_IDX', 'regGFX_IMU_FENCE_LOG_ADDR',
|
|
'regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX', 'regGFX_IMU_FENCE_LOG_INIT',
|
|
'regGFX_IMU_FENCE_LOG_INIT_BASE_IDX', 'regGFX_IMU_FUSESTRAP',
|
|
'regGFX_IMU_FUSE_CTRL', 'regGFX_IMU_FUSE_CTRL_BASE_IDX',
|
|
'regGFX_IMU_FW_GTS_HI', 'regGFX_IMU_FW_GTS_HI_BASE_IDX',
|
|
'regGFX_IMU_FW_GTS_LO', 'regGFX_IMU_FW_GTS_LO_BASE_IDX',
|
|
'regGFX_IMU_GAP_PWROK', 'regGFX_IMU_GAP_PWROK_BASE_IDX',
|
|
'regGFX_IMU_GFXCLK_BYPASS_CTRL',
|
|
'regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX',
|
|
'regGFX_IMU_GFX_IH_GASKET_CTRL',
|
|
'regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX',
|
|
'regGFX_IMU_GFX_ISO_CTRL', 'regGFX_IMU_GFX_ISO_CTRL_BASE_IDX',
|
|
'regGFX_IMU_GFX_RESET_CTRL', 'regGFX_IMU_GFX_RESET_CTRL_BASE_IDX',
|
|
'regGFX_IMU_GTS_OFFSET_HI', 'regGFX_IMU_GTS_OFFSET_HI_BASE_IDX',
|
|
'regGFX_IMU_GTS_OFFSET_LO', 'regGFX_IMU_GTS_OFFSET_LO_BASE_IDX',
|
|
'regGFX_IMU_IH_CTRL_1', 'regGFX_IMU_IH_CTRL_1_BASE_IDX',
|
|
'regGFX_IMU_IH_CTRL_2', 'regGFX_IMU_IH_CTRL_2_BASE_IDX',
|
|
'regGFX_IMU_IH_CTRL_3', 'regGFX_IMU_IH_CTRL_3_BASE_IDX',
|
|
'regGFX_IMU_IH_STATUS', 'regGFX_IMU_IH_STATUS_BASE_IDX',
|
|
'regGFX_IMU_I_RAM_ADDR', 'regGFX_IMU_I_RAM_ADDR_BASE_IDX',
|
|
'regGFX_IMU_I_RAM_DATA', 'regGFX_IMU_I_RAM_DATA_BASE_IDX',
|
|
'regGFX_IMU_MP1_MUTEX', 'regGFX_IMU_MP1_MUTEX_BASE_IDX',
|
|
'regGFX_IMU_MSG_FLAGS', 'regGFX_IMU_MSG_FLAGS_BASE_IDX',
|
|
'regGFX_IMU_PIC_INTR', 'regGFX_IMU_PIC_INTR_BASE_IDX',
|
|
'regGFX_IMU_PIC_INTR_ID', 'regGFX_IMU_PIC_INTR_ID_BASE_IDX',
|
|
'regGFX_IMU_PIC_INT_EDGE', 'regGFX_IMU_PIC_INT_EDGE_BASE_IDX',
|
|
'regGFX_IMU_PIC_INT_LVL', 'regGFX_IMU_PIC_INT_LVL_BASE_IDX',
|
|
'regGFX_IMU_PIC_INT_MASK', 'regGFX_IMU_PIC_INT_MASK_BASE_IDX',
|
|
'regGFX_IMU_PIC_INT_PRI_0', 'regGFX_IMU_PIC_INT_PRI_0_BASE_IDX',
|
|
'regGFX_IMU_PIC_INT_PRI_1', 'regGFX_IMU_PIC_INT_PRI_1_BASE_IDX',
|
|
'regGFX_IMU_PIC_INT_PRI_2', 'regGFX_IMU_PIC_INT_PRI_2_BASE_IDX',
|
|
'regGFX_IMU_PIC_INT_PRI_3', 'regGFX_IMU_PIC_INT_PRI_3_BASE_IDX',
|
|
'regGFX_IMU_PIC_INT_PRI_4', 'regGFX_IMU_PIC_INT_PRI_4_BASE_IDX',
|
|
'regGFX_IMU_PIC_INT_PRI_5', 'regGFX_IMU_PIC_INT_PRI_5_BASE_IDX',
|
|
'regGFX_IMU_PIC_INT_PRI_6', 'regGFX_IMU_PIC_INT_PRI_6_BASE_IDX',
|
|
'regGFX_IMU_PIC_INT_PRI_7', 'regGFX_IMU_PIC_INT_PRI_7_BASE_IDX',
|
|
'regGFX_IMU_PIC_INT_STATUS', 'regGFX_IMU_PIC_INT_STATUS_BASE_IDX',
|
|
'regGFX_IMU_PROGRAM_CTR', 'regGFX_IMU_PROGRAM_CTR_BASE_IDX',
|
|
'regGFX_IMU_PWRMGT_IRQ_CTRL',
|
|
'regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX', 'regGFX_IMU_PWROK',
|
|
'regGFX_IMU_PWROKRAW', 'regGFX_IMU_PWROKRAW_BASE_IDX',
|
|
'regGFX_IMU_PWROK_BASE_IDX', 'regGFX_IMU_RESETn',
|
|
'regGFX_IMU_RESETn_BASE_IDX', 'regGFX_IMU_RLC_BOOTLOADER_ADDR_HI',
|
|
'regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX',
|
|
'regGFX_IMU_RLC_BOOTLOADER_ADDR_LO',
|
|
'regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX',
|
|
'regGFX_IMU_RLC_BOOTLOADER_SIZE',
|
|
'regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX',
|
|
'regGFX_IMU_RLC_CG_CTRL', 'regGFX_IMU_RLC_CG_CTRL_BASE_IDX',
|
|
'regGFX_IMU_RLC_CMD', 'regGFX_IMU_RLC_CMD_BASE_IDX',
|
|
'regGFX_IMU_RLC_DATA_0', 'regGFX_IMU_RLC_DATA_0_BASE_IDX',
|
|
'regGFX_IMU_RLC_DATA_1', 'regGFX_IMU_RLC_DATA_1_BASE_IDX',
|
|
'regGFX_IMU_RLC_DATA_2', 'regGFX_IMU_RLC_DATA_2_BASE_IDX',
|
|
'regGFX_IMU_RLC_DATA_3', 'regGFX_IMU_RLC_DATA_3_BASE_IDX',
|
|
'regGFX_IMU_RLC_DATA_4', 'regGFX_IMU_RLC_DATA_4_BASE_IDX',
|
|
'regGFX_IMU_RLC_GTS_OFFSET_HI',
|
|
'regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX',
|
|
'regGFX_IMU_RLC_GTS_OFFSET_LO',
|
|
'regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX',
|
|
'regGFX_IMU_RLC_MSG_STATUS', 'regGFX_IMU_RLC_MSG_STATUS_BASE_IDX',
|
|
'regGFX_IMU_RLC_MUTEX', 'regGFX_IMU_RLC_MUTEX_BASE_IDX',
|
|
'regGFX_IMU_RLC_OVERRIDE', 'regGFX_IMU_RLC_OVERRIDE_BASE_IDX',
|
|
'regGFX_IMU_RLC_RAM_ADDR_HIGH',
|
|
'regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX',
|
|
'regGFX_IMU_RLC_RAM_ADDR_LOW',
|
|
'regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX', 'regGFX_IMU_RLC_RAM_DATA',
|
|
'regGFX_IMU_RLC_RAM_DATA_BASE_IDX', 'regGFX_IMU_RLC_RAM_INDEX',
|
|
'regGFX_IMU_RLC_RAM_INDEX_BASE_IDX',
|
|
'regGFX_IMU_RLC_RESET_VECTOR',
|
|
'regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX', 'regGFX_IMU_RLC_STATUS',
|
|
'regGFX_IMU_RLC_STATUS_BASE_IDX', 'regGFX_IMU_RLC_THROTTLE_GFX',
|
|
'regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX', 'regGFX_IMU_SCRATCH_0',
|
|
'regGFX_IMU_SCRATCH_0_BASE_IDX', 'regGFX_IMU_SCRATCH_1',
|
|
'regGFX_IMU_SCRATCH_10', 'regGFX_IMU_SCRATCH_10_BASE_IDX',
|
|
'regGFX_IMU_SCRATCH_11', 'regGFX_IMU_SCRATCH_11_BASE_IDX',
|
|
'regGFX_IMU_SCRATCH_12', 'regGFX_IMU_SCRATCH_12_BASE_IDX',
|
|
'regGFX_IMU_SCRATCH_13', 'regGFX_IMU_SCRATCH_13_BASE_IDX',
|
|
'regGFX_IMU_SCRATCH_14', 'regGFX_IMU_SCRATCH_14_BASE_IDX',
|
|
'regGFX_IMU_SCRATCH_15', 'regGFX_IMU_SCRATCH_15_BASE_IDX',
|
|
'regGFX_IMU_SCRATCH_1_BASE_IDX', 'regGFX_IMU_SCRATCH_2',
|
|
'regGFX_IMU_SCRATCH_2_BASE_IDX', 'regGFX_IMU_SCRATCH_3',
|
|
'regGFX_IMU_SCRATCH_3_BASE_IDX', 'regGFX_IMU_SCRATCH_4',
|
|
'regGFX_IMU_SCRATCH_4_BASE_IDX', 'regGFX_IMU_SCRATCH_5',
|
|
'regGFX_IMU_SCRATCH_5_BASE_IDX', 'regGFX_IMU_SCRATCH_6',
|
|
'regGFX_IMU_SCRATCH_6_BASE_IDX', 'regGFX_IMU_SCRATCH_7',
|
|
'regGFX_IMU_SCRATCH_7_BASE_IDX', 'regGFX_IMU_SCRATCH_8',
|
|
'regGFX_IMU_SCRATCH_8_BASE_IDX', 'regGFX_IMU_SCRATCH_9',
|
|
'regGFX_IMU_SCRATCH_9_BASE_IDX', 'regGFX_IMU_SMUIO_VIDCHG_CTRL',
|
|
'regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX', 'regGFX_IMU_SOC_ADDR',
|
|
'regGFX_IMU_SOC_ADDR_BASE_IDX', 'regGFX_IMU_SOC_DATA',
|
|
'regGFX_IMU_SOC_DATA_BASE_IDX', 'regGFX_IMU_SOC_REQ',
|
|
'regGFX_IMU_SOC_REQ_BASE_IDX', 'regGFX_IMU_STATUS',
|
|
'regGFX_IMU_STATUS_BASE_IDX', 'regGFX_IMU_TELEMETRY',
|
|
'regGFX_IMU_TELEMETRY_BASE_IDX', 'regGFX_IMU_TELEMETRY_DATA',
|
|
'regGFX_IMU_TELEMETRY_DATA_BASE_IDX',
|
|
'regGFX_IMU_TELEMETRY_TEMPERATURE',
|
|
'regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX',
|
|
'regGFX_IMU_TIMER0_CMP0', 'regGFX_IMU_TIMER0_CMP0_BASE_IDX',
|
|
'regGFX_IMU_TIMER0_CMP1', 'regGFX_IMU_TIMER0_CMP1_BASE_IDX',
|
|
'regGFX_IMU_TIMER0_CMP3', 'regGFX_IMU_TIMER0_CMP3_BASE_IDX',
|
|
'regGFX_IMU_TIMER0_CMP_AUTOINC',
|
|
'regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX',
|
|
'regGFX_IMU_TIMER0_CMP_INTEN',
|
|
'regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER0_CTRL0',
|
|
'regGFX_IMU_TIMER0_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER0_CTRL1',
|
|
'regGFX_IMU_TIMER0_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER0_VALUE',
|
|
'regGFX_IMU_TIMER0_VALUE_BASE_IDX', 'regGFX_IMU_TIMER1_CMP0',
|
|
'regGFX_IMU_TIMER1_CMP0_BASE_IDX', 'regGFX_IMU_TIMER1_CMP1',
|
|
'regGFX_IMU_TIMER1_CMP1_BASE_IDX', 'regGFX_IMU_TIMER1_CMP3',
|
|
'regGFX_IMU_TIMER1_CMP3_BASE_IDX',
|
|
'regGFX_IMU_TIMER1_CMP_AUTOINC',
|
|
'regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX',
|
|
'regGFX_IMU_TIMER1_CMP_INTEN',
|
|
'regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER1_CTRL0',
|
|
'regGFX_IMU_TIMER1_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER1_CTRL1',
|
|
'regGFX_IMU_TIMER1_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER1_VALUE',
|
|
'regGFX_IMU_TIMER1_VALUE_BASE_IDX', 'regGFX_IMU_TIMER2_CMP0',
|
|
'regGFX_IMU_TIMER2_CMP0_BASE_IDX', 'regGFX_IMU_TIMER2_CMP1',
|
|
'regGFX_IMU_TIMER2_CMP1_BASE_IDX', 'regGFX_IMU_TIMER2_CMP3',
|
|
'regGFX_IMU_TIMER2_CMP3_BASE_IDX',
|
|
'regGFX_IMU_TIMER2_CMP_AUTOINC',
|
|
'regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX',
|
|
'regGFX_IMU_TIMER2_CMP_INTEN',
|
|
'regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER2_CTRL0',
|
|
'regGFX_IMU_TIMER2_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER2_CTRL1',
|
|
'regGFX_IMU_TIMER2_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER2_VALUE',
|
|
'regGFX_IMU_TIMER2_VALUE_BASE_IDX', 'regGFX_IMU_VDCI_RESET_CTRL',
|
|
'regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX', 'regGFX_IMU_VF_CTRL',
|
|
'regGFX_IMU_VF_CTRL_BASE_IDX', 'regGFX_PIPE_CONTROL',
|
|
'regGFX_PIPE_CONTROL_BASE_IDX', 'regGFX_PIPE_PRIORITY',
|
|
'regGFX_PIPE_PRIORITY_BASE_IDX', 'regGL1A_PERFCOUNTER0_HI',
|
|
'regGL1A_PERFCOUNTER0_HI_BASE_IDX', 'regGL1A_PERFCOUNTER0_LO',
|
|
'regGL1A_PERFCOUNTER0_LO_BASE_IDX', 'regGL1A_PERFCOUNTER0_SELECT',
|
|
'regGL1A_PERFCOUNTER0_SELECT1',
|
|
'regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regGL1A_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER1_HI',
|
|
'regGL1A_PERFCOUNTER1_HI_BASE_IDX', 'regGL1A_PERFCOUNTER1_LO',
|
|
'regGL1A_PERFCOUNTER1_LO_BASE_IDX', 'regGL1A_PERFCOUNTER1_SELECT',
|
|
'regGL1A_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER2_HI',
|
|
'regGL1A_PERFCOUNTER2_HI_BASE_IDX', 'regGL1A_PERFCOUNTER2_LO',
|
|
'regGL1A_PERFCOUNTER2_LO_BASE_IDX', 'regGL1A_PERFCOUNTER2_SELECT',
|
|
'regGL1A_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER3_HI',
|
|
'regGL1A_PERFCOUNTER3_HI_BASE_IDX', 'regGL1A_PERFCOUNTER3_LO',
|
|
'regGL1A_PERFCOUNTER3_LO_BASE_IDX', 'regGL1A_PERFCOUNTER3_SELECT',
|
|
'regGL1A_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER0_HI',
|
|
'regGL1C_PERFCOUNTER0_HI_BASE_IDX', 'regGL1C_PERFCOUNTER0_LO',
|
|
'regGL1C_PERFCOUNTER0_LO_BASE_IDX', 'regGL1C_PERFCOUNTER0_SELECT',
|
|
'regGL1C_PERFCOUNTER0_SELECT1',
|
|
'regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regGL1C_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER1_HI',
|
|
'regGL1C_PERFCOUNTER1_HI_BASE_IDX', 'regGL1C_PERFCOUNTER1_LO',
|
|
'regGL1C_PERFCOUNTER1_LO_BASE_IDX', 'regGL1C_PERFCOUNTER1_SELECT',
|
|
'regGL1C_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER2_HI',
|
|
'regGL1C_PERFCOUNTER2_HI_BASE_IDX', 'regGL1C_PERFCOUNTER2_LO',
|
|
'regGL1C_PERFCOUNTER2_LO_BASE_IDX', 'regGL1C_PERFCOUNTER2_SELECT',
|
|
'regGL1C_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER3_HI',
|
|
'regGL1C_PERFCOUNTER3_HI_BASE_IDX', 'regGL1C_PERFCOUNTER3_LO',
|
|
'regGL1C_PERFCOUNTER3_LO_BASE_IDX', 'regGL1C_PERFCOUNTER3_SELECT',
|
|
'regGL1C_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL1C_STATUS',
|
|
'regGL1C_STATUS_BASE_IDX', 'regGL1C_UTCL0_CNTL1',
|
|
'regGL1C_UTCL0_CNTL1_BASE_IDX', 'regGL1C_UTCL0_CNTL2',
|
|
'regGL1C_UTCL0_CNTL2_BASE_IDX', 'regGL1C_UTCL0_RETRY',
|
|
'regGL1C_UTCL0_RETRY_BASE_IDX', 'regGL1C_UTCL0_STATUS',
|
|
'regGL1C_UTCL0_STATUS_BASE_IDX', 'regGL1H_ARB_CTRL',
|
|
'regGL1H_ARB_CTRL_BASE_IDX', 'regGL1H_ARB_STATUS',
|
|
'regGL1H_ARB_STATUS_BASE_IDX', 'regGL1H_BURST_CTRL',
|
|
'regGL1H_BURST_CTRL_BASE_IDX', 'regGL1H_BURST_MASK',
|
|
'regGL1H_BURST_MASK_BASE_IDX', 'regGL1H_GL1_CREDITS',
|
|
'regGL1H_GL1_CREDITS_BASE_IDX', 'regGL1H_ICG_CTRL',
|
|
'regGL1H_ICG_CTRL_BASE_IDX', 'regGL1H_PERFCOUNTER0_HI',
|
|
'regGL1H_PERFCOUNTER0_HI_BASE_IDX', 'regGL1H_PERFCOUNTER0_LO',
|
|
'regGL1H_PERFCOUNTER0_LO_BASE_IDX', 'regGL1H_PERFCOUNTER0_SELECT',
|
|
'regGL1H_PERFCOUNTER0_SELECT1',
|
|
'regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regGL1H_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER1_HI',
|
|
'regGL1H_PERFCOUNTER1_HI_BASE_IDX', 'regGL1H_PERFCOUNTER1_LO',
|
|
'regGL1H_PERFCOUNTER1_LO_BASE_IDX', 'regGL1H_PERFCOUNTER1_SELECT',
|
|
'regGL1H_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER2_HI',
|
|
'regGL1H_PERFCOUNTER2_HI_BASE_IDX', 'regGL1H_PERFCOUNTER2_LO',
|
|
'regGL1H_PERFCOUNTER2_LO_BASE_IDX', 'regGL1H_PERFCOUNTER2_SELECT',
|
|
'regGL1H_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER3_HI',
|
|
'regGL1H_PERFCOUNTER3_HI_BASE_IDX', 'regGL1H_PERFCOUNTER3_LO',
|
|
'regGL1H_PERFCOUNTER3_LO_BASE_IDX', 'regGL1H_PERFCOUNTER3_SELECT',
|
|
'regGL1H_PERFCOUNTER3_SELECT_BASE_IDX',
|
|
'regGL1I_GL1R_MGCG_OVERRIDE',
|
|
'regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX',
|
|
'regGL1I_GL1R_REP_FGCG_OVERRIDE',
|
|
'regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX', 'regGL1_ARB_STATUS',
|
|
'regGL1_ARB_STATUS_BASE_IDX', 'regGL1_DRAM_BURST_MASK',
|
|
'regGL1_DRAM_BURST_MASK_BASE_IDX', 'regGL1_PIPE_STEER',
|
|
'regGL1_PIPE_STEER_BASE_IDX', 'regGL2A_ADDR_MATCH_CTRL',
|
|
'regGL2A_ADDR_MATCH_CTRL_BASE_IDX', 'regGL2A_ADDR_MATCH_MASK',
|
|
'regGL2A_ADDR_MATCH_MASK_BASE_IDX', 'regGL2A_ADDR_MATCH_SIZE',
|
|
'regGL2A_ADDR_MATCH_SIZE_BASE_IDX', 'regGL2A_PERFCOUNTER0_HI',
|
|
'regGL2A_PERFCOUNTER0_HI_BASE_IDX', 'regGL2A_PERFCOUNTER0_LO',
|
|
'regGL2A_PERFCOUNTER0_LO_BASE_IDX', 'regGL2A_PERFCOUNTER0_SELECT',
|
|
'regGL2A_PERFCOUNTER0_SELECT1',
|
|
'regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regGL2A_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER1_HI',
|
|
'regGL2A_PERFCOUNTER1_HI_BASE_IDX', 'regGL2A_PERFCOUNTER1_LO',
|
|
'regGL2A_PERFCOUNTER1_LO_BASE_IDX', 'regGL2A_PERFCOUNTER1_SELECT',
|
|
'regGL2A_PERFCOUNTER1_SELECT1',
|
|
'regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regGL2A_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER2_HI',
|
|
'regGL2A_PERFCOUNTER2_HI_BASE_IDX', 'regGL2A_PERFCOUNTER2_LO',
|
|
'regGL2A_PERFCOUNTER2_LO_BASE_IDX', 'regGL2A_PERFCOUNTER2_SELECT',
|
|
'regGL2A_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER3_HI',
|
|
'regGL2A_PERFCOUNTER3_HI_BASE_IDX', 'regGL2A_PERFCOUNTER3_LO',
|
|
'regGL2A_PERFCOUNTER3_LO_BASE_IDX', 'regGL2A_PERFCOUNTER3_SELECT',
|
|
'regGL2A_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL2A_PRIORITY_CTRL',
|
|
'regGL2A_PRIORITY_CTRL_BASE_IDX', 'regGL2A_RESP_THROTTLE_CTRL',
|
|
'regGL2A_RESP_THROTTLE_CTRL_BASE_IDX', 'regGL2C_ADDR_MATCH_MASK',
|
|
'regGL2C_ADDR_MATCH_MASK_BASE_IDX', 'regGL2C_ADDR_MATCH_SIZE',
|
|
'regGL2C_ADDR_MATCH_SIZE_BASE_IDX', 'regGL2C_CM_CTRL0',
|
|
'regGL2C_CM_CTRL0_BASE_IDX', 'regGL2C_CM_CTRL1',
|
|
'regGL2C_CM_CTRL1_BASE_IDX', 'regGL2C_CM_STALL',
|
|
'regGL2C_CM_STALL_BASE_IDX', 'regGL2C_CTRL', 'regGL2C_CTRL2',
|
|
'regGL2C_CTRL2_BASE_IDX', 'regGL2C_CTRL3',
|
|
'regGL2C_CTRL3_BASE_IDX', 'regGL2C_CTRL4',
|
|
'regGL2C_CTRL4_BASE_IDX', 'regGL2C_CTRL_BASE_IDX',
|
|
'regGL2C_DISCARD_STALL_CTRL',
|
|
'regGL2C_DISCARD_STALL_CTRL_BASE_IDX', 'regGL2C_LB_CTR_CTRL',
|
|
'regGL2C_LB_CTR_CTRL_BASE_IDX', 'regGL2C_LB_CTR_SEL0',
|
|
'regGL2C_LB_CTR_SEL0_BASE_IDX', 'regGL2C_LB_CTR_SEL1',
|
|
'regGL2C_LB_CTR_SEL1_BASE_IDX', 'regGL2C_LB_DATA0',
|
|
'regGL2C_LB_DATA0_BASE_IDX', 'regGL2C_LB_DATA1',
|
|
'regGL2C_LB_DATA1_BASE_IDX', 'regGL2C_LB_DATA2',
|
|
'regGL2C_LB_DATA2_BASE_IDX', 'regGL2C_LB_DATA3',
|
|
'regGL2C_LB_DATA3_BASE_IDX', 'regGL2C_PERFCOUNTER0_HI',
|
|
'regGL2C_PERFCOUNTER0_HI_BASE_IDX', 'regGL2C_PERFCOUNTER0_LO',
|
|
'regGL2C_PERFCOUNTER0_LO_BASE_IDX', 'regGL2C_PERFCOUNTER0_SELECT',
|
|
'regGL2C_PERFCOUNTER0_SELECT1',
|
|
'regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regGL2C_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER1_HI',
|
|
'regGL2C_PERFCOUNTER1_HI_BASE_IDX', 'regGL2C_PERFCOUNTER1_LO',
|
|
'regGL2C_PERFCOUNTER1_LO_BASE_IDX', 'regGL2C_PERFCOUNTER1_SELECT',
|
|
'regGL2C_PERFCOUNTER1_SELECT1',
|
|
'regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regGL2C_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER2_HI',
|
|
'regGL2C_PERFCOUNTER2_HI_BASE_IDX', 'regGL2C_PERFCOUNTER2_LO',
|
|
'regGL2C_PERFCOUNTER2_LO_BASE_IDX', 'regGL2C_PERFCOUNTER2_SELECT',
|
|
'regGL2C_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER3_HI',
|
|
'regGL2C_PERFCOUNTER3_HI_BASE_IDX', 'regGL2C_PERFCOUNTER3_LO',
|
|
'regGL2C_PERFCOUNTER3_LO_BASE_IDX', 'regGL2C_PERFCOUNTER3_SELECT',
|
|
'regGL2C_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL2C_SOFT_RESET',
|
|
'regGL2C_SOFT_RESET_BASE_IDX', 'regGL2C_WBINVL2',
|
|
'regGL2C_WBINVL2_BASE_IDX', 'regGL2_PIPE_STEER_0',
|
|
'regGL2_PIPE_STEER_0_BASE_IDX', 'regGL2_PIPE_STEER_1',
|
|
'regGL2_PIPE_STEER_1_BASE_IDX', 'regGL2_PIPE_STEER_2',
|
|
'regGL2_PIPE_STEER_2_BASE_IDX', 'regGL2_PIPE_STEER_3',
|
|
'regGL2_PIPE_STEER_3_BASE_IDX', 'regGRBM_CAM_DATA',
|
|
'regGRBM_CAM_DATA_BASE_IDX', 'regGRBM_CAM_DATA_UPPER',
|
|
'regGRBM_CAM_DATA_UPPER_BASE_IDX', 'regGRBM_CAM_INDEX',
|
|
'regGRBM_CAM_INDEX_BASE_IDX', 'regGRBM_CHIP_REVISION',
|
|
'regGRBM_CHIP_REVISION_BASE_IDX', 'regGRBM_CNTL',
|
|
'regGRBM_CNTL_BASE_IDX', 'regGRBM_DSM_BYPASS',
|
|
'regGRBM_DSM_BYPASS_BASE_IDX', 'regGRBM_FENCE_RANGE0',
|
|
'regGRBM_FENCE_RANGE0_BASE_IDX', 'regGRBM_FENCE_RANGE1',
|
|
'regGRBM_FENCE_RANGE1_BASE_IDX', 'regGRBM_GFX_CLKEN_CNTL',
|
|
'regGRBM_GFX_CLKEN_CNTL_BASE_IDX', 'regGRBM_GFX_CNTL',
|
|
'regGRBM_GFX_CNTL_BASE_IDX', 'regGRBM_GFX_CNTL_SR_DATA',
|
|
'regGRBM_GFX_CNTL_SR_DATA_BASE_IDX', 'regGRBM_GFX_CNTL_SR_SELECT',
|
|
'regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX', 'regGRBM_GFX_INDEX',
|
|
'regGRBM_GFX_INDEX_BASE_IDX', 'regGRBM_GFX_INDEX_SR_DATA',
|
|
'regGRBM_GFX_INDEX_SR_DATA_BASE_IDX',
|
|
'regGRBM_GFX_INDEX_SR_SELECT',
|
|
'regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX', 'regGRBM_HYP_CAM_DATA',
|
|
'regGRBM_HYP_CAM_DATA_BASE_IDX', 'regGRBM_HYP_CAM_DATA_UPPER',
|
|
'regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX', 'regGRBM_HYP_CAM_INDEX',
|
|
'regGRBM_HYP_CAM_INDEX_BASE_IDX', 'regGRBM_IH_CREDIT',
|
|
'regGRBM_IH_CREDIT_BASE_IDX', 'regGRBM_INT_CNTL',
|
|
'regGRBM_INT_CNTL_BASE_IDX', 'regGRBM_INVALID_PIPE',
|
|
'regGRBM_INVALID_PIPE_BASE_IDX', 'regGRBM_NOWHERE',
|
|
'regGRBM_NOWHERE_BASE_IDX', 'regGRBM_PERFCOUNTER0_HI',
|
|
'regGRBM_PERFCOUNTER0_HI_BASE_IDX', 'regGRBM_PERFCOUNTER0_LO',
|
|
'regGRBM_PERFCOUNTER0_LO_BASE_IDX', 'regGRBM_PERFCOUNTER0_SELECT',
|
|
'regGRBM_PERFCOUNTER0_SELECT_BASE_IDX',
|
|
'regGRBM_PERFCOUNTER0_SELECT_HI',
|
|
'regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX',
|
|
'regGRBM_PERFCOUNTER1_HI', 'regGRBM_PERFCOUNTER1_HI_BASE_IDX',
|
|
'regGRBM_PERFCOUNTER1_LO', 'regGRBM_PERFCOUNTER1_LO_BASE_IDX',
|
|
'regGRBM_PERFCOUNTER1_SELECT',
|
|
'regGRBM_PERFCOUNTER1_SELECT_BASE_IDX',
|
|
'regGRBM_PERFCOUNTER1_SELECT_HI',
|
|
'regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX', 'regGRBM_PWR_CNTL',
|
|
'regGRBM_PWR_CNTL2', 'regGRBM_PWR_CNTL2_BASE_IDX',
|
|
'regGRBM_PWR_CNTL_BASE_IDX', 'regGRBM_READ_ERROR',
|
|
'regGRBM_READ_ERROR2', 'regGRBM_READ_ERROR2_BASE_IDX',
|
|
'regGRBM_READ_ERROR_BASE_IDX', 'regGRBM_SCRATCH_REG0',
|
|
'regGRBM_SCRATCH_REG0_BASE_IDX', 'regGRBM_SCRATCH_REG1',
|
|
'regGRBM_SCRATCH_REG1_BASE_IDX', 'regGRBM_SCRATCH_REG2',
|
|
'regGRBM_SCRATCH_REG2_BASE_IDX', 'regGRBM_SCRATCH_REG3',
|
|
'regGRBM_SCRATCH_REG3_BASE_IDX', 'regGRBM_SCRATCH_REG4',
|
|
'regGRBM_SCRATCH_REG4_BASE_IDX', 'regGRBM_SCRATCH_REG5',
|
|
'regGRBM_SCRATCH_REG5_BASE_IDX', 'regGRBM_SCRATCH_REG6',
|
|
'regGRBM_SCRATCH_REG6_BASE_IDX', 'regGRBM_SCRATCH_REG7',
|
|
'regGRBM_SCRATCH_REG7_BASE_IDX', 'regGRBM_SE0_PERFCOUNTER_HI',
|
|
'regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX',
|
|
'regGRBM_SE0_PERFCOUNTER_LO',
|
|
'regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX',
|
|
'regGRBM_SE0_PERFCOUNTER_SELECT',
|
|
'regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX',
|
|
'regGRBM_SE1_PERFCOUNTER_HI',
|
|
'regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX',
|
|
'regGRBM_SE1_PERFCOUNTER_LO',
|
|
'regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX',
|
|
'regGRBM_SE1_PERFCOUNTER_SELECT',
|
|
'regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX',
|
|
'regGRBM_SE2_PERFCOUNTER_HI',
|
|
'regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX',
|
|
'regGRBM_SE2_PERFCOUNTER_LO',
|
|
'regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX',
|
|
'regGRBM_SE2_PERFCOUNTER_SELECT',
|
|
'regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX',
|
|
'regGRBM_SE3_PERFCOUNTER_HI',
|
|
'regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX',
|
|
'regGRBM_SE3_PERFCOUNTER_LO',
|
|
'regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX',
|
|
'regGRBM_SE3_PERFCOUNTER_SELECT',
|
|
'regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX',
|
|
'regGRBM_SE4_PERFCOUNTER_HI',
|
|
'regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX',
|
|
'regGRBM_SE4_PERFCOUNTER_LO',
|
|
'regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX',
|
|
'regGRBM_SE4_PERFCOUNTER_SELECT',
|
|
'regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX',
|
|
'regGRBM_SE5_PERFCOUNTER_HI',
|
|
'regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX',
|
|
'regGRBM_SE5_PERFCOUNTER_LO',
|
|
'regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX',
|
|
'regGRBM_SE5_PERFCOUNTER_SELECT',
|
|
'regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX',
|
|
'regGRBM_SE6_PERFCOUNTER_HI',
|
|
'regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX',
|
|
'regGRBM_SE6_PERFCOUNTER_LO',
|
|
'regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX',
|
|
'regGRBM_SE6_PERFCOUNTER_SELECT',
|
|
'regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX', 'regGRBM_SEC_CNTL',
|
|
'regGRBM_SEC_CNTL_BASE_IDX', 'regGRBM_SE_REMAP_CNTL',
|
|
'regGRBM_SE_REMAP_CNTL_BASE_IDX', 'regGRBM_SKEW_CNTL',
|
|
'regGRBM_SKEW_CNTL_BASE_IDX', 'regGRBM_SOFT_RESET',
|
|
'regGRBM_SOFT_RESET_BASE_IDX', 'regGRBM_STATUS',
|
|
'regGRBM_STATUS2', 'regGRBM_STATUS2_BASE_IDX', 'regGRBM_STATUS3',
|
|
'regGRBM_STATUS3_BASE_IDX', 'regGRBM_STATUS_BASE_IDX',
|
|
'regGRBM_STATUS_SE0', 'regGRBM_STATUS_SE0_BASE_IDX',
|
|
'regGRBM_STATUS_SE1', 'regGRBM_STATUS_SE1_BASE_IDX',
|
|
'regGRBM_STATUS_SE2', 'regGRBM_STATUS_SE2_BASE_IDX',
|
|
'regGRBM_STATUS_SE3', 'regGRBM_STATUS_SE3_BASE_IDX',
|
|
'regGRBM_STATUS_SE4', 'regGRBM_STATUS_SE4_BASE_IDX',
|
|
'regGRBM_STATUS_SE5', 'regGRBM_STATUS_SE5_BASE_IDX',
|
|
'regGRBM_TRAP_ADDR', 'regGRBM_TRAP_ADDR_BASE_IDX',
|
|
'regGRBM_TRAP_ADDR_MSK', 'regGRBM_TRAP_ADDR_MSK_BASE_IDX',
|
|
'regGRBM_TRAP_OP', 'regGRBM_TRAP_OP_BASE_IDX', 'regGRBM_TRAP_WD',
|
|
'regGRBM_TRAP_WD_BASE_IDX', 'regGRBM_TRAP_WD_MSK',
|
|
'regGRBM_TRAP_WD_MSK_BASE_IDX', 'regGRBM_UTCL2_INVAL_RANGE_END',
|
|
'regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX',
|
|
'regGRBM_UTCL2_INVAL_RANGE_START',
|
|
'regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX',
|
|
'regGRBM_WAIT_IDLE_CLOCKS', 'regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX',
|
|
'regGRBM_WRITE_ERROR', 'regGRBM_WRITE_ERROR_BASE_IDX',
|
|
'regGRTAVFS_CLK_CNTL', 'regGRTAVFS_CLK_CNTL_BASE_IDX',
|
|
'regGRTAVFS_GENERAL_0', 'regGRTAVFS_GENERAL_0_BASE_IDX',
|
|
'regGRTAVFS_PSM_CNTL', 'regGRTAVFS_PSM_CNTL_BASE_IDX',
|
|
'regGRTAVFS_RTAVFS_RD_DATA', 'regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX',
|
|
'regGRTAVFS_RTAVFS_REG_ADDR',
|
|
'regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX',
|
|
'regGRTAVFS_RTAVFS_REG_CTRL',
|
|
'regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX',
|
|
'regGRTAVFS_RTAVFS_REG_STATUS',
|
|
'regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX',
|
|
'regGRTAVFS_RTAVFS_WR_DATA', 'regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX',
|
|
'regGRTAVFS_SE_CLK_CNTL', 'regGRTAVFS_SE_CLK_CNTL_BASE_IDX',
|
|
'regGRTAVFS_SE_GENERAL_0', 'regGRTAVFS_SE_GENERAL_0_BASE_IDX',
|
|
'regGRTAVFS_SE_PSM_CNTL', 'regGRTAVFS_SE_PSM_CNTL_BASE_IDX',
|
|
'regGRTAVFS_SE_RTAVFS_RD_DATA',
|
|
'regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX',
|
|
'regGRTAVFS_SE_RTAVFS_REG_ADDR',
|
|
'regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX',
|
|
'regGRTAVFS_SE_RTAVFS_REG_CTRL',
|
|
'regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX',
|
|
'regGRTAVFS_SE_RTAVFS_REG_STATUS',
|
|
'regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX',
|
|
'regGRTAVFS_SE_RTAVFS_WR_DATA',
|
|
'regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX',
|
|
'regGRTAVFS_SE_SOFT_RESET', 'regGRTAVFS_SE_SOFT_RESET_BASE_IDX',
|
|
'regGRTAVFS_SE_TARG_FREQ', 'regGRTAVFS_SE_TARG_FREQ_BASE_IDX',
|
|
'regGRTAVFS_SE_TARG_VOLT', 'regGRTAVFS_SE_TARG_VOLT_BASE_IDX',
|
|
'regGRTAVFS_SOFT_RESET', 'regGRTAVFS_SOFT_RESET_BASE_IDX',
|
|
'regGRTAVFS_TARG_FREQ', 'regGRTAVFS_TARG_FREQ_BASE_IDX',
|
|
'regGRTAVFS_TARG_VOLT', 'regGRTAVFS_TARG_VOLT_BASE_IDX',
|
|
'regGUS_DRAM_COMBINE_FLUSH', 'regGUS_DRAM_COMBINE_FLUSH_BASE_IDX',
|
|
'regGUS_DRAM_COMBINE_RD_WR_EN',
|
|
'regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX',
|
|
'regGUS_DRAM_GROUP_BURST', 'regGUS_DRAM_GROUP_BURST_BASE_IDX',
|
|
'regGUS_DRAM_PRI_AGE_COEFF', 'regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX',
|
|
'regGUS_DRAM_PRI_AGE_RATE', 'regGUS_DRAM_PRI_AGE_RATE_BASE_IDX',
|
|
'regGUS_DRAM_PRI_FIXED', 'regGUS_DRAM_PRI_FIXED_BASE_IDX',
|
|
'regGUS_DRAM_PRI_QUANT1_PRI1',
|
|
'regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX',
|
|
'regGUS_DRAM_PRI_QUANT1_PRI2',
|
|
'regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX',
|
|
'regGUS_DRAM_PRI_QUANT1_PRI3',
|
|
'regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX',
|
|
'regGUS_DRAM_PRI_QUANT1_PRI4',
|
|
'regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX',
|
|
'regGUS_DRAM_PRI_QUANT1_PRI5',
|
|
'regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX',
|
|
'regGUS_DRAM_PRI_QUANT_PRI1',
|
|
'regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX',
|
|
'regGUS_DRAM_PRI_QUANT_PRI2',
|
|
'regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX',
|
|
'regGUS_DRAM_PRI_QUANT_PRI3',
|
|
'regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX',
|
|
'regGUS_DRAM_PRI_QUANT_PRI4',
|
|
'regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX',
|
|
'regGUS_DRAM_PRI_QUANT_PRI5',
|
|
'regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX', 'regGUS_DRAM_PRI_QUEUING',
|
|
'regGUS_DRAM_PRI_QUEUING_BASE_IDX',
|
|
'regGUS_DRAM_PRI_URGENCY_COEFF',
|
|
'regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX',
|
|
'regGUS_DRAM_PRI_URGENCY_MODE',
|
|
'regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX', 'regGUS_ERR_STATUS',
|
|
'regGUS_ERR_STATUS_BASE_IDX', 'regGUS_ICG_CTRL',
|
|
'regGUS_ICG_CTRL_BASE_IDX', 'regGUS_IO_GROUP_BURST',
|
|
'regGUS_IO_GROUP_BURST_BASE_IDX', 'regGUS_IO_RD_COMBINE_FLUSH',
|
|
'regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_AGE_COEFF',
|
|
'regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_AGE_RATE', 'regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_FIXED', 'regGUS_IO_RD_PRI_FIXED_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_QUANT1_PRI1',
|
|
'regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_QUANT1_PRI2',
|
|
'regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_QUANT1_PRI3',
|
|
'regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_QUANT1_PRI4',
|
|
'regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_QUANT_PRI1',
|
|
'regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_QUANT_PRI2',
|
|
'regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_QUANT_PRI3',
|
|
'regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_QUANT_PRI4',
|
|
'regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_QUEUING', 'regGUS_IO_RD_PRI_QUEUING_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_URGENCY_COEFF',
|
|
'regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX',
|
|
'regGUS_IO_RD_PRI_URGENCY_MODE',
|
|
'regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX',
|
|
'regGUS_IO_WR_COMBINE_FLUSH',
|
|
'regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_AGE_COEFF',
|
|
'regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_AGE_RATE', 'regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_FIXED', 'regGUS_IO_WR_PRI_FIXED_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_QUANT1_PRI1',
|
|
'regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_QUANT1_PRI2',
|
|
'regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_QUANT1_PRI3',
|
|
'regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_QUANT1_PRI4',
|
|
'regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_QUANT_PRI1',
|
|
'regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_QUANT_PRI2',
|
|
'regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_QUANT_PRI3',
|
|
'regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_QUANT_PRI4',
|
|
'regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_QUEUING', 'regGUS_IO_WR_PRI_QUEUING_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_URGENCY_COEFF',
|
|
'regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX',
|
|
'regGUS_IO_WR_PRI_URGENCY_MODE',
|
|
'regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX', 'regGUS_L1_CH0_CMD_IN',
|
|
'regGUS_L1_CH0_CMD_IN_BASE_IDX', 'regGUS_L1_CH0_CMD_OUT',
|
|
'regGUS_L1_CH0_CMD_OUT_BASE_IDX', 'regGUS_L1_CH0_DATA_IN',
|
|
'regGUS_L1_CH0_DATA_IN_BASE_IDX', 'regGUS_L1_CH0_DATA_OUT',
|
|
'regGUS_L1_CH0_DATA_OUT_BASE_IDX', 'regGUS_L1_CH0_DATA_U_IN',
|
|
'regGUS_L1_CH0_DATA_U_IN_BASE_IDX', 'regGUS_L1_CH0_DATA_U_OUT',
|
|
'regGUS_L1_CH0_DATA_U_OUT_BASE_IDX', 'regGUS_L1_CH1_CMD_IN',
|
|
'regGUS_L1_CH1_CMD_IN_BASE_IDX', 'regGUS_L1_CH1_CMD_OUT',
|
|
'regGUS_L1_CH1_CMD_OUT_BASE_IDX', 'regGUS_L1_CH1_DATA_IN',
|
|
'regGUS_L1_CH1_DATA_IN_BASE_IDX', 'regGUS_L1_CH1_DATA_OUT',
|
|
'regGUS_L1_CH1_DATA_OUT_BASE_IDX', 'regGUS_L1_CH1_DATA_U_IN',
|
|
'regGUS_L1_CH1_DATA_U_IN_BASE_IDX', 'regGUS_L1_CH1_DATA_U_OUT',
|
|
'regGUS_L1_CH1_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA0_CMD_IN',
|
|
'regGUS_L1_SA0_CMD_IN_BASE_IDX', 'regGUS_L1_SA0_CMD_OUT',
|
|
'regGUS_L1_SA0_CMD_OUT_BASE_IDX', 'regGUS_L1_SA0_DATA_IN',
|
|
'regGUS_L1_SA0_DATA_IN_BASE_IDX', 'regGUS_L1_SA0_DATA_OUT',
|
|
'regGUS_L1_SA0_DATA_OUT_BASE_IDX', 'regGUS_L1_SA0_DATA_U_IN',
|
|
'regGUS_L1_SA0_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA0_DATA_U_OUT',
|
|
'regGUS_L1_SA0_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA1_CMD_IN',
|
|
'regGUS_L1_SA1_CMD_IN_BASE_IDX', 'regGUS_L1_SA1_CMD_OUT',
|
|
'regGUS_L1_SA1_CMD_OUT_BASE_IDX', 'regGUS_L1_SA1_DATA_IN',
|
|
'regGUS_L1_SA1_DATA_IN_BASE_IDX', 'regGUS_L1_SA1_DATA_OUT',
|
|
'regGUS_L1_SA1_DATA_OUT_BASE_IDX', 'regGUS_L1_SA1_DATA_U_IN',
|
|
'regGUS_L1_SA1_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA1_DATA_U_OUT',
|
|
'regGUS_L1_SA1_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA2_CMD_IN',
|
|
'regGUS_L1_SA2_CMD_IN_BASE_IDX', 'regGUS_L1_SA2_CMD_OUT',
|
|
'regGUS_L1_SA2_CMD_OUT_BASE_IDX', 'regGUS_L1_SA2_DATA_IN',
|
|
'regGUS_L1_SA2_DATA_IN_BASE_IDX', 'regGUS_L1_SA2_DATA_OUT',
|
|
'regGUS_L1_SA2_DATA_OUT_BASE_IDX', 'regGUS_L1_SA2_DATA_U_IN',
|
|
'regGUS_L1_SA2_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA2_DATA_U_OUT',
|
|
'regGUS_L1_SA2_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA3_CMD_IN',
|
|
'regGUS_L1_SA3_CMD_IN_BASE_IDX', 'regGUS_L1_SA3_CMD_OUT',
|
|
'regGUS_L1_SA3_CMD_OUT_BASE_IDX', 'regGUS_L1_SA3_DATA_IN',
|
|
'regGUS_L1_SA3_DATA_IN_BASE_IDX', 'regGUS_L1_SA3_DATA_OUT',
|
|
'regGUS_L1_SA3_DATA_OUT_BASE_IDX', 'regGUS_L1_SA3_DATA_U_IN',
|
|
'regGUS_L1_SA3_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA3_DATA_U_OUT',
|
|
'regGUS_L1_SA3_DATA_U_OUT_BASE_IDX', 'regGUS_LATENCY_SAMPLING',
|
|
'regGUS_LATENCY_SAMPLING_BASE_IDX', 'regGUS_MISC', 'regGUS_MISC2',
|
|
'regGUS_MISC2_BASE_IDX', 'regGUS_MISC3', 'regGUS_MISC3_BASE_IDX',
|
|
'regGUS_MISC_BASE_IDX', 'regGUS_PERFCOUNTER0_CFG',
|
|
'regGUS_PERFCOUNTER0_CFG_BASE_IDX', 'regGUS_PERFCOUNTER1_CFG',
|
|
'regGUS_PERFCOUNTER1_CFG_BASE_IDX', 'regGUS_PERFCOUNTER2_HI',
|
|
'regGUS_PERFCOUNTER2_HI_BASE_IDX', 'regGUS_PERFCOUNTER2_LO',
|
|
'regGUS_PERFCOUNTER2_LO_BASE_IDX', 'regGUS_PERFCOUNTER2_MODE',
|
|
'regGUS_PERFCOUNTER2_MODE_BASE_IDX', 'regGUS_PERFCOUNTER2_SELECT',
|
|
'regGUS_PERFCOUNTER2_SELECT1',
|
|
'regGUS_PERFCOUNTER2_SELECT1_BASE_IDX',
|
|
'regGUS_PERFCOUNTER2_SELECT_BASE_IDX', 'regGUS_PERFCOUNTER_HI',
|
|
'regGUS_PERFCOUNTER_HI_BASE_IDX', 'regGUS_PERFCOUNTER_LO',
|
|
'regGUS_PERFCOUNTER_LO_BASE_IDX', 'regGUS_PERFCOUNTER_RSLT_CNTL',
|
|
'regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regGUS_SDP_ARB_FINAL',
|
|
'regGUS_SDP_ARB_FINAL_BASE_IDX', 'regGUS_SDP_CREDITS',
|
|
'regGUS_SDP_CREDITS_BASE_IDX', 'regGUS_SDP_ENABLE',
|
|
'regGUS_SDP_ENABLE_BASE_IDX', 'regGUS_SDP_QOS_VC_PRIORITY',
|
|
'regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX', 'regGUS_SDP_REQ_CNTL',
|
|
'regGUS_SDP_REQ_CNTL_BASE_IDX', 'regGUS_SDP_TAG_RESERVE0',
|
|
'regGUS_SDP_TAG_RESERVE0_BASE_IDX', 'regGUS_SDP_TAG_RESERVE1',
|
|
'regGUS_SDP_TAG_RESERVE1_BASE_IDX', 'regGUS_SDP_VCC_RESERVE0',
|
|
'regGUS_SDP_VCC_RESERVE0_BASE_IDX', 'regGUS_SDP_VCC_RESERVE1',
|
|
'regGUS_SDP_VCC_RESERVE1_BASE_IDX', 'regGUS_SDP_VCD_RESERVE0',
|
|
'regGUS_SDP_VCD_RESERVE0_BASE_IDX', 'regGUS_SDP_VCD_RESERVE1',
|
|
'regGUS_SDP_VCD_RESERVE1_BASE_IDX', 'regGUS_WRRSP_FIFO_CNTL',
|
|
'regGUS_WRRSP_FIFO_CNTL_BASE_IDX', 'regIA_ENHANCE',
|
|
'regIA_ENHANCE_BASE_IDX', 'regIA_UTCL1_CNTL',
|
|
'regIA_UTCL1_CNTL_BASE_IDX', 'regIA_UTCL1_STATUS',
|
|
'regIA_UTCL1_STATUS_2', 'regIA_UTCL1_STATUS_2_BASE_IDX',
|
|
'regIA_UTCL1_STATUS_BASE_IDX', 'regICG_CHA_CTRL',
|
|
'regICG_CHA_CTRL_BASE_IDX', 'regICG_CHCG_CLK_CTRL',
|
|
'regICG_CHCG_CLK_CTRL_BASE_IDX', 'regICG_CHC_CLK_CTRL',
|
|
'regICG_CHC_CLK_CTRL_BASE_IDX', 'regICG_GL1A_CTRL',
|
|
'regICG_GL1A_CTRL_BASE_IDX', 'regICG_GL1C_CLK_CTRL',
|
|
'regICG_GL1C_CLK_CTRL_BASE_IDX', 'regICG_LDS_CLK_CTRL',
|
|
'regICG_LDS_CLK_CTRL_BASE_IDX', 'regICG_SP_CLK_CTRL',
|
|
'regICG_SP_CLK_CTRL_BASE_IDX', 'regLDS_CONFIG',
|
|
'regLDS_CONFIG_BASE_IDX', 'regPA_CL_CLIP_CNTL',
|
|
'regPA_CL_CLIP_CNTL_BASE_IDX', 'regPA_CL_CNTL_STATUS',
|
|
'regPA_CL_CNTL_STATUS_BASE_IDX', 'regPA_CL_ENHANCE',
|
|
'regPA_CL_ENHANCE_BASE_IDX', 'regPA_CL_GB_HORZ_CLIP_ADJ',
|
|
'regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX', 'regPA_CL_GB_HORZ_DISC_ADJ',
|
|
'regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX', 'regPA_CL_GB_VERT_CLIP_ADJ',
|
|
'regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX', 'regPA_CL_GB_VERT_DISC_ADJ',
|
|
'regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX', 'regPA_CL_NANINF_CNTL',
|
|
'regPA_CL_NANINF_CNTL_BASE_IDX', 'regPA_CL_NGG_CNTL',
|
|
'regPA_CL_NGG_CNTL_BASE_IDX', 'regPA_CL_POINT_CULL_RAD',
|
|
'regPA_CL_POINT_CULL_RAD_BASE_IDX', 'regPA_CL_POINT_SIZE',
|
|
'regPA_CL_POINT_SIZE_BASE_IDX', 'regPA_CL_POINT_X_RAD',
|
|
'regPA_CL_POINT_X_RAD_BASE_IDX', 'regPA_CL_POINT_Y_RAD',
|
|
'regPA_CL_POINT_Y_RAD_BASE_IDX', 'regPA_CL_PROG_NEAR_CLIP_Z',
|
|
'regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX', 'regPA_CL_UCP_0_W',
|
|
'regPA_CL_UCP_0_W_BASE_IDX', 'regPA_CL_UCP_0_X',
|
|
'regPA_CL_UCP_0_X_BASE_IDX', 'regPA_CL_UCP_0_Y',
|
|
'regPA_CL_UCP_0_Y_BASE_IDX', 'regPA_CL_UCP_0_Z',
|
|
'regPA_CL_UCP_0_Z_BASE_IDX', 'regPA_CL_UCP_1_W',
|
|
'regPA_CL_UCP_1_W_BASE_IDX', 'regPA_CL_UCP_1_X',
|
|
'regPA_CL_UCP_1_X_BASE_IDX', 'regPA_CL_UCP_1_Y',
|
|
'regPA_CL_UCP_1_Y_BASE_IDX', 'regPA_CL_UCP_1_Z',
|
|
'regPA_CL_UCP_1_Z_BASE_IDX', 'regPA_CL_UCP_2_W',
|
|
'regPA_CL_UCP_2_W_BASE_IDX', 'regPA_CL_UCP_2_X',
|
|
'regPA_CL_UCP_2_X_BASE_IDX', 'regPA_CL_UCP_2_Y',
|
|
'regPA_CL_UCP_2_Y_BASE_IDX', 'regPA_CL_UCP_2_Z',
|
|
'regPA_CL_UCP_2_Z_BASE_IDX', 'regPA_CL_UCP_3_W',
|
|
'regPA_CL_UCP_3_W_BASE_IDX', 'regPA_CL_UCP_3_X',
|
|
'regPA_CL_UCP_3_X_BASE_IDX', 'regPA_CL_UCP_3_Y',
|
|
'regPA_CL_UCP_3_Y_BASE_IDX', 'regPA_CL_UCP_3_Z',
|
|
'regPA_CL_UCP_3_Z_BASE_IDX', 'regPA_CL_UCP_4_W',
|
|
'regPA_CL_UCP_4_W_BASE_IDX', 'regPA_CL_UCP_4_X',
|
|
'regPA_CL_UCP_4_X_BASE_IDX', 'regPA_CL_UCP_4_Y',
|
|
'regPA_CL_UCP_4_Y_BASE_IDX', 'regPA_CL_UCP_4_Z',
|
|
'regPA_CL_UCP_4_Z_BASE_IDX', 'regPA_CL_UCP_5_W',
|
|
'regPA_CL_UCP_5_W_BASE_IDX', 'regPA_CL_UCP_5_X',
|
|
'regPA_CL_UCP_5_X_BASE_IDX', 'regPA_CL_UCP_5_Y',
|
|
'regPA_CL_UCP_5_Y_BASE_IDX', 'regPA_CL_UCP_5_Z',
|
|
'regPA_CL_UCP_5_Z_BASE_IDX', 'regPA_CL_VPORT_XOFFSET',
|
|
'regPA_CL_VPORT_XOFFSET_1', 'regPA_CL_VPORT_XOFFSET_10',
|
|
'regPA_CL_VPORT_XOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_11',
|
|
'regPA_CL_VPORT_XOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_12',
|
|
'regPA_CL_VPORT_XOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_13',
|
|
'regPA_CL_VPORT_XOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_14',
|
|
'regPA_CL_VPORT_XOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_15',
|
|
'regPA_CL_VPORT_XOFFSET_15_BASE_IDX',
|
|
'regPA_CL_VPORT_XOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_2',
|
|
'regPA_CL_VPORT_XOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_3',
|
|
'regPA_CL_VPORT_XOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_4',
|
|
'regPA_CL_VPORT_XOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_5',
|
|
'regPA_CL_VPORT_XOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_6',
|
|
'regPA_CL_VPORT_XOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_7',
|
|
'regPA_CL_VPORT_XOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_8',
|
|
'regPA_CL_VPORT_XOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_9',
|
|
'regPA_CL_VPORT_XOFFSET_9_BASE_IDX',
|
|
'regPA_CL_VPORT_XOFFSET_BASE_IDX', 'regPA_CL_VPORT_XSCALE',
|
|
'regPA_CL_VPORT_XSCALE_1', 'regPA_CL_VPORT_XSCALE_10',
|
|
'regPA_CL_VPORT_XSCALE_10_BASE_IDX', 'regPA_CL_VPORT_XSCALE_11',
|
|
'regPA_CL_VPORT_XSCALE_11_BASE_IDX', 'regPA_CL_VPORT_XSCALE_12',
|
|
'regPA_CL_VPORT_XSCALE_12_BASE_IDX', 'regPA_CL_VPORT_XSCALE_13',
|
|
'regPA_CL_VPORT_XSCALE_13_BASE_IDX', 'regPA_CL_VPORT_XSCALE_14',
|
|
'regPA_CL_VPORT_XSCALE_14_BASE_IDX', 'regPA_CL_VPORT_XSCALE_15',
|
|
'regPA_CL_VPORT_XSCALE_15_BASE_IDX',
|
|
'regPA_CL_VPORT_XSCALE_1_BASE_IDX', 'regPA_CL_VPORT_XSCALE_2',
|
|
'regPA_CL_VPORT_XSCALE_2_BASE_IDX', 'regPA_CL_VPORT_XSCALE_3',
|
|
'regPA_CL_VPORT_XSCALE_3_BASE_IDX', 'regPA_CL_VPORT_XSCALE_4',
|
|
'regPA_CL_VPORT_XSCALE_4_BASE_IDX', 'regPA_CL_VPORT_XSCALE_5',
|
|
'regPA_CL_VPORT_XSCALE_5_BASE_IDX', 'regPA_CL_VPORT_XSCALE_6',
|
|
'regPA_CL_VPORT_XSCALE_6_BASE_IDX', 'regPA_CL_VPORT_XSCALE_7',
|
|
'regPA_CL_VPORT_XSCALE_7_BASE_IDX', 'regPA_CL_VPORT_XSCALE_8',
|
|
'regPA_CL_VPORT_XSCALE_8_BASE_IDX', 'regPA_CL_VPORT_XSCALE_9',
|
|
'regPA_CL_VPORT_XSCALE_9_BASE_IDX',
|
|
'regPA_CL_VPORT_XSCALE_BASE_IDX', 'regPA_CL_VPORT_YOFFSET',
|
|
'regPA_CL_VPORT_YOFFSET_1', 'regPA_CL_VPORT_YOFFSET_10',
|
|
'regPA_CL_VPORT_YOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_11',
|
|
'regPA_CL_VPORT_YOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_12',
|
|
'regPA_CL_VPORT_YOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_13',
|
|
'regPA_CL_VPORT_YOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_14',
|
|
'regPA_CL_VPORT_YOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_15',
|
|
'regPA_CL_VPORT_YOFFSET_15_BASE_IDX',
|
|
'regPA_CL_VPORT_YOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_2',
|
|
'regPA_CL_VPORT_YOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_3',
|
|
'regPA_CL_VPORT_YOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_4',
|
|
'regPA_CL_VPORT_YOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_5',
|
|
'regPA_CL_VPORT_YOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_6',
|
|
'regPA_CL_VPORT_YOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_7',
|
|
'regPA_CL_VPORT_YOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_8',
|
|
'regPA_CL_VPORT_YOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_9',
|
|
'regPA_CL_VPORT_YOFFSET_9_BASE_IDX',
|
|
'regPA_CL_VPORT_YOFFSET_BASE_IDX', 'regPA_CL_VPORT_YSCALE',
|
|
'regPA_CL_VPORT_YSCALE_1', 'regPA_CL_VPORT_YSCALE_10',
|
|
'regPA_CL_VPORT_YSCALE_10_BASE_IDX', 'regPA_CL_VPORT_YSCALE_11',
|
|
'regPA_CL_VPORT_YSCALE_11_BASE_IDX', 'regPA_CL_VPORT_YSCALE_12',
|
|
'regPA_CL_VPORT_YSCALE_12_BASE_IDX', 'regPA_CL_VPORT_YSCALE_13',
|
|
'regPA_CL_VPORT_YSCALE_13_BASE_IDX', 'regPA_CL_VPORT_YSCALE_14',
|
|
'regPA_CL_VPORT_YSCALE_14_BASE_IDX', 'regPA_CL_VPORT_YSCALE_15',
|
|
'regPA_CL_VPORT_YSCALE_15_BASE_IDX',
|
|
'regPA_CL_VPORT_YSCALE_1_BASE_IDX', 'regPA_CL_VPORT_YSCALE_2',
|
|
'regPA_CL_VPORT_YSCALE_2_BASE_IDX', 'regPA_CL_VPORT_YSCALE_3',
|
|
'regPA_CL_VPORT_YSCALE_3_BASE_IDX', 'regPA_CL_VPORT_YSCALE_4',
|
|
'regPA_CL_VPORT_YSCALE_4_BASE_IDX', 'regPA_CL_VPORT_YSCALE_5',
|
|
'regPA_CL_VPORT_YSCALE_5_BASE_IDX', 'regPA_CL_VPORT_YSCALE_6',
|
|
'regPA_CL_VPORT_YSCALE_6_BASE_IDX', 'regPA_CL_VPORT_YSCALE_7',
|
|
'regPA_CL_VPORT_YSCALE_7_BASE_IDX', 'regPA_CL_VPORT_YSCALE_8',
|
|
'regPA_CL_VPORT_YSCALE_8_BASE_IDX', 'regPA_CL_VPORT_YSCALE_9',
|
|
'regPA_CL_VPORT_YSCALE_9_BASE_IDX',
|
|
'regPA_CL_VPORT_YSCALE_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET',
|
|
'regPA_CL_VPORT_ZOFFSET_1', 'regPA_CL_VPORT_ZOFFSET_10',
|
|
'regPA_CL_VPORT_ZOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_11',
|
|
'regPA_CL_VPORT_ZOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_12',
|
|
'regPA_CL_VPORT_ZOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_13',
|
|
'regPA_CL_VPORT_ZOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_14',
|
|
'regPA_CL_VPORT_ZOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_15',
|
|
'regPA_CL_VPORT_ZOFFSET_15_BASE_IDX',
|
|
'regPA_CL_VPORT_ZOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_2',
|
|
'regPA_CL_VPORT_ZOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_3',
|
|
'regPA_CL_VPORT_ZOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_4',
|
|
'regPA_CL_VPORT_ZOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_5',
|
|
'regPA_CL_VPORT_ZOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_6',
|
|
'regPA_CL_VPORT_ZOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_7',
|
|
'regPA_CL_VPORT_ZOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_8',
|
|
'regPA_CL_VPORT_ZOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_9',
|
|
'regPA_CL_VPORT_ZOFFSET_9_BASE_IDX',
|
|
'regPA_CL_VPORT_ZOFFSET_BASE_IDX', 'regPA_CL_VPORT_ZSCALE',
|
|
'regPA_CL_VPORT_ZSCALE_1', 'regPA_CL_VPORT_ZSCALE_10',
|
|
'regPA_CL_VPORT_ZSCALE_10_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_11',
|
|
'regPA_CL_VPORT_ZSCALE_11_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_12',
|
|
'regPA_CL_VPORT_ZSCALE_12_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_13',
|
|
'regPA_CL_VPORT_ZSCALE_13_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_14',
|
|
'regPA_CL_VPORT_ZSCALE_14_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_15',
|
|
'regPA_CL_VPORT_ZSCALE_15_BASE_IDX',
|
|
'regPA_CL_VPORT_ZSCALE_1_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_2',
|
|
'regPA_CL_VPORT_ZSCALE_2_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_3',
|
|
'regPA_CL_VPORT_ZSCALE_3_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_4',
|
|
'regPA_CL_VPORT_ZSCALE_4_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_5',
|
|
'regPA_CL_VPORT_ZSCALE_5_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_6',
|
|
'regPA_CL_VPORT_ZSCALE_6_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_7',
|
|
'regPA_CL_VPORT_ZSCALE_7_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_8',
|
|
'regPA_CL_VPORT_ZSCALE_8_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_9',
|
|
'regPA_CL_VPORT_ZSCALE_9_BASE_IDX',
|
|
'regPA_CL_VPORT_ZSCALE_BASE_IDX', 'regPA_CL_VRS_CNTL',
|
|
'regPA_CL_VRS_CNTL_BASE_IDX', 'regPA_CL_VS_OUT_CNTL',
|
|
'regPA_CL_VS_OUT_CNTL_BASE_IDX', 'regPA_CL_VTE_CNTL',
|
|
'regPA_CL_VTE_CNTL_BASE_IDX', 'regPA_PH_ENHANCE',
|
|
'regPA_PH_ENHANCE_BASE_IDX', 'regPA_PH_INTERFACE_FIFO_SIZE',
|
|
'regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER0_HI', 'regPA_PH_PERFCOUNTER0_HI_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER0_LO', 'regPA_PH_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER0_SELECT', 'regPA_PH_PERFCOUNTER0_SELECT1',
|
|
'regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER1_HI', 'regPA_PH_PERFCOUNTER1_HI_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER1_LO', 'regPA_PH_PERFCOUNTER1_LO_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER1_SELECT', 'regPA_PH_PERFCOUNTER1_SELECT1',
|
|
'regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER2_HI', 'regPA_PH_PERFCOUNTER2_HI_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER2_LO', 'regPA_PH_PERFCOUNTER2_LO_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER2_SELECT', 'regPA_PH_PERFCOUNTER2_SELECT1',
|
|
'regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER3_HI', 'regPA_PH_PERFCOUNTER3_HI_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER3_LO', 'regPA_PH_PERFCOUNTER3_LO_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER3_SELECT', 'regPA_PH_PERFCOUNTER3_SELECT1',
|
|
'regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER4_HI', 'regPA_PH_PERFCOUNTER4_HI_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER4_LO', 'regPA_PH_PERFCOUNTER4_LO_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER4_SELECT',
|
|
'regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER5_HI', 'regPA_PH_PERFCOUNTER5_HI_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER5_LO', 'regPA_PH_PERFCOUNTER5_LO_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER5_SELECT',
|
|
'regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER6_HI', 'regPA_PH_PERFCOUNTER6_HI_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER6_LO', 'regPA_PH_PERFCOUNTER6_LO_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER6_SELECT',
|
|
'regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER7_HI', 'regPA_PH_PERFCOUNTER7_HI_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER7_LO', 'regPA_PH_PERFCOUNTER7_LO_BASE_IDX',
|
|
'regPA_PH_PERFCOUNTER7_SELECT',
|
|
'regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX', 'regPA_RATE_CNTL',
|
|
'regPA_RATE_CNTL_BASE_IDX', 'regPA_SC_AA_CONFIG',
|
|
'regPA_SC_AA_CONFIG_BASE_IDX', 'regPA_SC_AA_MASK_X0Y0_X1Y0',
|
|
'regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX',
|
|
'regPA_SC_AA_MASK_X0Y1_X1Y1',
|
|
'regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3',
|
|
'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX',
|
|
'regPA_SC_ATM_CNTL', 'regPA_SC_ATM_CNTL_BASE_IDX',
|
|
'regPA_SC_BINNER_CNTL_0', 'regPA_SC_BINNER_CNTL_0_BASE_IDX',
|
|
'regPA_SC_BINNER_CNTL_1', 'regPA_SC_BINNER_CNTL_1_BASE_IDX',
|
|
'regPA_SC_BINNER_CNTL_2', 'regPA_SC_BINNER_CNTL_2_BASE_IDX',
|
|
'regPA_SC_BINNER_CNTL_OVERRIDE',
|
|
'regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX',
|
|
'regPA_SC_BINNER_EVENT_CNTL_0',
|
|
'regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX',
|
|
'regPA_SC_BINNER_EVENT_CNTL_1',
|
|
'regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX',
|
|
'regPA_SC_BINNER_EVENT_CNTL_2',
|
|
'regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX',
|
|
'regPA_SC_BINNER_EVENT_CNTL_3',
|
|
'regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX',
|
|
'regPA_SC_BINNER_PERF_CNTL_0',
|
|
'regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX',
|
|
'regPA_SC_BINNER_PERF_CNTL_1',
|
|
'regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX',
|
|
'regPA_SC_BINNER_PERF_CNTL_2',
|
|
'regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX',
|
|
'regPA_SC_BINNER_PERF_CNTL_3',
|
|
'regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX',
|
|
'regPA_SC_BINNER_TIMEOUT_COUNTER',
|
|
'regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX',
|
|
'regPA_SC_CENTROID_PRIORITY_0',
|
|
'regPA_SC_CENTROID_PRIORITY_0_BASE_IDX',
|
|
'regPA_SC_CENTROID_PRIORITY_1',
|
|
'regPA_SC_CENTROID_PRIORITY_1_BASE_IDX', 'regPA_SC_CLIPRECT_0_BR',
|
|
'regPA_SC_CLIPRECT_0_BR_BASE_IDX', 'regPA_SC_CLIPRECT_0_TL',
|
|
'regPA_SC_CLIPRECT_0_TL_BASE_IDX', 'regPA_SC_CLIPRECT_1_BR',
|
|
'regPA_SC_CLIPRECT_1_BR_BASE_IDX', 'regPA_SC_CLIPRECT_1_TL',
|
|
'regPA_SC_CLIPRECT_1_TL_BASE_IDX', 'regPA_SC_CLIPRECT_2_BR',
|
|
'regPA_SC_CLIPRECT_2_BR_BASE_IDX', 'regPA_SC_CLIPRECT_2_TL',
|
|
'regPA_SC_CLIPRECT_2_TL_BASE_IDX', 'regPA_SC_CLIPRECT_3_BR',
|
|
'regPA_SC_CLIPRECT_3_BR_BASE_IDX', 'regPA_SC_CLIPRECT_3_TL',
|
|
'regPA_SC_CLIPRECT_3_TL_BASE_IDX', 'regPA_SC_CLIPRECT_RULE',
|
|
'regPA_SC_CLIPRECT_RULE_BASE_IDX',
|
|
'regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL',
|
|
'regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX',
|
|
'regPA_SC_DSM_CNTL', 'regPA_SC_DSM_CNTL_BASE_IDX',
|
|
'regPA_SC_EDGERULE', 'regPA_SC_EDGERULE_BASE_IDX',
|
|
'regPA_SC_ENHANCE', 'regPA_SC_ENHANCE_1',
|
|
'regPA_SC_ENHANCE_1_BASE_IDX', 'regPA_SC_ENHANCE_2',
|
|
'regPA_SC_ENHANCE_2_BASE_IDX', 'regPA_SC_ENHANCE_3',
|
|
'regPA_SC_ENHANCE_3_BASE_IDX', 'regPA_SC_ENHANCE_BASE_IDX',
|
|
'regPA_SC_FIFO_DEPTH_CNTL', 'regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX',
|
|
'regPA_SC_FIFO_SIZE', 'regPA_SC_FIFO_SIZE_BASE_IDX',
|
|
'regPA_SC_FORCE_EOV_MAX_CNTS',
|
|
'regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX',
|
|
'regPA_SC_GENERIC_SCISSOR_BR',
|
|
'regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX',
|
|
'regPA_SC_GENERIC_SCISSOR_TL',
|
|
'regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX',
|
|
'regPA_SC_HP3D_TRAP_SCREEN_COUNT',
|
|
'regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX',
|
|
'regPA_SC_HP3D_TRAP_SCREEN_H', 'regPA_SC_HP3D_TRAP_SCREEN_HV_EN',
|
|
'regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX',
|
|
'regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK',
|
|
'regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX',
|
|
'regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX',
|
|
'regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE',
|
|
'regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX',
|
|
'regPA_SC_HP3D_TRAP_SCREEN_V',
|
|
'regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX', 'regPA_SC_IF_FIFO_SIZE',
|
|
'regPA_SC_IF_FIFO_SIZE_BASE_IDX', 'regPA_SC_LINE_CNTL',
|
|
'regPA_SC_LINE_CNTL_BASE_IDX', 'regPA_SC_LINE_STIPPLE',
|
|
'regPA_SC_LINE_STIPPLE_BASE_IDX', 'regPA_SC_LINE_STIPPLE_STATE',
|
|
'regPA_SC_LINE_STIPPLE_STATE_BASE_IDX', 'regPA_SC_MODE_CNTL_0',
|
|
'regPA_SC_MODE_CNTL_0_BASE_IDX', 'regPA_SC_MODE_CNTL_1',
|
|
'regPA_SC_MODE_CNTL_1_BASE_IDX', 'regPA_SC_NGG_MODE_CNTL',
|
|
'regPA_SC_NGG_MODE_CNTL_BASE_IDX',
|
|
'regPA_SC_P3D_TRAP_SCREEN_COUNT',
|
|
'regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX',
|
|
'regPA_SC_P3D_TRAP_SCREEN_H', 'regPA_SC_P3D_TRAP_SCREEN_HV_EN',
|
|
'regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX',
|
|
'regPA_SC_P3D_TRAP_SCREEN_HV_LOCK',
|
|
'regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX',
|
|
'regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX',
|
|
'regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE',
|
|
'regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX',
|
|
'regPA_SC_P3D_TRAP_SCREEN_V',
|
|
'regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX',
|
|
'regPA_SC_PACKER_WAVE_ID_CNTL',
|
|
'regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX',
|
|
'regPA_SC_PBB_OVERRIDE_FLAG',
|
|
'regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX', 'regPA_SC_PERFCOUNTER0_HI',
|
|
'regPA_SC_PERFCOUNTER0_HI_BASE_IDX', 'regPA_SC_PERFCOUNTER0_LO',
|
|
'regPA_SC_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER0_SELECT', 'regPA_SC_PERFCOUNTER0_SELECT1',
|
|
'regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER1_HI', 'regPA_SC_PERFCOUNTER1_HI_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER1_LO', 'regPA_SC_PERFCOUNTER1_LO_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER1_SELECT',
|
|
'regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER2_HI', 'regPA_SC_PERFCOUNTER2_HI_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER2_LO', 'regPA_SC_PERFCOUNTER2_LO_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER2_SELECT',
|
|
'regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER3_HI', 'regPA_SC_PERFCOUNTER3_HI_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER3_LO', 'regPA_SC_PERFCOUNTER3_LO_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER3_SELECT',
|
|
'regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER4_HI', 'regPA_SC_PERFCOUNTER4_HI_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER4_LO', 'regPA_SC_PERFCOUNTER4_LO_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER4_SELECT',
|
|
'regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER5_HI', 'regPA_SC_PERFCOUNTER5_HI_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER5_LO', 'regPA_SC_PERFCOUNTER5_LO_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER5_SELECT',
|
|
'regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER6_HI', 'regPA_SC_PERFCOUNTER6_HI_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER6_LO', 'regPA_SC_PERFCOUNTER6_LO_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER6_SELECT',
|
|
'regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER7_HI', 'regPA_SC_PERFCOUNTER7_HI_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER7_LO', 'regPA_SC_PERFCOUNTER7_LO_BASE_IDX',
|
|
'regPA_SC_PERFCOUNTER7_SELECT',
|
|
'regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX',
|
|
'regPA_SC_PKR_WAVE_TABLE_CNTL',
|
|
'regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX', 'regPA_SC_RASTER_CONFIG',
|
|
'regPA_SC_RASTER_CONFIG_1', 'regPA_SC_RASTER_CONFIG_1_BASE_IDX',
|
|
'regPA_SC_RASTER_CONFIG_BASE_IDX',
|
|
'regPA_SC_SCREEN_EXTENT_CONTROL',
|
|
'regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX',
|
|
'regPA_SC_SCREEN_EXTENT_MAX_0',
|
|
'regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX',
|
|
'regPA_SC_SCREEN_EXTENT_MAX_1',
|
|
'regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX',
|
|
'regPA_SC_SCREEN_EXTENT_MIN_0',
|
|
'regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX',
|
|
'regPA_SC_SCREEN_EXTENT_MIN_1',
|
|
'regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX',
|
|
'regPA_SC_SCREEN_SCISSOR_BR',
|
|
'regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX',
|
|
'regPA_SC_SCREEN_SCISSOR_TL',
|
|
'regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX', 'regPA_SC_SHADER_CONTROL',
|
|
'regPA_SC_SHADER_CONTROL_BASE_IDX',
|
|
'regPA_SC_TILE_STEERING_CREST_OVERRIDE',
|
|
'regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX',
|
|
'regPA_SC_TILE_STEERING_OVERRIDE',
|
|
'regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX',
|
|
'regPA_SC_TRAP_SCREEN_COUNT',
|
|
'regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX', 'regPA_SC_TRAP_SCREEN_H',
|
|
'regPA_SC_TRAP_SCREEN_HV_EN',
|
|
'regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX',
|
|
'regPA_SC_TRAP_SCREEN_HV_LOCK',
|
|
'regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX',
|
|
'regPA_SC_TRAP_SCREEN_H_BASE_IDX',
|
|
'regPA_SC_TRAP_SCREEN_OCCURRENCE',
|
|
'regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX',
|
|
'regPA_SC_TRAP_SCREEN_V', 'regPA_SC_TRAP_SCREEN_V_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_0_BR',
|
|
'regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_0_TL',
|
|
'regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_10_BR',
|
|
'regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_10_TL',
|
|
'regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_11_BR',
|
|
'regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_11_TL',
|
|
'regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_12_BR',
|
|
'regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_12_TL',
|
|
'regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_13_BR',
|
|
'regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_13_TL',
|
|
'regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_14_BR',
|
|
'regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_14_TL',
|
|
'regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_15_BR',
|
|
'regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_15_TL',
|
|
'regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_1_BR',
|
|
'regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_1_TL',
|
|
'regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_2_BR',
|
|
'regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_2_TL',
|
|
'regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_3_BR',
|
|
'regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_3_TL',
|
|
'regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_4_BR',
|
|
'regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_4_TL',
|
|
'regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_5_BR',
|
|
'regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_5_TL',
|
|
'regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_6_BR',
|
|
'regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_6_TL',
|
|
'regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_7_BR',
|
|
'regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_7_TL',
|
|
'regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_8_BR',
|
|
'regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_8_TL',
|
|
'regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_9_BR',
|
|
'regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX',
|
|
'regPA_SC_VPORT_SCISSOR_9_TL',
|
|
'regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX', 'regPA_SC_VPORT_ZMAX_0',
|
|
'regPA_SC_VPORT_ZMAX_0_BASE_IDX', 'regPA_SC_VPORT_ZMAX_1',
|
|
'regPA_SC_VPORT_ZMAX_10', 'regPA_SC_VPORT_ZMAX_10_BASE_IDX',
|
|
'regPA_SC_VPORT_ZMAX_11', 'regPA_SC_VPORT_ZMAX_11_BASE_IDX',
|
|
'regPA_SC_VPORT_ZMAX_12', 'regPA_SC_VPORT_ZMAX_12_BASE_IDX',
|
|
'regPA_SC_VPORT_ZMAX_13', 'regPA_SC_VPORT_ZMAX_13_BASE_IDX',
|
|
'regPA_SC_VPORT_ZMAX_14', 'regPA_SC_VPORT_ZMAX_14_BASE_IDX',
|
|
'regPA_SC_VPORT_ZMAX_15', 'regPA_SC_VPORT_ZMAX_15_BASE_IDX',
|
|
'regPA_SC_VPORT_ZMAX_1_BASE_IDX', 'regPA_SC_VPORT_ZMAX_2',
|
|
'regPA_SC_VPORT_ZMAX_2_BASE_IDX', 'regPA_SC_VPORT_ZMAX_3',
|
|
'regPA_SC_VPORT_ZMAX_3_BASE_IDX', 'regPA_SC_VPORT_ZMAX_4',
|
|
'regPA_SC_VPORT_ZMAX_4_BASE_IDX', 'regPA_SC_VPORT_ZMAX_5',
|
|
'regPA_SC_VPORT_ZMAX_5_BASE_IDX', 'regPA_SC_VPORT_ZMAX_6',
|
|
'regPA_SC_VPORT_ZMAX_6_BASE_IDX', 'regPA_SC_VPORT_ZMAX_7',
|
|
'regPA_SC_VPORT_ZMAX_7_BASE_IDX', 'regPA_SC_VPORT_ZMAX_8',
|
|
'regPA_SC_VPORT_ZMAX_8_BASE_IDX', 'regPA_SC_VPORT_ZMAX_9',
|
|
'regPA_SC_VPORT_ZMAX_9_BASE_IDX', 'regPA_SC_VPORT_ZMIN_0',
|
|
'regPA_SC_VPORT_ZMIN_0_BASE_IDX', 'regPA_SC_VPORT_ZMIN_1',
|
|
'regPA_SC_VPORT_ZMIN_10', 'regPA_SC_VPORT_ZMIN_10_BASE_IDX',
|
|
'regPA_SC_VPORT_ZMIN_11', 'regPA_SC_VPORT_ZMIN_11_BASE_IDX',
|
|
'regPA_SC_VPORT_ZMIN_12', 'regPA_SC_VPORT_ZMIN_12_BASE_IDX',
|
|
'regPA_SC_VPORT_ZMIN_13', 'regPA_SC_VPORT_ZMIN_13_BASE_IDX',
|
|
'regPA_SC_VPORT_ZMIN_14', 'regPA_SC_VPORT_ZMIN_14_BASE_IDX',
|
|
'regPA_SC_VPORT_ZMIN_15', 'regPA_SC_VPORT_ZMIN_15_BASE_IDX',
|
|
'regPA_SC_VPORT_ZMIN_1_BASE_IDX', 'regPA_SC_VPORT_ZMIN_2',
|
|
'regPA_SC_VPORT_ZMIN_2_BASE_IDX', 'regPA_SC_VPORT_ZMIN_3',
|
|
'regPA_SC_VPORT_ZMIN_3_BASE_IDX', 'regPA_SC_VPORT_ZMIN_4',
|
|
'regPA_SC_VPORT_ZMIN_4_BASE_IDX', 'regPA_SC_VPORT_ZMIN_5',
|
|
'regPA_SC_VPORT_ZMIN_5_BASE_IDX', 'regPA_SC_VPORT_ZMIN_6',
|
|
'regPA_SC_VPORT_ZMIN_6_BASE_IDX', 'regPA_SC_VPORT_ZMIN_7',
|
|
'regPA_SC_VPORT_ZMIN_7_BASE_IDX', 'regPA_SC_VPORT_ZMIN_8',
|
|
'regPA_SC_VPORT_ZMIN_8_BASE_IDX', 'regPA_SC_VPORT_ZMIN_9',
|
|
'regPA_SC_VPORT_ZMIN_9_BASE_IDX', 'regPA_SC_VRS_OVERRIDE_CNTL',
|
|
'regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX', 'regPA_SC_VRS_RATE_BASE',
|
|
'regPA_SC_VRS_RATE_BASE_BASE_IDX', 'regPA_SC_VRS_RATE_BASE_EXT',
|
|
'regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX',
|
|
'regPA_SC_VRS_RATE_CACHE_CNTL',
|
|
'regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX',
|
|
'regPA_SC_VRS_RATE_FEEDBACK_BASE',
|
|
'regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX',
|
|
'regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT',
|
|
'regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX',
|
|
'regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY',
|
|
'regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX',
|
|
'regPA_SC_VRS_RATE_SIZE_XY', 'regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX',
|
|
'regPA_SC_VRS_SURFACE_CNTL', 'regPA_SC_VRS_SURFACE_CNTL_1',
|
|
'regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX',
|
|
'regPA_SC_VRS_SURFACE_CNTL_BASE_IDX', 'regPA_SC_WINDOW_OFFSET',
|
|
'regPA_SC_WINDOW_OFFSET_BASE_IDX', 'regPA_SC_WINDOW_SCISSOR_BR',
|
|
'regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX',
|
|
'regPA_SC_WINDOW_SCISSOR_TL',
|
|
'regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX', 'regPA_STATE_STEREO_X',
|
|
'regPA_STATE_STEREO_X_BASE_IDX', 'regPA_STEREO_CNTL',
|
|
'regPA_STEREO_CNTL_BASE_IDX', 'regPA_SU_CNTL_STATUS',
|
|
'regPA_SU_CNTL_STATUS_BASE_IDX',
|
|
'regPA_SU_HARDWARE_SCREEN_OFFSET',
|
|
'regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX', 'regPA_SU_LINE_CNTL',
|
|
'regPA_SU_LINE_CNTL_BASE_IDX', 'regPA_SU_LINE_STIPPLE_CNTL',
|
|
'regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX',
|
|
'regPA_SU_LINE_STIPPLE_SCALE',
|
|
'regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX',
|
|
'regPA_SU_LINE_STIPPLE_VALUE',
|
|
'regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX',
|
|
'regPA_SU_OVER_RASTERIZATION_CNTL',
|
|
'regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER0_HI', 'regPA_SU_PERFCOUNTER0_HI_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER0_LO', 'regPA_SU_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER0_SELECT', 'regPA_SU_PERFCOUNTER0_SELECT1',
|
|
'regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER1_HI', 'regPA_SU_PERFCOUNTER1_HI_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER1_LO', 'regPA_SU_PERFCOUNTER1_LO_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER1_SELECT', 'regPA_SU_PERFCOUNTER1_SELECT1',
|
|
'regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER2_HI', 'regPA_SU_PERFCOUNTER2_HI_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER2_LO', 'regPA_SU_PERFCOUNTER2_LO_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER2_SELECT', 'regPA_SU_PERFCOUNTER2_SELECT1',
|
|
'regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER3_HI', 'regPA_SU_PERFCOUNTER3_HI_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER3_LO', 'regPA_SU_PERFCOUNTER3_LO_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER3_SELECT', 'regPA_SU_PERFCOUNTER3_SELECT1',
|
|
'regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX',
|
|
'regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX', 'regPA_SU_POINT_MINMAX',
|
|
'regPA_SU_POINT_MINMAX_BASE_IDX', 'regPA_SU_POINT_SIZE',
|
|
'regPA_SU_POINT_SIZE_BASE_IDX',
|
|
'regPA_SU_POLY_OFFSET_BACK_OFFSET',
|
|
'regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX',
|
|
'regPA_SU_POLY_OFFSET_BACK_SCALE',
|
|
'regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX',
|
|
'regPA_SU_POLY_OFFSET_CLAMP',
|
|
'regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX',
|
|
'regPA_SU_POLY_OFFSET_DB_FMT_CNTL',
|
|
'regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX',
|
|
'regPA_SU_POLY_OFFSET_FRONT_OFFSET',
|
|
'regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX',
|
|
'regPA_SU_POLY_OFFSET_FRONT_SCALE',
|
|
'regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX',
|
|
'regPA_SU_PRIM_FILTER_CNTL', 'regPA_SU_PRIM_FILTER_CNTL_BASE_IDX',
|
|
'regPA_SU_SC_MODE_CNTL', 'regPA_SU_SC_MODE_CNTL_BASE_IDX',
|
|
'regPA_SU_SMALL_PRIM_FILTER_CNTL',
|
|
'regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX', 'regPA_SU_VTX_CNTL',
|
|
'regPA_SU_VTX_CNTL_BASE_IDX', 'regPCC_PERF_COUNTER',
|
|
'regPCC_PERF_COUNTER_BASE_IDX', 'regPCC_PWRBRK_HYSTERESIS_CTRL',
|
|
'regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX',
|
|
'regPCC_STALL_PATTERN_1_2', 'regPCC_STALL_PATTERN_1_2_BASE_IDX',
|
|
'regPCC_STALL_PATTERN_3_4', 'regPCC_STALL_PATTERN_3_4_BASE_IDX',
|
|
'regPCC_STALL_PATTERN_5_6', 'regPCC_STALL_PATTERN_5_6_BASE_IDX',
|
|
'regPCC_STALL_PATTERN_7', 'regPCC_STALL_PATTERN_7_BASE_IDX',
|
|
'regPCC_STALL_PATTERN_CTRL', 'regPCC_STALL_PATTERN_CTRL_BASE_IDX',
|
|
'regPC_PERFCOUNTER0_HI', 'regPC_PERFCOUNTER0_HI_BASE_IDX',
|
|
'regPC_PERFCOUNTER0_LO', 'regPC_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regPC_PERFCOUNTER0_SELECT', 'regPC_PERFCOUNTER0_SELECT1',
|
|
'regPC_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regPC_PERFCOUNTER0_SELECT_BASE_IDX', 'regPC_PERFCOUNTER1_HI',
|
|
'regPC_PERFCOUNTER1_HI_BASE_IDX', 'regPC_PERFCOUNTER1_LO',
|
|
'regPC_PERFCOUNTER1_LO_BASE_IDX', 'regPC_PERFCOUNTER1_SELECT',
|
|
'regPC_PERFCOUNTER1_SELECT1',
|
|
'regPC_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regPC_PERFCOUNTER1_SELECT_BASE_IDX', 'regPC_PERFCOUNTER2_HI',
|
|
'regPC_PERFCOUNTER2_HI_BASE_IDX', 'regPC_PERFCOUNTER2_LO',
|
|
'regPC_PERFCOUNTER2_LO_BASE_IDX', 'regPC_PERFCOUNTER2_SELECT',
|
|
'regPC_PERFCOUNTER2_SELECT1',
|
|
'regPC_PERFCOUNTER2_SELECT1_BASE_IDX',
|
|
'regPC_PERFCOUNTER2_SELECT_BASE_IDX', 'regPC_PERFCOUNTER3_HI',
|
|
'regPC_PERFCOUNTER3_HI_BASE_IDX', 'regPC_PERFCOUNTER3_LO',
|
|
'regPC_PERFCOUNTER3_LO_BASE_IDX', 'regPC_PERFCOUNTER3_SELECT',
|
|
'regPC_PERFCOUNTER3_SELECT1',
|
|
'regPC_PERFCOUNTER3_SELECT1_BASE_IDX',
|
|
'regPC_PERFCOUNTER3_SELECT_BASE_IDX', 'regPMM_CNTL',
|
|
'regPMM_CNTL2', 'regPMM_CNTL2_BASE_IDX', 'regPMM_CNTL_BASE_IDX',
|
|
'regPMM_STATUS', 'regPMM_STATUS_BASE_IDX',
|
|
'regPWRBRK_PERF_COUNTER', 'regPWRBRK_PERF_COUNTER_BASE_IDX',
|
|
'regPWRBRK_STALL_PATTERN_1_2',
|
|
'regPWRBRK_STALL_PATTERN_1_2_BASE_IDX',
|
|
'regPWRBRK_STALL_PATTERN_3_4',
|
|
'regPWRBRK_STALL_PATTERN_3_4_BASE_IDX',
|
|
'regPWRBRK_STALL_PATTERN_5_6',
|
|
'regPWRBRK_STALL_PATTERN_5_6_BASE_IDX',
|
|
'regPWRBRK_STALL_PATTERN_7', 'regPWRBRK_STALL_PATTERN_7_BASE_IDX',
|
|
'regPWRBRK_STALL_PATTERN_CTRL',
|
|
'regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX', 'regRLC_AUTO_PG_CTRL',
|
|
'regRLC_AUTO_PG_CTRL_BASE_IDX', 'regRLC_BUSY_CLK_CNTL',
|
|
'regRLC_BUSY_CLK_CNTL_BASE_IDX', 'regRLC_CAC_MASK_CNTL',
|
|
'regRLC_CAC_MASK_CNTL_BASE_IDX', 'regRLC_CAPTURE_GPU_CLOCK_COUNT',
|
|
'regRLC_CAPTURE_GPU_CLOCK_COUNT_1',
|
|
'regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX',
|
|
'regRLC_CAPTURE_GPU_CLOCK_COUNT_2',
|
|
'regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX',
|
|
'regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX',
|
|
'regRLC_CGCG_CGLS_CTRL', 'regRLC_CGCG_CGLS_CTRL_3D',
|
|
'regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX',
|
|
'regRLC_CGCG_CGLS_CTRL_BASE_IDX', 'regRLC_CGCG_RAMP_CTRL',
|
|
'regRLC_CGCG_RAMP_CTRL_3D', 'regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX',
|
|
'regRLC_CGCG_RAMP_CTRL_BASE_IDX', 'regRLC_CGTT_MGCG_OVERRIDE',
|
|
'regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX', 'regRLC_CLK_CNTL',
|
|
'regRLC_CLK_CNTL_BASE_IDX', 'regRLC_CLK_COUNT_CTRL',
|
|
'regRLC_CLK_COUNT_CTRL_BASE_IDX', 'regRLC_CLK_COUNT_GFXCLK_LSB',
|
|
'regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX',
|
|
'regRLC_CLK_COUNT_GFXCLK_MSB',
|
|
'regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX',
|
|
'regRLC_CLK_COUNT_REFCLK_LSB',
|
|
'regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX',
|
|
'regRLC_CLK_COUNT_REFCLK_MSB',
|
|
'regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX', 'regRLC_CLK_COUNT_STAT',
|
|
'regRLC_CLK_COUNT_STAT_BASE_IDX',
|
|
'regRLC_CLK_RESIDENCY_CNTR_CTRL',
|
|
'regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX',
|
|
'regRLC_CLK_RESIDENCY_EVENT_CNTR',
|
|
'regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX',
|
|
'regRLC_CLK_RESIDENCY_REF_CNTR',
|
|
'regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_CNTL',
|
|
'regRLC_CNTL_BASE_IDX', 'regRLC_CP_EOF_INT',
|
|
'regRLC_CP_EOF_INT_BASE_IDX', 'regRLC_CP_EOF_INT_CNT',
|
|
'regRLC_CP_EOF_INT_CNT_BASE_IDX', 'regRLC_CP_SCHEDULERS',
|
|
'regRLC_CP_SCHEDULERS_BASE_IDX', 'regRLC_CP_STAT_INVAL_CTRL',
|
|
'regRLC_CP_STAT_INVAL_CTRL_BASE_IDX', 'regRLC_CP_STAT_INVAL_STAT',
|
|
'regRLC_CP_STAT_INVAL_STAT_BASE_IDX', 'regRLC_CSIB_ADDR_HI',
|
|
'regRLC_CSIB_ADDR_HI_BASE_IDX', 'regRLC_CSIB_ADDR_LO',
|
|
'regRLC_CSIB_ADDR_LO_BASE_IDX', 'regRLC_CSIB_LENGTH',
|
|
'regRLC_CSIB_LENGTH_BASE_IDX', 'regRLC_DS_RESIDENCY_CNTR_CTRL',
|
|
'regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX',
|
|
'regRLC_DS_RESIDENCY_EVENT_CNTR',
|
|
'regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX',
|
|
'regRLC_DS_RESIDENCY_REF_CNTR',
|
|
'regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_DYN_PG_REQUEST',
|
|
'regRLC_DYN_PG_REQUEST_BASE_IDX', 'regRLC_DYN_PG_STATUS',
|
|
'regRLC_DYN_PG_STATUS_BASE_IDX', 'regRLC_F32_UCODE_VERSION',
|
|
'regRLC_F32_UCODE_VERSION_BASE_IDX', 'regRLC_FWL_FIRST_VIOL_ADDR',
|
|
'regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX',
|
|
'regRLC_GENERAL_RESIDENCY_CNTR_CTRL',
|
|
'regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX',
|
|
'regRLC_GENERAL_RESIDENCY_EVENT_CNTR',
|
|
'regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX',
|
|
'regRLC_GENERAL_RESIDENCY_REF_CNTR',
|
|
'regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX',
|
|
'regRLC_GFX_IH_ARBITER_STAT',
|
|
'regRLC_GFX_IH_ARBITER_STAT_BASE_IDX',
|
|
'regRLC_GFX_IH_CLIENT_CTRL', 'regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX',
|
|
'regRLC_GFX_IH_CLIENT_OTHER_STAT',
|
|
'regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX',
|
|
'regRLC_GFX_IH_CLIENT_SDMA_STAT',
|
|
'regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX',
|
|
'regRLC_GFX_IH_CLIENT_SE_STAT_H',
|
|
'regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX',
|
|
'regRLC_GFX_IH_CLIENT_SE_STAT_L',
|
|
'regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX', 'regRLC_GFX_IMU_CMD',
|
|
'regRLC_GFX_IMU_CMD_BASE_IDX', 'regRLC_GFX_IMU_DATA_0',
|
|
'regRLC_GFX_IMU_DATA_0_BASE_IDX', 'regRLC_GPM_CP_DMA_COMPLETE_T0',
|
|
'regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX',
|
|
'regRLC_GPM_CP_DMA_COMPLETE_T1',
|
|
'regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX', 'regRLC_GPM_GENERAL_0',
|
|
'regRLC_GPM_GENERAL_0_BASE_IDX', 'regRLC_GPM_GENERAL_1',
|
|
'regRLC_GPM_GENERAL_10', 'regRLC_GPM_GENERAL_10_BASE_IDX',
|
|
'regRLC_GPM_GENERAL_11', 'regRLC_GPM_GENERAL_11_BASE_IDX',
|
|
'regRLC_GPM_GENERAL_12', 'regRLC_GPM_GENERAL_12_BASE_IDX',
|
|
'regRLC_GPM_GENERAL_13', 'regRLC_GPM_GENERAL_13_BASE_IDX',
|
|
'regRLC_GPM_GENERAL_14', 'regRLC_GPM_GENERAL_14_BASE_IDX',
|
|
'regRLC_GPM_GENERAL_15', 'regRLC_GPM_GENERAL_15_BASE_IDX',
|
|
'regRLC_GPM_GENERAL_16', 'regRLC_GPM_GENERAL_16_BASE_IDX',
|
|
'regRLC_GPM_GENERAL_1_BASE_IDX', 'regRLC_GPM_GENERAL_2',
|
|
'regRLC_GPM_GENERAL_2_BASE_IDX', 'regRLC_GPM_GENERAL_3',
|
|
'regRLC_GPM_GENERAL_3_BASE_IDX', 'regRLC_GPM_GENERAL_4',
|
|
'regRLC_GPM_GENERAL_4_BASE_IDX', 'regRLC_GPM_GENERAL_5',
|
|
'regRLC_GPM_GENERAL_5_BASE_IDX', 'regRLC_GPM_GENERAL_6',
|
|
'regRLC_GPM_GENERAL_6_BASE_IDX', 'regRLC_GPM_GENERAL_7',
|
|
'regRLC_GPM_GENERAL_7_BASE_IDX', 'regRLC_GPM_GENERAL_8',
|
|
'regRLC_GPM_GENERAL_8_BASE_IDX', 'regRLC_GPM_GENERAL_9',
|
|
'regRLC_GPM_GENERAL_9_BASE_IDX', 'regRLC_GPM_INT_DISABLE_TH0',
|
|
'regRLC_GPM_INT_DISABLE_TH0_BASE_IDX', 'regRLC_GPM_INT_FORCE_TH0',
|
|
'regRLC_GPM_INT_FORCE_TH0_BASE_IDX', 'regRLC_GPM_INT_STAT_TH0',
|
|
'regRLC_GPM_INT_STAT_TH0_BASE_IDX', 'regRLC_GPM_IRAM_ADDR',
|
|
'regRLC_GPM_IRAM_ADDR_BASE_IDX', 'regRLC_GPM_IRAM_DATA',
|
|
'regRLC_GPM_IRAM_DATA_BASE_IDX', 'regRLC_GPM_LEGACY_INT_CLEAR',
|
|
'regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX',
|
|
'regRLC_GPM_LEGACY_INT_DISABLE',
|
|
'regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX',
|
|
'regRLC_GPM_LEGACY_INT_STAT',
|
|
'regRLC_GPM_LEGACY_INT_STAT_BASE_IDX', 'regRLC_GPM_PERF_COUNT_0',
|
|
'regRLC_GPM_PERF_COUNT_0_BASE_IDX', 'regRLC_GPM_PERF_COUNT_1',
|
|
'regRLC_GPM_PERF_COUNT_1_BASE_IDX', 'regRLC_GPM_SCRATCH_ADDR',
|
|
'regRLC_GPM_SCRATCH_ADDR_BASE_IDX', 'regRLC_GPM_SCRATCH_DATA',
|
|
'regRLC_GPM_SCRATCH_DATA_BASE_IDX', 'regRLC_GPM_STAT',
|
|
'regRLC_GPM_STAT_BASE_IDX', 'regRLC_GPM_THREAD_ENABLE',
|
|
'regRLC_GPM_THREAD_ENABLE_BASE_IDX',
|
|
'regRLC_GPM_THREAD_INVALIDATE_CACHE',
|
|
'regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX',
|
|
'regRLC_GPM_THREAD_PRIORITY',
|
|
'regRLC_GPM_THREAD_PRIORITY_BASE_IDX', 'regRLC_GPM_THREAD_RESET',
|
|
'regRLC_GPM_THREAD_RESET_BASE_IDX', 'regRLC_GPM_TIMER_CTRL',
|
|
'regRLC_GPM_TIMER_CTRL_BASE_IDX', 'regRLC_GPM_TIMER_INT_0',
|
|
'regRLC_GPM_TIMER_INT_0_BASE_IDX', 'regRLC_GPM_TIMER_INT_1',
|
|
'regRLC_GPM_TIMER_INT_1_BASE_IDX', 'regRLC_GPM_TIMER_INT_2',
|
|
'regRLC_GPM_TIMER_INT_2_BASE_IDX', 'regRLC_GPM_TIMER_INT_3',
|
|
'regRLC_GPM_TIMER_INT_3_BASE_IDX', 'regRLC_GPM_TIMER_INT_4',
|
|
'regRLC_GPM_TIMER_INT_4_BASE_IDX', 'regRLC_GPM_TIMER_STAT',
|
|
'regRLC_GPM_TIMER_STAT_BASE_IDX', 'regRLC_GPM_UCODE_ADDR',
|
|
'regRLC_GPM_UCODE_ADDR_BASE_IDX', 'regRLC_GPM_UCODE_DATA',
|
|
'regRLC_GPM_UCODE_DATA_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_0',
|
|
'regRLC_GPM_UTCL1_CNTL_0_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_1',
|
|
'regRLC_GPM_UTCL1_CNTL_1_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_2',
|
|
'regRLC_GPM_UTCL1_CNTL_2_BASE_IDX',
|
|
'regRLC_GPM_UTCL1_TH0_ERROR_1',
|
|
'regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX',
|
|
'regRLC_GPM_UTCL1_TH0_ERROR_2',
|
|
'regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX',
|
|
'regRLC_GPM_UTCL1_TH1_ERROR_1',
|
|
'regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX',
|
|
'regRLC_GPM_UTCL1_TH1_ERROR_2',
|
|
'regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX',
|
|
'regRLC_GPM_UTCL1_TH2_ERROR_1',
|
|
'regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX',
|
|
'regRLC_GPM_UTCL1_TH2_ERROR_2',
|
|
'regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX', 'regRLC_GPR_REG1',
|
|
'regRLC_GPR_REG1_BASE_IDX', 'regRLC_GPR_REG2',
|
|
'regRLC_GPR_REG2_BASE_IDX', 'regRLC_GPU_CLOCK_32',
|
|
'regRLC_GPU_CLOCK_32_BASE_IDX', 'regRLC_GPU_CLOCK_32_RES_SEL',
|
|
'regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX',
|
|
'regRLC_GPU_CLOCK_COUNT_LSB', 'regRLC_GPU_CLOCK_COUNT_LSB_1',
|
|
'regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX',
|
|
'regRLC_GPU_CLOCK_COUNT_LSB_2',
|
|
'regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX',
|
|
'regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX',
|
|
'regRLC_GPU_CLOCK_COUNT_MSB', 'regRLC_GPU_CLOCK_COUNT_MSB_1',
|
|
'regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX',
|
|
'regRLC_GPU_CLOCK_COUNT_MSB_2',
|
|
'regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX',
|
|
'regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX',
|
|
'regRLC_GPU_CLOCK_COUNT_SPM_LSB',
|
|
'regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX',
|
|
'regRLC_GPU_CLOCK_COUNT_SPM_MSB',
|
|
'regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX',
|
|
'regRLC_GPU_IOV_CFG_REG1', 'regRLC_GPU_IOV_CFG_REG1_BASE_IDX',
|
|
'regRLC_GPU_IOV_CFG_REG2', 'regRLC_GPU_IOV_CFG_REG2_BASE_IDX',
|
|
'regRLC_GPU_IOV_CFG_REG6', 'regRLC_GPU_IOV_CFG_REG6_BASE_IDX',
|
|
'regRLC_GPU_IOV_CFG_REG8', 'regRLC_GPU_IOV_CFG_REG8_BASE_IDX',
|
|
'regRLC_GPU_IOV_F32_CNTL', 'regRLC_GPU_IOV_F32_CNTL_BASE_IDX',
|
|
'regRLC_GPU_IOV_F32_INVALIDATE_CACHE',
|
|
'regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX',
|
|
'regRLC_GPU_IOV_F32_RESET', 'regRLC_GPU_IOV_F32_RESET_BASE_IDX',
|
|
'regRLC_GPU_IOV_INT_DISABLE',
|
|
'regRLC_GPU_IOV_INT_DISABLE_BASE_IDX', 'regRLC_GPU_IOV_INT_FORCE',
|
|
'regRLC_GPU_IOV_INT_FORCE_BASE_IDX', 'regRLC_GPU_IOV_INT_STAT',
|
|
'regRLC_GPU_IOV_INT_STAT_BASE_IDX',
|
|
'regRLC_GPU_IOV_PERF_CNT_CNTL',
|
|
'regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX',
|
|
'regRLC_GPU_IOV_PERF_CNT_RD_ADDR',
|
|
'regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX',
|
|
'regRLC_GPU_IOV_PERF_CNT_RD_DATA',
|
|
'regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX',
|
|
'regRLC_GPU_IOV_PERF_CNT_WR_ADDR',
|
|
'regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX',
|
|
'regRLC_GPU_IOV_PERF_CNT_WR_DATA',
|
|
'regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX',
|
|
'regRLC_GPU_IOV_RLC_RESPONSE',
|
|
'regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX', 'regRLC_GPU_IOV_SCH_0',
|
|
'regRLC_GPU_IOV_SCH_0_BASE_IDX', 'regRLC_GPU_IOV_SCH_1',
|
|
'regRLC_GPU_IOV_SCH_1_BASE_IDX', 'regRLC_GPU_IOV_SCH_2',
|
|
'regRLC_GPU_IOV_SCH_2_BASE_IDX', 'regRLC_GPU_IOV_SCH_3',
|
|
'regRLC_GPU_IOV_SCH_3_BASE_IDX', 'regRLC_GPU_IOV_SCH_BLOCK',
|
|
'regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX',
|
|
'regRLC_GPU_IOV_SCRATCH_ADDR',
|
|
'regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX',
|
|
'regRLC_GPU_IOV_SCRATCH_DATA',
|
|
'regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA0_BUSY_STATUS',
|
|
'regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA0_STATUS',
|
|
'regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA1_BUSY_STATUS',
|
|
'regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA1_STATUS',
|
|
'regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA2_BUSY_STATUS',
|
|
'regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA2_STATUS',
|
|
'regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA3_BUSY_STATUS',
|
|
'regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA3_STATUS',
|
|
'regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA4_BUSY_STATUS',
|
|
'regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA4_STATUS',
|
|
'regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA5_BUSY_STATUS',
|
|
'regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA5_STATUS',
|
|
'regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA6_BUSY_STATUS',
|
|
'regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA6_STATUS',
|
|
'regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA7_BUSY_STATUS',
|
|
'regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SDMA7_STATUS',
|
|
'regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_SMU_RESPONSE',
|
|
'regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX',
|
|
'regRLC_GPU_IOV_UCODE_ADDR', 'regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX',
|
|
'regRLC_GPU_IOV_UCODE_DATA', 'regRLC_GPU_IOV_UCODE_DATA_BASE_IDX',
|
|
'regRLC_GPU_IOV_VF_DOORBELL_STATUS',
|
|
'regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX',
|
|
'regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR',
|
|
'regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX',
|
|
'regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET',
|
|
'regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX',
|
|
'regRLC_GPU_IOV_VF_ENABLE', 'regRLC_GPU_IOV_VF_ENABLE_BASE_IDX',
|
|
'regRLC_GPU_IOV_VF_MASK', 'regRLC_GPU_IOV_VF_MASK_BASE_IDX',
|
|
'regRLC_GPU_IOV_VM_BUSY_STATUS',
|
|
'regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX', 'regRLC_GTS_OFFSET_LSB',
|
|
'regRLC_GTS_OFFSET_LSB_BASE_IDX', 'regRLC_GTS_OFFSET_MSB',
|
|
'regRLC_GTS_OFFSET_MSB_BASE_IDX', 'regRLC_HYP_RLCG_UCODE_CHKSUM',
|
|
'regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX',
|
|
'regRLC_HYP_RLCP_UCODE_CHKSUM',
|
|
'regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX',
|
|
'regRLC_HYP_RLCV_UCODE_CHKSUM',
|
|
'regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX', 'regRLC_HYP_SEMAPHORE_0',
|
|
'regRLC_HYP_SEMAPHORE_0_BASE_IDX', 'regRLC_HYP_SEMAPHORE_1',
|
|
'regRLC_HYP_SEMAPHORE_1_BASE_IDX', 'regRLC_HYP_SEMAPHORE_2',
|
|
'regRLC_HYP_SEMAPHORE_2_BASE_IDX', 'regRLC_HYP_SEMAPHORE_3',
|
|
'regRLC_HYP_SEMAPHORE_3_BASE_IDX', 'regRLC_IH_COOKIE',
|
|
'regRLC_IH_COOKIE_BASE_IDX', 'regRLC_IH_COOKIE_CNTL',
|
|
'regRLC_IH_COOKIE_CNTL_BASE_IDX', 'regRLC_IMU_BOOTLOAD_ADDR_HI',
|
|
'regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX',
|
|
'regRLC_IMU_BOOTLOAD_ADDR_LO',
|
|
'regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX',
|
|
'regRLC_IMU_BOOTLOAD_SIZE', 'regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX',
|
|
'regRLC_IMU_MISC', 'regRLC_IMU_MISC_BASE_IDX',
|
|
'regRLC_IMU_RESET_VECTOR', 'regRLC_IMU_RESET_VECTOR_BASE_IDX',
|
|
'regRLC_INT_STAT', 'regRLC_INT_STAT_BASE_IDX',
|
|
'regRLC_JUMP_TABLE_RESTORE', 'regRLC_JUMP_TABLE_RESTORE_BASE_IDX',
|
|
'regRLC_LX6_CNTL', 'regRLC_LX6_CNTL_BASE_IDX',
|
|
'regRLC_LX6_DRAM_ADDR', 'regRLC_LX6_DRAM_ADDR_BASE_IDX',
|
|
'regRLC_LX6_DRAM_DATA', 'regRLC_LX6_DRAM_DATA_BASE_IDX',
|
|
'regRLC_LX6_IRAM_ADDR', 'regRLC_LX6_IRAM_ADDR_BASE_IDX',
|
|
'regRLC_LX6_IRAM_DATA', 'regRLC_LX6_IRAM_DATA_BASE_IDX',
|
|
'regRLC_MAX_PG_WGP', 'regRLC_MAX_PG_WGP_BASE_IDX',
|
|
'regRLC_MEM_SLP_CNTL', 'regRLC_MEM_SLP_CNTL_BASE_IDX',
|
|
'regRLC_MGCG_CTRL', 'regRLC_MGCG_CTRL_BASE_IDX',
|
|
'regRLC_PACE_INT_CLEAR', 'regRLC_PACE_INT_CLEAR_BASE_IDX',
|
|
'regRLC_PACE_INT_DISABLE', 'regRLC_PACE_INT_DISABLE_BASE_IDX',
|
|
'regRLC_PACE_INT_FORCE', 'regRLC_PACE_INT_FORCE_BASE_IDX',
|
|
'regRLC_PACE_INT_STAT', 'regRLC_PACE_INT_STAT_BASE_IDX',
|
|
'regRLC_PACE_SCRATCH_ADDR', 'regRLC_PACE_SCRATCH_ADDR_BASE_IDX',
|
|
'regRLC_PACE_SCRATCH_DATA', 'regRLC_PACE_SCRATCH_DATA_BASE_IDX',
|
|
'regRLC_PACE_SPARE_INT', 'regRLC_PACE_SPARE_INT_1',
|
|
'regRLC_PACE_SPARE_INT_1_BASE_IDX',
|
|
'regRLC_PACE_SPARE_INT_BASE_IDX', 'regRLC_PACE_TIMER_CTRL',
|
|
'regRLC_PACE_TIMER_CTRL_BASE_IDX', 'regRLC_PACE_TIMER_INT_0',
|
|
'regRLC_PACE_TIMER_INT_0_BASE_IDX', 'regRLC_PACE_TIMER_INT_1',
|
|
'regRLC_PACE_TIMER_INT_1_BASE_IDX', 'regRLC_PACE_TIMER_STAT',
|
|
'regRLC_PACE_TIMER_STAT_BASE_IDX', 'regRLC_PACE_UCODE_ADDR',
|
|
'regRLC_PACE_UCODE_ADDR_BASE_IDX', 'regRLC_PACE_UCODE_DATA',
|
|
'regRLC_PACE_UCODE_DATA_BASE_IDX',
|
|
'regRLC_PCC_RESIDENCY_CNTR_CTRL',
|
|
'regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX',
|
|
'regRLC_PCC_RESIDENCY_EVENT_CNTR',
|
|
'regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX',
|
|
'regRLC_PCC_RESIDENCY_REF_CNTR',
|
|
'regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX',
|
|
'regRLC_PERFCOUNTER0_HI', 'regRLC_PERFCOUNTER0_HI_BASE_IDX',
|
|
'regRLC_PERFCOUNTER0_LO', 'regRLC_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regRLC_PERFCOUNTER0_SELECT',
|
|
'regRLC_PERFCOUNTER0_SELECT_BASE_IDX', 'regRLC_PERFCOUNTER1_HI',
|
|
'regRLC_PERFCOUNTER1_HI_BASE_IDX', 'regRLC_PERFCOUNTER1_LO',
|
|
'regRLC_PERFCOUNTER1_LO_BASE_IDX', 'regRLC_PERFCOUNTER1_SELECT',
|
|
'regRLC_PERFCOUNTER1_SELECT_BASE_IDX', 'regRLC_PERFMON_CNTL',
|
|
'regRLC_PERFMON_CNTL_BASE_IDX', 'regRLC_PG_ALWAYS_ON_WGP_MASK',
|
|
'regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX', 'regRLC_PG_CNTL',
|
|
'regRLC_PG_CNTL_BASE_IDX', 'regRLC_PG_DELAY', 'regRLC_PG_DELAY_2',
|
|
'regRLC_PG_DELAY_2_BASE_IDX', 'regRLC_PG_DELAY_3',
|
|
'regRLC_PG_DELAY_3_BASE_IDX', 'regRLC_PG_DELAY_BASE_IDX',
|
|
'regRLC_POWER_RESIDENCY_CNTR_CTRL',
|
|
'regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX',
|
|
'regRLC_POWER_RESIDENCY_EVENT_CNTR',
|
|
'regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX',
|
|
'regRLC_POWER_RESIDENCY_REF_CNTR',
|
|
'regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_R2I_CNTL_0',
|
|
'regRLC_R2I_CNTL_0_BASE_IDX', 'regRLC_R2I_CNTL_1',
|
|
'regRLC_R2I_CNTL_1_BASE_IDX', 'regRLC_R2I_CNTL_2',
|
|
'regRLC_R2I_CNTL_2_BASE_IDX', 'regRLC_R2I_CNTL_3',
|
|
'regRLC_R2I_CNTL_3_BASE_IDX', 'regRLC_REFCLOCK_TIMESTAMP_LSB',
|
|
'regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX',
|
|
'regRLC_REFCLOCK_TIMESTAMP_MSB',
|
|
'regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX',
|
|
'regRLC_RLCG_DOORBELL_0_DATA_HI',
|
|
'regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX',
|
|
'regRLC_RLCG_DOORBELL_0_DATA_LO',
|
|
'regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX',
|
|
'regRLC_RLCG_DOORBELL_1_DATA_HI',
|
|
'regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX',
|
|
'regRLC_RLCG_DOORBELL_1_DATA_LO',
|
|
'regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX',
|
|
'regRLC_RLCG_DOORBELL_2_DATA_HI',
|
|
'regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX',
|
|
'regRLC_RLCG_DOORBELL_2_DATA_LO',
|
|
'regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX',
|
|
'regRLC_RLCG_DOORBELL_3_DATA_HI',
|
|
'regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX',
|
|
'regRLC_RLCG_DOORBELL_3_DATA_LO',
|
|
'regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX',
|
|
'regRLC_RLCG_DOORBELL_CNTL', 'regRLC_RLCG_DOORBELL_CNTL_BASE_IDX',
|
|
'regRLC_RLCG_DOORBELL_RANGE',
|
|
'regRLC_RLCG_DOORBELL_RANGE_BASE_IDX',
|
|
'regRLC_RLCG_DOORBELL_STAT', 'regRLC_RLCG_DOORBELL_STAT_BASE_IDX',
|
|
'regRLC_RLCP_DOORBELL_0_DATA_HI',
|
|
'regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX',
|
|
'regRLC_RLCP_DOORBELL_0_DATA_LO',
|
|
'regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX',
|
|
'regRLC_RLCP_DOORBELL_1_DATA_HI',
|
|
'regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX',
|
|
'regRLC_RLCP_DOORBELL_1_DATA_LO',
|
|
'regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX',
|
|
'regRLC_RLCP_DOORBELL_2_DATA_HI',
|
|
'regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX',
|
|
'regRLC_RLCP_DOORBELL_2_DATA_LO',
|
|
'regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX',
|
|
'regRLC_RLCP_DOORBELL_3_DATA_HI',
|
|
'regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX',
|
|
'regRLC_RLCP_DOORBELL_3_DATA_LO',
|
|
'regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX',
|
|
'regRLC_RLCP_DOORBELL_CNTL', 'regRLC_RLCP_DOORBELL_CNTL_BASE_IDX',
|
|
'regRLC_RLCP_DOORBELL_RANGE',
|
|
'regRLC_RLCP_DOORBELL_RANGE_BASE_IDX',
|
|
'regRLC_RLCP_DOORBELL_STAT', 'regRLC_RLCP_DOORBELL_STAT_BASE_IDX',
|
|
'regRLC_RLCP_IRAM_ADDR', 'regRLC_RLCP_IRAM_ADDR_BASE_IDX',
|
|
'regRLC_RLCP_IRAM_DATA', 'regRLC_RLCP_IRAM_DATA_BASE_IDX',
|
|
'regRLC_RLCS_ABORTED_PD_SEQUENCE',
|
|
'regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX',
|
|
'regRLC_RLCS_AUXILIARY_REG_1',
|
|
'regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX',
|
|
'regRLC_RLCS_AUXILIARY_REG_2',
|
|
'regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX',
|
|
'regRLC_RLCS_AUXILIARY_REG_3',
|
|
'regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX',
|
|
'regRLC_RLCS_AUXILIARY_REG_4',
|
|
'regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX',
|
|
'regRLC_RLCS_BOOTLOAD_ID_STATUS1',
|
|
'regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX',
|
|
'regRLC_RLCS_BOOTLOAD_ID_STATUS2',
|
|
'regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX',
|
|
'regRLC_RLCS_BOOTLOAD_STATUS',
|
|
'regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX',
|
|
'regRLC_RLCS_CGCG_REQUEST', 'regRLC_RLCS_CGCG_REQUEST_BASE_IDX',
|
|
'regRLC_RLCS_CGCG_STATUS', 'regRLC_RLCS_CGCG_STATUS_BASE_IDX',
|
|
'regRLC_RLCS_CMP_IDLE_CNTL', 'regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_CP_DMA_SRCID_OVER',
|
|
'regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX',
|
|
'regRLC_RLCS_CP_INT_CTRL_1', 'regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX',
|
|
'regRLC_RLCS_CP_INT_CTRL_2', 'regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX',
|
|
'regRLC_RLCS_CP_INT_INFO_1', 'regRLC_RLCS_CP_INT_INFO_1_BASE_IDX',
|
|
'regRLC_RLCS_CP_INT_INFO_2', 'regRLC_RLCS_CP_INT_INFO_2_BASE_IDX',
|
|
'regRLC_RLCS_DEC_DUMP_ADDR', 'regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX',
|
|
'regRLC_RLCS_DEC_END', 'regRLC_RLCS_DEC_END_BASE_IDX',
|
|
'regRLC_RLCS_DEC_START', 'regRLC_RLCS_DEC_START_BASE_IDX',
|
|
'regRLC_RLCS_DIDT_FORCE_STALL',
|
|
'regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX', 'regRLC_RLCS_DSM_TRIG',
|
|
'regRLC_RLCS_DSM_TRIG_BASE_IDX', 'regRLC_RLCS_EDC_INT_CNTL',
|
|
'regRLC_RLCS_EDC_INT_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_EXCEPTION_REG_1',
|
|
'regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX',
|
|
'regRLC_RLCS_EXCEPTION_REG_2',
|
|
'regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX',
|
|
'regRLC_RLCS_EXCEPTION_REG_3',
|
|
'regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX',
|
|
'regRLC_RLCS_EXCEPTION_REG_4',
|
|
'regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX', 'regRLC_RLCS_GCR_DATA_0',
|
|
'regRLC_RLCS_GCR_DATA_0_BASE_IDX', 'regRLC_RLCS_GCR_DATA_1',
|
|
'regRLC_RLCS_GCR_DATA_1_BASE_IDX', 'regRLC_RLCS_GCR_DATA_2',
|
|
'regRLC_RLCS_GCR_DATA_2_BASE_IDX', 'regRLC_RLCS_GCR_DATA_3',
|
|
'regRLC_RLCS_GCR_DATA_3_BASE_IDX', 'regRLC_RLCS_GCR_STATUS',
|
|
'regRLC_RLCS_GCR_STATUS_BASE_IDX', 'regRLC_RLCS_GENERAL_0',
|
|
'regRLC_RLCS_GENERAL_0_BASE_IDX', 'regRLC_RLCS_GENERAL_1',
|
|
'regRLC_RLCS_GENERAL_10', 'regRLC_RLCS_GENERAL_10_BASE_IDX',
|
|
'regRLC_RLCS_GENERAL_11', 'regRLC_RLCS_GENERAL_11_BASE_IDX',
|
|
'regRLC_RLCS_GENERAL_12', 'regRLC_RLCS_GENERAL_12_BASE_IDX',
|
|
'regRLC_RLCS_GENERAL_13', 'regRLC_RLCS_GENERAL_13_BASE_IDX',
|
|
'regRLC_RLCS_GENERAL_14', 'regRLC_RLCS_GENERAL_14_BASE_IDX',
|
|
'regRLC_RLCS_GENERAL_15', 'regRLC_RLCS_GENERAL_15_BASE_IDX',
|
|
'regRLC_RLCS_GENERAL_16', 'regRLC_RLCS_GENERAL_16_BASE_IDX',
|
|
'regRLC_RLCS_GENERAL_1_BASE_IDX', 'regRLC_RLCS_GENERAL_2',
|
|
'regRLC_RLCS_GENERAL_2_BASE_IDX', 'regRLC_RLCS_GENERAL_3',
|
|
'regRLC_RLCS_GENERAL_3_BASE_IDX', 'regRLC_RLCS_GENERAL_4',
|
|
'regRLC_RLCS_GENERAL_4_BASE_IDX', 'regRLC_RLCS_GENERAL_5',
|
|
'regRLC_RLCS_GENERAL_5_BASE_IDX', 'regRLC_RLCS_GENERAL_6',
|
|
'regRLC_RLCS_GENERAL_6_BASE_IDX', 'regRLC_RLCS_GENERAL_7',
|
|
'regRLC_RLCS_GENERAL_7_BASE_IDX', 'regRLC_RLCS_GENERAL_8',
|
|
'regRLC_RLCS_GENERAL_8_BASE_IDX', 'regRLC_RLCS_GENERAL_9',
|
|
'regRLC_RLCS_GENERAL_9_BASE_IDX',
|
|
'regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL',
|
|
'regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_GFX_DS_CNTL', 'regRLC_RLCS_GFX_DS_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_GFX_MEM_POWER_CTRL_LO',
|
|
'regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX',
|
|
'regRLC_RLCS_GFX_RM_CNTL', 'regRLC_RLCS_GFX_RM_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_GPM_LEGACY_INT_DISABLE',
|
|
'regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX',
|
|
'regRLC_RLCS_GPM_LEGACY_INT_STAT',
|
|
'regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX',
|
|
'regRLC_RLCS_GPM_STAT', 'regRLC_RLCS_GPM_STAT_2',
|
|
'regRLC_RLCS_GPM_STAT_2_BASE_IDX',
|
|
'regRLC_RLCS_GPM_STAT_BASE_IDX',
|
|
'regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL',
|
|
'regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_GRBM_IDLE_BUSY_STAT',
|
|
'regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX',
|
|
'regRLC_RLCS_GRBM_SOFT_RESET',
|
|
'regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX',
|
|
'regRLC_RLCS_IH_COOKIE_SEMAPHORE',
|
|
'regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX',
|
|
'regRLC_RLCS_IH_SEMAPHORE', 'regRLC_RLCS_IH_SEMAPHORE_BASE_IDX',
|
|
'regRLC_RLCS_IMU_GFX_DOORBELL_FENCE',
|
|
'regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RAM_ADDR_0_LSB',
|
|
'regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RAM_ADDR_0_MSB',
|
|
'regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RAM_ADDR_1_LSB',
|
|
'regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RAM_ADDR_1_MSB',
|
|
'regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RAM_CNTL', 'regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RAM_DATA_0',
|
|
'regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RAM_DATA_1',
|
|
'regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RLC_MSG_CNTL',
|
|
'regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RLC_MSG_CONTROL',
|
|
'regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RLC_MSG_DATA0',
|
|
'regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RLC_MSG_DATA1',
|
|
'regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RLC_MSG_DATA2',
|
|
'regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RLC_MSG_DATA3',
|
|
'regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RLC_MSG_DATA4',
|
|
'regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RLC_MUTEX_CNTL',
|
|
'regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RLC_STATUS',
|
|
'regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0',
|
|
'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX',
|
|
'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1',
|
|
'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX',
|
|
'regRLC_RLCS_IMU_VIDCHG_CNTL',
|
|
'regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_IOV_CMD_STATUS',
|
|
'regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX',
|
|
'regRLC_RLCS_IOV_CNTX_LOC_SIZE',
|
|
'regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX',
|
|
'regRLC_RLCS_IOV_SCH_BLOCK', 'regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX',
|
|
'regRLC_RLCS_IOV_VM_BUSY_STATUS',
|
|
'regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX',
|
|
'regRLC_RLCS_KMD_LOG_CNTL1', 'regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX',
|
|
'regRLC_RLCS_KMD_LOG_CNTL2', 'regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX',
|
|
'regRLC_RLCS_PERFMON_CLK_CNTL_UCODE',
|
|
'regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX',
|
|
'regRLC_RLCS_PG_CHANGE_READ',
|
|
'regRLC_RLCS_PG_CHANGE_READ_BASE_IDX',
|
|
'regRLC_RLCS_PG_CHANGE_STATUS',
|
|
'regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX',
|
|
'regRLC_RLCS_PMM_CGCG_CNTL', 'regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_POWER_BRAKE_CNTL',
|
|
'regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_POWER_BRAKE_CNTL_TH1',
|
|
'regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX',
|
|
'regRLC_RLCS_RLC_IMU_MSG_CNTL',
|
|
'regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_RLC_IMU_MSG_CONTROL',
|
|
'regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX',
|
|
'regRLC_RLCS_RLC_IMU_MSG_DATA0',
|
|
'regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX',
|
|
'regRLC_RLCS_RLC_IMU_STATUS',
|
|
'regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX',
|
|
'regRLC_RLCS_SDMA_INT_CNTL_1',
|
|
'regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX',
|
|
'regRLC_RLCS_SDMA_INT_CNTL_2',
|
|
'regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX',
|
|
'regRLC_RLCS_SDMA_INT_INFO', 'regRLC_RLCS_SDMA_INT_INFO_BASE_IDX',
|
|
'regRLC_RLCS_SDMA_INT_STAT', 'regRLC_RLCS_SDMA_INT_STAT_BASE_IDX',
|
|
'regRLC_RLCS_SOC_DS_CNTL', 'regRLC_RLCS_SOC_DS_CNTL_BASE_IDX',
|
|
'regRLC_RLCS_SPM_INT_CTRL', 'regRLC_RLCS_SPM_INT_CTRL_BASE_IDX',
|
|
'regRLC_RLCS_SPM_INT_INFO_1',
|
|
'regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX',
|
|
'regRLC_RLCS_SPM_INT_INFO_2',
|
|
'regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX',
|
|
'regRLC_RLCS_SPM_SQTT_MODE', 'regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX',
|
|
'regRLC_RLCS_SRM_SRCID_CNTL',
|
|
'regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX', 'regRLC_RLCS_UTCL2_CNTL',
|
|
'regRLC_RLCS_UTCL2_CNTL_BASE_IDX', 'regRLC_RLCS_WGP_READ',
|
|
'regRLC_RLCS_WGP_READ_BASE_IDX', 'regRLC_RLCS_WGP_STATUS',
|
|
'regRLC_RLCS_WGP_STATUS_BASE_IDX', 'regRLC_RLCV_COMMAND',
|
|
'regRLC_RLCV_COMMAND_BASE_IDX', 'regRLC_RLCV_DOORBELL_0_DATA_HI',
|
|
'regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX',
|
|
'regRLC_RLCV_DOORBELL_0_DATA_LO',
|
|
'regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX',
|
|
'regRLC_RLCV_DOORBELL_1_DATA_HI',
|
|
'regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX',
|
|
'regRLC_RLCV_DOORBELL_1_DATA_LO',
|
|
'regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX',
|
|
'regRLC_RLCV_DOORBELL_2_DATA_HI',
|
|
'regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX',
|
|
'regRLC_RLCV_DOORBELL_2_DATA_LO',
|
|
'regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX',
|
|
'regRLC_RLCV_DOORBELL_3_DATA_HI',
|
|
'regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX',
|
|
'regRLC_RLCV_DOORBELL_3_DATA_LO',
|
|
'regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX',
|
|
'regRLC_RLCV_DOORBELL_CNTL', 'regRLC_RLCV_DOORBELL_CNTL_BASE_IDX',
|
|
'regRLC_RLCV_DOORBELL_RANGE',
|
|
'regRLC_RLCV_DOORBELL_RANGE_BASE_IDX',
|
|
'regRLC_RLCV_DOORBELL_STAT', 'regRLC_RLCV_DOORBELL_STAT_BASE_IDX',
|
|
'regRLC_RLCV_IRAM_ADDR', 'regRLC_RLCV_IRAM_ADDR_BASE_IDX',
|
|
'regRLC_RLCV_IRAM_DATA', 'regRLC_RLCV_IRAM_DATA_BASE_IDX',
|
|
'regRLC_RLCV_SAFE_MODE', 'regRLC_RLCV_SAFE_MODE_BASE_IDX',
|
|
'regRLC_RLCV_SPARE_INT', 'regRLC_RLCV_SPARE_INT_1',
|
|
'regRLC_RLCV_SPARE_INT_1_BASE_IDX',
|
|
'regRLC_RLCV_SPARE_INT_BASE_IDX', 'regRLC_RLCV_TIMER_CTRL',
|
|
'regRLC_RLCV_TIMER_CTRL_BASE_IDX', 'regRLC_RLCV_TIMER_INT_0',
|
|
'regRLC_RLCV_TIMER_INT_0_BASE_IDX', 'regRLC_RLCV_TIMER_INT_1',
|
|
'regRLC_RLCV_TIMER_INT_1_BASE_IDX', 'regRLC_RLCV_TIMER_STAT',
|
|
'regRLC_RLCV_TIMER_STAT_BASE_IDX', 'regRLC_SAFE_MODE',
|
|
'regRLC_SAFE_MODE_BASE_IDX', 'regRLC_SDMA0_BUSY_STATUS',
|
|
'regRLC_SDMA0_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA0_STATUS',
|
|
'regRLC_SDMA0_STATUS_BASE_IDX', 'regRLC_SDMA1_BUSY_STATUS',
|
|
'regRLC_SDMA1_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA1_STATUS',
|
|
'regRLC_SDMA1_STATUS_BASE_IDX', 'regRLC_SDMA2_BUSY_STATUS',
|
|
'regRLC_SDMA2_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA2_STATUS',
|
|
'regRLC_SDMA2_STATUS_BASE_IDX', 'regRLC_SDMA3_BUSY_STATUS',
|
|
'regRLC_SDMA3_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA3_STATUS',
|
|
'regRLC_SDMA3_STATUS_BASE_IDX', 'regRLC_SEMAPHORE_0',
|
|
'regRLC_SEMAPHORE_0_BASE_IDX', 'regRLC_SEMAPHORE_1',
|
|
'regRLC_SEMAPHORE_1_BASE_IDX', 'regRLC_SEMAPHORE_2',
|
|
'regRLC_SEMAPHORE_2_BASE_IDX', 'regRLC_SEMAPHORE_3',
|
|
'regRLC_SEMAPHORE_3_BASE_IDX', 'regRLC_SERDES_BUSY',
|
|
'regRLC_SERDES_BUSY_BASE_IDX', 'regRLC_SERDES_CTRL',
|
|
'regRLC_SERDES_CTRL_BASE_IDX', 'regRLC_SERDES_DATA',
|
|
'regRLC_SERDES_DATA_BASE_IDX', 'regRLC_SERDES_MASK',
|
|
'regRLC_SERDES_MASK_BASE_IDX', 'regRLC_SERDES_RD_DATA_0',
|
|
'regRLC_SERDES_RD_DATA_0_BASE_IDX', 'regRLC_SERDES_RD_DATA_1',
|
|
'regRLC_SERDES_RD_DATA_1_BASE_IDX', 'regRLC_SERDES_RD_DATA_2',
|
|
'regRLC_SERDES_RD_DATA_2_BASE_IDX', 'regRLC_SERDES_RD_DATA_3',
|
|
'regRLC_SERDES_RD_DATA_3_BASE_IDX', 'regRLC_SERDES_RD_INDEX',
|
|
'regRLC_SERDES_RD_INDEX_BASE_IDX', 'regRLC_SMU_ARGUMENT_1',
|
|
'regRLC_SMU_ARGUMENT_1_BASE_IDX', 'regRLC_SMU_ARGUMENT_2',
|
|
'regRLC_SMU_ARGUMENT_2_BASE_IDX', 'regRLC_SMU_ARGUMENT_3',
|
|
'regRLC_SMU_ARGUMENT_3_BASE_IDX', 'regRLC_SMU_ARGUMENT_4',
|
|
'regRLC_SMU_ARGUMENT_4_BASE_IDX', 'regRLC_SMU_ARGUMENT_5',
|
|
'regRLC_SMU_ARGUMENT_5_BASE_IDX', 'regRLC_SMU_CLK_REQ',
|
|
'regRLC_SMU_CLK_REQ_BASE_IDX', 'regRLC_SMU_COMMAND',
|
|
'regRLC_SMU_COMMAND_BASE_IDX', 'regRLC_SMU_MESSAGE',
|
|
'regRLC_SMU_MESSAGE_1', 'regRLC_SMU_MESSAGE_1_BASE_IDX',
|
|
'regRLC_SMU_MESSAGE_2', 'regRLC_SMU_MESSAGE_2_BASE_IDX',
|
|
'regRLC_SMU_MESSAGE_BASE_IDX', 'regRLC_SMU_SAFE_MODE',
|
|
'regRLC_SMU_SAFE_MODE_BASE_IDX', 'regRLC_SPARE',
|
|
'regRLC_SPARE_BASE_IDX', 'regRLC_SPARE_INT_0',
|
|
'regRLC_SPARE_INT_0_BASE_IDX', 'regRLC_SPARE_INT_1',
|
|
'regRLC_SPARE_INT_1_BASE_IDX', 'regRLC_SPARE_INT_2',
|
|
'regRLC_SPARE_INT_2_BASE_IDX', 'regRLC_SPM_ACCUM_CTRL',
|
|
'regRLC_SPM_ACCUM_CTRLRAM_ADDR',
|
|
'regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX',
|
|
'regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET',
|
|
'regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX',
|
|
'regRLC_SPM_ACCUM_CTRLRAM_DATA',
|
|
'regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX',
|
|
'regRLC_SPM_ACCUM_CTRL_BASE_IDX',
|
|
'regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS',
|
|
'regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX',
|
|
'regRLC_SPM_ACCUM_DATARAM_ADDR',
|
|
'regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX',
|
|
'regRLC_SPM_ACCUM_DATARAM_DATA',
|
|
'regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX',
|
|
'regRLC_SPM_ACCUM_DATARAM_WRCOUNT',
|
|
'regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX',
|
|
'regRLC_SPM_ACCUM_MODE', 'regRLC_SPM_ACCUM_MODE_BASE_IDX',
|
|
'regRLC_SPM_ACCUM_SAMPLES_REQUESTED',
|
|
'regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX',
|
|
'regRLC_SPM_ACCUM_STATUS', 'regRLC_SPM_ACCUM_STATUS_BASE_IDX',
|
|
'regRLC_SPM_ACCUM_SWA_DATARAM_ADDR',
|
|
'regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX',
|
|
'regRLC_SPM_ACCUM_SWA_DATARAM_DATA',
|
|
'regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX',
|
|
'regRLC_SPM_ACCUM_THRESHOLD',
|
|
'regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX',
|
|
'regRLC_SPM_GFXCLOCK_HIGHCOUNT',
|
|
'regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX',
|
|
'regRLC_SPM_GFXCLOCK_LOWCOUNT',
|
|
'regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX',
|
|
'regRLC_SPM_GLOBAL_DELAY_IND_ADDR',
|
|
'regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX',
|
|
'regRLC_SPM_GLOBAL_DELAY_IND_DATA',
|
|
'regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX',
|
|
'regRLC_SPM_GLOBAL_MUXSEL_ADDR',
|
|
'regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX',
|
|
'regRLC_SPM_GLOBAL_MUXSEL_DATA',
|
|
'regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX', 'regRLC_SPM_INT_CNTL',
|
|
'regRLC_SPM_INT_CNTL_BASE_IDX', 'regRLC_SPM_INT_INFO_1',
|
|
'regRLC_SPM_INT_INFO_1_BASE_IDX', 'regRLC_SPM_INT_INFO_2',
|
|
'regRLC_SPM_INT_INFO_2_BASE_IDX', 'regRLC_SPM_INT_STATUS',
|
|
'regRLC_SPM_INT_STATUS_BASE_IDX', 'regRLC_SPM_MC_CNTL',
|
|
'regRLC_SPM_MC_CNTL_BASE_IDX', 'regRLC_SPM_MODE',
|
|
'regRLC_SPM_MODE_BASE_IDX', 'regRLC_SPM_PAUSE',
|
|
'regRLC_SPM_PAUSE_BASE_IDX', 'regRLC_SPM_PERFMON_CNTL',
|
|
'regRLC_SPM_PERFMON_CNTL_BASE_IDX',
|
|
'regRLC_SPM_PERFMON_RING_BASE_HI',
|
|
'regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX',
|
|
'regRLC_SPM_PERFMON_RING_BASE_LO',
|
|
'regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX',
|
|
'regRLC_SPM_PERFMON_RING_SIZE',
|
|
'regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX',
|
|
'regRLC_SPM_PERFMON_SEGMENT_SIZE',
|
|
'regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX',
|
|
'regRLC_SPM_RING_RDPTR', 'regRLC_SPM_RING_RDPTR_BASE_IDX',
|
|
'regRLC_SPM_RING_WRPTR', 'regRLC_SPM_RING_WRPTR_BASE_IDX',
|
|
'regRLC_SPM_RSPM_CMD', 'regRLC_SPM_RSPM_CMD_ACK',
|
|
'regRLC_SPM_RSPM_CMD_ACK_BASE_IDX',
|
|
'regRLC_SPM_RSPM_CMD_BASE_IDX', 'regRLC_SPM_RSPM_REQ_DATA_HI',
|
|
'regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX',
|
|
'regRLC_SPM_RSPM_REQ_DATA_LO',
|
|
'regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX', 'regRLC_SPM_RSPM_REQ_OP',
|
|
'regRLC_SPM_RSPM_REQ_OP_BASE_IDX', 'regRLC_SPM_RSPM_RET_DATA',
|
|
'regRLC_SPM_RSPM_RET_DATA_BASE_IDX', 'regRLC_SPM_RSPM_RET_OP',
|
|
'regRLC_SPM_RSPM_RET_OP_BASE_IDX', 'regRLC_SPM_SAMPLE_CNT',
|
|
'regRLC_SPM_SAMPLE_CNT_BASE_IDX', 'regRLC_SPM_SEGMENT_THRESHOLD',
|
|
'regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX',
|
|
'regRLC_SPM_SE_DELAY_IND_ADDR',
|
|
'regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX',
|
|
'regRLC_SPM_SE_DELAY_IND_DATA',
|
|
'regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX',
|
|
'regRLC_SPM_SE_MUXSEL_ADDR', 'regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX',
|
|
'regRLC_SPM_SE_MUXSEL_DATA', 'regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX',
|
|
'regRLC_SPM_SE_RSPM_REQ_DATA_HI',
|
|
'regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX',
|
|
'regRLC_SPM_SE_RSPM_REQ_DATA_LO',
|
|
'regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX',
|
|
'regRLC_SPM_SE_RSPM_REQ_OP', 'regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX',
|
|
'regRLC_SPM_SE_RSPM_RET_DATA',
|
|
'regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX',
|
|
'regRLC_SPM_SE_RSPM_RET_OP', 'regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX',
|
|
'regRLC_SPM_SPARE', 'regRLC_SPM_SPARE_BASE_IDX',
|
|
'regRLC_SPM_STATUS', 'regRLC_SPM_STATUS_BASE_IDX',
|
|
'regRLC_SPM_THREAD_TRACE_CTRL',
|
|
'regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX', 'regRLC_SPM_UTCL1_CNTL',
|
|
'regRLC_SPM_UTCL1_CNTL_BASE_IDX', 'regRLC_SPM_UTCL1_ERROR_1',
|
|
'regRLC_SPM_UTCL1_ERROR_1_BASE_IDX', 'regRLC_SPM_UTCL1_ERROR_2',
|
|
'regRLC_SPM_UTCL1_ERROR_2_BASE_IDX', 'regRLC_SPP_CAM_ADDR',
|
|
'regRLC_SPP_CAM_ADDR_BASE_IDX', 'regRLC_SPP_CAM_DATA',
|
|
'regRLC_SPP_CAM_DATA_BASE_IDX', 'regRLC_SPP_CAM_EXT_ADDR',
|
|
'regRLC_SPP_CAM_EXT_ADDR_BASE_IDX', 'regRLC_SPP_CAM_EXT_DATA',
|
|
'regRLC_SPP_CAM_EXT_DATA_BASE_IDX', 'regRLC_SPP_CTRL',
|
|
'regRLC_SPP_CTRL_BASE_IDX', 'regRLC_SPP_GLOBAL_SH_ID',
|
|
'regRLC_SPP_GLOBAL_SH_ID_BASE_IDX',
|
|
'regRLC_SPP_GLOBAL_SH_ID_VALID',
|
|
'regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX',
|
|
'regRLC_SPP_INFLIGHT_RD_ADDR',
|
|
'regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX',
|
|
'regRLC_SPP_INFLIGHT_RD_DATA',
|
|
'regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX', 'regRLC_SPP_PBB_INFO',
|
|
'regRLC_SPP_PBB_INFO_BASE_IDX', 'regRLC_SPP_PROF_INFO_1',
|
|
'regRLC_SPP_PROF_INFO_1_BASE_IDX', 'regRLC_SPP_PROF_INFO_2',
|
|
'regRLC_SPP_PROF_INFO_2_BASE_IDX', 'regRLC_SPP_PVT_LEVEL_MAX',
|
|
'regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX', 'regRLC_SPP_PVT_STAT_0',
|
|
'regRLC_SPP_PVT_STAT_0_BASE_IDX', 'regRLC_SPP_PVT_STAT_1',
|
|
'regRLC_SPP_PVT_STAT_1_BASE_IDX', 'regRLC_SPP_PVT_STAT_2',
|
|
'regRLC_SPP_PVT_STAT_2_BASE_IDX', 'regRLC_SPP_PVT_STAT_3',
|
|
'regRLC_SPP_PVT_STAT_3_BASE_IDX', 'regRLC_SPP_RESET',
|
|
'regRLC_SPP_RESET_BASE_IDX', 'regRLC_SPP_SHADER_PROFILE_EN',
|
|
'regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX',
|
|
'regRLC_SPP_SSF_CAPTURE_EN', 'regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX',
|
|
'regRLC_SPP_SSF_THRESHOLD_0',
|
|
'regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX',
|
|
'regRLC_SPP_SSF_THRESHOLD_1',
|
|
'regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX',
|
|
'regRLC_SPP_SSF_THRESHOLD_2',
|
|
'regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX',
|
|
'regRLC_SPP_STALL_STATE_UPDATE',
|
|
'regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX', 'regRLC_SPP_STATUS',
|
|
'regRLC_SPP_STATUS_BASE_IDX', 'regRLC_SRM_ARAM_ADDR',
|
|
'regRLC_SRM_ARAM_ADDR_BASE_IDX', 'regRLC_SRM_ARAM_DATA',
|
|
'regRLC_SRM_ARAM_DATA_BASE_IDX', 'regRLC_SRM_CNTL',
|
|
'regRLC_SRM_CNTL_BASE_IDX', 'regRLC_SRM_DRAM_ADDR',
|
|
'regRLC_SRM_DRAM_ADDR_BASE_IDX', 'regRLC_SRM_DRAM_DATA',
|
|
'regRLC_SRM_DRAM_DATA_BASE_IDX', 'regRLC_SRM_GPM_ABORT',
|
|
'regRLC_SRM_GPM_ABORT_BASE_IDX', 'regRLC_SRM_GPM_COMMAND',
|
|
'regRLC_SRM_GPM_COMMAND_BASE_IDX',
|
|
'regRLC_SRM_GPM_COMMAND_STATUS',
|
|
'regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_0',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_1',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_2',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_3',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_4',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_5',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_6',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_7',
|
|
'regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_0',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_1',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_2',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_3',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_4',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_5',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_6',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_7',
|
|
'regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX', 'regRLC_SRM_STAT',
|
|
'regRLC_SRM_STAT_BASE_IDX', 'regRLC_STAT',
|
|
'regRLC_STATIC_PG_STATUS', 'regRLC_STATIC_PG_STATUS_BASE_IDX',
|
|
'regRLC_STAT_BASE_IDX', 'regRLC_UCODE_CNTL',
|
|
'regRLC_UCODE_CNTL_BASE_IDX', 'regRLC_ULV_RESIDENCY_CNTR_CTRL',
|
|
'regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX',
|
|
'regRLC_ULV_RESIDENCY_EVENT_CNTR',
|
|
'regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX',
|
|
'regRLC_ULV_RESIDENCY_REF_CNTR',
|
|
'regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_UTCL1_STATUS',
|
|
'regRLC_UTCL1_STATUS_2', 'regRLC_UTCL1_STATUS_2_BASE_IDX',
|
|
'regRLC_UTCL1_STATUS_BASE_IDX', 'regRLC_WGP_STATUS',
|
|
'regRLC_WGP_STATUS_BASE_IDX', 'regRLC_XT_CORE_ALT_RESET_VEC',
|
|
'regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX',
|
|
'regRLC_XT_CORE_FAULT_INFO', 'regRLC_XT_CORE_FAULT_INFO_BASE_IDX',
|
|
'regRLC_XT_CORE_INTERRUPT', 'regRLC_XT_CORE_INTERRUPT_BASE_IDX',
|
|
'regRLC_XT_CORE_RESERVED', 'regRLC_XT_CORE_RESERVED_BASE_IDX',
|
|
'regRLC_XT_CORE_STATUS', 'regRLC_XT_CORE_STATUS_BASE_IDX',
|
|
'regRLC_XT_DOORBELL_0_DATA_HI',
|
|
'regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX',
|
|
'regRLC_XT_DOORBELL_0_DATA_LO',
|
|
'regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX',
|
|
'regRLC_XT_DOORBELL_1_DATA_HI',
|
|
'regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX',
|
|
'regRLC_XT_DOORBELL_1_DATA_LO',
|
|
'regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX',
|
|
'regRLC_XT_DOORBELL_2_DATA_HI',
|
|
'regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX',
|
|
'regRLC_XT_DOORBELL_2_DATA_LO',
|
|
'regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX',
|
|
'regRLC_XT_DOORBELL_3_DATA_HI',
|
|
'regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX',
|
|
'regRLC_XT_DOORBELL_3_DATA_LO',
|
|
'regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX',
|
|
'regRLC_XT_DOORBELL_CNTL', 'regRLC_XT_DOORBELL_CNTL_BASE_IDX',
|
|
'regRLC_XT_DOORBELL_RANGE', 'regRLC_XT_DOORBELL_RANGE_BASE_IDX',
|
|
'regRLC_XT_DOORBELL_STAT', 'regRLC_XT_DOORBELL_STAT_BASE_IDX',
|
|
'regRLC_XT_INT_VEC_CLEAR', 'regRLC_XT_INT_VEC_CLEAR_BASE_IDX',
|
|
'regRLC_XT_INT_VEC_FORCE', 'regRLC_XT_INT_VEC_FORCE_BASE_IDX',
|
|
'regRLC_XT_INT_VEC_MUX_INT_SEL',
|
|
'regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX',
|
|
'regRLC_XT_INT_VEC_MUX_SEL', 'regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX',
|
|
'regRMI_CLOCK_CNTRL', 'regRMI_CLOCK_CNTRL_BASE_IDX',
|
|
'regRMI_DEMUX_CNTL', 'regRMI_DEMUX_CNTL_BASE_IDX',
|
|
'regRMI_GENERAL_CNTL', 'regRMI_GENERAL_CNTL1',
|
|
'regRMI_GENERAL_CNTL1_BASE_IDX', 'regRMI_GENERAL_CNTL_BASE_IDX',
|
|
'regRMI_GENERAL_STATUS', 'regRMI_GENERAL_STATUS_BASE_IDX',
|
|
'regRMI_PERFCOUNTER0_HI', 'regRMI_PERFCOUNTER0_HI_BASE_IDX',
|
|
'regRMI_PERFCOUNTER0_LO', 'regRMI_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regRMI_PERFCOUNTER0_SELECT', 'regRMI_PERFCOUNTER0_SELECT1',
|
|
'regRMI_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regRMI_PERFCOUNTER0_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER1_HI',
|
|
'regRMI_PERFCOUNTER1_HI_BASE_IDX', 'regRMI_PERFCOUNTER1_LO',
|
|
'regRMI_PERFCOUNTER1_LO_BASE_IDX', 'regRMI_PERFCOUNTER1_SELECT',
|
|
'regRMI_PERFCOUNTER1_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER2_HI',
|
|
'regRMI_PERFCOUNTER2_HI_BASE_IDX', 'regRMI_PERFCOUNTER2_LO',
|
|
'regRMI_PERFCOUNTER2_LO_BASE_IDX', 'regRMI_PERFCOUNTER2_SELECT',
|
|
'regRMI_PERFCOUNTER2_SELECT1',
|
|
'regRMI_PERFCOUNTER2_SELECT1_BASE_IDX',
|
|
'regRMI_PERFCOUNTER2_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER3_HI',
|
|
'regRMI_PERFCOUNTER3_HI_BASE_IDX', 'regRMI_PERFCOUNTER3_LO',
|
|
'regRMI_PERFCOUNTER3_LO_BASE_IDX', 'regRMI_PERFCOUNTER3_SELECT',
|
|
'regRMI_PERFCOUNTER3_SELECT_BASE_IDX', 'regRMI_PERF_COUNTER_CNTL',
|
|
'regRMI_PERF_COUNTER_CNTL_BASE_IDX',
|
|
'regRMI_PROBE_POP_LOGIC_CNTL',
|
|
'regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX', 'regRMI_RB_GLX_CID_MAP',
|
|
'regRMI_RB_GLX_CID_MAP_BASE_IDX', 'regRMI_SCOREBOARD_CNTL',
|
|
'regRMI_SCOREBOARD_CNTL_BASE_IDX', 'regRMI_SCOREBOARD_STATUS0',
|
|
'regRMI_SCOREBOARD_STATUS0_BASE_IDX', 'regRMI_SCOREBOARD_STATUS1',
|
|
'regRMI_SCOREBOARD_STATUS1_BASE_IDX', 'regRMI_SCOREBOARD_STATUS2',
|
|
'regRMI_SCOREBOARD_STATUS2_BASE_IDX', 'regRMI_SPARE',
|
|
'regRMI_SPARE_1', 'regRMI_SPARE_1_BASE_IDX', 'regRMI_SPARE_2',
|
|
'regRMI_SPARE_2_BASE_IDX', 'regRMI_SPARE_BASE_IDX',
|
|
'regRMI_SUBBLOCK_STATUS0', 'regRMI_SUBBLOCK_STATUS0_BASE_IDX',
|
|
'regRMI_SUBBLOCK_STATUS1', 'regRMI_SUBBLOCK_STATUS1_BASE_IDX',
|
|
'regRMI_SUBBLOCK_STATUS2', 'regRMI_SUBBLOCK_STATUS2_BASE_IDX',
|
|
'regRMI_SUBBLOCK_STATUS3', 'regRMI_SUBBLOCK_STATUS3_BASE_IDX',
|
|
'regRMI_TCIW_FORMATTER0_CNTL',
|
|
'regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX',
|
|
'regRMI_TCIW_FORMATTER1_CNTL',
|
|
'regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX', 'regRMI_UTCL1_CNTL1',
|
|
'regRMI_UTCL1_CNTL1_BASE_IDX', 'regRMI_UTCL1_CNTL2',
|
|
'regRMI_UTCL1_CNTL2_BASE_IDX', 'regRMI_UTCL1_STATUS',
|
|
'regRMI_UTCL1_STATUS_BASE_IDX', 'regRMI_UTC_UNIT_CONFIG',
|
|
'regRMI_UTC_UNIT_CONFIG_BASE_IDX', 'regRMI_UTC_XNACK_N_MISC_CNTL',
|
|
'regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX',
|
|
'regRMI_XBAR_ARBITER_CONFIG', 'regRMI_XBAR_ARBITER_CONFIG_1',
|
|
'regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX',
|
|
'regRMI_XBAR_ARBITER_CONFIG_BASE_IDX', 'regRMI_XBAR_CONFIG',
|
|
'regRMI_XBAR_CONFIG_BASE_IDX', 'regRTAVFS_RTAVFS_REG_ADDR',
|
|
'regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX', 'regRTAVFS_RTAVFS_WR_DATA',
|
|
'regRTAVFS_RTAVFS_WR_DATA_BASE_IDX', 'regSCRATCH_REG0',
|
|
'regSCRATCH_REG0_BASE_IDX', 'regSCRATCH_REG1',
|
|
'regSCRATCH_REG1_BASE_IDX', 'regSCRATCH_REG2',
|
|
'regSCRATCH_REG2_BASE_IDX', 'regSCRATCH_REG3',
|
|
'regSCRATCH_REG3_BASE_IDX', 'regSCRATCH_REG4',
|
|
'regSCRATCH_REG4_BASE_IDX', 'regSCRATCH_REG5',
|
|
'regSCRATCH_REG5_BASE_IDX', 'regSCRATCH_REG6',
|
|
'regSCRATCH_REG6_BASE_IDX', 'regSCRATCH_REG7',
|
|
'regSCRATCH_REG7_BASE_IDX', 'regSCRATCH_REG_ATOMIC',
|
|
'regSCRATCH_REG_ATOMIC_BASE_IDX', 'regSCRATCH_REG_CMPSWAP_ATOMIC',
|
|
'regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX', 'regSDMA0_AQL_STATUS',
|
|
'regSDMA0_AQL_STATUS_BASE_IDX', 'regSDMA0_ATOMIC_CNTL',
|
|
'regSDMA0_ATOMIC_CNTL_BASE_IDX', 'regSDMA0_ATOMIC_PREOP_HI',
|
|
'regSDMA0_ATOMIC_PREOP_HI_BASE_IDX', 'regSDMA0_ATOMIC_PREOP_LO',
|
|
'regSDMA0_ATOMIC_PREOP_LO_BASE_IDX', 'regSDMA0_BA_THRESHOLD',
|
|
'regSDMA0_BA_THRESHOLD_BASE_IDX', 'regSDMA0_BROADCAST_UCODE_ADDR',
|
|
'regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX',
|
|
'regSDMA0_BROADCAST_UCODE_DATA',
|
|
'regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX', 'regSDMA0_CE_CTRL',
|
|
'regSDMA0_CE_CTRL_BASE_IDX', 'regSDMA0_CHICKEN_BITS',
|
|
'regSDMA0_CHICKEN_BITS_2', 'regSDMA0_CHICKEN_BITS_2_BASE_IDX',
|
|
'regSDMA0_CHICKEN_BITS_BASE_IDX', 'regSDMA0_CLOCK_GATING_STATUS',
|
|
'regSDMA0_CLOCK_GATING_STATUS_BASE_IDX', 'regSDMA0_CNTL',
|
|
'regSDMA0_CNTL1', 'regSDMA0_CNTL1_BASE_IDX',
|
|
'regSDMA0_CNTL_BASE_IDX', 'regSDMA0_CRD_CNTL',
|
|
'regSDMA0_CRD_CNTL_BASE_IDX', 'regSDMA0_DEC_START',
|
|
'regSDMA0_DEC_START_BASE_IDX', 'regSDMA0_EA_DBIT_ADDR_DATA',
|
|
'regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX',
|
|
'regSDMA0_EA_DBIT_ADDR_INDEX',
|
|
'regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX', 'regSDMA0_EDC_CONFIG',
|
|
'regSDMA0_EDC_CONFIG_BASE_IDX', 'regSDMA0_EDC_COUNTER',
|
|
'regSDMA0_EDC_COUNTER_BASE_IDX', 'regSDMA0_EDC_COUNTER_CLEAR',
|
|
'regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX', 'regSDMA0_ERROR_LOG',
|
|
'regSDMA0_ERROR_LOG_BASE_IDX', 'regSDMA0_F32_CNTL',
|
|
'regSDMA0_F32_CNTL_BASE_IDX', 'regSDMA0_F32_COUNTER',
|
|
'regSDMA0_F32_COUNTER_BASE_IDX', 'regSDMA0_F32_MISC_CNTL',
|
|
'regSDMA0_F32_MISC_CNTL_BASE_IDX', 'regSDMA0_FED_STATUS',
|
|
'regSDMA0_FED_STATUS_BASE_IDX', 'regSDMA0_FREEZE',
|
|
'regSDMA0_FREEZE_BASE_IDX', 'regSDMA0_GB_ADDR_CONFIG',
|
|
'regSDMA0_GB_ADDR_CONFIG_BASE_IDX',
|
|
'regSDMA0_GB_ADDR_CONFIG_READ',
|
|
'regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX',
|
|
'regSDMA0_GLOBAL_QUANTUM', 'regSDMA0_GLOBAL_QUANTUM_BASE_IDX',
|
|
'regSDMA0_GLOBAL_TIMESTAMP_HI',
|
|
'regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX',
|
|
'regSDMA0_GLOBAL_TIMESTAMP_LO',
|
|
'regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX',
|
|
'regSDMA0_HBM_PAGE_CONFIG', 'regSDMA0_HBM_PAGE_CONFIG_BASE_IDX',
|
|
'regSDMA0_HOLE_ADDR_HI', 'regSDMA0_HOLE_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_HOLE_ADDR_LO', 'regSDMA0_HOLE_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_IB_OFFSET_FETCH', 'regSDMA0_IB_OFFSET_FETCH_BASE_IDX',
|
|
'regSDMA0_ID', 'regSDMA0_ID_BASE_IDX', 'regSDMA0_INT_STATUS',
|
|
'regSDMA0_INT_STATUS_BASE_IDX', 'regSDMA0_PERFCNT_MISC_CNTL',
|
|
'regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX',
|
|
'regSDMA0_PERFCNT_PERFCOUNTER0_CFG',
|
|
'regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX',
|
|
'regSDMA0_PERFCNT_PERFCOUNTER1_CFG',
|
|
'regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX',
|
|
'regSDMA0_PERFCNT_PERFCOUNTER_HI',
|
|
'regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX',
|
|
'regSDMA0_PERFCNT_PERFCOUNTER_LO',
|
|
'regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX',
|
|
'regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL',
|
|
'regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
|
|
'regSDMA0_PERFCOUNTER0_HI', 'regSDMA0_PERFCOUNTER0_HI_BASE_IDX',
|
|
'regSDMA0_PERFCOUNTER0_LO', 'regSDMA0_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regSDMA0_PERFCOUNTER0_SELECT', 'regSDMA0_PERFCOUNTER0_SELECT1',
|
|
'regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX',
|
|
'regSDMA0_PERFCOUNTER1_HI', 'regSDMA0_PERFCOUNTER1_HI_BASE_IDX',
|
|
'regSDMA0_PERFCOUNTER1_LO', 'regSDMA0_PERFCOUNTER1_LO_BASE_IDX',
|
|
'regSDMA0_PERFCOUNTER1_SELECT', 'regSDMA0_PERFCOUNTER1_SELECT1',
|
|
'regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX',
|
|
'regSDMA0_PHYSICAL_ADDR_HI', 'regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_PHYSICAL_ADDR_LO', 'regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_POWER_CNTL', 'regSDMA0_POWER_CNTL_BASE_IDX',
|
|
'regSDMA0_PROCESS_QUANTUM0', 'regSDMA0_PROCESS_QUANTUM0_BASE_IDX',
|
|
'regSDMA0_PROCESS_QUANTUM1', 'regSDMA0_PROCESS_QUANTUM1_BASE_IDX',
|
|
'regSDMA0_PROGRAM', 'regSDMA0_PROGRAM_BASE_IDX',
|
|
'regSDMA0_PUB_DUMMY_REG0', 'regSDMA0_PUB_DUMMY_REG0_BASE_IDX',
|
|
'regSDMA0_PUB_DUMMY_REG1', 'regSDMA0_PUB_DUMMY_REG1_BASE_IDX',
|
|
'regSDMA0_PUB_DUMMY_REG2', 'regSDMA0_PUB_DUMMY_REG2_BASE_IDX',
|
|
'regSDMA0_PUB_DUMMY_REG3', 'regSDMA0_PUB_DUMMY_REG3_BASE_IDX',
|
|
'regSDMA0_QUEUE0_CONTEXT_STATUS',
|
|
'regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA0_QUEUE0_CSA_ADDR_HI',
|
|
'regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE0_CSA_ADDR_LO',
|
|
'regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE0_DOORBELL', 'regSDMA0_QUEUE0_DOORBELL_BASE_IDX',
|
|
'regSDMA0_QUEUE0_DOORBELL_LOG',
|
|
'regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA0_QUEUE0_DOORBELL_OFFSET',
|
|
'regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA0_QUEUE0_DUMMY_REG', 'regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX',
|
|
'regSDMA0_QUEUE0_IB_BASE_HI',
|
|
'regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE0_IB_BASE_LO',
|
|
'regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE0_IB_CNTL',
|
|
'regSDMA0_QUEUE0_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_IB_OFFSET',
|
|
'regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE0_IB_RPTR',
|
|
'regSDMA0_QUEUE0_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE0_IB_SIZE',
|
|
'regSDMA0_QUEUE0_IB_SIZE_BASE_IDX',
|
|
'regSDMA0_QUEUE0_IB_SUB_REMAIN',
|
|
'regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA0_QUEUE0_MIDCMD_CNTL',
|
|
'regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA0',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA1', 'regSDMA0_QUEUE0_MIDCMD_DATA10',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA2',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA3',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA4',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA5',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA6',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA7',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA8',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA9',
|
|
'regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA0_QUEUE0_MINOR_PTR_UPDATE',
|
|
'regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA0_QUEUE0_PREEMPT', 'regSDMA0_QUEUE0_PREEMPT_BASE_IDX',
|
|
'regSDMA0_QUEUE0_RB_AQL_CNTL',
|
|
'regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_RB_BASE',
|
|
'regSDMA0_QUEUE0_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE0_RB_BASE_HI',
|
|
'regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE0_RB_CNTL',
|
|
'regSDMA0_QUEUE0_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_RB_PREEMPT',
|
|
'regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE0_RB_RPTR',
|
|
'regSDMA0_QUEUE0_RB_RPTR_ADDR_HI',
|
|
'regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE0_RB_RPTR_ADDR_LO',
|
|
'regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE0_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE0_RB_RPTR_HI',
|
|
'regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE0_RB_WPTR',
|
|
'regSDMA0_QUEUE0_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE0_RB_WPTR_HI',
|
|
'regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE0_SCHEDULE_CNTL',
|
|
'regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE0_SKIP_CNTL', 'regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE1_CONTEXT_STATUS',
|
|
'regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA0_QUEUE1_CSA_ADDR_HI',
|
|
'regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE1_CSA_ADDR_LO',
|
|
'regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE1_DOORBELL', 'regSDMA0_QUEUE1_DOORBELL_BASE_IDX',
|
|
'regSDMA0_QUEUE1_DOORBELL_LOG',
|
|
'regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA0_QUEUE1_DOORBELL_OFFSET',
|
|
'regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA0_QUEUE1_DUMMY_REG', 'regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX',
|
|
'regSDMA0_QUEUE1_IB_BASE_HI',
|
|
'regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE1_IB_BASE_LO',
|
|
'regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE1_IB_CNTL',
|
|
'regSDMA0_QUEUE1_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_IB_OFFSET',
|
|
'regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE1_IB_RPTR',
|
|
'regSDMA0_QUEUE1_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE1_IB_SIZE',
|
|
'regSDMA0_QUEUE1_IB_SIZE_BASE_IDX',
|
|
'regSDMA0_QUEUE1_IB_SUB_REMAIN',
|
|
'regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA0_QUEUE1_MIDCMD_CNTL',
|
|
'regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA0',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA1', 'regSDMA0_QUEUE1_MIDCMD_DATA10',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA2',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA3',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA4',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA5',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA6',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA7',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA8',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA9',
|
|
'regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA0_QUEUE1_MINOR_PTR_UPDATE',
|
|
'regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA0_QUEUE1_PREEMPT', 'regSDMA0_QUEUE1_PREEMPT_BASE_IDX',
|
|
'regSDMA0_QUEUE1_RB_AQL_CNTL',
|
|
'regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_RB_BASE',
|
|
'regSDMA0_QUEUE1_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE1_RB_BASE_HI',
|
|
'regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE1_RB_CNTL',
|
|
'regSDMA0_QUEUE1_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_RB_PREEMPT',
|
|
'regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE1_RB_RPTR',
|
|
'regSDMA0_QUEUE1_RB_RPTR_ADDR_HI',
|
|
'regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE1_RB_RPTR_ADDR_LO',
|
|
'regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE1_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE1_RB_RPTR_HI',
|
|
'regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE1_RB_WPTR',
|
|
'regSDMA0_QUEUE1_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE1_RB_WPTR_HI',
|
|
'regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE1_SCHEDULE_CNTL',
|
|
'regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE1_SKIP_CNTL', 'regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE2_CONTEXT_STATUS',
|
|
'regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA0_QUEUE2_CSA_ADDR_HI',
|
|
'regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE2_CSA_ADDR_LO',
|
|
'regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE2_DOORBELL', 'regSDMA0_QUEUE2_DOORBELL_BASE_IDX',
|
|
'regSDMA0_QUEUE2_DOORBELL_LOG',
|
|
'regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA0_QUEUE2_DOORBELL_OFFSET',
|
|
'regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA0_QUEUE2_DUMMY_REG', 'regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX',
|
|
'regSDMA0_QUEUE2_IB_BASE_HI',
|
|
'regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE2_IB_BASE_LO',
|
|
'regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE2_IB_CNTL',
|
|
'regSDMA0_QUEUE2_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_IB_OFFSET',
|
|
'regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE2_IB_RPTR',
|
|
'regSDMA0_QUEUE2_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE2_IB_SIZE',
|
|
'regSDMA0_QUEUE2_IB_SIZE_BASE_IDX',
|
|
'regSDMA0_QUEUE2_IB_SUB_REMAIN',
|
|
'regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA0_QUEUE2_MIDCMD_CNTL',
|
|
'regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA0',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA1', 'regSDMA0_QUEUE2_MIDCMD_DATA10',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA2',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA3',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA4',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA5',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA6',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA7',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA8',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA9',
|
|
'regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA0_QUEUE2_MINOR_PTR_UPDATE',
|
|
'regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA0_QUEUE2_PREEMPT', 'regSDMA0_QUEUE2_PREEMPT_BASE_IDX',
|
|
'regSDMA0_QUEUE2_RB_AQL_CNTL',
|
|
'regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_RB_BASE',
|
|
'regSDMA0_QUEUE2_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE2_RB_BASE_HI',
|
|
'regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE2_RB_CNTL',
|
|
'regSDMA0_QUEUE2_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_RB_PREEMPT',
|
|
'regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE2_RB_RPTR',
|
|
'regSDMA0_QUEUE2_RB_RPTR_ADDR_HI',
|
|
'regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE2_RB_RPTR_ADDR_LO',
|
|
'regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE2_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE2_RB_RPTR_HI',
|
|
'regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE2_RB_WPTR',
|
|
'regSDMA0_QUEUE2_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE2_RB_WPTR_HI',
|
|
'regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE2_SCHEDULE_CNTL',
|
|
'regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE2_SKIP_CNTL', 'regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE3_CONTEXT_STATUS',
|
|
'regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA0_QUEUE3_CSA_ADDR_HI',
|
|
'regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE3_CSA_ADDR_LO',
|
|
'regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE3_DOORBELL', 'regSDMA0_QUEUE3_DOORBELL_BASE_IDX',
|
|
'regSDMA0_QUEUE3_DOORBELL_LOG',
|
|
'regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA0_QUEUE3_DOORBELL_OFFSET',
|
|
'regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA0_QUEUE3_DUMMY_REG', 'regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX',
|
|
'regSDMA0_QUEUE3_IB_BASE_HI',
|
|
'regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE3_IB_BASE_LO',
|
|
'regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE3_IB_CNTL',
|
|
'regSDMA0_QUEUE3_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_IB_OFFSET',
|
|
'regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE3_IB_RPTR',
|
|
'regSDMA0_QUEUE3_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE3_IB_SIZE',
|
|
'regSDMA0_QUEUE3_IB_SIZE_BASE_IDX',
|
|
'regSDMA0_QUEUE3_IB_SUB_REMAIN',
|
|
'regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA0_QUEUE3_MIDCMD_CNTL',
|
|
'regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA0',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA1', 'regSDMA0_QUEUE3_MIDCMD_DATA10',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA2',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA3',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA4',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA5',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA6',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA7',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA8',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA9',
|
|
'regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA0_QUEUE3_MINOR_PTR_UPDATE',
|
|
'regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA0_QUEUE3_PREEMPT', 'regSDMA0_QUEUE3_PREEMPT_BASE_IDX',
|
|
'regSDMA0_QUEUE3_RB_AQL_CNTL',
|
|
'regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_RB_BASE',
|
|
'regSDMA0_QUEUE3_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE3_RB_BASE_HI',
|
|
'regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE3_RB_CNTL',
|
|
'regSDMA0_QUEUE3_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_RB_PREEMPT',
|
|
'regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE3_RB_RPTR',
|
|
'regSDMA0_QUEUE3_RB_RPTR_ADDR_HI',
|
|
'regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE3_RB_RPTR_ADDR_LO',
|
|
'regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE3_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE3_RB_RPTR_HI',
|
|
'regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE3_RB_WPTR',
|
|
'regSDMA0_QUEUE3_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE3_RB_WPTR_HI',
|
|
'regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE3_SCHEDULE_CNTL',
|
|
'regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE3_SKIP_CNTL', 'regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE4_CONTEXT_STATUS',
|
|
'regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA0_QUEUE4_CSA_ADDR_HI',
|
|
'regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE4_CSA_ADDR_LO',
|
|
'regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE4_DOORBELL', 'regSDMA0_QUEUE4_DOORBELL_BASE_IDX',
|
|
'regSDMA0_QUEUE4_DOORBELL_LOG',
|
|
'regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA0_QUEUE4_DOORBELL_OFFSET',
|
|
'regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA0_QUEUE4_DUMMY_REG', 'regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX',
|
|
'regSDMA0_QUEUE4_IB_BASE_HI',
|
|
'regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE4_IB_BASE_LO',
|
|
'regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE4_IB_CNTL',
|
|
'regSDMA0_QUEUE4_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_IB_OFFSET',
|
|
'regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE4_IB_RPTR',
|
|
'regSDMA0_QUEUE4_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE4_IB_SIZE',
|
|
'regSDMA0_QUEUE4_IB_SIZE_BASE_IDX',
|
|
'regSDMA0_QUEUE4_IB_SUB_REMAIN',
|
|
'regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA0_QUEUE4_MIDCMD_CNTL',
|
|
'regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA0',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA1', 'regSDMA0_QUEUE4_MIDCMD_DATA10',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA2',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA3',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA4',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA5',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA6',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA7',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA8',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA9',
|
|
'regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA0_QUEUE4_MINOR_PTR_UPDATE',
|
|
'regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA0_QUEUE4_PREEMPT', 'regSDMA0_QUEUE4_PREEMPT_BASE_IDX',
|
|
'regSDMA0_QUEUE4_RB_AQL_CNTL',
|
|
'regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_RB_BASE',
|
|
'regSDMA0_QUEUE4_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE4_RB_BASE_HI',
|
|
'regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE4_RB_CNTL',
|
|
'regSDMA0_QUEUE4_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_RB_PREEMPT',
|
|
'regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE4_RB_RPTR',
|
|
'regSDMA0_QUEUE4_RB_RPTR_ADDR_HI',
|
|
'regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE4_RB_RPTR_ADDR_LO',
|
|
'regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE4_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE4_RB_RPTR_HI',
|
|
'regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE4_RB_WPTR',
|
|
'regSDMA0_QUEUE4_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE4_RB_WPTR_HI',
|
|
'regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE4_SCHEDULE_CNTL',
|
|
'regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE4_SKIP_CNTL', 'regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE5_CONTEXT_STATUS',
|
|
'regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA0_QUEUE5_CSA_ADDR_HI',
|
|
'regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE5_CSA_ADDR_LO',
|
|
'regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE5_DOORBELL', 'regSDMA0_QUEUE5_DOORBELL_BASE_IDX',
|
|
'regSDMA0_QUEUE5_DOORBELL_LOG',
|
|
'regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA0_QUEUE5_DOORBELL_OFFSET',
|
|
'regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA0_QUEUE5_DUMMY_REG', 'regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX',
|
|
'regSDMA0_QUEUE5_IB_BASE_HI',
|
|
'regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE5_IB_BASE_LO',
|
|
'regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE5_IB_CNTL',
|
|
'regSDMA0_QUEUE5_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_IB_OFFSET',
|
|
'regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE5_IB_RPTR',
|
|
'regSDMA0_QUEUE5_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE5_IB_SIZE',
|
|
'regSDMA0_QUEUE5_IB_SIZE_BASE_IDX',
|
|
'regSDMA0_QUEUE5_IB_SUB_REMAIN',
|
|
'regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA0_QUEUE5_MIDCMD_CNTL',
|
|
'regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA0',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA1', 'regSDMA0_QUEUE5_MIDCMD_DATA10',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA2',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA3',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA4',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA5',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA6',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA7',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA8',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA9',
|
|
'regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA0_QUEUE5_MINOR_PTR_UPDATE',
|
|
'regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA0_QUEUE5_PREEMPT', 'regSDMA0_QUEUE5_PREEMPT_BASE_IDX',
|
|
'regSDMA0_QUEUE5_RB_AQL_CNTL',
|
|
'regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_RB_BASE',
|
|
'regSDMA0_QUEUE5_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE5_RB_BASE_HI',
|
|
'regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE5_RB_CNTL',
|
|
'regSDMA0_QUEUE5_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_RB_PREEMPT',
|
|
'regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE5_RB_RPTR',
|
|
'regSDMA0_QUEUE5_RB_RPTR_ADDR_HI',
|
|
'regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE5_RB_RPTR_ADDR_LO',
|
|
'regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE5_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE5_RB_RPTR_HI',
|
|
'regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE5_RB_WPTR',
|
|
'regSDMA0_QUEUE5_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE5_RB_WPTR_HI',
|
|
'regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE5_SCHEDULE_CNTL',
|
|
'regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE5_SKIP_CNTL', 'regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE6_CONTEXT_STATUS',
|
|
'regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA0_QUEUE6_CSA_ADDR_HI',
|
|
'regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE6_CSA_ADDR_LO',
|
|
'regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE6_DOORBELL', 'regSDMA0_QUEUE6_DOORBELL_BASE_IDX',
|
|
'regSDMA0_QUEUE6_DOORBELL_LOG',
|
|
'regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA0_QUEUE6_DOORBELL_OFFSET',
|
|
'regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA0_QUEUE6_DUMMY_REG', 'regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX',
|
|
'regSDMA0_QUEUE6_IB_BASE_HI',
|
|
'regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE6_IB_BASE_LO',
|
|
'regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE6_IB_CNTL',
|
|
'regSDMA0_QUEUE6_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_IB_OFFSET',
|
|
'regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE6_IB_RPTR',
|
|
'regSDMA0_QUEUE6_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE6_IB_SIZE',
|
|
'regSDMA0_QUEUE6_IB_SIZE_BASE_IDX',
|
|
'regSDMA0_QUEUE6_IB_SUB_REMAIN',
|
|
'regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA0_QUEUE6_MIDCMD_CNTL',
|
|
'regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA0',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA1', 'regSDMA0_QUEUE6_MIDCMD_DATA10',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA2',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA3',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA4',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA5',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA6',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA7',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA8',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA9',
|
|
'regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA0_QUEUE6_MINOR_PTR_UPDATE',
|
|
'regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA0_QUEUE6_PREEMPT', 'regSDMA0_QUEUE6_PREEMPT_BASE_IDX',
|
|
'regSDMA0_QUEUE6_RB_AQL_CNTL',
|
|
'regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_RB_BASE',
|
|
'regSDMA0_QUEUE6_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE6_RB_BASE_HI',
|
|
'regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE6_RB_CNTL',
|
|
'regSDMA0_QUEUE6_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_RB_PREEMPT',
|
|
'regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE6_RB_RPTR',
|
|
'regSDMA0_QUEUE6_RB_RPTR_ADDR_HI',
|
|
'regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE6_RB_RPTR_ADDR_LO',
|
|
'regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE6_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE6_RB_RPTR_HI',
|
|
'regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE6_RB_WPTR',
|
|
'regSDMA0_QUEUE6_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE6_RB_WPTR_HI',
|
|
'regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE6_SCHEDULE_CNTL',
|
|
'regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE6_SKIP_CNTL', 'regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE7_CONTEXT_STATUS',
|
|
'regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA0_QUEUE7_CSA_ADDR_HI',
|
|
'regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE7_CSA_ADDR_LO',
|
|
'regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE7_DOORBELL', 'regSDMA0_QUEUE7_DOORBELL_BASE_IDX',
|
|
'regSDMA0_QUEUE7_DOORBELL_LOG',
|
|
'regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA0_QUEUE7_DOORBELL_OFFSET',
|
|
'regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA0_QUEUE7_DUMMY_REG', 'regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX',
|
|
'regSDMA0_QUEUE7_IB_BASE_HI',
|
|
'regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE7_IB_BASE_LO',
|
|
'regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE7_IB_CNTL',
|
|
'regSDMA0_QUEUE7_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_IB_OFFSET',
|
|
'regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE7_IB_RPTR',
|
|
'regSDMA0_QUEUE7_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE7_IB_SIZE',
|
|
'regSDMA0_QUEUE7_IB_SIZE_BASE_IDX',
|
|
'regSDMA0_QUEUE7_IB_SUB_REMAIN',
|
|
'regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA0_QUEUE7_MIDCMD_CNTL',
|
|
'regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA0',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA1', 'regSDMA0_QUEUE7_MIDCMD_DATA10',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA2',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA3',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA4',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA5',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA6',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA7',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA8',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA9',
|
|
'regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA0_QUEUE7_MINOR_PTR_UPDATE',
|
|
'regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA0_QUEUE7_PREEMPT', 'regSDMA0_QUEUE7_PREEMPT_BASE_IDX',
|
|
'regSDMA0_QUEUE7_RB_AQL_CNTL',
|
|
'regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_RB_BASE',
|
|
'regSDMA0_QUEUE7_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE7_RB_BASE_HI',
|
|
'regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE7_RB_CNTL',
|
|
'regSDMA0_QUEUE7_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_RB_PREEMPT',
|
|
'regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE7_RB_RPTR',
|
|
'regSDMA0_QUEUE7_RB_RPTR_ADDR_HI',
|
|
'regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE7_RB_RPTR_ADDR_LO',
|
|
'regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE7_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE7_RB_RPTR_HI',
|
|
'regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE7_RB_WPTR',
|
|
'regSDMA0_QUEUE7_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE7_RB_WPTR_HI',
|
|
'regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA0_QUEUE7_SCHEDULE_CNTL',
|
|
'regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE7_SKIP_CNTL', 'regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA0_QUEUE_RESET_REQ', 'regSDMA0_QUEUE_RESET_REQ_BASE_IDX',
|
|
'regSDMA0_QUEUE_STATUS0', 'regSDMA0_QUEUE_STATUS0_BASE_IDX',
|
|
'regSDMA0_RB_RPTR_FETCH', 'regSDMA0_RB_RPTR_FETCH_BASE_IDX',
|
|
'regSDMA0_RB_RPTR_FETCH_HI', 'regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX',
|
|
'regSDMA0_RELAX_ORDERING_LUT',
|
|
'regSDMA0_RELAX_ORDERING_LUT_BASE_IDX', 'regSDMA0_RLC_CGCG_CTRL',
|
|
'regSDMA0_RLC_CGCG_CTRL_BASE_IDX', 'regSDMA0_SCRATCH_RAM_ADDR',
|
|
'regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX', 'regSDMA0_SCRATCH_RAM_DATA',
|
|
'regSDMA0_SCRATCH_RAM_DATA_BASE_IDX',
|
|
'regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL',
|
|
'regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX',
|
|
'regSDMA0_STATUS1_REG', 'regSDMA0_STATUS1_REG_BASE_IDX',
|
|
'regSDMA0_STATUS2_REG', 'regSDMA0_STATUS2_REG_BASE_IDX',
|
|
'regSDMA0_STATUS3_REG', 'regSDMA0_STATUS3_REG_BASE_IDX',
|
|
'regSDMA0_STATUS4_REG', 'regSDMA0_STATUS4_REG_BASE_IDX',
|
|
'regSDMA0_STATUS5_REG', 'regSDMA0_STATUS5_REG_BASE_IDX',
|
|
'regSDMA0_STATUS6_REG', 'regSDMA0_STATUS6_REG_BASE_IDX',
|
|
'regSDMA0_STATUS_REG', 'regSDMA0_STATUS_REG_BASE_IDX',
|
|
'regSDMA0_TILING_CONFIG', 'regSDMA0_TILING_CONFIG_BASE_IDX',
|
|
'regSDMA0_TIMESTAMP_CNTL', 'regSDMA0_TIMESTAMP_CNTL_BASE_IDX',
|
|
'regSDMA0_TLBI_GCR_CNTL', 'regSDMA0_TLBI_GCR_CNTL_BASE_IDX',
|
|
'regSDMA0_UCODE1_CHECKSUM', 'regSDMA0_UCODE1_CHECKSUM_BASE_IDX',
|
|
'regSDMA0_UCODE_ADDR', 'regSDMA0_UCODE_ADDR_BASE_IDX',
|
|
'regSDMA0_UCODE_CHECKSUM', 'regSDMA0_UCODE_CHECKSUM_BASE_IDX',
|
|
'regSDMA0_UCODE_DATA', 'regSDMA0_UCODE_DATA_BASE_IDX',
|
|
'regSDMA0_UCODE_SELFLOAD_CONTROL',
|
|
'regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX', 'regSDMA0_UTCL1_CNTL',
|
|
'regSDMA0_UTCL1_CNTL_BASE_IDX', 'regSDMA0_UTCL1_INV0',
|
|
'regSDMA0_UTCL1_INV0_BASE_IDX', 'regSDMA0_UTCL1_INV1',
|
|
'regSDMA0_UTCL1_INV1_BASE_IDX', 'regSDMA0_UTCL1_INV2',
|
|
'regSDMA0_UTCL1_INV2_BASE_IDX', 'regSDMA0_UTCL1_PAGE',
|
|
'regSDMA0_UTCL1_PAGE_BASE_IDX', 'regSDMA0_UTCL1_RD_STATUS',
|
|
'regSDMA0_UTCL1_RD_STATUS_BASE_IDX', 'regSDMA0_UTCL1_RD_XNACK0',
|
|
'regSDMA0_UTCL1_RD_XNACK0_BASE_IDX', 'regSDMA0_UTCL1_RD_XNACK1',
|
|
'regSDMA0_UTCL1_RD_XNACK1_BASE_IDX', 'regSDMA0_UTCL1_TIMEOUT',
|
|
'regSDMA0_UTCL1_TIMEOUT_BASE_IDX', 'regSDMA0_UTCL1_WATERMK',
|
|
'regSDMA0_UTCL1_WATERMK_BASE_IDX', 'regSDMA0_UTCL1_WR_STATUS',
|
|
'regSDMA0_UTCL1_WR_STATUS_BASE_IDX', 'regSDMA0_UTCL1_WR_XNACK0',
|
|
'regSDMA0_UTCL1_WR_XNACK0_BASE_IDX', 'regSDMA0_UTCL1_WR_XNACK1',
|
|
'regSDMA0_UTCL1_WR_XNACK1_BASE_IDX', 'regSDMA0_VERSION',
|
|
'regSDMA0_VERSION_BASE_IDX', 'regSDMA0_WATCHDOG_CNTL',
|
|
'regSDMA0_WATCHDOG_CNTL_BASE_IDX', 'regSDMA1_AQL_STATUS',
|
|
'regSDMA1_AQL_STATUS_BASE_IDX', 'regSDMA1_ATOMIC_CNTL',
|
|
'regSDMA1_ATOMIC_CNTL_BASE_IDX', 'regSDMA1_ATOMIC_PREOP_HI',
|
|
'regSDMA1_ATOMIC_PREOP_HI_BASE_IDX', 'regSDMA1_ATOMIC_PREOP_LO',
|
|
'regSDMA1_ATOMIC_PREOP_LO_BASE_IDX', 'regSDMA1_BA_THRESHOLD',
|
|
'regSDMA1_BA_THRESHOLD_BASE_IDX', 'regSDMA1_BROADCAST_UCODE_ADDR',
|
|
'regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX',
|
|
'regSDMA1_BROADCAST_UCODE_DATA',
|
|
'regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX', 'regSDMA1_CE_CTRL',
|
|
'regSDMA1_CE_CTRL_BASE_IDX', 'regSDMA1_CHICKEN_BITS',
|
|
'regSDMA1_CHICKEN_BITS_2', 'regSDMA1_CHICKEN_BITS_2_BASE_IDX',
|
|
'regSDMA1_CHICKEN_BITS_BASE_IDX', 'regSDMA1_CLOCK_GATING_STATUS',
|
|
'regSDMA1_CLOCK_GATING_STATUS_BASE_IDX', 'regSDMA1_CNTL',
|
|
'regSDMA1_CNTL1', 'regSDMA1_CNTL1_BASE_IDX',
|
|
'regSDMA1_CNTL_BASE_IDX', 'regSDMA1_CRD_CNTL',
|
|
'regSDMA1_CRD_CNTL_BASE_IDX', 'regSDMA1_DEC_START',
|
|
'regSDMA1_DEC_START_BASE_IDX', 'regSDMA1_EA_DBIT_ADDR_DATA',
|
|
'regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX',
|
|
'regSDMA1_EA_DBIT_ADDR_INDEX',
|
|
'regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX', 'regSDMA1_EDC_CONFIG',
|
|
'regSDMA1_EDC_CONFIG_BASE_IDX', 'regSDMA1_EDC_COUNTER',
|
|
'regSDMA1_EDC_COUNTER_BASE_IDX', 'regSDMA1_EDC_COUNTER_CLEAR',
|
|
'regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX', 'regSDMA1_ERROR_LOG',
|
|
'regSDMA1_ERROR_LOG_BASE_IDX', 'regSDMA1_F32_CNTL',
|
|
'regSDMA1_F32_CNTL_BASE_IDX', 'regSDMA1_F32_COUNTER',
|
|
'regSDMA1_F32_COUNTER_BASE_IDX', 'regSDMA1_F32_MISC_CNTL',
|
|
'regSDMA1_F32_MISC_CNTL_BASE_IDX', 'regSDMA1_FED_STATUS',
|
|
'regSDMA1_FED_STATUS_BASE_IDX', 'regSDMA1_FREEZE',
|
|
'regSDMA1_FREEZE_BASE_IDX', 'regSDMA1_GB_ADDR_CONFIG',
|
|
'regSDMA1_GB_ADDR_CONFIG_BASE_IDX',
|
|
'regSDMA1_GB_ADDR_CONFIG_READ',
|
|
'regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX',
|
|
'regSDMA1_GLOBAL_QUANTUM', 'regSDMA1_GLOBAL_QUANTUM_BASE_IDX',
|
|
'regSDMA1_GLOBAL_TIMESTAMP_HI',
|
|
'regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX',
|
|
'regSDMA1_GLOBAL_TIMESTAMP_LO',
|
|
'regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX',
|
|
'regSDMA1_HBM_PAGE_CONFIG', 'regSDMA1_HBM_PAGE_CONFIG_BASE_IDX',
|
|
'regSDMA1_HOLE_ADDR_HI', 'regSDMA1_HOLE_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_HOLE_ADDR_LO', 'regSDMA1_HOLE_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_IB_OFFSET_FETCH', 'regSDMA1_IB_OFFSET_FETCH_BASE_IDX',
|
|
'regSDMA1_ID', 'regSDMA1_ID_BASE_IDX', 'regSDMA1_INT_STATUS',
|
|
'regSDMA1_INT_STATUS_BASE_IDX', 'regSDMA1_PERFCNT_MISC_CNTL',
|
|
'regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX',
|
|
'regSDMA1_PERFCNT_PERFCOUNTER0_CFG',
|
|
'regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX',
|
|
'regSDMA1_PERFCNT_PERFCOUNTER1_CFG',
|
|
'regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX',
|
|
'regSDMA1_PERFCNT_PERFCOUNTER_HI',
|
|
'regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX',
|
|
'regSDMA1_PERFCNT_PERFCOUNTER_LO',
|
|
'regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX',
|
|
'regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL',
|
|
'regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX',
|
|
'regSDMA1_PERFCOUNTER0_HI', 'regSDMA1_PERFCOUNTER0_HI_BASE_IDX',
|
|
'regSDMA1_PERFCOUNTER0_LO', 'regSDMA1_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regSDMA1_PERFCOUNTER0_SELECT', 'regSDMA1_PERFCOUNTER0_SELECT1',
|
|
'regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX',
|
|
'regSDMA1_PERFCOUNTER1_HI', 'regSDMA1_PERFCOUNTER1_HI_BASE_IDX',
|
|
'regSDMA1_PERFCOUNTER1_LO', 'regSDMA1_PERFCOUNTER1_LO_BASE_IDX',
|
|
'regSDMA1_PERFCOUNTER1_SELECT', 'regSDMA1_PERFCOUNTER1_SELECT1',
|
|
'regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX',
|
|
'regSDMA1_PHYSICAL_ADDR_HI', 'regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_PHYSICAL_ADDR_LO', 'regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_POWER_CNTL', 'regSDMA1_POWER_CNTL_BASE_IDX',
|
|
'regSDMA1_PROCESS_QUANTUM0', 'regSDMA1_PROCESS_QUANTUM0_BASE_IDX',
|
|
'regSDMA1_PROCESS_QUANTUM1', 'regSDMA1_PROCESS_QUANTUM1_BASE_IDX',
|
|
'regSDMA1_PROGRAM', 'regSDMA1_PROGRAM_BASE_IDX',
|
|
'regSDMA1_PUB_DUMMY_REG0', 'regSDMA1_PUB_DUMMY_REG0_BASE_IDX',
|
|
'regSDMA1_PUB_DUMMY_REG1', 'regSDMA1_PUB_DUMMY_REG1_BASE_IDX',
|
|
'regSDMA1_PUB_DUMMY_REG2', 'regSDMA1_PUB_DUMMY_REG2_BASE_IDX',
|
|
'regSDMA1_PUB_DUMMY_REG3', 'regSDMA1_PUB_DUMMY_REG3_BASE_IDX',
|
|
'regSDMA1_QUEUE0_CONTEXT_STATUS',
|
|
'regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA1_QUEUE0_CSA_ADDR_HI',
|
|
'regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE0_CSA_ADDR_LO',
|
|
'regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE0_DOORBELL', 'regSDMA1_QUEUE0_DOORBELL_BASE_IDX',
|
|
'regSDMA1_QUEUE0_DOORBELL_LOG',
|
|
'regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA1_QUEUE0_DOORBELL_OFFSET',
|
|
'regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA1_QUEUE0_DUMMY_REG', 'regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX',
|
|
'regSDMA1_QUEUE0_IB_BASE_HI',
|
|
'regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE0_IB_BASE_LO',
|
|
'regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE0_IB_CNTL',
|
|
'regSDMA1_QUEUE0_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_IB_OFFSET',
|
|
'regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE0_IB_RPTR',
|
|
'regSDMA1_QUEUE0_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE0_IB_SIZE',
|
|
'regSDMA1_QUEUE0_IB_SIZE_BASE_IDX',
|
|
'regSDMA1_QUEUE0_IB_SUB_REMAIN',
|
|
'regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA1_QUEUE0_MIDCMD_CNTL',
|
|
'regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA0',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA1', 'regSDMA1_QUEUE0_MIDCMD_DATA10',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA2',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA3',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA4',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA5',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA6',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA7',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA8',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA9',
|
|
'regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA1_QUEUE0_MINOR_PTR_UPDATE',
|
|
'regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA1_QUEUE0_PREEMPT', 'regSDMA1_QUEUE0_PREEMPT_BASE_IDX',
|
|
'regSDMA1_QUEUE0_RB_AQL_CNTL',
|
|
'regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_RB_BASE',
|
|
'regSDMA1_QUEUE0_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE0_RB_BASE_HI',
|
|
'regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE0_RB_CNTL',
|
|
'regSDMA1_QUEUE0_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_RB_PREEMPT',
|
|
'regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE0_RB_RPTR',
|
|
'regSDMA1_QUEUE0_RB_RPTR_ADDR_HI',
|
|
'regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE0_RB_RPTR_ADDR_LO',
|
|
'regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE0_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE0_RB_RPTR_HI',
|
|
'regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE0_RB_WPTR',
|
|
'regSDMA1_QUEUE0_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE0_RB_WPTR_HI',
|
|
'regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE0_SCHEDULE_CNTL',
|
|
'regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE0_SKIP_CNTL', 'regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE1_CONTEXT_STATUS',
|
|
'regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA1_QUEUE1_CSA_ADDR_HI',
|
|
'regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE1_CSA_ADDR_LO',
|
|
'regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE1_DOORBELL', 'regSDMA1_QUEUE1_DOORBELL_BASE_IDX',
|
|
'regSDMA1_QUEUE1_DOORBELL_LOG',
|
|
'regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA1_QUEUE1_DOORBELL_OFFSET',
|
|
'regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA1_QUEUE1_DUMMY_REG', 'regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX',
|
|
'regSDMA1_QUEUE1_IB_BASE_HI',
|
|
'regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE1_IB_BASE_LO',
|
|
'regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE1_IB_CNTL',
|
|
'regSDMA1_QUEUE1_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_IB_OFFSET',
|
|
'regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE1_IB_RPTR',
|
|
'regSDMA1_QUEUE1_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE1_IB_SIZE',
|
|
'regSDMA1_QUEUE1_IB_SIZE_BASE_IDX',
|
|
'regSDMA1_QUEUE1_IB_SUB_REMAIN',
|
|
'regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA1_QUEUE1_MIDCMD_CNTL',
|
|
'regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA0',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA1', 'regSDMA1_QUEUE1_MIDCMD_DATA10',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA2',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA3',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA4',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA5',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA6',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA7',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA8',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA9',
|
|
'regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA1_QUEUE1_MINOR_PTR_UPDATE',
|
|
'regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA1_QUEUE1_PREEMPT', 'regSDMA1_QUEUE1_PREEMPT_BASE_IDX',
|
|
'regSDMA1_QUEUE1_RB_AQL_CNTL',
|
|
'regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_RB_BASE',
|
|
'regSDMA1_QUEUE1_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE1_RB_BASE_HI',
|
|
'regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE1_RB_CNTL',
|
|
'regSDMA1_QUEUE1_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_RB_PREEMPT',
|
|
'regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE1_RB_RPTR',
|
|
'regSDMA1_QUEUE1_RB_RPTR_ADDR_HI',
|
|
'regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE1_RB_RPTR_ADDR_LO',
|
|
'regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE1_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE1_RB_RPTR_HI',
|
|
'regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE1_RB_WPTR',
|
|
'regSDMA1_QUEUE1_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE1_RB_WPTR_HI',
|
|
'regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE1_SCHEDULE_CNTL',
|
|
'regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE1_SKIP_CNTL', 'regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE2_CONTEXT_STATUS',
|
|
'regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA1_QUEUE2_CSA_ADDR_HI',
|
|
'regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE2_CSA_ADDR_LO',
|
|
'regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE2_DOORBELL', 'regSDMA1_QUEUE2_DOORBELL_BASE_IDX',
|
|
'regSDMA1_QUEUE2_DOORBELL_LOG',
|
|
'regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA1_QUEUE2_DOORBELL_OFFSET',
|
|
'regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA1_QUEUE2_DUMMY_REG', 'regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX',
|
|
'regSDMA1_QUEUE2_IB_BASE_HI',
|
|
'regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE2_IB_BASE_LO',
|
|
'regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE2_IB_CNTL',
|
|
'regSDMA1_QUEUE2_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_IB_OFFSET',
|
|
'regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE2_IB_RPTR',
|
|
'regSDMA1_QUEUE2_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE2_IB_SIZE',
|
|
'regSDMA1_QUEUE2_IB_SIZE_BASE_IDX',
|
|
'regSDMA1_QUEUE2_IB_SUB_REMAIN',
|
|
'regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA1_QUEUE2_MIDCMD_CNTL',
|
|
'regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA0',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA1', 'regSDMA1_QUEUE2_MIDCMD_DATA10',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA2',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA3',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA4',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA5',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA6',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA7',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA8',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA9',
|
|
'regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA1_QUEUE2_MINOR_PTR_UPDATE',
|
|
'regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA1_QUEUE2_PREEMPT', 'regSDMA1_QUEUE2_PREEMPT_BASE_IDX',
|
|
'regSDMA1_QUEUE2_RB_AQL_CNTL',
|
|
'regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_RB_BASE',
|
|
'regSDMA1_QUEUE2_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE2_RB_BASE_HI',
|
|
'regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE2_RB_CNTL',
|
|
'regSDMA1_QUEUE2_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_RB_PREEMPT',
|
|
'regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE2_RB_RPTR',
|
|
'regSDMA1_QUEUE2_RB_RPTR_ADDR_HI',
|
|
'regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE2_RB_RPTR_ADDR_LO',
|
|
'regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE2_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE2_RB_RPTR_HI',
|
|
'regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE2_RB_WPTR',
|
|
'regSDMA1_QUEUE2_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE2_RB_WPTR_HI',
|
|
'regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE2_SCHEDULE_CNTL',
|
|
'regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE2_SKIP_CNTL', 'regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE3_CONTEXT_STATUS',
|
|
'regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA1_QUEUE3_CSA_ADDR_HI',
|
|
'regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE3_CSA_ADDR_LO',
|
|
'regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE3_DOORBELL', 'regSDMA1_QUEUE3_DOORBELL_BASE_IDX',
|
|
'regSDMA1_QUEUE3_DOORBELL_LOG',
|
|
'regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA1_QUEUE3_DOORBELL_OFFSET',
|
|
'regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA1_QUEUE3_DUMMY_REG', 'regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX',
|
|
'regSDMA1_QUEUE3_IB_BASE_HI',
|
|
'regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE3_IB_BASE_LO',
|
|
'regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE3_IB_CNTL',
|
|
'regSDMA1_QUEUE3_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_IB_OFFSET',
|
|
'regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE3_IB_RPTR',
|
|
'regSDMA1_QUEUE3_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE3_IB_SIZE',
|
|
'regSDMA1_QUEUE3_IB_SIZE_BASE_IDX',
|
|
'regSDMA1_QUEUE3_IB_SUB_REMAIN',
|
|
'regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA1_QUEUE3_MIDCMD_CNTL',
|
|
'regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA0',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA1', 'regSDMA1_QUEUE3_MIDCMD_DATA10',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA2',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA3',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA4',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA5',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA6',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA7',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA8',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA9',
|
|
'regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA1_QUEUE3_MINOR_PTR_UPDATE',
|
|
'regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA1_QUEUE3_PREEMPT', 'regSDMA1_QUEUE3_PREEMPT_BASE_IDX',
|
|
'regSDMA1_QUEUE3_RB_AQL_CNTL',
|
|
'regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_RB_BASE',
|
|
'regSDMA1_QUEUE3_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE3_RB_BASE_HI',
|
|
'regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE3_RB_CNTL',
|
|
'regSDMA1_QUEUE3_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_RB_PREEMPT',
|
|
'regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE3_RB_RPTR',
|
|
'regSDMA1_QUEUE3_RB_RPTR_ADDR_HI',
|
|
'regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE3_RB_RPTR_ADDR_LO',
|
|
'regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE3_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE3_RB_RPTR_HI',
|
|
'regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE3_RB_WPTR',
|
|
'regSDMA1_QUEUE3_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE3_RB_WPTR_HI',
|
|
'regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE3_SCHEDULE_CNTL',
|
|
'regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE3_SKIP_CNTL', 'regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE4_CONTEXT_STATUS',
|
|
'regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA1_QUEUE4_CSA_ADDR_HI',
|
|
'regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE4_CSA_ADDR_LO',
|
|
'regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE4_DOORBELL', 'regSDMA1_QUEUE4_DOORBELL_BASE_IDX',
|
|
'regSDMA1_QUEUE4_DOORBELL_LOG',
|
|
'regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA1_QUEUE4_DOORBELL_OFFSET',
|
|
'regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA1_QUEUE4_DUMMY_REG', 'regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX',
|
|
'regSDMA1_QUEUE4_IB_BASE_HI',
|
|
'regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE4_IB_BASE_LO',
|
|
'regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE4_IB_CNTL',
|
|
'regSDMA1_QUEUE4_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_IB_OFFSET',
|
|
'regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE4_IB_RPTR',
|
|
'regSDMA1_QUEUE4_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE4_IB_SIZE',
|
|
'regSDMA1_QUEUE4_IB_SIZE_BASE_IDX',
|
|
'regSDMA1_QUEUE4_IB_SUB_REMAIN',
|
|
'regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA1_QUEUE4_MIDCMD_CNTL',
|
|
'regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA0',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA1', 'regSDMA1_QUEUE4_MIDCMD_DATA10',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA2',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA3',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA4',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA5',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA6',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA7',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA8',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA9',
|
|
'regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA1_QUEUE4_MINOR_PTR_UPDATE',
|
|
'regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA1_QUEUE4_PREEMPT', 'regSDMA1_QUEUE4_PREEMPT_BASE_IDX',
|
|
'regSDMA1_QUEUE4_RB_AQL_CNTL',
|
|
'regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_RB_BASE',
|
|
'regSDMA1_QUEUE4_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE4_RB_BASE_HI',
|
|
'regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE4_RB_CNTL',
|
|
'regSDMA1_QUEUE4_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_RB_PREEMPT',
|
|
'regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE4_RB_RPTR',
|
|
'regSDMA1_QUEUE4_RB_RPTR_ADDR_HI',
|
|
'regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE4_RB_RPTR_ADDR_LO',
|
|
'regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE4_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE4_RB_RPTR_HI',
|
|
'regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE4_RB_WPTR',
|
|
'regSDMA1_QUEUE4_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE4_RB_WPTR_HI',
|
|
'regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE4_SCHEDULE_CNTL',
|
|
'regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE4_SKIP_CNTL', 'regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE5_CONTEXT_STATUS',
|
|
'regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA1_QUEUE5_CSA_ADDR_HI',
|
|
'regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE5_CSA_ADDR_LO',
|
|
'regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE5_DOORBELL', 'regSDMA1_QUEUE5_DOORBELL_BASE_IDX',
|
|
'regSDMA1_QUEUE5_DOORBELL_LOG',
|
|
'regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA1_QUEUE5_DOORBELL_OFFSET',
|
|
'regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA1_QUEUE5_DUMMY_REG', 'regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX',
|
|
'regSDMA1_QUEUE5_IB_BASE_HI',
|
|
'regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE5_IB_BASE_LO',
|
|
'regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE5_IB_CNTL',
|
|
'regSDMA1_QUEUE5_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_IB_OFFSET',
|
|
'regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE5_IB_RPTR',
|
|
'regSDMA1_QUEUE5_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE5_IB_SIZE',
|
|
'regSDMA1_QUEUE5_IB_SIZE_BASE_IDX',
|
|
'regSDMA1_QUEUE5_IB_SUB_REMAIN',
|
|
'regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA1_QUEUE5_MIDCMD_CNTL',
|
|
'regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA0',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA1', 'regSDMA1_QUEUE5_MIDCMD_DATA10',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA2',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA3',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA4',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA5',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA6',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA7',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA8',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA9',
|
|
'regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA1_QUEUE5_MINOR_PTR_UPDATE',
|
|
'regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA1_QUEUE5_PREEMPT', 'regSDMA1_QUEUE5_PREEMPT_BASE_IDX',
|
|
'regSDMA1_QUEUE5_RB_AQL_CNTL',
|
|
'regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_RB_BASE',
|
|
'regSDMA1_QUEUE5_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE5_RB_BASE_HI',
|
|
'regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE5_RB_CNTL',
|
|
'regSDMA1_QUEUE5_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_RB_PREEMPT',
|
|
'regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE5_RB_RPTR',
|
|
'regSDMA1_QUEUE5_RB_RPTR_ADDR_HI',
|
|
'regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE5_RB_RPTR_ADDR_LO',
|
|
'regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE5_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE5_RB_RPTR_HI',
|
|
'regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE5_RB_WPTR',
|
|
'regSDMA1_QUEUE5_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE5_RB_WPTR_HI',
|
|
'regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE5_SCHEDULE_CNTL',
|
|
'regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE5_SKIP_CNTL', 'regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE6_CONTEXT_STATUS',
|
|
'regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA1_QUEUE6_CSA_ADDR_HI',
|
|
'regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE6_CSA_ADDR_LO',
|
|
'regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE6_DOORBELL', 'regSDMA1_QUEUE6_DOORBELL_BASE_IDX',
|
|
'regSDMA1_QUEUE6_DOORBELL_LOG',
|
|
'regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA1_QUEUE6_DOORBELL_OFFSET',
|
|
'regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA1_QUEUE6_DUMMY_REG', 'regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX',
|
|
'regSDMA1_QUEUE6_IB_BASE_HI',
|
|
'regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE6_IB_BASE_LO',
|
|
'regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE6_IB_CNTL',
|
|
'regSDMA1_QUEUE6_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_IB_OFFSET',
|
|
'regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE6_IB_RPTR',
|
|
'regSDMA1_QUEUE6_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE6_IB_SIZE',
|
|
'regSDMA1_QUEUE6_IB_SIZE_BASE_IDX',
|
|
'regSDMA1_QUEUE6_IB_SUB_REMAIN',
|
|
'regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA1_QUEUE6_MIDCMD_CNTL',
|
|
'regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA0',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA1', 'regSDMA1_QUEUE6_MIDCMD_DATA10',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA2',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA3',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA4',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA5',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA6',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA7',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA8',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA9',
|
|
'regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA1_QUEUE6_MINOR_PTR_UPDATE',
|
|
'regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA1_QUEUE6_PREEMPT', 'regSDMA1_QUEUE6_PREEMPT_BASE_IDX',
|
|
'regSDMA1_QUEUE6_RB_AQL_CNTL',
|
|
'regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_RB_BASE',
|
|
'regSDMA1_QUEUE6_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE6_RB_BASE_HI',
|
|
'regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE6_RB_CNTL',
|
|
'regSDMA1_QUEUE6_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_RB_PREEMPT',
|
|
'regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE6_RB_RPTR',
|
|
'regSDMA1_QUEUE6_RB_RPTR_ADDR_HI',
|
|
'regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE6_RB_RPTR_ADDR_LO',
|
|
'regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE6_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE6_RB_RPTR_HI',
|
|
'regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE6_RB_WPTR',
|
|
'regSDMA1_QUEUE6_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE6_RB_WPTR_HI',
|
|
'regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE6_SCHEDULE_CNTL',
|
|
'regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE6_SKIP_CNTL', 'regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE7_CONTEXT_STATUS',
|
|
'regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX',
|
|
'regSDMA1_QUEUE7_CSA_ADDR_HI',
|
|
'regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE7_CSA_ADDR_LO',
|
|
'regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE7_DOORBELL', 'regSDMA1_QUEUE7_DOORBELL_BASE_IDX',
|
|
'regSDMA1_QUEUE7_DOORBELL_LOG',
|
|
'regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX',
|
|
'regSDMA1_QUEUE7_DOORBELL_OFFSET',
|
|
'regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX',
|
|
'regSDMA1_QUEUE7_DUMMY_REG', 'regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX',
|
|
'regSDMA1_QUEUE7_IB_BASE_HI',
|
|
'regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE7_IB_BASE_LO',
|
|
'regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE7_IB_CNTL',
|
|
'regSDMA1_QUEUE7_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_IB_OFFSET',
|
|
'regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE7_IB_RPTR',
|
|
'regSDMA1_QUEUE7_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE7_IB_SIZE',
|
|
'regSDMA1_QUEUE7_IB_SIZE_BASE_IDX',
|
|
'regSDMA1_QUEUE7_IB_SUB_REMAIN',
|
|
'regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX',
|
|
'regSDMA1_QUEUE7_MIDCMD_CNTL',
|
|
'regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA0',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA1', 'regSDMA1_QUEUE7_MIDCMD_DATA10',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA2',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA3',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA4',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA5',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA6',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA7',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA8',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA9',
|
|
'regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX',
|
|
'regSDMA1_QUEUE7_MINOR_PTR_UPDATE',
|
|
'regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX',
|
|
'regSDMA1_QUEUE7_PREEMPT', 'regSDMA1_QUEUE7_PREEMPT_BASE_IDX',
|
|
'regSDMA1_QUEUE7_RB_AQL_CNTL',
|
|
'regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_RB_BASE',
|
|
'regSDMA1_QUEUE7_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE7_RB_BASE_HI',
|
|
'regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE7_RB_CNTL',
|
|
'regSDMA1_QUEUE7_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_RB_PREEMPT',
|
|
'regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE7_RB_RPTR',
|
|
'regSDMA1_QUEUE7_RB_RPTR_ADDR_HI',
|
|
'regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE7_RB_RPTR_ADDR_LO',
|
|
'regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE7_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE7_RB_RPTR_HI',
|
|
'regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE7_RB_WPTR',
|
|
'regSDMA1_QUEUE7_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE7_RB_WPTR_HI',
|
|
'regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI',
|
|
'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX',
|
|
'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO',
|
|
'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX',
|
|
'regSDMA1_QUEUE7_SCHEDULE_CNTL',
|
|
'regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE7_SKIP_CNTL', 'regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX',
|
|
'regSDMA1_QUEUE_RESET_REQ', 'regSDMA1_QUEUE_RESET_REQ_BASE_IDX',
|
|
'regSDMA1_QUEUE_STATUS0', 'regSDMA1_QUEUE_STATUS0_BASE_IDX',
|
|
'regSDMA1_RB_RPTR_FETCH', 'regSDMA1_RB_RPTR_FETCH_BASE_IDX',
|
|
'regSDMA1_RB_RPTR_FETCH_HI', 'regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX',
|
|
'regSDMA1_RELAX_ORDERING_LUT',
|
|
'regSDMA1_RELAX_ORDERING_LUT_BASE_IDX', 'regSDMA1_RLC_CGCG_CTRL',
|
|
'regSDMA1_RLC_CGCG_CTRL_BASE_IDX', 'regSDMA1_SCRATCH_RAM_ADDR',
|
|
'regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX', 'regSDMA1_SCRATCH_RAM_DATA',
|
|
'regSDMA1_SCRATCH_RAM_DATA_BASE_IDX',
|
|
'regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL',
|
|
'regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX',
|
|
'regSDMA1_STATUS1_REG', 'regSDMA1_STATUS1_REG_BASE_IDX',
|
|
'regSDMA1_STATUS2_REG', 'regSDMA1_STATUS2_REG_BASE_IDX',
|
|
'regSDMA1_STATUS3_REG', 'regSDMA1_STATUS3_REG_BASE_IDX',
|
|
'regSDMA1_STATUS4_REG', 'regSDMA1_STATUS4_REG_BASE_IDX',
|
|
'regSDMA1_STATUS5_REG', 'regSDMA1_STATUS5_REG_BASE_IDX',
|
|
'regSDMA1_STATUS6_REG', 'regSDMA1_STATUS6_REG_BASE_IDX',
|
|
'regSDMA1_STATUS_REG', 'regSDMA1_STATUS_REG_BASE_IDX',
|
|
'regSDMA1_TILING_CONFIG', 'regSDMA1_TILING_CONFIG_BASE_IDX',
|
|
'regSDMA1_TIMESTAMP_CNTL', 'regSDMA1_TIMESTAMP_CNTL_BASE_IDX',
|
|
'regSDMA1_TLBI_GCR_CNTL', 'regSDMA1_TLBI_GCR_CNTL_BASE_IDX',
|
|
'regSDMA1_UCODE1_CHECKSUM', 'regSDMA1_UCODE1_CHECKSUM_BASE_IDX',
|
|
'regSDMA1_UCODE_ADDR', 'regSDMA1_UCODE_ADDR_BASE_IDX',
|
|
'regSDMA1_UCODE_CHECKSUM', 'regSDMA1_UCODE_CHECKSUM_BASE_IDX',
|
|
'regSDMA1_UCODE_DATA', 'regSDMA1_UCODE_DATA_BASE_IDX',
|
|
'regSDMA1_UCODE_SELFLOAD_CONTROL',
|
|
'regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX', 'regSDMA1_UTCL1_CNTL',
|
|
'regSDMA1_UTCL1_CNTL_BASE_IDX', 'regSDMA1_UTCL1_INV0',
|
|
'regSDMA1_UTCL1_INV0_BASE_IDX', 'regSDMA1_UTCL1_INV1',
|
|
'regSDMA1_UTCL1_INV1_BASE_IDX', 'regSDMA1_UTCL1_INV2',
|
|
'regSDMA1_UTCL1_INV2_BASE_IDX', 'regSDMA1_UTCL1_PAGE',
|
|
'regSDMA1_UTCL1_PAGE_BASE_IDX', 'regSDMA1_UTCL1_RD_STATUS',
|
|
'regSDMA1_UTCL1_RD_STATUS_BASE_IDX', 'regSDMA1_UTCL1_RD_XNACK0',
|
|
'regSDMA1_UTCL1_RD_XNACK0_BASE_IDX', 'regSDMA1_UTCL1_RD_XNACK1',
|
|
'regSDMA1_UTCL1_RD_XNACK1_BASE_IDX', 'regSDMA1_UTCL1_TIMEOUT',
|
|
'regSDMA1_UTCL1_TIMEOUT_BASE_IDX', 'regSDMA1_UTCL1_WATERMK',
|
|
'regSDMA1_UTCL1_WATERMK_BASE_IDX', 'regSDMA1_UTCL1_WR_STATUS',
|
|
'regSDMA1_UTCL1_WR_STATUS_BASE_IDX', 'regSDMA1_UTCL1_WR_XNACK0',
|
|
'regSDMA1_UTCL1_WR_XNACK0_BASE_IDX', 'regSDMA1_UTCL1_WR_XNACK1',
|
|
'regSDMA1_UTCL1_WR_XNACK1_BASE_IDX', 'regSDMA1_VERSION',
|
|
'regSDMA1_VERSION_BASE_IDX', 'regSDMA1_WATCHDOG_CNTL',
|
|
'regSDMA1_WATCHDOG_CNTL_BASE_IDX', 'regSE0_CAC_AGGR_GFXCLK_CYCLE',
|
|
'regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE0_CAC_AGGR_LOWER',
|
|
'regSE0_CAC_AGGR_LOWER_BASE_IDX', 'regSE0_CAC_AGGR_UPPER',
|
|
'regSE0_CAC_AGGR_UPPER_BASE_IDX', 'regSE1_CAC_AGGR_GFXCLK_CYCLE',
|
|
'regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE1_CAC_AGGR_LOWER',
|
|
'regSE1_CAC_AGGR_LOWER_BASE_IDX', 'regSE1_CAC_AGGR_UPPER',
|
|
'regSE1_CAC_AGGR_UPPER_BASE_IDX', 'regSE2_CAC_AGGR_GFXCLK_CYCLE',
|
|
'regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE2_CAC_AGGR_LOWER',
|
|
'regSE2_CAC_AGGR_LOWER_BASE_IDX', 'regSE2_CAC_AGGR_UPPER',
|
|
'regSE2_CAC_AGGR_UPPER_BASE_IDX', 'regSE3_CAC_AGGR_GFXCLK_CYCLE',
|
|
'regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE3_CAC_AGGR_LOWER',
|
|
'regSE3_CAC_AGGR_LOWER_BASE_IDX', 'regSE3_CAC_AGGR_UPPER',
|
|
'regSE3_CAC_AGGR_UPPER_BASE_IDX', 'regSE4_CAC_AGGR_GFXCLK_CYCLE',
|
|
'regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE4_CAC_AGGR_LOWER',
|
|
'regSE4_CAC_AGGR_LOWER_BASE_IDX', 'regSE4_CAC_AGGR_UPPER',
|
|
'regSE4_CAC_AGGR_UPPER_BASE_IDX', 'regSE5_CAC_AGGR_GFXCLK_CYCLE',
|
|
'regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE5_CAC_AGGR_LOWER',
|
|
'regSE5_CAC_AGGR_LOWER_BASE_IDX', 'regSE5_CAC_AGGR_UPPER',
|
|
'regSE5_CAC_AGGR_UPPER_BASE_IDX', 'regSEDC_GL1_GL2_OVERRIDES',
|
|
'regSEDC_GL1_GL2_OVERRIDES_BASE_IDX', 'regSE_CAC_CTRL_1',
|
|
'regSE_CAC_CTRL_1_BASE_IDX', 'regSE_CAC_CTRL_2',
|
|
'regSE_CAC_CTRL_2_BASE_IDX', 'regSE_CAC_IND_DATA',
|
|
'regSE_CAC_IND_DATA_BASE_IDX', 'regSE_CAC_IND_INDEX',
|
|
'regSE_CAC_IND_INDEX_BASE_IDX', 'regSE_CAC_WEIGHT_BCI_0',
|
|
'regSE_CAC_WEIGHT_BCI_0_BASE_IDX', 'regSE_CAC_WEIGHT_CB_0',
|
|
'regSE_CAC_WEIGHT_CB_0_BASE_IDX', 'regSE_CAC_WEIGHT_CB_1',
|
|
'regSE_CAC_WEIGHT_CB_10', 'regSE_CAC_WEIGHT_CB_10_BASE_IDX',
|
|
'regSE_CAC_WEIGHT_CB_11', 'regSE_CAC_WEIGHT_CB_11_BASE_IDX',
|
|
'regSE_CAC_WEIGHT_CB_1_BASE_IDX', 'regSE_CAC_WEIGHT_CB_2',
|
|
'regSE_CAC_WEIGHT_CB_2_BASE_IDX', 'regSE_CAC_WEIGHT_CB_3',
|
|
'regSE_CAC_WEIGHT_CB_3_BASE_IDX', 'regSE_CAC_WEIGHT_CB_4',
|
|
'regSE_CAC_WEIGHT_CB_4_BASE_IDX', 'regSE_CAC_WEIGHT_CB_5',
|
|
'regSE_CAC_WEIGHT_CB_5_BASE_IDX', 'regSE_CAC_WEIGHT_CB_6',
|
|
'regSE_CAC_WEIGHT_CB_6_BASE_IDX', 'regSE_CAC_WEIGHT_CB_7',
|
|
'regSE_CAC_WEIGHT_CB_7_BASE_IDX', 'regSE_CAC_WEIGHT_CB_8',
|
|
'regSE_CAC_WEIGHT_CB_8_BASE_IDX', 'regSE_CAC_WEIGHT_CB_9',
|
|
'regSE_CAC_WEIGHT_CB_9_BASE_IDX', 'regSE_CAC_WEIGHT_CU_0',
|
|
'regSE_CAC_WEIGHT_CU_0_BASE_IDX', 'regSE_CAC_WEIGHT_DB_0',
|
|
'regSE_CAC_WEIGHT_DB_0_BASE_IDX', 'regSE_CAC_WEIGHT_DB_1',
|
|
'regSE_CAC_WEIGHT_DB_1_BASE_IDX', 'regSE_CAC_WEIGHT_DB_2',
|
|
'regSE_CAC_WEIGHT_DB_2_BASE_IDX', 'regSE_CAC_WEIGHT_DB_3',
|
|
'regSE_CAC_WEIGHT_DB_3_BASE_IDX', 'regSE_CAC_WEIGHT_DB_4',
|
|
'regSE_CAC_WEIGHT_DB_4_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_0',
|
|
'regSE_CAC_WEIGHT_GL1C_0_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_1',
|
|
'regSE_CAC_WEIGHT_GL1C_1_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_2',
|
|
'regSE_CAC_WEIGHT_GL1C_2_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_0',
|
|
'regSE_CAC_WEIGHT_LDS_0_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_1',
|
|
'regSE_CAC_WEIGHT_LDS_1_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_2',
|
|
'regSE_CAC_WEIGHT_LDS_2_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_3',
|
|
'regSE_CAC_WEIGHT_LDS_3_BASE_IDX', 'regSE_CAC_WEIGHT_PA_0',
|
|
'regSE_CAC_WEIGHT_PA_0_BASE_IDX', 'regSE_CAC_WEIGHT_PA_1',
|
|
'regSE_CAC_WEIGHT_PA_1_BASE_IDX', 'regSE_CAC_WEIGHT_PA_2',
|
|
'regSE_CAC_WEIGHT_PA_2_BASE_IDX', 'regSE_CAC_WEIGHT_PA_3',
|
|
'regSE_CAC_WEIGHT_PA_3_BASE_IDX', 'regSE_CAC_WEIGHT_PC_0',
|
|
'regSE_CAC_WEIGHT_PC_0_BASE_IDX', 'regSE_CAC_WEIGHT_RMI_0',
|
|
'regSE_CAC_WEIGHT_RMI_0_BASE_IDX', 'regSE_CAC_WEIGHT_RMI_1',
|
|
'regSE_CAC_WEIGHT_RMI_1_BASE_IDX', 'regSE_CAC_WEIGHT_SC_0',
|
|
'regSE_CAC_WEIGHT_SC_0_BASE_IDX', 'regSE_CAC_WEIGHT_SC_1',
|
|
'regSE_CAC_WEIGHT_SC_1_BASE_IDX', 'regSE_CAC_WEIGHT_SC_2',
|
|
'regSE_CAC_WEIGHT_SC_2_BASE_IDX', 'regSE_CAC_WEIGHT_SC_3',
|
|
'regSE_CAC_WEIGHT_SC_3_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_0',
|
|
'regSE_CAC_WEIGHT_SPI_0_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_1',
|
|
'regSE_CAC_WEIGHT_SPI_1_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_2',
|
|
'regSE_CAC_WEIGHT_SPI_2_BASE_IDX', 'regSE_CAC_WEIGHT_SP_0',
|
|
'regSE_CAC_WEIGHT_SP_0_BASE_IDX', 'regSE_CAC_WEIGHT_SP_1',
|
|
'regSE_CAC_WEIGHT_SP_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQC_0',
|
|
'regSE_CAC_WEIGHT_SQC_0_BASE_IDX', 'regSE_CAC_WEIGHT_SQC_1',
|
|
'regSE_CAC_WEIGHT_SQC_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_0',
|
|
'regSE_CAC_WEIGHT_SQ_0_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_1',
|
|
'regSE_CAC_WEIGHT_SQ_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_2',
|
|
'regSE_CAC_WEIGHT_SQ_2_BASE_IDX', 'regSE_CAC_WEIGHT_SXRB_0',
|
|
'regSE_CAC_WEIGHT_SXRB_0_BASE_IDX', 'regSE_CAC_WEIGHT_SX_0',
|
|
'regSE_CAC_WEIGHT_SX_0_BASE_IDX', 'regSE_CAC_WEIGHT_TA_0',
|
|
'regSE_CAC_WEIGHT_TA_0_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_0',
|
|
'regSE_CAC_WEIGHT_TCP_0_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_1',
|
|
'regSE_CAC_WEIGHT_TCP_1_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_2',
|
|
'regSE_CAC_WEIGHT_TCP_2_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_3',
|
|
'regSE_CAC_WEIGHT_TCP_3_BASE_IDX', 'regSE_CAC_WEIGHT_TD_0',
|
|
'regSE_CAC_WEIGHT_TD_0_BASE_IDX', 'regSE_CAC_WEIGHT_TD_1',
|
|
'regSE_CAC_WEIGHT_TD_1_BASE_IDX', 'regSE_CAC_WEIGHT_TD_2',
|
|
'regSE_CAC_WEIGHT_TD_2_BASE_IDX', 'regSE_CAC_WEIGHT_TD_3',
|
|
'regSE_CAC_WEIGHT_TD_3_BASE_IDX', 'regSE_CAC_WEIGHT_TD_4',
|
|
'regSE_CAC_WEIGHT_TD_4_BASE_IDX', 'regSE_CAC_WEIGHT_TD_5',
|
|
'regSE_CAC_WEIGHT_TD_5_BASE_IDX', 'regSE_CAC_WEIGHT_UTCL1_0',
|
|
'regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX',
|
|
'regSE_CAC_WINDOW_AGGR_VALUE',
|
|
'regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX',
|
|
'regSE_CAC_WINDOW_GFXCLK_CYCLE',
|
|
'regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX', 'regSH_MEM_BASES',
|
|
'regSH_MEM_BASES_BASE_IDX', 'regSH_MEM_CONFIG',
|
|
'regSH_MEM_CONFIG_BASE_IDX', 'regSH_RESERVED_REG0',
|
|
'regSH_RESERVED_REG0_BASE_IDX', 'regSH_RESERVED_REG1',
|
|
'regSH_RESERVED_REG1_BASE_IDX', 'regSMU_RLC_RESPONSE',
|
|
'regSMU_RLC_RESPONSE_BASE_IDX', 'regSPI_ARB_CNTL_0',
|
|
'regSPI_ARB_CNTL_0_BASE_IDX', 'regSPI_ARB_CYCLES_0',
|
|
'regSPI_ARB_CYCLES_0_BASE_IDX', 'regSPI_ARB_CYCLES_1',
|
|
'regSPI_ARB_CYCLES_1_BASE_IDX', 'regSPI_ARB_PRIORITY',
|
|
'regSPI_ARB_PRIORITY_BASE_IDX', 'regSPI_ATTRIBUTE_RING_BASE',
|
|
'regSPI_ATTRIBUTE_RING_BASE_BASE_IDX',
|
|
'regSPI_ATTRIBUTE_RING_SIZE',
|
|
'regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX', 'regSPI_BARYC_CNTL',
|
|
'regSPI_BARYC_CNTL_BASE_IDX', 'regSPI_COMPUTE_QUEUE_RESET',
|
|
'regSPI_COMPUTE_QUEUE_RESET_BASE_IDX',
|
|
'regSPI_COMPUTE_WF_CTX_SAVE',
|
|
'regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX',
|
|
'regSPI_COMPUTE_WF_CTX_SAVE_STATUS',
|
|
'regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX',
|
|
'regSPI_CONFIG_CNTL', 'regSPI_CONFIG_CNTL_1',
|
|
'regSPI_CONFIG_CNTL_1_BASE_IDX', 'regSPI_CONFIG_CNTL_2',
|
|
'regSPI_CONFIG_CNTL_2_BASE_IDX', 'regSPI_CONFIG_CNTL_BASE_IDX',
|
|
'regSPI_CONFIG_PS_CU_EN', 'regSPI_CONFIG_PS_CU_EN_BASE_IDX',
|
|
'regSPI_CSQ_WF_ACTIVE_COUNT_0',
|
|
'regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX',
|
|
'regSPI_CSQ_WF_ACTIVE_COUNT_1',
|
|
'regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX',
|
|
'regSPI_CSQ_WF_ACTIVE_COUNT_2',
|
|
'regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX',
|
|
'regSPI_CSQ_WF_ACTIVE_COUNT_3',
|
|
'regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX',
|
|
'regSPI_CSQ_WF_ACTIVE_STATUS',
|
|
'regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX', 'regSPI_DSM_CNTL',
|
|
'regSPI_DSM_CNTL2', 'regSPI_DSM_CNTL2_BASE_IDX',
|
|
'regSPI_DSM_CNTL_BASE_IDX', 'regSPI_EDC_CNT',
|
|
'regSPI_EDC_CNT_BASE_IDX', 'regSPI_EXP_THROTTLE_CTRL',
|
|
'regSPI_EXP_THROTTLE_CTRL_BASE_IDX', 'regSPI_FEATURE_CTRL',
|
|
'regSPI_FEATURE_CTRL_BASE_IDX', 'regSPI_GDBG_PER_VMID_CNTL',
|
|
'regSPI_GDBG_PER_VMID_CNTL_BASE_IDX', 'regSPI_GDBG_TRAP_CONFIG',
|
|
'regSPI_GDBG_TRAP_CONFIG_BASE_IDX', 'regSPI_GDBG_WAVE_CNTL',
|
|
'regSPI_GDBG_WAVE_CNTL3', 'regSPI_GDBG_WAVE_CNTL3_BASE_IDX',
|
|
'regSPI_GDBG_WAVE_CNTL_BASE_IDX', 'regSPI_GDS_CREDITS',
|
|
'regSPI_GDS_CREDITS_BASE_IDX', 'regSPI_GFX_CNTL',
|
|
'regSPI_GFX_CNTL_BASE_IDX', 'regSPI_GFX_SCRATCH_BASE_HI',
|
|
'regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX',
|
|
'regSPI_GFX_SCRATCH_BASE_LO',
|
|
'regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX', 'regSPI_GS_THROTTLE_CNTL1',
|
|
'regSPI_GS_THROTTLE_CNTL1_BASE_IDX', 'regSPI_GS_THROTTLE_CNTL2',
|
|
'regSPI_GS_THROTTLE_CNTL2_BASE_IDX', 'regSPI_INTERP_CONTROL_0',
|
|
'regSPI_INTERP_CONTROL_0_BASE_IDX', 'regSPI_LB_CTR_CTRL',
|
|
'regSPI_LB_CTR_CTRL_BASE_IDX', 'regSPI_LB_DATA_REG',
|
|
'regSPI_LB_DATA_REG_BASE_IDX', 'regSPI_LB_DATA_WAVES',
|
|
'regSPI_LB_DATA_WAVES_BASE_IDX', 'regSPI_LB_WGP_MASK',
|
|
'regSPI_LB_WGP_MASK_BASE_IDX', 'regSPI_P0_TRAP_SCREEN_GPR_MIN',
|
|
'regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX',
|
|
'regSPI_P0_TRAP_SCREEN_PSBA_HI',
|
|
'regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX',
|
|
'regSPI_P0_TRAP_SCREEN_PSBA_LO',
|
|
'regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX',
|
|
'regSPI_P0_TRAP_SCREEN_PSMA_HI',
|
|
'regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX',
|
|
'regSPI_P0_TRAP_SCREEN_PSMA_LO',
|
|
'regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX',
|
|
'regSPI_P1_TRAP_SCREEN_GPR_MIN',
|
|
'regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX',
|
|
'regSPI_P1_TRAP_SCREEN_PSBA_HI',
|
|
'regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX',
|
|
'regSPI_P1_TRAP_SCREEN_PSBA_LO',
|
|
'regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX',
|
|
'regSPI_P1_TRAP_SCREEN_PSMA_HI',
|
|
'regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX',
|
|
'regSPI_P1_TRAP_SCREEN_PSMA_LO',
|
|
'regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX',
|
|
'regSPI_PERFCOUNTER0_HI', 'regSPI_PERFCOUNTER0_HI_BASE_IDX',
|
|
'regSPI_PERFCOUNTER0_LO', 'regSPI_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regSPI_PERFCOUNTER0_SELECT', 'regSPI_PERFCOUNTER0_SELECT1',
|
|
'regSPI_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regSPI_PERFCOUNTER0_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER1_HI',
|
|
'regSPI_PERFCOUNTER1_HI_BASE_IDX', 'regSPI_PERFCOUNTER1_LO',
|
|
'regSPI_PERFCOUNTER1_LO_BASE_IDX', 'regSPI_PERFCOUNTER1_SELECT',
|
|
'regSPI_PERFCOUNTER1_SELECT1',
|
|
'regSPI_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regSPI_PERFCOUNTER1_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER2_HI',
|
|
'regSPI_PERFCOUNTER2_HI_BASE_IDX', 'regSPI_PERFCOUNTER2_LO',
|
|
'regSPI_PERFCOUNTER2_LO_BASE_IDX', 'regSPI_PERFCOUNTER2_SELECT',
|
|
'regSPI_PERFCOUNTER2_SELECT1',
|
|
'regSPI_PERFCOUNTER2_SELECT1_BASE_IDX',
|
|
'regSPI_PERFCOUNTER2_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER3_HI',
|
|
'regSPI_PERFCOUNTER3_HI_BASE_IDX', 'regSPI_PERFCOUNTER3_LO',
|
|
'regSPI_PERFCOUNTER3_LO_BASE_IDX', 'regSPI_PERFCOUNTER3_SELECT',
|
|
'regSPI_PERFCOUNTER3_SELECT1',
|
|
'regSPI_PERFCOUNTER3_SELECT1_BASE_IDX',
|
|
'regSPI_PERFCOUNTER3_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER4_HI',
|
|
'regSPI_PERFCOUNTER4_HI_BASE_IDX', 'regSPI_PERFCOUNTER4_LO',
|
|
'regSPI_PERFCOUNTER4_LO_BASE_IDX', 'regSPI_PERFCOUNTER4_SELECT',
|
|
'regSPI_PERFCOUNTER4_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER5_HI',
|
|
'regSPI_PERFCOUNTER5_HI_BASE_IDX', 'regSPI_PERFCOUNTER5_LO',
|
|
'regSPI_PERFCOUNTER5_LO_BASE_IDX', 'regSPI_PERFCOUNTER5_SELECT',
|
|
'regSPI_PERFCOUNTER5_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER_BINS',
|
|
'regSPI_PERFCOUNTER_BINS_BASE_IDX',
|
|
'regSPI_PG_ENABLE_STATIC_WGP_MASK',
|
|
'regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX', 'regSPI_PQEV_CTRL',
|
|
'regSPI_PQEV_CTRL_BASE_IDX', 'regSPI_PS_INPUT_ADDR',
|
|
'regSPI_PS_INPUT_ADDR_BASE_IDX', 'regSPI_PS_INPUT_CNTL_0',
|
|
'regSPI_PS_INPUT_CNTL_0_BASE_IDX', 'regSPI_PS_INPUT_CNTL_1',
|
|
'regSPI_PS_INPUT_CNTL_10', 'regSPI_PS_INPUT_CNTL_10_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_11', 'regSPI_PS_INPUT_CNTL_11_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_12', 'regSPI_PS_INPUT_CNTL_12_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_13', 'regSPI_PS_INPUT_CNTL_13_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_14', 'regSPI_PS_INPUT_CNTL_14_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_15', 'regSPI_PS_INPUT_CNTL_15_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_16', 'regSPI_PS_INPUT_CNTL_16_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_17', 'regSPI_PS_INPUT_CNTL_17_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_18', 'regSPI_PS_INPUT_CNTL_18_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_19', 'regSPI_PS_INPUT_CNTL_19_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_1_BASE_IDX', 'regSPI_PS_INPUT_CNTL_2',
|
|
'regSPI_PS_INPUT_CNTL_20', 'regSPI_PS_INPUT_CNTL_20_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_21', 'regSPI_PS_INPUT_CNTL_21_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_22', 'regSPI_PS_INPUT_CNTL_22_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_23', 'regSPI_PS_INPUT_CNTL_23_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_24', 'regSPI_PS_INPUT_CNTL_24_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_25', 'regSPI_PS_INPUT_CNTL_25_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_26', 'regSPI_PS_INPUT_CNTL_26_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_27', 'regSPI_PS_INPUT_CNTL_27_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_28', 'regSPI_PS_INPUT_CNTL_28_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_29', 'regSPI_PS_INPUT_CNTL_29_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_2_BASE_IDX', 'regSPI_PS_INPUT_CNTL_3',
|
|
'regSPI_PS_INPUT_CNTL_30', 'regSPI_PS_INPUT_CNTL_30_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_31', 'regSPI_PS_INPUT_CNTL_31_BASE_IDX',
|
|
'regSPI_PS_INPUT_CNTL_3_BASE_IDX', 'regSPI_PS_INPUT_CNTL_4',
|
|
'regSPI_PS_INPUT_CNTL_4_BASE_IDX', 'regSPI_PS_INPUT_CNTL_5',
|
|
'regSPI_PS_INPUT_CNTL_5_BASE_IDX', 'regSPI_PS_INPUT_CNTL_6',
|
|
'regSPI_PS_INPUT_CNTL_6_BASE_IDX', 'regSPI_PS_INPUT_CNTL_7',
|
|
'regSPI_PS_INPUT_CNTL_7_BASE_IDX', 'regSPI_PS_INPUT_CNTL_8',
|
|
'regSPI_PS_INPUT_CNTL_8_BASE_IDX', 'regSPI_PS_INPUT_CNTL_9',
|
|
'regSPI_PS_INPUT_CNTL_9_BASE_IDX', 'regSPI_PS_INPUT_ENA',
|
|
'regSPI_PS_INPUT_ENA_BASE_IDX', 'regSPI_PS_IN_CONTROL',
|
|
'regSPI_PS_IN_CONTROL_BASE_IDX', 'regSPI_PS_MAX_WAVE_ID',
|
|
'regSPI_PS_MAX_WAVE_ID_BASE_IDX', 'regSPI_RESOURCE_RESERVE_CU_0',
|
|
'regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_1', 'regSPI_RESOURCE_RESERVE_CU_10',
|
|
'regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_11',
|
|
'regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_12',
|
|
'regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_13',
|
|
'regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_14',
|
|
'regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_15',
|
|
'regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_2',
|
|
'regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_3',
|
|
'regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_4',
|
|
'regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_5',
|
|
'regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_6',
|
|
'regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_7',
|
|
'regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_8',
|
|
'regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_CU_9',
|
|
'regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_0',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_1',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_10',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_11',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_12',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_13',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_14',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_15',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_2',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_3',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_4',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_5',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_6',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_7',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_8',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_9',
|
|
'regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX',
|
|
'regSPI_SHADER_COL_FORMAT', 'regSPI_SHADER_COL_FORMAT_BASE_IDX',
|
|
'regSPI_SHADER_GS_MESHLET_DIM',
|
|
'regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX',
|
|
'regSPI_SHADER_GS_MESHLET_EXP_ALLOC',
|
|
'regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX',
|
|
'regSPI_SHADER_IDX_FORMAT', 'regSPI_SHADER_IDX_FORMAT_BASE_IDX',
|
|
'regSPI_SHADER_PGM_CHKSUM_GS',
|
|
'regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX',
|
|
'regSPI_SHADER_PGM_CHKSUM_HS',
|
|
'regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX',
|
|
'regSPI_SHADER_PGM_CHKSUM_PS',
|
|
'regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX', 'regSPI_SHADER_PGM_HI_ES',
|
|
'regSPI_SHADER_PGM_HI_ES_BASE_IDX', 'regSPI_SHADER_PGM_HI_ES_GS',
|
|
'regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX', 'regSPI_SHADER_PGM_HI_GS',
|
|
'regSPI_SHADER_PGM_HI_GS_BASE_IDX', 'regSPI_SHADER_PGM_HI_HS',
|
|
'regSPI_SHADER_PGM_HI_HS_BASE_IDX', 'regSPI_SHADER_PGM_HI_LS',
|
|
'regSPI_SHADER_PGM_HI_LS_BASE_IDX', 'regSPI_SHADER_PGM_HI_LS_HS',
|
|
'regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX', 'regSPI_SHADER_PGM_HI_PS',
|
|
'regSPI_SHADER_PGM_HI_PS_BASE_IDX', 'regSPI_SHADER_PGM_LO_ES',
|
|
'regSPI_SHADER_PGM_LO_ES_BASE_IDX', 'regSPI_SHADER_PGM_LO_ES_GS',
|
|
'regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX', 'regSPI_SHADER_PGM_LO_GS',
|
|
'regSPI_SHADER_PGM_LO_GS_BASE_IDX', 'regSPI_SHADER_PGM_LO_HS',
|
|
'regSPI_SHADER_PGM_LO_HS_BASE_IDX', 'regSPI_SHADER_PGM_LO_LS',
|
|
'regSPI_SHADER_PGM_LO_LS_BASE_IDX', 'regSPI_SHADER_PGM_LO_LS_HS',
|
|
'regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX', 'regSPI_SHADER_PGM_LO_PS',
|
|
'regSPI_SHADER_PGM_LO_PS_BASE_IDX', 'regSPI_SHADER_PGM_RSRC1_GS',
|
|
'regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX',
|
|
'regSPI_SHADER_PGM_RSRC1_HS',
|
|
'regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX',
|
|
'regSPI_SHADER_PGM_RSRC1_PS',
|
|
'regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX',
|
|
'regSPI_SHADER_PGM_RSRC2_GS',
|
|
'regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX',
|
|
'regSPI_SHADER_PGM_RSRC2_HS',
|
|
'regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX',
|
|
'regSPI_SHADER_PGM_RSRC2_PS',
|
|
'regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX',
|
|
'regSPI_SHADER_PGM_RSRC3_GS',
|
|
'regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX',
|
|
'regSPI_SHADER_PGM_RSRC3_HS',
|
|
'regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX',
|
|
'regSPI_SHADER_PGM_RSRC3_PS',
|
|
'regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX',
|
|
'regSPI_SHADER_PGM_RSRC4_GS',
|
|
'regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX',
|
|
'regSPI_SHADER_PGM_RSRC4_HS',
|
|
'regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX',
|
|
'regSPI_SHADER_PGM_RSRC4_PS',
|
|
'regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX', 'regSPI_SHADER_POS_FORMAT',
|
|
'regSPI_SHADER_POS_FORMAT_BASE_IDX',
|
|
'regSPI_SHADER_REQ_CTRL_ESGS',
|
|
'regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX',
|
|
'regSPI_SHADER_REQ_CTRL_LSHS',
|
|
'regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX',
|
|
'regSPI_SHADER_REQ_CTRL_PS', 'regSPI_SHADER_REQ_CTRL_PS_BASE_IDX',
|
|
'regSPI_SHADER_RSRC_LIMIT_CTRL',
|
|
'regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX',
|
|
'regSPI_SHADER_USER_ACCUM_ESGS_0',
|
|
'regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX',
|
|
'regSPI_SHADER_USER_ACCUM_ESGS_1',
|
|
'regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX',
|
|
'regSPI_SHADER_USER_ACCUM_ESGS_2',
|
|
'regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX',
|
|
'regSPI_SHADER_USER_ACCUM_ESGS_3',
|
|
'regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX',
|
|
'regSPI_SHADER_USER_ACCUM_LSHS_0',
|
|
'regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX',
|
|
'regSPI_SHADER_USER_ACCUM_LSHS_1',
|
|
'regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX',
|
|
'regSPI_SHADER_USER_ACCUM_LSHS_2',
|
|
'regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX',
|
|
'regSPI_SHADER_USER_ACCUM_LSHS_3',
|
|
'regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX',
|
|
'regSPI_SHADER_USER_ACCUM_PS_0',
|
|
'regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX',
|
|
'regSPI_SHADER_USER_ACCUM_PS_1',
|
|
'regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX',
|
|
'regSPI_SHADER_USER_ACCUM_PS_2',
|
|
'regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX',
|
|
'regSPI_SHADER_USER_ACCUM_PS_3',
|
|
'regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_ADDR_HI_GS',
|
|
'regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_ADDR_HI_HS',
|
|
'regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_ADDR_LO_GS',
|
|
'regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_ADDR_LO_HS',
|
|
'regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_0',
|
|
'regSPI_SHADER_USER_DATA_GS_0_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_1', 'regSPI_SHADER_USER_DATA_GS_10',
|
|
'regSPI_SHADER_USER_DATA_GS_10_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_11',
|
|
'regSPI_SHADER_USER_DATA_GS_11_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_12',
|
|
'regSPI_SHADER_USER_DATA_GS_12_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_13',
|
|
'regSPI_SHADER_USER_DATA_GS_13_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_14',
|
|
'regSPI_SHADER_USER_DATA_GS_14_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_15',
|
|
'regSPI_SHADER_USER_DATA_GS_15_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_16',
|
|
'regSPI_SHADER_USER_DATA_GS_16_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_17',
|
|
'regSPI_SHADER_USER_DATA_GS_17_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_18',
|
|
'regSPI_SHADER_USER_DATA_GS_18_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_19',
|
|
'regSPI_SHADER_USER_DATA_GS_19_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_1_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_2', 'regSPI_SHADER_USER_DATA_GS_20',
|
|
'regSPI_SHADER_USER_DATA_GS_20_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_21',
|
|
'regSPI_SHADER_USER_DATA_GS_21_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_22',
|
|
'regSPI_SHADER_USER_DATA_GS_22_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_23',
|
|
'regSPI_SHADER_USER_DATA_GS_23_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_24',
|
|
'regSPI_SHADER_USER_DATA_GS_24_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_25',
|
|
'regSPI_SHADER_USER_DATA_GS_25_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_26',
|
|
'regSPI_SHADER_USER_DATA_GS_26_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_27',
|
|
'regSPI_SHADER_USER_DATA_GS_27_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_28',
|
|
'regSPI_SHADER_USER_DATA_GS_28_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_29',
|
|
'regSPI_SHADER_USER_DATA_GS_29_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_2_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_3', 'regSPI_SHADER_USER_DATA_GS_30',
|
|
'regSPI_SHADER_USER_DATA_GS_30_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_31',
|
|
'regSPI_SHADER_USER_DATA_GS_31_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_3_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_4',
|
|
'regSPI_SHADER_USER_DATA_GS_4_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_5',
|
|
'regSPI_SHADER_USER_DATA_GS_5_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_6',
|
|
'regSPI_SHADER_USER_DATA_GS_6_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_7',
|
|
'regSPI_SHADER_USER_DATA_GS_7_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_8',
|
|
'regSPI_SHADER_USER_DATA_GS_8_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_GS_9',
|
|
'regSPI_SHADER_USER_DATA_GS_9_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_0',
|
|
'regSPI_SHADER_USER_DATA_HS_0_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_1', 'regSPI_SHADER_USER_DATA_HS_10',
|
|
'regSPI_SHADER_USER_DATA_HS_10_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_11',
|
|
'regSPI_SHADER_USER_DATA_HS_11_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_12',
|
|
'regSPI_SHADER_USER_DATA_HS_12_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_13',
|
|
'regSPI_SHADER_USER_DATA_HS_13_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_14',
|
|
'regSPI_SHADER_USER_DATA_HS_14_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_15',
|
|
'regSPI_SHADER_USER_DATA_HS_15_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_16',
|
|
'regSPI_SHADER_USER_DATA_HS_16_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_17',
|
|
'regSPI_SHADER_USER_DATA_HS_17_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_18',
|
|
'regSPI_SHADER_USER_DATA_HS_18_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_19',
|
|
'regSPI_SHADER_USER_DATA_HS_19_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_1_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_2', 'regSPI_SHADER_USER_DATA_HS_20',
|
|
'regSPI_SHADER_USER_DATA_HS_20_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_21',
|
|
'regSPI_SHADER_USER_DATA_HS_21_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_22',
|
|
'regSPI_SHADER_USER_DATA_HS_22_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_23',
|
|
'regSPI_SHADER_USER_DATA_HS_23_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_24',
|
|
'regSPI_SHADER_USER_DATA_HS_24_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_25',
|
|
'regSPI_SHADER_USER_DATA_HS_25_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_26',
|
|
'regSPI_SHADER_USER_DATA_HS_26_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_27',
|
|
'regSPI_SHADER_USER_DATA_HS_27_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_28',
|
|
'regSPI_SHADER_USER_DATA_HS_28_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_29',
|
|
'regSPI_SHADER_USER_DATA_HS_29_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_2_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_3', 'regSPI_SHADER_USER_DATA_HS_30',
|
|
'regSPI_SHADER_USER_DATA_HS_30_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_31',
|
|
'regSPI_SHADER_USER_DATA_HS_31_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_3_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_4',
|
|
'regSPI_SHADER_USER_DATA_HS_4_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_5',
|
|
'regSPI_SHADER_USER_DATA_HS_5_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_6',
|
|
'regSPI_SHADER_USER_DATA_HS_6_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_7',
|
|
'regSPI_SHADER_USER_DATA_HS_7_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_8',
|
|
'regSPI_SHADER_USER_DATA_HS_8_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_HS_9',
|
|
'regSPI_SHADER_USER_DATA_HS_9_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_0',
|
|
'regSPI_SHADER_USER_DATA_PS_0_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_1', 'regSPI_SHADER_USER_DATA_PS_10',
|
|
'regSPI_SHADER_USER_DATA_PS_10_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_11',
|
|
'regSPI_SHADER_USER_DATA_PS_11_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_12',
|
|
'regSPI_SHADER_USER_DATA_PS_12_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_13',
|
|
'regSPI_SHADER_USER_DATA_PS_13_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_14',
|
|
'regSPI_SHADER_USER_DATA_PS_14_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_15',
|
|
'regSPI_SHADER_USER_DATA_PS_15_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_16',
|
|
'regSPI_SHADER_USER_DATA_PS_16_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_17',
|
|
'regSPI_SHADER_USER_DATA_PS_17_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_18',
|
|
'regSPI_SHADER_USER_DATA_PS_18_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_19',
|
|
'regSPI_SHADER_USER_DATA_PS_19_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_1_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_2', 'regSPI_SHADER_USER_DATA_PS_20',
|
|
'regSPI_SHADER_USER_DATA_PS_20_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_21',
|
|
'regSPI_SHADER_USER_DATA_PS_21_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_22',
|
|
'regSPI_SHADER_USER_DATA_PS_22_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_23',
|
|
'regSPI_SHADER_USER_DATA_PS_23_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_24',
|
|
'regSPI_SHADER_USER_DATA_PS_24_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_25',
|
|
'regSPI_SHADER_USER_DATA_PS_25_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_26',
|
|
'regSPI_SHADER_USER_DATA_PS_26_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_27',
|
|
'regSPI_SHADER_USER_DATA_PS_27_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_28',
|
|
'regSPI_SHADER_USER_DATA_PS_28_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_29',
|
|
'regSPI_SHADER_USER_DATA_PS_29_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_2_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_3', 'regSPI_SHADER_USER_DATA_PS_30',
|
|
'regSPI_SHADER_USER_DATA_PS_30_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_31',
|
|
'regSPI_SHADER_USER_DATA_PS_31_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_3_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_4',
|
|
'regSPI_SHADER_USER_DATA_PS_4_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_5',
|
|
'regSPI_SHADER_USER_DATA_PS_5_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_6',
|
|
'regSPI_SHADER_USER_DATA_PS_6_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_7',
|
|
'regSPI_SHADER_USER_DATA_PS_7_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_8',
|
|
'regSPI_SHADER_USER_DATA_PS_8_BASE_IDX',
|
|
'regSPI_SHADER_USER_DATA_PS_9',
|
|
'regSPI_SHADER_USER_DATA_PS_9_BASE_IDX', 'regSPI_SHADER_Z_FORMAT',
|
|
'regSPI_SHADER_Z_FORMAT_BASE_IDX',
|
|
'regSPI_SX_EXPORT_BUFFER_SIZES',
|
|
'regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX',
|
|
'regSPI_SX_SCOREBOARD_BUFFER_SIZES',
|
|
'regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX',
|
|
'regSPI_TMPRING_SIZE', 'regSPI_TMPRING_SIZE_BASE_IDX',
|
|
'regSPI_USER_ACCUM_VMID_CNTL',
|
|
'regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX', 'regSPI_VS_OUT_CONFIG',
|
|
'regSPI_VS_OUT_CONFIG_BASE_IDX', 'regSPI_WAVE_LIMIT_CNTL',
|
|
'regSPI_WAVE_LIMIT_CNTL_BASE_IDX', 'regSPI_WCL_PIPE_PERCENT_CS0',
|
|
'regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX',
|
|
'regSPI_WCL_PIPE_PERCENT_CS1',
|
|
'regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX',
|
|
'regSPI_WCL_PIPE_PERCENT_CS2',
|
|
'regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX',
|
|
'regSPI_WCL_PIPE_PERCENT_CS3',
|
|
'regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX',
|
|
'regSPI_WCL_PIPE_PERCENT_CS4',
|
|
'regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX',
|
|
'regSPI_WCL_PIPE_PERCENT_CS5',
|
|
'regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX',
|
|
'regSPI_WCL_PIPE_PERCENT_CS6',
|
|
'regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX',
|
|
'regSPI_WCL_PIPE_PERCENT_CS7',
|
|
'regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX',
|
|
'regSPI_WCL_PIPE_PERCENT_GFX',
|
|
'regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX',
|
|
'regSPI_WCL_PIPE_PERCENT_HP3D',
|
|
'regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_CNTL', 'regSPI_WF_LIFETIME_CNTL_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_LIMIT_0',
|
|
'regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_LIMIT_1',
|
|
'regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_LIMIT_2',
|
|
'regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_LIMIT_3',
|
|
'regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_LIMIT_4',
|
|
'regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_LIMIT_5',
|
|
'regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_0',
|
|
'regSPI_WF_LIFETIME_STATUS_0_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_11',
|
|
'regSPI_WF_LIFETIME_STATUS_11_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_13',
|
|
'regSPI_WF_LIFETIME_STATUS_13_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_14',
|
|
'regSPI_WF_LIFETIME_STATUS_14_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_15',
|
|
'regSPI_WF_LIFETIME_STATUS_15_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_16',
|
|
'regSPI_WF_LIFETIME_STATUS_16_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_17',
|
|
'regSPI_WF_LIFETIME_STATUS_17_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_18',
|
|
'regSPI_WF_LIFETIME_STATUS_18_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_19',
|
|
'regSPI_WF_LIFETIME_STATUS_19_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_2', 'regSPI_WF_LIFETIME_STATUS_20',
|
|
'regSPI_WF_LIFETIME_STATUS_20_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_21',
|
|
'regSPI_WF_LIFETIME_STATUS_21_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_2_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_4',
|
|
'regSPI_WF_LIFETIME_STATUS_4_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_6',
|
|
'regSPI_WF_LIFETIME_STATUS_6_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_7',
|
|
'regSPI_WF_LIFETIME_STATUS_7_BASE_IDX',
|
|
'regSPI_WF_LIFETIME_STATUS_9',
|
|
'regSPI_WF_LIFETIME_STATUS_9_BASE_IDX', 'regSP_CONFIG',
|
|
'regSP_CONFIG_BASE_IDX', 'regSQC_CACHES',
|
|
'regSQC_CACHES_BASE_IDX', 'regSQC_CONFIG',
|
|
'regSQC_CONFIG_BASE_IDX', 'regSQG_CONFIG',
|
|
'regSQG_CONFIG_BASE_IDX', 'regSQG_GL1H_STATUS',
|
|
'regSQG_GL1H_STATUS_BASE_IDX', 'regSQG_PERFCOUNTER0_HI',
|
|
'regSQG_PERFCOUNTER0_HI_BASE_IDX', 'regSQG_PERFCOUNTER0_LO',
|
|
'regSQG_PERFCOUNTER0_LO_BASE_IDX', 'regSQG_PERFCOUNTER0_SELECT',
|
|
'regSQG_PERFCOUNTER0_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER1_HI',
|
|
'regSQG_PERFCOUNTER1_HI_BASE_IDX', 'regSQG_PERFCOUNTER1_LO',
|
|
'regSQG_PERFCOUNTER1_LO_BASE_IDX', 'regSQG_PERFCOUNTER1_SELECT',
|
|
'regSQG_PERFCOUNTER1_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER2_HI',
|
|
'regSQG_PERFCOUNTER2_HI_BASE_IDX', 'regSQG_PERFCOUNTER2_LO',
|
|
'regSQG_PERFCOUNTER2_LO_BASE_IDX', 'regSQG_PERFCOUNTER2_SELECT',
|
|
'regSQG_PERFCOUNTER2_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER3_HI',
|
|
'regSQG_PERFCOUNTER3_HI_BASE_IDX', 'regSQG_PERFCOUNTER3_LO',
|
|
'regSQG_PERFCOUNTER3_LO_BASE_IDX', 'regSQG_PERFCOUNTER3_SELECT',
|
|
'regSQG_PERFCOUNTER3_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER4_HI',
|
|
'regSQG_PERFCOUNTER4_HI_BASE_IDX', 'regSQG_PERFCOUNTER4_LO',
|
|
'regSQG_PERFCOUNTER4_LO_BASE_IDX', 'regSQG_PERFCOUNTER4_SELECT',
|
|
'regSQG_PERFCOUNTER4_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER5_HI',
|
|
'regSQG_PERFCOUNTER5_HI_BASE_IDX', 'regSQG_PERFCOUNTER5_LO',
|
|
'regSQG_PERFCOUNTER5_LO_BASE_IDX', 'regSQG_PERFCOUNTER5_SELECT',
|
|
'regSQG_PERFCOUNTER5_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER6_HI',
|
|
'regSQG_PERFCOUNTER6_HI_BASE_IDX', 'regSQG_PERFCOUNTER6_LO',
|
|
'regSQG_PERFCOUNTER6_LO_BASE_IDX', 'regSQG_PERFCOUNTER6_SELECT',
|
|
'regSQG_PERFCOUNTER6_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER7_HI',
|
|
'regSQG_PERFCOUNTER7_HI_BASE_IDX', 'regSQG_PERFCOUNTER7_LO',
|
|
'regSQG_PERFCOUNTER7_LO_BASE_IDX', 'regSQG_PERFCOUNTER7_SELECT',
|
|
'regSQG_PERFCOUNTER7_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER_CTRL',
|
|
'regSQG_PERFCOUNTER_CTRL2', 'regSQG_PERFCOUNTER_CTRL2_BASE_IDX',
|
|
'regSQG_PERFCOUNTER_CTRL_BASE_IDX', 'regSQG_PERF_SAMPLE_FINISH',
|
|
'regSQG_PERF_SAMPLE_FINISH_BASE_IDX', 'regSQG_STATUS',
|
|
'regSQG_STATUS_BASE_IDX', 'regSQ_ALU_CLK_CTRL',
|
|
'regSQ_ALU_CLK_CTRL_BASE_IDX', 'regSQ_ARB_CONFIG',
|
|
'regSQ_ARB_CONFIG_BASE_IDX', 'regSQ_CMD', 'regSQ_CMD_BASE_IDX',
|
|
'regSQ_CONFIG', 'regSQ_CONFIG_BASE_IDX', 'regSQ_DEBUG',
|
|
'regSQ_DEBUG_BASE_IDX', 'regSQ_DEBUG_HOST_TRAP_STATUS',
|
|
'regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX', 'regSQ_DEBUG_STS_GLOBAL',
|
|
'regSQ_DEBUG_STS_GLOBAL2', 'regSQ_DEBUG_STS_GLOBAL2_BASE_IDX',
|
|
'regSQ_DEBUG_STS_GLOBAL_BASE_IDX', 'regSQ_DSM_CNTL',
|
|
'regSQ_DSM_CNTL2', 'regSQ_DSM_CNTL2_BASE_IDX',
|
|
'regSQ_DSM_CNTL_BASE_IDX', 'regSQ_FIFO_SIZES',
|
|
'regSQ_FIFO_SIZES_BASE_IDX', 'regSQ_IND_DATA',
|
|
'regSQ_IND_DATA_BASE_IDX', 'regSQ_IND_INDEX',
|
|
'regSQ_IND_INDEX_BASE_IDX', 'regSQ_INTERRUPT_AUTO_MASK',
|
|
'regSQ_INTERRUPT_AUTO_MASK_BASE_IDX', 'regSQ_INTERRUPT_MSG_CTRL',
|
|
'regSQ_INTERRUPT_MSG_CTRL_BASE_IDX', 'regSQ_LDS_CLK_CTRL',
|
|
'regSQ_LDS_CLK_CTRL_BASE_IDX', 'regSQ_PERFCOUNTER0_LO',
|
|
'regSQ_PERFCOUNTER0_LO_BASE_IDX', 'regSQ_PERFCOUNTER0_SELECT',
|
|
'regSQ_PERFCOUNTER0_SELECT_BASE_IDX',
|
|
'regSQ_PERFCOUNTER10_SELECT',
|
|
'regSQ_PERFCOUNTER10_SELECT_BASE_IDX',
|
|
'regSQ_PERFCOUNTER11_SELECT',
|
|
'regSQ_PERFCOUNTER11_SELECT_BASE_IDX',
|
|
'regSQ_PERFCOUNTER12_SELECT',
|
|
'regSQ_PERFCOUNTER12_SELECT_BASE_IDX',
|
|
'regSQ_PERFCOUNTER13_SELECT',
|
|
'regSQ_PERFCOUNTER13_SELECT_BASE_IDX',
|
|
'regSQ_PERFCOUNTER14_SELECT',
|
|
'regSQ_PERFCOUNTER14_SELECT_BASE_IDX',
|
|
'regSQ_PERFCOUNTER15_SELECT',
|
|
'regSQ_PERFCOUNTER15_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER1_LO',
|
|
'regSQ_PERFCOUNTER1_LO_BASE_IDX', 'regSQ_PERFCOUNTER1_SELECT',
|
|
'regSQ_PERFCOUNTER1_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER2_LO',
|
|
'regSQ_PERFCOUNTER2_LO_BASE_IDX', 'regSQ_PERFCOUNTER2_SELECT',
|
|
'regSQ_PERFCOUNTER2_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER3_LO',
|
|
'regSQ_PERFCOUNTER3_LO_BASE_IDX', 'regSQ_PERFCOUNTER3_SELECT',
|
|
'regSQ_PERFCOUNTER3_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER4_LO',
|
|
'regSQ_PERFCOUNTER4_LO_BASE_IDX', 'regSQ_PERFCOUNTER4_SELECT',
|
|
'regSQ_PERFCOUNTER4_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER5_LO',
|
|
'regSQ_PERFCOUNTER5_LO_BASE_IDX', 'regSQ_PERFCOUNTER5_SELECT',
|
|
'regSQ_PERFCOUNTER5_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER6_LO',
|
|
'regSQ_PERFCOUNTER6_LO_BASE_IDX', 'regSQ_PERFCOUNTER6_SELECT',
|
|
'regSQ_PERFCOUNTER6_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER7_LO',
|
|
'regSQ_PERFCOUNTER7_LO_BASE_IDX', 'regSQ_PERFCOUNTER7_SELECT',
|
|
'regSQ_PERFCOUNTER7_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER8_SELECT',
|
|
'regSQ_PERFCOUNTER8_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER9_SELECT',
|
|
'regSQ_PERFCOUNTER9_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER_CTRL',
|
|
'regSQ_PERFCOUNTER_CTRL2', 'regSQ_PERFCOUNTER_CTRL2_BASE_IDX',
|
|
'regSQ_PERFCOUNTER_CTRL_BASE_IDX', 'regSQ_PERF_SNAPSHOT_CTRL',
|
|
'regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX', 'regSQ_RANDOM_WAVE_PRI',
|
|
'regSQ_RANDOM_WAVE_PRI_BASE_IDX', 'regSQ_RUNTIME_CONFIG',
|
|
'regSQ_RUNTIME_CONFIG_BASE_IDX', 'regSQ_SHADER_TBA_HI',
|
|
'regSQ_SHADER_TBA_HI_BASE_IDX', 'regSQ_SHADER_TBA_LO',
|
|
'regSQ_SHADER_TBA_LO_BASE_IDX', 'regSQ_SHADER_TMA_HI',
|
|
'regSQ_SHADER_TMA_HI_BASE_IDX', 'regSQ_SHADER_TMA_LO',
|
|
'regSQ_SHADER_TMA_LO_BASE_IDX', 'regSQ_TEX_CLK_CTRL',
|
|
'regSQ_TEX_CLK_CTRL_BASE_IDX', 'regSQ_THREAD_TRACE_BUF0_BASE',
|
|
'regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_BUF0_SIZE',
|
|
'regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_BUF1_BASE',
|
|
'regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_BUF1_SIZE',
|
|
'regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_CTRL', 'regSQ_THREAD_TRACE_CTRL_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_DROPPED_CNTR',
|
|
'regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_GFX_DRAW_CNTR',
|
|
'regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_GFX_MARKER_CNTR',
|
|
'regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_HP3D_DRAW_CNTR',
|
|
'regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_HP3D_MARKER_CNTR',
|
|
'regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_MASK', 'regSQ_THREAD_TRACE_MASK_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_STATUS', 'regSQ_THREAD_TRACE_STATUS2',
|
|
'regSQ_THREAD_TRACE_STATUS2_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_STATUS_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_TOKEN_MASK',
|
|
'regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_USERDATA_0',
|
|
'regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_USERDATA_1',
|
|
'regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_USERDATA_2',
|
|
'regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_USERDATA_3',
|
|
'regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_USERDATA_4',
|
|
'regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_USERDATA_5',
|
|
'regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_USERDATA_6',
|
|
'regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_USERDATA_7',
|
|
'regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX',
|
|
'regSQ_THREAD_TRACE_WPTR', 'regSQ_THREAD_TRACE_WPTR_BASE_IDX',
|
|
'regSQ_WATCH0_ADDR_H', 'regSQ_WATCH0_ADDR_H_BASE_IDX',
|
|
'regSQ_WATCH0_ADDR_L', 'regSQ_WATCH0_ADDR_L_BASE_IDX',
|
|
'regSQ_WATCH0_CNTL', 'regSQ_WATCH0_CNTL_BASE_IDX',
|
|
'regSQ_WATCH1_ADDR_H', 'regSQ_WATCH1_ADDR_H_BASE_IDX',
|
|
'regSQ_WATCH1_ADDR_L', 'regSQ_WATCH1_ADDR_L_BASE_IDX',
|
|
'regSQ_WATCH1_CNTL', 'regSQ_WATCH1_CNTL_BASE_IDX',
|
|
'regSQ_WATCH2_ADDR_H', 'regSQ_WATCH2_ADDR_H_BASE_IDX',
|
|
'regSQ_WATCH2_ADDR_L', 'regSQ_WATCH2_ADDR_L_BASE_IDX',
|
|
'regSQ_WATCH2_CNTL', 'regSQ_WATCH2_CNTL_BASE_IDX',
|
|
'regSQ_WATCH3_ADDR_H', 'regSQ_WATCH3_ADDR_H_BASE_IDX',
|
|
'regSQ_WATCH3_ADDR_L', 'regSQ_WATCH3_ADDR_L_BASE_IDX',
|
|
'regSQ_WATCH3_CNTL', 'regSQ_WATCH3_CNTL_BASE_IDX',
|
|
'regSX_BLEND_OPT_CONTROL', 'regSX_BLEND_OPT_CONTROL_BASE_IDX',
|
|
'regSX_BLEND_OPT_EPSILON', 'regSX_BLEND_OPT_EPSILON_BASE_IDX',
|
|
'regSX_DEBUG_1', 'regSX_DEBUG_1_BASE_IDX', 'regSX_MRT0_BLEND_OPT',
|
|
'regSX_MRT0_BLEND_OPT_BASE_IDX', 'regSX_MRT1_BLEND_OPT',
|
|
'regSX_MRT1_BLEND_OPT_BASE_IDX', 'regSX_MRT2_BLEND_OPT',
|
|
'regSX_MRT2_BLEND_OPT_BASE_IDX', 'regSX_MRT3_BLEND_OPT',
|
|
'regSX_MRT3_BLEND_OPT_BASE_IDX', 'regSX_MRT4_BLEND_OPT',
|
|
'regSX_MRT4_BLEND_OPT_BASE_IDX', 'regSX_MRT5_BLEND_OPT',
|
|
'regSX_MRT5_BLEND_OPT_BASE_IDX', 'regSX_MRT6_BLEND_OPT',
|
|
'regSX_MRT6_BLEND_OPT_BASE_IDX', 'regSX_MRT7_BLEND_OPT',
|
|
'regSX_MRT7_BLEND_OPT_BASE_IDX', 'regSX_PERFCOUNTER0_HI',
|
|
'regSX_PERFCOUNTER0_HI_BASE_IDX', 'regSX_PERFCOUNTER0_LO',
|
|
'regSX_PERFCOUNTER0_LO_BASE_IDX', 'regSX_PERFCOUNTER0_SELECT',
|
|
'regSX_PERFCOUNTER0_SELECT1',
|
|
'regSX_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regSX_PERFCOUNTER0_SELECT_BASE_IDX', 'regSX_PERFCOUNTER1_HI',
|
|
'regSX_PERFCOUNTER1_HI_BASE_IDX', 'regSX_PERFCOUNTER1_LO',
|
|
'regSX_PERFCOUNTER1_LO_BASE_IDX', 'regSX_PERFCOUNTER1_SELECT',
|
|
'regSX_PERFCOUNTER1_SELECT1',
|
|
'regSX_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regSX_PERFCOUNTER1_SELECT_BASE_IDX', 'regSX_PERFCOUNTER2_HI',
|
|
'regSX_PERFCOUNTER2_HI_BASE_IDX', 'regSX_PERFCOUNTER2_LO',
|
|
'regSX_PERFCOUNTER2_LO_BASE_IDX', 'regSX_PERFCOUNTER2_SELECT',
|
|
'regSX_PERFCOUNTER2_SELECT_BASE_IDX', 'regSX_PERFCOUNTER3_HI',
|
|
'regSX_PERFCOUNTER3_HI_BASE_IDX', 'regSX_PERFCOUNTER3_LO',
|
|
'regSX_PERFCOUNTER3_LO_BASE_IDX', 'regSX_PERFCOUNTER3_SELECT',
|
|
'regSX_PERFCOUNTER3_SELECT_BASE_IDX', 'regSX_PS_DOWNCONVERT',
|
|
'regSX_PS_DOWNCONVERT_BASE_IDX', 'regSX_PS_DOWNCONVERT_CONTROL',
|
|
'regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX', 'regTA_BC_BASE_ADDR',
|
|
'regTA_BC_BASE_ADDR_BASE_IDX', 'regTA_BC_BASE_ADDR_HI',
|
|
'regTA_BC_BASE_ADDR_HI_BASE_IDX', 'regTA_CGTT_CTRL',
|
|
'regTA_CGTT_CTRL_BASE_IDX', 'regTA_CNTL', 'regTA_CNTL2',
|
|
'regTA_CNTL2_BASE_IDX', 'regTA_CNTL_AUX',
|
|
'regTA_CNTL_AUX_BASE_IDX', 'regTA_CNTL_BASE_IDX',
|
|
'regTA_CS_BC_BASE_ADDR', 'regTA_CS_BC_BASE_ADDR_BASE_IDX',
|
|
'regTA_CS_BC_BASE_ADDR_HI', 'regTA_CS_BC_BASE_ADDR_HI_BASE_IDX',
|
|
'regTA_PERFCOUNTER0_HI', 'regTA_PERFCOUNTER0_HI_BASE_IDX',
|
|
'regTA_PERFCOUNTER0_LO', 'regTA_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regTA_PERFCOUNTER0_SELECT', 'regTA_PERFCOUNTER0_SELECT1',
|
|
'regTA_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regTA_PERFCOUNTER0_SELECT_BASE_IDX', 'regTA_PERFCOUNTER1_HI',
|
|
'regTA_PERFCOUNTER1_HI_BASE_IDX', 'regTA_PERFCOUNTER1_LO',
|
|
'regTA_PERFCOUNTER1_LO_BASE_IDX', 'regTA_PERFCOUNTER1_SELECT',
|
|
'regTA_PERFCOUNTER1_SELECT_BASE_IDX', 'regTA_SCRATCH',
|
|
'regTA_SCRATCH_BASE_IDX', 'regTA_STATUS', 'regTA_STATUS_BASE_IDX',
|
|
'regTCP_CNTL', 'regTCP_CNTL2', 'regTCP_CNTL2_BASE_IDX',
|
|
'regTCP_CNTL_BASE_IDX', 'regTCP_DEBUG_DATA',
|
|
'regTCP_DEBUG_DATA_BASE_IDX', 'regTCP_DEBUG_INDEX',
|
|
'regTCP_DEBUG_INDEX_BASE_IDX', 'regTCP_INVALIDATE',
|
|
'regTCP_INVALIDATE_BASE_IDX', 'regTCP_PERFCOUNTER0_HI',
|
|
'regTCP_PERFCOUNTER0_HI_BASE_IDX', 'regTCP_PERFCOUNTER0_LO',
|
|
'regTCP_PERFCOUNTER0_LO_BASE_IDX', 'regTCP_PERFCOUNTER0_SELECT',
|
|
'regTCP_PERFCOUNTER0_SELECT1',
|
|
'regTCP_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regTCP_PERFCOUNTER0_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER1_HI',
|
|
'regTCP_PERFCOUNTER1_HI_BASE_IDX', 'regTCP_PERFCOUNTER1_LO',
|
|
'regTCP_PERFCOUNTER1_LO_BASE_IDX', 'regTCP_PERFCOUNTER1_SELECT',
|
|
'regTCP_PERFCOUNTER1_SELECT1',
|
|
'regTCP_PERFCOUNTER1_SELECT1_BASE_IDX',
|
|
'regTCP_PERFCOUNTER1_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER2_HI',
|
|
'regTCP_PERFCOUNTER2_HI_BASE_IDX', 'regTCP_PERFCOUNTER2_LO',
|
|
'regTCP_PERFCOUNTER2_LO_BASE_IDX', 'regTCP_PERFCOUNTER2_SELECT',
|
|
'regTCP_PERFCOUNTER2_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER3_HI',
|
|
'regTCP_PERFCOUNTER3_HI_BASE_IDX', 'regTCP_PERFCOUNTER3_LO',
|
|
'regTCP_PERFCOUNTER3_LO_BASE_IDX', 'regTCP_PERFCOUNTER3_SELECT',
|
|
'regTCP_PERFCOUNTER3_SELECT_BASE_IDX',
|
|
'regTCP_PERFCOUNTER_FILTER', 'regTCP_PERFCOUNTER_FILTER2',
|
|
'regTCP_PERFCOUNTER_FILTER2_BASE_IDX',
|
|
'regTCP_PERFCOUNTER_FILTER_BASE_IDX',
|
|
'regTCP_PERFCOUNTER_FILTER_EN',
|
|
'regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX', 'regTCP_STATUS',
|
|
'regTCP_STATUS_BASE_IDX', 'regTCP_WATCH0_ADDR_H',
|
|
'regTCP_WATCH0_ADDR_H_BASE_IDX', 'regTCP_WATCH0_ADDR_L',
|
|
'regTCP_WATCH0_ADDR_L_BASE_IDX', 'regTCP_WATCH0_CNTL',
|
|
'regTCP_WATCH0_CNTL_BASE_IDX', 'regTCP_WATCH1_ADDR_H',
|
|
'regTCP_WATCH1_ADDR_H_BASE_IDX', 'regTCP_WATCH1_ADDR_L',
|
|
'regTCP_WATCH1_ADDR_L_BASE_IDX', 'regTCP_WATCH1_CNTL',
|
|
'regTCP_WATCH1_CNTL_BASE_IDX', 'regTCP_WATCH2_ADDR_H',
|
|
'regTCP_WATCH2_ADDR_H_BASE_IDX', 'regTCP_WATCH2_ADDR_L',
|
|
'regTCP_WATCH2_ADDR_L_BASE_IDX', 'regTCP_WATCH2_CNTL',
|
|
'regTCP_WATCH2_CNTL_BASE_IDX', 'regTCP_WATCH3_ADDR_H',
|
|
'regTCP_WATCH3_ADDR_H_BASE_IDX', 'regTCP_WATCH3_ADDR_L',
|
|
'regTCP_WATCH3_ADDR_L_BASE_IDX', 'regTCP_WATCH3_CNTL',
|
|
'regTCP_WATCH3_CNTL_BASE_IDX', 'regTD_DSM_CNTL',
|
|
'regTD_DSM_CNTL2', 'regTD_DSM_CNTL2_BASE_IDX',
|
|
'regTD_DSM_CNTL_BASE_IDX', 'regTD_PERFCOUNTER0_HI',
|
|
'regTD_PERFCOUNTER0_HI_BASE_IDX', 'regTD_PERFCOUNTER0_LO',
|
|
'regTD_PERFCOUNTER0_LO_BASE_IDX', 'regTD_PERFCOUNTER0_SELECT',
|
|
'regTD_PERFCOUNTER0_SELECT1',
|
|
'regTD_PERFCOUNTER0_SELECT1_BASE_IDX',
|
|
'regTD_PERFCOUNTER0_SELECT_BASE_IDX', 'regTD_PERFCOUNTER1_HI',
|
|
'regTD_PERFCOUNTER1_HI_BASE_IDX', 'regTD_PERFCOUNTER1_LO',
|
|
'regTD_PERFCOUNTER1_LO_BASE_IDX', 'regTD_PERFCOUNTER1_SELECT',
|
|
'regTD_PERFCOUNTER1_SELECT_BASE_IDX', 'regTD_SCRATCH',
|
|
'regTD_SCRATCH_BASE_IDX', 'regTD_STATUS', 'regTD_STATUS_BASE_IDX',
|
|
'regUCONFIG_RESERVED_REG0', 'regUCONFIG_RESERVED_REG0_BASE_IDX',
|
|
'regUCONFIG_RESERVED_REG1', 'regUCONFIG_RESERVED_REG1_BASE_IDX',
|
|
'regUTCL1_ALOG', 'regUTCL1_ALOG_BASE_IDX', 'regUTCL1_CTRL_0',
|
|
'regUTCL1_CTRL_0_BASE_IDX', 'regUTCL1_CTRL_1',
|
|
'regUTCL1_CTRL_1_BASE_IDX', 'regUTCL1_CTRL_2',
|
|
'regUTCL1_CTRL_2_BASE_IDX', 'regUTCL1_FIFO_SIZING',
|
|
'regUTCL1_FIFO_SIZING_BASE_IDX', 'regUTCL1_PERFCOUNTER0_HI',
|
|
'regUTCL1_PERFCOUNTER0_HI_BASE_IDX', 'regUTCL1_PERFCOUNTER0_LO',
|
|
'regUTCL1_PERFCOUNTER0_LO_BASE_IDX',
|
|
'regUTCL1_PERFCOUNTER0_SELECT',
|
|
'regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX',
|
|
'regUTCL1_PERFCOUNTER1_HI', 'regUTCL1_PERFCOUNTER1_HI_BASE_IDX',
|
|
'regUTCL1_PERFCOUNTER1_LO', 'regUTCL1_PERFCOUNTER1_LO_BASE_IDX',
|
|
'regUTCL1_PERFCOUNTER1_SELECT',
|
|
'regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX',
|
|
'regUTCL1_PERFCOUNTER2_HI', 'regUTCL1_PERFCOUNTER2_HI_BASE_IDX',
|
|
'regUTCL1_PERFCOUNTER2_LO', 'regUTCL1_PERFCOUNTER2_LO_BASE_IDX',
|
|
'regUTCL1_PERFCOUNTER2_SELECT',
|
|
'regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX',
|
|
'regUTCL1_PERFCOUNTER3_HI', 'regUTCL1_PERFCOUNTER3_HI_BASE_IDX',
|
|
'regUTCL1_PERFCOUNTER3_LO', 'regUTCL1_PERFCOUNTER3_LO_BASE_IDX',
|
|
'regUTCL1_PERFCOUNTER3_SELECT',
|
|
'regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX', 'regUTCL1_STATUS',
|
|
'regUTCL1_STATUS_BASE_IDX', 'regUTCL1_UTCL0_INVREQ_DISABLE',
|
|
'regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX', 'regVGT_DMA_BASE',
|
|
'regVGT_DMA_BASE_BASE_IDX', 'regVGT_DMA_BASE_HI',
|
|
'regVGT_DMA_BASE_HI_BASE_IDX', 'regVGT_DMA_DATA_FIFO_DEPTH',
|
|
'regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX', 'regVGT_DMA_INDEX_TYPE',
|
|
'regVGT_DMA_INDEX_TYPE_BASE_IDX', 'regVGT_DMA_MAX_SIZE',
|
|
'regVGT_DMA_MAX_SIZE_BASE_IDX', 'regVGT_DMA_NUM_INSTANCES',
|
|
'regVGT_DMA_NUM_INSTANCES_BASE_IDX', 'regVGT_DMA_REQ_FIFO_DEPTH',
|
|
'regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX', 'regVGT_DMA_SIZE',
|
|
'regVGT_DMA_SIZE_BASE_IDX', 'regVGT_DRAW_INITIATOR',
|
|
'regVGT_DRAW_INITIATOR_BASE_IDX', 'regVGT_DRAW_INIT_FIFO_DEPTH',
|
|
'regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX',
|
|
'regVGT_DRAW_PAYLOAD_CNTL', 'regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX',
|
|
'regVGT_ENHANCE', 'regVGT_ENHANCE_BASE_IDX',
|
|
'regVGT_ESGS_RING_ITEMSIZE', 'regVGT_ESGS_RING_ITEMSIZE_BASE_IDX',
|
|
'regVGT_EVENT_ADDRESS_REG', 'regVGT_EVENT_ADDRESS_REG_BASE_IDX',
|
|
'regVGT_EVENT_INITIATOR', 'regVGT_EVENT_INITIATOR_BASE_IDX',
|
|
'regVGT_GS_INSTANCE_CNT', 'regVGT_GS_INSTANCE_CNT_BASE_IDX',
|
|
'regVGT_GS_MAX_VERT_OUT', 'regVGT_GS_MAX_VERT_OUT_BASE_IDX',
|
|
'regVGT_GS_MAX_WAVE_ID', 'regVGT_GS_MAX_WAVE_ID_BASE_IDX',
|
|
'regVGT_GS_OUT_PRIM_TYPE', 'regVGT_GS_OUT_PRIM_TYPE_BASE_IDX',
|
|
'regVGT_HOS_MAX_TESS_LEVEL', 'regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX',
|
|
'regVGT_HOS_MIN_TESS_LEVEL', 'regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX',
|
|
'regVGT_HS_OFFCHIP_PARAM', 'regVGT_HS_OFFCHIP_PARAM_BASE_IDX',
|
|
'regVGT_INDEX_TYPE', 'regVGT_INDEX_TYPE_BASE_IDX',
|
|
'regVGT_INSTANCE_BASE_ID', 'regVGT_INSTANCE_BASE_ID_BASE_IDX',
|
|
'regVGT_LS_HS_CONFIG', 'regVGT_LS_HS_CONFIG_BASE_IDX',
|
|
'regVGT_MC_LAT_CNTL', 'regVGT_MC_LAT_CNTL_BASE_IDX',
|
|
'regVGT_MULTI_PRIM_IB_RESET_INDX',
|
|
'regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX', 'regVGT_NUM_INDICES',
|
|
'regVGT_NUM_INDICES_BASE_IDX', 'regVGT_NUM_INSTANCES',
|
|
'regVGT_NUM_INSTANCES_BASE_IDX', 'regVGT_PRIMITIVEID_EN',
|
|
'regVGT_PRIMITIVEID_EN_BASE_IDX', 'regVGT_PRIMITIVEID_RESET',
|
|
'regVGT_PRIMITIVEID_RESET_BASE_IDX', 'regVGT_PRIMITIVE_TYPE',
|
|
'regVGT_PRIMITIVE_TYPE_BASE_IDX', 'regVGT_REUSE_OFF',
|
|
'regVGT_REUSE_OFF_BASE_IDX', 'regVGT_SHADER_STAGES_EN',
|
|
'regVGT_SHADER_STAGES_EN_BASE_IDX',
|
|
'regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE',
|
|
'regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX',
|
|
'regVGT_STRMOUT_DRAW_OPAQUE_OFFSET',
|
|
'regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX',
|
|
'regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE',
|
|
'regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX',
|
|
'regVGT_SYS_CONFIG', 'regVGT_SYS_CONFIG_BASE_IDX',
|
|
'regVGT_TESS_DISTRIBUTION', 'regVGT_TESS_DISTRIBUTION_BASE_IDX',
|
|
'regVGT_TF_MEMORY_BASE', 'regVGT_TF_MEMORY_BASE_BASE_IDX',
|
|
'regVGT_TF_MEMORY_BASE_HI', 'regVGT_TF_MEMORY_BASE_HI_BASE_IDX',
|
|
'regVGT_TF_PARAM', 'regVGT_TF_PARAM_BASE_IDX',
|
|
'regVGT_TF_RING_SIZE', 'regVGT_TF_RING_SIZE_BASE_IDX',
|
|
'regVIOLATION_DATA_ASYNC_VF_PROG',
|
|
'regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX', 'regWD_CNTL_STATUS',
|
|
'regWD_CNTL_STATUS_BASE_IDX', 'regWD_ENHANCE',
|
|
'regWD_ENHANCE_BASE_IDX', 'regWD_QOS', 'regWD_QOS_BASE_IDX',
|
|
'regWD_UTCL1_CNTL', 'regWD_UTCL1_CNTL_BASE_IDX',
|
|
'regWD_UTCL1_STATUS', 'regWD_UTCL1_STATUS_BASE_IDX',
|
|
'struct_IP_BASE', 'struct_IP_BASE_INSTANCE',
|
|
'struct_SDMA_PKT_ATOMIC_TAG', 'struct_SDMA_PKT_ATOMIC_TAG_0_0',
|
|
'struct_SDMA_PKT_ATOMIC_TAG_1_0',
|
|
'struct_SDMA_PKT_ATOMIC_TAG_2_0',
|
|
'struct_SDMA_PKT_ATOMIC_TAG_3_0',
|
|
'struct_SDMA_PKT_ATOMIC_TAG_4_0',
|
|
'struct_SDMA_PKT_ATOMIC_TAG_5_0',
|
|
'struct_SDMA_PKT_ATOMIC_TAG_6_0',
|
|
'struct_SDMA_PKT_ATOMIC_TAG_7_0',
|
|
'struct_SDMA_PKT_CONSTANT_FILL_TAG',
|
|
'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0',
|
|
'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0',
|
|
'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0',
|
|
'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0',
|
|
'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_TAG',
|
|
'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0',
|
|
'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0',
|
|
'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0',
|
|
'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0',
|
|
'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG',
|
|
'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0',
|
|
'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0',
|
|
'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG',
|
|
'struct_SDMA_PKT_POLL_REGMEM_TAG',
|
|
'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0',
|
|
'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0',
|
|
'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0',
|
|
'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0',
|
|
'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0',
|
|
'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0',
|
|
'struct_SDMA_PKT_TIMESTAMP_TAG',
|
|
'struct_SDMA_PKT_TIMESTAMP_TAG_0_0',
|
|
'struct_SDMA_PKT_TIMESTAMP_TAG_1_0',
|
|
'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG',
|
|
'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0',
|
|
'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION',
|
|
'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION',
|
|
'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION',
|
|
'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION',
|
|
'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION',
|
|
'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION',
|
|
'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION',
|
|
'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION',
|
|
'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION',
|
|
'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION',
|
|
'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION',
|
|
'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION',
|
|
'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION',
|
|
'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION',
|
|
'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION',
|
|
'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION',
|
|
'union_SDMA_PKT_FENCE_TAG_DATA_UNION',
|
|
'union_SDMA_PKT_FENCE_TAG_HEADER_UNION',
|
|
'union_SDMA_PKT_GCR_TAG_HEADER_UNION',
|
|
'union_SDMA_PKT_GCR_TAG_WORD1_UNION',
|
|
'union_SDMA_PKT_GCR_TAG_WORD2_UNION',
|
|
'union_SDMA_PKT_GCR_TAG_WORD3_UNION',
|
|
'union_SDMA_PKT_GCR_TAG_WORD4_UNION',
|
|
'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION',
|
|
'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION',
|
|
'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION',
|
|
'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION',
|
|
'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION',
|
|
'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION',
|
|
'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION',
|
|
'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION',
|
|
'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION',
|
|
'union_SDMA_PKT_TRAP_TAG_HEADER_UNION',
|
|
'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION']
|
|
|